diff --git a/.github/PULL_REQUEST_TEMPLATE b/.github/PULL_REQUEST_TEMPLATE index 2e978b61380862..86abcf019375d4 100644 --- a/.github/PULL_REQUEST_TEMPLATE +++ b/.github/PULL_REQUEST_TEMPLATE @@ -4,7 +4,7 @@ the Gerrit change. **Please ensure you adhere to every item in this list.** -More info can be found at https://github.com/golang/go/wiki/CommitMessage +More info can be found at https://go.dev/wiki/CommitMessage + The PR title is formatted as follows: `net/http: frob the quux before blarfing` + The package name goes before the colon @@ -12,14 +12,14 @@ More info can be found at https://github.com/golang/go/wiki/CommitMessage "This change modifies Go to ___________" + Lowercase verb after the colon + No trailing period - + Keep the title as short as possible. ideally under 76 characters or shorter + + Keep the title as short as possible, ideally 72 characters or shorter + No Markdown -+ The first PR comment (this one) is wrapped at 76 characters, unless it's ++ The first PR comment (this one) is wrapped at around 72 characters, unless it's really needed (ASCII art, table, or long link) + If there is a corresponding issue, add either `Fixes #1234` or `Updates #1234` (the latter if this is not a complete fix) to this comment + If referring to a repo other than `golang/go` you can use the - `owner/repo#issue_number` syntax: `Fixes golang/tools#1234` + `owner/repo#issue_number` syntax: `Fixes golang/vscode-go#1234` + We do not use Signed-off-by lines in Go. Please don't add them. Our Gerrit server & GitHub bots enforce CLA compliance instead. + Delete these instructions once you have read and applied them diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml new file mode 100644 index 00000000000000..0db2e81c5b78d9 --- /dev/null +++ b/.github/workflows/ci.yml @@ -0,0 +1,41 @@ +name: CI + +on: + workflow_dispatch: + push: + branches: + - master + - 'cockroach-*' + pull_request: + branches: + - master + - 'cockroach-*' + +jobs: + build-and-test: + runs-on: ubuntu-24.04 + steps: + - uses: actions/checkout@v5 + + - name: Set up bootstrap Go + uses: actions/setup-go@v6 + with: + go-version: '1.24' + cache: false + + - name: Save GOROOT_BOOTSTRAP + run: echo "GOROOT_BOOTSTRAP=$(go env GOROOT)" >> "$GITHUB_ENV" + + - name: Build toolchain + run: cd src && ./make.bash + + # Run the dist test suite, skipping: + # :race / :race-external — need race detector build (dist test -race) + # testfortran — needs gfortran + # relnote:check — needs doc/next/ fragments (not on release branches) + - name: Run tests + run: | + bin/go tool dist test -k \ + -run '!:(race|race-external)$|testfortran|relnote:check' + env: + GOROOT: ${{ github.workspace }} diff --git a/.gitignore b/.gitignore index c6512e64a4ef39..344b31f7ac1c1d 100644 --- a/.gitignore +++ b/.gitignore @@ -30,6 +30,7 @@ _testmain.go /misc/cgo/testso/main /pkg/ /src/*.*/ +/src/_artifacts/ /src/cmd/cgo/zdefaultcc.go /src/cmd/dist/dist /src/cmd/go/internal/cfg/zdefaultcc.go diff --git a/VERSION b/VERSION new file mode 100644 index 00000000000000..8a3457effbde79 --- /dev/null +++ b/VERSION @@ -0,0 +1,2 @@ +go1.27.2 +time 2026-10-02T20:28:03Z diff --git a/api/except.txt b/api/except.txt index facae98033fe38..7dddd0e3805179 100644 --- a/api/except.txt +++ b/api/except.txt @@ -1,6 +1,13 @@ pkg crypto/tls, type ConnectionState struct, TLSUnique //deprecated pkg debug/elf, const R_PPC64_SECTOFF_LO_DS = 61 pkg encoding/json, method (*RawMessage) MarshalJSON() ([]uint8, error) +pkg encoding/json, method (*RawMessage) UnmarshalJSON([]uint8) error +pkg encoding/json, method (RawMessage) MarshalJSON() ([]uint8, error) +pkg encoding/json, type Marshaler interface { MarshalJSON } +pkg encoding/json, type Marshaler interface, MarshalJSON() ([]uint8, error) +pkg encoding/json, type RawMessage []uint8 +pkg encoding/json, type Unmarshaler interface { UnmarshalJSON } +pkg encoding/json, type Unmarshaler interface, UnmarshalJSON([]uint8) error pkg math, const MaxFloat64 = 1.79769e+308 // 179769313486231570814527423731704356798100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 pkg math, const SmallestNonzeroFloat32 = 1.4013e-45 // 17516230804060213386546619791123951641/12500000000000000000000000000000000000000000000000000000000000000000000000000000000 pkg math, const SmallestNonzeroFloat64 = 4.94066e-324 // 4940656458412465441765687928682213723651/1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -503,6 +510,7 @@ pkg unicode, const Version = "10.0.0" pkg unicode, const Version = "11.0.0" pkg unicode, const Version = "12.0.0" pkg unicode, const Version = "13.0.0" +pkg unicode, const Version = "15.0.0" pkg unicode, const Version = "6.2.0" pkg unicode, const Version = "6.3.0" pkg unicode, const Version = "7.0.0" diff --git a/api/go1.16.txt b/api/go1.16.txt index e12a050939a374..1cae348af9a592 100644 --- a/api/go1.16.txt +++ b/api/go1.16.txt @@ -538,7 +538,6 @@ pkg encoding/json, type UnmarshalFieldError //deprecated pkg go/build, const AllowBinary //deprecated pkg go/doc, type Package struct, Bugs //deprecated pkg go/importer, func For //deprecated -pkg go/importer, func ForCompiler //deprecated pkg go/types, func NewInterface //deprecated pkg go/types, method (*Interface) Embedded //deprecated pkg image, var ZP //deprecated diff --git a/api/go1.25.txt b/api/go1.25.txt index d50d19545f163a..273b3a14de0b67 100644 --- a/api/go1.25.txt +++ b/api/go1.25.txt @@ -109,3 +109,9 @@ pkg testing/synctest, func Wait() #67434 pkg unicode, var CategoryAliases map[string]string #70780 pkg unicode, var Cn *RangeTable #70780 pkg unicode, var LC *RangeTable #70780 +pkg context, func PropagateCancel(Context, func()) bool #0 +pkg runtime, func NumRunnableGoroutines() (int, int) #0 +pkg runtime, func CurrentP() int #0 +pkg runtime, func Yield() int64 #0 +pkg runtime, func GCAssistEnabled() bool #0 +pkg runtime, func SetGCAssistEnabled(bool) bool #0 diff --git a/api/go1.26.txt b/api/go1.26.txt new file mode 100644 index 00000000000000..0706895bbdfef4 --- /dev/null +++ b/api/go1.26.txt @@ -0,0 +1,180 @@ +pkg bytes, method (*Buffer) Peek(int) ([]uint8, error) #73794 +pkg crypto, type Decapsulator interface { Decapsulate, Encapsulator } #75300 +pkg crypto, type Decapsulator interface, Decapsulate([]uint8) ([]uint8, error) #75300 +pkg crypto, type Decapsulator interface, Encapsulator() Encapsulator #75300 +pkg crypto, type Encapsulator interface { Bytes, Encapsulate } #75300 +pkg crypto, type Encapsulator interface, Bytes() []uint8 #75300 +pkg crypto, type Encapsulator interface, Encapsulate() ([]uint8, []uint8) #75300 +pkg crypto/ecdh, type KeyExchanger interface { Curve, ECDH, PublicKey } #75300 +pkg crypto/ecdh, type KeyExchanger interface, Curve() Curve #75300 +pkg crypto/ecdh, type KeyExchanger interface, ECDH(*PublicKey) ([]uint8, error) #75300 +pkg crypto/ecdh, type KeyExchanger interface, PublicKey() *PublicKey #75300 +pkg crypto/ecdsa, type PrivateKey struct, D //deprecated #63963 +pkg crypto/ecdsa, type PublicKey struct, X //deprecated #63963 +pkg crypto/ecdsa, type PublicKey struct, Y //deprecated #63963 +pkg crypto/fips140, func Enforced() bool #74630 +pkg crypto/fips140, func Version() string #75301 +pkg crypto/fips140, func WithoutEnforcement(func()) #74630 +pkg crypto/hpke, func AES128GCM() AEAD #75300 +pkg crypto/hpke, func AES256GCM() AEAD #75300 +pkg crypto/hpke, func ChaCha20Poly1305() AEAD #75300 +pkg crypto/hpke, func DHKEM(ecdh.Curve) KEM #75300 +pkg crypto/hpke, func ExportOnly() AEAD #75300 +pkg crypto/hpke, func HKDFSHA256() KDF #75300 +pkg crypto/hpke, func HKDFSHA384() KDF #75300 +pkg crypto/hpke, func HKDFSHA512() KDF #75300 +pkg crypto/hpke, func MLKEM1024() KEM #75300 +pkg crypto/hpke, func MLKEM1024P384() KEM #75300 +pkg crypto/hpke, func MLKEM768() KEM #75300 +pkg crypto/hpke, func MLKEM768P256() KEM #75300 +pkg crypto/hpke, func MLKEM768X25519() KEM #75300 +pkg crypto/hpke, func NewAEAD(uint16) (AEAD, error) #75300 +pkg crypto/hpke, func NewDHKEMPrivateKey(ecdh.KeyExchanger) (PrivateKey, error) #75300 +pkg crypto/hpke, func NewDHKEMPublicKey(*ecdh.PublicKey) (PublicKey, error) #75300 +pkg crypto/hpke, func NewHybridPrivateKey(crypto.Decapsulator, ecdh.KeyExchanger) (PrivateKey, error) #75300 +pkg crypto/hpke, func NewHybridPublicKey(crypto.Encapsulator, *ecdh.PublicKey) (PublicKey, error) #75300 +pkg crypto/hpke, func NewKDF(uint16) (KDF, error) #75300 +pkg crypto/hpke, func NewKEM(uint16) (KEM, error) #75300 +pkg crypto/hpke, func NewMLKEMPrivateKey(crypto.Decapsulator) (PrivateKey, error) #75300 +pkg crypto/hpke, func NewMLKEMPublicKey(crypto.Encapsulator) (PublicKey, error) #75300 +pkg crypto/hpke, func NewRecipient([]uint8, PrivateKey, KDF, AEAD, []uint8) (*Recipient, error) #75300 +pkg crypto/hpke, func NewSender(PublicKey, KDF, AEAD, []uint8) ([]uint8, *Sender, error) #75300 +pkg crypto/hpke, func Open(PrivateKey, KDF, AEAD, []uint8, []uint8) ([]uint8, error) #75300 +pkg crypto/hpke, func SHAKE128() KDF #75300 +pkg crypto/hpke, func SHAKE256() KDF #75300 +pkg crypto/hpke, func Seal(PublicKey, KDF, AEAD, []uint8, []uint8) ([]uint8, error) #75300 +pkg crypto/hpke, method (*Recipient) Export(string, int) ([]uint8, error) #75300 +pkg crypto/hpke, method (*Recipient) Open([]uint8, []uint8) ([]uint8, error) #75300 +pkg crypto/hpke, method (*Sender) Export(string, int) ([]uint8, error) #75300 +pkg crypto/hpke, method (*Sender) Seal([]uint8, []uint8) ([]uint8, error) #75300 +pkg crypto/hpke, type AEAD interface, ID() uint16 #75300 +pkg crypto/hpke, type AEAD interface, unexported methods #75300 +pkg crypto/hpke, type KDF interface, ID() uint16 #75300 +pkg crypto/hpke, type KDF interface, unexported methods #75300 +pkg crypto/hpke, type KEM interface, DeriveKeyPair([]uint8) (PrivateKey, error) #75300 +pkg crypto/hpke, type KEM interface, GenerateKey() (PrivateKey, error) #75300 +pkg crypto/hpke, type KEM interface, ID() uint16 #75300 +pkg crypto/hpke, type KEM interface, NewPrivateKey([]uint8) (PrivateKey, error) #75300 +pkg crypto/hpke, type KEM interface, NewPublicKey([]uint8) (PublicKey, error) #75300 +pkg crypto/hpke, type KEM interface, unexported methods #75300 +pkg crypto/hpke, type PrivateKey interface, Bytes() ([]uint8, error) #75300 +pkg crypto/hpke, type PrivateKey interface, KEM() KEM #75300 +pkg crypto/hpke, type PrivateKey interface, PublicKey() PublicKey #75300 +pkg crypto/hpke, type PrivateKey interface, unexported methods #75300 +pkg crypto/hpke, type PublicKey interface, Bytes() []uint8 #75300 +pkg crypto/hpke, type PublicKey interface, KEM() KEM #75300 +pkg crypto/hpke, type PublicKey interface, unexported methods #75300 +pkg crypto/hpke, type Recipient struct #75300 +pkg crypto/hpke, type Sender struct #75300 +pkg crypto/mlkem, method (*DecapsulationKey1024) Encapsulator() crypto.Encapsulator #75300 +pkg crypto/mlkem, method (*DecapsulationKey768) Encapsulator() crypto.Encapsulator #75300 +pkg crypto/mlkem/mlkemtest, func Encapsulate1024(*mlkem.EncapsulationKey1024, []uint8) ([]uint8, []uint8, error) #73627 +pkg crypto/mlkem/mlkemtest, func Encapsulate768(*mlkem.EncapsulationKey768, []uint8) ([]uint8, []uint8, error) #73627 +pkg crypto/rsa, func DecryptPKCS1v15 //deprecated #75302 +pkg crypto/rsa, func DecryptPKCS1v15SessionKey //deprecated #75302 +pkg crypto/rsa, func EncryptOAEPWithOptions(io.Reader, *PublicKey, []uint8, *OAEPOptions) ([]uint8, error) #65716 +pkg crypto/rsa, func EncryptPKCS1v15 //deprecated #75302 +pkg crypto/rsa, type PKCS1v15DecryptOptions //deprecated #75302 +pkg crypto/tls, const QUICErrorEvent = 10 #75108 +pkg crypto/tls, const QUICErrorEvent QUICEventKind #75108 +pkg crypto/tls, const SecP256r1MLKEM768 = 4587 #71206 +pkg crypto/tls, const SecP256r1MLKEM768 CurveID #71206 +pkg crypto/tls, const SecP384r1MLKEM1024 = 4589 #71206 +pkg crypto/tls, const SecP384r1MLKEM1024 CurveID #71206 +pkg crypto/tls, type ClientHelloInfo struct, HelloRetryRequest bool #74425 +pkg crypto/tls, type ConnectionState struct, HelloRetryRequest bool #74425 +pkg crypto/tls, type QUICEvent struct, Err error #75108 +pkg crypto/x509, func OIDFromASN1OID(asn1.ObjectIdentifier) (OID, error) #75325 +pkg crypto/x509, method (ExtKeyUsage) OID() OID #75325 +pkg crypto/x509, method (ExtKeyUsage) String() string #56866 +pkg crypto/x509, method (KeyUsage) String() string #56866 +pkg debug/elf, const R_LARCH_CALL36 = 110 #75562 +pkg debug/elf, const R_LARCH_CALL36 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC32 = 13 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC32 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC64 = 14 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC64 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC64_HI12 = 118 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC64_HI12 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC64_LO20 = 117 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC64_LO20 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC64_PC_HI12 = 114 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC64_PC_HI12 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC64_PC_LO20 = 113 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC64_PC_LO20 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_CALL = 120 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_CALL R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_HI20 = 115 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_HI20 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_LD = 119 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_LD R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_LO12 = 116 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_LO12 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_PCREL20_S2 = 126 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_PCREL20_S2 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_PC_HI20 = 111 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_PC_HI20 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_PC_LO12 = 112 #75562 +pkg debug/elf, const R_LARCH_TLS_DESC_PC_LO12 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_GD_PCREL20_S2 = 125 #75562 +pkg debug/elf, const R_LARCH_TLS_GD_PCREL20_S2 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_LD_PCREL20_S2 = 124 #75562 +pkg debug/elf, const R_LARCH_TLS_LD_PCREL20_S2 R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_LE_ADD_R = 122 #75562 +pkg debug/elf, const R_LARCH_TLS_LE_ADD_R R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_LE_HI20_R = 121 #75562 +pkg debug/elf, const R_LARCH_TLS_LE_HI20_R R_LARCH #75562 +pkg debug/elf, const R_LARCH_TLS_LE_LO12_R = 123 #75562 +pkg debug/elf, const R_LARCH_TLS_LE_LO12_R R_LARCH #75562 +pkg errors, func AsType[$0 error](error) ($0, bool) #51945 +pkg go/ast, func ParseDirective(token.Pos, string) (Directive, bool) #68021 +pkg go/ast, method (*Directive) End() token.Pos #68021 +pkg go/ast, method (*Directive) ParseArgs() ([]DirectiveArg, error) #68021 +pkg go/ast, method (*Directive) Pos() token.Pos #68021 +pkg go/ast, type BasicLit struct, ValueEnd token.Pos #76031 +pkg go/ast, type Directive struct #68021 +pkg go/ast, type Directive struct, Args string #68021 +pkg go/ast, type Directive struct, ArgsPos token.Pos #68021 +pkg go/ast, type Directive struct, Name string #68021 +pkg go/ast, type Directive struct, Slash token.Pos #68021 +pkg go/ast, type Directive struct, Tool string #68021 +pkg go/ast, type DirectiveArg struct #68021 +pkg go/ast, type DirectiveArg struct, Arg string #68021 +pkg go/ast, type DirectiveArg struct, Pos token.Pos #68021 +pkg go/token, method (*File) End() Pos #75849 +pkg log/slog, func NewMultiHandler(...Handler) *MultiHandler #65954 +pkg log/slog, method (*MultiHandler) Enabled(context.Context, Level) bool #65954 +pkg log/slog, method (*MultiHandler) Handle(context.Context, Record) error #65954 +pkg log/slog, method (*MultiHandler) WithAttrs([]Attr) Handler #65954 +pkg log/slog, method (*MultiHandler) WithGroup(string) Handler #65954 +pkg log/slog, type MultiHandler struct #65954 +pkg net, method (*Dialer) DialIP(context.Context, string, netip.Addr, netip.Addr) (*IPConn, error) #49097 +pkg net, method (*Dialer) DialTCP(context.Context, string, netip.AddrPort, netip.AddrPort) (*TCPConn, error) #49097 +pkg net, method (*Dialer) DialUDP(context.Context, string, netip.AddrPort, netip.AddrPort) (*UDPConn, error) #49097 +pkg net, method (*Dialer) DialUnix(context.Context, string, *UnixAddr, *UnixAddr) (*UnixConn, error) #49097 +pkg net/http, method (*ClientConn) Available() int #75772 +pkg net/http, method (*ClientConn) Close() error #75772 +pkg net/http, method (*ClientConn) Err() error #75772 +pkg net/http, method (*ClientConn) InFlight() int #75772 +pkg net/http, method (*ClientConn) Release() #75772 +pkg net/http, method (*ClientConn) Reserve() error #75772 +pkg net/http, method (*ClientConn) RoundTrip(*Request) (*Response, error) #75772 +pkg net/http, method (*ClientConn) SetStateHook(func(*ClientConn)) #75772 +pkg net/http, method (*Transport) NewClientConn(context.Context, string, string) (*ClientConn, error) #75772 +pkg net/http, type ClientConn struct #75772 +pkg net/http, type HTTP2Config struct, StrictMaxConcurrentRequests bool #67813 +pkg net/http/httputil, type ReverseProxy struct, Director //deprecated #73161 +pkg net/netip, method (Prefix) Compare(Prefix) int #61642 +pkg os, method (*Process) WithHandle(func(uintptr)) error #70352 +pkg os, var ErrNoHandle error #70352 +pkg reflect, method (Value) Fields() iter.Seq2[StructField, Value] #66631 +pkg reflect, method (Value) Methods() iter.Seq2[Method, Value] #66631 +pkg reflect, type Type interface, Fields() iter.Seq[StructField] #66631 +pkg reflect, type Type interface, Ins() iter.Seq[Type] #66631 +pkg reflect, type Type interface, Methods() iter.Seq[Method] #66631 +pkg reflect, type Type interface, Outs() iter.Seq[Type] #66631 +pkg testing, method (*B) ArtifactDir() string #71287 +pkg testing, method (*F) ArtifactDir() string #71287 +pkg testing, method (*T) ArtifactDir() string #71287 +pkg testing, type TB interface, ArtifactDir() string #71287 +pkg testing/cryptotest, func SetGlobalRandom(*testing.T, uint64) #70942 diff --git a/api/go1.27.txt b/api/go1.27.txt new file mode 100644 index 00000000000000..04b797d9f9a7c1 --- /dev/null +++ b/api/go1.27.txt @@ -0,0 +1,317 @@ +pkg bytes, func CutLast([]uint8, []uint8) ([]uint8, []uint8, bool) #71151 +pkg crypto, const MLDSAMu = 20 #77626 +pkg crypto, const MLDSAMu Hash #77626 +pkg crypto/mldsa, const MLDSA44PublicKeySize = 1312 #77626 +pkg crypto/mldsa, const MLDSA44PublicKeySize ideal-int #77626 +pkg crypto/mldsa, const MLDSA44SignatureSize = 2420 #77626 +pkg crypto/mldsa, const MLDSA44SignatureSize ideal-int #77626 +pkg crypto/mldsa, const MLDSA65PublicKeySize = 1952 #77626 +pkg crypto/mldsa, const MLDSA65PublicKeySize ideal-int #77626 +pkg crypto/mldsa, const MLDSA65SignatureSize = 3309 #77626 +pkg crypto/mldsa, const MLDSA65SignatureSize ideal-int #77626 +pkg crypto/mldsa, const MLDSA87PublicKeySize = 2592 #77626 +pkg crypto/mldsa, const MLDSA87PublicKeySize ideal-int #77626 +pkg crypto/mldsa, const MLDSA87SignatureSize = 4627 #77626 +pkg crypto/mldsa, const MLDSA87SignatureSize ideal-int #77626 +pkg crypto/mldsa, const PrivateKeySize = 32 #77626 +pkg crypto/mldsa, const PrivateKeySize ideal-int #77626 +pkg crypto/mldsa, func GenerateKey(Parameters) (*PrivateKey, error) #77626 +pkg crypto/mldsa, func MLDSA44() Parameters #77626 +pkg crypto/mldsa, func MLDSA65() Parameters #77626 +pkg crypto/mldsa, func MLDSA87() Parameters #77626 +pkg crypto/mldsa, func NewPrivateKey(Parameters, []uint8) (*PrivateKey, error) #77626 +pkg crypto/mldsa, func NewPublicKey(Parameters, []uint8) (*PublicKey, error) #77626 +pkg crypto/mldsa, func Verify(*PublicKey, []uint8, []uint8, *Options) error #77626 +pkg crypto/mldsa, method (*Options) HashFunc() crypto.Hash #77626 +pkg crypto/mldsa, method (*PrivateKey) Bytes() []uint8 #77626 +pkg crypto/mldsa, method (*PrivateKey) Equal(crypto.PrivateKey) bool #77626 +pkg crypto/mldsa, method (*PrivateKey) Public() crypto.PublicKey #77626 +pkg crypto/mldsa, method (*PrivateKey) PublicKey() *PublicKey #77626 +pkg crypto/mldsa, method (*PrivateKey) Sign(io.Reader, []uint8, crypto.SignerOpts) ([]uint8, error) #77626 +pkg crypto/mldsa, method (*PrivateKey) SignDeterministic([]uint8, crypto.SignerOpts) ([]uint8, error) #77626 +pkg crypto/mldsa, method (*PublicKey) Bytes() []uint8 #77626 +pkg crypto/mldsa, method (*PublicKey) Equal(crypto.PublicKey) bool #77626 +pkg crypto/mldsa, method (*PublicKey) Parameters() Parameters #77626 +pkg crypto/mldsa, method (Parameters) PublicKeySize() int #77626 +pkg crypto/mldsa, method (Parameters) SignatureSize() int #77626 +pkg crypto/mldsa, method (Parameters) String() string #77626 +pkg crypto/mldsa, type Options struct #77626 +pkg crypto/mldsa, type Options struct, Context string #77626 +pkg crypto/mldsa, type Parameters struct #77626 +pkg crypto/mldsa, type PrivateKey struct #77626 +pkg crypto/mldsa, type PublicKey struct #77626 +pkg crypto/tls, const MLDSA44 = 2308 #78888 +pkg crypto/tls, const MLDSA44 SignatureScheme #78888 +pkg crypto/tls, const MLDSA65 = 2309 #78888 +pkg crypto/tls, const MLDSA65 SignatureScheme #78888 +pkg crypto/tls, const MLDSA87 = 2310 #78888 +pkg crypto/tls, const MLDSA87 SignatureScheme #78888 +pkg crypto/tls, const MLKEM1024 = 514 #78543 +pkg crypto/tls, const MLKEM1024 CurveID #78543 +pkg crypto/tls, type Config struct, Rand //deprecated #79367 +pkg crypto/tls, type ConnectionState struct, LocalCertificate [][]uint8 #24673 +pkg crypto/tls, type QUICConfig struct, ClientHelloInfoConn net.Conn #77363 +pkg crypto/x509, const MLDSA = 5 #78888 +pkg crypto/x509, const MLDSA PublicKeyAlgorithm #78888 +pkg crypto/x509, const MLDSA44 = 17 #78888 +pkg crypto/x509, const MLDSA44 SignatureAlgorithm #78888 +pkg crypto/x509, const MLDSA65 = 18 #78888 +pkg crypto/x509, const MLDSA65 SignatureAlgorithm #78888 +pkg crypto/x509, const MLDSA87 = 19 #78888 +pkg crypto/x509, const MLDSA87 SignatureAlgorithm #78888 +pkg crypto/x509, type Certificate struct, RawSignatureAlgorithm []uint8 #76133 +pkg crypto/x509, type CertificateRequest struct, RawSignatureAlgorithm []uint8 #76133 +pkg crypto/x509, type RevocationList struct, RawSignatureAlgorithm []uint8 #76133 +pkg database/sql, func ConvertAssign(driver.ScanContext, interface{}, driver.Value) error #67546 +pkg database/sql/driver, type RowsColumnScanner interface { Close, Columns, Next, NextRow, ScanColumn } #67546 +pkg database/sql/driver, type RowsColumnScanner interface, Close() error #67546 +pkg database/sql/driver, type RowsColumnScanner interface, Columns() []string #67546 +pkg database/sql/driver, type RowsColumnScanner interface, Next([]Value) error #67546 +pkg database/sql/driver, type RowsColumnScanner interface, NextRow() error #67546 +pkg database/sql/driver, type RowsColumnScanner interface, ScanColumn(ScanContext, int, interface{}) error #67546 +pkg database/sql/driver, type ScanContext struct #67546 +pkg encoding/json, func CallMethodsWithLegacySemantics(bool) jsonopts.Options #71497 +pkg encoding/json, func DefaultOptionsV1() jsonopts.Options #71497 +pkg encoding/json, func FormatByteArrayAsArray(bool) jsonopts.Options #71497 +pkg encoding/json, func FormatBytesWithLegacySemantics(bool) jsonopts.Options #71497 +pkg encoding/json, func FormatDurationAsNano(bool) jsonopts.Options #71497 +pkg encoding/json, func MatchCaseSensitiveDelimiter(bool) jsonopts.Options #71497 +pkg encoding/json, func MergeWithLegacySemantics(bool) jsonopts.Options #71497 +pkg encoding/json, func OmitEmptyWithLegacySemantics(bool) jsonopts.Options #71497 +pkg encoding/json, func ParseBytesWithLooseRFC4648(bool) jsonopts.Options #71497 +pkg encoding/json, func ParseTimeWithLooseRFC3339(bool) jsonopts.Options #71497 +pkg encoding/json, func ReportErrorsWithLegacySemantics(bool) jsonopts.Options #71497 +pkg encoding/json, func StringifyWithLegacySemantics(bool) jsonopts.Options #71497 +pkg encoding/json, func UnmarshalArrayFromAnyLength(bool) jsonopts.Options #71497 +pkg encoding/json, method (*Number) UnmarshalJSONFrom(*jsontext.Decoder) error #71497 +pkg encoding/json, method (*UnmarshalTypeError) Unwrap() error #71497 +pkg encoding/json, method (Number) MarshalJSONTo(*jsontext.Encoder) error #71497 +pkg encoding/json, type Marshaler = json.Marshaler #71497 +pkg encoding/json, type Options = jsonopts.Options #71497 +pkg encoding/json, type RawMessage = jsontext.Value #71497 +pkg encoding/json, type UnmarshalTypeError struct, Err error #71497 +pkg encoding/json, type Unmarshaler = json.Unmarshaler #71497 +pkg encoding/json/jsontext, const KindBeginArray = 91 #71497 +pkg encoding/json/jsontext, const KindBeginArray Kind #71497 +pkg encoding/json/jsontext, const KindBeginObject = 123 #71497 +pkg encoding/json/jsontext, const KindBeginObject Kind #71497 +pkg encoding/json/jsontext, const KindEndArray = 93 #71497 +pkg encoding/json/jsontext, const KindEndArray Kind #71497 +pkg encoding/json/jsontext, const KindEndObject = 125 #71497 +pkg encoding/json/jsontext, const KindEndObject Kind #71497 +pkg encoding/json/jsontext, const KindFalse = 102 #71497 +pkg encoding/json/jsontext, const KindFalse Kind #71497 +pkg encoding/json/jsontext, const KindInvalid = 0 #71497 +pkg encoding/json/jsontext, const KindInvalid Kind #71497 +pkg encoding/json/jsontext, const KindNull = 110 #71497 +pkg encoding/json/jsontext, const KindNull Kind #71497 +pkg encoding/json/jsontext, const KindNumber = 48 #71497 +pkg encoding/json/jsontext, const KindNumber Kind #71497 +pkg encoding/json/jsontext, const KindString = 34 #71497 +pkg encoding/json/jsontext, const KindString Kind #71497 +pkg encoding/json/jsontext, const KindTrue = 116 #71497 +pkg encoding/json/jsontext, const KindTrue Kind #71497 +pkg encoding/json/jsontext, func AllowDuplicateNames(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func AllowInvalidUTF8(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func AppendFloat([]uint8, float64, int) []uint8 #71497 +pkg encoding/json/jsontext, func AppendFormat[$0 interface{ ~[]uint8 | ~string }]([]uint8, $0, ...jsonopts.Options) ([]uint8, error) #71497 +pkg encoding/json/jsontext, func AppendQuote[$0 interface{ ~[]uint8 | ~string }]([]uint8, $0) ([]uint8, error) #71497 +pkg encoding/json/jsontext, func AppendUnquote[$0 interface{ ~[]uint8 | ~string }]([]uint8, $0) ([]uint8, error) #71497 +pkg encoding/json/jsontext, func Bool(bool) Token #71497 +pkg encoding/json/jsontext, func CanonicalizeRawFloats(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func CanonicalizeRawInts(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func EscapeForHTML(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func EscapeForJS(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func Float(float64) Token #71497 +pkg encoding/json/jsontext, func Float32(float32) Token #71497 +pkg encoding/json/jsontext, func Int(int64) Token #71497 +pkg encoding/json/jsontext, func Multiline(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func NewDecoder(io.Reader, ...jsonopts.Options) *Decoder #71497 +pkg encoding/json/jsontext, func NewEncoder(io.Writer, ...jsonopts.Options) *Encoder #71497 +pkg encoding/json/jsontext, func PreserveRawStrings(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func ReorderRawObjects(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func SpaceAfterColon(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func SpaceAfterComma(bool) jsonopts.Options #71497 +pkg encoding/json/jsontext, func String(string) Token #71497 +pkg encoding/json/jsontext, func Uint(uint64) Token #71497 +pkg encoding/json/jsontext, func WithIndent(string) jsonopts.Options #71497 +pkg encoding/json/jsontext, func WithIndentPrefix(string) jsonopts.Options #71497 +pkg encoding/json/jsontext, method (*Decoder) InputOffset() int64 #71497 +pkg encoding/json/jsontext, method (*Decoder) Options() jsonopts.Options #71497 +pkg encoding/json/jsontext, method (*Decoder) PeekKind() Kind #71497 +pkg encoding/json/jsontext, method (*Decoder) ReadToken() (Token, error) #71497 +pkg encoding/json/jsontext, method (*Decoder) ReadValue() (Value, error) #71497 +pkg encoding/json/jsontext, method (*Decoder) Reset(io.Reader, ...jsonopts.Options) #71497 +pkg encoding/json/jsontext, method (*Decoder) SkipValue() error #71497 +pkg encoding/json/jsontext, method (*Decoder) StackDepth() int #71497 +pkg encoding/json/jsontext, method (*Decoder) StackIndex(int) (Kind, int64) #71497 +pkg encoding/json/jsontext, method (*Decoder) StackPointer() Pointer #71497 +pkg encoding/json/jsontext, method (*Decoder) UnreadBuffer() []uint8 #71497 +pkg encoding/json/jsontext, method (*Encoder) AvailableBuffer() []uint8 #71497 +pkg encoding/json/jsontext, method (*Encoder) Options() jsonopts.Options #71497 +pkg encoding/json/jsontext, method (*Encoder) OutputOffset() int64 #71497 +pkg encoding/json/jsontext, method (*Encoder) Reset(io.Writer, ...jsonopts.Options) #71497 +pkg encoding/json/jsontext, method (*Encoder) StackDepth() int #71497 +pkg encoding/json/jsontext, method (*Encoder) StackIndex(int) (Kind, int64) #71497 +pkg encoding/json/jsontext, method (*Encoder) StackPointer() Pointer #71497 +pkg encoding/json/jsontext, method (*Encoder) WriteToken(Token) error #71497 +pkg encoding/json/jsontext, method (*Encoder) WriteValue(Value) error #71497 +pkg encoding/json/jsontext, method (*SyntacticError) Error() string #71497 +pkg encoding/json/jsontext, method (*SyntacticError) Unwrap() error #71497 +pkg encoding/json/jsontext, method (*Value) Canonicalize(...jsonopts.Options) error #71497 +pkg encoding/json/jsontext, method (*Value) Compact(...jsonopts.Options) error #71497 +pkg encoding/json/jsontext, method (*Value) Format(...jsonopts.Options) error #71497 +pkg encoding/json/jsontext, method (*Value) Indent(...jsonopts.Options) error #71497 +pkg encoding/json/jsontext, method (*Value) UnmarshalJSON([]uint8) error #71497 +pkg encoding/json/jsontext, method (Kind) String() string #71497 +pkg encoding/json/jsontext, method (Pointer) AppendToken(string) Pointer #71497 +pkg encoding/json/jsontext, method (Pointer) Contains(Pointer) bool #71497 +pkg encoding/json/jsontext, method (Pointer) IsValid() bool #71497 +pkg encoding/json/jsontext, method (Pointer) LastToken() string #71497 +pkg encoding/json/jsontext, method (Pointer) Parent() Pointer #71497 +pkg encoding/json/jsontext, method (Pointer) Tokens() iter.Seq[string] #71497 +pkg encoding/json/jsontext, method (Token) Bool() bool #71497 +pkg encoding/json/jsontext, method (Token) Clone() Token #71497 +pkg encoding/json/jsontext, method (Token) Float() (float64, error) #71497 +pkg encoding/json/jsontext, method (Token) Float32() (float32, error) #71497 +pkg encoding/json/jsontext, method (Token) Int() (int64, error) #71497 +pkg encoding/json/jsontext, method (Token) Kind() Kind #71497 +pkg encoding/json/jsontext, method (Token) String() string #71497 +pkg encoding/json/jsontext, method (Token) Uint() (uint64, error) #71497 +pkg encoding/json/jsontext, method (Value) Clone() Value #71497 +pkg encoding/json/jsontext, method (Value) IsValid(...jsonopts.Options) bool #71497 +pkg encoding/json/jsontext, method (Value) Kind() Kind #71497 +pkg encoding/json/jsontext, method (Value) MarshalJSON() ([]uint8, error) #71497 +pkg encoding/json/jsontext, method (Value) String() string #71497 +pkg encoding/json/jsontext, type Decoder struct #71497 +pkg encoding/json/jsontext, type Encoder struct #71497 +pkg encoding/json/jsontext, type Kind uint8 #71497 +pkg encoding/json/jsontext, type Options = jsonopts.Options #71497 +pkg encoding/json/jsontext, type Pointer string #71497 +pkg encoding/json/jsontext, type SyntacticError struct #71497 +pkg encoding/json/jsontext, type SyntacticError struct, ByteOffset int64 #71497 +pkg encoding/json/jsontext, type SyntacticError struct, Err error #71497 +pkg encoding/json/jsontext, type SyntacticError struct, JSONPointer Pointer #71497 +pkg encoding/json/jsontext, type Token struct #71497 +pkg encoding/json/jsontext, type Value []uint8 #71497 +pkg encoding/json/jsontext, var BeginArray Token #71497 +pkg encoding/json/jsontext, var BeginObject Token #71497 +pkg encoding/json/jsontext, var EndArray Token #71497 +pkg encoding/json/jsontext, var EndObject Token #71497 +pkg encoding/json/jsontext, var ErrDuplicateName error #71497 +pkg encoding/json/jsontext, var ErrNonStringName error #71497 +pkg encoding/json/jsontext, var False Token #71497 +pkg encoding/json/jsontext, var Internal exporter #71497 +pkg encoding/json/jsontext, var Null Token #71497 +pkg encoding/json/jsontext, var True Token #71497 +pkg encoding/json/v2, func DefaultOptionsV2() jsonopts.Options #71497 +pkg encoding/json/v2, func Deterministic(bool) jsonopts.Options #71497 +pkg encoding/json/v2, func FormatNilMapAsNull(bool) jsonopts.Options #71497 +pkg encoding/json/v2, func FormatNilSliceAsNull(bool) jsonopts.Options #71497 +pkg encoding/json/v2, func GetOption[$0 interface{}](jsonopts.Options, func($0) jsonopts.Options) ($0, bool) #71497 +pkg encoding/json/v2, func JoinMarshalers(...*typedArshalers[jsontext.Encoder]) *typedArshalers[jsontext.Encoder] #71497 +pkg encoding/json/v2, func JoinOptions(...jsonopts.Options) jsonopts.Options #71497 +pkg encoding/json/v2, func JoinUnmarshalers(...*typedArshalers[jsontext.Decoder]) *typedArshalers[jsontext.Decoder] #71497 +pkg encoding/json/v2, func Marshal(interface{}, ...jsonopts.Options) ([]uint8, error) #71497 +pkg encoding/json/v2, func MarshalEncode(*jsontext.Encoder, interface{}, ...jsonopts.Options) error #71497 +pkg encoding/json/v2, func MarshalFunc[$0 interface{}](func($0) ([]uint8, error)) *typedArshalers[jsontext.Encoder] #71497 +pkg encoding/json/v2, func MarshalToFunc[$0 interface{}](func(*jsontext.Encoder, $0) error) *typedArshalers[jsontext.Encoder] #71497 +pkg encoding/json/v2, func MarshalWrite(io.Writer, interface{}, ...jsonopts.Options) error #71497 +pkg encoding/json/v2, func MatchCaseInsensitiveNames(bool) jsonopts.Options #71497 +pkg encoding/json/v2, func OmitZeroStructFields(bool) jsonopts.Options #71497 +pkg encoding/json/v2, func RejectUnknownMembers(bool) jsonopts.Options #71497 +pkg encoding/json/v2, func StringifyNumbers(bool) jsonopts.Options #71497 +pkg encoding/json/v2, func Unmarshal([]uint8, interface{}, ...jsonopts.Options) error #71497 +pkg encoding/json/v2, func UnmarshalDecode(*jsontext.Decoder, interface{}, ...jsonopts.Options) error #71497 +pkg encoding/json/v2, func UnmarshalFromFunc[$0 interface{}](func(*jsontext.Decoder, $0) error) *typedArshalers[jsontext.Decoder] #71497 +pkg encoding/json/v2, func UnmarshalFunc[$0 interface{}](func([]uint8, $0) error) *typedArshalers[jsontext.Decoder] #71497 +pkg encoding/json/v2, func UnmarshalRead(io.Reader, interface{}, ...jsonopts.Options) error #71497 +pkg encoding/json/v2, func WithMarshalers(*typedArshalers[jsontext.Encoder]) jsonopts.Options #71497 +pkg encoding/json/v2, func WithUnmarshalers(*typedArshalers[jsontext.Decoder]) jsonopts.Options #71497 +pkg encoding/json/v2, method (*SemanticError) Error() string #71497 +pkg encoding/json/v2, method (*SemanticError) Unwrap() error #71497 +pkg encoding/json/v2, type Marshaler interface { MarshalJSON } #71497 +pkg encoding/json/v2, type Marshaler interface, MarshalJSON() ([]uint8, error) #71497 +pkg encoding/json/v2, type MarshalerTo interface { MarshalJSONTo } #71497 +pkg encoding/json/v2, type MarshalerTo interface, MarshalJSONTo(*jsontext.Encoder) error #71497 +pkg encoding/json/v2, type Marshalers = typedArshalers[jsontext.Encoder] #71497 +pkg encoding/json/v2, type Options = jsonopts.Options #71497 +pkg encoding/json/v2, type SemanticError struct #71497 +pkg encoding/json/v2, type SemanticError struct, ByteOffset int64 #71497 +pkg encoding/json/v2, type SemanticError struct, Err error #71497 +pkg encoding/json/v2, type SemanticError struct, GoType reflect.Type #71497 +pkg encoding/json/v2, type SemanticError struct, JSONKind jsontext.Kind #71497 +pkg encoding/json/v2, type SemanticError struct, JSONPointer jsontext.Pointer #71497 +pkg encoding/json/v2, type SemanticError struct, JSONValue jsontext.Value #71497 +pkg encoding/json/v2, type Unmarshaler interface { UnmarshalJSON } #71497 +pkg encoding/json/v2, type Unmarshaler interface, UnmarshalJSON([]uint8) error #71497 +pkg encoding/json/v2, type UnmarshalerFrom interface { UnmarshalJSONFrom } #71497 +pkg encoding/json/v2, type UnmarshalerFrom interface, UnmarshalJSONFrom(*jsontext.Decoder) error #71497 +pkg encoding/json/v2, type Unmarshalers = typedArshalers[jsontext.Decoder] #71497 +pkg encoding/json/v2, var ErrUnknownName error #71497 +pkg go/constant, func StringLen(Value) int64 #79042 +pkg go/scanner, method (*Scanner) End() token.Pos #74958 +pkg go/token, method (*File) String() string #76285 +pkg go/types, method (*TypeList) String() string #79287 +pkg go/types, method (*TypeParamList) String() string #79287 +pkg go/types, method (Hasher) Equal(Type, Type) bool #69420 +pkg go/types, method (Hasher) Hash(*maphash.Hash, Type) #69420 +pkg go/types, method (HasherIgnoreTags) Equal(Type, Type) bool #69420 +pkg go/types, method (HasherIgnoreTags) Hash(*maphash.Hash, Type) #69420 +pkg go/types, method (Instance) String() string #79287 +pkg go/types, type Hasher struct #69420 +pkg go/types, type HasherIgnoreTags struct #69420 +pkg hash/maphash, method (ComparableHasher[$0]) Equal($0, $0) bool #70471 +pkg hash/maphash, method (ComparableHasher[$0]) Hash(*Hash, $0) #70471 +pkg hash/maphash, type ComparableHasher[$0 comparable] struct #70471 +pkg hash/maphash, type Hasher[$0 interface{}] interface { Equal, Hash } #70471 +pkg hash/maphash, type Hasher[$0 interface{}] interface, Equal($0, $0) bool #70471 +pkg hash/maphash, type Hasher[$0 interface{}] interface, Hash(*Hash, $0) #70471 +pkg math/big, const Ceil = 5 #76821 +pkg math/big, const Ceil RoundingMode #76821 +pkg math/big, const Floor = 4 #76821 +pkg math/big, const Floor RoundingMode #76821 +pkg math/big, const Round = 0 #76821 +pkg math/big, const Round RoundingMode #76821 +pkg math/big, const Trunc = 2 #76821 +pkg math/big, const Trunc RoundingMode #76821 +pkg math/big, method (*Int) Divide(*Int, *Int, *Int, RoundingMode) (*Int, *Int) #76821 +pkg math/rand/v2, method (*Rand) N[$0 intType]($0) $0 #77853 +pkg net/http, type Server struct, DisableClientPriority bool #75500 +pkg net/http, const DefaultMaxHeaderValueCount = 500 #79936 +pkg net/http, const DefaultMaxHeaderValueCount ideal-int #79936 +pkg net/http, type Server struct, MaxHeaderValueCount int #79936 +pkg net/http/httptest, func NewTestServer(testing.TB, http.Handler) *Server #76608 +pkg net/url, method (*URL) Clone() *URL #73450 +pkg net/url, method (Values) Clone() Values #73450 +pkg strings, func CutLast(string, string) (string, string, bool) #71151 +pkg testing/synctest, func Sleep(time.Duration) #77169 +pkg unicode, const Version = "17.0.0" #77266 +pkg unicode, var Beria_Erfe *RangeTable #77266 +pkg unicode, var Garay *RangeTable #77266 +pkg unicode, var Gurung_Khema *RangeTable #77266 +pkg unicode, var IDS_Unary_Operator *RangeTable #77266 +pkg unicode, var ID_Compat_Math_Continue *RangeTable #77266 +pkg unicode, var ID_Compat_Math_Start *RangeTable #77266 +pkg unicode, var Kirat_Rai *RangeTable #77266 +pkg unicode, var Modifier_Combining_Mark *RangeTable #77266 +pkg unicode, var Ol_Onal *RangeTable #77266 +pkg unicode, var Sidetic *RangeTable #77266 +pkg unicode, var Sunuwar *RangeTable #77266 +pkg unicode, var Tai_Yo *RangeTable #77266 +pkg unicode, var Todhri *RangeTable #77266 +pkg unicode, var Tolong_Siki *RangeTable #77266 +pkg unicode, var Tulu_Tigalari *RangeTable #77266 +pkg uuid, func Max() UUID #62026 +pkg uuid, func MustParse(string) UUID #62026 +pkg uuid, func New() UUID #62026 +pkg uuid, func NewV4() UUID #62026 +pkg uuid, func NewV7() UUID #62026 +pkg uuid, func Nil() UUID #62026 +pkg uuid, func Parse(string) (UUID, error) #62026 +pkg uuid, method (*UUID) UnmarshalText([]uint8) error #62026 +pkg uuid, method (UUID) AppendText([]uint8) ([]uint8, error) #62026 +pkg uuid, method (UUID) Compare(UUID) int #62026 +pkg uuid, method (UUID) MarshalText() ([]uint8, error) #62026 +pkg uuid, method (UUID) String() string #62026 +pkg uuid, type UUID [16]uint8 #62026 diff --git a/api/go1.txt b/api/go1.txt index 5e3dea5a372525..54e4a2833e048a 100644 --- a/api/go1.txt +++ b/api/go1.txt @@ -30869,3 +30869,6 @@ pkg unicode/utf8, func RuneLen(int32) int pkg unicode/utf8, func RuneStart(uint8) bool pkg unicode/utf8, func Valid([]uint8) bool pkg unicode/utf8, func ValidString(string) bool +pkg context, func PropagateCancel(Context, func()) bool +pkg runtime, func Grunningnanos() int64 +pkg runtime, func NumRunnableGoroutines() (int, int) diff --git a/api/next/49097.txt b/api/next/49097.txt deleted file mode 100644 index f7240954c66228..00000000000000 --- a/api/next/49097.txt +++ /dev/null @@ -1,4 +0,0 @@ -pkg net, method (*Dialer) DialIP(context.Context, string, netip.Addr, netip.Addr) (*IPConn, error) #49097 -pkg net, method (*Dialer) DialTCP(context.Context, string, netip.AddrPort, netip.AddrPort) (*TCPConn, error) #49097 -pkg net, method (*Dialer) DialUDP(context.Context, string, netip.AddrPort, netip.AddrPort) (*UDPConn, error) #49097 -pkg net, method (*Dialer) DialUnix(context.Context, string, *UnixAddr, *UnixAddr) (*UnixConn, error) #49097 diff --git a/api/next/51945.txt b/api/next/51945.txt deleted file mode 100644 index 7db1f093e5a2a5..00000000000000 --- a/api/next/51945.txt +++ /dev/null @@ -1 +0,0 @@ -pkg errors, func AsType[$0 error](error) ($0, bool) #51945 diff --git a/api/next/61642.txt b/api/next/61642.txt deleted file mode 100644 index dd67874ab9fba4..00000000000000 --- a/api/next/61642.txt +++ /dev/null @@ -1 +0,0 @@ -pkg net/netip, method (Prefix) Compare(Prefix) int #61642 diff --git a/api/next/63963.txt b/api/next/63963.txt deleted file mode 100644 index c1aaae5044c0a4..00000000000000 --- a/api/next/63963.txt +++ /dev/null @@ -1,3 +0,0 @@ -pkg crypto/ecdsa, type PrivateKey struct, D //deprecated #63963 -pkg crypto/ecdsa, type PublicKey struct, X //deprecated #63963 -pkg crypto/ecdsa, type PublicKey struct, Y //deprecated #63963 diff --git a/api/next/65954.txt b/api/next/65954.txt deleted file mode 100644 index 88d7c2668fe02d..00000000000000 --- a/api/next/65954.txt +++ /dev/null @@ -1,6 +0,0 @@ -pkg log/slog, func NewMultiHandler(...Handler) *MultiHandler #65954 -pkg log/slog, method (*MultiHandler) Enabled(context.Context, Level) bool #65954 -pkg log/slog, method (*MultiHandler) Handle(context.Context, Record) error #65954 -pkg log/slog, method (*MultiHandler) WithAttrs([]Attr) Handler #65954 -pkg log/slog, method (*MultiHandler) WithGroup(string) Handler #65954 -pkg log/slog, type MultiHandler struct #65954 diff --git a/api/next/67546.txt b/api/next/67546.txt deleted file mode 100644 index 0b5b4b981c19a6..00000000000000 --- a/api/next/67546.txt +++ /dev/null @@ -1,5 +0,0 @@ -pkg database/sql/driver, type RowsColumnScanner interface { Close, Columns, Next, ScanColumn } #67546 -pkg database/sql/driver, type RowsColumnScanner interface, Close() error #67546 -pkg database/sql/driver, type RowsColumnScanner interface, Columns() []string #67546 -pkg database/sql/driver, type RowsColumnScanner interface, Next([]Value) error #67546 -pkg database/sql/driver, type RowsColumnScanner interface, ScanColumn(interface{}, int) error #67546 diff --git a/api/next/67813.txt b/api/next/67813.txt deleted file mode 100644 index b420a141e1fbc7..00000000000000 --- a/api/next/67813.txt +++ /dev/null @@ -1 +0,0 @@ -pkg net/http, type HTTP2Config struct, StrictMaxConcurrentRequests bool #67813 diff --git a/api/next/68021.txt b/api/next/68021.txt deleted file mode 100644 index 46156e06654878..00000000000000 --- a/api/next/68021.txt +++ /dev/null @@ -1,13 +0,0 @@ -pkg go/ast, func ParseDirective(token.Pos, string) (Directive, bool) #68021 -pkg go/ast, method (*Directive) End() token.Pos #68021 -pkg go/ast, method (*Directive) ParseArgs() ([]DirectiveArg, error) #68021 -pkg go/ast, method (*Directive) Pos() token.Pos #68021 -pkg go/ast, type Directive struct #68021 -pkg go/ast, type Directive struct, Args string #68021 -pkg go/ast, type Directive struct, ArgsPos token.Pos #68021 -pkg go/ast, type Directive struct, Name string #68021 -pkg go/ast, type Directive struct, Slash token.Pos #68021 -pkg go/ast, type Directive struct, Tool string #68021 -pkg go/ast, type DirectiveArg struct #68021 -pkg go/ast, type DirectiveArg struct, Arg string #68021 -pkg go/ast, type DirectiveArg struct, Pos token.Pos #68021 diff --git a/api/next/70352.txt b/api/next/70352.txt deleted file mode 100644 index cd264046c3641d..00000000000000 --- a/api/next/70352.txt +++ /dev/null @@ -1,2 +0,0 @@ -pkg os, method (*Process) WithHandle(func(uintptr)) error #70352 -pkg os, var ErrNoHandle error #70352 diff --git a/api/next/71287.txt b/api/next/71287.txt deleted file mode 100644 index c1e09a1f523082..00000000000000 --- a/api/next/71287.txt +++ /dev/null @@ -1,4 +0,0 @@ -pkg testing, method (*B) ArtifactDir() string #71287 -pkg testing, method (*F) ArtifactDir() string #71287 -pkg testing, method (*T) ArtifactDir() string #71287 -pkg testing, type TB interface, ArtifactDir() string #71287 diff --git a/api/next/73161.txt b/api/next/73161.txt deleted file mode 100644 index 86526b597a9463..00000000000000 --- a/api/next/73161.txt +++ /dev/null @@ -1 +0,0 @@ -pkg net/http/httputil, type ReverseProxy struct, Director //deprecated #73161 diff --git a/codereview.cfg b/codereview.cfg index 77a74f108eae36..374849066b3121 100644 --- a/codereview.cfg +++ b/codereview.cfg @@ -1 +1,2 @@ -branch: master +branch: release-branch.go1.27 +parent-branch: master diff --git a/doc/asm.html b/doc/asm.html index dd395ec8331467..5db13905e3e50e 100644 --- a/doc/asm.html +++ b/doc/asm.html @@ -1039,6 +1039,12 @@

MIPS, MIPS64

GOMIPS64_hardfloat or GOMIPS64_softfloat.

+

RISCV64

+ +

+Reference: Go RISCV64 Assembly Instructions Reference Manual +

+

Unsupported opcodes

diff --git a/doc/go_spec.html b/doc/go_spec.html index d6c7962a961b88..1234e9aa374879 100644 --- a/doc/go_spec.html +++ b/doc/go_spec.html @@ -1,6 +1,6 @@ @@ -825,8 +825,11 @@

Types

-Predeclared types, defined types, and type parameters are called named types. -An alias denotes a named type if the type given in the alias declaration is a named type. +Predeclared types (excluding any), +defined types, and +type parameters are called named types. +An alias denotes a named type if the type given in the alias declaration is a named type. +All named types are distinct.

Boolean types

@@ -835,7 +838,7 @@

Boolean types

A boolean type represents the set of Boolean truth values denoted by the predeclared constants true and false. The predeclared boolean type is bool; -it is a defined type. +it is a named type.

Numeric types

@@ -884,8 +887,7 @@

Numeric types

-To avoid portability issues all numeric types are defined -types and thus distinct except +To avoid portability issues all numeric types are named types and thus distinct except byte, which is an alias for uint8, and rune, which is an alias for int32. Explicit conversions @@ -904,7 +906,7 @@

String types

Strings are immutable: once created, it is impossible to change the contents of a string. The predeclared string type is string; -it is a defined type. +it is a named type.

@@ -1118,9 +1120,7 @@

Struct types

-Promoted fields act like ordinary fields -of a struct except that they cannot be used as field names in -composite literals of the struct. +Promoted fields act like ordinary fields of a struct.

@@ -1294,6 +1294,8 @@

Basic interfaces

exactly of the methods specified by the interface. Interfaces whose type sets can be defined entirely by a list of methods are called basic interfaces. +Interface methods cannot declare type parameters, +but they may use type parameters from the interface declaration.

@@ -1349,7 +1351,8 @@ 

Basic interfaces

-For convenience, the predeclared type any is an alias for the empty interface. +For convenience, the predeclared type any is an alias for the empty interface; +it is not a named type. [Go 1.18]

@@ -1984,6 +1987,13 @@

Assignability

x implements T.
  • +x is a (possibly partially instantiated) generic function, T +is a function type, and any type arguments not provided explicitly for x +can be inferred such that (after full instantiation) +x and T have identical underlying types +[Go 1.27]. +
  • +
  • x is the predeclared identifier nil and T is a pointer, function, slice, map, channel, or interface type, but not a type parameter. @@ -2487,11 +2497,15 @@

    Alias declarations

    -In an alias declaration the given type cannot be a type parameter. +In an alias declaration the given type cannot be a type parameter declared in the same declaration.

    -type A[P any] = P    // illegal: P is a type parameter
    +type A[P any] = P   // illegal: P is a type parameter declared in the declaration of A
    +
    +func f[P any]() {
    +	type A = P  // ok: T is a type parameter declared by the enclosing function
    +}
     

    Type definitions

    @@ -2601,8 +2615,8 @@

    Type definitions

     type T[P any] P    // illegal: P is a type parameter
     
    -func f[T any]() {
    -	type L T   // illegal: T is a type parameter declared by the enclosing function
    +func f[P any]() {
    +	type L P   // illegal: P is a type parameter declared by the enclosing function
     }
     
    @@ -2620,11 +2634,11 @@

    Type definitions

    Type parameter declarations

    -A type parameter list declares the type parameters of a generic function or type declaration. +A type parameter list declares the type parameters of a generic function, method, or type declaration. The type parameter list looks like an ordinary function parameter list except that the type parameter names must all be present and the list is enclosed in square brackets rather than parentheses -[Go 1.18]. +[Go 1.18, Go 1.27].

    @@ -2638,7 +2652,7 @@ 

    Type parameter declarations

    Each name declares a type parameter, which is a new and different named type that acts as a placeholder for an (as of yet) unknown type in the declaration. The type parameter is replaced with a type argument upon -instantiation of the generic function or type. +instantiation of the generic function, method, or type.

    @@ -2686,22 +2700,6 @@ 

    Type parameter declarations

    with a generic type.

    -

    -Within a type parameter list of a generic type T, a type constraint -may not (directly, or indirectly through the type parameter list of another -generic type) refer to T. -

    - -
    -type T1[P T1[P]] …                    // illegal: T1 refers to itself
    -type T2[P interface{ T2[int] }] …     // illegal: T2 refers to itself
    -type T3[P interface{ m(T3[int])}] …   // illegal: T3 refers to itself
    -type T4[P T5[P]] …                    // illegal: T4 refers to T5 and
    -type T5[P T4[P]] …                    //          T5 refers to T4
    -
    -type T6[P int] struct{ f *T6[P] }     // ok: reference to T6 is not in type parameter list
    -
    -

    Type constraints

    @@ -2956,7 +2954,7 @@

    Function declarations

    If the function declaration specifies type parameters, -the function name denotes a generic function. +the function name denotes a generic function [Go 1.18]. A generic function must be instantiated before it can be called or used as a value.

    @@ -2989,7 +2987,7 @@

    Method declarations

    -MethodDecl = "func" Receiver MethodName Signature [ FunctionBody ] .
    +MethodDecl = "func" Receiver MethodName [ TypeParameters ] Signature [ FunctionBody ] .
     Receiver   = Parameters .
     
    @@ -3000,7 +2998,7 @@

    Method declarations

    pointer to a defined type T, possibly followed by a list of type parameter names [P1, P2, …] enclosed in square brackets. T is called the receiver base type. A receiver base type cannot be -a pointer or interface type and it must be defined in the same package as the method. +a pointer or interface type and it must be declared in the same package as the method. The method is said to be bound to its receiver base type and the method name is visible only within selectors for type T or *T. @@ -3082,6 +3080,27 @@

    Method declarations

    func (*IPair) Second() int { … } // illegal: alias must not denote instantiated type Pair[int, int]
    +

    +If the method declaration specifies type parameters +(possibly in addition to type parameters declared by the receiver specification), the method name denotes +a generic method [Go 1.27]. +Like a generic function, a generic method must be instantiated before it can +be called or used as a value. +

    + +
    +type List[E any] []E
    +
    +// Apply returns the list obtained from applying f to each element of l.
    +func (l List[E]) Apply[F any](f func(E) F) List[F] {
    +	r := make(List[F], len(l))
    +	for i, x := range l {
    +		r[i] = f(x)
    +	}
    +	return r
    +}
    +
    +

    Expressions

    @@ -3155,7 +3174,8 @@

    Composite literals

    Composite literals construct new values for structs, arrays, slices, and maps each time they are evaluated. -They consist of the type of the literal followed by a brace-bound list of elements. +They consist of the type of the literal followed by a (possibly empty) +brace-bound list of elements. Each element may optionally be preceded by a corresponding key.

    @@ -3180,38 +3200,61 @@

    Composite literals

    If the LiteralType is a type parameter, all types in its type set must have the same underlying type which must be a valid composite literal type. +

    + +

    The types of the elements and keys must be assignable -to the respective field, element, and key types of type T; +to the respective field, element, and key types of the LiteralType; there is no additional conversion. -The key is interpreted as a field name for struct literals, +The key is interpreted as a field selector for struct literals, an index for array and slice literals, and a key for map literals. -For map literals, all elements must have a key. It is an error -to specify multiple elements with the same field name or -constant key value. For non-constant map keys, see the section on -evaluation order. +It is an error to specify multiple elements with the same field selector +or constant key value. +A literal may omit the element list; such a literal evaluates +to the zero value for its type. +

    + +

    +A parsing ambiguity arises when a composite literal using the +TypeName form of the LiteralType appears as an operand between the +keyword and the opening brace of the block +of an "if", "for", or "switch" statement, and the composite literal +is not enclosed in parentheses, square brackets, or curly braces. +In this rare case, the opening brace of the literal is erroneously parsed +as the one introducing the block of statements. To resolve the ambiguity, +the composite literal must appear within parentheses. +

    + +
    +if x == (T{a,b,c}[i]) { … }
    +if (x == T{a,b,c}[i]) { … }
    +
    + +

    Struct literals

    + +

    +For struct literals without keys, the element list must contain an element +for each struct field in the order in which the fields are declared.

    -For struct literals the following rules apply: +For struct literals with keys the following rules apply:

    @@ -3219,8 +3262,9 @@

    Composite literals

    Given the declarations

    -type Point3D struct { x, y, z float64 }
    -type Line struct { p, q Point3D }
    +type Object  struct { name, color string }
    +type Point3D struct { Object; x, y, z float64 }
    +type Line    struct { Object; p, q Point3D }
     

    @@ -3228,10 +3272,22 @@

    Composite literals

    -origin := Point3D{}                            // zero value for Point3D
    -line := Line{origin, Point3D{y: -4, z: 12.3}}  // zero value for line.q.x
    +origin := Point3D{}                                       // zero value for Point3D
    +line1 := Line{Object{}, origin, Point3D{y: -4, z: 12.3}}  // zero value for line1.q.x
    +line2 := Line{name: "diagonal", q: Point3D{1, 1, 1}}      // zero value for line2.Object.color, line2.p
    +
    + +

    +but field selectors may not denote overlapping fields: +

    + +
    +obj   := Object{"edge", "black"}
    +line3 := Line{Object: obj, name: "diagonal"}              // invalid: name denotes a field inside Object
     
    +

    Array and slice literals

    +

    For array and slice literals the following rules apply:

    @@ -3307,6 +3363,16 @@

    Composite literals

    tmp[0 : n]
    +

    Map literals

    + +

    +For map literals, each element must have a key. +For non-constant map keys, see the section on +evaluation order. +

    + +

    Elision of element types

    +

    Within a composite literal of array, slice, or map type T, elements or map keys that are themselves composite literals may elide the respective @@ -3327,22 +3393,6 @@

    Composite literals

    [2]PPoint{{1.5, -3.5}, {}} // same as [2]PPoint{PPoint(&Point{1.5, -3.5}), PPoint(&Point{})} -

    -A parsing ambiguity arises when a composite literal using the -TypeName form of the LiteralType appears as an operand between the -keyword and the opening brace of the block -of an "if", "for", or "switch" statement, and the composite literal -is not enclosed in parentheses, square brackets, or curly braces. -In this rare case, the opening brace of the literal is erroneously parsed -as the one introducing the block of statements. To resolve the ambiguity, -the composite literal must appear within parentheses. -

    - -
    -if x == (T{a,b,c}[i]) { … }
    -if (x == T{a,b,c}[i]) { … }
    -
    -

    Examples of valid array, slice, and map literals:

    @@ -3390,7 +3440,7 @@

    Function literals

    Function literals are closures: they may refer to variables -defined in a surrounding function. Those variables are then shared between +declared in a surrounding function. Those variables are then shared between the surrounding function and the function literal, and they survive as long as they are accessible.

    @@ -4334,8 +4384,8 @@

    Passing arguments to ...Instantiations

    -A generic function or type is instantiated by substituting type arguments -for the type parameters [Go 1.18]. +A generic function, method, or type is instantiated by substituting type arguments +for the type parameters [Go 1.18][Go 1.27]. Instantiation proceeds in two steps:

    @@ -4355,8 +4405,8 @@

    Instantiations

    -Instantiating a type results in a new non-generic named type; -instantiating a function produces a new non-generic function. +Instantiating a generic type, function, or method results in a non-generic type, function, +or method, respectively.

    @@ -4369,7 +4419,7 @@ 

    Instantiations

    -When using a generic function, type arguments may be provided explicitly, +When using a generic function or method, type arguments may be provided explicitly, or they may be partially or completely inferred from the context in which the function is used. Provided that they can be inferred, type argument lists may be omitted entirely if the function is: @@ -4393,7 +4443,7 @@

    Instantiations

    In all other cases, a (possibly partial) type argument list must be present. If a type argument list is absent or partial, all missing type arguments -must be inferrable from the context in which the function is used. +must be inferable from the context in which the function is used.

    @@ -4532,11 +4582,16 @@ 

    Type inference

    -Type inference supports calls of generic functions and assignments -of generic functions to (explicitly function-typed) variables. -This includes passing generic functions as arguments to other -(possibly also generic) functions, and returning generic functions -as results. +Type inference supports calls of generic functions and any use of +a generic function in a context where the function must be +assignable to a (non-generic) +function type. +The latter includes assigning a generic function to a variable +(including passing it as an argument to another function), +converting a generic function to a function type, and others. +

    + +

    Type inference operates on a set of equations specific to each of these cases. The equations are as follows (type argument lists are omitted for clarity): @@ -4545,12 +4600,12 @@

    Type inference

    • - For a function call f(a0, a1, …) where + In a function call f(a0, a1, …) where f or a function argument ai is a generic function:
      Each pair (ai, pi) of corresponding - function arguments and parameters where ai is not an + function arguments and parameters of fwhere ai is not an untyped constant yields an equation typeof(pi) ≡A typeof(ai).
      @@ -4562,19 +4617,10 @@

      Type inference

    • - For an assignment v = f of a generic function f to a - (non-generic) variable v of function type: -
      - typeof(v) ≡A typeof(f). -

      -
    • -
    • -

      - For a return statement return …, f, … where f is a - generic function returned as a result to a (non-generic) result variable - r of function type: + In a context where a generic function f must be + assignable to a (non-generic) function type T:
      - typeof(r) ≡A typeof(f). + typeof(f) ≡A T.

    @@ -4873,7 +4919,7 @@

    Operator precedence

    x <= f() // x <= f() ^a >> b // (^a) >> b f() || g() // f() || g() -x == y+1 && <-chanInt > 0 // (x == (y+1)) && ((<-chanInt) > 0) +x == y+1 && <-chanInt > 0 // (x == (y+1)) && ((<-chanInt) > 0)
    @@ -6043,7 +6089,7 @@

    Expression statements

    -append cap complex imag len make new real
    +append cap complex imag len make max min new real
     unsafe.Add unsafe.Alignof unsafe.Offsetof unsafe.Sizeof unsafe.Slice unsafe.SliceData unsafe.String unsafe.StringData
     
    @@ -6718,9 +6764,9 @@

    For statements with range clause

    map m map[K]V key k K m[k] V channel c chan E, <-chan E element e E integer value n integer type, or untyped int value i see below -function, 0 values f func(func() bool) -function, 1 value f func(func(V) bool) value v V -function, 2 values f func(func(K, V) bool) key k K v V +function, 0 values f func(yield func() bool) +function, 1 value f func(yield func(V) bool) value v V yield cannot be variadic +function, 2 values f func(yield func(K, V) bool) key k K v V yield cannot be variadic
      @@ -6791,6 +6837,13 @@

      For statements with range clause

    +

    +If the type of the range expression is a type parameter, +all types in its type set must have the same underlying type and the range expression must be valid +for that type, or, if the type set contains channel types, it must only contain channel types with +identical element types, and all channel types must permit receive operations. +

    +

    The iteration variables may be declared by the "range" clause using a form of short variable declaration @@ -6883,7 +6936,7 @@

    For statements with range clause

    } func (t *Tree[K, V]) walk(yield func(key K, val V) bool) bool { - return t == nil || t.left.walk(yield) && yield(t.key, t.value) && t.right.walk(yield) + return t == nil || t.left.walk(yield) && yield(t.key, t.value) && t.right.walk(yield) } func (t *Tree[K, V]) Walk(yield func(key K, val V) bool) { @@ -6895,14 +6948,16 @@

    For statements with range clause

    for k, v := range t.Walk { // process k, v } - -

    -If the type of the range expression is a type parameter, -all types in its type set must have the same underlying type and the range expression must be valid -for that type, or, if the type set contains channel types, it must only contain channel types with -identical element types, and all channel types must permit receive operations. -

    +// xor returns the xor-ed bytes of S +func xor[S ~[]byte](s S) byte { + var r byte + for _, b := range s { + r ^= b + } + return r +} +

    Go statements

    @@ -7383,8 +7438,8 @@

    Appending to and copying slices

    where E is the element type of S and the respective parameter passing rules apply. -As a special case, append also accepts a first argument assignable -to type []byte with a second argument of string type followed by +As a special case, append also accepts a slice whose type is assignable to +type []byte with a second argument of string type followed by .... This form appends the bytes of the string.

    @@ -7508,7 +7563,7 @@

    Close

    If the type of the argument to close is a type parameter, -all types in its type set must be channels with the same element type. +all types in its type set must be channels. It is an error if any of those channels is a receive-only channel.

    @@ -7806,40 +7861,32 @@

    Min and max

    Allocation

    - The built-in function new creates a new, initialized - variable and returns - a pointer to it. - - It accepts a single argument, which may be either an expression or a type. -

    -

    - If the argument expr is an expression of - type T, or an untyped constant expression - whose default type is T, - then new(expr) allocates a variable of - type T, initializes it to the value - of expr, and returns its address, a value of - type *T. +The built-in function new creates a new, initialized +variable and returns +a pointer to it. +It accepts a single argument, which may be either a type or an expression.

    +

    - If the argument is a type T, then new(T) - allocates a variable initialized to - the zero value of type T. +If the argument is a type T, then new(T) +allocates a variable of type T initialized to its +zero value.

    -

    - For example, new(123) and new(int) each - return a pointer to a new variable of type int. - The value of the first variable is 123, and the value - of the second is 0. +

    +If the argument is an expression x, then new(x) +allocates a variable of the type of x initialized to the value of x. +If that value is an untyped constant, it is first implicitly converted +to its default type; +if it is an untyped boolean value, it is first implicitly converted to type bool. +The predeclared identifier nil cannot be used as an argument to new.

    -
    -new(T)
    -
    -

    -For instance +For example, new(int) and new(123) each +return a pointer to a new variable of type int. +The value of the first variable is 0, and the value +of the second is 123. Similarly

    @@ -7848,13 +7895,12 @@ 

    Allocation

    -allocates storage for a variable of type S, +allocates a variable of type S, initializes it (a=0, b=0.0), and returns a value of type *S containing the address -of the location. +of the variable.

    -

    Handling panics

    Two built-in functions, panic and recover, @@ -8330,7 +8376,7 @@

    Package initialization

    -Multiple such functions may be defined per package, even within a single +Multiple such functions may be declared per package, even within a single source file. In the package block, the init identifier can be used only to declare init functions, yet the identifier itself is not declared. Thus @@ -8412,7 +8458,7 @@

    Errors

    It is the conventional interface for representing an error condition, with the nil value representing no error. -For instance, a function to read data from a file might be defined: +For instance, a function to read data from a file might be declared:

    @@ -8793,6 +8839,23 @@ 

    Go 1.24

  • +

    Go 1.27

    + +

    Type unification rules

    diff --git a/doc/godebug.md b/doc/godebug.md index c12ce5311d90d1..49b513c4cb559e 100644 --- a/doc/godebug.md +++ b/doc/godebug.md @@ -85,6 +85,9 @@ if the work module's `go.mod` or the workspace's `go.work` says `go` `1.20`, then the program defaults to `panicnil=1`, matching Go 1.20 instead of Go 1.21. +As an exception, GODEBUGs introduced for security releases +will have the new behavior apply to all versions. + Because this method of setting GODEBUG defaults was introduced only in Go 1.21, programs listing versions of Go earlier than Go 1.20 are configured to match Go 1.20, not the older version. @@ -133,9 +136,7 @@ are also treated as invalid. The defaults that will be compiled into a main package are reported by the command: -{{raw ` go list -f '{{.DefaultGODEBUG}}' my/main/package -`}} Only differences from the base Go toolchain defaults are reported. @@ -153,16 +154,100 @@ for example, see the [runtime documentation](/pkg/runtime#hdr-Environment_Variables) and the [go command documentation](/cmd/go#hdr-Build_and_test_caching). +### Go 1.28 + +Go 1.28 changed +[`net/http.FileServer`](/pkg/net/http#FileServer), +[`net/http.FileServerFS`](/pkg/net/http#FileServerFS), +[`net/http.ServeContent`](/pkg/net/http#ServeContent), +[`net/http.ServeFile`](/pkg/net/http#ServeFile), and +[`net/http.ServeFileFS`](/pkg/net/http#ServeFileFS) to +limit the maximum number of ranges in a Range header. +When the number of ranges in a header exceeds the new +`httpservecontentmaxranges` setting, the header is ignored. +The default value is `httpservecontentmaxranges=200`. +Setting `httpservecontentmaxranges=0` disables the limit. +To avoid denial of service attacks, this setting and default +was backported to Go 1.27.2 and Go 1.26.9. + +### Go 1.27 + +Go 1.27 removed the `gotypesalias` setting, as noted in the [Go 1.22](#go-122) section. + +Go 1.27 removed the `tlsunsafeekm` setting, as noted in the [Go 1.22](#go-122) section. + +Go 1.27 removed the `tlsrsakex` setting, as noted in the [Go 1.22](#go-122) section. + +Go 1.27 removed the `tls3des` setting, as noted in the [Go 1.23](#go-123) section. + +Go 1.27 removed the `tls10server` setting, as noted in the [Go 1.22](#go-122) section. + +Go 1.27 removed the `x509keypairleaf` setting, as noted in the [Go 1.23](#go-123) section. + +Go 1.27 removed the `asynctimerchan` setting, as noted in the [Go 1.23](#go-123) section. + +Go 1.27 added a new `htmlmetacontenturlescape` setting that controls whether +html/template will escape URLs in the `url=` portion of the content attribute of +HTML meta tags. The default `htmlmetacontentescape=1` will cause URLs to be +escaped. Setting `htmlmetacontentescape=0` disables this behavior. To avoid +content injection attacks, this setting and default was backported to Go 1.25.8 +and Go 1.26.1. + +Go 1.27 changes the default for `tracebacklabels` (added in [Go 1.26](#go-126)) +to `1`. This opt-out is expected to be kept indefinitely in case goroutine +labels acquire sensitive information that shouldn't be made available in +tracebacks. + +Go 1.27 added a new `x509sslcertoverrideplatform` setting that controls whether +crypto/x509 will load roots from disk on Windows and Darwin when `SSL_CERT_FILE` +or `SSL_CERT_DIR` are set. The default value `x509sslcertoverrideplatform=1` will +cause roots to be loaded from disk when these environment variables are set. +Setting `x509sslcertoverrideplatform=0` disables this behavior in favor of using +the platform certificate store instead of honoring the environment variables. We +plan to remove this setting in Go 1.31. + +Go 1.27 added a `fips140ems` setting that when set to `0` disables the +enforcement of Extended Master Secret in FIPS 140-3 mode. There is no change in +default behavior. This setting was backported to Go 1.26.6 and Go 1.25.13. +We plan to remove this setting in Go 1.31. + ### Go 1.26 Go 1.26 added a new `httpcookiemaxnum` setting that controls the maximum number of cookies that net/http will accept when parsing HTTP headers. If the number of -cookie in a header exceeds the number set in `httpcookiemaxnum`, cookie parsing +cookies in a header exceeds the number set in `httpcookiemaxnum`, cookie parsing will fail early. The default value is `httpcookiemaxnum=3000`. Setting `httpcookiemaxnum=0` will allow the cookie parsing to accept an indefinite number of cookies. To avoid denial of service attacks, this setting and default was backported to Go 1.25.2 and Go 1.24.8. +Go 1.26 added a new `urlmaxqueryparams` setting that controls the maximum number +of query parameters that net/url will accept when parsing a URL-encoded query string. +If the number of parameters exceeds the number set in `urlmaxqueryparams`, +parsing will fail early. The default value is `urlmaxqueryparams=10000`. +Setting `urlmaxqueryparams=0` disables the limit. To avoid denial of service +attacks, this setting and default was backported to Go 1.25.6 and Go 1.24.12. + +Go 1.26 added a new `urlstrictcolons` setting that controls whether `net/url.Parse` +allows malformed hostnames containing colons outside of a bracketed IPv6 address. +The default `urlstrictcolons=1` rejects URLs such as `http://localhost:1:2` or `http://::1/`. +Colons are permitted as part of a bracketed IPv6 address, such as `http://[::1]/`. + +Go 1.26 enabled two additional post-quantum key exchange mechanisms: +SecP256r1MLKEM768 and SecP384r1MLKEM1024. The default can be reverted using the +[`tlssecpmlkem` setting](/pkg/crypto/tls/#Config.CurvePreferences). + +Go 1.26 added a new `tracebacklabels` setting that controls the inclusion of +goroutine labels set through the the `runtime/pprof` package. Setting `tracebacklabels=1` +includes these key/value pairs in the goroutine status header of runtime +tracebacks and debug=2 runtime/pprof stack dumps. This format may change in the future. +(see go.dev/issue/76349) + +Go 1.26 added a new `cryptocustomrand` setting that controls whether most crypto/... +APIs ignore the random `io.Reader` parameter. For Go 1.26, it defaults +to `cryptocustomrand=0`, ignoring the random parameters. Using `cryptocustomrand=1` +reverts to the pre-Go 1.26 behavior. + ### Go 1.25 Go 1.25 added a new `decoratemappings` setting that controls whether the Go @@ -285,8 +370,8 @@ Go 1.23 changed the channels created by package time to be unbuffered (synchronous), which makes correct use of the [`Timer.Stop`](/pkg/time/#Timer.Stop) and [`Timer.Reset`](/pkg/time/#Timer.Reset) method results much easier. The [`asynctimerchan` setting](/pkg/time/#NewTimer) disables this change. -There are no runtime metrics for this change, -This setting may be removed in a future release, Go 1.27 at the earliest. +There are no runtime metrics for this change. +This setting will be removed in Go 1.27. Go 1.23 changed the mode bits reported by [`os.Lstat`](/pkg/os#Lstat) and [`os.Stat`](/pkg/os#Stat) for reparse points, which can be controlled with the `winsymlink` setting. @@ -323,6 +408,7 @@ any effect. Go 1.23 changed the default TLS cipher suites used by clients and servers when not explicitly configured, removing 3DES cipher suites. The default can be reverted using the [`tls3des` setting](/pkg/crypto/tls/#Config.CipherSuites). +This setting will be removed in Go 1.27. Go 1.23 changed the behavior of [`tls.X509KeyPair`](/pkg/crypto/tls#X509KeyPair) and [`tls.LoadX509KeyPair`](/pkg/crypto/tls#LoadX509KeyPair) to populate the @@ -330,6 +416,7 @@ Leaf field of the returned [`tls.Certificate`](/pkg/crypto/tls#Certificate). This behavior is controlled by the `x509keypairleaf` setting. For Go 1.23, it defaults to `x509keypairleaf=1`. Previous versions default to `x509keypairleaf=0`. +This setting will be removed in Go 1.27. Go 1.23 changed [`net/http.ServeContent`](/pkg/net/http#ServeContent), @@ -363,21 +450,24 @@ Whether the type checker produces `Alias` types or not is controlled by the [`gotypesalias` setting](/pkg/go/types#Alias). For Go 1.22 it defaults to `gotypesalias=0`. For Go 1.23, `gotypesalias=1` will become the default. -This setting will be removed in a future release, Go 1.27 at the earliest. +This setting will be removed in Go 1.27. Go 1.22 changed the default minimum TLS version supported by both servers and clients to TLS 1.2. The default can be reverted to TLS 1.0 using the [`tls10server` setting](/pkg/crypto/tls/#Config). +This setting will be removed in Go 1.27. Go 1.22 changed the default TLS cipher suites used by clients and servers when not explicitly configured, removing the cipher suites which used RSA based key exchange. The default can be reverted using the [`tlsrsakex` setting](/pkg/crypto/tls/#Config). +This setting will be removed in Go 1.27. Go 1.22 disabled [`ConnectionState.ExportKeyingMaterial`](/pkg/crypto/tls/#ConnectionState.ExportKeyingMaterial) when the connection supports neither TLS 1.3 nor Extended Master Secret (implemented in Go 1.21). It can be reenabled with the [`tlsunsafeekm` setting](/pkg/crypto/tls/#ConnectionState.ExportKeyingMaterial). +This setting will be removed in Go 1.27. Go 1.22 changed how the runtime interacts with transparent huge pages on Linux. In particular, a common default Linux kernel configuration can result in diff --git a/doc/initial/6-stdlib/99-minor/0-heading.md b/doc/initial/6-stdlib/99-minor/0-heading.md index e80ebc64c380fd..266d98f496a779 100644 --- a/doc/initial/6-stdlib/99-minor/0-heading.md +++ b/doc/initial/6-stdlib/99-minor/0-heading.md @@ -1,10 +1 @@ ### Minor changes to the library {#minor_library_changes} - -#### go/types - -The `Var.Kind` method returns an enumeration of type `VarKind` that -classifies the variable (package-level, local, receiver, parameter, -result, or struct field). See issue #70250. - -Callers of `NewVar` or `NewParam` are encouraged to call `Var.SetKind` -to ensure that this attribute is set correctly in all cases. diff --git a/doc/next/1-intro.md b/doc/next/1-intro.md deleted file mode 100644 index 3cd0d66b5ad4e3..00000000000000 --- a/doc/next/1-intro.md +++ /dev/null @@ -1,8 +0,0 @@ - - -## DRAFT RELEASE NOTES — Introduction to Go 1.26 {#introduction} - -**Go 1.26 is not yet released. These are work-in-progress release notes. -Go 1.26 is expected to be released in February 2026.** diff --git a/doc/next/2-language.md b/doc/next/2-language.md deleted file mode 100644 index 71da62f59e59ab..00000000000000 --- a/doc/next/2-language.md +++ /dev/null @@ -1,32 +0,0 @@ -## Changes to the language {#language} - - - -The built-in `new` function, which creates a new variable, now allows -its operand to be an expression, specifying the initial value of the -variable. - -This feature is particularly useful when working with serialization -packages such as `encoding/json` or protocol buffers that use a -pointer to represent an optional value, as it enables an optional -field to be populated in a simple expression, for example: - -```go -import "encoding/json" - -type Person struct { - Name string `json:"name"` - Age *int `json:"age"` // age if known; nil otherwise -} - -func personJSON(name string, born time.Time) ([]byte, error) { - return json.Marshal(Person{ - Name: name, - Age: new(yearsSince(born)), - }) -} - -func yearsSince(t time.Time) int { - return int(time.Since(t).Hours() / (365.25 * 24)) // approximately -} -``` diff --git a/doc/next/3-tools.md b/doc/next/3-tools.md deleted file mode 100644 index c0a4601c0b9e74..00000000000000 --- a/doc/next/3-tools.md +++ /dev/null @@ -1,21 +0,0 @@ -## Tools {#tools} - -### Go command {#go-command} - - -`cmd/doc`, and `go tool doc` have been deleted. `go doc` can be used as -a replacement for `go tool doc`: it takes the same flags and arguments and -has the same behavior. - - -The `go fix` command, following the pattern of `go vet` in Go 1.10, -now uses the Go analysis framework (`golang.org/x/tools/go/analysis`). -This means the same analyzers that provide diagnostics in `go vet` -can be used to suggest and apply fixes in `go fix`. -The `go fix` command's historical fixers, all of which were obsolete, -have been removed and replaced by a suite of new analyzers that -offer fixes to use newer features of the language and library. - - -### Cgo {#cgo} - diff --git a/doc/next/4-runtime.md b/doc/next/4-runtime.md deleted file mode 100644 index 1f8e445e0b10de..00000000000000 --- a/doc/next/4-runtime.md +++ /dev/null @@ -1 +0,0 @@ -## Runtime {#runtime} diff --git a/doc/next/5-toolchain.md b/doc/next/5-toolchain.md deleted file mode 100644 index cc32f30a521a6d..00000000000000 --- a/doc/next/5-toolchain.md +++ /dev/null @@ -1,12 +0,0 @@ -## Compiler {#compiler} - -## Assembler {#assembler} - -## Linker {#linker} - -## Bootstrap {#bootstrap} - - -As mentioned in the [Go 1.24 release notes](/doc/go1.24#bootstrap), Go 1.26 now requires -Go 1.24.6 or later for bootstrap. -We expect that Go 1.28 will require a minor release of Go 1.26 or later for bootstrap. diff --git a/doc/next/6-stdlib/0-heading.md b/doc/next/6-stdlib/0-heading.md deleted file mode 100644 index a992170d433326..00000000000000 --- a/doc/next/6-stdlib/0-heading.md +++ /dev/null @@ -1,2 +0,0 @@ -## Standard library {#library} - diff --git a/doc/next/6-stdlib/99-minor/0-heading.md b/doc/next/6-stdlib/99-minor/0-heading.md deleted file mode 100644 index e80ebc64c380fd..00000000000000 --- a/doc/next/6-stdlib/99-minor/0-heading.md +++ /dev/null @@ -1,10 +0,0 @@ -### Minor changes to the library {#minor_library_changes} - -#### go/types - -The `Var.Kind` method returns an enumeration of type `VarKind` that -classifies the variable (package-level, local, receiver, parameter, -result, or struct field). See issue #70250. - -Callers of `NewVar` or `NewParam` are encouraged to call `Var.SetKind` -to ensure that this attribute is set correctly in all cases. diff --git a/doc/next/6-stdlib/99-minor/README b/doc/next/6-stdlib/99-minor/README deleted file mode 100644 index fac778de050642..00000000000000 --- a/doc/next/6-stdlib/99-minor/README +++ /dev/null @@ -1 +0,0 @@ -API changes and other small changes to the standard library go here. diff --git a/doc/next/6-stdlib/99-minor/crypto/ecdsa/63963.md b/doc/next/6-stdlib/99-minor/crypto/ecdsa/63963.md deleted file mode 100644 index 81efc00bb5d657..00000000000000 --- a/doc/next/6-stdlib/99-minor/crypto/ecdsa/63963.md +++ /dev/null @@ -1 +0,0 @@ -The `big.Int` fields of [PublicKey] and [PrivateKey] are now deprecated. diff --git a/doc/next/6-stdlib/99-minor/crypto/rsa/74115.md b/doc/next/6-stdlib/99-minor/crypto/rsa/74115.md deleted file mode 100644 index a3647a79f2efd8..00000000000000 --- a/doc/next/6-stdlib/99-minor/crypto/rsa/74115.md +++ /dev/null @@ -1,5 +0,0 @@ -If [PrivateKey] fields are modified after calling [PrivateKey.Precompute], -[PrivateKey.Validate] now fails. - -[PrivateKey.D] is now checked for consistency with precomputed values, even if -it is not used. diff --git a/doc/next/6-stdlib/99-minor/database/sql/driver/67546.md b/doc/next/6-stdlib/99-minor/database/sql/driver/67546.md deleted file mode 100644 index 8cb9089583a89d..00000000000000 --- a/doc/next/6-stdlib/99-minor/database/sql/driver/67546.md +++ /dev/null @@ -1 +0,0 @@ -A database driver may implement [RowsColumnScanner] to entirely override `Scan` behavior. diff --git a/doc/next/6-stdlib/99-minor/errors/51945.md b/doc/next/6-stdlib/99-minor/errors/51945.md deleted file mode 100644 index 44ac7222e6d990..00000000000000 --- a/doc/next/6-stdlib/99-minor/errors/51945.md +++ /dev/null @@ -1,2 +0,0 @@ -The new [AsType] function is a generic version of [As]. It is type-safe, faster, -and, in most cases, easier to use. diff --git a/doc/next/6-stdlib/99-minor/go/ast/68021.md b/doc/next/6-stdlib/99-minor/go/ast/68021.md deleted file mode 100644 index 0ff1a0b11e8e0c..00000000000000 --- a/doc/next/6-stdlib/99-minor/go/ast/68021.md +++ /dev/null @@ -1,4 +0,0 @@ -The new [ParseDirective] function parses [directive -comments](/doc/comment#Syntax), which are comments such as `//go:generate`. -Source code tools can support their own directive comments and this new API -should help them implement the conventional syntax. diff --git a/doc/next/6-stdlib/99-minor/image/jpeg/75603.md b/doc/next/6-stdlib/99-minor/image/jpeg/75603.md deleted file mode 100644 index 43421761fdad82..00000000000000 --- a/doc/next/6-stdlib/99-minor/image/jpeg/75603.md +++ /dev/null @@ -1,2 +0,0 @@ -The JPEG encoder and decoder have been replaced with new, faster, more accurate implementations. -Code that expects specific bit-for-bit outputs from the encoder or decoder may need to be updated. diff --git a/doc/next/6-stdlib/99-minor/log/slog/65954.md b/doc/next/6-stdlib/99-minor/log/slog/65954.md deleted file mode 100644 index 631ed665df24a7..00000000000000 --- a/doc/next/6-stdlib/99-minor/log/slog/65954.md +++ /dev/null @@ -1,6 +0,0 @@ -The [`NewMultiHandler`](/pkg/log/slog#NewMultiHandler) function creates a -[`MultiHandler`](/pkg/log/slog#MultiHandler) that invokes all the given Handlers. -Its `Enable` method reports whether any of the handlers' `Enabled` methods -return true. -Its `Handle`, `WithAttr` and `WithGroup` methods call the corresponding method -on each of the enabled handlers. diff --git a/doc/next/6-stdlib/99-minor/net/49097.md b/doc/next/6-stdlib/99-minor/net/49097.md deleted file mode 100644 index bb7947b0a11377..00000000000000 --- a/doc/next/6-stdlib/99-minor/net/49097.md +++ /dev/null @@ -1 +0,0 @@ -Added context aware dial functions for TCP, UDP, IP and Unix networks. diff --git a/doc/next/6-stdlib/99-minor/net/http/67813.md b/doc/next/6-stdlib/99-minor/net/http/67813.md deleted file mode 100644 index 74b8c7644f831e..00000000000000 --- a/doc/next/6-stdlib/99-minor/net/http/67813.md +++ /dev/null @@ -1,4 +0,0 @@ -The new -[HTTP2Config.StrictMaxConcurrentRequests](/pkg/net/http#HTTP2Config.StrictMaxConcurrentRequests) -field controls whether a new connection should be opened -if an existing HTTP/2 connection has exceeded its stream limit. diff --git a/doc/next/6-stdlib/99-minor/net/http/httptest/31054.md b/doc/next/6-stdlib/99-minor/net/http/httptest/31054.md deleted file mode 100644 index ef6a4898f26a9d..00000000000000 --- a/doc/next/6-stdlib/99-minor/net/http/httptest/31054.md +++ /dev/null @@ -1,2 +0,0 @@ -The HTTP client returned by [Server.Client] will now redirect requests for -`example.com` and any subdomains to the server being tested. diff --git a/doc/next/6-stdlib/99-minor/net/http/httputil/73161.md b/doc/next/6-stdlib/99-minor/net/http/httputil/73161.md deleted file mode 100644 index f6318f85534746..00000000000000 --- a/doc/next/6-stdlib/99-minor/net/http/httputil/73161.md +++ /dev/null @@ -1,11 +0,0 @@ -The [ReverseProxy.Director] configuration field is deprecated -in favor of [ReverseProxy.Rewrite]. - -A malicious client can remove headers added by a `Director` function -by designating those headers as hop-by-hop. Since there is no way to address -this problem within the scope of the `Director` API, we added a new -`Rewrite` hook in Go 1.20. `Rewrite` hooks are provided with both the -unmodified inbound request received by the proxy and the outbound request -which will be sent by the proxy. - -Since the `Director` hook is fundamentally unsafe, we are now deprecating it. diff --git a/doc/next/6-stdlib/99-minor/net/netip/61642.md b/doc/next/6-stdlib/99-minor/net/netip/61642.md deleted file mode 100644 index 3d79f2e76aee04..00000000000000 --- a/doc/next/6-stdlib/99-minor/net/netip/61642.md +++ /dev/null @@ -1 +0,0 @@ -The new [Prefix.Compare] method compares two prefixes. diff --git a/doc/next/6-stdlib/99-minor/os/70352.md b/doc/next/6-stdlib/99-minor/os/70352.md deleted file mode 100644 index 5651639dadb499..00000000000000 --- a/doc/next/6-stdlib/99-minor/os/70352.md +++ /dev/null @@ -1,4 +0,0 @@ -The new [Process.WithHandle] method provides access to an internal process -handle on supported platforms (Linux 5.4 or later and Windows). On Linux, -the process handle is a pidfd. The method returns [ErrNoHandle] on unsupported -platforms or when no process handle is available. diff --git a/doc/next/6-stdlib/99-minor/os/73676.md b/doc/next/6-stdlib/99-minor/os/73676.md deleted file mode 100644 index 70d01f262d86fc..00000000000000 --- a/doc/next/6-stdlib/99-minor/os/73676.md +++ /dev/null @@ -1,4 +0,0 @@ -On Windows, the [OpenFile] `flag` parameter can now contain any combination of -Windows-specific file flags, such as `FILE_FLAG_OVERLAPPED` and -`FILE_FLAG_SEQUENTIAL_SCAN`, for control of file or device caching behavior, -access modes, and other special-purpose flags. \ No newline at end of file diff --git a/doc/next/6-stdlib/99-minor/testing/71287.md b/doc/next/6-stdlib/99-minor/testing/71287.md deleted file mode 100644 index 82cac638101099..00000000000000 --- a/doc/next/6-stdlib/99-minor/testing/71287.md +++ /dev/null @@ -1,18 +0,0 @@ -The new methods [T.ArtifactDir], [B.ArtifactDir], and [F.ArtifactDir] -return a directory in which to write test output files (artifacts). - -When the `-artifacts` flag is provided to `go test`, -this directory will be located under the output directory -(specified with `-outputdir`, or the current directory by default). -Otherwise, artifacts are stored in a temporary directory -which is removed after the test completes. - -The first call to `ArtifactDir` when `-artifacts` is provided -writes the location of the directory to the test log. - -For example, in a test named `TestArtifacts`, -`t.ArtifactDir()` emits: - -``` -=== ARTIFACTS Test /path/to/artifact/dir -``` diff --git a/doc/next/7-ports.md b/doc/next/7-ports.md deleted file mode 100644 index 07445454227bcb..00000000000000 --- a/doc/next/7-ports.md +++ /dev/null @@ -1,6 +0,0 @@ -## Ports {#ports} - -### Windows - - -As [announced](/doc/go1.25#windows) in the Go 1.25 release notes, the [broken](/doc/go1.24#windows) 32-bit windows/arm port (`GOOS=windows` `GOARCH=arm`) is removed. diff --git a/lib/fips140/certified.txt b/lib/fips140/certified.txt new file mode 100644 index 00000000000000..efd3caba85ba62 --- /dev/null +++ b/lib/fips140/certified.txt @@ -0,0 +1 @@ +v1.0.0-c2097c7c diff --git a/lib/fips140/fips140.sum b/lib/fips140/fips140.sum index 703d1dc60e58ab..5dff95b1b62e9e 100644 --- a/lib/fips140/fips140.sum +++ b/lib/fips140/fips140.sum @@ -1,4 +1,7 @@ -# SHA256 checksums of snapshot zip files in this directory. +# Checksums of snapshot zip files in this directory. +# Each line is "NAME SHA256HEX H1HASH", where SHA256HEX is the SHA256 +# checksum of the zip file and H1HASH is the module zip hash of its +# contents, as recorded in go.sum files and the module cache. # These checksums are included in the FIPS security policy # (validation instructions sent to the lab) and MUST NOT CHANGE. # That is, the zip files themselves must not change. @@ -9,4 +12,5 @@ # # go test cmd/go/internal/fips140 -update # -v1.0.0-c2097c7c.zip daf3614e0406f67ae6323c902db3f953a1effb199142362a039e7526dfb9368b +v1.0.0-c2097c7c.zip daf3614e0406f67ae6323c902db3f953a1effb199142362a039e7526dfb9368b h1:YapsF69QWGwygaBqdI0rp7IfE5a6tAwepNAHONVcWqQ= +v1.26.0.zip 9b28f847fdf1db4a36cb2b2f8ec09443c039383f085630a03ecfaddf6db7ea23 h1:dtoPX1ALGGp4rMLzyh6oqIkYRXnXxRkpPWu56l5DFpM= diff --git a/lib/fips140/inprocess.txt b/lib/fips140/inprocess.txt index efd3caba85ba62..426c2fb87f5d08 100644 --- a/lib/fips140/inprocess.txt +++ b/lib/fips140/inprocess.txt @@ -1 +1 @@ -v1.0.0-c2097c7c +v1.26.0 diff --git a/lib/fips140/v1.26.0.zip b/lib/fips140/v1.26.0.zip new file mode 100644 index 00000000000000..f53ade80367a8b Binary files /dev/null and b/lib/fips140/v1.26.0.zip differ diff --git a/lib/hg/goreposum.py b/lib/hg/goreposum.py new file mode 100644 index 00000000000000..1a7d7a444667a9 --- /dev/null +++ b/lib/hg/goreposum.py @@ -0,0 +1,64 @@ +# Copyright 2025 The Go Authors. All rights reserved. +# Use of this source code is governed by a BSD-style +# license that can be found in the LICENSE file. + +# Mercurial extension to add a 'goreposum' command that +# computes a hash of a remote repo's tag state. +# Tag definitions can come from the .hgtags file stored in +# any head of any branch, and the server protocol does not +# expose the tags directly. However, the protocol does expose +# the hashes of all the branch heads, so we can use a hash of +# all those branch names and heads as a conservative snapshot +# of the entire remote repo state, and use that as the tag sum. +# Any change on the server then invalidates the tag sum, +# even if it didn't have anything to do with tags, but at least +# we will avoid re-cloning a server when there have been no +# changes at all. +# +# Separately, this extension also adds a 'golookup' command that +# returns the hash of a specific reference, like 'default' or a tag. +# And golookup of a hash confirms that it still exists on the server. +# We can use that to revalidate that specific versions still exist and +# have the same meaning they did the last time we checked. +# +# Usage: +# +# hg --config "extensions.goreposum=$GOROOT/lib/hg/goreposum.py" goreposum REPOURL + +import base64, hashlib, sys +from mercurial import registrar, ui, hg, node +from mercurial.i18n import _ +cmdtable = {} +command = registrar.command(cmdtable) +@command(b'goreposum', [], _('url'), norepo=True) +def goreposum(ui, url): + """ + goreposum computes a checksum of all the named state in the remote repo. + It hashes together all the branch names and hashes + and then all the bookmark names and hashes. + Tags are stored in .hgtags files in any of the branches, + so the branch metadata includes the tags as well. + """ + h = hashlib.sha256() + peer = hg.peer(ui, {}, url) + for name, revs in peer.branchmap().items(): + h.update(name) + for r in revs: + h.update(b' ') + h.update(r) + h.update(b'\n') + if (b'bookmarks' in peer.listkeys(b'namespaces')): + for name, rev in peer.listkeys(b'bookmarks').items(): + h.update(name) + h.update(b'=') + h.update(rev) + h.update(b'\n') + print('r1:'+base64.standard_b64encode(h.digest()).decode('utf-8')) + +@command(b'golookup', [], _('url rev'), norepo=True) +def golookup(ui, url, rev): + """ + golookup looks up a single identifier in the repo, + printing its hash. + """ + print(node.hex(hg.peer(ui, {}, url).lookup(rev)).decode('utf-8')) diff --git a/lib/time/update.bash b/lib/time/update.bash index 66494752ea3c4b..768c244cf0f374 100755 --- a/lib/time/update.bash +++ b/lib/time/update.bash @@ -24,8 +24,8 @@ # in the CL match the update.bash in the CL. # Versions to use. -CODE=2025b -DATA=2025b +CODE=2026c +DATA=2026c set -e diff --git a/lib/time/zoneinfo.zip b/lib/time/zoneinfo.zip index b107695d1ef042..46c90a2b806a92 100644 Binary files a/lib/time/zoneinfo.zip and b/lib/time/zoneinfo.zip differ diff --git a/src/README.vendor b/src/README.vendor index e6a58d5fb55505..156a81dad4c18d 100644 --- a/src/README.vendor +++ b/src/README.vendor @@ -39,12 +39,14 @@ Go from source and use that 'go' binary to update its source tree. Requirements may be added, updated, and removed with 'go get'. The vendor directory may be updated with 'go mod vendor'. +Tree inconsistencies are reported by 'go test cmd/internal/moddeps'. A typical sequence might be: cd src # or src/cmd go get golang.org/x/net@master go mod tidy go mod vendor + go test cmd/internal/moddeps Use caution when passing '-u' to 'go get'. The '-u' flag updates modules providing all transitively imported packages, not only @@ -53,3 +55,22 @@ the module providing the target package. Note that 'go mod vendor' only copies packages that are transitively imported by packages in the current module. If a new package is needed, it should be imported before running 'go mod vendor'. + +Go release cycle considerations +=============================== + +Applying changes to packages that are vendored follows the considerations +written down at go.dev/s/release. + +When the Go tree is open for development, a specific change may be pulled in +at any time that it is needed. During the release freeze, the bar for changes +in vendored packages is the same as it is for changes in non-vendored packages. +After a major release is out, minor Go releases follow a more involved process +documented at go.dev/wiki/MinorReleases#cherry-pick-cls-for-vendored-golangorgx-packages. + +In addition to individual updates that happen on demand, all dependencies in +the std and cmd modules are updated to their latest available versions at least +twice during every major release cycle. This is done to avoid the possibility of +some dependencies being left on very old versions and in turn make their eventual +update more disruptive. This recurring process is tracked in go.dev/issue/36905. +The golang.org/x/build/cmd/updatestd command exists to assist with that process. diff --git a/src/archive/tar/format.go b/src/archive/tar/format.go index 9954b4d9f5548a..32e58a9d9b4e1e 100644 --- a/src/archive/tar/format.go +++ b/src/archive/tar/format.go @@ -147,6 +147,12 @@ const ( // Max length of a special file (PAX header, GNU long name or link). // This matches the limit used by libarchive. maxSpecialFileSize = 1 << 20 + + // Maximum number of sparse file entries. + // We should never actually hit this limit + // (every sparse encoding will first be limited by maxSpecialFileSize), + // but this adds an additional layer of defense. + maxSparseFileEntries = 1 << 20 ) // blockPadding computes the number of bytes needed to pad offset up to the diff --git a/src/archive/tar/reader.go b/src/archive/tar/reader.go index 16ac2f5b17c28b..e426c72ffe9cc3 100644 --- a/src/archive/tar/reader.go +++ b/src/archive/tar/reader.go @@ -45,8 +45,9 @@ func NewReader(r io.Reader) *Reader { // Any remaining data in the current file is automatically discarded. // At the end of the archive, Next returns the error io.EOF. // -// If Next encounters a non-local name (as defined by [filepath.IsLocal]) +// If Next encounters a non-local file name (as defined by [filepath.IsLocal]) // and the GODEBUG environment variable contains `tarinsecurepath=0`, +// Only file names are validated, not link targets. // Next returns the header with an [ErrInsecurePath] error. // A future version of Go may introduce this behavior by default. // Programs that want to accept non-local names can ignore @@ -490,7 +491,8 @@ func (tr *Reader) readOldGNUSparseMap(hdr *Header, blk *block) (sparseDatas, err } s := blk.toGNU().sparse() spd := make(sparseDatas, 0, s.maxEntries()) - for { + totalSize := len(s) + for totalSize < maxSpecialFileSize { for i := 0; i < s.maxEntries(); i++ { // This termination condition is identical to GNU and BSD tar. if s.entry(i).offset()[0] == 0x00 { @@ -501,7 +503,11 @@ func (tr *Reader) readOldGNUSparseMap(hdr *Header, blk *block) (sparseDatas, err if p.err != nil { return nil, p.err } - spd = append(spd, sparseEntry{Offset: offset, Length: length}) + var err error + spd, err = appendSparseEntry(spd, sparseEntry{Offset: offset, Length: length}) + if err != nil { + return nil, err + } } if s.isExtended()[0] > 0 { @@ -510,10 +516,12 @@ func (tr *Reader) readOldGNUSparseMap(hdr *Header, blk *block) (sparseDatas, err return nil, err } s = blk.toSparse() + totalSize += len(s) continue } return spd, nil // Done } + return nil, errSparseTooLong } // readGNUSparseMap1x0 reads the sparse map as stored in GNU's PAX sparse format @@ -586,7 +594,10 @@ func readGNUSparseMap1x0(r io.Reader) (sparseDatas, error) { if err1 != nil || err2 != nil { return nil, ErrHeader } - spd = append(spd, sparseEntry{Offset: offset, Length: length}) + spd, err = appendSparseEntry(spd, sparseEntry{Offset: offset, Length: length}) + if err != nil { + return nil, err + } } return spd, nil } @@ -620,12 +631,22 @@ func readGNUSparseMap0x1(paxHdrs map[string]string) (sparseDatas, error) { if err1 != nil || err2 != nil { return nil, ErrHeader } - spd = append(spd, sparseEntry{Offset: offset, Length: length}) + spd, err = appendSparseEntry(spd, sparseEntry{Offset: offset, Length: length}) + if err != nil { + return nil, err + } sparseMap = sparseMap[2:] } return spd, nil } +func appendSparseEntry(spd sparseDatas, ent sparseEntry) (sparseDatas, error) { + if len(spd) >= maxSparseFileEntries { + return nil, errSparseTooLong + } + return append(spd, ent), nil +} + // Read reads from the current file in the tar archive. // It returns (0, io.EOF) when it reaches the end of that file, // until [Next] is called to advance to the next file. diff --git a/src/archive/tar/reader_test.go b/src/archive/tar/reader_test.go index fca53dae741bd5..a324674cb7bb19 100644 --- a/src/archive/tar/reader_test.go +++ b/src/archive/tar/reader_test.go @@ -10,6 +10,7 @@ import ( "errors" "fmt" "hash/crc32" + "internal/obscuretestdata" "io" "maps" "math" @@ -25,10 +26,11 @@ import ( func TestReader(t *testing.T) { vectors := []struct { - file string // Test input file - headers []*Header // Expected output headers - chksums []string // CRC32 checksum of files, leave as nil if not checked - err error // Expected error to occur + file string // Test input file + obscured bool // Obscured with obscuretestdata package + headers []*Header // Expected output headers + chksums []string // CRC32 checksum of files, leave as nil if not checked + err error // Expected error to occur }{{ file: "testdata/gnu.tar", headers: []*Header{{ @@ -523,8 +525,9 @@ func TestReader(t *testing.T) { file: "testdata/pax-nul-path.tar", err: ErrHeader, }, { - file: "testdata/neg-size.tar", - err: ErrHeader, + file: "testdata/neg-size.tar.base64", + obscured: true, + err: ErrHeader, }, { file: "testdata/issue10968.tar", err: ErrHeader, @@ -629,15 +632,24 @@ func TestReader(t *testing.T) { }} for _, v := range vectors { - t.Run(path.Base(v.file), func(t *testing.T) { - f, err := os.Open(v.file) + t.Run(strings.TrimSuffix(path.Base(v.file), ".base64"), func(t *testing.T) { + path := v.file + if v.obscured { + tf, err := obscuretestdata.DecodeToTempFile(path) + if err != nil { + t.Fatalf("obscuredtestdata.DecodeToTempFile(%s): %v", path, err) + } + path = tf + } + + f, err := os.Open(path) if err != nil { t.Fatalf("unexpected error: %v", err) } defer f.Close() var fr io.Reader = f - if strings.HasSuffix(v.file, ".bz2") { + if strings.HasSuffix(v.file, ".bz2") || strings.HasSuffix(v.file, ".bz2.base64") { fr = bzip2.NewReader(fr) } @@ -775,7 +787,7 @@ type readBadSeeker struct{ io.ReadSeeker } func (rbs *readBadSeeker) Seek(int64, int) (int64, error) { return 0, fmt.Errorf("illegal seek") } -// TestReadTruncation test the ending condition on various truncated files and +// TestReadTruncation tests the ending condition on various truncated files and // that truncated files are still detected even if the underlying io.Reader // satisfies io.Seeker. func TestReadTruncation(t *testing.T) { @@ -1133,6 +1145,17 @@ func TestReadOldGNUSparseMap(t *testing.T) { input: makeInput(FormatGNU, "", makeSparseStrings(sparseDatas{{10 << 30, 512}, {20 << 30, 512}})...), wantMap: sparseDatas{{10 << 30, 512}, {20 << 30, 512}}, + }, { + input: makeInput(FormatGNU, "", + makeSparseStrings(func() sparseDatas { + var datas sparseDatas + // This is more than enough entries to exceed our limit. + for i := range int64(1 << 20) { + datas = append(datas, sparseEntry{i * 2, (i * 2) + 1}) + } + return datas + }())...), + wantErr: errSparseTooLong, }} for i, v := range vectors { diff --git a/src/archive/tar/stat_unix.go b/src/archive/tar/stat_unix.go index f999f56db6c915..891a1a3b4a3e30 100644 --- a/src/archive/tar/stat_unix.go +++ b/src/archive/tar/stat_unix.go @@ -19,7 +19,7 @@ func init() { sysStat = statUnix } -// userMap and groupMap caches UID and GID lookups for performance reasons. +// userMap and groupMap cache UID and GID lookups for performance reasons. // The downside is that renaming uname or gname by the OS never takes effect. var userMap, groupMap sync.Map // map[int]string diff --git a/src/archive/tar/strconv.go b/src/archive/tar/strconv.go index 217efe9e2ee7f4..d3c28a8c4e3bce 100644 --- a/src/archive/tar/strconv.go +++ b/src/archive/tar/strconv.go @@ -312,7 +312,7 @@ func formatPAXRecord(k, v string) (string, error) { // "%d %s=%s\n" % (size, key, value) // // Keys and values should be UTF-8, but the number of bad writers out there -// forces us to be a more liberal. +// forces us to be more liberal. // Thus, we only reject all keys with NUL, and only reject NULs in values // for the PAX version of the USTAR string fields. // The key must not contain an '=' character. diff --git a/src/archive/tar/testdata/gnu-sparse-big.tar b/src/archive/tar/testdata/gnu-sparse-big.tar deleted file mode 100644 index 1a5cfc96d92983..00000000000000 Binary files a/src/archive/tar/testdata/gnu-sparse-big.tar and /dev/null differ diff --git a/src/archive/tar/testdata/gnu-sparse-big.tar.base64 b/src/archive/tar/testdata/gnu-sparse-big.tar.base64 new file mode 100644 index 00000000000000..c25505083b1304 --- /dev/null +++ b/src/archive/tar/testdata/gnu-sparse-big.tar.base64 @@ -0,0 +1,90 @@ +Z251LXNwYXJzZQAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAADAwMDAwMDAAMDAwMDAw +MAAwMDAwMDAwADAwMDAwMDA2MDAwADAwMDAwMDAwMDAwADAyMjIyNwAgUwAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAB1c3RhciAgAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAwMDAwMDAwADAwMDAw +MDAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAACAAAAAAAAAAlQL4gAw +MDAwMDAwMTAwMACAAAAAAAAABKgXxgAwMDAwMDAwMTAwMACAAAAAAAAABvwjqgAwMDAwMDAwMTAw +MACAAAAAAAAACVAvjgAwMDAwMDAwMTAwMAABgAAAAAAAAA34R1gAAAAAAAAAAAAAAAAAAAAAAACA +AAAAAAAAC6Q7cgAwMDAwMDAwMTAwMACAAAAAAAAADfhHVgAwMDAwMDAwMTAwMAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1 +Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5AAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAADAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2 +Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAMDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3 +ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OQAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4 +OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5AAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAADAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5 +MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAMDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkw +MTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OQAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA= diff --git a/src/archive/tar/testdata/neg-size.tar b/src/archive/tar/testdata/neg-size.tar deleted file mode 100644 index 21edf38cc3c3d9..00000000000000 Binary files a/src/archive/tar/testdata/neg-size.tar and /dev/null differ diff --git a/src/archive/tar/testdata/neg-size.tar.base64 b/src/archive/tar/testdata/neg-size.tar.base64 new file mode 100644 index 00000000000000..b7e26a05b1e1ce --- /dev/null +++ b/src/archive/tar/testdata/neg-size.tar.base64 @@ -0,0 +1,9 @@ +EwMwMBMDLTgyMTk1MDI5NnQTE4NzfINzEzAwcXfhZrsDMDAwAAAAEDAxMRNz9DEwMTAwdBMTg3N8 +g3NzADATc3yDc3P0eFMTc/QxMDEwMHQTE4NzfINzc/QwE3N8g3Nz9HFTMNR0MBMwMHEw9DAAAAAQ +MDGAABAwMTETc/QxMDH0MHQTMDBx1OFmuwMAAAD/gICAADExNTYyMQAgMBP///+AMTAwdHhTMDB0 +MBMwMHF3MDEwMTAwdBMTg3N8g3Nz9HhTMDB0MBMwMHF34Wa7AzAwMAAAABAwMTETc/QxMDEwMHQT +E4NzfINzc/QwE3N8g3Nz9HhTE3P0MTAxMDB0ExODc3yDc3MwMBNzfINzczB4UzAwdDATMDBxMDAA +gAAAEDAxc/QxMDEwMHQTAAAAIOFmuwMwNAAAABAwMTET////gDEwMHR4UzAwdDATMDBxd+FmuwMw +MDAAAAAQMDExE3ODc3P0eFMTc/QxMDEwMHQTE4NzfINzc/QzMTEwMzM2MjQ4NDYxMjgzODBzfINz +c/R4UzAwdDATMDBxMDAwAAAAEDAxAAAQMDExE3P0MTAxMDB0EzAwcdThZrsDMDQAAAAQg3N8g3Nz +9DATc3yDc3P0eFMwMHQwEzAwcTAwMAAAABAwMQAAEDAxMRNz9DEwMTAwdBMwMHgw4Wa7AwAAEDA= diff --git a/src/archive/tar/testdata/pax-sparse-big.tar b/src/archive/tar/testdata/pax-sparse-big.tar deleted file mode 100644 index 65d1f8eceb0849..00000000000000 Binary files a/src/archive/tar/testdata/pax-sparse-big.tar and /dev/null differ diff --git a/src/archive/tar/testdata/pax-sparse-big.tar.base64 b/src/archive/tar/testdata/pax-sparse-big.tar.base64 new file mode 100644 index 00000000000000..640ef32159fd48 --- /dev/null +++ b/src/archive/tar/testdata/pax-sparse-big.tar.base64 @@ -0,0 +1,108 @@ +UGF4SGVhZGVycy4wL3BheC1zcGFyc2UAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAADAwMDAwMDAAMDAwMDAw +MAAwMDAwMDAwADAwMDAwMDAwMTcyADAwMDAwMDAwMDAwADAxMjIyNwAgeAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAB1c3RhcgAwMAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAy +MiBHTlUuc3BhcnNlLm1ham9yPTEKMjIgR05VLnNwYXJzZS5taW5vcj0wCjMwIEdOVS5zcGFyc2Uu +bmFtZT1wYXgtc3BhcnNlCjM1IEdOVS5zcGFyc2UucmVhbHNpemU9NjAwMDAwMDAwMDAKMTMgc2l6 +ZT0zNTg0CgAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAEdO +VVNwYXJzZUZpbGUuMC9wYXgtc3BhcnNlAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAwMDAwMDAwADAwMDAwMDAA +MDAwMDAwMAAwMDAwMDAwNzAwMAAwMDAwMDAwMDAwMAAwMTM3MzcAIDAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAdXN0YXIAMDAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAMDAwMDAwMAAwMDAwMDAw +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAANgo5 +OTk5OTk5NDg4CjUxMgoxOTk5OTk5OTQ4OAo1MTIKMjk5OTk5OTk0ODgKNTEyCjM5OTk5OTk5NDg4 +CjUxMgo0OTk5OTk5OTQ4OAo1MTIKNTk5OTk5OTk0ODgKNTEyCgAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAMDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3 +ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OQAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4 +OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5AAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAADAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5 +MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAMDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkw +MTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OQAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAx +MjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5AAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAADAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEy +MzQ1Njc4OTAxMjM0NTY3ODkwMTIzNDU2Nzg5MDEyMzQ1Njc4OTAxMjM0NTY3ODkAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA diff --git a/src/archive/tar/testdata/writer-big-long.tar b/src/archive/tar/testdata/writer-big-long.tar deleted file mode 100644 index 09fc5dd3dd7fc5..00000000000000 Binary files a/src/archive/tar/testdata/writer-big-long.tar and /dev/null differ diff --git a/src/archive/tar/testdata/writer-big-long.tar.base64 b/src/archive/tar/testdata/writer-big-long.tar.base64 new file mode 100644 index 00000000000000..171d2870685f39 --- /dev/null +++ b/src/archive/tar/testdata/writer-big-long.tar.base64 @@ -0,0 +1,27 @@ +bG9uZ25hbWUvbG9uZ25hbWUvbG9uZ25hbWUvbG9uZ25hbWUvbG9uZ25hbWUvbG9uZ25hbWUvbG9u +Z25hbWUvbG9uZ25hbWUvbG9uZ25hbWUvbG9uZ25hbWUvbG9uZ25hbWUvbDAwMDAwMDAAMDAwMDAw +MAAwMDAwMDAwADAwMDAwMDAwMjU2ADAwMDAwMDAwMDAwADAzMTQyMAAgeAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAB1c3RhcgAwMAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAx +NTQgcGF0aD1sb25nbmFtZS9sb25nbmFtZS9sb25nbmFtZS9sb25nbmFtZS9sb25nbmFtZS9sb25n +bmFtZS9sb25nbmFtZS9sb25nbmFtZS9sb25nbmFtZS9sb25nbmFtZS9sb25nbmFtZS9sb25nbmFt +ZS9sb25nbmFtZS9sb25nbmFtZS9sb25nbmFtZS8xNmdpZy50eHQKMjAgc2l6ZT0xNzE3OTg2OTE4 +NAoAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAGxv +bmduYW1lL2xvbmduYW1lL2xvbmduYW1lL2xvbmduYW1lL2xvbmduYW1lL2xvbmduYW1lL2xvbmdu +YW1lL2xvbmduYW1lL2xvbmduYW1lL2xvbmduYW1lL2xvbmduYW1lL2wwMDAwNjQ0ADAwMDE3NTAA +MDAwMTc1MAAwMDAwMDAwMDAwMAAxMjMzMjc3MDUwNwAwMzY0NjIAIDAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAdXN0YXIAMDBndWlsbGF1bWUAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAGd1aWxsYXVtZQAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAMDAwMDAwMAAwMDAwMDAw +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA diff --git a/src/archive/tar/writer_test.go b/src/archive/tar/writer_test.go index 9e484432ea90b6..759000f6b9569a 100644 --- a/src/archive/tar/writer_test.go +++ b/src/archive/tar/writer_test.go @@ -8,6 +8,7 @@ import ( "bytes" "encoding/hex" "errors" + "internal/obscuretestdata" "io" "io/fs" "maps" @@ -74,8 +75,9 @@ func TestWriter(t *testing.T) { ) vectors := []struct { - file string // Optional filename of expected output - tests []testFnc + file string // Optional filename of expected output + obscured bool // Whether file is obscured + tests []testFnc }{{ // The writer test file was produced with this command: // tar (GNU tar) 1.26 @@ -151,7 +153,8 @@ func TestWriter(t *testing.T) { // bsdtar -xvf writer-big-long.tar // // This file is in PAX format. - file: "testdata/writer-big-long.tar", + file: "testdata/writer-big-long.tar.base64", + obscured: true, tests: []testFnc{ testHeader{Header{ Typeflag: TypeReg, @@ -393,7 +396,8 @@ func TestWriter(t *testing.T) { testClose{}, }, }, { - file: "testdata/gnu-sparse-big.tar", + file: "testdata/gnu-sparse-big.tar.base64", + obscured: true, tests: []testFnc{ testHeader{Header{ Typeflag: TypeGNUSparse, @@ -425,7 +429,8 @@ func TestWriter(t *testing.T) { testClose{nil}, }, }, { - file: "testdata/pax-sparse-big.tar", + file: "testdata/pax-sparse-big.tar.base64", + obscured: true, tests: []testFnc{ testHeader{Header{ Typeflag: TypeReg, @@ -483,7 +488,7 @@ func TestWriter(t *testing.T) { return x == y } for _, v := range vectors { - t.Run(path.Base(v.file), func(t *testing.T) { + t.Run(strings.TrimSuffix(path.Base(v.file), ".base64"), func(t *testing.T) { const maxSize = 10 << 10 // 10KiB buf := new(bytes.Buffer) tw := NewWriter(iotest.TruncateWriter(buf, maxSize)) @@ -522,7 +527,16 @@ func TestWriter(t *testing.T) { } if v.file != "" { - want, err := os.ReadFile(v.file) + path := v.file + if v.obscured { + tf, err := obscuretestdata.DecodeToTempFile(path) + if err != nil { + t.Fatalf("obscuretestdata.DecodeToTempFile(%s): %v", path, err) + } + path = tf + } + + want, err := os.ReadFile(path) if err != nil { t.Fatalf("ReadFile() = %v, want nil", err) } diff --git a/src/archive/zip/reader.go b/src/archive/zip/reader.go index 6b57f767fc849d..8741456d99e9cc 100644 --- a/src/archive/zip/reader.go +++ b/src/archive/zip/reader.go @@ -63,7 +63,6 @@ type File struct { zip *Reader zipr io.ReaderAt headerOffset int64 // includes overall ZIP archive baseOffset - zip64 bool // zip64 extended information extra field presence } // OpenReader will open the Zip file specified by name and return a ReadCloser. @@ -406,10 +405,6 @@ func readDirectoryHeader(f *File, r io.Reader) error { f.NonUTF8 = f.Flags&0x800 == 0 } - needUSize := f.UncompressedSize == ^uint32(0) - needCSize := f.CompressedSize == ^uint32(0) - needHeaderOffset := f.headerOffset == int64(^uint32(0)) - // Best effort to find what we need. // Other zip authors might not even follow the basic format, // and we'll just ignore the Extra content in that case. @@ -425,28 +420,23 @@ parseExtras: switch fieldTag { case zip64ExtraID: - f.zip64 = true - // update directory values from the zip64 extra block. // They should only be consulted if the sizes read earlier // are maxed out. - // See golang.org/issue/13367. - if needUSize { - needUSize = false + // See go.dev/issue/13367 and go.dev/issue/31692. + if f.UncompressedSize == ^uint32(0) { if len(fieldBuf) < 8 { return ErrFormat } f.UncompressedSize64 = fieldBuf.uint64() } - if needCSize { - needCSize = false + if f.CompressedSize == ^uint32(0) { if len(fieldBuf) < 8 { return ErrFormat } f.CompressedSize64 = fieldBuf.uint64() } - if needHeaderOffset { - needHeaderOffset = false + if f.headerOffset == int64(^uint32(0)) { if len(fieldBuf) < 8 { return ErrFormat } @@ -509,20 +499,6 @@ parseExtras: } } - // Assume that uncompressed size 2³²-1 could plausibly happen in - // an old zip32 file that was sharding inputs into the largest chunks - // possible (or is just malicious; search the web for 42.zip). - // If needUSize is true still, it means we didn't see a zip64 extension. - // As long as the compressed size is not also 2³²-1 (implausible) - // and the header is not also 2³²-1 (equally implausible), - // accept the uncompressed size 2³²-1 as valid. - // If nothing else, this keeps archive/zip working with 42.zip. - _ = needUSize - - if needCSize || needHeaderOffset { - return ErrFormat - } - return nil } @@ -605,7 +581,7 @@ func readDirectoryEnd(r io.ReaderAt, size int64) (dir *directoryEnd, baseOffset d.comment = string(b[:l]) // These values mean that the file can be a zip64 file - if d.directoryRecords == 0xffff || d.directorySize == 0xffff || d.directoryOffset == 0xffffffff { + if d.directoryRecords == 0xffff || d.directorySize == 0xffffffff || d.directoryOffset == 0xffffffff { p, err := findDirectory64End(r, directoryEndOffset) if err == nil && p >= 0 { directoryEndOffset = p @@ -834,7 +810,16 @@ func (r *Reader) initFileList() { continue } - for dir := path.Dir(name); dir != "."; dir = path.Dir(dir) { + dir := name + for { + if idx := strings.LastIndex(dir, "/"); idx < 0 { + break + } else { + dir = dir[:idx] + } + if dirs[dir] { + break + } dirs[dir] = true } diff --git a/src/archive/zip/reader_test.go b/src/archive/zip/reader_test.go index cb8a0c28714eff..5ce994e4dd95c5 100644 --- a/src/archive/zip/reader_test.go +++ b/src/archive/zip/reader_test.go @@ -9,6 +9,7 @@ import ( "encoding/binary" "encoding/hex" "errors" + "fmt" "internal/obscuretestdata" "io" "io/fs" @@ -1874,3 +1875,83 @@ func TestBaseOffsetPlusOverflow(t *testing.T) { // as the section reader offset & size were < 0. NewReader(bytes.NewReader(data), int64(len(data))+1875) } + +func BenchmarkReaderOneDeepDir(b *testing.B) { + var buf bytes.Buffer + zw := NewWriter(&buf) + + for i := range 4000 { + name := strings.Repeat("a/", i) + "data" + zw.CreateHeader(&FileHeader{ + Name: name, + Method: Store, + }) + } + + if err := zw.Close(); err != nil { + b.Fatal(err) + } + data := buf.Bytes() + + for b.Loop() { + zr, err := NewReader(bytes.NewReader(data), int64(len(data))) + if err != nil { + b.Fatal(err) + } + zr.Open("does-not-exist") + } +} + +func BenchmarkReaderManyDeepDirs(b *testing.B) { + var buf bytes.Buffer + zw := NewWriter(&buf) + + for i := range 2850 { + name := fmt.Sprintf("%x", i) + name = strings.Repeat("/"+name, i+1)[1:] + + zw.CreateHeader(&FileHeader{ + Name: name, + Method: Store, + }) + } + + if err := zw.Close(); err != nil { + b.Fatal(err) + } + data := buf.Bytes() + + for b.Loop() { + zr, err := NewReader(bytes.NewReader(data), int64(len(data))) + if err != nil { + b.Fatal(err) + } + zr.Open("does-not-exist") + } +} + +func BenchmarkReaderManyShallowFiles(b *testing.B) { + var buf bytes.Buffer + zw := NewWriter(&buf) + + for i := range 310000 { + name := fmt.Sprintf("%v", i) + zw.CreateHeader(&FileHeader{ + Name: name, + Method: Store, + }) + } + + if err := zw.Close(); err != nil { + b.Fatal(err) + } + data := buf.Bytes() + + for b.Loop() { + zr, err := NewReader(bytes.NewReader(data), int64(len(data))) + if err != nil { + b.Fatal(err) + } + zr.Open("does-not-exist") + } +} diff --git a/src/archive/zip/struct.go b/src/archive/zip/struct.go index 3ebf39f5a694a2..f09323a581dade 100644 --- a/src/archive/zip/struct.go +++ b/src/archive/zip/struct.go @@ -156,7 +156,11 @@ type FileHeader struct { // UncompressedSize64 is the uncompressed size of the file in bytes. UncompressedSize64 uint64 - Extra []byte + // Extra are the extensible data fields. The writer automatically includes + // the appropriate Zip64 field if necessary, and [Writer.Close] appends the + // Central Directory version of the Zip64 field to Extra. + Extra []byte + ExternalAttrs uint32 // Meaning depends on CreatorVersion } @@ -337,11 +341,6 @@ func (h *FileHeader) SetMode(mode fs.FileMode) { } } -// isZip64 reports whether the file size exceeds the 32 bit limit -func (h *FileHeader) isZip64() bool { - return h.CompressedSize64 >= uint32max || h.UncompressedSize64 >= uint32max -} - func (h *FileHeader) hasDataDescriptor() bool { return h.Flags&0x8 != 0 } diff --git a/src/archive/zip/testdata/zip64/go126-deflate-zeros-5g.zsparse b/src/archive/zip/testdata/zip64/go126-deflate-zeros-5g.zsparse new file mode 100644 index 00000000000000..8bd977eaaa2c09 Binary files /dev/null and b/src/archive/zip/testdata/zip64/go126-deflate-zeros-5g.zsparse differ diff --git a/src/archive/zip/testdata/zip64/go126-offset-eq-4g.zsparse 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0a310054e37678..40bc505ea8f17a 100644 --- a/src/archive/zip/writer.go +++ b/src/archive/zip/writer.go @@ -42,6 +42,10 @@ type header struct { } // NewWriter returns a new [Writer] writing a zip file to w. +// +// Note that the exact bytes written to w are not covered by the Go 1 +// compatibility promise. Callers, including tests, should not depend on the +// exact written bytes. func NewWriter(w io.Writer) *Writer { return &Writer{cw: &countWriter{w: bufio.NewWriter(w)}} } @@ -89,48 +93,65 @@ func (w *Writer) Close() error { // write central directory start := w.cw.count + usedZip64 := false for _, h := range w.dir { + // For the Central Directory, we always have the correct sizes. + // + // Implementations disagree on what triggers the inclusion of a Zip64 + // extra field: Info-ZIP only writes it if any size or offset EXCEEDS + // 4GiB - 1, while libarchive writes it if any size REACHES OR EXCEEDS + // 4GiB - 1, or if the offset EXCEEDS 4GiB - 1. The spec is ambiguous. + // + // We conservatively write Zip64 extra fields if any size or offset + // REACHES OR EXCEEDS 4GiB - 1, to maximize compatibility with readers. + // There is no ambiguity in parsing, so there is no downside to it. + // + // The spec is clear though that all and only the fields that REACH OR + // EXCEED 4GiB - 1 are included in the Zip64 extra, once it's present. + readerVersion := h.ReaderVersion + if h.CompressedSize64 >= uint32max || h.UncompressedSize64 >= uint32max || h.offset >= uint32max { + usedZip64 = true + readerVersion = max(readerVersion, zipVersion45) + var size uint16 + var buf [28]byte // 2x uint16 + up to 3x uint64 + eb := writeBuf(buf[:]) + eb.uint16(zip64ExtraID) + eb.uint16(0) // size to be filled out later + if h.UncompressedSize64 >= uint32max { + eb.uint64(h.UncompressedSize64) + size += 8 + } + if h.CompressedSize64 >= uint32max { + eb.uint64(h.CompressedSize64) + size += 8 + } + if h.offset >= uint32max { + eb.uint64(h.offset) + size += 8 + } + sb := writeBuf(buf[2:]) + sb.uint16(size) + h.Extra = append(h.Extra, buf[:4+size]...) + } + var buf [directoryHeaderLen]byte b := writeBuf(buf[:]) b.uint32(uint32(directoryHeaderSignature)) b.uint16(h.CreatorVersion) - b.uint16(h.ReaderVersion) + b.uint16(readerVersion) b.uint16(h.Flags) b.uint16(h.Method) b.uint16(h.ModifiedTime) b.uint16(h.ModifiedDate) b.uint32(h.CRC32) - if h.isZip64() || h.offset >= uint32max { - // the file needs a zip64 header. store maxint in both - // 32 bit size fields (and offset later) to signal that the - // zip64 extra header should be used. - b.uint32(uint32max) // compressed size - b.uint32(uint32max) // uncompressed size - - // append a zip64 extra block to Extra - var buf [28]byte // 2x uint16 + 3x uint64 - eb := writeBuf(buf[:]) - eb.uint16(zip64ExtraID) - eb.uint16(24) // size = 3x uint64 - eb.uint64(h.UncompressedSize64) - eb.uint64(h.CompressedSize64) - eb.uint64(h.offset) - h.Extra = append(h.Extra, buf[:]...) - } else { - b.uint32(h.CompressedSize) - b.uint32(h.UncompressedSize) - } - + b.uint32(uint32(min(h.CompressedSize64, uint32max))) + b.uint32(uint32(min(h.UncompressedSize64, uint32max))) b.uint16(uint16(len(h.Name))) b.uint16(uint16(len(h.Extra))) b.uint16(uint16(len(h.Comment))) b = b[4:] // skip disk number start and internal file attr (2x uint16) b.uint32(h.ExternalAttrs) - if h.offset > uint32max { - b.uint32(uint32max) - } else { - b.uint32(uint32(h.offset)) - } + b.uint32(uint32(min(h.offset, uint32max))) if _, err := w.cw.Write(buf[:]); err != nil { return err } @@ -154,7 +175,11 @@ func (w *Writer) Close() error { f(size, offset) } - if records >= uint16max || size >= uint32max || offset >= uint32max { + // Emit the Zip64 EOCD records whenever any individual entry needed a Zip64 + // extra field, even if the EOCD's own fields fit in 32 bits, matching + // Info-ZIP (but not libarchive). See APPNOTE 4.3.9.2: "when Zip64 + // extensions are in use, the EOCD64 record must be present." + if usedZip64 || records >= uint16max || size >= uint32max || offset >= uint32max { var buf [directory64EndLen + directory64LocLen]byte b := writeBuf(buf[:]) @@ -179,24 +204,18 @@ func (w *Writer) Close() error { if _, err := w.cw.Write(buf[:]); err != nil { return err } - - // store max values in the regular end record to signal - // that the zip64 values should be used instead - records = uint16max - size = uint32max - offset = uint32max } // write end record var buf [directoryEndLen]byte b := writeBuf(buf[:]) b.uint32(uint32(directoryEndSignature)) - b = b[4:] // skip over disk number and first disk number (2x uint16) - b.uint16(uint16(records)) // number of entries this disk - b.uint16(uint16(records)) // number of entries total - b.uint32(uint32(size)) // size of directory - b.uint32(uint32(offset)) // start of directory - b.uint16(uint16(len(w.comment))) // byte size of EOCD comment + b = b[4:] // skip over disk number and first disk number (2x uint16) + b.uint16(uint16(min(uint16max, records))) // number of entries this disk + b.uint16(uint16(min(uint16max, records))) // number of entries total + b.uint32(uint32(min(uint32max, size))) // size of directory + b.uint32(uint32(min(uint32max, offset))) // start of directory + b.uint16(uint16(len(w.comment))) // byte size of EOCD comment if _, err := w.cw.Write(buf[:]); err != nil { return err } @@ -394,38 +413,79 @@ func writeHeader(w io.Writer, h *header) error { return errLongExtra } + // The correct behavior of a streaming writer, implemented by Info-ZIP 3.0, + // would be to write 0xFFFFFFFF in the size fields and then write a Zip64 + // extra field with the sizes at zero (to signal they are stored in a ZIP64 + // data descriptor, in case the file is > 4GiB). + // + // We don't do that, and instead write zeroes directly in the size fields, + // because that wastes 28 bytes for every file smaller than 4GiB, and + // because it would change the encoding of nearly every zip file created by + // archive/zip. (No one should rely on it being stable, but still.) + // + // Anyway, the Local File Header is not that important, as the Central + // Directory is authoritative, and there we always write the correct sizes. + // + // If we do know the sizes, because [Writer.CreateRaw] is used and the data + // descriptor flag is not set, then we write them to the header. If either + // size reaches 4GiB, we write 0xFFFFFFFF placeholders and a Zip64 extra + // field with BOTH sizes, per the spec and matching Info-ZIP. Note this is + // different from the Central Directory Zip64 extra field logic, somehow. + // + // (One final interesting case that doesn't apply to us: if the input is + // streaming but the output is seekable, Info-ZIP always writes Zip64 extra + // fields, and then goes back and patches in the sizes, even for files < 4GiB.) + + var zip64ExtraInfo []byte + readerVersion := h.ReaderVersion + noDataDescriptor := h.raw && !h.hasDataDescriptor() + if noDataDescriptor && (h.CompressedSize64 > uint32max || h.UncompressedSize64 > uint32max) { + readerVersion = max(readerVersion, zipVersion45) + zip64ExtraInfo = make([]byte, 20) // 2x uint16 + 2x uint64 + b := writeBuf(zip64ExtraInfo) + b.uint16(zip64ExtraID) + b.uint16(16) // size of Zip64 extra field data + b.uint64(h.UncompressedSize64) + b.uint64(h.CompressedSize64) + } + var buf [fileHeaderLen]byte b := writeBuf(buf[:]) b.uint32(uint32(fileHeaderSignature)) - b.uint16(h.ReaderVersion) + b.uint16(readerVersion) b.uint16(h.Flags) b.uint16(h.Method) b.uint16(h.ModifiedTime) b.uint16(h.ModifiedDate) - // In raw mode (caller does the compression), the values are either - // written here or in the trailing data descriptor based on the header - // flags. - if h.raw && !h.hasDataDescriptor() { + if noDataDescriptor { b.uint32(h.CRC32) - b.uint32(uint32(min(h.CompressedSize64, uint32max))) - b.uint32(uint32(min(h.UncompressedSize64, uint32max))) + if zip64ExtraInfo != nil { + b.uint32(uint32max) + b.uint32(uint32max) + } else { + b.uint32(uint32(h.CompressedSize64)) + b.uint32(uint32(h.UncompressedSize64)) + } } else { - // When this package handle the compression, these values are - // always written to the trailing data descriptor. b.uint32(0) // crc32 b.uint32(0) // compressed size b.uint32(0) // uncompressed size } b.uint16(uint16(len(h.Name))) - b.uint16(uint16(len(h.Extra))) + b.uint16(uint16(len(h.Extra) + len(zip64ExtraInfo))) if _, err := w.Write(buf[:]); err != nil { return err } if _, err := io.WriteString(w, h.Name); err != nil { return err } - _, err := w.Write(h.Extra) - return err + if _, err := w.Write(h.Extra); err != nil { + return err + } + if _, err := w.Write(zip64ExtraInfo); err != nil { + return err + } + return nil } // CreateRaw adds a file to the zip archive using the provided [FileHeader] and @@ -597,7 +657,7 @@ func (w *fileWriter) close() error { fh.CompressedSize64 = uint64(w.compCount.count) fh.UncompressedSize64 = uint64(w.rawCount.count) - if fh.isZip64() { + if w.CompressedSize64 > uint32max || w.UncompressedSize64 > uint32max { fh.CompressedSize = uint32max fh.UncompressedSize = uint32max fh.ReaderVersion = zipVersion45 // requires 4.5 - File uses ZIP64 format extensions @@ -613,13 +673,13 @@ func (w *fileWriter) writeDataDescriptor() error { if !w.hasDataDescriptor() { return nil } - // Write data descriptor. This is more complicated than one would - // think, see e.g. comments in zipfile.c:putextended() and - // https://bugs.openjdk.org/browse/JDK-7073588. - // The approach here is to write 8 byte sizes if needed without - // adding a zip64 extra in the local header (too late anyway). + // See the comment in [writeHeader] about how and why we don't signal ZIP64 + // mode in the local file header. If one of the sizes turns out to exceed + // 4GiB, we use the 64-bit sizes anyway, for lack of alternatives. + // + // See also https://bugs.openjdk.org/browse/JDK-7073588. var buf []byte - if w.isZip64() { + if w.CompressedSize64 > uint32max || w.UncompressedSize64 > uint32max { buf = make([]byte, dataDescriptor64Len) } else { buf = make([]byte, dataDescriptorLen) @@ -627,7 +687,7 @@ func (w *fileWriter) writeDataDescriptor() error { b := writeBuf(buf) b.uint32(dataDescriptorSignature) // de-facto standard, required by OS X b.uint32(w.CRC32) - if w.isZip64() { + if w.CompressedSize64 > uint32max || w.UncompressedSize64 > uint32max { b.uint64(w.CompressedSize64) b.uint64(w.UncompressedSize64) } else { diff --git a/src/archive/zip/zip64_sparse_test.go b/src/archive/zip/zip64_sparse_test.go new file mode 100644 index 00000000000000..96260a425a5df6 --- /dev/null +++ b/src/archive/zip/zip64_sparse_test.go @@ -0,0 +1,240 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package zip + +import ( + "cmp" + "compress/gzip" + "errors" + "fmt" + "io" + "os" + "slices" +) + +// A sparseFile represents an archive as a sequence of non-zero byte spans +// (the LFH headers, the Central Directory, the EOCD records, and any +// non-zero compressed bodies) plus a total length. Bytes outside any span +// are implicitly zero. This is the storage format used for goldens under +// testdata/zip64/ (suffix .zsparse) and the in-memory shape produced by +// the writer-reproduction harness. +// +// On-disk layout (all little-endian): +// +// uint64 size +// uint32 numSpans +// for each span: +// uint64 offset +// uint32 dataLen +// dataLen bytes +// +// Spans are sorted by offset and non-overlapping. +type sparseFile struct { + Size int64 + Spans []sparseSpan +} + +type sparseSpan struct { + Offset int64 + Data []byte +} + +// ReadAt implements [io.ReaderAt] by serving the underlying spans and +// synthesizing zero bytes for any gap inside [0, Size). +func (f *sparseFile) ReadAt(p []byte, off int64) (int, error) { + if off < 0 { + return 0, errors.New("sparseFile: negative offset") + } + if off >= f.Size { + return 0, io.EOF + } + end := min(off+int64(len(p)), f.Size) + n := int(end - off) + clear(p[:n]) + for _, s := range f.Spans { + sEnd := s.Offset + int64(len(s.Data)) + if sEnd <= off || s.Offset >= end { + continue + } + from := max(s.Offset, off) + to := min(sEnd, end) + copy(p[from-off:to-off], s.Data[from-s.Offset:to-s.Offset]) + } + if n < len(p) { + return n, io.EOF + } + return n, nil +} + +// materializeTail returns the last keep bytes of the conceptual file as a +// plain byte slice, suitable for [parseCD]. +func (f *sparseFile) materializeTail(keep int64) (data []byte, baseOff uint64) { + if keep > f.Size { + keep = f.Size + } + base := f.Size - keep + buf := make([]byte, keep) + f.ReadAt(buf, base) + return buf, uint64(base) +} + +const sparseChunk = 4096 + +// scanSparse stream-reads r and builds a sparseFile, treating any contiguous +// run of zero bytes (rounded to sparseChunk boundaries) as a gap. Adjacent +// non-zero chunks are coalesced into one span. +func scanSparse(r io.Reader) (*sparseFile, error) { + f := &sparseFile{} + var cur *sparseSpan + buf := make([]byte, sparseChunk) + for { + n, err := io.ReadFull(r, buf) + if n > 0 { + chunk := buf[:n] + if isAllZero(chunk) { + if cur != nil { + f.Spans = append(f.Spans, *cur) + cur = nil + } + } else { + if cur == nil { + cur = &sparseSpan{Offset: f.Size} + } + cur.Data = append(cur.Data, chunk...) + } + f.Size += int64(n) + } + if err != nil { + if err == io.EOF || err == io.ErrUnexpectedEOF { + break + } + return nil, err + } + } + if cur != nil { + f.Spans = append(f.Spans, *cur) + } + return f, nil +} + +// writeSparse serializes f to w in the on-disk format described on +// [sparseFile]. +func writeSparse(w io.Writer, f *sparseFile) error { + var hdr [12]byte + le.PutUint64(hdr[:8], uint64(f.Size)) + le.PutUint32(hdr[8:12], uint32(len(f.Spans))) + if _, err := w.Write(hdr[:]); err != nil { + return err + } + for _, s := range f.Spans { + var b [12]byte + le.PutUint64(b[:8], uint64(s.Offset)) + le.PutUint32(b[8:12], uint32(len(s.Data))) + if _, err := w.Write(b[:]); err != nil { + return err + } + if _, err := w.Write(s.Data); err != nil { + return err + } + } + return nil +} + +// readSparse parses the on-disk format from r. +func readSparse(r io.Reader) (*sparseFile, error) { + var hdr [12]byte + if _, err := io.ReadFull(r, hdr[:]); err != nil { + return nil, err + } + f := &sparseFile{ + Size: int64(le.Uint64(hdr[:8])), + } + n := le.Uint32(hdr[8:12]) + if n > 1<<20 { + return nil, fmt.Errorf("sparseFile: implausible span count %d", n) + } + f.Spans = make([]sparseSpan, n) + for i := range f.Spans { + var b [12]byte + if _, err := io.ReadFull(r, b[:]); err != nil { + return nil, err + } + f.Spans[i].Offset = int64(le.Uint64(b[:8])) + sz := le.Uint32(b[8:12]) + f.Spans[i].Data = make([]byte, sz) + if _, err := io.ReadFull(r, f.Spans[i].Data); err != nil { + return nil, err + } + } + if !slices.IsSortedFunc(f.Spans, func(a, b sparseSpan) int { + return cmp.Compare(a.Offset, b.Offset) + }) { + return nil, errors.New("sparseFile: spans not sorted") + } + return f, nil +} + +// readSparseFile reads a sparse file from path. The file is expected to be +// gzip-compressed; the outer gzip wrap shrinks goldens that contain non-zero +// compressed bodies (e.g., the deflate-zeros entries) by 100x because +// deflate-of-zeros is highly repetitive. Small Store goldens benefit too: +// gzip's header overhead is ~30 bytes, well under the bytes saved on a 4 KB +// sparse representation. +func readSparseFile(path string) (*sparseFile, error) { + f, err := os.Open(path) + if err != nil { + return nil, err + } + defer f.Close() + zr, err := gzip.NewReader(f) + if err != nil { + return nil, err + } + defer zr.Close() + return readSparse(zr) +} + +// isAllZero reports whether every byte in b is 0. +func isAllZero(b []byte) bool { + for _, c := range b { + if c != 0 { + return false + } + } + return true +} + +// sparseBuffer accumulates writes into a [sparseFile], dropping any +// chunkSize-byte chunk that is all-zero. This makes capturing the result +// of pushing multi-GiB streams of zeros through the writer almost free — +// the only bytes that end up retained are the LFHs, the Central +// Directory, the EOCD records, and any non-zero compressed body. +type sparseBuffer struct { + f sparseFile + cur *sparseSpan +} + +func (t *sparseBuffer) Write(p []byte) (int, error) { + n := len(p) + for len(p) > 0 { + k := len(p) + if k > sparseChunk { + k = sparseChunk + } + chunk := p[:k] + if isAllZero(chunk) { + t.cur = nil + } else { + if t.cur == nil { + t.f.Spans = append(t.f.Spans, sparseSpan{Offset: t.f.Size}) + t.cur = &t.f.Spans[len(t.f.Spans)-1] + } + t.cur.Data = append(t.cur.Data, chunk...) + } + t.f.Size += int64(k) + p = p[k:] + } + return n, nil +} diff --git a/src/archive/zip/zip64_test.go b/src/archive/zip/zip64_test.go new file mode 100644 index 00000000000000..9252e6ac3de3ac --- /dev/null +++ b/src/archive/zip/zip64_test.go @@ -0,0 +1,614 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package zip + +import ( + "bytes" + "encoding/binary" + "errors" + "fmt" + "io" + "path/filepath" + "slices" + "strings" + "testing" +) + +// TestZip64WriterCDGoldens checks that the archive/zip Writer emits a Central +// Directory that matches the Zip64 conventions used by Info-ZIP, libarchive, +// and the pre-CL archive/zip writer (go126-*), for archives at or above 4 GiB, +// except where we intentionally diverged. +// +// For each golden in testdata/zip64/*.zsparse (see [sparseFile] for the +// committed format), the test: +// 1. Parses the golden's CD into a producer-independent snapshot — which +// fields hold 0xFFFFFFFF placeholders, which Zip64 extra sub-fields are +// present and in what order, and the EOCD/EOCD64 values. +// 2. Verifies the production [NewReader] parses the same archive. +// 3. Replays the same entries through a fresh [Writer] into a [sparseBuffer] +// and parses our own CD. +// 4. Verifies the production [NewReader] parses our reproduced archive too. +// 5. Compares the two snapshots field-by-field, ignoring producer-specific +// details (creator version, external attrs, non-Zip64 extras, absolute +// byte offsets that depend on LFH/data-descriptor layout). +func TestZip64WriterCDGoldens(t *testing.T) { + if testing.Short() { + t.Skip("skipping in short mode; each golden replays a multi-GiB write") + } + + matches, err := filepath.Glob("testdata/zip64/*.zsparse") + if err != nil { + t.Fatal(err) + } + if len(matches) == 0 { + t.Fatal("missing Zip64 goldens in testdata/zip64") + } + + // Tail materialized for parseCD. Goldens have ≤ 2 entries; their CD + // plus EOCD records fits in well under 1 MiB. + const tailKeep = 1 << 20 + + // archive/zip's writer takes the most defensive position on every + // spec-fuzzy point: it always emits the Zip64 extra at the 0xFFFFFFFF + // boundary (matching libarchive but more conservative than Info-ZIP) AND + // emits EOCD64 whenever any entry has a Zip64 extra in its CD record + // (matching Info-ZIP but more conservative than libarchive). The go126- + // goldens are output of an older archive/zip writer, and the format + // deliberately diverges; they are kept here so the reader-side check + // enforces backwards compatibility with archives produced by our own past + // writer, and to ensure we only diverge where intended. + expectedDiff := map[string]bool{ + // Info-ZIP treats a CD size field of exactly 0xFFFFFFFF as a real + // value and omits the Zip64 extra; archive/zip defensively emits + // the Zip64 extra with USize64+CSize64. + "infozip-store-4g-minus-1": true, + + // Info-ZIP treats a CD offset field of exactly 0xFFFFFFFF as a real + // value and omits the Zip64 extra for offset; archive/zip defensively + // emits the Zip64 extra with the offset sub-field. + "infozip-offset-eq-4g": true, + + // libarchive's writer emits EOCD64 only on EOCD-level overflow (CD + // size/offset > 4GiB, records > 0xFFFF); archive/zip also emits + // EOCD64 when any per-entry CD record uses a Zip64 extra, even if + // the EOCD fields fit in 32 bits. + "libarchive-deflate-zeros-5g": true, + + // libarchive's LFH always carries a UT timestamp extra (~9 bytes), + // so its dirOffset for a body of 4GiB-59 lands just past 0xFFFFFFFF + // and it emits EOCD64. archive/zip's streaming LFH has no such + // extras and stays under uint32max. + "libarchive-store-just-under-4g": true, + + // The old archive/zip writer differs from the current writer on + // every Zip64-using entry: it always wrote a fixed 24-byte Zip64 + // extra with all three sub-fields (usize, csize, offset) and set + // both 32-bit size fields to 0xFFFFFFFF whenever the per-entry + // trigger fired; it also set the EOCD records/size/offset to the + // placeholder values whenever EOCD64 was present. + "go126-store-5g": true, + "go126-deflate-zeros-5g": true, + "go126-store-4g-minus-1": true, + "go126-store-4g-minus-2": true, + "go126-store-exact-4g": true, + "go126-offset-past-4g": true, + "go126-offset-eq-4g": true, + "go126-store-just-under-4g": false, + } + + for _, path := range matches { + name := strings.TrimSuffix(filepath.Base(path), ".zsparse") + t.Run(name, func(t *testing.T) { + t.Parallel() + goldenSF, err := readSparseFile(path) + if err != nil { + t.Fatalf("read golden: %v", err) + } + goldenData, goldenBase := goldenSF.materializeTail(tailKeep) + golden, err := parseCD(goldenData, goldenBase) + if err != nil { + t.Fatalf("parse golden CD: %v", err) + } + + // Verify the production Reader can parse the full golden. + checkReaderMatchesSnapshot(t, "golden", goldenSF, golden) + + oursSF := reproduceCD(t, golden) + oursData, oursBase := oursSF.materializeTail(tailKeep) + got, err := parseCD(oursData, oursBase) + if err != nil { + t.Fatalf("parse reproduced CD: %v\nbytes:\n%s", err, hexDump(oursData)) + } + // Verify the production Reader can parse archive/zip's own + // output and gets the same view of the entries. + checkReaderMatchesSnapshot(t, "reproduced", oursSF, got) + + if expectedDiff[name] { + var cap captureReporter + compareCDSnapshots(&cap, golden, got) + if !cap.failed { + t.Errorf("expected this golden to fail equivalence, but it passed") + } else { + t.Logf("expected mismatch:\n%s", indent(cap.msg.String(), " ")) + } + return + } + compareCDSnapshots(t, golden, got) + }) + } +} + +// errReporter is the subset of [testing.TB] that [compareCDSnapshots] uses. +// The captureReporter implementation lets the test capture mismatches for +// expected-failure cases instead of propagating them to the outer t. +type errReporter interface { + Errorf(format string, args ...any) + Helper() +} + +type captureReporter struct { + failed bool + msg strings.Builder +} + +func (c *captureReporter) Errorf(format string, args ...any) { + c.failed = true + fmt.Fprintf(&c.msg, format+"\n", args...) +} + +func (c *captureReporter) Helper() {} + +// checkReaderMatchesSnapshot opens the archive backed by the sparseFile +// using the production [NewReader] and asserts that the entry list it +// returns matches the [cdSnapshot] (entry count, names, resolved 64-bit +// sizes). +func checkReaderMatchesSnapshot(t *testing.T, label string, f *sparseFile, snap *cdSnapshot) { + t.Helper() + zr, err := NewReader(f, f.Size) + if err != nil { + t.Fatalf("%s: NewReader: %v", label, err) + } + if g, w := len(zr.File), len(snap.Entries); g != w { + t.Errorf("%s: NewReader returned %d files, parseCD found %d", label, g, w) + return + } + for i, f := range zr.File { + want := &snap.Entries[i] + if f.Name != want.Name { + t.Errorf("%s entry %d: Name = %q, want %q", label, i, f.Name, want.Name) + } + if f.UncompressedSize64 != want.USize64 { + t.Errorf("%s entry %d %q: UncompressedSize64 = %d, want %d", label, i, want.Name, f.UncompressedSize64, want.USize64) + } + if f.CompressedSize64 != want.CSize64 { + t.Errorf("%s entry %d %q: CompressedSize64 = %d, want %d", label, i, want.Name, f.CompressedSize64, want.CSize64) + } + } +} + +// indent prefixes every line of s with prefix. +func indent(s, prefix string) string { + if s == "" { + return s + } + lines := strings.Split(strings.TrimRight(s, "\n"), "\n") + for i, l := range lines { + lines[i] = prefix + l + } + return strings.Join(lines, "\n") + "\n" +} + +// reproduceCD writes a zip archive with the same logical entries as golden +// into a [sparseBuffer] (which drops all-zero chunks, so pushing multi-GiB +// streams of zeros through the writer is essentially free) and returns the +// resulting [sparseFile]. +// +// For entries where compressed == uncompressed (Store, or other 1:1 cases) +// we drive the Writer through [Writer.CreateHeader] so that the data +// descriptor, offset accounting, and Close-time CD emission all exercise +// the production streaming path. The CRC32 hasher is replaced with +// [fakeHash32] to avoid hashing many GiB of zeros. +// +// For entries where compressed ≪ uncompressed (Method=Deflate over zeros), +// actually deflating multi-GiB streams at test time is prohibitively slow, +// so we fall back to [Writer.CreateRaw] and declare the sizes directly. +// The Central Directory output is identical either way. +func reproduceCD(t *testing.T, golden *cdSnapshot) *sparseFile { + t.Helper() + sb := &sparseBuffer{} + w := NewWriter(sb) + for i, e := range golden.Entries { + if e.CSize64 == e.USize64 { + fh := &FileHeader{Name: e.Name, Method: e.Method} + fw, err := w.CreateHeader(fh) + if err != nil { + t.Fatalf("CreateHeader[%d %q]: %v", i, e.Name, err) + } + fw.(*fileWriter).crc32 = fakeHash32{} + if _, err := io.CopyN(fw, zeros{}, int64(e.USize64)); err != nil { + t.Fatalf("CopyN[%d %q]: %v", i, e.Name, err) + } + continue + } + fh := &FileHeader{ + Name: e.Name, + Method: e.Method, + CompressedSize64: e.CSize64, + UncompressedSize64: e.USize64, + } + fw, err := w.CreateRaw(fh) + if err != nil { + t.Fatalf("CreateRaw[%d %q]: %v", i, e.Name, err) + } + if _, err := io.CopyN(fw, zeros{}, int64(e.CSize64)); err != nil { + t.Fatalf("CopyN[%d %q]: %v", i, e.Name, err) + } + } + if err := w.Close(); err != nil { + t.Fatalf("Close: %v", err) + } + return &sb.f +} + +// compareCDSnapshots asserts that got matches want on Zip64-relevant fields. +// +// Per-entry size fields (RawCSize, RawUSize, CSize64, USize64) are compared +// exactly — we feed them in from the golden when reproducing, so the writer +// has no excuse to disagree. Per-entry RawOffset and the EOCD records/size/ +// offset fields are compared only as placeholder-or-not: their absolute +// values depend on producer-specific LFH layout (Info-ZIP packs sizes into +// the LFH; archive/zip's streaming path uses a data descriptor; libarchive +// adds UT extras) and that's not what this test is pinning down. +func compareCDSnapshots(t errReporter, want, got *cdSnapshot) { + t.Helper() + if g, w := len(got.Entries), len(want.Entries); g != w { + t.Errorf("entry count = %d, want %d", g, w) + return + } + for i := range want.Entries { + we, ge := &want.Entries[i], &got.Entries[i] + // csize and usize come from the declared FileHeader values, so the + // raw 32-bit fields must match exactly (real value vs. placeholder + // choice and, when not placeholder, the value itself). + if we.RawCSize != ge.RawCSize { + t.Errorf("entry %d %q: RawCSize = %#08x, want %#08x", i, we.Name, ge.RawCSize, we.RawCSize) + } + if we.RawUSize != ge.RawUSize { + t.Errorf("entry %d %q: RawUSize = %#08x, want %#08x", i, we.Name, ge.RawUSize, we.RawUSize) + } + // Resolved csize/usize must match — we fed them in from the golden. + if we.CSize64 != ge.CSize64 { + t.Errorf("entry %d %q: CSize64 = %d, want %d", i, we.Name, ge.CSize64, we.CSize64) + } + if we.USize64 != ge.USize64 { + t.Errorf("entry %d %q: USize64 = %d, want %d", i, we.Name, ge.USize64, we.USize64) + } + // Offset is layout-dependent. Compare placeholder-or-not, not value. + if isPlaceholder32(we.RawOffset) != isPlaceholder32(ge.RawOffset) { + t.Errorf("entry %d %q: RawOffset placeholder = %#08x, want %#08x", i, we.Name, ge.RawOffset, we.RawOffset) + } + + // Zip64 sub-field presence/order, must match exactly. + if !slices.Equal(we.Z64ExtraFields, ge.Z64ExtraFields) { + t.Errorf("entry %d %q: Zip64 sub-field order = %v, want %v", i, we.Name, ge.Z64ExtraFields, we.Z64ExtraFields) + } + // ReaderVersion ≥ 45 whenever a Zip64 extra is present. + if len(we.Z64ExtraFields) > 0 && ge.ReaderVersion < zipVersion45 { + t.Errorf("entry %d %q: ReaderVersion = %d, want ≥ %d (Zip64 extra present)", i, we.Name, ge.ReaderVersion, zipVersion45) + } + } + + // EOCD: compare placeholder-or-not for each field. Exact values are + // layout-dependent. + if isPlaceholder16(want.EOCD.Records) != isPlaceholder16(got.EOCD.Records) { + t.Errorf("EOCD records placeholder = %#x, want %#x", got.EOCD.Records, want.EOCD.Records) + } + if isPlaceholder32(want.EOCD.Size) != isPlaceholder32(got.EOCD.Size) { + t.Errorf("EOCD size placeholder = %#x, want %#x", got.EOCD.Size, want.EOCD.Size) + } + if isPlaceholder32(want.EOCD.Offset) != isPlaceholder32(got.EOCD.Offset) { + t.Errorf("EOCD offset placeholder = %#x, want %#x", got.EOCD.Offset, want.EOCD.Offset) + } + + if got.HasEOCD64 != want.HasEOCD64 { + t.Errorf("EOCD64 present = %v, want %v", got.HasEOCD64, want.HasEOCD64) + } + if want.HasEOCD64 && got.HasEOCD64 { + if got.EOCD64.Records != want.EOCD64.Records { + t.Errorf("EOCD64 records = %d, want %d", got.EOCD64.Records, want.EOCD64.Records) + } + // EOCD64.Size and EOCD64.Offset are layout-dependent. + } +} + +func isPlaceholder32(v uint32) bool { return v == uint32max } +func isPlaceholder16(v uint16) bool { return v == uint16max } + +// CD snapshot types and parser + +// zip64SubID identifies one of the three sub-fields that may appear in a +// Zip64 extended-information extra field, in the spec-defined order. +type zip64SubID int + +const ( + z64USize zip64SubID = iota + 1 + z64CSize + z64Offset +) + +func (s zip64SubID) String() string { + switch s { + case z64USize: + return "usize" + case z64CSize: + return "csize" + case z64Offset: + return "offset" + } + return fmt.Sprintf("zip64SubID(%d)", int(s)) +} + +type cdEntry struct { + Name string + Method uint16 + ReaderVersion uint16 + + // Raw 32-bit fields from the CD record. A value of 0xFFFFFFFF indicates + // the real value is in the Zip64 extended-information extra field. + RawCSize uint32 + RawUSize uint32 + RawOffset uint32 + + // Resolved 64-bit values (from the 32-bit field if not a placeholder, + // otherwise from the Zip64 extra). + CSize64 uint64 + USize64 uint64 + Offset64 uint64 + + // Sub-fields present in the Zip64 extra, in the order they appear. + Z64ExtraFields []zip64SubID +} + +type eocdRec struct { + Records uint16 // 0xFFFF if placeholder + Size uint32 // 0xFFFFFFFF if placeholder + Offset uint32 // 0xFFFFFFFF if placeholder +} + +type eocd64Rec struct { + Records uint64 + Size uint64 + Offset uint64 +} + +type cdSnapshot struct { + Entries []cdEntry + EOCD eocdRec + HasEOCD64 bool + EOCD64 eocd64Rec +} + +var le = binary.LittleEndian + +// parseCD parses the Central Directory and EOCD records of a zip archive +// from its raw bytes. data must be the tail of the archive, with baseOffset +// indicating where data[0] sits in the original archive (0 for whole-archive +// input). +func parseCD(data []byte, baseOffset uint64) (*cdSnapshot, error) { + sigOff, err := findEOCD(data) + if err != nil { + return nil, err + } + snap := &cdSnapshot{} + snap.EOCD.Records = le.Uint16(data[sigOff+10:]) + snap.EOCD.Size = le.Uint32(data[sigOff+12:]) + snap.EOCD.Offset = le.Uint32(data[sigOff+16:]) + + dirOffset := uint64(snap.EOCD.Offset) + nRecords := uint64(snap.EOCD.Records) + + // toData converts an absolute archive offset to a data slice offset, + // returning false if it lies before our captured tail. + toData := func(absOff uint64) (uint64, bool) { + if absOff < baseOffset { + return 0, false + } + return absOff - baseOffset, true + } + + // Look for an EOCD64 locator immediately preceding the EOCD record. + if sigOff >= directory64LocLen { + locOff := sigOff - directory64LocLen + if le.Uint32(data[locOff:]) == directory64LocSignature { + eocd64Off := le.Uint64(data[locOff+8:]) + eocd64DataOff, ok := toData(eocd64Off) + if !ok { + return nil, fmt.Errorf("zip: EOCD64 at %#x before captured tail (base %#x)", eocd64Off, baseOffset) + } + if eocd64DataOff+directory64EndLen > uint64(len(data)) { + return nil, errors.New("zip: EOCD64 offset out of range") + } + if le.Uint32(data[eocd64DataOff:]) != directory64EndSignature { + return nil, errors.New("zip: EOCD64 signature mismatch") + } + snap.HasEOCD64 = true + snap.EOCD64.Records = le.Uint64(data[eocd64DataOff+32:]) + snap.EOCD64.Size = le.Uint64(data[eocd64DataOff+40:]) + snap.EOCD64.Offset = le.Uint64(data[eocd64DataOff+48:]) + dirOffset = snap.EOCD64.Offset + nRecords = snap.EOCD64.Records + } + } + + off, ok := toData(dirOffset) + if !ok { + return nil, fmt.Errorf("zip: CD at %#x before captured tail (base %#x)", dirOffset, baseOffset) + } + for i := uint64(0); i < nRecords; i++ { + if off+directoryHeaderLen > uint64(len(data)) { + return nil, fmt.Errorf("zip: CD entry %d out of range", i) + } + rec := data[off:] + if le.Uint32(rec) != directoryHeaderSignature { + return nil, fmt.Errorf("zip: bad CD signature at offset %d", off) + } + var e cdEntry + e.ReaderVersion = le.Uint16(rec[6:]) + e.Method = le.Uint16(rec[10:]) + e.RawCSize = le.Uint32(rec[20:]) + e.RawUSize = le.Uint32(rec[24:]) + nameLen := uint64(le.Uint16(rec[28:])) + extraLen := uint64(le.Uint16(rec[30:])) + commLen := uint64(le.Uint16(rec[32:])) + e.RawOffset = le.Uint32(rec[42:]) + + recLen := uint64(directoryHeaderLen) + nameLen + extraLen + commLen + if off+recLen > uint64(len(data)) { + return nil, fmt.Errorf("zip: CD entry %d truncated", i) + } + nameOff := off + directoryHeaderLen + extraOff := nameOff + nameLen + e.Name = string(data[nameOff:extraOff]) + extra := data[extraOff : extraOff+extraLen] + + e.CSize64 = uint64(e.RawCSize) + e.USize64 = uint64(e.RawUSize) + e.Offset64 = uint64(e.RawOffset) + + // Walk extra fields; consume the Zip64 sub-field if present. + // Per the spec and Info-ZIP convention, the Zip64 extra contains + // 8-byte values for exactly the size/offset fields whose 32-bit + // counterpart is 0xFFFFFFFF, in the order: USize, CSize, Offset. + for len(extra) >= 4 { + tag := le.Uint16(extra) + size := uint64(le.Uint16(extra[2:])) + if 4+size > uint64(len(extra)) { + break + } + field := extra[4 : 4+size] + extra = extra[4+size:] + if tag != zip64ExtraID { + continue + } + if e.RawUSize == uint32max && len(field) >= 8 { + e.USize64 = le.Uint64(field) + e.Z64ExtraFields = append(e.Z64ExtraFields, z64USize) + field = field[8:] + } + if e.RawCSize == uint32max && len(field) >= 8 { + e.CSize64 = le.Uint64(field) + e.Z64ExtraFields = append(e.Z64ExtraFields, z64CSize) + field = field[8:] + } + if e.RawOffset == uint32max && len(field) >= 8 { + e.Offset64 = le.Uint64(field) + e.Z64ExtraFields = append(e.Z64ExtraFields, z64Offset) + field = field[8:] + } + } + + snap.Entries = append(snap.Entries, e) + off += recLen + } + return snap, nil +} + +// findEOCD locates the EOCD record by scanning back from the end of data, +// matching both the signature and the trailing comment-length field. +func findEOCD(data []byte) (uint64, error) { + if len(data) < directoryEndLen { + return 0, errors.New("zip: too short for EOCD") + } + maxComment := uint16max + lo := len(data) - directoryEndLen + hi := lo + if hi > maxComment { + lo = hi - maxComment + } else { + lo = 0 + } + for i := hi; i >= lo; i-- { + if le.Uint32(data[i:]) != directoryEndSignature { + continue + } + cl := int(le.Uint16(data[i+20:])) + if i+directoryEndLen+cl == len(data) { + return uint64(i), nil + } + } + return 0, errors.New("zip: EOCD not found") +} + +// hexDump returns a short hex dump of data for failure messages. +func hexDump(data []byte) string { + if len(data) > 4096 { + data = data[len(data)-4096:] + } + var b strings.Builder + for i := 0; i < len(data); i += 16 { + end := min(i+16, len(data)) + fmt.Fprintf(&b, "%04x % x\n", i, data[i:end]) + } + return b.String() +} + +// TestZip64LFHBothPlaceholders covers the [Writer.CreateRaw] + no-data- +// descriptor path where the entry's uncompressed or compressed size exceeds +// 4 GiB. The Local File Header carries a Zip64 extra with both 8-byte +// USize64 and CSize64 sub-fields (matching Info-ZIP), so per APPNOTE 4.5.3 +// both 32-bit size fields in the LFH must be the 0xFFFFFFFF placeholder — +// even if only one of the sizes actually overflows. +func TestZip64LFHBothPlaceholders(t *testing.T) { + var buf bytes.Buffer + w := NewWriter(&buf) + fh := &FileHeader{ + Name: "x", + Method: Deflate, + CompressedSize64: 1024, + UncompressedSize64: 5 << 30, // > 4 GiB + } + fw, err := w.CreateRaw(fh) + if err != nil { + t.Fatal(err) + } + if _, err := io.CopyN(fw, zeros{}, int64(fh.CompressedSize64)); err != nil { + t.Fatal(err) + } + if err := w.Close(); err != nil { + t.Fatal(err) + } + + b := buf.Bytes() + if got := le.Uint32(b[14:18]); got != fh.CRC32 { + t.Errorf("LFH CRC32 = %#x, want %#x", got, fh.CRC32) + } + if got := le.Uint32(b[18:22]); got != uint32max { + t.Errorf("LFH CompressedSize = %#x, want %#x (placeholder)", got, uint32(uint32max)) + } + if got := le.Uint32(b[22:26]); got != uint32max { + t.Errorf("LFH UncompressedSize = %#x, want %#x (placeholder)", got, uint32(uint32max)) + } + + // The Zip64 LFH extra should carry both 64-bit sub-fields in + // USize64-then-CSize64 order. + nameLen := uint64(le.Uint16(b[26:28])) + extraLen := uint64(le.Uint16(b[28:30])) + if want := uint64(20); extraLen != want { + t.Fatalf("LFH extra length = %d, want %d", extraLen, want) + } + extra := b[30+nameLen : 30+nameLen+extraLen] + if tag := le.Uint16(extra[:2]); tag != zip64ExtraID { + t.Errorf("Zip64 extra tag = %#x, want %#x", tag, zip64ExtraID) + } + if dataLen := le.Uint16(extra[2:4]); dataLen != 16 { + t.Errorf("Zip64 extra data length = %d, want 16", dataLen) + } + if got := le.Uint64(extra[4:12]); got != fh.UncompressedSize64 { + t.Errorf("Zip64 USize64 = %d, want %d", got, fh.UncompressedSize64) + } + if got := le.Uint64(extra[12:20]); got != fh.CompressedSize64 { + t.Errorf("Zip64 CSize64 = %d, want %d", got, fh.CompressedSize64) + } +} diff --git a/src/archive/zip/zip_test.go b/src/archive/zip/zip_test.go index 5a6689a0eb1163..1f36b365ecbbbc 100644 --- a/src/archive/zip/zip_test.go +++ b/src/archive/zip/zip_test.go @@ -14,7 +14,7 @@ import ( "hash" "internal/testenv" "io" - "runtime" + "math/bits" "slices" "strings" "testing" @@ -494,12 +494,15 @@ func suffixIsZip64(t *testing.T, zip sizedReaderAt) bool { // Zip64 is required if the total size of the records is uint32max. func TestZip64LargeDirectory(t *testing.T) { - if runtime.GOARCH == "wasm" { - t.Skip("too slow on wasm") + if testenv.CPUIsSlow() { + t.Skip("too slow") } if testing.Short() { t.Skip("skipping in short mode") } + if bits.UintSize == 32 { + t.Skip("skipping on 32-bit platforms") + } t.Parallel() // gen returns a func that writes a zip with a wantLen bytes // of central directory. @@ -538,15 +541,30 @@ func TestZip64LargeDirectory(t *testing.T) { } t.Run("uint32max-1_NoZip64", func(t *testing.T) { t.Parallel() - if generatesZip64(t, gen(uint32max-1)) { + buf := new(rleBuffer) + w := NewWriter(buf) + gen(uint32max - 1)(w) + if suffixIsZip64(t, buf) { t.Error("unexpected zip64") } + if _, err := NewReader(buf, buf.Size()); err != nil { + t.Errorf("NewReader: %v", err) + } }) t.Run("uint32max_HasZip64", func(t *testing.T) { t.Parallel() - if !generatesZip64(t, gen(uint32max)) { + buf := new(rleBuffer) + w := NewWriter(buf) + gen(uint32max)(w) + if !suffixIsZip64(t, buf) { t.Error("expected zip64") } + // Round-trip through NewReader. With CD size exactly 0xFFFFFFFF, + // records well below 0xFFFF, and dirOffset == 0, the only EOCD + // field that holds the placeholder is directorySize. + if _, err := NewReader(buf, buf.Size()); err != nil { + t.Errorf("NewReader: %v", err) + } }) } diff --git a/src/bufio/bufio.go b/src/bufio/bufio.go index 141a9a1a2a2305..f9b762be8d4966 100644 --- a/src/bufio/bufio.go +++ b/src/bufio/bufio.go @@ -30,7 +30,7 @@ var ( // Reader implements buffering for an io.Reader object. // A new Reader is created by calling [NewReader] or [NewReaderSize]; -// alternatively the zero value of a Reader may be used after calling [Reset] +// alternatively the zero value of a Reader may be used after calling [Reader.Reset] // on it. type Reader struct { buf []byte diff --git a/src/builtin/builtin.go b/src/builtin/builtin.go index afa2a10f9091dc..be53077d9cb495 100644 --- a/src/builtin/builtin.go +++ b/src/builtin/builtin.go @@ -122,6 +122,10 @@ type Type int // invocation. type Type1 int +// TypeOrExpr is here for the purposes of documentation only. It is a stand-in +// for either a Go type or an expression. +type TypeOrExpr int + // IntegerType is here for the purposes of documentation only. It is a stand-in // for any integer type: int, uint, int8 etc. type IntegerType int @@ -220,10 +224,15 @@ func max[T cmp.Ordered](x T, y ...T) T // min will return NaN. func min[T cmp.Ordered](x T, y ...T) T -// The new built-in function allocates memory. The first argument is a type, -// not a value, and the value returned is a pointer to a newly -// allocated zero value of that type. -func new(Type) *Type +// The built-in function new allocates a new, initialized variable and returns +// a pointer to it. It accepts a single argument, which may be either a type +// or an expression. +// If the argument is a type T, then new(T) allocates a variable of type T +// initialized to its zero value. +// Otherwise, the argument is an expression x and new(x) allocates a variable +// of the type of x initialized to the value of x. If that value is an untyped +// constant, it is first implicitly converted to its default type. +func new(TypeOrExpr) *Type // The complex built-in function constructs a complex value from two // floating-point values. The real and imaginary parts must be of the same diff --git a/src/bytes/buffer.go b/src/bytes/buffer.go index 9684513942da88..03f17d624daa23 100644 --- a/src/bytes/buffer.go +++ b/src/bytes/buffer.go @@ -77,6 +77,18 @@ func (b *Buffer) String() string { return string(b.buf[b.off:]) } +// Peek returns the next n bytes without advancing the buffer. +// If Peek returns fewer than n bytes, it also returns [io.EOF]. +// The slice is only valid until the next call to a read or write method. +// The slice aliases the buffer content at least until the next buffer modification, +// so immediate changes to the slice will affect the result of future reads. +func (b *Buffer) Peek(n int) ([]byte, error) { + if b.Len() < n { + return b.buf[b.off:], io.EOF + } + return b.buf[b.off : b.off+n], nil +} + // empty reports whether the unread portion of the buffer is empty. func (b *Buffer) empty() bool { return len(b.buf) <= b.off } @@ -299,9 +311,9 @@ func (b *Buffer) WriteByte(c byte) error { } // WriteRune appends the UTF-8 encoding of Unicode code point r to the -// buffer, returning its length and an error, which is always nil but is -// included to match [bufio.Writer]'s WriteRune. The buffer is grown as needed; -// if it becomes too large, WriteRune will panic with [ErrTooLarge]. +// buffer, returning the number of bytes written and a nil error. The nil +// error is included to match [bufio.Writer]'s WriteRune. The buffer is grown +// as needed; if it becomes too large, WriteRune will panic with [ErrTooLarge]. func (b *Buffer) WriteRune(r rune) (n int, err error) { // Compare as uint32 to correctly handle negative runes. if uint32(r) < utf8.RuneSelf { diff --git a/src/bytes/buffer_test.go b/src/bytes/buffer_test.go index b46ba1204eb806..9c1ba0a838054f 100644 --- a/src/bytes/buffer_test.go +++ b/src/bytes/buffer_test.go @@ -531,6 +531,40 @@ func TestReadString(t *testing.T) { } } +var peekTests = []struct { + buffer string + skip int + n int + expected string + err error +}{ + {"", 0, 0, "", nil}, + {"aaa", 0, 3, "aaa", nil}, + {"foobar", 0, 2, "fo", nil}, + {"a", 0, 2, "a", io.EOF}, + {"helloworld", 4, 3, "owo", nil}, + {"helloworld", 5, 5, "world", nil}, + {"helloworld", 5, 6, "world", io.EOF}, + {"helloworld", 10, 1, "", io.EOF}, +} + +func TestPeek(t *testing.T) { + for _, test := range peekTests { + buf := NewBufferString(test.buffer) + buf.Next(test.skip) + bytes, err := buf.Peek(test.n) + if string(bytes) != test.expected { + t.Errorf("expected %q, got %q", test.expected, bytes) + } + if err != test.err { + t.Errorf("expected error %v, got %v", test.err, err) + } + if buf.Len() != len(test.buffer)-test.skip { + t.Errorf("bad length after peek: %d, want %d", buf.Len(), len(test.buffer)-test.skip) + } + } +} + func BenchmarkReadString(b *testing.B) { const n = 32 << 10 diff --git a/src/bytes/bytes.go b/src/bytes/bytes.go index 87183c01955829..b0daa5dfc41c20 100644 --- a/src/bytes/bytes.go +++ b/src/bytes/bytes.go @@ -89,6 +89,7 @@ func ContainsRune(b []byte, r rune) bool { } // ContainsFunc reports whether any of the UTF-8-encoded code points r within b satisfy f(r). +// It stops as soon as a call to f returns true. func ContainsFunc(b []byte, f func(rune) bool) bool { return IndexFunc(b, f) >= 0 } @@ -98,15 +99,6 @@ func IndexByte(b []byte, c byte) int { return bytealg.IndexByte(b, c) } -func indexBytePortable(s []byte, c byte) int { - for i, b := range s { - if b == c { - return i - } - } - return -1 -} - // LastIndex returns the index of the last instance of sep in s, or -1 if sep is not present in s. func LastIndex(s, sep []byte) int { n := len(sep) @@ -246,7 +238,7 @@ func IndexAny(s []byte, chars string) int { } return IndexRune(s, r) } - if len(s) > 8 { + if shouldUseASCIISet(len(s)) { if as, isASCII := makeASCIISet(chars); isASCII { for i, c := range s { if as.contains(c) { @@ -301,7 +293,7 @@ func LastIndexAny(s []byte, chars string) int { // Avoid scanning all of s. return -1 } - if len(s) > 8 { + if shouldUseASCIISet(len(s)) { if as, isASCII := makeASCIISet(chars); isASCII { for i := len(s) - 1; i >= 0; i-- { if as.contains(s[i]) { @@ -388,9 +380,7 @@ func genSplit(s, sep []byte, sepSave, n int) [][]byte { if n < 0 { n = Count(s, sep) + 1 } - if n > len(s)+1 { - n = len(s) + 1 - } + n = min(n, len(s)+1) a := make([][]byte, n) n-- @@ -935,15 +925,22 @@ func lastIndexFunc(s []byte, f func(r rune) bool, truth bool) int { return -1 } -// asciiSet is a 32-byte value, where each bit represents the presence of a -// given ASCII character in the set. The 128-bits of the lower 16 bytes, -// starting with the least-significant bit of the lowest word to the -// most-significant bit of the highest word, map to the full range of all -// 128 ASCII characters. The 128-bits of the upper 16 bytes will be zeroed, -// ensuring that any non-ASCII character will be reported as not in the set. -// This allocates a total of 32 bytes even though the upper half -// is unused to avoid bounds checks in asciiSet.contains. -type asciiSet [8]uint32 +// asciiSet is a 256-byte lookup table for fast ASCII character membership testing. +// Each element corresponds to an ASCII character value, with true indicating the +// character is in the set. Using bool instead of byte allows the compiler to +// eliminate the comparison instruction, as bool values are guaranteed to be 0 or 1. +// +// The full 256-element table is used rather than a 128-element table to avoid +// additional operations in the lookup path. Alternative approaches were tested: +// - [128]bool with explicit bounds check (if c >= 128): introduces branches +// that cause pipeline stalls, resulting in ~70% slower performance +// - [128]bool with masking (c&0x7f): eliminates bounds checks but the AND +// operation still costs ~10% performance compared to direct indexing +// +// The 256-element array allows direct indexing with no bounds checks, no branches, +// and no masking operations, providing optimal performance. The additional 128 bytes +// of memory is a worthwhile tradeoff for the simpler, faster code. +type asciiSet [256]bool // makeASCIISet creates a set of ASCII characters and reports whether all // characters in chars are ASCII. @@ -953,14 +950,24 @@ func makeASCIISet(chars string) (as asciiSet, ok bool) { if c >= utf8.RuneSelf { return as, false } - as[c/32] |= 1 << (c % 32) + as[c] = true } return as, true } // contains reports whether c is inside the set. func (as *asciiSet) contains(c byte) bool { - return (as[c/32] & (1 << (c % 32))) != 0 + return as[c] +} + +// shouldUseASCIISet returns whether to use the lookup table optimization. +// The threshold of 8 bytes balances initialization cost against per-byte +// search cost, performing well across all charset sizes. +// +// More complex heuristics (e.g., different thresholds per charset size) +// add branching overhead that eats away any theoretical improvements. +func shouldUseASCIISet(bufLen int) bool { + return bufLen > 8 } // containsRune is a simplified version of strings.ContainsRune @@ -1413,3 +1420,16 @@ func CutSuffix(s, suffix []byte) (before []byte, found bool) { } return s[:len(s)-len(suffix)], true } + +// CutLast slices s around the last instance of sep, +// returning the text before and after sep. +// The found result reports whether sep appears in s. +// If sep does not appear in s, CutLast returns s, nil, false. +// +// CutLast returns slices of the original slice s, not copies. +func CutLast(s, sep []byte) (before, after []byte, found bool) { + if i := LastIndex(s, sep); i >= 0 { + return s[:i], s[i+len(sep):], true + } + return s, nil, false +} diff --git a/src/bytes/bytes_test.go b/src/bytes/bytes_test.go index f18915c879e097..20d333217e81e2 100644 --- a/src/bytes/bytes_test.go +++ b/src/bytes/bytes_test.go @@ -323,10 +323,6 @@ func TestIndexByte(t *testing.T) { if pos != tt.i { t.Errorf(`IndexByte(%q, '%c') = %v`, tt.a, b, pos) } - posp := IndexBytePortable(a, b) - if posp != tt.i { - t.Errorf(`indexBytePortable(%q, '%c') = %v`, tt.a, b, posp) - } } } @@ -617,8 +613,18 @@ func BenchmarkIndexByte(b *testing.B) { benchBytes(b, indexSizes, bmIndexByte(IndexByte)) } +// indexBytePortable use as the baseline for performance comparisons. +func indexBytePortable(s []byte, c byte) int { + for i, b := range s { + if b == c { + return i + } + } + return -1 +} + func BenchmarkIndexBytePortable(b *testing.B) { - benchBytes(b, indexSizes, bmIndexByte(IndexBytePortable)) + benchBytes(b, indexSizes, bmIndexByte(indexBytePortable)) } func bmIndexByte(index func([]byte, byte) int) func(b *testing.B, n int) { @@ -961,7 +967,7 @@ func TestSplit(t *testing.T) { if tt.n < 0 { b := sliceOfString(Split([]byte(tt.s), []byte(tt.sep))) if !slices.Equal(result, b) { - t.Errorf("Split disagrees withSplitN(%q, %q, %d) = %v; want %v", tt.s, tt.sep, tt.n, b, a) + t.Errorf("Split disagrees with SplitN(%q, %q, %d) = %v; want %v", tt.s, tt.sep, tt.n, b, a) } } if len(a) > 0 { @@ -1023,7 +1029,7 @@ func TestSplitAfter(t *testing.T) { if tt.n < 0 { b := sliceOfString(SplitAfter([]byte(tt.s), []byte(tt.sep))) if !slices.Equal(result, b) { - t.Errorf("SplitAfter disagrees withSplitAfterN(%q, %q, %d) = %v; want %v", tt.s, tt.sep, tt.n, b, a) + t.Errorf("SplitAfter disagrees with SplitAfterN(%q, %q, %d) = %v; want %v", tt.s, tt.sep, tt.n, b, a) } } } @@ -1224,7 +1230,7 @@ func TestMap(t *testing.T) { // Run a couple of awful growth/shrinkage tests a := tenRunes('a') - // 1. Grow. This triggers two reallocations in Map. + // 1. Grow. This triggers two reallocations in Map. maxRune := func(r rune) rune { return unicode.MaxRune } m := Map(maxRune, []byte(a)) expect := tenRunes(unicode.MaxRune) @@ -1970,6 +1976,27 @@ func TestCut(t *testing.T) { } } +func TestCutLast(t *testing.T) { + tests := []struct { + s, sep string + before, after string + found bool + }{ + {"a/b/c", "/", "a/b", "c", true}, + {"a//b//c", "//", "a//b", "c", true}, + {"abc", "/", "abc", "", false}, + {"abc", "", "abc", "", true}, + {"", "", "", "", true}, + {"/abc", "/", "", "abc", true}, + {"abc/", "/", "abc", "", true}, + } + for _, tt := range tests { + if before, after, found := CutLast([]byte(tt.s), []byte(tt.sep)); string(before) != tt.before || string(after) != tt.after || found != tt.found { + t.Errorf("CutLast(%q, %q) = %q, %q, %v; want %q, %q, %v", tt.s, tt.sep, before, after, found, tt.before, tt.after, tt.found) + } + } +} + var cutPrefixTests = []struct { s, sep string after string diff --git a/src/bytes/export_test.go b/src/bytes/export_test.go deleted file mode 100644 index b65428d9ce8489..00000000000000 --- a/src/bytes/export_test.go +++ /dev/null @@ -1,8 +0,0 @@ -// Copyright 2009 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -package bytes - -// Export func for testing -var IndexBytePortable = indexBytePortable diff --git a/src/cmd/api/api_test.go b/src/cmd/api/api_test.go index 98ebf168ef3949..784bdb74e428e0 100644 --- a/src/cmd/api/api_test.go +++ b/src/cmd/api/api_test.go @@ -232,7 +232,6 @@ var warmupCache = sync.OnceFunc(func() { // Warm up the import cache in parallel. var wg sync.WaitGroup for _, context := range contexts { - context := context wg.Add(1) go func() { defer wg.Done() diff --git a/src/cmd/api/main_test.go b/src/cmd/api/main_test.go index ed366be4e77267..f217319f1579a0 100644 --- a/src/cmd/api/main_test.go +++ b/src/cmd/api/main_test.go @@ -17,6 +17,7 @@ import ( "go/parser" "go/token" "go/types" + "internal/buildcfg" "internal/testenv" "io" "log" @@ -116,12 +117,20 @@ func Check(t *testing.T) { for _, c := range contexts { c.Compiler = build.Default.Compiler + + // Include baseline goexperiment.* tool tags. + baseline, err := buildcfg.ParseGOEXPERIMENT(c.GOOS, c.GOARCH, "") + if err != nil { + t.Fatal(err) + } + for _, exp := range baseline.Enabled() { + c.ToolTags = append(c.ToolTags, "goexperiment."+exp) + } } walkers := make([]*Walker, len(contexts)) var wg sync.WaitGroup for i, context := range contexts { - i, context := i, context wg.Add(1) go func() { defer wg.Done() @@ -390,7 +399,7 @@ func (w *Walker) parseFile(dir, file string) (*ast.File, error) { return f, nil } - f, err := parser.ParseFile(fset, filename, nil, parser.ParseComments) + f, err := parser.ParseFile(fset, filename, nil, parser.ParseComments|parser.SkipObjectResolution) if err != nil { return nil, err } @@ -1154,14 +1163,15 @@ func needApproval(filename string) bool { func (w *Walker) collectDeprecated() { isDeprecated := func(doc *ast.CommentGroup) bool { - if doc != nil { - for _, c := range doc.List { - if strings.HasPrefix(c.Text, "// Deprecated:") { - return true - } - } - } - return false + // Look for "Deprecated:" (case-sensitive) at the beginning (not middle) of a paragraph. + // It's typically found in the last paragraph, but it's not required to be the last one. + // The colon is typically followed by a space, but it can also be a newline, as was the + // case at https://go.dev/pkg/go/build#AllowBinary for example. + // + // See https://go.dev/wiki/Deprecated and https://go.dev/ref/mod#go-mod-file-module-deprecation. + text := doc.Text() + return strings.HasPrefix(text, "Deprecated: ") || strings.Contains(text, "\n\nDeprecated: ") || + strings.HasPrefix(text, "Deprecated:\n") || strings.Contains(text, "\n\nDeprecated:\n") } w.deprecated = make(map[token.Pos]bool) diff --git a/src/cmd/api/testdata/src/pkg/issue79145/golden.txt b/src/cmd/api/testdata/src/pkg/issue79145/golden.txt new file mode 100644 index 00000000000000..a62e6b70018a09 --- /dev/null +++ b/src/cmd/api/testdata/src/pkg/issue79145/golden.txt @@ -0,0 +1,5 @@ +pkg issue79145, const Tau = 6.28319 // 314159265358979323846264338327950288419716939937510582097494459/50000000000000000000000000000000000000000000000000000000000000 +pkg issue79145, const Tau ideal-float +pkg issue79145, const Old //deprecated +pkg issue79145, const Old = true +pkg issue79145, const Old ideal-bool diff --git a/src/cmd/api/testdata/src/pkg/issue79145/issue79145.go b/src/cmd/api/testdata/src/pkg/issue79145/issue79145.go new file mode 100644 index 00000000000000..bf6e5386e27fc6 --- /dev/null +++ b/src/cmd/api/testdata/src/pkg/issue79145/issue79145.go @@ -0,0 +1,14 @@ +package issue79145 + +// Tau is the constant τ, which equals to 6.283185... or 2π. Tau is not +// Deprecated: please find more information at https://oeis.org/A019692. +const Tau = 2 * pi + +const pi = 3.14159265358979323846264338327950288419716939937510582097494459 // https://oeis.org/A000796; like math.Pi + +/* +Old is something old. + +Deprecated: Use New instead. +*/ +const Old = true diff --git a/src/cmd/asm/internal/arch/arch.go b/src/cmd/asm/internal/arch/arch.go index 8481a8f378f2cb..dd955bd3a87b24 100644 --- a/src/cmd/asm/internal/arch/arch.go +++ b/src/cmd/asm/internal/arch/arch.go @@ -92,7 +92,8 @@ func jumpX86(word string) bool { func jumpRISCV(word string) bool { switch word { case "BEQ", "BEQZ", "BGE", "BGEU", "BGEZ", "BGT", "BGTU", "BGTZ", "BLE", "BLEU", "BLEZ", - "BLT", "BLTU", "BLTZ", "BNE", "BNEZ", "CALL", "JAL", "JALR", "JMP": + "BLT", "BLTU", "BLTZ", "BNE", "BNEZ", "CALL", "CBEQZ", "CBNEZ", "CJ", "CJALR", "CJR", + "JAL", "JALR", "JMP": return true } return false @@ -274,6 +275,15 @@ func archArm64() *Arch { for i := arm64.REG_V0; i <= arm64.REG_V31; i++ { register[obj.Rconv(i)] = int16(i) } + for i := arm64.REG_Z0; i <= arm64.REG_Z31; i++ { + register[obj.Rconv(i)] = int16(i) + } + for i := arm64.REG_P0; i <= arm64.REG_P15; i++ { + register[obj.Rconv(i)] = int16(i) + } + for i := arm64.REG_PN0; i <= arm64.REG_PN15; i++ { + register[obj.Rconv(i)] = int16(i) + } // System registers. for i := 0; i < len(arm64.SystemReg); i++ { @@ -291,9 +301,12 @@ func archArm64() *Arch { delete(register, "R28") register["g"] = arm64.REG_R28 registerPrefix := map[string]bool{ - "F": true, - "R": true, - "V": true, + "F": true, + "R": true, + "V": true, + "Z": true, + "P": true, + "PN": true, } instructions := make(map[string]obj.As) diff --git a/src/cmd/asm/internal/arch/arm64.go b/src/cmd/asm/internal/arch/arm64.go index d562e5907d6fc1..24020a336b7536 100644 --- a/src/cmd/asm/internal/arch/arm64.go +++ b/src/cmd/asm/internal/arch/arm64.go @@ -182,6 +182,18 @@ func arm64RegisterNumber(name string, n int16) (int16, bool) { if 0 <= n && n <= 31 { return arm64.REG_V0 + n, true } + case "Z": + if 0 <= n && n <= 31 { + return arm64.REG_Z0 + n, true + } + case "P": + if 0 <= n && n <= 15 { + return arm64.REG_P0 + n, true + } + case "PN": + if 0 <= n && n <= 15 { + return arm64.REG_PN0 + n, true + } } return 0, false } @@ -197,9 +209,17 @@ func ARM64RegisterShift(reg, op, count int16) (int64, error) { // ARM64RegisterArrangement constructs an ARM64 vector register arrangement. func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) { - var curQ, curSize uint16 - if name[0] != 'V' { - return 0, errors.New("expect V0 through V31; found: " + name) + var curQ, curSize, prefix uint16 + if name[0] != 'V' && name[0] != 'Z' && name[0] != 'P' { + return 0, errors.New("expect V0-V31, Z0-Z31, or P0-P15; found: " + name) + } + switch name[0] { + case 'V': + prefix = 0 + case 'Z': + prefix = 1 + case 'P': + prefix = 2 } if reg < 0 { return 0, errors.New("invalid register number: " + name) @@ -229,30 +249,23 @@ func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) { case "D2": curSize = 3 curQ = 1 + case "B": + curSize = 1 + curQ = 2 + case "H": + curSize = 2 + curQ = 2 + case "S": + curSize = 3 + curQ = 2 + case "D": + curSize = 1 + curQ = 3 + case "Q": + curSize = 2 + curQ = 3 default: return 0, errors.New("invalid arrangement in ARM64 register list") } - return (int64(curQ) & 1 << 30) | (int64(curSize&3) << 10), nil -} - -// ARM64RegisterListOffset generates offset encoding according to AArch64 specification. -func ARM64RegisterListOffset(firstReg, regCnt int, arrangement int64) (int64, error) { - offset := int64(firstReg) - switch regCnt { - case 1: - offset |= 0x7 << 12 - case 2: - offset |= 0xa << 12 - case 3: - offset |= 0x6 << 12 - case 4: - offset |= 0x2 << 12 - default: - return 0, errors.New("invalid register numbers in ARM64 register list") - } - offset |= arrangement - // arm64 uses the 60th bit to differentiate from other archs - // For more details, refer to: obj/arm64/list7.go - offset |= 1 << 60 - return offset, nil + return (int64(prefix) << 32) | (int64(curQ) & 3 << 30) | (int64(curSize&3) << 10), nil } diff --git a/src/cmd/asm/internal/arch/loong64.go b/src/cmd/asm/internal/arch/loong64.go index 21263d34331513..4f62f5210b5740 100644 --- a/src/cmd/asm/internal/arch/loong64.go +++ b/src/cmd/asm/internal/arch/loong64.go @@ -75,48 +75,51 @@ var loong64LasxArngExtMap = map[string]int16{ // Loong64RegisterExtension constructs an Loong64 register with extension or arrangement. func Loong64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error { var ok bool - var arng_type int16 - var simd_type int16 + var arngType int16 + var simdType int16 + var simdReg int16 switch { case reg >= loong64.REG_V0 && reg <= loong64.REG_V31: - simd_type = loong64.LSX + simdType = loong64.LSX + simdReg = reg - loong64.REG_V0 case reg >= loong64.REG_X0 && reg <= loong64.REG_X31: - simd_type = loong64.LASX + simdType = loong64.LASX + simdReg = reg - loong64.REG_X0 default: return errors.New("Loong64 extension: invalid LSX/LASX register: " + fmt.Sprintf("%d", reg)) } if isIndex { - arng_type, ok = loong64ElemExtMap[ext] + arngType, ok = loong64ElemExtMap[ext] if !ok { return errors.New("Loong64 extension: invalid LSX/LASX arrangement type: " + ext) } a.Reg = loong64.REG_ELEM - a.Reg += ((reg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT) - a.Reg += ((arng_type & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT) - a.Reg += ((simd_type & loong64.EXT_SIMDTYPE_MASK) << loong64.EXT_SIMDTYPE_SHIFT) + a.Reg += ((simdReg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT) + a.Reg += ((arngType & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT) + a.Reg += ((simdType & loong64.EXT_SIMDTYPE_MASK) << loong64.EXT_SIMDTYPE_SHIFT) a.Index = num } else { - switch simd_type { + switch simdType { case loong64.LSX: - arng_type, ok = loong64LsxArngExtMap[ext] + arngType, ok = loong64LsxArngExtMap[ext] if !ok { return errors.New("Loong64 extension: invalid LSX arrangement type: " + ext) } case loong64.LASX: - arng_type, ok = loong64LasxArngExtMap[ext] + arngType, ok = loong64LasxArngExtMap[ext] if !ok { return errors.New("Loong64 extension: invalid LASX arrangement type: " + ext) } } a.Reg = loong64.REG_ARNG - a.Reg += ((reg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT) - a.Reg += ((arng_type & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT) - a.Reg += ((simd_type & loong64.EXT_SIMDTYPE_MASK) << loong64.EXT_SIMDTYPE_SHIFT) + a.Reg += ((simdReg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT) + a.Reg += ((arngType & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT) + a.Reg += ((simdType & loong64.EXT_SIMDTYPE_MASK) << loong64.EXT_SIMDTYPE_SHIFT) } return nil diff --git a/src/cmd/asm/internal/arch/riscv64.go b/src/cmd/asm/internal/arch/riscv64.go index 891d2be0e5cf20..b7ee8c27cc0bb9 100644 --- a/src/cmd/asm/internal/arch/riscv64.go +++ b/src/cmd/asm/internal/arch/riscv64.go @@ -47,6 +47,22 @@ func IsRISCV64CSRO(op obj.As) (imm bool, ok bool) { return } +// IsRISCV64PseudoCSRO reports whether the op is a pseudo instruction +// that uses CSR symbolic names, whether that instruction expects a register +// or an immediate source operand and what the expected index of the operand +// containing the CSR name should be. +func IsRISCV64PseudoCSRO(op obj.As) (imm bool, index int, ok bool) { + switch op { + case riscv.ACSRCI, riscv.ACSRSI, riscv.ACSRWI: + imm, index, ok = true, 1, true + case riscv.ACSRC, riscv.ACSRS, riscv.ACSRW: + imm, index, ok = false, 1, true + case riscv.ACSRR: + imm, index, ok = false, 0, true + } + return +} + var riscv64SpecialOperand map[string]riscv.SpecialOperand // RISCV64SpecialOperand returns the internal representation of a special operand. @@ -69,6 +85,10 @@ func RISCV64SpecialOperand(name string) riscv.SpecialOperand { } riscv64SpecialOperand[csrName] = riscv.SpecialOperand(int(csrCode) + int(riscv.SPOP_CSR_BEGIN)) } + // Add the FENCE operands + for opd := riscv.SPOP_FENCE_BEGIN + 1; opd < riscv.SPOP_FENCE_END; opd++ { + riscv64SpecialOperand[opd.String()] = opd + } } if opd, ok := riscv64SpecialOperand[name]; ok { return opd diff --git a/src/cmd/asm/internal/asm/asm.go b/src/cmd/asm/internal/asm/asm.go index 0f75edf4e5d254..731fb26eb638c9 100644 --- a/src/cmd/asm/internal/asm/asm.go +++ b/src/cmd/asm/internal/asm/asm.go @@ -15,6 +15,7 @@ import ( "cmd/asm/internal/flags" "cmd/asm/internal/lex" "cmd/internal/obj" + "cmd/internal/obj/arm64" "cmd/internal/obj/ppc64" "cmd/internal/obj/riscv" "cmd/internal/obj/x86" @@ -593,6 +594,10 @@ func (p *Parser) branch(addr *obj.Addr, target *obj.Prog) { addr.Val = target } +func isARM64SVE(op obj.As) bool { + return op > arm64.ASVESTART +} + // asmInstruction assembles an instruction. // MOVW R9, (R10) func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) { @@ -660,6 +665,25 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) { prog.AddRestSource(a[1]) break } + } else if p.arch.Family == sys.RISCV64 { + // RISCV64 pseudo instructions that reference CSRs with symbolic names. + if isImm, specialIndex, ok := arch.IsRISCV64PseudoCSRO(op); ok { + if a[0].Type != obj.TYPE_CONST && isImm { + p.errorf("invalid value for first operand to %s instruction, must be a 5 bit unsigned immediate", op) + return + } + if a[specialIndex].Type != obj.TYPE_SPECIAL { + p.errorf("invalid value for first or second operand to %s instruction, must be a CSR name", op) + return + } + prog.AddRestSourceArgs([]obj.Addr{a[specialIndex]}) + if specialIndex == 0 { + prog.To = a[1] + } else { + prog.From = a[0] + } + break + } } prog.From = a[0] prog.To = a[1] @@ -741,6 +765,11 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) { // For ARM64 CASP-like instructions, its 2nd destination operand is register pair(Rt, Rt+1) that can // not fit into prog.RegTo2, so save it to the prog.RestArgs. prog.AddRestDest(a[2]) + case isARM64SVE(op): + // SVE instructions, see arm64/goops_gen.go + prog.From = a[0] + prog.AddRestSource(a[1]) + prog.To = a[2] default: prog.From = a[0] prog.Reg = p.getRegister(prog, op, &a[1]) @@ -843,6 +872,13 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) { break } if p.arch.Family == sys.ARM64 { + if isARM64SVE(op) { + // SVE instructions, see arm64/goops_gen.go + prog.From = a[0] + prog.AddRestSourceArgs([]obj.Addr{a[1], a[2]}) + prog.To = a[3] + break + } prog.From = a[0] prog.Reg = p.getRegister(prog, op, &a[1]) prog.AddRestSource(a[2]) @@ -891,6 +927,13 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) { p.errorf("can't handle %s instruction with 4 operands", op) return case 5: + if p.arch.Family == sys.ARM64 && isARM64SVE(op) { + // SVE instructions, see arm64/goops_gen.go + prog.From = a[0] + prog.AddRestSourceArgs([]obj.Addr{a[1], a[2], a[3]}) + prog.To = a[4] + break + } if p.arch.Family == sys.PPC64 { prog.From = a[0] // Second arg is always a register type on ppc64. @@ -914,6 +957,13 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) { p.errorf("can't handle %s instruction with 5 operands", op) return case 6: + if p.arch.Family == sys.ARM64 && isARM64SVE(op) { + // SVE instructions, see arm64/goops_gen.go + prog.From = a[0] + prog.AddRestSourceArgs([]obj.Addr{a[1], a[2], a[3], a[4]}) + prog.To = a[5] + break + } if p.arch.Family == sys.ARM && arch.IsARMMRC(op) { // Strange special case: MCR, MRC. prog.To.Type = obj.TYPE_CONST diff --git a/src/cmd/asm/internal/asm/endtoend_test.go b/src/cmd/asm/internal/asm/endtoend_test.go index afaf02815f94a2..e2f23ff61240a0 100644 --- a/src/cmd/asm/internal/asm/endtoend_test.go +++ b/src/cmd/asm/internal/asm/endtoend_test.go @@ -38,7 +38,7 @@ func testEndToEnd(t *testing.T, goarch, file string) { ctxt.IsAsm = true defer ctxt.Bso.Flush() failed := false - ctxt.DiagFunc = func(format string, args ...interface{}) { + ctxt.DiagFunc = func(format string, args ...any) { failed = true t.Errorf(format, args...) } @@ -193,12 +193,17 @@ Diff: top := pList.Firstpc var text *obj.LSym ok = true - ctxt.DiagFunc = func(format string, args ...interface{}) { + ctxt.DiagFunc = func(format string, args ...any) { t.Errorf(format, args...) ok = false } obj.Flushplist(ctxt, pList, nil) + if !ok { + // If we've encountered errors, the output is unlikely to be sane. + t.FailNow() + } + for p := top; p != nil; p = p.Link { if p.As == obj.ATEXT { text = p.From.Sym @@ -294,7 +299,7 @@ func testErrors(t *testing.T, goarch, file string, flags ...string) { failed := false var errBuf bytes.Buffer parser.errorWriter = &errBuf - ctxt.DiagFunc = func(format string, args ...interface{}) { + ctxt.DiagFunc = func(format string, args ...any) { failed = true s := fmt.Sprintf(format, args...) if !strings.HasSuffix(s, "\n") { @@ -409,6 +414,20 @@ func TestARM64Encoder(t *testing.T) { testEndToEnd(t, "arm64", "arm64enc") } +func TestARM64SVEEncoder(t *testing.T) { + if !buildcfg.Experiment.SIMD { + t.Skip("test requires GOEXPERIMENT=simd") + } + testEndToEnd(t, "arm64", "arm64sveenc") +} + +func TestARM64SVEErrors(t *testing.T) { + if !buildcfg.Experiment.SIMD { + t.Skip("test requires GOEXPERIMENT=simd") + } + testErrors(t, "arm64", "arm64sveerror") +} + func TestARM64Errors(t *testing.T) { testErrors(t, "arm64", "arm64error") } @@ -467,6 +486,7 @@ func TestLOONG64Encoder(t *testing.T) { testEndToEnd(t, "loong64", "loong64enc3") testEndToEnd(t, "loong64", "loong64enc4") testEndToEnd(t, "loong64", "loong64enc5") + testEndToEnd(t, "loong64", "loong64enc6") testEndToEnd(t, "loong64", "loong64") } @@ -485,16 +505,35 @@ func TestPPC64EndToEnd(t *testing.T) { } } -func TestRISCVEndToEnd(t *testing.T) { - testEndToEnd(t, "riscv64", "riscv64") +func testRISCV64AllProfiles(t *testing.T, testFn func(t *testing.T)) { + t.Helper() + + defer func(orig int) { buildcfg.GORISCV64 = orig }(buildcfg.GORISCV64) + + for _, goriscv64 := range []int{20, 22, 23} { + t.Run(fmt.Sprintf("rva%vu64", goriscv64), func(t *testing.T) { + buildcfg.GORISCV64 = goriscv64 + testFn(t) + }) + } +} + +func TestRISCV64EndToEnd(t *testing.T) { + testRISCV64AllProfiles(t, func(t *testing.T) { + testEndToEnd(t, "riscv64", "riscv64") + }) } -func TestRISCVErrors(t *testing.T) { - testErrors(t, "riscv64", "riscv64error") +func TestRISCV64Errors(t *testing.T) { + testRISCV64AllProfiles(t, func(t *testing.T) { + testErrors(t, "riscv64", "riscv64error") + }) } -func TestRISCVValidation(t *testing.T) { - testErrors(t, "riscv64", "riscv64validation") +func TestRISCV64Validation(t *testing.T) { + testRISCV64AllProfiles(t, func(t *testing.T) { + testErrors(t, "riscv64", "riscv64validation") + }) } func TestS390XEndToEnd(t *testing.T) { diff --git a/src/cmd/asm/internal/asm/parse.go b/src/cmd/asm/internal/asm/parse.go index 545f6c7553351b..bf69f9d1bd7083 100644 --- a/src/cmd/asm/internal/asm/parse.go +++ b/src/cmd/asm/internal/asm/parse.go @@ -78,7 +78,7 @@ func NewParser(ctxt *obj.Link, ar *arch.Arch, lexer lex.TokenReader) *Parser { // and turn it into a recoverable panic. var panicOnError bool -func (p *Parser) errorf(format string, args ...interface{}) { +func (p *Parser) errorf(format string, args ...any) { if panicOnError { panic(fmt.Errorf(format, args...)) } @@ -90,7 +90,7 @@ func (p *Parser) errorf(format string, args ...interface{}) { if p.lex != nil { // Put file and line information on head of message. format = "%s:%d: " + format + "\n" - args = append([]interface{}{p.lex.File(), p.lineNum}, args...) + args = append([]any{p.lex.File(), p.lineNum}, args...) } fmt.Fprintf(p.errorWriter, format, args...) p.errorCount++ @@ -423,6 +423,70 @@ func (p *Parser) operand(a *obj.Addr) { } } + // Detect AC_PREGSEL operand syntax: [selreg, $idximm](preg.T2) + if tok.ScanToken == '[' && p.arch.Family == sys.ARM64 { + pos := p.inputPos + if pos+5 < len(p.input) && p.input[pos].ScanToken == scanner.Ident && + p.input[pos+1].ScanToken == ',' && p.input[pos+2].ScanToken == '$' && + p.input[pos+3].ScanToken == scanner.Int && p.input[pos+4].ScanToken == ']' && + p.input[pos+5].ScanToken == '(' { + + selregStr := p.input[pos].String() + immStr := p.input[pos+3].String() + + pos += 6 // past '(' + if pos < len(p.input) && p.input[pos].ScanToken == scanner.Ident { + pregStr := p.input[pos].String() + pos++ + ext := "" + if pos < len(p.input) && p.input[pos].ScanToken == '.' { + pos++ + if pos < len(p.input) && p.input[pos].ScanToken == scanner.Ident { + ext = p.input[pos].String() + pos++ + } + } + if pos < len(p.input) && p.input[pos].ScanToken == ')' { + // Matches AC_PREGSEL syntax! + p.inputPos = pos + 1 // consume the parsed tokens + + // Encode components + selreg, ok1 := p.registerReference(selregStr) + preg, ok2 := p.registerReference(pregStr) + idximm := int64(p.atoi(immStr)) + + if !ok1 || !ok2 { + p.errorf("invalid registers in pregsel operand") + return + } + + var arng2 int + switch ext { + case "B": + arng2 = arm64.ARNG_B + case "H": + arng2 = arm64.ARNG_H + case "S": + arng2 = arm64.ARNG_S + case "D": + arng2 = arm64.ARNG_D + case "Q": + arng2 = arm64.ARNG_Q + default: + p.errorf("invalid P register arrangement: %s", ext) + return + } + + // Pack values into a.Offset + a.Type = obj.TYPE_REG + a.Offset = int64(preg&31) | int64((arng2&15)<<5) | int64((selreg&31)<<9) | (idximm << 14) | (int64(1) << 62) + p.expectOperandEnd() + return + } + } + } + } + // Special register list syntax for arm: [R1,R3-R7] if tok.ScanToken == '[' { if prefix != 0 { @@ -472,6 +536,30 @@ func (p *Parser) operand(a *obj.Addr) { return } + // Detect (VL*imm) or (-VL*imm) pattern in ARM64 + if p.arch.Family == sys.ARM64 && len(p.input) >= 5 && p.input[0].ScanToken == '(' { + pos := 1 + sign := int64(1) + if p.input[pos].ScanToken == '-' { + sign = -1 + pos++ + } else if p.input[pos].ScanToken == '+' { + pos++ + } + if pos+3 < len(p.input) && p.input[pos].String() == "VL" && p.input[pos+1].ScanToken == '*' && p.input[pos+2].ScanToken == scanner.Int && p.input[pos+3].ScanToken == ')' { + imm := int64(p.atoi(p.input[pos+2].String())) + imm *= sign + a.Offset = imm + a.Scale = -32768 // bit 15 signals multiple of Vector Length + + // Remove the (VL*imm) tokens and let operand parse the remaining sequence (reg.T) + p.input = p.input[pos+4:] + p.inputPos = 0 + p.operand(a) + return + } + } + // Constant. haveConstant := false switch tok.ScanToken { @@ -579,7 +667,7 @@ func (p *Parser) atRegisterExtension() bool { switch p.arch.Family { case sys.ARM64, sys.Loong64: // R1.xxx - return p.peek() == '.' + return p.peek() == '.' || p.peek() == '[' default: return false } @@ -743,7 +831,7 @@ func (p *Parser) registerExtension(a *obj.Addr, name string, prefix rune) { if p.peek() == lex.LSH { // (Rn)(Rm<<2), the shifted offset register. ext = "LSL" - } else { + } else if p.peek() == '.' { // (Rn)(Rm.UXTW<1), the extended offset register. // Rm.UXTW<<3, the extended register. p.get('.') @@ -775,7 +863,7 @@ func (p *Parser) registerExtension(a *obj.Addr, name string, prefix rune) { switch p.arch.Family { case sys.ARM64: - err := arm64.ARM64RegisterExtension(a, ext, reg, num, isAmount, isIndex) + err := arm64.EncodeRegisterExtension(a, ext, reg, num, isAmount, isIndex) if err != nil { p.errorf("%v", err) } @@ -971,8 +1059,133 @@ func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) { if !ok { p.errorf("indirect through non-register %s", tok) } + // SVE extended addressing support + var ext string + var mod int64 + var amount int64 + isSVEMemExt := false + + if p.arch.Family == sys.ARM64 && (p.peek() == '.' || p.peek() == lex.LSH) { + // The index is a vector register, or contains a shift, then this is SVE extended addressing. + isSVEMemExt = true + if p.peek() == '.' { + p.get('.') + tok2 := p.next() + str := tok2.String() + if str == "UXTW" || str == "SXTW" { + switch str { + case "UXTW": + mod = 1 + case "SXTW": + mod = 2 + } + } else { + ext = str + if p.peek() == '.' { + p.get('.') + tok3 := p.next() + modStr := tok3.String() + switch modStr { + case "UXTW": + mod = 1 + case "SXTW": + mod = 2 + default: + p.errorf("unknown modifier %s", modStr) + } + } + } + } + if p.peek() == lex.LSH { + p.get(lex.LSH) + tok4 := p.get(scanner.Int) + amount, _ = strconv.ParseInt(tok4.String(), 10, 16) + } + } p.get(')') a.Type = obj.TYPE_MEM + + if isSVEMemExt { + encodedR1 := r1 + if ext != "" { + if r1 >= arm64.REG_Z0 && r1 <= arm64.REG_Z31 { + var arng int + switch ext { + case "B": + arng = arm64.ARNG_B + case "H": + arng = arm64.ARNG_H + case "S": + arng = arm64.ARNG_S + case "D": + arng = arm64.ARNG_D + case "Q": + arng = arm64.ARNG_Q + default: + p.errorf("unknown arrangement %s", ext) + } + if arng != 0 { + encodedR1 = arm64.REG_ZARNG + (r1 & 31) + int16((arng&15)<<5) + } + } else { + p.errorf("arrangement not allowed for this register") + } + } + + if p.peek() != '(' { + a.Reg = encodedR1 + return + } + p.get('(') + tok5 := p.next() + r2, ok := p.registerReference(tok5.String()) + if !ok { + p.errorf("expected register") + } + var ext2 string + if p.peek() == '.' { + p.get('.') + tok6 := p.next() + ext2 = tok6.String() + } + p.get(')') + + encodedR2 := r2 + if ext2 != "" { + if r2 >= arm64.REG_Z0 && r2 <= arm64.REG_Z31 { + var arng int + switch ext2 { + case "B": + arng = arm64.ARNG_B + case "H": + arng = arm64.ARNG_H + case "S": + arng = arm64.ARNG_S + case "D": + arng = arm64.ARNG_D + case "Q": + arng = arm64.ARNG_Q + default: + p.errorf("unknown arrangement %s", ext2) + } + if arng != 0 { + encodedR2 = arm64.REG_ZARNG + (r2 & 31) + int16((arng&15)<<5) + } + } else { + p.errorf("arrangement not allowed for this register") + } + } + + a.Index = encodedR2 // Base + a.Reg = encodedR1 // Index + a.Offset = 0 // Ensure offset is 0 + + var scaleValue int16 = -32768 // Bit 15 set + scaleValue |= int16(amount << 12) + scaleValue |= int16(mod << 9) + a.Scale = scaleValue + return + } if r1 < 0 { // Pseudo-register reference. if r2 != 0 { @@ -1117,13 +1330,26 @@ ListLoop: } switch p.arch.Family { case sys.ARM64: - // Vn.T + // Vn.T, Zn.T, Pn.T name := tok.String() r, ok := p.registerReference(name) if !ok { p.errorf("invalid register: %s", name) } - reg := r - p.arch.Register["V0"] + var registerBase int16 + registerCntMask := 31 + switch name[0] { + case 'V': + registerBase = p.arch.Register["V0"] + case 'Z': + registerBase = p.arch.Register["Z0"] + case 'P': + registerBase = p.arch.Register["P0"] + registerCntMask = 15 + default: + p.errorf("invalid register in register list: %s", name) + } + reg := r - registerBase p.get('.') tok := p.next() ext := tok.String() @@ -1141,8 +1367,33 @@ ListLoop: } else if nextReg != int(reg) { p.errorf("incontiguous register in ARM64 register list: %s", name) } - regCnt++ - nextReg = (nextReg + 1) % 32 + if p.peek() == '-' && name[0] == 'Z' { + // register range in SVE + p.next() + nameHi := p.next().String() + if nameHi[0] != 'Z' { + p.errorf("invalid register in register range: %s", nameHi) + } + rHi, ok2 := p.registerReference(nameHi) + if !ok2 { + p.errorf("invalid register: %s", nameHi) + } + regHi := rHi - registerBase + p.get('.') + extHi := p.next().String() + hiArrangement, err := arch.ARM64RegisterArrangement(regHi, nameHi, extHi) + if err != nil { + p.errorf("%v", err) + } + if hiArrangement != arrangement { + p.errorf("inconsistent arrangement in ARM64 register list range") + } + // Scale stores the range size - 1. + a.Scale = regHi - reg + } else { + regCnt++ + nextReg = (nextReg + 1) & registerCntMask + } case sys.ARM: // Parse the upper and lower bounds. lo := p.registerNumber(tok.String()) @@ -1174,7 +1425,7 @@ ListLoop: case sys.ARM: a.Offset = int64(bits) case sys.ARM64: - offset, err := arch.ARM64RegisterListOffset(firstReg, regCnt, arrangement) + offset, err := arm64.RegisterListOffset(firstReg, regCnt, arrangement, a.Scale) if err != nil { p.errorf("%v", err) } diff --git a/src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s b/src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s index 4bf58a39a43266..8b104307cd2697 100644 --- a/src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s +++ b/src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s @@ -169,3 +169,8 @@ TEXT ·a34(SB), 0, $0-0 SHLXQ AX, CX, R15 ADDQ $1, R15 RET + +// Ensure from3 get GOT-rewritten without errors. +TEXT ·a35(SB), 0, $0-0 + VGF2P8AFFINEQB $0, runtime·writeBarrier(SB), Z1, Z1 + RET diff --git a/src/cmd/asm/internal/asm/testdata/amd64enc.s b/src/cmd/asm/internal/asm/testdata/amd64enc.s index 5bba292dee43f6..c93c479735ae39 100644 --- a/src/cmd/asm/internal/asm/testdata/amd64enc.s +++ b/src/cmd/asm/internal/asm/testdata/amd64enc.s @@ -2425,6 +2425,15 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 MOVQ $-249346713, (R11) // 49c703674523f1 MOVQ $-249346713, DX // 48c7c2674523f1 MOVQ $-249346713, R11 // 49c7c3674523f1 + // Positive immediates that fit in 32 bits use the shorter 5-byte + // MOV r64, imm32 (zero-extended) form rather than the 7-byte sign- + // extended c7 /0 form. See Ziq_rp in cmd/internal/obj/x86/asm6.go. + MOVQ $305419896, DX // ba78563412 + MOVQ $305419896, R11 // 41bb78563412 + MOVQ $2147483648, DX // ba00000080 + MOVQ $2147483648, R11 // 41bb00000080 + MOVQ $4294967295, DX // baffffffff + MOVQ $4294967295, R11 // 41bbffffffff MOVQ DX, (BX) // 488913 MOVQ R11, (BX) // 4c891b MOVQ DX, (R11) // 498913 diff --git a/src/cmd/asm/internal/asm/testdata/arm.s b/src/cmd/asm/internal/asm/testdata/arm.s index 93edc8854ead47..fcc6ac32df4d0d 100644 --- a/src/cmd/asm/internal/asm/testdata/arm.s +++ b/src/cmd/asm/internal/asm/testdata/arm.s @@ -1089,10 +1089,23 @@ jmp_label_3: RSC $0xffffff4b, R5 // RSC $4294967115, R5 // b4b0e0e30b50e5e0 RSC.S $0xffffffb5, R2, R3 // RSC.S $4294967221, R2, R3 // 4ab0e0e30b30f2e0 RSC.S $0xffffff4a, R5 // RSC.S $4294967114, R5 // b5b0e0e30b50f5e0 - AND $0xffffffaa, R2, R3 // AND $4294967210, R2, R3 // 55b0e0e30b3002e0 - AND $0xffffff55, R5 // AND $4294967125, R5 // aab0e0e30b5005e0 - AND.S $0xffffffab, R2, R3 // AND.S $4294967211, R2, R3 // 54b0e0e30b3012e0 - AND.S $0xffffff54, R5 // AND.S $4294967124, R5 // abb0e0e30b5015e0 + AND $0xffffffaa, R2, R3 // AND $4294967210, R2, R3 // 5530c2e3 + AND $0xffffff55, R5 // AND $4294967125, R5 // aa50c5e3 + AND.S $0xffffffab, R2, R3 // AND.S $4294967211, R2, R3 // 5430d2e3 + AND.S $0xffffff54, R5 // AND.S $4294967124, R5 // ab50d5e3 + // AND with a negative-rotated immediate: emit a single BIC, + // not the two-instruction MVN+AND synthesis (which clobbers R11). + AND $0xfffffffc, R0, R1 // AND $4294967292, R0, R1 // 0310c0e3 + AND $0xfffffff0, R0, R1 // AND $4294967280, R0, R1 // 0f10c0e3 + AND $0xffffff00, R0, R1 // AND $4294967040, R0, R1 // ff10c0e3 + AND $0xfffffffc, R8 // AND $4294967292, R8 // 0380c8e3 + AND.S $0xfffffffc, R0, R1 // AND.S $4294967292, R0, R1 // 0310d0e3 + // AND with an irregular immediate (neither rot8 nor ~rot8 fit) + // still goes through the literal-pool synthesis: MOVW pool(PC), + // R11; AND R11, Rn, Rd. Encoded form depends on pool placement, + // so just round-trip the disassembly. + AND $0xaaaaaaaa, R0, R1 // AND $2863311530, R0, R1 + AND.S $0xaaaaaaaa, R0, R1 // AND.S $2863311530, R0, R1 ORR $0xffffffaa, R2, R3 // ORR $4294967210, R2, R3 // 55b0e0e30b3082e1 ORR $0xffffff55, R5 // ORR $4294967125, R5 // aab0e0e30b5085e1 ORR.S $0xffffffab, R2, R3 // ORR.S $4294967211, R2, R3 // 54b0e0e30b3092e1 diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index 109a3d8316678b..be4bf0c65a58e9 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -110,8 +110,50 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VADDP V1.D2, V2.D2, V3.D2 // 43bce14e VAND V21.B8, V12.B8, V3.B8 // 831d350e VCMEQ V1.H4, V2.H4, V3.H4 // 438c612e + VCMEQ $0, V2.H4, V3.H4 // 4398600e + VCMGE V1.H4, V2.H4, V3.H4 // 433c610e + VCMGE $0, V2.H4, V3.H4 // 4388602e + VCMGT V1.H4, V2.H4, V3.H4 // 4334610e + VCMGT $0, V2.H4, V3.H4 // 4388600e + VCMHI V1.H4, V2.H4, V3.H4 // 4334612e + VCMHS V1.H4, V2.H4, V3.H4 // 433c612e + VCMLE $0, V2.H4, V3.H4 // 4398602e + VCMLT $0, V2.H4, V3.H4 // 43a8600e + VFCMEQ V1.S4, V2.S4, V3.S4 // 43e4214e + VFCMEQ $(0.0), V2.S4, V3.S4 // 43d8a04e + VFCMGE V1.S4, V2.S4, V3.S4 // 43e4216e + VFCMGE $(0.0), V2.S4, V3.S4 // 43c8a06e + VFCMGT V1.S4, V2.S4, V3.S4 // 43e4a16e + VFCMGT $(0.0), V2.S4, V3.S4 // 43c8a04e + VFCMLE $(0.0), V2.S4, V3.S4 // 43d8a06e + VFCMLT $(0.0), V2.S4, V3.S4 // 43e8a04e + VFADD V0.S4, V0.S4, V1.S4 // 01d4204e + VFADD V0.D2, V0.D2, V1.D2 // 01d4604e + VFSUB V0.S4, V0.S4, V1.S4 // 01d4a04e + VFSUB V0.D2, V0.D2, V1.D2 // 01d4e04e + VFMUL V0.S4, V0.S4, V1.S4 // 01dc206e + VFMUL V0.D2, V0.D2, V1.D2 // 01dc606e + VFDIV V0.S4, V0.S4, V1.S4 // 01fc206e + VFDIV V0.D2, V0.D2, V1.D2 // 01fc606e + VSQADD V0.S4, V0.S4, V1.S4 // 010ca04e + VSQADD V0.D2, V0.D2, V1.D2 // 010ce04e + VUQADD V0.S4, V0.S4, V1.S4 // 010ca06e + VUQADD V0.D2, V0.D2, V1.D2 // 010ce06e + VSQSUB V0.S4, V0.S4, V1.S4 // 012ca04e + VSQSUB V0.D2, V0.D2, V1.D2 // 012ce04e + VUQSUB V0.S4, V0.S4, V1.S4 // 012ca06e + VUQSUB V0.D2, V0.D2, V1.D2 // 012ce06e + VMUL V0.S4, V0.S4, V1.S4 // 019ca04e + VMLA V0.S4, V0.S4, V1.S4 // 0194a04e + VMLS V0.S4, V0.S4, V1.S4 // 0194a06e VORR V5.B16, V4.B16, V3.B16 // 831ca54e + VBIC V0.B8, V1.B8, V2.B8 // 221c600e + VORN V0.B16, V1.B16, V2.B16 // 221ce04e VADD V16.S4, V5.S4, V9.S4 // a984b04e + VSHADD V0.S4, V1.S4, V2.S4 // 2204a04e + VSRHADD V0.S4, V1.S4, V2.S4 // 2214a04e + VUHADD V0.S4, V1.S4, V2.S4 // 2204a06e + VURHADD V0.S4, V1.S4, V2.S4 // 2214a06e VEOR V0.B16, V1.B16, V0.B16 // 201c206e VADDV V0.S4, V0 // 00b8b14e VMOVI $82, V0.B16 // 40e6024f @@ -137,6 +179,41 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VUSHR $8, V1.H8, V2.H8 // 2204186f VUSHR $2, V1.B8, V2.B8 // 22040e2f VUSHR $2, V1.B16, V2.B16 // 22040e6f + VSHRN $7, V1.H8, V0.B8 // 2084090f + VSHRN $15, V1.S4, V0.H4 // 2084110f + VSHRN $31, V1.D2, V0.S2 // 2084210f + VSHRN2 $7, V1.H8, V0.B16 // 2084094f + VSHRN2 $15, V1.S4, V0.H8 // 2084114f + VSHRN2 $31, V1.D2, V0.S4 // 2084214f + VSSHR $2, V0.B8, V1.B8 // 01040e0f + VSSHR $2, V0.B16, V1.B16 // 01040e4f + VSSHR $8, V0.H4, V1.H4 // 0104180f + VSSHR $8, V0.H8, V1.H8 // 0104184f + VSSHR $16, V0.S2, V1.S2 // 0104300f + VSSHR $16, V0.S4, V1.S4 // 0104304f + VSSHR $32, V0.D2, V1.D2 // 0104604f + VSRSHR $2, V0.B8, V1.B8 // 01240e0f + VSRSHR $2, V0.B16, V1.B16 // 01240e4f + VSRSHR $8, V0.H4, V1.H4 // 0124180f + VSRSHR $8, V0.H8, V1.H8 // 0124184f + VSRSHR $16, V0.S2, V1.S2 // 0124300f + VSRSHR $16, V0.S4, V1.S4 // 0124304f + VSRSHR $32, V0.D2, V1.D2 // 0124604f + VFSQRT V0.S2, V1.S2 // 01f8a12e + VFSQRT V0.S4, V1.S4 // 01f8a16e + VFSQRT V0.D2, V1.D2 // 01f8e16e + VFRINTN V0.S2, V1.S2 // 0188210e + VFRINTN V0.S4, V1.S4 // 0188214e + VFRINTN V0.D2, V1.D2 // 0188614e + VFRINTP V0.S2, V1.S2 // 0188a10e + VFRINTP V0.S4, V1.S4 // 0188a14e + VFRINTP V0.D2, V1.D2 // 0188e14e + VFRINTM V0.S2, V1.S2 // 0198210e + VFRINTM V0.S4, V1.S4 // 0198214e + VFRINTM V0.D2, V1.D2 // 0198614e + VFRINTZ V0.S2, V1.S2 // 0198a10e + VFRINTZ V0.S4, V1.S4 // 0198a14e + VFRINTZ V0.D2, V1.D2 // 0198e14e VSHL $56, V1.D2, V2.D2 // 2254784f VSHL $24, V1.S4, V2.S4 // 2254384f VSHL $24, V1.S2, V2.S2 // 2254380f @@ -144,6 +221,48 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VSHL $8, V1.H8, V2.H8 // 2254184f VSHL $2, V1.B8, V2.B8 // 22540a0f VSHL $2, V1.B16, V2.B16 // 22540a4f + VSQSHL $56, V1.D2, V2.D2 // 2274784f + VSQSHL $24, V1.S4, V2.S4 // 2274384f + VSQSHL $24, V1.S2, V2.S2 // 2274380f + VSQSHL $8, V1.H4, V2.H4 // 2274180f + VSQSHL $8, V1.H8, V2.H8 // 2274184f + VSQSHL $2, V1.B8, V2.B8 // 22740a0f + VSQSHL $2, V1.B16, V2.B16 // 22740a4f + VUQSHL $56, V1.D2, V2.D2 // 2274786f + VUQSHL $24, V1.S4, V2.S4 // 2274386f + VUQSHL $24, V1.S2, V2.S2 // 2274382f + VUQSHL $8, V1.H4, V2.H4 // 2274182f + VUQSHL $8, V1.H8, V2.H8 // 2274186f + VUQSHL $2, V1.B8, V2.B8 // 22740a2f + VUQSHL $2, V1.B16, V2.B16 // 22740a6f + VSSHL V1.D2, V2.D2, V3.D2 // 4344e14e + VSSHL V1.S4, V2.S4, V3.S4 // 4344a14e + VSSHL V1.S2, V2.S2, V3.S2 // 4344a10e + VSSHL V1.H4, V2.H4, V3.H4 // 4344610e + VSSHL V1.H8, V2.H8, V3.H8 // 4344614e + VSSHL V1.B8, V2.B8, V3.B8 // 4344210e + VSSHL V1.B16, V2.B16, V3.B16 // 4344214e + VUSHL V1.D2, V2.D2, V3.D2 // 4344e16e + VUSHL V1.S4, V2.S4, V3.S4 // 4344a16e + VUSHL V1.S2, V2.S2, V3.S2 // 4344a12e + VUSHL V1.H4, V2.H4, V3.H4 // 4344612e + VUSHL V1.H8, V2.H8, V3.H8 // 4344616e + VUSHL V1.B8, V2.B8, V3.B8 // 4344212e + VUSHL V1.B16, V2.B16, V3.B16 // 4344216e + VSQSHL V1.D2, V2.D2, V3.D2 // 434ce14e + VSQSHL V1.S4, V2.S4, V3.S4 // 434ca14e + VSQSHL V1.S2, V2.S2, V3.S2 // 434ca10e + VSQSHL V1.H4, V2.H4, V3.H4 // 434c610e + VSQSHL V1.H8, V2.H8, V3.H8 // 434c614e + VSQSHL V1.B8, V2.B8, V3.B8 // 434c210e + VSQSHL V1.B16, V2.B16, V3.B16 // 434c214e + VUQSHL V1.D2, V2.D2, V3.D2 // 434ce16e + VUQSHL V1.S4, V2.S4, V3.S4 // 434ca16e + VUQSHL V1.S2, V2.S2, V3.S2 // 434ca12e + VUQSHL V1.H4, V2.H4, V3.H4 // 434c612e + VUQSHL V1.H8, V2.H8, V3.H8 // 434c616e + VUQSHL V1.B8, V2.B8, V3.B8 // 434c212e + VUQSHL V1.B16, V2.B16, V3.B16 // 434c216e VSRI $56, V1.D2, V2.D2 // 2244486f VSRI $24, V1.S4, V2.S4 // 2244286f VSRI $24, V1.S2, V2.S2 // 2244282f @@ -203,6 +322,36 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VUXTL2 V30.H8, V30.S4 // dea7106f VUXTL2 V29.S4, V2.D2 // a2a7206f VUXTL2 V30.B16, V2.H8 // c2a7086f + VSXTL V1.B8, V2.H8 // 22a4080f + VSXTL V1.H4, V2.S4 // 22a4100f + VSXTL V1.S2, V2.D2 // 22a4200f + VSXTL2 V1.B16, V2.H8 // 22a4084f + VSXTL2 V1.H8, V2.S4 // 22a4104f + VSXTL2 V1.S4, V2.D2 // 22a4204f + VXTN V1.H8, V2.B8 // 2228210e + VXTN V1.S4, V2.H4 // 2228610e + VXTN V1.D2, V2.S2 // 2228a10e + VXTN2 V1.H8, V2.B16 // 2228214e + VXTN2 V1.S4, V2.H8 // 2228614e + VXTN2 V1.D2, V2.S4 // 2228a14e + VSQXTN V1.H8, V2.B8 // 2248210e + VSQXTN V1.S4, V2.H4 // 2248610e + VSQXTN V1.D2, V2.S2 // 2248a10e + VSQXTN2 V1.H8, V2.B16 // 2248214e + VSQXTN2 V1.S4, V2.H8 // 2248614e + VSQXTN2 V1.D2, V2.S4 // 2248a14e + VSQXTUN V1.H8, V2.B8 // 2228212e + VSQXTUN V1.S4, V2.H4 // 2228612e + VSQXTUN V1.D2, V2.S2 // 2228a12e + VSQXTUN2 V1.H8, V2.B16 // 2228216e + VSQXTUN2 V1.S4, V2.H8 // 2228616e + VSQXTUN2 V1.D2, V2.S4 // 2228a16e + VUQXTN V1.H8, V2.B8 // 2248212e + VUQXTN V1.S4, V2.H4 // 2248612e + VUQXTN V1.D2, V2.S2 // 2248a12e + VUQXTN2 V1.H8, V2.B16 // 2248216e + VUQXTN2 V1.S4, V2.H8 // 2248616e + VUQXTN2 V1.D2, V2.S4 // 2248a16e VBIT V21.B16, V25.B16, V4.B16 // 241fb56e VBSL V23.B16, V3.B16, V7.B16 // 671c776e VCMTST V2.B8, V29.B8, V2.B8 // a28f220e @@ -226,6 +375,15 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VUSHLL $7, V30.B8, V30.H8 // dea70f2f VUSHLL $15, V30.H4, V29.S4 // dda71f2f VUSHLL2 $31, V30.S4, V2.D2 // c2a73f6f + VSSHLL $0, V1.B8, V2.H8 // 22a4080f + VSSHLL $0, V1.H4, V2.S4 // 22a4100f + VSSHLL $0, V1.S2, V2.D2 // 22a4200f + VSSHLL2 $0, V1.B16, V2.H8 // 22a4084f + VSSHLL2 $0, V1.H8, V2.S4 // 22a4104f + VSSHLL2 $0, V1.S4, V2.D2 // 22a4204f + VSSHLL $7, V1.B8, V2.H8 // 22a40f0f + VSSHLL $15, V1.H4, V2.S4 // 22a41f0f + VSSHLL2 $31, V1.S4, V2.D2 // 22a43f4f VBIF V0.B8, V30.B8, V1.B8 // c11fe02e VBIF V30.B16, V0.B16, V2.B16 // 021cfe6e FMOVS $(4.0), F0 // 0010221e @@ -258,6 +416,23 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VUMIN V3.H8, V2.H8, V1.H8 // 416c636e VUMIN V3.S2, V2.S2, V1.S2 // 416ca32e VUMIN V3.S4, V2.S4, V1.S4 // 416ca36e + VSMAX V3.S4, V2.S4, V1.S4 // 4164a34e + VSMIN V3.S4, V2.S4, V1.S4 // 416ca34e + VSMAXP V3.S4, V2.S4, V1.S4 // 41a4a34e + VSMINP V3.S4, V2.S4, V1.S4 // 41aca34e + VUMAXP V3.S4, V2.S4, V1.S4 // 41a4a36e + VUMINP V3.S4, V2.S4, V1.S4 // 41aca36e + VFMAX V3.S4, V2.S4, V1.S4 // 41f4234e + VFMIN V3.S4, V2.S4, V1.S4 // 41f4a34e + VFMAXNM V3.S4, V2.S4, V1.S4 // 41c4234e + VFMINNM V3.S4, V2.S4, V1.S4 // 41c4a34e + VFMAXP V3.S4, V2.S4, V1.S4 // 41f4236e + VFADDP V3.S4, V2.S4, V1.S4 // 41d4236e + VFADDP V3.S2, V2.S2, V1.S2 // 41d4232e + VFADDP V3.D2, V2.D2, V1.D2 // 41d4636e + VFMINP V3.S4, V2.S4, V1.S4 // 41f4a36e + VFMAXNMP V3.S4, V2.S4, V1.S4 // 41c4236e + VFMINNMP V3.S4, V2.S4, V1.S4 // 41c4a36e FCCMPS LT, F1, F2, $1 // 41b4211e FMADDS F1, F3, F2, F4 // 440c011f FMADDD F4, F5, F4, F4 // 8414441f @@ -283,10 +458,14 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 PRFM 8(R12), PLIL3STRM // 8d0580f9 PRFM (R8), $25 // 190180f9 PRFM 8(R9), $30 // 3e0580f9 + RPRFM (R1), R2, PLDKEEP // 3848a2f8 + RPRFM (RSP), R4, PSTSTRM // fd4ba4f8 + RPRFM (R6), R12, $25 // d978acf8 NOOP // 1f2003d5 HINT $0 // 1f2003d5 DMB $1 SVC + SB // ff3003d5 // encryption SHA256H V9.S4, V3, V2 // 6240095e @@ -309,11 +488,76 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VPMULL2 V2.D2, V1.D2, V4.Q1 // 24e0e24e VPMULL V2.B8, V1.B8, V3.H8 // 23e0220e VPMULL2 V2.B16, V1.B16, V4.H8 // 24e0224e + VUMULL V0.H4, V1.H4, V21.S4 // 35c0602e + VUMULL2 V0.H8, V1.H8, V22.S4 // 36c0606e + VUMULL V22.H4, V31.H4, V23.S4 // f7c3762e + VUMULL2 V22.H8, V31.H8, V24.S4 // f8c3766e + VUMLAL V0.H4, V1.H4, V21.S4 // 3580602e + VUMLAL2 V0.H8, V1.H8, V22.S4 // 3680606e + VUMLSL V0.H4, V1.H4, V21.S4 // 35a0602e + VUMLSL2 V0.H8, V1.H8, V22.S4 // 36a0606e + VSMULL V0.B8, V1.B8, V5.H8 // 25c0200e + VSMULL2 V0.B16, V1.B16, V6.H8 // 26c0204e + VSMULL V0.S2, V1.S2, V7.D2 // 27c0a00e + VSMULL2 V0.S4, V1.S4, V8.D2 // 28c0a04e + VSMLAL V0.H4, V1.H4, V21.S4 // 3580600e + VSMLAL2 V0.H8, V1.H8, V22.S4 // 3680604e + VSMLSL V0.H4, V1.H4, V21.S4 // 35a0600e + VSMLSL2 V0.H8, V1.H8, V22.S4 // 36a0604e VEOR3 V2.B16, V7.B16, V12.B16, V25.B16 // 990907ce VBCAX V1.B16, V2.B16, V26.B16, V31.B16 // 5f0722ce VREV32 V5.B16, V5.B16 // a508206e VREV64 V2.S2, V3.S2 // 4308a00e VREV64 V2.S4, V3.S4 // 4308a04e + VREV16 V7.B16, V5.B16 // e518204e + VREV16 V7.B8, V5.B8 // e518200e + + VABS V0.B8, V1.B8 // 01b8200e + VABS V0.B16, V1.B16 // 01b8204e + VABS V0.H4, V1.H4 // 01b8600e + VABS V0.H8, V1.H8 // 01b8604e + VABS V0.S2, V1.S2 // 01b8a00e + VABS V0.S4, V1.S4 // 01b8a04e + VABS V0.D2, V1.D2 // 01b8e04e + VCLS V0.B8, V1.B8 // 0148200e + VCLS V0.B16, V1.B16 // 0148204e + VCLS V0.H4, V1.H4 // 0148600e + VCLS V0.H8, V1.H8 // 0148604e + VCLS V0.S2, V1.S2 // 0148a00e + VCLS V0.S4, V1.S4 // 0148a04e + VCLZ V0.B8, V1.B8 // 0148202e + VCLZ V0.B16, V1.B16 // 0148206e + VCLZ V0.H4, V1.H4 // 0148602e + VCLZ V0.H8, V1.H8 // 0148606e + VCLZ V0.S2, V1.S2 // 0148a02e + VCLZ V0.S4, V1.S4 // 0148a06e + VNEG V0.B8, V1.B8 // 01b8202e + VNEG V0.B16, V1.B16 // 01b8206e + VNEG V0.H4, V1.H4 // 01b8602e + VNEG V0.H8, V1.H8 // 01b8606e + VNEG V0.S2, V1.S2 // 01b8a02e + VNEG V0.S4, V1.S4 // 01b8a06e + VNEG V0.D2, V1.D2 // 01b8e06e + VFABS V0.S2, V1.S2 // 01f8a00e + VFABS V0.S4, V1.S4 // 01f8a04e + VFABS V0.D2, V1.D2 // 01f8e04e + VFNEG V0.S2, V1.S2 // 01f8a02e + VFNEG V0.S4, V1.S4 // 01f8a06e + VFNEG V0.D2, V1.D2 // 01f8e06e + VSQABS V0.B8, V1.B8 // 0178200e + VSQABS V0.B16, V1.B16 // 0178204e + VSQABS V0.H4, V1.H4 // 0178600e + VSQABS V0.H8, V1.H8 // 0178604e + VSQABS V0.S2, V1.S2 // 0178a00e + VSQABS V0.S4, V1.S4 // 0178a04e + VSQNEG V0.B8, V1.B8 // 0178202e + VSQNEG V0.B16, V1.B16 // 0178206e + VSQNEG V0.H4, V1.H4 // 0178602e + VSQNEG V0.H8, V1.H8 // 0178606e + VSQNEG V0.S2, V1.S2 // 0178a02e + VSQNEG V0.S4, V1.S4 // 0178a06e + VNOT V0.B8, V1.B8 // 0158202e + VNOT V0.B16, V1.B16 // 0158206e // logical ops // @@ -400,6 +644,8 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 MOVD $0x11110000, R1 // MOVD $286326784, R1 // 2122a2d2 MOVD $0xaaaa0000aaaa1111, R1 // MOVD $-6149102338357718767, R1 // 212282d24155b5f24155f5f2 MOVD $0x1111ffff1111aaaa, R1 // MOVD $1230045644216969898, R1 // a1aa8a922122a2f22122e2f2 + MOVD $0xaaaaaaaaaaaaaaab, R1 // MOVD $-6148914691236517205, R1 // e1f301b2615595f2 + MOVD $0x0ff019940ff00ff0, R1 // MOVD $1148446028692721648, R1 // e19f0cb28132c3f2 MOVD $0, R1 // e1031faa MOVD $-1, R1 // 01008092 MOVD $0x210000, R0 // MOVD $2162688, R0 // 2004a0d2 @@ -589,30 +835,30 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 MOVD R3, 4095(R17) // 3bfe3f91630300f9 // large aligned offset, use two instructions(add+ldr/str). - MOVB R1, 0x1001(R2) // MOVB R1, 4097(R2) // 5b04409161070039 + MOVB R1, 0x1001(R2) // MOVB R1, 4097(R2) // 5b08009161ff3f39 MOVB R1, 0xffffff(R2) // MOVB R1, 16777215(R2) // 5bfc7f9161ff3f39 - MOVH R1, 0x2002(R2) // MOVH R1, 8194(R2) // 5b08409161070079 + MOVH R1, 0x2002(R2) // MOVH R1, 8194(R2) // 5b10009161ff3f79 MOVH R1, 0x1000ffe(R2) // MOVH R1, 16781310(R2) // 5bfc7f9161ff3f79 - MOVW R1, 0x4004(R2) // MOVW R1, 16388(R2) // 5b104091610700b9 + MOVW R1, 0x4004(R2) // MOVW R1, 16388(R2) // 5b20009161ff3fb9 MOVW R1, 0x1002ffc(R2) // MOVW R1, 16789500(R2) // 5bfc7f9161ff3fb9 - MOVD R1, 0x8008(R2) // MOVD R1, 32776(R2) // 5b204091610700f9 + MOVD R1, 0x8008(R2) // MOVD R1, 32776(R2) // 5b40009161ff3ff9 MOVD R1, 0x1006ff8(R2) // MOVD R1, 16805880(R2) // 5bfc7f9161ff3ff9 - FMOVS F1, 0x4004(R2) // FMOVS F1, 16388(R2) // 5b104091610700bd + FMOVS F1, 0x4004(R2) // FMOVS F1, 16388(R2) // 5b20009161ff3fbd FMOVS F1, 0x1002ffc(R2) // FMOVS F1, 16789500(R2) // 5bfc7f9161ff3fbd - FMOVD F1, 0x8008(R2) // FMOVD F1, 32776(R2) // 5b204091610700fd + FMOVD F1, 0x8008(R2) // FMOVD F1, 32776(R2) // 5b40009161ff3ffd FMOVD F1, 0x1006ff8(R2) // FMOVD F1, 16805880(R2) // 5bfc7f9161ff3ffd - MOVB 0x1001(R1), R2 // MOVB 4097(R1), R2 // 3b04409162078039 + MOVB 0x1001(R1), R2 // MOVB 4097(R1), R2 // 3b08009162ffbf39 MOVB 0xffffff(R1), R2 // MOVB 16777215(R1), R2 // 3bfc7f9162ffbf39 - MOVH 0x2002(R1), R2 // MOVH 8194(R1), R2 // 3b08409162078079 + MOVH 0x2002(R1), R2 // MOVH 8194(R1), R2 // 3b10009162ffbf79 MOVH 0x1000ffe(R1), R2 // MOVH 16781310(R1), R2 // 3bfc7f9162ffbf79 - MOVW 0x4004(R1), R2 // MOVW 16388(R1), R2 // 3b104091620780b9 + MOVW 0x4004(R1), R2 // MOVW 16388(R1), R2 // 3b20009162ffbfb9 MOVW 0x1002ffc(R1), R2 // MOVW 16789500(R1), R2 // 3bfc7f9162ffbfb9 - MOVD 0x8008(R1), R2 // MOVD 32776(R1), R2 // 3b204091620740f9 + MOVD 0x8008(R1), R2 // MOVD 32776(R1), R2 // 3b40009162ff7ff9 MOVD 0x1006ff8(R1), R2 // MOVD 16805880(R1), R2 // 3bfc7f9162ff7ff9 - FMOVS 0x4004(R1), F2 // FMOVS 16388(R1), F2 // 3b104091620740bd + FMOVS 0x4004(R1), F2 // FMOVS 16388(R1), F2 // 3b20009162ff7fbd FMOVS 0x1002ffc(R1), F2 // FMOVS 16789500(R1), F2 // 3bfc7f9162ff7fbd - FMOVD 0x8008(R1), F2 // FMOVD 32776(R1), F2 // 3b204091620740fd + FMOVD 0x8008(R1), F2 // FMOVD 32776(R1), F2 // 3b40009162ff7ffd FMOVD 0x1006ff8(R1), F2 // FMOVD 16805880(R1), F2 // 3bfc7f9162ff7ffd // very large or unaligned offset uses constant pool. @@ -630,6 +876,8 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 FMOVS F1, 0x44332211(R2) // FMOVS F1, 1144201745(R2) FMOVD F1, 0x1007000(R2) // FMOVD F1, 16805888(R2) FMOVD F1, 0x44332211(R2) // FMOVD F1, 1144201745(R2) + FMOVQ F1, 0x1003000(R2) // FMOVQ F1, 16789504(R2) + FMOVQ F1, 0x44332211(R2) // FMOVQ F1, 1144201745(R2) MOVB 0x1000000(R1), R2 // MOVB 16777216(R1), R2 MOVB 0x44332211(R1), R2 // MOVB 1144201745(R1), R2 @@ -643,6 +891,8 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 FMOVS 0x44332211(R1), F2 // FMOVS 1144201745(R1), F2 FMOVD 0x1000000(R1), F2 // FMOVD 16777216(R1), F2 FMOVD 0x44332211(R1), F2 // FMOVD 1144201745(R1), F2 + FMOVQ 0x1000000(R1), F2 // FMOVQ 16777216(R1), F2 + FMOVQ 0x44332211(R1), F2 // FMOVQ 1144201745(R1), F2 // shifted or extended register offset. MOVD (R2)(R6.SXTW), R4 // 44c866f8 @@ -692,6 +942,12 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 FMOVD F4, (R2)(R6) // 446826fc FMOVD F4, (R2)(R6<<3) // 447826fc +// global address + FMOVQ F5, x+8(SB) + FMOVQ F5, x(SB) + FMOVQ x+8(SB), F5 + FMOVQ x(SB), F5 + // vmov VMOV V8.S[1], R1 // 013d0c0e VMOV V0.D[0], R11 // 0b3c084e @@ -1902,4 +2158,42 @@ next: AUTIA1716 // 9f2103d5 AUTIB1716 // df2103d5 +// Vector Reduction Instructions + VSMAXV V0.B8, V0 // 00a8300e + VSMAXV V0.B16, V0 // 00a8304e + VSMAXV V0.H4, V0 // 00a8700e + VSMAXV V0.H8, V0 // 00a8704e + VSMAXV V0.S4, V0 // 00a8b04e + VSMINV V0.B8, V0 // 00a8310e + VSMINV V0.B16, V0 // 00a8314e + VSMINV V0.H4, V0 // 00a8710e + VSMINV V0.H8, V0 // 00a8714e + VSMINV V0.S4, V0 // 00a8b14e + VUMAXV V0.B8, V0 // 00a8302e + VUMAXV V0.B16, V0 // 00a8306e + VUMAXV V0.H4, V0 // 00a8702e + VUMAXV V0.H8, V0 // 00a8706e + VUMAXV V0.S4, V0 // 00a8b06e + VUMINV V0.B8, V0 // 00a8312e + VUMINV V0.B16, V0 // 00a8316e + VUMINV V0.H4, V0 // 00a8712e + VUMINV V0.H8, V0 // 00a8716e + VUMINV V0.S4, V0 // 00a8b16e + VFMAXV V0.S4, V0 // 00f8306e + VFMINV V0.S4, V0 // 00f8b06e + VFMAXNMV V0.S4, V0 // 00c8306e + VFMINNMV V0.S4, V0 // 00c8b06e + VFCVTZS V1.S4, V2.S4 // 22b8a14e + VFCVTZS V1.D2, V2.D2 // 22b8e14e + VFCVTZU V1.S4, V2.S4 // 22b8a16e + VFCVTZU V1.D2, V2.D2 // 22b8e16e + VSCVTF V1.S4, V2.S4 // 22d8214e + VSCVTF V1.D2, V2.D2 // 22d8614e + VUCVTF V1.S4, V2.S4 // 22d8216e + VUCVTF V1.D2, V2.D2 // 22d8616e + VFCVTN V1.D2, V2.S2 // 2268610e + VFCVTN2 V1.D2, V2.S4 // 2268614e + VFCVTL V1.S2, V2.D2 // 2278610e + VFCVTL2 V1.S4, V2.D2 // 2278614e + END diff --git a/src/cmd/asm/internal/asm/testdata/arm64enc.s b/src/cmd/asm/internal/asm/testdata/arm64enc.s index cc002a1584d2c7..76151a3570fe33 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64enc.s +++ b/src/cmd/asm/internal/asm/testdata/arm64enc.s @@ -426,18 +426,18 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 YIELD // 3f2003d5 //TODO FABD F0, F5, F11 // abd4a07e //TODO VFABD V30.S2, V8.S2, V24.S2 // 18d5be2e - //TODO VFABS V5.S4, V24.S4 // b8f8a04e + VFABS V5.S4, V24.S4 // b8f8a04e FABSS F2, F28 // 5cc0201e FABSD F0, F14 // 0ec0601e //TODO FACGE F25, F16, F0 // 00ee797e //TODO VFACGE V11.S2, V15.S2, V9.S2 // e9ed2b2e //TODO FACGT F20, F16, F27 // 1beef47e //TODO VFACGT V15.S4, V25.S4, V22.S4 // 36efaf6e - //TODO VFADD V21.D2, V10.D2, V21.D2 // 55d5754e + VFADD V21.D2, V10.D2, V21.D2 // 55d5754e FADDS F12, F2, F10 // 4a282c1e FADDD F24, F14, F12 // cc29781e //TODO VFADDP V4.D2, F13 // 8dd8707e - //TODO VFADDP V30.S4, V3.S4, V11.S4 // 6bd43e6e + VFADDP V30.S4, V3.S4, V11.S4 // 6bd43e6e FCCMPS LE, F17, F12, $14 // 8ed5311e FCCMPD HI, F11, F15, $15 // ef856b1e FCCMPES HS, F28, F13, $13 // bd253c1e @@ -547,34 +547,34 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 FCVTZUS F12, R29 // 9d01399e FCVTZUDW F27, R22 // 7603791e FCVTZUD F25, R22 // 3603799e - //TODO VFDIV V6.D2, V1.D2, V27.D2 // 3bfc666e + VFDIV V6.D2, V1.D2, V27.D2 // 3bfc666e FDIVS F16, F10, F20 // 5419301e FDIVD F11, F25, F30 // 3e1b6b1e FMADDS F15, F2, F8, F1 // 01090f1f FMADDD F15, F21, F25, F9 // 29574f1f - //TODO VFMAX V23.D2, V27.D2, V14.D2 // 6ef7774e + VFMAX V23.D2, V27.D2, V14.D2 // 6ef7774e FMAXS F5, F28, F27 // 9b4b251e FMAXD F12, F31, F31 // ff4b6c1e - //TODO VFMAXNM V3.D2, V12.D2, V27.D2 // 9bc5634e + VFMAXNM V3.D2, V12.D2, V27.D2 // 9bc5634e FMAXNMS F11, F24, F12 // 0c6b2b1e FMAXNMD F20, F6, F16 // d068741e //TODO VFMAXNMP V3.S2, F2 // 62c8307e - //TODO VFMAXNMP V25.S2, V4.S2, V2.S2 // 82c4392e + VFMAXNMP V25.S2, V4.S2, V2.S2 // 82c4392e //TODO VFMAXNMV V14.S4, F15 // cfc9306e //TODO VFMAXP V3.S2, F27 // 7bf8307e - //TODO VFMAXP V29.S2, V30.S2, V9.S2 // c9f73d2e + VFMAXP V29.S2, V30.S2, V9.S2 // c9f73d2e //TODO VFMAXV V13.S4, F14 // aef9306e - //TODO VFMIN V19.D2, V30.D2, V7.D2 // c7f7f34e + VFMIN V19.D2, V30.D2, V7.D2 // c7f7f34e FMINS F26, F18, F30 // 5e5a3a1e FMIND F29, F4, F21 // 95587d1e - //TODO VFMINNM V21.S4, V5.S4, V1.S4 // a1c4b54e + VFMINNM V21.S4, V5.S4, V1.S4 // a1c4b54e FMINNMS F23, F20, F1 // 817a371e FMINNMD F8, F3, F24 // 7878681e //TODO VFMINNMP V16.D2, F12 // 0ccaf07e - //TODO VFMINNMP V10.S4, V25.S4, V27.S4 // 3bc7aa6e + VFMINNMP V10.S4, V25.S4, V27.S4 // 3bc7aa6e //TODO VFMINNMV V8.S4, F3 // 03c9b06e //TODO VFMINP V10.S2, F20 // 54f9b07e - //TODO VFMINP V1.D2, V10.D2, V3.D2 // 43f5e16e + VFMINP V1.D2, V10.D2, V3.D2 // 43f5e16e //TODO VFMINV V11.S4, F9 // 69f9b06e //TODO VFMLA V6.S[0], F2, F14 // 4e10865f //TODO VFMLA V28.S[2], V2.S2, V30.S2 // 5e189c0f @@ -596,14 +596,14 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 FMSUBD F11, F7, F15, F31 // ff9d4b1f //TODO VFMUL V9.S[2], F21, F19 // b39a895f //TODO VFMUL V26.S[2], V26.S2, V2.S2 // 429b9a0f - //TODO VFMUL V21.D2, V17.D2, V25.D2 // 39de756e + VFMUL V21.D2, V17.D2, V25.D2 // 39de756e FMULS F0, F6, F24 // d808201e FMULD F5, F29, F9 // a90b651e //TODO VFMULX V26.S[2], F20, F8 // 889a9a7f //TODO VFMULX V12.D[1], V21.D2, V31.D2 // bf9acc6f //TODO FMULX F16, F1, F31 // 3fdc705e //TODO VFMULX V29.S2, V13.S2, V31.S2 // bfdd3d0e - //TODO VFNEG V18.S2, V12.S2 // 4cfaa02e + VFNEG V18.S2, V12.S2 // 4cfaa02e FNEGS F16, F5 // 0542211e FNEGD F31, F31 // ff43611e FNMADDS F17, F22, F6, F20 // d458311f @@ -623,26 +623,26 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 //TODO VFRINTI V21.D2, V31.D2 // bf9ae16e FRINTIS F17, F17 // 31c2271e FRINTID F9, F15 // 2fc1671e - //TODO VFRINTM V9.D2, V27.D2 // 3b99614e + VFRINTM V9.D2, V27.D2 // 3b99614e FRINTMS F24, F16 // 1043251e FRINTMD F5, F2 // a240651e - //TODO VFRINTN V30.S4, V2.S4 // c28b214e + VFRINTN V30.S4, V2.S4 // c28b214e FRINTNS F26, F14 // 4e43241e FRINTND F28, F12 // 8c43641e - //TODO VFRINTP V27.D2, V31.D2 // 7f8be14e + VFRINTP V27.D2, V31.D2 // 7f8be14e FRINTPS F27, F4 // 64c3241e FRINTPD F6, F22 // d6c0641e //TODO VFRINTX V25.D2, V0.D2 // 209b616e FRINTXS F26, F10 // 4a43271e FRINTXD F16, F12 // 0c42671e - //TODO VFRINTZ V25.S4, V27.S4 // 3b9ba14e + VFRINTZ V25.S4, V27.S4 // 3b9ba14e FRINTZS F3, F28 // 7cc0251e FRINTZD F24, F6 // 06c3651e //TODO FRSQRTE F29, F5 // a5dbe17e //TODO VFRSQRTE V18.S2, V1.S2 // 41daa12e //TODO FRSQRTS F17, F7, F24 // f8fcf15e //TODO VFRSQRTS V14.S2, V10.S2, V24.S2 // 58fdae0e - //TODO VFSQRT V2.D2, V21.D2 // 55f8e16e + VFSQRT V2.D2, V21.D2 // 55f8e16e FSQRTS F0, F9 // 09c0211e FSQRTD F14, F27 // dbc1611e FSUBS F25, F23, F0 // e03a391e @@ -762,5 +762,6 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 VMOV V0.B[1], R11 // 0b3c030e VMOV V1.H[3], R12 // 2c3c0e0e VUSHR $6, V22.H8, V23.H8 // d7061a6f + SB // ff3003d5 RET diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index ce88e3ca540f13..25dd523479d189 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -141,12 +141,27 @@ TEXT errors(SB),$0 VPMULL2 V1.H4, V2.H4, V3.Q1 // ERROR "operand mismatch" VPMULL2 V1.D1, V2.D1, V3.Q1 // ERROR "operand mismatch" VPMULL2 V1.B8, V2.B8, V3.H8 // ERROR "operand mismatch" + VPMULL2 V0.H8, V1.H8, V21.S4 // ERROR "invalid arrangement" + VUMULL V0.D1, V1.D1, V7.Q1 // ERROR "invalid arrangement" + VUMULL2 V0.B8, V1.B8, V21.H8 // ERROR "operand mismatch" + VUMLAL2 V0.D2, V1.D2, V7.Q1 // ERROR "invalid arrangement" + VUMLAL V0.H4, V1.H4, V21.H4 // ERROR "operand mismatch" + VUMLSL V0.H8, V1.H8, V21.H8 // ERROR "operand mismatch" + VSMULL2 V0.D2, V1.D2, V7.Q1 // ERROR "invalid arrangement" + VSMULL V0.B8, V1.B8, V5.B8 // ERROR "operand mismatch" + VSMLAL2 V0.D2, V1.D2, V7.Q1 // ERROR "invalid arrangement" + VSMLAL V0.S2, V1.S2, V21.S2 // ERROR "operand mismatch" + VSMLSL2 V0.B8, V1.B8, V6.H8 // ERROR "operand mismatch" VEXT $8, V1.B16, V2.B8, V2.B16 // ERROR "invalid arrangement" VEXT $8, V1.H8, V2.H8, V2.H8 // ERROR "invalid arrangement" VRBIT V1.B16, V2.B8 // ERROR "invalid arrangement" VRBIT V1.H4, V2.H4 // ERROR "invalid arrangement" VUSHR $56, V1.D2, V2.H4 // ERROR "invalid arrangement" VUSHR $127, V1.D2, V2.D2 // ERROR "shift out of range" + VSSHR $127, V1.D2, V2.D2 // ERROR "shift out of range" + VSSHR $56, V1.D2, V2.H4 // ERROR "invalid arrangement" + VSRSHR $127, V1.D2, V2.D2 // ERROR "shift out of range" + VSRSHR $56, V1.D2, V2.H4 // ERROR "invalid arrangement" VLD1.P (R8)(R9.SXTX<<2), [V2.B16] // ERROR "invalid extended register" VLD1.P (R8)(R9<<2), [V2.B16] // ERROR "invalid extended register" VST1.P [V1.B16], (R8)(R9.UXTW) // ERROR "invalid extended register" @@ -363,6 +378,8 @@ TEXT errors(SB),$0 VUXTL V30.D2, V30.H8 // ERROR "operand mismatch" VUXTL2 V20.B8, V21.H8 // ERROR "operand mismatch" VUXTL V3.D2, V4.B8 // ERROR "operand mismatch" + VSXTL V3.D2, V4.B8 // ERROR "operand mismatch" + VSXTL2 V20.B8, V21.H8 // ERROR "operand mismatch" VUZP1 V0.B8, V30.B8, V1.B16 // ERROR "operand mismatch" VUZP2 V0.Q1, V30.Q1, V1.Q1 // ERROR "invalid arrangement" VUSHLL $0, V30.D2, V30.H8 // ERROR "operand mismatch" @@ -377,8 +394,26 @@ TEXT errors(SB),$0 VUMIN V1.D2, V2.D2, V3.D2 // ERROR "invalid arrangement" VUMAX V1.B8, V2.B8, V3.B16 // ERROR "operand mismatch" VUMIN V1.H4, V2.S4, V3.H4 // ERROR "operand mismatch" + VSMAX V1.D2, V2.D2, V3.D2 // ERROR "invalid arrangement" + VSMIN V1.D2, V2.D2, V3.D2 // ERROR "invalid arrangement" + VSMAX V1.B8, V2.B8, V3.B16 // ERROR "operand mismatch" + VSMIN V1.H4, V2.S4, V3.H4 // ERROR "operand mismatch" + VSMAXP V1.D2, V2.D2, V3.D2 // ERROR "invalid arrangement" + VSMINP V1.D2, V2.D2, V3.D2 // ERROR "invalid arrangement" + VUMAXP V1.D2, V2.D2, V3.D2 // ERROR "invalid arrangement" + VUMINP V1.D2, V2.D2, V3.D2 // ERROR "invalid arrangement" + VFMAX V1.B8, V2.B8, V3.B8 // ERROR "invalid arrangement" + VFMIN V1.B16, V2.B16, V3.B16 // ERROR "invalid arrangement" + VFADDP V1.B8, V2.B8, V3.B8 // ERROR "invalid arrangement" + VFADDP V1.B16, V2.B16, V3.B16 // ERROR "invalid arrangement" + VFADDP V1.H4, V2.H4, V3.H4 // ERROR "invalid arrangement" + VFADDP V1.H8, V2.H8, V3.H8 // ERROR "invalid arrangement" VSLI $64, V7.D2, V8.D2 // ERROR "shift out of range" VUSRA $0, V7.D2, V8.D2 // ERROR "shift out of range" + VSSHL V1.B8, V2.B8, V3.B16 // ERROR "operand mismatch" + VUSHL V1.B8, V2.B8, V3.B16 // ERROR "operand mismatch" + VSQSHL V1.B8, V2.B8, V3.B16 // ERROR "operand mismatch" + VUQSHL V1.B8, V2.B8, V3.B16 // ERROR "operand mismatch" CASPD (R3, R4), (R2), (R8, R9) // ERROR "source register pair must start from even register" CASPD (R2, R3), (R2), (R9, R10) // ERROR "destination register pair must start from even register" CASPD (R2, R4), (R2), (R8, R9) // ERROR "source register pair must be contiguous" @@ -428,4 +463,66 @@ TEXT errors(SB),$0 AUTIBSP C // ERROR "illegal combination" AUTIA1716 $45 // ERROR "illegal combination" AUTIB1716 R0 // ERROR "illegal combination" + SB $1 // ERROR "illegal combination" + RPRFM (R1), RSP, PLDKEEP // ERROR "illegal combination" + RPRFM 2(RSP), R4, PSTSTRM // ERROR "illegal combination" + RPRFM (R2), R3, $100 // ERROR "range prefetch immediate must be 0 to 63" + RPRFM (R5), R6, PLDL1KEEP // ERROR "illegal range prefetch operand" + + // VMUL family invalid arrangement tests + VMUL V0.D2, V0.D2, V1.D2 // ERROR "invalid arrangement" + VMLA V0.D2, V0.D2, V1.D2 // ERROR "invalid arrangement" + VMLS V0.D2, V0.D2, V1.D2 // ERROR "invalid arrangement" + // VMUL family operand mismatch tests + VMUL V0.S4, V0.D2, V1.S4 // ERROR "operand mismatch" + VMLA V0.H4, V0.S4, V1.H4 // ERROR "operand mismatch" + VMLS V0.B8, V0.H4, V1.B8 // ERROR "operand mismatch" + // VBIC/VORN family invalid arrangement tests + VBIC V0.S4, V0.S4, V1.S4 // ERROR "invalid arrangement" + VBIC V0.H4, V0.H4, V1.H4 // ERROR "invalid arrangement" + VBIC V0.D2, V0.D2, V1.D2 // ERROR "invalid arrangement" + VORN V0.S4, V0.S4, V1.S4 // ERROR "invalid arrangement" + VORN V0.H4, V0.H4, V1.H4 // ERROR "invalid arrangement" + VORN V0.D2, V0.D2, V1.D2 // ERROR "invalid arrangement" + VSMAXV V0.B8, V0.S4 // ERROR "illegal combination" + VUMAXV V0.S4, V0.H8 // ERROR "illegal combination" + VFMAXV V0.S4, V0.D2 // ERROR "illegal combination" + VFMAXV V0.D2, V0 // ERROR "invalid arrangement" + VFMINV V0.D2, V0 // ERROR "invalid arrangement" + VFMAXNMV V0.D2, V0 // ERROR "invalid arrangement" + VFMINNMV V0.D2, V0 // ERROR "invalid arrangement" + VFMAXV V0.S2, V0 // ERROR "invalid arrangement" + VFMINV V0.S2, V0 // ERROR "invalid arrangement" + VFMAXNMV V0.S2, V0 // ERROR "invalid arrangement" + VFMINNMV V0.S2, V0 // ERROR "invalid arrangement" + VFMAXV V0.H4, V0 // ERROR "invalid arrangement" + VFMAXV V0.H8, V0 // ERROR "invalid arrangement" + VFMINV V0.H4, V0 // ERROR "invalid arrangement" + VFMINV V0.H8, V0 // ERROR "invalid arrangement" + VFMAXNMV V0.H4, V0 // ERROR "invalid arrangement" + VFMAXNMV V0.H8, V0 // ERROR "invalid arrangement" + VFMINNMV V0.H4, V0 // ERROR "invalid arrangement" + VFMINNMV V0.H8, V0 // ERROR "invalid arrangement" + + // Shifts and misc. conversion error test cases + VXTN V1.B8, V0.B8 // ERROR "invalid arrangement" + VXTN2 V1.H8, V0.B8 // ERROR "invalid arrangement" + VSHRN $8, V1.B8, V0.B8 // ERROR "invalid arrangement" + VSHRN $8, V1.S4, V0.S4 // ERROR "invalid arrangement" + VSHRN $8, V1.H8, V0.H8 // ERROR "invalid arrangement" + VSHRN2 $8, V1.B8, V0.B16 // ERROR "invalid arrangement" + VSHRN2 $8, V1.S4, V0.S4 // ERROR "invalid arrangement" + VSHRN2 $8, V1.H8, V0.H8 // ERROR "invalid arrangement" + VSSHLL $0, V1.D2, V2.H8 // ERROR "operand mismatch" + VSSHLL2 $0, V1.B8, V2.H8 // ERROR "operand mismatch" + VSSHLL $8, V1.B8, V2.H8 // ERROR "shift amount out of range" + VSQXTN V1.B8, V0.B8 // ERROR "invalid arrangement" + VSQXTN2 V1.H8, V0.B8 // ERROR "invalid arrangement" + VSQXTUN V1.B8, V0.B8 // ERROR "invalid arrangement" + VUQXTN V1.B8, V0.B8 // ERROR "invalid arrangement" + VFCVTZS V1.B8, V2.B8 // ERROR "invalid arrangement" + VFCVTZU V1.H4, V2.H4 // ERROR "invalid arrangement" + VSCVTF V1.B8, V2.B8 // ERROR "invalid arrangement" + VFCVTN V1.B8, V2.B8 // ERROR "invalid arrangement" + VFCVTL V1.H4, V2.S4 // ERROR "operand mismatch" RET diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s new file mode 100644 index 00000000000000..8fb275c59d57e9 --- /dev/null +++ b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s @@ -0,0 +1,1401 @@ +// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT. + +#include "../../../../../runtime/textflag.h" + +TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 + PAND P4.B, P2.B, P1.Z, P14.B // 4e440425 + PANDS P4.B, P2.B, P1.Z, P14.B // 4e444425 + PBIC P4.B, P2.B, P1.Z, P14.B // 5e440425 + PBICS P4.B, P2.B, P1.Z, P14.B // 5e444425 + PBRKA P5.B, P9.Z, P2.B // a2641025 + PBRKAS P5.B, P9.Z, P4.B // a4645025 + PBRKB P5.B, P9.Z, P2.B // a2649025 + PBRKBS P5.B, P9.Z, P4.B // a464d025 + PBRKN P4.B, P2.B, P1.Z, P4.B // 44441825 + PBRKNS P4.B, P2.B, P1.Z, P4.B // 44445825 + PBRKPA P4.B, P2.B, P1.Z, P14.B // 4ec40425 + PBRKPAS P4.B, P2.B, P1.Z, P14.B // 4ec44425 + PBRKPB P4.B, P2.B, P1.Z, P14.B // 5ec40425 + PBRKPBS P4.B, P2.B, P1.Z, P14.B // 5ec44425 + PEOR P4.B, P2.B, P1.Z, P14.B // 4e460425 + PEORS P4.B, P2.B, P1.Z, P14.B // 4e464425 + PNAND P4.B, P2.B, P1.Z, P14.B // 5e468425 + PNANDS P4.B, P2.B, P1.Z, P14.B // 5e46c425 + PNOR P4.B, P2.B, P1.Z, P14.B // 4e468425 + PNORS P4.B, P2.B, P1.Z, P14.B // 4e46c425 + PORN P4.B, P2.B, P1.Z, P14.B // 5e448425 + PORNS P4.B, P2.B, P1.Z, P14.B // 5e44c425 + PORR P4.B, P2.B, P1.Z, P14.B // 4e448425 + PORRS P4.B, P2.B, P1.Z, P14.B // 4e44c425 + PPFALSE P13.B // 0de41825 + PPFIRST P5.B, P9, P5.B // 25c15825 + PPNEXT P5.D, P4, P5.D // 85c4d925 + PPTEST P14.B, P0 // c0c15025 + PPTRUE PN14.S // 1678a025 + PPUNPKHI P14.B, P0.H // c0413105 + PPUNPKLO P14.B, P0.H // c0413005 + PRDFFR P14.Z, P0.B // c0f11825 + PRDFFR P13.B // 0df01925 + PRDFFRS P14.Z, P0.B // c0f15825 + PREV P14.S, P13.S // cd41b405 + PSEL P4.B, P2.B, P1, P14.B // 5e460425 + PTRN1 P5.D, P4.D, P2.D // 8250e505 + PTRN2 P5.D, P4.D, P2.D // 8254e505 + PUZP1 P5.D, P4.D, P2.D // 8248e505 + PUZP2 P5.D, P4.D, P2.D // 824ce505 + PWRFFR P13.B // a0912825 + PZIP1 P5.D, P4.D, P2.D // 8240e505 + PZIP2 P5.D, P4.D, P2.D // 8244e505 + SETFFR // 00902c25 + ZABS Z7.D, P4.M, Z13.D // edb0d604 + ZABS Z7.D, P4.Z, Z13.D // edb0c604 + ZADCLB Z7.D, Z23.D, Z13.D // edd24745 + ZADCLT Z7.D, Z23.D, Z13.D // edd64745 + ZADD Z15.B, Z0.B, P3.M, Z0.B // e00d0004 + ZADD Z7.D, Z23.D, Z13.D // ed02e704 + ZADDHNB Z22.S, Z10.S, Z8.H // 4861b645 + ZADDHNT Z22.S, Z10.S, Z8.H // 4865b645 + ZADDP Z15.B, Z0.B, P3.M, Z0.B // e0ad1144 + ZADDPT Z23.D, Z13.D, P1.M, Z13.D // ed06c404 + ZADDPT Z7.D, Z6.D, Z23.D // d708e704 + // TODO: ADDQP + ZADDQV Z25.S, P3, V5.S4 // 252f8504 + // TODO: ADDSUBP + ZAESD Z7.B, Z6.B, Z6.B // e6e42245 + ZAESE Z7.B, Z6.B, Z6.B // e6e02245 + ZAESIMC Z11.B, Z11.B // 0be42045 + ZAESMC Z11.B, Z11.B // 0be02045 + ZAND Z15.B, Z0.B, P3.M, Z0.B // e00d1a04 + ZAND Z7.D, Z6.D, Z23.D // d7302704 + ZANDQV Z25.S, P3, V5.S4 // 252f9e04 + ZASR Z15.B, Z0.B, P3.M, Z0.B // e08d1004 + ZASR Z2.D, Z10.D, P3.M, Z10.D // 4a8cd004 + ZASR Z7.D, Z6.H, Z13.H // cd806704 + ZASRR Z15.B, Z0.B, P3.M, Z0.B // e08d1404 + ZBCAX Z23.D, Z13.D, Z21.D, Z21.D // f53a6d04 + ZBDEP Z7.D, Z23.D, Z13.D // edb6c745 + ZBEXT Z7.D, Z23.D, Z13.D // edb2c745 + ZBF1CVT Z11.B, Z6.H // 66390865 + ZBF1CVTLT Z11.B, Z6.H // 66390965 + ZBF2CVT Z11.B, Z6.H // 663d0865 + ZBF2CVTLT Z11.B, Z6.H // 663d0965 + ZBFADD Z23.H, Z13.H, P1.M, Z13.H // ed860065 + ZBFADD Z7.H, Z6.H, Z23.H // d7000765 + ZBFCLAMP Z7.H, Z6.H, Z23.H // d7242764 + ZBFCVT Z13.S, P1.M, Z22.H // b6a58a65 + ZBFCVT Z13.S, P1.Z, Z22.H // b6c59a64 + ZBFCVTNT Z13.S, P1.M, Z22.H // b6a58a64 + ZBFCVTNT Z13.S, P1.Z, Z22.H // b6a58264 + ZBFDOT Z7.H, Z6.H, Z23.S // d7806764 + ZBFMAX Z23.H, Z13.H, P1.M, Z13.H // ed860665 + ZBFMAXNM Z23.H, Z13.H, P1.M, Z13.H // ed860465 + ZBFMIN Z23.H, Z13.H, P1.M, Z13.H // ed860765 + ZBFMINNM Z23.H, Z13.H, P1.M, Z13.H // ed860565 + ZBFMLA Z23.H, Z13.H, P1.M, Z22.H // b6053765 + ZBFMLALB Z7.H, Z6.H, Z23.S // d780e764 + ZBFMLALT Z7.H, Z6.H, Z23.S // d784e764 + ZBFMLS Z23.H, Z13.H, P1.M, Z22.H // b6253765 + ZBFMLSLB Z7.H, Z6.H, Z23.S // d7a0e764 + ZBFMLSLT Z7.H, Z6.H, Z23.S // d7a4e764 + // TODO: BFMMLA .H, .H, .H + ZBFMMLA Z7.H, Z6.H, Z23.S // d7e46764 + ZBFMUL Z23.H, Z13.H, P1.M, Z13.H // ed860265 + ZBFMUL Z7.H, Z6.H, Z23.H // d7080765 + ZBFSCALE Z23.H, Z13.H, P1.M, Z13.H // ed860965 + ZBFSUB Z23.H, Z13.H, P1.M, Z13.H // ed860165 + ZBFSUB Z7.H, Z6.H, Z23.H // d7040765 + ZBGRP Z7.D, Z23.D, Z13.D // edbac745 + ZBIC Z15.B, Z0.B, P3.M, Z0.B // e00d1b04 + ZBIC Z7.D, Z6.D, Z23.D // d730e704 + ZBSL Z23.D, Z13.D, Z21.D, Z21.D // f53e2d04 + ZBSL1N Z23.D, Z13.D, Z21.D, Z21.D // f53e6d04 + ZBSL2N Z23.D, Z13.D, Z21.D, Z21.D // f53ead04 + ZCLASTA Z15.B, Z0.B, P3, Z0.B // e08d2805 + ZCLASTB Z15.B, Z0.B, P3, Z0.B // e08d2905 + ZCLS Z7.D, P4.M, Z13.D // edb0d804 + ZCLS Z7.D, P4.Z, Z13.D // edb0c804 + ZCLZ Z7.D, P4.M, Z13.D // edb0d904 + ZCLZ Z7.D, P4.Z, Z13.D // edb0c904 + ZCMPEQ Z0.H, Z2.H, P0.Z, P14.H // 4ea04024 + ZCMPEQ Z0.D, Z12.S, P0.Z, P14.S // 8e218024 + ZCMPGE Z0.H, Z2.H, P0.Z, P14.H // 4e804024 + ZCMPGE Z0.D, Z12.S, P0.Z, P14.S // 8e418024 + ZCMPGT Z0.H, Z2.H, P0.Z, P14.H // 5e804024 + ZCMPGT Z0.D, Z12.S, P0.Z, P14.S // 9e418024 + ZCMPHI Z0.H, Z2.H, P0.Z, P14.H // 5e004024 + ZCMPHI Z0.D, Z12.S, P0.Z, P14.S // 9ec18024 + ZCMPHS Z0.H, Z2.H, P0.Z, P14.H // 4e004024 + ZCMPHS Z0.D, Z12.S, P0.Z, P14.S // 8ec18024 + // TODO: CMPLE + // TODO: CMPLO + // TODO: CMPLS + // TODO: CMPLT + ZCMPNE Z0.H, Z2.H, P0.Z, P14.H // 5ea04024 + ZCMPNE Z0.D, Z12.S, P0.Z, P14.S // 9e218024 + ZCNOT Z7.D, P4.M, Z13.D // edb0db04 + ZCNOT Z7.D, P4.Z, Z13.D // edb0cb04 + ZCNT Z7.D, P4.M, Z13.D // edb0da04 + ZCNT Z7.D, P4.Z, Z13.D // edb0ca04 + ZCOMPACT Z7.D, P4, Z13.D // ed90e105 + ZCOMPACT Z7.D, P4, Z13.D // ed90e105 + ZDECP P14.S, Z26.S // da81ad25 + ZEOR Z15.B, Z0.B, P3.M, Z0.B // e00d1904 + ZEOR Z7.D, Z6.D, Z23.D // d730a704 + ZEOR3 Z23.D, Z13.D, Z21.D, Z21.D // f53a2d04 + ZEORBT Z7.D, Z23.D, Z13.D // ed92c745 + ZEORQV Z25.S, P3, V5.S4 // 252f9d04 + ZEORTB Z7.D, Z23.D, Z13.D // ed96c745 + ZEXPAND Z7.D, P4, Z13.D // ed90f105 + ZF1CVT Z11.B, Z6.H // 66310865 + ZF1CVTLT Z11.B, Z6.H // 66310965 + ZF2CVT Z11.B, Z6.H // 66350865 + ZF2CVTLT Z11.B, Z6.H // 66350965 + ZFABD Z25.S, Z2.S, P1.M, Z2.S // 22878865 + ZFABS Z7.D, P4.M, Z13.D // edb0dc04 + ZFABS Z7.D, P4.Z, Z13.D // edb0cc04 + ZFACGE Z0.H, Z2.H, P0.Z, P14.H // 5ec04065 + ZFACGT Z0.H, Z2.H, P0.Z, P14.H // 5ee04065 + ZFADD Z25.S, Z2.S, P1.M, Z2.S // 22878065 + ZFADD Z7.D, Z23.D, Z13.D // ed02c765 + ZFADDP Z25.S, Z2.S, P1.M, Z2.S // 22879064 + ZFADDQV Z25.S, P3, V5.S4 // 25af9064 + ZFAMAX Z25.S, Z2.S, P1.M, Z2.S // 22878e65 + ZFAMIN Z25.S, Z2.S, P1.M, Z2.S // 22878f65 + ZFCLAMP Z7.D, Z23.D, Z13.D // ed26e764 + ZFCMEQ Z0.H, Z2.H, P0.Z, P14.H // 4e604065 + ZFCMGE Z0.H, Z2.H, P0.Z, P14.H // 4e404065 + ZFCMGT Z0.H, Z2.H, P0.Z, P14.H // 5e404065 + ZFCMNE Z0.H, Z2.H, P0.Z, P14.H // 5e604065 + ZFCMUO Z0.H, Z2.H, P0.Z, P14.H // 4ec04065 + ZFCVT Z13.H, P1.M, Z22.S // b6a58965 + ZFCVT Z13.H, P1.Z, Z22.S // b6a59a64 + ZFCVT Z13.H, P1.M, Z22.D // b6a5c965 + ZFCVT Z13.H, P1.Z, Z22.D // b6a5da64 + ZFCVT Z13.S, P1.M, Z22.H // b6a58865 + ZFCVT Z13.S, P1.Z, Z22.H // b6859a64 + ZFCVT Z13.S, P1.M, Z22.D // b6a5cb65 + ZFCVT Z13.S, P1.Z, Z22.D // b6e5da64 + ZFCVT Z13.D, P1.M, Z22.H // b6a5c865 + ZFCVT Z13.D, P1.Z, Z22.H // b685da64 + ZFCVT Z13.D, P1.M, Z22.S // b6a5ca65 + ZFCVT Z13.D, P1.Z, Z22.S // b6c5da64 + ZFCVTLT Z13.H, P1.M, Z22.S // b6a58964 + ZFCVTLT Z13.H, P1.Z, Z22.S // b6a58164 + ZFCVTLT Z13.S, P1.M, Z22.D // b6a5cb64 + ZFCVTLT Z13.S, P1.Z, Z22.D // b6a5c364 + ZFCVTNT Z13.S, P1.M, Z22.H // b6a58864 + ZFCVTNT Z13.S, P1.Z, Z22.H // b6a58064 + ZFCVTNT Z13.D, P1.M, Z22.S // b6a5ca64 + ZFCVTNT Z13.D, P1.Z, Z22.S // b6a5c264 + ZFCVTX Z13.D, P1.M, Z22.S // b6a50a65 + ZFCVTX Z13.D, P1.Z, Z22.S // b6c51a64 + ZFCVTXNT Z13.D, P1.M, Z22.S // b6a50a64 + ZFCVTXNT Z13.D, P1.Z, Z22.S // b6a50264 + ZFCVTZS Z13.H, P1.M, Z22.H // b6a55a65 + ZFCVTZS Z13.H, P1.Z, Z22.H // b6c55e64 + ZFCVTZS Z13.H, P1.M, Z22.S // b6a55c65 + ZFCVTZS Z13.H, P1.Z, Z22.S // b6855f64 + ZFCVTZS Z13.H, P1.M, Z22.D // b6a55e65 + ZFCVTZS Z13.H, P1.Z, Z22.D // b6c55f64 + ZFCVTZS Z13.S, P1.M, Z22.S // b6a59c65 + ZFCVTZS Z13.S, P1.Z, Z22.S // b6859f64 + ZFCVTZS Z13.S, P1.M, Z22.D // b6a5dc65 + ZFCVTZS Z13.S, P1.Z, Z22.D // b685df64 + ZFCVTZS Z13.D, P1.M, Z22.S // b6a5d865 + ZFCVTZS Z13.D, P1.Z, Z22.S // b685de64 + ZFCVTZS Z13.D, P1.M, Z22.D // b6a5de65 + ZFCVTZS Z13.D, P1.Z, Z22.D // b6c5df64 + ZFCVTZU Z13.H, P1.M, Z22.H // b6a55b65 + ZFCVTZU Z13.H, P1.Z, Z22.H // b6e55e64 + ZFCVTZU Z13.H, P1.M, Z22.S // b6a55d65 + ZFCVTZU Z13.H, P1.Z, Z22.S // b6a55f64 + ZFCVTZU Z13.H, P1.M, Z22.D // b6a55f65 + ZFCVTZU Z13.H, P1.Z, Z22.D // b6e55f64 + ZFCVTZU Z13.S, P1.M, Z22.S // b6a59d65 + ZFCVTZU Z13.S, P1.Z, Z22.S // b6a59f64 + ZFCVTZU Z13.S, P1.M, Z22.D // b6a5dd65 + ZFCVTZU Z13.S, P1.Z, Z22.D // b6a5df64 + ZFCVTZU Z13.D, P1.M, Z22.S // b6a5d965 + ZFCVTZU Z13.D, P1.Z, Z22.S // b6a5de64 + ZFCVTZU Z13.D, P1.M, Z22.D // b6a5df65 + ZFCVTZU Z13.D, P1.Z, Z22.D // b6e5df64 + ZFDIV Z25.S, Z2.S, P1.M, Z2.S // 22878d65 + ZFDIVR Z25.S, Z2.S, P1.M, Z2.S // 22878c65 + ZFDOT Z7.H, Z6.H, Z23.S // d7802764 + ZFDOT Z7.B, Z6.B, Z23.H // d7842764 + ZFDOT Z7.B, Z6.B, Z23.S // d7846764 + ZFEXPA Z1.S, Z26.S // 3ab8a004 + ZFLOGB Z7.D, P4.M, Z13.D // edb01e65 + ZFLOGB Z7.D, P4.Z, Z13.D // edf01e64 + ZFMAD Z0.H, Z2.H, P0.M, Z14.H // 4e806065 + ZFMAX Z25.S, Z2.S, P1.M, Z2.S // 22878665 + ZFMAXNM Z25.S, Z2.S, P1.M, Z2.S // 22878465 + ZFMAXNMP Z25.S, Z2.S, P1.M, Z2.S // 22879464 + ZFMAXNMQV Z25.S, P3, V5.S4 // 25af9464 + ZFMAXP Z25.S, Z2.S, P1.M, Z2.S // 22879664 + ZFMAXQV Z25.S, P3, V5.S4 // 25af9664 + ZFMIN Z25.S, Z2.S, P1.M, Z2.S // 22878765 + ZFMINNM Z25.S, Z2.S, P1.M, Z2.S // 22878565 + ZFMINNMP Z25.S, Z2.S, P1.M, Z2.S // 22879564 + ZFMINNMQV Z25.S, P3, V5.S4 // 25af9564 + ZFMINP Z25.S, Z2.S, P1.M, Z2.S // 22879764 + ZFMINQV Z25.S, P3, V5.S4 // 25af9764 + ZFMLA Z0.H, Z2.H, P0.M, Z14.H // 4e006065 + ZFMLALB Z7.H, Z6.H, Z23.S // d780a764 + ZFMLALB Z7.B, Z6.B, Z23.H // d788a764 + ZFMLALLBB Z7.B, Z6.B, Z23.S // d7882764 + ZFMLALLBT Z7.B, Z6.B, Z23.S // d7982764 + ZFMLALLTB Z7.B, Z6.B, Z23.S // d7a82764 + ZFMLALLTT Z7.B, Z6.B, Z23.S // d7b82764 + ZFMLALT Z7.H, Z6.H, Z23.S // d784a764 + ZFMLALT Z7.B, Z6.B, Z23.H // d798a764 + ZFMLS Z0.H, Z2.H, P0.M, Z14.H // 4e206065 + ZFMLSLB Z7.H, Z6.H, Z23.S // d7a0a764 + ZFMLSLT Z7.H, Z6.H, Z23.S // d7a4a764 + // TODO: FMMLA .H, .H, .H + ZFMMLA Z7.S, Z6.S, Z23.S // d7e4a764 + ZFMMLA Z7.D, Z6.D, Z23.D // d7e4e764 + ZFMMLA Z7.H, Z6.H, Z23.S // d7e42764 + ZFMMLA Z7.B, Z6.B, Z23.H // d7e06764 + ZFMMLA Z7.B, Z6.B, Z23.S // d7e02764 + ZFMSB Z0.H, Z2.H, P0.M, Z14.H // 4ea06065 + ZFMUL Z25.S, Z2.S, P1.M, Z2.S // 22878265 + ZFMUL Z7.D, Z23.D, Z13.D // ed0ac765 + ZFMULX Z25.S, Z2.S, P1.M, Z2.S // 22878a65 + ZFNEG Z7.D, P4.M, Z13.D // edb0dd04 + ZFNEG Z7.D, P4.Z, Z13.D // edb0cd04 + ZFNMAD Z0.H, Z2.H, P0.M, Z14.H // 4ec06065 + ZFNMLA Z0.H, Z2.H, P0.M, Z14.H // 4e406065 + ZFNMLS Z0.H, Z2.H, P0.M, Z14.H // 4e606065 + ZFNMSB Z0.H, Z2.H, P0.M, Z14.H // 4ee06065 + ZFRECPE Z1.S, Z26.S // 3a308e65 + ZFRECPS Z7.D, Z23.D, Z13.D // ed1ac765 + ZFRECPX Z7.D, P4.M, Z13.D // edb0cc65 + ZFRECPX Z7.D, P4.Z, Z13.D // ed90db64 + ZFRINT32X Z7.D, P4.M, Z13.D // edb01365 + ZFRINT32X Z7.D, P4.Z, Z13.D // edf01c64 + ZFRINT32Z Z7.D, P4.M, Z13.D // edb01265 + ZFRINT32Z Z7.D, P4.Z, Z13.D // edd01c64 + ZFRINT64X Z7.D, P4.M, Z13.D // edb01765 + ZFRINT64X Z7.D, P4.Z, Z13.D // edf01d64 + ZFRINT64Z Z7.D, P4.M, Z13.D // edb01665 + ZFRINT64Z Z7.D, P4.Z, Z13.D // edd01d64 + ZFRINTA Z7.D, P4.M, Z13.D // edb0c465 + ZFRINTA Z7.D, P4.Z, Z13.D // ed90d964 + ZFRINTI Z7.D, P4.M, Z13.D // edb0c765 + ZFRINTI Z7.D, P4.Z, Z13.D // edf0d964 + ZFRINTM Z7.D, P4.M, Z13.D // edb0c265 + ZFRINTM Z7.D, P4.Z, Z13.D // edd0d864 + ZFRINTN Z7.D, P4.M, Z13.D // edb0c065 + ZFRINTN Z7.D, P4.Z, Z13.D // ed90d864 + ZFRINTP Z7.D, P4.M, Z13.D // edb0c165 + ZFRINTP Z7.D, P4.Z, Z13.D // edb0d864 + ZFRINTX Z7.D, P4.M, Z13.D // edb0c665 + ZFRINTX Z7.D, P4.Z, Z13.D // edd0d964 + ZFRINTZ Z7.D, P4.M, Z13.D // edb0c365 + ZFRINTZ Z7.D, P4.Z, Z13.D // edf0d864 + ZFRSQRTE Z1.S, Z26.S // 3a308f65 + ZFRSQRTS Z7.D, Z23.D, Z13.D // ed1ec765 + ZFSCALE Z25.S, Z2.S, P1.M, Z2.S // 22878965 + ZFSQRT Z7.D, P4.M, Z13.D // edb0cd65 + ZFSQRT Z7.D, P4.Z, Z13.D // edb0db64 + ZFSUB Z25.S, Z2.S, P1.M, Z2.S // 22878165 + ZFSUB Z7.D, Z23.D, Z13.D // ed06c765 + ZFSUBR Z25.S, Z2.S, P1.M, Z2.S // 22878365 + ZFTSMUL Z7.D, Z23.D, Z13.D // ed0ec765 + ZFTSSEL Z7.D, Z23.D, Z13.D // edb2e704 + ZHISTCNT Z19.S, Z20.S, P1.Z, Z2.S // 82c6b345 + ZHISTSEG Z7.B, Z6.B, Z23.B // d7a02745 + ZINCP P14.S, Z26.S // da81ac25 + ZLSL Z15.B, Z0.B, P3.M, Z0.B // e08d1304 + ZLSL Z2.D, Z10.D, P3.M, Z10.D // 4a8cd304 + ZLSL Z7.D, Z6.H, Z13.H // cd8c6704 + ZLSLR Z15.B, Z0.B, P3.M, Z0.B // e08d1704 + ZLSR Z15.B, Z0.B, P3.M, Z0.B // e08d1104 + ZLSR Z2.D, Z10.D, P3.M, Z10.D // 4a8cd104 + ZLSR Z7.D, Z6.H, Z13.H // cd846704 + ZLSRR Z15.B, Z0.B, P3.M, Z0.B // e08d1504 + ZMAD Z0.H, Z2.H, P0.M, Z14.H // 0ec04204 + ZMADPT Z7.D, Z6.D, Z23.D // f7d8c644 + ZMATCH Z0.H, Z2.H, P0.Z, P14.H // 4e806045 + ZMLA Z0.H, Z2.H, P0.M, Z14.H // 4e404004 + ZMLAPT Z7.D, Z6.D, Z23.D // d7d0c744 + ZMLS Z0.H, Z2.H, P0.M, Z14.H // 4e604004 + ZMOVPRFX Z7.D, P4.Z, Z21.D // f530d004 + ZMOVPRFX Z11, Z6 // 66bd2004 + ZMSB Z0.H, Z2.H, P0.M, Z14.H // 0ee04204 + ZMUL Z15.B, Z0.B, P3.M, Z0.B // e00d1004 + ZMUL Z7.D, Z23.D, Z13.D // ed62e704 + ZNBSL Z23.D, Z13.D, Z21.D, Z21.D // f53eed04 + ZNEG Z7.D, P4.M, Z13.D // edb0d704 + ZNEG Z7.D, P4.Z, Z13.D // edb0c704 + ZNMATCH Z0.H, Z2.H, P0.Z, P14.H // 5e806045 + ZNOT Z7.D, P4.M, Z13.D // edb0de04 + ZNOT Z7.D, P4.Z, Z13.D // edb0ce04 + ZORQV Z25.S, P3, V5.S4 // 252f9c04 + ZORR Z15.B, Z0.B, P3.M, Z0.B // e00d1804 + ZORR Z7.D, Z6.D, Z23.D // d7306704 + ZPMOV Z11, P0.B // 60392a05 + ZPMOV P14.B, Z6 // c6392b05 + ZPMUL Z7.B, Z6.B, Z23.B // d7642704 + ZPMULLB Z8.B, Z4.B, Z30.H // 9e684845 + ZPMULLB Z7.D, Z6.D, Z23.Q // d7680745 + ZPMULLT Z8.B, Z4.B, Z30.H // 9e6c4845 + ZPMULLT Z7.D, Z6.D, Z23.Q // d76c0745 + ZRADDHNB Z22.S, Z10.S, Z8.H // 4869b645 + ZRADDHNT Z22.S, Z10.S, Z8.H // 486db645 + ZRAX1 Z7.D, Z6.D, Z23.D // d7f42745 + ZRBIT Z7.D, P4.M, Z13.D // ed90e705 + ZRBIT Z7.D, P4.Z, Z13.D // edb0e705 + ZREV Z1.S, Z26.S // 3a38b805 + ZREVB Z7.D, P4.M, Z13.D // ed90e405 + ZREVB Z7.D, P4.Z, Z13.D // edb0e405 + ZREVD Z13.Q, P1.M, Z22.Q // b6852e05 + ZREVD Z13.Q, P1.Z, Z22.Q // b6a52e05 + ZREVH Z7.D, P4.M, Z13.D // ed90e505 + ZREVH Z7.D, P4.Z, Z13.D // edb0e505 + ZREVW Z13.D, P1.M, Z22.D // b685e605 + ZREVW Z13.D, P1.Z, Z22.D // b6a5e605 + ZRSUBHNB Z22.S, Z10.S, Z8.H // 4879b645 + ZRSUBHNT Z22.S, Z10.S, Z8.H // 487db645 + ZSABA Z7.D, Z23.D, Z13.D // edfac745 + // TODO: SABAL ., ., . + ZSABALB Z8.B, Z4.B, Z30.H // 9ec04845 + ZSABALT Z8.B, Z4.B, Z30.H // 9ec44845 + ZSABD Z15.B, Z0.B, P3.M, Z0.B // e00d0c04 + ZSABDLB Z8.B, Z4.B, Z30.H // 9e304845 + ZSABDLT Z8.B, Z4.B, Z30.H // 9e344845 + ZSADALP Z14.S, P1.M, Z1.D // c1a5c444 + ZSADDLB Z8.B, Z4.B, Z30.H // 9e004845 + ZSADDLBT Z8.B, Z4.B, Z30.H // 9e804845 + ZSADDLT Z8.B, Z4.B, Z30.H // 9e044845 + ZSADDWB Z22.S, Z10.D, Z5.D // 4541d645 + ZSADDWT Z22.S, Z10.D, Z5.D // 4545d645 + ZSBCLB Z7.D, Z23.D, Z13.D // edd2c745 + ZSBCLT Z7.D, Z23.D, Z13.D // edd6c745 + ZSCLAMP Z7.D, Z23.D, Z13.D // edc2c744 + // TODO: SCVTF ., . + ZSCVTF Z13.H, P1.M, Z22.H // b6a55265 + ZSCVTF Z13.H, P1.Z, Z22.H // b6c55c64 + ZSCVTF Z13.S, P1.M, Z22.H // b6a55465 + ZSCVTF Z13.S, P1.Z, Z22.H // b6855d64 + ZSCVTF Z13.S, P1.M, Z22.S // b6a59465 + ZSCVTF Z13.S, P1.Z, Z22.S // b6859d64 + ZSCVTF Z13.S, P1.M, Z22.D // b6a5d065 + ZSCVTF Z13.S, P1.Z, Z22.D // b685dc64 + ZSCVTF Z13.D, P1.M, Z22.H // b6a55665 + ZSCVTF Z13.D, P1.Z, Z22.H // b6c55d64 + ZSCVTF Z13.D, P1.M, Z22.S // b6a5d465 + ZSCVTF Z13.D, P1.Z, Z22.S // b685dd64 + ZSCVTF Z13.D, P1.M, Z22.D // b6a5d665 + ZSCVTF Z13.D, P1.Z, Z22.D // b6c5dd64 + // TODO: SCVTFLT + ZSDIV Z25.S, Z2.S, P1.M, Z2.S // 22079404 + ZSDIVR Z25.S, Z2.S, P1.M, Z2.S // 22079604 + // TODO: SDOT .H, .B, .B + ZSDOT Z7.H, Z6.H, Z23.S // d7c80744 + ZSDOT Z15.B, Z0.B, Z12.S // 0c008f44 + ZSEL Z23.B, Z21.B, P14, Z2.B // a2fa3705 + ZSHADD Z15.B, Z0.B, P3.M, Z0.B // e08d1044 + ZSHSUB Z15.B, Z0.B, P3.M, Z0.B // e08d1244 + ZSHSUBR Z15.B, Z0.B, P3.M, Z0.B // e08d1644 + ZSM4E Z7.S, Z6.S, Z6.S // e6e02345 + ZSM4EKEY Z7.S, Z6.S, Z23.S // d7f02745 + ZSMAX Z15.B, Z0.B, P3.M, Z0.B // e00d0804 + ZSMAXP Z15.B, Z0.B, P3.M, Z0.B // e0ad1444 + ZSMAXQV Z25.S, P3, V5.S4 // 252f8c04 + ZSMIN Z15.B, Z0.B, P3.M, Z0.B // e00d0a04 + ZSMINP Z15.B, Z0.B, P3.M, Z0.B // e0ad1644 + ZSMINQV Z25.S, P3, V5.S4 // 252f8e04 + ZSMLALB Z8.B, Z4.B, Z30.H // 9e404844 + ZSMLALT Z8.B, Z4.B, Z30.H // 9e444844 + ZSMLSLB Z8.B, Z4.B, Z30.H // 9e504844 + ZSMLSLT Z8.B, Z4.B, Z30.H // 9e544844 + ZSMMLA Z7.B, Z6.B, Z23.S // d7980745 + ZSMULH Z15.B, Z0.B, P3.M, Z0.B // e00d1204 + ZSMULH Z7.D, Z23.D, Z13.D // ed6ae704 + ZSMULLB Z8.B, Z4.B, Z30.H // 9e704845 + ZSMULLT Z8.B, Z4.B, Z30.H // 9e744845 + ZSPLICE Z15.B, Z0.B, P3, Z0.B // e08d2c05 + ZSQABS Z7.D, P4.M, Z13.D // edb0c844 + ZSQABS Z7.D, P4.Z, Z13.D // edb0ca44 + ZSQADD Z15.B, Z0.B, P3.M, Z0.B // e08d1844 + ZSQADD Z7.D, Z23.D, Z13.D // ed12e704 + ZSQDECP P14.S, Z26.S // da81aa25 + ZSQDMLALB Z8.B, Z4.B, Z30.H // 9e604844 + ZSQDMLALBT Z8.B, Z4.B, Z30.H // 9e084844 + ZSQDMLALT Z8.B, Z4.B, Z30.H // 9e644844 + ZSQDMLSLB Z8.B, Z4.B, Z30.H // 9e684844 + ZSQDMLSLBT Z8.B, Z4.B, Z30.H // 9e0c4844 + ZSQDMLSLT Z8.B, Z4.B, Z30.H // 9e6c4844 + ZSQDMULH Z7.D, Z23.D, Z13.D // ed72e704 + ZSQDMULLB Z8.B, Z4.B, Z30.H // 9e604845 + ZSQDMULLT Z8.B, Z4.B, Z30.H // 9e644845 + ZSQINCP P14.S, Z26.S // da81a825 + ZSQNEG Z7.D, P4.M, Z13.D // edb0c944 + ZSQNEG Z7.D, P4.Z, Z13.D // edb0cb44 + ZSQRDMLAH Z7.D, Z23.D, Z13.D // ed72c744 + ZSQRDMLSH Z7.D, Z23.D, Z13.D // ed76c744 + ZSQRDMULH Z7.D, Z23.D, Z13.D // ed76e704 + ZSQRSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0a44 + ZSQRSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0e44 + ZSQSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0844 + ZSQSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0c44 + ZSQSUB Z15.B, Z0.B, P3.M, Z0.B // e08d1a44 + ZSQSUB Z7.D, Z23.D, Z13.D // ed1ae704 + ZSQSUBR Z15.B, Z0.B, P3.M, Z0.B // e08d1e44 + ZSQXTNB Z30.D, Z29.S // dd436045 + ZSQXTNT Z30.D, Z29.S // dd476045 + ZSQXTUNB Z30.D, Z29.S // dd536045 + ZSQXTUNT Z30.D, Z29.S // dd576045 + ZSRHADD Z15.B, Z0.B, P3.M, Z0.B // e08d1444 + ZSRSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0244 + ZSRSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0644 + ZSSUBLB Z8.B, Z4.B, Z30.H // 9e104845 + ZSSUBLBT Z8.B, Z4.B, Z30.H // 9e884845 + ZSSUBLT Z8.B, Z4.B, Z30.H // 9e144845 + ZSSUBLTB Z8.B, Z4.B, Z30.H // 9e8c4845 + ZSSUBWB Z22.S, Z10.D, Z5.D // 4551d645 + ZSSUBWT Z22.S, Z10.D, Z5.D // 4555d645 + ZSUB Z15.B, Z0.B, P3.M, Z0.B // e00d0104 + ZSUB Z7.D, Z23.D, Z13.D // ed06e704 + ZSUBHNB Z22.S, Z10.S, Z8.H // 4871b645 + ZSUBHNT Z22.S, Z10.S, Z8.H // 4875b645 + // TODO: SUBP ., /M, ., . + ZSUBPT Z23.D, Z13.D, P1.M, Z13.D // ed06c504 + ZSUBPT Z7.D, Z6.D, Z23.D // d70ce704 + ZSUBR Z15.B, Z0.B, P3.M, Z0.B // e00d0304 + ZSUNPKHI Z15.B, Z0.H // e0397105 + ZSUNPKLO Z15.B, Z0.H // e0397005 + ZSUQADD Z15.B, Z0.B, P3.M, Z0.B // e08d1c44 + ZSXTB Z7.D, P4.M, Z13.D // edb0d004 + ZSXTB Z7.D, P4.Z, Z13.D // edb0c004 + ZSXTH Z7.D, P4.M, Z13.D // edb0d204 + ZSXTH Z7.D, P4.Z, Z13.D // edb0c204 + ZSXTW Z13.D, P1.M, Z22.D // b6a5d404 + ZSXTW Z13.D, P1.Z, Z22.D // b6a5c404 + ZTBX Z7.D, Z23.D, Z13.D // ed2ee705 + ZTBXQ Z7.D, Z23.D, Z13.D // ed36e705 + ZTRN1 Z7.D, Z23.D, Z13.D // ed72e705 + ZTRN1 Z7.Q, Z6.Q, Z23.Q // d718a705 + ZTRN2 Z7.D, Z23.D, Z13.D // ed76e705 + ZTRN2 Z7.Q, Z6.Q, Z23.Q // d71ca705 + ZUABA Z7.D, Z23.D, Z13.D // edfec745 + // TODO: UABAL ., ., . + ZUABALB Z8.B, Z4.B, Z30.H // 9ec84845 + ZUABALT Z8.B, Z4.B, Z30.H // 9ecc4845 + ZUABD Z15.B, Z0.B, P3.M, Z0.B // e00d0d04 + ZUABDLB Z8.B, Z4.B, Z30.H // 9e384845 + ZUABDLT Z8.B, Z4.B, Z30.H // 9e3c4845 + ZUADALP Z14.S, P1.M, Z1.D // c1a5c544 + ZUADDLB Z8.B, Z4.B, Z30.H // 9e084845 + ZUADDLT Z8.B, Z4.B, Z30.H // 9e0c4845 + ZUADDWB Z22.S, Z10.D, Z5.D // 4549d645 + ZUADDWT Z22.S, Z10.D, Z5.D // 454dd645 + ZUCLAMP Z7.D, Z23.D, Z13.D // edc6c744 + // TODO: UCVTF ., . + ZUCVTF Z13.H, P1.M, Z22.H // b6a55365 + ZUCVTF Z13.H, P1.Z, Z22.H // b6e55c64 + ZUCVTF Z13.S, P1.M, Z22.H // b6a55565 + ZUCVTF Z13.S, P1.Z, Z22.H // b6a55d64 + ZUCVTF Z13.S, P1.M, Z22.S // b6a59565 + ZUCVTF Z13.S, P1.Z, Z22.S // b6a59d64 + ZUCVTF Z13.S, P1.M, Z22.D // b6a5d165 + ZUCVTF Z13.S, P1.Z, Z22.D // b6a5dc64 + ZUCVTF Z13.D, P1.M, Z22.H // b6a55765 + ZUCVTF Z13.D, P1.Z, Z22.H // b6e55d64 + ZUCVTF Z13.D, P1.M, Z22.S // b6a5d565 + ZUCVTF Z13.D, P1.Z, Z22.S // b6a5dd64 + ZUCVTF Z13.D, P1.M, Z22.D // b6a5d765 + ZUCVTF Z13.D, P1.Z, Z22.D // b6e5dd64 + // TODO: UCVTFLT + ZUDIV Z25.S, Z2.S, P1.M, Z2.S // 22079504 + ZUDIVR Z25.S, Z2.S, P1.M, Z2.S // 22079704 + // TODO: UDOT .H, .B, .B + ZUDOT Z7.H, Z6.H, Z23.S // d7cc0744 + ZUDOT Z15.B, Z0.B, Z12.S // 0c048f44 + ZUHADD Z15.B, Z0.B, P3.M, Z0.B // e08d1144 + ZUHSUB Z15.B, Z0.B, P3.M, Z0.B // e08d1344 + ZUHSUBR Z15.B, Z0.B, P3.M, Z0.B // e08d1744 + ZUMAX Z15.B, Z0.B, P3.M, Z0.B // e00d0904 + ZUMAXP Z15.B, Z0.B, P3.M, Z0.B // e0ad1544 + ZUMAXQV Z25.S, P3, V5.S4 // 252f8d04 + ZUMIN Z15.B, Z0.B, P3.M, Z0.B // e00d0b04 + ZUMINP Z15.B, Z0.B, P3.M, Z0.B // e0ad1744 + ZUMINQV Z25.S, P3, V5.S4 // 252f8f04 + ZUMLALB Z8.B, Z4.B, Z30.H // 9e484844 + ZUMLALT Z8.B, Z4.B, Z30.H // 9e4c4844 + ZUMLSLB Z8.B, Z4.B, Z30.H // 9e584844 + ZUMLSLT Z8.B, Z4.B, Z30.H // 9e5c4844 + ZUMMLA Z7.B, Z6.B, Z23.S // d798c745 + ZUMULH Z15.B, Z0.B, P3.M, Z0.B // e00d1304 + ZUMULH Z7.D, Z23.D, Z13.D // ed6ee704 + ZUMULLB Z8.B, Z4.B, Z30.H // 9e784845 + ZUMULLT Z8.B, Z4.B, Z30.H // 9e7c4845 + ZUQADD Z15.B, Z0.B, P3.M, Z0.B // e08d1944 + ZUQADD Z7.D, Z23.D, Z13.D // ed16e704 + ZUQDECP P14.S, Z26.S // da81ab25 + ZUQINCP P14.S, Z26.S // da81a925 + ZUQRSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0b44 + ZUQRSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0f44 + ZUQSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0944 + ZUQSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0d44 + ZUQSUB Z15.B, Z0.B, P3.M, Z0.B // e08d1b44 + ZUQSUB Z7.D, Z23.D, Z13.D // ed1ee704 + ZUQSUBR Z15.B, Z0.B, P3.M, Z0.B // e08d1f44 + ZUQXTNB Z30.D, Z29.S // dd4b6045 + ZUQXTNT Z30.D, Z29.S // dd4f6045 + ZURECPE Z13.S, P1.M, Z22.S // b6a58044 + ZURECPE Z13.S, P1.Z, Z22.S // b6a58244 + ZURHADD Z15.B, Z0.B, P3.M, Z0.B // e08d1544 + ZURSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0344 + ZURSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0744 + ZURSQRTE Z13.S, P1.M, Z22.S // b6a58144 + ZURSQRTE Z13.S, P1.Z, Z22.S // b6a58344 + ZUSDOT Z7.B, Z6.B, Z23.S // d7788744 + ZUSMMLA Z7.B, Z6.B, Z23.S // d7988745 + ZUSQADD Z15.B, Z0.B, P3.M, Z0.B // e08d1d44 + ZUSUBLB Z8.B, Z4.B, Z30.H // 9e184845 + ZUSUBLT Z8.B, Z4.B, Z30.H // 9e1c4845 + ZUSUBWB Z22.S, Z10.D, Z5.D // 4559d645 + ZUSUBWT Z22.S, Z10.D, Z5.D // 455dd645 + ZUUNPKHI Z15.B, Z0.H // e0397305 + ZUUNPKLO Z15.B, Z0.H // e0397205 + ZUXTB Z7.D, P4.M, Z13.D // edb0d104 + ZUXTB Z7.D, P4.Z, Z13.D // edb0c104 + ZUXTH Z7.D, P4.M, Z13.D // edb0d304 + ZUXTH Z7.D, P4.Z, Z13.D // edb0c304 + ZUXTW Z13.D, P1.M, Z22.D // b6a5d504 + ZUXTW Z13.D, P1.Z, Z22.D // b6a5c504 + ZUZP1 Z7.D, Z23.D, Z13.D // ed6ae705 + ZUZP1 Z7.Q, Z6.Q, Z23.Q // d708a705 + ZUZP2 Z7.D, Z23.D, Z13.D // ed6ee705 + ZUZP2 Z7.Q, Z6.Q, Z23.Q // d70ca705 + ZUZPQ1 Z7.D, Z23.D, Z13.D // edeac744 + ZUZPQ2 Z7.D, Z23.D, Z13.D // edeec744 + ZZIP1 Z7.D, Z23.D, Z13.D // ed62e705 + ZZIP1 Z7.Q, Z6.Q, Z23.Q // d700a705 + ZZIP2 Z7.D, Z23.D, Z13.D // ed66e705 + ZZIP2 Z7.Q, Z6.Q, Z23.Q // d704a705 + ZZIPQ1 Z7.D, Z23.D, Z13.D // ede2c744 + ZZIPQ2 Z7.D, Z23.D, Z13.D // ede6c744 + CTERMEQ ZR, R25 // 2023ff25 + CTERMEQW ZR, R25 // 2023bf25 + CTERMNE ZR, R25 // 3023ff25 + CTERMNEW ZR, R25 // 3023bf25 + PCNTP P2.B, P14, R2 // 42b82025 + PDECP P14.S, ZR // df89ad25 + PFIRSTP P2.B, P14, R2 // 42b82125 + PINCP P14.S, ZR // df89ac25 + PLASTP P2.B, P14, R2 // 42b82225 + PSQDECP P14.S, ZR // df8daa25 + PSQDECPW R8, P10.D, R8 // 4889ea25 + PSQINCP P14.S, ZR // df8da825 + PSQINCPW R8, P10.D, R8 // 4889e825 + PUQDECP P14.S, ZR // df8dab25 + PUQDECPW P14.S, ZR // df89ab25 + PUQINCP P14.S, ZR // df8da925 + PUQINCPW P14.S, ZR // df89a925 + PWHILEGE R2, R10, P10.H // 4a116225 + PWHILEGEW R2, R10, P10.H // 4a016225 + PWHILEGT R2, R10, P10.H // 5a116225 + PWHILEGTW R2, R10, P10.H // 5a016225 + PWHILEHI R2, R10, P10.H // 5a196225 + PWHILEHIW R2, R10, P10.H // 5a096225 + PWHILEHS R2, R10, P10.H // 4a196225 + PWHILEHSW R2, R10, P10.H // 4a096225 + PWHILELE R2, R10, P10.H // 5a156225 + PWHILELEW R2, R10, P10.H // 5a056225 + PWHILELO R2, R10, P10.H // 4a1d6225 + PWHILELOW R2, R10, P10.H // 4a0d6225 + PWHILELS R2, R10, P10.H // 5a1d6225 + PWHILELSW R2, R10, P10.H // 5a0d6225 + PWHILELT R2, R10, P10.H // 4a156225 + PWHILELTW R2, R10, P10.H // 4a056225 + PWHILERW R2, R10, P10.H // 5a316225 + PWHILEWR R2, R10, P10.H // 4a316225 + ZANDVB Z6.B, P3, V2 // c22c1a04 + ZANDVD Z10.D, P3, V15 // 4f2dda04 + ZANDVH Z3.H, P1, V29 // 7d245a04 + ZANDVS Z17.S, P1, V27 // 3b269a04 + ZCLASTA Z9.D, R10, P2, R10 // 2aa9f005 + ZCLASTAB Z2.B, V29, P1, V29 // 5d842a05 + ZCLASTAD Z9.D, V10, P2, V10 // 2a89ea05 + ZCLASTAH Z8.H, V15, P2, V15 // 0f896a05 + ZCLASTAS Z26.S, V30, P7, V30 // 5e9faa05 + ZCLASTAW Z8.H, R15, P2, R15 // 0fa97005 + ZCLASTB Z9.D, R10, P2, R10 // 2aa9f105 + ZCLASTBB Z2.B, V29, P1, V29 // 5d842b05 + ZCLASTBD Z9.D, V10, P2, V10 // 2a89eb05 + ZCLASTBH Z8.H, V15, P2, V15 // 0f896b05 + ZCLASTBS Z26.S, V30, P7, V30 // 5e9fab05 + ZCLASTBW Z8.H, R15, P2, R15 // 0fa97105 + ZCPY R20, P1.M, Z2.D // 82a6e805 + ZCPYB V4, P1.M, Z16.B // 90842005 + ZCPYD V20, P1.M, Z2.D // 8286e005 + ZCPYH V7, P6.M, Z23.H // f7986005 + ZCPYS V13, P1.M, Z22.S // b685a005 + ZCPYW RSP, P5.M, Z6.H // e6b76805 + ZDUP R2, Z10.D // 4a38e005 + ZDUPW R25, Z11.B // 2b3b2005 + ZEORVB Z6.B, P3, V2 // c22c1904 + ZEORVD Z10.D, P3, V15 // 4f2dd904 + ZEORVH Z3.H, P1, V29 // 7d245904 + ZEORVS Z17.S, P1, V27 // 3b269904 + ZFADDAD Z9.D, V10, P2, V10 // 2a29d865 + ZFADDAH Z8.H, V15, P2, V15 // 0f295865 + ZFADDAS Z26.S, V30, P7, V30 // 5e3f9865 + ZFADDVD Z10.D, P3, V15 // 4f2dc065 + ZFADDVH Z3.H, P1, V29 // 7d244065 + ZFADDVS Z17.S, P1, V27 // 3b268065 + ZFMAXNMVD Z10.D, P3, V15 // 4f2dc465 + ZFMAXNMVH Z3.H, P1, V29 // 7d244465 + ZFMAXNMVS Z17.S, P1, V27 // 3b268465 + ZFMAXVD Z10.D, P3, V15 // 4f2dc665 + ZFMAXVH Z3.H, P1, V29 // 7d244665 + ZFMAXVS Z17.S, P1, V27 // 3b268665 + ZFMINNMVD Z10.D, P3, V15 // 4f2dc565 + ZFMINNMVH Z3.H, P1, V29 // 7d244565 + ZFMINNMVS Z17.S, P1, V27 // 3b268565 + ZFMINVD Z10.D, P3, V15 // 4f2dc765 + ZFMINVH Z3.H, P1, V29 // 7d244765 + ZFMINVS Z17.S, P1, V27 // 3b268765 + ZINDEX R13, R20, Z9.D // 894eed04 + ZINDEXW R2, R10, Z8.H // 484d6204 + ZINSR R2, Z10.D // 4a38e405 + ZINSRB V25, Z11.B // 2b3b3405 + ZINSRD V2, Z10.D // 4a38f405 + ZINSRH V7, Z6.H // e6387405 + ZINSRS V14, Z8.S // c839b405 + ZINSRW R25, Z11.B // 2b3b2405 + ZLASTA Z10.D, P3, R15 // 4fade005 + ZLASTAB Z6.B, P3, V2 // c28c2205 + ZLASTAD Z10.D, P3, V15 // 4f8de205 + ZLASTAH Z3.H, P1, V29 // 7d846205 + ZLASTAS Z17.S, P1, V27 // 3b86a205 + ZLASTAW Z6.B, P3, R2 // c2ac2005 + ZLASTB Z10.D, P3, R15 // 4fade105 + ZLASTBB Z6.B, P3, V2 // c28c2305 + ZLASTBD Z10.D, P3, V15 // 4f8de305 + ZLASTBH Z3.H, P1, V29 // 7d846305 + ZLASTBS Z17.S, P1, V27 // 3b86a305 + ZLASTBW Z6.B, P3, R2 // c2ac2105 + ZORVB Z6.B, P3, V2 // c22c1804 + ZORVD Z10.D, P3, V15 // 4f2dd804 + ZORVH Z3.H, P1, V29 // 7d245804 + ZORVS Z17.S, P1, V27 // 3b269804 + ZSADDVD Z6.B, P3, V2 // c22c0004 + ZSMAXVB Z6.B, P3, V2 // c22c0804 + ZSMAXVD Z10.D, P3, V15 // 4f2dc804 + ZSMAXVH Z3.H, P1, V29 // 7d244804 + ZSMAXVS Z17.S, P1, V27 // 3b268804 + ZSMINVB Z6.B, P3, V2 // c22c0a04 + ZSMINVD Z10.D, P3, V15 // 4f2dca04 + ZSMINVH Z3.H, P1, V29 // 7d244a04 + ZSMINVS Z17.S, P1, V27 // 3b268a04 + ZUADDVD Z10.D, P3, V15 // 4f2dc104 + ZUMAXVB Z6.B, P3, V2 // c22c0904 + ZUMAXVD Z10.D, P3, V15 // 4f2dc904 + ZUMAXVH Z3.H, P1, V29 // 7d244904 + ZUMAXVS Z17.S, P1, V27 // 3b268904 + ZUMINVB Z6.B, P3, V2 // c22c0b04 + ZUMINVD Z10.D, P3, V15 // 4f2dcb04 + ZUMINVH Z3.H, P1, V29 // 7d244b04 + ZUMINVS Z17.S, P1, V27 // 3b268b04 + PPEXT PN11[1], P13.S // 7d71a025 + ZBFDOT Z6.H[3], Z23.H, Z13.S // ed427e64 + ZBFMLA Z6.H[3], Z23.H, Z13.H // ed0a3e64 + ZBFMLALB Z6.H[3], Z23.H, Z13.S // ed4aee64 + ZBFMLALT Z6.H[3], Z23.H, Z13.S // ed4eee64 + ZBFMLS Z6.H[3], Z23.H, Z13.H // ed0e3e64 + ZBFMLSLB Z6.H[3], Z23.H, Z13.S // ed6aee64 + ZBFMLSLT Z6.H[3], Z23.H, Z13.S // ed6eee64 + ZBFMUL Z6.H[3], Z23.H, Z13.H // ed2a3e64 + ZDUP Z27.Q[1], Z25.Q // 79237005 + ZDUPQ Z8.H[2], Z15.H // 0f252a05 + ZFDOT Z6.H[3], Z23.H, Z13.S // ed423e64 + ZFDOT Z6.B[3], Z23.B, Z13.H // ed4e2e64 + ZFDOT Z6.B[3], Z23.B, Z13.S // ed467e64 + ZFMLA Z6.H[3], Z23.H, Z13.H // ed023e64 + ZFMLA Z6.S[3], Z23.S, Z13.S // ed02be64 + ZFMLA Z5.D[0], Z15.D, Z6.D // e601e564 + ZFMLALB Z6.H[3], Z23.H, Z13.S // ed4aae64 + ZFMLALB Z6.B[3], Z23.B, Z13.H // ed5e2664 + ZFMLALLBB Z6.B[3], Z23.B, Z13.S // edce2664 + ZFMLALLBT Z6.B[3], Z23.B, Z13.S // edce6664 + ZFMLALLTB Z6.B[3], Z23.B, Z13.S // edcea664 + ZFMLALLTT Z6.B[3], Z23.B, Z13.S // edcee664 + ZFMLALT Z6.H[3], Z23.H, Z13.S // ed4eae64 + ZFMLALT Z6.B[3], Z23.B, Z13.H // ed5ea664 + ZFMLS Z6.H[3], Z23.H, Z13.H // ed063e64 + ZFMLS Z6.S[3], Z23.S, Z13.S // ed06be64 + ZFMLS Z5.D[0], Z15.D, Z6.D // e605e564 + ZFMLSLB Z6.H[3], Z23.H, Z13.S // ed6aae64 + ZFMLSLT Z6.H[3], Z23.H, Z13.S // ed6eae64 + ZFMUL Z6.H[3], Z23.H, Z13.H // ed223e64 + ZFMUL Z6.S[3], Z23.S, Z13.S // ed22be64 + ZFMUL Z5.D[0], Z15.D, Z6.D // e621e564 + ZMLA Z6.H[3], Z23.H, Z13.H // ed0a3e44 + ZMLA Z6.S[3], Z23.S, Z13.S // ed0abe44 + ZMLA Z5.D[0], Z15.D, Z6.D // e609e544 + ZMLS Z6.H[3], Z23.H, Z13.H // ed0e3e44 + ZMLS Z6.S[3], Z23.S, Z13.S // ed0ebe44 + ZMLS Z5.D[0], Z15.D, Z6.D // e60de544 + ZMUL Z6.H[3], Z23.H, Z13.H // edfa3e44 + ZMUL Z6.S[3], Z23.S, Z13.S // edfabe44 + ZMUL Z5.D[0], Z15.D, Z6.D // e6f9e544 + ZPMOV Z27[1], P13.S // 6d3b6a05 + ZPMOV Z27[1], P13.S // 6d3b6a05 + ZPMOV Z27[1], P13.S // 6d3b6a05 + ZPMOV P14.S, Z25[2] // d9396d05 + ZPMOV P14.S, Z25[2] // d9396d05 + ZPMOV P14.S, Z25[2] // d9396d05 + // TODO: SDOT .H, .B, .B[] + ZSDOT Z6.H[3], Z23.H, Z13.S // edca9e44 + ZSDOT Z6.B[3], Z23.B, Z13.S // ed02be44 + ZSDOT Z5.H[0], Z15.H, Z6.D // e601e544 + ZSMLALB Z6.H[3], Z23.H, Z13.S // ed8aae44 + ZSMLALB Z6.S[3], Z23.S, Z13.D // ed8af644 + ZSMLALT Z6.H[3], Z23.H, Z13.S // ed8eae44 + ZSMLALT Z6.S[3], Z23.S, Z13.D // ed8ef644 + ZSMLSLB Z6.H[3], Z23.H, Z13.S // edaaae44 + ZSMLSLB Z6.S[3], Z23.S, Z13.D // edaaf644 + ZSMLSLT Z6.H[3], Z23.H, Z13.S // edaeae44 + ZSMLSLT Z6.S[3], Z23.S, Z13.D // edaef644 + ZSMULLB Z6.H[3], Z23.H, Z13.S // edcaae44 + ZSMULLB Z6.S[3], Z23.S, Z13.D // edcaf644 + ZSMULLT Z6.H[3], Z23.H, Z13.S // edceae44 + ZSMULLT Z6.S[3], Z23.S, Z13.D // edcef644 + ZSQDMLALB Z6.H[3], Z23.H, Z13.S // ed2aae44 + ZSQDMLALB Z6.S[3], Z23.S, Z13.D // ed2af644 + ZSQDMLALT Z6.H[3], Z23.H, Z13.S // ed2eae44 + ZSQDMLALT Z6.S[3], Z23.S, Z13.D // ed2ef644 + ZSQDMLSLB Z6.H[3], Z23.H, Z13.S // ed3aae44 + ZSQDMLSLB Z6.S[3], Z23.S, Z13.D // ed3af644 + ZSQDMLSLT Z6.H[3], Z23.H, Z13.S // ed3eae44 + ZSQDMLSLT Z6.S[3], Z23.S, Z13.D // ed3ef644 + ZSQDMULH Z6.H[3], Z23.H, Z13.H // edf23e44 + ZSQDMULH Z6.S[3], Z23.S, Z13.S // edf2be44 + ZSQDMULH Z5.D[0], Z15.D, Z6.D // e6f1e544 + ZSQDMULLB Z6.H[3], Z23.H, Z13.S // edeaae44 + ZSQDMULLB Z6.S[3], Z23.S, Z13.D // edeaf644 + ZSQDMULLT Z6.H[3], Z23.H, Z13.S // edeeae44 + ZSQDMULLT Z6.S[3], Z23.S, Z13.D // edeef644 + ZSQRDMLAH Z6.H[3], Z23.H, Z13.H // ed123e44 + ZSQRDMLAH Z6.S[3], Z23.S, Z13.S // ed12be44 + ZSQRDMLAH Z5.D[0], Z15.D, Z6.D // e611e544 + ZSQRDMLSH Z6.H[3], Z23.H, Z13.H // ed163e44 + ZSQRDMLSH Z6.S[3], Z23.S, Z13.S // ed16be44 + ZSQRDMLSH Z5.D[0], Z15.D, Z6.D // e615e544 + ZSQRDMULH Z6.H[3], Z23.H, Z13.H // edf63e44 + ZSQRDMULH Z6.S[3], Z23.S, Z13.S // edf6be44 + ZSQRDMULH Z5.D[0], Z15.D, Z6.D // e6f5e544 + ZSUDOT Z6.B[3], Z23.B, Z13.S // ed1ebe44 + // TODO: UDOT .H, .B, .B[] + ZUDOT Z6.H[3], Z23.H, Z13.S // edce9e44 + ZUDOT Z6.B[3], Z23.B, Z13.S // ed06be44 + ZUDOT Z5.H[0], Z15.H, Z6.D // e605e544 + ZUMLALB Z6.H[3], Z23.H, Z13.S // ed9aae44 + ZUMLALB Z6.S[3], Z23.S, Z13.D // ed9af644 + ZUMLALT Z6.H[3], Z23.H, Z13.S // ed9eae44 + ZUMLALT Z6.S[3], Z23.S, Z13.D // ed9ef644 + ZUMLSLB Z6.H[3], Z23.H, Z13.S // edbaae44 + ZUMLSLB Z6.S[3], Z23.S, Z13.D // edbaf644 + ZUMLSLT Z6.H[3], Z23.H, Z13.S // edbeae44 + ZUMLSLT Z6.S[3], Z23.S, Z13.D // edbef644 + ZUMULLB Z6.H[3], Z23.H, Z13.S // eddaae44 + ZUMULLB Z6.S[3], Z23.S, Z13.D // eddaf644 + ZUMULLT Z6.H[3], Z23.H, Z13.S // eddeae44 + ZUMULLT Z6.S[3], Z23.S, Z13.D // eddef644 + ZUSDOT Z6.B[3], Z23.B, Z13.S // ed1abe44 + ADDPL $9, R11, RSP // 3f516b04 + ADDVL $9, R11, RSP // 3f512b04 + RDVL $1, R27 // 3b50bf04 + ZADD $6, Z7.D, Z7.D // c7c0e025 + ZAND $6, Z7.D, Z7.D // 27f88305 + ZASR $6, Z23.B, P1.M, Z23.B // 57850004 + ZASR $6, Z7.D, Z23.D // f790fa04 + ZASRD $6, Z23.B, P1.M, Z23.B // 57850404 + ZCADD $270, Z25.S, Z22.S, Z22.S // 36df8045 + ZCDOT $0, Z5.B[3], Z16.B, Z26.S // 1a42bd44 + ZCDOT $270, Z3.H[0], Z2.H, Z23.D // 574ce344 + ZCDOT $270, Z28.B, Z1.B, Z9.S // 291c9c44 + ZCMLA $0, Z5.H[3], Z16.H, Z26.H // 1a62bd44 + ZCMLA $270, Z3.S[0], Z2.S, Z23.S // 576ce344 + ZCMLA $180, Z19.S, Z20.S, Z9.S // 892a9344 + ZCMPEQ $6, Z23.B, P1.Z, P14.B // ee860625 + ZCMPGE $6, Z23.B, P1.Z, P14.B // ee060625 + ZCMPGT $6, Z23.B, P1.Z, P14.B // fe060625 + ZCMPHI $6, Z23.B, P1.Z, P14.B // fe862124 + ZCMPHS $6, Z23.B, P1.Z, P14.B // ee862124 + // TODO: CMPLE + // TODO: CMPLO + // TODO: CMPLS + // TODO: CMPLT + ZCMPNE $6, Z23.B, P1.Z, P14.B // fe860625 + ZCPY $6, P5.M, Z6.H // c6405505 + ZCPY $6, P5.Z, Z6.H // c6005505 + ZDUP $9, Z11.B // 2bc13825 + ZDUPM $7, Z6.H // 4604c005 + ZEOR $6, Z7.D, Z7.D // 27f84305 + ZEXT $6, Z23.B, Z13.B, Z13.B // ed1a2005 + ZEXTQ $6, Z23.B, Z13.B, Z13.B // ed266605 + ZFADD $(1.0), Z5.D, P5.M, Z5.D // 2594d865 + ZFCADD $90, Z13.S, Z4.S, P4.M, Z4.S // a4918064 + ZFCMEQ $(0.0), Z7.D, P4.Z, P2.D // e230d265 + ZFCMGE $(0.0), Z7.D, P4.Z, P2.D // e230d065 + ZFCMGT $(0.0), Z7.D, P4.Z, P2.D // f230d065 + ZFCMLA $0, Z5.H[3], Z16.H, Z26.H // 1a12bd64 + ZFCMLA $270, Z3.S[0], Z2.S, Z23.S // 571ce364 + ZFCMLA $180, Z30.D, Z29.D, P7.M, Z25.D // b95fde64 + ZFCMLE $(0.0), Z7.D, P4.Z, P2.D // f230d165 + ZFCMLT $(0.0), Z7.D, P4.Z, P2.D // e230d165 + ZFCMNE $(0.0), Z7.D, P4.Z, P2.D // e230d365 + ZFCPY $(2.0), P6.M, Z23.H // 17c05605 + ZFDUP $(2.0), Z4.S // 04c0b925 + ZFMAX $(0.0), Z3.D, P1.M, Z3.D // 0384de65 + ZFMAXNM $(0.0), Z3.D, P1.M, Z3.D // 0384dc65 + ZFMIN $(0.0), Z3.D, P1.M, Z3.D // 0384df65 + ZFMINNM $(0.0), Z3.D, P1.M, Z3.D // 0384dd65 + ZFMUL $(2.0), Z16.S, P1.M, Z16.S // 30849a65 + ZFSUB $(1.0), Z5.D, P5.M, Z5.D // 2594d965 + ZFSUBR $(1.0), Z5.D, P5.M, Z5.D // 2594db65 + ZFTMAD $3, Z13.S, Z9.S, Z9.S // a9819365 + ZINDEX R11, $6, Z7.D // c748eb04 + ZINDEX $1, $11, Z26.S // 7a41a104 + ZINDEX $8, R24, Z14.D // 0e47e804 + ZINDEXW R2, $10, Z8.H // 48496204 + ZINDEXW $1, R27, Z26.S // 7a47a104 + ZLSL $6, Z23.B, P1.M, Z23.B // d7850304 + ZLSL $6, Z7.D, Z23.D // f79ca604 + ZLSR $6, Z23.B, P1.M, Z23.B // 57850104 + ZLSR $6, Z7.D, Z23.D // f794fa04 + ZMUL $6, Z7.D, Z7.D // c7c0f025 + ZORR $6, Z7.D, Z7.D // 27f80305 + ZRSHRNB $9, Z7.S, Z23.H // f7183745 + ZRSHRNT $9, Z7.S, Z23.H // f71c3745 + ZSHRNB $9, Z7.S, Z23.H // f7103745 + ZSHRNT $9, Z7.S, Z23.H // f7143745 + ZSLI $6, Z7.D, Z23.D // f7f48645 + ZSMAX $6, Z7.D, Z7.D // c7c0e825 + ZSMIN $6, Z7.D, Z7.D // c7c0ea25 + ZSQADD $6, Z7.D, Z7.D // c7c0e425 + ZSQCADD $270, Z25.S, Z22.S, Z22.S // 36df8145 + ZSQRDCMLAH $0, Z5.H[3], Z16.H, Z26.H // 1a72bd44 + ZSQRDCMLAH $270, Z3.S[0], Z2.S, Z23.S // 577ce344 + ZSQRDCMLAH $180, Z19.S, Z20.S, Z9.S // 893a9344 + ZSQRSHRNB $9, Z7.S, Z23.H // f7283745 + ZSQRSHRNT $9, Z7.S, Z23.H // f72c3745 + ZSQRSHRUNB $9, Z7.S, Z23.H // f7083745 + ZSQRSHRUNT $9, Z7.S, Z23.H // f70c3745 + ZSQSHL $6, Z23.B, P1.M, Z23.B // d7850604 + ZSQSHLU $6, Z23.B, P1.M, Z23.B // d7850f04 + ZSQSHRNB $9, Z7.S, Z23.H // f7203745 + ZSQSHRNT $9, Z7.S, Z23.H // f7243745 + ZSQSHRUNB $9, Z7.S, Z23.H // f7003745 + ZSQSHRUNT $9, Z7.S, Z23.H // f7043745 + ZSQSUB $6, Z7.D, Z7.D // c7c0e625 + ZSRI $6, Z7.D, Z23.D // f7f0da45 + ZSRSHR $6, Z23.B, P1.M, Z23.B // 57850c04 + ZSRSRA $6, Z7.D, Z23.D // f7e8da45 + ZSSHLLB $5, Z22.S, Z10.D // caa24545 + ZSSHLLT $5, Z22.S, Z10.D // caa64545 + ZSSRA $6, Z7.D, Z23.D // f7e0da45 + ZSUB $6, Z7.D, Z7.D // c7c0e125 + ZSUBR $6, Z7.D, Z7.D // c7c0e325 + ZUMAX $6, Z7.D, Z7.D // c7c0e925 + ZUMIN $6, Z7.D, Z7.D // c7c0eb25 + ZUQADD $6, Z7.D, Z7.D // c7c0e525 + ZUQRSHRNB $9, Z7.S, Z23.H // f7383745 + ZUQRSHRNT $9, Z7.S, Z23.H // f73c3745 + ZUQSHL $6, Z23.B, P1.M, Z23.B // d7850704 + ZUQSHRNB $9, Z7.S, Z23.H // f7303745 + ZUQSHRNT $9, Z7.S, Z23.H // f7343745 + ZUQSUB $6, Z7.D, Z7.D // c7c0e725 + ZURSHR $6, Z23.B, P1.M, Z23.B // 57850d04 + ZURSRA $6, Z7.D, Z23.D // f7ecda45 + ZUSHLLB $5, Z22.S, Z10.D // caaa4545 + ZUSHLLT $5, Z22.S, Z10.D // caae4545 + ZUSRA $6, Z7.D, Z23.D // f7e4da45 + ZXAR $6, Z23.B, Z21.B, Z21.B // f5362a04 + PPEXT PN11[1], [P13.S, P14.S] // 7d75a025 + PWHILEGE R2, R10, [P10.H, P11.H] // 5a516225 + PWHILEGT R2, R10, [P10.H, P11.H] // 5b516225 + PWHILEHI R2, R10, [P10.H, P11.H] // 5b596225 + PWHILEHS R2, R10, [P10.H, P11.H] // 5a596225 + PWHILELE R2, R10, [P10.H, P11.H] // 5b556225 + PWHILELO R2, R10, [P10.H, P11.H] // 5a5d6225 + PWHILELS R2, R10, [P10.H, P11.H] // 5b5d6225 + PWHILELT R2, R10, [P10.H, P11.H] // 5a556225 + ZEXT $6, [Z7.B, Z8.B], Z6.B // e6186005 + ZLUTI2 Z6[3], [Z23.B], Z13.B // edb2e645 + ZLUTI2 Z6[3], [Z23.H], Z13.H // edba6645 + ZLUTI4 Z22[1], [Z2.B], Z10.B // 4aa4f645 + ZLUTI4 Z6[3], [Z23.H, Z24.H], Z13.H // edb6e645 + ZLUTI4 Z6[3], [Z23.H], Z13.H // edbee645 + // TODO: LUTI6 + // TODO: LUTI6 + ZSPLICE [Z7.D, Z8.D], P4, Z13.D // ed90ed05 + ZTBL Z7.D, [Z23.D], Z13.D // ed32e705 + ZTBL Z7.D, [Z23.D, Z24.D], Z13.D // ed2ae705 + ZTBLQ Z7.D, [Z23.D], Z13.D // edfac744 + ZADR (Z16.S)(Z12.S), Z13.S // 8da1b004 + ZADR (Z7.D.SXTW<<2)(Z6.D), Z23.D // d7a82704 + ZADR (Z7.D.UXTW<<2)(Z6.D), Z23.D // d7a86704 + ZLD1B (R6)(R14), P4.Z, [Z13.B] // cd5106a4 + ZLD1B (R6)(R14), P4.Z, [Z13.H] // cd5126a4 + ZLD1B (R6)(R14), P4.Z, [Z13.S] // cd5146a4 + ZLD1B (R6)(R14), P4.Z, [Z13.D] // cd5166a4 + ZLD1B (Z10.D)(R19), P3.Z, [Z15.D] // 6fce4ac4 + ZLD1B (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 644c0484 + ZLD1B (Z6.D)(R14), P4.Z, [Z13.D] // cdd146c4 + ZLD1D (R6<<3)(R14), P4.Z, [Z13.D] // cd51e6a5 + ZLD1D (R6<<3)(R14), P4.Z, [Z13.Q] // cd9186a5 + ZLD1D (Z23.D<<3)(R24), P1.Z, [Z22.D] // 16c7f7c5 + ZLD1D (Z10.D)(R19), P3.Z, [Z15.D] // 6fcecac5 + ZLD1D (Z6.D<<3)(R14), P4.Z, [Z13.D] // cdd1e6c5 + ZLD1D (Z6.D)(R14), P4.Z, [Z13.D] // cdd1c6c5 + ZLD1H (R6<<1)(R14), P4.Z, [Z13.H] // cd51a6a4 + ZLD1H (R6<<1)(R14), P4.Z, [Z13.S] // cd51c6a4 + ZLD1H (R6<<1)(R14), P4.Z, [Z13.D] // cd51e6a4 + ZLD1H (Z4.S.UXTW<<1)(R3), P3.Z, [Z4.S] // 644ca484 + ZLD1H (Z23.D<<1)(R24), P1.Z, [Z22.D] // 16c7f7c4 + ZLD1H (Z10.D)(R19), P3.Z, [Z15.D] // 6fcecac4 + ZLD1H (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 644c8484 + ZLD1H (Z6.D<<1)(R14), P4.Z, [Z13.D] // cdd1e6c4 + ZLD1H (Z6.D)(R14), P4.Z, [Z13.D] // cdd1c6c4 + ZLD1Q (R6)(Z7.D), P4.Z, [Z13.Q] // edb006c4 + ZLD1ROB (R6)(R14), P4.Z, [Z13.B] // cd1126a4 + ZLD1ROD (R6<<3)(R14), P4.Z, [Z13.D] // cd11a6a5 + ZLD1ROH (R6<<1)(R14), P4.Z, [Z13.H] // cd11a6a4 + ZLD1ROW (R6<<2)(R14), P4.Z, [Z13.S] // cd1126a5 + ZLD1RQB (R6)(R14), P4.Z, [Z13.B] // cd1106a4 + ZLD1RQD (R6<<3)(R14), P4.Z, [Z13.D] // cd1186a5 + ZLD1RQH (R6<<1)(R14), P4.Z, [Z13.H] // cd1186a4 + ZLD1RQW (R6<<2)(R14), P4.Z, [Z13.S] // cd1106a5 + ZLD1SB (R6)(R14), P4.Z, [Z13.H] // cd51c6a5 + ZLD1SB (R6)(R14), P4.Z, [Z13.S] // cd51a6a5 + ZLD1SB (R6)(R14), P4.Z, [Z13.D] // cd5186a5 + ZLD1SB (Z10.D)(R19), P3.Z, [Z15.D] // 6f8e4ac4 + ZLD1SB (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 640c0484 + ZLD1SB (Z6.D)(R14), P4.Z, [Z13.D] // cd9146c4 + ZLD1SH (R6<<1)(R14), P4.Z, [Z13.S] // cd5126a5 + ZLD1SH (R6<<1)(R14), P4.Z, [Z13.D] // cd5106a5 + ZLD1SH (Z4.S.UXTW<<1)(R3), P3.Z, [Z4.S] // 640ca484 + ZLD1SH (Z23.D<<1)(R24), P1.Z, [Z22.D] // 1687f7c4 + ZLD1SH (Z10.D)(R19), P3.Z, [Z15.D] // 6f8ecac4 + ZLD1SH (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 640c8484 + ZLD1SH (Z6.D<<1)(R14), P4.Z, [Z13.D] // cd91e6c4 + ZLD1SH (Z6.D)(R14), P4.Z, [Z13.D] // cd91c6c4 + ZLD1SW (R6<<2)(R14), P4.Z, [Z13.D] // cd5186a4 + ZLD1SW (Z23.D<<2)(R24), P1.Z, [Z22.D] // 168777c5 + ZLD1SW (Z10.D)(R19), P3.Z, [Z15.D] // 6f8e4ac5 + ZLD1SW (Z6.D<<2)(R14), P4.Z, [Z13.D] // cd9166c5 + ZLD1SW (Z6.D)(R14), P4.Z, [Z13.D] // cd9146c5 + ZLD1W (R6<<2)(R14), P4.Z, [Z13.S] // cd5146a5 + ZLD1W (R6<<2)(R14), P4.Z, [Z13.D] // cd5166a5 + ZLD1W (R6<<2)(R14), P4.Z, [Z13.Q] // cd9106a5 + ZLD1W (Z4.S.UXTW<<2)(R3), P3.Z, [Z4.S] // 644c2485 + ZLD1W (Z23.D<<2)(R24), P1.Z, [Z22.D] // 16c777c5 + ZLD1W (Z10.D)(R19), P3.Z, [Z15.D] // 6fce4ac5 + ZLD1W (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 644c0485 + ZLD1W (Z6.D<<2)(R14), P4.Z, [Z13.D] // cdd166c5 + ZLD1W (Z6.D)(R14), P4.Z, [Z13.D] // cdd146c5 + ZLD2B (R6)(R14), P4.Z, [Z13.B, Z14.B] // cdd126a4 + ZLD2D (R6<<3)(R14), P4.Z, [Z13.D, Z14.D] // cdd1a6a5 + ZLD2H (R6<<1)(R14), P4.Z, [Z13.H, Z14.H] // cdd1a6a4 + ZLD2Q (R6<<4)(R14), P4.Z, [Z13.Q, Z14.Q] // cd91a6a4 + ZLD2W (R6<<2)(R14), P4.Z, [Z13.S, Z14.S] // cdd126a5 + ZLD3B (R6)(R14), P4.Z, [Z13.B, Z14.B, Z15.B] // cdd146a4 + ZLD3D (R6<<3)(R14), P4.Z, [Z13.D, Z14.D, Z15.D] // cdd1c6a5 + ZLD3H (R6<<1)(R14), P4.Z, [Z13.H, Z14.H, Z15.H] // cdd1c6a4 + ZLD3Q (R6<<4)(R14), P4.Z, [Z13.Q, Z14.Q, Z15.Q] // cd9126a5 + ZLD3W (R6<<2)(R14), P4.Z, [Z13.S, Z14.S, Z15.S] // cdd146a5 + ZLD4B (R6)(R14), P4.Z, [Z13.B, Z14.B, Z15.B, Z16.B]// cdd166a4 + ZLD4D (R6<<3)(R14), P4.Z, [Z13.D, Z14.D, Z15.D, Z16.D]// cdd1e6a5 + ZLD4H (R6<<1)(R14), P4.Z, [Z13.H, Z14.H, Z15.H, Z16.H]// cdd1e6a4 + ZLD4Q (R6<<4)(R14), P4.Z, [Z13.Q, Z14.Q, Z15.Q, Z16.Q]// cd91a6a5 + ZLD4W (R6<<2)(R14), P4.Z, [Z13.S, Z14.S, Z15.S, Z16.S]// cdd166a5 + ZLDFF1B (R6)(R14), P4.Z, [Z13.B] // cd7106a4 + ZLDFF1B (R6)(R14), P4.Z, [Z13.H] // cd7126a4 + ZLDFF1B (R6)(R14), P4.Z, [Z13.S] // cd7146a4 + ZLDFF1B (R6)(R14), P4.Z, [Z13.D] // cd7166a4 + ZLDFF1B (Z10.D)(R19), P3.Z, [Z15.D] // 6fee4ac4 + ZLDFF1B (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 646c0484 + ZLDFF1B (Z6.D)(R14), P4.Z, [Z13.D] // cdf146c4 + ZLDFF1D (R6<<3)(R14), P4.Z, [Z13.D] // cd71e6a5 + ZLDFF1D (Z23.D<<3)(R24), P1.Z, [Z22.D] // 16e7f7c5 + ZLDFF1D (Z10.D)(R19), P3.Z, [Z15.D] // 6feecac5 + ZLDFF1D (Z6.D<<3)(R14), P4.Z, [Z13.D] // cdf1e6c5 + ZLDFF1D (Z6.D)(R14), P4.Z, [Z13.D] // cdf1c6c5 + ZLDFF1H (R6<<1)(R14), P4.Z, [Z13.H] // cd71a6a4 + ZLDFF1H (R6<<1)(R14), P4.Z, [Z13.S] // cd71c6a4 + ZLDFF1H (R6<<1)(R14), P4.Z, [Z13.D] // cd71e6a4 + ZLDFF1H (Z4.S.UXTW<<1)(R3), P3.Z, [Z4.S] // 646ca484 + ZLDFF1H (Z23.D<<1)(R24), P1.Z, [Z22.D] // 16e7f7c4 + ZLDFF1H (Z10.D)(R19), P3.Z, [Z15.D] // 6feecac4 + ZLDFF1H (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 646c8484 + ZLDFF1H (Z6.D<<1)(R14), P4.Z, [Z13.D] // cdf1e6c4 + ZLDFF1H (Z6.D)(R14), P4.Z, [Z13.D] // cdf1c6c4 + ZLDFF1SB (R6)(R14), P4.Z, [Z13.H] // cd71c6a5 + ZLDFF1SB (R6)(R14), P4.Z, [Z13.S] // cd71a6a5 + ZLDFF1SB (R6)(R14), P4.Z, [Z13.D] // cd7186a5 + ZLDFF1SB (Z10.D)(R19), P3.Z, [Z15.D] // 6fae4ac4 + ZLDFF1SB (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 642c0484 + ZLDFF1SB (Z6.D)(R14), P4.Z, [Z13.D] // cdb146c4 + ZLDFF1SH (R6<<1)(R14), P4.Z, [Z13.S] // cd7126a5 + ZLDFF1SH (R6<<1)(R14), P4.Z, [Z13.D] // cd7106a5 + ZLDFF1SH (Z4.S.UXTW<<1)(R3), P3.Z, [Z4.S] // 642ca484 + ZLDFF1SH (Z23.D<<1)(R24), P1.Z, [Z22.D] // 16a7f7c4 + ZLDFF1SH (Z10.D)(R19), P3.Z, [Z15.D] // 6faecac4 + ZLDFF1SH (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 642c8484 + ZLDFF1SH (Z6.D<<1)(R14), P4.Z, [Z13.D] // cdb1e6c4 + ZLDFF1SH (Z6.D)(R14), P4.Z, [Z13.D] // cdb1c6c4 + ZLDFF1SW (R6<<2)(R14), P4.Z, [Z13.D] // cd7186a4 + ZLDFF1SW (Z23.D<<2)(R24), P1.Z, [Z22.D] // 16a777c5 + ZLDFF1SW (Z10.D)(R19), P3.Z, [Z15.D] // 6fae4ac5 + ZLDFF1SW (Z6.D<<2)(R14), P4.Z, [Z13.D] // cdb166c5 + ZLDFF1SW (Z6.D)(R14), P4.Z, [Z13.D] // cdb146c5 + ZLDFF1W (R6<<2)(R14), P4.Z, [Z13.S] // cd7146a5 + ZLDFF1W (R6<<2)(R14), P4.Z, [Z13.D] // cd7166a5 + ZLDFF1W (Z4.S.UXTW<<2)(R3), P3.Z, [Z4.S] // 646c2485 + ZLDFF1W (Z23.D<<2)(R24), P1.Z, [Z22.D] // 16e777c5 + ZLDFF1W (Z10.D)(R19), P3.Z, [Z15.D] // 6fee4ac5 + ZLDFF1W (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 646c0485 + ZLDFF1W (Z6.D<<2)(R14), P4.Z, [Z13.D] // cdf166c5 + ZLDFF1W (Z6.D)(R14), P4.Z, [Z13.D] // cdf146c5 + ZLDNT1B (R6)(R14), P4.Z, [Z13.B] // cdd106a4 + ZLDNT1B (R6)(Z7.S), P4.Z, [Z13.S] // edb00684 + ZLDNT1B (R6)(Z7.D), P4.Z, [Z13.D] // edd006c4 + ZLDNT1D (R6<<3)(R14), P4.Z, [Z13.D] // cdd186a5 + ZLDNT1D (R6)(Z7.D), P4.Z, [Z13.D] // edd086c5 + ZLDNT1H (R6<<1)(R14), P4.Z, [Z13.H] // cdd186a4 + ZLDNT1H (R6)(Z7.S), P4.Z, [Z13.S] // edb08684 + ZLDNT1H (R6)(Z7.D), P4.Z, [Z13.D] // edd086c4 + ZLDNT1SB (R6)(Z7.S), P4.Z, [Z13.S] // ed900684 + ZLDNT1SB (R6)(Z7.D), P4.Z, [Z13.D] // ed9006c4 + ZLDNT1SH (R6)(Z7.S), P4.Z, [Z13.S] // ed908684 + ZLDNT1SH (R6)(Z7.D), P4.Z, [Z13.D] // ed9086c4 + ZLDNT1SW (R6)(Z7.D), P4.Z, [Z13.D] // ed9006c5 + ZLDNT1W (R6<<2)(R14), P4.Z, [Z13.S] // cdd106a5 + ZLDNT1W (R6)(Z7.S), P4.Z, [Z13.S] // edb00685 + ZLDNT1W (R6)(Z7.D), P4.Z, [Z13.D] // edd006c5 + ZST1B [Z7.D], P4, (R21)(R7) // e75075e4 + ZST1B [Z6.D], P4, (Z21.D.UXTW)(R7) // e69015e4 + ZST1B [Z6.S], P4, (Z21.S.UXTW)(R7) // e69055e4 + ZST1B [Z8.D], P3, (Z6.D)(RSP) // e8af06e4 + ZST1D [Z8.D], P3, (R6<<3)(RSP) // e84fe6e5 + ZST1D [Z8.Q], P3, (R6<<3)(RSP) // e84fc6e5 + ZST1D [Z6.D], P4, (Z21.D.UXTW<<3)(R7) // e690b5e5 + ZST1D [Z6.D], P4, (Z21.D.UXTW)(R7) // e69095e5 + ZST1D [Z8.D], P3, (Z6.D<<3)(RSP) // e8afa6e5 + ZST1D [Z8.D], P3, (Z6.D)(RSP) // e8af86e5 + ZST1H [Z7.D], P4, (R21<<1)(R7) // e750f5e4 + ZST1H [Z6.S], P4, (Z21.S.UXTW<<1)(R7) // e690f5e4 + ZST1H [Z6.D], P4, (Z21.D.UXTW<<1)(R7) // e690b5e4 + ZST1H [Z6.D], P4, (Z21.D.UXTW)(R7) // e69095e4 + ZST1H [Z6.S], P4, (Z21.S.UXTW)(R7) // e690d5e4 + ZST1H [Z8.D], P3, (Z6.D<<1)(RSP) // e8afa6e4 + ZST1H [Z8.D], P3, (Z6.D)(RSP) // e8af86e4 + ZST1Q [Z8.Q], P3, (R6)(Z15.D) // e82d26e4 + ZST1W [Z7.D], P4, (R21<<2)(R7) // e75075e5 + ZST1W [Z8.Q], P3, (R6<<2)(RSP) // e84f06e5 + ZST1W [Z6.S], P4, (Z21.S.UXTW<<2)(R7) // e69075e5 + ZST1W [Z6.D], P4, (Z21.D.UXTW<<2)(R7) // e69035e5 + ZST1W [Z6.D], P4, (Z21.D.UXTW)(R7) // e69015e5 + ZST1W [Z6.S], P4, (Z21.S.UXTW)(R7) // e69055e5 + ZST1W [Z8.D], P3, (Z6.D<<2)(RSP) // e8af26e5 + ZST1W [Z8.D], P3, (Z6.D)(RSP) // e8af06e5 + ZST2B [Z8.B, Z9.B], P3, (R6)(RSP) // e86f26e4 + ZST2D [Z8.D, Z9.D], P3, (R6<<3)(RSP) // e86fa6e5 + ZST2H [Z8.H, Z9.H], P3, (R6<<1)(RSP) // e86fa6e4 + ZST2Q [Z8.Q, Z9.Q], P3, (R6<<4)(RSP) // e80f66e4 + ZST2W [Z8.S, Z9.S], P3, (R6<<2)(RSP) // e86f26e5 + ZST3B [Z8.B, Z9.B, Z10.B], P3, (R6)(RSP) // e86f46e4 + ZST3D [Z8.D, Z9.D, Z10.D], P3, (R6<<3)(RSP) // e86fc6e5 + ZST3H [Z8.H, Z9.H, Z10.H], P3, (R6<<1)(RSP) // e86fc6e4 + ZST3Q [Z8.Q, Z9.Q, Z10.Q], P3, (R6<<4)(RSP) // e80fa6e4 + ZST3W [Z8.S, Z9.S, Z10.S], P3, (R6<<2)(RSP) // e86f46e5 + ZST4B [Z8.B, Z9.B, Z10.B, Z11.B], P3, (R6)(RSP) // e86f66e4 + ZST4D [Z8.D, Z9.D, Z10.D, Z11.D], P3, (R6<<3)(RSP)// e86fe6e5 + ZST4H [Z8.H, Z9.H, Z10.H, Z11.H], P3, (R6<<1)(RSP)// e86fe6e4 + ZST4Q [Z8.Q, Z9.Q, Z10.Q, Z11.Q], P3, (R6<<4)(RSP)// e80fe6e4 + ZST4W [Z8.S, Z9.S, Z10.S, Z11.S], P3, (R6<<2)(RSP)// e86f66e5 + ZSTNT1B [Z8.B], P3, (R6)(RSP) // e86f06e4 + ZSTNT1B [Z8.S], P3, (R6)(Z15.S) // e82d46e4 + ZSTNT1B [Z8.D], P3, (R6)(Z15.D) // e82d06e4 + ZSTNT1D [Z8.D], P3, (R6<<3)(RSP) // e86f86e5 + ZSTNT1D [Z8.D], P3, (R6)(Z15.D) // e82d86e5 + ZSTNT1H [Z8.H], P3, (R6<<1)(RSP) // e86f86e4 + ZSTNT1H [Z8.S], P3, (R6)(Z15.S) // e82dc6e4 + ZSTNT1H [Z8.D], P3, (R6)(Z15.D) // e82d86e4 + ZSTNT1W [Z8.S], P3, (R6<<2)(RSP) // e86f06e5 + ZSTNT1W [Z8.S], P3, (R6)(Z15.S) // e82d46e5 + ZSTNT1W [Z8.D], P3, (R6)(Z15.D) // e82d06e5 + PCNTP VLx2, PN13.D, R5 // a583e025 + PPRFB (R8)(RSP), P3, PSTL3KEEP // eccf0884 + PPRFD (R8<<3)(RSP), P3, PSTL3KEEP // eccf8885 + PPRFH (R8<<1)(RSP), P3, PSTL3KEEP // eccf8884 + PPRFW (R8<<2)(RSP), P3, PSTL3KEEP // eccf0885 + PWHILEGE VLx4, R21, R9, PN12.H // 34617525 + PWHILEGT VLx4, R21, R9, PN12.H // 3c617525 + PWHILEHI VLx4, R21, R9, PN12.H // 3c697525 + PWHILEHS VLx4, R21, R9, PN12.H // 34697525 + PWHILELE VLx4, R21, R9, PN12.H // 3c657525 + PWHILELO VLx4, R21, R9, PN12.H // 346d7525 + PWHILELS VLx4, R21, R9, PN12.H // 3c6d7525 + PWHILELT VLx4, R21, R9, PN12.H // 34657525 + ZPRFB (Z6.S.SXTW)(R14), P2, PLDL1STRM // c1096684 + ZPRFB (Z6.D.SXTW)(R14), P2, PLDL1STRM // c10966c4 + ZPRFB (Z8.D)(RSP), P3, PSTL3KEEP // ec8f68c4 + ZPRFD (Z6.S.SXTW<<3)(R14), P2, PLDL1STRM // c1696684 + ZPRFD (Z6.D.SXTW<<3)(R14), P2, PLDL1STRM // c16966c4 + ZPRFD (Z8.D<<3)(RSP), P3, PSTL3KEEP // ecef68c4 + ZPRFH (Z6.S.SXTW<<1)(R14), P2, PLDL1STRM // c1296684 + ZPRFH (Z6.D.SXTW<<1)(R14), P2, PLDL1STRM // c12966c4 + ZPRFH (Z8.D<<1)(RSP), P3, PSTL3KEEP // ecaf68c4 + ZPRFW (Z6.S.SXTW<<2)(R14), P2, PLDL1STRM // c1496684 + ZPRFW (Z6.D.SXTW<<2)(R14), P2, PLDL1STRM // c14966c4 + ZPRFW (Z8.D<<2)(RSP), P3, PSTL3KEEP // eccf68c4 + ZLD1B 6(Z7.S), P4.Z, [Z13.S] // edd02684 + ZLD1B 6(Z7.D), P4.Z, [Z13.D] // edd026c4 + ZLD1D 8(Z14.D), P6.Z, [Z6.D] // c6d9a1c5 + ZLD1H 6(Z7.S), P4.Z, [Z13.S] // edd0a384 + ZLD1H 6(Z7.D), P4.Z, [Z13.D] // edd0a3c4 + ZLD1RB 6(R14), P4.Z, [Z13.B] // cd914684 + ZLD1RB 6(R14), P4.Z, [Z13.H] // cdb14684 + ZLD1RB 6(R14), P4.Z, [Z13.S] // cdd14684 + ZLD1RB 6(R14), P4.Z, [Z13.D] // cdf14684 + ZLD1RD 8(R29), P6.Z, [Z6.D] // a6fbc185 + ZLD1RH 6(R14), P4.Z, [Z13.H] // cdb1c384 + ZLD1RH 6(R14), P4.Z, [Z13.S] // cdd1c384 + ZLD1RH 6(R14), P4.Z, [Z13.D] // cdf1c384 + ZLD1ROB (R5), P2.Z, [Z23.B] // b72820a4 + ZLD1ROD (R5), P2.Z, [Z23.D] // b728a0a5 + ZLD1ROH (R5), P2.Z, [Z23.H] // b728a0a4 + ZLD1ROW (R5), P2.Z, [Z23.S] // b72820a5 + ZLD1RQB (R5), P2.Z, [Z23.B] // b72800a4 + ZLD1RQD (R5), P2.Z, [Z23.D] // b72880a5 + ZLD1RQH (R5), P2.Z, [Z23.H] // b72880a4 + ZLD1RQW (R5), P2.Z, [Z23.S] // b72800a5 + ZLD1RSB 6(R14), P4.Z, [Z13.H] // cdd1c685 + ZLD1RSB 6(R14), P4.Z, [Z13.S] // cdb1c685 + ZLD1RSB 6(R14), P4.Z, [Z13.D] // cd91c685 + ZLD1RSH 6(R14), P4.Z, [Z13.S] // cdb14385 + ZLD1RSH 6(R14), P4.Z, [Z13.D] // cd914385 + ZLD1RSW 12(R4), P6.Z, [Z25.D] // 9998c384 + ZLD1RW 12(R4), P6.Z, [Z25.S] // 99d84385 + ZLD1RW 12(R4), P6.Z, [Z25.D] // 99f84385 + ZLD1SB 6(Z7.S), P4.Z, [Z13.S] // ed902684 + ZLD1SB 6(Z7.D), P4.Z, [Z13.D] // ed9026c4 + ZLD1SH 6(Z7.S), P4.Z, [Z13.S] // ed90a384 + ZLD1SH 6(Z7.D), P4.Z, [Z13.D] // ed90a3c4 + ZLD1SW 12(Z0.D), P6.Z, [Z25.D] // 199823c5 + ZLD1W 12(Z0.S), P6.Z, [Z25.S] // 19d82385 + ZLD1W 12(Z0.D), P6.Z, [Z25.D] // 19d823c5 + ZLDFF1B 6(Z7.S), P4.Z, [Z13.S] // edf02684 + ZLDFF1B 6(Z7.D), P4.Z, [Z13.D] // edf026c4 + ZLDFF1D 8(Z14.D), P6.Z, [Z6.D] // c6f9a1c5 + ZLDFF1H 6(Z7.S), P4.Z, [Z13.S] // edf0a384 + ZLDFF1H 6(Z7.D), P4.Z, [Z13.D] // edf0a3c4 + ZLDFF1SB 6(Z7.S), P4.Z, [Z13.S] // edb02684 + ZLDFF1SB 6(Z7.D), P4.Z, [Z13.D] // edb026c4 + ZLDFF1SH 6(Z7.S), P4.Z, [Z13.S] // edb0a384 + ZLDFF1SH 6(Z7.D), P4.Z, [Z13.D] // edb0a3c4 + ZLDFF1SW 12(Z0.D), P6.Z, [Z25.D] // 19b823c5 + ZLDFF1W 12(Z0.S), P6.Z, [Z25.S] // 19f82385 + ZLDFF1W 12(Z0.D), P6.Z, [Z25.D] // 19f823c5 + ZPRFB 8(Z10.S), P3, PSTL3KEEP // 4ced0884 + ZPRFB 8(Z10.D), P3, PSTL3KEEP // 4ced08c4 + ZPRFD 8(Z10.S), P3, PSTL3KEEP // 4ced8185 + ZPRFD 8(Z10.D), P3, PSTL3KEEP // 4ced81c5 + ZPRFH 8(Z10.S), P3, PSTL3KEEP // 4ced8484 + ZPRFH 8(Z10.D), P3, PSTL3KEEP // 4ced84c4 + ZPRFW 8(Z10.S), P3, PSTL3KEEP // 4ced0285 + ZPRFW 8(Z10.D), P3, PSTL3KEEP // 4ced02c5 + ZST1B [Z8.S], P3, 6(Z15.S) // e8ad66e4 + ZST1B [Z8.D], P3, 6(Z15.D) // e8ad46e4 + ZST1D [Z16.D], P2, (Z5.D) // b0a8c0e5 + ZST1H [Z8.S], P3, 6(Z15.S) // e8ade3e4 + ZST1H [Z8.D], P3, 6(Z15.D) // e8adc3e4 + ZST1W [Z16.S], P2, (Z5.S) // b0a860e5 + ZST1W [Z16.D], P2, (Z5.D) // b0a840e5 + PLDR (-VL*2)(RSP), P5 // e51bbf85 + PPRFB (VL*1)(RSP), P3, PSTL3KEEP // ec0fc185 + PPRFD (VL*1)(RSP), P3, PSTL3KEEP // ec6fc185 + PPRFH (VL*1)(RSP), P3, PSTL3KEEP // ec2fc185 + PPRFW (VL*1)(RSP), P3, PSTL3KEEP // ec4fc185 + PSTR P14, (-VL*1)(R0) // 0e1cbfe5 + ZLD1B (-VL*2)(R14), P4.Z, [Z13.B] // cdb10ea4 + ZLD1B (-VL*2)(R14), P4.Z, [Z13.H] // cdb12ea4 + ZLD1B (-VL*2)(R14), P4.Z, [Z13.S] // cdb14ea4 + ZLD1B (-VL*2)(R14), P4.Z, [Z13.D] // cdb16ea4 + ZLD1D (-VL*2)(R14), P4.Z, [Z13.D] // cdb1eea5 + ZLD1D (-VL*2)(R14), P4.Z, [Z13.Q] // cd319ea5 + ZLD1H (-VL*2)(R14), P4.Z, [Z13.H] // cdb1aea4 + ZLD1H (-VL*2)(R14), P4.Z, [Z13.S] // cdb1cea4 + ZLD1H (-VL*2)(R14), P4.Z, [Z13.D] // cdb1eea4 + ZLD1SB (-VL*2)(R14), P4.Z, [Z13.H] // cdb1cea5 + ZLD1SB (-VL*2)(R14), P4.Z, [Z13.S] // cdb1aea5 + ZLD1SB (-VL*2)(R14), P4.Z, [Z13.D] // cdb18ea5 + ZLD1SH (-VL*2)(R14), P4.Z, [Z13.S] // cdb12ea5 + ZLD1SH (-VL*2)(R14), P4.Z, [Z13.D] // cdb10ea5 + ZLD1SW (-VL*2)(R14), P4.Z, [Z13.D] // cdb18ea4 + ZLD1W (-VL*2)(R14), P4.Z, [Z13.S] // cdb14ea5 + ZLD1W (-VL*2)(R14), P4.Z, [Z13.D] // cdb16ea5 + ZLD1W (-VL*2)(R14), P4.Z, [Z13.Q] // cd311ea5 + ZLD2B (-VL*2)(R14), P4.Z, [Z13.B, Z14.B] // cdf12fa4 + ZLD2D (-VL*2)(R14), P4.Z, [Z13.D, Z14.D] // cdf1afa5 + ZLD2H (-VL*2)(R14), P4.Z, [Z13.H, Z14.H] // cdf1afa4 + ZLD2Q (-VL*2)(R14), P4.Z, [Z13.Q, Z14.Q] // cdf19fa4 + ZLD2W (-VL*2)(R14), P4.Z, [Z13.S, Z14.S] // cdf12fa5 + ZLD3B (-VL*3)(R10), P4.Z, [Z21.B, Z22.B, Z23.B] // 55f14fa4 + ZLD3D (-VL*3)(R10), P4.Z, [Z21.D, Z22.D, Z23.D] // 55f1cfa5 + ZLD3H (-VL*3)(R10), P4.Z, [Z21.H, Z22.H, Z23.H] // 55f1cfa4 + ZLD3Q (-VL*3)(R10), P4.Z, [Z21.Q, Z22.Q, Z23.Q] // 55f11fa5 + ZLD3W (-VL*3)(R10), P4.Z, [Z21.S, Z22.S, Z23.S] // 55f14fa5 + ZLD4B (VL*4)(R4), P6.Z, [Z25.B, Z26.B, Z27.B, Z28.B]// 99f861a4 + ZLD4D (VL*4)(R4), P6.Z, [Z25.D, Z26.D, Z27.D, Z28.D]// 99f8e1a5 + ZLD4H (VL*4)(R4), P6.Z, [Z25.H, Z26.H, Z27.H, Z28.H]// 99f8e1a4 + ZLD4Q (VL*4)(R4), P6.Z, [Z25.Q, Z26.Q, Z27.Q, Z28.Q]// 99f891a5 + ZLD4W (VL*4)(R4), P6.Z, [Z25.S, Z26.S, Z27.S, Z28.S]// 99f861a5 + ZLDNF1B (-VL*2)(R14), P4.Z, [Z13.B] // cdb11ea4 + ZLDNF1B (-VL*2)(R14), P4.Z, [Z13.H] // cdb13ea4 + ZLDNF1B (-VL*2)(R14), P4.Z, [Z13.S] // cdb15ea4 + ZLDNF1B (-VL*2)(R14), P4.Z, [Z13.D] // cdb17ea4 + ZLDNF1D (-VL*2)(R14), P4.Z, [Z13.D] // cdb1fea5 + ZLDNF1H (-VL*2)(R14), P4.Z, [Z13.H] // cdb1bea4 + ZLDNF1H (-VL*2)(R14), P4.Z, [Z13.S] // cdb1dea4 + ZLDNF1H (-VL*2)(R14), P4.Z, [Z13.D] // cdb1fea4 + ZLDNF1SB (-VL*2)(R14), P4.Z, [Z13.H] // cdb1dea5 + ZLDNF1SB (-VL*2)(R14), P4.Z, [Z13.S] // cdb1bea5 + ZLDNF1SB (-VL*2)(R14), P4.Z, [Z13.D] // cdb19ea5 + ZLDNF1SH (-VL*2)(R14), P4.Z, [Z13.S] // cdb13ea5 + ZLDNF1SH (-VL*2)(R14), P4.Z, [Z13.D] // cdb11ea5 + ZLDNF1SW (-VL*2)(R14), P4.Z, [Z13.D] // cdb19ea4 + ZLDNF1W (-VL*2)(R14), P4.Z, [Z13.S] // cdb15ea5 + ZLDNF1W (-VL*2)(R14), P4.Z, [Z13.D] // cdb17ea5 + ZLDNT1B (-VL*2)(R14), P4.Z, [Z13.B] // cdf10ea4 + ZLDNT1D (-VL*2)(R14), P4.Z, [Z13.D] // cdf18ea5 + ZLDNT1H (-VL*2)(R14), P4.Z, [Z13.H] // cdf18ea4 + ZLDNT1W (-VL*2)(R14), P4.Z, [Z13.S] // cdf10ea5 + ZLDR (-VL*2)(RSP), Z7 // e75bbf85 + ZST1B [Z7.D], P4, (-VL*3)(R7) // e7f06de4 + ZST1D [Z8.D], P3, (-VL*2)(RSP) // e8efeee5 + ZST1D [Z8.Q], P3, (-VL*2)(RSP) // e8efcee5 + ZST1H [Z7.D], P4, (-VL*3)(R7) // e7f0ede4 + ZST1W [Z7.D], P4, (-VL*3)(R7) // e7f06de5 + ZST1W [Z8.Q], P3, (-VL*2)(RSP) // e8ef0ee5 + ZST2B [Z8.B, Z9.B], P3, (-VL*2)(RSP) // e8ef3fe4 + ZST2D [Z8.D, Z9.D], P3, (-VL*2)(RSP) // e8efbfe5 + ZST2H [Z8.H, Z9.H], P3, (-VL*2)(RSP) // e8efbfe4 + ZST2Q [Z8.Q, Z9.Q], P3, (-VL*2)(RSP) // e80f4fe4 + ZST2W [Z8.S, Z9.S], P3, (-VL*2)(RSP) // e8ef3fe5 + ZST3B [Z2.B, Z3.B, Z4.B], P1, (-VL*3)(R12) // 82e55fe4 + ZST3D [Z2.D, Z3.D, Z4.D], P1, (-VL*3)(R12) // 82e5dfe5 + ZST3H [Z2.H, Z3.H, Z4.H], P1, (-VL*3)(R12) // 82e5dfe4 + ZST3Q [Z2.Q, Z3.Q, Z4.Q], P1, (-VL*3)(R12) // 82058fe4 + ZST3W [Z2.S, Z3.S, Z4.S], P1, (-VL*3)(R12) // 82e55fe5 + ZST4B [Z16.B, Z17.B, Z18.B, Z19.B], P2, (-VL*8)(R9)// 30e97ee4 + ZST4D [Z16.D, Z17.D, Z18.D, Z19.D], P2, (-VL*8)(R9)// 30e9fee5 + ZST4H [Z16.H, Z17.H, Z18.H, Z19.H], P2, (-VL*8)(R9)// 30e9fee4 + ZST4Q [Z16.Q, Z17.Q, Z18.Q, Z19.Q], P2, (-VL*8)(R9)// 3009cee4 + ZST4W [Z16.S, Z17.S, Z18.S, Z19.S], P2, (-VL*8)(R9)// 30e97ee5 + ZSTNT1B [Z8.B], P3, (-VL*2)(RSP) // e8ef1ee4 + ZSTNT1D [Z8.D], P3, (-VL*2)(RSP) // e8ef9ee5 + ZSTNT1H [Z8.H], P3, (-VL*2)(RSP) // e8ef9ee4 + ZSTNT1W [Z8.S], P3, (-VL*2)(RSP) // e8ef1ee5 + ZSTR Z11, (-VL*1)(R0) // 0b5cbfe5 + ZAESD Z21.Q[1], [Z22.B-Z23.B], [Z22.B-Z23.B] // b6ee2a45 + ZAESD Z10.Q[2], [Z8.B-Z11.B], [Z8.B-Z11.B] // 48ed3645 + ZAESDIMC Z21.Q[1], [Z22.B-Z23.B], [Z22.B-Z23.B] // b6ee2b45 + ZAESDIMC Z10.Q[2], [Z8.B-Z11.B], [Z8.B-Z11.B] // 48ed3745 + ZAESE Z21.Q[1], [Z22.B-Z23.B], [Z22.B-Z23.B] // b6ea2a45 + ZAESE Z10.Q[2], [Z8.B-Z11.B], [Z8.B-Z11.B] // 48e93645 + ZAESEMC Z21.Q[1], [Z22.B-Z23.B], [Z22.B-Z23.B] // b6ea2b45 + ZAESEMC Z10.Q[2], [Z8.B-Z11.B], [Z8.B-Z11.B] // 48e93745 + ZBFCVTN [Z2.H-Z3.H], Z10.B // 4a380a65 + ZFCVTN [Z2.H-Z3.H], Z10.B // 4a300a65 + ZFCVTNB [Z2.S-Z3.S], Z10.B // 4a340a65 + ZFCVTNT [Z2.S-Z3.S], Z10.B // 4a3c0a65 + // TODO: FCVTZSN + // TODO: FCVTZUN + ZLD1B (-VL*6)(R3), PN10.Z, [Z24.B-Z25.B] // 78084da0 + ZLD1B (VL*4)(RSP), PN10.Z, [Z16.B-Z19.B] // f08b41a0 + ZLD1B (R5)(R27), PN12.Z, [Z6.B-Z7.B] // 661305a0 + ZLD1B (R2)(R3), PN10.Z, [Z24.B-Z27.B] // 788802a0 + ZLD1D (-VL*6)(R3), PN10.Z, [Z24.D-Z25.D] // 78684da0 + ZLD1D (VL*4)(RSP), PN10.Z, [Z16.D-Z19.D] // f0eb41a0 + ZLD1D (R5<<3)(R27), PN12.Z, [Z6.D-Z7.D] // 667305a0 + ZLD1D (R2<<3)(R3), PN10.Z, [Z24.D-Z27.D] // 78e802a0 + ZLD1H (-VL*6)(R3), PN10.Z, [Z24.H-Z25.H] // 78284da0 + ZLD1H (VL*4)(RSP), PN10.Z, [Z16.H-Z19.H] // f0ab41a0 + ZLD1H (R5<<1)(R27), PN12.Z, [Z6.H-Z7.H] // 663305a0 + ZLD1H (R2<<1)(R3), PN10.Z, [Z24.H-Z27.H] // 78a802a0 + ZLD1W (-VL*6)(R3), PN10.Z, [Z24.S-Z25.S] // 78484da0 + ZLD1W (VL*4)(RSP), PN10.Z, [Z16.S-Z19.S] // f0cb41a0 + ZLD1W (R5<<2)(R27), PN12.Z, [Z6.S-Z7.S] // 665305a0 + ZLD1W (R2<<2)(R3), PN10.Z, [Z24.S-Z27.S] // 78c802a0 + ZLDNT1B (-VL*6)(R3), PN10.Z, [Z24.B-Z25.B] // 79084da0 + ZLDNT1B (VL*4)(RSP), PN10.Z, [Z16.B-Z19.B] // f18b41a0 + ZLDNT1B (R5)(R27), PN12.Z, [Z6.B-Z7.B] // 671305a0 + ZLDNT1B (R2)(R3), PN10.Z, [Z24.B-Z27.B] // 798802a0 + ZLDNT1D (-VL*6)(R3), PN10.Z, [Z24.D-Z25.D] // 79684da0 + ZLDNT1D (VL*4)(RSP), PN10.Z, [Z16.D-Z19.D] // f1eb41a0 + ZLDNT1D (R5<<3)(R27), PN12.Z, [Z6.D-Z7.D] // 677305a0 + ZLDNT1D (R2<<3)(R3), PN10.Z, [Z24.D-Z27.D] // 79e802a0 + ZLDNT1H (-VL*6)(R3), PN10.Z, [Z24.H-Z25.H] // 79284da0 + ZLDNT1H (VL*4)(RSP), PN10.Z, [Z16.H-Z19.H] // f1ab41a0 + ZLDNT1H (R5<<1)(R27), PN12.Z, [Z6.H-Z7.H] // 673305a0 + ZLDNT1H (R2<<1)(R3), PN10.Z, [Z24.H-Z27.H] // 79a802a0 + ZLDNT1W (-VL*6)(R3), PN10.Z, [Z24.S-Z25.S] // 79484da0 + ZLDNT1W (VL*4)(RSP), PN10.Z, [Z16.S-Z19.S] // f1cb41a0 + ZLDNT1W (R5<<2)(R27), PN12.Z, [Z6.S-Z7.S] // 675305a0 + ZLDNT1W (R2<<2)(R3), PN10.Z, [Z24.S-Z27.S] // 79c802a0 + ZPMLAL Z13.D, Z21.D, [Z22.Q-Z23.Q] // b6fe2d45 + ZPMULL Z13.D, Z21.D, [Z22.Q-Z23.Q] // b6fa2d45 + ZSQCVTN [Z2.S-Z3.S], Z10.H // 4a403145 + ZSQCVTUN [Z2.S-Z3.S], Z10.H // 4a503145 + // TODO: SQRSHRN .B, { .H-.H }, # + ZSQRSHRN $6, [Z2.S-Z3.S], Z10.H // 4a28ba45 + // TODO: SQRSHRUN .B, { .H-.H }, # + ZSQRSHRUN $6, [Z2.S-Z3.S], Z10.H // 4a08ba45 + // TODO: SQSHRN ., { .-. }, # + // TODO: SQSHRUN ., { .-. }, # + ZST1B [Z14.B-Z15.B], PN12, (-VL*4)(R17) // 2e126ea0 + ZST1B [Z4.B-Z7.B], PN12, (VL*4)(RSP) // e49361a0 + ZST1B [Z14.B-Z15.B], PN12, (R20)(R17) // 2e1234a0 + ZST1B [Z4.B-Z7.B], PN12, (R12)(RSP) // e4932ca0 + ZST1D [Z14.D-Z15.D], PN12, (-VL*4)(R17) // 2e726ea0 + ZST1D [Z4.D-Z7.D], PN12, (VL*4)(RSP) // e4f361a0 + ZST1D [Z14.D-Z15.D], PN12, (R20<<3)(R17) // 2e7234a0 + ZST1D [Z4.D-Z7.D], PN12, (R12<<3)(RSP) // e4f32ca0 + ZST1H [Z14.H-Z15.H], PN12, (-VL*4)(R17) // 2e326ea0 + ZST1H [Z4.H-Z7.H], PN12, (VL*4)(RSP) // e4b361a0 + ZST1H [Z14.H-Z15.H], PN12, (R20<<1)(R17) // 2e3234a0 + ZST1H [Z4.H-Z7.H], PN12, (R12<<1)(RSP) // e4b32ca0 + ZST1W [Z14.S-Z15.S], PN12, (-VL*4)(R17) // 2e526ea0 + ZST1W [Z4.S-Z7.S], PN12, (VL*4)(RSP) // e4d361a0 + ZST1W [Z14.S-Z15.S], PN12, (R20<<2)(R17) // 2e5234a0 + ZST1W [Z4.S-Z7.S], PN12, (R12<<2)(RSP) // e4d32ca0 + ZSTNT1B [Z14.B-Z15.B], PN12, (-VL*4)(R17) // 2f126ea0 + ZSTNT1B [Z4.B-Z7.B], PN12, (VL*4)(RSP) // e59361a0 + ZSTNT1B [Z14.B-Z15.B], PN12, (R20)(R17) // 2f1234a0 + ZSTNT1B [Z4.B-Z7.B], PN12, (R12)(RSP) // e5932ca0 + ZSTNT1D [Z14.D-Z15.D], PN12, (-VL*4)(R17) // 2f726ea0 + ZSTNT1D [Z4.D-Z7.D], PN12, (VL*4)(RSP) // e5f361a0 + ZSTNT1D [Z14.D-Z15.D], PN12, (R20<<3)(R17) // 2f7234a0 + ZSTNT1D [Z4.D-Z7.D], PN12, (R12<<3)(RSP) // e5f32ca0 + ZSTNT1H [Z14.H-Z15.H], PN12, (-VL*4)(R17) // 2f326ea0 + ZSTNT1H [Z4.H-Z7.H], PN12, (VL*4)(RSP) // e5b361a0 + ZSTNT1H [Z14.H-Z15.H], PN12, (R20<<1)(R17) // 2f3234a0 + ZSTNT1H [Z4.H-Z7.H], PN12, (R12<<1)(RSP) // e5b32ca0 + ZSTNT1W [Z14.S-Z15.S], PN12, (-VL*4)(R17) // 2f526ea0 + ZSTNT1W [Z4.S-Z7.S], PN12, (VL*4)(RSP) // e5d361a0 + ZSTNT1W [Z14.S-Z15.S], PN12, (R20<<2)(R17) // 2f5234a0 + ZSTNT1W [Z4.S-Z7.S], PN12, (R12<<2)(RSP) // e5d32ca0 + ZUQCVTN [Z2.S-Z3.S], Z10.H // 4a483145 + // TODO: UQRSHRN .B, { .H-.H }, # + ZUQRSHRN $6, [Z2.S-Z3.S], Z10.H // 4a38ba45 + // TODO: UQSHRN ., { .-. }, # + RET diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s new file mode 100644 index 00000000000000..f381ff534b94b6 --- /dev/null +++ b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s @@ -0,0 +1,1400 @@ +// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT. + +#include "../../../../../runtime/textflag.h" + +TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 + PAND P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PANDS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PBIC P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PBICS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PBRKA P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + PBRKAS P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + PBRKB P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + PBRKBS P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + PBRKN P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PBRKNS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PBRKPA P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PBRKPAS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PBRKPB P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PBRKPBS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PEOR P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PEORS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PNAND P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PNANDS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PNOR P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PNORS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PORN P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PORNS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PORR P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PORRS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PPFALSE P14.S // ERROR "illegal combination from SVE" + PPFIRST P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + PPNEXT P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + PPTEST P14.S, P13.Z // ERROR "illegal combination from SVE" + PPTRUE PN5.D // ERROR "illegal combination from SVE" + PPUNPKHI P14.S, P13.S // ERROR "illegal combination from SVE" + PPUNPKLO P14.S, P13.S // ERROR "illegal combination from SVE" + PRDFFR P14.Z, P13.S // ERROR "illegal combination from SVE" + PRDFFR P14.S // ERROR "illegal combination from SVE" + PRDFFRS P14.Z, P13.S // ERROR "illegal combination from SVE" + PREV P14.B, P5.D // ERROR "illegal combination from SVE" + PSEL P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE" + PTRN1 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE" + PTRN2 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE" + PUZP1 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE" + PUZP2 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE" + PWRFFR P14.S // ERROR "illegal combination from SVE" + PZIP1 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE" + PZIP2 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE" + ZABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZADCLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZADCLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZADDHNB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZADDHNT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZADDP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZADDPT Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZADDPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + // TODO: ADDQP + ZADDQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + // TODO: ADDSUBP + ZAESD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZAESE Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZAESIMC Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZAESMC Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZAND Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZAND Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZANDQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZASR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZASR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZASR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZASRR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBCAX Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE" + ZBDEP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBEXT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBF1CVT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZBF1CVTLT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZBF2CVT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZBF2CVTLT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZBFADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBFADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZBFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZBFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZBFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZBFDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMAX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBFMAXNM Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBFMIN Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBFMINNM Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBFMLA Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBFMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMLS Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBFMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + // TODO: BFMMLA .H, .H, .H + ZBFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMUL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBFMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFSCALE Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBFSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBFSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBGRP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBIC Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZBIC Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBSL Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE" + ZBSL1N Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE" + ZBSL2N Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE" + ZCLASTA Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZCLASTB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZCLS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZCLS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZCLZ Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZCLZ Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZCMPEQ Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPEQ Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPGE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPGE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPGT Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPGT Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPHI Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPHI Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPHS Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPHS Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPLE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPLO Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPLS Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPLT Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPNE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCMPNE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZCNOT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZCNOT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZCNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZCNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZCOMPACT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZCOMPACT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZDECP P14.B, Z7.D // ERROR "illegal combination from SVE" + ZEOR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZEOR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZEOR3 Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE" + ZEORBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZEORQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZEORTB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZEXPAND Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZF1CVT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZF1CVTLT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZF2CVT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZF2CVTLT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZFABD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFACGE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZFACGT Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZFADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFADDP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFADDQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZFAMAX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFAMIN Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFCMEQ Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZFCMGE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZFCMGT Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZFCMNE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZFCMUO Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTLT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTLT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTLT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTLT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTXNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTXNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFDIV Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFDIVR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFEXPA Z11.B, Z7.D // ERROR "illegal combination from SVE" + ZFLOGB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFLOGB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFMAD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMAX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMAXNM Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMAXNMP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMAXNMQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZFMAXP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMAXQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZFMIN Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMINNM Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMINNMP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMINNMQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZFMINP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMINQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZFMLA Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALLBB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALLBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALLTB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALLTT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLS Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + // TODO: FMMLA .H, .H, .H + ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMSB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMUL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMULX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFNMAD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFNMLA Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFNMLS Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFNMSB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFRECPE Z11.B, Z7.D // ERROR "illegal combination from SVE" + ZFRECPS Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFRECPX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRECPX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINT32X Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINT32X Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINT32Z Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINT32Z Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINT64X Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINT64X Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINT64Z Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINT64Z Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTA Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTA Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTI Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTI Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTM Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTM Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTN Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTN Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTP Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTP Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTZ Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRINTZ Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFRSQRTE Z11.B, Z7.D // ERROR "illegal combination from SVE" + ZFRSQRTS Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFSCALE Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFSQRT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFSQRT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZFSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZFTSMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFTSSEL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZHISTCNT Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZHISTSEG Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZINCP P14.B, Z7.D // ERROR "illegal combination from SVE" + ZLSL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZLSL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZLSL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZLSLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZLSR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZLSR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZLSR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZLSRR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZMAD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZMADPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMATCH Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZMLA Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZMLAPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMLS Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZMOVPRFX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZMOVPRFX Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZMSB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZMUL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZNBSL Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE" + ZNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZNMATCH Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE" + ZNOT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZNOT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZORQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZORR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZORR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZPMOV Z1.S, P13.S // ERROR "illegal combination from SVE" + ZPMOV P14.S, Z26.S // ERROR "illegal combination from SVE" + ZPMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZPMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZPMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZPMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZPMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZRADDHNB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZRADDHNT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZRAX1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZRBIT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZRBIT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZREV Z11.B, Z7.D // ERROR "illegal combination from SVE" + ZREVB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZREVB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZREVD Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZREVD Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZREVH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZREVH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZREVW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZREVW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZRSUBHNB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZRSUBHNT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSABA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + // TODO: SABAL ., ., . + ZSABALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSABALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSABD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSABDLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSABDLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSADALP Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSADDLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSADDLBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSADDLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSADDWB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSADDWT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSBCLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSBCLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + // TODO: SCVTF ., . + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + // TODO: SCVTFLT + ZSDIV Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSDIVR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + // TODO: SDOT .H, .B, .B + ZSDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSEL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSHADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSHSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSHSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSM4E Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSM4EKEY Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMAX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSMAXP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSMAXQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZSMIN Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSMINP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSMINQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZSMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMULH Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSMULH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSPLICE Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSQABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSQABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSQADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSQADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDECP P14.B, Z7.D // ERROR "illegal combination from SVE" + ZSQDMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLALBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLSLBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMULH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQINCP P14.B, Z7.D // ERROR "illegal combination from SVE" + ZSQNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSQNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMLAH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMLSH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMULH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSQRSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSQSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSQSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSQSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSQSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSQXTNB Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZSQXTNT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZSQXTUNB Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZSQXTUNT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZSRHADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSRSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSRSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSSUBLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSSUBLBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSSUBLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSSUBLTB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSSUBWB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSSUBWT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSUBHNB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSUBHNT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + // TODO: SUBP ., /M, ., . + ZSUBPT Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSUBPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSUNPKHI Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZSUNPKLO Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZSUQADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZSXTB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSXTB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSXTH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSXTH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSXTW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZSXTW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZTBX Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZTBXQ Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZTRN1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZTRN1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZTRN2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZTRN2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUABA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + // TODO: UABAL ., ., . + ZUABALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUABALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUABD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUABDLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUABDLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUADALP Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUADDLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUADDLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUADDWB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUADDWT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + // TODO: UCVTF ., . + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + // TODO: UCVTFLT + ZUDIV Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUDIVR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + // TODO: UDOT .H, .B, .B + ZUDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUHADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUHSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUHSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUMAX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUMAXP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUMAXQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZUMIN Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUMINP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUMINQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE" + ZUMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMULH Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUMULH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUQADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUQADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUQDECP P14.B, Z7.D // ERROR "illegal combination from SVE" + ZUQINCP P14.B, Z7.D // ERROR "illegal combination from SVE" + ZUQRSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUQRSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUQSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUQSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUQSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUQSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUQSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUQXTNB Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZUQXTNT Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZURECPE Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZURECPE Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZURHADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZURSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZURSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZURSQRTE Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZURSQRTE Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUSDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUSMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUSQADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE" + ZUSUBLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUSUBLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUSUBWB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUSUBWT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUUNPKHI Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZUUNPKLO Z1.S, Z26.S // ERROR "illegal combination from SVE" + ZUXTB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUXTB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUXTH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUXTH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUXTW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUXTW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZUZP1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUZP1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUZP2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUZP2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUZPQ1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUZPQ2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZZIP1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZZIP1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZZIP2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZZIP2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZZIPQ1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZZIPQ2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE" + CTERMEQ RSP, R27 // ERROR "illegal combination from SVE" + CTERMEQW RSP, R27 // ERROR "illegal combination from SVE" + CTERMNE RSP, R27 // ERROR "illegal combination from SVE" + CTERMNEW RSP, R27 // ERROR "illegal combination from SVE" + PCNTP P14.S, P13.Z, R11 // ERROR "illegal combination from SVE" + PDECP P7.Q, RSP // ERROR "illegal combination from SVE" + PFIRSTP P14.S, P13.Z, R11 // ERROR "illegal combination from SVE" + PINCP P7.Q, RSP // ERROR "illegal combination from SVE" + PLASTP P14.S, P13.Z, R11 // ERROR "illegal combination from SVE" + PSQDECP P7.Q, RSP // ERROR "illegal combination from SVE" + PSQDECPW RSP, P7.Q, R25 // ERROR "illegal combination from SVE" + PSQINCP P7.Q, RSP // ERROR "illegal combination from SVE" + PSQINCPW RSP, P7.Q, R25 // ERROR "illegal combination from SVE" + PUQDECP P7.Q, RSP // ERROR "illegal combination from SVE" + PUQDECPW P7.Q, RSP // ERROR "illegal combination from SVE" + PUQINCP P7.Q, RSP // ERROR "illegal combination from SVE" + PUQINCPW P7.Q, RSP // ERROR "illegal combination from SVE" + PWHILEGE RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILEGEW RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILEGT RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILEGTW RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILEHI RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILEHIW RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILEHS RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILEHSW RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILELE RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILELEW RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILELO RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILELOW RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILELS RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILELSW RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILELT RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILELTW RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILERW RSP, R27, P13.S // ERROR "illegal combination from SVE" + PWHILEWR RSP, R27, P13.S // ERROR "illegal combination from SVE" + ZANDVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZANDVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZANDVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZANDVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZCLASTA Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTAB Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTAD Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTAH Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTAS Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTAW Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTB Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTBB Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTBD Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTBH Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTBS Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCLASTBW Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZCPY RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZCPYB RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZCPYD RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZCPYH RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZCPYS RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZCPYW RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZDUP RSP, Z27.Q // ERROR "illegal combination from SVE" + ZDUPW RSP, Z27.Q // ERROR "illegal combination from SVE" + ZEORVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZEORVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZEORVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZEORVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFADDAD Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZFADDAH Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZFADDAS Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE" + ZFADDVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFADDVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFADDVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMAXNMVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMAXNMVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMAXNMVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMAXVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMAXVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMAXVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMINNMVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMINNMVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMINNMVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMINVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMINVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZFMINVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZINDEX RSP, R27, Z26.S // ERROR "illegal combination from SVE" + ZINDEXW RSP, R27, Z26.S // ERROR "illegal combination from SVE" + ZINSR RSP, Z27.Q // ERROR "illegal combination from SVE" + ZINSRB RSP, Z27.Q // ERROR "illegal combination from SVE" + ZINSRD RSP, Z27.Q // ERROR "illegal combination from SVE" + ZINSRH RSP, Z27.Q // ERROR "illegal combination from SVE" + ZINSRS RSP, Z27.Q // ERROR "illegal combination from SVE" + ZINSRW RSP, Z27.Q // ERROR "illegal combination from SVE" + ZLASTA Z1.S, P13.Z, R11 // ERROR "illegal combination from SVE" + ZLASTAB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZLASTAD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZLASTAH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZLASTAS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZLASTAW Z1.S, P13.Z, R11 // ERROR "illegal combination from SVE" + ZLASTB Z1.S, P13.Z, R11 // ERROR "illegal combination from SVE" + ZLASTBB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZLASTBD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZLASTBH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZLASTBS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZLASTBW Z1.S, P13.Z, R11 // ERROR "illegal combination from SVE" + ZORVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZORVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZORVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZORVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZSADDVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZSMAXVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZSMAXVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZSMAXVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZSMAXVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZSMINVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZSMINVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZSMINVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZSMINVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZUADDVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZUMAXVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZUMAXVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZUMAXVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZUMAXVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZUMINVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZUMINVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZUMINVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + ZUMINVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE" + PPEXT PN6[3], P5.D // ERROR "illegal combination from SVE" + ZBFDOT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMLA Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMLALB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMLALT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMLS Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMLSLB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMLSLT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZBFMUL Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZDUP Z7.D[2], Z23.B // ERROR "illegal combination from SVE" + ZDUPQ Z27.Q[1], Z25.Q // ERROR "illegal combination from SVE" + ZFDOT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFDOT Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFDOT Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLA Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLA Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLA Z27.D[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALB Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALLBB Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALLBT Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALLTB Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALLTT Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLALT Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLS Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLS Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLS Z27.D[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLSLB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMLSLT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMUL Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMUL Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZFMUL Z27.D[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMLA Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMLA Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMLA Z27.D[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMLS Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMLS Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMLS Z27.D[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMUL Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMUL Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZMUL Z27.D[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZPMOV Z13[3], P1.Q // ERROR "illegal combination from SVE" + ZPMOV Z13[3], P1.Q // ERROR "illegal combination from SVE" + ZPMOV Z13[3], P1.Q // ERROR "illegal combination from SVE" + ZPMOV P14.B, Z6[3] // ERROR "illegal combination from SVE" + ZPMOV P14.B, Z6[3] // ERROR "illegal combination from SVE" + ZPMOV P14.B, Z6[3] // ERROR "illegal combination from SVE" + // TODO: SDOT .H, .B, .B[] + ZSDOT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSDOT Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSDOT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLALB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLALB Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLALT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLALT Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLSLB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLSLB Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLSLT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMLSLT Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMULLB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMULLB Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMULLT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSMULLT Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLALB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLALB Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLALT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLALT Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLSLB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLSLB Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLSLT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMLSLT Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMULH Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMULH Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMULH Z27.D[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMULLB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMULLB Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMULLT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQDMULLT Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMLAH Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMLAH Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMLAH Z27.D[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMLSH Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMLSH Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMLSH Z27.D[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMULH Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMULH Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSQRDMULH Z27.D[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZSUDOT Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + // TODO: UDOT .H, .B, .B[] + ZUDOT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUDOT Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUDOT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLALB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLALB Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLALT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLALT Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLSLB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLSLB Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLSLT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMLSLT Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMULLB Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMULLB Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMULLT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUMULLT Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ZUSDOT Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ADDPL $1, R27, ZR // ERROR "illegal combination from SVE" + ADDVL $1, R27, ZR // ERROR "illegal combination from SVE" + RDVL $11, RSP // ERROR "illegal combination from SVE" + ZADD $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZAND $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZASR $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZASR $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZASRD $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZCADD $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCDOT $1, Z26.B[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCDOT $1, Z26.H[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCDOT $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCMLA $1, Z26.H[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCMLA $1, Z26.S[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCMLA $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCMPEQ $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPGE $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPGT $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPHI $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPHS $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPLE $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPLO $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPLS $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPLT $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPNE $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCPY $1, P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZCPY $1, P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZDUP $1, Z27.Q // ERROR "illegal combination from SVE" + ZDUPM $1, Z27.Q // ERROR "illegal combination from SVE" + ZEOR $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZEXT $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZEXTQ $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZFADD $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFCADD $1, Z27.Q, Z25.Q, P0.Z, Z6.H // ERROR "illegal combination from SVE" + ZFCMEQ $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCMGE $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCMGT $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCMLA $1, Z26.H[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZFCMLA $1, Z26.S[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZFCMLA $1, Z27.Q, Z25.Q, P0.Z, Z6.H // ERROR "illegal combination from SVE" + ZFCMLE $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCMLT $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCMNE $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCPY $(3.6), P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZFDUP $(3.6), Z27.Q // ERROR "illegal combination from SVE" + ZFMAX $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFMAXNM $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFMIN $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFMINNM $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFMUL $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFSUB $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFSUBR $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFTMAD $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZINDEX RSP, $11, Z26.S // ERROR "illegal combination from SVE" + ZINDEX $7, $90, Z21.Q // ERROR "illegal combination from SVE" + // TODO: INDEX + ZINDEXW RSP, $11, Z26.S // ERROR "illegal combination from SVE" + // TODO: INDEX + ZLSL $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZLSL $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZLSR $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZLSR $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZMUL $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZORR $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZRSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZRSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSLI $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSMAX $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSMIN $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQADD $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQCADD $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZSQRDCMLAH $1, Z26.H[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZSQRDCMLAH $1, Z26.S[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZSQRDCMLAH $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZSQRSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQRSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQRSHRUNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQRSHRUNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQSHL $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZSQSHLU $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZSQSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQSHRUNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQSHRUNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQSUB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSRI $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSRSHR $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZSRSRA $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSSHLLB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSSHLLT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSSRA $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSUB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSUBR $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUMAX $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUMIN $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQADD $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQRSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQRSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQSHL $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZUQSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQSUB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZURSHR $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZURSRA $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUSHLLB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUSHLLT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUSRA $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZXAR $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + PPEXT PN6[3], [P5.D, P6.D] // ERROR "illegal combination from SVE" + PWHILEGE RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE" + PWHILEGT RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE" + PWHILEHI RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE" + PWHILEHS RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE" + PWHILELE RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE" + PWHILELO RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE" + PWHILELS RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE" + PWHILELT RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE" + ZEXT $1, [Z27.Q, Z28.Q], Z25.Q // ERROR "illegal combination from SVE" + ZLUTI2 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE" + ZLUTI2 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE" + ZLUTI4 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE" + ZLUTI4 Z27[1], [Z26.S, Z27.S], Z11.B // ERROR "illegal combination from SVE" + ZLUTI4 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE" + // TODO: LUTI6 + // TODO: LUTI6 + ZSPLICE [Z1.S, Z2.S], P13.Z, Z11.B // ERROR "illegal combination from SVE" + ZTBL Z1.S, [Z26.S], Z11.B // ERROR "illegal combination from SVE" + ZTBL Z1.S, [Z26.S, Z27.S], Z11.B // ERROR "illegal combination from SVE" + ZTBLQ Z1.S, [Z26.S], Z11.B // ERROR "illegal combination from SVE" + ZADR (Z26.S.SXTW<<1)(Z1.S), Z7.D // ERROR "illegal combination from SVE" + ZADR (Z27.D.SXTW<<3)(Z1.D), Z25.Q // ERROR "illegal combination from SVE" + ZADR (Z27.D.UXTW<<3)(Z1.D), Z25.Q // ERROR "illegal combination from SVE" + ZLD1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1B (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1B (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1D (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1D (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1D (Z27.D.UXTW<<3)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1D (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1D (Z27.D<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1D (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (Z27.S.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1H (Z27.D.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1H (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1H (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1H (Z27.D<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1Q (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROD (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROW (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQD (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQW (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SB (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SB (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.S.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.D.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.D<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SW (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SW (Z27.D.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SW (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SW (Z27.D<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SW (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W (Z27.S.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1W (Z27.D.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1W (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1W (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1W (Z27.D<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD2B (R27)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2D (R27<<3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2H (R27<<1)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2Q (R27<<4)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2W (R27<<2)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD3B (R27)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3D (R27<<3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3H (R27<<1)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3Q (R27<<4)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3W (R27<<2)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD4B (R27)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4D (R27<<3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4H (R27<<1)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4Q (R27<<4)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4W (R27<<2)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLDFF1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1B (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1B (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1B (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1D (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1D (Z27.D.UXTW<<3)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1D (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1D (Z27.D<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1D (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.S.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.D.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.D<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SB (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SB (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SB (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.S.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.D.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.D<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SW (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SW (Z27.D.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SW (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SW (Z27.D<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SW (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1W (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1W (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.S.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.D.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.D<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1B (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1B (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1D (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1D (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1H (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1H (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1SB (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1SB (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1SH (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1SH (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1SW (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1W (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1W (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1W (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1B [Z1.S], P13.Z, (R6)(RSP) // ERROR "illegal combination from SVE" + ZST1B [Z1.S], P13.Z, (Z6.D.SXTW)(RSP) // ERROR "illegal combination from SVE" + ZST1B [Z1.S], P13.Z, (Z6.S.SXTW)(RSP) // ERROR "illegal combination from SVE" + ZST1B [Z1.S], P13.Z, (Z6.D)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S], P13.Z, (R6<<3)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S], P13.Z, (R6<<3)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S], P13.Z, (Z6.D.SXTW<<3)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S], P13.Z, (Z6.D.SXTW)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S], P13.Z, (Z6.D<<3)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S], P13.Z, (Z6.D)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S], P13.Z, (R6<<1)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S], P13.Z, (Z6.S.SXTW<<1)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S], P13.Z, (Z6.D.SXTW<<1)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S], P13.Z, (Z6.D.SXTW)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S], P13.Z, (Z6.S.SXTW)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S], P13.Z, (Z6.D<<1)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S], P13.Z, (Z6.D)(RSP) // ERROR "illegal combination from SVE" + ZST1Q [Z1.S], P13.Z, (R6)(Z11.D) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, (R6<<2)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, (R6<<2)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, (Z6.S.SXTW<<2)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, (Z6.D.SXTW<<2)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, (Z6.D.SXTW)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, (Z6.S.SXTW)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, (Z6.D<<2)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, (Z6.D)(RSP) // ERROR "illegal combination from SVE" + ZST2B [Z1.S, Z2.S], P13.Z, (R6)(RSP) // ERROR "illegal combination from SVE" + ZST2D [Z1.S, Z2.S], P13.Z, (R6<<3)(RSP) // ERROR "illegal combination from SVE" + ZST2H [Z1.S, Z2.S], P13.Z, (R6<<1)(RSP) // ERROR "illegal combination from SVE" + ZST2Q [Z1.S, Z2.S], P13.Z, (R6<<4)(RSP) // ERROR "illegal combination from SVE" + ZST2W [Z1.S, Z2.S], P13.Z, (R6<<2)(RSP) // ERROR "illegal combination from SVE" + ZST3B [Z1.S, Z2.S, Z3.S], P13.Z, (R6)(RSP) // ERROR "illegal combination from SVE" + ZST3D [Z1.S, Z2.S, Z3.S], P13.Z, (R6<<3)(RSP) // ERROR "illegal combination from SVE" + ZST3H [Z1.S, Z2.S, Z3.S], P13.Z, (R6<<1)(RSP) // ERROR "illegal combination from SVE" + ZST3Q [Z1.S, Z2.S, Z3.S], P13.Z, (R6<<4)(RSP) // ERROR "illegal combination from SVE" + ZST3W [Z1.S, Z2.S, Z3.S], P13.Z, (R6<<2)(RSP) // ERROR "illegal combination from SVE" + ZST4B [Z1.S, Z2.S, Z3.S, Z4.S], P13.Z, (R6)(RSP) // ERROR "illegal combination from SVE" + ZST4D [Z1.S, Z2.S, Z3.S, Z4.S], P13.Z, (R6<<3)(RSP)// ERROR "illegal combination from SVE" + ZST4H [Z1.S, Z2.S, Z3.S, Z4.S], P13.Z, (R6<<1)(RSP)// ERROR "illegal combination from SVE" + ZST4Q [Z1.S, Z2.S, Z3.S, Z4.S], P13.Z, (R6<<4)(RSP)// ERROR "illegal combination from SVE" + ZST4W [Z1.S, Z2.S, Z3.S, Z4.S], P13.Z, (R6<<2)(RSP)// ERROR "illegal combination from SVE" + ZSTNT1B [Z1.S], P13.Z, (R6)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1B [Z1.S], P13.Z, (R6)(Z11.S) // ERROR "illegal combination from SVE" + ZSTNT1B [Z1.S], P13.Z, (R6)(Z11.D) // ERROR "illegal combination from SVE" + ZSTNT1D [Z1.S], P13.Z, (R6<<3)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1D [Z1.S], P13.Z, (R6)(Z11.D) // ERROR "illegal combination from SVE" + ZSTNT1H [Z1.S], P13.Z, (R6<<1)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1H [Z1.S], P13.Z, (R6)(Z11.S) // ERROR "illegal combination from SVE" + ZSTNT1H [Z1.S], P13.Z, (R6)(Z11.D) // ERROR "illegal combination from SVE" + ZSTNT1W [Z1.S], P13.Z, (R6<<2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1W [Z1.S], P13.Z, (R6)(Z11.S) // ERROR "illegal combination from SVE" + ZSTNT1W [Z1.S], P13.Z, (R6)(Z11.D) // ERROR "illegal combination from SVE" + PCNTP VLx4, PN7.Q, R25 // ERROR "illegal combination from SVE" + PPRFB (R27)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + PPRFD (R27<<3)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + PPRFH (R27<<1)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + PPRFW (R27<<2)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + PWHILEGE VLx4, R27, ZR, PN7.Q // ERROR "illegal combination from SVE" + PWHILEGT VLx4, R27, ZR, PN7.Q // ERROR "illegal combination from SVE" + PWHILEHI VLx4, R27, ZR, PN7.Q // ERROR "illegal combination from SVE" + PWHILEHS VLx4, R27, ZR, PN7.Q // ERROR "illegal combination from SVE" + PWHILELE VLx4, R27, ZR, PN7.Q // ERROR "illegal combination from SVE" + PWHILELO VLx4, R27, ZR, PN7.Q // ERROR "illegal combination from SVE" + PWHILELS VLx4, R27, ZR, PN7.Q // ERROR "illegal combination from SVE" + PWHILELT VLx4, R27, ZR, PN7.Q // ERROR "illegal combination from SVE" + ZPRFB (Z27.S.UXTW)(RSP), P7.Z, PLDL1KEEP // ERROR "illegal combination from SVE" + ZPRFB (Z27.D.UXTW)(RSP), P7.Z, PLDL1KEEP // ERROR "illegal combination from SVE" + ZPRFB (Z27.D)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZPRFD (Z27.S.UXTW<<3)(RSP), P7.Z, PLDL1KEEP // ERROR "illegal combination from SVE" + ZPRFD (Z27.D.UXTW<<3)(RSP), P7.Z, PLDL1KEEP // ERROR "illegal combination from SVE" + ZPRFD (Z27.D<<3)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZPRFH (Z27.S.UXTW<<1)(RSP), P7.Z, PLDL1KEEP // ERROR "illegal combination from SVE" + ZPRFH (Z27.D.UXTW<<1)(RSP), P7.Z, PLDL1KEEP // ERROR "illegal combination from SVE" + ZPRFH (Z27.D<<1)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZPRFW (Z27.S.UXTW<<2)(RSP), P7.Z, PLDL1KEEP // ERROR "illegal combination from SVE" + ZPRFW (Z27.D.UXTW<<2)(RSP), P7.Z, PLDL1KEEP // ERROR "illegal combination from SVE" + ZPRFW (Z27.D<<2)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZLD1B 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1D 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RB 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RB 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RB 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RB 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RD 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RH 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RH 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RH 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROB 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROD 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROH 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROW 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQB 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQD 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQH 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQW 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RSB 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RSB 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RSB 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RSH 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RSH 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RSW 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RW 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RW 11(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SW 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1B 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1B 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1D 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SB 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SB 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SH 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SH 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SW 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1W 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1W 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZPRFB 11(Z1.S), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZPRFB 11(Z1.D), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZPRFD 11(Z1.S), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZPRFD 11(Z1.D), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZPRFH 11(Z1.S), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZPRFH 11(Z1.D), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZPRFW 11(Z1.S), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZPRFW 11(Z1.D), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + ZST1B [Z1.S], P13.Z, 6(Z11.S) // ERROR "illegal combination from SVE" + ZST1B [Z1.S], P13.Z, 6(Z11.D) // ERROR "illegal combination from SVE" + ZST1D [Z1.S], P13.Z, 6(Z11.D) // ERROR "illegal combination from SVE" + ZST1H [Z1.S], P13.Z, 6(Z11.S) // ERROR "illegal combination from SVE" + ZST1H [Z1.S], P13.Z, 6(Z11.D) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, 6(Z11.S) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, 6(Z11.D) // ERROR "illegal combination from SVE" + PLDR (VL*3)(RSP), P13.Z // ERROR "illegal combination from SVE" + PPRFB (VL*3)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + PPRFD (VL*3)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + PPRFH (VL*3)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + PPRFW (VL*3)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE" + PSTR P14.Z, (VL*1)(RSP) // ERROR "illegal combination from SVE" + ZLD1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1D (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1D (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SW (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD2B (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2D (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2H (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2Q (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2W (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD3B (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3D (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3H (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3Q (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3W (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD4B (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4D (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4H (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4Q (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4W (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLDNF1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1D (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1SH (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1SH (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1SW (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1W (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNF1W (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1D (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1W (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDR (VL*3)(RSP), Z26.S // ERROR "illegal combination from SVE" + ZST1B [Z1.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST2B [Z1.S, Z2.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST2D [Z1.S, Z2.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST2H [Z1.S, Z2.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST2Q [Z1.S, Z2.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST2W [Z1.S, Z2.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST3B [Z1.S, Z2.S, Z3.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST3D [Z1.S, Z2.S, Z3.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST3H [Z1.S, Z2.S, Z3.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST3Q [Z1.S, Z2.S, Z3.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST3W [Z1.S, Z2.S, Z3.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST4B [Z1.S, Z2.S, Z3.S, Z4.S], P13.Z, (-VL*2)(RSP)// ERROR "illegal combination from SVE" + ZST4D [Z1.S, Z2.S, Z3.S, Z4.S], P13.Z, (-VL*2)(RSP)// ERROR "illegal combination from SVE" + ZST4H [Z1.S, Z2.S, Z3.S, Z4.S], P13.Z, (-VL*2)(RSP)// ERROR "illegal combination from SVE" + ZST4Q [Z1.S, Z2.S, Z3.S, Z4.S], P13.Z, (-VL*2)(RSP)// ERROR "illegal combination from SVE" + ZST4W [Z1.S, Z2.S, Z3.S, Z4.S], P13.Z, (-VL*2)(RSP)// ERROR "illegal combination from SVE" + ZSTNT1B [Z1.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1D [Z1.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1H [Z1.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1W [Z1.S], P13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTR Z1.S, (VL*1)(RSP) // ERROR "illegal combination from SVE" + ZAESD Z27.Q[1], [Z26.S-Z27.S], [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZAESD Z27.Q[1], [Z26.S-Z29.S], [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZAESDIMC Z27.Q[1], [Z26.S-Z27.S], [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZAESDIMC Z27.Q[1], [Z26.S-Z29.S], [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZAESE Z27.Q[1], [Z26.S-Z27.S], [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZAESE Z27.Q[1], [Z26.S-Z29.S], [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZAESEMC Z27.Q[1], [Z26.S-Z27.S], [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZAESEMC Z27.Q[1], [Z26.S-Z29.S], [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZBFCVTN [Z1.S-Z2.S], Z26.S // ERROR "illegal combination from SVE" + ZFCVTN [Z1.S-Z2.S], Z26.S // ERROR "illegal combination from SVE" + ZFCVTNB [Z1.S-Z2.S], Z26.S // ERROR "illegal combination from SVE" + ZFCVTNT [Z1.S-Z2.S], Z26.S // ERROR "illegal combination from SVE" + // TODO: FCVTZSN + // TODO: FCVTZUN + ZLD1B (VL*3)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLD1B (VL*3)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLD1B (R27)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLD1B (R27)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLD1D (VL*3)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLD1D (VL*3)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLD1D (R27<<3)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLD1D (R27<<3)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLD1H (VL*3)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLD1H (VL*3)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLD1H (R27<<1)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLD1H (R27<<1)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLD1W (VL*3)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLD1W (VL*3)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLD1W (R27<<2)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLD1W (R27<<2)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLDNT1B (VL*3)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLDNT1B (VL*3)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLDNT1B (R27)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLDNT1B (R27)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLDNT1D (VL*3)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLDNT1D (VL*3)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLDNT1D (R27<<3)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLDNT1D (R27<<3)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLDNT1H (VL*3)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLDNT1H (VL*3)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLDNT1H (R27<<1)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLDNT1H (R27<<1)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLDNT1W (VL*3)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLDNT1W (VL*3)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZLDNT1W (R27<<2)(RSP), PN13.Z, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZLDNT1W (R27<<2)(RSP), PN13.Z, [Z11.B-Z14.B] // ERROR "illegal combination from SVE" + ZPMLAL Z1.S, Z26.S, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZPMULL Z1.S, Z26.S, [Z11.B-Z12.B] // ERROR "illegal combination from SVE" + ZSQCVTN [Z1.S-Z2.S], Z26.S // ERROR "illegal combination from SVE" + ZSQCVTUN [Z1.S-Z2.S], Z26.S // ERROR "illegal combination from SVE" + // TODO: SQRSHRN .B, { .H-.H }, # + ZSQRSHRN $1, [Z27.Q-Z28.Q], Z25.Q // ERROR "illegal combination from SVE" + // TODO: SQRSHRUN .B, { .H-.H }, # + ZSQRSHRUN $1, [Z27.Q-Z28.Q], Z25.Q // ERROR "illegal combination from SVE" + // TODO: SQSHRN ., { .-. }, # + // TODO: SQSHRUN ., { .-. }, # + ZST1B [Z1.S-Z2.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1B [Z1.S-Z4.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1B [Z1.S-Z2.S], PN13.Z, (R6)(RSP) // ERROR "illegal combination from SVE" + ZST1B [Z1.S-Z4.S], PN13.Z, (R6)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S-Z2.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S-Z4.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S-Z2.S], PN13.Z, (R6<<3)(RSP) // ERROR "illegal combination from SVE" + ZST1D [Z1.S-Z4.S], PN13.Z, (R6<<3)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S-Z2.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S-Z4.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S-Z2.S], PN13.Z, (R6<<1)(RSP) // ERROR "illegal combination from SVE" + ZST1H [Z1.S-Z4.S], PN13.Z, (R6<<1)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S-Z2.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S-Z4.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S-Z2.S], PN13.Z, (R6<<2)(RSP) // ERROR "illegal combination from SVE" + ZST1W [Z1.S-Z4.S], PN13.Z, (R6<<2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1B [Z1.S-Z2.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1B [Z1.S-Z4.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1B [Z1.S-Z2.S], PN13.Z, (R6)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1B [Z1.S-Z4.S], PN13.Z, (R6)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1D [Z1.S-Z2.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1D [Z1.S-Z4.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1D [Z1.S-Z2.S], PN13.Z, (R6<<3)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1D [Z1.S-Z4.S], PN13.Z, (R6<<3)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1H [Z1.S-Z2.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1H [Z1.S-Z4.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1H [Z1.S-Z2.S], PN13.Z, (R6<<1)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1H [Z1.S-Z4.S], PN13.Z, (R6<<1)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1W [Z1.S-Z2.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1W [Z1.S-Z4.S], PN13.Z, (-VL*2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1W [Z1.S-Z2.S], PN13.Z, (R6<<2)(RSP) // ERROR "illegal combination from SVE" + ZSTNT1W [Z1.S-Z4.S], PN13.Z, (R6<<2)(RSP) // ERROR "illegal combination from SVE" + ZUQCVTN [Z1.S-Z2.S], Z26.S // ERROR "illegal combination from SVE" + // TODO: UQRSHRN .B, { .H-.H }, # + ZUQRSHRN $1, [Z27.Q-Z28.Q], Z25.Q // ERROR "illegal combination from SVE" + // TODO: UQSHRN ., { .-. }, # + RET diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s index fd86db7a4fc184..fa433d53e12134 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s @@ -33,13 +33,17 @@ lable2: MOVV R4, R5 // 85001500 MOVBU R4, R5 // 85fc4303 SUB R4, R5, R6 // a6101100 + SUBW R4, R5, R6 // a6101100 SUBV R4, R5, R6 // a6901100 ADD R4, R5, R6 // a6101000 + ADDW R4, R5, R6 // a6101000 ADDV R4, R5, R6 // a6901000 AND R4, R5, R6 // a6901400 SUB R4, R5 // a5101100 + SUBW R4, R5 // a5101100 SUBV R4, R5 // a5901100 ADD R4, R5 // a5101000 + ADDW R4, R5 // a5101000 ADDV R4, R5 // a5901000 AND R4, R5 // a5901400 NEGW R4, R5 // 05101100 @@ -93,8 +97,6 @@ lable2: MOVV R4, 1(R5) // a404c029 MOVB R4, 1(R5) // a4040029 MOVBU R4, 1(R5) // a4040029 - SC R4, 1(R5) // a4040021 - SCV R4, 1(R5) // a4040023 MOVW y+8(FP), R4 // 64408028 MOVWU y+8(FP), R4 // 6440802a MOVV y+8(FP), R4 // 6440c028 @@ -105,8 +107,6 @@ lable2: MOVV 1(R5), R4 // a404c028 MOVB 1(R5), R4 // a4040028 MOVBU 1(R5), R4 // a404002a - LL 1(R5), R4 // a4040020 - LLV 1(R5), R4 // a4040022 MOVW $4(R4), R5 // 8510c002 MOVV $4(R4), R5 // 8510c002 MOVW $-1, R4 // 04fcff02 @@ -115,6 +115,8 @@ lable2: MOVV $1, R4 // 04048003 ADD $-1, R4, R5 // 85fcbf02 ADD $-1, R4 // 84fcbf02 + ADDW $-1, R4, R5 // 85fcbf02 + ADDW $-1, R4 // 84fcbf02 ADDV $-1, R4, R5 // 85fcff02 ADDV $-1, R4 // 84fcff02 AND $1, R4, R5 // 85044003 @@ -165,6 +167,8 @@ lable2: // mul MUL R4, R5 // a5101c00 MUL R4, R5, R6 // a6101c00 + MULW R4, R5 // a5101c00 + MULW R4, R5, R6 // a6101c00 MULV R4, R5 // a5901d00 MULV R4, R5, R6 // a6901d00 MULVU R4, R5 // a5901d00 @@ -191,20 +195,26 @@ lable2: MOVHU R4, 1(R5) // a4044029 MOVHU y+8(FP), R4 // 6440402a MOVHU 1(R5), R4 // a404402a - MULU R4, R5 // a5101c00 - MULU R4, R5, R6 // a6101c00 MULH R4, R5 // a5901c00 MULH R4, R5, R6 // a6901c00 MULHU R4, R5 // a5101d00 MULHU R4, R5, R6 // a6101d00 REM R4, R5 // a5902000 REM R4, R5, R6 // a6902000 + REMW R4, R5 // a5902000 + REMW R4, R5, R6 // a6902000 REMU R4, R5 // a5902100 REMU R4, R5, R6 // a6902100 + REMWU R4, R5 // a5902100 + REMWU R4, R5, R6 // a6902100 DIV R4, R5 // a5102000 DIV R4, R5, R6 // a6102000 + DIVW R4, R5 // a5102000 + DIVW R4, R5, R6 // a6102000 DIVU R4, R5 // a5102100 DIVU R4, R5, R6 // a6102100 + DIVWU R4, R5 // a5102100 + DIVWU R4, R5, R6 // a6102100 SRLV R4, R5 // a5101900 SRLV R4, R5, R6 // a6101900 SRLV $4, R4, R5 // 85104500 @@ -212,6 +222,12 @@ lable2: SRLV $32, R4, R5 // 85804500 SRLV $32, R4 // 84804500 + // MULW.D.W[U] instructions + MULWVW R4, R5 // a5101f00 + MULWVW R4, R5, R6 // a6101f00 + MULWVWU R4, R5 // a5901f00 + MULWVWU R4, R5, R6 // a6901f00 + MASKEQZ R4, R5, R6 // a6101300 MASKNEZ R4, R5, R6 // a6901300 @@ -261,22 +277,18 @@ lable2: MOVV R4, FCC0 // 80d81401 // LDPTR.{W/D} and STPTR.{W/D} instructions - MOVWP R5, -32768(R4) // 85008025 MOVWP R5, 32764(R4) // 85fc7f25 MOVWP R5, 32(R4) // 85200025 MOVWP R5, 4(R4) // 85040025 MOVWP R5, (R4) // 85000025 - MOVVP R5, -32768(R4) // 85008027 MOVVP R5, 32764(R4) // 85fc7f27 MOVVP R5, 32(R4) // 85200027 MOVVP R5, 4(R4) // 85040027 MOVVP R5, (R4) // 85000027 - MOVWP -32768(R5), R4 // a4008024 MOVWP 32764(R5), R4 // a4fc7f24 MOVWP 32(R5), R4 // a4200024 MOVWP 4(R5), R4 // a4040024 MOVWP (R5), R4 // a4000024 - MOVVP -32768(R5), R4 // a4008026 MOVVP 32764(R5), R4 // a4fc7f26 MOVVP 32(R5), R4 // a4200026 MOVVP 4(R5), R4 // a4040026 @@ -338,6 +350,18 @@ lable2: AMMAXDBVU R14, (R13), R12 // acb97038 AMMINDBWU R14, (R13), R12 // ac397138 AMMINDBVU R14, (R13), R12 // acb97138 + LL 4096(R5), R4 // a4001020 + LLW 4096(R5), R4 // a4001020 + LLV 4096(R5), R4 // a4001022 + LLACQW (R5), R4 // a4805738 + LLACQV (R5), R4 // a4885738 + SC R4, 4096(R5) // a4001021 + SCW R4, 4096(R5) // a4001021 + SCV R4, 4096(R5) // a4001023 + SCQ R4, R5, (R6) // c4145738 + SCRELW R4, (R6) // c4845738 + SCRELV R4, (R6) // c48c5738 + FMADDF F2, F14, F9, F16 // 30391108 FMADDD F11, F20, F23, F12 // ecd22508 @@ -379,6 +403,10 @@ lable2: FTINTVF F0, F1 // 01241b01 FTINTVD F0, F1 // 01281b01 + // FRINT{F,D} instructions + FRINTF F0, F1 // 01441e01 + FRINTD F0, F1 // 01481e01 + FMAXAF F4, F5, F6 // a6900c01 FMAXAF F4, F5 // a5900c01 FMAXAD F4, F5, F6 // a6100d01 @@ -537,12 +565,18 @@ lable2: XVMOVQ X28.V[3], X8 // 88ef0377 XVMOVQ X27.V[0], X9 // 69e30377 - //Move vector element to vector. + // Move vector element to vector. VMOVQ V1.B[3], V9.B16 // 298cf772 VMOVQ V2.H[2], V8.H8 // 48c8f772 VMOVQ V3.W[1], V7.W4 // 67e4f772 VMOVQ V4.V[0], V6.V2 // 86f0f772 + // Move vector register to vector register. + VMOVQ V1, V9 // 29002d73 + VMOVQ V2, V8 // 48002d73 + XVMOVQ X3, X7 // 67002d77 + XVMOVQ X4, X6 // 86002d77 + // Load data from memory and broadcast to each element of a vector register: VMOVQ offset(Rj), . VMOVQ (R4), V0.B16 // 80008030 VMOVQ 1(R4), V0.B16 // 80048030 @@ -589,6 +623,42 @@ lable2: XVSEQV $15, X2, X4 // 44bc8176 XVSEQV $-15, X2, X4 // 44c48176 + // VSLTB{B,H,W,V}, XVSLTB{B,H,W,V} instruction + VSLTB V1, V2, V3 // 43040670 + VSLTH V1, V2, V3 // 43840670 + VSLTW V1, V2, V3 // 43040770 + VSLTV V1, V2, V3 // 43840770 + XVSLTB X1, X2, X3 // 43040674 + XVSLTH X1, X2, X3 // 43840674 + XVSLTW X1, X2, X3 // 43040774 + XVSLTV X1, X2, X3 // 43840774 + VSLTB $1, V2, V3 // 43048672 + VSLTH $-16, V2, V3 // 43c08672 + VSLTW $-16, V2, V3 // 43408772 + VSLTV $-15, V2, V3 // 43c48772 + XVSLTB $1, X2, X3 // 43048676 + XVSLTH $-16, X2, X3 // 43c08676 + XVSLTW $-16, X2, X3 // 43408776 + XVSLTV $-16, X2, X3 // 43c08776 + + // VSLTB{B,H,W,V}U, XVSLTB{B,H,W,V}U instruction + VSLTBU V1, V2, V3 // 43040870 + VSLTHU V1, V2, V3 // 43840870 + VSLTWU V1, V2, V3 // 43040970 + VSLTVU V1, V2, V3 // 43840970 + XVSLTBU X1, X2, X3 // 43040874 + XVSLTHU X1, X2, X3 // 43840874 + XVSLTWU X1, X2, X3 // 43040974 + XVSLTVU X1, X2, X3 // 43840974 + VSLTBU $0, V2, V3 // 43008872 + VSLTHU $31, V2, V3 // 43fc8872 + VSLTWU $16, V2, V3 // 43408972 + VSLTVU $1, V2, V3 // 43848972 + XVSLTBU $0, X2, X3 // 43008876 + XVSLTHU $31, X2, X3 // 43fc8876 + XVSLTWU $8, X2, X3 // 43208976 + XVSLTVU $0, X2, X3 // 43808976 + // VPCNT{B,H,W,V}, XVPCNT{B,H,W,V} instruction VPCNTB V1, V2 // 22209c72 VPCNTH V1, V2 // 22249c72 @@ -824,6 +894,7 @@ lable2: XVSUBQ X3, X2, X1 // 418c2d75 // [X]VADD{B,H,W,V}U, [X]VSUB{B,H,W,V}U instructions + VADDBU $1, V2 // 42048a72 VADDBU $1, V2, V1 // 41048a72 VADDHU $2, V2, V1 // 41888a72 VADDWU $3, V2, V1 // 410c8b72 @@ -841,6 +912,42 @@ lable2: XVSUBWU $15, X1, X2 // 223c8d76 XVSUBVU $16, X1, X2 // 22c08d76 + // [X]VSADD{B,H,W,V}, [X]VSSUB{B,H,W,V} instructions + VSADDB V1, V2, V3 // 43044670 + VSADDH V1, V2, V3 // 43844670 + VSADDW V1, V2, V3 // 43044770 + VSADDV V1, V2, V3 // 43844770 + VSSUBB V1, V2, V3 // 43044870 + VSSUBH V1, V2, V3 // 43844870 + VSSUBW V1, V2, V3 // 43044970 + VSSUBV V1, V2, V3 // 43844970 + XVSADDB X3, X2, X1 // 410c4674 + XVSADDH X3, X2, X1 // 418c4674 + XVSADDW X3, X2, X1 // 410c4774 + XVSADDV X3, X2, X1 // 418c4774 + XVSSUBB X3, X2, X1 // 410c4874 + XVSSUBH X3, X2, X1 // 418c4874 + XVSSUBW X3, X2, X1 // 410c4974 + XVSSUBV X3, X2, X1 // 418c4974 + + // [X]VSADD{B,H,W,V}U, [X]VSSUB{B,H,W,V}U instructions + VSADDBU V1, V2, V3 // 43044a70 + VSADDHU V1, V2, V3 // 43844a70 + VSADDWU V1, V2, V3 // 43044b70 + VSADDVU V1, V2, V3 // 43844b70 + VSSUBBU V1, V2, V3 // 43044c70 + VSSUBHU V1, V2, V3 // 43844c70 + VSSUBWU V1, V2, V3 // 43044d70 + VSSUBVU V1, V2, V3 // 43844d70 + XVSADDBU X1, X2, X3 // 43044a74 + XVSADDHU X1, X2, X3 // 43844a74 + XVSADDWU X1, X2, X3 // 43044b74 + XVSADDVU X1, X2, X3 // 43844b74 + XVSSUBBU X1, X2, X3 // 43044c74 + XVSSUBHU X1, X2, X3 // 43844c74 + XVSSUBWU X1, X2, X3 // 43044d74 + XVSSUBVU X1, X2, X3 // 43844d74 + // [X]VILV{L/H}{B,H,W,V} instructions VILVLB V1, V2, V3 // 43041a71 VILVLH V1, V2, V3 // 43841a71 @@ -995,6 +1102,150 @@ lable2: XVMULWODVWUW X1, X2, X3 // 4304a374 XVMULWODQVUV X1, X2, X3 // 4384a374 + // [X]VADDW{EV/OD}.{H.B/W.H/D.W/Q.D} instructions + VADDWEVHB V1, V2, V3 // 43041e70 + VADDWEVWH V1, V2, V3 // 43841e70 + VADDWEVVW V1, V2, V3 // 43041f70 + VADDWEVQV V1, V2, V3 // 43841f70 + VADDWODHB V1, V2, V3 // 43042270 + VADDWODWH V1, V2, V3 // 43842270 + VADDWODVW V1, V2, V3 // 43042370 + VADDWODQV V1, V2, V3 // 43842370 + XVADDWEVHB X1, X2, X3 // 43041e74 + XVADDWEVWH X1, X2, X3 // 43841e74 + XVADDWEVVW X1, X2, X3 // 43041f74 + XVADDWEVQV X1, X2, X3 // 43841f74 + XVADDWODHB X1, X2, X3 // 43042274 + XVADDWODWH X1, X2, X3 // 43842274 + XVADDWODVW X1, X2, X3 // 43042374 + XVADDWODQV X1, X2, X3 // 43842374 + + // [X]VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D} instructions + VSUBWEVHB V1, V2, V3 // 43042070 + VSUBWEVWH V1, V2, V3 // 43842070 + VSUBWEVVW V1, V2, V3 // 43042170 + VSUBWEVQV V1, V2, V3 // 43842170 + VSUBWODHB V1, V2, V3 // 43042470 + VSUBWODWH V1, V2, V3 // 43842470 + VSUBWODVW V1, V2, V3 // 43042570 + VSUBWODQV V1, V2, V3 // 43842570 + XVSUBWEVHB X1, X2, X3 // 43042074 + XVSUBWEVWH X1, X2, X3 // 43842074 + XVSUBWEVVW X1, X2, X3 // 43042174 + XVSUBWEVQV X1, X2, X3 // 43842174 + XVSUBWODHB X1, X2, X3 // 43042474 + XVSUBWODWH X1, X2, X3 // 43842474 + XVSUBWODVW X1, X2, X3 // 43042574 + XVSUBWODQV X1, X2, X3 // 43842574 + + // [X]VADDW{EV/OD}.{H.B/W.H/D.W/Q.D}U instructions + VADDWEVHBU V1, V2, V3 // 43042e70 + VADDWEVWHU V1, V2, V3 // 43842e70 + VADDWEVVWU V1, V2, V3 // 43042f70 + VADDWEVQVU V1, V2, V3 // 43842f70 + VADDWODHBU V1, V2, V3 // 43043270 + VADDWODWHU V1, V2, V3 // 43843270 + VADDWODVWU V1, V2, V3 // 43043370 + VADDWODQVU V1, V2, V3 // 43843370 + XVADDWEVHBU X1, X2, X3 // 43042e74 + XVADDWEVWHU X1, X2, X3 // 43842e74 + XVADDWEVVWU X1, X2, X3 // 43042f74 + XVADDWEVQVU X1, X2, X3 // 43842f74 + XVADDWODHBU X1, X2, X3 // 43043274 + XVADDWODWHU X1, X2, X3 // 43843274 + XVADDWODVWU X1, X2, X3 // 43043374 + XVADDWODQVU X1, X2, X3 // 43843374 + + // [X]VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}U instructions + VSUBWEVHBU V1, V2, V3 // 43043070 + VSUBWEVWHU V1, V2, V3 // 43843070 + VSUBWEVVWU V1, V2, V3 // 43043170 + VSUBWEVQVU V1, V2, V3 // 43843170 + VSUBWODHBU V1, V2, V3 // 43043470 + VSUBWODWHU V1, V2, V3 // 43843470 + VSUBWODVWU V1, V2, V3 // 43043570 + VSUBWODQVU V1, V2, V3 // 43843570 + XVSUBWEVHBU X1, X2, X3 // 43043074 + XVSUBWEVWHU X1, X2, X3 // 43843074 + XVSUBWEVVWU X1, X2, X3 // 43043174 + XVSUBWEVQVU X1, X2, X3 // 43843174 + XVSUBWODHBU X1, X2, X3 // 43043474 + XVSUBWODWHU X1, X2, X3 // 43843474 + XVSUBWODVWU X1, X2, X3 // 43043574 + XVSUBWODQVU X1, X2, X3 // 43843574 + + // [X]VMADD.{B/H/W/D}, [X]VMSUB.{B/H/W/D} instructions + VMADDB V1, V2, V3 // 4304a870 + VMADDH V1, V2, V3 // 4384a870 + VMADDW V1, V2, V3 // 4304a970 + VMADDV V1, V2, V3 // 4384a970 + VMSUBB V1, V2, V3 // 4304aa70 + VMSUBH V1, V2, V3 // 4384aa70 + VMSUBW V1, V2, V3 // 4304ab70 + VMSUBV V1, V2, V3 // 4384ab70 + XVMADDB X1, X2, X3 // 4304a874 + XVMADDH X1, X2, X3 // 4384a874 + XVMADDW X1, X2, X3 // 4304a974 + XVMADDV X1, X2, X3 // 4384a974 + XVMSUBB X1, X2, X3 // 4304aa74 + XVMSUBH X1, X2, X3 // 4384aa74 + XVMSUBW X1, X2, X3 // 4304ab74 + XVMSUBV X1, X2, X3 // 4384ab74 + + // [X]VMADDW{EV/OD}.{H.B/W.H/D.W/Q.D} instructions + VMADDWEVHB V1, V2, V3 // 4304ac70 + VMADDWEVWH V1, V2, V3 // 4384ac70 + VMADDWEVVW V1, V2, V3 // 4304ad70 + VMADDWEVQV V1, V2, V3 // 4384ad70 + VMADDWODHB V1, V2, V3 // 4304ae70 + VMADDWODWH V1, V2, V3 // 4384ae70 + VMADDWODVW V1, V2, V3 // 4304af70 + VMADDWODQV V1, V2, V3 // 4384af70 + XVMADDWEVHB X1, X2, X3 // 4304ac74 + XVMADDWEVWH X1, X2, X3 // 4384ac74 + XVMADDWEVVW X1, X2, X3 // 4304ad74 + XVMADDWEVQV X1, X2, X3 // 4384ad74 + XVMADDWODHB X1, X2, X3 // 4304ae74 + XVMADDWODWH X1, X2, X3 // 4384ae74 + XVMADDWODVW X1, X2, X3 // 4304af74 + XVMADDWODQV X1, X2, X3 // 4384af74 + + // [X]VMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}U instructions + VMADDWEVHBU V1, V2, V3 // 4304b470 + VMADDWEVWHU V1, V2, V3 // 4384b470 + VMADDWEVVWU V1, V2, V3 // 4304b570 + VMADDWEVQVU V1, V2, V3 // 4384b570 + VMADDWODHBU V1, V2, V3 // 4304b670 + VMADDWODWHU V1, V2, V3 // 4384b670 + VMADDWODVWU V1, V2, V3 // 4304b770 + VMADDWODQVU V1, V2, V3 // 4384b770 + XVMADDWEVHBU X1, X2, X3 // 4304b474 + XVMADDWEVWHU X1, X2, X3 // 4384b474 + XVMADDWEVVWU X1, X2, X3 // 4304b574 + XVMADDWEVQVU X1, X2, X3 // 4384b574 + XVMADDWODHBU X1, X2, X3 // 4304b674 + XVMADDWODWHU X1, X2, X3 // 4384b674 + XVMADDWODVWU X1, X2, X3 // 4304b774 + XVMADDWODQVU X1, X2, X3 // 4384b774 + + // [X]VMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D} instructions + VMADDWEVHBUB V1, V2, V3 // 4304bc70 + VMADDWEVWHUH V1, V2, V3 // 4384bc70 + VMADDWEVVWUW V1, V2, V3 // 4304bd70 + VMADDWEVQVUV V1, V2, V3 // 4384bd70 + VMADDWODHBUB V1, V2, V3 // 4304be70 + VMADDWODWHUH V1, V2, V3 // 4384be70 + VMADDWODVWUW V1, V2, V3 // 4304bf70 + VMADDWODQVUV V1, V2, V3 // 4384bf70 + XVMADDWEVHBUB X1, X2, X3 // 4304bc74 + XVMADDWEVWHUH X1, X2, X3 // 4384bc74 + XVMADDWEVVWUW X1, X2, X3 // 4304bd74 + XVMADDWEVQVUV X1, X2, X3 // 4384bd74 + XVMADDWODHBUB X1, X2, X3 // 4304be74 + XVMADDWODWHUH X1, X2, X3 // 4384be74 + XVMADDWODVWUW X1, X2, X3 // 4304bf74 + XVMADDWODQVUV X1, X2, X3 // 4384bf74 + // [X]VSHUF4I.{B/H/W/D} instructions VSHUF4IB $0, V2, V1 // 41009073 VSHUF4IB $16, V2, V1 // 41409073 @@ -1021,6 +1272,32 @@ lable2: XVSHUF4IV $8, X1, X2 // 22209c77 XVSHUF4IV $15, X1, X2 // 223c9c77 + // [X]VSHUF.{B/H/W/V} instructions + VSHUFH V1, V2, V3 // 43847a71 + VSHUFW V1, V2, V3 // 43047b71 + VSHUFV V1, V2, V3 // 43847b71 + XVSHUFH X1, X2, X3 // 43847a75 + XVSHUFW X1, X2, X3 // 43047b75 + XVSHUFV X1, X2, X3 // 43847b75 + VSHUFB V1, V2, V3, V4 // 6488500d + XVSHUFB X1, X2, X3, X4 // 6488600d + + // VPERMIW, XVPERMI{W,V,Q} instructions + VPERMIW $0x1B, V1, V2 // VPERMIW $27, V1, V2 // 226ce473 + XVPERMIW $0x2B, X1, X2 // XVPERMIW $43, X1, X2 // 22ace477 + XVPERMIV $0x3B, X1, X2 // XVPERMIV $59, X1, X2 // 22ece877 + XVPERMIQ $0x4B, X1, X2 // XVPERMIQ $75, X1, X2 // 222ced77 + + // A{,X}VEXTRINS.{B,H,W,V} instructions + VEXTRINSB $0x18, V1, V2 // VEXTRINSB $24, V1, V2 // 22608c73 + VEXTRINSH $0x27, V1, V2 // VEXTRINSH $39, V1, V2 // 229c8873 + VEXTRINSW $0x36, V1, V2 // VEXTRINSW $54, V1, V2 // 22d88473 + VEXTRINSV $0x45, V1, V2 // VEXTRINSV $69, V1, V2 // 22148173 + XVEXTRINSB $0x54, X1, X2 // XVEXTRINSB $84, X1, X2 // 22508d77 + XVEXTRINSH $0x63, X1, X2 // XVEXTRINSH $99, X1, X2 // 228c8977 + XVEXTRINSW $0x72, X1, X2 // XVEXTRINSW $114, X1, X2 // 22c88577 + XVEXTRINSV $0x81, X1, X2 // XVEXTRINSV $129, X1, X2 // 22048277 + // [X]VSETEQZ.V, [X]VSETNEZ.V VSETEQV V1, FCC0 // 20989c72 VSETNEV V1, FCC0 // 209c9c72 diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc2.s b/src/cmd/asm/internal/asm/testdata/loong64enc2.s index 91aed4e2c7007d..38f50d2bfc235f 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc2.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc2.s @@ -21,6 +21,10 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 ADD $4096, R4, R5 // 3e00001485781000 ADD $65536, R4 // 1e02001484781000 ADD $4096, R4 // 3e00001484781000 + ADDW $65536, R4, R5 // 1e02001485781000 + ADDW $4096, R4, R5 // 3e00001485781000 + ADDW $65536, R4 // 1e02001484781000 + ADDW $4096, R4 // 3e00001484781000 ADDV $65536, R4, R5 // 1e02001485f81000 ADDV $4096, R4, R5 // 3e00001485f81000 ADDV $65536, R4 // 1e02001484f81000 @@ -37,10 +41,6 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 SGTU $4096, R4, R5 // 3e00001485f81200 SGTU $65536, R4 // 1e02001484f81200 SGTU $4096, R4 // 3e00001484f81200 - ADDU $65536, R4, R5 // 1e02001485781000 - ADDU $4096, R4, R5 // 3e00001485781000 - ADDU $65536, R4 // 1e02001484781000 - ADDU $4096, R4 // 3e00001484781000 ADDVU $65536, R4, R5 // 1e02001485f81000 ADDVU $4096, R4, R5 // 3e00001485f81000 ADDVU $65536, R4 // 1e02001484f81000 diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc3.s b/src/cmd/asm/internal/asm/testdata/loong64enc3.s index 2d83bd719a584e..8b5f96bf4a224a 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc3.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc3.s @@ -11,12 +11,16 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 MOVV $4096(R4), R5 // 3e000014de03800385f81000 ADD $74565, R4 // 5e020014de178d0384781000 ADD $4097, R4 // 3e000014de07800384781000 + ADDW $74565, R4 // 5e020014de178d0384781000 + ADDW $4097, R4 // 3e000014de07800384781000 ADDV $74565, R4 // 5e020014de178d0384f81000 ADDV $4097, R4 // 3e000014de07800384f81000 AND $74565, R4 // 5e020014de178d0384f81400 AND $4097, R4 // 3e000014de07800384f81400 ADD $74565, R4, R5 // 5e020014de178d0385781000 ADD $4097, R4, R5 // 3e000014de07800385781000 + ADDW $74565, R4, R5 // 5e020014de178d0385781000 + ADDW $4097, R4, R5 // 3e000014de07800385781000 ADDV $74565, R4, R5 // 5e020014de178d0385f81000 ADDV $4097, R4, R5 // 3e000014de07800385f81000 AND $74565, R4, R5 // 5e020014de178d0385f81400 @@ -42,8 +46,10 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 MOVB R4, 4096(R5) // 3e000014de971000c4030029 MOVBU R4, 65536(R5) // 1e020014de971000c4030029 MOVBU R4, 4096(R5) // 3e000014de971000c4030029 - SC R4, 65536(R5) // 1e020014de971000c4030021 - SC R4, 4096(R5) // 3e000014de971000c4030021 + SC R4, 65536(R5) // 1e040010de971000c4030021 + SCV R4, 65536(R5) // 1e040010de971000c4030023 + LL 65536(R5), R4 // 1e040010de971000c4030020 + LLV 65536(R5), R4 // 1e040010de971000c4030022 MOVW y+65540(FP), R4 // 1e020014de8f1000c4338028 MOVWU y+65540(FP), R4 // 1e020014de8f1000c433802a MOVV y+65540(FP), R4 // 1e020014de8f1000c433c028 @@ -105,10 +111,6 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 SGTU $74565, R4, R5 // 5e020014de178d0385f81200 SGTU $4097, R4 // 3e000014de07800384f81200 SGTU $4097, R4, R5 // 3e000014de07800385f81200 - ADDU $74565, R4 // 5e020014de178d0384781000 - ADDU $74565, R4, R5 // 5e020014de178d0385781000 - ADDU $4097, R4 // 3e000014de07800384781000 - ADDU $4097, R4, R5 // 3e000014de07800385781000 ADDVU $4097, R4 // 3e000014de07800384f81000 ADDVU $4097, R4, R5 // 3e000014de07800385f81000 ADDVU $74565, R4 // 5e020014de178d0384f81000 @@ -122,6 +124,21 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 XOR $4097, R4 // 3e000014de07800384f81500 XOR $4097, R4, R5 // 3e000014de07800385f81500 + MOVWP R5, -32768(R4) // 1efcff13de931000c5038025 + MOVWP R5, 32768(R4) // 1e000010de931000c5038025 + MOVWP R5, 65536(R4) // 1e040010de931000c5030025 + MOVWP R5, 1048576(R4) // 1e400010de931000c5030025 + MOVVP R5, -32768(R4) // 1efcff13de931000c5038027 + MOVVP R5, 65536(R4) // 1e040010de931000c5030027 + MOVVP R5, 1048576(R4) // 1e400010de931000c5030027 + MOVWP -32768(R5), R4 // 1efcff13de971000c4038024 + MOVWP 2229248(R5), R4 // 1e880010de971000c4030424 + MOVWP -2145518592(R5), R4 // 1e740012de971000c403fc24 + MOVVP -32768(R5), R4 // 1efcff13de971000c4038026 + MOVVP 2229248(R5), R4 // 1e880010de971000c4030426 + MOVVP -2145518592(R5), R4 // 1e740012de971000c403fc26 + + // MOVV C_DCON32_12S, r MOVV $0x27312345fffff800, R4 // MOVV $2824077224892692480, R4 // 0400a002a468241684cc0903 MOVV $0xf7312345fffff800, R4 // MOVV $-634687288927848448, R4 // 0400a002a468241684cc3d03 diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc6.s b/src/cmd/asm/internal/asm/testdata/loong64enc6.s new file mode 100644 index 00000000000000..bd19ea76012a5a --- /dev/null +++ b/src/cmd/asm/internal/asm/testdata/loong64enc6.s @@ -0,0 +1,12 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +#include "../../../../../runtime/textflag.h" + +TEXT asmtest(SB),DUPOK|NOSPLIT,$0 + // MOVWP LOREG_64(Rx), Ry + MOVWP 81985529216486896(R4), R5 // 9e571315dec3b703feac6816de4b000384f8100085000025 + MOVWP -81985529216486896(R4), R5 // 7ea8ec14de4388031e539717deb73f0384f8100085000025 + MOVWP R4, 81985529216486896(R5) // 9e571315dec3b703feac6816de4b0003a5f81000a4000025 + MOVWP R4, -81985529216486896(R5) // 7ea8ec14de4388031e539717deb73f03a5f81000a4000025 diff --git a/src/cmd/asm/internal/asm/testdata/loong64error.s b/src/cmd/asm/internal/asm/testdata/loong64error.s index 2dcd34bf61c676..25ef3a85a46738 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64error.s +++ b/src/cmd/asm/internal/asm/testdata/loong64error.s @@ -7,3 +7,9 @@ TEXT errors(SB),$0 XVSHUF4IV $16, X1, X2 // ERROR "operand out of range 0 to 15" ADDV16 $1, R4, R5 // ERROR "the constant must be a multiple of 65536." ADDV16 $65535, R4, R5 // ERROR "the constant must be a multiple of 65536." + SC R4, 1(R5) // ERROR "offset must be a multiple of 4." + SCW R4, 1(R5) // ERROR "offset must be a multiple of 4." + SCV R4, 1(R5) // ERROR "offset must be a multiple of 4." + LL 1(R5), R4 // ERROR "offset must be a multiple of 4." + LLW 1(R5), R4 // ERROR "offset must be a multiple of 4." + LLV 1(R5), R4 // ERROR "offset must be a multiple of 4." diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s index 702b82223b36af..752743892f6eaa 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64.s @@ -11,7 +11,6 @@ start: // // 2.4: Integer Computational Instructions - ADDI $2047, X5 // 9382f27f ADDI $-2048, X5 // 93820280 ADDI $2048, X5 // 9382024093820240 @@ -140,6 +139,10 @@ start: // 2.7: Memory Ordering Instructions FENCE // 0f00f00f + FENCE W, W // 0f001001 + FENCE I, O // 0f004008 + FENCE IORW, IORW // 0f00f00f + FENCE.TSO // 0f003083 // 4.2: Integer Computational Instructions (RV64I) ADDIW $1, X5, X6 // 1b831200 @@ -172,7 +175,17 @@ start: SD X5, (X6) // 23305300 SD X5, 4(X6) // 23325300 - // 7.1: CSR Instructions + // 6.1: CSR Instructions + CSRC X5, VSTART // 73b08200 + CSRC $2, VSTART // 73708100 + CSRCI $2, VSTART // 73708100 + CSRR CYCLE, X5 // f32200c0 + CSRR VCSR, X5 // f322f000 + CSRR VL, X5 // f32200c2 + CSRR VLENB, X5 // f32220c2 + CSRR VSTART, X5 // f3228000 + CSRR VXSAT, X5 // f3229000 + CSRR VXRM, X5 // f322a000 CSRRC X0, CYCLE, X5 // f33200c0 CSRRC X0, CYCLE, X0 // 733000c0 CSRRC X10, CYCLE, X5 // f33205c0 @@ -189,26 +202,35 @@ start: CSRRW X10, CYCLE, X5 // f31205c0 CSRRW $2, TIME, X5 // f35211c0 CSRRWI $2, TIME, X5 // f35211c0 + CSRS X10, VSTART // 73208500 + CSRS $2, VSTART // 73608100 + CSRSI $2, VSTART // 73608100 + CSRW X10, VSTART // 73108500 + CSRW $2, VSTART // 73508100 + CSRWI $2, VSTART // 73508100 // 8.1: Base Counters and Timers (Zicntr) RDCYCLE X5 // f32200c0 RDTIME X5 // f32210c0 RDINSTRET X5 // f32220c0 - // 12.3: Integer Conditional Operations (Zicond) + // 9: Zihintpause Extension for Pause Hint + PAUSE // 0f000001 + + // 11.1: Integer Conditional Operations (Zicond) CZEROEQZ X5, X6, X7 // b353530e CZEROEQZ X5, X7 // b3d3530e CZERONEZ X5, X6, X7 // b373530e CZERONEZ X5, X7 // b3f3530e - // 13.1: Multiplication Operations + // 12.1: Multiplication Operations MUL X5, X6, X7 // b3035302 MULH X5, X6, X7 // b3135302 MULHU X5, X6, X7 // b3335302 MULHSU X5, X6, X7 // b3235302 MULW X5, X6, X7 // bb035302 - // 13.2: Division Operations + // 12.2: Division Operations DIV X5, X6, X7 // b3435302 DIVU X5, X6, X7 // b3535302 REM X5, X6, X7 // b3635302 @@ -218,13 +240,13 @@ start: REMW X5, X6, X7 // bb635302 REMUW X5, X6, X7 // bb735302 - // 14.2: Load-Reserved/Store-Conditional (Zalrsc) + // 13.2: Load-Reserved/Store-Conditional (Zalrsc) LRW (X5), X6 // 2fa30214 LRD (X5), X6 // 2fb30214 SCW X5, (X6), X7 // af23531a SCD X5, (X6), X7 // af33531a - // 14.4: Atomic Memory Operations (Zaamo) + // 13.4: Atomic Memory Operations (Zaamo) AMOSWAPW X5, (X6), X7 // af23530e AMOSWAPD X5, (X6), X7 // af33530e AMOADDW X5, (X6), X7 // af235306 @@ -244,13 +266,13 @@ start: AMOMINUW X5, (X6), X7 // af2353c6 AMOMINUD X5, (X6), X7 // af3353c6 - // 20.5: Single-Precision Load and Store Instructions + // 21.5: Single-Precision Load and Store Instructions FLW (X5), F0 // 07a00200 FLW 4(X5), F0 // 07a04200 FSW F0, (X5) // 27a00200 FSW F0, 4(X5) // 27a20200 - // 20.6: Single-Precision Floating-Point Computational Instructions + // 21.6: Single-Precision Floating-Point Computational Instructions FADDS F1, F0, F2 // 53011000 FSUBS F1, F0, F2 // 53011008 FMULS F1, F0, F2 // 53011010 @@ -259,7 +281,7 @@ start: FMAXS F1, F0, F2 // 53111028 FSQRTS F0, F1 // d3000058 - // 20.7: Single-Precision Floating-Point Conversion and Move Instructions + // 21.7: Single-Precision Floating-Point Conversion and Move Instructions FCVTWS F0, X5 // d31200c0 FCVTWS.RNE F0, X5 // d30200c0 FCVTWS.RTZ F0, X5 // d31200c0 @@ -300,21 +322,21 @@ start: FNMSUBS F1, F2, F3, F4 // 4b822018 FNMADDS F1, F2, F3, F4 // 4f822018 - // 20.8: Single-Precision Floating-Point Compare Instructions + // 21.8: Single-Precision Floating-Point Compare Instructions FEQS F0, F1, X7 // d3a300a0 FLTS F0, F1, X7 // d39300a0 FLES F0, F1, X7 // d38300a0 - // 20.9: Single-Precision Floating-Point Classify Instruction + // 21.9: Single-Precision Floating-Point Classify Instruction FCLASSS F0, X5 // d31200e0 - // 21.3: Double-Precision Load and Store Instructions + // 22.3: Double-Precision Load and Store Instructions FLD (X5), F0 // 07b00200 FLD 4(X5), F0 // 07b04200 FSD F0, (X5) // 27b00200 FSD F0, 4(X5) // 27b20200 - // 21.4: Double-Precision Floating-Point Computational Instructions + // 22.4: Double-Precision Floating-Point Computational Instructions FADDD F1, F0, F2 // 53011002 FSUBD F1, F0, F2 // 5301100a FMULD F1, F0, F2 // 53011012 @@ -323,7 +345,7 @@ start: FMAXD F1, F0, F2 // 5311102a FSQRTD F0, F1 // d300005a - // 21.5: Double-Precision Floating-Point Conversion and Move Instructions + // 22.5: Double-Precision Floating-Point Conversion and Move Instructions FCVTWD F0, X5 // d31200c2 FCVTWD.RNE F0, X5 // d30200c2 FCVTWD.RTZ F0, X5 // d31200c2 @@ -364,15 +386,85 @@ start: FNMSUBD F1, F2, F3, F4 // 4b82201a FNMADDD F1, F2, F3, F4 // 4f82201a - // 21.6: Double-Precision Floating-Point Compare Instructions + // 22.6: Double-Precision Floating-Point Compare Instructions FEQD F0, F1, X7 // d3a300a2 FLTD F0, F1, X7 // d39300a2 FLED F0, F1, X7 // d38300a2 - // 21.7: Double-Precision Floating-Point Classify Instruction + // 22.7: Double-Precision Floating-Point Classify Instruction FCLASSD F0, X5 // d31200e2 - // 28.4.1: Address Generation Instructions (Zba) + // + // "C" Extension for Compressed Instructions, Version 2.0 + // + + // 28.3.1: Compressed Stack-Pointer-Based Loads and Stores + CLWSP 20(SP), X10 // 5245 + CLDSP 24(SP), X10 // 6265 + CFLDSP 32(SP), F10 // 0235 + CSWSP X10, 20(SP) // 2aca + CSDSP X10, 24(SP) // 2aec + CFSDSP F10, 32(SP) // 2ab0 + + // 28.3.2: Compressed Register-Based Loads and Stores + CLW 20(X10), X11 // 4c49 + CLD 24(X10), X11 // 0c6d + CFLD 32(X10), F11 // 0c31 + CSW X11, 20(X10) // 4cc9 + CSD X11, 24(X10) // 0ced + CFSD F11, 32(X10) // 0cb1 + + // 28.4: Compressed Control Transfer Instructions + CJ 1(PC) // 09a0 + CJR X5 // 8282 + CJALR X5 // 8292 + CBEQZ X10, 1(PC) // 09c1 + CBNEZ X10, 1(PC) // 09e1 + + // 28.5.1: Compressed Integer Constant-Generation Instructions + CLI $-32, X5 // 8152 + CLI $31, X5 // fd42 + CLUI $-32, X5 // 8172 + CLUI $31, X5 // fd62 + + // 28.5.2: Compressed Integer Register-Immediate Operations + CADD $-32, X5 // 8112 + CADD $31, X5 // fd02 + CADDI $-32, X5 // 8112 + CADDI $31, X5 // fd02 + CADDW $-32, X5 // 8132 + CADDW $31, X5 // fd22 + CADDIW $-32, X5 // 8132 + CADDIW $31, X5 // fd22 + CADDI16SP $-512, SP // 0171 + CADDI16SP $496, SP // 7d61 + CADDI4SPN $4, SP, X10 // 4800 + CADDI4SPN $1020, SP, X10 // e81f + CSLLI $63, X5 // fe12 + CSRLI $63, X10 // 7d91 + CSRAI $63, X10 // 7d95 + CAND $-32, X10 // 0199 + CAND $31, X10 // 7d89 + CANDI $-32, X10 // 0199 + CANDI $31, X10 // 7d89 + + // 28.5.3: Compressed Integer Register-Register Operations + CMV X6, X5 // 9a82 + CADD X9, X8 // 2694 + CAND X9, X8 // 658c + COR X9, X8 // 458c + CXOR X9, X8 // 258c + CSUB X9, X8 // 058c + CADDW X9, X8 // 259c + CSUBW X9, X8 // 059c + + // 28.5.5: Compressed NOP Instruction + CNOP // 0100 + + // 28.5.6: Compressed Breakpoint Instruction + CEBREAK // 0290 + + // 30.2: Address Generation Instructions (Zba) ADDUW X10, X11, X12 // 3b86a508 ADDUW X10, X11 // bb85a508 SH1ADD X11, X12, X13 // b326b620 @@ -396,7 +488,7 @@ start: // "B" Extension for Bit Manipulation, Version 1.0.0 // - // 28.4.2: Basic Bit Manipulation (Zbb) + // 30.3: Basic Bit Manipulation (Zbb) ANDN X19, X20, X21 // b37a3a41 or 93caf9ffb37a5a01 ANDN X19, X20 // 337a3a41 or 93cff9ff337afa01 CLZ X20, X21 // 931a0a60 @@ -420,8 +512,6 @@ start: XNOR X18, X19, X20 // 33ca2941 or 33ca2901134afaff XNOR X18, X19 // b3c92941 or b3c9290193c9f9ff ZEXTH X19, X20 // 3bca0908 - - // 28.4.2: Bitwise Rotation (Zbb) ROL X8, X9, X10 // 33958460 or b30f8040b3dff4013395840033e5af00 ROL X8, X9 // b3948460 or b30f8040b3dff401b3948400b3e49f00 ROLW X9, X10, X11 // bb159560 or b30f9040bb5ff501bb159500b3e5bf00 @@ -439,7 +529,15 @@ start: ORCB X5, X6 // 13d37228 REV8 X7, X8 // 13d4836b - // 28.4.4: Single-bit Instructions (Zbs) + // 30.4: Carry-less multiplication (Zbc) + CLMUL X5, X6, X7 // b313530a + CLMUL X5, X6 // 3313530a + CLMULH X5, X6, X7 // b333530a + CLMULH X5, X6 // 3333530a + CLMULR X5, X6, X7 // b323530a + CLMULR X5, X6 // 3323530a + + // 30.5: Single-bit Instructions (Zbs) BCLR X23, X24, X25 // b31c7c49 BCLR $63, X24 // 131cfc4b BCLRI $1, X25, X26 // 139d1c48 @@ -497,7 +595,7 @@ start: VLMV (X10), V3 // 8701b502 VSMV V3, (X10) // a701b502 - // 31.7.5: Vector Strided Instructions + // 31.7.5: Vector Constant-Stride Instructions VLSE8V (X10), X11, V3 // 8701b50a VLSE8V (X10), X11, V0, V3 // 8701b508 VLSE16V (X10), X11, V3 // 8751b50a @@ -549,7 +647,7 @@ start: VSOXEI64V V3, V2, (X10) // a771250e VSOXEI64V V3, V2, V0, (X10) // a771250c - // 31.7.7: Unit-stride Fault-Only-First Loads + // 31.7.7: Vector Unit-stride Fault-Only-First Loads VLE8FFV (X10), V8 // 07040503 VLE16FFV (X10), V8 // 07540503 VLE32FFV (X10), V8 // 07640503 @@ -559,8 +657,6 @@ start: VLE32FFV (X10), V0, V8 // 07640501 VLE64FFV (X10), V0, V8 // 07740501 - // 31.7.8: Vector Load/Store Segment Instructions - // 31.7.8.1: Vector Unit-Stride Segment Loads and Stores VLSEG2E8V (X10), V8 // 07040522 VLSEG2E16V (X10), V8 // 07540522 @@ -751,7 +847,7 @@ start: VLSEG8E32FFV (X10), V0, V8 // 076405e1 VLSEG8E64FFV (X10), V0, V8 // 077405e1 - // 31.7.8.2: Vector Strided Segment Loads and Stores + // 31.7.8.2: Vector Constant-Stride Segment Loads and Stores VLSSEG2E8V (X10), X11, V8 // 0704b52a VLSSEG2E16V (X10), X11, V8 // 0754b52a VLSSEG2E32V (X10), X11, V8 // 0764b52a @@ -879,7 +975,6 @@ start: VSSSEG8E64V V24, X11, V0, (X10) // 277cb5e8 // 31.7.8.3: Vector Indexed Segment Loads and Stores - VLUXSEG2EI8V (X10), V4, V8 // 07044526 VLUXSEG2EI16V (X10), V4, V8 // 07544526 VLUXSEG2EI32V (X10), V4, V8 // 07644526 @@ -1895,6 +1990,50 @@ start: VMV4RV V8, V4 // 57b2819e VMV8RV V8, V0 // 57b0839e + // 33.2.1: Vector Basic Bit-manipulation (Zvbb) + VANDNVV V1, V2, V3 // d7812006 + VANDNVV V1, V2, V0, V3 // d7812004 + VANDNVX X10, V2, V3 // d7412506 + VANDNVX X10, V2, V0, V3 // d7412504 + VBREVV V2, V3 // d721254a + VBREVV V2, V0, V3 // d7212548 + VBREV8V V2, V3 // d721244a + VBREV8V V2, V0, V3 // d7212448 + VREV8V V2, V3 // d7a1244a + VREV8V V2, V0, V3 // d7a12448 + VCLZV V2, V3 // d721264a + VCLZV V2, V0, V3 // d7212648 + VCTZV V2, V3 // d7a1264a + VCTZV V2, V0, V3 // d7a12648 + VCPOPV V2, V3 // d721274a + VCPOPV V2, V0, V3 // d7212748 + VROLVV V1, V2, V3 // d7812056 + VROLVV V1, V2, V0, V3 // d7812054 + VROLVX X10, V2, V3 // d7412556 + VROLVX X10, V2, V0, V3 // d7412554 + VRORVV V1, V2, V3 // d7812052 + VRORVV V1, V2, V0, V3 // d7812050 + VRORVX X10, V2, V3 // d7412552 + VRORVX X10, V2, V0, V3 // d7412550 + VRORVI $16, V2, V3 // d7312852 + VRORVI $16, V2, V0, V3 // d7312850 + VWSLLVV V1, V2, V3 // d78120d6 + VWSLLVV V1, V2, V0, V3 // d78120d4 + VWSLLVX X10, V2, V3 // d74125d6 + VWSLLVX X10, V2, V0, V3 // d74125d4 + VWSLLVI $16, V2, V3 // d73128d6 + VWSLLVI $16, V2, V0, V3 // d73128d4 + + // 33.2.2: Vector Carryless Multiplication (Zvbc) + VCLMULVV V1, V2, V3 // d7a12032 + VCLMULVV V1, V2, V0, V3 // d7a12030 + VCLMULVX X10, V2, V3 // d7612532 + VCLMULVX X10, V2, V0, V3 // d7612530 + VCLMULHVV V1, V2, V3 // d7a12036 + VCLMULHVV V1, V2, V0, V3 // d7a12034 + VCLMULHVX X10, V2, V3 // d7612536 + VCLMULHVX X10, V2, V0, V3 // d7612534 + // // Privileged ISA // @@ -1923,9 +2062,12 @@ start: // Converted to load and shift(s) MOV $0xffffffff, X5 // MOV $4294967295, X5 // 9302f0ff93d20202 + MOV $0x80000001, X5 // MOV $2147483649, X5 // b70200809b8212009392020293d20202 or b70200809b821200bb820208 MOV $0x100000000, X5 // MOV $4294967296, X5 // 9302100093920202 MOV $0xfffffffffffda, X5 // MOV $4503599627370458, X5 // 9302d0fe9392d20093d2c200 MOV $0xffffffffffffe, X5 // MOV $4503599627370494, X5 // 9302f0ff9392d20093d2c200 + MOV $0x0800000010000000, X5 // MOV $576460752571858944, X5 // b70200809b8212009392020293d24200 + MOV $0x0abcdabcd0000000, X5 // MOV $773733740479250432, X5 // b7b2cdab9b82d2bc9392020293d24200 MOV $0x7fffffff00000000, X5 // MOV $9223372032559808512, X5 // b70200809b82f2ff93920202 MOV $0x8000000100000000, X5 // MOV $-9223372032559808512, X5 // b70200809b82120093920202 MOV $0xffffffff00000000, X5 // MOV $-4294967296, X5 // 9302f0ff93920202 @@ -1933,11 +2075,8 @@ start: MOV $0x7fffffffffffffff, X5 // MOV $9223372036854775807, X5 // 9302f0ff93d21200 // Converted to load of symbol (AUIPC + LD) - MOV $0x80000001, X5 // MOV $2147483649, X5 // 9702000083b20200 MOV $0x100000001, X5 // MOV $4294967297, X5 // 9702000083b20200 - MOV $0x0800000010000000, X5 // MOV $576460752571858944, X5 // 9702000083b20200 MOV $0x8000000010000000, X5 // MOV $-9223372036586340352, X5 // 9702000083b20200 - MOV $0x0abcdabcd0000000, X5 // MOV $773733740479250432, X5 // 9702000083b20200 MOV $0x8abcdabcd0000000, X5 // MOV $-8449638296375525376, X5 // 9702000083b20200 MOV $0xfff0000000ffffff, X5 // MOV $-4503599610593281, X5 // 9702000083b20200 diff --git a/src/cmd/asm/internal/asm/testdata/riscv64error.s b/src/cmd/asm/internal/asm/testdata/riscv64error.s index 3c09770d2a2dcd..fd5e4acdf37c50 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64error.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64error.s @@ -3,9 +3,14 @@ // license that can be found in the LICENSE file. TEXT errors(SB),$0 + CSRC X5, TU // ERROR "unknown CSR" + CSRC (X5), CYCLE // ERROR "integer register or immediate expected for 1st operand" + CSRC $-1, TIME // ERROR "immediate out of range 0 to 31" + CSRR TU, X5 // ERROR "unknown CSR" + CSRR CYCLE, (X5) // ERROR "needs an integer register output" CSRRC (X10), CYCLE, X5 // ERROR "integer register or immediate expected for 1st operand" CSRRC X0, TU, X5 // ERROR "unknown CSR" - CSRRC X0, CYCLE // ERROR "missing CSR name" + CSRRC X0, X5 // ERROR "missing CSR name" CSRRC X0, CYCLE, (X10) // ERROR "needs an integer register output" CSRRC $-1, TIME, X15 // ERROR "immediate out of range 0 to 31" CSRRCI $32, TIME, X15 // ERROR "immediate out of range 0 to 31" @@ -13,17 +18,25 @@ TEXT errors(SB),$0 CSRRS (X10), CYCLE, X5 // ERROR "integer register or immediate expected for 1st operand" CSRRS X0, CYCLE, (X10) // ERROR "needs an integer register output" CSRRS X0, TU, X5 // ERROR "unknown CSR" - CSRRS X0, CYCLE // ERROR "missing CSR name" + CSRRS X0, X5 // ERROR "missing CSR name" CSRRS $-1, TIME, X15 // ERROR "immediate out of range 0 to 31" CSRRSI $32, TIME, X15 // ERROR "immediate out of range 0 to 31" CSRRSI $1, TIME, (X15) // ERROR "needs an integer register output" CSRRW (X10), CYCLE, X5 // ERROR "integer register or immediate expected for 1st operand" CSRRW X0, TU, X5 // ERROR "unknown CSR" - CSRRW X0, CYCLE // ERROR "missing CSR name" + CSRRW X0, X5 // ERROR "missing CSR name" CSRRW X0, CYCLE, (X5) // ERROR "needs an integer register output" CSRRW $-1, TIME, X15 // ERROR "immediate out of range 0 to 31" CSRRWI $32, TIME, X15 // ERROR "immediate out of range 0 to 31" CSRRWI $1, TIME, (X15) // ERROR "needs an integer register output" + CSRW X5, TU // ERROR "unknown CSR" + CSRW $-1, TIME // ERROR "immediate out of range 0 to 31" + CSRWI $32, TIME // ERROR "immediate out of range 0 to 31" + CSRS (X5), CYCLE // ERROR "integer register or immediate expected for 1st operand" + CSRS X5, TU // ERROR "unknown CSR" + CSRS $-1, TIME // ERROR "immediate out of range 0 to 31" + CSRSI $32, TIME // ERROR "immediate out of range 0 to 31" + CSRW (X5), CYCLE // ERROR "integer register or immediate expected for 1st operand" MOV $errors(SB), (X5) // ERROR "address load must target register" MOV $8(SP), (X5) // ERROR "address load must target register" MOVB $8(SP), X5 // ERROR "unsupported address load" @@ -68,6 +81,13 @@ TEXT errors(SB),$0 SD X5, 4294967296(X6) // ERROR "constant 4294967296 too large" FNES F1, (X5) // ERROR "needs an integer register output" + // Memory Ordering Instructions + FENCE X1, R // ERROR "invalid FENCE predecessor operand" + FENCE R, X2 // ERROR "invalid FENCE successor operand" + FENCE $1, R // ERROR "invalid FENCE predecessor operand" + FENCE R, $2 // ERROR "invalid FENCE successor operand" + FENCE.TSO R, R // ERROR "FENCE.TSO must not have operands" + // // "V" Standard Extension for Vector Operations, Version 1.0 // @@ -416,5 +436,25 @@ TEXT errors(SB),$0 VRGATHEREI16VV V1, V2, V4, V3 // ERROR "invalid vector mask register" VRGATHERVX X10, V2, V4, V3 // ERROR "invalid vector mask register" VRGATHERVI $16, V2, V4, V3 // ERROR "invalid vector mask register" + VANDNVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VANDNVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VBREVV V2, V3, V4 // ERROR "invalid vector mask register" + VBREV8V V2, V3, V4 // ERROR "invalid vector mask register" + VREV8V V2, V3, V4 // ERROR "invalid vector mask register" + VCLZV V2, V3, V4 // ERROR "invalid vector mask register" + VCTZV V2, V3, V4 // ERROR "invalid vector mask register" + VCPOPV V2, V3, V4 // ERROR "invalid vector mask register" + VROLVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VROLVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VRORVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VRORVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VRORVI $16, V2, V4, V3 // ERROR "invalid vector mask register" + VWSLLVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWSLLVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWSLLVI $16, V2, V4, V3 // ERROR "invalid vector mask register" + VCLMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VCLMULVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VCLMULHVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VCLMULHVX X10, V2, V4, V3 // ERROR "invalid vector mask register" RET diff --git a/src/cmd/asm/internal/asm/testdata/riscv64validation.s b/src/cmd/asm/internal/asm/testdata/riscv64validation.s index c8ae4c92114bbc..4e4e16286b6355 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64validation.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64validation.s @@ -15,6 +15,144 @@ TEXT validation(SB),$0 WORD $-1 // ERROR "must be in range [0x0, 0xffffffff]" WORD $0x100000000 // ERROR "must be in range [0x0, 0xffffffff]" + // + // "C" Extension for Compressed Instructions, Version 2.0 + // + CLWSP 20(X5), X10 // ERROR "rs2 must be SP/X2" + CLWSP 20(SP), X0 // ERROR "cannot use register X0" + CLWSP 20(SP), F10 // ERROR "expected integer register in rd position" + CLWSP 22(SP), X10 // ERROR "must be a multiple of 4" + CLDSP 24(X5), X10 // ERROR "rs2 must be SP/X2" + CLDSP 24(SP), X0 // ERROR "cannot use register X0" + CLDSP 24(SP), F10 // ERROR "expected integer register in rd position" + CLDSP 28(SP), X10 // ERROR "must be a multiple of 8" + CFLDSP 32(X5), F10 // ERROR "rs2 must be SP/X2" + CFLDSP 32(SP), X10 // ERROR "expected float register in rd position" + CFLDSP 36(SP), F10 // ERROR "must be a multiple of 8" + CSWSP X10, 20(X5) // ERROR "rd must be SP/X2" + CSWSP F10, 20(SP) // ERROR "expected integer register in rs2 position" + CSWSP X10, 22(SP) // ERROR "must be a multiple of 4" + CSDSP X10, 24(X5) // ERROR "rd must be SP/X2" + CSDSP F10, 24(SP) // ERROR "expected integer register in rs2 position" + CSDSP X10, 28(SP) // ERROR "must be a multiple of 8" + CFSDSP F10, 32(X5) // ERROR "rd must be SP/X2" + CFSDSP X10, 32(SP) // ERROR "expected float register in rs2 position" + CFSDSP F10, 36(SP) // ERROR "must be a multiple of 8" + CLW 20(X10), F11 // ERROR "expected integer prime register in rd position" + CLW 20(X5), X11 // ERROR "expected integer prime register in rs1 position" + CLW 20(X10), X5 // ERROR "expected integer prime register in rd position" + CLW -1(X10), X11 // ERROR "must be in range [0, 127]" + CLW 22(X10), X11 // ERROR "must be a multiple of 4" + CLW 128(X10), X11 // ERROR "must be in range [0, 127]" + CLD 24(X10), F11 // ERROR "expected integer prime register in rd position" + CLD 24(X5), X11 // ERROR "expected integer prime register in rs1 position" + CLD -1(X10), X11 // ERROR "must be in range [0, 255]" + CLD 30(X10), X11 // ERROR "must be a multiple of 8" + CLD 256(X10), X11 // ERROR "must be in range [0, 255]" + CFLD 32(X10), X11 // ERROR "expected float prime register in rd position" + CFLD 32(X5), F11 // ERROR "expected integer prime register in rs1 position" + CFLD -1(X10), F11 // ERROR "must be in range [0, 255]" + CFLD 34(X10), F11 // ERROR "must be a multiple of 8" + CFLD 256(X10), F11 // ERROR "must be in range [0, 255]" + CSW F11, 20(X10) // ERROR "expected integer prime register in rs2 position" + CSW X11, -1(X10) // ERROR "must be in range [0, 127]" + CSW X11, 22(X10) // ERROR "must be a multiple of 4" + CSW X11, 128(X10) // ERROR "must be in range [0, 127]" + CSD F11, 24(X10) // ERROR "expected integer prime register in rs2 position" + CSD X11, -1(X10) // ERROR "must be in range [0, 255]" + CSD X11, 28(X10) // ERROR "must be a multiple of 8" + CSD X11, 256(X10) // ERROR "must be in range [0, 255]" + CFSD X11, 32(X10) // ERROR "expected float prime register in rs2 position" + CFSD F11, -1(X10) // ERROR "must be in range [0, 255]" + CFSD F11, 36(X10) // ERROR "must be a multiple of 8" + CFSD F11, 256(X10) // ERROR "must be in range [0, 255]" + CJR X0 // ERROR "cannot use register X0 in rs1" + CJR X10, X11 // ERROR "expected no register in rs2" + CJALR X0 // ERROR "cannot use register X0 in rs1" + CJALR X10, X11 // ERROR "expected no register in rd" + CBEQZ X5, 1(PC) // ERROR "expected integer prime register in rs1" + CBNEZ X5, 1(PC) // ERROR "expected integer prime register in rs1" + CLI $3, X0 // ERROR "cannot use register X0 in rd" + CLI $-33, X5 // ERROR "must be in range [-32, 31]" + CLI $32, X5 // ERROR "must be in range [-32, 31]" + CLUI $0, X5 // ERROR "immediate cannot be zero" + CLUI $3, X0 // ERROR "cannot use register X0 in rd" + CLUI $3, X2 // ERROR "cannot use register SP/X2 in rd" + CLUI $-33, X5 // ERROR "must be in range [-32, 31]" + CLUI $32, X5 // ERROR "must be in range [-32, 31]" + CADD $31, X5, X6 // ERROR "rd must be the same as rs1" + CADD $-33, X5 // ERROR "must be in range [-32, 31]" + CADD $32, X5 // ERROR "must be in range [-32, 31]" + CADDI $0, X5 // ERROR "immediate cannot be zero" + CADDI $31, X5, X6 // ERROR "rd must be the same as rs1" + CADDI $-33, X5 // ERROR "must be in range [-32, 31]" + CADDI $32, X5 // ERROR "must be in range [-32, 31]" + CADDW $-33, X5 // ERROR "must be in range [-32, 31]" + CADDW $32, X5 // ERROR "must be in range [-32, 31]" + CADDIW $-33, X5 // ERROR "must be in range [-32, 31]" + CADDIW $32, X5 // ERROR "must be in range [-32, 31]" + CADDI16SP $0, SP // ERROR "immediate cannot be zero" + CADDI16SP $16, X5 // ERROR "rd must be SP/X2" + CADDI16SP $-513, SP // ERROR "must be in range [-512, 511]" + CADDI16SP $20, SP // ERROR "must be a multiple of 16" + CADDI16SP $512, SP // ERROR "must be in range [-512, 511]" + CADDI4SPN $4, SP, X5 // ERROR "expected integer prime register in rd" + CADDI4SPN $4, X5, X10 // ERROR "SP/X2 must be in rs1" + CADDI4SPN $-1, SP, X10 // ERROR "must be in range [0, 1023]" + CADDI4SPN $0, SP, X10 // ERROR "immediate cannot be zero" + CADDI4SPN $6, SP, X10 // ERROR "must be a multiple of 4" + CADDI4SPN $1024, SP, X10 // ERROR "must be in range [0, 1023]" + CSLLI $63, X5, X6 // ERROR "rd must be the same as rs1" + CSLLI $-1, X5 // ERROR "must be in range [0, 63]" + CSLLI $0, X5 // ERROR "immediate cannot be zero" + CSLLI $64, X5 // ERROR "must be in range [0, 63]" + CSRLI $63, X10, X11 // ERROR "rd must be the same as rs1" + CSRLI $63, X5 // ERROR "expected integer prime register in rd" + CSRLI $-1, X10 // ERROR "must be in range [0, 63]" + CSRLI $0, X10 // ERROR "immediate cannot be zero" + CSRLI $64, X10 // ERROR "must be in range [0, 63]" + CSRAI $63, X10, X11 // ERROR "rd must be the same as rs1" + CSRAI $63, X5 // ERROR "expected integer prime register in rd" + CSRAI $-1, X10 // ERROR "must be in range [0, 63]" + CSRAI $0, X10 // ERROR "immediate cannot be zero" + CSRAI $64, X10 // ERROR "must be in range [0, 63]" + CAND $1, X10, X11 // ERROR "rd must be the same as rs1" + CAND $1, X5 // ERROR "expected integer prime register in rd" + CAND $-64, X10 // ERROR "must be in range [-32, 31]" + CAND $63, X10 // ERROR "must be in range [-32, 31]" + CANDI $1, X10, X11 // ERROR "rd must be the same as rs1" + CANDI $1, X5 // ERROR "expected integer prime register in rd" + CANDI $-64, X10 // ERROR "must be in range [-32, 31]" + CANDI $63, X10 // ERROR "must be in range [-32, 31]" + CMV X0, X5 // ERROR "cannot use register X0 in rs2" + CMV X5, X6, X7 // ERROR "expected no register in rs1" + CMV X5, X0 // ERROR "cannot use register X0 in rd" + CMV F1, X5 // ERROR "expected integer register in rs2" + CMV X5, F1 // ERROR "expected integer register in rd" + CADD X5, X6, X7 // ERROR "rd must be the same as rs1" + CADD X0, X8 // ERROR "cannot use register X0 in rs2" + CADD X8, X0 // ERROR "cannot use register X0 in rd" + CAND X10, X11, X12 // ERROR "rd must be the same as rs1" + CAND X5, X11 // ERROR "expected integer prime register in rs2" + CAND X10, X5 // ERROR "expected integer prime register in rd" + COR X10, X11, X12 // ERROR "rd must be the same as rs1" + COR X5, X11 // ERROR "expected integer prime register in rs2" + COR X10, X5 // ERROR "expected integer prime register in rd" + CXOR X10, X11, X12 // ERROR "rd must be the same as rs1" + CXOR X5, X11 // ERROR "expected integer prime register in rs2" + CXOR X10, X5 // ERROR "expected integer prime register in rd" + CSUB X10, X11, X12 // ERROR "rd must be the same as rs1" + CSUB X5, X11 // ERROR "expected integer prime register in rs2" + CSUB X10, X5 // ERROR "expected integer prime register in rd" + CADDW X10, X11, X12 // ERROR "rd must be the same as rs1" + CADDW X5, X11 // ERROR "expected integer prime register in rs2" + CADDW X10, X5 // ERROR "expected integer prime register in rd" + CSUBW X10, X11, X12 // ERROR "rd must be the same as rs1" + CSUBW X5, X11 // ERROR "expected integer prime register in rs2" + CSUBW X10, X5 // ERROR "expected integer prime register in rd" + CNOP X10 // ERROR "expected no register in rs2" + CEBREAK X10 // ERROR "expected no register in rs2" + // // "V" Standard Extension for Vector Operations, Version 1.0 // @@ -459,5 +597,9 @@ TEXT validation(SB),$0 VMV2RV X10, V10 // ERROR "expected vector register in vs2 position" VMV4RV X10, V4 // ERROR "expected vector register in vs2 position" VMV8RV X10, V0 // ERROR "expected vector register in vs2 position" + VRORVI $32, V2, V4 // ERROR "unsigned immediate 32 must be in range [0, 31]" + VRORVI $-1, V2, V4 // ERROR "unsigned immediate -1 must be in range [0, 31]" + VWSLLVI $32, V2, V4 // ERROR "unsigned immediate 32 must be in range [0, 31]" + VWSLLVI $-1, V2, V4 // ERROR "unsigned immediate -1 must be in range [0, 31]" RET diff --git a/src/cmd/asm/internal/asm/testdata/s390x.s b/src/cmd/asm/internal/asm/testdata/s390x.s index 93c3ec9ea7f22e..cb9a9917a5fde5 100644 --- a/src/cmd/asm/internal/asm/testdata/s390x.s +++ b/src/cmd/asm/internal/asm/testdata/s390x.s @@ -456,6 +456,7 @@ TEXT main·foo(SB),DUPOK|NOSPLIT,$16-0 // TEXT main.foo(SB), DUPOK|NOSPLIT, $16- VST V1, (R15) // e710f000000e VL (R15), V31 // e7f0f0000806 VST V31, (R15) // e7f0f000080e + VSTRL V4, $6, 1(R4) // e6064001403d VESLB $5, V14 // e7ee00050030 VESRAG $0, V15, V16 // e70f0000383a VLM (R15), V8, V23 // e787f0000436 diff --git a/src/cmd/asm/internal/flags/flags.go b/src/cmd/asm/internal/flags/flags.go index e15a062749fab5..a02dcae2c6f0ed 100644 --- a/src/cmd/asm/internal/flags/flags.go +++ b/src/cmd/asm/internal/flags/flags.go @@ -26,11 +26,13 @@ var ( SymABIs = flag.Bool("gensymabis", false, "write symbol ABI information to output file, don't assemble") Importpath = flag.String("p", obj.UnlinkablePkg, "set expected package import to path") Spectre = flag.String("spectre", "", "enable spectre mitigations in `list` (all, ret)") + Std = flag.Bool("std", false, "building standard library") ) var DebugFlags struct { - MayMoreStack string `help:"call named function before all stack growth checks"` - PCTab string `help:"print named pc-value table\nOne of: pctospadj, pctofile, pctoline, pctoinline, pctopcdata"` + CompressInstructions int `help:"use compressed instructions when possible (if supported by architecture)"` + MayMoreStack string `help:"call named function before all stack growth checks"` + PCTab string `help:"print named pc-value table\nOne of: pctospadj, pctofile, pctoline, pctoinline, pctopcdata"` } var ( @@ -47,6 +49,8 @@ func init() { flag.Var(objabi.NewDebugFlag(&DebugFlags, nil), "d", "enable debugging settings; try -d help") objabi.AddVersionFlag() // -V objabi.Flagcount("S", "print assembly and machine code", &PrintOut) + + DebugFlags.CompressInstructions = 1 } // MultiFlag allows setting a value multiple times to collect a list, as in -I=dir1 -I=dir2. diff --git a/src/cmd/asm/internal/lex/input.go b/src/cmd/asm/internal/lex/input.go index 789e229a779916..342ac5ac483beb 100644 --- a/src/cmd/asm/internal/lex/input.go +++ b/src/cmd/asm/internal/lex/input.go @@ -68,7 +68,7 @@ func predefine(defines flags.MultiFlag) map[string]*Macro { var panicOnError bool // For testing. -func (in *Input) Error(args ...interface{}) { +func (in *Input) Error(args ...any) { if panicOnError { panic(fmt.Errorf("%s:%d: %s", in.File(), in.Line(), fmt.Sprintln(args...))) } @@ -77,7 +77,7 @@ func (in *Input) Error(args ...interface{}) { } // expectText is like Error but adds "got XXX" where XXX is a quoted representation of the most recent token. -func (in *Input) expectText(args ...interface{}) { +func (in *Input) expectText(args ...any) { in.Error(append(args, "; got", strconv.Quote(in.Stack.Text()))...) } diff --git a/src/cmd/asm/main.go b/src/cmd/asm/main.go index 9db1fec8beac3c..d553fc8c32c0c2 100644 --- a/src/cmd/asm/main.go +++ b/src/cmd/asm/main.go @@ -40,6 +40,7 @@ func main() { log.Fatalf("unrecognized architecture %s", GOARCH) } ctxt := obj.Linknew(architecture.LinkArch) + ctxt.CompressInstructions = flags.DebugFlags.CompressInstructions != 0 ctxt.Debugasm = flags.PrintOut ctxt.Debugvlog = flags.DebugV ctxt.Flag_dynlink = *flags.Dynlink @@ -49,6 +50,7 @@ func main() { ctxt.Debugpcln = flags.DebugFlags.PCTab ctxt.IsAsm = true ctxt.Pkgpath = *flags.Importpath + ctxt.Std = *flags.Std ctxt.DwTextCount = objabi.DummyDwarfFunctionCountForAssembler() switch *flags.Spectre { default: @@ -93,7 +95,7 @@ func main() { for _, f := range flag.Args() { lexer := lex.NewLexer(f) parser := asm.NewParser(ctxt, architecture, lexer) - ctxt.DiagFunc = func(format string, args ...interface{}) { + ctxt.DiagFunc = func(format string, args ...any) { diag = true log.Printf(format, args...) } diff --git a/src/cmd/cgo/ast.go b/src/cmd/cgo/ast.go index 861479db7acf5b..df0552f525adad 100644 --- a/src/cmd/cgo/ast.go +++ b/src/cmd/cgo/ast.go @@ -199,7 +199,7 @@ func commentText(g *ast.CommentGroup) string { return strings.Join(pieces, "") } -func (f *File) validateIdents(x interface{}, context astContext) { +func (f *File) validateIdents(x any, context astContext) { if x, ok := x.(*ast.Ident); ok { if f.isMangledName(x.Name) { error_(x.Pos(), "identifier %q may conflict with identifiers generated by cgo", x.Name) @@ -208,7 +208,7 @@ func (f *File) validateIdents(x interface{}, context astContext) { } // Save various references we are going to need later. -func (f *File) saveExprs(x interface{}, context astContext) { +func (f *File) saveExprs(x any, context astContext) { switch x := x.(type) { case *ast.Expr: switch (*x).(type) { @@ -278,7 +278,7 @@ func (f *File) saveCall(call *ast.CallExpr, context astContext) { } // If a function should be exported add it to ExpFunc. -func (f *File) saveExport(x interface{}, context astContext) { +func (f *File) saveExport(x any, context astContext) { n, ok := x.(*ast.FuncDecl) if !ok { return @@ -301,24 +301,19 @@ func (f *File) saveExport(x interface{}, context astContext) { error_(c.Pos(), "export comment has wrong name %q, want %q", name, n.Name.Name) } - doc := "" - for _, c1 := range n.Doc.List { - if c1 != c { - doc += c1.Text + "\n" - } - } - f.ExpFunc = append(f.ExpFunc, &ExpFunc{ Func: n, ExpName: name, - Doc: doc, + // Caution: Do not set the Doc field on purpose + // to ensure that there are no unintended artifacts + // in the binary. See https://go.dev/issue/76697. }) break } } // Make f.ExpFunc[i] point at the Func from this AST instead of the other one. -func (f *File) saveExport2(x interface{}, context astContext) { +func (f *File) saveExport2(x any, context astContext) { n, ok := x.(*ast.FuncDecl) if !ok { return @@ -355,7 +350,7 @@ const ( ) // walk walks the AST x, calling visit(f, x, context) for each node. -func (f *File) walk(x interface{}, context astContext, visit func(*File, interface{}, astContext)) { +func (f *File) walk(x any, context astContext, visit func(*File, any, astContext)) { visit(f, x, context) switch n := x.(type) { case *ast.Expr: @@ -363,7 +358,8 @@ func (f *File) walk(x interface{}, context astContext, visit func(*File, interfa // everything else just recurs default: - f.walkUnexpected(x, context, visit) + error_(token.NoPos, "unexpected type %T in walk", x) + panic("unexpected type") case nil: @@ -396,6 +392,9 @@ func (f *File) walk(x interface{}, context astContext, visit func(*File, interfa case *ast.IndexExpr: f.walk(&n.X, ctxExpr, visit) f.walk(&n.Index, ctxExpr, visit) + case *ast.IndexListExpr: + f.walk(&n.X, ctxExpr, visit) + f.walk(n.Indices, ctxExpr, visit) case *ast.SliceExpr: f.walk(&n.X, ctxExpr, visit) if n.Low != nil { @@ -434,8 +433,8 @@ func (f *File) walk(x interface{}, context astContext, visit func(*File, interfa case *ast.StructType: f.walk(n.Fields, ctxField, visit) case *ast.FuncType: - if tparams := funcTypeTypeParams(n); tparams != nil { - f.walk(tparams, ctxParam, visit) + if n.TypeParams != nil { + f.walk(n.TypeParams, ctxParam, visit) } f.walk(n.Params, ctxParam, visit) if n.Results != nil { @@ -524,8 +523,8 @@ func (f *File) walk(x interface{}, context astContext, visit func(*File, interfa f.walk(n.Values, ctxExpr, visit) } case *ast.TypeSpec: - if tparams := typeSpecTypeParams(n); tparams != nil { - f.walk(tparams, ctxParam, visit) + if n.TypeParams != nil { + f.walk(n.TypeParams, ctxParam, visit) } f.walk(&n.Type, ctxType, visit) diff --git a/src/cmd/cgo/ast_go1.go b/src/cmd/cgo/ast_go1.go deleted file mode 100644 index 2f65f0f718356f..00000000000000 --- a/src/cmd/cgo/ast_go1.go +++ /dev/null @@ -1,25 +0,0 @@ -// Copyright 2021 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -//go:build compiler_bootstrap - -package main - -import ( - "go/ast" - "go/token" -) - -func (f *File) walkUnexpected(x interface{}, context astContext, visit func(*File, interface{}, astContext)) { - error_(token.NoPos, "unexpected type %T in walk", x) - panic("unexpected type") -} - -func funcTypeTypeParams(n *ast.FuncType) *ast.FieldList { - return nil -} - -func typeSpecTypeParams(n *ast.TypeSpec) *ast.FieldList { - return nil -} diff --git a/src/cmd/cgo/ast_go118.go b/src/cmd/cgo/ast_go118.go deleted file mode 100644 index ced30728dc9a79..00000000000000 --- a/src/cmd/cgo/ast_go118.go +++ /dev/null @@ -1,32 +0,0 @@ -// Copyright 2021 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -//go:build !compiler_bootstrap - -package main - -import ( - "go/ast" - "go/token" -) - -func (f *File) walkUnexpected(x interface{}, context astContext, visit func(*File, interface{}, astContext)) { - switch n := x.(type) { - default: - error_(token.NoPos, "unexpected type %T in walk", x) - panic("unexpected type") - - case *ast.IndexListExpr: - f.walk(&n.X, ctxExpr, visit) - f.walk(n.Indices, ctxExpr, visit) - } -} - -func funcTypeTypeParams(n *ast.FuncType) *ast.FieldList { - return n.TypeParams -} - -func typeSpecTypeParams(n *ast.TypeSpec) *ast.FieldList { - return n.TypeParams -} diff --git a/src/cmd/cgo/doc.go b/src/cmd/cgo/doc.go index ef5272299bbf07..47d243d1a16190 100644 --- a/src/cmd/cgo/doc.go +++ b/src/cmd/cgo/doc.go @@ -127,7 +127,7 @@ environment variable when running the go tool: set it to 1 to enable the use of cgo, and to 0 to disable it. The go tool will set the build constraint "cgo" if cgo is enabled. The special import "C" implies the "cgo" build constraint, as though the file also said -"//go:build cgo". Therefore, if cgo is disabled, files that import +"//go:build cgo". Therefore, if cgo is disabled, files that import "C" will not be built by the go tool. (For more about build constraints see https://golang.org/pkg/go/build/#hdr-Build_Constraints). @@ -425,8 +425,8 @@ and of course there is nothing stopping the C code from doing anything it likes. However, programs that break these rules are likely to fail in unexpected and unpredictable ways. -The runtime/cgo.Handle type can be used to safely pass Go values -between Go and C. See the runtime/cgo package documentation for details. +The type [runtime/cgo.Handle] can be used to safely pass Go values +between Go and C. Note: the current implementation has a bug. While Go code is permitted to write nil or a C pointer (but not a Go pointer) to C memory, the diff --git a/src/cmd/cgo/gcc.go b/src/cmd/cgo/gcc.go index 886ddf2d461b65..b8b8d6baec6554 100644 --- a/src/cmd/cgo/gcc.go +++ b/src/cmd/cgo/gcc.go @@ -24,6 +24,7 @@ import ( "math" "os" "os/exec" + "path/filepath" "slices" "strconv" "strings" @@ -1056,7 +1057,7 @@ func (p *Package) rewriteCall(f *File, call *Call) (string, bool) { func (p *Package) needsPointerCheck(f *File, t ast.Expr, arg ast.Expr) bool { // An untyped nil does not need a pointer check, and when // _cgoCheckPointer returns the untyped nil the type assertion we - // are going to insert will fail. Easier to just skip nil arguments. + // are going to insert will fail. Easier to just skip nil arguments. // TODO: Note that this fails if nil is shadowed. if id, ok := arg.(*ast.Ident); ok && id.Name == "nil" { return false @@ -1121,6 +1122,9 @@ func (p *Package) hasPointer(f *File, t ast.Expr, top bool) bool { if t.Name == "error" { return true } + if t.Name == "any" { + return true + } if goTypes[t.Name] != nil { return false } @@ -1158,7 +1162,7 @@ func (p *Package) hasPointer(f *File, t ast.Expr, top bool) bool { // If addPosition is true, add position info to the idents of C names in arg. func (p *Package) mangle(f *File, arg *ast.Expr, addPosition bool) (ast.Expr, bool) { needsUnsafe := false - f.walk(arg, ctxExpr, func(f *File, arg interface{}, context astContext) { + f.walk(arg, ctxExpr, func(f *File, arg any, context astContext) { px, ok := arg.(*ast.Expr) if !ok { return @@ -1792,7 +1796,7 @@ var n atomic.Int64 func gccTmp() string { c := strconv.Itoa(int(n.Add(1))) - return *objDir + "_cgo_" + c + ".o" + return filepath.Join(outputDir(), "_cgo_"+c+".o") } // gccCmd returns the gcc command line to use for compiling @@ -2439,7 +2443,7 @@ func (tr *TypeRepr) Empty() bool { // Set modifies the type representation. // If fargs are provided, repr is used as a format for fmt.Sprintf. // Otherwise, repr is used unprocessed as the type representation. -func (tr *TypeRepr) Set(repr string, fargs ...interface{}) { +func (tr *TypeRepr) Set(repr string, fargs ...any) { tr.Repr = repr tr.FormatArgs = fargs } @@ -2713,7 +2717,7 @@ func (c *typeConv) loadType(dtype dwarf.Type, pos token.Pos, parent string) *Typ // so execute the basic things that the struct case would do // other than try to determine a Go representation. tt := *t - tt.C = &TypeRepr{"%s %s", []interface{}{dt.Kind, tag}} + tt.C = &TypeRepr{"%s %s", []any{dt.Kind, tag}} // We don't know what the representation of this struct is, so don't let // anyone allocate one on the Go side. As a side effect of this annotation, // pointers to this type will not be considered pointers in Go. They won't @@ -2743,7 +2747,7 @@ func (c *typeConv) loadType(dtype dwarf.Type, pos token.Pos, parent string) *Typ t.Align = align tt := *t if tag != "" { - tt.C = &TypeRepr{"struct %s", []interface{}{tag}} + tt.C = &TypeRepr{"struct %s", []any{tag}} } tt.Go = g if c.incompleteStructs[tag] { @@ -3010,7 +3014,7 @@ func (c *typeConv) FuncType(dtype *dwarf.FuncType, pos token.Pos) *FuncType { for i, f := range dtype.ParamType { // gcc's DWARF generator outputs a single DotDotDotType parameter for // function pointers that specify no parameters (e.g. void - // (*__cgo_0)()). Treat this special case as void. This case is + // (*__cgo_0)()). Treat this special case as void. This case is // invalid according to ISO C anyway (i.e. void (*__cgo_1)(...) is not // legal). if _, ok := f.(*dwarf.DotDotDotType); ok && i == 0 { @@ -3081,7 +3085,7 @@ func (c *typeConv) Struct(dt *dwarf.StructType, pos token.Pos) (expr *ast.Struct off := int64(0) // Rename struct fields that happen to be named Go keywords into - // _{keyword}. Create a map from C ident -> Go ident. The Go ident will + // _{keyword}. Create a map from C ident -> Go ident. The Go ident will // be mangled. Any existing identifier that already has the same name on // the C-side will cause the Go-mangled version to be prefixed with _. // (e.g. in a struct with fields '_type' and 'type', the latter would be @@ -3309,7 +3313,7 @@ func godefsFields(fld []*ast.Field) { // fieldPrefix returns the prefix that should be removed from all the // field names when generating the C or Go code. For generated // C, we leave the names as is (tv_sec, tv_usec), since that's what -// people are used to seeing in C. For generated Go code, such as +// people are used to seeing in C. For generated Go code, such as // package syscall's data structures, we drop a common prefix // (so sec, usec, which will get turned into Sec, Usec for exporting). func fieldPrefix(fld []*ast.Field) string { @@ -3456,7 +3460,7 @@ func (c *typeConv) badCFType(dt *dwarf.TypedefType) bool { // Tagged pointer support // Low-bit set means tagged object, next 3 bits (currently) // define the tagged object class, next 4 bits are for type -// information for the specific tagged object class. Thus, +// information for the specific tagged object class. Thus, // the low byte is for type info, and the rest of a pointer // (32 or 64-bit) is for payload, whatever the tagged class. // diff --git a/src/cmd/cgo/godefs.go b/src/cmd/cgo/godefs.go index 9cf626c17322c2..93f9027157183b 100644 --- a/src/cmd/cgo/godefs.go +++ b/src/cmd/cgo/godefs.go @@ -117,7 +117,7 @@ func (p *Package) godefs(f *File, args []string) string { var gofmtBuf strings.Builder // gofmt returns the gofmt-formatted string for an AST node. -func gofmt(n interface{}) string { +func gofmt(n any) string { gofmtBuf.Reset() err := printer.Fprint(&gofmtBuf, fset, n) if err != nil { diff --git a/src/cmd/cgo/internal/test/buildid_linux.go b/src/cmd/cgo/internal/test/buildid_linux.go index 84d3edb664eb25..7e0fd0fd126a02 100644 --- a/src/cmd/cgo/internal/test/buildid_linux.go +++ b/src/cmd/cgo/internal/test/buildid_linux.go @@ -4,9 +4,9 @@ package cgotest -// Test that we have no more than one build ID. In the past we used +// Test that we have no more than one build ID. In the past we used // to generate a separate build ID for each package using cgo, and the -// linker concatenated them all. We don't want that--we only want +// linker concatenated them all. We don't want that--we only want // one. import ( @@ -42,7 +42,7 @@ sections: for len(d) > 0 { // ELF standards differ as to the sizes in - // note sections. Both the GNU linker and + // note sections. Both the GNU linker and // gold always generate 32-bit sizes, so that // is what we assume here. diff --git a/src/cmd/cgo/internal/test/callback.go b/src/cmd/cgo/internal/test/callback.go index 478bf8294af3a5..8f8dd8fded6f15 100644 --- a/src/cmd/cgo/internal/test/callback.go +++ b/src/cmd/cgo/internal/test/callback.go @@ -40,7 +40,7 @@ func nestedCall(f func()) { callbackMutex.Unlock() // Pass the address of i because the C function was written to - // take a pointer. We could pass an int if we felt like + // take a pointer. We could pass an int if we felt like // rewriting the C code. C.callback(unsafe.Pointer(&i)) diff --git a/src/cmd/cgo/internal/test/callstub_linux_ppc64le.go b/src/cmd/cgo/internal/test/callstub_linux_ppc64le.go deleted file mode 100644 index 93c29e1c7cdd97..00000000000000 --- a/src/cmd/cgo/internal/test/callstub_linux_ppc64le.go +++ /dev/null @@ -1,20 +0,0 @@ -// Copyright 2023 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -package cgotest - -// extern int notoc_func(void); -// int TestPPC64Stubs(void) { -// return notoc_func(); -// } -import "C" -import "testing" - -func testPPC64CallStubs(t *testing.T) { - // Verify the trampolines run on the testing machine. If they - // do not, or are missing, a crash is expected. - if C.TestPPC64Stubs() != 0 { - t.Skipf("This test requires binutils 2.35 or newer.") - } -} diff --git a/src/cmd/cgo/internal/test/callstub_linux_ppc64x.go b/src/cmd/cgo/internal/test/callstub_linux_ppc64x.go new file mode 100644 index 00000000000000..b0dd69fd64ba39 --- /dev/null +++ b/src/cmd/cgo/internal/test/callstub_linux_ppc64x.go @@ -0,0 +1,22 @@ +// Copyright 2023 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build (ppc64 || ppc64le) && linux && cgo + +package cgotest + +// extern int notoc_func(void); +// int TestPPC64Stubs(void) { +// return notoc_func(); +// } +import "C" +import "testing" + +func testPPC64CallStubs(t *testing.T) { + // Verify the trampolines run on the testing machine. If they + // do not, or are missing, a crash is expected. + if C.TestPPC64Stubs() != 0 { + t.Skipf("This test requires binutils 2.35 or newer.") + } +} diff --git a/src/cmd/cgo/internal/test/cgo_darwin_test.go b/src/cmd/cgo/internal/test/cgo_darwin_test.go new file mode 100644 index 00000000000000..e6c67a13f22f13 --- /dev/null +++ b/src/cmd/cgo/internal/test/cgo_darwin_test.go @@ -0,0 +1,12 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build cgo && darwin + +package cgotest + +import "testing" + +func TestIssue76023(t *testing.T) { issue76023(t) } +func TestGlobalDataDynimport(t *testing.T) { unsignedRelocDynimport(t) } diff --git a/src/cmd/cgo/internal/test/cgo_test.go b/src/cmd/cgo/internal/test/cgo_test.go index 5393552e07a4d1..17f9225cf9bf83 100644 --- a/src/cmd/cgo/internal/test/cgo_test.go +++ b/src/cmd/cgo/internal/test/cgo_test.go @@ -12,100 +12,106 @@ import "testing" // so that they can use cgo (import "C"). // These wrappers are here for gotest to find. -func Test1328(t *testing.T) { test1328(t) } -func Test1560(t *testing.T) { test1560(t) } -func Test1635(t *testing.T) { test1635(t) } -func Test3250(t *testing.T) { test3250(t) } -func Test3729(t *testing.T) { test3729(t) } -func Test3775(t *testing.T) { test3775(t) } -func Test4029(t *testing.T) { test4029(t) } -func Test4339(t *testing.T) { test4339(t) } -func Test5227(t *testing.T) { test5227(t) } -func Test5242(t *testing.T) { test5242(t) } -func Test5337(t *testing.T) { test5337(t) } -func Test5548(t *testing.T) { test5548(t) } -func Test5603(t *testing.T) { test5603(t) } -func Test5986(t *testing.T) { test5986(t) } -func Test6390(t *testing.T) { test6390(t) } -func Test6833(t *testing.T) { test6833(t) } -func Test6907(t *testing.T) { test6907(t) } -func Test6907Go(t *testing.T) { test6907Go(t) } -func Test7560(t *testing.T) { test7560(t) } -func Test7665(t *testing.T) { test7665(t) } -func Test7978(t *testing.T) { test7978(t) } -func Test8092(t *testing.T) { test8092(t) } -func Test8517(t *testing.T) { test8517(t) } -func Test8694(t *testing.T) { test8694(t) } -func Test8756(t *testing.T) { test8756(t) } -func Test8811(t *testing.T) { test8811(t) } -func Test9026(t *testing.T) { test9026(t) } -func Test9510(t *testing.T) { test9510(t) } -func Test9557(t *testing.T) { test9557(t) } -func Test10303(t *testing.T) { test10303(t, 10) } -func Test11925(t *testing.T) { test11925(t) } -func Test12030(t *testing.T) { test12030(t) } -func Test14838(t *testing.T) { test14838(t) } -func Test17065(t *testing.T) { test17065(t) } -func Test17537(t *testing.T) { test17537(t) } -func Test18126(t *testing.T) { test18126(t) } -func Test18720(t *testing.T) { test18720(t) } -func Test20129(t *testing.T) { test20129(t) } -func Test20266(t *testing.T) { test20266(t) } -func Test20369(t *testing.T) { test20369(t) } -func Test20910(t *testing.T) { test20910(t) } -func Test21708(t *testing.T) { test21708(t) } -func Test21809(t *testing.T) { test21809(t) } -func Test21897(t *testing.T) { test21897(t) } -func Test22906(t *testing.T) { test22906(t) } -func Test23356(t *testing.T) { test23356(t) } -func Test24206(t *testing.T) { test24206(t) } -func Test25143(t *testing.T) { test25143(t) } -func Test26066(t *testing.T) { test26066(t) } -func Test26213(t *testing.T) { test26213(t) } -func Test27660(t *testing.T) { test27660(t) } -func Test28896(t *testing.T) { test28896(t) } -func Test30065(t *testing.T) { test30065(t) } -func Test32579(t *testing.T) { test32579(t) } -func Test31891(t *testing.T) { test31891(t) } -func Test42018(t *testing.T) { test42018(t) } -func Test45451(t *testing.T) { test45451(t) } -func Test49633(t *testing.T) { test49633(t) } -func Test69086(t *testing.T) { test69086(t) } -func TestAlign(t *testing.T) { testAlign(t) } -func TestAtol(t *testing.T) { testAtol(t) } -func TestBlocking(t *testing.T) { testBlocking(t) } -func TestBoolAlign(t *testing.T) { testBoolAlign(t) } -func TestCallGoWithString(t *testing.T) { testCallGoWithString(t) } -func TestCallback(t *testing.T) { testCallback(t) } -func TestCallbackCallers(t *testing.T) { testCallbackCallers(t) } -func TestCallbackGC(t *testing.T) { testCallbackGC(t) } -func TestCallbackPanic(t *testing.T) { testCallbackPanic(t) } -func TestCallbackPanicLocked(t *testing.T) { testCallbackPanicLocked(t) } -func TestCallbackPanicLoop(t *testing.T) { testCallbackPanicLoop(t) } -func TestCallbackStack(t *testing.T) { testCallbackStack(t) } -func TestCflags(t *testing.T) { testCflags(t) } -func TestCheckConst(t *testing.T) { testCheckConst(t) } -func TestConst(t *testing.T) { testConst(t) } -func TestCthread(t *testing.T) { testCthread(t) } -func TestEnum(t *testing.T) { testEnum(t) } -func TestNamedEnum(t *testing.T) { testNamedEnum(t) } -func TestCastToEnum(t *testing.T) { testCastToEnum(t) } -func TestErrno(t *testing.T) { testErrno(t) } -func TestFpVar(t *testing.T) { testFpVar(t) } -func TestGCC68255(t *testing.T) { testGCC68255(t) } -func TestHandle(t *testing.T) { testHandle(t) } -func TestHelpers(t *testing.T) { testHelpers(t) } -func TestLibgcc(t *testing.T) { testLibgcc(t) } -func TestMultipleAssign(t *testing.T) { testMultipleAssign(t) } -func TestNaming(t *testing.T) { testNaming(t) } -func TestPanicFromC(t *testing.T) { testPanicFromC(t) } -func TestPrintf(t *testing.T) { testPrintf(t) } -func TestReturnAfterGrow(t *testing.T) { testReturnAfterGrow(t) } -func TestReturnAfterGrowFromGo(t *testing.T) { testReturnAfterGrowFromGo(t) } -func TestSetEnv(t *testing.T) { testSetEnv(t) } -func TestThreadLock(t *testing.T) { testThreadLockFunc(t) } -func TestUnsignedInt(t *testing.T) { testUnsignedInt(t) } -func TestZeroArgCallback(t *testing.T) { testZeroArgCallback(t) } +func Test1328(t *testing.T) { test1328(t) } +func Test1560(t *testing.T) { test1560(t) } +func Test1635(t *testing.T) { test1635(t) } +func Test3250(t *testing.T) { test3250(t) } +func Test3729(t *testing.T) { test3729(t) } +func Test3775(t *testing.T) { test3775(t) } +func Test4029(t *testing.T) { test4029(t) } +func Test4339(t *testing.T) { test4339(t) } +func Test5227(t *testing.T) { test5227(t) } +func Test5242(t *testing.T) { test5242(t) } +func Test5337(t *testing.T) { test5337(t) } +func Test5548(t *testing.T) { test5548(t) } +func Test5603(t *testing.T) { test5603(t) } +func Test5986(t *testing.T) { test5986(t) } +func Test6390(t *testing.T) { test6390(t) } +func Test6833(t *testing.T) { test6833(t) } +func Test6907(t *testing.T) { test6907(t) } +func Test6907Go(t *testing.T) { test6907Go(t) } +func Test7560(t *testing.T) { test7560(t) } +func Test7665(t *testing.T) { test7665(t) } +func Test7978(t *testing.T) { test7978(t) } +func Test8092(t *testing.T) { test8092(t) } +func Test8517(t *testing.T) { test8517(t) } +func Test8694(t *testing.T) { test8694(t) } +func Test8756(t *testing.T) { test8756(t) } +func Test8811(t *testing.T) { test8811(t) } +func Test9026(t *testing.T) { test9026(t) } +func Test9510(t *testing.T) { test9510(t) } +func Test9557(t *testing.T) { test9557(t) } +func Test10303(t *testing.T) { test10303(t, 10) } +func Test11925(t *testing.T) { test11925(t) } +func Test12030(t *testing.T) { test12030(t) } +func Test14838(t *testing.T) { test14838(t) } +func Test17065(t *testing.T) { test17065(t) } +func Test17537(t *testing.T) { test17537(t) } +func Test18126(t *testing.T) { test18126(t) } +func Test18720(t *testing.T) { test18720(t) } +func Test20129(t *testing.T) { test20129(t) } +func Test20266(t *testing.T) { test20266(t) } +func Test20369(t *testing.T) { test20369(t) } +func Test20910(t *testing.T) { test20910(t) } +func Test21708(t *testing.T) { test21708(t) } +func Test21809(t *testing.T) { test21809(t) } +func Test21897(t *testing.T) { test21897(t) } +func Test22906(t *testing.T) { test22906(t) } +func Test23356(t *testing.T) { test23356(t) } +func Test24206(t *testing.T) { test24206(t) } +func Test25143(t *testing.T) { test25143(t) } +func Test26066(t *testing.T) { test26066(t) } +func Test26213(t *testing.T) { test26213(t) } +func Test27660(t *testing.T) { test27660(t) } +func Test28896(t *testing.T) { test28896(t) } +func Test30065(t *testing.T) { test30065(t) } +func Test32579(t *testing.T) { test32579(t) } +func Test31891(t *testing.T) { test31891(t) } +func Test42018(t *testing.T) { test42018(t) } +func Test45451(t *testing.T) { test45451(t) } +func Test49633(t *testing.T) { test49633(t) } +func Test69086(t *testing.T) { test69086(t) } +func TestAlign(t *testing.T) { testAlign(t) } +func TestAtol(t *testing.T) { testAtol(t) } +func TestBlocking(t *testing.T) { testBlocking(t) } +func TestBoolAlign(t *testing.T) { testBoolAlign(t) } +func TestCallGoWithString(t *testing.T) { testCallGoWithString(t) } +func TestCallback(t *testing.T) { testCallback(t) } +func TestCallbackCallers(t *testing.T) { testCallbackCallers(t) } +func TestCallbackInInit(t *testing.T) { testCallbackInInit(t) } +func TestCallbackGC(t *testing.T) { testCallbackGC(t) } +func TestCallbackPanic(t *testing.T) { testCallbackPanic(t) } +func TestCallbackPanicLocked(t *testing.T) { testCallbackPanicLocked(t) } +func TestCallbackPanicLoop(t *testing.T) { testCallbackPanicLoop(t) } +func TestCallbackStack(t *testing.T) { testCallbackStack(t) } +func TestCflags(t *testing.T) { testCflags(t) } +func TestCheckConst(t *testing.T) { testCheckConst(t) } +func TestConst(t *testing.T) { testConst(t) } +func TestCthread(t *testing.T) { testCthread(t) } +func TestEnum(t *testing.T) { testEnum(t) } +func TestNamedEnum(t *testing.T) { testNamedEnum(t) } +func TestCastToEnum(t *testing.T) { testCastToEnum(t) } +func TestErrno(t *testing.T) { testErrno(t) } +func TestFpVar(t *testing.T) { testFpVar(t) } +func TestGCC68255(t *testing.T) { testGCC68255(t) } +func TestHandle(t *testing.T) { testHandle(t) } +func TestHelpers(t *testing.T) { testHelpers(t) } +func TestLibgcc(t *testing.T) { testLibgcc(t) } +func TestMultipleAssign(t *testing.T) { testMultipleAssign(t) } +func TestNaming(t *testing.T) { testNaming(t) } +func TestPanicFromC(t *testing.T) { testPanicFromC(t) } +func TestPrintf(t *testing.T) { testPrintf(t) } +func TestReturnAfterGrow(t *testing.T) { testReturnAfterGrow(t) } +func TestReturnAfterGrowFromGo(t *testing.T) { testReturnAfterGrowFromGo(t) } +func TestSetEnv(t *testing.T) { testSetEnv(t) } +func TestThreadLock(t *testing.T) { testThreadLockFunc(t) } +func TestUnsignedInt(t *testing.T) { testUnsignedInt(t) } +func TestZeroArgCallback(t *testing.T) { testZeroArgCallback(t) } +func Test76340(t *testing.T) { test76340(t) } +func TestDITCgo(t *testing.T) { testDITCgo(t) } +func TestDITCgoCallback(t *testing.T) { testDITCgoCallback(t) } +func TestDITCgoCallbackEnableDIT(t *testing.T) { testDITCgoCallbackEnableDIT(t) } +func TestDITCgoCallbackDisableDIT(t *testing.T) { testDITCgoCallbackDisableDIT(t) } func BenchmarkCgoCall(b *testing.B) { benchCgoCall(b) } func BenchmarkGoString(b *testing.B) { benchGoString(b) } diff --git a/src/cmd/cgo/internal/test/cthread_unix.c b/src/cmd/cgo/internal/test/cthread_unix.c index d0da643158e5f4..1901c6437f7b3d 100644 --- a/src/cmd/cgo/internal/test/cthread_unix.c +++ b/src/cmd/cgo/internal/test/cthread_unix.c @@ -56,3 +56,18 @@ callGoInCThread(int max) return max; } + +static void* +callbackInInitCThread(void* unused) +{ + callbackInInit(); + return NULL; +} + +void +callbackInInitC(void) +{ + pthread_t thread; + + pthread_create(&thread, NULL, callbackInInitCThread, NULL); +} diff --git a/src/cmd/cgo/internal/test/cthread_windows.c b/src/cmd/cgo/internal/test/cthread_windows.c index 4e52209dee1d18..5bfc6f2c485976 100644 --- a/src/cmd/cgo/internal/test/cthread_windows.c +++ b/src/cmd/cgo/internal/test/cthread_windows.c @@ -57,3 +57,19 @@ callGoInCThread(int max) CloseHandle((HANDLE)thread_id); return max; } + +__stdcall +static unsigned int +callbackInInitCThread(void* unused) +{ + callbackInInit(); + return 0; +} + +void +callbackInInitC(void) +{ + uintptr_t thread_id; + thread_id = _beginthreadex(0, 0, callbackInInitCThread, NULL, 0, 0); + CloseHandle((HANDLE)thread_id); +} diff --git a/src/cmd/cgo/internal/test/gcc68255/a.go b/src/cmd/cgo/internal/test/gcc68255/a.go index e106dee3ec023d..cc4804b90bd122 100644 --- a/src/cmd/cgo/internal/test/gcc68255/a.go +++ b/src/cmd/cgo/internal/test/gcc68255/a.go @@ -3,7 +3,7 @@ // license that can be found in the LICENSE file. // Test that it's OK to have C code that does nothing other than -// initialize a global variable. This used to fail with gccgo. +// initialize a global variable. This used to fail with gccgo. package gcc68255 diff --git a/src/cmd/cgo/internal/test/issue76023.go b/src/cmd/cgo/internal/test/issue76023.go new file mode 100644 index 00000000000000..7fe8ae53f7eb66 --- /dev/null +++ b/src/cmd/cgo/internal/test/issue76023.go @@ -0,0 +1,27 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build darwin + +package cgotest + +/* +#cgo LDFLAGS: -Wl,-undefined,dynamic_lookup + +extern void __gotest_cgo_null_api(void) __attribute__((weak_import)); + +int issue76023(void) { + if (__gotest_cgo_null_api) return 1; + return 0; +} +*/ +import "C" +import "testing" + +func issue76023(t *testing.T) { + r := C.issue76023() + if r != 0 { + t.Error("found __gotest_cgo_null_api") + } +} diff --git a/src/cmd/cgo/internal/test/issue76861.go b/src/cmd/cgo/internal/test/issue76861.go new file mode 100644 index 00000000000000..225e2acc3f64be --- /dev/null +++ b/src/cmd/cgo/internal/test/issue76861.go @@ -0,0 +1,12 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build cgo + +package cgotest + +// Issue 43639: No runtime test needed, make sure package +// cmd/cgo/internal/test/issue76861 compiles without error. + +import _ "cmd/cgo/internal/test/issue76861" diff --git a/src/cmd/cgo/internal/test/issue76861/a.go b/src/cmd/cgo/internal/test/issue76861/a.go new file mode 100644 index 00000000000000..18a7bda490c52b --- /dev/null +++ b/src/cmd/cgo/internal/test/issue76861/a.go @@ -0,0 +1,13 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package issue76861 + +// #cgo CFLAGS: -Wall -Werror +// void issue76861(void) {} +import "C" + +func Issue76861() { + C.issue76861() +} diff --git a/src/cmd/cgo/internal/test/linux_ppc64le_test.go b/src/cmd/cgo/internal/test/linux_ppc64le_test.go deleted file mode 100644 index 67b6b161d695fc..00000000000000 --- a/src/cmd/cgo/internal/test/linux_ppc64le_test.go +++ /dev/null @@ -1,13 +0,0 @@ -// Copyright 2023 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -//go:build ppc64le && linux && cgo - -package cgotest - -import "testing" - -func TestPPC64CallStubs(t *testing.T) { - testPPC64CallStubs(t) -} diff --git a/src/cmd/cgo/internal/test/linux_ppc64x_test.go b/src/cmd/cgo/internal/test/linux_ppc64x_test.go new file mode 100644 index 00000000000000..a6e85b6ea34d08 --- /dev/null +++ b/src/cmd/cgo/internal/test/linux_ppc64x_test.go @@ -0,0 +1,13 @@ +// Copyright 2023 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build (ppc64 || ppc64le) && linux && cgo + +package cgotest + +import "testing" + +func TestPPC64CallStubs(t *testing.T) { + testPPC64CallStubs(t) +} diff --git a/src/cmd/cgo/internal/test/seh_internal_windows_test.go b/src/cmd/cgo/internal/test/seh_internal_windows_test.go deleted file mode 100644 index 708ffdc6f60bda..00000000000000 --- a/src/cmd/cgo/internal/test/seh_internal_windows_test.go +++ /dev/null @@ -1,16 +0,0 @@ -// Copyright 2024 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -//go:build cgo && windows && internal - -package cgotest - -import ( - "internal/testenv" - "testing" -) - -func TestCallbackCallersSEH(t *testing.T) { - testenv.SkipFlaky(t, 65116) -} diff --git a/src/cmd/cgo/internal/test/seh_windows_test.go b/src/cmd/cgo/internal/test/seh_windows_test.go index 4a8d5bbd4dcc02..7bbed5b04e3f6f 100644 --- a/src/cmd/cgo/internal/test/seh_windows_test.go +++ b/src/cmd/cgo/internal/test/seh_windows_test.go @@ -2,7 +2,7 @@ // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. -//go:build cgo && windows && !internal +//go:build cgo && windows package cgotest diff --git a/src/cmd/cgo/internal/test/stubtest_linux_ppc64le.S b/src/cmd/cgo/internal/test/stubtest_linux_ppc64le.S deleted file mode 100644 index 0c519705a508f2..00000000000000 --- a/src/cmd/cgo/internal/test/stubtest_linux_ppc64le.S +++ /dev/null @@ -1,122 +0,0 @@ -// Copyright 2023 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -// When linking C ELFv2 objects, the Go linker may need to insert calling stubs. -// A call stub is usually needed when the ELFv2 st_other attribute is different -// between caller and callee. -// -// The type of call stub inserted will vary depending on GOPPC64 and the -// buildmode (e.g pie builds shared code, default builds fixed-position code). -// CI is set up to run for P8 and P10 machines, and this test is run in both -// pie and default modes. -// -// Several functions are written with interesting st_other attributes, and -// call each other to test various calling combinations which require stubs. -// -// The call tree is as follows, starting from TestPPC64Stubs (A C function): -// TestPPC64Stubs (compiled PIC by default by Go) -// notoc_func [called TOC -> NOTOC (but R2 is preserved)] -// toc_func [called NOTOC -> TOC] -// notoc_nor2_func [called TOC -> NOTOC] -// random [dynamic TOC call] -// random [dynamic NOTOC call] -// -// Depending on the GOPPC64/buildmode used, and type of call, one of 7 stubs may need inserted: -// -// TOC -> NOTOC: Save R2, call global entry. (valid for any GOPPC64) -// TOC save slot is rewrittent to restore TOC. -// NOTOC -> TOC [P10]: A PIC call stub using P10 instructions to call the global entry -// NOTOC -> TOC [P8]: A PIC call stub using P8 instructions to call the global entry -// -// TOC -> dynamic: A PLT call stub is generated which saves R2. -// TOC save slot is rewritten to restore TOC. -// NOTOC -> dynamic [P10]: A stub using pcrel instructions is generated. -// NOTOC -> dynamic [P8/default]: A P8 compatible, non-PIC stub is generated -// NOTOC -> dynamic [P8/pie]: A P8 compatible, PIC stub is generated -// -// -// Some notes about other cases: -// TOC -> TOC, NOTOC -> NOTOC, NOTOC -> TOC local calls do not require require call stubs. -// TOC -> NOTOC (R2 is preserved, st_other==0): A special case where a call stub is not needed. - -// This test requires a binutils with power10 and ELFv2 1.5 support. This is earliest verified version. -.if .gasversion. >= 23500 - -// A function which does not guarantee R2 is preserved. -// R2 is clobbered here to ensure the stubs preserve it. - .globl notoc_nor2_func - .type notoc_nor2_func, @function -notoc_nor2_func: - .localentry notoc_nor2_func,1 - li 2,0 - blr - -// A function which expects R2 to hold TOC, and has a distinct local entry. - .globl toc_func - .type toc_func, @function -toc_func: - addis 2,12,.TOC.-toc_func@ha - addi 2,2,.TOC.-toc_func@l - .localentry toc_func, .-toc_func - mflr 0 - std 0,16(1) - stdu 1,-32(1) - - // Call a NOTOC function which clobbers R2. - bl notoc_nor2_func - nop - - // Call libc random. This should generate a TOC relative plt stub. - bl random - nop - - addi 1,1,32 - ld 0,16(1) - mtlr 0 - blr - -// An ELFv2 st_other==0 function. It preserves R2 (TOC), but does not use it. - .globl notoc_func - .type notoc_func, @function -notoc_func: - // Save R2 and LR and stack a frame. - mflr 0 - std 0,16(1) - stdu 1,-32(1) - - // Save R2 in TOC save slot. - std 2,24(1) - - // clobber R2 - li 2,0 - - // Call type2_func. A call stub from notoc to toc should be inserted. - bl toc_func@notoc - - // Call libc random. A notoc plt stub should be inserted. - bl random@notoc - - // Return 0 to indicate the test ran. - li 3,0 - - // Restore R2 - ld 2,24(1) - - // Restore LR and pop stack - addi 1,1,32 - ld 0,16(1) - mtlr 0 - blr - -.else - -// A stub for older binutils - .globl notoc_func - .type notoc_func, @function -notoc_func: - // Return 1 to indicate the test was skipped. - li 3,1 - blr - -.endif diff --git a/src/cmd/cgo/internal/test/stubtest_linux_ppc64x.S b/src/cmd/cgo/internal/test/stubtest_linux_ppc64x.S new file mode 100644 index 00000000000000..668eb3224e6dc1 --- /dev/null +++ b/src/cmd/cgo/internal/test/stubtest_linux_ppc64x.S @@ -0,0 +1,124 @@ +// Copyright 2023 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build (ppc64 || ppc64le) && linux && cgo + +// When linking C ELFv2 objects, the Go linker may need to insert calling stubs. +// A call stub is usually needed when the ELFv2 st_other attribute is different +// between caller and callee. +// +// The type of call stub inserted will vary depending on GOPPC64 and the +// buildmode (e.g pie builds shared code, default builds fixed-position code). +// CI is set up to run for P8 and P10 machines, and this test is run in both +// pie and default modes. +// +// Several functions are written with interesting st_other attributes, and +// call each other to test various calling combinations which require stubs. +// +// The call tree is as follows, starting from TestPPC64Stubs (A C function): +// TestPPC64Stubs (compiled PIC by default by Go) +// notoc_func [called TOC -> NOTOC (but R2 is preserved)] +// toc_func [called NOTOC -> TOC] +// notoc_nor2_func [called TOC -> NOTOC] +// random [dynamic TOC call] +// random [dynamic NOTOC call] +// +// Depending on the GOPPC64/buildmode used, and type of call, one of 7 stubs may need inserted: +// +// TOC -> NOTOC: Save R2, call global entry. (valid for any GOPPC64) +// TOC save slot is rewrittent to restore TOC. +// NOTOC -> TOC [P10]: A PIC call stub using P10 instructions to call the global entry +// NOTOC -> TOC [P8]: A PIC call stub using P8 instructions to call the global entry +// +// TOC -> dynamic: A PLT call stub is generated which saves R2. +// TOC save slot is rewritten to restore TOC. +// NOTOC -> dynamic [P10]: A stub using pcrel instructions is generated. +// NOTOC -> dynamic [P8/default]: A P8 compatible, non-PIC stub is generated +// NOTOC -> dynamic [P8/pie]: A P8 compatible, PIC stub is generated +// +// +// Some notes about other cases: +// TOC -> TOC, NOTOC -> NOTOC, NOTOC -> TOC local calls do not require require call stubs. +// TOC -> NOTOC (R2 is preserved, st_other==0): A special case where a call stub is not needed. + +// This test requires a binutils with power10 and ELFv2 1.5 support. This is earliest verified version. +.if .gasversion. >= 23500 + +// A function which does not guarantee R2 is preserved. +// R2 is clobbered here to ensure the stubs preserve it. + .globl notoc_nor2_func + .type notoc_nor2_func, @function +notoc_nor2_func: + .localentry notoc_nor2_func,1 + li 2,0 + blr + +// A function which expects R2 to hold TOC, and has a distinct local entry. + .globl toc_func + .type toc_func, @function +toc_func: + addis 2,12,.TOC.-toc_func@ha + addi 2,2,.TOC.-toc_func@l + .localentry toc_func, .-toc_func + mflr 0 + std 0,16(1) + stdu 1,-32(1) + + // Call a NOTOC function which clobbers R2. + bl notoc_nor2_func + nop + + // Call libc random. This should generate a TOC relative plt stub. + bl random + nop + + addi 1,1,32 + ld 0,16(1) + mtlr 0 + blr + +// An ELFv2 st_other==0 function. It preserves R2 (TOC), but does not use it. + .globl notoc_func + .type notoc_func, @function +notoc_func: + // Save R2 and LR and stack a frame. + mflr 0 + std 0,16(1) + stdu 1,-32(1) + + // Save R2 in TOC save slot. + std 2,24(1) + + // clobber R2 + li 2,0 + + // Call type2_func. A call stub from notoc to toc should be inserted. + bl toc_func@notoc + + // Call libc random. A notoc plt stub should be inserted. + bl random@notoc + + // Return 0 to indicate the test ran. + li 3,0 + + // Restore R2 + ld 2,24(1) + + // Restore LR and pop stack + addi 1,1,32 + ld 0,16(1) + mtlr 0 + blr + +.else + +// A stub for older binutils + .globl notoc_func + .type notoc_func, @function +notoc_func: + // Return 1 to indicate the test was skipped. + li 3,1 + blr + +.endif diff --git a/src/cmd/cgo/internal/test/test.go b/src/cmd/cgo/internal/test/test.go index 9626407d882ef2..3f0732b428b2fc 100644 --- a/src/cmd/cgo/internal/test/test.go +++ b/src/cmd/cgo/internal/test/test.go @@ -953,13 +953,61 @@ typedef struct { } issue69086struct; static int issue690861(issue69086struct* p) { p->b = 1234; return p->c; } static int issue690862(unsigned long ul1, unsigned long ul2, unsigned int u, issue69086struct s) { return (int)(s.b); } + +char issue75751v = 1; +char * const issue75751p = &issue75751v; +#define issue75751m issue75751p +char * const volatile issue75751p2 = &issue75751v; +#define issue75751m2 issue75751p2 + +typedef struct { void *t; void *v; } GoInterface; +extern int exportAny76340Param(GoInterface); +extern GoInterface exportAny76340Return(int); + +int issue76340testFromC(GoInterface obj) { + return exportAny76340Param(obj); +} + +GoInterface issue76340returnFromC(int val) { + return exportAny76340Return(val); +} + +static void enableDIT() { + #ifdef __arm64__ + __asm__ __volatile__("msr dit, #1"); + #endif +} + +static void disableDIT() { + #ifdef __arm64__ + __asm__ __volatile__("msr dit, #0"); + #endif +} + +extern uint8_t ditCallback(); + +static uint8_t ditCallbackTest() { + return ditCallback(); +} + +static void ditCallbackEnableDIT() { + enableDIT(); + ditCallback(); +} + +static void ditCallbackDisableDIT() { + disableDIT(); + ditCallback(); +} */ import "C" import ( "context" + "crypto/subtle" "fmt" "internal/asan" + "internal/runtime/sys" "math" "math/rand" "os" @@ -2396,3 +2444,100 @@ func test69086(t *testing.T) { t.Errorf("call: got %d, want 1234", got) } } + +// Issue 75751: no runtime test, just make sure it compiles. +func test75751() int { + return int(*C.issue75751m) + int(*C.issue75751m2) +} + +// Issue 76340. +func test76340(t *testing.T) { + var emptyInterface C.GoInterface + r1 := C.issue76340testFromC(emptyInterface) + if r1 != 0 { + t.Errorf("issue76340testFromC with nil interface: got %d, want 0", r1) + } + + r2 := C.issue76340returnFromC(42) + if r2.t == nil && r2.v == nil { + t.Error("issue76340returnFromC(42) returned nil interface") + } + + r3 := C.issue76340returnFromC(0) + if r3.t != nil || r3.v != nil { + t.Errorf("issue76340returnFromC(0) returned non-nil interface: got %v, want nil", r3) + } +} + +func testDITCgo(t *testing.T) { + if !sys.DITSupported { + t.Skip("CPU does not support DIT") + } + + ditAlreadyEnabled := sys.DITEnabled() + C.enableDIT() + + if ditAlreadyEnabled != sys.DITEnabled() { + t.Fatalf("DIT state not preserved across cgo call: before %t, after %t", ditAlreadyEnabled, sys.DITEnabled()) + } + + subtle.WithDataIndependentTiming(func() { + C.disableDIT() + + if !sys.DITEnabled() { + t.Fatal("DIT disabled after disabling in cgo call") + } + }) +} + +func testDITCgoCallback(t *testing.T) { + if !sys.DITSupported { + t.Skip("CPU does not support DIT") + } + + ditAlreadyEnabled := sys.DITEnabled() + + subtle.WithDataIndependentTiming(func() { + if C.ditCallbackTest() != 1 { + t.Fatal("DIT not enabled in cgo callback within WithDataIndependentTiming") + } + }) + + if ditAlreadyEnabled != sys.DITEnabled() { + t.Fatalf("DIT state not preserved across cgo callback: before %t, after %t", ditAlreadyEnabled, sys.DITEnabled()) + } +} + +func testDITCgoCallbackEnableDIT(t *testing.T) { + if !sys.DITSupported { + t.Skip("CPU does not support DIT") + } + + ditAlreadyEnabled := sys.DITEnabled() + + C.ditCallbackEnableDIT() + + if ditAlreadyEnabled != sys.DITEnabled() { + t.Fatalf("DIT state not preserved across cgo callback: before %t, after %t", ditAlreadyEnabled, sys.DITEnabled()) + } +} + +func testDITCgoCallbackDisableDIT(t *testing.T) { + if !sys.DITSupported { + t.Skip("CPU does not support DIT") + } + + ditAlreadyEnabled := sys.DITEnabled() + + subtle.WithDataIndependentTiming(func() { + C.ditCallbackDisableDIT() + + if !sys.DITEnabled() { + t.Fatal("DIT disabled after disabling in cgo call") + } + }) + + if ditAlreadyEnabled != sys.DITEnabled() { + t.Fatalf("DIT state not preserved across cgo callback: before %t, after %t", ditAlreadyEnabled, sys.DITEnabled()) + } +} diff --git a/src/cmd/cgo/internal/test/testx.go b/src/cmd/cgo/internal/test/testx.go index 9a63b9e10087ad..1c5ac99bd28596 100644 --- a/src/cmd/cgo/internal/test/testx.go +++ b/src/cmd/cgo/internal/test/testx.go @@ -11,6 +11,7 @@ package cgotest import ( + "internal/runtime/sys" "runtime" "runtime/cgo" "runtime/debug" @@ -25,6 +26,7 @@ import ( // threads extern void doAdd(int, int); extern int callGoInCThread(int); +extern void callbackInInitC(void); // issue 1328 void IntoC(void); @@ -595,3 +597,54 @@ func test49633(t *testing.T) { t.Errorf("msg = %q, want 'hello'", v.msg) } } + +//export exportAny76340Param +func exportAny76340Param(obj any) C.int { + if obj == nil { + return 0 + } + + return 1 +} + +//export exportAny76340Return +func exportAny76340Return(val C.int) any { + if val == 0 { + return nil + } + + return int(val) +} + +//export ditCallback +func ditCallback() uint8 { + if sys.DITEnabled() { + return 1 + } + return 0 +} + +// Test C calling back into Go before init is done. +// In particular, this does not trigger false race +// (the fix is in CL 746581). + +var callbackInInitVar int + +func init() { + C.callbackInInitC() + callbackInInitVar = 123 +} + +var callbackInInitChan = make(chan int) + +//export callbackInInit +func callbackInInit() { + if callbackInInitVar != 123 { + panic("callbackInInitVar not initialized to 123") + } + callbackInInitChan <- 1 +} + +func testCallbackInInit(t *testing.T) { + <-callbackInInitChan // make sure callbackInInit runs +} diff --git a/src/cmd/cgo/internal/test/unsigned_reloc_darwin.go b/src/cmd/cgo/internal/test/unsigned_reloc_darwin.go new file mode 100644 index 00000000000000..3db5ed19161ea8 --- /dev/null +++ b/src/cmd/cgo/internal/test/unsigned_reloc_darwin.go @@ -0,0 +1,41 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build darwin + +package cgotest + +/* +#include + +// Global function pointer to a dynamically-linked libc function. +// When compiled to a Mach-O object, this produces a RELOC_UNSIGNED +// relocation targeting the external symbol _puts. +int (*_cgo_test_dynref_puts)(const char *) = puts; + +static int cgo_call_dynref(void) { + if (_cgo_test_dynref_puts == 0) { + return -1; + } + // Call the resolved function pointer. puts returns a non-negative + // value on success. + return _cgo_test_dynref_puts("cgo unsigned reloc test"); +} +*/ +import "C" + +import "testing" + +// unsignedRelocDynimport verifies that the Go internal linker correctly +// handles Mach-O UNSIGNED relocations targeting dynamic import symbols. +// The C preamble above contains a global function pointer initialized +// to puts, which produces a RELOC_UNSIGNED relocation to the external +// symbol _puts. If the linker can't handle this, the test binary +// won't link at all. +func unsignedRelocDynimport(t *testing.T) { + got := C.cgo_call_dynref() + if got < 0 { + t.Fatal("C function pointer to puts not resolved") + } +} diff --git a/src/cmd/cgo/internal/testcarchive/carchive_test.go b/src/cmd/cgo/internal/testcarchive/carchive_test.go index 7c6e2b1d848def..a04959e85979fc 100644 --- a/src/cmd/cgo/internal/testcarchive/carchive_test.go +++ b/src/cmd/cgo/internal/testcarchive/carchive_test.go @@ -502,7 +502,7 @@ func TestInstall(t *testing.T) { func TestEarlySignalHandler(t *testing.T) { switch GOOS { - case "darwin", "ios": + case "ios": switch GOARCH { case "arm64": t.Skipf("skipping on %s/%s; see https://golang.org/issue/13701", GOOS, GOARCH) @@ -1351,7 +1351,7 @@ func TestDeepStack(t *testing.T) { } func BenchmarkCgoCallbackMainThread(b *testing.B) { - // Benchmark for calling into Go fron C main thread. + // Benchmark for calling into Go from C main thread. // See issue #68587. // // It uses a subprocess, which is a C binary that calls diff --git a/src/cmd/cgo/internal/testcshared/cshared_test.go b/src/cmd/cgo/internal/testcshared/cshared_test.go index c01f5cf2cfbe7a..abaa75587eb3a1 100644 --- a/src/cmd/cgo/internal/testcshared/cshared_test.go +++ b/src/cmd/cgo/internal/testcshared/cshared_test.go @@ -462,7 +462,7 @@ func GoFunc%d() {} // NumberOfNames is the number of functions exported with a unique name. // NumberOfFunctions can be higher than that because it also counts - // functions exported only by ordinal, a unique number asigned by the linker, + // functions exported only by ordinal, a unique number assigned by the linker, // and linkers might add an unknown number of their own ordinal-only functions. if wantAll { if e.NumberOfNames <= uint32(exportedSymbols) { @@ -942,3 +942,29 @@ func TestIssue68411(t *testing.T) { t.Error("missing functions") } } + +func TestSymbolicFunctions(t *testing.T) { + // Test that we can build a c-shared library with -Wl,-Bsymbolic-functions, + // see issue 80632. + globalSkip(t) + testenv.MustHaveGoBuild(t) + testenv.MustHaveCGO(t) + testenv.MustHaveBuildMode(t, "c-shared") + if GOOS != "linux" { + t.Skip("Skipping on non-Linux OS") + } + + t.Parallel() + + tmpdir := t.TempDir() + libname := filepath.Join(tmpdir, "libbsymbolic.a") + + run(t, + nil, + "go", "build", + "-buildmode=c-shared", + "-installsuffix", "testcshared", + "-ldflags=-extldflags=-Wl,-Bsymbolic-functions", + "-o", libname, "./libgo", + ) +} diff --git a/src/cmd/cgo/internal/testerrors/argposition_test.go b/src/cmd/cgo/internal/testerrors/argposition_test.go index 035552127b8f46..30447e7a68807e 100644 --- a/src/cmd/cgo/internal/testerrors/argposition_test.go +++ b/src/cmd/cgo/internal/testerrors/argposition_test.go @@ -96,7 +96,7 @@ func TestArgumentsPositions(t *testing.T) { t.Fatal(err) } fset := token.NewFileSet() - f, err := parser.ParseFile(fset, "", mainProcessed, parser.AllErrors) + f, err := parser.ParseFile(fset, "", mainProcessed, parser.AllErrors|parser.SkipObjectResolution) if err != nil { fmt.Println(err) return diff --git a/src/cmd/cgo/internal/testerrors/errors_test.go b/src/cmd/cgo/internal/testerrors/errors_test.go index 80d2c402cec0c2..6af7c94168a14b 100644 --- a/src/cmd/cgo/internal/testerrors/errors_test.go +++ b/src/cmd/cgo/internal/testerrors/errors_test.go @@ -72,7 +72,7 @@ func expect(t *testing.T, errors []*regexp.Regexp, files ...string) { defer os.RemoveAll(dir) dst := filepath.Join(dir, strings.TrimSuffix(files[0], ".go")) - args := []string{"build", "-gcflags=-L -e", "-o=" + dst} // TODO(gri) no need for -gcflags=-L if go tool is adjusted + args := []string{"build", "-gcflags=-e", "-o=" + dst} for _, file := range files { args = append(args, path(file)) } @@ -152,7 +152,6 @@ func TestToleratesOptimizationFlag(t *testing.T) { "", "-O", } { - cflags := cflags t.Run(cflags, func(t *testing.T) { testenv.MustHaveGoBuild(t) testenv.MustHaveCGO(t) diff --git a/src/cmd/cgo/internal/testerrors/ptr_test.go b/src/cmd/cgo/internal/testerrors/ptr_test.go index beba0d26ac1818..bc1cc1c6e08ed8 100644 --- a/src/cmd/cgo/internal/testerrors/ptr_test.go +++ b/src/cmd/cgo/internal/testerrors/ptr_test.go @@ -14,6 +14,7 @@ import ( "os" "os/exec" "path/filepath" + "regexp" "slices" "strings" "sync/atomic" @@ -24,15 +25,16 @@ var tmp = flag.String("tmp", "", "use `dir` for temporary files and do not clean // ptrTest is the tests without the boilerplate. type ptrTest struct { - name string // for reporting - c string // the cgo comment - c1 string // cgo comment forced into non-export cgo file - imports []string // a list of imports - support string // supporting functions - body string // the body of the main function - extra []extra // extra files - fail bool // whether the test should fail - expensive bool // whether the test requires the expensive check + name string // for reporting + c string // the cgo comment + c1 string // cgo comment forced into non-export cgo file + imports []string // a list of imports + support string // supporting functions + body string // the body of the main function + extra []extra // extra files + fail bool // whether the test should fail + expensive bool // whether the test requires the expensive check + errTextRegexp string // error text regexp; if empty, use the pattern `.*unpinned Go.*` } type extra struct { @@ -489,6 +491,27 @@ var ptrTests = []ptrTest{ body: `i := 0; a := &[2]unsafe.Pointer{nil, unsafe.Pointer(&i)}; C.f45(&a[0])`, fail: true, }, + { + // Passing a Go map as argument to C. + name: "argmap", + c: `void f46(void* p) {}`, + imports: []string{"unsafe"}, + body: `m := map[int]int{0: 1,}; C.f46(unsafe.Pointer(&m))`, + fail: true, + errTextRegexp: `.*argument of cgo function has Go pointer to unpinned Go map`, + }, + { + // Returning a Go map to C. + name: "retmap", + c: `extern void f47();`, + support: `//export GoMap47 + func GoMap47() map[int]int { return map[int]int{0: 1,} }`, + body: `C.f47()`, + c1: `extern void* GoMap47(); + void f47() { GoMap47(); }`, + fail: true, + errTextRegexp: `.*result of Go function GoMap47 called from cgo is unpinned Go map or points to unpinned Go map.*`, + }, } func TestPointerChecks(t *testing.T) { @@ -519,7 +542,6 @@ func TestPointerChecks(t *testing.T) { // after testOne finishes. var pending int32 for _, pt := range ptrTests { - pt := pt t.Run(pt.name, func(t *testing.T) { atomic.AddInt32(&pending, +1) defer func() { @@ -690,11 +712,17 @@ func testOne(t *testing.T, pt ptrTest, exe, exe2 string) { } buf, err := runcmd(cgocheck) + + var pattern string = pt.errTextRegexp + if pt.errTextRegexp == "" { + pattern = `.*unpinned Go.*` + } + if pt.fail { if err == nil { t.Logf("%s", buf) t.Fatalf("did not fail as expected") - } else if !bytes.Contains(buf, []byte("Go pointer")) { + } else if ok, _ := regexp.Match(pattern, buf); !ok { t.Logf("%s", buf) t.Fatalf("did not print expected error (failed with %v)", err) } diff --git a/src/cmd/cgo/internal/testfortran/fortran_test.go b/src/cmd/cgo/internal/testfortran/fortran_test.go index 9ccf916d841d66..771590e34adaa5 100644 --- a/src/cmd/cgo/internal/testfortran/fortran_test.go +++ b/src/cmd/cgo/internal/testfortran/fortran_test.go @@ -47,14 +47,19 @@ func TestFortran(t *testing.T) { switch runtime.GOOS { case "darwin": libExt = "dylib" - case "aix": + case "aix", "openbsd", "windows": libExt = "a" } - libPath, err := exec.Command(fc, append([]string{"-print-file-name=libgfortran." + libExt}, fcExtra...)...).CombinedOutput() + libName := "libgfortran." + libExt + b, err := exec.Command(fc, append([]string{"-print-file-name=" + libName}, fcExtra...)...).CombinedOutput() if err != nil { - t.Errorf("error invoking %s: %s", fc, err) + t.Fatalf("error invoking %s: %s", fc, err) } - libDir := filepath.Dir(string(libPath)) + libPath := strings.TrimSpace(string(b)) + if libPath == libName { + t.Fatalf("Failed to get full library path for %q", libName) + } + libDir := filepath.Dir(libPath) cgoLDFlags := os.Getenv("CGO_LDFLAGS") cgoLDFlags += " -L " + libDir if runtime.GOOS != "aix" { diff --git a/src/cmd/cgo/internal/testout/out_test.go b/src/cmd/cgo/internal/testout/out_test.go index e8ea5092a3562b..ff506c8cd97fbd 100644 --- a/src/cmd/cgo/internal/testout/out_test.go +++ b/src/cmd/cgo/internal/testout/out_test.go @@ -18,6 +18,32 @@ import ( "testing" ) +// TestDisallowSmuggledCode tests that +// docstrings do not smuggle code into +// files generated by Cgo. +func TestDisallowSmuggledCode(t *testing.T) { + testenv.MustHaveGoRun(t) + testenv.MustHaveCGO(t) + objDir := cgo(t, "comments.go") + + file, err := os.Open(filepath.Join(objDir, "_cgo_export.h")) + if err != nil { + t.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + for scanner.Scan() { + line := strings.TrimSpace(scanner.Text()) + if strings.Contains(line, `"Hello, I am exploiting CVE-2025-61732!\n"`) { + t.Fatalf(`got %q, want ""`, line) + } + } + if err := scanner.Err(); err != nil { + t.Fatal(err) + } +} + type methodAlign struct { Method string Align int @@ -43,23 +69,7 @@ var wantAligns = map[string]int{ func TestAligned(t *testing.T) { testenv.MustHaveGoRun(t) testenv.MustHaveCGO(t) - - testdata, err := filepath.Abs("testdata") - if err != nil { - t.Fatal(err) - } - - objDir := t.TempDir() - - cmd := testenv.Command(t, testenv.GoToolPath(t), "tool", "cgo", - "-objdir", objDir, - filepath.Join(testdata, "aligned.go")) - cmd.Stderr = new(bytes.Buffer) - - err = cmd.Run() - if err != nil { - t.Fatalf("%#q: %v\n%s", cmd, err, cmd.Stderr) - } + objDir := cgo(t, "aligned.go") haveAligns, err := parseAlign(filepath.Join(objDir, "_cgo_export.c")) if err != nil { @@ -84,6 +94,28 @@ func TestAligned(t *testing.T) { } } +// cgo executes 'go tool cgo' on testFile +// and returns the objdir containing the +// generated files. +func cgo(t *testing.T, testFile string) string { + objDir := t.TempDir() + testdata, err := filepath.Abs("testdata") + if err != nil { + t.Fatal(err) + } + + cmd := testenv.Command(t, testenv.GoToolPath(t), "tool", "cgo", + "-objdir", objDir, + filepath.Join(testdata, testFile)) + + cmd.Stderr = new(bytes.Buffer) + if err = cmd.Run(); err != nil { + t.Fatalf("%#q: %v\n%s", cmd, err, cmd.Stderr) + } + + return objDir +} + func parseAlign(filename string) ([]methodAlign, error) { file, err := os.Open(filename) if err != nil { diff --git a/src/cmd/cgo/internal/testout/testdata/comments.go b/src/cmd/cgo/internal/testout/testdata/comments.go new file mode 100644 index 00000000000000..c1fcaeea4a2f1c --- /dev/null +++ b/src/cmd/cgo/internal/testout/testdata/comments.go @@ -0,0 +1,47 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +/* +#include + +#pragma once + +extern void go_func(); + + +void print(const char *str) { + printf("%s", str); + go_func(); +} +*/ +import "C" +import "fmt" + +func main() { + str := C.CString("Hello from C\n") + C.print(str) +} + +// \ +/* + +#ifndef AUTO_PRINT_H +#define AUTO_PRINT_H + +#include + +__attribute__((constructor)) +static void inject(void) { + printf("Hello, I am exploiting CVE-2025-61732!\n"); +} + +#endif + +/* */ +//export go_func +func go_func() { + fmt.Println("Hello from Go") +} diff --git a/src/cmd/cgo/internal/testplugin/plugin_test.go b/src/cmd/cgo/internal/testplugin/plugin_test.go index 2afb542ec4f17c..4f0458b7dee472 100644 --- a/src/cmd/cgo/internal/testplugin/plugin_test.go +++ b/src/cmd/cgo/internal/testplugin/plugin_test.go @@ -37,7 +37,7 @@ func TestMain(m *testing.M) { var tmpDir string // prettyPrintf prints lines with tmpDir sanitized. -func prettyPrintf(format string, args ...interface{}) { +func prettyPrintf(format string, args ...any) { s := fmt.Sprintf(format, args...) if tmpDir != "" { s = strings.ReplaceAll(s, tmpDir, "$TMPDIR") @@ -430,3 +430,14 @@ func TestIssue75102(t *testing.T) { goCmd(t, "build", "-o", "issue75102.exe", "./issue75102/main.go") run(t, "./issue75102.exe") } + +func TestIssue81303(t *testing.T) { + // Issue 81303: the itab copies of a plugin must not hide the itabs + // of the host for the same interface/type pairs. + globalSkip(t) + goCmd(t, "build", "-buildmode=plugin", "-o", "issue81303p1.so", "./issue81303/plugin1.go") + goCmd(t, "build", "-buildmode=plugin", "-o", "issue81303p2.so", "./issue81303/plugin2.go") + goCmd(t, "build", "-buildmode=plugin", "-o", "issue81303p3.so", "./issue81303/plugin3.go") + goCmd(t, "build", "-o", "issue81303.exe", "./issue81303/main.go") + run(t, "./issue81303.exe") +} diff --git a/src/cmd/cgo/internal/testplugin/testdata/issue81303/main.go b/src/cmd/cgo/internal/testplugin/testdata/issue81303/main.go new file mode 100644 index 00000000000000..7b2ea1595f18ac --- /dev/null +++ b/src/cmd/cgo/internal/testplugin/testdata/issue81303/main.go @@ -0,0 +1,39 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Issue 81303: a plugin has its own copies of the itabs of the host. +// The runtime added these copies to the itab table as second entries +// for the same interface/type pairs. After the table grew, a lookup +// could return the copy from the plugin. A type switch compares the +// itab with the itab of the host, so it took the default case. +// +// Each plugin imports package p, which uses go/ast, so each plugin +// adds a copy of every go/ast itab of the host. The host walks a +// syntax tree before and after each plugin loads. The three plugins +// are the same because plugin.Open loads a plugin path only once. + +package main + +import ( + "log" + "plugin" + + "testplugin/issue81303/p" +) + +func main() { + p.Walk() + for _, name := range []string{"issue81303p1.so", "issue81303p2.so", "issue81303p3.so"} { + pl, err := plugin.Open(name) + if err != nil { + log.Fatal(err) + } + f, err := pl.Lookup("F") + if err != nil { + log.Fatal(err) + } + f.(func())() + p.Walk() + } +} diff --git a/src/cmd/cgo/internal/testplugin/testdata/issue81303/p/p.go b/src/cmd/cgo/internal/testplugin/testdata/issue81303/p/p.go new file mode 100644 index 00000000000000..960d35e4376d5d --- /dev/null +++ b/src/cmd/cgo/internal/testplugin/testdata/issue81303/p/p.go @@ -0,0 +1,48 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package p + +import ( + "go/ast" + "go/parser" + "go/token" + "log" +) + +const src = `package p + +import "fmt" + +type T struct{ x int } + +func (t *T) M(n int) (r int) { + defer func() { r++ }() + go fmt.Println(n) + if n > 0 { + r = n + } else { + r = -n + } + for i := 0; i < n; i++ { + r += t.x + } + switch v := any(n).(type) { + case int: + r = v + } + return +} +` + +// Walk parses src and walks the syntax tree. ast.Walk converts each +// node to ast.Node, which looks up the itab in the itab table, and +// then compares that itab with the itab of the host in a type switch. +func Walk() { + f, err := parser.ParseFile(token.NewFileSet(), "src.go", src, parser.SkipObjectResolution) + if err != nil { + log.Fatal(err) + } + ast.Inspect(f, func(ast.Node) bool { return true }) +} diff --git a/src/cmd/cgo/internal/testplugin/testdata/issue81303/plugin1.go b/src/cmd/cgo/internal/testplugin/testdata/issue81303/plugin1.go new file mode 100644 index 00000000000000..c97a98583684ea --- /dev/null +++ b/src/cmd/cgo/internal/testplugin/testdata/issue81303/plugin1.go @@ -0,0 +1,11 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import "testplugin/issue81303/p" + +func main() {} + +func F() { p.Walk() } diff --git a/src/cmd/cgo/internal/testplugin/testdata/issue81303/plugin2.go b/src/cmd/cgo/internal/testplugin/testdata/issue81303/plugin2.go new file mode 100644 index 00000000000000..c97a98583684ea --- /dev/null +++ b/src/cmd/cgo/internal/testplugin/testdata/issue81303/plugin2.go @@ -0,0 +1,11 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import "testplugin/issue81303/p" + +func main() {} + +func F() { p.Walk() } diff --git a/src/cmd/cgo/internal/testplugin/testdata/issue81303/plugin3.go b/src/cmd/cgo/internal/testplugin/testdata/issue81303/plugin3.go new file mode 100644 index 00000000000000..c97a98583684ea --- /dev/null +++ b/src/cmd/cgo/internal/testplugin/testdata/issue81303/plugin3.go @@ -0,0 +1,11 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import "testplugin/issue81303/p" + +func main() {} + +func F() { p.Walk() } diff --git a/src/cmd/cgo/internal/testsanitizers/asan_test.go b/src/cmd/cgo/internal/testsanitizers/asan_test.go index cb7d857280416f..a2d420402018e7 100644 --- a/src/cmd/cgo/internal/testsanitizers/asan_test.go +++ b/src/cmd/cgo/internal/testsanitizers/asan_test.go @@ -48,7 +48,6 @@ func TestASAN(t *testing.T) { {src: "arena_fail.go", memoryAccessError: "use-after-poison", errorLocation: "arena_fail.go:26", experiments: []string{"arenas"}}, } for _, tc := range cases { - tc := tc name := strings.TrimSuffix(tc.src, ".go") t.Run(name, func(t *testing.T) { t.Parallel() diff --git a/src/cmd/cgo/internal/testsanitizers/cc_test.go b/src/cmd/cgo/internal/testsanitizers/cc_test.go index f2239fb9cffc2e..cfd670585637b2 100644 --- a/src/cmd/cgo/internal/testsanitizers/cc_test.go +++ b/src/cmd/cgo/internal/testsanitizers/cc_test.go @@ -13,6 +13,7 @@ package sanitizers_test import ( "bytes" + "context" "encoding/json" "errors" "fmt" @@ -110,6 +111,24 @@ func appendExperimentEnv(cmd *exec.Cmd, experiments []string) { cmd.Env = append(cmd.Env, "GOEXPERIMENT="+exps) } +func appendASANOptions(cmd *exec.Cmd, opts ...string) { + if cmd.Env == nil { + cmd.Env = cmd.Environ() + } + var asanOptions string + for _, evar := range cmd.Env { + name, value, ok := strings.Cut(evar, "=") + if ok && name == "ASAN_OPTIONS" { + asanOptions = value + } + } + if asanOptions != "" { + asanOptions += ":" + } + asanOptions += strings.Join(opts, ":") + cmd.Env = append(cmd.Env, "ASAN_OPTIONS="+asanOptions) +} + // mustRun executes t and fails cmd with a well-formatted message if it fails. func mustRun(t *testing.T, cmd *exec.Cmd) { t.Helper() @@ -137,7 +156,7 @@ func mustRun(t *testing.T, cmd *exec.Cmd) { } // cc returns a cmd that executes `$(go env CC) $(go env GOGCCFLAGS) $args`. -func cc(args ...string) (*exec.Cmd, error) { +func cc(ctx context.Context, args ...string) (*exec.Cmd, error) { CC, err := goEnv("CC") if err != nil { return nil, err @@ -186,7 +205,7 @@ func cc(args ...string) (*exec.Cmd, error) { flags = append(flags, GOGCCFLAGS[start:]) } - cmd := exec.Command(CC, flags...) + cmd := exec.CommandContext(ctx, CC, flags...) cmd.Args = append(cmd.Args, args...) return cmd, nil } @@ -211,7 +230,7 @@ func compilerVersion() (version, error) { compiler.err = func() error { compiler.name = "unknown" - cmd, err := cc("--version") + cmd, err := cc(context.Background(), "--version") if err != nil { return err } @@ -224,7 +243,7 @@ func compilerVersion() (version, error) { var match [][]byte if bytes.HasPrefix(out, []byte("gcc")) { compiler.name = "gcc" - cmd, err := cc("-dumpfullversion", "-dumpversion") + cmd, err := cc(context.Background(), "-dumpfullversion", "-dumpversion") if err != nil { return err } @@ -464,6 +483,11 @@ int LLVMFuzzerTestOneInput(char *data, size_t size) { `) func (c *config) checkCSanitizer() (skip bool, err error) { + // The sanitizer probes compile and run tiny C programs. If either step + // takes longer than this, treat the C sanitizer configuration as broken + // instead of letting the package-level test timeout fire. + probeTimeout := 20 * time.Second + dir, err := os.MkdirTemp("", c.sanitizer) if err != nil { return false, fmt.Errorf("failed to create temp directory: %v", err) @@ -481,14 +505,26 @@ func (c *config) checkCSanitizer() (skip bool, err error) { } dst := filepath.Join(dir, "return0") - cmd, err := cc(c.cFlags...) + compileCtx, cancelCompile := context.WithTimeout(context.Background(), probeTimeout) + defer cancelCompile() + cmd, err := cc(compileCtx, c.cFlags...) if err != nil { return false, err } cmd.Args = append(cmd.Args, c.ldFlags...) cmd.Args = append(cmd.Args, "-o", dst, src) + if c.sanitizer == "address" { + // This is only a compiler support probe for ASAN. Some libasan versions + // run a slow LeakSanitizer check at exit even for this no-op C program, + // which can hang TestASAN before it starts testing Go binaries. + appendASANOptions(cmd, "leak_check_at_exit=0") + } + makeHangProne(cmd) out, err := cmd.CombinedOutput() if err != nil { + if errors.Is(compileCtx.Err(), context.DeadlineExceeded) { + return true, fmt.Errorf("%#q timed out after %v", cmd, probeTimeout) + } if bytes.Contains(out, []byte("-fsanitize")) && (bytes.Contains(out, []byte("unrecognized")) || bytes.Contains(out, []byte("unsupported"))) { @@ -502,7 +538,20 @@ func (c *config) checkCSanitizer() (skip bool, err error) { return false, nil } - if out, err := exec.Command(dst).CombinedOutput(); err != nil { + runCtx, cancelRun := context.WithTimeout(context.Background(), probeTimeout) + defer cancelRun() + cmd = exec.CommandContext(runCtx, dst) + makeHangProne(cmd) + if c.sanitizer == "address" { + // Match the compile-time probe above: avoid libasan's implicit LSan exit + // scan for this standalone C binary. The explicit LSAN tests still run + // with leak checking enabled. + appendASANOptions(cmd, "leak_check_at_exit=0") + } + if out, err := cmd.CombinedOutput(); err != nil { + if errors.Is(runCtx.Err(), context.DeadlineExceeded) { + return true, fmt.Errorf("%#q timed out after %v", cmd, probeTimeout) + } if os.IsNotExist(err) { return true, fmt.Errorf("%#q failed to produce executable: %v", cmd, err) } @@ -537,7 +586,7 @@ func (c *config) checkRuntime() (skip bool, err error) { // libcgo.h sets CGO_TSAN if it detects TSAN support in the C compiler. // Dump the preprocessor defines to check that works. // (Sometimes it doesn't: see https://golang.org/issue/15983.) - cmd, err := cc(c.cFlags...) + cmd, err := cc(context.Background(), c.cFlags...) if err != nil { return false, err } @@ -594,8 +643,14 @@ func newTempDir(t *testing.T) *tempDir { // leak. func hangProneCmd(name string, arg ...string) *exec.Cmd { cmd := exec.Command(name, arg...) + makeHangProne(cmd) + return cmd +} + +// makeHangProne configures cmd to receive SIGKILL when the parent process receives SIGINT. +// See [hangProneCmd] for details. +func makeHangProne(cmd *exec.Cmd) { cmd.SysProcAttr = &syscall.SysProcAttr{ Pdeathsig: syscall.SIGKILL, } - return cmd } diff --git a/src/cmd/cgo/internal/testsanitizers/cshared_test.go b/src/cmd/cgo/internal/testsanitizers/cshared_test.go index 0cf094ead79e66..76559679a00542 100644 --- a/src/cmd/cgo/internal/testsanitizers/cshared_test.go +++ b/src/cmd/cgo/internal/testsanitizers/cshared_test.go @@ -54,7 +54,6 @@ func TestShared(t *testing.T) { } for _, tc := range cases { - tc := tc name := strings.TrimSuffix(tc.src, ".go") //The memory sanitizer tests require support for the -msan option. if tc.sanitizer == "memory" && !platform.MSanSupported(GOOS, GOARCH) { @@ -83,7 +82,7 @@ func TestShared(t *testing.T) { } dstBin := dir.Join(name) - cmd, err := cc(config.cFlags...) + cmd, err := cc(t.Context(), config.cFlags...) if err != nil { t.Fatal(err) } diff --git a/src/cmd/cgo/internal/testsanitizers/libfuzzer_test.go b/src/cmd/cgo/internal/testsanitizers/libfuzzer_test.go index 9f548d66eace03..b53c6aafcc1b7f 100644 --- a/src/cmd/cgo/internal/testsanitizers/libfuzzer_test.go +++ b/src/cmd/cgo/internal/testsanitizers/libfuzzer_test.go @@ -43,7 +43,6 @@ func TestLibFuzzer(t *testing.T) { {goSrc: "libfuzzer2.go", cSrc: "libfuzzer2.c", expectedError: "panic: found it"}, } for _, tc := range cases { - tc := tc name := strings.TrimSuffix(tc.goSrc, ".go") t.Run(name, func(t *testing.T) { t.Parallel() @@ -57,7 +56,7 @@ func TestLibFuzzer(t *testing.T) { mustRun(t, config.goCmd("build", "-buildmode=c-archive", "-o", archivePath, srcPath(tc.goSrc))) // build C code (if any) and link with Go code - cmd, err := cc(config.cFlags...) + cmd, err := cc(t.Context(), config.cFlags...) if err != nil { t.Fatalf("error running cc: %v", err) } diff --git a/src/cmd/cgo/internal/testsanitizers/msan_test.go b/src/cmd/cgo/internal/testsanitizers/msan_test.go index 554cceaff88669..811a1438397eb0 100644 --- a/src/cmd/cgo/internal/testsanitizers/msan_test.go +++ b/src/cmd/cgo/internal/testsanitizers/msan_test.go @@ -62,7 +62,6 @@ func TestMSAN(t *testing.T) { {src: "arena_fail.go", wantErr: true, experiments: []string{"arenas"}}, } for _, tc := range cases { - tc := tc name := strings.TrimSuffix(tc.src, ".go") t.Run(name, func(t *testing.T) { t.Parallel() diff --git a/src/cmd/cgo/internal/testsanitizers/tsan_test.go b/src/cmd/cgo/internal/testsanitizers/tsan_test.go index 589db2e6bc4e34..81fc00900f9e37 100644 --- a/src/cmd/cgo/internal/testsanitizers/tsan_test.go +++ b/src/cmd/cgo/internal/testsanitizers/tsan_test.go @@ -59,7 +59,6 @@ func TestTSAN(t *testing.T) { {src: "tsan_tracebackctxt", needsRuntime: true}, // Subdirectory } for _, tc := range cases { - tc := tc name := strings.TrimSuffix(tc.src, ".go") t.Run(name, func(t *testing.T) { t.Parallel() diff --git a/src/cmd/cgo/internal/testshared/shared_test.go b/src/cmd/cgo/internal/testshared/shared_test.go index 3d401b604ebbba..f785f423ac36fd 100644 --- a/src/cmd/cgo/internal/testshared/shared_test.go +++ b/src/cmd/cgo/internal/testshared/shared_test.go @@ -1175,10 +1175,10 @@ func TestStd(t *testing.T) { tmpDir := t.TempDir() // Use a temporary pkgdir to not interfere with other tests, and not write to GOROOT. // Cannot use goCmd as it runs with cloned GOROOT which is incomplete. - runWithEnv(t, "building std", []string{"GOROOT=" + oldGOROOT}, + runWithEnv(t, "building std", []string{"GOROOT=" + oldGOROOT, "GOEXPERIMENT=nosimd"}, filepath.Join(oldGOROOT, "bin", "go"), "install", "-buildmode=shared", "-pkgdir="+tmpDir, "std") // Issue #58966. - runWithEnv(t, "testing issue #58966", []string{"GOROOT=" + oldGOROOT}, + runWithEnv(t, "testing issue #58966", []string{"GOROOT=" + oldGOROOT, "GOEXPERIMENT=nosimd"}, filepath.Join(oldGOROOT, "bin", "go"), "run", "-linkshared", "-pkgdir="+tmpDir, "./issue58966/main.go") } diff --git a/src/cmd/cgo/internal/teststdio/stdio_test.go b/src/cmd/cgo/internal/teststdio/stdio_test.go index 9150281ae87ff3..f9e7fe507989f4 100644 --- a/src/cmd/cgo/internal/teststdio/stdio_test.go +++ b/src/cmd/cgo/internal/teststdio/stdio_test.go @@ -56,7 +56,6 @@ func TestTestRun(t *testing.T) { "fib.go", "hello.go", } { - file := file wantFile := strings.Replace(file, ".go", ".out", 1) t.Run(file, func(t *testing.T) { cmd := exec.Command(testenv.GoToolPath(t), "run", file) diff --git a/src/cmd/cgo/internal/teststdio/testdata/fib.go b/src/cmd/cgo/internal/teststdio/testdata/fib.go index 96173683353151..69147880c20df2 100644 --- a/src/cmd/cgo/internal/teststdio/testdata/fib.go +++ b/src/cmd/cgo/internal/teststdio/testdata/fib.go @@ -5,7 +5,7 @@ //go:build test_run // Compute Fibonacci numbers with two goroutines -// that pass integers back and forth. No actual +// that pass integers back and forth. No actual // concurrency, just threads and synchronization // and foreign code on multiple pthreads. diff --git a/src/cmd/cgo/main.go b/src/cmd/cgo/main.go index 5e08427daf9cc2..452840a4cfbb19 100644 --- a/src/cmd/cgo/main.go +++ b/src/cmd/cgo/main.go @@ -72,8 +72,8 @@ type File struct { ExpFunc []*ExpFunc // exported functions for this file Name map[string]*Name // map from Go name to Name NamePos map[*Name]token.Pos // map from Name to position of the first reference - NoCallbacks map[string]bool // C function names that with #cgo nocallback directive - NoEscapes map[string]bool // C function names that with #cgo noescape directive + NoCallbacks map[string]bool // C function names with #cgo nocallback directive + NoEscapes map[string]bool // C function names with #cgo noescape directive Edit *edit.Buffer debugs []*debug // debug data from iterations of gccDebug. Initialized by File.loadDebug. @@ -148,7 +148,7 @@ type ExpFunc struct { // A TypeRepr contains the string representation of a type. type TypeRepr struct { Repr string - FormatArgs []interface{} + FormatArgs []any } // A Type collects information about a type in both the C and Go worlds. @@ -320,6 +320,10 @@ func main() { conf.Mode &^= printer.SourcePos } + if *objDir == "" { + *objDir = "_obj" + } + args := flag.Args() if len(args) < 1 { usage() @@ -446,14 +450,6 @@ func main() { cPrefix = fmt.Sprintf("_%x", h.Sum(nil)[0:6]) - if *objDir == "" { - *objDir = "_obj" - } - // make sure that `objDir` directory exists, so that we can write - // all the output files there. - os.MkdirAll(*objDir, 0o700) - *objDir += string(filepath.Separator) - for i, input := range goFiles { f := fs[i] p.Translate(f) diff --git a/src/cmd/cgo/out.go b/src/cmd/cgo/out.go index a2bcdf89c5ad44..151000f5813c3d 100644 --- a/src/cmd/cgo/out.go +++ b/src/cmd/cgo/out.go @@ -33,15 +33,15 @@ var ( // writeDefs creates output files to be compiled by gc and gcc. func (p *Package) writeDefs() { var fgo2, fc io.Writer - f := creat(*objDir + "_cgo_gotypes.go") + f := creat("_cgo_gotypes.go") defer f.Close() fgo2 = f if *gccgo { - f := creat(*objDir + "_cgo_defun.c") + f := creat("_cgo_defun.c") defer f.Close() fc = f } - fm := creat(*objDir + "_cgo_main.c") + fm := creat("_cgo_main.c") var gccgoInit strings.Builder @@ -50,7 +50,7 @@ func (p *Package) writeDefs() { fmt.Fprintf(fgo2, "//go:cgo_ldflag %q\n", arg) } } else { - fflg := creat(*objDir + "_cgo_flags") + fflg := creat("_cgo_flags") for _, arg := range p.LdFlags { fmt.Fprintf(fflg, "_CGO_LDFLAGS=%s\n", arg) } @@ -242,8 +242,8 @@ func (p *Package) writeDefs() { } } - fgcc := creat(*objDir + "_cgo_export.c") - fgcch := creat(*objDir + "_cgo_export.h") + fgcc := creat("_cgo_export.c") + fgcch := creat("_cgo_export.h") if *gccgo { p.writeGccgoExports(fgo2, fm, fgcc, fgcch) } else { @@ -263,8 +263,11 @@ func (p *Package) writeDefs() { } if *exportHeader != "" && len(p.ExpFunc) > 0 { - fexp := creat(*exportHeader) - fgcch, err := os.Open(*objDir + "_cgo_export.h") + fexp, err := os.Create(*exportHeader) + if err != nil { + fatalf("%s", err) + } + fgcch, err := os.Open(filepath.Join(outputDir(), "_cgo_export.h")) if err != nil { fatalf("%s", err) } @@ -457,6 +460,36 @@ func checkImportSymName(s string) { // Also assumes that gc convention is to word-align the // input and output parameters. func (p *Package) structType(n *Name) (string, int64) { + // It's possible for us to see a type with a top-level const here, + // which will give us an unusable struct type. See #75751. + // The top-level const will always appear as a final qualifier, + // constructed by typeConv.loadType in the dwarf.QualType case. + // The top-level const is meaningless here and can simply be removed. + stripConst := func(s string) string { + i := strings.LastIndex(s, "const") + if i == -1 { + return s + } + + // A top-level const can only be followed by other qualifiers. + if r, ok := strings.CutSuffix(s, "const"); ok { + return strings.TrimSpace(r) + } + + var nonConst []string + for _, f := range strings.Fields(s[i:]) { + switch f { + case "const": + case "restrict", "volatile": + nonConst = append(nonConst, f) + default: + return s + } + } + + return strings.TrimSpace(s[:i]) + " " + strings.Join(nonConst, " ") + } + var buf strings.Builder fmt.Fprint(&buf, "struct {\n") off := int64(0) @@ -468,7 +501,7 @@ func (p *Package) structType(n *Name) (string, int64) { } c := t.Typedef if c == "" { - c = t.C.String() + c = stripConst(t.C.String()) } fmt.Fprintf(&buf, "\t\t%s p%d;\n", c, i) off += t.Size @@ -484,7 +517,7 @@ func (p *Package) structType(n *Name) (string, int64) { fmt.Fprintf(&buf, "\t\tchar __pad%d[%d];\n", off, pad) off += pad } - fmt.Fprintf(&buf, "\t\t%s r;\n", t.C) + fmt.Fprintf(&buf, "\t\t%s r;\n", stripConst(t.C.String())) off += t.Size } if off%p.PtrSize != 0 { @@ -649,13 +682,15 @@ func (p *Package) writeDefsFunc(fgo2 io.Writer, n *Name, callsMalloc *bool) { if p.noEscapes[n.C] && p.noCallbacks[n.C] { touchFunc = "_Cgo_keepalive" } - fmt.Fprintf(fgo2, "\tif _Cgo_always_false {\n") - if d.Type.Params != nil { + + if len(paramnames) > 0 { + fmt.Fprintf(fgo2, "\tif _Cgo_always_false {\n") for _, name := range paramnames { fmt.Fprintf(fgo2, "\t\t%s(%s)\n", touchFunc, name) } + fmt.Fprintf(fgo2, "\t}\n") } - fmt.Fprintf(fgo2, "\t}\n") + fmt.Fprintf(fgo2, "\treturn\n") fmt.Fprintf(fgo2, "}\n") } @@ -665,8 +700,8 @@ func (p *Package) writeOutput(f *File, srcfile string) { base := srcfile base = strings.TrimSuffix(base, ".go") base = filepath.Base(base) - fgo1 := creat(*objDir + base + ".cgo1.go") - fgcc := creat(*objDir + base + ".cgo2.c") + fgo1 := creat(base + ".cgo1.go") + fgcc := creat(base + ".cgo2.c") p.GoFiles = append(p.GoFiles, base+".cgo1.go") p.GccFiles = append(p.GccFiles, base+".cgo2.c") @@ -751,13 +786,13 @@ func (p *Package) writeOutputFunc(fgcc *os.File, n *Name) { // We're trying to write a gcc struct that matches gc's layout. // Use packed attribute to force no padding in this struct in case // gcc has different packing requirements. - fmt.Fprintf(fgcc, "\t%s %v *_cgo_a = v;\n", ctype, p.packedAttribute()) - if n.FuncType.Result != nil { - // Save the stack top for use below. - fmt.Fprintf(fgcc, "\tchar *_cgo_stktop = _cgo_topofstack();\n") - } tr := n.FuncType.Result + if (n.Kind != "macro" && len(n.FuncType.Params) > 0) || tr != nil { + fmt.Fprintf(fgcc, "\t%s %v *_cgo_a = v;\n", ctype, p.packedAttribute()) + } if tr != nil { + // Save the stack top for use below. + fmt.Fprintf(fgcc, "\tchar *_cgo_stktop = _cgo_topofstack();\n") fmt.Fprintf(fgcc, "\t__typeof__(_cgo_a->r) _cgo_r;\n") } fmt.Fprintf(fgcc, "\t_cgo_tsan_acquire();\n") @@ -787,7 +822,7 @@ func (p *Package) writeOutputFunc(fgcc *os.File, n *Name) { fmt.Fprintf(fgcc, "\t_cgo_errno = errno;\n") } fmt.Fprintf(fgcc, "\t_cgo_tsan_release();\n") - if n.FuncType.Result != nil { + if tr != nil { // The cgo call may have caused a stack copy (via a callback). // Adjust the return value pointer appropriately. fmt.Fprintf(fgcc, "\t_cgo_a = (void*)((char*)_cgo_a + (_cgo_topofstack() - _cgo_stktop));\n") @@ -951,7 +986,7 @@ func (p *Package) writeExports(fgo2, fm, fgcc, fgcch io.Writer) { npad := 0 // the align is at least 1 (for char) maxAlign := int64(1) - argField := func(typ ast.Expr, namePat string, args ...interface{}) { + argField := func(typ ast.Expr, namePat string, args ...any) { name := fmt.Sprintf(namePat, args...) t := p.cgoType(typ) if off%t.Align != 0 { @@ -1144,6 +1179,10 @@ func (p *Package) writeExports(fgo2, fm, fgcc, fgcch io.Writer) { if !p.hasPointer(nil, atype, false) { return } + + // Use the export'ed file/line in error messages. + pos := fset.Position(exp.Func.Pos()) + fmt.Fprintf(fgo2, "//line %s:%d\n", pos.Filename, pos.Line) fmt.Fprintf(fgo2, "\t_cgoCheckResult(a.r%d)\n", i) }) } @@ -1359,7 +1398,7 @@ func gccgoToSymbol(ppath string) string { fatalf("unable to locate gccgo: %v", err) } } - gccgoMangler, err = pkgpath.ToSymbolFunc(cmd, *objDir) + gccgoMangler, err = pkgpath.ToSymbolFunc(cmd, outputDir()) if err != nil { fatalf("%v", err) } @@ -1406,7 +1445,7 @@ func forFieldList(fl *ast.FieldList, fn func(int, string, ast.Expr)) { } } -func c(repr string, args ...interface{}) *TypeRepr { +func c(repr string, args ...any) *TypeRepr { return &TypeRepr{repr, args} } @@ -1522,6 +1561,9 @@ func (p *Package) doCgoType(e ast.Expr, m map[ast.Expr]bool) *Type { if t.Name == "error" { return &Type{Size: 2 * p.PtrSize, Align: p.PtrSize, C: c("GoInterface")} } + if t.Name == "any" { + return &Type{Size: 2 * p.PtrSize, Align: p.PtrSize, C: c("GoInterface")} + } if r, ok := goTypes[t.Name]; ok { return goTypesFixup(r) } diff --git a/src/cmd/cgo/util.go b/src/cmd/cgo/util.go index 23b4a414db7562..bf34d61e902dca 100644 --- a/src/cmd/cgo/util.go +++ b/src/cmd/cgo/util.go @@ -10,6 +10,7 @@ import ( "go/token" "os" "os/exec" + "path/filepath" "slices" ) @@ -75,7 +76,7 @@ func lineno(pos token.Pos) string { } // Die with an error message. -func fatalf(msg string, args ...interface{}) { +func fatalf(msg string, args ...any) { // If we've already printed other errors, they might have // caused the fatal condition. Assume they're enough. if nerrors == 0 { @@ -86,7 +87,7 @@ func fatalf(msg string, args ...interface{}) { var nerrors int -func error_(pos token.Pos, msg string, args ...interface{}) { +func error_(pos token.Pos, msg string, args ...any) { nerrors++ if pos.IsValid() { fmt.Fprintf(os.Stderr, "%s: ", fset.Position(pos).String()) @@ -97,10 +98,17 @@ func error_(pos token.Pos, msg string, args ...interface{}) { fmt.Fprintf(os.Stderr, "\n") } +// create creates a file in the output directory. func creat(name string) *os.File { - f, err := os.Create(name) + f, err := os.Create(filepath.Join(outputDir(), name)) if err != nil { fatalf("%s", err) } return f } + +// outputDir returns the output directory, making sure that it exists. +func outputDir() string { + os.MkdirAll(*objDir, 0o700) + return *objDir +} diff --git a/src/cmd/compile/README.md b/src/cmd/compile/README.md index 02429d5688659e..de667e60e37f2e 100644 --- a/src/cmd/compile/README.md +++ b/src/cmd/compile/README.md @@ -157,7 +157,8 @@ The format of the export data file has gone through a number of iterations. Its current form is called "unified", and it is a serialized representation of an object graph, with an index allowing lazy decoding of parts of the whole (since most imports are used to -provide only a handful of symbols). +provide only a handful of symbols). See [here](internal/noder/README.md) +for details on making changes to unified IR. The GOROOT repository contains a reader and a writer for the unified format; it encodes from/decodes to the compiler's IR. diff --git a/src/cmd/compile/abi-internal.md b/src/cmd/compile/abi-internal.md index eae230dc070d86..535acedd84b4ea 100644 --- a/src/cmd/compile/abi-internal.md +++ b/src/cmd/compile/abi-internal.md @@ -643,8 +643,6 @@ Registers R20 - R21, R23 – R28, R30 - R31, F16 – F31 are permanent scratch r Register R2 is reserved and never used. -Register R20, R21 is Used by runtime.duffcopy, runtime.duffzero. - Special-purpose registers used within Go generated code and Go assembly code are as follows: @@ -653,7 +651,6 @@ are as follows: | R0 | Zero value | Same | Same | | R1 | Link register | Link register | Scratch | | R3 | Stack pointer | Same | Same | -| R20,R21 | Scratch | Scratch | Used by duffcopy, duffzero | | R22 | Current goroutine | Same | Same | | R29 | Closure context pointer | Same | Same | | R30, R31 | used by the assembler | Same | Same | @@ -799,17 +796,15 @@ assembly code are as follows: | X2 | Stack pointer | Same | Same | | X3 | Global pointer | Same | Used by dynamic linker | | X4 | TLS (thread pointer) | TLS | Scratch | -| X24,X25 | Scratch | Scratch | Used by duffcopy, duffzero | | X26 | Closure context pointer | Scratch | Scratch | | X27 | Current goroutine | Same | Same | | X31 | Scratch | Scratch | Scratch | *Rationale*: These register meanings are compatible with Go’s -stack-based calling convention. Context register X20 will change to X26, -duffcopy, duffzero register will change to X24, X25 before this register ABI been adopted. +stack-based calling convention. X10 – X17, X8, X9, X18 – X23, is the same order as A0 – A7, S0 – S7 in platform ABI. F10 – F17, F8, F9, F18 – F23, is the same order as FA0 – FA7, FS0 – FS7 in platform ABI. -X8 – X23, F8 – F15 are used for compressed instruction (RVC) which will benefit code size in the future. +X8 – X23, F8 – F15 are used for compressed instruction (RVC) which benefits code size. #### Stack layout @@ -833,6 +828,51 @@ The riscv64 has Zicsr extension for control and status register (CSR) and treated as scratch register. All bits in CSR are system flags and are not modified by Go. +### s390x architecture + +The s390x architecture uses R2 – R9 for integer arguments and integer results. + +It uses F0 – F15 for floating-point arguments and results. + +Special-purpose registers used within Go generated code and Go assembly code +are as follows: + +| Register | Call meaning | Return meaning | Body meaning | +| --- | --- | --- | --- | +| R0 | Zero value | Same | Same | +| R1 | Scratch | Scratch | Scratch | +| R10, R11 | used by the assembler | Same | Same | +| R12 | Closure context pointer | Same | Same | +| R13 | Current goroutine | Same | Same | +| R14 | Link register | Link register | Scratch | +| R15 | Stack pointer | Same | Same | + +*Rationale*: These register meanings are compatible with Go’s stack-based +calling convention. + +#### Stack layout + +The stack pointer, R15, grows down and is aligned to 8 bytes. + +A function's stack frame, after the frame is created, is laid out as +follows: + + +------------------------------+ + | ... locals ... | + | ... outgoing arguments ... | + | return PC | ← R15 points to + +------------------------------+ ↓ lower addresses + +This stack layout is used by both register-based (ABIInternal) and +stack-based (ABI0) calling conventions. + +The "return PC" is loaded to the link register R14, as part of the +s390x `BL` operation. + +#### Flags +The s390x architecture maintains a single condition code (CC) field in the Program Status Word (PSW). +Go-generated code sets and tests this condition code to control conditional branches. + ## Future directions ### Spill path improvements diff --git a/src/cmd/compile/default.pgo b/src/cmd/compile/default.pgo index 2c2588704f3f6e..06e63b47811f70 100644 Binary files a/src/cmd/compile/default.pgo and b/src/cmd/compile/default.pgo differ diff --git a/src/cmd/compile/doc.go b/src/cmd/compile/doc.go index 81e6189a262381..dee509218965f8 100644 --- a/src/cmd/compile/doc.go +++ b/src/cmd/compile/doc.go @@ -198,9 +198,15 @@ all other compiler directives are of the form // is peeled off the same way if it is valid. Anything before that is considered the filename // (possibly including blanks and colons). Invalid line or column values are reported as errors. // +// A relative filename is interpreted relative to the directory of the file +// containing the directive. Absolute filenames are used as given. A filename +// inherited from a previous directive (the empty-filename form //line :line:col) +// is reused verbatim and is not re-resolved. +// // Examples: // -// //line foo.go:10 the filename is foo.go, and the line number is 10 for the next line +// //line foo.go:10 the (relative) filename is foo.go, and the line number is 10 for the next line +// //line ../foo.go:10 relative filenames are resolved against the directive's source directory // //line C:foo.go:10 colons are permitted in filenames, here the filename is C:foo.go, and the line is 10 // //line a:100 :10 blanks are permitted in filenames, here the filename is " a:100 " (excluding quotes) // /*line :10:20*/x the position of x is in the current file with line number 10 and column number 20 diff --git a/src/cmd/compile/internal/abi/abiutils.go b/src/cmd/compile/internal/abi/abiutils.go index dacaad3f300833..0e1cf88757ea21 100644 --- a/src/cmd/compile/internal/abi/abiutils.go +++ b/src/cmd/compile/internal/abi/abiutils.go @@ -150,12 +150,12 @@ func appendParamTypes(rts []*types.Type, t *types.Type) []*types.Type { if w == 0 { return rts } - if t.IsScalar() || t.IsPtrShaped() { + if t.IsScalar() || t.IsPtrShaped() || t.IsSIMD() { if t.IsComplex() { c := types.FloatForComplex(t) return append(rts, c, c) } else { - if int(t.Size()) <= types.RegSize { + if int(t.Size()) <= types.RegSize || t.IsSIMD() { return append(rts, t) } // assume 64bit int on 32-bit machine @@ -199,6 +199,9 @@ func appendParamOffsets(offsets []int64, at int64, t *types.Type) ([]int64, int6 if w == 0 { return offsets, at } + if t.IsSIMD() { + return append(offsets, at), at + w + } if t.IsScalar() || t.IsPtrShaped() { if t.IsComplex() || int(t.Size()) > types.RegSize { // complex and *int64 on 32-bit s := w / 2 @@ -275,13 +278,6 @@ func NewABIConfig(iRegsCount, fRegsCount int, offsetForLocals int64, which uint8 return &ABIConfig{offsetForLocals: offsetForLocals, regAmounts: RegAmounts{iRegsCount, fRegsCount}, which: obj.ABI(which)} } -// Copy returns config. -// -// TODO(mdempsky): Remove. -func (config *ABIConfig) Copy() *ABIConfig { - return config -} - // Which returns the ABI number func (config *ABIConfig) Which() obj.ABI { return config.which @@ -521,11 +517,11 @@ func (state *assignState) allocateRegs(regs []RegIndex, t *types.Type) []RegInde } ri := state.rUsed.intRegs rf := state.rUsed.floatRegs - if t.IsScalar() || t.IsPtrShaped() { + if t.IsScalar() || t.IsPtrShaped() || t.IsSIMD() { if t.IsComplex() { regs = append(regs, RegIndex(rf+state.rTotal.intRegs), RegIndex(rf+1+state.rTotal.intRegs)) rf += 2 - } else if t.IsFloat() { + } else if t.IsFloat() || t.IsSIMD() { regs = append(regs, RegIndex(rf+state.rTotal.intRegs)) rf += 1 } else { diff --git a/src/cmd/compile/internal/abt/avlint32.go b/src/cmd/compile/internal/abt/avlint32.go index ddfca346a2f751..e41a6c0ca40bd8 100644 --- a/src/cmd/compile/internal/abt/avlint32.go +++ b/src/cmd/compile/internal/abt/avlint32.go @@ -28,7 +28,7 @@ type T struct { type node32 struct { // Standard conventions hold for left = smaller, right = larger left, right *node32 - data interface{} + data any key int32 height_ int8 } @@ -49,21 +49,21 @@ func (t *T) IsSingle() bool { // VisitInOrder applies f to the key and data pairs in t, // with keys ordered from smallest to largest. -func (t *T) VisitInOrder(f func(int32, interface{})) { +func (t *T) VisitInOrder(f func(int32, any)) { if t.root == nil { return } t.root.visitInOrder(f) } -func (n *node32) nilOrData() interface{} { +func (n *node32) nilOrData() any { if n == nil { return nil } return n.data } -func (n *node32) nilOrKeyAndData() (k int32, d interface{}) { +func (n *node32) nilOrKeyAndData() (k int32, d any) { if n == nil { k = NOT_KEY32 d = nil @@ -83,7 +83,7 @@ func (n *node32) height() int8 { // Find returns the data associated with x in the tree, or // nil if x is not in the tree. -func (t *T) Find(x int32) interface{} { +func (t *T) Find(x int32) any { return t.root.find(x).nilOrData() } @@ -92,7 +92,7 @@ func (t *T) Find(x int32) interface{} { // x was already a key in the tree. The previous data associated // with x is returned, and is nil if x was not previously a // key in the tree. -func (t *T) Insert(x int32, data interface{}) interface{} { +func (t *T) Insert(x int32, data any) any { if x == NOT_KEY32 { panic("Cannot use sentinel value -0x80000000 as key") } @@ -105,7 +105,7 @@ func (t *T) Insert(x int32, data interface{}) interface{} { } else { newroot, n, o = n.aInsert(x) } - var r interface{} + var r any if o != nil { r = o.data } else { @@ -121,7 +121,7 @@ func (t *T) Copy() *T { return &u } -func (t *T) Delete(x int32) interface{} { +func (t *T) Delete(x int32) any { n := t.root if n == nil { return nil @@ -135,7 +135,7 @@ func (t *T) Delete(x int32) interface{} { return d.data } -func (t *T) DeleteMin() (int32, interface{}) { +func (t *T) DeleteMin() (int32, any) { n := t.root if n == nil { return NOT_KEY32, nil @@ -149,7 +149,7 @@ func (t *T) DeleteMin() (int32, interface{}) { return d.key, d.data } -func (t *T) DeleteMax() (int32, interface{}) { +func (t *T) DeleteMax() (int32, any) { n := t.root if n == nil { return NOT_KEY32, nil @@ -172,7 +172,7 @@ func (t *T) Size() int { // not be symmetric. If f returns nil, then the key and data are not // added to the result. If f itself is nil, then whatever value was // already present in the smaller set is used. -func (t *T) Intersection(u *T, f func(x, y interface{}) interface{}) *T { +func (t *T) Intersection(u *T, f func(x, y any) any) *T { if t.Size() == 0 || u.Size() == 0 { return &T{} } @@ -227,7 +227,7 @@ func (t *T) Intersection(u *T, f func(x, y interface{}) interface{}) *T { // is given by f(t's data, u's data) -- f need not be symmetric. If f returns nil, // then the key and data are not added to the result. If f itself is nil, then // whatever value was already present in the larger set is used. -func (t *T) Union(u *T, f func(x, y interface{}) interface{}) *T { +func (t *T) Union(u *T, f func(x, y any) any) *T { if t.Size() == 0 { return u } @@ -284,7 +284,7 @@ func (t *T) Union(u *T, f func(x, y interface{}) interface{}) *T { // of f applied to data corresponding to equal keys. If f returns nil // (or if f is nil) then the key+data are excluded, as usual. If f // returns not-nil, then that key+data pair is inserted. instead. -func (t *T) Difference(u *T, f func(x, y interface{}) interface{}) *T { +func (t *T) Difference(u *T, f func(x, y any) any) *T { if t.Size() == 0 { return &T{} } @@ -365,7 +365,7 @@ func (t *node32) equals(u *node32) bool { return it.done() == iu.done() } -func (t *T) Equiv(u *T, eqv func(x, y interface{}) bool) bool { +func (t *T) Equiv(u *T, eqv func(x, y any) bool) bool { if t == u { return true } @@ -375,7 +375,7 @@ func (t *T) Equiv(u *T, eqv func(x, y interface{}) bool) bool { return t.root.equiv(u.root, eqv) } -func (t *node32) equiv(u *node32, eqv func(x, y interface{}) bool) bool { +func (t *node32) equiv(u *node32, eqv func(x, y any) bool) bool { if t == u { return true } @@ -404,7 +404,7 @@ type Iterator struct { it iterator } -func (it *Iterator) Next() (int32, interface{}) { +func (it *Iterator) Next() (int32, any) { x := it.it.next() if x == nil { return NOT_KEY32, nil @@ -461,37 +461,37 @@ func (it *iterator) next() *node32 { // Min returns the minimum element of t. // If t is empty, then (NOT_KEY32, nil) is returned. -func (t *T) Min() (k int32, d interface{}) { +func (t *T) Min() (k int32, d any) { return t.root.min().nilOrKeyAndData() } // Max returns the maximum element of t. // If t is empty, then (NOT_KEY32, nil) is returned. -func (t *T) Max() (k int32, d interface{}) { +func (t *T) Max() (k int32, d any) { return t.root.max().nilOrKeyAndData() } // Glb returns the greatest-lower-bound-exclusive of x and the associated // data. If x has no glb in the tree, then (NOT_KEY32, nil) is returned. -func (t *T) Glb(x int32) (k int32, d interface{}) { +func (t *T) Glb(x int32) (k int32, d any) { return t.root.glb(x, false).nilOrKeyAndData() } // GlbEq returns the greatest-lower-bound-inclusive of x and the associated // data. If x has no glbEQ in the tree, then (NOT_KEY32, nil) is returned. -func (t *T) GlbEq(x int32) (k int32, d interface{}) { +func (t *T) GlbEq(x int32) (k int32, d any) { return t.root.glb(x, true).nilOrKeyAndData() } // Lub returns the least-upper-bound-exclusive of x and the associated // data. If x has no lub in the tree, then (NOT_KEY32, nil) is returned. -func (t *T) Lub(x int32) (k int32, d interface{}) { +func (t *T) Lub(x int32) (k int32, d any) { return t.root.lub(x, false).nilOrKeyAndData() } // LubEq returns the least-upper-bound-inclusive of x and the associated // data. If x has no lubEq in the tree, then (NOT_KEY32, nil) is returned. -func (t *T) LubEq(x int32) (k int32, d interface{}) { +func (t *T) LubEq(x int32) (k int32, d any) { return t.root.lub(x, true).nilOrKeyAndData() } @@ -499,7 +499,7 @@ func (t *node32) isLeaf() bool { return t.left == nil && t.right == nil && t.height_ == LEAF_HEIGHT } -func (t *node32) visitInOrder(f func(int32, interface{})) { +func (t *node32) visitInOrder(f func(int32, any)) { if t.left != nil { t.left.visitInOrder(f) } diff --git a/src/cmd/compile/internal/abt/avlint32_test.go b/src/cmd/compile/internal/abt/avlint32_test.go index 7fa9ed4fd68236..71962445f2b1d8 100644 --- a/src/cmd/compile/internal/abt/avlint32_test.go +++ b/src/cmd/compile/internal/abt/avlint32_test.go @@ -317,7 +317,7 @@ func applicIterator(te *testing.T, x []int32) { } } -func equiv(a, b interface{}) bool { +func equiv(a, b any) bool { sa, sb := a.(*sstring), b.(*sstring) return *sa == *sb } @@ -450,16 +450,16 @@ func TestEquals(t *testing.T) { []int32{1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 24, 22, 20, 18, 16, 14, 12, 10, 8, 6, 4, 2}) } -func first(x, y interface{}) interface{} { +func first(x, y any) any { return x } -func second(x, y interface{}) interface{} { +func second(x, y any) any { return y } -func alwaysNil(x, y interface{}) interface{} { +func alwaysNil(x, y any) any { return nil } -func smaller(x, y interface{}) interface{} { +func smaller(x, y any) any { xi, _ := strconv.Atoi(fmt.Sprint(x)) yi, _ := strconv.Atoi(fmt.Sprint(y)) if xi < yi { @@ -560,7 +560,7 @@ func (s *sstring) String() string { return s.s } -func stringer(s string) interface{} { +func stringer(s string) any { return &sstring{s} } diff --git a/src/cmd/compile/internal/amd64/simdssa.go b/src/cmd/compile/internal/amd64/simdssa.go new file mode 100644 index 00000000000000..12f20f15ea4628 --- /dev/null +++ b/src/cmd/compile/internal/amd64/simdssa.go @@ -0,0 +1,4389 @@ +// Code generated by 'simdgen -o godefs -goroot $GOROOT -arch amd64 -xedPath $XED_PATH go_amd64.yaml types.yaml categories.yaml'; DO NOT EDIT. + +package amd64 + +import ( + "cmd/compile/internal/ssa" + "cmd/compile/internal/ssagen" + "cmd/internal/obj" + "cmd/internal/obj/x86" +) + +func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { + var p *obj.Prog + switch v.Op { + case ssa.OpAMD64VAESIMC128, + ssa.OpAMD64VPABSB128, + ssa.OpAMD64VPABSB256, + ssa.OpAMD64VPABSB512, + ssa.OpAMD64VPABSW128, + ssa.OpAMD64VPABSW256, + ssa.OpAMD64VPABSW512, + ssa.OpAMD64VPABSD128, + ssa.OpAMD64VPABSD256, + ssa.OpAMD64VPABSD512, + ssa.OpAMD64VPABSQ128, + ssa.OpAMD64VPABSQ256, + ssa.OpAMD64VPABSQ512, + ssa.OpAMD64VCVTPD2PSX128, + ssa.OpAMD64VCVTPD2PSY128, + ssa.OpAMD64VCVTPD2PS256, + ssa.OpAMD64VCVTDQ2PS128, + ssa.OpAMD64VCVTDQ2PS256, + ssa.OpAMD64VCVTDQ2PS512, + ssa.OpAMD64VCVTQQ2PSX128, + ssa.OpAMD64VCVTQQ2PSY128, + ssa.OpAMD64VCVTQQ2PS256, + ssa.OpAMD64VCVTUDQ2PS128, + ssa.OpAMD64VCVTUDQ2PS256, + ssa.OpAMD64VCVTUDQ2PS512, + ssa.OpAMD64VCVTUQQ2PSX128, + ssa.OpAMD64VCVTUQQ2PSY128, + ssa.OpAMD64VCVTUQQ2PS256, + ssa.OpAMD64VCVTPS2PD256, + ssa.OpAMD64VCVTPS2PD512, + ssa.OpAMD64VCVTDQ2PD256, + ssa.OpAMD64VCVTDQ2PD512, + ssa.OpAMD64VCVTQQ2PD128, + ssa.OpAMD64VCVTQQ2PD256, + ssa.OpAMD64VCVTQQ2PD512, + ssa.OpAMD64VCVTUDQ2PD256, + ssa.OpAMD64VCVTUDQ2PD512, + ssa.OpAMD64VCVTUQQ2PD128, + ssa.OpAMD64VCVTUQQ2PD256, + ssa.OpAMD64VCVTUQQ2PD512, + ssa.OpAMD64VCVTTPS2DQ128, + ssa.OpAMD64VCVTTPS2DQ256, + ssa.OpAMD64VCVTTPS2DQ512, + ssa.OpAMD64VCVTTPD2DQX128, + ssa.OpAMD64VCVTTPD2DQY128, + ssa.OpAMD64VCVTTPD2DQ256, + ssa.OpAMD64VCVTTPS2QQ256, + ssa.OpAMD64VCVTTPS2QQ512, + ssa.OpAMD64VCVTTPD2QQ128, + ssa.OpAMD64VCVTTPD2QQ256, + ssa.OpAMD64VCVTTPD2QQ512, + ssa.OpAMD64VCVTTPS2UDQ128, + ssa.OpAMD64VCVTTPS2UDQ256, + ssa.OpAMD64VCVTTPS2UDQ512, + ssa.OpAMD64VCVTTPD2UDQX128, + ssa.OpAMD64VCVTTPD2UDQY128, + ssa.OpAMD64VCVTTPD2UDQ256, + ssa.OpAMD64VCVTTPS2UQQ256, + ssa.OpAMD64VCVTTPS2UQQ512, + ssa.OpAMD64VCVTTPD2UQQ128, + ssa.OpAMD64VCVTTPD2UQQ256, + ssa.OpAMD64VCVTTPD2UQQ512, + ssa.OpAMD64VPMOVSXBQ128, + ssa.OpAMD64VPMOVSXWQ128, + ssa.OpAMD64VPMOVSXDQ128, + ssa.OpAMD64VPMOVZXBQ128, + ssa.OpAMD64VPMOVZXWQ128, + ssa.OpAMD64VPMOVZXDQ128, + ssa.OpAMD64VPMOVSXBD128, + ssa.OpAMD64VPMOVSXWD128, + ssa.OpAMD64VPMOVSXBQ256, + ssa.OpAMD64VPMOVSXWQ256, + ssa.OpAMD64VPMOVZXBD128, + ssa.OpAMD64VPMOVZXWD128, + ssa.OpAMD64VPMOVZXBQ256, + ssa.OpAMD64VPMOVZXWQ256, + ssa.OpAMD64VPMOVSXBW128, + ssa.OpAMD64VPMOVSXBD256, + ssa.OpAMD64VPMOVSXBQ512, + ssa.OpAMD64VPMOVZXBW128, + ssa.OpAMD64VPMOVZXBD256, + ssa.OpAMD64VPMOVZXBQ512, + ssa.OpAMD64VPMOVSXBW256, + ssa.OpAMD64VPMOVSXBW512, + ssa.OpAMD64VPMOVSXBD512, + ssa.OpAMD64VPMOVSXWD256, + ssa.OpAMD64VPMOVSXWD512, + ssa.OpAMD64VPMOVSXWQ512, + ssa.OpAMD64VPMOVSXDQ256, + ssa.OpAMD64VPMOVSXDQ512, + ssa.OpAMD64VPMOVZXBW256, + ssa.OpAMD64VPMOVZXBW512, + ssa.OpAMD64VPMOVZXBD512, + ssa.OpAMD64VPMOVZXWD256, + ssa.OpAMD64VPMOVZXWD512, + ssa.OpAMD64VPMOVZXWQ512, + ssa.OpAMD64VPMOVZXDQ256, + ssa.OpAMD64VPMOVZXDQ512, + ssa.OpAMD64VPLZCNTD128, + ssa.OpAMD64VPLZCNTD256, + ssa.OpAMD64VPLZCNTD512, + ssa.OpAMD64VPLZCNTQ128, + ssa.OpAMD64VPLZCNTQ256, + ssa.OpAMD64VPLZCNTQ512, + ssa.OpAMD64VPOPCNTB128, + ssa.OpAMD64VPOPCNTB256, + ssa.OpAMD64VPOPCNTB512, + ssa.OpAMD64VPOPCNTW128, + ssa.OpAMD64VPOPCNTW256, + ssa.OpAMD64VPOPCNTW512, + ssa.OpAMD64VPOPCNTD128, + ssa.OpAMD64VPOPCNTD256, + ssa.OpAMD64VPOPCNTD512, + ssa.OpAMD64VPOPCNTQ128, + ssa.OpAMD64VPOPCNTQ256, + ssa.OpAMD64VPOPCNTQ512, + ssa.OpAMD64VRCPPS128, + ssa.OpAMD64VRCPPS256, + ssa.OpAMD64VRCP14PS512, + ssa.OpAMD64VRCP14PD128, + ssa.OpAMD64VRCP14PD256, + ssa.OpAMD64VRCP14PD512, + ssa.OpAMD64VRSQRTPS128, + ssa.OpAMD64VRSQRTPS256, + ssa.OpAMD64VRSQRT14PS512, + ssa.OpAMD64VRSQRT14PD128, + ssa.OpAMD64VRSQRT14PD256, + ssa.OpAMD64VRSQRT14PD512, + ssa.OpAMD64VPMOVSWB128_128, + ssa.OpAMD64VPMOVSWB128_256, + ssa.OpAMD64VPMOVSWB256, + ssa.OpAMD64VPMOVSDB128_128, + ssa.OpAMD64VPMOVSDB128_256, + ssa.OpAMD64VPMOVSDB128_512, + ssa.OpAMD64VPMOVSQB128_128, + ssa.OpAMD64VPMOVSQB128_256, + ssa.OpAMD64VPMOVSQB128_512, + ssa.OpAMD64VPMOVSDW128_128, + ssa.OpAMD64VPMOVSDW128_256, + ssa.OpAMD64VPMOVSDW256, + ssa.OpAMD64VPMOVSQW128_128, + ssa.OpAMD64VPMOVSQW128_256, + ssa.OpAMD64VPMOVSQW128_512, + ssa.OpAMD64VPMOVSQD128_128, + ssa.OpAMD64VPMOVSQD128_256, + ssa.OpAMD64VPMOVSQD256, + ssa.OpAMD64VPMOVUSWB128_128, + ssa.OpAMD64VPMOVUSWB128_256, + ssa.OpAMD64VPMOVUSWB256, + ssa.OpAMD64VPMOVUSDB128_128, + ssa.OpAMD64VPMOVUSDB128_256, + ssa.OpAMD64VPMOVUSDB128_512, + ssa.OpAMD64VPMOVUSQB128_128, + ssa.OpAMD64VPMOVUSQB128_256, + ssa.OpAMD64VPMOVUSQB128_512, + ssa.OpAMD64VPMOVUSDW128_128, + ssa.OpAMD64VPMOVUSDW128_256, + ssa.OpAMD64VPMOVUSDW256, + ssa.OpAMD64VPMOVUSQW128_128, + ssa.OpAMD64VPMOVUSQW128_256, + ssa.OpAMD64VPMOVUSQW128_512, + ssa.OpAMD64VPMOVUSQD128_128, + ssa.OpAMD64VPMOVUSQD128_256, + ssa.OpAMD64VPMOVUSQD256, + ssa.OpAMD64VSQRTPS128, + ssa.OpAMD64VSQRTPS256, + ssa.OpAMD64VSQRTPS512, + ssa.OpAMD64VSQRTPD128, + ssa.OpAMD64VSQRTPD256, + ssa.OpAMD64VSQRTPD512, + ssa.OpAMD64VPMOVWB128_128, + ssa.OpAMD64VPMOVWB128_256, + ssa.OpAMD64VPMOVWB256, + ssa.OpAMD64VPMOVDB128_128, + ssa.OpAMD64VPMOVDB128_256, + ssa.OpAMD64VPMOVDB128_512, + ssa.OpAMD64VPMOVQB128_128, + ssa.OpAMD64VPMOVQB128_256, + ssa.OpAMD64VPMOVQB128_512, + ssa.OpAMD64VPMOVDW128_128, + ssa.OpAMD64VPMOVDW128_256, + ssa.OpAMD64VPMOVDW256, + ssa.OpAMD64VPMOVQW128_128, + ssa.OpAMD64VPMOVQW128_256, + ssa.OpAMD64VPMOVQW128_512, + ssa.OpAMD64VPMOVQD128_128, + ssa.OpAMD64VPMOVQD128_256, + ssa.OpAMD64VPMOVQD256, + ssa.OpAMD64VPBROADCASTQ128, + ssa.OpAMD64VBROADCASTSS128, + ssa.OpAMD64VBROADCASTSD256, + ssa.OpAMD64VPBROADCASTD128, + ssa.OpAMD64VPBROADCASTQ256, + ssa.OpAMD64VBROADCASTSS256, + ssa.OpAMD64VBROADCASTSD512, + ssa.OpAMD64VPBROADCASTW128, + ssa.OpAMD64VPBROADCASTD256, + ssa.OpAMD64VPBROADCASTQ512, + ssa.OpAMD64VBROADCASTSS512, + ssa.OpAMD64VPBROADCASTB128, + ssa.OpAMD64VPBROADCASTW256, + ssa.OpAMD64VPBROADCASTD512, + ssa.OpAMD64VPBROADCASTB256, + ssa.OpAMD64VPBROADCASTW512, + ssa.OpAMD64VPBROADCASTB512: + p = simdV11(s, v) + + case ssa.OpAMD64VAESDECLAST128, + ssa.OpAMD64VAESDECLAST256, + ssa.OpAMD64VAESDECLAST512, + ssa.OpAMD64VAESDEC128, + ssa.OpAMD64VAESDEC256, + ssa.OpAMD64VAESDEC512, + ssa.OpAMD64VAESENCLAST128, + ssa.OpAMD64VAESENCLAST256, + ssa.OpAMD64VAESENCLAST512, + ssa.OpAMD64VAESENC128, + ssa.OpAMD64VAESENC256, + ssa.OpAMD64VAESENC512, + ssa.OpAMD64VADDPS128, + ssa.OpAMD64VADDPS256, + ssa.OpAMD64VADDPS512, + ssa.OpAMD64VADDPD128, + ssa.OpAMD64VADDPD256, + ssa.OpAMD64VADDPD512, + ssa.OpAMD64VPADDB128, + ssa.OpAMD64VPADDB256, + ssa.OpAMD64VPADDB512, + ssa.OpAMD64VPADDW128, + ssa.OpAMD64VPADDW256, + ssa.OpAMD64VPADDW512, + ssa.OpAMD64VPADDD128, + ssa.OpAMD64VPADDD256, + ssa.OpAMD64VPADDD512, + ssa.OpAMD64VPADDQ128, + ssa.OpAMD64VPADDQ256, + ssa.OpAMD64VPADDQ512, + ssa.OpAMD64VADDSUBPS128, + ssa.OpAMD64VADDSUBPS256, + ssa.OpAMD64VADDSUBPD128, + ssa.OpAMD64VADDSUBPD256, + ssa.OpAMD64VPADDSB128, + ssa.OpAMD64VPADDSB256, + ssa.OpAMD64VPADDSB512, + ssa.OpAMD64VPADDSW128, + ssa.OpAMD64VPADDSW256, + ssa.OpAMD64VPADDSW512, + ssa.OpAMD64VPADDUSB128, + ssa.OpAMD64VPADDUSB256, + ssa.OpAMD64VPADDUSB512, + ssa.OpAMD64VPADDUSW128, + ssa.OpAMD64VPADDUSW256, + ssa.OpAMD64VPADDUSW512, + ssa.OpAMD64VPAND128, + ssa.OpAMD64VPAND256, + ssa.OpAMD64VPANDD512, + ssa.OpAMD64VPANDQ512, + ssa.OpAMD64VPANDN128, + ssa.OpAMD64VPANDN256, + ssa.OpAMD64VPANDND512, + ssa.OpAMD64VPANDNQ512, + ssa.OpAMD64VPAVGB128, + ssa.OpAMD64VPAVGB256, + ssa.OpAMD64VPAVGB512, + ssa.OpAMD64VPAVGW128, + ssa.OpAMD64VPAVGW256, + ssa.OpAMD64VPAVGW512, + ssa.OpAMD64VHADDPS128, + ssa.OpAMD64VHADDPD128, + ssa.OpAMD64VPHADDW128, + ssa.OpAMD64VPHADDD128, + ssa.OpAMD64VHADDPS256, + ssa.OpAMD64VHADDPD256, + ssa.OpAMD64VPHADDW256, + ssa.OpAMD64VPHADDD256, + ssa.OpAMD64VPHADDSW128, + ssa.OpAMD64VPHADDSW256, + ssa.OpAMD64VHSUBPS128, + ssa.OpAMD64VHSUBPD128, + ssa.OpAMD64VPHSUBW128, + ssa.OpAMD64VPHSUBD128, + ssa.OpAMD64VHSUBPS256, + ssa.OpAMD64VHSUBPD256, + ssa.OpAMD64VPHSUBW256, + ssa.OpAMD64VPHSUBD256, + ssa.OpAMD64VPHSUBSW128, + ssa.OpAMD64VPHSUBSW256, + ssa.OpAMD64VDIVPS128, + ssa.OpAMD64VDIVPS256, + ssa.OpAMD64VDIVPS512, + ssa.OpAMD64VDIVPD128, + ssa.OpAMD64VDIVPD256, + ssa.OpAMD64VDIVPD512, + ssa.OpAMD64VPMADDWD128, + ssa.OpAMD64VPMADDWD256, + ssa.OpAMD64VPMADDWD512, + ssa.OpAMD64VPMADDUBSW128, + ssa.OpAMD64VPMADDUBSW256, + ssa.OpAMD64VPMADDUBSW512, + ssa.OpAMD64VPCMPEQB128, + ssa.OpAMD64VPCMPEQB256, + ssa.OpAMD64VPCMPEQW128, + ssa.OpAMD64VPCMPEQW256, + ssa.OpAMD64VPCMPEQD128, + ssa.OpAMD64VPCMPEQD256, + ssa.OpAMD64VPCMPEQQ128, + ssa.OpAMD64VPCMPEQQ256, + ssa.OpAMD64VGF2P8MULB128, + ssa.OpAMD64VGF2P8MULB256, + ssa.OpAMD64VGF2P8MULB512, + ssa.OpAMD64VPCMPGTB128, + ssa.OpAMD64VPCMPGTB256, + ssa.OpAMD64VPCMPGTW128, + ssa.OpAMD64VPCMPGTW256, + ssa.OpAMD64VPCMPGTD128, + ssa.OpAMD64VPCMPGTD256, + ssa.OpAMD64VPCMPGTQ128, + ssa.OpAMD64VPCMPGTQ256, + ssa.OpAMD64VPUNPCKHWD128, + ssa.OpAMD64VPUNPCKHDQ128, + ssa.OpAMD64VPUNPCKHQDQ128, + ssa.OpAMD64VPUNPCKHWD256, + ssa.OpAMD64VPUNPCKHWD512, + ssa.OpAMD64VPUNPCKHDQ256, + ssa.OpAMD64VPUNPCKHDQ512, + ssa.OpAMD64VPUNPCKHQDQ256, + ssa.OpAMD64VPUNPCKHQDQ512, + ssa.OpAMD64VPUNPCKLWD128, + ssa.OpAMD64VPUNPCKLDQ128, + ssa.OpAMD64VPUNPCKLQDQ128, + ssa.OpAMD64VPUNPCKLWD256, + ssa.OpAMD64VPUNPCKLWD512, + ssa.OpAMD64VPUNPCKLDQ256, + ssa.OpAMD64VPUNPCKLDQ512, + ssa.OpAMD64VPUNPCKLQDQ256, + ssa.OpAMD64VPUNPCKLQDQ512, + ssa.OpAMD64VMAXPS128, + ssa.OpAMD64VMAXPS256, + ssa.OpAMD64VMAXPS512, + ssa.OpAMD64VMAXPD128, + ssa.OpAMD64VMAXPD256, + ssa.OpAMD64VMAXPD512, + ssa.OpAMD64VPMAXSB128, + ssa.OpAMD64VPMAXSB256, + ssa.OpAMD64VPMAXSB512, + ssa.OpAMD64VPMAXSW128, + ssa.OpAMD64VPMAXSW256, + ssa.OpAMD64VPMAXSW512, + ssa.OpAMD64VPMAXSD128, + ssa.OpAMD64VPMAXSD256, + ssa.OpAMD64VPMAXSD512, + ssa.OpAMD64VPMAXSQ128, + ssa.OpAMD64VPMAXSQ256, + ssa.OpAMD64VPMAXSQ512, + ssa.OpAMD64VPMAXUB128, + ssa.OpAMD64VPMAXUB256, + ssa.OpAMD64VPMAXUB512, + ssa.OpAMD64VPMAXUW128, + ssa.OpAMD64VPMAXUW256, + ssa.OpAMD64VPMAXUW512, + ssa.OpAMD64VPMAXUD128, + ssa.OpAMD64VPMAXUD256, + ssa.OpAMD64VPMAXUD512, + ssa.OpAMD64VPMAXUQ128, + ssa.OpAMD64VPMAXUQ256, + ssa.OpAMD64VPMAXUQ512, + ssa.OpAMD64VMINPS128, + ssa.OpAMD64VMINPS256, + ssa.OpAMD64VMINPS512, + ssa.OpAMD64VMINPD128, + ssa.OpAMD64VMINPD256, + ssa.OpAMD64VMINPD512, + ssa.OpAMD64VPMINSB128, + ssa.OpAMD64VPMINSB256, + ssa.OpAMD64VPMINSB512, + ssa.OpAMD64VPMINSW128, + ssa.OpAMD64VPMINSW256, + ssa.OpAMD64VPMINSW512, + ssa.OpAMD64VPMINSD128, + ssa.OpAMD64VPMINSD256, + ssa.OpAMD64VPMINSD512, + ssa.OpAMD64VPMINSQ128, + ssa.OpAMD64VPMINSQ256, + ssa.OpAMD64VPMINSQ512, + ssa.OpAMD64VPMINUB128, + ssa.OpAMD64VPMINUB256, + ssa.OpAMD64VPMINUB512, + ssa.OpAMD64VPMINUW128, + ssa.OpAMD64VPMINUW256, + ssa.OpAMD64VPMINUW512, + ssa.OpAMD64VPMINUD128, + ssa.OpAMD64VPMINUD256, + ssa.OpAMD64VPMINUD512, + ssa.OpAMD64VPMINUQ128, + ssa.OpAMD64VPMINUQ256, + ssa.OpAMD64VPMINUQ512, + ssa.OpAMD64VMULPS128, + ssa.OpAMD64VMULPS256, + ssa.OpAMD64VMULPS512, + ssa.OpAMD64VMULPD128, + ssa.OpAMD64VMULPD256, + ssa.OpAMD64VMULPD512, + ssa.OpAMD64VPMULLW128, + ssa.OpAMD64VPMULLW256, + ssa.OpAMD64VPMULLW512, + ssa.OpAMD64VPMULLD128, + ssa.OpAMD64VPMULLD256, + ssa.OpAMD64VPMULLD512, + ssa.OpAMD64VPMULLQ128, + ssa.OpAMD64VPMULLQ256, + ssa.OpAMD64VPMULLQ512, + ssa.OpAMD64VPMULHW128, + ssa.OpAMD64VPMULHW256, + ssa.OpAMD64VPMULHW512, + ssa.OpAMD64VPMULHUW128, + ssa.OpAMD64VPMULHUW256, + ssa.OpAMD64VPMULHUW512, + ssa.OpAMD64VPSIGNB128, + ssa.OpAMD64VPSIGNB256, + ssa.OpAMD64VPSIGNW128, + ssa.OpAMD64VPSIGNW256, + ssa.OpAMD64VPSIGND128, + ssa.OpAMD64VPSIGND256, + ssa.OpAMD64VPMULDQ128, + ssa.OpAMD64VPMULDQ256, + ssa.OpAMD64VPMULUDQ128, + ssa.OpAMD64VPMULUDQ256, + ssa.OpAMD64VPOR128, + ssa.OpAMD64VPOR256, + ssa.OpAMD64VPORD512, + ssa.OpAMD64VPORQ512, + ssa.OpAMD64VPERMB128, + ssa.OpAMD64VPERMB256, + ssa.OpAMD64VPERMB512, + ssa.OpAMD64VPERMW128, + ssa.OpAMD64VPERMW256, + ssa.OpAMD64VPERMW512, + ssa.OpAMD64VPERMPS256, + ssa.OpAMD64VPERMD256, + ssa.OpAMD64VPERMPS512, + ssa.OpAMD64VPERMD512, + ssa.OpAMD64VPERMPD256, + ssa.OpAMD64VPERMQ256, + ssa.OpAMD64VPERMPD512, + ssa.OpAMD64VPERMQ512, + ssa.OpAMD64VPSHUFB128, + ssa.OpAMD64VPSHUFB256, + ssa.OpAMD64VPSHUFB512, + ssa.OpAMD64VPROLVD128, + ssa.OpAMD64VPROLVD256, + ssa.OpAMD64VPROLVD512, + ssa.OpAMD64VPROLVQ128, + ssa.OpAMD64VPROLVQ256, + ssa.OpAMD64VPROLVQ512, + ssa.OpAMD64VPRORVD128, + ssa.OpAMD64VPRORVD256, + ssa.OpAMD64VPRORVD512, + ssa.OpAMD64VPRORVQ128, + ssa.OpAMD64VPRORVQ256, + ssa.OpAMD64VPRORVQ512, + ssa.OpAMD64VPACKSSDW128, + ssa.OpAMD64VPACKSSDW256, + ssa.OpAMD64VPACKSSDW512, + ssa.OpAMD64VPACKUSDW128, + ssa.OpAMD64VPACKUSDW256, + ssa.OpAMD64VPACKUSDW512, + ssa.OpAMD64VSCALEFPS128, + ssa.OpAMD64VSCALEFPS256, + ssa.OpAMD64VSCALEFPS512, + ssa.OpAMD64VSCALEFPD128, + ssa.OpAMD64VSCALEFPD256, + ssa.OpAMD64VSCALEFPD512, + ssa.OpAMD64VPSLLVW128, + ssa.OpAMD64VPSLLVW256, + ssa.OpAMD64VPSLLVW512, + ssa.OpAMD64VPSLLVD128, + ssa.OpAMD64VPSLLVD256, + ssa.OpAMD64VPSLLVD512, + ssa.OpAMD64VPSLLVQ128, + ssa.OpAMD64VPSLLVQ256, + ssa.OpAMD64VPSLLVQ512, + ssa.OpAMD64VPSRAVW128, + ssa.OpAMD64VPSRAVW256, + ssa.OpAMD64VPSRAVW512, + ssa.OpAMD64VPSRAVD128, + ssa.OpAMD64VPSRAVD256, + ssa.OpAMD64VPSRAVD512, + ssa.OpAMD64VPSRAVQ128, + ssa.OpAMD64VPSRAVQ256, + ssa.OpAMD64VPSRAVQ512, + ssa.OpAMD64VPSRLVW128, + ssa.OpAMD64VPSRLVW256, + ssa.OpAMD64VPSRLVW512, + ssa.OpAMD64VPSRLVD128, + ssa.OpAMD64VPSRLVD256, + ssa.OpAMD64VPSRLVD512, + ssa.OpAMD64VPSRLVQ128, + ssa.OpAMD64VPSRLVQ256, + ssa.OpAMD64VPSRLVQ512, + ssa.OpAMD64VSUBPS128, + ssa.OpAMD64VSUBPS256, + ssa.OpAMD64VSUBPS512, + ssa.OpAMD64VSUBPD128, + ssa.OpAMD64VSUBPD256, + ssa.OpAMD64VSUBPD512, + ssa.OpAMD64VPSUBB128, + ssa.OpAMD64VPSUBB256, + ssa.OpAMD64VPSUBB512, + ssa.OpAMD64VPSUBW128, + ssa.OpAMD64VPSUBW256, + ssa.OpAMD64VPSUBW512, + ssa.OpAMD64VPSUBD128, + ssa.OpAMD64VPSUBD256, + ssa.OpAMD64VPSUBD512, + ssa.OpAMD64VPSUBQ128, + ssa.OpAMD64VPSUBQ256, + ssa.OpAMD64VPSUBQ512, + ssa.OpAMD64VPSUBSB128, + ssa.OpAMD64VPSUBSB256, + ssa.OpAMD64VPSUBSB512, + ssa.OpAMD64VPSUBSW128, + ssa.OpAMD64VPSUBSW256, + ssa.OpAMD64VPSUBSW512, + ssa.OpAMD64VPSUBUSB128, + ssa.OpAMD64VPSUBUSB256, + ssa.OpAMD64VPSUBUSB512, + ssa.OpAMD64VPSUBUSW128, + ssa.OpAMD64VPSUBUSW256, + ssa.OpAMD64VPSUBUSW512, + ssa.OpAMD64VPSADBW128, + ssa.OpAMD64VPSADBW256, + ssa.OpAMD64VPSADBW512, + ssa.OpAMD64VPXOR128, + ssa.OpAMD64VPXOR256, + ssa.OpAMD64VPXORD512, + ssa.OpAMD64VPXORQ512: + p = simdV21(s, v) + + case ssa.OpAMD64VPCMPEQB512, + ssa.OpAMD64VPCMPEQW512, + ssa.OpAMD64VPCMPEQD512, + ssa.OpAMD64VPCMPEQQ512, + ssa.OpAMD64VPCMPGTB512, + ssa.OpAMD64VPCMPGTW512, + ssa.OpAMD64VPCMPGTD512, + ssa.OpAMD64VPCMPGTQ512: + p = simdV2k(s, v) + + case ssa.OpAMD64VADDPSMasked128, + ssa.OpAMD64VADDPSMasked256, + ssa.OpAMD64VADDPSMasked512, + ssa.OpAMD64VADDPDMasked128, + ssa.OpAMD64VADDPDMasked256, + ssa.OpAMD64VADDPDMasked512, + ssa.OpAMD64VPADDBMasked128, + ssa.OpAMD64VPADDBMasked256, + ssa.OpAMD64VPADDBMasked512, + ssa.OpAMD64VPADDWMasked128, + ssa.OpAMD64VPADDWMasked256, + ssa.OpAMD64VPADDWMasked512, + ssa.OpAMD64VPADDDMasked128, + ssa.OpAMD64VPADDDMasked256, + ssa.OpAMD64VPADDDMasked512, + ssa.OpAMD64VPADDQMasked128, + ssa.OpAMD64VPADDQMasked256, + ssa.OpAMD64VPADDQMasked512, + ssa.OpAMD64VPADDSBMasked128, + ssa.OpAMD64VPADDSBMasked256, + ssa.OpAMD64VPADDSBMasked512, + ssa.OpAMD64VPADDSWMasked128, + ssa.OpAMD64VPADDSWMasked256, + ssa.OpAMD64VPADDSWMasked512, + ssa.OpAMD64VPADDUSBMasked128, + ssa.OpAMD64VPADDUSBMasked256, + ssa.OpAMD64VPADDUSBMasked512, + ssa.OpAMD64VPADDUSWMasked128, + ssa.OpAMD64VPADDUSWMasked256, + ssa.OpAMD64VPADDUSWMasked512, + ssa.OpAMD64VPANDDMasked128, + ssa.OpAMD64VPANDDMasked256, + ssa.OpAMD64VPANDDMasked512, + ssa.OpAMD64VPANDQMasked128, + ssa.OpAMD64VPANDQMasked256, + ssa.OpAMD64VPANDQMasked512, + ssa.OpAMD64VPANDNDMasked128, + ssa.OpAMD64VPANDNDMasked256, + ssa.OpAMD64VPANDNDMasked512, + ssa.OpAMD64VPANDNQMasked128, + ssa.OpAMD64VPANDNQMasked256, + ssa.OpAMD64VPANDNQMasked512, + ssa.OpAMD64VPAVGBMasked128, + ssa.OpAMD64VPAVGBMasked256, + ssa.OpAMD64VPAVGBMasked512, + ssa.OpAMD64VPAVGWMasked128, + ssa.OpAMD64VPAVGWMasked256, + ssa.OpAMD64VPAVGWMasked512, + ssa.OpAMD64VDIVPSMasked128, + ssa.OpAMD64VDIVPSMasked256, + ssa.OpAMD64VDIVPSMasked512, + ssa.OpAMD64VDIVPDMasked128, + ssa.OpAMD64VDIVPDMasked256, + ssa.OpAMD64VDIVPDMasked512, + ssa.OpAMD64VPMADDWDMasked128, + ssa.OpAMD64VPMADDWDMasked256, + ssa.OpAMD64VPMADDWDMasked512, + ssa.OpAMD64VPMADDUBSWMasked128, + ssa.OpAMD64VPMADDUBSWMasked256, + ssa.OpAMD64VPMADDUBSWMasked512, + ssa.OpAMD64VGF2P8MULBMasked128, + ssa.OpAMD64VGF2P8MULBMasked256, + ssa.OpAMD64VGF2P8MULBMasked512, + ssa.OpAMD64VMAXPSMasked128, + ssa.OpAMD64VMAXPSMasked256, + ssa.OpAMD64VMAXPSMasked512, + ssa.OpAMD64VMAXPDMasked128, + ssa.OpAMD64VMAXPDMasked256, + ssa.OpAMD64VMAXPDMasked512, + ssa.OpAMD64VPMAXSBMasked128, + ssa.OpAMD64VPMAXSBMasked256, + ssa.OpAMD64VPMAXSBMasked512, + ssa.OpAMD64VPMAXSWMasked128, + ssa.OpAMD64VPMAXSWMasked256, + ssa.OpAMD64VPMAXSWMasked512, + ssa.OpAMD64VPMAXSDMasked128, + ssa.OpAMD64VPMAXSDMasked256, + ssa.OpAMD64VPMAXSDMasked512, + ssa.OpAMD64VPMAXSQMasked128, + ssa.OpAMD64VPMAXSQMasked256, + ssa.OpAMD64VPMAXSQMasked512, + ssa.OpAMD64VPMAXUBMasked128, + ssa.OpAMD64VPMAXUBMasked256, + ssa.OpAMD64VPMAXUBMasked512, + ssa.OpAMD64VPMAXUWMasked128, + ssa.OpAMD64VPMAXUWMasked256, + ssa.OpAMD64VPMAXUWMasked512, + ssa.OpAMD64VPMAXUDMasked128, + ssa.OpAMD64VPMAXUDMasked256, + ssa.OpAMD64VPMAXUDMasked512, + ssa.OpAMD64VPMAXUQMasked128, + ssa.OpAMD64VPMAXUQMasked256, + ssa.OpAMD64VPMAXUQMasked512, + ssa.OpAMD64VMINPSMasked128, + ssa.OpAMD64VMINPSMasked256, + ssa.OpAMD64VMINPSMasked512, + ssa.OpAMD64VMINPDMasked128, + ssa.OpAMD64VMINPDMasked256, + ssa.OpAMD64VMINPDMasked512, + ssa.OpAMD64VPMINSBMasked128, + ssa.OpAMD64VPMINSBMasked256, + ssa.OpAMD64VPMINSBMasked512, + ssa.OpAMD64VPMINSWMasked128, + ssa.OpAMD64VPMINSWMasked256, + ssa.OpAMD64VPMINSWMasked512, + ssa.OpAMD64VPMINSDMasked128, + ssa.OpAMD64VPMINSDMasked256, + ssa.OpAMD64VPMINSDMasked512, + ssa.OpAMD64VPMINSQMasked128, + ssa.OpAMD64VPMINSQMasked256, + ssa.OpAMD64VPMINSQMasked512, + ssa.OpAMD64VPMINUBMasked128, + ssa.OpAMD64VPMINUBMasked256, + ssa.OpAMD64VPMINUBMasked512, + ssa.OpAMD64VPMINUWMasked128, + ssa.OpAMD64VPMINUWMasked256, + ssa.OpAMD64VPMINUWMasked512, + ssa.OpAMD64VPMINUDMasked128, + ssa.OpAMD64VPMINUDMasked256, + ssa.OpAMD64VPMINUDMasked512, + ssa.OpAMD64VPMINUQMasked128, + ssa.OpAMD64VPMINUQMasked256, + ssa.OpAMD64VPMINUQMasked512, + ssa.OpAMD64VPMULHWMasked128, + ssa.OpAMD64VPMULHWMasked256, + ssa.OpAMD64VPMULHWMasked512, + ssa.OpAMD64VPMULHUWMasked128, + ssa.OpAMD64VPMULHUWMasked256, + ssa.OpAMD64VPMULHUWMasked512, + ssa.OpAMD64VMULPSMasked128, + ssa.OpAMD64VMULPSMasked256, + ssa.OpAMD64VMULPSMasked512, + ssa.OpAMD64VMULPDMasked128, + ssa.OpAMD64VMULPDMasked256, + ssa.OpAMD64VMULPDMasked512, + ssa.OpAMD64VPMULLWMasked128, + ssa.OpAMD64VPMULLWMasked256, + ssa.OpAMD64VPMULLWMasked512, + ssa.OpAMD64VPMULLDMasked128, + ssa.OpAMD64VPMULLDMasked256, + ssa.OpAMD64VPMULLDMasked512, + ssa.OpAMD64VPMULLQMasked128, + ssa.OpAMD64VPMULLQMasked256, + ssa.OpAMD64VPMULLQMasked512, + ssa.OpAMD64VPORDMasked128, + ssa.OpAMD64VPORDMasked256, + ssa.OpAMD64VPORDMasked512, + ssa.OpAMD64VPORQMasked128, + ssa.OpAMD64VPORQMasked256, + ssa.OpAMD64VPORQMasked512, + ssa.OpAMD64VPERMBMasked128, + ssa.OpAMD64VPERMBMasked256, + ssa.OpAMD64VPERMBMasked512, + ssa.OpAMD64VPERMWMasked128, + ssa.OpAMD64VPERMWMasked256, + ssa.OpAMD64VPERMWMasked512, + ssa.OpAMD64VPERMPSMasked256, + ssa.OpAMD64VPERMDMasked256, + ssa.OpAMD64VPERMPSMasked512, + ssa.OpAMD64VPERMDMasked512, + ssa.OpAMD64VPERMPDMasked256, + ssa.OpAMD64VPERMQMasked256, + ssa.OpAMD64VPERMPDMasked512, + ssa.OpAMD64VPERMQMasked512, + ssa.OpAMD64VPSHUFBMasked256, + ssa.OpAMD64VPSHUFBMasked512, + ssa.OpAMD64VPSHUFBMasked128, + ssa.OpAMD64VPROLVDMasked128, + ssa.OpAMD64VPROLVDMasked256, + ssa.OpAMD64VPROLVDMasked512, + ssa.OpAMD64VPROLVQMasked128, + ssa.OpAMD64VPROLVQMasked256, + ssa.OpAMD64VPROLVQMasked512, + ssa.OpAMD64VPRORVDMasked128, + ssa.OpAMD64VPRORVDMasked256, + ssa.OpAMD64VPRORVDMasked512, + ssa.OpAMD64VPRORVQMasked128, + ssa.OpAMD64VPRORVQMasked256, + ssa.OpAMD64VPRORVQMasked512, + ssa.OpAMD64VPACKSSDWMasked256, + ssa.OpAMD64VPACKSSDWMasked512, + ssa.OpAMD64VPACKSSDWMasked128, + ssa.OpAMD64VPACKUSDWMasked256, + ssa.OpAMD64VPACKUSDWMasked512, + ssa.OpAMD64VPACKUSDWMasked128, + ssa.OpAMD64VSCALEFPSMasked128, + ssa.OpAMD64VSCALEFPSMasked256, + ssa.OpAMD64VSCALEFPSMasked512, + ssa.OpAMD64VSCALEFPDMasked128, + ssa.OpAMD64VSCALEFPDMasked256, + ssa.OpAMD64VSCALEFPDMasked512, + ssa.OpAMD64VPSLLVWMasked128, + ssa.OpAMD64VPSLLVWMasked256, + ssa.OpAMD64VPSLLVWMasked512, + ssa.OpAMD64VPSLLVDMasked128, + ssa.OpAMD64VPSLLVDMasked256, + ssa.OpAMD64VPSLLVDMasked512, + ssa.OpAMD64VPSLLVQMasked128, + ssa.OpAMD64VPSLLVQMasked256, + ssa.OpAMD64VPSLLVQMasked512, + ssa.OpAMD64VPSRAVWMasked128, + ssa.OpAMD64VPSRAVWMasked256, + ssa.OpAMD64VPSRAVWMasked512, + ssa.OpAMD64VPSRAVDMasked128, + ssa.OpAMD64VPSRAVDMasked256, + ssa.OpAMD64VPSRAVDMasked512, + ssa.OpAMD64VPSRAVQMasked128, + ssa.OpAMD64VPSRAVQMasked256, + ssa.OpAMD64VPSRAVQMasked512, + ssa.OpAMD64VPSRLVWMasked128, + ssa.OpAMD64VPSRLVWMasked256, + ssa.OpAMD64VPSRLVWMasked512, + ssa.OpAMD64VPSRLVDMasked128, + ssa.OpAMD64VPSRLVDMasked256, + ssa.OpAMD64VPSRLVDMasked512, + ssa.OpAMD64VPSRLVQMasked128, + ssa.OpAMD64VPSRLVQMasked256, + ssa.OpAMD64VPSRLVQMasked512, + ssa.OpAMD64VSUBPSMasked128, + ssa.OpAMD64VSUBPSMasked256, + ssa.OpAMD64VSUBPSMasked512, + ssa.OpAMD64VSUBPDMasked128, + ssa.OpAMD64VSUBPDMasked256, + ssa.OpAMD64VSUBPDMasked512, + ssa.OpAMD64VPSUBBMasked128, + ssa.OpAMD64VPSUBBMasked256, + ssa.OpAMD64VPSUBBMasked512, + ssa.OpAMD64VPSUBWMasked128, + ssa.OpAMD64VPSUBWMasked256, + ssa.OpAMD64VPSUBWMasked512, + ssa.OpAMD64VPSUBDMasked128, + ssa.OpAMD64VPSUBDMasked256, + ssa.OpAMD64VPSUBDMasked512, + ssa.OpAMD64VPSUBQMasked128, + ssa.OpAMD64VPSUBQMasked256, + ssa.OpAMD64VPSUBQMasked512, + ssa.OpAMD64VPSUBSBMasked128, + ssa.OpAMD64VPSUBSBMasked256, + ssa.OpAMD64VPSUBSBMasked512, + ssa.OpAMD64VPSUBSWMasked128, + ssa.OpAMD64VPSUBSWMasked256, + ssa.OpAMD64VPSUBSWMasked512, + ssa.OpAMD64VPSUBUSBMasked128, + ssa.OpAMD64VPSUBUSBMasked256, + ssa.OpAMD64VPSUBUSBMasked512, + ssa.OpAMD64VPSUBUSWMasked128, + ssa.OpAMD64VPSUBUSWMasked256, + ssa.OpAMD64VPSUBUSWMasked512, + ssa.OpAMD64VPXORDMasked128, + ssa.OpAMD64VPXORDMasked256, + ssa.OpAMD64VPXORDMasked512, + ssa.OpAMD64VPXORQMasked128, + ssa.OpAMD64VPXORQMasked256, + ssa.OpAMD64VPXORQMasked512, + ssa.OpAMD64VPBLENDMBMasked512, + ssa.OpAMD64VPBLENDMWMasked512, + ssa.OpAMD64VPBLENDMDMasked512, + ssa.OpAMD64VPBLENDMQMasked512: + p = simdV2kv(s, v) + + case ssa.OpAMD64VPABSBMasked128, + ssa.OpAMD64VPABSBMasked256, + ssa.OpAMD64VPABSBMasked512, + ssa.OpAMD64VPABSWMasked128, + ssa.OpAMD64VPABSWMasked256, + ssa.OpAMD64VPABSWMasked512, + ssa.OpAMD64VPABSDMasked128, + ssa.OpAMD64VPABSDMasked256, + ssa.OpAMD64VPABSDMasked512, + ssa.OpAMD64VPABSQMasked128, + ssa.OpAMD64VPABSQMasked256, + ssa.OpAMD64VPABSQMasked512, + ssa.OpAMD64VCOMPRESSPSMasked128, + ssa.OpAMD64VCOMPRESSPSMasked256, + ssa.OpAMD64VCOMPRESSPSMasked512, + ssa.OpAMD64VCOMPRESSPDMasked128, + ssa.OpAMD64VCOMPRESSPDMasked256, + ssa.OpAMD64VCOMPRESSPDMasked512, + ssa.OpAMD64VPCOMPRESSBMasked128, + ssa.OpAMD64VPCOMPRESSBMasked256, + ssa.OpAMD64VPCOMPRESSBMasked512, + ssa.OpAMD64VPCOMPRESSWMasked128, + ssa.OpAMD64VPCOMPRESSWMasked256, + ssa.OpAMD64VPCOMPRESSWMasked512, + ssa.OpAMD64VPCOMPRESSDMasked128, + ssa.OpAMD64VPCOMPRESSDMasked256, + ssa.OpAMD64VPCOMPRESSDMasked512, + ssa.OpAMD64VPCOMPRESSQMasked128, + ssa.OpAMD64VPCOMPRESSQMasked256, + ssa.OpAMD64VPCOMPRESSQMasked512, + ssa.OpAMD64VCVTPD2PSXMasked128, + ssa.OpAMD64VCVTPD2PSYMasked128, + ssa.OpAMD64VCVTPD2PSMasked256, + ssa.OpAMD64VCVTDQ2PSMasked128, + ssa.OpAMD64VCVTDQ2PSMasked256, + ssa.OpAMD64VCVTDQ2PSMasked512, + ssa.OpAMD64VCVTQQ2PSXMasked128, + ssa.OpAMD64VCVTQQ2PSYMasked128, + ssa.OpAMD64VCVTQQ2PSMasked256, + ssa.OpAMD64VCVTUDQ2PSMasked128, + ssa.OpAMD64VCVTUDQ2PSMasked256, + ssa.OpAMD64VCVTUDQ2PSMasked512, + ssa.OpAMD64VCVTUQQ2PSXMasked128, + ssa.OpAMD64VCVTUQQ2PSYMasked128, + ssa.OpAMD64VCVTUQQ2PSMasked256, + ssa.OpAMD64VCVTPS2PDMasked256, + ssa.OpAMD64VCVTPS2PDMasked512, + ssa.OpAMD64VCVTDQ2PDMasked256, + ssa.OpAMD64VCVTDQ2PDMasked512, + ssa.OpAMD64VCVTQQ2PDMasked128, + ssa.OpAMD64VCVTQQ2PDMasked256, + ssa.OpAMD64VCVTQQ2PDMasked512, + ssa.OpAMD64VCVTUDQ2PDMasked256, + ssa.OpAMD64VCVTUDQ2PDMasked512, + ssa.OpAMD64VCVTUQQ2PDMasked128, + ssa.OpAMD64VCVTUQQ2PDMasked256, + ssa.OpAMD64VCVTUQQ2PDMasked512, + ssa.OpAMD64VCVTTPS2DQMasked128, + ssa.OpAMD64VCVTTPS2DQMasked256, + ssa.OpAMD64VCVTTPS2DQMasked512, + ssa.OpAMD64VCVTTPD2DQXMasked128, + ssa.OpAMD64VCVTTPD2DQYMasked128, + ssa.OpAMD64VCVTTPD2DQMasked256, + ssa.OpAMD64VCVTTPS2QQMasked256, + ssa.OpAMD64VCVTTPS2QQMasked512, + ssa.OpAMD64VCVTTPD2QQMasked128, + ssa.OpAMD64VCVTTPD2QQMasked256, + ssa.OpAMD64VCVTTPD2QQMasked512, + ssa.OpAMD64VCVTTPS2UDQMasked128, + ssa.OpAMD64VCVTTPS2UDQMasked256, + ssa.OpAMD64VCVTTPS2UDQMasked512, + ssa.OpAMD64VCVTTPD2UDQXMasked128, + ssa.OpAMD64VCVTTPD2UDQYMasked128, + ssa.OpAMD64VCVTTPD2UDQMasked256, + ssa.OpAMD64VCVTTPS2UQQMasked256, + ssa.OpAMD64VCVTTPS2UQQMasked512, + ssa.OpAMD64VCVTTPD2UQQMasked128, + ssa.OpAMD64VCVTTPD2UQQMasked256, + ssa.OpAMD64VCVTTPD2UQQMasked512, + ssa.OpAMD64VEXPANDPSMasked128, + ssa.OpAMD64VEXPANDPSMasked256, + ssa.OpAMD64VEXPANDPSMasked512, + ssa.OpAMD64VEXPANDPDMasked128, + ssa.OpAMD64VEXPANDPDMasked256, + ssa.OpAMD64VEXPANDPDMasked512, + ssa.OpAMD64VPEXPANDBMasked128, + ssa.OpAMD64VPEXPANDBMasked256, + ssa.OpAMD64VPEXPANDBMasked512, + ssa.OpAMD64VPEXPANDWMasked128, + ssa.OpAMD64VPEXPANDWMasked256, + ssa.OpAMD64VPEXPANDWMasked512, + ssa.OpAMD64VPEXPANDDMasked128, + ssa.OpAMD64VPEXPANDDMasked256, + ssa.OpAMD64VPEXPANDDMasked512, + ssa.OpAMD64VPEXPANDQMasked128, + ssa.OpAMD64VPEXPANDQMasked256, + ssa.OpAMD64VPEXPANDQMasked512, + ssa.OpAMD64VPMOVSXBQMasked128, + ssa.OpAMD64VPMOVSXWQMasked128, + ssa.OpAMD64VPMOVSXDQMasked128, + ssa.OpAMD64VPMOVZXBQMasked128, + ssa.OpAMD64VPMOVZXWQMasked128, + ssa.OpAMD64VPMOVZXDQMasked128, + ssa.OpAMD64VPMOVSXBDMasked128, + ssa.OpAMD64VPMOVSXWDMasked128, + ssa.OpAMD64VPMOVSXBQMasked256, + ssa.OpAMD64VPMOVSXWQMasked256, + ssa.OpAMD64VPMOVZXBDMasked128, + ssa.OpAMD64VPMOVZXWDMasked128, + ssa.OpAMD64VPMOVZXBQMasked256, + ssa.OpAMD64VPMOVZXWQMasked256, + ssa.OpAMD64VPMOVSXBWMasked128, + ssa.OpAMD64VPMOVSXBDMasked256, + ssa.OpAMD64VPMOVSXBQMasked512, + ssa.OpAMD64VPMOVZXBWMasked128, + ssa.OpAMD64VPMOVZXBDMasked256, + ssa.OpAMD64VPMOVZXBQMasked512, + ssa.OpAMD64VPMOVSXBWMasked256, + ssa.OpAMD64VPMOVSXBWMasked512, + ssa.OpAMD64VPMOVSXBDMasked512, + ssa.OpAMD64VPMOVSXWDMasked256, + ssa.OpAMD64VPMOVSXWDMasked512, + ssa.OpAMD64VPMOVSXWQMasked512, + ssa.OpAMD64VPMOVSXDQMasked256, + ssa.OpAMD64VPMOVSXDQMasked512, + ssa.OpAMD64VPMOVZXBWMasked256, + ssa.OpAMD64VPMOVZXBWMasked512, + ssa.OpAMD64VPMOVZXBDMasked512, + ssa.OpAMD64VPMOVZXWDMasked256, + ssa.OpAMD64VPMOVZXWDMasked512, + ssa.OpAMD64VPMOVZXWQMasked512, + ssa.OpAMD64VPMOVZXDQMasked256, + ssa.OpAMD64VPMOVZXDQMasked512, + ssa.OpAMD64VPLZCNTDMasked128, + ssa.OpAMD64VPLZCNTDMasked256, + ssa.OpAMD64VPLZCNTDMasked512, + ssa.OpAMD64VPLZCNTQMasked128, + ssa.OpAMD64VPLZCNTQMasked256, + ssa.OpAMD64VPLZCNTQMasked512, + ssa.OpAMD64VPOPCNTBMasked128, + ssa.OpAMD64VPOPCNTBMasked256, + ssa.OpAMD64VPOPCNTBMasked512, + ssa.OpAMD64VPOPCNTWMasked128, + ssa.OpAMD64VPOPCNTWMasked256, + ssa.OpAMD64VPOPCNTWMasked512, + ssa.OpAMD64VPOPCNTDMasked128, + ssa.OpAMD64VPOPCNTDMasked256, + ssa.OpAMD64VPOPCNTDMasked512, + ssa.OpAMD64VPOPCNTQMasked128, + ssa.OpAMD64VPOPCNTQMasked256, + ssa.OpAMD64VPOPCNTQMasked512, + ssa.OpAMD64VRCP14PSMasked128, + ssa.OpAMD64VRCP14PSMasked256, + ssa.OpAMD64VRCP14PSMasked512, + ssa.OpAMD64VRCP14PDMasked128, + ssa.OpAMD64VRCP14PDMasked256, + ssa.OpAMD64VRCP14PDMasked512, + ssa.OpAMD64VRSQRT14PSMasked128, + ssa.OpAMD64VRSQRT14PSMasked256, + ssa.OpAMD64VRSQRT14PSMasked512, + ssa.OpAMD64VRSQRT14PDMasked128, + ssa.OpAMD64VRSQRT14PDMasked256, + ssa.OpAMD64VRSQRT14PDMasked512, + ssa.OpAMD64VPMOVSWBMasked128_128, + ssa.OpAMD64VPMOVSWBMasked128_256, + ssa.OpAMD64VPMOVSWBMasked256, + ssa.OpAMD64VPMOVSDBMasked128_128, + ssa.OpAMD64VPMOVSDBMasked128_256, + ssa.OpAMD64VPMOVSDBMasked128_512, + ssa.OpAMD64VPMOVSQBMasked128_128, + ssa.OpAMD64VPMOVSQBMasked128_256, + ssa.OpAMD64VPMOVSQBMasked128_512, + ssa.OpAMD64VPMOVSDWMasked128_128, + ssa.OpAMD64VPMOVSDWMasked128_256, + ssa.OpAMD64VPMOVSDWMasked256, + ssa.OpAMD64VPMOVSQWMasked128_128, + ssa.OpAMD64VPMOVSQWMasked128_256, + ssa.OpAMD64VPMOVSQWMasked128_512, + ssa.OpAMD64VPMOVSQDMasked128_128, + ssa.OpAMD64VPMOVSQDMasked128_256, + ssa.OpAMD64VPMOVSQDMasked256, + ssa.OpAMD64VPMOVUSWBMasked128_128, + ssa.OpAMD64VPMOVUSWBMasked128_256, + ssa.OpAMD64VPMOVUSWBMasked256, + ssa.OpAMD64VPMOVUSDBMasked128_128, + ssa.OpAMD64VPMOVUSDBMasked128_256, + ssa.OpAMD64VPMOVUSDBMasked128_512, + ssa.OpAMD64VPMOVUSQBMasked128_128, + ssa.OpAMD64VPMOVUSQBMasked128_256, + ssa.OpAMD64VPMOVUSQBMasked128_512, + ssa.OpAMD64VPMOVUSDWMasked128_128, + ssa.OpAMD64VPMOVUSDWMasked128_256, + ssa.OpAMD64VPMOVUSDWMasked256, + ssa.OpAMD64VPMOVUSQWMasked128_128, + ssa.OpAMD64VPMOVUSQWMasked128_256, + ssa.OpAMD64VPMOVUSQWMasked128_512, + ssa.OpAMD64VPMOVUSQDMasked128_128, + ssa.OpAMD64VPMOVUSQDMasked128_256, + ssa.OpAMD64VPMOVUSQDMasked256, + ssa.OpAMD64VSQRTPSMasked128, + ssa.OpAMD64VSQRTPSMasked256, + ssa.OpAMD64VSQRTPSMasked512, + ssa.OpAMD64VSQRTPDMasked128, + ssa.OpAMD64VSQRTPDMasked256, + ssa.OpAMD64VSQRTPDMasked512, + ssa.OpAMD64VPMOVWBMasked128_128, + ssa.OpAMD64VPMOVWBMasked128_256, + ssa.OpAMD64VPMOVWBMasked256, + ssa.OpAMD64VPMOVDBMasked128_128, + ssa.OpAMD64VPMOVDBMasked128_256, + ssa.OpAMD64VPMOVDBMasked128_512, + ssa.OpAMD64VPMOVQBMasked128_128, + ssa.OpAMD64VPMOVQBMasked128_256, + ssa.OpAMD64VPMOVQBMasked128_512, + ssa.OpAMD64VPMOVDWMasked128_128, + ssa.OpAMD64VPMOVDWMasked128_256, + ssa.OpAMD64VPMOVDWMasked256, + ssa.OpAMD64VPMOVQWMasked128_128, + ssa.OpAMD64VPMOVQWMasked128_256, + ssa.OpAMD64VPMOVQWMasked128_512, + ssa.OpAMD64VPMOVQDMasked128_128, + ssa.OpAMD64VPMOVQDMasked128_256, + ssa.OpAMD64VPMOVQDMasked256, + ssa.OpAMD64VPBROADCASTQMasked128, + ssa.OpAMD64VBROADCASTSSMasked128, + ssa.OpAMD64VBROADCASTSDMasked256, + ssa.OpAMD64VPBROADCASTDMasked128, + ssa.OpAMD64VPBROADCASTQMasked256, + ssa.OpAMD64VBROADCASTSSMasked256, + ssa.OpAMD64VBROADCASTSDMasked512, + ssa.OpAMD64VPBROADCASTWMasked128, + ssa.OpAMD64VPBROADCASTDMasked256, + ssa.OpAMD64VPBROADCASTQMasked512, + ssa.OpAMD64VBROADCASTSSMasked512, + ssa.OpAMD64VPBROADCASTBMasked128, + ssa.OpAMD64VPBROADCASTWMasked256, + ssa.OpAMD64VPBROADCASTDMasked512, + ssa.OpAMD64VPBROADCASTBMasked256, + ssa.OpAMD64VPBROADCASTWMasked512, + ssa.OpAMD64VPBROADCASTBMasked512, + ssa.OpAMD64VMOVDQU8Masked128, + ssa.OpAMD64VMOVDQU8Masked256, + ssa.OpAMD64VMOVDQU8Masked512, + ssa.OpAMD64VMOVDQU16Masked128, + ssa.OpAMD64VMOVDQU16Masked256, + ssa.OpAMD64VMOVDQU16Masked512, + ssa.OpAMD64VMOVDQU32Masked128, + ssa.OpAMD64VMOVDQU32Masked256, + ssa.OpAMD64VMOVDQU32Masked512, + ssa.OpAMD64VMOVDQU64Masked128, + ssa.OpAMD64VMOVDQU64Masked256, + ssa.OpAMD64VMOVDQU64Masked512: + p = simdVkv(s, v) + + case ssa.OpAMD64VPBLENDVB128, + ssa.OpAMD64VPBLENDVB256: + p = simdV31(s, v) + + case ssa.OpAMD64VAESKEYGENASSIST128, + ssa.OpAMD64VROUNDPS128, + ssa.OpAMD64VROUNDPS256, + ssa.OpAMD64VROUNDPD128, + ssa.OpAMD64VROUNDPD256, + ssa.OpAMD64VRNDSCALEPS128, + ssa.OpAMD64VRNDSCALEPS256, + ssa.OpAMD64VRNDSCALEPS512, + ssa.OpAMD64VRNDSCALEPD128, + ssa.OpAMD64VRNDSCALEPD256, + ssa.OpAMD64VRNDSCALEPD512, + ssa.OpAMD64VREDUCEPS128, + ssa.OpAMD64VREDUCEPS256, + ssa.OpAMD64VREDUCEPS512, + ssa.OpAMD64VREDUCEPD128, + ssa.OpAMD64VREDUCEPD256, + ssa.OpAMD64VREDUCEPD512, + ssa.OpAMD64VEXTRACTF128128, + ssa.OpAMD64VEXTRACTF64X4256, + ssa.OpAMD64VEXTRACTI128128, + ssa.OpAMD64VEXTRACTI64X4256, + ssa.OpAMD64VPSHUFD128, + ssa.OpAMD64VPSHUFD256, + ssa.OpAMD64VPSHUFD512, + ssa.OpAMD64VPSHUFHW128, + ssa.OpAMD64VPSHUFHW256, + ssa.OpAMD64VPSHUFHW512, + ssa.OpAMD64VPSHUFLW128, + ssa.OpAMD64VPSHUFLW256, + ssa.OpAMD64VPSHUFLW512, + ssa.OpAMD64VPROLD128, + ssa.OpAMD64VPROLD256, + ssa.OpAMD64VPROLD512, + ssa.OpAMD64VPROLQ128, + ssa.OpAMD64VPROLQ256, + ssa.OpAMD64VPROLQ512, + ssa.OpAMD64VPRORD128, + ssa.OpAMD64VPRORD256, + ssa.OpAMD64VPRORD512, + ssa.OpAMD64VPRORQ128, + ssa.OpAMD64VPRORQ256, + ssa.OpAMD64VPRORQ512, + ssa.OpAMD64VPSLLW128const, + ssa.OpAMD64VPSLLW256const, + ssa.OpAMD64VPSLLW512const, + ssa.OpAMD64VPSLLD128const, + ssa.OpAMD64VPSLLD256const, + ssa.OpAMD64VPSLLD512const, + ssa.OpAMD64VPSLLQ128const, + ssa.OpAMD64VPSLLQ256const, + ssa.OpAMD64VPSLLQ512const, + ssa.OpAMD64VPSRAW128const, + ssa.OpAMD64VPSRAW256const, + ssa.OpAMD64VPSRAW512const, + ssa.OpAMD64VPSRAD128const, + ssa.OpAMD64VPSRAD256const, + ssa.OpAMD64VPSRAD512const, + ssa.OpAMD64VPSRAQ128const, + ssa.OpAMD64VPSRAQ256const, + ssa.OpAMD64VPSRAQ512const, + ssa.OpAMD64VPSRLW128const, + ssa.OpAMD64VPSRLW256const, + ssa.OpAMD64VPSRLW512const, + ssa.OpAMD64VPSRLD128const, + ssa.OpAMD64VPSRLD256const, + ssa.OpAMD64VPSRLD512const, + ssa.OpAMD64VPSRLQ128const, + ssa.OpAMD64VPSRLQ256const, + ssa.OpAMD64VPSRLQ512const: + p = simdV11Imm8(s, v) + + case ssa.OpAMD64VRNDSCALEPSMasked128, + ssa.OpAMD64VRNDSCALEPSMasked256, + ssa.OpAMD64VRNDSCALEPSMasked512, + ssa.OpAMD64VRNDSCALEPDMasked128, + ssa.OpAMD64VRNDSCALEPDMasked256, + ssa.OpAMD64VRNDSCALEPDMasked512, + ssa.OpAMD64VREDUCEPSMasked128, + ssa.OpAMD64VREDUCEPSMasked256, + ssa.OpAMD64VREDUCEPSMasked512, + ssa.OpAMD64VREDUCEPDMasked128, + ssa.OpAMD64VREDUCEPDMasked256, + ssa.OpAMD64VREDUCEPDMasked512, + ssa.OpAMD64VPSHUFDMasked256, + ssa.OpAMD64VPSHUFDMasked512, + ssa.OpAMD64VPSHUFHWMasked256, + ssa.OpAMD64VPSHUFHWMasked512, + ssa.OpAMD64VPSHUFHWMasked128, + ssa.OpAMD64VPSHUFLWMasked256, + ssa.OpAMD64VPSHUFLWMasked512, + ssa.OpAMD64VPSHUFLWMasked128, + ssa.OpAMD64VPSHUFDMasked128, + ssa.OpAMD64VPROLDMasked128, + ssa.OpAMD64VPROLDMasked256, + ssa.OpAMD64VPROLDMasked512, + ssa.OpAMD64VPROLQMasked128, + ssa.OpAMD64VPROLQMasked256, + ssa.OpAMD64VPROLQMasked512, + ssa.OpAMD64VPRORDMasked128, + ssa.OpAMD64VPRORDMasked256, + ssa.OpAMD64VPRORDMasked512, + ssa.OpAMD64VPRORQMasked128, + ssa.OpAMD64VPRORQMasked256, + ssa.OpAMD64VPRORQMasked512, + ssa.OpAMD64VPSLLWMasked128const, + ssa.OpAMD64VPSLLWMasked256const, + ssa.OpAMD64VPSLLWMasked512const, + ssa.OpAMD64VPSLLDMasked128const, + ssa.OpAMD64VPSLLDMasked256const, + ssa.OpAMD64VPSLLDMasked512const, + ssa.OpAMD64VPSLLQMasked128const, + ssa.OpAMD64VPSLLQMasked256const, + ssa.OpAMD64VPSLLQMasked512const, + ssa.OpAMD64VPSRAWMasked128const, + ssa.OpAMD64VPSRAWMasked256const, + ssa.OpAMD64VPSRAWMasked512const, + ssa.OpAMD64VPSRADMasked128const, + ssa.OpAMD64VPSRADMasked256const, + ssa.OpAMD64VPSRADMasked512const, + ssa.OpAMD64VPSRAQMasked128const, + ssa.OpAMD64VPSRAQMasked256const, + ssa.OpAMD64VPSRAQMasked512const, + ssa.OpAMD64VPSRLWMasked128const, + ssa.OpAMD64VPSRLWMasked256const, + ssa.OpAMD64VPSRLWMasked512const, + ssa.OpAMD64VPSRLDMasked128const, + ssa.OpAMD64VPSRLDMasked256const, + ssa.OpAMD64VPSRLDMasked512const, + ssa.OpAMD64VPSRLQMasked128const, + ssa.OpAMD64VPSRLQMasked256const, + ssa.OpAMD64VPSRLQMasked512const: + p = simdVkvImm8(s, v) + + case ssa.OpAMD64VPERM2F128256, + ssa.OpAMD64VPERM2I128256, + ssa.OpAMD64VPALIGNR128, + ssa.OpAMD64VPALIGNR256, + ssa.OpAMD64VPALIGNR512, + ssa.OpAMD64VCMPPS128, + ssa.OpAMD64VCMPPS256, + ssa.OpAMD64VCMPPD128, + ssa.OpAMD64VCMPPD256, + ssa.OpAMD64VGF2P8AFFINEQB128, + ssa.OpAMD64VGF2P8AFFINEQB256, + ssa.OpAMD64VGF2P8AFFINEQB512, + ssa.OpAMD64VGF2P8AFFINEINVQB128, + ssa.OpAMD64VGF2P8AFFINEINVQB256, + ssa.OpAMD64VGF2P8AFFINEINVQB512, + ssa.OpAMD64VINSERTF128256, + ssa.OpAMD64VINSERTF64X4512, + ssa.OpAMD64VINSERTI128256, + ssa.OpAMD64VINSERTI64X4512, + ssa.OpAMD64VPSHLDW128, + ssa.OpAMD64VPSHLDW256, + ssa.OpAMD64VPSHLDW512, + ssa.OpAMD64VPSHLDD128, + ssa.OpAMD64VPSHLDD256, + ssa.OpAMD64VPSHLDD512, + ssa.OpAMD64VPSHLDQ128, + ssa.OpAMD64VPSHLDQ256, + ssa.OpAMD64VPSHLDQ512, + ssa.OpAMD64VPSHRDW128, + ssa.OpAMD64VPSHRDW256, + ssa.OpAMD64VPSHRDW512, + ssa.OpAMD64VPSHRDD128, + ssa.OpAMD64VPSHRDD256, + ssa.OpAMD64VPSHRDD512, + ssa.OpAMD64VPSHRDQ128, + ssa.OpAMD64VPSHRDQ256, + ssa.OpAMD64VPSHRDQ512, + ssa.OpAMD64VPCLMULQDQ128, + ssa.OpAMD64VPCLMULQDQ256, + ssa.OpAMD64VPCLMULQDQ512, + ssa.OpAMD64VSHUFPS128, + ssa.OpAMD64VSHUFPD128, + ssa.OpAMD64VSHUFPS256, + ssa.OpAMD64VSHUFPS512, + ssa.OpAMD64VSHUFPD256, + ssa.OpAMD64VSHUFPD512: + p = simdV21Imm8(s, v) + + case ssa.OpAMD64VCMPPS512, + ssa.OpAMD64VCMPPD512, + ssa.OpAMD64VPCMPUB512, + ssa.OpAMD64VPCMPUW512, + ssa.OpAMD64VPCMPUD512, + ssa.OpAMD64VPCMPUQ512, + ssa.OpAMD64VPCMPB512, + ssa.OpAMD64VPCMPW512, + ssa.OpAMD64VPCMPD512, + ssa.OpAMD64VPCMPQ512: + p = simdV2kImm8(s, v) + + case ssa.OpAMD64VCMPPSMasked128, + ssa.OpAMD64VCMPPSMasked256, + ssa.OpAMD64VCMPPSMasked512, + ssa.OpAMD64VCMPPDMasked128, + ssa.OpAMD64VCMPPDMasked256, + ssa.OpAMD64VCMPPDMasked512, + ssa.OpAMD64VPCMPBMasked128, + ssa.OpAMD64VPCMPBMasked256, + ssa.OpAMD64VPCMPBMasked512, + ssa.OpAMD64VPCMPWMasked128, + ssa.OpAMD64VPCMPWMasked256, + ssa.OpAMD64VPCMPWMasked512, + ssa.OpAMD64VPCMPDMasked128, + ssa.OpAMD64VPCMPDMasked256, + ssa.OpAMD64VPCMPDMasked512, + ssa.OpAMD64VPCMPQMasked128, + ssa.OpAMD64VPCMPQMasked256, + ssa.OpAMD64VPCMPQMasked512, + ssa.OpAMD64VPCMPUBMasked128, + ssa.OpAMD64VPCMPUBMasked256, + ssa.OpAMD64VPCMPUBMasked512, + ssa.OpAMD64VPCMPUWMasked128, + ssa.OpAMD64VPCMPUWMasked256, + ssa.OpAMD64VPCMPUWMasked512, + ssa.OpAMD64VPCMPUDMasked128, + ssa.OpAMD64VPCMPUDMasked256, + ssa.OpAMD64VPCMPUDMasked512, + ssa.OpAMD64VPCMPUQMasked128, + ssa.OpAMD64VPCMPUQMasked256, + ssa.OpAMD64VPCMPUQMasked512: + p = simdV2kkImm8(s, v) + + case ssa.OpAMD64VPDPWSSD128, + ssa.OpAMD64VPDPWSSD256, + ssa.OpAMD64VPDPWSSD512, + ssa.OpAMD64VPERMI2B128, + ssa.OpAMD64VPERMI2B256, + ssa.OpAMD64VPERMI2B512, + ssa.OpAMD64VPERMI2W128, + ssa.OpAMD64VPERMI2W256, + ssa.OpAMD64VPERMI2W512, + ssa.OpAMD64VPERMI2PS128, + ssa.OpAMD64VPERMI2D128, + ssa.OpAMD64VPERMI2PS256, + ssa.OpAMD64VPERMI2D256, + ssa.OpAMD64VPERMI2PS512, + ssa.OpAMD64VPERMI2D512, + ssa.OpAMD64VPERMI2PD128, + ssa.OpAMD64VPERMI2Q128, + ssa.OpAMD64VPERMI2PD256, + ssa.OpAMD64VPERMI2Q256, + ssa.OpAMD64VPERMI2PD512, + ssa.OpAMD64VPERMI2Q512, + ssa.OpAMD64VFMADD213PS128, + ssa.OpAMD64VFMADD213PS256, + ssa.OpAMD64VFMADD213PS512, + ssa.OpAMD64VFMADD213PD128, + ssa.OpAMD64VFMADD213PD256, + ssa.OpAMD64VFMADD213PD512, + ssa.OpAMD64VFMADDSUB213PS128, + ssa.OpAMD64VFMADDSUB213PS256, + ssa.OpAMD64VFMADDSUB213PS512, + ssa.OpAMD64VFMADDSUB213PD128, + ssa.OpAMD64VFMADDSUB213PD256, + ssa.OpAMD64VFMADDSUB213PD512, + ssa.OpAMD64VFMSUBADD213PS128, + ssa.OpAMD64VFMSUBADD213PS256, + ssa.OpAMD64VFMSUBADD213PS512, + ssa.OpAMD64VFMSUBADD213PD128, + ssa.OpAMD64VFMSUBADD213PD256, + ssa.OpAMD64VFMSUBADD213PD512, + ssa.OpAMD64VPSHLDVW128, + ssa.OpAMD64VPSHLDVW256, + ssa.OpAMD64VPSHLDVW512, + ssa.OpAMD64VPSHLDVD128, + ssa.OpAMD64VPSHLDVD256, + ssa.OpAMD64VPSHLDVD512, + ssa.OpAMD64VPSHLDVQ128, + ssa.OpAMD64VPSHLDVQ256, + ssa.OpAMD64VPSHLDVQ512, + ssa.OpAMD64VPSHRDVW128, + ssa.OpAMD64VPSHRDVW256, + ssa.OpAMD64VPSHRDVW512, + ssa.OpAMD64VPSHRDVD128, + ssa.OpAMD64VPSHRDVD256, + ssa.OpAMD64VPSHRDVD512, + ssa.OpAMD64VPSHRDVQ128, + ssa.OpAMD64VPSHRDVQ256, + ssa.OpAMD64VPSHRDVQ512: + p = simdV31ResultInArg0(s, v) + + case ssa.OpAMD64VPDPWSSDMasked128, + ssa.OpAMD64VPDPWSSDMasked256, + ssa.OpAMD64VPDPWSSDMasked512, + ssa.OpAMD64VADDPSMasked128Merging, + ssa.OpAMD64VADDPSMasked256Merging, + ssa.OpAMD64VADDPSMasked512Merging, + ssa.OpAMD64VADDPDMasked128Merging, + ssa.OpAMD64VADDPDMasked256Merging, + ssa.OpAMD64VADDPDMasked512Merging, + ssa.OpAMD64VPADDBMasked128Merging, + ssa.OpAMD64VPADDBMasked256Merging, + ssa.OpAMD64VPADDBMasked512Merging, + ssa.OpAMD64VPADDWMasked128Merging, + ssa.OpAMD64VPADDWMasked256Merging, + ssa.OpAMD64VPADDWMasked512Merging, + ssa.OpAMD64VPADDDMasked128Merging, + ssa.OpAMD64VPADDDMasked256Merging, + ssa.OpAMD64VPADDDMasked512Merging, + ssa.OpAMD64VPADDQMasked128Merging, + ssa.OpAMD64VPADDQMasked256Merging, + ssa.OpAMD64VPADDQMasked512Merging, + ssa.OpAMD64VPADDSBMasked128Merging, + ssa.OpAMD64VPADDSBMasked256Merging, + ssa.OpAMD64VPADDSBMasked512Merging, + ssa.OpAMD64VPADDSWMasked128Merging, + ssa.OpAMD64VPADDSWMasked256Merging, + ssa.OpAMD64VPADDSWMasked512Merging, + ssa.OpAMD64VPADDUSBMasked128Merging, + ssa.OpAMD64VPADDUSBMasked256Merging, + ssa.OpAMD64VPADDUSBMasked512Merging, + ssa.OpAMD64VPADDUSWMasked128Merging, + ssa.OpAMD64VPADDUSWMasked256Merging, + ssa.OpAMD64VPADDUSWMasked512Merging, + ssa.OpAMD64VPANDDMasked128Merging, + ssa.OpAMD64VPANDDMasked256Merging, + ssa.OpAMD64VPANDDMasked512Merging, + ssa.OpAMD64VPANDQMasked128Merging, + ssa.OpAMD64VPANDQMasked256Merging, + ssa.OpAMD64VPANDQMasked512Merging, + ssa.OpAMD64VPAVGBMasked128Merging, + ssa.OpAMD64VPAVGBMasked256Merging, + ssa.OpAMD64VPAVGBMasked512Merging, + ssa.OpAMD64VPAVGWMasked128Merging, + ssa.OpAMD64VPAVGWMasked256Merging, + ssa.OpAMD64VPAVGWMasked512Merging, + ssa.OpAMD64VPERMI2BMasked128, + ssa.OpAMD64VPERMI2BMasked256, + ssa.OpAMD64VPERMI2BMasked512, + ssa.OpAMD64VPERMI2WMasked128, + ssa.OpAMD64VPERMI2WMasked256, + ssa.OpAMD64VPERMI2WMasked512, + ssa.OpAMD64VPERMI2PSMasked128, + ssa.OpAMD64VPERMI2DMasked128, + ssa.OpAMD64VPERMI2PSMasked256, + ssa.OpAMD64VPERMI2DMasked256, + ssa.OpAMD64VPERMI2PSMasked512, + ssa.OpAMD64VPERMI2DMasked512, + ssa.OpAMD64VPERMI2PDMasked128, + ssa.OpAMD64VPERMI2QMasked128, + ssa.OpAMD64VPERMI2PDMasked256, + ssa.OpAMD64VPERMI2QMasked256, + ssa.OpAMD64VPERMI2PDMasked512, + ssa.OpAMD64VPERMI2QMasked512, + ssa.OpAMD64VDIVPSMasked128Merging, + ssa.OpAMD64VDIVPSMasked256Merging, + ssa.OpAMD64VDIVPSMasked512Merging, + ssa.OpAMD64VDIVPDMasked128Merging, + ssa.OpAMD64VDIVPDMasked256Merging, + ssa.OpAMD64VDIVPDMasked512Merging, + ssa.OpAMD64VPMADDWDMasked128Merging, + ssa.OpAMD64VPMADDWDMasked256Merging, + ssa.OpAMD64VPMADDWDMasked512Merging, + ssa.OpAMD64VPMADDUBSWMasked128Merging, + ssa.OpAMD64VPMADDUBSWMasked256Merging, + ssa.OpAMD64VPMADDUBSWMasked512Merging, + ssa.OpAMD64VGF2P8MULBMasked128Merging, + ssa.OpAMD64VGF2P8MULBMasked256Merging, + ssa.OpAMD64VGF2P8MULBMasked512Merging, + ssa.OpAMD64VMAXPSMasked128Merging, + ssa.OpAMD64VMAXPSMasked256Merging, + ssa.OpAMD64VMAXPSMasked512Merging, + ssa.OpAMD64VMAXPDMasked128Merging, + ssa.OpAMD64VMAXPDMasked256Merging, + ssa.OpAMD64VMAXPDMasked512Merging, + ssa.OpAMD64VPMAXSBMasked128Merging, + ssa.OpAMD64VPMAXSBMasked256Merging, + ssa.OpAMD64VPMAXSBMasked512Merging, + ssa.OpAMD64VPMAXSWMasked128Merging, + ssa.OpAMD64VPMAXSWMasked256Merging, + ssa.OpAMD64VPMAXSWMasked512Merging, + ssa.OpAMD64VPMAXSDMasked128Merging, + ssa.OpAMD64VPMAXSDMasked256Merging, + ssa.OpAMD64VPMAXSDMasked512Merging, + ssa.OpAMD64VPMAXSQMasked128Merging, + ssa.OpAMD64VPMAXSQMasked256Merging, + ssa.OpAMD64VPMAXSQMasked512Merging, + ssa.OpAMD64VPMAXUBMasked128Merging, + ssa.OpAMD64VPMAXUBMasked256Merging, + ssa.OpAMD64VPMAXUBMasked512Merging, + ssa.OpAMD64VPMAXUWMasked128Merging, + ssa.OpAMD64VPMAXUWMasked256Merging, + ssa.OpAMD64VPMAXUWMasked512Merging, + ssa.OpAMD64VPMAXUDMasked128Merging, + ssa.OpAMD64VPMAXUDMasked256Merging, + ssa.OpAMD64VPMAXUDMasked512Merging, + ssa.OpAMD64VPMAXUQMasked128Merging, + ssa.OpAMD64VPMAXUQMasked256Merging, + ssa.OpAMD64VPMAXUQMasked512Merging, + ssa.OpAMD64VMINPSMasked128Merging, + ssa.OpAMD64VMINPSMasked256Merging, + ssa.OpAMD64VMINPSMasked512Merging, + ssa.OpAMD64VMINPDMasked128Merging, + ssa.OpAMD64VMINPDMasked256Merging, + ssa.OpAMD64VMINPDMasked512Merging, + ssa.OpAMD64VPMINSBMasked128Merging, + ssa.OpAMD64VPMINSBMasked256Merging, + ssa.OpAMD64VPMINSBMasked512Merging, + ssa.OpAMD64VPMINSWMasked128Merging, + ssa.OpAMD64VPMINSWMasked256Merging, + ssa.OpAMD64VPMINSWMasked512Merging, + ssa.OpAMD64VPMINSDMasked128Merging, + ssa.OpAMD64VPMINSDMasked256Merging, + ssa.OpAMD64VPMINSDMasked512Merging, + ssa.OpAMD64VPMINSQMasked128Merging, + ssa.OpAMD64VPMINSQMasked256Merging, + ssa.OpAMD64VPMINSQMasked512Merging, + ssa.OpAMD64VPMINUBMasked128Merging, + ssa.OpAMD64VPMINUBMasked256Merging, + ssa.OpAMD64VPMINUBMasked512Merging, + ssa.OpAMD64VPMINUWMasked128Merging, + ssa.OpAMD64VPMINUWMasked256Merging, + ssa.OpAMD64VPMINUWMasked512Merging, + ssa.OpAMD64VPMINUDMasked128Merging, + ssa.OpAMD64VPMINUDMasked256Merging, + ssa.OpAMD64VPMINUDMasked512Merging, + ssa.OpAMD64VPMINUQMasked128Merging, + ssa.OpAMD64VPMINUQMasked256Merging, + ssa.OpAMD64VPMINUQMasked512Merging, + ssa.OpAMD64VFMADDSUB213PSMasked128, + ssa.OpAMD64VFMADDSUB213PSMasked256, + ssa.OpAMD64VFMADDSUB213PSMasked512, + ssa.OpAMD64VFMADDSUB213PDMasked128, + ssa.OpAMD64VFMADDSUB213PDMasked256, + ssa.OpAMD64VFMADDSUB213PDMasked512, + ssa.OpAMD64VFMADD213PSMasked128, + ssa.OpAMD64VFMADD213PSMasked256, + ssa.OpAMD64VFMADD213PSMasked512, + ssa.OpAMD64VFMADD213PDMasked128, + ssa.OpAMD64VFMADD213PDMasked256, + ssa.OpAMD64VFMADD213PDMasked512, + ssa.OpAMD64VFMSUBADD213PSMasked128, + ssa.OpAMD64VFMSUBADD213PSMasked256, + ssa.OpAMD64VFMSUBADD213PSMasked512, + ssa.OpAMD64VFMSUBADD213PDMasked128, + ssa.OpAMD64VFMSUBADD213PDMasked256, + ssa.OpAMD64VFMSUBADD213PDMasked512, + ssa.OpAMD64VPMULHWMasked128Merging, + ssa.OpAMD64VPMULHWMasked256Merging, + ssa.OpAMD64VPMULHWMasked512Merging, + ssa.OpAMD64VPMULHUWMasked128Merging, + ssa.OpAMD64VPMULHUWMasked256Merging, + ssa.OpAMD64VPMULHUWMasked512Merging, + ssa.OpAMD64VMULPSMasked128Merging, + ssa.OpAMD64VMULPSMasked256Merging, + ssa.OpAMD64VMULPSMasked512Merging, + ssa.OpAMD64VMULPDMasked128Merging, + ssa.OpAMD64VMULPDMasked256Merging, + ssa.OpAMD64VMULPDMasked512Merging, + ssa.OpAMD64VPMULLWMasked128Merging, + ssa.OpAMD64VPMULLWMasked256Merging, + ssa.OpAMD64VPMULLWMasked512Merging, + ssa.OpAMD64VPMULLDMasked128Merging, + ssa.OpAMD64VPMULLDMasked256Merging, + ssa.OpAMD64VPMULLDMasked512Merging, + ssa.OpAMD64VPMULLQMasked128Merging, + ssa.OpAMD64VPMULLQMasked256Merging, + ssa.OpAMD64VPMULLQMasked512Merging, + ssa.OpAMD64VPORDMasked128Merging, + ssa.OpAMD64VPORDMasked256Merging, + ssa.OpAMD64VPORDMasked512Merging, + ssa.OpAMD64VPORQMasked128Merging, + ssa.OpAMD64VPORQMasked256Merging, + ssa.OpAMD64VPORQMasked512Merging, + ssa.OpAMD64VPSHUFBMasked256Merging, + ssa.OpAMD64VPSHUFBMasked512Merging, + ssa.OpAMD64VPSHUFBMasked128Merging, + ssa.OpAMD64VPROLVDMasked128Merging, + ssa.OpAMD64VPROLVDMasked256Merging, + ssa.OpAMD64VPROLVDMasked512Merging, + ssa.OpAMD64VPROLVQMasked128Merging, + ssa.OpAMD64VPROLVQMasked256Merging, + ssa.OpAMD64VPROLVQMasked512Merging, + ssa.OpAMD64VPRORVDMasked128Merging, + ssa.OpAMD64VPRORVDMasked256Merging, + ssa.OpAMD64VPRORVDMasked512Merging, + ssa.OpAMD64VPRORVQMasked128Merging, + ssa.OpAMD64VPRORVQMasked256Merging, + ssa.OpAMD64VPRORVQMasked512Merging, + ssa.OpAMD64VPACKSSDWMasked256Merging, + ssa.OpAMD64VPACKSSDWMasked512Merging, + ssa.OpAMD64VPACKSSDWMasked128Merging, + ssa.OpAMD64VPACKUSDWMasked256Merging, + ssa.OpAMD64VPACKUSDWMasked512Merging, + ssa.OpAMD64VPACKUSDWMasked128Merging, + ssa.OpAMD64VSCALEFPSMasked128Merging, + ssa.OpAMD64VSCALEFPSMasked256Merging, + ssa.OpAMD64VSCALEFPSMasked512Merging, + ssa.OpAMD64VSCALEFPDMasked128Merging, + ssa.OpAMD64VSCALEFPDMasked256Merging, + ssa.OpAMD64VSCALEFPDMasked512Merging, + ssa.OpAMD64VPSHLDVWMasked128, + ssa.OpAMD64VPSHLDVWMasked256, + ssa.OpAMD64VPSHLDVWMasked512, + ssa.OpAMD64VPSHLDVDMasked128, + ssa.OpAMD64VPSHLDVDMasked256, + ssa.OpAMD64VPSHLDVDMasked512, + ssa.OpAMD64VPSHLDVQMasked128, + ssa.OpAMD64VPSHLDVQMasked256, + ssa.OpAMD64VPSHLDVQMasked512, + ssa.OpAMD64VPSLLVWMasked128Merging, + ssa.OpAMD64VPSLLVWMasked256Merging, + ssa.OpAMD64VPSLLVWMasked512Merging, + ssa.OpAMD64VPSLLVDMasked128Merging, + ssa.OpAMD64VPSLLVDMasked256Merging, + ssa.OpAMD64VPSLLVDMasked512Merging, + ssa.OpAMD64VPSLLVQMasked128Merging, + ssa.OpAMD64VPSLLVQMasked256Merging, + ssa.OpAMD64VPSLLVQMasked512Merging, + ssa.OpAMD64VPSHRDVWMasked128, + ssa.OpAMD64VPSHRDVWMasked256, + ssa.OpAMD64VPSHRDVWMasked512, + ssa.OpAMD64VPSHRDVDMasked128, + ssa.OpAMD64VPSHRDVDMasked256, + ssa.OpAMD64VPSHRDVDMasked512, + ssa.OpAMD64VPSHRDVQMasked128, + ssa.OpAMD64VPSHRDVQMasked256, + ssa.OpAMD64VPSHRDVQMasked512, + ssa.OpAMD64VPSRAVWMasked128Merging, + ssa.OpAMD64VPSRAVWMasked256Merging, + ssa.OpAMD64VPSRAVWMasked512Merging, + ssa.OpAMD64VPSRAVDMasked128Merging, + ssa.OpAMD64VPSRAVDMasked256Merging, + ssa.OpAMD64VPSRAVDMasked512Merging, + ssa.OpAMD64VPSRAVQMasked128Merging, + ssa.OpAMD64VPSRAVQMasked256Merging, + ssa.OpAMD64VPSRAVQMasked512Merging, + ssa.OpAMD64VPSRLVWMasked128Merging, + ssa.OpAMD64VPSRLVWMasked256Merging, + ssa.OpAMD64VPSRLVWMasked512Merging, + ssa.OpAMD64VPSRLVDMasked128Merging, + ssa.OpAMD64VPSRLVDMasked256Merging, + ssa.OpAMD64VPSRLVDMasked512Merging, + ssa.OpAMD64VPSRLVQMasked128Merging, + ssa.OpAMD64VPSRLVQMasked256Merging, + ssa.OpAMD64VPSRLVQMasked512Merging, + ssa.OpAMD64VSUBPSMasked128Merging, + ssa.OpAMD64VSUBPSMasked256Merging, + ssa.OpAMD64VSUBPSMasked512Merging, + ssa.OpAMD64VSUBPDMasked128Merging, + ssa.OpAMD64VSUBPDMasked256Merging, + ssa.OpAMD64VSUBPDMasked512Merging, + ssa.OpAMD64VPSUBBMasked128Merging, + ssa.OpAMD64VPSUBBMasked256Merging, + ssa.OpAMD64VPSUBBMasked512Merging, + ssa.OpAMD64VPSUBWMasked128Merging, + ssa.OpAMD64VPSUBWMasked256Merging, + ssa.OpAMD64VPSUBWMasked512Merging, + ssa.OpAMD64VPSUBDMasked128Merging, + ssa.OpAMD64VPSUBDMasked256Merging, + ssa.OpAMD64VPSUBDMasked512Merging, + ssa.OpAMD64VPSUBQMasked128Merging, + ssa.OpAMD64VPSUBQMasked256Merging, + ssa.OpAMD64VPSUBQMasked512Merging, + ssa.OpAMD64VPSUBSBMasked128Merging, + ssa.OpAMD64VPSUBSBMasked256Merging, + ssa.OpAMD64VPSUBSBMasked512Merging, + ssa.OpAMD64VPSUBSWMasked128Merging, + ssa.OpAMD64VPSUBSWMasked256Merging, + ssa.OpAMD64VPSUBSWMasked512Merging, + ssa.OpAMD64VPSUBUSBMasked128Merging, + ssa.OpAMD64VPSUBUSBMasked256Merging, + ssa.OpAMD64VPSUBUSBMasked512Merging, + ssa.OpAMD64VPSUBUSWMasked128Merging, + ssa.OpAMD64VPSUBUSWMasked256Merging, + ssa.OpAMD64VPSUBUSWMasked512Merging, + ssa.OpAMD64VPXORDMasked128Merging, + ssa.OpAMD64VPXORDMasked256Merging, + ssa.OpAMD64VPXORDMasked512Merging, + ssa.OpAMD64VPXORQMasked128Merging, + ssa.OpAMD64VPXORQMasked256Merging, + ssa.OpAMD64VPXORQMasked512Merging: + p = simdV3kvResultInArg0(s, v) + + case ssa.OpAMD64VPSLLW128, + ssa.OpAMD64VPSLLW256, + ssa.OpAMD64VPSLLW512, + ssa.OpAMD64VPSLLD128, + ssa.OpAMD64VPSLLD256, + ssa.OpAMD64VPSLLD512, + ssa.OpAMD64VPSLLQ128, + ssa.OpAMD64VPSLLQ256, + ssa.OpAMD64VPSLLQ512, + ssa.OpAMD64VPSRAW128, + ssa.OpAMD64VPSRAW256, + ssa.OpAMD64VPSRAW512, + ssa.OpAMD64VPSRAD128, + ssa.OpAMD64VPSRAD256, + ssa.OpAMD64VPSRAD512, + ssa.OpAMD64VPSRAQ128, + ssa.OpAMD64VPSRAQ256, + ssa.OpAMD64VPSRAQ512, + ssa.OpAMD64VPSRLW128, + ssa.OpAMD64VPSRLW256, + ssa.OpAMD64VPSRLW512, + ssa.OpAMD64VPSRLD128, + ssa.OpAMD64VPSRLD256, + ssa.OpAMD64VPSRLD512, + ssa.OpAMD64VPSRLQ128, + ssa.OpAMD64VPSRLQ256, + ssa.OpAMD64VPSRLQ512: + p = simdVfpv(s, v) + + case ssa.OpAMD64VPSLLWMasked128, + ssa.OpAMD64VPSLLWMasked256, + ssa.OpAMD64VPSLLWMasked512, + ssa.OpAMD64VPSLLDMasked128, + ssa.OpAMD64VPSLLDMasked256, + ssa.OpAMD64VPSLLDMasked512, + ssa.OpAMD64VPSLLQMasked128, + ssa.OpAMD64VPSLLQMasked256, + ssa.OpAMD64VPSLLQMasked512, + ssa.OpAMD64VPSRAWMasked128, + ssa.OpAMD64VPSRAWMasked256, + ssa.OpAMD64VPSRAWMasked512, + ssa.OpAMD64VPSRADMasked128, + ssa.OpAMD64VPSRADMasked256, + ssa.OpAMD64VPSRADMasked512, + ssa.OpAMD64VPSRAQMasked128, + ssa.OpAMD64VPSRAQMasked256, + ssa.OpAMD64VPSRAQMasked512, + ssa.OpAMD64VPSRLWMasked128, + ssa.OpAMD64VPSRLWMasked256, + ssa.OpAMD64VPSRLWMasked512, + ssa.OpAMD64VPSRLDMasked128, + ssa.OpAMD64VPSRLDMasked256, + ssa.OpAMD64VPSRLDMasked512, + ssa.OpAMD64VPSRLQMasked128, + ssa.OpAMD64VPSRLQMasked256, + ssa.OpAMD64VPSRLQMasked512: + p = simdVfpkv(s, v) + + case ssa.OpAMD64VPINSRD128, + ssa.OpAMD64VPINSRQ128, + ssa.OpAMD64VPINSRB128, + ssa.OpAMD64VPINSRW128: + p = simdVgpvImm(s, v) + + case ssa.OpAMD64VPEXTRD128, + ssa.OpAMD64VPEXTRQ128, + ssa.OpAMD64VPEXTRB128, + ssa.OpAMD64VPEXTRW128: + p = simdVgpImm(s, v) + + case ssa.OpAMD64VPALIGNRMasked256, + ssa.OpAMD64VPALIGNRMasked512, + ssa.OpAMD64VPALIGNRMasked128, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked128, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked256, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked512, + ssa.OpAMD64VGF2P8AFFINEQBMasked128, + ssa.OpAMD64VGF2P8AFFINEQBMasked256, + ssa.OpAMD64VGF2P8AFFINEQBMasked512, + ssa.OpAMD64VPSHLDWMasked128, + ssa.OpAMD64VPSHLDWMasked256, + ssa.OpAMD64VPSHLDWMasked512, + ssa.OpAMD64VPSHLDDMasked128, + ssa.OpAMD64VPSHLDDMasked256, + ssa.OpAMD64VPSHLDDMasked512, + ssa.OpAMD64VPSHLDQMasked128, + ssa.OpAMD64VPSHLDQMasked256, + ssa.OpAMD64VPSHLDQMasked512, + ssa.OpAMD64VPSHRDWMasked128, + ssa.OpAMD64VPSHRDWMasked256, + ssa.OpAMD64VPSHRDWMasked512, + ssa.OpAMD64VPSHRDDMasked128, + ssa.OpAMD64VPSHRDDMasked256, + ssa.OpAMD64VPSHRDDMasked512, + ssa.OpAMD64VPSHRDQMasked128, + ssa.OpAMD64VPSHRDQMasked256, + ssa.OpAMD64VPSHRDQMasked512: + p = simdV2kvImm8(s, v) + + case ssa.OpAMD64VPABSBMasked128load, + ssa.OpAMD64VPABSBMasked256load, + ssa.OpAMD64VPABSWMasked128load, + ssa.OpAMD64VPABSWMasked256load, + ssa.OpAMD64VPABSDMasked128load, + ssa.OpAMD64VPABSDMasked256load, + ssa.OpAMD64VPABSDMasked512load, + ssa.OpAMD64VPABSQMasked128load, + ssa.OpAMD64VPABSQMasked256load, + ssa.OpAMD64VPABSQMasked512load, + ssa.OpAMD64VCVTPD2PSXMasked128load, + ssa.OpAMD64VCVTPD2PSYMasked128load, + ssa.OpAMD64VCVTPD2PSMasked256load, + ssa.OpAMD64VCVTDQ2PSMasked128load, + ssa.OpAMD64VCVTDQ2PSMasked256load, + ssa.OpAMD64VCVTDQ2PSMasked512load, + ssa.OpAMD64VCVTQQ2PSXMasked128load, + ssa.OpAMD64VCVTQQ2PSYMasked128load, + ssa.OpAMD64VCVTQQ2PSMasked256load, + ssa.OpAMD64VCVTUDQ2PSMasked128load, + ssa.OpAMD64VCVTUDQ2PSMasked256load, + ssa.OpAMD64VCVTUDQ2PSMasked512load, + ssa.OpAMD64VCVTUQQ2PSXMasked128load, + ssa.OpAMD64VCVTUQQ2PSYMasked128load, + ssa.OpAMD64VCVTUQQ2PSMasked256load, + ssa.OpAMD64VCVTPS2PDMasked256load, + ssa.OpAMD64VCVTPS2PDMasked512load, + ssa.OpAMD64VCVTDQ2PDMasked256load, + ssa.OpAMD64VCVTDQ2PDMasked512load, + ssa.OpAMD64VCVTQQ2PDMasked128load, + ssa.OpAMD64VCVTQQ2PDMasked256load, + ssa.OpAMD64VCVTQQ2PDMasked512load, + ssa.OpAMD64VCVTUDQ2PDMasked256load, + ssa.OpAMD64VCVTUDQ2PDMasked512load, + ssa.OpAMD64VCVTUQQ2PDMasked128load, + ssa.OpAMD64VCVTUQQ2PDMasked256load, + ssa.OpAMD64VCVTUQQ2PDMasked512load, + ssa.OpAMD64VCVTTPS2DQMasked128load, + ssa.OpAMD64VCVTTPS2DQMasked256load, + ssa.OpAMD64VCVTTPS2DQMasked512load, + ssa.OpAMD64VCVTTPD2DQXMasked128load, + ssa.OpAMD64VCVTTPD2DQYMasked128load, + ssa.OpAMD64VCVTTPD2DQMasked256load, + ssa.OpAMD64VCVTTPS2QQMasked256load, + ssa.OpAMD64VCVTTPS2QQMasked512load, + ssa.OpAMD64VCVTTPD2QQMasked128load, + ssa.OpAMD64VCVTTPD2QQMasked256load, + ssa.OpAMD64VCVTTPD2QQMasked512load, + ssa.OpAMD64VCVTTPS2UDQMasked128load, + ssa.OpAMD64VCVTTPS2UDQMasked256load, + ssa.OpAMD64VCVTTPS2UDQMasked512load, + ssa.OpAMD64VCVTTPD2UDQXMasked128load, + ssa.OpAMD64VCVTTPD2UDQYMasked128load, + ssa.OpAMD64VCVTTPD2UDQMasked256load, + ssa.OpAMD64VCVTTPS2UQQMasked256load, + ssa.OpAMD64VCVTTPS2UQQMasked512load, + ssa.OpAMD64VCVTTPD2UQQMasked128load, + ssa.OpAMD64VCVTTPD2UQQMasked256load, + ssa.OpAMD64VCVTTPD2UQQMasked512load, + ssa.OpAMD64VEXPANDPSMasked128load, + ssa.OpAMD64VEXPANDPSMasked256load, + ssa.OpAMD64VEXPANDPDMasked128load, + ssa.OpAMD64VEXPANDPDMasked256load, + ssa.OpAMD64VPEXPANDBMasked128load, + ssa.OpAMD64VPEXPANDBMasked256load, + ssa.OpAMD64VPEXPANDWMasked128load, + ssa.OpAMD64VPEXPANDWMasked256load, + ssa.OpAMD64VPEXPANDDMasked128load, + ssa.OpAMD64VPEXPANDDMasked256load, + ssa.OpAMD64VPEXPANDQMasked128load, + ssa.OpAMD64VPEXPANDQMasked256load, + ssa.OpAMD64VPMOVSXWQMasked128load, + ssa.OpAMD64VPMOVSXDQMasked128load, + ssa.OpAMD64VPMOVZXWQMasked128load, + ssa.OpAMD64VPMOVZXDQMasked128load, + ssa.OpAMD64VPMOVSXBDMasked128load, + ssa.OpAMD64VPMOVSXWDMasked128load, + ssa.OpAMD64VPMOVSXBQMasked256load, + ssa.OpAMD64VPMOVSXWQMasked256load, + ssa.OpAMD64VPMOVZXBDMasked128load, + ssa.OpAMD64VPMOVZXWDMasked128load, + ssa.OpAMD64VPMOVZXBQMasked256load, + ssa.OpAMD64VPMOVZXWQMasked256load, + ssa.OpAMD64VPMOVSXBWMasked128load, + ssa.OpAMD64VPMOVSXBDMasked256load, + ssa.OpAMD64VPMOVSXBQMasked512load, + ssa.OpAMD64VPMOVZXBWMasked128load, + ssa.OpAMD64VPMOVZXBDMasked256load, + ssa.OpAMD64VPMOVZXBQMasked512load, + ssa.OpAMD64VPMOVSXBWMasked256load, + ssa.OpAMD64VPMOVSXBWMasked512load, + ssa.OpAMD64VPMOVSXBDMasked512load, + ssa.OpAMD64VPMOVSXWDMasked256load, + ssa.OpAMD64VPMOVSXWDMasked512load, + ssa.OpAMD64VPMOVSXWQMasked512load, + ssa.OpAMD64VPMOVSXDQMasked256load, + ssa.OpAMD64VPMOVSXDQMasked512load, + ssa.OpAMD64VPMOVZXBWMasked256load, + ssa.OpAMD64VPMOVZXBWMasked512load, + ssa.OpAMD64VPMOVZXBDMasked512load, + ssa.OpAMD64VPMOVZXWDMasked256load, + ssa.OpAMD64VPMOVZXWDMasked512load, + ssa.OpAMD64VPMOVZXWQMasked512load, + ssa.OpAMD64VPMOVZXDQMasked256load, + ssa.OpAMD64VPMOVZXDQMasked512load, + ssa.OpAMD64VPLZCNTDMasked128load, + ssa.OpAMD64VPLZCNTDMasked256load, + ssa.OpAMD64VPLZCNTDMasked512load, + ssa.OpAMD64VPLZCNTQMasked128load, + ssa.OpAMD64VPLZCNTQMasked256load, + ssa.OpAMD64VPLZCNTQMasked512load, + ssa.OpAMD64VPOPCNTBMasked128load, + ssa.OpAMD64VPOPCNTBMasked256load, + ssa.OpAMD64VPOPCNTWMasked128load, + ssa.OpAMD64VPOPCNTWMasked256load, + ssa.OpAMD64VPOPCNTDMasked128load, + ssa.OpAMD64VPOPCNTDMasked256load, + ssa.OpAMD64VPOPCNTDMasked512load, + ssa.OpAMD64VPOPCNTQMasked128load, + ssa.OpAMD64VPOPCNTQMasked256load, + ssa.OpAMD64VPOPCNTQMasked512load, + ssa.OpAMD64VRCP14PSMasked128load, + ssa.OpAMD64VRCP14PSMasked256load, + ssa.OpAMD64VRCP14PSMasked512load, + ssa.OpAMD64VRCP14PDMasked128load, + ssa.OpAMD64VRCP14PDMasked256load, + ssa.OpAMD64VRCP14PDMasked512load, + ssa.OpAMD64VRSQRT14PSMasked128load, + ssa.OpAMD64VRSQRT14PSMasked256load, + ssa.OpAMD64VRSQRT14PSMasked512load, + ssa.OpAMD64VRSQRT14PDMasked128load, + ssa.OpAMD64VRSQRT14PDMasked256load, + ssa.OpAMD64VRSQRT14PDMasked512load, + ssa.OpAMD64VSQRTPSMasked128load, + ssa.OpAMD64VSQRTPSMasked256load, + ssa.OpAMD64VSQRTPSMasked512load, + ssa.OpAMD64VSQRTPDMasked128load, + ssa.OpAMD64VSQRTPDMasked256load, + ssa.OpAMD64VSQRTPDMasked512load, + ssa.OpAMD64VPBROADCASTQMasked128load, + ssa.OpAMD64VBROADCASTSSMasked128load, + ssa.OpAMD64VBROADCASTSDMasked256load, + ssa.OpAMD64VPBROADCASTDMasked128load, + ssa.OpAMD64VPBROADCASTQMasked256load, + ssa.OpAMD64VBROADCASTSSMasked256load, + ssa.OpAMD64VBROADCASTSDMasked512load, + ssa.OpAMD64VPBROADCASTDMasked256load, + ssa.OpAMD64VPBROADCASTQMasked512load, + ssa.OpAMD64VBROADCASTSSMasked512load, + ssa.OpAMD64VPBROADCASTBMasked128load, + ssa.OpAMD64VPBROADCASTDMasked512load, + ssa.OpAMD64VPBROADCASTBMasked256load, + ssa.OpAMD64VPBROADCASTBMasked512load: + p = simdVkvload(s, v) + + case ssa.OpAMD64VAESDECLAST128load, + ssa.OpAMD64VAESDECLAST256load, + ssa.OpAMD64VAESDEC128load, + ssa.OpAMD64VAESDEC256load, + ssa.OpAMD64VAESENCLAST128load, + ssa.OpAMD64VAESENCLAST256load, + ssa.OpAMD64VAESENC128load, + ssa.OpAMD64VAESENC256load, + ssa.OpAMD64VADDPS128load, + ssa.OpAMD64VADDPS256load, + ssa.OpAMD64VADDPS512load, + ssa.OpAMD64VADDPD128load, + ssa.OpAMD64VADDPD256load, + ssa.OpAMD64VADDPD512load, + ssa.OpAMD64VPADDB128load, + ssa.OpAMD64VPADDB256load, + ssa.OpAMD64VPADDW128load, + ssa.OpAMD64VPADDW256load, + ssa.OpAMD64VPADDD128load, + ssa.OpAMD64VPADDD256load, + ssa.OpAMD64VPADDD512load, + ssa.OpAMD64VPADDQ128load, + ssa.OpAMD64VPADDQ256load, + ssa.OpAMD64VPADDQ512load, + ssa.OpAMD64VADDSUBPS128load, + ssa.OpAMD64VADDSUBPS256load, + ssa.OpAMD64VADDSUBPD128load, + ssa.OpAMD64VADDSUBPD256load, + ssa.OpAMD64VPADDSB128load, + ssa.OpAMD64VPADDSB256load, + ssa.OpAMD64VPADDSW128load, + ssa.OpAMD64VPADDSW256load, + ssa.OpAMD64VPADDUSB128load, + ssa.OpAMD64VPADDUSB256load, + ssa.OpAMD64VPADDUSW128load, + ssa.OpAMD64VPADDUSW256load, + ssa.OpAMD64VPAND128load, + ssa.OpAMD64VPAND256load, + ssa.OpAMD64VPANDD512load, + ssa.OpAMD64VPANDQ512load, + ssa.OpAMD64VPANDN128load, + ssa.OpAMD64VPANDN256load, + ssa.OpAMD64VPANDND512load, + ssa.OpAMD64VPANDNQ512load, + ssa.OpAMD64VPAVGB128load, + ssa.OpAMD64VPAVGB256load, + ssa.OpAMD64VPAVGW128load, + ssa.OpAMD64VPAVGW256load, + ssa.OpAMD64VHADDPS128load, + ssa.OpAMD64VHADDPD128load, + ssa.OpAMD64VPHADDW128load, + ssa.OpAMD64VPHADDD128load, + ssa.OpAMD64VHADDPS256load, + ssa.OpAMD64VHADDPD256load, + ssa.OpAMD64VPHADDW256load, + ssa.OpAMD64VPHADDD256load, + ssa.OpAMD64VPHADDSW128load, + ssa.OpAMD64VPHADDSW256load, + ssa.OpAMD64VHSUBPS128load, + ssa.OpAMD64VHSUBPD128load, + ssa.OpAMD64VPHSUBW128load, + ssa.OpAMD64VPHSUBD128load, + ssa.OpAMD64VHSUBPS256load, + ssa.OpAMD64VHSUBPD256load, + ssa.OpAMD64VPHSUBW256load, + ssa.OpAMD64VPHSUBD256load, + ssa.OpAMD64VPHSUBSW128load, + ssa.OpAMD64VPHSUBSW256load, + ssa.OpAMD64VDIVPS128load, + ssa.OpAMD64VDIVPS256load, + ssa.OpAMD64VDIVPS512load, + ssa.OpAMD64VDIVPD128load, + ssa.OpAMD64VDIVPD256load, + ssa.OpAMD64VDIVPD512load, + ssa.OpAMD64VPMADDWD128load, + ssa.OpAMD64VPMADDWD256load, + ssa.OpAMD64VPMADDUBSW128load, + ssa.OpAMD64VPMADDUBSW256load, + ssa.OpAMD64VPCMPEQB128load, + ssa.OpAMD64VPCMPEQB256load, + ssa.OpAMD64VPCMPEQW128load, + ssa.OpAMD64VPCMPEQW256load, + ssa.OpAMD64VPCMPEQD128load, + ssa.OpAMD64VPCMPEQD256load, + ssa.OpAMD64VPCMPEQQ128load, + ssa.OpAMD64VPCMPEQQ256load, + ssa.OpAMD64VGF2P8MULB128load, + ssa.OpAMD64VGF2P8MULB256load, + ssa.OpAMD64VPCMPGTB128load, + ssa.OpAMD64VPCMPGTB256load, + ssa.OpAMD64VPCMPGTW128load, + ssa.OpAMD64VPCMPGTW256load, + ssa.OpAMD64VPCMPGTD128load, + ssa.OpAMD64VPCMPGTD256load, + ssa.OpAMD64VPCMPGTQ128load, + ssa.OpAMD64VPCMPGTQ256load, + ssa.OpAMD64VPUNPCKHWD128load, + ssa.OpAMD64VPUNPCKHDQ128load, + ssa.OpAMD64VPUNPCKHQDQ128load, + ssa.OpAMD64VPUNPCKHWD256load, + ssa.OpAMD64VPUNPCKHDQ256load, + ssa.OpAMD64VPUNPCKHDQ512load, + ssa.OpAMD64VPUNPCKHQDQ256load, + ssa.OpAMD64VPUNPCKHQDQ512load, + ssa.OpAMD64VPUNPCKLWD128load, + ssa.OpAMD64VPUNPCKLDQ128load, + ssa.OpAMD64VPUNPCKLQDQ128load, + ssa.OpAMD64VPUNPCKLWD256load, + ssa.OpAMD64VPUNPCKLDQ256load, + ssa.OpAMD64VPUNPCKLDQ512load, + ssa.OpAMD64VPUNPCKLQDQ256load, + ssa.OpAMD64VPUNPCKLQDQ512load, + ssa.OpAMD64VMAXPS128load, + ssa.OpAMD64VMAXPS256load, + ssa.OpAMD64VMAXPS512load, + ssa.OpAMD64VMAXPD128load, + ssa.OpAMD64VMAXPD256load, + ssa.OpAMD64VMAXPD512load, + ssa.OpAMD64VPMAXSB128load, + ssa.OpAMD64VPMAXSB256load, + ssa.OpAMD64VPMAXSW128load, + ssa.OpAMD64VPMAXSW256load, + ssa.OpAMD64VPMAXSD128load, + ssa.OpAMD64VPMAXSD256load, + ssa.OpAMD64VPMAXSD512load, + ssa.OpAMD64VPMAXSQ128load, + ssa.OpAMD64VPMAXSQ256load, + ssa.OpAMD64VPMAXSQ512load, + ssa.OpAMD64VPMAXUB128load, + ssa.OpAMD64VPMAXUB256load, + ssa.OpAMD64VPMAXUW128load, + ssa.OpAMD64VPMAXUW256load, + ssa.OpAMD64VPMAXUD128load, + ssa.OpAMD64VPMAXUD256load, + ssa.OpAMD64VPMAXUD512load, + ssa.OpAMD64VPMAXUQ128load, + ssa.OpAMD64VPMAXUQ256load, + ssa.OpAMD64VPMAXUQ512load, + ssa.OpAMD64VMINPS128load, + ssa.OpAMD64VMINPS256load, + ssa.OpAMD64VMINPS512load, + ssa.OpAMD64VMINPD128load, + ssa.OpAMD64VMINPD256load, + ssa.OpAMD64VMINPD512load, + ssa.OpAMD64VPMINSB128load, + ssa.OpAMD64VPMINSB256load, + ssa.OpAMD64VPMINSW128load, + ssa.OpAMD64VPMINSW256load, + ssa.OpAMD64VPMINSD128load, + ssa.OpAMD64VPMINSD256load, + ssa.OpAMD64VPMINSD512load, + ssa.OpAMD64VPMINSQ128load, + ssa.OpAMD64VPMINSQ256load, + ssa.OpAMD64VPMINSQ512load, + ssa.OpAMD64VPMINUB128load, + ssa.OpAMD64VPMINUB256load, + ssa.OpAMD64VPMINUW128load, + ssa.OpAMD64VPMINUW256load, + ssa.OpAMD64VPMINUD128load, + ssa.OpAMD64VPMINUD256load, + ssa.OpAMD64VPMINUD512load, + ssa.OpAMD64VPMINUQ128load, + ssa.OpAMD64VPMINUQ256load, + ssa.OpAMD64VPMINUQ512load, + ssa.OpAMD64VMULPS128load, + ssa.OpAMD64VMULPS256load, + ssa.OpAMD64VMULPS512load, + ssa.OpAMD64VMULPD128load, + ssa.OpAMD64VMULPD256load, + ssa.OpAMD64VMULPD512load, + ssa.OpAMD64VPMULLW128load, + ssa.OpAMD64VPMULLW256load, + ssa.OpAMD64VPMULLD128load, + ssa.OpAMD64VPMULLD256load, + ssa.OpAMD64VPMULLD512load, + ssa.OpAMD64VPMULLQ128load, + ssa.OpAMD64VPMULLQ256load, + ssa.OpAMD64VPMULLQ512load, + ssa.OpAMD64VPMULHW128load, + ssa.OpAMD64VPMULHW256load, + ssa.OpAMD64VPMULHUW128load, + ssa.OpAMD64VPMULHUW256load, + ssa.OpAMD64VPSIGNB128load, + ssa.OpAMD64VPSIGNB256load, + ssa.OpAMD64VPSIGNW128load, + ssa.OpAMD64VPSIGNW256load, + ssa.OpAMD64VPSIGND128load, + ssa.OpAMD64VPSIGND256load, + ssa.OpAMD64VPMULDQ128load, + ssa.OpAMD64VPMULDQ256load, + ssa.OpAMD64VPMULUDQ128load, + ssa.OpAMD64VPMULUDQ256load, + ssa.OpAMD64VPOR128load, + ssa.OpAMD64VPOR256load, + ssa.OpAMD64VPORD512load, + ssa.OpAMD64VPORQ512load, + ssa.OpAMD64VPERMB128load, + ssa.OpAMD64VPERMB256load, + ssa.OpAMD64VPERMW128load, + ssa.OpAMD64VPERMW256load, + ssa.OpAMD64VPERMPS256load, + ssa.OpAMD64VPERMD256load, + ssa.OpAMD64VPERMPS512load, + ssa.OpAMD64VPERMD512load, + ssa.OpAMD64VPERMPD256load, + ssa.OpAMD64VPERMQ256load, + ssa.OpAMD64VPERMPD512load, + ssa.OpAMD64VPERMQ512load, + ssa.OpAMD64VPSHUFB128load, + ssa.OpAMD64VPSHUFB256load, + ssa.OpAMD64VPROLVD128load, + ssa.OpAMD64VPROLVD256load, + ssa.OpAMD64VPROLVD512load, + ssa.OpAMD64VPROLVQ128load, + ssa.OpAMD64VPROLVQ256load, + ssa.OpAMD64VPROLVQ512load, + ssa.OpAMD64VPRORVD128load, + ssa.OpAMD64VPRORVD256load, + ssa.OpAMD64VPRORVD512load, + ssa.OpAMD64VPRORVQ128load, + ssa.OpAMD64VPRORVQ256load, + ssa.OpAMD64VPRORVQ512load, + ssa.OpAMD64VPACKSSDW128load, + ssa.OpAMD64VPACKSSDW256load, + ssa.OpAMD64VPACKSSDW512load, + ssa.OpAMD64VPACKUSDW128load, + ssa.OpAMD64VPACKUSDW256load, + ssa.OpAMD64VPACKUSDW512load, + ssa.OpAMD64VSCALEFPS128load, + ssa.OpAMD64VSCALEFPS256load, + ssa.OpAMD64VSCALEFPS512load, + ssa.OpAMD64VSCALEFPD128load, + ssa.OpAMD64VSCALEFPD256load, + ssa.OpAMD64VSCALEFPD512load, + ssa.OpAMD64VPSLLVW128load, + ssa.OpAMD64VPSLLVW256load, + ssa.OpAMD64VPSLLVD128load, + ssa.OpAMD64VPSLLVD256load, + ssa.OpAMD64VPSLLVD512load, + ssa.OpAMD64VPSLLVQ128load, + ssa.OpAMD64VPSLLVQ256load, + ssa.OpAMD64VPSLLVQ512load, + ssa.OpAMD64VPSRAVW128load, + ssa.OpAMD64VPSRAVW256load, + ssa.OpAMD64VPSRAVD128load, + ssa.OpAMD64VPSRAVD256load, + ssa.OpAMD64VPSRAVD512load, + ssa.OpAMD64VPSRAVQ128load, + ssa.OpAMD64VPSRAVQ256load, + ssa.OpAMD64VPSRAVQ512load, + ssa.OpAMD64VPSRLVW128load, + ssa.OpAMD64VPSRLVW256load, + ssa.OpAMD64VPSRLVD128load, + ssa.OpAMD64VPSRLVD256load, + ssa.OpAMD64VPSRLVD512load, + ssa.OpAMD64VPSRLVQ128load, + ssa.OpAMD64VPSRLVQ256load, + ssa.OpAMD64VPSRLVQ512load, + ssa.OpAMD64VSUBPS128load, + ssa.OpAMD64VSUBPS256load, + ssa.OpAMD64VSUBPS512load, + ssa.OpAMD64VSUBPD128load, + ssa.OpAMD64VSUBPD256load, + ssa.OpAMD64VSUBPD512load, + ssa.OpAMD64VPSUBB128load, + ssa.OpAMD64VPSUBB256load, + ssa.OpAMD64VPSUBW128load, + ssa.OpAMD64VPSUBW256load, + ssa.OpAMD64VPSUBD128load, + ssa.OpAMD64VPSUBD256load, + ssa.OpAMD64VPSUBD512load, + ssa.OpAMD64VPSUBQ128load, + ssa.OpAMD64VPSUBQ256load, + ssa.OpAMD64VPSUBQ512load, + ssa.OpAMD64VPSUBSB128load, + ssa.OpAMD64VPSUBSB256load, + ssa.OpAMD64VPSUBSW128load, + ssa.OpAMD64VPSUBSW256load, + ssa.OpAMD64VPSUBUSB128load, + ssa.OpAMD64VPSUBUSB256load, + ssa.OpAMD64VPSUBUSW128load, + ssa.OpAMD64VPSUBUSW256load, + ssa.OpAMD64VPSADBW128load, + ssa.OpAMD64VPSADBW256load, + ssa.OpAMD64VPXOR128load, + ssa.OpAMD64VPXOR256load, + ssa.OpAMD64VPXORD512load, + ssa.OpAMD64VPXORQ512load: + p = simdV21load(s, v) + + case ssa.OpAMD64VPDPWSSD128load, + ssa.OpAMD64VPDPWSSD256load, + ssa.OpAMD64VPDPWSSD512load, + ssa.OpAMD64VPERMI2B128load, + ssa.OpAMD64VPERMI2B256load, + ssa.OpAMD64VPERMI2W128load, + ssa.OpAMD64VPERMI2W256load, + ssa.OpAMD64VPERMI2PS128load, + ssa.OpAMD64VPERMI2D128load, + ssa.OpAMD64VPERMI2PS256load, + ssa.OpAMD64VPERMI2D256load, + ssa.OpAMD64VPERMI2PS512load, + ssa.OpAMD64VPERMI2D512load, + ssa.OpAMD64VPERMI2PD128load, + ssa.OpAMD64VPERMI2Q128load, + ssa.OpAMD64VPERMI2PD256load, + ssa.OpAMD64VPERMI2Q256load, + ssa.OpAMD64VPERMI2PD512load, + ssa.OpAMD64VPERMI2Q512load, + ssa.OpAMD64VFMADD213PS128load, + ssa.OpAMD64VFMADD213PS256load, + ssa.OpAMD64VFMADD213PS512load, + ssa.OpAMD64VFMADD213PD128load, + ssa.OpAMD64VFMADD213PD256load, + ssa.OpAMD64VFMADD213PD512load, + ssa.OpAMD64VFMADDSUB213PS128load, + ssa.OpAMD64VFMADDSUB213PS256load, + ssa.OpAMD64VFMADDSUB213PS512load, + ssa.OpAMD64VFMADDSUB213PD128load, + ssa.OpAMD64VFMADDSUB213PD256load, + ssa.OpAMD64VFMADDSUB213PD512load, + ssa.OpAMD64VFMSUBADD213PS128load, + ssa.OpAMD64VFMSUBADD213PS256load, + ssa.OpAMD64VFMSUBADD213PS512load, + ssa.OpAMD64VFMSUBADD213PD128load, + ssa.OpAMD64VFMSUBADD213PD256load, + ssa.OpAMD64VFMSUBADD213PD512load, + ssa.OpAMD64VPSHLDVW128load, + ssa.OpAMD64VPSHLDVW256load, + ssa.OpAMD64VPSHLDVD128load, + ssa.OpAMD64VPSHLDVD256load, + ssa.OpAMD64VPSHLDVD512load, + ssa.OpAMD64VPSHLDVQ128load, + ssa.OpAMD64VPSHLDVQ256load, + ssa.OpAMD64VPSHLDVQ512load, + ssa.OpAMD64VPSHRDVW128load, + ssa.OpAMD64VPSHRDVW256load, + ssa.OpAMD64VPSHRDVD128load, + ssa.OpAMD64VPSHRDVD256load, + ssa.OpAMD64VPSHRDVD512load, + ssa.OpAMD64VPSHRDVQ128load, + ssa.OpAMD64VPSHRDVQ256load, + ssa.OpAMD64VPSHRDVQ512load: + p = simdV31loadResultInArg0(s, v) + + case ssa.OpAMD64VPDPWSSDMasked128load, + ssa.OpAMD64VPDPWSSDMasked256load, + ssa.OpAMD64VPDPWSSDMasked512load, + ssa.OpAMD64VPERMI2BMasked128load, + ssa.OpAMD64VPERMI2BMasked256load, + ssa.OpAMD64VPERMI2WMasked128load, + ssa.OpAMD64VPERMI2WMasked256load, + ssa.OpAMD64VPERMI2PSMasked128load, + ssa.OpAMD64VPERMI2DMasked128load, + ssa.OpAMD64VPERMI2PSMasked256load, + ssa.OpAMD64VPERMI2DMasked256load, + ssa.OpAMD64VPERMI2PSMasked512load, + ssa.OpAMD64VPERMI2DMasked512load, + ssa.OpAMD64VPERMI2PDMasked128load, + ssa.OpAMD64VPERMI2QMasked128load, + ssa.OpAMD64VPERMI2PDMasked256load, + ssa.OpAMD64VPERMI2QMasked256load, + ssa.OpAMD64VPERMI2PDMasked512load, + ssa.OpAMD64VPERMI2QMasked512load, + ssa.OpAMD64VFMADDSUB213PSMasked128load, + ssa.OpAMD64VFMADDSUB213PSMasked256load, + ssa.OpAMD64VFMADDSUB213PSMasked512load, + ssa.OpAMD64VFMADDSUB213PDMasked128load, + ssa.OpAMD64VFMADDSUB213PDMasked256load, + ssa.OpAMD64VFMADDSUB213PDMasked512load, + ssa.OpAMD64VFMADD213PSMasked128load, + ssa.OpAMD64VFMADD213PSMasked256load, + ssa.OpAMD64VFMADD213PSMasked512load, + ssa.OpAMD64VFMADD213PDMasked128load, + ssa.OpAMD64VFMADD213PDMasked256load, + ssa.OpAMD64VFMADD213PDMasked512load, + ssa.OpAMD64VFMSUBADD213PSMasked128load, + ssa.OpAMD64VFMSUBADD213PSMasked256load, + ssa.OpAMD64VFMSUBADD213PSMasked512load, + ssa.OpAMD64VFMSUBADD213PDMasked128load, + ssa.OpAMD64VFMSUBADD213PDMasked256load, + ssa.OpAMD64VFMSUBADD213PDMasked512load, + ssa.OpAMD64VPSHLDVWMasked128load, + ssa.OpAMD64VPSHLDVWMasked256load, + ssa.OpAMD64VPSHLDVDMasked128load, + ssa.OpAMD64VPSHLDVDMasked256load, + ssa.OpAMD64VPSHLDVDMasked512load, + ssa.OpAMD64VPSHLDVQMasked128load, + ssa.OpAMD64VPSHLDVQMasked256load, + ssa.OpAMD64VPSHLDVQMasked512load, + ssa.OpAMD64VPSHRDVWMasked128load, + ssa.OpAMD64VPSHRDVWMasked256load, + ssa.OpAMD64VPSHRDVDMasked128load, + ssa.OpAMD64VPSHRDVDMasked256load, + ssa.OpAMD64VPSHRDVDMasked512load, + ssa.OpAMD64VPSHRDVQMasked128load, + ssa.OpAMD64VPSHRDVQMasked256load, + ssa.OpAMD64VPSHRDVQMasked512load: + p = simdV3kvloadResultInArg0(s, v) + + case ssa.OpAMD64VADDPSMasked128load, + ssa.OpAMD64VADDPSMasked256load, + ssa.OpAMD64VADDPSMasked512load, + ssa.OpAMD64VADDPDMasked128load, + ssa.OpAMD64VADDPDMasked256load, + ssa.OpAMD64VADDPDMasked512load, + ssa.OpAMD64VPADDBMasked128load, + ssa.OpAMD64VPADDBMasked256load, + ssa.OpAMD64VPADDWMasked128load, + ssa.OpAMD64VPADDWMasked256load, + ssa.OpAMD64VPADDDMasked128load, + ssa.OpAMD64VPADDDMasked256load, + ssa.OpAMD64VPADDDMasked512load, + ssa.OpAMD64VPADDQMasked128load, + ssa.OpAMD64VPADDQMasked256load, + ssa.OpAMD64VPADDQMasked512load, + ssa.OpAMD64VPADDSBMasked128load, + ssa.OpAMD64VPADDSBMasked256load, + ssa.OpAMD64VPADDSWMasked128load, + ssa.OpAMD64VPADDSWMasked256load, + ssa.OpAMD64VPADDUSBMasked128load, + ssa.OpAMD64VPADDUSBMasked256load, + ssa.OpAMD64VPADDUSWMasked128load, + ssa.OpAMD64VPADDUSWMasked256load, + ssa.OpAMD64VPANDDMasked128load, + ssa.OpAMD64VPANDDMasked256load, + ssa.OpAMD64VPANDDMasked512load, + ssa.OpAMD64VPANDQMasked128load, + ssa.OpAMD64VPANDQMasked256load, + ssa.OpAMD64VPANDQMasked512load, + ssa.OpAMD64VPANDNDMasked128load, + ssa.OpAMD64VPANDNDMasked256load, + ssa.OpAMD64VPANDNDMasked512load, + ssa.OpAMD64VPANDNQMasked128load, + ssa.OpAMD64VPANDNQMasked256load, + ssa.OpAMD64VPANDNQMasked512load, + ssa.OpAMD64VPAVGBMasked128load, + ssa.OpAMD64VPAVGBMasked256load, + ssa.OpAMD64VPAVGWMasked128load, + ssa.OpAMD64VPAVGWMasked256load, + ssa.OpAMD64VDIVPSMasked128load, + ssa.OpAMD64VDIVPSMasked256load, + ssa.OpAMD64VDIVPSMasked512load, + ssa.OpAMD64VDIVPDMasked128load, + ssa.OpAMD64VDIVPDMasked256load, + ssa.OpAMD64VDIVPDMasked512load, + ssa.OpAMD64VPMADDWDMasked128load, + ssa.OpAMD64VPMADDWDMasked256load, + ssa.OpAMD64VPMADDUBSWMasked128load, + ssa.OpAMD64VPMADDUBSWMasked256load, + ssa.OpAMD64VGF2P8MULBMasked128load, + ssa.OpAMD64VGF2P8MULBMasked256load, + ssa.OpAMD64VMAXPSMasked128load, + ssa.OpAMD64VMAXPSMasked256load, + ssa.OpAMD64VMAXPSMasked512load, + ssa.OpAMD64VMAXPDMasked128load, + ssa.OpAMD64VMAXPDMasked256load, + ssa.OpAMD64VMAXPDMasked512load, + ssa.OpAMD64VPMAXSBMasked128load, + ssa.OpAMD64VPMAXSBMasked256load, + ssa.OpAMD64VPMAXSWMasked128load, + ssa.OpAMD64VPMAXSWMasked256load, + ssa.OpAMD64VPMAXSDMasked128load, + ssa.OpAMD64VPMAXSDMasked256load, + ssa.OpAMD64VPMAXSDMasked512load, + ssa.OpAMD64VPMAXSQMasked128load, + ssa.OpAMD64VPMAXSQMasked256load, + ssa.OpAMD64VPMAXSQMasked512load, + ssa.OpAMD64VPMAXUBMasked128load, + ssa.OpAMD64VPMAXUBMasked256load, + ssa.OpAMD64VPMAXUWMasked128load, + ssa.OpAMD64VPMAXUWMasked256load, + ssa.OpAMD64VPMAXUDMasked128load, + ssa.OpAMD64VPMAXUDMasked256load, + ssa.OpAMD64VPMAXUDMasked512load, + ssa.OpAMD64VPMAXUQMasked128load, + ssa.OpAMD64VPMAXUQMasked256load, + ssa.OpAMD64VPMAXUQMasked512load, + ssa.OpAMD64VMINPSMasked128load, + ssa.OpAMD64VMINPSMasked256load, + ssa.OpAMD64VMINPSMasked512load, + ssa.OpAMD64VMINPDMasked128load, + ssa.OpAMD64VMINPDMasked256load, + ssa.OpAMD64VMINPDMasked512load, + ssa.OpAMD64VPMINSBMasked128load, + ssa.OpAMD64VPMINSBMasked256load, + ssa.OpAMD64VPMINSWMasked128load, + ssa.OpAMD64VPMINSWMasked256load, + ssa.OpAMD64VPMINSDMasked128load, + ssa.OpAMD64VPMINSDMasked256load, + ssa.OpAMD64VPMINSDMasked512load, + ssa.OpAMD64VPMINSQMasked128load, + ssa.OpAMD64VPMINSQMasked256load, + ssa.OpAMD64VPMINSQMasked512load, + ssa.OpAMD64VPMINUBMasked128load, + ssa.OpAMD64VPMINUBMasked256load, + ssa.OpAMD64VPMINUWMasked128load, + ssa.OpAMD64VPMINUWMasked256load, + ssa.OpAMD64VPMINUDMasked128load, + ssa.OpAMD64VPMINUDMasked256load, + ssa.OpAMD64VPMINUDMasked512load, + ssa.OpAMD64VPMINUQMasked128load, + ssa.OpAMD64VPMINUQMasked256load, + ssa.OpAMD64VPMINUQMasked512load, + ssa.OpAMD64VPMULHWMasked128load, + ssa.OpAMD64VPMULHWMasked256load, + ssa.OpAMD64VPMULHUWMasked128load, + ssa.OpAMD64VPMULHUWMasked256load, + ssa.OpAMD64VMULPSMasked128load, + ssa.OpAMD64VMULPSMasked256load, + ssa.OpAMD64VMULPSMasked512load, + ssa.OpAMD64VMULPDMasked128load, + ssa.OpAMD64VMULPDMasked256load, + ssa.OpAMD64VMULPDMasked512load, + ssa.OpAMD64VPMULLWMasked128load, + ssa.OpAMD64VPMULLWMasked256load, + ssa.OpAMD64VPMULLDMasked128load, + ssa.OpAMD64VPMULLDMasked256load, + ssa.OpAMD64VPMULLDMasked512load, + ssa.OpAMD64VPMULLQMasked128load, + ssa.OpAMD64VPMULLQMasked256load, + ssa.OpAMD64VPMULLQMasked512load, + ssa.OpAMD64VPORDMasked128load, + ssa.OpAMD64VPORDMasked256load, + ssa.OpAMD64VPORDMasked512load, + ssa.OpAMD64VPORQMasked128load, + ssa.OpAMD64VPORQMasked256load, + ssa.OpAMD64VPORQMasked512load, + ssa.OpAMD64VPERMBMasked128load, + ssa.OpAMD64VPERMBMasked256load, + ssa.OpAMD64VPERMWMasked128load, + ssa.OpAMD64VPERMWMasked256load, + ssa.OpAMD64VPERMPSMasked256load, + ssa.OpAMD64VPERMDMasked256load, + ssa.OpAMD64VPERMPSMasked512load, + ssa.OpAMD64VPERMDMasked512load, + ssa.OpAMD64VPERMPDMasked256load, + ssa.OpAMD64VPERMQMasked256load, + ssa.OpAMD64VPERMPDMasked512load, + ssa.OpAMD64VPERMQMasked512load, + ssa.OpAMD64VPSHUFBMasked256load, + ssa.OpAMD64VPSHUFBMasked128load, + ssa.OpAMD64VPROLVDMasked128load, + ssa.OpAMD64VPROLVDMasked256load, + ssa.OpAMD64VPROLVDMasked512load, + ssa.OpAMD64VPROLVQMasked128load, + ssa.OpAMD64VPROLVQMasked256load, + ssa.OpAMD64VPROLVQMasked512load, + ssa.OpAMD64VPRORVDMasked128load, + ssa.OpAMD64VPRORVDMasked256load, + ssa.OpAMD64VPRORVDMasked512load, + ssa.OpAMD64VPRORVQMasked128load, + ssa.OpAMD64VPRORVQMasked256load, + ssa.OpAMD64VPRORVQMasked512load, + ssa.OpAMD64VPACKSSDWMasked256load, + ssa.OpAMD64VPACKSSDWMasked512load, + ssa.OpAMD64VPACKSSDWMasked128load, + ssa.OpAMD64VPACKUSDWMasked256load, + ssa.OpAMD64VPACKUSDWMasked512load, + ssa.OpAMD64VPACKUSDWMasked128load, + ssa.OpAMD64VSCALEFPSMasked128load, + ssa.OpAMD64VSCALEFPSMasked256load, + ssa.OpAMD64VSCALEFPSMasked512load, + ssa.OpAMD64VSCALEFPDMasked128load, + ssa.OpAMD64VSCALEFPDMasked256load, + ssa.OpAMD64VSCALEFPDMasked512load, + ssa.OpAMD64VPSLLVWMasked128load, + ssa.OpAMD64VPSLLVWMasked256load, + ssa.OpAMD64VPSLLVDMasked128load, + ssa.OpAMD64VPSLLVDMasked256load, + ssa.OpAMD64VPSLLVDMasked512load, + ssa.OpAMD64VPSLLVQMasked128load, + ssa.OpAMD64VPSLLVQMasked256load, + ssa.OpAMD64VPSLLVQMasked512load, + ssa.OpAMD64VPSRAVWMasked128load, + ssa.OpAMD64VPSRAVWMasked256load, + ssa.OpAMD64VPSRAVDMasked128load, + ssa.OpAMD64VPSRAVDMasked256load, + ssa.OpAMD64VPSRAVDMasked512load, + ssa.OpAMD64VPSRAVQMasked128load, + ssa.OpAMD64VPSRAVQMasked256load, + ssa.OpAMD64VPSRAVQMasked512load, + ssa.OpAMD64VPSRLVWMasked128load, + ssa.OpAMD64VPSRLVWMasked256load, + ssa.OpAMD64VPSRLVDMasked128load, + ssa.OpAMD64VPSRLVDMasked256load, + ssa.OpAMD64VPSRLVDMasked512load, + ssa.OpAMD64VPSRLVQMasked128load, + ssa.OpAMD64VPSRLVQMasked256load, + ssa.OpAMD64VPSRLVQMasked512load, + ssa.OpAMD64VSUBPSMasked128load, + ssa.OpAMD64VSUBPSMasked256load, + ssa.OpAMD64VSUBPSMasked512load, + ssa.OpAMD64VSUBPDMasked128load, + ssa.OpAMD64VSUBPDMasked256load, + ssa.OpAMD64VSUBPDMasked512load, + ssa.OpAMD64VPSUBBMasked128load, + ssa.OpAMD64VPSUBBMasked256load, + ssa.OpAMD64VPSUBWMasked128load, + ssa.OpAMD64VPSUBWMasked256load, + ssa.OpAMD64VPSUBDMasked128load, + ssa.OpAMD64VPSUBDMasked256load, + ssa.OpAMD64VPSUBDMasked512load, + ssa.OpAMD64VPSUBQMasked128load, + ssa.OpAMD64VPSUBQMasked256load, + ssa.OpAMD64VPSUBQMasked512load, + ssa.OpAMD64VPSUBSBMasked128load, + ssa.OpAMD64VPSUBSBMasked256load, + ssa.OpAMD64VPSUBSWMasked128load, + ssa.OpAMD64VPSUBSWMasked256load, + ssa.OpAMD64VPSUBUSBMasked128load, + ssa.OpAMD64VPSUBUSBMasked256load, + ssa.OpAMD64VPSUBUSWMasked128load, + ssa.OpAMD64VPSUBUSWMasked256load, + ssa.OpAMD64VPXORDMasked128load, + ssa.OpAMD64VPXORDMasked256load, + ssa.OpAMD64VPXORDMasked512load, + ssa.OpAMD64VPXORQMasked128load, + ssa.OpAMD64VPXORQMasked256load, + ssa.OpAMD64VPXORQMasked512load, + ssa.OpAMD64VPBLENDMDMasked512load, + ssa.OpAMD64VPBLENDMQMasked512load: + p = simdV2kvload(s, v) + + case ssa.OpAMD64VPCMPEQD512load, + ssa.OpAMD64VPCMPEQQ512load, + ssa.OpAMD64VPCMPGTD512load, + ssa.OpAMD64VPCMPGTQ512load: + p = simdV2kload(s, v) + + case ssa.OpAMD64VAESIMC128load, + ssa.OpAMD64VPABSB128load, + ssa.OpAMD64VPABSB256load, + ssa.OpAMD64VPABSW128load, + ssa.OpAMD64VPABSW256load, + ssa.OpAMD64VPABSD128load, + ssa.OpAMD64VPABSD256load, + ssa.OpAMD64VPABSD512load, + ssa.OpAMD64VPABSQ128load, + ssa.OpAMD64VPABSQ256load, + ssa.OpAMD64VPABSQ512load, + ssa.OpAMD64VCVTPD2PSX128load, + ssa.OpAMD64VCVTPD2PSY128load, + ssa.OpAMD64VCVTPD2PS256load, + ssa.OpAMD64VCVTDQ2PS128load, + ssa.OpAMD64VCVTDQ2PS256load, + ssa.OpAMD64VCVTDQ2PS512load, + ssa.OpAMD64VCVTQQ2PSX128load, + ssa.OpAMD64VCVTQQ2PSY128load, + ssa.OpAMD64VCVTQQ2PS256load, + ssa.OpAMD64VCVTUDQ2PS128load, + ssa.OpAMD64VCVTUDQ2PS256load, + ssa.OpAMD64VCVTUDQ2PS512load, + ssa.OpAMD64VCVTUQQ2PSX128load, + ssa.OpAMD64VCVTUQQ2PSY128load, + ssa.OpAMD64VCVTUQQ2PS256load, + ssa.OpAMD64VCVTPS2PD256load, + ssa.OpAMD64VCVTPS2PD512load, + ssa.OpAMD64VCVTDQ2PD256load, + ssa.OpAMD64VCVTDQ2PD512load, + ssa.OpAMD64VCVTQQ2PD128load, + ssa.OpAMD64VCVTQQ2PD256load, + ssa.OpAMD64VCVTQQ2PD512load, + ssa.OpAMD64VCVTUDQ2PD256load, + ssa.OpAMD64VCVTUDQ2PD512load, + ssa.OpAMD64VCVTUQQ2PD128load, + ssa.OpAMD64VCVTUQQ2PD256load, + ssa.OpAMD64VCVTUQQ2PD512load, + ssa.OpAMD64VCVTTPS2DQ128load, + ssa.OpAMD64VCVTTPS2DQ256load, + ssa.OpAMD64VCVTTPS2DQ512load, + ssa.OpAMD64VCVTTPD2DQX128load, + ssa.OpAMD64VCVTTPD2DQY128load, + ssa.OpAMD64VCVTTPD2DQ256load, + ssa.OpAMD64VCVTTPS2QQ256load, + ssa.OpAMD64VCVTTPS2QQ512load, + ssa.OpAMD64VCVTTPD2QQ128load, + ssa.OpAMD64VCVTTPD2QQ256load, + ssa.OpAMD64VCVTTPD2QQ512load, + ssa.OpAMD64VCVTTPS2UDQ128load, + ssa.OpAMD64VCVTTPS2UDQ256load, + ssa.OpAMD64VCVTTPS2UDQ512load, + ssa.OpAMD64VCVTTPD2UDQX128load, + ssa.OpAMD64VCVTTPD2UDQY128load, + ssa.OpAMD64VCVTTPD2UDQ256load, + ssa.OpAMD64VCVTTPS2UQQ256load, + ssa.OpAMD64VCVTTPS2UQQ512load, + ssa.OpAMD64VCVTTPD2UQQ128load, + ssa.OpAMD64VCVTTPD2UQQ256load, + ssa.OpAMD64VCVTTPD2UQQ512load, + ssa.OpAMD64VPMOVSXBQ128load, + ssa.OpAMD64VPMOVSXWQ128load, + ssa.OpAMD64VPMOVSXDQ128load, + ssa.OpAMD64VPMOVZXBQ128load, + ssa.OpAMD64VPMOVZXWQ128load, + ssa.OpAMD64VPMOVZXDQ128load, + ssa.OpAMD64VPMOVSXBD128load, + ssa.OpAMD64VPMOVSXWD128load, + ssa.OpAMD64VPMOVSXBQ256load, + ssa.OpAMD64VPMOVSXWQ256load, + ssa.OpAMD64VPMOVZXBD128load, + ssa.OpAMD64VPMOVZXWD128load, + ssa.OpAMD64VPMOVZXBQ256load, + ssa.OpAMD64VPMOVZXWQ256load, + ssa.OpAMD64VPMOVSXBW128load, + ssa.OpAMD64VPMOVSXBD256load, + ssa.OpAMD64VPMOVSXBQ512load, + ssa.OpAMD64VPMOVZXBW128load, + ssa.OpAMD64VPMOVZXBD256load, + ssa.OpAMD64VPMOVZXBQ512load, + ssa.OpAMD64VPMOVSXBW256load, + ssa.OpAMD64VPMOVSXBW512load, + ssa.OpAMD64VPMOVSXBD512load, + ssa.OpAMD64VPMOVSXWD256load, + ssa.OpAMD64VPMOVSXWD512load, + ssa.OpAMD64VPMOVSXWQ512load, + ssa.OpAMD64VPMOVSXDQ256load, + ssa.OpAMD64VPMOVSXDQ512load, + ssa.OpAMD64VPMOVZXBW256load, + ssa.OpAMD64VPMOVZXBW512load, + ssa.OpAMD64VPMOVZXBD512load, + ssa.OpAMD64VPMOVZXWD256load, + ssa.OpAMD64VPMOVZXWD512load, + ssa.OpAMD64VPMOVZXWQ512load, + ssa.OpAMD64VPMOVZXDQ256load, + ssa.OpAMD64VPMOVZXDQ512load, + ssa.OpAMD64VPLZCNTD128load, + ssa.OpAMD64VPLZCNTD256load, + ssa.OpAMD64VPLZCNTD512load, + ssa.OpAMD64VPLZCNTQ128load, + ssa.OpAMD64VPLZCNTQ256load, + ssa.OpAMD64VPLZCNTQ512load, + ssa.OpAMD64VPOPCNTB128load, + ssa.OpAMD64VPOPCNTB256load, + ssa.OpAMD64VPOPCNTW128load, + ssa.OpAMD64VPOPCNTW256load, + ssa.OpAMD64VPOPCNTD128load, + ssa.OpAMD64VPOPCNTD256load, + ssa.OpAMD64VPOPCNTD512load, + ssa.OpAMD64VPOPCNTQ128load, + ssa.OpAMD64VPOPCNTQ256load, + ssa.OpAMD64VPOPCNTQ512load, + ssa.OpAMD64VRCPPS128load, + ssa.OpAMD64VRCPPS256load, + ssa.OpAMD64VRCP14PS512load, + ssa.OpAMD64VRCP14PD128load, + ssa.OpAMD64VRCP14PD256load, + ssa.OpAMD64VRCP14PD512load, + ssa.OpAMD64VRSQRTPS128load, + ssa.OpAMD64VRSQRTPS256load, + ssa.OpAMD64VRSQRT14PS512load, + ssa.OpAMD64VRSQRT14PD128load, + ssa.OpAMD64VRSQRT14PD256load, + ssa.OpAMD64VRSQRT14PD512load, + ssa.OpAMD64VSQRTPS128load, + ssa.OpAMD64VSQRTPS256load, + ssa.OpAMD64VSQRTPS512load, + ssa.OpAMD64VSQRTPD128load, + ssa.OpAMD64VSQRTPD256load, + ssa.OpAMD64VSQRTPD512load, + ssa.OpAMD64VPBROADCASTQ128load, + ssa.OpAMD64VBROADCASTSS128load, + ssa.OpAMD64VBROADCASTSD256load, + ssa.OpAMD64VPBROADCASTD128load, + ssa.OpAMD64VPBROADCASTQ256load, + ssa.OpAMD64VBROADCASTSS256load, + ssa.OpAMD64VBROADCASTSD512load, + ssa.OpAMD64VPBROADCASTW128load, + ssa.OpAMD64VPBROADCASTD256load, + ssa.OpAMD64VPBROADCASTQ512load, + ssa.OpAMD64VBROADCASTSS512load, + ssa.OpAMD64VPBROADCASTB128load, + ssa.OpAMD64VPBROADCASTW256load, + ssa.OpAMD64VPBROADCASTD512load, + ssa.OpAMD64VPBROADCASTB256load, + ssa.OpAMD64VPBROADCASTB512load: + p = simdV11load(s, v) + + case ssa.OpAMD64VAESKEYGENASSIST128load, + ssa.OpAMD64VROUNDPS128load, + ssa.OpAMD64VROUNDPS256load, + ssa.OpAMD64VROUNDPD128load, + ssa.OpAMD64VROUNDPD256load, + ssa.OpAMD64VRNDSCALEPS128load, + ssa.OpAMD64VRNDSCALEPS256load, + ssa.OpAMD64VRNDSCALEPS512load, + ssa.OpAMD64VRNDSCALEPD128load, + ssa.OpAMD64VRNDSCALEPD256load, + ssa.OpAMD64VRNDSCALEPD512load, + ssa.OpAMD64VREDUCEPS128load, + ssa.OpAMD64VREDUCEPS256load, + ssa.OpAMD64VREDUCEPS512load, + ssa.OpAMD64VREDUCEPD128load, + ssa.OpAMD64VREDUCEPD256load, + ssa.OpAMD64VREDUCEPD512load, + ssa.OpAMD64VPSHUFD128load, + ssa.OpAMD64VPSHUFD256load, + ssa.OpAMD64VPSHUFD512load, + ssa.OpAMD64VPSHUFHW128load, + ssa.OpAMD64VPSHUFHW256load, + ssa.OpAMD64VPSHUFLW128load, + ssa.OpAMD64VPSHUFLW256load, + ssa.OpAMD64VPROLD128load, + ssa.OpAMD64VPROLD256load, + ssa.OpAMD64VPROLD512load, + ssa.OpAMD64VPROLQ128load, + ssa.OpAMD64VPROLQ256load, + ssa.OpAMD64VPROLQ512load, + ssa.OpAMD64VPRORD128load, + ssa.OpAMD64VPRORD256load, + ssa.OpAMD64VPRORD512load, + ssa.OpAMD64VPRORQ128load, + ssa.OpAMD64VPRORQ256load, + ssa.OpAMD64VPRORQ512load, + ssa.OpAMD64VPSLLD512constload, + ssa.OpAMD64VPSLLQ512constload, + ssa.OpAMD64VPSRAD512constload, + ssa.OpAMD64VPSRAQ128constload, + ssa.OpAMD64VPSRAQ256constload, + ssa.OpAMD64VPSRAQ512constload, + ssa.OpAMD64VPSRLD512constload, + ssa.OpAMD64VPSRLQ512constload: + p = simdV11loadImm8(s, v) + + case ssa.OpAMD64VRNDSCALEPSMasked128load, + ssa.OpAMD64VRNDSCALEPSMasked256load, + ssa.OpAMD64VRNDSCALEPSMasked512load, + ssa.OpAMD64VRNDSCALEPDMasked128load, + ssa.OpAMD64VRNDSCALEPDMasked256load, + ssa.OpAMD64VRNDSCALEPDMasked512load, + ssa.OpAMD64VREDUCEPSMasked128load, + ssa.OpAMD64VREDUCEPSMasked256load, + ssa.OpAMD64VREDUCEPSMasked512load, + ssa.OpAMD64VREDUCEPDMasked128load, + ssa.OpAMD64VREDUCEPDMasked256load, + ssa.OpAMD64VREDUCEPDMasked512load, + ssa.OpAMD64VPSHUFDMasked256load, + ssa.OpAMD64VPSHUFDMasked512load, + ssa.OpAMD64VPSHUFHWMasked256load, + ssa.OpAMD64VPSHUFHWMasked128load, + ssa.OpAMD64VPSHUFLWMasked256load, + ssa.OpAMD64VPSHUFLWMasked128load, + ssa.OpAMD64VPSHUFDMasked128load, + ssa.OpAMD64VPROLDMasked128load, + ssa.OpAMD64VPROLDMasked256load, + ssa.OpAMD64VPROLDMasked512load, + ssa.OpAMD64VPROLQMasked128load, + ssa.OpAMD64VPROLQMasked256load, + ssa.OpAMD64VPROLQMasked512load, + ssa.OpAMD64VPRORDMasked128load, + ssa.OpAMD64VPRORDMasked256load, + ssa.OpAMD64VPRORDMasked512load, + ssa.OpAMD64VPRORQMasked128load, + ssa.OpAMD64VPRORQMasked256load, + ssa.OpAMD64VPRORQMasked512load, + ssa.OpAMD64VPSLLWMasked128constload, + ssa.OpAMD64VPSLLWMasked256constload, + ssa.OpAMD64VPSLLDMasked128constload, + ssa.OpAMD64VPSLLDMasked256constload, + ssa.OpAMD64VPSLLDMasked512constload, + ssa.OpAMD64VPSLLQMasked128constload, + ssa.OpAMD64VPSLLQMasked256constload, + ssa.OpAMD64VPSLLQMasked512constload, + ssa.OpAMD64VPSRAWMasked128constload, + ssa.OpAMD64VPSRAWMasked256constload, + ssa.OpAMD64VPSRADMasked128constload, + ssa.OpAMD64VPSRADMasked256constload, + ssa.OpAMD64VPSRADMasked512constload, + ssa.OpAMD64VPSRAQMasked128constload, + ssa.OpAMD64VPSRAQMasked256constload, + ssa.OpAMD64VPSRAQMasked512constload, + ssa.OpAMD64VPSRLWMasked128constload, + ssa.OpAMD64VPSRLWMasked256constload, + ssa.OpAMD64VPSRLDMasked128constload, + ssa.OpAMD64VPSRLDMasked256constload, + ssa.OpAMD64VPSRLDMasked512constload, + ssa.OpAMD64VPSRLQMasked128constload, + ssa.OpAMD64VPSRLQMasked256constload, + ssa.OpAMD64VPSRLQMasked512constload: + p = simdVkvloadImm8(s, v) + + case ssa.OpAMD64VPERM2F128256load, + ssa.OpAMD64VPERM2I128256load, + ssa.OpAMD64VPALIGNR128load, + ssa.OpAMD64VPALIGNR256load, + ssa.OpAMD64VCMPPS128load, + ssa.OpAMD64VCMPPS256load, + ssa.OpAMD64VCMPPD128load, + ssa.OpAMD64VCMPPD256load, + ssa.OpAMD64VGF2P8AFFINEQB128load, + ssa.OpAMD64VGF2P8AFFINEQB256load, + ssa.OpAMD64VGF2P8AFFINEQB512load, + ssa.OpAMD64VGF2P8AFFINEINVQB128load, + ssa.OpAMD64VGF2P8AFFINEINVQB256load, + ssa.OpAMD64VGF2P8AFFINEINVQB512load, + ssa.OpAMD64VINSERTF128256load, + ssa.OpAMD64VINSERTF64X4512load, + ssa.OpAMD64VINSERTI128256load, + ssa.OpAMD64VINSERTI64X4512load, + ssa.OpAMD64VPSHLDW128load, + ssa.OpAMD64VPSHLDW256load, + ssa.OpAMD64VPSHLDD128load, + ssa.OpAMD64VPSHLDD256load, + ssa.OpAMD64VPSHLDD512load, + ssa.OpAMD64VPSHLDQ128load, + ssa.OpAMD64VPSHLDQ256load, + ssa.OpAMD64VPSHLDQ512load, + ssa.OpAMD64VPSHRDW128load, + ssa.OpAMD64VPSHRDW256load, + ssa.OpAMD64VPSHRDD128load, + ssa.OpAMD64VPSHRDD256load, + ssa.OpAMD64VPSHRDD512load, + ssa.OpAMD64VPSHRDQ128load, + ssa.OpAMD64VPSHRDQ256load, + ssa.OpAMD64VPSHRDQ512load, + ssa.OpAMD64VPCLMULQDQ128load, + ssa.OpAMD64VPCLMULQDQ256load, + ssa.OpAMD64VSHUFPS128load, + ssa.OpAMD64VSHUFPD128load, + ssa.OpAMD64VSHUFPS256load, + ssa.OpAMD64VSHUFPS512load, + ssa.OpAMD64VSHUFPD256load, + ssa.OpAMD64VSHUFPD512load: + p = simdV21loadImm8(s, v) + + case ssa.OpAMD64VCMPPS512load, + ssa.OpAMD64VCMPPD512load, + ssa.OpAMD64VPCMPUD512load, + ssa.OpAMD64VPCMPUQ512load, + ssa.OpAMD64VPCMPD512load, + ssa.OpAMD64VPCMPQ512load: + p = simdV2kloadImm8(s, v) + + case ssa.OpAMD64VCMPPSMasked128load, + ssa.OpAMD64VCMPPSMasked256load, + ssa.OpAMD64VCMPPSMasked512load, + ssa.OpAMD64VCMPPDMasked128load, + ssa.OpAMD64VCMPPDMasked256load, + ssa.OpAMD64VCMPPDMasked512load, + ssa.OpAMD64VPCMPBMasked128load, + ssa.OpAMD64VPCMPBMasked256load, + ssa.OpAMD64VPCMPWMasked128load, + ssa.OpAMD64VPCMPWMasked256load, + ssa.OpAMD64VPCMPDMasked128load, + ssa.OpAMD64VPCMPDMasked256load, + ssa.OpAMD64VPCMPDMasked512load, + ssa.OpAMD64VPCMPQMasked128load, + ssa.OpAMD64VPCMPQMasked256load, + ssa.OpAMD64VPCMPQMasked512load, + ssa.OpAMD64VPCMPUBMasked128load, + ssa.OpAMD64VPCMPUBMasked256load, + ssa.OpAMD64VPCMPUWMasked128load, + ssa.OpAMD64VPCMPUWMasked256load, + ssa.OpAMD64VPCMPUDMasked128load, + ssa.OpAMD64VPCMPUDMasked256load, + ssa.OpAMD64VPCMPUDMasked512load, + ssa.OpAMD64VPCMPUQMasked128load, + ssa.OpAMD64VPCMPUQMasked256load, + ssa.OpAMD64VPCMPUQMasked512load: + p = simdV2kkloadImm8(s, v) + + case ssa.OpAMD64VPALIGNRMasked256load, + ssa.OpAMD64VPALIGNRMasked128load, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked128load, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked256load, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked512load, + ssa.OpAMD64VGF2P8AFFINEQBMasked128load, + ssa.OpAMD64VGF2P8AFFINEQBMasked256load, + ssa.OpAMD64VGF2P8AFFINEQBMasked512load, + ssa.OpAMD64VPSHLDWMasked128load, + ssa.OpAMD64VPSHLDWMasked256load, + ssa.OpAMD64VPSHLDDMasked128load, + ssa.OpAMD64VPSHLDDMasked256load, + ssa.OpAMD64VPSHLDDMasked512load, + ssa.OpAMD64VPSHLDQMasked128load, + ssa.OpAMD64VPSHLDQMasked256load, + ssa.OpAMD64VPSHLDQMasked512load, + ssa.OpAMD64VPSHRDWMasked128load, + ssa.OpAMD64VPSHRDWMasked256load, + ssa.OpAMD64VPSHRDDMasked128load, + ssa.OpAMD64VPSHRDDMasked256load, + ssa.OpAMD64VPSHRDDMasked512load, + ssa.OpAMD64VPSHRDQMasked128load, + ssa.OpAMD64VPSHRDQMasked256load, + ssa.OpAMD64VPSHRDQMasked512load: + p = simdV2kvloadImm8(s, v) + + case ssa.OpAMD64VPTERNLOGD128, + ssa.OpAMD64VPTERNLOGD256, + ssa.OpAMD64VPTERNLOGD512, + ssa.OpAMD64VPTERNLOGQ128, + ssa.OpAMD64VPTERNLOGQ256, + ssa.OpAMD64VPTERNLOGQ512: + p = simdV31ResultInArg0Imm8(s, v) + + case ssa.OpAMD64VPTERNLOGD128load, + ssa.OpAMD64VPTERNLOGD256load, + ssa.OpAMD64VPTERNLOGD512load, + ssa.OpAMD64VPTERNLOGQ128load, + ssa.OpAMD64VPTERNLOGQ256load, + ssa.OpAMD64VPTERNLOGQ512load: + p = simdV31loadResultInArg0Imm8(s, v) + + case ssa.OpAMD64SHA1MSG1128, + ssa.OpAMD64SHA1MSG2128, + ssa.OpAMD64SHA1NEXTE128, + ssa.OpAMD64SHA256MSG1128, + ssa.OpAMD64SHA256MSG2128: + p = simdV21ResultInArg0(s, v) + + case ssa.OpAMD64SHA1RNDS4128: + p = simdV21ResultInArg0Imm8(s, v) + + case ssa.OpAMD64SHA256RNDS2128: + p = simdV31x0AtIn2ResultInArg0(s, v) + + case ssa.OpAMD64VPABSBMasked128Merging, + ssa.OpAMD64VPABSBMasked256Merging, + ssa.OpAMD64VPABSBMasked512Merging, + ssa.OpAMD64VPABSWMasked128Merging, + ssa.OpAMD64VPABSWMasked256Merging, + ssa.OpAMD64VPABSWMasked512Merging, + ssa.OpAMD64VPABSDMasked128Merging, + ssa.OpAMD64VPABSDMasked256Merging, + ssa.OpAMD64VPABSDMasked512Merging, + ssa.OpAMD64VPABSQMasked128Merging, + ssa.OpAMD64VPABSQMasked256Merging, + ssa.OpAMD64VPABSQMasked512Merging, + ssa.OpAMD64VRNDSCALEPSMasked128Merging, + ssa.OpAMD64VRNDSCALEPSMasked256Merging, + ssa.OpAMD64VRNDSCALEPSMasked512Merging, + ssa.OpAMD64VRNDSCALEPDMasked128Merging, + ssa.OpAMD64VRNDSCALEPDMasked256Merging, + ssa.OpAMD64VRNDSCALEPDMasked512Merging, + ssa.OpAMD64VREDUCEPSMasked128Merging, + ssa.OpAMD64VREDUCEPSMasked256Merging, + ssa.OpAMD64VREDUCEPSMasked512Merging, + ssa.OpAMD64VREDUCEPDMasked128Merging, + ssa.OpAMD64VREDUCEPDMasked256Merging, + ssa.OpAMD64VREDUCEPDMasked512Merging, + ssa.OpAMD64VCVTPD2PSXMasked128Merging, + ssa.OpAMD64VCVTPD2PSYMasked128Merging, + ssa.OpAMD64VCVTPD2PSMasked256Merging, + ssa.OpAMD64VCVTDQ2PSMasked128Merging, + ssa.OpAMD64VCVTDQ2PSMasked256Merging, + ssa.OpAMD64VCVTDQ2PSMasked512Merging, + ssa.OpAMD64VCVTQQ2PSXMasked128Merging, + ssa.OpAMD64VCVTQQ2PSYMasked128Merging, + ssa.OpAMD64VCVTQQ2PSMasked256Merging, + ssa.OpAMD64VCVTUDQ2PSMasked128Merging, + ssa.OpAMD64VCVTUDQ2PSMasked256Merging, + ssa.OpAMD64VCVTUDQ2PSMasked512Merging, + ssa.OpAMD64VCVTUQQ2PSXMasked128Merging, + ssa.OpAMD64VCVTUQQ2PSYMasked128Merging, + ssa.OpAMD64VCVTUQQ2PSMasked256Merging, + ssa.OpAMD64VCVTPS2PDMasked256Merging, + ssa.OpAMD64VCVTPS2PDMasked512Merging, + ssa.OpAMD64VCVTDQ2PDMasked256Merging, + ssa.OpAMD64VCVTDQ2PDMasked512Merging, + ssa.OpAMD64VCVTQQ2PDMasked128Merging, + ssa.OpAMD64VCVTQQ2PDMasked256Merging, + ssa.OpAMD64VCVTQQ2PDMasked512Merging, + ssa.OpAMD64VCVTUDQ2PDMasked256Merging, + ssa.OpAMD64VCVTUDQ2PDMasked512Merging, + ssa.OpAMD64VCVTUQQ2PDMasked128Merging, + ssa.OpAMD64VCVTUQQ2PDMasked256Merging, + ssa.OpAMD64VCVTUQQ2PDMasked512Merging, + ssa.OpAMD64VCVTTPS2DQMasked128Merging, + ssa.OpAMD64VCVTTPS2DQMasked256Merging, + ssa.OpAMD64VCVTTPS2DQMasked512Merging, + ssa.OpAMD64VCVTTPD2DQXMasked128Merging, + ssa.OpAMD64VCVTTPD2DQYMasked128Merging, + ssa.OpAMD64VCVTTPD2DQMasked256Merging, + ssa.OpAMD64VCVTTPS2QQMasked256Merging, + ssa.OpAMD64VCVTTPS2QQMasked512Merging, + ssa.OpAMD64VCVTTPD2QQMasked128Merging, + ssa.OpAMD64VCVTTPD2QQMasked256Merging, + ssa.OpAMD64VCVTTPD2QQMasked512Merging, + ssa.OpAMD64VCVTTPS2UDQMasked128Merging, + ssa.OpAMD64VCVTTPS2UDQMasked256Merging, + ssa.OpAMD64VCVTTPS2UDQMasked512Merging, + ssa.OpAMD64VCVTTPD2UDQXMasked128Merging, + ssa.OpAMD64VCVTTPD2UDQYMasked128Merging, + ssa.OpAMD64VCVTTPD2UDQMasked256Merging, + ssa.OpAMD64VCVTTPS2UQQMasked256Merging, + ssa.OpAMD64VCVTTPS2UQQMasked512Merging, + ssa.OpAMD64VCVTTPD2UQQMasked128Merging, + ssa.OpAMD64VCVTTPD2UQQMasked256Merging, + ssa.OpAMD64VCVTTPD2UQQMasked512Merging, + ssa.OpAMD64VPMOVSXBQMasked128Merging, + ssa.OpAMD64VPMOVSXWQMasked128Merging, + ssa.OpAMD64VPMOVSXDQMasked128Merging, + ssa.OpAMD64VPMOVZXBQMasked128Merging, + ssa.OpAMD64VPMOVZXWQMasked128Merging, + ssa.OpAMD64VPMOVZXDQMasked128Merging, + ssa.OpAMD64VPMOVSXBDMasked128Merging, + ssa.OpAMD64VPMOVSXWDMasked128Merging, + ssa.OpAMD64VPMOVSXBQMasked256Merging, + ssa.OpAMD64VPMOVSXWQMasked256Merging, + ssa.OpAMD64VPMOVZXBDMasked128Merging, + ssa.OpAMD64VPMOVZXWDMasked128Merging, + ssa.OpAMD64VPMOVZXBQMasked256Merging, + ssa.OpAMD64VPMOVZXWQMasked256Merging, + ssa.OpAMD64VPMOVSXBWMasked128Merging, + ssa.OpAMD64VPMOVSXBDMasked256Merging, + ssa.OpAMD64VPMOVSXBQMasked512Merging, + ssa.OpAMD64VPMOVZXBWMasked128Merging, + ssa.OpAMD64VPMOVZXBDMasked256Merging, + ssa.OpAMD64VPMOVZXBQMasked512Merging, + ssa.OpAMD64VPMOVSXBWMasked256Merging, + ssa.OpAMD64VPMOVSXBWMasked512Merging, + ssa.OpAMD64VPMOVSXBDMasked512Merging, + ssa.OpAMD64VPMOVSXWDMasked256Merging, + ssa.OpAMD64VPMOVSXWDMasked512Merging, + ssa.OpAMD64VPMOVSXWQMasked512Merging, + ssa.OpAMD64VPMOVSXDQMasked256Merging, + ssa.OpAMD64VPMOVSXDQMasked512Merging, + ssa.OpAMD64VPMOVZXBWMasked256Merging, + ssa.OpAMD64VPMOVZXBWMasked512Merging, + ssa.OpAMD64VPMOVZXBDMasked512Merging, + ssa.OpAMD64VPMOVZXWDMasked256Merging, + ssa.OpAMD64VPMOVZXWDMasked512Merging, + ssa.OpAMD64VPMOVZXWQMasked512Merging, + ssa.OpAMD64VPMOVZXDQMasked256Merging, + ssa.OpAMD64VPMOVZXDQMasked512Merging, + ssa.OpAMD64VPLZCNTDMasked128Merging, + ssa.OpAMD64VPLZCNTDMasked256Merging, + ssa.OpAMD64VPLZCNTDMasked512Merging, + ssa.OpAMD64VPLZCNTQMasked128Merging, + ssa.OpAMD64VPLZCNTQMasked256Merging, + ssa.OpAMD64VPLZCNTQMasked512Merging, + ssa.OpAMD64VPOPCNTBMasked128Merging, + ssa.OpAMD64VPOPCNTBMasked256Merging, + ssa.OpAMD64VPOPCNTBMasked512Merging, + ssa.OpAMD64VPOPCNTWMasked128Merging, + ssa.OpAMD64VPOPCNTWMasked256Merging, + ssa.OpAMD64VPOPCNTWMasked512Merging, + ssa.OpAMD64VPOPCNTDMasked128Merging, + ssa.OpAMD64VPOPCNTDMasked256Merging, + ssa.OpAMD64VPOPCNTDMasked512Merging, + ssa.OpAMD64VPOPCNTQMasked128Merging, + ssa.OpAMD64VPOPCNTQMasked256Merging, + ssa.OpAMD64VPOPCNTQMasked512Merging, + ssa.OpAMD64VRCP14PSMasked128Merging, + ssa.OpAMD64VRCP14PSMasked256Merging, + ssa.OpAMD64VRCP14PSMasked512Merging, + ssa.OpAMD64VRCP14PDMasked128Merging, + ssa.OpAMD64VRCP14PDMasked256Merging, + ssa.OpAMD64VRCP14PDMasked512Merging, + ssa.OpAMD64VRSQRT14PSMasked128Merging, + ssa.OpAMD64VRSQRT14PSMasked256Merging, + ssa.OpAMD64VRSQRT14PSMasked512Merging, + ssa.OpAMD64VRSQRT14PDMasked128Merging, + ssa.OpAMD64VRSQRT14PDMasked256Merging, + ssa.OpAMD64VRSQRT14PDMasked512Merging, + ssa.OpAMD64VPMOVSWBMasked128_128Merging, + ssa.OpAMD64VPMOVSWBMasked128_256Merging, + ssa.OpAMD64VPMOVSWBMasked256Merging, + ssa.OpAMD64VPMOVSDBMasked128_128Merging, + ssa.OpAMD64VPMOVSDBMasked128_256Merging, + ssa.OpAMD64VPMOVSDBMasked128_512Merging, + ssa.OpAMD64VPMOVSQBMasked128_128Merging, + ssa.OpAMD64VPMOVSQBMasked128_256Merging, + ssa.OpAMD64VPMOVSQBMasked128_512Merging, + ssa.OpAMD64VPMOVSDWMasked128_128Merging, + ssa.OpAMD64VPMOVSDWMasked128_256Merging, + ssa.OpAMD64VPMOVSDWMasked256Merging, + ssa.OpAMD64VPMOVSQWMasked128_128Merging, + ssa.OpAMD64VPMOVSQWMasked128_256Merging, + ssa.OpAMD64VPMOVSQWMasked128_512Merging, + ssa.OpAMD64VPMOVSQDMasked128_128Merging, + ssa.OpAMD64VPMOVSQDMasked128_256Merging, + ssa.OpAMD64VPMOVSQDMasked256Merging, + ssa.OpAMD64VPMOVUSWBMasked128_128Merging, + ssa.OpAMD64VPMOVUSWBMasked128_256Merging, + ssa.OpAMD64VPMOVUSWBMasked256Merging, + ssa.OpAMD64VPMOVUSDBMasked128_128Merging, + ssa.OpAMD64VPMOVUSDBMasked128_256Merging, + ssa.OpAMD64VPMOVUSDBMasked128_512Merging, + ssa.OpAMD64VPMOVUSQBMasked128_128Merging, + ssa.OpAMD64VPMOVUSQBMasked128_256Merging, + ssa.OpAMD64VPMOVUSQBMasked128_512Merging, + ssa.OpAMD64VPMOVUSDWMasked128_128Merging, + ssa.OpAMD64VPMOVUSDWMasked128_256Merging, + ssa.OpAMD64VPMOVUSDWMasked256Merging, + ssa.OpAMD64VPMOVUSQWMasked128_128Merging, + ssa.OpAMD64VPMOVUSQWMasked128_256Merging, + ssa.OpAMD64VPMOVUSQWMasked128_512Merging, + ssa.OpAMD64VPMOVUSQDMasked128_128Merging, + ssa.OpAMD64VPMOVUSQDMasked128_256Merging, + ssa.OpAMD64VPMOVUSQDMasked256Merging, + ssa.OpAMD64VSQRTPSMasked128Merging, + ssa.OpAMD64VSQRTPSMasked256Merging, + ssa.OpAMD64VSQRTPSMasked512Merging, + ssa.OpAMD64VSQRTPDMasked128Merging, + ssa.OpAMD64VSQRTPDMasked256Merging, + ssa.OpAMD64VSQRTPDMasked512Merging, + ssa.OpAMD64VPMOVWBMasked128_128Merging, + ssa.OpAMD64VPMOVWBMasked128_256Merging, + ssa.OpAMD64VPMOVWBMasked256Merging, + ssa.OpAMD64VPMOVDBMasked128_128Merging, + ssa.OpAMD64VPMOVDBMasked128_256Merging, + ssa.OpAMD64VPMOVDBMasked128_512Merging, + ssa.OpAMD64VPMOVQBMasked128_128Merging, + ssa.OpAMD64VPMOVQBMasked128_256Merging, + ssa.OpAMD64VPMOVQBMasked128_512Merging, + ssa.OpAMD64VPMOVDWMasked128_128Merging, + ssa.OpAMD64VPMOVDWMasked128_256Merging, + ssa.OpAMD64VPMOVDWMasked256Merging, + ssa.OpAMD64VPMOVQWMasked128_128Merging, + ssa.OpAMD64VPMOVQWMasked128_256Merging, + ssa.OpAMD64VPMOVQWMasked128_512Merging, + ssa.OpAMD64VPMOVQDMasked128_128Merging, + ssa.OpAMD64VPMOVQDMasked128_256Merging, + ssa.OpAMD64VPMOVQDMasked256Merging, + ssa.OpAMD64VPBROADCASTQMasked128Merging, + ssa.OpAMD64VBROADCASTSSMasked128Merging, + ssa.OpAMD64VBROADCASTSDMasked256Merging, + ssa.OpAMD64VPBROADCASTDMasked128Merging, + ssa.OpAMD64VPBROADCASTQMasked256Merging, + ssa.OpAMD64VBROADCASTSSMasked256Merging, + ssa.OpAMD64VBROADCASTSDMasked512Merging, + ssa.OpAMD64VPBROADCASTWMasked128Merging, + ssa.OpAMD64VPBROADCASTDMasked256Merging, + ssa.OpAMD64VPBROADCASTQMasked512Merging, + ssa.OpAMD64VBROADCASTSSMasked512Merging, + ssa.OpAMD64VPBROADCASTBMasked128Merging, + ssa.OpAMD64VPBROADCASTWMasked256Merging, + ssa.OpAMD64VPBROADCASTDMasked512Merging, + ssa.OpAMD64VPBROADCASTBMasked256Merging, + ssa.OpAMD64VPBROADCASTWMasked512Merging, + ssa.OpAMD64VPBROADCASTBMasked512Merging, + ssa.OpAMD64VPSHUFDMasked256Merging, + ssa.OpAMD64VPSHUFDMasked512Merging, + ssa.OpAMD64VPSHUFHWMasked256Merging, + ssa.OpAMD64VPSHUFHWMasked512Merging, + ssa.OpAMD64VPSHUFHWMasked128Merging, + ssa.OpAMD64VPSHUFLWMasked256Merging, + ssa.OpAMD64VPSHUFLWMasked512Merging, + ssa.OpAMD64VPSHUFLWMasked128Merging, + ssa.OpAMD64VPSHUFDMasked128Merging, + ssa.OpAMD64VPROLDMasked128Merging, + ssa.OpAMD64VPROLDMasked256Merging, + ssa.OpAMD64VPROLDMasked512Merging, + ssa.OpAMD64VPROLQMasked128Merging, + ssa.OpAMD64VPROLQMasked256Merging, + ssa.OpAMD64VPROLQMasked512Merging, + ssa.OpAMD64VPRORDMasked128Merging, + ssa.OpAMD64VPRORDMasked256Merging, + ssa.OpAMD64VPRORDMasked512Merging, + ssa.OpAMD64VPRORQMasked128Merging, + ssa.OpAMD64VPRORQMasked256Merging, + ssa.OpAMD64VPRORQMasked512Merging, + ssa.OpAMD64VPSLLWMasked128constMerging, + ssa.OpAMD64VPSLLWMasked256constMerging, + ssa.OpAMD64VPSLLWMasked512constMerging, + ssa.OpAMD64VPSLLDMasked128constMerging, + ssa.OpAMD64VPSLLDMasked256constMerging, + ssa.OpAMD64VPSLLDMasked512constMerging, + ssa.OpAMD64VPSLLQMasked128constMerging, + ssa.OpAMD64VPSLLQMasked256constMerging, + ssa.OpAMD64VPSLLQMasked512constMerging, + ssa.OpAMD64VPSRAWMasked128constMerging, + ssa.OpAMD64VPSRAWMasked256constMerging, + ssa.OpAMD64VPSRAWMasked512constMerging, + ssa.OpAMD64VPSRADMasked128constMerging, + ssa.OpAMD64VPSRADMasked256constMerging, + ssa.OpAMD64VPSRADMasked512constMerging, + ssa.OpAMD64VPSRAQMasked128constMerging, + ssa.OpAMD64VPSRAQMasked256constMerging, + ssa.OpAMD64VPSRAQMasked512constMerging, + ssa.OpAMD64VPSRLWMasked128constMerging, + ssa.OpAMD64VPSRLWMasked256constMerging, + ssa.OpAMD64VPSRLWMasked512constMerging, + ssa.OpAMD64VPSRLDMasked128constMerging, + ssa.OpAMD64VPSRLDMasked256constMerging, + ssa.OpAMD64VPSRLDMasked512constMerging, + ssa.OpAMD64VPSRLQMasked128constMerging, + ssa.OpAMD64VPSRLQMasked256constMerging, + ssa.OpAMD64VPSRLQMasked512constMerging: + p = simdV2kvResultInArg0(s, v) + + default: + // Unknown reg shape + return false + } + + // Masked operation are always compiled with zeroing. + switch v.Op { + case ssa.OpAMD64VPABSBMasked128, + ssa.OpAMD64VPABSBMasked128load, + ssa.OpAMD64VPABSBMasked256, + ssa.OpAMD64VPABSBMasked256load, + ssa.OpAMD64VPABSBMasked512, + ssa.OpAMD64VPABSWMasked128, + ssa.OpAMD64VPABSWMasked128load, + ssa.OpAMD64VPABSWMasked256, + ssa.OpAMD64VPABSWMasked256load, + ssa.OpAMD64VPABSWMasked512, + ssa.OpAMD64VPABSDMasked128, + ssa.OpAMD64VPABSDMasked128load, + ssa.OpAMD64VPABSDMasked256, + ssa.OpAMD64VPABSDMasked256load, + ssa.OpAMD64VPABSDMasked512, + ssa.OpAMD64VPABSDMasked512load, + ssa.OpAMD64VPABSQMasked128, + ssa.OpAMD64VPABSQMasked128load, + ssa.OpAMD64VPABSQMasked256, + ssa.OpAMD64VPABSQMasked256load, + ssa.OpAMD64VPABSQMasked512, + ssa.OpAMD64VPABSQMasked512load, + ssa.OpAMD64VPDPWSSDMasked128, + ssa.OpAMD64VPDPWSSDMasked128load, + ssa.OpAMD64VPDPWSSDMasked256, + ssa.OpAMD64VPDPWSSDMasked256load, + ssa.OpAMD64VPDPWSSDMasked512, + ssa.OpAMD64VPDPWSSDMasked512load, + ssa.OpAMD64VADDPSMasked128, + ssa.OpAMD64VADDPSMasked128load, + ssa.OpAMD64VADDPSMasked256, + ssa.OpAMD64VADDPSMasked256load, + ssa.OpAMD64VADDPSMasked512, + ssa.OpAMD64VADDPSMasked512load, + ssa.OpAMD64VADDPDMasked128, + ssa.OpAMD64VADDPDMasked128load, + ssa.OpAMD64VADDPDMasked256, + ssa.OpAMD64VADDPDMasked256load, + ssa.OpAMD64VADDPDMasked512, + ssa.OpAMD64VADDPDMasked512load, + ssa.OpAMD64VPADDBMasked128, + ssa.OpAMD64VPADDBMasked128load, + ssa.OpAMD64VPADDBMasked256, + ssa.OpAMD64VPADDBMasked256load, + ssa.OpAMD64VPADDBMasked512, + ssa.OpAMD64VPADDWMasked128, + ssa.OpAMD64VPADDWMasked128load, + ssa.OpAMD64VPADDWMasked256, + ssa.OpAMD64VPADDWMasked256load, + ssa.OpAMD64VPADDWMasked512, + ssa.OpAMD64VPADDDMasked128, + ssa.OpAMD64VPADDDMasked128load, + ssa.OpAMD64VPADDDMasked256, + ssa.OpAMD64VPADDDMasked256load, + ssa.OpAMD64VPADDDMasked512, + ssa.OpAMD64VPADDDMasked512load, + ssa.OpAMD64VPADDQMasked128, + ssa.OpAMD64VPADDQMasked128load, + ssa.OpAMD64VPADDQMasked256, + ssa.OpAMD64VPADDQMasked256load, + ssa.OpAMD64VPADDQMasked512, + ssa.OpAMD64VPADDQMasked512load, + ssa.OpAMD64VPADDSBMasked128, + ssa.OpAMD64VPADDSBMasked128load, + ssa.OpAMD64VPADDSBMasked256, + ssa.OpAMD64VPADDSBMasked256load, + ssa.OpAMD64VPADDSBMasked512, + ssa.OpAMD64VPADDSWMasked128, + ssa.OpAMD64VPADDSWMasked128load, + ssa.OpAMD64VPADDSWMasked256, + ssa.OpAMD64VPADDSWMasked256load, + ssa.OpAMD64VPADDSWMasked512, + ssa.OpAMD64VPADDUSBMasked128, + ssa.OpAMD64VPADDUSBMasked128load, + ssa.OpAMD64VPADDUSBMasked256, + ssa.OpAMD64VPADDUSBMasked256load, + ssa.OpAMD64VPADDUSBMasked512, + ssa.OpAMD64VPADDUSWMasked128, + ssa.OpAMD64VPADDUSWMasked128load, + ssa.OpAMD64VPADDUSWMasked256, + ssa.OpAMD64VPADDUSWMasked256load, + ssa.OpAMD64VPADDUSWMasked512, + ssa.OpAMD64VPANDDMasked128, + ssa.OpAMD64VPANDDMasked128load, + ssa.OpAMD64VPANDDMasked256, + ssa.OpAMD64VPANDDMasked256load, + ssa.OpAMD64VPANDDMasked512, + ssa.OpAMD64VPANDDMasked512load, + ssa.OpAMD64VPANDQMasked128, + ssa.OpAMD64VPANDQMasked128load, + ssa.OpAMD64VPANDQMasked256, + ssa.OpAMD64VPANDQMasked256load, + ssa.OpAMD64VPANDQMasked512, + ssa.OpAMD64VPANDQMasked512load, + ssa.OpAMD64VPANDNDMasked128, + ssa.OpAMD64VPANDNDMasked128load, + ssa.OpAMD64VPANDNDMasked256, + ssa.OpAMD64VPANDNDMasked256load, + ssa.OpAMD64VPANDNDMasked512, + ssa.OpAMD64VPANDNDMasked512load, + ssa.OpAMD64VPANDNQMasked128, + ssa.OpAMD64VPANDNQMasked128load, + ssa.OpAMD64VPANDNQMasked256, + ssa.OpAMD64VPANDNQMasked256load, + ssa.OpAMD64VPANDNQMasked512, + ssa.OpAMD64VPANDNQMasked512load, + ssa.OpAMD64VPAVGBMasked128, + ssa.OpAMD64VPAVGBMasked128load, + ssa.OpAMD64VPAVGBMasked256, + ssa.OpAMD64VPAVGBMasked256load, + ssa.OpAMD64VPAVGBMasked512, + ssa.OpAMD64VPAVGWMasked128, + ssa.OpAMD64VPAVGWMasked128load, + ssa.OpAMD64VPAVGWMasked256, + ssa.OpAMD64VPAVGWMasked256load, + ssa.OpAMD64VPAVGWMasked512, + ssa.OpAMD64VRNDSCALEPSMasked128, + ssa.OpAMD64VRNDSCALEPSMasked128load, + ssa.OpAMD64VRNDSCALEPSMasked256, + ssa.OpAMD64VRNDSCALEPSMasked256load, + ssa.OpAMD64VRNDSCALEPSMasked512, + ssa.OpAMD64VRNDSCALEPSMasked512load, + ssa.OpAMD64VRNDSCALEPDMasked128, + ssa.OpAMD64VRNDSCALEPDMasked128load, + ssa.OpAMD64VRNDSCALEPDMasked256, + ssa.OpAMD64VRNDSCALEPDMasked256load, + ssa.OpAMD64VRNDSCALEPDMasked512, + ssa.OpAMD64VRNDSCALEPDMasked512load, + ssa.OpAMD64VREDUCEPSMasked128, + ssa.OpAMD64VREDUCEPSMasked128load, + ssa.OpAMD64VREDUCEPSMasked256, + ssa.OpAMD64VREDUCEPSMasked256load, + ssa.OpAMD64VREDUCEPSMasked512, + ssa.OpAMD64VREDUCEPSMasked512load, + ssa.OpAMD64VREDUCEPDMasked128, + ssa.OpAMD64VREDUCEPDMasked128load, + ssa.OpAMD64VREDUCEPDMasked256, + ssa.OpAMD64VREDUCEPDMasked256load, + ssa.OpAMD64VREDUCEPDMasked512, + ssa.OpAMD64VREDUCEPDMasked512load, + ssa.OpAMD64VCOMPRESSPSMasked128, + ssa.OpAMD64VCOMPRESSPSMasked256, + ssa.OpAMD64VCOMPRESSPSMasked512, + ssa.OpAMD64VCOMPRESSPDMasked128, + ssa.OpAMD64VCOMPRESSPDMasked256, + ssa.OpAMD64VCOMPRESSPDMasked512, + ssa.OpAMD64VPCOMPRESSBMasked128, + ssa.OpAMD64VPCOMPRESSBMasked256, + ssa.OpAMD64VPCOMPRESSBMasked512, + ssa.OpAMD64VPCOMPRESSWMasked128, + ssa.OpAMD64VPCOMPRESSWMasked256, + ssa.OpAMD64VPCOMPRESSWMasked512, + ssa.OpAMD64VPCOMPRESSDMasked128, + ssa.OpAMD64VPCOMPRESSDMasked256, + ssa.OpAMD64VPCOMPRESSDMasked512, + ssa.OpAMD64VPCOMPRESSQMasked128, + ssa.OpAMD64VPCOMPRESSQMasked256, + ssa.OpAMD64VPCOMPRESSQMasked512, + ssa.OpAMD64VPERMI2BMasked128, + ssa.OpAMD64VPERMI2BMasked128load, + ssa.OpAMD64VPERMI2BMasked256, + ssa.OpAMD64VPERMI2BMasked256load, + ssa.OpAMD64VPERMI2BMasked512, + ssa.OpAMD64VPERMI2WMasked128, + ssa.OpAMD64VPERMI2WMasked128load, + ssa.OpAMD64VPERMI2WMasked256, + ssa.OpAMD64VPERMI2WMasked256load, + ssa.OpAMD64VPERMI2WMasked512, + ssa.OpAMD64VPERMI2PSMasked128, + ssa.OpAMD64VPERMI2PSMasked128load, + ssa.OpAMD64VPERMI2DMasked128, + ssa.OpAMD64VPERMI2DMasked128load, + ssa.OpAMD64VPERMI2PSMasked256, + ssa.OpAMD64VPERMI2PSMasked256load, + ssa.OpAMD64VPERMI2DMasked256, + ssa.OpAMD64VPERMI2DMasked256load, + ssa.OpAMD64VPERMI2PSMasked512, + ssa.OpAMD64VPERMI2PSMasked512load, + ssa.OpAMD64VPERMI2DMasked512, + ssa.OpAMD64VPERMI2DMasked512load, + ssa.OpAMD64VPERMI2PDMasked128, + ssa.OpAMD64VPERMI2PDMasked128load, + ssa.OpAMD64VPERMI2QMasked128, + ssa.OpAMD64VPERMI2QMasked128load, + ssa.OpAMD64VPERMI2PDMasked256, + ssa.OpAMD64VPERMI2PDMasked256load, + ssa.OpAMD64VPERMI2QMasked256, + ssa.OpAMD64VPERMI2QMasked256load, + ssa.OpAMD64VPERMI2PDMasked512, + ssa.OpAMD64VPERMI2PDMasked512load, + ssa.OpAMD64VPERMI2QMasked512, + ssa.OpAMD64VPERMI2QMasked512load, + ssa.OpAMD64VPALIGNRMasked256, + ssa.OpAMD64VPALIGNRMasked256load, + ssa.OpAMD64VPALIGNRMasked512, + ssa.OpAMD64VPALIGNRMasked128, + ssa.OpAMD64VPALIGNRMasked128load, + ssa.OpAMD64VCVTPD2PSXMasked128, + ssa.OpAMD64VCVTPD2PSXMasked128load, + ssa.OpAMD64VCVTPD2PSYMasked128, + ssa.OpAMD64VCVTPD2PSYMasked128load, + ssa.OpAMD64VCVTPD2PSMasked256, + ssa.OpAMD64VCVTPD2PSMasked256load, + ssa.OpAMD64VCVTDQ2PSMasked128, + ssa.OpAMD64VCVTDQ2PSMasked128load, + ssa.OpAMD64VCVTDQ2PSMasked256, + ssa.OpAMD64VCVTDQ2PSMasked256load, + ssa.OpAMD64VCVTDQ2PSMasked512, + ssa.OpAMD64VCVTDQ2PSMasked512load, + ssa.OpAMD64VCVTQQ2PSXMasked128, + ssa.OpAMD64VCVTQQ2PSXMasked128load, + ssa.OpAMD64VCVTQQ2PSYMasked128, + ssa.OpAMD64VCVTQQ2PSYMasked128load, + ssa.OpAMD64VCVTQQ2PSMasked256, + ssa.OpAMD64VCVTQQ2PSMasked256load, + ssa.OpAMD64VCVTUDQ2PSMasked128, + ssa.OpAMD64VCVTUDQ2PSMasked128load, + ssa.OpAMD64VCVTUDQ2PSMasked256, + ssa.OpAMD64VCVTUDQ2PSMasked256load, + ssa.OpAMD64VCVTUDQ2PSMasked512, + ssa.OpAMD64VCVTUDQ2PSMasked512load, + ssa.OpAMD64VCVTUQQ2PSXMasked128, + ssa.OpAMD64VCVTUQQ2PSXMasked128load, + ssa.OpAMD64VCVTUQQ2PSYMasked128, + ssa.OpAMD64VCVTUQQ2PSYMasked128load, + ssa.OpAMD64VCVTUQQ2PSMasked256, + ssa.OpAMD64VCVTUQQ2PSMasked256load, + ssa.OpAMD64VCVTPS2PDMasked256, + ssa.OpAMD64VCVTPS2PDMasked256load, + ssa.OpAMD64VCVTPS2PDMasked512, + ssa.OpAMD64VCVTPS2PDMasked512load, + ssa.OpAMD64VCVTDQ2PDMasked256, + ssa.OpAMD64VCVTDQ2PDMasked256load, + ssa.OpAMD64VCVTDQ2PDMasked512, + ssa.OpAMD64VCVTDQ2PDMasked512load, + ssa.OpAMD64VCVTQQ2PDMasked128, + ssa.OpAMD64VCVTQQ2PDMasked128load, + ssa.OpAMD64VCVTQQ2PDMasked256, + ssa.OpAMD64VCVTQQ2PDMasked256load, + ssa.OpAMD64VCVTQQ2PDMasked512, + ssa.OpAMD64VCVTQQ2PDMasked512load, + ssa.OpAMD64VCVTUDQ2PDMasked256, + ssa.OpAMD64VCVTUDQ2PDMasked256load, + ssa.OpAMD64VCVTUDQ2PDMasked512, + ssa.OpAMD64VCVTUDQ2PDMasked512load, + ssa.OpAMD64VCVTUQQ2PDMasked128, + ssa.OpAMD64VCVTUQQ2PDMasked128load, + ssa.OpAMD64VCVTUQQ2PDMasked256, + ssa.OpAMD64VCVTUQQ2PDMasked256load, + ssa.OpAMD64VCVTUQQ2PDMasked512, + ssa.OpAMD64VCVTUQQ2PDMasked512load, + ssa.OpAMD64VCVTTPS2DQMasked128, + ssa.OpAMD64VCVTTPS2DQMasked128load, + ssa.OpAMD64VCVTTPS2DQMasked256, + ssa.OpAMD64VCVTTPS2DQMasked256load, + ssa.OpAMD64VCVTTPS2DQMasked512, + ssa.OpAMD64VCVTTPS2DQMasked512load, + ssa.OpAMD64VCVTTPD2DQXMasked128, + ssa.OpAMD64VCVTTPD2DQXMasked128load, + ssa.OpAMD64VCVTTPD2DQYMasked128, + ssa.OpAMD64VCVTTPD2DQYMasked128load, + ssa.OpAMD64VCVTTPD2DQMasked256, + ssa.OpAMD64VCVTTPD2DQMasked256load, + ssa.OpAMD64VCVTTPS2QQMasked256, + ssa.OpAMD64VCVTTPS2QQMasked256load, + ssa.OpAMD64VCVTTPS2QQMasked512, + ssa.OpAMD64VCVTTPS2QQMasked512load, + ssa.OpAMD64VCVTTPD2QQMasked128, + ssa.OpAMD64VCVTTPD2QQMasked128load, + ssa.OpAMD64VCVTTPD2QQMasked256, + ssa.OpAMD64VCVTTPD2QQMasked256load, + ssa.OpAMD64VCVTTPD2QQMasked512, + ssa.OpAMD64VCVTTPD2QQMasked512load, + ssa.OpAMD64VCVTTPS2UDQMasked128, + ssa.OpAMD64VCVTTPS2UDQMasked128load, + ssa.OpAMD64VCVTTPS2UDQMasked256, + ssa.OpAMD64VCVTTPS2UDQMasked256load, + ssa.OpAMD64VCVTTPS2UDQMasked512, + ssa.OpAMD64VCVTTPS2UDQMasked512load, + ssa.OpAMD64VCVTTPD2UDQXMasked128, + ssa.OpAMD64VCVTTPD2UDQXMasked128load, + ssa.OpAMD64VCVTTPD2UDQYMasked128, + ssa.OpAMD64VCVTTPD2UDQYMasked128load, + ssa.OpAMD64VCVTTPD2UDQMasked256, + ssa.OpAMD64VCVTTPD2UDQMasked256load, + ssa.OpAMD64VCVTTPS2UQQMasked256, + ssa.OpAMD64VCVTTPS2UQQMasked256load, + ssa.OpAMD64VCVTTPS2UQQMasked512, + ssa.OpAMD64VCVTTPS2UQQMasked512load, + ssa.OpAMD64VCVTTPD2UQQMasked128, + ssa.OpAMD64VCVTTPD2UQQMasked128load, + ssa.OpAMD64VCVTTPD2UQQMasked256, + ssa.OpAMD64VCVTTPD2UQQMasked256load, + ssa.OpAMD64VCVTTPD2UQQMasked512, + ssa.OpAMD64VCVTTPD2UQQMasked512load, + ssa.OpAMD64VDIVPSMasked128, + ssa.OpAMD64VDIVPSMasked128load, + ssa.OpAMD64VDIVPSMasked256, + ssa.OpAMD64VDIVPSMasked256load, + ssa.OpAMD64VDIVPSMasked512, + ssa.OpAMD64VDIVPSMasked512load, + ssa.OpAMD64VDIVPDMasked128, + ssa.OpAMD64VDIVPDMasked128load, + ssa.OpAMD64VDIVPDMasked256, + ssa.OpAMD64VDIVPDMasked256load, + ssa.OpAMD64VDIVPDMasked512, + ssa.OpAMD64VDIVPDMasked512load, + ssa.OpAMD64VPMADDWDMasked128, + ssa.OpAMD64VPMADDWDMasked128load, + ssa.OpAMD64VPMADDWDMasked256, + ssa.OpAMD64VPMADDWDMasked256load, + ssa.OpAMD64VPMADDWDMasked512, + ssa.OpAMD64VPMADDUBSWMasked128, + ssa.OpAMD64VPMADDUBSWMasked128load, + ssa.OpAMD64VPMADDUBSWMasked256, + ssa.OpAMD64VPMADDUBSWMasked256load, + ssa.OpAMD64VPMADDUBSWMasked512, + ssa.OpAMD64VEXPANDPSMasked128, + ssa.OpAMD64VEXPANDPSMasked128load, + ssa.OpAMD64VEXPANDPSMasked256, + ssa.OpAMD64VEXPANDPSMasked256load, + ssa.OpAMD64VEXPANDPSMasked512, + ssa.OpAMD64VEXPANDPDMasked128, + ssa.OpAMD64VEXPANDPDMasked128load, + ssa.OpAMD64VEXPANDPDMasked256, + ssa.OpAMD64VEXPANDPDMasked256load, + ssa.OpAMD64VEXPANDPDMasked512, + ssa.OpAMD64VPEXPANDBMasked128, + ssa.OpAMD64VPEXPANDBMasked128load, + ssa.OpAMD64VPEXPANDBMasked256, + ssa.OpAMD64VPEXPANDBMasked256load, + ssa.OpAMD64VPEXPANDBMasked512, + ssa.OpAMD64VPEXPANDWMasked128, + ssa.OpAMD64VPEXPANDWMasked128load, + ssa.OpAMD64VPEXPANDWMasked256, + ssa.OpAMD64VPEXPANDWMasked256load, + ssa.OpAMD64VPEXPANDWMasked512, + ssa.OpAMD64VPEXPANDDMasked128, + ssa.OpAMD64VPEXPANDDMasked128load, + ssa.OpAMD64VPEXPANDDMasked256, + ssa.OpAMD64VPEXPANDDMasked256load, + ssa.OpAMD64VPEXPANDDMasked512, + ssa.OpAMD64VPEXPANDQMasked128, + ssa.OpAMD64VPEXPANDQMasked128load, + ssa.OpAMD64VPEXPANDQMasked256, + ssa.OpAMD64VPEXPANDQMasked256load, + ssa.OpAMD64VPEXPANDQMasked512, + ssa.OpAMD64VPMOVSXBQMasked128, + ssa.OpAMD64VPMOVSXWQMasked128, + ssa.OpAMD64VPMOVSXWQMasked128load, + ssa.OpAMD64VPMOVSXDQMasked128, + ssa.OpAMD64VPMOVSXDQMasked128load, + ssa.OpAMD64VPMOVZXBQMasked128, + ssa.OpAMD64VPMOVZXWQMasked128, + ssa.OpAMD64VPMOVZXWQMasked128load, + ssa.OpAMD64VPMOVZXDQMasked128, + ssa.OpAMD64VPMOVZXDQMasked128load, + ssa.OpAMD64VPMOVSXBDMasked128, + ssa.OpAMD64VPMOVSXBDMasked128load, + ssa.OpAMD64VPMOVSXWDMasked128, + ssa.OpAMD64VPMOVSXWDMasked128load, + ssa.OpAMD64VPMOVSXBQMasked256, + ssa.OpAMD64VPMOVSXBQMasked256load, + ssa.OpAMD64VPMOVSXWQMasked256, + ssa.OpAMD64VPMOVSXWQMasked256load, + ssa.OpAMD64VPMOVZXBDMasked128, + ssa.OpAMD64VPMOVZXBDMasked128load, + ssa.OpAMD64VPMOVZXWDMasked128, + ssa.OpAMD64VPMOVZXWDMasked128load, + ssa.OpAMD64VPMOVZXBQMasked256, + ssa.OpAMD64VPMOVZXBQMasked256load, + ssa.OpAMD64VPMOVZXWQMasked256, + ssa.OpAMD64VPMOVZXWQMasked256load, + ssa.OpAMD64VPMOVSXBWMasked128, + ssa.OpAMD64VPMOVSXBWMasked128load, + ssa.OpAMD64VPMOVSXBDMasked256, + ssa.OpAMD64VPMOVSXBDMasked256load, + ssa.OpAMD64VPMOVSXBQMasked512, + ssa.OpAMD64VPMOVSXBQMasked512load, + ssa.OpAMD64VPMOVZXBWMasked128, + ssa.OpAMD64VPMOVZXBWMasked128load, + ssa.OpAMD64VPMOVZXBDMasked256, + ssa.OpAMD64VPMOVZXBDMasked256load, + ssa.OpAMD64VPMOVZXBQMasked512, + ssa.OpAMD64VPMOVZXBQMasked512load, + ssa.OpAMD64VPMOVSXBWMasked256, + ssa.OpAMD64VPMOVSXBWMasked256load, + ssa.OpAMD64VPMOVSXBWMasked512, + ssa.OpAMD64VPMOVSXBWMasked512load, + ssa.OpAMD64VPMOVSXBDMasked512, + ssa.OpAMD64VPMOVSXBDMasked512load, + ssa.OpAMD64VPMOVSXWDMasked256, + ssa.OpAMD64VPMOVSXWDMasked256load, + ssa.OpAMD64VPMOVSXWDMasked512, + ssa.OpAMD64VPMOVSXWDMasked512load, + ssa.OpAMD64VPMOVSXWQMasked512, + ssa.OpAMD64VPMOVSXWQMasked512load, + ssa.OpAMD64VPMOVSXDQMasked256, + ssa.OpAMD64VPMOVSXDQMasked256load, + ssa.OpAMD64VPMOVSXDQMasked512, + ssa.OpAMD64VPMOVSXDQMasked512load, + ssa.OpAMD64VPMOVZXBWMasked256, + ssa.OpAMD64VPMOVZXBWMasked256load, + ssa.OpAMD64VPMOVZXBWMasked512, + ssa.OpAMD64VPMOVZXBWMasked512load, + ssa.OpAMD64VPMOVZXBDMasked512, + ssa.OpAMD64VPMOVZXBDMasked512load, + ssa.OpAMD64VPMOVZXWDMasked256, + ssa.OpAMD64VPMOVZXWDMasked256load, + ssa.OpAMD64VPMOVZXWDMasked512, + ssa.OpAMD64VPMOVZXWDMasked512load, + ssa.OpAMD64VPMOVZXWQMasked512, + ssa.OpAMD64VPMOVZXWQMasked512load, + ssa.OpAMD64VPMOVZXDQMasked256, + ssa.OpAMD64VPMOVZXDQMasked256load, + ssa.OpAMD64VPMOVZXDQMasked512, + ssa.OpAMD64VPMOVZXDQMasked512load, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked128, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked128load, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked256, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked256load, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked512, + ssa.OpAMD64VGF2P8AFFINEINVQBMasked512load, + ssa.OpAMD64VGF2P8AFFINEQBMasked128, + ssa.OpAMD64VGF2P8AFFINEQBMasked128load, + ssa.OpAMD64VGF2P8AFFINEQBMasked256, + ssa.OpAMD64VGF2P8AFFINEQBMasked256load, + ssa.OpAMD64VGF2P8AFFINEQBMasked512, + ssa.OpAMD64VGF2P8AFFINEQBMasked512load, + ssa.OpAMD64VGF2P8MULBMasked128, + ssa.OpAMD64VGF2P8MULBMasked128load, + ssa.OpAMD64VGF2P8MULBMasked256, + ssa.OpAMD64VGF2P8MULBMasked256load, + ssa.OpAMD64VGF2P8MULBMasked512, + ssa.OpAMD64VPLZCNTDMasked128, + ssa.OpAMD64VPLZCNTDMasked128load, + ssa.OpAMD64VPLZCNTDMasked256, + ssa.OpAMD64VPLZCNTDMasked256load, + ssa.OpAMD64VPLZCNTDMasked512, + ssa.OpAMD64VPLZCNTDMasked512load, + ssa.OpAMD64VPLZCNTQMasked128, + ssa.OpAMD64VPLZCNTQMasked128load, + ssa.OpAMD64VPLZCNTQMasked256, + ssa.OpAMD64VPLZCNTQMasked256load, + ssa.OpAMD64VPLZCNTQMasked512, + ssa.OpAMD64VPLZCNTQMasked512load, + ssa.OpAMD64VMAXPSMasked128, + ssa.OpAMD64VMAXPSMasked128load, + ssa.OpAMD64VMAXPSMasked256, + ssa.OpAMD64VMAXPSMasked256load, + ssa.OpAMD64VMAXPSMasked512, + ssa.OpAMD64VMAXPSMasked512load, + ssa.OpAMD64VMAXPDMasked128, + ssa.OpAMD64VMAXPDMasked128load, + ssa.OpAMD64VMAXPDMasked256, + ssa.OpAMD64VMAXPDMasked256load, + ssa.OpAMD64VMAXPDMasked512, + ssa.OpAMD64VMAXPDMasked512load, + ssa.OpAMD64VPMAXSBMasked128, + ssa.OpAMD64VPMAXSBMasked128load, + ssa.OpAMD64VPMAXSBMasked256, + ssa.OpAMD64VPMAXSBMasked256load, + ssa.OpAMD64VPMAXSBMasked512, + ssa.OpAMD64VPMAXSWMasked128, + ssa.OpAMD64VPMAXSWMasked128load, + ssa.OpAMD64VPMAXSWMasked256, + ssa.OpAMD64VPMAXSWMasked256load, + ssa.OpAMD64VPMAXSWMasked512, + ssa.OpAMD64VPMAXSDMasked128, + ssa.OpAMD64VPMAXSDMasked128load, + ssa.OpAMD64VPMAXSDMasked256, + ssa.OpAMD64VPMAXSDMasked256load, + ssa.OpAMD64VPMAXSDMasked512, + ssa.OpAMD64VPMAXSDMasked512load, + ssa.OpAMD64VPMAXSQMasked128, + ssa.OpAMD64VPMAXSQMasked128load, + ssa.OpAMD64VPMAXSQMasked256, + ssa.OpAMD64VPMAXSQMasked256load, + ssa.OpAMD64VPMAXSQMasked512, + ssa.OpAMD64VPMAXSQMasked512load, + ssa.OpAMD64VPMAXUBMasked128, + ssa.OpAMD64VPMAXUBMasked128load, + ssa.OpAMD64VPMAXUBMasked256, + ssa.OpAMD64VPMAXUBMasked256load, + ssa.OpAMD64VPMAXUBMasked512, + ssa.OpAMD64VPMAXUWMasked128, + ssa.OpAMD64VPMAXUWMasked128load, + ssa.OpAMD64VPMAXUWMasked256, + ssa.OpAMD64VPMAXUWMasked256load, + ssa.OpAMD64VPMAXUWMasked512, + ssa.OpAMD64VPMAXUDMasked128, + ssa.OpAMD64VPMAXUDMasked128load, + ssa.OpAMD64VPMAXUDMasked256, + ssa.OpAMD64VPMAXUDMasked256load, + ssa.OpAMD64VPMAXUDMasked512, + ssa.OpAMD64VPMAXUDMasked512load, + ssa.OpAMD64VPMAXUQMasked128, + ssa.OpAMD64VPMAXUQMasked128load, + ssa.OpAMD64VPMAXUQMasked256, + ssa.OpAMD64VPMAXUQMasked256load, + ssa.OpAMD64VPMAXUQMasked512, + ssa.OpAMD64VPMAXUQMasked512load, + ssa.OpAMD64VMINPSMasked128, + ssa.OpAMD64VMINPSMasked128load, + ssa.OpAMD64VMINPSMasked256, + ssa.OpAMD64VMINPSMasked256load, + ssa.OpAMD64VMINPSMasked512, + ssa.OpAMD64VMINPSMasked512load, + ssa.OpAMD64VMINPDMasked128, + ssa.OpAMD64VMINPDMasked128load, + ssa.OpAMD64VMINPDMasked256, + ssa.OpAMD64VMINPDMasked256load, + ssa.OpAMD64VMINPDMasked512, + ssa.OpAMD64VMINPDMasked512load, + ssa.OpAMD64VPMINSBMasked128, + ssa.OpAMD64VPMINSBMasked128load, + ssa.OpAMD64VPMINSBMasked256, + ssa.OpAMD64VPMINSBMasked256load, + ssa.OpAMD64VPMINSBMasked512, + ssa.OpAMD64VPMINSWMasked128, + ssa.OpAMD64VPMINSWMasked128load, + ssa.OpAMD64VPMINSWMasked256, + ssa.OpAMD64VPMINSWMasked256load, + ssa.OpAMD64VPMINSWMasked512, + ssa.OpAMD64VPMINSDMasked128, + ssa.OpAMD64VPMINSDMasked128load, + ssa.OpAMD64VPMINSDMasked256, + ssa.OpAMD64VPMINSDMasked256load, + ssa.OpAMD64VPMINSDMasked512, + ssa.OpAMD64VPMINSDMasked512load, + ssa.OpAMD64VPMINSQMasked128, + ssa.OpAMD64VPMINSQMasked128load, + ssa.OpAMD64VPMINSQMasked256, + ssa.OpAMD64VPMINSQMasked256load, + ssa.OpAMD64VPMINSQMasked512, + ssa.OpAMD64VPMINSQMasked512load, + ssa.OpAMD64VPMINUBMasked128, + ssa.OpAMD64VPMINUBMasked128load, + ssa.OpAMD64VPMINUBMasked256, + ssa.OpAMD64VPMINUBMasked256load, + ssa.OpAMD64VPMINUBMasked512, + ssa.OpAMD64VPMINUWMasked128, + ssa.OpAMD64VPMINUWMasked128load, + ssa.OpAMD64VPMINUWMasked256, + ssa.OpAMD64VPMINUWMasked256load, + ssa.OpAMD64VPMINUWMasked512, + ssa.OpAMD64VPMINUDMasked128, + ssa.OpAMD64VPMINUDMasked128load, + ssa.OpAMD64VPMINUDMasked256, + ssa.OpAMD64VPMINUDMasked256load, + ssa.OpAMD64VPMINUDMasked512, + ssa.OpAMD64VPMINUDMasked512load, + ssa.OpAMD64VPMINUQMasked128, + ssa.OpAMD64VPMINUQMasked128load, + ssa.OpAMD64VPMINUQMasked256, + ssa.OpAMD64VPMINUQMasked256load, + ssa.OpAMD64VPMINUQMasked512, + ssa.OpAMD64VPMINUQMasked512load, + ssa.OpAMD64VFMADDSUB213PSMasked128, + ssa.OpAMD64VFMADDSUB213PSMasked128load, + ssa.OpAMD64VFMADDSUB213PSMasked256, + ssa.OpAMD64VFMADDSUB213PSMasked256load, + ssa.OpAMD64VFMADDSUB213PSMasked512, + ssa.OpAMD64VFMADDSUB213PSMasked512load, + ssa.OpAMD64VFMADDSUB213PDMasked128, + ssa.OpAMD64VFMADDSUB213PDMasked128load, + ssa.OpAMD64VFMADDSUB213PDMasked256, + ssa.OpAMD64VFMADDSUB213PDMasked256load, + ssa.OpAMD64VFMADDSUB213PDMasked512, + ssa.OpAMD64VFMADDSUB213PDMasked512load, + ssa.OpAMD64VFMADD213PSMasked128, + ssa.OpAMD64VFMADD213PSMasked128load, + ssa.OpAMD64VFMADD213PSMasked256, + ssa.OpAMD64VFMADD213PSMasked256load, + ssa.OpAMD64VFMADD213PSMasked512, + ssa.OpAMD64VFMADD213PSMasked512load, + ssa.OpAMD64VFMADD213PDMasked128, + ssa.OpAMD64VFMADD213PDMasked128load, + ssa.OpAMD64VFMADD213PDMasked256, + ssa.OpAMD64VFMADD213PDMasked256load, + ssa.OpAMD64VFMADD213PDMasked512, + ssa.OpAMD64VFMADD213PDMasked512load, + ssa.OpAMD64VFMSUBADD213PSMasked128, + ssa.OpAMD64VFMSUBADD213PSMasked128load, + ssa.OpAMD64VFMSUBADD213PSMasked256, + ssa.OpAMD64VFMSUBADD213PSMasked256load, + ssa.OpAMD64VFMSUBADD213PSMasked512, + ssa.OpAMD64VFMSUBADD213PSMasked512load, + ssa.OpAMD64VFMSUBADD213PDMasked128, + ssa.OpAMD64VFMSUBADD213PDMasked128load, + ssa.OpAMD64VFMSUBADD213PDMasked256, + ssa.OpAMD64VFMSUBADD213PDMasked256load, + ssa.OpAMD64VFMSUBADD213PDMasked512, + ssa.OpAMD64VFMSUBADD213PDMasked512load, + ssa.OpAMD64VPMULHWMasked128, + ssa.OpAMD64VPMULHWMasked128load, + ssa.OpAMD64VPMULHWMasked256, + ssa.OpAMD64VPMULHWMasked256load, + ssa.OpAMD64VPMULHWMasked512, + ssa.OpAMD64VPMULHUWMasked128, + ssa.OpAMD64VPMULHUWMasked128load, + ssa.OpAMD64VPMULHUWMasked256, + ssa.OpAMD64VPMULHUWMasked256load, + ssa.OpAMD64VPMULHUWMasked512, + ssa.OpAMD64VMULPSMasked128, + ssa.OpAMD64VMULPSMasked128load, + ssa.OpAMD64VMULPSMasked256, + ssa.OpAMD64VMULPSMasked256load, + ssa.OpAMD64VMULPSMasked512, + ssa.OpAMD64VMULPSMasked512load, + ssa.OpAMD64VMULPDMasked128, + ssa.OpAMD64VMULPDMasked128load, + ssa.OpAMD64VMULPDMasked256, + ssa.OpAMD64VMULPDMasked256load, + ssa.OpAMD64VMULPDMasked512, + ssa.OpAMD64VMULPDMasked512load, + ssa.OpAMD64VPMULLWMasked128, + ssa.OpAMD64VPMULLWMasked128load, + ssa.OpAMD64VPMULLWMasked256, + ssa.OpAMD64VPMULLWMasked256load, + ssa.OpAMD64VPMULLWMasked512, + ssa.OpAMD64VPMULLDMasked128, + ssa.OpAMD64VPMULLDMasked128load, + ssa.OpAMD64VPMULLDMasked256, + ssa.OpAMD64VPMULLDMasked256load, + ssa.OpAMD64VPMULLDMasked512, + ssa.OpAMD64VPMULLDMasked512load, + ssa.OpAMD64VPMULLQMasked128, + ssa.OpAMD64VPMULLQMasked128load, + ssa.OpAMD64VPMULLQMasked256, + ssa.OpAMD64VPMULLQMasked256load, + ssa.OpAMD64VPMULLQMasked512, + ssa.OpAMD64VPMULLQMasked512load, + ssa.OpAMD64VPOPCNTBMasked128, + ssa.OpAMD64VPOPCNTBMasked128load, + ssa.OpAMD64VPOPCNTBMasked256, + ssa.OpAMD64VPOPCNTBMasked256load, + ssa.OpAMD64VPOPCNTBMasked512, + ssa.OpAMD64VPOPCNTWMasked128, + ssa.OpAMD64VPOPCNTWMasked128load, + ssa.OpAMD64VPOPCNTWMasked256, + ssa.OpAMD64VPOPCNTWMasked256load, + ssa.OpAMD64VPOPCNTWMasked512, + ssa.OpAMD64VPOPCNTDMasked128, + ssa.OpAMD64VPOPCNTDMasked128load, + ssa.OpAMD64VPOPCNTDMasked256, + ssa.OpAMD64VPOPCNTDMasked256load, + ssa.OpAMD64VPOPCNTDMasked512, + ssa.OpAMD64VPOPCNTDMasked512load, + ssa.OpAMD64VPOPCNTQMasked128, + ssa.OpAMD64VPOPCNTQMasked128load, + ssa.OpAMD64VPOPCNTQMasked256, + ssa.OpAMD64VPOPCNTQMasked256load, + ssa.OpAMD64VPOPCNTQMasked512, + ssa.OpAMD64VPOPCNTQMasked512load, + ssa.OpAMD64VPORDMasked128, + ssa.OpAMD64VPORDMasked128load, + ssa.OpAMD64VPORDMasked256, + ssa.OpAMD64VPORDMasked256load, + ssa.OpAMD64VPORDMasked512, + ssa.OpAMD64VPORDMasked512load, + ssa.OpAMD64VPORQMasked128, + ssa.OpAMD64VPORQMasked128load, + ssa.OpAMD64VPORQMasked256, + ssa.OpAMD64VPORQMasked256load, + ssa.OpAMD64VPORQMasked512, + ssa.OpAMD64VPORQMasked512load, + ssa.OpAMD64VPERMBMasked128, + ssa.OpAMD64VPERMBMasked128load, + ssa.OpAMD64VPERMBMasked256, + ssa.OpAMD64VPERMBMasked256load, + ssa.OpAMD64VPERMBMasked512, + ssa.OpAMD64VPERMWMasked128, + ssa.OpAMD64VPERMWMasked128load, + ssa.OpAMD64VPERMWMasked256, + ssa.OpAMD64VPERMWMasked256load, + ssa.OpAMD64VPERMWMasked512, + ssa.OpAMD64VPERMPSMasked256, + ssa.OpAMD64VPERMPSMasked256load, + ssa.OpAMD64VPERMDMasked256, + ssa.OpAMD64VPERMDMasked256load, + ssa.OpAMD64VPERMPSMasked512, + ssa.OpAMD64VPERMPSMasked512load, + ssa.OpAMD64VPERMDMasked512, + ssa.OpAMD64VPERMDMasked512load, + ssa.OpAMD64VPERMPDMasked256, + ssa.OpAMD64VPERMPDMasked256load, + ssa.OpAMD64VPERMQMasked256, + ssa.OpAMD64VPERMQMasked256load, + ssa.OpAMD64VPERMPDMasked512, + ssa.OpAMD64VPERMPDMasked512load, + ssa.OpAMD64VPERMQMasked512, + ssa.OpAMD64VPERMQMasked512load, + ssa.OpAMD64VPSHUFBMasked256, + ssa.OpAMD64VPSHUFBMasked256load, + ssa.OpAMD64VPSHUFBMasked512, + ssa.OpAMD64VPSHUFBMasked128, + ssa.OpAMD64VPSHUFBMasked128load, + ssa.OpAMD64VRCP14PSMasked128, + ssa.OpAMD64VRCP14PSMasked128load, + ssa.OpAMD64VRCP14PSMasked256, + ssa.OpAMD64VRCP14PSMasked256load, + ssa.OpAMD64VRCP14PSMasked512, + ssa.OpAMD64VRCP14PSMasked512load, + ssa.OpAMD64VRCP14PDMasked128, + ssa.OpAMD64VRCP14PDMasked128load, + ssa.OpAMD64VRCP14PDMasked256, + ssa.OpAMD64VRCP14PDMasked256load, + ssa.OpAMD64VRCP14PDMasked512, + ssa.OpAMD64VRCP14PDMasked512load, + ssa.OpAMD64VRSQRT14PSMasked128, + ssa.OpAMD64VRSQRT14PSMasked128load, + ssa.OpAMD64VRSQRT14PSMasked256, + ssa.OpAMD64VRSQRT14PSMasked256load, + ssa.OpAMD64VRSQRT14PSMasked512, + ssa.OpAMD64VRSQRT14PSMasked512load, + ssa.OpAMD64VRSQRT14PDMasked128, + ssa.OpAMD64VRSQRT14PDMasked128load, + ssa.OpAMD64VRSQRT14PDMasked256, + ssa.OpAMD64VRSQRT14PDMasked256load, + ssa.OpAMD64VRSQRT14PDMasked512, + ssa.OpAMD64VRSQRT14PDMasked512load, + ssa.OpAMD64VPROLVDMasked128, + ssa.OpAMD64VPROLVDMasked128load, + ssa.OpAMD64VPROLVDMasked256, + ssa.OpAMD64VPROLVDMasked256load, + ssa.OpAMD64VPROLVDMasked512, + ssa.OpAMD64VPROLVDMasked512load, + ssa.OpAMD64VPROLVQMasked128, + ssa.OpAMD64VPROLVQMasked128load, + ssa.OpAMD64VPROLVQMasked256, + ssa.OpAMD64VPROLVQMasked256load, + ssa.OpAMD64VPROLVQMasked512, + ssa.OpAMD64VPROLVQMasked512load, + ssa.OpAMD64VPRORVDMasked128, + ssa.OpAMD64VPRORVDMasked128load, + ssa.OpAMD64VPRORVDMasked256, + ssa.OpAMD64VPRORVDMasked256load, + ssa.OpAMD64VPRORVDMasked512, + ssa.OpAMD64VPRORVDMasked512load, + ssa.OpAMD64VPRORVQMasked128, + ssa.OpAMD64VPRORVQMasked128load, + ssa.OpAMD64VPRORVQMasked256, + ssa.OpAMD64VPRORVQMasked256load, + ssa.OpAMD64VPRORVQMasked512, + ssa.OpAMD64VPRORVQMasked512load, + ssa.OpAMD64VPMOVSWBMasked128_128, + ssa.OpAMD64VPMOVSWBMasked128_256, + ssa.OpAMD64VPMOVSWBMasked256, + ssa.OpAMD64VPMOVSDBMasked128_128, + ssa.OpAMD64VPMOVSDBMasked128_256, + ssa.OpAMD64VPMOVSDBMasked128_512, + ssa.OpAMD64VPMOVSQBMasked128_128, + ssa.OpAMD64VPMOVSQBMasked128_256, + ssa.OpAMD64VPMOVSQBMasked128_512, + ssa.OpAMD64VPACKSSDWMasked256, + ssa.OpAMD64VPACKSSDWMasked256load, + ssa.OpAMD64VPACKSSDWMasked512, + ssa.OpAMD64VPACKSSDWMasked512load, + ssa.OpAMD64VPACKSSDWMasked128, + ssa.OpAMD64VPACKSSDWMasked128load, + ssa.OpAMD64VPMOVSDWMasked128_128, + ssa.OpAMD64VPMOVSDWMasked128_256, + ssa.OpAMD64VPMOVSDWMasked256, + ssa.OpAMD64VPMOVSQWMasked128_128, + ssa.OpAMD64VPMOVSQWMasked128_256, + ssa.OpAMD64VPMOVSQWMasked128_512, + ssa.OpAMD64VPMOVSQDMasked128_128, + ssa.OpAMD64VPMOVSQDMasked128_256, + ssa.OpAMD64VPMOVSQDMasked256, + ssa.OpAMD64VPMOVUSWBMasked128_128, + ssa.OpAMD64VPMOVUSWBMasked128_256, + ssa.OpAMD64VPMOVUSWBMasked256, + ssa.OpAMD64VPMOVUSDBMasked128_128, + ssa.OpAMD64VPMOVUSDBMasked128_256, + ssa.OpAMD64VPMOVUSDBMasked128_512, + ssa.OpAMD64VPMOVUSQBMasked128_128, + ssa.OpAMD64VPMOVUSQBMasked128_256, + ssa.OpAMD64VPMOVUSQBMasked128_512, + ssa.OpAMD64VPACKUSDWMasked256, + ssa.OpAMD64VPACKUSDWMasked256load, + ssa.OpAMD64VPACKUSDWMasked512, + ssa.OpAMD64VPACKUSDWMasked512load, + ssa.OpAMD64VPACKUSDWMasked128, + ssa.OpAMD64VPACKUSDWMasked128load, + ssa.OpAMD64VPMOVUSDWMasked128_128, + ssa.OpAMD64VPMOVUSDWMasked128_256, + ssa.OpAMD64VPMOVUSDWMasked256, + ssa.OpAMD64VPMOVUSQWMasked128_128, + ssa.OpAMD64VPMOVUSQWMasked128_256, + ssa.OpAMD64VPMOVUSQWMasked128_512, + ssa.OpAMD64VPMOVUSQDMasked128_128, + ssa.OpAMD64VPMOVUSQDMasked128_256, + ssa.OpAMD64VPMOVUSQDMasked256, + ssa.OpAMD64VSCALEFPSMasked128, + ssa.OpAMD64VSCALEFPSMasked128load, + ssa.OpAMD64VSCALEFPSMasked256, + ssa.OpAMD64VSCALEFPSMasked256load, + ssa.OpAMD64VSCALEFPSMasked512, + ssa.OpAMD64VSCALEFPSMasked512load, + ssa.OpAMD64VSCALEFPDMasked128, + ssa.OpAMD64VSCALEFPDMasked128load, + ssa.OpAMD64VSCALEFPDMasked256, + ssa.OpAMD64VSCALEFPDMasked256load, + ssa.OpAMD64VSCALEFPDMasked512, + ssa.OpAMD64VSCALEFPDMasked512load, + ssa.OpAMD64VPSHLDWMasked128, + ssa.OpAMD64VPSHLDWMasked128load, + ssa.OpAMD64VPSHLDWMasked256, + ssa.OpAMD64VPSHLDWMasked256load, + ssa.OpAMD64VPSHLDWMasked512, + ssa.OpAMD64VPSHLDDMasked128, + ssa.OpAMD64VPSHLDDMasked128load, + ssa.OpAMD64VPSHLDDMasked256, + ssa.OpAMD64VPSHLDDMasked256load, + ssa.OpAMD64VPSHLDDMasked512, + ssa.OpAMD64VPSHLDDMasked512load, + ssa.OpAMD64VPSHLDQMasked128, + ssa.OpAMD64VPSHLDQMasked128load, + ssa.OpAMD64VPSHLDQMasked256, + ssa.OpAMD64VPSHLDQMasked256load, + ssa.OpAMD64VPSHLDQMasked512, + ssa.OpAMD64VPSHLDQMasked512load, + ssa.OpAMD64VPSLLWMasked128, + ssa.OpAMD64VPSLLWMasked256, + ssa.OpAMD64VPSLLWMasked512, + ssa.OpAMD64VPSLLDMasked128, + ssa.OpAMD64VPSLLDMasked256, + ssa.OpAMD64VPSLLDMasked512, + ssa.OpAMD64VPSLLQMasked128, + ssa.OpAMD64VPSLLQMasked256, + ssa.OpAMD64VPSLLQMasked512, + ssa.OpAMD64VPSHRDWMasked128, + ssa.OpAMD64VPSHRDWMasked128load, + ssa.OpAMD64VPSHRDWMasked256, + ssa.OpAMD64VPSHRDWMasked256load, + ssa.OpAMD64VPSHRDWMasked512, + ssa.OpAMD64VPSHRDDMasked128, + ssa.OpAMD64VPSHRDDMasked128load, + ssa.OpAMD64VPSHRDDMasked256, + ssa.OpAMD64VPSHRDDMasked256load, + ssa.OpAMD64VPSHRDDMasked512, + ssa.OpAMD64VPSHRDDMasked512load, + ssa.OpAMD64VPSHRDQMasked128, + ssa.OpAMD64VPSHRDQMasked128load, + ssa.OpAMD64VPSHRDQMasked256, + ssa.OpAMD64VPSHRDQMasked256load, + ssa.OpAMD64VPSHRDQMasked512, + ssa.OpAMD64VPSHRDQMasked512load, + ssa.OpAMD64VPSRAWMasked128, + ssa.OpAMD64VPSRAWMasked256, + ssa.OpAMD64VPSRAWMasked512, + ssa.OpAMD64VPSRADMasked128, + ssa.OpAMD64VPSRADMasked256, + ssa.OpAMD64VPSRADMasked512, + ssa.OpAMD64VPSRAQMasked128, + ssa.OpAMD64VPSRAQMasked256, + ssa.OpAMD64VPSRAQMasked512, + ssa.OpAMD64VPSRLWMasked128, + ssa.OpAMD64VPSRLWMasked256, + ssa.OpAMD64VPSRLWMasked512, + ssa.OpAMD64VPSRLDMasked128, + ssa.OpAMD64VPSRLDMasked256, + ssa.OpAMD64VPSRLDMasked512, + ssa.OpAMD64VPSRLQMasked128, + ssa.OpAMD64VPSRLQMasked256, + ssa.OpAMD64VPSRLQMasked512, + ssa.OpAMD64VPSHLDVWMasked128, + ssa.OpAMD64VPSHLDVWMasked128load, + ssa.OpAMD64VPSHLDVWMasked256, + ssa.OpAMD64VPSHLDVWMasked256load, + ssa.OpAMD64VPSHLDVWMasked512, + ssa.OpAMD64VPSHLDVDMasked128, + ssa.OpAMD64VPSHLDVDMasked128load, + ssa.OpAMD64VPSHLDVDMasked256, + ssa.OpAMD64VPSHLDVDMasked256load, + ssa.OpAMD64VPSHLDVDMasked512, + ssa.OpAMD64VPSHLDVDMasked512load, + ssa.OpAMD64VPSHLDVQMasked128, + ssa.OpAMD64VPSHLDVQMasked128load, + ssa.OpAMD64VPSHLDVQMasked256, + ssa.OpAMD64VPSHLDVQMasked256load, + ssa.OpAMD64VPSHLDVQMasked512, + ssa.OpAMD64VPSHLDVQMasked512load, + ssa.OpAMD64VPSLLVWMasked128, + ssa.OpAMD64VPSLLVWMasked128load, + ssa.OpAMD64VPSLLVWMasked256, + ssa.OpAMD64VPSLLVWMasked256load, + ssa.OpAMD64VPSLLVWMasked512, + ssa.OpAMD64VPSLLVDMasked128, + ssa.OpAMD64VPSLLVDMasked128load, + ssa.OpAMD64VPSLLVDMasked256, + ssa.OpAMD64VPSLLVDMasked256load, + ssa.OpAMD64VPSLLVDMasked512, + ssa.OpAMD64VPSLLVDMasked512load, + ssa.OpAMD64VPSLLVQMasked128, + ssa.OpAMD64VPSLLVQMasked128load, + ssa.OpAMD64VPSLLVQMasked256, + ssa.OpAMD64VPSLLVQMasked256load, + ssa.OpAMD64VPSLLVQMasked512, + ssa.OpAMD64VPSLLVQMasked512load, + ssa.OpAMD64VPSHRDVWMasked128, + ssa.OpAMD64VPSHRDVWMasked128load, + ssa.OpAMD64VPSHRDVWMasked256, + ssa.OpAMD64VPSHRDVWMasked256load, + ssa.OpAMD64VPSHRDVWMasked512, + ssa.OpAMD64VPSHRDVDMasked128, + ssa.OpAMD64VPSHRDVDMasked128load, + ssa.OpAMD64VPSHRDVDMasked256, + ssa.OpAMD64VPSHRDVDMasked256load, + ssa.OpAMD64VPSHRDVDMasked512, + ssa.OpAMD64VPSHRDVDMasked512load, + ssa.OpAMD64VPSHRDVQMasked128, + ssa.OpAMD64VPSHRDVQMasked128load, + ssa.OpAMD64VPSHRDVQMasked256, + ssa.OpAMD64VPSHRDVQMasked256load, + ssa.OpAMD64VPSHRDVQMasked512, + ssa.OpAMD64VPSHRDVQMasked512load, + ssa.OpAMD64VPSRAVWMasked128, + ssa.OpAMD64VPSRAVWMasked128load, + ssa.OpAMD64VPSRAVWMasked256, + ssa.OpAMD64VPSRAVWMasked256load, + ssa.OpAMD64VPSRAVWMasked512, + ssa.OpAMD64VPSRAVDMasked128, + ssa.OpAMD64VPSRAVDMasked128load, + ssa.OpAMD64VPSRAVDMasked256, + ssa.OpAMD64VPSRAVDMasked256load, + ssa.OpAMD64VPSRAVDMasked512, + ssa.OpAMD64VPSRAVDMasked512load, + ssa.OpAMD64VPSRAVQMasked128, + ssa.OpAMD64VPSRAVQMasked128load, + ssa.OpAMD64VPSRAVQMasked256, + ssa.OpAMD64VPSRAVQMasked256load, + ssa.OpAMD64VPSRAVQMasked512, + ssa.OpAMD64VPSRAVQMasked512load, + ssa.OpAMD64VPSRLVWMasked128, + ssa.OpAMD64VPSRLVWMasked128load, + ssa.OpAMD64VPSRLVWMasked256, + ssa.OpAMD64VPSRLVWMasked256load, + ssa.OpAMD64VPSRLVWMasked512, + ssa.OpAMD64VPSRLVDMasked128, + ssa.OpAMD64VPSRLVDMasked128load, + ssa.OpAMD64VPSRLVDMasked256, + ssa.OpAMD64VPSRLVDMasked256load, + ssa.OpAMD64VPSRLVDMasked512, + ssa.OpAMD64VPSRLVDMasked512load, + ssa.OpAMD64VPSRLVQMasked128, + ssa.OpAMD64VPSRLVQMasked128load, + ssa.OpAMD64VPSRLVQMasked256, + ssa.OpAMD64VPSRLVQMasked256load, + ssa.OpAMD64VPSRLVQMasked512, + ssa.OpAMD64VPSRLVQMasked512load, + ssa.OpAMD64VSQRTPSMasked128, + ssa.OpAMD64VSQRTPSMasked128load, + ssa.OpAMD64VSQRTPSMasked256, + ssa.OpAMD64VSQRTPSMasked256load, + ssa.OpAMD64VSQRTPSMasked512, + ssa.OpAMD64VSQRTPSMasked512load, + ssa.OpAMD64VSQRTPDMasked128, + ssa.OpAMD64VSQRTPDMasked128load, + ssa.OpAMD64VSQRTPDMasked256, + ssa.OpAMD64VSQRTPDMasked256load, + ssa.OpAMD64VSQRTPDMasked512, + ssa.OpAMD64VSQRTPDMasked512load, + ssa.OpAMD64VSUBPSMasked128, + ssa.OpAMD64VSUBPSMasked128load, + ssa.OpAMD64VSUBPSMasked256, + ssa.OpAMD64VSUBPSMasked256load, + ssa.OpAMD64VSUBPSMasked512, + ssa.OpAMD64VSUBPSMasked512load, + ssa.OpAMD64VSUBPDMasked128, + ssa.OpAMD64VSUBPDMasked128load, + ssa.OpAMD64VSUBPDMasked256, + ssa.OpAMD64VSUBPDMasked256load, + ssa.OpAMD64VSUBPDMasked512, + ssa.OpAMD64VSUBPDMasked512load, + ssa.OpAMD64VPSUBBMasked128, + ssa.OpAMD64VPSUBBMasked128load, + ssa.OpAMD64VPSUBBMasked256, + ssa.OpAMD64VPSUBBMasked256load, + ssa.OpAMD64VPSUBBMasked512, + ssa.OpAMD64VPSUBWMasked128, + ssa.OpAMD64VPSUBWMasked128load, + ssa.OpAMD64VPSUBWMasked256, + ssa.OpAMD64VPSUBWMasked256load, + ssa.OpAMD64VPSUBWMasked512, + ssa.OpAMD64VPSUBDMasked128, + ssa.OpAMD64VPSUBDMasked128load, + ssa.OpAMD64VPSUBDMasked256, + ssa.OpAMD64VPSUBDMasked256load, + ssa.OpAMD64VPSUBDMasked512, + ssa.OpAMD64VPSUBDMasked512load, + ssa.OpAMD64VPSUBQMasked128, + ssa.OpAMD64VPSUBQMasked128load, + ssa.OpAMD64VPSUBQMasked256, + ssa.OpAMD64VPSUBQMasked256load, + ssa.OpAMD64VPSUBQMasked512, + ssa.OpAMD64VPSUBQMasked512load, + ssa.OpAMD64VPSUBSBMasked128, + ssa.OpAMD64VPSUBSBMasked128load, + ssa.OpAMD64VPSUBSBMasked256, + ssa.OpAMD64VPSUBSBMasked256load, + ssa.OpAMD64VPSUBSBMasked512, + ssa.OpAMD64VPSUBSWMasked128, + ssa.OpAMD64VPSUBSWMasked128load, + ssa.OpAMD64VPSUBSWMasked256, + ssa.OpAMD64VPSUBSWMasked256load, + ssa.OpAMD64VPSUBSWMasked512, + ssa.OpAMD64VPSUBUSBMasked128, + ssa.OpAMD64VPSUBUSBMasked128load, + ssa.OpAMD64VPSUBUSBMasked256, + ssa.OpAMD64VPSUBUSBMasked256load, + ssa.OpAMD64VPSUBUSBMasked512, + ssa.OpAMD64VPSUBUSWMasked128, + ssa.OpAMD64VPSUBUSWMasked128load, + ssa.OpAMD64VPSUBUSWMasked256, + ssa.OpAMD64VPSUBUSWMasked256load, + ssa.OpAMD64VPSUBUSWMasked512, + ssa.OpAMD64VPMOVWBMasked128_128, + ssa.OpAMD64VPMOVWBMasked128_256, + ssa.OpAMD64VPMOVWBMasked256, + ssa.OpAMD64VPMOVDBMasked128_128, + ssa.OpAMD64VPMOVDBMasked128_256, + ssa.OpAMD64VPMOVDBMasked128_512, + ssa.OpAMD64VPMOVQBMasked128_128, + ssa.OpAMD64VPMOVQBMasked128_256, + ssa.OpAMD64VPMOVQBMasked128_512, + ssa.OpAMD64VPMOVDWMasked128_128, + ssa.OpAMD64VPMOVDWMasked128_256, + ssa.OpAMD64VPMOVDWMasked256, + ssa.OpAMD64VPMOVQWMasked128_128, + ssa.OpAMD64VPMOVQWMasked128_256, + ssa.OpAMD64VPMOVQWMasked128_512, + ssa.OpAMD64VPMOVQDMasked128_128, + ssa.OpAMD64VPMOVQDMasked128_256, + ssa.OpAMD64VPMOVQDMasked256, + ssa.OpAMD64VPXORDMasked128, + ssa.OpAMD64VPXORDMasked128load, + ssa.OpAMD64VPXORDMasked256, + ssa.OpAMD64VPXORDMasked256load, + ssa.OpAMD64VPXORDMasked512, + ssa.OpAMD64VPXORDMasked512load, + ssa.OpAMD64VPXORQMasked128, + ssa.OpAMD64VPXORQMasked128load, + ssa.OpAMD64VPXORQMasked256, + ssa.OpAMD64VPXORQMasked256load, + ssa.OpAMD64VPXORQMasked512, + ssa.OpAMD64VPXORQMasked512load, + ssa.OpAMD64VPBROADCASTQMasked128, + ssa.OpAMD64VPBROADCASTQMasked128load, + ssa.OpAMD64VBROADCASTSSMasked128, + ssa.OpAMD64VBROADCASTSSMasked128load, + ssa.OpAMD64VBROADCASTSDMasked256, + ssa.OpAMD64VBROADCASTSDMasked256load, + ssa.OpAMD64VPBROADCASTDMasked128, + ssa.OpAMD64VPBROADCASTDMasked128load, + ssa.OpAMD64VPBROADCASTQMasked256, + ssa.OpAMD64VPBROADCASTQMasked256load, + ssa.OpAMD64VBROADCASTSSMasked256, + ssa.OpAMD64VBROADCASTSSMasked256load, + ssa.OpAMD64VBROADCASTSDMasked512, + ssa.OpAMD64VBROADCASTSDMasked512load, + ssa.OpAMD64VPBROADCASTWMasked128, + ssa.OpAMD64VPBROADCASTDMasked256, + ssa.OpAMD64VPBROADCASTDMasked256load, + ssa.OpAMD64VPBROADCASTQMasked512, + ssa.OpAMD64VPBROADCASTQMasked512load, + ssa.OpAMD64VBROADCASTSSMasked512, + ssa.OpAMD64VBROADCASTSSMasked512load, + ssa.OpAMD64VPBROADCASTBMasked128, + ssa.OpAMD64VPBROADCASTBMasked128load, + ssa.OpAMD64VPBROADCASTWMasked256, + ssa.OpAMD64VPBROADCASTDMasked512, + ssa.OpAMD64VPBROADCASTDMasked512load, + ssa.OpAMD64VPBROADCASTBMasked256, + ssa.OpAMD64VPBROADCASTBMasked256load, + ssa.OpAMD64VPBROADCASTWMasked512, + ssa.OpAMD64VPBROADCASTBMasked512, + ssa.OpAMD64VPBROADCASTBMasked512load, + ssa.OpAMD64VMOVDQU8Masked128, + ssa.OpAMD64VMOVDQU8Masked256, + ssa.OpAMD64VMOVDQU8Masked512, + ssa.OpAMD64VMOVDQU16Masked128, + ssa.OpAMD64VMOVDQU16Masked256, + ssa.OpAMD64VMOVDQU16Masked512, + ssa.OpAMD64VMOVDQU32Masked128, + ssa.OpAMD64VMOVDQU32Masked256, + ssa.OpAMD64VMOVDQU32Masked512, + ssa.OpAMD64VMOVDQU64Masked128, + ssa.OpAMD64VMOVDQU64Masked256, + ssa.OpAMD64VMOVDQU64Masked512, + ssa.OpAMD64VPSHUFDMasked256, + ssa.OpAMD64VPSHUFDMasked256load, + ssa.OpAMD64VPSHUFDMasked512, + ssa.OpAMD64VPSHUFDMasked512load, + ssa.OpAMD64VPSHUFHWMasked256, + ssa.OpAMD64VPSHUFHWMasked256load, + ssa.OpAMD64VPSHUFHWMasked512, + ssa.OpAMD64VPSHUFHWMasked128, + ssa.OpAMD64VPSHUFHWMasked128load, + ssa.OpAMD64VPSHUFLWMasked256, + ssa.OpAMD64VPSHUFLWMasked256load, + ssa.OpAMD64VPSHUFLWMasked512, + ssa.OpAMD64VPSHUFLWMasked128, + ssa.OpAMD64VPSHUFLWMasked128load, + ssa.OpAMD64VPSHUFDMasked128, + ssa.OpAMD64VPSHUFDMasked128load, + ssa.OpAMD64VPROLDMasked128, + ssa.OpAMD64VPROLDMasked128load, + ssa.OpAMD64VPROLDMasked256, + ssa.OpAMD64VPROLDMasked256load, + ssa.OpAMD64VPROLDMasked512, + ssa.OpAMD64VPROLDMasked512load, + ssa.OpAMD64VPROLQMasked128, + ssa.OpAMD64VPROLQMasked128load, + ssa.OpAMD64VPROLQMasked256, + ssa.OpAMD64VPROLQMasked256load, + ssa.OpAMD64VPROLQMasked512, + ssa.OpAMD64VPROLQMasked512load, + ssa.OpAMD64VPRORDMasked128, + ssa.OpAMD64VPRORDMasked128load, + ssa.OpAMD64VPRORDMasked256, + ssa.OpAMD64VPRORDMasked256load, + ssa.OpAMD64VPRORDMasked512, + ssa.OpAMD64VPRORDMasked512load, + ssa.OpAMD64VPRORQMasked128, + ssa.OpAMD64VPRORQMasked128load, + ssa.OpAMD64VPRORQMasked256, + ssa.OpAMD64VPRORQMasked256load, + ssa.OpAMD64VPRORQMasked512, + ssa.OpAMD64VPRORQMasked512load, + ssa.OpAMD64VPSLLWMasked128const, + ssa.OpAMD64VPSLLWMasked128constload, + ssa.OpAMD64VPSLLWMasked256const, + ssa.OpAMD64VPSLLWMasked256constload, + ssa.OpAMD64VPSLLWMasked512const, + ssa.OpAMD64VPSLLDMasked128const, + ssa.OpAMD64VPSLLDMasked128constload, + ssa.OpAMD64VPSLLDMasked256const, + ssa.OpAMD64VPSLLDMasked256constload, + ssa.OpAMD64VPSLLDMasked512const, + ssa.OpAMD64VPSLLDMasked512constload, + ssa.OpAMD64VPSLLQMasked128const, + ssa.OpAMD64VPSLLQMasked128constload, + ssa.OpAMD64VPSLLQMasked256const, + ssa.OpAMD64VPSLLQMasked256constload, + ssa.OpAMD64VPSLLQMasked512const, + ssa.OpAMD64VPSLLQMasked512constload, + ssa.OpAMD64VPSRAWMasked128const, + ssa.OpAMD64VPSRAWMasked128constload, + ssa.OpAMD64VPSRAWMasked256const, + ssa.OpAMD64VPSRAWMasked256constload, + ssa.OpAMD64VPSRAWMasked512const, + ssa.OpAMD64VPSRADMasked128const, + ssa.OpAMD64VPSRADMasked128constload, + ssa.OpAMD64VPSRADMasked256const, + ssa.OpAMD64VPSRADMasked256constload, + ssa.OpAMD64VPSRADMasked512const, + ssa.OpAMD64VPSRADMasked512constload, + ssa.OpAMD64VPSRAQMasked128const, + ssa.OpAMD64VPSRAQMasked128constload, + ssa.OpAMD64VPSRAQMasked256const, + ssa.OpAMD64VPSRAQMasked256constload, + ssa.OpAMD64VPSRAQMasked512const, + ssa.OpAMD64VPSRAQMasked512constload, + ssa.OpAMD64VPSRLWMasked128const, + ssa.OpAMD64VPSRLWMasked128constload, + ssa.OpAMD64VPSRLWMasked256const, + ssa.OpAMD64VPSRLWMasked256constload, + ssa.OpAMD64VPSRLWMasked512const, + ssa.OpAMD64VPSRLDMasked128const, + ssa.OpAMD64VPSRLDMasked128constload, + ssa.OpAMD64VPSRLDMasked256const, + ssa.OpAMD64VPSRLDMasked256constload, + ssa.OpAMD64VPSRLDMasked512const, + ssa.OpAMD64VPSRLDMasked512constload, + ssa.OpAMD64VPSRLQMasked128const, + ssa.OpAMD64VPSRLQMasked128constload, + ssa.OpAMD64VPSRLQMasked256const, + ssa.OpAMD64VPSRLQMasked256constload, + ssa.OpAMD64VPSRLQMasked512const, + ssa.OpAMD64VPSRLQMasked512constload: + x86.ParseSuffix(p, "Z") + } + + // Ensure p is marked as used (may not be used in all generated code paths) + _ = p + return true +} diff --git a/src/cmd/compile/internal/amd64/ssa.go b/src/cmd/compile/internal/amd64/ssa.go index 6331501dc92fdb..cd5a2be7057c59 100644 --- a/src/cmd/compile/internal/amd64/ssa.go +++ b/src/cmd/compile/internal/amd64/ssa.go @@ -43,11 +43,31 @@ func ssaMarkMoves(s *ssagen.State, b *ssa.Block) { } } -// loadByType returns the load instruction of the given type. -func loadByType(t *types.Type) obj.As { - // Avoid partial register write - if !t.IsFloat() { - switch t.Size() { +func isGPReg(r int16) bool { + return x86.REG_AL <= r && r <= x86.REG_R15 +} + +func isFPReg(r int16) bool { + return x86.REG_X0 <= r && r <= x86.REG_Z31 +} + +func isKReg(r int16) bool { + return x86.REG_K0 <= r && r <= x86.REG_K7 +} + +func isLowFPReg(r int16) bool { + return x86.REG_X0 <= r && r <= x86.REG_X15 +} + +func isHighFPReg(r int16) bool { + return x86.REG_X16 <= r && r <= x86.REG_X31 || x86.REG_Y16 <= r && r <= x86.REG_Y31 || x86.REG_Z16 <= r && r <= x86.REG_Z31 +} + +// loadByRegWidth returns the load instruction of the given register of a given width. +func loadByRegWidth(r int16, width int64) obj.As { + // Avoid partial register write for GPR + if !isFPReg(r) && !isKReg(r) { + switch width { case 1: return x86.AMOVBLZX case 2: @@ -55,61 +75,95 @@ func loadByType(t *types.Type) obj.As { } } // Otherwise, there's no difference between load and store opcodes. - return storeByType(t) + return storeByRegWidth(r, width) } -// storeByType returns the store instruction of the given type. -func storeByType(t *types.Type) obj.As { - width := t.Size() - if t.IsFloat() { +// storeByRegWidth returns the store instruction of the given register of a given width. +// It's also used for loading const to a reg. +func storeByRegWidth(r int16, width int64) obj.As { + if isHighFPReg(r) { + // High registers require AVX512 instruction + return x86.AVMOVDQU64 + } + if isFPReg(r) { switch width { case 4: return x86.AMOVSS case 8: return x86.AMOVSD - } - } else { - switch width { - case 1: - return x86.AMOVB - case 2: - return x86.AMOVW - case 4: - return x86.AMOVL - case 8: - return x86.AMOVQ case 16: + // int128s are in SSE registers return x86.AMOVUPS + case 32: + return x86.AVMOVDQU + case 64: + return x86.AVMOVDQU64 } } - panic(fmt.Sprintf("bad store type %v", t)) + if isKReg(r) { + return x86.AKMOVQ + } + // gp + switch width { + case 1: + return x86.AMOVB + case 2: + return x86.AMOVW + case 4: + return x86.AMOVL + case 8: + return x86.AMOVQ + } + panic(fmt.Sprintf("bad store reg=%v, width=%d", r, width)) } -// moveByType returns the reg->reg move instruction of the given type. -func moveByType(t *types.Type) obj.As { - if t.IsFloat() { +// moveByRegsWidth returns the reg->reg move instruction of the given dest/src registers of a given width. +func moveByRegsWidth(dest, src int16, width int64) obj.As { + // fp -> fp + if isFPReg(dest) && isFPReg(src) { + if isHighFPReg(src) || isHighFPReg(dest) { + // High registers require AVX512 instruction + return x86.AVMOVDQU64 + } // Moving the whole sse2 register is faster // than moving just the correct low portion of it. // There is no xmm->xmm move with 1 byte opcode, // so use movups, which has 2 byte opcode. - return x86.AMOVUPS - } else { - switch t.Size() { - case 1: - // Avoids partial register write - return x86.AMOVL - case 2: - return x86.AMOVL - case 4: - return x86.AMOVL - case 8: - return x86.AMOVQ - case 16: - return x86.AMOVUPS // int128s are in SSE registers - default: - panic(fmt.Sprintf("bad int register width %d:%v", t.Size(), t)) + if width <= 16 { + return x86.AMOVUPS + } + if width <= 32 { + return x86.AVMOVDQU + } + return x86.AVMOVDQU64 + } + // k -> gp, gp -> k, k -> k + if isKReg(dest) || isKReg(src) { + if isFPReg(dest) || isFPReg(src) { + panic(fmt.Sprintf("bad move, src=%v, dest=%v, width=%d", src, dest, width)) } + return x86.AKMOVQ } + // gp -> fp, fp -> gp, gp -> gp + switch width { + case 1: + // Avoids partial register write + return x86.AMOVL + case 2: + return x86.AMOVL + case 4: + return x86.AMOVL + case 8: + return x86.AMOVQ + case 16: + // int128s are in SSE registers + return x86.AMOVUPS + case 32: + return x86.AVMOVDQU + case 64: + return x86.AVMOVDQU64 + } + panic(fmt.Sprintf("bad move, src=%v, dest=%v, width=%d", src, dest, width)) } // opregreg emits instructions for @@ -259,15 +313,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Reg = v.Reg() p.From.Reg = x86.REG_X15 - case ssa.OpAMD64SHRDQ, ssa.OpAMD64SHLDQ: - p := s.Prog(v.Op.Asm()) - lo, hi, bits := v.Args[0].Reg(), v.Args[1].Reg(), v.Args[2].Reg() - p.From.Type = obj.TYPE_REG - p.From.Reg = bits - p.To.Type = obj.TYPE_REG - p.To.Reg = lo - p.AddRestSourceReg(hi) - case ssa.OpAMD64BLSIQ, ssa.OpAMD64BLSIL, ssa.OpAMD64BLSMSKQ, ssa.OpAMD64BLSMSKL, ssa.OpAMD64BLSRQ, ssa.OpAMD64BLSRL: @@ -605,7 +650,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { // But this requires a way for regalloc to know that SRC might be // clobbered by this instruction. t := v.RegTmp() - opregreg(s, moveByType(v.Type), t, v.Args[1].Reg()) + opregreg(s, moveByRegsWidth(t, v.Args[1].Reg(), v.Type.Size()), t, v.Args[1].Reg()) p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REG @@ -650,11 +695,33 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { case ssa.OpAMD64SUBQconst, ssa.OpAMD64SUBLconst, ssa.OpAMD64ANDLconst, ssa.OpAMD64ORQconst, ssa.OpAMD64ORLconst, - ssa.OpAMD64XORQconst, ssa.OpAMD64XORLconst, - ssa.OpAMD64SHLQconst, ssa.OpAMD64SHLLconst, + ssa.OpAMD64XORQconst, ssa.OpAMD64XORLconst: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = v.AuxInt + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() + + case ssa.OpAMD64SHLQconst, ssa.OpAMD64SHLLconst, ssa.OpAMD64SHRQconst, ssa.OpAMD64SHRLconst, ssa.OpAMD64SHRWconst, ssa.OpAMD64SHRBconst, ssa.OpAMD64SARQconst, ssa.OpAMD64SARLconst, ssa.OpAMD64SARWconst, ssa.OpAMD64SARBconst, ssa.OpAMD64ROLQconst, ssa.OpAMD64ROLLconst, ssa.OpAMD64ROLWconst, ssa.OpAMD64ROLBconst: + var maxShift int64 + switch v.Op { + case ssa.OpAMD64SHLQconst, ssa.OpAMD64SHRQconst, ssa.OpAMD64SARQconst, ssa.OpAMD64ROLQconst: + maxShift = 63 + case ssa.OpAMD64SHLLconst, ssa.OpAMD64SHRLconst, ssa.OpAMD64SARLconst, ssa.OpAMD64ROLLconst: + maxShift = 31 + case ssa.OpAMD64SHRWconst, ssa.OpAMD64SARWconst, ssa.OpAMD64ROLWconst: + maxShift = 15 + case ssa.OpAMD64SHRBconst, ssa.OpAMD64SARBconst, ssa.OpAMD64ROLBconst: + maxShift = 7 + default: + panic("unreachable") + } + if v.AuxInt < 0 || v.AuxInt > maxShift { + v.Fatalf("shift amount out of range [0,%d]: %d", maxShift, v.AuxInt) + } p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_CONST p.From.Offset = v.AuxInt @@ -777,9 +844,14 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.From.Offset = v.AuxInt p.To.Type = obj.TYPE_REG p.To.Reg = x + case ssa.OpAMD64MOVSSconst, ssa.OpAMD64MOVSDconst: x := v.Reg() - p := s.Prog(v.Op.Asm()) + if !isFPReg(x) && v.AuxInt == 0 && v.Aux == nil { + opregreg(s, x86.AXORL, x, x) + break + } + p := s.Prog(storeByRegWidth(x, v.Type.Size())) p.From.Type = obj.TYPE_FCONST p.From.Val = math.Float64frombits(uint64(v.AuxInt)) p.To.Type = obj.TYPE_REG @@ -1174,29 +1246,50 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { if v.Type.IsMemory() { return } - x := v.Args[0].Reg() + arg := v.Args[0] + x := arg.Reg() y := v.Reg() + if v.Type.IsSIMD() { + x = simdOrMaskReg(arg) + y = simdOrMaskReg(v) + } if x != y { - opregreg(s, moveByType(v.Type), y, x) + width := v.Type.Size() + if width == 8 && isGPReg(y) && ssa.ZeroUpper32Bits(arg, 3) { + // The source was naturally zext-ed from 32 to 64 bits, + // but we are asked to do a full 64-bit copy. + // Save the REX prefix byte in I-CACHE by using a 32-bit move, + // since it zeroes the upper 32 bits anyway. + width = 4 + } + opregreg(s, moveByRegsWidth(y, x, width), y, x) } case ssa.OpLoadReg: if v.Type.IsFlags() { v.Fatalf("load flags not implemented: %v", v.LongString()) return } - p := s.Prog(loadByType(v.Type)) + r := v.Reg() + p := s.Prog(loadByRegWidth(r, v.Type.Size())) ssagen.AddrAuto(&p.From, v.Args[0]) p.To.Type = obj.TYPE_REG - p.To.Reg = v.Reg() + if v.Type.IsSIMD() { + r = simdOrMaskReg(v) + } + p.To.Reg = r case ssa.OpStoreReg: if v.Type.IsFlags() { v.Fatalf("store flags not implemented: %v", v.LongString()) return } - p := s.Prog(storeByType(v.Type)) + r := v.Args[0].Reg() + if v.Type.IsSIMD() { + r = simdOrMaskReg(v.Args[0]) + } + p := s.Prog(storeByRegWidth(r, v.Type.Size())) p.From.Type = obj.TYPE_REG - p.From.Reg = v.Args[0].Reg() + p.From.Reg = r ssagen.AddrAuto(&p.To, v) case ssa.OpAMD64LoweredHasCPUFeature: p := s.Prog(x86.AMOVBLZX) @@ -1210,8 +1303,14 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { for _, ap := range v.Block.Func.RegArgs { // Pass the spill/unspill information along to the assembler, offset by size of return PC pushed on stack. addr := ssagen.SpillSlotAddr(ap, x86.REG_SP, v.Block.Func.Config.PtrSize) + reg := ap.Reg + t := ap.Type + sz := t.Size() + if t.IsSIMD() { + reg = simdRegBySize(reg, sz) + } s.FuncInfo().AddSpill( - obj.RegSpill{Reg: ap.Reg, Addr: addr, Unspill: loadByType(ap.Type), Spill: storeByType(ap.Type)}) + obj.RegSpill{Reg: reg, Addr: addr, Unspill: loadByRegWidth(reg, sz), Spill: storeByRegWidth(reg, sz)}) } v.Block.Func.RegArgs = nil ssagen.CheckArgReg(v) @@ -1224,21 +1323,21 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { } r := v.Reg() getgFromTLS(s, r) - case ssa.OpAMD64CALLstatic, ssa.OpAMD64CALLtail: + case ssa.OpAMD64CALLstatic, ssa.OpAMD64CALLtail, ssa.OpAMD64CALLtailinter: if s.ABI == obj.ABI0 && v.Aux.(*ssa.AuxCall).Fn.ABI() == obj.ABIInternal { // zeroing X15 when entering ABIInternal from ABI0 - opregreg(s, x86.AXORPS, x86.REG_X15, x86.REG_X15) + zeroX15(s) // set G register from TLS getgFromTLS(s, x86.REG_R14) } - if v.Op == ssa.OpAMD64CALLtail { + if v.Op == ssa.OpAMD64CALLtail || v.Op == ssa.OpAMD64CALLtailinter { s.TailCall(v) break } s.Call(v) if s.ABI == obj.ABIInternal && v.Aux.(*ssa.AuxCall).Fn.ABI() == obj.ABI0 { // zeroing X15 when entering ABIInternal from ABI0 - opregreg(s, x86.AXORPS, x86.REG_X15, x86.REG_X15) + zeroX15(s) // set G register from TLS getgFromTLS(s, x86.REG_R14) } @@ -1409,7 +1508,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { } case ssa.OpAMD64LoweredRound32F, ssa.OpAMD64LoweredRound64F: // input is already rounded - case ssa.OpAMD64ROUNDSD: + case ssa.OpAMD64ROUNDSD, ssa.OpAMD64ROUNDSS: p := s.Prog(v.Op.Asm()) val := v.AuxInt // 0 means math.RoundToEven, 1 Floor, 2 Ceil, 3 Trunc @@ -1643,11 +1742,703 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.From.Offset = int64(x) p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg() + + // SIMD ops + case ssa.OpAMD64VZEROUPPER, ssa.OpAMD64VZEROALL: + s.Prog(v.Op.Asm()) + + case ssa.OpAMD64Zero128: // no code emitted + + case ssa.OpAMD64Zero256, ssa.OpAMD64Zero512: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v) + p.AddRestSourceReg(simdReg(v)) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + + case ssa.OpAMD64VMOVSSf2v, ssa.OpAMD64VMOVSDf2v: + // These are for initializing the least 32/64 bits of a SIMD register from a "float". + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = v.Args[0].Reg() + p.AddRestSourceReg(x86.REG_X15) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + + case ssa.OpAMD64VMOVQload, ssa.OpAMD64VMOVDload, + ssa.OpAMD64VMOVSSload, ssa.OpAMD64VMOVSDload: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.From, v) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + + case ssa.OpAMD64VMOVSSconst, ssa.OpAMD64VMOVSDconst: + // for loading constants directly into SIMD registers + x := simdReg(v) + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_FCONST + p.From.Val = math.Float64frombits(uint64(v.AuxInt)) + p.To.Type = obj.TYPE_REG + p.To.Reg = x + + case ssa.OpAMD64VMOVD, ssa.OpAMD64VMOVQ: + // These are for initializing the least 32/64 bits of a SIMD register from an "int". + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = v.Args[0].Reg() + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + + case ssa.OpAMD64VMOVDQUload128, ssa.OpAMD64VMOVDQUload256, ssa.OpAMD64VMOVDQUload512, + ssa.OpAMD64KMOVBload, ssa.OpAMD64KMOVWload, ssa.OpAMD64KMOVDload, ssa.OpAMD64KMOVQload: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.From, v) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdOrMaskReg(v) + case ssa.OpAMD64VMOVDQUstore128, ssa.OpAMD64VMOVDQUstore256, ssa.OpAMD64VMOVDQUstore512, + ssa.OpAMD64KMOVBstore, ssa.OpAMD64KMOVWstore, ssa.OpAMD64KMOVDstore, ssa.OpAMD64KMOVQstore: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdOrMaskReg(v.Args[1]) + p.To.Type = obj.TYPE_MEM + p.To.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.To, v) + + case ssa.OpAMD64VPMASK32load128, ssa.OpAMD64VPMASK64load128, ssa.OpAMD64VPMASK32load256, ssa.OpAMD64VPMASK64load256: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.From, v) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + p.AddRestSourceReg(simdReg(v.Args[1])) // masking simd reg + + case ssa.OpAMD64VPMASK32store128, ssa.OpAMD64VPMASK64store128, ssa.OpAMD64VPMASK32store256, ssa.OpAMD64VPMASK64store256: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[2]) + p.To.Type = obj.TYPE_MEM + p.To.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.To, v) + p.AddRestSourceReg(simdReg(v.Args[1])) // masking simd reg + + case ssa.OpAMD64VPMASK64load512, ssa.OpAMD64VPMASK32load512, ssa.OpAMD64VPMASK16load512, ssa.OpAMD64VPMASK8load512: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.From, v) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + p.AddRestSourceReg(v.Args[1].Reg()) // simd mask reg + x86.ParseSuffix(p, "Z") // must be zero if not in mask + + case ssa.OpAMD64KANDB, ssa.OpAMD64KANDW, ssa.OpAMD64KANDD, ssa.OpAMD64KANDQ, + ssa.OpAMD64KORB, ssa.OpAMD64KORW, ssa.OpAMD64KORD, ssa.OpAMD64KORQ, + ssa.OpAMD64KXORB, ssa.OpAMD64KXORW, ssa.OpAMD64KXORD, ssa.OpAMD64KXORQ, + ssa.OpAMD64KXNORB, ssa.OpAMD64KXNORW, ssa.OpAMD64KXNORD, ssa.OpAMD64KXNORQ: // XNOR == EQ + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = v.Args[0].Reg() + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() + p.AddRestSourceReg(v.Args[1].Reg()) // masking simd reg + + case ssa.OpAMD64VPMASK64store512, ssa.OpAMD64VPMASK32store512, ssa.OpAMD64VPMASK16store512, ssa.OpAMD64VPMASK8store512: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[2]) + p.To.Type = obj.TYPE_MEM + p.To.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.To, v) + p.AddRestSourceReg(v.Args[1].Reg()) // simd mask reg + + case ssa.OpAMD64VPMOVMToVec8x16, + ssa.OpAMD64VPMOVMToVec8x32, + ssa.OpAMD64VPMOVMToVec8x64, + ssa.OpAMD64VPMOVMToVec16x8, + ssa.OpAMD64VPMOVMToVec16x16, + ssa.OpAMD64VPMOVMToVec16x32, + ssa.OpAMD64VPMOVMToVec32x4, + ssa.OpAMD64VPMOVMToVec32x8, + ssa.OpAMD64VPMOVMToVec32x16, + ssa.OpAMD64VPMOVMToVec64x2, + ssa.OpAMD64VPMOVMToVec64x4, + ssa.OpAMD64VPMOVMToVec64x8: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = v.Args[0].Reg() + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + + case ssa.OpAMD64VPMOVVec8x16ToM, + ssa.OpAMD64VPMOVVec8x32ToM, + ssa.OpAMD64VPMOVVec8x64ToM, + ssa.OpAMD64VPMOVVec16x8ToM, + ssa.OpAMD64VPMOVVec16x16ToM, + ssa.OpAMD64VPMOVVec16x32ToM, + ssa.OpAMD64VPMOVVec32x4ToM, + ssa.OpAMD64VPMOVVec32x8ToM, + ssa.OpAMD64VPMOVVec32x16ToM, + ssa.OpAMD64VPMOVVec64x2ToM, + ssa.OpAMD64VPMOVVec64x4ToM, + ssa.OpAMD64VPMOVVec64x8ToM, + ssa.OpAMD64VPMOVMSKB128, + ssa.OpAMD64VPMOVMSKB256, + ssa.OpAMD64VMOVMSKPS128, + ssa.OpAMD64VMOVMSKPS256, + ssa.OpAMD64VMOVMSKPD128, + ssa.OpAMD64VMOVMSKPD256: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[0]) + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() + + case ssa.OpAMD64KMOVQk, ssa.OpAMD64KMOVDk, ssa.OpAMD64KMOVWk, ssa.OpAMD64KMOVBk, + ssa.OpAMD64KMOVQi, ssa.OpAMD64KMOVDi, ssa.OpAMD64KMOVWi, ssa.OpAMD64KMOVBi: + // See also ssa.OpAMD64KMOVQload + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = v.Args[0].Reg() + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() + case ssa.OpAMD64VPTEST: + // Some instructions setting flags put their second operand into the destination reg. + // See also CMP[BWDQ]. + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[0]) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v.Args[1]) + default: - v.Fatalf("genValue not implemented: %s", v.LongString()) + if !ssaGenSIMDValue(s, v) { + v.Fatalf("genValue not implemented: %s", v.LongString()) + } } } +// zeroX15 zeroes the X15 register. +func zeroX15(s *ssagen.State) { + opregreg(s, x86.AXORPS, x86.REG_X15, x86.REG_X15) +} + +// Example instruction: VRSQRTPS X1, X1 +func simdV11(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[0]) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPSUBD X1, X2, X3 +func simdV21(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + // Vector registers operands follows a right-to-left order. + // e.g. VPSUBD X1, X2, X3 means X3 = X2 - X1. + p.From.Reg = simdReg(v.Args[1]) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// This function is to accustomize the shifts. +// The 2nd arg is an XMM, and this function merely checks that. +// Example instruction: VPSLLQ Z1, X1, Z2 +func simdVfpv(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + // Vector registers operands follows a right-to-left order. + // e.g. VPSUBD X1, X2, X3 means X3 = X2 - X1. + p.From.Reg = v.Args[1].Reg() + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPCMPEQW Z26, Z30, K4 +func simdV2k(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[1]) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = maskReg(v) + return p +} + +// Example instruction: VPMINUQ X21, X3, K3, X31 +func simdV2kv(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[1]) + p.AddRestSourceReg(simdReg(v.Args[0])) + // These "simd*" series of functions assumes: + // Any "K" register that serves as the write-mask + // or "predicate" for "predicated AVX512 instructions" + // sits right at the end of the operand list. + // TODO: verify this assumption. + p.AddRestSourceReg(maskReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPABSB X1, X2, K3 (masking merging) +func simdV2kvResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[1]) + // These "simd*" series of functions assumes: + // Any "K" register that serves as the write-mask + // or "predicate" for "predicated AVX512 instructions" + // sits right at the end of the operand list. + // TODO: verify this assumption. + p.AddRestSourceReg(maskReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// This function is to accustomize the shifts. +// The 2nd arg is an XMM, and this function merely checks that. +// Example instruction: VPSLLQ Z1, X1, K1, Z2 +func simdVfpkv(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = v.Args[1].Reg() + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(maskReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPCMPEQW Z26, Z30, K1, K4 +func simdV2kk(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[1]) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(maskReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = maskReg(v) + return p +} + +// Example instruction: VPOPCNTB X14, K4, X16 +func simdVkv(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[0]) + p.AddRestSourceReg(maskReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VROUNDPD $7, X2, X2 +func simdV11Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Offset = int64(v.AuxUInt8()) + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VREDUCEPD $126, X1, K3, X31 +func simdVkvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Offset = int64(v.AuxUInt8()) + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(maskReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VCMPPS $7, X2, X9, X2 +func simdV21Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Offset = int64(v.AuxUInt8()) + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPINSRB $3, DX, X0, X0 +func simdVgpvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Offset = int64(v.AuxUInt8()) + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(v.Args[1].Reg()) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} +func simdVgpvImm(s *ssagen.State, v *ssa.Value) *obj.Prog { + // within simdgen, the choice of intrinsic shape and the output + // intruction format are linked. In the case of VgpImm, there is + // a difference in the intrinsic, but no difference in the + // instruction, it is just like VgpvImm8. + // + // See also, simdVgpImm and simdVgpImm8 + return simdVgpvImm8(s, v) +} + +// Example instruction: VPCMPD $1, Z1, Z2, K1 +func simdV2kImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Offset = int64(v.AuxUInt8()) + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = maskReg(v) + return p +} + +// Example instruction: VPCMPD $1, Z1, Z2, K2, K1 +func simdV2kkImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Offset = int64(v.AuxUInt8()) + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(maskReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = maskReg(v) + return p +} + +func simdV2kvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Offset = int64(v.AuxUInt8()) + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(maskReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VFMADD213PD Z2, Z1, Z0 +func simdV31ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[2]) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +func simdV31ResultInArg0Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Offset = int64(v.AuxUInt8()) + p.From.Type = obj.TYPE_CONST + + p.AddRestSourceReg(simdReg(v.Args[2])) + p.AddRestSourceReg(simdReg(v.Args[1])) + // p.AddRestSourceReg(x86.REG_K0) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// v31loadResultInArg0Imm8 +// Example instruction: +// for (VPTERNLOGD128load {sym} [makeValAndOff(int32(int8(c)),off)] x y ptr mem) +func simdV31loadResultInArg0Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + sc := v.AuxValAndOff() + p := s.Prog(v.Op.Asm()) + + p.From.Type = obj.TYPE_CONST + p.From.Offset = sc.Val64() + + m := obj.Addr{Type: obj.TYPE_MEM, Reg: v.Args[2].Reg()} + ssagen.AddAux2(&m, v, sc.Off64()) + p.AddRestSource(m) + + p.AddRestSourceReg(simdReg(v.Args[1])) + return p +} + +// Example instruction: VFMADD213PD Z2, Z1, K1, Z0 +func simdV3kvResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[2]) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(maskReg(v.Args[3])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +func simdVgpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Offset = int64(v.AuxUInt8()) + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() + return p +} + +func simdVgpImm(s *ssagen.State, v *ssa.Value) *obj.Prog { + // within simdgen, the choice of intrinsic shape and the output + // intruction format are linked. In the case of VgpImm, there is + // a difference in the intrinsic, but no difference in the + // instruction, it is just like VgpImm8. + return simdVgpImm8(s, v) +} + +// Currently unused +func simdV31(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[2]) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Currently unused +func simdV3kv(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[2]) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(maskReg(v.Args[3])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VRCP14PS (DI), K6, X22 +func simdVkvload(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.From, v) + p.AddRestSourceReg(maskReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPSLLVD (DX), X7, X18 +func simdV21load(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[1].Reg() + ssagen.AddAux(&p.From, v) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPDPWSSD (SI), X24, X18 +func simdV31loadResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[2].Reg() + ssagen.AddAux(&p.From, v) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPDPWSSD (SI), X24, K1, X18 +func simdV3kvloadResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[2].Reg() + ssagen.AddAux(&p.From, v) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(maskReg(v.Args[3])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPSLLVD (SI), X1, K1, X2 +func simdV2kvload(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[1].Reg() + ssagen.AddAux(&p.From, v) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(maskReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPCMPEQD (SI), X1, K1 +func simdV2kload(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[1].Reg() + ssagen.AddAux(&p.From, v) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = maskReg(v) + return p +} + +// Example instruction: VCVTTPS2DQ (BX), X2 +func simdV11load(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.From, v) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPSHUFD $7, (BX), X11 +func simdV11loadImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + sc := v.AuxValAndOff() + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = sc.Val64() + m := obj.Addr{Type: obj.TYPE_MEM, Reg: v.Args[0].Reg()} + ssagen.AddAux2(&m, v, sc.Off64()) + p.AddRestSource(m) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPRORD $81, -15(R14), K7, Y1 +func simdVkvloadImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + sc := v.AuxValAndOff() + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = sc.Val64() + m := obj.Addr{Type: obj.TYPE_MEM, Reg: v.Args[0].Reg()} + ssagen.AddAux2(&m, v, sc.Off64()) + p.AddRestSource(m) + p.AddRestSourceReg(maskReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPSHLDD $82, 7(SI), Y21, Y3 +func simdV21loadImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + sc := v.AuxValAndOff() + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = sc.Val64() + m := obj.Addr{Type: obj.TYPE_MEM, Reg: v.Args[1].Reg()} + ssagen.AddAux2(&m, v, sc.Off64()) + p.AddRestSource(m) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VCMPPS $81, -7(DI), Y16, K3 +func simdV2kloadImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + sc := v.AuxValAndOff() + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = sc.Val64() + m := obj.Addr{Type: obj.TYPE_MEM, Reg: v.Args[1].Reg()} + ssagen.AddAux2(&m, v, sc.Off64()) + p.AddRestSource(m) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = maskReg(v) + return p +} + +// Example instruction: VCMPPS $81, -7(DI), Y16, K1, K3 +func simdV2kkloadImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + sc := v.AuxValAndOff() + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = sc.Val64() + m := obj.Addr{Type: obj.TYPE_MEM, Reg: v.Args[1].Reg()} + ssagen.AddAux2(&m, v, sc.Off64()) + p.AddRestSource(m) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(maskReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = maskReg(v) + return p +} + +// Example instruction: VGF2P8AFFINEINVQB $64, -17(BP), X31, K3, X26 +func simdV2kvloadImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + sc := v.AuxValAndOff() + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = sc.Val64() + m := obj.Addr{Type: obj.TYPE_MEM, Reg: v.Args[1].Reg()} + ssagen.AddAux2(&m, v, sc.Off64()) + p.AddRestSource(m) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(maskReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: SHA1NEXTE X2, X2 +func simdV21ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[1]) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: SHA1RNDS4 $1, X2, X2 +func simdV21ResultInArg0Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Offset = int64(v.AuxUInt8()) + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: SHA256RNDS2 X0, X11, X2 +func simdV31x0AtIn2ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog { + return simdV31ResultInArg0(s, v) +} + var blockJump = [...]struct { asm, invasm obj.As }{ @@ -1732,7 +2523,7 @@ func ssaGenBlock(s *ssagen.State, b, next *ssa.Block) { } func loadRegResult(s *ssagen.State, f *ssa.Func, t *types.Type, reg int16, n *ir.Name, off int64) *obj.Prog { - p := s.Prog(loadByType(t)) + p := s.Prog(loadByRegWidth(reg, t.Size())) p.From.Type = obj.TYPE_MEM p.From.Name = obj.NAME_AUTO p.From.Sym = n.Linksym() @@ -1743,7 +2534,7 @@ func loadRegResult(s *ssagen.State, f *ssa.Func, t *types.Type, reg int16, n *ir } func spillArgReg(pp *objw.Progs, p *obj.Prog, f *ssa.Func, t *types.Type, reg int16, n *ir.Name, off int64) *obj.Prog { - p = pp.Append(p, storeByType(t), obj.TYPE_REG, reg, 0, obj.TYPE_MEM, 0, n.FrameOffset()+off) + p = pp.Append(p, storeByRegWidth(reg, t.Size()), obj.TYPE_REG, reg, 0, obj.TYPE_MEM, 0, n.FrameOffset()+off) p.To.Name = obj.NAME_PARAM p.To.Sym = n.Linksym() p.Pos = p.Pos.WithNotStmt() @@ -1778,3 +2569,58 @@ func move16(s *ssagen.State, src, dst, tmp int16, off int64) { p.To.Reg = dst p.To.Offset = off } + +// XXX maybe make this part of v.Reg? +// On the other hand, it is architecture-specific. +func simdReg(v *ssa.Value) int16 { + t := v.Type + if !t.IsSIMD() { + base.Fatalf("simdReg: not a simd type; v=%s, b=b%d, f=%s", v.LongString(), v.Block.ID, v.Block.Func.Name) + } + return simdRegBySize(v.Reg(), t.Size()) +} + +func simdRegBySize(reg int16, size int64) int16 { + switch size { + case 16: + return reg + case 32: + return reg + (x86.REG_Y0 - x86.REG_X0) + case 64: + return reg + (x86.REG_Z0 - x86.REG_X0) + } + panic("simdRegBySize: bad size") +} + +// XXX k mask +func maskReg(v *ssa.Value) int16 { + t := v.Type + if !t.IsSIMD() { + base.Fatalf("maskReg: not a simd type; v=%s, b=b%d, f=%s", v.LongString(), v.Block.ID, v.Block.Func.Name) + } + switch t.Size() { + case 8: + return v.Reg() + } + panic("unreachable") +} + +// XXX k mask + vec +func simdOrMaskReg(v *ssa.Value) int16 { + t := v.Type + if t.Size() <= 8 { + return maskReg(v) + } + return simdReg(v) +} + +// XXX this is used for shift operations only. +// regalloc will issue OpCopy with incorrect type, but the assigned +// register should be correct, and this function is merely checking +// the sanity of this part. +func simdCheckRegOnly(v *ssa.Value, regStart, regEnd int16) int16 { + if v.Reg() > regEnd || v.Reg() < regStart { + panic("simdCheckRegOnly: not the desired register") + } + return v.Reg() +} diff --git a/src/cmd/compile/internal/amd64/versions_nosimd_test.go b/src/cmd/compile/internal/amd64/versions_nosimd_test.go new file mode 100644 index 00000000000000..bbfe1c1aeaf85f --- /dev/null +++ b/src/cmd/compile/internal/amd64/versions_nosimd_test.go @@ -0,0 +1,14 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build !(amd64 && goexperiment.simd && !boringcrypto) + +package amd64_test + +func testLoop2(n int, x float64) float64 { + return 0 +} +func testLoop3(n int, x float64) float64 { + return 0 +} diff --git a/src/cmd/compile/internal/amd64/versions_simd_test.go b/src/cmd/compile/internal/amd64/versions_simd_test.go new file mode 100644 index 00000000000000..e05311ce664dc9 --- /dev/null +++ b/src/cmd/compile/internal/amd64/versions_simd_test.go @@ -0,0 +1,36 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build amd64 && goexperiment.simd && !boringcrypto + +package amd64_test + +import "simd/archsimd" + +//go:noinline +func testLoop2(n int, x float64) float64 { + var r float64 + for range n { + if archsimd.X86.AVX2() { + v := archsimd.BroadcastFloat64x2(x) + v = v.Mul(v) + r += v.GetElem(0) + } + } + return r +} + +//go:noinline +func testLoop3(n int, x float64) float64 { + var r float64 + if !archsimd.X86.AVX2() { + n = 0 + } + for range n { + v := archsimd.BroadcastFloat64x2(x) + v = v.Mul(v) + r += v.GetElem(0) + } + return r +} diff --git a/src/cmd/compile/internal/amd64/versions_test.go b/src/cmd/compile/internal/amd64/versions_test.go index 15395fc5e5283f..2563d1b3118f73 100644 --- a/src/cmd/compile/internal/amd64/versions_test.go +++ b/src/cmd/compile/internal/amd64/versions_test.go @@ -247,6 +247,7 @@ func setOf(keys ...string) map[string]bool { var runtimeFeatures = setOf( "adx", "aes", "avx", "avx2", "bmi1", "bmi2", "erms", "fma", "pclmulqdq", "popcnt", "rdtscp", "sse3", "sse41", "sse42", "ssse3", + "avx512f", "avx512dq", ) var featureToOpcodes = map[string][]string{ @@ -279,6 +280,7 @@ var featureToOpcodes = map[string][]string{ "fma": {"vfmadd231sd"}, "movbe": {"movbeqq", "movbeq", "movbell", "movbel", "movbe"}, "lzcnt": {"lzcntq", "lzcntl", "lzcnt"}, + "avx2": {"vmovsd", "vpbroadcastq", "vmulpd", "vpextrq"}, // not a complete list } // Test to use POPCNT instruction, if available @@ -432,3 +434,21 @@ func TestFMA(t *testing.T) { } } } + +func TestLoop(t *testing.T) { + // Make sure non-v1 ops are not lifted out of loops (and + // hence, out of the cpu feature test that guards them). + // See issue 78997. + testLoop1(6, 7) + testLoop2(6, 7) // in versions_(no)simd_test.go + testLoop3(6, 7) // in versions_(no)simd_test.go +} + +//go:noinline +func testLoop1(n int, x uint64) int { + var r int + for range n { + r += bits.OnesCount64(x) + } + return r +} diff --git a/src/cmd/compile/internal/arm/ssa.go b/src/cmd/compile/internal/arm/ssa.go index a3bfb491b8b25f..9dca52bf11a6d2 100644 --- a/src/cmd/compile/internal/arm/ssa.go +++ b/src/cmd/compile/internal/arm/ssa.go @@ -245,6 +245,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Type = obj.TYPE_REG p.To.Reg = r case ssa.OpARMADDS, + ssa.OpARMADCS, ssa.OpARMSUBS: r := v.Reg0() r1 := v.Args[0].Reg() @@ -700,7 +701,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Reg = v.Reg() case ssa.OpARMCALLstatic, ssa.OpARMCALLclosure, ssa.OpARMCALLinter: s.Call(v) - case ssa.OpARMCALLtail: + case ssa.OpARMCALLtail, ssa.OpARMCALLtailinter: s.TailCall(v) case ssa.OpARMCALLudiv: p := s.Prog(obj.ACALL) diff --git a/src/cmd/compile/internal/arm64/simdssa.go b/src/cmd/compile/internal/arm64/simdssa.go new file mode 100644 index 00000000000000..41ae2925425494 --- /dev/null +++ b/src/cmd/compile/internal/arm64/simdssa.go @@ -0,0 +1,469 @@ +// Code generated by 'simdgen -o godefs -goroot $GOROOT -arch arm64 -arm64Path $ARM64_ISA_PATH go_arm64.yaml types.yaml categories.yaml'; DO NOT EDIT. + +package arm64 + +import ( + "cmd/compile/internal/ssa" + "cmd/compile/internal/ssagen" + "cmd/internal/obj" + "cmd/internal/obj/arm64" +) + +func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { + var p *obj.Prog + switch v.Op { + case ssa.OpARM64VABS16B, + ssa.OpARM64VCLS16B, + ssa.OpARM64VCLZ16B, + ssa.OpARM64VNEG16B, + ssa.OpARM64VNOT16B, + ssa.OpARM64VCNT16B: + p = simdV11(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VFABS2D, + ssa.OpARM64VABS2D, + ssa.OpARM64VFRINTP2D, + ssa.OpARM64VSCVTF2D, + ssa.OpARM64VUCVTF2D, + ssa.OpARM64VFCVTZS2D, + ssa.OpARM64VFCVTZU2D, + ssa.OpARM64VFRINTM2D, + ssa.OpARM64VFNEG2D, + ssa.OpARM64VNEG2D, + ssa.OpARM64VFRINTN2D, + ssa.OpARM64VFSQRT2D, + ssa.OpARM64VFRINTZ2D: + p = simdV11(s, v, arm64.ARNG_2D) + + case ssa.OpARM64VFABS4S, + ssa.OpARM64VABS4S, + ssa.OpARM64VFRINTP4S, + ssa.OpARM64VSCVTF4S, + ssa.OpARM64VUCVTF4S, + ssa.OpARM64VFCVTZS4S, + ssa.OpARM64VFCVTZU4S, + ssa.OpARM64VFRINTM4S, + ssa.OpARM64VCLS4S, + ssa.OpARM64VCLZ4S, + ssa.OpARM64VFNEG4S, + ssa.OpARM64VNEG4S, + ssa.OpARM64VFRINTN4S, + ssa.OpARM64VFSQRT4S, + ssa.OpARM64VFRINTZ4S: + p = simdV11(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VABS8H, + ssa.OpARM64VCLS8H, + ssa.OpARM64VCLZ8H, + ssa.OpARM64VNEG8H: + p = simdV11(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VSHL16B, + ssa.OpARM64VSSHR16B, + ssa.OpARM64VUSHR16B, + ssa.OpARM64VSQSHL16Bconst, + ssa.OpARM64VUQSHL16Bconst: + p = simdV11Imm(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VSHL2D, + ssa.OpARM64VSSHR2D, + ssa.OpARM64VUSHR2D, + ssa.OpARM64VSQSHL2Dconst, + ssa.OpARM64VUQSHL2Dconst: + p = simdV11Imm(s, v, arm64.ARNG_2D) + + case ssa.OpARM64VSHL4S, + ssa.OpARM64VSSHR4S, + ssa.OpARM64VUSHR4S, + ssa.OpARM64VSQSHL4Sconst, + ssa.OpARM64VUQSHL4Sconst: + p = simdV11Imm(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSHL8H, + ssa.OpARM64VSSHR8H, + ssa.OpARM64VUSHR8H, + ssa.OpARM64VSQSHL8Hconst, + ssa.OpARM64VUQSHL8Hconst: + p = simdV11Imm(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VDUPBbcast: + p = simdV11ImmIn1(s, v, arm64.ARNG_B) + + case ssa.OpARM64VDUPDbcast: + p = simdV11ImmIn1(s, v, arm64.ARNG_D) + + case ssa.OpARM64VDUPHbcast: + p = simdV11ImmIn1(s, v, arm64.ARNG_H) + + case ssa.OpARM64VDUPSbcast: + p = simdV11ImmIn1(s, v, arm64.ARNG_S) + + case ssa.OpARM64VSMAXV16B, + ssa.OpARM64VUMAXV16B, + ssa.OpARM64VSMINV16B, + ssa.OpARM64VUMINV16B, + ssa.OpARM64VADDV16B: + p = simdV11Scalar(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VFMAXV4S, + ssa.OpARM64VSMAXV4S, + ssa.OpARM64VUMAXV4S, + ssa.OpARM64VFMINV4S, + ssa.OpARM64VSMINV4S, + ssa.OpARM64VUMINV4S, + ssa.OpARM64VADDV4S: + p = simdV11Scalar(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSMAXV8H, + ssa.OpARM64VUMAXV8H, + ssa.OpARM64VSMINV8H, + ssa.OpARM64VUMINV8H, + ssa.OpARM64VADDV8H: + p = simdV11Scalar(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VDUPDextr: + p = simdV11ScalarImmIn1(s, v, arm64.ARNG_D) + + case ssa.OpARM64VDUPSextr: + p = simdV11ScalarImmIn1(s, v, arm64.ARNG_S) + + case ssa.OpARM64VADD16B, + ssa.OpARM64VSQADD16B, + ssa.OpARM64VUQADD16B, + ssa.OpARM64VAND16B, + ssa.OpARM64VBIC16B, + ssa.OpARM64VSRHADD16B, + ssa.OpARM64VURHADD16B, + ssa.OpARM64VUZP116B, + ssa.OpARM64VUZP216B, + ssa.OpARM64VCMEQ16B, + ssa.OpARM64VCMGT16B, + ssa.OpARM64VCMHI16B, + ssa.OpARM64VCMGE16B, + ssa.OpARM64VCMHS16B, + ssa.OpARM64VTRN116B, + ssa.OpARM64VZIP216B, + ssa.OpARM64VZIP116B, + ssa.OpARM64VTRN216B, + ssa.OpARM64VSMAX16B, + ssa.OpARM64VUMAX16B, + ssa.OpARM64VSMIN16B, + ssa.OpARM64VUMIN16B, + ssa.OpARM64VMUL16B, + ssa.OpARM64VORR16B, + ssa.OpARM64VORN16B, + ssa.OpARM64VSSHL16B, + ssa.OpARM64VUSHL16B, + ssa.OpARM64VSQSHL16B, + ssa.OpARM64VUQSHL16B, + ssa.OpARM64VSUB16B, + ssa.OpARM64VSQSUB16B, + ssa.OpARM64VUQSUB16B, + ssa.OpARM64VEOR16B: + p = simdV21(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VFADD2D, + ssa.OpARM64VADD2D, + ssa.OpARM64VSQADD2D, + ssa.OpARM64VUQADD2D, + ssa.OpARM64VFADDP2D, + ssa.OpARM64VADDP2D, + ssa.OpARM64VUZP12D, + ssa.OpARM64VUZP22D, + ssa.OpARM64VFDIV2D, + ssa.OpARM64VFCMEQ2D, + ssa.OpARM64VCMEQ2D, + ssa.OpARM64VFCMGT2D, + ssa.OpARM64VCMGT2D, + ssa.OpARM64VCMHI2D, + ssa.OpARM64VFCMGE2D, + ssa.OpARM64VCMGE2D, + ssa.OpARM64VCMHS2D, + ssa.OpARM64VTRN12D, + ssa.OpARM64VZIP22D, + ssa.OpARM64VZIP12D, + ssa.OpARM64VTRN22D, + ssa.OpARM64VFMAX2D, + ssa.OpARM64VFMIN2D, + ssa.OpARM64VFMUL2D, + ssa.OpARM64VSSHL2D, + ssa.OpARM64VUSHL2D, + ssa.OpARM64VSQSHL2D, + ssa.OpARM64VUQSHL2D, + ssa.OpARM64VFSUB2D, + ssa.OpARM64VSUB2D, + ssa.OpARM64VSQSUB2D, + ssa.OpARM64VUQSUB2D: + p = simdV21(s, v, arm64.ARNG_2D) + + case ssa.OpARM64VFADD4S, + ssa.OpARM64VADD4S, + ssa.OpARM64VSQADD4S, + ssa.OpARM64VUQADD4S, + ssa.OpARM64VSRHADD4S, + ssa.OpARM64VURHADD4S, + ssa.OpARM64VFADDP4S, + ssa.OpARM64VADDP4S, + ssa.OpARM64VUZP14S, + ssa.OpARM64VUZP24S, + ssa.OpARM64VFDIV4S, + ssa.OpARM64VFCMEQ4S, + ssa.OpARM64VCMEQ4S, + ssa.OpARM64VFCMGT4S, + ssa.OpARM64VCMGT4S, + ssa.OpARM64VCMHI4S, + ssa.OpARM64VFCMGE4S, + ssa.OpARM64VCMGE4S, + ssa.OpARM64VCMHS4S, + ssa.OpARM64VTRN14S, + ssa.OpARM64VZIP24S, + ssa.OpARM64VZIP14S, + ssa.OpARM64VTRN24S, + ssa.OpARM64VFMAX4S, + ssa.OpARM64VSMAX4S, + ssa.OpARM64VUMAX4S, + ssa.OpARM64VFMIN4S, + ssa.OpARM64VSMIN4S, + ssa.OpARM64VUMIN4S, + ssa.OpARM64VFMUL4S, + ssa.OpARM64VMUL4S, + ssa.OpARM64VSSHL4S, + ssa.OpARM64VUSHL4S, + ssa.OpARM64VSQSHL4S, + ssa.OpARM64VUQSHL4S, + ssa.OpARM64VFSUB4S, + ssa.OpARM64VSUB4S, + ssa.OpARM64VSQSUB4S, + ssa.OpARM64VUQSUB4S: + p = simdV21(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VADD8H, + ssa.OpARM64VSQADD8H, + ssa.OpARM64VUQADD8H, + ssa.OpARM64VSRHADD8H, + ssa.OpARM64VURHADD8H, + ssa.OpARM64VADDP8H, + ssa.OpARM64VUZP18H, + ssa.OpARM64VUZP28H, + ssa.OpARM64VCMEQ8H, + ssa.OpARM64VCMGT8H, + ssa.OpARM64VCMHI8H, + ssa.OpARM64VCMGE8H, + ssa.OpARM64VCMHS8H, + ssa.OpARM64VTRN18H, + ssa.OpARM64VZIP28H, + ssa.OpARM64VZIP18H, + ssa.OpARM64VTRN28H, + ssa.OpARM64VSMAX8H, + ssa.OpARM64VUMAX8H, + ssa.OpARM64VSMIN8H, + ssa.OpARM64VUMIN8H, + ssa.OpARM64VMUL8H, + ssa.OpARM64VSSHL8H, + ssa.OpARM64VUSHL8H, + ssa.OpARM64VSQSHL8H, + ssa.OpARM64VUQSHL8H, + ssa.OpARM64VSUB8H, + ssa.OpARM64VSQSUB8H, + ssa.OpARM64VUQSUB8H: + p = simdV21(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VEXT16B: + p = simdV21Imm(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VMLA16B, + ssa.OpARM64VBIF16B, + ssa.OpARM64VBIT16B: + p = simdV31ResultInArg0(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VFMLA2D: + p = simdV31ResultInArg0(s, v, arm64.ARNG_2D) + + case ssa.OpARM64VFMLA4S, + ssa.OpARM64VMLA4S: + p = simdV31ResultInArg0(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VMLA8H: + p = simdV31ResultInArg0(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VMOVBextr: + p = simdVgpImmIn1(s, v, arm64.ARNG_B) + + case ssa.OpARM64VMOVDextr: + p = simdVgpImmIn1(s, v, arm64.ARNG_D) + + case ssa.OpARM64VMOVHextr: + p = simdVgpImmIn1(s, v, arm64.ARNG_H) + + case ssa.OpARM64VMOVSextr: + p = simdVgpImmIn1(s, v, arm64.ARNG_S) + + case ssa.OpARM64VMOVBins: + p = simdVgpvResultInArg0ImmOutIn0(s, v, arm64.ARNG_B) + + case ssa.OpARM64VMOVDins: + p = simdVgpvResultInArg0ImmOutIn0(s, v, arm64.ARNG_D) + + case ssa.OpARM64VMOVHins: + p = simdVgpvResultInArg0ImmOutIn0(s, v, arm64.ARNG_H) + + case ssa.OpARM64VMOVSins: + p = simdVgpvResultInArg0ImmOutIn0(s, v, arm64.ARNG_S) + + case ssa.OpARM64VMOVDins0: + p = simdVfpvResultInArg0ImmOutIn1(s, v, arm64.ARNG_D) + + case ssa.OpARM64VMOVSins0: + p = simdVfpvResultInArg0ImmOutIn1(s, v, arm64.ARNG_S) + + case ssa.OpARM64VSXTL16B, + ssa.OpARM64VUXTL16B: + p = simdV11Long(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VFCVTL4S, + ssa.OpARM64VSXTL4S, + ssa.OpARM64VUXTL4S: + p = simdV11Long(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSXTL8H, + ssa.OpARM64VUXTL8H: + p = simdV11Long(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VFCVTN2D, + ssa.OpARM64VSQXTN2D, + ssa.OpARM64VSQXTUN2D, + ssa.OpARM64VUQXTN2D, + ssa.OpARM64VXTN2D: + p = simdV11Narrow(s, v, arm64.ARNG_2D) + + case ssa.OpARM64VSQXTN4S, + ssa.OpARM64VSQXTUN4S, + ssa.OpARM64VUQXTN4S, + ssa.OpARM64VXTN4S: + p = simdV11Narrow(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSQXTN8H, + ssa.OpARM64VSQXTUN8H, + ssa.OpARM64VUQXTN8H, + ssa.OpARM64VXTN8H: + p = simdV11Narrow(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VSHRN2D: + p = simdV11ImmNarrow(s, v, arm64.ARNG_2D) + + case ssa.OpARM64VSHRN4S: + p = simdV11ImmNarrow(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSHRN8H: + p = simdV11ImmNarrow(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VSSHLL16B, + ssa.OpARM64VUSHLL16B: + p = simdV11ImmLong(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VSSHLL4S, + ssa.OpARM64VUSHLL4S: + p = simdV11ImmLong(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSSHLL8H, + ssa.OpARM64VUSHLL8H: + p = simdV11ImmLong(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VSMULL16B, + ssa.OpARM64VUMULL16B: + p = simdV21Long(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VPMULL2D: + p = simdV21Long(s, v, arm64.ARNG_2D) + + case ssa.OpARM64VSMULL4S, + ssa.OpARM64VUMULL4S: + p = simdV21Long(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSMULL8H, + ssa.OpARM64VUMULL8H: + p = simdV21Long(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VSXTL2_16B, + ssa.OpARM64VUXTL2_16B: + p = simdV11Long2(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VFCVTL2_4S, + ssa.OpARM64VSXTL2_4S, + ssa.OpARM64VUXTL2_4S: + p = simdV11Long2(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSXTL2_8H, + ssa.OpARM64VUXTL2_8H: + p = simdV11Long2(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VFCVTN2_2D, + ssa.OpARM64VSQXTN2_2D, + ssa.OpARM64VSQXTUN2_2D, + ssa.OpARM64VUQXTN2_2D, + ssa.OpARM64VXTN2_2D: + p = simdV21Narrow2(s, v, arm64.ARNG_2D) + + case ssa.OpARM64VSQXTN2_4S, + ssa.OpARM64VSQXTUN2_4S, + ssa.OpARM64VUQXTN2_4S, + ssa.OpARM64VXTN2_4S: + p = simdV21Narrow2(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSQXTN2_8H, + ssa.OpARM64VSQXTUN2_8H, + ssa.OpARM64VUQXTN2_8H, + ssa.OpARM64VXTN2_8H: + p = simdV21Narrow2(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VSHRN2_2D: + p = simdV21ImmNarrow2(s, v, arm64.ARNG_2D) + + case ssa.OpARM64VSHRN2_4S: + p = simdV21ImmNarrow2(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSHRN2_8H: + p = simdV21ImmNarrow2(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VSSHLL2_16B, + ssa.OpARM64VUSHLL2_16B: + p = simdV11ImmLong2(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VSSHLL2_4S, + ssa.OpARM64VUSHLL2_4S: + p = simdV11ImmLong2(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSSHLL2_8H, + ssa.OpARM64VUSHLL2_8H: + p = simdV11ImmLong2(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VSMULL2_16B, + ssa.OpARM64VUMULL2_16B: + p = simdV21Long2(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VPMULL2_2D: + p = simdV21Long2(s, v, arm64.ARNG_2D) + + case ssa.OpARM64VSMULL2_4S, + ssa.OpARM64VUMULL2_4S: + p = simdV21Long2(s, v, arm64.ARNG_4S) + + case ssa.OpARM64VSMULL2_8H, + ssa.OpARM64VUMULL2_8H: + p = simdV21Long2(s, v, arm64.ARNG_8H) + + case ssa.OpARM64VTBL16B: + p = simdV21List(s, v, arm64.ARNG_16B) + + case ssa.OpARM64VTBX16B: + p = simdV31ResultInArg0List(s, v, arm64.ARNG_16B) + + default: + // Unknown reg shape + return false + } + + // Ensure p is marked as used (may not be used in all generated code paths) + _ = p + return true +} diff --git a/src/cmd/compile/internal/arm64/ssa.go b/src/cmd/compile/internal/arm64/ssa.go index 43ecb6b4b715b4..44bf01dfa47db2 100644 --- a/src/cmd/compile/internal/arm64/ssa.go +++ b/src/cmd/compile/internal/arm64/ssa.go @@ -21,7 +21,11 @@ import ( // loadByType returns the load instruction of the given type. func loadByType(t *types.Type) obj.As { - if t.IsFloat() { + if t.IsSIMD() { + if t.Size() == 16 { + return arm64.AFMOVQ // Use FMOVQ (LDR Q) for 128-bit SIMD loads + } + } else if t.IsFloat() { switch t.Size() { case 4: return arm64.AFMOVS @@ -57,7 +61,11 @@ func loadByType(t *types.Type) obj.As { // storeByType returns the store instruction of the given type. func storeByType(t *types.Type) obj.As { - if t.IsFloat() { + if t.IsSIMD() { + if t.Size() == 16 { + return arm64.AFMOVQ // Use FMOVQ (STR Q) for 128-bit SIMD stores + } + } else if t.IsFloat() { switch t.Size() { case 4: return arm64.AFMOVS @@ -162,6 +170,410 @@ func genIndexedOperand(op ssa.Op, base, idx int16) obj.Addr { return mop } +// simdRegArng encodes ssa value's register with specified simd arrangement +func simdRegArng(reg int16, arng int16) int16 { + if reg < arm64.REG_F0 || arm64.REG_F31 < reg { + base.Fatalf("expected fp register: r%d", reg) + } + var err error + if reg, err = arm64.RegisterArrangement(reg, arng, false); err != nil { + base.Fatalf("bad simd register arrangement: %v", err) + } + return reg +} + +// simdRegElem encodes ssa value's reference to a vector register element +func simdRegElem(reg int16, arng int16, idx int16) (res obj.Addr) { + if reg < arm64.REG_F0 || arm64.REG_F31 < reg { + base.Fatalf("expected fp register: r%d", reg) + } + elem, err := arm64.RegisterArrangement(reg, arng, true /*indexing*/) + if err != nil { + base.Fatalf("bad simd register indexing arrangement: %v", err) + } + res.Type = obj.TYPE_REG + res.Class = arm64.C_ELEM + res.Index = idx + res.Reg = elem + return +} + +// allLanes converts an element arrangement to its 128-bit vector arrangement. +// e.g., ARNG_B -> ARNG_16B, ARNG_S -> ARNG_4S +func allLanes(arng int16) int16 { + switch arng { + case arm64.ARNG_B: + return arm64.ARNG_16B + case arm64.ARNG_H: + return arm64.ARNG_8H + case arm64.ARNG_S: + return arm64.ARNG_4S + case arm64.ARNG_D: + return arm64.ARNG_2D + default: + base.Fatalf("unsupported element arrangement: %d", arng) + return 0 + } +} + +// arngNarrow converts arng to its narrow (halved element width and vector width) arrangement. +func arngNarrow(arng int16) int16 { + switch arng { + case arm64.ARNG_8H: + return arm64.ARNG_8B + case arm64.ARNG_4S: + return arm64.ARNG_4H + case arm64.ARNG_2D: + return arm64.ARNG_2S + default: + base.Fatalf("unsupported narrow input arrangement: %d", arng) + return 0 + } +} + +// arngLong converts a half-lane arrangement to its long (doubled element width and vector width) arrangement. +func arngLong(arng int16) int16 { + switch arng { + case arm64.ARNG_8B: + return arm64.ARNG_8H + case arm64.ARNG_4H: + return arm64.ARNG_4S + case arm64.ARNG_2S: + return arm64.ARNG_2D + case arm64.ARNG_1D: + return arm64.ARNG_1Q + default: + base.Fatalf("unsupported long input arrangement: %d", arng) + return 0 + } +} + +// arngHalfLanes converts a full-width arrangement to its half-lane (64-bit) arrangement. +// Same element width, half the lanes. Used for long base variant sources. +func arngHalfLanes(arng int16) int16 { + switch arng { + case arm64.ARNG_16B: + return arm64.ARNG_8B + case arm64.ARNG_8H: + return arm64.ARNG_4H + case arm64.ARNG_4S: + return arm64.ARNG_2S + case arm64.ARNG_2D: + return arm64.ARNG_1D + default: + base.Fatalf("unsupported halfLanes input arrangement: %d", arng) + return 0 + } +} + +// arngTwiceLanes converts a half-lane (64-bit) arrangement to its full-width arrangement. +// Same element width, double the lanes. Inverse of arngHalfLanes. +func arngTwiceLanes(arng int16) int16 { + switch arng { + case arm64.ARNG_8B: + return arm64.ARNG_16B + case arm64.ARNG_4H: + return arm64.ARNG_8H + case arm64.ARNG_2S: + return arm64.ARNG_4S + default: + base.Fatalf("unsupported twiceLanes input arrangement: %d", arng) + return 0 + } +} + +// simdV01Imm generates a VMOVI-like instruction, e.g. VMOVI $0, V0.B16 +func simdV01Imm(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = int64(v.AuxUInt8()) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arrangement) + return p +} + +// simdV11Asm generates element-wise unary vector operations with explicit asm, e.g. VMOV V1.B16, V0.B16 +func simdV11Asm(s *ssagen.State, asm obj.As, src, dst int16, arrangement int16) *obj.Prog { + p := s.Prog(asm) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(src, arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(dst, arrangement) + return p +} + +// simdV11 generates element-wise unary vector operations, e.g. VCNT V1.B8, V0.B8 +func simdV11(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + return simdV11Asm(s, v.Op.Asm(), v.Args[0].Reg(), v.Reg(), arrangement) +} + +// simdV11Imm generates a unary vector operation with immediate constant, +// e.g. VUSHR $3, V1.B16, V0.B16 +func simdV11Imm(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = int64(v.AuxUInt8()) + p.Reg = simdRegArng(v.Args[0].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arrangement) + return p +} + +// simdV11ImmIn1 generates a broadcast1ToN instruction, +// e.g. VDUP V1.S[0], V0.S4 (duplicate element 0 to all lanes) +// The arrangement parameter specifies the element arrangement (e.g., ARNG_S, ARNG_D) +func simdV11ImmIn1(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From = simdRegElem(v.Args[0].Reg(), arrangement, int16(v.AuxUInt8())) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), allLanes(arrangement)) + return p +} + +// simdV11Scalar generates vector-to-scalar reduction operations, e.g. VUADDLV V1.B8, V0 +func simdV11Scalar(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[0].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() - arm64.REG_F0 + arm64.REG_V0 + return p +} + +// simdV11ScalarImmIn1 generates a SIMD instruction with indexed input and +// scalar-in-vector-register output, e.g. VDUP V1.S[1], V0 +// The arrangement parameter specifies the source arrangement (e.g., S, D) +func simdV11ScalarImmIn1(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From = simdRegElem(v.Args[0].Reg(), arrangement, int16(v.AuxUInt8())) + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() - arm64.REG_F0 + arm64.REG_V0 + p.To.Class = arm64.C_VREG + return p +} + +// simdV21 generates element-wise binary vector operations, e.g. VFADD V1.S4, V2.S4, V0.S4 +func simdV21(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[1].Reg(), arrangement) + p.Reg = simdRegArng(v.Args[0].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arrangement) + return p +} + +// simdV21Imm generates a binary instruction with immediate, e.g. EXT $imm, Vm.16B, Vn.16B, Vd.16B +func simdV21Imm(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = int64(v.AuxUInt8()) + p.Reg = simdRegArng(v.Args[0].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arrangement) + p.AddRestSource(obj.Addr{Type: obj.TYPE_REG, Reg: simdRegArng(v.Args[1].Reg(), arrangement)}) + return p +} + +// simdV31ResultInArg0 generates a destructive 3-register instruction, +// e.g. VBIT Vm.16B, Vn.16B, Vd.16B. +func simdV31ResultInArg0(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[2].Reg(), arrangement) + p.Reg = simdRegArng(v.Args[1].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arrangement) + return p +} + +// simdV21List generates a binary instruction with register list, e.g. TBL Vm.Ta, {Vn.B16}, Vd.Ta. +func simdV21List(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + if v.Op.Asm() != arm64.AVTBL { // TODO: support other instructions as needed. + panic("simdV21List: expected VTBL") + } + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[1].Reg(), arrangement) + // TBL requires B16 table arrangement. + // Also, multi-element register lists are not supported by regalloc. + const listB16 = int64(1 << 30) + regList, _ := arm64.RegisterListOffset(int(v.Args[0].Reg()&31), 1, listB16, 0) + p.AddRestSource(obj.Addr{Type: obj.TYPE_REGLIST, Offset: regList}) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arrangement) + return p +} + +// simdV31ResultInArg0List generates a destructive 3-register instruction +// with register list, e.g. TBX Vm.Ta, {Vn.B16}, Vd.Ta. +func simdV31ResultInArg0List(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + if v.Op.Asm() != arm64.AVTBX { // TODO: support other instructions as needed. + panic("simdV31ResultInArg0List: expected VTBX") + } + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[2].Reg(), arrangement) + // TBX requires B16 table arrangement. + // Also, multi-element register lists are not supported by regalloc. + const listB16 = int64(1 << 30) + regList, _ := arm64.RegisterListOffset(int(v.Args[1].Reg()&31), 1, listB16, 0) + p.AddRestSource(obj.Addr{Type: obj.TYPE_REGLIST, Offset: regList}) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arrangement) + return p +} + +// simdVfpvResultInArg0ImmOutIn1 generates vector floating-point SetElem, +// e.g. VMOV V2.S[0], V1.S[3] (INS element instruction) +// The arrangement parameter specifies the vector element arrangement (e.g., S, D) +func simdVfpvResultInArg0ImmOutIn1(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.To = simdRegElem(v.Reg(), arrangement, int16(v.AuxUInt8())) + p.From = simdRegElem(v.Args[1].Reg(), arrangement, 0) + return p +} + +// simdVgpImmIn1 generates vector GetElem instruction VMOV V1.S[2], R0 +// The arrangement parameter specifies the vector element arrangement (e.g., S, D) +func simdVgpImmIn1(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From = simdRegElem(v.Args[0].Reg(), arrangement, int16(v.AuxUInt8())) + p.To.Reg = v.Reg() + p.To.Type = obj.TYPE_REG + return p +} + +// simdVgpvResultInArg0ImmOutIn0 generates vector SetElem, e.g. VMOV R0, V1.S[2] (INS general instruction) +// The arrangement parameter specifies the vector element arrangement (e.g., S, D) +func simdVgpvResultInArg0ImmOutIn0(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.To = simdRegElem(v.Reg(), arrangement, int16(v.AuxUInt8())) + p.From.Reg = v.Args[1].Reg() + p.From.Type = obj.TYPE_REG + return p +} + +// Narrow and long lowering helpers + +// simdV11Narrow generates a pure narrowing instruction, e.g. XTN Vn.8H, Vd.8B +func simdV11Narrow(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[0].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arngNarrow(arrangement)) + return p +} + +// simdV21Narrow2 generates a a destructive (updating upper half only) narrow "2" instruction, +// e.g. XTN2 V1.4S, V0.8H. The arrangement parameter specifies the source arrangement. +func simdV21Narrow2(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[1].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arngTwiceLanes(arngNarrow(arrangement))) + return p +} + +// simdV11ImmNarrow generates a pure narrowing instruction with immediate, e.g. SHRN $imm, V1.4S, V0.8B +// The arrangement parameter specifies the source arrangement. +func simdV11ImmNarrow(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = int64(v.AuxUInt8()) + p.Reg = simdRegArng(v.Args[0].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arngNarrow(arrangement)) + return p +} + +// simdV21ImmNarrow2 generates a destructive (updating upper half only) narrow "2" instruction +// with immediate, e.g. SHRN2 $imm, V1.4S, V0.16B. The arrangement parameter specifies the source arrangement. +func simdV21ImmNarrow2(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = int64(v.AuxUInt8()) + p.Reg = simdRegArng(v.Args[1].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arngTwiceLanes(arngNarrow(arrangement))) + return p +} + +// simdV11Long generates a unary long instruction, e.g. SXTL V1.4H, V0.8H +// The instruction reads the lower half of the source, the destination has 2x element size. +func simdV11Long(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + src := arngHalfLanes(arrangement) + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[0].Reg(), src) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arngLong(src)) + return p +} + +// simdV11Long2 generates a unary long "2" instruction, e.g. SXTL2 V1.4S, V0.2D +// The instruction reads the upper half of the source, the destination has 2x element size. +func simdV11Long2(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[0].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arngLong(arngHalfLanes(arrangement))) + return p +} + +// simdV11ImmLong generates a long instruction with immediate, e.g. USHLL $imm, V1.4H, V0.8H +// The instruction reads the lower half of the source, the destination has 2x element size. +func simdV11ImmLong(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + src := arngHalfLanes(arrangement) + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = int64(v.AuxUInt8()) + p.Reg = simdRegArng(v.Args[0].Reg(), src) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arngLong(src)) + return p +} + +// simdV11ImmLong2 generates a long "2" instruction with immediate, e.g. USHLL2 $imm, V1.4S, V0.2D +// The instruction reads the upper half of the source, the destination has 2x element size. +func simdV11ImmLong2(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_CONST + p.From.Offset = int64(v.AuxUInt8()) + p.Reg = simdRegArng(v.Args[0].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arngLong(arngHalfLanes(arrangement))) + return p +} + +// simdV21Long generates a binary long instruction, e.g. UMULL V1.4H, V2.4H, V0.8H +// The instruction reads lower halves of its sources, the destination has 2x element size. +func simdV21Long(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + src := arngHalfLanes(arrangement) + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[1].Reg(), src) + p.Reg = simdRegArng(v.Args[0].Reg(), src) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arngLong(src)) + return p +} + +// simdV21Long2 generates a binary long "2" instruction, e.g. UMULL2 V1.4S, V2.4S, V0.2D +// The instruction reads upper halves of its sources, the destination has 2x element size. +func simdV21Long2(s *ssagen.State, v *ssa.Value, arrangement int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdRegArng(v.Args[1].Reg(), arrangement) + p.Reg = simdRegArng(v.Args[0].Reg(), arrangement) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdRegArng(v.Reg(), arngLong(arngHalfLanes(arrangement))) + return p +} + func ssaGenValue(s *ssagen.State, v *ssa.Value) { switch v.Op { case ssa.OpCopy, ssa.OpARM64MOVDreg: @@ -183,6 +595,13 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { default: panic("bad float size") } + } else if v.Type.IsSIMD() { + if v.Type.Size() == 16 { + simdV11Asm(s, arm64.AVMOV, x, y, arm64.ARNG_16B) + return + } else { + panic("bad simd size") + } } p := s.Prog(as) p.From.Type = obj.TYPE_REG @@ -191,6 +610,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Reg = y case ssa.OpARM64MOVDnop, ssa.OpARM64ZERO: // nothing to do + case ssa.OpARM64VMOVI16B: + simdV01Imm(s, v, arm64.ARNG_16B) case ssa.OpLoadReg: if v.Type.IsFlags() { v.Fatalf("load flags not implemented: %v", v.LongString()) @@ -510,14 +931,15 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpARM64MOVWUload, ssa.OpARM64MOVDload, ssa.OpARM64FMOVSload, - ssa.OpARM64FMOVDload: + ssa.OpARM64FMOVDload, + ssa.OpARM64FMOVQload: p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_MEM p.From.Reg = v.Args[0].Reg() ssagen.AddAux(&p.From, v) p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg() - case ssa.OpARM64LDP, ssa.OpARM64LDPW, ssa.OpARM64LDPSW, ssa.OpARM64FLDPD, ssa.OpARM64FLDPS: + case ssa.OpARM64LDP, ssa.OpARM64LDPW, ssa.OpARM64LDPSW, ssa.OpARM64FLDPD, ssa.OpARM64FLDPS, ssa.OpARM64FLDPQ: p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_MEM p.From.Reg = v.Args[0].Reg() @@ -560,6 +982,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpARM64MOVDstore, ssa.OpARM64FMOVSstore, ssa.OpARM64FMOVDstore, + ssa.OpARM64FMOVQstore, ssa.OpARM64STLRB, ssa.OpARM64STLR, ssa.OpARM64STLRW: @@ -584,7 +1007,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To = genIndexedOperand(v.Op, v.Args[0].Reg(), v.Args[1].Reg()) p.From.Type = obj.TYPE_REG p.From.Reg = v.Args[2].Reg() - case ssa.OpARM64STP, ssa.OpARM64STPW, ssa.OpARM64FSTPD, ssa.OpARM64FSTPS: + case ssa.OpARM64STP, ssa.OpARM64STPW, ssa.OpARM64FSTPD, ssa.OpARM64FSTPS, ssa.OpARM64FSTPQ: p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REGREG p.From.Reg = v.Args[1].Reg() @@ -963,6 +1386,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { case ssa.OpARM64MVN, ssa.OpARM64NEG, ssa.OpARM64FABSD, + ssa.OpARM64FABSS, ssa.OpARM64FMOVDfpgp, ssa.OpARM64FMOVDgpfp, ssa.OpARM64FMOVSfpgp, @@ -1001,7 +1425,12 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpARM64FRINTMD, ssa.OpARM64FRINTND, ssa.OpARM64FRINTPD, - ssa.OpARM64FRINTZD: + ssa.OpARM64FRINTZD, + ssa.OpARM64FRINTAS, + ssa.OpARM64FRINTMS, + ssa.OpARM64FRINTNS, + ssa.OpARM64FRINTPS, + ssa.OpARM64FRINTZS: p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REG p.From.Reg = v.Args[0].Reg() @@ -1010,17 +1439,9 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { case ssa.OpARM64LoweredRound32F, ssa.OpARM64LoweredRound64F: // input is already rounded case ssa.OpARM64VCNT: - p := s.Prog(v.Op.Asm()) - p.From.Type = obj.TYPE_REG - p.From.Reg = (v.Args[0].Reg()-arm64.REG_F0)&31 + arm64.REG_ARNG + ((arm64.ARNG_8B & 15) << 5) - p.To.Type = obj.TYPE_REG - p.To.Reg = (v.Reg()-arm64.REG_F0)&31 + arm64.REG_ARNG + ((arm64.ARNG_8B & 15) << 5) + simdV11(s, v, arm64.ARNG_8B) case ssa.OpARM64VUADDLV: - p := s.Prog(v.Op.Asm()) - p.From.Type = obj.TYPE_REG - p.From.Reg = (v.Args[0].Reg()-arm64.REG_F0)&31 + arm64.REG_ARNG + ((arm64.ARNG_8B & 15) << 5) - p.To.Type = obj.TYPE_REG - p.To.Reg = v.Reg() - arm64.REG_F0 + arm64.REG_V0 + simdV11Scalar(s, v, arm64.ARNG_8B) case ssa.OpARM64CSEL, ssa.OpARM64CSEL0: r1 := int16(arm64.REGZERO) if v.Op != ssa.OpARM64CSEL0 { @@ -1314,7 +1735,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { case ssa.OpARM64CALLstatic, ssa.OpARM64CALLclosure, ssa.OpARM64CALLinter: s.Call(v) - case ssa.OpARM64CALLtail: + case ssa.OpARM64CALLtail, ssa.OpARM64CALLtailinter: s.TailCall(v) case ssa.OpARM64LoweredWB: p := s.Prog(obj.ACALL) @@ -1322,6 +1743,11 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Name = obj.NAME_EXTERN // AuxInt encodes how many buffer entries we need. p.To.Sym = ir.Syms.GCWriteBarrier[v.AuxInt-1] + case ssa.OpARM64LoweredMemEq: + p := s.Prog(obj.ACALL) + p.To.Type = obj.TYPE_MEM + p.To.Name = obj.NAME_EXTERN + p.To.Sym = ir.Syms.Memequal case ssa.OpARM64LoweredPanicBoundsRR, ssa.OpARM64LoweredPanicBoundsRC, ssa.OpARM64LoweredPanicBoundsCR, ssa.OpARM64LoweredPanicBoundsCC: // Compute the constant we put in the PCData entry for this call. @@ -1507,7 +1933,9 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg() default: - v.Fatalf("genValue not implemented: %s", v.LongString()) + if !ssaGenSIMDValue(s, v) { + v.Fatalf("genValue not implemented: %s", v.LongString()) + } } } diff --git a/src/cmd/compile/internal/base/base.go b/src/cmd/compile/internal/base/base.go index ee3772c5ca2bfa..405c7938a51aad 100644 --- a/src/cmd/compile/internal/base/base.go +++ b/src/cmd/compile/internal/base/base.go @@ -5,11 +5,7 @@ package base import ( - "fmt" "os" - "runtime" - "runtime/debug" - "runtime/metrics" ) var atExitFuncs []func() @@ -29,193 +25,3 @@ func Exit(code int) { // To enable tracing support (-t flag), set EnableTrace to true. const EnableTrace = false - -// forEachGC calls fn each GC cycle until it returns false. -func forEachGC(fn func() bool) { - type T [32]byte // large enough to avoid runtime's tiny object allocator - - var finalizer func(*T) - finalizer = func(p *T) { - if fn() { - runtime.SetFinalizer(p, finalizer) - } - } - - finalizer(new(T)) -} - -// AdjustStartingHeap modifies GOGC so that GC should not occur until the heap -// grows to the requested size. This is intended but not promised, though it -// is true-mostly, depending on when the adjustment occurs and on the -// compiler's input and behavior. Once this size is approximately reached -// GOGC is reset to 100; subsequent GCs may reduce the heap below the requested -// size, but this function does not affect that. -// -// -d=gcadjust=1 enables logging of GOGC adjustment events. -// -// NOTE: If you think this code would help startup time in your own -// application and you decide to use it, please benchmark first to see if it -// actually works for you (it may not: the Go compiler is not typical), and -// whatever the outcome, please leave a comment on bug #56546. This code -// uses supported interfaces, but depends more than we like on -// current+observed behavior of the garbage collector, so if many people need -// this feature, we should consider/propose a better way to accomplish it. -func AdjustStartingHeap(requestedHeapGoal uint64) { - logHeapTweaks := Debug.GCAdjust == 1 - mp := runtime.GOMAXPROCS(0) - gcConcurrency := Flag.LowerC - - const ( - goal = "/gc/heap/goal:bytes" - count = "/gc/cycles/total:gc-cycles" - allocs = "/gc/heap/allocs:bytes" - frees = "/gc/heap/frees:bytes" - ) - - sample := []metrics.Sample{{Name: goal}, {Name: count}, {Name: allocs}, {Name: frees}} - const ( - GOAL = 0 - COUNT = 1 - ALLOCS = 2 - FREES = 3 - ) - - // Assumptions and observations of Go's garbage collector, as of Go 1.17-1.20: - - // - the initial heap goal is 4M, by fiat. It is possible for Go to start - // with a heap as small as 512k, so this may change in the future. - - // - except for the first heap goal, heap goal is a function of - // observed-live at the previous GC and current GOGC. After the first - // GC, adjusting GOGC immediately updates GOGC; before the first GC, - // adjusting GOGC does not modify goal (but the change takes effect after - // the first GC). - - // - the before/after first GC behavior is not guaranteed anywhere, it's - // just behavior, and it's a bad idea to rely on it. - - // - we don't know exactly when GC will run, even after we adjust GOGC; the - // first GC may not have happened yet, may have already happened, or may - // be currently in progress, and GCs can start for several reasons. - - // - forEachGC above will run the provided function at some delay after each - // GC's mark phase terminates; finalizers are run after marking as the - // spans containing finalizable objects are swept, driven by GC - // background activity and allocation demand. - - // - "live at last GC" is not available through the current metrics - // interface. Instead, live is estimated by knowing the adjusted value of - // GOGC and the new heap goal following a GC (this requires knowing that - // at least one GC has occurred): - // estLive = 100 * newGoal / (100 + currentGogc) - // this new value of GOGC - // newGogc = 100*requestedHeapGoal/estLive - 100 - // will result in the desired goal. The logging code checks that the - // resulting goal is correct. - - // There's a small risk that the finalizer will be slow to run after a GC - // that expands the goal to a huge value, and that this will lead to - // out-of-memory. This doesn't seem to happen; in experiments on a variety - // of machines with a variety of extra loads to disrupt scheduling, the - // worst overshoot observed was 50% past requestedHeapGoal. - - metrics.Read(sample) - for _, s := range sample { - if s.Value.Kind() == metrics.KindBad { - // Just return, a slightly slower compilation is a tolerable outcome. - if logHeapTweaks { - fmt.Fprintf(os.Stderr, "GCAdjust: Regret unexpected KindBad for metric %s\n", s.Name) - } - return - } - } - - // Tinker with GOGC to make the heap grow rapidly at first. - currentGoal := sample[GOAL].Value.Uint64() // Believe this will be 4MByte or less, perhaps 512k - myGogc := 100 * requestedHeapGoal / currentGoal - if myGogc <= 150 { - return - } - - if logHeapTweaks { - sample := append([]metrics.Sample(nil), sample...) // avoid races with GC callback - AtExit(func() { - metrics.Read(sample) - goal := sample[GOAL].Value.Uint64() - count := sample[COUNT].Value.Uint64() - oldGogc := debug.SetGCPercent(100) - if oldGogc == 100 { - fmt.Fprintf(os.Stderr, "GCAdjust: AtExit goal %d gogc %d count %d maxprocs %d gcConcurrency %d\n", - goal, oldGogc, count, mp, gcConcurrency) - } else { - inUse := sample[ALLOCS].Value.Uint64() - sample[FREES].Value.Uint64() - overPct := 100 * (int(inUse) - int(requestedHeapGoal)) / int(requestedHeapGoal) - fmt.Fprintf(os.Stderr, "GCAdjust: AtExit goal %d gogc %d count %d maxprocs %d gcConcurrency %d overPct %d\n", - goal, oldGogc, count, mp, gcConcurrency, overPct) - - } - }) - } - - debug.SetGCPercent(int(myGogc)) - - adjustFunc := func() bool { - - metrics.Read(sample) - goal := sample[GOAL].Value.Uint64() - count := sample[COUNT].Value.Uint64() - - if goal <= requestedHeapGoal { // Stay the course - if logHeapTweaks { - fmt.Fprintf(os.Stderr, "GCAdjust: Reuse GOGC adjust, current goal %d, count is %d, current gogc %d\n", - goal, count, myGogc) - } - return true - } - - // Believe goal has been adjusted upwards, else it would be less-than-or-equal than requestedHeapGoal - calcLive := 100 * goal / (100 + myGogc) - - if 2*calcLive < requestedHeapGoal { // calcLive can exceed requestedHeapGoal! - myGogc = 100*requestedHeapGoal/calcLive - 100 - - if myGogc > 125 { - // Not done growing the heap. - oldGogc := debug.SetGCPercent(int(myGogc)) - - if logHeapTweaks { - // Check that the new goal looks right - inUse := sample[ALLOCS].Value.Uint64() - sample[FREES].Value.Uint64() - metrics.Read(sample) - newGoal := sample[GOAL].Value.Uint64() - pctOff := 100 * (int64(newGoal) - int64(requestedHeapGoal)) / int64(requestedHeapGoal) - // Check that the new goal is close to requested. 3% of make.bash fails this test. Why, TBD. - if pctOff < 2 { - fmt.Fprintf(os.Stderr, "GCAdjust: Retry GOGC adjust, current goal %d, count is %d, gogc was %d, is now %d, calcLive %d pctOff %d\n", - goal, count, oldGogc, myGogc, calcLive, pctOff) - } else { - // The GC is being annoying and not giving us the goal that we requested, say more to help understand when/why. - fmt.Fprintf(os.Stderr, "GCAdjust: Retry GOGC adjust, current goal %d, count is %d, gogc was %d, is now %d, calcLive %d pctOff %d inUse %d\n", - goal, count, oldGogc, myGogc, calcLive, pctOff, inUse) - } - } - return true - } - } - - // In this case we're done boosting GOGC, set it to 100 and don't set a new finalizer. - oldGogc := debug.SetGCPercent(100) - // inUse helps estimate how late the finalizer ran; at the instant the previous GC ended, - // it was (in theory) equal to the previous GC's heap goal. In a growing heap it is - // expected to grow to the new heap goal. - inUse := sample[ALLOCS].Value.Uint64() - sample[FREES].Value.Uint64() - overPct := 100 * (int(inUse) - int(requestedHeapGoal)) / int(requestedHeapGoal) - if logHeapTweaks { - fmt.Fprintf(os.Stderr, "GCAdjust: Reset GOGC adjust, old goal %d, count is %d, gogc was %d, calcLive %d inUse %d overPct %d\n", - goal, count, oldGogc, calcLive, inUse, overPct) - } - return false - } - - forEachGC(adjustFunc) -} diff --git a/src/cmd/compile/internal/base/debug.go b/src/cmd/compile/internal/base/debug.go index 9e8ab2f488bb4d..a4cbe724e88c2f 100644 --- a/src/cmd/compile/internal/base/debug.go +++ b/src/cmd/compile/internal/base/debug.go @@ -12,38 +12,47 @@ var Debug DebugFlags // DebugFlags defines the debugging configuration values (see var Debug). // Each struct field is a different value, named for the lower-case of the field name. // Each field must be an int or string and must have a `help` struct tag. +// Don't forget to note that concurrency is "ok" when it is, +// else the compiler will serialize for that flag. // // The -d option takes a comma-separated list of settings. // Each setting is name=value; for ints, name is short for name=1. type DebugFlags struct { AlignHot int `help:"enable hot block alignment (currently requires -pgo)" concurrent:"ok"` Append int `help:"print information about append compilation"` + AstDump string `help:"for specified function/method, dump AST/IR at interesting points in compilation, to file pkg.func.ast. Use leading ~ for regular expression match."` Checkptr int `help:"instrument unsafe pointer conversions\n0: instrumentation disabled\n1: conversions involving unsafe.Pointer are instrumented\n2: conversions to unsafe.Pointer force heap allocation" concurrent:"ok"` Closure int `help:"print information about closure compilation"` + CompressInstructions int `help:"use compressed instructions when possible (if supported by architecture)" concurrent:"ok"` Converthash string `help:"hash value for use in debugging changes to platform-dependent float-to-[u]int conversion" concurrent:"ok"` Defer int `help:"print information about defer compilation"` DisableNil int `help:"disable nil checks" concurrent:"ok"` DumpInlFuncProps string `help:"dump function properties from inl heuristics to specified file"` DumpInlCallSiteScores int `help:"dump scored callsites during inlining"` - InlScoreAdj string `help:"set inliner score adjustments (ex: -d=inlscoreadj=panicPathAdj:10/passConstToNestedIfAdj:-90)"` + InlScoreAdj string `help:"set inliner score adjustments (ex: -d=inlscoreadj=panicPathAdj:10/passConstToNestedIfAdj:-90)" concurrent:"ok"` InlBudgetSlack int `help:"amount to expand the initial inline budget when new inliner enabled. Defaults to 80 if option not set." concurrent:"ok"` DumpPtrs int `help:"show Node pointers values in dump output"` DwarfInl int `help:"print information about DWARF inlined function creation"` EscapeMutationsCalls int `help:"print extra escape analysis diagnostics about mutations and calls" concurrent:"ok"` EscapeDebug int `help:"print information about escape analysis and resulting optimizations" concurrent:"ok"` + EscapeAlias int `help:"print information about alias analysis" concurrent:"ok"` + EscapeAliasCheck int `help:"enable additional validation for alias analysis" concurrent:"ok"` Export int `help:"print export data"` FIPSHash string `help:"hash value for FIPS debugging" concurrent:"ok"` Fmahash string `help:"hash value for use in debugging platform-dependent multiply-add use" concurrent:"ok"` + FreeAppend int `help:"insert frees of append results when proven safe (0 disabled, 1 enabled, 2 enabled + log)" concurrent:"ok"` GCAdjust int `help:"log adjustments to GOGC" concurrent:"ok"` GCCheck int `help:"check heap/gc use by compiler" concurrent:"ok"` GCProg int `help:"print dump of GC programs"` + GCStart int `help:"specify \"starting\" compiler's heap size in MiB" concurrent:"ok"` Gossahash string `help:"hash value for use in debugging the compiler"` InlFuncsWithClosures int `help:"allow functions with closures to be inlined" concurrent:"ok"` InlStaticInit int `help:"allow static initialization of inlined calls" concurrent:"ok"` + InterfaceCycles int `help:"allow anonymous interface cycles" concurrent:"ok"` Libfuzzer int `help:"enable coverage instrumentation for libfuzzer"` LiteralAllocHash string `help:"hash value for use in debugging literal allocation optimizations" concurrent:"ok"` - LoopVar int `help:"shared (0, default), 1 (private loop variables), 2, private + log"` - LoopVarHash string `help:"for debugging changes in loop behavior. Overrides experiment and loopvar flag."` + LoopVar int `help:"shared (0), 1 (private loop variables, default), 2, private + log" concurrent:"ok"` + LoopVarHash string `help:"for debugging changes in loop behavior. Overrides experiment and loopvar flag." concurrent:"ok"` LocationLists int `help:"print information about DWARF location list creation"` MaxShapeLen int `help:"hash shape names longer than this threshold (default 500)" concurrent:"ok"` MergeLocals int `help:"merge together non-interfering local stack slots" concurrent:"ok"` @@ -59,10 +68,11 @@ type DebugFlags struct { Panic int `help:"show all compiler panics"` Reshape int `help:"print information about expression reshaping"` Shapify int `help:"print information about shaping recursive types"` + Simd int `help:"print information about simd analysis and code transformation" concurrent:"ok"` Slice int `help:"print information about slice compilation"` SoftFloat int `help:"force compiler to emit soft-float code" concurrent:"ok"` StaticCopy int `help:"print information about missed static copies" concurrent:"ok"` - SyncFrames int `help:"how many writer stack frames to include at sync points in unified export data"` + SyncFrames int `help:"how many writer stack frames to include at sync points in unified export data" concurrent:"ok"` TailCall int `help:"print information about tail calls"` TypeAssert int `help:"print information about type assertion inlining"` WB int `help:"print information about write barriers"` @@ -78,7 +88,7 @@ type DebugFlags struct { VariableMakeHash string `help:"hash value for debugging stack allocation of variable-sized make results" concurrent:"ok"` VariableMakeThreshold int `help:"threshold in bytes for possible stack allocation of variable-sized make results" concurrent:"ok"` WrapGlobalMapDbg int `help:"debug trace output for global map init wrapping"` - WrapGlobalMapCtl int `help:"global map init wrap control (0 => default, 1 => off, 2 => stress mode, no size cutoff)"` + WrapGlobalMapCtl int `help:"global map init wrap control (0 => default, 1 => off, 2 => stress mode, no size cutoff)" concurrent:"ok"` ZeroCopy int `help:"enable zero-copy string->[]byte conversions" concurrent:"ok"` ConcurrentOk bool // true if only concurrentOk flags seen diff --git a/src/cmd/compile/internal/base/flag.go b/src/cmd/compile/internal/base/flag.go index 1d211e0a2dd9f4..c8f1b2db30db6d 100644 --- a/src/cmd/compile/internal/base/flag.go +++ b/src/cmd/compile/internal/base/flag.go @@ -78,6 +78,7 @@ type CmdFlags struct { LowerR CountFlag "help:\"debug generated wrappers\"" LowerT bool "help:\"enable tracing for debugging the compiler\"" LowerW CountFlag "help:\"debug type checking\"" + LowerU CountFlag "help:\"emit unsorted warnings/errors\"" LowerV *bool "help:\"increase debug verbosity\"" // Special characters @@ -177,10 +178,12 @@ func ParseFlags() { Flag.WB = true Debug.ConcurrentOk = true + Debug.CompressInstructions = 1 Debug.MaxShapeLen = 500 Debug.AlignHot = 1 Debug.InlFuncsWithClosures = 1 Debug.InlStaticInit = 1 + Debug.FreeAppend = 1 Debug.PGOInline = 1 Debug.PGODevirtualize = 2 Debug.SyncFrames = -1 // disable sync markers by default @@ -299,6 +302,7 @@ func ParseFlags() { } parseSpectre(Flag.Spectre) // left as string for RecordFlags + Ctxt.CompressInstructions = Debug.CompressInstructions != 0 Ctxt.Flag_shared = Ctxt.Flag_dynlink || Ctxt.Flag_shared Ctxt.Flag_optimize = Flag.N == 0 Ctxt.Debugasm = int(Flag.S) @@ -471,7 +475,6 @@ func concurrentFlagOk() bool { Flag.E == 0 && Flag.K == 0 && Flag.L == 0 && - Flag.LowerH == 0 && Flag.LowerJ == 0 && Flag.LowerM == 0 && Flag.LowerR == 0 diff --git a/src/cmd/compile/internal/base/print.go b/src/cmd/compile/internal/base/print.go index 9e3348c1ecca89..10c47b43c40080 100644 --- a/src/cmd/compile/internal/base/print.go +++ b/src/cmd/compile/internal/base/print.go @@ -45,7 +45,7 @@ func SyntaxErrors() int { } // addErrorMsg adds a new errorMsg (which may be a warning) to errorMsgs. -func addErrorMsg(pos src.XPos, code errors.Code, format string, args ...interface{}) { +func addErrorMsg(pos src.XPos, code errors.Code, format string, args ...any) { msg := fmt.Sprintf(format, args...) // Only add the position if know the position. // See issue golang.org/issue/11361. @@ -83,7 +83,9 @@ func FlushErrors() { if len(errorMsgs) == 0 { return } - sort.Stable(byPos(errorMsgs)) + if Flag.LowerU == 0 { + sort.Stable(byPos(errorMsgs)) + } for i, err := range errorMsgs { if i == 0 || err.msg != errorMsgs[i-1].msg { fmt.Print(err.msg) @@ -108,12 +110,12 @@ func sameline(a, b src.XPos) bool { } // Errorf reports a formatted error at the current line. -func Errorf(format string, args ...interface{}) { +func Errorf(format string, args ...any) { ErrorfAt(Pos, 0, format, args...) } // ErrorfAt reports a formatted error message at pos. -func ErrorfAt(pos src.XPos, code errors.Code, format string, args ...interface{}) { +func ErrorfAt(pos src.XPos, code errors.Code, format string, args ...any) { msg := fmt.Sprintf(format, args...) if strings.HasPrefix(msg, "syntax error") { @@ -164,7 +166,7 @@ func UpdateErrorDot(line string, name, expr string) { // In general the Go compiler does NOT generate warnings, // so this should be used only when the user has opted in // to additional output by setting a particular flag. -func Warn(format string, args ...interface{}) { +func Warn(format string, args ...any) { WarnfAt(Pos, format, args...) } @@ -172,7 +174,7 @@ func Warn(format string, args ...interface{}) { // In general the Go compiler does NOT generate warnings, // so this should be used only when the user has opted in // to additional output by setting a particular flag. -func WarnfAt(pos src.XPos, format string, args ...interface{}) { +func WarnfAt(pos src.XPos, format string, args ...any) { addErrorMsg(pos, 0, format, args...) if Flag.LowerM != 0 { FlushErrors() @@ -191,7 +193,7 @@ func WarnfAt(pos src.XPos, format string, args ...interface{}) { // prints a stack trace. // // If -h has been specified, Fatalf panics to force the usual runtime info dump. -func Fatalf(format string, args ...interface{}) { +func Fatalf(format string, args ...any) { FatalfAt(Pos, format, args...) } @@ -209,7 +211,7 @@ var bugStack = counter.NewStack("compile/bug", 16) // 16 is arbitrary; used by g // prints a stack trace. // // If -h has been specified, FatalfAt panics to force the usual runtime info dump. -func FatalfAt(pos src.XPos, format string, args ...interface{}) { +func FatalfAt(pos src.XPos, format string, args ...any) { FlushErrors() bugStack.Inc() @@ -244,14 +246,14 @@ func Assert(b bool) { } // Assertf reports a fatal error with Fatalf, unless b is true. -func Assertf(b bool, format string, args ...interface{}) { +func Assertf(b bool, format string, args ...any) { if !b { Fatalf(format, args...) } } // AssertfAt reports a fatal error with FatalfAt, unless b is true. -func AssertfAt(b bool, pos src.XPos, format string, args ...interface{}) { +func AssertfAt(b bool, pos src.XPos, format string, args ...any) { if !b { FatalfAt(pos, format, args...) } diff --git a/src/cmd/compile/internal/base/startheap.go b/src/cmd/compile/internal/base/startheap.go new file mode 100644 index 00000000000000..1d2713efdbc3f9 --- /dev/null +++ b/src/cmd/compile/internal/base/startheap.go @@ -0,0 +1,272 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package base + +import ( + "fmt" + "os" + "runtime" + "runtime/debug" + "runtime/metrics" + "sync" +) + +// forEachGC calls fn each GC cycle until it returns false. +func forEachGC(fn func() bool) { + type T [32]byte // large enough to avoid runtime's tiny object allocator + var finalizer func(*T) + finalizer = func(p *T) { + + if fn() { + runtime.SetFinalizer(p, finalizer) + } + } + + finalizer(new(T)) +} + +// AdjustStartingHeap modifies GOGC so that GC should not occur until the heap +// grows to the requested size. This is intended but not promised, though it +// is true-mostly, depending on when the adjustment occurs and on the +// compiler's input and behavior. Once the live heap is approximately half +// this size, GOGC is reset to its value when AdjustStartingHeap was called; +// subsequent GCs may reduce the heap below the requested size, but this +// function does not affect that. +// +// logHeapTweaks (-d=gcadjust=1) enables logging of GOGC adjustment events. +// +// The temporarily requested GOGC is derated from what would be the "obvious" +// value necessary to hit the starting heap goal because the obvious +// (goal/live-1)*100 value seems to grow RSS a little more than it "should" +// (compared to GOMEMLIMIT, e.g.) and the assumption is that the GC's control +// algorithms are tuned for GOGC near 100, and not tuned for huge values of +// GOGC. Different derating factors apply for "lo" and "hi" values of GOGC; +// lo is below derateBreak, hi is above derateBreak. The derating factors, +// expressed as integer percentages, are derateLoPct and derateHiPct. +// 60-75 is an okay value for derateLoPct, 30-65 seems like a good value for +// derateHiPct, and 600 seems like a good value for derateBreak. If these +// are zero, defaults are used instead. +// +// NOTE: If you think this code would help startup time in your own +// application and you decide to use it, please benchmark first to see if it +// actually works for you (it may not: the Go compiler is not typical), and +// whatever the outcome, please leave a comment on bug #56546. This code +// uses supported interfaces, but depends more than we like on +// current+observed behavior of the garbage collector, so if many people need +// this feature, we should consider/propose a better way to accomplish it. +func AdjustStartingHeap(requestedHeapGoal, derateBreak, derateLoPct, derateHiPct uint64, logHeapTweaks bool) { + mp := runtime.GOMAXPROCS(0) + + const ( + SHgoal = "/gc/heap/goal:bytes" + SHcount = "/gc/cycles/total:gc-cycles" + SHallocs = "/gc/heap/allocs:bytes" + SHfrees = "/gc/heap/frees:bytes" + ) + + var sample = []metrics.Sample{{Name: SHgoal}, {Name: SHcount}, {Name: SHallocs}, {Name: SHfrees}} + + const ( + SH_GOAL = 0 + SH_COUNT = 1 + SH_ALLOCS = 2 + SH_FREES = 3 + + MB = 1_000_000 + ) + + // These particular magic numbers are designed to make the RSS footprint of -d=-gcstart=2000 + // resemble that of GOMEMLIMIT=2000MiB GOGC=10000 when building large projects + // (e.g. the Go compiler itself, and the microsoft's typescript AST package), + // with the further restriction that these magic numbers did a good job of reducing user-cpu + // for builds at either gcstart=2000 or gcstart=128. + // + // The benchmarking to obtain this was (a version of): + // + // for i in {1..50} ; do + // for what in std cmd/compile cmd/fix cmd/go github.com/microsoft/typescript-go/internal/ast ; do + // whatbase=`basename ${what}` + // for sh in 128 2000 ; do + // for br in 500 600 ; do + // for shlo in 65 70; do + // for shhi in 55 60 ; do + // benchcmd -n=2 ${whatbase} go build -a \ + // -gcflags=all=-d=gcstart=${sh},gcstartloderate=${shlo},gcstarthiderate=${shhi},gcstartbreak=${br} \ + // ${what} | tee -a startheap${sh}_${br}_${shhi}_${shlo}.bench + // done + // done + // done + // done + // done + // done + // + // benchcmd is "go install github.com/aclements/go-misc/benchcmd@latest" + + if derateBreak == 0 { + derateBreak = 600 + } + if derateLoPct == 0 { + derateLoPct = 70 + } + if derateHiPct == 0 { + derateHiPct = 55 + } + + gogcDerate := func(myGogc uint64) uint64 { + if myGogc < derateBreak { + return (myGogc * derateLoPct) / 100 + } + return (myGogc * derateHiPct) / 100 + } + + // Assumptions and observations of Go's garbage collector, as of Go 1.17-1.20: + + // - the initial heap goal is 4MiB, by fiat. It is possible for Go to start + // with a heap as small as 512k, so this may change in the future. + + // - except for the first heap goal, heap goal is a function of + // observed-live at the previous GC and current GOGC. After the first + // GC, adjusting GOGC immediately updates GOGC; before the first GC, + // adjusting GOGC does not modify goal (but the change takes effect after + // the first GC). + + // - the before/after first GC behavior is not guaranteed anywhere, it's + // just behavior, and it's a bad idea to rely on it. + + // - we don't know exactly when GC will run, even after we adjust GOGC; the + // first GC may not have happened yet, may have already happened, or may + // be currently in progress, and GCs can start for several reasons. + + // - forEachGC above will run the provided function at some delay after each + // GC's mark phase terminates; finalizers are run after marking as the + // spans containing finalizable objects are swept, driven by GC + // background activity and allocation demand. + + // - "live at last GC" is not available through the current metrics + // interface. Instead, live is estimated by knowing the adjusted value of + // GOGC and the new heap goal following a GC (this requires knowing that + // at least one GC has occurred): + // estLive = 100 * newGoal / (100 + currentGogc) + // this new value of GOGC + // newGogc = 100*requestedHeapGoal/estLive - 100 + // will result in the desired goal. The logging code checks that the + // resulting goal is correct. + + // There's a small risk that the finalizer will be slow to run after a GC + // that expands the goal to a huge value, and that this will lead to + // out-of-memory. This doesn't seem to happen; in experiments on a variety + // of machines with a variety of extra loads to disrupt scheduling, the + // worst overshoot observed was 50% past requestedHeapGoal. + + metrics.Read(sample) + for _, s := range sample { + if s.Value.Kind() == metrics.KindBad { + // Just return, a slightly slower compilation is a tolerable outcome. + if logHeapTweaks { + fmt.Fprintf(os.Stderr, "GCAdjust: Regret unexpected KindBad for metric %s\n", s.Name) + } + return + } + } + + // Tinker with GOGC to make the heap grow rapidly at first. + currentGoal := sample[SH_GOAL].Value.Uint64() // Believe this will be 4MByte or less, perhaps 512k + myGogc := 100 * requestedHeapGoal / currentGoal + myGogc = gogcDerate(myGogc) + if myGogc <= 125 { + return + } + + if logHeapTweaks { + sample := append([]metrics.Sample(nil), sample...) // avoid races with GC callback + AtExit(func() { + metrics.Read(sample) + goal := sample[SH_GOAL].Value.Uint64() + count := sample[SH_COUNT].Value.Uint64() + oldGogc := debug.SetGCPercent(100) + if oldGogc == 100 { + fmt.Fprintf(os.Stderr, "GCAdjust: AtExit goal %dMB gogc %d count %d maxprocs %d\n", + goal/MB, oldGogc, count, mp) + } else { + inUse := sample[SH_ALLOCS].Value.Uint64() - sample[SH_FREES].Value.Uint64() + overPct := 100 * (int(inUse) - int(requestedHeapGoal)) / int(requestedHeapGoal) + fmt.Fprintf(os.Stderr, "GCAdjust: AtExit goal %dMB gogc %d count %d maxprocs %d overPct %d\n", + goal/MB, oldGogc, count, mp, overPct) + + } + }) + } + + originalGOGC := debug.SetGCPercent(int(myGogc)) + + // forEachGC finalizers ought not overlap, but they could run in separate threads. + // This ought not matter, but just in case it bothers the/a race detector, + // use this mutex. + var forEachGCLock sync.Mutex + + adjustFunc := func() bool { + + forEachGCLock.Lock() + defer forEachGCLock.Unlock() + + metrics.Read(sample) + goal := sample[SH_GOAL].Value.Uint64() + count := sample[SH_COUNT].Value.Uint64() + + if goal <= requestedHeapGoal { // Stay the course + if logHeapTweaks { + fmt.Fprintf(os.Stderr, "GCAdjust: Reuse GOGC adjust, current goal %dMB, count is %d, current gogc %d\n", + goal/MB, count, myGogc) + } + return true + } + + // Believe goal has been adjusted upwards, else it would be less-than-or-equal to requestedHeapGoal + calcLive := 100 * goal / (100 + myGogc) + + if 2*calcLive < requestedHeapGoal { // calcLive can exceed requestedHeapGoal! + myGogc = 100*requestedHeapGoal/calcLive - 100 + myGogc = gogcDerate(myGogc) + + if myGogc > 125 { + // Not done growing the heap. + oldGogc := debug.SetGCPercent(int(myGogc)) + + if logHeapTweaks { + // Check that the new goal looks right + inUse := sample[SH_ALLOCS].Value.Uint64() - sample[SH_FREES].Value.Uint64() + metrics.Read(sample) + newGoal := sample[SH_GOAL].Value.Uint64() + pctOff := 100 * (int64(newGoal) - int64(requestedHeapGoal)) / int64(requestedHeapGoal) + // Check that the new goal is close to requested. 3% of make.bash fails this test. Why, TBD. + if pctOff < 2 { + fmt.Fprintf(os.Stderr, "GCAdjust: Retry GOGC adjust, current goal %dMB, count is %d, gogc was %d, is now %d, calcLive %dMB pctOff %d\n", + goal/MB, count, oldGogc, myGogc, calcLive/MB, pctOff) + } else { + // The GC is being annoying and not giving us the goal that we requested, say more to help understand when/why. + fmt.Fprintf(os.Stderr, "GCAdjust: Retry GOGC adjust, current goal %dMB, count is %d, gogc was %d, is now %d, calcLive %dMB pctOff %d inUse %dMB\n", + goal/MB, count, oldGogc, myGogc, calcLive/MB, pctOff, inUse/MB) + } + } + return true + } + } + + // In this case we're done boosting GOGC, set it to its original value and don't set a new finalizer. + oldGogc := debug.SetGCPercent(originalGOGC) + // inUse helps estimate how late the finalizer ran; at the instant the previous GC ended, + // it was (in theory) equal to the previous GC's heap goal. In a growing heap it is + // expected to grow to the new heap goal. + if logHeapTweaks { + inUse := sample[SH_ALLOCS].Value.Uint64() - sample[SH_FREES].Value.Uint64() + overPct := 100 * (int(inUse) - int(requestedHeapGoal)) / int(requestedHeapGoal) + fmt.Fprintf(os.Stderr, "GCAdjust: Reset GOGC adjust, old goal %dMB, count is %d, gogc was %d, gogc is now %d, calcLive %dMB inUse %dMB overPct %d\n", + goal/MB, count, oldGogc, originalGOGC, calcLive/MB, inUse/MB, overPct) + } + return false + } + + forEachGC(adjustFunc) +} diff --git a/src/cmd/compile/internal/base/timings.go b/src/cmd/compile/internal/base/timings.go index f48ac93699b816..cbcd4dc6f55b55 100644 --- a/src/cmd/compile/internal/base/timings.go +++ b/src/cmd/compile/internal/base/timings.go @@ -168,7 +168,7 @@ type lines [][]string func (lines *lines) add(label string, n int, dt, tot time.Duration, events []*event) { var line []string - add := func(format string, args ...interface{}) { + add := func(format string, args ...any) { line = append(line, fmt.Sprintf(format, args...)) } diff --git a/src/cmd/compile/internal/bitvec/bv.go b/src/cmd/compile/internal/bitvec/bv.go index 9214aa6cd05560..57a8237ab08224 100644 --- a/src/cmd/compile/internal/bitvec/bv.go +++ b/src/cmd/compile/internal/bitvec/bv.go @@ -8,7 +8,6 @@ import ( "math/bits" "cmd/compile/internal/base" - "cmd/internal/src" ) const ( @@ -34,12 +33,9 @@ type Bulk struct { nword int32 } -func NewBulk(nbit int32, count int32, pos src.XPos) Bulk { +func NewBulk(nbit int32, count int32) Bulk { nword := (nbit + wordBits - 1) / wordBits size := int64(nword) * int64(count) - if int64(int32(size*4)) != size*4 { - base.FatalfAt(pos, "NewBulk too big: nbit=%d count=%d nword=%d size=%d", nbit, count, nword, size) - } return Bulk{ words: make([]uint32, size), nbit: nbit, diff --git a/src/cmd/compile/internal/bloop/bloop.go b/src/cmd/compile/internal/bloop/bloop.go new file mode 100644 index 00000000000000..d5f001abf06ae1 --- /dev/null +++ b/src/cmd/compile/internal/bloop/bloop.go @@ -0,0 +1,366 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package bloop + +// This file contains support routines for keeping +// statements alive +// in such loops (example): +// +// for b.Loop() { +// var a, b int +// a = 5 +// b = 6 +// f(a, b) +// } +// +// The results of a, b and f(a, b) will be kept alive. +// +// Formally, the lhs (if they are [ir.Name]-s) of +// [ir.AssignStmt], [ir.AssignListStmt], +// [ir.AssignOpStmt], and the results of [ir.CallExpr] +// or its args if it doesn't return a value will be kept +// alive. +// +// The keep alive logic is implemented with as wrapping a +// runtime.KeepAlive around the Name. +// +// TODO: currently this is implemented with KeepAlive +// because it will prevent DSE and DCE which is probably +// what we want right now. And KeepAlive takes an ssa +// value instead of a symbol, which is easier to manage. +// But since KeepAlive's context was mainly in the runtime +// and GC, should we implement a new intrinsic that lowers +// to OpVarLive? Peeling out the symbols is a bit tricky +// and also VarLive seems to assume that there exists a +// VarDef on the same symbol that dominates it. + +import ( + "cmd/compile/internal/base" + "cmd/compile/internal/ir" + "cmd/compile/internal/typecheck" + "cmd/compile/internal/types" + "cmd/internal/src" +) + +// getNameFromNode tries to iteratively peel down the node to +// get the name. +func getNameFromNode(n ir.Node) *ir.Name { + // Tries to iteratively peel down the node to get the names. + for n != nil { + switch n.Op() { + case ir.ONAME: + // Found the name, stop the loop. + return n.(*ir.Name) + case ir.OSLICE, ir.OSLICE3: + n = n.(*ir.SliceExpr).X + case ir.ODOT: + n = n.(*ir.SelectorExpr).X + case ir.OCONV, ir.OCONVIFACE, ir.OCONVNOP: + n = n.(*ir.ConvExpr).X + case ir.OADDR: + n = n.(*ir.AddrExpr).X + case ir.ODOTPTR: + n = n.(*ir.SelectorExpr).X + case ir.OINDEX, ir.OINDEXMAP: + n = n.(*ir.IndexExpr).X + default: + n = nil + } + } + return nil +} + +// getAddressableNameFromNode is like getNameFromNode but returns nil if the node is not addressable. +func getAddressableNameFromNode(n ir.Node) *ir.Name { + if name := getNameFromNode(n); name != nil && ir.IsAddressable(name) { + return name + } + return nil +} + +// getKeepAliveNodes analyzes an IR node and returns a list of nodes that must be kept alive. +func getKeepAliveNodes(pos src.XPos, n ir.Node) ir.Nodes { + name := getAddressableNameFromNode(n) + if name != nil { + debugName(name, pos) + return ir.Nodes{name} + } else if deref, ok := n.(*ir.StarExpr); ok && deref != nil { + if base.Flag.LowerM > 1 { + base.WarnfAt(pos, "dereference will be kept alive") + } + return ir.Nodes{deref} + } else if base.Flag.LowerM > 1 { + base.WarnfAt(pos, "expr is unknown to bloop pass") + } + return nil +} + +// keepAliveAt returns a statement that is either curNode, or a +// block containing curNode followed by a call to runtime.KeepAlive for each +// node in ns. These calls ensure that nodes in ns will be live until +// after curNode's execution. +func keepAliveAt(ns ir.Nodes, curNode ir.Node) ir.Node { + if len(ns) == 0 { + return curNode + } + + pos := curNode.Pos() + calls := ir.Nodes{curNode} + for _, n := range ns { + if n == nil || n.Sym() == nil || n.Sym().IsBlank() { + continue + } + if !ir.IsAddressable(n) { + base.FatalfAt(n.Pos(), "keepAliveAt: node %v is not addressable", n) + } + arg := ir.NewConvExpr(pos, ir.OCONV, types.Types[types.TUNSAFEPTR], typecheck.NodAddr(n)) + callExpr := typecheck.Call(pos, typecheck.LookupRuntime("KeepAlive"), ir.Nodes{arg}, false).(*ir.CallExpr) + callExpr.IsCompilerVarLive = true + callExpr.NoInline = true + calls = append(calls, callExpr) + } + + return ir.NewBlockStmt(pos, calls) +} + +func debugName(name *ir.Name, pos src.XPos) { + if base.Flag.LowerM > 1 { + if name.Linksym() != nil { + base.WarnfAt(pos, "%s will be kept alive", name.Linksym().Name) + } else { + base.WarnfAt(pos, "expr will be kept alive") + } + } +} + +// preserveCallResults assigns the results of a call statement to temporary variables to ensure they remain alive. +func preserveCallResults(curFn *ir.Func, call *ir.CallExpr) ir.Node { + var ns ir.Nodes + lhs := make(ir.Nodes, call.Fun.Type().NumResults()) + for i, res := range call.Fun.Type().Results() { + tmp := typecheck.TempAt(call.Pos(), curFn, res.Type) + lhs[i] = tmp + ns = append(ns, tmp) + } + + if base.Flag.LowerM > 1 { + plural := "" + if call.Fun.Type().NumResults() > 1 { + plural = "s" + } + base.WarnfAt(call.Pos(), "function result%s will be kept alive", plural) + } + + assign := typecheck.AssignExpr(ir.NewAssignListStmt(call.Pos(), ir.OAS2, lhs, ir.Nodes{call})).(*ir.AssignListStmt) + assign.Def = true + for _, tmp := range lhs { + // Place temp declarations in the loop body to help escape analysis. + assign.PtrInit().Append(typecheck.Stmt(ir.NewDecl(assign.Pos(), ir.ODCL, tmp.(*ir.Name)))) + } + return keepAliveAt(ns, assign) +} + +// preserveCallArgs ensures the arguments of a call statement are kept alive by transforming them into temporaries if necessary. +func preserveCallArgs(curFn *ir.Func, call *ir.CallExpr) ir.Node { + var argTmps ir.Nodes + var names ir.Nodes + preserveTmp := func(pos src.XPos, n ir.Node) ir.Node { + tmp := typecheck.TempAt(pos, curFn, n.Type()) + assign := ir.NewAssignStmt(pos, tmp, n) + assign.Def = true + // Place temp declarations in the loop body to help escape analysis. + assign.PtrInit().Append(typecheck.Stmt(ir.NewDecl(assign.Pos(), ir.ODCL, tmp))) + argTmps = append(argTmps, typecheck.AssignExpr(assign)) + names = append(names, tmp) + if base.Flag.LowerM > 1 { + base.WarnfAt(call.Pos(), "function arg will be kept alive") + } + return tmp + } + for i, a := range call.Args { + if name := getAddressableNameFromNode(a); name != nil { + // If they are name, keep them alive directly. + debugName(name, call.Pos()) + names = append(names, name) + } else if a.Op() == ir.OSLICELIT { + // variadic args are encoded as slice literal. + s := a.(*ir.CompLitExpr) + var ns ir.Nodes + for i, elem := range s.List { + if name := getAddressableNameFromNode(elem); name != nil { + debugName(name, call.Pos()) + ns = append(ns, name) + } else { + // We need a temporary to save this arg. + s.List[i] = preserveTmp(elem.Pos(), elem) + } + } + names = append(names, ns...) + } else { + // expressions, we need to assign them to temps and change the original arg to reference them. + call.Args[i] = preserveTmp(call.Pos(), a) + } + } + if len(argTmps) > 0 { + argTmps = append(argTmps, call) + return keepAliveAt(names, ir.NewBlockStmt(call.Pos(), argTmps)) + } + return keepAliveAt(names, call) +} + +// preserveStmt transforms stmt so that any names defined/assigned within it +// are used after stmt's execution, preventing their dead code elimination +// and dead store elimination. The return value is the transformed statement. +func preserveStmt(curFn *ir.Func, stmt ir.Node) ir.Node { + switch n := stmt.(type) { + case *ir.AssignStmt: + // If the left hand side is blank, we need to assign it to a temp + // so that it can be kept alive. + if ir.IsBlank(n.X) { + tmp := typecheck.TempAt(n.Pos(), curFn, n.Y.Type()) + n.X = tmp + n.Def = true + n.PtrInit().Append(typecheck.Stmt(ir.NewDecl(n.Pos(), ir.ODCL, tmp))) + stmt = typecheck.AssignExpr(n) + n = stmt.(*ir.AssignStmt) + } + return keepAliveAt(getKeepAliveNodes(n.Pos(), n.X), n) + case *ir.AssignListStmt: + var ns ir.Nodes + hasBlank := false + for i, lhs := range n.Lhs { + if ir.IsBlank(lhs) { + // If the left hand side has blanks, we need to assign them to temps + // so that they can be kept alive. + var typ *types.Type + // AssignListStmt can have tuple or a list of expressions on the right hand side. + if len(n.Rhs) == 1 && n.Rhs[0].Type() != nil && + n.Rhs[0].Type().IsTuple() && + len(n.Lhs) == n.Rhs[0].Type().NumFields() { + typ = n.Rhs[0].Type().Field(i).Type + } else if len(n.Rhs) == len(n.Lhs) { + typ = n.Rhs[i].Type() + } else { + // Unrecognized shapes, skip? + base.WarnfAt(n.Pos(), "unrecognized shape for assign list stmt for blank assignment") + continue + } + tmp := typecheck.TempAt(n.Pos(), curFn, typ) + n.Lhs[i] = tmp + n.PtrInit().Append(typecheck.Stmt(ir.NewDecl(n.Pos(), ir.ODCL, tmp))) + hasBlank = true + } + ns = append(ns, getKeepAliveNodes(n.Pos(), n.Lhs[i])...) + } + if hasBlank { + // blank nodes are rewritten to temps, we need to typecheck the node again. + n.Def = true + stmt = typecheck.AssignExpr(n) + n = stmt.(*ir.AssignListStmt) + } + return keepAliveAt(ns, n) + case *ir.AssignOpStmt: + return keepAliveAt(getKeepAliveNodes(n.Pos(), n.X), n) + case *ir.CallExpr: + // The function's results are not assigned, preserve them. + if n.Fun != nil && n.Fun.Type() != nil && n.Fun.Type().NumResults() != 0 { + return preserveCallResults(curFn, n) + } + // This function doesn't return anything, keep its args alive. + return preserveCallArgs(curFn, n) + } + return stmt +} + +func preserveStmts(curFn *ir.Func, list ir.Nodes) { + for i := range list { + list[i] = preserveStmt(curFn, list[i]) + } +} + +// isTestingBLoop returns true if it matches the node as a +// testing.(*B).Loop. See issue #61515. +func isTestingBLoop(t ir.Node) bool { + if t.Op() != ir.OFOR { + return false + } + nFor, ok := t.(*ir.ForStmt) + if !ok || nFor.Cond == nil || nFor.Cond.Op() != ir.OCALLFUNC { + return false + } + n, ok := nFor.Cond.(*ir.CallExpr) + if !ok || n.Fun == nil || n.Fun.Op() != ir.OMETHEXPR { + return false + } + name := ir.MethodExprName(n.Fun) + if name == nil { + return false + } + if fSym := name.Sym(); fSym != nil && name.Class == ir.PFUNC && fSym.Pkg != nil && + fSym.Name == "(*B).Loop" && fSym.Pkg.Path == "testing" { + // Attempting to match a function call to testing.(*B).Loop + return true + } + return false +} + +type editor struct { + inBloop bool + curFn *ir.Func +} + +func (e editor) edit(n ir.Node) ir.Node { + e.inBloop = isTestingBLoop(n) || e.inBloop + // It's in bloop, mark the stmts with bodies. + ir.EditChildren(n, e.edit) + if e.inBloop { + switch n := n.(type) { + case *ir.ForStmt: + preserveStmts(e.curFn, n.Body) + case *ir.IfStmt: + preserveStmts(e.curFn, n.Body) + preserveStmts(e.curFn, n.Else) + case *ir.BlockStmt: + preserveStmts(e.curFn, n.List) + case *ir.CaseClause: + preserveStmts(e.curFn, n.List) + preserveStmts(e.curFn, n.Body) + case *ir.CommClause: + preserveStmts(e.curFn, n.Body) + case *ir.RangeStmt: + preserveStmts(e.curFn, n.Body) + } + } + return n +} + +// Walk performs a walk on all functions in the package +// if it imports testing and wrap the results of all qualified +// statements in a runtime.KeepAlive intrinsic call. See package +// doc for more details. +// +// for b.Loop() {...} +// +// loop's body. +func Walk(pkg *ir.Package) { + hasTesting := false + for _, i := range pkg.Imports { + if i.Path == "testing" { + hasTesting = true + break + } + } + if !hasTesting { + return + } + for _, fn := range pkg.Funcs { + e := editor{false, fn} + ir.EditChildren(fn, e.edit) + if ir.MatchAstDump(fn, "bloop") { + ir.AstDump(fn, "bloop, "+ir.FuncName(fn)) + } + } + +} diff --git a/src/cmd/compile/internal/compare/compare.go b/src/cmd/compile/internal/compare/compare.go index 638eb37a622109..11793fc85ba102 100644 --- a/src/cmd/compile/internal/compare/compare.go +++ b/src/cmd/compile/internal/compare/compare.go @@ -257,8 +257,8 @@ func EqStruct(t *types.Type, np, nq ir.Node) ([]ir.Node, bool) { func EqString(s, t ir.Node) (eqlen *ir.BinaryExpr, eqmem *ir.CallExpr) { s = typecheck.Conv(s, types.Types[types.TSTRING]) t = typecheck.Conv(t, types.Types[types.TSTRING]) - sptr := ir.NewUnaryExpr(base.Pos, ir.OSPTR, s) - tptr := ir.NewUnaryExpr(base.Pos, ir.OSPTR, t) + sptr := ir.NewConvExpr(base.Pos, ir.OCONVNOP, types.Types[types.TUNSAFEPTR], ir.NewUnaryExpr(base.Pos, ir.OSPTR, s)) + tptr := ir.NewConvExpr(base.Pos, ir.OCONVNOP, types.Types[types.TUNSAFEPTR], ir.NewUnaryExpr(base.Pos, ir.OSPTR, t)) slen := typecheck.Conv(ir.NewUnaryExpr(base.Pos, ir.OLEN, s), types.Types[types.TUINTPTR]) tlen := typecheck.Conv(ir.NewUnaryExpr(base.Pos, ir.OLEN, t), types.Types[types.TUINTPTR]) @@ -293,7 +293,7 @@ func EqString(s, t ir.Node) (eqlen *ir.BinaryExpr, eqmem *ir.CallExpr) { cmplen = tlen } - fn := typecheck.LookupRuntime("memequal", types.Types[types.TUINT8], types.Types[types.TUINT8]) + fn := typecheck.LookupRuntime("memequal") call := typecheck.Call(base.Pos, fn, []ir.Node{sptr, tptr, ir.Copy(cmplen)}, false).(*ir.CallExpr) cmp := ir.NewBinaryExpr(base.Pos, ir.OEQ, slen, tlen) diff --git a/src/cmd/compile/internal/deadlocals/deadlocals.go b/src/cmd/compile/internal/deadlocals/deadlocals.go index 238450416a9463..9eeb1fb379faa3 100644 --- a/src/cmd/compile/internal/deadlocals/deadlocals.go +++ b/src/cmd/compile/internal/deadlocals/deadlocals.go @@ -23,7 +23,11 @@ func Funcs(fns []*ir.Func) { zero := ir.NewBasicLit(base.AutogeneratedPos, types.Types[types.TINT], constant.MakeInt64(0)) for _, fn := range fns { + if fn.IsClosure() { + if ir.MatchAstDump(fn, "deadlocals closure") { + ir.AstDump(fn, "deadlocals closure skipped, "+ir.FuncName(fn)) + } continue } @@ -44,6 +48,14 @@ func Funcs(fns []*ir.Func) { *as.lhs = ir.BlankNode *as.rhs = zero } + if len(assigns) > 0 { + // k.Defn might be pointing at one of the + // assignments we're overwriting. + k.Defn = nil + } + } + if ir.MatchAstDump(fn, "deadlocals") { + ir.AstDump(fn, "deadLocals, "+ir.FuncName(fn)) } } } diff --git a/src/cmd/compile/internal/devirtualize/devirtualize.go b/src/cmd/compile/internal/devirtualize/devirtualize.go index cb4608a0246574..08af63c39e8465 100644 --- a/src/cmd/compile/internal/devirtualize/devirtualize.go +++ b/src/cmd/compile/internal/devirtualize/devirtualize.go @@ -131,7 +131,7 @@ func StaticCall(s *State, call *ir.CallExpr) { // type assertion that we make here would also have failed, but with a different // panic "pkg.Iface is nil, not *pkg.Impl", where previously we would get a nil panic. // We fix this, by introducing an additional nilcheck on the itab. - // Calling a method on an nil interface (in most cases) is a bug in a program, so it is fine + // Calling a method on a nil interface (in most cases) is a bug in a program, so it is fine // to devirtualize and further (possibly) inline them, even though we would never reach // the called function. dt.UseNilPanic = true @@ -182,6 +182,17 @@ const concreteTypeDebug = false // Returns nil when the concrete type could not be determined, or when there are multiple // (different) types assigned to an interface. func concreteType(s *State, n ir.Node) (typ *types.Type) { + if concreteTypeDebug { + base.Warn("concreteType(%v) - analyzing", n) + defer func() { + t := typ.String() + if typ == nil { + t = " (unknown static type)" + } + base.Warn("concreteType(%v) -> %v", n, t) + }() + } + typ = concreteType1(s, n, make(map[*ir.Name]struct{})) if typ == &noType { return nil @@ -197,7 +208,7 @@ var noType types.Type // concreteType1 analyzes the node n and returns its concrete type if it is statically known. // Otherwise, it returns a nil Type, indicating that a concrete type was not determined. -// When n is known to be statically nil or a self-assignment is detected, in returns a sentinel [noType] type instead. +// When n is known to be statically nil or a self-assignment is detected, it returns a sentinel [noType] type instead. func concreteType1(s *State, n ir.Node, seen map[*ir.Name]struct{}) (outT *types.Type) { nn := n // for debug messages @@ -207,6 +218,9 @@ func concreteType1(s *State, n ir.Node, seen map[*ir.Name]struct{}) (outT *types if outT != &noType { t = outT.String() } + if outT == nil { + t = " (unknown static type)" + } base.Warn("concreteType1(%v) -> %v", nn, t) }() } @@ -293,9 +307,22 @@ func concreteType1(s *State, n ir.Node, seen map[*ir.Name]struct{}) (outT *types continue } } - if t == nil || (typ != nil && !types.Identical(typ, t)) { - return nil + if t == nil { + return nil // unknown concrete type } + + // Methods are only declared on named types, and each named type + // is represented by a unique [*types.Type], thus pointer comparison + // is fine here. + // + // The only scenario where [types.IdenticalStrict] could help here is with + // unnamed struct types that embed another type (e.g. foo = struct { Impl }{}). + // However, such patterns are uncommon and not worth the additional complexity + // in the devirtualizer. + if typ != nil && typ != t { + return nil // assigned with a different type + } + typ = t } @@ -310,7 +337,7 @@ func concreteType1(s *State, n ir.Node, seen map[*ir.Name]struct{}) (outT *types // assignment can be one of: // - nil - assignment from an interface type. // - *types.Type - assignment from a concrete type (non-interface). -// - ir.Node - assignment from a ir.Node. +// - ir.Node - assignment from an ir.Node. // // In most cases assignment should be an [ir.Node], but in cases where we // do not follow the data-flow, we return either a concrete type (*types.Type) or a nil. @@ -560,8 +587,8 @@ func (s *State) analyze(nodes ir.Nodes) { assign(n.Key, nil) assign(n.Value, nil) } else { - // We will not reach here in case of an range-over-func, as it is - // rewrtten to function calls in the noder package. + // We will not reach here in case of a range-over-func, as it is + // rewritten to function calls in the noder package. base.FatalfAt(n.Pos(), "range over unexpected type %v", n.X.Type()) } case ir.OSWITCH: diff --git a/src/cmd/compile/internal/devirtualize/pgo.go b/src/cmd/compile/internal/devirtualize/pgo.go index a8980bb86b1547..5bb0454f8b5ee6 100644 --- a/src/cmd/compile/internal/devirtualize/pgo.go +++ b/src/cmd/compile/internal/devirtualize/pgo.go @@ -484,6 +484,7 @@ func condCall(curfn *ir.Func, pos src.XPos, cond ir.Node, thenCall, elseCall *ir res := ir.NewInlinedCallExpr(pos, body, retvars) res.SetType(thenCall.Type()) res.SetTypecheck(1) + res.Reshape = thenCall.Reshape return res } diff --git a/src/cmd/compile/internal/dwarfgen/dwarf.go b/src/cmd/compile/internal/dwarfgen/dwarf.go index 9d975e0bc1ac7d..3f654fabee7e97 100644 --- a/src/cmd/compile/internal/dwarfgen/dwarf.go +++ b/src/cmd/compile/internal/dwarfgen/dwarf.go @@ -93,7 +93,7 @@ func Info(ctxt *obj.Link, fnsym *obj.LSym, infosym *obj.LSym, curfn obj.Func) (s default: continue } - if !ssa.IsVarWantedForDebug(n) { + if !shouldEmitDwarfVar(n) { continue } apdecls = append(apdecls, n) @@ -178,18 +178,78 @@ func createDwarfVars(fnsym *obj.LSym, complexOK bool, fn *ir.Func, apDecls []*ir // Collect a raw list of DWARF vars. var vars []*dwarf.Var var decls []*ir.Name - var selected ir.NameSet - if base.Ctxt.Flag_locationlists && base.Ctxt.Flag_optimize && fn.DebugInfo != nil && complexOK { - decls, vars, selected = createComplexVars(fnsym, fn, closureVars) - } else if fn.ABI == obj.ABIInternal && base.Flag.N != 0 && complexOK { - decls, vars, selected = createABIVars(fnsym, fn, apDecls, closureVars) - } else { - decls, vars, selected = createSimpleVars(fnsym, apDecls, closureVars) - } + // Build a VarID lookup map for SSA debug info if available. + var debug *ssa.FuncDebug + var varIDMap map[*ir.Name]ssa.VarID if fn.DebugInfo != nil { - // Recover zero sized variables eliminated by the stackframe pass - for _, n := range fn.DebugInfo.(*ssa.FuncDebug).OptDcl { + debug = fn.DebugInfo.(*ssa.FuncDebug) + varIDMap = make(map[*ir.Name]ssa.VarID, len(debug.Vars)) + for i, n := range debug.Vars { + varIDMap[n] = ssa.VarID(i) + } + } + canUseComplex := complexOK && debug != nil + + // markVarSeen marks a variable and all its associated slot names as seen. + // This is needed because decomposed variables may have slots whose ir.Name + // differs from the variable itself (e.g., PAUTO vs PPARAMOUT for the same + // logical variable). Without this, the dcl loop could create duplicate + // conservative entries for names that are already covered by a complex var. + seen := make(map[*ir.Name]bool) + markVarSeen := func(n *ir.Name, varID ssa.VarID) { + seen[n] = true + if debug != nil && int(varID) < len(debug.VarSlots) { + for _, slot := range debug.VarSlots[varID] { + seen[debug.Slots[slot].N] = true + } + } + } + + // Unified loop: for each variable in apDecls, try createComplexVar + // (SSA debug info) first, then fall back to createSimpleVar. + for _, n := range apDecls { + if !shouldEmitDwarfVar(n) { + continue + } + if canUseComplex { + if vid, ok := varIDMap[n]; ok { + if dvar := createComplexVar(fnsym, fn, vid, closureVars); dvar != nil { + decls = append(decls, n) + vars = append(vars, dvar) + markVarSeen(n, vid) + continue + } + } + } + seen[n] = true + decls = append(decls, n) + vars = append(vars, createSimpleVar(fnsym, n, closureVars)) + } + + // Add SSA-tracked vars not in apDecls. + if canUseComplex { + for i, n := range debug.Vars { + if seen[n] { + continue + } + if !shouldEmitDwarfVar(n) { + continue + } + if dvar := createComplexVar(fnsym, fn, ssa.VarID(i), closureVars); dvar != nil { + decls = append(decls, n) + vars = append(vars, dvar) + markVarSeen(n, ssa.VarID(i)) + } + } + } + + // Recover zero-sized variables eliminated by the stackframe pass. + if debug != nil { + for _, n := range debug.OptDcl { + if seen[n] { + continue + } if n.Class != ir.PAUTO { continue } @@ -199,21 +259,23 @@ func createDwarfVars(fnsym *obj.LSym, complexOK bool, fn *ir.Func, apDecls []*ir vars = append(vars, createSimpleVar(fnsym, n, closureVars)) vars[len(vars)-1].StackOffset = 0 fnsym.Func().RecordAutoType(reflectdata.TypeLinksym(n.Type())) + seen[n] = true } } } + // For inlined functions or functions with register output params, + // collect additional declarations that may not be in apDecls. dcl := apDecls if fnsym.WasInlined() { dcl = preInliningDcls(fnsym) - } else { + } else if debug != nil { // The backend's stackframe pass prunes away entries from the // fn's Dcl list, including PARAMOUT nodes that correspond to // output params passed in registers. Add back in these // entries here so that we can process them properly during // DWARF-gen. See issue 48573 for more details. - debugInfo := fn.DebugInfo.(*ssa.FuncDebug) - for _, n := range debugInfo.RegOutputParams { + for _, n := range debug.RegOutputParams { if !ssa.IsVarWantedForDebug(n) { continue } @@ -224,83 +286,33 @@ func createDwarfVars(fnsym *obj.LSym, complexOK bool, fn *ir.Func, apDecls []*ir } } - // If optimization is enabled, the list above will typically be - // missing some of the original pre-optimization variables in the - // function (they may have been promoted to registers, folded into - // constants, dead-coded away, etc). Input arguments not eligible - // for SSA optimization are also missing. Here we add back in entries - // for selected missing vars. Note that the recipe below creates a - // conservative location. The idea here is that we want to - // communicate to the user that "yes, there is a variable named X - // in this function, but no, I don't have enough information to - // reliably report its contents." - // For non-SSA-able arguments, however, the correct information - // is known -- they have a single home on the stack. + // Process remaining variables not yet handled. For each variable, + // try createComplexVar first, then fall back to createSimpleVar + // for non-SSA-able params, or createConservativeVar for the rest. for _, n := range dcl { - if selected.Has(n) { + if seen[n] { continue } - c := n.Sym().Name[0] - if c == '.' || n.Type().IsUntyped() { + if !shouldEmitDwarfVar(n) { continue } + seen[n] = true + if canUseComplex { + if vid, ok := varIDMap[n]; ok { + if dvar := createComplexVar(fnsym, fn, vid, closureVars); dvar != nil { + decls = append(decls, n) + vars = append(vars, dvar) + continue + } + } + } if n.Class == ir.PPARAM && !ssa.CanSSA(n.Type()) { - // SSA-able args get location lists, and may move in and - // out of registers, so those are handled elsewhere. - // Autos and named output params seem to get handled - // with VARDEF, which creates location lists. - // Args not of SSA-able type are treated here; they - // are homed on the stack in a single place for the - // entire call. - vars = append(vars, createSimpleVar(fnsym, n, closureVars)) decls = append(decls, n) + vars = append(vars, createSimpleVar(fnsym, n, closureVars)) continue } - typename := dwarf.InfoPrefix + types.TypeSymName(n.Type()) decls = append(decls, n) - tag := dwarf.DW_TAG_variable - isReturnValue := (n.Class == ir.PPARAMOUT) - if n.Class == ir.PPARAM || n.Class == ir.PPARAMOUT { - tag = dwarf.DW_TAG_formal_parameter - } - inlIndex := 0 - if base.Flag.GenDwarfInl > 1 { - if n.InlFormal() || n.InlLocal() { - inlIndex = posInlIndex(n.Pos()) + 1 - if n.InlFormal() { - tag = dwarf.DW_TAG_formal_parameter - } - } - } - declpos := base.Ctxt.InnermostPos(n.Pos()) - dvar := &dwarf.Var{ - Name: n.Sym().Name, - IsReturnValue: isReturnValue, - Tag: tag, - WithLoclist: true, - StackOffset: int32(n.FrameOffset()), - Type: base.Ctxt.Lookup(typename), - DeclFile: declpos.RelFilename(), - DeclLine: declpos.RelLine(), - DeclCol: declpos.RelCol(), - InlIndex: int32(inlIndex), - ChildIndex: -1, - DictIndex: n.DictIndex, - ClosureOffset: closureOffset(n, closureVars), - } - if n.Esc() == ir.EscHeap { - if n.Heapaddr == nil { - base.Fatalf("invalid heap allocated var without Heapaddr") - } - debug := fn.DebugInfo.(*ssa.FuncDebug) - list := createHeapDerefLocationList(n, debug.EntryID) - dvar.PutLocationList = func(listSym, startPC dwarf.Sym) { - debug.PutLocationList(list, base.Ctxt, listSym.(*obj.LSym), startPC.(*obj.LSym)) - } - } - vars = append(vars, dvar) - // Record go type to ensure that it gets emitted by the linker. - fnsym.Func().RecordAutoType(reflectdata.TypeLinksym(n.Type())) + vars = append(vars, createConservativeVar(fnsym, fn, n, closureVars)) } // Sort decls and vars. @@ -309,6 +321,64 @@ func createDwarfVars(fnsym *obj.LSym, complexOK bool, fn *ir.Func, apDecls []*ir return decls, vars } +// createConservativeVar creates a DWARF variable with a conservative location +// description. This is used for variables that were optimized away or otherwise +// don't have precise location info. The intent is to communicate that "yes, +// there is a variable named X in this function, but no, I don't have enough +// information to reliably report its contents." +// For heap-escaped variables, a location list is created that describes +// dereferencing the pointer at the stack offset. +func createConservativeVar(fnsym *obj.LSym, fn *ir.Func, n *ir.Name, closureVars map[*ir.Name]int64) *dwarf.Var { + typename := dwarf.InfoPrefix + types.TypeSymName(n.Type()) + tag := dwarf.DW_TAG_variable + isReturnValue := (n.Class == ir.PPARAMOUT) + if n.Class == ir.PPARAM || n.Class == ir.PPARAMOUT { + tag = dwarf.DW_TAG_formal_parameter + } + inlIndex := 0 + if base.Flag.GenDwarfInl > 1 { + if n.InlFormal() || n.InlLocal() { + inlIndex = posInlIndex(n.Pos()) + 1 + if n.InlFormal() { + tag = dwarf.DW_TAG_formal_parameter + } + } + } + declpos := base.Ctxt.InnermostPos(n.Pos()) + dvar := &dwarf.Var{ + Name: n.Sym().Name, + IsReturnValue: isReturnValue, + Tag: tag, + WithLoclist: true, + StackOffset: int32(n.FrameOffset()), + Type: base.Ctxt.Lookup(typename), + DeclFile: declpos.RelFilename(), + DeclLine: declpos.RelLine(), + DeclCol: declpos.RelCol(), + InlIndex: int32(inlIndex), + ChildIndex: -1, + DictIndex: n.DictIndex, + ClosureOffset: closureOffset(n, closureVars), + } + if n.Esc() == ir.EscHeap && n.Heapaddr != nil { + // The variable was promoted to the heap and has a known heap + // address, so describe its location by dereferencing the pointer + // stored at its stack offset. A heap-escaped variable may have no + // Heapaddr if it was declared in unreachable code: escape analysis + // marks it as heap-allocated, but SSA generation skips the dead + // declaration and never allocates the address. In that case fall + // through and emit a conservative variable with no location list. + debug := fn.DebugInfo.(*ssa.FuncDebug) + list := createHeapDerefLocationList(n, debug.EntryID) + dvar.PutLocationList = func(listSym, startPC dwarf.Sym) { + debug.PutLocationList(list, base.Ctxt, listSym.(*obj.LSym), startPC.(*obj.LSym)) + } + } + // Record go type to ensure that it gets emitted by the linker. + fnsym.Func().RecordAutoType(reflectdata.TypeLinksym(n.Type())) + return dvar +} + // sortDeclsAndVars sorts the decl and dwarf var lists according to // parameter declaration order, so as to insure that when a subprogram // DIE is emitted, its parameter children appear in declaration order. @@ -368,10 +438,7 @@ func preInliningDcls(fnsym *obj.LSym) []*ir.Name { fn := base.Ctxt.DwFixups.GetPrecursorFunc(fnsym).(*ir.Func) var rdcl []*ir.Name for _, n := range fn.Inl.Dcl { - c := n.Sym().Name[0] - // Avoid reporting "_" parameters, since if there are more than - // one, it can result in a collision later on, as in #23179. - if n.Sym().Name == "_" || c == '.' || n.Type().IsUntyped() { + if n.Sym().Name[0] == '.' || !shouldEmitDwarfVarSafe(n) { continue } rdcl = append(rdcl, n) @@ -379,24 +446,6 @@ func preInliningDcls(fnsym *obj.LSym) []*ir.Name { return rdcl } -// createSimpleVars creates a DWARF entry for every variable declared in the -// function, claiming that they are permanently on the stack. -func createSimpleVars(fnsym *obj.LSym, apDecls []*ir.Name, closureVars map[*ir.Name]int64) ([]*ir.Name, []*dwarf.Var, ir.NameSet) { - var vars []*dwarf.Var - var decls []*ir.Name - var selected ir.NameSet - for _, n := range apDecls { - if ir.IsAutoTmp(n) { - continue - } - - decls = append(decls, n) - vars = append(vars, createSimpleVar(fnsym, n, closureVars)) - selected.Add(n) - } - return decls, vars, selected -} - func createSimpleVar(fnsym *obj.LSym, n *ir.Name, closureVars map[*ir.Name]int64) *dwarf.Var { var tag int var offs int64 @@ -457,63 +506,6 @@ func createSimpleVar(fnsym *obj.LSym, n *ir.Name, closureVars map[*ir.Name]int64 } } -// createABIVars creates DWARF variables for functions in which the -// register ABI is enabled but optimization is turned off. It uses a -// hybrid approach in which register-resident input params are -// captured with location lists, and all other vars use the "simple" -// strategy. -func createABIVars(fnsym *obj.LSym, fn *ir.Func, apDecls []*ir.Name, closureVars map[*ir.Name]int64) ([]*ir.Name, []*dwarf.Var, ir.NameSet) { - - // Invoke createComplexVars to generate dwarf vars for input parameters - // that are register-allocated according to the ABI rules. - decls, vars, selected := createComplexVars(fnsym, fn, closureVars) - - // Now fill in the remainder of the variables: input parameters - // that are not register-resident, output parameters, and local - // variables. - for _, n := range apDecls { - if ir.IsAutoTmp(n) { - continue - } - if _, ok := selected[n]; ok { - // already handled - continue - } - - decls = append(decls, n) - vars = append(vars, createSimpleVar(fnsym, n, closureVars)) - selected.Add(n) - } - - return decls, vars, selected -} - -// createComplexVars creates recomposed DWARF vars with location lists, -// suitable for describing optimized code. -func createComplexVars(fnsym *obj.LSym, fn *ir.Func, closureVars map[*ir.Name]int64) ([]*ir.Name, []*dwarf.Var, ir.NameSet) { - debugInfo := fn.DebugInfo.(*ssa.FuncDebug) - - // Produce a DWARF variable entry for each user variable. - var decls []*ir.Name - var vars []*dwarf.Var - var ssaVars ir.NameSet - - for varID, dvar := range debugInfo.Vars { - n := dvar - ssaVars.Add(n) - for _, slot := range debugInfo.VarSlots[varID] { - ssaVars.Add(debugInfo.Slots[slot].N) - } - - if dvar := createComplexVar(fnsym, fn, ssa.VarID(varID), closureVars); dvar != nil { - decls = append(decls, n) - vars = append(vars, dvar) - } - } - - return decls, vars, ssaVars -} - // createComplexVar builds a single DWARF variable entry and location list. func createComplexVar(fnsym *obj.LSym, fn *ir.Func, varID ssa.VarID, closureVars map[*ir.Name]int64) *dwarf.Var { debug := fn.DebugInfo.(*ssa.FuncDebug) @@ -573,7 +565,7 @@ func createComplexVar(fnsym *obj.LSym, fn *ir.Func, varID ssa.VarID, closureVars // createHeapDerefLocationList creates a location list for a heap-escaped variable // that describes "dereference pointer at stack offset" -func createHeapDerefLocationList(n *ir.Name, entryID ssa.ID) []byte { +func createHeapDerefLocationList(n *ir.Name, entryID ssa.ID) []ssa.LocListEntry { // Get the stack offset where the heap pointer is stored heapPtrOffset := n.Heapaddr.FrameOffset() if base.Ctxt.Arch.FixedFrameSize == 0 { @@ -584,14 +576,18 @@ func createHeapDerefLocationList(n *ir.Name, entryID ssa.ID) []byte { } // Create a location expression: DW_OP_fbreg DW_OP_deref - var locExpr []byte - var sizeIdx int - locExpr, sizeIdx = ssa.SetupLocList(base.Ctxt, entryID, locExpr, ssa.BlockStart.ID, ssa.FuncEnd.ID) - locExpr = append(locExpr, dwarf.DW_OP_fbreg) - locExpr = dwarf.AppendSleb128(locExpr, heapPtrOffset) - locExpr = append(locExpr, dwarf.DW_OP_deref) - base.Ctxt.Arch.ByteOrder.PutUint16(locExpr[sizeIdx:], uint16(len(locExpr)-sizeIdx-2)) - return locExpr + var expr []byte + expr = append(expr, dwarf.DW_OP_fbreg) + expr = dwarf.AppendSleb128(expr, heapPtrOffset) + expr = append(expr, dwarf.DW_OP_deref) + + return []ssa.LocListEntry{{ + StartBlock: entryID, + StartValue: ssa.BlockStart.ID, + EndBlock: entryID, + EndValue: ssa.FuncEnd.ID, + Expr: expr, + }} } // RecordFlags records the specified command-line flags to be placed @@ -667,6 +663,34 @@ func RecordPackageName() { s.P = []byte(types.LocalPkg.Name) } +// shouldEmitDwarfVar reports whether n should have a DWARF variable entry. +// This consolidates filtering that was previously spread across IR (AutoTemp), +// SSA (IsVarWantedForDebug), and dwarfgen (symbol name checks). +func shouldEmitDwarfVar(n *ir.Name) bool { + if ir.IsAutoTmp(n) { + return false + } + return shouldEmitDwarfVarSafe(n) +} + +// shouldEmitDwarfVarSafe is like shouldEmitDwarfVar but omits the ir.IsAutoTmp +// check, making it safe to call during parallel compilation on shared ir.Name +// nodes (e.g., in preInliningDcls). ir.IsAutoTmp reads the mutable flags bitset, +// which can race with other goroutines writing different flags during compilation. +// Auto temps have names starting with "." so callers must filter those separately. +func shouldEmitDwarfVarSafe(n *ir.Name) bool { + if !ssa.IsVarWantedForDebug(n) { + return false + } + if n.Sym().Name == "_" { + return false + } + if n.Type().IsUntyped() { + return false + } + return true +} + func closureOffset(n *ir.Name, closureVars map[*ir.Name]int64) int64 { return closureVars[n] } diff --git a/src/cmd/compile/internal/dwarfgen/marker.go b/src/cmd/compile/internal/dwarfgen/marker.go index ec6ce45a900bc0..dc622899d9c88e 100644 --- a/src/cmd/compile/internal/dwarfgen/marker.go +++ b/src/cmd/compile/internal/dwarfgen/marker.go @@ -20,7 +20,7 @@ type ScopeMarker struct { // checkPos validates the given position and returns the current scope. func (m *ScopeMarker) checkPos(pos src.XPos) ir.ScopeID { if !pos.IsKnown() { - base.Fatalf("unknown scope position") + base.Fatalf("unknown scope position, pos=%v", pos) } if len(m.marks) == 0 { diff --git a/src/cmd/compile/internal/escape/alias.go b/src/cmd/compile/internal/escape/alias.go new file mode 100644 index 00000000000000..f0351e8f671441 --- /dev/null +++ b/src/cmd/compile/internal/escape/alias.go @@ -0,0 +1,528 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package escape + +import ( + "cmd/compile/internal/base" + "cmd/compile/internal/ir" + "cmd/internal/src" + "fmt" + "maps" + "path/filepath" +) + +type aliasAnalysis struct { + // fn is the function being analyzed. + fn *ir.Func + + // candidateSlices are declared slices that + // start unaliased and might still be unaliased. + candidateSlices map[*ir.Name]candidateSlice + + // noAliasAppends are appends that have been + // proven to use an unaliased slice. + noAliasAppends []*ir.CallExpr + + // loops is a stack of observed loops, + // each with a list of candidate appends. + loops [][]candidateAppend + + // State for optional validation checking (doubleCheck mode): + processed map[ir.Node]int // count of times each node was processed, for doubleCheck mode + doubleCheck bool // whether to do doubleCheck mode +} + +// candidateSlice tracks information about a declared slice +// that might be unaliased. +type candidateSlice struct { + loopDepth int // depth of loop when slice was declared +} + +// candidateAppend tracks information about an OAPPEND that +// might be using an unaliased slice. +type candidateAppend struct { + s *ir.Name // the slice argument in 's = append(s, ...)' + call *ir.CallExpr // the append call +} + +// aliasAnalysis looks for specific patterns of slice usage and proves +// that certain appends are operating on non-aliased slices. +// +// This allows us to emit calls to free the backing arrays for certain +// non-aliased slices at runtime when we know the memory is logically dead. +// +// The analysis is conservative, giving up on any operation we do not +// explicitly understand. +func (aa *aliasAnalysis) analyze(fn *ir.Func) { + // Walk the function body to discover slice declarations, their uses, + // and any append that we can prove is using an unaliased slice. + // + // An example is: + // + // var s []T + // for _, v := range input { + // f() + // s = append(s, g(v)) // s cannot be aliased here + // h() + // } + // return s + // + // Here, we can prove that the append to s is operating on an unaliased slice, + // and that conclusion is unaffected by s later being returned and escaping. + // + // In contrast, in this example, the aliasing of s in the loop body means the + // append can be operating on an aliased slice, so we do not record s as unaliased: + // + // var s []T + // var alias []T + // for _, v := range input { + // s = append(s, v) // s is aliased on second pass through loop body + // alias = s + // } + // + // Arbitrary uses of s after an append do not affect the aliasing conclusion + // for that append, but only if the append cannot be revisited at execution time + // via a loop or goto. + // + // We track the loop depth when a slice was declared and verify all uses of a slice + // are non-aliasing until we return to that depth. In other words, we make sure + // we have processed any possible execution-time revisiting of the slice prior + // to making our final determination. + // + // This approach helps for example with nested loops, such as: + // + // var s []int + // for range 10 { + // for range 10 { + // s = append(s, 0) // s is proven as non-aliased here + // } + // } + // alias = s // both loops are complete + // + // Or in contrast: + // + // var s []int + // for range 10 { + // for range 10 { + // s = append(s, 0) // s is treated as aliased here + // } + // alias = s // aliased, and outermost loop cycles back + // } + // + // As we walk the function, we look for things like: + // + // 1. Slice declarations (currently supporting 'var s []T', 's := make([]T, ...)', + // and 's := []T{...}'). + // 2. Appends to a slice of the form 's = append(s, ...)'. + // 3. Other uses of the slice, which we treat as potential aliasing outside + // of a few known safe cases. + // 4. A start of a loop, which we track in a stack so that + // any uses of a slice within a loop body are treated as potential + // aliasing, including statements in the loop body after an append. + // Candidate appends are stored in the loop stack at the loop depth of their + // corresponding slice declaration (rather than the loop depth of the append), + // which essentially postpones a decision about the candidate append. + // 5. An end of a loop, which pops the loop stack and allows us to + // conclusively treat candidate appends from the loop body based + // on the loop depth of the slice declaration. + // + // Note that as we pop a candidate append at the end of a loop, we know + // its corresponding slice was unaliased throughout the loop being popped + // if the slice is still in the candidate slice map (without having been + // removed for potential aliasing), and we know we can make a final decision + // about a candidate append if we have returned to the loop depth + // where its slice was declared. In other words, there is no unanalyzed + // control flow that could take us back at execution-time to the + // candidate append in the now analyzed loop. This helps for example + // with nested loops, such as in our examples just above. + // + // We give up on a particular candidate slice if we see any use of it + // that we don't explicitly understand, and we give up on all of + // our candidate slices if we see any goto or label, which could be + // unstructured control flow. (TODO(thepudds): we remove the goto/label + // restriction in a subsequent CL.) + // + // Note that the intended use is to indicate that a slice is safe to pass + // to runtime.freegc, which currently requires that the passed pointer + // point to the base of its heap object. + // + // Therefore, we currently do not allow any re-slicing of the slice, though we could + // potentially allow s[0:x] or s[:x] or similar. (Slice expressions that alter + // the capacity might be possible to allow with freegc changes, though they are + // currently disallowed here like all slice expressions). + // + // TODO(thepudds): we could support the slice being used as non-escaping function call parameter + // but to do that, we need to verify any creation of specials via user code triggers an escape, + // or mail better runtime.freegc support for specials, or have a temporary compile-time solution + // for specials. (Currently, this analysis side-steps specials because any use of a slice + // that might cause a user-created special will cause it to be treated as aliased, and + // separately, runtime.freegc handles profiling-related specials). + + // Initialize. + aa.fn = fn + aa.candidateSlices = make(map[*ir.Name]candidateSlice) // slices that might be unaliased + + // doubleCheck controls whether we do a sanity check of our processing logic + // by counting each node visited in our main pass, and then comparing those counts + // against a simple walk at the end. The main intent is to help catch missing + // any nodes squirreled away in some spot we forgot to examine in our main pass. + aa.doubleCheck = base.Debug.EscapeAliasCheck > 0 + aa.processed = make(map[ir.Node]int) + + if base.Debug.EscapeAlias >= 2 { + aa.diag(fn.Pos(), fn, "====== starting func", "======") + } + + ir.DoChildren(fn, aa.visit) + + for _, call := range aa.noAliasAppends { + if base.Debug.EscapeAlias >= 1 { + base.WarnfAt(call.Pos(), "alias analysis: append using non-aliased slice: %v in func %v", + call, fn) + } + if base.Debug.FreeAppend > 0 { + call.AppendNoAlias = true + } + } + + if aa.doubleCheck { + doubleCheckProcessed(fn, aa.processed) + } +} + +func (aa *aliasAnalysis) visit(n ir.Node) bool { + if n == nil { + return false + } + + if base.Debug.EscapeAlias >= 3 { + fmt.Printf("%-25s alias analysis: visiting node: %12s %-18T %v\n", + fmtPosShort(n.Pos())+":", n.Op().String(), n, n) + } + + // As we visit nodes, we want to ensure we handle all children + // without missing any (through ignorance or future changes). + // We do this by counting nodes as we visit them or otherwise + // declare a node to be fully processed. + // + // In particular, we want to ensure we don't miss the use + // of a slice in some expression that might be an aliasing usage. + // + // When doubleCheck is enabled, we compare the counts + // accumulated in our analysis against counts from a trivial walk, + // failing if there is any mismatch. + // + // This call here counts that we have visited this node n + // via our main visit method. (In contrast, some nodes won't + // be visited by the main visit method, but instead will be + // manually marked via countProcessed when we believe we have fully + // dealt with the node). + aa.countProcessed(n) + + switch n.Op() { + case ir.ODCL: + decl := n.(*ir.Decl) + + if decl.X != nil && decl.X.Type().IsSlice() && decl.X.Class == ir.PAUTO { + s := decl.X + if _, ok := aa.candidateSlices[s]; ok { + base.FatalfAt(n.Pos(), "candidate slice already tracked as candidate: %v", s) + } + if base.Debug.EscapeAlias >= 2 { + aa.diag(n.Pos(), s, "adding candidate slice", "(loop depth: %d)", len(aa.loops)) + } + aa.candidateSlices[s] = candidateSlice{loopDepth: len(aa.loops)} + } + // No children aside from the declared ONAME. + aa.countProcessed(decl.X) + return false + + case ir.ONAME: + + // We are seeing a name we have not already handled in another case, + // so remove any corresponding candidate slice. + if n.Type().IsSlice() { + name := n.(*ir.Name) + _, ok := aa.candidateSlices[name] + if ok { + delete(aa.candidateSlices, name) + if base.Debug.EscapeAlias >= 2 { + aa.diag(n.Pos(), name, "removing candidate slice", "") + } + } + } + // No children. + return false + + case ir.OAS2: + n := n.(*ir.AssignListStmt) + aa.analyzeAssign(n, n.Lhs, n.Rhs) + return false + + case ir.OAS: + assign := n.(*ir.AssignStmt) + aa.analyzeAssign(n, []ir.Node{assign.X}, []ir.Node{assign.Y}) + return false + + case ir.OFOR, ir.ORANGE: + aa.visitList(n.Init()) + + if n.Op() == ir.ORANGE { + // TODO(thepudds): previously we visited this range expression + // in the switch just below, after pushing the loop. This current placement + // is more correct, but generate a test or find an example in stdlib or similar + // where it matters. (Our current tests do not complain.) + aa.visit(n.(*ir.RangeStmt).X) + } + + // Push a new loop. + aa.loops = append(aa.loops, nil) + + // Process the loop. + switch n.Op() { + case ir.OFOR: + forstmt := n.(*ir.ForStmt) + aa.visit(forstmt.Cond) + aa.visitList(forstmt.Body) + aa.visit(forstmt.Post) + case ir.ORANGE: + rangestmt := n.(*ir.RangeStmt) + aa.visit(rangestmt.Key) + aa.visit(rangestmt.Value) + aa.visitList(rangestmt.Body) + default: + base.Fatalf("loop not OFOR or ORANGE: %v", n) + } + + // Pop the loop. + var candidateAppends []candidateAppend + candidateAppends, aa.loops = aa.loops[len(aa.loops)-1], aa.loops[:len(aa.loops)-1] + for _, a := range candidateAppends { + // We are done with the loop, so we can validate any candidate appends + // that have not had their slice removed yet. We know a slice is unaliased + // throughout the loop if the slice is still in the candidate slice map. + if cs, ok := aa.candidateSlices[a.s]; ok { + if cs.loopDepth == len(aa.loops) { + // We've returned to the loop depth where the slice was declared and + // hence made it all the way through any loops that started after + // that declaration. + if base.Debug.EscapeAlias >= 2 { + aa.diag(n.Pos(), a.s, "proved non-aliased append", + "(completed loop, decl at depth: %d)", cs.loopDepth) + } + aa.noAliasAppends = append(aa.noAliasAppends, a.call) + } else if cs.loopDepth < len(aa.loops) { + if base.Debug.EscapeAlias >= 2 { + aa.diag(n.Pos(), a.s, "cannot prove non-aliased append", + "(completed loop, decl at depth: %d)", cs.loopDepth) + } + } else { + panic("impossible: candidate slice loopDepth > current loop depth") + } + } + } + return false + + case ir.OLEN, ir.OCAP: + n := n.(*ir.UnaryExpr) + if n.X.Op() == ir.ONAME { + // This does not disqualify a candidate slice. + aa.visitList(n.Init()) + aa.countProcessed(n.X) + } else { + ir.DoChildren(n, aa.visit) + } + return false + + case ir.OCLOSURE: + // Give up on all our in-progress slices. + closure := n.(*ir.ClosureExpr) + if base.Debug.EscapeAlias >= 2 { + aa.diag(n.Pos(), closure.Func, "clearing all in-progress slices due to OCLOSURE", + "(was %d in-progress slices)", len(aa.candidateSlices)) + } + clear(aa.candidateSlices) + return ir.DoChildren(n, aa.visit) + + case ir.OLABEL, ir.OGOTO: + // Give up on all our in-progress slices. + if base.Debug.EscapeAlias >= 2 { + aa.diag(n.Pos(), n, "clearing all in-progress slices due to label or goto", + "(was %d in-progress slices)", len(aa.candidateSlices)) + } + clear(aa.candidateSlices) + return false + + default: + return ir.DoChildren(n, aa.visit) + } +} + +func (aa *aliasAnalysis) visitList(nodes []ir.Node) { + for _, n := range nodes { + aa.visit(n) + } +} + +// analyzeAssign evaluates the assignment dsts... = srcs... +// +// assign is an *ir.AssignStmt or *ir.AssignListStmt. +func (aa *aliasAnalysis) analyzeAssign(assign ir.Node, dsts, srcs []ir.Node) { + aa.visitList(assign.Init()) + for i := range dsts { + dst := dsts[i] + src := srcs[i] + + if dst.Op() != ir.ONAME || !dst.Type().IsSlice() { + // Nothing for us to do aside from visiting the remaining children. + aa.visit(dst) + aa.visit(src) + continue + } + + // We have a slice being assigned to an ONAME. + + // Check for simple zero value assignments to an ONAME, which we ignore. + if src == nil { + aa.countProcessed(dst) + continue + } + + if base.Debug.EscapeAlias >= 4 { + srcfn := "" + if src.Op() == ir.ONAME { + srcfn = fmt.Sprintf("%v.", src.Name().Curfn) + } + aa.diag(assign.Pos(), assign, "visiting slice assignment", "%v.%v = %s%v (%s %T = %s %T)", + dst.Name().Curfn, dst, srcfn, src, dst.Op().String(), dst, src.Op().String(), src) + } + + // Now check what we have on the RHS. + switch src.Op() { + // Cases: + + // Check for s := make([]T, ...) or s := []T{...}, along with the '=' version + // of those which does not alias s as long as s is not used in the make. + // + // TODO(thepudds): we need to be sure that 's := []T{1,2,3}' does not end up backed by a + // global static. Ad-hoc testing indicates that example and similar seem to be + // stack allocated, but that was not exhaustive testing. We do have runtime.freegc + // able to throw if it finds a global static, but should test more. + // + // TODO(thepudds): could also possibly allow 's := append([]T(nil), ...)' + // and 's := append([]T{}, ...)'. + case ir.OMAKESLICE, ir.OSLICELIT: + name := dst.(*ir.Name) + if name.Class == ir.PAUTO { + if base.Debug.EscapeAlias > 1 { + aa.diag(assign.Pos(), assign, "assignment from make or slice literal", "") + } + // If this is Def=true, the ODCL in the init will causes this to be tracked + // as a candidate slice. We walk the init and RHS but avoid visiting the name + // in the LHS, which would remove the slice from the candidate list after it + // was just added. + aa.visit(src) + aa.countProcessed(name) + continue + } + + // Check for s = append(s, <...>). + case ir.OAPPEND: + s := dst.(*ir.Name) + call := src.(*ir.CallExpr) + if call.Args[0] == s { + // Matches s = append(s, <...>). + // First visit other arguments in case they use s. + aa.visitList(call.Args[1:]) + // Mark the call as processed, and s twice. + aa.countProcessed(s, call, s) + + // We have now examined all non-ONAME children of assign. + + // This is now the heart of the analysis. + // Check to see if this slice is a live candidate. + cs, ok := aa.candidateSlices[s] + if ok { + if cs.loopDepth == len(aa.loops) { + // No new loop has started after the declaration of s, + // so this is definitive. + if base.Debug.EscapeAlias >= 2 { + aa.diag(assign.Pos(), assign, "proved non-aliased append", + "(loop depth: %d, equals decl depth)", len(aa.loops)) + } + aa.noAliasAppends = append(aa.noAliasAppends, call) + } else if cs.loopDepth < len(aa.loops) { + // A new loop has started since the declaration of s, + // so we can't validate this append yet, but + // remember it in case we can validate it later when + // all loops using s are done. + aa.loops[cs.loopDepth] = append(aa.loops[cs.loopDepth], + candidateAppend{s: s, call: call}) + } else { + panic("impossible: candidate slice loopDepth > current loop depth") + } + } + continue + } + } // End of switch on src.Op(). + + // Reached bottom of the loop over assignments. + // If we get here, we need to visit the dst and src normally. + aa.visit(dst) + aa.visit(src) + } +} + +func (aa *aliasAnalysis) countProcessed(nodes ...ir.Node) { + if aa.doubleCheck { + for _, n := range nodes { + aa.processed[n]++ + } + } +} + +func (aa *aliasAnalysis) diag(pos src.XPos, n ir.Node, what string, format string, args ...any) { + fmt.Printf("%-25s alias analysis: %-30s %-20s %s\n", + fmtPosShort(pos)+":", + what+":", + fmt.Sprintf("%v", n), + fmt.Sprintf(format, args...)) +} + +// doubleCheckProcessed does a sanity check for missed nodes in our visit. +func doubleCheckProcessed(fn *ir.Func, processed map[ir.Node]int) { + // Do a trivial walk while counting the nodes + // to compare against the counts in processed. + + observed := make(map[ir.Node]int) + var walk func(n ir.Node) bool + walk = func(n ir.Node) bool { + observed[n]++ + return ir.DoChildren(n, walk) + } + ir.DoChildren(fn, walk) + + if !maps.Equal(processed, observed) { + // The most likely mistake might be something was missed while building processed, + // so print extra details in that direction. + for n, observedCount := range observed { + processedCount, ok := processed[n] + if processedCount != observedCount || !ok { + base.WarnfAt(n.Pos(), + "alias analysis: mismatch for %T: %v: processed %d times, observed %d times", + n, n, processedCount, observedCount) + } + } + base.FatalfAt(fn.Pos(), "alias analysis: mismatch in visited nodes") + } +} + +func fmtPosShort(xpos src.XPos) string { + // TODO(thepudds): I think I did this a simpler way a while ago? Or maybe add base.FmtPosShort + // or similar? Or maybe just use base.FmtPos and give up on nicely aligned log messages? + pos := base.Ctxt.PosTable.Pos(xpos) + shortLine := filepath.Base(pos.AbsFilename()) + ":" + pos.LineNumber() + return shortLine +} diff --git a/src/cmd/compile/internal/escape/assign.go b/src/cmd/compile/internal/escape/assign.go index 6af53886831a1e..27f13ca5aa2d39 100644 --- a/src/cmd/compile/internal/escape/assign.go +++ b/src/cmd/compile/internal/escape/assign.go @@ -50,6 +50,8 @@ func (e *escape) addr(n ir.Node) hole { case ir.OINDEXMAP: n := n.(*ir.IndexExpr) e.discard(n.X) + // Keys used in map assignments must escape. + // See "Hashing Pointers" doc in internal/runtime/maps/map.go. e.assignHeap(n.Index, "key of map put", n) } diff --git a/src/cmd/compile/internal/escape/call.go b/src/cmd/compile/internal/escape/call.go index f9351de975fdab..8619e6010b0baa 100644 --- a/src/cmd/compile/internal/escape/call.go +++ b/src/cmd/compile/internal/escape/call.go @@ -31,28 +31,39 @@ func (e *escape) call(ks []hole, call ir.Node) { call := call.(*ir.CallExpr) typecheck.AssertFixedCall(call) - // Pick out the function callee, if statically known. + // Pick out the function callee(s), if statically known. + // fns collects all known callees; for a single static callee + // it has one element. For unknown callees fns is nil. // - // TODO(mdempsky): Change fn from *ir.Name to *ir.Func, but some - // functions (e.g., runtime builtins, method wrappers, generated - // eq/hash functions) don't have it set. Investigate whether - // that's a concern. - var fn *ir.Name + // TODO(mdempsky): Change fns from []*ir.Name to []*ir.Func, + // but some functions (e.g., runtime builtins, method wrappers, + // generated eq/hash functions) don't have it set. Investigate + // whether that's a concern. + var fns []*ir.Name switch call.Op() { case ir.OCALLFUNC: - // TODO(thepudds): use an ir.ReassignOracle here. - v := ir.StaticValue(call.Fun) - fn = ir.StaticCalleeName(v) + ro := e.reassignOracle(e.curfn) + v := ro.StaticValue(call.Fun) + if fn := ir.StaticCalleeName(v); fn != nil { + fns = []*ir.Name{fn} + } else if name, ok := v.(*ir.Name); ok { + fns = resolveAssignedCallees(ro.FuncAssignments(name.Canonical())) + } } fntype := call.Fun.Type() - if fn != nil { - fntype = fn.Type() + if len(fns) == 1 { + fntype = fns[0].Type() } - if ks != nil && fn != nil && e.inMutualBatch(fn) { - for i, result := range fn.Type().Results() { - e.expr(ks[i], result.Nname.(*ir.Name)) + // Wire result flows for in-batch callees. + if ks != nil { + for _, f := range fns { + if e.inMutualBatch(f) { + for i, result := range f.Type().Results() { + e.expr(ks[i], result.Nname.(*ir.Name)) + } + } } } @@ -60,7 +71,7 @@ func (e *escape) call(ks []hole, call ir.Node) { if call.Op() == ir.OCALLFUNC { // Evaluate callee function expression. calleeK := e.discardHole() - if fn == nil { // unknown callee + if len(fns) == 0 { // unknown callee for _, k := range ks { if k.dst != &e.blankLoc { // The results flow somewhere, but we don't statically @@ -77,53 +88,48 @@ func (e *escape) call(ks []hole, call ir.Node) { recvArg = call.Fun.(*ir.SelectorExpr).X } - // argumentParam handles escape analysis of assigning a call - // argument to its corresponding parameter. - argumentParam := func(param *types.Field, arg ir.Node) { - e.rewriteArgument(arg, call, fn) - argument(e.tagHole(ks, fn, param), arg) - } - - // internal/abi.EscapeNonString forces its argument to be on - // the heap, if it contains a non-string pointer. - // This is used in hash/maphash.Comparable, where we cannot - // hash pointers to local variables, as the address of the - // local variable might change on stack growth. - // Strings are okay as the hash depends on only the content, - // not the pointer. - // This is also used in unique.clone, to model the data flow - // edge on the value with strings excluded, because strings - // are cloned (by content). - // The actual call we match is - // internal/abi.EscapeNonString[go.shape.T](dict, go.shape.T) - if fn != nil && fn.Sym().Pkg.Path == "internal/abi" && strings.HasPrefix(fn.Sym().Name, "EscapeNonString[") { - ps := fntype.Params() - if len(ps) == 2 && ps[1].Type.IsShape() { - if !hasNonStringPointers(ps[1].Type) { - argumentParam = func(param *types.Field, arg ir.Node) { - argument(e.discardHole(), arg) - } - } else { - argumentParam = func(param *types.Field, arg ir.Node) { - argument(e.heapHole(), arg) - } - } - } - } - args := call.Args - if recvParam := fntype.Recv(); recvParam != nil { + if fntype.Recv() != nil { if recvArg == nil { // Function call using method expression. Receiver argument is // at the front of the regular arguments list. recvArg, args = args[0], args[1:] } - - argumentParam(recvParam, recvArg) } - for i, param := range fntype.Params() { - argumentParam(param, args[i]) + if call.IsCompilerVarLive { + // Don't escape compiler-inserted KeepAlive. + if recvArg != nil { + argument(e.discardHole(), recvArg) + } + for _, arg := range args { + argument(e.discardHole(), arg) + } + } else if isEscapeNonString(fns, fntype) { + // internal/abi.EscapeNonString forces its argument to + // the heap if it contains a non-string pointer. This is + // used in hash/maphash.Comparable (where we cannot hash + // pointers to locals whose address may change on stack + // growth) and unique.clone (to model the data flow edge + // with strings excluded, because strings are cloned by + // content). The actual call we match is: + // internal/abi.EscapeNonString[go.shape.T](dict, go.shape.T) + k := e.heapHole() + if !hasNonStringPointers(fntype.Params()[1].Type) { + k = e.discardHole() + } + for _, arg := range args { + argument(k, arg) + } + } else { + if recvArg != nil { + e.rewriteArgument(recvArg, call, fns) + argument(e.mergedTagHole(ks, fns, -1, len(fntype.Params())), recvArg) + } + for i := range fntype.Params() { + e.rewriteArgument(args[i], call, fns) + argument(e.mergedTagHole(ks, fns, i, len(fntype.Params())), args[i]) + } } case ir.OINLCALL: @@ -198,6 +204,8 @@ func (e *escape) call(ks []hole, call ir.Node) { e.discard(arg) } e.discard(call.RType) + // Note: keys used in map deletes do not need to escape. + // See "Hashing Pointers" doc in internal/runtime/maps/map.go. case ir.OMIN, ir.OMAX: call := call.(*ir.CallExpr) @@ -262,12 +270,14 @@ func (e *escape) goDeferStmt(n *ir.GoDeferStmt) { } // rewriteArgument rewrites the argument arg of the given call expression. -// fn is the static callee function, if known. -func (e *escape) rewriteArgument(arg ir.Node, call *ir.CallExpr, fn *ir.Name) { - if fn == nil || fn.Func == nil { - return +// fns is the list of statically known callees, if any. +func (e *escape) rewriteArgument(arg ir.Node, call *ir.CallExpr, fns []*ir.Name) { + var pragma ir.PragmaFlag + for _, fn := range fns { + if fn.Func != nil { + pragma |= fn.Func.Pragma + } } - pragma := fn.Func.Pragma if pragma&(ir.UintptrKeepAlive|ir.UintptrEscapes) == 0 { return } @@ -354,6 +364,25 @@ func (e *escape) copyExpr(pos src.XPos, expr ir.Node, init *ir.Nodes) *ir.Name { return tmp } +func (e *escape) mergedTagHole(ks []hole, fns []*ir.Name, paramIdx int, nParams int) hole { + if len(fns) == 0 { + return e.heapHole() + } + holes := make([]hole, 0, len(fns)) + for _, f := range fns { + offset := nParams - len(f.Type().Params()) + j := paramIdx - offset + var p *types.Field + if j >= 0 { + p = f.Type().Params()[j] + } else { + p = f.Type().Recv() + } + holes = append(holes, e.tagHole(ks, f, p)) + } + return e.teeHole(holes...) +} + // tagHole returns a hole for evaluating an argument passed to param. // ks should contain the holes representing where the function // callee's results flows. fn is the statically-known callee function, @@ -397,6 +426,34 @@ func (e *escape) tagHole(ks []hole, fn *ir.Name, param *types.Field) hole { return e.teeHole(tagKs...) } +// resolveAssignedCallees resolves all assignment RHS values to static +// callee names, skipping zero-value assignments since nil panics on +// call and can't cause escape. +func resolveAssignedCallees(assigns []*ir.AssignStmt) []*ir.Name { + fns := make([]*ir.Name, 0, len(assigns)) + for _, as := range assigns { + if ir.IsZero(as.Y) { + continue // zero value panics on call; skip + } + callee := ir.StaticCalleeName(as.Y) + if callee == nil { + return nil + } + if callee.Func != nil && callee.Func.Pragma&(ir.UintptrKeepAlive|ir.UintptrEscapes) != 0 { + return nil + } + fns = append(fns, callee) + } + return fns +} + +func isEscapeNonString(fns []*ir.Name, fntype *types.Type) bool { + return len(fns) == 1 && + fns[0].Sym().Pkg.Path == "internal/abi" && + strings.HasPrefix(fns[0].Sym().Name, "EscapeNonString[") && + len(fntype.Params()) == 2 && fntype.Params()[1].Type.IsShape() +} + func hasNonStringPointers(t *types.Type) bool { if !t.HasPointers() { return false diff --git a/src/cmd/compile/internal/escape/escape.go b/src/cmd/compile/internal/escape/escape.go index 59250edfef0078..1c8e3824e9bc8e 100644 --- a/src/cmd/compile/internal/escape/escape.go +++ b/src/cmd/compile/internal/escape/escape.go @@ -8,6 +8,7 @@ import ( "fmt" "go/constant" "go/token" + "internal/goexperiment" "cmd/compile/internal/base" "cmd/compile/internal/ir" @@ -369,6 +370,21 @@ func (b *batch) finish(fns []*ir.Func) { } } } + + if goexperiment.RuntimeFreegc { + // Look for specific patterns of usage, such as appends + // to slices that we can prove are not aliased. + for _, fn := range fns { + a := aliasAnalysis{} + a.analyze(fn) + } + } + + for _, fn := range fns { + if ir.MatchAstDump(fn, "escape") { + ir.AstDump(fn, "escape, "+ir.FuncName(fn)) + } + } } // inMutualBatch reports whether function fn is in the batch of diff --git a/src/cmd/compile/internal/escape/expr.go b/src/cmd/compile/internal/escape/expr.go index 1521c2edd17605..468c4713f5b925 100644 --- a/src/cmd/compile/internal/escape/expr.go +++ b/src/cmd/compile/internal/escape/expr.go @@ -90,6 +90,8 @@ func (e *escape) exprSkipInit(k hole, n ir.Node) { case ir.OINDEXMAP: n := n.(*ir.IndexExpr) e.discard(n.X) + // Keys used in map lookups do not need to escape. + // See "Hashing Pointers" doc in internal/runtime/maps/map.go. e.discard(n.Index) case ir.OSLICE, ir.OSLICEARR, ir.OSLICE3, ir.OSLICE3ARR, ir.OSLICESTR: n := n.(*ir.SliceExpr) diff --git a/src/cmd/compile/internal/escape/leaks.go b/src/cmd/compile/internal/escape/leaks.go index 942f87d2a225ff..176bccd8470e7b 100644 --- a/src/cmd/compile/internal/escape/leaks.go +++ b/src/cmd/compile/internal/escape/leaks.go @@ -124,3 +124,21 @@ func parseLeaks(s string) leaks { copy(l[:], s[4:]) return l } + +func ParseLeaks(s string) leaks { + return parseLeaks(s) +} + +// Any reports whether the value flows anywhere at all. +func (l leaks) Any() bool { + // TODO: do mutator/callee matter? + if l.Heap() >= 0 || l.Mutator() >= 0 || l.Callee() >= 0 { + return true + } + for i := range numEscResults { + if l.Result(i) >= 0 { + return true + } + } + return false +} diff --git a/src/cmd/compile/internal/gc/compile.go b/src/cmd/compile/internal/gc/compile.go index 1a40df9a84ff04..3d8974ee299b71 100644 --- a/src/cmd/compile/internal/gc/compile.go +++ b/src/cmd/compile/internal/gc/compile.go @@ -29,7 +29,7 @@ var ( compilequeue []*ir.Func // functions waiting to be compiled ) -func enqueueFunc(fn *ir.Func) { +func enqueueFunc(fn *ir.Func, symABIs *ssagen.SymABIs) { if ir.CurFunc != nil { base.FatalfAt(fn.Pos(), "enqueueFunc %v inside %v", fn, ir.CurFunc) } @@ -49,22 +49,30 @@ func enqueueFunc(fn *ir.Func) { } if len(fn.Body) == 0 { - // Initialize ABI wrappers if necessary. - ir.InitLSym(fn, false) - types.CalcSize(fn.Type()) - a := ssagen.AbiForBodylessFuncStackMap(fn) - abiInfo := a.ABIAnalyzeFuncType(fn.Type()) // abiInfo has spill/home locations for wrapper - if fn.ABI == obj.ABI0 { - // The current args_stackmap generation assumes the function - // is ABI0, and only ABI0 assembly function can have a FUNCDATA - // reference to args_stackmap (see cmd/internal/obj/plist.go:Flushplist). - // So avoid introducing an args_stackmap if the func is not ABI0. - liveness.WriteFuncMap(fn, abiInfo) - - x := ssagen.EmitArgInfo(fn, abiInfo) - objw.Global(x, int32(len(x.P)), obj.RODATA|obj.LOCAL) + if ir.IsIntrinsicSym(fn.Sym()) && fn.Sym().Linkname == "" && !symABIs.HasDef(fn.Sym()) { + // Generate the function body for a bodyless intrinsic, in case it + // is used in a non-call context (e.g. as a function pointer). + // We skip functions defined in assembly, or has a linkname (which + // could be defined in another package). + ssagen.GenIntrinsicBody(fn) + } else { + // Initialize ABI wrappers if necessary. + ir.InitLSym(fn, false) + types.CalcSize(fn.Type()) + a := ssagen.AbiForBodylessFuncStackMap(fn) + abiInfo := a.ABIAnalyzeFuncType(fn.Type()) // abiInfo has spill/home locations for wrapper + if fn.ABI == obj.ABI0 { + // The current args_stackmap generation assumes the function + // is ABI0, and only ABI0 assembly function can have a FUNCDATA + // reference to args_stackmap (see cmd/internal/obj/plist.go:Flushplist). + // So avoid introducing an args_stackmap if the func is not ABI0. + liveness.WriteFuncMap(fn, abiInfo) + + x := ssagen.EmitArgInfo(fn, abiInfo) + objw.Global(x, int32(len(x.P)), obj.RODATA|obj.LOCAL) + } + return } - return } errorsBefore := base.Errors() @@ -113,6 +121,9 @@ func prepareFunc(fn *ir.Func) { ir.CurFunc = fn walk.Walk(fn) + if ir.MatchAstDump(fn, "walk") { + ir.AstDump(fn, "walk, "+ir.FuncName(fn)) + } ir.CurFunc = nil // enforce no further uses of CurFunc base.Ctxt.DwTextCount++ @@ -134,73 +145,47 @@ func compileFunctions(profile *pgoir.Profile) { // Compile the longest functions first, // since they're most likely to be the slowest. // This helps avoid stragglers. + // Since we remove from the end of the slice queue, + // that means shortest to longest. slices.SortFunc(compilequeue, func(a, b *ir.Func) int { - return cmp.Compare(len(b.Body), len(a.Body)) + return cmp.Compare(len(a.Body), len(b.Body)) }) } - // By default, we perform work right away on the current goroutine - // as the solo worker. - queue := func(work func(int)) { - work(0) - } + var mu sync.Mutex + var wg sync.WaitGroup + mu.Lock() - if nWorkers := base.Flag.LowerC; nWorkers > 1 { - // For concurrent builds, we allow the work queue - // to grow arbitrarily large, but only nWorkers work items - // can be running concurrently. - workq := make(chan func(int)) - done := make(chan int) + for workerId := range base.Flag.LowerC { + // TODO: replace with wg.Go when the oldest bootstrap has it. + // With the current policy, that'd be go1.27. + wg.Add(1) go func() { - ids := make([]int, nWorkers) - for i := range ids { - ids[i] = i - } - var pending []func(int) + defer wg.Done() + var closures []*ir.Func for { - select { - case work := <-workq: - pending = append(pending, work) - case id := <-done: - ids = append(ids, id) - } - for len(pending) > 0 && len(ids) > 0 { - work := pending[len(pending)-1] - id := ids[len(ids)-1] - pending = pending[:len(pending)-1] - ids = ids[:len(ids)-1] - go func() { - work(id) - done <- id - }() + mu.Lock() + compilequeue = append(compilequeue, closures...) + remaining := len(compilequeue) + if remaining == 0 { + mu.Unlock() + return } + fn := compilequeue[len(compilequeue)-1] + compilequeue = compilequeue[:len(compilequeue)-1] + mu.Unlock() + ssagen.Compile(fn, workerId, profile) + closures = fn.Closures } }() - queue = func(work func(int)) { - workq <- work - } - } - - var wg sync.WaitGroup - var compile func([]*ir.Func) - compile = func(fns []*ir.Func) { - wg.Add(len(fns)) - for _, fn := range fns { - fn := fn - queue(func(worker int) { - ssagen.Compile(fn, worker, profile) - compile(fn.Closures) - wg.Done() - }) - } } types.CalcSizeDisabled = true // not safe to calculate sizes concurrently base.Ctxt.InParallel = true - compile(compilequeue) - compilequeue = nil + mu.Unlock() wg.Wait() + compilequeue = nil base.Ctxt.InParallel = false types.CalcSizeDisabled = false diff --git a/src/cmd/compile/internal/gc/main.go b/src/cmd/compile/internal/gc/main.go index 42e2afaee4fc24..2b8ecda9d16c0f 100644 --- a/src/cmd/compile/internal/gc/main.go +++ b/src/cmd/compile/internal/gc/main.go @@ -8,6 +8,7 @@ import ( "bufio" "bytes" "cmd/compile/internal/base" + "cmd/compile/internal/bloop" "cmd/compile/internal/coverage" "cmd/compile/internal/deadlocals" "cmd/compile/internal/dwarfgen" @@ -22,6 +23,7 @@ import ( "cmd/compile/internal/pkginit" "cmd/compile/internal/reflectdata" "cmd/compile/internal/rttype" + "cmd/compile/internal/slice" "cmd/compile/internal/ssa" "cmd/compile/internal/ssagen" "cmd/compile/internal/staticinit" @@ -45,6 +47,8 @@ import ( // already been some compiler errors). It may also be invoked from the explicit panic in // hcrash(), in which case, we pass the panic on through. func handlePanic() { + ir.CloseHTMLWriters() + noder.CloseHTMLWriters() if err := recover(); err != nil { if err == "-h" { // Force real panic now with -h option (hcrash) - the error @@ -81,10 +85,13 @@ func Main(archInit func(*ssagen.ArchInfo)) { base.DebugSSA = ssa.PhaseOption base.ParseFlags() - if os.Getenv("GOGC") == "" { // GOGC set disables starting heap adjustment - // More processors will use more heap, but assume that more memory is available. - // So 1 processor -> 40MB, 4 -> 64MB, 12 -> 128MB - base.AdjustStartingHeap(uint64(32+8*base.Flag.LowerC) << 20) + if flagGCStart := base.Debug.GCStart; flagGCStart > 0 || // explicit flags overrides environment variable disable of GC boost + os.Getenv("GOGC") == "" && os.Getenv("GOMEMLIMIT") == "" && base.Flag.LowerC != 1 { // explicit GC knobs or no concurrency implies default heap + startHeapMB := int64(128) + if flagGCStart > 0 { + startHeapMB = int64(flagGCStart) + } + base.AdjustStartingHeap(uint64(startHeapMB)<<20, 0, 0, 0, base.Debug.GCAdjust == 1) } types.LocalPkg = types.NewPkg(base.Ctxt.Pkgpath, "") @@ -186,9 +193,9 @@ func Main(archInit func(*ssagen.ArchInfo)) { ir.EscFmt = escape.Fmt ir.IsIntrinsicCall = ssagen.IsIntrinsicCall + ir.IsIntrinsicSym = ssagen.IsIntrinsicSym inline.SSADumpInline = ssagen.DumpInline ssagen.InitEnv() - ssagen.InitTables() types.PtrSize = ssagen.Arch.LinkArch.PtrSize types.RegSize = ssagen.Arch.LinkArch.RegSize @@ -202,6 +209,11 @@ func Main(archInit func(*ssagen.ArchInfo)) { typecheck.InitRuntime() rttype.Init() + // Some intrinsics (notably, the simd intrinsics) mention + // types "eagerly", thus ssagen must be initialized AFTER + // the type system is ready. + ssagen.InitTables() + // Parse and typecheck input. noder.LoadPackage(flag.Args()) @@ -233,10 +245,25 @@ func Main(archInit func(*ssagen.ArchInfo)) { } } + for _, fn := range typecheck.Target.Funcs { + if ir.MatchAstDump(fn, "start") { + ir.AstDump(fn, "start, "+ir.FuncName(fn)) + } + } + + // Apply bloop markings. + bloop.Walk(typecheck.Target) + // Interleaved devirtualization and inlining. base.Timer.Start("fe", "devirtualize-and-inline") interleaved.DevirtualizeAndInlinePackage(typecheck.Target, profile) + for _, fn := range typecheck.Target.Funcs { + if ir.MatchAstDump(fn, "devirtualize-and-inline") { + ir.AstDump(fn, "devirtualize-and-inline, "+ir.FuncName(fn)) + } + } + noder.MakeWrappers(typecheck.Target) // must happen after inlining // Get variable capture right in for loops. @@ -266,6 +293,8 @@ func Main(archInit func(*ssagen.ArchInfo)) { base.Timer.Start("fe", "escapes") escape.Funcs(typecheck.Target.Funcs) + slice.Funcs(typecheck.Target.Funcs) + loopvar.LogTransformations(transformed) // Collect information for go:nowritebarrierrec @@ -302,7 +331,7 @@ func Main(archInit func(*ssagen.ArchInfo)) { } if nextFunc < len(typecheck.Target.Funcs) { - enqueueFunc(typecheck.Target.Funcs[nextFunc]) + enqueueFunc(typecheck.Target.Funcs[nextFunc], symABIs) nextFunc++ continue } diff --git a/src/cmd/compile/internal/importer/gcimporter_test.go b/src/cmd/compile/internal/importer/gcimporter_test.go index 11e4ee6b583b6a..e81a71f266eb90 100644 --- a/src/cmd/compile/internal/importer/gcimporter_test.go +++ b/src/cmd/compile/internal/importer/gcimporter_test.go @@ -720,3 +720,71 @@ var _ issue63285.A[issue63285.B[any]] t.Errorf("Check failed: %v", err) } } + +func TestGenMeth(t *testing.T) { + testenv.MustHaveGoBuild(t) + + // This package only handles gc export data. + if runtime.Compiler != "gc" { + t.Skipf("gc-built packages not available (compiler = %s)", runtime.Compiler) + } + + tmpdir := t.TempDir() + testoutdir := filepath.Join(tmpdir, "testdata") + if err := os.Mkdir(testoutdir, 0700); err != nil { + t.Fatalf("making output dir: %v", err) + } + + compile(t, "testdata", "genmeth.go", testoutdir, nil) + + genmeth, err := Import(make(map[string]*types2.Package), "./testdata/genmeth", tmpdir, nil) + if err != nil { + t.Fatal(err) + } + + check := func(pkgname, src string, imports importMap) (*types2.Package, error) { + f, err := syntax.Parse(syntax.NewFileBase(pkgname), strings.NewReader(src), nil, nil, 0) + if err != nil { + return nil, err + } + config := &types2.Config{ + Importer: imports, + } + return config.Check(pkgname, []*syntax.File{f}, nil) + } + + const pSrc = `package p + +import "genmeth" + +func _() { + var ex func(int) genmeth.List[int] + var fl func(genmeth.List[int]) genmeth.List[int] + + var l genmeth.List[int] + l = l.Map(ex).FlatMap(fl) + + var bl genmeth.BiList[int, any] + bl = bl.MapKeys(ex).Flip().FlatMapValues(fl).Flip() + + var id func(int) int + + var op genmeth.Option[int] + var _ int = op.MapIfPresent(id).Get() + + var ol genmeth.OrderedList[int] + var _ int = ol.Min().Get() + + var b genmeth.Box[int] + b.Set(42) + var _ int = b.Get() +} +` + + importer := importMap{ + "genmeth": genmeth, + } + if _, err := check("p", pSrc, importer); err != nil { + t.Errorf("Check failed: %v", err) + } +} diff --git a/src/cmd/compile/internal/importer/testdata/genmeth.go b/src/cmd/compile/internal/importer/testdata/genmeth.go new file mode 100644 index 00000000000000..0b5aa7e5a35762 --- /dev/null +++ b/src/cmd/compile/internal/importer/testdata/genmeth.go @@ -0,0 +1,49 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// This file is used to generate an object file which +// serves as test file for gcimporter_test.go. +// +// Function bodies are never read, so panics are used +// for brevity. Struct contents are also never filled +// in. + +package genmeth + +// monads +type Either[A, B any] struct {} + +func (Either[A, B]) A() A { panic(42) } +func (Either[A, B]) B() B { panic(42) } + +type Option[T any] struct {} + +func (Option[T]) Get() T { panic(42) } +func (Option[T]) GetOrDefault[U any](u U) Either[T, U] { panic(42) } +func (Option[T]) MapIfPresent[U any](f func(T) U) Option[U] { panic(42) } + +// pointer receiver +type Box[P any] struct {} + +func (*Box[P]) Get() P { panic(42) } +func (*Box[P]) Set(p P) { panic(42) } + +// streaming +type List[E any] []E +func (List[E]) Map[R any](f func(E) R) List[R] { panic(42) } +func (List[E]) FlatMap[R any](f func(E) List[R]) List[R] { panic(42) } +func (List[E1]) Zip[E2, R any](l List[E2], f func(E1, E2) R) List[R] { panic(42) } + +type Pair[A, B any] struct {} +type BiList[A, B any] List[Pair[A, B]] + +func (BiList[A, B]) Flip() BiList[B, A] { panic(42) } +func (BiList[A, B]) MapKeys[R any](f func(A) R) BiList[R, B] { panic(42) } +func (BiList[A, B]) MapValues[R any](f func(B) R) BiList[A, R] { panic(42) } +func (BiList[A, B]) FlatMapValues[R any](f func(B) List[R]) BiList[A, R] { panic(42) } +func (BiList[A, B]) MapEntries[K, V any](f func(Pair[A, B]) Pair[K, V]) BiList[K, V] { panic(42) } + +type OrderedList[E comparable] []E +func (OrderedList[E]) Min() Option[E] { panic(42) } +func (OrderedList[E]) Max() Option[E] { panic(42) } diff --git a/src/cmd/compile/internal/importer/ureader.go b/src/cmd/compile/internal/importer/ureader.go index f6df56b70e665c..fbe275be04c62b 100644 --- a/src/cmd/compile/internal/importer/ureader.go +++ b/src/cmd/compile/internal/importer/ureader.go @@ -6,6 +6,9 @@ package importer import ( + "cmp" + "slices" + "cmd/compile/internal/base" "cmd/compile/internal/syntax" "cmd/compile/internal/types2" @@ -72,8 +75,10 @@ type reader struct { } type readerDict struct { - bounds []typeInfo + rtbounds []typeInfo + rtparams []*types2.TypeParam + tbounds []typeInfo tparams []*types2.TypeParam derived []derivedInfo @@ -262,7 +267,11 @@ func (r *reader) doTyp() (res types2.Type) { return name.Type() case pkgbits.TypeTypeParam: - return r.dict.tparams[r.Len()] + n := r.Len() + if n < len(r.dict.rtbounds) { + return r.dict.rtparams[n] + } + return r.dict.tparams[n-len(r.dict.rtbounds)] case pkgbits.TypeArray: len := int64(r.Uint64()) @@ -421,7 +430,7 @@ func (pr *pkgReader) objIdx(idx pkgbits.Index) (*types2.Package, string) { pos := r.pos() var tparams []*types2.TypeParam if r.Version().Has(pkgbits.AliasTypeParamNames) { - tparams = r.typeParamNames(false) + tparams = r.typeParamNames(false, false) } typ := r.typ() return newAliasTypeName(pr.enableAlias, pos, objPkg, objName, typ, tparams) @@ -434,7 +443,10 @@ func (pr *pkgReader) objIdx(idx pkgbits.Index) (*types2.Package, string) { case pkgbits.ObjFunc: pos := r.pos() - tparams := r.typeParamNames(false) + if r.Version().Has(pkgbits.GenericMethods) { + assert(!r.Bool()) // generic methods are read in their defining type + } + tparams := r.typeParamNames(false, false) sig := r.signature(nil, nil, tparams) return types2.NewFunc(pos, objPkg, objName, sig) @@ -442,7 +454,7 @@ func (pr *pkgReader) objIdx(idx pkgbits.Index) (*types2.Package, string) { pos := r.pos() return types2.NewTypeNameLazy(pos, objPkg, objName, func(_ *types2.Named) ([]*types2.TypeParam, types2.Type, []*types2.Func, []func()) { - tparams := r.typeParamNames(true) + tparams := r.typeParamNames(true, false) // TODO(mdempsky): Rewrite receiver types to underlying is an // Interface? The go/types importer does this (I think because @@ -450,12 +462,70 @@ func (pr *pkgReader) objIdx(idx pkgbits.Index) (*types2.Package, string) { // about it, so maybe we can avoid worrying about that here. underlying := r.typ().Underlying() - methods := make([]*types2.Func, r.Len()) - for i := range methods { - methods[i] = r.method(true) + type indexedMethod struct { + index int // (or -1 in V4) + fn *types2.Func + } + var methods []indexedMethod + + if r.Version().Has(pkgbits.GenericMethods) { + // V4 (go1.27.0) emitted all non-generic methods + // before all generic ones, discarding source + // order: a bug (go.dev/issue/81188). + // V5 (go1.27.x) fixes it by emitting an explicit + // index along with each method. + + // ordinary methods + for range r.Len() { + idx, m := r.method(true) + methods = append(methods, indexedMethod{idx, m}) + } + + // generic methods + for range r.Len() { + // Careful: objIdx is used to read in package-scoped declarations, which + // methods are not. Instead, decode it here. This makes it easier to + // associate it with the type and avoids the main objIdx loop. + idx := r.Reloc(pkgbits.SectionObj) + + t := pr.tempReader(pkgbits.SectionObj, idx, pkgbits.SyncObject1) + t.dict = pr.objDictIdx(idx) + + pos := t.pos() + assert(t.Bool()) // generic method + pkg, name := t.selector() + rtparams := t.typeParamNames(true, true) + recv := t.param() + methodIdx := -1 + if r.Version().Has(pkgbits.PreserveMethodOrder) { + methodIdx = t.Len() + } + tparams := t.typeParamNames(true, false) + sig := t.signature(recv, rtparams, tparams) + + r.delayed = append(r.delayed, t.delayed...) // propagate before retiring + pr.retireReader(t) + methods = append(methods, indexedMethod{methodIdx, types2.NewFunc(pos, pkg, name, sig)}) + } + + if r.Version().Has(pkgbits.PreserveMethodOrder) { + slices.SortFunc(methods, func(a, b indexedMethod) int { + return cmp.Compare(a.index, b.index) + }) + } + } else { + for range r.Len() { + _, m := r.method(true) + methods = append(methods, indexedMethod{-1, m}) + } + } + + funcs := make([]*types2.Func, len(methods)) + for i, m := range methods { + funcs[i] = m.fn } - return tparams, underlying, methods, r.delayed + return tparams, underlying, funcs, r.delayed }) case pkgbits.ObjVar: @@ -477,9 +547,20 @@ func (pr *pkgReader) objDictIdx(idx pkgbits.Index) *readerDict { base.Fatalf("unexpected object with %v implicit type parameter(s)", implicits) } - dict.bounds = make([]typeInfo, r.Len()) - for i := range dict.bounds { - dict.bounds[i] = r.typInfo() + nreceivers := 0 + if r.Version().Has(pkgbits.GenericMethods) { + nreceivers = r.Len() + } + nexplicits := r.Len() + + dict.rtbounds = make([]typeInfo, nreceivers) + for i := range dict.rtbounds { + dict.rtbounds[i] = r.typInfo() + } + + dict.tbounds = make([]typeInfo, nexplicits) + for i := range dict.tbounds { + dict.tbounds[i] = r.typInfo() } dict.derived = make([]derivedInfo, r.Len()) @@ -498,15 +579,24 @@ func (pr *pkgReader) objDictIdx(idx pkgbits.Index) *readerDict { return &dict } -func (r *reader) typeParamNames(isLazy bool) []*types2.TypeParam { +func (r *reader) typeParamNames(isLazy bool, isGenMeth bool) []*types2.TypeParam { r.Sync(pkgbits.SyncTypeParamNames) - // Note: This code assumes it only processes objects without - // implement type parameters. This is currently fine, because - // reader is only used to read in exported declarations, which are - // always package scoped. + // Note: This code assumes there are no implicit type parameters. + // This is fine since it only reads exported declarations, which + // never have implicits. - if len(r.dict.bounds) == 0 { + var in []typeInfo + var out *[]*types2.TypeParam + if isGenMeth { + in = r.dict.rtbounds + out = &r.dict.rtparams + } else { + in = r.dict.tbounds + out = &r.dict.tparams + } + + if len(in) == 0 { return nil } @@ -515,51 +605,57 @@ func (r *reader) typeParamNames(isLazy bool) []*types2.TypeParam { // create all the TypeNames and TypeParams, then we construct and // set the bound type. - r.dict.tparams = make([]*types2.TypeParam, len(r.dict.bounds)) - for i := range r.dict.bounds { + // We have to save tparams outside of the closure, because typeParamNames + // can be called multiple times with the same dictionary instance. + tparams := make([]*types2.TypeParam, len(in)) + *out = tparams + + for i := range in { pos := r.pos() pkg, name := r.localIdent() tname := types2.NewTypeName(pos, pkg, name, nil) - r.dict.tparams[i] = types2.NewTypeParam(tname, nil) + tparams[i] = types2.NewTypeParam(tname, nil) } // Type parameters that are read by lazy loaders cannot have their // constraints set eagerly; do them after loading (go.dev/issue/63285). if isLazy { // The reader dictionary will continue mutating before we have time - // to call delayed functions; must make a local copy of both the type - // parameters and their (unexpanded) constraints. - bounds := make([]types2.Type, len(r.dict.bounds)) - for i, bound := range r.dict.bounds { - bounds[i] = r.p.typIdx(bound, r.dict) + // to call delayed functions; make a local copy of the constraints. + types := make([]types2.Type, len(in)) + for i, info := range in { + types[i] = r.p.typIdx(info, r.dict) } - tparams := r.dict.tparams r.delayed = append(r.delayed, func() { - for i, bound := range bounds { - tparams[i].SetConstraint(bound) + for i, typ := range types { + tparams[i].SetConstraint(typ) } }) } else { - for i, bound := range r.dict.bounds { - r.dict.tparams[i].SetConstraint(r.p.typIdx(bound, r.dict)) + for i, info := range in { + tparams[i].SetConstraint(r.p.typIdx(info, r.dict)) } } - return r.dict.tparams + return tparams } -func (r *reader) method(isLazy bool) *types2.Func { +func (r *reader) method(isLazy bool) (int, *types2.Func) { r.Sync(pkgbits.SyncMethod) + idx := -1 + if r.Version().Has(pkgbits.PreserveMethodOrder) { + idx = r.Len() + } pos := r.pos() pkg, name := r.selector() - rtparams := r.typeParamNames(isLazy) + rtparams := r.typeParamNames(isLazy, false) sig := r.signature(r.param(), rtparams, nil) _ = r.pos() // TODO(mdempsky): Remove; this is a hacker for linker.go. - return types2.NewFunc(pos, pkg, name, sig) + return idx, types2.NewFunc(pos, pkg, name, sig) } func (r *reader) qualifiedIdent() (*types2.Package, string) { return r.ident(pkgbits.SyncSym) } diff --git a/src/cmd/compile/internal/inline/inl.go b/src/cmd/compile/internal/inline/inl.go index 3a9243e0291f5e..bd8c3c1a23f482 100644 --- a/src/cmd/compile/internal/inline/inl.go +++ b/src/cmd/compile/internal/inline/inl.go @@ -179,6 +179,25 @@ func CanInlineFuncs(funcs []*ir.Func, profile *pgoir.Profile) { }) } +func simdCreditMultiplier(fn *ir.Func) int32 { + for _, field := range fn.Type().RecvParamsResults() { + if field.Type.IsSIMD() { + return 3 + } + } + // Sometimes code uses closures, that do not take simd + // parameters, to perform repetitive SIMD operations. + // fn. These really need to be inlined, or the anticipated + // awesome SIMD performance will be missed. + for _, v := range fn.ClosureVars { + if v.Type().IsSIMD() { + return 16 // 11 16 ought to be enough. + } + } + + return 1 +} + // inlineBudget determines the max budget for function 'fn' prior to // analyzing the hairiness of the body of 'fn'. We pass in the pgo // profile if available (which can change the budget), also a @@ -186,9 +205,14 @@ func CanInlineFuncs(funcs []*ir.Func, profile *pgoir.Profile) { // possibility that a call to the function might have its score // adjusted downwards. If 'verbose' is set, then print a remark where // we boost the budget due to PGO. +// Note that inlineCostOk has the final say on whether an inline will +// happen; changes here merely make inlines possible. func inlineBudget(fn *ir.Func, profile *pgoir.Profile, relaxed bool, verbose bool) int32 { // Update the budget for profile-guided inlining. budget := int32(inlineMaxBudget) + + budget *= simdCreditMultiplier(fn) + if IsPgoHotFunc(fn, profile) { budget = inlineHotMaxBudget if verbose { @@ -202,6 +226,7 @@ func inlineBudget(fn *ir.Func, profile *pgoir.Profile, relaxed bool, verbose boo // be very liberal here, if the closure is only called once, the budget is large budget = max(budget, inlineClosureCalledOnceCost) } + return budget } @@ -261,17 +286,27 @@ func CanInline(fn *ir.Func, profile *pgoir.Profile) { // locals, and we use this map to produce a pruned Inline.Dcl // list. See issue 25459 for more context. + dbg := ir.MatchAstDump(fn, "inline") + visitor := hairyVisitor{ curFunc: fn, + debug: isDebugFn(fn), isBigFunc: IsBigFunc(fn), budget: budget, maxBudget: budget, extraCallCost: cc, profile: profile, + dbg: dbg, // Useful for downstream debugging } + if visitor.tooHairy(fn) { reason = visitor.reason + if dbg { + ir.AstDump(fn, "inline, too hairy because "+visitor.reason+", "+ir.FuncName(fn)) + } return + } else if dbg { + ir.AstDump(fn, "inline, OK, "+ir.FuncName(fn)) } n.Func.Inl = &ir.Inline{ @@ -289,9 +324,9 @@ func CanInline(fn *ir.Func, profile *pgoir.Profile) { // function is inlinable. func noteInlinableFunc(n *ir.Name, fn *ir.Func, cost int32) { if base.Flag.LowerM > 1 { - fmt.Printf("%v: can inline %v with cost %d as: %v { %v }\n", ir.Line(fn), n, cost, fn.Type(), fn.Body) + fmt.Printf("%v: can inline %v with cost %d as: %v { %v }\n", ir.Line(fn), n.DiagName(), cost, fn.Type(), fn.Body) } else if base.Flag.LowerM != 0 { - fmt.Printf("%v: can inline %v\n", ir.Line(fn), n) + fmt.Printf("%v: can inline %v\n", ir.Line(fn), n.DiagName()) } // JSON optimization log output. if logopt.Enabled() { @@ -407,6 +442,7 @@ type hairyVisitor struct { // This is needed to access the current caller in the doNode function. curFunc *ir.Func isBigFunc bool + debug bool budget int32 maxBudget int32 reason string @@ -414,6 +450,17 @@ type hairyVisitor struct { usedLocals ir.NameSet do func(ir.Node) bool profile *pgoir.Profile + dbg bool +} + +func isDebugFn(fn *ir.Func) bool { + // if n := fn.Nname; n != nil { + // if n.Sym().Name == "Int32x8.Transpose8" && n.Sym().Pkg.Path == "simd/archsimd" { + // fmt.Printf("isDebugFn '%s' DOT '%s'\n", n.Sym().Pkg.Path, n.Sym().Name) + // return true + // } + // } + return false } func (v *hairyVisitor) tooHairy(fn *ir.Func) bool { @@ -434,6 +481,9 @@ func (v *hairyVisitor) doNode(n ir.Node) bool { if n == nil { return false } + if v.debug { + fmt.Printf("%v: doNode %v budget is %d\n", ir.Line(n), n.Op(), v.budget) + } opSwitch: switch n.Op() { // Call is okay if inlinable and we have the budget for the body. @@ -476,6 +526,9 @@ opSwitch: break opSwitch case "panicrangestate": cheap = true + case "deferrangefunc": + v.reason = "defer call in range func" + return true } } } @@ -551,12 +604,19 @@ opSwitch: } if cheap { + if v.debug { + if ir.IsIntrinsicCall(n) { + fmt.Printf("%v: cheap call is also intrinsic, %v\n", ir.Line(n), n) + } + } break // treat like any other node, that is, cost of 1 } if ir.IsIntrinsicCall(n) { - // Treat like any other node. - break + if v.debug { + fmt.Printf("%v: intrinsic call, %v\n", ir.Line(n), n) + } + break // Treat like any other node. } if callee := inlCallee(v.curFunc, n.Fun, v.profile, false); callee != nil && typecheck.HaveInlineBody(callee) { @@ -583,6 +643,10 @@ opSwitch: } } + if v.debug { + fmt.Printf("%v: costly OCALLFUNC %v\n", ir.Line(n), n) + } + // Call cost for non-leaf inlining. v.budget -= extraCost @@ -592,6 +656,9 @@ opSwitch: // Things that are too hairy, irrespective of the budget case ir.OCALL, ir.OCALLINTER: // Call cost for non-leaf inlining. + if v.debug { + fmt.Printf("%v: costly OCALL %v\n", ir.Line(n), n) + } v.budget -= v.extraCallCost case ir.OPANIC: @@ -754,7 +821,7 @@ opSwitch: v.budget-- // When debugging, don't stop early, to get full cost of inlining this function - if v.budget < 0 && base.Flag.LowerM < 2 && !logopt.Enabled() { + if v.budget < 0 && base.Flag.LowerM < 2 && !logopt.Enabled() && !v.debug { v.reason = "too expensive" return true } @@ -845,7 +912,7 @@ func TryInlineCall(callerfn *ir.Func, call *ir.CallExpr, bigCaller bool, profile } if fn := inlCallee(callerfn, call.Fun, profile, false); fn != nil && typecheck.HaveInlineBody(fn) { - return mkinlcall(callerfn, call, fn, bigCaller, closureCalledOnce) + return mkinlcall(callerfn, call, fn, bigCaller, closureCalledOnce, profile) } return nil } @@ -893,7 +960,7 @@ var SSADumpInline = func(*ir.Func) {} // InlineCall allows the inliner implementation to be overridden. // If it returns nil, the function will not be inlined. -var InlineCall = func(callerfn *ir.Func, call *ir.CallExpr, fn *ir.Func, inlIndex int) *ir.InlinedCallExpr { +var InlineCall = func(callerfn *ir.Func, call *ir.CallExpr, fn *ir.Func, inlIndex int, profile *pgoir.Profile) *ir.InlinedCallExpr { base.Fatalf("inline.InlineCall not overridden") panic("unreachable") } @@ -914,6 +981,8 @@ func inlineCostOK(n *ir.CallExpr, caller, callee *ir.Func, bigCaller, closureCal maxCost = inlineBigFunctionMaxCost } + simdMaxCost := simdCreditMultiplier(callee) * maxCost + if callee.ClosureParent != nil { maxCost *= 2 // favor inlining closures if closureCalledOnce { // really favor inlining the one call to this closure @@ -921,6 +990,8 @@ func inlineCostOK(n *ir.CallExpr, caller, callee *ir.Func, bigCaller, closureCal } } + maxCost = max(maxCost, simdMaxCost) + metric := callee.Inl.Cost if inlheur.Enabled() { score, ok := inlheur.GetCallSiteScore(caller, n) @@ -1084,7 +1155,7 @@ func canInlineCallExpr(callerfn *ir.Func, n *ir.CallExpr, callee *ir.Func, bigCa // The result of mkinlcall MUST be assigned back to n, e.g. // // n.Left = mkinlcall(n.Left, fn, isddd) -func mkinlcall(callerfn *ir.Func, n *ir.CallExpr, fn *ir.Func, bigCaller, closureCalledOnce bool) *ir.InlinedCallExpr { +func mkinlcall(callerfn *ir.Func, n *ir.CallExpr, fn *ir.Func, bigCaller, closureCalledOnce bool, profile *pgoir.Profile) *ir.InlinedCallExpr { ok, score, hot := canInlineCallExpr(callerfn, n, fn, bigCaller, closureCalledOnce, true) if !ok { return nil @@ -1156,19 +1227,19 @@ func mkinlcall(callerfn *ir.Func, n *ir.CallExpr, fn *ir.Func, bigCaller, closur if base.Flag.LowerM != 0 { if buildcfg.Experiment.NewInliner { fmt.Printf("%v: inlining call to %v with score %d\n", - ir.Line(n), fn, score) + ir.Line(n), fn.Nname.DiagName(), score) } else { - fmt.Printf("%v: inlining call to %v\n", ir.Line(n), fn) + fmt.Printf("%v: inlining call to %v\n", ir.Line(n), fn.Nname.DiagName()) } } if base.Flag.LowerM > 2 { fmt.Printf("%v: Before inlining: %+v\n", ir.Line(n), n) } - res := InlineCall(callerfn, n, fn, inlIndex) + res := InlineCall(callerfn, n, fn, inlIndex, profile) if res == nil { - base.FatalfAt(n.Pos(), "inlining call to %v failed", fn) + base.FatalfAt(n.Pos(), "inlining call to %v failed", fn.Nname.DiagName()) } if base.Flag.LowerM > 2 { diff --git a/src/cmd/compile/internal/inline/inlheur/analyze_func_params.go b/src/cmd/compile/internal/inline/inlheur/analyze_func_params.go index f6bd84c3f507f1..abfcb3ab328997 100644 --- a/src/cmd/compile/internal/inline/inlheur/analyze_func_params.go +++ b/src/cmd/compile/internal/inline/inlheur/analyze_func_params.go @@ -122,9 +122,9 @@ func (pa *paramsAnalyzer) findParamIdx(n *ir.Name) int { type testfType func(x ir.Node, param *ir.Name, idx int) (bool, bool) -// paramsAnalyzer invokes function 'testf' on the specified expression -// 'x' for each parameter, and if the result is TRUE, or's 'flag' into -// the flags for that param. +// checkParams invokes function 'testf' on the specified expression 'x' +// for each parameter. If the result is TRUE, it OR's either 'flag' or 'mayflag' +// into the flags for that param, depending on whether we are in a conditional context. func (pa *paramsAnalyzer) checkParams(x ir.Node, flag ParamPropBits, mayflag ParamPropBits, testf testfType) { for idx, p := range pa.params { if !pa.top[idx] && pa.values[idx] == ParamNoInfo { diff --git a/src/cmd/compile/internal/inline/interleaved/interleaved.go b/src/cmd/compile/internal/inline/interleaved/interleaved.go index c83bbdb718df56..d66f1a84cc9906 100644 --- a/src/cmd/compile/internal/inline/interleaved/interleaved.go +++ b/src/cmd/compile/internal/inline/interleaved/interleaved.go @@ -20,6 +20,13 @@ import ( // DevirtualizeAndInlinePackage interleaves devirtualization and inlining on // all functions within pkg. func DevirtualizeAndInlinePackage(pkg *ir.Package, profile *pgoir.Profile) { + if base.Flag.W > 1 { + for _, fn := range typecheck.Target.Funcs { + s := fmt.Sprintf("\nbefore devirtualize-and-inline %v", fn.Sym()) + ir.DumpList(s, fn.Body) + } + } + if profile != nil && base.Debug.PGODevirtualize > 0 { // TODO(mdempsky): Integrate into DevirtualizeAndInlineFunc below. ir.VisitFuncsBottomUp(typecheck.Target.Funcs, func(list []*ir.Func, recursive bool) { @@ -254,28 +261,6 @@ func (s *inlClosureState) mark(n ir.Node) ir.Node { return n // already visited n.X before wrapping } - if isTestingBLoop(n) { - // No inlining nor devirtualization performed on b.Loop body - if base.Flag.LowerM > 0 { - fmt.Printf("%v: skip inlining within testing.B.loop for %v\n", ir.Line(n), n) - } - // We still want to explore inlining opportunities in other parts of ForStmt. - nFor, _ := n.(*ir.ForStmt) - nForInit := nFor.Init() - for i, x := range nForInit { - if x != nil { - nForInit[i] = s.mark(x) - } - } - if nFor.Cond != nil { - nFor.Cond = s.mark(nFor.Cond) - } - if nFor.Post != nil { - nFor.Post = s.mark(nFor.Post) - } - return n - } - if p != nil { n = p.X // in this case p was copied in from a (marked) inlined function, this is a new unvisited node. } @@ -371,29 +356,3 @@ func match(n ir.Node) bool { } return false } - -// isTestingBLoop returns true if it matches the node as a -// testing.(*B).Loop. See issue #61515. -func isTestingBLoop(t ir.Node) bool { - if t.Op() != ir.OFOR { - return false - } - nFor, ok := t.(*ir.ForStmt) - if !ok || nFor.Cond == nil || nFor.Cond.Op() != ir.OCALLFUNC { - return false - } - n, ok := nFor.Cond.(*ir.CallExpr) - if !ok || n.Fun == nil || n.Fun.Op() != ir.OMETHEXPR { - return false - } - name := ir.MethodExprName(n.Fun) - if name == nil { - return false - } - if fSym := name.Sym(); fSym != nil && name.Class == ir.PFUNC && fSym.Pkg != nil && - fSym.Name == "(*B).Loop" && fSym.Pkg.Path == "testing" { - // Attempting to match a function call to testing.(*B).Loop - return true - } - return false -} diff --git a/src/cmd/compile/internal/ir/class_string.go b/src/cmd/compile/internal/ir/class_string.go index 11a94c004701ba..bd14c417b2b639 100644 --- a/src/cmd/compile/internal/ir/class_string.go +++ b/src/cmd/compile/internal/ir/class_string.go @@ -23,8 +23,9 @@ const _Class_name = "PxxxPEXTERNPAUTOPAUTOHEAPPPARAMPPARAMOUTPTYPEPARAMPFUNC" var _Class_index = [...]uint8{0, 4, 11, 16, 25, 31, 40, 50, 55} func (i Class) String() string { - if i >= Class(len(_Class_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_Class_index)-1 { return "Class(" + strconv.FormatInt(int64(i), 10) + ")" } - return _Class_name[_Class_index[i]:_Class_index[i+1]] + return _Class_name[_Class_index[idx]:_Class_index[idx+1]] } diff --git a/src/cmd/compile/internal/ir/dump.go b/src/cmd/compile/internal/ir/dump.go index 4c218682ea6c75..9dfadc7f250af1 100644 --- a/src/cmd/compile/internal/ir/dump.go +++ b/src/cmd/compile/internal/ir/dump.go @@ -9,11 +9,16 @@ package ir import ( + "crypto/sha256" + "encoding/hex" "fmt" "io" + "net/url" "os" "reflect" "regexp" + "strings" + "sync" "cmd/compile/internal/base" "cmd/compile/internal/types" @@ -21,7 +26,7 @@ import ( ) // DumpAny is like FDumpAny but prints to stderr. -func DumpAny(root interface{}, filter string, depth int) { +func DumpAny(root any, filter string, depth int) { FDumpAny(os.Stderr, root, filter, depth) } @@ -42,7 +47,7 @@ func DumpAny(root interface{}, filter string, depth int) { // rather than their type; struct fields with zero values or // non-matching field names are omitted, and "…" means recursion // depth has been reached or struct fields have been omitted. -func FDumpAny(w io.Writer, root interface{}, filter string, depth int) { +func FDumpAny(w io.Writer, root any, filter string, depth int) { if root == nil { fmt.Fprintln(w, "nil") return @@ -63,6 +68,167 @@ func FDumpAny(w io.Writer, root interface{}, filter string, depth int) { p.printf("\n") } +// MatchAstDump returns true if the fn matches the value +// of the astdump debug flag. Fn matches in the following +// cases: +// +// - astdump == name(fn) +// - astdump == pkgname(fn).name(fn) +// - astdump == afterslash(pkgname(fn)).name(fn) +// - astdump begins with a "~" and what follows "~" is a +// regular expression matching pkgname(fn).name(fn) +// +// If MatchAstDump returns true, it also prints to os.Stderr +// +// \nir.Match(, ) for \n +func MatchAstDump(fn *Func, where string) bool { + if len(base.Debug.AstDump) == 0 { + return false + } + return matchForDump(fn, base.Ctxt.Pkgpath, where) +} + +// matchForDump is marked noinline to ensure that the exported +// function MatchAstDump IS inlineable and is also small, because +// common case is AstDump is not set. +// +//go:noinline +func matchForDump(fn *Func, pkgPath, where string) bool { + return MatchPkgFn(pkgPath, FuncName(fn), base.Debug.AstDump) +} + +// MatchPkgFn returns true if pkg and fnName "match" toMatch. +// "~REGEXP" matches REGEXP against pkgName + "." + fnName +// "aFunc" matches "aFunc" (in any package) +// "aPkg.aFunc" matches "aPkg.aFunc" +// "aPkg/subPkg.aFunc" matches "subPkg.aFunc" +func MatchPkgFn(pkgName, fnName, toMatch string) bool { + if toMatch[0] == '~' { + dbgRE := regexp.MustCompile(toMatch[1:]) + return dbgRE.MatchString(pkgName + "." + fnName) + } + if fnName == toMatch { + return true + } + matchPkgDotName := func(pkg string) bool { + // Allocation-free equality check for toMatch == base.Ctxt.Pkgpath + "." + fnName + return len(toMatch) == len(pkg)+1+len(fnName) && + strings.HasPrefix(toMatch, pkg) && toMatch[len(pkg)] == '.' && strings.HasSuffix(toMatch, fnName) + } + if matchPkgDotName(pkgName) { + return true + } + if l := strings.LastIndexByte(pkgName, '/'); l > 0 && matchPkgDotName(pkgName[l+1:]) { + return true + } + + return false +} + +// AstDump appends the ast dump for fn to the ast dump file for fn. +// The generated file name is +// +// url.PathEscape(PkgFuncName(fn)) + ".ast" +// +// It also prints +// +// Writing ast output to \n +// +// to os.Stderr. +func AstDump(fn *Func, why string) { + err := withLockAndFile( + fn, + func(w io.Writer) { + FDump(w, why, fn) + }, + ) + // strip text following comma, for phase names. + comma := strings.Index(why, ",") + if comma > 0 { + why = why[:comma] + } + DumpNodeHTML(fn, why, fn) + if err != nil { + fmt.Fprintf(os.Stderr, "Dump returned error %v\n", err) + } +} + +var mu sync.Mutex +var astDumpFiles = make(map[string]bool) + +func escapedFileName(fn *Func, suffix string) string { + return EscapedFileName(PkgFuncName(fn), suffix) +} + +// EscapedFileName constructs a file name from fn and suffix, +// url-path-escaping the function part of the name and replacing it +// with a hash if it is too long. The suffix is neither escaped +// nor including in the length calculation, so an excessively +// creative suffix will result in problems. +func EscapedFileName(fn, suffix string) string { + name := url.PathEscape(fn) + if len(name) > 125 { // arbitrary limit on file names, as if anyone types these in by hand + hash := sha256.Sum256([]byte(name)) + name = hex.EncodeToString(hash[:8]) + } + return name + suffix +} + +// withLockAndFile manages ast dump files for various function names +// and invokes a dumping function to write output, under a lock. +func withLockAndFile(fn *Func, dump func(io.Writer)) (err error) { + name := escapedFileName(fn, ".ast") + + // Ensure that debugging output is not scrambled and is written promptly + mu.Lock() + defer mu.Unlock() + mode := os.O_APPEND | os.O_RDWR + if !astDumpFiles[name] { + astDumpFiles[name] = true + mode = os.O_CREATE | os.O_TRUNC | os.O_RDWR + fmt.Fprintf(os.Stderr, "Writing text ast output for %s to %s\n", PkgFuncName(fn), name) + } + + fi, err := os.OpenFile(name, mode, 0777) + if err != nil { + return err + } + defer func() { err = fi.Close() }() + dump(fi) + return +} + +var htmlWriters = make(map[*Func]*HTMLWriter) +var orderedFuncs = []*Func{} + +// DumpNodeHTML dumps the node n to the HTML writer for fn. +// It uses the same phase name as the text dump. +func DumpNodeHTML(fn *Func, why string, n Node) { + mu.Lock() + defer mu.Unlock() + w, ok := htmlWriters[fn] + if !ok { + name := escapedFileName(fn, ".html") + w = NewHTMLWriter(name, fn, "") + htmlWriters[fn] = w + orderedFuncs = append(orderedFuncs, fn) + } + w.WritePhase(why, why) +} + +// CloseHTMLWriters closes the HTML writer for fn, if one exists. +func CloseHTMLWriters() { + mu.Lock() + defer mu.Unlock() + for _, fn := range orderedFuncs { + if w, ok := htmlWriters[fn]; ok { + w.Close("Writing html ast output for %s to %s\n", PkgFuncName(w.Func), w.path) + delete(htmlWriters, fn) + } + } + orderedFuncs = nil +} + type dumper struct { output io.Writer fieldrx *regexp.Regexp // field name filter @@ -110,7 +276,7 @@ func (p *dumper) Write(data []byte) (n int, err error) { } // printf is a convenience wrapper. -func (p *dumper) printf(format string, args ...interface{}) { +func (p *dumper) printf(format string, args ...any) { if _, err := fmt.Fprintf(p, format, args...); err != nil { panic(err) } diff --git a/src/cmd/compile/internal/ir/dump_test.go b/src/cmd/compile/internal/ir/dump_test.go new file mode 100644 index 00000000000000..6b607062c47e77 --- /dev/null +++ b/src/cmd/compile/internal/ir/dump_test.go @@ -0,0 +1,44 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ir + +import ( + "testing" +) + +func testMatch(t *testing.T, pkgName, fnName, toMatch string, match bool) { + if MatchPkgFn(pkgName, fnName, toMatch) != match { + t.Errorf("%v != matchPkgFn(%s, %s, %s)", match, pkgName, fnName, toMatch) + } +} + +func TestMatchPkgFn(t *testing.T) { + // "aFunc" matches "aFunc" (in any package) + // "aPkg.aFunc" matches "aPkg.aFunc" + // "aPkg/subPkg.aFunc" matches "subPkg.aFunc" + + match := func(pkgName, fnName, toMatch string) { + if !MatchPkgFn(pkgName, fnName, toMatch) { + t.Errorf("matchPkgFn(%s, %s, %s) did not match", pkgName, fnName, toMatch) + } + } + match("aPkg", "AFunc", "AFunc") + match("aPkg", "AFunc", "AFunc") + match("aPkg", "AFunc", "aPkg.AFunc") + match("aPkg/sPkg", "AFunc", "aPkg/sPkg.AFunc") + match("aPkg/sPkg", "AFunc", "sPkg.AFunc") + + notmatch := func(pkgName, fnName, toMatch string) { + if MatchPkgFn(pkgName, fnName, toMatch) { + t.Errorf("matchPkgFn(%s, %s, %s) should not match", pkgName, fnName, toMatch) + } + } + notmatch("aPkg", "AFunc", "BFunc") + notmatch("aPkg", "AFunc", "aPkg.BFunc") + notmatch("aPkg", "AFunc", "bPkg.AFunc") + notmatch("aPkg", "AFunc", "aPkg_AFunc") + notmatch("aPkg/sPkg", "AFunc", "aPkg/ssPkg.AFunc") + notmatch("aPkg/sPkg", "AFunc", "XPkg.AFunc") +} diff --git a/src/cmd/compile/internal/ir/expr.go b/src/cmd/compile/internal/ir/expr.go index 7a75ff40f2d609..9b4577bd37f332 100644 --- a/src/cmd/compile/internal/ir/expr.go +++ b/src/cmd/compile/internal/ir/expr.go @@ -184,14 +184,20 @@ func (n *BinaryExpr) SetOp(op Op) { // A CallExpr is a function call Fun(Args). type CallExpr struct { miniExpr - Fun Node - Args Nodes - DeferAt Node - RType Node `mknode:"-"` // see reflectdata/helpers.go - KeepAlive []*Name // vars to be kept alive until call returns - IsDDD bool - GoDefer bool // whether this call is part of a go or defer statement - NoInline bool // whether this call must not be inlined + Fun Node + Args Nodes + DeferAt Node + RType Node `mknode:"-"` // see reflectdata/helpers.go + KeepAlive []*Name // vars to be kept alive until call returns + IsDDD bool + GoDefer bool // whether this call is part of a go or defer statement + NoInline bool // whether this call must not be inlined + UseBuf bool // use stack buffer for backing store (OAPPEND only) + AppendNoAlias bool // backing store proven to be unaliased (OAPPEND only) + // whether it's a runtime.KeepAlive call the compiler generates to + // keep a variable alive. See #73137. + IsCompilerVarLive bool + Reshape bool } func NewCallExpr(pos src.XPos, op Op, fun Node, args []Node) *CallExpr { @@ -371,6 +377,7 @@ type InlinedCallExpr struct { miniExpr Body Nodes ReturnVars Nodes // must be side-effect free + Reshape bool } func NewInlinedCallExpr(pos src.XPos, body, retvars []Node) *InlinedCallExpr { @@ -386,10 +393,16 @@ func (n *InlinedCallExpr) SingleResult() Node { if have := len(n.ReturnVars); have != 1 { base.FatalfAt(n.Pos(), "inlined call has %v results, expected 1", have) } - if !n.Type().HasShape() && n.ReturnVars[0].Type().HasShape() { - // If the type of the call is not a shape, but the type of the return value - // is a shape, we need to do an implicit conversion, so the real type - // of n is maintained. + + // If the type of the call is not a shape, but the type of the return value + // is a shape, we need to do an implicit conversion, so the real type + // of n is maintained. + needImplicitConv := !n.Type().HasShape() && n.ReturnVars[0].Type().HasShape() + if n.Reshape { // or if the inlined call expr needs reshaping. + needImplicitConv = true + } + + if needImplicitConv { r := NewConvExpr(n.Pos(), OCONVNOP, n.Type(), n.ReturnVars[0]) r.SetTypecheck(1) return r @@ -680,7 +693,7 @@ type TypeAssertExpr struct { // When set to true, if this assert would panic, then use a nil pointer panic // instead of an interface conversion panic. - // It must not be set for type asserts using the commaok form. + // It must not be set for type assertions using the commaok form. UseNilPanic bool } @@ -1027,6 +1040,9 @@ func StaticCalleeName(n Node) *Name { // IsIntrinsicCall reports whether the compiler back end will treat the call as an intrinsic operation. var IsIntrinsicCall = func(*CallExpr) bool { return false } +// IsIntrinsicSym reports whether the compiler back end will treat a call to this symbol as an intrinsic operation. +var IsIntrinsicSym = func(*types.Sym) bool { return false } + // SameSafeExpr checks whether it is safe to reuse one of l and r // instead of computing both. SameSafeExpr assumes that l and r are // used in the same statement or expression. In order for it to be @@ -1145,6 +1161,14 @@ func ParamNames(ft *types.Type) []Node { return args } +func RecvParamNames(ft *types.Type) []Node { + args := make([]Node, ft.NumRecvs()+ft.NumParams()) + for i, f := range ft.RecvParams() { + args[i] = f.Nname.(*Name) + } + return args +} + // MethodSym returns the method symbol representing a method name // associated with a specific receiver type. // @@ -1269,3 +1293,28 @@ func MethodExprFunc(n Node) *types.Field { base.Fatalf("unexpected node: %v (%v)", n, n.Op()) panic("unreachable") } + +// A MoveToHeapExpr takes a slice as input and moves it to the +// heap (by copying the backing store if it is not already +// on the heap). +type MoveToHeapExpr struct { + miniExpr + Slice Node + // An expression that evaluates to a *runtime._type + // that represents the slice element type. + RType Node + // If PreserveCapacity is true, the capacity of + // the resulting slice, and all of the elements in + // [len:cap], must be preserved. + // If PreserveCapacity is false, the resulting + // slice may have any capacity >= len, with any + // elements in the resulting [len:cap] range zeroed. + PreserveCapacity bool +} + +func NewMoveToHeapExpr(pos src.XPos, slice Node) *MoveToHeapExpr { + n := &MoveToHeapExpr{Slice: slice} + n.pos = pos + n.op = OMOVE2HEAP + return n +} diff --git a/src/cmd/compile/internal/ir/fmt.go b/src/cmd/compile/internal/ir/fmt.go index ae4ff62652eac0..00bc1af0ffbd39 100644 --- a/src/cmd/compile/internal/ir/fmt.go +++ b/src/cmd/compile/internal/ir/fmt.go @@ -574,7 +574,7 @@ func exprFmt(n Node, s fmt.State, prec int) { // Special case for rune constants. if typ == types.RuneType || typ == types.UntypedRune { if x, ok := constant.Uint64Val(val); ok && x <= utf8.MaxRune { - fmt.Fprintf(s, "%q", x) + fmt.Fprintf(s, "%q", rune(x)) return } } @@ -897,11 +897,19 @@ func (l Nodes) Format(s fmt.State, verb rune) { // Dump // Dump prints the message s followed by a debug dump of n. +// This includes all the recursive structure under n. func Dump(s string, n Node) { fmt.Printf("%s%+v\n", s, n) } +// FDump prints to w the message s followed by a debug dump of n. +// This includes all the recursive structure under n. +func FDump(w io.Writer, s string, n Node) { + fmt.Fprintf(w, "%s%+v\n", s, n) +} + // DumpList prints the message s followed by a debug dump of each node in the list. +// This includes all the recursive structure under each node in the list. func DumpList(s string, list Nodes) { var buf bytes.Buffer FDumpList(&buf, s, list) @@ -909,6 +917,7 @@ func DumpList(s string, list Nodes) { } // FDumpList prints to w the message s followed by a debug dump of each node in the list. +// This includes all the recursive structure under each node in the list. func FDumpList(w io.Writer, s string, list Nodes) { io.WriteString(w, s) dumpNodes(w, list, 1) diff --git a/src/cmd/compile/internal/ir/func.go b/src/cmd/compile/internal/ir/func.go index 668537c90e6a40..e3879276d979d5 100644 --- a/src/cmd/compile/internal/ir/func.go +++ b/src/cmd/compile/internal/ir/func.go @@ -7,11 +7,12 @@ package ir import ( "cmd/compile/internal/base" "cmd/compile/internal/types" + "cmd/internal/hash" "cmd/internal/obj" "cmd/internal/objabi" "cmd/internal/src" + "encoding/base64" "fmt" - "strings" "unicode/utf8" ) @@ -90,7 +91,7 @@ type Func struct { Marks []Mark FieldTrack map[*obj.LSym]struct{} - DebugInfo interface{} + DebugInfo any LSym *obj.LSym // Linker object in this function's native ABI (Func.ABI) Inl *Inline @@ -148,7 +149,7 @@ type Func struct { // a WebAssembly function import. WasmImport *WasmImport // WasmExport is used by the //go:wasmexport directive to store info about - // a WebAssembly function import. + // a WebAssembly function export. WasmExport *WasmExport } @@ -315,7 +316,9 @@ func PkgFuncName(f *Func) string { } s := f.Sym() pkg := s.Pkg - + if pkg == nil { + return "." + s.Name + } return pkg.Path + "." + s.Name } @@ -428,10 +431,9 @@ func ClosureDebugRuntimeCheck(clo *ClosureExpr) { var globClosgen int32 // closureName generates a new unique name for a closure within outerfn at pos. -func closureName(outerfn *Func, pos src.XPos, why Op) *types.Sym { - if outerfn.OClosure != nil && outerfn.OClosure.Func.RangeParent != nil { - outerfn = outerfn.OClosure.Func.RangeParent - } +// gen is an optional counter for the closure name. If it is 0, the counter +// will be computed based on outerfn. +func closureName(outerfn *Func, pos src.XPos, why Op, gen int) *types.Sym { pkg := types.LocalPkg outer := "glob." var suffix string = "." @@ -449,7 +451,6 @@ func closureName(outerfn *Func, pos src.XPos, why Op) *types.Sym { case ODEFER: suffix = ".deferwrap" } - gen := &globClosgen // There may be multiple functions named "_". In those // cases, we can't use their individual Closgens as it @@ -457,30 +458,59 @@ func closureName(outerfn *Func, pos src.XPos, why Op) *types.Sym { if !IsBlank(outerfn.Nname) { pkg = outerfn.Sym().Pkg outer = FuncName(outerfn) - - switch why { - case OCLOSURE: - gen = &outerfn.funcLitGen - case ORANGE: - gen = &outerfn.rangeLitGen - default: - gen = &outerfn.goDeferGen - } } - // If this closure was created due to inlining, then incorporate any - // inlined functions' names into the closure's linker symbol name - // too (#60324). + // If this closure was created due to inlining, find the original + // outer function's name for the closure (#60324). + var inlHash string if inlIndex := base.Ctxt.InnermostPos(pos).Base().InliningIndex(); inlIndex >= 0 { - names := []string{outer} + // The compiler doesn't like multiple symbols with the same + // name. We make a unique suffix temporarily for the + // compiler, and strip it during object file writing, so + // it will not be the linker symbol name. For linking, + // we use a content hash to disambiguate instead. + // We choose the suffix as a hash of the inline call stack. + h := hash.New32() + fmt.Fprint(h, inlIndex) base.Ctxt.InlTree.AllParents(inlIndex, func(call obj.InlinedCall) { - names = append(names, call.Name) + if call.Parent >= 0 { + fmt.Fprint(h, " ", call.Parent) + } }) - outer = strings.Join(names, ".") + inlHash = base64.StdEncoding.EncodeToString(h.Sum(nil)[:8]) + + outer = base.Ctxt.InlTree.InlinedFuncName(inlIndex) + if pkgPath := base.Ctxt.InlTree.InlinedFuncPkg(inlIndex); pkgPath != "" { + pkg = types.NewPkg(pkgPath, "") + } } - *gen++ - return pkg.Lookup(fmt.Sprintf("%s%s%d", outer, suffix, *gen)) + if gen == 0 { + p := &globClosgen + if !IsBlank(outerfn.Nname) { + switch why { + case OCLOSURE: + p = &outerfn.funcLitGen + case ORANGE: + p = &outerfn.rangeLitGen + default: + p = &outerfn.goDeferGen + } + } + *p++ + gen = int(*p) + } + + name := fmt.Sprintf("%s%s%d", outer, suffix, gen) + if inlHash != "" { + // Attach the inline hash (see the comment above). + // If it already has a hash, trim it, so we don't include + // two hashes for nested closures. The new hash should be + // enough to disambiguate. + name = obj.TrimInlineHash(name) + "#" + inlHash + "#" + } + + return pkg.Lookup(name) } // NewClosureFunc creates a new Func to represent a function literal @@ -498,14 +528,19 @@ func closureName(outerfn *Func, pos src.XPos, why Op) *types.Sym { // why is the reason we're generating this Func. It can be OCLOSURE // (for a normal function literal) or OGO or ODEFER (for wrapping a // call expression that has parameters or results). -func NewClosureFunc(fpos, cpos src.XPos, why Op, typ *types.Type, outerfn *Func, pkg *Package) *Func { +// +// gen is an optional counter for the closure name. If it is 0, +// the counter will be computed based on outerfn. +func NewClosureFunc(fpos, cpos src.XPos, why Op, typ *types.Type, outerfn *Func, pkg *Package, gen int) *Func { if outerfn == nil { base.FatalfAt(fpos, "outerfn is nil") } - fn := NewFunc(fpos, fpos, closureName(outerfn, cpos, why), typ) + fn := NewFunc(fpos, fpos, closureName(outerfn, cpos, why, gen), typ) fn.SetDupok(outerfn.Dupok()) // if the outer function is dupok, so is the closure + fn.Linksym().Set(obj.AttrContentAddressable, true) + clo := &ClosureExpr{Func: fn} clo.op = OCLOSURE clo.pos = cpos diff --git a/src/cmd/compile/internal/ir/html.go b/src/cmd/compile/internal/ir/html.go new file mode 100644 index 00000000000000..0f766ae15fe800 --- /dev/null +++ b/src/cmd/compile/internal/ir/html.go @@ -0,0 +1,1086 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ir + +import ( + "bufio" + "cmd/compile/internal/base" + "cmd/compile/internal/types" + "cmd/internal/src" + "crypto/sha256" + "encoding/hex" + "fmt" + "html" + "io" + "os" + "path/filepath" + "reflect" + "regexp" + "strings" +) + +// An HTMLWriter dumps IR to multicolumn HTML, similar to what the +// ssa backend does for GOSSAFUNC. This is not the format used for +// the ast column in GOSSAFUNC output. +type HTMLWriter struct { + HTMLWriterBase + Func *Func +} + +type HTMLWriterBase struct { + w *BufferedWriterCloser + canonIdMap map[any]int + prevCanonId int + path string + prevHash []byte + pendingPhases []string + pendingTitles []string + doDump func(string) func() +} + +func (h *HTMLWriterBase) Init(out io.WriteCloser, reportPath string, doDump func(string) func()) { + h.w = NewBufferedWriterCloser(out) + h.canonIdMap = make(map[any]int) + h.path = reportPath + h.doDump = doDump +} + +// BufferedWriterCloser is here to help avoid pre-buffering the whole +// rendered HTML in memory, which can cause problems for large inputs. +type BufferedWriterCloser struct { + file io.Closer + w *bufio.Writer +} + +func (b *BufferedWriterCloser) Write(p []byte) (n int, err error) { + return b.w.Write(p) +} + +func (b *BufferedWriterCloser) Close() error { + b.w.Flush() + b.w = nil + return b.file.Close() +} + +func NewBufferedWriterCloser(f io.WriteCloser) *BufferedWriterCloser { + return &BufferedWriterCloser{file: f, w: bufio.NewWriter(f)} +} + +func NewHTMLWriter(path string, f *Func, cfgMask string) *HTMLWriter { + path = strings.ReplaceAll(path, "/", string(filepath.Separator)) + out, err := os.OpenFile(path, os.O_WRONLY|os.O_CREATE|os.O_TRUNC, 0644) + if err != nil { + base.Fatalf("%v", err) + } + reportPath := path + if !filepath.IsAbs(reportPath) { + pwd, err := os.Getwd() + if err != nil { + base.Fatalf("%v", err) + } + reportPath = filepath.Join(pwd, path) + } + h := HTMLWriter{ + Func: f, + } + h.Init(out, reportPath, h.FuncHTML) + h.start() + return &h +} + +func (h *HTMLWriterBase) Path() string { + return h.path +} + +// CanonId assigns indices to nodes based on pointer identity. +// this helps ensure that output html files don't gratuitously +// differ from run to run. +func (h *HTMLWriterBase) CanonId(n any) int { + if id := h.canonIdMap[n]; id > 0 { + return id + } + h.prevCanonId++ + h.canonIdMap[n] = h.prevCanonId + return h.prevCanonId +} + +// Fatalf reports an error and exits. +func (w *HTMLWriterBase) Fatalf(msg string, args ...any) { + base.FatalfAt(src.NoXPos, msg, args...) +} + +const ( + RightArrow = "►" // \u25BA click-to-open (is closed) + DownArrow = "▼" // \u25BC click-to-close (is open) +) + +func (w *HTMLWriter) start() { + if w == nil { + return + } + escName := html.EscapeString(PkgFuncName(w.Func)) + w.Print("") + w.Print("") + w.Printf(` + + +%s +%s +AST display for %s +`, escName, CSS, JS("bloop", "loopvar", "escape", "slice", "walk"), escName) + w.Print("") + w.Print("

    ") + w.Print(html.EscapeString(w.Func.Sym().Name)) + w.Print("

    ") + w.Print(` +help +
    + +

    +Click anywhere on a node (with "cell" cursor) to outline a node and all of its subtrees. +

    +

    +Click on a name (with "crosshair" cursor) to highlight every occurrence of a name. +(Note that all the name nodes are the same node, so those also all outline together). +

    +

    +Click on a file, line, or column (with "crosshair" cursor) to highlight positions +in that file, at that file:line, or at that file:line:column, respectively.
    Inlined +locations are not treated as a single location, but as a sequence of locations that +can be independently highlighted. +

    +

    +Click on a ` + DownArrow + ` to collapse a subtree, or on a ` + RightArrow + ` to expand a subtree. +

    + + +
    + + +`) + w.Print("") + w.Print("") +} + +func (w *HTMLWriterBase) Close(format string, args ...any) { + if w == nil { + return + } + w.Print("") + w.Print("
    ") + w.Print("") + w.Print("\n") + w.w.Close() + fmt.Fprintf(os.Stderr, format, args...) +} + +// WritePhase writes f in a column headed by title. +// phase is used for collapsing columns and should be unique across the table. +func (w *HTMLWriterBase) WritePhase(phase, title string) { + if w == nil { + return // avoid generating HTML just to discard it + } + w.pendingPhases = append(w.pendingPhases, phase) + w.pendingTitles = append(w.pendingTitles, title) + w.flushPhases() +} + +// flushPhases collects any pending phases and titles, writes them to the html, and resets the pending slices. +func (w *HTMLWriterBase) flushPhases() { + phaseLen := len(w.pendingPhases) + if phaseLen == 0 { + return + } + phases := strings.Join(w.pendingPhases, " + ") + w.WriteMultiTitleColumn( + phases, + w.pendingTitles, + "allow-x-scroll", + w.doDump(w.pendingPhases[phaseLen-1]), + ) + w.pendingPhases = w.pendingPhases[:0] + w.pendingTitles = w.pendingTitles[:0] +} + +func (w *HTMLWriterBase) WriteMultiTitleColumn(phase string, titles []string, class string, writeContent func()) { + if w == nil { + return + } + id := strings.ReplaceAll(phase, " ", "-") + // collapsed column + w.Printf("
    %v
    ", id, phase) + + if class == "" { + w.Printf("", id) + } else { + w.Printf("", id, class) + } + for _, title := range titles { + w.Print("

    " + title + "

    ") + } + writeContent() + w.Print("
    ") + w.Print("\n") +} + +func (w *HTMLWriterBase) Printf(msg string, v ...any) { + if _, err := fmt.Fprintf(w.w, msg, v...); err != nil { + w.Fatalf("%v", err) + } +} + +func (w *HTMLWriterBase) Print(s string) { + if _, err := fmt.Fprint(w.w, s); err != nil { + w.Fatalf("%v", err) + } +} + +func (w *HTMLWriterBase) indent(n int) { + indent(w.w, n) +} + +func (w *HTMLWriter) FuncHTML(phase string) func() { + return func() { + w.Print("
    ") // use pre for formatting to preserve indentation
    +		w.dumpNodesHTML(w.Func.Body, 1)
    +		w.Print("
    ") + } +} + +func (h *HTMLWriter) dumpNodesHTML(list Nodes, depth int) { + if len(list) == 0 { + h.Print(" ") + return + } + + for _, n := range list { + h.dumpNodeHTML(n, depth) + } +} + +const indentString = ". " + +// indent prints indentation to w. +func (h *HTMLWriterBase) indentForToggle(depth int, hasChildren bool) { + h.Print("\n") + if depth == 0 { + return + } + for i := 0; i < depth-1; i++ { + h.Print(indentString) + } + if hasChildren { + // Remove 2 spaces, which have similar rendered width to + // leading ir.DownArrow and trailing space. + h.Print(indentString[:len(indentString)-2]) + } else { + h.Print(indentString) + } +} + +func (h *HTMLWriter) dumpNodeHTML(n Node, depth int) { + hasChildren := nodeHasChildren(n) + h.indentForToggle(depth, hasChildren) + + if depth > 40 { + h.Print("...") + return + } + + if n == nil { + h.Print("NilIrNode") + return + } + + // For HTML, we want to wrap the node and its details in a span that can be highlighted + // across all occurrences of the span in all columns, so it has to be linked to the node ID, + // which is its address. Canonicalize the address to a counter so that repeated compiler + // runs yield the same html. + // + // JS Equivalence logic: + // var c = elem.classList.item(0); + // var x = document.getElementsByClassName(c); + // + // Tag each class with its canonicalized index. + + h.Printf("", h.CanonId(n)) + defer h.Printf("") + + if hasChildren { + h.Print(`` + DownArrow + ` `) // NOTE TRAILING SPACE after ! + } + + if len(n.Init()) != 0 { + h.Print(``) + h.Printf("%+v-init", n.Op()) + h.dumpNodesHTML(n.Init(), depth+1) + h.indent(depth) + h.Print(``) + } + + switch n.Op() { + default: + h.Printf("%+v", n.Op()) + h.dumpNodeHeaderHTML(n) + + case OLITERAL: + h.Printf("%+v-%v", n.Op(), html.EscapeString(fmt.Sprintf("%v", n.Val()))) + h.dumpNodeHeaderHTML(n) + return + + case ONAME, ONONAME: + if n.Sym() != nil { + // Name highlighting: + // Create a hash for the symbol name to use as a class + // We use the same irValueClicked logic which uses the first class as the identifier + name := fmt.Sprintf("%v", n.Sym()) + hash := sha256.Sum256([]byte(name)) + symID := "sym-" + hex.EncodeToString(hash[:6]) + h.Printf("%+v-%+v", n.Op(), symID, html.EscapeString(name)) + } else { + h.Printf("%+v", n.Op()) + } + h.dumpNodeHeaderHTML(n) + return + + case OLINKSYMOFFSET: + n := n.(*LinksymOffsetExpr) + h.Printf("%+v-%v", n.Op(), html.EscapeString(fmt.Sprintf("%v", n.Linksym))) + if n.Offset_ != 0 { + h.Printf("%+v", n.Offset_) + } + h.dumpNodeHeaderHTML(n) + + case OASOP: + n := n.(*AssignOpStmt) + h.Printf("%+v-%+v", n.Op(), n.AsOp) + h.dumpNodeHeaderHTML(n) + + case OTYPE: + h.Printf("%+v %+v", n.Op(), html.EscapeString(fmt.Sprintf("%v", n.Sym()))) + h.dumpNodeHeaderHTML(n) + return + + case OCLOSURE: + h.Printf("%+v", n.Op()) + h.dumpNodeHeaderHTML(n) + + case ODCLFUNC: + n := n.(*Func) + h.Printf("%+v", n.Op()) + h.dumpNodeHeaderHTML(n) + if hasChildren { + h.Print(``) + defer h.Print(``) + } + fn := n + if len(fn.Dcl) > 0 { + h.indent(depth) + h.Printf("%+v-Dcl", n.Op()) + for _, dcl := range n.Dcl { + h.dumpNodeHTML(dcl, depth+1) + } + } + if len(fn.ClosureVars) > 0 { + h.indent(depth) + h.Printf("%+v-ClosureVars", n.Op()) + for _, cv := range fn.ClosureVars { + h.dumpNodeHTML(cv, depth+1) + } + } + if len(fn.Body) > 0 { + h.indent(depth) + h.Printf("%+v-body", n.Op()) + h.dumpNodesHTML(fn.Body, depth+1) + } + return + } + if hasChildren { + h.Print(``) + defer h.Print(``) + } + + v := reflect.ValueOf(n).Elem() + t := reflect.TypeOf(n).Elem() + nf := t.NumField() + for i := 0; i < nf; i++ { + tf := t.Field(i) + vf := v.Field(i) + if tf.PkgPath != "" { + continue + } + switch tf.Type.Kind() { + case reflect.Interface, reflect.Ptr, reflect.Slice: + if vf.IsNil() { + continue + } + } + name := strings.TrimSuffix(tf.Name, "_") + switch name { + case "X", "Y", "Index", "Chan", "Value", "Call": + name = "" + } + switch val := vf.Interface().(type) { + case Node: + if name != "" { + h.indent(depth) + h.Printf("%+v-%s", n.Op(), name) + } + h.dumpNodeHTML(val, depth+1) + case Nodes: + if len(val) == 0 { + continue + } + if name != "" { + h.indent(depth) + h.Printf("%+v-%s", n.Op(), name) + } + h.dumpNodesHTML(val, depth+1) + default: + if vf.Kind() == reflect.Slice && vf.Type().Elem().Implements(nodeType) { + if vf.Len() == 0 { + continue + } + if name != "" { + h.indent(depth) + h.Printf("%+v-%s", n.Op(), name) + } + for i, n := 0, vf.Len(); i < n; i++ { + h.dumpNodeHTML(vf.Index(i).Interface().(Node), depth+1) + } + } + } + } +} + +func nodeHasChildren(n Node) bool { + if n == nil { + return false + } + if len(n.Init()) != 0 { + return true + } + switch n.Op() { + case OLITERAL, ONAME, ONONAME, OTYPE: + return false + case ODCLFUNC: + n := n.(*Func) + return len(n.Dcl) > 0 || len(n.ClosureVars) > 0 || len(n.Body) > 0 + } + + v := reflect.ValueOf(n).Elem() + t := reflect.TypeOf(n).Elem() + nf := t.NumField() + for i := 0; i < nf; i++ { + tf := t.Field(i) + vf := v.Field(i) + if tf.PkgPath != "" { + continue + } + switch tf.Type.Kind() { + case reflect.Interface, reflect.Ptr, reflect.Slice: + if vf.IsNil() { + continue + } + } + switch val := vf.Interface().(type) { + case Node: + return true + case Nodes: + if len(val) > 0 { + return true + } + default: + if vf.Kind() == reflect.Slice && vf.Type().Elem().Implements(nodeType) { + if vf.Len() > 0 { + return true + } + } + } + } + return false +} + +func (h *HTMLWriter) dumpNodeHeaderHTML(n Node) { + // print pointer to be able to see identical nodes + if base.Debug.DumpPtrs != 0 { + h.Printf(" p(%p)", n) + } + + if base.Debug.DumpPtrs != 0 && n.Name() != nil && n.Name().Defn != nil { + h.Printf(" defn(%p)", n.Name().Defn) + } + + if base.Debug.DumpPtrs != 0 && n.Name() != nil && n.Name().Curfn != nil { + h.Printf(" curfn(%p)", n.Name().Curfn) + } + if base.Debug.DumpPtrs != 0 && n.Name() != nil && n.Name().Outer != nil { + h.Printf(" outer(%p)", n.Name().Outer) + } + + if EscFmt != nil { + if esc := EscFmt(n); esc != "" { + h.Printf(" %s", html.EscapeString(esc)) + } + } + + if n.Sym() != nil && n.Op() != ONAME && n.Op() != ONONAME && n.Op() != OTYPE { + h.Printf(" %+v", html.EscapeString(fmt.Sprintf("%v", n.Sym()))) + } + + v := reflect.ValueOf(n).Elem() + t := v.Type() + nf := t.NumField() + for i := 0; i < nf; i++ { + tf := t.Field(i) + if tf.PkgPath != "" { + continue + } + k := tf.Type.Kind() + if reflect.Bool <= k && k <= reflect.Complex128 { + name := strings.TrimSuffix(tf.Name, "_") + vf := v.Field(i) + vfi := vf.Interface() + if name == "Offset" && vfi == types.BADWIDTH || name != "Offset" && vf.IsZero() { + continue + } + if vfi == true { + h.Printf(" %s", name) + } else { + h.Printf(" %s:%+v", name, html.EscapeString(fmt.Sprintf("%v", vf.Interface()))) + } + } + } + + v = reflect.ValueOf(n) + t = v.Type() + nm := t.NumMethod() + for i := 0; i < nm; i++ { + tm := t.Method(i) + if tm.PkgPath != "" { + continue + } + m := v.Method(i) + mt := m.Type() + if mt.NumIn() == 0 && mt.NumOut() == 1 && mt.Out(0).Kind() == reflect.Bool { + func() { + defer func() { recover() }() + if m.Call(nil)[0].Bool() { + name := strings.TrimSuffix(tm.Name, "_") + h.Printf(" %s", name) + } + }() + } + } + + if n.Op() == OCLOSURE { + n := n.(*ClosureExpr) + if fn := n.Func; fn != nil && fn.Nname.Sym() != nil { + h.Printf(" fnName(%+v)", html.EscapeString(fmt.Sprintf("%v", fn.Nname.Sym()))) + } + } + + if n.Type() != nil { + if n.Op() == OTYPE { + h.Printf(" type") + } + h.Printf(" %+v", html.EscapeString(fmt.Sprintf("%v", n.Type()))) + } + if n.Typecheck() != 0 { + h.Printf(" tc(%d)", n.Typecheck()) + } + + if n.Pos().IsKnown() { + h.Print(" ") + switch n.Pos().IsStmt() { + case src.PosNotStmt: + h.Print("_") + case src.PosIsStmt: + h.Print("+") + } + sep := "" + base.Ctxt.AllPos(n.Pos(), func(pos src.Pos) { + h.Print(sep) + sep = " " + // Hierarchical highlighting: + // Click file -> highlight all ranges in this file + // Click line -> highlight all ranges at this line (in this file) + // Click col -> highlight this specific range + + file := pos.Filename() + // Create a hash for the filename to use as a class + hash := sha256.Sum256([]byte(file)) + fileID := "loc-" + hex.EncodeToString(hash[:6]) + lineID := fmt.Sprintf("%s-L%d", fileID, pos.Line()) + colID := fmt.Sprintf("%s-C%d", lineID, pos.Col()) + + // File part: triggers fileID + h.Printf("%s:", fileID, html.EscapeString(filepath.Base(file))) + // Line part: triggers lineID (and fileID via class list) + h.Printf("%d:", lineID, fileID, pos.Line()) + // Col part: triggers colID (and lineID, fileID) + h.Printf("%d", colID, lineID, fileID, pos.Col()) + }) + h.Print("") + } +} + +const CSS = ` +` + +// safePhaseNameString is a very conservative limit on phase names +// that can safely be encoded as JavaScript strings by wrapping with +// double-quotes. +var safePhaseNameString = regexp.MustCompile("^[a-zA-Z0-9_ .]+$") + +func JS(opened ...string) string { + var middle strings.Builder + + // "bloop", + // "loopvar", + // "escape", + // "slice", + // "walk", + + // This is only for default-display purposes, and the expected strings + // are the names of compiler phases. If a wonky name is rejected, the + // "harm" is that a pane in the debugging display is not pre-opened. + for _, s := range opened { + if !safePhaseNameString.MatchString(s) { + continue + } + middle.WriteString("\t\"") + middle.WriteString(s) + middle.WriteString("\",\n") + } + return JS1 + middle.String() + JS2 +} + +const ( + JS1 = ` +` +) diff --git a/src/cmd/compile/internal/ir/html_test.go b/src/cmd/compile/internal/ir/html_test.go new file mode 100644 index 00000000000000..c15adcc9acf0a9 --- /dev/null +++ b/src/cmd/compile/internal/ir/html_test.go @@ -0,0 +1,104 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ir + +import ( + "cmd/compile/internal/base" + "cmd/compile/internal/types" + "cmd/internal/obj" + "cmd/internal/src" + "os" + "path/filepath" + "strings" + "testing" +) + +func TestHTMLWriter(t *testing.T) { + // Initialize base.Ctxt to avoid panics + base.Ctxt = new(obj.Link) + + // Setup a temporary directory for output + tmpDir := t.TempDir() + + // Mock func + fn := &Func{ + Nname: &Name{ + sym: &types.Sym{Name: "TestFunc"}, + }, + } + // Func embeds miniExpr, so we might need to set op if checked + fn.op = ODCLFUNC + + // Create HTMLWriter + outFile := filepath.Join(tmpDir, "test.html") + w := NewHTMLWriter(outFile, fn, "") + if w == nil { + t.Fatalf("Failed to create HTMLWriter") + } + + // Write a phase + w.WritePhase("phase1", "Phase 1") + + // Register a file/line + posBase := src.NewFileBase("test.go", "test.go") + // base.Ctxt.PosTable.Register(posBase) -- Not needed/doesn't exist + pos := src.MakePos(posBase, 10, 1) + + // Create a dummy node + n := &Name{ + sym: &types.Sym{Name: "VarX"}, + Class: PAUTO, + } + n.op = ONAME + n.pos = base.Ctxt.PosTable.XPos(pos) + + // Add another phase which actually dumps something interesting + fn.Body = []Node{n} + w.WritePhase("phase2", "Phase 2") + + // Test escaping + n2 := &Name{ + sym: &types.Sym{Name: ""}, + Class: PAUTO, + } + n2.op = ONAME + fn.Body = []Node{n2} + w.WritePhase("phase3", "Phase 3") + + w.Close("Writing html ast output for %s to %s\n", PkgFuncName(w.Func), w.path) + + // Verify file exists and has content + content, err := os.ReadFile(outFile) + if err != nil { + t.Fatalf("Failed to read output file: %v", err) + } + + s := string(content) + if len(s) == 0 { + t.Errorf("Output file is empty") + } + + // Check for Expected strings + expected := []string{ + "", + "Phase 1", + "Phase 2", + "Phase 2", + "VarX", + "NAME", + "<Bad>", + "resizer", + "loc-", + "line-number", + "sym-", + "variable-name", + } + + for _, e := range expected { + if !strings.Contains(s, e) { + t.Errorf("Output missing %q", e) + } + } +} diff --git a/src/cmd/compile/internal/ir/name.go b/src/cmd/compile/internal/ir/name.go index 6f8d0a7fcc1989..cf5ec8ec487c5a 100644 --- a/src/cmd/compile/internal/ir/name.go +++ b/src/cmd/compile/internal/ir/name.go @@ -43,8 +43,8 @@ type Name struct { Func *Func // TODO(austin): nil for I.M Offset_ int64 val constant.Value - Opt interface{} // for use by escape analysis - Embed *[]Embed // list of embedded files, for ONAME var + Opt any // for use by escape or slice analysis + Embed *[]Embed // list of embedded files, for ONAME var // For a local variable (not param) or extern, the initializing assignment (OAS or OAS2). // For a closure var, the ONAME node of the original (outermost) captured variable. @@ -167,6 +167,10 @@ func (*Name) CanBeNtype() {} func (*Name) CanBeAnSSASym() {} func (*Name) CanBeAnSSAAux() {} +// DiagName returns the symbol name for diagnostics. +// XXX should it be part of the formatter? +func (n *Name) DiagName() string { return obj.TrimInlineHash(fmt.Sprint(n.Sym())) } + // Pragma returns the PragmaFlag for p, which must be for an OTYPE. func (n *Name) Pragma() PragmaFlag { return n.pragma } diff --git a/src/cmd/compile/internal/ir/node.go b/src/cmd/compile/internal/ir/node.go index 8c61bb6ed5a481..509a47e3c970b6 100644 --- a/src/cmd/compile/internal/ir/node.go +++ b/src/cmd/compile/internal/ir/node.go @@ -18,6 +18,9 @@ import ( // A Node is the abstract interface to an IR node. type Node interface { // Formatting + // For debugging output, use one of + // Dump/FDump/DumpList/FDumplist (in fmt.go) + // DumpAny/FDumpAny (in dump.go) Format(s fmt.State, verb rune) // Source position. @@ -293,6 +296,7 @@ const ( OLINKSYMOFFSET // offset within a name OJUMPTABLE // A jump table structure for implementing dense expression switches OINTERFACESWITCH // A type switch with interface cases + OMOVE2HEAP // Promote a stack-backed slice to heap // opcodes for generics ODYNAMICDOTTYPE // x = i.(T) where T is a type parameter (or derived from a type parameter) diff --git a/src/cmd/compile/internal/ir/node_gen.go b/src/cmd/compile/internal/ir/node_gen.go index 2221045c93d215..2ae0a43e49617c 100644 --- a/src/cmd/compile/internal/ir/node_gen.go +++ b/src/cmd/compile/internal/ir/node_gen.go @@ -1175,6 +1175,40 @@ func (n *MakeExpr) editChildrenWithHidden(edit func(Node) Node) { } } +func (n *MoveToHeapExpr) Format(s fmt.State, verb rune) { fmtNode(n, s, verb) } +func (n *MoveToHeapExpr) copy() Node { + c := *n + c.init = copyNodes(c.init) + return &c +} +func (n *MoveToHeapExpr) doChildren(do func(Node) bool) bool { + if doNodes(n.init, do) { + return true + } + if n.Slice != nil && do(n.Slice) { + return true + } + if n.RType != nil && do(n.RType) { + return true + } + return false +} +func (n *MoveToHeapExpr) doChildrenWithHidden(do func(Node) bool) bool { + return n.doChildren(do) +} +func (n *MoveToHeapExpr) editChildren(edit func(Node) Node) { + editNodes(n.init, edit) + if n.Slice != nil { + n.Slice = edit(n.Slice).(Node) + } + if n.RType != nil { + n.RType = edit(n.RType).(Node) + } +} +func (n *MoveToHeapExpr) editChildrenWithHidden(edit func(Node) Node) { + n.editChildren(edit) +} + func (n *Name) Format(s fmt.State, verb rune) { fmtNode(n, s, verb) } func (n *NilExpr) Format(s fmt.State, verb rune) { fmtNode(n, s, verb) } diff --git a/src/cmd/compile/internal/ir/op_string.go b/src/cmd/compile/internal/ir/op_string.go index 7494beee4c58e0..6c1c99a35d840f 100644 --- a/src/cmd/compile/internal/ir/op_string.go +++ b/src/cmd/compile/internal/ir/op_string.go @@ -151,22 +151,24 @@ func _() { _ = x[OLINKSYMOFFSET-140] _ = x[OJUMPTABLE-141] _ = x[OINTERFACESWITCH-142] - _ = x[ODYNAMICDOTTYPE-143] - _ = x[ODYNAMICDOTTYPE2-144] - _ = x[ODYNAMICTYPE-145] - _ = x[OTAILCALL-146] - _ = x[OGETG-147] - _ = x[OGETCALLERSP-148] - _ = x[OEND-149] + _ = x[OMOVE2HEAP-143] + _ = x[ODYNAMICDOTTYPE-144] + _ = x[ODYNAMICDOTTYPE2-145] + _ = x[ODYNAMICTYPE-146] + _ = x[OTAILCALL-147] + _ = x[OGETG-148] + _ = x[OGETCALLERSP-149] + _ = x[OEND-150] } -const _Op_name = "XXXNAMENONAMETYPELITERALNILADDSUBORXORADDSTRADDRANDANDAPPENDBYTES2STRBYTES2STRTMPRUNES2STRSTR2BYTESSTR2BYTESTMPSTR2RUNESSLICE2ARRSLICE2ARRPTRASAS2AS2DOTTYPEAS2FUNCAS2MAPRAS2RECVASOPCALLCALLFUNCCALLMETHCALLINTERCAPCLEARCLOSECLOSURECOMPLITMAPLITSTRUCTLITARRAYLITSLICELITPTRLITCONVCONVIFACECONVNOPCOPYDCLDCLFUNCDELETEDOTDOTPTRDOTMETHDOTINTERXDOTDOTTYPEDOTTYPE2EQNELTLEGEGTDEREFINDEXINDEXMAPKEYSTRUCTKEYLENMAKEMAKECHANMAKEMAPMAKESLICEMAKESLICECOPYMULDIVMODLSHRSHANDANDNOTNEWNOTBITNOTPLUSNEGORORPANICPRINTPRINTLNPARENSENDSLICESLICEARRSLICESTRSLICE3SLICE3ARRSLICEHEADERSTRINGHEADERRECOVERRECVRUNESTRSELRECV2MINMAXREALIMAGCOMPLEXUNSAFEADDUNSAFESLICEUNSAFESLICEDATAUNSAFESTRINGUNSAFESTRINGDATAMETHEXPRMETHVALUEBLOCKBREAKCASECONTINUEDEFERFALLFORGOTOIFLABELGORANGERETURNSELECTSWITCHTYPESWINLCALLMAKEFACEITABIDATASPTRCFUNCCHECKNILRESULTINLMARKLINKSYMOFFSETJUMPTABLEINTERFACESWITCHDYNAMICDOTTYPEDYNAMICDOTTYPE2DYNAMICTYPETAILCALLGETGGETCALLERSPEND" +const _Op_name = "XXXNAMENONAMETYPELITERALNILADDSUBORXORADDSTRADDRANDANDAPPENDBYTES2STRBYTES2STRTMPRUNES2STRSTR2BYTESSTR2BYTESTMPSTR2RUNESSLICE2ARRSLICE2ARRPTRASAS2AS2DOTTYPEAS2FUNCAS2MAPRAS2RECVASOPCALLCALLFUNCCALLMETHCALLINTERCAPCLEARCLOSECLOSURECOMPLITMAPLITSTRUCTLITARRAYLITSLICELITPTRLITCONVCONVIFACECONVNOPCOPYDCLDCLFUNCDELETEDOTDOTPTRDOTMETHDOTINTERXDOTDOTTYPEDOTTYPE2EQNELTLEGEGTDEREFINDEXINDEXMAPKEYSTRUCTKEYLENMAKEMAKECHANMAKEMAPMAKESLICEMAKESLICECOPYMULDIVMODLSHRSHANDANDNOTNEWNOTBITNOTPLUSNEGORORPANICPRINTPRINTLNPARENSENDSLICESLICEARRSLICESTRSLICE3SLICE3ARRSLICEHEADERSTRINGHEADERRECOVERRECVRUNESTRSELRECV2MINMAXREALIMAGCOMPLEXUNSAFEADDUNSAFESLICEUNSAFESLICEDATAUNSAFESTRINGUNSAFESTRINGDATAMETHEXPRMETHVALUEBLOCKBREAKCASECONTINUEDEFERFALLFORGOTOIFLABELGORANGERETURNSELECTSWITCHTYPESWINLCALLMAKEFACEITABIDATASPTRCFUNCCHECKNILRESULTINLMARKLINKSYMOFFSETJUMPTABLEINTERFACESWITCHMOVE2HEAPDYNAMICDOTTYPEDYNAMICDOTTYPE2DYNAMICTYPETAILCALLGETGGETCALLERSPEND" -var _Op_index = [...]uint16{0, 3, 7, 13, 17, 24, 27, 30, 33, 35, 38, 44, 48, 54, 60, 69, 81, 90, 99, 111, 120, 129, 141, 143, 146, 156, 163, 170, 177, 181, 185, 193, 201, 210, 213, 218, 223, 230, 237, 243, 252, 260, 268, 274, 278, 287, 294, 298, 301, 308, 314, 317, 323, 330, 338, 342, 349, 357, 359, 361, 363, 365, 367, 369, 374, 379, 387, 390, 399, 402, 406, 414, 421, 430, 443, 446, 449, 452, 455, 458, 461, 467, 470, 473, 479, 483, 486, 490, 495, 500, 507, 512, 516, 521, 529, 537, 543, 552, 563, 575, 582, 586, 593, 601, 604, 607, 611, 615, 622, 631, 642, 657, 669, 685, 693, 702, 707, 712, 716, 724, 729, 733, 736, 740, 742, 747, 749, 754, 760, 766, 772, 778, 785, 793, 797, 802, 806, 811, 819, 825, 832, 845, 854, 869, 883, 898, 909, 917, 921, 932, 935} +var _Op_index = [...]uint16{0, 3, 7, 13, 17, 24, 27, 30, 33, 35, 38, 44, 48, 54, 60, 69, 81, 90, 99, 111, 120, 129, 141, 143, 146, 156, 163, 170, 177, 181, 185, 193, 201, 210, 213, 218, 223, 230, 237, 243, 252, 260, 268, 274, 278, 287, 294, 298, 301, 308, 314, 317, 323, 330, 338, 342, 349, 357, 359, 361, 363, 365, 367, 369, 374, 379, 387, 390, 399, 402, 406, 414, 421, 430, 443, 446, 449, 452, 455, 458, 461, 467, 470, 473, 479, 483, 486, 490, 495, 500, 507, 512, 516, 521, 529, 537, 543, 552, 563, 575, 582, 586, 593, 601, 604, 607, 611, 615, 622, 631, 642, 657, 669, 685, 693, 702, 707, 712, 716, 724, 729, 733, 736, 740, 742, 747, 749, 754, 760, 766, 772, 778, 785, 793, 797, 802, 806, 811, 819, 825, 832, 845, 854, 869, 878, 892, 907, 918, 926, 930, 941, 944} func (i Op) String() string { - if i >= Op(len(_Op_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_Op_index)-1 { return "Op(" + strconv.FormatInt(int64(i), 10) + ")" } - return _Op_name[_Op_index[i]:_Op_index[i+1]] + return _Op_name[_Op_index[idx]:_Op_index[idx+1]] } diff --git a/src/cmd/compile/internal/ir/reassignment.go b/src/cmd/compile/internal/ir/reassignment.go index ba14d078a2ff26..ff3d08cd5b1bbc 100644 --- a/src/cmd/compile/internal/ir/reassignment.go +++ b/src/cmd/compile/internal/ir/reassignment.go @@ -6,6 +6,7 @@ package ir import ( "cmd/compile/internal/base" + "cmd/compile/internal/types" ) // A ReassignOracle efficiently answers queries about whether local @@ -21,6 +22,15 @@ type ReassignOracle struct { // maps candidate name to its defining assignment (or // for params, defining func). singleDef map[*Name]Node + + // funcAssigns tracks all known simple assignments (OAS) to + // func-typed PAUTO variables. Only func-typed variables are + // tracked because this data is used exclusively for callee + // resolution in escape analysis. Deletion means the candidate was + // invalidated (e.g., addr-taken, non-simple assignment form, or too + // many assignments). Assignments inside nested closures are accepted + // because the only alternative value is nil, which panics on call. + funcAssigns map[*Name][]*AssignStmt } // Init initializes the oracle based on the IR in function fn, laying @@ -33,6 +43,7 @@ func (ro *ReassignOracle) Init(fn *Func) { // Collect candidate map. Start by adding function parameters // explicitly. ro.singleDef = make(map[*Name]Node) + ro.funcAssigns = make(map[*Name][]*AssignStmt) sig := fn.Type() numParams := sig.NumRecvs() + sig.NumParams() for _, param := range fn.Dcl[:numParams] { @@ -48,8 +59,21 @@ func (ro *ReassignOracle) Init(fn *Func) { var findLocals func(n Node) bool findLocals = func(n Node) bool { if nn, ok := n.(*Name); ok { - if nn.Defn != nil && !nn.Addrtaken() && nn.Class == PAUTO { - ro.singleDef[nn] = nn.Defn + if nn.Class == PAUTO && !nn.Addrtaken() { + isFunc := nn.Type().Kind() == types.TFUNC + if nn.Defn == nil { + // Bare declaration (e.g., "var f func()"). + if isFunc { + ro.funcAssigns[nn] = nil + } + } else if _, ok := nn.Defn.(*AssignStmt); ok { + ro.singleDef[nn] = nn.Defn + if isFunc { + ro.funcAssigns[nn] = nil + } + } else { + ro.singleDef[nn] = nn.Defn + } } } else if nn, ok := n.(*ClosureExpr); ok { Any(nn.Func, findLocals) @@ -71,26 +95,35 @@ func (ro *ReassignOracle) Init(fn *Func) { // pruneIfNeeded examines node nn appearing on the left hand side // of assignment statement asn to see if it contains a reassignment - // to any nodes in our candidate map ro.singleDef; if a reassignment - // is found, the corresponding name is deleted from singleDef. + // to any nodes in our candidate maps; if a reassignment is found, + // the corresponding name is deleted. pruneIfNeeded := func(nn Node, asn Node) { oname := outerName(nn) if oname == nil { return } - defn, ok := ro.singleDef[oname] - if !ok { - return + if defn, ok := ro.singleDef[oname]; ok { + // any assignment to a param invalidates the entry. + paramAssigned := oname.Class == PPARAM + // assignment to local ok iff assignment is its orig def. + localAssigned := (oname.Class == PAUTO && asn != defn) + if paramAssigned || localAssigned { + // We found an assignment to name N that doesn't + // correspond to its original definition; remove + // from candidates. + delete(ro.singleDef, oname) + } } - // any assignment to a param invalidates the entry. - paramAssigned := oname.Class == PPARAM - // assignment to local ok iff assignment is its orig def. - localAssigned := (oname.Class == PAUTO && asn != defn) - if paramAssigned || localAssigned { - // We found an assignment to name N that doesn't - // correspond to its original definition; remove - // from candidates. - delete(ro.singleDef, oname) + if _, ok := ro.funcAssigns[oname]; ok { + as, isOAS := asn.(*AssignStmt) + if isOAS && isNilAssign(as) { + // Zero-value assignment (nil, bare decl), skip. + } else if !isOAS { + // Not a simple assignment: invalidate. + delete(ro.funcAssigns, oname) + } else { + ro.funcAssigns[oname] = append(ro.funcAssigns[oname], as) + } } } @@ -139,6 +172,11 @@ func (ro *ReassignOracle) StaticValue(n Node) Node { continue } + if n.Op() == OPAREN { + n = n.(*ParenExpr).X + continue + } + n1 := ro.staticValue1(n) if n1 == nil { if consistencyCheckEnabled { @@ -203,3 +241,26 @@ func (ro *ReassignOracle) Reassigned(n *Name) bool { } return result } + +// FuncAssignments returns all known simple assignments to a func-typed +// variable. For variables defined with := and a non-zero value, the +// defining assignment is included. Returns nil if the variable is not +// func-typed, was invalidated (addr-taken, non-simple assignment, +// too many assignments), or has no tracked assignments. Assignments +// inside nested closures are accepted because the only alternative +// value is nil, which panics on call. +func (ro *ReassignOracle) FuncAssignments(name *Name) []*AssignStmt { + return ro.funcAssigns[name.Canonical()] +} + +// isNilAssign reports whether as has a nil or absent RHS. +func isNilAssign(as *AssignStmt) bool { + if as.Y == nil { + return true + } + y := as.Y + for y.Op() == OCONVNOP { + y = y.(*ConvExpr).X + } + return IsNil(y) +} diff --git a/src/cmd/compile/internal/ir/sizeof_test.go b/src/cmd/compile/internal/ir/sizeof_test.go index 14b6b4f3cd4750..b805155e6e3b79 100644 --- a/src/cmd/compile/internal/ir/sizeof_test.go +++ b/src/cmd/compile/internal/ir/sizeof_test.go @@ -16,9 +16,9 @@ func TestSizeof(t *testing.T) { const _64bit = unsafe.Sizeof(uintptr(0)) == 8 var tests = []struct { - val interface{} // type as a value - _32bit uintptr // size on 32bit platforms - _64bit uintptr // size on 64bit platforms + val any // type as a value + _32bit uintptr // size on 32bit platforms + _64bit uintptr // size on 64bit platforms }{ {Func{}, 184, 312}, {Name{}, 96, 160}, diff --git a/src/cmd/compile/internal/ir/stmt.go b/src/cmd/compile/internal/ir/stmt.go index 0801ecdd9e8722..affa5f4551e450 100644 --- a/src/cmd/compile/internal/ir/stmt.go +++ b/src/cmd/compile/internal/ir/stmt.go @@ -42,6 +42,7 @@ func (*Decl) isStmt() {} type Stmt interface { Node isStmt() + PtrInit() *Nodes } // A miniStmt is a miniNode with extra fields common to statements. diff --git a/src/cmd/compile/internal/ir/symtab.go b/src/cmd/compile/internal/ir/symtab.go index f8eb4578809312..57cde66fb5601c 100644 --- a/src/cmd/compile/internal/ir/symtab.go +++ b/src/cmd/compile/internal/ir/symtab.go @@ -29,12 +29,20 @@ type symsStruct struct { GCWriteBarrier [8]*obj.LSym Goschedguarded *obj.LSym Growslice *obj.LSym + GrowsliceBuf *obj.LSym + GrowsliceBufNoAlias *obj.LSym + GrowsliceNoAlias *obj.LSym + MoveSlice *obj.LSym + MoveSliceNoScan *obj.LSym + MoveSliceNoCap *obj.LSym + MoveSliceNoCapNoScan *obj.LSym InterfaceSwitch *obj.LSym MallocGC *obj.LSym - MallocGCSmallNoScan [27]*obj.LSym - MallocGCSmallScanNoHeader [27]*obj.LSym - MallocGCTiny [16]*obj.LSym + MallocGCTiny *obj.LSym + MallocGCSmallNoScan [8]*obj.LSym + MallocGCSmallScanNoHeader [8]*obj.LSym Memmove *obj.LSym + Memequal *obj.LSym Msanread *obj.LSym Msanwrite *obj.LSym Msanmove *obj.LSym @@ -48,6 +56,7 @@ type symsStruct struct { PanicdottypeI *obj.LSym Panicnildottype *obj.LSym Panicoverflow *obj.LSym + PanicSimdImm *obj.LSym Racefuncenter *obj.LSym Racefuncexit *obj.LSym Raceread *obj.LSym @@ -58,22 +67,24 @@ type symsStruct struct { WBZero *obj.LSym WBMove *obj.LSym // Wasm - SigPanic *obj.LSym - Staticuint64s *obj.LSym - Typedmemmove *obj.LSym - Udiv *obj.LSym - WriteBarrier *obj.LSym - Zerobase *obj.LSym - ZeroVal *obj.LSym - ARM64HasATOMICS *obj.LSym - ARMHasVFPv4 *obj.LSym - Loong64HasLAMCAS *obj.LSym - Loong64HasLAM_BH *obj.LSym - Loong64HasLSX *obj.LSym - RISCV64HasZbb *obj.LSym - X86HasFMA *obj.LSym - X86HasPOPCNT *obj.LSym - X86HasSSE41 *obj.LSym + SigPanic *obj.LSym + Staticuint64s *obj.LSym + Typedmemmove *obj.LSym + Udiv *obj.LSym + WriteBarrier *obj.LSym + Zerobase *obj.LSym + ZeroVal *obj.LSym + ARM64HasATOMICS *obj.LSym + ARMHasVFPv4 *obj.LSym + Loong64HasLAMCAS *obj.LSym + Loong64HasLAM_BH *obj.LSym + Loong64HasDBAR_HINTS *obj.LSym + Loong64HasLSX *obj.LSym + RISCV64HasZbb *obj.LSym + X86HasAVX *obj.LSym + X86HasFMA *obj.LSym + X86HasPOPCNT *obj.LSym + X86HasSSE41 *obj.LSym // Wasm WasmDiv *obj.LSym // Wasm diff --git a/src/cmd/compile/internal/liveness/arg.go b/src/cmd/compile/internal/liveness/arg.go index 77960f5e15a1f9..69ead6ecc5fdc8 100644 --- a/src/cmd/compile/internal/liveness/arg.go +++ b/src/cmd/compile/internal/liveness/arg.go @@ -132,7 +132,7 @@ func ArgLiveness(fn *ir.Func, f *ssa.Func, pp *objw.Progs) (blockIdx, valueIdx m } nargs := int32(len(lv.args)) - bulk := bitvec.NewBulk(nargs, int32(len(f.Blocks)*2), fn.Pos()) + bulk := bitvec.NewBulk(nargs, int32(len(f.Blocks)*2)) for _, b := range f.Blocks { be := &lv.be[b.ID] be.livein = bulk.Next() @@ -316,6 +316,7 @@ func (lv *argLiveness) emit() *obj.LSym { lsym := base.Ctxt.Lookup(lv.fn.LSym.Name + ".argliveinfo") lsym.Set(obj.AttrContentAddressable, true) + lsym.Align = 1 off := objw.Uint8(lsym, 0, argOffsets[0]) // smallest offset that needs liveness info. for idx, live := range livenessMaps { diff --git a/src/cmd/compile/internal/liveness/mergelocals.go b/src/cmd/compile/internal/liveness/mergelocals.go index 6967ee016ee710..b9be0dd4c9768d 100644 --- a/src/cmd/compile/internal/liveness/mergelocals.go +++ b/src/cmd/compile/internal/liveness/mergelocals.go @@ -513,8 +513,26 @@ func (cs *cstate) populateIndirectUseTable(cands []*ir.Name) ([]*ir.Name, []cand } } } - for _, arg := range v.Args { + for idx, arg := range v.Args { if nc, ok := pendingUses[arg.ID]; ok { + if !v.AddrSinkArg(idx) { + // If this op may propagate its input address + // to somewhere else, we must track where that + // somewhere else might be. See issue 80127. + if v.Type.IsMemory() { + // Might be stored to memory. Give up. + continue + } + // Some sort of address arithmetic. + if _, ok := pendingUses[v.ID]; ok { + // v has used multiple addresses, which is something + // we can't keep track of. Give up. + continue + } + // Treat this op as producing the address of the same variable + // that its argument was the address of. + pendingUses[v.ID] = nameCount{n: nc.n, count: v.Uses} + } // We found a use of some value that took the // address of nc.n. Record this inst as a // potential indirect use. diff --git a/src/cmd/compile/internal/liveness/plive.go b/src/cmd/compile/internal/liveness/plive.go index 9b8f15e9c276f7..02643fa352efde 100644 --- a/src/cmd/compile/internal/liveness/plive.go +++ b/src/cmd/compile/internal/liveness/plive.go @@ -17,6 +17,7 @@ package liveness import ( "cmp" "fmt" + "math" "os" "slices" "sort" @@ -427,7 +428,7 @@ func newliveness(fn *ir.Func, f *ssa.Func, vars []*ir.Name, idx map[*ir.Name]int nblocks := int32(len(f.Blocks)) nvars := int32(len(vars)) - bulk := bitvec.NewBulk(nvars, nblocks*7, fn.Pos()) + bulk := bitvec.NewBulk(nvars, nblocks*4) for _, b := range f.Blocks { be := lv.blockEffects(b) @@ -1367,6 +1368,10 @@ func (lv *Liveness) emit() (argsSym, liveSym *obj.LSym) { loff := objw.Uint32(&liveSymTmp, 0, uint32(len(lv.stackMaps))) // number of bitmaps loff = objw.Uint32(&liveSymTmp, loff, uint32(locals.N)) // number of bits in each bitmap + // Check for overflow before serializing stackmaps + checkStackmapOverflow(args, len(lv.stackMaps), lv.fn.Pos()) + checkStackmapOverflow(locals, len(lv.stackMaps), lv.fn.Pos()) + for _, live := range lv.stackMaps { args.Clear() locals.Clear() @@ -1473,6 +1478,7 @@ func (lv *Liveness) emitStackObjects() *obj.LSym { // Format must match runtime/stack.go:stackObjectRecord. x := base.Ctxt.Lookup(lv.fn.LSym.Name + ".stkobj") x.Set(obj.AttrContentAddressable, true) + x.Align = int16(types.PtrSize) // see https://go.dev/issue/80668 lv.fn.LSym.Func().StackObjects = x off := 0 off = objw.Uintptr(x, off, uint64(len(vars))) @@ -1534,6 +1540,9 @@ func isfat(t *types.Type) bool { } return true case types.TSTRUCT: + if t.IsSIMD() { + return false + } // Struct with 1 field, check if field is fat if t.NumFields() == 1 { return isfat(t.Field(0).Type) @@ -1563,6 +1572,10 @@ func WriteFuncMap(fn *ir.Func, abiInfo *abi.ABIParamResultInfo) { if fn.Type().NumResults() > 0 { nbitmap = 2 } + + // defensive check: function arguments can't realistically be large enough for overflow here + checkStackmapOverflow(bv, nbitmap, fn.Pos()) + lsym := base.Ctxt.Lookup(fn.LSym.Name + ".args_stackmap") lsym.Set(obj.AttrLinkname, true) // allow args_stackmap referenced from assembly off := objw.Uint32(lsym, 0, uint32(nbitmap)) @@ -1580,3 +1593,18 @@ func WriteFuncMap(fn *ir.Func, abiInfo *abi.ABIParamResultInfo) { objw.Global(lsym, int32(off), obj.RODATA|obj.LOCAL) } + +// checkStackmapOverflow checks for potential overflow in runtime stackmap reading. +// Runtime computes: n * ((nbit+7)/8) using int32 arithmetic. +// See runtime.stackmapdata implementation. +func checkStackmapOverflow(bv bitvec.BitVec, count int, pos src.XPos) { + if bv.N <= 0 || count <= 0 { + return + } + bytesPerBitVec := (int64(bv.N) + 7) >> 3 + totalBytes := bytesPerBitVec * int64(count) + if totalBytes > math.MaxInt32 { + // runtime.stackmap has to support 64-bit values to avoid this restriction, see issue 77170 + base.FatalfAt(pos, "liveness stackmaps are too large: nbit=%d count=%d totalBytes=%d exceeds MaxInt32", bv.N, count, totalBytes) + } +} diff --git a/src/cmd/compile/internal/logopt/log_opts.go b/src/cmd/compile/internal/logopt/log_opts.go index d08f6fb5d6d92f..c47c9ee5afb23b 100644 --- a/src/cmd/compile/internal/logopt/log_opts.go +++ b/src/cmd/compile/internal/logopt/log_opts.go @@ -224,12 +224,12 @@ type Diagnostic struct { // A LoggedOpt is what the compiler produces and accumulates, // to be converted to JSON for human or IDE consumption. type LoggedOpt struct { - pos src.XPos // Source code position at which the event occurred. If it is inlined, outer and all inlined locations will appear in JSON. - lastPos src.XPos // Usually the same as pos; current exception is for reporting entire range of transformed loops - compilerPass string // Compiler pass. For human/adhoc consumption; does not appear in JSON (yet) - functionName string // Function name. For human/adhoc consumption; does not appear in JSON (yet) - what string // The (non) optimization; "nilcheck", "boundsCheck", "inline", "noInline" - target []interface{} // Optional target(s) or parameter(s) of "what" -- what was inlined, why it was not, size of copy, etc. 1st is most important/relevant. + pos src.XPos // Source code position at which the event occurred. If it is inlined, outer and all inlined locations will appear in JSON. + lastPos src.XPos // Usually the same as pos; current exception is for reporting entire range of transformed loops + compilerPass string // Compiler pass. For human/adhoc consumption; does not appear in JSON (yet) + functionName string // Function name. For human/adhoc consumption; does not appear in JSON (yet) + what string // The (non) optimization; "nilcheck", "boundsCheck", "inline", "noInline" + target []any // Optional target(s) or parameter(s) of "what" -- what was inlined, why it was not, size of copy, etc. 1st is most important/relevant. } type logFormat uint8 @@ -325,7 +325,7 @@ var mu = sync.Mutex{} // mu protects loggedOpts. // Pos is the source position (including inlining), what is the message, pass is which pass created the message, // funcName is the name of the function // A typical use for this to accumulate an explanation for a missed optimization, for example, why did something escape? -func NewLoggedOpt(pos, lastPos src.XPos, what, pass, funcName string, args ...interface{}) *LoggedOpt { +func NewLoggedOpt(pos, lastPos src.XPos, what, pass, funcName string, args ...any) *LoggedOpt { pass = strings.ReplaceAll(pass, " ", "_") return &LoggedOpt{pos, lastPos, pass, funcName, what, args} } @@ -333,7 +333,7 @@ func NewLoggedOpt(pos, lastPos src.XPos, what, pass, funcName string, args ...in // LogOpt logs information about a (usually missed) optimization performed by the compiler. // Pos is the source position (including inlining), what is the message, pass is which pass created the message, // funcName is the name of the function. -func LogOpt(pos src.XPos, what, pass, funcName string, args ...interface{}) { +func LogOpt(pos src.XPos, what, pass, funcName string, args ...any) { if Format == None { return } @@ -346,7 +346,7 @@ func LogOpt(pos src.XPos, what, pass, funcName string, args ...interface{}) { // LogOptRange is the same as LogOpt, but includes the ability to express a range of positions, // not just a point. -func LogOptRange(pos, lastPos src.XPos, what, pass, funcName string, args ...interface{}) { +func LogOptRange(pos, lastPos src.XPos, what, pass, funcName string, args ...any) { if Format == None { return } diff --git a/src/cmd/compile/internal/loong64/ssa.go b/src/cmd/compile/internal/loong64/ssa.go index 5e554282839d2e..090d3d186c53b4 100644 --- a/src/cmd/compile/internal/loong64/ssa.go +++ b/src/cmd/compile/internal/loong64/ssa.go @@ -187,6 +187,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpLOONG64DIVD, ssa.OpLOONG64MULV, ssa.OpLOONG64MULHV, ssa.OpLOONG64MULHVU, ssa.OpLOONG64MULH, ssa.OpLOONG64MULHU, ssa.OpLOONG64DIVV, ssa.OpLOONG64REMV, ssa.OpLOONG64DIVVU, ssa.OpLOONG64REMVU, + ssa.OpLOONG64MULWVW, ssa.OpLOONG64MULWVWU, ssa.OpLOONG64FCOPYSGD: p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REG @@ -528,6 +529,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpLOONG64BITREV4B, ssa.OpLOONG64BITREVW, ssa.OpLOONG64BITREVV, + ssa.OpLOONG64ABSF, ssa.OpLOONG64ABSD: p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REG @@ -537,7 +539,11 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { case ssa.OpLOONG64VPCNT64, ssa.OpLOONG64VPCNT32, - ssa.OpLOONG64VPCNT16: + ssa.OpLOONG64VPCNT16, + ssa.OpLOONG64FRINTND, + ssa.OpLOONG64FRINTZD, + ssa.OpLOONG64FRINTPD, + ssa.OpLOONG64FRINTMD: p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REG p.From.Reg = ((v.Args[0].Reg() - loong64.REG_F0) & 31) + loong64.REG_V0 @@ -574,7 +580,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { } case ssa.OpLOONG64LoweredZeroLoop: ptrReg := v.Args[0].Reg() - countReg := v.RegTmp() + endReg := v.RegTmp() + flagReg := int16(loong64.REGTMP) var off int64 n := v.AuxInt loopSize := int64(64) @@ -587,58 +594,109 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { // vs // 16 instuctions in the straightline code // Might as well use straightline code. - v.Fatalf("ZeroLoop size tool small %d", n) + v.Fatalf("ZeroLoop size too small %d", n) } - // Put iteration count in a register. - // MOVV $n/loopSize, countReg - p := s.Prog(loong64.AMOVV) - p.From.Type = obj.TYPE_CONST - p.From.Offset = n / loopSize - p.To.Type = obj.TYPE_REG - p.To.Reg = countReg - cntInit := p + // ADDV n - n%loopSize, ptrReg, endReg + // MOVBU ir.Syms.Loong64HasLSX, flagReg + // BNE flagReg, lsxInit + // genericLoop: + // for off = 0; off < loopSize; off += 8 { + // zero8(s, ptrReg, off) + // } + // ADDV $loopSize, ptrReg + // BNE endReg, ptrReg, genericLoop + // JMP tail + // lsxInit: + // VXORV V31, V31, V31 + // lsxLoop: + // for off = 0; off < loopSize; off += 16 { + // zero16(s, V31, ptrReg, off) + // } + // ADDV $loopSize, ptrReg + // BNE endReg, ptrReg, lsxLoop + // tail: + // n %= loopSize + // for off = 0; n >= 8; off += 8, n -= 8 { + // zero8(s, ptrReg, off) + // } + // + // if n != 0 { + // zero8(s, ptrReg, off+n-8) + // } + + p1 := s.Prog(loong64.AADDV) + p1.From.Type = obj.TYPE_CONST + p1.From.Offset = n - n%loopSize + p1.Reg = ptrReg + p1.To.Type = obj.TYPE_REG + p1.To.Reg = endReg - // Zero loopSize bytes starting at ptrReg. - for range loopSize / 8 { - // MOVV ZR, off(ptrReg) + p2 := s.Prog(loong64.AMOVBU) + p2.From.Type = obj.TYPE_MEM + p2.From.Name = obj.NAME_EXTERN + p2.From.Sym = ir.Syms.Loong64HasLSX + p2.To.Type = obj.TYPE_REG + p2.To.Reg = flagReg + + p3 := s.Prog(loong64.ABNE) + p3.From.Type = obj.TYPE_REG + p3.From.Reg = flagReg + p3.To.Type = obj.TYPE_BRANCH + + for off = 0; off < loopSize; off += 8 { zero8(s, ptrReg, off) - off += 8 } - // Increment ptrReg by loopSize. - // ADDV $loopSize, ptrReg - p = s.Prog(loong64.AADDV) - p.From.Type = obj.TYPE_CONST - p.From.Offset = loopSize - p.To.Type = obj.TYPE_REG - p.To.Reg = ptrReg + p4 := s.Prog(loong64.AADDV) + p4.From.Type = obj.TYPE_CONST + p4.From.Offset = loopSize + p4.To.Type = obj.TYPE_REG + p4.To.Reg = ptrReg - // Decrement loop count. - // SUBV $1, countReg - p = s.Prog(loong64.ASUBV) - p.From.Type = obj.TYPE_CONST - p.From.Offset = 1 - p.To.Type = obj.TYPE_REG - p.To.Reg = countReg + p5 := s.Prog(loong64.ABNE) + p5.From.Type = obj.TYPE_REG + p5.From.Reg = endReg + p5.Reg = ptrReg + p5.To.Type = obj.TYPE_BRANCH + p5.To.SetTarget(p3.Link) - // Jump to loop header if we're not done yet. - // BNE countReg, loop header - p = s.Prog(loong64.ABNE) - p.From.Type = obj.TYPE_REG - p.From.Reg = countReg - p.To.Type = obj.TYPE_BRANCH - p.To.SetTarget(cntInit.Link) + p6 := s.Prog(obj.AJMP) + p6.To.Type = obj.TYPE_BRANCH + + p7 := s.Prog(loong64.AVXORV) + p7.From.Type = obj.TYPE_REG + p7.From.Reg = loong64.REG_V31 + p7.To.Type = obj.TYPE_REG + p7.To.Reg = loong64.REG_V31 + p3.To.SetTarget(p7) + + for off = 0; off < loopSize; off += 16 { + zero16(s, loong64.REG_V31, ptrReg, off) + } + + p8 := s.Prog(loong64.AADDV) + p8.From.Type = obj.TYPE_CONST + p8.From.Offset = loopSize + p8.To.Type = obj.TYPE_REG + p8.To.Reg = ptrReg + + p9 := s.Prog(loong64.ABNE) + p9.From.Type = obj.TYPE_REG + p9.From.Reg = endReg + p9.Reg = ptrReg + p9.To.Type = obj.TYPE_BRANCH + p9.To.SetTarget(p7.Link) + + p10 := s.Prog(obj.ANOP) + p6.To.SetTarget(p10) // Multiples of the loop size are now done. n %= loopSize - - off = 0 // Write any fractional portion. - for n >= 8 { - // MOVV ZR, off(ptrReg) + for off = 0; n >= 8; off += 8 { + // MOVV ZR, off(ptrReg) zero8(s, ptrReg, off) - off += 8 n -= 8 } @@ -652,7 +710,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { if dstReg == srcReg { break } - tmpReg := int16(loong64.REG_R20) + tmpReg := int16(loong64.REG_R23) n := v.AuxInt if n < 16 { v.Fatalf("Move too small %d", n) @@ -678,8 +736,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { if dstReg == srcReg { break } - countReg := int16(loong64.REG_R20) - tmpReg := int16(loong64.REG_R21) + srcEndReg := int16(loong64.REG_R23) + tmpReg := int16(loong64.REG_R24) var off int64 n := v.AuxInt loopSize := int64(64) @@ -692,78 +750,74 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { // vs // 16 instructions in the straightline code // Might as well use straightline code. - v.Fatalf("ZeroLoop size too small %d", n) + v.Fatalf("MoveLoop size too small %d", n) } - // Put iteration count in a register. - // MOVV $n/loopSize, countReg - p := s.Prog(loong64.AMOVV) - p.From.Type = obj.TYPE_CONST - p.From.Offset = n / loopSize - p.To.Type = obj.TYPE_REG - p.To.Reg = countReg - cntInit := p + // ADDV n - n%loopSize, srcReg, srcEndReg + // Loop8: + // for off = 0; off < loopSize; off += 8 { + // move8(s, srcReg, dstReg, tmpReg, off) + // } + // ADDV $loopSize, srcReg + // ADDV $loopSize, dstReg + // BNE srcEndReg, srcReg, Loop8 + // + // n %= loopSize + // for off = 0; n >= 8; off += 8 { + // move8(s, srcReg, dstReg, tmpReg, off) + // n -= 8 + // } + // + // if n != 0 { + // move8(s, srcReg, dstReg, tmpReg, off+n-8) + // } + + p1 := s.Prog(loong64.AADDV) + p1.From.Type = obj.TYPE_CONST + p1.From.Offset = n - n%loopSize + p1.Reg = srcReg + p1.To.Type = obj.TYPE_REG + p1.To.Reg = srcEndReg - // Move loopSize bytes starting at srcReg to dstReg. - for range loopSize / 8 { - // MOVV off(srcReg), tmpReg - // MOVV tmpReg, off(dstReg) + for off = 0; off < loopSize; off += 8 { move8(s, srcReg, dstReg, tmpReg, off) - off += 8 } - // Increment srcReg and destReg by loopSize. - // ADDV $loopSize, srcReg - p = s.Prog(loong64.AADDV) - p.From.Type = obj.TYPE_CONST - p.From.Offset = loopSize - p.To.Type = obj.TYPE_REG - p.To.Reg = srcReg - // ADDV $loopSize, dstReg - p = s.Prog(loong64.AADDV) - p.From.Type = obj.TYPE_CONST - p.From.Offset = loopSize - p.To.Type = obj.TYPE_REG - p.To.Reg = dstReg + p2 := s.Prog(loong64.AADDV) + p2.From.Type = obj.TYPE_CONST + p2.From.Offset = loopSize + p2.To.Type = obj.TYPE_REG + p2.To.Reg = srcReg - // Decrement loop count. - // SUBV $1, countReg - p = s.Prog(loong64.ASUBV) - p.From.Type = obj.TYPE_CONST - p.From.Offset = 1 - p.To.Type = obj.TYPE_REG - p.To.Reg = countReg + p3 := s.Prog(loong64.AADDV) + p3.From.Type = obj.TYPE_CONST + p3.From.Offset = loopSize + p3.To.Type = obj.TYPE_REG + p3.To.Reg = dstReg - // Jump to loop header if we're not done yet. - // BNE countReg, loop header - p = s.Prog(loong64.ABNE) - p.From.Type = obj.TYPE_REG - p.From.Reg = countReg - p.To.Type = obj.TYPE_BRANCH - p.To.SetTarget(cntInit.Link) + p4 := s.Prog(loong64.ABNE) + p4.From.Type = obj.TYPE_REG + p4.From.Reg = srcEndReg + p4.Reg = srcReg + p4.To.Type = obj.TYPE_BRANCH + p4.To.SetTarget(p1.Link) // Multiples of the loop size are now done. n %= loopSize - off = 0 // Copy any fractional portion. - for n >= 8 { - // MOVV off(srcReg), tmpReg - // MOVV tmpReg, off(dstReg) + for off = 0; n >= 8; off += 8 { move8(s, srcReg, dstReg, tmpReg, off) - off += 8 n -= 8 } if n != 0 { - // MOVV off+n-8(srcReg), tmpReg - // MOVV tmpReg, off+n-8(srcReg) move8(s, srcReg, dstReg, tmpReg, off+n-8) } case ssa.OpLOONG64CALLstatic, ssa.OpLOONG64CALLclosure, ssa.OpLOONG64CALLinter: s.Call(v) - case ssa.OpLOONG64CALLtail: + case ssa.OpLOONG64CALLtail, ssa.OpLOONG64CALLtailinter: s.TailCall(v) case ssa.OpLOONG64LoweredWB: p := s.Prog(obj.ACALL) @@ -1333,7 +1387,7 @@ func move8(s *ssagen.State, src, dst, tmp int16, off int64) { // zero8 zeroes 8 bytes at reg+off. func zero8(s *ssagen.State, reg int16, off int64) { - // MOVV ZR, off(reg) + // MOVV ZR, off(reg) p := s.Prog(loong64.AMOVV) p.From.Type = obj.TYPE_REG p.From.Reg = loong64.REGZERO @@ -1341,3 +1395,14 @@ func zero8(s *ssagen.State, reg int16, off int64) { p.To.Reg = reg p.To.Offset = off } + +// zero16 zeroes 16 bytes at reg+off. +func zero16(s *ssagen.State, regZero, regBase int16, off int64) { + // VMOVQ regZero, off(regBase) + p := s.Prog(loong64.AVMOVQ) + p.From.Type = obj.TYPE_REG + p.From.Reg = regZero + p.To.Type = obj.TYPE_MEM + p.To.Reg = regBase + p.To.Offset = off +} diff --git a/src/cmd/compile/internal/loopvar/loopvar.go b/src/cmd/compile/internal/loopvar/loopvar.go index 5a4590d2998d0c..d2da412ed5263d 100644 --- a/src/cmd/compile/internal/loopvar/loopvar.go +++ b/src/cmd/compile/internal/loopvar/loopvar.go @@ -448,6 +448,11 @@ func ForCapture(fn *ir.Func) []VarAndLoop { } } ir.WithFunc(fn, forCapture) + + if ir.MatchAstDump(fn, "loopvar") { + ir.AstDump(fn, "loopvar, "+ir.FuncName(fn)) + } + return transformed } @@ -557,7 +562,7 @@ func LogTransformations(transformed []VarAndLoop) { if logopt.Enabled() { // For automated checking of coverage of this transformation, include this in the JSON information. - var nString interface{} = n + var nString any = n if inner != outer { nString = fmt.Sprintf("%v (from inline)", n) } diff --git a/src/cmd/compile/internal/loopvar/loopvar_test.go b/src/cmd/compile/internal/loopvar/loopvar_test.go index 0265dd06eec788..c4ff8f620dc5e6 100644 --- a/src/cmd/compile/internal/loopvar/loopvar_test.go +++ b/src/cmd/compile/internal/loopvar/loopvar_test.go @@ -6,6 +6,7 @@ package loopvar_test import ( "internal/testenv" + "os" "os/exec" "path/filepath" "regexp" @@ -381,3 +382,62 @@ func TestLoopVarVersionDisableGoBuild(t *testing.T) { t.Errorf("err=%v == nil", err) } } + +// TestLoopVarLineDirective tests that loopvar version detection works correctly +// with line directives. This is a regression test for a bug where FileBase() was +// used instead of Base(), causing incorrect version lookup when line directives +// were present. +func TestLoopVarLineDirective(t *testing.T) { + switch runtime.GOOS { + case "linux", "darwin": + default: + t.Skipf("Slow test, usually avoid it, os=%s not linux or darwin", runtime.GOOS) + } + switch runtime.GOARCH { + case "amd64", "arm64": + default: + t.Skipf("Slow test, usually avoid it, arch=%s not amd64 or arm64", runtime.GOARCH) + } + + testenv.MustHaveGoBuild(t) + gocmd := testenv.GoToolPath(t) + tmpdir := t.TempDir() + output := filepath.Join(tmpdir, "foo.exe") + + // Create a go.mod file with Go 1.21 to test compatibility behavior. + // When building with a higher Go compiler, the loopvar should be created per-loop. + gomodPath := filepath.Join(tmpdir, "go.mod") + if err := os.WriteFile(gomodPath, []byte("module test\n\ngo 1.21\n"), 0644); err != nil { + t.Fatal(err) + } + + // Copy the test file (with line directive) to the temporary module + testFile := "range_esc_closure_linedir.go" + srcPath := filepath.Join("testdata", testFile) + dstPath := filepath.Join(tmpdir, testFile) + src, err := os.ReadFile(srcPath) + if err != nil { + t.Fatal(err) + } + if err := os.WriteFile(dstPath, src, 0644); err != nil { + t.Fatal(err) + } + + // Build the module (not as a single file, so go.mod is respected) + cmd := testenv.Command(t, gocmd, "build", "-o", output, ".") + cmd.Dir = tmpdir + b, err := cmd.CombinedOutput() + if err != nil { + t.Logf("build output: %s", b) + t.Fatal(err) + } + t.Logf("build output: %s", b) + + cmd = testenv.Command(t, output) + b, err = cmd.CombinedOutput() + t.Logf("run output: %s", b) + + if err != nil { + t.Errorf("expected success (exit code 0), got: %v", err) + } +} diff --git a/src/cmd/compile/internal/loopvar/testdata/range_esc_closure_linedir.go b/src/cmd/compile/internal/loopvar/testdata/range_esc_closure_linedir.go new file mode 100644 index 00000000000000..24823e8990f29f --- /dev/null +++ b/src/cmd/compile/internal/loopvar/testdata/range_esc_closure_linedir.go @@ -0,0 +1,24 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//line range_esc_closure_linedir.go:5 +package main + +import "fmt" + +var is []func() int + +func main() { + var ints = []int{0, 0, 0} + for i := range ints { + is = append(is, func() int { return i }) + } + + for _, f := range is { + fmt.Println(f()) + if f() != 2 { + panic("loop variable i: expected shared per-loop, but got distinct per-iteration") + } + } +} diff --git a/src/cmd/compile/internal/midway/analysis.go b/src/cmd/compile/internal/midway/analysis.go new file mode 100644 index 00000000000000..ab7482161d6895 --- /dev/null +++ b/src/cmd/compile/internal/midway/analysis.go @@ -0,0 +1,296 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package midway + +import ( + "cmd/compile/internal/base" + "cmd/compile/internal/syntax" + "cmd/compile/internal/types2" +) + +// Analyzer holds the state for SIMD dependency analysis +type Analyzer struct { + pkg *types2.Package + info *types2.Info + isDependentObj map[types2.Object]bool // does an Object depend on a simd type in some way? + isDependentMethod map[types2.Object]bool // is this dependent Object also a method? (methods are not renamed, their types are) + hasDependentMethod map[types2.Type]bool // is this a type that has a dependent method? + visited map[types2.Type]bool // if in map, type has been visited, and value is whether type is dependent + inSimd bool // true if the current package is the simd package (which is a special case) +} + +func NewAnalyzer(pkg *types2.Package, info *types2.Info) *Analyzer { + return &Analyzer{ + pkg: pkg, + info: info, + isDependentObj: make(map[types2.Object]bool), + isDependentMethod: make(map[types2.Object]bool), + hasDependentMethod: make(map[types2.Type]bool), + visited: make(map[types2.Type]bool), + inSimd: pkg.Path() == simdPkg, + } +} + +// Analyze builds the set of SIMD-dependent objects +func (a *Analyzer) Analyze(files []*syntax.File) bool { + // Phase 1: Seed dependence from types and signatures + hdmsize := len(a.hasDependentMethod) + + for { + for _, obj := range a.info.Defs { + if obj != nil { + a.markIfDependent(obj) + } + } + for _, obj := range a.info.Uses { + if obj != nil { + a.markIfDependent(obj) + } + } + if hdmsize == len(a.hasDependentMethod) { + break + } + if base.Debug.Simd > 0 { + base.Warn("hasDependentMethod increased from %d to %d", hdmsize, len(a.hasDependentMethod)) + } + hdmsize = len(a.hasDependentMethod) + clear(a.visited) + } + + // Phase 2: Transitive closure via function bodies + changed := true + for changed { + changed = false + for _, file := range files { + for _, decl := range file.DeclList { + if fn, ok := decl.(*syntax.FuncDecl); ok { + if fn.Name == nil { + continue + } + obj := a.info.Defs[fn.Name] + if obj == nil || a.isDependentObj[obj] { + continue + } + + if a.hasBodyDependency(fn) { + a.isDependentObj[obj] = true + changed = true + } + } + } + } + } + + return len(a.isDependentObj) > 0 +} + +func (a *Analyzer) hasBodyDependency(fn *syntax.FuncDecl) bool { + if fn.Body == nil { + return false + } + // Walk the body and check identifiers + // This will also note any variable references that are dependent. + found := false + syntax.Inspect(fn.Body, func(n syntax.Node) bool { + if id, ok := n.(*syntax.Name); ok { + obj := a.info.Uses[id] + if obj == nil { + obj = a.info.Defs[id] + } + if obj != nil { + if _, isFunc := obj.(*types2.Func); !isFunc { + if a.isDependentObj[obj] { + found = true + return false + } + } else { + sig := obj.Type().(*types2.Signature) + if a.HasDependentSignature(sig) { + found = true + return false + } + } + if a.isDependentType(obj.Type()) { + // Whatever this is, it makes the outer object dependent. + // If this is a package variable with dependent type, mark the + // variable as dependent, so that references to it become dependent. + if obj, ok := obj.(*types2.Var); ok && obj.Kind() == types2.PackageVar { + // everything else is nested within a dependent function/struct/scope + // and does not need its own renaming + a.isDependentObj[obj] = true + } + found = true + return false + } + if isBaseSimdTypeObj(obj) { + found = true + return false + } + } + } + return true + }) + return found +} + +func (a *Analyzer) markIfDependent(obj types2.Object) bool { + if a.isDependentObj[obj] { + return true + } + + isDep := false + isDepMeth := false + switch obj := obj.(type) { + case *types2.Var: + if obj.Pkg() == a.pkg && obj.Parent() == a.pkg.Scope() { + isDep = a.isDependentType(obj.Type()) + } + case *types2.TypeName: + isDep = a.isDependentType(obj.Type()) + case *types2.Func: + sig := obj.Type().(*types2.Signature) + if a.HasDependentSignature(sig) { + // NOT dependent if it is a method of one of the base SIMD types. + // TODO: what about aliases of base SIMD types? + if rcv := sig.Recv(); rcv == nil { + isDep = true + } else if named, ok := rcv.Type().(*types2.Named); !ok || !isBaseSimdType(named) { + isDep = true + t := rcv.Type() + if !a.isDependentType(t) { + a.markHasMethod(t) + } + isDepMeth = true + } + } + } + + // Also check if obj name is "simd.Type" (base case) + if isBaseSimdTypeObj(obj) { + isDep = true + } + + if isDep { + if base.Debug.Simd > 0 { + base.Warn("%s: %v is simd-dependent", obj.Pos().String(), obj) + } + a.isDependentObj[obj] = true + } + if isDepMeth { + if base.Debug.Simd > 0 { + base.Warn("%s: %v is simd-dependent method", obj.Pos().String(), obj) + } + a.isDependentMethod[obj] = true + } + return isDep +} + +func (a *Analyzer) isDependentType(t types2.Type) bool { + return a.checkTypeRecursive(t) +} + +func (a *Analyzer) checkTypeRecursive(t types2.Type) bool { + if t == nil { + return false + } + if a.hasDependentMethod[t] { + a.visited[t] = true + } + if b, ok := a.visited[t]; ok { + return b // Break cycles + } + a.visited[t] = false + + memo := func(b bool) bool { + a.visited[t] = b + return b + } + + // Unwrap aliases + if named, ok := t.(*types2.Named); ok { + if isBaseSimdType(named) { + return memo(true) + } + if a.checkTypeRecursive(named.Underlying()) { + return memo(true) + } + } + + switch t := t.(type) { + case *types2.Basic: + return false + case *types2.Pointer: + return memo(a.checkTypeRecursive(t.Elem())) + case *types2.Slice: + return memo(a.checkTypeRecursive(t.Elem())) + case *types2.Array: + return memo(a.checkTypeRecursive(t.Elem())) + case *types2.Map: + return memo(a.checkTypeRecursive(t.Key()) || + a.checkTypeRecursive(t.Elem())) + case *types2.Chan: + return memo(a.checkTypeRecursive(t.Elem())) + case *types2.Struct: + for i := 0; i < t.NumFields(); i++ { + if a.checkTypeRecursive(t.Field(i).Type()) { + return memo(true) + } + } + case *types2.Signature: + return memo(a.HasDependentSignature(t)) + case *types2.Tuple: + for i := 0; i < t.Len(); i++ { + if a.checkTypeRecursive(t.At(i).Type()) { + return memo(true) + } + } + case *types2.Alias: + return memo(a.checkTypeRecursive(types2.Unalias(t))) + } + return false +} + +// This attempts to mark types that are not otherwise dependent +// as being dependent, if they have a method with a dependent +// signature. +func (a *Analyzer) markHasMethod(t types2.Type) { + if t == nil { + return + } + if a.hasDependentMethod[t] { + return + } + + a.hasDependentMethod[t] = true + + switch t := t.(type) { + case *types2.Pointer: + a.markHasMethod(t.Elem()) + case *types2.Alias: + a.markHasMethod(t.Rhs()) + } + return +} + +func isBaseSimdType(t *types2.Named) bool { + return isBaseSimdTypeObj(t.Obj()) +} + +func isBaseSimdTypeObj(obj types2.Object) bool { + if obj == nil || obj.Pkg() == nil { + return false + } + if obj.Pkg().Path() != simdPkg { + return false + } + return isSimdTypeName(obj.Name()) +} + +func (a *Analyzer) HasDependentSignature(sig *types2.Signature) bool { + // TODO what about type parameters? Need to invent a test that provokes that case. + return a.isDependentType(sig.Params()) || + a.isDependentType(sig.Results()) || + (sig.Recv() != nil && a.isDependentType(sig.Recv().Type())) +} diff --git a/src/cmd/compile/internal/midway/check.go b/src/cmd/compile/internal/midway/check.go new file mode 100644 index 00000000000000..b9809a7c00dd5a --- /dev/null +++ b/src/cmd/compile/internal/midway/check.go @@ -0,0 +1,27 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package midway + +import ( + "cmd/compile/internal/base" + "cmd/compile/internal/syntax" +) + +// CheckPositions checks that all nodes in the files have known positions. +// This converts lack-of-Pos into an early fatal error instead of a later +// weird downstream error (e.g., in the linker, in debugging information). +func CheckPositions(files []*syntax.File, phase string) { + for _, file := range files { + syntax.Inspect(file, func(n syntax.Node) bool { + if n == nil { + return true + } + if !n.Pos().IsKnown() { + base.Fatalf("Phase %s, Node without known position: %T\n", phase, n) + } + return true + }) + } +} diff --git a/src/cmd/compile/internal/midway/deepcopy.go b/src/cmd/compile/internal/midway/deepcopy.go new file mode 100644 index 00000000000000..99f6ef0a6f471f --- /dev/null +++ b/src/cmd/compile/internal/midway/deepcopy.go @@ -0,0 +1,627 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package midway + +import ( + "fmt" + "strings" + + "cmd/compile/internal/base" + "cmd/compile/internal/syntax" + "cmd/compile/internal/types2" +) + +// DeepCopier clones syntax nodes and maintains types2.Info mappings. +type DeepCopier struct { + VecLen int + info *types2.Info + pkg *types2.Package + analyzer *Analyzer + suffix string + + vars map[*types2.Var]*types2.Var +} + +func NewDeepCopier(pkg *types2.Package, info *types2.Info, vecLen int, analyzer *Analyzer, suffix string) *DeepCopier { + return &DeepCopier{ + VecLen: vecLen, + info: info, + pkg: pkg, + analyzer: analyzer, + suffix: suffix, + vars: make(map[*types2.Var]*types2.Var), + } +} + +func (c *DeepCopier) registerDef(newName *syntax.Name, oldName *syntax.Name) { + if oldName == nil || newName == nil { + return + } + if oldObj := c.info.Defs[oldName]; oldObj != nil { + if val, isVar := oldObj.(*types2.Var); isVar { + newObj := types2.NewVar(newName.Pos(), c.pkg, newName.Value, val.Type()) + c.vars[val] = newObj + c.info.Defs[newName] = newObj + } else { + c.info.Defs[newName] = oldObj + } + } +} + +func (c *DeepCopier) mapUse(newName *syntax.Name, oldName *syntax.Name) { + if oldName == nil || newName == nil { + return + } + if oldObj := c.info.Uses[oldName]; oldObj != nil { + if val, isVar := oldObj.(*types2.Var); isVar && c.vars[val] != nil { + c.info.Uses[newName] = c.vars[val] + } else { + c.info.Uses[newName] = oldObj + } + } +} + +// OnName rewrites "dependent" and SIMD names to their architecture-specific version. +func (c *DeepCopier) OnName(id *syntax.Name) *syntax.Name { + obj := c.info.Uses[id] + if obj == nil { + obj = c.info.Defs[id] + } + if obj == nil { + return nil + } + // Don't rename methods of dependent types + if c.analyzer.isDependentMethod[obj] { + return nil + } + + if c.analyzer.isDependentObj[obj] || isBaseSimdTypeObj(obj) { + newId := syntax.NewName(id.Pos(), id.Value+c.suffix) + // Object link will be handled manually in deepcopier Use/Def mapper + if base.Debug.Simd > 0 { + base.Warn("%s: rewriting name %s to %s", id.Pos().String(), id.Value, newId.Value) + } + return newId + } + return nil +} + +// OnNameExpr rewrites references to simd. into +// .. +func (c *DeepCopier) OnNameExpr(id *syntax.Name) syntax.Expr { + obj := c.info.Uses[id] + if obj == nil { + obj = c.info.Defs[id] + } + if obj == nil { + return nil + } + + if isBaseSimdTypeObj(obj) { + // if it is a name, that means that this is in the simd package, + // and the name must be replaced with a selector referencing + // the architecture-dependent packages. + name := id.Value + width := nameToElemBitWidth(name) + if width > 0 { + archsimdId := syntax.NewName(id.Pos(), archPkg) + if c.VecLen == 0 { + // special case for emulation + newSel := &syntax.SelectorExpr{ + X: archsimdId, + Sel: id, // name is unchanged for emulation + } + newSel.SetPos(id.Pos()) + return newSel + } + + count := c.VecLen / width + base := name[:len(name)-1] + newName := fmt.Sprintf("%sx%d", base, count) + newSelId := syntax.NewName(id.Pos(), newName) + newSel := &syntax.SelectorExpr{ + X: archsimdId, + Sel: newSelId, + } + newSel.SetPos(id.Pos()) + return newSel + } + } + + if c.analyzer.isDependentObj[obj] { + newId := syntax.NewName(id.Pos(), id.Value+c.suffix) + // Object link will be handled manually in deepcopier Use/Def mapper + if base.Debug.Simd > 0 { + base.Warn("%s: rewriting name %s to %s", id.Pos().String(), id.Value, newId.Value) + } + return newId + } + return nil +} + +// OnSelector is looking for simd.Something, to be rewritten into +// appropriately. Note that this will not work properly within the simd +// package because there is no "simd." selection there. +func (c *DeepCopier) OnSelector(se *syntax.SelectorExpr) syntax.Expr { + if x, ok := se.X.(*syntax.Name); ok { + obj := c.info.Uses[x] + if pkgName, isPkg := obj.(*types2.PkgName); isPkg && pkgName.Imported().Path() == simdPkg { + // This first little bit detects name = Load-Type-Width-s-{,Part} + // and converts the name to Type-Width-s (for nameToWidth), sets isLoad, + // and initializes the suffix appropriately. + prefix := "" + nameSuffix := "" + name := se.Sel.Value + end := len(name) + if strings.HasPrefix(name, "Load") { + prefix = "Load" + if strings.HasSuffix(name, "Part") { + end = strings.Index(name, "Part") + nameSuffix = "Part" + } + name = name[len("Load"):end] + } + if strings.HasPrefix(name, "Broadcast") { + prefix = "Broadcast" + name = name[len("Broadcast"):end] + } + + width := nameToElemBitWidth(name) + if width > 0 { + archsimdId := syntax.NewName(se.Pos(), archPkg) + if c.VecLen == 0 { + // emulated instead, name is unchanged + newSel := &syntax.SelectorExpr{ + X: archsimdId, + Sel: se.Sel, + } + newSel.SetPos(se.Pos()) + return newSel + } + + count := c.VecLen / width + base := name[:len(name)-1] + newName := fmt.Sprintf("%sx%d", base, count) + newName = prefix + newName + nameSuffix + + newSelId := syntax.NewName(se.Sel.Pos(), newName) + + newSel := &syntax.SelectorExpr{ + X: archsimdId, + Sel: newSelId, + } + newSel.SetPos(se.Pos()) + return newSel + } + } + } + return nil +} + +func (c *DeepCopier) CopyDecl(d syntax.Decl) syntax.Decl { + if d == nil { + return nil + } + switch d := d.(type) { + case *syntax.FuncDecl: + return c.CopyFuncDecl(d) + case *syntax.VarDecl: + return c.CopyVarDecl(d) + case *syntax.TypeDecl: + return c.CopyTypeDecl(d) + case *syntax.ConstDecl: + return c.CopyConstDecl(d) + case *syntax.ImportDecl: + newD := &syntax.ImportDecl{ + Group: d.Group, + Pragma: d.Pragma, + LocalPkgName: c.CopyName(d.LocalPkgName, false), + Path: c.CopyExpr(d.Path).(*syntax.BasicLit), + } + newD.SetPos(d.Pos()) + return newD + default: + return d + } +} + +func (c *DeepCopier) CopyVarDecl(d *syntax.VarDecl) *syntax.VarDecl { + newD := &syntax.VarDecl{ + Group: d.Group, + Pragma: d.Pragma, + Type: c.CopyExpr(d.Type), + Values: c.CopyExpr(d.Values), + } + newD.SetPos(d.Pos()) + for _, n := range d.NameList { + newN := c.CopyName(n, true) + newD.NameList = append(newD.NameList, newN) + } + return newD +} + +func (c *DeepCopier) CopyTypeDecl(d *syntax.TypeDecl) *syntax.TypeDecl { + newD := &syntax.TypeDecl{ + Group: d.Group, + Pragma: d.Pragma, + Name: c.CopyName(d.Name, true), + TParamList: c.CopyFieldList(d.TParamList), + Alias: d.Alias, + Type: c.CopyExpr(d.Type), + } + newD.SetPos(d.Pos()) + return newD +} + +func (c *DeepCopier) CopyConstDecl(d *syntax.ConstDecl) *syntax.ConstDecl { + newD := &syntax.ConstDecl{ + Group: d.Group, + Pragma: d.Pragma, + Type: c.CopyExpr(d.Type), + Values: c.CopyExpr(d.Values), + } + newD.SetPos(d.Pos()) + for _, n := range d.NameList { + newD.NameList = append(newD.NameList, c.CopyName(n, true)) + } + return newD +} + +func (c *DeepCopier) CopyFuncDecl(d *syntax.FuncDecl) *syntax.FuncDecl { + newD := &syntax.FuncDecl{ + Pragma: d.Pragma, + Recv: c.CopyField(d.Recv), + Name: c.CopyName(d.Name, true), + TParamList: c.CopyFieldList(d.TParamList), + Type: c.CopyExpr(d.Type).(*syntax.FuncType), + } + newD.SetPos(d.Pos()) + + // Create and register new types2.Func + if oldFuncObj, ok := c.info.Defs[d.Name].(*types2.Func); ok { + newFuncObj := types2.NewFunc(newD.Name.Pos(), c.pkg, newD.Name.Value, oldFuncObj.Type().(*types2.Signature)) + c.info.Defs[newD.Name] = newFuncObj + } + + newD.Body = c.CopyBlockStmt(d.Body) + return newD +} + +func (c *DeepCopier) CopyName(id *syntax.Name, isDef bool) *syntax.Name { + if id == nil { + return nil + } + if match := c.OnName(id); match != nil { + match.SetPos(id.Pos()) + if isDef { + c.registerDef(match, id) + } else { + c.mapUse(match, id) + } + return match + } + newId := syntax.NewName(id.Pos(), id.Value) + if isDef { + c.registerDef(newId, id) + } else { + c.mapUse(newId, id) + } + return newId +} + +func (c *DeepCopier) CopyNameExpr(id *syntax.Name) syntax.Expr { + if !c.analyzer.inSimd { + return c.CopyName(id, false) + } + if id == nil { + return nil + } + + if match := c.OnNameExpr(id); match != nil { + match.SetPos(id.Pos()) + if n, ok := match.(*syntax.Name); ok { + c.mapUse(n, id) + } + return match + } + + newId := syntax.NewName(id.Pos(), id.Value) + c.mapUse(newId, id) + return newId +} + +func (c *DeepCopier) CopyExpr(e syntax.Expr) syntax.Expr { + if e == nil { + return nil + } + var newE syntax.Expr + switch e := e.(type) { + case *syntax.Name: + return c.CopyNameExpr(e) + case *syntax.BasicLit: + newLit := &syntax.BasicLit{Value: e.Value, Kind: e.Kind, Bad: e.Bad} + newE = newLit + case *syntax.CompositeLit: + newLit := &syntax.CompositeLit{ + Type: c.CopyExpr(e.Type), + NKeys: e.NKeys, + Rbrace: e.Rbrace, + } + for _, el := range e.ElemList { + newLit.ElemList = append(newLit.ElemList, c.CopyExpr(el)) + } + newE = newLit + case *syntax.KeyValueExpr: + newE = &syntax.KeyValueExpr{Key: c.CopyExpr(e.Key), Value: c.CopyExpr(e.Value)} + case *syntax.FuncLit: + newE = &syntax.FuncLit{Type: c.CopyExpr(e.Type).(*syntax.FuncType), Body: c.CopyBlockStmt(e.Body)} + case *syntax.ParenExpr: + newE = &syntax.ParenExpr{X: c.CopyExpr(e.X)} + case *syntax.SelectorExpr: + if sub := c.OnSelector(e); sub != nil { + sub.SetPos(e.Pos()) + if sel := c.info.Selections[e]; sel != nil { + c.info.Selections[sub.(*syntax.SelectorExpr)] = sel + } + return sub + } + newSel := &syntax.SelectorExpr{X: c.CopyExpr(e.X), Sel: c.CopyName(e.Sel, false)} + if sel := c.info.Selections[e]; sel != nil { + c.info.Selections[newSel] = sel + } + newE = newSel + case *syntax.IndexExpr: + newE = &syntax.IndexExpr{X: c.CopyExpr(e.X), Index: c.CopyExpr(e.Index)} + case *syntax.SliceExpr: + newE = &syntax.SliceExpr{ + X: c.CopyExpr(e.X), + Index: [3]syntax.Expr{c.CopyExpr(e.Index[0]), c.CopyExpr(e.Index[1]), c.CopyExpr(e.Index[2])}, + Full: e.Full, + } + case *syntax.AssertExpr: + newE = &syntax.AssertExpr{X: c.CopyExpr(e.X), Type: c.CopyExpr(e.Type)} + case *syntax.TypeSwitchGuard: + newE = &syntax.TypeSwitchGuard{Lhs: c.CopyName(e.Lhs, true), X: c.CopyExpr(e.X)} + case *syntax.Operation: + newE = &syntax.Operation{Op: e.Op, X: c.CopyExpr(e.X), Y: c.CopyExpr(e.Y)} + case *syntax.CallExpr: + newCall := &syntax.CallExpr{ + Fun: c.CopyExpr(e.Fun), + HasDots: e.HasDots, + } + for _, a := range e.ArgList { + newCall.ArgList = append(newCall.ArgList, c.CopyExpr(a)) + } + newE = newCall + case *syntax.ListExpr: + newList := &syntax.ListExpr{} + for _, el := range e.ElemList { + newList.ElemList = append(newList.ElemList, c.CopyExpr(el)) + } + newE = newList + case *syntax.ArrayType: + newE = &syntax.ArrayType{Len: c.CopyExpr(e.Len), Elem: c.CopyExpr(e.Elem)} + case *syntax.SliceType: + newE = &syntax.SliceType{Elem: c.CopyExpr(e.Elem)} + case *syntax.DotsType: + newE = &syntax.DotsType{Elem: c.CopyExpr(e.Elem)} + case *syntax.StructType: + newE = &syntax.StructType{ + FieldList: c.CopyFieldList(e.FieldList), + TagList: e.TagList, // Shallow copy for tags is fine usually + } + case *syntax.InterfaceType: + newE = &syntax.InterfaceType{MethodList: c.CopyFieldList(e.MethodList)} + case *syntax.FuncType: + newE = &syntax.FuncType{ + ParamList: c.CopyFieldList(e.ParamList), + ResultList: c.CopyFieldList(e.ResultList), + } + case *syntax.MapType: + newE = &syntax.MapType{Key: c.CopyExpr(e.Key), Value: c.CopyExpr(e.Value)} + case *syntax.ChanType: + newE = &syntax.ChanType{Dir: e.Dir, Elem: c.CopyExpr(e.Elem)} + case *syntax.BadExpr: + newE = &syntax.BadExpr{} + default: + newE = e + } + newE.SetPos(e.Pos()) + return newE +} + +func (c *DeepCopier) CopyStmt(s syntax.Stmt) syntax.Stmt { + if s == nil { + return nil + } + var newS syntax.Stmt + switch s := s.(type) { + case *syntax.DeclStmt: + newDeclList := make([]syntax.Decl, len(s.DeclList)) + for i, v := range s.DeclList { + newDeclList[i] = c.CopyDecl(v) + } + newS = &syntax.DeclStmt{DeclList: newDeclList} + case *syntax.ExprStmt: + newS = &syntax.ExprStmt{X: c.CopyExpr(s.X)} + case *syntax.SendStmt: + newS = &syntax.SendStmt{Chan: c.CopyExpr(s.Chan), Value: c.CopyExpr(s.Value)} + case *syntax.AssignStmt: + newS = &syntax.AssignStmt{Op: s.Op, Lhs: c.CopyExpr(s.Lhs), Rhs: c.CopyExpr(s.Rhs)} + case *syntax.ReturnStmt: + newS = &syntax.ReturnStmt{Results: c.CopyExpr(s.Results)} + case *syntax.BranchStmt: + // TODO this is broken + newS = &syntax.BranchStmt{Tok: s.Tok, Label: c.CopyName(s.Label, false), Target: nil} // Targets need fix-up + case *syntax.CallStmt: + newS = &syntax.CallStmt{Tok: s.Tok, Call: c.CopyExpr(s.Call), DeferAt: c.CopyExpr(s.DeferAt)} + case *syntax.IfStmt: + newS = &syntax.IfStmt{ + Init: c.CopySimpleStmt(s.Init), + Cond: c.CopyExpr(s.Cond), + Then: c.CopyBlockStmt(s.Then), + Else: c.CopyStmt(s.Else), + } + case *syntax.ForStmt: + newS = &syntax.ForStmt{ + Init: c.CopySimpleStmt(s.Init), + Cond: c.CopyExpr(s.Cond), + Post: c.CopySimpleStmt(s.Post), + Body: c.CopyBlockStmt(s.Body), + } + case *syntax.SwitchStmt: + newS = &syntax.SwitchStmt{ + Init: c.CopySimpleStmt(s.Init), + Tag: c.CopyExpr(s.Tag), + Body: c.CopyCaseClauses(s.Body), + Rbrace: s.Rbrace, + } + case *syntax.SelectStmt: + newS = &syntax.SelectStmt{ + Body: c.CopyCommClauses(s.Body), + Rbrace: s.Rbrace, + } + case *syntax.EmptyStmt: + newS = &syntax.EmptyStmt{} + case *syntax.LabeledStmt: + newS = &syntax.LabeledStmt{Label: c.CopyName(s.Label, true), Stmt: c.CopyStmt(s.Stmt)} // Labels are defs + case *syntax.BlockStmt: + return c.CopyBlockStmt(s) + default: + newS = s + } + newS.SetPos(s.Pos()) + return newS +} + +func (c *DeepCopier) CopySimpleStmt(s syntax.SimpleStmt) syntax.SimpleStmt { + if s == nil { + return nil + } + switch s := s.(type) { + case *syntax.RangeClause: + newS := &syntax.RangeClause{ + Def: s.Def, + X: c.CopyExpr(s.X), + } + // In a range clause, Lhs may contain definitions if Def is true. + if list, ok := s.Lhs.(*syntax.ListExpr); ok && s.Def { + newList := &syntax.ListExpr{} + for _, el := range list.ElemList { + if id, ok := el.(*syntax.Name); ok { + newList.ElemList = append(newList.ElemList, c.CopyName(id, true)) + } else { + newList.ElemList = append(newList.ElemList, c.CopyExpr(el)) + } + } + newS.Lhs = newList + } else if id, ok := s.Lhs.(*syntax.Name); ok && s.Def { + newS.Lhs = c.CopyName(id, true) + } else { + newS.Lhs = c.CopyExpr(s.Lhs) + } + newS.Lhs.SetPos(s.Lhs.Pos()) + newS.SetPos(s.Pos()) + return newS + case *syntax.AssignStmt: + // Check for := + isDef := false + if list, ok := s.Lhs.(*syntax.ListExpr); ok { + for _, el := range list.ElemList { + if id, ok := el.(*syntax.Name); ok && c.info.Defs[id] != nil { + isDef = true + break + } + } + } else if id, ok := s.Lhs.(*syntax.Name); ok && c.info.Defs[id] != nil { + isDef = true + } + + newS := &syntax.AssignStmt{Op: s.Op, Rhs: c.CopyExpr(s.Rhs)} + if isDef { + if list, ok := s.Lhs.(*syntax.ListExpr); ok { + newList := &syntax.ListExpr{} + for _, el := range list.ElemList { + if id, ok := el.(*syntax.Name); ok && c.info.Defs[id] != nil { + newList.ElemList = append(newList.ElemList, c.CopyName(id, true)) + } else { + newList.ElemList = append(newList.ElemList, c.CopyExpr(el)) + } + } + newS.Lhs = newList + } else if id, ok := s.Lhs.(*syntax.Name); ok { + newS.Lhs = c.CopyName(id, true) + } + } else { + newS.Lhs = c.CopyExpr(s.Lhs) + } + newS.Lhs.SetPos(s.Lhs.Pos()) + newS.SetPos(s.Pos()) + return newS + default: + return c.CopyStmt(s).(syntax.SimpleStmt) + } +} + +func (c *DeepCopier) CopyCaseClauses(list []*syntax.CaseClause) []*syntax.CaseClause { + var newList []*syntax.CaseClause + for _, cc := range list { + newC := &syntax.CaseClause{Cases: c.CopyExpr(cc.Cases), Colon: cc.Colon} + for _, b := range cc.Body { + newC.Body = append(newC.Body, c.CopyStmt(b)) + } + newC.SetPos(cc.Pos()) + newList = append(newList, newC) + } + return newList +} + +func (c *DeepCopier) CopyCommClauses(list []*syntax.CommClause) []*syntax.CommClause { + var newList []*syntax.CommClause + for _, cc := range list { + newC := &syntax.CommClause{Comm: c.CopySimpleStmt(cc.Comm), Colon: cc.Colon} + for _, b := range cc.Body { + newC.Body = append(newC.Body, c.CopyStmt(b)) + } + newC.SetPos(cc.Pos()) + newList = append(newList, newC) + } + return newList +} + +func (c *DeepCopier) CopyBlockStmt(b *syntax.BlockStmt) *syntax.BlockStmt { + if b == nil { + return nil + } + newB := &syntax.BlockStmt{Rbrace: b.Rbrace} + for _, s := range b.List { + newB.List = append(newB.List, c.CopyStmt(s)) + } + newB.SetPos(b.Pos()) + return newB +} + +func (c *DeepCopier) CopyFieldList(f []*syntax.Field) []*syntax.Field { + if f == nil { + return nil + } + var newF []*syntax.Field + for _, field := range f { + newF = append(newF, c.CopyField(field)) + } + return newF +} + +func (c *DeepCopier) CopyField(f *syntax.Field) *syntax.Field { + if f == nil { + return nil + } + newF := &syntax.Field{ + Name: c.CopyName(f.Name, true), + Type: c.CopyExpr(f.Type), + } + newF.SetPos(f.Pos()) + return newF +} diff --git a/src/cmd/compile/internal/midway/midway.go b/src/cmd/compile/internal/midway/midway.go new file mode 100644 index 00000000000000..9adeec8024530c --- /dev/null +++ b/src/cmd/compile/internal/midway/midway.go @@ -0,0 +1,38 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package midway + +import ( + "internal/buildcfg" +) + +func rewriteSizes() []int { + switch buildcfg.GOARCH { + case "wasm": + return []int{0, 128} + case "amd64": + return []int{0, 128, 256, 512} + case "arm64": + return []int{0, 128} // this will change for SVE and cannot just be a size-based choice. + } + return nil +} + +const simdPkg = "simd" +const archFullPkg = "simd/internal/bridge" +const archPkg = "bridge" +const vectorSizeFn = "VectorBitSize" +const emulatedFn = "Emulated" + +func isSimdTypeName(s string) bool { + switch s { + case "Int8s", "Int16s", "Int32s", "Int64s", + "Uint8s", "Uint16s", "Uint32s", "Uint64s", + "Mask8s", "Mask16s", "Mask32s", "Mask64s", + "Float32s", "Float64s": + return true + } + return false +} diff --git a/src/cmd/compile/internal/midway/rewrite.go b/src/cmd/compile/internal/midway/rewrite.go new file mode 100644 index 00000000000000..e80930bcd79346 --- /dev/null +++ b/src/cmd/compile/internal/midway/rewrite.go @@ -0,0 +1,545 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package midway + +import ( + "cmd/compile/internal/base" + "cmd/compile/internal/syntax" + "cmd/compile/internal/types2" + "fmt" + "internal/buildcfg" + "strings" +) + +// "Midway" rewriting +// +// Go attempts to provide a package similar to the the "Highway" library +// for C++ (https://google.github.io/highway). The library package is "simd" +// and defines vector types with unspecified widths that are bound to particular +// machine dependent types as late as program execution. This is accomplished +// by rewriting code that depends on these types into code that references +// architecture-specific types, perhaps more than once, and if necessary +// dynamically choosing which version to execute based on hardware attributes. +// +// The rewriting takes place early in the compiler, after type checking but +// before conversion to "unified" IR. To ensure that types are correctly set +// on the modified version of the code, type checking information is reset and +// the type checking phase is re-run. The places some limits on the shape of +// the rewrites, but it also ensures that the rewritten code is well-formed. +// +// Rewritten code does not reference "archsimd" types directly, but instead +// references types in a "bridge" package that filters the available methods +// and adds a few more. The package used relies on a builder/compiler hack; +// the compiler's type checker enforces export naming conventions, but the +// build system limits visibility to unrelated "internal" packages and can be +// modified to allow access in special cases (like this one). This allows the +// rewritten code to reference types, functions, and methods that are not +// accessible otherwise. +// +// The rewrite works in phases. The first is "analysis", to discover functions, +// types, methods, and variables that depend on "simd" types. "Depend on" means +// any mention of a simd type, and for types, also includes types that have a +// simd-dependent method. Dependent functions are split into two categories; +// those whose dependence includes their signature, and those that do not. +// The second category forms the boundary between code that depends on simd and +// code that does not. Notice that there cannot be a boundary method, because +// (by design) the receiver type is simd-dependent and thus a dependent method +// also has a dependent type in its signature. +// +// The second phase rewrites such "boundary" functions into a "dispatch" version +// and (later, third phase) "specialized" versions. The dispatch function +// will choose which specialized version to call based on which simd implementation +// has been chosen, and forward parameters and results to/from that specialized version +// of the function. The dispatch version shares the same name as the original function. +// Note that this applies to functions only, and not methods. + +// The third phase specializes dependent functions (both kinds), methods, +// global variables, and types into size/emulation/feature-specific variants. +// Except for methods, this is done by adding a suffix beginning with "@" to +// the name. Because "@" cannot appear in legal Go identifiers this removes +// the risk of a naming overlap. Methods are specialized, but not renamed, +// because their receiver type is renamed instead. Not changing method names +// preserves interface satisfaction, for example in the case of generic interfaces. +// +// Non-boundary dependent function and methods are not rewritten into dispatch +// functions/methods, but remain in the generated code because they must be +// present in the export data so that other packages that import them will still +// compile before rewriting. Their bodies are replaced with panic(...) to allow +// compilation while preventing even worse chaos in the event of a bug either in +// the compiler or through ambitious use of reflection or assembly language. +// + +/* Example rewrites + +// Type alias, global variable, and init function: + +// before: +type MyInt8s = simd.Int8s +func Generic[T haslen](x int) int { + var v T + return x + v.Len() +} +var VL int +func init() { + VL = Generic[MyInt8s](1) +} +// dispatch: +func init() { + switch simd.VectorBitSize() { + case + 128: + init@simd128() + return + case 256: + init@simd256() + return + case 512: + init@simd512() + return + default: + panic("unsupported vector size") + } +} +// specialized (128) +type MyInt8s@simd128 = archsimd.Int8x16 +func init@simd128() { + VL = Generic[MyInt8s@simd128](1) +} + + +// structure containing simd fields, and with simd methods + +// before +// A struct dependent on SIMD +type VectorC struct { + Field simd.Float32s +} +func (v *VectorC) MethodOfSimd() bool { + return false +} +func (v VectorC) Data() simd.Float32s { + return v.Field +} +func (v VectorC) Foo(x VectorC) VectorC { + return VectorC{Field: v.Field.Add(x.Field)} +} + +// dispatch +// technically there is none, but functions with panicking bodies +// remain because code must pass type checking before rewriting. +type VectorC struct { + Field simd.Float32s +} +func (v *VectorC) MethodOfSimd() bool { + panic(...) +} +func (v VectorC) Data() simd.Float32s { + panic(...) +} +func (v VectorC) Foo(x VectorC) VectorC { + panic(...) +} + +// specialized (128) + +// A struct dependent on SIMD +type VectorC@simd128 struct { + Field bridge.Float32x4 +} +func (v *VectorC@simd128) MethodOfSimd() bool { + return false +} +func (v VectorC@simd128) Data() bridge.Float32x4 { + return v.Field +} +func (v VectorC@simd128) Foo(x VectorC@simd128) VectorC@simd128 { + return VectorC@simd128{Field: v.Field.Add(x.Field)} +} + +*/ + +type Rewriter struct { + pkg *types2.Package + analyzer *Analyzer + info *types2.Info + sizes []int +} + +func NewRewriter(pkg *types2.Package, info *types2.Info, analyzer *Analyzer, sizes []int) *Rewriter { + return &Rewriter{ + pkg: pkg, + info: info, + analyzer: analyzer, + sizes: sizes, + } +} + +func (r *Rewriter) Rewrite(files []*syntax.File) { + + // First duplicate and specialize all dependent functions and variables. + for _, fileAST := range files { + + var newDecls []syntax.Decl + for _, k := range r.sizes { + newDecls = r.generateForSize(fileAST, k, newDecls) + } + + // Then replace original functions with dispatchers. + // This also edits the DeclList of fileAST. + r.generateDispatchers(fileAST) + + fileAST.DeclList = append(fileAST.DeclList, newDecls...) + } +} + +func (r *Rewriter) generateDispatchers(fileAST *syntax.File) { + var newDecls []syntax.Decl + + change := false + + for _, decl := range fileAST.DeclList { + switch d := decl.(type) { + case *syntax.FuncDecl: + if d.Name == nil { + newDecls = append(newDecls, d) + continue + } + obj := r.info.Defs[d.Name] + if !r.analyzer.isDependentObj[obj] || r.analyzer.inSimd { + newDecls = append(newDecls, d) + continue + } + + sig, ok := obj.Type().(*types2.Signature) + if !ok { + newDecls = append(newDecls, d) + continue + } + + change = true + if r.analyzer.HasDependentSignature(sig) { + if base.Debug.Simd > 0 { + base.Warn("%s: removing body of dependent-sig original function %v", d.Pos().String(), d.Name.Value) + } + d.Body = r.blockOf(d.Pos(), r.panicStmt(d.Pos(), + "unexpected call of original function rewritten to specialized SIMD")) + newDecls = append(newDecls, d) + continue + } + + // Clean signature -> Replace body with dispatcher + d.Body = r.createDispatcherBody(d, sig) + newDecls = append(newDecls, d) + + case *syntax.VarDecl: + // Keep var decls even if rewritten, so that pre-rewrite code parses correctly. + // TODO figure out how to deal with side-effects in initializers. + newDecls = append(newDecls, d) + + case *syntax.TypeDecl: + // Keep all types; we need the untranslated copy if a method referencing it + // needs to typecheck pre-translation. + newDecls = append(newDecls, d) + default: + newDecls = append(newDecls, decl) + } + } + + if !change { + return + } + + fileAST.DeclList = newDecls + + if !r.analyzer.inSimd { + // Inject an import to the bridge package (if not exists) + hasArchSimd := false + var simdImport *syntax.ImportDecl + p := fileAST.Pos() + for _, decl := range fileAST.DeclList { + if imp, ok := decl.(*syntax.ImportDecl); ok { + if imp.Path.Value == `"`+archFullPkg+`"` { + hasArchSimd = true + if simdImport == nil { + p = imp.Pos() + } + } + if imp.Path.Value == `"`+simdPkg+`"` { + simdImport = imp + p = imp.Pos() + } + } + } + + if !hasArchSimd { + r.injectImport(fileAST, archFullPkg, p) + } + + // Ensure at least one use of "simd" + // var _ = simd.VectorBitLen() + fun := &syntax.SelectorExpr{ + X: syntax.NewName(p, simdPkg), // Assume this is resolvable + Sel: syntax.NewName(p, vectorSizeFn), + } + fun.SetPos(p) + call := &syntax.CallExpr{Fun: fun} + call.SetPos(p) + + name := syntax.NewName(p, "_") + + varDecl := &syntax.VarDecl{NameList: []*syntax.Name{name}, Values: call} + varDecl.SetPos(p) + fileAST.DeclList = append(fileAST.DeclList, varDecl) + } +} + +func (r *Rewriter) injectImport(fileAST *syntax.File, toImport string, simdImportPos syntax.Pos) { + importDecl := &syntax.ImportDecl{ + Path: &syntax.BasicLit{Value: `"` + toImport + `"`, Kind: syntax.StringLit}, + } + importDecl.Path.SetPos(simdImportPos) + importDecl.SetPos(simdImportPos) + fileAST.DeclList = append([]syntax.Decl{importDecl}, fileAST.DeclList...) +} + +func (r *Rewriter) createDispatcherBody(d *syntax.FuncDecl, sig *types2.Signature) *syntax.BlockStmt { + + // Build call arguments from the function parameters + args := func() []syntax.Expr { + var args []syntax.Expr + if d.Type.ParamList != nil { + for _, field := range d.Type.ParamList { + if field.Name != nil { + paramName := syntax.NewName(field.Pos(), field.Name.Value) + args = append(args, paramName) + } + } + } + return args + } + + // Slap a pos on an expression + pe := func(e syntax.Expr) syntax.Expr { + e.SetPos(d.Pos()) + return e + } + // Slap a pos on a statement + ps := func(e syntax.Stmt) syntax.Stmt { + e.SetPos(d.Pos()) + return e + } + + // switch ast node. + // the goal is something like (for now, till there are finer-grained choices) + // switch simd.VectorSize() { + // case 128: if simd.Emulated() { call the specialize-for-emulation-code(args) } + // else { call the specialize-for-128-code(args) } + // case 256: call the specialize-for-256-code(args) + // etc + // } + // + // the cases above deal with the usual `return call(...)` vs `call(...); return` + switchStmt := &syntax.SwitchStmt{ + Tag: pe(&syntax.CallExpr{ + Fun: pe(&syntax.SelectorExpr{ + X: syntax.NewName(d.Pos(), simdPkg), // Assume this is resolvable + Sel: syntax.NewName(d.Pos(), vectorSizeFn), + }), + }), + Body: []*syntax.CaseClause{}, + } + + var emulation syntax.Stmt + + for _, k := range r.sizes { + fnName := fmt.Sprintf("%s@simd%d", d.Name.Value, k) + fnIdent := syntax.NewName(d.Pos(), fnName) + + callExpr := pe(&syntax.CallExpr{ + Fun: pe(fnIdent), + ArgList: args(), + }) + + // callReturnStmt is either `return call(...)` or `call(...); return` + var callReturnStmt syntax.Stmt + if d.Type.ResultList != nil && len(d.Type.ResultList) > 0 { + callReturnStmt = &syntax.ReturnStmt{Results: callExpr} + } else { + callReturnStmt = &syntax.BlockStmt{ + List: []syntax.Stmt{ + ps(&syntax.ExprStmt{X: callExpr}), + ps(&syntax.ReturnStmt{}), + }, + Rbrace: d.Pos(), + } + } + callReturnStmt.SetPos(d.Pos()) + + if k == 0 { + // emulation == `if simd.Emulated() { callReturnStmt }` + // save it for the first part of the 128 case. + cond := pe(&syntax.CallExpr{ + Fun: pe(&syntax.SelectorExpr{ + X: syntax.NewName(d.Pos(), simdPkg), // Assume this is resolvable + Sel: syntax.NewName(d.Pos(), emulatedFn), + })}) + + blockStmt, ok := callReturnStmt.(*syntax.BlockStmt) + if !ok { + blockStmt = &syntax.BlockStmt{ + List: []syntax.Stmt{callReturnStmt}, + Rbrace: d.Pos(), + } + blockStmt.SetPos(d.Pos()) + } + + emulation = ps(&syntax.IfStmt{ + Cond: cond, + Then: blockStmt, + }) + continue + } + + var caseBody []syntax.Stmt + // assume that 128 is a case; when we do scalable simd, this may change. + // For now, if there is emulation, it is 128-bit (only). + if emulation != nil && k == 128 { + caseBody = append(caseBody, emulation) + emulation = nil + } + + caseClause := &syntax.CaseClause{ + Cases: pe(&syntax.BasicLit{Kind: syntax.IntLit, Value: fmt.Sprintf("%d", k)}), + Body: append(caseBody, callReturnStmt), + } + caseClause.SetPos(d.Pos()) + switchStmt.Body = append(switchStmt.Body, caseClause) + } + + panicStmt := r.panicStmt(d.Pos(), "unsupported vector size in simd-rewritten code") + return r.blockOf(d.Pos(), switchStmt, panicStmt) +} + +func (r *Rewriter) blockOf(p syntax.Pos, stmts ...syntax.Stmt) *syntax.BlockStmt { + for _, s := range stmts { + s.SetPos(p) + } + blockStmt := &syntax.BlockStmt{List: stmts} + blockStmt.SetPos(p) + return blockStmt +} + +func (r *Rewriter) panicStmt(p syntax.Pos, unquotedMessage string) *syntax.ExprStmt { + pe := func(e syntax.Expr) syntax.Expr { + e.SetPos(p) + return e + } + fnName := "panic" + fnIdent := pe(syntax.NewName(p, fnName)) + callExpr := pe(&syntax.CallExpr{ + Fun: fnIdent, + ArgList: []syntax.Expr{pe(&syntax.BasicLit{Value: `"` + unquotedMessage + `"`, Kind: syntax.StringLit})}, + }) + panicStmt := &syntax.ExprStmt{X: callExpr} + panicStmt.SetPos(p) + return panicStmt +} + +func (r *Rewriter) generateForSize(fileAST *syntax.File, k int, newDecls []syntax.Decl) []syntax.Decl { + copier := NewDeepCopier(r.pkg, r.info, k, r.analyzer, fmt.Sprintf("@simd%d", k)) + for _, decl := range fileAST.DeclList { + if r.shouldIncludeDecl(decl) { + newDecl := copier.CopyDecl(decl) + newDecls = append(newDecls, newDecl) + } + } + return newDecls +} + +func nameToElemBitWidth(name string) int { + var width int + switch name { + case "Int8s", "Uint8s", "Mask8s": + width = 8 + case "Int16s", "Uint16s", "Mask16s": + width = 16 + case "Int32s", "Uint32s", "Float32s", "Mask32s": + width = 32 + case "Int64s", "Uint64s", "Float64s", "Mask64s": + width = 64 + } + return width +} + +func (r *Rewriter) shouldIncludeDecl(decl syntax.Decl) bool { + // Files (and declarations) in the simd package are excluded + // from processing, except for those that whose name begins + // with "tofrom_". + if r.analyzer.inSimd { + theFile := decl.Pos().Base().Filename() + + lastSlash := strings.LastIndex(theFile, simdPkg+"/") + lastBackslash := strings.LastIndex(theFile, simdPkg+"\\") + + // Windows paths can be chaos, all we care, is whether the very last part + // of the path is any-path-separator + "tofrom_" + anything-else, given that + // we already know that we are in the simd package. + maxSlash := max(lastSlash, lastBackslash) + if maxSlash == -1 { + return false + } + if !strings.HasPrefix(theFile[maxSlash:], simdPkg+"/tofrom_") && + !strings.HasPrefix(theFile[maxSlash:], simdPkg+"\\tofrom_") { + return false + } + } + + switch d := decl.(type) { + case *syntax.FuncDecl: + if d.Name != nil { + return r.analyzer.isDependentObj[r.info.Defs[d.Name]] + } + case *syntax.TypeDecl: + return r.analyzer.isDependentObj[r.info.Defs[d.Name]] + case *syntax.VarDecl: + for _, name := range d.NameList { + if r.analyzer.isDependentObj[r.info.Defs[name]] { + return true + } + } + } + return false +} + +// Generate an API matching the standalone compilation call +func RewriteWrapper(pkg *types2.Package, info *types2.Info, files []*syntax.File) bool { + if !buildcfg.Experiment.SIMD { + return false + } + + switch buildcfg.GOARCH { + case "wasm", "amd64", "arm64": + default: + return false + } + + sizes := rewriteSizes() + if len(sizes) == 0 { + return false + } + analyzer := NewAnalyzer(pkg, info) + if !analyzer.Analyze(files) { + return false + } + + CheckPositions(files, "before midway") + + rewriter := NewRewriter(pkg, info, analyzer, sizes) + rewriter.Rewrite(files) + + CheckPositions(files, "after midway") + + return true +} diff --git a/src/cmd/compile/internal/mips/ssa.go b/src/cmd/compile/internal/mips/ssa.go index c338fdc6b3e46b..d89d2afcaf3fad 100644 --- a/src/cmd/compile/internal/mips/ssa.go +++ b/src/cmd/compile/internal/mips/ssa.go @@ -197,7 +197,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpMIPSANDconst, ssa.OpMIPSORconst, ssa.OpMIPSXORconst, - ssa.OpMIPSNORconst, ssa.OpMIPSSLLconst, ssa.OpMIPSSRLconst, ssa.OpMIPSSRAconst, @@ -213,11 +212,25 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpMIPSMULTU, ssa.OpMIPSDIV, ssa.OpMIPSDIVU: - // result in hi,lo + // HI, LO results exist in low quality registers that can't + // be stored without using REGTMP. + // This used to cause corruptions since store might also need + // REGTMP to materialize the address. + // Instead we move the result into high quality registers. p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REG p.From.Reg = v.Args[1].Reg() p.Reg = v.Args[0].Reg() + p1 := s.Prog(mips.AMOVW) + p1.From.Type = obj.TYPE_REG + p1.From.Reg = mips.REG_HI + p1.To.Type = obj.TYPE_REG + p1.To.Reg = v.Reg0() + p2 := s.Prog(mips.AMOVW) + p2.From.Type = obj.TYPE_REG + p2.From.Reg = mips.REG_LO + p2.To.Type = obj.TYPE_REG + p2.To.Reg = v.Reg1() case ssa.OpMIPSMOVWconst: r := v.Reg() p := s.Prog(v.Op.Asm()) @@ -479,7 +492,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p6.To.SetTarget(p2) case ssa.OpMIPSCALLstatic, ssa.OpMIPSCALLclosure, ssa.OpMIPSCALLinter: s.Call(v) - case ssa.OpMIPSCALLtail: + case ssa.OpMIPSCALLtail, ssa.OpMIPSCALLtailinter: s.TailCall(v) case ssa.OpMIPSLoweredWB: p := s.Prog(obj.ACALL) diff --git a/src/cmd/compile/internal/mips64/ssa.go b/src/cmd/compile/internal/mips64/ssa.go index 6eae8fe0dd50eb..8b096f0014ac7c 100644 --- a/src/cmd/compile/internal/mips64/ssa.go +++ b/src/cmd/compile/internal/mips64/ssa.go @@ -191,7 +191,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpMIPS64ANDconst, ssa.OpMIPS64ORconst, ssa.OpMIPS64XORconst, - ssa.OpMIPS64NORconst, ssa.OpMIPS64SLLVconst, ssa.OpMIPS64SRLVconst, ssa.OpMIPS64SRAVconst, @@ -207,11 +206,25 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpMIPS64MULVU, ssa.OpMIPS64DIVV, ssa.OpMIPS64DIVVU: - // result in hi,lo + // HI, LO results exist in low quality registers that can't + // be stored without using REGTMP. + // This used to cause corruptions since store might also need + // REGTMP to materialize the address. + // Instead we move the result into high quality registers. p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REG p.From.Reg = v.Args[1].Reg() p.Reg = v.Args[0].Reg() + p1 := s.Prog(mips.AMOVV) + p1.From.Type = obj.TYPE_REG + p1.From.Reg = mips.REG_HI + p1.To.Type = obj.TYPE_REG + p1.To.Reg = v.Reg0() + p2 := s.Prog(mips.AMOVV) + p2.From.Type = obj.TYPE_REG + p2.From.Reg = mips.REG_LO + p2.To.Type = obj.TYPE_REG + p2.To.Reg = v.Reg1() case ssa.OpMIPS64MOVVconst: r := v.Reg() p := s.Prog(v.Op.Asm()) @@ -353,6 +366,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpMIPS64MOVVgpfp, ssa.OpMIPS64NEGF, ssa.OpMIPS64NEGD, + ssa.OpMIPS64ABSF, ssa.OpMIPS64ABSD, ssa.OpMIPS64SQRTF, ssa.OpMIPS64SQRTD: @@ -490,7 +504,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p6.To.SetTarget(p2) case ssa.OpMIPS64CALLstatic, ssa.OpMIPS64CALLclosure, ssa.OpMIPS64CALLinter: s.Call(v) - case ssa.OpMIPS64CALLtail: + case ssa.OpMIPS64CALLtail, ssa.OpMIPS64CALLtailinter: s.TailCall(v) case ssa.OpMIPS64LoweredWB: p := s.Prog(obj.ACALL) diff --git a/src/cmd/compile/internal/noder/README.md b/src/cmd/compile/internal/noder/README.md new file mode 100644 index 00000000000000..eb7a3697ef92da --- /dev/null +++ b/src/cmd/compile/internal/noder/README.md @@ -0,0 +1,83 @@ +# Making Unified Intermediate Representation (UIR) Changes + +For general information on export data, see [here](../../README.md). + +UIR is the serial form of the compiler's intermediate representation, used to +propagate bodies of generic and/or inlined functions from one compilation unit +to another. + +The Go compiler has a single, canonical UIR writer implementation in +`src/cmd/compile/internal/noder/writer.go`. When we update the byte stream that +the UIR writer writes, *all* of the UIR readers need to be reviewed and +potentially updated; a change might not be backward compatible for them. These +instructions outline the steps required to keep all UIR readers up-to-date. + +## The Writer + +The UIR version written by the compiler is controlled by +`src/cmd/compile/internal/noder/unified.go`. Do not change this yet. Instead: + +1. Add a version flag N+1 for `MyChange` in `internal/pkgbits/version.go`. +2. Update the UIR writer in `src/cmd/compile/internal/noder/writer.go` to guard + the writing of any fields added in N+1. Note: readers still on version N + *must* be oblivious to this change to avoid breaking the readers on + submission. + +## The Readers + +Besides the compiler itself, there are other readers in go, x/tools, and +externally. Those in x/tools and the general public exist because +`go list -export` produces export data files in this format and we support the +ability of applications to decode it. + +> Note that there is an upcoming plan to decouple the compiler's IR from x/tools +> by changing the format encoded by `go list -export`; this would make UIR a +> private detail of the compiler, free to break at any time. For now, these +> instructions must still be followed. + +We assume that external readers will update on their own. The necessary reader +updates in go and x/tools are detailed below. + +### go + +3. Update the compiler's own UIR reader in + `src/cmd/compile/internal/noder/reader.go` to guard the reading of any fields + added in N+1. +4. Repeat this change for the readers in `src/go/internal/gcimporter/ureader.go` + and `src/cmd/compile/internal/importer/ureader.go`. Note that these readers + only read data needed for type checking (in `src/go/types` and + `src/cmd/compile/internal/types2` respectively). For instance, they do not + read exported function bodies. Thus, it's possible that a change to UIR (such + as the encoding of function bodies) would require no change to these readers. + +### x/tools + +5. Add a version flag for `MyChange` in `internal/pkgbits/version.go`. Note: + x/tools has its own pkgbits implementation, which is intended to be an exact + copy of the [one in go](#the-writer). Any change made to one must be + reflected in the other. +6. Update the x/tools UIR reader in `internal/gcimporter/ureader.go` to guard + the reading of any fields added in N+1. Call this commit C. +7. In go, take the commit hash for C and update `src/cmd/go.mod` to use x/tools@C + per the [vendoring instructions](https://go.dev/wiki/MinorReleases#cherry-pick-cls-for-vendored-golangorgx-packages). + +## Finalizing + +> If this UIR change will be tested, check the [following section](#testing) and +> consider when it makes to finalize. + +Only after reviewing *all* of the readers, bump the UIR version written by the +writer to N+1 in `src/cmd/compile/internal/noder/unified.go`. Because the +readers have already been updated to handle version N+1, this change is +compatible. + +## Testing + +If making changes related to some new feature requiring extensive testing, it's +best to postpone bumping the UIR version until *all* of the tests are in. To +commit tests incrementally, develop them with a locally-incremented UIR version +and commit *skipped* tests; don't yet bump the remote UIR version. + +Once all of the required tests are in, bump the remote UIR version while turning +on all of the previously skipped tests. This minimizes churn on the UIR version +as testing uncovers any discrepancies. diff --git a/src/cmd/compile/internal/noder/dump.go b/src/cmd/compile/internal/noder/dump.go new file mode 100644 index 00000000000000..629848fff576c5 --- /dev/null +++ b/src/cmd/compile/internal/noder/dump.go @@ -0,0 +1,70 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package noder + +import ( + "sync" + + "cmd/compile/internal/base" + "cmd/compile/internal/ir" + "cmd/compile/internal/syntax" + "cmd/compile/internal/types2" +) + +// MatchASTDump returns true if the fn matches the value +// of the astdump debug flag. +func MatchASTDump(fn *syntax.FuncDecl) bool { + if len(base.Debug.AstDump) == 0 { + return false + } + if fn.Name == nil { + return false + } + return matchForDump(fn, base.Ctxt.Pkgpath) +} + +// matchForDump is marked noinline to ensure that the exported +// function MatchAstDump IS inlineable and is also small, because +// common case is AstDump is not set. +// +//go:noinline +func matchForDump(fn *syntax.FuncDecl, pkgPath string) bool { + return ir.MatchPkgFn(pkgPath, fn.Name.Value, base.Debug.AstDump) +} + +func escapedFileName(fn *syntax.FuncDecl, suffix string) string { + return ir.EscapedFileName(base.Ctxt.Pkgpath+"."+fn.Name.Value, suffix) +} + +var mu sync.Mutex +var htmlWriters = make(map[*syntax.FuncDecl]*HTMLWriter) +var orderedFuncs = []*syntax.FuncDecl{} + +// DumpNodeHTML dumps the node n to the HTML writer for fn. +func DumpNodeHTML(pkg *types2.Package, file *syntax.File, info *types2.Info, fn *syntax.FuncDecl, why string, n syntax.Node) { + mu.Lock() + defer mu.Unlock() + w, ok := htmlWriters[fn] + if !ok { + name := escapedFileName(fn, ".syntax.html") + w = NewHTMLWriter(pkg, file, info, name, fn, "") + htmlWriters[fn] = w + orderedFuncs = append(orderedFuncs, fn) + } + w.WritePhase(why, why) +} + +// CloseHTMLWriters closes the HTML writer for fn, if one exists. +func CloseHTMLWriters() { + mu.Lock() + defer mu.Unlock() + for _, fn := range orderedFuncs { + if w, ok := htmlWriters[fn]; ok { + w.Close("Writing html syntax output for %s to %s\n", w.pkgFuncName(), w.Path()) + delete(htmlWriters, fn) + } + } + orderedFuncs = nil +} diff --git a/src/cmd/compile/internal/noder/html.go b/src/cmd/compile/internal/noder/html.go new file mode 100644 index 00000000000000..d68dd56b52441c --- /dev/null +++ b/src/cmd/compile/internal/noder/html.go @@ -0,0 +1,420 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package noder + +import ( + "cmd/compile/internal/base" + "cmd/compile/internal/ir" + "cmd/compile/internal/syntax" + "cmd/compile/internal/types2" + "crypto/sha256" + "encoding/hex" + "fmt" + "html" + "os" + "path/filepath" + "reflect" + "strings" +) + +// An HTMLWriter dumps syntax nodes to multicolumn HTML, similar to what the +// ssa backend does for GOSSAFUNC. +type HTMLWriter struct { + ir.HTMLWriterBase + + Decl *syntax.FuncDecl + pkg *types2.Package + file *syntax.File + info *types2.Info +} + +func NewHTMLWriter(pkg *types2.Package, file *syntax.File, info *types2.Info, path string, decl *syntax.FuncDecl, cfgMask string) *HTMLWriter { + path = strings.ReplaceAll(path, "/", string(filepath.Separator)) + out, err := os.OpenFile(path, os.O_WRONLY|os.O_CREATE|os.O_TRUNC, 0644) + if err != nil { + panic(err) + } + reportPath := path + if !filepath.IsAbs(reportPath) { + pwd, err := os.Getwd() + if err != nil { + panic(err) + } + reportPath = filepath.Join(pwd, path) + } + h := HTMLWriter{ + pkg: pkg, + file: file, + info: info, + Decl: decl, + } + h.Init(out, reportPath, h.DeclHTML) + h.start() + return &h +} + +func (w *HTMLWriter) pkgFuncName() string { + p := w.pkg.Path() + if p == "" { + p = base.Ctxt.Pkgpath + } + return p + "." + w.Decl.Name.Value +} + +func (w *HTMLWriter) start() { + if w == nil { + return + } + escName := html.EscapeString(w.pkgFuncName()) + w.Print("") + w.Print("") + w.Printf(` + + +%s +%s +AST display for %s +`, escName, ir.CSS, ir.JS("checked", "rangefunc"), escName) + w.Print("") + w.Print("

    ") + w.Print(escName) + w.Print("

    ") + w.Print(` +help +
    + +

    +Click anywhere on a node (with "cell" cursor) to outline a node and all of its subtrees. +

    +

    +Click on a name (with "crosshair" cursor) to highlight every occurrence of a name. +(Note that all the name nodes are the same node, so those also all outline together). +

    +

    +Click on a file, line, or column (with "crosshair" cursor) to highlight positions +in that file, at that file:line, or at that file:line:column, respectively.
    Inlined +locations are not treated as a single location, but as a sequence of locations that +can be independently highlighted. +

    +

    +Click on a ` + ir.DownArrow + ` to collapse a subtree, or on a ` + ir.RightArrow + ` to expand a subtree. +

    +

    +Non-tree attributes, like scope and type lookups, are displayed in italics. Those may +also be clicked to highlight identity relationships within and between phases. +

    + +
    + + +`) + w.Print("") + w.Print("") +} + +func (w *HTMLWriter) DeclHTML(phase string) func() { + return func() { + w.Print("
    ") // use pre for formatting to preserve indentation
    +		w.dumpScopeHTML(w.pkg.Scope(), 1, false)
    +		w.dumpScopeHTML(w.info.Scopes[w.file], 1, false)
    +		w.dumpNodeHTML(w.Decl, 1, "")
    +		w.Print("
    ") + } +} + +func (h *HTMLWriter) dumpNodesHTML(list []syntax.Node, depth int) { + if len(list) == 0 { + h.Print(" ") + return + } + + for _, n := range list { + h.dumpNodeHTML(n, depth, "") + } +} + +func isValid(t types2.Type) bool { + return t != nil && types2.Unalias(t) != types2.Typ[types2.Invalid] +} + +const indentString = ". " + +func (w *HTMLWriter) indent(n int) { + w.Print("\n") + for range n { + w.Print(indentString) + } +} + +// indentForToggle prints indentation to w. +func (h *HTMLWriter) indentForToggle(depth int, hasChildren bool) { + h.Print("\n") + if depth == 0 { + return + } + for range depth - 1 { + h.Print(indentString) + } + if hasChildren { + // Remove 2 spaces, which have similar rendered width to + // leading ir.DownArrow and trailing space. + h.Print(indentString[:len(indentString)-2]) + } else { + h.Print(indentString) + } +} + +// dumpScopeHTML writes a string representation of the scope to w, +// with the scope elements sorted by name. +// The level of indentation is controlled by n >= 0, with +// n == 0 for no indentation. +// If recurse is set, it also writes nested (children) scopes. +func (h *HTMLWriter) dumpScopeHTML(s *types2.Scope, depth int, recur bool) { + hasChildren := true // TODO detect empty scopes + h.indentForToggle(depth, hasChildren) + if hasChildren { + h.Printf("", h.CanonId(s)) + defer h.Printf("") + // NOTE TRAILING SPACE after ! See indentForToggle above. + h.Print(`` + ir.DownArrow + ` `) + } + h.Printf("scope %s %p", html.EscapeString(s.Comment()), s) + + if hasChildren { + h.Print(``) + defer h.Print(``) + + for _, name := range s.Names() { + obj := s.Lookup(name) + h.dumpOutlineNodeHTML(depth+1, "", obj) + } + + if recur { + for i := range s.NumChildren() { + c := s.Child(i) + h.dumpScopeHTML(c, depth+1, recur) + } + } + } +} + +func (h *HTMLWriter) dumpOutlineNodeHTML(depth int, pfx string, obj fmt.Stringer) { + h.indentForToggle(depth, false) + h.Printf("%s%s", + h.CanonId(obj), pfx, html.EscapeString(obj.String())) +} + +func (h *HTMLWriter) dumpNodeHTML(n syntax.Node, depth int, prefix string) { + hasChildren := h.nodeHasChildren(n) + h.indentForToggle(depth, hasChildren) + + if depth > 40 { + h.Print("...") + return + } + + if n == nil { + h.Print("NilSyntaxNode") + return + } + + h.Printf("", h.CanonId(n)) + defer h.Printf("") + + if hasChildren { + // NOTE TRAILING SPACE after ! See indentForToggle above. + h.Print(`` + ir.DownArrow + ` `) // NOTE TRAILING SPACE after ! + } + + opName := strings.TrimPrefix(fmt.Sprintf("%T", n), "*syntax.") + + if prefix != "" { + h.Printf("%s", html.EscapeString(prefix)) + } + + switch n := n.(type) { + case *syntax.BasicLit: + h.Printf("%s-%v", opName, html.EscapeString(n.Value)) + h.dumpNodeHeaderHTML(n) + return + + case *syntax.Name: + name := n.Value + hash := sha256.Sum256([]byte(name)) + symID := "sym-" + hex.EncodeToString(hash[:6]) + h.Printf("%s-%s", opName, symID, html.EscapeString(name)) + h.dumpNodeHeaderHTML(n) + if hasChildren { + h.Print(``) + defer h.Print(``) + + if obj := h.info.ObjectOf(n); obj != nil { + h.dumpOutlineNodeHTML(depth+1, "objectOf=", obj) + } + if typ := h.info.TypeOf(n); isValid(typ) { + h.dumpOutlineNodeHTML(depth+1, "typeOf=", typ) + } + } + return + + case syntax.Expr: + h.Printf("%s", opName) + h.dumpNodeHeaderHTML(n) + if hasChildren { + h.Print(``) + defer h.Print(``) + + if typ := h.info.TypeOf(n); isValid(typ) { + h.dumpOutlineNodeHTML(depth+1, "typeOf=", typ) + } + } + + default: + h.Printf("%s", opName) + h.dumpNodeHeaderHTML(n) + if hasChildren { + h.Print(``) + defer h.Print(``) + } + } + + if s := h.info.Scopes[n]; s != nil && s.Len() > 0 { + h.dumpScopeHTML(s, depth+1, false) + } + + v := reflect.ValueOf(n).Elem() + t := v.Type() + nf := t.NumField() + for i := 0; i < nf; i++ { + tf := t.Field(i) + vf := v.Field(i) + if tf.PkgPath != "" { + continue + } + switch tf.Type.Kind() { + case reflect.Interface, reflect.Ptr, reflect.Slice: + if vf.IsNil() { + continue + } + } + name := strings.TrimSuffix(tf.Name, "_") + + switch val := vf.Interface().(type) { + case syntax.Node: + if name != "" { + h.dumpNodeHTML(val, depth+1, name+": ") + } else { + h.dumpNodeHTML(val, depth+1, "") + } + default: + if vf.Kind() == reflect.Slice && vf.Type().Elem().Implements(nodeType) { + if vf.Len() == 0 { + continue + } + if name != "" { + for i := range vf.Len() { + h.dumpNodeHTML(vf.Index(i).Interface().(syntax.Node), depth+1, + fmt.Sprintf("%s[%d]: ", name, i)) + } + } else { + for i := range vf.Len() { + h.dumpNodeHTML(vf.Index(i).Interface().(syntax.Node), depth+1, "") + } + } + } + } + } +} + +var nodeType = reflect.TypeFor[syntax.Node]() + +func (h *HTMLWriter) nodeHasChildren(n syntax.Node) bool { + if n == nil { + return false + } + switch x := n.(type) { + case *syntax.BasicLit: + return false + case *syntax.Name: + return h.info.ObjectOf(x) != nil || isValid(h.info.TypeOf(x)) + case syntax.Expr: + if isValid(h.info.TypeOf(x)) { + return true + } + } + + v := reflect.ValueOf(n).Elem() + t := reflect.TypeOf(n).Elem() + nf := t.NumField() + for i := 0; i < nf; i++ { + tf := t.Field(i) + vf := v.Field(i) + if tf.PkgPath != "" { + continue + } + switch tf.Type.Kind() { + case reflect.Interface, reflect.Ptr, reflect.Slice: + if vf.IsNil() { + continue + } + } + switch vf.Interface().(type) { + case syntax.Node: + return true + default: + if vf.Kind() == reflect.Slice && vf.Type().Elem().Implements(nodeType) && vf.Len() > 0 { + return true + } + } + } + return false +} + +func (h *HTMLWriter) dumpNodeHeaderHTML(n syntax.Node) { + v := reflect.ValueOf(n).Elem() + t := v.Type() + nf := t.NumField() + for i := 0; i < nf; i++ { + tf := t.Field(i) + if tf.PkgPath != "" { + continue + } + k := tf.Type.Kind() + if reflect.Bool <= k && k <= reflect.Complex128 || k == reflect.String { + name := strings.TrimSuffix(tf.Name, "_") + if name == "Value" { + continue + } + vf := v.Field(i) + vfi := vf.Interface() + if vf.IsZero() { + continue + } + if vfi == true { + h.Printf(" %s", name) + } else { + h.Printf(" %s:%+v", name, html.EscapeString(fmt.Sprint(vf.Interface()))) + } + } + } + + if n.Pos().IsKnown() { + h.Print(" ") + file := n.Pos().Base().Filename() + if file != "" { + hash := sha256.Sum256([]byte(file)) + fileID := "loc-" + hex.EncodeToString(hash[:6]) + lineID := fmt.Sprintf("%s-L%d", fileID, n.Pos().Line()) + colID := fmt.Sprintf("%s-C%d", lineID, n.Pos().Col()) + + h.Printf("%s:", fileID, html.EscapeString(filepath.Base(file))) + h.Printf("%d:", lineID, fileID, n.Pos().Line()) + h.Printf("%d", colID, lineID, fileID, n.Pos().Col()) + } else { + h.Printf("%v", html.EscapeString(n.Pos().String())) + } + h.Print("") + } +} diff --git a/src/cmd/compile/internal/noder/import.go b/src/cmd/compile/internal/noder/import.go index 910988f0612ca9..1069cbdfe8f3f5 100644 --- a/src/cmd/compile/internal/noder/import.go +++ b/src/cmd/compile/internal/noder/import.go @@ -192,7 +192,10 @@ func readImportFile(path string, target *ir.Package, env *types2.Context, packag pkg1 = types.NewPkg(path, "") if packages != nil { pkg2 = packages[path] - assert(pkg1.Direct == (pkg2 != nil && pkg2.Complete())) + if !(pkg1.Direct == (pkg2 != nil && pkg2.Complete())) { + + base.Fatalf("pkg1.Direct == (pkg2 != nil && pkg2.Complete()), path=%s\npackages=%v", path, packages) + } } if pkg1.Direct { diff --git a/src/cmd/compile/internal/noder/irgen.go b/src/cmd/compile/internal/noder/irgen.go index 05f0affe8a8a43..e8b177f18fa12e 100644 --- a/src/cmd/compile/internal/noder/irgen.go +++ b/src/cmd/compile/internal/noder/irgen.go @@ -12,8 +12,11 @@ import ( "sort" "cmd/compile/internal/base" + "cmd/compile/internal/midway" "cmd/compile/internal/rangefunc" "cmd/compile/internal/syntax" + "cmd/compile/internal/typecheck" + "cmd/compile/internal/types" "cmd/compile/internal/types2" "cmd/internal/src" ) @@ -44,6 +47,9 @@ func checkFiles(m posMap, noders []*noder) (*types2.Package, *types2.Info, map[* fileBaseMap[p.file.Pos().FileBase()] = p.file } + didMidway := false + +recheck: // typechecking ctxt := types2.NewContext() importer := gcimports{ @@ -56,7 +62,6 @@ func checkFiles(m posMap, noders []*noder) (*types2.Package, *types2.Info, map[* IgnoreBranchErrors: true, // parser already checked via syntax.CheckBranches mode Importer: &importer, Sizes: types2.SizesFor("gc", buildcfg.GOARCH), - EnableAlias: true, } if base.Flag.ErrorURL { conf.ErrorURL = " [go.dev/e/%s]" @@ -172,6 +177,33 @@ func checkFiles(m posMap, noders []*noder) (*types2.Package, *types2.Info, map[* } base.ExitIfErrors() + if len(base.Debug.AstDump) > 0 { + dumpSyntax(pkg, info, files, "checked") + } + + if buildcfg.Experiment.SIMD && !didMidway { + didMidway = true + // Perform midway transformation on AST directly + if midway.RewriteWrapper(pkg, info, files) { + // midway made changes; type checking must be repeated. + if len(base.Debug.AstDump) > 0 { + // TODO how should this interact with -W and textual dumps + dumpSyntax(pkg, info, files, "midway before recheck") + } + // necessary to reset type checking + for _, p := range types.PkgMap() { + p.Direct = false + } + // necessary to reset type checking + typecheck.Target.Imports = nil + goto recheck + } + } + + if len(base.Debug.AstDump) > 0 { + dumpSyntax(pkg, info, files, "midway after recheck") + } + // Rewrite range over function to explicit function calls // with the loop bodies converted into new implicit closures. // We do this now, before serialization to unified IR, so that if the @@ -181,9 +213,25 @@ func checkFiles(m posMap, noders []*noder) (*types2.Package, *types2.Info, map[* // and bodyReaderFor will fail. rangeInfo := rangefunc.Rewrite(pkg, info, files) + if len(base.Debug.AstDump) > 0 { + dumpSyntax(pkg, info, files, "rangefunc") + } + return pkg, info, rangeInfo } +func dumpSyntax(pkg *types2.Package, info *types2.Info, files []*syntax.File, phase string) { + for _, file := range files { + for _, decl := range file.DeclList { + if fn, ok := decl.(*syntax.FuncDecl); ok { + if MatchASTDump(fn) { + DumpNodeHTML(pkg, file, info, fn, phase, fn) + } + } + } + } +} + // A cycleFinder detects anonymous interface cycles (go.dev/issue/56103). type cycleFinder struct { cyclic map[*types2.Interface]bool diff --git a/src/cmd/compile/internal/noder/linker.go b/src/cmd/compile/internal/noder/linker.go index 51b03a1897e830..df1e248398b8c8 100644 --- a/src/cmd/compile/internal/noder/linker.go +++ b/src/cmd/compile/internal/noder/linker.go @@ -338,6 +338,7 @@ func (l *linker) linkname(w *pkgbits.Encoder, name *ir.Name) { linkname := name.Sym().Linkname if !l.lsymIdx(w, linkname, name.Linksym()) { w.String(linkname) + w.Bool(name.Linksym().IsLinknameStd()) } } diff --git a/src/cmd/compile/internal/noder/noder.go b/src/cmd/compile/internal/noder/noder.go index 79a90783336030..5d33072690f075 100644 --- a/src/cmd/compile/internal/noder/noder.go +++ b/src/cmd/compile/internal/noder/noder.go @@ -41,7 +41,6 @@ func LoadPackage(filenames []string) { // Move the entire syntax processing logic into a separate goroutine to avoid blocking on the "sem". go func() { for i, filename := range filenames { - filename := filename p := noders[i] sem <- struct{}{} go func() { @@ -104,9 +103,10 @@ type noder struct { err chan syntax.Error } -// linkname records a //go:linkname directive. +// linkname records a //go:linkname or //go:linknamestd directive. type linkname struct { pos syntax.Pos + std bool local string remote string } @@ -175,6 +175,10 @@ type pragmas struct { WasmExport *WasmExport } +func (p *pragmas) Nointerface() bool { + return p.Flag&ir.Nointerface != 0 +} + // WasmImport stores metadata associated with the //go:wasmimport pragma type WasmImport struct { Pos syntax.Pos @@ -274,10 +278,10 @@ func (p *noder) pragma(pos syntax.Pos, blankLine bool, text string, old syntax.P } } - case strings.HasPrefix(text, "go:linkname "): + case strings.HasPrefix(text, "go:linkname "), strings.HasPrefix(text, "go:linknamestd "): f := strings.Fields(text) if !(2 <= len(f) && len(f) <= 3) { - p.error(syntax.Error{Pos: pos, Msg: "usage: //go:linkname localname [linkname]"}) + p.error(syntax.Error{Pos: pos, Msg: fmt.Sprintf("usage: //%s localname [linkname]", f[0])}) break } // The second argument is optional. If omitted, we use @@ -295,7 +299,7 @@ func (p *noder) pragma(pos syntax.Pos, blankLine bool, text string, old syntax.P } else { panic("missing pkgpath") } - p.linknames = append(p.linknames, linkname{pos, f[1], target}) + p.linknames = append(p.linknames, linkname{pos, f[0] == "go:linknamestd", f[1], target}) case text == "go:embed", strings.HasPrefix(text, "go:embed "): args, err := parseGoEmbed(text[len("go:embed"):]) diff --git a/src/cmd/compile/internal/noder/reader.go b/src/cmd/compile/internal/noder/reader.go index d7dd58d8caafe8..405f9c44ad372d 100644 --- a/src/cmd/compile/internal/noder/reader.go +++ b/src/cmd/compile/internal/noder/reader.go @@ -19,6 +19,7 @@ import ( "cmd/compile/internal/inline/interleaved" "cmd/compile/internal/ir" "cmd/compile/internal/objw" + "cmd/compile/internal/pgoir" "cmd/compile/internal/reflectdata" "cmd/compile/internal/staticinit" "cmd/compile/internal/typecheck" @@ -100,6 +101,11 @@ type reader struct { dict *readerDict + // funcLitGen is a counter for closure names. + funcLitGen int + // rangeLitGen is a counter for range func closure names. + rangeLitGen int + // TODO(mdempsky): The state below is all specific to reading // function bodies. It probably makes sense to split it out // separately so that it doesn't take up space in every reader @@ -198,6 +204,9 @@ type readerDict struct { // implicits counts how many of types within targs are implicit type // arguments; the rest are explicit. implicits int + // receivers counts how many of types within targs are receiver type + // arguments; they are explicit. + receivers int derived []derivedInfo // reloc index of the derived type's descriptor derivedTypes []*types.Type // slice of previously computed derived types @@ -781,17 +790,32 @@ func (pr *pkgReader) objIdxMayFail(idx index, implicits, explicits []*types.Type return name, nil case pkgbits.ObjFunc: - if sym.Name == "init" { - sym = Renameinit() - } - npos := r.pos() setBasePos(npos) + + var sel *types.Sym + var recv *types.Field + if r.Version().Has(pkgbits.GenericMethods) && r.Bool() { + sel = r.selector() + r.recvTypeParamNames() + recv = r.param() + if r.Version().Has(pkgbits.PreserveMethodOrder) { + _ = r.Len() // method index not needed in compiler + } + } else { + if sym.Name == "init" { + sym = Renameinit() + } + } r.typeParamNames() - typ := r.signature(nil) + typ := r.signature(recv) fpos := r.pos() fn := ir.NewFunc(fpos, npos, sym, typ) + if r.hasTypeParams() && r.dict.shaped { + typ.SetHasShape(true) + } + name := fn.Nname if !sym.IsBlank() { if sym.Def != nil { @@ -812,7 +836,7 @@ func (pr *pkgReader) objIdxMayFail(idx index, implicits, explicits []*types.Type } } - rext.funcExt(name, nil) + rext.funcExt(name, sel) return name, nil case pkgbits.ObjType: @@ -860,39 +884,83 @@ func (pr *pkgReader) objIdxMayFail(idx index, implicits, explicits []*types.Type } } +// mangle shapes the non-shaped symbol sym under the current dictionary. func (dict *readerDict) mangle(sym *types.Sym) *types.Sym { if !dict.hasTypeParams() { return sym } + var buf strings.Builder // If sym is a locally defined generic type, we need the suffix to // stay at the end after mangling so that types/fmt.go can strip it // out again when writing the type's runtime descriptor (#54456). - base, suffix := types.SplitVargenSuffix(sym.Name) + n0, vsuff := types.SplitVargenSuffix(sym.Name) + n1, msuff := types.SplitMethSuffix(sym.Name) + + // Methods are never locally defined. + var n string + assert(vsuff == "" || msuff == "") + if vsuff != "" { + n = n0 + } else { + n = n1 + } - var buf strings.Builder - buf.WriteString(base) - buf.WriteByte('[') - for i, targ := range dict.targs { - if i > 0 { - if i == dict.implicits { - buf.WriteByte(';') - } else { + var j int + assert(dict.implicits == 0 || dict.receivers == 0) + if msuff != "" { + j = dict.receivers // consume receiver type arguments + } else { + j = len(dict.targs) // consume all type arguments + } + + // put type arguments inside parenthesis; (*T)[int] -> (*T[int]) + n, ok := strings.CutSuffix(n, ")") + + // type arguments, if any + buf.WriteString(n) + if j > 0 { + buf.WriteByte('[') + for i := 0; i < j; i++ { + if i > 0 { + if i == dict.implicits { + buf.WriteByte(';') + } else { + buf.WriteByte(',') + } + } + buf.WriteString(dict.targs[i].LinkString()) + } + buf.WriteByte(']') + } + + if ok { + buf.WriteString(")") + } + + buf.WriteString(vsuff) + buf.WriteString(msuff) + + // method arguments, if any + if msuff != "" { + buf.WriteByte('[') + for i := j; i < len(dict.targs); i++ { + if i > j { buf.WriteByte(',') } + buf.WriteString(dict.targs[i].LinkString()) } - buf.WriteString(targ.LinkString()) + buf.WriteByte(']') } - buf.WriteByte(']') - buf.WriteString(suffix) + return sym.Pkg.Lookup(buf.String()) } -// shapify returns the shape type for targ. +// Shapify returns the shape type for targ. // // If basic is true, then the type argument is used to instantiate a // type parameter whose constraint is a basic interface. -func shapify(targ *types.Type, basic bool) *types.Type { +func Shapify(targ *types.Type, basic bool) *types.Type { if targ.Kind() == types.TFORW { if targ.IsFullyInstantiated() { // For recursive instantiated type argument, it may still be a TFORW @@ -930,19 +998,8 @@ func shapify(targ *types.Type, basic bool) *types.Type { // types, and discarding struct field names and tags. However, we'll // need to start tracking how type parameters are actually used to // implement some of these optimizations. - pointerShaping := basic && targ.IsPtr() && !targ.Elem().NotInHeap() - // The exception is when the type parameter is a pointer to a type - // which `Type.HasShape()` returns true, but `Type.IsShape()` returns - // false, like `*[]go.shape.T`. This is because the type parameter is - // used to instantiate a generic function inside another generic function. - // In this case, we want to keep the targ as-is, otherwise, we may lose the - // original type after `*[]go.shape.T` is shapified to `*go.shape.uint8`. - // See issue #54535, #71184. - if pointerShaping && !targ.Elem().IsShape() && targ.Elem().HasShape() { - return targ - } under := targ.Underlying() - if pointerShaping { + if basic && targ.IsPtr() && !targ.Elem().NotInHeap() { under = types.NewPtr(types.Types[types.TUINT8]) } @@ -977,7 +1034,11 @@ func (pr *pkgReader) objDictIdx(sym *types.Sym, idx index, implicits, explicits } nimplicits := r.Len() - nexplicits := r.Len() + nreceivers := 0 + if r.Version().Has(pkgbits.GenericMethods) { + nreceivers = r.Len() + } + nexplicits := r.Len() + nreceivers if nimplicits > len(implicits) || nexplicits != len(explicits) { return nil, fmt.Errorf("%v has %v+%v params, but instantiated with %v+%v args", sym, nimplicits, nexplicits, len(implicits), len(explicits)) @@ -985,6 +1046,7 @@ func (pr *pkgReader) objDictIdx(sym *types.Sym, idx index, implicits, explicits dict.targs = append(implicits[:nimplicits:nimplicits], explicits...) dict.implicits = nimplicits + dict.receivers = nreceivers // Within the compiler, we can just skip over the type parameters. for range dict.targs[dict.implicits:] { @@ -1019,7 +1081,7 @@ func (pr *pkgReader) objDictIdx(sym *types.Sym, idx index, implicits, explicits for i, targ := range dict.targs { basic := r.Bool() if dict.shaped { - dict.targs[i] = shapify(targ, basic) + dict.targs[i] = Shapify(targ, basic) } } @@ -1051,10 +1113,19 @@ func (pr *pkgReader) objDictIdx(sym *types.Sym, idx index, implicits, explicits return &dict, nil } +func (r *reader) recvTypeParamNames() { + r.Sync(pkgbits.SyncTypeParamNames) + + for range r.dict.targs[r.dict.implicits : r.dict.implicits+r.dict.receivers] { + r.pos() + r.localIdent() + } +} + func (r *reader) typeParamNames() { r.Sync(pkgbits.SyncTypeParamNames) - for range r.dict.targs[r.dict.implicits:] { + for range r.dict.targs[r.dict.implicits+r.dict.receivers:] { r.pos() r.localIdent() } @@ -1062,6 +1133,9 @@ func (r *reader) typeParamNames() { func (r *reader) method(rext *reader) *types.Field { r.Sync(pkgbits.SyncMethod) + if r.Version().Has(pkgbits.PreserveMethodOrder) { + _ = r.Len() // method index not needed in compiler + } npos := r.pos() sym := r.selector() r.typeParamNames() @@ -1233,6 +1307,7 @@ func (r *reader) linkname(name *ir.Name) { lsym.Set(obj.AttrIndexed, true) } else { linkname := r.String() + std := r.Bool() sym := name.Sym() sym.Linkname = linkname if sym.Pkg == types.LocalPkg && linkname != "" { @@ -1242,7 +1317,11 @@ func (r *reader) linkname(name *ir.Name) { // corresponding packages). So we can tell in which package // the linkname is used (pulled), and the linker can // make a decision for allowing or disallowing it. - sym.Linksym().Set(obj.AttrLinkname, true) + if std { + sym.Linksym().Set(obj.AttrLinknameStd, true) + } else { + sym.Linksym().Set(obj.AttrLinkname, true) + } } } } @@ -1304,7 +1383,19 @@ func (r *reader) addBody(fn *ir.Func, method *types.Sym) { func (pri pkgReaderIndex) funcBody(fn *ir.Func) { r := pri.asReader(pkgbits.SectionBody, pkgbits.SyncFuncBody) + panicking := true + defer func() { + if panicking { + // TODO not sure what the best way to print in this context is. + // If code panics in unified IR reading, you want *something* like this. + // Whoever ends up debugging the next unified IR failure, please + // improve this (base.Warnf?) if you can figure out how. + fmt.Printf("****** panic traversed funcBody of %v\n", fn) + } + }() r.funcBody(fn) + panicking = false + } // funcBody reads a function body definition from the element @@ -1364,13 +1455,12 @@ func (r *reader) callShaped(pos src.XPos) { var shapedFn ir.Node if r.methodSym == nil { - // Instantiating a generic function; shapedObj is the shaped - // function itself. + // Instantiating a generic function; shapedObj is the shaped function itself. assert(shapedObj.Op() == ir.ONAME && shapedObj.Class == ir.PFUNC) shapedFn = shapedObj } else { - // Instantiating a generic type's method; shapedObj is the shaped - // type, so we need to select it's corresponding method. + // Instantiating a generic type's method; shapedObj is the shaped method itself + // if the method is generic — else, it is the shaped type declaring the method. shapedFn = shapedMethodExpr(pos, shapedObj, r.methodSym) } @@ -2496,6 +2586,11 @@ func (r *reader) expr() (res ir.Node) { } x.SetType(typ) + + if call, ok := x.(*ir.CallExpr); ok { + call.Reshape = true + } + return x case exprConvert: @@ -2507,6 +2602,22 @@ func (r *reader) expr() (res ir.Node) { identical := r.Bool() x := r.expr() + // spec: "If the type is a type parameter, the constant is converted + // into a non-constant value of the type parameter." + if dstTypeParam && ir.IsConstNode(x) { + // ConvertVal only handles conversions to constant types. + if v := typecheck.ConvertVal(x.Val(), typ, false); v.Kind() != constant.Unknown { + x = ir.NewBasicLit(x.Pos(), typ, v) + // Wrap in an OCONVNOP node to ensure result is non-constant. + n := Implicit(ir.NewConvExpr(pos, ir.OCONVNOP, typ, x)) + n.SetTypecheck(1) + return n + } + // A Go language constant could be converted to a non-constant value, + // like converting string to []byte/[]rune. In this case, just construct + // the conversion expression as usual, see #79960. + } + // TODO(mdempsky): Stop constructing expressions of untyped type. x = typecheck.DefaultLit(x, typ) @@ -2539,13 +2650,6 @@ func (r *reader) expr() (res ir.Node) { } } - // spec: "If the type is a type parameter, the constant is converted - // into a non-constant value of the type parameter." - if dstTypeParam && ir.IsConstNode(n) { - // Wrap in an OCONVNOP node to ensure result is non-constant. - n = Implicit(ir.NewConvExpr(pos, ir.OCONVNOP, n.Type(), n)) - n.SetTypecheck(1) - } return n case exprRuntimeBuiltin: @@ -2846,14 +2950,18 @@ func (r *reader) optExpr() ir.Node { // otherwise, they need to create their own wrapper. func (r *reader) methodExpr() (wrapperFn, baseFn, dictPtr ir.Node) { recv := r.typ() - sig0 := r.typ() + + var sig *types.Type + generic := r.Version().Has(pkgbits.GenericMethods) && r.Bool() + if !generic { + // Signature type to return (i.e., recv prepended to the method's + // normal parameters list). + sig = typecheck.NewMethodType(r.typ(), recv) + } + pos := r.pos() sym := r.selector() - // Signature type to return (i.e., recv prepended to the method's - // normal parameters list). - sig := typecheck.NewMethodType(sig0, recv) - if r.Bool() { // type parameter method expression idx := r.Len() word := r.dictWord(pos, r.dict.typeParamMethodExprsOffset()+idx) @@ -2871,20 +2979,12 @@ func (r *reader) methodExpr() (wrapperFn, baseFn, dictPtr ir.Node) { return fn, fn, nil } - // TODO(mdempsky): I'm pretty sure this isn't needed: implicits is - // only relevant to locally defined types, but they can't have - // (non-promoted) methods. - var implicits []*types.Type - if r.dict != nil { - implicits = r.dict.targs - } - if r.Bool() { // dynamic subdictionary idx := r.Len() info := r.dict.subdicts[idx] explicits := r.p.typListIdx(info.explicits, r.dict) - shapedObj := r.p.objIdx(info.idx, implicits, explicits, true).(*ir.Name) + shapedObj := r.p.objIdx(info.idx, nil, explicits, true).(*ir.Name) shapedFn := shapedMethodExpr(pos, shapedObj, sym) // TODO(mdempsky): Is there a more robust way to get the @@ -2899,10 +2999,10 @@ func (r *reader) methodExpr() (wrapperFn, baseFn, dictPtr ir.Node) { info := r.objInfo() explicits := r.p.typListIdx(info.explicits, r.dict) - shapedObj := r.p.objIdx(info.idx, implicits, explicits, true).(*ir.Name) + shapedObj := r.p.objIdx(info.idx, nil, explicits, true).(*ir.Name) shapedFn := shapedMethodExpr(pos, shapedObj, sym) - dict := r.p.objDictName(info.idx, implicits, explicits) + dict := r.p.objDictName(info.idx, nil, explicits) dictPtr := typecheck.Expr(ir.NewAddrExpr(pos, dict)) // Check that dictPtr matches shapedFn's dictionary parameter. @@ -2910,13 +3010,20 @@ func (r *reader) methodExpr() (wrapperFn, baseFn, dictPtr ir.Node) { base.FatalfAt(pos, "dict %L, but shaped method %L", dict, shapedFn) } - // For statically known instantiations, we can take advantage of - // the stenciled wrapper. - base.AssertfAt(!recv.HasShape(), pos, "shaped receiver %v", recv) - wrapperFn := typecheck.NewMethodExpr(pos, recv, sym) - base.AssertfAt(types.Identical(sig, wrapperFn.Type()), pos, "wrapper %L does not have type %v", wrapperFn, sig) - - return wrapperFn, shapedFn, dictPtr + if !generic { + // For statically known instantiations, we can take advantage of + // the stenciled wrapper. + base.AssertfAt(!recv.HasShape(), pos, "shaped receiver %v", recv) + wrapperFn := typecheck.NewMethodExpr(pos, recv, sym) + base.AssertfAt(types.Identical(sig, wrapperFn.Type()), pos, "wrapper %L does not have type %v", wrapperFn, sig) + return wrapperFn, shapedFn, dictPtr + } else { + // Also statically known, but there is a good amount of existing + // machinery downstream which makes assumptions about method + // wrapper functions. It's safest not to emit them for now. + // TODO(mark): Emit wrapper functions for generic methods. + return nil, shapedFn, dictPtr + } } // Simple method expression; no dictionary needed. @@ -2925,28 +3032,90 @@ func (r *reader) methodExpr() (wrapperFn, baseFn, dictPtr ir.Node) { return fn, fn, nil } -// shapedMethodExpr returns the specified method on the given shaped -// type. -func shapedMethodExpr(pos src.XPos, obj *ir.Name, sym *types.Sym) *ir.SelectorExpr { - assert(obj.Op() == ir.OTYPE) +// shapedMethodExpr creates an OMETHEXPR for obj using sym. +// +// If obj is an OTYPE, it must refer to a generic type. If obj is an ONAME, +// it must refer to a generic method. In either case, sym.Name must be the +// unqualified name of the method. +// +// For example, given: +// +// package p +// +// type T[P any] struct {} +// +// func (T[P]) m() {} +// func (T[P]) n[Q any]() {} +// +// then, using S as go.shape.int: +// - in T[int].m, obj is T[S] and sym.Name is "m". +// - in T[int].n[int], obj is T[S].n[S] and sym.Name is "n". +// +// Note that we could have pushed dictionaries down to methods in every case, +// but since non-generic methods will always share the same "type environment" +// as their defining type, we can optimize by reusing the type's dictionary. +func shapedMethodExpr(pos src.XPos, obj *ir.Name, sym *types.Sym) ir.Node { + if obj.Op() == ir.OTYPE { + // non-generic method on generic type + typ := obj.Type() + assert(typ.HasShape()) + + method := func() *types.Field { + for _, m := range typ.Methods() { + if m.Sym == sym { + return m + } + } - typ := obj.Type() - assert(typ.HasShape()) + base.FatalfAt(pos, "failed to find method %v in shaped type %v", sym, typ) + panic("unreachable") + }() - method := func() *types.Field { - for _, method := range typ.Methods() { - if method.Sym == sym { - return method + return typecheck.NewMethodExpr(pos, method.Type.Recv().Type, sym) + } else { + // generic method on possibly generic type + assert(obj.Op() == ir.ONAME && obj.Class == ir.PFUNC) + typ := obj.Type() + assert(typ.HasShape()) + + // OMETHEXPR assumes that the linker symbol to call looks like ".". + // This works because non-generic method symbols are relative to their type. But generic + // methods use fully-qualified names, so this won't work. + // + // To use OMETHEXPR for generic methods, we craft a dummy field on the type by removing + // the qualifier; OMETHEXPR will put it back later. + lsym := obj.Linksym().Name + // Since the method is generic, we know the method name must be followed by a bracket. + // TODO(mark): It's not ideal to rely on string naming here. Find a more robust solution. + idx := func() int { // Find the index of the bracket following the method name. + depth, i := 0, len(lsym)-1 + for { + switch lsym[i] { + case ']': + depth++ + case '[': + depth-- + } + if depth == 0 { + return i + } + i-- } - } + }() + msym := sym.Pkg.Lookup(lsym[idx-len(sym.Name):]) - base.FatalfAt(pos, "failed to find method %v in shaped type %v", sym, typ) - panic("unreachable") - }() + // Note that the field name here includes the type arguments; while also not ideal, the + // types package does not seem to complain. + m := types.NewField(obj.Pos(), msym, typ) + m.Nname = obj - // Construct an OMETHEXPR node. - recv := method.Type.Recv().Type - return typecheck.NewMethodExpr(pos, recv, sym) + n := ir.NewSelectorExpr(pos, ir.OMETHEXPR, ir.TypeNode(typ.Recv().Type), msym) + n.Selection = m + n.SetType(typecheck.NewMethodType(typ, typ.Recv().Type)) + n.SetTypecheck(1) + + return n + } } func (r *reader) multiExpr() []ir.Node { @@ -3005,7 +3174,7 @@ func (r *reader) tempCopy(pos src.XPos, expr ir.Node, init *ir.Nodes) *ir.Name { assign := ir.NewAssignStmt(pos, tmp, expr) assign.Def = true - init.Append(typecheck.Stmt(ir.NewAssignStmt(pos, tmp, expr))) + init.Append(typecheck.Stmt(assign)) tmp.Defn = assign @@ -3028,21 +3197,37 @@ func (r *reader) compLit() ir.Node { if typ.IsMap() { rtype = r.rtype(pos) } - isStruct := typ.Kind() == types.TSTRUCT - elems := make([]ir.Node, r.Len()) - for i := range elems { - elemp := &elems[i] - - if isStruct { - sk := ir.NewStructKeyExpr(r.pos(), typ.Field(r.Len()), nil) - *elemp, elemp = sk, &sk.Value - } else if r.Bool() { - kv := ir.NewKeyExpr(r.pos(), r.expr(), nil) - *elemp, elemp = kv, &kv.Value + var elems []ir.Node + if r.Version().Has(pkgbits.CompactCompLiterals) { + n := r.Int() + elems = make([]ir.Node, max(n, -n) /* abs(n) */) + switch typ.Kind() { + default: + base.FatalfAt(pos, "unexpected composite literal type: %v", typ) + case types.TARRAY: + r.arrayElems(n >= 0, elems) + case types.TMAP: + r.mapElems(elems) + case types.TSLICE: + r.arrayElems(n >= 0, elems) + case types.TSTRUCT: + r.structElems(typ, n >= 0, elems) + } + } else { + elems = make([]ir.Node, r.Len()) + isStruct := typ.Kind() == types.TSTRUCT + for i := range elems { + elemp := &elems[i] + if isStruct { + sk := ir.NewStructKeyExpr(r.pos(), typ.Field(r.Len()), nil) + *elemp, elemp = sk, &sk.Value + } else if r.Bool() { + kv := ir.NewKeyExpr(r.pos(), r.expr(), nil) + *elemp, elemp = kv, &kv.Value + } + *elemp = r.expr() } - - *elemp = r.expr() } lit := typecheck.Expr(ir.NewCompLitExpr(pos, ir.OCOMPLIT, typ, elems)) @@ -3057,6 +3242,64 @@ func (r *reader) compLit() ir.Node { return lit } +func (r *reader) arrayElems(valuesOnly bool, elems []ir.Node) { + if valuesOnly { + for i := range elems { + elems[i] = r.expr() + } + return + } + // some elements may have a key + for i := range elems { + if r.Bool() { + kv := ir.NewKeyExpr(r.pos(), r.expr(), nil) + kv.Value = r.expr() + elems[i] = kv + } else { + elems[i] = r.expr() + } + } +} + +func (r *reader) mapElems(elems []ir.Node) { + // all elements have a key + for i := range elems { + kv := ir.NewKeyExpr(r.pos(), r.expr(), nil) + kv.Value = r.expr() + elems[i] = kv + } +} + +func (r *reader) structElems(typ *types.Type, valuesOnly bool, elems []ir.Node) { + if valuesOnly { + for i := range elems { + sk := ir.NewStructKeyExpr(r.pos(), typ.Field(i), nil) + sk.Value = r.expr() + elems[i] = sk + } + return + } + + // all elements have a key + for i := range elems { + pos := r.pos() + var fld *types.Field + if n := r.Int(); n < 0 { + // embedded field + typ := typ // don't modify the original typ + for range -n { + fld = typ.Field(r.Int()) + typ = fld.Type + } + } else { // n >= 0 + fld = typ.Field(n) + } + sk := ir.NewStructKeyExpr(pos, fld, nil) + sk.Value = r.expr() + elems[i] = sk + } +} + func (r *reader) funcLit() ir.Node { r.Sync(pkgbits.SyncFuncLit) @@ -3112,8 +3355,17 @@ func (r *reader) inlClosureFunc(origPos src.XPos, sig *types.Type, why ir.Op) *i curfn = r.curfn } + var gen int + if why == ir.ORANGE { + r.rangeLitGen++ + gen = r.rangeLitGen + } else { + r.funcLitGen++ + gen = r.funcLitGen + } + // TODO(mdempsky): Remove hard-coding of typecheck.Target. - return ir.NewClosureFunc(origPos, r.inlPos(origPos), why, sig, curfn, typecheck.Target) + return ir.NewClosureFunc(origPos, r.inlPos(origPos), why, sig, curfn, typecheck.Target, gen) } func (r *reader) exprList() []ir.Node { @@ -3449,7 +3701,7 @@ var inlgen = 0 // unifiedInlineCall implements inline.NewInline by re-reading the function // body from its Unified IR export data. -func unifiedInlineCall(callerfn *ir.Func, call *ir.CallExpr, fn *ir.Func, inlIndex int) *ir.InlinedCallExpr { +func unifiedInlineCall(callerfn *ir.Func, call *ir.CallExpr, fn *ir.Func, inlIndex int, profile *pgoir.Profile) *ir.InlinedCallExpr { pri, ok := bodyReaderFor(fn) if !ok { base.FatalfAt(call.Pos(), "cannot inline call to %v: missing inline body", fn) @@ -3563,7 +3815,7 @@ func unifiedInlineCall(callerfn *ir.Func, call *ir.CallExpr, fn *ir.Func, inlInd // potentially be recursively inlined themselves; but we shouldn't // need to read in the non-inlined bodies for the declarations // themselves. But currently it's an easy fix to #50552. - readBodies(typecheck.Target, true) + readBodies(typecheck.Target, true, profile) // Replace any "return" statements within the function body. var edit func(ir.Node) ir.Node @@ -3599,6 +3851,7 @@ func unifiedInlineCall(callerfn *ir.Func, call *ir.CallExpr, fn *ir.Func, inlInd res.SetInit(init) res.SetType(call.Type()) res.SetTypecheck(1) + res.Reshape = call.Reshape // Inlining shouldn't add any functions to todoBodies. assert(len(todoBodies) == 0) @@ -3750,7 +4003,7 @@ type methodValueWrapper struct { // needWrapper records that wrapper methods may be needed at link // time. func (r *reader) needWrapper(typ *types.Type) { - if typ.IsPtr() { + if typ.IsPtr() || typ.IsKind(types.TFORW) { return } @@ -3993,9 +4246,12 @@ func addTailCall(pos src.XPos, fn *ir.Func, recv ir.Node, method *types.Field) { call := typecheck.Call(pos, dot, args, method.Type.IsVariadic()).(*ir.CallExpr) if recv.Type() != nil && recv.Type().IsPtr() && method.Type.Recv().Type.IsPtr() && - method.Embedded != 0 && !types.IsInterfaceMethod(method.Type) && - !unifiedHaveInlineBody(ir.MethodExprName(dot).Func) && - !(base.Ctxt.Arch.Name == "ppc64le" && base.Ctxt.Flag_dynlink) { + method.Embedded != 0 && + (types.IsInterfaceMethod(method.Type) && base.Ctxt.Arch.Name != "wasm" || + !types.IsInterfaceMethod(method.Type) && !unifiedHaveInlineBody(ir.MethodExprName(dot).Func)) && + // TODO: implement wasm indirect tail calls + // TODO: do we need the ppc64le/dynlink restriction for interface tail calls? + !((base.Ctxt.Arch.Name == "ppc64le" || base.Ctxt.Arch.Name == "ppc64") && base.Ctxt.Flag_dynlink) { if base.Debug.TailCall != 0 { base.WarnfAt(fn.Nname.Type().Recv().Type.Elem().Pos(), "tail call emitted for the method %v wrapper", method.Nname) } @@ -4034,6 +4290,8 @@ const dictParamName = typecheck.LocalDictName // // The parameter types.Fields are all copied too, so their Nname // fields can be initialized for use by the shape function. +// +// All signatures returned by shapeSig are marked as shaped. func shapeSig(fn *ir.Func, dict *readerDict) *types.Type { sig := fn.Nname.Type() oldRecv := sig.Recv() @@ -4056,5 +4314,7 @@ func shapeSig(fn *ir.Func, dict *readerDict) *types.Type { results[i] = types.NewField(result.Pos, result.Sym, result.Type) } - return types.NewSignature(recv, params, results) + typ := types.NewSignature(recv, params, results) + typ.SetHasShape(true) + return typ } diff --git a/src/cmd/compile/internal/noder/unified.go b/src/cmd/compile/internal/noder/unified.go index 05f4483d0d9f28..b8b0a0a144a6ec 100644 --- a/src/cmd/compile/internal/noder/unified.go +++ b/src/cmd/compile/internal/noder/unified.go @@ -24,6 +24,10 @@ import ( "cmd/internal/src" ) +// uirVersion is the unified IR version to use for encoding/decoding. +// Use V5 for generic method index ordering. +const uirVersion = pkgbits.V5 + // localPkgReader holds the package reader used for reading the local // package. It exists so the unified IR linker can refer back to it // later. @@ -76,7 +80,7 @@ func LookupFunc(fullName string) (*ir.Func, error) { // readBodies to post-process any funcs on the "todoBodies" list // that were added as a result of the lookup operations. func PostLookupCleanup() { - readBodies(typecheck.Target, false) + readBodies(typecheck.Target, false, nil) } func lookupFunction(pkg *types.Pkg, symName string) (*ir.Func, error) { @@ -201,7 +205,7 @@ func unified(m posMap, noders []*noder) { r := localPkgReader.newReader(pkgbits.SectionMeta, pkgbits.PrivateRootIdx, pkgbits.SyncPrivate) r.pkgInit(types.LocalPkg, target) - readBodies(target, false) + readBodies(target, false, nil) // Check that nothing snuck past typechecking. for _, fn := range target.Funcs { @@ -235,7 +239,7 @@ func unified(m posMap, noders []*noder) { // If duringInlining is true, then the inline.InlineDecls is called as // necessary on instantiations of imported generic functions, so their // inlining costs can be computed. -func readBodies(target *ir.Package, duringInlining bool) { +func readBodies(target *ir.Package, duringInlining bool, profile *pgoir.Profile) { var inlDecls []*ir.Func // Don't use range--bodyIdx can add closures to todoBodies. @@ -302,7 +306,7 @@ func readBodies(target *ir.Package, duringInlining bool) { oldLowerM := base.Flag.LowerM base.Flag.LowerM = 0 - inline.CanInlineFuncs(inlDecls, nil) + inline.CanInlineFuncs(inlDecls, profile) base.Flag.LowerM = oldLowerM for _, fn := range inlDecls { @@ -463,10 +467,8 @@ func readPackage(pr *pkgReader, importpkg *types.Pkg, localStub bool) { // writeUnifiedExport writes to `out` the finalized, self-contained // Unified IR export data file for the current compilation unit. func writeUnifiedExport(out io.Writer) { - // Use V2 as the encoded version for aliastypeparams. - version := pkgbits.V2 l := linker{ - pw: pkgbits.NewPkgEncoder(version, base.Debug.SyncFrames), + pw: pkgbits.NewPkgEncoder(uirVersion, base.Debug.SyncFrames), pkgs: make(map[string]index), decls: make(map[*types.Sym]index), @@ -487,6 +489,12 @@ func writeUnifiedExport(out io.Writer) { r.Sync(pkgbits.SyncPkg) selfPkgIdx = l.relocIdx(pr, pkgbits.SectionPkg, r.Reloc(pkgbits.SectionPkg)) + // Versions must match. + // TODO: It seems that we should be able to use r.Version() for NewPkgEncoder + // instead of passing uirVersion, but NewPkgEncoder is created before r. + // If that is correct, we should make that happen. + assert(r.Version() == uirVersion) + if r.Version().Has(pkgbits.HasInit) { r.Bool() } diff --git a/src/cmd/compile/internal/noder/writer.go b/src/cmd/compile/internal/noder/writer.go index 9c90d221c28a7e..8ca91973e3d632 100644 --- a/src/cmd/compile/internal/noder/writer.go +++ b/src/cmd/compile/internal/noder/writer.go @@ -11,7 +11,9 @@ import ( "go/version" "internal/buildcfg" "internal/pkgbits" + "log" "os" + "slices" "strings" "cmd/compile/internal/base" @@ -81,12 +83,16 @@ type pkgWriter struct { // Maps from types2.Objects back to their syntax.Decl. - funDecls map[*types2.Func]*syntax.FuncDecl - typDecls map[*types2.TypeName]typeDeclGen + funDecls map[*types2.Func]*syntax.FuncDecl + typDecls map[*types2.TypeName]typeDeclGen + methodIdx map[*types2.Func]int // method declaration order, for x/tools decoder (#81188) // linknames maps package-scope objects to their linker symbol name, - // if specified by a //go:linkname directive. - linknames map[types2.Object]string + // if specified by a //go:linkname or //go:linknamestd directive. + linknames map[types2.Object]struct { + remote string + std bool + } // cgoPragmas accumulates any //go:cgo_* pragmas that need to be // passed through to cmd/link. @@ -96,10 +102,8 @@ type pkgWriter struct { // newPkgWriter returns an initialized pkgWriter for the specified // package. func newPkgWriter(m posMap, pkg *types2.Package, info *types2.Info, otherInfo map[*syntax.FuncLit]bool) *pkgWriter { - // Use V2 as the encoded version for aliastypeparams. - version := pkgbits.V2 return &pkgWriter{ - PkgEncoder: pkgbits.NewPkgEncoder(version, base.Debug.SyncFrames), + PkgEncoder: pkgbits.NewPkgEncoder(uirVersion, base.Debug.SyncFrames), m: m, curpkg: pkg, @@ -112,20 +116,24 @@ func newPkgWriter(m posMap, pkg *types2.Package, info *types2.Info, otherInfo ma posBasesIdx: make(map[*syntax.PosBase]index), - funDecls: make(map[*types2.Func]*syntax.FuncDecl), - typDecls: make(map[*types2.TypeName]typeDeclGen), + funDecls: make(map[*types2.Func]*syntax.FuncDecl), + typDecls: make(map[*types2.TypeName]typeDeclGen), + methodIdx: make(map[*types2.Func]int), - linknames: make(map[types2.Object]string), + linknames: make(map[types2.Object]struct { + remote string + std bool + }), } } // errorf reports a user error about thing p. -func (pw *pkgWriter) errorf(p poser, msg string, args ...interface{}) { +func (pw *pkgWriter) errorf(p poser, msg string, args ...any) { base.ErrorfAt(pw.m.pos(p), 0, msg, args...) } // fatalf reports an internal compiler error about thing p. -func (pw *pkgWriter) fatalf(p poser, msg string, args ...interface{}) { +func (pw *pkgWriter) fatalf(p poser, msg string, args ...any) { base.FatalfAt(pw.m.pos(p), msg, args...) } @@ -198,9 +206,10 @@ type writer struct { // A writerDict tracks types and objects that are used by a declaration. type writerDict struct { - // implicits is a slice of type parameters from the enclosing - // declarations. + // implicits contains type parameters from enclosing declarations. implicits []*types2.TypeParam + // receivers contains receiver type parameters of the declaration. + receivers []*types2.TypeParam // derived is a slice of type indices for computing derived types // (i.e., types that depend on the declaration's type parameters). @@ -224,8 +233,7 @@ type itabInfo struct { // typeParamIndex returns the index of the given type parameter within // the dictionary. This may differ from typ.Index() when there are -// implicit type parameters due to defined types declared within a -// generic function or method. +// implicit or receiver type parameters. func (dict *writerDict) typeParamIndex(typ *types2.TypeParam) int { for idx, implicit := range dict.implicits { if implicit == typ { @@ -233,7 +241,13 @@ func (dict *writerDict) typeParamIndex(typ *types2.TypeParam) int { } } - return len(dict.implicits) + typ.Index() + for idx, receiver := range dict.receivers { + if receiver == typ { + return len(dict.implicits) + idx + } + } + + return len(dict.implicits) + len(dict.receivers) + typ.Index() } // A derivedInfo represents a reference to an encoded generic Go type. @@ -618,7 +632,7 @@ func (pw *pkgWriter) typIdx(typ types2.Type, dict *writerDict) typeInfo { } // namedType writes a use of the given named type into the bitstream. -func (w *writer) namedType(obj *types2.TypeName, targs *types2.TypeList) { +func (w *writer) namedType(obj *types2.TypeName, targs []types2.Type) { // Named types that are declared within a generic function (and // thus have implicit type parameters) are always derived types. if w.p.hasImplicitTypeParams(obj) { @@ -723,7 +737,7 @@ func (w *writer) param(param *types2.Var) { // If obj is a generic object, then explicits are the explicit type // arguments used to instantiate it (i.e., used to substitute the // object's own declared type parameters). -func (w *writer) obj(obj types2.Object, explicits *types2.TypeList) { +func (w *writer) obj(obj types2.Object, explicits []types2.Type) { w.objInfo(w.p.objInstIdx(obj, explicits, w.dict)) } @@ -745,10 +759,10 @@ func (w *writer) objInfo(info objInfo) { // objInstIdx returns the indices for an object and a corresponding // list of type arguments used to instantiate it, adding them to the // export data as needed. -func (pw *pkgWriter) objInstIdx(obj types2.Object, explicits *types2.TypeList, dict *writerDict) objInfo { - explicitInfos := make([]typeInfo, explicits.Len()) +func (pw *pkgWriter) objInstIdx(obj types2.Object, explicits []types2.Type, dict *writerDict) objInfo { + explicitInfos := make([]typeInfo, len(explicits)) for i := range explicitInfos { - explicitInfos[i] = pw.typIdx(explicits.At(i), dict) + explicitInfos[i] = pw.typIdx(explicits[i], dict) } return objInfo{idx: pw.objIdx(obj), explicits: explicitInfos} } @@ -769,10 +783,16 @@ func (pw *pkgWriter) objIdx(obj types2.Object) index { if isDefinedType(obj) && obj.Pkg() == pw.curpkg { decl, ok := pw.typDecls[obj.(*types2.TypeName)] - assert(ok) + if !ok { + base.Fatalf("%v not in pw.typDecls", obj.(*types2.TypeName)) + } dict.implicits = decl.implicits } + if isGenericMethod(obj.Type()) { + dict.receivers = asTypeParamSlice(obj.Type().(*types2.Signature).RecvTypeParams()) + } + // We encode objects into 4 elements across different sections, all // sharing the same index: // @@ -842,11 +862,34 @@ func (w *writer) doObj(wext *writer, obj types2.Object) pkgbits.CodeObj { return pkgbits.ObjConst case *types2.Func: + if base.Flag.LowerH > 0 { + // Unified IR panics are the worst; this is a huge help in debugging them. + defer func() { + if p := recover(); p != nil { + log.Printf("Intercepted unified IR writer panic for function %s, repanicking", obj.FullName()) + panic(p) + } + }() + } decl, ok := w.p.funDecls[obj] assert(ok) sig := obj.Type().(*types2.Signature) w.pos(obj) + if isGenericMethod(sig) { + w.Bool(true) // generic method + + w.selector(obj) + w.typeParamNames(sig.RecvTypeParams()) + w.param(sig.Recv()) + if w.Version().Has(pkgbits.PreserveMethodOrder) { + w.Len(w.p.methodIdx[obj.Origin()]) + } + } else { + if w.Version().Has(pkgbits.GenericMethods) { + w.Bool(false) // function + } + } w.typeParamNames(sig.TypeParams()) w.signature(sig) w.pos(decl) @@ -879,9 +922,31 @@ func (w *writer) doObj(wext *writer, obj types2.Object) pkgbits.CodeObj { wext.typeExt(obj) w.typ(named.Underlying()) - w.Len(named.NumMethods()) - for i := 0; i < named.NumMethods(); i++ { - w.method(wext, named.Method(i)) + // separate generic and non-generic methods + var methods, gmethods []*types2.Func + for i := range named.NumMethods() { + m := named.Method(i) + w.p.methodIdx[m] = i + if isGenericMethod(m.Type()) { + gmethods = append(gmethods, m) + } else { + methods = append(methods, m) + } + } + // encode non-generic methods inline + w.Len(len(methods)) + for _, m := range methods { + w.method(wext, m) + } + if len(gmethods) > 0 { + assert(w.Version().Has(pkgbits.GenericMethods)) + } + // encode a pointer to each generic method + if w.Version().Has(pkgbits.GenericMethods) { + w.Len(len(gmethods)) + for _, m := range gmethods { + w.Reloc(pkgbits.SectionObj, w.p.objIdx(m)) + } } return pkgbits.ObjType @@ -901,14 +966,23 @@ func (w *writer) objDict(obj types2.Object, dict *writerDict) { // doesn't care about referenced functions. w.dict = dict // TODO(mdempsky): This is a bit sketchy. - w.Len(len(dict.implicits)) + rtparams := objRecvTypeParams(obj) tparams := objTypeParams(obj) - ntparams := tparams.Len() - w.Len(ntparams) - for i := 0; i < ntparams; i++ { - w.typ(tparams.At(i).Constraint()) + + if w.Version().Has(pkgbits.GenericMethods) { + w.Len(len(rtparams)) + } else { + assert(len(rtparams) == 0) + } + w.Len(len(tparams)) + + for _, rtparam := range rtparams { + w.typ(rtparam.Constraint()) + } + for _, tparam := range tparams { + w.typ(tparam.Constraint()) } nderived := len(dict.derived) @@ -938,8 +1012,10 @@ func (w *writer) objDict(obj types2.Object, dict *writerDict) { for _, implicit := range dict.implicits { w.Bool(implicit.Underlying().(*types2.Interface).IsMethodSet()) } - for i := 0; i < ntparams; i++ { - tparam := tparams.At(i) + for _, rtparam := range rtparams { + w.Bool(rtparam.Underlying().(*types2.Interface).IsMethodSet()) + } + for _, tparam := range tparams { w.Bool(tparam.Underlying().(*types2.Interface).IsMethodSet()) } @@ -985,6 +1061,9 @@ func (w *writer) method(wext *writer, meth *types2.Func) { sig := meth.Type().(*types2.Signature) w.Sync(pkgbits.SyncMethod) + if w.Version().Has(pkgbits.PreserveMethodOrder) { + w.Len(w.p.methodIdx[meth.Origin()]) + } w.pos(meth) w.selector(meth) w.typeParamNames(sig.RecvTypeParams()) @@ -995,8 +1074,8 @@ func (w *writer) method(wext *writer, meth *types2.Func) { wext.funcExt(meth) } -// qualifiedIdent writes out the name of an object declared at package -// scope. (For now, it's also used to refer to local defined types.) +// qualifiedIdent writes out the name of an object typically declared at package +// scope. It's also used to refer to generic methods and locally defined types. func (w *writer) qualifiedIdent(obj types2.Object) { w.Sync(pkgbits.SyncSym) @@ -1014,6 +1093,17 @@ func (w *writer) qualifiedIdent(obj types2.Object) { } } + // Generic methods are promoted to objects and thus need qualified identifiers. + // They must be contextualized by their defining type. + if isGenericMethod(obj.Type()) { + recv := obj.Type().(*types2.Signature).Recv().Type() + fstr := "%s.%s" + if _, ok := types2.Unalias(recv).(*types2.Pointer); ok { + fstr = "(*%s).%s" + } + name = fmt.Sprintf(fstr, types2.Unalias(deref2(recv)).(*types2.Named).Obj().Name(), name) + } + w.pkg(obj.Pkg()) w.String(name) } @@ -1154,7 +1244,9 @@ func (w *writer) varExt(obj *types2.Var) { func (w *writer) linkname(obj types2.Object) { w.Sync(pkgbits.SyncLinkname) w.Int64(-1) - w.String(w.p.linknames[obj]) + info := w.p.linknames[obj] + w.String(info.remote) + w.Bool(info.std) } func (w *writer) pragmaFlag(p ir.PragmaFlag) { @@ -1557,7 +1649,7 @@ func (w *writer) forStmt(stmt *syntax.ForStmt) { func (w *writer) distinctVars(stmt *syntax.ForStmt) bool { lv := base.Debug.LoopVar - fileVersion := w.p.info.FileVersions[stmt.Pos().Base()] + fileVersion := w.p.info.FileVersions[stmt.Pos().FileBase()] is122 := fileVersion == "" || version.Compare(fileVersion, "go1.22") >= 0 // Turning off loopvar for 1.22 is only possible with loopvarhash=qn @@ -1801,7 +1893,7 @@ func (w *writer) expr(expr syntax.Expr) { expr = syntax.Unparen(expr) // skip parens; unneeded after typecheck obj, inst := lookupObj(w.p, expr) - targs := inst.TypeArgs + targs := asTypeSlice(inst.TypeArgs) if tv, ok := w.p.maybeTypeAndValue(expr); ok { if tv.IsRuntimeHelper() { @@ -1846,7 +1938,7 @@ func (w *writer) expr(expr syntax.Expr) { } if obj != nil { - if targs.Len() != 0 { + if len(targs) != 0 { obj := obj.(*types2.Func) w.Code(exprFuncInst) @@ -1896,41 +1988,30 @@ func (w *writer) expr(expr syntax.Expr) { w.selector(sel.Obj()) case types2.MethodVal: - w.Code(exprMethodVal) - typ := w.recvExpr(expr, sel) - w.pos(expr) - w.methodExpr(expr, typ, sel) + w.methVal(expr, sel) case types2.MethodExpr: - w.Code(exprMethodExpr) - - tv := w.p.typeAndValue(expr.X) - assert(tv.IsType()) - - index := sel.Index() - implicits := index[:len(index)-1] - - typ := tv.Type - w.typ(typ) - - w.Len(len(implicits)) - for _, ix := range implicits { - w.Len(ix) - typ = deref2(typ).Underlying().(*types2.Struct).Field(ix).Type() - } - - recv := sel.Obj().(*types2.Func).Type().(*types2.Signature).Recv().Type() - if w.Bool(isPtrTo(typ, recv)) { // need deref - typ = recv - } else if w.Bool(isPtrTo(recv, typ)) { // need addr - typ = recv - } - - w.pos(expr) - w.methodExpr(expr, typ, sel) + w.methExpr(expr, sel) } case *syntax.IndexExpr: + // might be explicit instantiation of a generic method + if selector, ok := expr.X.(*syntax.SelectorExpr); ok { + if sel, ok := w.p.info.Selections[selector]; ok { + switch sel.Kind() { + default: + w.p.fatalf(selector, "unexpected selection kind: %v", sel.Kind()) + case types2.FieldVal: + // not a method + case types2.MethodVal: + w.methVal(selector, sel) + return + case types2.MethodExpr: + w.methExpr(selector, sel) + return + } + } + } _ = w.p.typeOf(expr.Index) // ensure this is an index expression, not an instantiation xtyp := w.p.typeOf(expr.X) @@ -2102,7 +2183,11 @@ func (w *writer) expr(expr syntax.Expr) { writeFunExpr := func() { fun := syntax.Unparen(expr.Fun) - if selector, ok := fun.(*syntax.SelectorExpr); ok { + expr := fun + if idx, ok := expr.(*syntax.IndexExpr); ok { + expr = idx.X + } + if selector, ok := expr.(*syntax.SelectorExpr); ok { if sel, ok := w.p.info.Selections[selector]; ok && sel.Kind() == types2.MethodVal { w.Bool(true) // method call typ := w.recvExpr(selector, sel) @@ -2117,7 +2202,7 @@ func (w *writer) expr(expr syntax.Expr) { obj := obj.(*types2.Func) w.pos(fun) - w.funcInst(obj, inst.TypeArgs) + w.funcInst(obj, asTypeSlice(inst.TypeArgs)) return } @@ -2156,6 +2241,42 @@ func (w *writer) optExpr(expr syntax.Expr) { } } +func (w *writer) methVal(expr *syntax.SelectorExpr, sel *types2.Selection) { + w.Code(exprMethodVal) + typ := w.recvExpr(expr, sel) + w.pos(expr) + w.methodExpr(expr, typ, sel) +} + +func (w *writer) methExpr(expr *syntax.SelectorExpr, sel *types2.Selection) { + w.Code(exprMethodExpr) + + tv := w.p.typeAndValue(expr.X) + assert(tv.IsType()) + + index := sel.Index() + implicits := index[:len(index)-1] + + typ := tv.Type + w.typ(typ) + + w.Len(len(implicits)) + for _, ix := range implicits { + w.Len(ix) + typ = deref2(typ).Underlying().(*types2.Struct).Field(ix).Type() + } + + recv := sel.Obj().(*types2.Func).Type().(*types2.Signature).Recv().Type() + if w.Bool(isPtrTo(typ, recv)) { // need deref + typ = recv + } else if w.Bool(isPtrTo(recv, typ)) { // need addr + typ = recv + } + + w.pos(expr) + w.methodExpr(expr, typ, sel) +} + // recvExpr writes out expr.X, but handles any implicit addressing, // dereferencing, and field selections appropriate for the method // selection. @@ -2185,7 +2306,7 @@ func (w *writer) recvExpr(expr *syntax.SelectorExpr, sel *types2.Selection) type } // funcInst writes a reference to an instantiated function. -func (w *writer) funcInst(obj *types2.Func, targs *types2.TypeList) { +func (w *writer) funcInst(obj *types2.Func, targs []types2.Type) { info := w.p.objInstIdx(obj, targs, w.dict) // Type arguments list contains derived types; we can emit a static @@ -2213,7 +2334,18 @@ func (w *writer) methodExpr(expr *syntax.SelectorExpr, recv types2.Type, sel *ty sig := fun.Type().(*types2.Signature) w.typ(recv) - w.typ(sig) + + // only pass the signature if it's not a generic method + if isGenericMethod(sig) { + assert(w.Version().Has(pkgbits.GenericMethods)) + w.Bool(true) + } else { + if w.Version().Has(pkgbits.GenericMethods) { + w.Bool(false) + } + w.typ(sig) + } + w.pos(expr) w.selector(fun) @@ -2231,31 +2363,37 @@ func (w *writer) methodExpr(expr *syntax.SelectorExpr, recv types2.Type, sel *ty w.p.fatalf(expr, "isInterface inconsistency: %v and %v", recv, sig.Recv().Type()) } - if !isInterface(recv) { - if named, ok := types2.Unalias(deref2(recv)).(*types2.Named); ok { - obj, targs := splitNamed(named) - info := w.p.objInstIdx(obj, targs, w.dict) - - // Method on a derived receiver type. These can be handled by a - // static call to the shaped method, but require dynamically - // looking up the appropriate dictionary argument in the current - // function's runtime dictionary. - if w.p.hasImplicitTypeParams(obj) || info.anyDerived() { - w.Bool(true) // dynamic subdictionary - w.Len(w.dict.subdictIdx(info)) - return - } - - // Method on a fully known receiver type. These can be handled - // by a static call to the shaped method, and with a static - // reference to the receiver type's dictionary. - if targs.Len() != 0 { - w.Bool(false) // no dynamic subdictionary - w.Bool(true) // static dictionary - w.objInfo(info) - return - } + if isConcreteMethod(sig) { + tname, tExplicits := splitNamed(types2.Unalias(deref2(recv)).(*types2.Named)) + var info objInfo + if isGenericMethod(sig) { + // For generic methods, the shaped object is the method itself. + mExplicits := asTypeSlice(w.p.info.Instances[expr.Sel].TypeArgs) + info = w.p.objInstIdx(fun.Origin(), slices.Concat(tExplicits, mExplicits), w.dict) + } else { + // For non-generic concrete methods on generic types, the shaped object + // is the type. The method must be looked up on the type by name. + info = w.p.objInstIdx(tname, tExplicits, w.dict) + } + // We don't know all of the type arguments statically. These can be + // handled by a static call to the shaped method, but require + // dynamically looking up the appropriate dictionary argument + // in the current function's runtime dictionary. + if info.anyDerived() { + w.Bool(true) // dynamic subdictionary + w.Len(w.dict.subdictIdx(info)) + return } + // We know all of the type arguments statically. These can be handled + // by a static call to the shaped method, and with a static reference + // to either the receiver type's or method's dictionary (see above). + if len(info.explicits) > 0 { + w.Bool(false) // no dynamic subdictionary + w.Bool(true) // static dictionary + w.objInfo(info) + return + } + // no type arguments } w.Bool(false) // no dynamic subdictionary @@ -2346,6 +2484,25 @@ func (w *writer) compLit(lit *syntax.CompositeLit) { if ptr, ok := types2.CoreType(typ).(*types2.Pointer); ok { typ = ptr.Elem() } + + if w.Version().Has(pkgbits.CompactCompLiterals) { + switch typ0 := typ; typ := types2.CoreType(typ).(type) { + default: + w.p.fatalf(lit, "unexpected composite literal type: %v", typ) + case *types2.Array: + w.arrayElems(typ.Elem(), lit.ElemList) + case *types2.Map: + w.rtype(typ0) + w.mapElems(typ.Key(), typ.Elem(), lit.ElemList) + case *types2.Slice: + w.arrayElems(typ.Elem(), lit.ElemList) + case *types2.Struct: + w.structElems(typ, lit.NKeys == 0, lit.ElemList) + } + return + } + + // old format var keyType, elemType types2.Type var structType *types2.Struct switch typ0 := typ; typ := types2.CoreType(typ).(type) { @@ -2388,6 +2545,76 @@ func (w *writer) compLit(lit *syntax.CompositeLit) { } } +func (w *writer) arrayElems(elemType types2.Type, elems []syntax.Expr) { + valuesOnly := true + for _, elem := range elems { + if _, ok := elem.(*syntax.KeyValueExpr); ok { + valuesOnly = false + break + } + } + + if valuesOnly { + w.Int(len(elems)) + for _, elem := range elems { + w.implicitConvExpr(elemType, elem) + } + return + } + // some elements may have a key + w.Int(-len(elems)) + for _, elem := range elems { + if kv, ok := elem.(*syntax.KeyValueExpr); w.Bool(ok) { + w.pos(kv.Key) // use position of Key rather than of elem (which has position of ':') + w.implicitConvExpr(nil, kv.Key) + elem = kv.Value + } + w.implicitConvExpr(elemType, elem) + } +} + +func (w *writer) mapElems(keyType, valueType types2.Type, elems []syntax.Expr) { + // all elements have a key + w.Int(-len(elems)) + for _, elem := range elems { + kv := elem.(*syntax.KeyValueExpr) + w.pos(kv.Key) // use position of Key rather than of elem (which has position of ':') + w.implicitConvExpr(keyType, kv.Key) + w.implicitConvExpr(valueType, kv.Value) + } +} + +func (w *writer) structElems(typ *types2.Struct, valuesOnly bool, elems []syntax.Expr) { + n := len(elems) + if valuesOnly { + // no element has a key + w.Int(n) + for i, elem := range elems { + w.pos(elem) + w.implicitConvExpr(typ.Field(i).Type(), elem) + } + return + } + // all elements have a key + w.Int(-n) + for _, elem := range elems { + kv := elem.(*syntax.KeyValueExpr) + w.pos(kv.Key) // use position of Key rather than of elem (which has position of ':') + // TODO(gri): rather than doing this lookup again, perhaps the index should be recorded by types2 + fld, index, _ := types2.LookupFieldOrMethod(typ, false, w.p.curpkg, kv.Key.(*syntax.Name).Value) + if n := len(index); n > 1 { + // embedded field + w.Int(-n) + for _, i := range index { + w.Int(i) + } + } else { // n == 1 + w.Int(index[0]) + } + w.implicitConvExpr(fld.Type(), kv.Value) + } +} + func (w *writer) funcLit(expr *syntax.FuncLit) { sig := w.p.typeOf(expr).(*types2.Signature) @@ -2521,6 +2748,26 @@ func isInterface(typ types2.Type) bool { return ok } +// isConcreteMethod reports whether typ is a concrete method. That is, +// it's a method with a receiver that isn't an interface type. +func isConcreteMethod(typ types2.Type) bool { + sig, ok := typ.(*types2.Signature) + return ok && sig.Recv() != nil && !isInterface(sig.Recv().Type()) +} + +// TODO(mark): Use isGenericMethod. It is included now to help justify +// the existence of isConcreteMethod. + +// isGenericMethod reports whether typ is a generic method. That is, +// it's a method with type parameters apart from those which may or +// may not appear on the receiver type. +// +// Note that generic methods are always concrete methods. +func isGenericMethod(typ types2.Type) bool { + sig, ok := typ.(*types2.Signature) + return ok && sig.Recv() != nil && sig.TypeParams().Len() > 0 +} + // op writes an Op into the bitstream. func (w *writer) op(op ir.Op) { // TODO(mdempsky): Remove in favor of explicit codes? Would make @@ -2563,16 +2810,15 @@ type declCollector struct { } func (c *declCollector) withTParams(obj types2.Object) *declCollector { - tparams := objTypeParams(obj) - n := tparams.Len() - if n == 0 { + tparams := slices.Concat(objRecvTypeParams(obj), objTypeParams(obj)) + if len(tparams) == 0 { return c } copy := *c copy.implicits = copy.implicits[:len(copy.implicits):len(copy.implicits)] - for i := 0; i < n; i++ { - copy.implicits = append(copy.implicits, tparams.At(i)) + for _, tparam := range tparams { + copy.implicits = append(copy.implicits, tparam) } return © } @@ -2663,26 +2909,33 @@ func (pw *pkgWriter) collectDecls(noders []*noder) { pw.cgoPragmas = append(pw.cgoPragmas, p.pragcgobuf...) for _, l := range p.linknames { + directive := "go:linkname" + if l.std { + directive = "go:linknamestd" + } if !file.importedUnsafe { - pw.errorf(l.pos, "//go:linkname only allowed in Go files that import \"unsafe\"") + pw.errorf(l.pos, "//%s only allowed in Go files that import \"unsafe\"", directive) continue } if strings.Contains(l.remote, "[") && strings.Contains(l.remote, "]") { - pw.errorf(l.pos, "//go:linkname reference of an instantiation is not allowed") + pw.errorf(l.pos, "//%s reference of an instantiation is not allowed", directive) continue } switch obj := pw.curpkg.Scope().Lookup(l.local).(type) { case *types2.Func, *types2.Var: if _, ok := pw.linknames[obj]; !ok { - pw.linknames[obj] = l.remote + pw.linknames[obj] = struct { + remote string + std bool + }{l.remote, l.std} } else { - pw.errorf(l.pos, "duplicate //go:linkname for %s", l.local) + pw.errorf(l.pos, "duplicate //%s for %s", directive, l.local) } default: if types.AllowsGoVersion(1, 18) { - pw.errorf(l.pos, "//go:linkname must refer to declared function or variable") + pw.errorf(l.pos, "//%s must refer to declared function or variable", directive) } } } @@ -2998,44 +3251,72 @@ func fieldIndex(info *types2.Info, str *types2.Struct, key *syntax.Name) int { panic(fmt.Sprintf("%s: %v is not a field of %v", key.Pos(), field, str)) } +// objRecvTypeParams returns the receiver type parameters on the given object. +func objRecvTypeParams(obj types2.Object) []*types2.TypeParam { + if f, ok := obj.(*types2.Func); ok { + return asTypeParamSlice(f.Signature().RecvTypeParams()) + } + return nil +} + // objTypeParams returns the type parameters on the given object. -func objTypeParams(obj types2.Object) *types2.TypeParamList { - switch obj := obj.(type) { +func objTypeParams(obj types2.Object) []*types2.TypeParam { + switch t := obj.(type) { case *types2.Func: - sig := obj.Type().(*types2.Signature) - if sig.Recv() != nil { - return sig.RecvTypeParams() - } - return sig.TypeParams() + return asTypeParamSlice(t.Signature().TypeParams()) case *types2.TypeName: switch t := obj.Type().(type) { case *types2.Named: - return t.TypeParams() + return asTypeParamSlice(t.TypeParams()) case *types2.Alias: - return t.TypeParams() + return asTypeParamSlice(t.TypeParams()) } } return nil } +// asTypeParamSlice unpacks a types2.TypeParamList to a []types2.TypeParam +func asTypeParamSlice(l *types2.TypeParamList) []*types2.TypeParam { + if l.Len() == 0 { + return nil + } + s := make([]*types2.TypeParam, l.Len()) + for i := range l.Len() { + s[i] = l.At(i) + } + return s +} + // splitNamed decomposes a use of a defined type into its original // type definition and the type arguments used to instantiate it. -func splitNamed(typ *types2.Named) (*types2.TypeName, *types2.TypeList) { +func splitNamed(typ *types2.Named) (*types2.TypeName, []types2.Type) { base.Assertf(typ.TypeParams().Len() == typ.TypeArgs().Len(), "use of uninstantiated type: %v", typ) orig := typ.Origin() base.Assertf(orig.TypeArgs() == nil, "origin %v of %v has type arguments", orig, typ) base.Assertf(typ.Obj() == orig.Obj(), "%v has object %v, but %v has object %v", typ, typ.Obj(), orig, orig.Obj()) - return typ.Obj(), typ.TypeArgs() + return typ.Obj(), asTypeSlice(typ.TypeArgs()) } // splitAlias is like splitNamed, but for an alias type. -func splitAlias(typ *types2.Alias) (*types2.TypeName, *types2.TypeList) { +func splitAlias(typ *types2.Alias) (*types2.TypeName, []types2.Type) { orig := typ.Origin() base.Assertf(typ.Obj() == orig.Obj(), "alias type %v has object %v, but %v has object %v", typ, typ.Obj(), orig, orig.Obj()) - return typ.Obj(), typ.TypeArgs() + return typ.Obj(), asTypeSlice(typ.TypeArgs()) +} + +// asTypeSlice unpacks a types2.TypeList to a []types2.Type +func asTypeSlice(l *types2.TypeList) []types2.Type { + if l.Len() == 0 { + return nil + } + s := make([]types2.Type, l.Len()) + for i := range l.Len() { + s[i] = l.At(i) + } + return s } func asPragmaFlag(p syntax.Pragma) ir.PragmaFlag { diff --git a/src/cmd/compile/internal/ppc64/ssa.go b/src/cmd/compile/internal/ppc64/ssa.go index f0d228559f3a87..a0d81d31d6de7d 100644 --- a/src/cmd/compile/internal/ppc64/ssa.go +++ b/src/cmd/compile/internal/ppc64/ssa.go @@ -135,6 +135,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { // AND/OR Rarg1, Rtmp // STBCCC/STWCCC Rtmp, (Rarg0) // BNE -3(PC) + // LWSYNC ld := ppc64.ALBAR st := ppc64.ASTBCCC if v.Op == ssa.OpPPC64LoweredAtomicAnd32 || v.Op == ssa.OpPPC64LoweredAtomicOr32 { @@ -170,6 +171,10 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p3 := s.Prog(ppc64.ABNE) p3.To.Type = obj.TYPE_BRANCH p3.To.SetTarget(p) + // LWSYNC - Provide acquire ordering to pair with the + // release (pre-LWSYNC) above, making the operation + // sequentially consistent. + s.Prog(ppc64.ALWSYNC) case ssa.OpPPC64LoweredAtomicAdd32, ssa.OpPPC64LoweredAtomicAdd64: @@ -179,6 +184,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { // STDCCC/STWCCC Rout, (Rarg0) // BNE -3(PC) // MOVW Rout,Rout (if Add32) + // LWSYNC ld := ppc64.ALDAR st := ppc64.ASTDCCC if v.Op == ssa.OpPPC64LoweredAtomicAdd32 { @@ -188,10 +194,10 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { r0 := v.Args[0].Reg() r1 := v.Args[1].Reg() out := v.Reg0() - // LWSYNC - Assuming shared data not write-through-required nor - // caching-inhibited. See Appendix B.2.2.2 in the ISA 2.07b. - plwsync := s.Prog(ppc64.ALWSYNC) - plwsync.To.Type = obj.TYPE_NONE + // LWSYNC - Provide acquire ordering to pair with the + // release (pre-LWSYNC) above, making the operation + // sequentially consistent. + s.Prog(ppc64.ALWSYNC) // LDAR or LWAR p := s.Prog(ld) p.From.Type = obj.TYPE_MEM @@ -223,6 +229,11 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p5.From.Type = obj.TYPE_REG p5.From.Reg = out } + // LWSYNC - Provide acquire ordering to pair with the + // release (pre-LWSYNC) above, making the operation + // sequentially consistent. + plwsync2 := s.Prog(ppc64.ALWSYNC) + plwsync2.To.Type = obj.TYPE_NONE case ssa.OpPPC64LoweredAtomicExchange8, ssa.OpPPC64LoweredAtomicExchange32, @@ -1869,7 +1880,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { case ssa.OpPPC64CALLstatic: s.Call(v) - case ssa.OpPPC64CALLtail: + case ssa.OpPPC64CALLtail, ssa.OpPPC64CALLtailinter: s.TailCall(v) case ssa.OpPPC64CALLclosure, ssa.OpPPC64CALLinter: diff --git a/src/cmd/compile/internal/rangefunc/rewrite.go b/src/cmd/compile/internal/rangefunc/rewrite.go index 74c7f55801c6d7..2421efbad83f68 100644 --- a/src/cmd/compile/internal/rangefunc/rewrite.go +++ b/src/cmd/compile/internal/rangefunc/rewrite.go @@ -994,7 +994,14 @@ func (r *rewriter) computeBranchNext() { l := n.Label.Value labels = append(labels, l) f := forStack[len(forStack)-1] - r.labelLoop[l] = f + if _, existed := r.labelLoop[l]; existed { + // The typechecker has already validated that labels are unique within this scope. + // If a duplicate label 'X' is encountered, it must reside in a nested scope + // (e.g., inside a function literal). Because nested labels do not affect + // the current control flow analysis, they can be safely ignored. + } else { + r.labelLoop[l] = f + } } } else { n := stack[len(stack)-1] @@ -1175,7 +1182,7 @@ func (r *rewriter) bodyFunc(body []syntax.Stmt, lhs []syntax.Expr, def bool, fty Type: types2.NewSignatureType(nil, nil, nil, types2.NewTuple(params...), types2.NewTuple(results...), - false), + ftyp.Variadic()), } tv.SetIsValue() bodyFunc.SetTypeInfo(tv) diff --git a/src/cmd/compile/internal/reflectdata/alg.go b/src/cmd/compile/internal/reflectdata/alg.go index 7cc50d866f2740..f74a42eac11a6a 100644 --- a/src/cmd/compile/internal/reflectdata/alg.go +++ b/src/cmd/compile/internal/reflectdata/alg.go @@ -6,136 +6,93 @@ package reflectdata import ( "fmt" + "go/constant" + "strconv" + "strings" "cmd/compile/internal/base" - "cmd/compile/internal/compare" "cmd/compile/internal/ir" "cmd/compile/internal/objw" "cmd/compile/internal/typecheck" "cmd/compile/internal/types" "cmd/internal/obj" - "cmd/internal/src" ) -// AlgType returns the fixed-width AMEMxx variants instead of the general -// AMEM kind when possible. -func AlgType(t *types.Type) types.AlgKind { - a := types.AlgType(t) - if a == types.AMEM { - if t.Alignment() < int64(base.Ctxt.Arch.Alignment) && t.Alignment() < t.Size() { - // For example, we can't treat [2]int16 as an int32 if int32s require - // 4-byte alignment. See issue 46283. - return a - } - switch t.Size() { - case 0: - return types.AMEM0 - case 1: - return types.AMEM8 - case 2: - return types.AMEM16 - case 4: - return types.AMEM32 - case 8: - return types.AMEM64 - case 16: - return types.AMEM128 - } - } - - return a -} - // genhash returns a symbol which is the closure used to compute // the hash of a value of type t. -// Note: the generated function must match runtime.typehash exactly. func genhash(t *types.Type) *obj.LSym { - switch AlgType(t) { - default: - // genhash is only called for types that have equality - base.Fatalf("genhash %v", t) - case types.AMEM0: + return genhashSig(eqSignature(t)) +} + +func genhashSig(sig string) *obj.LSym { + if len(sig) > 0 && sig[0] == sigAlign { + _, sig = parseNum(sig[1:]) + } + switch sig { + case "": return sysClosure("memhash0") - case types.AMEM8: + case string(sigMemory) + "1": return sysClosure("memhash8") - case types.AMEM16: + case string(sigMemory) + "2": return sysClosure("memhash16") - case types.AMEM32: + case string(sigMemory) + "4": return sysClosure("memhash32") - case types.AMEM64: + case string(sigMemory) + "8": return sysClosure("memhash64") - case types.AMEM128: + case string(sigMemory) + "16": return sysClosure("memhash128") - case types.ASTRING: + case string(sigString): return sysClosure("strhash") - case types.AINTER: + case string(sigIface): return sysClosure("interhash") - case types.ANILINTER: + case string(sigEface): return sysClosure("nilinterhash") - case types.AFLOAT32: + case string(sigFloat32): return sysClosure("f32hash") - case types.AFLOAT64: + case string(sigFloat64): return sysClosure("f64hash") - case types.ACPLX64: + case string(sigFloat32) + string(sigFloat32): return sysClosure("c64hash") - case types.ACPLX128: + case string(sigFloat64) + string(sigFloat64): return sysClosure("c128hash") - case types.AMEM: - // For other sizes of plain memory, we build a closure - // that calls memhash_varlen. The size of the memory is - // encoded in the first slot of the closure. - closure := TypeLinksymLookup(fmt.Sprintf(".hashfunc%d", t.Size())) - if len(closure.P) > 0 { // already generated - return closure - } - if memhashvarlen == nil { - memhashvarlen = typecheck.LookupRuntimeFunc("memhash_varlen") - } - ot := 0 - ot = objw.SymPtr(closure, ot, memhashvarlen, 0) - ot = objw.Uintptr(closure, ot, uint64(t.Size())) // size encoded in closure - objw.Global(closure, int32(ot), obj.DUPOK|obj.RODATA) - return closure - case types.ASPECIAL: - break } - closure := TypeLinksymPrefix(".hashfunc", t) + closure := TypeLinksymLookup(".hashfunc." + sig) if len(closure.P) > 0 { // already generated return closure } - // Generate hash functions for subtypes. - // There are cases where we might not use these hashes, - // but in that case they will get dead-code eliminated. - // (And the closure generated by genhash will also get - // dead-code eliminated, as we call the subtype hashers - // directly.) - switch t.Kind() { - case types.TARRAY: - genhash(t.Elem()) - case types.TSTRUCT: - for _, f := range t.Fields() { - genhash(f.Type) + if sig[0] == sigMemory { + n, rest := parseNum(sig[1:]) + if rest == "" { + // Just M%d. We can make a memhash_varlen closure. + // The size of the memory region to hash is encoded in the closure. + if memhashvarlen == nil { + memhashvarlen = typecheck.LookupRuntimeFunc("memhash_varlen") + } + ot := 0 + ot = objw.SymPtr(closure, ot, memhashvarlen, 0) + ot = objw.Uintptr(closure, ot, uint64(n)) // size encoded in closue + objw.Global(closure, int32(ot), obj.DUPOK|obj.RODATA) + return closure } } if base.Flag.LowerR != 0 { - fmt.Printf("genhash %v %v\n", closure, t) + fmt.Printf("genhash %s\n", sig) } - fn := hashFunc(t) + fn := hashFunc(sig) // Build closure. It doesn't close over any variables, so // it contains just the function pointer. objw.SymPtr(closure, 0, fn.Linksym(), 0) objw.Global(closure, int32(types.PtrSize), obj.DUPOK|obj.RODATA) - return closure } -func hashFunc(t *types.Type) *ir.Func { - sym := TypeSymPrefix(".hash", t) +func hashFunc(sig string) *ir.Func { + sym := types.TypeSymLookup(".hash." + sig) if sym.Def != nil { return sym.Def.(*ir.Name).Func } @@ -143,10 +100,10 @@ func hashFunc(t *types.Type) *ir.Func { pos := base.AutogeneratedPos // less confusing than end of input base.Pos = pos - // func sym(p *T, h uintptr) uintptr + // func sym(p unsafe.Pointer, h uintptr) uintptr fn := ir.NewFunc(pos, pos, sym, types.NewSignature(nil, []*types.Field{ - types.NewField(pos, typecheck.Lookup("p"), types.NewPtr(t)), + types.NewField(pos, typecheck.Lookup("p"), types.Types[types.TUNSAFEPTR]), types.NewField(pos, typecheck.Lookup("h"), types.Types[types.TUINTPTR]), }, []*types.Field{ @@ -155,81 +112,99 @@ func hashFunc(t *types.Type) *ir.Func { )) sym.Def = fn.Nname fn.Pragma |= ir.Noinline // TODO(mdempsky): We need to emit this during the unified frontend instead, to allow inlining. - typecheck.DeclFunc(fn) np := fn.Dcl[0] nh := fn.Dcl[1] - switch t.Kind() { - case types.TARRAY: - // An array of pure memory would be handled by the - // standard algorithm, so the element type must not be - // pure memory. - hashel := hashfor(t.Elem()) - - // for i := 0; i < nelem; i++ - ni := typecheck.TempAt(base.Pos, ir.CurFunc, types.Types[types.TINT]) - init := ir.NewAssignStmt(base.Pos, ni, ir.NewInt(base.Pos, 0)) - cond := ir.NewBinaryExpr(base.Pos, ir.OLT, ni, ir.NewInt(base.Pos, t.NumElem())) - post := ir.NewAssignStmt(base.Pos, ni, ir.NewBinaryExpr(base.Pos, ir.OADD, ni, ir.NewInt(base.Pos, 1))) - loop := ir.NewForStmt(base.Pos, nil, cond, post, nil, false) - loop.PtrInit().Append(init) - - // h = hashel(&p[i], h) - call := ir.NewCallExpr(base.Pos, ir.OCALL, hashel, nil) - - nx := ir.NewIndexExpr(base.Pos, np, ni) - nx.SetBounded(true) - na := typecheck.NodAddr(nx) - call.Args.Append(na) - call.Args.Append(nh) - loop.Body.Append(ir.NewAssignStmt(base.Pos, nh, call)) - - fn.Body.Append(loop) + // Skip alignment, hash functions can handle unaligned data. + if len(sig) > 0 && sig[0] == sigAlign { + _, sig = parseNum(sig[1:]) + } - case types.TSTRUCT: - // Walk the struct using memhash for runs of AMEM - // and calling specific hash functions for the others. - for i, fields := 0, t.Fields(); i < len(fields); { - f := fields[i] + // offset from np that we're currently working on + var off int64 - // Skip blank fields. - if f.Sym.IsBlank() { - i++ - continue - } + // Return np+off (as an unsafe.Pointer). + ptr := func() ir.Node { + c := ir.NewBasicLit(pos, types.Types[types.TUINTPTR], constant.MakeInt64(off)) + return ir.NewBinaryExpr(pos, ir.OUNSAFEADD, np, c) + } + // hash data using function name at np+off. + // Increment off by size. + hash := func(name string, size int64) { + p := ptr() + hashFn := typecheck.LookupRuntime(name) + call := ir.NewCallExpr(pos, ir.OCALL, hashFn, []ir.Node{p, nh}) + fn.Body.Append(ir.NewAssignStmt(pos, nh, call)) + off += size + } - // Hash non-memory fields with appropriate hash function. - if !compare.IsRegularMemory(f.Type) { - hashel := hashfor(f.Type) - call := ir.NewCallExpr(base.Pos, ir.OCALL, hashel, nil) - na := typecheck.NodAddr(typecheck.DotField(base.Pos, np, i)) - call.Args.Append(na) - call.Args.Append(nh) - fn.Body.Append(ir.NewAssignStmt(base.Pos, nh, call)) - i++ - continue + for len(sig) > 0 { + kind := sig[0] + sig = sig[1:] + switch kind { + case sigMemory: + var n int64 + n, sig = parseNum(sig) + switch { + case n == 4: + p := ptr() + memhash := typecheck.LookupRuntime("memhash32") + call := ir.NewCallExpr(pos, ir.OCALL, memhash, []ir.Node{p, nh}) + fn.Body.Append(ir.NewAssignStmt(pos, nh, call)) + case n == 8: + p := ptr() + memhash := typecheck.LookupRuntime("memhash64") + call := ir.NewCallExpr(pos, ir.OCALL, memhash, []ir.Node{p, nh}) + fn.Body.Append(ir.NewAssignStmt(pos, nh, call)) + default: + p := ptr() + memhash := typecheck.LookupRuntime("memhash") + size := ir.NewBasicLit(pos, types.Types[types.TUINTPTR], constant.MakeInt64(n)) + call := ir.NewCallExpr(pos, ir.OCALL, memhash, []ir.Node{p, nh, size}) + fn.Body.Append(ir.NewAssignStmt(pos, nh, call)) } - - // Otherwise, hash a maximal length run of raw memory. - size, next := compare.Memrun(t, i) - - // h = hashel(&p.first, size, h) - hashel := hashmem(f.Type) - call := ir.NewCallExpr(base.Pos, ir.OCALL, hashel, nil) - na := typecheck.NodAddr(typecheck.DotField(base.Pos, np, i)) - call.Args.Append(na) - call.Args.Append(nh) - call.Args.Append(ir.NewInt(base.Pos, size)) - fn.Body.Append(ir.NewAssignStmt(base.Pos, nh, call)) - - i = next + off += n + case sigFloat32: + hash("f32hash", 4) + case sigFloat64: + hash("f64hash", 8) + case sigString: + hash("strhash", 2*int64(types.PtrSize)) + case sigEface: + hash("nilinterhash", 2*int64(types.PtrSize)) + case sigIface: + hash("interhash", 2*int64(types.PtrSize)) + case sigSkip: + var n int64 + n, sig = parseNum(sig) + off += n + case sigArrayStart: + var n int64 + var elemSig string + n, elemSig, sig = parseArray(sig) + elemSize := sigSize(elemSig) + + // Loop N times, calling hash function for the element. + // for i := off; i < off + N*elemSize; i += elemSize { + // h = elemfn(p+i, h) + // } + elemFn := hashFunc(elemSig).Nname + idx := typecheck.TempAt(pos, ir.CurFunc, types.Types[types.TUINTPTR]) + init := ir.NewAssignStmt(pos, idx, ir.NewInt(pos, off)) + cond := ir.NewBinaryExpr(pos, ir.OLT, idx, ir.NewInt(pos, off+n*elemSize)) + post := ir.NewAssignStmt(pos, idx, ir.NewBinaryExpr(pos, ir.OADD, idx, ir.NewInt(pos, elemSize))) + + p := ir.NewBinaryExpr(pos, ir.OUNSAFEADD, np, idx) + call := typecheck.Call(pos, elemFn, []ir.Node{p, nh}, false) + as := ir.NewAssignStmt(pos, nh, call) + loop := ir.NewForStmt(pos, init, cond, post, []ir.Node{as}, false) + fn.Body.Append(loop) + off += n * elemSize } } - r := ir.NewReturnStmt(base.Pos, nil) - r.Results.Append(nh) - fn.Body.Append(r) + fn.Body.Append(ir.NewReturnStmt(pos, []ir.Node{nh})) if base.Flag.LowerR != 0 { ir.DumpList("genhash body", fn.Body) @@ -244,39 +219,9 @@ func hashFunc(t *types.Type) *ir.Func { }) fn.SetNilCheckDisabled(true) - return fn } -func runtimeHashFor(name string, t *types.Type) *ir.Name { - return typecheck.LookupRuntime(name, t) -} - -// hashfor returns the function to compute the hash of a value of type t. -func hashfor(t *types.Type) *ir.Name { - switch types.AlgType(t) { - case types.AMEM: - base.Fatalf("hashfor with AMEM type") - case types.AINTER: - return runtimeHashFor("interhash", t) - case types.ANILINTER: - return runtimeHashFor("nilinterhash", t) - case types.ASTRING: - return runtimeHashFor("strhash", t) - case types.AFLOAT32: - return runtimeHashFor("f32hash", t) - case types.AFLOAT64: - return runtimeHashFor("f64hash", t) - case types.ACPLX64: - return runtimeHashFor("c64hash", t) - case types.ACPLX128: - return runtimeHashFor("c128hash", t) - } - - fn := hashFunc(t) - return fn.Nname -} - // sysClosure returns a closure which will call the // given runtime function (with no closed-over variables). func sysClosure(name string) *obj.LSym { @@ -292,66 +237,88 @@ func sysClosure(name string) *obj.LSym { // geneq returns a symbol which is the closure used to compute // equality for two objects of type t. func geneq(t *types.Type) *obj.LSym { - switch AlgType(t) { + switch types.AlgType(t) { case types.ANOEQ, types.ANOALG: // The runtime will panic if it tries to compare // a type with a nil equality function. return nil - case types.AMEM0: + } + return geneqSig(eqSignature(t)) +} + +// geneqSig returns a symbol which is the closure used to compute +// equality for two objects with equality signature sig. +func geneqSig(sig string) *obj.LSym { + align := int64(types.PtrSize) + if len(sig) > 0 && sig[0] == sigAlign { + align, sig = parseNum(sig[1:]) + } + if base.Ctxt.Arch.CanMergeLoads { + align = 8 + } + switch sig { + case "": return sysClosure("memequal0") - case types.AMEM8: + case string(sigMemory) + "1": return sysClosure("memequal8") - case types.AMEM16: - return sysClosure("memequal16") - case types.AMEM32: - return sysClosure("memequal32") - case types.AMEM64: - return sysClosure("memequal64") - case types.AMEM128: - return sysClosure("memequal128") - case types.ASTRING: + case string(sigMemory) + "2": + if align >= 2 { + return sysClosure("memequal16") + } + case string(sigMemory) + "4": + if align >= 4 { + return sysClosure("memequal32") + } + case string(sigMemory) + "8": + if align >= 8 { + return sysClosure("memequal64") + } + case string(sigMemory) + "16": + if align >= 8 { + return sysClosure("memequal128") + } + case string(sigString): return sysClosure("strequal") - case types.AINTER: + case string(sigIface): return sysClosure("interequal") - case types.ANILINTER: + case string(sigEface): return sysClosure("nilinterequal") - case types.AFLOAT32: + case string(sigFloat32): return sysClosure("f32equal") - case types.AFLOAT64: + case string(sigFloat64): return sysClosure("f64equal") - case types.ACPLX64: + case string(sigFloat32) + string(sigFloat32): return sysClosure("c64equal") - case types.ACPLX128: + case string(sigFloat64) + string(sigFloat64): return sysClosure("c128equal") - case types.AMEM: - // make equality closure. The size of the type - // is encoded in the closure. - closure := TypeLinksymLookup(fmt.Sprintf(".eqfunc%d", t.Size())) - if len(closure.P) != 0 { - return closure - } - if memequalvarlen == nil { - memequalvarlen = typecheck.LookupRuntimeFunc("memequal_varlen") - } - ot := 0 - ot = objw.SymPtr(closure, ot, memequalvarlen, 0) - ot = objw.Uintptr(closure, ot, uint64(t.Size())) - objw.Global(closure, int32(ot), obj.DUPOK|obj.RODATA) - return closure - case types.ASPECIAL: - break } - closure := TypeLinksymPrefix(".eqfunc", t) + closure := TypeLinksymLookup(".eqfunc." + sig) if len(closure.P) > 0 { // already generated return closure } + if sig[0] == sigMemory { + n, rest := parseNum(sig[1:]) + if rest == "" { + // Just M%d. We can make a memequal_varlen closure. + // The size of the memory region to compare is encoded in the closure. + if memequalvarlen == nil { + memequalvarlen = typecheck.LookupRuntimeFunc("memequal_varlen") + } + ot := 0 + ot = objw.SymPtr(closure, ot, memequalvarlen, 0) + ot = objw.Uintptr(closure, ot, uint64(n)) + objw.Global(closure, int32(ot), obj.DUPOK|obj.RODATA) + return closure + } + } + if base.Flag.LowerR != 0 { - fmt.Printf("geneq %v\n", t) + fmt.Printf("geneqSig %s\n", sig) } - fn := eqFunc(t) + fn := eqFunc(sig) // Generate a closure which points at the function we just generated. objw.SymPtr(closure, 0, fn.Linksym(), 0) @@ -359,9 +326,8 @@ func geneq(t *types.Type) *obj.LSym { return closure } -func eqFunc(t *types.Type) *ir.Func { - // Autogenerate code for equality of structs and arrays. - sym := TypeSymPrefix(".eq", t) +func eqFunc(sig string) *ir.Func { + sym := types.TypeSymLookup(".eq." + sig) if sym.Def != nil { return sym.Def.(*ir.Name).Func } @@ -369,11 +335,11 @@ func eqFunc(t *types.Type) *ir.Func { pos := base.AutogeneratedPos // less confusing than end of input base.Pos = pos - // func sym(p, q *T) bool + // func sym(p, q unsafe.Pointer) bool fn := ir.NewFunc(pos, pos, sym, types.NewSignature(nil, []*types.Field{ - types.NewField(pos, typecheck.Lookup("p"), types.NewPtr(t)), - types.NewField(pos, typecheck.Lookup("q"), types.NewPtr(t)), + types.NewField(pos, typecheck.Lookup("p"), types.Types[types.TUNSAFEPTR]), + types.NewField(pos, typecheck.Lookup("q"), types.Types[types.TUNSAFEPTR]), }, []*types.Field{ types.NewField(pos, typecheck.Lookup("r"), types.Types[types.TBOOL]), @@ -381,7 +347,6 @@ func eqFunc(t *types.Type) *ir.Func { )) sym.Def = fn.Nname fn.Pragma |= ir.Noinline // TODO(mdempsky): We need to emit this during the unified frontend instead, to allow inlining. - typecheck.DeclFunc(fn) np := fn.Dcl[0] nq := fn.Dcl[1] @@ -390,231 +355,208 @@ func eqFunc(t *types.Type) *ir.Func { // Label to jump to if an equality test fails. neq := typecheck.AutoLabel(".neq") - // We reach here only for types that have equality but - // cannot be handled by the standard algorithms, - // so t must be either an array or a struct. - switch t.Kind() { - default: - base.Fatalf("geneq %v", t) - - case types.TARRAY: - nelem := t.NumElem() - - // checkAll generates code to check the equality of all array elements. - // If unroll is greater than nelem, checkAll generates: - // - // if eq(p[0], q[0]) && eq(p[1], q[1]) && ... { - // } else { - // goto neq - // } - // - // And so on. - // - // Otherwise it generates: - // - // iterateTo := nelem/unroll*unroll - // for i := 0; i < iterateTo; i += unroll { - // if eq(p[i+0], q[i+0]) && eq(p[i+1], q[i+1]) && ... && eq(p[i+unroll-1], q[i+unroll-1]) { - // } else { - // goto neq - // } - // } - // if eq(p[iterateTo+0], q[iterateTo+0]) && eq(p[iterateTo+1], q[iterateTo+1]) && ... { - // } else { - // goto neq - // } - // - checkAll := func(unroll int64, last bool, eq func(pi, qi ir.Node) ir.Node) { - // checkIdx generates a node to check for equality at index i. - checkIdx := func(i ir.Node) ir.Node { - // pi := p[i] - pi := ir.NewIndexExpr(base.Pos, np, i) - pi.SetBounded(true) - pi.SetType(t.Elem()) - // qi := q[i] - qi := ir.NewIndexExpr(base.Pos, nq, i) - qi.SetBounded(true) - qi.SetType(t.Elem()) - return eq(pi, qi) - } - - iterations := nelem / unroll - iterateTo := iterations * unroll - // If a loop is iterated only once, there shouldn't be any loop at all. - if iterations == 1 { - iterateTo = 0 - } - - if iterateTo > 0 { - // Generate an unrolled for loop. - // for i := 0; i < nelem/unroll*unroll; i += unroll - i := typecheck.TempAt(base.Pos, ir.CurFunc, types.Types[types.TINT]) - init := ir.NewAssignStmt(base.Pos, i, ir.NewInt(base.Pos, 0)) - cond := ir.NewBinaryExpr(base.Pos, ir.OLT, i, ir.NewInt(base.Pos, iterateTo)) - loop := ir.NewForStmt(base.Pos, nil, cond, nil, nil, false) - loop.PtrInit().Append(init) - - // if eq(p[i+0], q[i+0]) && eq(p[i+1], q[i+1]) && ... && eq(p[i+unroll-1], q[i+unroll-1]) { - // } else { - // goto neq - // } - for j := int64(0); j < unroll; j++ { - // if check {} else { goto neq } - nif := ir.NewIfStmt(base.Pos, checkIdx(i), nil, nil) - nif.Else.Append(ir.NewBranchStmt(base.Pos, ir.OGOTO, neq)) - loop.Body.Append(nif) - post := ir.NewAssignStmt(base.Pos, i, ir.NewBinaryExpr(base.Pos, ir.OADD, i, ir.NewInt(base.Pos, 1))) - loop.Body.Append(post) - } - - fn.Body.Append(loop) - - if nelem == iterateTo { - if last { - fn.Body.Append(ir.NewAssignStmt(base.Pos, nr, ir.NewBool(base.Pos, true))) - } - return - } - } + // Grab known alignment of argument pointers. (ptrSize is the default.) + align := int64(types.PtrSize) + if len(sig) > 0 && sig[0] == sigAlign { + sig = sig[1:] + align, sig = parseNum(sig) + } + unalignedOk := base.Ctxt.Arch.CanMergeLoads + + // offset from np/nq that we're currently working on + var off int64 + var hasCall bool + + // test takes a boolean. If it evaluates to false, short circuit + // and return false immediately. Otherwise, keep checking. + var lastTest ir.Node + test := func(eq ir.Node) { + // Buffer one test in lastTest so we can use the + // last one as the return value. + if lastTest != nil { + nif := ir.NewIfStmt(pos, lastTest, nil, []ir.Node{ir.NewBranchStmt(pos, ir.OGOTO, neq)}) + fn.Body.Append(nif) + } + lastTest = eq + } + // load loads data of type t from np+off and nq+off. + // Increments off by the size of t. + load := func(t *types.Type) (ir.Node, ir.Node) { + c := ir.NewBasicLit(pos, types.Types[types.TUINTPTR], constant.MakeInt64(off)) + p := ir.NewBinaryExpr(pos, ir.OUNSAFEADD, np, c) + q := ir.NewBinaryExpr(pos, ir.OUNSAFEADD, nq, c) + x := ir.NewStarExpr(pos, ir.NewConvExpr(pos, ir.OCONVNOP, t.PtrTo(), p)) + y := ir.NewStarExpr(pos, ir.NewConvExpr(pos, ir.OCONVNOP, t.PtrTo(), q)) + off += t.Size() + return x, y + } + // compare compares x and y and jumps to neq if they are not equal. + compare := func(x, y ir.Node) { + test(ir.NewBinaryExpr(pos, ir.OEQ, x, y)) + } - // Generate remaining checks, if nelem is not a multiple of unroll. - if last { - // Do last comparison in a different manner. - nelem-- - } - // if eq(p[iterateTo+0], q[iterateTo+0]) && eq(p[iterateTo+1], q[iterateTo+1]) && ... { - // } else { - // goto neq - // } - for j := iterateTo; j < nelem; j++ { - // if check {} else { goto neq } - nif := ir.NewIfStmt(base.Pos, checkIdx(ir.NewInt(base.Pos, j)), nil, nil) - nif.Else.Append(ir.NewBranchStmt(base.Pos, ir.OGOTO, neq)) - fn.Body.Append(nif) - } - if last { - fn.Body.Append(ir.NewAssignStmt(base.Pos, nr, checkIdx(ir.NewInt(base.Pos, nelem)))) - } + // We keep track of string contents that we don't compare immediately. + // We delay comparing string contents because they might be large and + // we'd rather compare scalars farther along in the signature first. + var pendingStrings []int64 + flushStrings := func() { + defer func(saveOff int64) { + off = saveOff + }(off) + for _, x := range pendingStrings { + off = x + ptrA, ptrB := load(types.Types[types.TUNSAFEPTR]) + len, _ := load(types.Types[types.TUINTPTR]) + // Note: we already checked that the lengths are equal. + memeq := typecheck.LookupRuntime("memequal") + test(typecheck.Call(pos, memeq, []ir.Node{ptrA, ptrB, len}, false)) + hasCall = true } + pendingStrings = pendingStrings[:0] + } - switch t.Elem().Kind() { - case types.TSTRING: - // Do two loops. First, check that all the lengths match (cheap). - // Second, check that all the contents match (expensive). - checkAll(3, false, func(pi, qi ir.Node) ir.Node { - // Compare lengths. - eqlen, _ := compare.EqString(pi, qi) - return eqlen - }) - checkAll(1, true, func(pi, qi ir.Node) ir.Node { - // Compare contents. - _, eqmem := compare.EqString(pi, qi) - return eqmem - }) - case types.TFLOAT32, types.TFLOAT64: - checkAll(2, true, func(pi, qi ir.Node) ir.Node { - // p[i] == q[i] - return ir.NewBinaryExpr(base.Pos, ir.OEQ, pi, qi) - }) - case types.TSTRUCT: - isCall := func(n ir.Node) bool { - return n.Op() == ir.OCALL || n.Op() == ir.OCALLFUNC + for len(sig) > 0 { + kind := sig[0] + sig = sig[1:] + switch kind { + case sigMemory: + var n int64 + n, sig = parseNum(sig) + if n > 64 { // TODO: why 64? + // For big regions, call memequal. + c := ir.NewBasicLit(pos, types.Types[types.TUINTPTR], constant.MakeInt64(off)) + p := ir.NewBinaryExpr(pos, ir.OUNSAFEADD, np, c) + q := ir.NewBinaryExpr(pos, ir.OUNSAFEADD, nq, c) + len := ir.NewBasicLit(pos, types.Types[types.TUINTPTR], constant.MakeInt64(n)) + memeq := typecheck.LookupRuntime("memequal") + test(typecheck.Call(pos, memeq, []ir.Node{p, q, len}, false)) + hasCall = true + off += n + n = 0 } - var expr ir.Node - var hasCallExprs bool - allCallExprs := true - and := func(cond ir.Node) { - if expr == nil { - expr = cond - } else { - expr = ir.NewLogicalExpr(base.Pos, ir.OANDAND, expr, cond) + n0 := n + for n != 0 { + switch { + case n >= 8 && (unalignedOk || align >= 8 && off%8 == 0): + compare(load(types.Types[types.TUINT64])) + n -= 8 + case (n == 5 || n == 6 || n == 7) && unalignedOk && n0 >= 8: + off -= 8 - n + compare(load(types.Types[types.TUINT64])) + n = 0 + case n >= 4 && (unalignedOk || align >= 4 && off%4 == 0): + compare(load(types.Types[types.TUINT32])) + n -= 4 + case n == 3 && unalignedOk && n0 >= 4: + off-- + compare(load(types.Types[types.TUINT32])) + n = 0 + case n >= 2 && (unalignedOk || align >= 2 && off%2 == 0): + compare(load(types.Types[types.TUINT16])) + n -= 2 + default: + compare(load(types.Types[types.TUINT8])) + n-- } } - - var tmpPos src.XPos - pi := ir.NewIndexExpr(tmpPos, np, ir.NewInt(tmpPos, 0)) - pi.SetBounded(true) - pi.SetType(t.Elem()) - qi := ir.NewIndexExpr(tmpPos, nq, ir.NewInt(tmpPos, 0)) - qi.SetBounded(true) - qi.SetType(t.Elem()) - flatConds, canPanic := compare.EqStruct(t.Elem(), pi, qi) - for _, c := range flatConds { - if isCall(c) { - hasCallExprs = true - } else { - allCallExprs = false - } - } - if !hasCallExprs || allCallExprs || canPanic { - checkAll(1, true, func(pi, qi ir.Node) ir.Node { - // p[i] == q[i] - return ir.NewBinaryExpr(base.Pos, ir.OEQ, pi, qi) - }) + case sigFloat32: + compare(load(types.Types[types.TFLOAT32])) + case sigFloat64: + compare(load(types.Types[types.TFLOAT64])) + case sigString: + // Compare just the lengths right now. + // Save the contents for later. + pendingStrings = append(pendingStrings, off) + off += int64(types.PtrSize) + compare(load(types.Types[types.TUINTPTR])) + case sigEface, sigIface: + // flushStrings here to ensure that we only get a panic from + // this interface test if all previous equality checks pass. + flushStrings() + typeX, typeY := load(types.Types[types.TUINTPTR].PtrTo()) + compare(typeX, typeY) + dataX, dataY := load(types.Types[types.TUNSAFEPTR]) + var eqFn *ir.Name + if kind == sigEface { + eqFn = typecheck.LookupRuntime("efaceeq") } else { - checkAll(4, false, func(pi, qi ir.Node) ir.Node { - expr = nil - flatConds, _ := compare.EqStruct(t.Elem(), pi, qi) - if len(flatConds) == 0 { - return ir.NewBool(base.Pos, true) - } - for _, c := range flatConds { - if !isCall(c) { - and(c) - } - } - return expr - }) - checkAll(2, true, func(pi, qi ir.Node) ir.Node { - expr = nil - flatConds, _ := compare.EqStruct(t.Elem(), pi, qi) - for _, c := range flatConds { - if isCall(c) { - and(c) - } - } - return expr - }) + eqFn = typecheck.LookupRuntime("ifaceeq") } - default: - checkAll(1, true, func(pi, qi ir.Node) ir.Node { - // p[i] == q[i] - return ir.NewBinaryExpr(base.Pos, ir.OEQ, pi, qi) - }) - } - - case types.TSTRUCT: - flatConds, _ := compare.EqStruct(t, np, nq) - if len(flatConds) == 0 { - fn.Body.Append(ir.NewAssignStmt(base.Pos, nr, ir.NewBool(base.Pos, true))) - } else { - for _, c := range flatConds[:len(flatConds)-1] { - // if cond {} else { goto neq } - n := ir.NewIfStmt(base.Pos, c, nil, nil) - n.Else.Append(ir.NewBranchStmt(base.Pos, ir.OGOTO, neq)) - fn.Body.Append(n) + test(typecheck.Call(pos, eqFn, []ir.Node{typeX, dataX, dataY}, false)) + hasCall = true + case sigSkip: + var n int64 + n, sig = parseNum(sig) + off += n + case sigArrayStart: + // Flush any pending test. + flushStrings() + // TODO: if the element comparison can't panic (no E or I), then + // maybe we don't need to do this flushStrings? + // On the other hand, maybe the unflushed string is not equal, but + // a big following array is all equal. + if lastTest != nil { + nif := ir.NewIfStmt(pos, lastTest, nil, []ir.Node{ir.NewBranchStmt(pos, ir.OGOTO, neq)}) + fn.Body.Append(nif) + lastTest = nil } - fn.Body.Append(ir.NewAssignStmt(base.Pos, nr, flatConds[len(flatConds)-1])) + + var n int64 + var elemSig string + n, elemSig, sig = parseArray(sig) + elemSize := sigSize(elemSig) + + // Loop N times, calling comparison function for the element. + // for i := off; i < off + N*elemSize; i += elemSize { + // if !eqfn(p+i, q+i) { goto neq } + // } + elemFn := eqFunc(sigTrimSkip(elemSig)).Nname + idx := typecheck.TempAt(pos, ir.CurFunc, types.Types[types.TUINTPTR]) + init := ir.NewAssignStmt(pos, idx, ir.NewInt(pos, off)) + cond := ir.NewBinaryExpr(pos, ir.OLT, idx, ir.NewInt(pos, off+n*elemSize)) + post := ir.NewAssignStmt(pos, idx, ir.NewBinaryExpr(pos, ir.OADD, idx, ir.NewInt(pos, elemSize))) + + p := ir.NewBinaryExpr(pos, ir.OUNSAFEADD, np, idx) + q := ir.NewBinaryExpr(pos, ir.OUNSAFEADD, nq, idx) + call := typecheck.Call(pos, elemFn, []ir.Node{p, q}, false) + nif := ir.NewIfStmt(pos, call, nil, []ir.Node{ir.NewBranchStmt(pos, ir.OGOTO, neq)}) + loop := ir.NewForStmt(pos, init, cond, post, []ir.Node{nif}, false) + fn.Body.Append(loop) + off += n * elemSize + + // TODO: if the element comparison can't panic, but has strings + // in it, maybe we do a loop first without string contents and a + // second loop with string contents. There is no way to accomplish + // this now they way this code works (to call the equality + // function of the sub-signature). } } + // Flush any pending tests. + // The last test is used directly as a result (instead of branching using it). + flushStrings() + if lastTest == nil { + lastTest = ir.NewBool(pos, true) + } + as := ir.NewAssignStmt(pos, nr, lastTest) + fn.Body.Append(as) // ret: // return ret := typecheck.AutoLabel(".ret") - fn.Body.Append(ir.NewLabelStmt(base.Pos, ret)) - fn.Body.Append(ir.NewReturnStmt(base.Pos, nil)) + fn.Body.Append(ir.NewLabelStmt(pos, ret)) + fn.Body.Append(ir.NewReturnStmt(pos, nil)) // neq: // r = false // return (or goto ret) - fn.Body.Append(ir.NewLabelStmt(base.Pos, neq)) - fn.Body.Append(ir.NewAssignStmt(base.Pos, nr, ir.NewBool(base.Pos, false))) - if compare.EqCanPanic(t) || anyCall(fn) { + fn.Body.Append(ir.NewLabelStmt(pos, neq)) + fn.Body.Append(ir.NewAssignStmt(pos, nr, ir.NewBool(pos, false))) + if hasCall { // Epilogue is large, so share it with the equal case. - fn.Body.Append(ir.NewBranchStmt(base.Pos, ir.OGOTO, ret)) + fn.Body.Append(ir.NewBranchStmt(pos, ir.OGOTO, ret)) } else { // Epilogue is small, so don't bother sharing. - fn.Body.Append(ir.NewReturnStmt(base.Pos, nil)) + fn.Body.Append(ir.NewReturnStmt(pos, nil)) } // TODO(khr): the epilogue size detection condition above isn't perfect. // We should really do a generic CL that shares epilogues across @@ -645,23 +587,311 @@ func eqFunc(t *types.Type) *ir.Func { func EqFor(t *types.Type) (ir.Node, bool) { switch types.AlgType(t) { case types.AMEM: - return typecheck.LookupRuntime("memequal", t, t), true + return typecheck.LookupRuntime("memequal"), true case types.ASPECIAL: - fn := eqFunc(t) + fn := eqFunc(eqSignature(t)) return fn.Nname, false } base.Fatalf("EqFor %v", t) return nil, false } -func anyCall(fn *ir.Func) bool { - return ir.Any(fn, func(n ir.Node) bool { - // TODO(rsc): No methods? - op := n.Op() - return op == ir.OCALL || op == ir.OCALLFUNC - }) +// eqSignature returns a signature of the equality function for type t. +// If two types have the same signature, they can use the same equality function. +// The signature lists the comparisons that the equality function needs +// to make, in order. So for instance, a type like: +// +// type S struct { +// i int32 +// j uint32 +// s string +// e error +// } +// +// Will have the signature "M8SI". +// +// M8 = 8 bytes of regular memory +// S = string +// I = nonempty interface +// +// The content of the signature is not intended for users. It is an +// internal condensation of the comparison operations that need to be +// performed. +// (Although, note that these names might be seen in tracebacks where +// the equality test panics due to incomparable interfaces.) +// +// Full signature spec: +// +// M%d = %d bytes of memory that should be compared directly +// K%d = %d bytes of memory that should not be compared (sKip) +// F = float32 +// G = float64 +// S = string +// I = non-empty interface +// E = empty interface +// [%d%s] = array: repeat signature %s %d times. +// A%d = known alignment of type pointers (defaults to ptrSize) +// +// An alignment directive is only needed on platforms that can't do +// unaligned loads. +// If an alignment directive is present, it must be first. +// Signatures can end early; a K%d is not required at the end. +func eqSignature(t *types.Type) string { + var e eqSigBuilder + if !base.Ctxt.Arch.CanMergeLoads { // alignment only matters if we can't use unaligned loads + if a := t.Alignment(); a != int64(types.PtrSize) { + e.r.WriteString(fmt.Sprintf("%c%d", sigAlign, a)) + } + } + e.build(t) + e.flush(true) + return e.r.String() } -func hashmem(t *types.Type) ir.Node { - return typecheck.LookupRuntime("memhash", t) +const ( + sigMemory = 'M' // followed by an integer number of bytes + sigSkip = 'K' // followed by an integer number of bytes + sigFloat32 = 'F' + sigFloat64 = 'G' + sigString = 'S' + sigIface = 'I' // non-empty interface + sigEface = 'E' // empty interface + sigArrayStart = '[' // followed by an iteration count, element signature, and sigArrayEnd + sigArrayEnd = ']' + sigAlign = 'A' // followed by an integer byte alignment +) + +type eqSigBuilder struct { + r strings.Builder + regMem int64 // queued up region of regular memory + skipMem int64 // queued up region of memory to skip +} + +func (e *eqSigBuilder) flush(atEnd bool) { + if e.regMem > 0 { + e.r.WriteString(fmt.Sprintf("%c%d", sigMemory, e.regMem)) + e.regMem = 0 + } + if e.skipMem > 0 { + if !atEnd { + e.r.WriteString(fmt.Sprintf("%c%d", sigSkip, e.skipMem)) + } + e.skipMem = 0 + } +} +func (e *eqSigBuilder) regular(n int64) { + if e.regMem == 0 { + e.flush(false) + } + e.regMem += n +} +func (e *eqSigBuilder) skip(n int64) { + if e.skipMem == 0 { + e.flush(false) + } + e.skipMem += n +} +func (e *eqSigBuilder) float32() { + e.flush(false) + e.r.WriteByte(sigFloat32) +} +func (e *eqSigBuilder) float64() { + e.flush(false) + e.r.WriteByte(sigFloat64) +} +func (e *eqSigBuilder) string() { + e.flush(false) + e.r.WriteByte(sigString) +} +func (e *eqSigBuilder) eface() { + e.flush(false) + e.r.WriteByte(sigEface) +} +func (e *eqSigBuilder) iface() { + e.flush(false) + e.r.WriteByte(sigIface) +} + +func (e *eqSigBuilder) build(t *types.Type) { + switch t.Kind() { + case types.TINT8, types.TUINT8, types.TBOOL: + e.regular(1) + case types.TINT16, types.TUINT16: + e.regular(2) + case types.TINT32, types.TUINT32: + e.regular(4) + case types.TINT64, types.TUINT64: + e.regular(8) + case types.TINT, types.TUINT, types.TUINTPTR, types.TPTR, types.TUNSAFEPTR, types.TCHAN: + e.regular(int64(types.PtrSize)) + case types.TFLOAT32: + e.float32() + case types.TFLOAT64: + e.float64() + case types.TCOMPLEX64: + e.float32() + e.float32() + case types.TCOMPLEX128: + e.float64() + e.float64() + case types.TSTRING: + e.string() + case types.TINTER: + if t.IsEmptyInterface() { + e.eface() + } else { + e.iface() + } + case types.TSTRUCT: + var off int64 + for _, f := range t.Fields() { + if f.Sym.IsBlank() { + continue + } + if off < f.Offset { + e.skip(f.Offset - off) + } + e.build(f.Type) + off = f.Offset + f.Type.Size() + } + if off < t.Size() { + e.skip(t.Size() - off) + } + case types.TARRAY: + if types.AlgType(t) == types.AMEM { + // TODO: some "regular equality" types don't hit here, + // like [8]sync/atomic.Pointer. Figure out how to + // handle the subtle difference between "AMEM" and + // "can be compared byte-by-byte for equality". + e.regular(t.Size()) + break + } + et := t.Elem() + n := t.NumElem() + switch n { + case 0: + case 1: + e.build(et) + default: + // To keep signatures small, we can't just repeat + // the element signature N times. Instead, we issue + // an array into the signature. Note that this can + // lead to a situation where two types which could + // share an equality function do not, like + // struct { a, b, c, d string } sig: SSSS + // [4]string sig: [4S] + // That's ok, just a tad inefficient. + // + // The generated loops are kind of inefficient as well, + // so unroll the loop a bit. + const unrollSize = 32 // make loop body compare around this many bytes + if et.Size() == 0 { + break // zero-size elements need no comparison + } + unroll := max(1, unrollSize/et.Size()) + // Do partial loops directly. + for n%unroll != 0 { + e.build(et) + n-- + } + if n == 0 { + break + } + // If we only have one loop left, do it directly. + if n == unroll { + for range n { + e.build(et) + } + break + } + e.flush(false) + e.r.WriteString(fmt.Sprintf("%c%d", sigArrayStart, n/unroll)) + for range unroll { + e.build(et) + } + e.flush(false) + e.r.WriteByte(sigArrayEnd) + } + default: + base.Fatalf("eqSigBuilder %v", t) + } +} + +// Parse and remove the number at the start of s. +func parseNum(s string) (int64, string) { + n := 0 + for n < len(s) && s[n] >= '0' && s[n] <= '9' { + n++ + } + x, err := strconv.ParseInt(s[:n], 10, 64) + if err != nil { + base.Fatalf("bad integer: %s", s[:n]) + } + return x, s[n:] +} + +// parseArray parses "%d%s]" from the front of a signature. +// Returns the repeat count (the %d), the element signature +// (the %s), and any remaining signature after the closing ']'. +func parseArray(sig string) (int64, string, string) { + var n int64 + n, sig = parseNum(sig) + // Find matching closing brace. + i := 0 + depth := 1 + for { + if i == len(sig) { + base.Fatalf("mismatched brackets in %s", sig) + } + switch sig[i] { + case sigArrayStart: + depth++ + case sigArrayEnd: + depth-- + if depth == 0 { + return n, sig[:i], sig[i+1:] + } + } + i++ + } +} + +// sigSize returns the size of the type described by the signature. +func sigSize(sig string) int64 { + var size int64 + for len(sig) > 0 { + kind := sig[0] + sig = sig[1:] + switch kind { + case sigMemory, sigSkip: + var n int64 + n, sig = parseNum(sig) + size += n + case sigFloat32: + size += 4 + case sigFloat64: + size += 8 + case sigString, sigIface, sigEface: + size += 2 * int64(types.PtrSize) + case sigArrayStart: + var n int64 + var elemSig string + n, elemSig, sig = parseArray(sig) + size += n * sigSize(elemSig) + } + } + return size +} + +func sigTrimSkip(s string) string { + i := strings.LastIndexByte(s, sigSkip) + if i < 0 { + return s + } + for j := i + 1; j < len(s); j++ { + if s[j] < '0' || s[j] > '9' { + return s + } + } + return s[:i] } diff --git a/src/cmd/compile/internal/reflectdata/map.go b/src/cmd/compile/internal/reflectdata/map.go index 2b43d4af27a250..38eada4522d153 100644 --- a/src/cmd/compile/internal/reflectdata/map.go +++ b/src/cmd/compile/internal/reflectdata/map.go @@ -13,6 +13,7 @@ import ( "cmd/internal/objabi" "cmd/internal/src" "internal/abi" + "internal/buildcfg" ) // MapGroupType makes the map slot group type given the type of the map. @@ -26,14 +27,6 @@ func MapGroupType(t *types.Type) *types.Type { // a correct GC program for it. // // Make sure this stays in sync with internal/runtime/maps/group.go. - // - // type group struct { - // ctrl uint64 - // slots [abi.MapGroupSlots]struct { - // key keyType - // elem elemType - // } - // } keytype := t.Key() elemtype := t.Elem() @@ -46,19 +39,48 @@ func MapGroupType(t *types.Type) *types.Type { elemtype = types.NewPtr(elemtype) } - slotFields := []*types.Field{ - makefield("key", keytype), - makefield("elem", elemtype), - } - slot := types.NewStruct(slotFields) - slot.SetNoalg(true) - - slotArr := types.NewArray(slot, abi.MapGroupSlots) - slotArr.SetNoalg(true) - - fields := []*types.Field{ - makefield("ctrl", types.Types[types.TUINT64]), - makefield("slots", slotArr), + var fields []*types.Field + if buildcfg.Experiment.MapSplitGroup { + // Split layout (KKKKVVVV): + // type group struct { + // ctrl uint64 + // keys [abi.MapGroupSlots]keyType + // elems [abi.MapGroupSlots]elemType + // } + keyArr := types.NewArray(keytype, abi.MapGroupSlots) + keyArr.SetNoalg(true) + + elemArr := types.NewArray(elemtype, abi.MapGroupSlots) + elemArr.SetNoalg(true) + + fields = []*types.Field{ + makefield("ctrl", types.Types[types.TUINT64]), + makefield("keys", keyArr), + makefield("elems", elemArr), + } + } else { + // Interleaved slot layout (KVKVKVKV): + // type group struct { + // ctrl uint64 + // slots [abi.MapGroupSlots]struct { + // key keyType + // elem elemType + // } + // } + slotFields := []*types.Field{ + makefield("key", keytype), + makefield("elem", elemtype), + } + slot := types.NewStruct(slotFields) + slot.SetNoalg(true) + + slotArr := types.NewArray(slot, abi.MapGroupSlots) + slotArr.SetNoalg(true) + + fields = []*types.Field{ + makefield("ctrl", types.Types[types.TUINT64]), + makefield("slots", slotArr), + } } group := types.NewStruct(fields) @@ -269,13 +291,30 @@ func writeMapType(t *types.Type, lsym *obj.LSym, c rttype.Cursor) { s3 := writeType(gtyp) hasher := genhash(t.Key()) - slotTyp := gtyp.Field(1).Type.Elem() - elemOff := slotTyp.Field(1).Offset - if AlgType(t.Key()) == types.AMEM64 && elemOff != 8 { - base.Fatalf("runtime assumes elemOff for 8-byte keys is 8, got %d", elemOff) - } - if AlgType(t.Key()) == types.ASTRING && elemOff != int64(2*types.PtrSize) { - base.Fatalf("runtime assumes elemOff for string keys is %d, got %d", 2*types.PtrSize, elemOff) + var keysOff int64 + var keyStride int64 + var elemsOff int64 + var elemStride int64 + var elemOff int64 + if buildcfg.Experiment.MapSplitGroup { + // Split layout: field 1 is keys array, field 2 is elems array. + keysOff = gtyp.Field(1).Offset + keyStride = gtyp.Field(1).Type.Elem().Size() + elemsOff = gtyp.Field(2).Offset + elemStride = gtyp.Field(2).Type.Elem().Size() + } else { + // Interleaved layout: field 1 is slots array. + // KeysOff = offset of slots array (first key). + // KeyStride = ElemStride = slot stride. + // ElemsOff = offset of slots + offset of elem within slot. + keysOff = gtyp.Field(1).Offset + slotTyp := gtyp.Field(1).Type.Elem() + slotSize := slotTyp.Size() + elemOffInSlot := slotTyp.Field(1).Offset + keyStride = slotSize + elemsOff = keysOff + elemOffInSlot + elemStride = slotSize + elemOff = slotTyp.Field(1).Offset } c.Field("Key").WritePtr(s1) @@ -283,7 +322,10 @@ func writeMapType(t *types.Type, lsym *obj.LSym, c rttype.Cursor) { c.Field("Group").WritePtr(s3) c.Field("Hasher").WritePtr(hasher) c.Field("GroupSize").WriteUintptr(uint64(gtyp.Size())) - c.Field("SlotSize").WriteUintptr(uint64(slotTyp.Size())) + c.Field("KeysOff").WriteUintptr(uint64(keysOff)) + c.Field("KeyStride").WriteUintptr(uint64(keyStride)) + c.Field("ElemsOff").WriteUintptr(uint64(elemsOff)) + c.Field("ElemStride").WriteUintptr(uint64(elemStride)) c.Field("ElemOff").WriteUintptr(uint64(elemOff)) var flags uint32 if needkeyupdate(t.Key()) { @@ -295,7 +337,7 @@ func writeMapType(t *types.Type, lsym *obj.LSym, c rttype.Cursor) { if t.Key().Size() > abi.MapMaxKeyBytes { flags |= abi.MapIndirectKey } - if t.Elem().Size() > abi.MapMaxKeyBytes { + if t.Elem().Size() > abi.MapMaxElemBytes { flags |= abi.MapIndirectElem } c.Field("Flags").WriteUint32(flags) diff --git a/src/cmd/compile/internal/reflectdata/reflect.go b/src/cmd/compile/internal/reflectdata/reflect.go index 38b9391c5f1a57..1fca65469b17b4 100644 --- a/src/cmd/compile/internal/reflectdata/reflect.go +++ b/src/cmd/compile/internal/reflectdata/reflect.go @@ -184,6 +184,7 @@ func dimportpath(p *types.Pkg) { ot := dnameData(s, 0, p.Path, "", nil, false, false) objw.Global(s, int32(ot), obj.DUPOK|obj.RODATA) s.Set(obj.AttrContentAddressable, true) + s.Align = 1 p.Pathsym = s } @@ -308,6 +309,7 @@ func dname(name, tag string, pkg *types.Pkg, exported, embedded bool) *obj.LSym ot := dnameData(s, 0, name, tag, pkg, exported, embedded) objw.Global(s, int32(ot), obj.DUPOK|obj.RODATA) s.Set(obj.AttrContentAddressable, true) + s.Align = 1 return s } @@ -756,6 +758,9 @@ func writeType(t *types.Type) *obj.LSym { // | method list, if any | dextratype // +--------------------------------+ - E + // internal/abi.Type.DescriptorSize is aware of this type layout, + // and must be changed if the layout change. + // UncommonType section is included if we have a name or a method. extra := t.Sym() != nil || len(methods(t)) != 0 @@ -960,6 +965,7 @@ func writeType(t *types.Type) *obj.LSym { keep = false } lsym.Set(obj.AttrMakeTypelink, keep) + lsym.Align = int16(types.PtrSize) return lsym } @@ -1079,6 +1085,7 @@ func writeITab(lsym *obj.LSym, typ, iface *types.Type, allowNonImplement bool) { // Nothing writes static itabs, so they are read only. objw.Global(lsym, int32(rttype.ITab.Size()+delta), int16(obj.DUPOK|obj.RODATA)) lsym.Set(obj.AttrContentAddressable, true) + lsym.Align = int16(types.PtrSize) } func WritePluginTable() { @@ -1274,6 +1281,9 @@ func dgcptrmask(t *types.Type, write bool) *obj.LSym { } objw.Global(lsym, int32(len(ptrmask)), obj.DUPOK|obj.RODATA|obj.LOCAL) lsym.Set(obj.AttrContentAddressable, true) + // The runtime expects ptrmasks to be aligned + // as a uintptr. + lsym.Align = int16(types.PtrSize) } return lsym } @@ -1282,7 +1292,6 @@ func dgcptrmask(t *types.Type, write bool) *obj.LSym { // word offsets in t that hold pointers. // ptrmask is assumed to fit at least types.PtrDataSize(t)/PtrSize bits. func fillptrmask(t *types.Type, ptrmask []byte) { - clear(ptrmask) if !t.HasPointers() { return } @@ -1305,8 +1314,8 @@ func dgcptrmaskOnDemand(t *types.Type, write bool) *obj.LSym { if write && !lsym.OnList() { // Note: contains a pointer, but a pointer to a // persistentalloc allocation. Starts with nil. - objw.Uintptr(lsym, 0, 0) - objw.Global(lsym, int32(types.PtrSize), obj.DUPOK|obj.NOPTR|obj.LOCAL) // TODO:bss? + // Allocated in BSS. + objw.Global(lsym, int32(types.PtrSize), obj.DUPOK|obj.NOPTR|obj.LOCAL) } return lsym } diff --git a/src/cmd/compile/internal/riscv64/ssa.go b/src/cmd/compile/internal/riscv64/ssa.go index 61de983bb02c00..f01f1bbbcf3cbf 100644 --- a/src/cmd/compile/internal/riscv64/ssa.go +++ b/src/cmd/compile/internal/riscv64/ssa.go @@ -294,7 +294,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.OpRISCV64FADDD, ssa.OpRISCV64FSUBD, ssa.OpRISCV64FMULD, ssa.OpRISCV64FDIVD, ssa.OpRISCV64FEQD, ssa.OpRISCV64FNED, ssa.OpRISCV64FLTD, ssa.OpRISCV64FLED, ssa.OpRISCV64FSGNJD, ssa.OpRISCV64MIN, ssa.OpRISCV64MAX, ssa.OpRISCV64MINU, ssa.OpRISCV64MAXU, - ssa.OpRISCV64SH1ADD, ssa.OpRISCV64SH2ADD, ssa.OpRISCV64SH3ADD: + ssa.OpRISCV64SH1ADD, ssa.OpRISCV64SH2ADD, ssa.OpRISCV64SH3ADD, + ssa.OpRISCV64CZEROEQZ, ssa.OpRISCV64CZERONEZ: r := v.Reg() r1 := v.Args[0].Reg() r2 := v.Args[1].Reg() @@ -418,7 +419,9 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.AddRestSource(obj.Addr{Type: obj.TYPE_REG, Reg: r3}) p.To.Type = obj.TYPE_REG p.To.Reg = r - case ssa.OpRISCV64FSQRTS, ssa.OpRISCV64FNEGS, ssa.OpRISCV64FABSD, ssa.OpRISCV64FSQRTD, ssa.OpRISCV64FNEGD, + case ssa.OpRISCV64FSQRTS, ssa.OpRISCV64FSQRTD, + ssa.OpRISCV64FNEGS, ssa.OpRISCV64FNEGD, + ssa.OpRISCV64FABSS, ssa.OpRISCV64FABSD, ssa.OpRISCV64FMVSX, ssa.OpRISCV64FMVXS, ssa.OpRISCV64FMVDX, ssa.OpRISCV64FMVXD, ssa.OpRISCV64FCVTSW, ssa.OpRISCV64FCVTSL, ssa.OpRISCV64FCVTWS, ssa.OpRISCV64FCVTLS, ssa.OpRISCV64FCVTDW, ssa.OpRISCV64FCVTDL, ssa.OpRISCV64FCVTWD, ssa.OpRISCV64FCVTLD, ssa.OpRISCV64FCVTDS, ssa.OpRISCV64FCVTSD, @@ -446,6 +449,14 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.From.Offset = v.AuxInt p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg() + case ssa.OpRISCV64FMOVDconst, ssa.OpRISCV64FMOVFconst: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_FCONST + p.From.Val = v.AuxFloat() + p.From.Name = obj.NAME_NONE + p.From.Reg = obj.REG_NONE + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() case ssa.OpRISCV64MOVaddr: p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_ADDR @@ -504,7 +515,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Reg = v.Reg() case ssa.OpRISCV64CALLstatic, ssa.OpRISCV64CALLclosure, ssa.OpRISCV64CALLinter: s.Call(v) - case ssa.OpRISCV64CALLtail: + case ssa.OpRISCV64CALLtail, ssa.OpRISCV64CALLtailinter: s.TailCall(v) case ssa.OpRISCV64LoweredWB: p := s.Prog(obj.ACALL) @@ -599,13 +610,23 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Sym = ir.Syms.PanicBounds case ssa.OpRISCV64LoweredAtomicLoad8: - s.Prog(riscv.AFENCE) + p1 := s.Prog(riscv.AFENCE) + p1.From.Type = obj.TYPE_SPECIAL + p1.From.Offset = int64(riscv.SPOP_FENCE_RW) + p1.To.Type = obj.TYPE_SPECIAL + p1.To.Offset = int64(riscv.SPOP_FENCE_RW) + p := s.Prog(riscv.AMOVBU) p.From.Type = obj.TYPE_MEM p.From.Reg = v.Args[0].Reg() p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg0() - s.Prog(riscv.AFENCE) + + p2 := s.Prog(riscv.AFENCE) + p2.From.Type = obj.TYPE_SPECIAL + p2.From.Offset = int64(riscv.SPOP_FENCE_R) + p2.To.Type = obj.TYPE_SPECIAL + p2.To.Offset = int64(riscv.SPOP_FENCE_RW) case ssa.OpRISCV64LoweredAtomicLoad32, ssa.OpRISCV64LoweredAtomicLoad64: as := riscv.ALRW @@ -619,13 +640,23 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Reg = v.Reg0() case ssa.OpRISCV64LoweredAtomicStore8: - s.Prog(riscv.AFENCE) + p1 := s.Prog(riscv.AFENCE) + p1.From.Type = obj.TYPE_SPECIAL + p1.From.Offset = int64(riscv.SPOP_FENCE_RW) + p1.To.Type = obj.TYPE_SPECIAL + p1.To.Offset = int64(riscv.SPOP_FENCE_W) + p := s.Prog(riscv.AMOVB) p.From.Type = obj.TYPE_REG p.From.Reg = v.Args[1].Reg() p.To.Type = obj.TYPE_MEM p.To.Reg = v.Args[0].Reg() - s.Prog(riscv.AFENCE) + + p2 := s.Prog(riscv.AFENCE) + p2.From.Type = obj.TYPE_SPECIAL + p2.From.Offset = int64(riscv.SPOP_FENCE_RW) + p2.To.Type = obj.TYPE_SPECIAL + p2.To.Offset = int64(riscv.SPOP_FENCE_RW) case ssa.OpRISCV64LoweredAtomicStore32, ssa.OpRISCV64LoweredAtomicStore64: as := riscv.AAMOSWAPW @@ -741,10 +772,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { case ssa.OpRISCV64LoweredZero: ptr := v.Args[0].Reg() - sc := v.AuxValAndOff() - n := sc.Val64() - - mov, sz := largestMove(sc.Off64()) + n, align := v.AuxSizeAndAlign() + mov, sz := largestMove(align) // mov ZERO, (offset)(Rarg0) var off int64 @@ -766,9 +795,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { case ssa.OpRISCV64LoweredZeroLoop: ptr := v.Args[0].Reg() - sc := v.AuxValAndOff() - n := sc.Val64() - mov, sz := largestMove(sc.Off64()) + n, align := v.AuxSizeAndAlign() + mov, sz := largestMove(align) chunk := 8 * sz if n <= 3*chunk { @@ -777,9 +805,21 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { tmp := v.RegTmp() + if n >= 1<<31 { + p := s.Prog(riscv.AMOV) + p.From.Type = obj.TYPE_CONST + p.From.Offset = n - n%chunk + p.To.Type = obj.TYPE_REG + p.To.Reg = tmp + } p := s.Prog(riscv.AADD) - p.From.Type = obj.TYPE_CONST - p.From.Offset = n - n%chunk + if n >= 1<<31 { + p.From.Type = obj.TYPE_REG + p.From.Reg = tmp + } else { + p.From.Type = obj.TYPE_CONST + p.From.Offset = n - n%chunk + } p.Reg = ptr p.To.Type = obj.TYPE_REG p.To.Reg = tmp @@ -828,9 +868,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { break } - sa := v.AuxValAndOff() - n := sa.Val64() - mov, sz := largestMove(sa.Off64()) + n, align := v.AuxSizeAndAlign() + mov, sz := largestMove(align) var off int64 tmp := int16(riscv.REG_X5) @@ -857,9 +896,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { break } - sc := v.AuxValAndOff() - n := sc.Val64() - mov, sz := largestMove(sc.Off64()) + n, align := v.AuxSizeAndAlign() + mov, sz := largestMove(align) chunk := 8 * sz if n <= 3*chunk { @@ -867,9 +905,21 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { } tmp := int16(riscv.REG_X5) + if n >= 1<<31 { + p := s.Prog(riscv.AMOV) + p.From.Type = obj.TYPE_CONST + p.From.Offset = n - n%chunk + p.To.Type = obj.TYPE_REG + p.To.Reg = riscv.REG_X6 + } p := s.Prog(riscv.AADD) - p.From.Type = obj.TYPE_CONST - p.From.Offset = n - n%chunk + if n >= 1<<31 { + p.From.Type = obj.TYPE_REG + p.From.Reg = riscv.REG_X6 + } else { + p.From.Type = obj.TYPE_CONST + p.From.Offset = n - n%chunk + } p.Reg = src p.To.Type = obj.TYPE_REG p.To.Reg = riscv.REG_X6 @@ -950,8 +1000,12 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Reg = v.Reg() case ssa.OpRISCV64LoweredPubBarrier: - // FENCE - s.Prog(v.Op.Asm()) + // FENCE W, W + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_SPECIAL + p.From.Offset = int64(riscv.SPOP_FENCE_W) + p.To.Type = obj.TYPE_SPECIAL + p.To.Offset = int64(riscv.SPOP_FENCE_W) case ssa.OpRISCV64LoweredRound32F, ssa.OpRISCV64LoweredRound64F: // input is already rounded diff --git a/src/cmd/compile/internal/rttype/rttype.go b/src/cmd/compile/internal/rttype/rttype.go index b8c95339915a52..b3fabedffa6348 100644 --- a/src/cmd/compile/internal/rttype/rttype.go +++ b/src/cmd/compile/internal/rttype/rttype.go @@ -88,6 +88,24 @@ func Init() { if got, want := int64(abi.ITabTypeOff(ptrSize)), ITab.OffsetOf("Type"); got != want { base.Fatalf("abi.ITabTypeOff() == %d, want %d", got, want) } + for _, test := range []struct { + kind abi.Kind + typ *types.Type + name string + }{ + {abi.Struct, StructType, "Struct"}, + {abi.Pointer, PtrType, "Pointer"}, + {abi.Func, FuncType, "Func"}, + {abi.Slice, SliceType, "Slice"}, + {abi.Array, ArrayType, "Array"}, + {abi.Chan, ChanType, "Chan"}, + {abi.Map, MapType, "Map"}, + {abi.Interface, InterfaceType, "Interface"}, + } { + if got, want := int64(abi.RTypeSize(test.kind, ptrSize)), test.typ.Size(); got != want { + base.Fatalf("abi.RTypeSize(%s) == %d, want %d", test.name, got, want) + } + } } // FromReflect translates from a host type to the equivalent target type. diff --git a/src/cmd/compile/internal/s390x/galign.go b/src/cmd/compile/internal/s390x/galign.go index d880834c220d91..1fb371a52c6ac2 100644 --- a/src/cmd/compile/internal/s390x/galign.go +++ b/src/cmd/compile/internal/s390x/galign.go @@ -20,4 +20,6 @@ func Init(arch *ssagen.ArchInfo) { arch.SSAMarkMoves = ssaMarkMoves arch.SSAGenValue = ssaGenValue arch.SSAGenBlock = ssaGenBlock + arch.LoadRegResult = loadRegResult + arch.SpillArgReg = spillArgReg } diff --git a/src/cmd/compile/internal/s390x/ssa.go b/src/cmd/compile/internal/s390x/ssa.go index de00f1ef8ce9ee..f34e02f72eb25c 100644 --- a/src/cmd/compile/internal/s390x/ssa.go +++ b/src/cmd/compile/internal/s390x/ssa.go @@ -10,6 +10,7 @@ import ( "cmd/compile/internal/base" "cmd/compile/internal/ir" "cmd/compile/internal/logopt" + "cmd/compile/internal/objw" "cmd/compile/internal/ssa" "cmd/compile/internal/ssagen" "cmd/compile/internal/types" @@ -130,7 +131,7 @@ func moveByType(t *types.Type) obj.As { return s390x.AMOVD } } - panic("bad load type") + panic("bad move type") } // opregreg emits instructions for @@ -540,6 +541,19 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.From.Type = obj.TYPE_REG p.From.Reg = v.Args[0].Reg() ssagen.AddrAuto(&p.To, v) + case ssa.OpArgIntReg, ssa.OpArgFloatReg: + // The assembler needs to wrap the entry safepoint/stack growth code with spill/unspill + // The loop only runs once. + for _, a := range v.Block.Func.RegArgs { + // Pass the spill/unspill information along to the assembler, offset by size of + // the saved LR slot. + addr := ssagen.SpillSlotAddr(a, s390x.REGSP, base.Ctxt.Arch.FixedFrameSize) + s.FuncInfo().AddSpill( + obj.RegSpill{Reg: a.Reg, Addr: addr, Unspill: loadByType(a.Type), Spill: storeByType(a.Type)}) + } + v.Block.Func.RegArgs = nil + + ssagen.CheckArgReg(v) case ssa.OpS390XLoweredGetClosurePtr: // Closure pointer is R12 (already) ssagen.CheckLoweredGetClosurePtr(v) @@ -566,7 +580,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.To.Reg = v.Reg() case ssa.OpS390XCALLstatic, ssa.OpS390XCALLclosure, ssa.OpS390XCALLinter: s.Call(v) - case ssa.OpS390XCALLtail: + case ssa.OpS390XCALLtail, ssa.OpS390XCALLtailinter: s.TailCall(v) case ssa.OpS390XLoweredWB: p := s.Prog(obj.ACALL) @@ -1029,3 +1043,22 @@ func ssaGenBlock(s *ssagen.State, b, next *ssa.Block) { s.Br(s390x.ABR, succs[1]) } } + +func loadRegResult(s *ssagen.State, f *ssa.Func, t *types.Type, reg int16, n *ir.Name, off int64) *obj.Prog { + p := s.Prog(loadByType(t)) + p.From.Type = obj.TYPE_MEM + p.From.Name = obj.NAME_AUTO + p.From.Sym = n.Linksym() + p.From.Offset = n.FrameOffset() + off + p.To.Type = obj.TYPE_REG + p.To.Reg = reg + return p +} + +func spillArgReg(pp *objw.Progs, p *obj.Prog, f *ssa.Func, t *types.Type, reg int16, n *ir.Name, off int64) *obj.Prog { + p = pp.Append(p, storeByType(t), obj.TYPE_REG, reg, 0, obj.TYPE_MEM, 0, n.FrameOffset()+off) + p.To.Name = obj.NAME_PARAM + p.To.Sym = n.Linksym() + p.Pos = p.Pos.WithNotStmt() + return p +} diff --git a/src/cmd/compile/internal/slice/slice.go b/src/cmd/compile/internal/slice/slice.go new file mode 100644 index 00000000000000..8669b0ed0cc7a4 --- /dev/null +++ b/src/cmd/compile/internal/slice/slice.go @@ -0,0 +1,514 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package slice + +// This file implements a stack-allocation optimization +// for the backing store of slices. +// +// Consider the code: +// +// var s []int +// for i := range ... { +// s = append(s, i) +// } +// return s +// +// Some of the append operations will need to do an allocation +// by calling growslice. This will happen on the 1st, 2nd, 4th, +// 8th, etc. append calls. The allocations done by all but the +// last growslice call will then immediately be garbage. +// +// We'd like to avoid doing some of those intermediate +// allocations if possible. +// +// If we can determine that the "return s" statement is the +// *only* way that the backing store for s escapes, then we +// can rewrite the code to something like: +// +// var s []int +// for i := range N { +// s = append(s, i) +// } +// s = move2heap(s) +// return s +// +// Using the move2heap runtime function, which does: +// +// move2heap(s): +// If s is not backed by a stackframe-allocated +// backing store, return s. Otherwise, copy s +// to the heap and return the copy. +// +// Now we can treat the backing store of s allocated at the +// append site as not escaping. Previous stack allocation +// optimizations now apply, which can use a fixed-size +// stack-allocated backing store for s when appending. +// (See ../ssagen/ssa.go:(*state).append) +// +// It is tricky to do this optimization safely. To describe +// our analysis, we first define what an "exclusive" slice +// variable is. +// +// A slice variable (a variable of slice type) is called +// "exclusive" if, when it has a reference to a +// stackframe-allocated backing store, it is the only +// variable with such a reference. +// +// In other words, a slice variable is exclusive if +// any of the following holds: +// 1) It points to a heap-allocated backing store +// 2) It points to a stack-allocated backing store +// for any parent frame. +// 3) It is the only variable that references its +// backing store. +// 4) It is nil. +// +// The nice thing about exclusive slice variables is that +// it is always safe to do +// s = move2heap(s) +// whenever s is an exclusive slice variable. Because no +// one else has a reference to the backing store, no one +// else can tell that we moved the backing store from one +// location to another. +// +// Note that exclusiveness is a dynamic property. A slice +// variable may be exclusive during some parts of execution +// and not exclusive during others. +// +// The following operations set or preserve the exclusivity +// of a slice variable s: +// s = nil +// s = append(s, ...) +// s = s[i:j] +// ... = s[i] +// s[i] = ... +// f(s) where f does not escape its argument +// Other operations destroy exclusivity. A non-exhaustive list includes: +// x = s +// *p = s +// f(s) where f escapes its argument +// return s +// To err on the safe side, we white list exclusivity-preserving +// operations and we asssume that any other operations that mention s +// destroy its exclusivity. +// +// Our strategy is to move the backing store of s to the heap before +// any exclusive->nonexclusive transition. That way, s will only ever +// have a reference to a stack backing store while it is exclusive. +// +// move2heap for a variable s is implemented with: +// if s points to within the stack frame { +// s2 := make([]T, s.len, s.cap) +// copy(s2[:s.cap], s[:s.cap]) +// s = s2 +// } +// Note that in general we need to copy all of s[:cap(s)] elements when +// moving to the heap. As an optimization, we keep track of slice variables +// whose capacity, and the elements in s[len(s):cap(s)], are never accessed. +// For those slice variables, we can allocate to the next size class above +// the length, which saves memory and copying cost. + +import ( + "cmd/compile/internal/base" + "cmd/compile/internal/escape" + "cmd/compile/internal/ir" + "cmd/compile/internal/reflectdata" +) + +func Funcs(all []*ir.Func) { + if base.Flag.N != 0 { + return + } + for _, fn := range all { + analyze(fn) + } + for _, fn := range all { + if ir.MatchAstDump(fn, "slice") { + ir.AstDump(fn, "slice, "+ir.FuncName(fn)) + } + } +} + +func analyze(fn *ir.Func) { + type sliceInfo struct { + // Slice variable. + s *ir.Name + + // Count of uses that this pass understands. + okUses int32 + // Count of all uses found. + allUses int32 + + // A place where the slice variable transitions from + // exclusive to nonexclusive. + // We could keep track of more than one, but one is enough for now. + // Currently, this can be either a return statement or + // an assignment. + // TODO: other possible transitions? + transition ir.Stmt + + // Each s = append(s, ...) instance we found. + appends []*ir.CallExpr + + // Weight of the number of s = append(s, ...) instances we found. + // The optimizations we do are only really useful if there are at + // least weight 2. (Note: appends in loops have weight >= 2.) + appendWeight int + + // Loop depth at declaration point. + // Use for heuristics only, it is not guaranteed to be correct + // in the presence of gotos. + declDepth int + + // Whether we ever do cap(s), or other operations that use cap(s) + // (possibly implicitly), like s[i:j]. + capUsed bool + } + + // Every variable (*ir.Name) that we are tracking will have + // a non-nil *sliceInfo in its Opt field. + haveLocalSlice := false + maxStackSize := int64(base.Debug.VariableMakeThreshold) + var namedRets []*ir.Name + for _, s := range fn.Dcl { + if !s.Type().IsSlice() { + continue + } + if s.Type().Elem().Size() > maxStackSize { + continue + } + if !base.VariableMakeHash.MatchPos(s.Pos(), nil) { + continue + } + s.Opt = &sliceInfo{s: s} // start tracking s + haveLocalSlice = true + if s.Class == ir.PPARAMOUT { + namedRets = append(namedRets, s) + } + } + if !haveLocalSlice { + return + } + + // Keep track of loop depth while walking. + loopDepth := 0 + + // tracking returns the info for the slice variable if n is a slice + // variable that we're still considering, or nil otherwise. + tracking := func(n ir.Node) *sliceInfo { + if n == nil || n.Op() != ir.ONAME { + return nil + } + s := n.(*ir.Name) + if s.Opt == nil { + return nil + } + return s.Opt.(*sliceInfo) + } + + // addTransition(n, loc) records that s experiences an exclusive->nonexclusive + // transition somewhere within loc. + addTransition := func(i *sliceInfo, loc ir.Stmt) { + if i.transition != nil { + // We only keep track of a single exclusive->nonexclusive transition + // for a slice variable. If we find more than one, give up. + // (More than one transition location would be fine, but we would + // start to get worried about introducing too much additional code.) + i.s.Opt = nil + return + } + if loopDepth > i.declDepth { + // Conservatively, we disable this optimization when the + // transition is inside a loop. This can result in adding + // overhead unnecessarily in cases like: + // func f(n int, p *[]byte) { + // var s []byte + // for i := range n { + // *p = s + // s = append(s, 0) + // } + // } + i.s.Opt = nil + return + } + i.transition = loc + } + + // Examine an x = y assignment that occurs somewhere within statement stmt. + assign := func(x, y ir.Node, stmt ir.Stmt) { + if i := tracking(x); i != nil { + // s = y. Check for understood patterns for y. + if y == nil || y.Op() == ir.ONIL { + // s = nil is ok. + i.okUses++ + } else if y.Op() == ir.OSLICELIT { + // s = []{...} is ok. + // Note: this reveals capacity. Should it? + i.okUses++ + i.capUsed = true + } else if y.Op() == ir.OSLICE { + y := y.(*ir.SliceExpr) + if y.X == i.s { + // s = s[...:...] is ok + i.okUses += 2 + i.capUsed = true + } + } else if y.Op() == ir.OAPPEND { + y := y.(*ir.CallExpr) + if y.Args[0] == i.s { + // s = append(s, ...) is ok + i.okUses += 2 + i.appends = append(i.appends, y) + i.appendWeight += 1 + (loopDepth - i.declDepth) + } + // TODO: s = append(nil, ...)? + } + // Note that technically s = make([]T, ...) preserves exclusivity, but + // we don't track that because we assume users who wrote that know + // better than the compiler does. + + // TODO: figure out how to handle s = fn(..., s, ...) + // It would be nice to maintain exclusivity of s in this situation. + // But unfortunately, fn can return one of its other arguments, which + // may be a slice with a stack-allocated backing store other than s. + // (which may have preexisting references to its backing store). + // + // Maybe we could do it if s is the only argument? + } + + if i := tracking(y); i != nil { + // ... = s + // Treat this as an exclusive->nonexclusive transition. + i.okUses++ + addTransition(i, stmt) + } + } + + // do walks n and everything below it, recording what happens to the + // slice variables we are tracking. It counts every mention of such a + // variable in allUses, and the subset of those mentions that this pass + // understands to preserve exclusivity in okUses. A variable whose two + // counts end up equal is only ever used in ways we understand; any + // other variable is dropped at the end of the analysis. Uses that + // definitely destroy exclusivity, like &s[i], stop the tracking right + // away by clearing s.Opt, which makes tracking report the variable as + // no longer being considered. + // + // It is always used as an ir.DoChildren visitor and always returns + // false, so that the whole function body is walked. + var do func(ir.Node) bool + do = func(n ir.Node) bool { + if n == nil { + return false + } + switch n.Op() { + case ir.ONAME: + if i := tracking(n); i != nil { + // A use of a slice variable. Count it. + i.allUses++ + } + case ir.ODCL: + n := n.(*ir.Decl) + if i := tracking(n.X); i != nil { + i.okUses++ + i.declDepth = loopDepth + } + case ir.OINDEX: + n := n.(*ir.IndexExpr) + if i := tracking(n.X); i != nil { + // s[i] is ok. + i.okUses++ + } + case ir.OLEN: + n := n.(*ir.UnaryExpr) + if i := tracking(n.X); i != nil { + // len(s) is ok + i.okUses++ + } + case ir.OCAP: + n := n.(*ir.UnaryExpr) + if i := tracking(n.X); i != nil { + // cap(s) is ok + i.okUses++ + i.capUsed = true + } + case ir.OADDR: + n := n.(*ir.AddrExpr) + // Walk down to the object whose interior we're taking the + // address of. Field selectors and array indexes don't leave + // that object, so &s[i], &s[i].f, and &s[i].f[j] all end up + // pointing into s's backing store. + // (We need this because s[i] is ok, but &s[i] is not.) + x := n.X + for x != nil { + switch x.Op() { + case ir.ODOT: + // &x.f points into x. + x = x.(*ir.SelectorExpr).X + continue + case ir.OINDEX: + idx := x.(*ir.IndexExpr) + if idx.X.Type().IsArray() { + // &a[i] points into a. + // Note: for a pointer to an array, or for a + // slice, the address points into a different + // object instead, so we stop here. + x = idx.X + continue + } + if i := tracking(idx.X); i != nil { + // &s[i] is definitely a nonexclusive transition. + i.s.Opt = nil + } + } + break + } + case ir.ORETURN: + n := n.(*ir.ReturnStmt) + for _, x := range n.Results { + if i := tracking(x); i != nil { + i.okUses++ + // We go exclusive->nonexclusive here + addTransition(i, n) + } + } + if len(n.Results) == 0 { + // Uses of named result variables are implicit here. + for _, x := range namedRets { + if i := tracking(x); i != nil { + addTransition(i, n) + } + } + } + case ir.OCALLFUNC: + n := n.(*ir.CallExpr) + for idx, arg := range n.Args { + if i := tracking(arg); i != nil { + if !argLeak(n, idx) { + // Passing s to a nonescaping arg is ok. + i.okUses++ + i.capUsed = true + } + } + } + case ir.ORANGE: + n := n.(*ir.RangeStmt) + if i := tracking(n.X); i != nil { + i.okUses++ + // Range over slice keeps a pointer to the backing store, see #79909. + addTransition(i, n) + } + case ir.OAS: + n := n.(*ir.AssignStmt) + assign(n.X, n.Y, n) + case ir.OAS2: + n := n.(*ir.AssignListStmt) + for i := range len(n.Lhs) { + assign(n.Lhs[i], n.Rhs[i], n) + } + case ir.OCLOSURE: + n := n.(*ir.ClosureExpr) + for _, v := range n.Func.ClosureVars { + do(v.Outer) + } + } + if n.Op() == ir.OFOR || n.Op() == ir.ORANGE { + // Note: loopDepth isn't really right for init portion + // of the for statement, but that's ok. Correctness + // does not depend on depth info. + loopDepth++ + defer func() { loopDepth-- }() + } + // Check all the children. + ir.DoChildren(n, do) + return false + } + + // Run the analysis over the whole body. + for _, stmt := range fn.Body { + do(stmt) + } + + // Process accumulated info to find slice variables + // that we can allocate on the stack. + for _, s := range fn.Dcl { + if s.Opt == nil { + continue + } + i := s.Opt.(*sliceInfo) + s.Opt = nil + if i.okUses != i.allUses { + // Some use of i.s that don't understand lurks. Give up. + continue + } + + // At this point, we've decided that we *can* do + // the optimization. + + if i.transition == nil { + // Exclusive for its whole lifetime. That means it + // didn't escape. We can already handle nonescaping + // slices without this pass. + continue + } + if i.appendWeight < 2 { + // This optimization only really helps if there is + // (dynamically) more than one append. + continue + } + + // Commit point - at this point we've decided we *should* + // do the optimization. + + // Insert a move2heap operation before the exclusive->nonexclusive + // transition. + move := ir.NewMoveToHeapExpr(i.transition.Pos(), i.s) + if i.capUsed { + move.PreserveCapacity = true + } + move.RType = reflectdata.AppendElemRType(i.transition.Pos(), i.appends[0]) + move.SetType(i.s.Type()) + move.SetTypecheck(1) + as := ir.NewAssignStmt(i.transition.Pos(), i.s, move) + as.SetTypecheck(1) + i.transition.PtrInit().Prepend(as) + // Note: we prepend because we need to put the move2heap + // operation first, before any other init work, as the transition + // might occur in the init work. + + // Now that we've inserted a move2heap operation before every + // exclusive -> nonexclusive transition, appends can now use + // stack backing stores. + // (This is the whole point of this pass, to enable stack + // allocation of append backing stores.) + for _, a := range i.appends { + a.SetEsc(ir.EscNone) + if i.capUsed { + a.UseBuf = true + } + } + } +} + +// argLeak reports if the idx'th argument to the call n escapes anywhere +// (to the heap, another argument, return value, etc.) +// If unknown returns true. +func argLeak(n *ir.CallExpr, idx int) bool { + if n.Op() != ir.OCALLFUNC { + return true + } + fn := ir.StaticCalleeName(ir.StaticValue(n.Fun)) + if fn == nil { + return true + } + fntype := fn.Type() + if recv := fntype.Recv(); recv != nil { + if idx == 0 { + return escape.ParseLeaks(recv.Note).Any() + } + idx-- + } + return escape.ParseLeaks(fntype.Params()[idx].Note).Any() +} diff --git a/src/cmd/compile/internal/ssa/_gen/386.rules b/src/cmd/compile/internal/ssa/_gen/386.rules index 5f1150241929eb..b7134e7cefd229 100644 --- a/src/cmd/compile/internal/ssa/_gen/386.rules +++ b/src/cmd/compile/internal/ssa/_gen/386.rules @@ -7,6 +7,7 @@ (Add(32|64)F ...) => (ADDS(S|D) ...) (Add32carry ...) => (ADDLcarry ...) (Add32withcarry ...) => (ADCL ...) +(Add32carrywithcarry ...) => (ADCLcarry ...) (Sub(Ptr|32|16|8) ...) => (SUBL ...) (Sub(32|64)F ...) => (SUBS(S|D) ...) @@ -325,6 +326,7 @@ (ClosureCall ...) => (CALLclosure ...) (InterCall ...) => (CALLinter ...) (TailCall ...) => (CALLtail ...) +(TailCallInter ...) => (CALLtailinter ...) // Miscellaneous (IsNonNil p) => (SETNE (TESTL p p)) diff --git a/src/cmd/compile/internal/ssa/_gen/386Ops.go b/src/cmd/compile/internal/ssa/_gen/386Ops.go index 60599a33abb587..791f93d21470e4 100644 --- a/src/cmd/compile/internal/ssa/_gen/386Ops.go +++ b/src/cmd/compile/internal/ssa/_gen/386Ops.go @@ -59,10 +59,10 @@ func init() { num[name] = i } buildReg := func(s string) regMask { - m := regMask(0) + m := regMask{} for _, r := range strings.Split(s, " ") { if n, ok := num[r]; ok { - m |= regMask(1) << uint(n) + m = m.addReg(uint(n)) continue } panic("register " + r + " not found") @@ -78,9 +78,9 @@ func init() { bx = buildReg("BX") gp = buildReg("AX CX DX BX BP SI DI") fp = buildReg("X0 X1 X2 X3 X4 X5 X6 X7") - gpsp = gp | buildReg("SP") - gpspsb = gpsp | buildReg("SB") - callerSave = gp | fp + gpsp = gp.union(buildReg("SP")) + gpspsb = gpsp.union(buildReg("SB")) + callerSave = gp.union(fp) ) // Common slices of register masks var ( @@ -90,121 +90,123 @@ func init() { // Common regInfo var ( - gp01 = regInfo{inputs: nil, outputs: gponly} - gp11 = regInfo{inputs: []regMask{gp}, outputs: gponly} - gp11sp = regInfo{inputs: []regMask{gpsp}, outputs: gponly} - gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: gponly} - gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly} - gp11carry = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp, 0}} - gp21carry = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp, 0}} - gp1carry1 = regInfo{inputs: []regMask{gp}, outputs: gponly} - gp2carry1 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly} - gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly} - gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly} - gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}} - gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax}, clobbers: dx} - gp21hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx}, clobbers: ax} - gp11mod = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{dx}, clobbers: ax} - gp21mul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx, ax}} + gp01 = regInfo{inputs: nil, outputs: gponly} + gp11 = regInfo{inputs: []regMask{gp}, outputs: gponly} + gp11sp = regInfo{inputs: []regMask{gpsp}, outputs: gponly} + gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: gponly} + gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly} + gp11carry = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp, regMask{}}} + gp21carry = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp, regMask{}}} + gp1carry1 = regInfo{inputs: []regMask{gp}, outputs: gponly} + gp2carry1 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly} + gp2carry1carry = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp, regMask{}}} + gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly} + gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly} + gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}} + gp11div = regInfo{inputs: []regMask{ax, gpsp.minus(dx)}, outputs: []regMask{ax}, clobbers: dx} + gp21hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx}, clobbers: ax} + gp11mod = regInfo{inputs: []regMask{ax, gpsp.minus(dx)}, outputs: []regMask{dx}, clobbers: ax} + gp21mul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx, ax}} gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}} gp1flags = regInfo{inputs: []regMask{gpsp}} - gp0flagsLoad = regInfo{inputs: []regMask{gpspsb, 0}} - gp1flagsLoad = regInfo{inputs: []regMask{gpspsb, gpsp, 0}} + gp0flagsLoad = regInfo{inputs: []regMask{gpspsb, regMask{}}} + gp1flagsLoad = regInfo{inputs: []regMask{gpspsb, gpsp, regMask{}}} flagsgp = regInfo{inputs: nil, outputs: gponly} readflags = regInfo{inputs: nil, outputs: gponly} - flagsgpax = regInfo{inputs: nil, clobbers: ax, outputs: []regMask{gp &^ ax}} + flagsgpax = regInfo{inputs: nil, clobbers: ax, outputs: []regMask{gp.minus(ax)}} - gpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: gponly} - gp21load = regInfo{inputs: []regMask{gp, gpspsb, 0}, outputs: gponly} - gploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: gponly} - gp21loadidx = regInfo{inputs: []regMask{gp, gpspsb, gpsp, 0}, outputs: gponly} + gpload = regInfo{inputs: []regMask{gpspsb, regMask{}}, outputs: gponly} + gp21load = regInfo{inputs: []regMask{gp, gpspsb, regMask{}}, outputs: gponly} + gploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, regMask{}}, outputs: gponly} + gp21loadidx = regInfo{inputs: []regMask{gp, gpspsb, gpsp, regMask{}}, outputs: gponly} - gpstore = regInfo{inputs: []regMask{gpspsb, gpsp, 0}} - gpstoreconst = regInfo{inputs: []regMask{gpspsb, 0}} - gpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, gpsp, 0}} - gpstoreconstidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}} + gpstore = regInfo{inputs: []regMask{gpspsb, gpsp, regMask{}}} + gpstoreconst = regInfo{inputs: []regMask{gpspsb, regMask{}}} + gpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, gpsp, regMask{}}} + gpstoreconstidx = regInfo{inputs: []regMask{gpspsb, gpsp, regMask{}}} fp01 = regInfo{inputs: nil, outputs: fponly} fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly} - fp21load = regInfo{inputs: []regMask{fp, gpspsb, 0}, outputs: fponly} + fp21load = regInfo{inputs: []regMask{fp, gpspsb, regMask{}}, outputs: fponly} fpgp = regInfo{inputs: fponly, outputs: gponly} gpfp = regInfo{inputs: gponly, outputs: fponly} fp11 = regInfo{inputs: fponly, outputs: fponly} fp2flags = regInfo{inputs: []regMask{fp, fp}} - fpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: fponly} - fploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: fponly} + fpload = regInfo{inputs: []regMask{gpspsb, regMask{}}, outputs: fponly} + fploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, regMask{}}, outputs: fponly} - fpstore = regInfo{inputs: []regMask{gpspsb, fp, 0}} - fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, 0}} + fpstore = regInfo{inputs: []regMask{gpspsb, fp, regMask{}}} + fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, regMask{}}} ) var _386ops = []opData{ // fp ops - {name: "ADDSS", argLength: 2, reg: fp21, asm: "ADDSS", commutative: true, resultInArg0: true}, // fp32 add - {name: "ADDSD", argLength: 2, reg: fp21, asm: "ADDSD", commutative: true, resultInArg0: true}, // fp64 add - {name: "SUBSS", argLength: 2, reg: fp21, asm: "SUBSS", resultInArg0: true}, // fp32 sub - {name: "SUBSD", argLength: 2, reg: fp21, asm: "SUBSD", resultInArg0: true}, // fp64 sub - {name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true}, // fp32 mul - {name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true}, // fp64 mul - {name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true}, // fp32 div - {name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true}, // fp64 div - - {name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // fp32 load - {name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // fp64 load - {name: "MOVSSconst", reg: fp01, asm: "MOVSS", aux: "Float32", rematerializeable: true}, // fp32 constant - {name: "MOVSDconst", reg: fp01, asm: "MOVSD", aux: "Float64", rematerializeable: true}, // fp64 constant - {name: "MOVSSloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSS", aux: "SymOff", symEffect: "Read"}, // fp32 load indexed by i - {name: "MOVSSloadidx4", argLength: 3, reg: fploadidx, asm: "MOVSS", aux: "SymOff", symEffect: "Read"}, // fp32 load indexed by 4*i - {name: "MOVSDloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSD", aux: "SymOff", symEffect: "Read"}, // fp64 load indexed by i - {name: "MOVSDloadidx8", argLength: 3, reg: fploadidx, asm: "MOVSD", aux: "SymOff", symEffect: "Read"}, // fp64 load indexed by 8*i - - {name: "MOVSSstore", argLength: 3, reg: fpstore, asm: "MOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // fp32 store - {name: "MOVSDstore", argLength: 3, reg: fpstore, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // fp64 store - {name: "MOVSSstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSS", aux: "SymOff", symEffect: "Write"}, // fp32 indexed by i store - {name: "MOVSSstoreidx4", argLength: 4, reg: fpstoreidx, asm: "MOVSS", aux: "SymOff", symEffect: "Write"}, // fp32 indexed by 4i store - {name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"}, // fp64 indexed by i store - {name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"}, // fp64 indexed by 8i store - - {name: "ADDSSload", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "ADDSDload", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "SUBSSload", argLength: 3, reg: fp21load, asm: "SUBSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "SUBSDload", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "MULSSload", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "MULSDload", argLength: 3, reg: fp21load, asm: "MULSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "DIVSSload", argLength: 3, reg: fp21load, asm: "DIVSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 / tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "DIVSDload", argLength: 3, reg: fp21load, asm: "DIVSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 / tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "ADDSS", argLength: 2, reg: fp21, asm: "ADDSS", commutative: true, resultInArg0: true, earlyOk: true}, // fp32 add + {name: "ADDSD", argLength: 2, reg: fp21, asm: "ADDSD", commutative: true, resultInArg0: true, earlyOk: true}, // fp64 add + {name: "SUBSS", argLength: 2, reg: fp21, asm: "SUBSS", resultInArg0: true, earlyOk: true}, // fp32 sub + {name: "SUBSD", argLength: 2, reg: fp21, asm: "SUBSD", resultInArg0: true, earlyOk: true}, // fp64 sub + {name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true, earlyOk: true}, // fp32 mul + {name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true, earlyOk: true}, // fp64 mul + {name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true, earlyOk: true}, // fp32 div + {name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true, earlyOk: true}, // fp64 div + + {name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // fp32 load + {name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // fp64 load + {name: "MOVSSconst", reg: fp01, asm: "MOVSS", aux: "Float32", rematerializeable: true, earlyOk: true}, // fp32 constant + {name: "MOVSDconst", reg: fp01, asm: "MOVSD", aux: "Float64", rematerializeable: true, earlyOk: true}, // fp64 constant + {name: "MOVSSloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSS", aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, // fp32 load indexed by i + {name: "MOVSSloadidx4", argLength: 3, reg: fploadidx, asm: "MOVSS", aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, // fp32 load indexed by 4*i + {name: "MOVSDloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSD", aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, // fp64 load indexed by i + {name: "MOVSDloadidx8", argLength: 3, reg: fploadidx, asm: "MOVSD", aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, // fp64 load indexed by 8*i + + {name: "MOVSSstore", argLength: 3, reg: fpstore, asm: "MOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // fp32 store + {name: "MOVSDstore", argLength: 3, reg: fpstore, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // fp64 store + {name: "MOVSSstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSS", aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // fp32 indexed by i store + {name: "MOVSSstoreidx4", argLength: 4, reg: fpstoreidx, asm: "MOVSS", aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // fp32 indexed by 4i store + {name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // fp64 indexed by i store + {name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // fp64 indexed by 8i store + + {name: "ADDSSload", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "ADDSDload", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // fp64 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "SUBSSload", argLength: 3, reg: fp21load, asm: "SUBSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // fp32 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "SUBSDload", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // fp64 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "MULSSload", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // fp32 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "MULSDload", argLength: 3, reg: fp21load, asm: "MULSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // fp64 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "DIVSSload", argLength: 3, reg: fp21load, asm: "DIVSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // fp32 arg0 / tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "DIVSDload", argLength: 3, reg: fp21load, asm: "DIVSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // fp64 arg0 / tmp, tmp loaded from arg1+auxint+aux, arg2 = mem // binary ops - {name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true, clobberFlags: true}, // arg0 + arg1 - {name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", typ: "UInt32", clobberFlags: true}, // arg0 + auxint + {name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true, clobberFlags: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", typ: "UInt32", clobberFlags: true, earlyOk: true}, // arg0 + auxint - {name: "ADDLcarry", argLength: 2, reg: gp21carry, asm: "ADDL", commutative: true, resultInArg0: true}, // arg0 + arg1, generates pair - {name: "ADDLconstcarry", argLength: 1, reg: gp11carry, asm: "ADDL", aux: "Int32", resultInArg0: true}, // arg0 + auxint, generates pair - {name: "ADCL", argLength: 3, reg: gp2carry1, asm: "ADCL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0+arg1+carry(arg2), where arg2 is flags - {name: "ADCLconst", argLength: 2, reg: gp1carry1, asm: "ADCL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0+auxint+carry(arg1), where arg1 is flags + {name: "ADDLcarry", argLength: 2, reg: gp21carry, asm: "ADDL", commutative: true, resultInArg0: true, earlyOk: true}, // arg0 + arg1, generates pair + {name: "ADDLconstcarry", argLength: 1, reg: gp11carry, asm: "ADDL", aux: "Int32", resultInArg0: true}, // arg0 + auxint, generates pair + {name: "ADCL", argLength: 3, reg: gp2carry1, asm: "ADCL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0+arg1+carry(arg2), where arg2 is flags + {name: "ADCLcarry", argLength: 3, reg: gp2carry1carry, asm: "ADCL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0+arg1+carry(arg2), where arg2 is flags, generates pair + {name: "ADCLconst", argLength: 2, reg: gp1carry1, asm: "ADCL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0+auxint+carry(arg1), where arg1 is flags - {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true, clobberFlags: true}, // arg0 - arg1 - {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 - auxint + {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 - arg1 + {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 - auxint {name: "SUBLcarry", argLength: 2, reg: gp21carry, asm: "SUBL", resultInArg0: true}, // arg0-arg1, generates pair {name: "SUBLconstcarry", argLength: 1, reg: gp11carry, asm: "SUBL", aux: "Int32", resultInArg0: true}, // arg0-auxint, generates pair {name: "SBBL", argLength: 3, reg: gp2carry1, asm: "SBBL", resultInArg0: true, clobberFlags: true}, // arg0-arg1-borrow(arg2), where arg2 is flags {name: "SBBLconst", argLength: 2, reg: gp1carry1, asm: "SBBL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0-auxint-borrow(arg1), where arg1 is flags - {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 * arg1 - {name: "MULLconst", argLength: 1, reg: gp11, asm: "IMUL3L", aux: "Int32", clobberFlags: true}, // arg0 * auxint + {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 * arg1 + {name: "MULLconst", argLength: 1, reg: gp11, asm: "IMUL3L", aux: "Int32", clobberFlags: true, earlyOk: true}, // arg0 * auxint - {name: "MULLU", argLength: 2, reg: regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{ax, 0}, clobbers: dx}, typ: "(UInt32,Flags)", asm: "MULL", commutative: true, clobberFlags: true}, // Let x = arg0*arg1 (full 32x32->64 unsigned multiply). Returns uint32(x), and flags set to overflow if uint32(x) != x. + {name: "MULLU", argLength: 2, reg: regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{ax, regMask{}}, clobbers: dx}, typ: "(UInt32,Flags)", asm: "MULL", commutative: true, clobberFlags: true, earlyOk: true}, // Let x = arg0*arg1 (full 32x32->64 unsigned multiply). Returns uint32(x), and flags set to overflow if uint32(x) != x. - {name: "HMULL", argLength: 2, reg: gp21hmul, commutative: true, asm: "IMULL", clobberFlags: true}, // (arg0 * arg1) >> width - {name: "HMULLU", argLength: 2, reg: gp21hmul, commutative: true, asm: "MULL", clobberFlags: true}, // (arg0 * arg1) >> width + {name: "HMULL", argLength: 2, reg: gp21hmul, commutative: true, asm: "IMULL", clobberFlags: true, earlyOk: true}, // (arg0 * arg1) >> width + {name: "HMULLU", argLength: 2, reg: gp21hmul, commutative: true, asm: "MULL", clobberFlags: true, earlyOk: true}, // (arg0 * arg1) >> width - {name: "MULLQU", argLength: 2, reg: gp21mul, commutative: true, asm: "MULL", clobberFlags: true}, // arg0 * arg1, high 32 in result[0], low 32 in result[1] + {name: "MULLQU", argLength: 2, reg: gp21mul, commutative: true, asm: "MULL", clobberFlags: true, earlyOk: true}, // arg0 * arg1, high 32 in result[0], low 32 in result[1] - {name: "AVGLU", argLength: 2, reg: gp21, commutative: true, resultInArg0: true, clobberFlags: true}, // (arg0 + arg1) / 2 as unsigned, all 32 result bits + {name: "AVGLU", argLength: 2, reg: gp21, commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // (arg0 + arg1) / 2 as unsigned, all 32 result bits // For DIVL, DIVW, MODL and MODW, AuxInt non-zero means that the divisor has been proved to be not -1. {name: "DIVL", argLength: 2, reg: gp11div, asm: "IDIVL", aux: "Bool", clobberFlags: true}, // arg0 / arg1 @@ -217,14 +219,14 @@ func init() { {name: "MODLU", argLength: 2, reg: gp11mod, asm: "DIVL", clobberFlags: true}, // arg0 % arg1 {name: "MODWU", argLength: 2, reg: gp11mod, asm: "DIVW", clobberFlags: true}, // arg0 % arg1 - {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 & arg1 - {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 & auxint + {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 & auxint - {name: "ORL", argLength: 2, reg: gp21, asm: "ORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 | arg1 - {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 | auxint + {name: "ORL", argLength: 2, reg: gp21, asm: "ORL", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 | arg1 + {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 | auxint - {name: "XORL", argLength: 2, reg: gp21, asm: "XORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 ^ arg1 - {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint + {name: "XORL", argLength: 2, reg: gp21, asm: "XORL", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 ^ arg1 + {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 ^ auxint {name: "CMPL", argLength: 2, reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1 {name: "CMPW", argLength: 2, reg: gp2flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to arg1 @@ -234,17 +236,17 @@ func init() { {name: "CMPBconst", argLength: 1, reg: gp1flags, asm: "CMPB", typ: "Flags", aux: "Int8"}, // arg0 compare to auxint // compare *(arg0+auxint+aux) to arg1 (in that order). arg2=mem. - {name: "CMPLload", argLength: 3, reg: gp1flagsLoad, asm: "CMPL", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, - {name: "CMPWload", argLength: 3, reg: gp1flagsLoad, asm: "CMPW", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, - {name: "CMPBload", argLength: 3, reg: gp1flagsLoad, asm: "CMPB", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, + {name: "CMPLload", argLength: 3, reg: gp1flagsLoad, asm: "CMPL", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, + {name: "CMPWload", argLength: 3, reg: gp1flagsLoad, asm: "CMPW", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, + {name: "CMPBload", argLength: 3, reg: gp1flagsLoad, asm: "CMPB", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, // compare *(arg0+ValAndOff(AuxInt).Off()+aux) to ValAndOff(AuxInt).Val() (in that order). arg1=mem. - {name: "CMPLconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPL", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, - {name: "CMPWconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPW", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, - {name: "CMPBconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPB", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, + {name: "CMPLconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPL", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, + {name: "CMPWconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPW", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, + {name: "CMPBconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPB", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, - {name: "UCOMISS", argLength: 2, reg: fp2flags, asm: "UCOMISS", typ: "Flags"}, // arg0 compare to arg1, f32 - {name: "UCOMISD", argLength: 2, reg: fp2flags, asm: "UCOMISD", typ: "Flags"}, // arg0 compare to arg1, f64 + {name: "UCOMISS", argLength: 2, reg: fp2flags, asm: "UCOMISS", typ: "Flags", earlyOk: true}, // arg0 compare to arg1, f32 + {name: "UCOMISD", argLength: 2, reg: fp2flags, asm: "UCOMISD", typ: "Flags", earlyOk: true}, // arg0 compare to arg1, f64 {name: "TESTL", argLength: 2, reg: gp2flags, commutative: true, asm: "TESTL", typ: "Flags"}, // (arg0 & arg1) compare to 0 {name: "TESTW", argLength: 2, reg: gp2flags, commutative: true, asm: "TESTW", typ: "Flags"}, // (arg0 & arg1) compare to 0 @@ -253,175 +255,175 @@ func init() { {name: "TESTWconst", argLength: 1, reg: gp1flags, asm: "TESTW", typ: "Flags", aux: "Int16"}, // (arg0 & auxint) compare to 0 {name: "TESTBconst", argLength: 1, reg: gp1flags, asm: "TESTB", typ: "Flags", aux: "Int8"}, // (arg0 & auxint) compare to 0 - {name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL", resultInArg0: true, clobberFlags: true}, // arg0 << arg1, shift amount is mod 32 - {name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 << auxint, shift amount 0-31 + {name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 << arg1, shift amount is mod 32 + {name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 << auxint, shift amount 0-31 // Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount! - {name: "SHRL", argLength: 2, reg: gp21shift, asm: "SHRL", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32 - {name: "SHRW", argLength: 2, reg: gp21shift, asm: "SHRW", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32 - {name: "SHRB", argLength: 2, reg: gp21shift, asm: "SHRB", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32 - {name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31 - {name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-15 - {name: "SHRBconst", argLength: 1, reg: gp11, asm: "SHRB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-7 - - {name: "SARL", argLength: 2, reg: gp21shift, asm: "SARL", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32 - {name: "SARW", argLength: 2, reg: gp21shift, asm: "SARW", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32 - {name: "SARB", argLength: 2, reg: gp21shift, asm: "SARB", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32 - {name: "SARLconst", argLength: 1, reg: gp11, asm: "SARL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31 - {name: "SARWconst", argLength: 1, reg: gp11, asm: "SARW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-15 - {name: "SARBconst", argLength: 1, reg: gp11, asm: "SARB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-7 - - {name: "ROLL", argLength: 2, reg: gp21shift, asm: "ROLL", resultInArg0: true, clobberFlags: true}, // 32 bits of arg0 rotate left by arg1 - {name: "ROLW", argLength: 2, reg: gp21shift, asm: "ROLW", resultInArg0: true, clobberFlags: true}, // low 16 bits of arg0 rotate left by arg1 - {name: "ROLB", argLength: 2, reg: gp21shift, asm: "ROLB", resultInArg0: true, clobberFlags: true}, // low 8 bits of arg0 rotate left by arg1 - {name: "ROLLconst", argLength: 1, reg: gp11, asm: "ROLL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-31 - {name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-15 - {name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-7 + {name: "SHRL", argLength: 2, reg: gp21shift, asm: "SHRL", resultInArg0: true, clobberFlags: true, earlyOk: true}, // unsigned arg0 >> arg1, shift amount is mod 32 + {name: "SHRW", argLength: 2, reg: gp21shift, asm: "SHRW", resultInArg0: true, clobberFlags: true, earlyOk: true}, // unsigned arg0 >> arg1, shift amount is mod 32 + {name: "SHRB", argLength: 2, reg: gp21shift, asm: "SHRB", resultInArg0: true, clobberFlags: true, earlyOk: true}, // unsigned arg0 >> arg1, shift amount is mod 32 + {name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // unsigned arg0 >> auxint, shift amount 0-31 + {name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int16", resultInArg0: true, clobberFlags: true, earlyOk: true}, // unsigned arg0 >> auxint, shift amount 0-15 + {name: "SHRBconst", argLength: 1, reg: gp11, asm: "SHRB", aux: "Int8", resultInArg0: true, clobberFlags: true, earlyOk: true}, // unsigned arg0 >> auxint, shift amount 0-7 + + {name: "SARL", argLength: 2, reg: gp21shift, asm: "SARL", resultInArg0: true, clobberFlags: true, earlyOk: true}, // signed arg0 >> arg1, shift amount is mod 32 + {name: "SARW", argLength: 2, reg: gp21shift, asm: "SARW", resultInArg0: true, clobberFlags: true, earlyOk: true}, // signed arg0 >> arg1, shift amount is mod 32 + {name: "SARB", argLength: 2, reg: gp21shift, asm: "SARB", resultInArg0: true, clobberFlags: true, earlyOk: true}, // signed arg0 >> arg1, shift amount is mod 32 + {name: "SARLconst", argLength: 1, reg: gp11, asm: "SARL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // signed arg0 >> auxint, shift amount 0-31 + {name: "SARWconst", argLength: 1, reg: gp11, asm: "SARW", aux: "Int16", resultInArg0: true, clobberFlags: true, earlyOk: true}, // signed arg0 >> auxint, shift amount 0-15 + {name: "SARBconst", argLength: 1, reg: gp11, asm: "SARB", aux: "Int8", resultInArg0: true, clobberFlags: true, earlyOk: true}, // signed arg0 >> auxint, shift amount 0-7 + + {name: "ROLL", argLength: 2, reg: gp21shift, asm: "ROLL", resultInArg0: true, clobberFlags: true, earlyOk: true}, // 32 bits of arg0 rotate left by arg1 + {name: "ROLW", argLength: 2, reg: gp21shift, asm: "ROLW", resultInArg0: true, clobberFlags: true, earlyOk: true}, // low 16 bits of arg0 rotate left by arg1 + {name: "ROLB", argLength: 2, reg: gp21shift, asm: "ROLB", resultInArg0: true, clobberFlags: true, earlyOk: true}, // low 8 bits of arg0 rotate left by arg1 + {name: "ROLLconst", argLength: 1, reg: gp11, asm: "ROLL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 rotate left auxint, rotate amount 0-31 + {name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int16", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 rotate left auxint, rotate amount 0-15 + {name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 rotate left auxint, rotate amount 0-7 // binary-op with a memory source operand - {name: "ADDLload", argLength: 3, reg: gp21load, asm: "ADDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "SUBLload", argLength: 3, reg: gp21load, asm: "SUBL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "MULLload", argLength: 3, reg: gp21load, asm: "IMULL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "ANDLload", argLength: 3, reg: gp21load, asm: "ANDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "ORLload", argLength: 3, reg: gp21load, asm: "ORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem - {name: "XORLload", argLength: 3, reg: gp21load, asm: "XORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "ADDLload", argLength: 3, reg: gp21load, asm: "ADDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "SUBLload", argLength: 3, reg: gp21load, asm: "SUBL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "MULLload", argLength: 3, reg: gp21load, asm: "IMULL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "ANDLload", argLength: 3, reg: gp21load, asm: "ANDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "ORLload", argLength: 3, reg: gp21load, asm: "ORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "XORLload", argLength: 3, reg: gp21load, asm: "XORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem // binary-op with an indexed memory source operand - {name: "ADDLloadidx4", argLength: 4, reg: gp21loadidx, asm: "ADDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read"}, // arg0 + tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem - {name: "SUBLloadidx4", argLength: 4, reg: gp21loadidx, asm: "SUBL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read"}, // arg0 - tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem - {name: "MULLloadidx4", argLength: 4, reg: gp21loadidx, asm: "IMULL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read"}, // arg0 * tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem - {name: "ANDLloadidx4", argLength: 4, reg: gp21loadidx, asm: "ANDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read"}, // arg0 & tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem - {name: "ORLloadidx4", argLength: 4, reg: gp21loadidx, asm: "ORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read"}, // arg0 | tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem - {name: "XORLloadidx4", argLength: 4, reg: gp21loadidx, asm: "XORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read"}, // arg0 ^ tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem + {name: "ADDLloadidx4", argLength: 4, reg: gp21loadidx, asm: "ADDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read", addrSinkArg1: true}, // arg0 + tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem + {name: "SUBLloadidx4", argLength: 4, reg: gp21loadidx, asm: "SUBL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read", addrSinkArg1: true}, // arg0 - tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem + {name: "MULLloadidx4", argLength: 4, reg: gp21loadidx, asm: "IMULL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read", addrSinkArg1: true}, // arg0 * tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem + {name: "ANDLloadidx4", argLength: 4, reg: gp21loadidx, asm: "ANDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read", addrSinkArg1: true}, // arg0 & tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem + {name: "ORLloadidx4", argLength: 4, reg: gp21loadidx, asm: "ORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read", addrSinkArg1: true}, // arg0 | tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem + {name: "XORLloadidx4", argLength: 4, reg: gp21loadidx, asm: "XORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read", addrSinkArg1: true}, // arg0 ^ tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem // unary ops - {name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL", resultInArg0: true, clobberFlags: true}, // -arg0 + {name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL", resultInArg0: true, clobberFlags: true, earlyOk: true}, // -arg0 - {name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL", resultInArg0: true}, // ^arg0 + {name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL", resultInArg0: true, earlyOk: true}, // ^arg0 - {name: "BSFL", argLength: 1, reg: gp11, asm: "BSFL", clobberFlags: true}, // arg0 # of low-order zeroes ; undef if zero - {name: "BSFW", argLength: 1, reg: gp11, asm: "BSFW", clobberFlags: true}, // arg0 # of low-order zeroes ; undef if zero - {name: "LoweredCtz32", argLength: 1, reg: gp11, clobberFlags: true}, // arg0 # of low-order zeroes - {name: "LoweredCtz64", argLength: 2, reg: gp21, resultNotInArgs: true, clobberFlags: true}, // arg1<<32+arg0 # of low-order zeroes + {name: "BSFL", argLength: 1, reg: gp11, asm: "BSFL", clobberFlags: true, earlyOk: true}, // arg0 # of low-order zeroes ; undef if zero + {name: "BSFW", argLength: 1, reg: gp11, asm: "BSFW", clobberFlags: true, earlyOk: true}, // arg0 # of low-order zeroes ; undef if zero + {name: "LoweredCtz32", argLength: 1, reg: gp11, clobberFlags: true, earlyOk: true}, // arg0 # of low-order zeroes + {name: "LoweredCtz64", argLength: 2, reg: gp21, resultNotInArgs: true, clobberFlags: true, earlyOk: true}, // arg1<<32+arg0 # of low-order zeroes - {name: "BSRL", argLength: 1, reg: gp11, asm: "BSRL", clobberFlags: true}, // arg0 # of high-order zeroes ; undef if zero - {name: "BSRW", argLength: 1, reg: gp11, asm: "BSRW", clobberFlags: true}, // arg0 # of high-order zeroes ; undef if zero + {name: "BSRL", argLength: 1, reg: gp11, asm: "BSRL", clobberFlags: true, earlyOk: true}, // arg0 # of high-order zeroes ; undef if zero + {name: "BSRW", argLength: 1, reg: gp11, asm: "BSRW", clobberFlags: true, earlyOk: true}, // arg0 # of high-order zeroes ; undef if zero - {name: "BSWAPL", argLength: 1, reg: gp11, asm: "BSWAPL", resultInArg0: true}, // arg0 swap bytes + {name: "BSWAPL", argLength: 1, reg: gp11, asm: "BSWAPL", resultInArg0: true, earlyOk: true}, // arg0 swap bytes - {name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD"}, // sqrt(arg0) - {name: "SQRTSS", argLength: 1, reg: fp11, asm: "SQRTSS"}, // sqrt(arg0), float32 + {name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD", earlyOk: true}, // sqrt(arg0) + {name: "SQRTSS", argLength: 1, reg: fp11, asm: "SQRTSS", earlyOk: true}, // sqrt(arg0), float32 - {name: "SBBLcarrymask", argLength: 1, reg: flagsgp, asm: "SBBL"}, // (int32)(-1) if carry is set, 0 if carry is clear. + {name: "SBBLcarrymask", argLength: 1, reg: flagsgp, asm: "SBBL", earlyOk: true}, // (int32)(-1) if carry is set, 0 if carry is clear. // Note: SBBW and SBBB are subsumed by SBBL - {name: "SETEQ", argLength: 1, reg: readflags, asm: "SETEQ"}, // extract == condition from arg0 - {name: "SETNE", argLength: 1, reg: readflags, asm: "SETNE"}, // extract != condition from arg0 - {name: "SETL", argLength: 1, reg: readflags, asm: "SETLT"}, // extract signed < condition from arg0 - {name: "SETLE", argLength: 1, reg: readflags, asm: "SETLE"}, // extract signed <= condition from arg0 - {name: "SETG", argLength: 1, reg: readflags, asm: "SETGT"}, // extract signed > condition from arg0 - {name: "SETGE", argLength: 1, reg: readflags, asm: "SETGE"}, // extract signed >= condition from arg0 - {name: "SETB", argLength: 1, reg: readflags, asm: "SETCS"}, // extract unsigned < condition from arg0 - {name: "SETBE", argLength: 1, reg: readflags, asm: "SETLS"}, // extract unsigned <= condition from arg0 - {name: "SETA", argLength: 1, reg: readflags, asm: "SETHI"}, // extract unsigned > condition from arg0 - {name: "SETAE", argLength: 1, reg: readflags, asm: "SETCC"}, // extract unsigned >= condition from arg0 - {name: "SETO", argLength: 1, reg: readflags, asm: "SETOS"}, // extract if overflow flag is set from arg0 + {name: "SETEQ", argLength: 1, reg: readflags, asm: "SETEQ", earlyOk: true}, // extract == condition from arg0 + {name: "SETNE", argLength: 1, reg: readflags, asm: "SETNE", earlyOk: true}, // extract != condition from arg0 + {name: "SETL", argLength: 1, reg: readflags, asm: "SETLT", earlyOk: true}, // extract signed < condition from arg0 + {name: "SETLE", argLength: 1, reg: readflags, asm: "SETLE", earlyOk: true}, // extract signed <= condition from arg0 + {name: "SETG", argLength: 1, reg: readflags, asm: "SETGT", earlyOk: true}, // extract signed > condition from arg0 + {name: "SETGE", argLength: 1, reg: readflags, asm: "SETGE", earlyOk: true}, // extract signed >= condition from arg0 + {name: "SETB", argLength: 1, reg: readflags, asm: "SETCS", earlyOk: true}, // extract unsigned < condition from arg0 + {name: "SETBE", argLength: 1, reg: readflags, asm: "SETLS", earlyOk: true}, // extract unsigned <= condition from arg0 + {name: "SETA", argLength: 1, reg: readflags, asm: "SETHI", earlyOk: true}, // extract unsigned > condition from arg0 + {name: "SETAE", argLength: 1, reg: readflags, asm: "SETCC", earlyOk: true}, // extract unsigned >= condition from arg0 + {name: "SETO", argLength: 1, reg: readflags, asm: "SETOS", earlyOk: true}, // extract if overflow flag is set from arg0 // Need different opcodes for floating point conditions because // any comparison involving a NaN is always FALSE and thus // the patterns for inverting conditions cannot be used. - {name: "SETEQF", argLength: 1, reg: flagsgpax, asm: "SETEQ", clobberFlags: true}, // extract == condition from arg0 - {name: "SETNEF", argLength: 1, reg: flagsgpax, asm: "SETNE", clobberFlags: true}, // extract != condition from arg0 - {name: "SETORD", argLength: 1, reg: flagsgp, asm: "SETPC"}, // extract "ordered" (No Nan present) condition from arg0 - {name: "SETNAN", argLength: 1, reg: flagsgp, asm: "SETPS"}, // extract "unordered" (Nan present) condition from arg0 - - {name: "SETGF", argLength: 1, reg: flagsgp, asm: "SETHI"}, // extract floating > condition from arg0 - {name: "SETGEF", argLength: 1, reg: flagsgp, asm: "SETCC"}, // extract floating >= condition from arg0 - - {name: "MOVBLSX", argLength: 1, reg: gp11, asm: "MOVBLSX"}, // sign extend arg0 from int8 to int32 - {name: "MOVBLZX", argLength: 1, reg: gp11, asm: "MOVBLZX"}, // zero extend arg0 from int8 to int32 - {name: "MOVWLSX", argLength: 1, reg: gp11, asm: "MOVWLSX"}, // sign extend arg0 from int16 to int32 - {name: "MOVWLZX", argLength: 1, reg: gp11, asm: "MOVWLZX"}, // zero extend arg0 from int16 to int32 - - {name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true}, // 32 low bits of auxint - - {name: "CVTTSD2SL", argLength: 1, reg: fpgp, asm: "CVTTSD2SL"}, // convert float64 to int32 - {name: "CVTTSS2SL", argLength: 1, reg: fpgp, asm: "CVTTSS2SL"}, // convert float32 to int32 - {name: "CVTSL2SS", argLength: 1, reg: gpfp, asm: "CVTSL2SS"}, // convert int32 to float32 - {name: "CVTSL2SD", argLength: 1, reg: gpfp, asm: "CVTSL2SD"}, // convert int32 to float64 - {name: "CVTSD2SS", argLength: 1, reg: fp11, asm: "CVTSD2SS"}, // convert float64 to float32 - {name: "CVTSS2SD", argLength: 1, reg: fp11, asm: "CVTSS2SD"}, // convert float32 to float64 - - {name: "PXOR", argLength: 2, reg: fp21, asm: "PXOR", commutative: true, resultInArg0: true}, // exclusive or, applied to X regs for float negation. - - {name: "LEAL", argLength: 1, reg: gp11sb, aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux - {name: "LEAL1", argLength: 2, reg: gp21sb, commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux - {name: "LEAL2", argLength: 2, reg: gp21sb, aux: "SymOff", symEffect: "Addr"}, // arg0 + 2*arg1 + auxint + aux - {name: "LEAL4", argLength: 2, reg: gp21sb, aux: "SymOff", symEffect: "Addr"}, // arg0 + 4*arg1 + auxint + aux - {name: "LEAL8", argLength: 2, reg: gp21sb, aux: "SymOff", symEffect: "Addr"}, // arg0 + 8*arg1 + auxint + aux + {name: "SETEQF", argLength: 1, reg: flagsgpax, asm: "SETEQ", clobberFlags: true, earlyOk: true}, // extract == condition from arg0 + {name: "SETNEF", argLength: 1, reg: flagsgpax, asm: "SETNE", clobberFlags: true, earlyOk: true}, // extract != condition from arg0 + {name: "SETORD", argLength: 1, reg: flagsgp, asm: "SETPC", earlyOk: true}, // extract "ordered" (No Nan present) condition from arg0 + {name: "SETNAN", argLength: 1, reg: flagsgp, asm: "SETPS", earlyOk: true}, // extract "unordered" (Nan present) condition from arg0 + + {name: "SETGF", argLength: 1, reg: flagsgp, asm: "SETHI", earlyOk: true}, // extract floating > condition from arg0 + {name: "SETGEF", argLength: 1, reg: flagsgp, asm: "SETCC", earlyOk: true}, // extract floating >= condition from arg0 + + {name: "MOVBLSX", argLength: 1, reg: gp11, asm: "MOVBLSX", earlyOk: true}, // sign extend arg0 from int8 to int32 + {name: "MOVBLZX", argLength: 1, reg: gp11, asm: "MOVBLZX", earlyOk: true}, // zero extend arg0 from int8 to int32 + {name: "MOVWLSX", argLength: 1, reg: gp11, asm: "MOVWLSX", earlyOk: true}, // sign extend arg0 from int16 to int32 + {name: "MOVWLZX", argLength: 1, reg: gp11, asm: "MOVWLZX", earlyOk: true}, // zero extend arg0 from int16 to int32 + + {name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true, earlyOk: true}, // 32 low bits of auxint + + {name: "CVTTSD2SL", argLength: 1, reg: fpgp, asm: "CVTTSD2SL", earlyOk: true}, // convert float64 to int32 + {name: "CVTTSS2SL", argLength: 1, reg: fpgp, asm: "CVTTSS2SL", earlyOk: true}, // convert float32 to int32 + {name: "CVTSL2SS", argLength: 1, reg: gpfp, asm: "CVTSL2SS", earlyOk: true}, // convert int32 to float32 + {name: "CVTSL2SD", argLength: 1, reg: gpfp, asm: "CVTSL2SD", earlyOk: true}, // convert int32 to float64 + {name: "CVTSD2SS", argLength: 1, reg: fp11, asm: "CVTSD2SS", earlyOk: true}, // convert float64 to float32 + {name: "CVTSS2SD", argLength: 1, reg: fp11, asm: "CVTSS2SD", earlyOk: true}, // convert float32 to float64 + + {name: "PXOR", argLength: 2, reg: fp21, asm: "PXOR", commutative: true, resultInArg0: true, earlyOk: true}, // exclusive or, applied to X regs for float negation. + + {name: "LEAL", argLength: 1, reg: gp11sb, aux: "SymOff", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxint + offset encoded in aux + {name: "LEAL1", argLength: 2, reg: gp21sb, commutative: true, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + arg1 + auxint + aux + {name: "LEAL2", argLength: 2, reg: gp21sb, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 2*arg1 + auxint + aux + {name: "LEAL4", argLength: 2, reg: gp21sb, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 4*arg1 + auxint + aux + {name: "LEAL8", argLength: 2, reg: gp21sb, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 8*arg1 + auxint + aux // Note: LEAL{1,2,4,8} must not have OpSB as either argument. // auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address - {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load byte from arg0+auxint+aux. arg1=mem. Zero extend. - {name: "MOVBLSXload", argLength: 2, reg: gpload, asm: "MOVBLSX", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // ditto, sign extend to int32 - {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Zero extend. - {name: "MOVWLSXload", argLength: 2, reg: gpload, asm: "MOVWLSX", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // ditto, sign extend to int32 - {name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Zero extend. - {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem - {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem - {name: "MOVLstore", argLength: 3, reg: gpstore, asm: "MOVL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load byte from arg0+auxint+aux. arg1=mem. Zero extend. + {name: "MOVBLSXload", argLength: 2, reg: gpload, asm: "MOVBLSX", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // ditto, sign extend to int32 + {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Zero extend. + {name: "MOVWLSXload", argLength: 2, reg: gpload, asm: "MOVWLSX", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // ditto, sign extend to int32 + {name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Zero extend. + {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store byte in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVLstore", argLength: 3, reg: gpstore, asm: "MOVL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem // direct binary-op on memory (read-modify-write) - {name: "ADDLmodify", argLength: 3, reg: gpstore, asm: "ADDL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, clobberFlags: true, symEffect: "Read,Write"}, // *(arg0+auxint+aux) += arg1, arg2=mem - {name: "SUBLmodify", argLength: 3, reg: gpstore, asm: "SUBL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, clobberFlags: true, symEffect: "Read,Write"}, // *(arg0+auxint+aux) -= arg1, arg2=mem - {name: "ANDLmodify", argLength: 3, reg: gpstore, asm: "ANDL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, clobberFlags: true, symEffect: "Read,Write"}, // *(arg0+auxint+aux) &= arg1, arg2=mem - {name: "ORLmodify", argLength: 3, reg: gpstore, asm: "ORL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, clobberFlags: true, symEffect: "Read,Write"}, // *(arg0+auxint+aux) |= arg1, arg2=mem - {name: "XORLmodify", argLength: 3, reg: gpstore, asm: "XORL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, clobberFlags: true, symEffect: "Read,Write"}, // *(arg0+auxint+aux) ^= arg1, arg2=mem + {name: "ADDLmodify", argLength: 3, reg: gpstore, asm: "ADDL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // *(arg0+auxint+aux) += arg1, arg2=mem + {name: "SUBLmodify", argLength: 3, reg: gpstore, asm: "SUBL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // *(arg0+auxint+aux) -= arg1, arg2=mem + {name: "ANDLmodify", argLength: 3, reg: gpstore, asm: "ANDL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // *(arg0+auxint+aux) &= arg1, arg2=mem + {name: "ORLmodify", argLength: 3, reg: gpstore, asm: "ORL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // *(arg0+auxint+aux) |= arg1, arg2=mem + {name: "XORLmodify", argLength: 3, reg: gpstore, asm: "XORL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // *(arg0+auxint+aux) ^= arg1, arg2=mem // direct binary-op on indexed memory (read-modify-write) - {name: "ADDLmodifyidx4", argLength: 4, reg: gpstoreidx, asm: "ADDL", aux: "SymOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write"}, // *(arg0+arg1*4+auxint+aux) += arg2, arg3=mem - {name: "SUBLmodifyidx4", argLength: 4, reg: gpstoreidx, asm: "SUBL", aux: "SymOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write"}, // *(arg0+arg1*4+auxint+aux) -= arg2, arg3=mem - {name: "ANDLmodifyidx4", argLength: 4, reg: gpstoreidx, asm: "ANDL", aux: "SymOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write"}, // *(arg0+arg1*4+auxint+aux) &= arg2, arg3=mem - {name: "ORLmodifyidx4", argLength: 4, reg: gpstoreidx, asm: "ORL", aux: "SymOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write"}, // *(arg0+arg1*4+auxint+aux) |= arg2, arg3=mem - {name: "XORLmodifyidx4", argLength: 4, reg: gpstoreidx, asm: "XORL", aux: "SymOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write"}, // *(arg0+arg1*4+auxint+aux) ^= arg2, arg3=mem + {name: "ADDLmodifyidx4", argLength: 4, reg: gpstoreidx, asm: "ADDL", aux: "SymOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // *(arg0+arg1*4+auxint+aux) += arg2, arg3=mem + {name: "SUBLmodifyidx4", argLength: 4, reg: gpstoreidx, asm: "SUBL", aux: "SymOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // *(arg0+arg1*4+auxint+aux) -= arg2, arg3=mem + {name: "ANDLmodifyidx4", argLength: 4, reg: gpstoreidx, asm: "ANDL", aux: "SymOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // *(arg0+arg1*4+auxint+aux) &= arg2, arg3=mem + {name: "ORLmodifyidx4", argLength: 4, reg: gpstoreidx, asm: "ORL", aux: "SymOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // *(arg0+arg1*4+auxint+aux) |= arg2, arg3=mem + {name: "XORLmodifyidx4", argLength: 4, reg: gpstoreidx, asm: "XORL", aux: "SymOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // *(arg0+arg1*4+auxint+aux) ^= arg2, arg3=mem // direct binary-op on memory with a constant (read-modify-write) - {name: "ADDLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ADDL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // add ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem - {name: "ANDLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ANDL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // and ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem - {name: "ORLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ORL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // or ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem - {name: "XORLconstmodify", argLength: 2, reg: gpstoreconst, asm: "XORL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // xor ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem + {name: "ADDLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ADDL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // add ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem + {name: "ANDLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ANDL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // and ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem + {name: "ORLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ORL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // or ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem + {name: "XORLconstmodify", argLength: 2, reg: gpstoreconst, asm: "XORL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // xor ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem // direct binary-op on indexed memory with a constant (read-modify-write) - {name: "ADDLconstmodifyidx4", argLength: 3, reg: gpstoreconstidx, asm: "ADDL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write"}, // add ValAndOff(AuxInt).Val() to arg0+arg1*4+ValAndOff(AuxInt).Off()+aux, arg2=mem - {name: "ANDLconstmodifyidx4", argLength: 3, reg: gpstoreconstidx, asm: "ANDL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write"}, // and ValAndOff(AuxInt).Val() to arg0+arg1*4+ValAndOff(AuxInt).Off()+aux, arg2=mem - {name: "ORLconstmodifyidx4", argLength: 3, reg: gpstoreconstidx, asm: "ORL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write"}, // or ValAndOff(AuxInt).Val() to arg0+arg1*4+ValAndOff(AuxInt).Off()+aux, arg2=mem - {name: "XORLconstmodifyidx4", argLength: 3, reg: gpstoreconstidx, asm: "XORL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write"}, // xor ValAndOff(AuxInt).Val() to arg0+arg1*4+ValAndOff(AuxInt).Off()+aux, arg2=mem + {name: "ADDLconstmodifyidx4", argLength: 3, reg: gpstoreconstidx, asm: "ADDL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // add ValAndOff(AuxInt).Val() to arg0+arg1*4+ValAndOff(AuxInt).Off()+aux, arg2=mem + {name: "ANDLconstmodifyidx4", argLength: 3, reg: gpstoreconstidx, asm: "ANDL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // and ValAndOff(AuxInt).Val() to arg0+arg1*4+ValAndOff(AuxInt).Off()+aux, arg2=mem + {name: "ORLconstmodifyidx4", argLength: 3, reg: gpstoreconstidx, asm: "ORL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // or ValAndOff(AuxInt).Val() to arg0+arg1*4+ValAndOff(AuxInt).Off()+aux, arg2=mem + {name: "XORLconstmodifyidx4", argLength: 3, reg: gpstoreconstidx, asm: "XORL", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, symEffect: "Read,Write", addrSinkArg0: true}, // xor ValAndOff(AuxInt).Val() to arg0+arg1*4+ValAndOff(AuxInt).Off()+aux, arg2=mem // indexed loads/stores - {name: "MOVBloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBLZX", aux: "SymOff", symEffect: "Read"}, // load a byte from arg0+arg1+auxint+aux. arg2=mem - {name: "MOVWloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVWLZX", aux: "SymOff", symEffect: "Read"}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem - {name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", aux: "SymOff", symEffect: "Read"}, // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem - {name: "MOVLloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVL", aux: "SymOff", symEffect: "Read"}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem - {name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff", symEffect: "Read"}, // load 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem + {name: "MOVBloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBLZX", aux: "SymOff", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load a byte from arg0+arg1+auxint+aux. arg2=mem + {name: "MOVWloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVWLZX", aux: "SymOff", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem + {name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem + {name: "MOVLloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVL", aux: "SymOff", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem + {name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, // load 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem // TODO: sign-extending indexed loads - {name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVB", aux: "SymOff", symEffect: "Write"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem - {name: "MOVWstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVW", aux: "SymOff", symEffect: "Write"}, // store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem - {name: "MOVWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVW", aux: "SymOff", symEffect: "Write"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem - {name: "MOVLstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVL", aux: "SymOff", symEffect: "Write"}, // store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem - {name: "MOVLstoreidx4", argLength: 4, reg: gpstoreidx, asm: "MOVL", aux: "SymOff", symEffect: "Write"}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem + {name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVB", aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVWstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVW", aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVW", aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem + {name: "MOVLstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVL", aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVLstoreidx4", argLength: 4, reg: gpstoreidx, asm: "MOVL", aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem // TODO: add size-mismatched indexed loads, like MOVBstoreidx4. // For storeconst ops, the AuxInt field encodes both // the value to store and an address offset of the store. // Cast AuxInt to a ValAndOff to extract Val and Off fields. - {name: "MOVBstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem - {name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store low 2 bytes of ... - {name: "MOVLstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store low 4 bytes of ... + {name: "MOVBstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem + {name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store low 2 bytes of ... + {name: "MOVLstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store low 4 bytes of ... - {name: "MOVBstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVB", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+1*arg1+ValAndOff(AuxInt).Off()+aux. arg2=mem - {name: "MOVWstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 2 bytes of ... arg1 ... - {name: "MOVWstoreconstidx2", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 2 bytes of ... 2*arg1 ... - {name: "MOVLstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 4 bytes of ... arg1 ... - {name: "MOVLstoreconstidx4", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 4 bytes of ... 4*arg1 ... + {name: "MOVBstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVB", aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true}, // store low byte of ValAndOff(AuxInt).Val() to arg0+1*arg1+ValAndOff(AuxInt).Off()+aux. arg2=mem + {name: "MOVWstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true}, // store low 2 bytes of ... arg1 ... + {name: "MOVWstoreconstidx2", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true}, // store low 2 bytes of ... 2*arg1 ... + {name: "MOVLstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true}, // store low 4 bytes of ... arg1 ... + {name: "MOVLstoreconstidx4", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true}, // store low 4 bytes of ... 4*arg1 ... // arg0 = pointer to start of memory to zero // arg1 = value to store (will always be zero) @@ -438,6 +440,7 @@ func init() { // Note: CX is only clobbered when dynamic linking. }, faultOnNilArg0: true, + addrSinkArg0: true, }, // arg0 = address of memory to zero @@ -453,12 +456,14 @@ func init() { clobbers: buildReg("DI CX"), }, faultOnNilArg0: true, + addrSinkArg0: true, }, - {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("DX"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem - {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem + {name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem + {name: "CALLtailinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("DX"), regMask{}}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem // arg0 = destination pointer // arg1 = source pointer @@ -476,6 +481,8 @@ func init() { clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // arg0 = destination pointer @@ -492,6 +499,8 @@ func init() { }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // (InvertFlags (CMPL a b)) == (CMPL b a) @@ -520,7 +529,7 @@ func init() { // LoweredWB invokes runtime.gcWriteBarrier. arg0=mem, auxint=# of write barrier slots // It saves all GP registers if necessary, but may clobber others. // Returns a pointer to a write barrier buffer in DI. - {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave &^ gp, outputs: []regMask{buildReg("DI")}}, clobberFlags: true, aux: "Int64"}, + {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave.minus(gp), outputs: []regMask{buildReg("DI")}}, clobberFlags: true, aux: "Int64"}, // LoweredPanicBoundsRR takes x and y, two values that caused a bounds check to fail. // the RC and CR versions are used when one of the arguments is a constant. CC is used @@ -533,8 +542,8 @@ func init() { {name: "LoweredPanicBoundsCC", argLength: 1, aux: "PanicBoundsCC", reg: regInfo{}, typ: "Mem", call: true}, // arg0=mem, returns memory. // Same as above, but the x value is 64 bits. - {name: "LoweredPanicExtendRR", argLength: 4, aux: "Int64", reg: regInfo{inputs: []regMask{ax | cx | dx | bx, ax | cx | dx | bx, gp}}, typ: "Mem", call: true}, // arg0=x_hi, arg1=x_lo, arg2=y, arg3=mem, returns memory. - {name: "LoweredPanicExtendRC", argLength: 3, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{ax | cx | dx | bx, ax | cx | dx | bx}}, typ: "Mem", call: true}, // arg0=x_hi, arg1=x_lo, arg2=mem, returns memory. + {name: "LoweredPanicExtendRR", argLength: 4, aux: "Int64", reg: regInfo{inputs: []regMask{ax.union(cx).union(dx).union(bx), ax.union(cx).union(dx).union(bx), gp}}, typ: "Mem", call: true}, // arg0=x_hi, arg1=x_lo, arg2=y, arg3=mem, returns memory. + {name: "LoweredPanicExtendRC", argLength: 3, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{ax.union(cx).union(dx).union(bx), ax.union(cx).union(dx).union(bx)}}, typ: "Mem", call: true}, // arg0=x_hi, arg1=x_lo, arg2=mem, returns memory. // Constant flag values. For any comparison, there are 5 possible // outcomes: the three from the signed total order (<,==,>) and the @@ -553,10 +562,10 @@ func init() { // MOVSXconst1 loads the address of the constant-pool entry into a register. // MOVSXconst2 loads the constant from that address. // MOVSXconst1 returns a pointer, but we type it as uint32 because it can never point to the Go heap. - {name: "MOVSSconst1", reg: gp01, typ: "UInt32", aux: "Float32"}, - {name: "MOVSDconst1", reg: gp01, typ: "UInt32", aux: "Float64"}, - {name: "MOVSSconst2", argLength: 1, reg: gpfp, asm: "MOVSS"}, - {name: "MOVSDconst2", argLength: 1, reg: gpfp, asm: "MOVSD"}, + {name: "MOVSSconst1", reg: gp01, typ: "UInt32", aux: "Float32", earlyOk: true}, + {name: "MOVSDconst1", reg: gp01, typ: "UInt32", aux: "Float64", earlyOk: true}, + {name: "MOVSSconst2", argLength: 1, reg: gpfp, asm: "MOVSS", earlyOk: true}, + {name: "MOVSDconst2", argLength: 1, reg: gpfp, asm: "MOVSD", earlyOk: true}, } var _386blocks = []blockData{ diff --git a/src/cmd/compile/internal/ssa/_gen/386splitload.rules b/src/cmd/compile/internal/ssa/_gen/386splitload.rules index 29d4f8c227f550..b4258b631fc4b9 100644 --- a/src/cmd/compile/internal/ssa/_gen/386splitload.rules +++ b/src/cmd/compile/internal/ssa/_gen/386splitload.rules @@ -4,7 +4,7 @@ // See the top of AMD64splitload.rules for discussion of these rules. -(CMP(L|W|B)load {sym} [off] ptr x mem) => (CMP(L|W|B) (MOV(L|W|B)load {sym} [off] ptr mem) x) +(CMP(L|W|B)load {sym} [off] ptr x mem) => (CMP(L|W|B) (MOV(L|W|B)load {sym} [off] ptr mem) x) (CMPLconstload {sym} [vo] ptr mem) => (CMPLconst (MOVLload {sym} [vo.Off()] ptr mem) [vo.Val()]) (CMPWconstload {sym} [vo] ptr mem) => (CMPWconst (MOVWload {sym} [vo.Off()] ptr mem) [vo.Val16()]) diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64.rules b/src/cmd/compile/internal/ssa/_gen/AMD64.rules index 0bea99e38de1bc..36c1e3354d6f06 100644 --- a/src/cmd/compile/internal/ssa/_gen/AMD64.rules +++ b/src/cmd/compile/internal/ssa/_gen/AMD64.rules @@ -27,15 +27,10 @@ (Div8u x y) => (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) (Div(32|64)F ...) => (DIVS(S|D) ...) -(Select0 (Add64carry x y c)) => - (Select0 (ADCQ x y (Select1 (NEGLflags c)))) -(Select1 (Add64carry x y c)) => - (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) -(Select0 (Sub64borrow x y c)) => - (Select0 (SBBQ x y (Select1 (NEGLflags c)))) -(Select1 (Sub64borrow x y c)) => - (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) - +(Select0 (Add64carry x y c)) => (Select0 (ADCQ x y (Select1 (NEGLflags c)))) +(Select1 (Add64carry x y c)) => (MOVBQZX (SETB (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) +(Select0 (Sub64borrow x y c)) => (Select0 (SBBQ x y (Select1 (NEGLflags c)))) +(Select1 (Sub64borrow x y c)) => (MOVBQZX (SETB (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) // Optimize ADCQ and friends (ADCQ x (MOVQconst [c]) carry) && is32Bit(c) => (ADCQconst x [int32(c)] carry) (ADCQ x y (FlagEQ)) => (ADDQcarry x y) @@ -46,7 +41,13 @@ (SBBQconst x [c] (FlagEQ)) => (SUBQconstborrow x [c]) (SUBQborrow x (MOVQconst [c])) && is32Bit(c) => (SUBQconstborrow x [int32(c)]) (Select1 (NEGLflags (MOVQconst [0]))) => (FlagEQ) -(Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) => x +(Select1 (NEGLflags (MOVBQZX (SETB x)))) => x +// Absorb InvertFlags into ADCQ/SBBQ: CF(InvertFlags(f)) = SETA(f), so +// re-materialize the carry/borrow through the SETA+NEGLflags path. +(ADCQ x y (InvertFlags f)) => (ADCQ x y (Select1 (NEGLflags (MOVBQZX (SETA f))))) +(ADCQconst x [c] (InvertFlags f)) => (ADCQconst x [c] (Select1 (NEGLflags (MOVBQZX (SETA f))))) +(SBBQ x y (InvertFlags f)) => (SBBQ x y (Select1 (NEGLflags (MOVBQZX (SETA f))))) +(SBBQconst x [c] (InvertFlags f)) => (SBBQconst x [c] (Select1 (NEGLflags (MOVBQZX (SETA f))))) (Mul64uhilo ...) => (MULQU2 ...) @@ -124,6 +125,8 @@ (Ceil x) => (ROUNDSD [2] x) (Trunc x) => (ROUNDSD [3] x) +(CVTSD2SS (ROUNDSD [c] (CVTSS2SD x))) => (ROUNDSS [c] x) + (FMA x y z) => (VFMADD231SD z x y) // Lowering extension @@ -385,6 +388,7 @@ (ClosureCall ...) => (CALLclosure ...) (InterCall ...) => (CALLinter ...) (TailCall ...) => (CALLtail ...) +(TailCallInter ...) => (CALLtailinter ...) // Lowering conditional moves // If the condition is a SETxx, we can just run a CMOV from the comparison that was @@ -397,20 +401,30 @@ (CondSelect x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && is16BitInt(t) => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond) -// If the condition does not set the flags, we need to generate a comparison. -(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 - => (CondSelect x y (MOVBQZX check)) -(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 - => (CondSelect x y (MOVWQZX check)) -(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 - => (CondSelect x y (MOVLQZX check)) - (CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) => (CMOVQNE y x (CMPQconst [0] check)) (CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) => (CMOVLNE y x (CMPQconst [0] check)) (CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) => (CMOVWNE y x (CMPQconst [0] check)) +(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && (is64BitInt(t) || isPtr(t)) + => (CMOVQNE y x (CMPLconst [0] check)) +(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && is32BitInt(t) + => (CMOVLNE y x (CMPLconst [0] check)) +(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && is16BitInt(t) + => (CMOVWNE y x (CMPLconst [0] check)) +(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && (is64BitInt(t) || isPtr(t)) + => (CMOVQNE y x (CMPWconst [0] check)) +(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && is32BitInt(t) + => (CMOVLNE y x (CMPWconst [0] check)) +(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && is16BitInt(t) + => (CMOVWNE y x (CMPWconst [0] check)) +(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && (is64BitInt(t) || isPtr(t)) + => (CMOVQNE y x (CMPBconst [0] check)) +(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && is32BitInt(t) + => (CMOVLNE y x (CMPBconst [0] check)) +(CondSelect x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && is16BitInt(t) + => (CMOVWNE y x (CMPBconst [0] check)) // Absorb InvertFlags (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond)) @@ -588,30 +602,30 @@ // mutandis, for UGE and SETAE, and CC and SETCC. ((NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => ((ULT|UGE) (BTL x y)) ((NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => ((ULT|UGE) (BTQ x y)) -((NE|EQ) (TESTLconst [c] x)) && isUnsignedPowerOfTwo(uint32(c)) +((NE|EQ) (TESTLconst [c] x)) && isPowerOfTwo(uint32(c)) => ((ULT|UGE) (BTLconst [int8(log32u(uint32(c)))] x)) -((NE|EQ) (TESTQconst [c] x)) && isUnsignedPowerOfTwo(uint64(c)) +((NE|EQ) (TESTQconst [c] x)) && isPowerOfTwo(uint64(c)) => ((ULT|UGE) (BTQconst [int8(log32u(uint32(c)))] x)) -((NE|EQ) (TESTQ (MOVQconst [c]) x)) && isUnsignedPowerOfTwo(uint64(c)) +((NE|EQ) (TESTQ (MOVQconst [c]) x)) && isPowerOfTwo(uint64(c)) => ((ULT|UGE) (BTQconst [int8(log64u(uint64(c)))] x)) (SET(NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => (SET(B|AE) (BTL x y)) (SET(NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => (SET(B|AE) (BTQ x y)) -(SET(NE|EQ) (TESTLconst [c] x)) && isUnsignedPowerOfTwo(uint32(c)) +(SET(NE|EQ) (TESTLconst [c] x)) && isPowerOfTwo(uint32(c)) => (SET(B|AE) (BTLconst [int8(log32u(uint32(c)))] x)) -(SET(NE|EQ) (TESTQconst [c] x)) && isUnsignedPowerOfTwo(uint64(c)) +(SET(NE|EQ) (TESTQconst [c] x)) && isPowerOfTwo(uint64(c)) => (SET(B|AE) (BTQconst [int8(log32u(uint32(c)))] x)) -(SET(NE|EQ) (TESTQ (MOVQconst [c]) x)) && isUnsignedPowerOfTwo(uint64(c)) +(SET(NE|EQ) (TESTQ (MOVQconst [c]) x)) && isPowerOfTwo(uint64(c)) => (SET(B|AE) (BTQconst [int8(log64u(uint64(c)))] x)) // SET..store variant (SET(NE|EQ)store [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) => (SET(B|AE)store [off] {sym} ptr (BTL x y) mem) (SET(NE|EQ)store [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) => (SET(B|AE)store [off] {sym} ptr (BTQ x y) mem) -(SET(NE|EQ)store [off] {sym} ptr (TESTLconst [c] x) mem) && isUnsignedPowerOfTwo(uint32(c)) +(SET(NE|EQ)store [off] {sym} ptr (TESTLconst [c] x) mem) && isPowerOfTwo(uint32(c)) => (SET(B|AE)store [off] {sym} ptr (BTLconst [int8(log32u(uint32(c)))] x) mem) -(SET(NE|EQ)store [off] {sym} ptr (TESTQconst [c] x) mem) && isUnsignedPowerOfTwo(uint64(c)) +(SET(NE|EQ)store [off] {sym} ptr (TESTQconst [c] x) mem) && isPowerOfTwo(uint64(c)) => (SET(B|AE)store [off] {sym} ptr (BTQconst [int8(log32u(uint32(c)))] x) mem) -(SET(NE|EQ)store [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) && isUnsignedPowerOfTwo(uint64(c)) +(SET(NE|EQ)store [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) && isPowerOfTwo(uint64(c)) => (SET(B|AE)store [off] {sym} ptr (BTQconst [int8(log64u(uint64(c)))] x) mem) // Handle bit-testing in the form (a>>b)&1 != 0 by building the above rules @@ -637,14 +651,14 @@ (XOR(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y) x) => (BTC(Q|L) x y) // Note: only convert OR/XOR to BTS/BTC if the constant wouldn't fit in // the constant field of the OR/XOR instruction. See issue 61694. -((OR|XOR)Q (MOVQconst [c]) x) && isUnsignedPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31 => (BT(S|C)Qconst [int8(log64u(uint64(c)))] x) +((OR|XOR)Q (MOVQconst [c]) x) && isPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31 => (BT(S|C)Qconst [int8(log64u(uint64(c)))] x) // Recognize bit clearing: a &^= 1< (BTR(Q|L) x y) (ANDN(Q|L) x (SHL(Q|L) (MOV(Q|L)const [1]) y)) => (BTR(Q|L) x y) // Note: only convert AND to BTR if the constant wouldn't fit in // the constant field of the AND instruction. See issue 61694. -(ANDQ (MOVQconst [c]) x) && isUnsignedPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31 => (BTRQconst [int8(log64u(uint64(^c)))] x) +(ANDQ (MOVQconst [c]) x) && isPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31 => (BTRQconst [int8(log64u(uint64(^c)))] x) // Special-case bit patterns on first/last bit. // generic.rules changes ANDs of high-part/low-part masks into a couple of shifts, @@ -817,10 +831,6 @@ ((SHRB|SARB)const x [0]) => x ((ROLQ|ROLL|ROLW|ROLB)const x [0]) => x -// Multi-register shifts -(ORQ (SH(R|L)Q lo bits) (SH(L|R)Q hi (NEGQ bits))) => (SH(R|L)DQ lo hi bits) -(ORQ (SH(R|L)XQ lo bits) (SH(L|R)XQ hi (NEGQ bits))) => (SH(R|L)DQ lo hi bits) - // Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits) // because the x86 instructions are defined to use all 5 bits of the shift even // for the small shifts. I don't think we'll ever generate a weird shift (e.g. @@ -899,7 +909,8 @@ (LEA(Q|L)2 [0] {s} (ADD(Q|L) x x) x) && s == nil => (SHL(Q|L)const [2] x) // (x + x) << 2 -> x << 3 and similar -(SHL(Q|L)const [c] (ADD(Q|L) x x)) => (SHL(Q|L)const [c+1] x) +(SHLQconst [c] (ADDQ x x)) && c < 63 => (SHLQconst [c+1] x) +(SHLLconst [c] (ADDL x x)) && c < 31 => (SHLLconst [c+1] x) // reverse ordering of compare instruction (SETL (InvertFlags x)) => (SETG x) @@ -1276,20 +1287,13 @@ (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) // Remove redundant *const ops -(ADDQconst [0] x) => x -(ADDLconst [c] x) && c==0 => x -(SUBQconst [0] x) => x -(SUBLconst [c] x) && c==0 => x -(ANDQconst [0] _) => (MOVQconst [0]) -(ANDLconst [c] _) && c==0 => (MOVLconst [0]) -(ANDQconst [-1] x) => x -(ANDLconst [c] x) && c==-1 => x -(ORQconst [0] x) => x -(ORLconst [c] x) && c==0 => x -(ORQconst [-1] _) => (MOVQconst [-1]) -(ORLconst [c] _) && c==-1 => (MOVLconst [-1]) -(XORQconst [0] x) => x -(XORLconst [c] x) && c==0 => x +(ADD(Q|L)const [0] x) => x +(SUB(Q|L)const [0] x) => x +(AND(Q|L)const [0] _) => (MOVLconst [0]) +(AND(Q|L)const [-1] x) => x +(OR(Q|L)const [0] x) => x +(OR(Q|L)const [-1] _) => (MOV(Q|L)const [-1]) +(XOR(Q|L)const [0] x) => x // TODO: since we got rid of the W/B versions, we might miss // things like (ANDLconst [0x100] x) which were formerly // (ANDBconst [0] x). Probably doesn't happen very often. @@ -1317,8 +1321,7 @@ (SARLconst [c] (MOVQconst [d])) => (MOVQconst [int64(int32(d))>>uint64(c)]) (SARWconst [c] (MOVQconst [d])) => (MOVQconst [int64(int16(d))>>uint64(c)]) (SARBconst [c] (MOVQconst [d])) => (MOVQconst [int64(int8(d))>>uint64(c)]) -(NEGQ (MOVQconst [c])) => (MOVQconst [-c]) -(NEGL (MOVLconst [c])) => (MOVLconst [-c]) +(NEG(Q|L) (MOV(Q|L)const [c])) => (MOV(Q|L)const [-c]) (MULQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)*d]) (MULLconst [c] (MOVLconst [d])) => (MOVLconst [c*d]) (ANDQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)&d]) @@ -1327,8 +1330,7 @@ (ORLconst [c] (MOVLconst [d])) => (MOVLconst [c|d]) (XORQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)^d]) (XORLconst [c] (MOVLconst [d])) => (MOVLconst [c^d]) -(NOTQ (MOVQconst [c])) => (MOVQconst [^c]) -(NOTL (MOVLconst [c])) => (MOVLconst [^c]) +(NOT(Q|L) (MOV(Q|L)const [c])) => (MOV(Q|L)const [^c]) (BTSQconst [c] (MOVQconst [d])) => (MOVQconst [d|(1< (MOVQconst [d&^(1< (MOVQconst [d^(1< (SUBQ x y) -(ADDL x (NEGL y)) => (SUBL x y) -(SUBQ x x) => (MOVQconst [0]) -(SUBL x x) => (MOVLconst [0]) -(ANDQ x x) => x -(ANDL x x) => x -(ORQ x x) => x -(ORL x x) => x -(XORQ x x) => (MOVQconst [0]) -(XORL x x) => (MOVLconst [0]) +(ADD(Q|L) x (NEG(Q|L) y)) => (SUB(Q|L) x y) +(SUB(Q|L) x x) => (MOVLconst [0]) +(AND(Q|L) x x) => x +(OR(Q|L) x x) => x +(XOR(Q|L) x x) => (MOVLconst [0]) (SHLLconst [d] (MOVLconst [c])) => (MOVLconst [c << uint64(d)]) (SHLQconst [d] (MOVQconst [c])) => (MOVQconst [c << uint64(d)]) @@ -1361,10 +1358,7 @@ (MULQconst [c] (NEGQ x)) && c != -(1<<31) => (MULQconst [-c] x) // checking AND against 0. -(CMPQconst a:(ANDQ x y) [0]) && a.Uses == 1 => (TESTQ x y) -(CMPLconst a:(ANDL x y) [0]) && a.Uses == 1 => (TESTL x y) -(CMPWconst a:(ANDL x y) [0]) && a.Uses == 1 => (TESTW x y) -(CMPBconst a:(ANDL x y) [0]) && a.Uses == 1 => (TESTB x y) +(CMP(Q|L|W|B)const a:(AND(Q|L|L|L) x y) [0]) && a.Uses == 1 => (TEST(Q|L|W|B) x y) (CMPQconst a:(ANDQconst [c] x) [0]) && a.Uses == 1 => (TESTQconst [c] x) (CMPLconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTLconst [c] x) (CMPWconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTWconst [int16(c)] x) @@ -1377,10 +1371,7 @@ (TESTB (MOVLconst [c]) x) => (TESTBconst [int8(c)] x) // TEST %reg,%reg is shorter than CMP -(CMPQconst x [0]) => (TESTQ x x) -(CMPLconst x [0]) => (TESTL x x) -(CMPWconst x [0]) => (TESTW x x) -(CMPBconst x [0]) => (TESTB x x) +(CMP(Q|L|W|B)const x [0]) => (TEST(Q|L|W|B) x x) (TESTQconst [-1] x) && x.Op != OpAMD64MOVQconst => (TESTQ x x) (TESTLconst [-1] x) && x.Op != OpAMD64MOVLconst => (TESTL x x) (TESTWconst [-1] x) && x.Op != OpAMD64MOVLconst => (TESTW x x) @@ -1568,7 +1559,8 @@ (MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read8(sym, int64(off)))]) (MOVWload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) -(MOVLload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) +(MOVLload [off] {sym} (SB) _) && symIsRO(sym) && is32BitInt(t) => (MOVLconst [int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) +(MOVLload [off] {sym} (SB) _) && symIsRO(sym) && is64BitInt(t) => (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) (MOVQload [off] {sym} (SB) _) && symIsRO(sym) => (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) (MOVBQSXload [off] {sym} (SB) _) && symIsRO(sym) => (MOVQconst [int64(int8(read8(sym, int64(off))))]) (MOVWQSXload [off] {sym} (SB) _) && symIsRO(sym) => (MOVQconst [int64(int16(read16(sym, int64(off), config.ctxt.Arch.ByteOrder)))]) @@ -1647,3 +1639,288 @@ // If we don't use the flags any more, just use the standard op. (Select0 a:(ADD(Q|L)constflags [c] x)) && a.Uses == 1 => (ADD(Q|L)const [c] x) + +// SIMD lowering rules + +// Mask conversions +// integers to masks +(Cvt16toMask8x16 x) => (VPMOVMToVec8x16 (KMOVWk x)) +(Cvt32toMask8x32 x) => (VPMOVMToVec8x32 (KMOVDk x)) +(Cvt64toMask8x64 x) => (VPMOVMToVec8x64 (KMOVQk x)) + +(Cvt8toMask16x8 x) => (VPMOVMToVec16x8 (KMOVBk x)) +(Cvt16toMask16x16 x) => (VPMOVMToVec16x16 (KMOVWk x)) +(Cvt32toMask16x32 x) => (VPMOVMToVec16x32 (KMOVDk x)) + +(Cvt8toMask32x4 x) => (VPMOVMToVec32x4 (KMOVBk x)) +(Cvt8toMask32x8 x) => (VPMOVMToVec32x8 (KMOVBk x)) +(Cvt16toMask32x16 x) => (VPMOVMToVec32x16 (KMOVWk x)) + +(Cvt8toMask64x2 x) => (VPMOVMToVec64x2 (KMOVBk x)) +(Cvt8toMask64x4 x) => (VPMOVMToVec64x4 (KMOVBk x)) +(Cvt8toMask64x8 x) => (VPMOVMToVec64x8 (KMOVBk x)) + +// masks to integers +(CvtMask8x16to16 ...) => (VPMOVMSKB128 ...) +(CvtMask8x32to32 ...) => (VPMOVMSKB256 ...) +(CvtMask8x64to64 x) => (KMOVQi (VPMOVVec8x64ToM x)) + +(CvtMask16x8to8 x) => (KMOVBi (VPMOVVec16x8ToM x)) +(CvtMask16x16to16 x) => (KMOVWi (VPMOVVec16x16ToM x)) +(CvtMask16x32to32 x) => (KMOVDi (VPMOVVec16x32ToM x)) + +(CvtMask32x4to8 ...) => (VMOVMSKPS128 ...) +(CvtMask32x8to8 ...) => (VMOVMSKPS256 ...) +(CvtMask32x16to16 x) => (KMOVWi (VPMOVVec32x16ToM x)) + +(CvtMask64x2to8 ...) => (VMOVMSKPD128 ...) +(CvtMask64x4to8 ...) => (VMOVMSKPD256 ...) +(CvtMask64x8to8 x) => (KMOVBi (VPMOVVec64x8ToM x)) + +// optimizations +(MOVBstore [off] {sym} ptr (KMOVBi mask) mem) => (KMOVBstore [off] {sym} ptr mask mem) +(MOVWstore [off] {sym} ptr (KMOVWi mask) mem) => (KMOVWstore [off] {sym} ptr mask mem) +(MOVLstore [off] {sym} ptr (KMOVDi mask) mem) => (KMOVDstore [off] {sym} ptr mask mem) +(MOVQstore [off] {sym} ptr (KMOVQi mask) mem) => (KMOVQstore [off] {sym} ptr mask mem) + +(KMOVBk l:(MOVBload [off] {sym} ptr mem)) && canMergeLoad(v, l) && clobber(l) => (KMOVBload [off] {sym} ptr mem) +(KMOVWk l:(MOVWload [off] {sym} ptr mem)) && canMergeLoad(v, l) && clobber(l) => (KMOVWload [off] {sym} ptr mem) +(KMOVDk l:(MOVLload [off] {sym} ptr mem)) && canMergeLoad(v, l) && clobber(l) => (KMOVDload [off] {sym} ptr mem) +(KMOVQk l:(MOVQload [off] {sym} ptr mem)) && canMergeLoad(v, l) && clobber(l) => (KMOVQload [off] {sym} ptr mem) + +// SIMD vector loads and stores +(Load ptr mem) && t.Size() == 16 => (VMOVDQUload128 ptr mem) +(Store {t} ptr val mem) && t.Size() == 16 => (VMOVDQUstore128 ptr val mem) + +(Load ptr mem) && t.Size() == 32 => (VMOVDQUload256 ptr mem) +(Store {t} ptr val mem) && t.Size() == 32 => (VMOVDQUstore256 ptr val mem) + +(Load ptr mem) && t.Size() == 64 => (VMOVDQUload512 ptr mem) +(Store {t} ptr val mem) && t.Size() == 64 => (VMOVDQUstore512 ptr val mem) + +// SIMD vector integer-vector-masked loads and stores. +(LoadMasked32 ptr mask mem) && t.Size() == 16 => (VPMASK32load128 ptr mask mem) +(LoadMasked32 ptr mask mem) && t.Size() == 32 => (VPMASK32load256 ptr mask mem) +(LoadMasked64 ptr mask mem) && t.Size() == 16 => (VPMASK64load128 ptr mask mem) +(LoadMasked64 ptr mask mem) && t.Size() == 32 => (VPMASK64load256 ptr mask mem) + +(StoreMasked32 {t} ptr mask val mem) && t.Size() == 16 => (VPMASK32store128 ptr mask val mem) +(StoreMasked32 {t} ptr mask val mem) && t.Size() == 32 => (VPMASK32store256 ptr mask val mem) +(StoreMasked64 {t} ptr mask val mem) && t.Size() == 16 => (VPMASK64store128 ptr mask val mem) +(StoreMasked64 {t} ptr mask val mem) && t.Size() == 32 => (VPMASK64store256 ptr mask val mem) + +// Misc +(IsZeroVec x) => (SETEQ (VPTEST x x)) + +(IsNaNFloat32x4 x) => (VCMPPS128 [3] x x) +(IsNaNFloat32x8 x) => (VCMPPS256 [3] x x) +(IsNaNFloat32x16 x) => (VPMOVMToVec32x16 (VCMPPS512 [3] x x)) +(IsNaNFloat64x2 x) => (VCMPPD128 [3] x x) +(IsNaNFloat64x4 x) => (VCMPPD256 [3] x x) +(IsNaNFloat64x8 x) => (VPMOVMToVec64x8 (VCMPPD512 [3] x x)) + +// SIMD vector K-masked loads and stores + +(LoadMasked64 ptr mask mem) && t.Size() == 64 => (VPMASK64load512 ptr (VPMOVVec64x8ToM mask) mem) +(LoadMasked32 ptr mask mem) && t.Size() == 64 => (VPMASK32load512 ptr (VPMOVVec32x16ToM mask) mem) +(LoadMasked16 ptr mask mem) && t.Size() == 64 => (VPMASK16load512 ptr (VPMOVVec16x32ToM mask) mem) +(LoadMasked8 ptr mask mem) && t.Size() == 64 => (VPMASK8load512 ptr (VPMOVVec8x64ToM mask) mem) + +(StoreMasked64 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK64store512 ptr (VPMOVVec64x8ToM mask) val mem) +(StoreMasked32 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK32store512 ptr (VPMOVVec32x16ToM mask) val mem) +(StoreMasked16 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK16store512 ptr (VPMOVVec16x32ToM mask) val mem) +(StoreMasked8 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK8store512 ptr (VPMOVVec8x64ToM mask) val mem) + +(ZeroSIMD ) && t.Size() == 16 => (Zero128 ) +(ZeroSIMD ) && t.Size() == 32 => (Zero256 ) +(ZeroSIMD ) && t.Size() == 64 => (Zero512 ) + +// optimize x.IsNaN().Or(y.IsNaN()) +// do these before the mask rewrites +(VPOR128 (VCMPP(S|D)128 [3] x x) (VCMPP(S|D)128 [3] y y)) => (VCMPP(S|D)128 [3] x y) +(VPOR256 (VCMPP(S|D)256 [3] x x) (VCMPP(S|D)256 [3] y y)) => (VCMPP(S|D)256 [3] x y) +(VPORD512 (VPMOVMToVec32x16 (VCMPPS512 [3] x x)) (VPMOVMToVec32x16 (VCMPPS512 [3] y y))) => + (VPMOVMToVec32x16 (VCMPPS512 [3] x y)) +(VPORD512 (VPMOVMToVec64x8 (VCMPPD512 [3] x x)) (VPMOVMToVec64x8 (VCMPPD512 [3] y y))) => + (VPMOVMToVec64x8 (VCMPPD512 [3] x y)) + +// Include these rules because you never know about rewrite order +(KANDB (VCMPPD512 [3] x x) (VCMPPD512 [3] y y)) => (VCMPPD512 [3] x x) // 512 = 64x8 -> KANDB +(KANDW (VCMPPS512 [3] x x) (VCMPPS512 [3] y y)) => (VCMPPS512 [3] x y) // 512 = 32x16 -> KANDW + +// These larger simplifying rules must come before the smaller simplifying rules that might break them). +// Rewrite rules for binary logical mask operations that apply to 8-bit elements (B, for bytes) of 128, 256, and 512-bit vectors +(VPAND128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x16 (KANDW x y)) +(VPAND256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x32 (KANDD x y)) +(VPANDD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x64 (KANDQ x y)) + +(VPOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x16 (KORW x y)) +(VPOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x32 (KORD x y)) +(VPORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x64 (KORQ x y)) + +(VPXOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x16 (KXORW x y)) +(VPXOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x32 (KXORD x y)) +(VPXORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x64 (KXORQ x y)) + +// Rewrite rules for binary logical mask operations that apply to 16-bit elements (W, for words) of 128, 256, and 512-bit vectors +(VPAND128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x8 (KANDB x y)) +(VPAND256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x16 (KANDW x y)) +(VPANDD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x32 (KANDD x y)) + +(VPOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x8 (KORB x y)) +(VPOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x16 (KORW x y)) +(VPORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x32 (KORD x y)) + +(VPXOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x8 (KXORB x y)) +(VPXOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x16 (KXORW x y)) +(VPXORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x32 (KXORD x y)) + +// Rewrite rules for binary logical mask operations that apply to 32-bit elements (D, for doublewords) of 128, 256, and 512-bit vectors +(VPAND128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x4 (KANDB x y)) +(VPAND256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x8 (KANDB x y)) +(VPANDD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x16 (KANDW x y)) + +(VPOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x4 (KORB x y)) +(VPOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x8 (KORB x y)) +(VPORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x16 (KORW x y)) + +(VPXOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x4 (KXORB x y)) +(VPXOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x8 (KXORB x y)) +(VPXORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x16 (KXORW x y)) + +// Rewrite rules for binary logical mask operations that apply to 64-bit elements (Q, for quadwords) of 128, 256, and 512-bit vectors +(VPAND128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x2 (KANDB x y)) +(VPAND256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x4 (KANDB x y)) +(VPANDD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x8 (KANDB x y)) + +(VPOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x2 (KORB x y)) +(VPOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x4 (KORB x y)) +(VPORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x8 (KORB x y)) + +(VPXOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x2 (KXORB x y)) +(VPXOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x4 (KXORB x y)) +(VPXORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x8 (KXORB x y)) + +(VPMOVVec8x16ToM (VPMOVMToVec8x16 x)) => x +(VPMOVVec8x32ToM (VPMOVMToVec8x32 x)) => x +(VPMOVVec8x64ToM (VPMOVMToVec8x64 x)) => x + +(VPMOVVec16x8ToM (VPMOVMToVec16x8 x)) => x +(VPMOVVec16x16ToM (VPMOVMToVec16x16 x)) => x +(VPMOVVec16x32ToM (VPMOVMToVec16x32 x)) => x + +(VPMOVVec32x4ToM (VPMOVMToVec32x4 x)) => x +(VPMOVVec32x8ToM (VPMOVMToVec32x8 x)) => x +(VPMOVVec32x16ToM (VPMOVMToVec32x16 x)) => x + +(VPMOVVec64x2ToM (VPMOVMToVec64x2 x)) => x +(VPMOVVec64x4ToM (VPMOVMToVec64x4 x)) => x +(VPMOVVec64x8ToM (VPMOVMToVec64x8 x)) => x + +(VPANDQ512 x (VPMOVMToVec64x8 k)) => (VMOVDQU64Masked512 x k) +(VPANDQ512 x (VPMOVMToVec32x16 k)) => (VMOVDQU32Masked512 x k) +(VPANDQ512 x (VPMOVMToVec16x32 k)) => (VMOVDQU16Masked512 x k) +(VPANDQ512 x (VPMOVMToVec8x64 k)) => (VMOVDQU8Masked512 x k) +(VPANDD512 x (VPMOVMToVec64x8 k)) => (VMOVDQU64Masked512 x k) +(VPANDD512 x (VPMOVMToVec32x16 k)) => (VMOVDQU32Masked512 x k) +(VPANDD512 x (VPMOVMToVec16x32 k)) => (VMOVDQU16Masked512 x k) +(VPANDD512 x (VPMOVMToVec8x64 k)) => (VMOVDQU8Masked512 x k) + +(VPAND128 x (VPMOVMToVec8x16 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU8Masked128 x k) +(VPAND128 x (VPMOVMToVec16x8 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU16Masked128 x k) +(VPAND128 x (VPMOVMToVec32x4 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU32Masked128 x k) +(VPAND128 x (VPMOVMToVec64x2 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU64Masked128 x k) + +(VPAND256 x (VPMOVMToVec8x32 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU8Masked256 x k) +(VPAND256 x (VPMOVMToVec16x16 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU16Masked256 x k) +(VPAND256 x (VPMOVMToVec32x8 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU32Masked256 x k) +(VPAND256 x (VPMOVMToVec64x4 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU64Masked256 x k) + +// Insert to zero of 32/64 bit floats and ints to a zero is just MOVS[SD] +(VPINSRQ128 [0] (Zero128 ) y) && y.Type.IsFloat() => (VMOVSDf2v y) +(VPINSRD128 [0] (Zero128 ) y) && y.Type.IsFloat() => (VMOVSSf2v y) +(VPINSRQ128 [0] (Zero128 ) y) && !y.Type.IsFloat() => (VMOVQ y) +(VPINSRD128 [0] (Zero128 ) y) && !y.Type.IsFloat() => (VMOVD y) + +// These rewrites can skip zero-extending the 8/16-bit inputs because they are +// only used as the input to a broadcast; the potentially "bad" bits are ignored +(VPBROADCASTB(128|256|512) x:(VPINSRB128 [0] (Zero128 ) y)) && x.Uses == 1 => + (VPBROADCASTB(128|256|512) (VMOVQ y)) +(VPBROADCASTW(128|256|512) x:(VPINSRW128 [0] (Zero128 ) y)) && x.Uses == 1 => + (VPBROADCASTW(128|256|512) (VMOVQ y)) + +(VMOVQ x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (VMOVQload [off] {sym} ptr mem) +(VMOVD x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (VMOVDload [off] {sym} ptr mem) + +(VMOVSDf2v x:(MOVSDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (VMOVSDload [off] {sym} ptr mem) +(VMOVSSf2v x:(MOVSSload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (VMOVSSload [off] {sym} ptr mem) + +(VMOVSDf2v x:(MOVSDconst [c] )) => (VMOVSDconst [c] ) +(VMOVSSf2v x:(MOVSSconst [c] )) => (VMOVSSconst [c] ) + +(VMOVDQUload(128|256|512) [off1] {sym} x:(ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) => (VMOVDQUload(128|256|512) [off1+off2] {sym} ptr mem) +(VMOVDQUstore(128|256|512) [off1] {sym} x:(ADDQconst [off2] ptr) val mem) && is32Bit(int64(off1)+int64(off2)) => (VMOVDQUstore(128|256|512) [off1+off2] {sym} ptr val mem) +(VMOVDQUload(128|256|512) [off1] {sym1} x:(LEAQ [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => (VMOVDQUload(128|256|512) [off1+off2] {mergeSym(sym1, sym2)} base mem) +(VMOVDQUstore(128|256|512) [off1] {sym1} x:(LEAQ [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => (VMOVDQUstore(128|256|512) [off1+off2] {mergeSym(sym1, sym2)} base val mem) + +// 2-op VPTEST optimizations +(SETEQ (VPTEST x:(VPAND(128|256) j k) y)) && x == y && x.Uses == 2 => (SETEQ (VPTEST j k)) +(SETEQ (VPTEST x:(VPAND(D|Q)512 j k) y)) && x == y && x.Uses == 2 => (SETEQ (VPTEST j k)) +(SETEQ (VPTEST x:(VPANDN(128|256) j k) y)) && x == y && x.Uses == 2 => (SETB (VPTEST k j)) // AndNot has swapped its operand order +(SETEQ (VPTEST x:(VPANDN(D|Q)512 j k) y)) && x == y && x.Uses == 2 => (SETB (VPTEST k j)) // AndNot has swapped its operand order +(EQ (VPTEST x:(VPAND(128|256) j k) y) yes no) && x == y && x.Uses == 2 => (EQ (VPTEST j k) yes no) +(EQ (VPTEST x:(VPAND(D|Q)512 j k) y) yes no) && x == y && x.Uses == 2 => (EQ (VPTEST j k) yes no) +(EQ (VPTEST x:(VPANDN(128|256) j k) y) yes no) && x == y && x.Uses == 2 => (ULT (VPTEST k j) yes no) // AndNot has swapped its operand order +(EQ (VPTEST x:(VPANDN(D|Q)512 j k) y) yes no) && x == y && x.Uses == 2 => (ULT (VPTEST k j) yes no) // AndNot has swapped its operand order + +// remove flags → bool → flags roundtrip +// Only do it if the flag generating instruction is local otherwise the likelihood flagalloc won't undo this optimization and makes things worse are slim. +(NE t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no) +(NE t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no) +(NE t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no) +(NE t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no) + +(CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) +(CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) +(CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) +(CMOVQNE yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) + +(CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) +(CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) +(CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) +(CMOVLNE yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) + +(CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) +(CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) +(CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) +(CMOVWNE yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags) + +(SETNE t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s +(SETNE t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s +(SETNE t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s +(SETNE t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => s + +(EQ t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no) +(EQ t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no) +(EQ t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no) +(EQ t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no) + +(CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) +(CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) +(CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) +(CMOVQEQ yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) + +(CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) +(CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) +(CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) +(CMOVLEQ yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) + +(CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) +(CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) +(CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) +(CMOVWEQ yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags) + +(SETEQ t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags) +(SETEQ t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags) +(SETEQ t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags) +(SETEQ t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags) diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go index e42b54398db1b1..c44fc679ad4636 100644 --- a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go +++ b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go @@ -62,7 +62,33 @@ var regNamesAMD64 = []string{ "X13", "X14", "X15", // constant 0 in ABIInternal - + "X16", + "X17", + "X18", + "X19", + "X20", + "X21", + "X22", + "X23", + "X24", + "X25", + "X26", + "X27", + "X28", + "X29", + "X30", + "X31", + + // TODO: update asyncPreempt for K registers. + // asyncPreempt also needs to store Z0-Z15 properly. + "K0", + "K1", + "K2", + "K3", + "K4", + "K5", + "K6", + "K7", // If you add registers, update asyncPreempt in runtime // pseudo-registers @@ -79,10 +105,10 @@ func init() { num[name] = i } buildReg := func(s string) regMask { - m := regMask(0) + m := regMask{} for _, r := range strings.Split(s, " ") { if n, ok := num[r]; ok { - m |= regMask(1) << uint(n) + m = m.addReg(uint(n)) continue } panic("register " + r + " not found") @@ -98,16 +124,28 @@ func init() { gp = buildReg("AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15") g = buildReg("g") fp = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14") + v = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14") + w = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31") x15 = buildReg("X15") - gpsp = gp | buildReg("SP") - gpspsb = gpsp | buildReg("SB") - gpspsbg = gpspsb | g - callerSave = gp | fp | g // runtime.setg (and anything calling it) may clobber g + mask = buildReg("K1 K2 K3 K4 K5 K6 K7") + gpsp = gp.union(buildReg("SP")) + gpspsb = gpsp.union(buildReg("SB")) + gpspsbg = gpspsb.union(g) + callerSave = gp.union(w).union(mask).union(g) // runtime.setg (and anything calling it) may clobber g + + vz = v.union(x15) + wz = w.union(x15) + x0 = buildReg("X0") ) // Common slices of register masks var ( - gponly = []regMask{gp} - fponly = []regMask{fp} + gponly = []regMask{gp} + fponly = []regMask{fp} + vonly = []regMask{v} + wonly = []regMask{w} + maskonly = []regMask{mask} + vzonly = []regMask{vz} + wzonly = []regMask{wz} ) // Common regInfo @@ -118,56 +156,124 @@ func init() { gp11sb = regInfo{inputs: []regMask{gpspsbg}, outputs: gponly} gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly} gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly} + gp21sp2 = regInfo{inputs: []regMask{gp, gpsp}, outputs: gponly} gp21sb = regInfo{inputs: []regMask{gpspsbg, gpsp}, outputs: gponly} gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}} - gp31shift = regInfo{inputs: []regMask{gp, gp, cx}, outputs: []regMask{gp}} - gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax, dx}} + gp11div = regInfo{inputs: []regMask{ax, gpsp.minus(dx)}, outputs: []regMask{ax, dx}} gp21hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx}, clobbers: ax} - gp21flags = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp, 0}} - gp2flags1flags = regInfo{inputs: []regMask{gp, gp, 0}, outputs: []regMask{gp, 0}} + gp21flags = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp, regMask{}}} + gp2flags1flags = regInfo{inputs: []regMask{gp, gp, regMask{}}, outputs: []regMask{gp, regMask{}}} gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}} gp1flags = regInfo{inputs: []regMask{gpsp}} - gp0flagsLoad = regInfo{inputs: []regMask{gpspsbg, 0}} - gp1flagsLoad = regInfo{inputs: []regMask{gpspsbg, gpsp, 0}} - gp2flagsLoad = regInfo{inputs: []regMask{gpspsbg, gpsp, gpsp, 0}} + gp0flagsLoad = regInfo{inputs: []regMask{gpspsbg, regMask{}}} + gp1flagsLoad = regInfo{inputs: []regMask{gpspsbg, gpsp, regMask{}}} + gp2flagsLoad = regInfo{inputs: []regMask{gpspsbg, gpsp, gpsp, regMask{}}} flagsgp = regInfo{inputs: nil, outputs: gponly} - gp11flags = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp, 0}} - gp1flags1flags = regInfo{inputs: []regMask{gp, 0}, outputs: []regMask{gp, 0}} + gp11flags = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp, regMask{}}} + gp1flags1flags = regInfo{inputs: []regMask{gp, regMask{}}, outputs: []regMask{gp, regMask{}}} readflags = regInfo{inputs: nil, outputs: gponly} - gpload = regInfo{inputs: []regMask{gpspsbg, 0}, outputs: gponly} - gp21load = regInfo{inputs: []regMask{gp, gpspsbg, 0}, outputs: gponly} - gploadidx = regInfo{inputs: []regMask{gpspsbg, gpsp, 0}, outputs: gponly} - gp21loadidx = regInfo{inputs: []regMask{gp, gpspsbg, gpsp, 0}, outputs: gponly} - gp21shxload = regInfo{inputs: []regMask{gpspsbg, gp, 0}, outputs: gponly} - gp21shxloadidx = regInfo{inputs: []regMask{gpspsbg, gpsp, gp, 0}, outputs: gponly} - - gpstore = regInfo{inputs: []regMask{gpspsbg, gpsp, 0}} - gpstoreconst = regInfo{inputs: []regMask{gpspsbg, 0}} - gpstoreidx = regInfo{inputs: []regMask{gpspsbg, gpsp, gpsp, 0}} - gpstoreconstidx = regInfo{inputs: []regMask{gpspsbg, gpsp, 0}} - gpstorexchg = regInfo{inputs: []regMask{gp, gpspsbg, 0}, outputs: []regMask{gp}} - cmpxchg = regInfo{inputs: []regMask{gp, ax, gp, 0}, outputs: []regMask{gp, 0}, clobbers: ax} - atomicLogic = regInfo{inputs: []regMask{gp &^ ax, gp &^ ax, 0}, outputs: []regMask{ax, 0}} + gpload = regInfo{inputs: []regMask{gpspsbg, regMask{}}, outputs: gponly} + gp21load = regInfo{inputs: []regMask{gp, gpspsbg, regMask{}}, outputs: gponly} + gploadidx = regInfo{inputs: []regMask{gpspsbg, gpsp, regMask{}}, outputs: gponly} + gp21loadidx = regInfo{inputs: []regMask{gp, gpspsbg, gpsp, regMask{}}, outputs: gponly} + gp21shxload = regInfo{inputs: []regMask{gpspsbg, gp, regMask{}}, outputs: gponly} + gp21shxloadidx = regInfo{inputs: []regMask{gpspsbg, gpsp, gp, regMask{}}, outputs: gponly} + + gpstore = regInfo{inputs: []regMask{gpspsbg, gpsp, regMask{}}} + gpstoreconst = regInfo{inputs: []regMask{gpspsbg, regMask{}}} + gpstoreidx = regInfo{inputs: []regMask{gpspsbg, gpsp, gpsp, regMask{}}} + gpstoreconstidx = regInfo{inputs: []regMask{gpspsbg, gpsp, regMask{}}} + gpstorexchg = regInfo{inputs: []regMask{gp, gpspsbg, regMask{}}, outputs: []regMask{gp}} + cmpxchg = regInfo{inputs: []regMask{gp, ax, gp, regMask{}}, outputs: []regMask{gp, regMask{}}, clobbers: ax} + atomicLogic = regInfo{inputs: []regMask{gp.minus(ax), gp.minus(ax), regMask{}}, outputs: []regMask{ax, regMask{}}} fp01 = regInfo{inputs: nil, outputs: fponly} fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly} fp31 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly} - fp21load = regInfo{inputs: []regMask{fp, gpspsbg, 0}, outputs: fponly} - fp21loadidx = regInfo{inputs: []regMask{fp, gpspsbg, gpspsb, 0}, outputs: fponly} + fp21load = regInfo{inputs: []regMask{fp, gpspsbg, regMask{}}, outputs: fponly} + fp21loadidx = regInfo{inputs: []regMask{fp, gpspsbg, gpspsb, regMask{}}, outputs: fponly} fpgp = regInfo{inputs: fponly, outputs: gponly} gpfp = regInfo{inputs: gponly, outputs: fponly} fp11 = regInfo{inputs: fponly, outputs: fponly} fp2flags = regInfo{inputs: []regMask{fp, fp}} - fpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: fponly} - fploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: fponly} - - fpstore = regInfo{inputs: []regMask{gpspsb, fp, 0}} - fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, 0}} + fpload = regInfo{inputs: []regMask{gpspsb, {}}, outputs: fponly} + fploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, {}}, outputs: fponly} + vload = regInfo{inputs: []regMask{gpspsb, {}}, outputs: vonly} + wload = regInfo{inputs: []regMask{gpspsb, {}}, outputs: wonly} + + fpstore = regInfo{inputs: []regMask{gpspsb, fp, {}}} + fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, {}}} + vstore = regInfo{inputs: []regMask{gpspsb, vz, {}}} + wstore = regInfo{inputs: []regMask{gpspsb, wz, {}}} + + // masked loads/stores, vector register or mask register + vloadv = regInfo{inputs: []regMask{gpspsb, v, {}}, outputs: vonly} + vstorev = regInfo{inputs: []regMask{gpspsb, v, vz, {}}} + wloadk = regInfo{inputs: []regMask{gpspsb, mask, {}}, outputs: wonly} + wstorek = regInfo{inputs: []regMask{gpspsb, mask, wz, {}}} + + v01 = regInfo{inputs: nil, outputs: vonly} + v11 = regInfo{inputs: vonly, outputs: vonly} // used in resultInArg0 ops, arg0 must not be x15 + v21 = regInfo{inputs: []regMask{v, vz}, outputs: vonly} // used in resultInArg0 ops, arg0 must not be x15 + vk = regInfo{inputs: vzonly, outputs: maskonly} + kv = regInfo{inputs: maskonly, outputs: vonly} + v2k = regInfo{inputs: []regMask{vz, vz}, outputs: maskonly} + vkv = regInfo{inputs: []regMask{vz, mask}, outputs: vonly} + v2kv = regInfo{inputs: []regMask{vz, vz, mask}, outputs: vonly} + v2kk = regInfo{inputs: []regMask{vz, vz, mask}, outputs: maskonly} + v31 = regInfo{inputs: []regMask{v, vz, vz}, outputs: vonly} // used in resultInArg0 ops, arg0 must not be x15 + v3kv = regInfo{inputs: []regMask{v, vz, vz, mask}, outputs: vonly} // used in resultInArg0 ops, arg0 must not be x15 + vgpv = regInfo{inputs: []regMask{vz, gp}, outputs: vonly} + vgp = regInfo{inputs: vonly, outputs: gponly} + vfpv = regInfo{inputs: []regMask{vz, fp}, outputs: vonly} + vfpkv = regInfo{inputs: []regMask{vz, fp, mask}, outputs: vonly} + fpv = regInfo{inputs: []regMask{fp}, outputs: vonly} + gpv = regInfo{inputs: []regMask{gp}, outputs: vonly} + v2flags = regInfo{inputs: []regMask{vz, vz}} + + w01 = regInfo{inputs: nil, outputs: wonly} + w11 = regInfo{inputs: wonly, outputs: wonly} // used in resultInArg0 ops, arg0 must not be x15 + w21 = regInfo{inputs: []regMask{wz, wz}, outputs: wonly} + wk = regInfo{inputs: wzonly, outputs: maskonly} + kw = regInfo{inputs: maskonly, outputs: wonly} + w2k = regInfo{inputs: []regMask{wz, wz}, outputs: maskonly} + wkw = regInfo{inputs: []regMask{wz, mask}, outputs: wonly} + w2kw = regInfo{inputs: []regMask{w, wz, mask}, outputs: wonly} // used in resultInArg0 ops, arg0 must not be x15 + w2kk = regInfo{inputs: []regMask{wz, wz, mask}, outputs: maskonly} + w31 = regInfo{inputs: []regMask{w, wz, wz}, outputs: wonly} // used in resultInArg0 ops, arg0 must not be x15 + w3kw = regInfo{inputs: []regMask{w, wz, wz, mask}, outputs: wonly} // used in resultInArg0 ops, arg0 must not be x15 + wgpw = regInfo{inputs: []regMask{wz, gp}, outputs: wonly} + wgp = regInfo{inputs: wzonly, outputs: gponly} + wfpw = regInfo{inputs: []regMask{wz, fp}, outputs: wonly} + wfpkw = regInfo{inputs: []regMask{wz, fp, mask}, outputs: wonly} + + // These register masks are used by SIMD only, they follow the pattern: + // Mem last, k mask second to last (if any), address right before mem and k mask. + wkwload = regInfo{inputs: []regMask{gpspsb, mask, regMask{}}, outputs: wonly} + v21load = regInfo{inputs: []regMask{v, gpspsb, regMask{}}, outputs: vonly} // used in resultInArg0 ops, arg0 must not be x15 + v31load = regInfo{inputs: []regMask{v, vz, gpspsb, regMask{}}, outputs: vonly} // used in resultInArg0 ops, arg0 must not be x15 + v11load = regInfo{inputs: []regMask{gpspsb, regMask{}}, outputs: vonly} + w21load = regInfo{inputs: []regMask{wz, gpspsb, regMask{}}, outputs: wonly} + w31load = regInfo{inputs: []regMask{w, wz, gpspsb, regMask{}}, outputs: wonly} // used in resultInArg0 ops, arg0 must not be x15 + w2kload = regInfo{inputs: []regMask{wz, gpspsb, regMask{}}, outputs: maskonly} + w2kwload = regInfo{inputs: []regMask{wz, gpspsb, mask, regMask{}}, outputs: wonly} + w11load = regInfo{inputs: []regMask{gpspsb, regMask{}}, outputs: wonly} + w3kwload = regInfo{inputs: []regMask{w, wz, gpspsb, mask, regMask{}}, outputs: wonly} // used in resultInArg0 ops, arg0 must not be x15 + w2kkload = regInfo{inputs: []regMask{wz, gpspsb, mask, regMask{}}, outputs: maskonly} + v31x0AtIn2 = regInfo{inputs: []regMask{v, vz, x0}, outputs: vonly} // used in resultInArg0 ops, arg0 must not be x15 + + kload = regInfo{inputs: []regMask{gpspsb, regMask{}}, outputs: maskonly} + kstore = regInfo{inputs: []regMask{gpspsb, mask, regMask{}}} + gpk = regInfo{inputs: gponly, outputs: maskonly} + kgp = regInfo{inputs: maskonly, outputs: gponly} + k2k = regInfo{inputs: []regMask{mask, mask}, outputs: maskonly} + + x15only = regInfo{inputs: nil, outputs: []regMask{x15}} prefreg = regInfo{inputs: []regMask{gpspsbg}} ) @@ -176,106 +282,106 @@ func init() { // {ADD,SUB,MUL,DIV}Sx: floating-point arithmetic // x==S for float32, x==D for float64 // computes arg0 OP arg1 - {name: "ADDSS", argLength: 2, reg: fp21, asm: "ADDSS", commutative: true, resultInArg0: true}, - {name: "ADDSD", argLength: 2, reg: fp21, asm: "ADDSD", commutative: true, resultInArg0: true}, - {name: "SUBSS", argLength: 2, reg: fp21, asm: "SUBSS", resultInArg0: true}, - {name: "SUBSD", argLength: 2, reg: fp21, asm: "SUBSD", resultInArg0: true}, - {name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true}, - {name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true}, - {name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true}, - {name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true}, + {name: "ADDSS", argLength: 2, reg: fp21, asm: "ADDSS", commutative: true, resultInArg0: true, earlyOk: true}, + {name: "ADDSD", argLength: 2, reg: fp21, asm: "ADDSD", commutative: true, resultInArg0: true, earlyOk: true}, + {name: "SUBSS", argLength: 2, reg: fp21, asm: "SUBSS", resultInArg0: true, earlyOk: true}, + {name: "SUBSD", argLength: 2, reg: fp21, asm: "SUBSD", resultInArg0: true, earlyOk: true}, + {name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true, earlyOk: true}, + {name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true, earlyOk: true}, + {name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true, earlyOk: true}, + {name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true, earlyOk: true}, // MOVSxload: floating-point loads // x==S for float32, x==D for float64 // load from arg0+auxint+aux, arg1 = mem - {name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, - {name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, + {name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, + {name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // MOVSxconst: floatint-point constants // x==S for float32, x==D for float64 - {name: "MOVSSconst", reg: fp01, asm: "MOVSS", aux: "Float32", rematerializeable: true}, - {name: "MOVSDconst", reg: fp01, asm: "MOVSD", aux: "Float64", rematerializeable: true}, + {name: "MOVSSconst", reg: fp01, asm: "MOVSS", aux: "Float32", rematerializeable: true, earlyOk: true}, + {name: "MOVSDconst", reg: fp01, asm: "MOVSD", aux: "Float64", rematerializeable: true, earlyOk: true}, // MOVSxloadidx: floating-point indexed loads // x==S for float32, x==D for float64 // load from arg0 + scale*arg1+auxint+aux, arg2 = mem - {name: "MOVSSloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSS", scale: 1, aux: "SymOff", symEffect: "Read"}, - {name: "MOVSSloadidx4", argLength: 3, reg: fploadidx, asm: "MOVSS", scale: 4, aux: "SymOff", symEffect: "Read"}, - {name: "MOVSDloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSD", scale: 1, aux: "SymOff", symEffect: "Read"}, - {name: "MOVSDloadidx8", argLength: 3, reg: fploadidx, asm: "MOVSD", scale: 8, aux: "SymOff", symEffect: "Read"}, + {name: "MOVSSloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSS", scale: 1, aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, + {name: "MOVSSloadidx4", argLength: 3, reg: fploadidx, asm: "MOVSS", scale: 4, aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, + {name: "MOVSDloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSD", scale: 1, aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, + {name: "MOVSDloadidx8", argLength: 3, reg: fploadidx, asm: "MOVSD", scale: 8, aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, // MOVSxstore: floating-point stores // x==S for float32, x==D for float64 // does *(arg0+auxint+aux) = arg1, arg2 = mem - {name: "MOVSSstore", argLength: 3, reg: fpstore, asm: "MOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, - {name: "MOVSDstore", argLength: 3, reg: fpstore, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, + {name: "MOVSSstore", argLength: 3, reg: fpstore, asm: "MOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, + {name: "MOVSDstore", argLength: 3, reg: fpstore, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // MOVSxstoreidx: floating-point indexed stores // x==S for float32, x==D for float64 // does *(arg0+scale*arg1+auxint+aux) = arg2, arg3 = mem - {name: "MOVSSstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSS", scale: 1, aux: "SymOff", symEffect: "Write"}, - {name: "MOVSSstoreidx4", argLength: 4, reg: fpstoreidx, asm: "MOVSS", scale: 4, aux: "SymOff", symEffect: "Write"}, - {name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", scale: 1, aux: "SymOff", symEffect: "Write"}, - {name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", scale: 8, aux: "SymOff", symEffect: "Write"}, + {name: "MOVSSstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSS", scale: 1, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, + {name: "MOVSSstoreidx4", argLength: 4, reg: fpstoreidx, asm: "MOVSS", scale: 4, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, + {name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", scale: 1, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, + {name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", scale: 8, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // {ADD,SUB,MUL,DIV}Sxload: floating-point load / op combo // x==S for float32, x==D for float64 // computes arg0 OP *(arg1+auxint+aux), arg2=mem - {name: "ADDSSload", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, - {name: "ADDSDload", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, - {name: "SUBSSload", argLength: 3, reg: fp21load, asm: "SUBSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, - {name: "SUBSDload", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, - {name: "MULSSload", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, - {name: "MULSDload", argLength: 3, reg: fp21load, asm: "MULSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, - {name: "DIVSSload", argLength: 3, reg: fp21load, asm: "DIVSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, - {name: "DIVSDload", argLength: 3, reg: fp21load, asm: "DIVSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, + {name: "ADDSSload", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, + {name: "ADDSDload", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, + {name: "SUBSSload", argLength: 3, reg: fp21load, asm: "SUBSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, + {name: "SUBSDload", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, + {name: "MULSSload", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, + {name: "MULSDload", argLength: 3, reg: fp21load, asm: "MULSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, + {name: "DIVSSload", argLength: 3, reg: fp21load, asm: "DIVSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, + {name: "DIVSDload", argLength: 3, reg: fp21load, asm: "DIVSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // {ADD,SUB,MUL,DIV}Sxloadidx: floating-point indexed load / op combo // x==S for float32, x==D for float64 // computes arg0 OP *(arg1+scale*arg2+auxint+aux), arg3=mem - {name: "ADDSSloadidx1", argLength: 4, reg: fp21loadidx, asm: "ADDSS", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "ADDSSloadidx4", argLength: 4, reg: fp21loadidx, asm: "ADDSS", scale: 4, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "ADDSDloadidx1", argLength: 4, reg: fp21loadidx, asm: "ADDSD", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "ADDSDloadidx8", argLength: 4, reg: fp21loadidx, asm: "ADDSD", scale: 8, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "SUBSSloadidx1", argLength: 4, reg: fp21loadidx, asm: "SUBSS", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "SUBSSloadidx4", argLength: 4, reg: fp21loadidx, asm: "SUBSS", scale: 4, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "SUBSDloadidx1", argLength: 4, reg: fp21loadidx, asm: "SUBSD", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "SUBSDloadidx8", argLength: 4, reg: fp21loadidx, asm: "SUBSD", scale: 8, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "MULSSloadidx1", argLength: 4, reg: fp21loadidx, asm: "MULSS", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "MULSSloadidx4", argLength: 4, reg: fp21loadidx, asm: "MULSS", scale: 4, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "MULSDloadidx1", argLength: 4, reg: fp21loadidx, asm: "MULSD", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "MULSDloadidx8", argLength: 4, reg: fp21loadidx, asm: "MULSD", scale: 8, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "DIVSSloadidx1", argLength: 4, reg: fp21loadidx, asm: "DIVSS", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "DIVSSloadidx4", argLength: 4, reg: fp21loadidx, asm: "DIVSS", scale: 4, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "DIVSDloadidx1", argLength: 4, reg: fp21loadidx, asm: "DIVSD", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, - {name: "DIVSDloadidx8", argLength: 4, reg: fp21loadidx, asm: "DIVSD", scale: 8, aux: "SymOff", resultInArg0: true, symEffect: "Read"}, + {name: "ADDSSloadidx1", argLength: 4, reg: fp21loadidx, asm: "ADDSS", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "ADDSSloadidx4", argLength: 4, reg: fp21loadidx, asm: "ADDSS", scale: 4, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "ADDSDloadidx1", argLength: 4, reg: fp21loadidx, asm: "ADDSD", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "ADDSDloadidx8", argLength: 4, reg: fp21loadidx, asm: "ADDSD", scale: 8, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "SUBSSloadidx1", argLength: 4, reg: fp21loadidx, asm: "SUBSS", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "SUBSSloadidx4", argLength: 4, reg: fp21loadidx, asm: "SUBSS", scale: 4, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "SUBSDloadidx1", argLength: 4, reg: fp21loadidx, asm: "SUBSD", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "SUBSDloadidx8", argLength: 4, reg: fp21loadidx, asm: "SUBSD", scale: 8, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "MULSSloadidx1", argLength: 4, reg: fp21loadidx, asm: "MULSS", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "MULSSloadidx4", argLength: 4, reg: fp21loadidx, asm: "MULSS", scale: 4, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "MULSDloadidx1", argLength: 4, reg: fp21loadidx, asm: "MULSD", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "MULSDloadidx8", argLength: 4, reg: fp21loadidx, asm: "MULSD", scale: 8, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "DIVSSloadidx1", argLength: 4, reg: fp21loadidx, asm: "DIVSS", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "DIVSSloadidx4", argLength: 4, reg: fp21loadidx, asm: "DIVSS", scale: 4, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "DIVSDloadidx1", argLength: 4, reg: fp21loadidx, asm: "DIVSD", scale: 1, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, + {name: "DIVSDloadidx8", argLength: 4, reg: fp21loadidx, asm: "DIVSD", scale: 8, aux: "SymOff", resultInArg0: true, symEffect: "Read", addrSinkArg1: true}, // {ADD,SUB,MUL,DIV,AND,OR,XOR}x: binary integer ops // unadorned versions compute arg0 OP arg1 // const versions compute arg0 OP auxint (auxint is a sign-extended 32-bit value) // constmodify versions compute *(arg0+ValAndOff(AuxInt).Off().aux) OP= ValAndOff(AuxInt).Val(), arg1 = mem // x==L operations zero the upper 4 bytes of the destination register (not meaningful for constmodify versions). - {name: "ADDQ", argLength: 2, reg: gp21sp, asm: "ADDQ", commutative: true, clobberFlags: true}, - {name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true, clobberFlags: true}, - {name: "ADDQconst", argLength: 1, reg: gp11sp, asm: "ADDQ", aux: "Int32", typ: "UInt64", clobberFlags: true}, - {name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", clobberFlags: true}, - {name: "ADDQconstmodify", argLength: 2, reg: gpstoreconst, asm: "ADDQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, - {name: "ADDLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ADDL", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, - - {name: "SUBQ", argLength: 2, reg: gp21, asm: "SUBQ", resultInArg0: true, clobberFlags: true}, - {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true, clobberFlags: true}, - {name: "SUBQconst", argLength: 1, reg: gp11, asm: "SUBQ", aux: "Int32", resultInArg0: true, clobberFlags: true}, - {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32", resultInArg0: true, clobberFlags: true}, - - {name: "MULQ", argLength: 2, reg: gp21, asm: "IMULQ", commutative: true, resultInArg0: true, clobberFlags: true}, - {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL", commutative: true, resultInArg0: true, clobberFlags: true}, - {name: "MULQconst", argLength: 1, reg: gp11, asm: "IMUL3Q", aux: "Int32", clobberFlags: true}, - {name: "MULLconst", argLength: 1, reg: gp11, asm: "IMUL3L", aux: "Int32", clobberFlags: true}, + {name: "ADDQ", argLength: 2, reg: gp21sp, asm: "ADDQ", commutative: true, clobberFlags: true, earlyOk: true}, + {name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true, clobberFlags: true, earlyOk: true}, + {name: "ADDQconst", argLength: 1, reg: gp11sp, asm: "ADDQ", aux: "Int32", typ: "UInt64", clobberFlags: true, earlyOk: true}, + {name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", clobberFlags: true, earlyOk: true}, + {name: "ADDQconstmodify", argLength: 2, reg: gpstoreconst, asm: "ADDQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, + {name: "ADDLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ADDL", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, + + {name: "SUBQ", argLength: 2, reg: gp21sp2, asm: "SUBQ", resultInArg0: true, clobberFlags: true, earlyOk: true}, + {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true, clobberFlags: true, earlyOk: true}, + {name: "SUBQconst", argLength: 1, reg: gp11, asm: "SUBQ", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, + {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, + + {name: "MULQ", argLength: 2, reg: gp21, asm: "IMULQ", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, + {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, + {name: "MULQconst", argLength: 1, reg: gp11, asm: "IMUL3Q", aux: "Int32", clobberFlags: true, earlyOk: true}, + {name: "MULLconst", argLength: 1, reg: gp11, asm: "IMUL3L", aux: "Int32", clobberFlags: true, earlyOk: true}, // Let x = arg0*arg1 (full 32x32->64 unsigned multiply). Returns uint32(x), and flags set to overflow if uint32(x) != x. - {name: "MULLU", argLength: 2, reg: regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{ax, 0}, clobbers: dx}, typ: "(UInt32,Flags)", asm: "MULL", commutative: true, clobberFlags: true}, + {name: "MULLU", argLength: 2, reg: regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{ax, regMask{}}, clobbers: dx}, typ: "(UInt32,Flags)", asm: "MULL", commutative: true, clobberFlags: true}, // Let x = arg0*arg1 (full 64x64->128 unsigned multiply). Returns uint64(x), and flags set to overflow if uint64(x) != x. - {name: "MULQU", argLength: 2, reg: regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{ax, 0}, clobbers: dx}, typ: "(UInt64,Flags)", asm: "MULQ", commutative: true, clobberFlags: true}, + {name: "MULQU", argLength: 2, reg: regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{ax, regMask{}}, clobbers: dx}, typ: "(UInt64,Flags)", asm: "MULQ", commutative: true, clobberFlags: true}, // HMULx[U]: computes the high bits of an integer multiply. // computes arg0 * arg1 >> (x==L?32:64) @@ -283,13 +389,13 @@ func init() { // HMULx[U] are intentionally not marked as commutative, even though they are. // This is because they have asymmetric register requirements. // There are rewrite rules to try to place arguments in preferable slots. - {name: "HMULQ", argLength: 2, reg: gp21hmul, asm: "IMULQ", clobberFlags: true}, - {name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL", clobberFlags: true}, - {name: "HMULQU", argLength: 2, reg: gp21hmul, asm: "MULQ", clobberFlags: true}, - {name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL", clobberFlags: true}, + {name: "HMULQ", argLength: 2, reg: gp21hmul, asm: "IMULQ", clobberFlags: true, earlyOk: true}, + {name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL", clobberFlags: true, earlyOk: true}, + {name: "HMULQU", argLength: 2, reg: gp21hmul, asm: "MULQ", clobberFlags: true, earlyOk: true}, + {name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL", clobberFlags: true, earlyOk: true}, // (arg0 + arg1) / 2 as unsigned, all 64 result bits - {name: "AVGQU", argLength: 2, reg: gp21, commutative: true, resultInArg0: true, clobberFlags: true}, + {name: "AVGQU", argLength: 2, reg: gp21, commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // DIVx[U] computes [arg0 / arg1, arg0 % arg1] // For signed versions, AuxInt non-zero means that the divisor has been proved to be not -1. @@ -322,29 +428,29 @@ func init() { {name: "SUBQconstborrow", argLength: 1, reg: gp11flags, typ: "(UInt64,Flags)", asm: "SUBQ", aux: "Int32", resultInArg0: true}, // r = arg0-auxint {name: "SBBQconst", argLength: 2, reg: gp1flags1flags, typ: "(UInt64,Flags)", asm: "SBBQ", aux: "Int32", resultInArg0: true}, // r = arg0-(auxint+carry(arg1)) - {name: "MULQU2", argLength: 2, reg: regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx, ax}}, commutative: true, asm: "MULQ", clobberFlags: true}, // arg0 * arg1, returns (hi, lo) - {name: "DIVQU2", argLength: 3, reg: regInfo{inputs: []regMask{dx, ax, gpsp}, outputs: []regMask{ax, dx}}, asm: "DIVQ", clobberFlags: true}, // arg0:arg1 / arg2 (128-bit divided by 64-bit), returns (q, r) - - {name: "ANDQ", argLength: 2, reg: gp21, asm: "ANDQ", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 & arg1 - {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 & arg1 - {name: "ANDQconst", argLength: 1, reg: gp11, asm: "ANDQ", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 & auxint - {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 & auxint - {name: "ANDQconstmodify", argLength: 2, reg: gpstoreconst, asm: "ANDQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // and ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem - {name: "ANDLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ANDL", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // and ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem - - {name: "ORQ", argLength: 2, reg: gp21, asm: "ORQ", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 | arg1 - {name: "ORL", argLength: 2, reg: gp21, asm: "ORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 | arg1 - {name: "ORQconst", argLength: 1, reg: gp11, asm: "ORQ", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 | auxint - {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 | auxint - {name: "ORQconstmodify", argLength: 2, reg: gpstoreconst, asm: "ORQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // or ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem - {name: "ORLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ORL", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // or ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem - - {name: "XORQ", argLength: 2, reg: gp21, asm: "XORQ", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 ^ arg1 - {name: "XORL", argLength: 2, reg: gp21, asm: "XORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 ^ arg1 - {name: "XORQconst", argLength: 1, reg: gp11, asm: "XORQ", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint - {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint - {name: "XORQconstmodify", argLength: 2, reg: gpstoreconst, asm: "XORQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // xor ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem - {name: "XORLconstmodify", argLength: 2, reg: gpstoreconst, asm: "XORL", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // xor ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem + {name: "MULQU2", argLength: 2, reg: regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx, ax}}, commutative: true, asm: "MULQ", clobberFlags: true, earlyOk: true}, // arg0 * arg1, returns (hi, lo) + {name: "DIVQU2", argLength: 3, reg: regInfo{inputs: []regMask{dx, ax, gpsp}, outputs: []regMask{ax, dx}}, asm: "DIVQ", clobberFlags: true}, // arg0:arg1 / arg2 (128-bit divided by 64-bit), returns (q, r) + + {name: "ANDQ", argLength: 2, reg: gp21, asm: "ANDQ", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDQconst", argLength: 1, reg: gp11, asm: "ANDQ", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 & auxint + {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 & auxint + {name: "ANDQconstmodify", argLength: 2, reg: gpstoreconst, asm: "ANDQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // and ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem + {name: "ANDLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ANDL", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // and ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem + + {name: "ORQ", argLength: 2, reg: gp21, asm: "ORQ", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 | arg1 + {name: "ORL", argLength: 2, reg: gp21, asm: "ORL", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 | arg1 + {name: "ORQconst", argLength: 1, reg: gp11, asm: "ORQ", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 | auxint + {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 | auxint + {name: "ORQconstmodify", argLength: 2, reg: gpstoreconst, asm: "ORQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // or ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem + {name: "ORLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ORL", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // or ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem + + {name: "XORQ", argLength: 2, reg: gp21, asm: "XORQ", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 ^ arg1 + {name: "XORL", argLength: 2, reg: gp21, asm: "XORL", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 ^ arg1 + {name: "XORQconst", argLength: 1, reg: gp11, asm: "XORQ", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 ^ auxint + {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 ^ auxint + {name: "XORQconstmodify", argLength: 2, reg: gpstoreconst, asm: "XORQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // xor ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem + {name: "XORLconstmodify", argLength: 2, reg: gpstoreconst, asm: "XORL", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // xor ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem // CMPx: compare arg0 to arg1. {name: "CMPQ", argLength: 2, reg: gp2flags, asm: "CMPQ", typ: "Flags"}, @@ -359,34 +465,34 @@ func init() { {name: "CMPBconst", argLength: 1, reg: gp1flags, asm: "CMPB", typ: "Flags", aux: "Int8"}, // CMPxload: compare *(arg0+auxint+aux) to arg1 (in that order). arg2=mem. - {name: "CMPQload", argLength: 3, reg: gp1flagsLoad, asm: "CMPQ", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, - {name: "CMPLload", argLength: 3, reg: gp1flagsLoad, asm: "CMPL", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, - {name: "CMPWload", argLength: 3, reg: gp1flagsLoad, asm: "CMPW", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, - {name: "CMPBload", argLength: 3, reg: gp1flagsLoad, asm: "CMPB", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, + {name: "CMPQload", argLength: 3, reg: gp1flagsLoad, asm: "CMPQ", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, + {name: "CMPLload", argLength: 3, reg: gp1flagsLoad, asm: "CMPL", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, + {name: "CMPWload", argLength: 3, reg: gp1flagsLoad, asm: "CMPW", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, + {name: "CMPBload", argLength: 3, reg: gp1flagsLoad, asm: "CMPB", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, // CMPxconstload: compare *(arg0+ValAndOff(AuxInt).Off()+aux) to ValAndOff(AuxInt).Val() (in that order). arg1=mem. - {name: "CMPQconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPQ", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, - {name: "CMPLconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPL", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, - {name: "CMPWconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPW", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, - {name: "CMPBconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPB", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true}, + {name: "CMPQconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPQ", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, + {name: "CMPLconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPL", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, + {name: "CMPWconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPW", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, + {name: "CMPBconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPB", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true, addrSinkArg0: true}, // CMPxloadidx: compare *(arg0+N*arg1+auxint+aux) to arg2 (in that order). arg3=mem. - {name: "CMPQloadidx8", argLength: 4, reg: gp2flagsLoad, asm: "CMPQ", scale: 8, aux: "SymOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPQloadidx1", argLength: 4, reg: gp2flagsLoad, asm: "CMPQ", scale: 1, commutative: true, aux: "SymOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPLloadidx4", argLength: 4, reg: gp2flagsLoad, asm: "CMPL", scale: 4, aux: "SymOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPLloadidx1", argLength: 4, reg: gp2flagsLoad, asm: "CMPL", scale: 1, commutative: true, aux: "SymOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPWloadidx2", argLength: 4, reg: gp2flagsLoad, asm: "CMPW", scale: 2, aux: "SymOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPWloadidx1", argLength: 4, reg: gp2flagsLoad, asm: "CMPW", scale: 1, commutative: true, aux: "SymOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPBloadidx1", argLength: 4, reg: gp2flagsLoad, asm: "CMPB", scale: 1, commutative: true, aux: "SymOff", typ: "Flags", symEffect: "Read"}, + {name: "CMPQloadidx8", argLength: 4, reg: gp2flagsLoad, asm: "CMPQ", scale: 8, aux: "SymOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true}, + {name: "CMPQloadidx1", argLength: 4, reg: gp2flagsLoad, asm: "CMPQ", scale: 1, commutative: true, aux: "SymOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, + {name: "CMPLloadidx4", argLength: 4, reg: gp2flagsLoad, asm: "CMPL", scale: 4, aux: "SymOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true}, + {name: "CMPLloadidx1", argLength: 4, reg: gp2flagsLoad, asm: "CMPL", scale: 1, commutative: true, aux: "SymOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, + {name: "CMPWloadidx2", argLength: 4, reg: gp2flagsLoad, asm: "CMPW", scale: 2, aux: "SymOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true}, + {name: "CMPWloadidx1", argLength: 4, reg: gp2flagsLoad, asm: "CMPW", scale: 1, commutative: true, aux: "SymOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, + {name: "CMPBloadidx1", argLength: 4, reg: gp2flagsLoad, asm: "CMPB", scale: 1, commutative: true, aux: "SymOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // CMPxconstloadidx: compare *(arg0+N*arg1+ValAndOff(AuxInt).Off()+aux) to ValAndOff(AuxInt).Val() (in that order). arg2=mem. - {name: "CMPQconstloadidx8", argLength: 3, reg: gp1flagsLoad, asm: "CMPQ", scale: 8, aux: "SymValAndOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPQconstloadidx1", argLength: 3, reg: gp1flagsLoad, asm: "CMPQ", scale: 1, commutative: true, aux: "SymValAndOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPLconstloadidx4", argLength: 3, reg: gp1flagsLoad, asm: "CMPL", scale: 4, aux: "SymValAndOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPLconstloadidx1", argLength: 3, reg: gp1flagsLoad, asm: "CMPL", scale: 1, commutative: true, aux: "SymValAndOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPWconstloadidx2", argLength: 3, reg: gp1flagsLoad, asm: "CMPW", scale: 2, aux: "SymValAndOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPWconstloadidx1", argLength: 3, reg: gp1flagsLoad, asm: "CMPW", scale: 1, commutative: true, aux: "SymValAndOff", typ: "Flags", symEffect: "Read"}, - {name: "CMPBconstloadidx1", argLength: 3, reg: gp1flagsLoad, asm: "CMPB", scale: 1, commutative: true, aux: "SymValAndOff", typ: "Flags", symEffect: "Read"}, + {name: "CMPQconstloadidx8", argLength: 3, reg: gp1flagsLoad, asm: "CMPQ", scale: 8, aux: "SymValAndOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true}, + {name: "CMPQconstloadidx1", argLength: 3, reg: gp1flagsLoad, asm: "CMPQ", scale: 1, commutative: true, aux: "SymValAndOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, + {name: "CMPLconstloadidx4", argLength: 3, reg: gp1flagsLoad, asm: "CMPL", scale: 4, aux: "SymValAndOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true}, + {name: "CMPLconstloadidx1", argLength: 3, reg: gp1flagsLoad, asm: "CMPL", scale: 1, commutative: true, aux: "SymValAndOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, + {name: "CMPWconstloadidx2", argLength: 3, reg: gp1flagsLoad, asm: "CMPW", scale: 2, aux: "SymValAndOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true}, + {name: "CMPWconstloadidx1", argLength: 3, reg: gp1flagsLoad, asm: "CMPW", scale: 1, commutative: true, aux: "SymValAndOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, + {name: "CMPBconstloadidx1", argLength: 3, reg: gp1flagsLoad, asm: "CMPB", scale: 1, commutative: true, aux: "SymValAndOff", typ: "Flags", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // UCOMISx: floating-point compare arg0 to arg1 // x==S for float32, x==D for float64 @@ -394,19 +500,19 @@ func init() { {name: "UCOMISD", argLength: 2, reg: fp2flags, asm: "UCOMISD", typ: "Flags"}, // bit test/set/clear operations - {name: "BTL", argLength: 2, reg: gp2flags, asm: "BTL", typ: "Flags"}, // test whether bit arg0%32 in arg1 is set - {name: "BTQ", argLength: 2, reg: gp2flags, asm: "BTQ", typ: "Flags"}, // test whether bit arg0%64 in arg1 is set - {name: "BTCL", argLength: 2, reg: gp21, asm: "BTCL", resultInArg0: true, clobberFlags: true}, // complement bit arg1%32 in arg0 - {name: "BTCQ", argLength: 2, reg: gp21, asm: "BTCQ", resultInArg0: true, clobberFlags: true}, // complement bit arg1%64 in arg0 - {name: "BTRL", argLength: 2, reg: gp21, asm: "BTRL", resultInArg0: true, clobberFlags: true}, // reset bit arg1%32 in arg0 - {name: "BTRQ", argLength: 2, reg: gp21, asm: "BTRQ", resultInArg0: true, clobberFlags: true}, // reset bit arg1%64 in arg0 - {name: "BTSL", argLength: 2, reg: gp21, asm: "BTSL", resultInArg0: true, clobberFlags: true}, // set bit arg1%32 in arg0 - {name: "BTSQ", argLength: 2, reg: gp21, asm: "BTSQ", resultInArg0: true, clobberFlags: true}, // set bit arg1%64 in arg0 - {name: "BTLconst", argLength: 1, reg: gp1flags, asm: "BTL", typ: "Flags", aux: "Int8"}, // test whether bit auxint in arg0 is set, 0 <= auxint < 32 - {name: "BTQconst", argLength: 1, reg: gp1flags, asm: "BTQ", typ: "Flags", aux: "Int8"}, // test whether bit auxint in arg0 is set, 0 <= auxint < 64 - {name: "BTCQconst", argLength: 1, reg: gp11, asm: "BTCQ", resultInArg0: true, clobberFlags: true, aux: "Int8"}, // complement bit auxint in arg0, 31 <= auxint < 64 - {name: "BTRQconst", argLength: 1, reg: gp11, asm: "BTRQ", resultInArg0: true, clobberFlags: true, aux: "Int8"}, // reset bit auxint in arg0, 31 <= auxint < 64 - {name: "BTSQconst", argLength: 1, reg: gp11, asm: "BTSQ", resultInArg0: true, clobberFlags: true, aux: "Int8"}, // set bit auxint in arg0, 31 <= auxint < 64 + {name: "BTL", argLength: 2, reg: gp2flags, asm: "BTL", typ: "Flags"}, // test whether bit arg0%32 in arg1 is set + {name: "BTQ", argLength: 2, reg: gp2flags, asm: "BTQ", typ: "Flags"}, // test whether bit arg0%64 in arg1 is set + {name: "BTCL", argLength: 2, reg: gp21, asm: "BTCL", resultInArg0: true, clobberFlags: true, earlyOk: true}, // complement bit arg1%32 in arg0 + {name: "BTCQ", argLength: 2, reg: gp21, asm: "BTCQ", resultInArg0: true, clobberFlags: true, earlyOk: true}, // complement bit arg1%64 in arg0 + {name: "BTRL", argLength: 2, reg: gp21, asm: "BTRL", resultInArg0: true, clobberFlags: true, earlyOk: true}, // reset bit arg1%32 in arg0 + {name: "BTRQ", argLength: 2, reg: gp21, asm: "BTRQ", resultInArg0: true, clobberFlags: true, earlyOk: true}, // reset bit arg1%64 in arg0 + {name: "BTSL", argLength: 2, reg: gp21, asm: "BTSL", resultInArg0: true, clobberFlags: true, earlyOk: true}, // set bit arg1%32 in arg0 + {name: "BTSQ", argLength: 2, reg: gp21, asm: "BTSQ", resultInArg0: true, clobberFlags: true, earlyOk: true}, // set bit arg1%64 in arg0 + {name: "BTLconst", argLength: 1, reg: gp1flags, asm: "BTL", typ: "Flags", aux: "Int8", earlyOk: true}, // test whether bit auxint in arg0 is set, 0 <= auxint < 32 + {name: "BTQconst", argLength: 1, reg: gp1flags, asm: "BTQ", typ: "Flags", aux: "Int8", earlyOk: true}, // test whether bit auxint in arg0 is set, 0 <= auxint < 64 + {name: "BTCQconst", argLength: 1, reg: gp11, asm: "BTCQ", resultInArg0: true, clobberFlags: true, aux: "Int8", earlyOk: true}, // complement bit auxint in arg0, 31 <= auxint < 64 + {name: "BTRQconst", argLength: 1, reg: gp11, asm: "BTRQ", resultInArg0: true, clobberFlags: true, aux: "Int8", earlyOk: true}, // reset bit auxint in arg0, 31 <= auxint < 64 + {name: "BTSQconst", argLength: 1, reg: gp11, asm: "BTSQ", resultInArg0: true, clobberFlags: true, aux: "Int8", earlyOk: true}, // set bit auxint in arg0, 31 <= auxint < 64 // BT[SRC]Qconstmodify // @@ -422,9 +528,9 @@ func init() { // // Note that there aren't non-const versions of these instructions. // Well, there are such instructions, but they are slow and weird so we don't use them. - {name: "BTSQconstmodify", argLength: 2, reg: gpstoreconst, asm: "BTSQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, - {name: "BTRQconstmodify", argLength: 2, reg: gpstoreconst, asm: "BTRQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, - {name: "BTCQconstmodify", argLength: 2, reg: gpstoreconst, asm: "BTCQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, + {name: "BTSQconstmodify", argLength: 2, reg: gpstoreconst, asm: "BTSQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, + {name: "BTRQconstmodify", argLength: 2, reg: gpstoreconst, asm: "BTRQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, + {name: "BTCQconstmodify", argLength: 2, reg: gpstoreconst, asm: "BTCQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write", addrSinkArg0: true}, // TESTx: compare (arg0 & arg1) to 0 {name: "TESTQ", argLength: 2, reg: gp2flags, commutative: true, asm: "TESTQ", typ: "Flags"}, @@ -446,33 +552,28 @@ func init() { // arg1 is the amount to shift, interpreted mod (Q=64,L=32,W=32,B=32) // (Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount!) // For *const versions, use auxint instead of arg1 as the shift amount. auxint must be in the range 0 to (Q=63,L=31,W=15,B=7) inclusive. - {name: "SHLQ", argLength: 2, reg: gp21shift, asm: "SHLQ", resultInArg0: true, clobberFlags: true}, - {name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL", resultInArg0: true, clobberFlags: true}, - {name: "SHLQconst", argLength: 1, reg: gp11, asm: "SHLQ", aux: "Int8", resultInArg0: true, clobberFlags: true}, - {name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int8", resultInArg0: true, clobberFlags: true}, - - {name: "SHRQ", argLength: 2, reg: gp21shift, asm: "SHRQ", resultInArg0: true, clobberFlags: true}, - {name: "SHRL", argLength: 2, reg: gp21shift, asm: "SHRL", resultInArg0: true, clobberFlags: true}, - {name: "SHRW", argLength: 2, reg: gp21shift, asm: "SHRW", resultInArg0: true, clobberFlags: true}, - {name: "SHRB", argLength: 2, reg: gp21shift, asm: "SHRB", resultInArg0: true, clobberFlags: true}, - {name: "SHRQconst", argLength: 1, reg: gp11, asm: "SHRQ", aux: "Int8", resultInArg0: true, clobberFlags: true}, - {name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int8", resultInArg0: true, clobberFlags: true}, - {name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int8", resultInArg0: true, clobberFlags: true}, - {name: "SHRBconst", argLength: 1, reg: gp11, asm: "SHRB", aux: "Int8", resultInArg0: true, clobberFlags: true}, - - {name: "SARQ", argLength: 2, reg: gp21shift, asm: "SARQ", resultInArg0: true, clobberFlags: true}, - {name: "SARL", argLength: 2, reg: gp21shift, asm: "SARL", resultInArg0: true, clobberFlags: true}, - {name: "SARW", argLength: 2, reg: gp21shift, asm: "SARW", resultInArg0: true, clobberFlags: true}, - {name: "SARB", argLength: 2, reg: gp21shift, asm: "SARB", resultInArg0: true, clobberFlags: true}, - {name: "SARQconst", argLength: 1, reg: gp11, asm: "SARQ", aux: "Int8", resultInArg0: true, clobberFlags: true}, - {name: "SARLconst", argLength: 1, reg: gp11, asm: "SARL", aux: "Int8", resultInArg0: true, clobberFlags: true}, - {name: "SARWconst", argLength: 1, reg: gp11, asm: "SARW", aux: "Int8", resultInArg0: true, clobberFlags: true}, - {name: "SARBconst", argLength: 1, reg: gp11, asm: "SARB", aux: "Int8", resultInArg0: true, clobberFlags: true}, - - // unsigned arg0 >> arg2, shifting in bits from arg1 (==(arg1<<64+arg0)>>arg2, keeping low 64 bits), shift amount is mod 64 - {name: "SHRDQ", argLength: 3, reg: gp31shift, asm: "SHRQ", resultInArg0: true, clobberFlags: true}, - // unsigned arg0 << arg2, shifting in bits from arg1 (==(arg0<<64+arg1)< hgfedcba // L: abcdefgh -> 0000hgfe (L zeros the upper 4 bytes) - {name: "BSWAPQ", argLength: 1, reg: gp11, asm: "BSWAPQ", resultInArg0: true}, - {name: "BSWAPL", argLength: 1, reg: gp11, asm: "BSWAPL", resultInArg0: true}, + {name: "BSWAPQ", argLength: 1, reg: gp11, asm: "BSWAPQ", resultInArg0: true, earlyOk: true}, + {name: "BSWAPL", argLength: 1, reg: gp11, asm: "BSWAPL", resultInArg0: true, earlyOk: true}, // POPCNTx counts the number of set bits in the low-order (L=32,Q=64) bits of arg0. // POPCNTx instructions are only guaranteed to be available if GOAMD64>=v2. @@ -687,8 +788,8 @@ func init() { // SQRTSx computes sqrt(arg0) // S = float32, D = float64 - {name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD"}, - {name: "SQRTSS", argLength: 1, reg: fp11, asm: "SQRTSS"}, + {name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD", earlyOk: true}, + {name: "SQRTSS", argLength: 1, reg: fp11, asm: "SQRTSS", earlyOk: true}, // ROUNDSD rounds arg0 to an integer depending on auxint // 0 means math.RoundToEven, 1 means math.Floor, 2 math.Ceil, 3 math.Trunc @@ -696,9 +797,10 @@ func init() { // ROUNDSD instruction is only guaraneteed to be available if GOAMD64>=v2. // For GOAMD64=v3. @@ -710,156 +812,156 @@ func init() { // Note that these operations don't exactly match the semantics of Go's // builtin min. In particular, these aren't commutative, because on various // special cases the 2nd argument is preferred. - {name: "MINSD", argLength: 2, reg: fp21, resultInArg0: true, asm: "MINSD"}, // min(arg0,arg1) - {name: "MINSS", argLength: 2, reg: fp21, resultInArg0: true, asm: "MINSS"}, // min(arg0,arg1) + {name: "MINSD", argLength: 2, reg: fp21, resultInArg0: true, asm: "MINSD", earlyOk: true}, // min(arg0,arg1) + {name: "MINSS", argLength: 2, reg: fp21, resultInArg0: true, asm: "MINSS", earlyOk: true}, // min(arg0,arg1) - {name: "SBBQcarrymask", argLength: 1, reg: flagsgp, asm: "SBBQ"}, // (int64)(-1) if carry is set, 0 if carry is clear. - {name: "SBBLcarrymask", argLength: 1, reg: flagsgp, asm: "SBBL"}, // (int32)(-1) if carry is set, 0 if carry is clear. + {name: "SBBQcarrymask", argLength: 1, reg: flagsgp, asm: "SBBQ", earlyOk: true}, // (int64)(-1) if carry is set, 0 if carry is clear. + {name: "SBBLcarrymask", argLength: 1, reg: flagsgp, asm: "SBBL", earlyOk: true}, // (int32)(-1) if carry is set, 0 if carry is clear. // Note: SBBW and SBBB are subsumed by SBBL - {name: "SETEQ", argLength: 1, reg: readflags, asm: "SETEQ"}, // extract == condition from arg0 - {name: "SETNE", argLength: 1, reg: readflags, asm: "SETNE"}, // extract != condition from arg0 - {name: "SETL", argLength: 1, reg: readflags, asm: "SETLT"}, // extract signed < condition from arg0 - {name: "SETLE", argLength: 1, reg: readflags, asm: "SETLE"}, // extract signed <= condition from arg0 - {name: "SETG", argLength: 1, reg: readflags, asm: "SETGT"}, // extract signed > condition from arg0 - {name: "SETGE", argLength: 1, reg: readflags, asm: "SETGE"}, // extract signed >= condition from arg0 - {name: "SETB", argLength: 1, reg: readflags, asm: "SETCS"}, // extract unsigned < condition from arg0 - {name: "SETBE", argLength: 1, reg: readflags, asm: "SETLS"}, // extract unsigned <= condition from arg0 - {name: "SETA", argLength: 1, reg: readflags, asm: "SETHI"}, // extract unsigned > condition from arg0 - {name: "SETAE", argLength: 1, reg: readflags, asm: "SETCC"}, // extract unsigned >= condition from arg0 - {name: "SETO", argLength: 1, reg: readflags, asm: "SETOS"}, // extract if overflow flag is set from arg0 + {name: "SETEQ", argLength: 1, reg: readflags, asm: "SETEQ", earlyOk: true}, // extract == condition from arg0 + {name: "SETNE", argLength: 1, reg: readflags, asm: "SETNE", earlyOk: true}, // extract != condition from arg0 + {name: "SETL", argLength: 1, reg: readflags, asm: "SETLT", earlyOk: true}, // extract signed < condition from arg0 + {name: "SETLE", argLength: 1, reg: readflags, asm: "SETLE", earlyOk: true}, // extract signed <= condition from arg0 + {name: "SETG", argLength: 1, reg: readflags, asm: "SETGT", earlyOk: true}, // extract signed > condition from arg0 + {name: "SETGE", argLength: 1, reg: readflags, asm: "SETGE", earlyOk: true}, // extract signed >= condition from arg0 + {name: "SETB", argLength: 1, reg: readflags, asm: "SETCS", earlyOk: true}, // extract unsigned < condition from arg0 + {name: "SETBE", argLength: 1, reg: readflags, asm: "SETLS", earlyOk: true}, // extract unsigned <= condition from arg0 + {name: "SETA", argLength: 1, reg: readflags, asm: "SETHI", earlyOk: true}, // extract unsigned > condition from arg0 + {name: "SETAE", argLength: 1, reg: readflags, asm: "SETCC", earlyOk: true}, // extract unsigned >= condition from arg0 + {name: "SETO", argLength: 1, reg: readflags, asm: "SETOS", earlyOk: true}, // extract if overflow flag is set from arg0 // Variants that store result to memory - {name: "SETEQstore", argLength: 3, reg: gpstoreconst, asm: "SETEQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract == condition from arg1 to arg0+auxint+aux, arg2=mem - {name: "SETNEstore", argLength: 3, reg: gpstoreconst, asm: "SETNE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract != condition from arg1 to arg0+auxint+aux, arg2=mem - {name: "SETLstore", argLength: 3, reg: gpstoreconst, asm: "SETLT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed < condition from arg1 to arg0+auxint+aux, arg2=mem - {name: "SETLEstore", argLength: 3, reg: gpstoreconst, asm: "SETLE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed <= condition from arg1 to arg0+auxint+aux, arg2=mem - {name: "SETGstore", argLength: 3, reg: gpstoreconst, asm: "SETGT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed > condition from arg1 to arg0+auxint+aux, arg2=mem - {name: "SETGEstore", argLength: 3, reg: gpstoreconst, asm: "SETGE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed >= condition from arg1 to arg0+auxint+aux, arg2=mem - {name: "SETBstore", argLength: 3, reg: gpstoreconst, asm: "SETCS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned < condition from arg1 to arg0+auxint+aux, arg2=mem - {name: "SETBEstore", argLength: 3, reg: gpstoreconst, asm: "SETLS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned <= condition from arg1 to arg0+auxint+aux, arg2=mem - {name: "SETAstore", argLength: 3, reg: gpstoreconst, asm: "SETHI", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned > condition from arg1 to arg0+auxint+aux, arg2=mem - {name: "SETAEstore", argLength: 3, reg: gpstoreconst, asm: "SETCC", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned >= condition from arg1 to arg0+auxint+aux, arg2=mem - {name: "SETEQstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETEQ", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract == condition from arg2 to arg0+arg1+auxint+aux, arg3=mem - {name: "SETNEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETNE", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract != condition from arg2 to arg0+arg1+auxint+aux, arg3=mem - {name: "SETLstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETLT", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract signed < condition from arg2 to arg0+arg1+auxint+aux, arg3=mem - {name: "SETLEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETLE", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract signed <= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem - {name: "SETGstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETGT", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract signed > condition from arg2 to arg0+arg1+auxint+aux, arg3=mem - {name: "SETGEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETGE", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract signed >= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem - {name: "SETBstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETCS", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract unsigned < condition from arg2 to arg0+arg1+auxint+aux, arg3=mem - {name: "SETBEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETLS", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract unsigned <= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem - {name: "SETAstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETHI", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract unsigned > condition from arg2 to arg0+arg1+auxint+aux, arg3=mem - {name: "SETAEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETCC", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract unsigned >= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem + {name: "SETEQstore", argLength: 3, reg: gpstoreconst, asm: "SETEQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // extract == condition from arg1 to arg0+auxint+aux, arg2=mem + {name: "SETNEstore", argLength: 3, reg: gpstoreconst, asm: "SETNE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // extract != condition from arg1 to arg0+auxint+aux, arg2=mem + {name: "SETLstore", argLength: 3, reg: gpstoreconst, asm: "SETLT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // extract signed < condition from arg1 to arg0+auxint+aux, arg2=mem + {name: "SETLEstore", argLength: 3, reg: gpstoreconst, asm: "SETLE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // extract signed <= condition from arg1 to arg0+auxint+aux, arg2=mem + {name: "SETGstore", argLength: 3, reg: gpstoreconst, asm: "SETGT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // extract signed > condition from arg1 to arg0+auxint+aux, arg2=mem + {name: "SETGEstore", argLength: 3, reg: gpstoreconst, asm: "SETGE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // extract signed >= condition from arg1 to arg0+auxint+aux, arg2=mem + {name: "SETBstore", argLength: 3, reg: gpstoreconst, asm: "SETCS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // extract unsigned < condition from arg1 to arg0+auxint+aux, arg2=mem + {name: "SETBEstore", argLength: 3, reg: gpstoreconst, asm: "SETLS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // extract unsigned <= condition from arg1 to arg0+auxint+aux, arg2=mem + {name: "SETAstore", argLength: 3, reg: gpstoreconst, asm: "SETHI", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // extract unsigned > condition from arg1 to arg0+auxint+aux, arg2=mem + {name: "SETAEstore", argLength: 3, reg: gpstoreconst, asm: "SETCC", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // extract unsigned >= condition from arg1 to arg0+auxint+aux, arg2=mem + {name: "SETEQstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETEQ", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // extract == condition from arg2 to arg0+arg1+auxint+aux, arg3=mem + {name: "SETNEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETNE", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // extract != condition from arg2 to arg0+arg1+auxint+aux, arg3=mem + {name: "SETLstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETLT", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // extract signed < condition from arg2 to arg0+arg1+auxint+aux, arg3=mem + {name: "SETLEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETLE", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // extract signed <= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem + {name: "SETGstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETGT", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // extract signed > condition from arg2 to arg0+arg1+auxint+aux, arg3=mem + {name: "SETGEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETGE", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // extract signed >= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem + {name: "SETBstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETCS", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // extract unsigned < condition from arg2 to arg0+arg1+auxint+aux, arg3=mem + {name: "SETBEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETLS", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // extract unsigned <= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem + {name: "SETAstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETHI", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // extract unsigned > condition from arg2 to arg0+arg1+auxint+aux, arg3=mem + {name: "SETAEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETCC", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // extract unsigned >= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem // Need different opcodes for floating point conditions because // any comparison involving a NaN is always FALSE and thus // the patterns for inverting conditions cannot be used. - {name: "SETEQF", argLength: 1, reg: flagsgp, asm: "SETEQ", clobberFlags: true, needIntTemp: true}, // extract == condition from arg0 - {name: "SETNEF", argLength: 1, reg: flagsgp, asm: "SETNE", clobberFlags: true, needIntTemp: true}, // extract != condition from arg0 - {name: "SETORD", argLength: 1, reg: flagsgp, asm: "SETPC"}, // extract "ordered" (No Nan present) condition from arg0 - {name: "SETNAN", argLength: 1, reg: flagsgp, asm: "SETPS"}, // extract "unordered" (Nan present) condition from arg0 - - {name: "SETGF", argLength: 1, reg: flagsgp, asm: "SETHI"}, // extract floating > condition from arg0 - {name: "SETGEF", argLength: 1, reg: flagsgp, asm: "SETCC"}, // extract floating >= condition from arg0 - - {name: "MOVBQSX", argLength: 1, reg: gp11, asm: "MOVBQSX"}, // sign extend arg0 from int8 to int64 - {name: "MOVBQZX", argLength: 1, reg: gp11, asm: "MOVBLZX"}, // zero extend arg0 from int8 to int64 - {name: "MOVWQSX", argLength: 1, reg: gp11, asm: "MOVWQSX"}, // sign extend arg0 from int16 to int64 - {name: "MOVWQZX", argLength: 1, reg: gp11, asm: "MOVWLZX"}, // zero extend arg0 from int16 to int64 - {name: "MOVLQSX", argLength: 1, reg: gp11, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64 - {name: "MOVLQZX", argLength: 1, reg: gp11, asm: "MOVL"}, // zero extend arg0 from int32 to int64 - - {name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true}, // 32 low bits of auxint (upper 32 are zeroed) - {name: "MOVQconst", reg: gp01, asm: "MOVQ", typ: "UInt64", aux: "Int64", rematerializeable: true}, // auxint - - {name: "CVTTSD2SL", argLength: 1, reg: fpgp, asm: "CVTTSD2SL"}, // convert float64 to int32 - {name: "CVTTSD2SQ", argLength: 1, reg: fpgp, asm: "CVTTSD2SQ"}, // convert float64 to int64 - {name: "CVTTSS2SL", argLength: 1, reg: fpgp, asm: "CVTTSS2SL"}, // convert float32 to int32 - {name: "CVTTSS2SQ", argLength: 1, reg: fpgp, asm: "CVTTSS2SQ"}, // convert float32 to int64 - {name: "CVTSL2SS", argLength: 1, reg: gpfp, asm: "CVTSL2SS"}, // convert int32 to float32 - {name: "CVTSL2SD", argLength: 1, reg: gpfp, asm: "CVTSL2SD"}, // convert int32 to float64 - {name: "CVTSQ2SS", argLength: 1, reg: gpfp, asm: "CVTSQ2SS"}, // convert int64 to float32 - {name: "CVTSQ2SD", argLength: 1, reg: gpfp, asm: "CVTSQ2SD"}, // convert int64 to float64 - {name: "CVTSD2SS", argLength: 1, reg: fp11, asm: "CVTSD2SS"}, // convert float64 to float32 - {name: "CVTSS2SD", argLength: 1, reg: fp11, asm: "CVTSS2SD"}, // convert float32 to float64 + {name: "SETEQF", argLength: 1, reg: flagsgp, asm: "SETEQ", clobberFlags: true, needIntTemp: true, earlyOk: true}, // extract == condition from arg0 + {name: "SETNEF", argLength: 1, reg: flagsgp, asm: "SETNE", clobberFlags: true, needIntTemp: true, earlyOk: true}, // extract != condition from arg0 + {name: "SETORD", argLength: 1, reg: flagsgp, asm: "SETPC", earlyOk: true}, // extract "ordered" (No Nan present) condition from arg0 + {name: "SETNAN", argLength: 1, reg: flagsgp, asm: "SETPS", earlyOk: true}, // extract "unordered" (Nan present) condition from arg0 + + {name: "SETGF", argLength: 1, reg: flagsgp, asm: "SETHI", earlyOk: true}, // extract floating > condition from arg0 + {name: "SETGEF", argLength: 1, reg: flagsgp, asm: "SETCC", earlyOk: true}, // extract floating >= condition from arg0 + + {name: "MOVBQSX", argLength: 1, reg: gp11, asm: "MOVBQSX", earlyOk: true}, // sign extend arg0 from int8 to int64 + {name: "MOVBQZX", argLength: 1, reg: gp11, asm: "MOVBLZX", earlyOk: true}, // zero extend arg0 from int8 to int64 + {name: "MOVWQSX", argLength: 1, reg: gp11, asm: "MOVWQSX", earlyOk: true}, // sign extend arg0 from int16 to int64 + {name: "MOVWQZX", argLength: 1, reg: gp11, asm: "MOVWLZX", earlyOk: true}, // zero extend arg0 from int16 to int64 + {name: "MOVLQSX", argLength: 1, reg: gp11, asm: "MOVLQSX", earlyOk: true}, // sign extend arg0 from int32 to int64 + {name: "MOVLQZX", argLength: 1, reg: gp11, asm: "MOVL", earlyOk: true}, // zero extend arg0 from int32 to int64 + + {name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true, earlyOk: true}, // 32 low bits of auxint (upper 32 are zeroed) + {name: "MOVQconst", reg: gp01, asm: "MOVQ", typ: "UInt64", aux: "Int64", rematerializeable: true, earlyOk: true}, // auxint + + {name: "CVTTSD2SL", argLength: 1, reg: fpgp, asm: "CVTTSD2SL", earlyOk: true}, // convert float64 to int32 + {name: "CVTTSD2SQ", argLength: 1, reg: fpgp, asm: "CVTTSD2SQ", earlyOk: true}, // convert float64 to int64 + {name: "CVTTSS2SL", argLength: 1, reg: fpgp, asm: "CVTTSS2SL", earlyOk: true}, // convert float32 to int32 + {name: "CVTTSS2SQ", argLength: 1, reg: fpgp, asm: "CVTTSS2SQ", earlyOk: true}, // convert float32 to int64 + {name: "CVTSL2SS", argLength: 1, reg: gpfp, asm: "CVTSL2SS", earlyOk: true}, // convert int32 to float32 + {name: "CVTSL2SD", argLength: 1, reg: gpfp, asm: "CVTSL2SD", earlyOk: true}, // convert int32 to float64 + {name: "CVTSQ2SS", argLength: 1, reg: gpfp, asm: "CVTSQ2SS", earlyOk: true}, // convert int64 to float32 + {name: "CVTSQ2SD", argLength: 1, reg: gpfp, asm: "CVTSQ2SD", earlyOk: true}, // convert int64 to float64 + {name: "CVTSD2SS", argLength: 1, reg: fp11, asm: "CVTSD2SS", earlyOk: true}, // convert float64 to float32 + {name: "CVTSS2SD", argLength: 1, reg: fp11, asm: "CVTSS2SD", earlyOk: true}, // convert float32 to float64 // Move values between int and float registers, with no conversion. // TODO: should we have generic versions of these? - {name: "MOVQi2f", argLength: 1, reg: gpfp, typ: "Float64"}, // move 64 bits from int to float reg - {name: "MOVQf2i", argLength: 1, reg: fpgp, typ: "UInt64"}, // move 64 bits from float to int reg - {name: "MOVLi2f", argLength: 1, reg: gpfp, typ: "Float32"}, // move 32 bits from int to float reg - {name: "MOVLf2i", argLength: 1, reg: fpgp, typ: "UInt32"}, // move 32 bits from float to int reg, zero extend + {name: "MOVQi2f", argLength: 1, reg: gpfp, typ: "Float64", earlyOk: true}, // move 64 bits from int to float reg + {name: "MOVQf2i", argLength: 1, reg: fpgp, typ: "UInt64", earlyOk: true}, // move 64 bits from float to int reg + {name: "MOVLi2f", argLength: 1, reg: gpfp, typ: "Float32", earlyOk: true}, // move 32 bits from int to float reg + {name: "MOVLf2i", argLength: 1, reg: fpgp, typ: "UInt32", earlyOk: true}, // move 32 bits from float to int reg, zero extend - {name: "PXOR", argLength: 2, reg: fp21, asm: "PXOR", commutative: true, resultInArg0: true}, // exclusive or, applied to X regs (for float negation). - {name: "POR", argLength: 2, reg: fp21, asm: "POR", commutative: true, resultInArg0: true}, // inclusive or, applied to X regs (for float min/max). + {name: "PXOR", argLength: 2, reg: fp21, asm: "PXOR", commutative: true, resultInArg0: true, earlyOk: true}, // exclusive or, applied to X regs (for float negation). + {name: "POR", argLength: 2, reg: fp21, asm: "POR", commutative: true, resultInArg0: true, earlyOk: true}, // inclusive or, applied to X regs (for float min/max). - {name: "LEAQ", argLength: 1, reg: gp11sb, asm: "LEAQ", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux - {name: "LEAL", argLength: 1, reg: gp11sb, asm: "LEAL", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux - {name: "LEAW", argLength: 1, reg: gp11sb, asm: "LEAW", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux + {name: "LEAQ", argLength: 1, reg: gp11sb, asm: "LEAQ", aux: "SymOff", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxint + offset encoded in aux + {name: "LEAL", argLength: 1, reg: gp11sb, asm: "LEAL", aux: "SymOff", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxint + offset encoded in aux + {name: "LEAW", argLength: 1, reg: gp11sb, asm: "LEAW", aux: "SymOff", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxint + offset encoded in aux // LEAxn computes arg0 + n*arg1 + auxint + aux // x==L zeroes the upper 4 bytes. - {name: "LEAQ1", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 1, commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux - {name: "LEAL1", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 1, commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux - {name: "LEAW1", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 1, commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux - {name: "LEAQ2", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 2, aux: "SymOff", symEffect: "Addr"}, // arg0 + 2*arg1 + auxint + aux - {name: "LEAL2", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 2, aux: "SymOff", symEffect: "Addr"}, // arg0 + 2*arg1 + auxint + aux - {name: "LEAW2", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 2, aux: "SymOff", symEffect: "Addr"}, // arg0 + 2*arg1 + auxint + aux - {name: "LEAQ4", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 4, aux: "SymOff", symEffect: "Addr"}, // arg0 + 4*arg1 + auxint + aux - {name: "LEAL4", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 4, aux: "SymOff", symEffect: "Addr"}, // arg0 + 4*arg1 + auxint + aux - {name: "LEAW4", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 4, aux: "SymOff", symEffect: "Addr"}, // arg0 + 4*arg1 + auxint + aux - {name: "LEAQ8", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 8, aux: "SymOff", symEffect: "Addr"}, // arg0 + 8*arg1 + auxint + aux - {name: "LEAL8", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 8, aux: "SymOff", symEffect: "Addr"}, // arg0 + 8*arg1 + auxint + aux - {name: "LEAW8", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 8, aux: "SymOff", symEffect: "Addr"}, // arg0 + 8*arg1 + auxint + aux + {name: "LEAQ1", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 1, commutative: true, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + arg1 + auxint + aux + {name: "LEAL1", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 1, commutative: true, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + arg1 + auxint + aux + {name: "LEAW1", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 1, commutative: true, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + arg1 + auxint + aux + {name: "LEAQ2", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 2, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 2*arg1 + auxint + aux + {name: "LEAL2", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 2, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 2*arg1 + auxint + aux + {name: "LEAW2", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 2, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 2*arg1 + auxint + aux + {name: "LEAQ4", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 4, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 4*arg1 + auxint + aux + {name: "LEAL4", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 4, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 4*arg1 + auxint + aux + {name: "LEAW4", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 4, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 4*arg1 + auxint + aux + {name: "LEAQ8", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 8, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 8*arg1 + auxint + aux + {name: "LEAL8", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 8, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 8*arg1 + auxint + aux + {name: "LEAW8", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 8, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + 8*arg1 + auxint + aux // Note: LEAx{1,2,4,8} must not have OpSB as either argument. // MOVxload: loads // Load (Q=8,L=4,W=2,B=1) bytes from (arg0+auxint+aux), arg1=mem. // "+auxint+aux" == add auxint and the offset of the symbol in aux (if any) to the effective address // Standard versions zero extend the result. SX versions sign extend the result. - {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, - {name: "MOVBQSXload", argLength: 2, reg: gpload, asm: "MOVBQSX", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, - {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, - {name: "MOVWQSXload", argLength: 2, reg: gpload, asm: "MOVWQSX", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, - {name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, - {name: "MOVLQSXload", argLength: 2, reg: gpload, asm: "MOVLQSX", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, - {name: "MOVQload", argLength: 2, reg: gpload, asm: "MOVQ", aux: "SymOff", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"}, + {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, + {name: "MOVBQSXload", argLength: 2, reg: gpload, asm: "MOVBQSX", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, + {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, + {name: "MOVWQSXload", argLength: 2, reg: gpload, asm: "MOVWQSX", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, + {name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, + {name: "MOVLQSXload", argLength: 2, reg: gpload, asm: "MOVLQSX", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, + {name: "MOVQload", argLength: 2, reg: gpload, asm: "MOVQ", aux: "SymOff", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // MOVxstore: stores // Store (Q=8,L=4,W=2,B=1) low bytes of arg1. // Does *(arg0+auxint+aux) = arg1, arg2=mem. - {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, - {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, - {name: "MOVLstore", argLength: 3, reg: gpstore, asm: "MOVL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, - {name: "MOVQstore", argLength: 3, reg: gpstore, asm: "MOVQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, + {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, + {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, + {name: "MOVLstore", argLength: 3, reg: gpstore, asm: "MOVL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, + {name: "MOVQstore", argLength: 3, reg: gpstore, asm: "MOVQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // MOVOload/store: 16 byte load/store // These operations are only used to move data around: there is no *O arithmetic, for example. - {name: "MOVOload", argLength: 2, reg: fpload, asm: "MOVUPS", aux: "SymOff", typ: "Int128", faultOnNilArg0: true, symEffect: "Read"}, // load 16 bytes from arg0+auxint+aux. arg1=mem - {name: "MOVOstore", argLength: 3, reg: fpstore, asm: "MOVUPS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVOload", argLength: 2, reg: fpload, asm: "MOVUPS", aux: "SymOff", typ: "Int128", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 16 bytes from arg0+auxint+aux. arg1=mem + {name: "MOVOstore", argLength: 3, reg: fpstore, asm: "MOVUPS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem // MOVxloadidx: indexed loads // load (Q=8,L=4,W=2,B=1) bytes from (arg0+scale*arg1+auxint+aux), arg2=mem. // Results are zero-extended. (TODO: sign-extending indexed loads) - {name: "MOVBloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBLZX", scale: 1, aux: "SymOff", typ: "UInt8", symEffect: "Read"}, - {name: "MOVWloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVWLZX", scale: 1, aux: "SymOff", typ: "UInt16", symEffect: "Read"}, - {name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", scale: 2, aux: "SymOff", typ: "UInt16", symEffect: "Read"}, - {name: "MOVLloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVL", scale: 1, aux: "SymOff", typ: "UInt32", symEffect: "Read"}, - {name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", scale: 4, aux: "SymOff", typ: "UInt32", symEffect: "Read"}, - {name: "MOVLloadidx8", argLength: 3, reg: gploadidx, asm: "MOVL", scale: 8, aux: "SymOff", typ: "UInt32", symEffect: "Read"}, - {name: "MOVQloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVQ", scale: 1, aux: "SymOff", typ: "UInt64", symEffect: "Read"}, - {name: "MOVQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVQ", scale: 8, aux: "SymOff", typ: "UInt64", symEffect: "Read"}, + {name: "MOVBloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBLZX", scale: 1, aux: "SymOff", typ: "UInt8", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVWloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVWLZX", scale: 1, aux: "SymOff", typ: "UInt16", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", scale: 2, aux: "SymOff", typ: "UInt16", symEffect: "Read", addrSinkArg0: true}, + {name: "MOVLloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVL", scale: 1, aux: "SymOff", typ: "UInt32", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", scale: 4, aux: "SymOff", typ: "UInt32", symEffect: "Read", addrSinkArg0: true}, + {name: "MOVLloadidx8", argLength: 3, reg: gploadidx, asm: "MOVL", scale: 8, aux: "SymOff", typ: "UInt32", symEffect: "Read", addrSinkArg0: true}, + {name: "MOVQloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVQ", scale: 1, aux: "SymOff", typ: "UInt64", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVQ", scale: 8, aux: "SymOff", typ: "UInt64", symEffect: "Read", addrSinkArg0: true}, // MOVxstoreidx: indexed stores // Store (Q=8,L=4,W=2,B=1) low bytes of arg2. // Does *(arg0+scale*arg1+auxint+aux) = arg2, arg3=mem. - {name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVB", scale: 1, aux: "SymOff", symEffect: "Write"}, - {name: "MOVWstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVW", scale: 1, aux: "SymOff", symEffect: "Write"}, - {name: "MOVWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVW", scale: 2, aux: "SymOff", symEffect: "Write"}, - {name: "MOVLstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVL", scale: 1, aux: "SymOff", symEffect: "Write"}, - {name: "MOVLstoreidx4", argLength: 4, reg: gpstoreidx, asm: "MOVL", scale: 4, aux: "SymOff", symEffect: "Write"}, - {name: "MOVLstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVL", scale: 8, aux: "SymOff", symEffect: "Write"}, - {name: "MOVQstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVQ", scale: 1, aux: "SymOff", symEffect: "Write"}, - {name: "MOVQstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVQ", scale: 8, aux: "SymOff", symEffect: "Write"}, + {name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVB", scale: 1, aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVWstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVW", scale: 1, aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVW", scale: 2, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, + {name: "MOVLstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVL", scale: 1, aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVLstoreidx4", argLength: 4, reg: gpstoreidx, asm: "MOVL", scale: 4, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, + {name: "MOVLstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVL", scale: 8, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, + {name: "MOVQstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVQ", scale: 1, aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVQstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVQ", scale: 8, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // TODO: add size-mismatched indexed loads/stores, like MOVBstoreidx4? @@ -867,22 +969,22 @@ func init() { // Store (O=16,Q=8,L=4,W=2,B=1) constant bytes. // Does *(arg0+ValAndOff(AuxInt).Off()+aux) = ValAndOff(AuxInt).Val(), arg1=mem. // O version can only store the constant 0. - {name: "MOVBstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, - {name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, - {name: "MOVLstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, - {name: "MOVQstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVQ", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, - {name: "MOVOstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVUPS", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, + {name: "MOVBstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, + {name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, + {name: "MOVLstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, + {name: "MOVQstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVQ", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, + {name: "MOVOstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVUPS", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // MOVxstoreconstidx: constant indexed stores // Store (Q=8,L=4,W=2,B=1) constant bytes. // Does *(arg0+scale*arg1+ValAndOff(AuxInt).Off()+aux) = ValAndOff(AuxInt).Val(), arg2=mem. - {name: "MOVBstoreconstidx1", argLength: 3, reg: gpstoreconstidx, commutative: true, asm: "MOVB", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, - {name: "MOVWstoreconstidx1", argLength: 3, reg: gpstoreconstidx, commutative: true, asm: "MOVW", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, - {name: "MOVWstoreconstidx2", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", scale: 2, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, - {name: "MOVLstoreconstidx1", argLength: 3, reg: gpstoreconstidx, commutative: true, asm: "MOVL", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, - {name: "MOVLstoreconstidx4", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", scale: 4, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, - {name: "MOVQstoreconstidx1", argLength: 3, reg: gpstoreconstidx, commutative: true, asm: "MOVQ", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, - {name: "MOVQstoreconstidx8", argLength: 3, reg: gpstoreconstidx, asm: "MOVQ", scale: 8, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, + {name: "MOVBstoreconstidx1", argLength: 3, reg: gpstoreconstidx, commutative: true, asm: "MOVB", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVWstoreconstidx1", argLength: 3, reg: gpstoreconstidx, commutative: true, asm: "MOVW", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVWstoreconstidx2", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", scale: 2, aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true}, + {name: "MOVLstoreconstidx1", argLength: 3, reg: gpstoreconstidx, commutative: true, asm: "MOVL", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVLstoreconstidx4", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", scale: 4, aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true}, + {name: "MOVQstoreconstidx1", argLength: 3, reg: gpstoreconstidx, commutative: true, asm: "MOVQ", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVQstoreconstidx8", argLength: 3, reg: gpstoreconstidx, asm: "MOVQ", scale: 8, aux: "SymValAndOff", typ: "Mem", symEffect: "Write", addrSinkArg0: true}, // arg0 = pointer to start of memory to zero // arg1 = mem @@ -896,6 +998,7 @@ func init() { inputs: []regMask{gp}, }, faultOnNilArg0: true, + addrSinkArg0: true, }, // arg0 = pointer to start of memory to zero @@ -912,6 +1015,7 @@ func init() { }, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, needIntTemp: true, }, @@ -928,13 +1032,15 @@ func init() { clobbers: buildReg("DI CX"), }, faultOnNilArg0: true, + addrSinkArg0: true, }, // With a register ABI, the actual register info for these instructions (i.e., what is used in regalloc) is augmented with per-call-site bindings of additional arguments to specific in and out registers. - {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem - {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem - {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{gpsp, buildReg("DX"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem - {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtailinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{gpsp, buildReg("DX"), regMask{}}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem // arg0 = destination pointer // arg1 = source pointer @@ -951,6 +1057,8 @@ func init() { }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // arg0 = destination pointer // arg1 = source pointer @@ -970,6 +1078,8 @@ func init() { clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, needIntTemp: true, }, @@ -987,6 +1097,8 @@ func init() { }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // (InvertFlags (CMPQ a b)) == (CMPQ b a) @@ -1014,7 +1126,7 @@ func init() { // LoweredWB invokes runtime.gcWriteBarrier{auxint}. arg0=mem, auxint=# of buffer entries needed. // It saves all GP registers if necessary, but may clobber others. // Returns a pointer to a write barrier buffer in R11. - {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave &^ (gp | g), outputs: []regMask{buildReg("R11")}}, clobberFlags: true, aux: "Int64"}, + {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave.minus(gp.union(g)), outputs: []regMask{buildReg("R11")}}, clobberFlags: true, aux: "Int64"}, {name: "LoweredHasCPUFeature", argLength: 0, reg: gp01, rematerializeable: true, typ: "UInt64", aux: "Sym", symEffect: "None"}, @@ -1130,25 +1242,25 @@ func init() { // CPUID feature: MOVBE // MOVBEWload does not satisfy zero extended, so only use MOVBEWstore - {name: "MOVBEWstore", argLength: 3, reg: gpstore, asm: "MOVBEW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // swap and store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem - {name: "MOVBELload", argLength: 2, reg: gpload, asm: "MOVBEL", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load and swap 4 bytes from arg0+auxint+aux. arg1=mem. Zero extend. - {name: "MOVBELstore", argLength: 3, reg: gpstore, asm: "MOVBEL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // swap and store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem - {name: "MOVBEQload", argLength: 2, reg: gpload, asm: "MOVBEQ", aux: "SymOff", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"}, // load and swap 8 bytes from arg0+auxint+aux. arg1=mem - {name: "MOVBEQstore", argLength: 3, reg: gpstore, asm: "MOVBEQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // swap and store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVBEWstore", argLength: 3, reg: gpstore, asm: "MOVBEW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // swap and store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVBELload", argLength: 2, reg: gpload, asm: "MOVBEL", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load and swap 4 bytes from arg0+auxint+aux. arg1=mem. Zero extend. + {name: "MOVBELstore", argLength: 3, reg: gpstore, asm: "MOVBEL", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // swap and store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVBEQload", argLength: 2, reg: gpload, asm: "MOVBEQ", aux: "SymOff", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load and swap 8 bytes from arg0+auxint+aux. arg1=mem + {name: "MOVBEQstore", argLength: 3, reg: gpstore, asm: "MOVBEQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // swap and store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem // indexed MOVBE loads - {name: "MOVBELloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBEL", scale: 1, aux: "SymOff", typ: "UInt32", symEffect: "Read"}, // load and swap 4 bytes from arg0+arg1+auxint+aux. arg2=mem. Zero extend. - {name: "MOVBELloadidx4", argLength: 3, reg: gploadidx, asm: "MOVBEL", scale: 4, aux: "SymOff", typ: "UInt32", symEffect: "Read"}, // load and swap 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem. Zero extend. - {name: "MOVBELloadidx8", argLength: 3, reg: gploadidx, asm: "MOVBEL", scale: 8, aux: "SymOff", typ: "UInt32", symEffect: "Read"}, // load and swap 4 bytes from arg0+8*arg1+auxint+aux. arg2=mem. Zero extend. - {name: "MOVBEQloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBEQ", scale: 1, aux: "SymOff", typ: "UInt64", symEffect: "Read"}, // load and swap 8 bytes from arg0+arg1+auxint+aux. arg2=mem - {name: "MOVBEQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVBEQ", scale: 8, aux: "SymOff", typ: "UInt64", symEffect: "Read"}, // load and swap 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem + {name: "MOVBELloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBEL", scale: 1, aux: "SymOff", typ: "UInt32", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load and swap 4 bytes from arg0+arg1+auxint+aux. arg2=mem. Zero extend. + {name: "MOVBELloadidx4", argLength: 3, reg: gploadidx, asm: "MOVBEL", scale: 4, aux: "SymOff", typ: "UInt32", symEffect: "Read", addrSinkArg0: true}, // load and swap 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem. Zero extend. + {name: "MOVBELloadidx8", argLength: 3, reg: gploadidx, asm: "MOVBEL", scale: 8, aux: "SymOff", typ: "UInt32", symEffect: "Read", addrSinkArg0: true}, // load and swap 4 bytes from arg0+8*arg1+auxint+aux. arg2=mem. Zero extend. + {name: "MOVBEQloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBEQ", scale: 1, aux: "SymOff", typ: "UInt64", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load and swap 8 bytes from arg0+arg1+auxint+aux. arg2=mem + {name: "MOVBEQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVBEQ", scale: 8, aux: "SymOff", typ: "UInt64", symEffect: "Read", addrSinkArg0: true}, // load and swap 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem // indexed MOVBE stores - {name: "MOVBEWstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVBEW", scale: 1, aux: "SymOff", symEffect: "Write"}, // swap and store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem - {name: "MOVBEWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVBEW", scale: 2, aux: "SymOff", symEffect: "Write"}, // swap and store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem - {name: "MOVBELstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVBEL", scale: 1, aux: "SymOff", symEffect: "Write"}, // swap and store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem - {name: "MOVBELstoreidx4", argLength: 4, reg: gpstoreidx, asm: "MOVBEL", scale: 4, aux: "SymOff", symEffect: "Write"}, // swap and store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem - {name: "MOVBELstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVBEL", scale: 8, aux: "SymOff", symEffect: "Write"}, // swap and store 4 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem - {name: "MOVBEQstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVBEQ", scale: 1, aux: "SymOff", symEffect: "Write"}, // swap and store 8 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem - {name: "MOVBEQstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVBEQ", scale: 8, aux: "SymOff", symEffect: "Write"}, // swap and store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem + {name: "MOVBEWstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVBEW", scale: 1, aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // swap and store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVBEWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVBEW", scale: 2, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // swap and store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem + {name: "MOVBELstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVBEL", scale: 1, aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // swap and store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVBELstoreidx4", argLength: 4, reg: gpstoreidx, asm: "MOVBEL", scale: 4, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // swap and store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem + {name: "MOVBELstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVBEL", scale: 8, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // swap and store 4 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem + {name: "MOVBEQstoreidx1", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVBEQ", scale: 1, aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // swap and store 8 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVBEQstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVBEQ", scale: 8, aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // swap and store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem // CPUID feature: BMI2. {name: "SARXQ", argLength: 2, reg: gp21, asm: "SARXQ"}, // signed arg0 >> arg1, shift amount is mod 64 @@ -1158,28 +1270,28 @@ func init() { {name: "SHRXQ", argLength: 2, reg: gp21, asm: "SHRXQ"}, // unsigned arg0 >> arg1, shift amount is mod 64 {name: "SHRXL", argLength: 2, reg: gp21, asm: "SHRXL"}, // unsigned uint32(arg0) >> arg1, shift amount is mod 32 - {name: "SARXLload", argLength: 3, reg: gp21shxload, asm: "SARXL", aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // signed *(arg0+auxint+aux) >> arg1, arg2=mem, shift amount is mod 32 - {name: "SARXQload", argLength: 3, reg: gp21shxload, asm: "SARXQ", aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read"}, // signed *(arg0+auxint+aux) >> arg1, arg2=mem, shift amount is mod 64 - {name: "SHLXLload", argLength: 3, reg: gp21shxload, asm: "SHLXL", aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // *(arg0+auxint+aux) << arg1, arg2=mem, shift amount is mod 32 - {name: "SHLXQload", argLength: 3, reg: gp21shxload, asm: "SHLXQ", aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read"}, // *(arg0+auxint+aux) << arg1, arg2=mem, shift amount is mod 64 - {name: "SHRXLload", argLength: 3, reg: gp21shxload, asm: "SHRXL", aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // unsigned *(arg0+auxint+aux) >> arg1, arg2=mem, shift amount is mod 32 - {name: "SHRXQload", argLength: 3, reg: gp21shxload, asm: "SHRXQ", aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read"}, // unsigned *(arg0+auxint+aux) >> arg1, arg2=mem, shift amount is mod 64 - - {name: "SARXLloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SARXL", scale: 1, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // signed *(arg0+1*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 - {name: "SARXLloadidx4", argLength: 4, reg: gp21shxloadidx, asm: "SARXL", scale: 4, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // signed *(arg0+4*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 - {name: "SARXLloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SARXL", scale: 8, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // signed *(arg0+8*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 - {name: "SARXQloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SARXQ", scale: 1, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read"}, // signed *(arg0+1*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 64 - {name: "SARXQloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SARXQ", scale: 8, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read"}, // signed *(arg0+8*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 64 - {name: "SHLXLloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SHLXL", scale: 1, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // *(arg0+1*arg1+auxint+aux) << arg2, arg3=mem, shift amount is mod 32 - {name: "SHLXLloadidx4", argLength: 4, reg: gp21shxloadidx, asm: "SHLXL", scale: 4, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // *(arg0+4*arg1+auxint+aux) << arg2, arg3=mem, shift amount is mod 32 - {name: "SHLXLloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SHLXL", scale: 8, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // *(arg0+8*arg1+auxint+aux) << arg2, arg3=mem, shift amount is mod 32 - {name: "SHLXQloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SHLXQ", scale: 1, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read"}, // *(arg0+1*arg1+auxint+aux) << arg2, arg3=mem, shift amount is mod 64 - {name: "SHLXQloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SHLXQ", scale: 8, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read"}, // *(arg0+8*arg1+auxint+aux) << arg2, arg3=mem, shift amount is mod 64 - {name: "SHRXLloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SHRXL", scale: 1, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // unsigned *(arg0+1*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 - {name: "SHRXLloadidx4", argLength: 4, reg: gp21shxloadidx, asm: "SHRXL", scale: 4, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // unsigned *(arg0+4*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 - {name: "SHRXLloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SHRXL", scale: 8, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read"}, // unsigned *(arg0+8*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 - {name: "SHRXQloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SHRXQ", scale: 1, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read"}, // unsigned *(arg0+1*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 64 - {name: "SHRXQloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SHRXQ", scale: 8, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read"}, // unsigned *(arg0+8*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 64 + {name: "SARXLload", argLength: 3, reg: gp21shxload, asm: "SARXL", aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // signed *(arg0+auxint+aux) >> arg1, arg2=mem, shift amount is mod 32 + {name: "SARXQload", argLength: 3, reg: gp21shxload, asm: "SARXQ", aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // signed *(arg0+auxint+aux) >> arg1, arg2=mem, shift amount is mod 64 + {name: "SHLXLload", argLength: 3, reg: gp21shxload, asm: "SHLXL", aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // *(arg0+auxint+aux) << arg1, arg2=mem, shift amount is mod 32 + {name: "SHLXQload", argLength: 3, reg: gp21shxload, asm: "SHLXQ", aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // *(arg0+auxint+aux) << arg1, arg2=mem, shift amount is mod 64 + {name: "SHRXLload", argLength: 3, reg: gp21shxload, asm: "SHRXL", aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // unsigned *(arg0+auxint+aux) >> arg1, arg2=mem, shift amount is mod 32 + {name: "SHRXQload", argLength: 3, reg: gp21shxload, asm: "SHRXQ", aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // unsigned *(arg0+auxint+aux) >> arg1, arg2=mem, shift amount is mod 64 + + {name: "SARXLloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SARXL", scale: 1, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // signed *(arg0+1*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 + {name: "SARXLloadidx4", argLength: 4, reg: gp21shxloadidx, asm: "SARXL", scale: 4, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // signed *(arg0+4*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 + {name: "SARXLloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SARXL", scale: 8, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // signed *(arg0+8*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 + {name: "SARXQloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SARXQ", scale: 1, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // signed *(arg0+1*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 64 + {name: "SARXQloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SARXQ", scale: 8, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // signed *(arg0+8*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 64 + {name: "SHLXLloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SHLXL", scale: 1, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // *(arg0+1*arg1+auxint+aux) << arg2, arg3=mem, shift amount is mod 32 + {name: "SHLXLloadidx4", argLength: 4, reg: gp21shxloadidx, asm: "SHLXL", scale: 4, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // *(arg0+4*arg1+auxint+aux) << arg2, arg3=mem, shift amount is mod 32 + {name: "SHLXLloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SHLXL", scale: 8, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // *(arg0+8*arg1+auxint+aux) << arg2, arg3=mem, shift amount is mod 32 + {name: "SHLXQloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SHLXQ", scale: 1, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // *(arg0+1*arg1+auxint+aux) << arg2, arg3=mem, shift amount is mod 64 + {name: "SHLXQloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SHLXQ", scale: 8, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // *(arg0+8*arg1+auxint+aux) << arg2, arg3=mem, shift amount is mod 64 + {name: "SHRXLloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SHRXL", scale: 1, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // unsigned *(arg0+1*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 + {name: "SHRXLloadidx4", argLength: 4, reg: gp21shxloadidx, asm: "SHRXL", scale: 4, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // unsigned *(arg0+4*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 + {name: "SHRXLloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SHRXL", scale: 8, aux: "SymOff", typ: "Uint32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // unsigned *(arg0+8*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 32 + {name: "SHRXQloadidx1", argLength: 4, reg: gp21shxloadidx, asm: "SHRXQ", scale: 1, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // unsigned *(arg0+1*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 64 + {name: "SHRXQloadidx8", argLength: 4, reg: gp21shxloadidx, asm: "SHRXQ", scale: 8, aux: "SymOff", typ: "Uint64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // unsigned *(arg0+8*arg1+auxint+aux) >> arg2, arg3=mem, shift amount is mod 64 // Unpack bytes, low 64-bits. // @@ -1234,6 +1346,152 @@ func init() { // // output[i] = (input[i] >> 7) & 1 {name: "PMOVMSKB", argLength: 1, reg: fpgp, asm: "PMOVMSKB"}, + + // SIMD ops + {name: "VMOVDQUload128", argLength: 2, reg: vload, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1 = mem + {name: "VMOVDQUstore128", argLength: 3, reg: vstore, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem + + {name: "VMOVDQUload256", argLength: 2, reg: vload, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1 = mem + {name: "VMOVDQUstore256", argLength: 3, reg: vstore, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem + + {name: "VMOVDQUload512", argLength: 2, reg: wload, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1 = mem + {name: "VMOVDQUstore512", argLength: 3, reg: wstore, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem + + // AVX2 32 and 64-bit element int-vector masked moves. + {name: "VPMASK32load128", argLength: 3, reg: vloadv, asm: "VPMASKMOVD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1=integer mask, arg2 = mem + {name: "VPMASK32store128", argLength: 4, reg: vstorev, asm: "VPMASKMOVD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg2, arg1=integer mask, arg3 = mem + {name: "VPMASK64load128", argLength: 3, reg: vloadv, asm: "VPMASKMOVQ", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1=integer mask, arg2 = mem + {name: "VPMASK64store128", argLength: 4, reg: vstorev, asm: "VPMASKMOVQ", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg2, arg1=integer mask, arg3 = mem + + {name: "VPMASK32load256", argLength: 3, reg: vloadv, asm: "VPMASKMOVD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1=integer mask, arg2 = mem + {name: "VPMASK32store256", argLength: 4, reg: vstorev, asm: "VPMASKMOVD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg2, arg1=integer mask, arg3 = mem + {name: "VPMASK64load256", argLength: 3, reg: vloadv, asm: "VPMASKMOVQ", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1=integer mask, arg2 = mem + {name: "VPMASK64store256", argLength: 4, reg: vstorev, asm: "VPMASKMOVQ", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg2, arg1=integer mask, arg3 = mem + + // AVX512 8-64-bit element mask-register masked moves + {name: "VPMASK8load512", argLength: 3, reg: wloadk, asm: "VMOVDQU8", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1=k mask, arg2 = mem + {name: "VPMASK8store512", argLength: 4, reg: wstorek, asm: "VMOVDQU8", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg2, arg1=k mask, arg3 = mem + {name: "VPMASK16load512", argLength: 3, reg: wloadk, asm: "VMOVDQU16", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1=k mask, arg2 = mem + {name: "VPMASK16store512", argLength: 4, reg: wstorek, asm: "VMOVDQU16", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg2, arg1=k mask, arg3 = mem + {name: "VPMASK32load512", argLength: 3, reg: wloadk, asm: "VMOVDQU32", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1=k mask, arg2 = mem + {name: "VPMASK32store512", argLength: 4, reg: wstorek, asm: "VMOVDQU32", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg2, arg1=k mask, arg3 = mem + {name: "VPMASK64load512", argLength: 3, reg: wloadk, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1=k mask, arg2 = mem + {name: "VPMASK64store512", argLength: 4, reg: wstorek, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg2, arg1=k mask, arg3 = mem + + // AVX512 moves between int-vector and mask registers + {name: "VPMOVMToVec8x16", argLength: 1, reg: kv, asm: "VPMOVM2B"}, + {name: "VPMOVMToVec8x32", argLength: 1, reg: kv, asm: "VPMOVM2B"}, + {name: "VPMOVMToVec8x64", argLength: 1, reg: kw, asm: "VPMOVM2B"}, + + {name: "VPMOVMToVec16x8", argLength: 1, reg: kv, asm: "VPMOVM2W"}, + {name: "VPMOVMToVec16x16", argLength: 1, reg: kv, asm: "VPMOVM2W"}, + {name: "VPMOVMToVec16x32", argLength: 1, reg: kw, asm: "VPMOVM2W"}, + + {name: "VPMOVMToVec32x4", argLength: 1, reg: kv, asm: "VPMOVM2D"}, + {name: "VPMOVMToVec32x8", argLength: 1, reg: kv, asm: "VPMOVM2D"}, + {name: "VPMOVMToVec32x16", argLength: 1, reg: kw, asm: "VPMOVM2D"}, + + {name: "VPMOVMToVec64x2", argLength: 1, reg: kv, asm: "VPMOVM2Q"}, + {name: "VPMOVMToVec64x4", argLength: 1, reg: kv, asm: "VPMOVM2Q"}, + {name: "VPMOVMToVec64x8", argLength: 1, reg: kw, asm: "VPMOVM2Q"}, + + {name: "VPMOVVec8x16ToM", argLength: 1, reg: vk, asm: "VPMOVB2M"}, + {name: "VPMOVVec8x32ToM", argLength: 1, reg: vk, asm: "VPMOVB2M"}, + {name: "VPMOVVec8x64ToM", argLength: 1, reg: wk, asm: "VPMOVB2M"}, + + {name: "VPMOVVec16x8ToM", argLength: 1, reg: vk, asm: "VPMOVW2M"}, + {name: "VPMOVVec16x16ToM", argLength: 1, reg: vk, asm: "VPMOVW2M"}, + {name: "VPMOVVec16x32ToM", argLength: 1, reg: wk, asm: "VPMOVW2M"}, + + {name: "VPMOVVec32x4ToM", argLength: 1, reg: vk, asm: "VPMOVD2M"}, + {name: "VPMOVVec32x8ToM", argLength: 1, reg: vk, asm: "VPMOVD2M"}, + {name: "VPMOVVec32x16ToM", argLength: 1, reg: wk, asm: "VPMOVD2M"}, + + {name: "VPMOVVec64x2ToM", argLength: 1, reg: vk, asm: "VPMOVQ2M"}, + {name: "VPMOVVec64x4ToM", argLength: 1, reg: vk, asm: "VPMOVQ2M"}, + {name: "VPMOVVec64x8ToM", argLength: 1, reg: wk, asm: "VPMOVQ2M"}, + + // AVX1/2 moves from int-vector to bitmask (extracting sign bits) + {name: "VPMOVMSKB128", argLength: 1, reg: vgp, asm: "VPMOVMSKB"}, + {name: "VPMOVMSKB256", argLength: 1, reg: vgp, asm: "VPMOVMSKB"}, + {name: "VMOVMSKPS128", argLength: 1, reg: vgp, asm: "VMOVMSKPS"}, + {name: "VMOVMSKPS256", argLength: 1, reg: vgp, asm: "VMOVMSKPS"}, + {name: "VMOVMSKPD128", argLength: 1, reg: vgp, asm: "VMOVMSKPD"}, + {name: "VMOVMSKPD256", argLength: 1, reg: vgp, asm: "VMOVMSKPD"}, + + // X15 is the zero register up to 128-bit. For larger values, we zero it on the fly. + {name: "Zero128", argLength: 0, reg: x15only, zeroWidth: true, fixedReg: true}, + {name: "Zero256", argLength: 0, reg: v01, asm: "VPXOR"}, + {name: "Zero512", argLength: 0, reg: w01, asm: "VPXORQ"}, + + // Move a 32/64 bit float to a 128-bit SIMD register. + {name: "VMOVSDf2v", argLength: 1, reg: fpv, asm: "VMOVSD"}, + {name: "VMOVSSf2v", argLength: 1, reg: fpv, asm: "VMOVSS"}, + + {name: "VMOVQ", argLength: 1, reg: gpv, asm: "VMOVQ"}, + {name: "VMOVD", argLength: 1, reg: gpv, asm: "VMOVD"}, + + {name: "VMOVQload", argLength: 2, reg: fpload, asm: "VMOVQ", aux: "SymOff", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"}, + {name: "VMOVDload", argLength: 2, reg: fpload, asm: "VMOVD", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, + {name: "VMOVSSload", argLength: 2, reg: fpload, asm: "VMOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, + {name: "VMOVSDload", argLength: 2, reg: fpload, asm: "VMOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, + + {name: "VMOVSSconst", reg: fp01, asm: "VMOVSS", aux: "Float32", rematerializeable: true}, + {name: "VMOVSDconst", reg: fp01, asm: "VMOVSD", aux: "Float64", rematerializeable: true}, + + {name: "VZEROUPPER", argLength: 1, reg: regInfo{clobbers: v}, asm: "VZEROUPPER"}, // arg=mem, returns mem + {name: "VZEROALL", argLength: 1, reg: regInfo{clobbers: v}, asm: "VZEROALL"}, // arg=mem, returns mem + + // KMOVxload: loads masks + // Load (Q=8,D=4,W=2,B=1) bytes from (arg0+auxint+aux), arg1=mem. + // "+auxint+aux" == add auxint and the offset of the symbol in aux (if any) to the effective address + {name: "KMOVBload", argLength: 2, reg: kload, asm: "KMOVB", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, + {name: "KMOVWload", argLength: 2, reg: kload, asm: "KMOVW", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, + {name: "KMOVDload", argLength: 2, reg: kload, asm: "KMOVD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, + {name: "KMOVQload", argLength: 2, reg: kload, asm: "KMOVQ", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, + + // KMOVxstore: stores masks + // Store (Q=8,D=4,W=2,B=1) low bytes of arg1. + // Does *(arg0+auxint+aux) = arg1, arg2=mem. + {name: "KMOVBstore", argLength: 3, reg: kstore, asm: "KMOVB", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, + {name: "KMOVWstore", argLength: 3, reg: kstore, asm: "KMOVW", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, + {name: "KMOVDstore", argLength: 3, reg: kstore, asm: "KMOVD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, + {name: "KMOVQstore", argLength: 3, reg: kstore, asm: "KMOVQ", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, + + // Move GP directly to mask register + {name: "KMOVQk", argLength: 1, reg: gpk, asm: "KMOVQ"}, + {name: "KMOVDk", argLength: 1, reg: gpk, asm: "KMOVD"}, + {name: "KMOVWk", argLength: 1, reg: gpk, asm: "KMOVW"}, + {name: "KMOVBk", argLength: 1, reg: gpk, asm: "KMOVB"}, + {name: "KMOVQi", argLength: 1, reg: kgp, asm: "KMOVQ"}, + {name: "KMOVDi", argLength: 1, reg: kgp, asm: "KMOVD"}, + {name: "KMOVWi", argLength: 1, reg: kgp, asm: "KMOVW"}, + {name: "KMOVBi", argLength: 1, reg: kgp, asm: "KMOVB"}, + + // Mask logical operations + {name: "KANDB", argLength: 2, reg: k2k, asm: "KANDB", typ: "Mask"}, + {name: "KANDW", argLength: 2, reg: k2k, asm: "KANDW", typ: "Mask"}, + {name: "KANDD", argLength: 2, reg: k2k, asm: "KANDD", typ: "Mask"}, + {name: "KANDQ", argLength: 2, reg: k2k, asm: "KANDQ", typ: "Mask"}, + + {name: "KORB", argLength: 2, reg: k2k, asm: "KORB", typ: "Mask"}, + {name: "KORW", argLength: 2, reg: k2k, asm: "KORW", typ: "Mask"}, + {name: "KORD", argLength: 2, reg: k2k, asm: "KORD", typ: "Mask"}, + {name: "KORQ", argLength: 2, reg: k2k, asm: "KORQ", typ: "Mask"}, + + {name: "KXORB", argLength: 2, reg: k2k, asm: "KXORB", typ: "Mask"}, + {name: "KXORW", argLength: 2, reg: k2k, asm: "KXORW", typ: "Mask"}, + {name: "KXORD", argLength: 2, reg: k2k, asm: "KXORD", typ: "Mask"}, + {name: "KXORQ", argLength: 2, reg: k2k, asm: "KXORQ", typ: "Mask"}, + + // Following Intel convention, we call it XNOR instead of EQ. + {name: "KXNORB", argLength: 2, reg: k2k, asm: "KXNORB", typ: "Mask"}, + {name: "KXNORW", argLength: 2, reg: k2k, asm: "KXNORW", typ: "Mask"}, + {name: "KXNORD", argLength: 2, reg: k2k, asm: "KXNORD", typ: "Mask"}, + {name: "KXNORQ", argLength: 2, reg: k2k, asm: "KXNORQ", typ: "Mask"}, + + // VPTEST + {name: "VPTEST", asm: "VPTEST", argLength: 2, reg: v2flags, clobberFlags: true, typ: "Flags"}, } var AMD64blocks = []blockData{ @@ -1262,17 +1520,21 @@ func init() { } archs = append(archs, arch{ - name: "AMD64", - pkg: "cmd/internal/obj/x86", - genfile: "../../amd64/ssa.go", - ops: AMD64ops, + name: "AMD64", + pkg: "cmd/internal/obj/x86", + genfile: "../../amd64/ssa.go", + genSIMDfile: "../../amd64/simdssa.go", + ops: append(AMD64ops, simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vfpkv, + w11, w21, w2k, wkw, w2kw, w2kk, w31, w3kw, wgpw, wgp, wfpw, wfpkw, wkwload, v21load, v31load, v11load, + w21load, w31load, w2kload, w2kwload, w11load, w3kwload, w2kkload, v31x0AtIn2)...), // AMD64ops, blocks: AMD64blocks, regnames: regNamesAMD64, ParamIntRegNames: "AX BX CX DI SI R8 R9 R10 R11", ParamFloatRegNames: "X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14", gpregmask: gp, fpregmask: fp, - specialregmask: x15, + specialregmask: mask.union(w.minus(v)), + simdregmask: v, framepointerreg: int8(num["BP"]), linkreg: -1, // not used }) diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules b/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules index ead4ec45f1e28f..9bdb5f8d803bdb 100644 --- a/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules +++ b/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules @@ -8,6 +8,6 @@ (SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y) // See comments in ARM64latelower.rules for why these are here. -(MOVLQZX x) && zeroUpper32Bits(x,3) => x -(MOVWQZX x) && zeroUpper48Bits(x,3) => x -(MOVBQZX x) && zeroUpper56Bits(x,3) => x +(MOVLQZX x) && ZeroUpper32Bits(x,3) => x +(MOVWQZX x) && ZeroUpper48Bits(x,3) => x +(MOVBQZX x) && ZeroUpper56Bits(x,3) => x diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64splitload.rules b/src/cmd/compile/internal/ssa/_gen/AMD64splitload.rules index dd8f8ac4a164fd..ad106b53cf3132 100644 --- a/src/cmd/compile/internal/ssa/_gen/AMD64splitload.rules +++ b/src/cmd/compile/internal/ssa/_gen/AMD64splitload.rules @@ -16,7 +16,7 @@ // For example: // (CMPBconstload c (ADDQ x y)) -> (CMPBconstloadidx1 c x y) -> (CMPB c (MOVBloadidx1 x y)) -(CMP(Q|L|W|B)load {sym} [off] ptr x mem) => (CMP(Q|L|W|B) (MOV(Q|L|W|B)load {sym} [off] ptr mem) x) +(CMP(Q|L|W|B)load {sym} [off] ptr x mem) => (CMP(Q|L|W|B) (MOV(Q|L|W|B)load {sym} [off] ptr mem) x) (CMP(Q|L|W|B)constload {sym} [vo] ptr mem) && vo.Val() == 0 => (TEST(Q|L|W|B) x:(MOV(Q|L|W|B)load {sym} [vo.Off()] ptr mem) x) @@ -25,10 +25,10 @@ (CMPWconstload {sym} [vo] ptr mem) && vo.Val() != 0 => (CMPWconst (MOVWload {sym} [vo.Off()] ptr mem) [vo.Val16()]) (CMPBconstload {sym} [vo] ptr mem) && vo.Val() != 0 => (CMPBconst (MOVBload {sym} [vo.Off()] ptr mem) [vo.Val8()]) -(CMP(Q|L|W|B)loadidx1 {sym} [off] ptr idx x mem) => (CMP(Q|L|W|B) (MOV(Q|L|W|B)loadidx1 {sym} [off] ptr idx mem) x) -(CMPQloadidx8 {sym} [off] ptr idx x mem) => (CMPQ (MOVQloadidx8 {sym} [off] ptr idx mem) x) -(CMPLloadidx4 {sym} [off] ptr idx x mem) => (CMPL (MOVLloadidx4 {sym} [off] ptr idx mem) x) -(CMPWloadidx2 {sym} [off] ptr idx x mem) => (CMPW (MOVWloadidx2 {sym} [off] ptr idx mem) x) +(CMP(Q|L|W|B)loadidx1 {sym} [off] ptr idx x mem) => (CMP(Q|L|W|B) (MOV(Q|L|W|B)loadidx1 {sym} [off] ptr idx mem) x) +(CMPQloadidx8 {sym} [off] ptr idx x mem) => (CMPQ (MOVQloadidx8 {sym} [off] ptr idx mem) x) +(CMPLloadidx4 {sym} [off] ptr idx x mem) => (CMPL (MOVLloadidx4 {sym} [off] ptr idx mem) x) +(CMPWloadidx2 {sym} [off] ptr idx x mem) => (CMPW (MOVWloadidx2 {sym} [off] ptr idx mem) x) (CMP(Q|L|W|B)constloadidx1 {sym} [vo] ptr idx mem) && vo.Val() == 0 => (TEST(Q|L|W|B) x:(MOV(Q|L|W|B)loadidx1 {sym} [vo.Off()] ptr idx mem) x) (CMPQconstloadidx8 {sym} [vo] ptr idx mem) && vo.Val() == 0 => (TESTQ x:(MOVQloadidx8 {sym} [vo.Off()] ptr idx mem) x) diff --git a/src/cmd/compile/internal/ssa/_gen/ARM.rules b/src/cmd/compile/internal/ssa/_gen/ARM.rules index 18b5d6bba6099e..6020992a7de2c6 100644 --- a/src/cmd/compile/internal/ssa/_gen/ARM.rules +++ b/src/cmd/compile/internal/ssa/_gen/ARM.rules @@ -6,6 +6,7 @@ (Add(32|64)F ...) => (ADD(F|D) ...) (Add32carry ...) => (ADDS ...) (Add32withcarry ...) => (ADC ...) +(Add32carrywithcarry ...) => (ADCS ...) (Sub(Ptr|32|16|8) ...) => (SUB ...) (Sub(32|64)F ...) => (SUB(F|D) ...) @@ -354,6 +355,7 @@ (ClosureCall ...) => (CALLclosure ...) (InterCall ...) => (CALLinter ...) (TailCall ...) => (CALLtail ...) +(TailCallInter ...) => (CALLtailinter ...) // checks (NilCheck ...) => (LoweredNilCheck ...) diff --git a/src/cmd/compile/internal/ssa/_gen/ARM64.rules b/src/cmd/compile/internal/ssa/_gen/ARM64.rules index f54a692725e513..4c6c437f26b9fe 100644 --- a/src/cmd/compile/internal/ssa/_gen/ARM64.rules +++ b/src/cmd/compile/internal/ssa/_gen/ARM64.rules @@ -145,59 +145,38 @@ // check shiftIsBounded first, if shift value is proved to be valid then we // can do the shift directly. // left shift -(Lsh(64|32|16|8)x64 x y) && shiftIsBounded(v) => (SLL x y) -(Lsh(64|32|16|8)x32 x y) && shiftIsBounded(v) => (SLL x y) -(Lsh(64|32|16|8)x16 x y) && shiftIsBounded(v) => (SLL x y) -(Lsh(64|32|16|8)x8 x y) && shiftIsBounded(v) => (SLL x y) +(Lsh32x(64|32|16|8) ...) => (Lsh64x(64|32|16|8) ...) +(Lsh16x(64|32|16|8) ...) => (Lsh64x(64|32|16|8) ...) +(Lsh8x(64|32|16|8) ...) => (Lsh64x(64|32|16|8) ...) + +(Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SLL x y) // signed right shift +(Rsh32x(64|32|16|8) [bounded] x y) => (Rsh64x(64|32|16|8) [bounded] (SignExt32to64 x) y) +(Rsh16x(64|32|16|8) [bounded] x y) => (Rsh64x(64|32|16|8) [bounded] (SignExt16to64 x) y) +(Rsh8x(64|32|16|8) [bounded] x y) => (Rsh64x(64|32|16|8) [bounded] (SignExt8to64 x) y) + (Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SRA x y) -(Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRA (SignExt32to64 x) y) -(Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRA (SignExt16to64 x) y) -(Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRA (SignExt8to64 x) y) // unsigned right shift +(Rsh32Ux(64|32|16|8) [bounded] x y) => (Rsh64Ux(64|32|16|8) [bounded] (ZeroExt32to64 x) y) +(Rsh16Ux(64|32|16|8) [bounded] x y) => (Rsh64Ux(64|32|16|8) [bounded] (ZeroExt16to64 x) y) +(Rsh8Ux(64|32|16|8) [bounded] x y) => (Rsh64Ux(64|32|16|8) [bounded] (ZeroExt8to64 x) y) + (Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRL x y) -(Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRL (ZeroExt32to64 x) y) -(Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRL (ZeroExt16to64 x) y) -(Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRL (ZeroExt8to64 x) y) // shift value may be out of range, use CMP + CSEL instead -(Lsh64x64 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) -(Lsh64x(32|16|8) x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) - -(Lsh32x64 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) -(Lsh32x(32|16|8) x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) - -(Lsh16x64 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) -(Lsh16x(32|16|8) x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) - -(Lsh8x64 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) -(Lsh8x(32|16|8) x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) - -(Rsh64Ux64 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] y)) -(Rsh64Ux(32|16|8) x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) - -(Rsh32Ux64 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] y)) -(Rsh32Ux(32|16|8) x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) - -(Rsh16Ux64 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] y)) -(Rsh16Ux(32|16|8) x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) - -(Rsh8Ux64 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] y)) -(Rsh8Ux(32|16|8) x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) +(Lsh64x64 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) +(Lsh64x32 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPWconst [64] y)) +(Lsh64x(16|8) [bounded] x y) && !shiftIsBounded(v) => (Lsh64x32 [bounded] x (ZeroExt(16|8)to32 y)) -(Rsh64x64 x y) && !shiftIsBounded(v) => (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) -(Rsh64x(32|16|8) x y) && !shiftIsBounded(v) => (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y)))) +(Rsh64Ux64 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] y)) +(Rsh64Ux32 x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPWconst [64] y)) +(Rsh64Ux(16|8) [bounded] x y) && !shiftIsBounded(v) => (Rsh64Ux32 [bounded] x (ZeroExt(16|8)to32 y)) -(Rsh32x64 x y) && !shiftIsBounded(v) => (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) -(Rsh32x(32|16|8) x y) && !shiftIsBounded(v) => (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y)))) - -(Rsh16x64 x y) && !shiftIsBounded(v) => (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) -(Rsh16x(32|16|8) x y) && !shiftIsBounded(v) => (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y)))) - -(Rsh8x64 x y) && !shiftIsBounded(v) => (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) -(Rsh8x(32|16|8) x y) && !shiftIsBounded(v) => (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y)))) +(Rsh64x64 x y) && !shiftIsBounded(v) => (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) +(Rsh64x32 x y) && !shiftIsBounded(v) => (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPWconst [64] y))) +(Rsh64x(16|8) [bounded] x y) && !shiftIsBounded(v) => (Rsh64x32 [bounded] x (ZeroExt(16|8)to32 y)) // constants (Const(64|32|16|8) [val]) => (MOVDconst [int64(val)]) @@ -341,6 +320,7 @@ (Load ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem) (Load ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem) (Load ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem) +(Load ptr mem) && t.Size() == 16 => (FMOVQload ptr mem) // stores (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem) @@ -349,6 +329,7 @@ (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem) (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem) (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem) +(Store {t} ptr val mem) && t.Size() == 16 => (FMOVQstore ptr val mem) // zeroing (Zero [0] _ mem) => mem @@ -434,42 +415,35 @@ (Move [15] dst src mem) => (MOVDstore [7] dst (MOVDload [7] src mem) (MOVDstore dst (MOVDload src mem) mem)) -(Move [16] dst src mem) => - (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem) +(Move [16] dst src mem) => (FMOVQstore dst (FMOVQload src mem) mem) (Move [s] dst src mem) && s > 16 && s <= 24 => (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem) - (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)) -(Move [s] dst src mem) && s > 24 && s <= 32 => - (STP [int32(s-16)] dst (Select0 (LDP [int32(s-16)] src mem)) (Select1 (LDP [int32(s-16)] src mem)) - (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)) + (FMOVQstore dst (FMOVQload src mem) mem)) +(Move [s] dst src mem) && s > 24 && s < 32 => + (FMOVQstore [int32(s-16)] dst (FMOVQload [int32(s-16)] src mem) + (FMOVQstore dst (FMOVQload src mem) mem)) +(Move [32] dst src mem) => + (FSTPQ dst (Select0 (FLDPQ src mem)) (Select1 (FLDPQ src mem)) mem) (Move [s] dst src mem) && s > 32 && s <= 40 => (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem) - (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) - (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem))) + (FSTPQ dst (Select0 (FLDPQ src mem)) (Select1 (FLDPQ src mem)) mem)) (Move [s] dst src mem) && s > 40 && s <= 48 => - (STP [int32(s-16)] dst (Select0 (LDP [int32(s-16)] src mem)) (Select1 (LDP [int32(s-16)] src mem)) - (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) - (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem))) -(Move [s] dst src mem) && s > 48 && s <= 56 => - (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem) - (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) - (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) - (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)))) -(Move [s] dst src mem) && s > 56 && s <= 64 => - (STP [int32(s-16)] dst (Select0 (LDP [int32(s-16)] src mem)) (Select1 (LDP [int32(s-16)] src mem)) - (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) - (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) - (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)))) + (FMOVQstore [int32(s-16)] dst (FMOVQload [int32(s-16)] src mem) + (FSTPQ dst (Select0 (FLDPQ src mem)) (Select1 (FLDPQ src mem)) mem)) +(Move [s] dst src mem) && s > 48 && s <= 64 => + (FSTPQ [int32(s-32)] dst (Select0 (FLDPQ [int32(s-32)] src mem)) (Select1 (FLDPQ [int32(s-32)] src mem)) + (FSTPQ dst (Select0 (FLDPQ src mem)) (Select1 (FLDPQ src mem)) mem)) (Move [s] dst src mem) && s > 64 && s < 192 && logLargeCopy(v, s) => (LoweredMove [s] dst src mem) (Move [s] dst src mem) && s >= 192 && logLargeCopy(v, s) => (LoweredMoveLoop [s] dst src mem) // calls -(StaticCall ...) => (CALLstatic ...) -(ClosureCall ...) => (CALLclosure ...) -(InterCall ...) => (CALLinter ...) -(TailCall ...) => (CALLtail ...) +(StaticCall ...) => (CALLstatic ...) +(ClosureCall ...) => (CALLclosure ...) +(InterCall ...) => (CALLinter ...) +(TailCall ...) => (CALLtail ...) +(TailCallInter ...) => (CALLtailinter ...) // checks (NilCheck ...) => (LoweredNilCheck ...) @@ -481,6 +455,7 @@ (GetClosurePtr ...) => (LoweredGetClosurePtr ...) (GetCallerSP ...) => (LoweredGetCallerSP ...) (GetCallerPC ...) => (LoweredGetCallerPC ...) +(MemEq ...) => (LoweredMemEq ...) // Absorb pseudo-ops into blocks. (If (Equal cc) yes no) => (EQ cc yes no) @@ -542,6 +517,11 @@ // Optimizations +// Replace widen -> wide_unop -> narrow with narrow_unop when one exists. +(FCVTDS (F(ABS|SQRT|RINTP|RINTM|RINTA|RINTN|RINTZ)D (FCVTSD x))) => + (F(ABS|SQRT|RINTP|RINTM|RINTA|RINTN|RINTZ)S x) + + // Absorb boolean tests into block (NZ (Equal cc) yes no) => (EQ cc yes no) (NZ (NotEqual cc) yes no) => (NE cc yes no) @@ -573,6 +553,8 @@ (TBNZ [0] (GreaterThanF cc) yes no) => (FGT cc yes no) (TBNZ [0] (GreaterEqualF cc) yes no) => (FGE cc yes no) +(TB(Z|NZ) [0] (XORconst [1] x) yes no) => (TB(NZ|Z) [0] x yes no) + ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TST x y) yes no) ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] x:(ANDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTconst [c] y) yes no) ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTW x y) yes no) @@ -641,6 +623,23 @@ (EQ (TSTWconst [c] x) yes no) && oneBit(int64(uint32(c))) => (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) (NE (TSTWconst [c] x) yes no) && oneBit(int64(uint32(c))) => (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) +((Z|NZ) s:(SRLconst [63] x) yes no) && s.Uses == 1 => (TB(Z|NZ) [63] x yes no) +((Z|NZ) s:(SRAconst [63] x) yes no) && s.Uses == 1 => (TB(Z|NZ) [63] x yes no) + +// Merge more operations into TBZ & TBNZ +(TB(Z|NZ) [t] sv:(SRLconst [s] x) yes no) && t+s < 64 && sv.Uses == 1 => (TB(Z|NZ) [t+s] x yes no ) +(TBZ [t] (SRLconst [s] x) yes no) && t+s >= 64 => (First yes no ) +(TBNZ [t] (SRLconst [s] x) yes no) && t+s >= 64 => (First no yes) + +(TB(Z|NZ) [t] sv:(SLLconst [s] x) yes no) && t-s >= 0 && sv.Uses == 1 => (TB(Z|NZ) [t-s] x yes no ) +(TBZ [t] (SLLconst [s] x) yes no) && t-s < 0 => (First yes no ) +(TBNZ [t] (SLLconst [s] x) yes no) && t-s < 0 => (First no yes) + +(TB(Z|NZ) [t] rv:(RORconst [r] x) yes no) && rv.Uses == 1 => (TB(Z|NZ) [int64(uint64(t+r)%64)] x yes no) + +(TB(Z|NZ) [t] sv:(SRAconst [s] x) yes no) && t+s < 64 && sv.Uses == 1 => (TB(Z|NZ) [t+s] x yes no) +(TB(Z|NZ) [t] sv:(SRAconst [s] x) yes no) && t+s >= 64 && sv.Uses == 1 => (TB(Z|NZ) [63 ] x yes no) + // Test sign-bit for signed comparisons against zero (GE (CMPWconst [0] x) yes no) => (TBZ [31] x yes no) (GE (CMPconst [0] x) yes no) => (TBZ [63] x yes no) @@ -685,6 +684,12 @@ (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => (FMOVDload [off1+int32(off2)] {sym} ptr mem) +(FMOVQload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) + && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => + (FMOVQload [off1+int32(off2)] {sym} ptr mem) +(FLDPQ [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) + && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => + (FLDPQ [off1+int32(off2)] {sym} ptr mem) // register indexed load (MOVDload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx ptr idx mem) @@ -770,6 +775,12 @@ (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => (FMOVDstore [off1+int32(off2)] {sym} ptr val mem) +(FMOVQstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) + && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => + (FMOVQstore [off1+int32(off2)] {sym} ptr val mem) +(FSTPQ [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) && is32Bit(int64(off1)+off2) + && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => + (FSTPQ [off1+int32(off2)] {sym} ptr val1 val2 mem) // register indexed store (MOVDstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr idx val mem) @@ -856,6 +867,14 @@ && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) +(FMOVQload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) + && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) + && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => + (FMOVQload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) +(FLDPQ [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) + && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) + && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => + (FLDPQ [off1+off2] {mergeSym(sym1,sym2)} ptr mem) (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) @@ -885,6 +904,14 @@ && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) +(FMOVQstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) + && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) + && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => + (FMOVQstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) +(FSTPQ [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) + && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) + && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => + (FSTPQ [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) // replace load from same location as preceding store with zero/sign extension (or copy in case of full width) // these seem to have bad interaction with other rules, resulting in slower code @@ -1571,6 +1598,8 @@ && (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) => (REV16 (ANDconst [0xffffffff] x)) +(REV16 (MOVWUreg x)) => (REV16W x) + // Extract from reg pair (ADDshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x) ( ORshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x) @@ -1644,6 +1673,7 @@ (SBFX [bfc] s:(SLLconst [sc] x)) && s.Uses == 1 && sc > bfc.lsb() + && sc < bfc.lsb()+bfc.width() => (SBFIZ [armBFAuxInt(sc - bfc.lsb(), bfc.width() - (sc-bfc.lsb()))] x) // ubfiz @@ -1814,3 +1844,15 @@ (Select0 (Mul64uover x y)) => (MUL x y) (Select1 (Mul64uover x y)) => (NotEqual (CMPconst (UMULH x y) [0])) + +// 32 mul 32 -> 64 +(MUL r:(MOVWUreg x) s:(MOVWUreg y)) && r.Uses == 1 && s.Uses == 1 => (UMULL x y) +(MUL r:(MOVWreg x) s:(MOVWreg y)) && r.Uses == 1 && s.Uses == 1 => (MULL x y) + +// ANDconst to zext +(ANDconst [0xffffffff] x) => (MOVWUreg x) +(ANDconst [0xffff ] x) => (MOVHUreg x) +(ANDconst [0xff ] x) => (MOVBUreg x) + +// SIMD zero +(ZeroSIMD ) && t.Size() == 16 => (VMOVI16B [0] ) diff --git a/src/cmd/compile/internal/ssa/_gen/ARM64Ops.go b/src/cmd/compile/internal/ssa/_gen/ARM64Ops.go index cc3758d10956d4..0da3151acd3e7c 100644 --- a/src/cmd/compile/internal/ssa/_gen/ARM64Ops.go +++ b/src/cmd/compile/internal/ssa/_gen/ARM64Ops.go @@ -124,10 +124,10 @@ func init() { num[name] = i } buildReg := func(s string) regMask { - m := regMask(0) + m := regMask{} for _, r := range strings.Split(s, " ") { if n, ok := num[r]; ok { - m |= regMask(1) << uint(n) + m = m.addReg(uint(n)) continue } panic("register " + r + " not found") @@ -138,12 +138,12 @@ func init() { // Common individual register masks var ( gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30") - gpg = gp | buildReg("g") - gpsp = gp | buildReg("SP") - gpspg = gpg | buildReg("SP") - gpspsbg = gpspg | buildReg("SB") + gpg = gp.union(buildReg("g")) + gpsp = gp.union(buildReg("SP")) + gpspg = gpg.union(buildReg("SP")) + gpspsbg = gpspg.union(buildReg("SB")) fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31") - callerSave = gp | fp | buildReg("g") // runtime.setg (and anything calling it) may clobber g + callerSave = gp.union(fp).union(buildReg("g")) // runtime.setg (and anything calling it) may clobber g r25 = buildReg("R25") r24to25 = buildReg("R24 R25") f16to17 = buildReg("F16 F17") @@ -153,31 +153,32 @@ func init() { // Common regInfo var ( gp01 = regInfo{inputs: nil, outputs: []regMask{gp}} - gp0flags1 = regInfo{inputs: []regMask{0}, outputs: []regMask{gp}} + gp0flags1 = regInfo{inputs: []regMask{regMask{}}, outputs: []regMask{gp}} gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}} gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}} gp1flags = regInfo{inputs: []regMask{gpg}} gp1flagsflags = regInfo{inputs: []regMask{gpg}} gp1flags1 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}} - gp11flags = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp, 0}} + gp11flags = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp, regMask{}}} gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}} gp21nog = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}} - gp21flags = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp, 0}} + gp21flags = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp, regMask{}}} gp2flags = regInfo{inputs: []regMask{gpg, gpg}} gp2flagsflags = regInfo{inputs: []regMask{gpg, gpg}} gp2flags1 = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}} - gp2flags1flags = regInfo{inputs: []regMask{gp, gp, 0}, outputs: []regMask{gp, 0}} + gp2flags1flags = regInfo{inputs: []regMask{gp, gp, regMask{}}, outputs: []regMask{gp, regMask{}}} gp2load = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}} gp31 = regInfo{inputs: []regMask{gpg, gpg, gpg}, outputs: []regMask{gp}} gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}} gpload2 = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gpg, gpg}} - gpstore = regInfo{inputs: []regMask{gpspsbg, gpg | rz}} - gpstore2 = regInfo{inputs: []regMask{gpspsbg, gpg | rz, gpg | rz}} - gpxchg = regInfo{inputs: []regMask{gpspsbg, gpg | rz}, outputs: []regMask{gp}} - gpcas = regInfo{inputs: []regMask{gpspsbg, gpg | rz, gpg | rz}, outputs: []regMask{gp}} + gpstore = regInfo{inputs: []regMask{gpspsbg, gpg.union(rz)}} + gpstore2 = regInfo{inputs: []regMask{gpspsbg, gpg.union(rz), gpg.union(rz)}} + gpxchg = regInfo{inputs: []regMask{gpspsbg, gpg.union(rz)}, outputs: []regMask{gp}} + gpcas = regInfo{inputs: []regMask{gpspsbg, gpg.union(rz), gpg.union(rz)}, outputs: []regMask{gp}} fp01 = regInfo{inputs: nil, outputs: []regMask{fp}} fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}} fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}} + fpgpfp = regInfo{inputs: []regMask{fp, gp}, outputs: []regMask{fp}} gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}} fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}} fp31 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: []regMask{fp}} @@ -195,107 +196,108 @@ func init() { ops := []opData{ // binary ops {name: "ADCSflags", argLength: 3, reg: gp2flags1flags, typ: "(UInt64,Flags)", asm: "ADCS", commutative: true}, // arg0+arg1+carry, set flags. - {name: "ADCzerocarry", argLength: 1, reg: gp0flags1, typ: "UInt64", asm: "ADC"}, // ZR+ZR+carry - {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1 - {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int64"}, // arg0 + auxInt + {name: "ADCzerocarry", argLength: 1, reg: gp0flags1, typ: "UInt64", asm: "ADC", earlyOk: true}, // ZR+ZR+carry + {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int64", earlyOk: true}, // arg0 + auxInt {name: "ADDSconstflags", argLength: 1, reg: gp11flags, typ: "(UInt64,Flags)", asm: "ADDS", aux: "Int64"}, // arg0+auxint, set flags. {name: "ADDSflags", argLength: 2, reg: gp21flags, typ: "(UInt64,Flags)", asm: "ADDS", commutative: true}, // arg0+arg1, set flags. - {name: "SUB", argLength: 2, reg: gp21, asm: "SUB"}, // arg0 - arg1 - {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int64"}, // arg0 - auxInt + {name: "SUB", argLength: 2, reg: gp21, asm: "SUB", earlyOk: true}, // arg0 - arg1 + {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int64", earlyOk: true}, // arg0 - auxInt {name: "SBCSflags", argLength: 3, reg: gp2flags1flags, typ: "(UInt64,Flags)", asm: "SBCS"}, // arg0-(arg1+borrowing), set flags. {name: "SUBSflags", argLength: 2, reg: gp21flags, typ: "(UInt64,Flags)", asm: "SUBS"}, // arg0 - arg1, set flags. - {name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true}, // arg0 * arg1 - {name: "MULW", argLength: 2, reg: gp21, asm: "MULW", commutative: true}, // arg0 * arg1, 32-bit - {name: "MNEG", argLength: 2, reg: gp21, asm: "MNEG", commutative: true}, // -arg0 * arg1 - {name: "MNEGW", argLength: 2, reg: gp21, asm: "MNEGW", commutative: true}, // -arg0 * arg1, 32-bit - {name: "MULH", argLength: 2, reg: gp21, asm: "SMULH", commutative: true}, // (arg0 * arg1) >> 64, signed - {name: "UMULH", argLength: 2, reg: gp21, asm: "UMULH", commutative: true}, // (arg0 * arg1) >> 64, unsigned - {name: "MULL", argLength: 2, reg: gp21, asm: "SMULL", commutative: true}, // arg0 * arg1, signed, 32-bit mult results in 64-bit - {name: "UMULL", argLength: 2, reg: gp21, asm: "UMULL", commutative: true}, // arg0 * arg1, unsigned, 32-bit mult results in 64-bit - {name: "DIV", argLength: 2, reg: gp21, asm: "SDIV"}, // arg0 / arg1, signed - {name: "UDIV", argLength: 2, reg: gp21, asm: "UDIV"}, // arg0 / arg1, unsigned - {name: "DIVW", argLength: 2, reg: gp21, asm: "SDIVW"}, // arg0 / arg1, signed, 32 bit - {name: "UDIVW", argLength: 2, reg: gp21, asm: "UDIVW"}, // arg0 / arg1, unsigned, 32 bit - {name: "MOD", argLength: 2, reg: gp21, asm: "REM"}, // arg0 % arg1, signed - {name: "UMOD", argLength: 2, reg: gp21, asm: "UREM"}, // arg0 % arg1, unsigned - {name: "MODW", argLength: 2, reg: gp21, asm: "REMW"}, // arg0 % arg1, signed, 32 bit - {name: "UMODW", argLength: 2, reg: gp21, asm: "UREMW"}, // arg0 % arg1, unsigned, 32 bit - - {name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true}, // arg0 + arg1 - {name: "FADDD", argLength: 2, reg: fp21, asm: "FADDD", commutative: true}, // arg0 + arg1 - {name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS"}, // arg0 - arg1 - {name: "FSUBD", argLength: 2, reg: fp21, asm: "FSUBD"}, // arg0 - arg1 - {name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true}, // arg0 * arg1 - {name: "FMULD", argLength: 2, reg: fp21, asm: "FMULD", commutative: true}, // arg0 * arg1 - {name: "FNMULS", argLength: 2, reg: fp21, asm: "FNMULS", commutative: true}, // -(arg0 * arg1) - {name: "FNMULD", argLength: 2, reg: fp21, asm: "FNMULD", commutative: true}, // -(arg0 * arg1) - {name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS"}, // arg0 / arg1 - {name: "FDIVD", argLength: 2, reg: fp21, asm: "FDIVD"}, // arg0 / arg1 - - {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1 - {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64"}, // arg0 & auxInt - {name: "OR", argLength: 2, reg: gp21, asm: "ORR", commutative: true}, // arg0 | arg1 - {name: "ORconst", argLength: 1, reg: gp11, asm: "ORR", aux: "Int64"}, // arg0 | auxInt - {name: "XOR", argLength: 2, reg: gp21, asm: "EOR", commutative: true}, // arg0 ^ arg1 - {name: "XORconst", argLength: 1, reg: gp11, asm: "EOR", aux: "Int64"}, // arg0 ^ auxInt - {name: "BIC", argLength: 2, reg: gp21, asm: "BIC"}, // arg0 &^ arg1 - {name: "EON", argLength: 2, reg: gp21, asm: "EON"}, // arg0 ^ ^arg1 - {name: "ORN", argLength: 2, reg: gp21, asm: "ORN"}, // arg0 | ^arg1 + {name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "MULW", argLength: 2, reg: gp21, asm: "MULW", commutative: true, earlyOk: true}, // arg0 * arg1, 32-bit + {name: "MNEG", argLength: 2, reg: gp21, asm: "MNEG", commutative: true, earlyOk: true}, // -arg0 * arg1 + {name: "MNEGW", argLength: 2, reg: gp21, asm: "MNEGW", commutative: true, earlyOk: true}, // -arg0 * arg1, 32-bit + {name: "MULH", argLength: 2, reg: gp21, asm: "SMULH", commutative: true, earlyOk: true}, // (arg0 * arg1) >> 64, signed + {name: "UMULH", argLength: 2, reg: gp21, asm: "UMULH", commutative: true, earlyOk: true}, // (arg0 * arg1) >> 64, unsigned + {name: "MULL", argLength: 2, reg: gp21, asm: "SMULL", commutative: true, earlyOk: true}, // arg0 * arg1, signed, 32-bit mult results in 64-bit + {name: "UMULL", argLength: 2, reg: gp21, asm: "UMULL", commutative: true, earlyOk: true}, // arg0 * arg1, unsigned, 32-bit mult results in 64-bit + {name: "DIV", argLength: 2, reg: gp21, asm: "SDIV", earlyOk: true}, // arg0 / arg1, signed + {name: "UDIV", argLength: 2, reg: gp21, asm: "UDIV", earlyOk: true}, // arg0 / arg1, unsigned + {name: "DIVW", argLength: 2, reg: gp21, asm: "SDIVW", earlyOk: true}, // arg0 / arg1, signed, 32 bit + {name: "UDIVW", argLength: 2, reg: gp21, asm: "UDIVW", earlyOk: true}, // arg0 / arg1, unsigned, 32 bit + {name: "MOD", argLength: 2, reg: gp21, asm: "REM", earlyOk: true}, // arg0 % arg1, signed + {name: "UMOD", argLength: 2, reg: gp21, asm: "UREM", earlyOk: true}, // arg0 % arg1, unsigned + {name: "MODW", argLength: 2, reg: gp21, asm: "REMW", earlyOk: true}, // arg0 % arg1, signed, 32 bit + {name: "UMODW", argLength: 2, reg: gp21, asm: "UREMW", earlyOk: true}, // arg0 % arg1, unsigned, 32 bit + + {name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "FADDD", argLength: 2, reg: fp21, asm: "FADDD", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS", earlyOk: true}, // arg0 - arg1 + {name: "FSUBD", argLength: 2, reg: fp21, asm: "FSUBD", earlyOk: true}, // arg0 - arg1 + {name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "FMULD", argLength: 2, reg: fp21, asm: "FMULD", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "FNMULS", argLength: 2, reg: fp21, asm: "FNMULS", commutative: true, earlyOk: true}, // -(arg0 * arg1) + {name: "FNMULD", argLength: 2, reg: fp21, asm: "FNMULD", commutative: true, earlyOk: true}, // -(arg0 * arg1) + {name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS", earlyOk: true}, // arg0 / arg1 + {name: "FDIVD", argLength: 2, reg: fp21, asm: "FDIVD", earlyOk: true}, // arg0 / arg1 + + {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64", earlyOk: true}, // arg0 & auxInt + {name: "OR", argLength: 2, reg: gp21, asm: "ORR", commutative: true, earlyOk: true}, // arg0 | arg1 + {name: "ORconst", argLength: 1, reg: gp11, asm: "ORR", aux: "Int64", earlyOk: true}, // arg0 | auxInt + {name: "XOR", argLength: 2, reg: gp21, asm: "EOR", commutative: true, earlyOk: true}, // arg0 ^ arg1 + {name: "XORconst", argLength: 1, reg: gp11, asm: "EOR", aux: "Int64", earlyOk: true}, // arg0 ^ auxInt + {name: "BIC", argLength: 2, reg: gp21, asm: "BIC", earlyOk: true}, // arg0 &^ arg1 + {name: "EON", argLength: 2, reg: gp21, asm: "EON", earlyOk: true}, // arg0 ^ ^arg1 + {name: "ORN", argLength: 2, reg: gp21, asm: "ORN", earlyOk: true}, // arg0 | ^arg1 // unary ops - {name: "MVN", argLength: 1, reg: gp11, asm: "MVN"}, // ^arg0 - {name: "NEG", argLength: 1, reg: gp11, asm: "NEG"}, // -arg0 - {name: "NEGSflags", argLength: 1, reg: gp11flags, typ: "(UInt64,Flags)", asm: "NEGS"}, // -arg0, set flags. - {name: "NGCzerocarry", argLength: 1, reg: gp0flags1, typ: "UInt64", asm: "NGC"}, // -1 if borrowing, 0 otherwise. - {name: "FABSD", argLength: 1, reg: fp11, asm: "FABSD"}, // abs(arg0), float64 - {name: "FNEGS", argLength: 1, reg: fp11, asm: "FNEGS"}, // -arg0, float32 - {name: "FNEGD", argLength: 1, reg: fp11, asm: "FNEGD"}, // -arg0, float64 - {name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD"}, // sqrt(arg0), float64 - {name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS"}, // sqrt(arg0), float32 - {name: "FMIND", argLength: 2, reg: fp21, asm: "FMIND"}, // min(arg0, arg1) - {name: "FMINS", argLength: 2, reg: fp21, asm: "FMINS"}, // min(arg0, arg1) - {name: "FMAXD", argLength: 2, reg: fp21, asm: "FMAXD"}, // max(arg0, arg1) - {name: "FMAXS", argLength: 2, reg: fp21, asm: "FMAXS"}, // max(arg0, arg1) - {name: "REV", argLength: 1, reg: gp11, asm: "REV"}, // byte reverse, 64-bit - {name: "REVW", argLength: 1, reg: gp11, asm: "REVW"}, // byte reverse, 32-bit - {name: "REV16", argLength: 1, reg: gp11, asm: "REV16"}, // byte reverse in each 16-bit halfword, 64-bit - {name: "REV16W", argLength: 1, reg: gp11, asm: "REV16W"}, // byte reverse in each 16-bit halfword, 32-bit - {name: "RBIT", argLength: 1, reg: gp11, asm: "RBIT"}, // bit reverse, 64-bit - {name: "RBITW", argLength: 1, reg: gp11, asm: "RBITW"}, // bit reverse, 32-bit - {name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ"}, // count leading zero, 64-bit - {name: "CLZW", argLength: 1, reg: gp11, asm: "CLZW"}, // count leading zero, 32-bit - {name: "VCNT", argLength: 1, reg: fp11, asm: "VCNT"}, // count set bits for each 8-bit unit and store the result in each 8-bit unit - {name: "VUADDLV", argLength: 1, reg: fp11, asm: "VUADDLV"}, // unsigned sum of eight bytes in a 64-bit value, zero extended to 64-bit. - {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true}, - {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true}, + {name: "MVN", argLength: 1, reg: gp11, asm: "MVN", earlyOk: true}, // ^arg0 + {name: "NEG", argLength: 1, reg: gp11, asm: "NEG", earlyOk: true}, // -arg0 + {name: "NEGSflags", argLength: 1, reg: gp11flags, typ: "(UInt64,Flags)", asm: "NEGS"}, // -arg0, set flags. + {name: "NGCzerocarry", argLength: 1, reg: gp0flags1, typ: "UInt64", asm: "NGC", earlyOk: true}, // -1 if borrowing, 0 otherwise. + {name: "FABSD", argLength: 1, reg: fp11, asm: "FABSD", earlyOk: true}, // abs(arg0), float64 + {name: "FABSS", argLength: 1, reg: fp11, asm: "FABSS", earlyOk: true}, // abs(arg0), float32 + {name: "FNEGS", argLength: 1, reg: fp11, asm: "FNEGS", earlyOk: true}, // -arg0, float32 + {name: "FNEGD", argLength: 1, reg: fp11, asm: "FNEGD", earlyOk: true}, // -arg0, float64 + {name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD", earlyOk: true}, // sqrt(arg0), float64 + {name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS", earlyOk: true}, // sqrt(arg0), float32 + {name: "FMIND", argLength: 2, reg: fp21, asm: "FMIND", earlyOk: true}, // min(arg0, arg1) + {name: "FMINS", argLength: 2, reg: fp21, asm: "FMINS", earlyOk: true}, // min(arg0, arg1) + {name: "FMAXD", argLength: 2, reg: fp21, asm: "FMAXD", earlyOk: true}, // max(arg0, arg1) + {name: "FMAXS", argLength: 2, reg: fp21, asm: "FMAXS", earlyOk: true}, // max(arg0, arg1) + {name: "REV", argLength: 1, reg: gp11, asm: "REV", earlyOk: true}, // byte reverse, 64-bit + {name: "REVW", argLength: 1, reg: gp11, asm: "REVW", earlyOk: true}, // byte reverse, 32-bit + {name: "REV16", argLength: 1, reg: gp11, asm: "REV16", earlyOk: true}, // byte reverse in each 16-bit halfword, 64-bit + {name: "REV16W", argLength: 1, reg: gp11, asm: "REV16W", earlyOk: true}, // byte reverse in each 16-bit halfword, 32-bit + {name: "RBIT", argLength: 1, reg: gp11, asm: "RBIT", earlyOk: true}, // bit reverse, 64-bit + {name: "RBITW", argLength: 1, reg: gp11, asm: "RBITW", earlyOk: true}, // bit reverse, 32-bit + {name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ", earlyOk: true}, // count leading zero, 64-bit + {name: "CLZW", argLength: 1, reg: gp11, asm: "CLZW", earlyOk: true}, // count leading zero, 32-bit + {name: "VCNT", argLength: 1, reg: fp11, asm: "VCNT", earlyOk: true}, // count set bits for each 8-bit unit and store the result in each 8-bit unit + {name: "VUADDLV", argLength: 1, reg: fp11, asm: "VUADDLV", earlyOk: true}, // unsigned sum of eight bytes in a 64-bit value, zero extended to 64-bit. + {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true, earlyOk: true}, + {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true, earlyOk: true}, // 3-operand, the addend comes first - {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS"}, // +arg0 + (arg1 * arg2) - {name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD"}, // +arg0 + (arg1 * arg2) - {name: "FNMADDS", argLength: 3, reg: fp31, asm: "FNMADDS"}, // -arg0 - (arg1 * arg2) - {name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD"}, // -arg0 - (arg1 * arg2) - {name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS"}, // +arg0 - (arg1 * arg2) - {name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD"}, // +arg0 - (arg1 * arg2) - {name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS"}, // -arg0 + (arg1 * arg2) - {name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD"}, // -arg0 + (arg1 * arg2) - {name: "MADD", argLength: 3, reg: gp31, asm: "MADD"}, // +arg0 + (arg1 * arg2) - {name: "MADDW", argLength: 3, reg: gp31, asm: "MADDW"}, // +arg0 + (arg1 * arg2), 32-bit - {name: "MSUB", argLength: 3, reg: gp31, asm: "MSUB"}, // +arg0 - (arg1 * arg2) - {name: "MSUBW", argLength: 3, reg: gp31, asm: "MSUBW"}, // +arg0 - (arg1 * arg2), 32-bit + {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS", earlyOk: true}, // +arg0 + (arg1 * arg2) + {name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", earlyOk: true}, // +arg0 + (arg1 * arg2) + {name: "FNMADDS", argLength: 3, reg: fp31, asm: "FNMADDS", earlyOk: true}, // -arg0 - (arg1 * arg2) + {name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD", earlyOk: true}, // -arg0 - (arg1 * arg2) + {name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS", earlyOk: true}, // +arg0 - (arg1 * arg2) + {name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", earlyOk: true}, // +arg0 - (arg1 * arg2) + {name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS", earlyOk: true}, // -arg0 + (arg1 * arg2) + {name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD", earlyOk: true}, // -arg0 + (arg1 * arg2) + {name: "MADD", argLength: 3, reg: gp31, asm: "MADD", earlyOk: true}, // +arg0 + (arg1 * arg2) + {name: "MADDW", argLength: 3, reg: gp31, asm: "MADDW", earlyOk: true}, // +arg0 + (arg1 * arg2), 32-bit + {name: "MSUB", argLength: 3, reg: gp31, asm: "MSUB", earlyOk: true}, // +arg0 - (arg1 * arg2) + {name: "MSUBW", argLength: 3, reg: gp31, asm: "MSUBW", earlyOk: true}, // +arg0 - (arg1 * arg2), 32-bit // shifts - {name: "SLL", argLength: 2, reg: gp21, asm: "LSL"}, // arg0 << arg1, shift amount is mod 64 - {name: "SLLconst", argLength: 1, reg: gp11, asm: "LSL", aux: "Int64"}, // arg0 << auxInt, auxInt should be in the range 0 to 63. - {name: "SRL", argLength: 2, reg: gp21, asm: "LSR"}, // arg0 >> arg1, unsigned, shift amount is mod 64 - {name: "SRLconst", argLength: 1, reg: gp11, asm: "LSR", aux: "Int64"}, // arg0 >> auxInt, unsigned, auxInt should be in the range 0 to 63. - {name: "SRA", argLength: 2, reg: gp21, asm: "ASR"}, // arg0 >> arg1, signed, shift amount is mod 64 - {name: "SRAconst", argLength: 1, reg: gp11, asm: "ASR", aux: "Int64"}, // arg0 >> auxInt, signed, auxInt should be in the range 0 to 63. - {name: "ROR", argLength: 2, reg: gp21, asm: "ROR"}, // arg0 right rotate by (arg1 mod 64) bits - {name: "RORW", argLength: 2, reg: gp21, asm: "RORW"}, // arg0 right rotate by (arg1 mod 32) bits - {name: "RORconst", argLength: 1, reg: gp11, asm: "ROR", aux: "Int64"}, // arg0 right rotate by auxInt bits, auxInt should be in the range 0 to 63. - {name: "RORWconst", argLength: 1, reg: gp11, asm: "RORW", aux: "Int64"}, // uint32(arg0) right rotate by auxInt bits, auxInt should be in the range 0 to 31. - {name: "EXTRconst", argLength: 2, reg: gp21, asm: "EXTR", aux: "Int64"}, // extract 64 bits from arg0:arg1 starting at lsb auxInt, auxInt should be in the range 0 to 63. - {name: "EXTRWconst", argLength: 2, reg: gp21, asm: "EXTRW", aux: "Int64"}, // extract 32 bits from arg0[31:0]:arg1[31:0] starting at lsb auxInt and zero top 32 bits, auxInt should be in the range 0 to 31. + {name: "SLL", argLength: 2, reg: gp21, asm: "LSL", earlyOk: true}, // arg0 << arg1, shift amount is mod 64 + {name: "SLLconst", argLength: 1, reg: gp11, asm: "LSL", aux: "Int64", earlyOk: true}, // arg0 << auxInt, auxInt should be in the range 0 to 63. + {name: "SRL", argLength: 2, reg: gp21, asm: "LSR", earlyOk: true}, // arg0 >> arg1, unsigned, shift amount is mod 64 + {name: "SRLconst", argLength: 1, reg: gp11, asm: "LSR", aux: "Int64", earlyOk: true}, // arg0 >> auxInt, unsigned, auxInt should be in the range 0 to 63. + {name: "SRA", argLength: 2, reg: gp21, asm: "ASR", earlyOk: true}, // arg0 >> arg1, signed, shift amount is mod 64 + {name: "SRAconst", argLength: 1, reg: gp11, asm: "ASR", aux: "Int64", earlyOk: true}, // arg0 >> auxInt, signed, auxInt should be in the range 0 to 63. + {name: "ROR", argLength: 2, reg: gp21, asm: "ROR", earlyOk: true}, // arg0 right rotate by (arg1 mod 64) bits + {name: "RORW", argLength: 2, reg: gp21, asm: "RORW", earlyOk: true}, // arg0 right rotate by (arg1 mod 32) bits + {name: "RORconst", argLength: 1, reg: gp11, asm: "ROR", aux: "Int64", earlyOk: true}, // arg0 right rotate by auxInt bits, auxInt should be in the range 0 to 63. + {name: "RORWconst", argLength: 1, reg: gp11, asm: "RORW", aux: "Int64", earlyOk: true}, // uint32(arg0) right rotate by auxInt bits, auxInt should be in the range 0 to 31. + {name: "EXTRconst", argLength: 2, reg: gp21, asm: "EXTR", aux: "Int64", earlyOk: true}, // extract 64 bits from arg0:arg1 starting at lsb auxInt, auxInt should be in the range 0 to 63. + {name: "EXTRWconst", argLength: 2, reg: gp21, asm: "EXTRW", aux: "Int64", earlyOk: true}, // extract 32 bits from arg0[31:0]:arg1[31:0] starting at lsb auxInt and zero top 32 bits, auxInt should be in the range 0 to 31. // comparisons {name: "CMP", argLength: 2, reg: gp2flags, asm: "CMP", typ: "Flags"}, // arg0 compare to arg1 @@ -316,43 +318,43 @@ func init() { {name: "FCMPD0", argLength: 1, reg: fp1flags, asm: "FCMPD", typ: "Flags"}, // arg0 compare to 0, float64 // shifted ops - {name: "MVNshiftLL", argLength: 1, reg: gp11, asm: "MVN", aux: "Int64"}, // ^(arg0<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. - {name: "MVNshiftRA", argLength: 1, reg: gp11, asm: "MVN", aux: "Int64"}, // ^(arg0>>auxInt), signed shift, auxInt should be in the range 0 to 63. - {name: "MVNshiftRO", argLength: 1, reg: gp11, asm: "MVN", aux: "Int64"}, // ^(arg0 ROR auxInt), signed shift, auxInt should be in the range 0 to 63. - {name: "NEGshiftLL", argLength: 1, reg: gp11, asm: "NEG", aux: "Int64"}, // -(arg0<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. - {name: "NEGshiftRA", argLength: 1, reg: gp11, asm: "NEG", aux: "Int64"}, // -(arg0>>auxInt), signed shift, auxInt should be in the range 0 to 63. - {name: "ADDshiftLL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int64"}, // arg0 + arg1<>auxInt, unsigned shift, auxInt should be in the range 0 to 63. - {name: "ADDshiftRA", argLength: 2, reg: gp21, asm: "ADD", aux: "Int64"}, // arg0 + arg1>>auxInt, signed shift, auxInt should be in the range 0 to 63. - {name: "SUBshiftLL", argLength: 2, reg: gp21, asm: "SUB", aux: "Int64"}, // arg0 - arg1<>auxInt, unsigned shift, auxInt should be in the range 0 to 63. - {name: "SUBshiftRA", argLength: 2, reg: gp21, asm: "SUB", aux: "Int64"}, // arg0 - arg1>>auxInt, signed shift, auxInt should be in the range 0 to 63. - {name: "ANDshiftLL", argLength: 2, reg: gp21, asm: "AND", aux: "Int64"}, // arg0 & (arg1<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. - {name: "ANDshiftRA", argLength: 2, reg: gp21, asm: "AND", aux: "Int64"}, // arg0 & (arg1>>auxInt), signed shift, auxInt should be in the range 0 to 63. - {name: "ANDshiftRO", argLength: 2, reg: gp21, asm: "AND", aux: "Int64"}, // arg0 & (arg1 ROR auxInt), signed shift, auxInt should be in the range 0 to 63. - {name: "ORshiftLL", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64"}, // arg0 | arg1<>auxInt, unsigned shift, auxInt should be in the range 0 to 63. - {name: "ORshiftRA", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64"}, // arg0 | arg1>>auxInt, signed shift, auxInt should be in the range 0 to 63. - {name: "ORshiftRO", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64"}, // arg0 | arg1 ROR auxInt, signed shift, auxInt should be in the range 0 to 63. - {name: "XORshiftLL", argLength: 2, reg: gp21, asm: "EOR", aux: "Int64"}, // arg0 ^ arg1<>auxInt, unsigned shift, auxInt should be in the range 0 to 63. - {name: "XORshiftRA", argLength: 2, reg: gp21, asm: "EOR", aux: "Int64"}, // arg0 ^ arg1>>auxInt, signed shift, auxInt should be in the range 0 to 63. - {name: "XORshiftRO", argLength: 2, reg: gp21, asm: "EOR", aux: "Int64"}, // arg0 ^ arg1 ROR auxInt, signed shift, auxInt should be in the range 0 to 63. - {name: "BICshiftLL", argLength: 2, reg: gp21, asm: "BIC", aux: "Int64"}, // arg0 &^ (arg1<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. - {name: "BICshiftRA", argLength: 2, reg: gp21, asm: "BIC", aux: "Int64"}, // arg0 &^ (arg1>>auxInt), signed shift, auxInt should be in the range 0 to 63. - {name: "BICshiftRO", argLength: 2, reg: gp21, asm: "BIC", aux: "Int64"}, // arg0 &^ (arg1 ROR auxInt), signed shift, auxInt should be in the range 0 to 63. - {name: "EONshiftLL", argLength: 2, reg: gp21, asm: "EON", aux: "Int64"}, // arg0 ^ ^(arg1<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. - {name: "EONshiftRA", argLength: 2, reg: gp21, asm: "EON", aux: "Int64"}, // arg0 ^ ^(arg1>>auxInt), signed shift, auxInt should be in the range 0 to 63. - {name: "EONshiftRO", argLength: 2, reg: gp21, asm: "EON", aux: "Int64"}, // arg0 ^ ^(arg1 ROR auxInt), signed shift, auxInt should be in the range 0 to 63. - {name: "ORNshiftLL", argLength: 2, reg: gp21, asm: "ORN", aux: "Int64"}, // arg0 | ^(arg1<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. - {name: "ORNshiftRA", argLength: 2, reg: gp21, asm: "ORN", aux: "Int64"}, // arg0 | ^(arg1>>auxInt), signed shift, auxInt should be in the range 0 to 63. - {name: "ORNshiftRO", argLength: 2, reg: gp21, asm: "ORN", aux: "Int64"}, // arg0 | ^(arg1 ROR auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "MVNshiftLL", argLength: 1, reg: gp11, asm: "MVN", aux: "Int64", earlyOk: true}, // ^(arg0<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. + {name: "MVNshiftRA", argLength: 1, reg: gp11, asm: "MVN", aux: "Int64", earlyOk: true}, // ^(arg0>>auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "MVNshiftRO", argLength: 1, reg: gp11, asm: "MVN", aux: "Int64", earlyOk: true}, // ^(arg0 ROR auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "NEGshiftLL", argLength: 1, reg: gp11, asm: "NEG", aux: "Int64", earlyOk: true}, // -(arg0<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. + {name: "NEGshiftRA", argLength: 1, reg: gp11, asm: "NEG", aux: "Int64", earlyOk: true}, // -(arg0>>auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "ADDshiftLL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int64", earlyOk: true}, // arg0 + arg1<>auxInt, unsigned shift, auxInt should be in the range 0 to 63. + {name: "ADDshiftRA", argLength: 2, reg: gp21, asm: "ADD", aux: "Int64", earlyOk: true}, // arg0 + arg1>>auxInt, signed shift, auxInt should be in the range 0 to 63. + {name: "SUBshiftLL", argLength: 2, reg: gp21, asm: "SUB", aux: "Int64", earlyOk: true}, // arg0 - arg1<>auxInt, unsigned shift, auxInt should be in the range 0 to 63. + {name: "SUBshiftRA", argLength: 2, reg: gp21, asm: "SUB", aux: "Int64", earlyOk: true}, // arg0 - arg1>>auxInt, signed shift, auxInt should be in the range 0 to 63. + {name: "ANDshiftLL", argLength: 2, reg: gp21, asm: "AND", aux: "Int64", earlyOk: true}, // arg0 & (arg1<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. + {name: "ANDshiftRA", argLength: 2, reg: gp21, asm: "AND", aux: "Int64", earlyOk: true}, // arg0 & (arg1>>auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "ANDshiftRO", argLength: 2, reg: gp21, asm: "AND", aux: "Int64", earlyOk: true}, // arg0 & (arg1 ROR auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "ORshiftLL", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64", earlyOk: true}, // arg0 | arg1<>auxInt, unsigned shift, auxInt should be in the range 0 to 63. + {name: "ORshiftRA", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64", earlyOk: true}, // arg0 | arg1>>auxInt, signed shift, auxInt should be in the range 0 to 63. + {name: "ORshiftRO", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64", earlyOk: true}, // arg0 | arg1 ROR auxInt, signed shift, auxInt should be in the range 0 to 63. + {name: "XORshiftLL", argLength: 2, reg: gp21, asm: "EOR", aux: "Int64", earlyOk: true}, // arg0 ^ arg1<>auxInt, unsigned shift, auxInt should be in the range 0 to 63. + {name: "XORshiftRA", argLength: 2, reg: gp21, asm: "EOR", aux: "Int64", earlyOk: true}, // arg0 ^ arg1>>auxInt, signed shift, auxInt should be in the range 0 to 63. + {name: "XORshiftRO", argLength: 2, reg: gp21, asm: "EOR", aux: "Int64", earlyOk: true}, // arg0 ^ arg1 ROR auxInt, signed shift, auxInt should be in the range 0 to 63. + {name: "BICshiftLL", argLength: 2, reg: gp21, asm: "BIC", aux: "Int64", earlyOk: true}, // arg0 &^ (arg1<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. + {name: "BICshiftRA", argLength: 2, reg: gp21, asm: "BIC", aux: "Int64", earlyOk: true}, // arg0 &^ (arg1>>auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "BICshiftRO", argLength: 2, reg: gp21, asm: "BIC", aux: "Int64", earlyOk: true}, // arg0 &^ (arg1 ROR auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "EONshiftLL", argLength: 2, reg: gp21, asm: "EON", aux: "Int64", earlyOk: true}, // arg0 ^ ^(arg1<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. + {name: "EONshiftRA", argLength: 2, reg: gp21, asm: "EON", aux: "Int64", earlyOk: true}, // arg0 ^ ^(arg1>>auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "EONshiftRO", argLength: 2, reg: gp21, asm: "EON", aux: "Int64", earlyOk: true}, // arg0 ^ ^(arg1 ROR auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "ORNshiftLL", argLength: 2, reg: gp21, asm: "ORN", aux: "Int64", earlyOk: true}, // arg0 | ^(arg1<>auxInt), unsigned shift, auxInt should be in the range 0 to 63. + {name: "ORNshiftRA", argLength: 2, reg: gp21, asm: "ORN", aux: "Int64", earlyOk: true}, // arg0 | ^(arg1>>auxInt), signed shift, auxInt should be in the range 0 to 63. + {name: "ORNshiftRO", argLength: 2, reg: gp21, asm: "ORN", aux: "Int64", earlyOk: true}, // arg0 | ^(arg1 ROR auxInt), signed shift, auxInt should be in the range 0 to 63. {name: "CMPshiftLL", argLength: 2, reg: gp2flags, asm: "CMP", aux: "Int64", typ: "Flags"}, // arg0 compare to arg1<>auxInt, unsigned shift, auxInt should be in the range 0 to 63. {name: "CMPshiftRA", argLength: 2, reg: gp2flags, asm: "CMP", aux: "Int64", typ: "Flags"}, // arg0 compare to arg1>>auxInt, signed shift, auxInt should be in the range 0 to 63. @@ -367,34 +369,35 @@ func init() { // bitfield ops // for all bitfield ops lsb is auxInt>>8, width is auxInt&0xff // insert low width bits of arg1 into the result starting at bit lsb, copy other bits from arg0 - {name: "BFI", argLength: 2, reg: gp21nog, asm: "BFI", aux: "ARM64BitField", resultInArg0: true}, + {name: "BFI", argLength: 2, reg: gp21nog, asm: "BFI", aux: "ARM64BitField", resultInArg0: true, earlyOk: true}, // extract width bits of arg1 starting at bit lsb and insert at low end of result, copy other bits from arg0 - {name: "BFXIL", argLength: 2, reg: gp21nog, asm: "BFXIL", aux: "ARM64BitField", resultInArg0: true}, + {name: "BFXIL", argLength: 2, reg: gp21nog, asm: "BFXIL", aux: "ARM64BitField", resultInArg0: true, earlyOk: true}, // insert low width bits of arg0 into the result starting at bit lsb, bits to the left of the inserted bit field are set to the high/sign bit of the inserted bit field, bits to the right are zeroed - {name: "SBFIZ", argLength: 1, reg: gp11, asm: "SBFIZ", aux: "ARM64BitField"}, + {name: "SBFIZ", argLength: 1, reg: gp11, asm: "SBFIZ", aux: "ARM64BitField", earlyOk: true}, // extract width bits of arg0 starting at bit lsb and insert at low end of result, remaining high bits are set to the high/sign bit of the extracted bitfield - {name: "SBFX", argLength: 1, reg: gp11, asm: "SBFX", aux: "ARM64BitField"}, + {name: "SBFX", argLength: 1, reg: gp11, asm: "SBFX", aux: "ARM64BitField", earlyOk: true}, // insert low width bits of arg0 into the result starting at bit lsb, bits to the left and right of the inserted bit field are zeroed - {name: "UBFIZ", argLength: 1, reg: gp11, asm: "UBFIZ", aux: "ARM64BitField"}, + {name: "UBFIZ", argLength: 1, reg: gp11, asm: "UBFIZ", aux: "ARM64BitField", earlyOk: true}, // extract width bits of arg0 starting at bit lsb and insert at low end of result, remaining high bits are zeroed - {name: "UBFX", argLength: 1, reg: gp11, asm: "UBFX", aux: "ARM64BitField"}, + {name: "UBFX", argLength: 1, reg: gp11, asm: "UBFX", aux: "ARM64BitField", earlyOk: true}, // moves - {name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVD", typ: "UInt64", rematerializeable: true}, // 64 bits from auxint - {name: "FMOVSconst", argLength: 0, reg: fp01, aux: "Float64", asm: "FMOVS", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float - {name: "FMOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "FMOVD", typ: "Float64", rematerializeable: true}, // auxint as 64-bit float - - {name: "MOVDaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP") | buildReg("SB")}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVD", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB - - {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVWUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVWU", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVDload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVD", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "FMOVSload", argLength: 2, reg: fpload, aux: "SymOff", asm: "FMOVS", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "FMOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "FMOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVD", typ: "UInt64", rematerializeable: true, earlyOk: true}, // 64 bits from auxint + {name: "FMOVSconst", argLength: 0, reg: fp01, aux: "Float64", asm: "FMOVS", typ: "Float32", rematerializeable: true, earlyOk: true}, // auxint as 64-bit float, convert to 32-bit float + {name: "FMOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "FMOVD", typ: "Float64", rematerializeable: true, earlyOk: true}, // auxint as 64-bit float + + {name: "MOVDaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP").union(buildReg("SB"))}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVD", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB + + {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "Int32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVWUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVWU", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVDload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVD", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "FMOVSload", argLength: 2, reg: fpload, aux: "SymOff", asm: "FMOVS", typ: "Float32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "FMOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "FMOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "FMOVQload", argLength: 2, reg: fpload, aux: "SymOff", asm: "FMOVQ", typ: "Vec128", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. // LDP instructions load the contents of two adjacent locations in memory into registers. // Address to start loading is addr = arg0 + auxInt + aux. @@ -402,114 +405,123 @@ func init() { // y := *(*T)(addr+sizeof(T)) // arg1=mem // Returns the tuple . - {name: "LDP", argLength: 2, reg: gpload2, aux: "SymOff", asm: "LDP", typ: "(UInt64,UInt64)", faultOnNilArg0: true, symEffect: "Read"}, // T=int64 (gp reg destination) - {name: "LDPW", argLength: 2, reg: gpload2, aux: "SymOff", asm: "LDPW", typ: "(UInt32,UInt32)", faultOnNilArg0: true, symEffect: "Read"}, // T=int32 (gp reg destination) unsigned extension - {name: "LDPSW", argLength: 2, reg: gpload2, aux: "SymOff", asm: "LDPSW", typ: "(Int32,Int32)", faultOnNilArg0: true, symEffect: "Read"}, // T=int32 (gp reg destination) signed extension - {name: "FLDPD", argLength: 2, reg: fpload2, aux: "SymOff", asm: "FLDPD", typ: "(Float64,Float64)", faultOnNilArg0: true, symEffect: "Read"}, // T=float64 (fp reg destination) - {name: "FLDPS", argLength: 2, reg: fpload2, aux: "SymOff", asm: "FLDPS", typ: "(Float32,Float32)", faultOnNilArg0: true, symEffect: "Read"}, // T=float32 (fp reg destination) + {name: "LDP", argLength: 2, reg: gpload2, aux: "SymOff", asm: "LDP", typ: "(UInt64,UInt64)", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // T=int64 (gp reg destination) + {name: "LDPW", argLength: 2, reg: gpload2, aux: "SymOff", asm: "LDPW", typ: "(UInt32,UInt32)", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // T=int32 (gp reg destination) unsigned extension + {name: "LDPSW", argLength: 2, reg: gpload2, aux: "SymOff", asm: "LDPSW", typ: "(Int32,Int32)", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // T=int32 (gp reg destination) signed extension + {name: "FLDPD", argLength: 2, reg: fpload2, aux: "SymOff", asm: "FLDPD", typ: "(Float64,Float64)", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // T=float64 (fp reg destination) + {name: "FLDPS", argLength: 2, reg: fpload2, aux: "SymOff", asm: "FLDPS", typ: "(Float32,Float32)", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // T=float32 (fp reg destination) + {name: "FLDPQ", argLength: 2, reg: fpload2, aux: "SymOff", asm: "FLDPQ", typ: "(Vec128,Vec128)", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // T=vec128 (fp reg destination) // register indexed load - {name: "MOVDloadidx", argLength: 3, reg: gp2load, asm: "MOVD", typ: "UInt64"}, // load 64-bit dword from arg0 + arg1, arg2 = mem. - {name: "MOVWloadidx", argLength: 3, reg: gp2load, asm: "MOVW", typ: "Int32"}, // load 32-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. - {name: "MOVWUloadidx", argLength: 3, reg: gp2load, asm: "MOVWU", typ: "UInt32"}, // load 32-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. - {name: "MOVHloadidx", argLength: 3, reg: gp2load, asm: "MOVH", typ: "Int16"}, // load 16-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. - {name: "MOVHUloadidx", argLength: 3, reg: gp2load, asm: "MOVHU", typ: "UInt16"}, // load 16-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. - {name: "MOVBloadidx", argLength: 3, reg: gp2load, asm: "MOVB", typ: "Int8"}, // load 8-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. - {name: "MOVBUloadidx", argLength: 3, reg: gp2load, asm: "MOVBU", typ: "UInt8"}, // load 8-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. - {name: "FMOVSloadidx", argLength: 3, reg: fp2load, asm: "FMOVS", typ: "Float32"}, // load 32-bit float from arg0 + arg1, arg2=mem. - {name: "FMOVDloadidx", argLength: 3, reg: fp2load, asm: "FMOVD", typ: "Float64"}, // load 64-bit float from arg0 + arg1, arg2=mem. + {name: "MOVDloadidx", argLength: 3, reg: gp2load, asm: "MOVD", typ: "UInt64", addrSinkArg0: true, addrSinkArg1: true}, // load 64-bit dword from arg0 + arg1, arg2 = mem. + {name: "MOVWloadidx", argLength: 3, reg: gp2load, asm: "MOVW", typ: "Int32", addrSinkArg0: true, addrSinkArg1: true}, // load 32-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. + {name: "MOVWUloadidx", argLength: 3, reg: gp2load, asm: "MOVWU", typ: "UInt32", addrSinkArg0: true, addrSinkArg1: true}, // load 32-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. + {name: "MOVHloadidx", argLength: 3, reg: gp2load, asm: "MOVH", typ: "Int16", addrSinkArg0: true, addrSinkArg1: true}, // load 16-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. + {name: "MOVHUloadidx", argLength: 3, reg: gp2load, asm: "MOVHU", typ: "UInt16", addrSinkArg0: true, addrSinkArg1: true}, // load 16-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. + {name: "MOVBloadidx", argLength: 3, reg: gp2load, asm: "MOVB", typ: "Int8", addrSinkArg0: true, addrSinkArg1: true}, // load 8-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. + {name: "MOVBUloadidx", argLength: 3, reg: gp2load, asm: "MOVBU", typ: "UInt8", addrSinkArg0: true, addrSinkArg1: true}, // load 8-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. + {name: "FMOVSloadidx", argLength: 3, reg: fp2load, asm: "FMOVS", typ: "Float32", addrSinkArg0: true, addrSinkArg1: true}, // load 32-bit float from arg0 + arg1, arg2=mem. + {name: "FMOVDloadidx", argLength: 3, reg: fp2load, asm: "FMOVD", typ: "Float64", addrSinkArg0: true, addrSinkArg1: true}, // load 64-bit float from arg0 + arg1, arg2=mem. // shifted register indexed load - {name: "MOVHloadidx2", argLength: 3, reg: gp2load, asm: "MOVH", typ: "Int16"}, // load 16-bit half-word from arg0 + arg1*2, sign-extended to 64-bit, arg2=mem. - {name: "MOVHUloadidx2", argLength: 3, reg: gp2load, asm: "MOVHU", typ: "UInt16"}, // load 16-bit half-word from arg0 + arg1*2, zero-extended to 64-bit, arg2=mem. - {name: "MOVWloadidx4", argLength: 3, reg: gp2load, asm: "MOVW", typ: "Int32"}, // load 32-bit word from arg0 + arg1*4, sign-extended to 64-bit, arg2=mem. - {name: "MOVWUloadidx4", argLength: 3, reg: gp2load, asm: "MOVWU", typ: "UInt32"}, // load 32-bit word from arg0 + arg1*4, zero-extended to 64-bit, arg2=mem. - {name: "MOVDloadidx8", argLength: 3, reg: gp2load, asm: "MOVD", typ: "UInt64"}, // load 64-bit double-word from arg0 + arg1*8, arg2 = mem. - {name: "FMOVSloadidx4", argLength: 3, reg: fp2load, asm: "FMOVS", typ: "Float32"}, // load 32-bit float from arg0 + arg1*4, arg2 = mem. - {name: "FMOVDloadidx8", argLength: 3, reg: fp2load, asm: "FMOVD", typ: "Float64"}, // load 64-bit float from arg0 + arg1*8, arg2 = mem. - - {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVDstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "FMOVSstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "FMOVS", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "FMOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "FMOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVHloadidx2", argLength: 3, reg: gp2load, asm: "MOVH", typ: "Int16", addrSinkArg0: true}, // load 16-bit half-word from arg0 + arg1*2, sign-extended to 64-bit, arg2=mem. + {name: "MOVHUloadidx2", argLength: 3, reg: gp2load, asm: "MOVHU", typ: "UInt16", addrSinkArg0: true}, // load 16-bit half-word from arg0 + arg1*2, zero-extended to 64-bit, arg2=mem. + {name: "MOVWloadidx4", argLength: 3, reg: gp2load, asm: "MOVW", typ: "Int32", addrSinkArg0: true}, // load 32-bit word from arg0 + arg1*4, sign-extended to 64-bit, arg2=mem. + {name: "MOVWUloadidx4", argLength: 3, reg: gp2load, asm: "MOVWU", typ: "UInt32", addrSinkArg0: true}, // load 32-bit word from arg0 + arg1*4, zero-extended to 64-bit, arg2=mem. + {name: "MOVDloadidx8", argLength: 3, reg: gp2load, asm: "MOVD", typ: "UInt64", addrSinkArg0: true}, // load 64-bit double-word from arg0 + arg1*8, arg2 = mem. + {name: "FMOVSloadidx4", argLength: 3, reg: fp2load, asm: "FMOVS", typ: "Float32", addrSinkArg0: true}, // load 32-bit float from arg0 + arg1*4, arg2 = mem. + {name: "FMOVDloadidx8", argLength: 3, reg: fp2load, asm: "FMOVD", typ: "Float64", addrSinkArg0: true}, // load 64-bit float from arg0 + arg1*8, arg2 = mem. + + {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVDstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "FMOVSstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "FMOVS", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "FMOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "FMOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "FMOVQstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "FMOVQ", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 16 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. // STP instructions store the contents of two registers to adjacent locations in memory. // Address to start storing is addr = arg0 + auxInt + aux. // *(*T)(addr) = arg1 // *(*T)(addr+sizeof(T)) = arg2 // arg3=mem. Returns mem. - {name: "STP", argLength: 4, reg: gpstore2, aux: "SymOff", asm: "STP", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // T=int64 (gp reg source) - {name: "STPW", argLength: 4, reg: gpstore2, aux: "SymOff", asm: "STPW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // T=int32 (gp reg source) - {name: "FSTPD", argLength: 4, reg: fpstore2, aux: "SymOff", asm: "FSTPD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // T=float64 (fp reg source) - {name: "FSTPS", argLength: 4, reg: fpstore2, aux: "SymOff", asm: "FSTPS", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // T=float32 (fp reg source) + {name: "STP", argLength: 4, reg: gpstore2, aux: "SymOff", asm: "STP", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // T=int64 (gp reg source) + {name: "STPW", argLength: 4, reg: gpstore2, aux: "SymOff", asm: "STPW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // T=int32 (gp reg source) + {name: "FSTPD", argLength: 4, reg: fpstore2, aux: "SymOff", asm: "FSTPD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // T=float64 (fp reg source) + {name: "FSTPS", argLength: 4, reg: fpstore2, aux: "SymOff", asm: "FSTPS", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // T=float32 (fp reg source) + {name: "FSTPQ", argLength: 4, reg: fpstore2, aux: "SymOff", asm: "FSTPQ", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // T=vec128 (fp reg source) // register indexed store - {name: "MOVBstoreidx", argLength: 4, reg: gpstore2, asm: "MOVB", typ: "Mem"}, // store 1 byte of arg2 to arg0 + arg1, arg3 = mem. - {name: "MOVHstoreidx", argLength: 4, reg: gpstore2, asm: "MOVH", typ: "Mem"}, // store 2 bytes of arg2 to arg0 + arg1, arg3 = mem. - {name: "MOVWstoreidx", argLength: 4, reg: gpstore2, asm: "MOVW", typ: "Mem"}, // store 4 bytes of arg2 to arg0 + arg1, arg3 = mem. - {name: "MOVDstoreidx", argLength: 4, reg: gpstore2, asm: "MOVD", typ: "Mem"}, // store 8 bytes of arg2 to arg0 + arg1, arg3 = mem. - {name: "FMOVSstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVS", typ: "Mem"}, // store 32-bit float of arg2 to arg0 + arg1, arg3=mem. - {name: "FMOVDstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVD", typ: "Mem"}, // store 64-bit float of arg2 to arg0 + arg1, arg3=mem. + {name: "MOVBstoreidx", argLength: 4, reg: gpstore2, asm: "MOVB", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store 1 byte of arg2 to arg0 + arg1, arg3 = mem. + {name: "MOVHstoreidx", argLength: 4, reg: gpstore2, asm: "MOVH", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store 2 bytes of arg2 to arg0 + arg1, arg3 = mem. + {name: "MOVWstoreidx", argLength: 4, reg: gpstore2, asm: "MOVW", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store 4 bytes of arg2 to arg0 + arg1, arg3 = mem. + {name: "MOVDstoreidx", argLength: 4, reg: gpstore2, asm: "MOVD", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store 8 bytes of arg2 to arg0 + arg1, arg3 = mem. + {name: "FMOVSstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVS", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store 32-bit float of arg2 to arg0 + arg1, arg3=mem. + {name: "FMOVDstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVD", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store 64-bit float of arg2 to arg0 + arg1, arg3=mem. // shifted register indexed store - {name: "MOVHstoreidx2", argLength: 4, reg: gpstore2, asm: "MOVH", typ: "Mem"}, // store 2 bytes of arg2 to arg0 + arg1*2, arg3 = mem. - {name: "MOVWstoreidx4", argLength: 4, reg: gpstore2, asm: "MOVW", typ: "Mem"}, // store 4 bytes of arg2 to arg0 + arg1*4, arg3 = mem. - {name: "MOVDstoreidx8", argLength: 4, reg: gpstore2, asm: "MOVD", typ: "Mem"}, // store 8 bytes of arg2 to arg0 + arg1*8, arg3 = mem. - {name: "FMOVSstoreidx4", argLength: 4, reg: fpstoreidx, asm: "FMOVS", typ: "Mem"}, // store 32-bit float of arg2 to arg0 + arg1*4, arg3=mem. - {name: "FMOVDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "FMOVD", typ: "Mem"}, // store 64-bit float of arg2 to arg0 + arg1*8, arg3=mem. + {name: "MOVHstoreidx2", argLength: 4, reg: gpstore2, asm: "MOVH", typ: "Mem", addrSinkArg0: true}, // store 2 bytes of arg2 to arg0 + arg1*2, arg3 = mem. + {name: "MOVWstoreidx4", argLength: 4, reg: gpstore2, asm: "MOVW", typ: "Mem", addrSinkArg0: true}, // store 4 bytes of arg2 to arg0 + arg1*4, arg3 = mem. + {name: "MOVDstoreidx8", argLength: 4, reg: gpstore2, asm: "MOVD", typ: "Mem", addrSinkArg0: true}, // store 8 bytes of arg2 to arg0 + arg1*8, arg3 = mem. + {name: "FMOVSstoreidx4", argLength: 4, reg: fpstoreidx, asm: "FMOVS", typ: "Mem", addrSinkArg0: true}, // store 32-bit float of arg2 to arg0 + arg1*4, arg3=mem. + {name: "FMOVDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "FMOVD", typ: "Mem", addrSinkArg0: true}, // store 64-bit float of arg2 to arg0 + arg1*8, arg3=mem. - {name: "FMOVDgpfp", argLength: 1, reg: gpfp, asm: "FMOVD"}, // move int64 to float64 (no conversion) - {name: "FMOVDfpgp", argLength: 1, reg: fpgp, asm: "FMOVD"}, // move float64 to int64 (no conversion) - {name: "FMOVSgpfp", argLength: 1, reg: gpfp, asm: "FMOVS"}, // move 32bits from int to float reg (no conversion) - {name: "FMOVSfpgp", argLength: 1, reg: fpgp, asm: "FMOVS"}, // move 32bits from float to int reg, zero extend (no conversion) + {name: "FMOVDgpfp", argLength: 1, reg: gpfp, asm: "FMOVD", earlyOk: true}, // move int64 to float64 (no conversion) + {name: "FMOVDfpgp", argLength: 1, reg: fpgp, asm: "FMOVD", earlyOk: true}, // move float64 to int64 (no conversion) + {name: "FMOVSgpfp", argLength: 1, reg: gpfp, asm: "FMOVS", earlyOk: true}, // move 32bits from int to float reg (no conversion) + {name: "FMOVSfpgp", argLength: 1, reg: fpgp, asm: "FMOVS", earlyOk: true}, // move 32bits from float to int reg, zero extend (no conversion) // conversions - {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte - {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte - {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"}, // move from arg0, sign-extended from half - {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half - {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"}, // move from arg0, sign-extended from word - {name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU"}, // move from arg0, unsign-extended from word - {name: "MOVDreg", argLength: 1, reg: gp11, asm: "MOVD"}, // move from arg0 - - {name: "MOVDnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true}, // nop, return arg0 in same register - - {name: "SCVTFWS", argLength: 1, reg: gpfp, asm: "SCVTFWS"}, // int32 -> float32 - {name: "SCVTFWD", argLength: 1, reg: gpfp, asm: "SCVTFWD"}, // int32 -> float64 - {name: "UCVTFWS", argLength: 1, reg: gpfp, asm: "UCVTFWS"}, // uint32 -> float32 - {name: "UCVTFWD", argLength: 1, reg: gpfp, asm: "UCVTFWD"}, // uint32 -> float64 - {name: "SCVTFS", argLength: 1, reg: gpfp, asm: "SCVTFS"}, // int64 -> float32 - {name: "SCVTFD", argLength: 1, reg: gpfp, asm: "SCVTFD"}, // int64 -> float64 - {name: "UCVTFS", argLength: 1, reg: gpfp, asm: "UCVTFS"}, // uint64 -> float32 - {name: "UCVTFD", argLength: 1, reg: gpfp, asm: "UCVTFD"}, // uint64 -> float64 - {name: "FCVTZSSW", argLength: 1, reg: fpgp, asm: "FCVTZSSW"}, // float32 -> int32 - {name: "FCVTZSDW", argLength: 1, reg: fpgp, asm: "FCVTZSDW"}, // float64 -> int32 - {name: "FCVTZUSW", argLength: 1, reg: fpgp, asm: "FCVTZUSW"}, // float32 -> uint32 - {name: "FCVTZUDW", argLength: 1, reg: fpgp, asm: "FCVTZUDW"}, // float64 -> uint32 - {name: "FCVTZSS", argLength: 1, reg: fpgp, asm: "FCVTZSS"}, // float32 -> int64 - {name: "FCVTZSD", argLength: 1, reg: fpgp, asm: "FCVTZSD"}, // float64 -> int64 - {name: "FCVTZUS", argLength: 1, reg: fpgp, asm: "FCVTZUS"}, // float32 -> uint64 - {name: "FCVTZUD", argLength: 1, reg: fpgp, asm: "FCVTZUD"}, // float64 -> uint64 - {name: "FCVTSD", argLength: 1, reg: fp11, asm: "FCVTSD"}, // float32 -> float64 - {name: "FCVTDS", argLength: 1, reg: fp11, asm: "FCVTDS"}, // float64 -> float32 - - // floating-point round to integral - {name: "FRINTAD", argLength: 1, reg: fp11, asm: "FRINTAD"}, - {name: "FRINTMD", argLength: 1, reg: fp11, asm: "FRINTMD"}, - {name: "FRINTND", argLength: 1, reg: fp11, asm: "FRINTND"}, - {name: "FRINTPD", argLength: 1, reg: fp11, asm: "FRINTPD"}, - {name: "FRINTZD", argLength: 1, reg: fp11, asm: "FRINTZD"}, + {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB", earlyOk: true}, // move from arg0, sign-extended from byte + {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU", earlyOk: true}, // move from arg0, unsign-extended from byte + {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH", earlyOk: true}, // move from arg0, sign-extended from half + {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU", earlyOk: true}, // move from arg0, unsign-extended from half + {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW", earlyOk: true}, // move from arg0, sign-extended from word + {name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU", earlyOk: true}, // move from arg0, unsign-extended from word + {name: "MOVDreg", argLength: 1, reg: gp11, asm: "MOVD", earlyOk: true}, // move from arg0 + + {name: "MOVDnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true, earlyOk: true}, // nop, return arg0 in same register + + {name: "SCVTFWS", argLength: 1, reg: gpfp, asm: "SCVTFWS", earlyOk: true}, // int32 -> float32 + {name: "SCVTFWD", argLength: 1, reg: gpfp, asm: "SCVTFWD", earlyOk: true}, // int32 -> float64 + {name: "UCVTFWS", argLength: 1, reg: gpfp, asm: "UCVTFWS", earlyOk: true}, // uint32 -> float32 + {name: "UCVTFWD", argLength: 1, reg: gpfp, asm: "UCVTFWD", earlyOk: true}, // uint32 -> float64 + {name: "SCVTFS", argLength: 1, reg: gpfp, asm: "SCVTFS", earlyOk: true}, // int64 -> float32 + {name: "SCVTFD", argLength: 1, reg: gpfp, asm: "SCVTFD", earlyOk: true}, // int64 -> float64 + {name: "UCVTFS", argLength: 1, reg: gpfp, asm: "UCVTFS", earlyOk: true}, // uint64 -> float32 + {name: "UCVTFD", argLength: 1, reg: gpfp, asm: "UCVTFD", earlyOk: true}, // uint64 -> float64 + {name: "FCVTZSSW", argLength: 1, reg: fpgp, asm: "FCVTZSSW", earlyOk: true}, // float32 -> int32 + {name: "FCVTZSDW", argLength: 1, reg: fpgp, asm: "FCVTZSDW", earlyOk: true}, // float64 -> int32 + {name: "FCVTZUSW", argLength: 1, reg: fpgp, asm: "FCVTZUSW", earlyOk: true}, // float32 -> uint32 + {name: "FCVTZUDW", argLength: 1, reg: fpgp, asm: "FCVTZUDW", earlyOk: true}, // float64 -> uint32 + {name: "FCVTZSS", argLength: 1, reg: fpgp, asm: "FCVTZSS", earlyOk: true}, // float32 -> int64 + {name: "FCVTZSD", argLength: 1, reg: fpgp, asm: "FCVTZSD", earlyOk: true}, // float64 -> int64 + {name: "FCVTZUS", argLength: 1, reg: fpgp, asm: "FCVTZUS", earlyOk: true}, // float32 -> uint64 + {name: "FCVTZUD", argLength: 1, reg: fpgp, asm: "FCVTZUD", earlyOk: true}, // float64 -> uint64 + {name: "FCVTSD", argLength: 1, reg: fp11, asm: "FCVTSD", earlyOk: true}, // float32 -> float64 + {name: "FCVTDS", argLength: 1, reg: fp11, asm: "FCVTDS", earlyOk: true}, // float64 -> float32 + + // 64-bit floating-point round to integers in 64-bit FP format + {name: "FRINTAD", argLength: 1, reg: fp11, asm: "FRINTAD", earlyOk: true}, // Round (ties Away from zero; 0.5 -> 1, -0.5 -> -1) + {name: "FRINTMD", argLength: 1, reg: fp11, asm: "FRINTMD", earlyOk: true}, // Floor (towards Minus; 0.5 -> 0, -0.5 -> -1) + {name: "FRINTND", argLength: 1, reg: fp11, asm: "FRINTND", earlyOk: true}, // Round (ties to even; ; 0.5 -> 0, 1.5 -> 2) + {name: "FRINTPD", argLength: 1, reg: fp11, asm: "FRINTPD", earlyOk: true}, // Ceil (towards Positive; 0.5 -> 1, -0.5 -> 0) + {name: "FRINTZD", argLength: 1, reg: fp11, asm: "FRINTZD", earlyOk: true}, // Trunc (towards Zero; 0.5 -> 0, -0.5 -> 0)) + // 32-bit floating-point round to integers in 32-bit FP format + {name: "FRINTAS", argLength: 1, reg: fp11, asm: "FRINTAS", earlyOk: true}, // Round (ties Away from zero; 0.5 -> 1, -0.5 -> -1) + {name: "FRINTMS", argLength: 1, reg: fp11, asm: "FRINTMS", earlyOk: true}, // Floor (towards Minus; 0.5 -> 0, -0.5 -> -1) + {name: "FRINTNS", argLength: 1, reg: fp11, asm: "FRINTNS", earlyOk: true}, // Round (ties to even; ; 0.5 -> 0, 1.5 -> 2) + {name: "FRINTPS", argLength: 1, reg: fp11, asm: "FRINTPS", earlyOk: true}, // Ceil (towards Positive; 0.5 -> 1, -0.5 -> 0) + {name: "FRINTZS", argLength: 1, reg: fp11, asm: "FRINTZS", earlyOk: true}, // Trunc (towards Zero; 0.5 -> 0, -0.5 -> 0)) // conditional instructions; auxint is // one of the arm64 comparison pseudo-ops (LessThan, LessThanU, etc.) - {name: "CSEL", argLength: 3, reg: gp2flags1, asm: "CSEL", aux: "CCop"}, // auxint(flags) ? arg0 : arg1 - {name: "CSEL0", argLength: 2, reg: gp1flags1, asm: "CSEL", aux: "CCop"}, // auxint(flags) ? arg0 : 0 - {name: "CSINC", argLength: 3, reg: gp2flags1, asm: "CSINC", aux: "CCop"}, // auxint(flags) ? arg0 : arg1 + 1 - {name: "CSINV", argLength: 3, reg: gp2flags1, asm: "CSINV", aux: "CCop"}, // auxint(flags) ? arg0 : ^arg1 - {name: "CSNEG", argLength: 3, reg: gp2flags1, asm: "CSNEG", aux: "CCop"}, // auxint(flags) ? arg0 : -arg1 - {name: "CSETM", argLength: 1, reg: readflags, asm: "CSETM", aux: "CCop"}, // auxint(flags) ? -1 : 0 + {name: "CSEL", argLength: 3, reg: gp2flags1, asm: "CSEL", aux: "CCop", earlyOk: true}, // auxint(flags) ? arg0 : arg1 + {name: "CSEL0", argLength: 2, reg: gp1flags1, asm: "CSEL", aux: "CCop", earlyOk: true}, // auxint(flags) ? arg0 : 0 + {name: "CSINC", argLength: 3, reg: gp2flags1, asm: "CSINC", aux: "CCop", earlyOk: true}, // auxint(flags) ? arg0 : arg1 + 1 + {name: "CSINV", argLength: 3, reg: gp2flags1, asm: "CSINV", aux: "CCop", earlyOk: true}, // auxint(flags) ? arg0 : ^arg1 + {name: "CSNEG", argLength: 3, reg: gp2flags1, asm: "CSNEG", aux: "CCop", earlyOk: true}, // auxint(flags) ? arg0 : -arg1 + {name: "CSETM", argLength: 1, reg: readflags, asm: "CSETM", aux: "CCop", earlyOk: true}, // auxint(flags) ? -1 : 0 // conditional comparison instructions; auxint is // combination of Cond, Nzcv and optional ConstValue @@ -517,45 +529,47 @@ func init() { // If the condition 'Cond' evaluates to true against current flags, // flags are set to the result of the comparison operation. // Otherwise, flags are set to the fallback value 'Nzcv'. - {name: "CCMP", argLength: 3, reg: gp2flagsflags, asm: "CCMP", aux: "ARM64ConditionalParams", typ: "Flag"}, // If Cond then flags = CMP arg0 arg1 else flags = Nzcv - {name: "CCMN", argLength: 3, reg: gp2flagsflags, asm: "CCMN", aux: "ARM64ConditionalParams", typ: "Flag"}, // If Cond then flags = CMN arg0 arg1 else flags = Nzcv - {name: "CCMPconst", argLength: 2, reg: gp1flagsflags, asm: "CCMP", aux: "ARM64ConditionalParams", typ: "Flag"}, // If Cond then flags = CMPconst [ConstValue] arg0 else flags = Nzcv - {name: "CCMNconst", argLength: 2, reg: gp1flagsflags, asm: "CCMN", aux: "ARM64ConditionalParams", typ: "Flag"}, // If Cond then flags = CMNconst [ConstValue] arg0 else flags = Nzcv + {name: "CCMP", argLength: 3, reg: gp2flagsflags, asm: "CCMP", aux: "ARM64ConditionalParams", typ: "Flags"}, // If Cond then flags = CMP arg0 arg1 else flags = Nzcv + {name: "CCMN", argLength: 3, reg: gp2flagsflags, asm: "CCMN", aux: "ARM64ConditionalParams", typ: "Flags"}, // If Cond then flags = CMN arg0 arg1 else flags = Nzcv + {name: "CCMPconst", argLength: 2, reg: gp1flagsflags, asm: "CCMP", aux: "ARM64ConditionalParams", typ: "Flags"}, // If Cond then flags = CMPconst [ConstValue] arg0 else flags = Nzcv + {name: "CCMNconst", argLength: 2, reg: gp1flagsflags, asm: "CCMN", aux: "ARM64ConditionalParams", typ: "Flags"}, // If Cond then flags = CMNconst [ConstValue] arg0 else flags = Nzcv - {name: "CCMPW", argLength: 3, reg: gp2flagsflags, asm: "CCMPW", aux: "ARM64ConditionalParams", typ: "Flag"}, // If Cond then flags = CMPW arg0 arg1 else flags = Nzcv - {name: "CCMNW", argLength: 3, reg: gp2flagsflags, asm: "CCMNW", aux: "ARM64ConditionalParams", typ: "Flag"}, // If Cond then flags = CMNW arg0 arg1 else flags = Nzcv - {name: "CCMPWconst", argLength: 2, reg: gp1flagsflags, asm: "CCMPW", aux: "ARM64ConditionalParams", typ: "Flag"}, // If Cond then flags = CCMPWconst [ConstValue] arg0 else flags = Nzcv - {name: "CCMNWconst", argLength: 2, reg: gp1flagsflags, asm: "CCMNW", aux: "ARM64ConditionalParams", typ: "Flag"}, // If Cond then flags = CCMNWconst [ConstValue] arg0 else flags = Nzcv + {name: "CCMPW", argLength: 3, reg: gp2flagsflags, asm: "CCMPW", aux: "ARM64ConditionalParams", typ: "Flags"}, // If Cond then flags = CMPW arg0 arg1 else flags = Nzcv + {name: "CCMNW", argLength: 3, reg: gp2flagsflags, asm: "CCMNW", aux: "ARM64ConditionalParams", typ: "Flags"}, // If Cond then flags = CMNW arg0 arg1 else flags = Nzcv + {name: "CCMPWconst", argLength: 2, reg: gp1flagsflags, asm: "CCMPW", aux: "ARM64ConditionalParams", typ: "Flags"}, // If Cond then flags = CCMPWconst [ConstValue] arg0 else flags = Nzcv + {name: "CCMNWconst", argLength: 2, reg: gp1flagsflags, asm: "CCMNW", aux: "ARM64ConditionalParams", typ: "Flags"}, // If Cond then flags = CCMNWconst [ConstValue] arg0 else flags = Nzcv // function calls - {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem - {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem - {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{gpsp, buildReg("R26"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem - {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtailinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{gpsp, buildReg("R26"), regMask{}}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem // pseudo-ops - {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil. arg1=mem. - - {name: "Equal", argLength: 1, reg: readflags}, // bool, true flags encode x==y false otherwise. - {name: "NotEqual", argLength: 1, reg: readflags}, // bool, true flags encode x!=y false otherwise. - {name: "LessThan", argLength: 1, reg: readflags}, // bool, true flags encode signed xy false otherwise. - {name: "GreaterEqual", argLength: 1, reg: readflags}, // bool, true flags encode signed x>=y false otherwise. - {name: "LessThanU", argLength: 1, reg: readflags}, // bool, true flags encode unsigned xy false otherwise. - {name: "GreaterEqualU", argLength: 1, reg: readflags}, // bool, true flags encode unsigned x>=y false otherwise. - {name: "LessThanF", argLength: 1, reg: readflags}, // bool, true flags encode floating-point xy false otherwise. - {name: "GreaterEqualF", argLength: 1, reg: readflags}, // bool, true flags encode floating-point x>=y false otherwise. - {name: "NotLessThanF", argLength: 1, reg: readflags}, // bool, true flags encode floating-point x>=y || x is unordered with y, false otherwise. - {name: "NotLessEqualF", argLength: 1, reg: readflags}, // bool, true flags encode floating-point x>y || x is unordered with y, false otherwise. - {name: "NotGreaterThanF", argLength: 1, reg: readflags}, // bool, true flags encode floating-point x<=y || x is unordered with y, false otherwise. - {name: "NotGreaterEqualF", argLength: 1, reg: readflags}, // bool, true flags encode floating-point x=y but without honoring overflow, false otherwise. + {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil. arg1=mem. + {name: "LoweredMemEq", argLength: 4, reg: regInfo{inputs: []regMask{buildReg("R0"), buildReg("R1"), buildReg("R2")}, outputs: []regMask{buildReg("R0")}, clobbers: callerSave}, typ: "Bool", faultOnNilArg0: true, faultOnNilArg1: true, clobberFlags: true, call: true}, // arg0, arg1 - pointers to memory, arg2=size, arg3=mem. + + {name: "Equal", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode x==y false otherwise. + {name: "NotEqual", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode x!=y false otherwise. + {name: "LessThan", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode signed xy false otherwise. + {name: "GreaterEqual", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode signed x>=y false otherwise. + {name: "LessThanU", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode unsigned xy false otherwise. + {name: "GreaterEqualU", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode unsigned x>=y false otherwise. + {name: "LessThanF", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode floating-point xy false otherwise. + {name: "GreaterEqualF", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode floating-point x>=y false otherwise. + {name: "NotLessThanF", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode floating-point x>=y || x is unordered with y, false otherwise. + {name: "NotLessEqualF", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode floating-point x>y || x is unordered with y, false otherwise. + {name: "NotGreaterThanF", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode floating-point x<=y || x is unordered with y, false otherwise. + {name: "NotGreaterEqualF", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode floating-point x=y but without honoring overflow, false otherwise. // medium zeroing // arg0 = address of memory to zero @@ -570,6 +584,7 @@ func init() { inputs: []regMask{gp}, }, faultOnNilArg0: true, + addrSinkArg0: true, }, // large zeroing @@ -586,6 +601,7 @@ func init() { clobbersArg0: true, }, faultOnNilArg0: true, + addrSinkArg0: true, needIntTemp: true, }, @@ -600,11 +616,13 @@ func init() { aux: "Int64", argLength: 3, reg: regInfo{ - inputs: []regMask{gp &^ r25, gp &^ r25}, - clobbers: r25 | f16to17, // TODO: figure out needIntTemp + x2 for floats + inputs: []regMask{gp.minus(r25), gp.minus(r25)}, + clobbers: r25.union(f16to17), // TODO: figure out needIntTemp + x2 for floats }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // large copying @@ -618,13 +636,15 @@ func init() { aux: "Int64", argLength: 3, reg: regInfo{ - inputs: []regMask{gp &^ r24to25, gp &^ r24to25}, - clobbers: r24to25 | f16to17, // TODO: figure out needIntTemp x2 + x2 for floats + inputs: []regMask{gp.minus(r24to25), gp.minus(r24to25)}, + clobbers: r24to25.union(f16to17), // TODO: figure out needIntTemp x2 + x2 for floats clobbersArg0: true, clobbersArg1: true, }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // Scheduler ensures LoweredGetClosurePtr occurs only in entry block, @@ -761,7 +781,7 @@ func init() { // but clobbers R30 (LR) because it's a call. // R16 and R17 may be clobbered by linker trampoline. // Returns a pointer to a write barrier buffer in R25. - {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ gpg) | buildReg("R16 R17 R30"), outputs: []regMask{buildReg("R25")}}, clobberFlags: true, aux: "Int64"}, + {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave.minus(gpg).union(buildReg("R16 R17 R30")), outputs: []regMask{buildReg("R25")}}, clobberFlags: true, aux: "Int64"}, // LoweredPanicBoundsRR takes x and y, two values that caused a bounds check to fail. // the RC and CR versions are used when one of the arguments is a constant. CC is used @@ -779,7 +799,11 @@ func init() { // Publication barrier {name: "DMB", argLength: 1, aux: "Int64", asm: "DMB", hasSideEffects: true}, // Do data barrier. arg0=memory, aux=option. - {name: "ZERO", zeroWidth: true, fixedReg: true}, // reads-as-zero register + {name: "ZERO", zeroWidth: true, fixedReg: true, earlyOk: true}, // reads-as-zero register + + // Broadcast constant to each lane of a SIMD register. aux=constant. + // TODO: add the other arrangements after assembler supports them, to be used in simdgen-generated opt rules. + {name: "VMOVI16B", argLength: 0, reg: fp01, asm: "VMOVI", aux: "UInt8", commutative: false, typ: "Vec128", resultInArg0: false}, } blocks := []blockData{ @@ -819,13 +843,15 @@ func init() { name: "ARM64", pkg: "cmd/internal/obj/arm64", genfile: "../../arm64/ssa.go", - ops: ops, + genSIMDfile: "../../arm64/simdssa.go", + ops: append(ops, simdARM64Ops(fp11, fp21, fp31, fpgp, fpgpfp, fp21)...), blocks: blocks, regnames: regNamesARM64, ParamIntRegNames: "R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15", ParamFloatRegNames: "F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15", gpregmask: gp, fpregmask: fp, + simdregmask: fp, framepointerreg: -1, // not used linkreg: int8(num["R30"]), }) diff --git a/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules b/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules index 8c43b960b9d964..7945a5454dc578 100644 --- a/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules +++ b/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules @@ -29,7 +29,7 @@ (MOVBUreg x:((Equal|NotEqual|LessThan|LessThanU|LessThanF|LessEqual|LessEqualU|LessEqualF|GreaterThan|GreaterThanU|GreaterThanF|GreaterEqual|GreaterEqualU|GreaterEqualF) _)) => x // omit unsigned extension -(MOVWUreg x) && zeroUpper32Bits(x, 3) => x +(MOVWUreg x) && ZeroUpper32Bits(x, 3) => x // don't extend after proper load (MOVBreg x:(MOVBload _ _)) => (MOVDreg x) diff --git a/src/cmd/compile/internal/ssa/_gen/ARMOps.go b/src/cmd/compile/internal/ssa/_gen/ARMOps.go index 01cd48835e2bc4..dc16ea6da4a820 100644 --- a/src/cmd/compile/internal/ssa/_gen/ARMOps.go +++ b/src/cmd/compile/internal/ssa/_gen/ARMOps.go @@ -74,10 +74,10 @@ func init() { num[name] = i } buildReg := func(s string) regMask { - m := regMask(0) + m := regMask{} for _, r := range strings.Split(s, " ") { if n, ok := num[r]; ok { - m |= regMask(1) << uint(n) + m = m.addReg(uint(n)) continue } panic("register " + r + " not found") @@ -88,12 +88,12 @@ func init() { // Common individual register masks var ( gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14") - gpg = gp | buildReg("g") - gpsp = gp | buildReg("SP") - gpspg = gpg | buildReg("SP") - gpspsbg = gpspg | buildReg("SB") + gpg = gp.union(buildReg("g")) + gpsp = gp.union(buildReg("SP")) + gpspg = gpg.union(buildReg("SP")) + gpspsbg = gpspg.union(buildReg("SB")) fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15") - callerSave = gp | fp | buildReg("g") // runtime.setg (and anything calling it) may clobber g + callerSave = gp.union(fp).union(buildReg("g")) // runtime.setg (and anything calling it) may clobber g lr = buildReg("R14") r0 = buildReg("R0") r1 = buildReg("R1") @@ -102,48 +102,49 @@ func init() { ) // Common regInfo var ( - gp01 = regInfo{inputs: nil, outputs: []regMask{gp}} - gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}} - gp11carry = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp, 0}} - gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}} - gp1flags = regInfo{inputs: []regMask{gpg}} - gp1flags1 = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}} - gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}} - gp21carry = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp, 0}} - gp2flags = regInfo{inputs: []regMask{gpg, gpg}} - gp2flags1 = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}} - gp22 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp, gp}} - gp31 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}} - gp31carry = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp, 0}} - gp3flags = regInfo{inputs: []regMask{gp, gp, gp}} - gp3flags1 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}} - gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}} - gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}} - gp2load = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}} - gp2store = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}} - fp01 = regInfo{inputs: nil, outputs: []regMask{fp}} - fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}} - fp1flags = regInfo{inputs: []regMask{fp}} - fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}, clobbers: buildReg("F15")} // int-float conversion uses F15 as tmp - gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}, clobbers: buildReg("F15")} - fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}} - fp31 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: []regMask{fp}} - fp2flags = regInfo{inputs: []regMask{fp, fp}} - fpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{fp}} - fpstore = regInfo{inputs: []regMask{gpspsbg, fp}} - readflags = regInfo{inputs: nil, outputs: []regMask{gp}} + gp01 = regInfo{inputs: nil, outputs: []regMask{gp}} + gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}} + gp11carry = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp, regMask{}}} + gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}} + gp1flags = regInfo{inputs: []regMask{gpg}} + gp1flags1 = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}} + gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}} + gp21carry = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp, regMask{}}} + gp2flags = regInfo{inputs: []regMask{gpg, gpg}} + gp2flags1 = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}} + gp2flags1carry = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp, regMask{}}} + gp22 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp, gp}} + gp31 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}} + gp31carry = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp, regMask{}}} + gp3flags = regInfo{inputs: []regMask{gp, gp, gp}} + gp3flags1 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}} + gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}} + gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}} + gp2load = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}} + gp2store = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}} + fp01 = regInfo{inputs: nil, outputs: []regMask{fp}} + fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}} + fp1flags = regInfo{inputs: []regMask{fp}} + fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}, clobbers: buildReg("F15")} // int-float conversion uses F15 as tmp + gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}, clobbers: buildReg("F15")} + fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}} + fp31 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: []regMask{fp}} + fp2flags = regInfo{inputs: []regMask{fp, fp}} + fpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{fp}} + fpstore = regInfo{inputs: []regMask{gpspsbg, fp}} + readflags = regInfo{inputs: nil, outputs: []regMask{gp}} ) ops := []opData{ // binary ops - {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1 - {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int32"}, // arg0 + auxInt - {name: "SUB", argLength: 2, reg: gp21, asm: "SUB"}, // arg0 - arg1 - {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int32"}, // arg0 - auxInt - {name: "RSB", argLength: 2, reg: gp21, asm: "RSB"}, // arg1 - arg0 - {name: "RSBconst", argLength: 1, reg: gp11, asm: "RSB", aux: "Int32"}, // auxInt - arg0 - {name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true}, // arg0 * arg1 - {name: "HMUL", argLength: 2, reg: gp21, asm: "MULL", commutative: true}, // (arg0 * arg1) >> 32, signed - {name: "HMULU", argLength: 2, reg: gp21, asm: "MULLU", commutative: true}, // (arg0 * arg1) >> 32, unsigned + {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int32", earlyOk: true}, // arg0 + auxInt + {name: "SUB", argLength: 2, reg: gp21, asm: "SUB", earlyOk: true}, // arg0 - arg1 + {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int32", earlyOk: true}, // arg0 - auxInt + {name: "RSB", argLength: 2, reg: gp21, asm: "RSB", earlyOk: true}, // arg1 - arg0 + {name: "RSBconst", argLength: 1, reg: gp11, asm: "RSB", aux: "Int32", earlyOk: true}, // auxInt - arg0 + {name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "HMUL", argLength: 2, reg: gp21, asm: "MULL", commutative: true, earlyOk: true}, // (arg0 * arg1) >> 32, signed + {name: "HMULU", argLength: 2, reg: gp21, asm: "MULLU", commutative: true, earlyOk: true}, // (arg0 * arg1) >> 32, unsigned // udiv runtime call for soft division // output0 = arg0/arg1, output1 = arg0%arg1 @@ -161,114 +162,115 @@ func init() { call: false, // TODO(mdempsky): Should this be true? }, - {name: "ADDS", argLength: 2, reg: gp21carry, asm: "ADD", commutative: true}, // arg0 + arg1, set carry flag - {name: "ADDSconst", argLength: 1, reg: gp11carry, asm: "ADD", aux: "Int32"}, // arg0 + auxInt, set carry flag - {name: "ADC", argLength: 3, reg: gp2flags1, asm: "ADC", commutative: true}, // arg0 + arg1 + carry, arg2=flags - {name: "ADCconst", argLength: 2, reg: gp1flags1, asm: "ADC", aux: "Int32"}, // arg0 + auxInt + carry, arg1=flags - {name: "SUBS", argLength: 2, reg: gp21carry, asm: "SUB"}, // arg0 - arg1, set carry flag - {name: "SUBSconst", argLength: 1, reg: gp11carry, asm: "SUB", aux: "Int32"}, // arg0 - auxInt, set carry flag - {name: "RSBSconst", argLength: 1, reg: gp11carry, asm: "RSB", aux: "Int32"}, // auxInt - arg0, set carry flag - {name: "SBC", argLength: 3, reg: gp2flags1, asm: "SBC"}, // arg0 - arg1 - carry, arg2=flags - {name: "SBCconst", argLength: 2, reg: gp1flags1, asm: "SBC", aux: "Int32"}, // arg0 - auxInt - carry, arg1=flags - {name: "RSCconst", argLength: 2, reg: gp1flags1, asm: "RSC", aux: "Int32"}, // auxInt - arg0 - carry, arg1=flags - - {name: "MULLU", argLength: 2, reg: gp22, asm: "MULLU", commutative: true}, // arg0 * arg1, high 32 bits in out0, low 32 bits in out1 - {name: "MULA", argLength: 3, reg: gp31, asm: "MULA"}, // arg0 * arg1 + arg2 - {name: "MULS", argLength: 3, reg: gp31, asm: "MULS"}, // arg2 - arg0 * arg1 - - {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1 - {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true}, // arg0 + arg1 - {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF"}, // arg0 - arg1 - {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"}, // arg0 - arg1 - {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1 - {name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1 - {name: "NMULF", argLength: 2, reg: fp21, asm: "NMULF", commutative: true}, // -(arg0 * arg1) - {name: "NMULD", argLength: 2, reg: fp21, asm: "NMULD", commutative: true}, // -(arg0 * arg1) - {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1 - {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1 - - {name: "MULAF", argLength: 3, reg: fp31, asm: "MULAF", resultInArg0: true}, // arg0 + (arg1 * arg2) - {name: "MULAD", argLength: 3, reg: fp31, asm: "MULAD", resultInArg0: true}, // arg0 + (arg1 * arg2) - {name: "MULSF", argLength: 3, reg: fp31, asm: "MULSF", resultInArg0: true}, // arg0 - (arg1 * arg2) - {name: "MULSD", argLength: 3, reg: fp31, asm: "MULSD", resultInArg0: true}, // arg0 - (arg1 * arg2) + {name: "ADDS", argLength: 2, reg: gp21carry, asm: "ADD", commutative: true, earlyOk: true}, // arg0 + arg1, set carry flag + {name: "ADDSconst", argLength: 1, reg: gp11carry, asm: "ADD", aux: "Int32", earlyOk: true}, // arg0 + auxInt, set carry flag + {name: "ADC", argLength: 3, reg: gp2flags1, asm: "ADC", commutative: true, earlyOk: true}, // arg0 + arg1 + carry, arg2=flags + {name: "ADCconst", argLength: 2, reg: gp1flags1, asm: "ADC", aux: "Int32", earlyOk: true}, // arg0 + auxInt + carry, arg1=flags + {name: "ADCS", argLength: 3, reg: gp2flags1carry, asm: "ADC", commutative: true}, // arg0 + arg1 + carrry, sets carry + {name: "SUBS", argLength: 2, reg: gp21carry, asm: "SUB"}, // arg0 - arg1, set carry flag + {name: "SUBSconst", argLength: 1, reg: gp11carry, asm: "SUB", aux: "Int32"}, // arg0 - auxInt, set carry flag + {name: "RSBSconst", argLength: 1, reg: gp11carry, asm: "RSB", aux: "Int32"}, // auxInt - arg0, set carry flag + {name: "SBC", argLength: 3, reg: gp2flags1, asm: "SBC"}, // arg0 - arg1 - carry, arg2=flags + {name: "SBCconst", argLength: 2, reg: gp1flags1, asm: "SBC", aux: "Int32"}, // arg0 - auxInt - carry, arg1=flags + {name: "RSCconst", argLength: 2, reg: gp1flags1, asm: "RSC", aux: "Int32"}, // auxInt - arg0 - carry, arg1=flags + + {name: "MULLU", argLength: 2, reg: gp22, asm: "MULLU", commutative: true, earlyOk: true}, // arg0 * arg1, high 32 bits in out0, low 32 bits in out1 + {name: "MULA", argLength: 3, reg: gp31, asm: "MULA", earlyOk: true}, // arg0 * arg1 + arg2 + {name: "MULS", argLength: 3, reg: gp31, asm: "MULS", earlyOk: true}, // arg2 - arg0 * arg1 + + {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF", earlyOk: true}, // arg0 - arg1 + {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD", earlyOk: true}, // arg0 - arg1 + {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "NMULF", argLength: 2, reg: fp21, asm: "NMULF", commutative: true, earlyOk: true}, // -(arg0 * arg1) + {name: "NMULD", argLength: 2, reg: fp21, asm: "NMULD", commutative: true, earlyOk: true}, // -(arg0 * arg1) + {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF", earlyOk: true}, // arg0 / arg1 + {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD", earlyOk: true}, // arg0 / arg1 + + {name: "MULAF", argLength: 3, reg: fp31, asm: "MULAF", resultInArg0: true, earlyOk: true}, // arg0 + (arg1 * arg2) + {name: "MULAD", argLength: 3, reg: fp31, asm: "MULAD", resultInArg0: true, earlyOk: true}, // arg0 + (arg1 * arg2) + {name: "MULSF", argLength: 3, reg: fp31, asm: "MULSF", resultInArg0: true, earlyOk: true}, // arg0 - (arg1 * arg2) + {name: "MULSD", argLength: 3, reg: fp31, asm: "MULSD", resultInArg0: true, earlyOk: true}, // arg0 - (arg1 * arg2) // FMULAD only exists on platforms with the VFPv4 instruction set. // Any use must be preceded by a successful check of runtime.arm_support_vfpv4. {name: "FMULAD", argLength: 3, reg: fp31, asm: "FMULAD", resultInArg0: true}, // arg0 + (arg1 * arg2) - {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1 - {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int32"}, // arg0 & auxInt - {name: "OR", argLength: 2, reg: gp21, asm: "ORR", commutative: true}, // arg0 | arg1 - {name: "ORconst", argLength: 1, reg: gp11, asm: "ORR", aux: "Int32"}, // arg0 | auxInt - {name: "XOR", argLength: 2, reg: gp21, asm: "EOR", commutative: true}, // arg0 ^ arg1 - {name: "XORconst", argLength: 1, reg: gp11, asm: "EOR", aux: "Int32"}, // arg0 ^ auxInt - {name: "BIC", argLength: 2, reg: gp21, asm: "BIC"}, // arg0 &^ arg1 - {name: "BICconst", argLength: 1, reg: gp11, asm: "BIC", aux: "Int32"}, // arg0 &^ auxInt + {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int32", earlyOk: true}, // arg0 & auxInt + {name: "OR", argLength: 2, reg: gp21, asm: "ORR", commutative: true, earlyOk: true}, // arg0 | arg1 + {name: "ORconst", argLength: 1, reg: gp11, asm: "ORR", aux: "Int32", earlyOk: true}, // arg0 | auxInt + {name: "XOR", argLength: 2, reg: gp21, asm: "EOR", commutative: true, earlyOk: true}, // arg0 ^ arg1 + {name: "XORconst", argLength: 1, reg: gp11, asm: "EOR", aux: "Int32", earlyOk: true}, // arg0 ^ auxInt + {name: "BIC", argLength: 2, reg: gp21, asm: "BIC", earlyOk: true}, // arg0 &^ arg1 + {name: "BICconst", argLength: 1, reg: gp11, asm: "BIC", aux: "Int32", earlyOk: true}, // arg0 &^ auxInt // bit extraction, AuxInt = Width<<8 | LSB - {name: "BFX", argLength: 1, reg: gp11, asm: "BFX", aux: "Int32"}, // extract W bits from bit L in arg0, then signed extend - {name: "BFXU", argLength: 1, reg: gp11, asm: "BFXU", aux: "Int32"}, // extract W bits from bit L in arg0, then unsigned extend + {name: "BFX", argLength: 1, reg: gp11, asm: "BFX", aux: "Int32", earlyOk: true}, // extract W bits from bit L in arg0, then signed extend + {name: "BFXU", argLength: 1, reg: gp11, asm: "BFXU", aux: "Int32", earlyOk: true}, // extract W bits from bit L in arg0, then unsigned extend // unary ops - {name: "MVN", argLength: 1, reg: gp11, asm: "MVN"}, // ^arg0 + {name: "MVN", argLength: 1, reg: gp11, asm: "MVN", earlyOk: true}, // ^arg0 - {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32 - {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 - {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64 - {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 - {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64 + {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF", earlyOk: true}, // -arg0, float32 + {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD", earlyOk: true}, // -arg0, float64 + {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD", earlyOk: true}, // sqrt(arg0), float64 + {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF", earlyOk: true}, // sqrt(arg0), float32 + {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD", earlyOk: true}, // abs(arg0), float64 - {name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ"}, // count leading zero - {name: "REV", argLength: 1, reg: gp11, asm: "REV"}, // reverse byte order - {name: "REV16", argLength: 1, reg: gp11, asm: "REV16"}, // reverse byte order in 16-bit halfwords - {name: "RBIT", argLength: 1, reg: gp11, asm: "RBIT"}, // reverse bit order + {name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ", earlyOk: true}, // count leading zero + {name: "REV", argLength: 1, reg: gp11, asm: "REV", earlyOk: true}, // reverse byte order + {name: "REV16", argLength: 1, reg: gp11, asm: "REV16", earlyOk: true}, // reverse byte order in 16-bit halfwords + {name: "RBIT", argLength: 1, reg: gp11, asm: "RBIT", earlyOk: true}, // reverse bit order // shifts - {name: "SLL", argLength: 2, reg: gp21, asm: "SLL"}, // arg0 << arg1, shift amount is mod 256 - {name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt, 0 <= auxInt < 32 - {name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> arg1, unsigned, shift amount is mod 256 - {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, unsigned, 0 <= auxInt < 32 - {name: "SRA", argLength: 2, reg: gp21, asm: "SRA"}, // arg0 >> arg1, signed, shift amount is mod 256 - {name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int32"}, // arg0 >> auxInt, signed, 0 <= auxInt < 32 - {name: "SRR", argLength: 2, reg: gp21}, // arg0 right rotate by arg1 bits - {name: "SRRconst", argLength: 1, reg: gp11, aux: "Int32"}, // arg0 right rotate by auxInt bits, 0 <= auxInt < 32 + {name: "SLL", argLength: 2, reg: gp21, asm: "SLL", earlyOk: true}, // arg0 << arg1, shift amount is mod 256 + {name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32", earlyOk: true}, // arg0 << auxInt, 0 <= auxInt < 32 + {name: "SRL", argLength: 2, reg: gp21, asm: "SRL", earlyOk: true}, // arg0 >> arg1, unsigned, shift amount is mod 256 + {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32", earlyOk: true}, // arg0 >> auxInt, unsigned, 0 <= auxInt < 32 + {name: "SRA", argLength: 2, reg: gp21, asm: "SRA", earlyOk: true}, // arg0 >> arg1, signed, shift amount is mod 256 + {name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int32", earlyOk: true}, // arg0 >> auxInt, signed, 0 <= auxInt < 32 + {name: "SRR", argLength: 2, reg: gp21, earlyOk: true}, // arg0 right rotate by arg1 bits + {name: "SRRconst", argLength: 1, reg: gp11, aux: "Int32", earlyOk: true}, // arg0 right rotate by auxInt bits, 0 <= auxInt < 32 // auxInt for all of these satisfy 0 <= auxInt < 32 - {name: "ADDshiftLL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1<>auxInt, unsigned shift - {name: "ADDshiftRA", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, signed shift - {name: "SUBshiftLL", argLength: 2, reg: gp21, asm: "SUB", aux: "Int32"}, // arg0 - arg1<>auxInt, unsigned shift - {name: "SUBshiftRA", argLength: 2, reg: gp21, asm: "SUB", aux: "Int32"}, // arg0 - arg1>>auxInt, signed shift - {name: "RSBshiftLL", argLength: 2, reg: gp21, asm: "RSB", aux: "Int32"}, // arg1<>auxInt - arg0, unsigned shift - {name: "RSBshiftRA", argLength: 2, reg: gp21, asm: "RSB", aux: "Int32"}, // arg1>>auxInt - arg0, signed shift - {name: "ANDshiftLL", argLength: 2, reg: gp21, asm: "AND", aux: "Int32"}, // arg0 & (arg1<>auxInt), unsigned shift - {name: "ANDshiftRA", argLength: 2, reg: gp21, asm: "AND", aux: "Int32"}, // arg0 & (arg1>>auxInt), signed shift - {name: "ORshiftLL", argLength: 2, reg: gp21, asm: "ORR", aux: "Int32"}, // arg0 | arg1<>auxInt, unsigned shift - {name: "ORshiftRA", argLength: 2, reg: gp21, asm: "ORR", aux: "Int32"}, // arg0 | arg1>>auxInt, signed shift - {name: "XORshiftLL", argLength: 2, reg: gp21, asm: "EOR", aux: "Int32"}, // arg0 ^ arg1<>auxInt, unsigned shift - {name: "XORshiftRA", argLength: 2, reg: gp21, asm: "EOR", aux: "Int32"}, // arg0 ^ arg1>>auxInt, signed shift - {name: "XORshiftRR", argLength: 2, reg: gp21, asm: "EOR", aux: "Int32"}, // arg0 ^ (arg1 right rotate by auxInt) - {name: "BICshiftLL", argLength: 2, reg: gp21, asm: "BIC", aux: "Int32"}, // arg0 &^ (arg1<>auxInt), unsigned shift - {name: "BICshiftRA", argLength: 2, reg: gp21, asm: "BIC", aux: "Int32"}, // arg0 &^ (arg1>>auxInt), signed shift - {name: "MVNshiftLL", argLength: 1, reg: gp11, asm: "MVN", aux: "Int32"}, // ^(arg0<>auxInt), unsigned shift - {name: "MVNshiftRA", argLength: 1, reg: gp11, asm: "MVN", aux: "Int32"}, // ^(arg0>>auxInt), signed shift - - {name: "ADCshiftLL", argLength: 3, reg: gp2flags1, asm: "ADC", aux: "Int32"}, // arg0 + arg1<>auxInt + carry, unsigned shift, arg2=flags - {name: "ADCshiftRA", argLength: 3, reg: gp2flags1, asm: "ADC", aux: "Int32"}, // arg0 + arg1>>auxInt + carry, signed shift, arg2=flags - {name: "SBCshiftLL", argLength: 3, reg: gp2flags1, asm: "SBC", aux: "Int32"}, // arg0 - arg1<>auxInt - carry, unsigned shift, arg2=flags - {name: "SBCshiftRA", argLength: 3, reg: gp2flags1, asm: "SBC", aux: "Int32"}, // arg0 - arg1>>auxInt - carry, signed shift, arg2=flags - {name: "RSCshiftLL", argLength: 3, reg: gp2flags1, asm: "RSC", aux: "Int32"}, // arg1<>auxInt - arg0 - carry, unsigned shift, arg2=flags - {name: "RSCshiftRA", argLength: 3, reg: gp2flags1, asm: "RSC", aux: "Int32"}, // arg1>>auxInt - arg0 - carry, signed shift, arg2=flags + {name: "ADDshiftLL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32", earlyOk: true}, // arg0 + arg1<>auxInt, unsigned shift + {name: "ADDshiftRA", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32", earlyOk: true}, // arg0 + arg1>>auxInt, signed shift + {name: "SUBshiftLL", argLength: 2, reg: gp21, asm: "SUB", aux: "Int32", earlyOk: true}, // arg0 - arg1<>auxInt, unsigned shift + {name: "SUBshiftRA", argLength: 2, reg: gp21, asm: "SUB", aux: "Int32", earlyOk: true}, // arg0 - arg1>>auxInt, signed shift + {name: "RSBshiftLL", argLength: 2, reg: gp21, asm: "RSB", aux: "Int32", earlyOk: true}, // arg1<>auxInt - arg0, unsigned shift + {name: "RSBshiftRA", argLength: 2, reg: gp21, asm: "RSB", aux: "Int32", earlyOk: true}, // arg1>>auxInt - arg0, signed shift + {name: "ANDshiftLL", argLength: 2, reg: gp21, asm: "AND", aux: "Int32", earlyOk: true}, // arg0 & (arg1<>auxInt), unsigned shift + {name: "ANDshiftRA", argLength: 2, reg: gp21, asm: "AND", aux: "Int32", earlyOk: true}, // arg0 & (arg1>>auxInt), signed shift + {name: "ORshiftLL", argLength: 2, reg: gp21, asm: "ORR", aux: "Int32", earlyOk: true}, // arg0 | arg1<>auxInt, unsigned shift + {name: "ORshiftRA", argLength: 2, reg: gp21, asm: "ORR", aux: "Int32", earlyOk: true}, // arg0 | arg1>>auxInt, signed shift + {name: "XORshiftLL", argLength: 2, reg: gp21, asm: "EOR", aux: "Int32", earlyOk: true}, // arg0 ^ arg1<>auxInt, unsigned shift + {name: "XORshiftRA", argLength: 2, reg: gp21, asm: "EOR", aux: "Int32", earlyOk: true}, // arg0 ^ arg1>>auxInt, signed shift + {name: "XORshiftRR", argLength: 2, reg: gp21, asm: "EOR", aux: "Int32", earlyOk: true}, // arg0 ^ (arg1 right rotate by auxInt) + {name: "BICshiftLL", argLength: 2, reg: gp21, asm: "BIC", aux: "Int32", earlyOk: true}, // arg0 &^ (arg1<>auxInt), unsigned shift + {name: "BICshiftRA", argLength: 2, reg: gp21, asm: "BIC", aux: "Int32", earlyOk: true}, // arg0 &^ (arg1>>auxInt), signed shift + {name: "MVNshiftLL", argLength: 1, reg: gp11, asm: "MVN", aux: "Int32", earlyOk: true}, // ^(arg0<>auxInt), unsigned shift + {name: "MVNshiftRA", argLength: 1, reg: gp11, asm: "MVN", aux: "Int32", earlyOk: true}, // ^(arg0>>auxInt), signed shift + + {name: "ADCshiftLL", argLength: 3, reg: gp2flags1, asm: "ADC", aux: "Int32", earlyOk: true}, // arg0 + arg1<>auxInt + carry, unsigned shift, arg2=flags + {name: "ADCshiftRA", argLength: 3, reg: gp2flags1, asm: "ADC", aux: "Int32", earlyOk: true}, // arg0 + arg1>>auxInt + carry, signed shift, arg2=flags + {name: "SBCshiftLL", argLength: 3, reg: gp2flags1, asm: "SBC", aux: "Int32", earlyOk: true}, // arg0 - arg1<>auxInt - carry, unsigned shift, arg2=flags + {name: "SBCshiftRA", argLength: 3, reg: gp2flags1, asm: "SBC", aux: "Int32", earlyOk: true}, // arg0 - arg1>>auxInt - carry, signed shift, arg2=flags + {name: "RSCshiftLL", argLength: 3, reg: gp2flags1, asm: "RSC", aux: "Int32", earlyOk: true}, // arg1<>auxInt - arg0 - carry, unsigned shift, arg2=flags + {name: "RSCshiftRA", argLength: 3, reg: gp2flags1, asm: "RSC", aux: "Int32", earlyOk: true}, // arg1>>auxInt - arg0 - carry, signed shift, arg2=flags {name: "ADDSshiftLL", argLength: 2, reg: gp21carry, asm: "ADD", aux: "Int32"}, // arg0 + arg1<>auxInt, unsigned shift, set carry flag @@ -280,40 +282,40 @@ func init() { {name: "RSBSshiftRL", argLength: 2, reg: gp21carry, asm: "RSB", aux: "Int32"}, // arg1>>auxInt - arg0, unsigned shift, set carry flag {name: "RSBSshiftRA", argLength: 2, reg: gp21carry, asm: "RSB", aux: "Int32"}, // arg1>>auxInt - arg0, signed shift, set carry flag - {name: "ADDshiftLLreg", argLength: 3, reg: gp31, asm: "ADD"}, // arg0 + arg1<>arg2, unsigned shift - {name: "ADDshiftRAreg", argLength: 3, reg: gp31, asm: "ADD"}, // arg0 + arg1>>arg2, signed shift - {name: "SUBshiftLLreg", argLength: 3, reg: gp31, asm: "SUB"}, // arg0 - arg1<>arg2, unsigned shift - {name: "SUBshiftRAreg", argLength: 3, reg: gp31, asm: "SUB"}, // arg0 - arg1>>arg2, signed shift - {name: "RSBshiftLLreg", argLength: 3, reg: gp31, asm: "RSB"}, // arg1<>arg2 - arg0, unsigned shift - {name: "RSBshiftRAreg", argLength: 3, reg: gp31, asm: "RSB"}, // arg1>>arg2 - arg0, signed shift - {name: "ANDshiftLLreg", argLength: 3, reg: gp31, asm: "AND"}, // arg0 & (arg1<>arg2), unsigned shift - {name: "ANDshiftRAreg", argLength: 3, reg: gp31, asm: "AND"}, // arg0 & (arg1>>arg2), signed shift - {name: "ORshiftLLreg", argLength: 3, reg: gp31, asm: "ORR"}, // arg0 | arg1<>arg2, unsigned shift - {name: "ORshiftRAreg", argLength: 3, reg: gp31, asm: "ORR"}, // arg0 | arg1>>arg2, signed shift - {name: "XORshiftLLreg", argLength: 3, reg: gp31, asm: "EOR"}, // arg0 ^ arg1<>arg2, unsigned shift - {name: "XORshiftRAreg", argLength: 3, reg: gp31, asm: "EOR"}, // arg0 ^ arg1>>arg2, signed shift - {name: "BICshiftLLreg", argLength: 3, reg: gp31, asm: "BIC"}, // arg0 &^ (arg1<>arg2), unsigned shift - {name: "BICshiftRAreg", argLength: 3, reg: gp31, asm: "BIC"}, // arg0 &^ (arg1>>arg2), signed shift - {name: "MVNshiftLLreg", argLength: 2, reg: gp21, asm: "MVN"}, // ^(arg0<>arg1), unsigned shift - {name: "MVNshiftRAreg", argLength: 2, reg: gp21, asm: "MVN"}, // ^(arg0>>arg1), signed shift - - {name: "ADCshiftLLreg", argLength: 4, reg: gp3flags1, asm: "ADC"}, // arg0 + arg1<>arg2 + carry, unsigned shift, arg3=flags - {name: "ADCshiftRAreg", argLength: 4, reg: gp3flags1, asm: "ADC"}, // arg0 + arg1>>arg2 + carry, signed shift, arg3=flags - {name: "SBCshiftLLreg", argLength: 4, reg: gp3flags1, asm: "SBC"}, // arg0 - arg1<>arg2 - carry, unsigned shift, arg3=flags - {name: "SBCshiftRAreg", argLength: 4, reg: gp3flags1, asm: "SBC"}, // arg0 - arg1>>arg2 - carry, signed shift, arg3=flags - {name: "RSCshiftLLreg", argLength: 4, reg: gp3flags1, asm: "RSC"}, // arg1<>arg2 - arg0 - carry, unsigned shift, arg3=flags - {name: "RSCshiftRAreg", argLength: 4, reg: gp3flags1, asm: "RSC"}, // arg1>>arg2 - arg0 - carry, signed shift, arg3=flags + {name: "ADDshiftLLreg", argLength: 3, reg: gp31, asm: "ADD", earlyOk: true}, // arg0 + arg1<>arg2, unsigned shift + {name: "ADDshiftRAreg", argLength: 3, reg: gp31, asm: "ADD", earlyOk: true}, // arg0 + arg1>>arg2, signed shift + {name: "SUBshiftLLreg", argLength: 3, reg: gp31, asm: "SUB", earlyOk: true}, // arg0 - arg1<>arg2, unsigned shift + {name: "SUBshiftRAreg", argLength: 3, reg: gp31, asm: "SUB", earlyOk: true}, // arg0 - arg1>>arg2, signed shift + {name: "RSBshiftLLreg", argLength: 3, reg: gp31, asm: "RSB", earlyOk: true}, // arg1<>arg2 - arg0, unsigned shift + {name: "RSBshiftRAreg", argLength: 3, reg: gp31, asm: "RSB", earlyOk: true}, // arg1>>arg2 - arg0, signed shift + {name: "ANDshiftLLreg", argLength: 3, reg: gp31, asm: "AND", earlyOk: true}, // arg0 & (arg1<>arg2), unsigned shift + {name: "ANDshiftRAreg", argLength: 3, reg: gp31, asm: "AND", earlyOk: true}, // arg0 & (arg1>>arg2), signed shift + {name: "ORshiftLLreg", argLength: 3, reg: gp31, asm: "ORR", earlyOk: true}, // arg0 | arg1<>arg2, unsigned shift + {name: "ORshiftRAreg", argLength: 3, reg: gp31, asm: "ORR", earlyOk: true}, // arg0 | arg1>>arg2, signed shift + {name: "XORshiftLLreg", argLength: 3, reg: gp31, asm: "EOR", earlyOk: true}, // arg0 ^ arg1<>arg2, unsigned shift + {name: "XORshiftRAreg", argLength: 3, reg: gp31, asm: "EOR", earlyOk: true}, // arg0 ^ arg1>>arg2, signed shift + {name: "BICshiftLLreg", argLength: 3, reg: gp31, asm: "BIC", earlyOk: true}, // arg0 &^ (arg1<>arg2), unsigned shift + {name: "BICshiftRAreg", argLength: 3, reg: gp31, asm: "BIC", earlyOk: true}, // arg0 &^ (arg1>>arg2), signed shift + {name: "MVNshiftLLreg", argLength: 2, reg: gp21, asm: "MVN", earlyOk: true}, // ^(arg0<>arg1), unsigned shift + {name: "MVNshiftRAreg", argLength: 2, reg: gp21, asm: "MVN", earlyOk: true}, // ^(arg0>>arg1), signed shift + + {name: "ADCshiftLLreg", argLength: 4, reg: gp3flags1, asm: "ADC", earlyOk: true}, // arg0 + arg1<>arg2 + carry, unsigned shift, arg3=flags + {name: "ADCshiftRAreg", argLength: 4, reg: gp3flags1, asm: "ADC", earlyOk: true}, // arg0 + arg1>>arg2 + carry, signed shift, arg3=flags + {name: "SBCshiftLLreg", argLength: 4, reg: gp3flags1, asm: "SBC", earlyOk: true}, // arg0 - arg1<>arg2 - carry, unsigned shift, arg3=flags + {name: "SBCshiftRAreg", argLength: 4, reg: gp3flags1, asm: "SBC", earlyOk: true}, // arg0 - arg1>>arg2 - carry, signed shift, arg3=flags + {name: "RSCshiftLLreg", argLength: 4, reg: gp3flags1, asm: "RSC", earlyOk: true}, // arg1<>arg2 - arg0 - carry, unsigned shift, arg3=flags + {name: "RSCshiftRAreg", argLength: 4, reg: gp3flags1, asm: "RSC", earlyOk: true}, // arg1>>arg2 - arg0 - carry, signed shift, arg3=flags {name: "ADDSshiftLLreg", argLength: 3, reg: gp31carry, asm: "ADD"}, // arg0 + arg1<>arg2, unsigned shift, set carry flag @@ -367,85 +369,86 @@ func init() { {name: "CMPD0", argLength: 1, reg: fp1flags, asm: "CMPD", typ: "Flags"}, // arg0 compare to 0, float64 // moves - {name: "MOVWconst", argLength: 0, reg: gp01, aux: "Int32", asm: "MOVW", typ: "UInt32", rematerializeable: true}, // 32 low bits of auxint - {name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVF", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float - {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true}, // auxint as 64-bit float - - {name: "MOVWaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP") | buildReg("SB")}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVW", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB - - {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - - {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - - {name: "MOVWloadidx", argLength: 3, reg: gp2load, asm: "MOVW", typ: "UInt32"}, // load from arg0 + arg1. arg2=mem - {name: "MOVWloadshiftLL", argLength: 3, reg: gp2load, asm: "MOVW", aux: "Int32", typ: "UInt32"}, // load from arg0 + arg1<>auxInt, unsigned shift. arg2=mem - {name: "MOVWloadshiftRA", argLength: 3, reg: gp2load, asm: "MOVW", aux: "Int32", typ: "UInt32"}, // load from arg0 + arg1>>auxInt, signed shift. arg2=mem - {name: "MOVBUloadidx", argLength: 3, reg: gp2load, asm: "MOVBU", typ: "UInt8"}, // load from arg0 + arg1. arg2=mem - {name: "MOVBloadidx", argLength: 3, reg: gp2load, asm: "MOVB", typ: "Int8"}, // load from arg0 + arg1. arg2=mem - {name: "MOVHUloadidx", argLength: 3, reg: gp2load, asm: "MOVHU", typ: "UInt16"}, // load from arg0 + arg1. arg2=mem - {name: "MOVHloadidx", argLength: 3, reg: gp2load, asm: "MOVH", typ: "Int16"}, // load from arg0 + arg1. arg2=mem - - {name: "MOVWstoreidx", argLength: 4, reg: gp2store, asm: "MOVW", typ: "Mem"}, // store arg2 to arg0 + arg1. arg3=mem - {name: "MOVWstoreshiftLL", argLength: 4, reg: gp2store, asm: "MOVW", aux: "Int32", typ: "Mem"}, // store arg2 to arg0 + arg1<>auxInt, unsigned shift. arg3=mem - {name: "MOVWstoreshiftRA", argLength: 4, reg: gp2store, asm: "MOVW", aux: "Int32", typ: "Mem"}, // store arg2 to arg0 + arg1>>auxInt, signed shift. arg3=mem - {name: "MOVBstoreidx", argLength: 4, reg: gp2store, asm: "MOVB", typ: "Mem"}, // store arg2 to arg0 + arg1. arg3=mem - {name: "MOVHstoreidx", argLength: 4, reg: gp2store, asm: "MOVH", typ: "Mem"}, // store arg2 to arg0 + arg1. arg3=mem - - {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVBS"}, // move from arg0, sign-extended from byte - {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte - {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVHS"}, // move from arg0, sign-extended from half - {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half - {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"}, // move from arg0 - - {name: "MOVWnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true}, // nop, return arg0 in same register - - {name: "MOVWF", argLength: 1, reg: gpfp, asm: "MOVWF"}, // int32 -> float32 - {name: "MOVWD", argLength: 1, reg: gpfp, asm: "MOVWD"}, // int32 -> float64 - {name: "MOVWUF", argLength: 1, reg: gpfp, asm: "MOVWF"}, // uint32 -> float32, set U bit in the instruction - {name: "MOVWUD", argLength: 1, reg: gpfp, asm: "MOVWD"}, // uint32 -> float64, set U bit in the instruction - {name: "MOVFW", argLength: 1, reg: fpgp, asm: "MOVFW"}, // float32 -> int32 - {name: "MOVDW", argLength: 1, reg: fpgp, asm: "MOVDW"}, // float64 -> int32 - {name: "MOVFWU", argLength: 1, reg: fpgp, asm: "MOVFW"}, // float32 -> uint32, set U bit in the instruction - {name: "MOVDWU", argLength: 1, reg: fpgp, asm: "MOVDW"}, // float64 -> uint32, set U bit in the instruction - {name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD"}, // float32 -> float64 - {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF"}, // float64 -> float32 + {name: "MOVWconst", argLength: 0, reg: gp01, aux: "Int32", asm: "MOVW", typ: "UInt32", rematerializeable: true, earlyOk: true}, // 32 low bits of auxint + {name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVF", typ: "Float32", rematerializeable: true, earlyOk: true}, // auxint as 64-bit float, convert to 32-bit float + {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true, earlyOk: true}, // auxint as 64-bit float + + {name: "MOVWaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP").union(buildReg("SB"))}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVW", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB + + {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + + {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + + {name: "MOVWloadidx", argLength: 3, reg: gp2load, asm: "MOVW", typ: "UInt32", addrSinkArg0: true}, // load from arg0 + arg1. arg2=mem + {name: "MOVWloadshiftLL", argLength: 3, reg: gp2load, asm: "MOVW", aux: "Int32", typ: "UInt32", addrSinkArg0: true}, // load from arg0 + arg1<>auxInt, unsigned shift. arg2=mem + {name: "MOVWloadshiftRA", argLength: 3, reg: gp2load, asm: "MOVW", aux: "Int32", typ: "UInt32", addrSinkArg0: true}, // load from arg0 + arg1>>auxInt, signed shift. arg2=mem + {name: "MOVBUloadidx", argLength: 3, reg: gp2load, asm: "MOVBU", typ: "UInt8", addrSinkArg0: true}, // load from arg0 + arg1. arg2=mem + {name: "MOVBloadidx", argLength: 3, reg: gp2load, asm: "MOVB", typ: "Int8", addrSinkArg0: true}, // load from arg0 + arg1. arg2=mem + {name: "MOVHUloadidx", argLength: 3, reg: gp2load, asm: "MOVHU", typ: "UInt16", addrSinkArg0: true}, // load from arg0 + arg1. arg2=mem + {name: "MOVHloadidx", argLength: 3, reg: gp2load, asm: "MOVH", typ: "Int16", addrSinkArg0: true}, // load from arg0 + arg1. arg2=mem + + {name: "MOVWstoreidx", argLength: 4, reg: gp2store, asm: "MOVW", typ: "Mem", addrSinkArg0: true}, // store arg2 to arg0 + arg1. arg3=mem + {name: "MOVWstoreshiftLL", argLength: 4, reg: gp2store, asm: "MOVW", aux: "Int32", typ: "Mem", addrSinkArg0: true}, // store arg2 to arg0 + arg1<>auxInt, unsigned shift. arg3=mem + {name: "MOVWstoreshiftRA", argLength: 4, reg: gp2store, asm: "MOVW", aux: "Int32", typ: "Mem", addrSinkArg0: true}, // store arg2 to arg0 + arg1>>auxInt, signed shift. arg3=mem + {name: "MOVBstoreidx", argLength: 4, reg: gp2store, asm: "MOVB", typ: "Mem", addrSinkArg0: true}, // store arg2 to arg0 + arg1. arg3=mem + {name: "MOVHstoreidx", argLength: 4, reg: gp2store, asm: "MOVH", typ: "Mem", addrSinkArg0: true}, // store arg2 to arg0 + arg1. arg3=mem + + {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVBS", earlyOk: true}, // move from arg0, sign-extended from byte + {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU", earlyOk: true}, // move from arg0, unsign-extended from byte + {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVHS", earlyOk: true}, // move from arg0, sign-extended from half + {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU", earlyOk: true}, // move from arg0, unsign-extended from half + {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW", earlyOk: true}, // move from arg0 + + {name: "MOVWnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true, earlyOk: true}, // nop, return arg0 in same register + + {name: "MOVWF", argLength: 1, reg: gpfp, asm: "MOVWF", earlyOk: true}, // int32 -> float32 + {name: "MOVWD", argLength: 1, reg: gpfp, asm: "MOVWD", earlyOk: true}, // int32 -> float64 + {name: "MOVWUF", argLength: 1, reg: gpfp, asm: "MOVWF", earlyOk: true}, // uint32 -> float32, set U bit in the instruction + {name: "MOVWUD", argLength: 1, reg: gpfp, asm: "MOVWD", earlyOk: true}, // uint32 -> float64, set U bit in the instruction + {name: "MOVFW", argLength: 1, reg: fpgp, asm: "MOVFW", earlyOk: true}, // float32 -> int32 + {name: "MOVDW", argLength: 1, reg: fpgp, asm: "MOVDW", earlyOk: true}, // float64 -> int32 + {name: "MOVFWU", argLength: 1, reg: fpgp, asm: "MOVFW", earlyOk: true}, // float32 -> uint32, set U bit in the instruction + {name: "MOVDWU", argLength: 1, reg: fpgp, asm: "MOVDW", earlyOk: true}, // float64 -> uint32, set U bit in the instruction + {name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD", earlyOk: true}, // float32 -> float64 + {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF", earlyOk: true}, // float64 -> float32 // conditional instructions, for lowering shifts - {name: "CMOVWHSconst", argLength: 2, reg: gp1flags1, asm: "MOVW", aux: "Int32", resultInArg0: true}, // replace arg0 w/ const if flags indicates HS, arg1=flags - {name: "CMOVWLSconst", argLength: 2, reg: gp1flags1, asm: "MOVW", aux: "Int32", resultInArg0: true}, // replace arg0 w/ const if flags indicates LS, arg1=flags - {name: "SRAcond", argLength: 3, reg: gp2flags1, asm: "SRA"}, // arg0 >> 31 if flags indicates HS, arg0 >> arg1 otherwise, signed shift, arg2=flags + {name: "CMOVWHSconst", argLength: 2, reg: gp1flags1, asm: "MOVW", aux: "Int32", resultInArg0: true, earlyOk: true}, // replace arg0 w/ const if flags indicates HS, arg1=flags + {name: "CMOVWLSconst", argLength: 2, reg: gp1flags1, asm: "MOVW", aux: "Int32", resultInArg0: true, earlyOk: true}, // replace arg0 w/ const if flags indicates LS, arg1=flags + {name: "SRAcond", argLength: 3, reg: gp2flags1, asm: "SRA", earlyOk: true}, // arg0 >> 31 if flags indicates HS, arg0 >> arg1 otherwise, signed shift, arg2=flags // function calls - {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R7"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem - {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem + {name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem + {name: "CALLtailinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R7"), regMask{}}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem // pseudo-ops {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil. arg1=mem. - {name: "Equal", argLength: 1, reg: readflags}, // bool, true flags encode x==y false otherwise. - {name: "NotEqual", argLength: 1, reg: readflags}, // bool, true flags encode x!=y false otherwise. - {name: "LessThan", argLength: 1, reg: readflags}, // bool, true flags encode signed xy false otherwise. - {name: "GreaterEqual", argLength: 1, reg: readflags}, // bool, true flags encode signed x>=y false otherwise. - {name: "LessThanU", argLength: 1, reg: readflags}, // bool, true flags encode unsigned xy false otherwise. - {name: "GreaterEqualU", argLength: 1, reg: readflags}, // bool, true flags encode unsigned x>=y false otherwise. + {name: "Equal", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode x==y false otherwise. + {name: "NotEqual", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode x!=y false otherwise. + {name: "LessThan", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode signed xy false otherwise. + {name: "GreaterEqual", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode signed x>=y false otherwise. + {name: "LessThanU", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode unsigned xy false otherwise. + {name: "GreaterEqualU", argLength: 1, reg: readflags, earlyOk: true}, // bool, true flags encode unsigned x>=y false otherwise. // duffzero (must be 4-byte aligned) // arg0 = address of memory to zero (in R1, changed as side effect) @@ -462,6 +465,7 @@ func init() { clobbers: buildReg("R1 R12 R14"), // R14 is LR, R12 is linker trampoline scratch register }, faultOnNilArg0: true, + addrSinkArg0: true, }, // duffcopy (must be 4-byte aligned) @@ -480,6 +484,8 @@ func init() { }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // large or unaligned zeroing @@ -501,6 +507,8 @@ func init() { }, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // large or unaligned move @@ -524,6 +532,9 @@ func init() { clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + // TODO: could use addrSinkArg2 here. }, // Scheduler ensures LoweredGetClosurePtr occurs only in entry block, @@ -545,14 +556,14 @@ func init() { // when both are constant (normally both 0, as prove derives the fact that a [0] bounds // failure means the length must have also been 0). // AuxInt contains a report code (see PanicBounds in genericOps.go). - {name: "LoweredPanicBoundsRR", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{gp &^ lr, gp &^ lr}}, typ: "Mem", call: true}, // arg0=x, arg1=y, arg2=mem, returns memory. - {name: "LoweredPanicBoundsRC", argLength: 2, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{gp &^ lr}}, typ: "Mem", call: true}, // arg0=x, arg1=mem, returns memory. - {name: "LoweredPanicBoundsCR", argLength: 2, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{gp &^ lr}}, typ: "Mem", call: true}, // arg0=y, arg1=mem, returns memory. - {name: "LoweredPanicBoundsCC", argLength: 1, aux: "PanicBoundsCC", reg: regInfo{}, typ: "Mem", call: true}, // arg0=mem, returns memory. + {name: "LoweredPanicBoundsRR", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{gp.minus(lr), gp.minus(lr)}}, typ: "Mem", call: true}, // arg0=x, arg1=y, arg2=mem, returns memory. + {name: "LoweredPanicBoundsRC", argLength: 2, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{gp.minus(lr)}}, typ: "Mem", call: true}, // arg0=x, arg1=mem, returns memory. + {name: "LoweredPanicBoundsCR", argLength: 2, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{gp.minus(lr)}}, typ: "Mem", call: true}, // arg0=y, arg1=mem, returns memory. + {name: "LoweredPanicBoundsCC", argLength: 1, aux: "PanicBoundsCC", reg: regInfo{}, typ: "Mem", call: true}, // arg0=mem, returns memory. // Same as above, but the x value is 64 bits. - {name: "LoweredPanicExtendRR", argLength: 4, aux: "Int64", reg: regInfo{inputs: []regMask{r0 | r1 | r2 | r3, r0 | r1 | r2 | r3, gp}}, typ: "Mem", call: true}, // arg0=x_hi, arg1=x_lo, arg2=y, arg3=mem, returns memory. - {name: "LoweredPanicExtendRC", argLength: 3, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{r0 | r1 | r2 | r3, r0 | r1 | r2 | r3}}, typ: "Mem", call: true}, // arg0=x_hi, arg1=x_lo, arg2=mem, returns memory. + {name: "LoweredPanicExtendRR", argLength: 4, aux: "Int64", reg: regInfo{inputs: []regMask{r0.union(r1).union(r2).union(r3), r0.union(r1).union(r2).union(r3), gp}}, typ: "Mem", call: true}, // arg0=x_hi, arg1=x_lo, arg2=y, arg3=mem, returns memory. + {name: "LoweredPanicExtendRC", argLength: 3, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{r0.union(r1).union(r2).union(r3), r0.union(r1).union(r2).union(r3)}}, typ: "Mem", call: true}, // arg0=x_hi, arg1=x_lo, arg2=mem, returns memory. // Constant flag value. // Note: there's an "unordered" outcome for floating-point @@ -569,7 +580,7 @@ func init() { // It saves all GP registers if necessary, // but clobbers R14 (LR) because it's a call, and R12 which is linker trampoline scratch register. // Returns a pointer to a write barrier buffer in R8. - {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ gpg) | buildReg("R12 R14"), outputs: []regMask{buildReg("R8")}}, clobberFlags: true, aux: "Int64"}} + {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave.minus(gpg).union(buildReg("R12 R14")), outputs: []regMask{buildReg("R8")}}, clobberFlags: true, aux: "Int64"}} blocks := []blockData{ {name: "EQ", controls: 1}, diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64.rules b/src/cmd/compile/internal/ssa/_gen/LOONG64.rules index 287eedee37401b..4baa0229d68e86 100644 --- a/src/cmd/compile/internal/ssa/_gen/LOONG64.rules +++ b/src/cmd/compile/internal/ssa/_gen/LOONG64.rules @@ -15,6 +15,10 @@ (Select0 (Mul64uover x y)) => (MULV x y) (Select1 (Mul64uover x y)) => (SGTU (MULHVU x y) (MOVVconst [0])) +// 32 mul 32 -> 64 +(MULV r:(MOVWUreg x) s:(MOVWUreg y)) && r.Uses == 1 && s.Uses == 1 => (MULWVWU x y) +(MULV r:(MOVWreg x) s:(MOVWreg y)) && r.Uses == 1 && s.Uses == 1 => (MULWVW x y) + (Hmul64 ...) => (MULHV ...) (Hmul64u ...) => (MULHVU ...) (Hmul32 ...) => (MULH ...) @@ -203,10 +207,16 @@ (PopCount16 x) => (MOVWfpgp (VPCNT16 (MOVWgpfp (ZeroExt16to32 x)))) // math package intrinsics -(Sqrt ...) => (SQRTD ...) +(Sqrt ...) => (SQRTD ...) (Sqrt32 ...) => (SQRTF ...) + (Abs ...) => (ABSD ...) -(Copysign ...) => (FCOPYSGD ...) +(Copysign ...) => (FCOPYSGD ...) + +(RoundToEven ...) => (FRINTND ...) +(Floor ...) => (FRINTMD ...) +(Ceil ...) => (FRINTPD ...) +(Trunc ...) => (FRINTZD ...) (Min(64|32)F ...) => (FMIN(D|F) ...) (Max(64|32)F ...) => (FMAX(D|F) ...) @@ -444,6 +454,7 @@ (ClosureCall ...) => (CALLclosure ...) (InterCall ...) => (CALLinter ...) (TailCall ...) => (CALLtail ...) +(TailCallInter ...) => (CALLtailinter ...) // atomic intrinsics (AtomicLoad(8|32|64) ...) => (LoweredAtomicLoad(8|32|64) ...) @@ -611,15 +622,24 @@ (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem) // register indexed load -(MOVVload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVVloadidx ptr idx mem) -(MOVWUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr idx mem) -(MOVWload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx ptr idx mem) -(MOVHUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr idx mem) -(MOVHload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx ptr idx mem) -(MOVBUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr idx mem) -(MOVBload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx ptr idx mem) -(MOVFload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVFloadidx ptr idx mem) -(MOVDload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx ptr idx mem) +(MOVVload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVVloadidx ptr idx mem) +(MOVVload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVVloadidx ptr (SLLVconst [shift] idx) mem) +(MOVWUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr idx mem) +(MOVWUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr (SLLVconst [shift] idx) mem) +(MOVWload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx ptr idx mem) +(MOVWload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx ptr (SLLVconst [shift] idx) mem) +(MOVHUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr idx mem) +(MOVHUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr (SLLVconst [shift] idx) mem) +(MOVHload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx ptr idx mem) +(MOVHload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx ptr (SLLVconst [shift] idx) mem) +(MOVBUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr idx mem) +(MOVBUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr (SLLVconst [shift] idx) mem) +(MOVBload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx ptr idx mem) +(MOVBload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx ptr (SLLVconst [shift] idx) mem) +(MOVFload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVFloadidx ptr idx mem) +(MOVFload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVFloadidx ptr (SLLVconst [shift] idx) mem) +(MOVDload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx ptr idx mem) +(MOVDload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx ptr (SLLVconst [shift] idx) mem) (MOVVloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVVload [int32(c)] ptr mem) (MOVVloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVVload [int32(c)] ptr mem) (MOVWUloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVWUload [int32(c)] ptr mem) @@ -640,12 +660,18 @@ (MOVDloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVDload [int32(c)] ptr mem) // register indexed store -(MOVVstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVVstoreidx ptr idx val mem) -(MOVWstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr idx val mem) -(MOVHstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr idx val mem) -(MOVBstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr idx val mem) -(MOVFstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVFstoreidx ptr idx val mem) -(MOVDstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr idx val mem) +(MOVVstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVVstoreidx ptr idx val mem) +(MOVVstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVVstoreidx ptr (SLLVconst [shift] idx) val mem) +(MOVWstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr idx val mem) +(MOVWstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr (SLLVconst [shift] idx) val mem) +(MOVHstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr idx val mem) +(MOVHstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr (SLLVconst [shift] idx) val mem) +(MOVBstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr idx val mem) +(MOVBstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr (SLLVconst [shift] idx) val mem) +(MOVFstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVFstoreidx ptr idx val mem) +(MOVFstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVFstoreidx ptr (SLLVconst [shift] idx) val mem) +(MOVDstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr idx val mem) +(MOVDstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr (SLLVconst [shift] idx) val mem) (MOVVstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVVstore [int32(c)] ptr val mem) (MOVVstoreidx (MOVVconst [c]) idx val mem) && is32Bit(c) => (MOVVstore [int32(c)] idx val mem) (MOVWstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVWstore [int32(c)] ptr val mem) @@ -728,9 +754,6 @@ (MULV x (MOVVconst [c])) && canMulStrengthReduce(config, c) => {mulStrengthReduce(v, x, c)} -(MULV (NEGV x) (MOVVconst [c])) => (MULV x (MOVVconst [-c])) -(MULV (NEGV x) (NEGV y)) => (MULV x y) - (ADDV x0 x1:(SLLVconst [c] y)) && x1.Uses == 1 && c > 0 && c <= 4 => (ADDshiftLLV x0 y [c]) // fold constant in ADDshift op @@ -757,6 +780,9 @@ (SUBF (NEGF (MULF x y)) z) && z.Block.Func.useFMA(v) => (FNMADDF x y z) (SUBD (NEGD (MULD x y)) z) && z.Block.Func.useFMA(v) => (FNMADDD x y z) +// Absorb conversion between 32 bit and 64 bit if both src and dst are 32 bit. +(MOVDF ((ABS|SQRT)D (MOVFD x))) => ((ABS|SQRT)F x) + // generic simplifications (ADDV x (NEGV y)) => (SUBV x y) (SUBV x (NEGV y)) => (ADDV x y) @@ -827,6 +853,11 @@ (MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x) +// Avoid extending when already sufficiently shifted. +(MOVBUreg x:(SRLconst [c] y)) && c >= 24 => x +(MOVHUreg x:(SRLconst [c] y)) && c >= 16 => x +(MOVWUreg x:(SRLconst [c] y)) => x + // Avoid extending when already sufficiently masked. (MOVBreg x:(ANDconst [c] y)) && c >= 0 && int64(int8(c)) == c => x (MOVHreg x:(ANDconst [c] y)) && c >= 0 && int64(int16(c)) == c => x diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go index 7e8b8bf497b8ff..a08c91e2075bd3 100644 --- a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +++ b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go @@ -110,10 +110,10 @@ func init() { num[name] = i } buildReg := func(s string) regMask { - m := regMask(0) + m := regMask{} for _, r := range strings.Split(s, " ") { if n, ok := num[r]; ok { - m |= regMask(1) << uint(n) + m = m.addReg(uint(n)) continue } panic("register " + r + " not found") @@ -124,12 +124,12 @@ func init() { // Common individual register masks var ( gp = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31") // R1 is LR, R2 is thread pointer, R3 is stack pointer, R22 is g, R30 is REGTMP - gpg = gp | buildReg("g") - gpsp = gp | buildReg("SP") - gpspg = gpg | buildReg("SP") - gpspsbg = gpspg | buildReg("SB") + gpg = gp.union(buildReg("g")) + gpsp = gp.union(buildReg("SP")) + gpspg = gpg.union(buildReg("SP")) + gpspsbg = gpspg.union(buildReg("SB")) fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31") - callerSave = gp | fp | buildReg("g") // runtime.setg (and anything calling it) may clobber g + callerSave = gp.union(fp).union(buildReg("g")) // runtime.setg (and anything calling it) may clobber g first16 = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19") rz = buildReg("ZERO") ) @@ -138,11 +138,11 @@ func init() { gp01 = regInfo{inputs: nil, outputs: []regMask{gp}} gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}} gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}} - gp21 = regInfo{inputs: []regMask{gpg, gpg | rz}, outputs: []regMask{gp}} + gp21 = regInfo{inputs: []regMask{gpg, gpg.union(rz)}, outputs: []regMask{gp}} gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}} gp2load = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}} gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}} - gpstore2 = regInfo{inputs: []regMask{gpspsbg, gpg, gpg | rz}} + gpstore2 = regInfo{inputs: []regMask{gpspsbg, gpg, gpg.union(rz)}} gpoldatom = regInfo{inputs: []regMask{gpspsbg, gpg}} gpxchg = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}} gpcas = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{gp}} @@ -162,111 +162,115 @@ func init() { ) ops := []opData{ // unary ops - {name: "NEGV", argLength: 1, reg: gp11}, // -arg0 - {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32 - {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 + {name: "NEGV", argLength: 1, reg: gp11, earlyOk: true}, // -arg0 + {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF", earlyOk: true}, // -arg0, float32 + {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD", earlyOk: true}, // -arg0, float64 - {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64 - {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 + {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD", earlyOk: true}, // sqrt(arg0), float64 + {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF", earlyOk: true}, // sqrt(arg0), float32 - {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64 + {name: "ABSF", argLength: 1, reg: fp11, asm: "ABSF", earlyOk: true}, // abs(arg0), float32 + {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD", earlyOk: true}, // abs(arg0), float64 - {name: "CLZW", argLength: 1, reg: gp11, asm: "CLZW"}, // Count leading (high order) zeroes (returns 0-32) - {name: "CLZV", argLength: 1, reg: gp11, asm: "CLZV"}, // Count leading (high order) zeroes (returns 0-64) - {name: "CTZW", argLength: 1, reg: gp11, asm: "CTZW"}, // Count trailing (low order) zeroes (returns 0-32) - {name: "CTZV", argLength: 1, reg: gp11, asm: "CTZV"}, // Count trailing (low order) zeroes (returns 0-64) + {name: "CLZW", argLength: 1, reg: gp11, asm: "CLZW", earlyOk: true}, // Count leading (high order) zeroes (returns 0-32) + {name: "CLZV", argLength: 1, reg: gp11, asm: "CLZV", earlyOk: true}, // Count leading (high order) zeroes (returns 0-64) + {name: "CTZW", argLength: 1, reg: gp11, asm: "CTZW", earlyOk: true}, // Count trailing (low order) zeroes (returns 0-32) + {name: "CTZV", argLength: 1, reg: gp11, asm: "CTZV", earlyOk: true}, // Count trailing (low order) zeroes (returns 0-64) - {name: "REVB2H", argLength: 1, reg: gp11, asm: "REVB2H"}, // Swap bytes: 0x11223344 -> 0x22114433 (sign extends to 64 bits) - {name: "REVB2W", argLength: 1, reg: gp11, asm: "REVB2W"}, // Swap bytes: 0x1122334455667788 -> 0x4433221188776655 - {name: "REVB4H", argLength: 1, reg: gp11, asm: "REVB4H"}, // Swap bytes: 0x1122334455667788 -> 0x2211443366558877 - {name: "REVBV", argLength: 1, reg: gp11, asm: "REVBV"}, // Swap bytes: 0x1122334455667788 -> 0x8877665544332211 + {name: "REVB2H", argLength: 1, reg: gp11, asm: "REVB2H", earlyOk: true}, // Swap bytes: 0x11223344 -> 0x22114433 (sign extends to 64 bits) + {name: "REVB2W", argLength: 1, reg: gp11, asm: "REVB2W", earlyOk: true}, // Swap bytes: 0x1122334455667788 -> 0x4433221188776655 + {name: "REVB4H", argLength: 1, reg: gp11, asm: "REVB4H", earlyOk: true}, // Swap bytes: 0x1122334455667788 -> 0x2211443366558877 + {name: "REVBV", argLength: 1, reg: gp11, asm: "REVBV", earlyOk: true}, // Swap bytes: 0x1122334455667788 -> 0x8877665544332211 - {name: "BITREV4B", argLength: 1, reg: gp11, asm: "BITREV4B"}, // Reverse the bits of each byte inside a 32-bit arg[0] - {name: "BITREVW", argLength: 1, reg: gp11, asm: "BITREVW"}, // Reverse the bits in a 32-bit arg[0] - {name: "BITREVV", argLength: 1, reg: gp11, asm: "BITREVV"}, // Reverse the bits in a 64-bit arg[0] + {name: "BITREV4B", argLength: 1, reg: gp11, asm: "BITREV4B", earlyOk: true}, // Reverse the bits of each byte inside a 32-bit arg[0] + {name: "BITREVW", argLength: 1, reg: gp11, asm: "BITREVW", earlyOk: true}, // Reverse the bits in a 32-bit arg[0] + {name: "BITREVV", argLength: 1, reg: gp11, asm: "BITREVV", earlyOk: true}, // Reverse the bits in a 64-bit arg[0] + // Note: these must be preceded by a check of the LSX bit {name: "VPCNT64", argLength: 1, reg: fp11, asm: "VPCNTV"}, // count set bits for each 64-bit unit and store the result in each 64-bit unit {name: "VPCNT32", argLength: 1, reg: fp11, asm: "VPCNTW"}, // count set bits for each 32-bit unit and store the result in each 32-bit unit {name: "VPCNT16", argLength: 1, reg: fp11, asm: "VPCNTH"}, // count set bits for each 16-bit unit and store the result in each 16-bit unit // binary ops - {name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true}, // arg0 + arg1 - {name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops. - {name: "ADDV16const", argLength: 1, reg: gp11sp, asm: "ADDV16", aux: "Int64"}, // arg0 + auxInt. auxInt is signed 32-bit and is a multiple of 65536, also in other *const ops. - {name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"}, // arg0 - arg1 - {name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64"}, // arg0 - auxInt - - {name: "MULV", argLength: 2, reg: gp21, asm: "MULV", commutative: true, typ: "Int64"}, // arg0 * arg1 - {name: "MULHV", argLength: 2, reg: gp21, asm: "MULHV", commutative: true, typ: "Int64"}, // (arg0 * arg1) >> 64, signed - {name: "MULHVU", argLength: 2, reg: gp21, asm: "MULHVU", commutative: true, typ: "UInt64"}, // (arg0 * arg1) >> 64, unsigned - {name: "MULH", argLength: 2, reg: gp21, asm: "MULH", commutative: true, typ: "Int32"}, // (arg0 * arg1) >> 32, signed - {name: "MULHU", argLength: 2, reg: gp21, asm: "MULHU", commutative: true, typ: "UInt32"}, // (arg0 * arg1) >> 32, unsigned - {name: "DIVV", argLength: 2, reg: gp21, asm: "DIVV", typ: "Int64"}, // arg0 / arg1, signed - {name: "DIVVU", argLength: 2, reg: gp21, asm: "DIVVU", typ: "UInt64"}, // arg0 / arg1, unsigned - {name: "REMV", argLength: 2, reg: gp21, asm: "REMV", typ: "Int64"}, // arg0 / arg1, signed - {name: "REMVU", argLength: 2, reg: gp21, asm: "REMVU", typ: "UInt64"}, // arg0 / arg1, unsigned - - {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1 - {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true}, // arg0 + arg1 - {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF"}, // arg0 - arg1 - {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"}, // arg0 - arg1 - {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1 - {name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1 - {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1 - {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1 - - {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1 - {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64"}, // arg0 & auxInt - {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0 | arg1 - {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"}, // arg0 | auxInt - {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, typ: "UInt64"}, // arg0 ^ arg1 - {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", typ: "UInt64"}, // arg0 ^ auxInt - {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true}, // ^(arg0 | arg1) - {name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int64"}, // ^(arg0 | auxInt) - {name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN"}, // arg0 & ^arg1 - {name: "ORN", argLength: 2, reg: gp21, asm: "ORN"}, // arg0 | ^arg1 - - {name: "FMADDF", argLength: 3, reg: fp31, asm: "FMADDF", commutative: true, typ: "Float32"}, // (arg0 * arg1) + arg2 - {name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", commutative: true, typ: "Float64"}, // (arg0 * arg1) + arg2 - {name: "FMSUBF", argLength: 3, reg: fp31, asm: "FMSUBF", commutative: true, typ: "Float32"}, // (arg0 * arg1) - arg2 - {name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", commutative: true, typ: "Float64"}, // (arg0 * arg1) - arg2 - {name: "FNMADDF", argLength: 3, reg: fp31, asm: "FNMADDF", commutative: true, typ: "Float32"}, // -((arg0 * arg1) + arg2) - {name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD", commutative: true, typ: "Float64"}, // -((arg0 * arg1) + arg2) - {name: "FNMSUBF", argLength: 3, reg: fp31, asm: "FNMSUBF", commutative: true, typ: "Float32"}, // -((arg0 * arg1) - arg2) - {name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD", commutative: true, typ: "Float64"}, // -((arg0 * arg1) - arg2) - - {name: "FMINF", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMINF", commutative: true, typ: "Float32"}, // min(arg0, arg1), float32 - {name: "FMIND", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMIND", commutative: true, typ: "Float64"}, // min(arg0, arg1), float64 - {name: "FMAXF", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXF", commutative: true, typ: "Float32"}, // max(arg0, arg1), float32 - {name: "FMAXD", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXD", commutative: true, typ: "Float64"}, // max(arg0, arg1), float64 - - {name: "MASKEQZ", argLength: 2, reg: gp21, asm: "MASKEQZ"}, // returns 0 if arg1 == 0, otherwise returns arg0 - {name: "MASKNEZ", argLength: 2, reg: gp21, asm: "MASKNEZ"}, // returns 0 if arg1 != 0, otherwise returns arg0 - {name: "FCOPYSGD", argLength: 2, reg: fp21, asm: "FCOPYSGD"}, // float64 + {name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64", earlyOk: true}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops. + {name: "ADDV16const", argLength: 1, reg: gp11sp, asm: "ADDV16", aux: "Int64", earlyOk: true}, // arg0 + auxInt. auxInt is signed 32-bit and is a multiple of 65536, also in other *const ops. + {name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU", earlyOk: true}, // arg0 - arg1 + {name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64", earlyOk: true}, // arg0 - auxInt + + {name: "MULV", argLength: 2, reg: gp21, asm: "MULV", commutative: true, typ: "Int64", earlyOk: true}, // arg0 * arg1 + {name: "MULHV", argLength: 2, reg: gp21, asm: "MULHV", commutative: true, typ: "Int64", earlyOk: true}, // (arg0 * arg1) >> 64, signed + {name: "MULHVU", argLength: 2, reg: gp21, asm: "MULHVU", commutative: true, typ: "UInt64", earlyOk: true}, // (arg0 * arg1) >> 64, unsigned + {name: "MULH", argLength: 2, reg: gp21, asm: "MULH", commutative: true, typ: "Int32", earlyOk: true}, // (arg0 * arg1) >> 32, signed + {name: "MULHU", argLength: 2, reg: gp21, asm: "MULHU", commutative: true, typ: "UInt32", earlyOk: true}, // (arg0 * arg1) >> 32, unsigned + {name: "DIVV", argLength: 2, reg: gp21, asm: "DIVV", typ: "Int64"}, // arg0 / arg1, signed + {name: "DIVVU", argLength: 2, reg: gp21, asm: "DIVVU", typ: "UInt64"}, // arg0 / arg1, unsigned + {name: "REMV", argLength: 2, reg: gp21, asm: "REMV", typ: "Int64"}, // arg0 / arg1, signed + {name: "REMVU", argLength: 2, reg: gp21, asm: "REMVU", typ: "UInt64"}, // arg0 / arg1, unsigned + {name: "MULWVW", argLength: 2, reg: gp21, asm: "MULWVW", commutative: true, earlyOk: true}, // arg0 * arg1, signed, 32-bit mult results in 64-bit + {name: "MULWVWU", argLength: 2, reg: gp21, asm: "MULWVWU", commutative: true, earlyOk: true}, // arg0 * arg1, unsigned, 32-bit mult results in 64-bit + + {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF", earlyOk: true}, // arg0 - arg1 + {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD", earlyOk: true}, // arg0 - arg1 + {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1 + {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1 + + {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64", earlyOk: true}, // arg0 & auxInt + {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true, earlyOk: true}, // arg0 | arg1 + {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64", earlyOk: true}, // arg0 | auxInt + {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, typ: "UInt64", earlyOk: true}, // arg0 ^ arg1 + {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", typ: "UInt64", earlyOk: true}, // arg0 ^ auxInt + {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true, earlyOk: true}, // ^(arg0 | arg1) + {name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int64", earlyOk: true}, // ^(arg0 | auxInt) + {name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN", earlyOk: true}, // arg0 & ^arg1 + {name: "ORN", argLength: 2, reg: gp21, asm: "ORN", earlyOk: true}, // arg0 | ^arg1 + + {name: "FMADDF", argLength: 3, reg: fp31, asm: "FMADDF", commutative: true, typ: "Float32", earlyOk: true}, // (arg0 * arg1) + arg2 + {name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", commutative: true, typ: "Float64", earlyOk: true}, // (arg0 * arg1) + arg2 + {name: "FMSUBF", argLength: 3, reg: fp31, asm: "FMSUBF", commutative: true, typ: "Float32", earlyOk: true}, // (arg0 * arg1) - arg2 + {name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", commutative: true, typ: "Float64", earlyOk: true}, // (arg0 * arg1) - arg2 + {name: "FNMADDF", argLength: 3, reg: fp31, asm: "FNMADDF", commutative: true, typ: "Float32", earlyOk: true}, // -((arg0 * arg1) + arg2) + {name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD", commutative: true, typ: "Float64", earlyOk: true}, // -((arg0 * arg1) + arg2) + {name: "FNMSUBF", argLength: 3, reg: fp31, asm: "FNMSUBF", commutative: true, typ: "Float32", earlyOk: true}, // -((arg0 * arg1) - arg2) + {name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD", commutative: true, typ: "Float64", earlyOk: true}, // -((arg0 * arg1) - arg2) + + {name: "FMINF", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMINF", commutative: true, typ: "Float32", earlyOk: true}, // min(arg0, arg1), float32 + {name: "FMIND", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMIND", commutative: true, typ: "Float64", earlyOk: true}, // min(arg0, arg1), float64 + {name: "FMAXF", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXF", commutative: true, typ: "Float32", earlyOk: true}, // max(arg0, arg1), float32 + {name: "FMAXD", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXD", commutative: true, typ: "Float64", earlyOk: true}, // max(arg0, arg1), float64 + + {name: "MASKEQZ", argLength: 2, reg: gp21, asm: "MASKEQZ", earlyOk: true}, // returns 0 if arg1 == 0, otherwise returns arg0 + {name: "MASKNEZ", argLength: 2, reg: gp21, asm: "MASKNEZ", earlyOk: true}, // returns 0 if arg1 != 0, otherwise returns arg0 + {name: "FCOPYSGD", argLength: 2, reg: fp21, asm: "FCOPYSGD", earlyOk: true}, // float64 // shifts - {name: "SLL", argLength: 2, reg: gp21, asm: "SLL"}, // arg0 << arg1, shift amount is mod 32 - {name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV"}, // arg0 << arg1, shift amount is mod 64 - {name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int64"}, // arg0 << auxInt, auxInt should be in the range 0 to 31. - {name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64"}, // arg0 << auxInt, auxInt should be in the range 0 to 63. - {name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> arg1, shift amount is mod 32 - {name: "SRLV", argLength: 2, reg: gp21, asm: "SRLV"}, // arg0 >> arg1, unsigned, shift amount is mod 64 - {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int64"}, // arg0 >> auxInt, auxInt should be in the range 0 to 31. - {name: "SRLVconst", argLength: 1, reg: gp11, asm: "SRLV", aux: "Int64"}, // arg0 >> auxInt, unsigned - {name: "SRA", argLength: 2, reg: gp21, asm: "SRA"}, // arg0 >> arg1, shift amount is mod 32 - {name: "SRAV", argLength: 2, reg: gp21, asm: "SRAV"}, // arg0 >> arg1, signed, shift amount is mod 64 - {name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int64"}, // arg0 >> auxInt, signed, auxInt should be in the range 0 to 31. - {name: "SRAVconst", argLength: 1, reg: gp11, asm: "SRAV", aux: "Int64"}, // arg0 >> auxInt, signed - {name: "ROTR", argLength: 2, reg: gp21, asm: "ROTR"}, // arg0 right rotate by (arg1 mod 32) bits - {name: "ROTRV", argLength: 2, reg: gp21, asm: "ROTRV"}, // arg0 right rotate by (arg1 mod 64) bits - {name: "ROTRconst", argLength: 1, reg: gp11, asm: "ROTR", aux: "Int64"}, // uint32(arg0) right rotate by auxInt bits, auxInt should be in the range 0 to 31. - {name: "ROTRVconst", argLength: 1, reg: gp11, asm: "ROTRV", aux: "Int64"}, // arg0 right rotate by auxInt bits, auxInt should be in the range 0 to 63. + {name: "SLL", argLength: 2, reg: gp21, asm: "SLL", earlyOk: true}, // arg0 << arg1, shift amount is mod 32 + {name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV", earlyOk: true}, // arg0 << arg1, shift amount is mod 64 + {name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int64", earlyOk: true}, // arg0 << auxInt, auxInt should be in the range 0 to 31. + {name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64", earlyOk: true}, // arg0 << auxInt, auxInt should be in the range 0 to 63. + {name: "SRL", argLength: 2, reg: gp21, asm: "SRL", earlyOk: true}, // arg0 >> arg1, shift amount is mod 32 + {name: "SRLV", argLength: 2, reg: gp21, asm: "SRLV", earlyOk: true}, // arg0 >> arg1, unsigned, shift amount is mod 64 + {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int64", earlyOk: true}, // arg0 >> auxInt, auxInt should be in the range 0 to 31. + {name: "SRLVconst", argLength: 1, reg: gp11, asm: "SRLV", aux: "Int64", earlyOk: true}, // arg0 >> auxInt, unsigned + {name: "SRA", argLength: 2, reg: gp21, asm: "SRA", earlyOk: true}, // arg0 >> arg1, shift amount is mod 32 + {name: "SRAV", argLength: 2, reg: gp21, asm: "SRAV", earlyOk: true}, // arg0 >> arg1, signed, shift amount is mod 64 + {name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int64", earlyOk: true}, // arg0 >> auxInt, signed, auxInt should be in the range 0 to 31. + {name: "SRAVconst", argLength: 1, reg: gp11, asm: "SRAV", aux: "Int64", earlyOk: true}, // arg0 >> auxInt, signed + {name: "ROTR", argLength: 2, reg: gp21, asm: "ROTR", earlyOk: true}, // arg0 right rotate by (arg1 mod 32) bits + {name: "ROTRV", argLength: 2, reg: gp21, asm: "ROTRV", earlyOk: true}, // arg0 right rotate by (arg1 mod 64) bits + {name: "ROTRconst", argLength: 1, reg: gp11, asm: "ROTR", aux: "Int64", earlyOk: true}, // uint32(arg0) right rotate by auxInt bits, auxInt should be in the range 0 to 31. + {name: "ROTRVconst", argLength: 1, reg: gp11, asm: "ROTRV", aux: "Int64", earlyOk: true}, // arg0 right rotate by auxInt bits, auxInt should be in the range 0 to 63. // comparisons - {name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool"}, // 1 if arg0 > arg1 (signed), 0 otherwise - {name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (signed), 0 otherwise - {name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"}, // 1 if arg0 > arg1 (unsigned), 0 otherwise - {name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (unsigned), 0 otherwise + {name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool", earlyOk: true}, // 1 if arg0 > arg1 (signed), 0 otherwise + {name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int64", typ: "Bool", earlyOk: true}, // 1 if auxInt > arg0 (signed), 0 otherwise + {name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool", earlyOk: true}, // 1 if arg0 > arg1 (unsigned), 0 otherwise + {name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int64", typ: "Bool", earlyOk: true}, // 1 if auxInt > arg0 (unsigned), 0 otherwise {name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32 {name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64 @@ -278,89 +282,96 @@ func init() { // bitfield ops // for bstrpick.w msbw is auxInt>>5, lsbw is auxInt&0x1f // for bstrpick.d msbd is auxInt>>6, lsbd is auxInt&0x3f - {name: "BSTRPICKW", argLength: 1, reg: gp11, asm: "BSTRPICKW", aux: "Int64"}, - {name: "BSTRPICKV", argLength: 1, reg: gp11, asm: "BSTRPICKV", aux: "Int64"}, + {name: "BSTRPICKW", argLength: 1, reg: gp11, asm: "BSTRPICKW", aux: "Int64", earlyOk: true}, + {name: "BSTRPICKV", argLength: 1, reg: gp11, asm: "BSTRPICKV", aux: "Int64", earlyOk: true}, // moves - {name: "MOVVconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVV", typ: "UInt64", rematerializeable: true}, // auxint - {name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVF", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float - {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true}, // auxint as 64-bit float - - {name: "MOVVaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP") | buildReg("SB")}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVV", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB - - {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVWUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVWU", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVVload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVV", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVVconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVV", typ: "UInt64", rematerializeable: true, earlyOk: true}, // auxint + {name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVF", typ: "Float32", rematerializeable: true, earlyOk: true}, // auxint as 64-bit float, convert to 32-bit float + {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true, earlyOk: true}, // auxint as 64-bit float + + {name: "MOVVaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP").union(buildReg("SB"))}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVV", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB + + {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "Int32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVWUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVWU", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVVload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVV", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. // register indexed load - {name: "MOVVloadidx", argLength: 3, reg: gp2load, asm: "MOVV", typ: "UInt64"}, // load 64-bit dword from arg0 + arg1, arg2 = mem. - {name: "MOVWloadidx", argLength: 3, reg: gp2load, asm: "MOVW", typ: "Int32"}, // load 32-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. - {name: "MOVWUloadidx", argLength: 3, reg: gp2load, asm: "MOVWU", typ: "UInt32"}, // load 32-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. - {name: "MOVHloadidx", argLength: 3, reg: gp2load, asm: "MOVH", typ: "Int16"}, // load 16-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. - {name: "MOVHUloadidx", argLength: 3, reg: gp2load, asm: "MOVHU", typ: "UInt16"}, // load 16-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. - {name: "MOVBloadidx", argLength: 3, reg: gp2load, asm: "MOVB", typ: "Int8"}, // load 8-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. - {name: "MOVBUloadidx", argLength: 3, reg: gp2load, asm: "MOVBU", typ: "UInt8"}, // load 8-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. - {name: "MOVFloadidx", argLength: 3, reg: fp2load, asm: "MOVF", typ: "Float32"}, // load 32-bit float from arg0 + arg1, arg2=mem. - {name: "MOVDloadidx", argLength: 3, reg: fp2load, asm: "MOVD", typ: "Float64"}, // load 64-bit float from arg0 + arg1, arg2=mem. - - {name: "MOVBstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg | rz}}, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVHstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg | rz}}, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVWstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg | rz}}, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVVstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg | rz}}, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVVloadidx", argLength: 3, reg: gp2load, asm: "MOVV", typ: "UInt64", addrSinkArg0: true}, // load 64-bit dword from arg0 + arg1, arg2 = mem. + {name: "MOVWloadidx", argLength: 3, reg: gp2load, asm: "MOVW", typ: "Int32", addrSinkArg0: true}, // load 32-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. + {name: "MOVWUloadidx", argLength: 3, reg: gp2load, asm: "MOVWU", typ: "UInt32", addrSinkArg0: true}, // load 32-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. + {name: "MOVHloadidx", argLength: 3, reg: gp2load, asm: "MOVH", typ: "Int16", addrSinkArg0: true}, // load 16-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. + {name: "MOVHUloadidx", argLength: 3, reg: gp2load, asm: "MOVHU", typ: "UInt16", addrSinkArg0: true}, // load 16-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. + {name: "MOVBloadidx", argLength: 3, reg: gp2load, asm: "MOVB", typ: "Int8", addrSinkArg0: true}, // load 8-bit word from arg0 + arg1, sign-extended to 64-bit, arg2=mem. + {name: "MOVBUloadidx", argLength: 3, reg: gp2load, asm: "MOVBU", typ: "UInt8", addrSinkArg0: true}, // load 8-bit word from arg0 + arg1, zero-extended to 64-bit, arg2=mem. + {name: "MOVFloadidx", argLength: 3, reg: fp2load, asm: "MOVF", typ: "Float32", addrSinkArg0: true}, // load 32-bit float from arg0 + arg1, arg2=mem. + {name: "MOVDloadidx", argLength: 3, reg: fp2load, asm: "MOVD", typ: "Float64", addrSinkArg0: true}, // load 64-bit float from arg0 + arg1, arg2=mem. + + {name: "MOVBstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg.union(rz)}}, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVHstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg.union(rz)}}, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVWstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg.union(rz)}}, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVVstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg.union(rz)}}, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. // register indexed store - {name: "MOVBstoreidx", argLength: 4, reg: gpstore2, asm: "MOVB", typ: "Mem"}, // store 1 byte of arg2 to arg0 + arg1, arg3 = mem. - {name: "MOVHstoreidx", argLength: 4, reg: gpstore2, asm: "MOVH", typ: "Mem"}, // store 2 bytes of arg2 to arg0 + arg1, arg3 = mem. - {name: "MOVWstoreidx", argLength: 4, reg: gpstore2, asm: "MOVW", typ: "Mem"}, // store 4 bytes of arg2 to arg0 + arg1, arg3 = mem. - {name: "MOVVstoreidx", argLength: 4, reg: gpstore2, asm: "MOVV", typ: "Mem"}, // store 8 bytes of arg2 to arg0 + arg1, arg3 = mem. - {name: "MOVFstoreidx", argLength: 4, reg: fpstore2, asm: "MOVF", typ: "Mem"}, // store 32-bit float of arg2 to arg0 + arg1, arg3=mem. - {name: "MOVDstoreidx", argLength: 4, reg: fpstore2, asm: "MOVD", typ: "Mem"}, // store 64-bit float of arg2 to arg0 + arg1, arg3=mem. + {name: "MOVBstoreidx", argLength: 4, reg: gpstore2, asm: "MOVB", typ: "Mem", addrSinkArg0: true}, // store 1 byte of arg2 to arg0 + arg1, arg3 = mem. + {name: "MOVHstoreidx", argLength: 4, reg: gpstore2, asm: "MOVH", typ: "Mem", addrSinkArg0: true}, // store 2 bytes of arg2 to arg0 + arg1, arg3 = mem. + {name: "MOVWstoreidx", argLength: 4, reg: gpstore2, asm: "MOVW", typ: "Mem", addrSinkArg0: true}, // store 4 bytes of arg2 to arg0 + arg1, arg3 = mem. + {name: "MOVVstoreidx", argLength: 4, reg: gpstore2, asm: "MOVV", typ: "Mem", addrSinkArg0: true}, // store 8 bytes of arg2 to arg0 + arg1, arg3 = mem. + {name: "MOVFstoreidx", argLength: 4, reg: fpstore2, asm: "MOVF", typ: "Mem", addrSinkArg0: true}, // store 32-bit float of arg2 to arg0 + arg1, arg3=mem. + {name: "MOVDstoreidx", argLength: 4, reg: fpstore2, asm: "MOVD", typ: "Mem", addrSinkArg0: true}, // store 64-bit float of arg2 to arg0 + arg1, arg3=mem. // moves (no conversion) - {name: "MOVWfpgp", argLength: 1, reg: fpgp, asm: "MOVW"}, // move float32 to int32 (no conversion). - {name: "MOVWgpfp", argLength: 1, reg: gpfp, asm: "MOVW"}, // move int32 to float32 (no conversion). - {name: "MOVVfpgp", argLength: 1, reg: fpgp, asm: "MOVV"}, // move float64 to int64 (no conversion). - {name: "MOVVgpfp", argLength: 1, reg: gpfp, asm: "MOVV"}, // move int64 to float64 (no conversion). + {name: "MOVWfpgp", argLength: 1, reg: fpgp, asm: "MOVW", earlyOk: true}, // move float32 to int32 (no conversion). + {name: "MOVWgpfp", argLength: 1, reg: gpfp, asm: "MOVW", earlyOk: true}, // move int32 to float32 (no conversion). + {name: "MOVVfpgp", argLength: 1, reg: fpgp, asm: "MOVV", earlyOk: true}, // move float64 to int64 (no conversion). + {name: "MOVVgpfp", argLength: 1, reg: gpfp, asm: "MOVV", earlyOk: true}, // move int64 to float64 (no conversion). // conversions - {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte - {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte - {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"}, // move from arg0, sign-extended from half - {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half - {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"}, // move from arg0, sign-extended from word - {name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU"}, // move from arg0, unsign-extended from word - {name: "MOVVreg", argLength: 1, reg: gp11, asm: "MOVV"}, // move from arg0 - - {name: "MOVVnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true}, // nop, return arg0 in same register - - {name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF"}, // int32 -> float32 - {name: "MOVWD", argLength: 1, reg: fp11, asm: "MOVWD"}, // int32 -> float64 - {name: "MOVVF", argLength: 1, reg: fp11, asm: "MOVVF"}, // int64 -> float32 - {name: "MOVVD", argLength: 1, reg: fp11, asm: "MOVVD"}, // int64 -> float64 - {name: "TRUNCFW", argLength: 1, reg: fp11, asm: "TRUNCFW"}, // float32 -> int32 - {name: "TRUNCDW", argLength: 1, reg: fp11, asm: "TRUNCDW"}, // float64 -> int32 - {name: "TRUNCFV", argLength: 1, reg: fp11, asm: "TRUNCFV"}, // float32 -> int64 - {name: "TRUNCDV", argLength: 1, reg: fp11, asm: "TRUNCDV"}, // float64 -> int64 - {name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD"}, // float32 -> float64 - {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF"}, // float64 -> float32 + {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB", earlyOk: true}, // move from arg0, sign-extended from byte + {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU", earlyOk: true}, // move from arg0, unsign-extended from byte + {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH", earlyOk: true}, // move from arg0, sign-extended from half + {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU", earlyOk: true}, // move from arg0, unsign-extended from half + {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW", earlyOk: true}, // move from arg0, sign-extended from word + {name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU", earlyOk: true}, // move from arg0, unsign-extended from word + {name: "MOVVreg", argLength: 1, reg: gp11, asm: "MOVV", earlyOk: true}, // move from arg0 + + {name: "MOVVnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true, earlyOk: true}, // nop, return arg0 in same register + + {name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF", earlyOk: true}, // int32 -> float32 + {name: "MOVWD", argLength: 1, reg: fp11, asm: "MOVWD", earlyOk: true}, // int32 -> float64 + {name: "MOVVF", argLength: 1, reg: fp11, asm: "MOVVF", earlyOk: true}, // int64 -> float32 + {name: "MOVVD", argLength: 1, reg: fp11, asm: "MOVVD", earlyOk: true}, // int64 -> float64 + {name: "TRUNCFW", argLength: 1, reg: fp11, asm: "TRUNCFW", earlyOk: true}, // float32 -> int32 + {name: "TRUNCDW", argLength: 1, reg: fp11, asm: "TRUNCDW", earlyOk: true}, // float64 -> int32 + {name: "TRUNCFV", argLength: 1, reg: fp11, asm: "TRUNCFV", earlyOk: true}, // float32 -> int64 + {name: "TRUNCDV", argLength: 1, reg: fp11, asm: "TRUNCDV", earlyOk: true}, // float64 -> int64 + {name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD", earlyOk: true}, // float32 -> float64 + {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF", earlyOk: true}, // float64 -> float32 + + // 64-bit floating-point round to integers in 64-bit FP format + {name: "FRINTND", argLength: 1, reg: fp11, asm: "VFRINTRNED"}, // Round (ties to even; ; 0.5 -> 0, 1.5 -> 2) + {name: "FRINTMD", argLength: 1, reg: fp11, asm: "VFRINTRMD"}, // Floor (towards Minus; 0.5 -> 0, -0.5 -> -1) + {name: "FRINTPD", argLength: 1, reg: fp11, asm: "VFRINTRPD"}, // Ceil (towards Positive; 0.5 -> 1, -0.5 -> 0) + {name: "FRINTZD", argLength: 1, reg: fp11, asm: "VFRINTRZD"}, // Trunc (towards Zero; 0.5 -> 0, -0.5 -> 0)) // Round ops to block fused-multiply-add extraction. - {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true}, - {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true}, + {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true, earlyOk: true}, + {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true, earlyOk: true}, // function calls - {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem - {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem - {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{gpsp, buildReg("R29"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem - {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtailinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{gpsp, buildReg("R29"), regMask{}}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem // medium zeroing // arg0 = address of memory to zero @@ -375,6 +386,7 @@ func init() { inputs: []regMask{gp}, }, faultOnNilArg0: true, + addrSinkArg0: true, }, // large zeroing @@ -388,10 +400,12 @@ func init() { argLength: 2, reg: regInfo{ inputs: []regMask{gp}, + clobbers: buildReg("F31"), clobbersArg0: true, }, faultOnNilArg0: true, needIntTemp: true, + addrSinkArg0: true, }, // medium copying @@ -405,11 +419,13 @@ func init() { aux: "Int64", argLength: 3, reg: regInfo{ - inputs: []regMask{gp &^ buildReg("R20"), gp &^ buildReg("R20")}, - clobbers: buildReg("R20"), + inputs: []regMask{gp.minus(buildReg("R23")), gp.minus(buildReg("R23"))}, + clobbers: buildReg("R23"), }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // large copying @@ -423,13 +439,15 @@ func init() { aux: "Int64", argLength: 3, reg: regInfo{ - inputs: []regMask{gp &^ buildReg("R20 R21"), gp &^ buildReg("R20 R21")}, - clobbers: buildReg("R20 R21"), + inputs: []regMask{gp.minus(buildReg("R23 R24")), gp.minus(buildReg("R23 R24"))}, + clobbers: buildReg("R23 R24"), clobbersArg0: true, clobbersArg1: true, }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // Atomic operations. @@ -520,8 +538,8 @@ func init() { // pseudo-ops {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil. arg1=mem. - {name: "FPFlagTrue", argLength: 1, reg: readflags}, // bool, true if FP flag is true - {name: "FPFlagFalse", argLength: 1, reg: readflags}, // bool, true if FP flag is false + {name: "FPFlagTrue", argLength: 1, reg: readflags, earlyOk: true}, // bool, true if FP flag is true + {name: "FPFlagFalse", argLength: 1, reg: readflags, earlyOk: true}, // bool, true if FP flag is false // Scheduler ensures LoweredGetClosurePtr occurs only in entry block, // and sorts it to the very beginning of the block to prevent other @@ -542,7 +560,7 @@ func init() { // but clobbers R1 (LR) because it's a call // and R30 (REGTMP). // Returns a pointer to a write barrier buffer in R29. - {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ gpg) | buildReg("R1"), outputs: []regMask{buildReg("R29")}}, clobberFlags: true, aux: "Int64"}, + {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave.minus(gpg).union(buildReg("R1")), outputs: []regMask{buildReg("R29")}}, clobberFlags: true, aux: "Int64"}, // Do data barrier. arg0=memorys {name: "LoweredPubBarrier", argLength: 1, asm: "DBAR", hasSideEffects: true}, @@ -565,8 +583,8 @@ func init() { {name: "PRELD", argLength: 2, aux: "Int64", reg: preldreg, asm: "PRELD", hasSideEffects: true}, {name: "PRELDX", argLength: 2, aux: "Int64", reg: preldreg, asm: "PRELDX", hasSideEffects: true}, - {name: "ADDshiftLLV", argLength: 2, aux: "Int64", reg: gp21, asm: "ALSLV"}, // arg0 + arg1< x y)) => (SGTU x (ADD x y)) (Add32withcarry x y c) => (ADD c (ADD x y)) +(Select0 (Add32carrywithcarry x y c)) => (ADD c (ADD x y)) +(Select1 (Add32carrywithcarry x y c)) => + (OR + (SGTU x xy:(ADD x y)) + (SGTU xy (ADD c xy))) + (Sub(Ptr|32|16|8) ...) => (SUB ...) (Sub(32|64)F ...) => (SUB(F|D) ...) @@ -121,7 +127,7 @@ (Neg(32|16|8) ...) => (NEG ...) (Neg(32|64)F ...) => (NEG(F|D) ...) -(Com(32|16|8) x) => (NORconst [0] x) +(Com(32|16|8) x) => (NOR (MOVWconst [0]) x) (Sqrt ...) => (SQRTD ...) (Sqrt32 ...) => (SQRTF ...) @@ -350,6 +356,7 @@ (ClosureCall ...) => (CALLclosure ...) (InterCall ...) => (CALLinter ...) (TailCall ...) => (CALLtail ...) +(TailCallInter ...) => (CALLtailinter ...) // atomic intrinsics (AtomicLoad(8|32) ...) => (LoweredAtomicLoad(8|32) ...) @@ -376,7 +383,7 @@ (OR (SLL (ZeroExt8to32 val) (SLLconst [3] (ANDconst [3] ptr))) - (NORconst [0] (SLL + (NOR (MOVWconst [0]) (SLL (MOVWconst [0xff]) (SLLconst [3] (ANDconst [3] ptr))))) mem) @@ -395,7 +402,7 @@ (SLLconst [3] (ANDconst [3] (XORconst [3] ptr)))) - (NORconst [0] (SLL + (NOR (MOVWconst [0]) (SLL (MOVWconst [0xff]) (SLLconst [3] (ANDconst [3] (XORconst [3] ptr)))))) mem) @@ -593,7 +600,6 @@ (AND x (MOVWconst [c])) => (ANDconst [c] x) (OR x (MOVWconst [c])) => (ORconst [c] x) (XOR x (MOVWconst [c])) => (XORconst [c] x) -(NOR x (MOVWconst [c])) => (NORconst [c] x) (SLL x (MOVWconst [c])) => (SLLconst x [c&31]) (SRL x (MOVWconst [c])) => (SRLconst x [c&31]) @@ -611,13 +617,13 @@ (Select0 (MULTU (MOVWconst [1]) _ )) => (MOVWconst [0]) (Select1 (MULTU (MOVWconst [-1]) x )) => (NEG x) (Select0 (MULTU (MOVWconst [-1]) x )) => (CMOVZ (ADDconst [-1] x) (MOVWconst [0]) x) -(Select1 (MULTU (MOVWconst [c]) x )) && isUnsignedPowerOfTwo(uint32(c)) => (SLLconst [int32(log32u(uint32(c)))] x) -(Select0 (MULTU (MOVWconst [c]) x )) && isUnsignedPowerOfTwo(uint32(c)) => (SRLconst [int32(32-log32u(uint32(c)))] x) +(Select1 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(uint32(c)) => (SLLconst [int32(log32u(uint32(c)))] x) +(Select0 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(uint32(c)) => (SRLconst [int32(32-log32u(uint32(c)))] x) (MUL (MOVWconst [0]) _ ) => (MOVWconst [0]) (MUL (MOVWconst [1]) x ) => x (MUL (MOVWconst [-1]) x ) => (NEG x) -(MUL (MOVWconst [c]) x ) && isUnsignedPowerOfTwo(uint32(c)) => (SLLconst [int32(log32u(uint32(c)))] x) +(MUL (MOVWconst [c]) x ) && isPowerOfTwo(uint32(c)) => (SLLconst [int32(log32u(uint32(c)))] x) // generic simplifications (ADD x (NEG y)) => (SUB x y) @@ -642,7 +648,6 @@ (ORconst [0] x) => x (ORconst [-1] _) => (MOVWconst [-1]) (XORconst [0] x) => x -(XORconst [-1] x) => (NORconst [0] x) // generic constant folding (ADDconst [c] (MOVWconst [d])) => (MOVWconst [int32(c+d)]) @@ -667,7 +672,6 @@ (ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x) (XORconst [c] (MOVWconst [d])) => (MOVWconst [c^d]) (XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x) -(NORconst [c] (MOVWconst [d])) => (MOVWconst [^(c|d)]) (NEG (MOVWconst [c])) => (MOVWconst [-c]) (MOVBreg (MOVWconst [c])) => (MOVWconst [int32(int8(c))]) (MOVBUreg (MOVWconst [c])) => (MOVWconst [int32(uint8(c))]) diff --git a/src/cmd/compile/internal/ssa/_gen/MIPS64.rules b/src/cmd/compile/internal/ssa/_gen/MIPS64.rules index da6ae942736eb6..0198874f222239 100644 --- a/src/cmd/compile/internal/ssa/_gen/MIPS64.rules +++ b/src/cmd/compile/internal/ssa/_gen/MIPS64.rules @@ -227,7 +227,8 @@ (Leq64U x y) => (XOR (MOVVconst [1]) (SGTU x y)) (OffPtr [off] ptr:(SP)) && is32Bit(off) => (MOVVaddr [int32(off)] ptr) -(OffPtr [off] ptr) => (ADDVconst [off] ptr) +(OffPtr [off] ptr) && is32Bit(off) => (ADDVconst [off] ptr) +(OffPtr [off] ptr) && !is32Bit(off) => (ADDV ptr (MOVVconst [off])) (Addr {sym} base) => (MOVVaddr {sym} base) (LocalAddr {sym} base mem) && t.Elem().HasPointers() => (MOVVaddr {sym} (SPanchored base mem)) @@ -405,6 +406,7 @@ (ClosureCall ...) => (CALLclosure ...) (InterCall ...) => (CALLinter ...) (TailCall ...) => (CALLtail ...) +(TailCallInter ...) => (CALLtailinter ...) // atomic intrinsics (AtomicLoad(8|32|64) ...) => (LoweredAtomicLoad(8|32|64) ...) @@ -433,7 +435,7 @@ (OR (SLLV (ZeroExt8to32 val) (SLLVconst [3] (ANDconst [3] ptr))) - (NORconst [0] (SLLV + (NOR (MOVVconst [0]) (SLLV (MOVVconst [0xff]) (SLLVconst [3] (ANDconst [3] ptr))))) mem) @@ -452,7 +454,7 @@ (SLLVconst [3] (ANDconst [3] (XORconst [3] ptr)))) - (NORconst [0] (SLLV + (NOR (MOVVconst [0]) (SLLV (MOVVconst [0xff]) (SLLVconst [3] (ANDconst [3] (XORconst [3] ptr)))))) mem) @@ -668,7 +670,6 @@ (AND x (MOVVconst [c])) && is32Bit(c) => (ANDconst [c] x) (OR x (MOVVconst [c])) && is32Bit(c) => (ORconst [c] x) (XOR x (MOVVconst [c])) && is32Bit(c) => (XORconst [c] x) -(NOR x (MOVVconst [c])) && is32Bit(c) => (NORconst [c] x) (SLLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0]) (SRLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0]) @@ -692,6 +693,9 @@ (Select0 (DIVVU _ (MOVVconst [1]))) => (MOVVconst [0]) // mod (Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) => (ANDconst [c-1] x) // mod +// Absorb conversion between 32 bit and 64 bit if both src and dst are 32 bit. +(MOVDF ((ABS|SQRT)D (MOVFD x))) => ((ABS|SQRT)F x) + // generic simplifications (ADDV x (NEGV y)) => (SUBV x y) (SUBV x (NEGV y)) => (ADDV x y) @@ -711,7 +715,6 @@ (ORconst [0] x) => x (ORconst [-1] _) => (MOVVconst [-1]) (XORconst [0] x) => x -(XORconst [-1] x) => (NORconst [0] x) // generic constant folding (ADDVconst [c] (MOVVconst [d])) => (MOVVconst [c+d]) @@ -734,7 +737,6 @@ (ORconst [c] (ORconst [d] x)) && is32Bit(c|d) => (ORconst [c|d] x) (XORconst [c] (MOVVconst [d])) => (MOVVconst [c^d]) (XORconst [c] (XORconst [d] x)) && is32Bit(c^d) => (XORconst [c^d] x) -(NORconst [c] (MOVVconst [d])) => (MOVVconst [^(c|d)]) (NEGV (MOVVconst [c])) => (MOVVconst [-c]) (MOVBreg (MOVVconst [c])) => (MOVVconst [int64(int8(c))]) (MOVBUreg (MOVVconst [c])) => (MOVVconst [int64(uint8(c))]) diff --git a/src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go b/src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go index fe3afbaabb8571..809502f33f9932 100644 --- a/src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go +++ b/src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go @@ -114,10 +114,10 @@ func init() { num[name] = i } buildReg := func(s string) regMask { - m := regMask(0) + m := regMask{} for _, r := range strings.Split(s, " ") { if n, ok := num[r]; ok { - m |= regMask(1) << uint(n) + m = m.addReg(uint(n)) continue } panic("register " + r + " not found") @@ -128,31 +128,36 @@ func init() { // Common individual register masks var ( gp = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31") - gpg = gp | buildReg("g") - gpsp = gp | buildReg("SP") - gpspg = gpg | buildReg("SP") - gpspsbg = gpspg | buildReg("SB") + gpg = gp.union(buildReg("g")) + gpsp = gp.union(buildReg("SP")) + gpspg = gpg.union(buildReg("SP")) + gpspsbg = gpspg.union(buildReg("SB")) fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31") lo = buildReg("LO") hi = buildReg("HI") - callerSave = gp | fp | lo | hi | buildReg("g") // runtime.setg (and anything calling it) may clobber g + callerSave = gp.union(fp).union(lo).union(hi).union(buildReg("g")) // runtime.setg (and anything calling it) may clobber g first16 = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16") rz = buildReg("ZERO") ) // Common regInfo var ( - gp01 = regInfo{inputs: nil, outputs: []regMask{gp}} - gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}} - gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}} - gp21 = regInfo{inputs: []regMask{gpg, gpg | rz}, outputs: []regMask{gp}} - gp2hilo = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{hi, lo}} - gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}} - gpstore = regInfo{inputs: []regMask{gpspsbg, gpg | rz}} - gpstore0 = regInfo{inputs: []regMask{gpspsbg}} - gpxchg = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}} - gpcas = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{gp}} - fp01 = regInfo{inputs: nil, outputs: []regMask{fp}} - fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}} + gp01 = regInfo{inputs: nil, outputs: []regMask{gp}} + gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}} + gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}} + gp21 = regInfo{inputs: []regMask{gpg, gpg.union(rz)}, outputs: []regMask{gp}} + // Multiply/divide move their results out of HI/LO into general + // registers as part of the op itself: a value living in HI/LO + // cannot be spilled, as spilling needs REGTMP as the data + // register, which collides with REGTMP-based address + // materialization when the frame is too large for 16-bit offsets. + gp22clobbershilo = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp, gp}, clobbers: hi.union(lo)} + gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}} + gpstore = regInfo{inputs: []regMask{gpspsbg, gpg.union(rz)}} + gpstore0 = regInfo{inputs: []regMask{gpspsbg}} + gpxchg = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}} + gpcas = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{gp}} + fp01 = regInfo{inputs: nil, outputs: []regMask{fp}} + fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}} //fp1flags = regInfo{inputs: []regMask{fp}} fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}} gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}} @@ -164,53 +169,53 @@ func init() { ) ops := []opData{ // binary ops - {name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true}, // arg0 + arg1 - {name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops. - {name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"}, // arg0 - arg1 - {name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64"}, // arg0 - auxInt - {name: "MULV", argLength: 2, reg: gp2hilo, asm: "MULV", commutative: true, typ: "(Int64,Int64)"}, // arg0 * arg1, signed, results hi,lo - {name: "MULVU", argLength: 2, reg: gp2hilo, asm: "MULVU", commutative: true, typ: "(UInt64,UInt64)"}, // arg0 * arg1, unsigned, results hi,lo - {name: "DIVV", argLength: 2, reg: gp2hilo, asm: "DIVV", typ: "(Int64,Int64)"}, // arg0 / arg1, signed, results hi=arg0%arg1,lo=arg0/arg1 - {name: "DIVVU", argLength: 2, reg: gp2hilo, asm: "DIVVU", typ: "(UInt64,UInt64)"}, // arg0 / arg1, signed, results hi=arg0%arg1,lo=arg0/arg1 - - {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1 - {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true}, // arg0 + arg1 - {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF"}, // arg0 - arg1 - {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"}, // arg0 - arg1 - {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1 - {name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1 - {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1 - {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1 - - {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1 - {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64"}, // arg0 & auxInt - {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0 | arg1 - {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"}, // arg0 | auxInt - {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, typ: "UInt64"}, // arg0 ^ arg1 - {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", typ: "UInt64"}, // arg0 ^ auxInt - {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true}, // ^(arg0 | arg1) - {name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int64"}, // ^(arg0 | auxInt) - - {name: "NEGV", argLength: 1, reg: gp11}, // -arg0 - {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32 - {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 - {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64 - {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64 - {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 + {name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64", earlyOk: true}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops. + {name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU", earlyOk: true}, // arg0 - arg1 + {name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64", earlyOk: true}, // arg0 - auxInt + {name: "MULV", argLength: 2, reg: gp22clobbershilo, asm: "MULV", commutative: true, typ: "(Int64,Int64)", earlyOk: true}, // arg0 * arg1, signed, results high,low + {name: "MULVU", argLength: 2, reg: gp22clobbershilo, asm: "MULVU", commutative: true, typ: "(UInt64,UInt64)", earlyOk: true}, // arg0 * arg1, unsigned, results high,low + {name: "DIVV", argLength: 2, reg: gp22clobbershilo, asm: "DIVV", typ: "(Int64,Int64)"}, // arg0 / arg1, signed, results arg0%arg1,arg0/arg1 + {name: "DIVVU", argLength: 2, reg: gp22clobbershilo, asm: "DIVVU", typ: "(UInt64,UInt64)"}, // arg0 / arg1, unsigned, results arg0%arg1,arg0/arg1 + + {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF", earlyOk: true}, // arg0 - arg1 + {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD", earlyOk: true}, // arg0 - arg1 + {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF", earlyOk: true}, // arg0 / arg1 + {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD", earlyOk: true}, // arg0 / arg1 + + {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64", earlyOk: true}, // arg0 & auxInt + {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true, earlyOk: true}, // arg0 | arg1 + {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64", earlyOk: true}, // arg0 | auxInt + {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, typ: "UInt64", earlyOk: true}, // arg0 ^ arg1 + {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", typ: "UInt64", earlyOk: true}, // arg0 ^ auxInt + {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true, earlyOk: true}, // ^(arg0 | arg1) + + {name: "NEGV", argLength: 1, reg: gp11, earlyOk: true}, // -arg0 + {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF", earlyOk: true}, // -arg0, float32 + {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD", earlyOk: true}, // -arg0, float64 + {name: "ABSF", argLength: 1, reg: fp11, asm: "ABSF", earlyOk: true}, // abs(arg0), float32 + {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD", earlyOk: true}, // abs(arg0), float64 + {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD", earlyOk: true}, // sqrt(arg0), float64 + {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF", earlyOk: true}, // sqrt(arg0), float32 // shifts - {name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV"}, // arg0 << arg1, shift amount is mod 64 - {name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64"}, // arg0 << auxInt - {name: "SRLV", argLength: 2, reg: gp21, asm: "SRLV"}, // arg0 >> arg1, unsigned, shift amount is mod 64 - {name: "SRLVconst", argLength: 1, reg: gp11, asm: "SRLV", aux: "Int64"}, // arg0 >> auxInt, unsigned - {name: "SRAV", argLength: 2, reg: gp21, asm: "SRAV"}, // arg0 >> arg1, signed, shift amount is mod 64 - {name: "SRAVconst", argLength: 1, reg: gp11, asm: "SRAV", aux: "Int64"}, // arg0 >> auxInt, signed + {name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV", earlyOk: true}, // arg0 << arg1, shift amount is mod 64 + {name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64", earlyOk: true}, // arg0 << auxInt + {name: "SRLV", argLength: 2, reg: gp21, asm: "SRLV", earlyOk: true}, // arg0 >> arg1, unsigned, shift amount is mod 64 + {name: "SRLVconst", argLength: 1, reg: gp11, asm: "SRLV", aux: "Int64", earlyOk: true}, // arg0 >> auxInt, unsigned + {name: "SRAV", argLength: 2, reg: gp21, asm: "SRAV", earlyOk: true}, // arg0 >> arg1, signed, shift amount is mod 64 + {name: "SRAVconst", argLength: 1, reg: gp11, asm: "SRAV", aux: "Int64", earlyOk: true}, // arg0 >> auxInt, signed // comparisons - {name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool"}, // 1 if arg0 > arg1 (signed), 0 otherwise - {name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (signed), 0 otherwise - {name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"}, // 1 if arg0 > arg1 (unsigned), 0 otherwise - {name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (unsigned), 0 otherwise + {name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool", earlyOk: true}, // 1 if arg0 > arg1 (signed), 0 otherwise + {name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int64", typ: "Bool", earlyOk: true}, // 1 if auxInt > arg0 (signed), 0 otherwise + {name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool", earlyOk: true}, // 1 if arg0 > arg1 (unsigned), 0 otherwise + {name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int64", typ: "Bool", earlyOk: true}, // 1 if auxInt > arg0 (unsigned), 0 otherwise {name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32 {name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64 @@ -220,64 +225,65 @@ func init() { {name: "CMPGTD", argLength: 2, reg: fp2flags, asm: "CMPGTD", typ: "Flags"}, // flags=true if arg0 > arg1, float64 // moves - {name: "MOVVconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVV", typ: "UInt64", rematerializeable: true}, // auxint - {name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVF", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float - {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true}, // auxint as 64-bit float - - {name: "MOVVaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP") | buildReg("SB")}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVV", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB - - {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVWUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVWU", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVVload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVV", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - - {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVVstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - - {name: "ZERO", zeroWidth: true, fixedReg: true}, + {name: "MOVVconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVV", typ: "UInt64", rematerializeable: true, earlyOk: true}, // auxint + {name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVF", typ: "Float32", rematerializeable: true, earlyOk: true}, // auxint as 64-bit float, convert to 32-bit float + {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true, earlyOk: true}, // auxint as 64-bit float + + {name: "MOVVaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP").union(buildReg("SB"))}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVV", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB + + {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "Int32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVWUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVWU", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVVload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVV", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + + {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVVstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + + {name: "ZERO", zeroWidth: true, fixedReg: true, earlyOk: true}, // moves (no conversion) - {name: "MOVWfpgp", argLength: 1, reg: fpgp, asm: "MOVW"}, // move float32 to int32 (no conversion). MIPS64 will perform sign-extend to 64-bit by default - {name: "MOVWgpfp", argLength: 1, reg: gpfp, asm: "MOVW"}, // move int32 to float32 (no conversion). MIPS64 will perform sign-extend to 64-bit by default - {name: "MOVVfpgp", argLength: 1, reg: fpgp, asm: "MOVV"}, // move float64 to int64 (no conversion). - {name: "MOVVgpfp", argLength: 1, reg: gpfp, asm: "MOVV"}, // move int64 to float64 (no conversion). + {name: "MOVWfpgp", argLength: 1, reg: fpgp, asm: "MOVW", earlyOk: true}, // move float32 to int32 (no conversion). MIPS64 will perform sign-extend to 64-bit by default + {name: "MOVWgpfp", argLength: 1, reg: gpfp, asm: "MOVW", earlyOk: true}, // move int32 to float32 (no conversion). MIPS64 will perform sign-extend to 64-bit by default + {name: "MOVVfpgp", argLength: 1, reg: fpgp, asm: "MOVV", earlyOk: true}, // move float64 to int64 (no conversion). + {name: "MOVVgpfp", argLength: 1, reg: gpfp, asm: "MOVV", earlyOk: true}, // move int64 to float64 (no conversion). // conversions - {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte - {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte - {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"}, // move from arg0, sign-extended from half - {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half - {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"}, // move from arg0, sign-extended from word - {name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU"}, // move from arg0, unsign-extended from word - {name: "MOVVreg", argLength: 1, reg: gp11, asm: "MOVV"}, // move from arg0 - - {name: "MOVVnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true}, // nop, return arg0 in same register - - {name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF"}, // int32 -> float32 - {name: "MOVWD", argLength: 1, reg: fp11, asm: "MOVWD"}, // int32 -> float64 - {name: "MOVVF", argLength: 1, reg: fp11, asm: "MOVVF"}, // int64 -> float32 - {name: "MOVVD", argLength: 1, reg: fp11, asm: "MOVVD"}, // int64 -> float64 - {name: "TRUNCFW", argLength: 1, reg: fp11, asm: "TRUNCFW"}, // float32 -> int32 - {name: "TRUNCDW", argLength: 1, reg: fp11, asm: "TRUNCDW"}, // float64 -> int32 - {name: "TRUNCFV", argLength: 1, reg: fp11, asm: "TRUNCFV"}, // float32 -> int64 - {name: "TRUNCDV", argLength: 1, reg: fp11, asm: "TRUNCDV"}, // float64 -> int64 - {name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD"}, // float32 -> float64 - {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF"}, // float64 -> float32 + {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB", earlyOk: true}, // move from arg0, sign-extended from byte + {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU", earlyOk: true}, // move from arg0, unsign-extended from byte + {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH", earlyOk: true}, // move from arg0, sign-extended from half + {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU", earlyOk: true}, // move from arg0, unsign-extended from half + {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW", earlyOk: true}, // move from arg0, sign-extended from word + {name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU", earlyOk: true}, // move from arg0, unsign-extended from word + {name: "MOVVreg", argLength: 1, reg: gp11, asm: "MOVV", earlyOk: true}, // move from arg0 + + {name: "MOVVnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true, earlyOk: true}, // nop, return arg0 in same register + + {name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF", earlyOk: true}, // int32 -> float32 + {name: "MOVWD", argLength: 1, reg: fp11, asm: "MOVWD", earlyOk: true}, // int32 -> float64 + {name: "MOVVF", argLength: 1, reg: fp11, asm: "MOVVF", earlyOk: true}, // int64 -> float32 + {name: "MOVVD", argLength: 1, reg: fp11, asm: "MOVVD", earlyOk: true}, // int64 -> float64 + {name: "TRUNCFW", argLength: 1, reg: fp11, asm: "TRUNCFW", earlyOk: true}, // float32 -> int32 + {name: "TRUNCDW", argLength: 1, reg: fp11, asm: "TRUNCDW", earlyOk: true}, // float64 -> int32 + {name: "TRUNCFV", argLength: 1, reg: fp11, asm: "TRUNCFV", earlyOk: true}, // float32 -> int64 + {name: "TRUNCDV", argLength: 1, reg: fp11, asm: "TRUNCDV", earlyOk: true}, // float64 -> int64 + {name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD", earlyOk: true}, // float32 -> float64 + {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF", earlyOk: true}, // float64 -> float32 // function calls - {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R22"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem - {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem + {name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem + {name: "CALLtailinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R22"), regMask{}}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem // duffzero // arg0 = address of memory to zero @@ -294,6 +300,7 @@ func init() { clobbers: buildReg("R1 R31"), }, faultOnNilArg0: true, + addrSinkArg0: true, }, // duffcopy @@ -312,6 +319,8 @@ func init() { }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // large or unaligned zeroing @@ -334,6 +343,8 @@ func init() { }, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // large or unaligned move @@ -360,6 +371,9 @@ func init() { clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + // TODO: could use addrSinkArg2 here. }, // atomic and/or. @@ -437,8 +451,8 @@ func init() { // pseudo-ops {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil. arg1=mem. - {name: "FPFlagTrue", argLength: 1, reg: readflags}, // bool, true if FP flag is true - {name: "FPFlagFalse", argLength: 1, reg: readflags}, // bool, true if FP flag is false + {name: "FPFlagTrue", argLength: 1, reg: readflags, earlyOk: true}, // bool, true if FP flag is true + {name: "FPFlagFalse", argLength: 1, reg: readflags, earlyOk: true}, // bool, true if FP flag is false // Scheduler ensures LoweredGetClosurePtr occurs only in entry block, // and sorts it to the very beginning of the block to prevent other @@ -459,7 +473,7 @@ func init() { // but clobbers R31 (LR) because it's a call // and R23 (REGTMP). // Returns a pointer to a write barrier buffer in R25. - {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ gpg) | buildReg("R31"), outputs: []regMask{buildReg("R25")}}, clobberFlags: true, aux: "Int64"}, + {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave.minus(gpg).union(buildReg("R31")), outputs: []regMask{buildReg("R25")}}, clobberFlags: true, aux: "Int64"}, // Do data barrier. arg0=memorys {name: "LoweredPubBarrier", argLength: 1, asm: "SYNC", hasSideEffects: true}, @@ -495,7 +509,7 @@ func init() { regnames: regNamesMIPS64, gpregmask: gp, fpregmask: fp, - specialregmask: hi | lo, + specialregmask: hi.union(lo), framepointerreg: -1, // not used linkreg: int8(num["R31"]), }) diff --git a/src/cmd/compile/internal/ssa/_gen/MIPSOps.go b/src/cmd/compile/internal/ssa/_gen/MIPSOps.go index a340775c07468e..0048210d16f5bc 100644 --- a/src/cmd/compile/internal/ssa/_gen/MIPSOps.go +++ b/src/cmd/compile/internal/ssa/_gen/MIPSOps.go @@ -98,10 +98,10 @@ func init() { num[name] = i } buildReg := func(s string) regMask { - m := regMask(0) + m := regMask{} for _, r := range strings.Split(s, " ") { if n, ok := num[r]; ok { - m |= regMask(1) << uint(n) + m = m.addReg(uint(n)) continue } panic("register " + r + " not found") @@ -112,93 +112,93 @@ func init() { // Common individual register masks var ( gp = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31") - gpg = gp | buildReg("g") - gpsp = gp | buildReg("SP") - gpspg = gpg | buildReg("SP") - gpspsbg = gpspg | buildReg("SB") + gpg = gp.union(buildReg("g")) + gpsp = gp.union(buildReg("SP")) + gpspg = gpg.union(buildReg("SP")) + gpspsbg = gpspg.union(buildReg("SB")) fp = buildReg("F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30") lo = buildReg("LO") hi = buildReg("HI") - callerSave = gp | fp | lo | hi | buildReg("g") // runtime.setg (and anything calling it) may clobber g + callerSave = gp.union(fp).union(lo).union(hi).union(buildReg("g")) // runtime.setg (and anything calling it) may clobber g first16 = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16") first4 = buildReg("R1 R2 R3 R4") ) // Common regInfo var ( - gp01 = regInfo{inputs: nil, outputs: []regMask{gp}} - gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}} - gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}} - gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}} - gp31 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}} - gp2hilo = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{hi, lo}} - gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}} - gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}} - gpxchg = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}} - gpcas = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{gp}} - gpstore0 = regInfo{inputs: []regMask{gpspsbg}} - fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}} - gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}} - fp01 = regInfo{inputs: nil, outputs: []regMask{fp}} - fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}} - fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}} - fp2flags = regInfo{inputs: []regMask{fp, fp}} - fpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{fp}} - fpstore = regInfo{inputs: []regMask{gpspsbg, fp}} - readflags = regInfo{inputs: nil, outputs: []regMask{gp}} + gp01 = regInfo{inputs: nil, outputs: []regMask{gp}} + gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}} + gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}} + gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}} + gp31 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}} + // See MIPS64Ops.go: results must not stay homed in HI/LO. + gp22clobbershilo = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp, gp}, clobbers: hi.union(lo)} + gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}} + gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}} + gpxchg = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}} + gpcas = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{gp}} + gpstore0 = regInfo{inputs: []regMask{gpspsbg}} + fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}} + gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}} + fp01 = regInfo{inputs: nil, outputs: []regMask{fp}} + fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}} + fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}} + fp2flags = regInfo{inputs: []regMask{fp, fp}} + fpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{fp}} + fpstore = regInfo{inputs: []regMask{gpspsbg, fp}} + readflags = regInfo{inputs: nil, outputs: []regMask{gp}} ) ops := []opData{ - {name: "ADD", argLength: 2, reg: gp21, asm: "ADDU", commutative: true}, // arg0 + arg1 - {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADDU", aux: "Int32"}, // arg0 + auxInt - {name: "SUB", argLength: 2, reg: gp21, asm: "SUBU"}, // arg0 - arg1 - {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUBU", aux: "Int32"}, // arg0 - auxInt - {name: "MUL", argLength: 2, reg: regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}, clobbers: hi | lo}, asm: "MUL", commutative: true}, // arg0 * arg1 - {name: "MULT", argLength: 2, reg: gp2hilo, asm: "MUL", commutative: true, typ: "(Int32,Int32)"}, // arg0 * arg1, signed, results hi,lo - {name: "MULTU", argLength: 2, reg: gp2hilo, asm: "MULU", commutative: true, typ: "(UInt32,UInt32)"}, // arg0 * arg1, unsigned, results hi,lo - {name: "DIV", argLength: 2, reg: gp2hilo, asm: "DIV", typ: "(Int32,Int32)"}, // arg0 / arg1, signed, results hi=arg0%arg1,lo=arg0/arg1 - {name: "DIVU", argLength: 2, reg: gp2hilo, asm: "DIVU", typ: "(UInt32,UInt32)"}, // arg0 / arg1, signed, results hi=arg0%arg1,lo=arg0/arg1 - - {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1 - {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true}, // arg0 + arg1 - {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF"}, // arg0 - arg1 - {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"}, // arg0 - arg1 - {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1 - {name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1 - {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1 - {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1 - - {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1 - {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int32"}, // arg0 & auxInt - {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0 | arg1 - {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int32"}, // arg0 | auxInt - {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, typ: "UInt32"}, // arg0 ^ arg1 - {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int32", typ: "UInt32"}, // arg0 ^ auxInt - {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true}, // ^(arg0 | arg1) - {name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int32"}, // ^(arg0 | auxInt) - - {name: "NEG", argLength: 1, reg: gp11}, // -arg0 - {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32 - {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 - {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64 - {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64 - {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 + {name: "ADD", argLength: 2, reg: gp21, asm: "ADDU", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADDU", aux: "Int32", earlyOk: true}, // arg0 + auxInt + {name: "SUB", argLength: 2, reg: gp21, asm: "SUBU", earlyOk: true}, // arg0 - arg1 + {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUBU", aux: "Int32", earlyOk: true}, // arg0 - auxInt + {name: "MUL", argLength: 2, reg: regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}, clobbers: hi.union(lo)}, asm: "MUL", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "MULT", argLength: 2, reg: gp22clobbershilo, asm: "MUL", commutative: true, typ: "(Int32,Int32)", earlyOk: true}, // arg0 * arg1, signed, results high,low + {name: "MULTU", argLength: 2, reg: gp22clobbershilo, asm: "MULU", commutative: true, typ: "(UInt32,UInt32)", earlyOk: true}, // arg0 * arg1, unsigned, results high,low + {name: "DIV", argLength: 2, reg: gp22clobbershilo, asm: "DIV", typ: "(Int32,Int32)"}, // arg0 / arg1, signed, results arg0%arg1,arg0/arg1 + {name: "DIVU", argLength: 2, reg: gp22clobbershilo, asm: "DIVU", typ: "(UInt32,UInt32)"}, // arg0 / arg1, signed, results arg0%arg1,arg0/arg1 + + {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF", earlyOk: true}, // arg0 - arg1 + {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD", earlyOk: true}, // arg0 - arg1 + {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true, earlyOk: true}, // arg0 * arg1 + {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF", earlyOk: true}, // arg0 / arg1 + {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD", earlyOk: true}, // arg0 / arg1 + + {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int32", earlyOk: true}, // arg0 & auxInt + {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true, earlyOk: true}, // arg0 | arg1 + {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int32", earlyOk: true}, // arg0 | auxInt + {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, typ: "UInt32", earlyOk: true}, // arg0 ^ arg1 + {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int32", typ: "UInt32", earlyOk: true}, // arg0 ^ auxInt + {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true, earlyOk: true}, // ^(arg0 | arg1) + + {name: "NEG", argLength: 1, reg: gp11, earlyOk: true}, // -arg0 + {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF", earlyOk: true}, // -arg0, float32 + {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD", earlyOk: true}, // -arg0, float64 + {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD", earlyOk: true}, // abs(arg0), float64 + {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD", earlyOk: true}, // sqrt(arg0), float64 + {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF", earlyOk: true}, // sqrt(arg0), float32 // shifts - {name: "SLL", argLength: 2, reg: gp21, asm: "SLL"}, // arg0 << arg1, shift amount is mod 32 - {name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt, shift amount must be 0 through 31 inclusive - {name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> arg1, unsigned, shift amount is mod 32 - {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, shift amount must be 0 through 31 inclusive - {name: "SRA", argLength: 2, reg: gp21, asm: "SRA"}, // arg0 >> arg1, signed, shift amount is mod 32 - {name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int32"}, // arg0 >> auxInt, signed, shift amount must be 0 through 31 inclusive + {name: "SLL", argLength: 2, reg: gp21, asm: "SLL", earlyOk: true}, // arg0 << arg1, shift amount is mod 32 + {name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32", earlyOk: true}, // arg0 << auxInt, shift amount must be 0 through 31 inclusive + {name: "SRL", argLength: 2, reg: gp21, asm: "SRL", earlyOk: true}, // arg0 >> arg1, unsigned, shift amount is mod 32 + {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32", earlyOk: true}, // arg0 >> auxInt, shift amount must be 0 through 31 inclusive + {name: "SRA", argLength: 2, reg: gp21, asm: "SRA", earlyOk: true}, // arg0 >> arg1, signed, shift amount is mod 32 + {name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int32", earlyOk: true}, // arg0 >> auxInt, signed, shift amount must be 0 through 31 inclusive - {name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ"}, + {name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ", earlyOk: true}, // comparisons - {name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool"}, // 1 if arg0 > arg1 (signed), 0 otherwise - {name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int32", typ: "Bool"}, // 1 if auxInt > arg0 (signed), 0 otherwise - {name: "SGTzero", argLength: 1, reg: gp11, asm: "SGT", typ: "Bool"}, // 1 if arg0 > 0 (signed), 0 otherwise - {name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"}, // 1 if arg0 > arg1 (unsigned), 0 otherwise - {name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int32", typ: "Bool"}, // 1 if auxInt > arg0 (unsigned), 0 otherwise - {name: "SGTUzero", argLength: 1, reg: gp11, asm: "SGTU", typ: "Bool"}, // 1 if arg0 > 0 (unsigned), 0 otherwise + {name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool", earlyOk: true}, // 1 if arg0 > arg1 (signed), 0 otherwise + {name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int32", typ: "Bool", earlyOk: true}, // 1 if auxInt > arg0 (signed), 0 otherwise + {name: "SGTzero", argLength: 1, reg: gp11, asm: "SGT", typ: "Bool", earlyOk: true}, // 1 if arg0 > 0 (signed), 0 otherwise + {name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool", earlyOk: true}, // 1 if arg0 > arg1 (unsigned), 0 otherwise + {name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int32", typ: "Bool", earlyOk: true}, // 1 if auxInt > arg0 (unsigned), 0 otherwise + {name: "SGTUzero", argLength: 1, reg: gp11, asm: "SGTU", typ: "Bool", earlyOk: true}, // 1 if arg0 > 0 (unsigned), 0 otherwise {name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32 {name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64 @@ -208,60 +208,61 @@ func init() { {name: "CMPGTD", argLength: 2, reg: fp2flags, asm: "CMPGTD", typ: "Flags"}, // flags=true if arg0 > arg1, float64 // moves - {name: "MOVWconst", argLength: 0, reg: gp01, aux: "Int32", asm: "MOVW", typ: "UInt32", rematerializeable: true}, // auxint - {name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float32", asm: "MOVF", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float - {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true}, // auxint as 64-bit float - - {name: "MOVWaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP") | buildReg("SB")}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVW", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB - - {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - {name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem. - - {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. - - {name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of zero to arg0 + auxInt + aux. arg1=mem. - {name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of zero to arg0 + auxInt + aux. arg1=mem. - {name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of zero to arg0 + auxInt + aux. arg1=mem. + {name: "MOVWconst", argLength: 0, reg: gp01, aux: "Int32", asm: "MOVW", typ: "UInt32", rematerializeable: true, earlyOk: true}, // auxint + {name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float32", asm: "MOVF", typ: "Float32", rematerializeable: true, earlyOk: true}, // auxint as 64-bit float, convert to 32-bit float + {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true, earlyOk: true}, // auxint as 64-bit float + + {name: "MOVWaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP").union(buildReg("SB"))}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVW", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB + + {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + {name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load from arg0 + auxInt + aux. arg1=mem. + + {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem. + + {name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 1 byte of zero to arg0 + auxInt + aux. arg1=mem. + {name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 2 bytes of zero to arg0 + auxInt + aux. arg1=mem. + {name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes of zero to arg0 + auxInt + aux. arg1=mem. // moves (no conversion) - {name: "MOVWfpgp", argLength: 1, reg: fpgp, asm: "MOVW"}, // move float32 to int32 (no conversion) - {name: "MOVWgpfp", argLength: 1, reg: gpfp, asm: "MOVW"}, // move int32 to float32 (no conversion) + {name: "MOVWfpgp", argLength: 1, reg: fpgp, asm: "MOVW", earlyOk: true}, // move float32 to int32 (no conversion) + {name: "MOVWgpfp", argLength: 1, reg: gpfp, asm: "MOVW", earlyOk: true}, // move int32 to float32 (no conversion) // conversions - {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte - {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte - {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"}, // move from arg0, sign-extended from half - {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half - {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"}, // move from arg0 + {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB", earlyOk: true}, // move from arg0, sign-extended from byte + {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU", earlyOk: true}, // move from arg0, unsign-extended from byte + {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH", earlyOk: true}, // move from arg0, sign-extended from half + {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU", earlyOk: true}, // move from arg0, unsign-extended from half + {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW", earlyOk: true}, // move from arg0 - {name: "MOVWnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true}, // nop, return arg0 in same register + {name: "MOVWnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true, earlyOk: true}, // nop, return arg0 in same register // conditional move on zero (returns arg1 if arg2 is 0, otherwise arg0) // order of parameters is reversed so we can use resultInArg0 (OpCMOVZ result arg1 arg2-> CMOVZ arg2reg, arg1reg, resultReg) - {name: "CMOVZ", argLength: 3, reg: gp31, asm: "CMOVZ", resultInArg0: true}, - {name: "CMOVZzero", argLength: 2, reg: regInfo{inputs: []regMask{gp, gpg}, outputs: []regMask{gp}}, asm: "CMOVZ", resultInArg0: true}, + {name: "CMOVZ", argLength: 3, reg: gp31, asm: "CMOVZ", resultInArg0: true, earlyOk: true}, + {name: "CMOVZzero", argLength: 2, reg: regInfo{inputs: []regMask{gp, gpg}, outputs: []regMask{gp}}, asm: "CMOVZ", resultInArg0: true, earlyOk: true}, - {name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF"}, // int32 -> float32 - {name: "MOVWD", argLength: 1, reg: fp11, asm: "MOVWD"}, // int32 -> float64 - {name: "TRUNCFW", argLength: 1, reg: fp11, asm: "TRUNCFW"}, // float32 -> int32 - {name: "TRUNCDW", argLength: 1, reg: fp11, asm: "TRUNCDW"}, // float64 -> int32 - {name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD"}, // float32 -> float64 - {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF"}, // float64 -> float32 + {name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF", earlyOk: true}, // int32 -> float32 + {name: "MOVWD", argLength: 1, reg: fp11, asm: "MOVWD", earlyOk: true}, // int32 -> float64 + {name: "TRUNCFW", argLength: 1, reg: fp11, asm: "TRUNCFW", earlyOk: true}, // float32 -> int32 + {name: "TRUNCDW", argLength: 1, reg: fp11, asm: "TRUNCDW", earlyOk: true}, // float64 -> int32 + {name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD", earlyOk: true}, // float32 -> float64 + {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF", earlyOk: true}, // float64 -> float32 // function calls - {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R22"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem - {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem + {name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem + {name: "CALLtailinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call fn by pointer. arg0=cpdeptr, arg1=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R22"), regMask{}}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem // atomic ops @@ -351,6 +352,8 @@ func init() { clobbers: buildReg("R1"), }, faultOnNilArg0: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // large or unaligned move @@ -376,13 +379,16 @@ func init() { }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + // TODO: could use addrSinkArg2 here. }, // pseudo-ops {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil. arg1=mem. - {name: "FPFlagTrue", argLength: 1, reg: readflags}, // bool, true if FP flag is true - {name: "FPFlagFalse", argLength: 1, reg: readflags}, // bool, true if FP flag is false + {name: "FPFlagTrue", argLength: 1, reg: readflags, earlyOk: true}, // bool, true if FP flag is true + {name: "FPFlagFalse", argLength: 1, reg: readflags, earlyOk: true}, // bool, true if FP flag is false // Scheduler ensures LoweredGetClosurePtr occurs only in entry block, // and sorts it to the very beginning of the block to prevent other @@ -403,7 +409,7 @@ func init() { // but clobbers R31 (LR) because it's a call // and R23 (REGTMP). // Returns a pointer to a write barrier buffer in R25. - {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ gpg) | buildReg("R31"), outputs: []regMask{buildReg("R25")}}, clobberFlags: true, aux: "Int64"}, + {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave.minus(gpg).union(buildReg("R31")), outputs: []regMask{buildReg("R25")}}, clobberFlags: true, aux: "Int64"}, // Do data barrier. arg0=memorys {name: "LoweredPubBarrier", argLength: 1, asm: "SYNC", hasSideEffects: true}, @@ -443,7 +449,7 @@ func init() { regnames: regNamesMIPS, gpregmask: gp, fpregmask: fp, - specialregmask: hi | lo, + specialregmask: hi.union(lo), framepointerreg: -1, // not used linkreg: int8(num["R31"]), }) diff --git a/src/cmd/compile/internal/ssa/_gen/PPC64.rules b/src/cmd/compile/internal/ssa/_gen/PPC64.rules index f5e381ac413fcf..0872648bf7ba27 100644 --- a/src/cmd/compile/internal/ssa/_gen/PPC64.rules +++ b/src/cmd/compile/internal/ssa/_gen/PPC64.rules @@ -18,7 +18,10 @@ (Max(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMAXJDP x y) // Combine 64 bit integer multiply and adds -(ADD l:(MULLD x y) z) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD x y z) +(ADD z l:(MULLD x y)) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD x y z ) +(ADD z l:(MULLDconst [x] y)) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD (MOVDconst [int64(x)]) y z ) +(ADDconst [z] l:(MULLD x y)) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD x y (MOVDconst [int64(z)])) +(ADDconst [z] l:(MULLDconst [x] y)) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD (MOVDconst [int64(x)]) y (MOVDconst [int64(z)])) (Mod16 x y) => (Mod32 (SignExt16to32 x) (SignExt16to32 y)) (Mod16u x y) => (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y)) @@ -139,6 +142,16 @@ (ROTLW x (MOVDconst [c])) => (ROTLWconst x [c&31]) (ROTL x (MOVDconst [c])) => (ROTLconst x [c&63]) +// uint8: logical ops with constant -> UI immediates (only if truncation needed). +(AND x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m)) => (ANDconst [int64(uint8(m))] x) +(OR x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m)) => (ORconst [int64(uint8(m))] x) +(XOR x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m)) => (XORconst [int64(uint8(m))] x) + +// uint16: logical ops with constant -> UI immediates (only if truncation needed). +(AND x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m)) => (ANDconst [int64(uint16(m))] x) +(OR x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m)) => (ORconst [int64(uint16(m))] x) +(XOR x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m)) => (XORconst [int64(uint16(m))] x) + // Combine rotate and mask operations (ANDconst [m] (ROTLWconst [r] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,m,32)] x) (AND (MOVDconst [m]) (ROTLWconst [r] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,m,32)] x) @@ -537,6 +550,7 @@ (ClosureCall ...) => (CALLclosure ...) (InterCall ...) => (CALLinter ...) (TailCall ...) => (CALLtail ...) +(TailCallInter ...) => (CALLtailinter ...) // Miscellaneous (GetClosurePtr ...) => (LoweredGetClosurePtr ...) @@ -865,10 +879,14 @@ (SLDconst [c] z:(ANDconst [d] x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c <= (64-getPPC64ShiftMaskLength(d)) => (CLRLSLDI [newPPC64ShiftAuxInt(c,64-getPPC64ShiftMaskLength(d),63,64)] x) (SLDconst [c] z:(AND (MOVDconst [d]) x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(64-getPPC64ShiftMaskLength(d)) => (CLRLSLDI [newPPC64ShiftAuxInt(c,64-getPPC64ShiftMaskLength(d),63,64)] x) +// (x + x) << c → x << (c+1) +(SLDconst [c] (ADD x x)) && c < 63 => (SLDconst [c+1] x) (SLWconst [c] z:(MOVBZreg x)) && z.Uses == 1 && c < 8 => (CLRLSLWI [newPPC64ShiftAuxInt(c,24,31,32)] x) (SLWconst [c] z:(MOVHZreg x)) && z.Uses == 1 && c < 16 => (CLRLSLWI [newPPC64ShiftAuxInt(c,16,31,32)] x) (SLWconst [c] z:(ANDconst [d] x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(32-getPPC64ShiftMaskLength(d)) => (CLRLSLWI [newPPC64ShiftAuxInt(c,32-getPPC64ShiftMaskLength(d),31,32)] x) (SLWconst [c] z:(AND (MOVDconst [d]) x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(32-getPPC64ShiftMaskLength(d)) => (CLRLSLWI [newPPC64ShiftAuxInt(c,32-getPPC64ShiftMaskLength(d),31,32)] x) +// (x + x) << c → x << (c+1) +(SLWconst [c] (ADD x x)) && c < 31 => (SLWconst [c+1] x) // special case for power9 (SL(W|D)const [c] z:(MOVWreg x)) && c < 32 && buildcfg.GOPPC64 >= 9 => (EXTSWSLconst [c] x) diff --git a/src/cmd/compile/internal/ssa/_gen/PPC64Ops.go b/src/cmd/compile/internal/ssa/_gen/PPC64Ops.go index 3c06208f7e21cd..f558f58167fb2f 100644 --- a/src/cmd/compile/internal/ssa/_gen/PPC64Ops.go +++ b/src/cmd/compile/internal/ssa/_gen/PPC64Ops.go @@ -109,10 +109,10 @@ func init() { num[name] = i } buildReg := func(s string) regMask { - m := regMask(0) + m := regMask{} for _, r := range strings.Split(s, " ") { if n, ok := num[r]; ok { - m |= regMask(1) << uint(n) + m = m.addReg(uint(n)) continue } panic("register " + r + " not found") @@ -135,30 +135,30 @@ func init() { callptr = buildReg("R12") // tls = buildReg("R13") gp01 = regInfo{inputs: nil, outputs: []regMask{gp}} - gp11 = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}} + gp11 = regInfo{inputs: []regMask{gp.union(sp).union(sb)}, outputs: []regMask{gp}} xergp = regInfo{inputs: []regMask{xer}, outputs: []regMask{gp}, clobbers: xer} - gp11cxer = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}, clobbers: xer} - gp11xer = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp, xer}} - gp1xer1xer = regInfo{inputs: []regMask{gp | sp | sb, xer}, outputs: []regMask{gp, xer}, clobbers: xer} - gp21 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}} - gp21a0 = regInfo{inputs: []regMask{gp, gp | sp | sb}, outputs: []regMask{gp}} - gp21cxer = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}, clobbers: xer} - gp21xer = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp, xer}, clobbers: xer} - gp2xer1xer = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, xer}, outputs: []regMask{gp, xer}, clobbers: xer} - gp31 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}} - gp1cr = regInfo{inputs: []regMask{gp | sp | sb}} - gp2cr = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}} + gp11cxer = regInfo{inputs: []regMask{gp.union(sp).union(sb)}, outputs: []regMask{gp}, clobbers: xer} + gp11xer = regInfo{inputs: []regMask{gp.union(sp).union(sb)}, outputs: []regMask{gp, xer}} + gp1xer1xer = regInfo{inputs: []regMask{gp.union(sp).union(sb), xer}, outputs: []regMask{gp, xer}, clobbers: xer} + gp21 = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp.union(sp).union(sb)}, outputs: []regMask{gp}} + gp21a0 = regInfo{inputs: []regMask{gp, gp.union(sp).union(sb)}, outputs: []regMask{gp}} + gp21cxer = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp.union(sp).union(sb)}, outputs: []regMask{gp}, clobbers: xer} + gp21xer = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp.union(sp).union(sb)}, outputs: []regMask{gp, xer}, clobbers: xer} + gp2xer1xer = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp.union(sp).union(sb), xer}, outputs: []regMask{gp, xer}, clobbers: xer} + gp31 = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp.union(sp).union(sb), gp.union(sp).union(sb)}, outputs: []regMask{gp}} + gp1cr = regInfo{inputs: []regMask{gp.union(sp).union(sb)}} + gp2cr = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp.union(sp).union(sb)}} crgp = regInfo{inputs: nil, outputs: []regMask{gp}} crgp11 = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}} crgp21 = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}} - gpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}} - gploadidx = regInfo{inputs: []regMask{gp | sp | sb, gp}, outputs: []regMask{gp}} - prefreg = regInfo{inputs: []regMask{gp | sp | sb}} - gpstore = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}} - gpstoreidx = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, gp | sp | sb}} - gpstorezero = regInfo{inputs: []regMask{gp | sp | sb}} // ppc64.REGZERO is reserved zero value - gpxchg = regInfo{inputs: []regMask{gp | sp | sb, gp}, outputs: []regMask{gp}} - gpcas = regInfo{inputs: []regMask{gp | sp | sb, gp, gp}, outputs: []regMask{gp}} + gpload = regInfo{inputs: []regMask{gp.union(sp).union(sb)}, outputs: []regMask{gp}} + gploadidx = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp}, outputs: []regMask{gp}} + prefreg = regInfo{inputs: []regMask{gp.union(sp).union(sb)}} + gpstore = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp.union(sp).union(sb)}} + gpstoreidx = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp.union(sp).union(sb), gp.union(sp).union(sb)}} + gpstorezero = regInfo{inputs: []regMask{gp.union(sp).union(sb)}} // ppc64.REGZERO is reserved zero value + gpxchg = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp}, outputs: []regMask{gp}} + gpcas = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp, gp}, outputs: []regMask{gp}} fp01 = regInfo{inputs: nil, outputs: []regMask{fp}} fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}} fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}} @@ -166,63 +166,63 @@ func init() { fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}} fp31 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: []regMask{fp}} fp2cr = regInfo{inputs: []regMask{fp, fp}} - fpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{fp}} - fploadidx = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{fp}} - fpstore = regInfo{inputs: []regMask{gp | sp | sb, fp}} - fpstoreidx = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, fp}} - callerSave = regMask(gp | fp | gr | xer) + fpload = regInfo{inputs: []regMask{gp.union(sp).union(sb)}, outputs: []regMask{fp}} + fploadidx = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp.union(sp).union(sb)}, outputs: []regMask{fp}} + fpstore = regInfo{inputs: []regMask{gp.union(sp).union(sb), fp}} + fpstoreidx = regInfo{inputs: []regMask{gp.union(sp).union(sb), gp.union(sp).union(sb), fp}} + callerSave = regMask(gp.union(fp).union(gr).union(xer)) first7 = buildReg("R3 R4 R5 R6 R7 R8 R9") ) ops := []opData{ - {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1 + {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true, earlyOk: true}, // arg0 + arg1 {name: "ADDCC", argLength: 2, reg: gp21, asm: "ADDCC", commutative: true, typ: "(Int,Flags)"}, // arg0 + arg1 - {name: "ADDconst", argLength: 1, reg: gp11, asm: "ADD", aux: "Int64"}, // arg0 + auxInt + {name: "ADDconst", argLength: 1, reg: gp11, asm: "ADD", aux: "Int64", earlyOk: true}, // arg0 + auxInt {name: "ADDCCconst", argLength: 1, reg: gp11cxer, asm: "ADDCCC", aux: "Int64", typ: "(Int,Flags)"}, // arg0 + auxInt sets CC, clobbers XER - {name: "FADD", argLength: 2, reg: fp21, asm: "FADD", commutative: true}, // arg0+arg1 - {name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true}, // arg0+arg1 - {name: "SUB", argLength: 2, reg: gp21, asm: "SUB"}, // arg0-arg1 + {name: "FADD", argLength: 2, reg: fp21, asm: "FADD", commutative: true, earlyOk: true}, // arg0+arg1 + {name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true, earlyOk: true}, // arg0+arg1 + {name: "SUB", argLength: 2, reg: gp21, asm: "SUB", earlyOk: true}, // arg0-arg1 {name: "SUBCC", argLength: 2, reg: gp21, asm: "SUBCC", typ: "(Int,Flags)"}, // arg0-arg1 sets CC {name: "SUBFCconst", argLength: 1, reg: gp11cxer, asm: "SUBC", aux: "Int64"}, // auxInt - arg0 (carry is ignored) - {name: "FSUB", argLength: 2, reg: fp21, asm: "FSUB"}, // arg0-arg1 - {name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS"}, // arg0-arg1 + {name: "FSUB", argLength: 2, reg: fp21, asm: "FSUB", earlyOk: true}, // arg0-arg1 + {name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS", earlyOk: true}, // arg0-arg1 // Note, the FPU works with float64 in register. - {name: "XSMINJDP", argLength: 2, reg: fp21, asm: "XSMINJDP"}, // fmin(arg0,arg1) - {name: "XSMAXJDP", argLength: 2, reg: fp21, asm: "XSMAXJDP"}, // fmax(arg0,arg1) - - {name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true}, // arg0*arg1 (signed 64-bit) - {name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true}, // arg0*arg1 (signed 32-bit) - {name: "MULLDconst", argLength: 1, reg: gp11, asm: "MULLD", aux: "Int32", typ: "Int64"}, // arg0*auxInt (signed 64-bit) - {name: "MULLWconst", argLength: 1, reg: gp11, asm: "MULLW", aux: "Int32", typ: "Int64"}, // arg0*auxInt (signed 64-bit) - {name: "MADDLD", argLength: 3, reg: gp31, asm: "MADDLD", typ: "Int64"}, // (arg0*arg1)+arg2 (signed 64-bit) - - {name: "MULHD", argLength: 2, reg: gp21, asm: "MULHD", commutative: true}, // (arg0 * arg1) >> 64, signed - {name: "MULHW", argLength: 2, reg: gp21, asm: "MULHW", commutative: true}, // (arg0 * arg1) >> 32, signed - {name: "MULHDU", argLength: 2, reg: gp21, asm: "MULHDU", commutative: true}, // (arg0 * arg1) >> 64, unsigned + {name: "XSMINJDP", argLength: 2, reg: fp21, asm: "XSMINJDP", earlyOk: true}, // fmin(arg0,arg1) + {name: "XSMAXJDP", argLength: 2, reg: fp21, asm: "XSMAXJDP", earlyOk: true}, // fmax(arg0,arg1) + + {name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true, earlyOk: true}, // arg0*arg1 (signed 64-bit) + {name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true, earlyOk: true}, // arg0*arg1 (signed 32-bit) + {name: "MULLDconst", argLength: 1, reg: gp11, asm: "MULLD", aux: "Int32", typ: "Int64", earlyOk: true}, // arg0*auxInt (signed 64-bit) + {name: "MULLWconst", argLength: 1, reg: gp11, asm: "MULLW", aux: "Int32", typ: "Int64", earlyOk: true}, // arg0*auxInt (signed 64-bit) + {name: "MADDLD", argLength: 3, reg: gp31, asm: "MADDLD", typ: "Int64", earlyOk: true}, // (arg0*arg1)+arg2 (signed 64-bit) + + {name: "MULHD", argLength: 2, reg: gp21, asm: "MULHD", commutative: true, earlyOk: true}, // (arg0 * arg1) >> 64, signed + {name: "MULHW", argLength: 2, reg: gp21, asm: "MULHW", commutative: true, earlyOk: true}, // (arg0 * arg1) >> 32, signed + {name: "MULHDU", argLength: 2, reg: gp21, asm: "MULHDU", commutative: true, earlyOk: true}, // (arg0 * arg1) >> 64, unsigned {name: "MULHDUCC", argLength: 2, reg: gp21, asm: "MULHDUCC", commutative: true, typ: "(Int64,Flags)"}, // (arg0 * arg1) >> 64, unsigned, sets CC - {name: "MULHWU", argLength: 2, reg: gp21, asm: "MULHWU", commutative: true}, // (arg0 * arg1) >> 32, unsigned + {name: "MULHWU", argLength: 2, reg: gp21, asm: "MULHWU", commutative: true, earlyOk: true}, // (arg0 * arg1) >> 32, unsigned - {name: "FMUL", argLength: 2, reg: fp21, asm: "FMUL", commutative: true}, // arg0*arg1 - {name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true}, // arg0*arg1 + {name: "FMUL", argLength: 2, reg: fp21, asm: "FMUL", commutative: true, earlyOk: true}, // arg0*arg1 + {name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true, earlyOk: true}, // arg0*arg1 - {name: "FMADD", argLength: 3, reg: fp31, asm: "FMADD"}, // arg0*arg1 + arg2 - {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS"}, // arg0*arg1 + arg2 - {name: "FMSUB", argLength: 3, reg: fp31, asm: "FMSUB"}, // arg0*arg1 - arg2 - {name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS"}, // arg0*arg1 - arg2 + {name: "FMADD", argLength: 3, reg: fp31, asm: "FMADD", earlyOk: true}, // arg0*arg1 + arg2 + {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS", earlyOk: true}, // arg0*arg1 + arg2 + {name: "FMSUB", argLength: 3, reg: fp31, asm: "FMSUB", earlyOk: true}, // arg0*arg1 - arg2 + {name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS", earlyOk: true}, // arg0*arg1 - arg2 - {name: "SRAD", argLength: 2, reg: gp21cxer, asm: "SRAD"}, // signed arg0 >> (arg1&127), 64 bit width (note: 127, not 63!) - {name: "SRAW", argLength: 2, reg: gp21cxer, asm: "SRAW"}, // signed arg0 >> (arg1&63), 32 bit width - {name: "SRD", argLength: 2, reg: gp21, asm: "SRD"}, // unsigned arg0 >> (arg1&127), 64 bit width - {name: "SRW", argLength: 2, reg: gp21, asm: "SRW"}, // unsigned arg0 >> (arg1&63), 32 bit width - {name: "SLD", argLength: 2, reg: gp21, asm: "SLD"}, // arg0 << (arg1&127), 64 bit width - {name: "SLW", argLength: 2, reg: gp21, asm: "SLW"}, // arg0 << (arg1&63), 32 bit width + {name: "SRAD", argLength: 2, reg: gp21cxer, asm: "SRAD", earlyOk: true}, // signed arg0 >> (arg1&127), 64 bit width (note: 127, not 63!) + {name: "SRAW", argLength: 2, reg: gp21cxer, asm: "SRAW", earlyOk: true}, // signed arg0 >> (arg1&63), 32 bit width + {name: "SRD", argLength: 2, reg: gp21, asm: "SRD", earlyOk: true}, // unsigned arg0 >> (arg1&127), 64 bit width + {name: "SRW", argLength: 2, reg: gp21, asm: "SRW", earlyOk: true}, // unsigned arg0 >> (arg1&63), 32 bit width + {name: "SLD", argLength: 2, reg: gp21, asm: "SLD", earlyOk: true}, // arg0 << (arg1&127), 64 bit width + {name: "SLW", argLength: 2, reg: gp21, asm: "SLW", earlyOk: true}, // arg0 << (arg1&63), 32 bit width - {name: "ROTL", argLength: 2, reg: gp21, asm: "ROTL"}, // arg0 rotate left by arg1 mod 64 - {name: "ROTLW", argLength: 2, reg: gp21, asm: "ROTLW"}, // uint32(arg0) rotate left by arg1 mod 32 + {name: "ROTL", argLength: 2, reg: gp21, asm: "ROTL", earlyOk: true}, // arg0 rotate left by arg1 mod 64 + {name: "ROTLW", argLength: 2, reg: gp21, asm: "ROTLW", earlyOk: true}, // uint32(arg0) rotate left by arg1 mod 32 // The following are ops to implement the extended mnemonics for shifts as described in section C.8 of the ISA. // The constant shift values are packed into the aux int32. - {name: "CLRLSLWI", argLength: 1, reg: gp11, asm: "CLRLSLWI", aux: "Int32"}, // - {name: "CLRLSLDI", argLength: 1, reg: gp11, asm: "CLRLSLDI", aux: "Int32"}, // + {name: "CLRLSLWI", argLength: 1, reg: gp11, asm: "CLRLSLWI", aux: "Int32", earlyOk: true}, // + {name: "CLRLSLDI", argLength: 1, reg: gp11, asm: "CLRLSLDI", aux: "Int32", earlyOk: true}, // // Operations which consume or generate the CA (xer) {name: "ADDC", argLength: 2, reg: gp21xer, asm: "ADDC", commutative: true, typ: "(UInt64, UInt64)"}, // arg0 + arg1 -> out, CA @@ -232,40 +232,40 @@ func init() { {name: "ADDE", argLength: 3, reg: gp2xer1xer, asm: "ADDE", typ: "(UInt64, UInt64)", commutative: true}, // arg0 + arg1 + CA (arg2) -> out, CA {name: "ADDZE", argLength: 2, reg: gp1xer1xer, asm: "ADDZE", typ: "(UInt64, UInt64)"}, // arg0 + CA (arg1) -> out, CA {name: "SUBE", argLength: 3, reg: gp2xer1xer, asm: "SUBE", typ: "(UInt64, UInt64)"}, // arg0 - arg1 - CA (arg2) -> out, CA - {name: "ADDZEzero", argLength: 1, reg: xergp, asm: "ADDZE", typ: "UInt64"}, // CA (arg0) + $0 -> out - {name: "SUBZEzero", argLength: 1, reg: xergp, asm: "SUBZE", typ: "UInt64"}, // $0 - CA (arg0) -> out - - {name: "SRADconst", argLength: 1, reg: gp11cxer, asm: "SRAD", aux: "Int64"}, // signed arg0 >> auxInt, 0 <= auxInt < 64, 64 bit width - {name: "SRAWconst", argLength: 1, reg: gp11cxer, asm: "SRAW", aux: "Int64"}, // signed arg0 >> auxInt, 0 <= auxInt < 32, 32 bit width - {name: "SRDconst", argLength: 1, reg: gp11, asm: "SRD", aux: "Int64"}, // unsigned arg0 >> auxInt, 0 <= auxInt < 64, 64 bit width - {name: "SRWconst", argLength: 1, reg: gp11, asm: "SRW", aux: "Int64"}, // unsigned arg0 >> auxInt, 0 <= auxInt < 32, 32 bit width - {name: "SLDconst", argLength: 1, reg: gp11, asm: "SLD", aux: "Int64"}, // arg0 << auxInt, 0 <= auxInt < 64, 64 bit width - {name: "SLWconst", argLength: 1, reg: gp11, asm: "SLW", aux: "Int64"}, // arg0 << auxInt, 0 <= auxInt < 32, 32 bit width - - {name: "ROTLconst", argLength: 1, reg: gp11, asm: "ROTL", aux: "Int64"}, // arg0 rotate left by auxInt bits - {name: "ROTLWconst", argLength: 1, reg: gp11, asm: "ROTLW", aux: "Int64"}, // uint32(arg0) rotate left by auxInt bits - {name: "EXTSWSLconst", argLength: 1, reg: gp11, asm: "EXTSWSLI", aux: "Int64"}, - - {name: "RLWINM", argLength: 1, reg: gp11, asm: "RLWNM", aux: "Int64"}, // Rotate and mask by immediate "rlwinm". encodePPC64RotateMask describes aux - {name: "RLWNM", argLength: 2, reg: gp21, asm: "RLWNM", aux: "Int64"}, // Rotate and mask by "rlwnm". encodePPC64RotateMask describes aux - {name: "RLWMI", argLength: 2, reg: gp21a0, asm: "RLWMI", aux: "Int64", resultInArg0: true}, // "rlwimi" similar aux encoding as above - {name: "RLDICL", argLength: 1, reg: gp11, asm: "RLDICL", aux: "Int64"}, // Auxint is encoded similarly to RLWINM, but only MB and SH are valid. ME is always 63. - {name: "RLDICLCC", argLength: 1, reg: gp11, asm: "RLDICLCC", aux: "Int64", typ: "(Int, Flags)"}, // Auxint is encoded similarly to RLWINM, but only MB and SH are valid. ME is always 63. Sets CC. - {name: "RLDICR", argLength: 1, reg: gp11, asm: "RLDICR", aux: "Int64"}, // Likewise, but only ME and SH are valid. MB is always 0. - - {name: "CNTLZD", argLength: 1, reg: gp11, asm: "CNTLZD"}, // count leading zeros + {name: "ADDZEzero", argLength: 1, reg: xergp, asm: "ADDZE", typ: "UInt64", earlyOk: true}, // CA (arg0) + $0 -> out + {name: "SUBZEzero", argLength: 1, reg: xergp, asm: "SUBZE", typ: "UInt64", earlyOk: true}, // $0 - CA (arg0) -> out + + {name: "SRADconst", argLength: 1, reg: gp11cxer, asm: "SRAD", aux: "Int64", earlyOk: true}, // signed arg0 >> auxInt, 0 <= auxInt < 64, 64 bit width + {name: "SRAWconst", argLength: 1, reg: gp11cxer, asm: "SRAW", aux: "Int64", earlyOk: true}, // signed arg0 >> auxInt, 0 <= auxInt < 32, 32 bit width + {name: "SRDconst", argLength: 1, reg: gp11, asm: "SRD", aux: "Int64", earlyOk: true}, // unsigned arg0 >> auxInt, 0 <= auxInt < 64, 64 bit width + {name: "SRWconst", argLength: 1, reg: gp11, asm: "SRW", aux: "Int64", earlyOk: true}, // unsigned arg0 >> auxInt, 0 <= auxInt < 32, 32 bit width + {name: "SLDconst", argLength: 1, reg: gp11, asm: "SLD", aux: "Int64", earlyOk: true}, // arg0 << auxInt, 0 <= auxInt < 64, 64 bit width + {name: "SLWconst", argLength: 1, reg: gp11, asm: "SLW", aux: "Int64", earlyOk: true}, // arg0 << auxInt, 0 <= auxInt < 32, 32 bit width + + {name: "ROTLconst", argLength: 1, reg: gp11, asm: "ROTL", aux: "Int64", earlyOk: true}, // arg0 rotate left by auxInt bits + {name: "ROTLWconst", argLength: 1, reg: gp11, asm: "ROTLW", aux: "Int64", earlyOk: true}, // uint32(arg0) rotate left by auxInt bits + {name: "EXTSWSLconst", argLength: 1, reg: gp11, asm: "EXTSWSLI", aux: "Int64", earlyOk: true}, + + {name: "RLWINM", argLength: 1, reg: gp11, asm: "RLWNM", aux: "Int64", earlyOk: true}, // Rotate and mask by immediate "rlwinm". encodePPC64RotateMask describes aux + {name: "RLWNM", argLength: 2, reg: gp21, asm: "RLWNM", aux: "Int64", earlyOk: true}, // Rotate and mask by "rlwnm". encodePPC64RotateMask describes aux + {name: "RLWMI", argLength: 2, reg: gp21a0, asm: "RLWMI", aux: "Int64", resultInArg0: true, earlyOk: true}, // "rlwimi" similar aux encoding as above + {name: "RLDICL", argLength: 1, reg: gp11, asm: "RLDICL", aux: "Int64", earlyOk: true}, // Auxint is encoded similarly to RLWINM, but only MB and SH are valid. ME is always 63. + {name: "RLDICLCC", argLength: 1, reg: gp11, asm: "RLDICLCC", aux: "Int64", typ: "(Int, Flags)"}, // Auxint is encoded similarly to RLWINM, but only MB and SH are valid. ME is always 63. Sets CC. + {name: "RLDICR", argLength: 1, reg: gp11, asm: "RLDICR", aux: "Int64", earlyOk: true}, // Likewise, but only ME and SH are valid. MB is always 0. + + {name: "CNTLZD", argLength: 1, reg: gp11, asm: "CNTLZD", earlyOk: true}, // count leading zeros {name: "CNTLZDCC", argLength: 1, reg: gp11, asm: "CNTLZDCC", typ: "(Int, Flags)"}, // count leading zeros, sets CC - {name: "CNTLZW", argLength: 1, reg: gp11, asm: "CNTLZW"}, // count leading zeros (32 bit) + {name: "CNTLZW", argLength: 1, reg: gp11, asm: "CNTLZW", earlyOk: true}, // count leading zeros (32 bit) - {name: "CNTTZD", argLength: 1, reg: gp11, asm: "CNTTZD"}, // count trailing zeros - {name: "CNTTZW", argLength: 1, reg: gp11, asm: "CNTTZW"}, // count trailing zeros (32 bit) + {name: "CNTTZD", argLength: 1, reg: gp11, asm: "CNTTZD", earlyOk: true}, // count trailing zeros + {name: "CNTTZW", argLength: 1, reg: gp11, asm: "CNTTZW", earlyOk: true}, // count trailing zeros (32 bit) - {name: "POPCNTD", argLength: 1, reg: gp11, asm: "POPCNTD"}, // number of set bits in arg0 - {name: "POPCNTW", argLength: 1, reg: gp11, asm: "POPCNTW"}, // number of set bits in each word of arg0 placed in corresponding word - {name: "POPCNTB", argLength: 1, reg: gp11, asm: "POPCNTB"}, // number of set bits in each byte of arg0 placed in corresponding byte + {name: "POPCNTD", argLength: 1, reg: gp11, asm: "POPCNTD", earlyOk: true}, // number of set bits in arg0 + {name: "POPCNTW", argLength: 1, reg: gp11, asm: "POPCNTW", earlyOk: true}, // number of set bits in each word of arg0 placed in corresponding word + {name: "POPCNTB", argLength: 1, reg: gp11, asm: "POPCNTB", earlyOk: true}, // number of set bits in each byte of arg0 placed in corresponding byte - {name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV"}, // arg0/arg1 - {name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS"}, // arg0/arg1 + {name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV", earlyOk: true}, // arg0/arg1 + {name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS", earlyOk: true}, // arg0/arg1 {name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"}, // arg0/arg1 (signed 64-bit) {name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"}, // arg0/arg1 (signed 32-bit) @@ -279,11 +279,11 @@ func init() { // MOD is implemented as rem := arg0 - (arg0/arg1) * arg1 // Conversions are all float-to-float register operations. "Integer" refers to encoding in the FP register. - {name: "FCTIDZ", argLength: 1, reg: fp11, asm: "FCTIDZ", typ: "Float64"}, // convert float to 64-bit int round towards zero - {name: "FCTIWZ", argLength: 1, reg: fp11, asm: "FCTIWZ", typ: "Float64"}, // convert float to 32-bit int round towards zero - {name: "FCFID", argLength: 1, reg: fp11, asm: "FCFID", typ: "Float64"}, // convert 64-bit integer to float - {name: "FCFIDS", argLength: 1, reg: fp11, asm: "FCFIDS", typ: "Float32"}, // convert 32-bit integer to float - {name: "FRSP", argLength: 1, reg: fp11, asm: "FRSP", typ: "Float64"}, // round float to 32-bit value + {name: "FCTIDZ", argLength: 1, reg: fp11, asm: "FCTIDZ", typ: "Float64", earlyOk: true}, // convert float to 64-bit int round towards zero + {name: "FCTIWZ", argLength: 1, reg: fp11, asm: "FCTIWZ", typ: "Float64", earlyOk: true}, // convert float to 32-bit int round towards zero + {name: "FCFID", argLength: 1, reg: fp11, asm: "FCFID", typ: "Float64", earlyOk: true}, // convert 64-bit integer to float + {name: "FCFIDS", argLength: 1, reg: fp11, asm: "FCFIDS", typ: "Float32", earlyOk: true}, // convert 32-bit integer to float + {name: "FRSP", argLength: 1, reg: fp11, asm: "FRSP", typ: "Float64", earlyOk: true}, // round float to 32-bit value // Movement between float and integer registers with no change in bits; accomplished with stores+loads on PPC. // Because the 32-bit load-literal-bits instructions have impoverished addressability, always widen the @@ -291,77 +291,77 @@ func init() { // There are optimizations that should apply -- (Xi2f64 (MOVWload (not-ADD-ptr+offset) ) ) could use // the word-load instructions. (Xi2f64 (MOVDload ptr )) can be (FMOVDload ptr) - {name: "MFVSRD", argLength: 1, reg: fpgp, asm: "MFVSRD", typ: "Int64"}, // move 64 bits of F register into G register - {name: "MTVSRD", argLength: 1, reg: gpfp, asm: "MTVSRD", typ: "Float64"}, // move 64 bits of G register into F register - - {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0&arg1 - {name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN"}, // arg0&^arg1 - {name: "ANDNCC", argLength: 2, reg: gp21, asm: "ANDNCC", typ: "(Int64,Flags)"}, // arg0&^arg1 sets CC - {name: "ANDCC", argLength: 2, reg: gp21, asm: "ANDCC", commutative: true, typ: "(Int64,Flags)"}, // arg0&arg1 sets CC - {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0|arg1 - {name: "ORN", argLength: 2, reg: gp21, asm: "ORN"}, // arg0|^arg1 - {name: "ORCC", argLength: 2, reg: gp21, asm: "ORCC", commutative: true, typ: "(Int,Flags)"}, // arg0|arg1 sets CC - {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true}, // ^(arg0|arg1) - {name: "NORCC", argLength: 2, reg: gp21, asm: "NORCC", commutative: true, typ: "(Int,Flags)"}, // ^(arg0|arg1) sets CC - {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", typ: "Int64", commutative: true}, // arg0^arg1 - {name: "XORCC", argLength: 2, reg: gp21, asm: "XORCC", commutative: true, typ: "(Int,Flags)"}, // arg0^arg1 sets CC - {name: "EQV", argLength: 2, reg: gp21, asm: "EQV", typ: "Int64", commutative: true}, // arg0^^arg1 - {name: "NEG", argLength: 1, reg: gp11, asm: "NEG"}, // -arg0 (integer) - {name: "NEGCC", argLength: 1, reg: gp11, asm: "NEGCC", typ: "(Int,Flags)"}, // -arg0 (integer) sets CC - {name: "BRD", argLength: 1, reg: gp11, asm: "BRD"}, // reversebytes64(arg0) - {name: "BRW", argLength: 1, reg: gp11, asm: "BRW"}, // reversebytes32(arg0) - {name: "BRH", argLength: 1, reg: gp11, asm: "BRH"}, // reversebytes16(arg0) - {name: "FNEG", argLength: 1, reg: fp11, asm: "FNEG"}, // -arg0 (floating point) - {name: "FSQRT", argLength: 1, reg: fp11, asm: "FSQRT"}, // sqrt(arg0) (floating point) - {name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS"}, // sqrt(arg0) (floating point, single precision) - {name: "FFLOOR", argLength: 1, reg: fp11, asm: "FRIM"}, // floor(arg0), float64 - {name: "FCEIL", argLength: 1, reg: fp11, asm: "FRIP"}, // ceil(arg0), float64 - {name: "FTRUNC", argLength: 1, reg: fp11, asm: "FRIZ"}, // trunc(arg0), float64 - {name: "FROUND", argLength: 1, reg: fp11, asm: "FRIN"}, // round(arg0), float64 - {name: "FABS", argLength: 1, reg: fp11, asm: "FABS"}, // abs(arg0), float64 - {name: "FNABS", argLength: 1, reg: fp11, asm: "FNABS"}, // -abs(arg0), float64 - {name: "FCPSGN", argLength: 2, reg: fp21, asm: "FCPSGN"}, // copysign arg0 -> arg1, float64 - - {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"}, // arg0|aux - {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64"}, // arg0^aux - {name: "ANDCCconst", argLength: 1, reg: regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}, asm: "ANDCC", aux: "Int64", typ: "(Int,Flags)"}, // arg0&aux == 0 // and-immediate sets CC on PPC, always. - {name: "ANDconst", argLength: 1, reg: regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}, clobberFlags: true, asm: "ANDCC", aux: "Int64", typ: "Int"}, // arg0&aux == 0 // and-immediate sets CC on PPC, always. - - {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB", typ: "Int64"}, // sign extend int8 to int64 - {name: "MOVBZreg", argLength: 1, reg: gp11, asm: "MOVBZ", typ: "Int64"}, // zero extend uint8 to uint64 - {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH", typ: "Int64"}, // sign extend int16 to int64 - {name: "MOVHZreg", argLength: 1, reg: gp11, asm: "MOVHZ", typ: "Int64"}, // zero extend uint16 to uint64 - {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW", typ: "Int64"}, // sign extend int32 to int64 - {name: "MOVWZreg", argLength: 1, reg: gp11, asm: "MOVWZ", typ: "Int64"}, // zero extend uint32 to uint64 + {name: "MFVSRD", argLength: 1, reg: fpgp, asm: "MFVSRD", typ: "Int64", earlyOk: true}, // move 64 bits of F register into G register + {name: "MTVSRD", argLength: 1, reg: gpfp, asm: "MTVSRD", typ: "Float64", earlyOk: true}, // move 64 bits of G register into F register + + {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true, earlyOk: true}, // arg0&arg1 + {name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN", earlyOk: true}, // arg0&^arg1 + {name: "ANDNCC", argLength: 2, reg: gp21, asm: "ANDNCC", typ: "(Int64,Flags)"}, // arg0&^arg1 sets CC + {name: "ANDCC", argLength: 2, reg: gp21, asm: "ANDCC", commutative: true, typ: "(Int64,Flags)"}, // arg0&arg1 sets CC + {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true, earlyOk: true}, // arg0|arg1 + {name: "ORN", argLength: 2, reg: gp21, asm: "ORN", earlyOk: true}, // arg0|^arg1 + {name: "ORCC", argLength: 2, reg: gp21, asm: "ORCC", commutative: true, typ: "(Int,Flags)"}, // arg0|arg1 sets CC + {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true, earlyOk: true}, // ^(arg0|arg1) + {name: "NORCC", argLength: 2, reg: gp21, asm: "NORCC", commutative: true, typ: "(Int,Flags)"}, // ^(arg0|arg1) sets CC + {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", typ: "Int64", commutative: true, earlyOk: true}, // arg0^arg1 + {name: "XORCC", argLength: 2, reg: gp21, asm: "XORCC", commutative: true, typ: "(Int,Flags)"}, // arg0^arg1 sets CC + {name: "EQV", argLength: 2, reg: gp21, asm: "EQV", typ: "Int64", commutative: true, earlyOk: true}, // arg0^^arg1 + {name: "NEG", argLength: 1, reg: gp11, asm: "NEG", earlyOk: true}, // -arg0 (integer) + {name: "NEGCC", argLength: 1, reg: gp11, asm: "NEGCC", typ: "(Int,Flags)"}, // -arg0 (integer) sets CC + {name: "BRD", argLength: 1, reg: gp11, asm: "BRD", earlyOk: true}, // reversebytes64(arg0) + {name: "BRW", argLength: 1, reg: gp11, asm: "BRW", earlyOk: true}, // reversebytes32(arg0) + {name: "BRH", argLength: 1, reg: gp11, asm: "BRH", earlyOk: true}, // reversebytes16(arg0) + {name: "FNEG", argLength: 1, reg: fp11, asm: "FNEG", earlyOk: true}, // -arg0 (floating point) + {name: "FSQRT", argLength: 1, reg: fp11, asm: "FSQRT", earlyOk: true}, // sqrt(arg0) (floating point) + {name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS", earlyOk: true}, // sqrt(arg0) (floating point, single precision) + {name: "FFLOOR", argLength: 1, reg: fp11, asm: "FRIM", earlyOk: true}, // floor(arg0), float64 + {name: "FCEIL", argLength: 1, reg: fp11, asm: "FRIP", earlyOk: true}, // ceil(arg0), float64 + {name: "FTRUNC", argLength: 1, reg: fp11, asm: "FRIZ", earlyOk: true}, // trunc(arg0), float64 + {name: "FROUND", argLength: 1, reg: fp11, asm: "FRIN", earlyOk: true}, // round(arg0), float64 + {name: "FABS", argLength: 1, reg: fp11, asm: "FABS", earlyOk: true}, // abs(arg0), float64 + {name: "FNABS", argLength: 1, reg: fp11, asm: "FNABS", earlyOk: true}, // -abs(arg0), float64 + {name: "FCPSGN", argLength: 2, reg: fp21, asm: "FCPSGN", earlyOk: true}, // copysign arg0 -> arg1, float64 + + {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64", earlyOk: true}, // arg0|aux + {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", earlyOk: true}, // arg0^aux + {name: "ANDCCconst", argLength: 1, reg: regInfo{inputs: []regMask{gp.union(sp).union(sb)}, outputs: []regMask{gp}}, asm: "ANDCC", aux: "Int64", typ: "(Int,Flags)", earlyOk: true}, // arg0&aux == 0 // and-immediate sets CC on PPC, always. + {name: "ANDconst", argLength: 1, reg: regInfo{inputs: []regMask{gp.union(sp).union(sb)}, outputs: []regMask{gp}}, clobberFlags: true, asm: "ANDCC", aux: "Int64", typ: "Int", earlyOk: true}, // arg0&aux == 0 // and-immediate sets CC on PPC, always. + + {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB", typ: "Int64", earlyOk: true}, // sign extend int8 to int64 + {name: "MOVBZreg", argLength: 1, reg: gp11, asm: "MOVBZ", typ: "Int64", earlyOk: true}, // zero extend uint8 to uint64 + {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH", typ: "Int64", earlyOk: true}, // sign extend int16 to int64 + {name: "MOVHZreg", argLength: 1, reg: gp11, asm: "MOVHZ", typ: "Int64", earlyOk: true}, // zero extend uint16 to uint64 + {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW", typ: "Int64", earlyOk: true}, // sign extend int32 to int64 + {name: "MOVWZreg", argLength: 1, reg: gp11, asm: "MOVWZ", typ: "Int64", earlyOk: true}, // zero extend uint32 to uint64 // Load bytes in the endian order of the arch from arg0+aux+auxint into a 64 bit register. - {name: "MOVBZload", argLength: 2, reg: gpload, asm: "MOVBZ", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load byte zero extend - {name: "MOVHload", argLength: 2, reg: gpload, asm: "MOVH", aux: "SymOff", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"}, // load 2 bytes sign extend - {name: "MOVHZload", argLength: 2, reg: gpload, asm: "MOVHZ", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load 2 bytes zero extend - {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"}, // load 4 bytes sign extend - {name: "MOVWZload", argLength: 2, reg: gpload, asm: "MOVWZ", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load 4 bytes zero extend - {name: "MOVDload", argLength: 2, reg: gpload, asm: "MOVD", aux: "SymOff", typ: "Int64", faultOnNilArg0: true, symEffect: "Read"}, // load 8 bytes + {name: "MOVBZload", argLength: 2, reg: gpload, asm: "MOVBZ", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load byte zero extend + {name: "MOVHload", argLength: 2, reg: gpload, asm: "MOVH", aux: "SymOff", typ: "Int16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 2 bytes sign extend + {name: "MOVHZload", argLength: 2, reg: gpload, asm: "MOVHZ", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 2 bytes zero extend + {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", typ: "Int32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 4 bytes sign extend + {name: "MOVWZload", argLength: 2, reg: gpload, asm: "MOVWZ", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 4 bytes zero extend + {name: "MOVDload", argLength: 2, reg: gpload, asm: "MOVD", aux: "SymOff", typ: "Int64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 8 bytes // Load bytes in reverse endian order of the arch from arg0 into a 64 bit register, all zero extend. // The generated instructions are indexed loads with no offset field in the instruction so the aux fields are not used. // In these cases the index register field is set to 0 and the full address is in the base register. - {name: "MOVDBRload", argLength: 2, reg: gpload, asm: "MOVDBR", typ: "UInt64", faultOnNilArg0: true}, // load 8 bytes reverse order - {name: "MOVWBRload", argLength: 2, reg: gpload, asm: "MOVWBR", typ: "UInt32", faultOnNilArg0: true}, // load 4 bytes zero extend reverse order - {name: "MOVHBRload", argLength: 2, reg: gpload, asm: "MOVHBR", typ: "UInt16", faultOnNilArg0: true}, // load 2 bytes zero extend reverse order + {name: "MOVDBRload", argLength: 2, reg: gpload, asm: "MOVDBR", typ: "UInt64", faultOnNilArg0: true, addrSinkArg0: true}, // load 8 bytes reverse order + {name: "MOVWBRload", argLength: 2, reg: gpload, asm: "MOVWBR", typ: "UInt32", faultOnNilArg0: true, addrSinkArg0: true}, // load 4 bytes zero extend reverse order + {name: "MOVHBRload", argLength: 2, reg: gpload, asm: "MOVHBR", typ: "UInt16", faultOnNilArg0: true, addrSinkArg0: true}, // load 2 bytes zero extend reverse order // In these cases an index register is used in addition to a base register // Loads from memory location arg[0] + arg[1]. - {name: "MOVBZloadidx", argLength: 3, reg: gploadidx, asm: "MOVBZ", typ: "UInt8"}, // zero extend uint8 to uint64 - {name: "MOVHloadidx", argLength: 3, reg: gploadidx, asm: "MOVH", typ: "Int16"}, // sign extend int16 to int64 - {name: "MOVHZloadidx", argLength: 3, reg: gploadidx, asm: "MOVHZ", typ: "UInt16"}, // zero extend uint16 to uint64 - {name: "MOVWloadidx", argLength: 3, reg: gploadidx, asm: "MOVW", typ: "Int32"}, // sign extend int32 to int64 - {name: "MOVWZloadidx", argLength: 3, reg: gploadidx, asm: "MOVWZ", typ: "UInt32"}, // zero extend uint32 to uint64 - {name: "MOVDloadidx", argLength: 3, reg: gploadidx, asm: "MOVD", typ: "Int64"}, - {name: "MOVHBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVHBR", typ: "Int16"}, // sign extend int16 to int64 - {name: "MOVWBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVWBR", typ: "Int32"}, // sign extend int32 to int64 - {name: "MOVDBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVDBR", typ: "Int64"}, - {name: "FMOVDloadidx", argLength: 3, reg: fploadidx, asm: "FMOVD", typ: "Float64"}, - {name: "FMOVSloadidx", argLength: 3, reg: fploadidx, asm: "FMOVS", typ: "Float32"}, + {name: "MOVBZloadidx", argLength: 3, reg: gploadidx, asm: "MOVBZ", typ: "UInt8", addrSinkArg0: true, addrSinkArg1: true}, // zero extend uint8 to uint64 + {name: "MOVHloadidx", argLength: 3, reg: gploadidx, asm: "MOVH", typ: "Int16", addrSinkArg0: true, addrSinkArg1: true}, // sign extend int16 to int64 + {name: "MOVHZloadidx", argLength: 3, reg: gploadidx, asm: "MOVHZ", typ: "UInt16", addrSinkArg0: true, addrSinkArg1: true}, // zero extend uint16 to uint64 + {name: "MOVWloadidx", argLength: 3, reg: gploadidx, asm: "MOVW", typ: "Int32", addrSinkArg0: true, addrSinkArg1: true}, // sign extend int32 to int64 + {name: "MOVWZloadidx", argLength: 3, reg: gploadidx, asm: "MOVWZ", typ: "UInt32", addrSinkArg0: true, addrSinkArg1: true}, // zero extend uint32 to uint64 + {name: "MOVDloadidx", argLength: 3, reg: gploadidx, asm: "MOVD", typ: "Int64", addrSinkArg0: true, addrSinkArg1: true}, + {name: "MOVHBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVHBR", typ: "Int16", addrSinkArg0: true, addrSinkArg1: true}, // sign extend int16 to int64 + {name: "MOVWBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVWBR", typ: "Int32", addrSinkArg0: true, addrSinkArg1: true}, // sign extend int32 to int64 + {name: "MOVDBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVDBR", typ: "Int64", addrSinkArg0: true, addrSinkArg1: true}, + {name: "FMOVDloadidx", argLength: 3, reg: fploadidx, asm: "FMOVD", typ: "Float64", addrSinkArg0: true, addrSinkArg1: true}, + {name: "FMOVSloadidx", argLength: 3, reg: fploadidx, asm: "FMOVS", typ: "Float32", addrSinkArg0: true, addrSinkArg1: true}, // Prefetch instruction // Do prefetch of address generated with arg0 and arg1 with option aux. arg0=addr,arg1=memory, aux=option. @@ -369,47 +369,47 @@ func init() { // Store bytes in the reverse endian order of the arch into arg0. // These are indexed stores with no offset field in the instruction so the auxint fields are not used. - {name: "MOVDBRstore", argLength: 3, reg: gpstore, asm: "MOVDBR", typ: "Mem", faultOnNilArg0: true}, // store 8 bytes reverse order - {name: "MOVWBRstore", argLength: 3, reg: gpstore, asm: "MOVWBR", typ: "Mem", faultOnNilArg0: true}, // store 4 bytes reverse order - {name: "MOVHBRstore", argLength: 3, reg: gpstore, asm: "MOVHBR", typ: "Mem", faultOnNilArg0: true}, // store 2 bytes reverse order + {name: "MOVDBRstore", argLength: 3, reg: gpstore, asm: "MOVDBR", typ: "Mem", faultOnNilArg0: true, addrSinkArg0: true}, // store 8 bytes reverse order + {name: "MOVWBRstore", argLength: 3, reg: gpstore, asm: "MOVWBR", typ: "Mem", faultOnNilArg0: true, addrSinkArg0: true}, // store 4 bytes reverse order + {name: "MOVHBRstore", argLength: 3, reg: gpstore, asm: "MOVHBR", typ: "Mem", faultOnNilArg0: true, addrSinkArg0: true}, // store 2 bytes reverse order // Floating point loads from arg0+aux+auxint - {name: "FMOVDload", argLength: 2, reg: fpload, asm: "FMOVD", aux: "SymOff", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load double float - {name: "FMOVSload", argLength: 2, reg: fpload, asm: "FMOVS", aux: "SymOff", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load single float + {name: "FMOVDload", argLength: 2, reg: fpload, asm: "FMOVD", aux: "SymOff", typ: "Float64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load double float + {name: "FMOVSload", argLength: 2, reg: fpload, asm: "FMOVS", aux: "SymOff", typ: "Float32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load single float // Store bytes in the endian order of the arch into arg0+aux+auxint - {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store byte - {name: "MOVHstore", argLength: 3, reg: gpstore, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes - {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes - {name: "MOVDstore", argLength: 3, reg: gpstore, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes + {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store byte + {name: "MOVHstore", argLength: 3, reg: gpstore, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 2 bytes + {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes + {name: "MOVDstore", argLength: 3, reg: gpstore, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes // Store floating point value into arg0+aux+auxint - {name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "FMOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store double flot - {name: "FMOVSstore", argLength: 3, reg: fpstore, asm: "FMOVS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store single float + {name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "FMOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store double flot + {name: "FMOVSstore", argLength: 3, reg: fpstore, asm: "FMOVS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store single float // Stores using index and base registers // Stores to arg[0] + arg[1] - {name: "MOVBstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVB", typ: "Mem"}, // store bye - {name: "MOVHstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVH", typ: "Mem"}, // store half word - {name: "MOVWstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVW", typ: "Mem"}, // store word - {name: "MOVDstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVD", typ: "Mem"}, // store double word - {name: "FMOVDstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVD", typ: "Mem"}, // store double float - {name: "FMOVSstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVS", typ: "Mem"}, // store single float - {name: "MOVHBRstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVHBR", typ: "Mem"}, // store half word reversed byte using index reg - {name: "MOVWBRstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVWBR", typ: "Mem"}, // store word reversed byte using index reg - {name: "MOVDBRstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVDBR", typ: "Mem"}, // store double word reversed byte using index reg + {name: "MOVBstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVB", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store bye + {name: "MOVHstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVH", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store half word + {name: "MOVWstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVW", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store word + {name: "MOVDstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVD", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store double word + {name: "FMOVDstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVD", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store double float + {name: "FMOVSstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVS", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store single float + {name: "MOVHBRstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVHBR", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store half word reversed byte using index reg + {name: "MOVWBRstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVWBR", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store word reversed byte using index reg + {name: "MOVDBRstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVDBR", typ: "Mem", addrSinkArg0: true, addrSinkArg1: true}, // store double word reversed byte using index reg // The following ops store 0 into arg0+aux+auxint arg1=mem - {name: "MOVBstorezero", argLength: 2, reg: gpstorezero, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store zero 1 byte - {name: "MOVHstorezero", argLength: 2, reg: gpstorezero, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store zero 2 bytes - {name: "MOVWstorezero", argLength: 2, reg: gpstorezero, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store zero 4 bytes - {name: "MOVDstorezero", argLength: 2, reg: gpstorezero, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store zero 8 bytes + {name: "MOVBstorezero", argLength: 2, reg: gpstorezero, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store zero 1 byte + {name: "MOVHstorezero", argLength: 2, reg: gpstorezero, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store zero 2 bytes + {name: "MOVWstorezero", argLength: 2, reg: gpstorezero, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store zero 4 bytes + {name: "MOVDstorezero", argLength: 2, reg: gpstorezero, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store zero 8 bytes - {name: "MOVDaddr", argLength: 1, reg: regInfo{inputs: []regMask{sp | sb | gp}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVD", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB/GP + {name: "MOVDaddr", argLength: 1, reg: regInfo{inputs: []regMask{sp.union(sb).union(gp)}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVD", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB/GP - {name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVD", typ: "Int64", rematerializeable: true}, // - {name: "FMOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "FMOVD", rematerializeable: true}, // - {name: "FMOVSconst", argLength: 0, reg: fp01, aux: "Float32", asm: "FMOVS", rematerializeable: true}, // + {name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVD", typ: "Int64", rematerializeable: true, earlyOk: true}, // + {name: "FMOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "FMOVD", rematerializeable: true, earlyOk: true}, // + {name: "FMOVSconst", argLength: 0, reg: fp01, aux: "Float32", asm: "FMOVS", rematerializeable: true, earlyOk: true}, // {name: "FCMPU", argLength: 2, reg: fp2cr, asm: "FCMPU", typ: "Flags"}, {name: "CMP", argLength: 2, reg: gp2cr, asm: "CMP", typ: "Flags"}, // arg0 compare to arg1 @@ -425,13 +425,13 @@ func init() { // ISELZ arg1 ? arg0 : $0 // auxInt values 0=LT 1=GT 2=EQ 3=SO (summary overflow/unordered) 4=GE 5=LE 6=NE 7=NSO (not summary overflow/not unordered) // Note, auxInt^4 inverts the comparison condition. For example, LT^4 becomes GE, and "ISEL [a] x y z" is equivalent to ISEL [a^4] y x z". - {name: "ISEL", argLength: 3, reg: crgp21, asm: "ISEL", aux: "Int32", typ: "Int32"}, - {name: "ISELZ", argLength: 2, reg: crgp11, asm: "ISEL", aux: "Int32"}, + {name: "ISEL", argLength: 3, reg: crgp21, asm: "ISEL", aux: "Int32", typ: "Int32", earlyOk: true}, + {name: "ISELZ", argLength: 2, reg: crgp11, asm: "ISEL", aux: "Int32", earlyOk: true}, // SETBC auxInt values 0=LT 1=GT 2=EQ (CRbit=1)? 1 : 0 - {name: "SETBC", argLength: 1, reg: crgp, asm: "SETBC", aux: "Int32", typ: "Int32"}, + {name: "SETBC", argLength: 1, reg: crgp, asm: "SETBC", aux: "Int32", typ: "Int32", earlyOk: true}, // SETBCR auxInt values 0=LT 1=GT 2=EQ (CRbit=1)? 0 : 1 - {name: "SETBCR", argLength: 1, reg: crgp, asm: "SETBCR", aux: "Int32", typ: "Int32"}, + {name: "SETBCR", argLength: 1, reg: crgp, asm: "SETBCR", aux: "Int32", typ: "Int32", earlyOk: true}, // pseudo-ops {name: "Equal", argLength: 1, reg: crgp}, // bool, true flags encode x==y false otherwise. @@ -460,15 +460,16 @@ func init() { {name: "LoweredGetCallerPC", reg: gp01, rematerializeable: true}, //arg0=ptr,arg1=mem, returns void. Faults if ptr is nil. - {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gp | sp | sb}, clobbers: tmp}, clobberFlags: true, nilCheck: true, faultOnNilArg0: true}, + {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gp.union(sp).union(sb)}, clobbers: tmp}, clobberFlags: true, nilCheck: true, faultOnNilArg0: true}, // Round ops to block fused-multiply-add extraction. {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true}, {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true}, - {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{callptr, ctxt, 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem - {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{callptr}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtailinter", argLength: -1, reg: regInfo{inputs: []regMask{callptr}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{callptr, ctxt, regMask{}}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{callptr}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem // large or unaligned zeroing // arg0 = address of memory to zero (in R3, changed as side effect) @@ -509,6 +510,7 @@ func init() { typ: "Mem", faultOnNilArg0: true, unsafePoint: true, + addrSinkArg0: true, }, { name: "LoweredZeroShort", @@ -519,6 +521,7 @@ func init() { typ: "Mem", faultOnNilArg0: true, unsafePoint: true, + addrSinkArg0: true, }, { name: "LoweredQuadZeroShort", @@ -530,6 +533,7 @@ func init() { typ: "Mem", faultOnNilArg0: true, unsafePoint: true, + addrSinkArg0: true, }, { name: "LoweredQuadZero", @@ -543,6 +547,7 @@ func init() { typ: "Mem", faultOnNilArg0: true, unsafePoint: true, + addrSinkArg0: true, }, // R31 is temp register @@ -591,6 +596,8 @@ func init() { faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, + addrSinkArg0: true, + addrSinkArg1: true, }, { name: "LoweredMoveShort", @@ -603,6 +610,8 @@ func init() { faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // The following is similar to the LoweredMove, but uses @@ -621,6 +630,8 @@ func init() { faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, + addrSinkArg0: true, + addrSinkArg1: true, }, { @@ -634,6 +645,8 @@ func init() { faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, + addrSinkArg0: true, + addrSinkArg1: true, }, {name: "LoweredAtomicStore8", argLength: 3, reg: gpstore, typ: "Mem", aux: "Int64", faultOnNilArg0: true, hasSideEffects: true}, @@ -700,7 +713,7 @@ func init() { // It preserves R0 through R17 (except special registers R1, R2, R11, R12, R13), g, and R20 and R21, // but may clobber anything else, including R31 (REGTMP). // Returns a pointer to a write barrier buffer in R29. - {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ buildReg("R0 R3 R4 R5 R6 R7 R8 R9 R10 R14 R15 R16 R17 R20 R21 g")) | buildReg("R31"), outputs: []regMask{buildReg("R29")}}, clobberFlags: true, aux: "Int64"}, + {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave.minus(buildReg("R0 R3 R4 R5 R6 R7 R8 R9 R10 R14 R15 R16 R17 R20 R21 g")).union(buildReg("R31")), outputs: []regMask{buildReg("R29")}}, clobberFlags: true, aux: "Int64"}, {name: "LoweredPubBarrier", argLength: 1, asm: "LWSYNC", hasSideEffects: true}, // Do data barrier. arg0=memory diff --git a/src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules b/src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules index 15e6f7251977c7..cd60e79a9dbf85 100644 --- a/src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules +++ b/src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules @@ -18,9 +18,6 @@ (SETBC [1] cmp) && buildcfg.GOPPC64 <= 9 => (ISELZ [1] (MOVDconst [1]) cmp) (SETBCR [1] cmp) && buildcfg.GOPPC64 <= 9 => (ISELZ [5] (MOVDconst [1]) cmp) -// The upper bits of the smaller than register values is undefined. Take advantage of that. -(AND x:(MOVDconst [m]) n) && t.Size() <= 2 => (ANDconst [int64(int16(m))] n) - // Convert simple bit masks to an equivalent rldic[lr] if possible. (AND x:(MOVDconst [m]) n) && isPPC64ValidShiftMask(m) => (RLDICL [encodePPC64RotateMask(0,m,64)] n) (AND x:(MOVDconst [m]) n) && m != 0 && isPPC64ValidShiftMask(^m) => (RLDICR [encodePPC64RotateMask(0,m,64)] n) diff --git a/src/cmd/compile/internal/ssa/_gen/RISCV64.rules b/src/cmd/compile/internal/ssa/_gen/RISCV64.rules index 7059273eb2fd4c..5270b26862b32f 100644 --- a/src/cmd/compile/internal/ssa/_gen/RISCV64.rules +++ b/src/cmd/compile/internal/ssa/_gen/RISCV64.rules @@ -376,11 +376,11 @@ // Unroll zeroing in medium size (at most 192 bytes i.e. 3 cachelines) (Zero [s] {t} ptr mem) && s <= 24*moveSize(t.Alignment(), config) => - (LoweredZero [makeValAndOff(int32(s),int32(t.Alignment()))] ptr mem) + (LoweredZero [s] {t.Alignment()} ptr mem) // Generic zeroing uses a loop (Zero [s] {t} ptr mem) && s > 24*moveSize(t.Alignment(), config) => - (LoweredZeroLoop [makeValAndOff(int32(s),int32(t.Alignment()))] ptr mem) + (LoweredZeroLoop [s] {t.Alignment()} ptr mem) // Checks (IsNonNil ...) => (SNEZ ...) @@ -446,12 +446,12 @@ // Generic move (Move [s] {t} dst src mem) && s > 0 && s <= 3*8*moveSize(t.Alignment(), config) && logLargeCopy(v, s) => - (LoweredMove [makeValAndOff(int32(s),int32(t.Alignment()))] dst src mem) + (LoweredMove [s] {t.Alignment()} dst src mem) // Generic move uses a loop (Move [s] {t} dst src mem) && s > 3*8*moveSize(t.Alignment(), config) && logLargeCopy(v, s) => - (LoweredMoveLoop [makeValAndOff(int32(s),int32(t.Alignment()))] dst src mem) + (LoweredMoveLoop [s] {t.Alignment()} dst src mem) // Boolean ops; 0=false, 1=true (AndB ...) => (AND ...) @@ -467,8 +467,7 @@ (OffPtr [off] ptr) => (ADD (MOVDconst [off]) ptr) (Const(64|32|16|8) [val]) => (MOVDconst [int64(val)]) -(Const32F [val]) => (FMVSX (MOVDconst [int64(math.Float32bits(val))])) -(Const64F [val]) => (FMVDX (MOVDconst [int64(math.Float64bits(val))])) +(Const(64|32)F ...) => (FMOV(D|F)const ...) (ConstNil) => (MOVDconst [0]) (ConstBool [val]) => (MOVDconst [int64(b2i(val))]) @@ -481,6 +480,7 @@ (ClosureCall ...) => (CALLclosure ...) (InterCall ...) => (CALLinter ...) (TailCall ...) => (CALLtail ...) +(TailCallInter ...) => (CALLtailinter ...) // Atomic Intrinsics (AtomicLoad(Ptr|64|32|8) ...) => (LoweredAtomicLoad(64|64|32|8) ...) @@ -622,17 +622,19 @@ (MOVBUreg x:(Select0 (LoweredAtomicCas64 _ _ _ _))) => (MOVDreg x) // Avoid sign extension after word arithmetic. -(MOVWreg x:(ADDIW _)) => (MOVDreg x) -(MOVWreg x:(SUBW _ _)) => (MOVDreg x) -(MOVWreg x:(NEGW _)) => (MOVDreg x) -(MOVWreg x:(MULW _ _)) => (MOVDreg x) -(MOVWreg x:(DIVW _ _)) => (MOVDreg x) -(MOVWreg x:(DIVUW _ _)) => (MOVDreg x) -(MOVWreg x:(REMW _ _)) => (MOVDreg x) -(MOVWreg x:(REMUW _ _)) => (MOVDreg x) -(MOVWreg x:(ROLW _ _)) => (MOVDreg x) -(MOVWreg x:(RORW _ _)) => (MOVDreg x) -(MOVWreg x:(RORIW _)) => (MOVDreg x) +// Careful to not omit the sign extension in cases where regalloc +// might restore without it, see issue 80577. +(MOVWreg x:(ADDIW _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) +(MOVWreg x:(SUBW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) +(MOVWreg x:(NEGW _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) +(MOVWreg x:(MULW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) +(MOVWreg x:(DIVW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) +(MOVWreg x:(DIVUW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) +(MOVWreg x:(REMW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) +(MOVWreg x:(REMUW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) +(MOVWreg x:(ROLW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) +(MOVWreg x:(RORW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) +(MOVWreg x:(RORIW _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x) // Fold double extensions. (MOVBreg x:(MOVBreg _)) => (MOVDreg x) @@ -690,36 +692,36 @@ (MOVDnop (MOVDconst [c])) => (MOVDconst [c]) // Avoid unnecessary zero and sign extension when right shifting. -(SRAI [x] (MOVWreg y)) && x >= 0 && x <= 31 => (SRAIW [int64(x)] y) -(SRLI [x] (MOVWUreg y)) && x >= 0 && x <= 31 => (SRLIW [int64(x)] y) +(SRAI [x] (MOVWreg y)) && x >= 0 && x <= 31 => (SRAIW [x] y) +(SRLI [x] (MOVWUreg y)) && x >= 0 && x <= 31 => (SRLIW [x] y) // Replace right shifts that exceed size of signed type. (SRAI [x] (MOVBreg y)) && x >= 8 => (SRAI [63] (SLLI [56] y)) (SRAI [x] (MOVHreg y)) && x >= 16 => (SRAI [63] (SLLI [48] y)) -(SRAI [x] (MOVWreg y)) && x >= 32 => (SRAIW [31] y) +(SRAI [x] (MOVWreg y)) && x >= 32 => (SRAIW [31] y) // Eliminate right shifts that exceed size of unsigned type. -(SRLI [x] (MOVBUreg y)) && x >= 8 => (MOVDconst [0]) -(SRLI [x] (MOVHUreg y)) && x >= 16 => (MOVDconst [0]) -(SRLI [x] (MOVWUreg y)) && x >= 32 => (MOVDconst [0]) +(SRLI [x] (MOVBUreg y)) && x >= 8 => (MOVDconst [0]) +(SRLI [x] (MOVHUreg y)) && x >= 16 => (MOVDconst [0]) +(SRLI [x] (MOVWUreg y)) && x >= 32 => (MOVDconst [0]) // Fold constant into immediate instructions where possible. (ADD (MOVDconst [val]) x) && is32Bit(val) && !t.IsPtr() => (ADDI [val] x) (AND (MOVDconst [val]) x) && is32Bit(val) => (ANDI [val] x) (OR (MOVDconst [val]) x) && is32Bit(val) => (ORI [val] x) (XOR (MOVDconst [val]) x) && is32Bit(val) => (XORI [val] x) -(ROL x (MOVDconst [val])) => (RORI [int64(int8(-val)&63)] x) -(ROLW x (MOVDconst [val])) => (RORIW [int64(int8(-val)&31)] x) -(ROR x (MOVDconst [val])) => (RORI [int64(val&63)] x) -(RORW x (MOVDconst [val])) => (RORIW [int64(val&31)] x) -(SLL x (MOVDconst [val])) => (SLLI [int64(val&63)] x) -(SRL x (MOVDconst [val])) => (SRLI [int64(val&63)] x) -(SLLW x (MOVDconst [val])) => (SLLIW [int64(val&31)] x) -(SRLW x (MOVDconst [val])) => (SRLIW [int64(val&31)] x) -(SRA x (MOVDconst [val])) => (SRAI [int64(val&63)] x) -(SRAW x (MOVDconst [val])) => (SRAIW [int64(val&31)] x) -(SLT x (MOVDconst [val])) && val >= -2048 && val <= 2047 => (SLTI [val] x) -(SLTU x (MOVDconst [val])) && val >= -2048 && val <= 2047 => (SLTIU [val] x) +(ROL x (MOVDconst [val])) => (RORI [-val&63] x) +(ROLW x (MOVDconst [val])) => (RORIW [-val&31] x) +(ROR x (MOVDconst [val])) => (RORI [val&63] x) +(RORW x (MOVDconst [val])) => (RORIW [val&31] x) +(SLL x (MOVDconst [val])) => (SLLI [val&63] x) +(SLLW x (MOVDconst [val])) => (SLLIW [val&31] x) +(SRL x (MOVDconst [val])) => (SRLI [val&63] x) +(SRLW x (MOVDconst [val])) => (SRLIW [val&31] x) +(SRA x (MOVDconst [val])) => (SRAI [val&63] x) +(SRAW x (MOVDconst [val])) => (SRAIW [val&31] x) +(SLT x (MOVDconst [val])) && is12Bit(val) => (SLTI [val] x) +(SLTU x (MOVDconst [val])) && is12Bit(val) => (SLTIU [val] x) // Replace negated left rotation with right rotation. (ROL x (NEG y)) => (ROR x y) @@ -783,7 +785,7 @@ (SRAI [x] (MOVDconst [y])) => (MOVDconst [int64(y) >> uint32(x)]) // Combine doubling via addition with shift. -(SLLI [c] (ADD x x)) && c < t.Size() * 8 - 1 => (SLLI [c+1] x) +(SLLI [c] (ADD x x)) && c < t.Size() * 8 - 1 => (SLLI [c+1] x) (SLLI [c] (ADD x x)) && c >= t.Size() * 8 - 1 => (MOVDconst [0]) // SLTI/SLTIU with constants. @@ -793,7 +795,6 @@ // SLTI/SLTIU with known outcomes. (SLTI [x] (ANDI [y] _)) && y >= 0 && int64(y) < int64(x) => (MOVDconst [1]) (SLTIU [x] (ANDI [y] _)) && y >= 0 && uint64(y) < uint64(x) => (MOVDconst [1]) -(SLTI [x] (ORI [y] _)) && y >= 0 && int64(y) >= int64(x) => (MOVDconst [0]) (SLTIU [x] (ORI [y] _)) && y >= 0 && uint64(y) >= uint64(x) => (MOVDconst [0]) // SLT/SLTU with known outcomes. @@ -824,16 +825,31 @@ (F(MADD|NMADD|MSUB|NMSUB)D x y neg:(FNEGD z)) && neg.Uses == 1 => (F(MSUB|NMSUB|MADD|NMADD)D x y z) // Test for -∞ (bit 0) using 64 bit classify instruction. -(FLTD x (FMVDX (MOVDconst [int64(math.Float64bits(-math.MaxFloat64))]))) => (ANDI [1] (FCLASSD x)) -(FLED (FMVDX (MOVDconst [int64(math.Float64bits(-math.MaxFloat64))])) x) => (SNEZ (ANDI [0xff &^ 1] (FCLASSD x))) -(FEQD x (FMVDX (MOVDconst [int64(math.Float64bits(math.Inf(-1)))]))) => (ANDI [1] (FCLASSD x)) -(FNED x (FMVDX (MOVDconst [int64(math.Float64bits(math.Inf(-1)))]))) => (SEQZ (ANDI [1] (FCLASSD x))) +(FLTD x (FMOVDconst [-math.MaxFloat64])) => (ANDI [0b00_0000_0001] (FCLASSD x)) +(FLED (FMOVDconst [-math.MaxFloat64]) x) => (SNEZ (ANDI [0b00_1111_1110] (FCLASSD x))) +(FEQD x (FMOVDconst [math.Inf(-1)])) => (ANDI [0b00_0000_0001] (FCLASSD x)) +(FNED x (FMOVDconst [math.Inf(-1)])) => (SEQZ (ANDI [0b00_0000_0001] (FCLASSD x))) // Test for +∞ (bit 7) using 64 bit classify instruction. -(FLTD (FMVDX (MOVDconst [int64(math.Float64bits(math.MaxFloat64))])) x) => (SNEZ (ANDI [1<<7] (FCLASSD x))) -(FLED x (FMVDX (MOVDconst [int64(math.Float64bits(math.MaxFloat64))]))) => (SNEZ (ANDI [0xff &^ (1<<7)] (FCLASSD x))) -(FEQD x (FMVDX (MOVDconst [int64(math.Float64bits(math.Inf(1)))]))) => (SNEZ (ANDI [1<<7] (FCLASSD x))) -(FNED x (FMVDX (MOVDconst [int64(math.Float64bits(math.Inf(1)))]))) => (SEQZ (ANDI [1<<7] (FCLASSD x))) +(FLTD (FMOVDconst [math.MaxFloat64]) x) => (SNEZ (ANDI [0b00_1000_0000] (FCLASSD x))) +(FLED x (FMOVDconst [math.MaxFloat64])) => (SNEZ (ANDI [0b00_0111_1111] (FCLASSD x))) +(FEQD x (FMOVDconst [math.Inf(1)])) => (SNEZ (ANDI [0b00_1000_0000] (FCLASSD x))) +(FNED x (FMOVDconst [math.Inf(1)])) => (SEQZ (ANDI [0b00_1000_0000] (FCLASSD x))) + +// Test for subnormal numbers using 64 bit classify instruction. +(FLTD x (FMOVDconst [+0x1p-1022])) => (SNEZ (ANDI [0b00_0011_1111] (FCLASSD x))) +(FLED (FMOVDconst [+0x1p-1022]) x) => (SNEZ (ANDI [0b00_1100_0000] (FCLASSD x))) +(FLED x (FMOVDconst [-0x1p-1022])) => (SNEZ (ANDI [0b00_0000_0011] (FCLASSD x))) +(FLTD (FMOVDconst [-0x1p-1022]) x) => (SNEZ (ANDI [0b00_1111_1100] (FCLASSD x))) + +// Absorb conversion between 32 bit and 64 bit if both src and dst are 32 bit. +(FCVTSD (F(ABS|SQRT)D (FCVTDS X))) => (F(ABS|SQRT)S X) + +// Absorb unary sign bit operations into 64 bit classify instruction. +(S(EQ|NE)Z (ANDI [c] (FCLASSD (FNEGD x)))) => (S(EQ|NE)Z (ANDI [(c&0b11_0000_0000)|int64(bits.Reverse8(uint8(c))&0b1111_1111)] (FCLASSD x))) +(S(EQ|NE)Z (ANDI [c] (FCLASSD (FABSD x)))) => (S(EQ|NE)Z (ANDI [(c&0b11_1111_0000)|int64(bits.Reverse8(uint8(c))&0b0000_1111)] (FCLASSD x))) +(B(EQ|NE)Z (ANDI [c] (FCLASSD (FNEGD x))) yes no) => (B(EQ|NE)Z (ANDI [(c&0b11_0000_0000)|int64(bits.Reverse8(uint8(c))&0b1111_1111)] (FCLASSD x)) yes no) +(B(EQ|NE)Z (ANDI [c] (FCLASSD (FABSD x))) yes no) => (B(EQ|NE)Z (ANDI [(c&0b11_1111_0000)|int64(bits.Reverse8(uint8(c))&0b0000_1111)] (FCLASSD x)) yes no) // // Optimisations for rva22u64 and above. @@ -849,3 +865,23 @@ (Max64 x y) && buildcfg.GORISCV64 >= 22 => (MAX x y) (Min64u x y) && buildcfg.GORISCV64 >= 22 => (MINU x y) (Max64u x y) && buildcfg.GORISCV64 >= 22 => (MAXU x y) + +// Conditional selection (note that these will only be emitted for rva23u64 and above) +(CondSelect x y cond) => + (OR (CZEROEQZ x (MOVBUreg cond)) (CZERONEZ y (MOVBUreg cond))) +(CZERO(EQ|NE)Z x (SNEZ y)) => (CZERO(EQ|NE)Z x y) +(CZERO(EQ|NE)Z x (SEQZ y)) => (CZERO(NE|EQ)Z x y) +(CZERO(EQ|NE)Z x (NEG y)) => (CZERO(EQ|NE)Z x y) +(CZEROEQZ x x) => x +(CZERONEZ x x) => (MOVDconst [0]) +(CZERO(EQ|NE)Z (MOVDconst [0]) _) => (MOVDconst [0]) + +// Optimize conditional arithmetic operations +(OR (CZEROEQZ x cond) (CZERONEZ ((ADD|SUB|OR|XOR|SUBW) x y) cond)) => ((ADD|SUB|OR|XOR|SUBW) x (CZERONEZ y cond)) +(OR (CZEROEQZ ((ADD|SUB|OR|XOR|SUBW) x y) cond) (CZERONEZ x cond)) => ((ADD|SUB|OR|XOR|SUBW) x (CZEROEQZ y cond)) +(OR x:(CZEROEQZ z cond) (CZERONEZ y:(AND z _) cond)) => (OR y x) +(OR (CZEROEQZ x:(AND z _) cond) y:(CZERONEZ z cond)) => (OR x y) +(OR x:(CZEROEQZ z cond) (CZERONEZ y:(ANDI [c] z) cond)) => (OR y x) +(OR (CZEROEQZ x:(ANDI [c] z) cond) y:(CZERONEZ z cond)) => (OR x y) +(OR (CZEROEQZ x cond) (CZERONEZ ((ADDI|ORI|XORI) [c] x) cond)) => ((ADD|OR|XOR) x (CZERONEZ (MOVDconst [c]) cond)) +(OR (CZEROEQZ ((ADDI|ORI|XORI) [c] x) cond) (CZERONEZ x cond)) => ((ADD|OR|XOR) x (CZEROEQZ (MOVDconst [c]) cond)) diff --git a/src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go b/src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go index 99f8f036379e7b..9aaa83533f2962 100644 --- a/src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go +++ b/src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go @@ -57,7 +57,7 @@ func init() { // // If name is specified, use it rather than the riscv reg number. addreg := func(r int, name string) regMask { - mask := regMask(1) << uint(len(regNamesRISCV64)) + mask := regMaskAt(uint(len(regNamesRISCV64))) if name == "" { name = riscv64RegName(r) } @@ -81,20 +81,20 @@ func init() { // ZERO, GP, TP and TMP are not in any gp mask. case riscv64REG_ZERO, riscv64REG_GP, riscv64REG_TP, riscv64REG_TMP: case riscv64REG_G: - gpgMask |= mask - gpspsbgMask |= mask + gpgMask = gpgMask.union(mask) + gpspsbgMask = gpspsbgMask.union(mask) case riscv64REG_SP: - gpspMask |= mask - gpspsbMask |= mask - gpspsbgMask |= mask + gpspMask = gpspMask.union(mask) + gpspsbMask = gpspsbMask.union(mask) + gpspsbgMask = gpspsbgMask.union(mask) default: - gpMask |= mask - gpgMask |= mask - gpspMask |= mask - gpspsbMask |= mask - gpspsbgMask |= mask + gpMask = gpMask.union(mask) + gpgMask = gpgMask.union(mask) + gpspMask = gpspMask.union(mask) + gpspsbMask = gpspsbMask.union(mask) + gpspsbgMask = gpspsbgMask.union(mask) if r >= 5 && r < 5+16 { - first16Mask |= mask + first16Mask = first16Mask.union(mask) } } } @@ -102,13 +102,13 @@ func init() { // Floating point registers. for r := 32; r <= 63; r++ { mask := addreg(r, "") - fpMask |= mask + fpMask = fpMask.union(mask) } // Pseudo-register: SB mask := addreg(-1, "SB") - gpspsbMask |= mask - gpspsbgMask |= mask + gpspsbMask = gpspsbMask.union(mask) + gpspsbgMask = gpspsbgMask.union(mask) if len(regNamesRISCV64) > 64 { // regMask is only 64 bits. @@ -116,200 +116,212 @@ func init() { } regCtxt := regNamed["X26"] - callerSave := gpMask | fpMask | regNamed["g"] - r5toR6 := regNamed["X5"] | regNamed["X6"] + callerSave := gpMask.union(fpMask).union(regNamed["g"]) + r5toR6 := regNamed["X5"].union(regNamed["X6"]) + regX5 := regNamed["X5"] var ( - gpstore = regInfo{inputs: []regMask{gpspsbMask, gpspMask, 0}} // SB in first input so we can load from a global, but not in second to avoid using SB as a temporary register + gpstore = regInfo{inputs: []regMask{gpspsbMask, gpspMask, regMask{}}} // SB in first input so we can load from a global, but not in second to avoid using SB as a temporary register gpstore0 = regInfo{inputs: []regMask{gpspsbMask}} gp01 = regInfo{outputs: []regMask{gpMask}} gp11 = regInfo{inputs: []regMask{gpMask}, outputs: []regMask{gpMask}} gp21 = regInfo{inputs: []regMask{gpMask, gpMask}, outputs: []regMask{gpMask}} gp22 = regInfo{inputs: []regMask{gpMask, gpMask}, outputs: []regMask{gpMask, gpMask}} - gpload = regInfo{inputs: []regMask{gpspsbMask, 0}, outputs: []regMask{gpMask}} + gpload = regInfo{inputs: []regMask{gpspsbMask, regMask{}}, outputs: []regMask{gpMask}} gp11sb = regInfo{inputs: []regMask{gpspsbMask}, outputs: []regMask{gpMask}} gpxchg = regInfo{inputs: []regMask{gpspsbgMask, gpgMask}, outputs: []regMask{gpMask}} gpcas = regInfo{inputs: []regMask{gpspsbgMask, gpgMask, gpgMask}, outputs: []regMask{gpMask}} gpatomic = regInfo{inputs: []regMask{gpspsbgMask, gpgMask}} + fp01 = regInfo{outputs: []regMask{fpMask}} fp11 = regInfo{inputs: []regMask{fpMask}, outputs: []regMask{fpMask}} fp21 = regInfo{inputs: []regMask{fpMask, fpMask}, outputs: []regMask{fpMask}} fp31 = regInfo{inputs: []regMask{fpMask, fpMask, fpMask}, outputs: []regMask{fpMask}} gpfp = regInfo{inputs: []regMask{gpMask}, outputs: []regMask{fpMask}} fpgp = regInfo{inputs: []regMask{fpMask}, outputs: []regMask{gpMask}} - fpstore = regInfo{inputs: []regMask{gpspsbMask, fpMask, 0}} - fpload = regInfo{inputs: []regMask{gpspsbMask, 0}, outputs: []regMask{fpMask}} + fpstore = regInfo{inputs: []regMask{gpspsbMask, fpMask, regMask{}}} + fpload = regInfo{inputs: []regMask{gpspsbMask, regMask{}}, outputs: []regMask{fpMask}} fp2gp = regInfo{inputs: []regMask{fpMask, fpMask}, outputs: []regMask{gpMask}} - call = regInfo{clobbers: callerSave} - callClosure = regInfo{inputs: []regMask{gpspMask, regCtxt, 0}, clobbers: callerSave} - callInter = regInfo{inputs: []regMask{gpMask}, clobbers: callerSave} + call = regInfo{clobbers: callerSave} + // Avoid using X5 as the source register of calls. Using X5 here triggers + // RAS pop-then-push behavior which is not correct for function calls. + // Please refer to section 2.5.1 of the RISC-V ISA + // (https://docs.riscv.org/reference/isa/unpriv/rv32.html#rashints) for details. + callClosure = regInfo{inputs: []regMask{gpspMask.minus(regX5), regCtxt, regMask{}}, clobbers: callerSave} + callInter = regInfo{inputs: []regMask{gpMask.minus(regX5)}, clobbers: callerSave} ) RISCV64ops := []opData{ - {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1 - {name: "ADDI", argLength: 1, reg: gp11sb, asm: "ADDI", aux: "Int64"}, // arg0 + auxint - {name: "ADDIW", argLength: 1, reg: gp11, asm: "ADDIW", aux: "Int64"}, // 32 low bits of arg0 + auxint, sign extended to 64 bits - {name: "NEG", argLength: 1, reg: gp11, asm: "NEG"}, // -arg0 - {name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"}, // -arg0 of 32 bits, sign extended to 64 bits - {name: "SUB", argLength: 2, reg: gp21, asm: "SUB"}, // arg0 - arg1 - {name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW"}, // 32 low bits of arg 0 - 32 low bits of arg 1, sign extended to 64 bits + {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDI", argLength: 1, reg: gp11sb, asm: "ADDI", aux: "Int64", earlyOk: true}, // arg0 + auxint + {name: "ADDIW", argLength: 1, reg: gp11, asm: "ADDIW", aux: "Int64", earlyOk: true}, // 32 low bits of arg0 + auxint, sign extended to 64 bits + {name: "NEG", argLength: 1, reg: gp11, asm: "NEG", earlyOk: true}, // -arg0 + {name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW", earlyOk: true}, // -arg0 of 32 bits, sign extended to 64 bits + {name: "SUB", argLength: 2, reg: gp21, asm: "SUB", earlyOk: true}, // arg0 - arg1 + {name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW", earlyOk: true}, // 32 low bits of arg 0 - 32 low bits of arg 1, sign extended to 64 bits // M extension. H means high (i.e., it returns the top bits of // the result). U means unsigned. W means word (i.e., 32-bit). - {name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true, typ: "Int64"}, // arg0 * arg1 - {name: "MULW", argLength: 2, reg: gp21, asm: "MULW", commutative: true, typ: "Int32"}, - {name: "MULH", argLength: 2, reg: gp21, asm: "MULH", commutative: true, typ: "Int64"}, - {name: "MULHU", argLength: 2, reg: gp21, asm: "MULHU", commutative: true, typ: "UInt64"}, - {name: "LoweredMuluhilo", argLength: 2, reg: gp22, resultNotInArgs: true}, // arg0 * arg1, return (hi, lo) - {name: "LoweredMuluover", argLength: 2, reg: gp22, resultNotInArgs: true}, // arg0 * arg1, return (64 bits of arg0*arg1, overflow) - - {name: "DIV", argLength: 2, reg: gp21, asm: "DIV", typ: "Int64"}, // arg0 / arg1 - {name: "DIVU", argLength: 2, reg: gp21, asm: "DIVU", typ: "UInt64"}, - {name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"}, - {name: "DIVUW", argLength: 2, reg: gp21, asm: "DIVUW", typ: "UInt32"}, - {name: "REM", argLength: 2, reg: gp21, asm: "REM", typ: "Int64"}, // arg0 % arg1 - {name: "REMU", argLength: 2, reg: gp21, asm: "REMU", typ: "UInt64"}, - {name: "REMW", argLength: 2, reg: gp21, asm: "REMW", typ: "Int32"}, - {name: "REMUW", argLength: 2, reg: gp21, asm: "REMUW", typ: "UInt32"}, - - {name: "MOVaddr", argLength: 1, reg: gp11sb, asm: "MOV", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux + {name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true, typ: "Int64", earlyOk: true}, // arg0 * arg1 + {name: "MULW", argLength: 2, reg: gp21, asm: "MULW", commutative: true, typ: "Int32", earlyOk: true}, + {name: "MULH", argLength: 2, reg: gp21, asm: "MULH", commutative: true, typ: "Int64", earlyOk: true}, + {name: "MULHU", argLength: 2, reg: gp21, asm: "MULHU", commutative: true, typ: "UInt64", earlyOk: true}, + {name: "LoweredMuluhilo", argLength: 2, reg: gp22, resultNotInArgs: true, earlyOk: true}, // arg0 * arg1, return (hi, lo) + {name: "LoweredMuluover", argLength: 2, reg: gp22, resultNotInArgs: true, earlyOk: true}, // arg0 * arg1, return (64 bits of arg0*arg1, overflow) + + {name: "DIV", argLength: 2, reg: gp21, asm: "DIV", typ: "Int64", earlyOk: true}, // arg0 / arg1 + {name: "DIVU", argLength: 2, reg: gp21, asm: "DIVU", typ: "UInt64", earlyOk: true}, + {name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32", earlyOk: true}, + {name: "DIVUW", argLength: 2, reg: gp21, asm: "DIVUW", typ: "UInt32", earlyOk: true}, + {name: "REM", argLength: 2, reg: gp21, asm: "REM", typ: "Int64", earlyOk: true}, // arg0 % arg1 + {name: "REMU", argLength: 2, reg: gp21, asm: "REMU", typ: "UInt64", earlyOk: true}, + {name: "REMW", argLength: 2, reg: gp21, asm: "REMW", typ: "Int32", earlyOk: true}, + {name: "REMUW", argLength: 2, reg: gp21, asm: "REMUW", typ: "UInt32", earlyOk: true}, + + {name: "MOVaddr", argLength: 1, reg: gp11sb, asm: "MOV", aux: "SymOff", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxint + offset encoded in aux // auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address - {name: "MOVDconst", reg: gp01, asm: "MOV", typ: "UInt64", aux: "Int64", rematerializeable: true}, // auxint + {name: "MOVDconst", reg: gp01, asm: "MOV", typ: "UInt64", aux: "Int64", rematerializeable: true, earlyOk: true}, // auxint + {name: "FMOVDconst", reg: fp01, asm: "MOVD", typ: "Float64", aux: "Float64", rematerializeable: true, earlyOk: true}, // auxint + {name: "FMOVFconst", reg: fp01, asm: "MOVF", typ: "Float32", aux: "Float32", rematerializeable: true, earlyOk: true}, // auxint // Loads: load bits from arg0+auxint+aux and extend to 64 bits; arg1=mem - {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVB", aux: "SymOff", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"}, // 8 bits, sign extend - {name: "MOVHload", argLength: 2, reg: gpload, asm: "MOVH", aux: "SymOff", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"}, // 16 bits, sign extend - {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"}, // 32 bits, sign extend - {name: "MOVDload", argLength: 2, reg: gpload, asm: "MOV", aux: "SymOff", typ: "Int64", faultOnNilArg0: true, symEffect: "Read"}, // 64 bits - {name: "MOVBUload", argLength: 2, reg: gpload, asm: "MOVBU", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // 8 bits, zero extend - {name: "MOVHUload", argLength: 2, reg: gpload, asm: "MOVHU", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // 16 bits, zero extend - {name: "MOVWUload", argLength: 2, reg: gpload, asm: "MOVWU", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // 32 bits, zero extend + {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVB", aux: "SymOff", typ: "Int8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // 8 bits, sign extend + {name: "MOVHload", argLength: 2, reg: gpload, asm: "MOVH", aux: "SymOff", typ: "Int16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // 16 bits, sign extend + {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", typ: "Int32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // 32 bits, sign extend + {name: "MOVDload", argLength: 2, reg: gpload, asm: "MOV", aux: "SymOff", typ: "Int64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // 64 bits + {name: "MOVBUload", argLength: 2, reg: gpload, asm: "MOVBU", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // 8 bits, zero extend + {name: "MOVHUload", argLength: 2, reg: gpload, asm: "MOVHU", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // 16 bits, zero extend + {name: "MOVWUload", argLength: 2, reg: gpload, asm: "MOVWU", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // 32 bits, zero extend // Stores: store lowest bits in arg1 to arg0+auxint+aux; arg2=mem - {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 8 bits - {name: "MOVHstore", argLength: 3, reg: gpstore, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 16 bits - {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 32 bits - {name: "MOVDstore", argLength: 3, reg: gpstore, asm: "MOV", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 64 bits + {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // 8 bits + {name: "MOVHstore", argLength: 3, reg: gpstore, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // 16 bits + {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // 32 bits + {name: "MOVDstore", argLength: 3, reg: gpstore, asm: "MOV", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // 64 bits // Stores: store of zero in arg0+auxint+aux; arg1=mem - {name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 8 bits - {name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 16 bits - {name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 32 bits - {name: "MOVDstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 64 bits + {name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // 8 bits + {name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // 16 bits + {name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // 32 bits + {name: "MOVDstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // 64 bits // Conversions - {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte - {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"}, // move from arg0, sign-extended from half - {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"}, // move from arg0, sign-extended from word - {name: "MOVDreg", argLength: 1, reg: gp11, asm: "MOV"}, // move from arg0 - {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte - {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half - {name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU"}, // move from arg0, unsign-extended from word + {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB", earlyOk: true}, // move from arg0, sign-extended from byte + {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH", earlyOk: true}, // move from arg0, sign-extended from half + {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW", earlyOk: true}, // move from arg0, sign-extended from word + {name: "MOVDreg", argLength: 1, reg: gp11, asm: "MOV", earlyOk: true}, // move from arg0 + {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU", earlyOk: true}, // move from arg0, unsign-extended from byte + {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU", earlyOk: true}, // move from arg0, unsign-extended from half + {name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU", earlyOk: true}, // move from arg0, unsign-extended from word - {name: "MOVDnop", argLength: 1, reg: regInfo{inputs: []regMask{gpMask}, outputs: []regMask{gpMask}}, resultInArg0: true}, // nop, return arg0 in same register + {name: "MOVDnop", argLength: 1, reg: regInfo{inputs: []regMask{gpMask}, outputs: []regMask{gpMask}}, resultInArg0: true, earlyOk: true}, // nop, return arg0 in same register // Shift ops - {name: "SLL", argLength: 2, reg: gp21, asm: "SLL"}, // arg0 << (aux1 & 63), logical left shift - {name: "SLLW", argLength: 2, reg: gp21, asm: "SLLW"}, // arg0 << (aux1 & 31), logical left shift of 32 bit value, sign extended to 64 bits - {name: "SRA", argLength: 2, reg: gp21, asm: "SRA"}, // arg0 >> (aux1 & 63), arithmetic right shift - {name: "SRAW", argLength: 2, reg: gp21, asm: "SRAW"}, // arg0 >> (aux1 & 31), arithmetic right shift of 32 bit value, sign extended to 64 bits - {name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> (aux1 & 63), logical right shift - {name: "SRLW", argLength: 2, reg: gp21, asm: "SRLW"}, // arg0 >> (aux1 & 31), logical right shift of 32 bit value, sign extended to 64 bits - {name: "SLLI", argLength: 1, reg: gp11, asm: "SLLI", aux: "Int64"}, // arg0 << auxint, shift amount 0-63, logical left shift - {name: "SLLIW", argLength: 1, reg: gp11, asm: "SLLIW", aux: "Int64"}, // arg0 << auxint, shift amount 0-31, logical left shift of 32 bit value, sign extended to 64 bits - {name: "SRAI", argLength: 1, reg: gp11, asm: "SRAI", aux: "Int64"}, // arg0 >> auxint, shift amount 0-63, arithmetic right shift - {name: "SRAIW", argLength: 1, reg: gp11, asm: "SRAIW", aux: "Int64"}, // arg0 >> auxint, shift amount 0-31, arithmetic right shift of 32 bit value, sign extended to 64 bits - {name: "SRLI", argLength: 1, reg: gp11, asm: "SRLI", aux: "Int64"}, // arg0 >> auxint, shift amount 0-63, logical right shift - {name: "SRLIW", argLength: 1, reg: gp11, asm: "SRLIW", aux: "Int64"}, // arg0 >> auxint, shift amount 0-31, logical right shift of 32 bit value, sign extended to 64 bits + {name: "SLL", argLength: 2, reg: gp21, asm: "SLL", earlyOk: true}, // arg0 << (aux1 & 63), logical left shift + {name: "SLLW", argLength: 2, reg: gp21, asm: "SLLW", earlyOk: true}, // arg0 << (aux1 & 31), logical left shift of 32 bit value, sign extended to 64 bits + {name: "SRA", argLength: 2, reg: gp21, asm: "SRA", earlyOk: true}, // arg0 >> (aux1 & 63), arithmetic right shift + {name: "SRAW", argLength: 2, reg: gp21, asm: "SRAW", earlyOk: true}, // arg0 >> (aux1 & 31), arithmetic right shift of 32 bit value, sign extended to 64 bits + {name: "SRL", argLength: 2, reg: gp21, asm: "SRL", earlyOk: true}, // arg0 >> (aux1 & 63), logical right shift + {name: "SRLW", argLength: 2, reg: gp21, asm: "SRLW", earlyOk: true}, // arg0 >> (aux1 & 31), logical right shift of 32 bit value, sign extended to 64 bits + {name: "SLLI", argLength: 1, reg: gp11, asm: "SLLI", aux: "Int64", earlyOk: true}, // arg0 << auxint, shift amount 0-63, logical left shift + {name: "SLLIW", argLength: 1, reg: gp11, asm: "SLLIW", aux: "Int64", earlyOk: true}, // arg0 << auxint, shift amount 0-31, logical left shift of 32 bit value, sign extended to 64 bits + {name: "SRAI", argLength: 1, reg: gp11, asm: "SRAI", aux: "Int64", earlyOk: true}, // arg0 >> auxint, shift amount 0-63, arithmetic right shift + {name: "SRAIW", argLength: 1, reg: gp11, asm: "SRAIW", aux: "Int64", earlyOk: true}, // arg0 >> auxint, shift amount 0-31, arithmetic right shift of 32 bit value, sign extended to 64 bits + {name: "SRLI", argLength: 1, reg: gp11, asm: "SRLI", aux: "Int64", earlyOk: true}, // arg0 >> auxint, shift amount 0-63, logical right shift + {name: "SRLIW", argLength: 1, reg: gp11, asm: "SRLIW", aux: "Int64", earlyOk: true}, // arg0 >> auxint, shift amount 0-31, logical right shift of 32 bit value, sign extended to 64 bits // Shift and add - {name: "SH1ADD", argLength: 2, reg: gp21, asm: "SH1ADD"}, // arg0 << 1 + arg1 - {name: "SH2ADD", argLength: 2, reg: gp21, asm: "SH2ADD"}, // arg0 << 2 + arg1 - {name: "SH3ADD", argLength: 2, reg: gp21, asm: "SH3ADD"}, // arg0 << 3 + arg1 + {name: "SH1ADD", argLength: 2, reg: gp21, asm: "SH1ADD", earlyOk: true}, // arg0 << 1 + arg1 + {name: "SH2ADD", argLength: 2, reg: gp21, asm: "SH2ADD", earlyOk: true}, // arg0 << 2 + arg1 + {name: "SH3ADD", argLength: 2, reg: gp21, asm: "SH3ADD", earlyOk: true}, // arg0 << 3 + arg1 // Bitwise ops - {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1 - {name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN"}, // ^arg0 & arg1 - {name: "ANDI", argLength: 1, reg: gp11, asm: "ANDI", aux: "Int64"}, // arg0 & auxint - {name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ"}, // count leading zeros - {name: "CLZW", argLength: 1, reg: gp11, asm: "CLZW"}, // count leading zeros of least significant word - {name: "CPOP", argLength: 1, reg: gp11, asm: "CPOP"}, // count set bits - {name: "CPOPW", argLength: 1, reg: gp11, asm: "CPOPW"}, // count set bits in least significant word - {name: "CTZ", argLength: 1, reg: gp11, asm: "CTZ"}, // count trailing zeros - {name: "CTZW", argLength: 1, reg: gp11, asm: "CTZW"}, // count trailing zeros of least significant word - {name: "NOT", argLength: 1, reg: gp11, asm: "NOT"}, // ^arg0 - {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0 | arg1 - {name: "ORN", argLength: 2, reg: gp21, asm: "ORN"}, // ^arg0 | arg1 - {name: "ORI", argLength: 1, reg: gp11, asm: "ORI", aux: "Int64"}, // arg0 | auxint - {name: "REV8", argLength: 1, reg: gp11, asm: "REV8"}, // reverse bytes - {name: "ROL", argLength: 2, reg: gp21, asm: "ROL"}, // rotate left arg0 by (arg1 & 63) - {name: "ROLW", argLength: 2, reg: gp21, asm: "ROLW"}, // rotate left least significant word of arg0 by (arg1 & 31), sign extended - {name: "ROR", argLength: 2, reg: gp21, asm: "ROR"}, // rotate right arg0 by (arg1 & 63) - {name: "RORI", argLength: 1, reg: gp11, asm: "RORI", aux: "Int64"}, // rotate right arg0 by auxint, shift amount 0-63 - {name: "RORIW", argLength: 1, reg: gp11, asm: "RORIW", aux: "Int64"}, // rotate right least significant word of arg0 by auxint, shift amount 0-31, sign extended - {name: "RORW", argLength: 2, reg: gp21, asm: "RORW"}, // rotate right least significant word of arg0 by (arg1 & 31), sign extended - {name: "XNOR", argLength: 2, reg: gp21, asm: "XNOR", commutative: true}, // ^(arg0 ^ arg1) - {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true}, // arg0 ^ arg1 - {name: "XORI", argLength: 1, reg: gp11, asm: "XORI", aux: "Int64"}, // arg0 ^ auxint + // CPOP/CPOPW need to check for zbb first + {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN", earlyOk: true}, // ^arg0 & arg1 + {name: "ANDI", argLength: 1, reg: gp11, asm: "ANDI", aux: "Int64", earlyOk: true}, // arg0 & auxint + {name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ", earlyOk: true}, // count leading zeros + {name: "CLZW", argLength: 1, reg: gp11, asm: "CLZW", earlyOk: true}, // count leading zeros of least significant word + {name: "CPOP", argLength: 1, reg: gp11, asm: "CPOP"}, // count set bits + {name: "CPOPW", argLength: 1, reg: gp11, asm: "CPOPW"}, // count set bits in least significant word + {name: "CTZ", argLength: 1, reg: gp11, asm: "CTZ", earlyOk: true}, // count trailing zeros + {name: "CTZW", argLength: 1, reg: gp11, asm: "CTZW", earlyOk: true}, // count trailing zeros of least significant word + {name: "NOT", argLength: 1, reg: gp11, asm: "NOT", earlyOk: true}, // ^arg0 + {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true, earlyOk: true}, // arg0 | arg1 + {name: "ORN", argLength: 2, reg: gp21, asm: "ORN", earlyOk: true}, // ^arg0 | arg1 + {name: "ORI", argLength: 1, reg: gp11, asm: "ORI", aux: "Int64", earlyOk: true}, // arg0 | auxint + {name: "REV8", argLength: 1, reg: gp11, asm: "REV8", earlyOk: true}, // reverse bytes + {name: "ROL", argLength: 2, reg: gp21, asm: "ROL", earlyOk: true}, // rotate left arg0 by (arg1 & 63) + {name: "ROLW", argLength: 2, reg: gp21, asm: "ROLW", earlyOk: true}, // rotate left least significant word of arg0 by (arg1 & 31), sign extended + {name: "ROR", argLength: 2, reg: gp21, asm: "ROR", earlyOk: true}, // rotate right arg0 by (arg1 & 63) + {name: "RORI", argLength: 1, reg: gp11, asm: "RORI", aux: "Int64", earlyOk: true}, // rotate right arg0 by auxint, shift amount 0-63 + {name: "RORIW", argLength: 1, reg: gp11, asm: "RORIW", aux: "Int64", earlyOk: true}, // rotate right least significant word of arg0 by auxint, shift amount 0-31, sign extended + {name: "RORW", argLength: 2, reg: gp21, asm: "RORW", earlyOk: true}, // rotate right least significant word of arg0 by (arg1 & 31), sign extended + {name: "XNOR", argLength: 2, reg: gp21, asm: "XNOR", commutative: true, earlyOk: true}, // ^(arg0 ^ arg1) + {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, earlyOk: true}, // arg0 ^ arg1 + {name: "XORI", argLength: 1, reg: gp11, asm: "XORI", aux: "Int64", earlyOk: true}, // arg0 ^ auxint // Minimum and maximum - {name: "MIN", argLength: 2, reg: gp21, asm: "MIN", commutative: true}, // min(arg0,arg1), signed - {name: "MAX", argLength: 2, reg: gp21, asm: "MAX", commutative: true}, // max(arg0,arg1), signed - {name: "MINU", argLength: 2, reg: gp21, asm: "MINU", commutative: true}, // min(arg0,arg1), unsigned - {name: "MAXU", argLength: 2, reg: gp21, asm: "MAXU", commutative: true}, // max(arg0,arg1), unsigned + {name: "MIN", argLength: 2, reg: gp21, asm: "MIN", commutative: true, earlyOk: true}, // min(arg0,arg1), signed + {name: "MAX", argLength: 2, reg: gp21, asm: "MAX", commutative: true, earlyOk: true}, // max(arg0,arg1), signed + {name: "MINU", argLength: 2, reg: gp21, asm: "MINU", commutative: true, earlyOk: true}, // min(arg0,arg1), unsigned + {name: "MAXU", argLength: 2, reg: gp21, asm: "MAXU", commutative: true, earlyOk: true}, // max(arg0,arg1), unsigned // Generate boolean values - {name: "SEQZ", argLength: 1, reg: gp11, asm: "SEQZ"}, // arg0 == 0, result is 0 or 1 - {name: "SNEZ", argLength: 1, reg: gp11, asm: "SNEZ"}, // arg0 != 0, result is 0 or 1 - {name: "SLT", argLength: 2, reg: gp21, asm: "SLT"}, // arg0 < arg1, result is 0 or 1 - {name: "SLTI", argLength: 1, reg: gp11, asm: "SLTI", aux: "Int64"}, // arg0 < auxint, result is 0 or 1 - {name: "SLTU", argLength: 2, reg: gp21, asm: "SLTU"}, // arg0 < arg1, unsigned, result is 0 or 1 - {name: "SLTIU", argLength: 1, reg: gp11, asm: "SLTIU", aux: "Int64"}, // arg0 < auxint, unsigned, result is 0 or 1 + {name: "SEQZ", argLength: 1, reg: gp11, asm: "SEQZ", earlyOk: true}, // arg0 == 0, result is 0 or 1 + {name: "SNEZ", argLength: 1, reg: gp11, asm: "SNEZ", earlyOk: true}, // arg0 != 0, result is 0 or 1 + {name: "SLT", argLength: 2, reg: gp21, asm: "SLT", earlyOk: true}, // arg0 < arg1, result is 0 or 1 + {name: "SLTI", argLength: 1, reg: gp11, asm: "SLTI", aux: "Int64", earlyOk: true}, // arg0 < auxint, result is 0 or 1 + {name: "SLTU", argLength: 2, reg: gp21, asm: "SLTU", earlyOk: true}, // arg0 < arg1, unsigned, result is 0 or 1 + {name: "SLTIU", argLength: 1, reg: gp11, asm: "SLTIU", aux: "Int64", earlyOk: true}, // arg0 < auxint, unsigned, result is 0 or 1 // Round ops to block fused-multiply-add extraction. - {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true}, - {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true}, + {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true, earlyOk: true}, + {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true, earlyOk: true}, // Calls - {name: "CALLstatic", argLength: -1, reg: call, aux: "CallOff", call: true}, // call static function aux.(*gc.Sym). last arg=mem, auxint=argsize, returns mem - {name: "CALLtail", argLength: -1, reg: call, aux: "CallOff", call: true, tailCall: true}, // tail call static function aux.(*gc.Sym). last arg=mem, auxint=argsize, returns mem - {name: "CALLclosure", argLength: -1, reg: callClosure, aux: "CallOff", call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem - {name: "CALLinter", argLength: -1, reg: callInter, aux: "CallOff", call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + {name: "CALLstatic", argLength: -1, reg: call, aux: "CallOff", call: true}, // call static function aux.(*gc.Sym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtail", argLength: -1, reg: call, aux: "CallOff", call: true, tailCall: true}, // tail call static function aux.(*gc.Sym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtailinter", argLength: -1, reg: callInter, aux: "CallOff", call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: -1, reg: callClosure, aux: "CallOff", call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: -1, reg: callInter, aux: "CallOff", call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem // Generic moves and zeros // general unrolled zeroing // arg0 = address of memory to zero // arg1 = mem - // auxint = element size and type alignment + // auxint = size + // aux = alignment (as an int64) // returns mem // mov ZERO, (OFFSET)(Rarg0) { name: "LoweredZero", - aux: "SymValAndOff", + aux: "SizeAndAlign", typ: "Mem", argLength: 2, - symEffect: "Write", faultOnNilArg0: true, + addrSinkArg0: true, reg: regInfo{ inputs: []regMask{gpMask}, }, }, // general unaligned zeroing // arg0 = address of memory to zero (clobber) - // arg2 = mem - // auxint = element size and type alignment + // arg1 = mem + // auxint = size + // aux = alignment (as an int64) // returns mem { name: "LoweredZeroLoop", - aux: "SymValAndOff", + aux: "SizeAndAlign", typ: "Mem", argLength: 2, - symEffect: "Write", needIntTemp: true, faultOnNilArg0: true, + addrSinkArg0: true, reg: regInfo{ inputs: []regMask{gpMask}, clobbersArg0: true, @@ -320,28 +332,31 @@ func init() { // arg0 = address of dst memory (clobber) // arg1 = address of src memory (clobber) // arg2 = mem - // auxint = size and type alignment + // auxint = size + // aux = alignment (as an int64) // returns mem // mov (offset)(Rarg1), TMP // mov TMP, (offset)(Rarg0) { name: "LoweredMove", - aux: "SymValAndOff", - symEffect: "Write", + aux: "SizeAndAlign", argLength: 3, reg: regInfo{ - inputs: []regMask{gpMask &^ regNamed["X5"], gpMask &^ regNamed["X5"]}, + inputs: []regMask{gpMask.minus(regNamed["X5"]), gpMask.minus(regNamed["X5"])}, clobbers: regNamed["X5"], }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // general unaligned move // arg0 = address of dst memory (clobber) // arg1 = address of src memory (clobber) - // arg3 = mem - // auxint = alignment + // arg2 = mem + // auxint = size + // aux = alignment (as an int64) // returns mem // ADD $sz, X6 //loop: @@ -353,17 +368,18 @@ func init() { // BNE X6, Rarg1, loop { name: "LoweredMoveLoop", - aux: "SymValAndOff", + aux: "SizeAndAlign", argLength: 3, - symEffect: "Write", reg: regInfo{ - inputs: []regMask{gpMask &^ r5toR6, gpMask &^ r5toR6}, + inputs: []regMask{gpMask.minus(r5toR6), gpMask.minus(r5toR6)}, clobbers: r5toR6, clobbersArg0: true, clobbersArg1: true, }, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, }, // Atomic loads. @@ -429,7 +445,7 @@ func init() { // but clobbers RA (LR) because it's a call // and T6 (REG_TMP). // Returns a pointer to a write barrier buffer in X24. - {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ (gpMask | regNamed["g"])) | regNamed["X1"], outputs: []regMask{regNamed["X24"]}}, clobberFlags: true, aux: "Int64"}, + {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave.minus(gpMask.union(regNamed["g"])).union(regNamed["X1"]), outputs: []regMask{regNamed["X24"]}}, clobberFlags: true, aux: "Int64"}, // Do data barrier. arg0=memorys {name: "LoweredPubBarrier", argLength: 1, asm: "FENCE", hasSideEffects: true}, @@ -445,60 +461,61 @@ func init() { {name: "LoweredPanicBoundsCC", argLength: 1, aux: "PanicBoundsCC", reg: regInfo{}, typ: "Mem", call: true}, // arg0=mem, returns memory. // F extension. - {name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true, typ: "Float32"}, // arg0 + arg1 - {name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS", commutative: false, typ: "Float32"}, // arg0 - arg1 - {name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true, typ: "Float32"}, // arg0 * arg1 - {name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS", commutative: false, typ: "Float32"}, // arg0 / arg1 - {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS", commutative: true, typ: "Float32"}, // (arg0 * arg1) + arg2 - {name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS", commutative: true, typ: "Float32"}, // (arg0 * arg1) - arg2 - {name: "FNMADDS", argLength: 3, reg: fp31, asm: "FNMADDS", commutative: true, typ: "Float32"}, // -(arg0 * arg1) + arg2 - {name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS", commutative: true, typ: "Float32"}, // -(arg0 * arg1) - arg2 - {name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS", typ: "Float32"}, // sqrt(arg0) - {name: "FNEGS", argLength: 1, reg: fp11, asm: "FNEGS", typ: "Float32"}, // -arg0 - {name: "FMVSX", argLength: 1, reg: gpfp, asm: "FMVSX", typ: "Float32"}, // reinterpret arg0 as float32 - {name: "FMVXS", argLength: 1, reg: fpgp, asm: "FMVXS", typ: "Int32"}, // reinterpret arg0 as int32, sign extended to 64 bits - {name: "FCVTSW", argLength: 1, reg: gpfp, asm: "FCVTSW", typ: "Float32"}, // float32(low 32 bits of arg0) - {name: "FCVTSL", argLength: 1, reg: gpfp, asm: "FCVTSL", typ: "Float32"}, // float32(arg0) - {name: "FCVTWS", argLength: 1, reg: fpgp, asm: "FCVTWS", typ: "Int32"}, // int32(arg0) - {name: "FCVTLS", argLength: 1, reg: fpgp, asm: "FCVTLS", typ: "Int64"}, // int64(arg0) - {name: "FMOVWload", argLength: 2, reg: fpload, asm: "MOVF", aux: "SymOff", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load float32 from arg0+auxint+aux - {name: "FMOVWstore", argLength: 3, reg: fpstore, asm: "MOVF", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store float32 to arg0+auxint+aux - {name: "FEQS", argLength: 2, reg: fp2gp, asm: "FEQS", commutative: true}, // arg0 == arg1 - {name: "FNES", argLength: 2, reg: fp2gp, asm: "FNES", commutative: true}, // arg0 != arg1 - {name: "FLTS", argLength: 2, reg: fp2gp, asm: "FLTS"}, // arg0 < arg1 - {name: "FLES", argLength: 2, reg: fp2gp, asm: "FLES"}, // arg0 <= arg1 - {name: "LoweredFMAXS", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXS", commutative: true, typ: "Float32"}, // max(arg0, arg1) - {name: "LoweredFMINS", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMINS", commutative: true, typ: "Float32"}, // min(arg0, arg1) + {name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true, typ: "Float32", earlyOk: true}, // arg0 + arg1 + {name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS", commutative: false, typ: "Float32", earlyOk: true}, // arg0 - arg1 + {name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true, typ: "Float32", earlyOk: true}, // arg0 * arg1 + {name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS", commutative: false, typ: "Float32", earlyOk: true}, // arg0 / arg1 + {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS", commutative: true, typ: "Float32", earlyOk: true}, // (arg0 * arg1) + arg2 + {name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS", commutative: true, typ: "Float32", earlyOk: true}, // (arg0 * arg1) - arg2 + {name: "FNMADDS", argLength: 3, reg: fp31, asm: "FNMADDS", commutative: true, typ: "Float32", earlyOk: true}, // -(arg0 * arg1) + arg2 + {name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS", commutative: true, typ: "Float32", earlyOk: true}, // -(arg0 * arg1) - arg2 + {name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS", typ: "Float32", earlyOk: true}, // sqrt(arg0) + {name: "FABSS", argLength: 1, reg: fp11, asm: "FABSS", typ: "Float32", earlyOk: true}, // abs(arg0) + {name: "FNEGS", argLength: 1, reg: fp11, asm: "FNEGS", typ: "Float32", earlyOk: true}, // -arg0 + {name: "FMVSX", argLength: 1, reg: gpfp, asm: "FMVSX", typ: "Float32", earlyOk: true}, // reinterpret arg0 as float32 + {name: "FMVXS", argLength: 1, reg: fpgp, asm: "FMVXS", typ: "Int32", earlyOk: true}, // reinterpret arg0 as int32, sign extended to 64 bits + {name: "FCVTSW", argLength: 1, reg: gpfp, asm: "FCVTSW", typ: "Float32", earlyOk: true}, // float32(low 32 bits of arg0) + {name: "FCVTSL", argLength: 1, reg: gpfp, asm: "FCVTSL", typ: "Float32", earlyOk: true}, // float32(arg0) + {name: "FCVTWS", argLength: 1, reg: fpgp, asm: "FCVTWS", typ: "Int32", earlyOk: true}, // int32(arg0) + {name: "FCVTLS", argLength: 1, reg: fpgp, asm: "FCVTLS", typ: "Int64", earlyOk: true}, // int64(arg0) + {name: "FMOVWload", argLength: 2, reg: fpload, asm: "MOVF", aux: "SymOff", typ: "Float32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load float32 from arg0+auxint+aux + {name: "FMOVWstore", argLength: 3, reg: fpstore, asm: "MOVF", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store float32 to arg0+auxint+aux + {name: "FEQS", argLength: 2, reg: fp2gp, asm: "FEQS", commutative: true, earlyOk: true}, // arg0 == arg1 + {name: "FNES", argLength: 2, reg: fp2gp, asm: "FNES", commutative: true, earlyOk: true}, // arg0 != arg1 + {name: "FLTS", argLength: 2, reg: fp2gp, asm: "FLTS", earlyOk: true}, // arg0 < arg1 + {name: "FLES", argLength: 2, reg: fp2gp, asm: "FLES", earlyOk: true}, // arg0 <= arg1 + {name: "LoweredFMAXS", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXS", commutative: true, typ: "Float32", earlyOk: true}, // max(arg0, arg1) + {name: "LoweredFMINS", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMINS", commutative: true, typ: "Float32", earlyOk: true}, // min(arg0, arg1) // D extension. - {name: "FADDD", argLength: 2, reg: fp21, asm: "FADDD", commutative: true, typ: "Float64"}, // arg0 + arg1 - {name: "FSUBD", argLength: 2, reg: fp21, asm: "FSUBD", commutative: false, typ: "Float64"}, // arg0 - arg1 - {name: "FMULD", argLength: 2, reg: fp21, asm: "FMULD", commutative: true, typ: "Float64"}, // arg0 * arg1 - {name: "FDIVD", argLength: 2, reg: fp21, asm: "FDIVD", commutative: false, typ: "Float64"}, // arg0 / arg1 - {name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", commutative: true, typ: "Float64"}, // (arg0 * arg1) + arg2 - {name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", commutative: true, typ: "Float64"}, // (arg0 * arg1) - arg2 - {name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD", commutative: true, typ: "Float64"}, // -(arg0 * arg1) + arg2 - {name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD", commutative: true, typ: "Float64"}, // -(arg0 * arg1) - arg2 - {name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD", typ: "Float64"}, // sqrt(arg0) - {name: "FNEGD", argLength: 1, reg: fp11, asm: "FNEGD", typ: "Float64"}, // -arg0 - {name: "FABSD", argLength: 1, reg: fp11, asm: "FABSD", typ: "Float64"}, // abs(arg0) - {name: "FSGNJD", argLength: 2, reg: fp21, asm: "FSGNJD", typ: "Float64"}, // copy sign of arg1 to arg0 - {name: "FMVDX", argLength: 1, reg: gpfp, asm: "FMVDX", typ: "Float64"}, // reinterpret arg0 as float64 - {name: "FMVXD", argLength: 1, reg: fpgp, asm: "FMVXD", typ: "Int64"}, // reinterpret arg0 as int64 - {name: "FCVTDW", argLength: 1, reg: gpfp, asm: "FCVTDW", typ: "Float64"}, // float64(low 32 bits of arg0) - {name: "FCVTDL", argLength: 1, reg: gpfp, asm: "FCVTDL", typ: "Float64"}, // float64(arg0) - {name: "FCVTWD", argLength: 1, reg: fpgp, asm: "FCVTWD", typ: "Int32"}, // int32(arg0) - {name: "FCVTLD", argLength: 1, reg: fpgp, asm: "FCVTLD", typ: "Int64"}, // int64(arg0) - {name: "FCVTDS", argLength: 1, reg: fp11, asm: "FCVTDS", typ: "Float64"}, // float64(arg0) - {name: "FCVTSD", argLength: 1, reg: fp11, asm: "FCVTSD", typ: "Float32"}, // float32(arg0) - {name: "FMOVDload", argLength: 2, reg: fpload, asm: "MOVD", aux: "SymOff", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load float64 from arg0+auxint+aux - {name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store float6 to arg0+auxint+aux - {name: "FEQD", argLength: 2, reg: fp2gp, asm: "FEQD", commutative: true}, // arg0 == arg1 - {name: "FNED", argLength: 2, reg: fp2gp, asm: "FNED", commutative: true}, // arg0 != arg1 - {name: "FLTD", argLength: 2, reg: fp2gp, asm: "FLTD"}, // arg0 < arg1 - {name: "FLED", argLength: 2, reg: fp2gp, asm: "FLED"}, // arg0 <= arg1 - {name: "LoweredFMIND", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMIND", commutative: true, typ: "Float64"}, // min(arg0, arg1) - {name: "LoweredFMAXD", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXD", commutative: true, typ: "Float64"}, // max(arg0, arg1) + {name: "FADDD", argLength: 2, reg: fp21, asm: "FADDD", commutative: true, typ: "Float64", earlyOk: true}, // arg0 + arg1 + {name: "FSUBD", argLength: 2, reg: fp21, asm: "FSUBD", commutative: false, typ: "Float64", earlyOk: true}, // arg0 - arg1 + {name: "FMULD", argLength: 2, reg: fp21, asm: "FMULD", commutative: true, typ: "Float64", earlyOk: true}, // arg0 * arg1 + {name: "FDIVD", argLength: 2, reg: fp21, asm: "FDIVD", commutative: false, typ: "Float64", earlyOk: true}, // arg0 / arg1 + {name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", commutative: true, typ: "Float64", earlyOk: true}, // (arg0 * arg1) + arg2 + {name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", commutative: true, typ: "Float64", earlyOk: true}, // (arg0 * arg1) - arg2 + {name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD", commutative: true, typ: "Float64", earlyOk: true}, // -(arg0 * arg1) + arg2 + {name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD", commutative: true, typ: "Float64", earlyOk: true}, // -(arg0 * arg1) - arg2 + {name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD", typ: "Float64", earlyOk: true}, // sqrt(arg0) + {name: "FNEGD", argLength: 1, reg: fp11, asm: "FNEGD", typ: "Float64", earlyOk: true}, // -arg0 + {name: "FABSD", argLength: 1, reg: fp11, asm: "FABSD", typ: "Float64", earlyOk: true}, // abs(arg0) + {name: "FSGNJD", argLength: 2, reg: fp21, asm: "FSGNJD", typ: "Float64", earlyOk: true}, // copy sign of arg1 to arg0 + {name: "FMVDX", argLength: 1, reg: gpfp, asm: "FMVDX", typ: "Float64", earlyOk: true}, // reinterpret arg0 as float64 + {name: "FMVXD", argLength: 1, reg: fpgp, asm: "FMVXD", typ: "Int64", earlyOk: true}, // reinterpret arg0 as int64 + {name: "FCVTDW", argLength: 1, reg: gpfp, asm: "FCVTDW", typ: "Float64", earlyOk: true}, // float64(low 32 bits of arg0) + {name: "FCVTDL", argLength: 1, reg: gpfp, asm: "FCVTDL", typ: "Float64", earlyOk: true}, // float64(arg0) + {name: "FCVTWD", argLength: 1, reg: fpgp, asm: "FCVTWD", typ: "Int32", earlyOk: true}, // int32(arg0) + {name: "FCVTLD", argLength: 1, reg: fpgp, asm: "FCVTLD", typ: "Int64", earlyOk: true}, // int64(arg0) + {name: "FCVTDS", argLength: 1, reg: fp11, asm: "FCVTDS", typ: "Float64", earlyOk: true}, // float64(arg0) + {name: "FCVTSD", argLength: 1, reg: fp11, asm: "FCVTSD", typ: "Float32", earlyOk: true}, // float32(arg0) + {name: "FMOVDload", argLength: 2, reg: fpload, asm: "MOVD", aux: "SymOff", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load float64 from arg0+auxint+aux + {name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store float6 to arg0+auxint+aux + {name: "FEQD", argLength: 2, reg: fp2gp, asm: "FEQD", commutative: true, earlyOk: true}, // arg0 == arg1 + {name: "FNED", argLength: 2, reg: fp2gp, asm: "FNED", commutative: true, earlyOk: true}, // arg0 != arg1 + {name: "FLTD", argLength: 2, reg: fp2gp, asm: "FLTD", earlyOk: true}, // arg0 < arg1 + {name: "FLED", argLength: 2, reg: fp2gp, asm: "FLED", earlyOk: true}, // arg0 <= arg1 + {name: "LoweredFMIND", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMIND", commutative: true, typ: "Float64", earlyOk: true}, // min(arg0, arg1) + {name: "LoweredFMAXD", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXD", commutative: true, typ: "Float64", earlyOk: true}, // max(arg0, arg1) // Floating point classify (in the F and D extensions). // @@ -518,8 +535,12 @@ func init() { // 8 | qNaN // 9 | sNaN // ====+============================= - {name: "FCLASSS", argLength: 1, reg: fpgp, asm: "FCLASSS", typ: "Int64"}, // classify float32 - {name: "FCLASSD", argLength: 1, reg: fpgp, asm: "FCLASSD", typ: "Int64"}, // classify float64 + {name: "FCLASSS", argLength: 1, reg: fpgp, asm: "FCLASSS", typ: "Int64", earlyOk: true}, // classify float32 + {name: "FCLASSD", argLength: 1, reg: fpgp, asm: "FCLASSD", typ: "Int64", earlyOk: true}, // classify float64 + + // RISC-V Integer Conditional (Zicond) operations extension + {name: "CZEROEQZ", argLength: 2, reg: gp21, asm: "CZEROEQZ"}, // arg1 == 0 result is 0, else arg0 + {name: "CZERONEZ", argLength: 2, reg: gp21, asm: "CZERONEZ"}, // arg1 != 0 result is 0, else arg0 } RISCV64blocks := []blockData{ diff --git a/src/cmd/compile/internal/ssa/_gen/S390X.rules b/src/cmd/compile/internal/ssa/_gen/S390X.rules index 664bf4a89c9024..ccaf7208c587e1 100644 --- a/src/cmd/compile/internal/ssa/_gen/S390X.rules +++ b/src/cmd/compile/internal/ssa/_gen/S390X.rules @@ -437,6 +437,7 @@ (ClosureCall ...) => (CALLclosure ...) (InterCall ...) => (CALLinter ...) (TailCall ...) => (CALLtail ...) +(TailCallInter ...) => (CALLtailinter ...) // Miscellaneous (IsNonNil p) => (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPconst p [0])) diff --git a/src/cmd/compile/internal/ssa/_gen/S390XOps.go b/src/cmd/compile/internal/ssa/_gen/S390XOps.go index c002d5bcc382a3..26b9d98241221d 100644 --- a/src/cmd/compile/internal/ssa/_gen/S390XOps.go +++ b/src/cmd/compile/internal/ssa/_gen/S390XOps.go @@ -97,10 +97,10 @@ func init() { num[name] = i } buildReg := func(s string) regMask { - m := regMask(0) + m := regMask{} for _, r := range strings.Split(s, " ") { if n, ok := num[r]; ok { - m |= regMask(1) << uint(n) + m = m.addReg(uint(n)) continue } panic("register " + r + " not found") @@ -118,16 +118,16 @@ func init() { // R10 is reserved by the assembler. gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14") - gpg = gp | buildReg("g") - gpsp = gp | sp + gpg = gp.union(buildReg("g")) + gpsp = gp.union(sp) // R0 is considered to contain the value 0 in address calculations. - ptr = gp &^ r0 - ptrsp = ptr | sp - ptrspsb = ptrsp | sb + ptr = gp.minus(r0) + ptrsp = ptr.union(sp) + ptrspsb = ptrsp.union(sb) fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15") - callerSave = gp | fp | buildReg("g") // runtime.setg (and anything calling it) may clobber g + callerSave = gp.union(fp).union(buildReg("g")) // runtime.setg (and anything calling it) may clobber g r1 = buildReg("R1") r2 = buildReg("R2") r3 = buildReg("R3") @@ -146,14 +146,14 @@ func init() { gp11sp = regInfo{inputs: []regMask{gpsp}, outputs: gponly} gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly} gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly} - gp21tmp = regInfo{inputs: []regMask{gp &^ tmp, gp &^ tmp}, outputs: []regMask{gp &^ tmp}, clobbers: tmp} + gp21tmp = regInfo{inputs: []regMask{gp.minus(tmp), gp.minus(tmp)}, outputs: []regMask{gp.minus(tmp)}, clobbers: tmp} // R0 evaluates to 0 when used as the number of bits to shift // so we need to exclude it from that operand. sh21 = regInfo{inputs: []regMask{gp, ptr}, outputs: gponly} - addr = regInfo{inputs: []regMask{sp | sb}, outputs: gponly} - addridx = regInfo{inputs: []regMask{sp | sb, ptrsp}, outputs: gponly} + addr = regInfo{inputs: []regMask{sp.union(sb)}, outputs: gponly} + addridx = regInfo{inputs: []regMask{sp.union(sb), ptrsp}, outputs: gponly} gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}} gp1flags = regInfo{inputs: []regMask{gpsp}} @@ -162,17 +162,17 @@ func init() { gp21flags = regInfo{inputs: []regMask{gp, gp}, outputs: gponly} gp2flags1flags = regInfo{inputs: []regMask{gp, gp}, outputs: gponly} - gpload = regInfo{inputs: []regMask{ptrspsb, 0}, outputs: gponly} - gploadidx = regInfo{inputs: []regMask{ptrspsb, ptrsp, 0}, outputs: gponly} - gpopload = regInfo{inputs: []regMask{gp, ptrsp, 0}, outputs: gponly} - gpstore = regInfo{inputs: []regMask{ptrspsb, gpsp, 0}} - gpstoreconst = regInfo{inputs: []regMask{ptrspsb, 0}} - gpstoreidx = regInfo{inputs: []regMask{ptrsp, ptrsp, gpsp, 0}} - gpstorebr = regInfo{inputs: []regMask{ptrsp, gpsp, 0}} - gpstorelaa = regInfo{inputs: []regMask{ptrspsb, gpsp, 0}, outputs: gponly} - gpstorelab = regInfo{inputs: []regMask{r1, gpsp, 0}, clobbers: r1} + gpload = regInfo{inputs: []regMask{ptrspsb, regMask{}}, outputs: gponly} + gploadidx = regInfo{inputs: []regMask{ptrspsb, ptrsp, regMask{}}, outputs: gponly} + gpopload = regInfo{inputs: []regMask{gp, ptrsp, regMask{}}, outputs: gponly} + gpstore = regInfo{inputs: []regMask{ptrspsb, gpsp, regMask{}}} + gpstoreconst = regInfo{inputs: []regMask{ptrspsb, regMask{}}} + gpstoreidx = regInfo{inputs: []regMask{ptrsp, ptrsp, gpsp, regMask{}}} + gpstorebr = regInfo{inputs: []regMask{ptrsp, gpsp, regMask{}}} + gpstorelaa = regInfo{inputs: []regMask{ptrspsb, gpsp, regMask{}}, outputs: gponly} + gpstorelab = regInfo{inputs: []regMask{r1, gpsp, regMask{}}, clobbers: r1} - gpmvc = regInfo{inputs: []regMask{ptrsp, ptrsp, 0}} + gpmvc = regInfo{inputs: []regMask{ptrsp, ptrsp, regMask{}}} fp01 = regInfo{inputs: []regMask{}, outputs: fponly} fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly} @@ -185,49 +185,49 @@ func init() { fp11clobber = regInfo{inputs: fponly, outputs: fponly} fp2flags = regInfo{inputs: []regMask{fp, fp}} - fpload = regInfo{inputs: []regMask{ptrspsb, 0}, outputs: fponly} - fploadidx = regInfo{inputs: []regMask{ptrsp, ptrsp, 0}, outputs: fponly} + fpload = regInfo{inputs: []regMask{ptrspsb, regMask{}}, outputs: fponly} + fploadidx = regInfo{inputs: []regMask{ptrsp, ptrsp, regMask{}}, outputs: fponly} - fpstore = regInfo{inputs: []regMask{ptrspsb, fp, 0}} - fpstoreidx = regInfo{inputs: []regMask{ptrsp, ptrsp, fp, 0}} + fpstore = regInfo{inputs: []regMask{ptrspsb, fp, regMask{}}} + fpstoreidx = regInfo{inputs: []regMask{ptrsp, ptrsp, fp, regMask{}}} - sync = regInfo{inputs: []regMask{0}} + sync = regInfo{inputs: []regMask{regMask{}}} // LoweredAtomicCas may overwrite arg1, so force it to R0 for now. - cas = regInfo{inputs: []regMask{ptrsp, r0, gpsp, 0}, outputs: []regMask{gp, 0}, clobbers: r0} + cas = regInfo{inputs: []regMask{ptrsp, r0, gpsp, regMask{}}, outputs: []regMask{gp, regMask{}}, clobbers: r0} // LoweredAtomicExchange overwrites the output before executing // CS{,G}, so the output register must not be the same as the // input register. For now we just force the output register to // R0. - exchange = regInfo{inputs: []regMask{ptrsp, gpsp &^ r0, 0}, outputs: []regMask{r0, 0}} + exchange = regInfo{inputs: []regMask{ptrsp, gpsp.minus(r0), regMask{}}, outputs: []regMask{r0, regMask{}}} ) var S390Xops = []opData{ // fp ops - {name: "FADDS", argLength: 2, reg: fp21clobber, typ: "(Float32,Flags)", asm: "FADDS", commutative: true, resultInArg0: true}, // fp32 arg0 + arg1 - {name: "FADD", argLength: 2, reg: fp21clobber, typ: "(Float64,Flags)", asm: "FADD", commutative: true, resultInArg0: true}, // fp64 arg0 + arg1 - {name: "FSUBS", argLength: 2, reg: fp21clobber, typ: "(Float32,Flags)", asm: "FSUBS", resultInArg0: true}, // fp32 arg0 - arg1 - {name: "FSUB", argLength: 2, reg: fp21clobber, typ: "(Float64,Flags)", asm: "FSUB", resultInArg0: true}, // fp64 arg0 - arg1 - {name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true, resultInArg0: true}, // fp32 arg0 * arg1 - {name: "FMUL", argLength: 2, reg: fp21, asm: "FMUL", commutative: true, resultInArg0: true}, // fp64 arg0 * arg1 - {name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS", resultInArg0: true}, // fp32 arg0 / arg1 - {name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV", resultInArg0: true}, // fp64 arg0 / arg1 - {name: "FNEGS", argLength: 1, reg: fp11clobber, asm: "FNEGS", clobberFlags: true}, // fp32 -arg0 - {name: "FNEG", argLength: 1, reg: fp11clobber, asm: "FNEG", clobberFlags: true}, // fp64 -arg0 - {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS", resultInArg0: true}, // fp32 arg1 * arg2 + arg0 - {name: "FMADD", argLength: 3, reg: fp31, asm: "FMADD", resultInArg0: true}, // fp64 arg1 * arg2 + arg0 - {name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS", resultInArg0: true}, // fp32 arg1 * arg2 - arg0 - {name: "FMSUB", argLength: 3, reg: fp31, asm: "FMSUB", resultInArg0: true}, // fp64 arg1 * arg2 - arg0 - {name: "LPDFR", argLength: 1, reg: fp11, asm: "LPDFR"}, // fp64/fp32 set sign bit - {name: "LNDFR", argLength: 1, reg: fp11, asm: "LNDFR"}, // fp64/fp32 clear sign bit - {name: "CPSDR", argLength: 2, reg: fp21, asm: "CPSDR"}, // fp64/fp32 copy arg1 sign bit to arg0 + {name: "FADDS", argLength: 2, reg: fp21clobber, typ: "(Float32,Flags)", asm: "FADDS", commutative: true, resultInArg0: true, earlyOk: true}, // fp32 arg0 + arg1 + {name: "FADD", argLength: 2, reg: fp21clobber, typ: "(Float64,Flags)", asm: "FADD", commutative: true, resultInArg0: true, earlyOk: true}, // fp64 arg0 + arg1 + {name: "FSUBS", argLength: 2, reg: fp21clobber, typ: "(Float32,Flags)", asm: "FSUBS", resultInArg0: true, earlyOk: true}, // fp32 arg0 - arg1 + {name: "FSUB", argLength: 2, reg: fp21clobber, typ: "(Float64,Flags)", asm: "FSUB", resultInArg0: true, earlyOk: true}, // fp64 arg0 - arg1 + {name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true, resultInArg0: true, earlyOk: true}, // fp32 arg0 * arg1 + {name: "FMUL", argLength: 2, reg: fp21, asm: "FMUL", commutative: true, resultInArg0: true, earlyOk: true}, // fp64 arg0 * arg1 + {name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS", resultInArg0: true, earlyOk: true}, // fp32 arg0 / arg1 + {name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV", resultInArg0: true, earlyOk: true}, // fp64 arg0 / arg1 + {name: "FNEGS", argLength: 1, reg: fp11clobber, asm: "FNEGS", clobberFlags: true, earlyOk: true}, // fp32 -arg0 + {name: "FNEG", argLength: 1, reg: fp11clobber, asm: "FNEG", clobberFlags: true, earlyOk: true}, // fp64 -arg0 + {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS", resultInArg0: true, earlyOk: true}, // fp32 arg1 * arg2 + arg0 + {name: "FMADD", argLength: 3, reg: fp31, asm: "FMADD", resultInArg0: true, earlyOk: true}, // fp64 arg1 * arg2 + arg0 + {name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS", resultInArg0: true, earlyOk: true}, // fp32 arg1 * arg2 - arg0 + {name: "FMSUB", argLength: 3, reg: fp31, asm: "FMSUB", resultInArg0: true, earlyOk: true}, // fp64 arg1 * arg2 - arg0 + {name: "LPDFR", argLength: 1, reg: fp11, asm: "LPDFR", earlyOk: true}, // fp64/fp32 set sign bit + {name: "LNDFR", argLength: 1, reg: fp11, asm: "LNDFR", earlyOk: true}, // fp64/fp32 clear sign bit + {name: "CPSDR", argLength: 2, reg: fp21, asm: "CPSDR", earlyOk: true}, // fp64/fp32 copy arg1 sign bit to arg0 // Single element vector floating point min / max instructions - {name: "WFMAXDB", argLength: 2, reg: fp21, asm: "WFMAXDB", typ: "Float64"}, // max[float64](arg0, arg1) - {name: "WFMAXSB", argLength: 2, reg: fp21, asm: "WFMAXSB", typ: "Float32"}, // max[float32](arg0, arg1) - {name: "WFMINDB", argLength: 2, reg: fp21, asm: "WFMINDB", typ: "Float64"}, // min[float64](arg0, arg1) - {name: "WFMINSB", argLength: 2, reg: fp21, asm: "WFMINSB", typ: "Float32"}, // min[float32](arg0, arg1) + {name: "WFMAXDB", argLength: 2, reg: fp21, asm: "WFMAXDB", typ: "Float64", earlyOk: true}, // max[float64](arg0, arg1) + {name: "WFMAXSB", argLength: 2, reg: fp21, asm: "WFMAXSB", typ: "Float32", earlyOk: true}, // max[float32](arg0, arg1) + {name: "WFMINDB", argLength: 2, reg: fp21, asm: "WFMINDB", typ: "Float64", earlyOk: true}, // min[float64](arg0, arg1) + {name: "WFMINSB", argLength: 2, reg: fp21, asm: "WFMINSB", typ: "Float32", earlyOk: true}, // min[float32](arg0, arg1) // Round to integer, float64 only. // @@ -238,44 +238,44 @@ func init() { // 5 | round toward 0 // 6 | round toward +∞ // 7 | round toward -∞ - {name: "FIDBR", argLength: 1, reg: fp11, asm: "FIDBR", aux: "Int8"}, + {name: "FIDBR", argLength: 1, reg: fp11, asm: "FIDBR", aux: "Int8", earlyOk: true}, - {name: "FMOVSload", argLength: 2, reg: fpload, asm: "FMOVS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // fp32 load - {name: "FMOVDload", argLength: 2, reg: fpload, asm: "FMOVD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // fp64 load - {name: "FMOVSconst", reg: fp01, asm: "FMOVS", aux: "Float32", rematerializeable: true}, // fp32 constant - {name: "FMOVDconst", reg: fp01, asm: "FMOVD", aux: "Float64", rematerializeable: true}, // fp64 constant - {name: "FMOVSloadidx", argLength: 3, reg: fploadidx, asm: "FMOVS", aux: "SymOff", symEffect: "Read"}, // fp32 load indexed by i - {name: "FMOVDloadidx", argLength: 3, reg: fploadidx, asm: "FMOVD", aux: "SymOff", symEffect: "Read"}, // fp64 load indexed by i + {name: "FMOVSload", argLength: 2, reg: fpload, asm: "FMOVS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // fp32 load + {name: "FMOVDload", argLength: 2, reg: fpload, asm: "FMOVD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // fp64 load + {name: "FMOVSconst", reg: fp01, asm: "FMOVS", aux: "Float32", rematerializeable: true, earlyOk: true}, // fp32 constant + {name: "FMOVDconst", reg: fp01, asm: "FMOVD", aux: "Float64", rematerializeable: true, earlyOk: true}, // fp64 constant + {name: "FMOVSloadidx", argLength: 3, reg: fploadidx, asm: "FMOVS", aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, // fp32 load indexed by i + {name: "FMOVDloadidx", argLength: 3, reg: fploadidx, asm: "FMOVD", aux: "SymOff", symEffect: "Read", addrSinkArg0: true}, // fp64 load indexed by i - {name: "FMOVSstore", argLength: 3, reg: fpstore, asm: "FMOVS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // fp32 store - {name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "FMOVD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // fp64 store - {name: "FMOVSstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVS", aux: "SymOff", symEffect: "Write"}, // fp32 indexed by i store - {name: "FMOVDstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVD", aux: "SymOff", symEffect: "Write"}, // fp64 indexed by i store + {name: "FMOVSstore", argLength: 3, reg: fpstore, asm: "FMOVS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // fp32 store + {name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "FMOVD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // fp64 store + {name: "FMOVSstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVS", aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // fp32 indexed by i store + {name: "FMOVDstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVD", aux: "SymOff", symEffect: "Write", addrSinkArg0: true}, // fp64 indexed by i store // binary ops - {name: "ADD", argLength: 2, reg: gp21sp, asm: "ADD", commutative: true, clobberFlags: true}, // arg0 + arg1 - {name: "ADDW", argLength: 2, reg: gp21sp, asm: "ADDW", commutative: true, clobberFlags: true}, // arg0 + arg1 - {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int32", typ: "UInt64", clobberFlags: true}, // arg0 + auxint - {name: "ADDWconst", argLength: 1, reg: gp11sp, asm: "ADDW", aux: "Int32", clobberFlags: true}, // arg0 + auxint - {name: "ADDload", argLength: 3, reg: gpopload, asm: "ADD", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 + *arg1. arg2=mem - {name: "ADDWload", argLength: 3, reg: gpopload, asm: "ADDW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 + *arg1. arg2=mem - - {name: "SUB", argLength: 2, reg: gp21, asm: "SUB", clobberFlags: true}, // arg0 - arg1 - {name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW", clobberFlags: true}, // arg0 - arg1 - {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 - auxint - {name: "SUBWconst", argLength: 1, reg: gp11, asm: "SUBW", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 - auxint - {name: "SUBload", argLength: 3, reg: gpopload, asm: "SUB", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 - *arg1. arg2=mem - {name: "SUBWload", argLength: 3, reg: gpopload, asm: "SUBW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 - *arg1. arg2=mem - - {name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 * arg1 - {name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 * arg1 - {name: "MULLDconst", argLength: 1, reg: gp11, asm: "MULLD", aux: "Int32", typ: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 * auxint - {name: "MULLWconst", argLength: 1, reg: gp11, asm: "MULLW", aux: "Int32", typ: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 * auxint - {name: "MULLDload", argLength: 3, reg: gpopload, asm: "MULLD", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 * *arg1. arg2=mem - {name: "MULLWload", argLength: 3, reg: gpopload, asm: "MULLW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 * *arg1. arg2=mem - - {name: "MULHD", argLength: 2, reg: gp21tmp, asm: "MULHD", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true}, // (arg0 * arg1) >> width - {name: "MULHDU", argLength: 2, reg: gp21tmp, asm: "MULHDU", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true}, // (arg0 * arg1) >> width + {name: "ADD", argLength: 2, reg: gp21sp, asm: "ADD", commutative: true, clobberFlags: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDW", argLength: 2, reg: gp21sp, asm: "ADDW", commutative: true, clobberFlags: true, earlyOk: true}, // arg0 + arg1 + {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int32", typ: "UInt64", clobberFlags: true, earlyOk: true}, // arg0 + auxint + {name: "ADDWconst", argLength: 1, reg: gp11sp, asm: "ADDW", aux: "Int32", clobberFlags: true, earlyOk: true}, // arg0 + auxint + {name: "ADDload", argLength: 3, reg: gpopload, asm: "ADD", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 + *arg1. arg2=mem + {name: "ADDWload", argLength: 3, reg: gpopload, asm: "ADDW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 + *arg1. arg2=mem + + {name: "SUB", argLength: 2, reg: gp21, asm: "SUB", clobberFlags: true, earlyOk: true}, // arg0 - arg1 + {name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW", clobberFlags: true, earlyOk: true}, // arg0 - arg1 + {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 - auxint + {name: "SUBWconst", argLength: 1, reg: gp11, asm: "SUBW", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 - auxint + {name: "SUBload", argLength: 3, reg: gpopload, asm: "SUB", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 - *arg1. arg2=mem + {name: "SUBWload", argLength: 3, reg: gpopload, asm: "SUBW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 - *arg1. arg2=mem + + {name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 * arg1 + {name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 * arg1 + {name: "MULLDconst", argLength: 1, reg: gp11, asm: "MULLD", aux: "Int32", typ: "Int64", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 * auxint + {name: "MULLWconst", argLength: 1, reg: gp11, asm: "MULLW", aux: "Int32", typ: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 * auxint + {name: "MULLDload", argLength: 3, reg: gpopload, asm: "MULLD", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 * *arg1. arg2=mem + {name: "MULLWload", argLength: 3, reg: gpopload, asm: "MULLW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 * *arg1. arg2=mem + + {name: "MULHD", argLength: 2, reg: gp21tmp, asm: "MULHD", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // (arg0 * arg1) >> width + {name: "MULHDU", argLength: 2, reg: gp21tmp, asm: "MULHDU", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true, earlyOk: true}, // (arg0 * arg1) >> width {name: "DIVD", argLength: 2, reg: gp21tmp, asm: "DIVD", resultInArg0: true, clobberFlags: true}, // arg0 / arg1 {name: "DIVW", argLength: 2, reg: gp21tmp, asm: "DIVW", resultInArg0: true, clobberFlags: true}, // arg0 / arg1 @@ -288,26 +288,26 @@ func init() { {name: "MODDU", argLength: 2, reg: gp21tmp, asm: "MODDU", resultInArg0: true, clobberFlags: true}, // arg0 % arg1 {name: "MODWU", argLength: 2, reg: gp21tmp, asm: "MODWU", resultInArg0: true, clobberFlags: true}, // arg0 % arg1 - {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true, clobberFlags: true}, // arg0 & arg1 - {name: "ANDW", argLength: 2, reg: gp21, asm: "ANDW", commutative: true, clobberFlags: true}, // arg0 & arg1 - {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 & auxint - {name: "ANDWconst", argLength: 1, reg: gp11, asm: "ANDW", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 & auxint - {name: "ANDload", argLength: 3, reg: gpopload, asm: "AND", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 & *arg1. arg2=mem - {name: "ANDWload", argLength: 3, reg: gpopload, asm: "ANDW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 & *arg1. arg2=mem - - {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true, clobberFlags: true}, // arg0 | arg1 - {name: "ORW", argLength: 2, reg: gp21, asm: "ORW", commutative: true, clobberFlags: true}, // arg0 | arg1 - {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 | auxint - {name: "ORWconst", argLength: 1, reg: gp11, asm: "ORW", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 | auxint - {name: "ORload", argLength: 3, reg: gpopload, asm: "OR", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 | *arg1. arg2=mem - {name: "ORWload", argLength: 3, reg: gpopload, asm: "ORW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 | *arg1. arg2=mem - - {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, clobberFlags: true}, // arg0 ^ arg1 - {name: "XORW", argLength: 2, reg: gp21, asm: "XORW", commutative: true, clobberFlags: true}, // arg0 ^ arg1 - {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint - {name: "XORWconst", argLength: 1, reg: gp11, asm: "XORW", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint - {name: "XORload", argLength: 3, reg: gpopload, asm: "XOR", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 ^ *arg1. arg2=mem - {name: "XORWload", argLength: 3, reg: gpopload, asm: "XORW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 ^ *arg1. arg2=mem + {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true, clobberFlags: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDW", argLength: 2, reg: gp21, asm: "ANDW", commutative: true, clobberFlags: true, earlyOk: true}, // arg0 & arg1 + {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 & auxint + {name: "ANDWconst", argLength: 1, reg: gp11, asm: "ANDW", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 & auxint + {name: "ANDload", argLength: 3, reg: gpopload, asm: "AND", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 & *arg1. arg2=mem + {name: "ANDWload", argLength: 3, reg: gpopload, asm: "ANDW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 & *arg1. arg2=mem + + {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true, clobberFlags: true, earlyOk: true}, // arg0 | arg1 + {name: "ORW", argLength: 2, reg: gp21, asm: "ORW", commutative: true, clobberFlags: true, earlyOk: true}, // arg0 | arg1 + {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 | auxint + {name: "ORWconst", argLength: 1, reg: gp11, asm: "ORW", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 | auxint + {name: "ORload", argLength: 3, reg: gpopload, asm: "OR", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 | *arg1. arg2=mem + {name: "ORWload", argLength: 3, reg: gpopload, asm: "ORW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 | *arg1. arg2=mem + + {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, clobberFlags: true, earlyOk: true}, // arg0 ^ arg1 + {name: "XORW", argLength: 2, reg: gp21, asm: "XORW", commutative: true, clobberFlags: true, earlyOk: true}, // arg0 ^ arg1 + {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 ^ auxint + {name: "XORWconst", argLength: 1, reg: gp11, asm: "XORW", aux: "Int32", resultInArg0: true, clobberFlags: true, earlyOk: true}, // arg0 ^ auxint + {name: "XORload", argLength: 3, reg: gpopload, asm: "XOR", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 ^ *arg1. arg2=mem + {name: "XORWload", argLength: 3, reg: gpopload, asm: "XORW", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // arg0 ^ *arg1. arg2=mem // Arithmetic ops with carry/borrow chain. // @@ -336,27 +336,27 @@ func init() { {name: "LTDBR", argLength: 1, reg: fp1flags, asm: "LTDBR", typ: "Flags"}, // arg0 compare to 0, f64 {name: "LTEBR", argLength: 1, reg: fp1flags, asm: "LTEBR", typ: "Flags"}, // arg0 compare to 0, f32 - {name: "SLD", argLength: 2, reg: sh21, asm: "SLD"}, // arg0 << arg1, shift amount is mod 64 - {name: "SLW", argLength: 2, reg: sh21, asm: "SLW"}, // arg0 << arg1, shift amount is mod 64 - {name: "SLDconst", argLength: 1, reg: gp11, asm: "SLD", aux: "UInt8"}, // arg0 << auxint, shift amount 0-63 - {name: "SLWconst", argLength: 1, reg: gp11, asm: "SLW", aux: "UInt8"}, // arg0 << auxint, shift amount 0-31 + {name: "SLD", argLength: 2, reg: sh21, asm: "SLD", earlyOk: true}, // arg0 << arg1, shift amount is mod 64 + {name: "SLW", argLength: 2, reg: sh21, asm: "SLW", earlyOk: true}, // arg0 << arg1, shift amount is mod 64 + {name: "SLDconst", argLength: 1, reg: gp11, asm: "SLD", aux: "UInt8", earlyOk: true}, // arg0 << auxint, shift amount 0-63 + {name: "SLWconst", argLength: 1, reg: gp11, asm: "SLW", aux: "UInt8", earlyOk: true}, // arg0 << auxint, shift amount 0-31 - {name: "SRD", argLength: 2, reg: sh21, asm: "SRD"}, // unsigned arg0 >> arg1, shift amount is mod 64 - {name: "SRW", argLength: 2, reg: sh21, asm: "SRW"}, // unsigned uint32(arg0) >> arg1, shift amount is mod 64 - {name: "SRDconst", argLength: 1, reg: gp11, asm: "SRD", aux: "UInt8"}, // unsigned arg0 >> auxint, shift amount 0-63 - {name: "SRWconst", argLength: 1, reg: gp11, asm: "SRW", aux: "UInt8"}, // unsigned uint32(arg0) >> auxint, shift amount 0-31 + {name: "SRD", argLength: 2, reg: sh21, asm: "SRD", earlyOk: true}, // unsigned arg0 >> arg1, shift amount is mod 64 + {name: "SRW", argLength: 2, reg: sh21, asm: "SRW", earlyOk: true}, // unsigned uint32(arg0) >> arg1, shift amount is mod 64 + {name: "SRDconst", argLength: 1, reg: gp11, asm: "SRD", aux: "UInt8", earlyOk: true}, // unsigned arg0 >> auxint, shift amount 0-63 + {name: "SRWconst", argLength: 1, reg: gp11, asm: "SRW", aux: "UInt8", earlyOk: true}, // unsigned uint32(arg0) >> auxint, shift amount 0-31 // Arithmetic shifts clobber flags. - {name: "SRAD", argLength: 2, reg: sh21, asm: "SRAD", clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 64 - {name: "SRAW", argLength: 2, reg: sh21, asm: "SRAW", clobberFlags: true}, // signed int32(arg0) >> arg1, shift amount is mod 64 - {name: "SRADconst", argLength: 1, reg: gp11, asm: "SRAD", aux: "UInt8", clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-63 - {name: "SRAWconst", argLength: 1, reg: gp11, asm: "SRAW", aux: "UInt8", clobberFlags: true}, // signed int32(arg0) >> auxint, shift amount 0-31 + {name: "SRAD", argLength: 2, reg: sh21, asm: "SRAD", clobberFlags: true, earlyOk: true}, // signed arg0 >> arg1, shift amount is mod 64 + {name: "SRAW", argLength: 2, reg: sh21, asm: "SRAW", clobberFlags: true, earlyOk: true}, // signed int32(arg0) >> arg1, shift amount is mod 64 + {name: "SRADconst", argLength: 1, reg: gp11, asm: "SRAD", aux: "UInt8", clobberFlags: true, earlyOk: true}, // signed arg0 >> auxint, shift amount 0-63 + {name: "SRAWconst", argLength: 1, reg: gp11, asm: "SRAW", aux: "UInt8", clobberFlags: true, earlyOk: true}, // signed int32(arg0) >> auxint, shift amount 0-31 // Rotate instructions. // Note: no RLLGconst - use RISBGZ instead. - {name: "RLLG", argLength: 2, reg: sh21, asm: "RLLG"}, // arg0 rotate left arg1, rotate amount 0-63 - {name: "RLL", argLength: 2, reg: sh21, asm: "RLL"}, // arg0 rotate left arg1, rotate amount 0-31 - {name: "RLLconst", argLength: 1, reg: gp11, asm: "RLL", aux: "UInt8"}, // arg0 rotate left auxint, rotate amount 0-31 + {name: "RLLG", argLength: 2, reg: sh21, asm: "RLLG", earlyOk: true}, // arg0 rotate left arg1, rotate amount 0-63 + {name: "RLL", argLength: 2, reg: sh21, asm: "RLL", earlyOk: true}, // arg0 rotate left arg1, rotate amount 0-31 + {name: "RLLconst", argLength: 1, reg: gp11, asm: "RLL", aux: "UInt8", earlyOk: true}, // arg0 rotate left auxint, rotate amount 0-31 // Rotate then (and|or|xor|insert) selected bits instructions. // @@ -377,117 +377,118 @@ func init() { // | RXSBG (XOR) | 0 | 47 | 16 | 0xffff_ffff_ffff_ffff | 0x0000_0000_0000_ffff | 0xffff_ffff_0000_ffff | // +-------------+-------+-----+--------+-----------------------+-----------------------+-----------------------+ // - {name: "RXSBG", argLength: 2, reg: gp21, asm: "RXSBG", resultInArg0: true, aux: "S390XRotateParams", clobberFlags: true}, // rotate then xor selected bits - {name: "RISBGZ", argLength: 1, reg: gp11, asm: "RISBGZ", aux: "S390XRotateParams", clobberFlags: true}, // rotate then insert selected bits [into zero] + {name: "RXSBG", argLength: 2, reg: gp21, asm: "RXSBG", resultInArg0: true, aux: "S390XRotateParams", clobberFlags: true, earlyOk: true}, // rotate then xor selected bits + {name: "RISBGZ", argLength: 1, reg: gp11, asm: "RISBGZ", aux: "S390XRotateParams", clobberFlags: true, earlyOk: true}, // rotate then insert selected bits [into zero] // unary ops - {name: "NEG", argLength: 1, reg: gp11, asm: "NEG", clobberFlags: true}, // -arg0 - {name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW", clobberFlags: true}, // -arg0 + {name: "NEG", argLength: 1, reg: gp11, asm: "NEG", clobberFlags: true, earlyOk: true}, // -arg0 + {name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW", clobberFlags: true, earlyOk: true}, // -arg0 - {name: "NOT", argLength: 1, reg: gp11, resultInArg0: true, clobberFlags: true}, // ^arg0 - {name: "NOTW", argLength: 1, reg: gp11, resultInArg0: true, clobberFlags: true}, // ^arg0 + {name: "NOT", argLength: 1, reg: gp11, resultInArg0: true, clobberFlags: true, earlyOk: true}, // ^arg0 + {name: "NOTW", argLength: 1, reg: gp11, resultInArg0: true, clobberFlags: true, earlyOk: true}, // ^arg0 - {name: "FSQRT", argLength: 1, reg: fp11, asm: "FSQRT"}, // sqrt(arg0) - {name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS"}, // sqrt(arg0), float32 + {name: "FSQRT", argLength: 1, reg: fp11, asm: "FSQRT", earlyOk: true}, // sqrt(arg0) + {name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS", earlyOk: true}, // sqrt(arg0), float32 // Conditional register-register moves. // The aux for these values is an s390x.CCMask value representing the condition code mask. - {name: "LOCGR", argLength: 3, reg: gp2flags1, resultInArg0: true, asm: "LOCGR", aux: "S390XCCMask"}, // load arg1 into arg0 if the condition code in arg2 matches a masked bit in aux. - - {name: "MOVBreg", argLength: 1, reg: gp11sp, asm: "MOVB", typ: "Int64"}, // sign extend arg0 from int8 to int64 - {name: "MOVBZreg", argLength: 1, reg: gp11sp, asm: "MOVBZ", typ: "UInt64"}, // zero extend arg0 from int8 to int64 - {name: "MOVHreg", argLength: 1, reg: gp11sp, asm: "MOVH", typ: "Int64"}, // sign extend arg0 from int16 to int64 - {name: "MOVHZreg", argLength: 1, reg: gp11sp, asm: "MOVHZ", typ: "UInt64"}, // zero extend arg0 from int16 to int64 - {name: "MOVWreg", argLength: 1, reg: gp11sp, asm: "MOVW", typ: "Int64"}, // sign extend arg0 from int32 to int64 - {name: "MOVWZreg", argLength: 1, reg: gp11sp, asm: "MOVWZ", typ: "UInt64"}, // zero extend arg0 from int32 to int64 - - {name: "MOVDconst", reg: gp01, asm: "MOVD", typ: "UInt64", aux: "Int64", rematerializeable: true}, // auxint - - {name: "LDGR", argLength: 1, reg: gpfp, asm: "LDGR"}, // move int64 to float64 (no conversion) - {name: "LGDR", argLength: 1, reg: fpgp, asm: "LGDR"}, // move float64 to int64 (no conversion) - - {name: "CFDBRA", argLength: 1, reg: fpgp, asm: "CFDBRA", clobberFlags: true}, // convert float64 to int32 - {name: "CGDBRA", argLength: 1, reg: fpgp, asm: "CGDBRA", clobberFlags: true}, // convert float64 to int64 - {name: "CFEBRA", argLength: 1, reg: fpgp, asm: "CFEBRA", clobberFlags: true}, // convert float32 to int32 - {name: "CGEBRA", argLength: 1, reg: fpgp, asm: "CGEBRA", clobberFlags: true}, // convert float32 to int64 - {name: "CEFBRA", argLength: 1, reg: gpfp, asm: "CEFBRA", clobberFlags: true}, // convert int32 to float32 - {name: "CDFBRA", argLength: 1, reg: gpfp, asm: "CDFBRA", clobberFlags: true}, // convert int32 to float64 - {name: "CEGBRA", argLength: 1, reg: gpfp, asm: "CEGBRA", clobberFlags: true}, // convert int64 to float32 - {name: "CDGBRA", argLength: 1, reg: gpfp, asm: "CDGBRA", clobberFlags: true}, // convert int64 to float64 - {name: "CLFEBR", argLength: 1, reg: fpgp, asm: "CLFEBR", clobberFlags: true}, // convert float32 to uint32 - {name: "CLFDBR", argLength: 1, reg: fpgp, asm: "CLFDBR", clobberFlags: true}, // convert float64 to uint32 - {name: "CLGEBR", argLength: 1, reg: fpgp, asm: "CLGEBR", clobberFlags: true}, // convert float32 to uint64 - {name: "CLGDBR", argLength: 1, reg: fpgp, asm: "CLGDBR", clobberFlags: true}, // convert float64 to uint64 - {name: "CELFBR", argLength: 1, reg: gpfp, asm: "CELFBR", clobberFlags: true}, // convert uint32 to float32 - {name: "CDLFBR", argLength: 1, reg: gpfp, asm: "CDLFBR", clobberFlags: true}, // convert uint32 to float64 - {name: "CELGBR", argLength: 1, reg: gpfp, asm: "CELGBR", clobberFlags: true}, // convert uint64 to float32 - {name: "CDLGBR", argLength: 1, reg: gpfp, asm: "CDLGBR", clobberFlags: true}, // convert uint64 to float64 - - {name: "LEDBR", argLength: 1, reg: fp11, asm: "LEDBR"}, // convert float64 to float32 - {name: "LDEBR", argLength: 1, reg: fp11, asm: "LDEBR"}, // convert float32 to float64 - - {name: "MOVDaddr", argLength: 1, reg: addr, aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux - {name: "MOVDaddridx", argLength: 2, reg: addridx, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux + {name: "LOCGR", argLength: 3, reg: gp2flags1, resultInArg0: true, asm: "LOCGR", aux: "S390XCCMask", earlyOk: true}, // load arg1 into arg0 if the condition code in arg2 matches a masked bit in aux. + + {name: "MOVBreg", argLength: 1, reg: gp11sp, asm: "MOVB", typ: "Int64", earlyOk: true}, // sign extend arg0 from int8 to int64 + {name: "MOVBZreg", argLength: 1, reg: gp11sp, asm: "MOVBZ", typ: "UInt64", earlyOk: true}, // zero extend arg0 from int8 to int64 + {name: "MOVHreg", argLength: 1, reg: gp11sp, asm: "MOVH", typ: "Int64", earlyOk: true}, // sign extend arg0 from int16 to int64 + {name: "MOVHZreg", argLength: 1, reg: gp11sp, asm: "MOVHZ", typ: "UInt64", earlyOk: true}, // zero extend arg0 from int16 to int64 + {name: "MOVWreg", argLength: 1, reg: gp11sp, asm: "MOVW", typ: "Int64", earlyOk: true}, // sign extend arg0 from int32 to int64 + {name: "MOVWZreg", argLength: 1, reg: gp11sp, asm: "MOVWZ", typ: "UInt64", earlyOk: true}, // zero extend arg0 from int32 to int64 + + {name: "MOVDconst", reg: gp01, asm: "MOVD", typ: "UInt64", aux: "Int64", rematerializeable: true, earlyOk: true}, // auxint + + {name: "LDGR", argLength: 1, reg: gpfp, asm: "LDGR", earlyOk: true}, // move int64 to float64 (no conversion) + {name: "LGDR", argLength: 1, reg: fpgp, asm: "LGDR", earlyOk: true}, // move float64 to int64 (no conversion) + + {name: "CFDBRA", argLength: 1, reg: fpgp, asm: "CFDBRA", clobberFlags: true, earlyOk: true}, // convert float64 to int32 + {name: "CGDBRA", argLength: 1, reg: fpgp, asm: "CGDBRA", clobberFlags: true, earlyOk: true}, // convert float64 to int64 + {name: "CFEBRA", argLength: 1, reg: fpgp, asm: "CFEBRA", clobberFlags: true, earlyOk: true}, // convert float32 to int32 + {name: "CGEBRA", argLength: 1, reg: fpgp, asm: "CGEBRA", clobberFlags: true, earlyOk: true}, // convert float32 to int64 + {name: "CEFBRA", argLength: 1, reg: gpfp, asm: "CEFBRA", clobberFlags: true, earlyOk: true}, // convert int32 to float32 + {name: "CDFBRA", argLength: 1, reg: gpfp, asm: "CDFBRA", clobberFlags: true, earlyOk: true}, // convert int32 to float64 + {name: "CEGBRA", argLength: 1, reg: gpfp, asm: "CEGBRA", clobberFlags: true, earlyOk: true}, // convert int64 to float32 + {name: "CDGBRA", argLength: 1, reg: gpfp, asm: "CDGBRA", clobberFlags: true, earlyOk: true}, // convert int64 to float64 + {name: "CLFEBR", argLength: 1, reg: fpgp, asm: "CLFEBR", clobberFlags: true, earlyOk: true}, // convert float32 to uint32 + {name: "CLFDBR", argLength: 1, reg: fpgp, asm: "CLFDBR", clobberFlags: true, earlyOk: true}, // convert float64 to uint32 + {name: "CLGEBR", argLength: 1, reg: fpgp, asm: "CLGEBR", clobberFlags: true, earlyOk: true}, // convert float32 to uint64 + {name: "CLGDBR", argLength: 1, reg: fpgp, asm: "CLGDBR", clobberFlags: true, earlyOk: true}, // convert float64 to uint64 + {name: "CELFBR", argLength: 1, reg: gpfp, asm: "CELFBR", clobberFlags: true, earlyOk: true}, // convert uint32 to float32 + {name: "CDLFBR", argLength: 1, reg: gpfp, asm: "CDLFBR", clobberFlags: true, earlyOk: true}, // convert uint32 to float64 + {name: "CELGBR", argLength: 1, reg: gpfp, asm: "CELGBR", clobberFlags: true, earlyOk: true}, // convert uint64 to float32 + {name: "CDLGBR", argLength: 1, reg: gpfp, asm: "CDLGBR", clobberFlags: true, earlyOk: true}, // convert uint64 to float64 + + {name: "LEDBR", argLength: 1, reg: fp11, asm: "LEDBR", earlyOk: true}, // convert float64 to float32 + {name: "LDEBR", argLength: 1, reg: fp11, asm: "LDEBR", earlyOk: true}, // convert float32 to float64 + + {name: "MOVDaddr", argLength: 1, reg: addr, aux: "SymOff", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // arg0 + auxint + offset encoded in aux + {name: "MOVDaddridx", argLength: 2, reg: addridx, aux: "SymOff", symEffect: "Addr", earlyOk: true}, // arg0 + arg1 + auxint + aux // auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address - {name: "MOVBZload", argLength: 2, reg: gpload, asm: "MOVBZ", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load byte from arg0+auxint+aux. arg1=mem. Zero extend. - {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVB", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // ditto, sign extend to int64 - {name: "MOVHZload", argLength: 2, reg: gpload, asm: "MOVHZ", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Zero extend. - {name: "MOVHload", argLength: 2, reg: gpload, asm: "MOVH", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // ditto, sign extend to int64 - {name: "MOVWZload", argLength: 2, reg: gpload, asm: "MOVWZ", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Zero extend. - {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // ditto, sign extend to int64 - {name: "MOVDload", argLength: 2, reg: gpload, asm: "MOVD", aux: "SymOff", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"}, // load 8 bytes from arg0+auxint+aux. arg1=mem - - {name: "MOVWBR", argLength: 1, reg: gp11, asm: "MOVWBR"}, // arg0 swap bytes - {name: "MOVDBR", argLength: 1, reg: gp11, asm: "MOVDBR"}, // arg0 swap bytes - - {name: "MOVHBRload", argLength: 2, reg: gpload, asm: "MOVHBR", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Reverse bytes. - {name: "MOVWBRload", argLength: 2, reg: gpload, asm: "MOVWBR", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Reverse bytes. - {name: "MOVDBRload", argLength: 2, reg: gpload, asm: "MOVDBR", aux: "SymOff", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"}, // load 8 bytes from arg0+auxint+aux. arg1=mem. Reverse bytes. - - {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem - {name: "MOVHstore", argLength: 3, reg: gpstore, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem - {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem - {name: "MOVDstore", argLength: 3, reg: gpstore, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem - {name: "MOVHBRstore", argLength: 3, reg: gpstorebr, asm: "MOVHBR", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem. Reverse bytes. - {name: "MOVWBRstore", argLength: 3, reg: gpstorebr, asm: "MOVWBR", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem. Reverse bytes. - {name: "MOVDBRstore", argLength: 3, reg: gpstorebr, asm: "MOVDBR", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem. Reverse bytes. + {name: "MOVBZload", argLength: 2, reg: gpload, asm: "MOVBZ", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load byte from arg0+auxint+aux. arg1=mem. Zero extend. + {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVB", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // ditto, sign extend to int64 + {name: "MOVHZload", argLength: 2, reg: gpload, asm: "MOVHZ", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Zero extend. + {name: "MOVHload", argLength: 2, reg: gpload, asm: "MOVH", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // ditto, sign extend to int64 + {name: "MOVWZload", argLength: 2, reg: gpload, asm: "MOVWZ", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Zero extend. + {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // ditto, sign extend to int64 + {name: "MOVDload", argLength: 2, reg: gpload, asm: "MOVD", aux: "SymOff", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 8 bytes from arg0+auxint+aux. arg1=mem + + {name: "MOVWBR", argLength: 1, reg: gp11, asm: "MOVWBR", earlyOk: true}, // arg0 swap bytes + {name: "MOVDBR", argLength: 1, reg: gp11, asm: "MOVDBR", earlyOk: true}, // arg0 swap bytes + + {name: "MOVHBRload", argLength: 2, reg: gpload, asm: "MOVHBR", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Reverse bytes. + {name: "MOVWBRload", argLength: 2, reg: gpload, asm: "MOVWBR", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Reverse bytes. + {name: "MOVDBRload", argLength: 2, reg: gpload, asm: "MOVDBR", aux: "SymOff", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read", addrSinkArg0: true}, // load 8 bytes from arg0+auxint+aux. arg1=mem. Reverse bytes. + + {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store byte in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVHstore", argLength: 3, reg: gpstore, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVDstore", argLength: 3, reg: gpstore, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVHBRstore", argLength: 3, reg: gpstorebr, asm: "MOVHBR", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem. Reverse bytes. + {name: "MOVWBRstore", argLength: 3, reg: gpstorebr, asm: "MOVWBR", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem. Reverse bytes. + {name: "MOVDBRstore", argLength: 3, reg: gpstorebr, asm: "MOVDBR", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem. Reverse bytes. {name: "MVC", argLength: 3, reg: gpmvc, asm: "MVC", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, symEffect: "None"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size,off // indexed loads/stores - {name: "MOVBZloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBZ", aux: "SymOff", typ: "UInt8", symEffect: "Read"}, // load a byte from arg0+arg1+auxint+aux. arg2=mem. Zero extend. - {name: "MOVBloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVB", aux: "SymOff", typ: "Int8", symEffect: "Read"}, // load a byte from arg0+arg1+auxint+aux. arg2=mem. Sign extend. - {name: "MOVHZloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVHZ", aux: "SymOff", typ: "UInt16", symEffect: "Read"}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem. Zero extend. - {name: "MOVHloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVH", aux: "SymOff", typ: "Int16", symEffect: "Read"}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem. Sign extend. - {name: "MOVWZloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVWZ", aux: "SymOff", typ: "UInt32", symEffect: "Read"}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem. Zero extend. - {name: "MOVWloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVW", aux: "SymOff", typ: "Int32", symEffect: "Read"}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem. Sign extend. - {name: "MOVDloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVD", aux: "SymOff", typ: "UInt64", symEffect: "Read"}, // load 8 bytes from arg0+arg1+auxint+aux. arg2=mem - {name: "MOVHBRloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVHBR", aux: "SymOff", typ: "Int16", symEffect: "Read"}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem. Reverse bytes. - {name: "MOVWBRloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVWBR", aux: "SymOff", typ: "Int32", symEffect: "Read"}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem. Reverse bytes. - {name: "MOVDBRloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVDBR", aux: "SymOff", typ: "Int64", symEffect: "Read"}, // load 8 bytes from arg0+arg1+auxint+aux. arg2=mem. Reverse bytes. - {name: "MOVBstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVB", aux: "SymOff", symEffect: "Write"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem - {name: "MOVHstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVH", aux: "SymOff", symEffect: "Write"}, // store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem - {name: "MOVWstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVW", aux: "SymOff", symEffect: "Write"}, // store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem - {name: "MOVDstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVD", aux: "SymOff", symEffect: "Write"}, // store 8 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem - {name: "MOVHBRstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVHBR", aux: "SymOff", symEffect: "Write"}, // store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem. Reverse bytes. - {name: "MOVWBRstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVWBR", aux: "SymOff", symEffect: "Write"}, // store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem. Reverse bytes. - {name: "MOVDBRstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVDBR", aux: "SymOff", symEffect: "Write"}, // store 8 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem. Reverse bytes. + {name: "MOVBZloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBZ", aux: "SymOff", typ: "UInt8", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load a byte from arg0+arg1+auxint+aux. arg2=mem. Zero extend. + {name: "MOVBloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVB", aux: "SymOff", typ: "Int8", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load a byte from arg0+arg1+auxint+aux. arg2=mem. Sign extend. + {name: "MOVHZloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVHZ", aux: "SymOff", typ: "UInt16", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem. Zero extend. + {name: "MOVHloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVH", aux: "SymOff", typ: "Int16", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem. Sign extend. + {name: "MOVWZloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVWZ", aux: "SymOff", typ: "UInt32", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem. Zero extend. + {name: "MOVWloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVW", aux: "SymOff", typ: "Int32", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem. Sign extend. + {name: "MOVDloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVD", aux: "SymOff", typ: "UInt64", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load 8 bytes from arg0+arg1+auxint+aux. arg2=mem + {name: "MOVHBRloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVHBR", aux: "SymOff", typ: "Int16", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem. Reverse bytes. + {name: "MOVWBRloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVWBR", aux: "SymOff", typ: "Int32", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem. Reverse bytes. + {name: "MOVDBRloadidx", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVDBR", aux: "SymOff", typ: "Int64", symEffect: "Read", addrSinkArg0: true, addrSinkArg1: true}, // load 8 bytes from arg0+arg1+auxint+aux. arg2=mem. Reverse bytes. + {name: "MOVBstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVB", aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVHstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVH", aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVWstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVW", aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVDstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVD", aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // store 8 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVHBRstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVHBR", aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem. Reverse bytes. + {name: "MOVWBRstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVWBR", aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem. Reverse bytes. + {name: "MOVDBRstoreidx", argLength: 4, reg: gpstoreidx, commutative: true, asm: "MOVDBR", aux: "SymOff", symEffect: "Write", addrSinkArg0: true, addrSinkArg1: true}, // store 8 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem. Reverse bytes. // For storeconst ops, the AuxInt field encodes both // the value to store and an address offset of the store. // Cast AuxInt to a ValAndOff to extract Val and Off fields. - {name: "MOVBstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem - {name: "MOVHstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVH", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store low 2 bytes of ... - {name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store low 4 bytes of ... - {name: "MOVDstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVD", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of ... + {name: "MOVBstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem + {name: "MOVHstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVH", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store low 2 bytes of ... + {name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store low 4 bytes of ... + {name: "MOVDstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVD", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, // store 8 bytes of ... - {name: "CLEAR", argLength: 2, reg: regInfo{inputs: []regMask{ptr, 0}}, asm: "CLEAR", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, symEffect: "Write"}, + {name: "CLEAR", argLength: 2, reg: regInfo{inputs: []regMask{ptr, regMask{}}}, asm: "CLEAR", aux: "SymValAndOff", typ: "Mem", clobberFlags: true, faultOnNilArg0: true, symEffect: "Write", addrSinkArg0: true}, - {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{ptrsp, buildReg("R12"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem - {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{ptr}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem + {name: "CALLtailinter", argLength: -1, reg: regInfo{inputs: []regMask{ptr}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{ptrsp, buildReg("R12"), regMask{}}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{ptr}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem // (InvertFlags (CMP a b)) == (CMP b a) // InvertFlags is a pseudo-op which can't appear in assembly output. @@ -509,25 +510,25 @@ func init() { {name: "LoweredGetCallerPC", reg: gp01, rematerializeable: true}, {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{ptrsp}}, clobberFlags: true, nilCheck: true, faultOnNilArg0: true}, // Round ops to block fused-multiply-add extraction. - {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true}, - {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true}, + {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true, earlyOk: true}, + {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true, earlyOk: true}, // LoweredWB invokes runtime.gcWriteBarrier. arg0=mem, aux=# of buffer entries needed // It saves all GP registers if necessary, // but clobbers R14 (LR) because it's a call, // and also clobbers R1 as the PLT stub does. // Returns a pointer to a write barrier buffer in R9. - {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ gpg) | buildReg("R14") | r1, outputs: []regMask{r9}}, clobberFlags: true, aux: "Int64"}, + {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: callerSave.minus(gpg).union(buildReg("R14")).union(r1), outputs: []regMask{r9}}, clobberFlags: true, aux: "Int64"}, // LoweredPanicBoundsRR takes x and y, two values that caused a bounds check to fail. // the RC and CR versions are used when one of the arguments is a constant. CC is used // when both are constant (normally both 0, as prove derives the fact that a [0] bounds // failure means the length must have also been 0). // AuxInt contains a report code (see PanicBounds in genericOps.go). - {name: "LoweredPanicBoundsRR", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{gp &^ lr, gp &^ lr}}, typ: "Mem", call: true}, // arg0=x, arg1=y, arg2=mem, returns memory. - {name: "LoweredPanicBoundsRC", argLength: 2, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{gp &^ lr}}, typ: "Mem", call: true}, // arg0=x, arg1=mem, returns memory. - {name: "LoweredPanicBoundsCR", argLength: 2, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{gp &^ lr}}, typ: "Mem", call: true}, // arg0=y, arg1=mem, returns memory. - {name: "LoweredPanicBoundsCC", argLength: 1, aux: "PanicBoundsCC", reg: regInfo{}, typ: "Mem", call: true}, // arg0=mem, returns memory. + {name: "LoweredPanicBoundsRR", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{gp.minus(lr), gp.minus(lr)}}, typ: "Mem", call: true}, // arg0=x, arg1=y, arg2=mem, returns memory. + {name: "LoweredPanicBoundsRC", argLength: 2, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{gp.minus(lr)}}, typ: "Mem", call: true}, // arg0=x, arg1=mem, returns memory. + {name: "LoweredPanicBoundsCR", argLength: 2, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{gp.minus(lr)}}, typ: "Mem", call: true}, // arg0=y, arg1=mem, returns memory. + {name: "LoweredPanicBoundsCC", argLength: 1, aux: "PanicBoundsCC", reg: regInfo{}, typ: "Mem", call: true}, // arg0=mem, returns memory. // Constant condition code values. The condition code can be 0, 1, 2 or 3. {name: "FlagEQ"}, // CC=0 (equal) @@ -604,6 +605,7 @@ func init() { asm: "FLOGR", typ: "UInt64", clobberFlags: true, + earlyOk: true, }, // population count @@ -618,6 +620,7 @@ func init() { asm: "POPCNT", typ: "UInt64", clobberFlags: true, + earlyOk: true, }, // unsigned multiplication (64x64 → 128) @@ -631,35 +634,38 @@ func init() { argLength: 2, reg: regInfo{inputs: []regMask{gp, r3}, outputs: []regMask{r2, r3}}, asm: "MLGR", + earlyOk: true, }, // pseudo operations to sum the output of the POPCNT instruction - {name: "SumBytes2", argLength: 1, typ: "UInt8"}, // sum the rightmost 2 bytes in arg0 ignoring overflow - {name: "SumBytes4", argLength: 1, typ: "UInt8"}, // sum the rightmost 4 bytes in arg0 ignoring overflow - {name: "SumBytes8", argLength: 1, typ: "UInt8"}, // sum all the bytes in arg0 ignoring overflow + {name: "SumBytes2", argLength: 1, typ: "UInt8", earlyOk: true}, // sum the rightmost 2 bytes in arg0 ignoring overflow + {name: "SumBytes4", argLength: 1, typ: "UInt8", earlyOk: true}, // sum the rightmost 4 bytes in arg0 ignoring overflow + {name: "SumBytes8", argLength: 1, typ: "UInt8", earlyOk: true}, // sum all the bytes in arg0 ignoring overflow // store multiple { name: "STMG2", argLength: 4, - reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), 0}}, + reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), regMask{}}}, aux: "SymOff", typ: "Mem", asm: "STMG", faultOnNilArg0: true, symEffect: "Write", clobberFlags: true, // TODO(mundaym): currently uses AGFI to handle large offsets + addrSinkArg0: true, }, { name: "STMG3", argLength: 5, - reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), buildReg("R3"), 0}}, + reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), buildReg("R3"), regMask{}}}, aux: "SymOff", typ: "Mem", asm: "STMG", faultOnNilArg0: true, symEffect: "Write", clobberFlags: true, // TODO(mundaym): currently uses AGFI to handle large offsets + addrSinkArg0: true, }, { name: "STMG4", @@ -670,7 +676,7 @@ func init() { buildReg("R2"), buildReg("R3"), buildReg("R4"), - 0, + regMask{}, }}, aux: "SymOff", typ: "Mem", @@ -678,28 +684,31 @@ func init() { faultOnNilArg0: true, symEffect: "Write", clobberFlags: true, // TODO(mundaym): currently uses AGFI to handle large offsets + addrSinkArg0: true, }, { name: "STM2", argLength: 4, - reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), 0}}, + reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), regMask{}}}, aux: "SymOff", typ: "Mem", asm: "STMY", faultOnNilArg0: true, symEffect: "Write", clobberFlags: true, // TODO(mundaym): currently uses AGFI to handle large offsets + addrSinkArg0: true, }, { name: "STM3", argLength: 5, - reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), buildReg("R3"), 0}}, + reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), buildReg("R3"), regMask{}}}, aux: "SymOff", typ: "Mem", asm: "STMY", faultOnNilArg0: true, symEffect: "Write", clobberFlags: true, // TODO(mundaym): currently uses AGFI to handle large offsets + addrSinkArg0: true, }, { name: "STM4", @@ -710,7 +719,7 @@ func init() { buildReg("R2"), buildReg("R3"), buildReg("R4"), - 0, + regMask{}, }}, aux: "SymOff", typ: "Mem", @@ -718,6 +727,7 @@ func init() { faultOnNilArg0: true, symEffect: "Write", clobberFlags: true, // TODO(mundaym): currently uses AGFI to handle large offsets + addrSinkArg0: true, }, // large move @@ -746,6 +756,9 @@ func init() { typ: "Mem", faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + // TODO: could use addrSinkArg2 here. }, // large clear @@ -771,6 +784,8 @@ func init() { clobberFlags: true, typ: "Mem", faultOnNilArg0: true, + addrSinkArg0: true, + addrSinkArg1: true, }, } @@ -812,16 +827,18 @@ func init() { } archs = append(archs, arch{ - name: "S390X", - pkg: "cmd/internal/obj/s390x", - genfile: "../../s390x/ssa.go", - ops: S390Xops, - blocks: S390Xblocks, - regnames: regNamesS390X, - gpregmask: gp, - fpregmask: fp, - framepointerreg: -1, // not used - linkreg: int8(num["R14"]), + name: "S390X", + pkg: "cmd/internal/obj/s390x", + genfile: "../../s390x/ssa.go", + ops: S390Xops, + blocks: S390Xblocks, + regnames: regNamesS390X, + ParamIntRegNames: "R2 R3 R4 R5 R6 R7 R8 R9", + ParamFloatRegNames: "F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15", + gpregmask: gp, + fpregmask: fp, + framepointerreg: -1, // not used + linkreg: int8(num["R14"]), imports: []string{ "cmd/internal/obj/s390x", }, diff --git a/src/cmd/compile/internal/ssa/_gen/Wasm.rules b/src/cmd/compile/internal/ssa/_gen/Wasm.rules index f632a01109f764..a2192dcf478467 100644 --- a/src/cmd/compile/internal/ssa/_gen/Wasm.rules +++ b/src/cmd/compile/internal/ssa/_gen/Wasm.rules @@ -2,6 +2,8 @@ // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. +(Last ___) => v.Args[len(v.Args)-1] + // Lowering arithmetic (Add(64|32|16|8|Ptr) ...) => (I64Add ...) (Add(64|32)F ...) => (F(64|32)Add ...) @@ -44,6 +46,37 @@ (Not ...) => (I64Eqz ...) +(Avg64u x y) => (I64Add (I64ShrU (I64Sub x y) (I64Const [1])) y) + +// High word of multiply without carry bits; see Hacker's Delight, 2nd. ed, Figure 8-2, p. 174. +(Hmul64 x y) => + (Last + x0: (ZeroExt32to64 x) + x1: (I64ShrS x (I64Const [32])) + y0: (ZeroExt32to64 y) + y1: (I64ShrS y (I64Const [32])) + x0y0: (I64Mul x0 y0) + tt: (I64Add (I64Mul x1 y0) (I64ShrU x0y0 (I64Const [32]))) + w1: (I64Add (I64Mul x0 y1) (ZeroExt32to64 tt)) + w2: (I64ShrS tt (I64Const [32])) + (I64Add (I64Add (I64Mul x1 y1) w2) (I64ShrS w1 (I64Const [32])))) + +// Same as Hmul64 but signed shifts now unsigned. +(Hmul64u x y) => + (Last + x0: (ZeroExt32to64 x) + x1: (I64ShrU x (I64Const [32])) + y0: (ZeroExt32to64 y) + y1: (I64ShrU y (I64Const [32])) + w0: (I64Mul x0 y0) + tt: (I64Add (I64Mul x1 y0) (I64ShrU w0 (I64Const [32]))) + w1: (I64Add (I64Mul x0 y1) (ZeroExt32to64 tt)) + w2: (I64ShrU tt (I64Const [32])) + hi: (I64Add (I64Add (I64Mul x1 y1) w2) (I64ShrU w1 (I64Const [32])))) + +(Select0 (Mul64uhilo x y)) => (Hmul64u x y) +(Select1 (Mul64uhilo x y)) => (I64Mul x y) + // Lowering pointer arithmetic (OffPtr ...) => (I64AddConst ...) @@ -190,6 +223,7 @@ // Lowering loads (Load ptr mem) && is32BitFloat(t) => (F32Load ptr mem) (Load ptr mem) && is64BitFloat(t) => (F64Load ptr mem) +(Load ptr mem) && t.Size() == 16 => (V128Load ptr mem) (Load ptr mem) && t.Size() == 8 => (I64Load ptr mem) (Load ptr mem) && t.Size() == 4 && !t.IsSigned() => (I64Load32U ptr mem) (Load ptr mem) && t.Size() == 4 && t.IsSigned() => (I64Load32S ptr mem) @@ -201,11 +235,14 @@ // Lowering stores (Store {t} ptr val mem) && is64BitFloat(t) => (F64Store ptr val mem) (Store {t} ptr val mem) && is32BitFloat(t) => (F32Store ptr val mem) +(Store {t} ptr val mem) && t.Size() == 16 => (V128Store ptr val mem) (Store {t} ptr val mem) && t.Size() == 8 => (I64Store ptr val mem) (Store {t} ptr val mem) && t.Size() == 4 => (I64Store32 ptr val mem) (Store {t} ptr val mem) && t.Size() == 2 => (I64Store16 ptr val mem) (Store {t} ptr val mem) && t.Size() == 1 => (I64Store8 ptr val mem) +(ZeroSIMD ) => (V128Zero ) + // Lowering moves (Move [0] _ _ mem) => mem (Move [1] dst src mem) => (I64Store8 dst (I64Load8U src mem) mem) @@ -290,6 +327,7 @@ (ClosureCall ...) => (LoweredClosureCall ...) (InterCall ...) => (LoweredInterCall ...) (TailCall ...) => (LoweredTailCall ...) +(TailCallInter ...) => (LoweredTailCallInter ...) // Miscellaneous (Convert ...) => (LoweredConvert ...) @@ -316,6 +354,9 @@ (Abs ...) => (F64Abs ...) (Copysign ...) => (F64Copysign ...) +(F32DemoteF64 (F64(Sqrt|Trunc|Ceil|Floor|Nearest|Abs) (F64PromoteF32 x))) => (F32(Sqrt|Trunc|Ceil|Floor|Nearest|Abs) x) +(F32DemoteF64 (F64Copysign (F64PromoteF32 x) (F64PromoteF32 y))) => (F32Copysign x y) + (Sqrt32 ...) => (F32Sqrt ...) (Ctz64 ...) => (I64Ctz ...) @@ -337,6 +378,7 @@ // --- Optimizations --- (I64Add (I64Const [x]) (I64Const [y])) => (I64Const [x + y]) +(I64Sub (I64Const [x]) (I64Const [y])) => (I64Const [x - y]) (I64Mul (I64Const [x]) (I64Const [y])) => (I64Const [x * y]) (I64And (I64Const [x]) (I64Const [y])) => (I64Const [x & y]) (I64Or (I64Const [x]) (I64Const [y])) => (I64Const [x | y]) @@ -352,6 +394,35 @@ (I64ShrU (I64Const [x]) (I64Const [y])) => (I64Const [int64(uint64(x) >> uint64(y))]) (I64ShrS (I64Const [x]) (I64Const [y])) => (I64Const [x >> uint64(y)]) +// Identity and absorption rules for AND/OR/XOR/MUL. +// These fire on nodes created during or after lowering. +(I64And x (I64Const [-1])) => x +(I64And x (I64Const [0])) => (I64Const [0]) +(I64Or x (I64Const [0])) => x +(I64Or x (I64Const [-1])) => (I64Const [-1]) +(I64Xor x (I64Const [0])) => x +(I64Mul x (I64Const [0])) => (I64Const [0]) +(I64Mul x (I64Const [1])) => x + +// Double-mask elimination: cascaded zero-extensions produce +// (I64And (I64And x C1) C2) which can be collapsed to a single mask. +(I64And (I64And x (I64Const [c1])) (I64Const [c2])) => (I64And x (I64Const [c1 & c2])) + +// Redundant sign-extensions: idempotent and narrower-subsumes-wider. +(I64Extend32S (I64Extend32S x)) => (I64Extend32S x) +(I64Extend16S (I64Extend16S x)) => (I64Extend16S x) +(I64Extend8S (I64Extend8S x)) => (I64Extend8S x) +(I64Extend32S (I64Extend16S x)) => (I64Extend16S x) +(I64Extend32S (I64Extend8S x)) => (I64Extend8S x) +(I64Extend16S (I64Extend8S x)) => (I64Extend8S x) + +// Sign-extend of a value already zero-extended from fewer bits is a no-op. +// E.g. (I64Extend32S (I64And x (I64Const [0xff]))) — top 33 bits are already +// zero, so sign-extending from 32 is identity. +(I64Extend32S x:(I64And _ (I64Const [c]))) && c >= 0 && int64(int32(c)) == c => x +(I64Extend16S x:(I64And _ (I64Const [c]))) && c >= 0 && int64(int16(c)) == c => x +(I64Extend8S x:(I64And _ (I64Const [c]))) && c >= 0 && int64(int8(c)) == c => x + // TODO: declare these operations as commutative and get rid of these rules? (I64Add (I64Const [x]) y) && y.Op != OpWasmI64Const => (I64Add y (I64Const [x])) (I64Mul (I64Const [x]) y) && y.Op != OpWasmI64Const => (I64Mul y (I64Const [x])) diff --git a/src/cmd/compile/internal/ssa/_gen/WasmOps.go b/src/cmd/compile/internal/ssa/_gen/WasmOps.go index 45bbed5f520201..706a2fc3d3abc7 100644 --- a/src/cmd/compile/internal/ssa/_gen/WasmOps.go +++ b/src/cmd/compile/internal/ssa/_gen/WasmOps.go @@ -58,6 +58,23 @@ var regNamesWasm = []string{ "F30", "F31", + "V0", + "V1", + "V2", + "V3", + "V4", + "V5", + "V6", + "V7", + "V8", + "V9", + "V10", + "V11", + "V12", + "V13", + "V14", + "V15", + "SP", "g", @@ -67,18 +84,15 @@ var regNamesWasm = []string{ func init() { // Make map from reg names to reg integers. - if len(regNamesWasm) > 64 { - panic("too many registers") - } num := map[string]int{} for i, name := range regNamesWasm { num[name] = i } buildReg := func(s string) regMask { - m := regMask(0) + m := regMask{} for _, r := range strings.Split(s, " ") { if n, ok := num[r]; ok { - m |= regMask(1) << uint(n) + m = m.addReg(uint(n)) continue } panic("register " + r + " not found") @@ -90,11 +104,12 @@ func init() { gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15") fp32 = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15") fp64 = buildReg("F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31") - gpsp = gp | buildReg("SP") - gpspsb = gpsp | buildReg("SB") + v128 = buildReg("V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15") + gpsp = gp.union(buildReg("SP")) + gpspsb = gpsp.union(buildReg("SB")) // The "registers", which are actually local variables, can get clobbered // if we're switching goroutines, because it unwinds the WebAssembly stack. - callerSave = gp | fp32 | fp64 | buildReg("g") + callerSave = gp.union(fp32).union(fp64).union(v128).union(buildReg("g")) ) // Common regInfo @@ -111,23 +126,47 @@ func init() { fp64_11 = regInfo{inputs: []regMask{fp64}, outputs: []regMask{fp64}} fp64_21 = regInfo{inputs: []regMask{fp64, fp64}, outputs: []regMask{fp64}} fp64_21gp = regInfo{inputs: []regMask{fp64, fp64}, outputs: []regMask{gp}} - gpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: []regMask{gp}} - gpstore = regInfo{inputs: []regMask{gpspsb, gpsp, 0}} - fp32load = regInfo{inputs: []regMask{gpspsb, 0}, outputs: []regMask{fp32}} - fp32store = regInfo{inputs: []regMask{gpspsb, fp32, 0}} - fp64load = regInfo{inputs: []regMask{gpspsb, 0}, outputs: []regMask{fp64}} - fp64store = regInfo{inputs: []regMask{gpspsb, fp64, 0}} + + gpload = regInfo{inputs: []regMask{gpspsb, regMask{}}, outputs: []regMask{gp}} + gpstore = regInfo{inputs: []regMask{gpspsb, gpsp, regMask{}}} + fp32load = regInfo{inputs: []regMask{gpspsb, regMask{}}, outputs: []regMask{fp32}} + fp32store = regInfo{inputs: []regMask{gpspsb, fp32, regMask{}}} + fp64load = regInfo{inputs: []regMask{gpspsb, regMask{}}, outputs: []regMask{fp64}} + fp64store = regInfo{inputs: []regMask{gpspsb, fp64, regMask{}}} + + v01 = regInfo{inputs: nil, outputs: []regMask{v128}} + vload = regInfo{inputs: []regMask{gpspsb, regMask{}}, outputs: []regMask{v128}} + vstore = regInfo{inputs: []regMask{gpspsb, v128, regMask{}}} + + v11 = regInfo{inputs: []regMask{v128}, outputs: []regMask{v128}} + v21 = regInfo{inputs: []regMask{v128, v128}, outputs: []regMask{v128}} + v31 = regInfo{inputs: []regMask{v128, v128, v128}, outputs: []regMask{v128}} + + v11gp = regInfo{inputs: []regMask{v128}, outputs: []regMask{gp}} + v11fp32 = regInfo{inputs: []regMask{v128}, outputs: []regMask{fp32}} + v11fp64 = regInfo{inputs: []regMask{v128}, outputs: []regMask{fp64}} + + v2gpv = regInfo{inputs: []regMask{v128, v128, gp}, outputs: []regMask{v128}} + + v1gpv = regInfo{inputs: []regMask{v128, gp}, outputs: []regMask{v128}} + v1fp32v = regInfo{inputs: []regMask{v128, fp32}, outputs: []regMask{v128}} + v1fp64v = regInfo{inputs: []regMask{v128, fp64}, outputs: []regMask{v128}} + + gpv = regInfo{inputs: []regMask{gp}, outputs: []regMask{v128}} + fp32v = regInfo{inputs: []regMask{fp32}, outputs: []regMask{v128}} + fp64v = regInfo{inputs: []regMask{fp64}, outputs: []regMask{v128}} ) var WasmOps = []opData{ - {name: "LoweredStaticCall", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "LoweredTailCall", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem - {name: "LoweredClosureCall", argLength: 3, reg: regInfo{inputs: []regMask{gp, gp, 0}, clobbers: callerSave}, aux: "CallOff", call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem - {name: "LoweredInterCall", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "LoweredStaticCall", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem + {name: "LoweredTailCall", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem + {name: "LoweredTailCallInter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + {name: "LoweredClosureCall", argLength: 3, reg: regInfo{inputs: []regMask{gp, gp, regMask{}}, clobbers: callerSave}, aux: "CallOff", call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem + {name: "LoweredInterCall", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem - {name: "LoweredAddr", argLength: 1, reg: gp11, aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // returns base+aux+auxint, arg0=base - {name: "LoweredMove", argLength: 3, reg: regInfo{inputs: []regMask{gp, gp}}, aux: "Int64"}, // large move. arg0=dst, arg1=src, arg2=mem, auxint=len, returns mem - {name: "LoweredZero", argLength: 2, reg: regInfo{inputs: []regMask{gp}}, aux: "Int64"}, // large zeroing. arg0=start, arg1=mem, auxint=len, returns mem + {name: "LoweredAddr", argLength: 1, reg: gp11, aux: "SymOff", rematerializeable: true, symEffect: "Addr", earlyOk: true}, // returns base+aux+auxint, arg0=base + {name: "LoweredMove", argLength: 3, reg: regInfo{inputs: []regMask{gp, gp}}, aux: "Int64", addrSinkArg0: true, addrSinkArg1: true}, // large move. arg0=dst, arg1=src, arg2=mem, auxint=len, returns mem + {name: "LoweredZero", argLength: 2, reg: regInfo{inputs: []regMask{gp}}, aux: "Int64", addrSinkArg0: true}, // large zeroing. arg0=start, arg1=mem, auxint=len, returns mem {name: "LoweredGetClosurePtr", reg: gp01}, // returns wasm.REG_CTXT, the closure pointer {name: "LoweredGetCallerPC", reg: gp01, rematerializeable: true}, // returns the PC of the caller of the current function @@ -146,129 +185,138 @@ func init() { // The following are native WebAssembly instructions, see https://webassembly.github.io/spec/core/syntax/instructions.html - {name: "Select", asm: "Select", argLength: 3, reg: gp31}, // returns arg0 if arg2 != 0, otherwise returns arg1 - - {name: "I64Load8U", asm: "I64Load8U", argLength: 2, reg: gpload, aux: "Int64", typ: "UInt8"}, // read unsigned 8-bit integer from address arg0+aux, arg1=mem - {name: "I64Load8S", asm: "I64Load8S", argLength: 2, reg: gpload, aux: "Int64", typ: "Int8"}, // read signed 8-bit integer from address arg0+aux, arg1=mem - {name: "I64Load16U", asm: "I64Load16U", argLength: 2, reg: gpload, aux: "Int64", typ: "UInt16"}, // read unsigned 16-bit integer from address arg0+aux, arg1=mem - {name: "I64Load16S", asm: "I64Load16S", argLength: 2, reg: gpload, aux: "Int64", typ: "Int16"}, // read signed 16-bit integer from address arg0+aux, arg1=mem - {name: "I64Load32U", asm: "I64Load32U", argLength: 2, reg: gpload, aux: "Int64", typ: "UInt32"}, // read unsigned 32-bit integer from address arg0+aux, arg1=mem - {name: "I64Load32S", asm: "I64Load32S", argLength: 2, reg: gpload, aux: "Int64", typ: "Int32"}, // read signed 32-bit integer from address arg0+aux, arg1=mem - {name: "I64Load", asm: "I64Load", argLength: 2, reg: gpload, aux: "Int64", typ: "UInt64"}, // read 64-bit integer from address arg0+aux, arg1=mem - {name: "I64Store8", asm: "I64Store8", argLength: 3, reg: gpstore, aux: "Int64", typ: "Mem"}, // store 8-bit integer arg1 at address arg0+aux, arg2=mem, returns mem - {name: "I64Store16", asm: "I64Store16", argLength: 3, reg: gpstore, aux: "Int64", typ: "Mem"}, // store 16-bit integer arg1 at address arg0+aux, arg2=mem, returns mem - {name: "I64Store32", asm: "I64Store32", argLength: 3, reg: gpstore, aux: "Int64", typ: "Mem"}, // store 32-bit integer arg1 at address arg0+aux, arg2=mem, returns mem - {name: "I64Store", asm: "I64Store", argLength: 3, reg: gpstore, aux: "Int64", typ: "Mem"}, // store 64-bit integer arg1 at address arg0+aux, arg2=mem, returns mem - - {name: "F32Load", asm: "F32Load", argLength: 2, reg: fp32load, aux: "Int64", typ: "Float32"}, // read 32-bit float from address arg0+aux, arg1=mem - {name: "F64Load", asm: "F64Load", argLength: 2, reg: fp64load, aux: "Int64", typ: "Float64"}, // read 64-bit float from address arg0+aux, arg1=mem - {name: "F32Store", asm: "F32Store", argLength: 3, reg: fp32store, aux: "Int64", typ: "Mem"}, // store 32-bit float arg1 at address arg0+aux, arg2=mem, returns mem - {name: "F64Store", asm: "F64Store", argLength: 3, reg: fp64store, aux: "Int64", typ: "Mem"}, // store 64-bit float arg1 at address arg0+aux, arg2=mem, returns mem - - {name: "I64Const", reg: gp01, aux: "Int64", rematerializeable: true, typ: "Int64"}, // returns the constant integer aux - {name: "F32Const", reg: fp32_01, aux: "Float32", rematerializeable: true, typ: "Float32"}, // returns the constant float aux - {name: "F64Const", reg: fp64_01, aux: "Float64", rematerializeable: true, typ: "Float64"}, // returns the constant float aux - - {name: "I64Eqz", asm: "I64Eqz", argLength: 1, reg: gp11, typ: "Bool"}, // arg0 == 0 - {name: "I64Eq", asm: "I64Eq", argLength: 2, reg: gp21, typ: "Bool"}, // arg0 == arg1 - {name: "I64Ne", asm: "I64Ne", argLength: 2, reg: gp21, typ: "Bool"}, // arg0 != arg1 - {name: "I64LtS", asm: "I64LtS", argLength: 2, reg: gp21, typ: "Bool"}, // arg0 < arg1 (signed) - {name: "I64LtU", asm: "I64LtU", argLength: 2, reg: gp21, typ: "Bool"}, // arg0 < arg1 (unsigned) - {name: "I64GtS", asm: "I64GtS", argLength: 2, reg: gp21, typ: "Bool"}, // arg0 > arg1 (signed) - {name: "I64GtU", asm: "I64GtU", argLength: 2, reg: gp21, typ: "Bool"}, // arg0 > arg1 (unsigned) - {name: "I64LeS", asm: "I64LeS", argLength: 2, reg: gp21, typ: "Bool"}, // arg0 <= arg1 (signed) - {name: "I64LeU", asm: "I64LeU", argLength: 2, reg: gp21, typ: "Bool"}, // arg0 <= arg1 (unsigned) - {name: "I64GeS", asm: "I64GeS", argLength: 2, reg: gp21, typ: "Bool"}, // arg0 >= arg1 (signed) - {name: "I64GeU", asm: "I64GeU", argLength: 2, reg: gp21, typ: "Bool"}, // arg0 >= arg1 (unsigned) - - {name: "F32Eq", asm: "F32Eq", argLength: 2, reg: fp32_21gp, typ: "Bool"}, // arg0 == arg1 - {name: "F32Ne", asm: "F32Ne", argLength: 2, reg: fp32_21gp, typ: "Bool"}, // arg0 != arg1 - {name: "F32Lt", asm: "F32Lt", argLength: 2, reg: fp32_21gp, typ: "Bool"}, // arg0 < arg1 - {name: "F32Gt", asm: "F32Gt", argLength: 2, reg: fp32_21gp, typ: "Bool"}, // arg0 > arg1 - {name: "F32Le", asm: "F32Le", argLength: 2, reg: fp32_21gp, typ: "Bool"}, // arg0 <= arg1 - {name: "F32Ge", asm: "F32Ge", argLength: 2, reg: fp32_21gp, typ: "Bool"}, // arg0 >= arg1 - - {name: "F64Eq", asm: "F64Eq", argLength: 2, reg: fp64_21gp, typ: "Bool"}, // arg0 == arg1 - {name: "F64Ne", asm: "F64Ne", argLength: 2, reg: fp64_21gp, typ: "Bool"}, // arg0 != arg1 - {name: "F64Lt", asm: "F64Lt", argLength: 2, reg: fp64_21gp, typ: "Bool"}, // arg0 < arg1 - {name: "F64Gt", asm: "F64Gt", argLength: 2, reg: fp64_21gp, typ: "Bool"}, // arg0 > arg1 - {name: "F64Le", asm: "F64Le", argLength: 2, reg: fp64_21gp, typ: "Bool"}, // arg0 <= arg1 - {name: "F64Ge", asm: "F64Ge", argLength: 2, reg: fp64_21gp, typ: "Bool"}, // arg0 >= arg1 - - {name: "I64Add", asm: "I64Add", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 + arg1 - {name: "I64AddConst", asm: "I64Add", argLength: 1, reg: gp11, aux: "Int64", typ: "Int64"}, // arg0 + aux - {name: "I64Sub", asm: "I64Sub", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 - arg1 - {name: "I64Mul", asm: "I64Mul", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 * arg1 - {name: "I64DivS", asm: "I64DivS", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 / arg1 (signed) - {name: "I64DivU", asm: "I64DivU", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 / arg1 (unsigned) - {name: "I64RemS", asm: "I64RemS", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 % arg1 (signed) - {name: "I64RemU", asm: "I64RemU", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 % arg1 (unsigned) - {name: "I64And", asm: "I64And", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 & arg1 - {name: "I64Or", asm: "I64Or", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 | arg1 - {name: "I64Xor", asm: "I64Xor", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 ^ arg1 - {name: "I64Shl", asm: "I64Shl", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 << (arg1 % 64) - {name: "I64ShrS", asm: "I64ShrS", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 >> (arg1 % 64) (signed) - {name: "I64ShrU", asm: "I64ShrU", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 >> (arg1 % 64) (unsigned) - - {name: "F32Neg", asm: "F32Neg", argLength: 1, reg: fp32_11, typ: "Float32"}, // -arg0 - {name: "F32Add", asm: "F32Add", argLength: 2, reg: fp32_21, typ: "Float32"}, // arg0 + arg1 - {name: "F32Sub", asm: "F32Sub", argLength: 2, reg: fp32_21, typ: "Float32"}, // arg0 - arg1 - {name: "F32Mul", asm: "F32Mul", argLength: 2, reg: fp32_21, typ: "Float32"}, // arg0 * arg1 - {name: "F32Div", asm: "F32Div", argLength: 2, reg: fp32_21, typ: "Float32"}, // arg0 / arg1 - - {name: "F64Neg", asm: "F64Neg", argLength: 1, reg: fp64_11, typ: "Float64"}, // -arg0 - {name: "F64Add", asm: "F64Add", argLength: 2, reg: fp64_21, typ: "Float64"}, // arg0 + arg1 - {name: "F64Sub", asm: "F64Sub", argLength: 2, reg: fp64_21, typ: "Float64"}, // arg0 - arg1 - {name: "F64Mul", asm: "F64Mul", argLength: 2, reg: fp64_21, typ: "Float64"}, // arg0 * arg1 - {name: "F64Div", asm: "F64Div", argLength: 2, reg: fp64_21, typ: "Float64"}, // arg0 / arg1 - - {name: "I64TruncSatF64S", asm: "I64TruncSatF64S", argLength: 1, reg: regInfo{inputs: []regMask{fp64}, outputs: []regMask{gp}}, typ: "Int64"}, // truncates the float arg0 to a signed integer (saturating) - {name: "I64TruncSatF64U", asm: "I64TruncSatF64U", argLength: 1, reg: regInfo{inputs: []regMask{fp64}, outputs: []regMask{gp}}, typ: "Int64"}, // truncates the float arg0 to an unsigned integer (saturating) - {name: "I64TruncSatF32S", asm: "I64TruncSatF32S", argLength: 1, reg: regInfo{inputs: []regMask{fp32}, outputs: []regMask{gp}}, typ: "Int64"}, // truncates the float arg0 to a signed integer (saturating) - {name: "I64TruncSatF32U", asm: "I64TruncSatF32U", argLength: 1, reg: regInfo{inputs: []regMask{fp32}, outputs: []regMask{gp}}, typ: "Int64"}, // truncates the float arg0 to an unsigned integer (saturating) - {name: "F32ConvertI64S", asm: "F32ConvertI64S", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{fp32}}, typ: "Float32"}, // converts the signed integer arg0 to a float - {name: "F32ConvertI64U", asm: "F32ConvertI64U", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{fp32}}, typ: "Float32"}, // converts the unsigned integer arg0 to a float - {name: "F64ConvertI64S", asm: "F64ConvertI64S", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{fp64}}, typ: "Float64"}, // converts the signed integer arg0 to a float - {name: "F64ConvertI64U", asm: "F64ConvertI64U", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{fp64}}, typ: "Float64"}, // converts the unsigned integer arg0 to a float - {name: "F32DemoteF64", asm: "F32DemoteF64", argLength: 1, reg: regInfo{inputs: []regMask{fp64}, outputs: []regMask{fp32}}, typ: "Float32"}, - {name: "F64PromoteF32", asm: "F64PromoteF32", argLength: 1, reg: regInfo{inputs: []regMask{fp32}, outputs: []regMask{fp64}}, typ: "Float64"}, - - {name: "I64Extend8S", asm: "I64Extend8S", argLength: 1, reg: gp11, typ: "Int64"}, // sign-extend arg0 from 8 to 64 bit - {name: "I64Extend16S", asm: "I64Extend16S", argLength: 1, reg: gp11, typ: "Int64"}, // sign-extend arg0 from 16 to 64 bit - {name: "I64Extend32S", asm: "I64Extend32S", argLength: 1, reg: gp11, typ: "Int64"}, // sign-extend arg0 from 32 to 64 bit - - {name: "F32Sqrt", asm: "F32Sqrt", argLength: 1, reg: fp32_11, typ: "Float32"}, // sqrt(arg0) - {name: "F32Trunc", asm: "F32Trunc", argLength: 1, reg: fp32_11, typ: "Float32"}, // trunc(arg0) - {name: "F32Ceil", asm: "F32Ceil", argLength: 1, reg: fp32_11, typ: "Float32"}, // ceil(arg0) - {name: "F32Floor", asm: "F32Floor", argLength: 1, reg: fp32_11, typ: "Float32"}, // floor(arg0) - {name: "F32Nearest", asm: "F32Nearest", argLength: 1, reg: fp32_11, typ: "Float32"}, // round(arg0) - {name: "F32Abs", asm: "F32Abs", argLength: 1, reg: fp32_11, typ: "Float32"}, // abs(arg0) - {name: "F32Copysign", asm: "F32Copysign", argLength: 2, reg: fp32_21, typ: "Float32"}, // copysign(arg0, arg1) - - {name: "F64Sqrt", asm: "F64Sqrt", argLength: 1, reg: fp64_11, typ: "Float64"}, // sqrt(arg0) - {name: "F64Trunc", asm: "F64Trunc", argLength: 1, reg: fp64_11, typ: "Float64"}, // trunc(arg0) - {name: "F64Ceil", asm: "F64Ceil", argLength: 1, reg: fp64_11, typ: "Float64"}, // ceil(arg0) - {name: "F64Floor", asm: "F64Floor", argLength: 1, reg: fp64_11, typ: "Float64"}, // floor(arg0) - {name: "F64Nearest", asm: "F64Nearest", argLength: 1, reg: fp64_11, typ: "Float64"}, // round(arg0) - {name: "F64Abs", asm: "F64Abs", argLength: 1, reg: fp64_11, typ: "Float64"}, // abs(arg0) - {name: "F64Copysign", asm: "F64Copysign", argLength: 2, reg: fp64_21, typ: "Float64"}, // copysign(arg0, arg1) - - {name: "I64Ctz", asm: "I64Ctz", argLength: 1, reg: gp11, typ: "Int64"}, // ctz(arg0) - {name: "I64Clz", asm: "I64Clz", argLength: 1, reg: gp11, typ: "Int64"}, // clz(arg0) - {name: "I32Rotl", asm: "I32Rotl", argLength: 2, reg: gp21, typ: "Int32"}, // rotl(arg0, arg1) - {name: "I64Rotl", asm: "I64Rotl", argLength: 2, reg: gp21, typ: "Int64"}, // rotl(arg0, arg1) - {name: "I64Popcnt", asm: "I64Popcnt", argLength: 1, reg: gp11, typ: "Int64"}, // popcnt(arg0) + {name: "Select", asm: "Select", argLength: 3, reg: gp31, earlyOk: true}, // returns arg0 if arg2 != 0, otherwise returns arg1 + {name: "SelectV", asm: "Select", argLength: 3, reg: v2gpv, earlyOk: true}, // returns arg0 if arg2 != 0, otherwise returns arg1 + + {name: "I64Load8U", asm: "I64Load8U", argLength: 2, reg: gpload, aux: "Int64", typ: "UInt8", addrSinkArg0: true}, // read unsigned 8-bit integer from address arg0+aux, arg1=mem + {name: "I64Load8S", asm: "I64Load8S", argLength: 2, reg: gpload, aux: "Int64", typ: "Int8", addrSinkArg0: true}, // read signed 8-bit integer from address arg0+aux, arg1=mem + {name: "I64Load16U", asm: "I64Load16U", argLength: 2, reg: gpload, aux: "Int64", typ: "UInt16", addrSinkArg0: true}, // read unsigned 16-bit integer from address arg0+aux, arg1=mem + {name: "I64Load16S", asm: "I64Load16S", argLength: 2, reg: gpload, aux: "Int64", typ: "Int16", addrSinkArg0: true}, // read signed 16-bit integer from address arg0+aux, arg1=mem + {name: "I64Load32U", asm: "I64Load32U", argLength: 2, reg: gpload, aux: "Int64", typ: "UInt32", addrSinkArg0: true}, // read unsigned 32-bit integer from address arg0+aux, arg1=mem + {name: "I64Load32S", asm: "I64Load32S", argLength: 2, reg: gpload, aux: "Int64", typ: "Int32", addrSinkArg0: true}, // read signed 32-bit integer from address arg0+aux, arg1=mem + {name: "I64Load", asm: "I64Load", argLength: 2, reg: gpload, aux: "Int64", typ: "UInt64", addrSinkArg0: true}, // read 64-bit integer from address arg0+aux, arg1=mem + {name: "I64Store8", asm: "I64Store8", argLength: 3, reg: gpstore, aux: "Int64", typ: "Mem", addrSinkArg0: true}, // store 8-bit integer arg1 at address arg0+aux, arg2=mem, returns mem + {name: "I64Store16", asm: "I64Store16", argLength: 3, reg: gpstore, aux: "Int64", typ: "Mem", addrSinkArg0: true}, // store 16-bit integer arg1 at address arg0+aux, arg2=mem, returns mem + {name: "I64Store32", asm: "I64Store32", argLength: 3, reg: gpstore, aux: "Int64", typ: "Mem", addrSinkArg0: true}, // store 32-bit integer arg1 at address arg0+aux, arg2=mem, returns mem + {name: "I64Store", asm: "I64Store", argLength: 3, reg: gpstore, aux: "Int64", typ: "Mem", addrSinkArg0: true}, // store 64-bit integer arg1 at address arg0+aux, arg2=mem, returns mem + + {name: "F32Load", asm: "F32Load", argLength: 2, reg: fp32load, aux: "Int64", typ: "Float32", addrSinkArg0: true}, // read 32-bit float from address arg0+aux, arg1=mem + {name: "F64Load", asm: "F64Load", argLength: 2, reg: fp64load, aux: "Int64", typ: "Float64", addrSinkArg0: true}, // read 64-bit float from address arg0+aux, arg1=mem + {name: "F32Store", asm: "F32Store", argLength: 3, reg: fp32store, aux: "Int64", typ: "Mem", addrSinkArg0: true}, // store 32-bit float arg1 at address arg0+aux, arg2=mem, returns mem + {name: "F64Store", asm: "F64Store", argLength: 3, reg: fp64store, aux: "Int64", typ: "Mem", addrSinkArg0: true}, // store 64-bit float arg1 at address arg0+aux, arg2=mem, returns mem + + {name: "I64Const", reg: gp01, aux: "Int64", rematerializeable: true, typ: "Int64", earlyOk: true}, // returns the constant integer aux + {name: "F32Const", reg: fp32_01, aux: "Float32", rematerializeable: true, typ: "Float32", earlyOk: true}, // returns the constant float aux + {name: "F64Const", reg: fp64_01, aux: "Float64", rematerializeable: true, typ: "Float64", earlyOk: true}, // returns the constant float aux + + {name: "V128Load", asm: "V128Load", argLength: 2, reg: vload, aux: "Int64", typ: "V128", addrSinkArg0: true}, // read 128-bit vector from address arg0+aux, arg1=mem + {name: "V128Store", asm: "V128Store", argLength: 3, reg: vstore, aux: "Int64", typ: "Mem", addrSinkArg0: true}, // store 128-bit vector arg1 at address arg0+aux, arg2=mem, returns mem + {name: "V128Zero", argLength: 0, reg: v01, asm: "V128Const", typ: "V128"}, + + {name: "I64Eqz", asm: "I64Eqz", argLength: 1, reg: gp11, typ: "Bool", earlyOk: true}, // arg0 == 0 + {name: "I64Eq", asm: "I64Eq", argLength: 2, reg: gp21, typ: "Bool", earlyOk: true}, // arg0 == arg1 + {name: "I64Ne", asm: "I64Ne", argLength: 2, reg: gp21, typ: "Bool", earlyOk: true}, // arg0 != arg1 + {name: "I64LtS", asm: "I64LtS", argLength: 2, reg: gp21, typ: "Bool", earlyOk: true}, // arg0 < arg1 (signed) + {name: "I64LtU", asm: "I64LtU", argLength: 2, reg: gp21, typ: "Bool", earlyOk: true}, // arg0 < arg1 (unsigned) + {name: "I64GtS", asm: "I64GtS", argLength: 2, reg: gp21, typ: "Bool", earlyOk: true}, // arg0 > arg1 (signed) + {name: "I64GtU", asm: "I64GtU", argLength: 2, reg: gp21, typ: "Bool", earlyOk: true}, // arg0 > arg1 (unsigned) + {name: "I64LeS", asm: "I64LeS", argLength: 2, reg: gp21, typ: "Bool", earlyOk: true}, // arg0 <= arg1 (signed) + {name: "I64LeU", asm: "I64LeU", argLength: 2, reg: gp21, typ: "Bool", earlyOk: true}, // arg0 <= arg1 (unsigned) + {name: "I64GeS", asm: "I64GeS", argLength: 2, reg: gp21, typ: "Bool", earlyOk: true}, // arg0 >= arg1 (signed) + {name: "I64GeU", asm: "I64GeU", argLength: 2, reg: gp21, typ: "Bool", earlyOk: true}, // arg0 >= arg1 (unsigned) + + {name: "F32Eq", asm: "F32Eq", argLength: 2, reg: fp32_21gp, typ: "Bool", earlyOk: true}, // arg0 == arg1 + {name: "F32Ne", asm: "F32Ne", argLength: 2, reg: fp32_21gp, typ: "Bool", earlyOk: true}, // arg0 != arg1 + {name: "F32Lt", asm: "F32Lt", argLength: 2, reg: fp32_21gp, typ: "Bool", earlyOk: true}, // arg0 < arg1 + {name: "F32Gt", asm: "F32Gt", argLength: 2, reg: fp32_21gp, typ: "Bool", earlyOk: true}, // arg0 > arg1 + {name: "F32Le", asm: "F32Le", argLength: 2, reg: fp32_21gp, typ: "Bool", earlyOk: true}, // arg0 <= arg1 + {name: "F32Ge", asm: "F32Ge", argLength: 2, reg: fp32_21gp, typ: "Bool", earlyOk: true}, // arg0 >= arg1 + + {name: "F64Eq", asm: "F64Eq", argLength: 2, reg: fp64_21gp, typ: "Bool", earlyOk: true}, // arg0 == arg1 + {name: "F64Ne", asm: "F64Ne", argLength: 2, reg: fp64_21gp, typ: "Bool", earlyOk: true}, // arg0 != arg1 + {name: "F64Lt", asm: "F64Lt", argLength: 2, reg: fp64_21gp, typ: "Bool", earlyOk: true}, // arg0 < arg1 + {name: "F64Gt", asm: "F64Gt", argLength: 2, reg: fp64_21gp, typ: "Bool", earlyOk: true}, // arg0 > arg1 + {name: "F64Le", asm: "F64Le", argLength: 2, reg: fp64_21gp, typ: "Bool", earlyOk: true}, // arg0 <= arg1 + {name: "F64Ge", asm: "F64Ge", argLength: 2, reg: fp64_21gp, typ: "Bool", earlyOk: true}, // arg0 >= arg1 + + {name: "I64Add", asm: "I64Add", argLength: 2, reg: gp21, typ: "Int64", earlyOk: true}, // arg0 + arg1 + {name: "I64AddConst", asm: "I64Add", argLength: 1, reg: gp11, aux: "Int64", typ: "Int64", earlyOk: true}, // arg0 + aux + {name: "I64Sub", asm: "I64Sub", argLength: 2, reg: gp21, typ: "Int64", earlyOk: true}, // arg0 - arg1 + {name: "I64Mul", asm: "I64Mul", argLength: 2, reg: gp21, typ: "Int64", earlyOk: true}, // arg0 * arg1 + {name: "I64DivS", asm: "I64DivS", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 / arg1 (signed) + {name: "I64DivU", asm: "I64DivU", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 / arg1 (unsigned) + {name: "I64RemS", asm: "I64RemS", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 % arg1 (signed) + {name: "I64RemU", asm: "I64RemU", argLength: 2, reg: gp21, typ: "Int64"}, // arg0 % arg1 (unsigned) + {name: "I64And", asm: "I64And", argLength: 2, reg: gp21, typ: "Int64", earlyOk: true}, // arg0 & arg1 + {name: "I64Or", asm: "I64Or", argLength: 2, reg: gp21, typ: "Int64", earlyOk: true}, // arg0 | arg1 + {name: "I64Xor", asm: "I64Xor", argLength: 2, reg: gp21, typ: "Int64", earlyOk: true}, // arg0 ^ arg1 + {name: "I64Shl", asm: "I64Shl", argLength: 2, reg: gp21, typ: "Int64", earlyOk: true}, // arg0 << (arg1 % 64) + {name: "I64ShrS", asm: "I64ShrS", argLength: 2, reg: gp21, typ: "Int64", earlyOk: true}, // arg0 >> (arg1 % 64) (signed) + {name: "I64ShrU", asm: "I64ShrU", argLength: 2, reg: gp21, typ: "Int64", earlyOk: true}, // arg0 >> (arg1 % 64) (unsigned) + + {name: "F32Neg", asm: "F32Neg", argLength: 1, reg: fp32_11, typ: "Float32", earlyOk: true}, // -arg0 + {name: "F32Add", asm: "F32Add", argLength: 2, reg: fp32_21, typ: "Float32", earlyOk: true}, // arg0 + arg1 + {name: "F32Sub", asm: "F32Sub", argLength: 2, reg: fp32_21, typ: "Float32", earlyOk: true}, // arg0 - arg1 + {name: "F32Mul", asm: "F32Mul", argLength: 2, reg: fp32_21, typ: "Float32", earlyOk: true}, // arg0 * arg1 + {name: "F32Div", asm: "F32Div", argLength: 2, reg: fp32_21, typ: "Float32", earlyOk: true}, // arg0 / arg1 + + {name: "F64Neg", asm: "F64Neg", argLength: 1, reg: fp64_11, typ: "Float64", earlyOk: true}, // -arg0 + {name: "F64Add", asm: "F64Add", argLength: 2, reg: fp64_21, typ: "Float64", earlyOk: true}, // arg0 + arg1 + {name: "F64Sub", asm: "F64Sub", argLength: 2, reg: fp64_21, typ: "Float64", earlyOk: true}, // arg0 - arg1 + {name: "F64Mul", asm: "F64Mul", argLength: 2, reg: fp64_21, typ: "Float64", earlyOk: true}, // arg0 * arg1 + {name: "F64Div", asm: "F64Div", argLength: 2, reg: fp64_21, typ: "Float64", earlyOk: true}, // arg0 / arg1 + + {name: "I64TruncSatF64S", asm: "I64TruncSatF64S", argLength: 1, reg: regInfo{inputs: []regMask{fp64}, outputs: []regMask{gp}}, typ: "Int64", earlyOk: true}, // truncates the float arg0 to a signed integer (saturating) + {name: "I64TruncSatF64U", asm: "I64TruncSatF64U", argLength: 1, reg: regInfo{inputs: []regMask{fp64}, outputs: []regMask{gp}}, typ: "Int64", earlyOk: true}, // truncates the float arg0 to an unsigned integer (saturating) + {name: "I64TruncSatF32S", asm: "I64TruncSatF32S", argLength: 1, reg: regInfo{inputs: []regMask{fp32}, outputs: []regMask{gp}}, typ: "Int64", earlyOk: true}, // truncates the float arg0 to a signed integer (saturating) + {name: "I64TruncSatF32U", asm: "I64TruncSatF32U", argLength: 1, reg: regInfo{inputs: []regMask{fp32}, outputs: []regMask{gp}}, typ: "Int64", earlyOk: true}, // truncates the float arg0 to an unsigned integer (saturating) + {name: "F32ConvertI64S", asm: "F32ConvertI64S", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{fp32}}, typ: "Float32", earlyOk: true}, // converts the signed integer arg0 to a float + {name: "F32ConvertI64U", asm: "F32ConvertI64U", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{fp32}}, typ: "Float32", earlyOk: true}, // converts the unsigned integer arg0 to a float + {name: "F64ConvertI64S", asm: "F64ConvertI64S", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{fp64}}, typ: "Float64", earlyOk: true}, // converts the signed integer arg0 to a float + {name: "F64ConvertI64U", asm: "F64ConvertI64U", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{fp64}}, typ: "Float64", earlyOk: true}, // converts the unsigned integer arg0 to a float + {name: "F32DemoteF64", asm: "F32DemoteF64", argLength: 1, reg: regInfo{inputs: []regMask{fp64}, outputs: []regMask{fp32}}, typ: "Float32", earlyOk: true}, + {name: "F64PromoteF32", asm: "F64PromoteF32", argLength: 1, reg: regInfo{inputs: []regMask{fp32}, outputs: []regMask{fp64}}, typ: "Float64", earlyOk: true}, + + {name: "I64Extend8S", asm: "I64Extend8S", argLength: 1, reg: gp11, typ: "Int64", earlyOk: true}, // sign-extend arg0 from 8 to 64 bit + {name: "I64Extend16S", asm: "I64Extend16S", argLength: 1, reg: gp11, typ: "Int64", earlyOk: true}, // sign-extend arg0 from 16 to 64 bit + {name: "I64Extend32S", asm: "I64Extend32S", argLength: 1, reg: gp11, typ: "Int64", earlyOk: true}, // sign-extend arg0 from 32 to 64 bit + + {name: "F32Sqrt", asm: "F32Sqrt", argLength: 1, reg: fp32_11, typ: "Float32", earlyOk: true}, // sqrt(arg0) + {name: "F32Trunc", asm: "F32Trunc", argLength: 1, reg: fp32_11, typ: "Float32", earlyOk: true}, // trunc(arg0) + {name: "F32Ceil", asm: "F32Ceil", argLength: 1, reg: fp32_11, typ: "Float32", earlyOk: true}, // ceil(arg0) + {name: "F32Floor", asm: "F32Floor", argLength: 1, reg: fp32_11, typ: "Float32", earlyOk: true}, // floor(arg0) + {name: "F32Nearest", asm: "F32Nearest", argLength: 1, reg: fp32_11, typ: "Float32", earlyOk: true}, // round(arg0) + {name: "F32Abs", asm: "F32Abs", argLength: 1, reg: fp32_11, typ: "Float32", earlyOk: true}, // abs(arg0) + {name: "F32Copysign", asm: "F32Copysign", argLength: 2, reg: fp32_21, typ: "Float32", earlyOk: true}, // copysign(arg0, arg1) + + {name: "F64Sqrt", asm: "F64Sqrt", argLength: 1, reg: fp64_11, typ: "Float64", earlyOk: true}, // sqrt(arg0) + {name: "F64Trunc", asm: "F64Trunc", argLength: 1, reg: fp64_11, typ: "Float64", earlyOk: true}, // trunc(arg0) + {name: "F64Ceil", asm: "F64Ceil", argLength: 1, reg: fp64_11, typ: "Float64", earlyOk: true}, // ceil(arg0) + {name: "F64Floor", asm: "F64Floor", argLength: 1, reg: fp64_11, typ: "Float64", earlyOk: true}, // floor(arg0) + {name: "F64Nearest", asm: "F64Nearest", argLength: 1, reg: fp64_11, typ: "Float64", earlyOk: true}, // round(arg0) + {name: "F64Abs", asm: "F64Abs", argLength: 1, reg: fp64_11, typ: "Float64", earlyOk: true}, // abs(arg0) + {name: "F64Copysign", asm: "F64Copysign", argLength: 2, reg: fp64_21, typ: "Float64", earlyOk: true}, // copysign(arg0, arg1) + + {name: "I64Ctz", asm: "I64Ctz", argLength: 1, reg: gp11, typ: "Int64", earlyOk: true}, // ctz(arg0) + {name: "I64Clz", asm: "I64Clz", argLength: 1, reg: gp11, typ: "Int64", earlyOk: true}, // clz(arg0) + {name: "I32Rotl", asm: "I32Rotl", argLength: 2, reg: gp21, typ: "Int32", earlyOk: true}, // rotl(arg0, arg1) + {name: "I64Rotl", asm: "I64Rotl", argLength: 2, reg: gp21, typ: "Int64", earlyOk: true}, // rotl(arg0, arg1) + {name: "I64Popcnt", asm: "I64Popcnt", argLength: 1, reg: gp11, typ: "Int64", earlyOk: true}, // popcnt(arg0) } + WasmOps = append(WasmOps, simdWasmOps(vload, vstore, v11, v21, v31, v11gp, v11fp32, v11fp64, v1gpv, v1fp32v, v1fp64v, gpv, fp32v, fp64v)...) + archs = append(archs, arch{ name: "Wasm", pkg: "cmd/internal/obj/wasm", genfile: "../../wasm/ssa.go", + genSIMDfile: "../../wasm/simdssa.go", ops: WasmOps, blocks: nil, regnames: regNamesWasm, gpregmask: gp, - fpregmask: fp32 | fp64, + fpregmask: fp32.union(fp64), + simdregmask: v128, fp32regmask: fp32, fp64regmask: fp64, framepointerreg: -1, // not used diff --git a/src/cmd/compile/internal/ssa/_gen/allocators.go b/src/cmd/compile/internal/ssa/_gen/allocators.go index 38acc5133abe86..7aaf5eaf82c77e 100644 --- a/src/cmd/compile/internal/ssa/_gen/allocators.go +++ b/src/cmd/compile/internal/ssa/_gen/allocators.go @@ -122,6 +122,16 @@ func genAllocators() { typ: "[]ID", base: "LimitSlice", }, + { + name: "UintSlice", + typ: "[]uint", + base: "LimitSlice", + }, + { + name: "KnownBitsEntriesSlice", + typ: "[]knownBitsEntry", + base: "LimitSlice", + }, } w := new(bytes.Buffer) diff --git a/src/cmd/compile/internal/ssa/_gen/dec.rules b/src/cmd/compile/internal/ssa/_gen/dec.rules index 5309a7f6b49f1e..97bc2a59788fad 100644 --- a/src/cmd/compile/internal/ssa/_gen/dec.rules +++ b/src/cmd/compile/internal/ssa/_gen/dec.rules @@ -4,7 +4,7 @@ // This file contains rules to decompose builtin compound types // (complex,string,slice,interface) into their constituent -// types. These rules work together with the decomposeBuiltIn +// types. These rules work together with the decomposeBuiltin // pass which handles phis of these types. (Store {t} _ _ mem) && t.Size() == 0 => mem @@ -80,7 +80,9 @@ // interface ops (ITab (IMake itab _)) => itab -(IData (IMake _ data)) => data +(IData (IMake _ data)) && data.Op != OpStructMake && data.Op != OpArrayMake1 => data +// Note: the conditional on data.Op ensures that StructMake/ArrayMake1 ops are +// unwrapped before the IMake is thrown away. See issue 77534. (Load ptr mem) && t.IsInterface() => (IMake @@ -97,8 +99,9 @@ // Helpers for expand calls // Some of these are copied from generic.rules -(IMake _typ (StructMake val)) => (IMake _typ val) -(StructSelect [0] (IData x)) => (IData x) +(IMake _typ (StructMake ___)) => imakeOfStructMake(v) +(StructSelect (IData x)) && v.Type.Size() > 0 => (IData x) +(StructSelect (IData x)) && v.Type.Size() == 0 => (Empty) (StructSelect [i] x:(StructMake ___)) => x.Args[i] @@ -109,7 +112,7 @@ // More annoying case: (ArraySelect[0] (StructSelect[0] isAPtr)) // There, result of the StructSelect is an Array (not a pointer) and // the pre-rewrite input to the ArraySelect is a struct, not a pointer. -(StructSelect [0] x) && x.Type.IsPtrShaped() => x +(StructSelect x) && x.Type.IsPtrShaped() => x (ArraySelect [0] x) && x.Type.IsPtrShaped() => x // These, too. Bits is bits. @@ -119,6 +122,7 @@ (Store _ (StructMake ___) _) => rewriteStructStore(v) +(IMake _typ (ArrayMake1 val)) => (IMake _typ val) (ArraySelect (ArrayMake1 x)) => x (ArraySelect [0] (IData x)) => (IData x) diff --git a/src/cmd/compile/internal/ssa/_gen/dec64.rules b/src/cmd/compile/internal/ssa/_gen/dec64.rules index ba776af1a705c6..483818906e6ff8 100644 --- a/src/cmd/compile/internal/ssa/_gen/dec64.rules +++ b/src/cmd/compile/internal/ssa/_gen/dec64.rules @@ -3,11 +3,15 @@ // license that can be found in the LICENSE file. // This file contains rules to decompose [u]int64 types on 32-bit -// architectures. These rules work together with the decomposeBuiltIn +// architectures. These rules work together with the decomposeBuiltin // pass which handles phis of these typ. +(Last ___) => v.Args[len(v.Args)-1] + (Int64Hi (Int64Make hi _)) => hi (Int64Lo (Int64Make _ lo)) => lo +(Select0 (MakeTuple x y)) => x +(Select1 (MakeTuple x y)) => y (Load ptr mem) && is64BitInt(t) && !config.BigEndian && t.IsSigned() => (Int64Make @@ -60,30 +64,85 @@ (Arg {n} [off]) (Arg {n} [off+4])) -(Add64 x y) => - (Int64Make - (Add32withcarry - (Int64Hi x) - (Int64Hi y) - (Select1 (Add32carry (Int64Lo x) (Int64Lo y)))) - (Select0 (Add32carry (Int64Lo x) (Int64Lo y)))) - -(Sub64 x y) => - (Int64Make - (Sub32withcarry - (Int64Hi x) - (Int64Hi y) - (Select1 (Sub32carry (Int64Lo x) (Int64Lo y)))) - (Select0 (Sub32carry (Int64Lo x) (Int64Lo y)))) +(Add64 x y) => + (Last + x0: (Int64Lo x) + x1: (Int64Hi x) + y0: (Int64Lo y) + y1: (Int64Hi y) + add: (Add32carry x0 y0) + (Int64Make + (Add32withcarry x1 y1 (Select1 add)) + (Select0 add))) + +(Sub64 x y) => + (Last + x0: (Int64Lo x) + x1: (Int64Hi x) + y0: (Int64Lo y) + y1: (Int64Hi y) + sub: (Sub32carry x0 y0) + (Int64Make + (Sub32withcarry x1 y1 (Select1 sub)) + (Select0 sub))) + +(Mul64 x y) => + (Last + x0: (Int64Lo x) + x1: (Int64Hi x) + y0: (Int64Lo y) + y1: (Int64Hi y) + x0y0: (Mul32uhilo x0 y0) + x0y0Hi: (Select0 x0y0) + x0y0Lo: (Select1 x0y0) + (Int64Make + (Add32 x0y0Hi + (Add32 + (Mul32 x0 y1) + (Mul32 x1 y0))) + x0y0Lo)) + +(Mul64uhilo x y) => + (Last + x0: (Int64Lo x) + x1: (Int64Hi x) + y0: (Int64Lo y) + y1: (Int64Hi y) + x0y0: (Mul32uhilo x0 y0) + x0y1: (Mul32uhilo x0 y1) + x1y0: (Mul32uhilo x1 y0) + x1y1: (Mul32uhilo x1 y1) + x0y0Hi: (Select0 x0y0) + x0y0Lo: (Select1 x0y0) + x0y1Hi: (Select0 x0y1) + x0y1Lo: (Select1 x0y1) + x1y0Hi: (Select0 x1y0) + x1y0Lo: (Select1 x1y0) + x1y1Hi: (Select0 x1y1) + x1y1Lo: (Select1 x1y1) + w1a: (Add32carry x0y0Hi x0y1Lo) + w2a: (Add32carrywithcarry x0y1Hi x1y0Hi (Select1 w1a)) + w3a: (Add32withcarry x1y1Hi (Const32 [0]) (Select1 w2a)) + w1b: (Add32carry x1y0Lo (Select0 w1a)) + w2b: (Add32carrywithcarry x1y1Lo (Select0 w2a) (Select1 w1b)) + w3b: (Add32withcarry w3a (Const32 [0]) (Select1 w2b)) + (MakeTuple + (Int64Make w3b (Select0 w2b)) + (Int64Make (Select0 w1b) x0y0Lo))) + +(Hmul64u x y) => (Select0 (Mul64uhilo x y)) + +// Hacker's Delight p. 175: signed hmul = unsigned hmul - (x<0)&y - (y<0)&x. +(Hmul64 x y) => + (Last + p: (Hmul64u x y) + xSign: (Int64Make xs:(Rsh32x32 (Int64Hi x) (Const32 [31])) xs) + ySign: (Int64Make ys:(Rsh32x32 (Int64Hi y) (Const32 [31])) ys) + (Sub64 (Sub64 p (And64 xSign y)) (And64 ySign x))) + +// (x+y)/2 => (x-y)/2 + y +(Avg64u x y) => (Add64 (Rsh64Ux32 (Sub64 x y) (Const32 [1])) y) -(Mul64 x y) => - (Int64Make - (Add32 - (Mul32 (Int64Lo x) (Int64Hi y)) - (Add32 - (Mul32 (Int64Hi x) (Int64Lo y)) - (Select0 (Mul32uhilo (Int64Lo x) (Int64Lo y))))) - (Select1 (Mul32uhilo (Int64Lo x) (Int64Lo y)))) (And64 x y) => (Int64Make @@ -217,11 +276,32 @@ (Rsh8x64 x y) => (Rsh8x32 x (Or32 (Zeromask (Int64Hi y)) (Int64Lo y))) (Rsh8Ux64 x y) => (Rsh8Ux32 x (Or32 (Zeromask (Int64Hi y)) (Int64Lo y))) + (RotateLeft64 x (Int64Make hi lo)) => (RotateLeft64 x lo) (RotateLeft32 x (Int64Make hi lo)) => (RotateLeft32 x lo) (RotateLeft16 x (Int64Make hi lo)) => (RotateLeft16 x lo) (RotateLeft8 x (Int64Make hi lo)) => (RotateLeft8 x lo) +// RotateLeft64 by constant, for use in divmod. +(RotateLeft64 x (Const(64|32|16|8) [c])) && c&63 == 0 => x +(RotateLeft64 x (Const(64|32|16|8) [c])) && c&63 == 32 => (Int64Make (Int64Lo x) (Int64Hi x)) +(RotateLeft64 x (Const(64|32|16|8) [c])) && 0 < c&63 && c&63 < 32 => + (Int64Make + (Or32 + (Lsh32x32 (Int64Hi x) (Const32 [int32(c&31)])) + (Rsh32Ux32 (Int64Lo x) (Const32 [int32(32-c&31)]))) + (Or32 + (Lsh32x32 (Int64Lo x) (Const32 [int32(c&31)])) + (Rsh32Ux32 (Int64Hi x) (Const32 [int32(32-c&31)])))) +(RotateLeft64 x (Const(64|32|16|8) [c])) && 32 < c&63 && c&63 < 64 => + (Int64Make + (Or32 + (Lsh32x32 (Int64Lo x) (Const32 [int32(c&31)])) + (Rsh32Ux32 (Int64Hi x) (Const32 [int32(32-c&31)]))) + (Or32 + (Lsh32x32 (Int64Hi x) (Const32 [int32(c&31)])) + (Rsh32Ux32 (Int64Lo x) (Const32 [int32(32-c&31)])))) + // Clean up constants a little (Or32 (Zeromask (Const32 [c])) y) && c == 0 => y (Or32 (Zeromask (Const32 [c])) y) && c != 0 => (Const32 [-1]) diff --git a/src/cmd/compile/internal/ssa/_gen/divisible.rules b/src/cmd/compile/internal/ssa/_gen/divisible.rules new file mode 100644 index 00000000000000..8c198838267226 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/divisible.rules @@ -0,0 +1,167 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Divisibility checks (x%c == 0 or x%c != 0) convert to multiply, rotate, compare. +// The opt pass rewrote x%c to x-(x/c)*c +// and then also rewrote x-(x/c)*c == 0 to x == (x/c)*c. +// If x/c is being used for a division already (div.Uses != 1) +// then we leave the expression alone. +// +// See ../magic.go for a detailed description of these algorithms. +// See test/codegen/divmod.go for tests. +// See divmod.rules for other division rules that run after these. + +// Divisiblity by unsigned or signed power of two. +(Eq(8|16|32|64) x (Mul(8|16|32|64) (Div(8|16|32|64)u x (Const(8|16|32|64) [c])) (Const(8|16|32|64) [c]))) + && x.Op != OpConst64 && isPowerOfTwo(c) => + (Eq(8|16|32|64) (And(8|16|32|64) x (Const(8|16|32|64) [c-1])) (Const(8|16|32|64) [0])) +(Eq(8|16|32|64) x (Mul(8|16|32|64) (Div(8|16|32|64) x (Const(8|16|32|64) [c])) (Const(8|16|32|64) [c]))) + && x.Op != OpConst64 && isPowerOfTwo(c) => + (Eq(8|16|32|64) (And(8|16|32|64) x (Const(8|16|32|64) [c-1])) (Const(8|16|32|64) [0])) +(Neq(8|16|32|64) x (Mul(8|16|32|64) (Div(8|16|32|64)u x (Const(8|16|32|64) [c])) (Const(8|16|32|64) [c]))) + && x.Op != OpConst64 && isPowerOfTwo(c) => + (Neq(8|16|32|64) (And(8|16|32|64) x (Const(8|16|32|64) [c-1])) (Const(8|16|32|64) [0])) +(Neq(8|16|32|64) x (Mul(8|16|32|64) (Div(8|16|32|64) x (Const(8|16|32|64) [c])) (Const(8|16|32|64) [c]))) + && x.Op != OpConst64 && isPowerOfTwo(c) => + (Neq(8|16|32|64) (And(8|16|32|64) x (Const(8|16|32|64) [c-1])) (Const(8|16|32|64) [0])) + +// Divisiblity by unsigned. +(Eq8 x (Mul8 div:(Div8u x (Const8 [c])) (Const8 [c]))) + && div.Uses == 1 + && x.Op != OpConst8 && udivisibleOK8(c) => + (Leq8U + (RotateLeft8 + (Mul8 x (Const8 [int8(udivisible8(c).m)])) + (Const8 [int8(8 - udivisible8(c).k)])) + (Const8 [int8(udivisible8(c).max)])) +(Neq8 x (Mul8 div:(Div8u x (Const8 [c])) (Const8 [c]))) + && div.Uses == 1 + && x.Op != OpConst8 && udivisibleOK8(c) => + (Less8U + (Const8 [int8(udivisible8(c).max)]) + (RotateLeft8 + (Mul8 x (Const8 [int8(udivisible8(c).m)])) + (Const8 [int8(8 - udivisible8(c).k)]))) +(Eq16 x (Mul16 div:(Div16u x (Const16 [c])) (Const16 [c]))) + && div.Uses == 1 + && x.Op != OpConst16 && udivisibleOK16(c) => + (Leq16U + (RotateLeft16 + (Mul16 x (Const16 [int16(udivisible16(c).m)])) + (Const16 [int16(16 - udivisible16(c).k)])) + (Const16 [int16(udivisible16(c).max)])) +(Neq16 x (Mul16 div:(Div16u x (Const16 [c])) (Const16 [c]))) + && div.Uses == 1 + && x.Op != OpConst16 && udivisibleOK16(c) => + (Less16U + (Const16 [int16(udivisible16(c).max)]) + (RotateLeft16 + (Mul16 x (Const16 [int16(udivisible16(c).m)])) + (Const16 [int16(16 - udivisible16(c).k)]))) +(Eq32 x (Mul32 div:(Div32u x (Const32 [c])) (Const32 [c]))) + && div.Uses == 1 + && x.Op != OpConst32 && udivisibleOK32(c) => + (Leq32U + (RotateLeft32 + (Mul32 x (Const32 [int32(udivisible32(c).m)])) + (Const32 [int32(32 - udivisible32(c).k)])) + (Const32 [int32(udivisible32(c).max)])) +(Neq32 x (Mul32 div:(Div32u x (Const32 [c])) (Const32 [c]))) + && div.Uses == 1 + && x.Op != OpConst32 && udivisibleOK32(c) => + (Less32U + (Const32 [int32(udivisible32(c).max)]) + (RotateLeft32 + (Mul32 x (Const32 [int32(udivisible32(c).m)])) + (Const32 [int32(32 - udivisible32(c).k)]))) +(Eq64 x (Mul64 div:(Div64u x (Const64 [c])) (Const64 [c]))) + && div.Uses == 1 + && x.Op != OpConst64 && udivisibleOK64(c) => + (Leq64U + (RotateLeft64 + (Mul64 x (Const64 [int64(udivisible64(c).m)])) + (Const64 [int64(64 - udivisible64(c).k)])) + (Const64 [int64(udivisible64(c).max)])) +(Neq64 x (Mul64 div:(Div64u x (Const64 [c])) (Const64 [c]))) + && div.Uses == 1 + && x.Op != OpConst64 && udivisibleOK64(c) => + (Less64U + (Const64 [int64(udivisible64(c).max)]) + (RotateLeft64 + (Mul64 x (Const64 [int64(udivisible64(c).m)])) + (Const64 [int64(64 - udivisible64(c).k)]))) + +// Divisiblity by signed. +(Eq8 x (Mul8 div:(Div8 x (Const8 [c])) (Const8 [c]))) + && div.Uses == 1 + && x.Op != OpConst8 && sdivisibleOK8(c) => + (Leq8U + (RotateLeft8 + (Add8 (Mul8 x (Const8 [int8(sdivisible8(c).m)])) + (Const8 [int8(sdivisible8(c).a)])) + (Const8 [int8(8 - sdivisible8(c).k)])) + (Const8 [int8(sdivisible8(c).max)])) +(Neq8 x (Mul8 div:(Div8 x (Const8 [c])) (Const8 [c]))) + && div.Uses == 1 + && x.Op != OpConst8 && sdivisibleOK8(c) => + (Less8U + (Const8 [int8(sdivisible8(c).max)]) + (RotateLeft8 + (Add8 (Mul8 x (Const8 [int8(sdivisible8(c).m)])) + (Const8 [int8(sdivisible8(c).a)])) + (Const8 [int8(8 - sdivisible8(c).k)]))) +(Eq16 x (Mul16 div:(Div16 x (Const16 [c])) (Const16 [c]))) + && div.Uses == 1 + && x.Op != OpConst16 && sdivisibleOK16(c) => + (Leq16U + (RotateLeft16 + (Add16 (Mul16 x (Const16 [int16(sdivisible16(c).m)])) + (Const16 [int16(sdivisible16(c).a)])) + (Const16 [int16(16 - sdivisible16(c).k)])) + (Const16 [int16(sdivisible16(c).max)])) +(Neq16 x (Mul16 div:(Div16 x (Const16 [c])) (Const16 [c]))) + && div.Uses == 1 + && x.Op != OpConst16 && sdivisibleOK16(c) => + (Less16U + (Const16 [int16(sdivisible16(c).max)]) + (RotateLeft16 + (Add16 (Mul16 x (Const16 [int16(sdivisible16(c).m)])) + (Const16 [int16(sdivisible16(c).a)])) + (Const16 [int16(16 - sdivisible16(c).k)]))) +(Eq32 x (Mul32 div:(Div32 x (Const32 [c])) (Const32 [c]))) + && div.Uses == 1 + && x.Op != OpConst32 && sdivisibleOK32(c) => + (Leq32U + (RotateLeft32 + (Add32 (Mul32 x (Const32 [int32(sdivisible32(c).m)])) + (Const32 [int32(sdivisible32(c).a)])) + (Const32 [int32(32 - sdivisible32(c).k)])) + (Const32 [int32(sdivisible32(c).max)])) +(Neq32 x (Mul32 div:(Div32 x (Const32 [c])) (Const32 [c]))) + && div.Uses == 1 + && x.Op != OpConst32 && sdivisibleOK32(c) => + (Less32U + (Const32 [int32(sdivisible32(c).max)]) + (RotateLeft32 + (Add32 (Mul32 x (Const32 [int32(sdivisible32(c).m)])) + (Const32 [int32(sdivisible32(c).a)])) + (Const32 [int32(32 - sdivisible32(c).k)]))) +(Eq64 x (Mul64 div:(Div64 x (Const64 [c])) (Const64 [c]))) + && div.Uses == 1 + && x.Op != OpConst64 && sdivisibleOK64(c) => + (Leq64U + (RotateLeft64 + (Add64 (Mul64 x (Const64 [int64(sdivisible64(c).m)])) + (Const64 [int64(sdivisible64(c).a)])) + (Const64 [int64(64 - sdivisible64(c).k)])) + (Const64 [int64(sdivisible64(c).max)])) +(Neq64 x (Mul64 div:(Div64 x (Const64 [c])) (Const64 [c]))) + && div.Uses == 1 + && x.Op != OpConst64 && sdivisibleOK64(c) => + (Less64U + (Const64 [int64(sdivisible64(c).max)]) + (RotateLeft64 + (Add64 (Mul64 x (Const64 [int64(sdivisible64(c).m)])) + (Const64 [int64(sdivisible64(c).a)])) + (Const64 [int64(64 - sdivisible64(c).k)]))) diff --git a/src/cmd/compile/internal/ssa/_gen/divisibleOps.go b/src/cmd/compile/internal/ssa/_gen/divisibleOps.go new file mode 100644 index 00000000000000..9fcd03aadb8f1b --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/divisibleOps.go @@ -0,0 +1,18 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +var divisibleOps = []opData{} + +var divisibleBlocks = []blockData{} + +func init() { + archs = append(archs, arch{ + name: "divisible", + ops: divisibleOps, + blocks: divisibleBlocks, + generic: true, + }) +} diff --git a/src/cmd/compile/internal/ssa/_gen/divmod.rules b/src/cmd/compile/internal/ssa/_gen/divmod.rules new file mode 100644 index 00000000000000..f06a43564654ee --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/divmod.rules @@ -0,0 +1,235 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Lowering of mul, div, and mod operations. +// Runs after prove, so that prove can analyze div and mod ops +// directly instead of these obscured expansions, +// but before decompose builtin, so that 32-bit systems +// can still lower 64-bit ops to 32-bit ones. +// +// See ../magic.go for a detailed description of these algorithms. +// See test/codegen/divmod.go for tests. + +// Unsigned div and mod by power of 2 handled in generic.rules. +// (The equivalent unsigned right shift and mask are simple enough for prove to analyze.) + +// Signed divide by power of 2. +// n / c = n >> log(c) if n >= 0 +// = (n+c-1) >> log(c) if n < 0 +// We conditionally add c-1 by adding n>>63>>(64-log(c)) (first shift signed, second shift unsigned). +(Div8 n (Const8 [c])) && isPowerOfTwo(c) => + (Rsh8x64 + (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [int64( 8-log8(c))]))) + (Const64 [int64(log8(c))])) +(Div16 n (Const16 [c])) && isPowerOfTwo(c) => + (Rsh16x64 + (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [int64(16-log16(c))]))) + (Const64 [int64(log16(c))])) +(Div32 n (Const32 [c])) && isPowerOfTwo(c) => + (Rsh32x64 + (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [int64(32-log32(c))]))) + (Const64 [int64(log32(c))])) +(Div64 n (Const64 [c])) && isPowerOfTwo(c) => + (Rsh64x64 + (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [int64(64-log64(c))]))) + (Const64 [int64(log64(c))])) + +// Divide, not a power of 2, by strength reduction to double-width multiply and shift. +// +// umagicN(c) computes m, s such that N-bit unsigned divide +// x/c = (x*((1<>N>>s = ((x*m)>>N+x)>>s +// where the multiplies are unsigned. +// Note that the returned m is always N+1 bits; umagicN omits the high 1<>N>>s - bool2int(x < 0). +// Here m is an unsigned N-bit number but x is signed. +// +// In general the division cases are: +// +// 1. A signed divide where 2N ≤ the register size. +// This form can use the signed algorithm directly. +// +// 2. A signed divide where m is even. +// This form can use a signed double-width multiply with m/2, +// shifting by s-1. +// +// 3. A signed divide where m is odd. +// This form can use x*m = ((x*(m-2^N))>>N+x) with a signed multiply. +// Since intN(m) is m-2^N < 0, the product and x have different signs, +// so there can be no overflow on the addition. +// +// 4. An unsigned divide where we know x < 1<<(N-1). +// This form can use the signed algorithm without the bool2int fixup, +// and since we know the product is only 2N-1 bits, we can use an +// unsigned multiply to obtain the high N bits directly, regardless +// of whether m is odd or even. +// +// 5. An unsigned divide where 2N+1 ≤ the register size. +// This form uses the unsigned algorithm with an explicit (1<>N>>s = ((x*m)>>N+x)>>s. +// Let hi = (x*m)>>N, so we want (hi+x) >> s = avg(hi, x) >> (s-1). + +// Case 1. Signed divides where 2N ≤ register size. +(Div8 x (Const8 [c])) && smagicOK8(c) => + (Sub8 + (Rsh32x64 + (Mul32 (SignExt8to32 x) (Const32 [int32(smagic8(c).m)])) + (Const64 [8 + smagic8(c).s])) + (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) +(Div16 x (Const16 [c])) && smagicOK16(c) => + (Sub16 + (Rsh32x64 + (Mul32 (SignExt16to32 x) (Const32 [int32(smagic16(c).m)])) + (Const64 [16 + smagic16(c).s])) + (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) +(Div32 x (Const32 [c])) && smagicOK32(c) && config.RegSize == 8 => + (Sub32 + (Rsh64x64 + (Mul64 (SignExt32to64 x) (Const64 [int64(smagic32(c).m)])) + (Const64 [32 + smagic32(c).s])) + (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) + +// Case 2. Signed divides where m is even. +(Div32 x (Const32 [c])) && smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 => + (Sub32 + (Rsh32x64 + (Hmul32 x (Const32 [int32(smagic32(c).m/2)])) + (Const64 [smagic32(c).s - 1])) + (Rsh32x64 x (Const64 [31]))) +(Div64 x (Const64 [c])) && smagicOK64(c) && smagic64(c).m&1 == 0 => + (Sub64 + (Rsh64x64 + (Hmul64 x (Const64 [int64(smagic64(c).m/2)])) + (Const64 [smagic64(c).s - 1])) + (Rsh64x64 x (Const64 [63]))) + +// Case 3. Signed divides where m is odd. +(Div32 x (Const32 [c])) && smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 => + (Sub32 + (Rsh32x64 + (Add32 x (Hmul32 x (Const32 [int32(smagic32(c).m)]))) + (Const64 [smagic32(c).s])) + (Rsh32x64 x (Const64 [31]))) +(Div64 x (Const64 [c])) && smagicOK64(c) && smagic64(c).m&1 != 0 => + (Sub64 + (Rsh64x64 + (Add64 x (Hmul64 x (Const64 [int64(smagic64(c).m)]))) + (Const64 [smagic64(c).s])) + (Rsh64x64 x (Const64 [63]))) + +// Case 4. Unsigned divide where x < 1<<(N-1). +// Skip Div8u since case 5's handling is just as good. +(Div16u x (Const16 [c])) && t.IsSigned() && smagicOK16(c) => + (Rsh32Ux64 + (Mul32 (SignExt16to32 x) (Const32 [int32(smagic16(c).m)])) + (Const64 [16 + smagic16(c).s])) +(Div32u x (Const32 [c])) && t.IsSigned() && smagicOK32(c) && config.RegSize == 8 => + (Rsh64Ux64 + (Mul64 (SignExt32to64 x) (Const64 [int64(smagic32(c).m)])) + (Const64 [32 + smagic32(c).s])) +(Div32u x (Const32 [c])) && t.IsSigned() && smagicOK32(c) && config.RegSize == 4 => + (Rsh32Ux64 + (Hmul32u x (Const32 [int32(smagic32(c).m)])) + (Const64 [smagic32(c).s])) +(Div64u x (Const64 [c])) && t.IsSigned() && smagicOK64(c) => + (Rsh64Ux64 + (Hmul64u x (Const64 [int64(smagic64(c).m)])) + (Const64 [smagic64(c).s])) + +// Case 5. Unsigned divide where 2N+1 ≤ register size. +(Div8u x (Const8 [c])) && umagicOK8(c) => + (Trunc32to8 + (Rsh32Ux64 + (Mul32 (ZeroExt8to32 x) (Const32 [int32(1<<8 + umagic8(c).m)])) + (Const64 [8 + umagic8(c).s]))) +(Div16u x (Const16 [c])) && umagicOK16(c) && config.RegSize == 8 => + (Trunc64to16 + (Rsh64Ux64 + (Mul64 (ZeroExt16to64 x) (Const64 [int64(1<<16 + umagic16(c).m)])) + (Const64 [16 + umagic16(c).s]))) + +// Case 6. Unsigned divide where m is even. +(Div16u x (Const16 [c])) && umagicOK16(c) && umagic16(c).m&1 == 0 => + (Trunc32to16 + (Rsh32Ux64 + (Mul32 (ZeroExt16to32 x) (Const32 [int32(1<<15 + umagic16(c).m/2)])) + (Const64 [16 + umagic16(c).s - 1]))) +(Div32u x (Const32 [c])) && umagicOK32(c) && umagic32(c).m&1 == 0 && config.RegSize == 8 => + (Trunc64to32 + (Rsh64Ux64 + (Mul64 (ZeroExt32to64 x) (Const64 [int64(1<<31 + umagic32(c).m/2)])) + (Const64 [32 + umagic32(c).s - 1]))) +(Div32u x (Const32 [c])) && umagicOK32(c) && umagic32(c).m&1 == 0 && config.RegSize == 4 => + (Rsh32Ux64 + (Hmul32u x (Const32 [int32(1<<31 + umagic32(c).m/2)])) + (Const64 [umagic32(c).s - 1])) +(Div64u x (Const64 [c])) && umagicOK64(c) && umagic64(c).m&1 == 0 => + (Rsh64Ux64 + (Hmul64u x (Const64 [int64(1<<63 + umagic64(c).m/2)])) + (Const64 [umagic64(c).s - 1])) + +// Case 7. Unsigned divide where c is even. +(Div16u x (Const16 [c])) && umagicOK16(c) && config.RegSize == 4 && c&1 == 0 => + (Trunc32to16 + (Rsh32Ux64 + (Mul32 + (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) + (Const32 [int32(1<<15 + (umagic16(c).m+1)/2)])) + (Const64 [16 + umagic16(c).s - 2]))) +(Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 8 && c&1 == 0 => + (Trunc64to32 + (Rsh64Ux64 + (Mul64 + (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1])) + (Const64 [int64(1<<31 + (umagic32(c).m+1)/2)])) + (Const64 [32 + umagic32(c).s - 2]))) +(Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 4 && c&1 == 0 => + (Rsh32Ux64 + (Hmul32u + (Rsh32Ux64 x (Const64 [1])) + (Const32 [int32(1<<31 + (umagic32(c).m+1)/2)])) + (Const64 [umagic32(c).s - 2])) +(Div64u x (Const64 [c])) && umagicOK64(c) && c&1 == 0 => + (Rsh64Ux64 + (Hmul64u + (Rsh64Ux64 x (Const64 [1])) + (Const64 [int64(1<<63 + (umagic64(c).m+1)/2)])) + (Const64 [umagic64(c).s - 2])) + +// Case 8. Unsigned divide using avg. +(Div16u x (Const16 [c])) && umagicOK16(c) && config.RegSize == 4 => + (Trunc32to16 + (Rsh32Ux64 + (Avg32u + (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) + (Mul32 (ZeroExt16to32 x) (Const32 [int32(umagic16(c).m)]))) + (Const64 [16 + umagic16(c).s - 1]))) +(Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 8 => + (Trunc64to32 + (Rsh64Ux64 + (Avg64u + (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) + (Mul64 (ZeroExt32to64 x) (Const64 [int64(umagic32(c).m)]))) + (Const64 [32 + umagic32(c).s - 1]))) +(Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 4 => + (Rsh32Ux64 + (Avg32u x (Hmul32u x (Const32 [int32(umagic32(c).m)]))) + (Const64 [umagic32(c).s - 1])) +(Div64u x (Const64 [c])) && umagicOK64(c) => + (Rsh64Ux64 + (Avg64u x (Hmul64u x (Const64 [int64(umagic64(c).m)]))) + (Const64 [umagic64(c).s - 1])) diff --git a/src/cmd/compile/internal/ssa/_gen/divmodOps.go b/src/cmd/compile/internal/ssa/_gen/divmodOps.go new file mode 100644 index 00000000000000..5e85386f78e427 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/divmodOps.go @@ -0,0 +1,18 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +var divmodOps = []opData{} + +var divmodBlocks = []blockData{} + +func init() { + archs = append(archs, arch{ + name: "divmod", + ops: divmodOps, + blocks: divmodBlocks, + generic: true, + }) +} diff --git a/src/cmd/compile/internal/ssa/_gen/generic.rules b/src/cmd/compile/internal/ssa/_gen/generic.rules index af9c24f53fd245..6c7f1767448e9e 100644 --- a/src/cmd/compile/internal/ssa/_gen/generic.rules +++ b/src/cmd/compile/internal/ssa/_gen/generic.rules @@ -195,19 +195,22 @@ // Convert x * -1 to -x. (Mul(8|16|32|64) (Const(8|16|32|64) [-1]) x) => (Neg(8|16|32|64) x) +// Convert -x * c to x * -c +(Mul(8|16|32|64) (Const(8|16|32|64) [c]) (Neg(8|16|32|64) x)) => (Mul(8|16|32|64) x (Const(8|16|32|64) [-c])) + +(Mul(8|16|32|64) (Neg(8|16|32|64) x) (Neg(8|16|32|64) y)) => (Mul(8|16|32|64) x y) + +// simplify negative on mul if possible +(Neg(8|16|32|64) (Mul(8|16|32|64) x (Const(8|16|32|64) [c]))) => (Mul(8|16|32|64) x (Const(8|16|32|64) [-c])) +(Neg(8|16|32|64) (Mul(8|16|32|64) x (Neg(8|16|32|64) y))) => (Mul(8|16|32|64) x y) + // DeMorgan's Laws (And(8|16|32|64) (Com(8|16|32|64) x) (Com(8|16|32|64) y)) => (Com(8|16|32|64) (Or(8|16|32|64) x y)) (Or(8|16|32|64) (Com(8|16|32|64) x) (Com(8|16|32|64) y)) => (Com(8|16|32|64) (And(8|16|32|64) x y)) -// Convert multiplication by a power of two to a shift. -(Mul8 n (Const8 [c])) && isPowerOfTwo(c) => (Lsh8x64 n (Const64 [log8(c)])) -(Mul16 n (Const16 [c])) && isPowerOfTwo(c) => (Lsh16x64 n (Const64 [log16(c)])) -(Mul32 n (Const32 [c])) && isPowerOfTwo(c) => (Lsh32x64 n (Const64 [log32(c)])) -(Mul64 n (Const64 [c])) && isPowerOfTwo(c) => (Lsh64x64 n (Const64 [log64(c)])) -(Mul8 n (Const8 [c])) && t.IsSigned() && isPowerOfTwo(-c) => (Neg8 (Lsh8x64 n (Const64 [log8(-c)]))) -(Mul16 n (Const16 [c])) && t.IsSigned() && isPowerOfTwo(-c) => (Neg16 (Lsh16x64 n (Const64 [log16(-c)]))) -(Mul32 n (Const32 [c])) && t.IsSigned() && isPowerOfTwo(-c) => (Neg32 (Lsh32x64 n (Const64 [log32(-c)]))) -(Mul64 n (Const64 [c])) && t.IsSigned() && isPowerOfTwo(-c) => (Neg64 (Lsh64x64 n (Const64 [log64(-c)]))) +// Absorption laws +(And(8|16|32|64) x (Or(8|16|32|64) x y)) => x +(Or(8|16|32|64) x (And(8|16|32|64) x y)) => x (Mod8 (Const8 [c]) (Const8 [d])) && d != 0 => (Const8 [c % d]) (Mod16 (Const16 [c]) (Const16 [d])) && d != 0 => (Const16 [c % d]) @@ -274,31 +277,46 @@ (IsSliceInBounds (Const64 [c]) (Const64 [d])) => (ConstBool [0 <= c && c <= d]) (IsSliceInBounds (SliceLen x) (SliceCap x)) => (ConstBool [true]) -(Eq(64|32|16|8) x x) => (ConstBool [true]) +(Eq(64|32|16|8|B) x x) => (ConstBool [true]) (EqB (ConstBool [c]) (ConstBool [d])) => (ConstBool [c == d]) (EqB (ConstBool [false]) x) => (Not x) (EqB (ConstBool [true]) x) => x +(EqB (Not x) y) => (NeqB x y) -(Neq(64|32|16|8) x x) => (ConstBool [false]) +(Neq(64|32|16|8|B) x x) => (ConstBool [false]) (NeqB (ConstBool [c]) (ConstBool [d])) => (ConstBool [c != d]) (NeqB (ConstBool [false]) x) => x (NeqB (ConstBool [true]) x) => (Not x) -(NeqB (Not x) (Not y)) => (NeqB x y) - -(Eq64 (Const64 [c]) (Add64 (Const64 [d]) x)) => (Eq64 (Const64 [c-d]) x) -(Eq32 (Const32 [c]) (Add32 (Const32 [d]) x)) => (Eq32 (Const32 [c-d]) x) -(Eq16 (Const16 [c]) (Add16 (Const16 [d]) x)) => (Eq16 (Const16 [c-d]) x) -(Eq8 (Const8 [c]) (Add8 (Const8 [d]) x)) => (Eq8 (Const8 [c-d]) x) - -(Neq64 (Const64 [c]) (Add64 (Const64 [d]) x)) => (Neq64 (Const64 [c-d]) x) -(Neq32 (Const32 [c]) (Add32 (Const32 [d]) x)) => (Neq32 (Const32 [c-d]) x) -(Neq16 (Const16 [c]) (Add16 (Const16 [d]) x)) => (Neq16 (Const16 [c-d]) x) -(Neq8 (Const8 [c]) (Add8 (Const8 [d]) x)) => (Neq8 (Const8 [c-d]) x) +(NeqB (Not x) y) => (EqB x y) (CondSelect x _ (ConstBool [true ])) => x (CondSelect _ y (ConstBool [false])) => y (CondSelect x x _) => x +// fold eq / neq between a constant and a compile time bijective operation into the constant. +(Eq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Add(64|32|16|8) (Const(64|32|16|8) [d]) x)) && o.Uses == 1 => (Eq(64|32|16|8) (Const(64|32|16|8) [c-d]) x) +(Neq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Add(64|32|16|8) (Const(64|32|16|8) [d]) x)) && o.Uses == 1 => (Neq(64|32|16|8) (Const(64|32|16|8) [c-d]) x) + +(Eq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Sub(64|32|16|8) x (Const(64|32|16|8) [d]))) && o.Uses == 1 => (Eq(64|32|16|8) (Const(64|32|16|8) [c+d]) x) +(Neq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Sub(64|32|16|8) x (Const(64|32|16|8) [d]))) && o.Uses == 1 => (Neq(64|32|16|8) (Const(64|32|16|8) [c+d]) x) + +(Eq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Sub(64|32|16|8) (Const(64|32|16|8) [d]) x)) && o.Uses == 1 => (Eq(64|32|16|8) (Const(64|32|16|8) [d-c]) x) +(Neq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Sub(64|32|16|8) (Const(64|32|16|8) [d]) x)) && o.Uses == 1 => (Neq(64|32|16|8) (Const(64|32|16|8) [d-c]) x) + +(Eq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Xor(64|32|16|8) (Const(64|32|16|8) [d]) x)) && o.Uses == 1 => (Eq(64|32|16|8) (Const(64|32|16|8) [d^c]) x) +(Neq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Xor(64|32|16|8) (Const(64|32|16|8) [d]) x)) && o.Uses == 1 => (Neq(64|32|16|8) (Const(64|32|16|8) [d^c]) x) + +(Eq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Com(64|32|16|8) x)) && o.Uses == 1 => (Eq(64|32|16|8) (Const(64|32|16|8) [^c]) x) +(Neq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Com(64|32|16|8) x)) && o.Uses == 1 => (Neq(64|32|16|8) (Const(64|32|16|8) [^c]) x) + +(Eq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Neg(64|32|16|8) x)) && o.Uses == 1 => (Eq(64|32|16|8) (Const(64|32|16|8) [-c]) x) +(Neq(64|32|16|8) (Const(64|32|16|8) [c]) o:(Neg(64|32|16|8) x)) && o.Uses == 1 => (Neq(64|32|16|8) (Const(64|32|16|8) [-c]) x) + +((Eq|Neq)64 (Const64 [c]) o:(Mul64 (Const64 [d]) x)) && uint64(d)%2 == 1 && o.Uses == 1 => ((Eq|Neq)64 (Const64 [int64(uint64(c) * modularMultiplicativeInverse(uint64(d))) ]) x) +((Eq|Neq)32 (Const32 [c]) o:(Mul32 (Const32 [d]) x)) && uint32(d)%2 == 1 && o.Uses == 1 => ((Eq|Neq)32 (Const32 [int32(uint32(c) * uint32(modularMultiplicativeInverse(uint64(d))))]) x) +((Eq|Neq)16 (Const16 [c]) o:(Mul16 (Const16 [d]) x)) && uint16(d)%2 == 1 && o.Uses == 1 => ((Eq|Neq)16 (Const16 [int16(uint16(c) * uint16(modularMultiplicativeInverse(uint64(d))))]) x) +((Eq|Neq)8 (Const8 [c]) o:(Mul8 (Const8 [d]) x)) && uint8( d)%2 == 1 && o.Uses == 1 => ((Eq|Neq)8 (Const8 [int8( uint8( c) * uint8( modularMultiplicativeInverse(uint64(d))))]) x) + // signed integer range: ( c <= x && x (<|<=) d ) -> ( unsigned(x-c) (<|<=) unsigned(d-c) ) (AndB (Leq64 (Const64 [c]) x) ((Less|Leq)64 x (Const64 [d]))) && d >= c => ((Less|Leq)64U (Sub64 x (Const64 [c])) (Const64 [d-c])) (AndB (Leq32 (Const32 [c]) x) ((Less|Leq)32 x (Const32 [d]))) && d >= c => ((Less|Leq)32U (Sub32 x (Const32 [c])) (Const32 [d-c])) @@ -347,6 +365,12 @@ (OrB ((Less|Leq)16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) && uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d) => ((Less|Leq)16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) (OrB ((Less|Leq)8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) && uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d) => ((Less|Leq)8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) +// single bit difference: ( x != c && x != d ) -> ( x|(c^d) != c ) +(AndB (Neq(64|32|16|8) x cv:(Const(64|32|16|8) [c])) (Neq(64|32|16|8) x (Const(64|32|16|8) [d]))) && c|d == c && oneBit(c^d) => (Neq(64|32|16|8) (Or(64|32|16|8) x (Const(64|32|16|8) [c^d])) cv) + +// single bit difference: ( x == c || x == d ) -> ( x|(c^d) == c ) +(OrB (Eq(64|32|16|8) x cv:(Const(64|32|16|8) [c])) (Eq(64|32|16|8) x (Const(64|32|16|8) [d]))) && c|d == c && oneBit(c^d) => (Eq(64|32|16|8) (Or(64|32|16|8) x (Const(64|32|16|8) [c^d])) cv) + // NaN check: ( x != x || x (>|>=|<|<=) c ) -> ( !(c (>=|>|<=|<) x) ) (OrB (Neq64F x x) ((Less|Leq)64F x y:(Const64F [c]))) => (Not ((Leq|Less)64F y x)) (OrB (Neq64F x x) ((Less|Leq)64F y:(Const64F [c]) x)) => (Not ((Leq|Less)64F x y)) @@ -380,13 +404,15 @@ // Distribute multiplication c * (d+x) -> c*d + c*x. Useful for: // a[i].b = ...; a[i+1].b = ... -(Mul64 (Const64 [c]) (Add64 (Const64 [d]) x)) => +// The !isPowerOfTwo is a kludge to keep a[i+1] using an index by a multiply, +// which turns into an index by a shift, which can use a shifted operand on ARM systems. +(Mul64 (Const64 [c]) (Add64 (Const64 [d]) x)) && !isPowerOfTwo(c) => (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) -(Mul32 (Const32 [c]) (Add32 (Const32 [d]) x)) => +(Mul32 (Const32 [c]) (Add32 (Const32 [d]) x)) && !isPowerOfTwo(c) => (Add32 (Const32 [c*d]) (Mul32 (Const32 [c]) x)) -(Mul16 (Const16 [c]) (Add16 (Const16 [d]) x)) => +(Mul16 (Const16 [c]) (Add16 (Const16 [d]) x)) && !isPowerOfTwo(c) => (Add16 (Const16 [c*d]) (Mul16 (Const16 [c]) x)) -(Mul8 (Const8 [c]) (Add8 (Const8 [d]) x)) => +(Mul8 (Const8 [c]) (Add8 (Const8 [d]) x)) && !isPowerOfTwo(c) => (Add8 (Const8 [c*d]) (Mul8 (Const8 [c]) x)) // Rewrite x*y ± x*z to x*(y±z) @@ -395,47 +421,52 @@ (Sub(64|32|16|8) (Mul(64|32|16|8) x y) (Mul(64|32|16|8) x z)) => (Mul(64|32|16|8) x (Sub(64|32|16|8) y z)) +// Canonicalize x+x to x << 1. +// This is often slower since most CPUs have more adders than shifters, but it can enable other optimizations. +// Arches who care about this like AMD64 convert x << 1 back to x+x in their arch-specific rules which is useful anyhow. +(Add(64|32|16|8) x x) => (Lsh(64|32|16|8)x64 x (Const64 [1])) + // rewrite shifts of 8/16/32 bit consts into 64 bit consts to reduce // the number of the other rewrite rules for const shifts -(Lsh64x32 x (Const32 [c])) => (Lsh64x64 x (Const64 [int64(uint32(c))])) -(Lsh64x16 x (Const16 [c])) => (Lsh64x64 x (Const64 [int64(uint16(c))])) -(Lsh64x8 x (Const8 [c])) => (Lsh64x64 x (Const64 [int64(uint8(c))])) -(Rsh64x32 x (Const32 [c])) => (Rsh64x64 x (Const64 [int64(uint32(c))])) -(Rsh64x16 x (Const16 [c])) => (Rsh64x64 x (Const64 [int64(uint16(c))])) -(Rsh64x8 x (Const8 [c])) => (Rsh64x64 x (Const64 [int64(uint8(c))])) -(Rsh64Ux32 x (Const32 [c])) => (Rsh64Ux64 x (Const64 [int64(uint32(c))])) -(Rsh64Ux16 x (Const16 [c])) => (Rsh64Ux64 x (Const64 [int64(uint16(c))])) -(Rsh64Ux8 x (Const8 [c])) => (Rsh64Ux64 x (Const64 [int64(uint8(c))])) - -(Lsh32x32 x (Const32 [c])) => (Lsh32x64 x (Const64 [int64(uint32(c))])) -(Lsh32x16 x (Const16 [c])) => (Lsh32x64 x (Const64 [int64(uint16(c))])) -(Lsh32x8 x (Const8 [c])) => (Lsh32x64 x (Const64 [int64(uint8(c))])) -(Rsh32x32 x (Const32 [c])) => (Rsh32x64 x (Const64 [int64(uint32(c))])) -(Rsh32x16 x (Const16 [c])) => (Rsh32x64 x (Const64 [int64(uint16(c))])) -(Rsh32x8 x (Const8 [c])) => (Rsh32x64 x (Const64 [int64(uint8(c))])) -(Rsh32Ux32 x (Const32 [c])) => (Rsh32Ux64 x (Const64 [int64(uint32(c))])) -(Rsh32Ux16 x (Const16 [c])) => (Rsh32Ux64 x (Const64 [int64(uint16(c))])) -(Rsh32Ux8 x (Const8 [c])) => (Rsh32Ux64 x (Const64 [int64(uint8(c))])) - -(Lsh16x32 x (Const32 [c])) => (Lsh16x64 x (Const64 [int64(uint32(c))])) -(Lsh16x16 x (Const16 [c])) => (Lsh16x64 x (Const64 [int64(uint16(c))])) -(Lsh16x8 x (Const8 [c])) => (Lsh16x64 x (Const64 [int64(uint8(c))])) -(Rsh16x32 x (Const32 [c])) => (Rsh16x64 x (Const64 [int64(uint32(c))])) -(Rsh16x16 x (Const16 [c])) => (Rsh16x64 x (Const64 [int64(uint16(c))])) -(Rsh16x8 x (Const8 [c])) => (Rsh16x64 x (Const64 [int64(uint8(c))])) -(Rsh16Ux32 x (Const32 [c])) => (Rsh16Ux64 x (Const64 [int64(uint32(c))])) -(Rsh16Ux16 x (Const16 [c])) => (Rsh16Ux64 x (Const64 [int64(uint16(c))])) -(Rsh16Ux8 x (Const8 [c])) => (Rsh16Ux64 x (Const64 [int64(uint8(c))])) - -(Lsh8x32 x (Const32 [c])) => (Lsh8x64 x (Const64 [int64(uint32(c))])) -(Lsh8x16 x (Const16 [c])) => (Lsh8x64 x (Const64 [int64(uint16(c))])) -(Lsh8x8 x (Const8 [c])) => (Lsh8x64 x (Const64 [int64(uint8(c))])) -(Rsh8x32 x (Const32 [c])) => (Rsh8x64 x (Const64 [int64(uint32(c))])) -(Rsh8x16 x (Const16 [c])) => (Rsh8x64 x (Const64 [int64(uint16(c))])) -(Rsh8x8 x (Const8 [c])) => (Rsh8x64 x (Const64 [int64(uint8(c))])) -(Rsh8Ux32 x (Const32 [c])) => (Rsh8Ux64 x (Const64 [int64(uint32(c))])) -(Rsh8Ux16 x (Const16 [c])) => (Rsh8Ux64 x (Const64 [int64(uint16(c))])) -(Rsh8Ux8 x (Const8 [c])) => (Rsh8Ux64 x (Const64 [int64(uint8(c))])) +(Lsh64x32 x (Const32 [c])) => (Lsh64x64 x (Const64 [int64(uint32(c))])) +(Lsh64x16 x (Const16 [c])) => (Lsh64x64 x (Const64 [int64(uint16(c))])) +(Lsh64x8 x (Const8 [c])) => (Lsh64x64 x (Const64 [int64(uint8(c))])) +(Rsh64x32 x (Const32 [c])) => (Rsh64x64 x (Const64 [int64(uint32(c))])) +(Rsh64x16 x (Const16 [c])) => (Rsh64x64 x (Const64 [int64(uint16(c))])) +(Rsh64x8 x (Const8 [c])) => (Rsh64x64 x (Const64 [int64(uint8(c))])) +(Rsh64Ux32 x (Const32 [c])) => (Rsh64Ux64 x (Const64 [int64(uint32(c))])) +(Rsh64Ux16 x (Const16 [c])) => (Rsh64Ux64 x (Const64 [int64(uint16(c))])) +(Rsh64Ux8 x (Const8 [c])) => (Rsh64Ux64 x (Const64 [int64(uint8(c))])) + +(Lsh32x32 x (Const32 [c])) => (Lsh32x64 x (Const64 [int64(uint32(c))])) +(Lsh32x16 x (Const16 [c])) => (Lsh32x64 x (Const64 [int64(uint16(c))])) +(Lsh32x8 x (Const8 [c])) => (Lsh32x64 x (Const64 [int64(uint8(c))])) +(Rsh32x32 x (Const32 [c])) => (Rsh32x64 x (Const64 [int64(uint32(c))])) +(Rsh32x16 x (Const16 [c])) => (Rsh32x64 x (Const64 [int64(uint16(c))])) +(Rsh32x8 x (Const8 [c])) => (Rsh32x64 x (Const64 [int64(uint8(c))])) +(Rsh32Ux32 x (Const32 [c])) => (Rsh32Ux64 x (Const64 [int64(uint32(c))])) +(Rsh32Ux16 x (Const16 [c])) => (Rsh32Ux64 x (Const64 [int64(uint16(c))])) +(Rsh32Ux8 x (Const8 [c])) => (Rsh32Ux64 x (Const64 [int64(uint8(c))])) + +(Lsh16x32 x (Const32 [c])) => (Lsh16x64 x (Const64 [int64(uint32(c))])) +(Lsh16x16 x (Const16 [c])) => (Lsh16x64 x (Const64 [int64(uint16(c))])) +(Lsh16x8 x (Const8 [c])) => (Lsh16x64 x (Const64 [int64(uint8(c))])) +(Rsh16x32 x (Const32 [c])) => (Rsh16x64 x (Const64 [int64(uint32(c))])) +(Rsh16x16 x (Const16 [c])) => (Rsh16x64 x (Const64 [int64(uint16(c))])) +(Rsh16x8 x (Const8 [c])) => (Rsh16x64 x (Const64 [int64(uint8(c))])) +(Rsh16Ux32 x (Const32 [c])) => (Rsh16Ux64 x (Const64 [int64(uint32(c))])) +(Rsh16Ux16 x (Const16 [c])) => (Rsh16Ux64 x (Const64 [int64(uint16(c))])) +(Rsh16Ux8 x (Const8 [c])) => (Rsh16Ux64 x (Const64 [int64(uint8(c))])) + +(Lsh8x32 x (Const32 [c])) => (Lsh8x64 x (Const64 [int64(uint32(c))])) +(Lsh8x16 x (Const16 [c])) => (Lsh8x64 x (Const64 [int64(uint16(c))])) +(Lsh8x8 x (Const8 [c])) => (Lsh8x64 x (Const64 [int64(uint8(c))])) +(Rsh8x32 x (Const32 [c])) => (Rsh8x64 x (Const64 [int64(uint32(c))])) +(Rsh8x16 x (Const16 [c])) => (Rsh8x64 x (Const64 [int64(uint16(c))])) +(Rsh8x8 x (Const8 [c])) => (Rsh8x64 x (Const64 [int64(uint8(c))])) +(Rsh8Ux32 x (Const32 [c])) => (Rsh8Ux64 x (Const64 [int64(uint32(c))])) +(Rsh8Ux16 x (Const16 [c])) => (Rsh8Ux64 x (Const64 [int64(uint16(c))])) +(Rsh8Ux8 x (Const8 [c])) => (Rsh8Ux64 x (Const64 [int64(uint8(c))])) // shifts by zero (Lsh(64|32|16|8)x64 x (Const64 [0])) => x @@ -629,6 +660,10 @@ (Sub(64|32|16|8) (Com(64|32|16|8) x) (Neg(64|32|16|8) x)) => (Const(64|32|16|8) [-1]) (Add(64|32|16|8) (Com(64|32|16|8) x) x) => (Const(64|32|16|8) [-1]) +// Prove does not simplify this because x + y might overflow into carry, +// however if no one care about the carry, let it overflow in a normal add. +(Select0 a:(Add64carry x y (Const64 [0]))) && a.Uses == 1 => (Add64 x y) + // Simplification when involving common integer // (t + x) - (t + y) == x - y // (t + x) - (y + t) == x - y @@ -785,6 +820,12 @@ && disjoint(p5, t5.Size(), p4, t4.Size()) => x +// Load from a region just copied by Move can read directly from the source. +(Load op:(OffPtr [o1] p1) move:(Move [n] p2 src mem)) + && o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p2) + && !isVolatile(src) + => @move.Block (Load (OffPtr [o1] src) mem) + // Pass constants through math.Float{32,64}bits and math.Float{32,64}frombits (Load p1 (Store {t2} p2 (Const64 [x]) _)) && isSamePtr(p1,p2) && t2.Size() == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x))) => (Const64F [math.Float64frombits(uint64(x))]) (Load p1 (Store {t2} p2 (Const32 [x]) _)) && isSamePtr(p1,p2) && t2.Size() == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x)))) => (Const32F [math.Float32frombits(uint32(x))]) @@ -930,15 +971,16 @@ // struct operations (StructSelect [i] x:(StructMake ___)) => x.Args[i] -(Load _ _) && t.IsStruct() && CanSSA(t) => rewriteStructLoad(v) +(Load _ _) && t.IsStruct() && t.Size() > 0 && CanSSA(t) && !t.IsSIMD() => rewriteStructLoad(v) (Store _ (StructMake ___) _) => rewriteStructStore(v) (StructSelect [i] x:(Load ptr mem)) && !CanSSA(t) => @x.Block (Load (OffPtr [t.FieldOff(int(i))] ptr) mem) // Putting struct{*byte} and similar into direct interfaces. -(IMake _typ (StructMake val)) => (IMake _typ val) -(StructSelect [0] (IData x)) => (IData x) +(IMake _typ (StructMake ___)) => imakeOfStructMake(v) +(StructSelect (IData x)) && v.Type.Size() > 0 => (IData x) +(StructSelect (IData x)) && v.Type.Size() == 0 => (Empty) // un-SSAable values use mem->mem copies (Store {t} dst (Load src mem) mem) && !CanSSA(t) => @@ -949,19 +991,19 @@ // array ops (ArraySelect (ArrayMake1 x)) => x -(Load _ _) && t.IsArray() && t.NumElem() == 0 => - (ArrayMake0) - (Load ptr mem) && t.IsArray() && t.NumElem() == 1 && CanSSA(t) => (ArrayMake1 (Load ptr mem)) -(Store _ (ArrayMake0) mem) => mem (Store dst (ArrayMake1 e) mem) => (Store {e.Type} dst e mem) // Putting [1]*byte and similar into direct interfaces. (IMake _typ (ArrayMake1 val)) => (IMake _typ val) (ArraySelect [0] (IData x)) => (IData x) +// zero-sized values. +(Load _ _) && t.Size() == 0 => (Empty) +(Store _ (Empty) mem) => mem + // string ops // Decomposing StringMake and lowering of StringPtr and StringLen // happens in a later pass, dec, so that these operations are available @@ -1004,6 +1046,8 @@ (ConstNil ) (Const64 [0]) (Const64 [0])) +(SliceLen (Phi (SliceMake _ x _) (SliceMake _ x _))) => x +(SliceCap (Phi (SliceMake _ _ x) (SliceMake _ _ x))) => x // Special rule to help constant slicing; len > 0 implies cap > 0 implies Slicemask is all 1 (SliceMake (AddPtr x (And64 y (Slicemask _))) w:(Const64 [c]) z) && c > 0 => (SliceMake (AddPtr x y) w z) @@ -1030,176 +1074,9 @@ // We must ensure that no intermediate computations are invalid pointers. (Convert a:(Add(64|32) (Add(64|32) (Convert ptr mem) off1) off2) mem) => (AddPtr ptr (Add(64|32) off1 off2)) -// strength reduction of divide by a constant. -// See ../magic.go for a detailed description of these algorithms. - -// Unsigned divide by power of 2. Strength reduce to a shift. -(Div8u n (Const8 [c])) && isUnsignedPowerOfTwo(uint8(c)) => (Rsh8Ux64 n (Const64 [log8u(uint8(c))])) -(Div16u n (Const16 [c])) && isUnsignedPowerOfTwo(uint16(c)) => (Rsh16Ux64 n (Const64 [log16u(uint16(c))])) -(Div32u n (Const32 [c])) && isUnsignedPowerOfTwo(uint32(c)) => (Rsh32Ux64 n (Const64 [log32u(uint32(c))])) -(Div64u n (Const64 [c])) && isUnsignedPowerOfTwo(uint64(c)) => (Rsh64Ux64 n (Const64 [log64u(uint64(c))])) - -// Signed non-negative divide by power of 2. -(Div8 n (Const8 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (Rsh8Ux64 n (Const64 [log8(c)])) -(Div16 n (Const16 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (Rsh16Ux64 n (Const64 [log16(c)])) -(Div32 n (Const32 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (Rsh32Ux64 n (Const64 [log32(c)])) -(Div64 n (Const64 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (Rsh64Ux64 n (Const64 [log64(c)])) -(Div64 n (Const64 [-1<<63])) && isNonNegative(n) => (Const64 [0]) - -// Unsigned divide, not a power of 2. Strength reduce to a multiply. -// For 8-bit divides, we just do a direct 9-bit by 8-bit multiply. -(Div8u x (Const8 [c])) && umagicOK8(c) => - (Trunc32to8 - (Rsh32Ux64 - (Mul32 - (Const32 [int32(1<<8+umagic8(c).m)]) - (ZeroExt8to32 x)) - (Const64 [8+umagic8(c).s]))) - -// For 16-bit divides on 64-bit machines, we do a direct 17-bit by 16-bit multiply. -(Div16u x (Const16 [c])) && umagicOK16(c) && config.RegSize == 8 => - (Trunc64to16 - (Rsh64Ux64 - (Mul64 - (Const64 [int64(1<<16+umagic16(c).m)]) - (ZeroExt16to64 x)) - (Const64 [16+umagic16(c).s]))) - -// For 16-bit divides on 32-bit machines -(Div16u x (Const16 [c])) && umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0 => - (Trunc32to16 - (Rsh32Ux64 - (Mul32 - (Const32 [int32(1<<15+umagic16(c).m/2)]) - (ZeroExt16to32 x)) - (Const64 [16+umagic16(c).s-1]))) -(Div16u x (Const16 [c])) && umagicOK16(c) && config.RegSize == 4 && c&1 == 0 => - (Trunc32to16 - (Rsh32Ux64 - (Mul32 - (Const32 [int32(1<<15+(umagic16(c).m+1)/2)]) - (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) - (Const64 [16+umagic16(c).s-2]))) -(Div16u x (Const16 [c])) && umagicOK16(c) && config.RegSize == 4 && config.useAvg => - (Trunc32to16 - (Rsh32Ux64 - (Avg32u - (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) - (Mul32 - (Const32 [int32(umagic16(c).m)]) - (ZeroExt16to32 x))) - (Const64 [16+umagic16(c).s-1]))) - -// For 32-bit divides on 32-bit machines -(Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul => - (Rsh32Ux64 - (Hmul32u - (Const32 [int32(1<<31+umagic32(c).m/2)]) - x) - (Const64 [umagic32(c).s-1])) -(Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul => - (Rsh32Ux64 - (Hmul32u - (Const32 [int32(1<<31+(umagic32(c).m+1)/2)]) - (Rsh32Ux64 x (Const64 [1]))) - (Const64 [umagic32(c).s-2])) -(Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul => - (Rsh32Ux64 - (Avg32u - x - (Hmul32u - (Const32 [int32(umagic32(c).m)]) - x)) - (Const64 [umagic32(c).s-1])) - -// For 32-bit divides on 64-bit machines -// We'll use a regular (non-hi) multiply for this case. -(Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0 => - (Trunc64to32 - (Rsh64Ux64 - (Mul64 - (Const64 [int64(1<<31+umagic32(c).m/2)]) - (ZeroExt32to64 x)) - (Const64 [32+umagic32(c).s-1]))) -(Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 8 && c&1 == 0 => - (Trunc64to32 - (Rsh64Ux64 - (Mul64 - (Const64 [int64(1<<31+(umagic32(c).m+1)/2)]) - (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) - (Const64 [32+umagic32(c).s-2]))) -(Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 8 && config.useAvg => - (Trunc64to32 - (Rsh64Ux64 - (Avg64u - (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) - (Mul64 - (Const64 [int64(umagic32(c).m)]) - (ZeroExt32to64 x))) - (Const64 [32+umagic32(c).s-1]))) - -// For unsigned 64-bit divides on 32-bit machines, -// if the constant fits in 16 bits (so that the last term -// fits in 32 bits), convert to three 32-bit divides by a constant. -// -// If 1<<32 = Q * c + R -// and x = hi << 32 + lo -// -// Then x = (hi/c*c + hi%c) << 32 + lo -// = hi/c*c<<32 + hi%c<<32 + lo -// = hi/c*c<<32 + (hi%c)*(Q*c+R) + lo/c*c + lo%c -// = hi/c*c<<32 + (hi%c)*Q*c + lo/c*c + (hi%c*R+lo%c) -// and x / c = (hi/c)<<32 + (hi%c)*Q + lo/c + (hi%c*R+lo%c)/c -(Div64u x (Const64 [c])) && c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul => - (Add64 - (Add64 - (Add64 - (Lsh64x64 - (ZeroExt32to64 - (Div32u - (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) - (Const32 [int32(c)]))) - (Const64 [32])) - (ZeroExt32to64 (Div32u (Trunc64to32 x) (Const32 [int32(c)])))) - (Mul64 - (ZeroExt32to64 - (Mod32u - (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) - (Const32 [int32(c)]))) - (Const64 [int64((1<<32)/c)]))) - (ZeroExt32to64 - (Div32u - (Add32 - (Mod32u (Trunc64to32 x) (Const32 [int32(c)])) - (Mul32 - (Mod32u - (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) - (Const32 [int32(c)])) - (Const32 [int32((1<<32)%c)]))) - (Const32 [int32(c)])))) - -// For 64-bit divides on 64-bit machines -// (64-bit divides on 32-bit machines are lowered to a runtime call by the walk pass.) -(Div64u x (Const64 [c])) && umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul => - (Rsh64Ux64 - (Hmul64u - (Const64 [int64(1<<63+umagic64(c).m/2)]) - x) - (Const64 [umagic64(c).s-1])) -(Div64u x (Const64 [c])) && umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul => - (Rsh64Ux64 - (Hmul64u - (Const64 [int64(1<<63+(umagic64(c).m+1)/2)]) - (Rsh64Ux64 x (Const64 [1]))) - (Const64 [umagic64(c).s-2])) -(Div64u x (Const64 [c])) && umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul => - (Rsh64Ux64 - (Avg64u - x - (Hmul64u - (Const64 [int64(umagic64(c).m)]) - x)) - (Const64 [umagic64(c).s-1])) +// Simplification of divisions. +// Only trivial, easily analyzed (by prove) rewrites here. +// Strength reduction of div to mul is delayed to divmod.rules. // Signed divide by a negative constant. Rewrite to divide by a positive constant. (Div8 n (Const8 [c])) && c < 0 && c != -1<<7 => (Neg8 (Div8 n (Const8 [-c]))) @@ -1210,115 +1087,50 @@ // Dividing by the most-negative number. Result is always 0 except // if the input is also the most-negative number. // We can detect that using the sign bit of x & -x. +(Div64 x (Const64 [-1<<63])) && isNonNegative(x) => (Const64 [0]) (Div8 x (Const8 [-1<<7 ])) => (Rsh8Ux64 (And8 x (Neg8 x)) (Const64 [7 ])) (Div16 x (Const16 [-1<<15])) => (Rsh16Ux64 (And16 x (Neg16 x)) (Const64 [15])) (Div32 x (Const32 [-1<<31])) => (Rsh32Ux64 (And32 x (Neg32 x)) (Const64 [31])) (Div64 x (Const64 [-1<<63])) => (Rsh64Ux64 (And64 x (Neg64 x)) (Const64 [63])) -// Signed divide by power of 2. -// n / c = n >> log(c) if n >= 0 -// = (n+c-1) >> log(c) if n < 0 -// We conditionally add c-1 by adding n>>63>>(64-log(c)) (first shift signed, second shift unsigned). -(Div8 n (Const8 [c])) && isPowerOfTwo(c) => - (Rsh8x64 - (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [int64( 8-log8(c))]))) - (Const64 [int64(log8(c))])) -(Div16 n (Const16 [c])) && isPowerOfTwo(c) => - (Rsh16x64 - (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [int64(16-log16(c))]))) - (Const64 [int64(log16(c))])) -(Div32 n (Const32 [c])) && isPowerOfTwo(c) => - (Rsh32x64 - (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [int64(32-log32(c))]))) - (Const64 [int64(log32(c))])) -(Div64 n (Const64 [c])) && isPowerOfTwo(c) => - (Rsh64x64 - (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [int64(64-log64(c))]))) - (Const64 [int64(log64(c))])) - -// Signed divide, not a power of 2. Strength reduce to a multiply. -(Div8 x (Const8 [c])) && smagicOK8(c) => - (Sub8 - (Rsh32x64 - (Mul32 - (Const32 [int32(smagic8(c).m)]) - (SignExt8to32 x)) - (Const64 [8+smagic8(c).s])) - (Rsh32x64 - (SignExt8to32 x) - (Const64 [31]))) -(Div16 x (Const16 [c])) && smagicOK16(c) => - (Sub16 - (Rsh32x64 - (Mul32 - (Const32 [int32(smagic16(c).m)]) - (SignExt16to32 x)) - (Const64 [16+smagic16(c).s])) - (Rsh32x64 - (SignExt16to32 x) - (Const64 [31]))) -(Div32 x (Const32 [c])) && smagicOK32(c) && config.RegSize == 8 => - (Sub32 - (Rsh64x64 - (Mul64 - (Const64 [int64(smagic32(c).m)]) - (SignExt32to64 x)) - (Const64 [32+smagic32(c).s])) - (Rsh64x64 - (SignExt32to64 x) - (Const64 [63]))) -(Div32 x (Const32 [c])) && smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul => - (Sub32 - (Rsh32x64 - (Hmul32 - (Const32 [int32(smagic32(c).m/2)]) - x) - (Const64 [smagic32(c).s-1])) - (Rsh32x64 - x - (Const64 [31]))) -(Div32 x (Const32 [c])) && smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul => - (Sub32 - (Rsh32x64 - (Add32 - (Hmul32 - (Const32 [int32(smagic32(c).m)]) - x) - x) - (Const64 [smagic32(c).s])) - (Rsh32x64 - x - (Const64 [31]))) -(Div64 x (Const64 [c])) && smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul => - (Sub64 - (Rsh64x64 - (Hmul64 - (Const64 [int64(smagic64(c).m/2)]) - x) - (Const64 [smagic64(c).s-1])) - (Rsh64x64 - x - (Const64 [63]))) -(Div64 x (Const64 [c])) && smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul => - (Sub64 - (Rsh64x64 - (Add64 - (Hmul64 - (Const64 [int64(smagic64(c).m)]) - x) - x) - (Const64 [smagic64(c).s])) - (Rsh64x64 - x - (Const64 [63]))) +// Unsigned divide by power of 2. Strength reduce to a shift. +(Div8u n (Const8 [c])) && isPowerOfTwo(uint8(c)) => (Rsh8Ux64 n (Const64 [log8u(uint8(c))])) +(Div16u n (Const16 [c])) && isPowerOfTwo(uint16(c)) => (Rsh16Ux64 n (Const64 [log16u(uint16(c))])) +(Div32u n (Const32 [c])) && isPowerOfTwo(uint32(c)) => (Rsh32Ux64 n (Const64 [log32u(uint32(c))])) +(Div64u n (Const64 [c])) && isPowerOfTwo(uint64(c)) => (Rsh64Ux64 n (Const64 [log64u(uint64(c))])) + +// Strength reduce multiplication by a power of two to a shift. +// Excluded from early opt so that prove can recognize mod +// by the x - (x/d)*d pattern. +// (Runs during "middle opt" and "late opt".) +(Mul8 x (Const8 [c])) && isPowerOfTwo(uint8(c)) && v.Block.Func.pass.name != "opt" => + (Lsh8x64 x (Const64 [log8u(uint8(c))])) +(Mul16 x (Const16 [c])) && isPowerOfTwo(uint16(c)) && v.Block.Func.pass.name != "opt" => + (Lsh16x64 x (Const64 [log16u(uint16(c))])) +(Mul32 x (Const32 [c])) && isPowerOfTwo(uint32(c)) && v.Block.Func.pass.name != "opt" => + (Lsh32x64 x (Const64 [log32u(uint32(c))])) +(Mul64 x (Const64 [c])) && isPowerOfTwo(uint64(c)) && v.Block.Func.pass.name != "opt" => + (Lsh64x64 x (Const64 [log64u(uint64(c))])) +(Mul8 x (Const8 [c])) && isPowerOfTwo(uint8(-c)) && v.Block.Func.pass.name != "opt" => + (Neg8 (Lsh8x64 x (Const64 [log8u(uint8(-c))]))) +(Mul16 x (Const16 [c])) && isPowerOfTwo(uint16(-c)) && v.Block.Func.pass.name != "opt" => + (Neg16 (Lsh16x64 x (Const64 [log16u(uint16(-c))]))) +(Mul32 x (Const32 [c])) && isPowerOfTwo(uint32(-c)) && v.Block.Func.pass.name != "opt" => + (Neg32 (Lsh32x64 x (Const64 [log32u(uint32(-c))]))) +(Mul64 x (Const64 [c])) && isPowerOfTwo(uint64(-c)) && v.Block.Func.pass.name != "opt" => + (Neg64 (Lsh64x64 x (Const64 [log64u(uint64(-c))]))) + +// Strength reduction of mod to div. +// Strength reduction of div to mul is delayed to divmod.rules. // Unsigned mod by power of 2 constant. -(Mod8u n (Const8 [c])) && isUnsignedPowerOfTwo(uint8(c)) => (And8 n (Const8 [c-1])) -(Mod16u n (Const16 [c])) && isUnsignedPowerOfTwo(uint16(c)) => (And16 n (Const16 [c-1])) -(Mod32u n (Const32 [c])) && isUnsignedPowerOfTwo(uint32(c)) => (And32 n (Const32 [c-1])) -(Mod64u n (Const64 [c])) && isUnsignedPowerOfTwo(uint64(c)) => (And64 n (Const64 [c-1])) +(Mod8u n (Const8 [c])) && isPowerOfTwo(uint8(c)) => (And8 n (Const8 [c-1])) +(Mod16u n (Const16 [c])) && isPowerOfTwo(uint16(c)) => (And16 n (Const16 [c-1])) +(Mod32u n (Const32 [c])) && isPowerOfTwo(uint32(c)) => (And32 n (Const32 [c-1])) +(Mod64u n (Const64 [c])) && isPowerOfTwo(uint64(c)) => (And64 n (Const64 [c-1])) // Signed non-negative mod by power of 2 constant. +// TODO: Replace ModN with ModNu in prove. (Mod8 n (Const8 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (And8 n (Const8 [c-1])) (Mod16 n (Const16 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (And16 n (Const16 [c-1])) (Mod32 n (Const32 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (And32 n (Const32 [c-1])) @@ -1342,16 +1154,18 @@ => (Sub32 x (Mul32 (Div32 x (Const32 [c])) (Const32 [c]))) (Mod64 x (Const64 [c])) && x.Op != OpConst64 && (c > 0 || c == -1<<63) => (Sub64 x (Mul64 (Div64 x (Const64 [c])) (Const64 [c]))) -(Mod8u x (Const8 [c])) && x.Op != OpConst8 && c > 0 && umagicOK8( c) +(Mod8u x (Const8 [c])) && x.Op != OpConst8 && c != 0 => (Sub8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) -(Mod16u x (Const16 [c])) && x.Op != OpConst16 && c > 0 && umagicOK16(c) +(Mod16u x (Const16 [c])) && x.Op != OpConst16 && c != 0 => (Sub16 x (Mul16 (Div16u x (Const16 [c])) (Const16 [c]))) -(Mod32u x (Const32 [c])) && x.Op != OpConst32 && c > 0 && umagicOK32(c) +(Mod32u x (Const32 [c])) && x.Op != OpConst32 && c != 0 => (Sub32 x (Mul32 (Div32u x (Const32 [c])) (Const32 [c]))) -(Mod64u x (Const64 [c])) && x.Op != OpConst64 && c > 0 && umagicOK64(c) +(Mod64u x (Const64 [c])) && x.Op != OpConst64 && c != 0 => (Sub64 x (Mul64 (Div64u x (Const64 [c])) (Const64 [c]))) -// For architectures without rotates on less than 32-bits, promote these checks to 32-bit. +// Set up for mod->mul+rot optimization in genericlateopt.rules. +// For architectures without rotates on less than 32-bits, promote to 32-bit. +// TODO: Also != 0 case? (Eq8 (Mod8u x (Const8 [c])) (Const8 [0])) && x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config) => (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [int32(uint8(c))])) (Const32 [0])) (Eq16 (Mod16u x (Const16 [c])) (Const16 [0])) && x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config) => @@ -1361,557 +1175,6 @@ (Eq16 (Mod16 x (Const16 [c])) (Const16 [0])) && x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config) => (Eq32 (Mod32 (SignExt16to32 x) (Const32 [int32(c)])) (Const32 [0])) -// Divisibility checks x%c == 0 convert to multiply and rotate. -// Note, x%c == 0 is rewritten as x == c*(x/c) during the opt pass -// where (x/c) is performed using multiplication with magic constants. -// To rewrite x%c == 0 requires pattern matching the rewritten expression -// and checking that the division by the same constant wasn't already calculated. -// This check is made by counting uses of the magic constant multiplication. -// Note that if there were an intermediate opt pass, this rule could be applied -// directly on the Div op and magic division rewrites could be delayed to late opt. - -// Unsigned divisibility checks convert to multiply and rotate. -(Eq8 x (Mul8 (Const8 [c]) - (Trunc32to8 - (Rsh32Ux64 - mul:(Mul32 - (Const32 [m]) - (ZeroExt8to32 x)) - (Const64 [s]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s - && x.Op != OpConst8 && udivisibleOK8(c) - => (Leq8U - (RotateLeft8 - (Mul8 - (Const8 [int8(udivisible8(c).m)]) - x) - (Const8 [int8(8-udivisible8(c).k)]) - ) - (Const8 [int8(udivisible8(c).max)]) - ) - -(Eq16 x (Mul16 (Const16 [c]) - (Trunc64to16 - (Rsh64Ux64 - mul:(Mul64 - (Const64 [m]) - (ZeroExt16to64 x)) - (Const64 [s]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s - && x.Op != OpConst16 && udivisibleOK16(c) - => (Leq16U - (RotateLeft16 - (Mul16 - (Const16 [int16(udivisible16(c).m)]) - x) - (Const16 [int16(16-udivisible16(c).k)]) - ) - (Const16 [int16(udivisible16(c).max)]) - ) - -(Eq16 x (Mul16 (Const16 [c]) - (Trunc32to16 - (Rsh32Ux64 - mul:(Mul32 - (Const32 [m]) - (ZeroExt16to32 x)) - (Const64 [s]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 - && x.Op != OpConst16 && udivisibleOK16(c) - => (Leq16U - (RotateLeft16 - (Mul16 - (Const16 [int16(udivisible16(c).m)]) - x) - (Const16 [int16(16-udivisible16(c).k)]) - ) - (Const16 [int16(udivisible16(c).max)]) - ) - -(Eq16 x (Mul16 (Const16 [c]) - (Trunc32to16 - (Rsh32Ux64 - mul:(Mul32 - (Const32 [m]) - (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) - (Const64 [s]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 - && x.Op != OpConst16 && udivisibleOK16(c) - => (Leq16U - (RotateLeft16 - (Mul16 - (Const16 [int16(udivisible16(c).m)]) - x) - (Const16 [int16(16-udivisible16(c).k)]) - ) - (Const16 [int16(udivisible16(c).max)]) - ) - -(Eq16 x (Mul16 (Const16 [c]) - (Trunc32to16 - (Rsh32Ux64 - (Avg32u - (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) - mul:(Mul32 - (Const32 [m]) - (ZeroExt16to32 x))) - (Const64 [s]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 - && x.Op != OpConst16 && udivisibleOK16(c) - => (Leq16U - (RotateLeft16 - (Mul16 - (Const16 [int16(udivisible16(c).m)]) - x) - (Const16 [int16(16-udivisible16(c).k)]) - ) - (Const16 [int16(udivisible16(c).max)]) - ) - -(Eq32 x (Mul32 (Const32 [c]) - (Rsh32Ux64 - mul:(Hmul32u - (Const32 [m]) - x) - (Const64 [s])) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 - && x.Op != OpConst32 && udivisibleOK32(c) - => (Leq32U - (RotateLeft32 - (Mul32 - (Const32 [int32(udivisible32(c).m)]) - x) - (Const32 [int32(32-udivisible32(c).k)]) - ) - (Const32 [int32(udivisible32(c).max)]) - ) - -(Eq32 x (Mul32 (Const32 [c]) - (Rsh32Ux64 - mul:(Hmul32u - (Const32 [m]) - (Rsh32Ux64 x (Const64 [1]))) - (Const64 [s])) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 - && x.Op != OpConst32 && udivisibleOK32(c) - => (Leq32U - (RotateLeft32 - (Mul32 - (Const32 [int32(udivisible32(c).m)]) - x) - (Const32 [int32(32-udivisible32(c).k)]) - ) - (Const32 [int32(udivisible32(c).max)]) - ) - -(Eq32 x (Mul32 (Const32 [c]) - (Rsh32Ux64 - (Avg32u - x - mul:(Hmul32u - (Const32 [m]) - x)) - (Const64 [s])) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(umagic32(c).m) && s == umagic32(c).s-1 - && x.Op != OpConst32 && udivisibleOK32(c) - => (Leq32U - (RotateLeft32 - (Mul32 - (Const32 [int32(udivisible32(c).m)]) - x) - (Const32 [int32(32-udivisible32(c).k)]) - ) - (Const32 [int32(udivisible32(c).max)]) - ) - -(Eq32 x (Mul32 (Const32 [c]) - (Trunc64to32 - (Rsh64Ux64 - mul:(Mul64 - (Const64 [m]) - (ZeroExt32to64 x)) - (Const64 [s]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 - && x.Op != OpConst32 && udivisibleOK32(c) - => (Leq32U - (RotateLeft32 - (Mul32 - (Const32 [int32(udivisible32(c).m)]) - x) - (Const32 [int32(32-udivisible32(c).k)]) - ) - (Const32 [int32(udivisible32(c).max)]) - ) - -(Eq32 x (Mul32 (Const32 [c]) - (Trunc64to32 - (Rsh64Ux64 - mul:(Mul64 - (Const64 [m]) - (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) - (Const64 [s]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 - && x.Op != OpConst32 && udivisibleOK32(c) - => (Leq32U - (RotateLeft32 - (Mul32 - (Const32 [int32(udivisible32(c).m)]) - x) - (Const32 [int32(32-udivisible32(c).k)]) - ) - (Const32 [int32(udivisible32(c).max)]) - ) - -(Eq32 x (Mul32 (Const32 [c]) - (Trunc64to32 - (Rsh64Ux64 - (Avg64u - (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) - mul:(Mul64 - (Const64 [m]) - (ZeroExt32to64 x))) - (Const64 [s]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 - && x.Op != OpConst32 && udivisibleOK32(c) - => (Leq32U - (RotateLeft32 - (Mul32 - (Const32 [int32(udivisible32(c).m)]) - x) - (Const32 [int32(32-udivisible32(c).k)]) - ) - (Const32 [int32(udivisible32(c).max)]) - ) - -(Eq64 x (Mul64 (Const64 [c]) - (Rsh64Ux64 - mul:(Hmul64u - (Const64 [m]) - x) - (Const64 [s])) - ) -) && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 - && x.Op != OpConst64 && udivisibleOK64(c) - => (Leq64U - (RotateLeft64 - (Mul64 - (Const64 [int64(udivisible64(c).m)]) - x) - (Const64 [64-udivisible64(c).k]) - ) - (Const64 [int64(udivisible64(c).max)]) - ) -(Eq64 x (Mul64 (Const64 [c]) - (Rsh64Ux64 - mul:(Hmul64u - (Const64 [m]) - (Rsh64Ux64 x (Const64 [1]))) - (Const64 [s])) - ) -) && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 - && x.Op != OpConst64 && udivisibleOK64(c) - => (Leq64U - (RotateLeft64 - (Mul64 - (Const64 [int64(udivisible64(c).m)]) - x) - (Const64 [64-udivisible64(c).k]) - ) - (Const64 [int64(udivisible64(c).max)]) - ) -(Eq64 x (Mul64 (Const64 [c]) - (Rsh64Ux64 - (Avg64u - x - mul:(Hmul64u - (Const64 [m]) - x)) - (Const64 [s])) - ) -) && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int64(umagic64(c).m) && s == umagic64(c).s-1 - && x.Op != OpConst64 && udivisibleOK64(c) - => (Leq64U - (RotateLeft64 - (Mul64 - (Const64 [int64(udivisible64(c).m)]) - x) - (Const64 [64-udivisible64(c).k]) - ) - (Const64 [int64(udivisible64(c).max)]) - ) - -// Signed divisibility checks convert to multiply, add and rotate. -(Eq8 x (Mul8 (Const8 [c]) - (Sub8 - (Rsh32x64 - mul:(Mul32 - (Const32 [m]) - (SignExt8to32 x)) - (Const64 [s])) - (Rsh32x64 - (SignExt8to32 x) - (Const64 [31]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(smagic8(c).m) && s == 8+smagic8(c).s - && x.Op != OpConst8 && sdivisibleOK8(c) - => (Leq8U - (RotateLeft8 - (Add8 - (Mul8 - (Const8 [int8(sdivisible8(c).m)]) - x) - (Const8 [int8(sdivisible8(c).a)]) - ) - (Const8 [int8(8-sdivisible8(c).k)]) - ) - (Const8 [int8(sdivisible8(c).max)]) - ) - -(Eq16 x (Mul16 (Const16 [c]) - (Sub16 - (Rsh32x64 - mul:(Mul32 - (Const32 [m]) - (SignExt16to32 x)) - (Const64 [s])) - (Rsh32x64 - (SignExt16to32 x) - (Const64 [31]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(smagic16(c).m) && s == 16+smagic16(c).s - && x.Op != OpConst16 && sdivisibleOK16(c) - => (Leq16U - (RotateLeft16 - (Add16 - (Mul16 - (Const16 [int16(sdivisible16(c).m)]) - x) - (Const16 [int16(sdivisible16(c).a)]) - ) - (Const16 [int16(16-sdivisible16(c).k)]) - ) - (Const16 [int16(sdivisible16(c).max)]) - ) - -(Eq32 x (Mul32 (Const32 [c]) - (Sub32 - (Rsh64x64 - mul:(Mul64 - (Const64 [m]) - (SignExt32to64 x)) - (Const64 [s])) - (Rsh64x64 - (SignExt32to64 x) - (Const64 [63]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int64(smagic32(c).m) && s == 32+smagic32(c).s - && x.Op != OpConst32 && sdivisibleOK32(c) - => (Leq32U - (RotateLeft32 - (Add32 - (Mul32 - (Const32 [int32(sdivisible32(c).m)]) - x) - (Const32 [int32(sdivisible32(c).a)]) - ) - (Const32 [int32(32-sdivisible32(c).k)]) - ) - (Const32 [int32(sdivisible32(c).max)]) - ) - -(Eq32 x (Mul32 (Const32 [c]) - (Sub32 - (Rsh32x64 - mul:(Hmul32 - (Const32 [m]) - x) - (Const64 [s])) - (Rsh32x64 - x - (Const64 [31]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 - && x.Op != OpConst32 && sdivisibleOK32(c) - => (Leq32U - (RotateLeft32 - (Add32 - (Mul32 - (Const32 [int32(sdivisible32(c).m)]) - x) - (Const32 [int32(sdivisible32(c).a)]) - ) - (Const32 [int32(32-sdivisible32(c).k)]) - ) - (Const32 [int32(sdivisible32(c).max)]) - ) - -(Eq32 x (Mul32 (Const32 [c]) - (Sub32 - (Rsh32x64 - (Add32 - mul:(Hmul32 - (Const32 [m]) - x) - x) - (Const64 [s])) - (Rsh32x64 - x - (Const64 [31]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int32(smagic32(c).m) && s == smagic32(c).s - && x.Op != OpConst32 && sdivisibleOK32(c) - => (Leq32U - (RotateLeft32 - (Add32 - (Mul32 - (Const32 [int32(sdivisible32(c).m)]) - x) - (Const32 [int32(sdivisible32(c).a)]) - ) - (Const32 [int32(32-sdivisible32(c).k)]) - ) - (Const32 [int32(sdivisible32(c).max)]) - ) - -(Eq64 x (Mul64 (Const64 [c]) - (Sub64 - (Rsh64x64 - mul:(Hmul64 - (Const64 [m]) - x) - (Const64 [s])) - (Rsh64x64 - x - (Const64 [63]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 - && x.Op != OpConst64 && sdivisibleOK64(c) - => (Leq64U - (RotateLeft64 - (Add64 - (Mul64 - (Const64 [int64(sdivisible64(c).m)]) - x) - (Const64 [int64(sdivisible64(c).a)]) - ) - (Const64 [64-sdivisible64(c).k]) - ) - (Const64 [int64(sdivisible64(c).max)]) - ) - -(Eq64 x (Mul64 (Const64 [c]) - (Sub64 - (Rsh64x64 - (Add64 - mul:(Hmul64 - (Const64 [m]) - x) - x) - (Const64 [s])) - (Rsh64x64 - x - (Const64 [63]))) - ) -) - && v.Block.Func.pass.name != "opt" && mul.Uses == 1 - && m == int64(smagic64(c).m) && s == smagic64(c).s - && x.Op != OpConst64 && sdivisibleOK64(c) - => (Leq64U - (RotateLeft64 - (Add64 - (Mul64 - (Const64 [int64(sdivisible64(c).m)]) - x) - (Const64 [int64(sdivisible64(c).a)]) - ) - (Const64 [64-sdivisible64(c).k]) - ) - (Const64 [int64(sdivisible64(c).max)]) - ) - -// Divisibility check for signed integers for power of two constant are simple mask. -// However, we must match against the rewritten n%c == 0 -> n - c*(n/c) == 0 -> n == c*(n/c) -// where n/c contains fixup code to handle signed n. -((Eq8|Neq8) n (Lsh8x64 - (Rsh8x64 - (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) - (Const64 [k])) - (Const64 [k])) -) && k > 0 && k < 7 && kbar == 8 - k - => ((Eq8|Neq8) (And8 n (Const8 [1< [0])) - -((Eq16|Neq16) n (Lsh16x64 - (Rsh16x64 - (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) - (Const64 [k])) - (Const64 [k])) -) && k > 0 && k < 15 && kbar == 16 - k - => ((Eq16|Neq16) (And16 n (Const16 [1< [0])) - -((Eq32|Neq32) n (Lsh32x64 - (Rsh32x64 - (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) - (Const64 [k])) - (Const64 [k])) -) && k > 0 && k < 31 && kbar == 32 - k - => ((Eq32|Neq32) (And32 n (Const32 [1< [0])) - -((Eq64|Neq64) n (Lsh64x64 - (Rsh64x64 - (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) - (Const64 [k])) - (Const64 [k])) -) && k > 0 && k < 63 && kbar == 64 - k - => ((Eq64|Neq64) (And64 n (Const64 [1< [0])) - (Eq(8|16|32|64) s:(Sub(8|16|32|64) x y) (Const(8|16|32|64) [0])) && s.Uses == 1 => (Eq(8|16|32|64) x y) (Neq(8|16|32|64) s:(Sub(8|16|32|64) x y) (Const(8|16|32|64) [0])) && s.Uses == 1 => (Neq(8|16|32|64) x y) @@ -1921,6 +1184,20 @@ (Neq(8|16|32|64) (And(8|16|32|64) x (Const(8|16|32|64) [y])) (Const(8|16|32|64) [y])) && oneBit(y) => (Eq(8|16|32|64) (And(8|16|32|64) x (Const(8|16|32|64) [y])) (Const(8|16|32|64) [0])) +// Mark newly generated bounded shifts as bounded, for opt passes after prove. +(Lsh64x(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 64 => (Lsh64x(8|16|32|64) [true] x con) +(Rsh64x(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 64 => (Rsh64x(8|16|32|64) [true] x con) +(Rsh64Ux(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 64 => (Rsh64Ux(8|16|32|64) [true] x con) +(Lsh32x(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 32 => (Lsh32x(8|16|32|64) [true] x con) +(Rsh32x(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 32 => (Rsh32x(8|16|32|64) [true] x con) +(Rsh32Ux(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 32 => (Rsh32Ux(8|16|32|64) [true] x con) +(Lsh16x(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 16 => (Lsh16x(8|16|32|64) [true] x con) +(Rsh16x(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 16 => (Rsh16x(8|16|32|64) [true] x con) +(Rsh16Ux(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 16 => (Rsh16Ux(8|16|32|64) [true] x con) +(Lsh8x(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 8 => (Lsh8x(8|16|32|64) [true] x con) +(Rsh8x(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 8 => (Rsh8x(8|16|32|64) [true] x con) +(Rsh8Ux(8|16|32|64) [false] x con:(Const(8|16|32|64) [c])) && 0 < c && c < 8 => (Rsh8Ux(8|16|32|64) [true] x con) + // Reassociate expressions involving // constants such that constants come first, // exposing obvious constant-folding opportunities. @@ -2279,6 +1556,78 @@ && isSamePtr(p, q) => (MakeResult (ConstBool [true]) mem) +(MemEq sptr tptr (Const64 [1]) mem) + => (Eq8 (Load sptr mem) (Load tptr mem)) + +(Load sptr:(Addr {scon} (SB)) mem) + && symIsRO(scon) + => (Const8 [int8(read8(scon,0))]) + +(MemEq sptr tptr (Const64 [2]) mem) + && canLoadUnaligned(config) + => (Eq16 (Load sptr mem) (Load tptr mem)) + +(Load sptr:(Addr {scon} (SB)) mem) + && symIsRO(scon) + => (Const16 [int16(read16(scon,0,config.ctxt.Arch.ByteOrder))]) + +(MemEq sptr tptr (Const64 [4]) mem) + && canLoadUnaligned(config) + => (Eq32 (Load sptr mem) (Load tptr mem)) + +(Load sptr:(Addr {scon} (SB)) mem) + && symIsRO(scon) + => (Const32 [int32(read32(scon,0,config.ctxt.Arch.ByteOrder))]) + +(MemEq sptr tptr (Const64 [8]) mem) + && canLoadUnaligned(config) && config.PtrSize == 8 + => (Eq64 (Load sptr mem) (Load tptr mem)) + +(Load sptr:(Addr {scon} (SB)) mem) + && symIsRO(scon) + => (Const64 [int64(read64(scon,0,config.ctxt.Arch.ByteOrder))]) + +(MemEq _ _ (Const64 [0]) _) => (ConstBool [true]) + +(MemEq p q _ _) && isSamePtr(p, q) => (ConstBool [true]) + +// 3-32 bytes memeq (enabled only with support of unaligned loads and 8-byte max word size) + +(MemEq p q (Const64 [c]) mem) + && (c == 3 || c == 5 || c == 9 || c == 17) + && canLoadUnaligned(config) + && config.RegSize == 8 + => (AndB (MemEq p q (Const64 [c-1]) mem) + (Eq8 (Load (OffPtr p [c-1]) mem) (Load (OffPtr q [c-1]) mem))) + +(MemEq p q (Const64 [c]) mem) + && (c == 6 || c == 10 || c == 18) + && canLoadUnaligned(config) + && config.RegSize == 8 + => (AndB (MemEq p q (Const64 [c-2]) mem) + (Eq16 (Load (OffPtr p [c-2]) mem) (Load (OffPtr q [c-2]) mem))) + +(MemEq p q (Const64 [c]) mem) + && (c == 7 || c == 11 || c == 19 || c == 20) + && canLoadUnaligned(config) + && config.RegSize == 8 + => (AndB (MemEq p q (Const64 [min(c-3,16)]) mem) + (Eq32 (Load (OffPtr p [c-4]) mem) (Load (OffPtr q [c-4]) mem))) + +(MemEq p q (Const64 [c]) mem) + && ((c >= 12 && c <= 16) || (c >= 21 && c <= 24)) + && canLoadUnaligned(config) + && config.RegSize == 8 + => (AndB (MemEq p q (Const64 [8 + int64(bool2int(c>16))*8]) mem) + (Eq64 (Load (OffPtr p [c-8]) mem) (Load (OffPtr q [c-8]) mem))) + +(MemEq p q (Const64 [c]) mem) + && c >= 25 && c <= 32 + && canLoadUnaligned(config) + && config.RegSize == 8 + => (AndB (MemEq p q (Const64 [16]) mem) + (MemEq (OffPtr p [16]) (OffPtr q [16]) (Const64 [c-16]) mem)) + // Turn known-size calls to memclrNoHeapPointers into a Zero. // Note that we are using types.Types[types.TUINT8] instead of sptr.Type.Elem() - see issue 55122 and CL 431496 for more details. (SelectN [0] call:(StaticCall {sym} sptr (Const(64|32) [c]) mem)) @@ -2773,8 +2122,13 @@ // See issue 56440. // Note there are 2 rules here, one for the pre-decomposed []T result and one for // the post-decomposed (*T,int,int) result. (The latter is generated after call expansion.) -(SliceLen (SelectN [0] (StaticLECall {sym} _ newLen:(Const(64|32)) _ _ _ _))) && isSameCall(sym, "runtime.growslice") => newLen -(SelectN [1] (StaticCall {sym} _ newLen:(Const(64|32)) _ _ _ _)) && v.Type.IsInteger() && isSameCall(sym, "runtime.growslice") => newLen +// TODO(thepudds): we probably need the new growsliceBuf and growsliceBufNoAlias here as well? +(SliceLen (SelectN [0] (StaticLECall {sym} _ newLen:(Const(64|32)) _ _ _ _))) + && (isSameCall(sym, "runtime.growslice") || isSameCall(sym, "runtime.growsliceNoAlias")) + => newLen +(SelectN [1] (StaticCall {sym} _ newLen:(Const(64|32)) _ _ _ _)) && v.Type.IsInteger() + && (isSameCall(sym, "runtime.growslice") || isSameCall(sym, "runtime.growsliceNoAlias")) + => newLen // Collapse moving A -> B -> C into just A -> C. // Later passes (deadstore, elim unread auto) will remove the A -> B move, if possible. @@ -2883,10 +2237,7 @@ (RotateLeft8 x (Sub(64|32|16|8) (Const(64|32|16|8) [c]) y)) && c&7 == 0 => (RotateLeft8 x (Neg(64|32|16|8) y)) // Ensure we don't do Const64 rotates in a 32-bit system. -(RotateLeft64 x (Const64 [c])) && config.PtrSize == 4 => (RotateLeft64 x (Const32 [int32(c)])) -(RotateLeft32 x (Const64 [c])) && config.PtrSize == 4 => (RotateLeft32 x (Const32 [int32(c)])) -(RotateLeft16 x (Const64 [c])) && config.PtrSize == 4 => (RotateLeft16 x (Const32 [int32(c)])) -(RotateLeft8 x (Const64 [c])) && config.PtrSize == 4 => (RotateLeft8 x (Const32 [int32(c)])) +(RotateLeft(64|32|16|8) x (Const64 [c])) && config.PtrSize == 4 => (RotateLeft(64|32|16|8) x (Const32 [int32(c)])) // Rotating by c, then by d, is the same as rotating by c+d. // We're trading a rotate for an add, which seems generally a good choice. It is especially good when c and d are constants. @@ -2923,7 +2274,7 @@ // we know the underlying type is pointer-ish. (StaticLECall {f} typ_ x y mem) && isSameCall(f, "runtime.efaceeq") - && isDirectType(typ_) + && isDirectAndComparableType(typ_) && clobber(v) => (MakeResult (EqPtr x y) mem) @@ -2931,7 +2282,7 @@ // we know the underlying type is pointer-ish. (StaticLECall {f} itab x y mem) && isSameCall(f, "runtime.ifaceeq") - && isDirectIface(itab) + && isDirectAndComparableIface(itab) && clobber(v) => (MakeResult (EqPtr x y) mem) @@ -2966,17 +2317,91 @@ => (StaticLECall {f} [argsize] dict_ (StringMake ptr len) mem) // Transform some CondSelect into math operations. -// if b { x++ } => x += b // but not on arm64 because it has CSINC -(CondSelect (Add8 x (Const8 [1])) x bool) && config.arch != "arm64" => (Add8 x (CvtBoolToUint8 bool)) -(CondSelect (Add(64|32|16) x (Const(64|32|16) [1])) x bool) && config.arch != "arm64" => (Add(64|32|16) x (ZeroExt8to(64|32|16) (CvtBoolToUint8 bool))) - -// if b { x-- } => x -= b -(CondSelect (Add8 x (Const8 [-1])) x bool) => (Sub8 x (CvtBoolToUint8 bool)) -(CondSelect (Add(64|32|16) x (Const(64|32|16) [-1])) x bool) => (Sub(64|32|16) x (ZeroExt8to(64|32|16) (CvtBoolToUint8 bool))) +// if b { x += c } => x += b * c +(CondSelect op:(Add8 x c:(Const8)) x bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Add8 x (Mul8 c (CvtBoolToUint8 bool))) +(CondSelect op:(Add(64|32|16) x c:(Const(64|32|16))) x bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Add(64|32|16) x (Mul(64|32|16) c (ZeroExt8to(64|32|16) (CvtBoolToUint8 bool)))) +// if !b { x += c } => x += !b * c +(CondSelect x op:(Add8 x c:(Const8)) bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Add8 x (Mul8 c (CvtBoolToUint8 (Not bool)))) +(CondSelect x op:(Add(64|32|16) x c:(Const(64|32|16))) bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Add(64|32|16) x (Mul(64|32|16) c (ZeroExt8to(64|32|16) (CvtBoolToUint8 (Not bool))))) + +// if b { x += c } => x -= b * -c // looks redundant but useful if the arch can inline materialize -c but not c +(CondSelect op:(Add8 x c:(Const8 [consT])) x bool) && + !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && + rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) => + (Sub8 x (Mul8 (Const8 [-consT]) (CvtBoolToUint8 bool))) +(CondSelect op:(Add(64|32|16) x c:(Const(64|32|16) [consT])) x bool) && + !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && + rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) => + (Sub(64|32|16) x (Mul(64|32|16) (Const(64|32|16) [-consT]) (ZeroExt8to(64|32|16) (CvtBoolToUint8 bool)))) +// if !b { x += c } => x -= !b * -c // looks redundant but useful if the arch can inline materialize -c but not c +(CondSelect x op:(Add8 x c:(Const8 [consT])) bool) && + !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && + rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) => + (Sub8 x (Mul8 (Const8 [-consT]) (CvtBoolToUint8 (Not bool)))) +(CondSelect x op:(Add(64|32|16) x c:(Const(64|32|16) [consT])) bool) && + !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && + rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) => + (Sub(64|32|16) x (Mul(64|32|16) (Const(64|32|16) [-consT]) (ZeroExt8to(64|32|16) (CvtBoolToUint8 (Not bool))))) // if b { x <<= 1 } => x <<= b (CondSelect (Lsh(64|32|16|8)x64 x (Const64 [1])) x bool) => (Lsh(64|32|16|8)x8 [true] x (CvtBoolToUint8 bool)) +// if !b { x <<= 1 } => x <<= !b +(CondSelect x (Lsh(64|32|16|8)x64 x (Const64 [1])) bool) => (Lsh(64|32|16|8)x8 [true] x (CvtBoolToUint8 (Not bool))) // if b { x >>= 1 } => x >>= b (CondSelect (Rsh(64|32|16|8)x64 x (Const64 [1])) x bool) => (Rsh(64|32|16|8)x8 [true] x (CvtBoolToUint8 bool)) (CondSelect (Rsh(64|32|16|8)Ux64 x (Const64 [1])) x bool) => (Rsh(64|32|16|8)Ux8 [true] x (CvtBoolToUint8 bool)) +// if !b { x >>= 1 } => x >>= !b +(CondSelect x (Rsh(64|32|16|8)x64 x (Const64 [1])) bool) => (Rsh(64|32|16|8)x8 [true] x (CvtBoolToUint8 (Not bool))) +(CondSelect x (Rsh(64|32|16|8)Ux64 x (Const64 [1])) bool) => (Rsh(64|32|16|8)Ux8 [true] x (CvtBoolToUint8 (Not bool))) + +// if b { x |= c } => x |= b * c +(CondSelect op:(Or8 x c:(Const8)) x bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Or8 x (Mul8 c (CvtBoolToUint8 bool))) +(CondSelect op:(Or(64|32|16) x c:(Const(64|32|16))) x bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Or(64|32|16) x (Mul(64|32|16) c (ZeroExt8to(64|32|16) (CvtBoolToUint8 bool)))) +// if !b { x |= c } => x |= !b * c +(CondSelect x op:(Or8 x c:(Const8)) bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Or8 x (Mul8 c (CvtBoolToUint8 (Not bool)))) +(CondSelect x op:(Or(64|32|16) x c:(Const(64|32|16))) bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Or(64|32|16) x (Mul(64|32|16) c (ZeroExt8to(64|32|16) (CvtBoolToUint8 (Not bool))))) + +// if b { x ^= c } => x ^= b * c +(CondSelect op:(Xor8 x c:(Const8)) x bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Xor8 x (Mul8 c (CvtBoolToUint8 bool))) +(CondSelect op:(Xor(64|32|16) x c:(Const(64|32|16))) x bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Xor(64|32|16) x (Mul(64|32|16) c (ZeroExt8to(64|32|16) (CvtBoolToUint8 bool)))) +// if !b { x ^= c } => x ^= !b * c +(CondSelect x op:(Xor8 x c:(Const8)) bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Xor8 x (Mul8 c (CvtBoolToUint8 (Not bool)))) +(CondSelect x op:(Xor(64|32|16) x c:(Const(64|32|16))) bool) && + rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) => + (Xor(64|32|16) x (Mul(64|32|16) c (ZeroExt8to(64|32|16) (CvtBoolToUint8 (Not bool))))) + +// bool(int(x)) => x +(Neq8 (CvtBoolToUint8 x) (Const8 [0])) => x +(Neq8 (CvtBoolToUint8 x) (Const8 [1])) => (Not x) +(Eq8 (CvtBoolToUint8 x) (Const8 [1])) => x +(Eq8 (CvtBoolToUint8 x) (Const8 [0])) => (Not x) +(Neq(64|32|16) (ZeroExt8to(64|32|16) (CvtBoolToUint8 x)) (Const(64|32|16) [0])) => x +(Neq(64|32|16) (ZeroExt8to(64|32|16) (CvtBoolToUint8 x)) (Const(64|32|16) [1])) => (Not x) +(Eq(64|32|16) (ZeroExt8to(64|32|16) (CvtBoolToUint8 x)) (Const(64|32|16) [1])) => x +(Eq(64|32|16) (ZeroExt8to(64|32|16) (CvtBoolToUint8 x)) (Const(64|32|16) [0])) => (Not x) + +// Canonicalize sext(int(bool)) => zext(int(bool)) +(SignExt8to(64|32|16) cvt:(CvtBoolToUint8 bool)) => (ZeroExt8to(64|32|16) cvt) diff --git a/src/cmd/compile/internal/ssa/_gen/genericOps.go b/src/cmd/compile/internal/ssa/_gen/genericOps.go index 1f6ad4e16d98f8..90df89eea6c339 100644 --- a/src/cmd/compile/internal/ssa/_gen/genericOps.go +++ b/src/cmd/compile/internal/ssa/_gen/genericOps.go @@ -16,6 +16,9 @@ package main // are signed or unsigned. var genericOps = []opData{ + // Pseudo-op. + {name: "Last", argLength: -1}, // return last element of tuple; for "let" bindings + // 2-input arithmetic // Types must be consistent with Go typing. Add, for example, must take two values // of the same type and produces that same type. @@ -372,6 +375,18 @@ var genericOps = []opData{ {name: "Load", argLength: 2}, // Load from arg0. arg1=memory {name: "Dereference", argLength: 2}, // Load from arg0. arg1=memory. Helper op for arg/result passing, result is an otherwise not-SSA-able "value". {name: "Store", argLength: 3, typ: "Mem", aux: "Typ"}, // Store arg1 to arg0. arg2=memory, aux=type. Returns memory. + + // masked memory operations. + // TODO add 16 and 8 + {name: "LoadMasked8", argLength: 3}, // Load from arg0, arg1 = mask of 8-bits, arg2 = memory + {name: "LoadMasked16", argLength: 3}, // Load from arg0, arg1 = mask of 16-bits, arg2 = memory + {name: "LoadMasked32", argLength: 3}, // Load from arg0, arg1 = mask of 32-bits, arg2 = memory + {name: "LoadMasked64", argLength: 3}, // Load from arg0, arg1 = mask of 64-bits, arg2 = memory + {name: "StoreMasked8", argLength: 4, typ: "Mem", aux: "Typ"}, // Store arg2 to arg0, arg1=mask of 8-bits, arg3 = memory + {name: "StoreMasked16", argLength: 4, typ: "Mem", aux: "Typ"}, // Store arg2 to arg0, arg1=mask of 16-bits, arg3 = memory + {name: "StoreMasked32", argLength: 4, typ: "Mem", aux: "Typ"}, // Store arg2 to arg0, arg1=mask of 32-bits, arg3 = memory + {name: "StoreMasked64", argLength: 4, typ: "Mem", aux: "Typ"}, // Store arg2 to arg0, arg1=mask of 64-bits, arg3 = memory + // Normally we require that the source and destination of Move do not overlap. // There is an exception when we know all the loads will happen before all // the stores. In that case, overlap is ok. See @@ -434,15 +449,17 @@ var genericOps = []opData{ // // Subsequent architecture-specific lowering only changes the opcode. - {name: "ClosureCall", argLength: -1, aux: "CallOff", call: true}, // arg0=code pointer, arg1=context ptr, arg2..argN-1 are register inputs, argN=memory. auxint=arg size. Returns Result of register results, plus memory. - {name: "StaticCall", argLength: -1, aux: "CallOff", call: true}, // call function aux.(*obj.LSym), arg0..argN-1 are register inputs, argN=memory. auxint=arg size. Returns Result of register results, plus memory. - {name: "InterCall", argLength: -1, aux: "CallOff", call: true}, // interface call. arg0=code pointer, arg1..argN-1 are register inputs, argN=memory, auxint=arg size. Returns Result of register results, plus memory. - {name: "TailCall", argLength: -1, aux: "CallOff", call: true}, // tail call function aux.(*obj.LSym), arg0..argN-1 are register inputs, argN=memory. auxint=arg size. Returns Result of register results, plus memory. + {name: "ClosureCall", argLength: -1, aux: "CallOff", call: true}, // arg0=code pointer, arg1=context ptr, arg2..argN-1 are register inputs, argN=memory. auxint=arg size. Returns Result of register results, plus memory. + {name: "StaticCall", argLength: -1, aux: "CallOff", call: true}, // call function aux.(*obj.LSym), arg0..argN-1 are register inputs, argN=memory. auxint=arg size. Returns Result of register results, plus memory. + {name: "InterCall", argLength: -1, aux: "CallOff", call: true}, // interface call. arg0=code pointer, arg1..argN-1 are register inputs, argN=memory, auxint=arg size. Returns Result of register results, plus memory. + {name: "TailCall", argLength: -1, aux: "CallOff", call: true}, // tail call function aux.(*obj.LSym), arg0..argN-1 are register inputs, argN=memory. auxint=arg size. Returns Result of register results, plus memory. + {name: "TailCallInter", argLength: -1, aux: "CallOff", call: true}, // tail call function arg0=code pointer, arg1..argN-1 are register inputs, argN=memory. auxint=arg size. Returns Result of register results, plus memory. - {name: "ClosureLECall", argLength: -1, aux: "CallOff", call: true}, // late-expanded closure call. arg0=code pointer, arg1=context ptr, arg2..argN-1 are inputs, argN is mem. auxint = arg size. Result is tuple of result(s), plus mem. - {name: "StaticLECall", argLength: -1, aux: "CallOff", call: true}, // late-expanded static call function aux.(*ssa.AuxCall.Fn). arg0..argN-1 are inputs, argN is mem. auxint = arg size. Result is tuple of result(s), plus mem. - {name: "InterLECall", argLength: -1, aux: "CallOff", call: true}, // late-expanded interface call. arg0=code pointer, arg1..argN-1 are inputs, argN is mem. auxint = arg size. Result is tuple of result(s), plus mem. - {name: "TailLECall", argLength: -1, aux: "CallOff", call: true}, // late-expanded static tail call function aux.(*ssa.AuxCall.Fn). arg0..argN-1 are inputs, argN is mem. auxint = arg size. Result is tuple of result(s), plus mem. + {name: "ClosureLECall", argLength: -1, aux: "CallOff", call: true}, // late-expanded closure call. arg0=code pointer, arg1=context ptr, arg2..argN-1 are inputs, argN is mem. auxint = arg size. Result is tuple of result(s), plus mem. + {name: "StaticLECall", argLength: -1, aux: "CallOff", call: true}, // late-expanded static call function aux.(*ssa.AuxCall.Fn). arg0..argN-1 are inputs, argN is mem. auxint = arg size. Result is tuple of result(s), plus mem. + {name: "InterLECall", argLength: -1, aux: "CallOff", call: true}, // late-expanded interface call. arg0=code pointer, arg1..argN-1 are inputs, argN is mem. auxint = arg size. Result is tuple of result(s), plus mem. + {name: "TailLECall", argLength: -1, aux: "CallOff", call: true}, // late-expanded static tail call function aux.(*ssa.AuxCall.Fn). arg0..argN-1 are inputs, argN is mem. auxint = arg size. Result is tuple of result(s), plus mem. + {name: "TailLECallInter", argLength: -1, aux: "CallOff", call: true}, // late-expanded static tail call function arg0=code pointer, arg1..argN-1 are inputs, argN is mem. auxint = arg size. Result is tuple of result(s), plus mem. // Conversions: signed extensions, zero (unsigned) extensions, truncations {name: "SignExt8to16", argLength: 1, typ: "Int16"}, @@ -522,12 +539,11 @@ var genericOps = []opData{ {name: "IData", argLength: 1}, // arg0=interface, returns data field // Structs - {name: "StructMake", argLength: -1}, // args...=field0..n-1. Returns struct with n fields. + {name: "StructMake", argLength: -1}, // args...=field0..n-1. Returns struct with n fields. Must have >0 size (use Empty otherwise). {name: "StructSelect", argLength: 1, aux: "Int64"}, // arg0=struct, auxint=field index. Returns the auxint'th field. // Arrays - {name: "ArrayMake0"}, // Returns array with 0 elements - {name: "ArrayMake1", argLength: 1}, // Returns array with 1 element + {name: "ArrayMake1", argLength: 1}, // Returns array with 1 element. Use Empty if the element is zero-sized. {name: "ArraySelect", argLength: 1, aux: "Int64"}, // arg0=array, auxint=index. Returns a[i]. // Spill&restore ops for the register allocator. These are @@ -557,8 +573,9 @@ var genericOps = []opData{ {name: "Int64Hi", argLength: 1, typ: "UInt32"}, // high 32-bit of arg0 {name: "Int64Lo", argLength: 1, typ: "UInt32"}, // low 32-bit of arg0 - {name: "Add32carry", argLength: 2, commutative: true, typ: "(UInt32,Flags)"}, // arg0 + arg1, returns (value, carry) - {name: "Add32withcarry", argLength: 3, commutative: true}, // arg0 + arg1 + arg2, arg2=carry (0 or 1) + {name: "Add32carry", argLength: 2, commutative: true, typ: "(UInt32,Flags)"}, // arg0 + arg1, returns (value, carry) + {name: "Add32withcarry", argLength: 3, commutative: true}, // arg0 + arg1 + arg2, arg2=carry (0 or 1) + {name: "Add32carrywithcarry", argLength: 3, commutative: true, typ: "(UInt32,Flags)"}, // arg0 + arg1 + arg2, arg2=carry, returns (value, carry) {name: "Sub32carry", argLength: 2, typ: "(UInt32,Flags)"}, // arg0 - arg1, returns (value, carry) {name: "Sub32withcarry", argLength: 3}, // arg0 - arg1 - arg2, arg2=carry (0 or 1) @@ -662,6 +679,54 @@ var genericOps = []opData{ // Prefetch instruction {name: "PrefetchCache", argLength: 2, hasSideEffects: true}, // Do prefetch arg0 to cache. arg0=addr, arg1=memory. {name: "PrefetchCacheStreamed", argLength: 2, hasSideEffects: true}, // Do non-temporal or streamed prefetch arg0 to cache. arg0=addr, arg1=memory. + + // Helper instruction which is semantically equivalent to calling runtime.memequal, but some targets may prefer to custom lower it later, e.g. for specific constant sizes. + {name: "MemEq", argLength: 4, commutative: true, typ: "Bool"}, // arg0=ptr0, arg1=ptr1, arg2=size, arg3=memory. + + // Value of a zero-sized type. + {name: "Empty", argLength: 0}, + + // SIMD + {name: "ZeroSIMD", argLength: 0}, // zero value of a vector + + // Convert integers to masks + {name: "Cvt16toMask8x16", argLength: 1}, // arg0 = integer mask value + {name: "Cvt32toMask8x32", argLength: 1}, // arg0 = integer mask value + {name: "Cvt64toMask8x64", argLength: 1}, // arg0 = integer mask value + {name: "Cvt8toMask16x8", argLength: 1}, // arg0 = integer mask value + {name: "Cvt16toMask16x16", argLength: 1}, // arg0 = integer mask value + {name: "Cvt32toMask16x32", argLength: 1}, // arg0 = integer mask value + {name: "Cvt8toMask32x4", argLength: 1}, // arg0 = integer mask value + {name: "Cvt8toMask32x8", argLength: 1}, // arg0 = integer mask value + {name: "Cvt16toMask32x16", argLength: 1}, // arg0 = integer mask value + {name: "Cvt8toMask64x2", argLength: 1}, // arg0 = integer mask value + {name: "Cvt8toMask64x4", argLength: 1}, // arg0 = integer mask value + {name: "Cvt8toMask64x8", argLength: 1}, // arg0 = integer mask value + + // Convert masks to integers + {name: "CvtMask8x16to16", argLength: 1}, // arg0 = mask + {name: "CvtMask8x32to32", argLength: 1}, // arg0 = mask + {name: "CvtMask8x64to64", argLength: 1}, // arg0 = mask + {name: "CvtMask16x8to8", argLength: 1}, // arg0 = mask + {name: "CvtMask16x16to16", argLength: 1}, // arg0 = mask + {name: "CvtMask16x32to32", argLength: 1}, // arg0 = mask + {name: "CvtMask32x4to8", argLength: 1}, // arg0 = mask + {name: "CvtMask32x8to8", argLength: 1}, // arg0 = mask + {name: "CvtMask32x16to16", argLength: 1}, // arg0 = mask + {name: "CvtMask64x2to8", argLength: 1}, // arg0 = mask + {name: "CvtMask64x4to8", argLength: 1}, // arg0 = mask + {name: "CvtMask64x8to8", argLength: 1}, // arg0 = mask + + // Returns true if arg0 is all zero. + {name: "IsZeroVec", argLength: 1}, + + // Returns a mask indicating whether arg0's elements are NaN. + {name: "IsNaNFloat32x4", argLength: 1}, + {name: "IsNaNFloat32x8", argLength: 1}, + {name: "IsNaNFloat32x16", argLength: 1}, + {name: "IsNaNFloat64x2", argLength: 1}, + {name: "IsNaNFloat64x4", argLength: 1}, + {name: "IsNaNFloat64x8", argLength: 1}, } // kind controls successors implicit exit @@ -689,6 +754,11 @@ var genericBlocks = []blockData{ } func init() { + genericOps = append(genericOps, simdGenericOps()...) + // When adding SIMD for another architecture, it may be useful to temporarily + // maintain a separate list of generic operations till that work stabilizes. + // For example: + // genericOps = append(genericOps, simdGenericOpsWasm()...) archs = append(archs, arch{ name: "generic", ops: genericOps, diff --git a/src/cmd/compile/internal/ssa/_gen/go.mod b/src/cmd/compile/internal/ssa/_gen/go.mod index 6f750a5618ab27..b8e6449efb2128 100644 --- a/src/cmd/compile/internal/ssa/_gen/go.mod +++ b/src/cmd/compile/internal/ssa/_gen/go.mod @@ -1,4 +1,5 @@ -module _gen +// N.B. cmd/... modules get special treatment, so avoid that prefix. +module compile/internal/ssa/_gen go 1.24 diff --git a/src/cmd/compile/internal/ssa/_gen/main.go b/src/cmd/compile/internal/ssa/_gen/main.go index 55f7dd1a1a88d3..6ca71b7e00c45d 100644 --- a/src/cmd/compile/internal/ssa/_gen/main.go +++ b/src/cmd/compile/internal/ssa/_gen/main.go @@ -32,6 +32,7 @@ type arch struct { name string pkg string // obj package to import for this arch. genfile string // source file containing opcode code generation. + genSIMDfile string // source file containing opcode code generation for SIMD. ops []opData blocks []blockData regnames []string @@ -41,6 +42,7 @@ type arch struct { fpregmask regMask fp32regmask regMask fp64regmask regMask + simdregmask regMask specialregmask regMask framepointerreg int8 linkreg int8 @@ -70,6 +72,9 @@ type opData struct { zeroWidth bool // op never translates into any machine code. example: copy, which may sometimes translate to machine code, is not zero-width. unsafePoint bool // this op is an unsafe point, i.e. not safe for async preemption fixedReg bool // this op will be assigned a fixed register + earlyOk bool // executing this op in an earlier block is ok + addrSinkArg0 bool // the address in arg0 does not propagate to the result + addrSinkArg1 bool // the address in arg1 does not propagate to the result symEffect string // effect this op has on symbol in aux scale uint8 // amd64/386 indexed load scale } @@ -95,19 +100,53 @@ type regInfo struct { outputs []regMask } -type regMask uint64 +type regMask struct { + v1, v2 uint64 +} + +func regMaskAt(i uint) regMask { + if i < 64 { + return regMask{v1: 1 << i} + } + return regMask{v2: 1 << (i - 64)} +} + +func (r regMask) empty() bool { + return r.v1 == 0 && r.v2 == 0 +} + +func (r regMask) hasReg(i uint) bool { + if i < 64 { + return (r.v1>>i)&1 != 0 + } + return (r.v2>>(i-64))&1 != 0 +} + +func (r regMask) addReg(i uint) regMask { + if i < 64 { + return regMask{r.v1 | 1<>= 1 } return buf.String() } @@ -183,7 +222,6 @@ func main() { } var wg sync.WaitGroup for _, task := range tasks { - task := task wg.Add(1) go func() { task() @@ -297,7 +335,7 @@ func genOp() { fmt.Fprintf(w, "argLen: %d,\n", v.argLength) if v.rematerializeable { - if v.reg.clobbers != 0 || v.reg.clobbersArg0 || v.reg.clobbersArg1 { + if !v.reg.clobbers.empty() || v.reg.clobbersArg0 || v.reg.clobbersArg1 { log.Fatalf("%s is rematerializeable and clobbers registers", v.name) } if v.clobberFlags { @@ -339,13 +377,13 @@ func genOp() { } if v.faultOnNilArg0 { fmt.Fprintln(w, "faultOnNilArg0: true,") - if v.aux != "Sym" && v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "Int32" && v.aux != "" { + if v.aux != "Sym" && v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "Int32" && v.aux != "SizeAndAlign" && v.aux != "" { log.Fatalf("faultOnNilArg0 with aux %s not allowed", v.aux) } } if v.faultOnNilArg1 { fmt.Fprintln(w, "faultOnNilArg1: true,") - if v.aux != "Sym" && v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "Int32" && v.aux != "" { + if v.aux != "Sym" && v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "Int32" && v.aux != "SizeAndAlign" && v.aux != "" { log.Fatalf("faultOnNilArg1 with aux %s not allowed", v.aux) } } @@ -358,6 +396,15 @@ func genOp() { if v.fixedReg { fmt.Fprintln(w, "fixedReg: true,") } + if v.earlyOk { + fmt.Fprintln(w, "earlyOk: true,") + } + if v.addrSinkArg0 { + fmt.Fprintln(w, "addrSinkArg0: true,") + } + if v.addrSinkArg1 { + fmt.Fprintln(w, "addrSinkArg1: true,") + } if v.unsafePoint { fmt.Fprintln(w, "unsafePoint: true,") } @@ -389,7 +436,7 @@ func genOp() { // that we will always be able to find a register. var s []intPair for i, r := range v.reg.inputs { - if r != 0 { + if !r.empty() { s = append(s, intPair{countRegs(r), i}) } } @@ -398,13 +445,13 @@ func genOp() { fmt.Fprintln(w, "inputs: []inputInfo{") for _, p := range s { r := v.reg.inputs[p.val] - fmt.Fprintf(w, "{%d,%d},%s\n", p.val, r, a.regMaskComment(r)) + fmt.Fprintf(w, "{%d,regMask{v1: %d, v2: %d}},%s\n", p.val, r.v1, r.v2, a.regMaskComment(r)) } fmt.Fprintln(w, "},") } - if v.reg.clobbers > 0 { - fmt.Fprintf(w, "clobbers: %d,%s\n", v.reg.clobbers, a.regMaskComment(v.reg.clobbers)) + if !v.reg.clobbers.empty() { + fmt.Fprintf(w, "clobbers: regMask{v1: %d, v2: %d},%s\n", v.reg.clobbers.v1, v.reg.clobbers.v2, a.regMaskComment(v.reg.clobbers)) } if v.reg.clobbersArg0 { fmt.Fprintf(w, "clobbersArg0: true,\n") @@ -423,7 +470,7 @@ func genOp() { fmt.Fprintln(w, "outputs: []outputInfo{") for _, p := range s { r := v.reg.outputs[p.val] - fmt.Fprintf(w, "{%d,%d},%s\n", p.val, r, a.regMaskComment(r)) + fmt.Fprintf(w, "{%d,regMask{v1: %d, v2: %d}},%s\n", p.val, r.v1, r.v2, a.regMaskComment(r)) } fmt.Fprintln(w, "},") } @@ -500,15 +547,18 @@ func genOp() { fmt.Fprintln(w, "}") fmt.Fprintf(w, "var paramIntReg%s = %#v\n", a.name, paramIntRegs) fmt.Fprintf(w, "var paramFloatReg%s = %#v\n", a.name, paramFloatRegs) - fmt.Fprintf(w, "var gpRegMask%s = regMask(%d)\n", a.name, a.gpregmask) - fmt.Fprintf(w, "var fpRegMask%s = regMask(%d)\n", a.name, a.fpregmask) - if a.fp32regmask != 0 { - fmt.Fprintf(w, "var fp32RegMask%s = regMask(%d)\n", a.name, a.fp32regmask) + fmt.Fprintf(w, "var gpRegMask%s = regMask{v1: %d, v2: %d}\n", a.name, a.gpregmask.v1, a.gpregmask.v2) + fmt.Fprintf(w, "var fpRegMask%s = regMask{v1: %d, v2: %d}\n", a.name, a.fpregmask.v1, a.fpregmask.v2) + if !a.fp32regmask.empty() { + fmt.Fprintf(w, "var fp32RegMask%s = regMask{v1: %d, v2: %d}\n", a.name, a.fp32regmask.v1, a.fp32regmask.v2) + } + if !a.fp64regmask.empty() { + fmt.Fprintf(w, "var fp64RegMask%s = regMask{v1: %d, v2: %d}\n", a.name, a.fp64regmask.v1, a.fp64regmask.v2) } - if a.fp64regmask != 0 { - fmt.Fprintf(w, "var fp64RegMask%s = regMask(%d)\n", a.name, a.fp64regmask) + if !a.simdregmask.empty() { + fmt.Fprintf(w, "var simdRegMask%s = regMask{v1: %d, v2: %d}\n", a.name, a.simdregmask.v1, a.simdregmask.v2) } - fmt.Fprintf(w, "var specialRegMask%s = regMask(%d)\n", a.name, a.specialregmask) + fmt.Fprintf(w, "var specialRegMask%s = regMask{v1: %d, v2: %d}\n", a.name, a.specialregmask.v1, a.specialregmask.v2) fmt.Fprintf(w, "var framepointerReg%s = int8(%d)\n", a.name, a.framepointerreg) fmt.Fprintf(w, "var linkReg%s = int8(%d)\n", a.name, a.linkreg) } @@ -547,6 +597,15 @@ func genOp() { if err != nil { log.Fatalf("can't read %s: %v", a.genfile, err) } + // Append the file of simd operations, too + if a.genSIMDfile != "" { + simdSrc, err := os.ReadFile(a.genSIMDfile) + if err != nil { + log.Fatalf("can't read %s: %v", a.genSIMDfile, err) + } + src = append(src, simdSrc...) + } + seen := make(map[string]bool, len(a.ops)) for _, m := range rxOp.FindAllSubmatch(src, -1) { seen[string(m[1])] = true @@ -570,7 +629,7 @@ func (a arch) Name() string { // countRegs returns the number of set bits in the register mask. func countRegs(r regMask) int { - return bits.OnesCount64(uint64(r)) + return bits.OnesCount64(r.v1) + bits.OnesCount64(r.v2) } // for sorting a pair of integers by key diff --git a/src/cmd/compile/internal/ssa/_gen/multiscanner.go b/src/cmd/compile/internal/ssa/_gen/multiscanner.go new file mode 100644 index 00000000000000..1c7520cadef9b8 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/multiscanner.go @@ -0,0 +1,117 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import ( + "bufio" + "io" +) + +// NamedScanner is a simple struct to pair a name with a Scanner. +type NamedScanner struct { + Name string + Scanner *bufio.Scanner +} + +// NamedReader is a simple struct to pair a name with a Reader, +// which will be converted to a Scanner using bufio.NewScanner. +type NamedReader struct { + Name string + Reader io.Reader +} + +// MultiScanner scans over multiple bufio.Scanners as if they were a single stream. +// It also keeps track of the name of the current scanner and the line number. +type MultiScanner struct { + scanners []NamedScanner + scannerIdx int + line int + totalLine int + err error +} + +// NewMultiScanner creates a new MultiScanner from slice of NamedScanners. +func NewMultiScanner(scanners []NamedScanner) *MultiScanner { + return &MultiScanner{ + scanners: scanners, + scannerIdx: -1, // Start before the first scanner + } +} + +// MultiScannerFromReaders creates a new MultiScanner from a slice of NamedReaders. +func MultiScannerFromReaders(readers []NamedReader) *MultiScanner { + var scanners []NamedScanner + for _, r := range readers { + scanners = append(scanners, NamedScanner{ + Name: r.Name, + Scanner: bufio.NewScanner(r.Reader), + }) + } + return NewMultiScanner(scanners) +} + +// Scan advances the scanner to the next token, which will then be +// available through the Text method. It returns false when the scan stops, +// either by reaching the end of the input or an error. +// After Scan returns false, the Err method will return any error that +// occurred during scanning, except that if it was io.EOF, Err +// will return nil. +func (ms *MultiScanner) Scan() bool { + if ms.scannerIdx == -1 { + ms.scannerIdx = 0 + } + + for ms.scannerIdx < len(ms.scanners) { + current := ms.scanners[ms.scannerIdx] + if current.Scanner.Scan() { + ms.line++ + ms.totalLine++ + return true + } + if err := current.Scanner.Err(); err != nil { + ms.err = err + return false + } + // Move to the next scanner + ms.scannerIdx++ + ms.line = 0 + } + + return false +} + +// Text returns the most recent token generated by a call to Scan. +func (ms *MultiScanner) Text() string { + if ms.scannerIdx < 0 || ms.scannerIdx >= len(ms.scanners) { + return "" + } + return ms.scanners[ms.scannerIdx].Scanner.Text() +} + +// Err returns the first non-EOF error that was encountered by the MultiScanner. +func (ms *MultiScanner) Err() error { + return ms.err +} + +// Name returns the name of the current scanner. +func (ms *MultiScanner) Name() string { + if ms.scannerIdx < 0 { + return "" + } + if ms.scannerIdx >= len(ms.scanners) { + return "" + } + return ms.scanners[ms.scannerIdx].Name +} + +// Line returns the current line number within the current scanner. +func (ms *MultiScanner) Line() int { + return ms.line +} + +// TotalLine returns the total number of lines scanned across all scanners. +func (ms *MultiScanner) TotalLine() int { + return ms.totalLine +} diff --git a/src/cmd/compile/internal/ssa/_gen/rulegen.go b/src/cmd/compile/internal/ssa/_gen/rulegen.go index f818b46511d04a..d9e96b61f58537 100644 --- a/src/cmd/compile/internal/ssa/_gen/rulegen.go +++ b/src/cmd/compile/internal/ssa/_gen/rulegen.go @@ -94,8 +94,11 @@ func genSplitLoadRules(arch arch) { genRulesSuffix(arch, "splitload") } func genLateLowerRules(arch arch) { genRulesSuffix(arch, "latelower") } func genRulesSuffix(arch arch, suff string) { + var readers []NamedReader // Open input file. - text, err := os.Open(arch.name + suff + ".rules") + var text io.Reader + name := arch.name + suff + ".rules" + text, err := os.Open(name) if err != nil { if suff == "" { // All architectures must have a plain rules file. @@ -104,18 +107,28 @@ func genRulesSuffix(arch arch, suff string) { // Some architectures have bonus rules files that others don't share. That's fine. return } + readers = append(readers, NamedReader{name, text}) + + // Check for file of SIMD rules to add + if suff == "" { + simdname := "simd" + arch.name + ".rules" + simdtext, err := os.Open(simdname) + if err == nil { + readers = append(readers, NamedReader{simdname, simdtext}) + } + } // oprules contains a list of rules for each block and opcode blockrules := map[string][]Rule{} oprules := map[string][]Rule{} // read rule file - scanner := bufio.NewScanner(text) + scanner := MultiScannerFromReaders(readers) rule := "" var lineno int var ruleLineno int // line number of "=>" for scanner.Scan() { - lineno++ + lineno = scanner.Line() line := scanner.Text() if i := strings.Index(line, "//"); i >= 0 { // Remove comments. Note that this isn't string safe, so @@ -142,7 +155,7 @@ func genRulesSuffix(arch arch, suff string) { break // continuing the line can't help, and it will only make errors worse } - loc := fmt.Sprintf("%s%s.rules:%d", arch.name, suff, ruleLineno) + loc := fmt.Sprintf("%s:%d", scanner.Name(), ruleLineno) for _, rule2 := range expandOr(rule) { r := Rule{Rule: rule2, Loc: loc} if rawop := strings.Split(rule2, " ")[0][1:]; isBlock(rawop, arch) { @@ -162,7 +175,7 @@ func genRulesSuffix(arch arch, suff string) { log.Fatalf("scanner failed: %v\n", err) } if balance(rule) != 0 { - log.Fatalf("%s.rules:%d: unbalanced rule: %v\n", arch.name, lineno, rule) + log.Fatalf("%s:%d: unbalanced rule: %v\n", scanner.Name(), lineno, rule) } // Order all the ops. @@ -276,7 +289,7 @@ func genRulesSuffix(arch arch, suff string) { buf := new(bytes.Buffer) fprint(buf, genFile) fset := token.NewFileSet() - file, err := parser.ParseFile(fset, "", buf, parser.ParseComments) + file, err := parser.ParseFile(fset, "", buf, parser.ParseComments|parser.SkipObjectResolution) if err != nil { filename := fmt.Sprintf("%s_broken.go", arch.name) if err := os.WriteFile(filename, buf.Bytes(), 0644); err != nil { @@ -828,7 +841,7 @@ func exprf(format string, a ...interface{}) ast.Expr { func stmtf(format string, a ...interface{}) Statement { src := fmt.Sprintf(format, a...) fsrc := "package p\nfunc _() {\n" + src + "\n}\n" - file, err := parser.ParseFile(token.NewFileSet(), "", fsrc, 0) + file, err := parser.ParseFile(token.NewFileSet(), "", fsrc, parser.SkipObjectResolution) if err != nil { log.Fatalf("stmt parse error on %q: %v", src, err) } @@ -862,7 +875,7 @@ func declReserved(name, value string) *Declare { if !reservedNames[name] { panic(fmt.Sprintf("declReserved call does not use a reserved name: %q", name)) } - return &Declare{name, exprf(value)} + return &Declare{name, exprf("%s", value)} } // breakf constructs a simple "if cond { break }" statement, using exprf for its @@ -889,7 +902,7 @@ func genBlockRewrite(rule Rule, arch arch, data blockData) *RuleRewrite { if vname == "" { vname = fmt.Sprintf("v_%v", i) } - rr.add(declf(rr.Loc, vname, cname)) + rr.add(declf(rr.Loc, vname, "%s", cname)) p, op := genMatch0(rr, arch, expr, vname, nil, false) // TODO: pass non-nil cnt? if op != "" { check := fmt.Sprintf("%s.Op == %s", cname, op) @@ -904,7 +917,7 @@ func genBlockRewrite(rule Rule, arch arch, data blockData) *RuleRewrite { } pos[i] = p } else { - rr.add(declf(rr.Loc, arg, cname)) + rr.add(declf(rr.Loc, arg, "%s", cname)) pos[i] = arg + ".Pos" } } @@ -1271,8 +1284,10 @@ func genResult0(rr *RuleRewrite, arch arch, result string, top, move bool, pos s case 0: case 1: rr.add(stmtf("%s.AddArg(%s)", v, all.String())) - default: + case 2, 3, 4, 5, 6: rr.add(stmtf("%s.AddArg%d(%s)", v, len(args), all.String())) + default: + rr.add(stmtf("%s.AddArgs(%s)", v, all.String())) } if cse != nil { @@ -1313,6 +1328,12 @@ outer: d++ case d > 0 && s[i] == close: d-- + case s[i] == ':': + // ignore spaces after colons + nonsp = true + for i+1 < len(s) && (s[i+1] == ' ' || s[i+1] == '\t') { + i++ + } default: nonsp = true } @@ -1347,7 +1368,7 @@ func extract(val string) (op, typ, auxint, aux string, args []string) { val = val[1 : len(val)-1] // remove () // Split val up into regions. - // Split by spaces/tabs, except those contained in (), {}, [], or <>. + // Split by spaces/tabs, except those contained in (), {}, [], or <> or after colon. s := split(val) // Extract restrictions and args. @@ -1439,7 +1460,7 @@ func opHasAuxInt(op opData) bool { switch op.aux { case "Bool", "Int8", "Int16", "Int32", "Int64", "Int128", "UInt8", "Float32", "Float64", "SymOff", "CallOff", "SymValAndOff", "TypSize", "ARM64BitField", "FlagConstant", "CCop", - "PanicBoundsC", "PanicBoundsCC", "ARM64ConditionalParams": + "PanicBoundsC", "PanicBoundsCC", "ARM64ConditionalParams", "SizeAndAlign": return true } return false @@ -1448,7 +1469,7 @@ func opHasAuxInt(op opData) bool { func opHasAux(op opData) bool { switch op.aux { case "String", "Sym", "SymOff", "Call", "CallOff", "SymValAndOff", "Typ", "TypSize", - "S390XCCMask", "S390XRotateParams", "PanicBoundsC", "PanicBoundsCC": + "S390XCCMask", "S390XRotateParams", "PanicBoundsC", "PanicBoundsCC", "SizeAndAlign": return true } return false @@ -1471,7 +1492,7 @@ func splitNameExpr(arg string) (name, expr string) { // colon is inside the parens, such as in "(Foo x:(Bar))". return "", arg } - return arg[:colon], arg[colon+1:] + return arg[:colon], strings.TrimSpace(arg[colon+1:]) } func getBlockInfo(op string, arch arch) (name string, data blockData) { @@ -1807,6 +1828,8 @@ func (op opData) auxType() string { return "PanicBoundsC" case "PanicBoundsCC": return "PanicBoundsCC" + case "SizeAndAlign": + return "int64" default: return "invalid" } @@ -1851,6 +1874,8 @@ func (op opData) auxIntType() string { return "arm64ConditionalParams" case "PanicBoundsC", "PanicBoundsCC": return "int64" + case "SizeAndAlign": + return "int64" default: return "invalid" } diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules new file mode 100644 index 00000000000000..4d9a3d3dd4d51c --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules @@ -0,0 +1,3621 @@ +// Code generated by 'simdgen -o godefs -goroot $GOROOT -arch amd64 -xedPath $XED_PATH go_amd64.yaml types.yaml categories.yaml'; DO NOT EDIT. + +(AESDecryptLastRoundUint8x16 ...) => (VAESDECLAST128 ...) // pureVreg +(AESDecryptLastRoundUint8x32 ...) => (VAESDECLAST256 ...) // pureVreg +(AESDecryptLastRoundUint8x64 ...) => (VAESDECLAST512 ...) // pureVreg +(AESDecryptOneRoundUint8x16 ...) => (VAESDEC128 ...) // pureVreg +(AESDecryptOneRoundUint8x32 ...) => (VAESDEC256 ...) // pureVreg +(AESDecryptOneRoundUint8x64 ...) => (VAESDEC512 ...) // pureVreg +(AESEncryptLastRoundUint8x16 ...) => (VAESENCLAST128 ...) // pureVreg +(AESEncryptLastRoundUint8x32 ...) => (VAESENCLAST256 ...) // pureVreg +(AESEncryptLastRoundUint8x64 ...) => (VAESENCLAST512 ...) // pureVreg +(AESEncryptOneRoundUint8x16 ...) => (VAESENC128 ...) // pureVreg +(AESEncryptOneRoundUint8x32 ...) => (VAESENC256 ...) // pureVreg +(AESEncryptOneRoundUint8x64 ...) => (VAESENC512 ...) // pureVreg +(AESInvMixColumnsUint32x4 ...) => (VAESIMC128 ...) // pureVreg +(AESRoundKeyGenAssistUint32x4 ...) => (VAESKEYGENASSIST128 ...) // pureVreg +(AbsInt8x16 ...) => (VPABSB128 ...) // pureVreg +(AbsInt8x32 ...) => (VPABSB256 ...) // pureVreg +(AbsInt8x64 ...) => (VPABSB512 ...) // pureVreg +(AbsInt16x8 ...) => (VPABSW128 ...) // pureVreg +(AbsInt16x16 ...) => (VPABSW256 ...) // pureVreg +(AbsInt16x32 ...) => (VPABSW512 ...) // pureVreg +(AbsInt32x4 ...) => (VPABSD128 ...) // pureVreg +(AbsInt32x8 ...) => (VPABSD256 ...) // pureVreg +(AbsInt32x16 ...) => (VPABSD512 ...) // pureVreg +(AbsInt64x2 ...) => (VPABSQ128 ...) // pureVreg +(AbsInt64x4 ...) => (VPABSQ256 ...) // pureVreg +(AbsInt64x8 ...) => (VPABSQ512 ...) // pureVreg +(AddFloat32x4 ...) => (VADDPS128 ...) // pureVreg +(AddFloat32x8 ...) => (VADDPS256 ...) // pureVreg +(AddFloat32x16 ...) => (VADDPS512 ...) // pureVreg +(AddFloat64x2 ...) => (VADDPD128 ...) // pureVreg +(AddFloat64x4 ...) => (VADDPD256 ...) // pureVreg +(AddFloat64x8 ...) => (VADDPD512 ...) // pureVreg +(AddInt8x16 ...) => (VPADDB128 ...) // pureVreg +(AddInt8x32 ...) => (VPADDB256 ...) // pureVreg +(AddInt8x64 ...) => (VPADDB512 ...) // pureVreg +(AddInt16x8 ...) => (VPADDW128 ...) // pureVreg +(AddInt16x16 ...) => (VPADDW256 ...) // pureVreg +(AddInt16x32 ...) => (VPADDW512 ...) // pureVreg +(AddInt32x4 ...) => (VPADDD128 ...) // pureVreg +(AddInt32x8 ...) => (VPADDD256 ...) // pureVreg +(AddInt32x16 ...) => (VPADDD512 ...) // pureVreg +(AddInt64x2 ...) => (VPADDQ128 ...) // pureVreg +(AddInt64x4 ...) => (VPADDQ256 ...) // pureVreg +(AddInt64x8 ...) => (VPADDQ512 ...) // pureVreg +(AddUint8x16 ...) => (VPADDB128 ...) // pureVreg +(AddUint8x32 ...) => (VPADDB256 ...) // pureVreg +(AddUint8x64 ...) => (VPADDB512 ...) // pureVreg +(AddUint16x8 ...) => (VPADDW128 ...) // pureVreg +(AddUint16x16 ...) => (VPADDW256 ...) // pureVreg +(AddUint16x32 ...) => (VPADDW512 ...) // pureVreg +(AddUint32x4 ...) => (VPADDD128 ...) // pureVreg +(AddUint32x8 ...) => (VPADDD256 ...) // pureVreg +(AddUint32x16 ...) => (VPADDD512 ...) // pureVreg +(AddUint64x2 ...) => (VPADDQ128 ...) // pureVreg +(AddUint64x4 ...) => (VPADDQ256 ...) // pureVreg +(AddUint64x8 ...) => (VPADDQ512 ...) // pureVreg +(AddOddSubEvenFloat32x4 ...) => (VADDSUBPS128 ...) // pureVreg +(AddOddSubEvenFloat32x8 ...) => (VADDSUBPS256 ...) // pureVreg +(AddOddSubEvenFloat64x2 ...) => (VADDSUBPD128 ...) // pureVreg +(AddOddSubEvenFloat64x4 ...) => (VADDSUBPD256 ...) // pureVreg +(AddSaturatedInt8x16 ...) => (VPADDSB128 ...) // pureVreg +(AddSaturatedInt8x32 ...) => (VPADDSB256 ...) // pureVreg +(AddSaturatedInt8x64 ...) => (VPADDSB512 ...) // pureVreg +(AddSaturatedInt16x8 ...) => (VPADDSW128 ...) // pureVreg +(AddSaturatedInt16x16 ...) => (VPADDSW256 ...) // pureVreg +(AddSaturatedInt16x32 ...) => (VPADDSW512 ...) // pureVreg +(AddSaturatedUint8x16 ...) => (VPADDUSB128 ...) // pureVreg +(AddSaturatedUint8x32 ...) => (VPADDUSB256 ...) // pureVreg +(AddSaturatedUint8x64 ...) => (VPADDUSB512 ...) // pureVreg +(AddSaturatedUint16x8 ...) => (VPADDUSW128 ...) // pureVreg +(AddSaturatedUint16x16 ...) => (VPADDUSW256 ...) // pureVreg +(AddSaturatedUint16x32 ...) => (VPADDUSW512 ...) // pureVreg +(AndInt8x16 ...) => (VPAND128 ...) // pureVreg +(AndInt8x32 ...) => (VPAND256 ...) // pureVreg +(AndInt8x64 ...) => (VPANDD512 ...) // pureVreg +(AndInt16x8 ...) => (VPAND128 ...) // pureVreg +(AndInt16x16 ...) => (VPAND256 ...) // pureVreg +(AndInt16x32 ...) => (VPANDD512 ...) // pureVreg +(AndInt32x4 ...) => (VPAND128 ...) // pureVreg +(AndInt32x8 ...) => (VPAND256 ...) // pureVreg +(AndInt32x16 ...) => (VPANDD512 ...) // pureVreg +(AndInt64x2 ...) => (VPAND128 ...) // pureVreg +(AndInt64x4 ...) => (VPAND256 ...) // pureVreg +(AndInt64x8 ...) => (VPANDQ512 ...) // pureVreg +(AndUint8x16 ...) => (VPAND128 ...) // pureVreg +(AndUint8x32 ...) => (VPAND256 ...) // pureVreg +(AndUint8x64 ...) => (VPANDD512 ...) // pureVreg +(AndUint16x8 ...) => (VPAND128 ...) // pureVreg +(AndUint16x16 ...) => (VPAND256 ...) // pureVreg +(AndUint16x32 ...) => (VPANDD512 ...) // pureVreg +(AndUint32x4 ...) => (VPAND128 ...) // pureVreg +(AndUint32x8 ...) => (VPAND256 ...) // pureVreg +(AndUint32x16 ...) => (VPANDD512 ...) // pureVreg +(AndUint64x2 ...) => (VPAND128 ...) // pureVreg +(AndUint64x4 ...) => (VPAND256 ...) // pureVreg +(AndUint64x8 ...) => (VPANDQ512 ...) // pureVreg +(AndNotInt8x16 ...) => (VPANDN128 ...) // pureVreg +(AndNotInt8x32 ...) => (VPANDN256 ...) // pureVreg +(AndNotInt8x64 ...) => (VPANDND512 ...) // pureVreg +(AndNotInt16x8 ...) => (VPANDN128 ...) // pureVreg +(AndNotInt16x16 ...) => (VPANDN256 ...) // pureVreg +(AndNotInt16x32 ...) => (VPANDND512 ...) // pureVreg +(AndNotInt32x4 ...) => (VPANDN128 ...) // pureVreg +(AndNotInt32x8 ...) => (VPANDN256 ...) // pureVreg +(AndNotInt32x16 ...) => (VPANDND512 ...) // pureVreg +(AndNotInt64x2 ...) => (VPANDN128 ...) // pureVreg +(AndNotInt64x4 ...) => (VPANDN256 ...) // pureVreg +(AndNotInt64x8 ...) => (VPANDNQ512 ...) // pureVreg +(AndNotUint8x16 ...) => (VPANDN128 ...) // pureVreg +(AndNotUint8x32 ...) => (VPANDN256 ...) // pureVreg +(AndNotUint8x64 ...) => (VPANDND512 ...) // pureVreg +(AndNotUint16x8 ...) => (VPANDN128 ...) // pureVreg +(AndNotUint16x16 ...) => (VPANDN256 ...) // pureVreg +(AndNotUint16x32 ...) => (VPANDND512 ...) // pureVreg +(AndNotUint32x4 ...) => (VPANDN128 ...) // pureVreg +(AndNotUint32x8 ...) => (VPANDN256 ...) // pureVreg +(AndNotUint32x16 ...) => (VPANDND512 ...) // pureVreg +(AndNotUint64x2 ...) => (VPANDN128 ...) // pureVreg +(AndNotUint64x4 ...) => (VPANDN256 ...) // pureVreg +(AndNotUint64x8 ...) => (VPANDNQ512 ...) // pureVreg +(AverageUint8x16 ...) => (VPAVGB128 ...) // pureVreg +(AverageUint8x32 ...) => (VPAVGB256 ...) // pureVreg +(AverageUint8x64 ...) => (VPAVGB512 ...) // pureVreg +(AverageUint16x8 ...) => (VPAVGW128 ...) // pureVreg +(AverageUint16x16 ...) => (VPAVGW256 ...) // pureVreg +(AverageUint16x32 ...) => (VPAVGW512 ...) // pureVreg +(CeilFloat32x4 x) => (VROUNDPS128 [2] x) // pureVreg +(CeilFloat32x8 x) => (VROUNDPS256 [2] x) // pureVreg +(CeilFloat64x2 x) => (VROUNDPD128 [2] x) // pureVreg +(CeilFloat64x4 x) => (VROUNDPD256 [2] x) // pureVreg +(CeilScaledFloat32x4 [a] x) => (VRNDSCALEPS128 [a+2] x) // pureVreg +(CeilScaledFloat32x8 [a] x) => (VRNDSCALEPS256 [a+2] x) // pureVreg +(CeilScaledFloat32x16 [a] x) => (VRNDSCALEPS512 [a+2] x) // pureVreg +(CeilScaledFloat64x2 [a] x) => (VRNDSCALEPD128 [a+2] x) // pureVreg +(CeilScaledFloat64x4 [a] x) => (VRNDSCALEPD256 [a+2] x) // pureVreg +(CeilScaledFloat64x8 [a] x) => (VRNDSCALEPD512 [a+2] x) // pureVreg +(CeilScaledResidueFloat32x4 [a] x) => (VREDUCEPS128 [a+2] x) // pureVreg +(CeilScaledResidueFloat32x8 [a] x) => (VREDUCEPS256 [a+2] x) // pureVreg +(CeilScaledResidueFloat32x16 [a] x) => (VREDUCEPS512 [a+2] x) // pureVreg +(CeilScaledResidueFloat64x2 [a] x) => (VREDUCEPD128 [a+2] x) // pureVreg +(CeilScaledResidueFloat64x4 [a] x) => (VREDUCEPD256 [a+2] x) // pureVreg +(CeilScaledResidueFloat64x8 [a] x) => (VREDUCEPD512 [a+2] x) // pureVreg +(CompressFloat32x4 x mask) => (VCOMPRESSPSMasked128 x (VPMOVVec32x4ToM mask)) // maskIn +(CompressFloat32x8 x mask) => (VCOMPRESSPSMasked256 x (VPMOVVec32x8ToM mask)) // maskIn +(CompressFloat32x16 x mask) => (VCOMPRESSPSMasked512 x (VPMOVVec32x16ToM mask)) // maskIn +(CompressFloat64x2 x mask) => (VCOMPRESSPDMasked128 x (VPMOVVec64x2ToM mask)) // maskIn +(CompressFloat64x4 x mask) => (VCOMPRESSPDMasked256 x (VPMOVVec64x4ToM mask)) // maskIn +(CompressFloat64x8 x mask) => (VCOMPRESSPDMasked512 x (VPMOVVec64x8ToM mask)) // maskIn +(CompressInt8x16 x mask) => (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM mask)) // maskIn +(CompressInt8x32 x mask) => (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM mask)) // maskIn +(CompressInt8x64 x mask) => (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM mask)) // maskIn +(CompressInt16x8 x mask) => (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM mask)) // maskIn +(CompressInt16x16 x mask) => (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM mask)) // maskIn +(CompressInt16x32 x mask) => (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM mask)) // maskIn +(CompressInt32x4 x mask) => (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM mask)) // maskIn +(CompressInt32x8 x mask) => (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM mask)) // maskIn +(CompressInt32x16 x mask) => (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM mask)) // maskIn +(CompressInt64x2 x mask) => (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM mask)) // maskIn +(CompressInt64x4 x mask) => (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM mask)) // maskIn +(CompressInt64x8 x mask) => (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM mask)) // maskIn +(CompressUint8x16 x mask) => (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM mask)) // maskIn +(CompressUint8x32 x mask) => (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM mask)) // maskIn +(CompressUint8x64 x mask) => (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM mask)) // maskIn +(CompressUint16x8 x mask) => (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM mask)) // maskIn +(CompressUint16x16 x mask) => (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM mask)) // maskIn +(CompressUint16x32 x mask) => (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM mask)) // maskIn +(CompressUint32x4 x mask) => (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM mask)) // maskIn +(CompressUint32x8 x mask) => (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM mask)) // maskIn +(CompressUint32x16 x mask) => (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM mask)) // maskIn +(CompressUint64x2 x mask) => (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM mask)) // maskIn +(CompressUint64x4 x mask) => (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM mask)) // maskIn +(CompressUint64x8 x mask) => (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM mask)) // maskIn +(ConcatAddPairsFloat32x4 ...) => (VHADDPS128 ...) // pureVreg +(ConcatAddPairsFloat64x2 ...) => (VHADDPD128 ...) // pureVreg +(ConcatAddPairsInt16x8 ...) => (VPHADDW128 ...) // pureVreg +(ConcatAddPairsInt32x4 ...) => (VPHADDD128 ...) // pureVreg +(ConcatAddPairsUint16x8 ...) => (VPHADDW128 ...) // pureVreg +(ConcatAddPairsUint32x4 ...) => (VPHADDD128 ...) // pureVreg +(ConcatAddPairsGroupedFloat32x8 ...) => (VHADDPS256 ...) // pureVreg +(ConcatAddPairsGroupedFloat64x4 ...) => (VHADDPD256 ...) // pureVreg +(ConcatAddPairsGroupedInt16x16 ...) => (VPHADDW256 ...) // pureVreg +(ConcatAddPairsGroupedInt32x8 ...) => (VPHADDD256 ...) // pureVreg +(ConcatAddPairsGroupedUint16x16 ...) => (VPHADDW256 ...) // pureVreg +(ConcatAddPairsGroupedUint32x8 ...) => (VPHADDD256 ...) // pureVreg +(ConcatAddPairsSaturatedInt16x8 ...) => (VPHADDSW128 ...) // pureVreg +(ConcatAddPairsSaturatedGroupedInt16x16 ...) => (VPHADDSW256 ...) // pureVreg +(ConcatPermuteFloat32x4 ...) => (VPERMI2PS128 ...) // pureVreg +(ConcatPermuteFloat32x8 ...) => (VPERMI2PS256 ...) // pureVreg +(ConcatPermuteFloat32x16 ...) => (VPERMI2PS512 ...) // pureVreg +(ConcatPermuteFloat64x2 ...) => (VPERMI2PD128 ...) // pureVreg +(ConcatPermuteFloat64x4 ...) => (VPERMI2PD256 ...) // pureVreg +(ConcatPermuteFloat64x8 ...) => (VPERMI2PD512 ...) // pureVreg +(ConcatPermuteInt8x16 ...) => (VPERMI2B128 ...) // pureVreg +(ConcatPermuteInt8x32 ...) => (VPERMI2B256 ...) // pureVreg +(ConcatPermuteInt8x64 ...) => (VPERMI2B512 ...) // pureVreg +(ConcatPermuteInt16x8 ...) => (VPERMI2W128 ...) // pureVreg +(ConcatPermuteInt16x16 ...) => (VPERMI2W256 ...) // pureVreg +(ConcatPermuteInt16x32 ...) => (VPERMI2W512 ...) // pureVreg +(ConcatPermuteInt32x4 ...) => (VPERMI2D128 ...) // pureVreg +(ConcatPermuteInt32x8 ...) => (VPERMI2D256 ...) // pureVreg +(ConcatPermuteInt32x16 ...) => (VPERMI2D512 ...) // pureVreg +(ConcatPermuteInt64x2 ...) => (VPERMI2Q128 ...) // pureVreg +(ConcatPermuteInt64x4 ...) => (VPERMI2Q256 ...) // pureVreg +(ConcatPermuteInt64x8 ...) => (VPERMI2Q512 ...) // pureVreg +(ConcatPermuteUint8x16 ...) => (VPERMI2B128 ...) // pureVreg +(ConcatPermuteUint8x32 ...) => (VPERMI2B256 ...) // pureVreg +(ConcatPermuteUint8x64 ...) => (VPERMI2B512 ...) // pureVreg +(ConcatPermuteUint16x8 ...) => (VPERMI2W128 ...) // pureVreg +(ConcatPermuteUint16x16 ...) => (VPERMI2W256 ...) // pureVreg +(ConcatPermuteUint16x32 ...) => (VPERMI2W512 ...) // pureVreg +(ConcatPermuteUint32x4 ...) => (VPERMI2D128 ...) // pureVreg +(ConcatPermuteUint32x8 ...) => (VPERMI2D256 ...) // pureVreg +(ConcatPermuteUint32x16 ...) => (VPERMI2D512 ...) // pureVreg +(ConcatPermuteUint64x2 ...) => (VPERMI2Q128 ...) // pureVreg +(ConcatPermuteUint64x4 ...) => (VPERMI2Q256 ...) // pureVreg +(ConcatPermuteUint64x8 ...) => (VPERMI2Q512 ...) // pureVreg +(ConcatPermute128ScalarsFloat32x8 ...) => (VPERM2F128256 ...) // pureVreg +(ConcatPermute128ScalarsFloat64x4 ...) => (VPERM2F128256 ...) // pureVreg +(ConcatPermute128ScalarsInt8x32 ...) => (VPERM2I128256 ...) // pureVreg +(ConcatPermute128ScalarsInt16x16 ...) => (VPERM2I128256 ...) // pureVreg +(ConcatPermute128ScalarsInt32x8 ...) => (VPERM2I128256 ...) // pureVreg +(ConcatPermute128ScalarsInt64x4 ...) => (VPERM2I128256 ...) // pureVreg +(ConcatPermute128ScalarsUint8x32 ...) => (VPERM2I128256 ...) // pureVreg +(ConcatPermute128ScalarsUint16x16 ...) => (VPERM2I128256 ...) // pureVreg +(ConcatPermute128ScalarsUint32x8 ...) => (VPERM2I128256 ...) // pureVreg +(ConcatPermute128ScalarsUint64x4 ...) => (VPERM2I128256 ...) // pureVreg +(ConcatShiftBytesRightUint8x16 ...) => (VPALIGNR128 ...) // pureVreg +(ConcatShiftBytesRightGroupedUint8x32 ...) => (VPALIGNR256 ...) // pureVreg +(ConcatShiftBytesRightGroupedUint8x64 ...) => (VPALIGNR512 ...) // pureVreg +(ConcatSubPairsFloat32x4 ...) => (VHSUBPS128 ...) // pureVreg +(ConcatSubPairsFloat64x2 ...) => (VHSUBPD128 ...) // pureVreg +(ConcatSubPairsInt16x8 ...) => (VPHSUBW128 ...) // pureVreg +(ConcatSubPairsInt32x4 ...) => (VPHSUBD128 ...) // pureVreg +(ConcatSubPairsUint16x8 ...) => (VPHSUBW128 ...) // pureVreg +(ConcatSubPairsUint32x4 ...) => (VPHSUBD128 ...) // pureVreg +(ConcatSubPairsGroupedFloat32x8 ...) => (VHSUBPS256 ...) // pureVreg +(ConcatSubPairsGroupedFloat64x4 ...) => (VHSUBPD256 ...) // pureVreg +(ConcatSubPairsGroupedInt16x16 ...) => (VPHSUBW256 ...) // pureVreg +(ConcatSubPairsGroupedInt32x8 ...) => (VPHSUBD256 ...) // pureVreg +(ConcatSubPairsGroupedUint16x16 ...) => (VPHSUBW256 ...) // pureVreg +(ConcatSubPairsGroupedUint32x8 ...) => (VPHSUBD256 ...) // pureVreg +(ConcatSubPairsSaturatedInt16x8 ...) => (VPHSUBSW128 ...) // pureVreg +(ConcatSubPairsSaturatedGroupedInt16x16 ...) => (VPHSUBSW256 ...) // pureVreg +(ConvertToFloat32Float64x2 ...) => (VCVTPD2PSX128 ...) // pureVreg +(ConvertToFloat32Float64x4 ...) => (VCVTPD2PSY128 ...) // pureVreg +(ConvertToFloat32Float64x8 ...) => (VCVTPD2PS256 ...) // pureVreg +(ConvertToFloat32Int32x4 ...) => (VCVTDQ2PS128 ...) // pureVreg +(ConvertToFloat32Int32x8 ...) => (VCVTDQ2PS256 ...) // pureVreg +(ConvertToFloat32Int32x16 ...) => (VCVTDQ2PS512 ...) // pureVreg +(ConvertToFloat32Int64x2 ...) => (VCVTQQ2PSX128 ...) // pureVreg +(ConvertToFloat32Int64x4 ...) => (VCVTQQ2PSY128 ...) // pureVreg +(ConvertToFloat32Int64x8 ...) => (VCVTQQ2PS256 ...) // pureVreg +(ConvertToFloat32Uint32x4 ...) => (VCVTUDQ2PS128 ...) // pureVreg +(ConvertToFloat32Uint32x8 ...) => (VCVTUDQ2PS256 ...) // pureVreg +(ConvertToFloat32Uint32x16 ...) => (VCVTUDQ2PS512 ...) // pureVreg +(ConvertToFloat32Uint64x2 ...) => (VCVTUQQ2PSX128 ...) // pureVreg +(ConvertToFloat32Uint64x4 ...) => (VCVTUQQ2PSY128 ...) // pureVreg +(ConvertToFloat32Uint64x8 ...) => (VCVTUQQ2PS256 ...) // pureVreg +(ConvertToFloat64Float32x4 ...) => (VCVTPS2PD256 ...) // pureVreg +(ConvertToFloat64Float32x8 ...) => (VCVTPS2PD512 ...) // pureVreg +(ConvertToFloat64Int32x4 ...) => (VCVTDQ2PD256 ...) // pureVreg +(ConvertToFloat64Int32x8 ...) => (VCVTDQ2PD512 ...) // pureVreg +(ConvertToFloat64Int64x2 ...) => (VCVTQQ2PD128 ...) // pureVreg +(ConvertToFloat64Int64x4 ...) => (VCVTQQ2PD256 ...) // pureVreg +(ConvertToFloat64Int64x8 ...) => (VCVTQQ2PD512 ...) // pureVreg +(ConvertToFloat64Uint32x4 ...) => (VCVTUDQ2PD256 ...) // pureVreg +(ConvertToFloat64Uint32x8 ...) => (VCVTUDQ2PD512 ...) // pureVreg +(ConvertToFloat64Uint64x2 ...) => (VCVTUQQ2PD128 ...) // pureVreg +(ConvertToFloat64Uint64x4 ...) => (VCVTUQQ2PD256 ...) // pureVreg +(ConvertToFloat64Uint64x8 ...) => (VCVTUQQ2PD512 ...) // pureVreg +(ConvertToInt32Float32x4 ...) => (VCVTTPS2DQ128 ...) // pureVreg +(ConvertToInt32Float32x8 ...) => (VCVTTPS2DQ256 ...) // pureVreg +(ConvertToInt32Float32x16 ...) => (VCVTTPS2DQ512 ...) // pureVreg +(ConvertToInt32Float64x2 ...) => (VCVTTPD2DQX128 ...) // pureVreg +(ConvertToInt32Float64x4 ...) => (VCVTTPD2DQY128 ...) // pureVreg +(ConvertToInt32Float64x8 ...) => (VCVTTPD2DQ256 ...) // pureVreg +(ConvertToInt64Float32x4 ...) => (VCVTTPS2QQ256 ...) // pureVreg +(ConvertToInt64Float32x8 ...) => (VCVTTPS2QQ512 ...) // pureVreg +(ConvertToInt64Float64x2 ...) => (VCVTTPD2QQ128 ...) // pureVreg +(ConvertToInt64Float64x4 ...) => (VCVTTPD2QQ256 ...) // pureVreg +(ConvertToInt64Float64x8 ...) => (VCVTTPD2QQ512 ...) // pureVreg +(ConvertToUint32Float32x4 ...) => (VCVTTPS2UDQ128 ...) // pureVreg +(ConvertToUint32Float32x8 ...) => (VCVTTPS2UDQ256 ...) // pureVreg +(ConvertToUint32Float32x16 ...) => (VCVTTPS2UDQ512 ...) // pureVreg +(ConvertToUint32Float64x2 ...) => (VCVTTPD2UDQX128 ...) // pureVreg +(ConvertToUint32Float64x4 ...) => (VCVTTPD2UDQY128 ...) // pureVreg +(ConvertToUint32Float64x8 ...) => (VCVTTPD2UDQ256 ...) // pureVreg +(ConvertToUint64Float32x4 ...) => (VCVTTPS2UQQ256 ...) // pureVreg +(ConvertToUint64Float32x8 ...) => (VCVTTPS2UQQ512 ...) // pureVreg +(ConvertToUint64Float64x2 ...) => (VCVTTPD2UQQ128 ...) // pureVreg +(ConvertToUint64Float64x4 ...) => (VCVTTPD2UQQ256 ...) // pureVreg +(ConvertToUint64Float64x8 ...) => (VCVTTPD2UQQ512 ...) // pureVreg +(DivFloat32x4 ...) => (VDIVPS128 ...) // pureVreg +(DivFloat32x8 ...) => (VDIVPS256 ...) // pureVreg +(DivFloat32x16 ...) => (VDIVPS512 ...) // pureVreg +(DivFloat64x2 ...) => (VDIVPD128 ...) // pureVreg +(DivFloat64x4 ...) => (VDIVPD256 ...) // pureVreg +(DivFloat64x8 ...) => (VDIVPD512 ...) // pureVreg +(DotProductPairsInt16x8 ...) => (VPMADDWD128 ...) // pureVreg +(DotProductPairsInt16x16 ...) => (VPMADDWD256 ...) // pureVreg +(DotProductPairsInt16x32 ...) => (VPMADDWD512 ...) // pureVreg +(DotProductPairsSaturatedUint8x16 ...) => (VPMADDUBSW128 ...) // pureVreg +(DotProductPairsSaturatedUint8x32 ...) => (VPMADDUBSW256 ...) // pureVreg +(DotProductPairsSaturatedUint8x64 ...) => (VPMADDUBSW512 ...) // pureVreg +(EqualFloat32x4 x y) => (VCMPPS128 [0] x y) // pureVreg +(EqualFloat32x8 x y) => (VCMPPS256 [0] x y) // pureVreg +(EqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [0] x y)) // maskOut +(EqualFloat64x2 x y) => (VCMPPD128 [0] x y) // pureVreg +(EqualFloat64x4 x y) => (VCMPPD256 [0] x y) // pureVreg +(EqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [0] x y)) // maskOut +(EqualInt8x16 ...) => (VPCMPEQB128 ...) // pureVreg +(EqualInt8x32 ...) => (VPCMPEQB256 ...) // pureVreg +(EqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPEQB512 x y)) // maskOut +(EqualInt16x8 ...) => (VPCMPEQW128 ...) // pureVreg +(EqualInt16x16 ...) => (VPCMPEQW256 ...) // pureVreg +(EqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPEQW512 x y)) // maskOut +(EqualInt32x4 ...) => (VPCMPEQD128 ...) // pureVreg +(EqualInt32x8 ...) => (VPCMPEQD256 ...) // pureVreg +(EqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPEQD512 x y)) // maskOut +(EqualInt64x2 ...) => (VPCMPEQQ128 ...) // pureVreg +(EqualInt64x4 ...) => (VPCMPEQQ256 ...) // pureVreg +(EqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPEQQ512 x y)) // maskOut +(EqualUint8x16 ...) => (VPCMPEQB128 ...) // pureVreg +(EqualUint8x32 ...) => (VPCMPEQB256 ...) // pureVreg +(EqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPEQB512 x y)) // maskOut +(EqualUint16x8 ...) => (VPCMPEQW128 ...) // pureVreg +(EqualUint16x16 ...) => (VPCMPEQW256 ...) // pureVreg +(EqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPEQW512 x y)) // maskOut +(EqualUint32x4 ...) => (VPCMPEQD128 ...) // pureVreg +(EqualUint32x8 ...) => (VPCMPEQD256 ...) // pureVreg +(EqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPEQD512 x y)) // maskOut +(EqualUint64x2 ...) => (VPCMPEQQ128 ...) // pureVreg +(EqualUint64x4 ...) => (VPCMPEQQ256 ...) // pureVreg +(EqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPEQQ512 x y)) // maskOut +(ExpandFloat32x4 x mask) => (VEXPANDPSMasked128 x (VPMOVVec32x4ToM mask)) // maskIn +(ExpandFloat32x8 x mask) => (VEXPANDPSMasked256 x (VPMOVVec32x8ToM mask)) // maskIn +(ExpandFloat32x16 x mask) => (VEXPANDPSMasked512 x (VPMOVVec32x16ToM mask)) // maskIn +(ExpandFloat64x2 x mask) => (VEXPANDPDMasked128 x (VPMOVVec64x2ToM mask)) // maskIn +(ExpandFloat64x4 x mask) => (VEXPANDPDMasked256 x (VPMOVVec64x4ToM mask)) // maskIn +(ExpandFloat64x8 x mask) => (VEXPANDPDMasked512 x (VPMOVVec64x8ToM mask)) // maskIn +(ExpandInt8x16 x mask) => (VPEXPANDBMasked128 x (VPMOVVec8x16ToM mask)) // maskIn +(ExpandInt8x32 x mask) => (VPEXPANDBMasked256 x (VPMOVVec8x32ToM mask)) // maskIn +(ExpandInt8x64 x mask) => (VPEXPANDBMasked512 x (VPMOVVec8x64ToM mask)) // maskIn +(ExpandInt16x8 x mask) => (VPEXPANDWMasked128 x (VPMOVVec16x8ToM mask)) // maskIn +(ExpandInt16x16 x mask) => (VPEXPANDWMasked256 x (VPMOVVec16x16ToM mask)) // maskIn +(ExpandInt16x32 x mask) => (VPEXPANDWMasked512 x (VPMOVVec16x32ToM mask)) // maskIn +(ExpandInt32x4 x mask) => (VPEXPANDDMasked128 x (VPMOVVec32x4ToM mask)) // maskIn +(ExpandInt32x8 x mask) => (VPEXPANDDMasked256 x (VPMOVVec32x8ToM mask)) // maskIn +(ExpandInt32x16 x mask) => (VPEXPANDDMasked512 x (VPMOVVec32x16ToM mask)) // maskIn +(ExpandInt64x2 x mask) => (VPEXPANDQMasked128 x (VPMOVVec64x2ToM mask)) // maskIn +(ExpandInt64x4 x mask) => (VPEXPANDQMasked256 x (VPMOVVec64x4ToM mask)) // maskIn +(ExpandInt64x8 x mask) => (VPEXPANDQMasked512 x (VPMOVVec64x8ToM mask)) // maskIn +(ExpandUint8x16 x mask) => (VPEXPANDBMasked128 x (VPMOVVec8x16ToM mask)) // maskIn +(ExpandUint8x32 x mask) => (VPEXPANDBMasked256 x (VPMOVVec8x32ToM mask)) // maskIn +(ExpandUint8x64 x mask) => (VPEXPANDBMasked512 x (VPMOVVec8x64ToM mask)) // maskIn +(ExpandUint16x8 x mask) => (VPEXPANDWMasked128 x (VPMOVVec16x8ToM mask)) // maskIn +(ExpandUint16x16 x mask) => (VPEXPANDWMasked256 x (VPMOVVec16x16ToM mask)) // maskIn +(ExpandUint16x32 x mask) => (VPEXPANDWMasked512 x (VPMOVVec16x32ToM mask)) // maskIn +(ExpandUint32x4 x mask) => (VPEXPANDDMasked128 x (VPMOVVec32x4ToM mask)) // maskIn +(ExpandUint32x8 x mask) => (VPEXPANDDMasked256 x (VPMOVVec32x8ToM mask)) // maskIn +(ExpandUint32x16 x mask) => (VPEXPANDDMasked512 x (VPMOVVec32x16ToM mask)) // maskIn +(ExpandUint64x2 x mask) => (VPEXPANDQMasked128 x (VPMOVVec64x2ToM mask)) // maskIn +(ExpandUint64x4 x mask) => (VPEXPANDQMasked256 x (VPMOVVec64x4ToM mask)) // maskIn +(ExpandUint64x8 x mask) => (VPEXPANDQMasked512 x (VPMOVVec64x8ToM mask)) // maskIn +(ExtendLo2ToInt64Int8x16 ...) => (VPMOVSXBQ128 ...) // pureVreg +(ExtendLo2ToInt64Int16x8 ...) => (VPMOVSXWQ128 ...) // pureVreg +(ExtendLo2ToInt64Int32x4 ...) => (VPMOVSXDQ128 ...) // pureVreg +(ExtendLo2ToUint64Uint8x16 ...) => (VPMOVZXBQ128 ...) // pureVreg +(ExtendLo2ToUint64Uint16x8 ...) => (VPMOVZXWQ128 ...) // pureVreg +(ExtendLo2ToUint64Uint32x4 ...) => (VPMOVZXDQ128 ...) // pureVreg +(ExtendLo4ToInt32Int8x16 ...) => (VPMOVSXBD128 ...) // pureVreg +(ExtendLo4ToInt32Int16x8 ...) => (VPMOVSXWD128 ...) // pureVreg +(ExtendLo4ToInt64Int8x16 ...) => (VPMOVSXBQ256 ...) // pureVreg +(ExtendLo4ToInt64Int16x8 ...) => (VPMOVSXWQ256 ...) // pureVreg +(ExtendLo4ToUint32Uint8x16 ...) => (VPMOVZXBD128 ...) // pureVreg +(ExtendLo4ToUint32Uint16x8 ...) => (VPMOVZXWD128 ...) // pureVreg +(ExtendLo4ToUint64Uint8x16 ...) => (VPMOVZXBQ256 ...) // pureVreg +(ExtendLo4ToUint64Uint16x8 ...) => (VPMOVZXWQ256 ...) // pureVreg +(ExtendLo8ToInt16Int8x16 ...) => (VPMOVSXBW128 ...) // pureVreg +(ExtendLo8ToInt32Int8x16 ...) => (VPMOVSXBD256 ...) // pureVreg +(ExtendLo8ToInt64Int8x16 ...) => (VPMOVSXBQ512 ...) // pureVreg +(ExtendLo8ToUint16Uint8x16 ...) => (VPMOVZXBW128 ...) // pureVreg +(ExtendLo8ToUint32Uint8x16 ...) => (VPMOVZXBD256 ...) // pureVreg +(ExtendLo8ToUint64Uint8x16 ...) => (VPMOVZXBQ512 ...) // pureVreg +(ExtendToInt16Int8x16 ...) => (VPMOVSXBW256 ...) // pureVreg +(ExtendToInt16Int8x32 ...) => (VPMOVSXBW512 ...) // pureVreg +(ExtendToInt32Int8x16 ...) => (VPMOVSXBD512 ...) // pureVreg +(ExtendToInt32Int16x8 ...) => (VPMOVSXWD256 ...) // pureVreg +(ExtendToInt32Int16x16 ...) => (VPMOVSXWD512 ...) // pureVreg +(ExtendToInt64Int16x8 ...) => (VPMOVSXWQ512 ...) // pureVreg +(ExtendToInt64Int32x4 ...) => (VPMOVSXDQ256 ...) // pureVreg +(ExtendToInt64Int32x8 ...) => (VPMOVSXDQ512 ...) // pureVreg +(ExtendToUint16Uint8x16 ...) => (VPMOVZXBW256 ...) // pureVreg +(ExtendToUint16Uint8x32 ...) => (VPMOVZXBW512 ...) // pureVreg +(ExtendToUint32Uint8x16 ...) => (VPMOVZXBD512 ...) // pureVreg +(ExtendToUint32Uint16x8 ...) => (VPMOVZXWD256 ...) // pureVreg +(ExtendToUint32Uint16x16 ...) => (VPMOVZXWD512 ...) // pureVreg +(ExtendToUint64Uint16x8 ...) => (VPMOVZXWQ512 ...) // pureVreg +(ExtendToUint64Uint32x4 ...) => (VPMOVZXDQ256 ...) // pureVreg +(ExtendToUint64Uint32x8 ...) => (VPMOVZXDQ512 ...) // pureVreg +(FloorFloat32x4 x) => (VROUNDPS128 [1] x) // pureVreg +(FloorFloat32x8 x) => (VROUNDPS256 [1] x) // pureVreg +(FloorFloat64x2 x) => (VROUNDPD128 [1] x) // pureVreg +(FloorFloat64x4 x) => (VROUNDPD256 [1] x) // pureVreg +(FloorScaledFloat32x4 [a] x) => (VRNDSCALEPS128 [a+1] x) // pureVreg +(FloorScaledFloat32x8 [a] x) => (VRNDSCALEPS256 [a+1] x) // pureVreg +(FloorScaledFloat32x16 [a] x) => (VRNDSCALEPS512 [a+1] x) // pureVreg +(FloorScaledFloat64x2 [a] x) => (VRNDSCALEPD128 [a+1] x) // pureVreg +(FloorScaledFloat64x4 [a] x) => (VRNDSCALEPD256 [a+1] x) // pureVreg +(FloorScaledFloat64x8 [a] x) => (VRNDSCALEPD512 [a+1] x) // pureVreg +(FloorScaledResidueFloat32x4 [a] x) => (VREDUCEPS128 [a+1] x) // pureVreg +(FloorScaledResidueFloat32x8 [a] x) => (VREDUCEPS256 [a+1] x) // pureVreg +(FloorScaledResidueFloat32x16 [a] x) => (VREDUCEPS512 [a+1] x) // pureVreg +(FloorScaledResidueFloat64x2 [a] x) => (VREDUCEPD128 [a+1] x) // pureVreg +(FloorScaledResidueFloat64x4 [a] x) => (VREDUCEPD256 [a+1] x) // pureVreg +(FloorScaledResidueFloat64x8 [a] x) => (VREDUCEPD512 [a+1] x) // pureVreg +(GaloisFieldAffineTransformUint8x16 ...) => (VGF2P8AFFINEQB128 ...) // pureVreg +(GaloisFieldAffineTransformUint8x32 ...) => (VGF2P8AFFINEQB256 ...) // pureVreg +(GaloisFieldAffineTransformUint8x64 ...) => (VGF2P8AFFINEQB512 ...) // pureVreg +(GaloisFieldAffineTransformInverseUint8x16 ...) => (VGF2P8AFFINEINVQB128 ...) // pureVreg +(GaloisFieldAffineTransformInverseUint8x32 ...) => (VGF2P8AFFINEINVQB256 ...) // pureVreg +(GaloisFieldAffineTransformInverseUint8x64 ...) => (VGF2P8AFFINEINVQB512 ...) // pureVreg +(GaloisFieldMulUint8x16 ...) => (VGF2P8MULB128 ...) // pureVreg +(GaloisFieldMulUint8x32 ...) => (VGF2P8MULB256 ...) // pureVreg +(GaloisFieldMulUint8x64 ...) => (VGF2P8MULB512 ...) // pureVreg +(GetElemFloat32x4 ...) => (VPEXTRD128 ...) // pureVreg +(GetElemFloat64x2 ...) => (VPEXTRQ128 ...) // pureVreg +(GetElemInt8x16 ...) => (VPEXTRB128 ...) // pureVreg +(GetElemInt16x8 ...) => (VPEXTRW128 ...) // pureVreg +(GetElemInt32x4 ...) => (VPEXTRD128 ...) // pureVreg +(GetElemInt64x2 ...) => (VPEXTRQ128 ...) // pureVreg +(GetElemUint8x16 ...) => (VPEXTRB128 ...) // pureVreg +(GetElemUint16x8 ...) => (VPEXTRW128 ...) // pureVreg +(GetElemUint32x4 ...) => (VPEXTRD128 ...) // pureVreg +(GetElemUint64x2 ...) => (VPEXTRQ128 ...) // pureVreg +(GetHiFloat32x8 x) => (VEXTRACTF128128 [1] x) // pureVreg +(GetHiFloat32x16 x) => (VEXTRACTF64X4256 [1] x) // pureVreg +(GetHiFloat64x4 x) => (VEXTRACTF128128 [1] x) // pureVreg +(GetHiFloat64x8 x) => (VEXTRACTF64X4256 [1] x) // pureVreg +(GetHiInt8x32 x) => (VEXTRACTI128128 [1] x) // pureVreg +(GetHiInt8x64 x) => (VEXTRACTI64X4256 [1] x) // pureVreg +(GetHiInt16x16 x) => (VEXTRACTI128128 [1] x) // pureVreg +(GetHiInt16x32 x) => (VEXTRACTI64X4256 [1] x) // pureVreg +(GetHiInt32x8 x) => (VEXTRACTI128128 [1] x) // pureVreg +(GetHiInt32x16 x) => (VEXTRACTI64X4256 [1] x) // pureVreg +(GetHiInt64x4 x) => (VEXTRACTI128128 [1] x) // pureVreg +(GetHiInt64x8 x) => (VEXTRACTI64X4256 [1] x) // pureVreg +(GetHiUint8x32 x) => (VEXTRACTI128128 [1] x) // pureVreg +(GetHiUint8x64 x) => (VEXTRACTI64X4256 [1] x) // pureVreg +(GetHiUint16x16 x) => (VEXTRACTI128128 [1] x) // pureVreg +(GetHiUint16x32 x) => (VEXTRACTI64X4256 [1] x) // pureVreg +(GetHiUint32x8 x) => (VEXTRACTI128128 [1] x) // pureVreg +(GetHiUint32x16 x) => (VEXTRACTI64X4256 [1] x) // pureVreg +(GetHiUint64x4 x) => (VEXTRACTI128128 [1] x) // pureVreg +(GetHiUint64x8 x) => (VEXTRACTI64X4256 [1] x) // pureVreg +(GetLoFloat32x8 x) => (VEXTRACTF128128 [0] x) // pureVreg +(GetLoFloat32x16 x) => (VEXTRACTF64X4256 [0] x) // pureVreg +(GetLoFloat64x4 x) => (VEXTRACTF128128 [0] x) // pureVreg +(GetLoFloat64x8 x) => (VEXTRACTF64X4256 [0] x) // pureVreg +(GetLoInt8x32 x) => (VEXTRACTI128128 [0] x) // pureVreg +(GetLoInt8x64 x) => (VEXTRACTI64X4256 [0] x) // pureVreg +(GetLoInt16x16 x) => (VEXTRACTI128128 [0] x) // pureVreg +(GetLoInt16x32 x) => (VEXTRACTI64X4256 [0] x) // pureVreg +(GetLoInt32x8 x) => (VEXTRACTI128128 [0] x) // pureVreg +(GetLoInt32x16 x) => (VEXTRACTI64X4256 [0] x) // pureVreg +(GetLoInt64x4 x) => (VEXTRACTI128128 [0] x) // pureVreg +(GetLoInt64x8 x) => (VEXTRACTI64X4256 [0] x) // pureVreg +(GetLoUint8x32 x) => (VEXTRACTI128128 [0] x) // pureVreg +(GetLoUint8x64 x) => (VEXTRACTI64X4256 [0] x) // pureVreg +(GetLoUint16x16 x) => (VEXTRACTI128128 [0] x) // pureVreg +(GetLoUint16x32 x) => (VEXTRACTI64X4256 [0] x) // pureVreg +(GetLoUint32x8 x) => (VEXTRACTI128128 [0] x) // pureVreg +(GetLoUint32x16 x) => (VEXTRACTI64X4256 [0] x) // pureVreg +(GetLoUint64x4 x) => (VEXTRACTI128128 [0] x) // pureVreg +(GetLoUint64x8 x) => (VEXTRACTI64X4256 [0] x) // pureVreg +(GreaterFloat32x4 x y) => (VCMPPS128 [14] x y) // pureVreg +(GreaterFloat32x8 x y) => (VCMPPS256 [14] x y) // pureVreg +(GreaterFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [14] x y)) // maskOut +(GreaterFloat64x2 x y) => (VCMPPD128 [14] x y) // pureVreg +(GreaterFloat64x4 x y) => (VCMPPD256 [14] x y) // pureVreg +(GreaterFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [14] x y)) // maskOut +(GreaterInt8x16 ...) => (VPCMPGTB128 ...) // pureVreg +(GreaterInt8x32 ...) => (VPCMPGTB256 ...) // pureVreg +(GreaterInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPGTB512 x y)) // maskOut +(GreaterInt16x8 ...) => (VPCMPGTW128 ...) // pureVreg +(GreaterInt16x16 ...) => (VPCMPGTW256 ...) // pureVreg +(GreaterInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPGTW512 x y)) // maskOut +(GreaterInt32x4 ...) => (VPCMPGTD128 ...) // pureVreg +(GreaterInt32x8 ...) => (VPCMPGTD256 ...) // pureVreg +(GreaterInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPGTD512 x y)) // maskOut +(GreaterInt64x2 ...) => (VPCMPGTQ128 ...) // pureVreg +(GreaterInt64x4 ...) => (VPCMPGTQ256 ...) // pureVreg +(GreaterInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPGTQ512 x y)) // maskOut +(GreaterUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [14] x y)) // maskOut +(GreaterUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [14] x y)) // maskOut +(GreaterUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [14] x y)) // maskOut +(GreaterUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [14] x y)) // maskOut +(GreaterEqualFloat32x4 x y) => (VCMPPS128 [13] x y) // pureVreg +(GreaterEqualFloat32x8 x y) => (VCMPPS256 [13] x y) // pureVreg +(GreaterEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [13] x y)) // maskOut +(GreaterEqualFloat64x2 x y) => (VCMPPD128 [13] x y) // pureVreg +(GreaterEqualFloat64x4 x y) => (VCMPPD256 [13] x y) // pureVreg +(GreaterEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [13] x y)) // maskOut +(GreaterEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [13] x y)) // maskOut +(GreaterEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [13] x y)) // maskOut +(GreaterEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [13] x y)) // maskOut +(GreaterEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [13] x y)) // maskOut +(GreaterEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [13] x y)) // maskOut +(GreaterEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [13] x y)) // maskOut +(GreaterEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [13] x y)) // maskOut +(GreaterEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [13] x y)) // maskOut +(InterleaveHiInt16x8 ...) => (VPUNPCKHWD128 ...) // pureVreg +(InterleaveHiInt32x4 ...) => (VPUNPCKHDQ128 ...) // pureVreg +(InterleaveHiInt64x2 ...) => (VPUNPCKHQDQ128 ...) // pureVreg +(InterleaveHiUint16x8 ...) => (VPUNPCKHWD128 ...) // pureVreg +(InterleaveHiUint32x4 ...) => (VPUNPCKHDQ128 ...) // pureVreg +(InterleaveHiUint64x2 ...) => (VPUNPCKHQDQ128 ...) // pureVreg +(InterleaveHiGroupedInt16x16 ...) => (VPUNPCKHWD256 ...) // pureVreg +(InterleaveHiGroupedInt16x32 ...) => (VPUNPCKHWD512 ...) // pureVreg +(InterleaveHiGroupedInt32x8 ...) => (VPUNPCKHDQ256 ...) // pureVreg +(InterleaveHiGroupedInt32x16 ...) => (VPUNPCKHDQ512 ...) // pureVreg +(InterleaveHiGroupedInt64x4 ...) => (VPUNPCKHQDQ256 ...) // pureVreg +(InterleaveHiGroupedInt64x8 ...) => (VPUNPCKHQDQ512 ...) // pureVreg +(InterleaveHiGroupedUint16x16 ...) => (VPUNPCKHWD256 ...) // pureVreg +(InterleaveHiGroupedUint16x32 ...) => (VPUNPCKHWD512 ...) // pureVreg +(InterleaveHiGroupedUint32x8 ...) => (VPUNPCKHDQ256 ...) // pureVreg +(InterleaveHiGroupedUint32x16 ...) => (VPUNPCKHDQ512 ...) // pureVreg +(InterleaveHiGroupedUint64x4 ...) => (VPUNPCKHQDQ256 ...) // pureVreg +(InterleaveHiGroupedUint64x8 ...) => (VPUNPCKHQDQ512 ...) // pureVreg +(InterleaveLoInt16x8 ...) => (VPUNPCKLWD128 ...) // pureVreg +(InterleaveLoInt32x4 ...) => (VPUNPCKLDQ128 ...) // pureVreg +(InterleaveLoInt64x2 ...) => (VPUNPCKLQDQ128 ...) // pureVreg +(InterleaveLoUint16x8 ...) => (VPUNPCKLWD128 ...) // pureVreg +(InterleaveLoUint32x4 ...) => (VPUNPCKLDQ128 ...) // pureVreg +(InterleaveLoUint64x2 ...) => (VPUNPCKLQDQ128 ...) // pureVreg +(InterleaveLoGroupedInt16x16 ...) => (VPUNPCKLWD256 ...) // pureVreg +(InterleaveLoGroupedInt16x32 ...) => (VPUNPCKLWD512 ...) // pureVreg +(InterleaveLoGroupedInt32x8 ...) => (VPUNPCKLDQ256 ...) // pureVreg +(InterleaveLoGroupedInt32x16 ...) => (VPUNPCKLDQ512 ...) // pureVreg +(InterleaveLoGroupedInt64x4 ...) => (VPUNPCKLQDQ256 ...) // pureVreg +(InterleaveLoGroupedInt64x8 ...) => (VPUNPCKLQDQ512 ...) // pureVreg +(InterleaveLoGroupedUint16x16 ...) => (VPUNPCKLWD256 ...) // pureVreg +(InterleaveLoGroupedUint16x32 ...) => (VPUNPCKLWD512 ...) // pureVreg +(InterleaveLoGroupedUint32x8 ...) => (VPUNPCKLDQ256 ...) // pureVreg +(InterleaveLoGroupedUint32x16 ...) => (VPUNPCKLDQ512 ...) // pureVreg +(InterleaveLoGroupedUint64x4 ...) => (VPUNPCKLQDQ256 ...) // pureVreg +(InterleaveLoGroupedUint64x8 ...) => (VPUNPCKLQDQ512 ...) // pureVreg +(LeadingZerosInt32x4 ...) => (VPLZCNTD128 ...) // pureVreg +(LeadingZerosInt32x8 ...) => (VPLZCNTD256 ...) // pureVreg +(LeadingZerosInt32x16 ...) => (VPLZCNTD512 ...) // pureVreg +(LeadingZerosInt64x2 ...) => (VPLZCNTQ128 ...) // pureVreg +(LeadingZerosInt64x4 ...) => (VPLZCNTQ256 ...) // pureVreg +(LeadingZerosInt64x8 ...) => (VPLZCNTQ512 ...) // pureVreg +(LeadingZerosUint32x4 ...) => (VPLZCNTD128 ...) // pureVreg +(LeadingZerosUint32x8 ...) => (VPLZCNTD256 ...) // pureVreg +(LeadingZerosUint32x16 ...) => (VPLZCNTD512 ...) // pureVreg +(LeadingZerosUint64x2 ...) => (VPLZCNTQ128 ...) // pureVreg +(LeadingZerosUint64x4 ...) => (VPLZCNTQ256 ...) // pureVreg +(LeadingZerosUint64x8 ...) => (VPLZCNTQ512 ...) // pureVreg +(LessFloat32x4 x y) => (VCMPPS128 [1] x y) // pureVreg +(LessFloat32x8 x y) => (VCMPPS256 [1] x y) // pureVreg +(LessFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [1] x y)) // maskOut +(LessFloat64x2 x y) => (VCMPPD128 [1] x y) // pureVreg +(LessFloat64x4 x y) => (VCMPPD256 [1] x y) // pureVreg +(LessFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [1] x y)) // maskOut +(LessInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [1] x y)) // maskOut +(LessInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [1] x y)) // maskOut +(LessInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [1] x y)) // maskOut +(LessInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [1] x y)) // maskOut +(LessUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [1] x y)) // maskOut +(LessUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [1] x y)) // maskOut +(LessUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [1] x y)) // maskOut +(LessUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [1] x y)) // maskOut +(LessEqualFloat32x4 x y) => (VCMPPS128 [2] x y) // pureVreg +(LessEqualFloat32x8 x y) => (VCMPPS256 [2] x y) // pureVreg +(LessEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [2] x y)) // maskOut +(LessEqualFloat64x2 x y) => (VCMPPD128 [2] x y) // pureVreg +(LessEqualFloat64x4 x y) => (VCMPPD256 [2] x y) // pureVreg +(LessEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [2] x y)) // maskOut +(LessEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [2] x y)) // maskOut +(LessEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [2] x y)) // maskOut +(LessEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [2] x y)) // maskOut +(LessEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [2] x y)) // maskOut +(LessEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [2] x y)) // maskOut +(LessEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [2] x y)) // maskOut +(LessEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [2] x y)) // maskOut +(LessEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [2] x y)) // maskOut +(MaxFloat32x4 ...) => (VMAXPS128 ...) // pureVreg +(MaxFloat32x8 ...) => (VMAXPS256 ...) // pureVreg +(MaxFloat32x16 ...) => (VMAXPS512 ...) // pureVreg +(MaxFloat64x2 ...) => (VMAXPD128 ...) // pureVreg +(MaxFloat64x4 ...) => (VMAXPD256 ...) // pureVreg +(MaxFloat64x8 ...) => (VMAXPD512 ...) // pureVreg +(MaxInt8x16 ...) => (VPMAXSB128 ...) // pureVreg +(MaxInt8x32 ...) => (VPMAXSB256 ...) // pureVreg +(MaxInt8x64 ...) => (VPMAXSB512 ...) // pureVreg +(MaxInt16x8 ...) => (VPMAXSW128 ...) // pureVreg +(MaxInt16x16 ...) => (VPMAXSW256 ...) // pureVreg +(MaxInt16x32 ...) => (VPMAXSW512 ...) // pureVreg +(MaxInt32x4 ...) => (VPMAXSD128 ...) // pureVreg +(MaxInt32x8 ...) => (VPMAXSD256 ...) // pureVreg +(MaxInt32x16 ...) => (VPMAXSD512 ...) // pureVreg +(MaxInt64x2 ...) => (VPMAXSQ128 ...) // pureVreg +(MaxInt64x4 ...) => (VPMAXSQ256 ...) // pureVreg +(MaxInt64x8 ...) => (VPMAXSQ512 ...) // pureVreg +(MaxUint8x16 ...) => (VPMAXUB128 ...) // pureVreg +(MaxUint8x32 ...) => (VPMAXUB256 ...) // pureVreg +(MaxUint8x64 ...) => (VPMAXUB512 ...) // pureVreg +(MaxUint16x8 ...) => (VPMAXUW128 ...) // pureVreg +(MaxUint16x16 ...) => (VPMAXUW256 ...) // pureVreg +(MaxUint16x32 ...) => (VPMAXUW512 ...) // pureVreg +(MaxUint32x4 ...) => (VPMAXUD128 ...) // pureVreg +(MaxUint32x8 ...) => (VPMAXUD256 ...) // pureVreg +(MaxUint32x16 ...) => (VPMAXUD512 ...) // pureVreg +(MaxUint64x2 ...) => (VPMAXUQ128 ...) // pureVreg +(MaxUint64x4 ...) => (VPMAXUQ256 ...) // pureVreg +(MaxUint64x8 ...) => (VPMAXUQ512 ...) // pureVreg +(MinFloat32x4 ...) => (VMINPS128 ...) // pureVreg +(MinFloat32x8 ...) => (VMINPS256 ...) // pureVreg +(MinFloat32x16 ...) => (VMINPS512 ...) // pureVreg +(MinFloat64x2 ...) => (VMINPD128 ...) // pureVreg +(MinFloat64x4 ...) => (VMINPD256 ...) // pureVreg +(MinFloat64x8 ...) => (VMINPD512 ...) // pureVreg +(MinInt8x16 ...) => (VPMINSB128 ...) // pureVreg +(MinInt8x32 ...) => (VPMINSB256 ...) // pureVreg +(MinInt8x64 ...) => (VPMINSB512 ...) // pureVreg +(MinInt16x8 ...) => (VPMINSW128 ...) // pureVreg +(MinInt16x16 ...) => (VPMINSW256 ...) // pureVreg +(MinInt16x32 ...) => (VPMINSW512 ...) // pureVreg +(MinInt32x4 ...) => (VPMINSD128 ...) // pureVreg +(MinInt32x8 ...) => (VPMINSD256 ...) // pureVreg +(MinInt32x16 ...) => (VPMINSD512 ...) // pureVreg +(MinInt64x2 ...) => (VPMINSQ128 ...) // pureVreg +(MinInt64x4 ...) => (VPMINSQ256 ...) // pureVreg +(MinInt64x8 ...) => (VPMINSQ512 ...) // pureVreg +(MinUint8x16 ...) => (VPMINUB128 ...) // pureVreg +(MinUint8x32 ...) => (VPMINUB256 ...) // pureVreg +(MinUint8x64 ...) => (VPMINUB512 ...) // pureVreg +(MinUint16x8 ...) => (VPMINUW128 ...) // pureVreg +(MinUint16x16 ...) => (VPMINUW256 ...) // pureVreg +(MinUint16x32 ...) => (VPMINUW512 ...) // pureVreg +(MinUint32x4 ...) => (VPMINUD128 ...) // pureVreg +(MinUint32x8 ...) => (VPMINUD256 ...) // pureVreg +(MinUint32x16 ...) => (VPMINUD512 ...) // pureVreg +(MinUint64x2 ...) => (VPMINUQ128 ...) // pureVreg +(MinUint64x4 ...) => (VPMINUQ256 ...) // pureVreg +(MinUint64x8 ...) => (VPMINUQ512 ...) // pureVreg +(MulFloat32x4 ...) => (VMULPS128 ...) // pureVreg +(MulFloat32x8 ...) => (VMULPS256 ...) // pureVreg +(MulFloat32x16 ...) => (VMULPS512 ...) // pureVreg +(MulFloat64x2 ...) => (VMULPD128 ...) // pureVreg +(MulFloat64x4 ...) => (VMULPD256 ...) // pureVreg +(MulFloat64x8 ...) => (VMULPD512 ...) // pureVreg +(MulInt16x8 ...) => (VPMULLW128 ...) // pureVreg +(MulInt16x16 ...) => (VPMULLW256 ...) // pureVreg +(MulInt16x32 ...) => (VPMULLW512 ...) // pureVreg +(MulInt32x4 ...) => (VPMULLD128 ...) // pureVreg +(MulInt32x8 ...) => (VPMULLD256 ...) // pureVreg +(MulInt32x16 ...) => (VPMULLD512 ...) // pureVreg +(MulInt64x2 ...) => (VPMULLQ128 ...) // pureVreg +(MulInt64x4 ...) => (VPMULLQ256 ...) // pureVreg +(MulInt64x8 ...) => (VPMULLQ512 ...) // pureVreg +(MulUint16x8 ...) => (VPMULLW128 ...) // pureVreg +(MulUint16x16 ...) => (VPMULLW256 ...) // pureVreg +(MulUint16x32 ...) => (VPMULLW512 ...) // pureVreg +(MulUint32x4 ...) => (VPMULLD128 ...) // pureVreg +(MulUint32x8 ...) => (VPMULLD256 ...) // pureVreg +(MulUint32x16 ...) => (VPMULLD512 ...) // pureVreg +(MulUint64x2 ...) => (VPMULLQ128 ...) // pureVreg +(MulUint64x4 ...) => (VPMULLQ256 ...) // pureVreg +(MulUint64x8 ...) => (VPMULLQ512 ...) // pureVreg +(MulAddFloat32x4 ...) => (VFMADD213PS128 ...) // pureVreg +(MulAddFloat32x8 ...) => (VFMADD213PS256 ...) // pureVreg +(MulAddFloat32x16 ...) => (VFMADD213PS512 ...) // pureVreg +(MulAddFloat64x2 ...) => (VFMADD213PD128 ...) // pureVreg +(MulAddFloat64x4 ...) => (VFMADD213PD256 ...) // pureVreg +(MulAddFloat64x8 ...) => (VFMADD213PD512 ...) // pureVreg +(MulAddEvenSubOddFloat32x4 ...) => (VFMADDSUB213PS128 ...) // pureVreg +(MulAddEvenSubOddFloat32x8 ...) => (VFMADDSUB213PS256 ...) // pureVreg +(MulAddEvenSubOddFloat32x16 ...) => (VFMADDSUB213PS512 ...) // pureVreg +(MulAddEvenSubOddFloat64x2 ...) => (VFMADDSUB213PD128 ...) // pureVreg +(MulAddEvenSubOddFloat64x4 ...) => (VFMADDSUB213PD256 ...) // pureVreg +(MulAddEvenSubOddFloat64x8 ...) => (VFMADDSUB213PD512 ...) // pureVreg +(MulAddOddSubEvenFloat32x4 ...) => (VFMSUBADD213PS128 ...) // pureVreg +(MulAddOddSubEvenFloat32x8 ...) => (VFMSUBADD213PS256 ...) // pureVreg +(MulAddOddSubEvenFloat32x16 ...) => (VFMSUBADD213PS512 ...) // pureVreg +(MulAddOddSubEvenFloat64x2 ...) => (VFMSUBADD213PD128 ...) // pureVreg +(MulAddOddSubEvenFloat64x4 ...) => (VFMSUBADD213PD256 ...) // pureVreg +(MulAddOddSubEvenFloat64x8 ...) => (VFMSUBADD213PD512 ...) // pureVreg +(MulHighInt16x8 ...) => (VPMULHW128 ...) // pureVreg +(MulHighInt16x16 ...) => (VPMULHW256 ...) // pureVreg +(MulHighInt16x32 ...) => (VPMULHW512 ...) // pureVreg +(MulHighUint16x8 ...) => (VPMULHUW128 ...) // pureVreg +(MulHighUint16x16 ...) => (VPMULHUW256 ...) // pureVreg +(MulHighUint16x32 ...) => (VPMULHUW512 ...) // pureVreg +(MulSignInt8x16 ...) => (VPSIGNB128 ...) // pureVreg +(MulSignInt8x32 ...) => (VPSIGNB256 ...) // pureVreg +(MulSignInt16x8 ...) => (VPSIGNW128 ...) // pureVreg +(MulSignInt16x16 ...) => (VPSIGNW256 ...) // pureVreg +(MulSignInt32x4 ...) => (VPSIGND128 ...) // pureVreg +(MulSignInt32x8 ...) => (VPSIGND256 ...) // pureVreg +(MulWidenEvenInt32x4 ...) => (VPMULDQ128 ...) // pureVreg +(MulWidenEvenInt32x8 ...) => (VPMULDQ256 ...) // pureVreg +(MulWidenEvenUint32x4 ...) => (VPMULUDQ128 ...) // pureVreg +(MulWidenEvenUint32x8 ...) => (VPMULUDQ256 ...) // pureVreg +(NotEqualFloat32x4 x y) => (VCMPPS128 [4] x y) // pureVreg +(NotEqualFloat32x8 x y) => (VCMPPS256 [4] x y) // pureVreg +(NotEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [4] x y)) // maskOut +(NotEqualFloat64x2 x y) => (VCMPPD128 [4] x y) // pureVreg +(NotEqualFloat64x4 x y) => (VCMPPD256 [4] x y) // pureVreg +(NotEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [4] x y)) // maskOut +(NotEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [4] x y)) // maskOut +(NotEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [4] x y)) // maskOut +(NotEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [4] x y)) // maskOut +(NotEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [4] x y)) // maskOut +(NotEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [4] x y)) // maskOut +(NotEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [4] x y)) // maskOut +(NotEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [4] x y)) // maskOut +(NotEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [4] x y)) // maskOut +(OnesCountInt8x16 ...) => (VPOPCNTB128 ...) // pureVreg +(OnesCountInt8x32 ...) => (VPOPCNTB256 ...) // pureVreg +(OnesCountInt8x64 ...) => (VPOPCNTB512 ...) // pureVreg +(OnesCountInt16x8 ...) => (VPOPCNTW128 ...) // pureVreg +(OnesCountInt16x16 ...) => (VPOPCNTW256 ...) // pureVreg +(OnesCountInt16x32 ...) => (VPOPCNTW512 ...) // pureVreg +(OnesCountInt32x4 ...) => (VPOPCNTD128 ...) // pureVreg +(OnesCountInt32x8 ...) => (VPOPCNTD256 ...) // pureVreg +(OnesCountInt32x16 ...) => (VPOPCNTD512 ...) // pureVreg +(OnesCountInt64x2 ...) => (VPOPCNTQ128 ...) // pureVreg +(OnesCountInt64x4 ...) => (VPOPCNTQ256 ...) // pureVreg +(OnesCountInt64x8 ...) => (VPOPCNTQ512 ...) // pureVreg +(OnesCountUint8x16 ...) => (VPOPCNTB128 ...) // pureVreg +(OnesCountUint8x32 ...) => (VPOPCNTB256 ...) // pureVreg +(OnesCountUint8x64 ...) => (VPOPCNTB512 ...) // pureVreg +(OnesCountUint16x8 ...) => (VPOPCNTW128 ...) // pureVreg +(OnesCountUint16x16 ...) => (VPOPCNTW256 ...) // pureVreg +(OnesCountUint16x32 ...) => (VPOPCNTW512 ...) // pureVreg +(OnesCountUint32x4 ...) => (VPOPCNTD128 ...) // pureVreg +(OnesCountUint32x8 ...) => (VPOPCNTD256 ...) // pureVreg +(OnesCountUint32x16 ...) => (VPOPCNTD512 ...) // pureVreg +(OnesCountUint64x2 ...) => (VPOPCNTQ128 ...) // pureVreg +(OnesCountUint64x4 ...) => (VPOPCNTQ256 ...) // pureVreg +(OnesCountUint64x8 ...) => (VPOPCNTQ512 ...) // pureVreg +(OrInt8x16 ...) => (VPOR128 ...) // pureVreg +(OrInt8x32 ...) => (VPOR256 ...) // pureVreg +(OrInt8x64 ...) => (VPORD512 ...) // pureVreg +(OrInt16x8 ...) => (VPOR128 ...) // pureVreg +(OrInt16x16 ...) => (VPOR256 ...) // pureVreg +(OrInt16x32 ...) => (VPORD512 ...) // pureVreg +(OrInt32x4 ...) => (VPOR128 ...) // pureVreg +(OrInt32x8 ...) => (VPOR256 ...) // pureVreg +(OrInt32x16 ...) => (VPORD512 ...) // pureVreg +(OrInt64x2 ...) => (VPOR128 ...) // pureVreg +(OrInt64x4 ...) => (VPOR256 ...) // pureVreg +(OrInt64x8 ...) => (VPORQ512 ...) // pureVreg +(OrUint8x16 ...) => (VPOR128 ...) // pureVreg +(OrUint8x32 ...) => (VPOR256 ...) // pureVreg +(OrUint8x64 ...) => (VPORD512 ...) // pureVreg +(OrUint16x8 ...) => (VPOR128 ...) // pureVreg +(OrUint16x16 ...) => (VPOR256 ...) // pureVreg +(OrUint16x32 ...) => (VPORD512 ...) // pureVreg +(OrUint32x4 ...) => (VPOR128 ...) // pureVreg +(OrUint32x8 ...) => (VPOR256 ...) // pureVreg +(OrUint32x16 ...) => (VPORD512 ...) // pureVreg +(OrUint64x2 ...) => (VPOR128 ...) // pureVreg +(OrUint64x4 ...) => (VPOR256 ...) // pureVreg +(OrUint64x8 ...) => (VPORQ512 ...) // pureVreg +(PermuteFloat32x8 ...) => (VPERMPS256 ...) // pureVreg +(PermuteFloat32x16 ...) => (VPERMPS512 ...) // pureVreg +(PermuteFloat64x4 ...) => (VPERMPD256 ...) // pureVreg +(PermuteFloat64x8 ...) => (VPERMPD512 ...) // pureVreg +(PermuteInt8x16 ...) => (VPERMB128 ...) // pureVreg +(PermuteInt8x32 ...) => (VPERMB256 ...) // pureVreg +(PermuteInt8x64 ...) => (VPERMB512 ...) // pureVreg +(PermuteInt16x8 ...) => (VPERMW128 ...) // pureVreg +(PermuteInt16x16 ...) => (VPERMW256 ...) // pureVreg +(PermuteInt16x32 ...) => (VPERMW512 ...) // pureVreg +(PermuteInt32x8 ...) => (VPERMD256 ...) // pureVreg +(PermuteInt32x16 ...) => (VPERMD512 ...) // pureVreg +(PermuteInt64x4 ...) => (VPERMQ256 ...) // pureVreg +(PermuteInt64x8 ...) => (VPERMQ512 ...) // pureVreg +(PermuteUint8x16 ...) => (VPERMB128 ...) // pureVreg +(PermuteUint8x32 ...) => (VPERMB256 ...) // pureVreg +(PermuteUint8x64 ...) => (VPERMB512 ...) // pureVreg +(PermuteUint16x8 ...) => (VPERMW128 ...) // pureVreg +(PermuteUint16x16 ...) => (VPERMW256 ...) // pureVreg +(PermuteUint16x32 ...) => (VPERMW512 ...) // pureVreg +(PermuteUint32x8 ...) => (VPERMD256 ...) // pureVreg +(PermuteUint32x16 ...) => (VPERMD512 ...) // pureVreg +(PermuteUint64x4 ...) => (VPERMQ256 ...) // pureVreg +(PermuteUint64x8 ...) => (VPERMQ512 ...) // pureVreg +(PermuteOrZeroInt8x16 ...) => (VPSHUFB128 ...) // pureVreg +(PermuteOrZeroUint8x16 ...) => (VPSHUFB128 ...) // pureVreg +(PermuteOrZeroGroupedInt8x32 ...) => (VPSHUFB256 ...) // pureVreg +(PermuteOrZeroGroupedInt8x64 ...) => (VPSHUFB512 ...) // pureVreg +(PermuteOrZeroGroupedUint8x32 ...) => (VPSHUFB256 ...) // pureVreg +(PermuteOrZeroGroupedUint8x64 ...) => (VPSHUFB512 ...) // pureVreg +(ReciprocalFloat32x4 ...) => (VRCPPS128 ...) // pureVreg +(ReciprocalFloat32x8 ...) => (VRCPPS256 ...) // pureVreg +(ReciprocalFloat32x16 ...) => (VRCP14PS512 ...) // pureVreg +(ReciprocalFloat64x2 ...) => (VRCP14PD128 ...) // pureVreg +(ReciprocalFloat64x4 ...) => (VRCP14PD256 ...) // pureVreg +(ReciprocalFloat64x8 ...) => (VRCP14PD512 ...) // pureVreg +(ReciprocalSqrtFloat32x4 ...) => (VRSQRTPS128 ...) // pureVreg +(ReciprocalSqrtFloat32x8 ...) => (VRSQRTPS256 ...) // pureVreg +(ReciprocalSqrtFloat32x16 ...) => (VRSQRT14PS512 ...) // pureVreg +(ReciprocalSqrtFloat64x2 ...) => (VRSQRT14PD128 ...) // pureVreg +(ReciprocalSqrtFloat64x4 ...) => (VRSQRT14PD256 ...) // pureVreg +(ReciprocalSqrtFloat64x8 ...) => (VRSQRT14PD512 ...) // pureVreg +(RotateLeftInt32x4 ...) => (VPROLVD128 ...) // pureVreg +(RotateLeftInt32x8 ...) => (VPROLVD256 ...) // pureVreg +(RotateLeftInt32x16 ...) => (VPROLVD512 ...) // pureVreg +(RotateLeftInt64x2 ...) => (VPROLVQ128 ...) // pureVreg +(RotateLeftInt64x4 ...) => (VPROLVQ256 ...) // pureVreg +(RotateLeftInt64x8 ...) => (VPROLVQ512 ...) // pureVreg +(RotateLeftUint32x4 ...) => (VPROLVD128 ...) // pureVreg +(RotateLeftUint32x8 ...) => (VPROLVD256 ...) // pureVreg +(RotateLeftUint32x16 ...) => (VPROLVD512 ...) // pureVreg +(RotateLeftUint64x2 ...) => (VPROLVQ128 ...) // pureVreg +(RotateLeftUint64x4 ...) => (VPROLVQ256 ...) // pureVreg +(RotateLeftUint64x8 ...) => (VPROLVQ512 ...) // pureVreg +(RotateRightInt32x4 ...) => (VPRORVD128 ...) // pureVreg +(RotateRightInt32x8 ...) => (VPRORVD256 ...) // pureVreg +(RotateRightInt32x16 ...) => (VPRORVD512 ...) // pureVreg +(RotateRightInt64x2 ...) => (VPRORVQ128 ...) // pureVreg +(RotateRightInt64x4 ...) => (VPRORVQ256 ...) // pureVreg +(RotateRightInt64x8 ...) => (VPRORVQ512 ...) // pureVreg +(RotateRightUint32x4 ...) => (VPRORVD128 ...) // pureVreg +(RotateRightUint32x8 ...) => (VPRORVD256 ...) // pureVreg +(RotateRightUint32x16 ...) => (VPRORVD512 ...) // pureVreg +(RotateRightUint64x2 ...) => (VPRORVQ128 ...) // pureVreg +(RotateRightUint64x4 ...) => (VPRORVQ256 ...) // pureVreg +(RotateRightUint64x8 ...) => (VPRORVQ512 ...) // pureVreg +(RoundFloat32x4 x) => (VROUNDPS128 [0] x) // pureVreg +(RoundFloat32x8 x) => (VROUNDPS256 [0] x) // pureVreg +(RoundFloat64x2 x) => (VROUNDPD128 [0] x) // pureVreg +(RoundFloat64x4 x) => (VROUNDPD256 [0] x) // pureVreg +(RoundScaledFloat32x4 [a] x) => (VRNDSCALEPS128 [a+0] x) // pureVreg +(RoundScaledFloat32x8 [a] x) => (VRNDSCALEPS256 [a+0] x) // pureVreg +(RoundScaledFloat32x16 [a] x) => (VRNDSCALEPS512 [a+0] x) // pureVreg +(RoundScaledFloat64x2 [a] x) => (VRNDSCALEPD128 [a+0] x) // pureVreg +(RoundScaledFloat64x4 [a] x) => (VRNDSCALEPD256 [a+0] x) // pureVreg +(RoundScaledFloat64x8 [a] x) => (VRNDSCALEPD512 [a+0] x) // pureVreg +(RoundScaledResidueFloat32x4 [a] x) => (VREDUCEPS128 [a+0] x) // pureVreg +(RoundScaledResidueFloat32x8 [a] x) => (VREDUCEPS256 [a+0] x) // pureVreg +(RoundScaledResidueFloat32x16 [a] x) => (VREDUCEPS512 [a+0] x) // pureVreg +(RoundScaledResidueFloat64x2 [a] x) => (VREDUCEPD128 [a+0] x) // pureVreg +(RoundScaledResidueFloat64x4 [a] x) => (VREDUCEPD256 [a+0] x) // pureVreg +(RoundScaledResidueFloat64x8 [a] x) => (VREDUCEPD512 [a+0] x) // pureVreg +(SHA1FourRoundsUint32x4 ...) => (SHA1RNDS4128 ...) // pureVreg +(SHA1Message1Uint32x4 ...) => (SHA1MSG1128 ...) // pureVreg +(SHA1Message2Uint32x4 ...) => (SHA1MSG2128 ...) // pureVreg +(SHA1NextEUint32x4 ...) => (SHA1NEXTE128 ...) // pureVreg +(SHA256Message1Uint32x4 ...) => (SHA256MSG1128 ...) // pureVreg +(SHA256Message2Uint32x4 ...) => (SHA256MSG2128 ...) // pureVreg +(SHA256TwoRoundsUint32x4 ...) => (SHA256RNDS2128 ...) // pureVreg +(SaturateToInt8Int16x8 ...) => (VPMOVSWB128_128 ...) // pureVreg +(SaturateToInt8Int16x16 ...) => (VPMOVSWB128_256 ...) // pureVreg +(SaturateToInt8Int16x32 ...) => (VPMOVSWB256 ...) // pureVreg +(SaturateToInt8Int32x4 ...) => (VPMOVSDB128_128 ...) // pureVreg +(SaturateToInt8Int32x8 ...) => (VPMOVSDB128_256 ...) // pureVreg +(SaturateToInt8Int32x16 ...) => (VPMOVSDB128_512 ...) // pureVreg +(SaturateToInt8Int64x2 ...) => (VPMOVSQB128_128 ...) // pureVreg +(SaturateToInt8Int64x4 ...) => (VPMOVSQB128_256 ...) // pureVreg +(SaturateToInt8Int64x8 ...) => (VPMOVSQB128_512 ...) // pureVreg +(SaturateToInt16Int32x4 ...) => (VPMOVSDW128_128 ...) // pureVreg +(SaturateToInt16Int32x8 ...) => (VPMOVSDW128_256 ...) // pureVreg +(SaturateToInt16Int32x16 ...) => (VPMOVSDW256 ...) // pureVreg +(SaturateToInt16Int64x2 ...) => (VPMOVSQW128_128 ...) // pureVreg +(SaturateToInt16Int64x4 ...) => (VPMOVSQW128_256 ...) // pureVreg +(SaturateToInt16Int64x8 ...) => (VPMOVSQW128_512 ...) // pureVreg +(SaturateToInt16ConcatInt32x4 ...) => (VPACKSSDW128 ...) // pureVreg +(SaturateToInt16ConcatGroupedInt32x8 ...) => (VPACKSSDW256 ...) // pureVreg +(SaturateToInt16ConcatGroupedInt32x16 ...) => (VPACKSSDW512 ...) // pureVreg +(SaturateToInt32Int64x2 ...) => (VPMOVSQD128_128 ...) // pureVreg +(SaturateToInt32Int64x4 ...) => (VPMOVSQD128_256 ...) // pureVreg +(SaturateToInt32Int64x8 ...) => (VPMOVSQD256 ...) // pureVreg +(SaturateToUint8Uint16x8 ...) => (VPMOVUSWB128_128 ...) // pureVreg +(SaturateToUint8Uint16x16 ...) => (VPMOVUSWB128_256 ...) // pureVreg +(SaturateToUint8Uint16x32 ...) => (VPMOVUSWB256 ...) // pureVreg +(SaturateToUint8Uint32x4 ...) => (VPMOVUSDB128_128 ...) // pureVreg +(SaturateToUint8Uint32x8 ...) => (VPMOVUSDB128_256 ...) // pureVreg +(SaturateToUint8Uint32x16 ...) => (VPMOVUSDB128_512 ...) // pureVreg +(SaturateToUint8Uint64x2 ...) => (VPMOVUSQB128_128 ...) // pureVreg +(SaturateToUint8Uint64x4 ...) => (VPMOVUSQB128_256 ...) // pureVreg +(SaturateToUint8Uint64x8 ...) => (VPMOVUSQB128_512 ...) // pureVreg +(SaturateToUint16Uint32x4 ...) => (VPMOVUSDW128_128 ...) // pureVreg +(SaturateToUint16Uint32x8 ...) => (VPMOVUSDW128_256 ...) // pureVreg +(SaturateToUint16Uint32x16 ...) => (VPMOVUSDW256 ...) // pureVreg +(SaturateToUint16Uint64x2 ...) => (VPMOVUSQW128_128 ...) // pureVreg +(SaturateToUint16Uint64x4 ...) => (VPMOVUSQW128_256 ...) // pureVreg +(SaturateToUint16Uint64x8 ...) => (VPMOVUSQW128_512 ...) // pureVreg +(SaturateToUint16ConcatInt32x4 ...) => (VPACKUSDW128 ...) // pureVreg +(SaturateToUint16ConcatGroupedInt32x8 ...) => (VPACKUSDW256 ...) // pureVreg +(SaturateToUint16ConcatGroupedInt32x16 ...) => (VPACKUSDW512 ...) // pureVreg +(SaturateToUint32Uint64x2 ...) => (VPMOVUSQD128_128 ...) // pureVreg +(SaturateToUint32Uint64x4 ...) => (VPMOVUSQD128_256 ...) // pureVreg +(SaturateToUint32Uint64x8 ...) => (VPMOVUSQD256 ...) // pureVreg +(ScaleFloat32x4 ...) => (VSCALEFPS128 ...) // pureVreg +(ScaleFloat32x8 ...) => (VSCALEFPS256 ...) // pureVreg +(ScaleFloat32x16 ...) => (VSCALEFPS512 ...) // pureVreg +(ScaleFloat64x2 ...) => (VSCALEFPD128 ...) // pureVreg +(ScaleFloat64x4 ...) => (VSCALEFPD256 ...) // pureVreg +(ScaleFloat64x8 ...) => (VSCALEFPD512 ...) // pureVreg +(SetElemFloat32x4 ...) => (VPINSRD128 ...) // pureVreg +(SetElemFloat64x2 ...) => (VPINSRQ128 ...) // pureVreg +(SetElemInt8x16 ...) => (VPINSRB128 ...) // pureVreg +(SetElemInt16x8 ...) => (VPINSRW128 ...) // pureVreg +(SetElemInt32x4 ...) => (VPINSRD128 ...) // pureVreg +(SetElemInt64x2 ...) => (VPINSRQ128 ...) // pureVreg +(SetElemUint8x16 ...) => (VPINSRB128 ...) // pureVreg +(SetElemUint16x8 ...) => (VPINSRW128 ...) // pureVreg +(SetElemUint32x4 ...) => (VPINSRD128 ...) // pureVreg +(SetElemUint64x2 ...) => (VPINSRQ128 ...) // pureVreg +(SetHiFloat32x8 x y) => (VINSERTF128256 [1] x y) // pureVreg +(SetHiFloat32x16 x y) => (VINSERTF64X4512 [1] x y) // pureVreg +(SetHiFloat64x4 x y) => (VINSERTF128256 [1] x y) // pureVreg +(SetHiFloat64x8 x y) => (VINSERTF64X4512 [1] x y) // pureVreg +(SetHiInt8x32 x y) => (VINSERTI128256 [1] x y) // pureVreg +(SetHiInt8x64 x y) => (VINSERTI64X4512 [1] x y) // pureVreg +(SetHiInt16x16 x y) => (VINSERTI128256 [1] x y) // pureVreg +(SetHiInt16x32 x y) => (VINSERTI64X4512 [1] x y) // pureVreg +(SetHiInt32x8 x y) => (VINSERTI128256 [1] x y) // pureVreg +(SetHiInt32x16 x y) => (VINSERTI64X4512 [1] x y) // pureVreg +(SetHiInt64x4 x y) => (VINSERTI128256 [1] x y) // pureVreg +(SetHiInt64x8 x y) => (VINSERTI64X4512 [1] x y) // pureVreg +(SetHiUint8x32 x y) => (VINSERTI128256 [1] x y) // pureVreg +(SetHiUint8x64 x y) => (VINSERTI64X4512 [1] x y) // pureVreg +(SetHiUint16x16 x y) => (VINSERTI128256 [1] x y) // pureVreg +(SetHiUint16x32 x y) => (VINSERTI64X4512 [1] x y) // pureVreg +(SetHiUint32x8 x y) => (VINSERTI128256 [1] x y) // pureVreg +(SetHiUint32x16 x y) => (VINSERTI64X4512 [1] x y) // pureVreg +(SetHiUint64x4 x y) => (VINSERTI128256 [1] x y) // pureVreg +(SetHiUint64x8 x y) => (VINSERTI64X4512 [1] x y) // pureVreg +(SetLoFloat32x8 x y) => (VINSERTF128256 [0] x y) // pureVreg +(SetLoFloat32x16 x y) => (VINSERTF64X4512 [0] x y) // pureVreg +(SetLoFloat64x4 x y) => (VINSERTF128256 [0] x y) // pureVreg +(SetLoFloat64x8 x y) => (VINSERTF64X4512 [0] x y) // pureVreg +(SetLoInt8x32 x y) => (VINSERTI128256 [0] x y) // pureVreg +(SetLoInt8x64 x y) => (VINSERTI64X4512 [0] x y) // pureVreg +(SetLoInt16x16 x y) => (VINSERTI128256 [0] x y) // pureVreg +(SetLoInt16x32 x y) => (VINSERTI64X4512 [0] x y) // pureVreg +(SetLoInt32x8 x y) => (VINSERTI128256 [0] x y) // pureVreg +(SetLoInt32x16 x y) => (VINSERTI64X4512 [0] x y) // pureVreg +(SetLoInt64x4 x y) => (VINSERTI128256 [0] x y) // pureVreg +(SetLoInt64x8 x y) => (VINSERTI64X4512 [0] x y) // pureVreg +(SetLoUint8x32 x y) => (VINSERTI128256 [0] x y) // pureVreg +(SetLoUint8x64 x y) => (VINSERTI64X4512 [0] x y) // pureVreg +(SetLoUint16x16 x y) => (VINSERTI128256 [0] x y) // pureVreg +(SetLoUint16x32 x y) => (VINSERTI64X4512 [0] x y) // pureVreg +(SetLoUint32x8 x y) => (VINSERTI128256 [0] x y) // pureVreg +(SetLoUint32x16 x y) => (VINSERTI64X4512 [0] x y) // pureVreg +(SetLoUint64x4 x y) => (VINSERTI128256 [0] x y) // pureVreg +(SetLoUint64x8 x y) => (VINSERTI64X4512 [0] x y) // pureVreg +(ShiftAllLeftInt16x8 ...) => (VPSLLW128 ...) // pureVreg +(VPSLLW128 x (MOVQconst [c])) => (VPSLLW128const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllLeftInt16x16 ...) => (VPSLLW256 ...) // pureVreg +(VPSLLW256 x (MOVQconst [c])) => (VPSLLW256const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllLeftInt16x32 ...) => (VPSLLW512 ...) // pureVreg +(VPSLLW512 x (MOVQconst [c])) => (VPSLLW512const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllLeftInt32x4 ...) => (VPSLLD128 ...) // pureVreg +(VPSLLD128 x (MOVQconst [c])) => (VPSLLD128const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllLeftInt32x8 ...) => (VPSLLD256 ...) // pureVreg +(VPSLLD256 x (MOVQconst [c])) => (VPSLLD256const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllLeftInt32x16 ...) => (VPSLLD512 ...) // pureVreg +(VPSLLD512 x (MOVQconst [c])) => (VPSLLD512const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllLeftInt64x2 ...) => (VPSLLQ128 ...) // pureVreg +(VPSLLQ128 x (MOVQconst [c])) => (VPSLLQ128const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllLeftInt64x4 ...) => (VPSLLQ256 ...) // pureVreg +(VPSLLQ256 x (MOVQconst [c])) => (VPSLLQ256const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllLeftInt64x8 ...) => (VPSLLQ512 ...) // pureVreg +(VPSLLQ512 x (MOVQconst [c])) => (VPSLLQ512const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllLeftUint16x8 ...) => (VPSLLW128 ...) // pureVreg +(ShiftAllLeftUint16x16 ...) => (VPSLLW256 ...) // pureVreg +(ShiftAllLeftUint16x32 ...) => (VPSLLW512 ...) // pureVreg +(ShiftAllLeftUint32x4 ...) => (VPSLLD128 ...) // pureVreg +(ShiftAllLeftUint32x8 ...) => (VPSLLD256 ...) // pureVreg +(ShiftAllLeftUint32x16 ...) => (VPSLLD512 ...) // pureVreg +(ShiftAllLeftUint64x2 ...) => (VPSLLQ128 ...) // pureVreg +(ShiftAllLeftUint64x4 ...) => (VPSLLQ256 ...) // pureVreg +(ShiftAllLeftUint64x8 ...) => (VPSLLQ512 ...) // pureVreg +(ShiftAllLeftConcatMod16Int16x8 ...) => (VPSHLDW128 ...) // pureVreg +(ShiftAllLeftConcatMod16Int16x16 ...) => (VPSHLDW256 ...) // pureVreg +(ShiftAllLeftConcatMod16Int16x32 ...) => (VPSHLDW512 ...) // pureVreg +(ShiftAllLeftConcatMod16Uint16x8 ...) => (VPSHLDW128 ...) // pureVreg +(ShiftAllLeftConcatMod16Uint16x16 ...) => (VPSHLDW256 ...) // pureVreg +(ShiftAllLeftConcatMod16Uint16x32 ...) => (VPSHLDW512 ...) // pureVreg +(ShiftAllLeftConcatMod32Int32x4 ...) => (VPSHLDD128 ...) // pureVreg +(ShiftAllLeftConcatMod32Int32x8 ...) => (VPSHLDD256 ...) // pureVreg +(ShiftAllLeftConcatMod32Int32x16 ...) => (VPSHLDD512 ...) // pureVreg +(ShiftAllLeftConcatMod32Uint32x4 ...) => (VPSHLDD128 ...) // pureVreg +(ShiftAllLeftConcatMod32Uint32x8 ...) => (VPSHLDD256 ...) // pureVreg +(ShiftAllLeftConcatMod32Uint32x16 ...) => (VPSHLDD512 ...) // pureVreg +(ShiftAllLeftConcatMod64Int64x2 ...) => (VPSHLDQ128 ...) // pureVreg +(ShiftAllLeftConcatMod64Int64x4 ...) => (VPSHLDQ256 ...) // pureVreg +(ShiftAllLeftConcatMod64Int64x8 ...) => (VPSHLDQ512 ...) // pureVreg +(ShiftAllLeftConcatMod64Uint64x2 ...) => (VPSHLDQ128 ...) // pureVreg +(ShiftAllLeftConcatMod64Uint64x4 ...) => (VPSHLDQ256 ...) // pureVreg +(ShiftAllLeftConcatMod64Uint64x8 ...) => (VPSHLDQ512 ...) // pureVreg +(VPSLLWMasked128 x (MOVQconst [c]) mask) => (VPSLLWMasked128const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSLLWMasked256 x (MOVQconst [c]) mask) => (VPSLLWMasked256const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSLLWMasked512 x (MOVQconst [c]) mask) => (VPSLLWMasked512const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSLLDMasked128 x (MOVQconst [c]) mask) => (VPSLLDMasked128const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSLLDMasked256 x (MOVQconst [c]) mask) => (VPSLLDMasked256const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSLLDMasked512 x (MOVQconst [c]) mask) => (VPSLLDMasked512const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSLLQMasked128 x (MOVQconst [c]) mask) => (VPSLLQMasked128const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSLLQMasked256 x (MOVQconst [c]) mask) => (VPSLLQMasked256const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSLLQMasked512 x (MOVQconst [c]) mask) => (VPSLLQMasked512const [amd64CapAVXShift(c)] x mask) // masksftimm +(ShiftAllRightInt16x8 ...) => (VPSRAW128 ...) // pureVreg +(VPSRAW128 x (MOVQconst [c])) => (VPSRAW128const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightInt16x16 ...) => (VPSRAW256 ...) // pureVreg +(VPSRAW256 x (MOVQconst [c])) => (VPSRAW256const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightInt16x32 ...) => (VPSRAW512 ...) // pureVreg +(VPSRAW512 x (MOVQconst [c])) => (VPSRAW512const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightInt32x4 ...) => (VPSRAD128 ...) // pureVreg +(VPSRAD128 x (MOVQconst [c])) => (VPSRAD128const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightInt32x8 ...) => (VPSRAD256 ...) // pureVreg +(VPSRAD256 x (MOVQconst [c])) => (VPSRAD256const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightInt32x16 ...) => (VPSRAD512 ...) // pureVreg +(VPSRAD512 x (MOVQconst [c])) => (VPSRAD512const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightInt64x2 ...) => (VPSRAQ128 ...) // pureVreg +(VPSRAQ128 x (MOVQconst [c])) => (VPSRAQ128const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightInt64x4 ...) => (VPSRAQ256 ...) // pureVreg +(VPSRAQ256 x (MOVQconst [c])) => (VPSRAQ256const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightInt64x8 ...) => (VPSRAQ512 ...) // pureVreg +(VPSRAQ512 x (MOVQconst [c])) => (VPSRAQ512const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightUint16x8 ...) => (VPSRLW128 ...) // pureVreg +(VPSRLW128 x (MOVQconst [c])) => (VPSRLW128const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightUint16x16 ...) => (VPSRLW256 ...) // pureVreg +(VPSRLW256 x (MOVQconst [c])) => (VPSRLW256const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightUint16x32 ...) => (VPSRLW512 ...) // pureVreg +(VPSRLW512 x (MOVQconst [c])) => (VPSRLW512const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightUint32x4 ...) => (VPSRLD128 ...) // pureVreg +(VPSRLD128 x (MOVQconst [c])) => (VPSRLD128const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightUint32x8 ...) => (VPSRLD256 ...) // pureVreg +(VPSRLD256 x (MOVQconst [c])) => (VPSRLD256const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightUint32x16 ...) => (VPSRLD512 ...) // pureVreg +(VPSRLD512 x (MOVQconst [c])) => (VPSRLD512const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightUint64x2 ...) => (VPSRLQ128 ...) // pureVreg +(VPSRLQ128 x (MOVQconst [c])) => (VPSRLQ128const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightUint64x4 ...) => (VPSRLQ256 ...) // pureVreg +(VPSRLQ256 x (MOVQconst [c])) => (VPSRLQ256const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightUint64x8 ...) => (VPSRLQ512 ...) // pureVreg +(VPSRLQ512 x (MOVQconst [c])) => (VPSRLQ512const [amd64CapAVXShift(c)] x) // sftimm +(ShiftAllRightConcatMod16Int16x8 ...) => (VPSHRDW128 ...) // pureVreg +(ShiftAllRightConcatMod16Int16x16 ...) => (VPSHRDW256 ...) // pureVreg +(ShiftAllRightConcatMod16Int16x32 ...) => (VPSHRDW512 ...) // pureVreg +(ShiftAllRightConcatMod16Uint16x8 ...) => (VPSHRDW128 ...) // pureVreg +(ShiftAllRightConcatMod16Uint16x16 ...) => (VPSHRDW256 ...) // pureVreg +(ShiftAllRightConcatMod16Uint16x32 ...) => (VPSHRDW512 ...) // pureVreg +(ShiftAllRightConcatMod32Int32x4 ...) => (VPSHRDD128 ...) // pureVreg +(ShiftAllRightConcatMod32Int32x8 ...) => (VPSHRDD256 ...) // pureVreg +(ShiftAllRightConcatMod32Int32x16 ...) => (VPSHRDD512 ...) // pureVreg +(ShiftAllRightConcatMod32Uint32x4 ...) => (VPSHRDD128 ...) // pureVreg +(ShiftAllRightConcatMod32Uint32x8 ...) => (VPSHRDD256 ...) // pureVreg +(ShiftAllRightConcatMod32Uint32x16 ...) => (VPSHRDD512 ...) // pureVreg +(ShiftAllRightConcatMod64Int64x2 ...) => (VPSHRDQ128 ...) // pureVreg +(ShiftAllRightConcatMod64Int64x4 ...) => (VPSHRDQ256 ...) // pureVreg +(ShiftAllRightConcatMod64Int64x8 ...) => (VPSHRDQ512 ...) // pureVreg +(ShiftAllRightConcatMod64Uint64x2 ...) => (VPSHRDQ128 ...) // pureVreg +(ShiftAllRightConcatMod64Uint64x4 ...) => (VPSHRDQ256 ...) // pureVreg +(ShiftAllRightConcatMod64Uint64x8 ...) => (VPSHRDQ512 ...) // pureVreg +(VPSRAWMasked128 x (MOVQconst [c]) mask) => (VPSRAWMasked128const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRAWMasked256 x (MOVQconst [c]) mask) => (VPSRAWMasked256const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRAWMasked512 x (MOVQconst [c]) mask) => (VPSRAWMasked512const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRADMasked128 x (MOVQconst [c]) mask) => (VPSRADMasked128const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRADMasked256 x (MOVQconst [c]) mask) => (VPSRADMasked256const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRADMasked512 x (MOVQconst [c]) mask) => (VPSRADMasked512const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRAQMasked128 x (MOVQconst [c]) mask) => (VPSRAQMasked128const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRAQMasked256 x (MOVQconst [c]) mask) => (VPSRAQMasked256const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRAQMasked512 x (MOVQconst [c]) mask) => (VPSRAQMasked512const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRLWMasked128 x (MOVQconst [c]) mask) => (VPSRLWMasked128const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRLWMasked256 x (MOVQconst [c]) mask) => (VPSRLWMasked256const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRLWMasked512 x (MOVQconst [c]) mask) => (VPSRLWMasked512const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRLDMasked128 x (MOVQconst [c]) mask) => (VPSRLDMasked128const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRLDMasked256 x (MOVQconst [c]) mask) => (VPSRLDMasked256const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRLDMasked512 x (MOVQconst [c]) mask) => (VPSRLDMasked512const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRLQMasked128 x (MOVQconst [c]) mask) => (VPSRLQMasked128const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRLQMasked256 x (MOVQconst [c]) mask) => (VPSRLQMasked256const [amd64CapAVXShift(c)] x mask) // masksftimm +(VPSRLQMasked512 x (MOVQconst [c]) mask) => (VPSRLQMasked512const [amd64CapAVXShift(c)] x mask) // masksftimm +(ShiftLeftInt16x8 ...) => (VPSLLVW128 ...) // pureVreg +(ShiftLeftInt16x16 ...) => (VPSLLVW256 ...) // pureVreg +(ShiftLeftInt16x32 ...) => (VPSLLVW512 ...) // pureVreg +(ShiftLeftInt32x4 ...) => (VPSLLVD128 ...) // pureVreg +(ShiftLeftInt32x8 ...) => (VPSLLVD256 ...) // pureVreg +(ShiftLeftInt32x16 ...) => (VPSLLVD512 ...) // pureVreg +(ShiftLeftInt64x2 ...) => (VPSLLVQ128 ...) // pureVreg +(ShiftLeftInt64x4 ...) => (VPSLLVQ256 ...) // pureVreg +(ShiftLeftInt64x8 ...) => (VPSLLVQ512 ...) // pureVreg +(ShiftLeftUint16x8 ...) => (VPSLLVW128 ...) // pureVreg +(ShiftLeftUint16x16 ...) => (VPSLLVW256 ...) // pureVreg +(ShiftLeftUint16x32 ...) => (VPSLLVW512 ...) // pureVreg +(ShiftLeftUint32x4 ...) => (VPSLLVD128 ...) // pureVreg +(ShiftLeftUint32x8 ...) => (VPSLLVD256 ...) // pureVreg +(ShiftLeftUint32x16 ...) => (VPSLLVD512 ...) // pureVreg +(ShiftLeftUint64x2 ...) => (VPSLLVQ128 ...) // pureVreg +(ShiftLeftUint64x4 ...) => (VPSLLVQ256 ...) // pureVreg +(ShiftLeftUint64x8 ...) => (VPSLLVQ512 ...) // pureVreg +(ShiftLeftConcatMod16Int16x8 ...) => (VPSHLDVW128 ...) // pureVreg +(ShiftLeftConcatMod16Int16x16 ...) => (VPSHLDVW256 ...) // pureVreg +(ShiftLeftConcatMod16Int16x32 ...) => (VPSHLDVW512 ...) // pureVreg +(ShiftLeftConcatMod16Uint16x8 ...) => (VPSHLDVW128 ...) // pureVreg +(ShiftLeftConcatMod16Uint16x16 ...) => (VPSHLDVW256 ...) // pureVreg +(ShiftLeftConcatMod16Uint16x32 ...) => (VPSHLDVW512 ...) // pureVreg +(ShiftLeftConcatMod32Int32x4 ...) => (VPSHLDVD128 ...) // pureVreg +(ShiftLeftConcatMod32Int32x8 ...) => (VPSHLDVD256 ...) // pureVreg +(ShiftLeftConcatMod32Int32x16 ...) => (VPSHLDVD512 ...) // pureVreg +(ShiftLeftConcatMod32Uint32x4 ...) => (VPSHLDVD128 ...) // pureVreg +(ShiftLeftConcatMod32Uint32x8 ...) => (VPSHLDVD256 ...) // pureVreg +(ShiftLeftConcatMod32Uint32x16 ...) => (VPSHLDVD512 ...) // pureVreg +(ShiftLeftConcatMod64Int64x2 ...) => (VPSHLDVQ128 ...) // pureVreg +(ShiftLeftConcatMod64Int64x4 ...) => (VPSHLDVQ256 ...) // pureVreg +(ShiftLeftConcatMod64Int64x8 ...) => (VPSHLDVQ512 ...) // pureVreg +(ShiftLeftConcatMod64Uint64x2 ...) => (VPSHLDVQ128 ...) // pureVreg +(ShiftLeftConcatMod64Uint64x4 ...) => (VPSHLDVQ256 ...) // pureVreg +(ShiftLeftConcatMod64Uint64x8 ...) => (VPSHLDVQ512 ...) // pureVreg +(ShiftRightInt16x8 ...) => (VPSRAVW128 ...) // pureVreg +(ShiftRightInt16x16 ...) => (VPSRAVW256 ...) // pureVreg +(ShiftRightInt16x32 ...) => (VPSRAVW512 ...) // pureVreg +(ShiftRightInt32x4 ...) => (VPSRAVD128 ...) // pureVreg +(ShiftRightInt32x8 ...) => (VPSRAVD256 ...) // pureVreg +(ShiftRightInt32x16 ...) => (VPSRAVD512 ...) // pureVreg +(ShiftRightInt64x2 ...) => (VPSRAVQ128 ...) // pureVreg +(ShiftRightInt64x4 ...) => (VPSRAVQ256 ...) // pureVreg +(ShiftRightInt64x8 ...) => (VPSRAVQ512 ...) // pureVreg +(ShiftRightUint16x8 ...) => (VPSRLVW128 ...) // pureVreg +(ShiftRightUint16x16 ...) => (VPSRLVW256 ...) // pureVreg +(ShiftRightUint16x32 ...) => (VPSRLVW512 ...) // pureVreg +(ShiftRightUint32x4 ...) => (VPSRLVD128 ...) // pureVreg +(ShiftRightUint32x8 ...) => (VPSRLVD256 ...) // pureVreg +(ShiftRightUint32x16 ...) => (VPSRLVD512 ...) // pureVreg +(ShiftRightUint64x2 ...) => (VPSRLVQ128 ...) // pureVreg +(ShiftRightUint64x4 ...) => (VPSRLVQ256 ...) // pureVreg +(ShiftRightUint64x8 ...) => (VPSRLVQ512 ...) // pureVreg +(ShiftRightConcatMod16Int16x8 ...) => (VPSHRDVW128 ...) // pureVreg +(ShiftRightConcatMod16Int16x16 ...) => (VPSHRDVW256 ...) // pureVreg +(ShiftRightConcatMod16Int16x32 ...) => (VPSHRDVW512 ...) // pureVreg +(ShiftRightConcatMod16Uint16x8 ...) => (VPSHRDVW128 ...) // pureVreg +(ShiftRightConcatMod16Uint16x16 ...) => (VPSHRDVW256 ...) // pureVreg +(ShiftRightConcatMod16Uint16x32 ...) => (VPSHRDVW512 ...) // pureVreg +(ShiftRightConcatMod32Int32x4 ...) => (VPSHRDVD128 ...) // pureVreg +(ShiftRightConcatMod32Int32x8 ...) => (VPSHRDVD256 ...) // pureVreg +(ShiftRightConcatMod32Int32x16 ...) => (VPSHRDVD512 ...) // pureVreg +(ShiftRightConcatMod32Uint32x4 ...) => (VPSHRDVD128 ...) // pureVreg +(ShiftRightConcatMod32Uint32x8 ...) => (VPSHRDVD256 ...) // pureVreg +(ShiftRightConcatMod32Uint32x16 ...) => (VPSHRDVD512 ...) // pureVreg +(ShiftRightConcatMod64Int64x2 ...) => (VPSHRDVQ128 ...) // pureVreg +(ShiftRightConcatMod64Int64x4 ...) => (VPSHRDVQ256 ...) // pureVreg +(ShiftRightConcatMod64Int64x8 ...) => (VPSHRDVQ512 ...) // pureVreg +(ShiftRightConcatMod64Uint64x2 ...) => (VPSHRDVQ128 ...) // pureVreg +(ShiftRightConcatMod64Uint64x4 ...) => (VPSHRDVQ256 ...) // pureVreg +(ShiftRightConcatMod64Uint64x8 ...) => (VPSHRDVQ512 ...) // pureVreg +(SqrtFloat32x4 ...) => (VSQRTPS128 ...) // pureVreg +(SqrtFloat32x8 ...) => (VSQRTPS256 ...) // pureVreg +(SqrtFloat32x16 ...) => (VSQRTPS512 ...) // pureVreg +(SqrtFloat64x2 ...) => (VSQRTPD128 ...) // pureVreg +(SqrtFloat64x4 ...) => (VSQRTPD256 ...) // pureVreg +(SqrtFloat64x8 ...) => (VSQRTPD512 ...) // pureVreg +(SubFloat32x4 ...) => (VSUBPS128 ...) // pureVreg +(SubFloat32x8 ...) => (VSUBPS256 ...) // pureVreg +(SubFloat32x16 ...) => (VSUBPS512 ...) // pureVreg +(SubFloat64x2 ...) => (VSUBPD128 ...) // pureVreg +(SubFloat64x4 ...) => (VSUBPD256 ...) // pureVreg +(SubFloat64x8 ...) => (VSUBPD512 ...) // pureVreg +(SubInt8x16 ...) => (VPSUBB128 ...) // pureVreg +(SubInt8x32 ...) => (VPSUBB256 ...) // pureVreg +(SubInt8x64 ...) => (VPSUBB512 ...) // pureVreg +(SubInt16x8 ...) => (VPSUBW128 ...) // pureVreg +(SubInt16x16 ...) => (VPSUBW256 ...) // pureVreg +(SubInt16x32 ...) => (VPSUBW512 ...) // pureVreg +(SubInt32x4 ...) => (VPSUBD128 ...) // pureVreg +(SubInt32x8 ...) => (VPSUBD256 ...) // pureVreg +(SubInt32x16 ...) => (VPSUBD512 ...) // pureVreg +(SubInt64x2 ...) => (VPSUBQ128 ...) // pureVreg +(SubInt64x4 ...) => (VPSUBQ256 ...) // pureVreg +(SubInt64x8 ...) => (VPSUBQ512 ...) // pureVreg +(SubUint8x16 ...) => (VPSUBB128 ...) // pureVreg +(SubUint8x32 ...) => (VPSUBB256 ...) // pureVreg +(SubUint8x64 ...) => (VPSUBB512 ...) // pureVreg +(SubUint16x8 ...) => (VPSUBW128 ...) // pureVreg +(SubUint16x16 ...) => (VPSUBW256 ...) // pureVreg +(SubUint16x32 ...) => (VPSUBW512 ...) // pureVreg +(SubUint32x4 ...) => (VPSUBD128 ...) // pureVreg +(SubUint32x8 ...) => (VPSUBD256 ...) // pureVreg +(SubUint32x16 ...) => (VPSUBD512 ...) // pureVreg +(SubUint64x2 ...) => (VPSUBQ128 ...) // pureVreg +(SubUint64x4 ...) => (VPSUBQ256 ...) // pureVreg +(SubUint64x8 ...) => (VPSUBQ512 ...) // pureVreg +(SubSaturatedInt8x16 ...) => (VPSUBSB128 ...) // pureVreg +(SubSaturatedInt8x32 ...) => (VPSUBSB256 ...) // pureVreg +(SubSaturatedInt8x64 ...) => (VPSUBSB512 ...) // pureVreg +(SubSaturatedInt16x8 ...) => (VPSUBSW128 ...) // pureVreg +(SubSaturatedInt16x16 ...) => (VPSUBSW256 ...) // pureVreg +(SubSaturatedInt16x32 ...) => (VPSUBSW512 ...) // pureVreg +(SubSaturatedUint8x16 ...) => (VPSUBUSB128 ...) // pureVreg +(SubSaturatedUint8x32 ...) => (VPSUBUSB256 ...) // pureVreg +(SubSaturatedUint8x64 ...) => (VPSUBUSB512 ...) // pureVreg +(SubSaturatedUint16x8 ...) => (VPSUBUSW128 ...) // pureVreg +(SubSaturatedUint16x16 ...) => (VPSUBUSW256 ...) // pureVreg +(SubSaturatedUint16x32 ...) => (VPSUBUSW512 ...) // pureVreg +(SumOf8AbsDiffUint8x16 ...) => (VPSADBW128 ...) // pureVreg +(SumOf8AbsDiffUint8x32 ...) => (VPSADBW256 ...) // pureVreg +(SumOf8AbsDiffUint8x64 ...) => (VPSADBW512 ...) // pureVreg +(TruncFloat32x4 x) => (VROUNDPS128 [3] x) // pureVreg +(TruncFloat32x8 x) => (VROUNDPS256 [3] x) // pureVreg +(TruncFloat64x2 x) => (VROUNDPD128 [3] x) // pureVreg +(TruncFloat64x4 x) => (VROUNDPD256 [3] x) // pureVreg +(TruncScaledFloat32x4 [a] x) => (VRNDSCALEPS128 [a+3] x) // pureVreg +(TruncScaledFloat32x8 [a] x) => (VRNDSCALEPS256 [a+3] x) // pureVreg +(TruncScaledFloat32x16 [a] x) => (VRNDSCALEPS512 [a+3] x) // pureVreg +(TruncScaledFloat64x2 [a] x) => (VRNDSCALEPD128 [a+3] x) // pureVreg +(TruncScaledFloat64x4 [a] x) => (VRNDSCALEPD256 [a+3] x) // pureVreg +(TruncScaledFloat64x8 [a] x) => (VRNDSCALEPD512 [a+3] x) // pureVreg +(TruncScaledResidueFloat32x4 [a] x) => (VREDUCEPS128 [a+3] x) // pureVreg +(TruncScaledResidueFloat32x8 [a] x) => (VREDUCEPS256 [a+3] x) // pureVreg +(TruncScaledResidueFloat32x16 [a] x) => (VREDUCEPS512 [a+3] x) // pureVreg +(TruncScaledResidueFloat64x2 [a] x) => (VREDUCEPD128 [a+3] x) // pureVreg +(TruncScaledResidueFloat64x4 [a] x) => (VREDUCEPD256 [a+3] x) // pureVreg +(TruncScaledResidueFloat64x8 [a] x) => (VREDUCEPD512 [a+3] x) // pureVreg +(TruncToInt8Int16x8 ...) => (VPMOVWB128_128 ...) // pureVreg +(TruncToInt8Int16x16 ...) => (VPMOVWB128_256 ...) // pureVreg +(TruncToInt8Int16x32 ...) => (VPMOVWB256 ...) // pureVreg +(TruncToInt8Int32x4 ...) => (VPMOVDB128_128 ...) // pureVreg +(TruncToInt8Int32x8 ...) => (VPMOVDB128_256 ...) // pureVreg +(TruncToInt8Int32x16 ...) => (VPMOVDB128_512 ...) // pureVreg +(TruncToInt8Int64x2 ...) => (VPMOVQB128_128 ...) // pureVreg +(TruncToInt8Int64x4 ...) => (VPMOVQB128_256 ...) // pureVreg +(TruncToInt8Int64x8 ...) => (VPMOVQB128_512 ...) // pureVreg +(TruncToInt16Int32x4 ...) => (VPMOVDW128_128 ...) // pureVreg +(TruncToInt16Int32x8 ...) => (VPMOVDW128_256 ...) // pureVreg +(TruncToInt16Int32x16 ...) => (VPMOVDW256 ...) // pureVreg +(TruncToInt16Int64x2 ...) => (VPMOVQW128_128 ...) // pureVreg +(TruncToInt16Int64x4 ...) => (VPMOVQW128_256 ...) // pureVreg +(TruncToInt16Int64x8 ...) => (VPMOVQW128_512 ...) // pureVreg +(TruncToInt32Int64x2 ...) => (VPMOVQD128_128 ...) // pureVreg +(TruncToInt32Int64x4 ...) => (VPMOVQD128_256 ...) // pureVreg +(TruncToInt32Int64x8 ...) => (VPMOVQD256 ...) // pureVreg +(TruncToUint8Uint16x8 ...) => (VPMOVWB128_128 ...) // pureVreg +(TruncToUint8Uint16x16 ...) => (VPMOVWB128_256 ...) // pureVreg +(TruncToUint8Uint16x32 ...) => (VPMOVWB256 ...) // pureVreg +(TruncToUint8Uint32x4 ...) => (VPMOVDB128_128 ...) // pureVreg +(TruncToUint8Uint32x8 ...) => (VPMOVDB128_256 ...) // pureVreg +(TruncToUint8Uint32x16 ...) => (VPMOVDB128_512 ...) // pureVreg +(TruncToUint8Uint64x2 ...) => (VPMOVQB128_128 ...) // pureVreg +(TruncToUint8Uint64x4 ...) => (VPMOVQB128_256 ...) // pureVreg +(TruncToUint8Uint64x8 ...) => (VPMOVQB128_512 ...) // pureVreg +(TruncToUint16Uint32x4 ...) => (VPMOVDW128_128 ...) // pureVreg +(TruncToUint16Uint32x8 ...) => (VPMOVDW128_256 ...) // pureVreg +(TruncToUint16Uint32x16 ...) => (VPMOVDW256 ...) // pureVreg +(TruncToUint16Uint64x2 ...) => (VPMOVQW128_128 ...) // pureVreg +(TruncToUint16Uint64x4 ...) => (VPMOVQW128_256 ...) // pureVreg +(TruncToUint16Uint64x8 ...) => (VPMOVQW128_512 ...) // pureVreg +(TruncToUint32Uint64x2 ...) => (VPMOVQD128_128 ...) // pureVreg +(TruncToUint32Uint64x4 ...) => (VPMOVQD128_256 ...) // pureVreg +(TruncToUint32Uint64x8 ...) => (VPMOVQD256 ...) // pureVreg +(XorInt8x16 ...) => (VPXOR128 ...) // pureVreg +(XorInt8x32 ...) => (VPXOR256 ...) // pureVreg +(XorInt8x64 ...) => (VPXORD512 ...) // pureVreg +(XorInt16x8 ...) => (VPXOR128 ...) // pureVreg +(XorInt16x16 ...) => (VPXOR256 ...) // pureVreg +(XorInt16x32 ...) => (VPXORD512 ...) // pureVreg +(XorInt32x4 ...) => (VPXOR128 ...) // pureVreg +(XorInt32x8 ...) => (VPXOR256 ...) // pureVreg +(XorInt32x16 ...) => (VPXORD512 ...) // pureVreg +(XorInt64x2 ...) => (VPXOR128 ...) // pureVreg +(XorInt64x4 ...) => (VPXOR256 ...) // pureVreg +(XorInt64x8 ...) => (VPXORQ512 ...) // pureVreg +(XorUint8x16 ...) => (VPXOR128 ...) // pureVreg +(XorUint8x32 ...) => (VPXOR256 ...) // pureVreg +(XorUint8x64 ...) => (VPXORD512 ...) // pureVreg +(XorUint16x8 ...) => (VPXOR128 ...) // pureVreg +(XorUint16x16 ...) => (VPXOR256 ...) // pureVreg +(XorUint16x32 ...) => (VPXORD512 ...) // pureVreg +(XorUint32x4 ...) => (VPXOR128 ...) // pureVreg +(XorUint32x8 ...) => (VPXOR256 ...) // pureVreg +(XorUint32x16 ...) => (VPXORD512 ...) // pureVreg +(XorUint64x2 ...) => (VPXOR128 ...) // pureVreg +(XorUint64x4 ...) => (VPXOR256 ...) // pureVreg +(XorUint64x8 ...) => (VPXORQ512 ...) // pureVreg +(blendInt8x16 ...) => (VPBLENDVB128 ...) // pureVreg +(blendInt8x32 ...) => (VPBLENDVB256 ...) // pureVreg +(blendMaskedInt8x64 x y mask) => (VPBLENDMBMasked512 x y (VPMOVVec8x64ToM mask)) // maskIn +(blendMaskedInt16x32 x y mask) => (VPBLENDMWMasked512 x y (VPMOVVec16x32ToM mask)) // maskIn +(blendMaskedInt32x16 x y mask) => (VPBLENDMDMasked512 x y (VPMOVVec32x16ToM mask)) // maskIn +(blendMaskedInt64x8 x y mask) => (VPBLENDMQMasked512 x y (VPMOVVec64x8ToM mask)) // maskIn +(broadcast1To2Float64x2 ...) => (VPBROADCASTQ128 ...) // pureVreg +(broadcast1To2Int64x2 ...) => (VPBROADCASTQ128 ...) // pureVreg +(broadcast1To2Uint64x2 ...) => (VPBROADCASTQ128 ...) // pureVreg +(broadcast1To2MaskedFloat64x2 x mask) => (VPBROADCASTQMasked128 x (VPMOVVec64x2ToM mask)) // maskIn +(broadcast1To2MaskedInt64x2 x mask) => (VPBROADCASTQMasked128 x (VPMOVVec64x2ToM mask)) // maskIn +(broadcast1To2MaskedUint64x2 x mask) => (VPBROADCASTQMasked128 x (VPMOVVec64x2ToM mask)) // maskIn +(broadcast1To4Float32x4 ...) => (VBROADCASTSS128 ...) // pureVreg +(broadcast1To4Float64x2 ...) => (VBROADCASTSD256 ...) // pureVreg +(broadcast1To4Int32x4 ...) => (VPBROADCASTD128 ...) // pureVreg +(broadcast1To4Int64x2 ...) => (VPBROADCASTQ256 ...) // pureVreg +(broadcast1To4Uint32x4 ...) => (VPBROADCASTD128 ...) // pureVreg +(broadcast1To4Uint64x2 ...) => (VPBROADCASTQ256 ...) // pureVreg +(broadcast1To4MaskedFloat32x4 x mask) => (VBROADCASTSSMasked128 x (VPMOVVec32x4ToM mask)) // maskIn +(broadcast1To4MaskedFloat64x2 x mask) => (VBROADCASTSDMasked256 x (VPMOVVec64x2ToM mask)) // maskIn +(broadcast1To4MaskedInt32x4 x mask) => (VPBROADCASTDMasked128 x (VPMOVVec32x4ToM mask)) // maskIn +(broadcast1To4MaskedInt64x2 x mask) => (VPBROADCASTQMasked256 x (VPMOVVec64x2ToM mask)) // maskIn +(broadcast1To4MaskedUint32x4 x mask) => (VPBROADCASTDMasked128 x (VPMOVVec32x4ToM mask)) // maskIn +(broadcast1To4MaskedUint64x2 x mask) => (VPBROADCASTQMasked256 x (VPMOVVec64x2ToM mask)) // maskIn +(broadcast1To8Float32x4 ...) => (VBROADCASTSS256 ...) // pureVreg +(broadcast1To8Float64x2 ...) => (VBROADCASTSD512 ...) // pureVreg +(broadcast1To8Int16x8 ...) => (VPBROADCASTW128 ...) // pureVreg +(broadcast1To8Int32x4 ...) => (VPBROADCASTD256 ...) // pureVreg +(broadcast1To8Int64x2 ...) => (VPBROADCASTQ512 ...) // pureVreg +(broadcast1To8Uint16x8 ...) => (VPBROADCASTW128 ...) // pureVreg +(broadcast1To8Uint32x4 ...) => (VPBROADCASTD256 ...) // pureVreg +(broadcast1To8Uint64x2 ...) => (VPBROADCASTQ512 ...) // pureVreg +(broadcast1To8MaskedFloat32x4 x mask) => (VBROADCASTSSMasked256 x (VPMOVVec32x4ToM mask)) // maskIn +(broadcast1To8MaskedFloat64x2 x mask) => (VBROADCASTSDMasked512 x (VPMOVVec64x2ToM mask)) // maskIn +(broadcast1To8MaskedInt16x8 x mask) => (VPBROADCASTWMasked128 x (VPMOVVec16x8ToM mask)) // maskIn +(broadcast1To8MaskedInt32x4 x mask) => (VPBROADCASTDMasked256 x (VPMOVVec32x4ToM mask)) // maskIn +(broadcast1To8MaskedInt64x2 x mask) => (VPBROADCASTQMasked512 x (VPMOVVec64x2ToM mask)) // maskIn +(broadcast1To8MaskedUint16x8 x mask) => (VPBROADCASTWMasked128 x (VPMOVVec16x8ToM mask)) // maskIn +(broadcast1To8MaskedUint32x4 x mask) => (VPBROADCASTDMasked256 x (VPMOVVec32x4ToM mask)) // maskIn +(broadcast1To8MaskedUint64x2 x mask) => (VPBROADCASTQMasked512 x (VPMOVVec64x2ToM mask)) // maskIn +(broadcast1To16Float32x4 ...) => (VBROADCASTSS512 ...) // pureVreg +(broadcast1To16Int8x16 ...) => (VPBROADCASTB128 ...) // pureVreg +(broadcast1To16Int16x8 ...) => (VPBROADCASTW256 ...) // pureVreg +(broadcast1To16Int32x4 ...) => (VPBROADCASTD512 ...) // pureVreg +(broadcast1To16Uint8x16 ...) => (VPBROADCASTB128 ...) // pureVreg +(broadcast1To16Uint16x8 ...) => (VPBROADCASTW256 ...) // pureVreg +(broadcast1To16Uint32x4 ...) => (VPBROADCASTD512 ...) // pureVreg +(broadcast1To16MaskedFloat32x4 x mask) => (VBROADCASTSSMasked512 x (VPMOVVec32x4ToM mask)) // maskIn +(broadcast1To16MaskedInt8x16 x mask) => (VPBROADCASTBMasked128 x (VPMOVVec8x16ToM mask)) // maskIn +(broadcast1To16MaskedInt16x8 x mask) => (VPBROADCASTWMasked256 x (VPMOVVec16x8ToM mask)) // maskIn +(broadcast1To16MaskedInt32x4 x mask) => (VPBROADCASTDMasked512 x (VPMOVVec32x4ToM mask)) // maskIn +(broadcast1To16MaskedUint8x16 x mask) => (VPBROADCASTBMasked128 x (VPMOVVec8x16ToM mask)) // maskIn +(broadcast1To16MaskedUint16x8 x mask) => (VPBROADCASTWMasked256 x (VPMOVVec16x8ToM mask)) // maskIn +(broadcast1To16MaskedUint32x4 x mask) => (VPBROADCASTDMasked512 x (VPMOVVec32x4ToM mask)) // maskIn +(broadcast1To32Int8x16 ...) => (VPBROADCASTB256 ...) // pureVreg +(broadcast1To32Int16x8 ...) => (VPBROADCASTW512 ...) // pureVreg +(broadcast1To32Uint8x16 ...) => (VPBROADCASTB256 ...) // pureVreg +(broadcast1To32Uint16x8 ...) => (VPBROADCASTW512 ...) // pureVreg +(broadcast1To32MaskedInt8x16 x mask) => (VPBROADCASTBMasked256 x (VPMOVVec8x16ToM mask)) // maskIn +(broadcast1To32MaskedInt16x8 x mask) => (VPBROADCASTWMasked512 x (VPMOVVec16x8ToM mask)) // maskIn +(broadcast1To32MaskedUint8x16 x mask) => (VPBROADCASTBMasked256 x (VPMOVVec8x16ToM mask)) // maskIn +(broadcast1To32MaskedUint16x8 x mask) => (VPBROADCASTWMasked512 x (VPMOVVec16x8ToM mask)) // maskIn +(broadcast1To64Int8x16 ...) => (VPBROADCASTB512 ...) // pureVreg +(broadcast1To64Uint8x16 ...) => (VPBROADCASTB512 ...) // pureVreg +(broadcast1To64MaskedInt8x16 x mask) => (VPBROADCASTBMasked512 x (VPMOVVec8x16ToM mask)) // maskIn +(broadcast1To64MaskedUint8x16 x mask) => (VPBROADCASTBMasked512 x (VPMOVVec8x16ToM mask)) // maskIn +(carrylessMultiplyUint64x2 ...) => (VPCLMULQDQ128 ...) // pureVreg +(carrylessMultiplyUint64x4 ...) => (VPCLMULQDQ256 ...) // pureVreg +(carrylessMultiplyUint64x8 ...) => (VPCLMULQDQ512 ...) // pureVreg +(concatSelectedConstantFloat32x4 ...) => (VSHUFPS128 ...) // pureVreg +(concatSelectedConstantFloat64x2 ...) => (VSHUFPD128 ...) // pureVreg +(concatSelectedConstantInt32x4 ...) => (VSHUFPS128 ...) // pureVreg +(concatSelectedConstantInt64x2 ...) => (VSHUFPD128 ...) // pureVreg +(concatSelectedConstantUint32x4 ...) => (VSHUFPS128 ...) // pureVreg +(concatSelectedConstantUint64x2 ...) => (VSHUFPD128 ...) // pureVreg +(concatSelectedConstantGroupedFloat32x8 ...) => (VSHUFPS256 ...) // pureVreg +(concatSelectedConstantGroupedFloat32x16 ...) => (VSHUFPS512 ...) // pureVreg +(concatSelectedConstantGroupedFloat64x4 ...) => (VSHUFPD256 ...) // pureVreg +(concatSelectedConstantGroupedFloat64x8 ...) => (VSHUFPD512 ...) // pureVreg +(concatSelectedConstantGroupedInt32x8 ...) => (VSHUFPS256 ...) // pureVreg +(concatSelectedConstantGroupedInt32x16 ...) => (VSHUFPS512 ...) // pureVreg +(concatSelectedConstantGroupedInt64x4 ...) => (VSHUFPD256 ...) // pureVreg +(concatSelectedConstantGroupedInt64x8 ...) => (VSHUFPD512 ...) // pureVreg +(concatSelectedConstantGroupedUint32x8 ...) => (VSHUFPS256 ...) // pureVreg +(concatSelectedConstantGroupedUint32x16 ...) => (VSHUFPS512 ...) // pureVreg +(concatSelectedConstantGroupedUint64x4 ...) => (VSHUFPD256 ...) // pureVreg +(concatSelectedConstantGroupedUint64x8 ...) => (VSHUFPD512 ...) // pureVreg +(permuteScalarsInt32x4 ...) => (VPSHUFD128 ...) // pureVreg +(permuteScalarsUint32x4 ...) => (VPSHUFD128 ...) // pureVreg +(permuteScalarsGroupedInt32x8 ...) => (VPSHUFD256 ...) // pureVreg +(permuteScalarsGroupedInt32x16 ...) => (VPSHUFD512 ...) // pureVreg +(permuteScalarsGroupedUint32x8 ...) => (VPSHUFD256 ...) // pureVreg +(permuteScalarsGroupedUint32x16 ...) => (VPSHUFD512 ...) // pureVreg +(permuteScalarsHiInt16x8 ...) => (VPSHUFHW128 ...) // pureVreg +(permuteScalarsHiUint16x8 ...) => (VPSHUFHW128 ...) // pureVreg +(permuteScalarsHiGroupedInt16x16 ...) => (VPSHUFHW256 ...) // pureVreg +(permuteScalarsHiGroupedInt16x32 ...) => (VPSHUFHW512 ...) // pureVreg +(permuteScalarsHiGroupedUint16x16 ...) => (VPSHUFHW256 ...) // pureVreg +(permuteScalarsHiGroupedUint16x32 ...) => (VPSHUFHW512 ...) // pureVreg +(permuteScalarsLoInt16x8 ...) => (VPSHUFLW128 ...) // pureVreg +(permuteScalarsLoUint16x8 ...) => (VPSHUFLW128 ...) // pureVreg +(permuteScalarsLoGroupedInt16x16 ...) => (VPSHUFLW256 ...) // pureVreg +(permuteScalarsLoGroupedInt16x32 ...) => (VPSHUFLW512 ...) // pureVreg +(permuteScalarsLoGroupedUint16x16 ...) => (VPSHUFLW256 ...) // pureVreg +(permuteScalarsLoGroupedUint16x32 ...) => (VPSHUFLW512 ...) // pureVreg +(VPSLLW128const [a] x) && a==0 => x // asmRule +(VPSLLW256const [a] x) && a==0 => x // asmRule +(VPSLLW512const [a] x) && a==0 => x // asmRule +(VPSLLD128const [a] x) && a==0 => x // asmRule +(VPSLLD256const [a] x) && a==0 => x // asmRule +(VPSLLD512const [a] x) && a==0 => x // asmRule +(VPSLLQ128const [a] x) && a==0 => x // asmRule +(VPSLLQ256const [a] x) && a==0 => x // asmRule +(VPSLLQ512const [a] x) && a==0 => x // asmRule +(VPSLLWMasked128const [a] x mask) && a==0 => x // asmRule +(VPSLLWMasked256const [a] x mask) && a==0 => x // asmRule +(VPSLLWMasked512const [a] x mask) && a==0 => x // asmRule +(VPSLLDMasked128const [a] x mask) && a==0 => x // asmRule +(VPSLLDMasked256const [a] x mask) && a==0 => x // asmRule +(VPSLLDMasked512const [a] x mask) && a==0 => x // asmRule +(VPSLLQMasked128const [a] x mask) && a==0 => x // asmRule +(VPSLLQMasked256const [a] x mask) && a==0 => x // asmRule +(VPSLLQMasked512const [a] x mask) && a==0 => x // asmRule +(VPSRAW128const [a] x) && a==0 => x // asmRule +(VPSRAW256const [a] x) && a==0 => x // asmRule +(VPSRAW512const [a] x) && a==0 => x // asmRule +(VPSRAD128const [a] x) && a==0 => x // asmRule +(VPSRAD256const [a] x) && a==0 => x // asmRule +(VPSRAD512const [a] x) && a==0 => x // asmRule +(VPSRAQ128const [a] x) && a==0 => x // asmRule +(VPSRAQ256const [a] x) && a==0 => x // asmRule +(VPSRAQ512const [a] x) && a==0 => x // asmRule +(VPSRLW128const [a] x) && a==0 => x // asmRule +(VPSRLW256const [a] x) && a==0 => x // asmRule +(VPSRLW512const [a] x) && a==0 => x // asmRule +(VPSRLD128const [a] x) && a==0 => x // asmRule +(VPSRLD256const [a] x) && a==0 => x // asmRule +(VPSRLD512const [a] x) && a==0 => x // asmRule +(VPSRLQ128const [a] x) && a==0 => x // asmRule +(VPSRLQ256const [a] x) && a==0 => x // asmRule +(VPSRLQ512const [a] x) && a==0 => x // asmRule +(VPSRAWMasked128const [a] x mask) && a==0 => x // asmRule +(VPSRAWMasked256const [a] x mask) && a==0 => x // asmRule +(VPSRAWMasked512const [a] x mask) && a==0 => x // asmRule +(VPSRADMasked128const [a] x mask) && a==0 => x // asmRule +(VPSRADMasked256const [a] x mask) && a==0 => x // asmRule +(VPSRADMasked512const [a] x mask) && a==0 => x // asmRule +(VPSRAQMasked128const [a] x mask) && a==0 => x // asmRule +(VPSRAQMasked256const [a] x mask) && a==0 => x // asmRule +(VPSRAQMasked512const [a] x mask) && a==0 => x // asmRule +(VPSRLWMasked128const [a] x mask) && a==0 => x // asmRule +(VPSRLWMasked256const [a] x mask) && a==0 => x // asmRule +(VPSRLWMasked512const [a] x mask) && a==0 => x // asmRule +(VPSRLDMasked128const [a] x mask) && a==0 => x // asmRule +(VPSRLDMasked256const [a] x mask) && a==0 => x // asmRule +(VPSRLDMasked512const [a] x mask) && a==0 => x // asmRule +(VPSRLQMasked128const [a] x mask) && a==0 => x // asmRule +(VPSRLQMasked256const [a] x mask) && a==0 => x // asmRule +(VPSRLQMasked512const [a] x mask) && a==0 => x // asmRule +(ternInt32x4 ...) => (VPTERNLOGD128 ...) // pureVreg +(ternInt32x8 ...) => (VPTERNLOGD256 ...) // pureVreg +(ternInt32x16 ...) => (VPTERNLOGD512 ...) // pureVreg +(ternInt64x2 ...) => (VPTERNLOGQ128 ...) // pureVreg +(ternInt64x4 ...) => (VPTERNLOGQ256 ...) // pureVreg +(ternInt64x8 ...) => (VPTERNLOGQ512 ...) // pureVreg +(ternUint32x4 ...) => (VPTERNLOGD128 ...) // pureVreg +(ternUint32x8 ...) => (VPTERNLOGD256 ...) // pureVreg +(ternUint32x16 ...) => (VPTERNLOGD512 ...) // pureVreg +(ternUint64x2 ...) => (VPTERNLOGQ128 ...) // pureVreg +(ternUint64x4 ...) => (VPTERNLOGQ256 ...) // pureVreg +(ternUint64x8 ...) => (VPTERNLOGQ512 ...) // pureVreg +(VMOVDQU8Masked128 (VPABSB128 x) mask) => (VPABSBMasked128 x mask) +(VMOVDQU8Masked256 (VPABSB256 x) mask) => (VPABSBMasked256 x mask) +(VMOVDQU8Masked512 (VPABSB512 x) mask) => (VPABSBMasked512 x mask) +(VMOVDQU16Masked128 (VPABSW128 x) mask) => (VPABSWMasked128 x mask) +(VMOVDQU16Masked256 (VPABSW256 x) mask) => (VPABSWMasked256 x mask) +(VMOVDQU16Masked512 (VPABSW512 x) mask) => (VPABSWMasked512 x mask) +(VMOVDQU32Masked128 (VPABSD128 x) mask) => (VPABSDMasked128 x mask) +(VMOVDQU32Masked256 (VPABSD256 x) mask) => (VPABSDMasked256 x mask) +(VMOVDQU32Masked512 (VPABSD512 x) mask) => (VPABSDMasked512 x mask) +(VMOVDQU64Masked128 (VPABSQ128 x) mask) => (VPABSQMasked128 x mask) +(VMOVDQU64Masked256 (VPABSQ256 x) mask) => (VPABSQMasked256 x mask) +(VMOVDQU64Masked512 (VPABSQ512 x) mask) => (VPABSQMasked512 x mask) +(VMOVDQU32Masked128 (VADDPS128 x y) mask) => (VADDPSMasked128 x y mask) +(VMOVDQU32Masked256 (VADDPS256 x y) mask) => (VADDPSMasked256 x y mask) +(VMOVDQU32Masked512 (VADDPS512 x y) mask) => (VADDPSMasked512 x y mask) +(VMOVDQU64Masked128 (VADDPD128 x y) mask) => (VADDPDMasked128 x y mask) +(VMOVDQU64Masked256 (VADDPD256 x y) mask) => (VADDPDMasked256 x y mask) +(VMOVDQU64Masked512 (VADDPD512 x y) mask) => (VADDPDMasked512 x y mask) +(VMOVDQU8Masked128 (VPADDB128 x y) mask) => (VPADDBMasked128 x y mask) +(VMOVDQU8Masked256 (VPADDB256 x y) mask) => (VPADDBMasked256 x y mask) +(VMOVDQU8Masked512 (VPADDB512 x y) mask) => (VPADDBMasked512 x y mask) +(VMOVDQU16Masked128 (VPADDW128 x y) mask) => (VPADDWMasked128 x y mask) +(VMOVDQU16Masked256 (VPADDW256 x y) mask) => (VPADDWMasked256 x y mask) +(VMOVDQU16Masked512 (VPADDW512 x y) mask) => (VPADDWMasked512 x y mask) +(VMOVDQU32Masked128 (VPADDD128 x y) mask) => (VPADDDMasked128 x y mask) +(VMOVDQU32Masked256 (VPADDD256 x y) mask) => (VPADDDMasked256 x y mask) +(VMOVDQU32Masked512 (VPADDD512 x y) mask) => (VPADDDMasked512 x y mask) +(VMOVDQU64Masked128 (VPADDQ128 x y) mask) => (VPADDQMasked128 x y mask) +(VMOVDQU64Masked256 (VPADDQ256 x y) mask) => (VPADDQMasked256 x y mask) +(VMOVDQU64Masked512 (VPADDQ512 x y) mask) => (VPADDQMasked512 x y mask) +(VMOVDQU8Masked128 (VPADDSB128 x y) mask) => (VPADDSBMasked128 x y mask) +(VMOVDQU8Masked256 (VPADDSB256 x y) mask) => (VPADDSBMasked256 x y mask) +(VMOVDQU8Masked512 (VPADDSB512 x y) mask) => (VPADDSBMasked512 x y mask) +(VMOVDQU16Masked128 (VPADDSW128 x y) mask) => (VPADDSWMasked128 x y mask) +(VMOVDQU16Masked256 (VPADDSW256 x y) mask) => (VPADDSWMasked256 x y mask) +(VMOVDQU16Masked512 (VPADDSW512 x y) mask) => (VPADDSWMasked512 x y mask) +(VMOVDQU8Masked128 (VPADDUSB128 x y) mask) => (VPADDUSBMasked128 x y mask) +(VMOVDQU8Masked256 (VPADDUSB256 x y) mask) => (VPADDUSBMasked256 x y mask) +(VMOVDQU8Masked512 (VPADDUSB512 x y) mask) => (VPADDUSBMasked512 x y mask) +(VMOVDQU16Masked128 (VPADDUSW128 x y) mask) => (VPADDUSWMasked128 x y mask) +(VMOVDQU16Masked256 (VPADDUSW256 x y) mask) => (VPADDUSWMasked256 x y mask) +(VMOVDQU16Masked512 (VPADDUSW512 x y) mask) => (VPADDUSWMasked512 x y mask) +(VMOVDQU32Masked512 (VPANDD512 x y) mask) => (VPANDDMasked512 x y mask) +(VMOVDQU64Masked512 (VPANDQ512 x y) mask) => (VPANDQMasked512 x y mask) +(VMOVDQU32Masked512 (VPANDND512 x y) mask) => (VPANDNDMasked512 x y mask) +(VMOVDQU64Masked512 (VPANDNQ512 x y) mask) => (VPANDNQMasked512 x y mask) +(VMOVDQU8Masked128 (VPAVGB128 x y) mask) => (VPAVGBMasked128 x y mask) +(VMOVDQU8Masked256 (VPAVGB256 x y) mask) => (VPAVGBMasked256 x y mask) +(VMOVDQU8Masked512 (VPAVGB512 x y) mask) => (VPAVGBMasked512 x y mask) +(VMOVDQU16Masked128 (VPAVGW128 x y) mask) => (VPAVGWMasked128 x y mask) +(VMOVDQU16Masked256 (VPAVGW256 x y) mask) => (VPAVGWMasked256 x y mask) +(VMOVDQU16Masked512 (VPAVGW512 x y) mask) => (VPAVGWMasked512 x y mask) +(VMOVDQU32Masked128 (VRNDSCALEPS128 [a] x) mask) => (VRNDSCALEPSMasked128 [a] x mask) +(VMOVDQU32Masked256 (VRNDSCALEPS256 [a] x) mask) => (VRNDSCALEPSMasked256 [a] x mask) +(VMOVDQU32Masked512 (VRNDSCALEPS512 [a] x) mask) => (VRNDSCALEPSMasked512 [a] x mask) +(VMOVDQU64Masked128 (VRNDSCALEPD128 [a] x) mask) => (VRNDSCALEPDMasked128 [a] x mask) +(VMOVDQU64Masked256 (VRNDSCALEPD256 [a] x) mask) => (VRNDSCALEPDMasked256 [a] x mask) +(VMOVDQU64Masked512 (VRNDSCALEPD512 [a] x) mask) => (VRNDSCALEPDMasked512 [a] x mask) +(VMOVDQU32Masked128 (VREDUCEPS128 [a] x) mask) => (VREDUCEPSMasked128 [a] x mask) +(VMOVDQU32Masked256 (VREDUCEPS256 [a] x) mask) => (VREDUCEPSMasked256 [a] x mask) +(VMOVDQU32Masked512 (VREDUCEPS512 [a] x) mask) => (VREDUCEPSMasked512 [a] x mask) +(VMOVDQU64Masked128 (VREDUCEPD128 [a] x) mask) => (VREDUCEPDMasked128 [a] x mask) +(VMOVDQU64Masked256 (VREDUCEPD256 [a] x) mask) => (VREDUCEPDMasked256 [a] x mask) +(VMOVDQU64Masked512 (VREDUCEPD512 [a] x) mask) => (VREDUCEPDMasked512 [a] x mask) +(VMOVDQU8Masked128 (VPERMI2B128 x y z) mask) => (VPERMI2BMasked128 x y z mask) +(VMOVDQU8Masked256 (VPERMI2B256 x y z) mask) => (VPERMI2BMasked256 x y z mask) +(VMOVDQU8Masked512 (VPERMI2B512 x y z) mask) => (VPERMI2BMasked512 x y z mask) +(VMOVDQU16Masked128 (VPERMI2W128 x y z) mask) => (VPERMI2WMasked128 x y z mask) +(VMOVDQU16Masked256 (VPERMI2W256 x y z) mask) => (VPERMI2WMasked256 x y z mask) +(VMOVDQU16Masked512 (VPERMI2W512 x y z) mask) => (VPERMI2WMasked512 x y z mask) +(VMOVDQU32Masked128 (VPERMI2PS128 x y z) mask) => (VPERMI2PSMasked128 x y z mask) +(VMOVDQU32Masked128 (VPERMI2D128 x y z) mask) => (VPERMI2DMasked128 x y z mask) +(VMOVDQU32Masked256 (VPERMI2PS256 x y z) mask) => (VPERMI2PSMasked256 x y z mask) +(VMOVDQU32Masked256 (VPERMI2D256 x y z) mask) => (VPERMI2DMasked256 x y z mask) +(VMOVDQU32Masked512 (VPERMI2PS512 x y z) mask) => (VPERMI2PSMasked512 x y z mask) +(VMOVDQU32Masked512 (VPERMI2D512 x y z) mask) => (VPERMI2DMasked512 x y z mask) +(VMOVDQU64Masked128 (VPERMI2PD128 x y z) mask) => (VPERMI2PDMasked128 x y z mask) +(VMOVDQU64Masked128 (VPERMI2Q128 x y z) mask) => (VPERMI2QMasked128 x y z mask) +(VMOVDQU64Masked256 (VPERMI2PD256 x y z) mask) => (VPERMI2PDMasked256 x y z mask) +(VMOVDQU64Masked256 (VPERMI2Q256 x y z) mask) => (VPERMI2QMasked256 x y z mask) +(VMOVDQU64Masked512 (VPERMI2PD512 x y z) mask) => (VPERMI2PDMasked512 x y z mask) +(VMOVDQU64Masked512 (VPERMI2Q512 x y z) mask) => (VPERMI2QMasked512 x y z mask) +(VMOVDQU8Masked256 (VPALIGNR256 [a] x y) mask) => (VPALIGNRMasked256 [a] x y mask) +(VMOVDQU8Masked512 (VPALIGNR512 [a] x y) mask) => (VPALIGNRMasked512 [a] x y mask) +(VMOVDQU8Masked128 (VPALIGNR128 [a] x y) mask) => (VPALIGNRMasked128 [a] x y mask) +(VMOVDQU64Masked128 (VCVTPD2PSX128 x) mask) => (VCVTPD2PSXMasked128 x mask) +(VMOVDQU64Masked128 (VCVTPD2PSY128 x) mask) => (VCVTPD2PSYMasked128 x mask) +(VMOVDQU64Masked256 (VCVTPD2PS256 x) mask) => (VCVTPD2PSMasked256 x mask) +(VMOVDQU32Masked128 (VCVTDQ2PS128 x) mask) => (VCVTDQ2PSMasked128 x mask) +(VMOVDQU32Masked256 (VCVTDQ2PS256 x) mask) => (VCVTDQ2PSMasked256 x mask) +(VMOVDQU32Masked512 (VCVTDQ2PS512 x) mask) => (VCVTDQ2PSMasked512 x mask) +(VMOVDQU64Masked128 (VCVTQQ2PSX128 x) mask) => (VCVTQQ2PSXMasked128 x mask) +(VMOVDQU64Masked128 (VCVTQQ2PSY128 x) mask) => (VCVTQQ2PSYMasked128 x mask) +(VMOVDQU64Masked256 (VCVTQQ2PS256 x) mask) => (VCVTQQ2PSMasked256 x mask) +(VMOVDQU32Masked128 (VCVTUDQ2PS128 x) mask) => (VCVTUDQ2PSMasked128 x mask) +(VMOVDQU32Masked256 (VCVTUDQ2PS256 x) mask) => (VCVTUDQ2PSMasked256 x mask) +(VMOVDQU32Masked512 (VCVTUDQ2PS512 x) mask) => (VCVTUDQ2PSMasked512 x mask) +(VMOVDQU64Masked128 (VCVTUQQ2PSX128 x) mask) => (VCVTUQQ2PSXMasked128 x mask) +(VMOVDQU64Masked128 (VCVTUQQ2PSY128 x) mask) => (VCVTUQQ2PSYMasked128 x mask) +(VMOVDQU64Masked256 (VCVTUQQ2PS256 x) mask) => (VCVTUQQ2PSMasked256 x mask) +(VMOVDQU32Masked256 (VCVTPS2PD256 x) mask) => (VCVTPS2PDMasked256 x mask) +(VMOVDQU32Masked512 (VCVTPS2PD512 x) mask) => (VCVTPS2PDMasked512 x mask) +(VMOVDQU32Masked256 (VCVTDQ2PD256 x) mask) => (VCVTDQ2PDMasked256 x mask) +(VMOVDQU32Masked512 (VCVTDQ2PD512 x) mask) => (VCVTDQ2PDMasked512 x mask) +(VMOVDQU64Masked128 (VCVTQQ2PD128 x) mask) => (VCVTQQ2PDMasked128 x mask) +(VMOVDQU64Masked256 (VCVTQQ2PD256 x) mask) => (VCVTQQ2PDMasked256 x mask) +(VMOVDQU64Masked512 (VCVTQQ2PD512 x) mask) => (VCVTQQ2PDMasked512 x mask) +(VMOVDQU32Masked256 (VCVTUDQ2PD256 x) mask) => (VCVTUDQ2PDMasked256 x mask) +(VMOVDQU32Masked512 (VCVTUDQ2PD512 x) mask) => (VCVTUDQ2PDMasked512 x mask) +(VMOVDQU64Masked128 (VCVTUQQ2PD128 x) mask) => (VCVTUQQ2PDMasked128 x mask) +(VMOVDQU64Masked256 (VCVTUQQ2PD256 x) mask) => (VCVTUQQ2PDMasked256 x mask) +(VMOVDQU64Masked512 (VCVTUQQ2PD512 x) mask) => (VCVTUQQ2PDMasked512 x mask) +(VMOVDQU32Masked128 (VCVTTPS2DQ128 x) mask) => (VCVTTPS2DQMasked128 x mask) +(VMOVDQU32Masked256 (VCVTTPS2DQ256 x) mask) => (VCVTTPS2DQMasked256 x mask) +(VMOVDQU32Masked512 (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512 x mask) +(VMOVDQU64Masked128 (VCVTTPD2DQX128 x) mask) => (VCVTTPD2DQXMasked128 x mask) +(VMOVDQU64Masked128 (VCVTTPD2DQY128 x) mask) => (VCVTTPD2DQYMasked128 x mask) +(VMOVDQU64Masked256 (VCVTTPD2DQ256 x) mask) => (VCVTTPD2DQMasked256 x mask) +(VMOVDQU32Masked256 (VCVTTPS2QQ256 x) mask) => (VCVTTPS2QQMasked256 x mask) +(VMOVDQU32Masked512 (VCVTTPS2QQ512 x) mask) => (VCVTTPS2QQMasked512 x mask) +(VMOVDQU64Masked128 (VCVTTPD2QQ128 x) mask) => (VCVTTPD2QQMasked128 x mask) +(VMOVDQU64Masked256 (VCVTTPD2QQ256 x) mask) => (VCVTTPD2QQMasked256 x mask) +(VMOVDQU64Masked512 (VCVTTPD2QQ512 x) mask) => (VCVTTPD2QQMasked512 x mask) +(VMOVDQU32Masked128 (VCVTTPS2UDQ128 x) mask) => (VCVTTPS2UDQMasked128 x mask) +(VMOVDQU32Masked256 (VCVTTPS2UDQ256 x) mask) => (VCVTTPS2UDQMasked256 x mask) +(VMOVDQU32Masked512 (VCVTTPS2UDQ512 x) mask) => (VCVTTPS2UDQMasked512 x mask) +(VMOVDQU64Masked128 (VCVTTPD2UDQX128 x) mask) => (VCVTTPD2UDQXMasked128 x mask) +(VMOVDQU64Masked128 (VCVTTPD2UDQY128 x) mask) => (VCVTTPD2UDQYMasked128 x mask) +(VMOVDQU64Masked256 (VCVTTPD2UDQ256 x) mask) => (VCVTTPD2UDQMasked256 x mask) +(VMOVDQU32Masked256 (VCVTTPS2UQQ256 x) mask) => (VCVTTPS2UQQMasked256 x mask) +(VMOVDQU32Masked512 (VCVTTPS2UQQ512 x) mask) => (VCVTTPS2UQQMasked512 x mask) +(VMOVDQU64Masked128 (VCVTTPD2UQQ128 x) mask) => (VCVTTPD2UQQMasked128 x mask) +(VMOVDQU64Masked256 (VCVTTPD2UQQ256 x) mask) => (VCVTTPD2UQQMasked256 x mask) +(VMOVDQU64Masked512 (VCVTTPD2UQQ512 x) mask) => (VCVTTPD2UQQMasked512 x mask) +(VMOVDQU32Masked128 (VDIVPS128 x y) mask) => (VDIVPSMasked128 x y mask) +(VMOVDQU32Masked256 (VDIVPS256 x y) mask) => (VDIVPSMasked256 x y mask) +(VMOVDQU32Masked512 (VDIVPS512 x y) mask) => (VDIVPSMasked512 x y mask) +(VMOVDQU64Masked128 (VDIVPD128 x y) mask) => (VDIVPDMasked128 x y mask) +(VMOVDQU64Masked256 (VDIVPD256 x y) mask) => (VDIVPDMasked256 x y mask) +(VMOVDQU64Masked512 (VDIVPD512 x y) mask) => (VDIVPDMasked512 x y mask) +(VMOVDQU16Masked128 (VPMADDWD128 x y) mask) => (VPMADDWDMasked128 x y mask) +(VMOVDQU16Masked256 (VPMADDWD256 x y) mask) => (VPMADDWDMasked256 x y mask) +(VMOVDQU16Masked512 (VPMADDWD512 x y) mask) => (VPMADDWDMasked512 x y mask) +(VMOVDQU16Masked128 (VPMADDUBSW128 x y) mask) => (VPMADDUBSWMasked128 x y mask) +(VMOVDQU16Masked256 (VPMADDUBSW256 x y) mask) => (VPMADDUBSWMasked256 x y mask) +(VMOVDQU16Masked512 (VPMADDUBSW512 x y) mask) => (VPMADDUBSWMasked512 x y mask) +(VMOVDQU8Masked128 (VPMOVSXBQ128 x) mask) => (VPMOVSXBQMasked128 x mask) +(VMOVDQU16Masked128 (VPMOVSXWQ128 x) mask) => (VPMOVSXWQMasked128 x mask) +(VMOVDQU32Masked128 (VPMOVSXDQ128 x) mask) => (VPMOVSXDQMasked128 x mask) +(VMOVDQU8Masked128 (VPMOVZXBQ128 x) mask) => (VPMOVZXBQMasked128 x mask) +(VMOVDQU16Masked128 (VPMOVZXWQ128 x) mask) => (VPMOVZXWQMasked128 x mask) +(VMOVDQU32Masked128 (VPMOVZXDQ128 x) mask) => (VPMOVZXDQMasked128 x mask) +(VMOVDQU8Masked128 (VPMOVSXBD128 x) mask) => (VPMOVSXBDMasked128 x mask) +(VMOVDQU16Masked128 (VPMOVSXWD128 x) mask) => (VPMOVSXWDMasked128 x mask) +(VMOVDQU8Masked256 (VPMOVSXBQ256 x) mask) => (VPMOVSXBQMasked256 x mask) +(VMOVDQU16Masked256 (VPMOVSXWQ256 x) mask) => (VPMOVSXWQMasked256 x mask) +(VMOVDQU8Masked128 (VPMOVZXBD128 x) mask) => (VPMOVZXBDMasked128 x mask) +(VMOVDQU16Masked128 (VPMOVZXWD128 x) mask) => (VPMOVZXWDMasked128 x mask) +(VMOVDQU8Masked256 (VPMOVZXBQ256 x) mask) => (VPMOVZXBQMasked256 x mask) +(VMOVDQU16Masked256 (VPMOVZXWQ256 x) mask) => (VPMOVZXWQMasked256 x mask) +(VMOVDQU8Masked128 (VPMOVSXBW128 x) mask) => (VPMOVSXBWMasked128 x mask) +(VMOVDQU8Masked256 (VPMOVSXBD256 x) mask) => (VPMOVSXBDMasked256 x mask) +(VMOVDQU8Masked512 (VPMOVSXBQ512 x) mask) => (VPMOVSXBQMasked512 x mask) +(VMOVDQU8Masked128 (VPMOVZXBW128 x) mask) => (VPMOVZXBWMasked128 x mask) +(VMOVDQU8Masked256 (VPMOVZXBD256 x) mask) => (VPMOVZXBDMasked256 x mask) +(VMOVDQU8Masked512 (VPMOVZXBQ512 x) mask) => (VPMOVZXBQMasked512 x mask) +(VMOVDQU8Masked256 (VPMOVSXBW256 x) mask) => (VPMOVSXBWMasked256 x mask) +(VMOVDQU8Masked512 (VPMOVSXBW512 x) mask) => (VPMOVSXBWMasked512 x mask) +(VMOVDQU8Masked512 (VPMOVSXBD512 x) mask) => (VPMOVSXBDMasked512 x mask) +(VMOVDQU16Masked256 (VPMOVSXWD256 x) mask) => (VPMOVSXWDMasked256 x mask) +(VMOVDQU16Masked512 (VPMOVSXWD512 x) mask) => (VPMOVSXWDMasked512 x mask) +(VMOVDQU16Masked512 (VPMOVSXWQ512 x) mask) => (VPMOVSXWQMasked512 x mask) +(VMOVDQU32Masked256 (VPMOVSXDQ256 x) mask) => (VPMOVSXDQMasked256 x mask) +(VMOVDQU32Masked512 (VPMOVSXDQ512 x) mask) => (VPMOVSXDQMasked512 x mask) +(VMOVDQU8Masked256 (VPMOVZXBW256 x) mask) => (VPMOVZXBWMasked256 x mask) +(VMOVDQU8Masked512 (VPMOVZXBW512 x) mask) => (VPMOVZXBWMasked512 x mask) +(VMOVDQU8Masked512 (VPMOVZXBD512 x) mask) => (VPMOVZXBDMasked512 x mask) +(VMOVDQU16Masked256 (VPMOVZXWD256 x) mask) => (VPMOVZXWDMasked256 x mask) +(VMOVDQU16Masked512 (VPMOVZXWD512 x) mask) => (VPMOVZXWDMasked512 x mask) +(VMOVDQU16Masked512 (VPMOVZXWQ512 x) mask) => (VPMOVZXWQMasked512 x mask) +(VMOVDQU32Masked256 (VPMOVZXDQ256 x) mask) => (VPMOVZXDQMasked256 x mask) +(VMOVDQU32Masked512 (VPMOVZXDQ512 x) mask) => (VPMOVZXDQMasked512 x mask) +(VMOVDQU8Masked128 (VGF2P8AFFINEINVQB128 [a] x y) mask) => (VGF2P8AFFINEINVQBMasked128 [a] x y mask) +(VMOVDQU8Masked256 (VGF2P8AFFINEINVQB256 [a] x y) mask) => (VGF2P8AFFINEINVQBMasked256 [a] x y mask) +(VMOVDQU8Masked512 (VGF2P8AFFINEINVQB512 [a] x y) mask) => (VGF2P8AFFINEINVQBMasked512 [a] x y mask) +(VMOVDQU8Masked128 (VGF2P8AFFINEQB128 [a] x y) mask) => (VGF2P8AFFINEQBMasked128 [a] x y mask) +(VMOVDQU8Masked256 (VGF2P8AFFINEQB256 [a] x y) mask) => (VGF2P8AFFINEQBMasked256 [a] x y mask) +(VMOVDQU8Masked512 (VGF2P8AFFINEQB512 [a] x y) mask) => (VGF2P8AFFINEQBMasked512 [a] x y mask) +(VMOVDQU8Masked128 (VGF2P8MULB128 x y) mask) => (VGF2P8MULBMasked128 x y mask) +(VMOVDQU8Masked256 (VGF2P8MULB256 x y) mask) => (VGF2P8MULBMasked256 x y mask) +(VMOVDQU8Masked512 (VGF2P8MULB512 x y) mask) => (VGF2P8MULBMasked512 x y mask) +(VMOVDQU32Masked128 (VPLZCNTD128 x) mask) => (VPLZCNTDMasked128 x mask) +(VMOVDQU32Masked256 (VPLZCNTD256 x) mask) => (VPLZCNTDMasked256 x mask) +(VMOVDQU32Masked512 (VPLZCNTD512 x) mask) => (VPLZCNTDMasked512 x mask) +(VMOVDQU64Masked128 (VPLZCNTQ128 x) mask) => (VPLZCNTQMasked128 x mask) +(VMOVDQU64Masked256 (VPLZCNTQ256 x) mask) => (VPLZCNTQMasked256 x mask) +(VMOVDQU64Masked512 (VPLZCNTQ512 x) mask) => (VPLZCNTQMasked512 x mask) +(VMOVDQU32Masked128 (VMAXPS128 x y) mask) => (VMAXPSMasked128 x y mask) +(VMOVDQU32Masked256 (VMAXPS256 x y) mask) => (VMAXPSMasked256 x y mask) +(VMOVDQU32Masked512 (VMAXPS512 x y) mask) => (VMAXPSMasked512 x y mask) +(VMOVDQU64Masked128 (VMAXPD128 x y) mask) => (VMAXPDMasked128 x y mask) +(VMOVDQU64Masked256 (VMAXPD256 x y) mask) => (VMAXPDMasked256 x y mask) +(VMOVDQU64Masked512 (VMAXPD512 x y) mask) => (VMAXPDMasked512 x y mask) +(VMOVDQU8Masked128 (VPMAXSB128 x y) mask) => (VPMAXSBMasked128 x y mask) +(VMOVDQU8Masked256 (VPMAXSB256 x y) mask) => (VPMAXSBMasked256 x y mask) +(VMOVDQU8Masked512 (VPMAXSB512 x y) mask) => (VPMAXSBMasked512 x y mask) +(VMOVDQU16Masked128 (VPMAXSW128 x y) mask) => (VPMAXSWMasked128 x y mask) +(VMOVDQU16Masked256 (VPMAXSW256 x y) mask) => (VPMAXSWMasked256 x y mask) +(VMOVDQU16Masked512 (VPMAXSW512 x y) mask) => (VPMAXSWMasked512 x y mask) +(VMOVDQU32Masked128 (VPMAXSD128 x y) mask) => (VPMAXSDMasked128 x y mask) +(VMOVDQU32Masked256 (VPMAXSD256 x y) mask) => (VPMAXSDMasked256 x y mask) +(VMOVDQU32Masked512 (VPMAXSD512 x y) mask) => (VPMAXSDMasked512 x y mask) +(VMOVDQU64Masked128 (VPMAXSQ128 x y) mask) => (VPMAXSQMasked128 x y mask) +(VMOVDQU64Masked256 (VPMAXSQ256 x y) mask) => (VPMAXSQMasked256 x y mask) +(VMOVDQU64Masked512 (VPMAXSQ512 x y) mask) => (VPMAXSQMasked512 x y mask) +(VMOVDQU8Masked128 (VPMAXUB128 x y) mask) => (VPMAXUBMasked128 x y mask) +(VMOVDQU8Masked256 (VPMAXUB256 x y) mask) => (VPMAXUBMasked256 x y mask) +(VMOVDQU8Masked512 (VPMAXUB512 x y) mask) => (VPMAXUBMasked512 x y mask) +(VMOVDQU16Masked128 (VPMAXUW128 x y) mask) => (VPMAXUWMasked128 x y mask) +(VMOVDQU16Masked256 (VPMAXUW256 x y) mask) => (VPMAXUWMasked256 x y mask) +(VMOVDQU16Masked512 (VPMAXUW512 x y) mask) => (VPMAXUWMasked512 x y mask) +(VMOVDQU32Masked128 (VPMAXUD128 x y) mask) => (VPMAXUDMasked128 x y mask) +(VMOVDQU32Masked256 (VPMAXUD256 x y) mask) => (VPMAXUDMasked256 x y mask) +(VMOVDQU32Masked512 (VPMAXUD512 x y) mask) => (VPMAXUDMasked512 x y mask) +(VMOVDQU64Masked128 (VPMAXUQ128 x y) mask) => (VPMAXUQMasked128 x y mask) +(VMOVDQU64Masked256 (VPMAXUQ256 x y) mask) => (VPMAXUQMasked256 x y mask) +(VMOVDQU64Masked512 (VPMAXUQ512 x y) mask) => (VPMAXUQMasked512 x y mask) +(VMOVDQU32Masked128 (VMINPS128 x y) mask) => (VMINPSMasked128 x y mask) +(VMOVDQU32Masked256 (VMINPS256 x y) mask) => (VMINPSMasked256 x y mask) +(VMOVDQU32Masked512 (VMINPS512 x y) mask) => (VMINPSMasked512 x y mask) +(VMOVDQU64Masked128 (VMINPD128 x y) mask) => (VMINPDMasked128 x y mask) +(VMOVDQU64Masked256 (VMINPD256 x y) mask) => (VMINPDMasked256 x y mask) +(VMOVDQU64Masked512 (VMINPD512 x y) mask) => (VMINPDMasked512 x y mask) +(VMOVDQU8Masked128 (VPMINSB128 x y) mask) => (VPMINSBMasked128 x y mask) +(VMOVDQU8Masked256 (VPMINSB256 x y) mask) => (VPMINSBMasked256 x y mask) +(VMOVDQU8Masked512 (VPMINSB512 x y) mask) => (VPMINSBMasked512 x y mask) +(VMOVDQU16Masked128 (VPMINSW128 x y) mask) => (VPMINSWMasked128 x y mask) +(VMOVDQU16Masked256 (VPMINSW256 x y) mask) => (VPMINSWMasked256 x y mask) +(VMOVDQU16Masked512 (VPMINSW512 x y) mask) => (VPMINSWMasked512 x y mask) +(VMOVDQU32Masked128 (VPMINSD128 x y) mask) => (VPMINSDMasked128 x y mask) +(VMOVDQU32Masked256 (VPMINSD256 x y) mask) => (VPMINSDMasked256 x y mask) +(VMOVDQU32Masked512 (VPMINSD512 x y) mask) => (VPMINSDMasked512 x y mask) +(VMOVDQU64Masked128 (VPMINSQ128 x y) mask) => (VPMINSQMasked128 x y mask) +(VMOVDQU64Masked256 (VPMINSQ256 x y) mask) => (VPMINSQMasked256 x y mask) +(VMOVDQU64Masked512 (VPMINSQ512 x y) mask) => (VPMINSQMasked512 x y mask) +(VMOVDQU8Masked128 (VPMINUB128 x y) mask) => (VPMINUBMasked128 x y mask) +(VMOVDQU8Masked256 (VPMINUB256 x y) mask) => (VPMINUBMasked256 x y mask) +(VMOVDQU8Masked512 (VPMINUB512 x y) mask) => (VPMINUBMasked512 x y mask) +(VMOVDQU16Masked128 (VPMINUW128 x y) mask) => (VPMINUWMasked128 x y mask) +(VMOVDQU16Masked256 (VPMINUW256 x y) mask) => (VPMINUWMasked256 x y mask) +(VMOVDQU16Masked512 (VPMINUW512 x y) mask) => (VPMINUWMasked512 x y mask) +(VMOVDQU32Masked128 (VPMINUD128 x y) mask) => (VPMINUDMasked128 x y mask) +(VMOVDQU32Masked256 (VPMINUD256 x y) mask) => (VPMINUDMasked256 x y mask) +(VMOVDQU32Masked512 (VPMINUD512 x y) mask) => (VPMINUDMasked512 x y mask) +(VMOVDQU64Masked128 (VPMINUQ128 x y) mask) => (VPMINUQMasked128 x y mask) +(VMOVDQU64Masked256 (VPMINUQ256 x y) mask) => (VPMINUQMasked256 x y mask) +(VMOVDQU64Masked512 (VPMINUQ512 x y) mask) => (VPMINUQMasked512 x y mask) +(VMOVDQU32Masked128 (VFMADDSUB213PS128 x y z) mask) => (VFMADDSUB213PSMasked128 x y z mask) +(VMOVDQU32Masked256 (VFMADDSUB213PS256 x y z) mask) => (VFMADDSUB213PSMasked256 x y z mask) +(VMOVDQU32Masked512 (VFMADDSUB213PS512 x y z) mask) => (VFMADDSUB213PSMasked512 x y z mask) +(VMOVDQU64Masked128 (VFMADDSUB213PD128 x y z) mask) => (VFMADDSUB213PDMasked128 x y z mask) +(VMOVDQU64Masked256 (VFMADDSUB213PD256 x y z) mask) => (VFMADDSUB213PDMasked256 x y z mask) +(VMOVDQU64Masked512 (VFMADDSUB213PD512 x y z) mask) => (VFMADDSUB213PDMasked512 x y z mask) +(VMOVDQU32Masked128 (VFMADD213PS128 x y z) mask) => (VFMADD213PSMasked128 x y z mask) +(VMOVDQU32Masked256 (VFMADD213PS256 x y z) mask) => (VFMADD213PSMasked256 x y z mask) +(VMOVDQU32Masked512 (VFMADD213PS512 x y z) mask) => (VFMADD213PSMasked512 x y z mask) +(VMOVDQU64Masked128 (VFMADD213PD128 x y z) mask) => (VFMADD213PDMasked128 x y z mask) +(VMOVDQU64Masked256 (VFMADD213PD256 x y z) mask) => (VFMADD213PDMasked256 x y z mask) +(VMOVDQU64Masked512 (VFMADD213PD512 x y z) mask) => (VFMADD213PDMasked512 x y z mask) +(VMOVDQU32Masked128 (VFMSUBADD213PS128 x y z) mask) => (VFMSUBADD213PSMasked128 x y z mask) +(VMOVDQU32Masked256 (VFMSUBADD213PS256 x y z) mask) => (VFMSUBADD213PSMasked256 x y z mask) +(VMOVDQU32Masked512 (VFMSUBADD213PS512 x y z) mask) => (VFMSUBADD213PSMasked512 x y z mask) +(VMOVDQU64Masked128 (VFMSUBADD213PD128 x y z) mask) => (VFMSUBADD213PDMasked128 x y z mask) +(VMOVDQU64Masked256 (VFMSUBADD213PD256 x y z) mask) => (VFMSUBADD213PDMasked256 x y z mask) +(VMOVDQU64Masked512 (VFMSUBADD213PD512 x y z) mask) => (VFMSUBADD213PDMasked512 x y z mask) +(VMOVDQU16Masked128 (VPMULHW128 x y) mask) => (VPMULHWMasked128 x y mask) +(VMOVDQU16Masked256 (VPMULHW256 x y) mask) => (VPMULHWMasked256 x y mask) +(VMOVDQU16Masked512 (VPMULHW512 x y) mask) => (VPMULHWMasked512 x y mask) +(VMOVDQU16Masked128 (VPMULHUW128 x y) mask) => (VPMULHUWMasked128 x y mask) +(VMOVDQU16Masked256 (VPMULHUW256 x y) mask) => (VPMULHUWMasked256 x y mask) +(VMOVDQU16Masked512 (VPMULHUW512 x y) mask) => (VPMULHUWMasked512 x y mask) +(VMOVDQU32Masked128 (VMULPS128 x y) mask) => (VMULPSMasked128 x y mask) +(VMOVDQU32Masked256 (VMULPS256 x y) mask) => (VMULPSMasked256 x y mask) +(VMOVDQU32Masked512 (VMULPS512 x y) mask) => (VMULPSMasked512 x y mask) +(VMOVDQU64Masked128 (VMULPD128 x y) mask) => (VMULPDMasked128 x y mask) +(VMOVDQU64Masked256 (VMULPD256 x y) mask) => (VMULPDMasked256 x y mask) +(VMOVDQU64Masked512 (VMULPD512 x y) mask) => (VMULPDMasked512 x y mask) +(VMOVDQU16Masked128 (VPMULLW128 x y) mask) => (VPMULLWMasked128 x y mask) +(VMOVDQU16Masked256 (VPMULLW256 x y) mask) => (VPMULLWMasked256 x y mask) +(VMOVDQU16Masked512 (VPMULLW512 x y) mask) => (VPMULLWMasked512 x y mask) +(VMOVDQU32Masked128 (VPMULLD128 x y) mask) => (VPMULLDMasked128 x y mask) +(VMOVDQU32Masked256 (VPMULLD256 x y) mask) => (VPMULLDMasked256 x y mask) +(VMOVDQU32Masked512 (VPMULLD512 x y) mask) => (VPMULLDMasked512 x y mask) +(VMOVDQU64Masked128 (VPMULLQ128 x y) mask) => (VPMULLQMasked128 x y mask) +(VMOVDQU64Masked256 (VPMULLQ256 x y) mask) => (VPMULLQMasked256 x y mask) +(VMOVDQU64Masked512 (VPMULLQ512 x y) mask) => (VPMULLQMasked512 x y mask) +(VMOVDQU8Masked128 (VPOPCNTB128 x) mask) => (VPOPCNTBMasked128 x mask) +(VMOVDQU8Masked256 (VPOPCNTB256 x) mask) => (VPOPCNTBMasked256 x mask) +(VMOVDQU8Masked512 (VPOPCNTB512 x) mask) => (VPOPCNTBMasked512 x mask) +(VMOVDQU16Masked128 (VPOPCNTW128 x) mask) => (VPOPCNTWMasked128 x mask) +(VMOVDQU16Masked256 (VPOPCNTW256 x) mask) => (VPOPCNTWMasked256 x mask) +(VMOVDQU16Masked512 (VPOPCNTW512 x) mask) => (VPOPCNTWMasked512 x mask) +(VMOVDQU32Masked128 (VPOPCNTD128 x) mask) => (VPOPCNTDMasked128 x mask) +(VMOVDQU32Masked256 (VPOPCNTD256 x) mask) => (VPOPCNTDMasked256 x mask) +(VMOVDQU32Masked512 (VPOPCNTD512 x) mask) => (VPOPCNTDMasked512 x mask) +(VMOVDQU64Masked128 (VPOPCNTQ128 x) mask) => (VPOPCNTQMasked128 x mask) +(VMOVDQU64Masked256 (VPOPCNTQ256 x) mask) => (VPOPCNTQMasked256 x mask) +(VMOVDQU64Masked512 (VPOPCNTQ512 x) mask) => (VPOPCNTQMasked512 x mask) +(VMOVDQU32Masked512 (VPORD512 x y) mask) => (VPORDMasked512 x y mask) +(VMOVDQU64Masked512 (VPORQ512 x y) mask) => (VPORQMasked512 x y mask) +(VMOVDQU8Masked128 (VPERMB128 x y) mask) => (VPERMBMasked128 x y mask) +(VMOVDQU8Masked256 (VPERMB256 x y) mask) => (VPERMBMasked256 x y mask) +(VMOVDQU8Masked512 (VPERMB512 x y) mask) => (VPERMBMasked512 x y mask) +(VMOVDQU16Masked128 (VPERMW128 x y) mask) => (VPERMWMasked128 x y mask) +(VMOVDQU16Masked256 (VPERMW256 x y) mask) => (VPERMWMasked256 x y mask) +(VMOVDQU16Masked512 (VPERMW512 x y) mask) => (VPERMWMasked512 x y mask) +(VMOVDQU32Masked256 (VPERMPS256 x y) mask) => (VPERMPSMasked256 x y mask) +(VMOVDQU32Masked256 (VPERMD256 x y) mask) => (VPERMDMasked256 x y mask) +(VMOVDQU32Masked512 (VPERMPS512 x y) mask) => (VPERMPSMasked512 x y mask) +(VMOVDQU32Masked512 (VPERMD512 x y) mask) => (VPERMDMasked512 x y mask) +(VMOVDQU64Masked256 (VPERMPD256 x y) mask) => (VPERMPDMasked256 x y mask) +(VMOVDQU64Masked256 (VPERMQ256 x y) mask) => (VPERMQMasked256 x y mask) +(VMOVDQU64Masked512 (VPERMPD512 x y) mask) => (VPERMPDMasked512 x y mask) +(VMOVDQU64Masked512 (VPERMQ512 x y) mask) => (VPERMQMasked512 x y mask) +(VMOVDQU8Masked256 (VPSHUFB256 x y) mask) => (VPSHUFBMasked256 x y mask) +(VMOVDQU8Masked512 (VPSHUFB512 x y) mask) => (VPSHUFBMasked512 x y mask) +(VMOVDQU8Masked128 (VPSHUFB128 x y) mask) => (VPSHUFBMasked128 x y mask) +(VMOVDQU32Masked512 (VRCP14PS512 x) mask) => (VRCP14PSMasked512 x mask) +(VMOVDQU64Masked128 (VRCP14PD128 x) mask) => (VRCP14PDMasked128 x mask) +(VMOVDQU64Masked256 (VRCP14PD256 x) mask) => (VRCP14PDMasked256 x mask) +(VMOVDQU64Masked512 (VRCP14PD512 x) mask) => (VRCP14PDMasked512 x mask) +(VMOVDQU32Masked512 (VRSQRT14PS512 x) mask) => (VRSQRT14PSMasked512 x mask) +(VMOVDQU64Masked128 (VRSQRT14PD128 x) mask) => (VRSQRT14PDMasked128 x mask) +(VMOVDQU64Masked256 (VRSQRT14PD256 x) mask) => (VRSQRT14PDMasked256 x mask) +(VMOVDQU64Masked512 (VRSQRT14PD512 x) mask) => (VRSQRT14PDMasked512 x mask) +(VMOVDQU32Masked128 (VPROLVD128 x y) mask) => (VPROLVDMasked128 x y mask) +(VMOVDQU32Masked256 (VPROLVD256 x y) mask) => (VPROLVDMasked256 x y mask) +(VMOVDQU32Masked512 (VPROLVD512 x y) mask) => (VPROLVDMasked512 x y mask) +(VMOVDQU64Masked128 (VPROLVQ128 x y) mask) => (VPROLVQMasked128 x y mask) +(VMOVDQU64Masked256 (VPROLVQ256 x y) mask) => (VPROLVQMasked256 x y mask) +(VMOVDQU64Masked512 (VPROLVQ512 x y) mask) => (VPROLVQMasked512 x y mask) +(VMOVDQU32Masked128 (VPRORVD128 x y) mask) => (VPRORVDMasked128 x y mask) +(VMOVDQU32Masked256 (VPRORVD256 x y) mask) => (VPRORVDMasked256 x y mask) +(VMOVDQU32Masked512 (VPRORVD512 x y) mask) => (VPRORVDMasked512 x y mask) +(VMOVDQU64Masked128 (VPRORVQ128 x y) mask) => (VPRORVQMasked128 x y mask) +(VMOVDQU64Masked256 (VPRORVQ256 x y) mask) => (VPRORVQMasked256 x y mask) +(VMOVDQU64Masked512 (VPRORVQ512 x y) mask) => (VPRORVQMasked512 x y mask) +(VMOVDQU16Masked128 (VPMOVSWB128_128 x) mask) => (VPMOVSWBMasked128_128 x mask) +(VMOVDQU16Masked256 (VPMOVSWB128_256 x) mask) => (VPMOVSWBMasked128_256 x mask) +(VMOVDQU16Masked256 (VPMOVSWB256 x) mask) => (VPMOVSWBMasked256 x mask) +(VMOVDQU32Masked128 (VPMOVSDB128_128 x) mask) => (VPMOVSDBMasked128_128 x mask) +(VMOVDQU32Masked256 (VPMOVSDB128_256 x) mask) => (VPMOVSDBMasked128_256 x mask) +(VMOVDQU32Masked512 (VPMOVSDB128_512 x) mask) => (VPMOVSDBMasked128_512 x mask) +(VMOVDQU64Masked128 (VPMOVSQB128_128 x) mask) => (VPMOVSQBMasked128_128 x mask) +(VMOVDQU64Masked256 (VPMOVSQB128_256 x) mask) => (VPMOVSQBMasked128_256 x mask) +(VMOVDQU64Masked512 (VPMOVSQB128_512 x) mask) => (VPMOVSQBMasked128_512 x mask) +(VMOVDQU32Masked256 (VPACKSSDW256 x y) mask) => (VPACKSSDWMasked256 x y mask) +(VMOVDQU32Masked512 (VPACKSSDW512 x y) mask) => (VPACKSSDWMasked512 x y mask) +(VMOVDQU32Masked128 (VPACKSSDW128 x y) mask) => (VPACKSSDWMasked128 x y mask) +(VMOVDQU32Masked128 (VPMOVSDW128_128 x) mask) => (VPMOVSDWMasked128_128 x mask) +(VMOVDQU32Masked256 (VPMOVSDW128_256 x) mask) => (VPMOVSDWMasked128_256 x mask) +(VMOVDQU32Masked256 (VPMOVSDW256 x) mask) => (VPMOVSDWMasked256 x mask) +(VMOVDQU64Masked128 (VPMOVSQW128_128 x) mask) => (VPMOVSQWMasked128_128 x mask) +(VMOVDQU64Masked256 (VPMOVSQW128_256 x) mask) => (VPMOVSQWMasked128_256 x mask) +(VMOVDQU64Masked512 (VPMOVSQW128_512 x) mask) => (VPMOVSQWMasked128_512 x mask) +(VMOVDQU64Masked128 (VPMOVSQD128_128 x) mask) => (VPMOVSQDMasked128_128 x mask) +(VMOVDQU64Masked256 (VPMOVSQD128_256 x) mask) => (VPMOVSQDMasked128_256 x mask) +(VMOVDQU64Masked256 (VPMOVSQD256 x) mask) => (VPMOVSQDMasked256 x mask) +(VMOVDQU16Masked128 (VPMOVUSWB128_128 x) mask) => (VPMOVUSWBMasked128_128 x mask) +(VMOVDQU16Masked256 (VPMOVUSWB128_256 x) mask) => (VPMOVUSWBMasked128_256 x mask) +(VMOVDQU16Masked256 (VPMOVUSWB256 x) mask) => (VPMOVUSWBMasked256 x mask) +(VMOVDQU32Masked128 (VPMOVUSDB128_128 x) mask) => (VPMOVUSDBMasked128_128 x mask) +(VMOVDQU32Masked256 (VPMOVUSDB128_256 x) mask) => (VPMOVUSDBMasked128_256 x mask) +(VMOVDQU32Masked512 (VPMOVUSDB128_512 x) mask) => (VPMOVUSDBMasked128_512 x mask) +(VMOVDQU64Masked128 (VPMOVUSQB128_128 x) mask) => (VPMOVUSQBMasked128_128 x mask) +(VMOVDQU64Masked256 (VPMOVUSQB128_256 x) mask) => (VPMOVUSQBMasked128_256 x mask) +(VMOVDQU64Masked512 (VPMOVUSQB128_512 x) mask) => (VPMOVUSQBMasked128_512 x mask) +(VMOVDQU32Masked256 (VPACKUSDW256 x y) mask) => (VPACKUSDWMasked256 x y mask) +(VMOVDQU32Masked512 (VPACKUSDW512 x y) mask) => (VPACKUSDWMasked512 x y mask) +(VMOVDQU32Masked128 (VPACKUSDW128 x y) mask) => (VPACKUSDWMasked128 x y mask) +(VMOVDQU32Masked128 (VPMOVUSDW128_128 x) mask) => (VPMOVUSDWMasked128_128 x mask) +(VMOVDQU32Masked256 (VPMOVUSDW128_256 x) mask) => (VPMOVUSDWMasked128_256 x mask) +(VMOVDQU32Masked256 (VPMOVUSDW256 x) mask) => (VPMOVUSDWMasked256 x mask) +(VMOVDQU64Masked128 (VPMOVUSQW128_128 x) mask) => (VPMOVUSQWMasked128_128 x mask) +(VMOVDQU64Masked256 (VPMOVUSQW128_256 x) mask) => (VPMOVUSQWMasked128_256 x mask) +(VMOVDQU64Masked512 (VPMOVUSQW128_512 x) mask) => (VPMOVUSQWMasked128_512 x mask) +(VMOVDQU64Masked128 (VPMOVUSQD128_128 x) mask) => (VPMOVUSQDMasked128_128 x mask) +(VMOVDQU64Masked256 (VPMOVUSQD128_256 x) mask) => (VPMOVUSQDMasked128_256 x mask) +(VMOVDQU64Masked256 (VPMOVUSQD256 x) mask) => (VPMOVUSQDMasked256 x mask) +(VMOVDQU32Masked128 (VSCALEFPS128 x y) mask) => (VSCALEFPSMasked128 x y mask) +(VMOVDQU32Masked256 (VSCALEFPS256 x y) mask) => (VSCALEFPSMasked256 x y mask) +(VMOVDQU32Masked512 (VSCALEFPS512 x y) mask) => (VSCALEFPSMasked512 x y mask) +(VMOVDQU64Masked128 (VSCALEFPD128 x y) mask) => (VSCALEFPDMasked128 x y mask) +(VMOVDQU64Masked256 (VSCALEFPD256 x y) mask) => (VSCALEFPDMasked256 x y mask) +(VMOVDQU64Masked512 (VSCALEFPD512 x y) mask) => (VSCALEFPDMasked512 x y mask) +(VMOVDQU16Masked128 (VPSHLDW128 [a] x y) mask) => (VPSHLDWMasked128 [a] x y mask) +(VMOVDQU16Masked256 (VPSHLDW256 [a] x y) mask) => (VPSHLDWMasked256 [a] x y mask) +(VMOVDQU16Masked512 (VPSHLDW512 [a] x y) mask) => (VPSHLDWMasked512 [a] x y mask) +(VMOVDQU32Masked128 (VPSHLDD128 [a] x y) mask) => (VPSHLDDMasked128 [a] x y mask) +(VMOVDQU32Masked256 (VPSHLDD256 [a] x y) mask) => (VPSHLDDMasked256 [a] x y mask) +(VMOVDQU32Masked512 (VPSHLDD512 [a] x y) mask) => (VPSHLDDMasked512 [a] x y mask) +(VMOVDQU64Masked128 (VPSHLDQ128 [a] x y) mask) => (VPSHLDQMasked128 [a] x y mask) +(VMOVDQU64Masked256 (VPSHLDQ256 [a] x y) mask) => (VPSHLDQMasked256 [a] x y mask) +(VMOVDQU64Masked512 (VPSHLDQ512 [a] x y) mask) => (VPSHLDQMasked512 [a] x y mask) +(VMOVDQU16Masked128 (VPSLLW128 x y) mask) => (VPSLLWMasked128 x y mask) +(VMOVDQU16Masked256 (VPSLLW256 x y) mask) => (VPSLLWMasked256 x y mask) +(VMOVDQU16Masked512 (VPSLLW512 x y) mask) => (VPSLLWMasked512 x y mask) +(VMOVDQU32Masked128 (VPSLLD128 x y) mask) => (VPSLLDMasked128 x y mask) +(VMOVDQU32Masked256 (VPSLLD256 x y) mask) => (VPSLLDMasked256 x y mask) +(VMOVDQU32Masked512 (VPSLLD512 x y) mask) => (VPSLLDMasked512 x y mask) +(VMOVDQU64Masked128 (VPSLLQ128 x y) mask) => (VPSLLQMasked128 x y mask) +(VMOVDQU64Masked256 (VPSLLQ256 x y) mask) => (VPSLLQMasked256 x y mask) +(VMOVDQU64Masked512 (VPSLLQ512 x y) mask) => (VPSLLQMasked512 x y mask) +(VMOVDQU16Masked128 (VPSHRDW128 [a] x y) mask) => (VPSHRDWMasked128 [a] x y mask) +(VMOVDQU16Masked256 (VPSHRDW256 [a] x y) mask) => (VPSHRDWMasked256 [a] x y mask) +(VMOVDQU16Masked512 (VPSHRDW512 [a] x y) mask) => (VPSHRDWMasked512 [a] x y mask) +(VMOVDQU32Masked128 (VPSHRDD128 [a] x y) mask) => (VPSHRDDMasked128 [a] x y mask) +(VMOVDQU32Masked256 (VPSHRDD256 [a] x y) mask) => (VPSHRDDMasked256 [a] x y mask) +(VMOVDQU32Masked512 (VPSHRDD512 [a] x y) mask) => (VPSHRDDMasked512 [a] x y mask) +(VMOVDQU64Masked128 (VPSHRDQ128 [a] x y) mask) => (VPSHRDQMasked128 [a] x y mask) +(VMOVDQU64Masked256 (VPSHRDQ256 [a] x y) mask) => (VPSHRDQMasked256 [a] x y mask) +(VMOVDQU64Masked512 (VPSHRDQ512 [a] x y) mask) => (VPSHRDQMasked512 [a] x y mask) +(VMOVDQU16Masked128 (VPSRAW128 x y) mask) => (VPSRAWMasked128 x y mask) +(VMOVDQU16Masked256 (VPSRAW256 x y) mask) => (VPSRAWMasked256 x y mask) +(VMOVDQU16Masked512 (VPSRAW512 x y) mask) => (VPSRAWMasked512 x y mask) +(VMOVDQU32Masked128 (VPSRAD128 x y) mask) => (VPSRADMasked128 x y mask) +(VMOVDQU32Masked256 (VPSRAD256 x y) mask) => (VPSRADMasked256 x y mask) +(VMOVDQU32Masked512 (VPSRAD512 x y) mask) => (VPSRADMasked512 x y mask) +(VMOVDQU64Masked128 (VPSRAQ128 x y) mask) => (VPSRAQMasked128 x y mask) +(VMOVDQU64Masked256 (VPSRAQ256 x y) mask) => (VPSRAQMasked256 x y mask) +(VMOVDQU64Masked512 (VPSRAQ512 x y) mask) => (VPSRAQMasked512 x y mask) +(VMOVDQU16Masked128 (VPSRLW128 x y) mask) => (VPSRLWMasked128 x y mask) +(VMOVDQU16Masked256 (VPSRLW256 x y) mask) => (VPSRLWMasked256 x y mask) +(VMOVDQU16Masked512 (VPSRLW512 x y) mask) => (VPSRLWMasked512 x y mask) +(VMOVDQU32Masked128 (VPSRLD128 x y) mask) => (VPSRLDMasked128 x y mask) +(VMOVDQU32Masked256 (VPSRLD256 x y) mask) => (VPSRLDMasked256 x y mask) +(VMOVDQU32Masked512 (VPSRLD512 x y) mask) => (VPSRLDMasked512 x y mask) +(VMOVDQU64Masked128 (VPSRLQ128 x y) mask) => (VPSRLQMasked128 x y mask) +(VMOVDQU64Masked256 (VPSRLQ256 x y) mask) => (VPSRLQMasked256 x y mask) +(VMOVDQU64Masked512 (VPSRLQ512 x y) mask) => (VPSRLQMasked512 x y mask) +(VMOVDQU16Masked128 (VPSHLDVW128 x y z) mask) => (VPSHLDVWMasked128 x y z mask) +(VMOVDQU16Masked256 (VPSHLDVW256 x y z) mask) => (VPSHLDVWMasked256 x y z mask) +(VMOVDQU16Masked512 (VPSHLDVW512 x y z) mask) => (VPSHLDVWMasked512 x y z mask) +(VMOVDQU32Masked128 (VPSHLDVD128 x y z) mask) => (VPSHLDVDMasked128 x y z mask) +(VMOVDQU32Masked256 (VPSHLDVD256 x y z) mask) => (VPSHLDVDMasked256 x y z mask) +(VMOVDQU32Masked512 (VPSHLDVD512 x y z) mask) => (VPSHLDVDMasked512 x y z mask) +(VMOVDQU64Masked128 (VPSHLDVQ128 x y z) mask) => (VPSHLDVQMasked128 x y z mask) +(VMOVDQU64Masked256 (VPSHLDVQ256 x y z) mask) => (VPSHLDVQMasked256 x y z mask) +(VMOVDQU64Masked512 (VPSHLDVQ512 x y z) mask) => (VPSHLDVQMasked512 x y z mask) +(VMOVDQU16Masked128 (VPSLLVW128 x y) mask) => (VPSLLVWMasked128 x y mask) +(VMOVDQU16Masked256 (VPSLLVW256 x y) mask) => (VPSLLVWMasked256 x y mask) +(VMOVDQU16Masked512 (VPSLLVW512 x y) mask) => (VPSLLVWMasked512 x y mask) +(VMOVDQU32Masked128 (VPSLLVD128 x y) mask) => (VPSLLVDMasked128 x y mask) +(VMOVDQU32Masked256 (VPSLLVD256 x y) mask) => (VPSLLVDMasked256 x y mask) +(VMOVDQU32Masked512 (VPSLLVD512 x y) mask) => (VPSLLVDMasked512 x y mask) +(VMOVDQU64Masked128 (VPSLLVQ128 x y) mask) => (VPSLLVQMasked128 x y mask) +(VMOVDQU64Masked256 (VPSLLVQ256 x y) mask) => (VPSLLVQMasked256 x y mask) +(VMOVDQU64Masked512 (VPSLLVQ512 x y) mask) => (VPSLLVQMasked512 x y mask) +(VMOVDQU16Masked128 (VPSHRDVW128 x y z) mask) => (VPSHRDVWMasked128 x y z mask) +(VMOVDQU16Masked256 (VPSHRDVW256 x y z) mask) => (VPSHRDVWMasked256 x y z mask) +(VMOVDQU16Masked512 (VPSHRDVW512 x y z) mask) => (VPSHRDVWMasked512 x y z mask) +(VMOVDQU32Masked128 (VPSHRDVD128 x y z) mask) => (VPSHRDVDMasked128 x y z mask) +(VMOVDQU32Masked256 (VPSHRDVD256 x y z) mask) => (VPSHRDVDMasked256 x y z mask) +(VMOVDQU32Masked512 (VPSHRDVD512 x y z) mask) => (VPSHRDVDMasked512 x y z mask) +(VMOVDQU64Masked128 (VPSHRDVQ128 x y z) mask) => (VPSHRDVQMasked128 x y z mask) +(VMOVDQU64Masked256 (VPSHRDVQ256 x y z) mask) => (VPSHRDVQMasked256 x y z mask) +(VMOVDQU64Masked512 (VPSHRDVQ512 x y z) mask) => (VPSHRDVQMasked512 x y z mask) +(VMOVDQU16Masked128 (VPSRAVW128 x y) mask) => (VPSRAVWMasked128 x y mask) +(VMOVDQU16Masked256 (VPSRAVW256 x y) mask) => (VPSRAVWMasked256 x y mask) +(VMOVDQU16Masked512 (VPSRAVW512 x y) mask) => (VPSRAVWMasked512 x y mask) +(VMOVDQU32Masked128 (VPSRAVD128 x y) mask) => (VPSRAVDMasked128 x y mask) +(VMOVDQU32Masked256 (VPSRAVD256 x y) mask) => (VPSRAVDMasked256 x y mask) +(VMOVDQU32Masked512 (VPSRAVD512 x y) mask) => (VPSRAVDMasked512 x y mask) +(VMOVDQU64Masked128 (VPSRAVQ128 x y) mask) => (VPSRAVQMasked128 x y mask) +(VMOVDQU64Masked256 (VPSRAVQ256 x y) mask) => (VPSRAVQMasked256 x y mask) +(VMOVDQU64Masked512 (VPSRAVQ512 x y) mask) => (VPSRAVQMasked512 x y mask) +(VMOVDQU16Masked128 (VPSRLVW128 x y) mask) => (VPSRLVWMasked128 x y mask) +(VMOVDQU16Masked256 (VPSRLVW256 x y) mask) => (VPSRLVWMasked256 x y mask) +(VMOVDQU16Masked512 (VPSRLVW512 x y) mask) => (VPSRLVWMasked512 x y mask) +(VMOVDQU32Masked128 (VPSRLVD128 x y) mask) => (VPSRLVDMasked128 x y mask) +(VMOVDQU32Masked256 (VPSRLVD256 x y) mask) => (VPSRLVDMasked256 x y mask) +(VMOVDQU32Masked512 (VPSRLVD512 x y) mask) => (VPSRLVDMasked512 x y mask) +(VMOVDQU64Masked128 (VPSRLVQ128 x y) mask) => (VPSRLVQMasked128 x y mask) +(VMOVDQU64Masked256 (VPSRLVQ256 x y) mask) => (VPSRLVQMasked256 x y mask) +(VMOVDQU64Masked512 (VPSRLVQ512 x y) mask) => (VPSRLVQMasked512 x y mask) +(VMOVDQU32Masked128 (VSQRTPS128 x) mask) => (VSQRTPSMasked128 x mask) +(VMOVDQU32Masked256 (VSQRTPS256 x) mask) => (VSQRTPSMasked256 x mask) +(VMOVDQU32Masked512 (VSQRTPS512 x) mask) => (VSQRTPSMasked512 x mask) +(VMOVDQU64Masked128 (VSQRTPD128 x) mask) => (VSQRTPDMasked128 x mask) +(VMOVDQU64Masked256 (VSQRTPD256 x) mask) => (VSQRTPDMasked256 x mask) +(VMOVDQU64Masked512 (VSQRTPD512 x) mask) => (VSQRTPDMasked512 x mask) +(VMOVDQU32Masked128 (VSUBPS128 x y) mask) => (VSUBPSMasked128 x y mask) +(VMOVDQU32Masked256 (VSUBPS256 x y) mask) => (VSUBPSMasked256 x y mask) +(VMOVDQU32Masked512 (VSUBPS512 x y) mask) => (VSUBPSMasked512 x y mask) +(VMOVDQU64Masked128 (VSUBPD128 x y) mask) => (VSUBPDMasked128 x y mask) +(VMOVDQU64Masked256 (VSUBPD256 x y) mask) => (VSUBPDMasked256 x y mask) +(VMOVDQU64Masked512 (VSUBPD512 x y) mask) => (VSUBPDMasked512 x y mask) +(VMOVDQU8Masked128 (VPSUBB128 x y) mask) => (VPSUBBMasked128 x y mask) +(VMOVDQU8Masked256 (VPSUBB256 x y) mask) => (VPSUBBMasked256 x y mask) +(VMOVDQU8Masked512 (VPSUBB512 x y) mask) => (VPSUBBMasked512 x y mask) +(VMOVDQU16Masked128 (VPSUBW128 x y) mask) => (VPSUBWMasked128 x y mask) +(VMOVDQU16Masked256 (VPSUBW256 x y) mask) => (VPSUBWMasked256 x y mask) +(VMOVDQU16Masked512 (VPSUBW512 x y) mask) => (VPSUBWMasked512 x y mask) +(VMOVDQU32Masked128 (VPSUBD128 x y) mask) => (VPSUBDMasked128 x y mask) +(VMOVDQU32Masked256 (VPSUBD256 x y) mask) => (VPSUBDMasked256 x y mask) +(VMOVDQU32Masked512 (VPSUBD512 x y) mask) => (VPSUBDMasked512 x y mask) +(VMOVDQU64Masked128 (VPSUBQ128 x y) mask) => (VPSUBQMasked128 x y mask) +(VMOVDQU64Masked256 (VPSUBQ256 x y) mask) => (VPSUBQMasked256 x y mask) +(VMOVDQU64Masked512 (VPSUBQ512 x y) mask) => (VPSUBQMasked512 x y mask) +(VMOVDQU8Masked128 (VPSUBSB128 x y) mask) => (VPSUBSBMasked128 x y mask) +(VMOVDQU8Masked256 (VPSUBSB256 x y) mask) => (VPSUBSBMasked256 x y mask) +(VMOVDQU8Masked512 (VPSUBSB512 x y) mask) => (VPSUBSBMasked512 x y mask) +(VMOVDQU16Masked128 (VPSUBSW128 x y) mask) => (VPSUBSWMasked128 x y mask) +(VMOVDQU16Masked256 (VPSUBSW256 x y) mask) => (VPSUBSWMasked256 x y mask) +(VMOVDQU16Masked512 (VPSUBSW512 x y) mask) => (VPSUBSWMasked512 x y mask) +(VMOVDQU8Masked128 (VPSUBUSB128 x y) mask) => (VPSUBUSBMasked128 x y mask) +(VMOVDQU8Masked256 (VPSUBUSB256 x y) mask) => (VPSUBUSBMasked256 x y mask) +(VMOVDQU8Masked512 (VPSUBUSB512 x y) mask) => (VPSUBUSBMasked512 x y mask) +(VMOVDQU16Masked128 (VPSUBUSW128 x y) mask) => (VPSUBUSWMasked128 x y mask) +(VMOVDQU16Masked256 (VPSUBUSW256 x y) mask) => (VPSUBUSWMasked256 x y mask) +(VMOVDQU16Masked512 (VPSUBUSW512 x y) mask) => (VPSUBUSWMasked512 x y mask) +(VMOVDQU16Masked128 (VPMOVWB128_128 x) mask) => (VPMOVWBMasked128_128 x mask) +(VMOVDQU16Masked256 (VPMOVWB128_256 x) mask) => (VPMOVWBMasked128_256 x mask) +(VMOVDQU16Masked256 (VPMOVWB256 x) mask) => (VPMOVWBMasked256 x mask) +(VMOVDQU32Masked128 (VPMOVDB128_128 x) mask) => (VPMOVDBMasked128_128 x mask) +(VMOVDQU32Masked256 (VPMOVDB128_256 x) mask) => (VPMOVDBMasked128_256 x mask) +(VMOVDQU32Masked512 (VPMOVDB128_512 x) mask) => (VPMOVDBMasked128_512 x mask) +(VMOVDQU64Masked128 (VPMOVQB128_128 x) mask) => (VPMOVQBMasked128_128 x mask) +(VMOVDQU64Masked256 (VPMOVQB128_256 x) mask) => (VPMOVQBMasked128_256 x mask) +(VMOVDQU64Masked512 (VPMOVQB128_512 x) mask) => (VPMOVQBMasked128_512 x mask) +(VMOVDQU32Masked128 (VPMOVDW128_128 x) mask) => (VPMOVDWMasked128_128 x mask) +(VMOVDQU32Masked256 (VPMOVDW128_256 x) mask) => (VPMOVDWMasked128_256 x mask) +(VMOVDQU32Masked256 (VPMOVDW256 x) mask) => (VPMOVDWMasked256 x mask) +(VMOVDQU64Masked128 (VPMOVQW128_128 x) mask) => (VPMOVQWMasked128_128 x mask) +(VMOVDQU64Masked256 (VPMOVQW128_256 x) mask) => (VPMOVQWMasked128_256 x mask) +(VMOVDQU64Masked512 (VPMOVQW128_512 x) mask) => (VPMOVQWMasked128_512 x mask) +(VMOVDQU64Masked128 (VPMOVQD128_128 x) mask) => (VPMOVQDMasked128_128 x mask) +(VMOVDQU64Masked256 (VPMOVQD128_256 x) mask) => (VPMOVQDMasked128_256 x mask) +(VMOVDQU64Masked256 (VPMOVQD256 x) mask) => (VPMOVQDMasked256 x mask) +(VMOVDQU32Masked512 (VPXORD512 x y) mask) => (VPXORDMasked512 x y mask) +(VMOVDQU64Masked512 (VPXORQ512 x y) mask) => (VPXORQMasked512 x y mask) +(VMOVDQU32Masked256 (VPSHUFD256 [a] x) mask) => (VPSHUFDMasked256 [a] x mask) +(VMOVDQU32Masked512 (VPSHUFD512 [a] x) mask) => (VPSHUFDMasked512 [a] x mask) +(VMOVDQU16Masked256 (VPSHUFHW256 [a] x) mask) => (VPSHUFHWMasked256 [a] x mask) +(VMOVDQU16Masked512 (VPSHUFHW512 [a] x) mask) => (VPSHUFHWMasked512 [a] x mask) +(VMOVDQU16Masked128 (VPSHUFHW128 [a] x) mask) => (VPSHUFHWMasked128 [a] x mask) +(VMOVDQU16Masked256 (VPSHUFLW256 [a] x) mask) => (VPSHUFLWMasked256 [a] x mask) +(VMOVDQU16Masked512 (VPSHUFLW512 [a] x) mask) => (VPSHUFLWMasked512 [a] x mask) +(VMOVDQU16Masked128 (VPSHUFLW128 [a] x) mask) => (VPSHUFLWMasked128 [a] x mask) +(VMOVDQU32Masked128 (VPSHUFD128 [a] x) mask) => (VPSHUFDMasked128 [a] x mask) +(VMOVDQU16Masked128 (VPSLLW128const [a] x) mask) => (VPSLLWMasked128const [a] x mask) +(VMOVDQU16Masked256 (VPSLLW256const [a] x) mask) => (VPSLLWMasked256const [a] x mask) +(VMOVDQU16Masked512 (VPSLLW512const [a] x) mask) => (VPSLLWMasked512const [a] x mask) +(VMOVDQU32Masked128 (VPSLLD128const [a] x) mask) => (VPSLLDMasked128const [a] x mask) +(VMOVDQU32Masked256 (VPSLLD256const [a] x) mask) => (VPSLLDMasked256const [a] x mask) +(VMOVDQU32Masked512 (VPSLLD512const [a] x) mask) => (VPSLLDMasked512const [a] x mask) +(VMOVDQU64Masked128 (VPSLLQ128const [a] x) mask) => (VPSLLQMasked128const [a] x mask) +(VMOVDQU64Masked256 (VPSLLQ256const [a] x) mask) => (VPSLLQMasked256const [a] x mask) +(VMOVDQU64Masked512 (VPSLLQ512const [a] x) mask) => (VPSLLQMasked512const [a] x mask) +(VMOVDQU16Masked128 (VPSRAW128const [a] x) mask) => (VPSRAWMasked128const [a] x mask) +(VMOVDQU16Masked256 (VPSRAW256const [a] x) mask) => (VPSRAWMasked256const [a] x mask) +(VMOVDQU16Masked512 (VPSRAW512const [a] x) mask) => (VPSRAWMasked512const [a] x mask) +(VMOVDQU32Masked128 (VPSRAD128const [a] x) mask) => (VPSRADMasked128const [a] x mask) +(VMOVDQU32Masked256 (VPSRAD256const [a] x) mask) => (VPSRADMasked256const [a] x mask) +(VMOVDQU32Masked512 (VPSRAD512const [a] x) mask) => (VPSRADMasked512const [a] x mask) +(VMOVDQU64Masked128 (VPSRAQ128const [a] x) mask) => (VPSRAQMasked128const [a] x mask) +(VMOVDQU64Masked256 (VPSRAQ256const [a] x) mask) => (VPSRAQMasked256const [a] x mask) +(VMOVDQU64Masked512 (VPSRAQ512const [a] x) mask) => (VPSRAQMasked512const [a] x mask) +(VMOVDQU16Masked128 (VPSRLW128const [a] x) mask) => (VPSRLWMasked128const [a] x mask) +(VMOVDQU16Masked256 (VPSRLW256const [a] x) mask) => (VPSRLWMasked256const [a] x mask) +(VMOVDQU16Masked512 (VPSRLW512const [a] x) mask) => (VPSRLWMasked512const [a] x mask) +(VMOVDQU32Masked128 (VPSRLD128const [a] x) mask) => (VPSRLDMasked128const [a] x mask) +(VMOVDQU32Masked256 (VPSRLD256const [a] x) mask) => (VPSRLDMasked256const [a] x mask) +(VMOVDQU32Masked512 (VPSRLD512const [a] x) mask) => (VPSRLDMasked512const [a] x mask) +(VMOVDQU64Masked128 (VPSRLQ128const [a] x) mask) => (VPSRLQMasked128const [a] x mask) +(VMOVDQU64Masked256 (VPSRLQ256const [a] x) mask) => (VPSRLQMasked256const [a] x mask) +(VMOVDQU64Masked512 (VPSRLQ512const [a] x) mask) => (VPSRLQMasked512const [a] x mask) +(VPBLENDMBMasked512 dst (VGF2P8MULB512 x y) mask) => (VGF2P8MULBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPABSB512 x) mask) => (VPABSBMasked512Merging dst x mask) +(VPBLENDMBMasked512 dst (VPADDB512 x y) mask) => (VPADDBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPADDSB512 x y) mask) => (VPADDSBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPADDUSB512 x y) mask) => (VPADDUSBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPAVGB512 x y) mask) => (VPAVGBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPMAXSB512 x y) mask) => (VPMAXSBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPMAXUB512 x y) mask) => (VPMAXUBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPMINSB512 x y) mask) => (VPMINSBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPMINUB512 x y) mask) => (VPMINUBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPOPCNTB512 x) mask) => (VPOPCNTBMasked512Merging dst x mask) +(VPBLENDMBMasked512 dst (VPSHUFB512 x y) mask) => (VPSHUFBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPSUBB512 x y) mask) => (VPSUBBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPSUBSB512 x y) mask) => (VPSUBSBMasked512Merging dst x y mask) +(VPBLENDMBMasked512 dst (VPSUBUSB512 x y) mask) => (VPSUBUSBMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VADDPS512 x y) mask) => (VADDPSMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VCVTDQ2PS512 x) mask) => (VCVTDQ2PSMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VCVTTPS2UDQ512 x) mask) => (VCVTTPS2UDQMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VCVTUDQ2PS512 x) mask) => (VCVTUDQ2PSMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VDIVPS512 x y) mask) => (VDIVPSMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VMAXPS512 x y) mask) => (VMAXPSMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VMINPS512 x y) mask) => (VMINPSMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VMULPS512 x y) mask) => (VMULPSMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPABSD512 x) mask) => (VPABSDMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VPACKSSDW512 x y) mask) => (VPACKSSDWMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPACKUSDW512 x y) mask) => (VPACKUSDWMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPADDD512 x y) mask) => (VPADDDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPANDD512 x y) mask) => (VPANDDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPLZCNTD512 x) mask) => (VPLZCNTDMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VPMAXSD512 x y) mask) => (VPMAXSDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPMAXUD512 x y) mask) => (VPMAXUDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPMINSD512 x y) mask) => (VPMINSDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPMINUD512 x y) mask) => (VPMINUDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPMOVDB128_512 x) mask) => (VPMOVDBMasked128_512Merging dst x mask) +(VPBLENDMDMasked512 dst (VPMOVDW256 x) mask) => (VPMOVDWMasked256Merging dst x mask) +(VPBLENDMDMasked512 dst (VPMOVSDB128_512 x) mask) => (VPMOVSDBMasked128_512Merging dst x mask) +(VPBLENDMDMasked512 dst (VPMOVSDW256 x) mask) => (VPMOVSDWMasked256Merging dst x mask) +(VPBLENDMDMasked512 dst (VPMOVUSDB128_512 x) mask) => (VPMOVUSDBMasked128_512Merging dst x mask) +(VPBLENDMDMasked512 dst (VPMOVUSDW256 x) mask) => (VPMOVUSDWMasked256Merging dst x mask) +(VPBLENDMDMasked512 dst (VPMULLD512 x y) mask) => (VPMULLDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPOPCNTD512 x) mask) => (VPOPCNTDMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VPORD512 x y) mask) => (VPORDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPROLVD512 x y) mask) => (VPROLVDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPRORVD512 x y) mask) => (VPRORVDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPSHUFD512 [a] x) mask) => (VPSHUFDMasked512Merging dst [a] x mask) +(VPBLENDMDMasked512 dst (VPSLLD512const [a] x) mask) => (VPSLLDMasked512constMerging dst [a] x mask) +(VPBLENDMDMasked512 dst (VPSLLVD512 x y) mask) => (VPSLLVDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPSRAD512const [a] x) mask) => (VPSRADMasked512constMerging dst [a] x mask) +(VPBLENDMDMasked512 dst (VPSRAVD512 x y) mask) => (VPSRAVDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPSRLD512const [a] x) mask) => (VPSRLDMasked512constMerging dst [a] x mask) +(VPBLENDMDMasked512 dst (VPSRLVD512 x y) mask) => (VPSRLVDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPSUBD512 x y) mask) => (VPSUBDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VPXORD512 x y) mask) => (VPXORDMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VRCP14PS512 x) mask) => (VRCP14PSMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VREDUCEPS512 [a] x) mask) => (VREDUCEPSMasked512Merging dst [a] x mask) +(VPBLENDMDMasked512 dst (VRNDSCALEPS512 [a] x) mask) => (VRNDSCALEPSMasked512Merging dst [a] x mask) +(VPBLENDMDMasked512 dst (VRSQRT14PS512 x) mask) => (VRSQRT14PSMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VSCALEFPS512 x y) mask) => (VSCALEFPSMasked512Merging dst x y mask) +(VPBLENDMDMasked512 dst (VSQRTPS512 x) mask) => (VSQRTPSMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VSUBPS512 x y) mask) => (VSUBPSMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VADDPD512 x y) mask) => (VADDPDMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VCVTPD2PS256 x) mask) => (VCVTPD2PSMasked256Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTQQ2PD512 x) mask) => (VCVTQQ2PDMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTQQ2PS256 x) mask) => (VCVTQQ2PSMasked256Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTTPD2DQ256 x) mask) => (VCVTTPD2DQMasked256Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTTPD2QQ512 x) mask) => (VCVTTPD2QQMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTTPD2UDQ256 x) mask) => (VCVTTPD2UDQMasked256Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTTPD2UQQ512 x) mask) => (VCVTTPD2UQQMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTUQQ2PD512 x) mask) => (VCVTUQQ2PDMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTUQQ2PS256 x) mask) => (VCVTUQQ2PSMasked256Merging dst x mask) +(VPBLENDMQMasked512 dst (VDIVPD512 x y) mask) => (VDIVPDMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VMAXPD512 x y) mask) => (VMAXPDMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VMINPD512 x y) mask) => (VMINPDMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VMULPD512 x y) mask) => (VMULPDMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPABSQ512 x) mask) => (VPABSQMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VPADDQ512 x y) mask) => (VPADDQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPANDQ512 x y) mask) => (VPANDQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPLZCNTQ512 x) mask) => (VPLZCNTQMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VPMAXSQ512 x y) mask) => (VPMAXSQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPMAXUQ512 x y) mask) => (VPMAXUQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPMINSQ512 x y) mask) => (VPMINSQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPMINUQ512 x y) mask) => (VPMINUQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPMOVQB128_512 x) mask) => (VPMOVQBMasked128_512Merging dst x mask) +(VPBLENDMQMasked512 dst (VPMOVQD256 x) mask) => (VPMOVQDMasked256Merging dst x mask) +(VPBLENDMQMasked512 dst (VPMOVQW128_512 x) mask) => (VPMOVQWMasked128_512Merging dst x mask) +(VPBLENDMQMasked512 dst (VPMOVSQB128_512 x) mask) => (VPMOVSQBMasked128_512Merging dst x mask) +(VPBLENDMQMasked512 dst (VPMOVSQD256 x) mask) => (VPMOVSQDMasked256Merging dst x mask) +(VPBLENDMQMasked512 dst (VPMOVSQW128_512 x) mask) => (VPMOVSQWMasked128_512Merging dst x mask) +(VPBLENDMQMasked512 dst (VPMOVUSQB128_512 x) mask) => (VPMOVUSQBMasked128_512Merging dst x mask) +(VPBLENDMQMasked512 dst (VPMOVUSQD256 x) mask) => (VPMOVUSQDMasked256Merging dst x mask) +(VPBLENDMQMasked512 dst (VPMOVUSQW128_512 x) mask) => (VPMOVUSQWMasked128_512Merging dst x mask) +(VPBLENDMQMasked512 dst (VPMULLQ512 x y) mask) => (VPMULLQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPOPCNTQ512 x) mask) => (VPOPCNTQMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VPORQ512 x y) mask) => (VPORQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPROLVQ512 x y) mask) => (VPROLVQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPRORVQ512 x y) mask) => (VPRORVQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPSLLQ512const [a] x) mask) => (VPSLLQMasked512constMerging dst [a] x mask) +(VPBLENDMQMasked512 dst (VPSLLVQ512 x y) mask) => (VPSLLVQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPSRAQ512const [a] x) mask) => (VPSRAQMasked512constMerging dst [a] x mask) +(VPBLENDMQMasked512 dst (VPSRAVQ512 x y) mask) => (VPSRAVQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPSRLQ512const [a] x) mask) => (VPSRLQMasked512constMerging dst [a] x mask) +(VPBLENDMQMasked512 dst (VPSRLVQ512 x y) mask) => (VPSRLVQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPSUBQ512 x y) mask) => (VPSUBQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VPXORQ512 x y) mask) => (VPXORQMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VRCP14PD512 x) mask) => (VRCP14PDMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VREDUCEPD512 [a] x) mask) => (VREDUCEPDMasked512Merging dst [a] x mask) +(VPBLENDMQMasked512 dst (VRNDSCALEPD512 [a] x) mask) => (VRNDSCALEPDMasked512Merging dst [a] x mask) +(VPBLENDMQMasked512 dst (VRSQRT14PD512 x) mask) => (VRSQRT14PDMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VSCALEFPD512 x y) mask) => (VSCALEFPDMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VSQRTPD512 x) mask) => (VSQRTPDMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VSUBPD512 x y) mask) => (VSUBPDMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPABSW512 x) mask) => (VPABSWMasked512Merging dst x mask) +(VPBLENDMWMasked512 dst (VPADDSW512 x y) mask) => (VPADDSWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPADDUSW512 x y) mask) => (VPADDUSWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPADDW512 x y) mask) => (VPADDWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPAVGW512 x y) mask) => (VPAVGWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPMADDUBSW512 x y) mask) => (VPMADDUBSWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPMADDWD512 x y) mask) => (VPMADDWDMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPMAXSW512 x y) mask) => (VPMAXSWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPMAXUW512 x y) mask) => (VPMAXUWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPMINSW512 x y) mask) => (VPMINSWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPMINUW512 x y) mask) => (VPMINUWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPMOVSWB256 x) mask) => (VPMOVSWBMasked256Merging dst x mask) +(VPBLENDMWMasked512 dst (VPMOVUSWB256 x) mask) => (VPMOVUSWBMasked256Merging dst x mask) +(VPBLENDMWMasked512 dst (VPMOVWB256 x) mask) => (VPMOVWBMasked256Merging dst x mask) +(VPBLENDMWMasked512 dst (VPMULHUW512 x y) mask) => (VPMULHUWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPMULHW512 x y) mask) => (VPMULHWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPMULLW512 x y) mask) => (VPMULLWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPOPCNTW512 x) mask) => (VPOPCNTWMasked512Merging dst x mask) +(VPBLENDMWMasked512 dst (VPSHUFHW512 [a] x) mask) => (VPSHUFHWMasked512Merging dst [a] x mask) +(VPBLENDMWMasked512 dst (VPSHUFLW512 [a] x) mask) => (VPSHUFLWMasked512Merging dst [a] x mask) +(VPBLENDMWMasked512 dst (VPSLLVW512 x y) mask) => (VPSLLVWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPSLLW512const [a] x) mask) => (VPSLLWMasked512constMerging dst [a] x mask) +(VPBLENDMWMasked512 dst (VPSRAVW512 x y) mask) => (VPSRAVWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPSRAW512const [a] x) mask) => (VPSRAWMasked512constMerging dst [a] x mask) +(VPBLENDMWMasked512 dst (VPSRLVW512 x y) mask) => (VPSRLVWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPSRLW512const [a] x) mask) => (VPSRLWMasked512constMerging dst [a] x mask) +(VPBLENDMWMasked512 dst (VPSUBSW512 x y) mask) => (VPSUBSWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPSUBUSW512 x y) mask) => (VPSUBUSWMasked512Merging dst x y mask) +(VPBLENDMWMasked512 dst (VPSUBW512 x y) mask) => (VPSUBWMasked512Merging dst x y mask) +(VPBLENDVB128 dst (VADDPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VADDPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VBROADCASTSD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSDMasked256Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VBROADCASTSD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSDMasked512Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VBROADCASTSS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VBROADCASTSS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked256Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VBROADCASTSS512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked512Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTDQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTDQ2PS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTPD2PSX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPD2PSXMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTPS2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPS2PDMasked256Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTQQ2PD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTQQ2PSX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTTPD2DQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQXMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTTPD2QQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTTPD2UDQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQXMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTTPD2UQQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UQQMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTTPS2DQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2DQMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTTPS2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked256Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTTPS2UDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTTPS2UQQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked256Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTUDQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTUDQ2PS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTUQQ2PD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTUQQ2PSX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VDIVPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VDIVPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VGF2P8MULB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VMAXPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMAXPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VMAXPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMAXPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VMINPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMINPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VMINPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMINPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VMULPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMULPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VMULPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMULPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPABSB128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPABSBMasked128Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPABSD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPABSDMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPABSQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPABSQMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPABSW128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPABSWMasked128Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPACKSSDW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPACKSSDWMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPACKUSDW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPACKUSDWMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPADDB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPADDD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPADDQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPADDSB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPADDSW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPADDUSB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDUSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPADDUSW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDUSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPADDW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPAVGB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPAVGBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPAVGW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPAVGWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTB128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTBMasked128Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTB256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTBMasked256Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTB512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTBMasked512Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTDMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTDMasked256Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTDMasked512Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTQMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTQMasked256Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTQMasked512Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTW128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTWMasked128Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTW256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTWMasked256Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPBROADCASTW512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPBROADCASTWMasked512Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPLZCNTD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPLZCNTDMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPLZCNTQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPLZCNTQMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMADDUBSW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMADDUBSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMADDWD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMADDWDMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMAXSB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMAXSD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXSDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMAXSQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXSQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMAXSW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMAXUB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXUBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMAXUD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXUDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMAXUQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXUQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMAXUW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXUWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMINSB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMINSD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINSDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMINSQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINSQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMINSW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMINUB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINUBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMINUD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINUDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMINUQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINUQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMINUW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINUWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVDB128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVDBMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMOVDW128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVDWMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMOVQB128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVQBMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMOVQD128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVQDMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMOVQW128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVQWMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMOVSDB128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSDBMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMOVSDW128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSDWMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMOVSQB128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSQBMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMOVSQD128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSQDMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMOVSQW128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSQWMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMOVSWB128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSWBMasked128_128Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVSXBD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXBDMasked128Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVSXBD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXBDMasked256Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVSXBD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXBDMasked512Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVSXBQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXBQMasked128Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVSXBQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXBQMasked256Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVSXBQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXBQMasked512Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVSXBW128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXBWMasked128Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVSXBW256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXBWMasked256Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVSXDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXDQMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMOVSXDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXDQMasked256Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMOVSXWD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXWDMasked128Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVSXWD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXWDMasked256Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVSXWQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXWQMasked128Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVSXWQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXWQMasked256Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVSXWQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXWQMasked512Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVUSDB128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSDBMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMOVUSDW128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSDWMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMOVUSQB128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSQBMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMOVUSQD128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSQDMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMOVUSQW128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSQWMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMOVUSWB128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSWBMasked128_128Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVWB128_128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVWBMasked128_128Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVZXBD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXBDMasked128Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVZXBD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXBDMasked256Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVZXBD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXBDMasked512Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVZXBQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXBQMasked128Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVZXBQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXBQMasked256Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVZXBQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXBQMasked512Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVZXBW128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXBWMasked128Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVZXBW256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXBWMasked256Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPMOVZXDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXDQMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMOVZXDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXDQMasked256Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMOVZXWD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXWDMasked128Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVZXWD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXWDMasked256Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVZXWQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXWQMasked128Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVZXWQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXWQMasked256Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMOVZXWQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXWQMasked512Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMULHUW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMULHUWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMULHW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMULHWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPMULLD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMULLDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPMULLQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMULLQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPMULLW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMULLWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPOPCNTB128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPOPCNTBMasked128Merging dst x (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPOPCNTD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPOPCNTDMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPOPCNTQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPOPCNTQMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPOPCNTW128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPOPCNTWMasked128Merging dst x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPROLVD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPROLVDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPROLVQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPROLVQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPRORVD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPRORVDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPRORVQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPRORVQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPSHUFB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSHUFBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPSHUFD128 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSHUFDMasked128Merging dst [a] x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPSHUFHW128 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSHUFHWMasked128Merging dst [a] x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPSHUFLW128 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSHUFLWMasked128Merging dst [a] x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPSLLD128const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLDMasked128constMerging dst [a] x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPSLLQ128const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLQMasked128constMerging dst [a] x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPSLLVD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLVDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPSLLVQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLVQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPSLLVW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLVWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPSLLW128const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLWMasked128constMerging dst [a] x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPSRAD128const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRADMasked128constMerging dst [a] x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPSRAQ128const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRAQMasked128constMerging dst [a] x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPSRAVD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRAVDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPSRAVQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRAVQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPSRAVW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRAVWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPSRAW128const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRAWMasked128constMerging dst [a] x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPSRLD128const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLDMasked128constMerging dst [a] x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPSRLQ128const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLQMasked128constMerging dst [a] x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPSRLVD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLVDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPSRLVQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLVQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPSRLVW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLVWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPSRLW128const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLWMasked128constMerging dst [a] x (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPSUBB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPSUBD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VPSUBQ128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VPSUBSB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPSUBSW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPSUBUSB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBUSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) +(VPBLENDVB128 dst (VPSUBUSW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBUSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VPSUBW128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) +(VPBLENDVB128 dst (VRCP14PD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VRCP14PDMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VREDUCEPD128 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VREDUCEPDMasked128Merging dst [a] x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VREDUCEPS128 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VREDUCEPSMasked128Merging dst [a] x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VRNDSCALEPD128 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VRNDSCALEPDMasked128Merging dst [a] x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VRNDSCALEPS128 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VRNDSCALEPSMasked128Merging dst [a] x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VRSQRT14PD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VRSQRT14PDMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VSCALEFPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSCALEFPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VSCALEFPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSCALEFPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VSQRTPD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSQRTPDMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VSQRTPS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSQRTPSMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VSUBPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSUBPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VSUBPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSUBPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) +(VPBLENDVB256 dst (VADDPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VADDPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTDQ2PD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTDQ2PS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTPD2PSY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPD2PSYMasked128Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTPS2PD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPS2PDMasked512Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTQQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTQQ2PSY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTTPD2DQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQYMasked128Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTTPD2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTTPD2UDQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQYMasked128Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTTPD2UQQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UQQMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTTPS2DQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2DQMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTTPS2QQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked512Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTTPS2UDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTTPS2UQQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked512Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTUDQ2PD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTUDQ2PS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTUQQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTUQQ2PSY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VDIVPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VDIVPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VGF2P8MULB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VMAXPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMAXPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VMAXPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMAXPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VMINPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMINPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VMINPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMINPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VMULPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMULPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VMULPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMULPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPABSB256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPABSBMasked256Merging dst x (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPABSD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPABSDMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPABSQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPABSQMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPABSW256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPABSWMasked256Merging dst x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPACKSSDW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPACKSSDWMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPACKUSDW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPACKUSDWMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPADDB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPADDD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPADDQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPADDSB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPADDSW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPADDUSB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDUSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPADDUSW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDUSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPADDW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPADDWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPAVGB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPAVGBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPAVGW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPAVGWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPLZCNTD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPLZCNTDMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPLZCNTQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPLZCNTQMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMADDUBSW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMADDUBSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMADDWD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMADDWDMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMAXSB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPMAXSD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXSDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMAXSQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXSQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMAXSW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMAXUB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXUBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPMAXUD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXUDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMAXUQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXUQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMAXUW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMAXUWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMINSB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPMINSD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINSDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMINSQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINSQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMINSW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMINUB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINUBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPMINUD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINUDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMINUQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINUQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMINUW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMINUWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMOVDB128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVDBMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMOVDW128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVDWMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMOVQB128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVQBMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMOVQD128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVQDMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMOVQW128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVQWMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMOVSDB128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSDBMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMOVSDW128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSDWMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMOVSQB128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSQBMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMOVSQD128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSQDMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMOVSQW128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSQWMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMOVSWB128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSWBMasked128_256Merging dst x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMOVSXBW512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXBWMasked512Merging dst x (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPMOVSXDQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXDQMasked512Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMOVSXWD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVSXWDMasked512Merging dst x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMOVUSDB128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSDBMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMOVUSDW128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSDWMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMOVUSQB128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSQBMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMOVUSQD128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSQDMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMOVUSQW128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSQWMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMOVUSWB128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVUSWBMasked128_256Merging dst x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMOVWB128_256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVWBMasked128_256Merging dst x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMOVZXBW512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXBWMasked512Merging dst x (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPMOVZXDQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXDQMasked512Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMOVZXWD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVZXWDMasked512Merging dst x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMULHUW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMULHUWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMULHW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMULHWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPMULLD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMULLDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPMULLQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMULLQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPMULLW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMULLWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPOPCNTB256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPOPCNTBMasked256Merging dst x (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPOPCNTD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPOPCNTDMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPOPCNTQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPOPCNTQMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPOPCNTW256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPOPCNTWMasked256Merging dst x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPROLVD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPROLVDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPROLVQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPROLVQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPRORVD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPRORVDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPRORVQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPRORVQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPSHUFB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSHUFBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPSHUFD256 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSHUFDMasked256Merging dst [a] x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPSHUFHW256 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSHUFHWMasked256Merging dst [a] x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPSHUFLW256 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSHUFLWMasked256Merging dst [a] x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPSLLD256const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLDMasked256constMerging dst [a] x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPSLLQ256const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLQMasked256constMerging dst [a] x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPSLLVD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLVDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPSLLVQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLVQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPSLLVW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLVWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPSLLW256const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSLLWMasked256constMerging dst [a] x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPSRAD256const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRADMasked256constMerging dst [a] x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPSRAQ256const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRAQMasked256constMerging dst [a] x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPSRAVD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRAVDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPSRAVQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRAVQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPSRAVW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRAVWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPSRAW256const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRAWMasked256constMerging dst [a] x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPSRLD256const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLDMasked256constMerging dst [a] x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPSRLQ256const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLQMasked256constMerging dst [a] x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPSRLVD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLVDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPSRLVQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLVQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPSRLVW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLVWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPSRLW256const [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSRLWMasked256constMerging dst [a] x (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPSUBB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPSUBD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VPSUBQ256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VPSUBSB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPSUBSW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPSUBUSB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBUSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) +(VPBLENDVB256 dst (VPSUBUSW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBUSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VPSUBW256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPSUBWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) +(VPBLENDVB256 dst (VRCP14PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VRCP14PDMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VREDUCEPD256 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VREDUCEPDMasked256Merging dst [a] x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VREDUCEPS256 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VREDUCEPSMasked256Merging dst [a] x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VRNDSCALEPD256 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VRNDSCALEPDMasked256Merging dst [a] x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VRNDSCALEPS256 [a] x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VRNDSCALEPSMasked256Merging dst [a] x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VRSQRT14PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VRSQRT14PDMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VSCALEFPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSCALEFPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VSCALEFPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSCALEFPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VSQRTPD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSQRTPDMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VSQRTPS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSQRTPSMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VSUBPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSUBPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VSUBPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSUBPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) +(VAESDECLAST128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VAESDECLAST128load {sym} [off] x ptr mem) // vregMem +(VAESDECLAST256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VAESDECLAST256load {sym} [off] x ptr mem) // vregMem +(VAESDEC128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VAESDEC128load {sym} [off] x ptr mem) // vregMem +(VAESDEC256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VAESDEC256load {sym} [off] x ptr mem) // vregMem +(VAESENCLAST128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VAESENCLAST128load {sym} [off] x ptr mem) // vregMem +(VAESENCLAST256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VAESENCLAST256load {sym} [off] x ptr mem) // vregMem +(VAESENC128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VAESENC128load {sym} [off] x ptr mem) // vregMem +(VAESENC256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VAESENC256load {sym} [off] x ptr mem) // vregMem +(VAESIMC128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VAESIMC128load {sym} [off] ptr mem) // vregMem +(VAESKEYGENASSIST128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VAESKEYGENASSIST128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPABSB128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSB128load {sym} [off] ptr mem) // vregMem +(VPABSB256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSB256load {sym} [off] ptr mem) // vregMem +(VPABSW128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSW128load {sym} [off] ptr mem) // vregMem +(VPABSW256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSW256load {sym} [off] ptr mem) // vregMem +(VPABSD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSD128load {sym} [off] ptr mem) // vregMem +(VPABSD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSD256load {sym} [off] ptr mem) // vregMem +(VPABSD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSD512load {sym} [off] ptr mem) // vregMem +(VPABSQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSQ128load {sym} [off] ptr mem) // vregMem +(VPABSQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSQ256load {sym} [off] ptr mem) // vregMem +(VPABSQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSQ512load {sym} [off] ptr mem) // vregMem +(VPABSBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSBMasked128load {sym} [off] ptr mask mem) // vregMem +(VPABSBMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSBMasked256load {sym} [off] ptr mask mem) // vregMem +(VPABSWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSWMasked128load {sym} [off] ptr mask mem) // vregMem +(VPABSWMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSWMasked256load {sym} [off] ptr mask mem) // vregMem +(VPABSDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSDMasked128load {sym} [off] ptr mask mem) // vregMem +(VPABSDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPABSDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSDMasked512load {sym} [off] ptr mask mem) // vregMem +(VPABSQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSQMasked128load {sym} [off] ptr mask mem) // vregMem +(VPABSQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSQMasked256load {sym} [off] ptr mask mem) // vregMem +(VPABSQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSQMasked512load {sym} [off] ptr mask mem) // vregMem +(VADDPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPS128load {sym} [off] x ptr mem) // vregMem +(VADDPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPS256load {sym} [off] x ptr mem) // vregMem +(VADDPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPS512load {sym} [off] x ptr mem) // vregMem +(VADDPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPD128load {sym} [off] x ptr mem) // vregMem +(VADDPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPD256load {sym} [off] x ptr mem) // vregMem +(VADDPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPD512load {sym} [off] x ptr mem) // vregMem +(VPADDB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDB128load {sym} [off] x ptr mem) // vregMem +(VPADDB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDB256load {sym} [off] x ptr mem) // vregMem +(VPADDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDW128load {sym} [off] x ptr mem) // vregMem +(VPADDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDW256load {sym} [off] x ptr mem) // vregMem +(VPADDD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDD128load {sym} [off] x ptr mem) // vregMem +(VPADDD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDD256load {sym} [off] x ptr mem) // vregMem +(VPADDD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDD512load {sym} [off] x ptr mem) // vregMem +(VPADDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDQ128load {sym} [off] x ptr mem) // vregMem +(VPADDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDQ256load {sym} [off] x ptr mem) // vregMem +(VPADDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDQ512load {sym} [off] x ptr mem) // vregMem +(VPDPWSSD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSD128load {sym} [off] x y ptr mem) // vregMem +(VPDPWSSD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSD256load {sym} [off] x y ptr mem) // vregMem +(VPDPWSSD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSD512load {sym} [off] x y ptr mem) // vregMem +(VPDPWSSDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPDPWSSDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPDPWSSDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VADDPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPSMasked128load {sym} [off] x ptr mask mem) // vregMem +(VADDPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPSMasked256load {sym} [off] x ptr mask mem) // vregMem +(VADDPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPSMasked512load {sym} [off] x ptr mask mem) // vregMem +(VADDPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VADDPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VADDPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPADDBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPADDBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPADDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPADDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPADDDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPADDDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPADDDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPADDQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPADDQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPADDQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VADDSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDSUBPS128load {sym} [off] x ptr mem) // vregMem +(VADDSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDSUBPS256load {sym} [off] x ptr mem) // vregMem +(VADDSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDSUBPD128load {sym} [off] x ptr mem) // vregMem +(VADDSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDSUBPD256load {sym} [off] x ptr mem) // vregMem +(VPADDSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDSB128load {sym} [off] x ptr mem) // vregMem +(VPADDSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDSB256load {sym} [off] x ptr mem) // vregMem +(VPADDSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDSW128load {sym} [off] x ptr mem) // vregMem +(VPADDSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDSW256load {sym} [off] x ptr mem) // vregMem +(VPADDUSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDUSB128load {sym} [off] x ptr mem) // vregMem +(VPADDUSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDUSB256load {sym} [off] x ptr mem) // vregMem +(VPADDUSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDUSW128load {sym} [off] x ptr mem) // vregMem +(VPADDUSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDUSW256load {sym} [off] x ptr mem) // vregMem +(VPADDSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDSBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPADDSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDSBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPADDSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDSWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPADDSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDSWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPADDUSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDUSBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPADDUSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDUSBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPADDUSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDUSWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPADDUSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDUSWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPAND128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPAND128load {sym} [off] x ptr mem) // vregMem +(VPAND256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPAND256load {sym} [off] x ptr mem) // vregMem +(VPANDD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPANDD512load {sym} [off] x ptr mem) // vregMem +(VPANDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPANDQ512load {sym} [off] x ptr mem) // vregMem +(VPANDDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPANDDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPANDDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPANDQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPANDQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPANDQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPANDN128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPANDN128load {sym} [off] x ptr mem) // vregMem +(VPANDN256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPANDN256load {sym} [off] x ptr mem) // vregMem +(VPANDND512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPANDND512load {sym} [off] x ptr mem) // vregMem +(VPANDNQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPANDNQ512load {sym} [off] x ptr mem) // vregMem +(VPANDNDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPANDNDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPANDNDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPANDNQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPANDNQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPANDNQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPAVGB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPAVGB128load {sym} [off] x ptr mem) // vregMem +(VPAVGB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPAVGB256load {sym} [off] x ptr mem) // vregMem +(VPAVGW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPAVGW128load {sym} [off] x ptr mem) // vregMem +(VPAVGW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPAVGW256load {sym} [off] x ptr mem) // vregMem +(VPAVGBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPAVGBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPAVGBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPAVGBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPAVGWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPAVGWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPAVGWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPAVGWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VROUNDPS128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VROUNDPS128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VROUNDPS256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VROUNDPS256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VROUNDPD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VROUNDPD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VROUNDPD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VROUNDPD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VRNDSCALEPS128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPS128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VRNDSCALEPS256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPS256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VRNDSCALEPS512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPS512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VRNDSCALEPD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VRNDSCALEPD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VRNDSCALEPD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPD512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VRNDSCALEPSMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPSMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VRNDSCALEPSMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPSMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VRNDSCALEPSMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPSMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VRNDSCALEPDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VRNDSCALEPDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VRNDSCALEPDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRNDSCALEPDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VREDUCEPS128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPS128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VREDUCEPS256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPS256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VREDUCEPS512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPS512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VREDUCEPD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VREDUCEPD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VREDUCEPD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPD512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VREDUCEPSMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPSMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VREDUCEPSMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPSMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VREDUCEPSMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPSMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VREDUCEPDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VREDUCEPDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VREDUCEPDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VREDUCEPDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VHADDPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VHADDPS128load {sym} [off] x ptr mem) // vregMem +(VHADDPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VHADDPD128load {sym} [off] x ptr mem) // vregMem +(VPHADDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHADDW128load {sym} [off] x ptr mem) // vregMem +(VPHADDD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHADDD128load {sym} [off] x ptr mem) // vregMem +(VHADDPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VHADDPS256load {sym} [off] x ptr mem) // vregMem +(VHADDPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VHADDPD256load {sym} [off] x ptr mem) // vregMem +(VPHADDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHADDW256load {sym} [off] x ptr mem) // vregMem +(VPHADDD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHADDD256load {sym} [off] x ptr mem) // vregMem +(VPHADDSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHADDSW128load {sym} [off] x ptr mem) // vregMem +(VPHADDSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHADDSW256load {sym} [off] x ptr mem) // vregMem +(VPERMI2B128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2B128load {sym} [off] x y ptr mem) // vregMem +(VPERMI2B256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2B256load {sym} [off] x y ptr mem) // vregMem +(VPERMI2W128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2W128load {sym} [off] x y ptr mem) // vregMem +(VPERMI2W256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2W256load {sym} [off] x y ptr mem) // vregMem +(VPERMI2PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PS128load {sym} [off] x y ptr mem) // vregMem +(VPERMI2D128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2D128load {sym} [off] x y ptr mem) // vregMem +(VPERMI2PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PS256load {sym} [off] x y ptr mem) // vregMem +(VPERMI2D256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2D256load {sym} [off] x y ptr mem) // vregMem +(VPERMI2PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PS512load {sym} [off] x y ptr mem) // vregMem +(VPERMI2D512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2D512load {sym} [off] x y ptr mem) // vregMem +(VPERMI2PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PD128load {sym} [off] x y ptr mem) // vregMem +(VPERMI2Q128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2Q128load {sym} [off] x y ptr mem) // vregMem +(VPERMI2PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PD256load {sym} [off] x y ptr mem) // vregMem +(VPERMI2Q256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2Q256load {sym} [off] x y ptr mem) // vregMem +(VPERMI2PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PD512load {sym} [off] x y ptr mem) // vregMem +(VPERMI2Q512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2Q512load {sym} [off] x y ptr mem) // vregMem +(VPERM2F128256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERM2F128256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPERM2I128256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERM2I128256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPERMI2BMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2BMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2BMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2BMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2WMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2WMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2WMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2WMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PSMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2DMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2DMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PSMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2DMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2DMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PSMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2DMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2DMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2QMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2QMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VPERMI2QMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VPALIGNR128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPALIGNR128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPALIGNR256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPALIGNR256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPALIGNRMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPALIGNRMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPALIGNRMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPALIGNRMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VHSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VHSUBPS128load {sym} [off] x ptr mem) // vregMem +(VHSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VHSUBPD128load {sym} [off] x ptr mem) // vregMem +(VPHSUBW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHSUBW128load {sym} [off] x ptr mem) // vregMem +(VPHSUBD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHSUBD128load {sym} [off] x ptr mem) // vregMem +(VHSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VHSUBPS256load {sym} [off] x ptr mem) // vregMem +(VHSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VHSUBPD256load {sym} [off] x ptr mem) // vregMem +(VPHSUBW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHSUBW256load {sym} [off] x ptr mem) // vregMem +(VPHSUBD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHSUBD256load {sym} [off] x ptr mem) // vregMem +(VPHSUBSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHSUBSW128load {sym} [off] x ptr mem) // vregMem +(VPHSUBSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPHSUBSW256load {sym} [off] x ptr mem) // vregMem +(VCVTPD2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPD2PSX128load {sym} [off] ptr mem) // vregMem +(VCVTPD2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPD2PSY128load {sym} [off] ptr mem) // vregMem +(VCVTPD2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPD2PS256load {sym} [off] ptr mem) // vregMem +(VCVTDQ2PS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PS128load {sym} [off] ptr mem) // vregMem +(VCVTDQ2PS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PS256load {sym} [off] ptr mem) // vregMem +(VCVTDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PS512load {sym} [off] ptr mem) // vregMem +(VCVTQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSX128load {sym} [off] ptr mem) // vregMem +(VCVTQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSY128load {sym} [off] ptr mem) // vregMem +(VCVTQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PS256load {sym} [off] ptr mem) // vregMem +(VCVTUDQ2PS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS128load {sym} [off] ptr mem) // vregMem +(VCVTUDQ2PS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS256load {sym} [off] ptr mem) // vregMem +(VCVTUDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS512load {sym} [off] ptr mem) // vregMem +(VCVTUQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSX128load {sym} [off] ptr mem) // vregMem +(VCVTUQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSY128load {sym} [off] ptr mem) // vregMem +(VCVTUQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PS256load {sym} [off] ptr mem) // vregMem +(VCVTPD2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPD2PSXMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTPD2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPD2PSYMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTPD2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPD2PSMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSXMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSYMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTUDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTUDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTUDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTUQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSXMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTUQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSYMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTUQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTPS2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2PD256load {sym} [off] ptr mem) // vregMem +(VCVTPS2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2PD512load {sym} [off] ptr mem) // vregMem +(VCVTDQ2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PD256load {sym} [off] ptr mem) // vregMem +(VCVTDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PD512load {sym} [off] ptr mem) // vregMem +(VCVTQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD128load {sym} [off] ptr mem) // vregMem +(VCVTQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD256load {sym} [off] ptr mem) // vregMem +(VCVTQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD512load {sym} [off] ptr mem) // vregMem +(VCVTUDQ2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PD256load {sym} [off] ptr mem) // vregMem +(VCVTUDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PD512load {sym} [off] ptr mem) // vregMem +(VCVTUQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD128load {sym} [off] ptr mem) // vregMem +(VCVTUQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD256load {sym} [off] ptr mem) // vregMem +(VCVTUQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD512load {sym} [off] ptr mem) // vregMem +(VCVTPS2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2PDMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTPS2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2PDMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PDMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PDMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTUDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PDMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTUDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PDMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTUQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTUQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTUQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTTPS2DQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ128load {sym} [off] ptr mem) // vregMem +(VCVTTPS2DQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ256load {sym} [off] ptr mem) // vregMem +(VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ512load {sym} [off] ptr mem) // vregMem +(VCVTTPD2DQX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQX128load {sym} [off] ptr mem) // vregMem +(VCVTTPD2DQY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQY128load {sym} [off] ptr mem) // vregMem +(VCVTTPD2DQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQ256load {sym} [off] ptr mem) // vregMem +(VCVTTPS2DQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTTPS2DQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTTPS2DQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2DQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQXMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2DQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQYMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2DQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTTPS2QQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQ256load {sym} [off] ptr mem) // vregMem +(VCVTTPS2QQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQ512load {sym} [off] ptr mem) // vregMem +(VCVTTPD2QQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ128load {sym} [off] ptr mem) // vregMem +(VCVTTPD2QQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ256load {sym} [off] ptr mem) // vregMem +(VCVTTPD2QQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ512load {sym} [off] ptr mem) // vregMem +(VCVTTPS2QQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTTPS2QQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2QQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2QQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2QQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ128load {sym} [off] ptr mem) // vregMem +(VCVTTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ256load {sym} [off] ptr mem) // vregMem +(VCVTTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ512load {sym} [off] ptr mem) // vregMem +(VCVTTPD2UDQX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQX128load {sym} [off] ptr mem) // vregMem +(VCVTTPD2UDQY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQY128load {sym} [off] ptr mem) // vregMem +(VCVTTPD2UDQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQ256load {sym} [off] ptr mem) // vregMem +(VCVTTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2UDQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQXMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2UDQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQYMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2UDQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTTPS2UQQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQ256load {sym} [off] ptr mem) // vregMem +(VCVTTPS2UQQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQ512load {sym} [off] ptr mem) // vregMem +(VCVTTPD2UQQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ128load {sym} [off] ptr mem) // vregMem +(VCVTTPD2UQQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ256load {sym} [off] ptr mem) // vregMem +(VCVTTPD2UQQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ512load {sym} [off] ptr mem) // vregMem +(VCVTTPS2UQQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTTPS2UQQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQMasked512load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2UQQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked128load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2UQQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked256load {sym} [off] ptr mask mem) // vregMem +(VCVTTPD2UQQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked512load {sym} [off] ptr mask mem) // vregMem +(VDIVPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS128load {sym} [off] x ptr mem) // vregMem +(VDIVPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS256load {sym} [off] x ptr mem) // vregMem +(VDIVPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS512load {sym} [off] x ptr mem) // vregMem +(VDIVPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD128load {sym} [off] x ptr mem) // vregMem +(VDIVPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD256load {sym} [off] x ptr mem) // vregMem +(VDIVPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD512load {sym} [off] x ptr mem) // vregMem +(VDIVPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked128load {sym} [off] x ptr mask mem) // vregMem +(VDIVPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked256load {sym} [off] x ptr mask mem) // vregMem +(VDIVPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked512load {sym} [off] x ptr mask mem) // vregMem +(VDIVPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VDIVPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VDIVPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMADDWD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMADDWD128load {sym} [off] x ptr mem) // vregMem +(VPMADDWD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMADDWD256load {sym} [off] x ptr mem) // vregMem +(VPMADDWDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMADDWDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMADDWDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMADDWDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMADDUBSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMADDUBSW128load {sym} [off] x ptr mem) // vregMem +(VPMADDUBSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMADDUBSW256load {sym} [off] x ptr mem) // vregMem +(VPMADDUBSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMADDUBSWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMADDUBSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMADDUBSWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPCMPEQB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQB128load {sym} [off] x ptr mem) // vregMem +(VPCMPEQB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQB256load {sym} [off] x ptr mem) // vregMem +(VPCMPEQW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQW128load {sym} [off] x ptr mem) // vregMem +(VPCMPEQW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQW256load {sym} [off] x ptr mem) // vregMem +(VPCMPEQD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQD128load {sym} [off] x ptr mem) // vregMem +(VPCMPEQD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQD256load {sym} [off] x ptr mem) // vregMem +(VPCMPEQD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQD512load {sym} [off] x ptr mem) // vregMem +(VPCMPEQQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQQ128load {sym} [off] x ptr mem) // vregMem +(VPCMPEQQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQQ256load {sym} [off] x ptr mem) // vregMem +(VPCMPEQQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQQ512load {sym} [off] x ptr mem) // vregMem +(VCMPPS128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCMPPS128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VCMPPS256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCMPPS256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VCMPPS512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCMPPS512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VCMPPD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCMPPD128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VCMPPD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCMPPD256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VCMPPD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCMPPD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VCMPPSMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCMPPSMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VCMPPSMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCMPPSMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VCMPPSMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCMPPSMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VCMPPDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCMPPDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VCMPPDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCMPPDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VCMPPDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCMPPDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPBMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPBMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPUBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPUBMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPUBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPUBMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPUWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPUWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPUWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPUWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPUDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPUDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPUDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPUDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPUDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPUDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPUQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPUQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPUQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPUQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPCMPUQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPCMPUQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VEXPANDPSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VEXPANDPSMasked128load {sym} [off] ptr mask mem) // vregMem +(VEXPANDPSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VEXPANDPSMasked256load {sym} [off] ptr mask mem) // vregMem +(VEXPANDPDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VEXPANDPDMasked128load {sym} [off] ptr mask mem) // vregMem +(VEXPANDPDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VEXPANDPDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPEXPANDBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPEXPANDBMasked128load {sym} [off] ptr mask mem) // vregMem +(VPEXPANDBMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPEXPANDBMasked256load {sym} [off] ptr mask mem) // vregMem +(VPEXPANDWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPEXPANDWMasked128load {sym} [off] ptr mask mem) // vregMem +(VPEXPANDWMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPEXPANDWMasked256load {sym} [off] ptr mask mem) // vregMem +(VPEXPANDDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPEXPANDDMasked128load {sym} [off] ptr mask mem) // vregMem +(VPEXPANDDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPEXPANDDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPEXPANDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPEXPANDQMasked128load {sym} [off] ptr mask mem) // vregMem +(VPEXPANDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPEXPANDQMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXBQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBQ128load {sym} [off] ptr mem) // vregMem +(VPMOVSXWQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWQ128load {sym} [off] ptr mem) // vregMem +(VPMOVSXDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXDQ128load {sym} [off] ptr mem) // vregMem +(VPMOVSXWQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWQMasked128load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXDQMasked128load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXBQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBQ128load {sym} [off] ptr mem) // vregMem +(VPMOVZXWQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWQ128load {sym} [off] ptr mem) // vregMem +(VPMOVZXDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXDQ128load {sym} [off] ptr mem) // vregMem +(VPMOVZXWQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWQMasked128load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXDQMasked128load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXBD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBD128load {sym} [off] ptr mem) // vregMem +(VPMOVSXWD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWD128load {sym} [off] ptr mem) // vregMem +(VPMOVSXBDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBDMasked128load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXWDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWDMasked128load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXBQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBQ256load {sym} [off] ptr mem) // vregMem +(VPMOVSXWQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWQ256load {sym} [off] ptr mem) // vregMem +(VPMOVSXBQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBQMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXWQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWQMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXBD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBD128load {sym} [off] ptr mem) // vregMem +(VPMOVZXWD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWD128load {sym} [off] ptr mem) // vregMem +(VPMOVZXBDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBDMasked128load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXWDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWDMasked128load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXBQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBQ256load {sym} [off] ptr mem) // vregMem +(VPMOVZXWQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWQ256load {sym} [off] ptr mem) // vregMem +(VPMOVZXBQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBQMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXWQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWQMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXBW128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBW128load {sym} [off] ptr mem) // vregMem +(VPMOVSXBWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBWMasked128load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXBD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBD256load {sym} [off] ptr mem) // vregMem +(VPMOVSXBDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXBQ512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBQ512load {sym} [off] ptr mem) // vregMem +(VPMOVSXBQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBQMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXBW128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBW128load {sym} [off] ptr mem) // vregMem +(VPMOVZXBWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBWMasked128load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXBD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBD256load {sym} [off] ptr mem) // vregMem +(VPMOVZXBDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXBQ512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBQ512load {sym} [off] ptr mem) // vregMem +(VPMOVZXBQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBQMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXBW256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBW256load {sym} [off] ptr mem) // vregMem +(VPMOVSXBW512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBW512load {sym} [off] ptr mem) // vregMem +(VPMOVSXBWMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBWMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXBWMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBWMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXBD512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBD512load {sym} [off] ptr mem) // vregMem +(VPMOVSXWD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWD256load {sym} [off] ptr mem) // vregMem +(VPMOVSXWD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWD512load {sym} [off] ptr mem) // vregMem +(VPMOVSXBDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXBDMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXWDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXWDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWDMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXWQ512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWQ512load {sym} [off] ptr mem) // vregMem +(VPMOVSXDQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXDQ256load {sym} [off] ptr mem) // vregMem +(VPMOVSXDQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXDQ512load {sym} [off] ptr mem) // vregMem +(VPMOVSXWQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXWQMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXDQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXDQMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVSXDQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVSXDQMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXBW256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBW256load {sym} [off] ptr mem) // vregMem +(VPMOVZXBW512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBW512load {sym} [off] ptr mem) // vregMem +(VPMOVZXBWMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBWMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXBWMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBWMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXBD512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBD512load {sym} [off] ptr mem) // vregMem +(VPMOVZXWD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWD256load {sym} [off] ptr mem) // vregMem +(VPMOVZXWD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWD512load {sym} [off] ptr mem) // vregMem +(VPMOVZXBDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXBDMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXWDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXWDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWDMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXWQ512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWQ512load {sym} [off] ptr mem) // vregMem +(VPMOVZXDQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXDQ256load {sym} [off] ptr mem) // vregMem +(VPMOVZXDQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXDQ512load {sym} [off] ptr mem) // vregMem +(VPMOVZXWQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXWQMasked512load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXDQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXDQMasked256load {sym} [off] ptr mask mem) // vregMem +(VPMOVZXDQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMOVZXDQMasked512load {sym} [off] ptr mask mem) // vregMem +(VGF2P8AFFINEQB128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEQB128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VGF2P8AFFINEQB256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEQB256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VGF2P8AFFINEQB512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEQB512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VGF2P8AFFINEINVQB128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEINVQB128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VGF2P8AFFINEINVQB256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEINVQB256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VGF2P8AFFINEINVQB512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEINVQB512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VGF2P8AFFINEINVQBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEINVQBMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VGF2P8AFFINEINVQBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEINVQBMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VGF2P8AFFINEINVQBMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEINVQBMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VGF2P8AFFINEQBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEQBMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VGF2P8AFFINEQBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEQBMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VGF2P8AFFINEQBMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VGF2P8AFFINEQBMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VGF2P8MULB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VGF2P8MULB128load {sym} [off] x ptr mem) // vregMem +(VGF2P8MULB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VGF2P8MULB256load {sym} [off] x ptr mem) // vregMem +(VGF2P8MULBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VGF2P8MULBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VGF2P8MULBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VGF2P8MULBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPCMPGTB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTB128load {sym} [off] x ptr mem) // vregMem +(VPCMPGTB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTB256load {sym} [off] x ptr mem) // vregMem +(VPCMPGTW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTW128load {sym} [off] x ptr mem) // vregMem +(VPCMPGTW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTW256load {sym} [off] x ptr mem) // vregMem +(VPCMPGTD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTD128load {sym} [off] x ptr mem) // vregMem +(VPCMPGTD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTD256load {sym} [off] x ptr mem) // vregMem +(VPCMPGTD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTD512load {sym} [off] x ptr mem) // vregMem +(VPCMPGTQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTQ128load {sym} [off] x ptr mem) // vregMem +(VPCMPGTQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTQ256load {sym} [off] x ptr mem) // vregMem +(VPCMPGTQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTQ512load {sym} [off] x ptr mem) // vregMem +(VPCMPUD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPUD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPCMPUQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPUQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPCMPD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPCMPQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPUNPCKHWD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHWD128load {sym} [off] x ptr mem) // vregMem +(VPUNPCKHDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHDQ128load {sym} [off] x ptr mem) // vregMem +(VPUNPCKHQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHQDQ128load {sym} [off] x ptr mem) // vregMem +(VPUNPCKHWD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHWD256load {sym} [off] x ptr mem) // vregMem +(VPUNPCKHDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHDQ256load {sym} [off] x ptr mem) // vregMem +(VPUNPCKHDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHDQ512load {sym} [off] x ptr mem) // vregMem +(VPUNPCKHQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHQDQ256load {sym} [off] x ptr mem) // vregMem +(VPUNPCKHQDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHQDQ512load {sym} [off] x ptr mem) // vregMem +(VPUNPCKLWD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLWD128load {sym} [off] x ptr mem) // vregMem +(VPUNPCKLDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLDQ128load {sym} [off] x ptr mem) // vregMem +(VPUNPCKLQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLQDQ128load {sym} [off] x ptr mem) // vregMem +(VPUNPCKLWD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLWD256load {sym} [off] x ptr mem) // vregMem +(VPUNPCKLDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLDQ256load {sym} [off] x ptr mem) // vregMem +(VPUNPCKLDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLDQ512load {sym} [off] x ptr mem) // vregMem +(VPUNPCKLQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLQDQ256load {sym} [off] x ptr mem) // vregMem +(VPUNPCKLQDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLQDQ512load {sym} [off] x ptr mem) // vregMem +(VPLZCNTD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTD128load {sym} [off] ptr mem) // vregMem +(VPLZCNTD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTD256load {sym} [off] ptr mem) // vregMem +(VPLZCNTD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTD512load {sym} [off] ptr mem) // vregMem +(VPLZCNTQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTQ128load {sym} [off] ptr mem) // vregMem +(VPLZCNTQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTQ256load {sym} [off] ptr mem) // vregMem +(VPLZCNTQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTQ512load {sym} [off] ptr mem) // vregMem +(VPLZCNTDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTDMasked128load {sym} [off] ptr mask mem) // vregMem +(VPLZCNTDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPLZCNTDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTDMasked512load {sym} [off] ptr mask mem) // vregMem +(VPLZCNTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTQMasked128load {sym} [off] ptr mask mem) // vregMem +(VPLZCNTQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTQMasked256load {sym} [off] ptr mask mem) // vregMem +(VPLZCNTQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTQMasked512load {sym} [off] ptr mask mem) // vregMem +(VMAXPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPS128load {sym} [off] x ptr mem) // vregMem +(VMAXPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPS256load {sym} [off] x ptr mem) // vregMem +(VMAXPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPS512load {sym} [off] x ptr mem) // vregMem +(VMAXPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPD128load {sym} [off] x ptr mem) // vregMem +(VMAXPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPD256load {sym} [off] x ptr mem) // vregMem +(VMAXPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPD512load {sym} [off] x ptr mem) // vregMem +(VPMAXSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSB128load {sym} [off] x ptr mem) // vregMem +(VPMAXSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSB256load {sym} [off] x ptr mem) // vregMem +(VPMAXSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSW128load {sym} [off] x ptr mem) // vregMem +(VPMAXSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSW256load {sym} [off] x ptr mem) // vregMem +(VPMAXSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSD128load {sym} [off] x ptr mem) // vregMem +(VPMAXSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSD256load {sym} [off] x ptr mem) // vregMem +(VPMAXSD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSD512load {sym} [off] x ptr mem) // vregMem +(VPMAXSQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQ128load {sym} [off] x ptr mem) // vregMem +(VPMAXSQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQ256load {sym} [off] x ptr mem) // vregMem +(VPMAXSQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQ512load {sym} [off] x ptr mem) // vregMem +(VPMAXUB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUB128load {sym} [off] x ptr mem) // vregMem +(VPMAXUB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUB256load {sym} [off] x ptr mem) // vregMem +(VPMAXUW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUW128load {sym} [off] x ptr mem) // vregMem +(VPMAXUW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUW256load {sym} [off] x ptr mem) // vregMem +(VPMAXUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUD128load {sym} [off] x ptr mem) // vregMem +(VPMAXUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUD256load {sym} [off] x ptr mem) // vregMem +(VPMAXUD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUD512load {sym} [off] x ptr mem) // vregMem +(VPMAXUQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQ128load {sym} [off] x ptr mem) // vregMem +(VPMAXUQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQ256load {sym} [off] x ptr mem) // vregMem +(VPMAXUQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQ512load {sym} [off] x ptr mem) // vregMem +(VMAXPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPSMasked128load {sym} [off] x ptr mask mem) // vregMem +(VMAXPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPSMasked256load {sym} [off] x ptr mask mem) // vregMem +(VMAXPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPSMasked512load {sym} [off] x ptr mask mem) // vregMem +(VMAXPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VMAXPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VMAXPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMAXSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMAXSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMAXSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMAXSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMAXSDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMAXSDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMAXSDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMAXSQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMAXSQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMAXSQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMAXUBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMAXUBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMAXUWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMAXUWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMAXUDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMAXUDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMAXUDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMAXUQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMAXUQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMAXUQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VMINPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPS128load {sym} [off] x ptr mem) // vregMem +(VMINPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPS256load {sym} [off] x ptr mem) // vregMem +(VMINPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPS512load {sym} [off] x ptr mem) // vregMem +(VMINPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPD128load {sym} [off] x ptr mem) // vregMem +(VMINPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPD256load {sym} [off] x ptr mem) // vregMem +(VMINPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPD512load {sym} [off] x ptr mem) // vregMem +(VPMINSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSB128load {sym} [off] x ptr mem) // vregMem +(VPMINSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSB256load {sym} [off] x ptr mem) // vregMem +(VPMINSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSW128load {sym} [off] x ptr mem) // vregMem +(VPMINSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSW256load {sym} [off] x ptr mem) // vregMem +(VPMINSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSD128load {sym} [off] x ptr mem) // vregMem +(VPMINSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSD256load {sym} [off] x ptr mem) // vregMem +(VPMINSD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSD512load {sym} [off] x ptr mem) // vregMem +(VPMINSQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSQ128load {sym} [off] x ptr mem) // vregMem +(VPMINSQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSQ256load {sym} [off] x ptr mem) // vregMem +(VPMINSQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSQ512load {sym} [off] x ptr mem) // vregMem +(VPMINUB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUB128load {sym} [off] x ptr mem) // vregMem +(VPMINUB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUB256load {sym} [off] x ptr mem) // vregMem +(VPMINUW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUW128load {sym} [off] x ptr mem) // vregMem +(VPMINUW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUW256load {sym} [off] x ptr mem) // vregMem +(VPMINUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUD128load {sym} [off] x ptr mem) // vregMem +(VPMINUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUD256load {sym} [off] x ptr mem) // vregMem +(VPMINUD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUD512load {sym} [off] x ptr mem) // vregMem +(VPMINUQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUQ128load {sym} [off] x ptr mem) // vregMem +(VPMINUQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUQ256load {sym} [off] x ptr mem) // vregMem +(VPMINUQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUQ512load {sym} [off] x ptr mem) // vregMem +(VMINPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPSMasked128load {sym} [off] x ptr mask mem) // vregMem +(VMINPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPSMasked256load {sym} [off] x ptr mask mem) // vregMem +(VMINPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPSMasked512load {sym} [off] x ptr mask mem) // vregMem +(VMINPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VMINPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VMINPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMINSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMINSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMINSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMINSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMINSDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMINSDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMINSDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMINSQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMINSQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMINSQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMINUBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMINUBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMINUWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMINUWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMINUDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMINUDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMINUDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMINUQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMINUQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMINUQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VMULPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPS128load {sym} [off] x ptr mem) // vregMem +(VMULPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPS256load {sym} [off] x ptr mem) // vregMem +(VMULPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPS512load {sym} [off] x ptr mem) // vregMem +(VMULPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPD128load {sym} [off] x ptr mem) // vregMem +(VMULPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPD256load {sym} [off] x ptr mem) // vregMem +(VMULPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPD512load {sym} [off] x ptr mem) // vregMem +(VPMULLW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLW128load {sym} [off] x ptr mem) // vregMem +(VPMULLW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLW256load {sym} [off] x ptr mem) // vregMem +(VPMULLD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLD128load {sym} [off] x ptr mem) // vregMem +(VPMULLD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLD256load {sym} [off] x ptr mem) // vregMem +(VPMULLD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLD512load {sym} [off] x ptr mem) // vregMem +(VPMULLQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLQ128load {sym} [off] x ptr mem) // vregMem +(VPMULLQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLQ256load {sym} [off] x ptr mem) // vregMem +(VPMULLQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLQ512load {sym} [off] x ptr mem) // vregMem +(VFMADD213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PS128load {sym} [off] x y ptr mem) // vregMem +(VFMADD213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PS256load {sym} [off] x y ptr mem) // vregMem +(VFMADD213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PS512load {sym} [off] x y ptr mem) // vregMem +(VFMADD213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PD128load {sym} [off] x y ptr mem) // vregMem +(VFMADD213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PD256load {sym} [off] x y ptr mem) // vregMem +(VFMADD213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PD512load {sym} [off] x y ptr mem) // vregMem +(VFMADDSUB213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PS128load {sym} [off] x y ptr mem) // vregMem +(VFMADDSUB213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PS256load {sym} [off] x y ptr mem) // vregMem +(VFMADDSUB213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PS512load {sym} [off] x y ptr mem) // vregMem +(VFMADDSUB213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PD128load {sym} [off] x y ptr mem) // vregMem +(VFMADDSUB213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PD256load {sym} [off] x y ptr mem) // vregMem +(VFMADDSUB213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PD512load {sym} [off] x y ptr mem) // vregMem +(VFMADDSUB213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PSMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VFMADDSUB213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PSMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VFMADDSUB213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PSMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VFMADDSUB213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PDMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VFMADDSUB213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PDMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VFMADDSUB213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PDMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VFMADD213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PSMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VFMADD213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PSMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VFMADD213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PSMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VFMADD213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PDMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VFMADD213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PDMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VFMADD213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PDMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VFMSUBADD213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PS128load {sym} [off] x y ptr mem) // vregMem +(VFMSUBADD213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PS256load {sym} [off] x y ptr mem) // vregMem +(VFMSUBADD213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PS512load {sym} [off] x y ptr mem) // vregMem +(VFMSUBADD213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PD128load {sym} [off] x y ptr mem) // vregMem +(VFMSUBADD213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PD256load {sym} [off] x y ptr mem) // vregMem +(VFMSUBADD213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PD512load {sym} [off] x y ptr mem) // vregMem +(VFMSUBADD213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PSMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VFMSUBADD213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PSMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VFMSUBADD213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PSMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VFMSUBADD213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PDMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VFMSUBADD213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PDMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VFMSUBADD213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PDMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VPMULHW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULHW128load {sym} [off] x ptr mem) // vregMem +(VPMULHW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULHW256load {sym} [off] x ptr mem) // vregMem +(VPMULHUW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULHUW128load {sym} [off] x ptr mem) // vregMem +(VPMULHUW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULHUW256load {sym} [off] x ptr mem) // vregMem +(VPMULHWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULHWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMULHWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULHWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMULHUWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULHUWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMULHUWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULHUWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VMULPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPSMasked128load {sym} [off] x ptr mask mem) // vregMem +(VMULPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPSMasked256load {sym} [off] x ptr mask mem) // vregMem +(VMULPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPSMasked512load {sym} [off] x ptr mask mem) // vregMem +(VMULPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VMULPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VMULPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMULLWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMULLWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMULLDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMULLDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMULLDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPMULLQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPMULLQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPMULLQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPSIGNB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSIGNB128load {sym} [off] x ptr mem) // vregMem +(VPSIGNB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSIGNB256load {sym} [off] x ptr mem) // vregMem +(VPSIGNW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSIGNW128load {sym} [off] x ptr mem) // vregMem +(VPSIGNW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSIGNW256load {sym} [off] x ptr mem) // vregMem +(VPSIGND128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSIGND128load {sym} [off] x ptr mem) // vregMem +(VPSIGND256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSIGND256load {sym} [off] x ptr mem) // vregMem +(VPMULDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULDQ128load {sym} [off] x ptr mem) // vregMem +(VPMULDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULDQ256load {sym} [off] x ptr mem) // vregMem +(VPMULUDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULUDQ128load {sym} [off] x ptr mem) // vregMem +(VPMULUDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULUDQ256load {sym} [off] x ptr mem) // vregMem +(VPOPCNTB128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTB128load {sym} [off] ptr mem) // vregMem +(VPOPCNTB256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTB256load {sym} [off] ptr mem) // vregMem +(VPOPCNTW128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTW128load {sym} [off] ptr mem) // vregMem +(VPOPCNTW256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTW256load {sym} [off] ptr mem) // vregMem +(VPOPCNTD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTD128load {sym} [off] ptr mem) // vregMem +(VPOPCNTD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTD256load {sym} [off] ptr mem) // vregMem +(VPOPCNTD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTD512load {sym} [off] ptr mem) // vregMem +(VPOPCNTQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQ128load {sym} [off] ptr mem) // vregMem +(VPOPCNTQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQ256load {sym} [off] ptr mem) // vregMem +(VPOPCNTQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQ512load {sym} [off] ptr mem) // vregMem +(VPOPCNTBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTBMasked128load {sym} [off] ptr mask mem) // vregMem +(VPOPCNTBMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTBMasked256load {sym} [off] ptr mask mem) // vregMem +(VPOPCNTWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTWMasked128load {sym} [off] ptr mask mem) // vregMem +(VPOPCNTWMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTWMasked256load {sym} [off] ptr mask mem) // vregMem +(VPOPCNTDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTDMasked128load {sym} [off] ptr mask mem) // vregMem +(VPOPCNTDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPOPCNTDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTDMasked512load {sym} [off] ptr mask mem) // vregMem +(VPOPCNTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQMasked128load {sym} [off] ptr mask mem) // vregMem +(VPOPCNTQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQMasked256load {sym} [off] ptr mask mem) // vregMem +(VPOPCNTQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQMasked512load {sym} [off] ptr mask mem) // vregMem +(VPOR128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOR128load {sym} [off] x ptr mem) // vregMem +(VPOR256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOR256load {sym} [off] x ptr mem) // vregMem +(VPORD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPORD512load {sym} [off] x ptr mem) // vregMem +(VPORQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPORQ512load {sym} [off] x ptr mem) // vregMem +(VPORDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPORDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPORDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPORQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPORQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPORQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPERMB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMB128load {sym} [off] x ptr mem) // vregMem +(VPERMB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMB256load {sym} [off] x ptr mem) // vregMem +(VPERMW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMW128load {sym} [off] x ptr mem) // vregMem +(VPERMW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMW256load {sym} [off] x ptr mem) // vregMem +(VPERMPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPS256load {sym} [off] x ptr mem) // vregMem +(VPERMD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMD256load {sym} [off] x ptr mem) // vregMem +(VPERMPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPS512load {sym} [off] x ptr mem) // vregMem +(VPERMD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMD512load {sym} [off] x ptr mem) // vregMem +(VPERMPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPD256load {sym} [off] x ptr mem) // vregMem +(VPERMQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMQ256load {sym} [off] x ptr mem) // vregMem +(VPERMPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPD512load {sym} [off] x ptr mem) // vregMem +(VPERMQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMQ512load {sym} [off] x ptr mem) // vregMem +(VPERMBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPERMBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPERMWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPERMWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPERMPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMPSMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPERMDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPERMPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMPSMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPERMDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPERMPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMPDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPERMQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPERMPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMPDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPERMQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPSHUFB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHUFB128load {sym} [off] x ptr mem) // vregMem +(VPSHUFB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHUFB256load {sym} [off] x ptr mem) // vregMem +(VPSHUFBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHUFBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSHUFBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHUFBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VRCPPS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRCPPS128load {sym} [off] ptr mem) // vregMem +(VRCPPS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRCPPS256load {sym} [off] ptr mem) // vregMem +(VRCP14PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRCP14PS512load {sym} [off] ptr mem) // vregMem +(VRCP14PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRCP14PD128load {sym} [off] ptr mem) // vregMem +(VRCP14PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRCP14PD256load {sym} [off] ptr mem) // vregMem +(VRCP14PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRCP14PD512load {sym} [off] ptr mem) // vregMem +(VRCP14PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PSMasked128load {sym} [off] ptr mask mem) // vregMem +(VRCP14PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PSMasked256load {sym} [off] ptr mask mem) // vregMem +(VRCP14PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PSMasked512load {sym} [off] ptr mask mem) // vregMem +(VRCP14PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PDMasked128load {sym} [off] ptr mask mem) // vregMem +(VRCP14PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PDMasked256load {sym} [off] ptr mask mem) // vregMem +(VRCP14PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PDMasked512load {sym} [off] ptr mask mem) // vregMem +(VRSQRTPS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRSQRTPS128load {sym} [off] ptr mem) // vregMem +(VRSQRTPS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRSQRTPS256load {sym} [off] ptr mem) // vregMem +(VRSQRT14PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PS512load {sym} [off] ptr mem) // vregMem +(VRSQRT14PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PD128load {sym} [off] ptr mem) // vregMem +(VRSQRT14PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PD256load {sym} [off] ptr mem) // vregMem +(VRSQRT14PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PD512load {sym} [off] ptr mem) // vregMem +(VRSQRT14PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PSMasked128load {sym} [off] ptr mask mem) // vregMem +(VRSQRT14PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PSMasked256load {sym} [off] ptr mask mem) // vregMem +(VRSQRT14PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PSMasked512load {sym} [off] ptr mask mem) // vregMem +(VRSQRT14PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PDMasked128load {sym} [off] ptr mask mem) // vregMem +(VRSQRT14PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PDMasked256load {sym} [off] ptr mask mem) // vregMem +(VRSQRT14PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PDMasked512load {sym} [off] ptr mask mem) // vregMem +(VPROLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVD128load {sym} [off] x ptr mem) // vregMem +(VPROLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVD256load {sym} [off] x ptr mem) // vregMem +(VPROLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVD512load {sym} [off] x ptr mem) // vregMem +(VPROLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVQ128load {sym} [off] x ptr mem) // vregMem +(VPROLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVQ256load {sym} [off] x ptr mem) // vregMem +(VPROLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVQ512load {sym} [off] x ptr mem) // vregMem +(VPROLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPROLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPROLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPROLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPROLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPROLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPRORVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVD128load {sym} [off] x ptr mem) // vregMem +(VPRORVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVD256load {sym} [off] x ptr mem) // vregMem +(VPRORVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVD512load {sym} [off] x ptr mem) // vregMem +(VPRORVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVQ128load {sym} [off] x ptr mem) // vregMem +(VPRORVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVQ256load {sym} [off] x ptr mem) // vregMem +(VPRORVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVQ512load {sym} [off] x ptr mem) // vregMem +(VPRORVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPRORVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPRORVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPRORVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPRORVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPRORVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPACKSSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW128load {sym} [off] x ptr mem) // vregMem +(VPACKSSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW256load {sym} [off] x ptr mem) // vregMem +(VPACKSSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW512load {sym} [off] x ptr mem) // vregMem +(VPACKSSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPACKSSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPACKSSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPACKUSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW128load {sym} [off] x ptr mem) // vregMem +(VPACKUSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW256load {sym} [off] x ptr mem) // vregMem +(VPACKUSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW512load {sym} [off] x ptr mem) // vregMem +(VPACKUSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPACKUSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPACKUSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VSCALEFPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPS128load {sym} [off] x ptr mem) // vregMem +(VSCALEFPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPS256load {sym} [off] x ptr mem) // vregMem +(VSCALEFPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPS512load {sym} [off] x ptr mem) // vregMem +(VSCALEFPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPD128load {sym} [off] x ptr mem) // vregMem +(VSCALEFPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPD256load {sym} [off] x ptr mem) // vregMem +(VSCALEFPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPD512load {sym} [off] x ptr mem) // vregMem +(VSCALEFPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPSMasked128load {sym} [off] x ptr mask mem) // vregMem +(VSCALEFPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPSMasked256load {sym} [off] x ptr mask mem) // vregMem +(VSCALEFPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPSMasked512load {sym} [off] x ptr mask mem) // vregMem +(VSCALEFPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VSCALEFPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VSCALEFPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VINSERTF128256 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VINSERTF128256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VINSERTF64X4512 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VINSERTF64X4512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VINSERTI128256 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VINSERTI128256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VINSERTI64X4512 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VINSERTI64X4512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHLDW128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDW128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHLDW256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDW256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHLDWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHLDWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHLDD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDD128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHLDD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDD256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHLDD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHLDDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHLDDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHLDDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHLDQ128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHLDQ256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHLDQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHLDQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHLDQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHLDQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHRDW128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDW128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHRDW256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDW256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHRDWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHRDWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHRDD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDD128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHRDD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDD256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHRDD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHRDDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHRDDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHRDDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHRDQ128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHRDQ256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHRDQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHRDQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHRDQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSHRDQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) // vregMem +(VPSLLVW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVW128load {sym} [off] x ptr mem) // vregMem +(VPSLLVW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVW256load {sym} [off] x ptr mem) // vregMem +(VPSLLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVD128load {sym} [off] x ptr mem) // vregMem +(VPSLLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVD256load {sym} [off] x ptr mem) // vregMem +(VPSLLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVD512load {sym} [off] x ptr mem) // vregMem +(VPSLLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQ128load {sym} [off] x ptr mem) // vregMem +(VPSLLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQ256load {sym} [off] x ptr mem) // vregMem +(VPSLLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQ512load {sym} [off] x ptr mem) // vregMem +(VPSHLDVW128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVW128load {sym} [off] x y ptr mem) // vregMem +(VPSHLDVW256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVW256load {sym} [off] x y ptr mem) // vregMem +(VPSHLDVWMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVWMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPSHLDVWMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVWMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPSHLDVD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVD128load {sym} [off] x y ptr mem) // vregMem +(VPSHLDVD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVD256load {sym} [off] x y ptr mem) // vregMem +(VPSHLDVD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVD512load {sym} [off] x y ptr mem) // vregMem +(VPSHLDVDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVDMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPSHLDVDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVDMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPSHLDVDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVDMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VPSHLDVQ128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQ128load {sym} [off] x y ptr mem) // vregMem +(VPSHLDVQ256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQ256load {sym} [off] x y ptr mem) // vregMem +(VPSHLDVQ512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQ512load {sym} [off] x y ptr mem) // vregMem +(VPSHLDVQMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPSHLDVQMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPSHLDVQMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VPSLLVWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSLLVWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSLLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSLLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSLLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPSLLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSLLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSLLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPSRAVW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVW128load {sym} [off] x ptr mem) // vregMem +(VPSRAVW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVW256load {sym} [off] x ptr mem) // vregMem +(VPSRAVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVD128load {sym} [off] x ptr mem) // vregMem +(VPSRAVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVD256load {sym} [off] x ptr mem) // vregMem +(VPSRAVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVD512load {sym} [off] x ptr mem) // vregMem +(VPSRAVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQ128load {sym} [off] x ptr mem) // vregMem +(VPSRAVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQ256load {sym} [off] x ptr mem) // vregMem +(VPSRAVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQ512load {sym} [off] x ptr mem) // vregMem +(VPSRLVW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVW128load {sym} [off] x ptr mem) // vregMem +(VPSRLVW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVW256load {sym} [off] x ptr mem) // vregMem +(VPSRLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVD128load {sym} [off] x ptr mem) // vregMem +(VPSRLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVD256load {sym} [off] x ptr mem) // vregMem +(VPSRLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVD512load {sym} [off] x ptr mem) // vregMem +(VPSRLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQ128load {sym} [off] x ptr mem) // vregMem +(VPSRLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQ256load {sym} [off] x ptr mem) // vregMem +(VPSRLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQ512load {sym} [off] x ptr mem) // vregMem +(VPSHRDVW128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVW128load {sym} [off] x y ptr mem) // vregMem +(VPSHRDVW256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVW256load {sym} [off] x y ptr mem) // vregMem +(VPSHRDVWMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVWMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPSHRDVWMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVWMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPSHRDVD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVD128load {sym} [off] x y ptr mem) // vregMem +(VPSHRDVD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVD256load {sym} [off] x y ptr mem) // vregMem +(VPSHRDVD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVD512load {sym} [off] x y ptr mem) // vregMem +(VPSHRDVDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVDMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPSHRDVDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVDMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPSHRDVDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVDMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VPSHRDVQ128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQ128load {sym} [off] x y ptr mem) // vregMem +(VPSHRDVQ256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQ256load {sym} [off] x y ptr mem) // vregMem +(VPSHRDVQ512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQ512load {sym} [off] x y ptr mem) // vregMem +(VPSHRDVQMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQMasked128load {sym} [off] x y ptr mask mem) // vregMem +(VPSHRDVQMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQMasked256load {sym} [off] x y ptr mask mem) // vregMem +(VPSHRDVQMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQMasked512load {sym} [off] x y ptr mask mem) // vregMem +(VPSRAVWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSRAVWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSRAVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSRAVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSRAVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPSRAVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSRAVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSRAVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPSRLVWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSRLVWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSRLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSRLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSRLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPSRLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSRLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSRLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VSQRTPS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPS128load {sym} [off] ptr mem) // vregMem +(VSQRTPS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPS256load {sym} [off] ptr mem) // vregMem +(VSQRTPS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPS512load {sym} [off] ptr mem) // vregMem +(VSQRTPD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPD128load {sym} [off] ptr mem) // vregMem +(VSQRTPD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPD256load {sym} [off] ptr mem) // vregMem +(VSQRTPD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPD512load {sym} [off] ptr mem) // vregMem +(VSQRTPSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPSMasked128load {sym} [off] ptr mask mem) // vregMem +(VSQRTPSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPSMasked256load {sym} [off] ptr mask mem) // vregMem +(VSQRTPSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPSMasked512load {sym} [off] ptr mask mem) // vregMem +(VSQRTPDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPDMasked128load {sym} [off] ptr mask mem) // vregMem +(VSQRTPDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPDMasked256load {sym} [off] ptr mask mem) // vregMem +(VSQRTPDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPDMasked512load {sym} [off] ptr mask mem) // vregMem +(VSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPS128load {sym} [off] x ptr mem) // vregMem +(VSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPS256load {sym} [off] x ptr mem) // vregMem +(VSUBPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPS512load {sym} [off] x ptr mem) // vregMem +(VSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPD128load {sym} [off] x ptr mem) // vregMem +(VSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPD256load {sym} [off] x ptr mem) // vregMem +(VSUBPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPD512load {sym} [off] x ptr mem) // vregMem +(VPSUBB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBB128load {sym} [off] x ptr mem) // vregMem +(VPSUBB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBB256load {sym} [off] x ptr mem) // vregMem +(VPSUBW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBW128load {sym} [off] x ptr mem) // vregMem +(VPSUBW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBW256load {sym} [off] x ptr mem) // vregMem +(VPSUBD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBD128load {sym} [off] x ptr mem) // vregMem +(VPSUBD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBD256load {sym} [off] x ptr mem) // vregMem +(VPSUBD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBD512load {sym} [off] x ptr mem) // vregMem +(VPSUBQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBQ128load {sym} [off] x ptr mem) // vregMem +(VPSUBQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBQ256load {sym} [off] x ptr mem) // vregMem +(VPSUBQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBQ512load {sym} [off] x ptr mem) // vregMem +(VSUBPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPSMasked128load {sym} [off] x ptr mask mem) // vregMem +(VSUBPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPSMasked256load {sym} [off] x ptr mask mem) // vregMem +(VSUBPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPSMasked512load {sym} [off] x ptr mask mem) // vregMem +(VSUBPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VSUBPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VSUBPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPSUBBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSUBBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSUBWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSUBWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSUBDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSUBDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSUBDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPSUBQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSUBQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSUBQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPSUBSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBSB128load {sym} [off] x ptr mem) // vregMem +(VPSUBSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBSB256load {sym} [off] x ptr mem) // vregMem +(VPSUBSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBSW128load {sym} [off] x ptr mem) // vregMem +(VPSUBSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBSW256load {sym} [off] x ptr mem) // vregMem +(VPSUBUSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBUSB128load {sym} [off] x ptr mem) // vregMem +(VPSUBUSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBUSB256load {sym} [off] x ptr mem) // vregMem +(VPSUBUSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBUSW128load {sym} [off] x ptr mem) // vregMem +(VPSUBUSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBUSW256load {sym} [off] x ptr mem) // vregMem +(VPSUBSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBSBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSUBSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBSBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSUBSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBSWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSUBSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBSWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSUBUSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBUSBMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSUBUSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBUSBMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSUBUSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBUSWMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPSUBUSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBUSWMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPSADBW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSADBW128load {sym} [off] x ptr mem) // vregMem +(VPSADBW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSADBW256load {sym} [off] x ptr mem) // vregMem +(VPXOR128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPXOR128load {sym} [off] x ptr mem) // vregMem +(VPXOR256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPXOR256load {sym} [off] x ptr mem) // vregMem +(VPXORD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPXORD512load {sym} [off] x ptr mem) // vregMem +(VPXORQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPXORQ512load {sym} [off] x ptr mem) // vregMem +(VPXORDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORDMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPXORDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORDMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPXORDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPXORQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORQMasked128load {sym} [off] x ptr mask mem) // vregMem +(VPXORQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORQMasked256load {sym} [off] x ptr mask mem) // vregMem +(VPXORQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPBLENDMDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBLENDMDMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPBLENDMQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBLENDMQMasked512load {sym} [off] x ptr mask mem) // vregMem +(VPBROADCASTQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTQ128load {sym} [off] ptr mem) // vregMem +(VPBROADCASTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTQMasked128load {sym} [off] ptr mask mem) // vregMem +(VBROADCASTSS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && v.Block.CPUfeatures.hasFeature(CPUavx) && canMergeLoad(v, l) && clobber(l) => (VBROADCASTSS128load {sym} [off] ptr mem) // vregMemFeatCheck +(VBROADCASTSD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && v.Block.CPUfeatures.hasFeature(CPUavx) && canMergeLoad(v, l) && clobber(l) => (VBROADCASTSD256load {sym} [off] ptr mem) // vregMemFeatCheck +(VPBROADCASTD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTD128load {sym} [off] ptr mem) // vregMem +(VPBROADCASTQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTQ256load {sym} [off] ptr mem) // vregMem +(VBROADCASTSSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VBROADCASTSSMasked128load {sym} [off] ptr mask mem) // vregMem +(VBROADCASTSDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VBROADCASTSDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPBROADCASTDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTDMasked128load {sym} [off] ptr mask mem) // vregMem +(VPBROADCASTQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTQMasked256load {sym} [off] ptr mask mem) // vregMem +(VBROADCASTSS256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && v.Block.CPUfeatures.hasFeature(CPUavx) && canMergeLoad(v, l) && clobber(l) => (VBROADCASTSS256load {sym} [off] ptr mem) // vregMemFeatCheck +(VBROADCASTSD512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VBROADCASTSD512load {sym} [off] ptr mem) // vregMem +(VPBROADCASTW128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTW128load {sym} [off] ptr mem) // vregMem +(VPBROADCASTD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTD256load {sym} [off] ptr mem) // vregMem +(VPBROADCASTQ512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTQ512load {sym} [off] ptr mem) // vregMem +(VBROADCASTSSMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VBROADCASTSSMasked256load {sym} [off] ptr mask mem) // vregMem +(VBROADCASTSDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VBROADCASTSDMasked512load {sym} [off] ptr mask mem) // vregMem +(VPBROADCASTDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTDMasked256load {sym} [off] ptr mask mem) // vregMem +(VPBROADCASTQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTQMasked512load {sym} [off] ptr mask mem) // vregMem +(VBROADCASTSS512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VBROADCASTSS512load {sym} [off] ptr mem) // vregMem +(VPBROADCASTB128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTB128load {sym} [off] ptr mem) // vregMem +(VPBROADCASTW256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTW256load {sym} [off] ptr mem) // vregMem +(VPBROADCASTD512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTD512load {sym} [off] ptr mem) // vregMem +(VBROADCASTSSMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VBROADCASTSSMasked512load {sym} [off] ptr mask mem) // vregMem +(VPBROADCASTBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTBMasked128load {sym} [off] ptr mask mem) // vregMem +(VPBROADCASTDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTDMasked512load {sym} [off] ptr mask mem) // vregMem +(VPBROADCASTB256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTB256load {sym} [off] ptr mem) // vregMem +(VPBROADCASTBMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTBMasked256load {sym} [off] ptr mask mem) // vregMem +(VPBROADCASTB512 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTB512load {sym} [off] ptr mem) // vregMem +(VPBROADCASTBMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBROADCASTBMasked512load {sym} [off] ptr mask mem) // vregMem +(VPCLMULQDQ128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCLMULQDQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPCLMULQDQ256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCLMULQDQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VSHUFPS128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSHUFPS128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VSHUFPD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSHUFPD128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VSHUFPS256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSHUFPS256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VSHUFPS512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSHUFPS512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VSHUFPD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSHUFPD256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VSHUFPD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSHUFPD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) // vregMem +(VPSHUFD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHUFD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSHUFD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHUFD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSHUFD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHUFD512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSHUFDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHUFDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSHUFDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHUFDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSHUFHW128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHUFHW128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSHUFHW256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHUFHW256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSHUFHWMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHUFHWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSHUFHWMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHUFHWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSHUFLW128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHUFLW128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSHUFLW256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHUFLW256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSHUFLWMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHUFLWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSHUFLWMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHUFLWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSHUFDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHUFDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPROLD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPROLD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPROLD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLD512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPROLQ128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPROLQ256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPROLQ512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPROLDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPROLDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPROLDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPROLQMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPROLQMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPROLQMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPRORD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPRORD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPRORD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORD512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPRORQ128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPRORQ256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPRORQ512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPRORDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPRORDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPRORDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPRORQMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPRORQMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPRORQMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSLLD512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLD512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSLLQ512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLQ512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSLLWMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLWMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSLLWMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLWMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSLLDMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLDMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSLLDMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLDMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSLLDMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLDMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSLLQMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLQMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSLLQMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLQMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSLLQMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLQMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRAD512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAD512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSRAQ128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAQ128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSRAQ256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAQ256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSRAQ512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAQ512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSRLD512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLD512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSRLQ512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLQ512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) // vregMem +(VPSRAWMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAWMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRAWMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAWMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRADMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRADMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRADMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRADMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRADMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRADMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRAQMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAQMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRAQMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAQMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRAQMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAQMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRLWMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLWMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRLWMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLWMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRLDMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLDMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRLDMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLDMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRLDMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLDMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRLQMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLQMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRLQMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLQMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPSRLQMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLQMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) // vregMem +(VPTERNLOGD128 [c] x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPTERNLOGD128load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) // vregMem +(VPTERNLOGD256 [c] x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPTERNLOGD256load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) // vregMem +(VPTERNLOGD512 [c] x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPTERNLOGD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) // vregMem +(VPTERNLOGQ128 [c] x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPTERNLOGQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) // vregMem +(VPTERNLOGQ256 [c] x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPTERNLOGQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) // vregMem +(VPTERNLOGQ512 [c] x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPTERNLOGQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) // vregMem diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go new file mode 100644 index 00000000000000..ccb988d110833d --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go @@ -0,0 +1,3114 @@ +// Code generated by 'simdgen -o godefs -goroot $GOROOT -arch amd64 -xedPath $XED_PATH go_amd64.yaml types.yaml categories.yaml'; DO NOT EDIT. + +package main + +func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vfpkv, w11, w21, w2k, wkw, w2kw, w2kk, w31, w3kw, wgpw, wgp, wfpw, wfpkw, + wkwload, v21load, v31load, v11load, w21load, w31load, w2kload, w2kwload, w11load, w3kwload, w2kkload, v31x0AtIn2 regInfo) []opData { + return []opData{ + {name: "SHA1MSG1128", argLength: 2, reg: v21, asm: "SHA1MSG1", typ: "Vec128", resultInArg0: true}, + {name: "SHA1MSG2128", argLength: 2, reg: v21, asm: "SHA1MSG2", typ: "Vec128", resultInArg0: true}, + {name: "SHA1NEXTE128", argLength: 2, reg: v21, asm: "SHA1NEXTE", typ: "Vec128", resultInArg0: true}, + {name: "SHA256MSG1128", argLength: 2, reg: v21, asm: "SHA256MSG1", typ: "Vec128", resultInArg0: true}, + {name: "SHA256MSG2128", argLength: 2, reg: v21, asm: "SHA256MSG2", typ: "Vec128", resultInArg0: true}, + {name: "SHA256RNDS2128", argLength: 3, reg: v31x0AtIn2, asm: "SHA256RNDS2", typ: "Vec128", resultInArg0: true}, + {name: "VADDPD128", argLength: 2, reg: v21, asm: "VADDPD", commutative: true, typ: "Vec128"}, + {name: "VADDPD256", argLength: 2, reg: v21, asm: "VADDPD", commutative: true, typ: "Vec256"}, + {name: "VADDPD512", argLength: 2, reg: w21, asm: "VADDPD", commutative: true, typ: "Vec512"}, + {name: "VADDPDMasked128", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec128"}, + {name: "VADDPDMasked256", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec256"}, + {name: "VADDPDMasked512", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec512"}, + {name: "VADDPS128", argLength: 2, reg: v21, asm: "VADDPS", commutative: true, typ: "Vec128"}, + {name: "VADDPS256", argLength: 2, reg: v21, asm: "VADDPS", commutative: true, typ: "Vec256"}, + {name: "VADDPS512", argLength: 2, reg: w21, asm: "VADDPS", commutative: true, typ: "Vec512"}, + {name: "VADDPSMasked128", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec128"}, + {name: "VADDPSMasked256", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec256"}, + {name: "VADDPSMasked512", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec512"}, + {name: "VADDSUBPD128", argLength: 2, reg: v21, asm: "VADDSUBPD", typ: "Vec128"}, + {name: "VADDSUBPD256", argLength: 2, reg: v21, asm: "VADDSUBPD", typ: "Vec256"}, + {name: "VADDSUBPS128", argLength: 2, reg: v21, asm: "VADDSUBPS", typ: "Vec128"}, + {name: "VADDSUBPS256", argLength: 2, reg: v21, asm: "VADDSUBPS", typ: "Vec256"}, + {name: "VAESDEC128", argLength: 2, reg: v21, asm: "VAESDEC", typ: "Vec128"}, + {name: "VAESDEC256", argLength: 2, reg: v21, asm: "VAESDEC", typ: "Vec256"}, + {name: "VAESDEC512", argLength: 2, reg: w21, asm: "VAESDEC", typ: "Vec512"}, + {name: "VAESDECLAST128", argLength: 2, reg: v21, asm: "VAESDECLAST", typ: "Vec128"}, + {name: "VAESDECLAST256", argLength: 2, reg: v21, asm: "VAESDECLAST", typ: "Vec256"}, + {name: "VAESDECLAST512", argLength: 2, reg: w21, asm: "VAESDECLAST", typ: "Vec512"}, + {name: "VAESENC128", argLength: 2, reg: v21, asm: "VAESENC", typ: "Vec128"}, + {name: "VAESENC256", argLength: 2, reg: v21, asm: "VAESENC", typ: "Vec256"}, + {name: "VAESENC512", argLength: 2, reg: w21, asm: "VAESENC", typ: "Vec512"}, + {name: "VAESENCLAST128", argLength: 2, reg: v21, asm: "VAESENCLAST", typ: "Vec128"}, + {name: "VAESENCLAST256", argLength: 2, reg: v21, asm: "VAESENCLAST", typ: "Vec256"}, + {name: "VAESENCLAST512", argLength: 2, reg: w21, asm: "VAESENCLAST", typ: "Vec512"}, + {name: "VAESIMC128", argLength: 1, reg: v11, asm: "VAESIMC", typ: "Vec128"}, + {name: "VBROADCASTSD256", argLength: 1, reg: v11, asm: "VBROADCASTSD", typ: "Vec256"}, + {name: "VBROADCASTSD512", argLength: 1, reg: w11, asm: "VBROADCASTSD", typ: "Vec512"}, + {name: "VBROADCASTSDMasked256", argLength: 2, reg: wkw, asm: "VBROADCASTSD", typ: "Vec256"}, + {name: "VBROADCASTSDMasked512", argLength: 2, reg: wkw, asm: "VBROADCASTSD", typ: "Vec512"}, + {name: "VBROADCASTSS128", argLength: 1, reg: v11, asm: "VBROADCASTSS", typ: "Vec128"}, + {name: "VBROADCASTSS256", argLength: 1, reg: v11, asm: "VBROADCASTSS", typ: "Vec256"}, + {name: "VBROADCASTSS512", argLength: 1, reg: w11, asm: "VBROADCASTSS", typ: "Vec512"}, + {name: "VBROADCASTSSMasked128", argLength: 2, reg: wkw, asm: "VBROADCASTSS", typ: "Vec128"}, + {name: "VBROADCASTSSMasked256", argLength: 2, reg: wkw, asm: "VBROADCASTSS", typ: "Vec256"}, + {name: "VBROADCASTSSMasked512", argLength: 2, reg: wkw, asm: "VBROADCASTSS", typ: "Vec512"}, + {name: "VCOMPRESSPDMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", typ: "Vec128"}, + {name: "VCOMPRESSPDMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", typ: "Vec256"}, + {name: "VCOMPRESSPDMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", typ: "Vec512"}, + {name: "VCOMPRESSPSMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", typ: "Vec128"}, + {name: "VCOMPRESSPSMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", typ: "Vec256"}, + {name: "VCOMPRESSPSMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", typ: "Vec512"}, + {name: "VCVTDQ2PD256", argLength: 1, reg: v11, asm: "VCVTDQ2PD", typ: "Vec256"}, + {name: "VCVTDQ2PD512", argLength: 1, reg: w11, asm: "VCVTDQ2PD", typ: "Vec512"}, + {name: "VCVTDQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTDQ2PD", typ: "Vec256"}, + {name: "VCVTDQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTDQ2PD", typ: "Vec512"}, + {name: "VCVTDQ2PS128", argLength: 1, reg: v11, asm: "VCVTDQ2PS", typ: "Vec128"}, + {name: "VCVTDQ2PS256", argLength: 1, reg: v11, asm: "VCVTDQ2PS", typ: "Vec256"}, + {name: "VCVTDQ2PS512", argLength: 1, reg: w11, asm: "VCVTDQ2PS", typ: "Vec512"}, + {name: "VCVTDQ2PSMasked128", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", typ: "Vec128"}, + {name: "VCVTDQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", typ: "Vec256"}, + {name: "VCVTDQ2PSMasked512", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", typ: "Vec512"}, + {name: "VCVTPD2PS256", argLength: 1, reg: w11, asm: "VCVTPD2PS", typ: "Vec256"}, + {name: "VCVTPD2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTPD2PS", typ: "Vec256"}, + {name: "VCVTPD2PSX128", argLength: 1, reg: v11, asm: "VCVTPD2PSX", typ: "Vec128"}, + {name: "VCVTPD2PSXMasked128", argLength: 2, reg: wkw, asm: "VCVTPD2PSX", typ: "Vec128"}, + {name: "VCVTPD2PSY128", argLength: 1, reg: v11, asm: "VCVTPD2PSY", typ: "Vec128"}, + {name: "VCVTPD2PSYMasked128", argLength: 2, reg: wkw, asm: "VCVTPD2PSY", typ: "Vec128"}, + {name: "VCVTPS2PD256", argLength: 1, reg: v11, asm: "VCVTPS2PD", typ: "Vec256"}, + {name: "VCVTPS2PD512", argLength: 1, reg: w11, asm: "VCVTPS2PD", typ: "Vec512"}, + {name: "VCVTPS2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTPS2PD", typ: "Vec256"}, + {name: "VCVTPS2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTPS2PD", typ: "Vec512"}, + {name: "VCVTQQ2PD128", argLength: 1, reg: w11, asm: "VCVTQQ2PD", typ: "Vec128"}, + {name: "VCVTQQ2PD256", argLength: 1, reg: w11, asm: "VCVTQQ2PD", typ: "Vec256"}, + {name: "VCVTQQ2PD512", argLength: 1, reg: w11, asm: "VCVTQQ2PD", typ: "Vec512"}, + {name: "VCVTQQ2PDMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", typ: "Vec128"}, + {name: "VCVTQQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", typ: "Vec256"}, + {name: "VCVTQQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", typ: "Vec512"}, + {name: "VCVTQQ2PS256", argLength: 1, reg: w11, asm: "VCVTQQ2PS", typ: "Vec256"}, + {name: "VCVTQQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTQQ2PS", typ: "Vec256"}, + {name: "VCVTQQ2PSX128", argLength: 1, reg: w11, asm: "VCVTQQ2PSX", typ: "Vec128"}, + {name: "VCVTQQ2PSXMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PSX", typ: "Vec128"}, + {name: "VCVTQQ2PSY128", argLength: 1, reg: w11, asm: "VCVTQQ2PSY", typ: "Vec128"}, + {name: "VCVTQQ2PSYMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PSY", typ: "Vec128"}, + {name: "VCVTTPD2DQ256", argLength: 1, reg: w11, asm: "VCVTTPD2DQ", typ: "Vec256"}, + {name: "VCVTTPD2DQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2DQ", typ: "Vec256"}, + {name: "VCVTTPD2DQX128", argLength: 1, reg: v11, asm: "VCVTTPD2DQX", typ: "Vec128"}, + {name: "VCVTTPD2DQXMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2DQX", typ: "Vec128"}, + {name: "VCVTTPD2DQY128", argLength: 1, reg: v11, asm: "VCVTTPD2DQY", typ: "Vec128"}, + {name: "VCVTTPD2DQYMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2DQY", typ: "Vec128"}, + {name: "VCVTTPD2QQ128", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", typ: "Vec128"}, + {name: "VCVTTPD2QQ256", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", typ: "Vec256"}, + {name: "VCVTTPD2QQ512", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", typ: "Vec512"}, + {name: "VCVTTPD2QQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", typ: "Vec128"}, + {name: "VCVTTPD2QQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", typ: "Vec256"}, + {name: "VCVTTPD2QQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", typ: "Vec512"}, + {name: "VCVTTPD2UDQ256", argLength: 1, reg: w11, asm: "VCVTTPD2UDQ", typ: "Vec256"}, + {name: "VCVTTPD2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQ", typ: "Vec256"}, + {name: "VCVTTPD2UDQX128", argLength: 1, reg: w11, asm: "VCVTTPD2UDQX", typ: "Vec128"}, + {name: "VCVTTPD2UDQXMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQX", typ: "Vec128"}, + {name: "VCVTTPD2UDQY128", argLength: 1, reg: w11, asm: "VCVTTPD2UDQY", typ: "Vec128"}, + {name: "VCVTTPD2UDQYMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQY", typ: "Vec128"}, + {name: "VCVTTPD2UQQ128", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", typ: "Vec128"}, + {name: "VCVTTPD2UQQ256", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", typ: "Vec256"}, + {name: "VCVTTPD2UQQ512", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", typ: "Vec512"}, + {name: "VCVTTPD2UQQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", typ: "Vec128"}, + {name: "VCVTTPD2UQQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", typ: "Vec256"}, + {name: "VCVTTPD2UQQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", typ: "Vec512"}, + {name: "VCVTTPS2DQ128", argLength: 1, reg: v11, asm: "VCVTTPS2DQ", typ: "Vec128"}, + {name: "VCVTTPS2DQ256", argLength: 1, reg: v11, asm: "VCVTTPS2DQ", typ: "Vec256"}, + {name: "VCVTTPS2DQ512", argLength: 1, reg: w11, asm: "VCVTTPS2DQ", typ: "Vec512"}, + {name: "VCVTTPS2DQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", typ: "Vec128"}, + {name: "VCVTTPS2DQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", typ: "Vec256"}, + {name: "VCVTTPS2DQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", typ: "Vec512"}, + {name: "VCVTTPS2QQ256", argLength: 1, reg: w11, asm: "VCVTTPS2QQ", typ: "Vec256"}, + {name: "VCVTTPS2QQ512", argLength: 1, reg: w11, asm: "VCVTTPS2QQ", typ: "Vec512"}, + {name: "VCVTTPS2QQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2QQ", typ: "Vec256"}, + {name: "VCVTTPS2QQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2QQ", typ: "Vec512"}, + {name: "VCVTTPS2UDQ128", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", typ: "Vec128"}, + {name: "VCVTTPS2UDQ256", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", typ: "Vec256"}, + {name: "VCVTTPS2UDQ512", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", typ: "Vec512"}, + {name: "VCVTTPS2UDQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", typ: "Vec128"}, + {name: "VCVTTPS2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", typ: "Vec256"}, + {name: "VCVTTPS2UDQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", typ: "Vec512"}, + {name: "VCVTTPS2UQQ256", argLength: 1, reg: w11, asm: "VCVTTPS2UQQ", typ: "Vec256"}, + {name: "VCVTTPS2UQQ512", argLength: 1, reg: w11, asm: "VCVTTPS2UQQ", typ: "Vec512"}, + {name: "VCVTTPS2UQQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", typ: "Vec256"}, + {name: "VCVTTPS2UQQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", typ: "Vec512"}, + {name: "VCVTUDQ2PD256", argLength: 1, reg: w11, asm: "VCVTUDQ2PD", typ: "Vec256"}, + {name: "VCVTUDQ2PD512", argLength: 1, reg: w11, asm: "VCVTUDQ2PD", typ: "Vec512"}, + {name: "VCVTUDQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTUDQ2PD", typ: "Vec256"}, + {name: "VCVTUDQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTUDQ2PD", typ: "Vec512"}, + {name: "VCVTUDQ2PS128", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", typ: "Vec128"}, + {name: "VCVTUDQ2PS256", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", typ: "Vec256"}, + {name: "VCVTUDQ2PS512", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", typ: "Vec512"}, + {name: "VCVTUDQ2PSMasked128", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", typ: "Vec128"}, + {name: "VCVTUDQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", typ: "Vec256"}, + {name: "VCVTUDQ2PSMasked512", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", typ: "Vec512"}, + {name: "VCVTUQQ2PD128", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", typ: "Vec128"}, + {name: "VCVTUQQ2PD256", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", typ: "Vec256"}, + {name: "VCVTUQQ2PD512", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", typ: "Vec512"}, + {name: "VCVTUQQ2PDMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", typ: "Vec128"}, + {name: "VCVTUQQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", typ: "Vec256"}, + {name: "VCVTUQQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", typ: "Vec512"}, + {name: "VCVTUQQ2PS256", argLength: 1, reg: w11, asm: "VCVTUQQ2PS", typ: "Vec256"}, + {name: "VCVTUQQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTUQQ2PS", typ: "Vec256"}, + {name: "VCVTUQQ2PSX128", argLength: 1, reg: w11, asm: "VCVTUQQ2PSX", typ: "Vec128"}, + {name: "VCVTUQQ2PSXMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PSX", typ: "Vec128"}, + {name: "VCVTUQQ2PSY128", argLength: 1, reg: w11, asm: "VCVTUQQ2PSY", typ: "Vec128"}, + {name: "VCVTUQQ2PSYMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PSY", typ: "Vec128"}, + {name: "VDIVPD128", argLength: 2, reg: v21, asm: "VDIVPD", typ: "Vec128"}, + {name: "VDIVPD256", argLength: 2, reg: v21, asm: "VDIVPD", typ: "Vec256"}, + {name: "VDIVPD512", argLength: 2, reg: w21, asm: "VDIVPD", typ: "Vec512"}, + {name: "VDIVPDMasked128", argLength: 3, reg: w2kw, asm: "VDIVPD", typ: "Vec128"}, + {name: "VDIVPDMasked256", argLength: 3, reg: w2kw, asm: "VDIVPD", typ: "Vec256"}, + {name: "VDIVPDMasked512", argLength: 3, reg: w2kw, asm: "VDIVPD", typ: "Vec512"}, + {name: "VDIVPS128", argLength: 2, reg: v21, asm: "VDIVPS", typ: "Vec128"}, + {name: "VDIVPS256", argLength: 2, reg: v21, asm: "VDIVPS", typ: "Vec256"}, + {name: "VDIVPS512", argLength: 2, reg: w21, asm: "VDIVPS", typ: "Vec512"}, + {name: "VDIVPSMasked128", argLength: 3, reg: w2kw, asm: "VDIVPS", typ: "Vec128"}, + {name: "VDIVPSMasked256", argLength: 3, reg: w2kw, asm: "VDIVPS", typ: "Vec256"}, + {name: "VDIVPSMasked512", argLength: 3, reg: w2kw, asm: "VDIVPS", typ: "Vec512"}, + {name: "VEXPANDPDMasked128", argLength: 2, reg: wkw, asm: "VEXPANDPD", typ: "Vec128"}, + {name: "VEXPANDPDMasked256", argLength: 2, reg: wkw, asm: "VEXPANDPD", typ: "Vec256"}, + {name: "VEXPANDPDMasked512", argLength: 2, reg: wkw, asm: "VEXPANDPD", typ: "Vec512"}, + {name: "VEXPANDPSMasked128", argLength: 2, reg: wkw, asm: "VEXPANDPS", typ: "Vec128"}, + {name: "VEXPANDPSMasked256", argLength: 2, reg: wkw, asm: "VEXPANDPS", typ: "Vec256"}, + {name: "VEXPANDPSMasked512", argLength: 2, reg: wkw, asm: "VEXPANDPS", typ: "Vec512"}, + {name: "VFMADD213PD128", argLength: 3, reg: v31, asm: "VFMADD213PD", typ: "Vec128", resultInArg0: true}, + {name: "VFMADD213PD256", argLength: 3, reg: v31, asm: "VFMADD213PD", typ: "Vec256", resultInArg0: true}, + {name: "VFMADD213PD512", argLength: 3, reg: w31, asm: "VFMADD213PD", typ: "Vec512", resultInArg0: true}, + {name: "VFMADD213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMADD213PD", typ: "Vec128", resultInArg0: true}, + {name: "VFMADD213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMADD213PD", typ: "Vec256", resultInArg0: true}, + {name: "VFMADD213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMADD213PD", typ: "Vec512", resultInArg0: true}, + {name: "VFMADD213PS128", argLength: 3, reg: v31, asm: "VFMADD213PS", typ: "Vec128", resultInArg0: true}, + {name: "VFMADD213PS256", argLength: 3, reg: v31, asm: "VFMADD213PS", typ: "Vec256", resultInArg0: true}, + {name: "VFMADD213PS512", argLength: 3, reg: w31, asm: "VFMADD213PS", typ: "Vec512", resultInArg0: true}, + {name: "VFMADD213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMADD213PS", typ: "Vec128", resultInArg0: true}, + {name: "VFMADD213PSMasked256", argLength: 4, reg: w3kw, asm: "VFMADD213PS", typ: "Vec256", resultInArg0: true}, + {name: "VFMADD213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMADD213PS", typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB213PD128", argLength: 3, reg: v31, asm: "VFMADDSUB213PD", typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB213PD256", argLength: 3, reg: v31, asm: "VFMADDSUB213PD", typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB213PD512", argLength: 3, reg: w31, asm: "VFMADDSUB213PD", typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB213PS128", argLength: 3, reg: v31, asm: "VFMADDSUB213PS", typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB213PS256", argLength: 3, reg: v31, asm: "VFMADDSUB213PS", typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB213PS512", argLength: 3, reg: w31, asm: "VFMADDSUB213PS", typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB213PSMasked256", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD213PD128", argLength: 3, reg: v31, asm: "VFMSUBADD213PD", typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD213PD256", argLength: 3, reg: v31, asm: "VFMSUBADD213PD", typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD213PD512", argLength: 3, reg: w31, asm: "VFMSUBADD213PD", typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD213PS128", argLength: 3, reg: v31, asm: "VFMSUBADD213PS", typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD213PS256", argLength: 3, reg: v31, asm: "VFMSUBADD213PS", typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD213PS512", argLength: 3, reg: w31, asm: "VFMSUBADD213PS", typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD213PSMasked256", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", typ: "Vec512", resultInArg0: true}, + {name: "VGF2P8MULB128", argLength: 2, reg: w21, asm: "VGF2P8MULB", typ: "Vec128"}, + {name: "VGF2P8MULB256", argLength: 2, reg: w21, asm: "VGF2P8MULB", typ: "Vec256"}, + {name: "VGF2P8MULB512", argLength: 2, reg: w21, asm: "VGF2P8MULB", typ: "Vec512"}, + {name: "VGF2P8MULBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", typ: "Vec128"}, + {name: "VGF2P8MULBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", typ: "Vec256"}, + {name: "VGF2P8MULBMasked512", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", typ: "Vec512"}, + {name: "VHADDPD128", argLength: 2, reg: v21, asm: "VHADDPD", typ: "Vec128"}, + {name: "VHADDPD256", argLength: 2, reg: v21, asm: "VHADDPD", typ: "Vec256"}, + {name: "VHADDPS128", argLength: 2, reg: v21, asm: "VHADDPS", typ: "Vec128"}, + {name: "VHADDPS256", argLength: 2, reg: v21, asm: "VHADDPS", typ: "Vec256"}, + {name: "VHSUBPD128", argLength: 2, reg: v21, asm: "VHSUBPD", typ: "Vec128"}, + {name: "VHSUBPD256", argLength: 2, reg: v21, asm: "VHSUBPD", typ: "Vec256"}, + {name: "VHSUBPS128", argLength: 2, reg: v21, asm: "VHSUBPS", typ: "Vec128"}, + {name: "VHSUBPS256", argLength: 2, reg: v21, asm: "VHSUBPS", typ: "Vec256"}, + {name: "VMAXPD128", argLength: 2, reg: v21, asm: "VMAXPD", commutative: true, typ: "Vec128"}, + {name: "VMAXPD256", argLength: 2, reg: v21, asm: "VMAXPD", commutative: true, typ: "Vec256"}, + {name: "VMAXPD512", argLength: 2, reg: w21, asm: "VMAXPD", commutative: true, typ: "Vec512"}, + {name: "VMAXPDMasked128", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec128"}, + {name: "VMAXPDMasked256", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec256"}, + {name: "VMAXPDMasked512", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec512"}, + {name: "VMAXPS128", argLength: 2, reg: v21, asm: "VMAXPS", commutative: true, typ: "Vec128"}, + {name: "VMAXPS256", argLength: 2, reg: v21, asm: "VMAXPS", commutative: true, typ: "Vec256"}, + {name: "VMAXPS512", argLength: 2, reg: w21, asm: "VMAXPS", commutative: true, typ: "Vec512"}, + {name: "VMAXPSMasked128", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec128"}, + {name: "VMAXPSMasked256", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec256"}, + {name: "VMAXPSMasked512", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec512"}, + {name: "VMINPD128", argLength: 2, reg: v21, asm: "VMINPD", commutative: true, typ: "Vec128"}, + {name: "VMINPD256", argLength: 2, reg: v21, asm: "VMINPD", commutative: true, typ: "Vec256"}, + {name: "VMINPD512", argLength: 2, reg: w21, asm: "VMINPD", commutative: true, typ: "Vec512"}, + {name: "VMINPDMasked128", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec128"}, + {name: "VMINPDMasked256", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec256"}, + {name: "VMINPDMasked512", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec512"}, + {name: "VMINPS128", argLength: 2, reg: v21, asm: "VMINPS", commutative: true, typ: "Vec128"}, + {name: "VMINPS256", argLength: 2, reg: v21, asm: "VMINPS", commutative: true, typ: "Vec256"}, + {name: "VMINPS512", argLength: 2, reg: w21, asm: "VMINPS", commutative: true, typ: "Vec512"}, + {name: "VMINPSMasked128", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec128"}, + {name: "VMINPSMasked256", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec256"}, + {name: "VMINPSMasked512", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec512"}, + {name: "VMOVDQU8Masked128", argLength: 2, reg: wkw, asm: "VMOVDQU8", typ: "Vec128"}, + {name: "VMOVDQU8Masked256", argLength: 2, reg: wkw, asm: "VMOVDQU8", typ: "Vec256"}, + {name: "VMOVDQU8Masked512", argLength: 2, reg: wkw, asm: "VMOVDQU8", typ: "Vec512"}, + {name: "VMOVDQU16Masked128", argLength: 2, reg: wkw, asm: "VMOVDQU16", typ: "Vec128"}, + {name: "VMOVDQU16Masked256", argLength: 2, reg: wkw, asm: "VMOVDQU16", typ: "Vec256"}, + {name: "VMOVDQU16Masked512", argLength: 2, reg: wkw, asm: "VMOVDQU16", typ: "Vec512"}, + {name: "VMOVDQU32Masked128", argLength: 2, reg: wkw, asm: "VMOVDQU32", typ: "Vec128"}, + {name: "VMOVDQU32Masked256", argLength: 2, reg: wkw, asm: "VMOVDQU32", typ: "Vec256"}, + {name: "VMOVDQU32Masked512", argLength: 2, reg: wkw, asm: "VMOVDQU32", typ: "Vec512"}, + {name: "VMOVDQU64Masked128", argLength: 2, reg: wkw, asm: "VMOVDQU64", typ: "Vec128"}, + {name: "VMOVDQU64Masked256", argLength: 2, reg: wkw, asm: "VMOVDQU64", typ: "Vec256"}, + {name: "VMOVDQU64Masked512", argLength: 2, reg: wkw, asm: "VMOVDQU64", typ: "Vec512"}, + {name: "VMULPD128", argLength: 2, reg: v21, asm: "VMULPD", commutative: true, typ: "Vec128"}, + {name: "VMULPD256", argLength: 2, reg: v21, asm: "VMULPD", commutative: true, typ: "Vec256"}, + {name: "VMULPD512", argLength: 2, reg: w21, asm: "VMULPD", commutative: true, typ: "Vec512"}, + {name: "VMULPDMasked128", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec128"}, + {name: "VMULPDMasked256", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec256"}, + {name: "VMULPDMasked512", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec512"}, + {name: "VMULPS128", argLength: 2, reg: v21, asm: "VMULPS", commutative: true, typ: "Vec128"}, + {name: "VMULPS256", argLength: 2, reg: v21, asm: "VMULPS", commutative: true, typ: "Vec256"}, + {name: "VMULPS512", argLength: 2, reg: w21, asm: "VMULPS", commutative: true, typ: "Vec512"}, + {name: "VMULPSMasked128", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec128"}, + {name: "VMULPSMasked256", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec256"}, + {name: "VMULPSMasked512", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec512"}, + {name: "VPABSB128", argLength: 1, reg: v11, asm: "VPABSB", typ: "Vec128"}, + {name: "VPABSB256", argLength: 1, reg: v11, asm: "VPABSB", typ: "Vec256"}, + {name: "VPABSB512", argLength: 1, reg: w11, asm: "VPABSB", typ: "Vec512"}, + {name: "VPABSBMasked128", argLength: 2, reg: wkw, asm: "VPABSB", typ: "Vec128"}, + {name: "VPABSBMasked256", argLength: 2, reg: wkw, asm: "VPABSB", typ: "Vec256"}, + {name: "VPABSBMasked512", argLength: 2, reg: wkw, asm: "VPABSB", typ: "Vec512"}, + {name: "VPABSD128", argLength: 1, reg: v11, asm: "VPABSD", typ: "Vec128"}, + {name: "VPABSD256", argLength: 1, reg: v11, asm: "VPABSD", typ: "Vec256"}, + {name: "VPABSD512", argLength: 1, reg: w11, asm: "VPABSD", typ: "Vec512"}, + {name: "VPABSDMasked128", argLength: 2, reg: wkw, asm: "VPABSD", typ: "Vec128"}, + {name: "VPABSDMasked256", argLength: 2, reg: wkw, asm: "VPABSD", typ: "Vec256"}, + {name: "VPABSDMasked512", argLength: 2, reg: wkw, asm: "VPABSD", typ: "Vec512"}, + {name: "VPABSQ128", argLength: 1, reg: w11, asm: "VPABSQ", typ: "Vec128"}, + {name: "VPABSQ256", argLength: 1, reg: w11, asm: "VPABSQ", typ: "Vec256"}, + {name: "VPABSQ512", argLength: 1, reg: w11, asm: "VPABSQ", typ: "Vec512"}, + {name: "VPABSQMasked128", argLength: 2, reg: wkw, asm: "VPABSQ", typ: "Vec128"}, + {name: "VPABSQMasked256", argLength: 2, reg: wkw, asm: "VPABSQ", typ: "Vec256"}, + {name: "VPABSQMasked512", argLength: 2, reg: wkw, asm: "VPABSQ", typ: "Vec512"}, + {name: "VPABSW128", argLength: 1, reg: v11, asm: "VPABSW", typ: "Vec128"}, + {name: "VPABSW256", argLength: 1, reg: v11, asm: "VPABSW", typ: "Vec256"}, + {name: "VPABSW512", argLength: 1, reg: w11, asm: "VPABSW", typ: "Vec512"}, + {name: "VPABSWMasked128", argLength: 2, reg: wkw, asm: "VPABSW", typ: "Vec128"}, + {name: "VPABSWMasked256", argLength: 2, reg: wkw, asm: "VPABSW", typ: "Vec256"}, + {name: "VPABSWMasked512", argLength: 2, reg: wkw, asm: "VPABSW", typ: "Vec512"}, + {name: "VPACKSSDW128", argLength: 2, reg: v21, asm: "VPACKSSDW", typ: "Vec128"}, + {name: "VPACKSSDW256", argLength: 2, reg: v21, asm: "VPACKSSDW", typ: "Vec256"}, + {name: "VPACKSSDW512", argLength: 2, reg: w21, asm: "VPACKSSDW", typ: "Vec512"}, + {name: "VPACKSSDWMasked128", argLength: 3, reg: w2kw, asm: "VPACKSSDW", typ: "Vec128"}, + {name: "VPACKSSDWMasked256", argLength: 3, reg: w2kw, asm: "VPACKSSDW", typ: "Vec256"}, + {name: "VPACKSSDWMasked512", argLength: 3, reg: w2kw, asm: "VPACKSSDW", typ: "Vec512"}, + {name: "VPACKUSDW128", argLength: 2, reg: v21, asm: "VPACKUSDW", typ: "Vec128"}, + {name: "VPACKUSDW256", argLength: 2, reg: v21, asm: "VPACKUSDW", typ: "Vec256"}, + {name: "VPACKUSDW512", argLength: 2, reg: w21, asm: "VPACKUSDW", typ: "Vec512"}, + {name: "VPACKUSDWMasked128", argLength: 3, reg: w2kw, asm: "VPACKUSDW", typ: "Vec128"}, + {name: "VPACKUSDWMasked256", argLength: 3, reg: w2kw, asm: "VPACKUSDW", typ: "Vec256"}, + {name: "VPACKUSDWMasked512", argLength: 3, reg: w2kw, asm: "VPACKUSDW", typ: "Vec512"}, + {name: "VPADDB128", argLength: 2, reg: v21, asm: "VPADDB", commutative: true, typ: "Vec128"}, + {name: "VPADDB256", argLength: 2, reg: v21, asm: "VPADDB", commutative: true, typ: "Vec256"}, + {name: "VPADDB512", argLength: 2, reg: w21, asm: "VPADDB", commutative: true, typ: "Vec512"}, + {name: "VPADDBMasked128", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec128"}, + {name: "VPADDBMasked256", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec256"}, + {name: "VPADDBMasked512", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec512"}, + {name: "VPADDD128", argLength: 2, reg: v21, asm: "VPADDD", commutative: true, typ: "Vec128"}, + {name: "VPADDD256", argLength: 2, reg: v21, asm: "VPADDD", commutative: true, typ: "Vec256"}, + {name: "VPADDD512", argLength: 2, reg: w21, asm: "VPADDD", commutative: true, typ: "Vec512"}, + {name: "VPADDDMasked128", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec128"}, + {name: "VPADDDMasked256", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec256"}, + {name: "VPADDDMasked512", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec512"}, + {name: "VPADDQ128", argLength: 2, reg: v21, asm: "VPADDQ", commutative: true, typ: "Vec128"}, + {name: "VPADDQ256", argLength: 2, reg: v21, asm: "VPADDQ", commutative: true, typ: "Vec256"}, + {name: "VPADDQ512", argLength: 2, reg: w21, asm: "VPADDQ", commutative: true, typ: "Vec512"}, + {name: "VPADDQMasked128", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec128"}, + {name: "VPADDQMasked256", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec256"}, + {name: "VPADDQMasked512", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec512"}, + {name: "VPADDSB128", argLength: 2, reg: v21, asm: "VPADDSB", commutative: true, typ: "Vec128"}, + {name: "VPADDSB256", argLength: 2, reg: v21, asm: "VPADDSB", commutative: true, typ: "Vec256"}, + {name: "VPADDSB512", argLength: 2, reg: w21, asm: "VPADDSB", commutative: true, typ: "Vec512"}, + {name: "VPADDSBMasked128", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec128"}, + {name: "VPADDSBMasked256", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec256"}, + {name: "VPADDSBMasked512", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec512"}, + {name: "VPADDSW128", argLength: 2, reg: v21, asm: "VPADDSW", commutative: true, typ: "Vec128"}, + {name: "VPADDSW256", argLength: 2, reg: v21, asm: "VPADDSW", commutative: true, typ: "Vec256"}, + {name: "VPADDSW512", argLength: 2, reg: w21, asm: "VPADDSW", commutative: true, typ: "Vec512"}, + {name: "VPADDSWMasked128", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec128"}, + {name: "VPADDSWMasked256", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec256"}, + {name: "VPADDSWMasked512", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec512"}, + {name: "VPADDUSB128", argLength: 2, reg: v21, asm: "VPADDUSB", commutative: true, typ: "Vec128"}, + {name: "VPADDUSB256", argLength: 2, reg: v21, asm: "VPADDUSB", commutative: true, typ: "Vec256"}, + {name: "VPADDUSB512", argLength: 2, reg: w21, asm: "VPADDUSB", commutative: true, typ: "Vec512"}, + {name: "VPADDUSBMasked128", argLength: 3, reg: w2kw, asm: "VPADDUSB", commutative: true, typ: "Vec128"}, + {name: "VPADDUSBMasked256", argLength: 3, reg: w2kw, asm: "VPADDUSB", commutative: true, typ: "Vec256"}, + {name: "VPADDUSBMasked512", argLength: 3, reg: w2kw, asm: "VPADDUSB", commutative: true, typ: "Vec512"}, + {name: "VPADDUSW128", argLength: 2, reg: v21, asm: "VPADDUSW", commutative: true, typ: "Vec128"}, + {name: "VPADDUSW256", argLength: 2, reg: v21, asm: "VPADDUSW", commutative: true, typ: "Vec256"}, + {name: "VPADDUSW512", argLength: 2, reg: w21, asm: "VPADDUSW", commutative: true, typ: "Vec512"}, + {name: "VPADDUSWMasked128", argLength: 3, reg: w2kw, asm: "VPADDUSW", commutative: true, typ: "Vec128"}, + {name: "VPADDUSWMasked256", argLength: 3, reg: w2kw, asm: "VPADDUSW", commutative: true, typ: "Vec256"}, + {name: "VPADDUSWMasked512", argLength: 3, reg: w2kw, asm: "VPADDUSW", commutative: true, typ: "Vec512"}, + {name: "VPADDW128", argLength: 2, reg: v21, asm: "VPADDW", commutative: true, typ: "Vec128"}, + {name: "VPADDW256", argLength: 2, reg: v21, asm: "VPADDW", commutative: true, typ: "Vec256"}, + {name: "VPADDW512", argLength: 2, reg: w21, asm: "VPADDW", commutative: true, typ: "Vec512"}, + {name: "VPADDWMasked128", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec128"}, + {name: "VPADDWMasked256", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec256"}, + {name: "VPADDWMasked512", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec512"}, + {name: "VPAND128", argLength: 2, reg: v21, asm: "VPAND", commutative: true, typ: "Vec128"}, + {name: "VPAND256", argLength: 2, reg: v21, asm: "VPAND", commutative: true, typ: "Vec256"}, + {name: "VPANDD512", argLength: 2, reg: w21, asm: "VPANDD", commutative: true, typ: "Vec512"}, + {name: "VPANDDMasked128", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec128"}, + {name: "VPANDDMasked256", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec256"}, + {name: "VPANDDMasked512", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec512"}, + {name: "VPANDN128", argLength: 2, reg: v21, asm: "VPANDN", typ: "Vec128"}, + {name: "VPANDN256", argLength: 2, reg: v21, asm: "VPANDN", typ: "Vec256"}, + {name: "VPANDND512", argLength: 2, reg: w21, asm: "VPANDND", typ: "Vec512"}, + {name: "VPANDNDMasked128", argLength: 3, reg: w2kw, asm: "VPANDND", typ: "Vec128"}, + {name: "VPANDNDMasked256", argLength: 3, reg: w2kw, asm: "VPANDND", typ: "Vec256"}, + {name: "VPANDNDMasked512", argLength: 3, reg: w2kw, asm: "VPANDND", typ: "Vec512"}, + {name: "VPANDNQ512", argLength: 2, reg: w21, asm: "VPANDNQ", typ: "Vec512"}, + {name: "VPANDNQMasked128", argLength: 3, reg: w2kw, asm: "VPANDNQ", typ: "Vec128"}, + {name: "VPANDNQMasked256", argLength: 3, reg: w2kw, asm: "VPANDNQ", typ: "Vec256"}, + {name: "VPANDNQMasked512", argLength: 3, reg: w2kw, asm: "VPANDNQ", typ: "Vec512"}, + {name: "VPANDQ512", argLength: 2, reg: w21, asm: "VPANDQ", commutative: true, typ: "Vec512"}, + {name: "VPANDQMasked128", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec128"}, + {name: "VPANDQMasked256", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec256"}, + {name: "VPANDQMasked512", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec512"}, + {name: "VPAVGB128", argLength: 2, reg: v21, asm: "VPAVGB", commutative: true, typ: "Vec128"}, + {name: "VPAVGB256", argLength: 2, reg: v21, asm: "VPAVGB", commutative: true, typ: "Vec256"}, + {name: "VPAVGB512", argLength: 2, reg: w21, asm: "VPAVGB", commutative: true, typ: "Vec512"}, + {name: "VPAVGBMasked128", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec128"}, + {name: "VPAVGBMasked256", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec256"}, + {name: "VPAVGBMasked512", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec512"}, + {name: "VPAVGW128", argLength: 2, reg: v21, asm: "VPAVGW", commutative: true, typ: "Vec128"}, + {name: "VPAVGW256", argLength: 2, reg: v21, asm: "VPAVGW", commutative: true, typ: "Vec256"}, + {name: "VPAVGW512", argLength: 2, reg: w21, asm: "VPAVGW", commutative: true, typ: "Vec512"}, + {name: "VPAVGWMasked128", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec128"}, + {name: "VPAVGWMasked256", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec256"}, + {name: "VPAVGWMasked512", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec512"}, + {name: "VPBLENDMBMasked512", argLength: 3, reg: w2kw, asm: "VPBLENDMB", typ: "Vec512"}, + {name: "VPBLENDMDMasked512", argLength: 3, reg: w2kw, asm: "VPBLENDMD", typ: "Vec512"}, + {name: "VPBLENDMQMasked512", argLength: 3, reg: w2kw, asm: "VPBLENDMQ", typ: "Vec512"}, + {name: "VPBLENDMWMasked512", argLength: 3, reg: w2kw, asm: "VPBLENDMW", typ: "Vec512"}, + {name: "VPBLENDVB128", argLength: 3, reg: v31, asm: "VPBLENDVB", typ: "Vec128"}, + {name: "VPBLENDVB256", argLength: 3, reg: v31, asm: "VPBLENDVB", typ: "Vec256"}, + {name: "VPBROADCASTB128", argLength: 1, reg: v11, asm: "VPBROADCASTB", typ: "Vec128"}, + {name: "VPBROADCASTB256", argLength: 1, reg: v11, asm: "VPBROADCASTB", typ: "Vec256"}, + {name: "VPBROADCASTB512", argLength: 1, reg: w11, asm: "VPBROADCASTB", typ: "Vec512"}, + {name: "VPBROADCASTBMasked128", argLength: 2, reg: wkw, asm: "VPBROADCASTB", typ: "Vec128"}, + {name: "VPBROADCASTBMasked256", argLength: 2, reg: wkw, asm: "VPBROADCASTB", typ: "Vec256"}, + {name: "VPBROADCASTBMasked512", argLength: 2, reg: wkw, asm: "VPBROADCASTB", typ: "Vec512"}, + {name: "VPBROADCASTD128", argLength: 1, reg: v11, asm: "VPBROADCASTD", typ: "Vec128"}, + {name: "VPBROADCASTD256", argLength: 1, reg: v11, asm: "VPBROADCASTD", typ: "Vec256"}, + {name: "VPBROADCASTD512", argLength: 1, reg: w11, asm: "VPBROADCASTD", typ: "Vec512"}, + {name: "VPBROADCASTDMasked128", argLength: 2, reg: wkw, asm: "VPBROADCASTD", typ: "Vec128"}, + {name: "VPBROADCASTDMasked256", argLength: 2, reg: wkw, asm: "VPBROADCASTD", typ: "Vec256"}, + {name: "VPBROADCASTDMasked512", argLength: 2, reg: wkw, asm: "VPBROADCASTD", typ: "Vec512"}, + {name: "VPBROADCASTQ128", argLength: 1, reg: v11, asm: "VPBROADCASTQ", typ: "Vec128"}, + {name: "VPBROADCASTQ256", argLength: 1, reg: v11, asm: "VPBROADCASTQ", typ: "Vec256"}, + {name: "VPBROADCASTQ512", argLength: 1, reg: w11, asm: "VPBROADCASTQ", typ: "Vec512"}, + {name: "VPBROADCASTQMasked128", argLength: 2, reg: wkw, asm: "VPBROADCASTQ", typ: "Vec128"}, + {name: "VPBROADCASTQMasked256", argLength: 2, reg: wkw, asm: "VPBROADCASTQ", typ: "Vec256"}, + {name: "VPBROADCASTQMasked512", argLength: 2, reg: wkw, asm: "VPBROADCASTQ", typ: "Vec512"}, + {name: "VPBROADCASTW128", argLength: 1, reg: v11, asm: "VPBROADCASTW", typ: "Vec128"}, + {name: "VPBROADCASTW256", argLength: 1, reg: v11, asm: "VPBROADCASTW", typ: "Vec256"}, + {name: "VPBROADCASTW512", argLength: 1, reg: w11, asm: "VPBROADCASTW", typ: "Vec512"}, + {name: "VPBROADCASTWMasked128", argLength: 2, reg: wkw, asm: "VPBROADCASTW", typ: "Vec128"}, + {name: "VPBROADCASTWMasked256", argLength: 2, reg: wkw, asm: "VPBROADCASTW", typ: "Vec256"}, + {name: "VPBROADCASTWMasked512", argLength: 2, reg: wkw, asm: "VPBROADCASTW", typ: "Vec512"}, + {name: "VPCMPEQB128", argLength: 2, reg: v21, asm: "VPCMPEQB", commutative: true, typ: "Vec128"}, + {name: "VPCMPEQB256", argLength: 2, reg: v21, asm: "VPCMPEQB", commutative: true, typ: "Vec256"}, + {name: "VPCMPEQB512", argLength: 2, reg: w2k, asm: "VPCMPEQB", commutative: true, typ: "Mask"}, + {name: "VPCMPEQD128", argLength: 2, reg: v21, asm: "VPCMPEQD", commutative: true, typ: "Vec128"}, + {name: "VPCMPEQD256", argLength: 2, reg: v21, asm: "VPCMPEQD", commutative: true, typ: "Vec256"}, + {name: "VPCMPEQD512", argLength: 2, reg: w2k, asm: "VPCMPEQD", commutative: true, typ: "Mask"}, + {name: "VPCMPEQQ128", argLength: 2, reg: v21, asm: "VPCMPEQQ", commutative: true, typ: "Vec128"}, + {name: "VPCMPEQQ256", argLength: 2, reg: v21, asm: "VPCMPEQQ", commutative: true, typ: "Vec256"}, + {name: "VPCMPEQQ512", argLength: 2, reg: w2k, asm: "VPCMPEQQ", commutative: true, typ: "Mask"}, + {name: "VPCMPEQW128", argLength: 2, reg: v21, asm: "VPCMPEQW", commutative: true, typ: "Vec128"}, + {name: "VPCMPEQW256", argLength: 2, reg: v21, asm: "VPCMPEQW", commutative: true, typ: "Vec256"}, + {name: "VPCMPEQW512", argLength: 2, reg: w2k, asm: "VPCMPEQW", commutative: true, typ: "Mask"}, + {name: "VPCMPGTB128", argLength: 2, reg: v21, asm: "VPCMPGTB", typ: "Vec128"}, + {name: "VPCMPGTB256", argLength: 2, reg: v21, asm: "VPCMPGTB", typ: "Vec256"}, + {name: "VPCMPGTB512", argLength: 2, reg: w2k, asm: "VPCMPGTB", typ: "Mask"}, + {name: "VPCMPGTD128", argLength: 2, reg: v21, asm: "VPCMPGTD", typ: "Vec128"}, + {name: "VPCMPGTD256", argLength: 2, reg: v21, asm: "VPCMPGTD", typ: "Vec256"}, + {name: "VPCMPGTD512", argLength: 2, reg: w2k, asm: "VPCMPGTD", typ: "Mask"}, + {name: "VPCMPGTQ128", argLength: 2, reg: v21, asm: "VPCMPGTQ", typ: "Vec128"}, + {name: "VPCMPGTQ256", argLength: 2, reg: v21, asm: "VPCMPGTQ", typ: "Vec256"}, + {name: "VPCMPGTQ512", argLength: 2, reg: w2k, asm: "VPCMPGTQ", typ: "Mask"}, + {name: "VPCMPGTW128", argLength: 2, reg: v21, asm: "VPCMPGTW", typ: "Vec128"}, + {name: "VPCMPGTW256", argLength: 2, reg: v21, asm: "VPCMPGTW", typ: "Vec256"}, + {name: "VPCMPGTW512", argLength: 2, reg: w2k, asm: "VPCMPGTW", typ: "Mask"}, + {name: "VPCOMPRESSBMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", typ: "Vec128"}, + {name: "VPCOMPRESSBMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", typ: "Vec256"}, + {name: "VPCOMPRESSBMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", typ: "Vec512"}, + {name: "VPCOMPRESSDMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", typ: "Vec128"}, + {name: "VPCOMPRESSDMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", typ: "Vec256"}, + {name: "VPCOMPRESSDMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", typ: "Vec512"}, + {name: "VPCOMPRESSQMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", typ: "Vec128"}, + {name: "VPCOMPRESSQMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", typ: "Vec256"}, + {name: "VPCOMPRESSQMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", typ: "Vec512"}, + {name: "VPCOMPRESSWMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", typ: "Vec128"}, + {name: "VPCOMPRESSWMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", typ: "Vec256"}, + {name: "VPCOMPRESSWMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", typ: "Vec512"}, + {name: "VPDPWSSD128", argLength: 3, reg: v31, asm: "VPDPWSSD", typ: "Vec128", resultInArg0: true}, + {name: "VPDPWSSD256", argLength: 3, reg: v31, asm: "VPDPWSSD", typ: "Vec256", resultInArg0: true}, + {name: "VPDPWSSD512", argLength: 3, reg: w31, asm: "VPDPWSSD", typ: "Vec512", resultInArg0: true}, + {name: "VPDPWSSDMasked128", argLength: 4, reg: w3kw, asm: "VPDPWSSD", typ: "Vec128", resultInArg0: true}, + {name: "VPDPWSSDMasked256", argLength: 4, reg: w3kw, asm: "VPDPWSSD", typ: "Vec256", resultInArg0: true}, + {name: "VPDPWSSDMasked512", argLength: 4, reg: w3kw, asm: "VPDPWSSD", typ: "Vec512", resultInArg0: true}, + {name: "VPERMB128", argLength: 2, reg: w21, asm: "VPERMB", typ: "Vec128"}, + {name: "VPERMB256", argLength: 2, reg: w21, asm: "VPERMB", typ: "Vec256"}, + {name: "VPERMB512", argLength: 2, reg: w21, asm: "VPERMB", typ: "Vec512"}, + {name: "VPERMBMasked128", argLength: 3, reg: w2kw, asm: "VPERMB", typ: "Vec128"}, + {name: "VPERMBMasked256", argLength: 3, reg: w2kw, asm: "VPERMB", typ: "Vec256"}, + {name: "VPERMBMasked512", argLength: 3, reg: w2kw, asm: "VPERMB", typ: "Vec512"}, + {name: "VPERMD256", argLength: 2, reg: v21, asm: "VPERMD", typ: "Vec256"}, + {name: "VPERMD512", argLength: 2, reg: w21, asm: "VPERMD", typ: "Vec512"}, + {name: "VPERMDMasked256", argLength: 3, reg: w2kw, asm: "VPERMD", typ: "Vec256"}, + {name: "VPERMDMasked512", argLength: 3, reg: w2kw, asm: "VPERMD", typ: "Vec512"}, + {name: "VPERMI2B128", argLength: 3, reg: w31, asm: "VPERMI2B", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2B256", argLength: 3, reg: w31, asm: "VPERMI2B", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2B512", argLength: 3, reg: w31, asm: "VPERMI2B", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2BMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2B", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2BMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2B", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2BMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2B", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2D128", argLength: 3, reg: w31, asm: "VPERMI2D", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2D256", argLength: 3, reg: w31, asm: "VPERMI2D", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2D512", argLength: 3, reg: w31, asm: "VPERMI2D", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2DMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2D", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2DMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2D", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2DMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2D", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2PD128", argLength: 3, reg: w31, asm: "VPERMI2PD", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2PD256", argLength: 3, reg: w31, asm: "VPERMI2PD", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2PD512", argLength: 3, reg: w31, asm: "VPERMI2PD", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2PDMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2PD", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2PDMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2PD", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2PDMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2PD", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2PS128", argLength: 3, reg: w31, asm: "VPERMI2PS", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2PS256", argLength: 3, reg: w31, asm: "VPERMI2PS", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2PS512", argLength: 3, reg: w31, asm: "VPERMI2PS", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2PSMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2PS", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2PSMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2PS", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2PSMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2PS", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2Q128", argLength: 3, reg: w31, asm: "VPERMI2Q", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2Q256", argLength: 3, reg: w31, asm: "VPERMI2Q", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2Q512", argLength: 3, reg: w31, asm: "VPERMI2Q", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2QMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2Q", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2QMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2Q", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2QMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2Q", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2W128", argLength: 3, reg: w31, asm: "VPERMI2W", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2W256", argLength: 3, reg: w31, asm: "VPERMI2W", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2W512", argLength: 3, reg: w31, asm: "VPERMI2W", typ: "Vec512", resultInArg0: true}, + {name: "VPERMI2WMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2W", typ: "Vec128", resultInArg0: true}, + {name: "VPERMI2WMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2W", typ: "Vec256", resultInArg0: true}, + {name: "VPERMI2WMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2W", typ: "Vec512", resultInArg0: true}, + {name: "VPERMPD256", argLength: 2, reg: w21, asm: "VPERMPD", typ: "Vec256"}, + {name: "VPERMPD512", argLength: 2, reg: w21, asm: "VPERMPD", typ: "Vec512"}, + {name: "VPERMPDMasked256", argLength: 3, reg: w2kw, asm: "VPERMPD", typ: "Vec256"}, + {name: "VPERMPDMasked512", argLength: 3, reg: w2kw, asm: "VPERMPD", typ: "Vec512"}, + {name: "VPERMPS256", argLength: 2, reg: v21, asm: "VPERMPS", typ: "Vec256"}, + {name: "VPERMPS512", argLength: 2, reg: w21, asm: "VPERMPS", typ: "Vec512"}, + {name: "VPERMPSMasked256", argLength: 3, reg: w2kw, asm: "VPERMPS", typ: "Vec256"}, + {name: "VPERMPSMasked512", argLength: 3, reg: w2kw, asm: "VPERMPS", typ: "Vec512"}, + {name: "VPERMQ256", argLength: 2, reg: w21, asm: "VPERMQ", typ: "Vec256"}, + {name: "VPERMQ512", argLength: 2, reg: w21, asm: "VPERMQ", typ: "Vec512"}, + {name: "VPERMQMasked256", argLength: 3, reg: w2kw, asm: "VPERMQ", typ: "Vec256"}, + {name: "VPERMQMasked512", argLength: 3, reg: w2kw, asm: "VPERMQ", typ: "Vec512"}, + {name: "VPERMW128", argLength: 2, reg: w21, asm: "VPERMW", typ: "Vec128"}, + {name: "VPERMW256", argLength: 2, reg: w21, asm: "VPERMW", typ: "Vec256"}, + {name: "VPERMW512", argLength: 2, reg: w21, asm: "VPERMW", typ: "Vec512"}, + {name: "VPERMWMasked128", argLength: 3, reg: w2kw, asm: "VPERMW", typ: "Vec128"}, + {name: "VPERMWMasked256", argLength: 3, reg: w2kw, asm: "VPERMW", typ: "Vec256"}, + {name: "VPERMWMasked512", argLength: 3, reg: w2kw, asm: "VPERMW", typ: "Vec512"}, + {name: "VPEXPANDBMasked128", argLength: 2, reg: wkw, asm: "VPEXPANDB", typ: "Vec128"}, + {name: "VPEXPANDBMasked256", argLength: 2, reg: wkw, asm: "VPEXPANDB", typ: "Vec256"}, + {name: "VPEXPANDBMasked512", argLength: 2, reg: wkw, asm: "VPEXPANDB", typ: "Vec512"}, + {name: "VPEXPANDDMasked128", argLength: 2, reg: wkw, asm: "VPEXPANDD", typ: "Vec128"}, + {name: "VPEXPANDDMasked256", argLength: 2, reg: wkw, asm: "VPEXPANDD", typ: "Vec256"}, + {name: "VPEXPANDDMasked512", argLength: 2, reg: wkw, asm: "VPEXPANDD", typ: "Vec512"}, + {name: "VPEXPANDQMasked128", argLength: 2, reg: wkw, asm: "VPEXPANDQ", typ: "Vec128"}, + {name: "VPEXPANDQMasked256", argLength: 2, reg: wkw, asm: "VPEXPANDQ", typ: "Vec256"}, + {name: "VPEXPANDQMasked512", argLength: 2, reg: wkw, asm: "VPEXPANDQ", typ: "Vec512"}, + {name: "VPEXPANDWMasked128", argLength: 2, reg: wkw, asm: "VPEXPANDW", typ: "Vec128"}, + {name: "VPEXPANDWMasked256", argLength: 2, reg: wkw, asm: "VPEXPANDW", typ: "Vec256"}, + {name: "VPEXPANDWMasked512", argLength: 2, reg: wkw, asm: "VPEXPANDW", typ: "Vec512"}, + {name: "VPHADDD128", argLength: 2, reg: v21, asm: "VPHADDD", typ: "Vec128"}, + {name: "VPHADDD256", argLength: 2, reg: v21, asm: "VPHADDD", typ: "Vec256"}, + {name: "VPHADDSW128", argLength: 2, reg: v21, asm: "VPHADDSW", typ: "Vec128"}, + {name: "VPHADDSW256", argLength: 2, reg: v21, asm: "VPHADDSW", typ: "Vec256"}, + {name: "VPHADDW128", argLength: 2, reg: v21, asm: "VPHADDW", typ: "Vec128"}, + {name: "VPHADDW256", argLength: 2, reg: v21, asm: "VPHADDW", typ: "Vec256"}, + {name: "VPHSUBD128", argLength: 2, reg: v21, asm: "VPHSUBD", typ: "Vec128"}, + {name: "VPHSUBD256", argLength: 2, reg: v21, asm: "VPHSUBD", typ: "Vec256"}, + {name: "VPHSUBSW128", argLength: 2, reg: v21, asm: "VPHSUBSW", typ: "Vec128"}, + {name: "VPHSUBSW256", argLength: 2, reg: v21, asm: "VPHSUBSW", typ: "Vec256"}, + {name: "VPHSUBW128", argLength: 2, reg: v21, asm: "VPHSUBW", typ: "Vec128"}, + {name: "VPHSUBW256", argLength: 2, reg: v21, asm: "VPHSUBW", typ: "Vec256"}, + {name: "VPLZCNTD128", argLength: 1, reg: w11, asm: "VPLZCNTD", typ: "Vec128"}, + {name: "VPLZCNTD256", argLength: 1, reg: w11, asm: "VPLZCNTD", typ: "Vec256"}, + {name: "VPLZCNTD512", argLength: 1, reg: w11, asm: "VPLZCNTD", typ: "Vec512"}, + {name: "VPLZCNTDMasked128", argLength: 2, reg: wkw, asm: "VPLZCNTD", typ: "Vec128"}, + {name: "VPLZCNTDMasked256", argLength: 2, reg: wkw, asm: "VPLZCNTD", typ: "Vec256"}, + {name: "VPLZCNTDMasked512", argLength: 2, reg: wkw, asm: "VPLZCNTD", typ: "Vec512"}, + {name: "VPLZCNTQ128", argLength: 1, reg: w11, asm: "VPLZCNTQ", typ: "Vec128"}, + {name: "VPLZCNTQ256", argLength: 1, reg: w11, asm: "VPLZCNTQ", typ: "Vec256"}, + {name: "VPLZCNTQ512", argLength: 1, reg: w11, asm: "VPLZCNTQ", typ: "Vec512"}, + {name: "VPLZCNTQMasked128", argLength: 2, reg: wkw, asm: "VPLZCNTQ", typ: "Vec128"}, + {name: "VPLZCNTQMasked256", argLength: 2, reg: wkw, asm: "VPLZCNTQ", typ: "Vec256"}, + {name: "VPLZCNTQMasked512", argLength: 2, reg: wkw, asm: "VPLZCNTQ", typ: "Vec512"}, + {name: "VPMADDUBSW128", argLength: 2, reg: v21, asm: "VPMADDUBSW", typ: "Vec128"}, + {name: "VPMADDUBSW256", argLength: 2, reg: v21, asm: "VPMADDUBSW", typ: "Vec256"}, + {name: "VPMADDUBSW512", argLength: 2, reg: w21, asm: "VPMADDUBSW", typ: "Vec512"}, + {name: "VPMADDUBSWMasked128", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", typ: "Vec128"}, + {name: "VPMADDUBSWMasked256", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", typ: "Vec256"}, + {name: "VPMADDUBSWMasked512", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", typ: "Vec512"}, + {name: "VPMADDWD128", argLength: 2, reg: v21, asm: "VPMADDWD", typ: "Vec128"}, + {name: "VPMADDWD256", argLength: 2, reg: v21, asm: "VPMADDWD", typ: "Vec256"}, + {name: "VPMADDWD512", argLength: 2, reg: w21, asm: "VPMADDWD", typ: "Vec512"}, + {name: "VPMADDWDMasked128", argLength: 3, reg: w2kw, asm: "VPMADDWD", typ: "Vec128"}, + {name: "VPMADDWDMasked256", argLength: 3, reg: w2kw, asm: "VPMADDWD", typ: "Vec256"}, + {name: "VPMADDWDMasked512", argLength: 3, reg: w2kw, asm: "VPMADDWD", typ: "Vec512"}, + {name: "VPMAXSB128", argLength: 2, reg: v21, asm: "VPMAXSB", commutative: true, typ: "Vec128"}, + {name: "VPMAXSB256", argLength: 2, reg: v21, asm: "VPMAXSB", commutative: true, typ: "Vec256"}, + {name: "VPMAXSB512", argLength: 2, reg: w21, asm: "VPMAXSB", commutative: true, typ: "Vec512"}, + {name: "VPMAXSBMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec128"}, + {name: "VPMAXSBMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec256"}, + {name: "VPMAXSBMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec512"}, + {name: "VPMAXSD128", argLength: 2, reg: v21, asm: "VPMAXSD", commutative: true, typ: "Vec128"}, + {name: "VPMAXSD256", argLength: 2, reg: v21, asm: "VPMAXSD", commutative: true, typ: "Vec256"}, + {name: "VPMAXSD512", argLength: 2, reg: w21, asm: "VPMAXSD", commutative: true, typ: "Vec512"}, + {name: "VPMAXSDMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec128"}, + {name: "VPMAXSDMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec256"}, + {name: "VPMAXSDMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec512"}, + {name: "VPMAXSQ128", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec128"}, + {name: "VPMAXSQ256", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec256"}, + {name: "VPMAXSQ512", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec512"}, + {name: "VPMAXSQMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec128"}, + {name: "VPMAXSQMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec256"}, + {name: "VPMAXSQMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec512"}, + {name: "VPMAXSW128", argLength: 2, reg: v21, asm: "VPMAXSW", commutative: true, typ: "Vec128"}, + {name: "VPMAXSW256", argLength: 2, reg: v21, asm: "VPMAXSW", commutative: true, typ: "Vec256"}, + {name: "VPMAXSW512", argLength: 2, reg: w21, asm: "VPMAXSW", commutative: true, typ: "Vec512"}, + {name: "VPMAXSWMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec128"}, + {name: "VPMAXSWMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec256"}, + {name: "VPMAXSWMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec512"}, + {name: "VPMAXUB128", argLength: 2, reg: v21, asm: "VPMAXUB", commutative: true, typ: "Vec128"}, + {name: "VPMAXUB256", argLength: 2, reg: v21, asm: "VPMAXUB", commutative: true, typ: "Vec256"}, + {name: "VPMAXUB512", argLength: 2, reg: w21, asm: "VPMAXUB", commutative: true, typ: "Vec512"}, + {name: "VPMAXUBMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec128"}, + {name: "VPMAXUBMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec256"}, + {name: "VPMAXUBMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec512"}, + {name: "VPMAXUD128", argLength: 2, reg: v21, asm: "VPMAXUD", commutative: true, typ: "Vec128"}, + {name: "VPMAXUD256", argLength: 2, reg: v21, asm: "VPMAXUD", commutative: true, typ: "Vec256"}, + {name: "VPMAXUD512", argLength: 2, reg: w21, asm: "VPMAXUD", commutative: true, typ: "Vec512"}, + {name: "VPMAXUDMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec128"}, + {name: "VPMAXUDMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec256"}, + {name: "VPMAXUDMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec512"}, + {name: "VPMAXUQ128", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec128"}, + {name: "VPMAXUQ256", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec256"}, + {name: "VPMAXUQ512", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec512"}, + {name: "VPMAXUQMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec128"}, + {name: "VPMAXUQMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec256"}, + {name: "VPMAXUQMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec512"}, + {name: "VPMAXUW128", argLength: 2, reg: v21, asm: "VPMAXUW", commutative: true, typ: "Vec128"}, + {name: "VPMAXUW256", argLength: 2, reg: v21, asm: "VPMAXUW", commutative: true, typ: "Vec256"}, + {name: "VPMAXUW512", argLength: 2, reg: w21, asm: "VPMAXUW", commutative: true, typ: "Vec512"}, + {name: "VPMAXUWMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec128"}, + {name: "VPMAXUWMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec256"}, + {name: "VPMAXUWMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec512"}, + {name: "VPMINSB128", argLength: 2, reg: v21, asm: "VPMINSB", commutative: true, typ: "Vec128"}, + {name: "VPMINSB256", argLength: 2, reg: v21, asm: "VPMINSB", commutative: true, typ: "Vec256"}, + {name: "VPMINSB512", argLength: 2, reg: w21, asm: "VPMINSB", commutative: true, typ: "Vec512"}, + {name: "VPMINSBMasked128", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec128"}, + {name: "VPMINSBMasked256", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec256"}, + {name: "VPMINSBMasked512", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec512"}, + {name: "VPMINSD128", argLength: 2, reg: v21, asm: "VPMINSD", commutative: true, typ: "Vec128"}, + {name: "VPMINSD256", argLength: 2, reg: v21, asm: "VPMINSD", commutative: true, typ: "Vec256"}, + {name: "VPMINSD512", argLength: 2, reg: w21, asm: "VPMINSD", commutative: true, typ: "Vec512"}, + {name: "VPMINSDMasked128", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec128"}, + {name: "VPMINSDMasked256", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec256"}, + {name: "VPMINSDMasked512", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec512"}, + {name: "VPMINSQ128", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec128"}, + {name: "VPMINSQ256", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec256"}, + {name: "VPMINSQ512", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec512"}, + {name: "VPMINSQMasked128", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec128"}, + {name: "VPMINSQMasked256", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec256"}, + {name: "VPMINSQMasked512", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec512"}, + {name: "VPMINSW128", argLength: 2, reg: v21, asm: "VPMINSW", commutative: true, typ: "Vec128"}, + {name: "VPMINSW256", argLength: 2, reg: v21, asm: "VPMINSW", commutative: true, typ: "Vec256"}, + {name: "VPMINSW512", argLength: 2, reg: w21, asm: "VPMINSW", commutative: true, typ: "Vec512"}, + {name: "VPMINSWMasked128", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec128"}, + {name: "VPMINSWMasked256", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec256"}, + {name: "VPMINSWMasked512", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec512"}, + {name: "VPMINUB128", argLength: 2, reg: v21, asm: "VPMINUB", commutative: true, typ: "Vec128"}, + {name: "VPMINUB256", argLength: 2, reg: v21, asm: "VPMINUB", commutative: true, typ: "Vec256"}, + {name: "VPMINUB512", argLength: 2, reg: w21, asm: "VPMINUB", commutative: true, typ: "Vec512"}, + {name: "VPMINUBMasked128", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec128"}, + {name: "VPMINUBMasked256", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec256"}, + {name: "VPMINUBMasked512", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec512"}, + {name: "VPMINUD128", argLength: 2, reg: v21, asm: "VPMINUD", commutative: true, typ: "Vec128"}, + {name: "VPMINUD256", argLength: 2, reg: v21, asm: "VPMINUD", commutative: true, typ: "Vec256"}, + {name: "VPMINUD512", argLength: 2, reg: w21, asm: "VPMINUD", commutative: true, typ: "Vec512"}, + {name: "VPMINUDMasked128", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec128"}, + {name: "VPMINUDMasked256", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec256"}, + {name: "VPMINUDMasked512", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec512"}, + {name: "VPMINUQ128", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec128"}, + {name: "VPMINUQ256", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec256"}, + {name: "VPMINUQ512", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec512"}, + {name: "VPMINUQMasked128", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec128"}, + {name: "VPMINUQMasked256", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec256"}, + {name: "VPMINUQMasked512", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec512"}, + {name: "VPMINUW128", argLength: 2, reg: v21, asm: "VPMINUW", commutative: true, typ: "Vec128"}, + {name: "VPMINUW256", argLength: 2, reg: v21, asm: "VPMINUW", commutative: true, typ: "Vec256"}, + {name: "VPMINUW512", argLength: 2, reg: w21, asm: "VPMINUW", commutative: true, typ: "Vec512"}, + {name: "VPMINUWMasked128", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec128"}, + {name: "VPMINUWMasked256", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec256"}, + {name: "VPMINUWMasked512", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec512"}, + {name: "VPMOVDB128_128", argLength: 1, reg: w11, asm: "VPMOVDB", typ: "Vec128"}, + {name: "VPMOVDB128_256", argLength: 1, reg: w11, asm: "VPMOVDB", typ: "Vec128"}, + {name: "VPMOVDB128_512", argLength: 1, reg: w11, asm: "VPMOVDB", typ: "Vec128"}, + {name: "VPMOVDBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVDB", typ: "Vec128"}, + {name: "VPMOVDBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVDB", typ: "Vec128"}, + {name: "VPMOVDBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVDB", typ: "Vec128"}, + {name: "VPMOVDW128_128", argLength: 1, reg: w11, asm: "VPMOVDW", typ: "Vec128"}, + {name: "VPMOVDW128_256", argLength: 1, reg: w11, asm: "VPMOVDW", typ: "Vec128"}, + {name: "VPMOVDW256", argLength: 1, reg: w11, asm: "VPMOVDW", typ: "Vec256"}, + {name: "VPMOVDWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVDW", typ: "Vec128"}, + {name: "VPMOVDWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVDW", typ: "Vec128"}, + {name: "VPMOVDWMasked256", argLength: 2, reg: wkw, asm: "VPMOVDW", typ: "Vec256"}, + {name: "VPMOVQB128_128", argLength: 1, reg: w11, asm: "VPMOVQB", typ: "Vec128"}, + {name: "VPMOVQB128_256", argLength: 1, reg: w11, asm: "VPMOVQB", typ: "Vec128"}, + {name: "VPMOVQB128_512", argLength: 1, reg: w11, asm: "VPMOVQB", typ: "Vec128"}, + {name: "VPMOVQBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVQB", typ: "Vec128"}, + {name: "VPMOVQBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVQB", typ: "Vec128"}, + {name: "VPMOVQBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVQB", typ: "Vec128"}, + {name: "VPMOVQD128_128", argLength: 1, reg: w11, asm: "VPMOVQD", typ: "Vec128"}, + {name: "VPMOVQD128_256", argLength: 1, reg: w11, asm: "VPMOVQD", typ: "Vec128"}, + {name: "VPMOVQD256", argLength: 1, reg: w11, asm: "VPMOVQD", typ: "Vec256"}, + {name: "VPMOVQDMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVQD", typ: "Vec128"}, + {name: "VPMOVQDMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVQD", typ: "Vec128"}, + {name: "VPMOVQDMasked256", argLength: 2, reg: wkw, asm: "VPMOVQD", typ: "Vec256"}, + {name: "VPMOVQW128_128", argLength: 1, reg: w11, asm: "VPMOVQW", typ: "Vec128"}, + {name: "VPMOVQW128_256", argLength: 1, reg: w11, asm: "VPMOVQW", typ: "Vec128"}, + {name: "VPMOVQW128_512", argLength: 1, reg: w11, asm: "VPMOVQW", typ: "Vec128"}, + {name: "VPMOVQWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVQW", typ: "Vec128"}, + {name: "VPMOVQWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVQW", typ: "Vec128"}, + {name: "VPMOVQWMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVQW", typ: "Vec128"}, + {name: "VPMOVSDB128_128", argLength: 1, reg: w11, asm: "VPMOVSDB", typ: "Vec128"}, + {name: "VPMOVSDB128_256", argLength: 1, reg: w11, asm: "VPMOVSDB", typ: "Vec128"}, + {name: "VPMOVSDB128_512", argLength: 1, reg: w11, asm: "VPMOVSDB", typ: "Vec128"}, + {name: "VPMOVSDBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSDB", typ: "Vec128"}, + {name: "VPMOVSDBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSDB", typ: "Vec128"}, + {name: "VPMOVSDBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVSDB", typ: "Vec128"}, + {name: "VPMOVSDW128_128", argLength: 1, reg: w11, asm: "VPMOVSDW", typ: "Vec128"}, + {name: "VPMOVSDW128_256", argLength: 1, reg: w11, asm: "VPMOVSDW", typ: "Vec128"}, + {name: "VPMOVSDW256", argLength: 1, reg: w11, asm: "VPMOVSDW", typ: "Vec256"}, + {name: "VPMOVSDWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSDW", typ: "Vec128"}, + {name: "VPMOVSDWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSDW", typ: "Vec128"}, + {name: "VPMOVSDWMasked256", argLength: 2, reg: wkw, asm: "VPMOVSDW", typ: "Vec256"}, + {name: "VPMOVSQB128_128", argLength: 1, reg: w11, asm: "VPMOVSQB", typ: "Vec128"}, + {name: "VPMOVSQB128_256", argLength: 1, reg: w11, asm: "VPMOVSQB", typ: "Vec128"}, + {name: "VPMOVSQB128_512", argLength: 1, reg: w11, asm: "VPMOVSQB", typ: "Vec128"}, + {name: "VPMOVSQBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSQB", typ: "Vec128"}, + {name: "VPMOVSQBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSQB", typ: "Vec128"}, + {name: "VPMOVSQBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVSQB", typ: "Vec128"}, + {name: "VPMOVSQD128_128", argLength: 1, reg: w11, asm: "VPMOVSQD", typ: "Vec128"}, + {name: "VPMOVSQD128_256", argLength: 1, reg: w11, asm: "VPMOVSQD", typ: "Vec128"}, + {name: "VPMOVSQD256", argLength: 1, reg: w11, asm: "VPMOVSQD", typ: "Vec256"}, + {name: "VPMOVSQDMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSQD", typ: "Vec128"}, + {name: "VPMOVSQDMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSQD", typ: "Vec128"}, + {name: "VPMOVSQDMasked256", argLength: 2, reg: wkw, asm: "VPMOVSQD", typ: "Vec256"}, + {name: "VPMOVSQW128_128", argLength: 1, reg: w11, asm: "VPMOVSQW", typ: "Vec128"}, + {name: "VPMOVSQW128_256", argLength: 1, reg: w11, asm: "VPMOVSQW", typ: "Vec128"}, + {name: "VPMOVSQW128_512", argLength: 1, reg: w11, asm: "VPMOVSQW", typ: "Vec128"}, + {name: "VPMOVSQWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSQW", typ: "Vec128"}, + {name: "VPMOVSQWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSQW", typ: "Vec128"}, + {name: "VPMOVSQWMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVSQW", typ: "Vec128"}, + {name: "VPMOVSWB128_128", argLength: 1, reg: w11, asm: "VPMOVSWB", typ: "Vec128"}, + {name: "VPMOVSWB128_256", argLength: 1, reg: w11, asm: "VPMOVSWB", typ: "Vec128"}, + {name: "VPMOVSWB256", argLength: 1, reg: w11, asm: "VPMOVSWB", typ: "Vec256"}, + {name: "VPMOVSWBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSWB", typ: "Vec128"}, + {name: "VPMOVSWBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSWB", typ: "Vec128"}, + {name: "VPMOVSWBMasked256", argLength: 2, reg: wkw, asm: "VPMOVSWB", typ: "Vec256"}, + {name: "VPMOVSXBD128", argLength: 1, reg: v11, asm: "VPMOVSXBD", typ: "Vec128"}, + {name: "VPMOVSXBD256", argLength: 1, reg: v11, asm: "VPMOVSXBD", typ: "Vec256"}, + {name: "VPMOVSXBD512", argLength: 1, reg: w11, asm: "VPMOVSXBD", typ: "Vec512"}, + {name: "VPMOVSXBDMasked128", argLength: 2, reg: wkw, asm: "VPMOVSXBD", typ: "Vec128"}, + {name: "VPMOVSXBDMasked256", argLength: 2, reg: wkw, asm: "VPMOVSXBD", typ: "Vec256"}, + {name: "VPMOVSXBDMasked512", argLength: 2, reg: wkw, asm: "VPMOVSXBD", typ: "Vec512"}, + {name: "VPMOVSXBQ128", argLength: 1, reg: v11, asm: "VPMOVSXBQ", typ: "Vec128"}, + {name: "VPMOVSXBQ256", argLength: 1, reg: v11, asm: "VPMOVSXBQ", typ: "Vec256"}, + {name: "VPMOVSXBQ512", argLength: 1, reg: w11, asm: "VPMOVSXBQ", typ: "Vec512"}, + {name: "VPMOVSXBQMasked128", argLength: 2, reg: wkw, asm: "VPMOVSXBQ", typ: "Vec128"}, + {name: "VPMOVSXBQMasked256", argLength: 2, reg: wkw, asm: "VPMOVSXBQ", typ: "Vec256"}, + {name: "VPMOVSXBQMasked512", argLength: 2, reg: wkw, asm: "VPMOVSXBQ", typ: "Vec512"}, + {name: "VPMOVSXBW128", argLength: 1, reg: v11, asm: "VPMOVSXBW", typ: "Vec128"}, + {name: "VPMOVSXBW256", argLength: 1, reg: v11, asm: "VPMOVSXBW", typ: "Vec256"}, + {name: "VPMOVSXBW512", argLength: 1, reg: w11, asm: "VPMOVSXBW", typ: "Vec512"}, + {name: "VPMOVSXBWMasked128", argLength: 2, reg: wkw, asm: "VPMOVSXBW", typ: "Vec128"}, + {name: "VPMOVSXBWMasked256", argLength: 2, reg: wkw, asm: "VPMOVSXBW", typ: "Vec256"}, + {name: "VPMOVSXBWMasked512", argLength: 2, reg: wkw, asm: "VPMOVSXBW", typ: "Vec512"}, + {name: "VPMOVSXDQ128", argLength: 1, reg: v11, asm: "VPMOVSXDQ", typ: "Vec128"}, + {name: "VPMOVSXDQ256", argLength: 1, reg: v11, asm: "VPMOVSXDQ", typ: "Vec256"}, + {name: "VPMOVSXDQ512", argLength: 1, reg: w11, asm: "VPMOVSXDQ", typ: "Vec512"}, + {name: "VPMOVSXDQMasked128", argLength: 2, reg: wkw, asm: "VPMOVSXDQ", typ: "Vec128"}, + {name: "VPMOVSXDQMasked256", argLength: 2, reg: wkw, asm: "VPMOVSXDQ", typ: "Vec256"}, + {name: "VPMOVSXDQMasked512", argLength: 2, reg: wkw, asm: "VPMOVSXDQ", typ: "Vec512"}, + {name: "VPMOVSXWD128", argLength: 1, reg: v11, asm: "VPMOVSXWD", typ: "Vec128"}, + {name: "VPMOVSXWD256", argLength: 1, reg: v11, asm: "VPMOVSXWD", typ: "Vec256"}, + {name: "VPMOVSXWD512", argLength: 1, reg: w11, asm: "VPMOVSXWD", typ: "Vec512"}, + {name: "VPMOVSXWDMasked128", argLength: 2, reg: wkw, asm: "VPMOVSXWD", typ: "Vec128"}, + {name: "VPMOVSXWDMasked256", argLength: 2, reg: wkw, asm: "VPMOVSXWD", typ: "Vec256"}, + {name: "VPMOVSXWDMasked512", argLength: 2, reg: wkw, asm: "VPMOVSXWD", typ: "Vec512"}, + {name: "VPMOVSXWQ128", argLength: 1, reg: v11, asm: "VPMOVSXWQ", typ: "Vec128"}, + {name: "VPMOVSXWQ256", argLength: 1, reg: v11, asm: "VPMOVSXWQ", typ: "Vec256"}, + {name: "VPMOVSXWQ512", argLength: 1, reg: w11, asm: "VPMOVSXWQ", typ: "Vec512"}, + {name: "VPMOVSXWQMasked128", argLength: 2, reg: wkw, asm: "VPMOVSXWQ", typ: "Vec128"}, + {name: "VPMOVSXWQMasked256", argLength: 2, reg: wkw, asm: "VPMOVSXWQ", typ: "Vec256"}, + {name: "VPMOVSXWQMasked512", argLength: 2, reg: wkw, asm: "VPMOVSXWQ", typ: "Vec512"}, + {name: "VPMOVUSDB128_128", argLength: 1, reg: w11, asm: "VPMOVUSDB", typ: "Vec128"}, + {name: "VPMOVUSDB128_256", argLength: 1, reg: w11, asm: "VPMOVUSDB", typ: "Vec128"}, + {name: "VPMOVUSDB128_512", argLength: 1, reg: w11, asm: "VPMOVUSDB", typ: "Vec128"}, + {name: "VPMOVUSDBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSDB", typ: "Vec128"}, + {name: "VPMOVUSDBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSDB", typ: "Vec128"}, + {name: "VPMOVUSDBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVUSDB", typ: "Vec128"}, + {name: "VPMOVUSDW128_128", argLength: 1, reg: w11, asm: "VPMOVUSDW", typ: "Vec128"}, + {name: "VPMOVUSDW128_256", argLength: 1, reg: w11, asm: "VPMOVUSDW", typ: "Vec128"}, + {name: "VPMOVUSDW256", argLength: 1, reg: w11, asm: "VPMOVUSDW", typ: "Vec256"}, + {name: "VPMOVUSDWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSDW", typ: "Vec128"}, + {name: "VPMOVUSDWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSDW", typ: "Vec128"}, + {name: "VPMOVUSDWMasked256", argLength: 2, reg: wkw, asm: "VPMOVUSDW", typ: "Vec256"}, + {name: "VPMOVUSQB128_128", argLength: 1, reg: w11, asm: "VPMOVUSQB", typ: "Vec128"}, + {name: "VPMOVUSQB128_256", argLength: 1, reg: w11, asm: "VPMOVUSQB", typ: "Vec128"}, + {name: "VPMOVUSQB128_512", argLength: 1, reg: w11, asm: "VPMOVUSQB", typ: "Vec128"}, + {name: "VPMOVUSQBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSQB", typ: "Vec128"}, + {name: "VPMOVUSQBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSQB", typ: "Vec128"}, + {name: "VPMOVUSQBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVUSQB", typ: "Vec128"}, + {name: "VPMOVUSQD128_128", argLength: 1, reg: w11, asm: "VPMOVUSQD", typ: "Vec128"}, + {name: "VPMOVUSQD128_256", argLength: 1, reg: w11, asm: "VPMOVUSQD", typ: "Vec128"}, + {name: "VPMOVUSQD256", argLength: 1, reg: w11, asm: "VPMOVUSQD", typ: "Vec256"}, + {name: "VPMOVUSQDMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSQD", typ: "Vec128"}, + {name: "VPMOVUSQDMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSQD", typ: "Vec128"}, + {name: "VPMOVUSQDMasked256", argLength: 2, reg: wkw, asm: "VPMOVUSQD", typ: "Vec256"}, + {name: "VPMOVUSQW128_128", argLength: 1, reg: w11, asm: "VPMOVUSQW", typ: "Vec128"}, + {name: "VPMOVUSQW128_256", argLength: 1, reg: w11, asm: "VPMOVUSQW", typ: "Vec128"}, + {name: "VPMOVUSQW128_512", argLength: 1, reg: w11, asm: "VPMOVUSQW", typ: "Vec128"}, + {name: "VPMOVUSQWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSQW", typ: "Vec128"}, + {name: "VPMOVUSQWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSQW", typ: "Vec128"}, + {name: "VPMOVUSQWMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVUSQW", typ: "Vec128"}, + {name: "VPMOVUSWB128_128", argLength: 1, reg: w11, asm: "VPMOVUSWB", typ: "Vec128"}, + {name: "VPMOVUSWB128_256", argLength: 1, reg: w11, asm: "VPMOVUSWB", typ: "Vec128"}, + {name: "VPMOVUSWB256", argLength: 1, reg: w11, asm: "VPMOVUSWB", typ: "Vec256"}, + {name: "VPMOVUSWBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSWB", typ: "Vec128"}, + {name: "VPMOVUSWBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSWB", typ: "Vec128"}, + {name: "VPMOVUSWBMasked256", argLength: 2, reg: wkw, asm: "VPMOVUSWB", typ: "Vec256"}, + {name: "VPMOVWB128_128", argLength: 1, reg: w11, asm: "VPMOVWB", typ: "Vec128"}, + {name: "VPMOVWB128_256", argLength: 1, reg: w11, asm: "VPMOVWB", typ: "Vec128"}, + {name: "VPMOVWB256", argLength: 1, reg: w11, asm: "VPMOVWB", typ: "Vec256"}, + {name: "VPMOVWBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVWB", typ: "Vec128"}, + {name: "VPMOVWBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVWB", typ: "Vec128"}, + {name: "VPMOVWBMasked256", argLength: 2, reg: wkw, asm: "VPMOVWB", typ: "Vec256"}, + {name: "VPMOVZXBD128", argLength: 1, reg: v11, asm: "VPMOVZXBD", typ: "Vec128"}, + {name: "VPMOVZXBD256", argLength: 1, reg: v11, asm: "VPMOVZXBD", typ: "Vec256"}, + {name: "VPMOVZXBD512", argLength: 1, reg: w11, asm: "VPMOVZXBD", typ: "Vec512"}, + {name: "VPMOVZXBDMasked128", argLength: 2, reg: wkw, asm: "VPMOVZXBD", typ: "Vec128"}, + {name: "VPMOVZXBDMasked256", argLength: 2, reg: wkw, asm: "VPMOVZXBD", typ: "Vec256"}, + {name: "VPMOVZXBDMasked512", argLength: 2, reg: wkw, asm: "VPMOVZXBD", typ: "Vec512"}, + {name: "VPMOVZXBQ128", argLength: 1, reg: v11, asm: "VPMOVZXBQ", typ: "Vec128"}, + {name: "VPMOVZXBQ256", argLength: 1, reg: v11, asm: "VPMOVZXBQ", typ: "Vec256"}, + {name: "VPMOVZXBQ512", argLength: 1, reg: w11, asm: "VPMOVZXBQ", typ: "Vec512"}, + {name: "VPMOVZXBQMasked128", argLength: 2, reg: wkw, asm: "VPMOVZXBQ", typ: "Vec128"}, + {name: "VPMOVZXBQMasked256", argLength: 2, reg: wkw, asm: "VPMOVZXBQ", typ: "Vec256"}, + {name: "VPMOVZXBQMasked512", argLength: 2, reg: wkw, asm: "VPMOVZXBQ", typ: "Vec512"}, + {name: "VPMOVZXBW128", argLength: 1, reg: v11, asm: "VPMOVZXBW", typ: "Vec128"}, + {name: "VPMOVZXBW256", argLength: 1, reg: v11, asm: "VPMOVZXBW", typ: "Vec256"}, + {name: "VPMOVZXBW512", argLength: 1, reg: w11, asm: "VPMOVZXBW", typ: "Vec512"}, + {name: "VPMOVZXBWMasked128", argLength: 2, reg: wkw, asm: "VPMOVZXBW", typ: "Vec128"}, + {name: "VPMOVZXBWMasked256", argLength: 2, reg: wkw, asm: "VPMOVZXBW", typ: "Vec256"}, + {name: "VPMOVZXBWMasked512", argLength: 2, reg: wkw, asm: "VPMOVZXBW", typ: "Vec512"}, + {name: "VPMOVZXDQ128", argLength: 1, reg: v11, asm: "VPMOVZXDQ", typ: "Vec128"}, + {name: "VPMOVZXDQ256", argLength: 1, reg: v11, asm: "VPMOVZXDQ", typ: "Vec256"}, + {name: "VPMOVZXDQ512", argLength: 1, reg: w11, asm: "VPMOVZXDQ", typ: "Vec512"}, + {name: "VPMOVZXDQMasked128", argLength: 2, reg: wkw, asm: "VPMOVZXDQ", typ: "Vec128"}, + {name: "VPMOVZXDQMasked256", argLength: 2, reg: wkw, asm: "VPMOVZXDQ", typ: "Vec256"}, + {name: "VPMOVZXDQMasked512", argLength: 2, reg: wkw, asm: "VPMOVZXDQ", typ: "Vec512"}, + {name: "VPMOVZXWD128", argLength: 1, reg: v11, asm: "VPMOVZXWD", typ: "Vec128"}, + {name: "VPMOVZXWD256", argLength: 1, reg: v11, asm: "VPMOVZXWD", typ: "Vec256"}, + {name: "VPMOVZXWD512", argLength: 1, reg: w11, asm: "VPMOVZXWD", typ: "Vec512"}, + {name: "VPMOVZXWDMasked128", argLength: 2, reg: wkw, asm: "VPMOVZXWD", typ: "Vec128"}, + {name: "VPMOVZXWDMasked256", argLength: 2, reg: wkw, asm: "VPMOVZXWD", typ: "Vec256"}, + {name: "VPMOVZXWDMasked512", argLength: 2, reg: wkw, asm: "VPMOVZXWD", typ: "Vec512"}, + {name: "VPMOVZXWQ128", argLength: 1, reg: v11, asm: "VPMOVZXWQ", typ: "Vec128"}, + {name: "VPMOVZXWQ256", argLength: 1, reg: v11, asm: "VPMOVZXWQ", typ: "Vec256"}, + {name: "VPMOVZXWQ512", argLength: 1, reg: w11, asm: "VPMOVZXWQ", typ: "Vec512"}, + {name: "VPMOVZXWQMasked128", argLength: 2, reg: wkw, asm: "VPMOVZXWQ", typ: "Vec128"}, + {name: "VPMOVZXWQMasked256", argLength: 2, reg: wkw, asm: "VPMOVZXWQ", typ: "Vec256"}, + {name: "VPMOVZXWQMasked512", argLength: 2, reg: wkw, asm: "VPMOVZXWQ", typ: "Vec512"}, + {name: "VPMULDQ128", argLength: 2, reg: v21, asm: "VPMULDQ", commutative: true, typ: "Vec128"}, + {name: "VPMULDQ256", argLength: 2, reg: v21, asm: "VPMULDQ", commutative: true, typ: "Vec256"}, + {name: "VPMULHUW128", argLength: 2, reg: v21, asm: "VPMULHUW", commutative: true, typ: "Vec128"}, + {name: "VPMULHUW256", argLength: 2, reg: v21, asm: "VPMULHUW", commutative: true, typ: "Vec256"}, + {name: "VPMULHUW512", argLength: 2, reg: w21, asm: "VPMULHUW", commutative: true, typ: "Vec512"}, + {name: "VPMULHUWMasked128", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec128"}, + {name: "VPMULHUWMasked256", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec256"}, + {name: "VPMULHUWMasked512", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec512"}, + {name: "VPMULHW128", argLength: 2, reg: v21, asm: "VPMULHW", commutative: true, typ: "Vec128"}, + {name: "VPMULHW256", argLength: 2, reg: v21, asm: "VPMULHW", commutative: true, typ: "Vec256"}, + {name: "VPMULHW512", argLength: 2, reg: w21, asm: "VPMULHW", commutative: true, typ: "Vec512"}, + {name: "VPMULHWMasked128", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec128"}, + {name: "VPMULHWMasked256", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec256"}, + {name: "VPMULHWMasked512", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec512"}, + {name: "VPMULLD128", argLength: 2, reg: v21, asm: "VPMULLD", commutative: true, typ: "Vec128"}, + {name: "VPMULLD256", argLength: 2, reg: v21, asm: "VPMULLD", commutative: true, typ: "Vec256"}, + {name: "VPMULLD512", argLength: 2, reg: w21, asm: "VPMULLD", commutative: true, typ: "Vec512"}, + {name: "VPMULLDMasked128", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec128"}, + {name: "VPMULLDMasked256", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec256"}, + {name: "VPMULLDMasked512", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec512"}, + {name: "VPMULLQ128", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec128"}, + {name: "VPMULLQ256", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec256"}, + {name: "VPMULLQ512", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec512"}, + {name: "VPMULLQMasked128", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec128"}, + {name: "VPMULLQMasked256", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec256"}, + {name: "VPMULLQMasked512", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec512"}, + {name: "VPMULLW128", argLength: 2, reg: v21, asm: "VPMULLW", commutative: true, typ: "Vec128"}, + {name: "VPMULLW256", argLength: 2, reg: v21, asm: "VPMULLW", commutative: true, typ: "Vec256"}, + {name: "VPMULLW512", argLength: 2, reg: w21, asm: "VPMULLW", commutative: true, typ: "Vec512"}, + {name: "VPMULLWMasked128", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec128"}, + {name: "VPMULLWMasked256", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec256"}, + {name: "VPMULLWMasked512", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec512"}, + {name: "VPMULUDQ128", argLength: 2, reg: v21, asm: "VPMULUDQ", commutative: true, typ: "Vec128"}, + {name: "VPMULUDQ256", argLength: 2, reg: v21, asm: "VPMULUDQ", commutative: true, typ: "Vec256"}, + {name: "VPOPCNTB128", argLength: 1, reg: w11, asm: "VPOPCNTB", typ: "Vec128"}, + {name: "VPOPCNTB256", argLength: 1, reg: w11, asm: "VPOPCNTB", typ: "Vec256"}, + {name: "VPOPCNTB512", argLength: 1, reg: w11, asm: "VPOPCNTB", typ: "Vec512"}, + {name: "VPOPCNTBMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTB", typ: "Vec128"}, + {name: "VPOPCNTBMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTB", typ: "Vec256"}, + {name: "VPOPCNTBMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTB", typ: "Vec512"}, + {name: "VPOPCNTD128", argLength: 1, reg: w11, asm: "VPOPCNTD", typ: "Vec128"}, + {name: "VPOPCNTD256", argLength: 1, reg: w11, asm: "VPOPCNTD", typ: "Vec256"}, + {name: "VPOPCNTD512", argLength: 1, reg: w11, asm: "VPOPCNTD", typ: "Vec512"}, + {name: "VPOPCNTDMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTD", typ: "Vec128"}, + {name: "VPOPCNTDMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTD", typ: "Vec256"}, + {name: "VPOPCNTDMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTD", typ: "Vec512"}, + {name: "VPOPCNTQ128", argLength: 1, reg: w11, asm: "VPOPCNTQ", typ: "Vec128"}, + {name: "VPOPCNTQ256", argLength: 1, reg: w11, asm: "VPOPCNTQ", typ: "Vec256"}, + {name: "VPOPCNTQ512", argLength: 1, reg: w11, asm: "VPOPCNTQ", typ: "Vec512"}, + {name: "VPOPCNTQMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTQ", typ: "Vec128"}, + {name: "VPOPCNTQMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTQ", typ: "Vec256"}, + {name: "VPOPCNTQMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTQ", typ: "Vec512"}, + {name: "VPOPCNTW128", argLength: 1, reg: w11, asm: "VPOPCNTW", typ: "Vec128"}, + {name: "VPOPCNTW256", argLength: 1, reg: w11, asm: "VPOPCNTW", typ: "Vec256"}, + {name: "VPOPCNTW512", argLength: 1, reg: w11, asm: "VPOPCNTW", typ: "Vec512"}, + {name: "VPOPCNTWMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTW", typ: "Vec128"}, + {name: "VPOPCNTWMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTW", typ: "Vec256"}, + {name: "VPOPCNTWMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTW", typ: "Vec512"}, + {name: "VPOR128", argLength: 2, reg: v21, asm: "VPOR", commutative: true, typ: "Vec128"}, + {name: "VPOR256", argLength: 2, reg: v21, asm: "VPOR", commutative: true, typ: "Vec256"}, + {name: "VPORD512", argLength: 2, reg: w21, asm: "VPORD", commutative: true, typ: "Vec512"}, + {name: "VPORDMasked128", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec128"}, + {name: "VPORDMasked256", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec256"}, + {name: "VPORDMasked512", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec512"}, + {name: "VPORQ512", argLength: 2, reg: w21, asm: "VPORQ", commutative: true, typ: "Vec512"}, + {name: "VPORQMasked128", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec128"}, + {name: "VPORQMasked256", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec256"}, + {name: "VPORQMasked512", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec512"}, + {name: "VPROLVD128", argLength: 2, reg: w21, asm: "VPROLVD", typ: "Vec128"}, + {name: "VPROLVD256", argLength: 2, reg: w21, asm: "VPROLVD", typ: "Vec256"}, + {name: "VPROLVD512", argLength: 2, reg: w21, asm: "VPROLVD", typ: "Vec512"}, + {name: "VPROLVDMasked128", argLength: 3, reg: w2kw, asm: "VPROLVD", typ: "Vec128"}, + {name: "VPROLVDMasked256", argLength: 3, reg: w2kw, asm: "VPROLVD", typ: "Vec256"}, + {name: "VPROLVDMasked512", argLength: 3, reg: w2kw, asm: "VPROLVD", typ: "Vec512"}, + {name: "VPROLVQ128", argLength: 2, reg: w21, asm: "VPROLVQ", typ: "Vec128"}, + {name: "VPROLVQ256", argLength: 2, reg: w21, asm: "VPROLVQ", typ: "Vec256"}, + {name: "VPROLVQ512", argLength: 2, reg: w21, asm: "VPROLVQ", typ: "Vec512"}, + {name: "VPROLVQMasked128", argLength: 3, reg: w2kw, asm: "VPROLVQ", typ: "Vec128"}, + {name: "VPROLVQMasked256", argLength: 3, reg: w2kw, asm: "VPROLVQ", typ: "Vec256"}, + {name: "VPROLVQMasked512", argLength: 3, reg: w2kw, asm: "VPROLVQ", typ: "Vec512"}, + {name: "VPRORVD128", argLength: 2, reg: w21, asm: "VPRORVD", typ: "Vec128"}, + {name: "VPRORVD256", argLength: 2, reg: w21, asm: "VPRORVD", typ: "Vec256"}, + {name: "VPRORVD512", argLength: 2, reg: w21, asm: "VPRORVD", typ: "Vec512"}, + {name: "VPRORVDMasked128", argLength: 3, reg: w2kw, asm: "VPRORVD", typ: "Vec128"}, + {name: "VPRORVDMasked256", argLength: 3, reg: w2kw, asm: "VPRORVD", typ: "Vec256"}, + {name: "VPRORVDMasked512", argLength: 3, reg: w2kw, asm: "VPRORVD", typ: "Vec512"}, + {name: "VPRORVQ128", argLength: 2, reg: w21, asm: "VPRORVQ", typ: "Vec128"}, + {name: "VPRORVQ256", argLength: 2, reg: w21, asm: "VPRORVQ", typ: "Vec256"}, + {name: "VPRORVQ512", argLength: 2, reg: w21, asm: "VPRORVQ", typ: "Vec512"}, + {name: "VPRORVQMasked128", argLength: 3, reg: w2kw, asm: "VPRORVQ", typ: "Vec128"}, + {name: "VPRORVQMasked256", argLength: 3, reg: w2kw, asm: "VPRORVQ", typ: "Vec256"}, + {name: "VPRORVQMasked512", argLength: 3, reg: w2kw, asm: "VPRORVQ", typ: "Vec512"}, + {name: "VPSADBW128", argLength: 2, reg: v21, asm: "VPSADBW", typ: "Vec128"}, + {name: "VPSADBW256", argLength: 2, reg: v21, asm: "VPSADBW", typ: "Vec256"}, + {name: "VPSADBW512", argLength: 2, reg: w21, asm: "VPSADBW", typ: "Vec512"}, + {name: "VPSHLDVD128", argLength: 3, reg: w31, asm: "VPSHLDVD", typ: "Vec128", resultInArg0: true}, + {name: "VPSHLDVD256", argLength: 3, reg: w31, asm: "VPSHLDVD", typ: "Vec256", resultInArg0: true}, + {name: "VPSHLDVD512", argLength: 3, reg: w31, asm: "VPSHLDVD", typ: "Vec512", resultInArg0: true}, + {name: "VPSHLDVDMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVD", typ: "Vec128", resultInArg0: true}, + {name: "VPSHLDVDMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVD", typ: "Vec256", resultInArg0: true}, + {name: "VPSHLDVDMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVD", typ: "Vec512", resultInArg0: true}, + {name: "VPSHLDVQ128", argLength: 3, reg: w31, asm: "VPSHLDVQ", typ: "Vec128", resultInArg0: true}, + {name: "VPSHLDVQ256", argLength: 3, reg: w31, asm: "VPSHLDVQ", typ: "Vec256", resultInArg0: true}, + {name: "VPSHLDVQ512", argLength: 3, reg: w31, asm: "VPSHLDVQ", typ: "Vec512", resultInArg0: true}, + {name: "VPSHLDVQMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", typ: "Vec128", resultInArg0: true}, + {name: "VPSHLDVQMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", typ: "Vec256", resultInArg0: true}, + {name: "VPSHLDVQMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", typ: "Vec512", resultInArg0: true}, + {name: "VPSHLDVW128", argLength: 3, reg: w31, asm: "VPSHLDVW", typ: "Vec128", resultInArg0: true}, + {name: "VPSHLDVW256", argLength: 3, reg: w31, asm: "VPSHLDVW", typ: "Vec256", resultInArg0: true}, + {name: "VPSHLDVW512", argLength: 3, reg: w31, asm: "VPSHLDVW", typ: "Vec512", resultInArg0: true}, + {name: "VPSHLDVWMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVW", typ: "Vec128", resultInArg0: true}, + {name: "VPSHLDVWMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVW", typ: "Vec256", resultInArg0: true}, + {name: "VPSHLDVWMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVW", typ: "Vec512", resultInArg0: true}, + {name: "VPSHRDVD128", argLength: 3, reg: w31, asm: "VPSHRDVD", typ: "Vec128", resultInArg0: true}, + {name: "VPSHRDVD256", argLength: 3, reg: w31, asm: "VPSHRDVD", typ: "Vec256", resultInArg0: true}, + {name: "VPSHRDVD512", argLength: 3, reg: w31, asm: "VPSHRDVD", typ: "Vec512", resultInArg0: true}, + {name: "VPSHRDVDMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVD", typ: "Vec128", resultInArg0: true}, + {name: "VPSHRDVDMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVD", typ: "Vec256", resultInArg0: true}, + {name: "VPSHRDVDMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVD", typ: "Vec512", resultInArg0: true}, + {name: "VPSHRDVQ128", argLength: 3, reg: w31, asm: "VPSHRDVQ", typ: "Vec128", resultInArg0: true}, + {name: "VPSHRDVQ256", argLength: 3, reg: w31, asm: "VPSHRDVQ", typ: "Vec256", resultInArg0: true}, + {name: "VPSHRDVQ512", argLength: 3, reg: w31, asm: "VPSHRDVQ", typ: "Vec512", resultInArg0: true}, + {name: "VPSHRDVQMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", typ: "Vec128", resultInArg0: true}, + {name: "VPSHRDVQMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", typ: "Vec256", resultInArg0: true}, + {name: "VPSHRDVQMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", typ: "Vec512", resultInArg0: true}, + {name: "VPSHRDVW128", argLength: 3, reg: w31, asm: "VPSHRDVW", typ: "Vec128", resultInArg0: true}, + {name: "VPSHRDVW256", argLength: 3, reg: w31, asm: "VPSHRDVW", typ: "Vec256", resultInArg0: true}, + {name: "VPSHRDVW512", argLength: 3, reg: w31, asm: "VPSHRDVW", typ: "Vec512", resultInArg0: true}, + {name: "VPSHRDVWMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVW", typ: "Vec128", resultInArg0: true}, + {name: "VPSHRDVWMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVW", typ: "Vec256", resultInArg0: true}, + {name: "VPSHRDVWMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVW", typ: "Vec512", resultInArg0: true}, + {name: "VPSHUFB128", argLength: 2, reg: v21, asm: "VPSHUFB", typ: "Vec128"}, + {name: "VPSHUFB256", argLength: 2, reg: v21, asm: "VPSHUFB", typ: "Vec256"}, + {name: "VPSHUFB512", argLength: 2, reg: w21, asm: "VPSHUFB", typ: "Vec512"}, + {name: "VPSHUFBMasked128", argLength: 3, reg: w2kw, asm: "VPSHUFB", typ: "Vec128"}, + {name: "VPSHUFBMasked256", argLength: 3, reg: w2kw, asm: "VPSHUFB", typ: "Vec256"}, + {name: "VPSHUFBMasked512", argLength: 3, reg: w2kw, asm: "VPSHUFB", typ: "Vec512"}, + {name: "VPSIGNB128", argLength: 2, reg: v21, asm: "VPSIGNB", typ: "Vec128"}, + {name: "VPSIGNB256", argLength: 2, reg: v21, asm: "VPSIGNB", typ: "Vec256"}, + {name: "VPSIGND128", argLength: 2, reg: v21, asm: "VPSIGND", typ: "Vec128"}, + {name: "VPSIGND256", argLength: 2, reg: v21, asm: "VPSIGND", typ: "Vec256"}, + {name: "VPSIGNW128", argLength: 2, reg: v21, asm: "VPSIGNW", typ: "Vec128"}, + {name: "VPSIGNW256", argLength: 2, reg: v21, asm: "VPSIGNW", typ: "Vec256"}, + {name: "VPSLLD128", argLength: 2, reg: vfpv, asm: "VPSLLD", typ: "Vec128"}, + {name: "VPSLLD256", argLength: 2, reg: vfpv, asm: "VPSLLD", typ: "Vec256"}, + {name: "VPSLLD512", argLength: 2, reg: wfpw, asm: "VPSLLD", typ: "Vec512"}, + {name: "VPSLLDMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLD", typ: "Vec128"}, + {name: "VPSLLDMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLD", typ: "Vec256"}, + {name: "VPSLLDMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLD", typ: "Vec512"}, + {name: "VPSLLQ128", argLength: 2, reg: vfpv, asm: "VPSLLQ", typ: "Vec128"}, + {name: "VPSLLQ256", argLength: 2, reg: vfpv, asm: "VPSLLQ", typ: "Vec256"}, + {name: "VPSLLQ512", argLength: 2, reg: wfpw, asm: "VPSLLQ", typ: "Vec512"}, + {name: "VPSLLQMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLQ", typ: "Vec128"}, + {name: "VPSLLQMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLQ", typ: "Vec256"}, + {name: "VPSLLQMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLQ", typ: "Vec512"}, + {name: "VPSLLVD128", argLength: 2, reg: v21, asm: "VPSLLVD", typ: "Vec128"}, + {name: "VPSLLVD256", argLength: 2, reg: v21, asm: "VPSLLVD", typ: "Vec256"}, + {name: "VPSLLVD512", argLength: 2, reg: w21, asm: "VPSLLVD", typ: "Vec512"}, + {name: "VPSLLVDMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVD", typ: "Vec128"}, + {name: "VPSLLVDMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVD", typ: "Vec256"}, + {name: "VPSLLVDMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVD", typ: "Vec512"}, + {name: "VPSLLVQ128", argLength: 2, reg: v21, asm: "VPSLLVQ", typ: "Vec128"}, + {name: "VPSLLVQ256", argLength: 2, reg: v21, asm: "VPSLLVQ", typ: "Vec256"}, + {name: "VPSLLVQ512", argLength: 2, reg: w21, asm: "VPSLLVQ", typ: "Vec512"}, + {name: "VPSLLVQMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVQ", typ: "Vec128"}, + {name: "VPSLLVQMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVQ", typ: "Vec256"}, + {name: "VPSLLVQMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVQ", typ: "Vec512"}, + {name: "VPSLLVW128", argLength: 2, reg: w21, asm: "VPSLLVW", typ: "Vec128"}, + {name: "VPSLLVW256", argLength: 2, reg: w21, asm: "VPSLLVW", typ: "Vec256"}, + {name: "VPSLLVW512", argLength: 2, reg: w21, asm: "VPSLLVW", typ: "Vec512"}, + {name: "VPSLLVWMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVW", typ: "Vec128"}, + {name: "VPSLLVWMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVW", typ: "Vec256"}, + {name: "VPSLLVWMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVW", typ: "Vec512"}, + {name: "VPSLLW128", argLength: 2, reg: vfpv, asm: "VPSLLW", typ: "Vec128"}, + {name: "VPSLLW256", argLength: 2, reg: vfpv, asm: "VPSLLW", typ: "Vec256"}, + {name: "VPSLLW512", argLength: 2, reg: wfpw, asm: "VPSLLW", typ: "Vec512"}, + {name: "VPSLLWMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLW", typ: "Vec128"}, + {name: "VPSLLWMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLW", typ: "Vec256"}, + {name: "VPSLLWMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLW", typ: "Vec512"}, + {name: "VPSRAD128", argLength: 2, reg: vfpv, asm: "VPSRAD", typ: "Vec128"}, + {name: "VPSRAD256", argLength: 2, reg: vfpv, asm: "VPSRAD", typ: "Vec256"}, + {name: "VPSRAD512", argLength: 2, reg: wfpw, asm: "VPSRAD", typ: "Vec512"}, + {name: "VPSRADMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAD", typ: "Vec128"}, + {name: "VPSRADMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAD", typ: "Vec256"}, + {name: "VPSRADMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAD", typ: "Vec512"}, + {name: "VPSRAQ128", argLength: 2, reg: wfpw, asm: "VPSRAQ", typ: "Vec128"}, + {name: "VPSRAQ256", argLength: 2, reg: wfpw, asm: "VPSRAQ", typ: "Vec256"}, + {name: "VPSRAQ512", argLength: 2, reg: wfpw, asm: "VPSRAQ", typ: "Vec512"}, + {name: "VPSRAQMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAQ", typ: "Vec128"}, + {name: "VPSRAQMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAQ", typ: "Vec256"}, + {name: "VPSRAQMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAQ", typ: "Vec512"}, + {name: "VPSRAVD128", argLength: 2, reg: v21, asm: "VPSRAVD", typ: "Vec128"}, + {name: "VPSRAVD256", argLength: 2, reg: v21, asm: "VPSRAVD", typ: "Vec256"}, + {name: "VPSRAVD512", argLength: 2, reg: w21, asm: "VPSRAVD", typ: "Vec512"}, + {name: "VPSRAVDMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVD", typ: "Vec128"}, + {name: "VPSRAVDMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVD", typ: "Vec256"}, + {name: "VPSRAVDMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVD", typ: "Vec512"}, + {name: "VPSRAVQ128", argLength: 2, reg: w21, asm: "VPSRAVQ", typ: "Vec128"}, + {name: "VPSRAVQ256", argLength: 2, reg: w21, asm: "VPSRAVQ", typ: "Vec256"}, + {name: "VPSRAVQ512", argLength: 2, reg: w21, asm: "VPSRAVQ", typ: "Vec512"}, + {name: "VPSRAVQMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVQ", typ: "Vec128"}, + {name: "VPSRAVQMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVQ", typ: "Vec256"}, + {name: "VPSRAVQMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVQ", typ: "Vec512"}, + {name: "VPSRAVW128", argLength: 2, reg: w21, asm: "VPSRAVW", typ: "Vec128"}, + {name: "VPSRAVW256", argLength: 2, reg: w21, asm: "VPSRAVW", typ: "Vec256"}, + {name: "VPSRAVW512", argLength: 2, reg: w21, asm: "VPSRAVW", typ: "Vec512"}, + {name: "VPSRAVWMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVW", typ: "Vec128"}, + {name: "VPSRAVWMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVW", typ: "Vec256"}, + {name: "VPSRAVWMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVW", typ: "Vec512"}, + {name: "VPSRAW128", argLength: 2, reg: vfpv, asm: "VPSRAW", typ: "Vec128"}, + {name: "VPSRAW256", argLength: 2, reg: vfpv, asm: "VPSRAW", typ: "Vec256"}, + {name: "VPSRAW512", argLength: 2, reg: wfpw, asm: "VPSRAW", typ: "Vec512"}, + {name: "VPSRAWMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAW", typ: "Vec128"}, + {name: "VPSRAWMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAW", typ: "Vec256"}, + {name: "VPSRAWMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAW", typ: "Vec512"}, + {name: "VPSRLD128", argLength: 2, reg: vfpv, asm: "VPSRLD", typ: "Vec128"}, + {name: "VPSRLD256", argLength: 2, reg: vfpv, asm: "VPSRLD", typ: "Vec256"}, + {name: "VPSRLD512", argLength: 2, reg: wfpw, asm: "VPSRLD", typ: "Vec512"}, + {name: "VPSRLDMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLD", typ: "Vec128"}, + {name: "VPSRLDMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLD", typ: "Vec256"}, + {name: "VPSRLDMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLD", typ: "Vec512"}, + {name: "VPSRLQ128", argLength: 2, reg: vfpv, asm: "VPSRLQ", typ: "Vec128"}, + {name: "VPSRLQ256", argLength: 2, reg: vfpv, asm: "VPSRLQ", typ: "Vec256"}, + {name: "VPSRLQ512", argLength: 2, reg: wfpw, asm: "VPSRLQ", typ: "Vec512"}, + {name: "VPSRLQMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLQ", typ: "Vec128"}, + {name: "VPSRLQMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLQ", typ: "Vec256"}, + {name: "VPSRLQMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLQ", typ: "Vec512"}, + {name: "VPSRLVD128", argLength: 2, reg: v21, asm: "VPSRLVD", typ: "Vec128"}, + {name: "VPSRLVD256", argLength: 2, reg: v21, asm: "VPSRLVD", typ: "Vec256"}, + {name: "VPSRLVD512", argLength: 2, reg: w21, asm: "VPSRLVD", typ: "Vec512"}, + {name: "VPSRLVDMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVD", typ: "Vec128"}, + {name: "VPSRLVDMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVD", typ: "Vec256"}, + {name: "VPSRLVDMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVD", typ: "Vec512"}, + {name: "VPSRLVQ128", argLength: 2, reg: v21, asm: "VPSRLVQ", typ: "Vec128"}, + {name: "VPSRLVQ256", argLength: 2, reg: v21, asm: "VPSRLVQ", typ: "Vec256"}, + {name: "VPSRLVQ512", argLength: 2, reg: w21, asm: "VPSRLVQ", typ: "Vec512"}, + {name: "VPSRLVQMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVQ", typ: "Vec128"}, + {name: "VPSRLVQMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVQ", typ: "Vec256"}, + {name: "VPSRLVQMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVQ", typ: "Vec512"}, + {name: "VPSRLVW128", argLength: 2, reg: w21, asm: "VPSRLVW", typ: "Vec128"}, + {name: "VPSRLVW256", argLength: 2, reg: w21, asm: "VPSRLVW", typ: "Vec256"}, + {name: "VPSRLVW512", argLength: 2, reg: w21, asm: "VPSRLVW", typ: "Vec512"}, + {name: "VPSRLVWMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVW", typ: "Vec128"}, + {name: "VPSRLVWMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVW", typ: "Vec256"}, + {name: "VPSRLVWMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVW", typ: "Vec512"}, + {name: "VPSRLW128", argLength: 2, reg: vfpv, asm: "VPSRLW", typ: "Vec128"}, + {name: "VPSRLW256", argLength: 2, reg: vfpv, asm: "VPSRLW", typ: "Vec256"}, + {name: "VPSRLW512", argLength: 2, reg: wfpw, asm: "VPSRLW", typ: "Vec512"}, + {name: "VPSRLWMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLW", typ: "Vec128"}, + {name: "VPSRLWMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLW", typ: "Vec256"}, + {name: "VPSRLWMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLW", typ: "Vec512"}, + {name: "VPSUBB128", argLength: 2, reg: v21, asm: "VPSUBB", typ: "Vec128"}, + {name: "VPSUBB256", argLength: 2, reg: v21, asm: "VPSUBB", typ: "Vec256"}, + {name: "VPSUBB512", argLength: 2, reg: w21, asm: "VPSUBB", typ: "Vec512"}, + {name: "VPSUBBMasked128", argLength: 3, reg: w2kw, asm: "VPSUBB", typ: "Vec128"}, + {name: "VPSUBBMasked256", argLength: 3, reg: w2kw, asm: "VPSUBB", typ: "Vec256"}, + {name: "VPSUBBMasked512", argLength: 3, reg: w2kw, asm: "VPSUBB", typ: "Vec512"}, + {name: "VPSUBD128", argLength: 2, reg: v21, asm: "VPSUBD", typ: "Vec128"}, + {name: "VPSUBD256", argLength: 2, reg: v21, asm: "VPSUBD", typ: "Vec256"}, + {name: "VPSUBD512", argLength: 2, reg: w21, asm: "VPSUBD", typ: "Vec512"}, + {name: "VPSUBDMasked128", argLength: 3, reg: w2kw, asm: "VPSUBD", typ: "Vec128"}, + {name: "VPSUBDMasked256", argLength: 3, reg: w2kw, asm: "VPSUBD", typ: "Vec256"}, + {name: "VPSUBDMasked512", argLength: 3, reg: w2kw, asm: "VPSUBD", typ: "Vec512"}, + {name: "VPSUBQ128", argLength: 2, reg: v21, asm: "VPSUBQ", typ: "Vec128"}, + {name: "VPSUBQ256", argLength: 2, reg: v21, asm: "VPSUBQ", typ: "Vec256"}, + {name: "VPSUBQ512", argLength: 2, reg: w21, asm: "VPSUBQ", typ: "Vec512"}, + {name: "VPSUBQMasked128", argLength: 3, reg: w2kw, asm: "VPSUBQ", typ: "Vec128"}, + {name: "VPSUBQMasked256", argLength: 3, reg: w2kw, asm: "VPSUBQ", typ: "Vec256"}, + {name: "VPSUBQMasked512", argLength: 3, reg: w2kw, asm: "VPSUBQ", typ: "Vec512"}, + {name: "VPSUBSB128", argLength: 2, reg: v21, asm: "VPSUBSB", typ: "Vec128"}, + {name: "VPSUBSB256", argLength: 2, reg: v21, asm: "VPSUBSB", typ: "Vec256"}, + {name: "VPSUBSB512", argLength: 2, reg: w21, asm: "VPSUBSB", typ: "Vec512"}, + {name: "VPSUBSBMasked128", argLength: 3, reg: w2kw, asm: "VPSUBSB", typ: "Vec128"}, + {name: "VPSUBSBMasked256", argLength: 3, reg: w2kw, asm: "VPSUBSB", typ: "Vec256"}, + {name: "VPSUBSBMasked512", argLength: 3, reg: w2kw, asm: "VPSUBSB", typ: "Vec512"}, + {name: "VPSUBSW128", argLength: 2, reg: v21, asm: "VPSUBSW", typ: "Vec128"}, + {name: "VPSUBSW256", argLength: 2, reg: v21, asm: "VPSUBSW", typ: "Vec256"}, + {name: "VPSUBSW512", argLength: 2, reg: w21, asm: "VPSUBSW", typ: "Vec512"}, + {name: "VPSUBSWMasked128", argLength: 3, reg: w2kw, asm: "VPSUBSW", typ: "Vec128"}, + {name: "VPSUBSWMasked256", argLength: 3, reg: w2kw, asm: "VPSUBSW", typ: "Vec256"}, + {name: "VPSUBSWMasked512", argLength: 3, reg: w2kw, asm: "VPSUBSW", typ: "Vec512"}, + {name: "VPSUBUSB128", argLength: 2, reg: v21, asm: "VPSUBUSB", typ: "Vec128"}, + {name: "VPSUBUSB256", argLength: 2, reg: v21, asm: "VPSUBUSB", typ: "Vec256"}, + {name: "VPSUBUSB512", argLength: 2, reg: w21, asm: "VPSUBUSB", typ: "Vec512"}, + {name: "VPSUBUSBMasked128", argLength: 3, reg: w2kw, asm: "VPSUBUSB", typ: "Vec128"}, + {name: "VPSUBUSBMasked256", argLength: 3, reg: w2kw, asm: "VPSUBUSB", typ: "Vec256"}, + {name: "VPSUBUSBMasked512", argLength: 3, reg: w2kw, asm: "VPSUBUSB", typ: "Vec512"}, + {name: "VPSUBUSW128", argLength: 2, reg: v21, asm: "VPSUBUSW", typ: "Vec128"}, + {name: "VPSUBUSW256", argLength: 2, reg: v21, asm: "VPSUBUSW", typ: "Vec256"}, + {name: "VPSUBUSW512", argLength: 2, reg: w21, asm: "VPSUBUSW", typ: "Vec512"}, + {name: "VPSUBUSWMasked128", argLength: 3, reg: w2kw, asm: "VPSUBUSW", typ: "Vec128"}, + {name: "VPSUBUSWMasked256", argLength: 3, reg: w2kw, asm: "VPSUBUSW", typ: "Vec256"}, + {name: "VPSUBUSWMasked512", argLength: 3, reg: w2kw, asm: "VPSUBUSW", typ: "Vec512"}, + {name: "VPSUBW128", argLength: 2, reg: v21, asm: "VPSUBW", typ: "Vec128"}, + {name: "VPSUBW256", argLength: 2, reg: v21, asm: "VPSUBW", typ: "Vec256"}, + {name: "VPSUBW512", argLength: 2, reg: w21, asm: "VPSUBW", typ: "Vec512"}, + {name: "VPSUBWMasked128", argLength: 3, reg: w2kw, asm: "VPSUBW", typ: "Vec128"}, + {name: "VPSUBWMasked256", argLength: 3, reg: w2kw, asm: "VPSUBW", typ: "Vec256"}, + {name: "VPSUBWMasked512", argLength: 3, reg: w2kw, asm: "VPSUBW", typ: "Vec512"}, + {name: "VPUNPCKHDQ128", argLength: 2, reg: v21, asm: "VPUNPCKHDQ", typ: "Vec128"}, + {name: "VPUNPCKHDQ256", argLength: 2, reg: v21, asm: "VPUNPCKHDQ", typ: "Vec256"}, + {name: "VPUNPCKHDQ512", argLength: 2, reg: w21, asm: "VPUNPCKHDQ", typ: "Vec512"}, + {name: "VPUNPCKHQDQ128", argLength: 2, reg: v21, asm: "VPUNPCKHQDQ", typ: "Vec128"}, + {name: "VPUNPCKHQDQ256", argLength: 2, reg: v21, asm: "VPUNPCKHQDQ", typ: "Vec256"}, + {name: "VPUNPCKHQDQ512", argLength: 2, reg: w21, asm: "VPUNPCKHQDQ", typ: "Vec512"}, + {name: "VPUNPCKHWD128", argLength: 2, reg: v21, asm: "VPUNPCKHWD", typ: "Vec128"}, + {name: "VPUNPCKHWD256", argLength: 2, reg: v21, asm: "VPUNPCKHWD", typ: "Vec256"}, + {name: "VPUNPCKHWD512", argLength: 2, reg: w21, asm: "VPUNPCKHWD", typ: "Vec512"}, + {name: "VPUNPCKLDQ128", argLength: 2, reg: v21, asm: "VPUNPCKLDQ", typ: "Vec128"}, + {name: "VPUNPCKLDQ256", argLength: 2, reg: v21, asm: "VPUNPCKLDQ", typ: "Vec256"}, + {name: "VPUNPCKLDQ512", argLength: 2, reg: w21, asm: "VPUNPCKLDQ", typ: "Vec512"}, + {name: "VPUNPCKLQDQ128", argLength: 2, reg: v21, asm: "VPUNPCKLQDQ", typ: "Vec128"}, + {name: "VPUNPCKLQDQ256", argLength: 2, reg: v21, asm: "VPUNPCKLQDQ", typ: "Vec256"}, + {name: "VPUNPCKLQDQ512", argLength: 2, reg: w21, asm: "VPUNPCKLQDQ", typ: "Vec512"}, + {name: "VPUNPCKLWD128", argLength: 2, reg: v21, asm: "VPUNPCKLWD", typ: "Vec128"}, + {name: "VPUNPCKLWD256", argLength: 2, reg: v21, asm: "VPUNPCKLWD", typ: "Vec256"}, + {name: "VPUNPCKLWD512", argLength: 2, reg: w21, asm: "VPUNPCKLWD", typ: "Vec512"}, + {name: "VPXOR128", argLength: 2, reg: v21, asm: "VPXOR", commutative: true, typ: "Vec128"}, + {name: "VPXOR256", argLength: 2, reg: v21, asm: "VPXOR", commutative: true, typ: "Vec256"}, + {name: "VPXORD512", argLength: 2, reg: w21, asm: "VPXORD", commutative: true, typ: "Vec512"}, + {name: "VPXORDMasked128", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec128"}, + {name: "VPXORDMasked256", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec256"}, + {name: "VPXORDMasked512", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec512"}, + {name: "VPXORQ512", argLength: 2, reg: w21, asm: "VPXORQ", commutative: true, typ: "Vec512"}, + {name: "VPXORQMasked128", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec128"}, + {name: "VPXORQMasked256", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec256"}, + {name: "VPXORQMasked512", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec512"}, + {name: "VRCP14PD128", argLength: 1, reg: w11, asm: "VRCP14PD", typ: "Vec128"}, + {name: "VRCP14PD256", argLength: 1, reg: w11, asm: "VRCP14PD", typ: "Vec256"}, + {name: "VRCP14PD512", argLength: 1, reg: w11, asm: "VRCP14PD", typ: "Vec512"}, + {name: "VRCP14PDMasked128", argLength: 2, reg: wkw, asm: "VRCP14PD", typ: "Vec128"}, + {name: "VRCP14PDMasked256", argLength: 2, reg: wkw, asm: "VRCP14PD", typ: "Vec256"}, + {name: "VRCP14PDMasked512", argLength: 2, reg: wkw, asm: "VRCP14PD", typ: "Vec512"}, + {name: "VRCP14PS512", argLength: 1, reg: w11, asm: "VRCP14PS", typ: "Vec512"}, + {name: "VRCP14PSMasked128", argLength: 2, reg: wkw, asm: "VRCP14PS", typ: "Vec128"}, + {name: "VRCP14PSMasked256", argLength: 2, reg: wkw, asm: "VRCP14PS", typ: "Vec256"}, + {name: "VRCP14PSMasked512", argLength: 2, reg: wkw, asm: "VRCP14PS", typ: "Vec512"}, + {name: "VRCPPS128", argLength: 1, reg: v11, asm: "VRCPPS", typ: "Vec128"}, + {name: "VRCPPS256", argLength: 1, reg: v11, asm: "VRCPPS", typ: "Vec256"}, + {name: "VRSQRT14PD128", argLength: 1, reg: w11, asm: "VRSQRT14PD", typ: "Vec128"}, + {name: "VRSQRT14PD256", argLength: 1, reg: w11, asm: "VRSQRT14PD", typ: "Vec256"}, + {name: "VRSQRT14PD512", argLength: 1, reg: w11, asm: "VRSQRT14PD", typ: "Vec512"}, + {name: "VRSQRT14PDMasked128", argLength: 2, reg: wkw, asm: "VRSQRT14PD", typ: "Vec128"}, + {name: "VRSQRT14PDMasked256", argLength: 2, reg: wkw, asm: "VRSQRT14PD", typ: "Vec256"}, + {name: "VRSQRT14PDMasked512", argLength: 2, reg: wkw, asm: "VRSQRT14PD", typ: "Vec512"}, + {name: "VRSQRT14PS512", argLength: 1, reg: w11, asm: "VRSQRT14PS", typ: "Vec512"}, + {name: "VRSQRT14PSMasked128", argLength: 2, reg: wkw, asm: "VRSQRT14PS", typ: "Vec128"}, + {name: "VRSQRT14PSMasked256", argLength: 2, reg: wkw, asm: "VRSQRT14PS", typ: "Vec256"}, + {name: "VRSQRT14PSMasked512", argLength: 2, reg: wkw, asm: "VRSQRT14PS", typ: "Vec512"}, + {name: "VRSQRTPS128", argLength: 1, reg: v11, asm: "VRSQRTPS", typ: "Vec128"}, + {name: "VRSQRTPS256", argLength: 1, reg: v11, asm: "VRSQRTPS", typ: "Vec256"}, + {name: "VSCALEFPD128", argLength: 2, reg: w21, asm: "VSCALEFPD", typ: "Vec128"}, + {name: "VSCALEFPD256", argLength: 2, reg: w21, asm: "VSCALEFPD", typ: "Vec256"}, + {name: "VSCALEFPD512", argLength: 2, reg: w21, asm: "VSCALEFPD", typ: "Vec512"}, + {name: "VSCALEFPDMasked128", argLength: 3, reg: w2kw, asm: "VSCALEFPD", typ: "Vec128"}, + {name: "VSCALEFPDMasked256", argLength: 3, reg: w2kw, asm: "VSCALEFPD", typ: "Vec256"}, + {name: "VSCALEFPDMasked512", argLength: 3, reg: w2kw, asm: "VSCALEFPD", typ: "Vec512"}, + {name: "VSCALEFPS128", argLength: 2, reg: w21, asm: "VSCALEFPS", typ: "Vec128"}, + {name: "VSCALEFPS256", argLength: 2, reg: w21, asm: "VSCALEFPS", typ: "Vec256"}, + {name: "VSCALEFPS512", argLength: 2, reg: w21, asm: "VSCALEFPS", typ: "Vec512"}, + {name: "VSCALEFPSMasked128", argLength: 3, reg: w2kw, asm: "VSCALEFPS", typ: "Vec128"}, + {name: "VSCALEFPSMasked256", argLength: 3, reg: w2kw, asm: "VSCALEFPS", typ: "Vec256"}, + {name: "VSCALEFPSMasked512", argLength: 3, reg: w2kw, asm: "VSCALEFPS", typ: "Vec512"}, + {name: "VSQRTPD128", argLength: 1, reg: v11, asm: "VSQRTPD", typ: "Vec128"}, + {name: "VSQRTPD256", argLength: 1, reg: v11, asm: "VSQRTPD", typ: "Vec256"}, + {name: "VSQRTPD512", argLength: 1, reg: w11, asm: "VSQRTPD", typ: "Vec512"}, + {name: "VSQRTPDMasked128", argLength: 2, reg: wkw, asm: "VSQRTPD", typ: "Vec128"}, + {name: "VSQRTPDMasked256", argLength: 2, reg: wkw, asm: "VSQRTPD", typ: "Vec256"}, + {name: "VSQRTPDMasked512", argLength: 2, reg: wkw, asm: "VSQRTPD", typ: "Vec512"}, + {name: "VSQRTPS128", argLength: 1, reg: v11, asm: "VSQRTPS", typ: "Vec128"}, + {name: "VSQRTPS256", argLength: 1, reg: v11, asm: "VSQRTPS", typ: "Vec256"}, + {name: "VSQRTPS512", argLength: 1, reg: w11, asm: "VSQRTPS", typ: "Vec512"}, + {name: "VSQRTPSMasked128", argLength: 2, reg: wkw, asm: "VSQRTPS", typ: "Vec128"}, + {name: "VSQRTPSMasked256", argLength: 2, reg: wkw, asm: "VSQRTPS", typ: "Vec256"}, + {name: "VSQRTPSMasked512", argLength: 2, reg: wkw, asm: "VSQRTPS", typ: "Vec512"}, + {name: "VSUBPD128", argLength: 2, reg: v21, asm: "VSUBPD", typ: "Vec128"}, + {name: "VSUBPD256", argLength: 2, reg: v21, asm: "VSUBPD", typ: "Vec256"}, + {name: "VSUBPD512", argLength: 2, reg: w21, asm: "VSUBPD", typ: "Vec512"}, + {name: "VSUBPDMasked128", argLength: 3, reg: w2kw, asm: "VSUBPD", typ: "Vec128"}, + {name: "VSUBPDMasked256", argLength: 3, reg: w2kw, asm: "VSUBPD", typ: "Vec256"}, + {name: "VSUBPDMasked512", argLength: 3, reg: w2kw, asm: "VSUBPD", typ: "Vec512"}, + {name: "VSUBPS128", argLength: 2, reg: v21, asm: "VSUBPS", typ: "Vec128"}, + {name: "VSUBPS256", argLength: 2, reg: v21, asm: "VSUBPS", typ: "Vec256"}, + {name: "VSUBPS512", argLength: 2, reg: w21, asm: "VSUBPS", typ: "Vec512"}, + {name: "VSUBPSMasked128", argLength: 3, reg: w2kw, asm: "VSUBPS", typ: "Vec128"}, + {name: "VSUBPSMasked256", argLength: 3, reg: w2kw, asm: "VSUBPS", typ: "Vec256"}, + {name: "VSUBPSMasked512", argLength: 3, reg: w2kw, asm: "VSUBPS", typ: "Vec512"}, + {name: "SHA1RNDS4128", argLength: 2, reg: v21, asm: "SHA1RNDS4", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VAESKEYGENASSIST128", argLength: 1, reg: v11, asm: "VAESKEYGENASSIST", aux: "UInt8", typ: "Vec128"}, + {name: "VCMPPD128", argLength: 2, reg: v21, asm: "VCMPPD", aux: "UInt8", typ: "Vec128"}, + {name: "VCMPPD256", argLength: 2, reg: v21, asm: "VCMPPD", aux: "UInt8", typ: "Vec256"}, + {name: "VCMPPD512", argLength: 2, reg: w2k, asm: "VCMPPD", aux: "UInt8", typ: "Mask"}, + {name: "VCMPPDMasked128", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "UInt8", typ: "Mask"}, + {name: "VCMPPDMasked256", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "UInt8", typ: "Mask"}, + {name: "VCMPPDMasked512", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "UInt8", typ: "Mask"}, + {name: "VCMPPS128", argLength: 2, reg: v21, asm: "VCMPPS", aux: "UInt8", typ: "Vec128"}, + {name: "VCMPPS256", argLength: 2, reg: v21, asm: "VCMPPS", aux: "UInt8", typ: "Vec256"}, + {name: "VCMPPS512", argLength: 2, reg: w2k, asm: "VCMPPS", aux: "UInt8", typ: "Mask"}, + {name: "VCMPPSMasked128", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "UInt8", typ: "Mask"}, + {name: "VCMPPSMasked256", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "UInt8", typ: "Mask"}, + {name: "VCMPPSMasked512", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "UInt8", typ: "Mask"}, + {name: "VEXTRACTF64X4256", argLength: 1, reg: w11, asm: "VEXTRACTF64X4", aux: "UInt8", typ: "Vec256"}, + {name: "VEXTRACTF128128", argLength: 1, reg: v11, asm: "VEXTRACTF128", aux: "UInt8", typ: "Vec128"}, + {name: "VEXTRACTI64X4256", argLength: 1, reg: w11, asm: "VEXTRACTI64X4", aux: "UInt8", typ: "Vec256"}, + {name: "VEXTRACTI128128", argLength: 1, reg: v11, asm: "VEXTRACTI128", aux: "UInt8", typ: "Vec128"}, + {name: "VGF2P8AFFINEINVQB128", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "UInt8", typ: "Vec128"}, + {name: "VGF2P8AFFINEINVQB256", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "UInt8", typ: "Vec256"}, + {name: "VGF2P8AFFINEINVQB512", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "UInt8", typ: "Vec512"}, + {name: "VGF2P8AFFINEINVQBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "UInt8", typ: "Vec128"}, + {name: "VGF2P8AFFINEINVQBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "UInt8", typ: "Vec256"}, + {name: "VGF2P8AFFINEINVQBMasked512", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "UInt8", typ: "Vec512"}, + {name: "VGF2P8AFFINEQB128", argLength: 2, reg: w21, asm: "VGF2P8AFFINEQB", aux: "UInt8", typ: "Vec128"}, + {name: "VGF2P8AFFINEQB256", argLength: 2, reg: w21, asm: "VGF2P8AFFINEQB", aux: "UInt8", typ: "Vec256"}, + {name: "VGF2P8AFFINEQB512", argLength: 2, reg: w21, asm: "VGF2P8AFFINEQB", aux: "UInt8", typ: "Vec512"}, + {name: "VGF2P8AFFINEQBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "UInt8", typ: "Vec128"}, + {name: "VGF2P8AFFINEQBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "UInt8", typ: "Vec256"}, + {name: "VGF2P8AFFINEQBMasked512", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "UInt8", typ: "Vec512"}, + {name: "VINSERTF64X4512", argLength: 2, reg: w21, asm: "VINSERTF64X4", aux: "UInt8", typ: "Vec512"}, + {name: "VINSERTF128256", argLength: 2, reg: v21, asm: "VINSERTF128", aux: "UInt8", typ: "Vec256"}, + {name: "VINSERTI64X4512", argLength: 2, reg: w21, asm: "VINSERTI64X4", aux: "UInt8", typ: "Vec512"}, + {name: "VINSERTI128256", argLength: 2, reg: v21, asm: "VINSERTI128", aux: "UInt8", typ: "Vec256"}, + {name: "VPALIGNR128", argLength: 2, reg: v21, asm: "VPALIGNR", aux: "UInt8", typ: "Vec128"}, + {name: "VPALIGNR256", argLength: 2, reg: v21, asm: "VPALIGNR", aux: "UInt8", typ: "Vec256"}, + {name: "VPALIGNR512", argLength: 2, reg: w21, asm: "VPALIGNR", aux: "UInt8", typ: "Vec512"}, + {name: "VPALIGNRMasked128", argLength: 3, reg: w2kw, asm: "VPALIGNR", aux: "UInt8", typ: "Vec128"}, + {name: "VPALIGNRMasked256", argLength: 3, reg: w2kw, asm: "VPALIGNR", aux: "UInt8", typ: "Vec256"}, + {name: "VPALIGNRMasked512", argLength: 3, reg: w2kw, asm: "VPALIGNR", aux: "UInt8", typ: "Vec512"}, + {name: "VPCLMULQDQ128", argLength: 2, reg: v21, asm: "VPCLMULQDQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPCLMULQDQ256", argLength: 2, reg: w21, asm: "VPCLMULQDQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPCLMULQDQ512", argLength: 2, reg: w21, asm: "VPCLMULQDQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPCMPB512", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPD512", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPDMasked128", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPDMasked256", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPQ512", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPQMasked128", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPQMasked256", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPQMasked512", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUB512", argLength: 2, reg: w2k, asm: "VPCMPUB", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUD512", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUDMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUDMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUQ512", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUQMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUQMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUQMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUW512", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUWMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPUWMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPW512", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPWMasked256", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "UInt8", typ: "Mask"}, + {name: "VPCMPWMasked512", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "UInt8", typ: "Mask"}, + {name: "VPERM2F128256", argLength: 2, reg: v21, asm: "VPERM2F128", aux: "UInt8", typ: "Vec256"}, + {name: "VPERM2I128256", argLength: 2, reg: v21, asm: "VPERM2I128", aux: "UInt8", typ: "Vec256"}, + {name: "VPEXTRB128", argLength: 1, reg: vgp, asm: "VPEXTRB", aux: "UInt8", typ: "int8"}, + {name: "VPEXTRD128", argLength: 1, reg: vgp, asm: "VPEXTRD", aux: "UInt8", typ: "int32"}, + {name: "VPEXTRQ128", argLength: 1, reg: vgp, asm: "VPEXTRQ", aux: "UInt8", typ: "int64"}, + {name: "VPEXTRW128", argLength: 1, reg: vgp, asm: "VPEXTRW", aux: "UInt8", typ: "int16"}, + {name: "VPINSRB128", argLength: 2, reg: vgpv, asm: "VPINSRB", aux: "UInt8", typ: "Vec128"}, + {name: "VPINSRD128", argLength: 2, reg: vgpv, asm: "VPINSRD", aux: "UInt8", typ: "Vec128"}, + {name: "VPINSRQ128", argLength: 2, reg: vgpv, asm: "VPINSRQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPINSRW128", argLength: 2, reg: vgpv, asm: "VPINSRW", aux: "UInt8", typ: "Vec128"}, + {name: "VPROLD128", argLength: 1, reg: w11, asm: "VPROLD", aux: "UInt8", typ: "Vec128"}, + {name: "VPROLD256", argLength: 1, reg: w11, asm: "VPROLD", aux: "UInt8", typ: "Vec256"}, + {name: "VPROLD512", argLength: 1, reg: w11, asm: "VPROLD", aux: "UInt8", typ: "Vec512"}, + {name: "VPROLDMasked128", argLength: 2, reg: wkw, asm: "VPROLD", aux: "UInt8", typ: "Vec128"}, + {name: "VPROLDMasked256", argLength: 2, reg: wkw, asm: "VPROLD", aux: "UInt8", typ: "Vec256"}, + {name: "VPROLDMasked512", argLength: 2, reg: wkw, asm: "VPROLD", aux: "UInt8", typ: "Vec512"}, + {name: "VPROLQ128", argLength: 1, reg: w11, asm: "VPROLQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPROLQ256", argLength: 1, reg: w11, asm: "VPROLQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPROLQ512", argLength: 1, reg: w11, asm: "VPROLQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPROLQMasked128", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPROLQMasked256", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPROLQMasked512", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPRORD128", argLength: 1, reg: w11, asm: "VPRORD", aux: "UInt8", typ: "Vec128"}, + {name: "VPRORD256", argLength: 1, reg: w11, asm: "VPRORD", aux: "UInt8", typ: "Vec256"}, + {name: "VPRORD512", argLength: 1, reg: w11, asm: "VPRORD", aux: "UInt8", typ: "Vec512"}, + {name: "VPRORDMasked128", argLength: 2, reg: wkw, asm: "VPRORD", aux: "UInt8", typ: "Vec128"}, + {name: "VPRORDMasked256", argLength: 2, reg: wkw, asm: "VPRORD", aux: "UInt8", typ: "Vec256"}, + {name: "VPRORDMasked512", argLength: 2, reg: wkw, asm: "VPRORD", aux: "UInt8", typ: "Vec512"}, + {name: "VPRORQ128", argLength: 1, reg: w11, asm: "VPRORQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPRORQ256", argLength: 1, reg: w11, asm: "VPRORQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPRORQ512", argLength: 1, reg: w11, asm: "VPRORQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPRORQMasked128", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPRORQMasked256", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPRORQMasked512", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHLDD128", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHLDD256", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHLDD512", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHLDDMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHLDDMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHLDDMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHLDQ128", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHLDQ256", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHLDQ512", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHLDQMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHLDQMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHLDQMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHLDW128", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHLDW256", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHLDW512", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHLDWMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHLDWMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHLDWMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHRDD128", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHRDD256", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHRDD512", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHRDDMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHRDDMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHRDDMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHRDQ128", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHRDQ256", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHRDQ512", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHRDQMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHRDQMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHRDQMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHRDW128", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHRDW256", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHRDW512", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHRDWMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHRDWMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHRDWMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHUFD128", argLength: 1, reg: v11, asm: "VPSHUFD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHUFD256", argLength: 1, reg: v11, asm: "VPSHUFD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHUFD512", argLength: 1, reg: w11, asm: "VPSHUFD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHUFDMasked128", argLength: 2, reg: wkw, asm: "VPSHUFD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHUFDMasked256", argLength: 2, reg: wkw, asm: "VPSHUFD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHUFDMasked512", argLength: 2, reg: wkw, asm: "VPSHUFD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHUFHW128", argLength: 1, reg: v11, asm: "VPSHUFHW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHUFHW256", argLength: 1, reg: v11, asm: "VPSHUFHW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHUFHW512", argLength: 1, reg: w11, asm: "VPSHUFHW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHUFHWMasked128", argLength: 2, reg: wkw, asm: "VPSHUFHW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHUFHWMasked256", argLength: 2, reg: wkw, asm: "VPSHUFHW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHUFHWMasked512", argLength: 2, reg: wkw, asm: "VPSHUFHW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHUFLW128", argLength: 1, reg: v11, asm: "VPSHUFLW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHUFLW256", argLength: 1, reg: v11, asm: "VPSHUFLW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHUFLW512", argLength: 1, reg: w11, asm: "VPSHUFLW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSHUFLWMasked128", argLength: 2, reg: wkw, asm: "VPSHUFLW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSHUFLWMasked256", argLength: 2, reg: wkw, asm: "VPSHUFLW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSHUFLWMasked512", argLength: 2, reg: wkw, asm: "VPSHUFLW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSLLD128const", argLength: 1, reg: v11, asm: "VPSLLD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSLLD256const", argLength: 1, reg: v11, asm: "VPSLLD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSLLD512const", argLength: 1, reg: w11, asm: "VPSLLD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSLLDMasked128const", argLength: 2, reg: wkw, asm: "VPSLLD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSLLDMasked256const", argLength: 2, reg: wkw, asm: "VPSLLD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSLLDMasked512const", argLength: 2, reg: wkw, asm: "VPSLLD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSLLQ128const", argLength: 1, reg: v11, asm: "VPSLLQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPSLLQ256const", argLength: 1, reg: v11, asm: "VPSLLQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPSLLQ512const", argLength: 1, reg: w11, asm: "VPSLLQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSLLQMasked128const", argLength: 2, reg: wkw, asm: "VPSLLQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPSLLQMasked256const", argLength: 2, reg: wkw, asm: "VPSLLQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPSLLQMasked512const", argLength: 2, reg: wkw, asm: "VPSLLQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSLLW128const", argLength: 1, reg: v11, asm: "VPSLLW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSLLW256const", argLength: 1, reg: v11, asm: "VPSLLW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSLLW512const", argLength: 1, reg: w11, asm: "VPSLLW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSLLWMasked128const", argLength: 2, reg: wkw, asm: "VPSLLW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSLLWMasked256const", argLength: 2, reg: wkw, asm: "VPSLLW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSLLWMasked512const", argLength: 2, reg: wkw, asm: "VPSLLW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRAD128const", argLength: 1, reg: v11, asm: "VPSRAD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRAD256const", argLength: 1, reg: v11, asm: "VPSRAD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRAD512const", argLength: 1, reg: w11, asm: "VPSRAD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRADMasked128const", argLength: 2, reg: wkw, asm: "VPSRAD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRADMasked256const", argLength: 2, reg: wkw, asm: "VPSRAD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRADMasked512const", argLength: 2, reg: wkw, asm: "VPSRAD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRAQ128const", argLength: 1, reg: w11, asm: "VPSRAQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRAQ256const", argLength: 1, reg: w11, asm: "VPSRAQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRAQ512const", argLength: 1, reg: w11, asm: "VPSRAQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRAQMasked128const", argLength: 2, reg: wkw, asm: "VPSRAQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRAQMasked256const", argLength: 2, reg: wkw, asm: "VPSRAQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRAQMasked512const", argLength: 2, reg: wkw, asm: "VPSRAQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRAW128const", argLength: 1, reg: v11, asm: "VPSRAW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRAW256const", argLength: 1, reg: v11, asm: "VPSRAW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRAW512const", argLength: 1, reg: w11, asm: "VPSRAW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRAWMasked128const", argLength: 2, reg: wkw, asm: "VPSRAW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRAWMasked256const", argLength: 2, reg: wkw, asm: "VPSRAW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRAWMasked512const", argLength: 2, reg: wkw, asm: "VPSRAW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRLD128const", argLength: 1, reg: v11, asm: "VPSRLD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRLD256const", argLength: 1, reg: v11, asm: "VPSRLD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRLD512const", argLength: 1, reg: w11, asm: "VPSRLD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRLDMasked128const", argLength: 2, reg: wkw, asm: "VPSRLD", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRLDMasked256const", argLength: 2, reg: wkw, asm: "VPSRLD", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRLDMasked512const", argLength: 2, reg: wkw, asm: "VPSRLD", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRLQ128const", argLength: 1, reg: v11, asm: "VPSRLQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRLQ256const", argLength: 1, reg: v11, asm: "VPSRLQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRLQ512const", argLength: 1, reg: w11, asm: "VPSRLQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRLQMasked128const", argLength: 2, reg: wkw, asm: "VPSRLQ", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRLQMasked256const", argLength: 2, reg: wkw, asm: "VPSRLQ", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRLQMasked512const", argLength: 2, reg: wkw, asm: "VPSRLQ", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRLW128const", argLength: 1, reg: v11, asm: "VPSRLW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRLW256const", argLength: 1, reg: v11, asm: "VPSRLW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRLW512const", argLength: 1, reg: w11, asm: "VPSRLW", aux: "UInt8", typ: "Vec512"}, + {name: "VPSRLWMasked128const", argLength: 2, reg: wkw, asm: "VPSRLW", aux: "UInt8", typ: "Vec128"}, + {name: "VPSRLWMasked256const", argLength: 2, reg: wkw, asm: "VPSRLW", aux: "UInt8", typ: "Vec256"}, + {name: "VPSRLWMasked512const", argLength: 2, reg: wkw, asm: "VPSRLW", aux: "UInt8", typ: "Vec512"}, + {name: "VPTERNLOGD128", argLength: 3, reg: w31, asm: "VPTERNLOGD", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPTERNLOGD256", argLength: 3, reg: w31, asm: "VPTERNLOGD", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPTERNLOGD512", argLength: 3, reg: w31, asm: "VPTERNLOGD", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPTERNLOGQ128", argLength: 3, reg: w31, asm: "VPTERNLOGQ", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPTERNLOGQ256", argLength: 3, reg: w31, asm: "VPTERNLOGQ", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPTERNLOGQ512", argLength: 3, reg: w31, asm: "VPTERNLOGQ", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VREDUCEPD128", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "UInt8", typ: "Vec128"}, + {name: "VREDUCEPD256", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "UInt8", typ: "Vec256"}, + {name: "VREDUCEPD512", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "UInt8", typ: "Vec512"}, + {name: "VREDUCEPDMasked128", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "UInt8", typ: "Vec128"}, + {name: "VREDUCEPDMasked256", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "UInt8", typ: "Vec256"}, + {name: "VREDUCEPDMasked512", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "UInt8", typ: "Vec512"}, + {name: "VREDUCEPS128", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "UInt8", typ: "Vec128"}, + {name: "VREDUCEPS256", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "UInt8", typ: "Vec256"}, + {name: "VREDUCEPS512", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "UInt8", typ: "Vec512"}, + {name: "VREDUCEPSMasked128", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "UInt8", typ: "Vec128"}, + {name: "VREDUCEPSMasked256", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "UInt8", typ: "Vec256"}, + {name: "VREDUCEPSMasked512", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "UInt8", typ: "Vec512"}, + {name: "VRNDSCALEPD128", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "UInt8", typ: "Vec128"}, + {name: "VRNDSCALEPD256", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "UInt8", typ: "Vec256"}, + {name: "VRNDSCALEPD512", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "UInt8", typ: "Vec512"}, + {name: "VRNDSCALEPDMasked128", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "UInt8", typ: "Vec128"}, + {name: "VRNDSCALEPDMasked256", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "UInt8", typ: "Vec256"}, + {name: "VRNDSCALEPDMasked512", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "UInt8", typ: "Vec512"}, + {name: "VRNDSCALEPS128", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "UInt8", typ: "Vec128"}, + {name: "VRNDSCALEPS256", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "UInt8", typ: "Vec256"}, + {name: "VRNDSCALEPS512", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "UInt8", typ: "Vec512"}, + {name: "VRNDSCALEPSMasked128", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "UInt8", typ: "Vec128"}, + {name: "VRNDSCALEPSMasked256", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "UInt8", typ: "Vec256"}, + {name: "VRNDSCALEPSMasked512", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "UInt8", typ: "Vec512"}, + {name: "VROUNDPD128", argLength: 1, reg: v11, asm: "VROUNDPD", aux: "UInt8", typ: "Vec128"}, + {name: "VROUNDPD256", argLength: 1, reg: v11, asm: "VROUNDPD", aux: "UInt8", typ: "Vec256"}, + {name: "VROUNDPS128", argLength: 1, reg: v11, asm: "VROUNDPS", aux: "UInt8", typ: "Vec128"}, + {name: "VROUNDPS256", argLength: 1, reg: v11, asm: "VROUNDPS", aux: "UInt8", typ: "Vec256"}, + {name: "VSHUFPD128", argLength: 2, reg: v21, asm: "VSHUFPD", aux: "UInt8", typ: "Vec128"}, + {name: "VSHUFPD256", argLength: 2, reg: v21, asm: "VSHUFPD", aux: "UInt8", typ: "Vec256"}, + {name: "VSHUFPD512", argLength: 2, reg: w21, asm: "VSHUFPD", aux: "UInt8", typ: "Vec512"}, + {name: "VSHUFPS128", argLength: 2, reg: v21, asm: "VSHUFPS", aux: "UInt8", typ: "Vec128"}, + {name: "VSHUFPS256", argLength: 2, reg: v21, asm: "VSHUFPS", aux: "UInt8", typ: "Vec256"}, + {name: "VSHUFPS512", argLength: 2, reg: w21, asm: "VSHUFPS", aux: "UInt8", typ: "Vec512"}, + {name: "VADDPD128load", argLength: 3, reg: v21load, asm: "VADDPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPD256load", argLength: 3, reg: v21load, asm: "VADDPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPD512load", argLength: 3, reg: w21load, asm: "VADDPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPDMasked128load", argLength: 4, reg: w2kwload, asm: "VADDPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPDMasked256load", argLength: 4, reg: w2kwload, asm: "VADDPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPDMasked512load", argLength: 4, reg: w2kwload, asm: "VADDPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPS128load", argLength: 3, reg: v21load, asm: "VADDPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPS256load", argLength: 3, reg: v21load, asm: "VADDPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPS512load", argLength: 3, reg: w21load, asm: "VADDPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPSMasked128load", argLength: 4, reg: w2kwload, asm: "VADDPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPSMasked256load", argLength: 4, reg: w2kwload, asm: "VADDPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VADDPSMasked512load", argLength: 4, reg: w2kwload, asm: "VADDPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VADDSUBPD128load", argLength: 3, reg: v21load, asm: "VADDSUBPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VADDSUBPD256load", argLength: 3, reg: v21load, asm: "VADDSUBPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VADDSUBPS128load", argLength: 3, reg: v21load, asm: "VADDSUBPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VADDSUBPS256load", argLength: 3, reg: v21load, asm: "VADDSUBPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VAESDEC128load", argLength: 3, reg: v21load, asm: "VAESDEC", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VAESDEC256load", argLength: 3, reg: v21load, asm: "VAESDEC", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VAESDECLAST128load", argLength: 3, reg: v21load, asm: "VAESDECLAST", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VAESDECLAST256load", argLength: 3, reg: v21load, asm: "VAESDECLAST", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VAESENC128load", argLength: 3, reg: v21load, asm: "VAESENC", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VAESENC256load", argLength: 3, reg: v21load, asm: "VAESENC", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VAESENCLAST128load", argLength: 3, reg: v21load, asm: "VAESENCLAST", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VAESENCLAST256load", argLength: 3, reg: v21load, asm: "VAESENCLAST", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VAESIMC128load", argLength: 2, reg: v11load, asm: "VAESIMC", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VBROADCASTSD256load", argLength: 2, reg: v11load, asm: "VBROADCASTSD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VBROADCASTSD512load", argLength: 2, reg: w11load, asm: "VBROADCASTSD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VBROADCASTSDMasked256load", argLength: 3, reg: wkwload, asm: "VBROADCASTSD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VBROADCASTSDMasked512load", argLength: 3, reg: wkwload, asm: "VBROADCASTSD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VBROADCASTSS128load", argLength: 2, reg: v11load, asm: "VBROADCASTSS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VBROADCASTSS256load", argLength: 2, reg: v11load, asm: "VBROADCASTSS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VBROADCASTSS512load", argLength: 2, reg: w11load, asm: "VBROADCASTSS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VBROADCASTSSMasked128load", argLength: 3, reg: wkwload, asm: "VBROADCASTSS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VBROADCASTSSMasked256load", argLength: 3, reg: wkwload, asm: "VBROADCASTSS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VBROADCASTSSMasked512load", argLength: 3, reg: wkwload, asm: "VBROADCASTSS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTDQ2PD256load", argLength: 2, reg: v11load, asm: "VCVTDQ2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTDQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTDQ2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTDQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTDQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTDQ2PS128load", argLength: 2, reg: v11load, asm: "VCVTDQ2PS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTDQ2PS256load", argLength: 2, reg: v11load, asm: "VCVTDQ2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTDQ2PS512load", argLength: 2, reg: w11load, asm: "VCVTDQ2PS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTDQ2PSMasked128load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTDQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTDQ2PSMasked512load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTPD2PS256load", argLength: 2, reg: w11load, asm: "VCVTPD2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTPD2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTPD2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTPD2PSX128load", argLength: 2, reg: v11load, asm: "VCVTPD2PSX", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTPD2PSXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTPD2PSX", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTPD2PSY128load", argLength: 2, reg: v11load, asm: "VCVTPD2PSY", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTPD2PSYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTPD2PSY", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTPS2PD256load", argLength: 2, reg: v11load, asm: "VCVTPS2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTPS2PD512load", argLength: 2, reg: w11load, asm: "VCVTPS2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTPS2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTPS2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTPS2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTPS2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PD128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PDMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTQQ2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PSX128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PSX", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PSXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PSX", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PSY128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PSY", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTQQ2PSYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PSY", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2DQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2DQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2DQX128load", argLength: 2, reg: v11load, asm: "VCVTTPD2DQX", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2DQXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQX", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2DQY128load", argLength: 2, reg: v11load, asm: "VCVTTPD2DQY", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2DQYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQY", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2QQ128load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2QQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2QQ512load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2QQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2QQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2QQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UDQX128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQX", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UDQXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQX", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UDQY128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQY", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UDQYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQY", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UQQ128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UQQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UQQ512load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UQQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UQQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPD2UQQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2DQ128load", argLength: 2, reg: v11load, asm: "VCVTTPS2DQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2DQ256load", argLength: 2, reg: v11load, asm: "VCVTTPS2DQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2DQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2DQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2DQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2DQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2QQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2QQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2QQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2QQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2QQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2QQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2QQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2QQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2UDQ128load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2UDQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2UDQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2UDQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2UQQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2UQQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2UQQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2UQQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2UQQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTTPS2UQQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUDQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUDQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUDQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUDQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUDQ2PS128load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUDQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUDQ2PS512load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUDQ2PSMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUDQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUDQ2PSMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PD128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PDMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PSX128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PSX", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PSXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PSX", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PSY128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PSY", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VCVTUQQ2PSYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PSY", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPD128load", argLength: 3, reg: v21load, asm: "VDIVPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPD256load", argLength: 3, reg: v21load, asm: "VDIVPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPD512load", argLength: 3, reg: w21load, asm: "VDIVPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPDMasked128load", argLength: 4, reg: w2kwload, asm: "VDIVPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPDMasked256load", argLength: 4, reg: w2kwload, asm: "VDIVPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPDMasked512load", argLength: 4, reg: w2kwload, asm: "VDIVPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPS128load", argLength: 3, reg: v21load, asm: "VDIVPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPS256load", argLength: 3, reg: v21load, asm: "VDIVPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPS512load", argLength: 3, reg: w21load, asm: "VDIVPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPSMasked128load", argLength: 4, reg: w2kwload, asm: "VDIVPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPSMasked256load", argLength: 4, reg: w2kwload, asm: "VDIVPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VDIVPSMasked512load", argLength: 4, reg: w2kwload, asm: "VDIVPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VEXPANDPDMasked128load", argLength: 3, reg: wkwload, asm: "VEXPANDPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VEXPANDPDMasked256load", argLength: 3, reg: wkwload, asm: "VEXPANDPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VEXPANDPSMasked128load", argLength: 3, reg: wkwload, asm: "VEXPANDPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VEXPANDPSMasked256load", argLength: 3, reg: wkwload, asm: "VEXPANDPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VFMADD213PD128load", argLength: 4, reg: v31load, asm: "VFMADD213PD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PD256load", argLength: 4, reg: v31load, asm: "VFMADD213PD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PD512load", argLength: 4, reg: w31load, asm: "VFMADD213PD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PDMasked128load", argLength: 5, reg: w3kwload, asm: "VFMADD213PD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PDMasked256load", argLength: 5, reg: w3kwload, asm: "VFMADD213PD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PDMasked512load", argLength: 5, reg: w3kwload, asm: "VFMADD213PD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PS128load", argLength: 4, reg: v31load, asm: "VFMADD213PS", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PS256load", argLength: 4, reg: v31load, asm: "VFMADD213PS", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PS512load", argLength: 4, reg: w31load, asm: "VFMADD213PS", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PSMasked128load", argLength: 5, reg: w3kwload, asm: "VFMADD213PS", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PSMasked256load", argLength: 5, reg: w3kwload, asm: "VFMADD213PS", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADD213PSMasked512load", argLength: 5, reg: w3kwload, asm: "VFMADD213PS", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PD128load", argLength: 4, reg: v31load, asm: "VFMADDSUB213PD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PD256load", argLength: 4, reg: v31load, asm: "VFMADDSUB213PD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PD512load", argLength: 4, reg: w31load, asm: "VFMADDSUB213PD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PDMasked128load", argLength: 5, reg: w3kwload, asm: "VFMADDSUB213PD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PDMasked256load", argLength: 5, reg: w3kwload, asm: "VFMADDSUB213PD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PDMasked512load", argLength: 5, reg: w3kwload, asm: "VFMADDSUB213PD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PS128load", argLength: 4, reg: v31load, asm: "VFMADDSUB213PS", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PS256load", argLength: 4, reg: v31load, asm: "VFMADDSUB213PS", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PS512load", argLength: 4, reg: w31load, asm: "VFMADDSUB213PS", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PSMasked128load", argLength: 5, reg: w3kwload, asm: "VFMADDSUB213PS", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PSMasked256load", argLength: 5, reg: w3kwload, asm: "VFMADDSUB213PS", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMADDSUB213PSMasked512load", argLength: 5, reg: w3kwload, asm: "VFMADDSUB213PS", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PD128load", argLength: 4, reg: v31load, asm: "VFMSUBADD213PD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PD256load", argLength: 4, reg: v31load, asm: "VFMSUBADD213PD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PD512load", argLength: 4, reg: w31load, asm: "VFMSUBADD213PD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PDMasked128load", argLength: 5, reg: w3kwload, asm: "VFMSUBADD213PD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PDMasked256load", argLength: 5, reg: w3kwload, asm: "VFMSUBADD213PD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PDMasked512load", argLength: 5, reg: w3kwload, asm: "VFMSUBADD213PD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PS128load", argLength: 4, reg: v31load, asm: "VFMSUBADD213PS", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PS256load", argLength: 4, reg: v31load, asm: "VFMSUBADD213PS", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PS512load", argLength: 4, reg: w31load, asm: "VFMSUBADD213PS", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PSMasked128load", argLength: 5, reg: w3kwload, asm: "VFMSUBADD213PS", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PSMasked256load", argLength: 5, reg: w3kwload, asm: "VFMSUBADD213PS", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VFMSUBADD213PSMasked512load", argLength: 5, reg: w3kwload, asm: "VFMSUBADD213PS", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VGF2P8MULB128load", argLength: 3, reg: w21load, asm: "VGF2P8MULB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VGF2P8MULB256load", argLength: 3, reg: w21load, asm: "VGF2P8MULB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VGF2P8MULBMasked128load", argLength: 4, reg: w2kwload, asm: "VGF2P8MULB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VGF2P8MULBMasked256load", argLength: 4, reg: w2kwload, asm: "VGF2P8MULB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VHADDPD128load", argLength: 3, reg: v21load, asm: "VHADDPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VHADDPD256load", argLength: 3, reg: v21load, asm: "VHADDPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VHADDPS128load", argLength: 3, reg: v21load, asm: "VHADDPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VHADDPS256load", argLength: 3, reg: v21load, asm: "VHADDPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VHSUBPD128load", argLength: 3, reg: v21load, asm: "VHSUBPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VHSUBPD256load", argLength: 3, reg: v21load, asm: "VHSUBPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VHSUBPS128load", argLength: 3, reg: v21load, asm: "VHSUBPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VHSUBPS256load", argLength: 3, reg: v21load, asm: "VHSUBPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPD128load", argLength: 3, reg: v21load, asm: "VMAXPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPD256load", argLength: 3, reg: v21load, asm: "VMAXPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPD512load", argLength: 3, reg: w21load, asm: "VMAXPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPDMasked128load", argLength: 4, reg: w2kwload, asm: "VMAXPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPDMasked256load", argLength: 4, reg: w2kwload, asm: "VMAXPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPDMasked512load", argLength: 4, reg: w2kwload, asm: "VMAXPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPS128load", argLength: 3, reg: v21load, asm: "VMAXPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPS256load", argLength: 3, reg: v21load, asm: "VMAXPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPS512load", argLength: 3, reg: w21load, asm: "VMAXPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPSMasked128load", argLength: 4, reg: w2kwload, asm: "VMAXPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPSMasked256load", argLength: 4, reg: w2kwload, asm: "VMAXPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMAXPSMasked512load", argLength: 4, reg: w2kwload, asm: "VMAXPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPD128load", argLength: 3, reg: v21load, asm: "VMINPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPD256load", argLength: 3, reg: v21load, asm: "VMINPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPD512load", argLength: 3, reg: w21load, asm: "VMINPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPDMasked128load", argLength: 4, reg: w2kwload, asm: "VMINPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPDMasked256load", argLength: 4, reg: w2kwload, asm: "VMINPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPDMasked512load", argLength: 4, reg: w2kwload, asm: "VMINPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPS128load", argLength: 3, reg: v21load, asm: "VMINPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPS256load", argLength: 3, reg: v21load, asm: "VMINPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPS512load", argLength: 3, reg: w21load, asm: "VMINPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPSMasked128load", argLength: 4, reg: w2kwload, asm: "VMINPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPSMasked256load", argLength: 4, reg: w2kwload, asm: "VMINPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMINPSMasked512load", argLength: 4, reg: w2kwload, asm: "VMINPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPD128load", argLength: 3, reg: v21load, asm: "VMULPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPD256load", argLength: 3, reg: v21load, asm: "VMULPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPD512load", argLength: 3, reg: w21load, asm: "VMULPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPDMasked128load", argLength: 4, reg: w2kwload, asm: "VMULPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPDMasked256load", argLength: 4, reg: w2kwload, asm: "VMULPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPDMasked512load", argLength: 4, reg: w2kwload, asm: "VMULPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPS128load", argLength: 3, reg: v21load, asm: "VMULPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPS256load", argLength: 3, reg: v21load, asm: "VMULPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPS512load", argLength: 3, reg: w21load, asm: "VMULPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPSMasked128load", argLength: 4, reg: w2kwload, asm: "VMULPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPSMasked256load", argLength: 4, reg: w2kwload, asm: "VMULPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VMULPSMasked512load", argLength: 4, reg: w2kwload, asm: "VMULPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSB128load", argLength: 2, reg: v11load, asm: "VPABSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSB256load", argLength: 2, reg: v11load, asm: "VPABSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSBMasked128load", argLength: 3, reg: wkwload, asm: "VPABSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSBMasked256load", argLength: 3, reg: wkwload, asm: "VPABSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSD128load", argLength: 2, reg: v11load, asm: "VPABSD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSD256load", argLength: 2, reg: v11load, asm: "VPABSD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSD512load", argLength: 2, reg: w11load, asm: "VPABSD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSDMasked128load", argLength: 3, reg: wkwload, asm: "VPABSD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSDMasked256load", argLength: 3, reg: wkwload, asm: "VPABSD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSDMasked512load", argLength: 3, reg: wkwload, asm: "VPABSD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSQ128load", argLength: 2, reg: w11load, asm: "VPABSQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSQ256load", argLength: 2, reg: w11load, asm: "VPABSQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSQ512load", argLength: 2, reg: w11load, asm: "VPABSQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSQMasked128load", argLength: 3, reg: wkwload, asm: "VPABSQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSQMasked256load", argLength: 3, reg: wkwload, asm: "VPABSQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSQMasked512load", argLength: 3, reg: wkwload, asm: "VPABSQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSW128load", argLength: 2, reg: v11load, asm: "VPABSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSW256load", argLength: 2, reg: v11load, asm: "VPABSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSWMasked128load", argLength: 3, reg: wkwload, asm: "VPABSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPABSWMasked256load", argLength: 3, reg: wkwload, asm: "VPABSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKSSDW128load", argLength: 3, reg: v21load, asm: "VPACKSSDW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKSSDW256load", argLength: 3, reg: v21load, asm: "VPACKSSDW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKSSDW512load", argLength: 3, reg: w21load, asm: "VPACKSSDW", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKSSDWMasked128load", argLength: 4, reg: w2kwload, asm: "VPACKSSDW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKSSDWMasked256load", argLength: 4, reg: w2kwload, asm: "VPACKSSDW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKSSDWMasked512load", argLength: 4, reg: w2kwload, asm: "VPACKSSDW", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKUSDW128load", argLength: 3, reg: v21load, asm: "VPACKUSDW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKUSDW256load", argLength: 3, reg: v21load, asm: "VPACKUSDW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKUSDW512load", argLength: 3, reg: w21load, asm: "VPACKUSDW", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKUSDWMasked128load", argLength: 4, reg: w2kwload, asm: "VPACKUSDW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKUSDWMasked256load", argLength: 4, reg: w2kwload, asm: "VPACKUSDW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPACKUSDWMasked512load", argLength: 4, reg: w2kwload, asm: "VPACKUSDW", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDB128load", argLength: 3, reg: v21load, asm: "VPADDB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDB256load", argLength: 3, reg: v21load, asm: "VPADDB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDBMasked128load", argLength: 4, reg: w2kwload, asm: "VPADDB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDBMasked256load", argLength: 4, reg: w2kwload, asm: "VPADDB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDD128load", argLength: 3, reg: v21load, asm: "VPADDD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDD256load", argLength: 3, reg: v21load, asm: "VPADDD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDD512load", argLength: 3, reg: w21load, asm: "VPADDD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDDMasked128load", argLength: 4, reg: w2kwload, asm: "VPADDD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDDMasked256load", argLength: 4, reg: w2kwload, asm: "VPADDD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDDMasked512load", argLength: 4, reg: w2kwload, asm: "VPADDD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDQ128load", argLength: 3, reg: v21load, asm: "VPADDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDQ256load", argLength: 3, reg: v21load, asm: "VPADDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDQ512load", argLength: 3, reg: w21load, asm: "VPADDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDQMasked128load", argLength: 4, reg: w2kwload, asm: "VPADDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDQMasked256load", argLength: 4, reg: w2kwload, asm: "VPADDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDQMasked512load", argLength: 4, reg: w2kwload, asm: "VPADDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDSB128load", argLength: 3, reg: v21load, asm: "VPADDSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDSB256load", argLength: 3, reg: v21load, asm: "VPADDSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDSBMasked128load", argLength: 4, reg: w2kwload, asm: "VPADDSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDSBMasked256load", argLength: 4, reg: w2kwload, asm: "VPADDSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDSW128load", argLength: 3, reg: v21load, asm: "VPADDSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDSW256load", argLength: 3, reg: v21load, asm: "VPADDSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDSWMasked128load", argLength: 4, reg: w2kwload, asm: "VPADDSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDSWMasked256load", argLength: 4, reg: w2kwload, asm: "VPADDSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDUSB128load", argLength: 3, reg: v21load, asm: "VPADDUSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDUSB256load", argLength: 3, reg: v21load, asm: "VPADDUSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDUSBMasked128load", argLength: 4, reg: w2kwload, asm: "VPADDUSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDUSBMasked256load", argLength: 4, reg: w2kwload, asm: "VPADDUSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDUSW128load", argLength: 3, reg: v21load, asm: "VPADDUSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDUSW256load", argLength: 3, reg: v21load, asm: "VPADDUSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDUSWMasked128load", argLength: 4, reg: w2kwload, asm: "VPADDUSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDUSWMasked256load", argLength: 4, reg: w2kwload, asm: "VPADDUSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDW128load", argLength: 3, reg: v21load, asm: "VPADDW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDW256load", argLength: 3, reg: v21load, asm: "VPADDW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDWMasked128load", argLength: 4, reg: w2kwload, asm: "VPADDW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPADDWMasked256load", argLength: 4, reg: w2kwload, asm: "VPADDW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPAND128load", argLength: 3, reg: v21load, asm: "VPAND", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPAND256load", argLength: 3, reg: v21load, asm: "VPAND", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDD512load", argLength: 3, reg: w21load, asm: "VPANDD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDDMasked128load", argLength: 4, reg: w2kwload, asm: "VPANDD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDDMasked256load", argLength: 4, reg: w2kwload, asm: "VPANDD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDDMasked512load", argLength: 4, reg: w2kwload, asm: "VPANDD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDN128load", argLength: 3, reg: v21load, asm: "VPANDN", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDN256load", argLength: 3, reg: v21load, asm: "VPANDN", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDND512load", argLength: 3, reg: w21load, asm: "VPANDND", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDNDMasked128load", argLength: 4, reg: w2kwload, asm: "VPANDND", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDNDMasked256load", argLength: 4, reg: w2kwload, asm: "VPANDND", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDNDMasked512load", argLength: 4, reg: w2kwload, asm: "VPANDND", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDNQ512load", argLength: 3, reg: w21load, asm: "VPANDNQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDNQMasked128load", argLength: 4, reg: w2kwload, asm: "VPANDNQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDNQMasked256load", argLength: 4, reg: w2kwload, asm: "VPANDNQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDNQMasked512load", argLength: 4, reg: w2kwload, asm: "VPANDNQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDQ512load", argLength: 3, reg: w21load, asm: "VPANDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDQMasked128load", argLength: 4, reg: w2kwload, asm: "VPANDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDQMasked256load", argLength: 4, reg: w2kwload, asm: "VPANDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPANDQMasked512load", argLength: 4, reg: w2kwload, asm: "VPANDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPAVGB128load", argLength: 3, reg: v21load, asm: "VPAVGB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPAVGB256load", argLength: 3, reg: v21load, asm: "VPAVGB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPAVGBMasked128load", argLength: 4, reg: w2kwload, asm: "VPAVGB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPAVGBMasked256load", argLength: 4, reg: w2kwload, asm: "VPAVGB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPAVGW128load", argLength: 3, reg: v21load, asm: "VPAVGW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPAVGW256load", argLength: 3, reg: v21load, asm: "VPAVGW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPAVGWMasked128load", argLength: 4, reg: w2kwload, asm: "VPAVGW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPAVGWMasked256load", argLength: 4, reg: w2kwload, asm: "VPAVGW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPBLENDMDMasked512load", argLength: 4, reg: w2kwload, asm: "VPBLENDMD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPBLENDMQMasked512load", argLength: 4, reg: w2kwload, asm: "VPBLENDMQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTB128load", argLength: 2, reg: v11load, asm: "VPBROADCASTB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTB256load", argLength: 2, reg: v11load, asm: "VPBROADCASTB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTB512load", argLength: 2, reg: w11load, asm: "VPBROADCASTB", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTBMasked128load", argLength: 3, reg: wkwload, asm: "VPBROADCASTB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTBMasked256load", argLength: 3, reg: wkwload, asm: "VPBROADCASTB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTBMasked512load", argLength: 3, reg: wkwload, asm: "VPBROADCASTB", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTD128load", argLength: 2, reg: v11load, asm: "VPBROADCASTD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTD256load", argLength: 2, reg: v11load, asm: "VPBROADCASTD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTD512load", argLength: 2, reg: w11load, asm: "VPBROADCASTD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTDMasked128load", argLength: 3, reg: wkwload, asm: "VPBROADCASTD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTDMasked256load", argLength: 3, reg: wkwload, asm: "VPBROADCASTD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTDMasked512load", argLength: 3, reg: wkwload, asm: "VPBROADCASTD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTQ128load", argLength: 2, reg: v11load, asm: "VPBROADCASTQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTQ256load", argLength: 2, reg: v11load, asm: "VPBROADCASTQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTQ512load", argLength: 2, reg: w11load, asm: "VPBROADCASTQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTQMasked128load", argLength: 3, reg: wkwload, asm: "VPBROADCASTQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTQMasked256load", argLength: 3, reg: wkwload, asm: "VPBROADCASTQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTQMasked512load", argLength: 3, reg: wkwload, asm: "VPBROADCASTQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTW128load", argLength: 2, reg: v11load, asm: "VPBROADCASTW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPBROADCASTW256load", argLength: 2, reg: v11load, asm: "VPBROADCASTW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPEQB128load", argLength: 3, reg: v21load, asm: "VPCMPEQB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPEQB256load", argLength: 3, reg: v21load, asm: "VPCMPEQB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPEQD128load", argLength: 3, reg: v21load, asm: "VPCMPEQD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPEQD256load", argLength: 3, reg: v21load, asm: "VPCMPEQD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPEQD512load", argLength: 3, reg: w2kload, asm: "VPCMPEQD", typ: "Mask", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPEQQ128load", argLength: 3, reg: v21load, asm: "VPCMPEQQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPEQQ256load", argLength: 3, reg: v21load, asm: "VPCMPEQQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPEQQ512load", argLength: 3, reg: w2kload, asm: "VPCMPEQQ", typ: "Mask", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPEQW128load", argLength: 3, reg: v21load, asm: "VPCMPEQW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPEQW256load", argLength: 3, reg: v21load, asm: "VPCMPEQW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPGTB128load", argLength: 3, reg: v21load, asm: "VPCMPGTB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPGTB256load", argLength: 3, reg: v21load, asm: "VPCMPGTB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPGTD128load", argLength: 3, reg: v21load, asm: "VPCMPGTD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPGTD256load", argLength: 3, reg: v21load, asm: "VPCMPGTD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPGTD512load", argLength: 3, reg: w2kload, asm: "VPCMPGTD", typ: "Mask", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPGTQ128load", argLength: 3, reg: v21load, asm: "VPCMPGTQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPGTQ256load", argLength: 3, reg: v21load, asm: "VPCMPGTQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPGTQ512load", argLength: 3, reg: w2kload, asm: "VPCMPGTQ", typ: "Mask", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPGTW128load", argLength: 3, reg: v21load, asm: "VPCMPGTW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPCMPGTW256load", argLength: 3, reg: v21load, asm: "VPCMPGTW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPDPWSSD128load", argLength: 4, reg: v31load, asm: "VPDPWSSD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPDPWSSD256load", argLength: 4, reg: v31load, asm: "VPDPWSSD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPDPWSSD512load", argLength: 4, reg: w31load, asm: "VPDPWSSD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPDPWSSDMasked128load", argLength: 5, reg: w3kwload, asm: "VPDPWSSD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPDPWSSDMasked256load", argLength: 5, reg: w3kwload, asm: "VPDPWSSD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPDPWSSDMasked512load", argLength: 5, reg: w3kwload, asm: "VPDPWSSD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMB128load", argLength: 3, reg: w21load, asm: "VPERMB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMB256load", argLength: 3, reg: w21load, asm: "VPERMB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMBMasked128load", argLength: 4, reg: w2kwload, asm: "VPERMB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMBMasked256load", argLength: 4, reg: w2kwload, asm: "VPERMB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMD256load", argLength: 3, reg: v21load, asm: "VPERMD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMD512load", argLength: 3, reg: w21load, asm: "VPERMD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMDMasked256load", argLength: 4, reg: w2kwload, asm: "VPERMD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMDMasked512load", argLength: 4, reg: w2kwload, asm: "VPERMD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMI2B128load", argLength: 4, reg: w31load, asm: "VPERMI2B", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2B256load", argLength: 4, reg: w31load, asm: "VPERMI2B", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2BMasked128load", argLength: 5, reg: w3kwload, asm: "VPERMI2B", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2BMasked256load", argLength: 5, reg: w3kwload, asm: "VPERMI2B", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2D128load", argLength: 4, reg: w31load, asm: "VPERMI2D", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2D256load", argLength: 4, reg: w31load, asm: "VPERMI2D", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2D512load", argLength: 4, reg: w31load, asm: "VPERMI2D", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2DMasked128load", argLength: 5, reg: w3kwload, asm: "VPERMI2D", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2DMasked256load", argLength: 5, reg: w3kwload, asm: "VPERMI2D", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2DMasked512load", argLength: 5, reg: w3kwload, asm: "VPERMI2D", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PD128load", argLength: 4, reg: w31load, asm: "VPERMI2PD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PD256load", argLength: 4, reg: w31load, asm: "VPERMI2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PD512load", argLength: 4, reg: w31load, asm: "VPERMI2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PDMasked128load", argLength: 5, reg: w3kwload, asm: "VPERMI2PD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PDMasked256load", argLength: 5, reg: w3kwload, asm: "VPERMI2PD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PDMasked512load", argLength: 5, reg: w3kwload, asm: "VPERMI2PD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PS128load", argLength: 4, reg: w31load, asm: "VPERMI2PS", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PS256load", argLength: 4, reg: w31load, asm: "VPERMI2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PS512load", argLength: 4, reg: w31load, asm: "VPERMI2PS", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PSMasked128load", argLength: 5, reg: w3kwload, asm: "VPERMI2PS", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PSMasked256load", argLength: 5, reg: w3kwload, asm: "VPERMI2PS", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2PSMasked512load", argLength: 5, reg: w3kwload, asm: "VPERMI2PS", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2Q128load", argLength: 4, reg: w31load, asm: "VPERMI2Q", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2Q256load", argLength: 4, reg: w31load, asm: "VPERMI2Q", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2Q512load", argLength: 4, reg: w31load, asm: "VPERMI2Q", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2QMasked128load", argLength: 5, reg: w3kwload, asm: "VPERMI2Q", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2QMasked256load", argLength: 5, reg: w3kwload, asm: "VPERMI2Q", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2QMasked512load", argLength: 5, reg: w3kwload, asm: "VPERMI2Q", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2W128load", argLength: 4, reg: w31load, asm: "VPERMI2W", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2W256load", argLength: 4, reg: w31load, asm: "VPERMI2W", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2WMasked128load", argLength: 5, reg: w3kwload, asm: "VPERMI2W", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMI2WMasked256load", argLength: 5, reg: w3kwload, asm: "VPERMI2W", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPERMPD256load", argLength: 3, reg: w21load, asm: "VPERMPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMPD512load", argLength: 3, reg: w21load, asm: "VPERMPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMPDMasked256load", argLength: 4, reg: w2kwload, asm: "VPERMPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMPDMasked512load", argLength: 4, reg: w2kwload, asm: "VPERMPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMPS256load", argLength: 3, reg: v21load, asm: "VPERMPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMPS512load", argLength: 3, reg: w21load, asm: "VPERMPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMPSMasked256load", argLength: 4, reg: w2kwload, asm: "VPERMPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMPSMasked512load", argLength: 4, reg: w2kwload, asm: "VPERMPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMQ256load", argLength: 3, reg: w21load, asm: "VPERMQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMQ512load", argLength: 3, reg: w21load, asm: "VPERMQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMQMasked256load", argLength: 4, reg: w2kwload, asm: "VPERMQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMQMasked512load", argLength: 4, reg: w2kwload, asm: "VPERMQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMW128load", argLength: 3, reg: w21load, asm: "VPERMW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMW256load", argLength: 3, reg: w21load, asm: "VPERMW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMWMasked128load", argLength: 4, reg: w2kwload, asm: "VPERMW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPERMWMasked256load", argLength: 4, reg: w2kwload, asm: "VPERMW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPEXPANDBMasked128load", argLength: 3, reg: wkwload, asm: "VPEXPANDB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPEXPANDBMasked256load", argLength: 3, reg: wkwload, asm: "VPEXPANDB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPEXPANDDMasked128load", argLength: 3, reg: wkwload, asm: "VPEXPANDD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPEXPANDDMasked256load", argLength: 3, reg: wkwload, asm: "VPEXPANDD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPEXPANDQMasked128load", argLength: 3, reg: wkwload, asm: "VPEXPANDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPEXPANDQMasked256load", argLength: 3, reg: wkwload, asm: "VPEXPANDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPEXPANDWMasked128load", argLength: 3, reg: wkwload, asm: "VPEXPANDW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPEXPANDWMasked256load", argLength: 3, reg: wkwload, asm: "VPEXPANDW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPHADDD128load", argLength: 3, reg: v21load, asm: "VPHADDD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPHADDD256load", argLength: 3, reg: v21load, asm: "VPHADDD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPHADDSW128load", argLength: 3, reg: v21load, asm: "VPHADDSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPHADDSW256load", argLength: 3, reg: v21load, asm: "VPHADDSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPHADDW128load", argLength: 3, reg: v21load, asm: "VPHADDW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPHADDW256load", argLength: 3, reg: v21load, asm: "VPHADDW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPHSUBD128load", argLength: 3, reg: v21load, asm: "VPHSUBD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPHSUBD256load", argLength: 3, reg: v21load, asm: "VPHSUBD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPHSUBSW128load", argLength: 3, reg: v21load, asm: "VPHSUBSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPHSUBSW256load", argLength: 3, reg: v21load, asm: "VPHSUBSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPHSUBW128load", argLength: 3, reg: v21load, asm: "VPHSUBW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPHSUBW256load", argLength: 3, reg: v21load, asm: "VPHSUBW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTD128load", argLength: 2, reg: w11load, asm: "VPLZCNTD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTD256load", argLength: 2, reg: w11load, asm: "VPLZCNTD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTD512load", argLength: 2, reg: w11load, asm: "VPLZCNTD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTDMasked128load", argLength: 3, reg: wkwload, asm: "VPLZCNTD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTDMasked256load", argLength: 3, reg: wkwload, asm: "VPLZCNTD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTDMasked512load", argLength: 3, reg: wkwload, asm: "VPLZCNTD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTQ128load", argLength: 2, reg: w11load, asm: "VPLZCNTQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTQ256load", argLength: 2, reg: w11load, asm: "VPLZCNTQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTQ512load", argLength: 2, reg: w11load, asm: "VPLZCNTQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTQMasked128load", argLength: 3, reg: wkwload, asm: "VPLZCNTQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTQMasked256load", argLength: 3, reg: wkwload, asm: "VPLZCNTQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPLZCNTQMasked512load", argLength: 3, reg: wkwload, asm: "VPLZCNTQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMADDUBSW128load", argLength: 3, reg: v21load, asm: "VPMADDUBSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMADDUBSW256load", argLength: 3, reg: v21load, asm: "VPMADDUBSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMADDUBSWMasked128load", argLength: 4, reg: w2kwload, asm: "VPMADDUBSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMADDUBSWMasked256load", argLength: 4, reg: w2kwload, asm: "VPMADDUBSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMADDWD128load", argLength: 3, reg: v21load, asm: "VPMADDWD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMADDWD256load", argLength: 3, reg: v21load, asm: "VPMADDWD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMADDWDMasked128load", argLength: 4, reg: w2kwload, asm: "VPMADDWD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMADDWDMasked256load", argLength: 4, reg: w2kwload, asm: "VPMADDWD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSB128load", argLength: 3, reg: v21load, asm: "VPMAXSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSB256load", argLength: 3, reg: v21load, asm: "VPMAXSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSBMasked128load", argLength: 4, reg: w2kwload, asm: "VPMAXSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSBMasked256load", argLength: 4, reg: w2kwload, asm: "VPMAXSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSD128load", argLength: 3, reg: v21load, asm: "VPMAXSD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSD256load", argLength: 3, reg: v21load, asm: "VPMAXSD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSD512load", argLength: 3, reg: w21load, asm: "VPMAXSD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSDMasked128load", argLength: 4, reg: w2kwload, asm: "VPMAXSD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSDMasked256load", argLength: 4, reg: w2kwload, asm: "VPMAXSD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSDMasked512load", argLength: 4, reg: w2kwload, asm: "VPMAXSD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSQ128load", argLength: 3, reg: w21load, asm: "VPMAXSQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSQ256load", argLength: 3, reg: w21load, asm: "VPMAXSQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSQ512load", argLength: 3, reg: w21load, asm: "VPMAXSQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSQMasked128load", argLength: 4, reg: w2kwload, asm: "VPMAXSQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSQMasked256load", argLength: 4, reg: w2kwload, asm: "VPMAXSQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSQMasked512load", argLength: 4, reg: w2kwload, asm: "VPMAXSQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSW128load", argLength: 3, reg: v21load, asm: "VPMAXSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSW256load", argLength: 3, reg: v21load, asm: "VPMAXSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSWMasked128load", argLength: 4, reg: w2kwload, asm: "VPMAXSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXSWMasked256load", argLength: 4, reg: w2kwload, asm: "VPMAXSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUB128load", argLength: 3, reg: v21load, asm: "VPMAXUB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUB256load", argLength: 3, reg: v21load, asm: "VPMAXUB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUBMasked128load", argLength: 4, reg: w2kwload, asm: "VPMAXUB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUBMasked256load", argLength: 4, reg: w2kwload, asm: "VPMAXUB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUD128load", argLength: 3, reg: v21load, asm: "VPMAXUD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUD256load", argLength: 3, reg: v21load, asm: "VPMAXUD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUD512load", argLength: 3, reg: w21load, asm: "VPMAXUD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUDMasked128load", argLength: 4, reg: w2kwload, asm: "VPMAXUD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUDMasked256load", argLength: 4, reg: w2kwload, asm: "VPMAXUD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUDMasked512load", argLength: 4, reg: w2kwload, asm: "VPMAXUD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUQ128load", argLength: 3, reg: w21load, asm: "VPMAXUQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUQ256load", argLength: 3, reg: w21load, asm: "VPMAXUQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUQ512load", argLength: 3, reg: w21load, asm: "VPMAXUQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUQMasked128load", argLength: 4, reg: w2kwload, asm: "VPMAXUQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUQMasked256load", argLength: 4, reg: w2kwload, asm: "VPMAXUQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUQMasked512load", argLength: 4, reg: w2kwload, asm: "VPMAXUQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUW128load", argLength: 3, reg: v21load, asm: "VPMAXUW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUW256load", argLength: 3, reg: v21load, asm: "VPMAXUW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUWMasked128load", argLength: 4, reg: w2kwload, asm: "VPMAXUW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMAXUWMasked256load", argLength: 4, reg: w2kwload, asm: "VPMAXUW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSB128load", argLength: 3, reg: v21load, asm: "VPMINSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSB256load", argLength: 3, reg: v21load, asm: "VPMINSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSBMasked128load", argLength: 4, reg: w2kwload, asm: "VPMINSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSBMasked256load", argLength: 4, reg: w2kwload, asm: "VPMINSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSD128load", argLength: 3, reg: v21load, asm: "VPMINSD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSD256load", argLength: 3, reg: v21load, asm: "VPMINSD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSD512load", argLength: 3, reg: w21load, asm: "VPMINSD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSDMasked128load", argLength: 4, reg: w2kwload, asm: "VPMINSD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSDMasked256load", argLength: 4, reg: w2kwload, asm: "VPMINSD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSDMasked512load", argLength: 4, reg: w2kwload, asm: "VPMINSD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSQ128load", argLength: 3, reg: w21load, asm: "VPMINSQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSQ256load", argLength: 3, reg: w21load, asm: "VPMINSQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSQ512load", argLength: 3, reg: w21load, asm: "VPMINSQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSQMasked128load", argLength: 4, reg: w2kwload, asm: "VPMINSQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSQMasked256load", argLength: 4, reg: w2kwload, asm: "VPMINSQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSQMasked512load", argLength: 4, reg: w2kwload, asm: "VPMINSQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSW128load", argLength: 3, reg: v21load, asm: "VPMINSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSW256load", argLength: 3, reg: v21load, asm: "VPMINSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSWMasked128load", argLength: 4, reg: w2kwload, asm: "VPMINSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINSWMasked256load", argLength: 4, reg: w2kwload, asm: "VPMINSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUB128load", argLength: 3, reg: v21load, asm: "VPMINUB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUB256load", argLength: 3, reg: v21load, asm: "VPMINUB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUBMasked128load", argLength: 4, reg: w2kwload, asm: "VPMINUB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUBMasked256load", argLength: 4, reg: w2kwload, asm: "VPMINUB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUD128load", argLength: 3, reg: v21load, asm: "VPMINUD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUD256load", argLength: 3, reg: v21load, asm: "VPMINUD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUD512load", argLength: 3, reg: w21load, asm: "VPMINUD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUDMasked128load", argLength: 4, reg: w2kwload, asm: "VPMINUD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUDMasked256load", argLength: 4, reg: w2kwload, asm: "VPMINUD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUDMasked512load", argLength: 4, reg: w2kwload, asm: "VPMINUD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUQ128load", argLength: 3, reg: w21load, asm: "VPMINUQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUQ256load", argLength: 3, reg: w21load, asm: "VPMINUQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUQ512load", argLength: 3, reg: w21load, asm: "VPMINUQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUQMasked128load", argLength: 4, reg: w2kwload, asm: "VPMINUQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUQMasked256load", argLength: 4, reg: w2kwload, asm: "VPMINUQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUQMasked512load", argLength: 4, reg: w2kwload, asm: "VPMINUQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUW128load", argLength: 3, reg: v21load, asm: "VPMINUW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUW256load", argLength: 3, reg: v21load, asm: "VPMINUW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUWMasked128load", argLength: 4, reg: w2kwload, asm: "VPMINUW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMINUWMasked256load", argLength: 4, reg: w2kwload, asm: "VPMINUW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBD128load", argLength: 2, reg: v11load, asm: "VPMOVSXBD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBD256load", argLength: 2, reg: v11load, asm: "VPMOVSXBD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBD512load", argLength: 2, reg: w11load, asm: "VPMOVSXBD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBDMasked128load", argLength: 3, reg: wkwload, asm: "VPMOVSXBD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBDMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVSXBD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBDMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVSXBD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBQ128load", argLength: 2, reg: v11load, asm: "VPMOVSXBQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBQ256load", argLength: 2, reg: v11load, asm: "VPMOVSXBQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBQ512load", argLength: 2, reg: w11load, asm: "VPMOVSXBQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBQMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVSXBQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBQMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVSXBQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBW128load", argLength: 2, reg: v11load, asm: "VPMOVSXBW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBW256load", argLength: 2, reg: v11load, asm: "VPMOVSXBW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBW512load", argLength: 2, reg: w11load, asm: "VPMOVSXBW", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBWMasked128load", argLength: 3, reg: wkwload, asm: "VPMOVSXBW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBWMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVSXBW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXBWMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVSXBW", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXDQ128load", argLength: 2, reg: v11load, asm: "VPMOVSXDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXDQ256load", argLength: 2, reg: v11load, asm: "VPMOVSXDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXDQ512load", argLength: 2, reg: w11load, asm: "VPMOVSXDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXDQMasked128load", argLength: 3, reg: wkwload, asm: "VPMOVSXDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXDQMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVSXDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXDQMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVSXDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWD128load", argLength: 2, reg: v11load, asm: "VPMOVSXWD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWD256load", argLength: 2, reg: v11load, asm: "VPMOVSXWD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWD512load", argLength: 2, reg: w11load, asm: "VPMOVSXWD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWDMasked128load", argLength: 3, reg: wkwload, asm: "VPMOVSXWD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWDMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVSXWD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWDMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVSXWD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWQ128load", argLength: 2, reg: v11load, asm: "VPMOVSXWQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWQ256load", argLength: 2, reg: v11load, asm: "VPMOVSXWQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWQ512load", argLength: 2, reg: w11load, asm: "VPMOVSXWQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWQMasked128load", argLength: 3, reg: wkwload, asm: "VPMOVSXWQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWQMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVSXWQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVSXWQMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVSXWQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBD128load", argLength: 2, reg: v11load, asm: "VPMOVZXBD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBD256load", argLength: 2, reg: v11load, asm: "VPMOVZXBD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBD512load", argLength: 2, reg: w11load, asm: "VPMOVZXBD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBDMasked128load", argLength: 3, reg: wkwload, asm: "VPMOVZXBD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBDMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVZXBD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBDMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVZXBD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBQ128load", argLength: 2, reg: v11load, asm: "VPMOVZXBQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBQ256load", argLength: 2, reg: v11load, asm: "VPMOVZXBQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBQ512load", argLength: 2, reg: w11load, asm: "VPMOVZXBQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBQMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVZXBQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBQMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVZXBQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBW128load", argLength: 2, reg: v11load, asm: "VPMOVZXBW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBW256load", argLength: 2, reg: v11load, asm: "VPMOVZXBW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBW512load", argLength: 2, reg: w11load, asm: "VPMOVZXBW", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBWMasked128load", argLength: 3, reg: wkwload, asm: "VPMOVZXBW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBWMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVZXBW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXBWMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVZXBW", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXDQ128load", argLength: 2, reg: v11load, asm: "VPMOVZXDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXDQ256load", argLength: 2, reg: v11load, asm: "VPMOVZXDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXDQ512load", argLength: 2, reg: w11load, asm: "VPMOVZXDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXDQMasked128load", argLength: 3, reg: wkwload, asm: "VPMOVZXDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXDQMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVZXDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXDQMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVZXDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWD128load", argLength: 2, reg: v11load, asm: "VPMOVZXWD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWD256load", argLength: 2, reg: v11load, asm: "VPMOVZXWD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWD512load", argLength: 2, reg: w11load, asm: "VPMOVZXWD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWDMasked128load", argLength: 3, reg: wkwload, asm: "VPMOVZXWD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWDMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVZXWD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWDMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVZXWD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWQ128load", argLength: 2, reg: v11load, asm: "VPMOVZXWQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWQ256load", argLength: 2, reg: v11load, asm: "VPMOVZXWQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWQ512load", argLength: 2, reg: w11load, asm: "VPMOVZXWQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWQMasked128load", argLength: 3, reg: wkwload, asm: "VPMOVZXWQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWQMasked256load", argLength: 3, reg: wkwload, asm: "VPMOVZXWQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMOVZXWQMasked512load", argLength: 3, reg: wkwload, asm: "VPMOVZXWQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULDQ128load", argLength: 3, reg: v21load, asm: "VPMULDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULDQ256load", argLength: 3, reg: v21load, asm: "VPMULDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULHUW128load", argLength: 3, reg: v21load, asm: "VPMULHUW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULHUW256load", argLength: 3, reg: v21load, asm: "VPMULHUW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULHUWMasked128load", argLength: 4, reg: w2kwload, asm: "VPMULHUW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULHUWMasked256load", argLength: 4, reg: w2kwload, asm: "VPMULHUW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULHW128load", argLength: 3, reg: v21load, asm: "VPMULHW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULHW256load", argLength: 3, reg: v21load, asm: "VPMULHW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULHWMasked128load", argLength: 4, reg: w2kwload, asm: "VPMULHW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULHWMasked256load", argLength: 4, reg: w2kwload, asm: "VPMULHW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLD128load", argLength: 3, reg: v21load, asm: "VPMULLD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLD256load", argLength: 3, reg: v21load, asm: "VPMULLD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLD512load", argLength: 3, reg: w21load, asm: "VPMULLD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLDMasked128load", argLength: 4, reg: w2kwload, asm: "VPMULLD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLDMasked256load", argLength: 4, reg: w2kwload, asm: "VPMULLD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLDMasked512load", argLength: 4, reg: w2kwload, asm: "VPMULLD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLQ128load", argLength: 3, reg: w21load, asm: "VPMULLQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLQ256load", argLength: 3, reg: w21load, asm: "VPMULLQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLQ512load", argLength: 3, reg: w21load, asm: "VPMULLQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLQMasked128load", argLength: 4, reg: w2kwload, asm: "VPMULLQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLQMasked256load", argLength: 4, reg: w2kwload, asm: "VPMULLQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLQMasked512load", argLength: 4, reg: w2kwload, asm: "VPMULLQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLW128load", argLength: 3, reg: v21load, asm: "VPMULLW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLW256load", argLength: 3, reg: v21load, asm: "VPMULLW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLWMasked128load", argLength: 4, reg: w2kwload, asm: "VPMULLW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULLWMasked256load", argLength: 4, reg: w2kwload, asm: "VPMULLW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULUDQ128load", argLength: 3, reg: v21load, asm: "VPMULUDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPMULUDQ256load", argLength: 3, reg: v21load, asm: "VPMULUDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTB128load", argLength: 2, reg: w11load, asm: "VPOPCNTB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTB256load", argLength: 2, reg: w11load, asm: "VPOPCNTB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTBMasked128load", argLength: 3, reg: wkwload, asm: "VPOPCNTB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTBMasked256load", argLength: 3, reg: wkwload, asm: "VPOPCNTB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTD128load", argLength: 2, reg: w11load, asm: "VPOPCNTD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTD256load", argLength: 2, reg: w11load, asm: "VPOPCNTD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTD512load", argLength: 2, reg: w11load, asm: "VPOPCNTD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTDMasked128load", argLength: 3, reg: wkwload, asm: "VPOPCNTD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTDMasked256load", argLength: 3, reg: wkwload, asm: "VPOPCNTD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTDMasked512load", argLength: 3, reg: wkwload, asm: "VPOPCNTD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTQ128load", argLength: 2, reg: w11load, asm: "VPOPCNTQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTQ256load", argLength: 2, reg: w11load, asm: "VPOPCNTQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTQ512load", argLength: 2, reg: w11load, asm: "VPOPCNTQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTQMasked128load", argLength: 3, reg: wkwload, asm: "VPOPCNTQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTQMasked256load", argLength: 3, reg: wkwload, asm: "VPOPCNTQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTQMasked512load", argLength: 3, reg: wkwload, asm: "VPOPCNTQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTW128load", argLength: 2, reg: w11load, asm: "VPOPCNTW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTW256load", argLength: 2, reg: w11load, asm: "VPOPCNTW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTWMasked128load", argLength: 3, reg: wkwload, asm: "VPOPCNTW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPOPCNTWMasked256load", argLength: 3, reg: wkwload, asm: "VPOPCNTW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPOR128load", argLength: 3, reg: v21load, asm: "VPOR", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPOR256load", argLength: 3, reg: v21load, asm: "VPOR", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPORD512load", argLength: 3, reg: w21load, asm: "VPORD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPORDMasked128load", argLength: 4, reg: w2kwload, asm: "VPORD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPORDMasked256load", argLength: 4, reg: w2kwload, asm: "VPORD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPORDMasked512load", argLength: 4, reg: w2kwload, asm: "VPORD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPORQ512load", argLength: 3, reg: w21load, asm: "VPORQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPORQMasked128load", argLength: 4, reg: w2kwload, asm: "VPORQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPORQMasked256load", argLength: 4, reg: w2kwload, asm: "VPORQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPORQMasked512load", argLength: 4, reg: w2kwload, asm: "VPORQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVD128load", argLength: 3, reg: w21load, asm: "VPROLVD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVD256load", argLength: 3, reg: w21load, asm: "VPROLVD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVD512load", argLength: 3, reg: w21load, asm: "VPROLVD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVDMasked128load", argLength: 4, reg: w2kwload, asm: "VPROLVD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVDMasked256load", argLength: 4, reg: w2kwload, asm: "VPROLVD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVDMasked512load", argLength: 4, reg: w2kwload, asm: "VPROLVD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVQ128load", argLength: 3, reg: w21load, asm: "VPROLVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVQ256load", argLength: 3, reg: w21load, asm: "VPROLVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVQ512load", argLength: 3, reg: w21load, asm: "VPROLVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVQMasked128load", argLength: 4, reg: w2kwload, asm: "VPROLVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVQMasked256load", argLength: 4, reg: w2kwload, asm: "VPROLVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPROLVQMasked512load", argLength: 4, reg: w2kwload, asm: "VPROLVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVD128load", argLength: 3, reg: w21load, asm: "VPRORVD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVD256load", argLength: 3, reg: w21load, asm: "VPRORVD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVD512load", argLength: 3, reg: w21load, asm: "VPRORVD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVDMasked128load", argLength: 4, reg: w2kwload, asm: "VPRORVD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVDMasked256load", argLength: 4, reg: w2kwload, asm: "VPRORVD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVDMasked512load", argLength: 4, reg: w2kwload, asm: "VPRORVD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVQ128load", argLength: 3, reg: w21load, asm: "VPRORVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVQ256load", argLength: 3, reg: w21load, asm: "VPRORVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVQ512load", argLength: 3, reg: w21load, asm: "VPRORVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVQMasked128load", argLength: 4, reg: w2kwload, asm: "VPRORVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVQMasked256load", argLength: 4, reg: w2kwload, asm: "VPRORVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPRORVQMasked512load", argLength: 4, reg: w2kwload, asm: "VPRORVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSADBW128load", argLength: 3, reg: v21load, asm: "VPSADBW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSADBW256load", argLength: 3, reg: v21load, asm: "VPSADBW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSHLDVD128load", argLength: 4, reg: w31load, asm: "VPSHLDVD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVD256load", argLength: 4, reg: w31load, asm: "VPSHLDVD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVD512load", argLength: 4, reg: w31load, asm: "VPSHLDVD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVDMasked128load", argLength: 5, reg: w3kwload, asm: "VPSHLDVD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVDMasked256load", argLength: 5, reg: w3kwload, asm: "VPSHLDVD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVDMasked512load", argLength: 5, reg: w3kwload, asm: "VPSHLDVD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVQ128load", argLength: 4, reg: w31load, asm: "VPSHLDVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVQ256load", argLength: 4, reg: w31load, asm: "VPSHLDVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVQ512load", argLength: 4, reg: w31load, asm: "VPSHLDVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVQMasked128load", argLength: 5, reg: w3kwload, asm: "VPSHLDVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVQMasked256load", argLength: 5, reg: w3kwload, asm: "VPSHLDVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVQMasked512load", argLength: 5, reg: w3kwload, asm: "VPSHLDVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVW128load", argLength: 4, reg: w31load, asm: "VPSHLDVW", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVW256load", argLength: 4, reg: w31load, asm: "VPSHLDVW", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVWMasked128load", argLength: 5, reg: w3kwload, asm: "VPSHLDVW", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHLDVWMasked256load", argLength: 5, reg: w3kwload, asm: "VPSHLDVW", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVD128load", argLength: 4, reg: w31load, asm: "VPSHRDVD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVD256load", argLength: 4, reg: w31load, asm: "VPSHRDVD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVD512load", argLength: 4, reg: w31load, asm: "VPSHRDVD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVDMasked128load", argLength: 5, reg: w3kwload, asm: "VPSHRDVD", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVDMasked256load", argLength: 5, reg: w3kwload, asm: "VPSHRDVD", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVDMasked512load", argLength: 5, reg: w3kwload, asm: "VPSHRDVD", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVQ128load", argLength: 4, reg: w31load, asm: "VPSHRDVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVQ256load", argLength: 4, reg: w31load, asm: "VPSHRDVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVQ512load", argLength: 4, reg: w31load, asm: "VPSHRDVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVQMasked128load", argLength: 5, reg: w3kwload, asm: "VPSHRDVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVQMasked256load", argLength: 5, reg: w3kwload, asm: "VPSHRDVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVQMasked512load", argLength: 5, reg: w3kwload, asm: "VPSHRDVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVW128load", argLength: 4, reg: w31load, asm: "VPSHRDVW", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVW256load", argLength: 4, reg: w31load, asm: "VPSHRDVW", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVWMasked128load", argLength: 5, reg: w3kwload, asm: "VPSHRDVW", typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHRDVWMasked256load", argLength: 5, reg: w3kwload, asm: "VPSHRDVW", typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, + {name: "VPSHUFB128load", argLength: 3, reg: v21load, asm: "VPSHUFB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSHUFB256load", argLength: 3, reg: v21load, asm: "VPSHUFB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSHUFBMasked128load", argLength: 4, reg: w2kwload, asm: "VPSHUFB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSHUFBMasked256load", argLength: 4, reg: w2kwload, asm: "VPSHUFB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSIGNB128load", argLength: 3, reg: v21load, asm: "VPSIGNB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSIGNB256load", argLength: 3, reg: v21load, asm: "VPSIGNB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSIGND128load", argLength: 3, reg: v21load, asm: "VPSIGND", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSIGND256load", argLength: 3, reg: v21load, asm: "VPSIGND", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSIGNW128load", argLength: 3, reg: v21load, asm: "VPSIGNW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSIGNW256load", argLength: 3, reg: v21load, asm: "VPSIGNW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVD128load", argLength: 3, reg: v21load, asm: "VPSLLVD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVD256load", argLength: 3, reg: v21load, asm: "VPSLLVD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVD512load", argLength: 3, reg: w21load, asm: "VPSLLVD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVDMasked128load", argLength: 4, reg: w2kwload, asm: "VPSLLVD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVDMasked256load", argLength: 4, reg: w2kwload, asm: "VPSLLVD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVDMasked512load", argLength: 4, reg: w2kwload, asm: "VPSLLVD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVQ128load", argLength: 3, reg: v21load, asm: "VPSLLVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVQ256load", argLength: 3, reg: v21load, asm: "VPSLLVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVQ512load", argLength: 3, reg: w21load, asm: "VPSLLVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVQMasked128load", argLength: 4, reg: w2kwload, asm: "VPSLLVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVQMasked256load", argLength: 4, reg: w2kwload, asm: "VPSLLVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVQMasked512load", argLength: 4, reg: w2kwload, asm: "VPSLLVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVW128load", argLength: 3, reg: w21load, asm: "VPSLLVW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVW256load", argLength: 3, reg: w21load, asm: "VPSLLVW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVWMasked128load", argLength: 4, reg: w2kwload, asm: "VPSLLVW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSLLVWMasked256load", argLength: 4, reg: w2kwload, asm: "VPSLLVW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVD128load", argLength: 3, reg: v21load, asm: "VPSRAVD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVD256load", argLength: 3, reg: v21load, asm: "VPSRAVD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVD512load", argLength: 3, reg: w21load, asm: "VPSRAVD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVDMasked128load", argLength: 4, reg: w2kwload, asm: "VPSRAVD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVDMasked256load", argLength: 4, reg: w2kwload, asm: "VPSRAVD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVDMasked512load", argLength: 4, reg: w2kwload, asm: "VPSRAVD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVQ128load", argLength: 3, reg: w21load, asm: "VPSRAVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVQ256load", argLength: 3, reg: w21load, asm: "VPSRAVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVQ512load", argLength: 3, reg: w21load, asm: "VPSRAVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVQMasked128load", argLength: 4, reg: w2kwload, asm: "VPSRAVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVQMasked256load", argLength: 4, reg: w2kwload, asm: "VPSRAVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVQMasked512load", argLength: 4, reg: w2kwload, asm: "VPSRAVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVW128load", argLength: 3, reg: w21load, asm: "VPSRAVW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVW256load", argLength: 3, reg: w21load, asm: "VPSRAVW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVWMasked128load", argLength: 4, reg: w2kwload, asm: "VPSRAVW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRAVWMasked256load", argLength: 4, reg: w2kwload, asm: "VPSRAVW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVD128load", argLength: 3, reg: v21load, asm: "VPSRLVD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVD256load", argLength: 3, reg: v21load, asm: "VPSRLVD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVD512load", argLength: 3, reg: w21load, asm: "VPSRLVD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVDMasked128load", argLength: 4, reg: w2kwload, asm: "VPSRLVD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVDMasked256load", argLength: 4, reg: w2kwload, asm: "VPSRLVD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVDMasked512load", argLength: 4, reg: w2kwload, asm: "VPSRLVD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVQ128load", argLength: 3, reg: v21load, asm: "VPSRLVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVQ256load", argLength: 3, reg: v21load, asm: "VPSRLVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVQ512load", argLength: 3, reg: w21load, asm: "VPSRLVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVQMasked128load", argLength: 4, reg: w2kwload, asm: "VPSRLVQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVQMasked256load", argLength: 4, reg: w2kwload, asm: "VPSRLVQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVQMasked512load", argLength: 4, reg: w2kwload, asm: "VPSRLVQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVW128load", argLength: 3, reg: w21load, asm: "VPSRLVW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVW256load", argLength: 3, reg: w21load, asm: "VPSRLVW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVWMasked128load", argLength: 4, reg: w2kwload, asm: "VPSRLVW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSRLVWMasked256load", argLength: 4, reg: w2kwload, asm: "VPSRLVW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBB128load", argLength: 3, reg: v21load, asm: "VPSUBB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBB256load", argLength: 3, reg: v21load, asm: "VPSUBB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBBMasked128load", argLength: 4, reg: w2kwload, asm: "VPSUBB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBBMasked256load", argLength: 4, reg: w2kwload, asm: "VPSUBB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBD128load", argLength: 3, reg: v21load, asm: "VPSUBD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBD256load", argLength: 3, reg: v21load, asm: "VPSUBD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBD512load", argLength: 3, reg: w21load, asm: "VPSUBD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBDMasked128load", argLength: 4, reg: w2kwload, asm: "VPSUBD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBDMasked256load", argLength: 4, reg: w2kwload, asm: "VPSUBD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBDMasked512load", argLength: 4, reg: w2kwload, asm: "VPSUBD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBQ128load", argLength: 3, reg: v21load, asm: "VPSUBQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBQ256load", argLength: 3, reg: v21load, asm: "VPSUBQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBQ512load", argLength: 3, reg: w21load, asm: "VPSUBQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBQMasked128load", argLength: 4, reg: w2kwload, asm: "VPSUBQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBQMasked256load", argLength: 4, reg: w2kwload, asm: "VPSUBQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBQMasked512load", argLength: 4, reg: w2kwload, asm: "VPSUBQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBSB128load", argLength: 3, reg: v21load, asm: "VPSUBSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBSB256load", argLength: 3, reg: v21load, asm: "VPSUBSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBSBMasked128load", argLength: 4, reg: w2kwload, asm: "VPSUBSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBSBMasked256load", argLength: 4, reg: w2kwload, asm: "VPSUBSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBSW128load", argLength: 3, reg: v21load, asm: "VPSUBSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBSW256load", argLength: 3, reg: v21load, asm: "VPSUBSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBSWMasked128load", argLength: 4, reg: w2kwload, asm: "VPSUBSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBSWMasked256load", argLength: 4, reg: w2kwload, asm: "VPSUBSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBUSB128load", argLength: 3, reg: v21load, asm: "VPSUBUSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBUSB256load", argLength: 3, reg: v21load, asm: "VPSUBUSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBUSBMasked128load", argLength: 4, reg: w2kwload, asm: "VPSUBUSB", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBUSBMasked256load", argLength: 4, reg: w2kwload, asm: "VPSUBUSB", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBUSW128load", argLength: 3, reg: v21load, asm: "VPSUBUSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBUSW256load", argLength: 3, reg: v21load, asm: "VPSUBUSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBUSWMasked128load", argLength: 4, reg: w2kwload, asm: "VPSUBUSW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBUSWMasked256load", argLength: 4, reg: w2kwload, asm: "VPSUBUSW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBW128load", argLength: 3, reg: v21load, asm: "VPSUBW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBW256load", argLength: 3, reg: v21load, asm: "VPSUBW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBWMasked128load", argLength: 4, reg: w2kwload, asm: "VPSUBW", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPSUBWMasked256load", argLength: 4, reg: w2kwload, asm: "VPSUBW", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKHDQ128load", argLength: 3, reg: v21load, asm: "VPUNPCKHDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKHDQ256load", argLength: 3, reg: v21load, asm: "VPUNPCKHDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKHDQ512load", argLength: 3, reg: w21load, asm: "VPUNPCKHDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKHQDQ128load", argLength: 3, reg: v21load, asm: "VPUNPCKHQDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKHQDQ256load", argLength: 3, reg: v21load, asm: "VPUNPCKHQDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKHQDQ512load", argLength: 3, reg: w21load, asm: "VPUNPCKHQDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKHWD128load", argLength: 3, reg: v21load, asm: "VPUNPCKHWD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKHWD256load", argLength: 3, reg: v21load, asm: "VPUNPCKHWD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKLDQ128load", argLength: 3, reg: v21load, asm: "VPUNPCKLDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKLDQ256load", argLength: 3, reg: v21load, asm: "VPUNPCKLDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKLDQ512load", argLength: 3, reg: w21load, asm: "VPUNPCKLDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKLQDQ128load", argLength: 3, reg: v21load, asm: "VPUNPCKLQDQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKLQDQ256load", argLength: 3, reg: v21load, asm: "VPUNPCKLQDQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKLQDQ512load", argLength: 3, reg: w21load, asm: "VPUNPCKLQDQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKLWD128load", argLength: 3, reg: v21load, asm: "VPUNPCKLWD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPUNPCKLWD256load", argLength: 3, reg: v21load, asm: "VPUNPCKLWD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPXOR128load", argLength: 3, reg: v21load, asm: "VPXOR", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPXOR256load", argLength: 3, reg: v21load, asm: "VPXOR", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPXORD512load", argLength: 3, reg: w21load, asm: "VPXORD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPXORDMasked128load", argLength: 4, reg: w2kwload, asm: "VPXORD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPXORDMasked256load", argLength: 4, reg: w2kwload, asm: "VPXORD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPXORDMasked512load", argLength: 4, reg: w2kwload, asm: "VPXORD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPXORQ512load", argLength: 3, reg: w21load, asm: "VPXORQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VPXORQMasked128load", argLength: 4, reg: w2kwload, asm: "VPXORQ", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VPXORQMasked256load", argLength: 4, reg: w2kwload, asm: "VPXORQ", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VPXORQMasked512load", argLength: 4, reg: w2kwload, asm: "VPXORQ", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VRCP14PD128load", argLength: 2, reg: w11load, asm: "VRCP14PD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VRCP14PD256load", argLength: 2, reg: w11load, asm: "VRCP14PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VRCP14PD512load", argLength: 2, reg: w11load, asm: "VRCP14PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VRCP14PDMasked128load", argLength: 3, reg: wkwload, asm: "VRCP14PD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VRCP14PDMasked256load", argLength: 3, reg: wkwload, asm: "VRCP14PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VRCP14PDMasked512load", argLength: 3, reg: wkwload, asm: "VRCP14PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VRCP14PS512load", argLength: 2, reg: w11load, asm: "VRCP14PS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VRCP14PSMasked128load", argLength: 3, reg: wkwload, asm: "VRCP14PS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VRCP14PSMasked256load", argLength: 3, reg: wkwload, asm: "VRCP14PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VRCP14PSMasked512load", argLength: 3, reg: wkwload, asm: "VRCP14PS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VRCPPS128load", argLength: 2, reg: v11load, asm: "VRCPPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VRCPPS256load", argLength: 2, reg: v11load, asm: "VRCPPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRT14PD128load", argLength: 2, reg: w11load, asm: "VRSQRT14PD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRT14PD256load", argLength: 2, reg: w11load, asm: "VRSQRT14PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRT14PD512load", argLength: 2, reg: w11load, asm: "VRSQRT14PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRT14PDMasked128load", argLength: 3, reg: wkwload, asm: "VRSQRT14PD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRT14PDMasked256load", argLength: 3, reg: wkwload, asm: "VRSQRT14PD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRT14PDMasked512load", argLength: 3, reg: wkwload, asm: "VRSQRT14PD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRT14PS512load", argLength: 2, reg: w11load, asm: "VRSQRT14PS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRT14PSMasked128load", argLength: 3, reg: wkwload, asm: "VRSQRT14PS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRT14PSMasked256load", argLength: 3, reg: wkwload, asm: "VRSQRT14PS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRT14PSMasked512load", argLength: 3, reg: wkwload, asm: "VRSQRT14PS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRTPS128load", argLength: 2, reg: v11load, asm: "VRSQRTPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VRSQRTPS256load", argLength: 2, reg: v11load, asm: "VRSQRTPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPD128load", argLength: 3, reg: w21load, asm: "VSCALEFPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPD256load", argLength: 3, reg: w21load, asm: "VSCALEFPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPD512load", argLength: 3, reg: w21load, asm: "VSCALEFPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPDMasked128load", argLength: 4, reg: w2kwload, asm: "VSCALEFPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPDMasked256load", argLength: 4, reg: w2kwload, asm: "VSCALEFPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPDMasked512load", argLength: 4, reg: w2kwload, asm: "VSCALEFPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPS128load", argLength: 3, reg: w21load, asm: "VSCALEFPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPS256load", argLength: 3, reg: w21load, asm: "VSCALEFPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPS512load", argLength: 3, reg: w21load, asm: "VSCALEFPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPSMasked128load", argLength: 4, reg: w2kwload, asm: "VSCALEFPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPSMasked256load", argLength: 4, reg: w2kwload, asm: "VSCALEFPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSCALEFPSMasked512load", argLength: 4, reg: w2kwload, asm: "VSCALEFPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPD128load", argLength: 2, reg: v11load, asm: "VSQRTPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPD256load", argLength: 2, reg: v11load, asm: "VSQRTPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPD512load", argLength: 2, reg: w11load, asm: "VSQRTPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPDMasked128load", argLength: 3, reg: wkwload, asm: "VSQRTPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPDMasked256load", argLength: 3, reg: wkwload, asm: "VSQRTPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPDMasked512load", argLength: 3, reg: wkwload, asm: "VSQRTPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPS128load", argLength: 2, reg: v11load, asm: "VSQRTPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPS256load", argLength: 2, reg: v11load, asm: "VSQRTPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPS512load", argLength: 2, reg: w11load, asm: "VSQRTPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPSMasked128load", argLength: 3, reg: wkwload, asm: "VSQRTPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPSMasked256load", argLength: 3, reg: wkwload, asm: "VSQRTPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSQRTPSMasked512load", argLength: 3, reg: wkwload, asm: "VSQRTPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPD128load", argLength: 3, reg: v21load, asm: "VSUBPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPD256load", argLength: 3, reg: v21load, asm: "VSUBPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPD512load", argLength: 3, reg: w21load, asm: "VSUBPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPDMasked128load", argLength: 4, reg: w2kwload, asm: "VSUBPD", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPDMasked256load", argLength: 4, reg: w2kwload, asm: "VSUBPD", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPDMasked512load", argLength: 4, reg: w2kwload, asm: "VSUBPD", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPS128load", argLength: 3, reg: v21load, asm: "VSUBPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPS256load", argLength: 3, reg: v21load, asm: "VSUBPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPS512load", argLength: 3, reg: w21load, asm: "VSUBPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPSMasked128load", argLength: 4, reg: w2kwload, asm: "VSUBPS", typ: "Vec128", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPSMasked256load", argLength: 4, reg: w2kwload, asm: "VSUBPS", typ: "Vec256", aux: "SymOff", symEffect: "Read"}, + {name: "VSUBPSMasked512load", argLength: 4, reg: w2kwload, asm: "VSUBPS", typ: "Vec512", aux: "SymOff", symEffect: "Read"}, + {name: "VAESKEYGENASSIST128load", argLength: 2, reg: v11load, asm: "VAESKEYGENASSIST", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPD128load", argLength: 3, reg: v21load, asm: "VCMPPD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPD256load", argLength: 3, reg: v21load, asm: "VCMPPD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPD512load", argLength: 3, reg: w2kload, asm: "VCMPPD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPDMasked128load", argLength: 4, reg: w2kkload, asm: "VCMPPD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPDMasked256load", argLength: 4, reg: w2kkload, asm: "VCMPPD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPDMasked512load", argLength: 4, reg: w2kkload, asm: "VCMPPD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPS128load", argLength: 3, reg: v21load, asm: "VCMPPS", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPS256load", argLength: 3, reg: v21load, asm: "VCMPPS", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPS512load", argLength: 3, reg: w2kload, asm: "VCMPPS", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPSMasked128load", argLength: 4, reg: w2kkload, asm: "VCMPPS", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPSMasked256load", argLength: 4, reg: w2kkload, asm: "VCMPPS", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VCMPPSMasked512load", argLength: 4, reg: w2kkload, asm: "VCMPPS", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEINVQB128load", argLength: 3, reg: w21load, asm: "VGF2P8AFFINEINVQB", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEINVQB256load", argLength: 3, reg: w21load, asm: "VGF2P8AFFINEINVQB", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEINVQB512load", argLength: 3, reg: w21load, asm: "VGF2P8AFFINEINVQB", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEINVQBMasked128load", argLength: 4, reg: w2kwload, asm: "VGF2P8AFFINEINVQB", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEINVQBMasked256load", argLength: 4, reg: w2kwload, asm: "VGF2P8AFFINEINVQB", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEINVQBMasked512load", argLength: 4, reg: w2kwload, asm: "VGF2P8AFFINEINVQB", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEQB128load", argLength: 3, reg: w21load, asm: "VGF2P8AFFINEQB", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEQB256load", argLength: 3, reg: w21load, asm: "VGF2P8AFFINEQB", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEQB512load", argLength: 3, reg: w21load, asm: "VGF2P8AFFINEQB", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEQBMasked128load", argLength: 4, reg: w2kwload, asm: "VGF2P8AFFINEQB", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEQBMasked256load", argLength: 4, reg: w2kwload, asm: "VGF2P8AFFINEQB", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VGF2P8AFFINEQBMasked512load", argLength: 4, reg: w2kwload, asm: "VGF2P8AFFINEQB", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VINSERTF64X4512load", argLength: 3, reg: w21load, asm: "VINSERTF64X4", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VINSERTF128256load", argLength: 3, reg: v21load, asm: "VINSERTF128", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VINSERTI64X4512load", argLength: 3, reg: w21load, asm: "VINSERTI64X4", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VINSERTI128256load", argLength: 3, reg: v21load, asm: "VINSERTI128", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPALIGNR128load", argLength: 3, reg: v21load, asm: "VPALIGNR", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPALIGNR256load", argLength: 3, reg: v21load, asm: "VPALIGNR", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPALIGNRMasked128load", argLength: 4, reg: w2kwload, asm: "VPALIGNR", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPALIGNRMasked256load", argLength: 4, reg: w2kwload, asm: "VPALIGNR", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCLMULQDQ128load", argLength: 3, reg: v21load, asm: "VPCLMULQDQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCLMULQDQ256load", argLength: 3, reg: w21load, asm: "VPCLMULQDQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPBMasked128load", argLength: 4, reg: w2kkload, asm: "VPCMPB", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPBMasked256load", argLength: 4, reg: w2kkload, asm: "VPCMPB", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPD512load", argLength: 3, reg: w2kload, asm: "VPCMPD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPDMasked128load", argLength: 4, reg: w2kkload, asm: "VPCMPD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPDMasked256load", argLength: 4, reg: w2kkload, asm: "VPCMPD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPDMasked512load", argLength: 4, reg: w2kkload, asm: "VPCMPD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPQ512load", argLength: 3, reg: w2kload, asm: "VPCMPQ", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPQMasked128load", argLength: 4, reg: w2kkload, asm: "VPCMPQ", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPQMasked256load", argLength: 4, reg: w2kkload, asm: "VPCMPQ", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPQMasked512load", argLength: 4, reg: w2kkload, asm: "VPCMPQ", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUBMasked128load", argLength: 4, reg: w2kkload, asm: "VPCMPUB", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUBMasked256load", argLength: 4, reg: w2kkload, asm: "VPCMPUB", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUD512load", argLength: 3, reg: w2kload, asm: "VPCMPUD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUDMasked128load", argLength: 4, reg: w2kkload, asm: "VPCMPUD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUDMasked256load", argLength: 4, reg: w2kkload, asm: "VPCMPUD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUDMasked512load", argLength: 4, reg: w2kkload, asm: "VPCMPUD", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUQ512load", argLength: 3, reg: w2kload, asm: "VPCMPUQ", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUQMasked128load", argLength: 4, reg: w2kkload, asm: "VPCMPUQ", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUQMasked256load", argLength: 4, reg: w2kkload, asm: "VPCMPUQ", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUQMasked512load", argLength: 4, reg: w2kkload, asm: "VPCMPUQ", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUWMasked128load", argLength: 4, reg: w2kkload, asm: "VPCMPUW", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPUWMasked256load", argLength: 4, reg: w2kkload, asm: "VPCMPUW", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPWMasked128load", argLength: 4, reg: w2kkload, asm: "VPCMPW", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPCMPWMasked256load", argLength: 4, reg: w2kkload, asm: "VPCMPW", typ: "Mask", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPERM2F128256load", argLength: 3, reg: v21load, asm: "VPERM2F128", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPERM2I128256load", argLength: 3, reg: v21load, asm: "VPERM2I128", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLD128load", argLength: 2, reg: w11load, asm: "VPROLD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLD256load", argLength: 2, reg: w11load, asm: "VPROLD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLD512load", argLength: 2, reg: w11load, asm: "VPROLD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLDMasked128load", argLength: 3, reg: wkwload, asm: "VPROLD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLDMasked256load", argLength: 3, reg: wkwload, asm: "VPROLD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLDMasked512load", argLength: 3, reg: wkwload, asm: "VPROLD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLQ128load", argLength: 2, reg: w11load, asm: "VPROLQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLQ256load", argLength: 2, reg: w11load, asm: "VPROLQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLQ512load", argLength: 2, reg: w11load, asm: "VPROLQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLQMasked128load", argLength: 3, reg: wkwload, asm: "VPROLQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLQMasked256load", argLength: 3, reg: wkwload, asm: "VPROLQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPROLQMasked512load", argLength: 3, reg: wkwload, asm: "VPROLQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORD128load", argLength: 2, reg: w11load, asm: "VPRORD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORD256load", argLength: 2, reg: w11load, asm: "VPRORD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORD512load", argLength: 2, reg: w11load, asm: "VPRORD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORDMasked128load", argLength: 3, reg: wkwload, asm: "VPRORD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORDMasked256load", argLength: 3, reg: wkwload, asm: "VPRORD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORDMasked512load", argLength: 3, reg: wkwload, asm: "VPRORD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORQ128load", argLength: 2, reg: w11load, asm: "VPRORQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORQ256load", argLength: 2, reg: w11load, asm: "VPRORQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORQ512load", argLength: 2, reg: w11load, asm: "VPRORQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORQMasked128load", argLength: 3, reg: wkwload, asm: "VPRORQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORQMasked256load", argLength: 3, reg: wkwload, asm: "VPRORQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPRORQMasked512load", argLength: 3, reg: wkwload, asm: "VPRORQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDD128load", argLength: 3, reg: w21load, asm: "VPSHLDD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDD256load", argLength: 3, reg: w21load, asm: "VPSHLDD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDD512load", argLength: 3, reg: w21load, asm: "VPSHLDD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDDMasked128load", argLength: 4, reg: w2kwload, asm: "VPSHLDD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDDMasked256load", argLength: 4, reg: w2kwload, asm: "VPSHLDD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDDMasked512load", argLength: 4, reg: w2kwload, asm: "VPSHLDD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDQ128load", argLength: 3, reg: w21load, asm: "VPSHLDQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDQ256load", argLength: 3, reg: w21load, asm: "VPSHLDQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDQ512load", argLength: 3, reg: w21load, asm: "VPSHLDQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDQMasked128load", argLength: 4, reg: w2kwload, asm: "VPSHLDQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDQMasked256load", argLength: 4, reg: w2kwload, asm: "VPSHLDQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDQMasked512load", argLength: 4, reg: w2kwload, asm: "VPSHLDQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDW128load", argLength: 3, reg: w21load, asm: "VPSHLDW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDW256load", argLength: 3, reg: w21load, asm: "VPSHLDW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDWMasked128load", argLength: 4, reg: w2kwload, asm: "VPSHLDW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHLDWMasked256load", argLength: 4, reg: w2kwload, asm: "VPSHLDW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDD128load", argLength: 3, reg: w21load, asm: "VPSHRDD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDD256load", argLength: 3, reg: w21load, asm: "VPSHRDD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDD512load", argLength: 3, reg: w21load, asm: "VPSHRDD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDDMasked128load", argLength: 4, reg: w2kwload, asm: "VPSHRDD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDDMasked256load", argLength: 4, reg: w2kwload, asm: "VPSHRDD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDDMasked512load", argLength: 4, reg: w2kwload, asm: "VPSHRDD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDQ128load", argLength: 3, reg: w21load, asm: "VPSHRDQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDQ256load", argLength: 3, reg: w21load, asm: "VPSHRDQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDQ512load", argLength: 3, reg: w21load, asm: "VPSHRDQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDQMasked128load", argLength: 4, reg: w2kwload, asm: "VPSHRDQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDQMasked256load", argLength: 4, reg: w2kwload, asm: "VPSHRDQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDQMasked512load", argLength: 4, reg: w2kwload, asm: "VPSHRDQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDW128load", argLength: 3, reg: w21load, asm: "VPSHRDW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDW256load", argLength: 3, reg: w21load, asm: "VPSHRDW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDWMasked128load", argLength: 4, reg: w2kwload, asm: "VPSHRDW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHRDWMasked256load", argLength: 4, reg: w2kwload, asm: "VPSHRDW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFD128load", argLength: 2, reg: v11load, asm: "VPSHUFD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFD256load", argLength: 2, reg: v11load, asm: "VPSHUFD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFD512load", argLength: 2, reg: w11load, asm: "VPSHUFD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFDMasked128load", argLength: 3, reg: wkwload, asm: "VPSHUFD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFDMasked256load", argLength: 3, reg: wkwload, asm: "VPSHUFD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFDMasked512load", argLength: 3, reg: wkwload, asm: "VPSHUFD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFHW128load", argLength: 2, reg: v11load, asm: "VPSHUFHW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFHW256load", argLength: 2, reg: v11load, asm: "VPSHUFHW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFHWMasked128load", argLength: 3, reg: wkwload, asm: "VPSHUFHW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFHWMasked256load", argLength: 3, reg: wkwload, asm: "VPSHUFHW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFLW128load", argLength: 2, reg: v11load, asm: "VPSHUFLW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFLW256load", argLength: 2, reg: v11load, asm: "VPSHUFLW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFLWMasked128load", argLength: 3, reg: wkwload, asm: "VPSHUFLW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSHUFLWMasked256load", argLength: 3, reg: wkwload, asm: "VPSHUFLW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSLLD512constload", argLength: 2, reg: w11load, asm: "VPSLLD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSLLDMasked128constload", argLength: 3, reg: wkwload, asm: "VPSLLD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSLLDMasked256constload", argLength: 3, reg: wkwload, asm: "VPSLLD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSLLDMasked512constload", argLength: 3, reg: wkwload, asm: "VPSLLD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSLLQ512constload", argLength: 2, reg: w11load, asm: "VPSLLQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSLLQMasked128constload", argLength: 3, reg: wkwload, asm: "VPSLLQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSLLQMasked256constload", argLength: 3, reg: wkwload, asm: "VPSLLQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSLLQMasked512constload", argLength: 3, reg: wkwload, asm: "VPSLLQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSLLWMasked128constload", argLength: 3, reg: wkwload, asm: "VPSLLW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSLLWMasked256constload", argLength: 3, reg: wkwload, asm: "VPSLLW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRAD512constload", argLength: 2, reg: w11load, asm: "VPSRAD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRADMasked128constload", argLength: 3, reg: wkwload, asm: "VPSRAD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRADMasked256constload", argLength: 3, reg: wkwload, asm: "VPSRAD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRADMasked512constload", argLength: 3, reg: wkwload, asm: "VPSRAD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRAQ128constload", argLength: 2, reg: w11load, asm: "VPSRAQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRAQ256constload", argLength: 2, reg: w11load, asm: "VPSRAQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRAQ512constload", argLength: 2, reg: w11load, asm: "VPSRAQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRAQMasked128constload", argLength: 3, reg: wkwload, asm: "VPSRAQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRAQMasked256constload", argLength: 3, reg: wkwload, asm: "VPSRAQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRAQMasked512constload", argLength: 3, reg: wkwload, asm: "VPSRAQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRAWMasked128constload", argLength: 3, reg: wkwload, asm: "VPSRAW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRAWMasked256constload", argLength: 3, reg: wkwload, asm: "VPSRAW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRLD512constload", argLength: 2, reg: w11load, asm: "VPSRLD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRLDMasked128constload", argLength: 3, reg: wkwload, asm: "VPSRLD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRLDMasked256constload", argLength: 3, reg: wkwload, asm: "VPSRLD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRLDMasked512constload", argLength: 3, reg: wkwload, asm: "VPSRLD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRLQ512constload", argLength: 2, reg: w11load, asm: "VPSRLQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRLQMasked128constload", argLength: 3, reg: wkwload, asm: "VPSRLQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRLQMasked256constload", argLength: 3, reg: wkwload, asm: "VPSRLQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRLQMasked512constload", argLength: 3, reg: wkwload, asm: "VPSRLQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRLWMasked128constload", argLength: 3, reg: wkwload, asm: "VPSRLW", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPSRLWMasked256constload", argLength: 3, reg: wkwload, asm: "VPSRLW", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VPTERNLOGD128load", argLength: 4, reg: w31load, asm: "VPTERNLOGD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: true}, + {name: "VPTERNLOGD256load", argLength: 4, reg: w31load, asm: "VPTERNLOGD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: true}, + {name: "VPTERNLOGD512load", argLength: 4, reg: w31load, asm: "VPTERNLOGD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: true}, + {name: "VPTERNLOGQ128load", argLength: 4, reg: w31load, asm: "VPTERNLOGQ", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: true}, + {name: "VPTERNLOGQ256load", argLength: 4, reg: w31load, asm: "VPTERNLOGQ", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: true}, + {name: "VPTERNLOGQ512load", argLength: 4, reg: w31load, asm: "VPTERNLOGQ", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: true}, + {name: "VREDUCEPD128load", argLength: 2, reg: w11load, asm: "VREDUCEPD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPD256load", argLength: 2, reg: w11load, asm: "VREDUCEPD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPD512load", argLength: 2, reg: w11load, asm: "VREDUCEPD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPDMasked128load", argLength: 3, reg: wkwload, asm: "VREDUCEPD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPDMasked256load", argLength: 3, reg: wkwload, asm: "VREDUCEPD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPDMasked512load", argLength: 3, reg: wkwload, asm: "VREDUCEPD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPS128load", argLength: 2, reg: w11load, asm: "VREDUCEPS", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPS256load", argLength: 2, reg: w11load, asm: "VREDUCEPS", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPS512load", argLength: 2, reg: w11load, asm: "VREDUCEPS", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPSMasked128load", argLength: 3, reg: wkwload, asm: "VREDUCEPS", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPSMasked256load", argLength: 3, reg: wkwload, asm: "VREDUCEPS", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VREDUCEPSMasked512load", argLength: 3, reg: wkwload, asm: "VREDUCEPS", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPD128load", argLength: 2, reg: w11load, asm: "VRNDSCALEPD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPD256load", argLength: 2, reg: w11load, asm: "VRNDSCALEPD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPD512load", argLength: 2, reg: w11load, asm: "VRNDSCALEPD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPDMasked128load", argLength: 3, reg: wkwload, asm: "VRNDSCALEPD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPDMasked256load", argLength: 3, reg: wkwload, asm: "VRNDSCALEPD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPDMasked512load", argLength: 3, reg: wkwload, asm: "VRNDSCALEPD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPS128load", argLength: 2, reg: w11load, asm: "VRNDSCALEPS", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPS256load", argLength: 2, reg: w11load, asm: "VRNDSCALEPS", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPS512load", argLength: 2, reg: w11load, asm: "VRNDSCALEPS", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPSMasked128load", argLength: 3, reg: wkwload, asm: "VRNDSCALEPS", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPSMasked256load", argLength: 3, reg: wkwload, asm: "VRNDSCALEPS", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VRNDSCALEPSMasked512load", argLength: 3, reg: wkwload, asm: "VRNDSCALEPS", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VROUNDPD128load", argLength: 2, reg: v11load, asm: "VROUNDPD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VROUNDPD256load", argLength: 2, reg: v11load, asm: "VROUNDPD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VROUNDPS128load", argLength: 2, reg: v11load, asm: "VROUNDPS", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VROUNDPS256load", argLength: 2, reg: v11load, asm: "VROUNDPS", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VSHUFPD128load", argLength: 3, reg: v21load, asm: "VSHUFPD", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VSHUFPD256load", argLength: 3, reg: v21load, asm: "VSHUFPD", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VSHUFPD512load", argLength: 3, reg: w21load, asm: "VSHUFPD", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VSHUFPS128load", argLength: 3, reg: v21load, asm: "VSHUFPS", typ: "Vec128", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VSHUFPS256load", argLength: 3, reg: v21load, asm: "VSHUFPS", typ: "Vec256", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VSHUFPS512load", argLength: 3, reg: w21load, asm: "VSHUFPS", typ: "Vec512", aux: "SymValAndOff", symEffect: "Read"}, + {name: "VADDPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VADDPD", typ: "Vec128", resultInArg0: true}, + {name: "VADDPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VADDPD", typ: "Vec256", resultInArg0: true}, + {name: "VADDPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VADDPD", typ: "Vec512", resultInArg0: true}, + {name: "VADDPSMasked128Merging", argLength: 4, reg: w3kw, asm: "VADDPS", typ: "Vec128", resultInArg0: true}, + {name: "VADDPSMasked256Merging", argLength: 4, reg: w3kw, asm: "VADDPS", typ: "Vec256", resultInArg0: true}, + {name: "VADDPSMasked512Merging", argLength: 4, reg: w3kw, asm: "VADDPS", typ: "Vec512", resultInArg0: true}, + {name: "VBROADCASTSDMasked256Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSD", typ: "Vec256", resultInArg0: true}, + {name: "VBROADCASTSDMasked512Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSD", typ: "Vec512", resultInArg0: true}, + {name: "VBROADCASTSSMasked128Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", typ: "Vec128", resultInArg0: true}, + {name: "VBROADCASTSSMasked256Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", typ: "Vec256", resultInArg0: true}, + {name: "VBROADCASTSSMasked512Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", typ: "Vec512", resultInArg0: true}, + {name: "VCVTDQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PD", typ: "Vec256", resultInArg0: true}, + {name: "VCVTDQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PD", typ: "Vec512", resultInArg0: true}, + {name: "VCVTDQ2PSMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", typ: "Vec128", resultInArg0: true}, + {name: "VCVTDQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", typ: "Vec256", resultInArg0: true}, + {name: "VCVTDQ2PSMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", typ: "Vec512", resultInArg0: true}, + {name: "VCVTPD2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTPD2PS", typ: "Vec256", resultInArg0: true}, + {name: "VCVTPD2PSXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTPD2PSX", typ: "Vec128", resultInArg0: true}, + {name: "VCVTPD2PSYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTPD2PSY", typ: "Vec128", resultInArg0: true}, + {name: "VCVTPS2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2PD", typ: "Vec256", resultInArg0: true}, + {name: "VCVTPS2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2PD", typ: "Vec512", resultInArg0: true}, + {name: "VCVTQQ2PDMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", typ: "Vec128", resultInArg0: true}, + {name: "VCVTQQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", typ: "Vec256", resultInArg0: true}, + {name: "VCVTQQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", typ: "Vec512", resultInArg0: true}, + {name: "VCVTQQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PS", typ: "Vec256", resultInArg0: true}, + {name: "VCVTQQ2PSXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PSX", typ: "Vec128", resultInArg0: true}, + {name: "VCVTQQ2PSYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PSY", typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2DQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQ", typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPD2DQXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQX", typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2DQYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQY", typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2QQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2QQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPD2QQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", typ: "Vec512", resultInArg0: true}, + {name: "VCVTTPD2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQ", typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPD2UDQXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQX", typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2UDQYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQY", typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2UQQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2UQQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPD2UQQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", typ: "Vec512", resultInArg0: true}, + {name: "VCVTTPS2DQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPS2DQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPS2DQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", typ: "Vec512", resultInArg0: true}, + {name: "VCVTTPS2QQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2QQ", typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPS2QQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2QQ", typ: "Vec512", resultInArg0: true}, + {name: "VCVTTPS2UDQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPS2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPS2UDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", typ: "Vec512", resultInArg0: true}, + {name: "VCVTTPS2UQQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPS2UQQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", typ: "Vec512", resultInArg0: true}, + {name: "VCVTUDQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PD", typ: "Vec256", resultInArg0: true}, + {name: "VCVTUDQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PD", typ: "Vec512", resultInArg0: true}, + {name: "VCVTUDQ2PSMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", typ: "Vec128", resultInArg0: true}, + {name: "VCVTUDQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", typ: "Vec256", resultInArg0: true}, + {name: "VCVTUDQ2PSMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", typ: "Vec512", resultInArg0: true}, + {name: "VCVTUQQ2PDMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", typ: "Vec128", resultInArg0: true}, + {name: "VCVTUQQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", typ: "Vec256", resultInArg0: true}, + {name: "VCVTUQQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", typ: "Vec512", resultInArg0: true}, + {name: "VCVTUQQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PS", typ: "Vec256", resultInArg0: true}, + {name: "VCVTUQQ2PSXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PSX", typ: "Vec128", resultInArg0: true}, + {name: "VCVTUQQ2PSYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PSY", typ: "Vec128", resultInArg0: true}, + {name: "VDIVPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", typ: "Vec128", resultInArg0: true}, + {name: "VDIVPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", typ: "Vec256", resultInArg0: true}, + {name: "VDIVPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", typ: "Vec512", resultInArg0: true}, + {name: "VDIVPSMasked128Merging", argLength: 4, reg: w3kw, asm: "VDIVPS", typ: "Vec128", resultInArg0: true}, + {name: "VDIVPSMasked256Merging", argLength: 4, reg: w3kw, asm: "VDIVPS", typ: "Vec256", resultInArg0: true}, + {name: "VDIVPSMasked512Merging", argLength: 4, reg: w3kw, asm: "VDIVPS", typ: "Vec512", resultInArg0: true}, + {name: "VGF2P8MULBMasked128Merging", argLength: 4, reg: w3kw, asm: "VGF2P8MULB", typ: "Vec128", resultInArg0: true}, + {name: "VGF2P8MULBMasked256Merging", argLength: 4, reg: w3kw, asm: "VGF2P8MULB", typ: "Vec256", resultInArg0: true}, + {name: "VGF2P8MULBMasked512Merging", argLength: 4, reg: w3kw, asm: "VGF2P8MULB", typ: "Vec512", resultInArg0: true}, + {name: "VMAXPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VMAXPD", typ: "Vec128", resultInArg0: true}, + {name: "VMAXPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VMAXPD", typ: "Vec256", resultInArg0: true}, + {name: "VMAXPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VMAXPD", typ: "Vec512", resultInArg0: true}, + {name: "VMAXPSMasked128Merging", argLength: 4, reg: w3kw, asm: "VMAXPS", typ: "Vec128", resultInArg0: true}, + {name: "VMAXPSMasked256Merging", argLength: 4, reg: w3kw, asm: "VMAXPS", typ: "Vec256", resultInArg0: true}, + {name: "VMAXPSMasked512Merging", argLength: 4, reg: w3kw, asm: "VMAXPS", typ: "Vec512", resultInArg0: true}, + {name: "VMINPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VMINPD", typ: "Vec128", resultInArg0: true}, + {name: "VMINPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VMINPD", typ: "Vec256", resultInArg0: true}, + {name: "VMINPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VMINPD", typ: "Vec512", resultInArg0: true}, + {name: "VMINPSMasked128Merging", argLength: 4, reg: w3kw, asm: "VMINPS", typ: "Vec128", resultInArg0: true}, + {name: "VMINPSMasked256Merging", argLength: 4, reg: w3kw, asm: "VMINPS", typ: "Vec256", resultInArg0: true}, + {name: "VMINPSMasked512Merging", argLength: 4, reg: w3kw, asm: "VMINPS", typ: "Vec512", resultInArg0: true}, + {name: "VMULPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VMULPD", typ: "Vec128", resultInArg0: true}, + {name: "VMULPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VMULPD", typ: "Vec256", resultInArg0: true}, + {name: "VMULPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VMULPD", typ: "Vec512", resultInArg0: true}, + {name: "VMULPSMasked128Merging", argLength: 4, reg: w3kw, asm: "VMULPS", typ: "Vec128", resultInArg0: true}, + {name: "VMULPSMasked256Merging", argLength: 4, reg: w3kw, asm: "VMULPS", typ: "Vec256", resultInArg0: true}, + {name: "VMULPSMasked512Merging", argLength: 4, reg: w3kw, asm: "VMULPS", typ: "Vec512", resultInArg0: true}, + {name: "VPABSBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPABSB", typ: "Vec128", resultInArg0: true}, + {name: "VPABSBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPABSB", typ: "Vec256", resultInArg0: true}, + {name: "VPABSBMasked512Merging", argLength: 3, reg: w2kw, asm: "VPABSB", typ: "Vec512", resultInArg0: true}, + {name: "VPABSDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPABSD", typ: "Vec128", resultInArg0: true}, + {name: "VPABSDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPABSD", typ: "Vec256", resultInArg0: true}, + {name: "VPABSDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPABSD", typ: "Vec512", resultInArg0: true}, + {name: "VPABSQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPABSQ", typ: "Vec128", resultInArg0: true}, + {name: "VPABSQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPABSQ", typ: "Vec256", resultInArg0: true}, + {name: "VPABSQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPABSQ", typ: "Vec512", resultInArg0: true}, + {name: "VPABSWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPABSW", typ: "Vec128", resultInArg0: true}, + {name: "VPABSWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPABSW", typ: "Vec256", resultInArg0: true}, + {name: "VPABSWMasked512Merging", argLength: 3, reg: w2kw, asm: "VPABSW", typ: "Vec512", resultInArg0: true}, + {name: "VPACKSSDWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPACKSSDW", typ: "Vec128", resultInArg0: true}, + {name: "VPACKSSDWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPACKSSDW", typ: "Vec256", resultInArg0: true}, + {name: "VPACKSSDWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPACKSSDW", typ: "Vec512", resultInArg0: true}, + {name: "VPACKUSDWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPACKUSDW", typ: "Vec128", resultInArg0: true}, + {name: "VPACKUSDWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPACKUSDW", typ: "Vec256", resultInArg0: true}, + {name: "VPACKUSDWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPACKUSDW", typ: "Vec512", resultInArg0: true}, + {name: "VPADDBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPADDB", typ: "Vec128", resultInArg0: true}, + {name: "VPADDBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPADDB", typ: "Vec256", resultInArg0: true}, + {name: "VPADDBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPADDB", typ: "Vec512", resultInArg0: true}, + {name: "VPADDDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPADDD", typ: "Vec128", resultInArg0: true}, + {name: "VPADDDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPADDD", typ: "Vec256", resultInArg0: true}, + {name: "VPADDDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPADDD", typ: "Vec512", resultInArg0: true}, + {name: "VPADDQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPADDQ", typ: "Vec128", resultInArg0: true}, + {name: "VPADDQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPADDQ", typ: "Vec256", resultInArg0: true}, + {name: "VPADDQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPADDQ", typ: "Vec512", resultInArg0: true}, + {name: "VPADDSBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPADDSB", typ: "Vec128", resultInArg0: true}, + {name: "VPADDSBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPADDSB", typ: "Vec256", resultInArg0: true}, + {name: "VPADDSBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPADDSB", typ: "Vec512", resultInArg0: true}, + {name: "VPADDSWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPADDSW", typ: "Vec128", resultInArg0: true}, + {name: "VPADDSWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPADDSW", typ: "Vec256", resultInArg0: true}, + {name: "VPADDSWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPADDSW", typ: "Vec512", resultInArg0: true}, + {name: "VPADDUSBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPADDUSB", typ: "Vec128", resultInArg0: true}, + {name: "VPADDUSBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPADDUSB", typ: "Vec256", resultInArg0: true}, + {name: "VPADDUSBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPADDUSB", typ: "Vec512", resultInArg0: true}, + {name: "VPADDUSWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPADDUSW", typ: "Vec128", resultInArg0: true}, + {name: "VPADDUSWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPADDUSW", typ: "Vec256", resultInArg0: true}, + {name: "VPADDUSWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPADDUSW", typ: "Vec512", resultInArg0: true}, + {name: "VPADDWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPADDW", typ: "Vec128", resultInArg0: true}, + {name: "VPADDWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPADDW", typ: "Vec256", resultInArg0: true}, + {name: "VPADDWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPADDW", typ: "Vec512", resultInArg0: true}, + {name: "VPANDDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPANDD", typ: "Vec128", resultInArg0: true}, + {name: "VPANDDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPANDD", typ: "Vec256", resultInArg0: true}, + {name: "VPANDDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPANDD", typ: "Vec512", resultInArg0: true}, + {name: "VPANDQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPANDQ", typ: "Vec128", resultInArg0: true}, + {name: "VPANDQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPANDQ", typ: "Vec256", resultInArg0: true}, + {name: "VPANDQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPANDQ", typ: "Vec512", resultInArg0: true}, + {name: "VPAVGBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPAVGB", typ: "Vec128", resultInArg0: true}, + {name: "VPAVGBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPAVGB", typ: "Vec256", resultInArg0: true}, + {name: "VPAVGBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPAVGB", typ: "Vec512", resultInArg0: true}, + {name: "VPAVGWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPAVGW", typ: "Vec128", resultInArg0: true}, + {name: "VPAVGWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPAVGW", typ: "Vec256", resultInArg0: true}, + {name: "VPAVGWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPAVGW", typ: "Vec512", resultInArg0: true}, + {name: "VPBROADCASTBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTB", typ: "Vec128", resultInArg0: true}, + {name: "VPBROADCASTBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTB", typ: "Vec256", resultInArg0: true}, + {name: "VPBROADCASTBMasked512Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTB", typ: "Vec512", resultInArg0: true}, + {name: "VPBROADCASTDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTD", typ: "Vec128", resultInArg0: true}, + {name: "VPBROADCASTDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTD", typ: "Vec256", resultInArg0: true}, + {name: "VPBROADCASTDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTD", typ: "Vec512", resultInArg0: true}, + {name: "VPBROADCASTQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTQ", typ: "Vec128", resultInArg0: true}, + {name: "VPBROADCASTQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTQ", typ: "Vec256", resultInArg0: true}, + {name: "VPBROADCASTQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTQ", typ: "Vec512", resultInArg0: true}, + {name: "VPBROADCASTWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTW", typ: "Vec128", resultInArg0: true}, + {name: "VPBROADCASTWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTW", typ: "Vec256", resultInArg0: true}, + {name: "VPBROADCASTWMasked512Merging", argLength: 3, reg: w2kw, asm: "VPBROADCASTW", typ: "Vec512", resultInArg0: true}, + {name: "VPLZCNTDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPLZCNTD", typ: "Vec128", resultInArg0: true}, + {name: "VPLZCNTDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPLZCNTD", typ: "Vec256", resultInArg0: true}, + {name: "VPLZCNTDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPLZCNTD", typ: "Vec512", resultInArg0: true}, + {name: "VPLZCNTQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPLZCNTQ", typ: "Vec128", resultInArg0: true}, + {name: "VPLZCNTQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPLZCNTQ", typ: "Vec256", resultInArg0: true}, + {name: "VPLZCNTQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPLZCNTQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMADDUBSWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMADDUBSW", typ: "Vec128", resultInArg0: true}, + {name: "VPMADDUBSWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMADDUBSW", typ: "Vec256", resultInArg0: true}, + {name: "VPMADDUBSWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMADDUBSW", typ: "Vec512", resultInArg0: true}, + {name: "VPMADDWDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMADDWD", typ: "Vec128", resultInArg0: true}, + {name: "VPMADDWDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMADDWD", typ: "Vec256", resultInArg0: true}, + {name: "VPMADDWDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMADDWD", typ: "Vec512", resultInArg0: true}, + {name: "VPMAXSBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMAXSB", typ: "Vec128", resultInArg0: true}, + {name: "VPMAXSBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMAXSB", typ: "Vec256", resultInArg0: true}, + {name: "VPMAXSBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMAXSB", typ: "Vec512", resultInArg0: true}, + {name: "VPMAXSDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMAXSD", typ: "Vec128", resultInArg0: true}, + {name: "VPMAXSDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMAXSD", typ: "Vec256", resultInArg0: true}, + {name: "VPMAXSDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMAXSD", typ: "Vec512", resultInArg0: true}, + {name: "VPMAXSQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMAXSQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMAXSQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMAXSQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMAXSQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMAXSQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMAXSWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMAXSW", typ: "Vec128", resultInArg0: true}, + {name: "VPMAXSWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMAXSW", typ: "Vec256", resultInArg0: true}, + {name: "VPMAXSWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMAXSW", typ: "Vec512", resultInArg0: true}, + {name: "VPMAXUBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMAXUB", typ: "Vec128", resultInArg0: true}, + {name: "VPMAXUBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMAXUB", typ: "Vec256", resultInArg0: true}, + {name: "VPMAXUBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMAXUB", typ: "Vec512", resultInArg0: true}, + {name: "VPMAXUDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMAXUD", typ: "Vec128", resultInArg0: true}, + {name: "VPMAXUDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMAXUD", typ: "Vec256", resultInArg0: true}, + {name: "VPMAXUDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMAXUD", typ: "Vec512", resultInArg0: true}, + {name: "VPMAXUQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMAXUQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMAXUQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMAXUQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMAXUQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMAXUQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMAXUWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMAXUW", typ: "Vec128", resultInArg0: true}, + {name: "VPMAXUWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMAXUW", typ: "Vec256", resultInArg0: true}, + {name: "VPMAXUWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMAXUW", typ: "Vec512", resultInArg0: true}, + {name: "VPMINSBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMINSB", typ: "Vec128", resultInArg0: true}, + {name: "VPMINSBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMINSB", typ: "Vec256", resultInArg0: true}, + {name: "VPMINSBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMINSB", typ: "Vec512", resultInArg0: true}, + {name: "VPMINSDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMINSD", typ: "Vec128", resultInArg0: true}, + {name: "VPMINSDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMINSD", typ: "Vec256", resultInArg0: true}, + {name: "VPMINSDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMINSD", typ: "Vec512", resultInArg0: true}, + {name: "VPMINSQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMINSQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMINSQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMINSQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMINSQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMINSQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMINSWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMINSW", typ: "Vec128", resultInArg0: true}, + {name: "VPMINSWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMINSW", typ: "Vec256", resultInArg0: true}, + {name: "VPMINSWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMINSW", typ: "Vec512", resultInArg0: true}, + {name: "VPMINUBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMINUB", typ: "Vec128", resultInArg0: true}, + {name: "VPMINUBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMINUB", typ: "Vec256", resultInArg0: true}, + {name: "VPMINUBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMINUB", typ: "Vec512", resultInArg0: true}, + {name: "VPMINUDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMINUD", typ: "Vec128", resultInArg0: true}, + {name: "VPMINUDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMINUD", typ: "Vec256", resultInArg0: true}, + {name: "VPMINUDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMINUD", typ: "Vec512", resultInArg0: true}, + {name: "VPMINUQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMINUQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMINUQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMINUQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMINUQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMINUQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMINUWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMINUW", typ: "Vec128", resultInArg0: true}, + {name: "VPMINUWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMINUW", typ: "Vec256", resultInArg0: true}, + {name: "VPMINUWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMINUW", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVDBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVDB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVDBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVDB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVDBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVDB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVDWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVDW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVDWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVDW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVDWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVDW", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVQBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVQB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVQBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVQB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVQBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVQB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVQDMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVQD", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVQDMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVQD", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVQDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVQD", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVQWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVQW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVQWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVQW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVQWMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVQW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSDBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSDBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSDBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSDWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSDWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSDWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDW", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVSQBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSQBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSQBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSQDMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQD", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSQDMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQD", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSQDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQD", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVSQWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSQWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSQWMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSWBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSWB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSWBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSWB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSWBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSWB", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVSXBDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBD", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSXBDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBD", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVSXBDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBD", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVSXBQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSXBQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVSXBQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVSXBWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSXBWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBW", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVSXBWMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBW", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVSXDQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXDQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSXDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXDQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVSXDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXDQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVSXWDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWD", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSXWDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWD", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVSXWDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWD", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVSXWQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVSXWQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVSXWQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVUSDBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSDBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSDBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSDWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSDWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSDWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDW", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVUSQBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSQBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSQBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSQDMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQD", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSQDMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQD", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSQDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQD", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVUSQWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSQWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSQWMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSWBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSWB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSWBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSWB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVUSWBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSWB", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVWBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVWB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVWBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVWB", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVWBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVWB", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVZXBDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBD", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVZXBDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBD", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVZXBDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBD", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVZXBQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVZXBQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVZXBQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVZXBWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBW", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVZXBWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBW", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVZXBWMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBW", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVZXDQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXDQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVZXDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXDQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVZXDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXDQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVZXWDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXWD", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVZXWDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXWD", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVZXWDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXWD", typ: "Vec512", resultInArg0: true}, + {name: "VPMOVZXWQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXWQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMOVZXWQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXWQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMOVZXWQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXWQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMULHUWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMULHUW", typ: "Vec128", resultInArg0: true}, + {name: "VPMULHUWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMULHUW", typ: "Vec256", resultInArg0: true}, + {name: "VPMULHUWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMULHUW", typ: "Vec512", resultInArg0: true}, + {name: "VPMULHWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMULHW", typ: "Vec128", resultInArg0: true}, + {name: "VPMULHWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMULHW", typ: "Vec256", resultInArg0: true}, + {name: "VPMULHWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMULHW", typ: "Vec512", resultInArg0: true}, + {name: "VPMULLDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMULLD", typ: "Vec128", resultInArg0: true}, + {name: "VPMULLDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMULLD", typ: "Vec256", resultInArg0: true}, + {name: "VPMULLDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMULLD", typ: "Vec512", resultInArg0: true}, + {name: "VPMULLQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMULLQ", typ: "Vec128", resultInArg0: true}, + {name: "VPMULLQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMULLQ", typ: "Vec256", resultInArg0: true}, + {name: "VPMULLQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMULLQ", typ: "Vec512", resultInArg0: true}, + {name: "VPMULLWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMULLW", typ: "Vec128", resultInArg0: true}, + {name: "VPMULLWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMULLW", typ: "Vec256", resultInArg0: true}, + {name: "VPMULLWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMULLW", typ: "Vec512", resultInArg0: true}, + {name: "VPOPCNTBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTB", typ: "Vec128", resultInArg0: true}, + {name: "VPOPCNTBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTB", typ: "Vec256", resultInArg0: true}, + {name: "VPOPCNTBMasked512Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTB", typ: "Vec512", resultInArg0: true}, + {name: "VPOPCNTDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTD", typ: "Vec128", resultInArg0: true}, + {name: "VPOPCNTDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTD", typ: "Vec256", resultInArg0: true}, + {name: "VPOPCNTDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTD", typ: "Vec512", resultInArg0: true}, + {name: "VPOPCNTQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTQ", typ: "Vec128", resultInArg0: true}, + {name: "VPOPCNTQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTQ", typ: "Vec256", resultInArg0: true}, + {name: "VPOPCNTQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTQ", typ: "Vec512", resultInArg0: true}, + {name: "VPOPCNTWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTW", typ: "Vec128", resultInArg0: true}, + {name: "VPOPCNTWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTW", typ: "Vec256", resultInArg0: true}, + {name: "VPOPCNTWMasked512Merging", argLength: 3, reg: w2kw, asm: "VPOPCNTW", typ: "Vec512", resultInArg0: true}, + {name: "VPORDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPORD", typ: "Vec128", resultInArg0: true}, + {name: "VPORDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPORD", typ: "Vec256", resultInArg0: true}, + {name: "VPORDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPORD", typ: "Vec512", resultInArg0: true}, + {name: "VPORQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPORQ", typ: "Vec128", resultInArg0: true}, + {name: "VPORQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPORQ", typ: "Vec256", resultInArg0: true}, + {name: "VPORQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPORQ", typ: "Vec512", resultInArg0: true}, + {name: "VPROLVDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPROLVD", typ: "Vec128", resultInArg0: true}, + {name: "VPROLVDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPROLVD", typ: "Vec256", resultInArg0: true}, + {name: "VPROLVDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPROLVD", typ: "Vec512", resultInArg0: true}, + {name: "VPROLVQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPROLVQ", typ: "Vec128", resultInArg0: true}, + {name: "VPROLVQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPROLVQ", typ: "Vec256", resultInArg0: true}, + {name: "VPROLVQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPROLVQ", typ: "Vec512", resultInArg0: true}, + {name: "VPRORVDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPRORVD", typ: "Vec128", resultInArg0: true}, + {name: "VPRORVDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPRORVD", typ: "Vec256", resultInArg0: true}, + {name: "VPRORVDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPRORVD", typ: "Vec512", resultInArg0: true}, + {name: "VPRORVQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPRORVQ", typ: "Vec128", resultInArg0: true}, + {name: "VPRORVQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPRORVQ", typ: "Vec256", resultInArg0: true}, + {name: "VPRORVQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPRORVQ", typ: "Vec512", resultInArg0: true}, + {name: "VPSHUFBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSHUFB", typ: "Vec128", resultInArg0: true}, + {name: "VPSHUFBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSHUFB", typ: "Vec256", resultInArg0: true}, + {name: "VPSHUFBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSHUFB", typ: "Vec512", resultInArg0: true}, + {name: "VPSLLVDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSLLVD", typ: "Vec128", resultInArg0: true}, + {name: "VPSLLVDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSLLVD", typ: "Vec256", resultInArg0: true}, + {name: "VPSLLVDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSLLVD", typ: "Vec512", resultInArg0: true}, + {name: "VPSLLVQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSLLVQ", typ: "Vec128", resultInArg0: true}, + {name: "VPSLLVQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSLLVQ", typ: "Vec256", resultInArg0: true}, + {name: "VPSLLVQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSLLVQ", typ: "Vec512", resultInArg0: true}, + {name: "VPSLLVWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSLLVW", typ: "Vec128", resultInArg0: true}, + {name: "VPSLLVWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSLLVW", typ: "Vec256", resultInArg0: true}, + {name: "VPSLLVWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSLLVW", typ: "Vec512", resultInArg0: true}, + {name: "VPSRAVDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSRAVD", typ: "Vec128", resultInArg0: true}, + {name: "VPSRAVDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSRAVD", typ: "Vec256", resultInArg0: true}, + {name: "VPSRAVDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSRAVD", typ: "Vec512", resultInArg0: true}, + {name: "VPSRAVQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSRAVQ", typ: "Vec128", resultInArg0: true}, + {name: "VPSRAVQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSRAVQ", typ: "Vec256", resultInArg0: true}, + {name: "VPSRAVQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSRAVQ", typ: "Vec512", resultInArg0: true}, + {name: "VPSRAVWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSRAVW", typ: "Vec128", resultInArg0: true}, + {name: "VPSRAVWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSRAVW", typ: "Vec256", resultInArg0: true}, + {name: "VPSRAVWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSRAVW", typ: "Vec512", resultInArg0: true}, + {name: "VPSRLVDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSRLVD", typ: "Vec128", resultInArg0: true}, + {name: "VPSRLVDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSRLVD", typ: "Vec256", resultInArg0: true}, + {name: "VPSRLVDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSRLVD", typ: "Vec512", resultInArg0: true}, + {name: "VPSRLVQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSRLVQ", typ: "Vec128", resultInArg0: true}, + {name: "VPSRLVQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSRLVQ", typ: "Vec256", resultInArg0: true}, + {name: "VPSRLVQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSRLVQ", typ: "Vec512", resultInArg0: true}, + {name: "VPSRLVWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSRLVW", typ: "Vec128", resultInArg0: true}, + {name: "VPSRLVWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSRLVW", typ: "Vec256", resultInArg0: true}, + {name: "VPSRLVWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSRLVW", typ: "Vec512", resultInArg0: true}, + {name: "VPSUBBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSUBB", typ: "Vec128", resultInArg0: true}, + {name: "VPSUBBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSUBB", typ: "Vec256", resultInArg0: true}, + {name: "VPSUBBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSUBB", typ: "Vec512", resultInArg0: true}, + {name: "VPSUBDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSUBD", typ: "Vec128", resultInArg0: true}, + {name: "VPSUBDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSUBD", typ: "Vec256", resultInArg0: true}, + {name: "VPSUBDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSUBD", typ: "Vec512", resultInArg0: true}, + {name: "VPSUBQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSUBQ", typ: "Vec128", resultInArg0: true}, + {name: "VPSUBQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSUBQ", typ: "Vec256", resultInArg0: true}, + {name: "VPSUBQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSUBQ", typ: "Vec512", resultInArg0: true}, + {name: "VPSUBSBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSUBSB", typ: "Vec128", resultInArg0: true}, + {name: "VPSUBSBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSUBSB", typ: "Vec256", resultInArg0: true}, + {name: "VPSUBSBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSUBSB", typ: "Vec512", resultInArg0: true}, + {name: "VPSUBSWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSUBSW", typ: "Vec128", resultInArg0: true}, + {name: "VPSUBSWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSUBSW", typ: "Vec256", resultInArg0: true}, + {name: "VPSUBSWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSUBSW", typ: "Vec512", resultInArg0: true}, + {name: "VPSUBUSBMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSUBUSB", typ: "Vec128", resultInArg0: true}, + {name: "VPSUBUSBMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSUBUSB", typ: "Vec256", resultInArg0: true}, + {name: "VPSUBUSBMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSUBUSB", typ: "Vec512", resultInArg0: true}, + {name: "VPSUBUSWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSUBUSW", typ: "Vec128", resultInArg0: true}, + {name: "VPSUBUSWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSUBUSW", typ: "Vec256", resultInArg0: true}, + {name: "VPSUBUSWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSUBUSW", typ: "Vec512", resultInArg0: true}, + {name: "VPSUBWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPSUBW", typ: "Vec128", resultInArg0: true}, + {name: "VPSUBWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPSUBW", typ: "Vec256", resultInArg0: true}, + {name: "VPSUBWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPSUBW", typ: "Vec512", resultInArg0: true}, + {name: "VPXORDMasked128Merging", argLength: 4, reg: w3kw, asm: "VPXORD", typ: "Vec128", resultInArg0: true}, + {name: "VPXORDMasked256Merging", argLength: 4, reg: w3kw, asm: "VPXORD", typ: "Vec256", resultInArg0: true}, + {name: "VPXORDMasked512Merging", argLength: 4, reg: w3kw, asm: "VPXORD", typ: "Vec512", resultInArg0: true}, + {name: "VPXORQMasked128Merging", argLength: 4, reg: w3kw, asm: "VPXORQ", typ: "Vec128", resultInArg0: true}, + {name: "VPXORQMasked256Merging", argLength: 4, reg: w3kw, asm: "VPXORQ", typ: "Vec256", resultInArg0: true}, + {name: "VPXORQMasked512Merging", argLength: 4, reg: w3kw, asm: "VPXORQ", typ: "Vec512", resultInArg0: true}, + {name: "VRCP14PDMasked128Merging", argLength: 3, reg: w2kw, asm: "VRCP14PD", typ: "Vec128", resultInArg0: true}, + {name: "VRCP14PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VRCP14PD", typ: "Vec256", resultInArg0: true}, + {name: "VRCP14PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VRCP14PD", typ: "Vec512", resultInArg0: true}, + {name: "VRCP14PSMasked128Merging", argLength: 3, reg: w2kw, asm: "VRCP14PS", typ: "Vec128", resultInArg0: true}, + {name: "VRCP14PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VRCP14PS", typ: "Vec256", resultInArg0: true}, + {name: "VRCP14PSMasked512Merging", argLength: 3, reg: w2kw, asm: "VRCP14PS", typ: "Vec512", resultInArg0: true}, + {name: "VRSQRT14PDMasked128Merging", argLength: 3, reg: w2kw, asm: "VRSQRT14PD", typ: "Vec128", resultInArg0: true}, + {name: "VRSQRT14PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VRSQRT14PD", typ: "Vec256", resultInArg0: true}, + {name: "VRSQRT14PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VRSQRT14PD", typ: "Vec512", resultInArg0: true}, + {name: "VRSQRT14PSMasked128Merging", argLength: 3, reg: w2kw, asm: "VRSQRT14PS", typ: "Vec128", resultInArg0: true}, + {name: "VRSQRT14PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VRSQRT14PS", typ: "Vec256", resultInArg0: true}, + {name: "VRSQRT14PSMasked512Merging", argLength: 3, reg: w2kw, asm: "VRSQRT14PS", typ: "Vec512", resultInArg0: true}, + {name: "VSCALEFPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VSCALEFPD", typ: "Vec128", resultInArg0: true}, + {name: "VSCALEFPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VSCALEFPD", typ: "Vec256", resultInArg0: true}, + {name: "VSCALEFPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VSCALEFPD", typ: "Vec512", resultInArg0: true}, + {name: "VSCALEFPSMasked128Merging", argLength: 4, reg: w3kw, asm: "VSCALEFPS", typ: "Vec128", resultInArg0: true}, + {name: "VSCALEFPSMasked256Merging", argLength: 4, reg: w3kw, asm: "VSCALEFPS", typ: "Vec256", resultInArg0: true}, + {name: "VSCALEFPSMasked512Merging", argLength: 4, reg: w3kw, asm: "VSCALEFPS", typ: "Vec512", resultInArg0: true}, + {name: "VSQRTPDMasked128Merging", argLength: 3, reg: w2kw, asm: "VSQRTPD", typ: "Vec128", resultInArg0: true}, + {name: "VSQRTPDMasked256Merging", argLength: 3, reg: w2kw, asm: "VSQRTPD", typ: "Vec256", resultInArg0: true}, + {name: "VSQRTPDMasked512Merging", argLength: 3, reg: w2kw, asm: "VSQRTPD", typ: "Vec512", resultInArg0: true}, + {name: "VSQRTPSMasked128Merging", argLength: 3, reg: w2kw, asm: "VSQRTPS", typ: "Vec128", resultInArg0: true}, + {name: "VSQRTPSMasked256Merging", argLength: 3, reg: w2kw, asm: "VSQRTPS", typ: "Vec256", resultInArg0: true}, + {name: "VSQRTPSMasked512Merging", argLength: 3, reg: w2kw, asm: "VSQRTPS", typ: "Vec512", resultInArg0: true}, + {name: "VSUBPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VSUBPD", typ: "Vec128", resultInArg0: true}, + {name: "VSUBPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VSUBPD", typ: "Vec256", resultInArg0: true}, + {name: "VSUBPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VSUBPD", typ: "Vec512", resultInArg0: true}, + {name: "VSUBPSMasked128Merging", argLength: 4, reg: w3kw, asm: "VSUBPS", typ: "Vec128", resultInArg0: true}, + {name: "VSUBPSMasked256Merging", argLength: 4, reg: w3kw, asm: "VSUBPS", typ: "Vec256", resultInArg0: true}, + {name: "VSUBPSMasked512Merging", argLength: 4, reg: w3kw, asm: "VSUBPS", typ: "Vec512", resultInArg0: true}, + {name: "VPROLDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPROLD", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPROLDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPROLD", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPROLDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPROLD", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPROLQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPROLQ", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPROLQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPROLQ", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPROLQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPROLQ", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPRORDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPRORD", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPRORDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPRORD", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPRORDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPRORD", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPRORQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPRORQ", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPRORQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPRORQ", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPRORQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPRORQ", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSHUFDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPSHUFD", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSHUFDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPSHUFD", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSHUFDMasked512Merging", argLength: 3, reg: w2kw, asm: "VPSHUFD", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSHUFHWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPSHUFHW", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSHUFHWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPSHUFHW", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSHUFHWMasked512Merging", argLength: 3, reg: w2kw, asm: "VPSHUFHW", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSHUFLWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPSHUFLW", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSHUFLWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPSHUFLW", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSHUFLWMasked512Merging", argLength: 3, reg: w2kw, asm: "VPSHUFLW", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSLLDMasked128constMerging", argLength: 3, reg: w2kw, asm: "VPSLLD", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSLLDMasked256constMerging", argLength: 3, reg: w2kw, asm: "VPSLLD", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSLLDMasked512constMerging", argLength: 3, reg: w2kw, asm: "VPSLLD", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSLLQMasked128constMerging", argLength: 3, reg: w2kw, asm: "VPSLLQ", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSLLQMasked256constMerging", argLength: 3, reg: w2kw, asm: "VPSLLQ", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSLLQMasked512constMerging", argLength: 3, reg: w2kw, asm: "VPSLLQ", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSLLWMasked128constMerging", argLength: 3, reg: w2kw, asm: "VPSLLW", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSLLWMasked256constMerging", argLength: 3, reg: w2kw, asm: "VPSLLW", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSLLWMasked512constMerging", argLength: 3, reg: w2kw, asm: "VPSLLW", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSRADMasked128constMerging", argLength: 3, reg: w2kw, asm: "VPSRAD", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSRADMasked256constMerging", argLength: 3, reg: w2kw, asm: "VPSRAD", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSRADMasked512constMerging", argLength: 3, reg: w2kw, asm: "VPSRAD", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSRAQMasked128constMerging", argLength: 3, reg: w2kw, asm: "VPSRAQ", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSRAQMasked256constMerging", argLength: 3, reg: w2kw, asm: "VPSRAQ", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSRAQMasked512constMerging", argLength: 3, reg: w2kw, asm: "VPSRAQ", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSRAWMasked128constMerging", argLength: 3, reg: w2kw, asm: "VPSRAW", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSRAWMasked256constMerging", argLength: 3, reg: w2kw, asm: "VPSRAW", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSRAWMasked512constMerging", argLength: 3, reg: w2kw, asm: "VPSRAW", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSRLDMasked128constMerging", argLength: 3, reg: w2kw, asm: "VPSRLD", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSRLDMasked256constMerging", argLength: 3, reg: w2kw, asm: "VPSRLD", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSRLDMasked512constMerging", argLength: 3, reg: w2kw, asm: "VPSRLD", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSRLQMasked128constMerging", argLength: 3, reg: w2kw, asm: "VPSRLQ", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSRLQMasked256constMerging", argLength: 3, reg: w2kw, asm: "VPSRLQ", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSRLQMasked512constMerging", argLength: 3, reg: w2kw, asm: "VPSRLQ", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VPSRLWMasked128constMerging", argLength: 3, reg: w2kw, asm: "VPSRLW", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VPSRLWMasked256constMerging", argLength: 3, reg: w2kw, asm: "VPSRLW", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VPSRLWMasked512constMerging", argLength: 3, reg: w2kw, asm: "VPSRLW", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VREDUCEPDMasked128Merging", argLength: 3, reg: w2kw, asm: "VREDUCEPD", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VREDUCEPDMasked256Merging", argLength: 3, reg: w2kw, asm: "VREDUCEPD", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VREDUCEPDMasked512Merging", argLength: 3, reg: w2kw, asm: "VREDUCEPD", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VREDUCEPSMasked128Merging", argLength: 3, reg: w2kw, asm: "VREDUCEPS", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VREDUCEPSMasked256Merging", argLength: 3, reg: w2kw, asm: "VREDUCEPS", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VREDUCEPSMasked512Merging", argLength: 3, reg: w2kw, asm: "VREDUCEPS", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VRNDSCALEPDMasked128Merging", argLength: 3, reg: w2kw, asm: "VRNDSCALEPD", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VRNDSCALEPDMasked256Merging", argLength: 3, reg: w2kw, asm: "VRNDSCALEPD", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VRNDSCALEPDMasked512Merging", argLength: 3, reg: w2kw, asm: "VRNDSCALEPD", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + {name: "VRNDSCALEPSMasked128Merging", argLength: 3, reg: w2kw, asm: "VRNDSCALEPS", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VRNDSCALEPSMasked256Merging", argLength: 3, reg: w2kw, asm: "VRNDSCALEPS", aux: "UInt8", typ: "Vec256", resultInArg0: true}, + {name: "VRNDSCALEPSMasked512Merging", argLength: 3, reg: w2kw, asm: "VRNDSCALEPS", aux: "UInt8", typ: "Vec512", resultInArg0: true}, + } +} diff --git a/src/cmd/compile/internal/ssa/_gen/simdARM64.rules b/src/cmd/compile/internal/ssa/_gen/simdARM64.rules new file mode 100644 index 00000000000000..131ab8eff5da23 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/simdARM64.rules @@ -0,0 +1,437 @@ +// Code generated by 'simdgen -o godefs -goroot $GOROOT -arch arm64 -arm64Path $ARM64_ISA_PATH go_arm64.yaml types.yaml categories.yaml'; DO NOT EDIT. + +(VFCVTL4S (VDUPDextr [1] x)) => (VFCVTL2_4S x) +(VMOVDins0 [1] dst (VDUPDextr [0] (VFCVTN2D y))) => (VFCVTN2_2D dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VSHRN2D [c] y))) => (VSHRN2_2D dst [c] y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VSHRN4S [c] y))) => (VSHRN2_4S dst [c] y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VSHRN8H [c] y))) => (VSHRN2_8H dst [c] y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTN2D y))) => (VSQXTN2_2D dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTN4S y))) => (VSQXTN2_4S dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTN8H y))) => (VSQXTN2_8H dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTUN2D y))) => (VSQXTUN2_2D dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTUN4S y))) => (VSQXTUN2_4S dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTUN8H y))) => (VSQXTUN2_8H dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VUQXTN2D y))) => (VUQXTN2_2D dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VUQXTN4S y))) => (VUQXTN2_4S dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VUQXTN8H y))) => (VUQXTN2_8H dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VXTN2D y))) => (VXTN2_2D dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VXTN4S y))) => (VXTN2_4S dst y) +(VMOVDins0 [1] dst (VDUPDextr [0] (VXTN8H y))) => (VXTN2_8H dst y) +(VPMULL2D (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VPMULL2_2D x y) +(VSMULL16B (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VSMULL2_16B x y) +(VSMULL4S (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VSMULL2_4S x y) +(VSMULL8H (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VSMULL2_8H x y) +(VSSHLL16B [a] (VDUPDextr [1] x)) => (VSSHLL2_16B [a] x) +(VSSHLL4S [a] (VDUPDextr [1] x)) => (VSSHLL2_4S [a] x) +(VSSHLL8H [a] (VDUPDextr [1] x)) => (VSSHLL2_8H [a] x) +(VSXTL16B (VDUPDextr [1] x)) => (VSXTL2_16B x) +(VSXTL4S (VDUPDextr [1] x)) => (VSXTL2_4S x) +(VSXTL8H (VDUPDextr [1] x)) => (VSXTL2_8H x) +(VUMULL16B (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VUMULL2_16B x y) +(VUMULL4S (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VUMULL2_4S x y) +(VUMULL8H (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VUMULL2_8H x y) +(VUSHLL16B [a] (VDUPDextr [1] x)) => (VUSHLL2_16B [a] x) +(VUSHLL4S [a] (VDUPDextr [1] x)) => (VUSHLL2_4S [a] x) +(VUSHLL8H [a] (VDUPDextr [1] x)) => (VUSHLL2_8H [a] x) +(VUXTL16B (VDUPDextr [1] x)) => (VUXTL2_16B x) +(VUXTL4S (VDUPDextr [1] x)) => (VUXTL2_4S x) +(VUXTL8H (VDUPDextr [1] x)) => (VUXTL2_8H x) +(AbsFloat32x4 ...) => (VFABS4S ...) // pureVreg +(AbsFloat64x2 ...) => (VFABS2D ...) // pureVreg +(AbsInt8x16 ...) => (VABS16B ...) // pureVreg +(AbsInt16x8 ...) => (VABS8H ...) // pureVreg +(AbsInt32x4 ...) => (VABS4S ...) // pureVreg +(AbsInt64x2 ...) => (VABS2D ...) // pureVreg +(AddFloat32x4 ...) => (VFADD4S ...) // pureVreg +(AddFloat64x2 ...) => (VFADD2D ...) // pureVreg +(AddInt8x16 ...) => (VADD16B ...) // pureVreg +(AddInt16x8 ...) => (VADD8H ...) // pureVreg +(AddInt32x4 ...) => (VADD4S ...) // pureVreg +(AddInt64x2 ...) => (VADD2D ...) // pureVreg +(AddUint8x16 ...) => (VADD16B ...) // pureVreg +(AddUint16x8 ...) => (VADD8H ...) // pureVreg +(AddUint32x4 ...) => (VADD4S ...) // pureVreg +(AddUint64x2 ...) => (VADD2D ...) // pureVreg +(AddSaturatedInt8x16 ...) => (VSQADD16B ...) // pureVreg +(AddSaturatedInt16x8 ...) => (VSQADD8H ...) // pureVreg +(AddSaturatedInt32x4 ...) => (VSQADD4S ...) // pureVreg +(AddSaturatedInt64x2 ...) => (VSQADD2D ...) // pureVreg +(AddSaturatedUint8x16 ...) => (VUQADD16B ...) // pureVreg +(AddSaturatedUint16x8 ...) => (VUQADD8H ...) // pureVreg +(AddSaturatedUint32x4 ...) => (VUQADD4S ...) // pureVreg +(AddSaturatedUint64x2 ...) => (VUQADD2D ...) // pureVreg +(AndInt8x16 ...) => (VAND16B ...) // pureVreg +(AndInt16x8 ...) => (VAND16B ...) // pureVreg +(AndInt32x4 ...) => (VAND16B ...) // pureVreg +(AndInt64x2 ...) => (VAND16B ...) // pureVreg +(AndUint8x16 ...) => (VAND16B ...) // pureVreg +(AndUint16x8 ...) => (VAND16B ...) // pureVreg +(AndUint32x4 ...) => (VAND16B ...) // pureVreg +(AndUint64x2 ...) => (VAND16B ...) // pureVreg +(AndNotInt8x16 ...) => (VBIC16B ...) // pureVreg +(AndNotInt16x8 ...) => (VBIC16B ...) // pureVreg +(AndNotInt32x4 ...) => (VBIC16B ...) // pureVreg +(AndNotInt64x2 ...) => (VBIC16B ...) // pureVreg +(AndNotUint8x16 ...) => (VBIC16B ...) // pureVreg +(AndNotUint16x8 ...) => (VBIC16B ...) // pureVreg +(AndNotUint32x4 ...) => (VBIC16B ...) // pureVreg +(AndNotUint64x2 ...) => (VBIC16B ...) // pureVreg +(AverageInt8x16 ...) => (VSRHADD16B ...) // pureVreg +(AverageInt16x8 ...) => (VSRHADD8H ...) // pureVreg +(AverageInt32x4 ...) => (VSRHADD4S ...) // pureVreg +(AverageUint8x16 ...) => (VURHADD16B ...) // pureVreg +(AverageUint16x8 ...) => (VURHADD8H ...) // pureVreg +(AverageUint32x4 ...) => (VURHADD4S ...) // pureVreg +(CeilFloat32x4 ...) => (VFRINTP4S ...) // pureVreg +(CeilFloat64x2 ...) => (VFRINTP2D ...) // pureVreg +(ConcatAddPairsFloat32x4 ...) => (VFADDP4S ...) // pureVreg +(ConcatAddPairsFloat64x2 ...) => (VFADDP2D ...) // pureVreg +(ConcatAddPairsInt16x8 ...) => (VADDP8H ...) // pureVreg +(ConcatAddPairsInt32x4 ...) => (VADDP4S ...) // pureVreg +(ConcatAddPairsInt64x2 ...) => (VADDP2D ...) // pureVreg +(ConcatAddPairsUint16x8 ...) => (VADDP8H ...) // pureVreg +(ConcatAddPairsUint32x4 ...) => (VADDP4S ...) // pureVreg +(ConcatAddPairsUint64x2 ...) => (VADDP2D ...) // pureVreg +(ConcatEvenInt8x16 ...) => (VUZP116B ...) // pureVreg +(ConcatEvenInt16x8 ...) => (VUZP18H ...) // pureVreg +(ConcatEvenInt32x4 ...) => (VUZP14S ...) // pureVreg +(ConcatEvenInt64x2 ...) => (VUZP12D ...) // pureVreg +(ConcatEvenUint8x16 ...) => (VUZP116B ...) // pureVreg +(ConcatEvenUint16x8 ...) => (VUZP18H ...) // pureVreg +(ConcatEvenUint32x4 ...) => (VUZP14S ...) // pureVreg +(ConcatEvenUint64x2 ...) => (VUZP12D ...) // pureVreg +(ConcatOddInt8x16 ...) => (VUZP216B ...) // pureVreg +(ConcatOddInt16x8 ...) => (VUZP28H ...) // pureVreg +(ConcatOddInt32x4 ...) => (VUZP24S ...) // pureVreg +(ConcatOddInt64x2 ...) => (VUZP22D ...) // pureVreg +(ConcatOddUint8x16 ...) => (VUZP216B ...) // pureVreg +(ConcatOddUint16x8 ...) => (VUZP28H ...) // pureVreg +(ConcatOddUint32x4 ...) => (VUZP24S ...) // pureVreg +(ConcatOddUint64x2 ...) => (VUZP22D ...) // pureVreg +(ConcatShiftBytesRightUint8x16 ...) => (VEXT16B ...) // pureVreg +(ConvertLo2ToFloat64Float32x4 ...) => (VFCVTL4S ...) // pureVreg +(ConvertToFloat32Float64x2 ...) => (VFCVTN2D ...) // pureVreg +(ConvertToFloat32Int32x4 ...) => (VSCVTF4S ...) // pureVreg +(ConvertToFloat32Uint32x4 ...) => (VUCVTF4S ...) // pureVreg +(ConvertToFloat64Int64x2 ...) => (VSCVTF2D ...) // pureVreg +(ConvertToFloat64Uint64x2 ...) => (VUCVTF2D ...) // pureVreg +(ConvertToInt32Float32x4 ...) => (VFCVTZS4S ...) // pureVreg +(ConvertToInt64Float64x2 ...) => (VFCVTZS2D ...) // pureVreg +(ConvertToUint32Float32x4 ...) => (VFCVTZU4S ...) // pureVreg +(ConvertToUint64Float64x2 ...) => (VFCVTZU2D ...) // pureVreg +(DivFloat32x4 ...) => (VFDIV4S ...) // pureVreg +(DivFloat64x2 ...) => (VFDIV2D ...) // pureVreg +(EqualFloat32x4 ...) => (VFCMEQ4S ...) // pureVreg +(EqualFloat64x2 ...) => (VFCMEQ2D ...) // pureVreg +(EqualInt8x16 ...) => (VCMEQ16B ...) // pureVreg +(EqualInt16x8 ...) => (VCMEQ8H ...) // pureVreg +(EqualInt32x4 ...) => (VCMEQ4S ...) // pureVreg +(EqualInt64x2 ...) => (VCMEQ2D ...) // pureVreg +(EqualUint8x16 ...) => (VCMEQ16B ...) // pureVreg +(EqualUint16x8 ...) => (VCMEQ8H ...) // pureVreg +(EqualUint32x4 ...) => (VCMEQ4S ...) // pureVreg +(EqualUint64x2 ...) => (VCMEQ2D ...) // pureVreg +(ExtendLo2ToInt64Int32x4 ...) => (VSXTL4S ...) // pureVreg +(ExtendLo2ToUint64Uint32x4 ...) => (VUXTL4S ...) // pureVreg +(ExtendLo4ToInt32Int16x8 ...) => (VSXTL8H ...) // pureVreg +(ExtendLo4ToUint32Uint16x8 ...) => (VUXTL8H ...) // pureVreg +(ExtendLo8ToInt16Int8x16 ...) => (VSXTL16B ...) // pureVreg +(ExtendLo8ToUint16Uint8x16 ...) => (VUXTL16B ...) // pureVreg +(FloorFloat32x4 ...) => (VFRINTM4S ...) // pureVreg +(FloorFloat64x2 ...) => (VFRINTM2D ...) // pureVreg +(GetElemFloat32x4 ...) => (VDUPSextr ...) // pureVreg +(GetElemFloat64x2 ...) => (VDUPDextr ...) // pureVreg +(GetElemInt8x16 ...) => (VMOVBextr ...) // pureVreg +(GetElemInt16x8 ...) => (VMOVHextr ...) // pureVreg +(GetElemInt32x4 ...) => (VMOVSextr ...) // pureVreg +(GetElemInt64x2 ...) => (VMOVDextr ...) // pureVreg +(GetElemUint8x16 ...) => (VMOVBextr ...) // pureVreg +(GetElemUint16x8 ...) => (VMOVHextr ...) // pureVreg +(GetElemUint32x4 ...) => (VMOVSextr ...) // pureVreg +(GetElemUint64x2 ...) => (VMOVDextr ...) // pureVreg +(GreaterFloat32x4 ...) => (VFCMGT4S ...) // pureVreg +(GreaterFloat64x2 ...) => (VFCMGT2D ...) // pureVreg +(GreaterInt8x16 ...) => (VCMGT16B ...) // pureVreg +(GreaterInt16x8 ...) => (VCMGT8H ...) // pureVreg +(GreaterInt32x4 ...) => (VCMGT4S ...) // pureVreg +(GreaterInt64x2 ...) => (VCMGT2D ...) // pureVreg +(GreaterUint8x16 ...) => (VCMHI16B ...) // pureVreg +(GreaterUint16x8 ...) => (VCMHI8H ...) // pureVreg +(GreaterUint32x4 ...) => (VCMHI4S ...) // pureVreg +(GreaterUint64x2 ...) => (VCMHI2D ...) // pureVreg +(GreaterEqualFloat32x4 ...) => (VFCMGE4S ...) // pureVreg +(GreaterEqualFloat64x2 ...) => (VFCMGE2D ...) // pureVreg +(GreaterEqualInt8x16 ...) => (VCMGE16B ...) // pureVreg +(GreaterEqualInt16x8 ...) => (VCMGE8H ...) // pureVreg +(GreaterEqualInt32x4 ...) => (VCMGE4S ...) // pureVreg +(GreaterEqualInt64x2 ...) => (VCMGE2D ...) // pureVreg +(GreaterEqualUint8x16 ...) => (VCMHS16B ...) // pureVreg +(GreaterEqualUint16x8 ...) => (VCMHS8H ...) // pureVreg +(GreaterEqualUint32x4 ...) => (VCMHS4S ...) // pureVreg +(GreaterEqualUint64x2 ...) => (VCMHS2D ...) // pureVreg +(InterleaveEvenInt8x16 ...) => (VTRN116B ...) // pureVreg +(InterleaveEvenInt16x8 ...) => (VTRN18H ...) // pureVreg +(InterleaveEvenInt32x4 ...) => (VTRN14S ...) // pureVreg +(InterleaveEvenInt64x2 ...) => (VTRN12D ...) // pureVreg +(InterleaveEvenUint8x16 ...) => (VTRN116B ...) // pureVreg +(InterleaveEvenUint16x8 ...) => (VTRN18H ...) // pureVreg +(InterleaveEvenUint32x4 ...) => (VTRN14S ...) // pureVreg +(InterleaveEvenUint64x2 ...) => (VTRN12D ...) // pureVreg +(InterleaveHiInt8x16 ...) => (VZIP216B ...) // pureVreg +(InterleaveHiInt16x8 ...) => (VZIP28H ...) // pureVreg +(InterleaveHiInt32x4 ...) => (VZIP24S ...) // pureVreg +(InterleaveHiInt64x2 ...) => (VZIP22D ...) // pureVreg +(InterleaveHiUint8x16 ...) => (VZIP216B ...) // pureVreg +(InterleaveHiUint16x8 ...) => (VZIP28H ...) // pureVreg +(InterleaveHiUint32x4 ...) => (VZIP24S ...) // pureVreg +(InterleaveHiUint64x2 ...) => (VZIP22D ...) // pureVreg +(InterleaveLoInt8x16 ...) => (VZIP116B ...) // pureVreg +(InterleaveLoInt16x8 ...) => (VZIP18H ...) // pureVreg +(InterleaveLoInt32x4 ...) => (VZIP14S ...) // pureVreg +(InterleaveLoInt64x2 ...) => (VZIP12D ...) // pureVreg +(InterleaveLoUint8x16 ...) => (VZIP116B ...) // pureVreg +(InterleaveLoUint16x8 ...) => (VZIP18H ...) // pureVreg +(InterleaveLoUint32x4 ...) => (VZIP14S ...) // pureVreg +(InterleaveLoUint64x2 ...) => (VZIP12D ...) // pureVreg +(InterleaveOddInt8x16 ...) => (VTRN216B ...) // pureVreg +(InterleaveOddInt16x8 ...) => (VTRN28H ...) // pureVreg +(InterleaveOddInt32x4 ...) => (VTRN24S ...) // pureVreg +(InterleaveOddInt64x2 ...) => (VTRN22D ...) // pureVreg +(InterleaveOddUint8x16 ...) => (VTRN216B ...) // pureVreg +(InterleaveOddUint16x8 ...) => (VTRN28H ...) // pureVreg +(InterleaveOddUint32x4 ...) => (VTRN24S ...) // pureVreg +(InterleaveOddUint64x2 ...) => (VTRN22D ...) // pureVreg +(LeadingSignBitsInt8x16 ...) => (VCLS16B ...) // pureVreg +(LeadingSignBitsInt16x8 ...) => (VCLS8H ...) // pureVreg +(LeadingSignBitsInt32x4 ...) => (VCLS4S ...) // pureVreg +(LeadingSignBitsUint8x16 ...) => (VCLS16B ...) // pureVreg +(LeadingSignBitsUint16x8 ...) => (VCLS8H ...) // pureVreg +(LeadingSignBitsUint32x4 ...) => (VCLS4S ...) // pureVreg +(LeadingZerosInt8x16 ...) => (VCLZ16B ...) // pureVreg +(LeadingZerosInt16x8 ...) => (VCLZ8H ...) // pureVreg +(LeadingZerosInt32x4 ...) => (VCLZ4S ...) // pureVreg +(LeadingZerosUint8x16 ...) => (VCLZ16B ...) // pureVreg +(LeadingZerosUint16x8 ...) => (VCLZ8H ...) // pureVreg +(LeadingZerosUint32x4 ...) => (VCLZ4S ...) // pureVreg +(LookupOrZeroInt8x16 ...) => (VTBL16B ...) // pureVreg +(LookupOrZeroUint8x16 ...) => (VTBL16B ...) // pureVreg +(MaxFloat32x4 ...) => (VFMAX4S ...) // pureVreg +(MaxFloat64x2 ...) => (VFMAX2D ...) // pureVreg +(MaxInt8x16 ...) => (VSMAX16B ...) // pureVreg +(MaxInt16x8 ...) => (VSMAX8H ...) // pureVreg +(MaxInt32x4 ...) => (VSMAX4S ...) // pureVreg +(MaxUint8x16 ...) => (VUMAX16B ...) // pureVreg +(MaxUint16x8 ...) => (VUMAX8H ...) // pureVreg +(MaxUint32x4 ...) => (VUMAX4S ...) // pureVreg +(MinFloat32x4 ...) => (VFMIN4S ...) // pureVreg +(MinFloat64x2 ...) => (VFMIN2D ...) // pureVreg +(MinInt8x16 ...) => (VSMIN16B ...) // pureVreg +(MinInt16x8 ...) => (VSMIN8H ...) // pureVreg +(MinInt32x4 ...) => (VSMIN4S ...) // pureVreg +(MinUint8x16 ...) => (VUMIN16B ...) // pureVreg +(MinUint16x8 ...) => (VUMIN8H ...) // pureVreg +(MinUint32x4 ...) => (VUMIN4S ...) // pureVreg +(MulFloat32x4 ...) => (VFMUL4S ...) // pureVreg +(MulFloat64x2 ...) => (VFMUL2D ...) // pureVreg +(MulInt8x16 ...) => (VMUL16B ...) // pureVreg +(MulInt16x8 ...) => (VMUL8H ...) // pureVreg +(MulInt32x4 ...) => (VMUL4S ...) // pureVreg +(MulUint8x16 ...) => (VMUL16B ...) // pureVreg +(MulUint16x8 ...) => (VMUL8H ...) // pureVreg +(MulUint32x4 ...) => (VMUL4S ...) // pureVreg +(MulAddFloat32x4 x y z) => (VFMLA4S z x y) // specialLower +(MulAddFloat64x2 x y z) => (VFMLA2D z x y) // specialLower +(MulAddInt8x16 x y z) => (VMLA16B z x y) // specialLower +(MulAddInt16x8 x y z) => (VMLA8H z x y) // specialLower +(MulAddInt32x4 x y z) => (VMLA4S z x y) // specialLower +(MulAddUint8x16 x y z) => (VMLA16B z x y) // specialLower +(MulAddUint16x8 x y z) => (VMLA8H z x y) // specialLower +(MulAddUint32x4 x y z) => (VMLA4S z x y) // specialLower +(MulWidenLoInt8x16 ...) => (VSMULL16B ...) // pureVreg +(MulWidenLoInt16x8 ...) => (VSMULL8H ...) // pureVreg +(MulWidenLoInt32x4 ...) => (VSMULL4S ...) // pureVreg +(MulWidenLoUint8x16 ...) => (VUMULL16B ...) // pureVreg +(MulWidenLoUint16x8 ...) => (VUMULL8H ...) // pureVreg +(MulWidenLoUint32x4 ...) => (VUMULL4S ...) // pureVreg +(NegFloat32x4 ...) => (VFNEG4S ...) // pureVreg +(NegFloat64x2 ...) => (VFNEG2D ...) // pureVreg +(NegInt8x16 ...) => (VNEG16B ...) // pureVreg +(NegInt16x8 ...) => (VNEG8H ...) // pureVreg +(NegInt32x4 ...) => (VNEG4S ...) // pureVreg +(NegInt64x2 ...) => (VNEG2D ...) // pureVreg +(NotInt8x16 ...) => (VNOT16B ...) // pureVreg +(NotInt16x8 ...) => (VNOT16B ...) // pureVreg +(NotInt32x4 ...) => (VNOT16B ...) // pureVreg +(NotInt64x2 ...) => (VNOT16B ...) // pureVreg +(NotUint8x16 ...) => (VNOT16B ...) // pureVreg +(NotUint16x8 ...) => (VNOT16B ...) // pureVreg +(NotUint32x4 ...) => (VNOT16B ...) // pureVreg +(NotUint64x2 ...) => (VNOT16B ...) // pureVreg +(OnesCountInt8x16 ...) => (VCNT16B ...) // pureVreg +(OnesCountUint8x16 ...) => (VCNT16B ...) // pureVreg +(OrInt8x16 ...) => (VORR16B ...) // pureVreg +(OrInt16x8 ...) => (VORR16B ...) // pureVreg +(OrInt32x4 ...) => (VORR16B ...) // pureVreg +(OrInt64x2 ...) => (VORR16B ...) // pureVreg +(OrUint8x16 ...) => (VORR16B ...) // pureVreg +(OrUint16x8 ...) => (VORR16B ...) // pureVreg +(OrUint32x4 ...) => (VORR16B ...) // pureVreg +(OrUint64x2 ...) => (VORR16B ...) // pureVreg +(OrNotInt8x16 ...) => (VORN16B ...) // pureVreg +(OrNotInt16x8 ...) => (VORN16B ...) // pureVreg +(OrNotInt32x4 ...) => (VORN16B ...) // pureVreg +(OrNotInt64x2 ...) => (VORN16B ...) // pureVreg +(OrNotUint8x16 ...) => (VORN16B ...) // pureVreg +(OrNotUint16x8 ...) => (VORN16B ...) // pureVreg +(OrNotUint32x4 ...) => (VORN16B ...) // pureVreg +(OrNotUint64x2 ...) => (VORN16B ...) // pureVreg +(RoundFloat32x4 ...) => (VFRINTN4S ...) // pureVreg +(RoundFloat64x2 ...) => (VFRINTN2D ...) // pureVreg +(SaturateToInt8Int16x8 ...) => (VSQXTN8H ...) // pureVreg +(SaturateToInt16Int32x4 ...) => (VSQXTN4S ...) // pureVreg +(SaturateToInt32Int64x2 ...) => (VSQXTN2D ...) // pureVreg +(SaturateToUint8Int16x8 ...) => (VSQXTUN8H ...) // pureVreg +(SaturateToUint8Uint16x8 ...) => (VUQXTN8H ...) // pureVreg +(SaturateToUint16Int32x4 ...) => (VSQXTUN4S ...) // pureVreg +(SaturateToUint16Uint32x4 ...) => (VUQXTN4S ...) // pureVreg +(SaturateToUint32Int64x2 ...) => (VSQXTUN2D ...) // pureVreg +(SaturateToUint32Uint64x2 ...) => (VUQXTN2D ...) // pureVreg +(SetElemFloat32x4 ...) => (VMOVSins0 ...) // pureVreg +(VMOVSins0 [0] (VMOVI16B [0]) y:(VDUPSextr [i] _)) => y // specialLower +(SetElemFloat64x2 ...) => (VMOVDins0 ...) // pureVreg +(VMOVDins0 [0] (VMOVI16B [0]) y:(VDUPDextr [i] _)) => y // specialLower +(SetElemInt8x16 ...) => (VMOVBins ...) // pureVreg +(SetElemInt16x8 ...) => (VMOVHins ...) // pureVreg +(SetElemInt32x4 ...) => (VMOVSins ...) // pureVreg +(SetElemInt64x2 ...) => (VMOVDins ...) // pureVreg +(SetElemUint8x16 ...) => (VMOVBins ...) // pureVreg +(SetElemUint16x8 ...) => (VMOVHins ...) // pureVreg +(SetElemUint32x4 ...) => (VMOVSins ...) // pureVreg +(SetElemUint64x2 ...) => (VMOVDins ...) // pureVreg +(ShiftInt8x16 ...) => (VSSHL16B ...) // pureVreg +(ShiftInt16x8 ...) => (VSSHL8H ...) // pureVreg +(ShiftInt32x4 ...) => (VSSHL4S ...) // pureVreg +(ShiftInt64x2 ...) => (VSSHL2D ...) // pureVreg +(ShiftUint8x16 ...) => (VUSHL16B ...) // pureVreg +(ShiftUint16x8 ...) => (VUSHL8H ...) // pureVreg +(ShiftUint32x4 ...) => (VUSHL4S ...) // pureVreg +(ShiftUint64x2 ...) => (VUSHL2D ...) // pureVreg +(ShiftAllLeftInt8x16 x y) => (VSSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower +(ShiftAllLeftInt16x8 x y) => (VSSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower +(ShiftAllLeftInt32x4 x y) => (VSSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower +(ShiftAllLeftInt64x2 x y) => (VSSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower +(ShiftAllLeftUint8x16 x y) => (VUSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower +(ShiftAllLeftUint16x8 x y) => (VUSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower +(ShiftAllLeftUint32x4 x y) => (VUSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower +(ShiftAllLeftUint64x2 x y) => (VUSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower +(ShiftAllRightInt8x16 x y) => (VSSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower +(ShiftAllRightInt16x8 x y) => (VSSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower +(ShiftAllRightInt32x4 x y) => (VSSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower +(ShiftAllRightInt64x2 x y) => (VSSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower +(ShiftAllRightUint8x16 x y) => (VUSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower +(ShiftAllRightUint16x8 x y) => (VUSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower +(ShiftAllRightUint32x4 x y) => (VUSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower +(ShiftAllRightUint64x2 x y) => (VUSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower +(ShiftSaturatedInt8x16 ...) => (VSQSHL16B ...) // pureVreg +(ShiftSaturatedInt16x8 ...) => (VSQSHL8H ...) // pureVreg +(ShiftSaturatedInt32x4 ...) => (VSQSHL4S ...) // pureVreg +(ShiftSaturatedInt64x2 ...) => (VSQSHL2D ...) // pureVreg +(ShiftSaturatedUint8x16 ...) => (VUQSHL16B ...) // pureVreg +(ShiftSaturatedUint16x8 ...) => (VUQSHL8H ...) // pureVreg +(ShiftSaturatedUint32x4 ...) => (VUQSHL4S ...) // pureVreg +(ShiftSaturatedUint64x2 ...) => (VUQSHL2D ...) // pureVreg +(SqrtFloat32x4 ...) => (VFSQRT4S ...) // pureVreg +(SqrtFloat64x2 ...) => (VFSQRT2D ...) // pureVreg +(SubFloat32x4 ...) => (VFSUB4S ...) // pureVreg +(SubFloat64x2 ...) => (VFSUB2D ...) // pureVreg +(SubInt8x16 ...) => (VSUB16B ...) // pureVreg +(SubInt16x8 ...) => (VSUB8H ...) // pureVreg +(SubInt32x4 ...) => (VSUB4S ...) // pureVreg +(SubInt64x2 ...) => (VSUB2D ...) // pureVreg +(SubUint8x16 ...) => (VSUB16B ...) // pureVreg +(SubUint16x8 ...) => (VSUB8H ...) // pureVreg +(SubUint32x4 ...) => (VSUB4S ...) // pureVreg +(SubUint64x2 ...) => (VSUB2D ...) // pureVreg +(SubSaturatedInt8x16 ...) => (VSQSUB16B ...) // pureVreg +(SubSaturatedInt16x8 ...) => (VSQSUB8H ...) // pureVreg +(SubSaturatedInt32x4 ...) => (VSQSUB4S ...) // pureVreg +(SubSaturatedInt64x2 ...) => (VSQSUB2D ...) // pureVreg +(SubSaturatedUint8x16 ...) => (VUQSUB16B ...) // pureVreg +(SubSaturatedUint16x8 ...) => (VUQSUB8H ...) // pureVreg +(SubSaturatedUint32x4 ...) => (VUQSUB4S ...) // pureVreg +(SubSaturatedUint64x2 ...) => (VUQSUB2D ...) // pureVreg +(TruncFloat32x4 ...) => (VFRINTZ4S ...) // pureVreg +(TruncFloat64x2 ...) => (VFRINTZ2D ...) // pureVreg +(TruncToInt8Int16x8 ...) => (VXTN8H ...) // pureVreg +(TruncToInt16Int32x4 ...) => (VXTN4S ...) // pureVreg +(TruncToInt32Int64x2 ...) => (VXTN2D ...) // pureVreg +(TruncToUint8Uint16x8 ...) => (VXTN8H ...) // pureVreg +(TruncToUint16Uint32x4 ...) => (VXTN4S ...) // pureVreg +(TruncToUint32Uint64x2 ...) => (VXTN2D ...) // pureVreg +(XorInt8x16 ...) => (VEOR16B ...) // pureVreg +(XorInt16x8 ...) => (VEOR16B ...) // pureVreg +(XorInt32x4 ...) => (VEOR16B ...) // pureVreg +(XorInt64x2 ...) => (VEOR16B ...) // pureVreg +(XorUint8x16 ...) => (VEOR16B ...) // pureVreg +(XorUint16x8 ...) => (VEOR16B ...) // pureVreg +(XorUint32x4 ...) => (VEOR16B ...) // pureVreg +(XorUint64x2 ...) => (VEOR16B ...) // pureVreg +(bitSelectInt8x16 ...) => (VBIF16B ...) // pureVreg +(VBIF16B x y (VNOT16B mask)) => (VBIT16B x y mask) // specialLower +(bitSelectNotInt8x16 ...) => (VBIT16B ...) // pureVreg +(VBIT16B x y (VNOT16B mask)) => (VBIF16B x y mask) // specialLower +(broadcast1To2Float64x2 x) => (VDUPDbcast [0] x) // pureVreg +(broadcast1To2Int64x2 x) => (VDUPDbcast [0] x) // pureVreg +(broadcast1To2Uint64x2 x) => (VDUPDbcast [0] x) // pureVreg +(broadcast1To4Float32x4 x) => (VDUPSbcast [0] x) // pureVreg +(broadcast1To4Int32x4 x) => (VDUPSbcast [0] x) // pureVreg +(broadcast1To4Uint32x4 x) => (VDUPSbcast [0] x) // pureVreg +(broadcast1To8Int16x8 x) => (VDUPHbcast [0] x) // pureVreg +(broadcast1To8Uint16x8 x) => (VDUPHbcast [0] x) // pureVreg +(broadcast1To16Int8x16 x) => (VDUPBbcast [0] x) // pureVreg +(VDUPBbcast [i] (VMOVBins [j] _ (MOVDconst [c]))) && i == j && c>=-128 && c<=255 => (VMOVI16B [uint8(c)]) // specialLower +(broadcast1To16Uint8x16 x) => (VDUPBbcast [0] x) // pureVreg +(carrylessMultiplyWidenLoUint64x2 ...) => (VPMULL2D ...) // pureVreg +(reduceMaxFloat32x4 ...) => (VFMAXV4S ...) // pureVreg +(reduceMaxInt8x16 ...) => (VSMAXV16B ...) // pureVreg +(reduceMaxInt16x8 ...) => (VSMAXV8H ...) // pureVreg +(reduceMaxInt32x4 ...) => (VSMAXV4S ...) // pureVreg +(reduceMaxUint8x16 ...) => (VUMAXV16B ...) // pureVreg +(reduceMaxUint16x8 ...) => (VUMAXV8H ...) // pureVreg +(reduceMaxUint32x4 ...) => (VUMAXV4S ...) // pureVreg +(reduceMinFloat32x4 ...) => (VFMINV4S ...) // pureVreg +(reduceMinInt8x16 ...) => (VSMINV16B ...) // pureVreg +(reduceMinInt16x8 ...) => (VSMINV8H ...) // pureVreg +(reduceMinInt32x4 ...) => (VSMINV4S ...) // pureVreg +(reduceMinUint8x16 ...) => (VUMINV16B ...) // pureVreg +(reduceMinUint16x8 ...) => (VUMINV8H ...) // pureVreg +(reduceMinUint32x4 ...) => (VUMINV4S ...) // pureVreg +(reduceSumInt8x16 ...) => (VADDV16B ...) // pureVreg +(reduceSumInt16x8 ...) => (VADDV8H ...) // pureVreg +(reduceSumInt32x4 ...) => (VADDV4S ...) // pureVreg +(reduceSumUint8x16 ...) => (VADDV16B ...) // pureVreg +(reduceSumUint16x8 ...) => (VADDV8H ...) // pureVreg +(reduceSumUint32x4 ...) => (VADDV4S ...) // pureVreg +(VSHL16B [a] x) && a==0 => x // asmRule +(VSHL8H [a] x) && a==0 => x // asmRule +(VSHL4S [a] x) && a==0 => x // asmRule +(VSHL2D [a] x) && a==0 => x // asmRule +(VSSHR16B [a] x) && a==0 => x // asmRule +(VSSHR8H [a] x) && a==0 => x // asmRule +(VSSHR4S [a] x) && a==0 => x // asmRule +(VSSHR2D [a] x) && a==0 => x // asmRule +(VUSHR16B [a] x) && a==0 => x // asmRule +(VUSHR8H [a] x) && a==0 => x // asmRule +(VUSHR4S [a] x) && a==0 => x // asmRule +(VUSHR2D [a] x) && a==0 => x // asmRule +(VSQSHL16Bconst [a] x) && a==0 => x // asmRule +(VSQSHL8Hconst [a] x) && a==0 => x // asmRule +(VSQSHL4Sconst [a] x) && a==0 => x // asmRule +(VSQSHL2Dconst [a] x) && a==0 => x // asmRule +(VUQSHL16Bconst [a] x) && a==0 => x // asmRule +(VUQSHL8Hconst [a] x) && a==0 => x // asmRule +(VUQSHL4Sconst [a] x) && a==0 => x // asmRule +(VUQSHL2Dconst [a] x) && a==0 => x // asmRule +(VSHRN8H [0] x) => (VXTN8H x) // specialLower +(VSHRN4S [0] x) => (VXTN4S x) // specialLower +(VSHRN2D [0] x) => (VXTN2D x) // specialLower diff --git a/src/cmd/compile/internal/ssa/_gen/simdARM64ops.go b/src/cmd/compile/internal/ssa/_gen/simdARM64ops.go new file mode 100644 index 00000000000000..3d4907a00f2ddc --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/simdARM64ops.go @@ -0,0 +1,314 @@ +// Code generated by 'simdgen -o godefs -goroot $GOROOT -arch arm64 -arm64Path $ARM64_ISA_PATH go_arm64.yaml types.yaml categories.yaml'; DO NOT EDIT. + +package main + +func simdARM64Ops(v11, v21, v31, vgp, vgpv, vfpv regInfo) []opData { + return []opData{ + {name: "VABS2D", argLength: 1, reg: v11, asm: "VABS", typ: "Vec128"}, + {name: "VABS4S", argLength: 1, reg: v11, asm: "VABS", typ: "Vec128"}, + {name: "VABS8H", argLength: 1, reg: v11, asm: "VABS", typ: "Vec128"}, + {name: "VABS16B", argLength: 1, reg: v11, asm: "VABS", typ: "Vec128"}, + {name: "VADD2D", argLength: 2, reg: v21, asm: "VADD", commutative: true, typ: "Vec128"}, + {name: "VADD4S", argLength: 2, reg: v21, asm: "VADD", commutative: true, typ: "Vec128"}, + {name: "VADD8H", argLength: 2, reg: v21, asm: "VADD", commutative: true, typ: "Vec128"}, + {name: "VADD16B", argLength: 2, reg: v21, asm: "VADD", commutative: true, typ: "Vec128"}, + {name: "VADDP2D", argLength: 2, reg: v21, asm: "VADDP", typ: "Vec128"}, + {name: "VADDP4S", argLength: 2, reg: v21, asm: "VADDP", typ: "Vec128"}, + {name: "VADDP8H", argLength: 2, reg: v21, asm: "VADDP", typ: "Vec128"}, + {name: "VADDV4S", argLength: 1, reg: v11, asm: "VADDV", typ: "Vec128"}, + {name: "VADDV8H", argLength: 1, reg: v11, asm: "VADDV", typ: "Vec128"}, + {name: "VADDV16B", argLength: 1, reg: v11, asm: "VADDV", typ: "Vec128"}, + {name: "VAND16B", argLength: 2, reg: v21, asm: "VAND", commutative: true, typ: "Vec128"}, + {name: "VBIC16B", argLength: 2, reg: v21, asm: "VBIC", typ: "Vec128"}, + {name: "VBIF16B", argLength: 3, reg: v31, asm: "VBIF", typ: "Vec128", resultInArg0: true}, + {name: "VBIT16B", argLength: 3, reg: v31, asm: "VBIT", typ: "Vec128", resultInArg0: true}, + {name: "VCLS4S", argLength: 1, reg: v11, asm: "VCLS", typ: "Vec128"}, + {name: "VCLS8H", argLength: 1, reg: v11, asm: "VCLS", typ: "Vec128"}, + {name: "VCLS16B", argLength: 1, reg: v11, asm: "VCLS", typ: "Vec128"}, + {name: "VCLZ4S", argLength: 1, reg: v11, asm: "VCLZ", typ: "Vec128"}, + {name: "VCLZ8H", argLength: 1, reg: v11, asm: "VCLZ", typ: "Vec128"}, + {name: "VCLZ16B", argLength: 1, reg: v11, asm: "VCLZ", typ: "Vec128"}, + {name: "VCMEQ2D", argLength: 2, reg: v21, asm: "VCMEQ", commutative: true, typ: "Vec128"}, + {name: "VCMEQ4S", argLength: 2, reg: v21, asm: "VCMEQ", commutative: true, typ: "Vec128"}, + {name: "VCMEQ8H", argLength: 2, reg: v21, asm: "VCMEQ", commutative: true, typ: "Vec128"}, + {name: "VCMEQ16B", argLength: 2, reg: v21, asm: "VCMEQ", commutative: true, typ: "Vec128"}, + {name: "VCMGE2D", argLength: 2, reg: v21, asm: "VCMGE", typ: "Vec128"}, + {name: "VCMGE4S", argLength: 2, reg: v21, asm: "VCMGE", typ: "Vec128"}, + {name: "VCMGE8H", argLength: 2, reg: v21, asm: "VCMGE", typ: "Vec128"}, + {name: "VCMGE16B", argLength: 2, reg: v21, asm: "VCMGE", typ: "Vec128"}, + {name: "VCMGT2D", argLength: 2, reg: v21, asm: "VCMGT", typ: "Vec128"}, + {name: "VCMGT4S", argLength: 2, reg: v21, asm: "VCMGT", typ: "Vec128"}, + {name: "VCMGT8H", argLength: 2, reg: v21, asm: "VCMGT", typ: "Vec128"}, + {name: "VCMGT16B", argLength: 2, reg: v21, asm: "VCMGT", typ: "Vec128"}, + {name: "VCMHI2D", argLength: 2, reg: v21, asm: "VCMHI", typ: "Vec128"}, + {name: "VCMHI4S", argLength: 2, reg: v21, asm: "VCMHI", typ: "Vec128"}, + {name: "VCMHI8H", argLength: 2, reg: v21, asm: "VCMHI", typ: "Vec128"}, + {name: "VCMHI16B", argLength: 2, reg: v21, asm: "VCMHI", typ: "Vec128"}, + {name: "VCMHS2D", argLength: 2, reg: v21, asm: "VCMHS", typ: "Vec128"}, + {name: "VCMHS4S", argLength: 2, reg: v21, asm: "VCMHS", typ: "Vec128"}, + {name: "VCMHS8H", argLength: 2, reg: v21, asm: "VCMHS", typ: "Vec128"}, + {name: "VCMHS16B", argLength: 2, reg: v21, asm: "VCMHS", typ: "Vec128"}, + {name: "VCNT16B", argLength: 1, reg: v11, asm: "VCNT", typ: "Vec128"}, + {name: "VEOR16B", argLength: 2, reg: v21, asm: "VEOR", commutative: true, typ: "Vec128"}, + {name: "VFABS2D", argLength: 1, reg: v11, asm: "VFABS", typ: "Vec128"}, + {name: "VFABS4S", argLength: 1, reg: v11, asm: "VFABS", typ: "Vec128"}, + {name: "VFADD2D", argLength: 2, reg: v21, asm: "VFADD", commutative: true, typ: "Vec128"}, + {name: "VFADD4S", argLength: 2, reg: v21, asm: "VFADD", commutative: true, typ: "Vec128"}, + {name: "VFADDP2D", argLength: 2, reg: v21, asm: "VFADDP", typ: "Vec128"}, + {name: "VFADDP4S", argLength: 2, reg: v21, asm: "VFADDP", typ: "Vec128"}, + {name: "VFCMEQ2D", argLength: 2, reg: v21, asm: "VFCMEQ", commutative: true, typ: "Vec128"}, + {name: "VFCMEQ4S", argLength: 2, reg: v21, asm: "VFCMEQ", commutative: true, typ: "Vec128"}, + {name: "VFCMGE2D", argLength: 2, reg: v21, asm: "VFCMGE", typ: "Vec128"}, + {name: "VFCMGE4S", argLength: 2, reg: v21, asm: "VFCMGE", typ: "Vec128"}, + {name: "VFCMGT2D", argLength: 2, reg: v21, asm: "VFCMGT", typ: "Vec128"}, + {name: "VFCMGT4S", argLength: 2, reg: v21, asm: "VFCMGT", typ: "Vec128"}, + {name: "VFCVTL2_4S", argLength: 1, reg: v11, asm: "VFCVTL2", typ: "Vec128"}, + {name: "VFCVTL4S", argLength: 1, reg: v11, asm: "VFCVTL", typ: "Vec128"}, + {name: "VFCVTN2D", argLength: 1, reg: v11, asm: "VFCVTN", typ: "Vec128"}, + {name: "VFCVTN2_2D", argLength: 2, reg: v21, asm: "VFCVTN2", typ: "Vec128", resultInArg0: true}, + {name: "VFCVTZS2D", argLength: 1, reg: v11, asm: "VFCVTZS", typ: "Vec128"}, + {name: "VFCVTZS4S", argLength: 1, reg: v11, asm: "VFCVTZS", typ: "Vec128"}, + {name: "VFCVTZU2D", argLength: 1, reg: v11, asm: "VFCVTZU", typ: "Vec128"}, + {name: "VFCVTZU4S", argLength: 1, reg: v11, asm: "VFCVTZU", typ: "Vec128"}, + {name: "VFDIV2D", argLength: 2, reg: v21, asm: "VFDIV", typ: "Vec128"}, + {name: "VFDIV4S", argLength: 2, reg: v21, asm: "VFDIV", typ: "Vec128"}, + {name: "VFMAX2D", argLength: 2, reg: v21, asm: "VFMAX", commutative: true, typ: "Vec128"}, + {name: "VFMAX4S", argLength: 2, reg: v21, asm: "VFMAX", commutative: true, typ: "Vec128"}, + {name: "VFMAXV4S", argLength: 1, reg: v11, asm: "VFMAXV", typ: "Vec128"}, + {name: "VFMIN2D", argLength: 2, reg: v21, asm: "VFMIN", commutative: true, typ: "Vec128"}, + {name: "VFMIN4S", argLength: 2, reg: v21, asm: "VFMIN", commutative: true, typ: "Vec128"}, + {name: "VFMINV4S", argLength: 1, reg: v11, asm: "VFMINV", typ: "Vec128"}, + {name: "VFMLA2D", argLength: 3, reg: v31, asm: "VFMLA", typ: "Vec128", resultInArg0: true}, + {name: "VFMLA4S", argLength: 3, reg: v31, asm: "VFMLA", typ: "Vec128", resultInArg0: true}, + {name: "VFMUL2D", argLength: 2, reg: v21, asm: "VFMUL", commutative: true, typ: "Vec128"}, + {name: "VFMUL4S", argLength: 2, reg: v21, asm: "VFMUL", commutative: true, typ: "Vec128"}, + {name: "VFNEG2D", argLength: 1, reg: v11, asm: "VFNEG", typ: "Vec128"}, + {name: "VFNEG4S", argLength: 1, reg: v11, asm: "VFNEG", typ: "Vec128"}, + {name: "VFRINTM2D", argLength: 1, reg: v11, asm: "VFRINTM", typ: "Vec128"}, + {name: "VFRINTM4S", argLength: 1, reg: v11, asm: "VFRINTM", typ: "Vec128"}, + {name: "VFRINTN2D", argLength: 1, reg: v11, asm: "VFRINTN", typ: "Vec128"}, + {name: "VFRINTN4S", argLength: 1, reg: v11, asm: "VFRINTN", typ: "Vec128"}, + {name: "VFRINTP2D", argLength: 1, reg: v11, asm: "VFRINTP", typ: "Vec128"}, + {name: "VFRINTP4S", argLength: 1, reg: v11, asm: "VFRINTP", typ: "Vec128"}, + {name: "VFRINTZ2D", argLength: 1, reg: v11, asm: "VFRINTZ", typ: "Vec128"}, + {name: "VFRINTZ4S", argLength: 1, reg: v11, asm: "VFRINTZ", typ: "Vec128"}, + {name: "VFSQRT2D", argLength: 1, reg: v11, asm: "VFSQRT", typ: "Vec128"}, + {name: "VFSQRT4S", argLength: 1, reg: v11, asm: "VFSQRT", typ: "Vec128"}, + {name: "VFSUB2D", argLength: 2, reg: v21, asm: "VFSUB", typ: "Vec128"}, + {name: "VFSUB4S", argLength: 2, reg: v21, asm: "VFSUB", typ: "Vec128"}, + {name: "VMLA4S", argLength: 3, reg: v31, asm: "VMLA", typ: "Vec128", resultInArg0: true}, + {name: "VMLA8H", argLength: 3, reg: v31, asm: "VMLA", typ: "Vec128", resultInArg0: true}, + {name: "VMLA16B", argLength: 3, reg: v31, asm: "VMLA", typ: "Vec128", resultInArg0: true}, + {name: "VMUL4S", argLength: 2, reg: v21, asm: "VMUL", commutative: true, typ: "Vec128"}, + {name: "VMUL8H", argLength: 2, reg: v21, asm: "VMUL", commutative: true, typ: "Vec128"}, + {name: "VMUL16B", argLength: 2, reg: v21, asm: "VMUL", commutative: true, typ: "Vec128"}, + {name: "VNEG2D", argLength: 1, reg: v11, asm: "VNEG", typ: "Vec128"}, + {name: "VNEG4S", argLength: 1, reg: v11, asm: "VNEG", typ: "Vec128"}, + {name: "VNEG8H", argLength: 1, reg: v11, asm: "VNEG", typ: "Vec128"}, + {name: "VNEG16B", argLength: 1, reg: v11, asm: "VNEG", typ: "Vec128"}, + {name: "VNOT16B", argLength: 1, reg: v11, asm: "VNOT", typ: "Vec128"}, + {name: "VORN16B", argLength: 2, reg: v21, asm: "VORN", typ: "Vec128"}, + {name: "VORR16B", argLength: 2, reg: v21, asm: "VORR", commutative: true, typ: "Vec128"}, + {name: "VPMULL2D", argLength: 2, reg: v21, asm: "VPMULL", commutative: true, typ: "Vec128"}, + {name: "VPMULL2_2D", argLength: 2, reg: v21, asm: "VPMULL2", commutative: true, typ: "Vec128"}, + {name: "VSCVTF2D", argLength: 1, reg: v11, asm: "VSCVTF", typ: "Vec128"}, + {name: "VSCVTF4S", argLength: 1, reg: v11, asm: "VSCVTF", typ: "Vec128"}, + {name: "VSMAX4S", argLength: 2, reg: v21, asm: "VSMAX", commutative: true, typ: "Vec128"}, + {name: "VSMAX8H", argLength: 2, reg: v21, asm: "VSMAX", commutative: true, typ: "Vec128"}, + {name: "VSMAX16B", argLength: 2, reg: v21, asm: "VSMAX", commutative: true, typ: "Vec128"}, + {name: "VSMAXV4S", argLength: 1, reg: v11, asm: "VSMAXV", typ: "Vec128"}, + {name: "VSMAXV8H", argLength: 1, reg: v11, asm: "VSMAXV", typ: "Vec128"}, + {name: "VSMAXV16B", argLength: 1, reg: v11, asm: "VSMAXV", typ: "Vec128"}, + {name: "VSMIN4S", argLength: 2, reg: v21, asm: "VSMIN", commutative: true, typ: "Vec128"}, + {name: "VSMIN8H", argLength: 2, reg: v21, asm: "VSMIN", commutative: true, typ: "Vec128"}, + {name: "VSMIN16B", argLength: 2, reg: v21, asm: "VSMIN", commutative: true, typ: "Vec128"}, + {name: "VSMINV4S", argLength: 1, reg: v11, asm: "VSMINV", typ: "Vec128"}, + {name: "VSMINV8H", argLength: 1, reg: v11, asm: "VSMINV", typ: "Vec128"}, + {name: "VSMINV16B", argLength: 1, reg: v11, asm: "VSMINV", typ: "Vec128"}, + {name: "VSMULL2_4S", argLength: 2, reg: v21, asm: "VSMULL2", commutative: true, typ: "Vec128"}, + {name: "VSMULL2_8H", argLength: 2, reg: v21, asm: "VSMULL2", commutative: true, typ: "Vec128"}, + {name: "VSMULL2_16B", argLength: 2, reg: v21, asm: "VSMULL2", commutative: true, typ: "Vec128"}, + {name: "VSMULL4S", argLength: 2, reg: v21, asm: "VSMULL", commutative: true, typ: "Vec128"}, + {name: "VSMULL8H", argLength: 2, reg: v21, asm: "VSMULL", commutative: true, typ: "Vec128"}, + {name: "VSMULL16B", argLength: 2, reg: v21, asm: "VSMULL", commutative: true, typ: "Vec128"}, + {name: "VSQADD2D", argLength: 2, reg: v21, asm: "VSQADD", commutative: true, typ: "Vec128"}, + {name: "VSQADD4S", argLength: 2, reg: v21, asm: "VSQADD", commutative: true, typ: "Vec128"}, + {name: "VSQADD8H", argLength: 2, reg: v21, asm: "VSQADD", commutative: true, typ: "Vec128"}, + {name: "VSQADD16B", argLength: 2, reg: v21, asm: "VSQADD", commutative: true, typ: "Vec128"}, + {name: "VSQSHL2D", argLength: 2, reg: v21, asm: "VSQSHL", typ: "Vec128"}, + {name: "VSQSHL4S", argLength: 2, reg: v21, asm: "VSQSHL", typ: "Vec128"}, + {name: "VSQSHL8H", argLength: 2, reg: v21, asm: "VSQSHL", typ: "Vec128"}, + {name: "VSQSHL16B", argLength: 2, reg: v21, asm: "VSQSHL", typ: "Vec128"}, + {name: "VSQSUB2D", argLength: 2, reg: v21, asm: "VSQSUB", typ: "Vec128"}, + {name: "VSQSUB4S", argLength: 2, reg: v21, asm: "VSQSUB", typ: "Vec128"}, + {name: "VSQSUB8H", argLength: 2, reg: v21, asm: "VSQSUB", typ: "Vec128"}, + {name: "VSQSUB16B", argLength: 2, reg: v21, asm: "VSQSUB", typ: "Vec128"}, + {name: "VSQXTN2D", argLength: 1, reg: v11, asm: "VSQXTN", typ: "Vec128"}, + {name: "VSQXTN2_2D", argLength: 2, reg: v21, asm: "VSQXTN2", typ: "Vec128", resultInArg0: true}, + {name: "VSQXTN2_4S", argLength: 2, reg: v21, asm: "VSQXTN2", typ: "Vec128", resultInArg0: true}, + {name: "VSQXTN2_8H", argLength: 2, reg: v21, asm: "VSQXTN2", typ: "Vec128", resultInArg0: true}, + {name: "VSQXTN4S", argLength: 1, reg: v11, asm: "VSQXTN", typ: "Vec128"}, + {name: "VSQXTN8H", argLength: 1, reg: v11, asm: "VSQXTN", typ: "Vec128"}, + {name: "VSQXTUN2D", argLength: 1, reg: v11, asm: "VSQXTUN", typ: "Vec128"}, + {name: "VSQXTUN2_2D", argLength: 2, reg: v21, asm: "VSQXTUN2", typ: "Vec128", resultInArg0: true}, + {name: "VSQXTUN2_4S", argLength: 2, reg: v21, asm: "VSQXTUN2", typ: "Vec128", resultInArg0: true}, + {name: "VSQXTUN2_8H", argLength: 2, reg: v21, asm: "VSQXTUN2", typ: "Vec128", resultInArg0: true}, + {name: "VSQXTUN4S", argLength: 1, reg: v11, asm: "VSQXTUN", typ: "Vec128"}, + {name: "VSQXTUN8H", argLength: 1, reg: v11, asm: "VSQXTUN", typ: "Vec128"}, + {name: "VSRHADD4S", argLength: 2, reg: v21, asm: "VSRHADD", commutative: true, typ: "Vec128"}, + {name: "VSRHADD8H", argLength: 2, reg: v21, asm: "VSRHADD", commutative: true, typ: "Vec128"}, + {name: "VSRHADD16B", argLength: 2, reg: v21, asm: "VSRHADD", commutative: true, typ: "Vec128"}, + {name: "VSSHL2D", argLength: 2, reg: v21, asm: "VSSHL", typ: "Vec128"}, + {name: "VSSHL4S", argLength: 2, reg: v21, asm: "VSSHL", typ: "Vec128"}, + {name: "VSSHL8H", argLength: 2, reg: v21, asm: "VSSHL", typ: "Vec128"}, + {name: "VSSHL16B", argLength: 2, reg: v21, asm: "VSSHL", typ: "Vec128"}, + {name: "VSUB2D", argLength: 2, reg: v21, asm: "VSUB", typ: "Vec128"}, + {name: "VSUB4S", argLength: 2, reg: v21, asm: "VSUB", typ: "Vec128"}, + {name: "VSUB8H", argLength: 2, reg: v21, asm: "VSUB", typ: "Vec128"}, + {name: "VSUB16B", argLength: 2, reg: v21, asm: "VSUB", typ: "Vec128"}, + {name: "VSXTL2_4S", argLength: 1, reg: v11, asm: "VSXTL2", typ: "Vec128"}, + {name: "VSXTL2_8H", argLength: 1, reg: v11, asm: "VSXTL2", typ: "Vec128"}, + {name: "VSXTL2_16B", argLength: 1, reg: v11, asm: "VSXTL2", typ: "Vec128"}, + {name: "VSXTL4S", argLength: 1, reg: v11, asm: "VSXTL", typ: "Vec128"}, + {name: "VSXTL8H", argLength: 1, reg: v11, asm: "VSXTL", typ: "Vec128"}, + {name: "VSXTL16B", argLength: 1, reg: v11, asm: "VSXTL", typ: "Vec128"}, + {name: "VTBL16B", argLength: 2, reg: v21, asm: "VTBL", typ: "Vec128"}, + {name: "VTBX16B", argLength: 3, reg: v31, asm: "VTBX", typ: "Vec128", resultInArg0: true}, + {name: "VTRN12D", argLength: 2, reg: v21, asm: "VTRN1", typ: "Vec128"}, + {name: "VTRN14S", argLength: 2, reg: v21, asm: "VTRN1", typ: "Vec128"}, + {name: "VTRN18H", argLength: 2, reg: v21, asm: "VTRN1", typ: "Vec128"}, + {name: "VTRN22D", argLength: 2, reg: v21, asm: "VTRN2", typ: "Vec128"}, + {name: "VTRN24S", argLength: 2, reg: v21, asm: "VTRN2", typ: "Vec128"}, + {name: "VTRN28H", argLength: 2, reg: v21, asm: "VTRN2", typ: "Vec128"}, + {name: "VTRN116B", argLength: 2, reg: v21, asm: "VTRN1", typ: "Vec128"}, + {name: "VTRN216B", argLength: 2, reg: v21, asm: "VTRN2", typ: "Vec128"}, + {name: "VUCVTF2D", argLength: 1, reg: v11, asm: "VUCVTF", typ: "Vec128"}, + {name: "VUCVTF4S", argLength: 1, reg: v11, asm: "VUCVTF", typ: "Vec128"}, + {name: "VUMAX4S", argLength: 2, reg: v21, asm: "VUMAX", commutative: true, typ: "Vec128"}, + {name: "VUMAX8H", argLength: 2, reg: v21, asm: "VUMAX", commutative: true, typ: "Vec128"}, + {name: "VUMAX16B", argLength: 2, reg: v21, asm: "VUMAX", commutative: true, typ: "Vec128"}, + {name: "VUMAXV4S", argLength: 1, reg: v11, asm: "VUMAXV", typ: "Vec128"}, + {name: "VUMAXV8H", argLength: 1, reg: v11, asm: "VUMAXV", typ: "Vec128"}, + {name: "VUMAXV16B", argLength: 1, reg: v11, asm: "VUMAXV", typ: "Vec128"}, + {name: "VUMIN4S", argLength: 2, reg: v21, asm: "VUMIN", commutative: true, typ: "Vec128"}, + {name: "VUMIN8H", argLength: 2, reg: v21, asm: "VUMIN", commutative: true, typ: "Vec128"}, + {name: "VUMIN16B", argLength: 2, reg: v21, asm: "VUMIN", commutative: true, typ: "Vec128"}, + {name: "VUMINV4S", argLength: 1, reg: v11, asm: "VUMINV", typ: "Vec128"}, + {name: "VUMINV8H", argLength: 1, reg: v11, asm: "VUMINV", typ: "Vec128"}, + {name: "VUMINV16B", argLength: 1, reg: v11, asm: "VUMINV", typ: "Vec128"}, + {name: "VUMULL2_4S", argLength: 2, reg: v21, asm: "VUMULL2", commutative: true, typ: "Vec128"}, + {name: "VUMULL2_8H", argLength: 2, reg: v21, asm: "VUMULL2", commutative: true, typ: "Vec128"}, + {name: "VUMULL2_16B", argLength: 2, reg: v21, asm: "VUMULL2", commutative: true, typ: "Vec128"}, + {name: "VUMULL4S", argLength: 2, reg: v21, asm: "VUMULL", commutative: true, typ: "Vec128"}, + {name: "VUMULL8H", argLength: 2, reg: v21, asm: "VUMULL", commutative: true, typ: "Vec128"}, + {name: "VUMULL16B", argLength: 2, reg: v21, asm: "VUMULL", commutative: true, typ: "Vec128"}, + {name: "VUQADD2D", argLength: 2, reg: v21, asm: "VUQADD", commutative: true, typ: "Vec128"}, + {name: "VUQADD4S", argLength: 2, reg: v21, asm: "VUQADD", commutative: true, typ: "Vec128"}, + {name: "VUQADD8H", argLength: 2, reg: v21, asm: "VUQADD", commutative: true, typ: "Vec128"}, + {name: "VUQADD16B", argLength: 2, reg: v21, asm: "VUQADD", commutative: true, typ: "Vec128"}, + {name: "VUQSHL2D", argLength: 2, reg: v21, asm: "VUQSHL", typ: "Vec128"}, + {name: "VUQSHL4S", argLength: 2, reg: v21, asm: "VUQSHL", typ: "Vec128"}, + {name: "VUQSHL8H", argLength: 2, reg: v21, asm: "VUQSHL", typ: "Vec128"}, + {name: "VUQSHL16B", argLength: 2, reg: v21, asm: "VUQSHL", typ: "Vec128"}, + {name: "VUQSUB2D", argLength: 2, reg: v21, asm: "VUQSUB", typ: "Vec128"}, + {name: "VUQSUB4S", argLength: 2, reg: v21, asm: "VUQSUB", typ: "Vec128"}, + {name: "VUQSUB8H", argLength: 2, reg: v21, asm: "VUQSUB", typ: "Vec128"}, + {name: "VUQSUB16B", argLength: 2, reg: v21, asm: "VUQSUB", typ: "Vec128"}, + {name: "VUQXTN2D", argLength: 1, reg: v11, asm: "VUQXTN", typ: "Vec128"}, + {name: "VUQXTN2_2D", argLength: 2, reg: v21, asm: "VUQXTN2", typ: "Vec128", resultInArg0: true}, + {name: "VUQXTN2_4S", argLength: 2, reg: v21, asm: "VUQXTN2", typ: "Vec128", resultInArg0: true}, + {name: "VUQXTN2_8H", argLength: 2, reg: v21, asm: "VUQXTN2", typ: "Vec128", resultInArg0: true}, + {name: "VUQXTN4S", argLength: 1, reg: v11, asm: "VUQXTN", typ: "Vec128"}, + {name: "VUQXTN8H", argLength: 1, reg: v11, asm: "VUQXTN", typ: "Vec128"}, + {name: "VURHADD4S", argLength: 2, reg: v21, asm: "VURHADD", commutative: true, typ: "Vec128"}, + {name: "VURHADD8H", argLength: 2, reg: v21, asm: "VURHADD", commutative: true, typ: "Vec128"}, + {name: "VURHADD16B", argLength: 2, reg: v21, asm: "VURHADD", commutative: true, typ: "Vec128"}, + {name: "VUSHL2D", argLength: 2, reg: v21, asm: "VUSHL", typ: "Vec128"}, + {name: "VUSHL4S", argLength: 2, reg: v21, asm: "VUSHL", typ: "Vec128"}, + {name: "VUSHL8H", argLength: 2, reg: v21, asm: "VUSHL", typ: "Vec128"}, + {name: "VUSHL16B", argLength: 2, reg: v21, asm: "VUSHL", typ: "Vec128"}, + {name: "VUXTL2_4S", argLength: 1, reg: v11, asm: "VUXTL2", typ: "Vec128"}, + {name: "VUXTL2_8H", argLength: 1, reg: v11, asm: "VUXTL2", typ: "Vec128"}, + {name: "VUXTL2_16B", argLength: 1, reg: v11, asm: "VUXTL2", typ: "Vec128"}, + {name: "VUXTL4S", argLength: 1, reg: v11, asm: "VUXTL", typ: "Vec128"}, + {name: "VUXTL8H", argLength: 1, reg: v11, asm: "VUXTL", typ: "Vec128"}, + {name: "VUXTL16B", argLength: 1, reg: v11, asm: "VUXTL", typ: "Vec128"}, + {name: "VUZP12D", argLength: 2, reg: v21, asm: "VUZP1", typ: "Vec128"}, + {name: "VUZP14S", argLength: 2, reg: v21, asm: "VUZP1", typ: "Vec128"}, + {name: "VUZP18H", argLength: 2, reg: v21, asm: "VUZP1", typ: "Vec128"}, + {name: "VUZP22D", argLength: 2, reg: v21, asm: "VUZP2", typ: "Vec128"}, + {name: "VUZP24S", argLength: 2, reg: v21, asm: "VUZP2", typ: "Vec128"}, + {name: "VUZP28H", argLength: 2, reg: v21, asm: "VUZP2", typ: "Vec128"}, + {name: "VUZP116B", argLength: 2, reg: v21, asm: "VUZP1", typ: "Vec128"}, + {name: "VUZP216B", argLength: 2, reg: v21, asm: "VUZP2", typ: "Vec128"}, + {name: "VXTN2D", argLength: 1, reg: v11, asm: "VXTN", typ: "Vec128"}, + {name: "VXTN2_2D", argLength: 2, reg: v21, asm: "VXTN2", typ: "Vec128", resultInArg0: true}, + {name: "VXTN2_4S", argLength: 2, reg: v21, asm: "VXTN2", typ: "Vec128", resultInArg0: true}, + {name: "VXTN2_8H", argLength: 2, reg: v21, asm: "VXTN2", typ: "Vec128", resultInArg0: true}, + {name: "VXTN4S", argLength: 1, reg: v11, asm: "VXTN", typ: "Vec128"}, + {name: "VXTN8H", argLength: 1, reg: v11, asm: "VXTN", typ: "Vec128"}, + {name: "VZIP12D", argLength: 2, reg: v21, asm: "VZIP1", typ: "Vec128"}, + {name: "VZIP14S", argLength: 2, reg: v21, asm: "VZIP1", typ: "Vec128"}, + {name: "VZIP18H", argLength: 2, reg: v21, asm: "VZIP1", typ: "Vec128"}, + {name: "VZIP22D", argLength: 2, reg: v21, asm: "VZIP2", typ: "Vec128"}, + {name: "VZIP24S", argLength: 2, reg: v21, asm: "VZIP2", typ: "Vec128"}, + {name: "VZIP28H", argLength: 2, reg: v21, asm: "VZIP2", typ: "Vec128"}, + {name: "VZIP116B", argLength: 2, reg: v21, asm: "VZIP1", typ: "Vec128"}, + {name: "VZIP216B", argLength: 2, reg: v21, asm: "VZIP2", typ: "Vec128"}, + {name: "VDUPBbcast", argLength: 1, reg: v11, asm: "VDUP", aux: "UInt8", typ: "Vec128"}, + {name: "VDUPDbcast", argLength: 1, reg: v11, asm: "VDUP", aux: "UInt8", typ: "Vec128"}, + {name: "VDUPDextr", argLength: 1, reg: v11, asm: "VDUP", aux: "UInt8", typ: "Vec128"}, + {name: "VDUPHbcast", argLength: 1, reg: v11, asm: "VDUP", aux: "UInt8", typ: "Vec128"}, + {name: "VDUPSbcast", argLength: 1, reg: v11, asm: "VDUP", aux: "UInt8", typ: "Vec128"}, + {name: "VDUPSextr", argLength: 1, reg: v11, asm: "VDUP", aux: "UInt8", typ: "Vec128"}, + {name: "VEXT16B", argLength: 2, reg: v21, asm: "VEXT", aux: "UInt8", typ: "Vec128"}, + {name: "VMOVBextr", argLength: 1, reg: vgp, asm: "VMOV", aux: "UInt8", typ: "int8"}, + {name: "VMOVBins", argLength: 2, reg: vgpv, asm: "VMOV", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VMOVDextr", argLength: 1, reg: vgp, asm: "VMOV", aux: "UInt8", typ: "int64"}, + {name: "VMOVDins", argLength: 2, reg: vgpv, asm: "VMOV", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VMOVDins0", argLength: 2, reg: vfpv, asm: "VMOV", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VMOVHextr", argLength: 1, reg: vgp, asm: "VMOV", aux: "UInt8", typ: "int16"}, + {name: "VMOVHins", argLength: 2, reg: vgpv, asm: "VMOV", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VMOVSextr", argLength: 1, reg: vgp, asm: "VMOV", aux: "UInt8", typ: "int32"}, + {name: "VMOVSins", argLength: 2, reg: vgpv, asm: "VMOV", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VMOVSins0", argLength: 2, reg: vfpv, asm: "VMOV", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VSHL2D", argLength: 1, reg: v11, asm: "VSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VSHL4S", argLength: 1, reg: v11, asm: "VSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VSHL8H", argLength: 1, reg: v11, asm: "VSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VSHL16B", argLength: 1, reg: v11, asm: "VSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VSHRN2D", argLength: 1, reg: v11, asm: "VSHRN", aux: "UInt8", typ: "Vec128"}, + {name: "VSHRN2_2D", argLength: 2, reg: v21, asm: "VSHRN2", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VSHRN2_4S", argLength: 2, reg: v21, asm: "VSHRN2", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VSHRN2_8H", argLength: 2, reg: v21, asm: "VSHRN2", aux: "UInt8", typ: "Vec128", resultInArg0: true}, + {name: "VSHRN4S", argLength: 1, reg: v11, asm: "VSHRN", aux: "UInt8", typ: "Vec128"}, + {name: "VSHRN8H", argLength: 1, reg: v11, asm: "VSHRN", aux: "UInt8", typ: "Vec128"}, + {name: "VSQSHL2Dconst", argLength: 1, reg: v11, asm: "VSQSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VSQSHL4Sconst", argLength: 1, reg: v11, asm: "VSQSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VSQSHL8Hconst", argLength: 1, reg: v11, asm: "VSQSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VSQSHL16Bconst", argLength: 1, reg: v11, asm: "VSQSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VSSHLL2_4S", argLength: 1, reg: v11, asm: "VSSHLL2", aux: "UInt8", typ: "Vec128"}, + {name: "VSSHLL2_8H", argLength: 1, reg: v11, asm: "VSSHLL2", aux: "UInt8", typ: "Vec128"}, + {name: "VSSHLL2_16B", argLength: 1, reg: v11, asm: "VSSHLL2", aux: "UInt8", typ: "Vec128"}, + {name: "VSSHLL4S", argLength: 1, reg: v11, asm: "VSSHLL", aux: "UInt8", typ: "Vec128"}, + {name: "VSSHLL8H", argLength: 1, reg: v11, asm: "VSSHLL", aux: "UInt8", typ: "Vec128"}, + {name: "VSSHLL16B", argLength: 1, reg: v11, asm: "VSSHLL", aux: "UInt8", typ: "Vec128"}, + {name: "VSSHR2D", argLength: 1, reg: v11, asm: "VSSHR", aux: "UInt8", typ: "Vec128"}, + {name: "VSSHR4S", argLength: 1, reg: v11, asm: "VSSHR", aux: "UInt8", typ: "Vec128"}, + {name: "VSSHR8H", argLength: 1, reg: v11, asm: "VSSHR", aux: "UInt8", typ: "Vec128"}, + {name: "VSSHR16B", argLength: 1, reg: v11, asm: "VSSHR", aux: "UInt8", typ: "Vec128"}, + {name: "VUQSHL2Dconst", argLength: 1, reg: v11, asm: "VUQSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VUQSHL4Sconst", argLength: 1, reg: v11, asm: "VUQSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VUQSHL8Hconst", argLength: 1, reg: v11, asm: "VUQSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VUQSHL16Bconst", argLength: 1, reg: v11, asm: "VUQSHL", aux: "UInt8", typ: "Vec128"}, + {name: "VUSHLL2_4S", argLength: 1, reg: v11, asm: "VUSHLL2", aux: "UInt8", typ: "Vec128"}, + {name: "VUSHLL2_8H", argLength: 1, reg: v11, asm: "VUSHLL2", aux: "UInt8", typ: "Vec128"}, + {name: "VUSHLL2_16B", argLength: 1, reg: v11, asm: "VUSHLL2", aux: "UInt8", typ: "Vec128"}, + {name: "VUSHLL4S", argLength: 1, reg: v11, asm: "VUSHLL", aux: "UInt8", typ: "Vec128"}, + {name: "VUSHLL8H", argLength: 1, reg: v11, asm: "VUSHLL", aux: "UInt8", typ: "Vec128"}, + {name: "VUSHLL16B", argLength: 1, reg: v11, asm: "VUSHLL", aux: "UInt8", typ: "Vec128"}, + {name: "VUSHR2D", argLength: 1, reg: v11, asm: "VUSHR", aux: "UInt8", typ: "Vec128"}, + {name: "VUSHR4S", argLength: 1, reg: v11, asm: "VUSHR", aux: "UInt8", typ: "Vec128"}, + {name: "VUSHR8H", argLength: 1, reg: v11, asm: "VUSHR", aux: "UInt8", typ: "Vec128"}, + {name: "VUSHR16B", argLength: 1, reg: v11, asm: "VUSHR", aux: "UInt8", typ: "Vec128"}, + } +} diff --git a/src/cmd/compile/internal/ssa/_gen/simdWasm.rules b/src/cmd/compile/internal/ssa/_gen/simdWasm.rules new file mode 100644 index 00000000000000..0afcc8429824a8 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/simdWasm.rules @@ -0,0 +1,314 @@ +// Code generated by 'wasmgen'; DO NOT EDIT. + +(AbsInt8x16 ...) => (I8x16Abs ...) +(AbsInt16x8 ...) => (I16x8Abs ...) +(AbsInt32x4 ...) => (I32x4Abs ...) +(AbsFloat32x4 ...) => (F32x4Abs ...) +(AbsInt64x2 ...) => (I64x2Abs ...) +(AbsFloat64x2 ...) => (F64x2Abs ...) +(AddInt8x16 ...) => (I8x16Add ...) +(AddInt16x8 ...) => (I16x8Add ...) +(AddInt32x4 ...) => (I32x4Add ...) +(AddFloat32x4 ...) => (F32x4Add ...) +(AddInt64x2 ...) => (I64x2Add ...) +(AddFloat64x2 ...) => (F64x2Add ...) +(AddSaturatedInt8x16 ...) => (I8x16AddSatS ...) +(AddSaturatedUint8x16 ...) => (I8x16AddSatU ...) +(AddSaturatedInt16x8 ...) => (I16x8AddSatS ...) +(AddSaturatedUint16x8 ...) => (I16x8AddSatU ...) +(AndInt8x16 ...) => (V128And ...) +(AndUint8x16 ...) => (V128And ...) +(AndInt16x8 ...) => (V128And ...) +(AndUint16x8 ...) => (V128And ...) +(AndInt32x4 ...) => (V128And ...) +(AndUint32x4 ...) => (V128And ...) +(AndInt64x2 ...) => (V128And ...) +(AndUint64x2 ...) => (V128And ...) +(AndNotInt8x16 ...) => (V128Andnot ...) +(AndNotUint8x16 ...) => (V128Andnot ...) +(AndNotInt16x8 ...) => (V128Andnot ...) +(AndNotUint16x8 ...) => (V128Andnot ...) +(AndNotInt32x4 ...) => (V128Andnot ...) +(AndNotUint32x4 ...) => (V128Andnot ...) +(AndNotInt64x2 ...) => (V128Andnot ...) +(AndNotUint64x2 ...) => (V128Andnot ...) +(AverageUint8x16 ...) => (I8x16AvgrU ...) +(AverageUint16x8 ...) => (I16x8AvgrU ...) +(BitSelectInt8x16 ...) => (V128Bitselect ...) +(BitSelectUint8x16 ...) => (V128Bitselect ...) +(BitSelectInt16x8 ...) => (V128Bitselect ...) +(BitSelectUint16x8 ...) => (V128Bitselect ...) +(BitSelectInt32x4 ...) => (V128Bitselect ...) +(BitSelectUint32x4 ...) => (V128Bitselect ...) +(BitSelectInt64x2 ...) => (V128Bitselect ...) +(BitSelectUint64x2 ...) => (V128Bitselect ...) +(BroadcastInt8x16 ...) => (I8x16Splat ...) +(BroadcastInt16x8 ...) => (I16x8Splat ...) +(BroadcastInt32x4 ...) => (I32x4Splat ...) +(BroadcastFloat32x4 ...) => (F32x4Splat ...) +(BroadcastInt64x2 ...) => (I64x2Splat ...) +(BroadcastFloat64x2 ...) => (F64x2Splat ...) +(CeilFloat32x4 ...) => (F32x4Ceil ...) +(CeilFloat64x2 ...) => (F64x2Ceil ...) +(ConvertLo2ToFloat64Int32x4 ...) => (F64x2ConvertLowI32x4S ...) +(ConvertLo2ToFloat64Uint32x4 ...) => (F64x2ConvertLowI32x4U ...) +(ConvertToFloat32Int32x4 ...) => (F32x4ConvertI32x4S ...) +(ConvertToFloat32Uint32x4 ...) => (F32x4ConvertI32x4U ...) +(ConvertToInt32Float32x4 ...) => (I32x4TruncSatF32x4S ...) +(ConvertToUint32Float32x4 ...) => (I32x4TruncSatF32x4U ...) +(DivFloat32x4 ...) => (F32x4Div ...) +(DivFloat64x2 ...) => (F64x2Div ...) +(EqualInt8x16 ...) => (I8x16Eq ...) +(EqualUint8x16 ...) => (I8x16Eq ...) +(EqualInt16x8 ...) => (I16x8Eq ...) +(EqualUint16x8 ...) => (I16x8Eq ...) +(EqualInt32x4 ...) => (I32x4Eq ...) +(EqualUint32x4 ...) => (I32x4Eq ...) +(EqualFloat32x4 ...) => (F32x4Eq ...) +(EqualInt64x2 ...) => (I64x2Eq ...) +(EqualUint64x2 ...) => (I64x2Eq ...) +(EqualFloat64x2 ...) => (F64x2Eq ...) +(ExtendHi2ToInt64Int32x4 ...) => (I64x2ExtendHighI32x4S ...) +(ExtendHi2ToUint64Uint32x4 ...) => (I64x2ExtendHighI32x4U ...) +(ExtendHi4ToInt32Int16x8 ...) => (I32x4ExtendHighI16x8S ...) +(ExtendHi4ToUint32Uint16x8 ...) => (I32x4ExtendHighI16x8U ...) +(ExtendHi8ToInt16Int8x16 ...) => (I16x8ExtendHighI8x16S ...) +(ExtendHi8ToUint16Uint8x16 ...) => (I16x8ExtendHighI8x16U ...) +(ExtendLo2ToInt64Int32x4 ...) => (I64x2ExtendLowI32x4S ...) +(ExtendLo2ToUint64Uint32x4 ...) => (I64x2ExtendLowI32x4U ...) +(ExtendLo4ToInt32Int16x8 ...) => (I32x4ExtendLowI16x8S ...) +(ExtendLo4ToUint32Uint16x8 ...) => (I32x4ExtendLowI16x8U ...) +(ExtendLo8ToInt16Int8x16 ...) => (I16x8ExtendLowI8x16S ...) +(ExtendLo8ToUint16Uint8x16 ...) => (I16x8ExtendLowI8x16U ...) +(FloorFloat32x4 ...) => (F32x4Floor ...) +(FloorFloat64x2 ...) => (F64x2Floor ...) +(GetElemInt8x16 ...) => (I8x16ExtractLaneS ...) +(GetElemUint8x16 ...) => (I8x16ExtractLaneU ...) +(GetElemInt16x8 ...) => (I16x8ExtractLaneS ...) +(GetElemUint16x8 ...) => (I16x8ExtractLaneU ...) +(GetElemInt32x4 ...) => (I32x4ExtractLane ...) +(GetElemUint32x4 ...) => (I32x4ExtractLane ...) +(GetElemFloat32x4 ...) => (F32x4ExtractLane ...) +(GetElemInt64x2 ...) => (I64x2ExtractLane ...) +(GetElemUint64x2 ...) => (I64x2ExtractLane ...) +(GetElemFloat64x2 ...) => (F64x2ExtractLane ...) +(GreaterInt8x16 ...) => (I8x16GtS ...) +(GreaterUint8x16 ...) => (I8x16GtU ...) +(GreaterInt16x8 ...) => (I16x8GtS ...) +(GreaterUint16x8 ...) => (I16x8GtU ...) +(GreaterInt32x4 ...) => (I32x4GtS ...) +(GreaterUint32x4 ...) => (I32x4GtU ...) +(GreaterFloat32x4 ...) => (F32x4Gt ...) +(GreaterInt64x2 ...) => (I64x2GtS ...) +(GreaterFloat64x2 ...) => (F64x2Gt ...) +(GreaterEqualInt8x16 ...) => (I8x16GeS ...) +(GreaterEqualUint8x16 ...) => (I8x16GeU ...) +(GreaterEqualInt16x8 ...) => (I16x8GeS ...) +(GreaterEqualUint16x8 ...) => (I16x8GeU ...) +(GreaterEqualInt32x4 ...) => (I32x4GeS ...) +(GreaterEqualUint32x4 ...) => (I32x4GeU ...) +(GreaterEqualFloat32x4 ...) => (F32x4Ge ...) +(GreaterEqualInt64x2 ...) => (I64x2GeS ...) +(GreaterEqualFloat64x2 ...) => (F64x2Ge ...) +(LessInt8x16 ...) => (I8x16LtS ...) +(LessUint8x16 ...) => (I8x16LtU ...) +(LessInt16x8 ...) => (I16x8LtS ...) +(LessUint16x8 ...) => (I16x8LtU ...) +(LessInt32x4 ...) => (I32x4LtS ...) +(LessUint32x4 ...) => (I32x4LtU ...) +(LessFloat32x4 ...) => (F32x4Lt ...) +(LessInt64x2 ...) => (I64x2LtS ...) +(LessFloat64x2 ...) => (F64x2Lt ...) +(LessEqualInt8x16 ...) => (I8x16LeS ...) +(LessEqualUint8x16 ...) => (I8x16LeU ...) +(LessEqualInt16x8 ...) => (I16x8LeS ...) +(LessEqualUint16x8 ...) => (I16x8LeU ...) +(LessEqualInt32x4 ...) => (I32x4LeS ...) +(LessEqualUint32x4 ...) => (I32x4LeU ...) +(LessEqualFloat32x4 ...) => (F32x4Le ...) +(LessEqualInt64x2 ...) => (I64x2LeS ...) +(LessEqualFloat64x2 ...) => (F64x2Le ...) +(LookupOrZeroInt8x16 ...) => (I8x16Swizzle ...) +(MaxInt8x16 ...) => (I8x16MaxS ...) +(MaxUint8x16 ...) => (I8x16MaxU ...) +(MaxInt16x8 ...) => (I16x8MaxS ...) +(MaxUint16x8 ...) => (I16x8MaxU ...) +(MaxInt32x4 ...) => (I32x4MaxS ...) +(MaxUint32x4 ...) => (I32x4MaxU ...) +(MaxFloat32x4 ...) => (F32x4Max ...) +(MaxFloat64x2 ...) => (F64x2Max ...) +(MinInt8x16 ...) => (I8x16MinS ...) +(MinUint8x16 ...) => (I8x16MinU ...) +(MinInt16x8 ...) => (I16x8MinS ...) +(MinUint16x8 ...) => (I16x8MinU ...) +(MinInt32x4 ...) => (I32x4MinS ...) +(MinUint32x4 ...) => (I32x4MinU ...) +(MinFloat32x4 ...) => (F32x4Min ...) +(MinFloat64x2 ...) => (F64x2Min ...) +(MulInt16x8 ...) => (I16x8Mul ...) +(MulUint16x8 ...) => (I16x8Mul ...) +(MulInt32x4 ...) => (I32x4Mul ...) +(MulUint32x4 ...) => (I32x4Mul ...) +(MulFloat32x4 ...) => (F32x4Mul ...) +(MulInt64x2 ...) => (I64x2Mul ...) +(MulUint64x2 ...) => (I64x2Mul ...) +(MulFloat64x2 ...) => (F64x2Mul ...) +(MulWidenHiInt8x16 ...) => (I16x8ExtmulHighI8x16S ...) +(MulWidenHiUint8x16 ...) => (I16x8ExtmulHighI8x16U ...) +(MulWidenHiInt16x8 ...) => (I32x4ExtmulHighI16x8S ...) +(MulWidenHiUint16x8 ...) => (I32x4ExtmulHighI16x8U ...) +(MulWidenHiInt32x4 ...) => (I64x2ExtmulHighI32x4S ...) +(MulWidenHiUint32x4 ...) => (I64x2ExtmulHighI32x4U ...) +(MulWidenLoInt8x16 ...) => (I16x8ExtmulLowI8x16S ...) +(MulWidenLoUint8x16 ...) => (I16x8ExtmulLowI8x16U ...) +(MulWidenLoInt16x8 ...) => (I32x4ExtmulLowI16x8S ...) +(MulWidenLoUint16x8 ...) => (I32x4ExtmulLowI16x8U ...) +(MulWidenLoInt32x4 ...) => (I64x2ExtmulLowI32x4S ...) +(MulWidenLoUint32x4 ...) => (I64x2ExtmulLowI32x4U ...) +(NegInt8x16 ...) => (I8x16Neg ...) +(NegInt16x8 ...) => (I16x8Neg ...) +(NegInt32x4 ...) => (I32x4Neg ...) +(NegFloat32x4 ...) => (F32x4Neg ...) +(NegInt64x2 ...) => (I64x2Neg ...) +(NegFloat64x2 ...) => (F64x2Neg ...) +(NotInt8x16 ...) => (V128Not ...) +(NotUint8x16 ...) => (V128Not ...) +(NotInt16x8 ...) => (V128Not ...) +(NotUint16x8 ...) => (V128Not ...) +(NotInt32x4 ...) => (V128Not ...) +(NotUint32x4 ...) => (V128Not ...) +(NotInt64x2 ...) => (V128Not ...) +(NotUint64x2 ...) => (V128Not ...) +(NotEqualInt8x16 ...) => (I8x16Ne ...) +(NotEqualUint8x16 ...) => (I8x16Ne ...) +(NotEqualInt16x8 ...) => (I16x8Ne ...) +(NotEqualUint16x8 ...) => (I16x8Ne ...) +(NotEqualInt32x4 ...) => (I32x4Ne ...) +(NotEqualUint32x4 ...) => (I32x4Ne ...) +(NotEqualFloat32x4 ...) => (F32x4Ne ...) +(NotEqualInt64x2 ...) => (I64x2Ne ...) +(NotEqualUint64x2 ...) => (I64x2Ne ...) +(NotEqualFloat64x2 ...) => (F64x2Ne ...) +(OnesCountInt8x16 ...) => (I8x16Popcnt ...) +(OrInt8x16 ...) => (V128Or ...) +(OrUint8x16 ...) => (V128Or ...) +(OrInt16x8 ...) => (V128Or ...) +(OrUint16x8 ...) => (V128Or ...) +(OrInt32x4 ...) => (V128Or ...) +(OrUint32x4 ...) => (V128Or ...) +(OrInt64x2 ...) => (V128Or ...) +(OrUint64x2 ...) => (V128Or ...) +(RotateAllLeftVarInt8x16 x y) => (V128Or (I8x16Shl x y) (I8x16ShrU x (I64Sub (I64Const [8]) y))) +(RotateAllLeftVarUint8x16 x y) => (V128Or (I8x16Shl x y) (I8x16ShrU x (I64Sub (I64Const [8]) y))) +(RotateAllLeftVarInt16x8 x y) => (V128Or (I16x8Shl x y) (I16x8ShrU x (I64Sub (I64Const [16]) y))) +(RotateAllLeftVarUint16x8 x y) => (V128Or (I16x8Shl x y) (I16x8ShrU x (I64Sub (I64Const [16]) y))) +(RotateAllLeftVarInt32x4 x y) => (V128Or (I32x4Shl x y) (I32x4ShrU x (I64Sub (I64Const [32]) y))) +(RotateAllLeftVarUint32x4 x y) => (V128Or (I32x4Shl x y) (I32x4ShrU x (I64Sub (I64Const [32]) y))) +(RotateAllLeftVarInt64x2 x y) => (V128Or (I64x2Shl x y) (I64x2ShrU x (I64Sub (I64Const [64]) y))) +(RotateAllLeftVarUint64x2 x y) => (V128Or (I64x2Shl x y) (I64x2ShrU x (I64Sub (I64Const [64]) y))) +(RotateAllRightVarInt8x16 x y) => (V128Or (I8x16ShrU x y) (I8x16Shl x (I64Sub (I64Const [8]) y))) +(RotateAllRightVarUint8x16 x y) => (V128Or (I8x16ShrU x y) (I8x16Shl x (I64Sub (I64Const [8]) y))) +(RotateAllRightVarInt16x8 x y) => (V128Or (I16x8ShrU x y) (I16x8Shl x (I64Sub (I64Const [16]) y))) +(RotateAllRightVarUint16x8 x y) => (V128Or (I16x8ShrU x y) (I16x8Shl x (I64Sub (I64Const [16]) y))) +(RotateAllRightVarInt32x4 x y) => (V128Or (I32x4ShrU x y) (I32x4Shl x (I64Sub (I64Const [32]) y))) +(RotateAllRightVarUint32x4 x y) => (V128Or (I32x4ShrU x y) (I32x4Shl x (I64Sub (I64Const [32]) y))) +(RotateAllRightVarInt64x2 x y) => (V128Or (I64x2ShrU x y) (I64x2Shl x (I64Sub (I64Const [64]) y))) +(RotateAllRightVarUint64x2 x y) => (V128Or (I64x2ShrU x y) (I64x2Shl x (I64Sub (I64Const [64]) y))) +(RoundFloat32x4 ...) => (F32x4Nearest ...) +(RoundFloat64x2 ...) => (F64x2Nearest ...) +(SetElemInt8x16 ...) => (I8x16ReplaceLane ...) +(SetElemUint8x16 ...) => (I8x16ReplaceLane ...) +(SetElemInt16x8 ...) => (I16x8ReplaceLane ...) +(SetElemUint16x8 ...) => (I16x8ReplaceLane ...) +(SetElemInt32x4 ...) => (I32x4ReplaceLane ...) +(SetElemUint32x4 ...) => (I32x4ReplaceLane ...) +(SetElemFloat32x4 ...) => (F32x4ReplaceLane ...) +(SetElemInt64x2 ...) => (I64x2ReplaceLane ...) +(SetElemUint64x2 ...) => (I64x2ReplaceLane ...) +(SetElemFloat64x2 ...) => (F64x2ReplaceLane ...) +(ShiftAllLeftInt8x16 x d:(Const64 [c])) && uint64(c) < 8 => (I8x16Shl x (I64Const [c])) +(ShiftAllLeftInt8x16 x d:(I64Const [c])) && uint64(c) < 8 => (I8x16Shl x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllLeftInt8x16 x y) => (SelectV (I8x16Shl x y) (V128Xor x x) (I64LtU y (I64Const [8]))) +(ShiftAllLeftUint8x16 x d:(Const64 [c])) && uint64(c) < 8 => (I8x16Shl x (I64Const [c])) +(ShiftAllLeftUint8x16 x d:(I64Const [c])) && uint64(c) < 8 => (I8x16Shl x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllLeftUint8x16 x y) => (SelectV (I8x16Shl x y) (V128Xor x x) (I64LtU y (I64Const [8]))) +(ShiftAllLeftInt16x8 x d:(Const64 [c])) && uint64(c) < 16 => (I16x8Shl x (I64Const [c])) +(ShiftAllLeftInt16x8 x d:(I64Const [c])) && uint64(c) < 16 => (I16x8Shl x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllLeftInt16x8 x y) => (SelectV (I16x8Shl x y) (V128Xor x x) (I64LtU y (I64Const [16]))) +(ShiftAllLeftUint16x8 x d:(Const64 [c])) && uint64(c) < 16 => (I16x8Shl x (I64Const [c])) +(ShiftAllLeftUint16x8 x d:(I64Const [c])) && uint64(c) < 16 => (I16x8Shl x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllLeftUint16x8 x y) => (SelectV (I16x8Shl x y) (V128Xor x x) (I64LtU y (I64Const [16]))) +(ShiftAllLeftInt32x4 x d:(Const64 [c])) && uint64(c) < 32 => (I32x4Shl x (I64Const [c])) +(ShiftAllLeftInt32x4 x d:(I64Const [c])) && uint64(c) < 32 => (I32x4Shl x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllLeftInt32x4 x y) => (SelectV (I32x4Shl x y) (V128Xor x x) (I64LtU y (I64Const [32]))) +(ShiftAllLeftUint32x4 x d:(Const64 [c])) && uint64(c) < 32 => (I32x4Shl x (I64Const [c])) +(ShiftAllLeftUint32x4 x d:(I64Const [c])) && uint64(c) < 32 => (I32x4Shl x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllLeftUint32x4 x y) => (SelectV (I32x4Shl x y) (V128Xor x x) (I64LtU y (I64Const [32]))) +(ShiftAllLeftInt64x2 x d:(Const64 [c])) && uint64(c) < 64 => (I64x2Shl x (I64Const [c])) +(ShiftAllLeftInt64x2 x d:(I64Const [c])) && uint64(c) < 64 => (I64x2Shl x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllLeftInt64x2 x y) => (SelectV (I64x2Shl x y) (V128Xor x x) (I64LtU y (I64Const [64]))) +(ShiftAllLeftUint64x2 x d:(Const64 [c])) && uint64(c) < 64 => (I64x2Shl x (I64Const [c])) +(ShiftAllLeftUint64x2 x d:(I64Const [c])) && uint64(c) < 64 => (I64x2Shl x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllLeftUint64x2 x y) => (SelectV (I64x2Shl x y) (V128Xor x x) (I64LtU y (I64Const [64]))) +(ShiftAllRightInt8x16 x d:(Const64 [c])) && uint64(c) < 8 => (I8x16ShrS x (I64Const [c])) +(ShiftAllRightInt8x16 x d:(I64Const [c])) && uint64(c) < 8 => (I8x16ShrS x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllRightInt8x16 x y) => (SelectV (I8x16ShrS x y) (I8x16ShrS x (I64Const [7])) (I64LtU y (I64Const [8]))) +(ShiftAllRightUint8x16 x d:(Const64 [c])) && uint64(c) < 8 => (I8x16ShrU x (I64Const [c])) +(ShiftAllRightUint8x16 x d:(I64Const [c])) && uint64(c) < 8 => (I8x16ShrU x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllRightUint8x16 x y) => (SelectV (I8x16ShrU x y) (V128Xor x x) (I64LtU y (I64Const [8]))) +(ShiftAllRightInt16x8 x d:(Const64 [c])) && uint64(c) < 16 => (I16x8ShrS x (I64Const [c])) +(ShiftAllRightInt16x8 x d:(I64Const [c])) && uint64(c) < 16 => (I16x8ShrS x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllRightInt16x8 x y) => (SelectV (I16x8ShrS x y) (I16x8ShrS x (I64Const [15])) (I64LtU y (I64Const [16]))) +(ShiftAllRightUint16x8 x d:(Const64 [c])) && uint64(c) < 16 => (I16x8ShrU x (I64Const [c])) +(ShiftAllRightUint16x8 x d:(I64Const [c])) && uint64(c) < 16 => (I16x8ShrU x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllRightUint16x8 x y) => (SelectV (I16x8ShrU x y) (V128Xor x x) (I64LtU y (I64Const [16]))) +(ShiftAllRightInt32x4 x d:(Const64 [c])) && uint64(c) < 32 => (I32x4ShrS x (I64Const [c])) +(ShiftAllRightInt32x4 x d:(I64Const [c])) && uint64(c) < 32 => (I32x4ShrS x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllRightInt32x4 x y) => (SelectV (I32x4ShrS x y) (I32x4ShrS x (I64Const [31])) (I64LtU y (I64Const [32]))) +(ShiftAllRightUint32x4 x d:(Const64 [c])) && uint64(c) < 32 => (I32x4ShrU x (I64Const [c])) +(ShiftAllRightUint32x4 x d:(I64Const [c])) && uint64(c) < 32 => (I32x4ShrU x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllRightUint32x4 x y) => (SelectV (I32x4ShrU x y) (V128Xor x x) (I64LtU y (I64Const [32]))) +(ShiftAllRightInt64x2 x d:(Const64 [c])) && uint64(c) < 64 => (I64x2ShrS x (I64Const [c])) +(ShiftAllRightInt64x2 x d:(I64Const [c])) && uint64(c) < 64 => (I64x2ShrS x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllRightInt64x2 x y) => (SelectV (I64x2ShrS x y) (I64x2ShrS x (I64Const [63])) (I64LtU y (I64Const [64]))) +(ShiftAllRightUint64x2 x d:(Const64 [c])) && uint64(c) < 64 => (I64x2ShrU x (I64Const [c])) +(ShiftAllRightUint64x2 x d:(I64Const [c])) && uint64(c) < 64 => (I64x2ShrU x d) +// TODO need to do 'shiftIsBounded' for WASM SIMD Shifts +(ShiftAllRightUint64x2 x y) => (SelectV (I64x2ShrU x y) (V128Xor x x) (I64LtU y (I64Const [64]))) +(SqrtFloat32x4 ...) => (F32x4Sqrt ...) +(SqrtFloat64x2 ...) => (F64x2Sqrt ...) +(SubInt8x16 ...) => (I8x16Sub ...) +(SubInt16x8 ...) => (I16x8Sub ...) +(SubInt32x4 ...) => (I32x4Sub ...) +(SubFloat32x4 ...) => (F32x4Sub ...) +(SubInt64x2 ...) => (I64x2Sub ...) +(SubFloat64x2 ...) => (F64x2Sub ...) +(SubSaturatedInt8x16 ...) => (I8x16SubSatS ...) +(SubSaturatedUint8x16 ...) => (I8x16SubSatU ...) +(SubSaturatedInt16x8 ...) => (I16x8SubSatS ...) +(SubSaturatedUint16x8 ...) => (I16x8SubSatU ...) +(TruncFloat32x4 ...) => (F32x4Trunc ...) +(TruncFloat64x2 ...) => (F64x2Trunc ...) +(XorInt8x16 ...) => (V128Xor ...) +(XorUint8x16 ...) => (V128Xor ...) +(XorInt16x8 ...) => (V128Xor ...) +(XorUint16x8 ...) => (V128Xor ...) +(XorInt32x4 ...) => (V128Xor ...) +(XorUint32x4 ...) => (V128Xor ...) +(XorInt64x2 ...) => (V128Xor ...) +(XorUint64x2 ...) => (V128Xor ...) diff --git a/src/cmd/compile/internal/ssa/_gen/simdWasmops.go b/src/cmd/compile/internal/ssa/_gen/simdWasmops.go new file mode 100644 index 00000000000000..9a1356eeb7f34f --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/simdWasmops.go @@ -0,0 +1,208 @@ +// Code generated by 'wasmgen'; DO NOT EDIT. + +package main + +func simdWasmOps(vload, vstore, v11, v21, v31, v11gp, v11fp32, v11fp64, v1gpv, v1fp32v, v1fp64v, gpv, fp32v, fp64v regInfo) []opData { + return []opData{ + {name: "I8x16AllTrue", argLength: 1, reg: v11, asm: "I8x16AllTrue", typ: "Bool"}, + {name: "V128AnyTrue", argLength: 1, reg: v11, asm: "V128AnyTrue", typ: "Bool"}, + {name: "I16x8AllTrue", argLength: 1, reg: v11, asm: "I16x8AllTrue", typ: "Bool"}, + {name: "I16x8Q15MulrSatS", argLength: 2, reg: v21, asm: "I16x8Q15MulrSatS", typ: "Vec128"}, + {name: "I16x8RelaxedQ15MulrS", argLength: 2, reg: v21, asm: "I16x8RelaxedQ15MulrS", typ: "Vec128"}, + {name: "I32x4AllTrue", argLength: 1, reg: v11, asm: "I32x4AllTrue", typ: "Bool"}, + {name: "F32x4Pmax", argLength: 2, reg: v21, asm: "F32x4Pmax", commutative: true, typ: "Vec128"}, + {name: "F32x4Pmin", argLength: 2, reg: v21, asm: "F32x4Pmin", commutative: true, typ: "Vec128"}, + {name: "F32x4RelaxedMax", argLength: 2, reg: v21, asm: "F32x4RelaxedMax", commutative: true, typ: "Vec128"}, + {name: "F32x4RelaxedMin", argLength: 2, reg: v21, asm: "F32x4RelaxedMin", commutative: true, typ: "Vec128"}, + {name: "I64x2AllTrue", argLength: 1, reg: v11, asm: "I64x2AllTrue", typ: "Bool"}, + {name: "F64x2Pmax", argLength: 2, reg: v21, asm: "F64x2Pmax", commutative: true, typ: "Vec128"}, + {name: "F64x2Pmin", argLength: 2, reg: v21, asm: "F64x2Pmin", commutative: true, typ: "Vec128"}, + {name: "F64x2RelaxedMax", argLength: 2, reg: v21, asm: "F64x2RelaxedMax", commutative: true, typ: "Vec128"}, + {name: "F64x2RelaxedMin", argLength: 2, reg: v21, asm: "F64x2RelaxedMin", commutative: true, typ: "Vec128"}, + {name: "I8x16Abs", argLength: 1, reg: v11, asm: "I8x16Abs", typ: "Vec128"}, + {name: "I16x8Abs", argLength: 1, reg: v11, asm: "I16x8Abs", typ: "Vec128"}, + {name: "I32x4Abs", argLength: 1, reg: v11, asm: "I32x4Abs", typ: "Vec128"}, + {name: "F32x4Abs", argLength: 1, reg: v11, asm: "F32x4Abs", typ: "Vec128"}, + {name: "I64x2Abs", argLength: 1, reg: v11, asm: "I64x2Abs", typ: "Vec128"}, + {name: "F64x2Abs", argLength: 1, reg: v11, asm: "F64x2Abs", typ: "Vec128"}, + {name: "I8x16Add", argLength: 2, reg: v21, asm: "I8x16Add", commutative: true, typ: "Vec128"}, + {name: "I16x8Add", argLength: 2, reg: v21, asm: "I16x8Add", commutative: true, typ: "Vec128"}, + {name: "I32x4Add", argLength: 2, reg: v21, asm: "I32x4Add", commutative: true, typ: "Vec128"}, + {name: "F32x4Add", argLength: 2, reg: v21, asm: "F32x4Add", commutative: true, typ: "Vec128"}, + {name: "I64x2Add", argLength: 2, reg: v21, asm: "I64x2Add", commutative: true, typ: "Vec128"}, + {name: "F64x2Add", argLength: 2, reg: v21, asm: "F64x2Add", commutative: true, typ: "Vec128"}, + {name: "I8x16AddSatS", argLength: 2, reg: v21, asm: "I8x16AddSatS", commutative: true, typ: "Vec128"}, + {name: "I8x16AddSatU", argLength: 2, reg: v21, asm: "I8x16AddSatU", commutative: true, typ: "Vec128"}, + {name: "I16x8AddSatS", argLength: 2, reg: v21, asm: "I16x8AddSatS", commutative: true, typ: "Vec128"}, + {name: "I16x8AddSatU", argLength: 2, reg: v21, asm: "I16x8AddSatU", commutative: true, typ: "Vec128"}, + {name: "V128And", argLength: 2, reg: v21, asm: "V128And", commutative: true, typ: "Vec128"}, + {name: "V128Andnot", argLength: 2, reg: v21, asm: "V128Andnot", typ: "Vec128"}, + {name: "I8x16AvgrU", argLength: 2, reg: v21, asm: "I8x16AvgrU", commutative: true, typ: "Vec128"}, + {name: "I16x8AvgrU", argLength: 2, reg: v21, asm: "I16x8AvgrU", commutative: true, typ: "Vec128"}, + {name: "V128Bitselect", argLength: 3, reg: v31, asm: "V128Bitselect", typ: "Vec128"}, + {name: "I8x16Splat", argLength: 1, reg: gpv, asm: "I8x16Splat", typ: "Vec128"}, + {name: "I16x8Splat", argLength: 1, reg: gpv, asm: "I16x8Splat", typ: "Vec128"}, + {name: "I32x4Splat", argLength: 1, reg: gpv, asm: "I32x4Splat", typ: "Vec128"}, + {name: "F32x4Splat", argLength: 1, reg: fp32v, asm: "F32x4Splat", typ: "Vec128"}, + {name: "I64x2Splat", argLength: 1, reg: gpv, asm: "I64x2Splat", typ: "Vec128"}, + {name: "F64x2Splat", argLength: 1, reg: fp64v, asm: "F64x2Splat", typ: "Vec128"}, + {name: "F32x4Ceil", argLength: 1, reg: v11, asm: "F32x4Ceil", typ: "Vec128"}, + {name: "F64x2Ceil", argLength: 1, reg: v11, asm: "F64x2Ceil", typ: "Vec128"}, + {name: "F64x2ConvertLowI32x4S", argLength: 1, reg: v11, asm: "F64x2ConvertLowI32x4S", typ: "Vec128"}, + {name: "F64x2ConvertLowI32x4U", argLength: 1, reg: v11, asm: "F64x2ConvertLowI32x4U", typ: "Vec128"}, + {name: "F32x4ConvertI32x4S", argLength: 1, reg: v11, asm: "F32x4ConvertI32x4S", typ: "Vec128"}, + {name: "F32x4ConvertI32x4U", argLength: 1, reg: v11, asm: "F32x4ConvertI32x4U", typ: "Vec128"}, + {name: "I32x4TruncSatF32x4S", argLength: 1, reg: v11, asm: "I32x4TruncSatF32x4S", typ: "Vec128"}, + {name: "I32x4TruncSatF32x4U", argLength: 1, reg: v11, asm: "I32x4TruncSatF32x4U", typ: "Vec128"}, + {name: "F32x4Div", argLength: 2, reg: v21, asm: "F32x4Div", typ: "Vec128"}, + {name: "F64x2Div", argLength: 2, reg: v21, asm: "F64x2Div", typ: "Vec128"}, + {name: "I8x16Eq", argLength: 2, reg: v21, asm: "I8x16Eq", commutative: true, typ: "Vec128"}, + {name: "I16x8Eq", argLength: 2, reg: v21, asm: "I16x8Eq", commutative: true, typ: "Vec128"}, + {name: "I32x4Eq", argLength: 2, reg: v21, asm: "I32x4Eq", commutative: true, typ: "Vec128"}, + {name: "F32x4Eq", argLength: 2, reg: v21, asm: "F32x4Eq", commutative: true, typ: "Vec128"}, + {name: "I64x2Eq", argLength: 2, reg: v21, asm: "I64x2Eq", commutative: true, typ: "Vec128"}, + {name: "F64x2Eq", argLength: 2, reg: v21, asm: "F64x2Eq", commutative: true, typ: "Vec128"}, + {name: "I64x2ExtendHighI32x4S", argLength: 1, reg: v11, asm: "I64x2ExtendHighI32x4S", typ: "Vec128"}, + {name: "I64x2ExtendHighI32x4U", argLength: 1, reg: v11, asm: "I64x2ExtendHighI32x4U", typ: "Vec128"}, + {name: "I32x4ExtendHighI16x8S", argLength: 1, reg: v11, asm: "I32x4ExtendHighI16x8S", typ: "Vec128"}, + {name: "I32x4ExtendHighI16x8U", argLength: 1, reg: v11, asm: "I32x4ExtendHighI16x8U", typ: "Vec128"}, + {name: "I16x8ExtendHighI8x16S", argLength: 1, reg: v11, asm: "I16x8ExtendHighI8x16S", typ: "Vec128"}, + {name: "I16x8ExtendHighI8x16U", argLength: 1, reg: v11, asm: "I16x8ExtendHighI8x16U", typ: "Vec128"}, + {name: "I64x2ExtendLowI32x4S", argLength: 1, reg: v11, asm: "I64x2ExtendLowI32x4S", typ: "Vec128"}, + {name: "I64x2ExtendLowI32x4U", argLength: 1, reg: v11, asm: "I64x2ExtendLowI32x4U", typ: "Vec128"}, + {name: "I32x4ExtendLowI16x8S", argLength: 1, reg: v11, asm: "I32x4ExtendLowI16x8S", typ: "Vec128"}, + {name: "I32x4ExtendLowI16x8U", argLength: 1, reg: v11, asm: "I32x4ExtendLowI16x8U", typ: "Vec128"}, + {name: "I16x8ExtendLowI8x16S", argLength: 1, reg: v11, asm: "I16x8ExtendLowI8x16S", typ: "Vec128"}, + {name: "I16x8ExtendLowI8x16U", argLength: 1, reg: v11, asm: "I16x8ExtendLowI8x16U", typ: "Vec128"}, + {name: "F32x4Floor", argLength: 1, reg: v11, asm: "F32x4Floor", typ: "Vec128"}, + {name: "F64x2Floor", argLength: 1, reg: v11, asm: "F64x2Floor", typ: "Vec128"}, + {name: "I8x16ExtractLaneS", argLength: 1, reg: v11gp, asm: "I8x16ExtractLaneS", aux: "UInt8", typ: "Vec128"}, + {name: "I8x16ExtractLaneU", argLength: 1, reg: v11gp, asm: "I8x16ExtractLaneU", aux: "UInt8", typ: "Vec128"}, + {name: "I16x8ExtractLaneS", argLength: 1, reg: v11gp, asm: "I16x8ExtractLaneS", aux: "UInt8", typ: "Vec128"}, + {name: "I16x8ExtractLaneU", argLength: 1, reg: v11gp, asm: "I16x8ExtractLaneU", aux: "UInt8", typ: "Vec128"}, + {name: "I32x4ExtractLane", argLength: 1, reg: v11gp, asm: "I32x4ExtractLane", aux: "UInt8", typ: "Vec128"}, + {name: "F32x4ExtractLane", argLength: 1, reg: v11fp32, asm: "F32x4ExtractLane", aux: "UInt8", typ: "Vec128"}, + {name: "I64x2ExtractLane", argLength: 1, reg: v11gp, asm: "I64x2ExtractLane", aux: "UInt8", typ: "Vec128"}, + {name: "F64x2ExtractLane", argLength: 1, reg: v11fp64, asm: "F64x2ExtractLane", aux: "UInt8", typ: "Vec128"}, + {name: "I8x16GtS", argLength: 2, reg: v21, asm: "I8x16GtS", typ: "Vec128"}, + {name: "I8x16GtU", argLength: 2, reg: v21, asm: "I8x16GtU", typ: "Vec128"}, + {name: "I16x8GtS", argLength: 2, reg: v21, asm: "I16x8GtS", typ: "Vec128"}, + {name: "I16x8GtU", argLength: 2, reg: v21, asm: "I16x8GtU", typ: "Vec128"}, + {name: "I32x4GtS", argLength: 2, reg: v21, asm: "I32x4GtS", typ: "Vec128"}, + {name: "I32x4GtU", argLength: 2, reg: v21, asm: "I32x4GtU", typ: "Vec128"}, + {name: "F32x4Gt", argLength: 2, reg: v21, asm: "F32x4Gt", typ: "Vec128"}, + {name: "I64x2GtS", argLength: 2, reg: v21, asm: "I64x2GtS", typ: "Vec128"}, + {name: "F64x2Gt", argLength: 2, reg: v21, asm: "F64x2Gt", typ: "Vec128"}, + {name: "I8x16GeS", argLength: 2, reg: v21, asm: "I8x16GeS", typ: "Vec128"}, + {name: "I8x16GeU", argLength: 2, reg: v21, asm: "I8x16GeU", typ: "Vec128"}, + {name: "I16x8GeS", argLength: 2, reg: v21, asm: "I16x8GeS", typ: "Vec128"}, + {name: "I16x8GeU", argLength: 2, reg: v21, asm: "I16x8GeU", typ: "Vec128"}, + {name: "I32x4GeS", argLength: 2, reg: v21, asm: "I32x4GeS", typ: "Vec128"}, + {name: "I32x4GeU", argLength: 2, reg: v21, asm: "I32x4GeU", typ: "Vec128"}, + {name: "F32x4Ge", argLength: 2, reg: v21, asm: "F32x4Ge", typ: "Vec128"}, + {name: "I64x2GeS", argLength: 2, reg: v21, asm: "I64x2GeS", typ: "Vec128"}, + {name: "F64x2Ge", argLength: 2, reg: v21, asm: "F64x2Ge", typ: "Vec128"}, + {name: "I8x16LtS", argLength: 2, reg: v21, asm: "I8x16LtS", typ: "Vec128"}, + {name: "I8x16LtU", argLength: 2, reg: v21, asm: "I8x16LtU", typ: "Vec128"}, + {name: "I16x8LtS", argLength: 2, reg: v21, asm: "I16x8LtS", typ: "Vec128"}, + {name: "I16x8LtU", argLength: 2, reg: v21, asm: "I16x8LtU", typ: "Vec128"}, + {name: "I32x4LtS", argLength: 2, reg: v21, asm: "I32x4LtS", typ: "Vec128"}, + {name: "I32x4LtU", argLength: 2, reg: v21, asm: "I32x4LtU", typ: "Vec128"}, + {name: "F32x4Lt", argLength: 2, reg: v21, asm: "F32x4Lt", typ: "Vec128"}, + {name: "I64x2LtS", argLength: 2, reg: v21, asm: "I64x2LtS", typ: "Vec128"}, + {name: "F64x2Lt", argLength: 2, reg: v21, asm: "F64x2Lt", typ: "Vec128"}, + {name: "I8x16LeS", argLength: 2, reg: v21, asm: "I8x16LeS", typ: "Vec128"}, + {name: "I8x16LeU", argLength: 2, reg: v21, asm: "I8x16LeU", typ: "Vec128"}, + {name: "I16x8LeS", argLength: 2, reg: v21, asm: "I16x8LeS", typ: "Vec128"}, + {name: "I16x8LeU", argLength: 2, reg: v21, asm: "I16x8LeU", typ: "Vec128"}, + {name: "I32x4LeS", argLength: 2, reg: v21, asm: "I32x4LeS", typ: "Vec128"}, + {name: "I32x4LeU", argLength: 2, reg: v21, asm: "I32x4LeU", typ: "Vec128"}, + {name: "F32x4Le", argLength: 2, reg: v21, asm: "F32x4Le", typ: "Vec128"}, + {name: "I64x2LeS", argLength: 2, reg: v21, asm: "I64x2LeS", typ: "Vec128"}, + {name: "F64x2Le", argLength: 2, reg: v21, asm: "F64x2Le", typ: "Vec128"}, + {name: "I8x16Swizzle", argLength: 2, reg: v21, asm: "I8x16Swizzle", typ: "Vec128"}, + {name: "I8x16MaxS", argLength: 2, reg: v21, asm: "I8x16MaxS", commutative: true, typ: "Vec128"}, + {name: "I8x16MaxU", argLength: 2, reg: v21, asm: "I8x16MaxU", commutative: true, typ: "Vec128"}, + {name: "I16x8MaxS", argLength: 2, reg: v21, asm: "I16x8MaxS", commutative: true, typ: "Vec128"}, + {name: "I16x8MaxU", argLength: 2, reg: v21, asm: "I16x8MaxU", commutative: true, typ: "Vec128"}, + {name: "I32x4MaxS", argLength: 2, reg: v21, asm: "I32x4MaxS", commutative: true, typ: "Vec128"}, + {name: "I32x4MaxU", argLength: 2, reg: v21, asm: "I32x4MaxU", commutative: true, typ: "Vec128"}, + {name: "F32x4Max", argLength: 2, reg: v21, asm: "F32x4Max", commutative: true, typ: "Vec128"}, + {name: "F64x2Max", argLength: 2, reg: v21, asm: "F64x2Max", commutative: true, typ: "Vec128"}, + {name: "I8x16MinS", argLength: 2, reg: v21, asm: "I8x16MinS", commutative: true, typ: "Vec128"}, + {name: "I8x16MinU", argLength: 2, reg: v21, asm: "I8x16MinU", commutative: true, typ: "Vec128"}, + {name: "I16x8MinS", argLength: 2, reg: v21, asm: "I16x8MinS", commutative: true, typ: "Vec128"}, + {name: "I16x8MinU", argLength: 2, reg: v21, asm: "I16x8MinU", commutative: true, typ: "Vec128"}, + {name: "I32x4MinS", argLength: 2, reg: v21, asm: "I32x4MinS", commutative: true, typ: "Vec128"}, + {name: "I32x4MinU", argLength: 2, reg: v21, asm: "I32x4MinU", commutative: true, typ: "Vec128"}, + {name: "F32x4Min", argLength: 2, reg: v21, asm: "F32x4Min", commutative: true, typ: "Vec128"}, + {name: "F64x2Min", argLength: 2, reg: v21, asm: "F64x2Min", commutative: true, typ: "Vec128"}, + {name: "I16x8Mul", argLength: 2, reg: v21, asm: "I16x8Mul", commutative: true, typ: "Vec128"}, + {name: "I32x4Mul", argLength: 2, reg: v21, asm: "I32x4Mul", commutative: true, typ: "Vec128"}, + {name: "F32x4Mul", argLength: 2, reg: v21, asm: "F32x4Mul", commutative: true, typ: "Vec128"}, + {name: "I64x2Mul", argLength: 2, reg: v21, asm: "I64x2Mul", commutative: true, typ: "Vec128"}, + {name: "F64x2Mul", argLength: 2, reg: v21, asm: "F64x2Mul", commutative: true, typ: "Vec128"}, + {name: "I16x8ExtmulHighI8x16S", argLength: 2, reg: v21, asm: "I16x8ExtmulHighI8x16S", commutative: true, typ: "Vec128"}, + {name: "I16x8ExtmulHighI8x16U", argLength: 2, reg: v21, asm: "I16x8ExtmulHighI8x16U", commutative: true, typ: "Vec128"}, + {name: "I32x4ExtmulHighI16x8S", argLength: 2, reg: v21, asm: "I32x4ExtmulHighI16x8S", commutative: true, typ: "Vec128"}, + {name: "I32x4ExtmulHighI16x8U", argLength: 2, reg: v21, asm: "I32x4ExtmulHighI16x8U", commutative: true, typ: "Vec128"}, + {name: "I64x2ExtmulHighI32x4S", argLength: 2, reg: v21, asm: "I64x2ExtmulHighI32x4S", commutative: true, typ: "Vec128"}, + {name: "I64x2ExtmulHighI32x4U", argLength: 2, reg: v21, asm: "I64x2ExtmulHighI32x4U", commutative: true, typ: "Vec128"}, + {name: "I16x8ExtmulLowI8x16S", argLength: 2, reg: v21, asm: "I16x8ExtmulLowI8x16S", commutative: true, typ: "Vec128"}, + {name: "I16x8ExtmulLowI8x16U", argLength: 2, reg: v21, asm: "I16x8ExtmulLowI8x16U", commutative: true, typ: "Vec128"}, + {name: "I32x4ExtmulLowI16x8S", argLength: 2, reg: v21, asm: "I32x4ExtmulLowI16x8S", commutative: true, typ: "Vec128"}, + {name: "I32x4ExtmulLowI16x8U", argLength: 2, reg: v21, asm: "I32x4ExtmulLowI16x8U", commutative: true, typ: "Vec128"}, + {name: "I64x2ExtmulLowI32x4S", argLength: 2, reg: v21, asm: "I64x2ExtmulLowI32x4S", commutative: true, typ: "Vec128"}, + {name: "I64x2ExtmulLowI32x4U", argLength: 2, reg: v21, asm: "I64x2ExtmulLowI32x4U", commutative: true, typ: "Vec128"}, + {name: "I8x16Neg", argLength: 1, reg: v11, asm: "I8x16Neg", typ: "Vec128"}, + {name: "I16x8Neg", argLength: 1, reg: v11, asm: "I16x8Neg", typ: "Vec128"}, + {name: "I32x4Neg", argLength: 1, reg: v11, asm: "I32x4Neg", typ: "Vec128"}, + {name: "F32x4Neg", argLength: 1, reg: v11, asm: "F32x4Neg", typ: "Vec128"}, + {name: "I64x2Neg", argLength: 1, reg: v11, asm: "I64x2Neg", typ: "Vec128"}, + {name: "F64x2Neg", argLength: 1, reg: v11, asm: "F64x2Neg", typ: "Vec128"}, + {name: "V128Not", argLength: 1, reg: v11, asm: "V128Not", typ: "Vec128"}, + {name: "I8x16Ne", argLength: 2, reg: v21, asm: "I8x16Ne", commutative: true, typ: "Vec128"}, + {name: "I16x8Ne", argLength: 2, reg: v21, asm: "I16x8Ne", commutative: true, typ: "Vec128"}, + {name: "I32x4Ne", argLength: 2, reg: v21, asm: "I32x4Ne", commutative: true, typ: "Vec128"}, + {name: "F32x4Ne", argLength: 2, reg: v21, asm: "F32x4Ne", commutative: true, typ: "Vec128"}, + {name: "I64x2Ne", argLength: 2, reg: v21, asm: "I64x2Ne", commutative: true, typ: "Vec128"}, + {name: "F64x2Ne", argLength: 2, reg: v21, asm: "F64x2Ne", commutative: true, typ: "Vec128"}, + {name: "I8x16Popcnt", argLength: 1, reg: v11, asm: "I8x16Popcnt", typ: "Vec128"}, + {name: "V128Or", argLength: 2, reg: v21, asm: "V128Or", commutative: true, typ: "Vec128"}, + {name: "F32x4Nearest", argLength: 1, reg: v11, asm: "F32x4Nearest", typ: "Vec128"}, + {name: "F64x2Nearest", argLength: 1, reg: v11, asm: "F64x2Nearest", typ: "Vec128"}, + {name: "I8x16ReplaceLane", argLength: 2, reg: v1gpv, asm: "I8x16ReplaceLane", aux: "UInt8", typ: "Vec128"}, + {name: "I16x8ReplaceLane", argLength: 2, reg: v1gpv, asm: "I16x8ReplaceLane", aux: "UInt8", typ: "Vec128"}, + {name: "I32x4ReplaceLane", argLength: 2, reg: v1gpv, asm: "I32x4ReplaceLane", aux: "UInt8", typ: "Vec128"}, + {name: "F32x4ReplaceLane", argLength: 2, reg: v1fp32v, asm: "F32x4ReplaceLane", aux: "UInt8", typ: "Vec128"}, + {name: "I64x2ReplaceLane", argLength: 2, reg: v1gpv, asm: "I64x2ReplaceLane", aux: "UInt8", typ: "Vec128"}, + {name: "F64x2ReplaceLane", argLength: 2, reg: v1fp64v, asm: "F64x2ReplaceLane", aux: "UInt8", typ: "Vec128"}, + {name: "I8x16Shl", argLength: 2, reg: v1gpv, asm: "I8x16Shl", typ: "Vec128"}, + {name: "I16x8Shl", argLength: 2, reg: v1gpv, asm: "I16x8Shl", typ: "Vec128"}, + {name: "I32x4Shl", argLength: 2, reg: v1gpv, asm: "I32x4Shl", typ: "Vec128"}, + {name: "I64x2Shl", argLength: 2, reg: v1gpv, asm: "I64x2Shl", typ: "Vec128"}, + {name: "I8x16ShrS", argLength: 2, reg: v1gpv, asm: "I8x16ShrS", typ: "Vec128"}, + {name: "I8x16ShrU", argLength: 2, reg: v1gpv, asm: "I8x16ShrU", typ: "Vec128"}, + {name: "I16x8ShrS", argLength: 2, reg: v1gpv, asm: "I16x8ShrS", typ: "Vec128"}, + {name: "I16x8ShrU", argLength: 2, reg: v1gpv, asm: "I16x8ShrU", typ: "Vec128"}, + {name: "I32x4ShrS", argLength: 2, reg: v1gpv, asm: "I32x4ShrS", typ: "Vec128"}, + {name: "I32x4ShrU", argLength: 2, reg: v1gpv, asm: "I32x4ShrU", typ: "Vec128"}, + {name: "I64x2ShrS", argLength: 2, reg: v1gpv, asm: "I64x2ShrS", typ: "Vec128"}, + {name: "I64x2ShrU", argLength: 2, reg: v1gpv, asm: "I64x2ShrU", typ: "Vec128"}, + {name: "F32x4Sqrt", argLength: 1, reg: v11, asm: "F32x4Sqrt", typ: "Vec128"}, + {name: "F64x2Sqrt", argLength: 1, reg: v11, asm: "F64x2Sqrt", typ: "Vec128"}, + {name: "I8x16Sub", argLength: 2, reg: v21, asm: "I8x16Sub", typ: "Vec128"}, + {name: "I16x8Sub", argLength: 2, reg: v21, asm: "I16x8Sub", typ: "Vec128"}, + {name: "I32x4Sub", argLength: 2, reg: v21, asm: "I32x4Sub", typ: "Vec128"}, + {name: "F32x4Sub", argLength: 2, reg: v21, asm: "F32x4Sub", typ: "Vec128"}, + {name: "I64x2Sub", argLength: 2, reg: v21, asm: "I64x2Sub", typ: "Vec128"}, + {name: "F64x2Sub", argLength: 2, reg: v21, asm: "F64x2Sub", typ: "Vec128"}, + {name: "I8x16SubSatS", argLength: 2, reg: v21, asm: "I8x16SubSatS", typ: "Vec128"}, + {name: "I8x16SubSatU", argLength: 2, reg: v21, asm: "I8x16SubSatU", typ: "Vec128"}, + {name: "I16x8SubSatS", argLength: 2, reg: v21, asm: "I16x8SubSatS", typ: "Vec128"}, + {name: "I16x8SubSatU", argLength: 2, reg: v21, asm: "I16x8SubSatU", typ: "Vec128"}, + {name: "F32x4Trunc", argLength: 1, reg: v11, asm: "F32x4Trunc", typ: "Vec128"}, + {name: "F64x2Trunc", argLength: 1, reg: v11, asm: "F64x2Trunc", typ: "Vec128"}, + {name: "V128Xor", argLength: 2, reg: v21, asm: "V128Xor", commutative: true, typ: "Vec128"}, + } +} diff --git a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go new file mode 100644 index 00000000000000..829d6b4a912464 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go @@ -0,0 +1,1575 @@ +// Code generated by 'simdgen' (merged automatically); DO NOT EDIT. + +package main + +func simdGenericOps() []opData { + return []opData{ + {name: "AESDecryptLastRoundUint8x16", argLength: 2}, // ARCH:amd64 + {name: "AESDecryptLastRoundUint8x32", argLength: 2}, // ARCH:amd64 + {name: "AESDecryptLastRoundUint8x64", argLength: 2}, // ARCH:amd64 + {name: "AESDecryptOneRoundUint8x16", argLength: 2}, // ARCH:amd64 + {name: "AESDecryptOneRoundUint8x32", argLength: 2}, // ARCH:amd64 + {name: "AESDecryptOneRoundUint8x64", argLength: 2}, // ARCH:amd64 + {name: "AESEncryptLastRoundUint8x16", argLength: 2}, // ARCH:amd64 + {name: "AESEncryptLastRoundUint8x32", argLength: 2}, // ARCH:amd64 + {name: "AESEncryptLastRoundUint8x64", argLength: 2}, // ARCH:amd64 + {name: "AESEncryptOneRoundUint8x16", argLength: 2}, // ARCH:amd64 + {name: "AESEncryptOneRoundUint8x32", argLength: 2}, // ARCH:amd64 + {name: "AESEncryptOneRoundUint8x64", argLength: 2}, // ARCH:amd64 + {name: "AESInvMixColumnsUint32x4", argLength: 1}, // ARCH:amd64 + {name: "AbsFloat32x4", argLength: 1}, // ARCH:arm64,wasm + {name: "AbsFloat64x2", argLength: 1}, // ARCH:arm64,wasm + {name: "AbsInt8x16", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "AbsInt8x32", argLength: 1}, // ARCH:amd64 + {name: "AbsInt8x64", argLength: 1}, // ARCH:amd64 + {name: "AbsInt16x8", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "AbsInt16x16", argLength: 1}, // ARCH:amd64 + {name: "AbsInt16x32", argLength: 1}, // ARCH:amd64 + {name: "AbsInt32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "AbsInt32x8", argLength: 1}, // ARCH:amd64 + {name: "AbsInt32x16", argLength: 1}, // ARCH:amd64 + {name: "AbsInt64x2", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "AbsInt64x4", argLength: 1}, // ARCH:amd64 + {name: "AbsInt64x8", argLength: 1}, // ARCH:amd64 + {name: "AddFloat32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AddFloat32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddFloat32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddFloat64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AddFloat64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddFloat64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AddInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AddInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AddInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddInt64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AddInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddOddSubEvenFloat32x4", argLength: 2}, // ARCH:amd64 + {name: "AddOddSubEvenFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "AddOddSubEvenFloat64x2", argLength: 2}, // ARCH:amd64 + {name: "AddOddSubEvenFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "AddSaturatedInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AddSaturatedInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddSaturatedInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddSaturatedInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AddSaturatedInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddSaturatedInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddSaturatedInt32x4", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "AddSaturatedInt64x2", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "AddSaturatedUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AddSaturatedUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddSaturatedUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddSaturatedUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AddSaturatedUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddSaturatedUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddSaturatedUint32x4", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "AddSaturatedUint64x2", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "AddUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64 + {name: "AddUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64 + {name: "AddUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64 + {name: "AddUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64 + {name: "AddUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AddUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AndInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AndInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AndInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AndInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndNotInt8x16", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "AndNotInt8x32", argLength: 2}, // ARCH:amd64 + {name: "AndNotInt8x64", argLength: 2}, // ARCH:amd64 + {name: "AndNotInt16x8", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "AndNotInt16x16", argLength: 2}, // ARCH:amd64 + {name: "AndNotInt16x32", argLength: 2}, // ARCH:amd64 + {name: "AndNotInt32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "AndNotInt32x8", argLength: 2}, // ARCH:amd64 + {name: "AndNotInt32x16", argLength: 2}, // ARCH:amd64 + {name: "AndNotInt64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "AndNotInt64x4", argLength: 2}, // ARCH:amd64 + {name: "AndNotInt64x8", argLength: 2}, // ARCH:amd64 + {name: "AndNotUint8x16", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "AndNotUint8x32", argLength: 2}, // ARCH:amd64 + {name: "AndNotUint8x64", argLength: 2}, // ARCH:amd64 + {name: "AndNotUint16x8", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "AndNotUint16x16", argLength: 2}, // ARCH:amd64 + {name: "AndNotUint16x32", argLength: 2}, // ARCH:amd64 + {name: "AndNotUint32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "AndNotUint32x8", argLength: 2}, // ARCH:amd64 + {name: "AndNotUint32x16", argLength: 2}, // ARCH:amd64 + {name: "AndNotUint64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "AndNotUint64x4", argLength: 2}, // ARCH:amd64 + {name: "AndNotUint64x8", argLength: 2}, // ARCH:amd64 + {name: "AndUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AndUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AndUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AndUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AndUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AverageInt8x16", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "AverageInt16x8", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "AverageInt32x4", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "AverageUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AverageUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AverageUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AverageUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "AverageUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AverageUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AverageUint32x4", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "BitSelectInt8x16", argLength: 3}, // ARCH:wasm + {name: "BitSelectInt16x8", argLength: 3}, // ARCH:wasm + {name: "BitSelectInt32x4", argLength: 3}, // ARCH:wasm + {name: "BitSelectInt64x2", argLength: 3}, // ARCH:wasm + {name: "BitSelectUint8x16", argLength: 3}, // ARCH:wasm + {name: "BitSelectUint16x8", argLength: 3}, // ARCH:wasm + {name: "BitSelectUint32x4", argLength: 3}, // ARCH:wasm + {name: "BitSelectUint64x2", argLength: 3}, // ARCH:wasm + {name: "BroadcastFloat32x4", argLength: 1}, // ARCH:wasm + {name: "BroadcastFloat64x2", argLength: 1}, // ARCH:wasm + {name: "BroadcastInt8x16", argLength: 1}, // ARCH:wasm + {name: "BroadcastInt16x8", argLength: 1}, // ARCH:wasm + {name: "BroadcastInt32x4", argLength: 1}, // ARCH:wasm + {name: "BroadcastInt64x2", argLength: 1}, // ARCH:wasm + {name: "CeilFloat32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "CeilFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "CeilFloat64x2", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "CeilFloat64x4", argLength: 1}, // ARCH:amd64 + {name: "CompressFloat32x4", argLength: 2}, // ARCH:amd64 + {name: "CompressFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "CompressFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "CompressFloat64x2", argLength: 2}, // ARCH:amd64 + {name: "CompressFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "CompressFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "CompressInt8x16", argLength: 2}, // ARCH:amd64 + {name: "CompressInt8x32", argLength: 2}, // ARCH:amd64 + {name: "CompressInt8x64", argLength: 2}, // ARCH:amd64 + {name: "CompressInt16x8", argLength: 2}, // ARCH:amd64 + {name: "CompressInt16x16", argLength: 2}, // ARCH:amd64 + {name: "CompressInt16x32", argLength: 2}, // ARCH:amd64 + {name: "CompressInt32x4", argLength: 2}, // ARCH:amd64 + {name: "CompressInt32x8", argLength: 2}, // ARCH:amd64 + {name: "CompressInt32x16", argLength: 2}, // ARCH:amd64 + {name: "CompressInt64x2", argLength: 2}, // ARCH:amd64 + {name: "CompressInt64x4", argLength: 2}, // ARCH:amd64 + {name: "CompressInt64x8", argLength: 2}, // ARCH:amd64 + {name: "CompressUint8x16", argLength: 2}, // ARCH:amd64 + {name: "CompressUint8x32", argLength: 2}, // ARCH:amd64 + {name: "CompressUint8x64", argLength: 2}, // ARCH:amd64 + {name: "CompressUint16x8", argLength: 2}, // ARCH:amd64 + {name: "CompressUint16x16", argLength: 2}, // ARCH:amd64 + {name: "CompressUint16x32", argLength: 2}, // ARCH:amd64 + {name: "CompressUint32x4", argLength: 2}, // ARCH:amd64 + {name: "CompressUint32x8", argLength: 2}, // ARCH:amd64 + {name: "CompressUint32x16", argLength: 2}, // ARCH:amd64 + {name: "CompressUint64x2", argLength: 2}, // ARCH:amd64 + {name: "CompressUint64x4", argLength: 2}, // ARCH:amd64 + {name: "CompressUint64x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatAddPairsFloat32x4", argLength: 2}, // ARCH:amd64,arm64 + {name: "ConcatAddPairsFloat64x2", argLength: 2}, // ARCH:amd64,arm64 + {name: "ConcatAddPairsGroupedFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatAddPairsGroupedFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "ConcatAddPairsGroupedInt16x16", argLength: 2}, // ARCH:amd64 + {name: "ConcatAddPairsGroupedInt32x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatAddPairsGroupedUint16x16", argLength: 2}, // ARCH:amd64 + {name: "ConcatAddPairsGroupedUint32x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatAddPairsInt16x8", argLength: 2}, // ARCH:amd64,arm64 + {name: "ConcatAddPairsInt32x4", argLength: 2}, // ARCH:amd64,arm64 + {name: "ConcatAddPairsInt64x2", argLength: 2}, // ARCH:arm64 + {name: "ConcatAddPairsSaturatedGroupedInt16x16", argLength: 2}, // ARCH:amd64 + {name: "ConcatAddPairsSaturatedInt16x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatAddPairsUint16x8", argLength: 2}, // ARCH:amd64,arm64 + {name: "ConcatAddPairsUint32x4", argLength: 2}, // ARCH:amd64,arm64 + {name: "ConcatAddPairsUint64x2", argLength: 2}, // ARCH:arm64 + {name: "ConcatEvenInt8x16", argLength: 2}, // ARCH:arm64 + {name: "ConcatEvenInt16x8", argLength: 2}, // ARCH:arm64 + {name: "ConcatEvenInt32x4", argLength: 2}, // ARCH:arm64 + {name: "ConcatEvenInt64x2", argLength: 2}, // ARCH:arm64 + {name: "ConcatEvenUint8x16", argLength: 2}, // ARCH:arm64 + {name: "ConcatEvenUint16x8", argLength: 2}, // ARCH:arm64 + {name: "ConcatEvenUint32x4", argLength: 2}, // ARCH:arm64 + {name: "ConcatEvenUint64x2", argLength: 2}, // ARCH:arm64 + {name: "ConcatOddInt8x16", argLength: 2}, // ARCH:arm64 + {name: "ConcatOddInt16x8", argLength: 2}, // ARCH:arm64 + {name: "ConcatOddInt32x4", argLength: 2}, // ARCH:arm64 + {name: "ConcatOddInt64x2", argLength: 2}, // ARCH:arm64 + {name: "ConcatOddUint8x16", argLength: 2}, // ARCH:arm64 + {name: "ConcatOddUint16x8", argLength: 2}, // ARCH:arm64 + {name: "ConcatOddUint32x4", argLength: 2}, // ARCH:arm64 + {name: "ConcatOddUint64x2", argLength: 2}, // ARCH:arm64 + {name: "ConcatPermuteFloat32x4", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteFloat32x8", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteFloat32x16", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteFloat64x2", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteFloat64x4", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteFloat64x8", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt8x16", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt8x32", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt8x64", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt16x8", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt16x16", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt16x32", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt32x4", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt32x8", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt32x16", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt64x2", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt64x4", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteInt64x8", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint8x16", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint8x32", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint8x64", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint16x8", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint16x16", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint16x32", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint32x4", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint32x8", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint32x16", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint64x2", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint64x4", argLength: 3}, // ARCH:amd64 + {name: "ConcatPermuteUint64x8", argLength: 3}, // ARCH:amd64 + {name: "ConcatSubPairsFloat32x4", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsFloat64x2", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsGroupedFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsGroupedFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsGroupedInt16x16", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsGroupedInt32x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsGroupedUint16x16", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsGroupedUint32x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsInt16x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsInt32x4", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsSaturatedGroupedInt16x16", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsSaturatedInt16x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsUint16x8", argLength: 2}, // ARCH:amd64 + {name: "ConcatSubPairsUint32x4", argLength: 2}, // ARCH:amd64 + {name: "ConvertLo2ToFloat64Float32x4", argLength: 1}, // ARCH:arm64 + {name: "ConvertLo2ToFloat64Int32x4", argLength: 1}, // ARCH:wasm + {name: "ConvertLo2ToFloat64Uint32x4", argLength: 1}, // ARCH:wasm + {name: "ConvertToFloat32Float64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "ConvertToFloat32Float64x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Float64x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Int32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "ConvertToFloat32Int32x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Int32x16", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Int64x2", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Int64x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Int64x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Uint32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "ConvertToFloat32Uint32x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Uint32x16", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Uint64x2", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Uint64x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat32Uint64x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat64Float32x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat64Float32x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat64Int32x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat64Int32x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat64Int64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "ConvertToFloat64Int64x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat64Int64x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat64Uint32x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat64Uint32x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat64Uint64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "ConvertToFloat64Uint64x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToFloat64Uint64x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToInt32Float32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "ConvertToInt32Float32x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToInt32Float32x16", argLength: 1}, // ARCH:amd64 + {name: "ConvertToInt32Float64x2", argLength: 1}, // ARCH:amd64 + {name: "ConvertToInt32Float64x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToInt32Float64x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToInt64Float32x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToInt64Float32x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToInt64Float64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "ConvertToInt64Float64x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToInt64Float64x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToUint32Float32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "ConvertToUint32Float32x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToUint32Float32x16", argLength: 1}, // ARCH:amd64 + {name: "ConvertToUint32Float64x2", argLength: 1}, // ARCH:amd64 + {name: "ConvertToUint32Float64x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToUint32Float64x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToUint64Float32x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToUint64Float32x8", argLength: 1}, // ARCH:amd64 + {name: "ConvertToUint64Float64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "ConvertToUint64Float64x4", argLength: 1}, // ARCH:amd64 + {name: "ConvertToUint64Float64x8", argLength: 1}, // ARCH:amd64 + {name: "DivFloat32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "DivFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "DivFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "DivFloat64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "DivFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "DivFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "DotProductPairsInt16x8", argLength: 2}, // ARCH:amd64 + {name: "DotProductPairsInt16x16", argLength: 2}, // ARCH:amd64 + {name: "DotProductPairsInt16x32", argLength: 2}, // ARCH:amd64 + {name: "DotProductPairsSaturatedUint8x16", argLength: 2}, // ARCH:amd64 + {name: "DotProductPairsSaturatedUint8x32", argLength: 2}, // ARCH:amd64 + {name: "DotProductPairsSaturatedUint8x64", argLength: 2}, // ARCH:amd64 + {name: "EqualFloat32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "EqualFloat32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualFloat32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualFloat64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "EqualFloat64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualFloat64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "EqualInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "EqualInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "EqualInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "EqualInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "EqualUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "EqualUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "EqualUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "EqualUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "ExpandFloat32x4", argLength: 2}, // ARCH:amd64 + {name: "ExpandFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "ExpandFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "ExpandFloat64x2", argLength: 2}, // ARCH:amd64 + {name: "ExpandFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "ExpandFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt8x16", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt8x32", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt8x64", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt16x8", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt16x16", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt16x32", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt32x4", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt32x8", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt32x16", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt64x2", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt64x4", argLength: 2}, // ARCH:amd64 + {name: "ExpandInt64x8", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint8x16", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint8x32", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint8x64", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint16x8", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint16x16", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint16x32", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint32x4", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint32x8", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint32x16", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint64x2", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint64x4", argLength: 2}, // ARCH:amd64 + {name: "ExpandUint64x8", argLength: 2}, // ARCH:amd64 + {name: "ExtendHi2ToInt64Int32x4", argLength: 1}, // ARCH:wasm + {name: "ExtendHi2ToUint64Uint32x4", argLength: 1}, // ARCH:wasm + {name: "ExtendHi4ToInt32Int16x8", argLength: 1}, // ARCH:wasm + {name: "ExtendHi4ToUint32Uint16x8", argLength: 1}, // ARCH:wasm + {name: "ExtendHi8ToInt16Int8x16", argLength: 1}, // ARCH:wasm + {name: "ExtendHi8ToUint16Uint8x16", argLength: 1}, // ARCH:wasm + {name: "ExtendLo2ToInt64Int8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo2ToInt64Int16x8", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo2ToInt64Int32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "ExtendLo2ToUint64Uint8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo2ToUint64Uint16x8", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo2ToUint64Uint32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "ExtendLo4ToInt32Int8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo4ToInt32Int16x8", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "ExtendLo4ToInt64Int8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo4ToInt64Int16x8", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo4ToUint32Uint8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo4ToUint32Uint16x8", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "ExtendLo4ToUint64Uint8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo4ToUint64Uint16x8", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo8ToInt16Int8x16", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "ExtendLo8ToInt32Int8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo8ToInt64Int8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo8ToUint16Uint8x16", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "ExtendLo8ToUint32Uint8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendLo8ToUint64Uint8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendToInt16Int8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendToInt16Int8x32", argLength: 1}, // ARCH:amd64 + {name: "ExtendToInt32Int8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendToInt32Int16x8", argLength: 1}, // ARCH:amd64 + {name: "ExtendToInt32Int16x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendToInt64Int16x8", argLength: 1}, // ARCH:amd64 + {name: "ExtendToInt64Int32x4", argLength: 1}, // ARCH:amd64 + {name: "ExtendToInt64Int32x8", argLength: 1}, // ARCH:amd64 + {name: "ExtendToUint16Uint8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendToUint16Uint8x32", argLength: 1}, // ARCH:amd64 + {name: "ExtendToUint32Uint8x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendToUint32Uint16x8", argLength: 1}, // ARCH:amd64 + {name: "ExtendToUint32Uint16x16", argLength: 1}, // ARCH:amd64 + {name: "ExtendToUint64Uint16x8", argLength: 1}, // ARCH:amd64 + {name: "ExtendToUint64Uint32x4", argLength: 1}, // ARCH:amd64 + {name: "ExtendToUint64Uint32x8", argLength: 1}, // ARCH:amd64 + {name: "FloorFloat32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "FloorFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "FloorFloat64x2", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "FloorFloat64x4", argLength: 1}, // ARCH:amd64 + {name: "GaloisFieldMulUint8x16", argLength: 2}, // ARCH:amd64 + {name: "GaloisFieldMulUint8x32", argLength: 2}, // ARCH:amd64 + {name: "GaloisFieldMulUint8x64", argLength: 2}, // ARCH:amd64 + {name: "GetHiFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "GetHiFloat32x16", argLength: 1}, // ARCH:amd64 + {name: "GetHiFloat64x4", argLength: 1}, // ARCH:amd64 + {name: "GetHiFloat64x8", argLength: 1}, // ARCH:amd64 + {name: "GetHiInt8x32", argLength: 1}, // ARCH:amd64 + {name: "GetHiInt8x64", argLength: 1}, // ARCH:amd64 + {name: "GetHiInt16x16", argLength: 1}, // ARCH:amd64 + {name: "GetHiInt16x32", argLength: 1}, // ARCH:amd64 + {name: "GetHiInt32x8", argLength: 1}, // ARCH:amd64 + {name: "GetHiInt32x16", argLength: 1}, // ARCH:amd64 + {name: "GetHiInt64x4", argLength: 1}, // ARCH:amd64 + {name: "GetHiInt64x8", argLength: 1}, // ARCH:amd64 + {name: "GetHiUint8x32", argLength: 1}, // ARCH:amd64 + {name: "GetHiUint8x64", argLength: 1}, // ARCH:amd64 + {name: "GetHiUint16x16", argLength: 1}, // ARCH:amd64 + {name: "GetHiUint16x32", argLength: 1}, // ARCH:amd64 + {name: "GetHiUint32x8", argLength: 1}, // ARCH:amd64 + {name: "GetHiUint32x16", argLength: 1}, // ARCH:amd64 + {name: "GetHiUint64x4", argLength: 1}, // ARCH:amd64 + {name: "GetHiUint64x8", argLength: 1}, // ARCH:amd64 + {name: "GetLoFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "GetLoFloat32x16", argLength: 1}, // ARCH:amd64 + {name: "GetLoFloat64x4", argLength: 1}, // ARCH:amd64 + {name: "GetLoFloat64x8", argLength: 1}, // ARCH:amd64 + {name: "GetLoInt8x32", argLength: 1}, // ARCH:amd64 + {name: "GetLoInt8x64", argLength: 1}, // ARCH:amd64 + {name: "GetLoInt16x16", argLength: 1}, // ARCH:amd64 + {name: "GetLoInt16x32", argLength: 1}, // ARCH:amd64 + {name: "GetLoInt32x8", argLength: 1}, // ARCH:amd64 + {name: "GetLoInt32x16", argLength: 1}, // ARCH:amd64 + {name: "GetLoInt64x4", argLength: 1}, // ARCH:amd64 + {name: "GetLoInt64x8", argLength: 1}, // ARCH:amd64 + {name: "GetLoUint8x32", argLength: 1}, // ARCH:amd64 + {name: "GetLoUint8x64", argLength: 1}, // ARCH:amd64 + {name: "GetLoUint16x16", argLength: 1}, // ARCH:amd64 + {name: "GetLoUint16x32", argLength: 1}, // ARCH:amd64 + {name: "GetLoUint32x8", argLength: 1}, // ARCH:amd64 + {name: "GetLoUint32x16", argLength: 1}, // ARCH:amd64 + {name: "GetLoUint64x4", argLength: 1}, // ARCH:amd64 + {name: "GetLoUint64x8", argLength: 1}, // ARCH:amd64 + {name: "GreaterEqualFloat32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "GreaterEqualFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualFloat64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "GreaterEqualFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualInt8x16", argLength: 2}, // ARCH:arm64,wasm + {name: "GreaterEqualInt8x64", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualInt16x8", argLength: 2}, // ARCH:arm64,wasm + {name: "GreaterEqualInt16x32", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualInt32x4", argLength: 2}, // ARCH:arm64,wasm + {name: "GreaterEqualInt32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualInt64x2", argLength: 2}, // ARCH:arm64,wasm + {name: "GreaterEqualInt64x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualUint8x16", argLength: 2}, // ARCH:arm64,wasm + {name: "GreaterEqualUint8x64", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualUint16x8", argLength: 2}, // ARCH:arm64,wasm + {name: "GreaterEqualUint16x32", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualUint32x4", argLength: 2}, // ARCH:arm64,wasm + {name: "GreaterEqualUint32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualUint64x2", argLength: 2}, // ARCH:arm64 + {name: "GreaterEqualUint64x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterFloat32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "GreaterFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterFloat64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "GreaterFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "GreaterFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterInt8x16", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "GreaterInt8x32", argLength: 2}, // ARCH:amd64 + {name: "GreaterInt8x64", argLength: 2}, // ARCH:amd64 + {name: "GreaterInt16x8", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "GreaterInt16x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterInt16x32", argLength: 2}, // ARCH:amd64 + {name: "GreaterInt32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "GreaterInt32x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterInt32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterInt64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "GreaterInt64x4", argLength: 2}, // ARCH:amd64 + {name: "GreaterInt64x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterUint8x16", argLength: 2}, // ARCH:arm64,wasm + {name: "GreaterUint8x64", argLength: 2}, // ARCH:amd64 + {name: "GreaterUint16x8", argLength: 2}, // ARCH:arm64,wasm + {name: "GreaterUint16x32", argLength: 2}, // ARCH:amd64 + {name: "GreaterUint32x4", argLength: 2}, // ARCH:arm64,wasm + {name: "GreaterUint32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterUint64x2", argLength: 2}, // ARCH:arm64 + {name: "GreaterUint64x8", argLength: 2}, // ARCH:amd64 + {name: "InterleaveEvenInt8x16", argLength: 2}, // ARCH:arm64 + {name: "InterleaveEvenInt16x8", argLength: 2}, // ARCH:arm64 + {name: "InterleaveEvenInt32x4", argLength: 2}, // ARCH:arm64 + {name: "InterleaveEvenInt64x2", argLength: 2}, // ARCH:arm64 + {name: "InterleaveEvenUint8x16", argLength: 2}, // ARCH:arm64 + {name: "InterleaveEvenUint16x8", argLength: 2}, // ARCH:arm64 + {name: "InterleaveEvenUint32x4", argLength: 2}, // ARCH:arm64 + {name: "InterleaveEvenUint64x2", argLength: 2}, // ARCH:arm64 + {name: "InterleaveHiGroupedInt16x16", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedInt16x32", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedInt32x8", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedInt32x16", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedInt64x4", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedInt64x8", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedUint16x16", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedUint16x32", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedUint32x8", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedUint32x16", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedUint64x4", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiGroupedUint64x8", argLength: 2}, // ARCH:amd64 + {name: "InterleaveHiInt8x16", argLength: 2}, // ARCH:arm64 + {name: "InterleaveHiInt16x8", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveHiInt32x4", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveHiInt64x2", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveHiUint8x16", argLength: 2}, // ARCH:arm64 + {name: "InterleaveHiUint16x8", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveHiUint32x4", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveHiUint64x2", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveLoGroupedInt16x16", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedInt16x32", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedInt32x8", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedInt32x16", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedInt64x4", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedInt64x8", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedUint16x16", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedUint16x32", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedUint32x8", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedUint32x16", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedUint64x4", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoGroupedUint64x8", argLength: 2}, // ARCH:amd64 + {name: "InterleaveLoInt8x16", argLength: 2}, // ARCH:arm64 + {name: "InterleaveLoInt16x8", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveLoInt32x4", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveLoInt64x2", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveLoUint8x16", argLength: 2}, // ARCH:arm64 + {name: "InterleaveLoUint16x8", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveLoUint32x4", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveLoUint64x2", argLength: 2}, // ARCH:amd64,arm64 + {name: "InterleaveOddInt8x16", argLength: 2}, // ARCH:arm64 + {name: "InterleaveOddInt16x8", argLength: 2}, // ARCH:arm64 + {name: "InterleaveOddInt32x4", argLength: 2}, // ARCH:arm64 + {name: "InterleaveOddInt64x2", argLength: 2}, // ARCH:arm64 + {name: "InterleaveOddUint8x16", argLength: 2}, // ARCH:arm64 + {name: "InterleaveOddUint16x8", argLength: 2}, // ARCH:arm64 + {name: "InterleaveOddUint32x4", argLength: 2}, // ARCH:arm64 + {name: "InterleaveOddUint64x2", argLength: 2}, // ARCH:arm64 + {name: "LeadingSignBitsInt8x16", argLength: 1}, // ARCH:arm64 + {name: "LeadingSignBitsInt16x8", argLength: 1}, // ARCH:arm64 + {name: "LeadingSignBitsInt32x4", argLength: 1}, // ARCH:arm64 + {name: "LeadingSignBitsUint8x16", argLength: 1}, // ARCH:arm64 + {name: "LeadingSignBitsUint16x8", argLength: 1}, // ARCH:arm64 + {name: "LeadingSignBitsUint32x4", argLength: 1}, // ARCH:arm64 + {name: "LeadingZerosInt8x16", argLength: 1}, // ARCH:arm64 + {name: "LeadingZerosInt16x8", argLength: 1}, // ARCH:arm64 + {name: "LeadingZerosInt32x4", argLength: 1}, // ARCH:amd64,arm64 + {name: "LeadingZerosInt32x8", argLength: 1}, // ARCH:amd64 + {name: "LeadingZerosInt32x16", argLength: 1}, // ARCH:amd64 + {name: "LeadingZerosInt64x2", argLength: 1}, // ARCH:amd64 + {name: "LeadingZerosInt64x4", argLength: 1}, // ARCH:amd64 + {name: "LeadingZerosInt64x8", argLength: 1}, // ARCH:amd64 + {name: "LeadingZerosUint8x16", argLength: 1}, // ARCH:arm64 + {name: "LeadingZerosUint16x8", argLength: 1}, // ARCH:arm64 + {name: "LeadingZerosUint32x4", argLength: 1}, // ARCH:amd64,arm64 + {name: "LeadingZerosUint32x8", argLength: 1}, // ARCH:amd64 + {name: "LeadingZerosUint32x16", argLength: 1}, // ARCH:amd64 + {name: "LeadingZerosUint64x2", argLength: 1}, // ARCH:amd64 + {name: "LeadingZerosUint64x4", argLength: 1}, // ARCH:amd64 + {name: "LeadingZerosUint64x8", argLength: 1}, // ARCH:amd64 + {name: "LessEqualFloat32x4", argLength: 2}, // ARCH:amd64,wasm + {name: "LessEqualFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "LessEqualFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "LessEqualFloat64x2", argLength: 2}, // ARCH:amd64,wasm + {name: "LessEqualFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "LessEqualFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "LessEqualInt8x16", argLength: 2}, // ARCH:wasm + {name: "LessEqualInt8x64", argLength: 2}, // ARCH:amd64 + {name: "LessEqualInt16x8", argLength: 2}, // ARCH:wasm + {name: "LessEqualInt16x32", argLength: 2}, // ARCH:amd64 + {name: "LessEqualInt32x4", argLength: 2}, // ARCH:wasm + {name: "LessEqualInt32x16", argLength: 2}, // ARCH:amd64 + {name: "LessEqualInt64x2", argLength: 2}, // ARCH:wasm + {name: "LessEqualInt64x8", argLength: 2}, // ARCH:amd64 + {name: "LessEqualUint8x16", argLength: 2}, // ARCH:wasm + {name: "LessEqualUint8x64", argLength: 2}, // ARCH:amd64 + {name: "LessEqualUint16x8", argLength: 2}, // ARCH:wasm + {name: "LessEqualUint16x32", argLength: 2}, // ARCH:amd64 + {name: "LessEqualUint32x4", argLength: 2}, // ARCH:wasm + {name: "LessEqualUint32x16", argLength: 2}, // ARCH:amd64 + {name: "LessEqualUint64x8", argLength: 2}, // ARCH:amd64 + {name: "LessFloat32x4", argLength: 2}, // ARCH:amd64,wasm + {name: "LessFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "LessFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "LessFloat64x2", argLength: 2}, // ARCH:amd64,wasm + {name: "LessFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "LessFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "LessInt8x16", argLength: 2}, // ARCH:wasm + {name: "LessInt8x64", argLength: 2}, // ARCH:amd64 + {name: "LessInt16x8", argLength: 2}, // ARCH:wasm + {name: "LessInt16x32", argLength: 2}, // ARCH:amd64 + {name: "LessInt32x4", argLength: 2}, // ARCH:wasm + {name: "LessInt32x16", argLength: 2}, // ARCH:amd64 + {name: "LessInt64x2", argLength: 2}, // ARCH:wasm + {name: "LessInt64x8", argLength: 2}, // ARCH:amd64 + {name: "LessUint8x16", argLength: 2}, // ARCH:wasm + {name: "LessUint8x64", argLength: 2}, // ARCH:amd64 + {name: "LessUint16x8", argLength: 2}, // ARCH:wasm + {name: "LessUint16x32", argLength: 2}, // ARCH:amd64 + {name: "LessUint32x4", argLength: 2}, // ARCH:wasm + {name: "LessUint32x16", argLength: 2}, // ARCH:amd64 + {name: "LessUint64x8", argLength: 2}, // ARCH:amd64 + {name: "LookupOrZeroInt8x16", argLength: 2}, // ARCH:arm64,wasm + {name: "LookupOrZeroUint8x16", argLength: 2}, // ARCH:arm64 + {name: "MaxFloat32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MaxFloat32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxFloat32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxFloat64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MaxFloat64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxFloat64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MaxInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MaxInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MaxInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxInt64x2", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MaxUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MaxUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MaxUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxUint64x2", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MaxUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinFloat32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MinFloat32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinFloat32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinFloat64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MinFloat64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinFloat64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MinInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MinInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MinInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinInt64x2", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MinUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MinUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MinUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinUint64x2", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MinUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulAddEvenSubOddFloat32x4", argLength: 3}, // ARCH:amd64 + {name: "MulAddEvenSubOddFloat32x8", argLength: 3}, // ARCH:amd64 + {name: "MulAddEvenSubOddFloat32x16", argLength: 3}, // ARCH:amd64 + {name: "MulAddEvenSubOddFloat64x2", argLength: 3}, // ARCH:amd64 + {name: "MulAddEvenSubOddFloat64x4", argLength: 3}, // ARCH:amd64 + {name: "MulAddEvenSubOddFloat64x8", argLength: 3}, // ARCH:amd64 + {name: "MulAddFloat32x4", argLength: 3}, // ARCH:amd64,arm64 + {name: "MulAddFloat32x8", argLength: 3}, // ARCH:amd64 + {name: "MulAddFloat32x16", argLength: 3}, // ARCH:amd64 + {name: "MulAddFloat64x2", argLength: 3}, // ARCH:amd64,arm64 + {name: "MulAddFloat64x4", argLength: 3}, // ARCH:amd64 + {name: "MulAddFloat64x8", argLength: 3}, // ARCH:amd64 + {name: "MulAddInt8x16", argLength: 3}, // ARCH:arm64 + {name: "MulAddInt16x8", argLength: 3}, // ARCH:arm64 + {name: "MulAddInt32x4", argLength: 3}, // ARCH:arm64 + {name: "MulAddOddSubEvenFloat32x4", argLength: 3}, // ARCH:amd64 + {name: "MulAddOddSubEvenFloat32x8", argLength: 3}, // ARCH:amd64 + {name: "MulAddOddSubEvenFloat32x16", argLength: 3}, // ARCH:amd64 + {name: "MulAddOddSubEvenFloat64x2", argLength: 3}, // ARCH:amd64 + {name: "MulAddOddSubEvenFloat64x4", argLength: 3}, // ARCH:amd64 + {name: "MulAddOddSubEvenFloat64x8", argLength: 3}, // ARCH:amd64 + {name: "MulAddUint8x16", argLength: 3}, // ARCH:arm64 + {name: "MulAddUint16x8", argLength: 3}, // ARCH:arm64 + {name: "MulAddUint32x4", argLength: 3}, // ARCH:arm64 + {name: "MulFloat32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MulFloat32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulFloat32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulFloat64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MulFloat64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulFloat64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulHighInt16x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulHighInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulHighInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulHighUint16x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulHighUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulHighUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulInt8x16", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "MulInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MulInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MulInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulInt64x2", argLength: 2, commutative: true}, // ARCH:amd64,wasm + {name: "MulInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulSignInt8x16", argLength: 2}, // ARCH:amd64 + {name: "MulSignInt8x32", argLength: 2}, // ARCH:amd64 + {name: "MulSignInt16x8", argLength: 2}, // ARCH:amd64 + {name: "MulSignInt16x16", argLength: 2}, // ARCH:amd64 + {name: "MulSignInt32x4", argLength: 2}, // ARCH:amd64 + {name: "MulSignInt32x8", argLength: 2}, // ARCH:amd64 + {name: "MulUint8x16", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "MulUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MulUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "MulUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,wasm + {name: "MulUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulWidenEvenInt32x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulWidenEvenInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulWidenEvenUint32x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulWidenEvenUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "MulWidenHiInt8x16", argLength: 2, commutative: true}, // ARCH:wasm + {name: "MulWidenHiInt16x8", argLength: 2, commutative: true}, // ARCH:wasm + {name: "MulWidenHiInt32x4", argLength: 2, commutative: true}, // ARCH:wasm + {name: "MulWidenHiUint8x16", argLength: 2, commutative: true}, // ARCH:wasm + {name: "MulWidenHiUint16x8", argLength: 2, commutative: true}, // ARCH:wasm + {name: "MulWidenHiUint32x4", argLength: 2, commutative: true}, // ARCH:wasm + {name: "MulWidenLoInt8x16", argLength: 2, commutative: true}, // ARCH:arm64,wasm + {name: "MulWidenLoInt16x8", argLength: 2, commutative: true}, // ARCH:arm64,wasm + {name: "MulWidenLoInt32x4", argLength: 2, commutative: true}, // ARCH:arm64,wasm + {name: "MulWidenLoUint8x16", argLength: 2, commutative: true}, // ARCH:arm64,wasm + {name: "MulWidenLoUint16x8", argLength: 2, commutative: true}, // ARCH:arm64,wasm + {name: "MulWidenLoUint32x4", argLength: 2, commutative: true}, // ARCH:arm64,wasm + {name: "NegFloat32x4", argLength: 1}, // ARCH:arm64,wasm + {name: "NegFloat64x2", argLength: 1}, // ARCH:arm64,wasm + {name: "NegInt8x16", argLength: 1}, // ARCH:arm64,wasm + {name: "NegInt16x8", argLength: 1}, // ARCH:arm64,wasm + {name: "NegInt32x4", argLength: 1}, // ARCH:arm64,wasm + {name: "NegInt64x2", argLength: 1}, // ARCH:arm64,wasm + {name: "NotEqualFloat32x4", argLength: 2, commutative: true}, // ARCH:amd64,wasm + {name: "NotEqualFloat32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualFloat32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualFloat64x2", argLength: 2, commutative: true}, // ARCH:amd64,wasm + {name: "NotEqualFloat64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualFloat64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualInt8x16", argLength: 2, commutative: true}, // ARCH:wasm + {name: "NotEqualInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualInt16x8", argLength: 2, commutative: true}, // ARCH:wasm + {name: "NotEqualInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualInt32x4", argLength: 2, commutative: true}, // ARCH:wasm + {name: "NotEqualInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualInt64x2", argLength: 2, commutative: true}, // ARCH:wasm + {name: "NotEqualInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualUint8x16", argLength: 2, commutative: true}, // ARCH:wasm + {name: "NotEqualUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualUint16x8", argLength: 2, commutative: true}, // ARCH:wasm + {name: "NotEqualUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualUint32x4", argLength: 2, commutative: true}, // ARCH:wasm + {name: "NotEqualUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualUint64x2", argLength: 2, commutative: true}, // ARCH:wasm + {name: "NotEqualUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotInt8x16", argLength: 1}, // ARCH:arm64,wasm + {name: "NotInt16x8", argLength: 1}, // ARCH:arm64,wasm + {name: "NotInt32x4", argLength: 1}, // ARCH:arm64,wasm + {name: "NotInt64x2", argLength: 1}, // ARCH:arm64,wasm + {name: "NotUint8x16", argLength: 1}, // ARCH:arm64,wasm + {name: "NotUint16x8", argLength: 1}, // ARCH:arm64,wasm + {name: "NotUint32x4", argLength: 1}, // ARCH:arm64,wasm + {name: "NotUint64x2", argLength: 1}, // ARCH:arm64,wasm + {name: "OnesCountInt8x16", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "OnesCountInt8x32", argLength: 1}, // ARCH:amd64 + {name: "OnesCountInt8x64", argLength: 1}, // ARCH:amd64 + {name: "OnesCountInt16x8", argLength: 1}, // ARCH:amd64 + {name: "OnesCountInt16x16", argLength: 1}, // ARCH:amd64 + {name: "OnesCountInt16x32", argLength: 1}, // ARCH:amd64 + {name: "OnesCountInt32x4", argLength: 1}, // ARCH:amd64 + {name: "OnesCountInt32x8", argLength: 1}, // ARCH:amd64 + {name: "OnesCountInt32x16", argLength: 1}, // ARCH:amd64 + {name: "OnesCountInt64x2", argLength: 1}, // ARCH:amd64 + {name: "OnesCountInt64x4", argLength: 1}, // ARCH:amd64 + {name: "OnesCountInt64x8", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint8x16", argLength: 1}, // ARCH:amd64,arm64 + {name: "OnesCountUint8x32", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint8x64", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint16x8", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint16x16", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint16x32", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint32x4", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint32x8", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint32x16", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint64x2", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint64x4", argLength: 1}, // ARCH:amd64 + {name: "OnesCountUint64x8", argLength: 1}, // ARCH:amd64 + {name: "OrInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "OrInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "OrInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "OrInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrInt64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "OrInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrNotInt8x16", argLength: 2}, // ARCH:arm64 + {name: "OrNotInt16x8", argLength: 2}, // ARCH:arm64 + {name: "OrNotInt32x4", argLength: 2}, // ARCH:arm64 + {name: "OrNotInt64x2", argLength: 2}, // ARCH:arm64 + {name: "OrNotUint8x16", argLength: 2}, // ARCH:arm64 + {name: "OrNotUint16x8", argLength: 2}, // ARCH:arm64 + {name: "OrNotUint32x4", argLength: 2}, // ARCH:arm64 + {name: "OrNotUint64x2", argLength: 2}, // ARCH:arm64 + {name: "OrUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "OrUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "OrUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "OrUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "OrUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "PermuteFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "PermuteFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "PermuteFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "PermuteFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "PermuteInt8x16", argLength: 2}, // ARCH:amd64 + {name: "PermuteInt8x32", argLength: 2}, // ARCH:amd64 + {name: "PermuteInt8x64", argLength: 2}, // ARCH:amd64 + {name: "PermuteInt16x8", argLength: 2}, // ARCH:amd64 + {name: "PermuteInt16x16", argLength: 2}, // ARCH:amd64 + {name: "PermuteInt16x32", argLength: 2}, // ARCH:amd64 + {name: "PermuteInt32x8", argLength: 2}, // ARCH:amd64 + {name: "PermuteInt32x16", argLength: 2}, // ARCH:amd64 + {name: "PermuteInt64x4", argLength: 2}, // ARCH:amd64 + {name: "PermuteInt64x8", argLength: 2}, // ARCH:amd64 + {name: "PermuteOrZeroGroupedInt8x32", argLength: 2}, // ARCH:amd64 + {name: "PermuteOrZeroGroupedInt8x64", argLength: 2}, // ARCH:amd64 + {name: "PermuteOrZeroGroupedUint8x32", argLength: 2}, // ARCH:amd64 + {name: "PermuteOrZeroGroupedUint8x64", argLength: 2}, // ARCH:amd64 + {name: "PermuteOrZeroInt8x16", argLength: 2}, // ARCH:amd64 + {name: "PermuteOrZeroUint8x16", argLength: 2}, // ARCH:amd64 + {name: "PermuteUint8x16", argLength: 2}, // ARCH:amd64 + {name: "PermuteUint8x32", argLength: 2}, // ARCH:amd64 + {name: "PermuteUint8x64", argLength: 2}, // ARCH:amd64 + {name: "PermuteUint16x8", argLength: 2}, // ARCH:amd64 + {name: "PermuteUint16x16", argLength: 2}, // ARCH:amd64 + {name: "PermuteUint16x32", argLength: 2}, // ARCH:amd64 + {name: "PermuteUint32x8", argLength: 2}, // ARCH:amd64 + {name: "PermuteUint32x16", argLength: 2}, // ARCH:amd64 + {name: "PermuteUint64x4", argLength: 2}, // ARCH:amd64 + {name: "PermuteUint64x8", argLength: 2}, // ARCH:amd64 + {name: "ReciprocalFloat32x4", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalFloat32x16", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalFloat64x2", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalFloat64x4", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalFloat64x8", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalSqrtFloat32x4", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalSqrtFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalSqrtFloat32x16", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalSqrtFloat64x2", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalSqrtFloat64x4", argLength: 1}, // ARCH:amd64 + {name: "ReciprocalSqrtFloat64x8", argLength: 1}, // ARCH:amd64 + {name: "RotateAllLeftVarInt8x16", argLength: 2}, // ARCH:wasm + {name: "RotateAllLeftVarInt16x8", argLength: 2}, // ARCH:wasm + {name: "RotateAllLeftVarInt32x4", argLength: 2}, // ARCH:wasm + {name: "RotateAllLeftVarInt64x2", argLength: 2}, // ARCH:wasm + {name: "RotateAllLeftVarUint8x16", argLength: 2}, // ARCH:wasm + {name: "RotateAllLeftVarUint16x8", argLength: 2}, // ARCH:wasm + {name: "RotateAllLeftVarUint32x4", argLength: 2}, // ARCH:wasm + {name: "RotateAllLeftVarUint64x2", argLength: 2}, // ARCH:wasm + {name: "RotateAllRightVarInt8x16", argLength: 2}, // ARCH:wasm + {name: "RotateAllRightVarInt16x8", argLength: 2}, // ARCH:wasm + {name: "RotateAllRightVarInt32x4", argLength: 2}, // ARCH:wasm + {name: "RotateAllRightVarInt64x2", argLength: 2}, // ARCH:wasm + {name: "RotateAllRightVarUint8x16", argLength: 2}, // ARCH:wasm + {name: "RotateAllRightVarUint16x8", argLength: 2}, // ARCH:wasm + {name: "RotateAllRightVarUint32x4", argLength: 2}, // ARCH:wasm + {name: "RotateAllRightVarUint64x2", argLength: 2}, // ARCH:wasm + {name: "RotateLeftInt32x4", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftInt32x8", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftInt32x16", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftInt64x2", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftInt64x4", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftInt64x8", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftUint32x4", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftUint32x8", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftUint32x16", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftUint64x2", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftUint64x4", argLength: 2}, // ARCH:amd64 + {name: "RotateLeftUint64x8", argLength: 2}, // ARCH:amd64 + {name: "RotateRightInt32x4", argLength: 2}, // ARCH:amd64 + {name: "RotateRightInt32x8", argLength: 2}, // ARCH:amd64 + {name: "RotateRightInt32x16", argLength: 2}, // ARCH:amd64 + {name: "RotateRightInt64x2", argLength: 2}, // ARCH:amd64 + {name: "RotateRightInt64x4", argLength: 2}, // ARCH:amd64 + {name: "RotateRightInt64x8", argLength: 2}, // ARCH:amd64 + {name: "RotateRightUint32x4", argLength: 2}, // ARCH:amd64 + {name: "RotateRightUint32x8", argLength: 2}, // ARCH:amd64 + {name: "RotateRightUint32x16", argLength: 2}, // ARCH:amd64 + {name: "RotateRightUint64x2", argLength: 2}, // ARCH:amd64 + {name: "RotateRightUint64x4", argLength: 2}, // ARCH:amd64 + {name: "RotateRightUint64x8", argLength: 2}, // ARCH:amd64 + {name: "RoundFloat32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "RoundFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "RoundFloat64x2", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "RoundFloat64x4", argLength: 1}, // ARCH:amd64 + {name: "SHA1Message1Uint32x4", argLength: 2}, // ARCH:amd64 + {name: "SHA1Message2Uint32x4", argLength: 2}, // ARCH:amd64 + {name: "SHA1NextEUint32x4", argLength: 2}, // ARCH:amd64 + {name: "SHA256Message1Uint32x4", argLength: 2}, // ARCH:amd64 + {name: "SHA256Message2Uint32x4", argLength: 2}, // ARCH:amd64 + {name: "SHA256TwoRoundsUint32x4", argLength: 3}, // ARCH:amd64 + {name: "SaturateToInt8Int16x8", argLength: 1}, // ARCH:amd64,arm64 + {name: "SaturateToInt8Int16x16", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt8Int16x32", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt8Int32x4", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt8Int32x8", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt8Int32x16", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt8Int64x2", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt8Int64x4", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt8Int64x8", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt16ConcatGroupedInt32x8", argLength: 2}, // ARCH:amd64 + {name: "SaturateToInt16ConcatGroupedInt32x16", argLength: 2}, // ARCH:amd64 + {name: "SaturateToInt16ConcatInt32x4", argLength: 2}, // ARCH:amd64 + {name: "SaturateToInt16Int32x4", argLength: 1}, // ARCH:amd64,arm64 + {name: "SaturateToInt16Int32x8", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt16Int32x16", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt16Int64x2", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt16Int64x4", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt16Int64x8", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt32Int64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "SaturateToInt32Int64x4", argLength: 1}, // ARCH:amd64 + {name: "SaturateToInt32Int64x8", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint8Int16x8", argLength: 1}, // ARCH:arm64 + {name: "SaturateToUint8Uint16x8", argLength: 1}, // ARCH:amd64,arm64 + {name: "SaturateToUint8Uint16x16", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint8Uint16x32", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint8Uint32x4", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint8Uint32x8", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint8Uint32x16", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint8Uint64x2", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint8Uint64x4", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint8Uint64x8", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint16ConcatGroupedInt32x8", argLength: 2}, // ARCH:amd64 + {name: "SaturateToUint16ConcatGroupedInt32x16", argLength: 2}, // ARCH:amd64 + {name: "SaturateToUint16ConcatInt32x4", argLength: 2}, // ARCH:amd64 + {name: "SaturateToUint16Int32x4", argLength: 1}, // ARCH:arm64 + {name: "SaturateToUint16Uint32x4", argLength: 1}, // ARCH:amd64,arm64 + {name: "SaturateToUint16Uint32x8", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint16Uint32x16", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint16Uint64x2", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint16Uint64x4", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint16Uint64x8", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint32Int64x2", argLength: 1}, // ARCH:arm64 + {name: "SaturateToUint32Uint64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "SaturateToUint32Uint64x4", argLength: 1}, // ARCH:amd64 + {name: "SaturateToUint32Uint64x8", argLength: 1}, // ARCH:amd64 + {name: "ScaleFloat32x4", argLength: 2}, // ARCH:amd64 + {name: "ScaleFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "ScaleFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "ScaleFloat64x2", argLength: 2}, // ARCH:amd64 + {name: "ScaleFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "ScaleFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "SetHiFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "SetHiFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "SetHiFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "SetHiFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "SetHiInt8x32", argLength: 2}, // ARCH:amd64 + {name: "SetHiInt8x64", argLength: 2}, // ARCH:amd64 + {name: "SetHiInt16x16", argLength: 2}, // ARCH:amd64 + {name: "SetHiInt16x32", argLength: 2}, // ARCH:amd64 + {name: "SetHiInt32x8", argLength: 2}, // ARCH:amd64 + {name: "SetHiInt32x16", argLength: 2}, // ARCH:amd64 + {name: "SetHiInt64x4", argLength: 2}, // ARCH:amd64 + {name: "SetHiInt64x8", argLength: 2}, // ARCH:amd64 + {name: "SetHiUint8x32", argLength: 2}, // ARCH:amd64 + {name: "SetHiUint8x64", argLength: 2}, // ARCH:amd64 + {name: "SetHiUint16x16", argLength: 2}, // ARCH:amd64 + {name: "SetHiUint16x32", argLength: 2}, // ARCH:amd64 + {name: "SetHiUint32x8", argLength: 2}, // ARCH:amd64 + {name: "SetHiUint32x16", argLength: 2}, // ARCH:amd64 + {name: "SetHiUint64x4", argLength: 2}, // ARCH:amd64 + {name: "SetHiUint64x8", argLength: 2}, // ARCH:amd64 + {name: "SetLoFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "SetLoFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "SetLoFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "SetLoFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "SetLoInt8x32", argLength: 2}, // ARCH:amd64 + {name: "SetLoInt8x64", argLength: 2}, // ARCH:amd64 + {name: "SetLoInt16x16", argLength: 2}, // ARCH:amd64 + {name: "SetLoInt16x32", argLength: 2}, // ARCH:amd64 + {name: "SetLoInt32x8", argLength: 2}, // ARCH:amd64 + {name: "SetLoInt32x16", argLength: 2}, // ARCH:amd64 + {name: "SetLoInt64x4", argLength: 2}, // ARCH:amd64 + {name: "SetLoInt64x8", argLength: 2}, // ARCH:amd64 + {name: "SetLoUint8x32", argLength: 2}, // ARCH:amd64 + {name: "SetLoUint8x64", argLength: 2}, // ARCH:amd64 + {name: "SetLoUint16x16", argLength: 2}, // ARCH:amd64 + {name: "SetLoUint16x32", argLength: 2}, // ARCH:amd64 + {name: "SetLoUint32x8", argLength: 2}, // ARCH:amd64 + {name: "SetLoUint32x16", argLength: 2}, // ARCH:amd64 + {name: "SetLoUint64x4", argLength: 2}, // ARCH:amd64 + {name: "SetLoUint64x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftInt8x16", argLength: 2}, // ARCH:arm64,wasm + {name: "ShiftAllLeftInt16x8", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllLeftInt16x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftInt16x32", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftInt32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllLeftInt32x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftInt32x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftInt64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllLeftInt64x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftInt64x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftUint8x16", argLength: 2}, // ARCH:arm64,wasm + {name: "ShiftAllLeftUint16x8", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllLeftUint16x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftUint16x32", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftUint32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllLeftUint32x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftUint32x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftUint64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllLeftUint64x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllLeftUint64x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightInt8x16", argLength: 2}, // ARCH:arm64,wasm + {name: "ShiftAllRightInt16x8", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllRightInt16x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightInt16x32", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightInt32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllRightInt32x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightInt32x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightInt64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllRightInt64x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightInt64x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightUint8x16", argLength: 2}, // ARCH:arm64,wasm + {name: "ShiftAllRightUint16x8", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllRightUint16x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightUint16x32", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightUint32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllRightUint32x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightUint32x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightUint64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllRightUint64x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftAllRightUint64x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftInt8x16", argLength: 2}, // ARCH:arm64 + {name: "ShiftInt16x8", argLength: 2}, // ARCH:arm64 + {name: "ShiftInt32x4", argLength: 2}, // ARCH:arm64 + {name: "ShiftInt64x2", argLength: 2}, // ARCH:arm64 + {name: "ShiftLeftConcatMod16Int16x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod16Int16x16", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod16Int16x32", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod16Uint16x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod16Uint16x16", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod16Uint16x32", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod32Int32x4", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod32Int32x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod32Int32x16", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod32Uint32x4", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod32Uint32x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod32Uint32x16", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod64Int64x2", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod64Int64x4", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod64Int64x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod64Uint64x2", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod64Uint64x4", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftConcatMod64Uint64x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftLeftInt16x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftInt16x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftInt16x32", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftInt32x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftInt32x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftInt32x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftInt64x2", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftInt64x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftInt64x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftUint16x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftUint16x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftUint16x32", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftUint32x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftUint32x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftUint32x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftUint64x2", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftUint64x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftLeftUint64x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightConcatMod16Int16x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod16Int16x16", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod16Int16x32", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod16Uint16x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod16Uint16x16", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod16Uint16x32", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod32Int32x4", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod32Int32x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod32Int32x16", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod32Uint32x4", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod32Uint32x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod32Uint32x16", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod64Int64x2", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod64Int64x4", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod64Int64x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod64Uint64x2", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod64Uint64x4", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightConcatMod64Uint64x8", argLength: 3}, // ARCH:amd64 + {name: "ShiftRightInt16x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightInt16x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightInt16x32", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightInt32x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightInt32x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightInt32x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightInt64x2", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightInt64x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightInt64x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightUint16x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightUint16x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightUint16x32", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightUint32x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightUint32x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightUint32x16", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightUint64x2", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightUint64x4", argLength: 2}, // ARCH:amd64 + {name: "ShiftRightUint64x8", argLength: 2}, // ARCH:amd64 + {name: "ShiftSaturatedInt8x16", argLength: 2}, // ARCH:arm64 + {name: "ShiftSaturatedInt16x8", argLength: 2}, // ARCH:arm64 + {name: "ShiftSaturatedInt32x4", argLength: 2}, // ARCH:arm64 + {name: "ShiftSaturatedInt64x2", argLength: 2}, // ARCH:arm64 + {name: "ShiftSaturatedUint8x16", argLength: 2}, // ARCH:arm64 + {name: "ShiftSaturatedUint16x8", argLength: 2}, // ARCH:arm64 + {name: "ShiftSaturatedUint32x4", argLength: 2}, // ARCH:arm64 + {name: "ShiftSaturatedUint64x2", argLength: 2}, // ARCH:arm64 + {name: "ShiftUint8x16", argLength: 2}, // ARCH:arm64 + {name: "ShiftUint16x8", argLength: 2}, // ARCH:arm64 + {name: "ShiftUint32x4", argLength: 2}, // ARCH:arm64 + {name: "ShiftUint64x2", argLength: 2}, // ARCH:arm64 + {name: "SqrtFloat32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "SqrtFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "SqrtFloat32x16", argLength: 1}, // ARCH:amd64 + {name: "SqrtFloat64x2", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "SqrtFloat64x4", argLength: 1}, // ARCH:amd64 + {name: "SqrtFloat64x8", argLength: 1}, // ARCH:amd64 + {name: "SubFloat32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "SubFloat32x8", argLength: 2}, // ARCH:amd64 + {name: "SubFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "SubFloat64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "SubFloat64x4", argLength: 2}, // ARCH:amd64 + {name: "SubFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "SubInt8x16", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "SubInt8x32", argLength: 2}, // ARCH:amd64 + {name: "SubInt8x64", argLength: 2}, // ARCH:amd64 + {name: "SubInt16x8", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "SubInt16x16", argLength: 2}, // ARCH:amd64 + {name: "SubInt16x32", argLength: 2}, // ARCH:amd64 + {name: "SubInt32x4", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "SubInt32x8", argLength: 2}, // ARCH:amd64 + {name: "SubInt32x16", argLength: 2}, // ARCH:amd64 + {name: "SubInt64x2", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "SubInt64x4", argLength: 2}, // ARCH:amd64 + {name: "SubInt64x8", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedInt8x16", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "SubSaturatedInt8x32", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedInt8x64", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedInt16x8", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "SubSaturatedInt16x16", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedInt16x32", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedInt32x4", argLength: 2}, // ARCH:arm64 + {name: "SubSaturatedInt64x2", argLength: 2}, // ARCH:arm64 + {name: "SubSaturatedUint8x16", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "SubSaturatedUint8x32", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedUint8x64", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedUint16x8", argLength: 2}, // ARCH:amd64,arm64,wasm + {name: "SubSaturatedUint16x16", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedUint16x32", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedUint32x4", argLength: 2}, // ARCH:arm64 + {name: "SubSaturatedUint64x2", argLength: 2}, // ARCH:arm64 + {name: "SubUint8x16", argLength: 2}, // ARCH:amd64,arm64 + {name: "SubUint8x32", argLength: 2}, // ARCH:amd64 + {name: "SubUint8x64", argLength: 2}, // ARCH:amd64 + {name: "SubUint16x8", argLength: 2}, // ARCH:amd64,arm64 + {name: "SubUint16x16", argLength: 2}, // ARCH:amd64 + {name: "SubUint16x32", argLength: 2}, // ARCH:amd64 + {name: "SubUint32x4", argLength: 2}, // ARCH:amd64,arm64 + {name: "SubUint32x8", argLength: 2}, // ARCH:amd64 + {name: "SubUint32x16", argLength: 2}, // ARCH:amd64 + {name: "SubUint64x2", argLength: 2}, // ARCH:amd64,arm64 + {name: "SubUint64x4", argLength: 2}, // ARCH:amd64 + {name: "SubUint64x8", argLength: 2}, // ARCH:amd64 + {name: "SumOf8AbsDiffUint8x16", argLength: 2}, // ARCH:amd64 + {name: "SumOf8AbsDiffUint8x32", argLength: 2}, // ARCH:amd64 + {name: "SumOf8AbsDiffUint8x64", argLength: 2}, // ARCH:amd64 + {name: "TruncFloat32x4", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "TruncFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "TruncFloat64x2", argLength: 1}, // ARCH:amd64,arm64,wasm + {name: "TruncFloat64x4", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt8Int16x8", argLength: 1}, // ARCH:amd64,arm64 + {name: "TruncToInt8Int16x16", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt8Int16x32", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt8Int32x4", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt8Int32x8", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt8Int32x16", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt8Int64x2", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt8Int64x4", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt8Int64x8", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt16Int32x4", argLength: 1}, // ARCH:amd64,arm64 + {name: "TruncToInt16Int32x8", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt16Int32x16", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt16Int64x2", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt16Int64x4", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt16Int64x8", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt32Int64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "TruncToInt32Int64x4", argLength: 1}, // ARCH:amd64 + {name: "TruncToInt32Int64x8", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint8Uint16x8", argLength: 1}, // ARCH:amd64,arm64 + {name: "TruncToUint8Uint16x16", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint8Uint16x32", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint8Uint32x4", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint8Uint32x8", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint8Uint32x16", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint8Uint64x2", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint8Uint64x4", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint8Uint64x8", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint16Uint32x4", argLength: 1}, // ARCH:amd64,arm64 + {name: "TruncToUint16Uint32x8", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint16Uint32x16", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint16Uint64x2", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint16Uint64x4", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint16Uint64x8", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint32Uint64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "TruncToUint32Uint64x4", argLength: 1}, // ARCH:amd64 + {name: "TruncToUint32Uint64x8", argLength: 1}, // ARCH:amd64 + {name: "XorInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "XorInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "XorInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "XorInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorInt64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "XorInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "XorUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "XorUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "XorUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm + {name: "XorUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "bitSelectInt8x16", argLength: 3}, // ARCH:arm64 + {name: "bitSelectNotInt8x16", argLength: 3}, // ARCH:arm64 + {name: "blendInt8x16", argLength: 3}, // ARCH:amd64 + {name: "blendInt8x32", argLength: 3}, // ARCH:amd64 + {name: "blendMaskedInt8x64", argLength: 3}, // ARCH:amd64 + {name: "blendMaskedInt16x32", argLength: 3}, // ARCH:amd64 + {name: "blendMaskedInt32x16", argLength: 3}, // ARCH:amd64 + {name: "blendMaskedInt64x8", argLength: 3}, // ARCH:amd64 + {name: "broadcast1To2Float64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "broadcast1To2Int64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "broadcast1To2MaskedFloat64x2", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To2MaskedInt64x2", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To2MaskedUint64x2", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To2Uint64x2", argLength: 1}, // ARCH:amd64,arm64 + {name: "broadcast1To4Float32x4", argLength: 1}, // ARCH:amd64,arm64 + {name: "broadcast1To4Float64x2", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To4Int32x4", argLength: 1}, // ARCH:amd64,arm64 + {name: "broadcast1To4Int64x2", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To4MaskedFloat32x4", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To4MaskedFloat64x2", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To4MaskedInt32x4", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To4MaskedInt64x2", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To4MaskedUint32x4", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To4MaskedUint64x2", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To4Uint32x4", argLength: 1}, // ARCH:amd64,arm64 + {name: "broadcast1To4Uint64x2", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To8Float32x4", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To8Float64x2", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To8Int16x8", argLength: 1}, // ARCH:amd64,arm64 + {name: "broadcast1To8Int32x4", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To8Int64x2", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To8MaskedFloat32x4", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To8MaskedFloat64x2", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To8MaskedInt16x8", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To8MaskedInt32x4", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To8MaskedInt64x2", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To8MaskedUint16x8", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To8MaskedUint32x4", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To8MaskedUint64x2", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To8Uint16x8", argLength: 1}, // ARCH:amd64,arm64 + {name: "broadcast1To8Uint32x4", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To8Uint64x2", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To16Float32x4", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To16Int8x16", argLength: 1}, // ARCH:amd64,arm64 + {name: "broadcast1To16Int16x8", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To16Int32x4", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To16MaskedFloat32x4", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To16MaskedInt8x16", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To16MaskedInt16x8", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To16MaskedInt32x4", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To16MaskedUint8x16", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To16MaskedUint16x8", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To16MaskedUint32x4", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To16Uint8x16", argLength: 1}, // ARCH:amd64,arm64 + {name: "broadcast1To16Uint16x8", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To16Uint32x4", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To32Int8x16", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To32Int16x8", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To32MaskedInt8x16", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To32MaskedInt16x8", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To32MaskedUint8x16", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To32MaskedUint16x8", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To32Uint8x16", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To32Uint16x8", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To64Int8x16", argLength: 1}, // ARCH:amd64 + {name: "broadcast1To64MaskedInt8x16", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To64MaskedUint8x16", argLength: 2}, // ARCH:amd64 + {name: "broadcast1To64Uint8x16", argLength: 1}, // ARCH:amd64 + {name: "carrylessMultiplyWidenLoUint64x2", argLength: 2, commutative: true}, // ARCH:arm64 + {name: "reduceMaxFloat32x4", argLength: 1}, // ARCH:arm64 + {name: "reduceMaxInt8x16", argLength: 1}, // ARCH:arm64 + {name: "reduceMaxInt16x8", argLength: 1}, // ARCH:arm64 + {name: "reduceMaxInt32x4", argLength: 1}, // ARCH:arm64 + {name: "reduceMaxUint8x16", argLength: 1}, // ARCH:arm64 + {name: "reduceMaxUint16x8", argLength: 1}, // ARCH:arm64 + {name: "reduceMaxUint32x4", argLength: 1}, // ARCH:arm64 + {name: "reduceMinFloat32x4", argLength: 1}, // ARCH:arm64 + {name: "reduceMinInt8x16", argLength: 1}, // ARCH:arm64 + {name: "reduceMinInt16x8", argLength: 1}, // ARCH:arm64 + {name: "reduceMinInt32x4", argLength: 1}, // ARCH:arm64 + {name: "reduceMinUint8x16", argLength: 1}, // ARCH:arm64 + {name: "reduceMinUint16x8", argLength: 1}, // ARCH:arm64 + {name: "reduceMinUint32x4", argLength: 1}, // ARCH:arm64 + {name: "reduceSumInt8x16", argLength: 1}, // ARCH:arm64 + {name: "reduceSumInt16x8", argLength: 1}, // ARCH:arm64 + {name: "reduceSumInt32x4", argLength: 1}, // ARCH:arm64 + {name: "reduceSumUint8x16", argLength: 1}, // ARCH:arm64 + {name: "reduceSumUint16x8", argLength: 1}, // ARCH:arm64 + {name: "reduceSumUint32x4", argLength: 1}, // ARCH:arm64 + {name: "AESRoundKeyGenAssistUint32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledResidueFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledResidueFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledResidueFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledResidueFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledResidueFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "CeilScaledResidueFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatPermute128ScalarsFloat32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatPermute128ScalarsFloat64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatPermute128ScalarsInt8x32", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatPermute128ScalarsInt16x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatPermute128ScalarsInt32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatPermute128ScalarsInt64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatPermute128ScalarsUint8x32", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatPermute128ScalarsUint16x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatPermute128ScalarsUint32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatPermute128ScalarsUint64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatShiftBytesRightGroupedUint8x32", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatShiftBytesRightGroupedUint8x64", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ConcatShiftBytesRightUint8x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64 + {name: "FloorScaledFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledResidueFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledResidueFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledResidueFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledResidueFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledResidueFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "FloorScaledResidueFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "GaloisFieldAffineTransformInverseUint8x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "GaloisFieldAffineTransformInverseUint8x32", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "GaloisFieldAffineTransformInverseUint8x64", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "GaloisFieldAffineTransformUint8x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "GaloisFieldAffineTransformUint8x32", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "GaloisFieldAffineTransformUint8x64", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "GetElemFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "GetElemFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "GetElemInt8x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "GetElemInt16x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "GetElemInt32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "GetElemInt64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "GetElemUint8x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "GetElemUint16x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "GetElemUint32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "GetElemUint64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "RoundScaledFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledResidueFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledResidueFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledResidueFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledResidueFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledResidueFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "RoundScaledResidueFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "SHA1FourRoundsUint32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "SetElemFloat32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "SetElemFloat64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "SetElemInt8x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "SetElemInt16x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "SetElemInt32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "SetElemInt64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "SetElemUint8x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "SetElemUint16x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "SetElemUint32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "SetElemUint64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64,arm64,wasm + {name: "ShiftAllLeftConcatMod16Int16x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod16Int16x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod16Int16x32", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod16Uint16x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod16Uint16x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod16Uint16x32", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod32Int32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod32Int32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod32Int32x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod32Uint32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod32Uint32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod32Uint32x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod64Int64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod64Int64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod64Int64x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod64Uint64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod64Uint64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllLeftConcatMod64Uint64x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod16Int16x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod16Int16x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod16Int16x32", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod16Uint16x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod16Uint16x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod16Uint16x32", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod32Int32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod32Int32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod32Int32x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod32Uint32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod32Uint32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod32Uint32x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod64Int64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod64Int64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod64Int64x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod64Uint64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod64Uint64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "ShiftAllRightConcatMod64Uint64x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledResidueFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledResidueFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledResidueFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledResidueFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledResidueFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "TruncScaledResidueFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "carrylessMultiplyUint64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "carrylessMultiplyUint64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "carrylessMultiplyUint64x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantFloat32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantFloat64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedFloat32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedFloat32x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedFloat64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedFloat64x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedInt32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedInt32x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedInt64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedInt64x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedUint32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedUint32x16", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedUint64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantGroupedUint64x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantInt32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantInt64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantUint32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "concatSelectedConstantUint64x2", argLength: 2, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsGroupedInt32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsGroupedInt32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsGroupedUint32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsGroupedUint32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsHiGroupedInt16x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsHiGroupedInt16x32", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsHiGroupedUint16x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsHiGroupedUint16x32", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsHiInt16x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsHiUint16x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsInt32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsLoGroupedInt16x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsLoGroupedInt16x32", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsLoGroupedUint16x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsLoGroupedUint16x32", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsLoInt16x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsLoUint16x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "permuteScalarsUint32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64 + {name: "ternInt32x4", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternInt32x8", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternInt32x16", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternInt64x2", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternInt64x4", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternInt64x8", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternUint32x4", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternUint32x8", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternUint32x16", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternUint64x2", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternUint64x4", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + {name: "ternUint64x8", argLength: 3, aux: "UInt8"}, // ARCH:amd64 + } +} diff --git a/src/cmd/compile/internal/ssa/allocators.go b/src/cmd/compile/internal/ssa/allocators.go index 10b1c582801db2..d1b8b35ba6ab7f 100644 --- a/src/cmd/compile/internal/ssa/allocators.go +++ b/src/cmd/compile/internal/ssa/allocators.go @@ -331,3 +331,55 @@ func (c *Cache) freeIDSlice(s []ID) { } c.freeLimitSlice(*(*[]limit)(unsafe.Pointer(&b))) } +func (c *Cache) allocUintSlice(n int) []uint { + var base limit + var derived uint + if unsafe.Sizeof(base)%unsafe.Sizeof(derived) != 0 { + panic("bad") + } + scale := unsafe.Sizeof(base) / unsafe.Sizeof(derived) + b := c.allocLimitSlice(int((uintptr(n) + scale - 1) / scale)) + s := unsafeheader.Slice{ + Data: unsafe.Pointer(&b[0]), + Len: n, + Cap: cap(b) * int(scale), + } + return *(*[]uint)(unsafe.Pointer(&s)) +} +func (c *Cache) freeUintSlice(s []uint) { + var base limit + var derived uint + scale := unsafe.Sizeof(base) / unsafe.Sizeof(derived) + b := unsafeheader.Slice{ + Data: unsafe.Pointer(&s[0]), + Len: int((uintptr(len(s)) + scale - 1) / scale), + Cap: int((uintptr(cap(s)) + scale - 1) / scale), + } + c.freeLimitSlice(*(*[]limit)(unsafe.Pointer(&b))) +} +func (c *Cache) allocKnownBitsEntriesSlice(n int) []knownBitsEntry { + var base limit + var derived knownBitsEntry + if unsafe.Sizeof(base)%unsafe.Sizeof(derived) != 0 { + panic("bad") + } + scale := unsafe.Sizeof(base) / unsafe.Sizeof(derived) + b := c.allocLimitSlice(int((uintptr(n) + scale - 1) / scale)) + s := unsafeheader.Slice{ + Data: unsafe.Pointer(&b[0]), + Len: n, + Cap: cap(b) * int(scale), + } + return *(*[]knownBitsEntry)(unsafe.Pointer(&s)) +} +func (c *Cache) freeKnownBitsEntriesSlice(s []knownBitsEntry) { + var base limit + var derived knownBitsEntry + scale := unsafe.Sizeof(base) / unsafe.Sizeof(derived) + b := unsafeheader.Slice{ + Data: unsafe.Pointer(&s[0]), + Len: int((uintptr(len(s)) + scale - 1) / scale), + Cap: int((uintptr(cap(s)) + scale - 1) / scale), + } + c.freeLimitSlice(*(*[]limit)(unsafe.Pointer(&b))) +} diff --git a/src/cmd/compile/internal/ssa/block.go b/src/cmd/compile/internal/ssa/block.go index 1240bfd6556a11..6564b85ec512bb 100644 --- a/src/cmd/compile/internal/ssa/block.go +++ b/src/cmd/compile/internal/ssa/block.go @@ -18,6 +18,9 @@ type Block struct { // Source position for block's control operation Pos src.XPos + // What cpu features (AVXnnn, SVEyyy) are implied to reach/execute this block? + CPUfeatures CPUfeatures + // The kind of block this is. Kind BlockKind @@ -424,9 +427,9 @@ func (b *Block) likelyBranch() bool { return true } -func (b *Block) Logf(msg string, args ...interface{}) { b.Func.Logf(msg, args...) } -func (b *Block) Log() bool { return b.Func.Log() } -func (b *Block) Fatalf(msg string, args ...interface{}) { b.Func.Fatalf(msg, args...) } +func (b *Block) Logf(msg string, args ...any) { b.Func.Logf(msg, args...) } +func (b *Block) Log() bool { return b.Func.Log() } +func (b *Block) Fatalf(msg string, args ...any) { b.Func.Fatalf(msg, args...) } type BranchPrediction int8 @@ -449,3 +452,57 @@ const ( HotPgoInitial = HotPgo | HotInitial // special case; single block loop, initial block is header block has a flow-in entry, but PGO says it is hot HotPgoInitialNotFLowIn = HotPgo | HotInitial | HotNotFlowIn // PGO says it is hot, and the loop is rotated so flow enters loop with a branch ) + +type CPUfeatures uint32 + +const ( + CPUNone CPUfeatures = 0 + CPUAll CPUfeatures = ^CPUfeatures(0) + CPUavx CPUfeatures = 1 << iota + CPUavx2 + CPUavxvnni + CPUavx512 + CPUbitalg + CPUgfni + CPUvbmi + CPUvbmi2 + CPUvpopcntdq + CPUavx512vnni + + CPUneon + CPUsve2 +) + +func (f CPUfeatures) hasFeature(x CPUfeatures) bool { + return f&x == x +} + +func (f CPUfeatures) String() string { + if f == CPUNone { + return "none" + } + if f == CPUAll { + return "all" + } + s := "" + foo := func(what string, feat CPUfeatures) { + if feat&f != 0 { + if s != "" { + s += "+" + } + s += what + } + } + foo("avx", CPUavx) + foo("avx2", CPUavx2) + foo("avx512", CPUavx512) + foo("avxvnni", CPUavxvnni) + foo("bitalg", CPUbitalg) + foo("gfni", CPUgfni) + foo("vbmi", CPUvbmi) + foo("vbmi2", CPUvbmi2) + foo("popcntdq", CPUvpopcntdq) + foo("avx512vnni", CPUavx512vnni) + + return s +} diff --git a/src/cmd/compile/internal/ssa/branchelim.go b/src/cmd/compile/internal/ssa/branchelim.go index a7d339cad064ac..8c411b541d4c81 100644 --- a/src/cmd/compile/internal/ssa/branchelim.go +++ b/src/cmd/compile/internal/ssa/branchelim.go @@ -21,10 +21,7 @@ import "cmd/internal/src" // rewrite Phis in the postdominator as CondSelects. func branchelim(f *Func) { // FIXME: add support for lowering CondSelects on more architectures - switch f.Config.arch { - case "arm64", "ppc64le", "ppc64", "amd64", "wasm", "loong64": - // implemented - default: + if !f.Config.haveCondSelect { return } @@ -73,7 +70,8 @@ func branchelim(f *Func) { } func canCondSelect(v *Value, arch string, loadAddr *sparseSet) bool { - if loadAddr.contains(v.ID) { + if loadAddr != nil && // prove calls this on some multiplies and doesn't take care of loadAddrs + loadAddr.contains(v.ID) { // The result of the soon-to-be conditional move is used to compute a load address. // We want to avoid generating a conditional move in this case // because the load address would now be data-dependent on the condition. diff --git a/src/cmd/compile/internal/ssa/cache.go b/src/cmd/compile/internal/ssa/cache.go index 0c16efcd57d6ac..59d768c34f4838 100644 --- a/src/cmd/compile/internal/ssa/cache.go +++ b/src/cmd/compile/internal/ssa/cache.go @@ -29,7 +29,7 @@ type Cache struct { ValueToProgAfter []*obj.Prog debugState debugState - Liveness interface{} // *gc.livenessFuncCache + Liveness any // *gc.livenessFuncCache // Free "headers" for use by the allocators in allocators.go. // Used to put slices in sync.Pools without allocation. diff --git a/src/cmd/compile/internal/ssa/check.go b/src/cmd/compile/internal/ssa/check.go index ef06bd91711515..9f08a88586142f 100644 --- a/src/cmd/compile/internal/ssa/check.go +++ b/src/cmd/compile/internal/ssa/check.go @@ -150,8 +150,9 @@ func checkFunc(f *Func) { case auxInt128: // AuxInt must be zero, so leave canHaveAuxInt set to false. case auxUInt8: - if v.AuxInt != int64(uint8(v.AuxInt)) { - f.Fatalf("bad uint8 AuxInt value for %v", v) + // Cast to int8 due to requirement of AuxInt, check its comment for details. + if v.AuxInt != int64(int8(v.AuxInt)) { + f.Fatalf("bad uint8 AuxInt value for %v, saw %d but need %d", v, v.AuxInt, int64(int8(v.AuxInt))) } canHaveAuxInt = true case auxFloat32: @@ -197,7 +198,7 @@ func checkFunc(f *Func) { canHaveAux = true case auxCCop: if opcodeTable[Op(v.AuxInt)].name == "OpInvalid" { - f.Fatalf("value %v has an AuxInt value that is a valid opcode", v) + f.Fatalf("value %v has an AuxInt value that is not a valid opcode", v) } canHaveAuxInt = true case auxS390XCCMask: @@ -218,8 +219,14 @@ func checkFunc(f *Func) { case auxPanicBoundsC, auxPanicBoundsCC: canHaveAux = true canHaveAuxInt = true + case auxSizeAndAlign: + if _, ok := v.Aux.(int64Aux); !ok { + f.Fatalf("value %v has Aux type %T, want int64Aux", v, v.Aux) + } + canHaveAux = true + canHaveAuxInt = true default: - f.Fatalf("unknown aux type for %s", v.Op) + f.Fatalf("unknown aux type %T for %s", opcodeTable[v.Op].auxType, v.Op) } if !canHaveAux && v.Aux != nil { f.Fatalf("value %s has an Aux value %v but shouldn't", v.LongString(), v.Aux) @@ -273,6 +280,10 @@ func checkFunc(f *Func) { } } + if (v.Op == OpStructMake || v.Op == OpArrayMake1) && v.Type.Size() == 0 { + f.Fatalf("zero-sized Make; use Empty instead %v", v) + } + if f.RegAlloc != nil && f.Config.SoftFloat && v.Type.IsFloat() { f.Fatalf("unexpected floating-point type %v", v.LongString()) } @@ -344,6 +355,47 @@ func checkFunc(f *Func) { v.Op, v.Args[1].Type.String()) } } + // Check size of args. + // This list isn't exhaustive, just the common ops. + // It also can't handle ops with args of different types, like shifts. + var argSize int64 + switch v.Op { + case OpAdd8, OpSub8, OpMul8, OpDiv8, OpDiv8u, OpMod8, OpMod8u, + OpAnd8, OpOr8, OpXor8, + OpEq8, OpNeq8, OpLess8, OpLeq8, + OpNeg8, OpCom8, + OpSignExt8to16, OpSignExt8to32, OpSignExt8to64, + OpZeroExt8to16, OpZeroExt8to32, OpZeroExt8to64: + argSize = 1 + case OpAdd16, OpSub16, OpMul16, OpDiv16, OpDiv16u, OpMod16, OpMod16u, + OpAnd16, OpOr16, OpXor16, + OpEq16, OpNeq16, OpLess16, OpLeq16, + OpNeg16, OpCom16, + OpSignExt16to32, OpSignExt16to64, + OpZeroExt16to32, OpZeroExt16to64, + OpTrunc16to8: + argSize = 2 + case OpAdd32, OpSub32, OpMul32, OpDiv32, OpDiv32u, OpMod32, OpMod32u, + OpAnd32, OpOr32, OpXor32, + OpEq32, OpNeq32, OpLess32, OpLeq32, + OpNeg32, OpCom32, + OpSignExt32to64, OpZeroExt32to64, + OpTrunc32to8, OpTrunc32to16: + argSize = 4 + case OpAdd64, OpSub64, OpMul64, OpDiv64, OpDiv64u, OpMod64, OpMod64u, + OpAnd64, OpOr64, OpXor64, + OpEq64, OpNeq64, OpLess64, OpLeq64, + OpNeg64, OpCom64, + OpTrunc64to8, OpTrunc64to16, OpTrunc64to32: + argSize = 8 + } + if argSize != 0 { + for i, arg := range v.Args { + if arg.Type.Size() != argSize { + f.Fatalf("arg %d to %s (%v) should be %d bytes in size, it is %s", i, v.Op, v, argSize, arg.Type.String()) + } + } + } // TODO: check for cycles in values } diff --git a/src/cmd/compile/internal/ssa/compile.go b/src/cmd/compile/internal/ssa/compile.go index c749ea9013d4c3..9d5d8188b86027 100644 --- a/src/cmd/compile/internal/ssa/compile.go +++ b/src/cmd/compile/internal/ssa/compile.go @@ -461,7 +461,7 @@ var passes = [...]pass{ {name: "short circuit", fn: shortcircuit}, {name: "decompose user", fn: decomposeUser, required: true}, {name: "pre-opt deadcode", fn: deadcode}, - {name: "opt", fn: opt, required: true}, // NB: some generic rules know the name of the opt pass. TODO: split required rules and optimizing rules + {name: "opt", fn: opt, required: true}, {name: "zero arg cse", fn: zcse, required: true}, // required to merge OpSB values {name: "opt deadcode", fn: deadcode, required: true}, // remove any blocks orphaned during opt {name: "generic cse", fn: cse}, @@ -469,12 +469,16 @@ var passes = [...]pass{ {name: "gcse deadcode", fn: deadcode, required: true}, // clean out after cse and phiopt {name: "nilcheckelim", fn: nilcheckelim}, {name: "prove", fn: prove}, + {name: "divisible", fn: divisible, required: true}, + {name: "divmod", fn: divmod, required: true}, + {name: "middle opt", fn: opt, required: true}, + {name: "known bits", fn: knownBits}, {name: "early fuse", fn: fuseEarly}, {name: "expand calls", fn: expandCalls, required: true}, {name: "decompose builtin", fn: postExpandCallsDecompose, required: true}, {name: "softfloat", fn: softfloat, required: true}, {name: "branchelim", fn: branchelim}, - {name: "late opt", fn: opt, required: true}, // TODO: split required rules and optimizing rules + {name: "late opt", fn: opt, required: true}, {name: "dead auto elim", fn: elimDeadAutosGeneric}, {name: "sccp", fn: sccp}, {name: "generic deadcode", fn: deadcode, required: true}, // remove dead stores, which otherwise mess up store chain @@ -485,6 +489,8 @@ var passes = [...]pass{ {name: "writebarrier", fn: writebarrier, required: true}, // expand write barrier ops {name: "insert resched checks", fn: insertLoopReschedChecks, disabled: !buildcfg.Experiment.PreemptibleLoops}, // insert resched checks in loops. + {name: "cpufeatures", fn: cpufeatures, required: buildcfg.Experiment.SIMD, disabled: !buildcfg.Experiment.SIMD}, + {name: "rewrite tern", fn: rewriteTern, required: false, disabled: !buildcfg.Experiment.SIMD}, {name: "lower", fn: lower, required: true}, {name: "addressing modes", fn: addressingModes, required: false}, {name: "late lower", fn: lateLower, required: true}, @@ -495,8 +501,11 @@ var passes = [...]pass{ {name: "tighten tuple selectors", fn: tightenTupleSelectors, required: true}, {name: "lowered deadcode", fn: deadcode, required: true}, {name: "checkLower", fn: checkLower, required: true}, + {name: "loop invariant", fn: licm}, {name: "late phielim and copyelim", fn: copyelim}, {name: "tighten", fn: tighten, required: true}, // move values closer to their uses + // TODO: fix 80102 and re-enable. + //{name: "merge conditional branches", fn: mergeConditionalBranches}, // generate conditional comparison instructions on ARM64 architecture {name: "late deadcode", fn: deadcode}, {name: "critical", fn: critical, required: true}, // remove critical edges {name: "phi tighten", fn: phiTighten}, // place rematerializable phi args near uses to reduce value lifetimes @@ -529,6 +538,12 @@ var passOrder = [...]constraint{ {"generic cse", "prove"}, // deadcode after prove to eliminate all new dead blocks. {"prove", "generic deadcode"}, + // divisible after prove to let prove analyze div and mod + {"prove", "divisible"}, + // divmod after divisible to avoid rewriting subexpressions of ones divisible will handle + {"divisible", "divmod"}, + // divmod before decompose builtin to handle 64-bit on 32-bit systems + {"divmod", "decompose builtin"}, // common-subexpression before dead-store elim, so that we recognize // when two address expressions are the same. {"generic cse", "dse"}, @@ -538,7 +553,7 @@ var passOrder = [...]constraint{ {"nilcheckelim", "generic deadcode"}, // nilcheckelim generates sequences of plain basic blocks {"nilcheckelim", "late fuse"}, - // nilcheckelim relies on opt to rewrite user nil checks + // nilcheckelim relies on the first opt to rewrite user nil checks {"opt", "nilcheckelim"}, // tighten will be most effective when as many values have been removed as possible {"generic deadcode", "tighten"}, @@ -587,6 +602,14 @@ var passOrder = [...]constraint{ {"branchelim", "late opt"}, // branchelim is an arch-independent pass. {"branchelim", "lower"}, + // lower needs cpu feature information (for SIMD) + {"cpufeatures", "lower"}, + // known bits is an arch-independent pass. + {"known bits", "lower"}, + // known bits does very little except some fancy constant folding and we need opt to clean it up. + {"known bits", "late opt"}, + // known bits does a better job once prove cleaned up some always taken and never taken branches. + {"prove", "known bits"}, } func init() { diff --git a/src/cmd/compile/internal/ssa/config.go b/src/cmd/compile/internal/ssa/config.go index 0f41bdea8bb27c..82244a2c43f24a 100644 --- a/src/cmd/compile/internal/ssa/config.go +++ b/src/cmd/compile/internal/ssa/config.go @@ -31,6 +31,7 @@ type Config struct { fpRegMask regMask // floating point register mask fp32RegMask regMask // floating point register mask fp64RegMask regMask // floating point register mask + simdRegMask regMask // simd register mask; may be same as fpRegMask specialRegMask regMask // special register mask intParamRegs []int8 // register numbers of integer param (in/out) registers floatParamRegs []int8 // register numbers of floating param (in/out) registers @@ -41,8 +42,6 @@ type Config struct { hasGReg bool // has hardware g register ctxt *obj.Link // Generic arch information optimize bool // Do optimization - useAvg bool // Use optimizations that need Avg* operations - useHmul bool // Use optimizations that need Hmul* operations SoftFloat bool // Race bool // race detector enabled BigEndian bool // @@ -50,6 +49,7 @@ type Config struct { haveBswap64 bool // architecture implements Bswap64 haveBswap32 bool // architecture implements Bswap32 haveBswap16 bool // architecture implements Bswap16 + haveCondSelect bool // architecture implements CondSelect // mulRecipes[x] = function to build v * x from v. mulRecipes map[int64]mulRecipe @@ -89,6 +89,10 @@ type Types struct { Float32Ptr *types.Type Float64Ptr *types.Type BytePtrPtr *types.Type + Vec128 *types.Type + Vec256 *types.Type + Vec512 *types.Type + Mask *types.Type } // NewTypes creates and populates a Types. @@ -123,21 +127,25 @@ func (t *Types) SetTypPtrs() { t.Float32Ptr = types.NewPtr(types.Types[types.TFLOAT32]) t.Float64Ptr = types.NewPtr(types.Types[types.TFLOAT64]) t.BytePtrPtr = types.NewPtr(types.NewPtr(types.Types[types.TUINT8])) + t.Vec128 = types.TypeVec128 + t.Vec256 = types.TypeVec256 + t.Vec512 = types.TypeVec512 + t.Mask = types.TypeMask } type Logger interface { // Logf logs a message from the compiler. - Logf(string, ...interface{}) + Logf(string, ...any) // Log reports whether logging is not a no-op // some logging calls account for more than a few heap allocations. Log() bool // Fatalf reports a compiler error and exits. - Fatalf(pos src.XPos, msg string, args ...interface{}) + Fatalf(pos src.XPos, msg string, args ...any) // Warnl writes compiler messages in the form expected by "errorcheck" tests - Warnl(pos src.XPos, fmt_ string, args ...interface{}) + Warnl(pos src.XPos, fmt_ string, args ...any) // Forwards the Debug flags from gc Debug_checknil() bool @@ -167,8 +175,6 @@ type Frontend interface { // NewConfig returns a new configuration object for the given architecture. func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat bool) *Config { c := &Config{arch: arch, Types: types} - c.useAvg = true - c.useHmul = true switch arch { case "amd64": c.PtrSize = 8 @@ -181,6 +187,7 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo c.registers = registersAMD64[:] c.gpRegMask = gpRegMaskAMD64 c.fpRegMask = fpRegMaskAMD64 + c.simdRegMask = simdRegMaskAMD64 c.specialRegMask = specialRegMaskAMD64 c.intParamRegs = paramIntRegAMD64 c.floatParamRegs = paramFloatRegAMD64 @@ -191,6 +198,7 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo c.haveBswap64 = true c.haveBswap32 = true c.haveBswap16 = true + c.haveCondSelect = true case "386": c.PtrSize = 4 c.RegSize = 4 @@ -227,6 +235,7 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo c.registers = registersARM64[:] c.gpRegMask = gpRegMaskARM64 c.fpRegMask = fpRegMaskARM64 + c.simdRegMask = simdRegMaskARM64 c.intParamRegs = paramIntRegARM64 c.floatParamRegs = paramFloatRegARM64 c.FPReg = framepointerRegARM64 @@ -236,6 +245,7 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo c.haveBswap64 = true c.haveBswap32 = true c.haveBswap16 = true + c.haveCondSelect = true case "ppc64": c.BigEndian = true fallthrough @@ -263,6 +273,7 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo c.haveBswap64 = true c.haveBswap32 = true c.haveBswap16 = true + c.haveCondSelect = true case "mips64": c.BigEndian = true fallthrough @@ -296,6 +307,10 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo c.LinkReg = linkRegLOONG64 c.hasGReg = true c.unalignedOK = true + c.haveBswap64 = true + c.haveBswap32 = true + c.haveBswap16 = true + c.haveCondSelect = true case "s390x": c.PtrSize = 8 c.RegSize = 8 @@ -304,6 +319,8 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo c.registers = registersS390X[:] c.gpRegMask = gpRegMaskS390X c.fpRegMask = fpRegMaskS390X + c.intParamRegs = paramIntRegS390X + c.floatParamRegs = paramFloatRegS390X c.FPReg = framepointerRegS390X c.LinkReg = linkRegS390X c.hasGReg = true @@ -351,11 +368,12 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo c.fpRegMask = fpRegMaskWasm c.fp32RegMask = fp32RegMaskWasm c.fp64RegMask = fp64RegMaskWasm + c.simdRegMask = simdRegMaskWasm c.FPReg = framepointerRegWasm c.LinkReg = linkRegWasm c.hasGReg = true - c.useAvg = false - c.useHmul = false + c.unalignedOK = true + c.haveCondSelect = true default: ctxt.Diag("arch %s not implemented", arch) } @@ -373,7 +391,7 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo // LoweredWB is secretly a CALL and CALLs on 386 in // shared mode get rewritten by obj6.go to go through // the GOT, which clobbers BX. - opcodeTable[Op386LoweredWB].reg.clobbers |= 1 << 3 // BX + opcodeTable[Op386LoweredWB].reg.clobbers = opcodeTable[Op386LoweredWB].reg.clobbers.addReg(3) // BX } c.buildRecipes(arch) diff --git a/src/cmd/compile/internal/ssa/copyelim.go b/src/cmd/compile/internal/ssa/copyelim.go index 09df63565be29c..762ffe1bd2d84c 100644 --- a/src/cmd/compile/internal/ssa/copyelim.go +++ b/src/cmd/compile/internal/ssa/copyelim.go @@ -105,11 +105,7 @@ func phielim(f *Func) { // This is an early place in SSA where all values are examined. // Rewrite all 0-sized Go values to remove accessors, dereferences, loads, etc. if t := v.Type; (t.IsStruct() || t.IsArray()) && t.Size() == 0 { - if t.IsStruct() { - v.reset(OpStructMake) - } else { - v.reset(OpArrayMake0) - } + v.reset(OpEmpty) } // Modify all values so no arg (including args // of OpCopy) is a copy. diff --git a/src/cmd/compile/internal/ssa/copyelim_test.go b/src/cmd/compile/internal/ssa/copyelim_test.go index fe31b12191646d..20e548f7fc9d3e 100644 --- a/src/cmd/compile/internal/ssa/copyelim_test.go +++ b/src/cmd/compile/internal/ssa/copyelim_test.go @@ -20,7 +20,7 @@ func BenchmarkCopyElim100000(b *testing.B) { benchmarkCopyElim(b, 100000) } func benchmarkCopyElim(b *testing.B, n int) { c := testConfig(b) - values := make([]interface{}, 0, n+2) + values := make([]any, 0, n+2) values = append(values, Valu("mem", OpInitMem, types.TypeMem, 0, nil)) last := "mem" for i := 0; i < n; i++ { diff --git a/src/cmd/compile/internal/ssa/cpufeatures.go b/src/cmd/compile/internal/ssa/cpufeatures.go new file mode 100644 index 00000000000000..e668958fab5339 --- /dev/null +++ b/src/cmd/compile/internal/ssa/cpufeatures.go @@ -0,0 +1,262 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "cmd/compile/internal/types" + "cmd/internal/obj" + "fmt" + "internal/goarch" +) + +type localEffect struct { + start CPUfeatures // features present at beginning of block + internal CPUfeatures // features implied by execution of block + end [2]CPUfeatures // for BlockIf, features present on outgoing edges + visited bool // On the first iteration this will be false for backedges. +} + +func (e localEffect) String() string { + return fmt.Sprintf("visited=%v, start=%v, internal=%v, end[0]=%v, end[1]=%v", e.visited, e.start, e.internal, e.end[0], e.end[1]) +} + +// ifEffect pattern matches for a BlockIf conditional on a load +// of a field from internal/cpu.X86 and returns the corresponding +// effect. +func ifEffect(b *Block) (features CPUfeatures, taken int) { + // TODO generalize for other architectures. + if b.Kind != BlockIf { + return + } + c := b.Controls[0] + + if c.Op == OpNot { + taken = 1 + c = c.Args[0] + } + if c.Op != OpLoad { + return + } + offPtr := c.Args[0] + if offPtr.Op != OpOffPtr { + return + } + addr := offPtr.Args[0] + if addr.Op != OpAddr || addr.Args[0].Op != OpSB { + return + } + sym := addr.Aux.(*obj.LSym) + if sym.Name != "internal/cpu.X86" { + return + } + o := offPtr.AuxInt + t := addr.Type + if !t.IsPtr() { + b.Func.Fatalf("The symbol %s is not a pointer, found %v instead", sym.Name, t) + } + t = t.Elem() + if !t.IsStruct() { + b.Func.Fatalf("The referent of symbol %s is not a struct, found %v instead", sym.Name, t) + } + match := "" + for _, f := range t.Fields() { + if o == f.Offset && f.Sym != nil { + match = f.Sym.Name + break + } + } + + switch match { + + case "HasAVX": + features = CPUavx + case "HasAVXVNNI": + features = CPUavx | CPUavxvnni + case "HasAVX2": + features = CPUavx2 | CPUavx + + // Compiler currently treats these all alike. + case "HasAVX512", "HasAVX512F", "HasAVX512CD", "HasAVX512BW", + "HasAVX512DQ", "HasAVX512VL", "HasAVX512VPCLMULQDQ": + features = CPUavx512 | CPUavx2 | CPUavx + + case "HasAVX512GFNI": + features = CPUavx512 | CPUgfni | CPUavx2 | CPUavx + case "HasAVX512VNNI": + features = CPUavx512 | CPUavx512vnni | CPUavx2 | CPUavx + case "HasAVX512VBMI": + features = CPUavx512 | CPUvbmi | CPUavx2 | CPUavx + case "HasAVX512VBMI2": + features = CPUavx512 | CPUvbmi2 | CPUavx2 | CPUavx + case "HasAVX512BITALG": + features = CPUavx512 | CPUbitalg | CPUavx2 | CPUavx + case "HasAVX512VPOPCNTDQ": + features = CPUavx512 | CPUvpopcntdq | CPUavx2 | CPUavx + + case "HasBMI1": + features = CPUvbmi + case "HasBMI2": + features = CPUvbmi2 + + // Features that are not currently interesting to the compiler. + case "HasAES", "HasADX", "HasERMS", "HasFSRM", "HasFMA", "HasGFNI", "HasOSXSAVE", + "HasPCLMULQDQ", "HasPOPCNT", "HasRDTSCP", "HasSHA", + "HasSSE3", "HasSSSE3", "HasSSE41", "HasSSE42": + + } + if b.Func.pass.debug > 2 { + b.Func.Warnl(b.Pos, "%s, block b%v has features offset %d, match is %s, features is %v", b.Func.Name, b.ID, o, match, features) + } + return +} + +func cpufeatures(f *Func) { + arch := f.Config.Ctxt().Arch.Family + // TODO there are other SIMD architectures + if arch != goarch.AMD64 { + return + } + + po := f.Postorder() + + effects := make([]localEffect, 1+f.NumBlocks(), 1+f.NumBlocks()) + + features := func(t *types.Type) CPUfeatures { + if t.IsSIMD() { + switch t.Size() { + case 16, 32: + return CPUavx + case 64: + return CPUavx512 | CPUavx2 | CPUavx + } + } + return CPUNone + } + + // visit blocks in reverse post order + // when b is visited, all of its predecessors (except for loop back edges) + // will have been visited + for i := len(po) - 1; i >= 0; i-- { + b := po[i] + + var feat CPUfeatures + + if b == f.Entry { + // Check the types of inputs and outputs, as well as annotations. + // Start with none and union all that is implied by all the types seen. + if f.Type != nil { // a problem for SSA tests + for _, field := range f.Type.RecvParamsResults() { + feat |= features(field.Type) + } + } + + } else { + // Start with all and intersect over predecessors + feat = CPUAll + for _, p := range b.Preds { + pb := p.Block() + if !effects[pb.ID].visited { + + continue + } + pi := p.Index() + if pb.Kind != BlockIf { + pi = 0 + } + + feat &= effects[pb.ID].end[pi] + } + } + + e := localEffect{start: feat, visited: true} + + // Separately capture the internal effects of this block + var internal CPUfeatures + for _, v := range b.Values { + // the rule applied here is, if the block contains any + // instruction that would fault if the feature (avx, avx512) + // were not present, then assume that the feature is present + // for all the instructions in the block, a fault is a fault. + t := v.Type + if t.IsResults() { + for i := 0; i < t.NumFields(); i++ { + feat |= features(t.FieldType(i)) + } + } else { + internal |= features(v.Type) + } + } + e.internal = internal + feat |= internal + + branchEffect, taken := ifEffect(b) + e.end = [2]CPUfeatures{feat, feat} + e.end[taken] |= branchEffect + + effects[b.ID] = e + if f.pass.debug > 1 && feat != CPUNone { + f.Warnl(b.Pos, "%s, block b%v has features %v", b.Func.Name, b.ID, feat) + } + + b.CPUfeatures = feat + f.maxCPUFeatures |= feat // not necessary to refine this estimate below + } + + // If the flow graph is irreducible, things can still change on backedges. + change := true + for change { + change = false + for i := len(po) - 1; i >= 0; i-- { + b := po[i] + + if b == f.Entry { + continue // cannot change + } + feat := CPUAll + for _, p := range b.Preds { + pb := p.Block() + pi := p.Index() + if pb.Kind != BlockIf { + pi = 0 + } + feat &= effects[pb.ID].end[pi] + } + e := effects[b.ID] + if feat == e.start { + continue + } + e.start = feat + effects[b.ID] = e + // uh-oh, something changed + if f.pass.debug > 1 { + f.Warnl(b.Pos, "%s, block b%v saw predecessor feature change", b.Func.Name, b.ID) + } + + feat |= e.internal + if feat == e.end[0]&e.end[1] { + continue + } + + branchEffect, taken := ifEffect(b) + e.end = [2]CPUfeatures{feat, feat} + e.end[taken] |= branchEffect + + effects[b.ID] = e + b.CPUfeatures = feat + if f.pass.debug > 1 { + f.Warnl(b.Pos, "%s, block b%v has new features %v", b.Func.Name, b.ID, feat) + } + change = true + } + } + if f.pass.debug > 0 { + for _, b := range f.Blocks { + if b.CPUfeatures != CPUNone { + f.Warnl(b.Pos, "%s, block b%v has features %v", b.Func.Name, b.ID, b.CPUfeatures) + } + + } + } +} diff --git a/src/cmd/compile/internal/ssa/cse.go b/src/cmd/compile/internal/ssa/cse.go index 28eb4f76a9d134..c8f87de99945d9 100644 --- a/src/cmd/compile/internal/ssa/cse.go +++ b/src/cmd/compile/internal/ssa/cse.go @@ -85,6 +85,11 @@ func cse(f *Func) { pNum++ } + // Keep a table to remap memory operand of any memory user which does not have a memory result (such as a regular load), + // to some dominating memory operation, skipping the memory defs that do not alias with it. + memTable := f.Cache.allocInt32Slice(f.NumValues()) + defer f.Cache.freeInt32Slice(memTable) + // Split equivalence classes at points where they have // non-equivalent arguments. Repeat until we can't find any // more splits. @@ -108,12 +113,23 @@ func cse(f *Func) { // Sort by eq class of arguments. slices.SortFunc(e, func(v, w *Value) int { + _, idxMem, _, _ := isMemUser(v) for i, a := range v.Args { - b := w.Args[i] - if valueEqClass[a.ID] < valueEqClass[b.ID] { + var aId, bId ID + if i != idxMem { + b := w.Args[i] + aId = a.ID + bId = b.ID + } else { + // A memory user's mem argument may be remapped to allow matching + // identical load-like instructions across disjoint stores. + aId, _ = getEffectiveMemoryArg(memTable, v) + bId, _ = getEffectiveMemoryArg(memTable, w) + } + if valueEqClass[aId] < valueEqClass[bId] { return -1 } - if valueEqClass[a.ID] > valueEqClass[b.ID] { + if valueEqClass[aId] > valueEqClass[bId] { return +1 } } @@ -126,12 +142,23 @@ func cse(f *Func) { v, w := e[j-1], e[j] // Note: commutative args already correctly ordered by byArgClass. eqArgs := true + _, idxMem, _, _ := isMemUser(v) for k, a := range v.Args { if v.Op == OpLocalAddr && k == 1 { continue } - b := w.Args[k] - if valueEqClass[a.ID] != valueEqClass[b.ID] { + var aId, bId ID + if k != idxMem { + b := w.Args[k] + aId = a.ID + bId = b.ID + } else { + // A memory user's mem argument may be remapped to allow matching + // identical load-like instructions across disjoint stores. + aId, _ = getEffectiveMemoryArg(memTable, v) + bId, _ = getEffectiveMemoryArg(memTable, w) + } + if valueEqClass[aId] != valueEqClass[bId] { eqArgs = false break } @@ -180,10 +207,19 @@ func cse(f *Func) { defer f.Cache.freeValueSlice(rewrite) for _, e := range partition { slices.SortFunc(e, func(v, w *Value) int { - c := cmp.Compare(sdom.domorder(v.Block), sdom.domorder(w.Block)) - if c != 0 { + if c := cmp.Compare(sdom.domorder(v.Block), sdom.domorder(w.Block)); c != 0 { return c } + if _, _, _, ok := isMemUser(v); ok { + // Additional ordering among the memory users within one block: prefer the earliest + // possible value among the set of equivalent values, that is the one with the lowest + // skip count (lowest number of memory defs skipped until their common def). + _, vSkips := getEffectiveMemoryArg(memTable, v) + _, wSkips := getEffectiveMemoryArg(memTable, w) + if c := cmp.Compare(vSkips, wSkips); c != 0 { + return c + } + } if v.Op == OpLocalAddr { // compare the memory args for OpLocalAddrs in the same block vm := v.Args[1] @@ -254,7 +290,7 @@ func cse(f *Func) { for _, v := range b.Values { for i, w := range v.Args { if x := rewrite[w.ID]; x != nil { - if w.Pos.IsStmt() == src.PosIsStmt { + if w.Pos.IsStmt() == src.PosIsStmt && w.Op != OpNilCheck { // about to lose a statement marker, w // w is an input to v; if they're in the same block // and the same line, v is a good-enough new statement boundary. @@ -420,3 +456,91 @@ func cmpVal(v, w *Value, auxIDs auxmap) types.Cmp { return types.CMPeq } + +// Query if the given instruction only uses "memory" argument and we may try to skip some memory "defs" if they do not alias with its address. +// Return index of pointer argument, index of "memory" argument, the access width and true on such instructions, otherwise return (-1, -1, 0, false). +func isMemUser(v *Value) (int, int, int64, bool) { + switch v.Op { + case OpLoad: + return 0, 1, v.Type.Size(), true + case OpNilCheck: + return 0, 1, 0, true + default: + return -1, -1, 0, false + } +} + +// Query if the given "memory"-defining instruction's memory destination can be analyzed for aliasing with a memory "user" instructions. +// Return index of pointer argument, index of "memory" argument, the access width and true on such instructions, otherwise return (-1, -1, 0, false). +// If the access width is 0, the pointer index may be -1 (no pointer operand is needed). +func isMemDef(v *Value) (int, int, int64, bool) { + switch v.Op { + case OpStore: + return 0, 2, auxToType(v.Aux).Size(), true + case OpVarDef: + return -1, 0, 0, true + case OpZero: + return 0, 1, v.AuxInt, true + default: + return -1, -1, 0, false + } +} + +// Mem table keeps memTableSkipBits lower bits to store the number of skips of "memory" operand +// and the rest to store the ID of the destination "memory"-producing instruction. +const memTableSkipBits = 8 + +// The maximum ID value we are able to store in the memTable, otherwise fall back to v.ID +const maxId = ID(1<<(31-memTableSkipBits)) - 1 + +// Return the first possibly-aliased store along the memory chain starting at v's memory argument and the number of not-aliased stores skipped. +func getEffectiveMemoryArg(memTable []int32, v *Value) (ID, uint32) { + if code := uint32(memTable[v.ID]); code != 0 { + return ID(code >> memTableSkipBits), code & ((1 << memTableSkipBits) - 1) + } + if idxPtr, idxMem, width, ok := isMemUser(v); ok { + // TODO: We could early return some predefined value if width==0 + memId := v.Args[idxMem].ID + if memId > maxId { + return memId, 0 + } + mem, skips := skipDisjointMemDefs(v, idxPtr, idxMem, width) + if mem.ID <= maxId { + memId = mem.ID + } else { + skips = 0 // avoid the skip + } + memTable[v.ID] = int32(memId< 50 { + // Skipping a memory def with a lot of uses may potentially increase register pressure. + break + } + if width == 0 { + mem = mem.Args[idxMem] + continue + } + defPtr := mem.Args[idxPtr] + if disjoint(defPtr, width, usePtr, useWidth) { + mem = mem.Args[idxMem] + continue + } + } + break + } + return mem, skips +} diff --git a/src/cmd/compile/internal/ssa/deadstore.go b/src/cmd/compile/internal/ssa/deadstore.go index d0adff788c0a4f..a3ee82883c8686 100644 --- a/src/cmd/compile/internal/ssa/deadstore.go +++ b/src/cmd/compile/internal/ssa/deadstore.go @@ -10,6 +10,10 @@ import ( "cmd/internal/obj" ) +// maxShadowRanges bounds the number of disjoint byte intervals +// we track per pointer to avoid quadratic behaviour. +const maxShadowRanges = 64 + // dse does dead-store elimination on the Function. // Dead stores are those which are unconditionally followed by // another store to the same location, with no intervening load. @@ -24,6 +28,10 @@ func dse(f *Func) { defer f.retSparseMap(shadowed) // localAddrs maps from a local variable (the Aux field of a LocalAddr value) to an instance of a LocalAddr value for that variable in the current block. localAddrs := map[any]*Value{} + + // shadowedRanges stores the actual range data. The 'shadowed' sparseMap stores a 1-based index into this slice. + var shadowedRanges []*shadowRanges + for _, b := range f.Blocks { // Find all the stores in this block. Categorize their uses: // loadUse contains stores which are used by a subsequent load. @@ -42,7 +50,18 @@ func dse(f *Func) { for _, a := range v.Args { if a.Block == b && a.Type.IsMemory() { storeUse.add(a.ID) - if v.Op != OpStore && v.Op != OpZero && v.Op != OpVarDef { + switch v.Op { + case OpStore, OpZero, OpVarDef: + // These ops never read from their memory input. + case OpMove: + // This op reads from its memory argument, but + // we can treat it as not doing so if we know + // the read is from read-only memory. + if v.Args[1].Op == OpAddr && symIsRO(auxToSym(v.Args[1].Aux)) { + break + } + fallthrough + default: // CALL, DUFFCOPY, etc. are both // reads and writes. loadUse.add(a.ID) @@ -89,10 +108,11 @@ func dse(f *Func) { // Walk backwards looking for dead stores. Keep track of shadowed addresses. // A "shadowed address" is a pointer, offset, and size describing a memory region that // is known to be written. We keep track of shadowed addresses in the shadowed map, - // mapping the ID of the address to a shadowRange where future writes will happen. + // mapping the ID of the address to a shadowRanges where future writes will happen. // Since we're walking backwards, writes to a shadowed region are useless, // as they will be immediately overwritten. shadowed.clear() + shadowedRanges = shadowedRanges[:0] v := last walkloop: @@ -100,8 +120,9 @@ func dse(f *Func) { // Someone might be reading this memory state. // Clear all shadowed addresses. shadowed.clear() + shadowedRanges = shadowedRanges[:0] } - if v.Op == OpStore || v.Op == OpZero { + if v.Op == OpStore || v.Op == OpZero || v.Op == OpMove { ptr := v.Args[0] var off int64 for ptr.Op == OpOffPtr { // Walk to base pointer @@ -109,9 +130,10 @@ func dse(f *Func) { ptr = ptr.Args[0] } var sz int64 - if v.Op == OpStore { + switch v.Op { + case OpStore: sz = v.Aux.(*types.Type).Size() - } else { // OpZero + case OpZero, OpMove: sz = v.AuxInt } if ptr.Op == OpLocalAddr { @@ -119,16 +141,22 @@ func dse(f *Func) { ptr = la } } - srNum, _ := shadowed.get(ptr.ID) - sr := shadowRange(srNum) - if sr.contains(off, off+sz) { - // Modify the store/zero into a copy of the memory state, + var si *shadowRanges + idx, ok := shadowed.get(ptr.ID) + if ok { + // The sparseMap stores a 1-based index, so we subtract 1. + si = shadowedRanges[idx-1] + } + + if si != nil && si.contains(off, off+sz) { + // Modify the store/zero/move into a copy of the memory state, // effectively eliding the store operation. - if v.Op == OpStore { - // store addr value mem + if v.Op == OpStore || v.Op == OpMove { + // Store addr value mem + // or Move dst src mem v.SetArgs1(v.Args[2]) } else { - // zero addr mem + // Zero addr mem v.SetArgs1(v.Args[1]) } v.Aux = nil @@ -136,7 +164,13 @@ func dse(f *Func) { v.Op = OpCopy } else { // Extend shadowed region. - shadowed.set(ptr.ID, int32(sr.merge(off, off+sz))) + if si == nil { + si = &shadowRanges{} + shadowedRanges = append(shadowedRanges, si) + // Store a 1-based index in the sparseMap. + shadowed.set(ptr.ID, int32(len(shadowedRanges))) + } + si.add(off, off+sz) } } // walk to previous store @@ -156,46 +190,51 @@ func dse(f *Func) { } } -// A shadowRange encodes a set of byte offsets [lo():hi()] from -// a given pointer that will be written to later in the block. -// A zero shadowRange encodes an empty shadowed range. -type shadowRange int32 - -func (sr shadowRange) lo() int64 { - return int64(sr & 0xffff) +// shadowRange represents a single byte range [lo,hi] that will be written. +type shadowRange struct { + lo, hi uint16 } -func (sr shadowRange) hi() int64 { - return int64((sr >> 16) & 0xffff) +// shadowRanges stores an unordered collection of disjoint byte ranges. +type shadowRanges struct { + ranges []shadowRange } // contains reports whether [lo:hi] is completely within sr. -func (sr shadowRange) contains(lo, hi int64) bool { - return lo >= sr.lo() && hi <= sr.hi() +func (sr *shadowRanges) contains(lo, hi int64) bool { + for _, r := range sr.ranges { + if lo >= int64(r.lo) && hi <= int64(r.hi) { + return true + } + } + return false } -// merge returns the union of sr and [lo:hi]. -// merge is allowed to return something smaller than the union. -func (sr shadowRange) merge(lo, hi int64) shadowRange { - if lo < 0 || hi > 0xffff { - // Ignore offsets that are too large or small. - return sr - } - if sr.lo() == sr.hi() { - // Old range is empty - use new one. - return shadowRange(lo + hi<<16) +func (sr *shadowRanges) add(lo, hi int64) { + // Ignore the store if: + // - the range doesn't fit in 16 bits, or + // - we already track maxShadowRanges intervals. + // The cap prevents a theoretical O(n^2) blow-up. + if lo < 0 || hi > 0xffff || len(sr.ranges) >= maxShadowRanges { + return } - if hi < sr.lo() || lo > sr.hi() { - // The two regions don't overlap or abut, so we would - // have to keep track of multiple disjoint ranges. - // Because we can only keep one, keep the larger one. - if sr.hi()-sr.lo() >= hi-lo { - return sr + nlo := lo + nhi := hi + out := sr.ranges[:0] + + for _, r := range sr.ranges { + if nhi < int64(r.lo) || nlo > int64(r.hi) { + out = append(out, r) + continue + } + if int64(r.lo) < nlo { + nlo = int64(r.lo) + } + if int64(r.hi) > nhi { + nhi = int64(r.hi) } - return shadowRange(lo + hi<<16) } - // Regions overlap or abut - compute the union. - return shadowRange(min(lo, sr.lo()) + max(hi, sr.hi())<<16) + sr.ranges = append(out, shadowRange{uint16(nlo), uint16(nhi)}) } // elimDeadAutosGeneric deletes autos that are never accessed. To achieve this @@ -203,9 +242,27 @@ func (sr shadowRange) merge(lo, hi int64) shadowRange { // reaches stores then we delete all the stores. The other operations will then // be eliminated by the dead code elimination pass. func elimDeadAutosGeneric(f *Func) { - addr := make(map[*Value]*ir.Name) // values that the address of the auto reaches - elim := make(map[*Value]*ir.Name) // values that could be eliminated if the auto is - var used ir.NameSet // used autos that must be kept + addr := make(map[*Value]*ir.Name) // values that the address of the auto reaches + elim := make(map[*Value]*ir.Name) // values that could be eliminated if the auto is + move := make(map[*ir.Name]ir.NameSet) // for a (Move &y &x _) and y is unused, move[y].Add(x) + var used ir.NameSet // used autos that must be kept + + // Adds a name to used and, when it is the target of a move, also + // propagates the used state to its source. + var usedAdd func(n *ir.Name) bool + usedAdd = func(n *ir.Name) bool { + if used.Has(n) { + return false + } + used.Add(n) + if s := move[n]; s != nil { + delete(move, n) + for n := range s { + usedAdd(n) + } + } + return true + } // visit the value and report whether any of the maps are updated visit := func(v *Value) (changed bool) { @@ -244,10 +301,7 @@ func elimDeadAutosGeneric(f *Func) { if !ok || (n.Class != ir.PAUTO && !isABIInternalParam(f, n)) { return } - if !used.Has(n) { - used.Add(n) - changed = true - } + changed = usedAdd(n) || changed return case OpStore, OpMove, OpZero: // v should be eliminated if we eliminate the auto. @@ -279,10 +333,22 @@ func elimDeadAutosGeneric(f *Func) { if v.Type.IsMemory() || v.Type.IsFlags() || v.Op == OpPhi || v.MemoryArg() != nil { for _, a := range args { if n, ok := addr[a]; ok { - if !used.Has(n) { - used.Add(n) - changed = true + // If the addr of n is used by an OpMove as its source arg, + // and the OpMove's target arg is the addr of a unused name, + // then temporarily treat n as unused, and record in move map. + if nam, ok := elim[v]; ok && v.Op == OpMove && !used.Has(nam) { + if used.Has(n) { + continue + } + s := move[nam] + if s == nil { + s = ir.NameSet{} + move[nam] = s + } + s.Add(n) + continue } + changed = usedAdd(n) || changed } } return @@ -291,17 +357,21 @@ func elimDeadAutosGeneric(f *Func) { // Propagate any auto addresses through v. var node *ir.Name for _, a := range args { - if n, ok := addr[a]; ok && !used.Has(n) { + if n, ok := addr[a]; ok { if node == nil { - node = n - } else if node != n { + if !used.Has(n) { + node = n + } + } else { + if node == n { + continue + } // Most of the time we only see one pointer // reaching an op, but some ops can take // multiple pointers (e.g. NeqPtr, Phi etc.). // This is rare, so just propagate the first // value to keep things simple. - used.Add(n) - changed = true + changed = usedAdd(n) || changed } } } @@ -316,8 +386,7 @@ func elimDeadAutosGeneric(f *Func) { } if addr[v] != node { // This doesn't happen in practice, but catch it just in case. - used.Add(node) - changed = true + changed = usedAdd(node) || changed } return } @@ -336,9 +405,8 @@ func elimDeadAutosGeneric(f *Func) { } // keep the auto if its address reaches a control value for _, c := range b.ControlValues() { - if n, ok := addr[c]; ok && !used.Has(n) { - used.Add(n) - changed = true + if n, ok := addr[c]; ok { + changed = usedAdd(n) || changed } } } diff --git a/src/cmd/compile/internal/ssa/deadstore_test.go b/src/cmd/compile/internal/ssa/deadstore_test.go index 4ccd6b8e91bf12..7c7a4dacf01c56 100644 --- a/src/cmd/compile/internal/ssa/deadstore_test.go +++ b/src/cmd/compile/internal/ssa/deadstore_test.go @@ -7,6 +7,8 @@ package ssa import ( "cmd/compile/internal/types" "cmd/internal/src" + "fmt" + "sort" "testing" ) @@ -172,3 +174,335 @@ func TestDeadStoreSmallStructInit(t *testing.T) { t.Errorf("dead store not removed") } } + +func TestDeadStoreArrayGap(t *testing.T) { + c := testConfig(t) + ptr := c.config.Types.BytePtr + i64 := c.config.Types.Int64 + + typ := types.NewArray(i64, 5) + tmp := c.Temp(typ) + + fun := c.Fun("entry", + Bloc("entry", + Valu("start", OpInitMem, types.TypeMem, 0, nil), + Valu("sp", OpSP, c.config.Types.Uintptr, 0, nil), + + Valu("base", OpLocalAddr, ptr, 0, tmp, "sp", "start"), + + Valu("p0", OpOffPtr, ptr, 0, nil, "base"), + Valu("p1", OpOffPtr, ptr, 8, nil, "base"), + Valu("p2", OpOffPtr, ptr, 16, nil, "base"), + Valu("p3", OpOffPtr, ptr, 24, nil, "base"), + Valu("p4", OpOffPtr, ptr, 32, nil, "base"), + + Valu("one", OpConst64, i64, 1, nil), + Valu("seven", OpConst64, i64, 7, nil), + Valu("zero", OpConst64, i64, 0, nil), + + Valu("mem0", OpZero, types.TypeMem, 40, typ, "base", "start"), + + Valu("s0", OpStore, types.TypeMem, 0, i64, "p0", "one", "mem0"), + Valu("s1", OpStore, types.TypeMem, 0, i64, "p1", "seven", "s0"), + Valu("s2", OpStore, types.TypeMem, 0, i64, "p3", "one", "s1"), + Valu("s3", OpStore, types.TypeMem, 0, i64, "p4", "one", "s2"), + Valu("s4", OpStore, types.TypeMem, 0, i64, "p2", "zero", "s3"), + + Goto("exit")), + Bloc("exit", + Exit("s4"))) + + CheckFunc(fun.f) + dse(fun.f) + CheckFunc(fun.f) + + if op := fun.values["mem0"].Op; op != OpCopy { + t.Fatalf("dead Zero not removed: got %s, want OpCopy", op) + } +} + +func TestShadowRanges(t *testing.T) { + t.Run("simple insert & contains", func(t *testing.T) { + var sr shadowRanges + sr.add(10, 20) + + wantRanges(t, sr.ranges, [][2]uint16{{10, 20}}) + if !sr.contains(12, 18) || !sr.contains(10, 20) { + t.Fatalf("contains failed after simple add") + } + if sr.contains(9, 11) || sr.contains(11, 21) { + t.Fatalf("contains erroneously true for non-contained range") + } + }) + + t.Run("merge overlapping", func(t *testing.T) { + var sr shadowRanges + sr.add(10, 20) + sr.add(15, 25) + + wantRanges(t, sr.ranges, [][2]uint16{{10, 25}}) + if !sr.contains(13, 24) { + t.Fatalf("contains should be true after merge") + } + }) + + t.Run("merge touching boundary", func(t *testing.T) { + var sr shadowRanges + sr.add(100, 150) + // touches at 150 - should coalesce + sr.add(150, 180) + + wantRanges(t, sr.ranges, [][2]uint16{{100, 180}}) + }) + + t.Run("union across several ranges", func(t *testing.T) { + var sr shadowRanges + sr.add(10, 20) + sr.add(30, 40) + // bridges second, not first + sr.add(25, 35) + + wantRanges(t, sr.ranges, [][2]uint16{{10, 20}, {25, 40}}) + + // envelops everything + sr.add(5, 50) + wantRanges(t, sr.ranges, [][2]uint16{{5, 50}}) + }) + + t.Run("disjoint intervals stay separate", func(t *testing.T) { + var sr shadowRanges + sr.add(10, 20) + sr.add(22, 30) + + wantRanges(t, sr.ranges, [][2]uint16{{10, 20}, {22, 30}}) + // spans both + if sr.contains(15, 25) { + t.Fatalf("contains across two disjoint ranges should be false") + } + }) + + t.Run("large uint16 offsets still work", func(t *testing.T) { + var sr shadowRanges + sr.add(40000, 45000) + + if !sr.contains(42000, 43000) { + t.Fatalf("contains failed for large uint16 values") + } + }) + + t.Run("out-of-bounds inserts ignored", func(t *testing.T) { + var sr shadowRanges + sr.add(10, 20) + sr.add(-5, 5) + sr.add(70000, 70010) + + wantRanges(t, sr.ranges, [][2]uint16{{10, 20}}) + }) +} + +// canonicalise order for comparisons +func sortRanges(r []shadowRange) { + sort.Slice(r, func(i, j int) bool { return r[i].lo < r[j].lo }) +} + +// compare actual slice with expected pairs +func wantRanges(t *testing.T, got []shadowRange, want [][2]uint16) { + t.Helper() + sortRanges(got) + + if len(got) != len(want) { + t.Fatalf("len(ranges)=%d, want %d (got=%v)", len(got), len(want), got) + } + + for i, w := range want { + if got[i].lo != w[0] || got[i].hi != w[1] { + t.Fatalf("range %d = [%d,%d], want [%d,%d] (full=%v)", + i, got[i].lo, got[i].hi, w[0], w[1], got) + } + } +} + +func BenchmarkDeadStore(b *testing.B) { + cfg := testConfig(b) + ptr := cfg.config.Types.BytePtr + + f := cfg.Fun("entry", + Bloc("entry", + Valu("start", OpInitMem, types.TypeMem, 0, nil), + Valu("sb", OpSB, cfg.config.Types.Uintptr, 0, nil), + Valu("v", OpConstBool, cfg.config.Types.Bool, 1, nil), + Valu("a1", OpAddr, ptr, 0, nil, "sb"), + Valu("a2", OpAddr, ptr, 0, nil, "sb"), + Valu("a3", OpAddr, ptr, 0, nil, "sb"), + Valu("z1", OpZero, types.TypeMem, 1, cfg.config.Types.Bool, "a3", "start"), + Valu("s1", OpStore, types.TypeMem, 0, cfg.config.Types.Bool, "a1", "v", "z1"), + Valu("s2", OpStore, types.TypeMem, 0, cfg.config.Types.Bool, "a2", "v", "s1"), + Valu("s3", OpStore, types.TypeMem, 0, cfg.config.Types.Bool, "a1", "v", "s2"), + Valu("s4", OpStore, types.TypeMem, 0, cfg.config.Types.Bool, "a3", "v", "s3"), + Goto("exit")), + Bloc("exit", + Exit("s3"))) + + runBench(b, func() { + dse(f.f) + }) +} + +func BenchmarkDeadStorePhi(b *testing.B) { + cfg := testConfig(b) + ptr := cfg.config.Types.BytePtr + + f := cfg.Fun("entry", + Bloc("entry", + Valu("start", OpInitMem, types.TypeMem, 0, nil), + Valu("sb", OpSB, cfg.config.Types.Uintptr, 0, nil), + Valu("v", OpConstBool, cfg.config.Types.Bool, 1, nil), + Valu("addr", OpAddr, ptr, 0, nil, "sb"), + Goto("loop")), + Bloc("loop", + Valu("phi", OpPhi, types.TypeMem, 0, nil, "start", "store"), + Valu("store", OpStore, types.TypeMem, 0, cfg.config.Types.Bool, "addr", "v", "phi"), + If("v", "loop", "exit")), + Bloc("exit", + Exit("store"))) + + runBench(b, func() { + dse(f.f) + }) +} + +func BenchmarkDeadStoreTypes(b *testing.B) { + cfg := testConfig(b) + + t1 := cfg.config.Types.UInt64.PtrTo() + t2 := cfg.config.Types.UInt32.PtrTo() + + f := cfg.Fun("entry", + Bloc("entry", + Valu("start", OpInitMem, types.TypeMem, 0, nil), + Valu("sb", OpSB, cfg.config.Types.Uintptr, 0, nil), + Valu("v", OpConstBool, cfg.config.Types.Bool, 1, nil), + Valu("a1", OpAddr, t1, 0, nil, "sb"), + Valu("a2", OpAddr, t2, 0, nil, "sb"), + Valu("s1", OpStore, types.TypeMem, 0, cfg.config.Types.Bool, "a1", "v", "start"), + Valu("s2", OpStore, types.TypeMem, 0, cfg.config.Types.Bool, "a2", "v", "s1"), + Goto("exit")), + Bloc("exit", + Exit("s2"))) + cse(f.f) + + runBench(b, func() { + dse(f.f) + }) +} + +func BenchmarkDeadStoreUnsafe(b *testing.B) { + cfg := testConfig(b) + ptr := cfg.config.Types.UInt64.PtrTo() + f := cfg.Fun("entry", + Bloc("entry", + Valu("start", OpInitMem, types.TypeMem, 0, nil), + Valu("sb", OpSB, cfg.config.Types.Uintptr, 0, nil), + Valu("v", OpConstBool, cfg.config.Types.Bool, 1, nil), + Valu("a1", OpAddr, ptr, 0, nil, "sb"), + Valu("s1", OpStore, types.TypeMem, 0, cfg.config.Types.Int64, "a1", "v", "start"), + Valu("s2", OpStore, types.TypeMem, 0, cfg.config.Types.Bool, "a1", "v", "s1"), + Goto("exit")), + Bloc("exit", + Exit("s2"))) + cse(f.f) + runBench(b, func() { + dse(f.f) + }) +} + +func BenchmarkDeadStoreSmallStructInit(b *testing.B) { + cfg := testConfig(b) + ptr := cfg.config.Types.BytePtr + + typ := types.NewStruct([]*types.Field{ + types.NewField(src.NoXPos, &types.Sym{Name: "A"}, cfg.config.Types.Int), + types.NewField(src.NoXPos, &types.Sym{Name: "B"}, cfg.config.Types.Int), + }) + tmp := cfg.Temp(typ) + + f := cfg.Fun("entry", + Bloc("entry", + Valu("start", OpInitMem, types.TypeMem, 0, nil), + Valu("sp", OpSP, cfg.config.Types.Uintptr, 0, nil), + Valu("zero", OpConst64, cfg.config.Types.Int, 0, nil), + + Valu("v6", OpLocalAddr, ptr, 0, tmp, "sp", "start"), + Valu("v3", OpOffPtr, ptr, 8, nil, "v6"), + Valu("v22", OpOffPtr, ptr, 0, nil, "v6"), + Valu("s1", OpStore, types.TypeMem, 0, cfg.config.Types.Int, "v22", "zero", "start"), + Valu("s2", OpStore, types.TypeMem, 0, cfg.config.Types.Int, "v3", "zero", "s1"), + + Valu("v8", OpLocalAddr, ptr, 0, tmp, "sp", "s2"), + Valu("v23", OpOffPtr, ptr, 8, nil, "v8"), + Valu("v25", OpOffPtr, ptr, 0, nil, "v8"), + Valu("s3", OpStore, types.TypeMem, 0, cfg.config.Types.Int, "v25", "zero", "s2"), + Valu("s4", OpStore, types.TypeMem, 0, cfg.config.Types.Int, "v23", "zero", "s3"), + Goto("exit")), + Bloc("exit", + Exit("s4"))) + cse(f.f) + + runBench(b, func() { + dse(f.f) + }) +} + +func BenchmarkDeadStoreLargeBlock(b *testing.B) { + // create a very large block with many shadowed stores + const ( + addrCount = 128 + // first 7 are dead + storesPerAddr = 8 + ) + cfg := testConfig(b) + ptrType := cfg.config.Types.BytePtr + boolType := cfg.config.Types.Bool + + items := []interface{}{ + Valu("start", OpInitMem, types.TypeMem, 0, nil), + Valu("sb", OpSB, cfg.config.Types.Uintptr, 0, nil), + Valu("v", OpConstBool, boolType, 1, nil), + } + + for i := 0; i < addrCount; i++ { + items = append(items, + Valu(fmt.Sprintf("addr%d", i), OpAddr, ptrType, 0, nil, "sb"), + ) + } + + prev := "start" + for round := 0; round < storesPerAddr; round++ { + for i := 0; i < addrCount; i++ { + store := fmt.Sprintf("s_%03d_%d", i, round) + addr := fmt.Sprintf("addr%d", i) + items = append(items, + Valu(store, OpStore, types.TypeMem, 0, boolType, addr, "v", prev), + ) + prev = store + } + } + + items = append(items, Goto("exit")) + entryBlk := Bloc("entry", items...) + exitBlk := Bloc("exit", Exit(prev)) + + f := cfg.Fun("stress", entryBlk, exitBlk) + + runBench(b, func() { + dse(f.f) + }) +} + +func runBench(b *testing.B, build func()) { + b.ReportAllocs() + b.ResetTimer() + for i := 0; i < b.N; i++ { + build() + } +} diff --git a/src/cmd/compile/internal/ssa/debug.go b/src/cmd/compile/internal/ssa/debug.go index 7edc414bda7eb7..f45bb4d388922b 100644 --- a/src/cmd/compile/internal/ssa/debug.go +++ b/src/cmd/compile/internal/ssa/debug.go @@ -13,7 +13,6 @@ import ( "cmd/internal/obj" "cmd/internal/src" "cmp" - "encoding/hex" "fmt" "internal/buildcfg" "math/bits" @@ -35,7 +34,7 @@ type FuncDebug struct { // The slots that make up each variable, indexed by VarID. VarSlots [][]SlotID // The location list data, indexed by VarID. Must be processed by PutLocationList. - LocationLists [][]byte + LocationLists [][]LocListEntry // Register-resident output parameters for the function. This is filled in at // SSA generation time. RegOutputParams []*ir.Name @@ -52,6 +51,15 @@ type FuncDebug struct { GetPC func(block, value ID) int64 } +// LocListEntry represents a single entry in a location list. +// StartBlock/StartValue and EndBlock/EndValue are SSA coordinates +// that get resolved to PCs during final encoding. +type LocListEntry struct { + StartBlock, StartValue ID + EndBlock, EndValue ID + Expr []byte // DWARF location expression (DW_OP_*) +} + type BlockDebug struct { // State at the start and end of the block. These are initialized, // and updated from new information that flows on back edges. @@ -195,7 +203,7 @@ type RegisterSet uint64 // logf prints debug-specific logging to stdout (always stdout) if the // current function is tagged by GOSSAFUNC (for ssa output directed // either to stdout or html). -func (s *debugState) logf(msg string, args ...interface{}) { +func (s *debugState) logf(msg string, args ...any) { if s.f.PrintOrHtmlSSA { fmt.Printf(msg, args...) } @@ -206,7 +214,7 @@ type debugState struct { slots []LocalSlot vars []*ir.Name varSlots [][]SlotID - lists [][]byte + lists [][]LocListEntry // The user variable that each slot rolls up to, indexed by SlotID. slotVars []VarID @@ -293,7 +301,7 @@ func (state *debugState) initializeCache(f *Func, numVars, numSlots int) { state.pendingEntries = pe if cap(state.lists) < numVars { - state.lists = make([][]byte, numVars) + state.lists = make([][]LocListEntry, numVars) } else { state.lists = state.lists[:numVars] clear(state.lists) @@ -1043,13 +1051,13 @@ func (state *debugState) processValue(v *Value, vSlots []SlotID, vReg *Register) // Handle any register clobbering. Call operations, for example, // clobber all registers even though they don't explicitly write to // them. - clobbers := uint64(opcodeTable[v.Op].reg.clobbers) + clobbers := opcodeTable[v.Op].reg.clobbers for { - if clobbers == 0 { + if clobbers.empty() { break } - reg := uint8(bits.TrailingZeros64(clobbers)) - clobbers &^= 1 << reg + reg := clobbers.pickReg() + clobbers = clobbers.removeReg(reg) for _, slot := range locs.registers[reg] { if state.loggingLevel > 1 { @@ -1348,7 +1356,7 @@ func (state *debugState) buildLocationLists(blockLocs []*BlockDebug) { if len(list) == 0 { state.logf("\t%v : empty list\n", state.vars[varID]) } else { - state.logf("\t%v : %q\n", state.vars[varID], hex.EncodeToString(state.lists[varID])) + state.logf("\t%v : %d entries\n", state.vars[varID], len(list)) } } } @@ -1405,32 +1413,14 @@ func (state *debugState) writePendingEntry(varID VarID, endBlock, endValue ID) { return } - // Pack the start/end coordinates into the start/end addresses - // of the entry, for decoding by PutLocationList. - start, startOK := encodeValue(state.ctxt, pending.startBlock, pending.startValue) - end, endOK := encodeValue(state.ctxt, endBlock, endValue) - if !startOK || !endOK { - // If someone writes a function that uses >65K values, - // they get incomplete debug info on 32-bit platforms. - return - } - if start == end { + // Skip zero-width entries where start and end coordinates are identical. + if pending.startBlock == endBlock && pending.startValue == endValue { if state.loggingLevel > 1 { - // Printf not logf so not gated by GOSSAFUNC; this should fire very rarely. - // TODO this fires a lot, need to figure out why. state.logf("Skipping empty location list for %v in %s\n", state.vars[varID], state.f.Name) } return } - list := state.lists[varID] - list = appendPtr(state.ctxt, list, start) - list = appendPtr(state.ctxt, list, end) - // Where to write the length of the location description once - // we know how big it is. - sizeIdx := len(list) - list = list[:len(list)+2] - if state.loggingLevel > 1 { var partStrs []string for i, slot := range state.varSlots[varID] { @@ -1439,6 +1429,8 @@ func (state *debugState) writePendingEntry(varID VarID, endBlock, endValue ID) { state.logf("Add entry for %v: \tb%vv%v-b%vv%v = \t%v\n", state.vars[varID], pending.startBlock, pending.startValue, endBlock, endValue, strings.Join(partStrs, " ")) } + // Build the DWARF location expression. + var expr []byte for i, slotID := range state.varSlots[varID] { loc := pending.pieces[i] slot := state.slots[slotID] @@ -1446,49 +1438,51 @@ func (state *debugState) writePendingEntry(varID VarID, endBlock, endValue ID) { if !loc.absent() { if loc.onStack() { if loc.stackOffsetValue() == 0 { - list = append(list, dwarf.DW_OP_call_frame_cfa) + expr = append(expr, dwarf.DW_OP_call_frame_cfa) } else { - list = append(list, dwarf.DW_OP_fbreg) - list = dwarf.AppendSleb128(list, int64(loc.stackOffsetValue())) + expr = append(expr, dwarf.DW_OP_fbreg) + expr = dwarf.AppendSleb128(expr, int64(loc.stackOffsetValue())) } } else { regnum := state.ctxt.Arch.DWARFRegisters[state.registers[firstReg(loc.Registers)].ObjNum()] if regnum < 32 { - list = append(list, dwarf.DW_OP_reg0+byte(regnum)) + expr = append(expr, dwarf.DW_OP_reg0+byte(regnum)) } else { - list = append(list, dwarf.DW_OP_regx) - list = dwarf.AppendUleb128(list, uint64(regnum)) + expr = append(expr, dwarf.DW_OP_regx) + expr = dwarf.AppendUleb128(expr, uint64(regnum)) } } } if len(state.varSlots[varID]) > 1 { - list = append(list, dwarf.DW_OP_piece) - list = dwarf.AppendUleb128(list, uint64(slot.Type.Size())) + expr = append(expr, dwarf.DW_OP_piece) + expr = dwarf.AppendUleb128(expr, uint64(slot.Type.Size())) } } - state.ctxt.Arch.ByteOrder.PutUint16(list[sizeIdx:], uint16(len(list)-sizeIdx-2)) - state.lists[varID] = list + + entry := LocListEntry{ + StartBlock: pending.startBlock, + StartValue: pending.startValue, + EndBlock: endBlock, + EndValue: endValue, + Expr: expr, + } + state.lists[varID] = append(state.lists[varID], entry) } -// PutLocationList adds list (a location list in its intermediate -// representation) to listSym. -func (debugInfo *FuncDebug) PutLocationList(list []byte, ctxt *obj.Link, listSym, startPC *obj.LSym) { +// PutLocationList adds entries (a location list in structured form) +// to listSym, encoding it in the appropriate DWARF format. +func (debugInfo *FuncDebug) PutLocationList(entries []LocListEntry, ctxt *obj.Link, listSym, startPC *obj.LSym) { if buildcfg.Experiment.Dwarf5 { - debugInfo.PutLocationListDwarf5(list, ctxt, listSym, startPC) + debugInfo.PutLocationListDwarf5(entries, ctxt, listSym, startPC) } else { - debugInfo.PutLocationListDwarf4(list, ctxt, listSym, startPC) + debugInfo.PutLocationListDwarf4(entries, ctxt, listSym, startPC) } } -// PutLocationListDwarf5 adds list (a location list in its intermediate -// representation) to listSym in DWARF 5 format. NB: this is a somewhat -// hacky implementation in that it actually reads a DWARF4 encoded -// info from list (with all its DWARF4-specific quirks) then re-encodes -// it in DWARF5. It would probably be better at some point to have -// ssa/debug encode the list in a version-independent form and then -// have this func (and PutLocationListDwarf4) intoduce the quirks. -func (debugInfo *FuncDebug) PutLocationListDwarf5(list []byte, ctxt *obj.Link, listSym, startPC *obj.LSym) { +// PutLocationListDwarf5 adds entries (a location list in structured form) +// to listSym in DWARF 5 format. +func (debugInfo *FuncDebug) PutLocationListDwarf5(entries []LocListEntry, ctxt *obj.Link, listSym, startPC *obj.LSym) { getPC := debugInfo.GetPC // base address entry @@ -1496,42 +1490,34 @@ func (debugInfo *FuncDebug) PutLocationListDwarf5(list []byte, ctxt *obj.Link, l listSym.WriteDwTxtAddrx(ctxt, listSym.Size, startPC, ctxt.DwTextCount*2) var stbuf, enbuf [10]byte - stb, enb := stbuf[:], enbuf[:] - // Re-read list, translating its address from block/value ID to PC. - for i := 0; i < len(list); { - begin := getPC(decodeValue(ctxt, readPtr(ctxt, list[i:]))) - end := getPC(decodeValue(ctxt, readPtr(ctxt, list[i+ctxt.Arch.PtrSize:]))) + for _, entry := range entries { + begin := getPC(entry.StartBlock, entry.StartValue) + end := getPC(entry.EndBlock, entry.EndValue) // Write LLE_offset_pair tag followed by payload (ULEB for start // and then end). listSym.WriteInt(ctxt, listSym.Size, 1, dwarf.DW_LLE_offset_pair) - stb, enb = stb[:0], enb[:0] + stb := stbuf[:0] + enb := enbuf[:0] stb = dwarf.AppendUleb128(stb, uint64(begin)) enb = dwarf.AppendUleb128(enb, uint64(end)) listSym.WriteBytes(ctxt, listSym.Size, stb) listSym.WriteBytes(ctxt, listSym.Size, enb) - // The encoded data in "list" is in DWARF4 format, which uses - // a 2-byte length; DWARF5 uses an LEB-encoded value for this - // length. Read the length and then re-encode it. - i += 2 * ctxt.Arch.PtrSize - datalen := int(ctxt.Arch.ByteOrder.Uint16(list[i:])) - i += 2 - stb = stb[:0] - stb = dwarf.AppendUleb128(stb, uint64(datalen)) - listSym.WriteBytes(ctxt, listSym.Size, stb) // copy length - listSym.WriteBytes(ctxt, listSym.Size, list[i:i+datalen]) // loc desc - - i += datalen + // DWARF5 uses ULEB128-encoded length for the location expression. + stb = stbuf[:0] + stb = dwarf.AppendUleb128(stb, uint64(len(entry.Expr))) + listSym.WriteBytes(ctxt, listSym.Size, stb) + listSym.WriteBytes(ctxt, listSym.Size, entry.Expr) } // Terminator listSym.WriteInt(ctxt, listSym.Size, 1, dwarf.DW_LLE_end_of_list) } -// PutLocationListDwarf4 adds list (a location list in its intermediate -// representation) to listSym in DWARF 4 format. -func (debugInfo *FuncDebug) PutLocationListDwarf4(list []byte, ctxt *obj.Link, listSym, startPC *obj.LSym) { +// PutLocationListDwarf4 adds entries (a location list in structured form) +// to listSym in DWARF 4 format. +func (debugInfo *FuncDebug) PutLocationListDwarf4(entries []LocListEntry, ctxt *obj.Link, listSym, startPC *obj.LSym) { getPC := debugInfo.GetPC if ctxt.UseBASEntries { @@ -1539,10 +1525,9 @@ func (debugInfo *FuncDebug) PutLocationListDwarf4(list []byte, ctxt *obj.Link, l listSym.WriteAddr(ctxt, listSym.Size, ctxt.Arch.PtrSize, startPC, 0) } - // Re-read list, translating its address from block/value ID to PC. - for i := 0; i < len(list); { - begin := getPC(decodeValue(ctxt, readPtr(ctxt, list[i:]))) - end := getPC(decodeValue(ctxt, readPtr(ctxt, list[i+ctxt.Arch.PtrSize:]))) + for _, entry := range entries { + begin := getPC(entry.StartBlock, entry.StartValue) + end := getPC(entry.EndBlock, entry.EndValue) // Horrible hack. If a range contains only zero-width // instructions, e.g. an Arg, and it's at the beginning of the @@ -1560,113 +1545,16 @@ func (debugInfo *FuncDebug) PutLocationListDwarf4(list []byte, ctxt *obj.Link, l listSym.WriteCURelativeAddr(ctxt, listSym.Size, startPC, end) } - i += 2 * ctxt.Arch.PtrSize - datalen := 2 + int(ctxt.Arch.ByteOrder.Uint16(list[i:])) - listSym.WriteBytes(ctxt, listSym.Size, list[i:i+datalen]) // copy datalen and location encoding - i += datalen + // Write 2-byte length prefix followed by the location expression. + listSym.WriteInt(ctxt, listSym.Size, 2, int64(len(entry.Expr))) + listSym.WriteBytes(ctxt, listSym.Size, entry.Expr) } - // Location list contents, now with real PCs. // End entry. listSym.WriteInt(ctxt, listSym.Size, ctxt.Arch.PtrSize, 0) listSym.WriteInt(ctxt, listSym.Size, ctxt.Arch.PtrSize, 0) } -// Pack a value and block ID into an address-sized uint, returning -// encoded value and boolean indicating whether the encoding succeeded. -// For 32-bit architectures the process may fail for very large -// procedures(the theory being that it's ok to have degraded debug -// quality in this case). -func encodeValue(ctxt *obj.Link, b, v ID) (uint64, bool) { - if ctxt.Arch.PtrSize == 8 { - result := uint64(b)<<32 | uint64(uint32(v)) - //ctxt.Logf("b %#x (%d) v %#x (%d) -> %#x\n", b, b, v, v, result) - return result, true - } - if ctxt.Arch.PtrSize != 4 { - panic("unexpected pointer size") - } - if ID(int16(b)) != b || ID(int16(v)) != v { - return 0, false - } - return uint64(b)<<16 | uint64(uint16(v)), true -} - -// Unpack a value and block ID encoded by encodeValue. -func decodeValue(ctxt *obj.Link, word uint64) (ID, ID) { - if ctxt.Arch.PtrSize == 8 { - b, v := ID(word>>32), ID(word) - //ctxt.Logf("%#x -> b %#x (%d) v %#x (%d)\n", word, b, b, v, v) - return b, v - } - if ctxt.Arch.PtrSize != 4 { - panic("unexpected pointer size") - } - return ID(word >> 16), ID(int16(word)) -} - -// Append a pointer-sized uint to buf. -func appendPtr(ctxt *obj.Link, buf []byte, word uint64) []byte { - if cap(buf) < len(buf)+20 { - b := make([]byte, len(buf), 20+cap(buf)*2) - copy(b, buf) - buf = b - } - writeAt := len(buf) - buf = buf[0 : len(buf)+ctxt.Arch.PtrSize] - writePtr(ctxt, buf[writeAt:], word) - return buf -} - -// Write a pointer-sized uint to the beginning of buf. -func writePtr(ctxt *obj.Link, buf []byte, word uint64) { - switch ctxt.Arch.PtrSize { - case 4: - ctxt.Arch.ByteOrder.PutUint32(buf, uint32(word)) - case 8: - ctxt.Arch.ByteOrder.PutUint64(buf, word) - default: - panic("unexpected pointer size") - } - -} - -// Read a pointer-sized uint from the beginning of buf. -func readPtr(ctxt *obj.Link, buf []byte) uint64 { - switch ctxt.Arch.PtrSize { - case 4: - return uint64(ctxt.Arch.ByteOrder.Uint32(buf)) - case 8: - return ctxt.Arch.ByteOrder.Uint64(buf) - default: - panic("unexpected pointer size") - } - -} - -// SetupLocList creates the initial portion of a location list for a -// user variable. It emits the encoded start/end of the range and a -// placeholder for the size. Return value is the new list plus the -// slot in the list holding the size (to be updated later). -func SetupLocList(ctxt *obj.Link, entryID ID, list []byte, st, en ID) ([]byte, int) { - start, startOK := encodeValue(ctxt, entryID, st) - end, endOK := encodeValue(ctxt, entryID, en) - if !startOK || !endOK { - // This could happen if someone writes a function that uses - // >65K values on a 32-bit platform. Hopefully a degraded debugging - // experience is ok in that case. - return nil, 0 - } - list = appendPtr(ctxt, list, start) - list = appendPtr(ctxt, list, end) - - // Where to write the length of the location description once - // we know how big it is. - sizeIdx := len(list) - list = list[:len(list)+2] - return list, sizeIdx -} - // locatePrologEnd walks the entry block of a function with incoming // register arguments and locates the last instruction in the prolog // that spills a register arg. It returns the ID of that instruction, @@ -1832,7 +1720,7 @@ func BuildFuncDebugNoOptimized(ctxt *obj.Link, f *Func, loggingEnabled bool, sta } // Allocate location lists. - rval.LocationLists = make([][]byte, numRegParams+extraForCloCtx) + rval.LocationLists = make([][]LocListEntry, numRegParams+extraForCloCtx) // Locate the value corresponding to the last spill of // an input register. @@ -1909,15 +1797,10 @@ func BuildFuncDebugNoOptimized(ctxt *obj.Link, f *Func, loggingEnabled bool, sta // Param is arriving in one or more registers. We need a 2-element // location expression for it. First entry in location list // will correspond to lifetime in input registers. - list, sizeIdx := SetupLocList(ctxt, f.Entry.ID, rval.LocationLists[pidx], - BlockStart.ID, afterPrologVal) - if list == nil { - pidx++ - continue - } if loggingEnabled { state.logf("param %v:\n [, %d]:\n", n, afterPrologVal) } + var regExpr []byte rtypes, _ := inp.RegisterTypesAndOffsets() padding := make([]uint64, 0, 32) padding = inp.ComputePadding(padding) @@ -1930,56 +1813,60 @@ func BuildFuncDebugNoOptimized(ctxt *obj.Link, f *Func, loggingEnabled bool, sta } dwreg := ctxt.Arch.DWARFRegisters[reg] if dwreg < 32 { - list = append(list, dwarf.DW_OP_reg0+byte(dwreg)) + regExpr = append(regExpr, dwarf.DW_OP_reg0+byte(dwreg)) } else { - list = append(list, dwarf.DW_OP_regx) - list = dwarf.AppendUleb128(list, uint64(dwreg)) + regExpr = append(regExpr, dwarf.DW_OP_regx) + regExpr = dwarf.AppendUleb128(regExpr, uint64(dwreg)) } if loggingEnabled { state.logf(" piece %d -> dwreg %d", k, dwreg) } if len(inp.Registers) > 1 { - list = append(list, dwarf.DW_OP_piece) + regExpr = append(regExpr, dwarf.DW_OP_piece) ts := rtypes[k].Size() - list = dwarf.AppendUleb128(list, uint64(ts)) + regExpr = dwarf.AppendUleb128(regExpr, uint64(ts)) if padding[k] > 0 { if loggingEnabled { state.logf(" [pad %d bytes]", padding[k]) } - list = append(list, dwarf.DW_OP_piece) - list = dwarf.AppendUleb128(list, padding[k]) + regExpr = append(regExpr, dwarf.DW_OP_piece) + regExpr = dwarf.AppendUleb128(regExpr, padding[k]) } } if loggingEnabled { state.logf("\n") } } - // fill in length of location expression element - ctxt.Arch.ByteOrder.PutUint16(list[sizeIdx:], uint16(len(list)-sizeIdx-2)) + rval.LocationLists[pidx] = append(rval.LocationLists[pidx], LocListEntry{ + StartBlock: f.Entry.ID, + StartValue: BlockStart.ID, + EndBlock: f.Entry.ID, + EndValue: afterPrologVal, + Expr: regExpr, + }) // Second entry in the location list will be the stack home // of the param, once it has been spilled. Emit that now. - list, sizeIdx = SetupLocList(ctxt, f.Entry.ID, list, - afterPrologVal, FuncEnd.ID) - if list == nil { - pidx++ - continue - } + var stackExpr []byte soff := stackOffset(sl) if soff == 0 { - list = append(list, dwarf.DW_OP_call_frame_cfa) + stackExpr = append(stackExpr, dwarf.DW_OP_call_frame_cfa) } else { - list = append(list, dwarf.DW_OP_fbreg) - list = dwarf.AppendSleb128(list, int64(soff)) + stackExpr = append(stackExpr, dwarf.DW_OP_fbreg) + stackExpr = dwarf.AppendSleb128(stackExpr, int64(soff)) } if loggingEnabled { state.logf(" [%d, ): stackOffset=%d\n", afterPrologVal, soff) } - // fill in size - ctxt.Arch.ByteOrder.PutUint16(list[sizeIdx:], uint16(len(list)-sizeIdx-2)) + rval.LocationLists[pidx] = append(rval.LocationLists[pidx], LocListEntry{ + StartBlock: f.Entry.ID, + StartValue: afterPrologVal, + EndBlock: f.Entry.ID, + EndValue: FuncEnd.ID, + Expr: stackExpr, + }) - rval.LocationLists[pidx] = list pidx++ } } diff --git a/src/cmd/compile/internal/ssa/debug_lines_test.go b/src/cmd/compile/internal/ssa/debug_lines_test.go index 79dbd91c2fc5c2..5dbfdeb7f6ee4c 100644 --- a/src/cmd/compile/internal/ssa/debug_lines_test.go +++ b/src/cmd/compile/internal/ssa/debug_lines_test.go @@ -45,7 +45,7 @@ func testGoArch() string { func hasRegisterABI() bool { switch testGoArch() { - case "amd64", "arm64", "loong64", "ppc64", "ppc64le", "riscv": + case "amd64", "arm64", "loong64", "ppc64", "ppc64le", "riscv", "s390x": return true } return false diff --git a/src/cmd/compile/internal/ssa/decompose.go b/src/cmd/compile/internal/ssa/decompose.go index cf9285741ed085..6ea69da0169fa3 100644 --- a/src/cmd/compile/internal/ssa/decompose.go +++ b/src/cmd/compile/internal/ssa/decompose.go @@ -13,14 +13,14 @@ import ( // decompose converts phi ops on compound builtin types into phi // ops on simple types, then invokes rewrite rules to decompose // other ops on those types. -func decomposeBuiltIn(f *Func) { +func decomposeBuiltin(f *Func) { // Decompose phis for _, b := range f.Blocks { for _, v := range b.Values { if v.Op != OpPhi { continue } - decomposeBuiltInPhi(v) + decomposeBuiltinPhi(v) } } @@ -100,7 +100,7 @@ func decomposeBuiltIn(f *Func) { } case t.IsFloat(): // floats are never decomposed, even ones bigger than RegSize - case t.Size() > f.Config.RegSize: + case t.Size() > f.Config.RegSize && !t.IsSIMD(): f.Fatalf("undecomposed named type %s %v", name, t) } } @@ -121,7 +121,7 @@ func maybeAppend2(f *Func, ss []*LocalSlot, s1, s2 *LocalSlot) []*LocalSlot { return maybeAppend(f, maybeAppend(f, ss, s1), s2) } -func decomposeBuiltInPhi(v *Value) { +func decomposeBuiltinPhi(v *Value) { switch { case v.Type.IsInteger() && v.Type.Size() > v.Block.Func.Config.RegSize: decomposeInt64Phi(v) @@ -135,7 +135,7 @@ func decomposeBuiltInPhi(v *Value) { decomposeInterfacePhi(v) case v.Type.IsFloat(): // floats are never decomposed, even ones bigger than RegSize - case v.Type.Size() > v.Block.Func.Config.RegSize: + case v.Type.Size() > v.Block.Func.Config.RegSize && !v.Type.IsSIMD(): v.Fatalf("%v undecomposed type %v", v, v.Type) } } @@ -248,7 +248,7 @@ func decomposeUser(f *Func) { for _, name := range f.Names { t := name.Type switch { - case t.IsStruct(): + case isStructNotSIMD(t): newNames = decomposeUserStructInto(f, name, newNames) case t.IsArray(): newNames = decomposeUserArrayInto(f, name, newNames) @@ -266,7 +266,7 @@ func decomposeUser(f *Func) { // returned. func decomposeUserArrayInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*LocalSlot { t := name.Type - if t.NumElem() == 0 { + if t.Size() == 0 { // TODO(khr): Not sure what to do here. Probably nothing. // Names for empty arrays aren't important. return slots @@ -293,7 +293,7 @@ func decomposeUserArrayInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Loc if t.Elem().IsArray() { return decomposeUserArrayInto(f, elemName, slots) - } else if t.Elem().IsStruct() { + } else if isStructNotSIMD(t.Elem()) { return decomposeUserStructInto(f, elemName, slots) } @@ -313,7 +313,7 @@ func decomposeUserStructInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Lo fnames = append(fnames, fs) // arrays and structs will be decomposed further, so // there's no need to record a name - if !fs.Type.IsArray() && !fs.Type.IsStruct() { + if !fs.Type.IsArray() && !isStructNotSIMD(fs.Type) { slots = maybeAppend(f, slots, fs) } } @@ -339,7 +339,7 @@ func decomposeUserStructInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Lo // now that this f.NamedValues contains values for the struct // fields, recurse into nested structs for i := 0; i < n; i++ { - if name.Type.FieldType(i).IsStruct() { + if isStructNotSIMD(name.Type.FieldType(i)) { slots = decomposeUserStructInto(f, fnames[i], slots) delete(f.NamedValues, *fnames[i]) } else if name.Type.FieldType(i).IsArray() { @@ -351,7 +351,7 @@ func decomposeUserStructInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Lo } func decomposeUserPhi(v *Value) { switch { - case v.Type.IsStruct(): + case isStructNotSIMD(v.Type): decomposeStructPhi(v) case v.Type.IsArray(): decomposeArrayPhi(v) @@ -362,10 +362,14 @@ func decomposeUserPhi(v *Value) { // and then recursively decomposes the phis for each field. func decomposeStructPhi(v *Value) { t := v.Type + if t.Size() == 0 { + v.reset(OpEmpty) + return + } n := t.NumFields() - var fields [MaxStruct]*Value + fields := make([]*Value, 0, MaxStruct) for i := 0; i < n; i++ { - fields[i] = v.Block.NewValue0(v.Pos, OpPhi, t.FieldType(i)) + fields = append(fields, v.Block.NewValue0(v.Pos, OpPhi, t.FieldType(i))) } for _, a := range v.Args { for i := 0; i < n; i++ { @@ -373,10 +377,10 @@ func decomposeStructPhi(v *Value) { } } v.reset(OpStructMake) - v.AddArgs(fields[:n]...) + v.AddArgs(fields...) // Recursively decompose phis for each field. - for _, f := range fields[:n] { + for _, f := range fields { decomposeUserPhi(f) } } @@ -385,8 +389,8 @@ func decomposeStructPhi(v *Value) { // and then recursively decomposes the element phi. func decomposeArrayPhi(v *Value) { t := v.Type - if t.NumElem() == 0 { - v.reset(OpArrayMake0) + if t.Size() == 0 { + v.reset(OpEmpty) return } if t.NumElem() != 1 { @@ -458,3 +462,7 @@ func deleteNamedVals(f *Func, toDelete []namedVal) { } f.Names = f.Names[:end] } + +func isStructNotSIMD(t *types.Type) bool { + return t.IsStruct() && !t.IsSIMD() +} diff --git a/src/cmd/compile/internal/ssa/downward_counting_loop.go b/src/cmd/compile/internal/ssa/downward_counting_loop.go new file mode 100644 index 00000000000000..b83997276cbaa0 --- /dev/null +++ b/src/cmd/compile/internal/ssa/downward_counting_loop.go @@ -0,0 +1,166 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "fmt" + +// maybeRewriteLoopToDownwardCountingLoop tries to rewrite the loop to a +// downward counting loop checking against start if the loop body does +// not depend on ind or nxt and end is known before the loop. +// That means this code: +// +// loop: +// ind = (Phi (Const [x]) nxt), +// if ind < end +// then goto enter_loop +// else goto exit_loop +// +// enter_loop: +// do something without using ind nor nxt +// nxt = inc + ind +// goto loop +// +// exit_loop: +// +// is rewritten to: +// +// loop: +// ind = (Phi end nxt) +// if (Const [x]) < ind +// then goto enter_loop +// else goto exit_loop +// +// enter_loop: +// do something without using ind nor nxt +// nxt = ind - inc +// goto loop +// +// exit_loop: +// +// This is better because it only requires to keep ind then nxt alive while looping, +// while the original form keeps ind then nxt and end alive. +// +// If the loop could not be rewritten, it is left unchanged. +func maybeRewriteLoopToDownwardCountingLoop(f *Func, v indVar) { + ind := v.ind + nxt := v.nxt + if !(ind.Uses == 2 && // 2 used by comparison and next + nxt.Uses == 1) { // 1 used by induction + return + } + + start, end := v.min, v.max + + if !start.isGenericIntConst() { + // if start is not a constant we would be winning nothing from inverting the loop + return + } + if end.isGenericIntConst() { + // TODO: if both start and end are constants we should rewrite such that the comparison + // is against zero and nxt is ++ or -- operation + // That means: + // for i := 2; i < 11; i += 2 { + // should be rewritten to: + // for i := 5; 0 < i; i-- { + return + } + + if end.Block == ind.Block { + // we can't rewrite loops where the condition depends on the loop body + // this simple check is forced to work because if this is true a Phi in ind.Block must exist + return + } + + check := v.entry.Preds[0].b.Controls[0] + + neededRoom := -v.step + + // The whole range of safe numbers to land in to stop the loop is shifted by one if the bounds are exclusive. + if neededRoom < 0 && v.flags&indVarMinExc == 1 { + neededRoom++ // safe because it is always against the number's sign + } + if neededRoom > 0 && v.flags&indVarMaxInc == 0 { + neededRoom-- // safe because it is always against the number's sign + } + + switch check.Op { + case OpLess8, OpLess16, OpLess32, OpLess64, OpLeq8, OpLeq16, OpLeq32, OpLeq64: + if _, ok := safeAdd(start.AuxInt, neededRoom, uint(start.Type.Size())*8); !ok { + // We lack sufficient room after start to safely land without an overflow. + // See go.dev/issue/78303 + return + } + case OpLess8U, OpLess16U, OpLess32U, OpLess64U, OpLeq8U, OpLeq16U, OpLeq32U, OpLeq64U: + panic(`parseIndVar didn't yet support unsigned induction variables, this code doesn't yet support them either. +If you are seeing this it is probably because you've fixed https://go.dev/issue/65918. +You need to update this code and add tests then.`) + case OpEq8, OpEq16, OpEq32, OpEq64, OpNeq8, OpNeq16, OpNeq32, OpNeq64: + panic(`parseIndVar didn't yet support induction variables using == or !=. +If you are seeing this it is probably because you've added support for them. +You need to update this code and add tests then.`) + default: + panic(fmt.Sprintf("unreachable; unexpected induction variable comparator %v %v", check, check.Op)) + } + + idxEnd, idxStart := -1, -1 + for i, v := range check.Args { + if v == end { + idxEnd = i + break + } + } + for i, v := range ind.Args { + if v == start { + idxStart = i + break + } + } + if idxEnd < 0 || idxStart < 0 { + return + } + + sdom := f.Sdom() + // the end may not dominate the ind after rewrite, check it first + if !sdom.IsAncestorEq(end.Block, ind.Block) { + return + } + + // swap start and end in the loop + check.SetArg(idxEnd, start) + ind.SetArg(idxStart, end) + + // invert the check + check.Args[0], check.Args[1] = check.Args[1], check.Args[0] + + if nxt.Args[0] != ind { + // unlike additions subtractions are not commutative so be sure we get it right + nxt.Args[0], nxt.Args[1] = nxt.Args[1], nxt.Args[0] + } + + switch nxt.Op { + case OpAdd8: + nxt.Op = OpSub8 + case OpAdd16: + nxt.Op = OpSub16 + case OpAdd32: + nxt.Op = OpSub32 + case OpAdd64: + nxt.Op = OpSub64 + case OpSub8: + nxt.Op = OpAdd8 + case OpSub16: + nxt.Op = OpAdd16 + case OpSub32: + nxt.Op = OpAdd32 + case OpSub64: + nxt.Op = OpAdd64 + default: + panic("unreachable") + } + + if f.pass.debug > 0 { + f.Warnl(ind.Pos, "Inverted loop iteration") + } +} diff --git a/src/cmd/compile/internal/ssa/expand_calls.go b/src/cmd/compile/internal/ssa/expand_calls.go index f6bb863c001798..a28febee937b4f 100644 --- a/src/cmd/compile/internal/ssa/expand_calls.go +++ b/src/cmd/compile/internal/ssa/expand_calls.go @@ -15,7 +15,7 @@ import ( func postExpandCallsDecompose(f *Func) { decomposeUser(f) // redo user decompose to cleanup after expand calls - decomposeBuiltIn(f) // handles both regular decomposition and cleanup. + decomposeBuiltin(f) // handles both regular decomposition and cleanup. } func expandCalls(f *Func) { @@ -70,7 +70,7 @@ func expandCalls(f *Func) { case OpInitMem: m0 = v - case OpClosureLECall, OpInterLECall, OpStaticLECall, OpTailLECall: + case OpClosureLECall, OpInterLECall, OpStaticLECall, OpTailLECall, OpTailLECallInter: calls = append(calls, v) case OpArg: @@ -199,6 +199,8 @@ func expandCalls(f *Func) { rewriteCall(v, OpStaticCall, 0) case OpTailLECall: rewriteCall(v, OpTailCall, 0) + case OpTailLECallInter: + rewriteCall(v, OpTailCallInter, 1) case OpClosureLECall: rewriteCall(v, OpClosureCall, 2) case OpInterLECall: @@ -280,7 +282,7 @@ func (x *expandState) rewriteCallArgs(v *Value, firstArg int) { argsWithoutMem := v.Args[firstArg : len(v.Args)-1] // Also strip closure/interface Op-specific args sp := x.sp - if v.Op == OpTailLECall { + if v.Op == OpTailLECall || v.Op == OpTailLECallInter { // For tail call, we unwind the frame before the call so we'll use the caller's // SP. sp = v.Block.NewValue1(src.NoXPos, OpGetCallerSP, x.typs.Uintptr, mem) @@ -396,6 +398,9 @@ func (x *expandState) decomposeAsNecessary(pos src.XPos, b *Block, a, m0 *Value, return mem case types.TSTRUCT: + if at.IsSIMD() { + break // XXX + } for i := 0; i < at.NumFields(); i++ { et := at.Field(i).Type // might need to read offsets from the fields e := b.NewValue1I(pos, OpStructSelect, et, int64(i), a) @@ -423,7 +428,14 @@ func (x *expandState) decomposeAsNecessary(pos src.XPos, b *Block, a, m0 *Value, if a.Op == OpIMake { data := a.Args[1] for data.Op == OpStructMake || data.Op == OpArrayMake1 { - data = data.Args[0] + // A struct make might have a few zero-sized fields. + // Use the pointer-y one we know is there. + for _, a := range data.Args { + if a.Type.Size() > 0 { + data = a + break + } + } } return x.decomposeAsNecessary(pos, b, data, mem, rc.next(data.Type)) } @@ -498,13 +510,7 @@ func (x *expandState) rewriteSelectOrArg(pos src.XPos, b *Block, container, a, m if at.Size() == 0 { // For consistency, create these values even though they'll ultimately be unused - if at.IsArray() { - return makeOf(a, OpArrayMake0, nil) - } - if at.IsStruct() { - return makeOf(a, OpStructMake, nil) - } - return a + return makeOf(a, OpEmpty, nil) } sk := selKey{from: container, size: 0, offsetOrIndex: rc.storeOffset, typ: at} @@ -544,6 +550,9 @@ func (x *expandState) rewriteSelectOrArg(pos src.XPos, b *Block, container, a, m case types.TSTRUCT: // Assume ssagen/ssa.go (in buildssa) spills large aggregates so they won't appear here. + if at.IsSIMD() { + break // XXX + } for i := 0; i < at.NumFields(); i++ { et := at.Field(i).Type e := x.rewriteSelectOrArg(pos, b, container, nil, m0, et, rc.next(et)) @@ -553,7 +562,7 @@ func (x *expandState) rewriteSelectOrArg(pos src.XPos, b *Block, container, a, m addArg(e) pos = pos.WithNotStmt() } - if at.NumFields() > 4 { + if at.NumFields() > MaxStruct && !types.IsDirectIface(at) { panic(fmt.Errorf("Too many fields (%d, %d bytes), container=%s", at.NumFields(), at.Size(), container.LongString())) } a = makeOf(a, OpStructMake, args) @@ -710,6 +719,9 @@ func (x *expandState) rewriteWideSelectToStores(pos src.XPos, b *Block, containe case types.TSTRUCT: // Assume ssagen/ssa.go (in buildssa) spills large aggregates so they won't appear here. + if at.IsSIMD() { + break // XXX + } for i := 0; i < at.NumFields(); i++ { et := at.Field(i).Type m0 = x.rewriteWideSelectToStores(pos, b, container, m0, et, rc.next(et)) @@ -951,7 +963,7 @@ func (x *expandState) indent(n int) { } // Printf does an indented fmt.Printf on the format and args. -func (x *expandState) Printf(format string, a ...interface{}) (n int, err error) { +func (x *expandState) Printf(format string, a ...any) (n int, err error) { if x.indentLevel > 0 { fmt.Printf("%[1]*s", x.indentLevel, "") } diff --git a/src/cmd/compile/internal/ssa/export_test.go b/src/cmd/compile/internal/ssa/export_test.go index c33c77f891cc53..3ab0be7311338c 100644 --- a/src/cmd/compile/internal/ssa/export_test.go +++ b/src/cmd/compile/internal/ssa/export_test.go @@ -98,12 +98,12 @@ func (TestFrontend) UseWriteBarrier() bool { return true // only writebarrier_test cares } -func (d TestFrontend) Logf(msg string, args ...interface{}) { d.t.Logf(msg, args...) } -func (d TestFrontend) Log() bool { return true } +func (d TestFrontend) Logf(msg string, args ...any) { d.t.Logf(msg, args...) } +func (d TestFrontend) Log() bool { return true } -func (d TestFrontend) Fatalf(_ src.XPos, msg string, args ...interface{}) { d.t.Fatalf(msg, args...) } -func (d TestFrontend) Warnl(_ src.XPos, msg string, args ...interface{}) { d.t.Logf(msg, args...) } -func (d TestFrontend) Debug_checknil() bool { return false } +func (d TestFrontend) Fatalf(_ src.XPos, msg string, args ...any) { d.t.Fatalf(msg, args...) } +func (d TestFrontend) Warnl(_ src.XPos, msg string, args ...any) { d.t.Logf(msg, args...) } +func (d TestFrontend) Debug_checknil() bool { return false } func (d TestFrontend) Func() *ir.Func { return d.f diff --git a/src/cmd/compile/internal/ssa/func.go b/src/cmd/compile/internal/ssa/func.go index fc8cb3f2fef0af..1c67691547a99c 100644 --- a/src/cmd/compile/internal/ssa/func.go +++ b/src/cmd/compile/internal/ssa/func.go @@ -36,11 +36,13 @@ type Func struct { HTMLWriter *HTMLWriter // html writer, for debugging PrintOrHtmlSSA bool // true if GOSSAFUNC matches, true even if fe.Log() (spew phase results to stdout) is false. There's an odd dependence on this in debug.go for method logf. ruleMatches map[string]int // number of times countRule was called during compilation for any given string - ABI0 *abi.ABIConfig // A copy, for no-sync access - ABI1 *abi.ABIConfig // A copy, for no-sync access + ABI0 *abi.ABIConfig // ABI configuration for ABI0 + ABI1 *abi.ABIConfig // ABI configuration for ABIInternal ABISelf *abi.ABIConfig // ABI for function being compiled ABIDefault *abi.ABIConfig // ABI for rtcall and other no-parsed-signature/pragma functions. + maxCPUFeatures CPUfeatures // union of all the CPU features in all the blocks. + scheduled bool // Values in Blocks are in final order laidout bool // Blocks are ordered NoSplit bool // true if function is marked as nosplit. Used by schedule check pass. @@ -336,7 +338,7 @@ func (f *Func) newValueNoBlock(op Op, t *types.Type, pos src.XPos) *Value { // context to allow item-by-item comparisons across runs. // For example: // awk 'BEGIN {FS="\t"} $3~/TIME/{sum+=$4} END{print "t(ns)=",sum}' t.log -func (f *Func) LogStat(key string, args ...interface{}) { +func (f *Func) LogStat(key string, args ...any) { value := "" for _, a := range args { value += fmt.Sprintf("\t%v", a) @@ -632,6 +634,19 @@ func (b *Block) NewValue4(pos src.XPos, op Op, t *types.Type, arg0, arg1, arg2, return v } +// NewValue4A returns a new value in the block with four arguments and zero aux values. +func (b *Block) NewValue4A(pos src.XPos, op Op, t *types.Type, aux Aux, arg0, arg1, arg2, arg3 *Value) *Value { + v := b.Func.newValue(op, t, b, pos) + v.AuxInt = 0 + v.Aux = aux + v.Args = []*Value{arg0, arg1, arg2, arg3} + arg0.Uses++ + arg1.Uses++ + arg2.Uses++ + arg3.Uses++ + return v +} + // NewValue4I returns a new value in the block with four arguments and auxint value. func (b *Block) NewValue4I(pos src.XPos, op Op, t *types.Type, auxint int64, arg0, arg1, arg2, arg3 *Value) *Value { v := b.Func.newValue(op, t, b, pos) @@ -729,12 +744,12 @@ func (f *Func) ConstOffPtrSP(t *types.Type, c int64, sp *Value) *Value { return v } -func (f *Func) Frontend() Frontend { return f.fe } -func (f *Func) Warnl(pos src.XPos, msg string, args ...interface{}) { f.fe.Warnl(pos, msg, args...) } -func (f *Func) Logf(msg string, args ...interface{}) { f.fe.Logf(msg, args...) } -func (f *Func) Log() bool { return f.fe.Log() } +func (f *Func) Frontend() Frontend { return f.fe } +func (f *Func) Warnl(pos src.XPos, msg string, args ...any) { f.fe.Warnl(pos, msg, args...) } +func (f *Func) Logf(msg string, args ...any) { f.fe.Logf(msg, args...) } +func (f *Func) Log() bool { return f.fe.Log() } -func (f *Func) Fatalf(msg string, args ...interface{}) { +func (f *Func) Fatalf(msg string, args ...any) { stats := "crashed" if f.Log() { f.Logf(" pass %s end %s\n", f.pass.name, stats) diff --git a/src/cmd/compile/internal/ssa/func_test.go b/src/cmd/compile/internal/ssa/func_test.go index 4639d674e145fa..479186b34d8db0 100644 --- a/src/cmd/compile/internal/ssa/func_test.go +++ b/src/cmd/compile/internal/ssa/func_test.go @@ -206,7 +206,7 @@ func (c *Conf) Fun(entry string, blocs ...bloc) fun { // Bloc defines a block for Fun. The bloc name should be unique // across the containing Fun. entries should consist of calls to valu, // as well as one call to Goto, If, or Exit to specify the block kind. -func Bloc(name string, entries ...interface{}) bloc { +func Bloc(name string, entries ...any) bloc { b := bloc{} b.name = name seenCtrl := false @@ -260,6 +260,11 @@ func Eq(cond, sub, alt string) ctrl { return ctrl{BlockAMD64EQ, cond, []string{sub, alt}} } +// Lt specifies a BlockAMD64LT. +func Lt(cond, yes, no string) ctrl { + return ctrl{BlockAMD64LT, cond, []string{yes, no}} +} + // bloc, ctrl, and valu are internal structures used by Bloc, Valu, Goto, // If, and Exit to help define blocks. diff --git a/src/cmd/compile/internal/ssa/fuse.go b/src/cmd/compile/internal/ssa/fuse.go index 0cee91b532b101..e95064c1df2eeb 100644 --- a/src/cmd/compile/internal/ssa/fuse.go +++ b/src/cmd/compile/internal/ssa/fuse.go @@ -10,7 +10,9 @@ import ( ) // fuseEarly runs fuse(f, fuseTypePlain|fuseTypeIntInRange|fuseTypeNanCheck). -func fuseEarly(f *Func) { fuse(f, fuseTypePlain|fuseTypeIntInRange|fuseTypeNanCheck) } +func fuseEarly(f *Func) { + fuse(f, fuseTypePlain|fuseTypeIntInRange|fuseTypeSingleBitDifference|fuseTypeNanCheck) +} // fuseLate runs fuse(f, fuseTypePlain|fuseTypeIf|fuseTypeBranchRedirect). func fuseLate(f *Func) { fuse(f, fuseTypePlain|fuseTypeIf|fuseTypeBranchRedirect) } @@ -21,6 +23,7 @@ const ( fuseTypePlain fuseType = 1 << iota fuseTypeIf fuseTypeIntInRange + fuseTypeSingleBitDifference fuseTypeNanCheck fuseTypeBranchRedirect fuseTypeShortCircuit @@ -41,6 +44,9 @@ func fuse(f *Func, typ fuseType) { if typ&fuseTypeIntInRange != 0 { changed = fuseIntInRange(b) || changed } + if typ&fuseTypeSingleBitDifference != 0 { + changed = fuseSingleBitDifference(b) || changed + } if typ&fuseTypeNanCheck != 0 { changed = fuseNanCheck(b) || changed } diff --git a/src/cmd/compile/internal/ssa/fuse_comparisons.go b/src/cmd/compile/internal/ssa/fuse_comparisons.go index b6eb8fcb90dfbc..898c0344853e3c 100644 --- a/src/cmd/compile/internal/ssa/fuse_comparisons.go +++ b/src/cmd/compile/internal/ssa/fuse_comparisons.go @@ -19,6 +19,14 @@ func fuseNanCheck(b *Block) bool { return fuseComparisons(b, canOptNanCheck) } +// fuseSingleBitDifference replaces the short-circuit operators between equality checks with +// constants that only differ by a single bit. For example, it would convert +// `if x == 4 || x == 6 { ... }` into `if (x == 4) | (x == 6) { ... }`. Rewrite rules can +// then optimize these using a bitwise operation, in this case generating `if x|2 == 6 { ... }`. +func fuseSingleBitDifference(b *Block) bool { + return fuseComparisons(b, canOptSingleBitDifference) +} + // fuseComparisons looks for control graphs that match this pattern: // // p - predecessor @@ -229,3 +237,40 @@ func canOptNanCheck(x, y *Value, op Op) bool { } return false } + +// canOptSingleBitDifference returns true if x op y matches either: +// +// v == c || v == d +// v != c && v != d +// +// Where c and d are constant values that differ by a single bit. +func canOptSingleBitDifference(x, y *Value, op Op) bool { + if x.Op != y.Op { + return false + } + switch x.Op { + case OpEq64, OpEq32, OpEq16, OpEq8: + if op != OpOrB { + return false + } + case OpNeq64, OpNeq32, OpNeq16, OpNeq8: + if op != OpAndB { + return false + } + default: + return false + } + + xi := getConstIntArgIndex(x) + if xi < 0 { + return false + } + yi := getConstIntArgIndex(y) + if yi < 0 { + return false + } + if x.Args[xi^1] != y.Args[yi^1] { + return false + } + return oneBit(x.Args[xi].AuxInt ^ y.Args[yi].AuxInt) +} diff --git a/src/cmd/compile/internal/ssa/html.go b/src/cmd/compile/internal/ssa/html.go index 85a414f31e59f9..7a6683e9f01542 100644 --- a/src/cmd/compile/internal/ssa/html.go +++ b/src/cmd/compile/internal/ssa/html.go @@ -53,13 +53,13 @@ func NewHTMLWriter(path string, f *Func, cfgMask string) *HTMLWriter { } // Fatalf reports an error and exits. -func (w *HTMLWriter) Fatalf(msg string, args ...interface{}) { +func (w *HTMLWriter) Fatalf(msg string, args ...any) { fe := w.Func.Frontend() fe.Fatalf(src.NoXPos, msg, args...) } // Logf calls the (w *HTMLWriter).Func's Logf method passing along a msg and args. -func (w *HTMLWriter) Logf(msg string, args ...interface{}) { +func (w *HTMLWriter) Logf(msg string, args ...any) { w.Func.Logf(msg, args...) } @@ -945,7 +945,7 @@ func (w *HTMLWriter) WriteMultiTitleColumn(phase string, titles []string, class, w.WriteString("\n") } -func (w *HTMLWriter) Printf(msg string, v ...interface{}) { +func (w *HTMLWriter) Printf(msg string, v ...any) { if _, err := fmt.Fprintf(w.w, msg, v...); err != nil { w.Fatalf("%v", err) } diff --git a/src/cmd/compile/internal/ssa/known_bits.go b/src/cmd/compile/internal/ssa/known_bits.go new file mode 100644 index 00000000000000..2d94ac72a1155d --- /dev/null +++ b/src/cmd/compile/internal/ssa/known_bits.go @@ -0,0 +1,359 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "slices" + "strings" +) + +func (kb *knownBitsState) fold(v *Value) (value, known int64) { + if kb.seenValues.Test(uint32(v.ID)) { + return kb.entries[v.ID].value, kb.entries[v.ID].known + } + defer func() { + // maintain the invariants: + // 3. booleans are stored as 1 byte values who are either 0 or 1. + if v.Type.IsBoolean() { + value &= 1 + known |= ^1 + } + + // 2. all values are sign-extended to int64 (inspired by RISC-V's xlen=64) + switch v.Type.Size() { + case 1: + value = int64(int8(value)) + known = int64(int8(known)) + case 2: + value = int64(int16(value)) + known = int64(int16(known)) + case 4: + value = int64(int32(value)) + known = int64(int32(known)) + case 8: + default: + panic("unreachable; unknown integer size") + } + + // 1. unknown bits are always set to 0 inside value + value &= known + + kb.entries[v.ID].known = known + kb.entries[v.ID].value = value + if v.Block.Func.pass.debug > 1 { + v.Block.Func.Warnl(v.Pos, "known bits state %v: %v", v, kb.entries[v.ID]) + } + }() + kb.seenValues.Set(uint32(v.ID)) // set seen early to give up on loops + + switch v.Op { + // TODO: rotates, ... + case OpConst64, OpConst32, OpConst16, OpConst8, OpConstBool: + return v.AuxInt, -1 + case OpAnd64, OpAnd32, OpAnd16, OpAnd8, OpAndB: + x, xk := kb.fold(v.Args[0]) + y, yk := kb.fold(v.Args[1]) + onesInBoth := x & y + zerosInX := ^x & xk + zerosInY := ^y & yk + return x & y, onesInBoth | zerosInX | zerosInY + case OpOr64, OpOr32, OpOr16, OpOr8, OpOrB: + x, xk := kb.fold(v.Args[0]) + y, yk := kb.fold(v.Args[1]) + zerosInBoth := ^x & ^y & (xk & yk) + onesInX := x + onesInY := y + return x | y, onesInX | onesInY | zerosInBoth + case OpXor64, OpXor32, OpXor16, OpXor8: + x, xk := kb.fold(v.Args[0]) + y, yk := kb.fold(v.Args[1]) + return x ^ y, xk & yk + case OpCom64, OpCom32, OpCom16, OpCom8, OpNot: + x, xk := kb.fold(v.Args[0]) + return ^x, xk + case OpPhi: + set := false + for i, arg := range v.Args { + if !kb.isLiveInEdge(v.Block, uint(i)) { + continue + } + a, k := kb.fold(arg) + if !set { + value, known = a, k + set = true + } else { + known &^= value ^ a + known &= k + } + if known == 0 { + break + } + } + return value, known + case OpCopy, OpCvtBoolToUint8, + OpSignExt8to16, OpSignExt8to32, OpSignExt8to64, OpSignExt16to32, OpSignExt16to64, OpSignExt32to64, + // The defer block handles maintaining the sign-extension invariant using v.Type.Size() + // thus we can just pass Truncs as-is. + OpTrunc64to32, OpTrunc64to16, OpTrunc64to8, OpTrunc32to16, OpTrunc32to8, OpTrunc16to8: + return kb.fold(v.Args[0]) + case OpEq64, OpEq32, OpEq16, OpEq8, OpEqB: + x, xk := kb.fold(v.Args[0]) + y, yk := kb.fold(v.Args[1]) + differentBits := x ^ y + if differentBits&xk&yk != 0 { + return 0, -1 + } + if xk == -1 && yk == -1 { + return boolToAuxInt(x == y), -1 + } + return 0, -1 << 1 + case OpNeq64, OpNeq32, OpNeq16, OpNeq8, OpNeqB: + x, xk := kb.fold(v.Args[0]) + y, yk := kb.fold(v.Args[1]) + differentBits := x ^ y + if differentBits&xk&yk != 0 { + return 1, -1 + } + if xk == -1 && yk == -1 { + return boolToAuxInt(x != y), -1 + } + return 0, -1 << 1 + case OpZeroExt8to16, OpZeroExt8to32, OpZeroExt8to64, OpZeroExt16to32, OpZeroExt16to64, OpZeroExt32to64: + x, k := kb.fold(v.Args[0]) + srcSize := v.Args[0].Type.Size() * 8 + mask := int64(1<> shift), int64(uint64(xk)>>shift | (^uint64(0) << (64 - shift))) + }) + case OpRsh8x8, OpRsh16x8, OpRsh32x8, OpRsh64x8, + OpRsh8x16, OpRsh16x16, OpRsh32x16, OpRsh64x16, + OpRsh8x32, OpRsh16x32, OpRsh32x32, OpRsh64x32, + OpRsh8x64, OpRsh16x64, OpRsh32x64, OpRsh64x64: + return kb.computeKnownBitsForShift(v, func(x, xk, xSize, shift int64) (value, known int64) { + return x >> shift, xk >> shift + }) + default: + return 0, 0 + } +} + +// knownBits does constant folding across bitfields +func knownBits(f *Func) { + kb := &knownBitsState{ + entries: f.Cache.allocKnownBitsEntriesSlice(f.NumValues()), + seenValues: f.Cache.allocBitset(f.NumValues()), + reachableBlocks: f.Cache.allocBitset(f.NumBlocks()), + } + defer f.Cache.freeKnownBitsEntriesSlice(kb.entries) + defer f.Cache.freeBitset(kb.seenValues) + defer f.Cache.freeBitset(kb.reachableBlocks) + clear(kb.seenValues) + clear(kb.entries) + clear(kb.reachableBlocks) + + blocks := f.postorder() + for _, b := range blocks { + kb.reachableBlocks.Set(uint32(b.ID)) + } + + for _, b := range slices.Backward(blocks) { + for _, v := range b.Values { + if v.Uses == 0 || !(v.Type.IsInteger() || v.Type.IsBoolean()) { + continue + } + switch v.Op { + case OpConst64, OpConst32, OpConst16, OpConst8, OpConstBool: + continue + } + val, k := kb.fold(v) + if k != -1 { + continue + } + if f.pass.debug > 0 { + var pval any = val + if v.Type.IsBoolean() { + pval = val != 0 + } + f.Warnl(v.Pos, "known value of %v (%v): %v", v, v.Op, pval) + } + var c *Value + switch v.Type.Size() { + case 1: + if v.Type.IsBoolean() { + c = f.ConstBool(v.Type, val != 0) + break + } + c = f.ConstInt8(v.Type, int8(val)) + case 2: + c = f.ConstInt16(v.Type, int16(val)) + case 4: + c = f.ConstInt32(v.Type, int32(val)) + case 8: + c = f.ConstInt64(v.Type, val) + default: + panic("unreachable; unknown integer size") + } + v.copyOf(c) + } + } +} + +type knownBitsState struct { + entries []knownBitsEntry // indexed by Value.ID + seenValues bitset // indexed by Value.ID (at the bit level) + reachableBlocks bitset // indexed by Block.ID (at the bit level) +} + +type knownBitsEntry struct { + // Two invariants: + // 1. unknown bits are always set to 0 inside value + // 2. all values are sign-extended to int64 (inspired by RISC-V's xlen=64) + // This means let's say you know an 8 bits value is 0b10??????, + // known = int64(int8(0b11000000)) + // value = int64(int8(0b10000000)) + // 3. booleans are stored as 1 byte values who are either 0 or 1. + known, value int64 +} + +func (kbe knownBitsEntry) String() string { + lut := []rune{ // indexed by knownBit<<1 | valueBit + 0b00: '?', + 0b01: '¿', // violates invariant 1 + 0b10: '0', + 0b11: '1', + } + var sb strings.Builder + sb.Grow(64) + for i := 63; i >= 0; i-- { + bits := (kbe.known>>i&1)<<1 | (kbe.value >> i & 1) + sb.WriteRune(lut[bits]) + } + return sb.String() +} + +func (kb *knownBitsState) isLiveInEdge(b *Block, index uint) bool { + inEdge := b.Preds[index] + return kb.isLiveOutEdge(inEdge.b, uint(inEdge.i)) +} + +func (kb *knownBitsState) isLiveOutEdge(b *Block, index uint) bool { + if !kb.reachableBlocks.Test(uint32(b.ID)) { + return false + } + + switch b.Kind { + case BlockFirst: + return index == 0 + case BlockPlain, BlockIf, BlockDefer, BlockRet, BlockRetJmp, BlockExit, BlockJumpTable: + return true + default: + panic("unreachable; unknown block kind") + } +} + +// computeKnownBitsForShift computes the known bits for a shift operation. +// Considering the following piece of code x = x << uint8(i) +// The algorithm is based on two observations: +// +// 1. computing a shift of a lattice by a constant (i) is easy: +// value, known = x<= uint64(xSize) { + return doShiftByAConst(x, xk, xSize, 64) + } + + set := false + if v.AuxInt == 0 && uint64(^yk) >= uint64(xSize) { + // this implement the default case of the equivalent switch above. + // if the shift isn't bounded and there are unknown bits above the shift size we might completely stomp all bits. + + value, known = doShiftByAConst(x, xk, xSize, 64) + set = true + } + + yk |= ^(xSize - 1) + + for i := range allPossibleValues(y, yk) { + a, k := doShiftByAConst(x, xk, xSize, i) + if !set { + value, known = a, k + set = true + } else { + known &^= value ^ a + known &= k + } + if known == 0 { + break + } + } + + return value & known, known +} + +// allPossibleValues iterates over all values that could exist. +// It scales exponentially with the number of unknown bits, +// the exact number of iterations will be uint128(1)< header | +// | | | +// | +-------+------+ +// | | +// | | +// | +-------v------+ +// | | | +// +------+ loop body | +// | | +// +--------------+ +// +// +// We consider all phis and memory operations as initial loop dependent set. +// So loop independent values are all loop values, +// minus transitive closure of initial loop dependent values. +// We remove those values from their BBs and move them to preheader. + +func licm(f *Func) { + // See likelyadjust.go for details about loop info. + nest := loopnestfor(f) + if len(nest.loops) == 0 || nest.hasIrreducible { + return + } + + uses := uses(f) + defer uses.free(f) + + loopDependent := f.Cache.allocBoolSlice(f.NumValues()) + defer f.Cache.freeBoolSlice(loopDependent) + queue := f.Cache.allocValueSlice(f.NumValues()) + defer f.Cache.freeValueSlice(queue) + queue = queue[:0] + + // Start with all values we can't move out of loops. + for _, b := range f.Blocks { + if loop := nest.b2l[b.ID]; loop == nil || !loop.isInner { + // Values outside any loop we don't care about. + // Values not in a leaf loop we can't handle. + continue + } + for _, v := range b.Values { + if opcodeTable[v.Op].earlyOk { + // Double check we didn't mark the wrong ops as earlyOk + if v.Type.IsMemory() || opcodeTable[v.Op].nilCheck || opcodeTable[v.Op].hasSideEffects || v.MemoryArg() != nil { + v.Fatalf("op %s has bad earlyOk mark", v.Op) + } + if !v.Type.IsPtr() { + // Note: can't move pointer arithmetic, as it may be guarded by conditionals + // and thus could materialize a bad pointer across a safepoint. + + continue // Ok to lift out of loop. + } + } + if v.Op == OpSelect0 || v.Op == OpSelect1 { + // These ops can (and must) move with the op they are selecting from. + continue + } + loopDependent[v.ID] = true + queue = append(queue, v) + } + } + + // If a value can't be moved out of a loop, neither can its users. + // The queue contains values which are loop dependent, but their users + // have not been marked as loop dependent yet. + for len(queue) > 0 { + v := queue[len(queue)-1] + queue = queue[:len(queue)-1] + + for _, u := range uses.get(v) { + if loop := nest.b2l[u.Block.ID]; loop == nil || !loop.isInner { + continue // see above + } + if loopDependent[u.ID] { + continue + } + loopDependent[u.ID] = true + queue = append(queue, u) + } + } + + // Anything not marked as loop-dependent can be moved out of its loop. + for _, b := range f.Blocks { + loop := nest.b2l[b.ID] + if loop == nil || !loop.isInner { + // loopDependent check is wrong for loops containing other loops, + // because then a value might have an argument computed inside + // a nested loop. + continue + } + if len(loop.header.Preds) != 2 { + continue // is never true? + } + anyMoved := false + for i, v := range b.Values { + if loopDependent[v.ID] { + continue + } + // Figure out where to move loop-independent values. + h := loop.header + var inIdx int + if int(h.Preds[0].b.ID) >= len(nest.b2l) || nest.b2l[h.Preds[0].b.ID] != loop { + inIdx = 0 + } else { + inIdx = 1 + } + dest := h.Preds[inIdx].b + if dest.Kind != BlockPlain { + outIdx := h.Preds[inIdx].i + // Introduce a new block between the loop + // header predecessor and the loop header itself. + mid := f.NewBlock(BlockPlain) + mid.Pos = dest.Pos + // Splice into graph. + mid.Preds = append(mid.Preds, Edge{dest, outIdx}) + mid.Succs = append(mid.Succs, Edge{h, inIdx}) + h.Preds[inIdx] = Edge{mid, 0} + dest.Succs[outIdx] = Edge{mid, 0} + + dest = mid + } + + b.Values[i] = nil + v.Block = dest + dest.Values = append(dest.Values, v) + anyMoved = true + } + if anyMoved { + // We just nil'd entries in b.Values above. Compact out the nils. + i := 0 + for _, v := range b.Values { + if v == nil { + continue + } + b.Values[i] = v + i++ + } + b.Values = b.Values[:i] + } + } +} diff --git a/src/cmd/compile/internal/ssa/licm_test.go b/src/cmd/compile/internal/ssa/licm_test.go new file mode 100644 index 00000000000000..1f23c1eead9a06 --- /dev/null +++ b/src/cmd/compile/internal/ssa/licm_test.go @@ -0,0 +1,69 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "cmd/compile/internal/types" + "testing" +) + +func TestLICM(t *testing.T) { + c := testConfig(t) + fun := c.Fun("entry", + Bloc("entry", + Valu("mem", OpInitMem, types.TypeMem, 0, nil), + Valu("sp", OpSP, c.config.Types.Uintptr, 0, nil), + Valu("a", OpConst64, c.config.Types.Int64, 14, nil), + Goto("loop")), + Bloc("loop", + Valu("b", OpAMD64MOVQconst, c.config.Types.Int64, 26, nil), + Valu("sum", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "a", "b"), + Valu("load", OpLoad, c.config.Types.BytePtr, 0, nil, "sp", "mem"), + Valu("nilptr", OpConstNil, c.config.Types.BytePtr, 0, nil), + Valu("bool", OpNeqPtr, c.config.Types.Bool, 0, nil, "load", "nilptr"), + If("bool", "loop", "exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + licm(fun.f) + CheckFunc(fun.f) + + b := fun.blocks["entry"] + if len(b.Values) != 5 { + // b,sum should have been moved from loop to entry + t.Errorf("loop invariant code wasn't lifted, but should have") + } +} + +func TestLICMNewBlock(t *testing.T) { + c := testConfig(t) + fun := c.Fun("entry", + Bloc("entry", + Valu("mem", OpInitMem, types.TypeMem, 0, nil), + Valu("sp", OpSP, c.config.Types.Uintptr, 0, nil), + Valu("a", OpConst64, c.config.Types.Int64, 14, nil), + Valu("bool2", OpConstBool, c.config.Types.Bool, 0, nil), + If("bool2", "loop", "exit")), + Bloc("loop", + Valu("b", OpAMD64MOVQconst, c.config.Types.Int64, 26, nil), + Valu("sum", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "a", "b"), + Valu("load", OpLoad, c.config.Types.BytePtr, 0, nil, "sp", "mem"), + Valu("nilptr", OpConstNil, c.config.Types.BytePtr, 0, nil), + Valu("bool", OpNeqPtr, c.config.Types.Bool, 0, nil, "load", "nilptr"), + If("bool", "loop", "exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + licm(fun.f) + CheckFunc(fun.f) + + b := fun.blocks["entry"].Succs[0].b + if len(b.Values) != 2 { + // b,sum should have been moved from loop to new block between entry & loop + t.Errorf("loop invariant code wasn't lifted, but should have") + } +} diff --git a/src/cmd/compile/internal/ssa/loopbce.go b/src/cmd/compile/internal/ssa/loopbce.go index aa6cc48cacbbe7..b3702d887527c4 100644 --- a/src/cmd/compile/internal/ssa/loopbce.go +++ b/src/cmd/compile/internal/ssa/loopbce.go @@ -13,9 +13,8 @@ import ( type indVarFlags uint8 const ( - indVarMinExc indVarFlags = 1 << iota // minimum value is exclusive (default: inclusive) - indVarMaxInc // maximum value is inclusive (default: exclusive) - indVarCountDown // if set the iteration starts at max and count towards min (default: min towards max) + indVarMinExc indVarFlags = 1 << iota // minimum value is exclusive (default: inclusive) + indVarMaxInc // maximum value is inclusive (default: exclusive) ) type indVar struct { @@ -23,9 +22,10 @@ type indVar struct { nxt *Value // the incremented variable min *Value // minimum value, inclusive/exclusive depends on flags max *Value // maximum value, inclusive/exclusive depends on flags - entry *Block // entry block in the loop. + entry *Block // the block where the edge from the succeeded comparison of the induction variable goes to, means when the bound check has passed. + step int64 // it will always be positive. flags indVarFlags - // Invariant: for all blocks strictly dominated by entry: + // Invariant: for all blocks dominated by entry: // min <= ind < max [if flags == 0] // min < ind < max [if flags == indVarMinExc] // min <= ind <= max [if flags == indVarMaxInc] @@ -83,259 +83,296 @@ func parseIndVar(ind *Value) (min, inc, nxt *Value, loopReturn Edge) { // goto loop // // exit_loop: +// +// We may have more than one induction variables, the loop in the go +// source code may looks like this: +// +// for i >= 0 && j >= 0 { +// // use i and j +// i-- +// j-- +// } +// +// So, also look for variables and blocks that satisfy the following +// +// loop: +// i = (Phi maxi nxti) +// j = (Phi maxj nxtj) +// if i >= mini +// then goto check_j +// else goto exit_loop +// +// check_j: +// if j >= minj +// then goto enter_loop +// else goto exit_loop +// +// enter_loop: +// do something +// nxti = i - di +// nxtj = j - dj +// goto loop +// +// exit_loop: func findIndVar(f *Func) []indVar { var iv []indVar sdom := f.Sdom() +nextblock: for _, b := range f.Blocks { - if b.Kind != BlockIf || len(b.Preds) != 2 { + if b.Kind != BlockIf { continue } - - var ind *Value // induction variable - var init *Value // starting value - var limit *Value // ending value - - // Check that the control if it either ind = 0; i-- - init, inc, nxt, loopReturn = parseIndVar(limit) + less := idx == 0 + // induction variable, ending value + ind, limit := c.Args[idx], c.Args[1-idx] + // starting value, increment value, next value, loop return edge + init, inc, nxt, loopReturn := parseIndVar(ind) if init == nil { - // No recognized induction variable on either operand - continue + continue // this is not an induction variable } - // Ok, the arguments were reversed. Swap them, and remember that we're - // looking at an ind >/>= loop (so the induction must be decrementing). - ind, limit = limit, ind - less = false - } - - if ind.Block != b { - // TODO: Could be extended to include disjointed loop headers. - // I don't think this is causing missed optimizations in real world code often. - // See https://go.dev/issue/63955 - continue - } + // This is ind.Block.Preds, not b.Preds. That's a restriction on the loop header, + // not the comparison block. + if len(ind.Block.Preds) != 2 { + continue + } - // Expect the increment to be a nonzero constant. - if !inc.isGenericIntConst() { - continue - } - step := inc.AuxInt - if step == 0 { - continue - } + // Expect the increment to be a nonzero constant. + if !inc.isGenericIntConst() { + continue + } + step := inc.AuxInt + if step == 0 { + continue + } + // step == minInt64 cannot be safely negated below, because -step + // overflows back to minInt64. The later underflow checks need a + // positive magnitude, so reject this case here. + if step == minSignedValue(ind.Type) { + continue + } - // startBody is the edge that eventually returns to the loop header. - var startBody Edge - switch { - case sdom.IsAncestorEq(b.Succs[0].b, loopReturn.b): - startBody = b.Succs[0] - case sdom.IsAncestorEq(b.Succs[1].b, loopReturn.b): - // if x { goto exit } else { goto entry } is identical to if !x { goto entry } else { goto exit } - startBody = b.Succs[1] - less = !less - inclusive = !inclusive - default: - continue - } + // startBody is the edge that eventually returns to the loop header. + var startBody Edge + switch { + case sdom.IsAncestorEq(b.Succs[0].b, loopReturn.b): + startBody = b.Succs[0] + case sdom.IsAncestorEq(b.Succs[1].b, loopReturn.b): + // if x { goto exit } else { goto entry } is identical to if !x { goto entry } else { goto exit } + startBody = b.Succs[1] + less = !less + inclusive = !inclusive + default: + continue + } - // Increment sign must match comparison direction. - // When incrementing, the termination comparison must be ind />= limit. - // See issue 26116. - if step > 0 && !less { - continue - } - if step < 0 && less { - continue - } + // Increment sign must match comparison direction. + // When incrementing, the termination comparison must be ind />= limit. + // See issue 26116. + if step > 0 && !less { + continue + } + if step < 0 && less { + continue + } - // Up to now we extracted the induction variable (ind), - // the increment delta (inc), the temporary sum (nxt), - // the initial value (init) and the limiting value (limit). - // - // We also know that ind has the form (Phi init nxt) where - // nxt is (Add inc nxt) which means: 1) inc dominates nxt - // and 2) there is a loop starting at inc and containing nxt. - // - // We need to prove that the induction variable is incremented - // only when it's smaller than the limiting value. - // Two conditions must happen listed below to accept ind - // as an induction variable. - - // First condition: loop entry has a single predecessor, which - // is the header block. This implies that b.Succs[0] is - // reached iff ind < limit. - if len(startBody.b.Preds) != 1 { - // the other successor must exit the loop. - continue - } + // Up to now we extracted the induction variable (ind), + // the increment delta (inc), the temporary sum (nxt), + // the initial value (init) and the limiting value (limit). + // + // We also know that ind has the form (Phi init nxt) where + // nxt is (Add inc nxt) which means: 1) inc dominates nxt + // and 2) there is a loop starting at inc and containing nxt. + // + // We need to prove that the induction variable is incremented + // only when it's smaller than the limiting value. + // Two conditions must happen listed below to accept ind + // as an induction variable. + + // First condition: the entry block has a single predecessor. + // The entry now means the in-loop edge where the induction variable + // comparison succeeded. Its predecessor is not necessarily the header + // block. This implies that b.Succs[0] is reached iff ind < limit. + if len(startBody.b.Preds) != 1 { + // the other successor must exit the loop. + continue + } - // Second condition: startBody.b dominates nxt so that - // nxt is computed when inc < limit. - if !sdom.IsAncestorEq(startBody.b, nxt.Block) { - // inc+ind can only be reached through the branch that enters the loop. - continue - } + // Second condition: startBody.b dominates nxt so that + // nxt is computed when inc < limit. + if !sdom.IsAncestorEq(startBody.b, nxt.Block) { + // inc+ind can only be reached through the branch that confirmed the + // induction variable is in bounds. + continue + } - // Check for overflow/underflow. We need to make sure that inc never causes - // the induction variable to wrap around. - // We use a function wrapper here for easy return true / return false / keep going logic. - // This function returns true if the increment will never overflow/underflow. - ok := func() bool { - if step > 0 { - if limit.isGenericIntConst() { - // Figure out the actual largest value. - v := limit.AuxInt - if !inclusive { - if v == minSignedValue(limit.Type) { - return false // < minint is never satisfiable. + // Check for overflow/underflow. We need to make sure that inc never causes + // the induction variable to wrap around. + // We use a function wrapper here for easy return true / return false / keep going logic. + // This function returns true if the increment will never overflow/underflow. + ok := func() bool { + if step > 0 { + if limit.isGenericIntConst() { + // Figure out the actual largest value. + v := limit.AuxInt + if !inclusive { + if v == minSignedValue(limit.Type) { + return false // < minint is never satisfiable. + } + v-- } - v-- - } - if init.isGenericIntConst() { - // Use stride to compute a better lower limit. - if init.AuxInt > v { + if init.isGenericIntConst() { + // Use stride to compute a better lower limit. + if init.AuxInt > v { + return false + } + // TODO(1.27): investigate passing a smaller-magnitude overflow limit to addU + // for addWillOverflow. + v = addU(init.AuxInt, diff(v, init.AuxInt)/uint64(step)*uint64(step)) + } + if addWillOverflow(v, step, maxSignedValue(ind.Type)) { return false } - v = addU(init.AuxInt, diff(v, init.AuxInt)/uint64(step)*uint64(step)) + if inclusive && v != limit.AuxInt || !inclusive && v+1 != limit.AuxInt { + // We know a better limit than the programmer did. Use our limit instead. + limit = f.constVal(limit.Op, limit.Type, v, true) + inclusive = true + } + return true } - if addWillOverflow(v, step) { + if step == 1 && !inclusive { + // Can't overflow because maxint is never a possible value. + return true + } + // If the limit is not a constant, check to see if it is a + // negative offset from a known non-negative value. + knn, k := findKNN(limit) + if knn == nil || k < 0 { return false } - if inclusive && v != limit.AuxInt || !inclusive && v+1 != limit.AuxInt { - // We know a better limit than the programmer did. Use our limit instead. - limit = f.constVal(limit.Op, limit.Type, v, true) - inclusive = true + // limit == (something nonnegative) - k. That subtraction can't underflow, so + // we can trust it. + if inclusive { + // ind <= knn - k cannot overflow if step is at most k + return step <= k } - return true - } - if step == 1 && !inclusive { - // Can't overflow because maxint is never a possible value. - return true - } - // If the limit is not a constant, check to see if it is a - // negative offset from a known non-negative value. - knn, k := findKNN(limit) - if knn == nil || k < 0 { - return false - } - // limit == (something nonnegative) - k. That subtraction can't underflow, so - // we can trust it. - if inclusive { - // ind <= knn - k cannot overflow if step is at most k - return step <= k - } - // ind < knn - k cannot overflow if step is at most k+1 - return step <= k+1 && k != maxSignedValue(limit.Type) - } else { // step < 0 - if limit.Op == OpConst64 { - // Figure out the actual smallest value. - v := limit.AuxInt - if !inclusive { - if v == maxSignedValue(limit.Type) { - return false // > maxint is never satisfiable. + // ind < knn - k cannot overflow if step is at most k+1 + return step <= k+1 && k != maxSignedValue(limit.Type) + + // TODO: other unrolling idioms + // for i := 0; i < KNN - KNN % k ; i += k + // for i := 0; i < KNN&^(k-1) ; i += k // k a power of 2 + // for i := 0; i < KNN&(-k) ; i += k // k a power of 2 + } else { // step < 0 + if limit.isGenericIntConst() { + // Figure out the actual smallest value. + v := limit.AuxInt + if !inclusive { + if v == maxSignedValue(limit.Type) { + return false // > maxint is never satisfiable. + } + v++ } - v++ - } - if init.isGenericIntConst() { - // Use stride to compute a better lower limit. - if init.AuxInt < v { + if init.isGenericIntConst() { + // Use stride to compute a better lower limit. + if init.AuxInt < v { + return false + } + // TODO(1.27): investigate passing a smaller-magnitude underflow limit to subU + // for subWillUnderflow. + v = subU(init.AuxInt, diff(init.AuxInt, v)/uint64(-step)*uint64(-step)) + } + if subWillUnderflow(v, -step, minSignedValue(ind.Type)) { return false } - v = subU(init.AuxInt, diff(init.AuxInt, v)/uint64(-step)*uint64(-step)) - } - if subWillUnderflow(v, -step) { - return false + if inclusive && v != limit.AuxInt || !inclusive && v-1 != limit.AuxInt { + // We know a better limit than the programmer did. Use our limit instead. + limit = f.constVal(limit.Op, limit.Type, v, true) + inclusive = true + } + return true } - if inclusive && v != limit.AuxInt || !inclusive && v-1 != limit.AuxInt { - // We know a better limit than the programmer did. Use our limit instead. - limit = f.constVal(limit.Op, limit.Type, v, true) - inclusive = true + if step == -1 && !inclusive { + // Can't underflow because minint is never a possible value. + return true } - return true - } - if step == -1 && !inclusive { - // Can't underflow because minint is never a possible value. - return true } + return false } - return false - - } - if ok() { - flags := indVarFlags(0) - var min, max *Value - if step > 0 { - min = init - max = limit - if inclusive { + if ok() { + flags := indVarFlags(0) + var min, max *Value + if step > 0 { + min = init + max = limit + if inclusive { + flags |= indVarMaxInc + } + } else { + min = limit + max = init flags |= indVarMaxInc + if !inclusive { + flags |= indVarMinExc + } + step = -step } - } else { - min = limit - max = init - flags |= indVarMaxInc - if !inclusive { - flags |= indVarMinExc + if f.pass.debug >= 1 { + printIndVar(b, ind, min, max, step, flags) } - flags |= indVarCountDown - step = -step - } - if f.pass.debug >= 1 { - printIndVar(b, ind, min, max, step, flags) - } - iv = append(iv, indVar{ - ind: ind, - nxt: nxt, - min: min, - max: max, - entry: startBody.b, - flags: flags, - }) - b.Logf("found induction variable %v (inc = %v, min = %v, max = %v)\n", ind, inc, min, max) + iv = append(iv, indVar{ + ind: ind, + nxt: nxt, + min: min, + max: max, + // This is startBody.b, where startBody is the edge from the comparison for the + // induction variable, not necessarily the in-loop edge from the loop header. + // Induction variable bounds are not valid in the loop before this edge. + entry: startBody.b, + step: step, + flags: flags, + }) + b.Logf("found induction variable %v (inc = %v, min = %v, max = %v)\n", ind, inc, min, max) + } } - - // TODO: other unrolling idioms - // for i := 0; i < KNN - KNN % k ; i += k - // for i := 0; i < KNN&^(k-1) ; i += k // k a power of 2 - // for i := 0; i < KNN&(-k) ; i += k // k a power of 2 } return iv } -// addWillOverflow reports whether x+y would result in a value more than maxint. -func addWillOverflow(x, y int64) bool { - return x+y < x +// subWillUnderflow checks if x - y underflows the min value. +// y must be positive. +func subWillUnderflow(x, y int64, min int64) bool { + if y < 0 { + base.Fatalf("expecting positive value") + } + return x < min+y } -// subWillUnderflow reports whether x-y would result in a value less than minint. -func subWillUnderflow(x, y int64) bool { - return x-y > x +// addWillOverflow checks if x + y overflows the max value. +// y must be positive. +func addWillOverflow(x, y int64, max int64) bool { + if y < 0 { + base.Fatalf("expecting positive value") + } + return x > max-y } // diff returns x-y as a uint64. Requires x>=y. @@ -356,7 +393,8 @@ func addU(x int64, y uint64) int64 { x += 1 y -= 1 << 63 } - if addWillOverflow(x, int64(y)) { + // TODO(1.27): investigate passing a smaller-magnitude overflow limit in here. + if addWillOverflow(x, int64(y), maxSignedValue(types.Types[types.TINT64])) { base.Fatalf("addU overflowed %d + %d", x, y) } return x + int64(y) @@ -372,7 +410,8 @@ func subU(x int64, y uint64) int64 { x -= 1 y -= 1 << 63 } - if subWillUnderflow(x, int64(y)) { + // TODO(1.27): investigate passing a smaller-magnitude underflow limit in here. + if subWillUnderflow(x, int64(y), minSignedValue(types.Types[types.TINT64])) { base.Fatalf("subU underflowed %d - %d", x, y) } return x - int64(y) diff --git a/src/cmd/compile/internal/ssa/loopreschedchecks.go b/src/cmd/compile/internal/ssa/loopreschedchecks.go index 125c468217dbf4..f9b91676da341c 100644 --- a/src/cmd/compile/internal/ssa/loopreschedchecks.go +++ b/src/cmd/compile/internal/ssa/loopreschedchecks.go @@ -75,10 +75,7 @@ func insertLoopReschedChecks(f *Func) { idom := f.Idom() po := f.postorder() - // The ordering in the dominator tree matters; it's important that - // the walk of the dominator tree also be a preorder (i.e., a node is - // visited only after all its non-backedge predecessors have been visited). - sdom := newSparseOrderedTree(f, idom, po) + sdom := f.Sdom() if f.pass.debug > 1 { fmt.Printf("before %s = %s\n", f.Name, sdom.treestructure(f.Entry)) diff --git a/src/cmd/compile/internal/ssa/memcombine.go b/src/cmd/compile/internal/ssa/memcombine.go index 6b1df7dc099e73..32b9b7a290a9ca 100644 --- a/src/cmd/compile/internal/ssa/memcombine.go +++ b/src/cmd/compile/internal/ssa/memcombine.go @@ -626,11 +626,10 @@ func combineStores(root *Value) { loadMem = nil break } - if load.Type.IsPtr() { + if load.Type.HasPointers() { // Don't combine stores containing a pointer, as we need - // a write barrier for those. This can't currently happen, - // but might in the future if we ever have another - // 8-byte-reg/4-byte-ptr architecture like amd64p32. + // a write barrier for those. This can happen on an + // 8-byte-reg/4-byte-ptr architecture like wasm32. loadMem = nil break } diff --git a/src/cmd/compile/internal/ssa/merge_conditional_branches.go b/src/cmd/compile/internal/ssa/merge_conditional_branches.go new file mode 100644 index 00000000000000..a0577593091ec9 --- /dev/null +++ b/src/cmd/compile/internal/ssa/merge_conditional_branches.go @@ -0,0 +1,890 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "cmd/compile/internal/types" +) + +const ( + InvalidIndex = -1 + iota + TrueConditionSuccIndex // Index for true condition successor in block's successor list + FalseConditionSuccIndex // Index for false condition successor in block's successor list +) + +// mergeConditionalBranches performs if-conversion optimization on ARM64 by +// transforming nested conditional branches into conditional comparison instructions. +// +// The optimization detects patterns where two consecutive conditional branches +// implement logical AND/OR operations and replaces them with CCMP/CCMN instructions +// that execute the second conditionally based on the first comparison result. +// +// Transformation Pattern: +// +// Original CFG: +// +// if1 (outer condition) +// / \ +// / \ +// / if2 (inner condition) +// | / \ +// | / \ +// | / \ +// b1 (common) b2 (target) +// +// Transformed CFG: +// +// new_if (conditional comparison) +// / \ +// / \ +// / p (empty plain block) +// | \ +// | \ +// | \ +// b1 (common) b2 (target) +// +// Transformation Conditions: +// - Both if1 and if2 must be ARM64 conditional blocks +// - if2 must have exactly one predecessor from if1 +// - if2 must not contain memory operations or side effects +// - The transformation must preserve phi node consistency in successor blocks +// +// This optimization eliminates branch mispredictions and improves instruction-level +// parallelism by leveraging ARM64's conditional execution capabilities. +// The resulting code uses conditional comparison instructions that test the second +// condition only if the first condition evaluates to a specific value. +func mergeConditionalBranches(f *Func) { + if f.Config.arch != "arm64" { + return + } + + // We iterate in postorder to ensure we process inner conditional blocks before + // their outer counterparts. This is crucial because: + // 1. Transformations create new conditional comparisons that combine inner and outer conditions + // 2. Processing inner blocks first ensures we don't miss nested patterns + // 3. It maintains the integrity of the CFG during transformations + // Reverse order (from leaves to root) allows safe modification without affecting + // yet-to-be-processed outer structures. + blocks := f.postorder() + + for _, block := range blocks { + // outerSuccIndex: index of the outedge from if1 to if2 + // innerSuccIndex: index of the outedge from if2 to b2 + outerSuccIndex, innerSuccIndex := detectNestedIfPattern(block) + + if outerSuccIndex != InvalidIndex && innerSuccIndex != InvalidIndex { + transformNestedIfPattern(block, outerSuccIndex, innerSuccIndex) + } + } +} + +// findFirstNonEmptyPlainBlock finds the first non-empty block in a chain of empty plain blocks +// starting from the specified child index of the parent block. It skips over empty blocks +// that serve only as pass-through nodes in the control flow graph. +func findFirstNonEmptyPlainBlock(parentBlock *Block, childIndex int) *Block { + childBlock := parentBlock.Succs[childIndex].Block() + for isEmptyPlainBlock(childBlock) { + childBlock = childBlock.Succs[0].Block() + } + return childBlock +} + +// isEmptyPlainBlock checks if a block is empty (contains no values), has exactly one +// predecessor and is of kind BlockPlain. Such blocks are typically +// artifacts of previous optimizations and can be safely removed or bypassed. +func isEmptyPlainBlock(block *Block) bool { + return block.Kind == BlockPlain && + len(block.Values) == 0 && + len(block.Preds) == 1 +} + +// removeEmptyPlainBlockChain removes a chain of empty plain blocks starting from +// the specified child index of the parent block. It traverses through consecutive +// empty blocks and deletes them from the control flow graph, connecting the parent +// directly to the first non-empty block in the chain. +func removeEmptyPlainBlockChain(parentBlock *Block, childIndex int) *Block { + childBlock := parentBlock.Succs[childIndex].Block() + for isEmptyPlainBlock(childBlock) { + nextBlock := childBlock.Succs[0].Block() + removeEmptyPlainBlock(childBlock) + childBlock = nextBlock + } + return childBlock +} + +// removeEmptyPlainBlock removes a single empty plain block from the control flow graph. +// It connects the block's predecessor directly to its successor, effectively bypassing +// the empty block, and then marks the block as invalid for future cleanup. +func removeEmptyPlainBlock(block *Block) { + prevEdge := block.Preds[0] + nextEdge := block.Succs[0] + + prevEdge.b.Succs[prevEdge.i] = nextEdge + nextEdge.b.Preds[nextEdge.i] = prevEdge + + block.removePred(0) + block.removeSucc(0) + block.Reset(BlockInvalid) +} + +// detectNestedIfPattern detects nested if patterns that can be transformed to conditional comparisons. +// It examines the outer block to see if it contains a nested conditional structure that matches +// the pattern for if-conversion. Returns the outer successor index (which branch contains the +// nested condition) and internal successor index (which branch of the nested condition leads to +// the common merge point), or InvalidIndex if no pattern is detected. +func detectNestedIfPattern(outerBlock *Block) (int, int) { + if !isIfBlock(outerBlock) { + // outerBlock doesn't contain comparison + return InvalidIndex, InvalidIndex + } + + // Skip empty blocks to find actual conditional targets + // Empty plain blocks are often inserted by previous optimizations + thenBlock := findFirstNonEmptyPlainBlock(outerBlock, TrueConditionSuccIndex) + elseBlock := findFirstNonEmptyPlainBlock(outerBlock, FalseConditionSuccIndex) + if thenBlock == elseBlock { + // Both branches lead to the same block, cannot transform + return InvalidIndex, InvalidIndex + } + + // Check for cyclic patterns where a condition refers back to the original block + if thenBlock == outerBlock { + // True branch forms a cycle back to outerBlock + return detectCyclePattern(outerBlock, FalseConditionSuccIndex) + } else if elseBlock == outerBlock { + // False branch forms a cycle back to outerBlock + return detectCyclePattern(outerBlock, TrueConditionSuccIndex) + } + + outerSuccIndex := InvalidIndex + + // Check if the true branch contains a nested conditional that can be moved + if len(thenBlock.Preds) == 1 && + isIfBlock(thenBlock) && + canValuesBeMoved(thenBlock) { + // True branch contains a valid nested condition + outerSuccIndex = TrueConditionSuccIndex + } else if len(elseBlock.Preds) == 1 && + isIfBlock(elseBlock) && + canValuesBeMoved(elseBlock) { + // False branch contains a valid nested condition + outerSuccIndex = FalseConditionSuccIndex + } else { + // This chain of blocks is not in pattern. + return InvalidIndex, InvalidIndex + } + + // Tree structure: + // + // outerBlock + // / \ + // / \ + // commonBothBlock innerBlock + // / \ + // / \ + // thenBlock elseBlock + // + // outerBlock: The outer conditional block being examined + // innerBlock: The inner conditional block (nested condition) + // commonBothBlock: The block reached when the outer condition is not met + // thenBlock/elseBlock: Successors of the inner conditional block + innerBlock := findFirstNonEmptyPlainBlock(outerBlock, outerSuccIndex) + commonBothBlock := findFirstNonEmptyPlainBlock(outerBlock, outerSuccIndex^1) + thenBlock = findFirstNonEmptyPlainBlock(innerBlock, TrueConditionSuccIndex) + elseBlock = findFirstNonEmptyPlainBlock(innerBlock, FalseConditionSuccIndex) + + // Determine which inner branch leads to the common merge point + // This identifies the index to NOT common merge point + var innerSuccIndex = InvalidIndex + switch commonBothBlock { + case elseBlock: + // Pattern: (if1 && if2) or (!if1 && if2) + // False branch of if2 leads to commonBothBlock, + // that means True branch leads to b2 (target) + innerSuccIndex = TrueConditionSuccIndex + case thenBlock: + // Pattern: (if1 && !if2) or (!if1 && !if2) + // True branch of if2 leads to commonBothBlock, + // that means False branch leads to b2 (target) + innerSuccIndex = FalseConditionSuccIndex + default: + // No pattern are matched + return InvalidIndex, InvalidIndex + } + + // Critical check: ensure phi nodes in merge blocks have consistent values + // This guarantees semantic preservation after transformation + outToCommonIndex := outerSuccIndex ^ 1 // index of the outedge from outerBlock to commonBothBlock + inToCommonIndex := innerSuccIndex ^ 1 // index of the outedge from innerBlock to commonBothBlock + if !checkSameValuesInPhiNodes(outerBlock, innerBlock, outToCommonIndex, inToCommonIndex) { + return InvalidIndex, InvalidIndex + } + + return outerSuccIndex, innerSuccIndex +} + +// detectCyclePattern detects cyclic patterns where a conditional block's successor +// refers back to the original block. This handles special cases where the control +// flow forms a loop-like structure that can still be optimized with conditional comparisons. +func detectCyclePattern(outerBlock *Block, outSuccIndex int) (int, int) { + secondCondBlock := findFirstNonEmptyPlainBlock(outerBlock, outSuccIndex) + + if len(secondCondBlock.Preds) != 1 || + len(secondCondBlock.Succs) != 2 || + !isIfBlock(secondCondBlock) || + !canValuesBeMoved(secondCondBlock) { + return InvalidIndex, InvalidIndex + } + + thenBlock := findFirstNonEmptyPlainBlock(secondCondBlock, TrueConditionSuccIndex) + elseBlock := findFirstNonEmptyPlainBlock(secondCondBlock, FalseConditionSuccIndex) + + if thenBlock == elseBlock { + // Both branches pointing to same block indicates degenerate case + return InvalidIndex, InvalidIndex + } + + // Check if the cycle connects back to the original block and verify phi consistency + switch outerBlock { + case thenBlock: + // True branch of inner condition leads back to outerBlock + if !checkSameValuesInPhiNodes(outerBlock, thenBlock, outSuccIndex^1, TrueConditionSuccIndex) { + return InvalidIndex, InvalidIndex + } + return outSuccIndex, FalseConditionSuccIndex + case elseBlock: + // False branch of inner condition leads back to outerBlock + if !checkSameValuesInPhiNodes(outerBlock, elseBlock, outSuccIndex^1, FalseConditionSuccIndex) { + return InvalidIndex, InvalidIndex + } + return outSuccIndex, TrueConditionSuccIndex + default: + // Pattern was not found + return InvalidIndex, InvalidIndex + } +} + +// checkSameValuesInPhiNodes checks if phi nodes in merge blocks have the same values +// for the given successor indices. This ensures that after transformation, phi nodes +// will receive the correct values from both paths. Returns true if all phi nodes +// have consistent arguments for the specified paths. +func checkSameValuesInPhiNodes(outerBlock, innerBlock *Block, outToCommonIndex, inToCommonIndex int) bool { + // Skip empty blocks to find actual phi-containing merge blocks + // Empty blocks don't affect phi nodes but complicate path tracking + for isEmptyPlainBlock(outerBlock.Succs[outToCommonIndex].Block()) { + outerBlock = outerBlock.Succs[outToCommonIndex].Block() + outToCommonIndex = 0 // After empty block, only one path exists + } + + for isEmptyPlainBlock(innerBlock.Succs[inToCommonIndex].Block()) { + innerBlock = innerBlock.Succs[inToCommonIndex].Block() + inToCommonIndex = 0 // After empty block, only one path exists + } + + // Both paths must lead to the same merge block for transformation to be valid + if outerBlock.Succs[outToCommonIndex].Block() != innerBlock.Succs[inToCommonIndex].Block() { + panic("checkSameValuesInPhiNodes: paths do not lead to the same merge block - invalid CFG pattern for if-conversion") + } + + argIndex1 := outerBlock.Succs[outToCommonIndex].Index() + argIndex2 := innerBlock.Succs[inToCommonIndex].Index() + + resultBlock := outerBlock.Succs[outToCommonIndex].Block() + for _, v := range resultBlock.Values { + if v.Op != OpPhi { + continue + } + + // If phi arguments from different paths don't match, + // merging the conditions would produce wrong values + if v.Args[argIndex1] != v.Args[argIndex2] { + return false + } + } + + return true +} + +// canValuesBeMoved checks if all values in a block can be safely moved to another block. +// This is necessary because during transformation, values from the inner conditional +// block are moved to the outer block. Values with side effects, memory operations, +// or phi nodes cannot be moved. +func canValuesBeMoved(b *Block) bool { + for _, v := range b.Values { + if !canValueBeMoved(v) { + return false + } + } + return true +} + +// canValueBeMoved checks if a single value can be safely moved to another block. +// Returns false for values that have side effects, are memory operations, phi nodes, +// or nil checks, as moving these could change program semantics. +func canValueBeMoved(v *Value) bool { + if v.Op == OpPhi { + return false + } + if v.Type.IsMemory() { + return false + } + if v.Op.HasSideEffects() { + return false + } + if opcodeTable[v.Op].nilCheck { + return false + } + if v.MemoryArg() != nil { + return false + } + return true +} + +// isIfBlock checks if a block is a conditional block that can participate in +// if-conversion. This includes all ARM64 conditional block kinds (EQ, NE, LT, etc.) +// and zero/non-zero test blocks (Z, NZ, ZW, NZW). +func isIfBlock(b *Block) bool { + switch b.Kind { + case BlockARM64EQ, + BlockARM64NE, + BlockARM64LT, + BlockARM64LE, + BlockARM64GT, + BlockARM64GE, + BlockARM64ULT, + BlockARM64ULE, + BlockARM64UGT, + BlockARM64UGE: + return isComparisonOperation(b.Controls[0]) + case BlockARM64Z, + BlockARM64NZ, + BlockARM64ZW, + BlockARM64NZW: + return true + default: + return false + } +} + +// isComparisonOperation checks if a value represents a comparison operation +// that can be used in conditional execution. Also ensures the value has only +// one use to prevent unexpected side effects from transformation. +func isComparisonOperation(value *Value) bool { + if value.Uses != 1 { + // This value can be transformed to another value. + // New value can get another results, not which are expected. + // That why we need to check this case. + return false + } + + switch value.Op { + case OpARM64CMP, + OpARM64CMPconst, + OpARM64CMN, + OpARM64CMNconst, + OpARM64CMPW, + OpARM64CMPWconst, + OpARM64CMNW, + OpARM64CMNWconst: + return true + default: + return false + } +} + +// transformNestedIfPattern transforms a detected nested if pattern into a +// conditional comparison. This is the main transformation function that +// coordinates all the steps needed to convert the nested conditionals into +// a single conditional comparison instruction. +func transformNestedIfPattern(outerBlock *Block, outSuccIndex, inSuccIndex int) { + clearPatternFromEmptyPlainBlocks(outerBlock, outSuccIndex) + innerBlock := outerBlock.Succs[outSuccIndex].Block() + + // Transform the control flow step by step: + // 1. Transform primary comparison to standard form if needed + // 2. Transform dependent comparison to work with conditional execution + // 3. Convert to conditional comparison operation (CCMP/CCMN) + // 4. Fix comparisons with constants to use constant forms when possible + // 5. Set the new control value for the transformed block + // 6. Move all values from inner block to outer block + // 7. Eliminate the now-redundant nested block + transformPrimaryComparisonValue(outerBlock) + transformDependentComparisonValue(innerBlock) + transformToConditionalComparisonValue(outerBlock, outSuccIndex, inSuccIndex) + fixComparisonWithConstant(innerBlock, outSuccIndex) + setNewControlValue(outerBlock, innerBlock, outSuccIndex, inSuccIndex) + moveAllValues(outerBlock, innerBlock) + elimNestedBlock(innerBlock, inSuccIndex) +} + +// clearPatternFromEmptyPlainBlocks removes all empty plain blocks from the +// detected pattern to simplify the control flow graph before transformation. +func clearPatternFromEmptyPlainBlocks(outerBlock *Block, outSuccIndex int) { + innerBlock := removeEmptyPlainBlockChain(outerBlock, outSuccIndex) + removeEmptyPlainBlockChain(outerBlock, outSuccIndex^1) + + removeEmptyPlainBlockChain(innerBlock, TrueConditionSuccIndex) + removeEmptyPlainBlockChain(innerBlock, FalseConditionSuccIndex) +} + +// moveAllValues moves all values from the source block to the destination block. +// This is used to consolidate the computations from the inner conditional block +// into the outer block as part of the if-conversion process. +func moveAllValues(dest, src *Block) { + for _, value := range src.Values { + value.Block = dest + dest.Values = append(dest.Values, value) + } + src.truncateValues(0) +} + +// elimNestedBlock eliminates a nested block that has been incorporated into +// the outer block through if-conversion. It removes the specified successor +// edge and updates phi nodes in the target block to remove the corresponding argument. +func elimNestedBlock(b *Block, index int) { + removedEdge := b.Succs[index^1] + + notBothMetBlock := removedEdge.Block() + i := removedEdge.Index() + + b.removeSucc(index ^ 1) + notBothMetBlock.removePred(i) + for _, v := range notBothMetBlock.Values { + if v.Op != OpPhi { + continue + } + notBothMetBlock.removePhiArg(v, i) + } + + b.Func.invalidateCFG() + b.Reset(BlockPlain) + b.Likely = BranchUnknown +} + +// setNewControlValue sets the new control value for the transformed block +// based on the inner block's control value. It also updates the branch +// likelihood based on the original block's branch prediction. +func setNewControlValue(outerBlock, innerBlock *Block, outSuccIndex, inSuccIndex int) { + outerBlock.resetWithControl(innerBlock.Kind, innerBlock.Controls[0]) + if !isBranchLikelyConsistentWithIndex(outerBlock, outSuccIndex) || + !isBranchLikelyConsistentWithIndex(innerBlock, inSuccIndex) { + outerBlock.Likely = BranchUnknown + } +} + +// isBranchLikelyConsistentWithIndex checks if the branch likelihood matches the expected +// index. Returns true if the likelihood is consistent with the branch direction. +func isBranchLikelyConsistentWithIndex(b *Block, index int) bool { + if index == TrueConditionSuccIndex && b.Likely == BranchLikely { + return true + } else if index == FalseConditionSuccIndex && b.Likely == BranchUnlikely { + return true + } + return false +} + +// transformPrimaryComparisonValue transforms special block kinds (Z, NZ, ZW, NZW) +// into standard comparison operations. These block kinds test for zero/non-zero +// and need to be converted to explicit comparisons with zero for conditional execution. +func transformPrimaryComparisonValue(block *Block) { + switch block.Kind { + case BlockARM64Z: + arg0 := block.Controls[0] + controlValue := block.NewValue1I(arg0.Pos, OpARM64CMPconst, types.TypeFlags, 0, arg0) + block.resetWithControl(BlockARM64EQ, controlValue) + case BlockARM64NZ: + arg0 := block.Controls[0] + controlValue := block.NewValue1I(arg0.Pos, OpARM64CMPconst, types.TypeFlags, 0, arg0) + block.resetWithControl(BlockARM64NE, controlValue) + case BlockARM64ZW: + arg0 := block.Controls[0] + controlValue := block.NewValue1I(arg0.Pos, OpARM64CMPWconst, types.TypeFlags, 0, arg0) + block.resetWithControl(BlockARM64EQ, controlValue) + case BlockARM64NZW: + arg0 := block.Controls[0] + controlValue := block.NewValue1I(arg0.Pos, OpARM64CMPWconst, types.TypeFlags, 0, arg0) + block.resetWithControl(BlockARM64NE, controlValue) + default: + return + } +} + +// transformDependentComparisonValue transforms the comparison in the dependent +// (inner) block to prepare it for conditional execution. This involves converting +// constant comparisons to register comparisons and handling special block kinds. +func transformDependentComparisonValue(block *Block) { + typ := &block.Func.Config.Types + + switch block.Kind { + case BlockARM64EQ, + BlockARM64NE, + BlockARM64LT, + BlockARM64LE, + BlockARM64GT, + BlockARM64GE, + BlockARM64ULT, + BlockARM64ULE, + BlockARM64UGT, + BlockARM64UGE: + value := block.Controls[0] + + switch value.Op { + case OpARM64CMPconst: + arg0 := value.Args[0] + auxConstant := auxIntToInt64(value.AuxInt) + value.reset(OpARM64CMP) + constantValue := block.Func.constVal(OpARM64MOVDconst, typ.UInt64, auxConstant, true) + value.AddArg2(arg0, constantValue) + case OpARM64CMNconst: + arg0 := value.Args[0] + auxConstant := auxIntToInt64(value.AuxInt) + value.reset(OpARM64CMN) + constantValue := block.Func.constVal(OpARM64MOVDconst, typ.UInt64, auxConstant, true) + value.AddArg2(arg0, constantValue) + case OpARM64CMPWconst: + arg0 := value.Args[0] + auxConstant := auxIntToInt32(value.AuxInt) + value.reset(OpARM64CMPW) + constantValue := block.Func.constVal(OpARM64MOVDconst, typ.UInt64, int64(auxConstant), true) + value.AddArg2(arg0, constantValue) + case OpARM64CMNWconst: + arg0 := value.Args[0] + auxConstant := auxIntToInt32(value.AuxInt) + value.reset(OpARM64CMNW) + constantValue := block.Func.constVal(OpARM64MOVDconst, typ.UInt64, int64(auxConstant), true) + value.AddArg2(arg0, constantValue) + default: + return + } + case BlockARM64Z: + arg0 := block.Controls[0] + arg1 := block.Func.constVal(OpARM64MOVDconst, typ.UInt64, 0, true) + comparisonValue := block.NewValue2(arg0.Pos, OpARM64CMP, types.TypeFlags, arg0, arg1) + block.resetWithControl(BlockARM64EQ, comparisonValue) + case BlockARM64NZ: + arg0 := block.Controls[0] + arg1 := block.Func.constVal(OpARM64MOVDconst, typ.UInt64, 0, true) + comparisonValue := block.NewValue2(arg0.Pos, OpARM64CMP, types.TypeFlags, arg0, arg1) + block.resetWithControl(BlockARM64NE, comparisonValue) + case BlockARM64ZW: + arg0 := block.Controls[0] + arg1 := block.Func.constVal(OpARM64MOVDconst, typ.UInt64, 0, true) + comparisonValue := block.NewValue2(arg0.Pos, OpARM64CMPW, types.TypeFlags, arg0, arg1) + block.resetWithControl(BlockARM64EQ, comparisonValue) + case BlockARM64NZW: + arg0 := block.Controls[0] + arg1 := block.Func.constVal(OpARM64MOVDconst, typ.UInt64, 0, true) + comparisonValue := block.NewValue2(arg0.Pos, OpARM64CMPW, types.TypeFlags, arg0, arg1) + block.resetWithControl(BlockARM64NE, comparisonValue) + default: + panic("Wrong block kind") + } +} + +// fixComparisonWithConstant optimizes conditional comparisons by converting +// them to constant forms when one operand is a small constant. This generates +// more efficient CCMPconst/CCMNconst instructions. +func fixComparisonWithConstant(block *Block, index int) { + // Helper function to extract 5-bit immediate from int64 constant (0-31 range) + getImm64 := func(auxInt int64) (uint8, bool) { + imm := auxIntToInt64(auxInt) + if imm&^0x1f == 0 { + return uint8(imm), true + } + return 0, false + } + + // Helper function to extract 5-bit immediate from int32 constant (0-31 range) + getImm32 := func(auxInt int64) (uint8, bool) { + imm := auxIntToInt32(auxInt) + if imm&^0x1f == 0 { + return uint8(imm), true + } + return 0, false + } + + // Helper function to convert conditional comparison to constant form if possible + // Algorithm: Check if either operand is a small 5-bit constant (0-31). If found: + // 1. Convert operation to constant form (CCMP -> CCMPconst, etc.) + // 2. Set the 'ind' flag for immediate mode + // 3. When constant is first operand (arg0), swap operands and invert condition + tryConvertToConstForm := func(value *Value, newOp Op, getImm func(int64) (uint8, bool)) { + params := value.AuxArm64ConditionalParams() + arg0 := value.Args[0] + arg1 := value.Args[1] + arg2 := value.Args[2] + // Check second operand for small constant + if arg1.Op == OpARM64MOVDconst { + if imm, ok := getImm(arg1.AuxInt); ok { + value.reset(newOp) + params.constValue = imm + params.ind = true + value.AuxInt = arm64ConditionalParamsToAuxInt(params) + value.AddArg2(arg0, arg2) + return + } + } + + // Check first operand for small constant + if arg0.Op == OpARM64MOVDconst { + if imm, ok := getImm(arg0.AuxInt); ok { + value.reset(newOp) + invertConditionsInBlock(block, ¶ms, index) + params.constValue = imm + params.ind = true + value.AuxInt = arm64ConditionalParamsToAuxInt(params) + value.AddArg2(arg1, arg2) + return + } + } + } + + // try to convert control value of block to constant form + controlValue := block.Controls[0] + switch controlValue.Op { + case OpARM64CCMP: + tryConvertToConstForm(controlValue, OpARM64CCMPconst, getImm64) + case OpARM64CCMN: + tryConvertToConstForm(controlValue, OpARM64CCMNconst, getImm64) + case OpARM64CCMPW: + tryConvertToConstForm(controlValue, OpARM64CCMPWconst, getImm32) + case OpARM64CCMNW: + tryConvertToConstForm(controlValue, OpARM64CCMNWconst, getImm32) + default: + return + } +} + +// invertConditionsInBlock inverts the condition in a block and returns updated +// conditional parameters. This is used when swapping operands in constant +// optimizations to maintain correct semantics. +func invertConditionsInBlock(block *Block, params *arm64ConditionalParams, index int) { + invertKind := invertBlockKind(block.Kind) + block.Kind = invertKind + if index == FalseConditionSuccIndex { + invertKind = negateBlockKind(invertKind) + } + params.nzcv = nzcvByBlockKind(invertKind) +} + +// transformToConditionalComparisonValue transforms the comparison operations +// to conditional comparison operations (CCMP/CCMN). This is the core transformation +// that creates the conditional execution pattern by combining the outer and inner +// conditions into a single conditional comparison instruction. +func transformToConditionalComparisonValue(outerBlock *Block, outSuccIndex, inSuccIndex int) { + innerBlock := outerBlock.Succs[outSuccIndex].Block() + + // Adjust block kinds and successors if needed to match expected pattern + if outSuccIndex != inSuccIndex { + outerBlock.Kind = negateBlockKind(outerBlock.Kind) + outerBlock.swapSuccessors() + outSuccIndex ^= 1 + } + + outerControl := outerBlock.Controls[0] + outerKind := outerBlock.Kind + + innerControl := innerBlock.Controls[0] + innerKind := innerBlock.Kind + + // Adjust conditions based on successor index + if outSuccIndex == FalseConditionSuccIndex { + outerKind = negateBlockKind(outerKind) + innerKind = negateBlockKind(innerKind) + } + + // Get conditional parameters and transform the operation + params := createConditionalParamsByBlockKind(outerKind, innerKind) + + innerControl.AddArg(outerControl) + innerControl.Op = transformOpToConditionalComparisonOperation(innerControl.Op) + innerControl.AuxInt = arm64ConditionalParamsToAuxInt(params) +} + +// transformOpToConditionalComparisonOperation maps standard comparison operations +// to their conditional comparison counterparts (e.g., CMP -> CCMP, CMN -> CCMN). +func transformOpToConditionalComparisonOperation(op Op) Op { + switch op { + case OpARM64CMP: + return OpARM64CCMP + case OpARM64CMN: + return OpARM64CCMN + case OpARM64CMPconst: + return OpARM64CCMPconst + case OpARM64CMNconst: + return OpARM64CCMNconst + case OpARM64CMPW: + return OpARM64CCMPW + case OpARM64CMNW: + return OpARM64CCMNW + case OpARM64CMPWconst: + return OpARM64CCMPWconst + case OpARM64CMNWconst: + return OpARM64CCMNWconst + default: + panic("Incorrect operation") + } +} + +// createConditionalParamsByBlockKind constructs conditional parameters for ARM64 conditional instructions. +// It combines two block kinds: +// - outerKind specifies the main condition (e.g., LT, GT) to be evaluated. +// - innerKind determines the NZCV flag pattern to be used when the main condition is FALSE. +// The resulting parameters are typically used by conditional comparison operations (CCMP, CCMN). +func createConditionalParamsByBlockKind(outerKind, innerKind BlockKind) arm64ConditionalParams { + cond := condByBlockKind(outerKind) // the condition code for the primary comparison + nzcv := nzcvByBlockKind(innerKind) // NZCV flags to apply when the condition is false + return arm64ConditionalParamsAuxInt(cond, nzcv) +} + +// condByBlockKind maps block kinds to their corresponding condition codes +// for ARM64 conditional execution. +func condByBlockKind(kind BlockKind) Op { + switch kind { + case BlockARM64EQ: + return OpARM64Equal + case BlockARM64NE: + return OpARM64NotEqual + case BlockARM64LT: + return OpARM64LessThan + case BlockARM64LE: + return OpARM64LessEqual + case BlockARM64GT: + return OpARM64GreaterThan + case BlockARM64GE: + return OpARM64GreaterEqual + case BlockARM64ULT: + return OpARM64LessThanU + case BlockARM64ULE: + return OpARM64LessEqualU + case BlockARM64UGT: + return OpARM64GreaterThanU + case BlockARM64UGE: + return OpARM64GreaterEqualU + default: + panic("Incorrect kind of Block") + } +} + +// nzcvByBlockKind returns NZCV flags encoding the *logical opposite* of the specified block condition. +// The returned flags represent the processor state to be used when the primary comparison condition +// evaluates to false. +// +// Each case constructs the flag pattern for the inverse condition: +// +// EQ -> NE, LT -> GE, GT -> LE, etc. +func nzcvByBlockKind(kind BlockKind) uint8 { + switch kind { + case BlockARM64EQ: + // Encode NE : Z == 0 + return packNZCV(false, false, false, false) // N=0,Z=0,C=0,V=0 + case BlockARM64NE: + // Encode EQ : Z == 1 + return packNZCV(false, true, false, false) // N=0,Z=1,C=0,V=0 + case BlockARM64LT: + // Encode GE : N == V + return packNZCV(false, false, false, false) // N=0,Z=0,C=0,V=0 + case BlockARM64LE: + // Encode GT : (Z == 0) && (N == V) + return packNZCV(false, false, false, false) // N=0,Z=0,C=0,V=0 + case BlockARM64GT: + // Encode LE : (Z == 1) || (N != V) + return packNZCV(false, true, false, false) // N=0,Z=1,C=0,V=0 + case BlockARM64GE: + // Encode LT : N != V + return packNZCV(false, false, false, true) // N=0,Z=0,C=0,V=1 + case BlockARM64ULT: + // Encode UGE : C == 1 + return packNZCV(false, false, true, false) // N=0,Z=0,C=1,V=0 + case BlockARM64ULE: + // Encode UGT : (C == 1) && (Z == 0) + return packNZCV(false, false, true, false) // N=0,Z=0,C=1,V=0 + case BlockARM64UGT: + // Encode ULE : (C == 0) || (Z == 1) + return packNZCV(false, false, false, false) // N=0,Z=0,C=0,V=0 + case BlockARM64UGE: + // Encode ULT : C == 0 + return packNZCV(false, false, false, false) // N=0,Z=0,C=0,V=0 + default: + panic("Incorrect kind of Block") + } +} + +// packNZCV packs boolean condition flags into a single byte representing +// the ARM64 NZCV condition flags: Negative, Zero, Carry, Overflow. +func packNZCV(N, Z, C, V bool) uint8 { + var NZCVFlags uint8 = 0 + if N { + NZCVFlags |= 1 << 3 + } + if Z { + NZCVFlags |= 1 << 2 + } + if C { + NZCVFlags |= 1 << 1 + } + if V { + NZCVFlags |= 1 + } + return NZCVFlags +} + +// negateBlockKind returns the logical negation of a block kind +// (e.g., EQ becomes NE, LT becomes GE). +func negateBlockKind(kind BlockKind) BlockKind { + switch kind { + case BlockARM64EQ: + return BlockARM64NE + case BlockARM64NE: + return BlockARM64EQ + case BlockARM64LT: + return BlockARM64GE + case BlockARM64LE: + return BlockARM64GT + case BlockARM64GT: + return BlockARM64LE + case BlockARM64GE: + return BlockARM64LT + case BlockARM64ULT: + return BlockARM64UGE + case BlockARM64ULE: + return BlockARM64UGT + case BlockARM64UGT: + return BlockARM64ULE + case BlockARM64UGE: + return BlockARM64ULT + default: + panic("Incorrect kind of Block") + } +} + +// invertBlockKind inverts the operands of a comparison block kind +// (e.g., LT becomes GT, LE becomes GE). +func invertBlockKind(kind BlockKind) BlockKind { + switch kind { + case BlockARM64EQ: + return BlockARM64EQ + case BlockARM64NE: + return BlockARM64NE + case BlockARM64LT: + return BlockARM64GT + case BlockARM64LE: + return BlockARM64GE + case BlockARM64GT: + return BlockARM64LT + case BlockARM64GE: + return BlockARM64LE + case BlockARM64ULT: + return BlockARM64UGT + case BlockARM64ULE: + return BlockARM64UGE + case BlockARM64UGT: + return BlockARM64ULT + case BlockARM64UGE: + return BlockARM64ULE + default: + panic("Incorrect kind of Block") + } +} diff --git a/src/cmd/compile/internal/ssa/merge_conditional_branches_test.go b/src/cmd/compile/internal/ssa/merge_conditional_branches_test.go new file mode 100644 index 00000000000000..08925a3ce0a8b1 --- /dev/null +++ b/src/cmd/compile/internal/ssa/merge_conditional_branches_test.go @@ -0,0 +1,282 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "cmd/compile/internal/types" + "testing" +) + +// ARM64Lt specifies BlockARM64LT +func ARM64Lt(cond, sub, alt string) ctrl { + return ctrl{BlockARM64LT, cond, []string{sub, alt}} +} + +// ARM64Gt specifies BlockARM64GT +func ARM64Gt(cond, sub, alt string) ctrl { + return ctrl{BlockARM64GT, cond, []string{sub, alt}} +} + +// ARM64Ne specifies BlockARM64NE +func ARM64Ne(cond, sub, alt string) ctrl { + return ctrl{BlockARM64NE, cond, []string{sub, alt}} +} + +// ARM64Eq specifies BlockARM64EQ +func ARM64Eq(cond, sub, alt string) ctrl { + return ctrl{BlockARM64EQ, cond, []string{sub, alt}} +} + +// isNewConditionCorrect verifies that a block has been correctly transformed +// to use conditional comparison (CCMP) with the expected parameters. +// It checks: +// - The block kind is BlockARM64LT (less than condition) +// - The control operation is OpARM64CCMPconst (conditional comparison with constant) +// - The condition code is OpARM64GreaterThan +// - The NZCV flags are set to 1 +// - The constant value being compared is 4 +// Returns true if all conditions match the expected transformation pattern +func isNewConditionCorrect(b *Block) bool { + if b.Kind != BlockARM64LT { + return false + } + + v := b.Controls[0] + if v.Op != OpARM64CCMPconst { + return false + } + + params := v.AuxArm64ConditionalParams() + if params.Cond() != OpARM64GreaterThan { + return false + } + if params.Nzcv() != 1 { + // NZCV flags should be set to 1 for this specific transformation + return false + } + if imm, ok := params.ConstValue(); !ok || imm != 4 { + return false + } + + return true +} + +// containsOpARM64CCMP checks if a block contains any ARM64 conditional comparison +// operations (CCMP or CCMPconst). This is used in tests to verify that the +// if-conversion optimization successfully generated conditional comparison +// instructions or to ensure they were not generated when inappropriate. +func containsOpARM64CCMP(b *Block) bool { + for _, v := range b.Values { + if v.Op == OpARM64CCMP || v.Op == OpARM64CCMPconst { + return true + } + } + return false +} + +// TestMergeConditionalBranchesWithoutPointers tests the if-conversion optimization +// on a simple case of logical AND (cond1 && cond2) without pointer operations. +// The test verifies that: +// - The optimization correctly transforms nested conditionals into CCMP instructions +// - The block structure is properly simplified (inner block becomes plain and empty) +// - The resulting control flow uses conditional comparison with correct parameters +// - No important blocks are accidentally deleted during transformation +// This represents the ideal case where the optimization should apply successfully. +func TestMergeConditionalBranchesWithoutPointers(t *testing.T) { + t.Run("arm64", func(t *testing.T) { + c := testConfigArch(t, "arm64") + intType := c.config.Types.Int64 + fun := c.Fun("entry", + Bloc("entry", + Valu("mem", + OpInitMem, + types.TypeMem, + 0, nil, + ), + Valu("a", + OpArg, + intType, + 0, c.Temp(intType), + ), + Valu("b", + OpArg, + intType, + 1, c.Temp(intType), + ), + Valu("cond1", + OpARM64CMPconst, + types.TypeFlags, + 1, nil, + "a", + ), + ARM64Gt("cond1", "second_comparison", "ret_false"), + ), + Bloc("second_comparison", + Valu("cond2", + OpARM64CMPconst, + types.TypeFlags, + 4, nil, + "b", + ), + ARM64Lt("cond2", "ret_false", "ret_true"), + ), + Bloc("ret_true", + Valu("const1", + OpARM64MOVDconst, + intType, + 1, nil, + ), + Valu("true_result", + OpMakeResult, + types.TypeMem, + 0, nil, + "const1", "mem", + ), + Ret("true_result"), + ), + Bloc("ret_false", + Valu("const0", + OpARM64MOVDconst, + intType, + 0, nil, + ), + Valu("false_result", + OpMakeResult, + types.TypeMem, + 0, nil, + "const0", "mem", + ), + Ret("false_result"), + ), + ) + + CheckFunc(fun.f) + mergeConditionalBranches(fun.f) + CheckFunc(fun.f) + + if len(fun.blocks) != 4 { + t.Errorf("Important block was deleted") + } + + entryBlock := fun.blocks["entry"] + secondBlock := fun.blocks["second_comparison"] + + if secondBlock.Kind != BlockPlain || len(secondBlock.Values) != 0 { + t.Errorf("Block with second condition wasn't cleaned") + } + + if !isNewConditionCorrect(entryBlock) { + t.Errorf("Entry block doesn't contain CCMP opertation") + } + }) +} + +// Test that pointer comparison with memory load doesn't generate CCMP +func TestNoCCMPWithPointerAndMemoryLoad(t *testing.T) { + t.Run("arm64", func(t *testing.T) { + c := testConfigArch(t, "arm64") + intType := c.config.Types.Int64 + ptrType := c.config.Types.BytePtr + + fun := c.Fun("entry", + Bloc("entry", + Valu("mem", + OpInitMem, + types.TypeMem, + 0, nil, + ), + Valu("ptr", + OpArg, + ptrType, + 0, c.Temp(ptrType), + ), + Valu("cond1", + OpARM64CMPconst, + types.TypeFlags, + 0, nil, // Compare with nil (0) + "ptr", + ), + ARM64Ne("cond1", "second_comparison", "ret_false"), // ptr != nil + ), + Bloc("second_comparison", + Valu("load", + OpLoad, + intType, + 0, nil, + "ptr", "mem", + ), + Valu("cond2", + OpARM64CMPconst, + types.TypeFlags, + 3, nil, // Compare with 3 + "load", + ), + ARM64Eq("cond2", "ret_true", "ret_false"), // *ptr == 3 + ), + Bloc("ret_true", + Valu("const1", + OpARM64MOVDconst, + intType, + 1, nil, + ), + Valu("true_result", + OpMakeResult, + types.TypeMem, + 0, nil, + "const1", "mem", + ), + Ret("true_result"), + ), + Bloc("ret_false", + Valu("const0", + OpARM64MOVDconst, + intType, + 0, nil, + ), + Valu("false_result", + OpMakeResult, + types.TypeMem, + 0, nil, + "const0", "mem", + ), + Ret("false_result"), + ), + ) + + CheckFunc(fun.f) + mergeConditionalBranches(fun.f) + CheckFunc(fun.f) + + // Verify that the second_comparison block still exists (not optimized away) + if fun.blocks["second_comparison"] == nil { + t.Errorf("Second comparison block was incorrectly removed") + } + + entryBlock := fun.blocks["entry"] + secondBlock := fun.blocks["second_comparison"] + + // Verify that entry block doesn't contain CCMP operation + if containsOpARM64CCMP(entryBlock) { + t.Errorf("Entry block contains CCMP operation, but shouldn't due to memory load") + } + + // Verify that second block contains the load operation + hasLoad := false + for _, v := range secondBlock.Values { + if v.Op == OpLoad { + hasLoad = true + break + } + } + if !hasLoad { + t.Errorf("Second comparison block should contain load operation") + } + + // The optimization shouldn't merge these blocks because of the memory operation + if secondBlock.Kind == BlockPlain { + t.Errorf("Block with memory load was incorrectly cleaned") + } + }) +} diff --git a/src/cmd/compile/internal/ssa/nilcheck.go b/src/cmd/compile/internal/ssa/nilcheck.go index 467c7514eee5f2..4db37450af69b2 100644 --- a/src/cmd/compile/internal/ssa/nilcheck.go +++ b/src/cmd/compile/internal/ssa/nilcheck.go @@ -217,13 +217,13 @@ func nilcheckelim2(f *Func) { f.Warnl(v.Pos, "removed nil check") } // For bug 33724, policy is that we might choose to bump an existing position - // off the faulting load in favor of the one from the nil check. + // off the faulting load/store in favor of the one from the nil check. // Iteration order means that first nilcheck in the chain wins, others // are bumped into the ordinary statement preservation algorithm. uid, _ := unnecessary.get(v.Args[0].ID) u := b.Values[uid] - if !u.Type.IsMemory() && !u.Pos.SameFileAndLine(v.Pos) { + if !u.Pos.SameFileAndLine(v.Pos) { if u.Pos.IsStmt() == src.PosIsStmt { pendingLines.add(u.Pos) } @@ -302,7 +302,7 @@ func nilcheckelim2(f *Func) { case auxInt64: // ARM uses this auxType for duffcopy/duffzero/alignment info. // It does not affect the effective address. - case auxNone: + case auxNone, auxSizeAndAlign: // offset is zero. default: v.Fatalf("can't handle aux %s (type %d) yet\n", v.auxString(), int(opcodeTable[v.Op].auxType)) diff --git a/src/cmd/compile/internal/ssa/op.go b/src/cmd/compile/internal/ssa/op.go index b279cf06bc05dd..0c4e902aece0e6 100644 --- a/src/cmd/compile/internal/ssa/op.go +++ b/src/cmd/compile/internal/ssa/op.go @@ -46,6 +46,9 @@ type opInfo struct { zeroWidth bool // op never translates into any machine code. example: copy, which may sometimes translate to machine code, is not zero-width. unsafePoint bool // this op is an unsafe point, i.e. not safe for async preemption fixedReg bool // this op will be assigned a fixed register + earlyOk bool // executing this op in an earlier block is ok + addrSinkArg0 bool // the address in arg0 does not propagate to the result + addrSinkArg1 bool // the address in arg1 does not propagate to the result symEffect SymEffect // effect this op has on symbol in aux scale uint8 // amd64/386 indexed load scale } @@ -132,7 +135,7 @@ type AuxCall struct { // At this point (active development of register ABI) that is very premature, // but if this turns out to be a cost, we could do it. func (a *AuxCall) Reg(i *regInfo, c *Config) *regInfo { - if a.reg.clobbers != 0 { + if !a.reg.clobbers.empty() { // Already updated return a.reg } @@ -146,7 +149,7 @@ func (a *AuxCall) Reg(i *regInfo, c *Config) *regInfo { for _, p := range a.abiInfo.InParams() { for _, r := range p.Registers { m := archRegForAbiReg(r, c) - a.reg.inputs = append(a.reg.inputs, inputInfo{idx: k, regs: (1 << m)}) + a.reg.inputs = append(a.reg.inputs, inputInfo{idx: k, regs: regMaskAt(register(m))}) k++ } } @@ -155,7 +158,7 @@ func (a *AuxCall) Reg(i *regInfo, c *Config) *regInfo { for _, p := range a.abiInfo.OutParams() { for _, r := range p.Registers { m := archRegForAbiReg(r, c) - a.reg.outputs = append(a.reg.outputs, outputInfo{idx: k, regs: (1 << m)}) + a.reg.outputs = append(a.reg.outputs, outputInfo{idx: k, regs: regMaskAt(register(m))}) k++ } } @@ -180,7 +183,7 @@ func (a *AuxCall) ResultReg(c *Config) *regInfo { for _, p := range a.abiInfo.OutParams() { for _, r := range p.Registers { m := archRegForAbiReg(r, c) - a.reg.inputs = append(a.reg.inputs, inputInfo{idx: k, regs: (1 << m)}) + a.reg.inputs = append(a.reg.inputs, inputInfo{idx: k, regs: regMaskAt(register(m))}) k++ } } @@ -381,6 +384,7 @@ const ( auxS390XCCMask // aux is a s390x 4-bit condition code mask auxS390XCCMaskInt8 // aux is a s390x 4-bit condition code mask, auxInt is an int8 immediate auxS390XCCMaskUint8 // aux is a s390x 4-bit condition code mask, auxInt is a uint8 immediate + auxSizeAndAlign // auxInt is an int64 size, aux is an int64 alignment ) // A SymEffect describes the effect that an SSA Value has on the variable diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go index 061f1333382af4..7aa8af2e78e5b9 100644 --- a/src/cmd/compile/internal/ssa/opGen.go +++ b/src/cmd/compile/internal/ssa/opGen.go @@ -386,6 +386,7 @@ const ( Op386ADDLcarry Op386ADDLconstcarry Op386ADCL + Op386ADCLcarry Op386ADCLconst Op386SUBL Op386SUBLconst @@ -560,6 +561,7 @@ const ( Op386REPSTOSL Op386CALLstatic Op386CALLtail + Op386CALLtailinter Op386CALLclosure Op386CALLinter Op386DUFFCOPY @@ -767,8 +769,6 @@ const ( OpAMD64SARLconst OpAMD64SARWconst OpAMD64SARBconst - OpAMD64SHRDQ - OpAMD64SHLDQ OpAMD64ROLQ OpAMD64ROLL OpAMD64ROLW @@ -928,6 +928,7 @@ const ( OpAMD64SQRTSD OpAMD64SQRTSS OpAMD64ROUNDSD + OpAMD64ROUNDSS OpAMD64LoweredRound32F OpAMD64LoweredRound64F OpAMD64VFMADD231SS @@ -1058,6 +1059,7 @@ const ( OpAMD64REPSTOSQ OpAMD64CALLstatic OpAMD64CALLtail + OpAMD64CALLtailinter OpAMD64CALLclosure OpAMD64CALLinter OpAMD64LoweredMove @@ -1167,6 +1169,3211 @@ const ( OpAMD64PSIGNB OpAMD64PCMPEQB OpAMD64PMOVMSKB + OpAMD64VMOVDQUload128 + OpAMD64VMOVDQUstore128 + OpAMD64VMOVDQUload256 + OpAMD64VMOVDQUstore256 + OpAMD64VMOVDQUload512 + OpAMD64VMOVDQUstore512 + OpAMD64VPMASK32load128 + OpAMD64VPMASK32store128 + OpAMD64VPMASK64load128 + OpAMD64VPMASK64store128 + OpAMD64VPMASK32load256 + OpAMD64VPMASK32store256 + OpAMD64VPMASK64load256 + OpAMD64VPMASK64store256 + OpAMD64VPMASK8load512 + OpAMD64VPMASK8store512 + OpAMD64VPMASK16load512 + OpAMD64VPMASK16store512 + OpAMD64VPMASK32load512 + OpAMD64VPMASK32store512 + OpAMD64VPMASK64load512 + OpAMD64VPMASK64store512 + OpAMD64VPMOVMToVec8x16 + OpAMD64VPMOVMToVec8x32 + OpAMD64VPMOVMToVec8x64 + OpAMD64VPMOVMToVec16x8 + OpAMD64VPMOVMToVec16x16 + OpAMD64VPMOVMToVec16x32 + OpAMD64VPMOVMToVec32x4 + OpAMD64VPMOVMToVec32x8 + OpAMD64VPMOVMToVec32x16 + OpAMD64VPMOVMToVec64x2 + OpAMD64VPMOVMToVec64x4 + OpAMD64VPMOVMToVec64x8 + OpAMD64VPMOVVec8x16ToM + OpAMD64VPMOVVec8x32ToM + OpAMD64VPMOVVec8x64ToM + OpAMD64VPMOVVec16x8ToM + OpAMD64VPMOVVec16x16ToM + OpAMD64VPMOVVec16x32ToM + OpAMD64VPMOVVec32x4ToM + OpAMD64VPMOVVec32x8ToM + OpAMD64VPMOVVec32x16ToM + OpAMD64VPMOVVec64x2ToM + OpAMD64VPMOVVec64x4ToM + OpAMD64VPMOVVec64x8ToM + OpAMD64VPMOVMSKB128 + OpAMD64VPMOVMSKB256 + OpAMD64VMOVMSKPS128 + OpAMD64VMOVMSKPS256 + OpAMD64VMOVMSKPD128 + OpAMD64VMOVMSKPD256 + OpAMD64Zero128 + OpAMD64Zero256 + OpAMD64Zero512 + OpAMD64VMOVSDf2v + OpAMD64VMOVSSf2v + OpAMD64VMOVQ + OpAMD64VMOVD + OpAMD64VMOVQload + OpAMD64VMOVDload + OpAMD64VMOVSSload + OpAMD64VMOVSDload + OpAMD64VMOVSSconst + OpAMD64VMOVSDconst + OpAMD64VZEROUPPER + OpAMD64VZEROALL + OpAMD64KMOVBload + OpAMD64KMOVWload + OpAMD64KMOVDload + OpAMD64KMOVQload + OpAMD64KMOVBstore + OpAMD64KMOVWstore + OpAMD64KMOVDstore + OpAMD64KMOVQstore + OpAMD64KMOVQk + OpAMD64KMOVDk + OpAMD64KMOVWk + OpAMD64KMOVBk + OpAMD64KMOVQi + OpAMD64KMOVDi + OpAMD64KMOVWi + OpAMD64KMOVBi + OpAMD64KANDB + OpAMD64KANDW + OpAMD64KANDD + OpAMD64KANDQ + OpAMD64KORB + OpAMD64KORW + OpAMD64KORD + OpAMD64KORQ + OpAMD64KXORB + OpAMD64KXORW + OpAMD64KXORD + OpAMD64KXORQ + OpAMD64KXNORB + OpAMD64KXNORW + OpAMD64KXNORD + OpAMD64KXNORQ + OpAMD64VPTEST + OpAMD64SHA1MSG1128 + OpAMD64SHA1MSG2128 + OpAMD64SHA1NEXTE128 + OpAMD64SHA256MSG1128 + OpAMD64SHA256MSG2128 + OpAMD64SHA256RNDS2128 + OpAMD64VADDPD128 + OpAMD64VADDPD256 + OpAMD64VADDPD512 + OpAMD64VADDPDMasked128 + OpAMD64VADDPDMasked256 + OpAMD64VADDPDMasked512 + OpAMD64VADDPS128 + OpAMD64VADDPS256 + OpAMD64VADDPS512 + OpAMD64VADDPSMasked128 + OpAMD64VADDPSMasked256 + OpAMD64VADDPSMasked512 + OpAMD64VADDSUBPD128 + OpAMD64VADDSUBPD256 + OpAMD64VADDSUBPS128 + OpAMD64VADDSUBPS256 + OpAMD64VAESDEC128 + OpAMD64VAESDEC256 + OpAMD64VAESDEC512 + OpAMD64VAESDECLAST128 + OpAMD64VAESDECLAST256 + OpAMD64VAESDECLAST512 + OpAMD64VAESENC128 + OpAMD64VAESENC256 + OpAMD64VAESENC512 + OpAMD64VAESENCLAST128 + OpAMD64VAESENCLAST256 + OpAMD64VAESENCLAST512 + OpAMD64VAESIMC128 + OpAMD64VBROADCASTSD256 + OpAMD64VBROADCASTSD512 + OpAMD64VBROADCASTSDMasked256 + OpAMD64VBROADCASTSDMasked512 + OpAMD64VBROADCASTSS128 + OpAMD64VBROADCASTSS256 + OpAMD64VBROADCASTSS512 + OpAMD64VBROADCASTSSMasked128 + OpAMD64VBROADCASTSSMasked256 + OpAMD64VBROADCASTSSMasked512 + OpAMD64VCOMPRESSPDMasked128 + OpAMD64VCOMPRESSPDMasked256 + OpAMD64VCOMPRESSPDMasked512 + OpAMD64VCOMPRESSPSMasked128 + OpAMD64VCOMPRESSPSMasked256 + OpAMD64VCOMPRESSPSMasked512 + OpAMD64VCVTDQ2PD256 + OpAMD64VCVTDQ2PD512 + OpAMD64VCVTDQ2PDMasked256 + OpAMD64VCVTDQ2PDMasked512 + OpAMD64VCVTDQ2PS128 + OpAMD64VCVTDQ2PS256 + OpAMD64VCVTDQ2PS512 + OpAMD64VCVTDQ2PSMasked128 + OpAMD64VCVTDQ2PSMasked256 + OpAMD64VCVTDQ2PSMasked512 + OpAMD64VCVTPD2PS256 + OpAMD64VCVTPD2PSMasked256 + OpAMD64VCVTPD2PSX128 + OpAMD64VCVTPD2PSXMasked128 + OpAMD64VCVTPD2PSY128 + OpAMD64VCVTPD2PSYMasked128 + OpAMD64VCVTPS2PD256 + OpAMD64VCVTPS2PD512 + OpAMD64VCVTPS2PDMasked256 + OpAMD64VCVTPS2PDMasked512 + OpAMD64VCVTQQ2PD128 + OpAMD64VCVTQQ2PD256 + OpAMD64VCVTQQ2PD512 + OpAMD64VCVTQQ2PDMasked128 + OpAMD64VCVTQQ2PDMasked256 + OpAMD64VCVTQQ2PDMasked512 + OpAMD64VCVTQQ2PS256 + OpAMD64VCVTQQ2PSMasked256 + OpAMD64VCVTQQ2PSX128 + OpAMD64VCVTQQ2PSXMasked128 + OpAMD64VCVTQQ2PSY128 + OpAMD64VCVTQQ2PSYMasked128 + OpAMD64VCVTTPD2DQ256 + OpAMD64VCVTTPD2DQMasked256 + OpAMD64VCVTTPD2DQX128 + OpAMD64VCVTTPD2DQXMasked128 + OpAMD64VCVTTPD2DQY128 + OpAMD64VCVTTPD2DQYMasked128 + OpAMD64VCVTTPD2QQ128 + OpAMD64VCVTTPD2QQ256 + OpAMD64VCVTTPD2QQ512 + OpAMD64VCVTTPD2QQMasked128 + OpAMD64VCVTTPD2QQMasked256 + OpAMD64VCVTTPD2QQMasked512 + OpAMD64VCVTTPD2UDQ256 + OpAMD64VCVTTPD2UDQMasked256 + OpAMD64VCVTTPD2UDQX128 + OpAMD64VCVTTPD2UDQXMasked128 + OpAMD64VCVTTPD2UDQY128 + OpAMD64VCVTTPD2UDQYMasked128 + OpAMD64VCVTTPD2UQQ128 + OpAMD64VCVTTPD2UQQ256 + OpAMD64VCVTTPD2UQQ512 + OpAMD64VCVTTPD2UQQMasked128 + OpAMD64VCVTTPD2UQQMasked256 + OpAMD64VCVTTPD2UQQMasked512 + OpAMD64VCVTTPS2DQ128 + OpAMD64VCVTTPS2DQ256 + OpAMD64VCVTTPS2DQ512 + OpAMD64VCVTTPS2DQMasked128 + OpAMD64VCVTTPS2DQMasked256 + OpAMD64VCVTTPS2DQMasked512 + OpAMD64VCVTTPS2QQ256 + OpAMD64VCVTTPS2QQ512 + OpAMD64VCVTTPS2QQMasked256 + OpAMD64VCVTTPS2QQMasked512 + OpAMD64VCVTTPS2UDQ128 + OpAMD64VCVTTPS2UDQ256 + OpAMD64VCVTTPS2UDQ512 + OpAMD64VCVTTPS2UDQMasked128 + OpAMD64VCVTTPS2UDQMasked256 + OpAMD64VCVTTPS2UDQMasked512 + OpAMD64VCVTTPS2UQQ256 + OpAMD64VCVTTPS2UQQ512 + OpAMD64VCVTTPS2UQQMasked256 + OpAMD64VCVTTPS2UQQMasked512 + OpAMD64VCVTUDQ2PD256 + OpAMD64VCVTUDQ2PD512 + OpAMD64VCVTUDQ2PDMasked256 + OpAMD64VCVTUDQ2PDMasked512 + OpAMD64VCVTUDQ2PS128 + OpAMD64VCVTUDQ2PS256 + OpAMD64VCVTUDQ2PS512 + OpAMD64VCVTUDQ2PSMasked128 + OpAMD64VCVTUDQ2PSMasked256 + OpAMD64VCVTUDQ2PSMasked512 + OpAMD64VCVTUQQ2PD128 + OpAMD64VCVTUQQ2PD256 + OpAMD64VCVTUQQ2PD512 + OpAMD64VCVTUQQ2PDMasked128 + OpAMD64VCVTUQQ2PDMasked256 + OpAMD64VCVTUQQ2PDMasked512 + OpAMD64VCVTUQQ2PS256 + OpAMD64VCVTUQQ2PSMasked256 + OpAMD64VCVTUQQ2PSX128 + OpAMD64VCVTUQQ2PSXMasked128 + OpAMD64VCVTUQQ2PSY128 + OpAMD64VCVTUQQ2PSYMasked128 + OpAMD64VDIVPD128 + OpAMD64VDIVPD256 + OpAMD64VDIVPD512 + OpAMD64VDIVPDMasked128 + OpAMD64VDIVPDMasked256 + OpAMD64VDIVPDMasked512 + OpAMD64VDIVPS128 + OpAMD64VDIVPS256 + OpAMD64VDIVPS512 + OpAMD64VDIVPSMasked128 + OpAMD64VDIVPSMasked256 + OpAMD64VDIVPSMasked512 + OpAMD64VEXPANDPDMasked128 + OpAMD64VEXPANDPDMasked256 + OpAMD64VEXPANDPDMasked512 + OpAMD64VEXPANDPSMasked128 + OpAMD64VEXPANDPSMasked256 + OpAMD64VEXPANDPSMasked512 + OpAMD64VFMADD213PD128 + OpAMD64VFMADD213PD256 + OpAMD64VFMADD213PD512 + OpAMD64VFMADD213PDMasked128 + OpAMD64VFMADD213PDMasked256 + OpAMD64VFMADD213PDMasked512 + OpAMD64VFMADD213PS128 + OpAMD64VFMADD213PS256 + OpAMD64VFMADD213PS512 + OpAMD64VFMADD213PSMasked128 + OpAMD64VFMADD213PSMasked256 + OpAMD64VFMADD213PSMasked512 + OpAMD64VFMADDSUB213PD128 + OpAMD64VFMADDSUB213PD256 + OpAMD64VFMADDSUB213PD512 + OpAMD64VFMADDSUB213PDMasked128 + OpAMD64VFMADDSUB213PDMasked256 + OpAMD64VFMADDSUB213PDMasked512 + OpAMD64VFMADDSUB213PS128 + OpAMD64VFMADDSUB213PS256 + OpAMD64VFMADDSUB213PS512 + OpAMD64VFMADDSUB213PSMasked128 + OpAMD64VFMADDSUB213PSMasked256 + OpAMD64VFMADDSUB213PSMasked512 + OpAMD64VFMSUBADD213PD128 + OpAMD64VFMSUBADD213PD256 + OpAMD64VFMSUBADD213PD512 + OpAMD64VFMSUBADD213PDMasked128 + OpAMD64VFMSUBADD213PDMasked256 + OpAMD64VFMSUBADD213PDMasked512 + OpAMD64VFMSUBADD213PS128 + OpAMD64VFMSUBADD213PS256 + OpAMD64VFMSUBADD213PS512 + OpAMD64VFMSUBADD213PSMasked128 + OpAMD64VFMSUBADD213PSMasked256 + OpAMD64VFMSUBADD213PSMasked512 + OpAMD64VGF2P8MULB128 + OpAMD64VGF2P8MULB256 + OpAMD64VGF2P8MULB512 + OpAMD64VGF2P8MULBMasked128 + OpAMD64VGF2P8MULBMasked256 + OpAMD64VGF2P8MULBMasked512 + OpAMD64VHADDPD128 + OpAMD64VHADDPD256 + OpAMD64VHADDPS128 + OpAMD64VHADDPS256 + OpAMD64VHSUBPD128 + OpAMD64VHSUBPD256 + OpAMD64VHSUBPS128 + OpAMD64VHSUBPS256 + OpAMD64VMAXPD128 + OpAMD64VMAXPD256 + OpAMD64VMAXPD512 + OpAMD64VMAXPDMasked128 + OpAMD64VMAXPDMasked256 + OpAMD64VMAXPDMasked512 + OpAMD64VMAXPS128 + OpAMD64VMAXPS256 + OpAMD64VMAXPS512 + OpAMD64VMAXPSMasked128 + OpAMD64VMAXPSMasked256 + OpAMD64VMAXPSMasked512 + OpAMD64VMINPD128 + OpAMD64VMINPD256 + OpAMD64VMINPD512 + OpAMD64VMINPDMasked128 + OpAMD64VMINPDMasked256 + OpAMD64VMINPDMasked512 + OpAMD64VMINPS128 + OpAMD64VMINPS256 + OpAMD64VMINPS512 + OpAMD64VMINPSMasked128 + OpAMD64VMINPSMasked256 + OpAMD64VMINPSMasked512 + OpAMD64VMOVDQU8Masked128 + OpAMD64VMOVDQU8Masked256 + OpAMD64VMOVDQU8Masked512 + OpAMD64VMOVDQU16Masked128 + OpAMD64VMOVDQU16Masked256 + OpAMD64VMOVDQU16Masked512 + OpAMD64VMOVDQU32Masked128 + OpAMD64VMOVDQU32Masked256 + OpAMD64VMOVDQU32Masked512 + OpAMD64VMOVDQU64Masked128 + OpAMD64VMOVDQU64Masked256 + OpAMD64VMOVDQU64Masked512 + OpAMD64VMULPD128 + OpAMD64VMULPD256 + OpAMD64VMULPD512 + OpAMD64VMULPDMasked128 + OpAMD64VMULPDMasked256 + OpAMD64VMULPDMasked512 + OpAMD64VMULPS128 + OpAMD64VMULPS256 + OpAMD64VMULPS512 + OpAMD64VMULPSMasked128 + OpAMD64VMULPSMasked256 + OpAMD64VMULPSMasked512 + OpAMD64VPABSB128 + OpAMD64VPABSB256 + OpAMD64VPABSB512 + OpAMD64VPABSBMasked128 + OpAMD64VPABSBMasked256 + OpAMD64VPABSBMasked512 + OpAMD64VPABSD128 + OpAMD64VPABSD256 + OpAMD64VPABSD512 + OpAMD64VPABSDMasked128 + OpAMD64VPABSDMasked256 + OpAMD64VPABSDMasked512 + OpAMD64VPABSQ128 + OpAMD64VPABSQ256 + OpAMD64VPABSQ512 + OpAMD64VPABSQMasked128 + OpAMD64VPABSQMasked256 + OpAMD64VPABSQMasked512 + OpAMD64VPABSW128 + OpAMD64VPABSW256 + OpAMD64VPABSW512 + OpAMD64VPABSWMasked128 + OpAMD64VPABSWMasked256 + OpAMD64VPABSWMasked512 + OpAMD64VPACKSSDW128 + OpAMD64VPACKSSDW256 + OpAMD64VPACKSSDW512 + OpAMD64VPACKSSDWMasked128 + OpAMD64VPACKSSDWMasked256 + OpAMD64VPACKSSDWMasked512 + OpAMD64VPACKUSDW128 + OpAMD64VPACKUSDW256 + OpAMD64VPACKUSDW512 + OpAMD64VPACKUSDWMasked128 + OpAMD64VPACKUSDWMasked256 + OpAMD64VPACKUSDWMasked512 + OpAMD64VPADDB128 + OpAMD64VPADDB256 + OpAMD64VPADDB512 + OpAMD64VPADDBMasked128 + OpAMD64VPADDBMasked256 + OpAMD64VPADDBMasked512 + OpAMD64VPADDD128 + OpAMD64VPADDD256 + OpAMD64VPADDD512 + OpAMD64VPADDDMasked128 + OpAMD64VPADDDMasked256 + OpAMD64VPADDDMasked512 + OpAMD64VPADDQ128 + OpAMD64VPADDQ256 + OpAMD64VPADDQ512 + OpAMD64VPADDQMasked128 + OpAMD64VPADDQMasked256 + OpAMD64VPADDQMasked512 + OpAMD64VPADDSB128 + OpAMD64VPADDSB256 + OpAMD64VPADDSB512 + OpAMD64VPADDSBMasked128 + OpAMD64VPADDSBMasked256 + OpAMD64VPADDSBMasked512 + OpAMD64VPADDSW128 + OpAMD64VPADDSW256 + OpAMD64VPADDSW512 + OpAMD64VPADDSWMasked128 + OpAMD64VPADDSWMasked256 + OpAMD64VPADDSWMasked512 + OpAMD64VPADDUSB128 + OpAMD64VPADDUSB256 + OpAMD64VPADDUSB512 + OpAMD64VPADDUSBMasked128 + OpAMD64VPADDUSBMasked256 + OpAMD64VPADDUSBMasked512 + OpAMD64VPADDUSW128 + OpAMD64VPADDUSW256 + OpAMD64VPADDUSW512 + OpAMD64VPADDUSWMasked128 + OpAMD64VPADDUSWMasked256 + OpAMD64VPADDUSWMasked512 + OpAMD64VPADDW128 + OpAMD64VPADDW256 + OpAMD64VPADDW512 + OpAMD64VPADDWMasked128 + OpAMD64VPADDWMasked256 + OpAMD64VPADDWMasked512 + OpAMD64VPAND128 + OpAMD64VPAND256 + OpAMD64VPANDD512 + OpAMD64VPANDDMasked128 + OpAMD64VPANDDMasked256 + OpAMD64VPANDDMasked512 + OpAMD64VPANDN128 + OpAMD64VPANDN256 + OpAMD64VPANDND512 + OpAMD64VPANDNDMasked128 + OpAMD64VPANDNDMasked256 + OpAMD64VPANDNDMasked512 + OpAMD64VPANDNQ512 + OpAMD64VPANDNQMasked128 + OpAMD64VPANDNQMasked256 + OpAMD64VPANDNQMasked512 + OpAMD64VPANDQ512 + OpAMD64VPANDQMasked128 + OpAMD64VPANDQMasked256 + OpAMD64VPANDQMasked512 + OpAMD64VPAVGB128 + OpAMD64VPAVGB256 + OpAMD64VPAVGB512 + OpAMD64VPAVGBMasked128 + OpAMD64VPAVGBMasked256 + OpAMD64VPAVGBMasked512 + OpAMD64VPAVGW128 + OpAMD64VPAVGW256 + OpAMD64VPAVGW512 + OpAMD64VPAVGWMasked128 + OpAMD64VPAVGWMasked256 + OpAMD64VPAVGWMasked512 + OpAMD64VPBLENDMBMasked512 + OpAMD64VPBLENDMDMasked512 + OpAMD64VPBLENDMQMasked512 + OpAMD64VPBLENDMWMasked512 + OpAMD64VPBLENDVB128 + OpAMD64VPBLENDVB256 + OpAMD64VPBROADCASTB128 + OpAMD64VPBROADCASTB256 + OpAMD64VPBROADCASTB512 + OpAMD64VPBROADCASTBMasked128 + OpAMD64VPBROADCASTBMasked256 + OpAMD64VPBROADCASTBMasked512 + OpAMD64VPBROADCASTD128 + OpAMD64VPBROADCASTD256 + OpAMD64VPBROADCASTD512 + OpAMD64VPBROADCASTDMasked128 + OpAMD64VPBROADCASTDMasked256 + OpAMD64VPBROADCASTDMasked512 + OpAMD64VPBROADCASTQ128 + OpAMD64VPBROADCASTQ256 + OpAMD64VPBROADCASTQ512 + OpAMD64VPBROADCASTQMasked128 + OpAMD64VPBROADCASTQMasked256 + OpAMD64VPBROADCASTQMasked512 + OpAMD64VPBROADCASTW128 + OpAMD64VPBROADCASTW256 + OpAMD64VPBROADCASTW512 + OpAMD64VPBROADCASTWMasked128 + OpAMD64VPBROADCASTWMasked256 + OpAMD64VPBROADCASTWMasked512 + OpAMD64VPCMPEQB128 + OpAMD64VPCMPEQB256 + OpAMD64VPCMPEQB512 + OpAMD64VPCMPEQD128 + OpAMD64VPCMPEQD256 + OpAMD64VPCMPEQD512 + OpAMD64VPCMPEQQ128 + OpAMD64VPCMPEQQ256 + OpAMD64VPCMPEQQ512 + OpAMD64VPCMPEQW128 + OpAMD64VPCMPEQW256 + OpAMD64VPCMPEQW512 + OpAMD64VPCMPGTB128 + OpAMD64VPCMPGTB256 + OpAMD64VPCMPGTB512 + OpAMD64VPCMPGTD128 + OpAMD64VPCMPGTD256 + OpAMD64VPCMPGTD512 + OpAMD64VPCMPGTQ128 + OpAMD64VPCMPGTQ256 + OpAMD64VPCMPGTQ512 + OpAMD64VPCMPGTW128 + OpAMD64VPCMPGTW256 + OpAMD64VPCMPGTW512 + OpAMD64VPCOMPRESSBMasked128 + OpAMD64VPCOMPRESSBMasked256 + OpAMD64VPCOMPRESSBMasked512 + OpAMD64VPCOMPRESSDMasked128 + OpAMD64VPCOMPRESSDMasked256 + OpAMD64VPCOMPRESSDMasked512 + OpAMD64VPCOMPRESSQMasked128 + OpAMD64VPCOMPRESSQMasked256 + OpAMD64VPCOMPRESSQMasked512 + OpAMD64VPCOMPRESSWMasked128 + OpAMD64VPCOMPRESSWMasked256 + OpAMD64VPCOMPRESSWMasked512 + OpAMD64VPDPWSSD128 + OpAMD64VPDPWSSD256 + OpAMD64VPDPWSSD512 + OpAMD64VPDPWSSDMasked128 + OpAMD64VPDPWSSDMasked256 + OpAMD64VPDPWSSDMasked512 + OpAMD64VPERMB128 + OpAMD64VPERMB256 + OpAMD64VPERMB512 + OpAMD64VPERMBMasked128 + OpAMD64VPERMBMasked256 + OpAMD64VPERMBMasked512 + OpAMD64VPERMD256 + OpAMD64VPERMD512 + OpAMD64VPERMDMasked256 + OpAMD64VPERMDMasked512 + OpAMD64VPERMI2B128 + OpAMD64VPERMI2B256 + OpAMD64VPERMI2B512 + OpAMD64VPERMI2BMasked128 + OpAMD64VPERMI2BMasked256 + OpAMD64VPERMI2BMasked512 + OpAMD64VPERMI2D128 + OpAMD64VPERMI2D256 + OpAMD64VPERMI2D512 + OpAMD64VPERMI2DMasked128 + OpAMD64VPERMI2DMasked256 + OpAMD64VPERMI2DMasked512 + OpAMD64VPERMI2PD128 + OpAMD64VPERMI2PD256 + OpAMD64VPERMI2PD512 + OpAMD64VPERMI2PDMasked128 + OpAMD64VPERMI2PDMasked256 + OpAMD64VPERMI2PDMasked512 + OpAMD64VPERMI2PS128 + OpAMD64VPERMI2PS256 + OpAMD64VPERMI2PS512 + OpAMD64VPERMI2PSMasked128 + OpAMD64VPERMI2PSMasked256 + OpAMD64VPERMI2PSMasked512 + OpAMD64VPERMI2Q128 + OpAMD64VPERMI2Q256 + OpAMD64VPERMI2Q512 + OpAMD64VPERMI2QMasked128 + OpAMD64VPERMI2QMasked256 + OpAMD64VPERMI2QMasked512 + OpAMD64VPERMI2W128 + OpAMD64VPERMI2W256 + OpAMD64VPERMI2W512 + OpAMD64VPERMI2WMasked128 + OpAMD64VPERMI2WMasked256 + OpAMD64VPERMI2WMasked512 + OpAMD64VPERMPD256 + OpAMD64VPERMPD512 + OpAMD64VPERMPDMasked256 + OpAMD64VPERMPDMasked512 + OpAMD64VPERMPS256 + OpAMD64VPERMPS512 + OpAMD64VPERMPSMasked256 + OpAMD64VPERMPSMasked512 + OpAMD64VPERMQ256 + OpAMD64VPERMQ512 + OpAMD64VPERMQMasked256 + OpAMD64VPERMQMasked512 + OpAMD64VPERMW128 + OpAMD64VPERMW256 + OpAMD64VPERMW512 + OpAMD64VPERMWMasked128 + OpAMD64VPERMWMasked256 + OpAMD64VPERMWMasked512 + OpAMD64VPEXPANDBMasked128 + OpAMD64VPEXPANDBMasked256 + OpAMD64VPEXPANDBMasked512 + OpAMD64VPEXPANDDMasked128 + OpAMD64VPEXPANDDMasked256 + OpAMD64VPEXPANDDMasked512 + OpAMD64VPEXPANDQMasked128 + OpAMD64VPEXPANDQMasked256 + OpAMD64VPEXPANDQMasked512 + OpAMD64VPEXPANDWMasked128 + OpAMD64VPEXPANDWMasked256 + OpAMD64VPEXPANDWMasked512 + OpAMD64VPHADDD128 + OpAMD64VPHADDD256 + OpAMD64VPHADDSW128 + OpAMD64VPHADDSW256 + OpAMD64VPHADDW128 + OpAMD64VPHADDW256 + OpAMD64VPHSUBD128 + OpAMD64VPHSUBD256 + OpAMD64VPHSUBSW128 + OpAMD64VPHSUBSW256 + OpAMD64VPHSUBW128 + OpAMD64VPHSUBW256 + OpAMD64VPLZCNTD128 + OpAMD64VPLZCNTD256 + OpAMD64VPLZCNTD512 + OpAMD64VPLZCNTDMasked128 + OpAMD64VPLZCNTDMasked256 + OpAMD64VPLZCNTDMasked512 + OpAMD64VPLZCNTQ128 + OpAMD64VPLZCNTQ256 + OpAMD64VPLZCNTQ512 + OpAMD64VPLZCNTQMasked128 + OpAMD64VPLZCNTQMasked256 + OpAMD64VPLZCNTQMasked512 + OpAMD64VPMADDUBSW128 + OpAMD64VPMADDUBSW256 + OpAMD64VPMADDUBSW512 + OpAMD64VPMADDUBSWMasked128 + OpAMD64VPMADDUBSWMasked256 + OpAMD64VPMADDUBSWMasked512 + OpAMD64VPMADDWD128 + OpAMD64VPMADDWD256 + OpAMD64VPMADDWD512 + OpAMD64VPMADDWDMasked128 + OpAMD64VPMADDWDMasked256 + OpAMD64VPMADDWDMasked512 + OpAMD64VPMAXSB128 + OpAMD64VPMAXSB256 + OpAMD64VPMAXSB512 + OpAMD64VPMAXSBMasked128 + OpAMD64VPMAXSBMasked256 + OpAMD64VPMAXSBMasked512 + OpAMD64VPMAXSD128 + OpAMD64VPMAXSD256 + OpAMD64VPMAXSD512 + OpAMD64VPMAXSDMasked128 + OpAMD64VPMAXSDMasked256 + OpAMD64VPMAXSDMasked512 + OpAMD64VPMAXSQ128 + OpAMD64VPMAXSQ256 + OpAMD64VPMAXSQ512 + OpAMD64VPMAXSQMasked128 + OpAMD64VPMAXSQMasked256 + OpAMD64VPMAXSQMasked512 + OpAMD64VPMAXSW128 + OpAMD64VPMAXSW256 + OpAMD64VPMAXSW512 + OpAMD64VPMAXSWMasked128 + OpAMD64VPMAXSWMasked256 + OpAMD64VPMAXSWMasked512 + OpAMD64VPMAXUB128 + OpAMD64VPMAXUB256 + OpAMD64VPMAXUB512 + OpAMD64VPMAXUBMasked128 + OpAMD64VPMAXUBMasked256 + OpAMD64VPMAXUBMasked512 + OpAMD64VPMAXUD128 + OpAMD64VPMAXUD256 + OpAMD64VPMAXUD512 + OpAMD64VPMAXUDMasked128 + OpAMD64VPMAXUDMasked256 + OpAMD64VPMAXUDMasked512 + OpAMD64VPMAXUQ128 + OpAMD64VPMAXUQ256 + OpAMD64VPMAXUQ512 + OpAMD64VPMAXUQMasked128 + OpAMD64VPMAXUQMasked256 + OpAMD64VPMAXUQMasked512 + OpAMD64VPMAXUW128 + OpAMD64VPMAXUW256 + OpAMD64VPMAXUW512 + OpAMD64VPMAXUWMasked128 + OpAMD64VPMAXUWMasked256 + OpAMD64VPMAXUWMasked512 + OpAMD64VPMINSB128 + OpAMD64VPMINSB256 + OpAMD64VPMINSB512 + OpAMD64VPMINSBMasked128 + OpAMD64VPMINSBMasked256 + OpAMD64VPMINSBMasked512 + OpAMD64VPMINSD128 + OpAMD64VPMINSD256 + OpAMD64VPMINSD512 + OpAMD64VPMINSDMasked128 + OpAMD64VPMINSDMasked256 + OpAMD64VPMINSDMasked512 + OpAMD64VPMINSQ128 + OpAMD64VPMINSQ256 + OpAMD64VPMINSQ512 + OpAMD64VPMINSQMasked128 + OpAMD64VPMINSQMasked256 + OpAMD64VPMINSQMasked512 + OpAMD64VPMINSW128 + OpAMD64VPMINSW256 + OpAMD64VPMINSW512 + OpAMD64VPMINSWMasked128 + OpAMD64VPMINSWMasked256 + OpAMD64VPMINSWMasked512 + OpAMD64VPMINUB128 + OpAMD64VPMINUB256 + OpAMD64VPMINUB512 + OpAMD64VPMINUBMasked128 + OpAMD64VPMINUBMasked256 + OpAMD64VPMINUBMasked512 + OpAMD64VPMINUD128 + OpAMD64VPMINUD256 + OpAMD64VPMINUD512 + OpAMD64VPMINUDMasked128 + OpAMD64VPMINUDMasked256 + OpAMD64VPMINUDMasked512 + OpAMD64VPMINUQ128 + OpAMD64VPMINUQ256 + OpAMD64VPMINUQ512 + OpAMD64VPMINUQMasked128 + OpAMD64VPMINUQMasked256 + OpAMD64VPMINUQMasked512 + OpAMD64VPMINUW128 + OpAMD64VPMINUW256 + OpAMD64VPMINUW512 + OpAMD64VPMINUWMasked128 + OpAMD64VPMINUWMasked256 + OpAMD64VPMINUWMasked512 + OpAMD64VPMOVDB128_128 + OpAMD64VPMOVDB128_256 + OpAMD64VPMOVDB128_512 + OpAMD64VPMOVDBMasked128_128 + OpAMD64VPMOVDBMasked128_256 + OpAMD64VPMOVDBMasked128_512 + OpAMD64VPMOVDW128_128 + OpAMD64VPMOVDW128_256 + OpAMD64VPMOVDW256 + OpAMD64VPMOVDWMasked128_128 + OpAMD64VPMOVDWMasked128_256 + OpAMD64VPMOVDWMasked256 + OpAMD64VPMOVQB128_128 + OpAMD64VPMOVQB128_256 + OpAMD64VPMOVQB128_512 + OpAMD64VPMOVQBMasked128_128 + OpAMD64VPMOVQBMasked128_256 + OpAMD64VPMOVQBMasked128_512 + OpAMD64VPMOVQD128_128 + OpAMD64VPMOVQD128_256 + OpAMD64VPMOVQD256 + OpAMD64VPMOVQDMasked128_128 + OpAMD64VPMOVQDMasked128_256 + OpAMD64VPMOVQDMasked256 + OpAMD64VPMOVQW128_128 + OpAMD64VPMOVQW128_256 + OpAMD64VPMOVQW128_512 + OpAMD64VPMOVQWMasked128_128 + OpAMD64VPMOVQWMasked128_256 + OpAMD64VPMOVQWMasked128_512 + OpAMD64VPMOVSDB128_128 + OpAMD64VPMOVSDB128_256 + OpAMD64VPMOVSDB128_512 + OpAMD64VPMOVSDBMasked128_128 + OpAMD64VPMOVSDBMasked128_256 + OpAMD64VPMOVSDBMasked128_512 + OpAMD64VPMOVSDW128_128 + OpAMD64VPMOVSDW128_256 + OpAMD64VPMOVSDW256 + OpAMD64VPMOVSDWMasked128_128 + OpAMD64VPMOVSDWMasked128_256 + OpAMD64VPMOVSDWMasked256 + OpAMD64VPMOVSQB128_128 + OpAMD64VPMOVSQB128_256 + OpAMD64VPMOVSQB128_512 + OpAMD64VPMOVSQBMasked128_128 + OpAMD64VPMOVSQBMasked128_256 + OpAMD64VPMOVSQBMasked128_512 + OpAMD64VPMOVSQD128_128 + OpAMD64VPMOVSQD128_256 + OpAMD64VPMOVSQD256 + OpAMD64VPMOVSQDMasked128_128 + OpAMD64VPMOVSQDMasked128_256 + OpAMD64VPMOVSQDMasked256 + OpAMD64VPMOVSQW128_128 + OpAMD64VPMOVSQW128_256 + OpAMD64VPMOVSQW128_512 + OpAMD64VPMOVSQWMasked128_128 + OpAMD64VPMOVSQWMasked128_256 + OpAMD64VPMOVSQWMasked128_512 + OpAMD64VPMOVSWB128_128 + OpAMD64VPMOVSWB128_256 + OpAMD64VPMOVSWB256 + OpAMD64VPMOVSWBMasked128_128 + OpAMD64VPMOVSWBMasked128_256 + OpAMD64VPMOVSWBMasked256 + OpAMD64VPMOVSXBD128 + OpAMD64VPMOVSXBD256 + OpAMD64VPMOVSXBD512 + OpAMD64VPMOVSXBDMasked128 + OpAMD64VPMOVSXBDMasked256 + OpAMD64VPMOVSXBDMasked512 + OpAMD64VPMOVSXBQ128 + OpAMD64VPMOVSXBQ256 + OpAMD64VPMOVSXBQ512 + OpAMD64VPMOVSXBQMasked128 + OpAMD64VPMOVSXBQMasked256 + OpAMD64VPMOVSXBQMasked512 + OpAMD64VPMOVSXBW128 + OpAMD64VPMOVSXBW256 + OpAMD64VPMOVSXBW512 + OpAMD64VPMOVSXBWMasked128 + OpAMD64VPMOVSXBWMasked256 + OpAMD64VPMOVSXBWMasked512 + OpAMD64VPMOVSXDQ128 + OpAMD64VPMOVSXDQ256 + OpAMD64VPMOVSXDQ512 + OpAMD64VPMOVSXDQMasked128 + OpAMD64VPMOVSXDQMasked256 + OpAMD64VPMOVSXDQMasked512 + OpAMD64VPMOVSXWD128 + OpAMD64VPMOVSXWD256 + OpAMD64VPMOVSXWD512 + OpAMD64VPMOVSXWDMasked128 + OpAMD64VPMOVSXWDMasked256 + OpAMD64VPMOVSXWDMasked512 + OpAMD64VPMOVSXWQ128 + OpAMD64VPMOVSXWQ256 + OpAMD64VPMOVSXWQ512 + OpAMD64VPMOVSXWQMasked128 + OpAMD64VPMOVSXWQMasked256 + OpAMD64VPMOVSXWQMasked512 + OpAMD64VPMOVUSDB128_128 + OpAMD64VPMOVUSDB128_256 + OpAMD64VPMOVUSDB128_512 + OpAMD64VPMOVUSDBMasked128_128 + OpAMD64VPMOVUSDBMasked128_256 + OpAMD64VPMOVUSDBMasked128_512 + OpAMD64VPMOVUSDW128_128 + OpAMD64VPMOVUSDW128_256 + OpAMD64VPMOVUSDW256 + OpAMD64VPMOVUSDWMasked128_128 + OpAMD64VPMOVUSDWMasked128_256 + OpAMD64VPMOVUSDWMasked256 + OpAMD64VPMOVUSQB128_128 + OpAMD64VPMOVUSQB128_256 + OpAMD64VPMOVUSQB128_512 + OpAMD64VPMOVUSQBMasked128_128 + OpAMD64VPMOVUSQBMasked128_256 + OpAMD64VPMOVUSQBMasked128_512 + OpAMD64VPMOVUSQD128_128 + OpAMD64VPMOVUSQD128_256 + OpAMD64VPMOVUSQD256 + OpAMD64VPMOVUSQDMasked128_128 + OpAMD64VPMOVUSQDMasked128_256 + OpAMD64VPMOVUSQDMasked256 + OpAMD64VPMOVUSQW128_128 + OpAMD64VPMOVUSQW128_256 + OpAMD64VPMOVUSQW128_512 + OpAMD64VPMOVUSQWMasked128_128 + OpAMD64VPMOVUSQWMasked128_256 + OpAMD64VPMOVUSQWMasked128_512 + OpAMD64VPMOVUSWB128_128 + OpAMD64VPMOVUSWB128_256 + OpAMD64VPMOVUSWB256 + OpAMD64VPMOVUSWBMasked128_128 + OpAMD64VPMOVUSWBMasked128_256 + OpAMD64VPMOVUSWBMasked256 + OpAMD64VPMOVWB128_128 + OpAMD64VPMOVWB128_256 + OpAMD64VPMOVWB256 + OpAMD64VPMOVWBMasked128_128 + OpAMD64VPMOVWBMasked128_256 + OpAMD64VPMOVWBMasked256 + OpAMD64VPMOVZXBD128 + OpAMD64VPMOVZXBD256 + OpAMD64VPMOVZXBD512 + OpAMD64VPMOVZXBDMasked128 + OpAMD64VPMOVZXBDMasked256 + OpAMD64VPMOVZXBDMasked512 + OpAMD64VPMOVZXBQ128 + OpAMD64VPMOVZXBQ256 + OpAMD64VPMOVZXBQ512 + OpAMD64VPMOVZXBQMasked128 + OpAMD64VPMOVZXBQMasked256 + OpAMD64VPMOVZXBQMasked512 + OpAMD64VPMOVZXBW128 + OpAMD64VPMOVZXBW256 + OpAMD64VPMOVZXBW512 + OpAMD64VPMOVZXBWMasked128 + OpAMD64VPMOVZXBWMasked256 + OpAMD64VPMOVZXBWMasked512 + OpAMD64VPMOVZXDQ128 + OpAMD64VPMOVZXDQ256 + OpAMD64VPMOVZXDQ512 + OpAMD64VPMOVZXDQMasked128 + OpAMD64VPMOVZXDQMasked256 + OpAMD64VPMOVZXDQMasked512 + OpAMD64VPMOVZXWD128 + OpAMD64VPMOVZXWD256 + OpAMD64VPMOVZXWD512 + OpAMD64VPMOVZXWDMasked128 + OpAMD64VPMOVZXWDMasked256 + OpAMD64VPMOVZXWDMasked512 + OpAMD64VPMOVZXWQ128 + OpAMD64VPMOVZXWQ256 + OpAMD64VPMOVZXWQ512 + OpAMD64VPMOVZXWQMasked128 + OpAMD64VPMOVZXWQMasked256 + OpAMD64VPMOVZXWQMasked512 + OpAMD64VPMULDQ128 + OpAMD64VPMULDQ256 + OpAMD64VPMULHUW128 + OpAMD64VPMULHUW256 + OpAMD64VPMULHUW512 + OpAMD64VPMULHUWMasked128 + OpAMD64VPMULHUWMasked256 + OpAMD64VPMULHUWMasked512 + OpAMD64VPMULHW128 + OpAMD64VPMULHW256 + OpAMD64VPMULHW512 + OpAMD64VPMULHWMasked128 + OpAMD64VPMULHWMasked256 + OpAMD64VPMULHWMasked512 + OpAMD64VPMULLD128 + OpAMD64VPMULLD256 + OpAMD64VPMULLD512 + OpAMD64VPMULLDMasked128 + OpAMD64VPMULLDMasked256 + OpAMD64VPMULLDMasked512 + OpAMD64VPMULLQ128 + OpAMD64VPMULLQ256 + OpAMD64VPMULLQ512 + OpAMD64VPMULLQMasked128 + OpAMD64VPMULLQMasked256 + OpAMD64VPMULLQMasked512 + OpAMD64VPMULLW128 + OpAMD64VPMULLW256 + OpAMD64VPMULLW512 + OpAMD64VPMULLWMasked128 + OpAMD64VPMULLWMasked256 + OpAMD64VPMULLWMasked512 + OpAMD64VPMULUDQ128 + OpAMD64VPMULUDQ256 + OpAMD64VPOPCNTB128 + OpAMD64VPOPCNTB256 + OpAMD64VPOPCNTB512 + OpAMD64VPOPCNTBMasked128 + OpAMD64VPOPCNTBMasked256 + OpAMD64VPOPCNTBMasked512 + OpAMD64VPOPCNTD128 + OpAMD64VPOPCNTD256 + OpAMD64VPOPCNTD512 + OpAMD64VPOPCNTDMasked128 + OpAMD64VPOPCNTDMasked256 + OpAMD64VPOPCNTDMasked512 + OpAMD64VPOPCNTQ128 + OpAMD64VPOPCNTQ256 + OpAMD64VPOPCNTQ512 + OpAMD64VPOPCNTQMasked128 + OpAMD64VPOPCNTQMasked256 + OpAMD64VPOPCNTQMasked512 + OpAMD64VPOPCNTW128 + OpAMD64VPOPCNTW256 + OpAMD64VPOPCNTW512 + OpAMD64VPOPCNTWMasked128 + OpAMD64VPOPCNTWMasked256 + OpAMD64VPOPCNTWMasked512 + OpAMD64VPOR128 + OpAMD64VPOR256 + OpAMD64VPORD512 + OpAMD64VPORDMasked128 + OpAMD64VPORDMasked256 + OpAMD64VPORDMasked512 + OpAMD64VPORQ512 + OpAMD64VPORQMasked128 + OpAMD64VPORQMasked256 + OpAMD64VPORQMasked512 + OpAMD64VPROLVD128 + OpAMD64VPROLVD256 + OpAMD64VPROLVD512 + OpAMD64VPROLVDMasked128 + OpAMD64VPROLVDMasked256 + OpAMD64VPROLVDMasked512 + OpAMD64VPROLVQ128 + OpAMD64VPROLVQ256 + OpAMD64VPROLVQ512 + OpAMD64VPROLVQMasked128 + OpAMD64VPROLVQMasked256 + OpAMD64VPROLVQMasked512 + OpAMD64VPRORVD128 + OpAMD64VPRORVD256 + OpAMD64VPRORVD512 + OpAMD64VPRORVDMasked128 + OpAMD64VPRORVDMasked256 + OpAMD64VPRORVDMasked512 + OpAMD64VPRORVQ128 + OpAMD64VPRORVQ256 + OpAMD64VPRORVQ512 + OpAMD64VPRORVQMasked128 + OpAMD64VPRORVQMasked256 + OpAMD64VPRORVQMasked512 + OpAMD64VPSADBW128 + OpAMD64VPSADBW256 + OpAMD64VPSADBW512 + OpAMD64VPSHLDVD128 + OpAMD64VPSHLDVD256 + OpAMD64VPSHLDVD512 + OpAMD64VPSHLDVDMasked128 + OpAMD64VPSHLDVDMasked256 + OpAMD64VPSHLDVDMasked512 + OpAMD64VPSHLDVQ128 + OpAMD64VPSHLDVQ256 + OpAMD64VPSHLDVQ512 + OpAMD64VPSHLDVQMasked128 + OpAMD64VPSHLDVQMasked256 + OpAMD64VPSHLDVQMasked512 + OpAMD64VPSHLDVW128 + OpAMD64VPSHLDVW256 + OpAMD64VPSHLDVW512 + OpAMD64VPSHLDVWMasked128 + OpAMD64VPSHLDVWMasked256 + OpAMD64VPSHLDVWMasked512 + OpAMD64VPSHRDVD128 + OpAMD64VPSHRDVD256 + OpAMD64VPSHRDVD512 + OpAMD64VPSHRDVDMasked128 + OpAMD64VPSHRDVDMasked256 + OpAMD64VPSHRDVDMasked512 + OpAMD64VPSHRDVQ128 + OpAMD64VPSHRDVQ256 + OpAMD64VPSHRDVQ512 + OpAMD64VPSHRDVQMasked128 + OpAMD64VPSHRDVQMasked256 + OpAMD64VPSHRDVQMasked512 + OpAMD64VPSHRDVW128 + OpAMD64VPSHRDVW256 + OpAMD64VPSHRDVW512 + OpAMD64VPSHRDVWMasked128 + OpAMD64VPSHRDVWMasked256 + OpAMD64VPSHRDVWMasked512 + OpAMD64VPSHUFB128 + OpAMD64VPSHUFB256 + OpAMD64VPSHUFB512 + OpAMD64VPSHUFBMasked128 + OpAMD64VPSHUFBMasked256 + OpAMD64VPSHUFBMasked512 + OpAMD64VPSIGNB128 + OpAMD64VPSIGNB256 + OpAMD64VPSIGND128 + OpAMD64VPSIGND256 + OpAMD64VPSIGNW128 + OpAMD64VPSIGNW256 + OpAMD64VPSLLD128 + OpAMD64VPSLLD256 + OpAMD64VPSLLD512 + OpAMD64VPSLLDMasked128 + OpAMD64VPSLLDMasked256 + OpAMD64VPSLLDMasked512 + OpAMD64VPSLLQ128 + OpAMD64VPSLLQ256 + OpAMD64VPSLLQ512 + OpAMD64VPSLLQMasked128 + OpAMD64VPSLLQMasked256 + OpAMD64VPSLLQMasked512 + OpAMD64VPSLLVD128 + OpAMD64VPSLLVD256 + OpAMD64VPSLLVD512 + OpAMD64VPSLLVDMasked128 + OpAMD64VPSLLVDMasked256 + OpAMD64VPSLLVDMasked512 + OpAMD64VPSLLVQ128 + OpAMD64VPSLLVQ256 + OpAMD64VPSLLVQ512 + OpAMD64VPSLLVQMasked128 + OpAMD64VPSLLVQMasked256 + OpAMD64VPSLLVQMasked512 + OpAMD64VPSLLVW128 + OpAMD64VPSLLVW256 + OpAMD64VPSLLVW512 + OpAMD64VPSLLVWMasked128 + OpAMD64VPSLLVWMasked256 + OpAMD64VPSLLVWMasked512 + OpAMD64VPSLLW128 + OpAMD64VPSLLW256 + OpAMD64VPSLLW512 + OpAMD64VPSLLWMasked128 + OpAMD64VPSLLWMasked256 + OpAMD64VPSLLWMasked512 + OpAMD64VPSRAD128 + OpAMD64VPSRAD256 + OpAMD64VPSRAD512 + OpAMD64VPSRADMasked128 + OpAMD64VPSRADMasked256 + OpAMD64VPSRADMasked512 + OpAMD64VPSRAQ128 + OpAMD64VPSRAQ256 + OpAMD64VPSRAQ512 + OpAMD64VPSRAQMasked128 + OpAMD64VPSRAQMasked256 + OpAMD64VPSRAQMasked512 + OpAMD64VPSRAVD128 + OpAMD64VPSRAVD256 + OpAMD64VPSRAVD512 + OpAMD64VPSRAVDMasked128 + OpAMD64VPSRAVDMasked256 + OpAMD64VPSRAVDMasked512 + OpAMD64VPSRAVQ128 + OpAMD64VPSRAVQ256 + OpAMD64VPSRAVQ512 + OpAMD64VPSRAVQMasked128 + OpAMD64VPSRAVQMasked256 + OpAMD64VPSRAVQMasked512 + OpAMD64VPSRAVW128 + OpAMD64VPSRAVW256 + OpAMD64VPSRAVW512 + OpAMD64VPSRAVWMasked128 + OpAMD64VPSRAVWMasked256 + OpAMD64VPSRAVWMasked512 + OpAMD64VPSRAW128 + OpAMD64VPSRAW256 + OpAMD64VPSRAW512 + OpAMD64VPSRAWMasked128 + OpAMD64VPSRAWMasked256 + OpAMD64VPSRAWMasked512 + OpAMD64VPSRLD128 + OpAMD64VPSRLD256 + OpAMD64VPSRLD512 + OpAMD64VPSRLDMasked128 + OpAMD64VPSRLDMasked256 + OpAMD64VPSRLDMasked512 + OpAMD64VPSRLQ128 + OpAMD64VPSRLQ256 + OpAMD64VPSRLQ512 + OpAMD64VPSRLQMasked128 + OpAMD64VPSRLQMasked256 + OpAMD64VPSRLQMasked512 + OpAMD64VPSRLVD128 + OpAMD64VPSRLVD256 + OpAMD64VPSRLVD512 + OpAMD64VPSRLVDMasked128 + OpAMD64VPSRLVDMasked256 + OpAMD64VPSRLVDMasked512 + OpAMD64VPSRLVQ128 + OpAMD64VPSRLVQ256 + OpAMD64VPSRLVQ512 + OpAMD64VPSRLVQMasked128 + OpAMD64VPSRLVQMasked256 + OpAMD64VPSRLVQMasked512 + OpAMD64VPSRLVW128 + OpAMD64VPSRLVW256 + OpAMD64VPSRLVW512 + OpAMD64VPSRLVWMasked128 + OpAMD64VPSRLVWMasked256 + OpAMD64VPSRLVWMasked512 + OpAMD64VPSRLW128 + OpAMD64VPSRLW256 + OpAMD64VPSRLW512 + OpAMD64VPSRLWMasked128 + OpAMD64VPSRLWMasked256 + OpAMD64VPSRLWMasked512 + OpAMD64VPSUBB128 + OpAMD64VPSUBB256 + OpAMD64VPSUBB512 + OpAMD64VPSUBBMasked128 + OpAMD64VPSUBBMasked256 + OpAMD64VPSUBBMasked512 + OpAMD64VPSUBD128 + OpAMD64VPSUBD256 + OpAMD64VPSUBD512 + OpAMD64VPSUBDMasked128 + OpAMD64VPSUBDMasked256 + OpAMD64VPSUBDMasked512 + OpAMD64VPSUBQ128 + OpAMD64VPSUBQ256 + OpAMD64VPSUBQ512 + OpAMD64VPSUBQMasked128 + OpAMD64VPSUBQMasked256 + OpAMD64VPSUBQMasked512 + OpAMD64VPSUBSB128 + OpAMD64VPSUBSB256 + OpAMD64VPSUBSB512 + OpAMD64VPSUBSBMasked128 + OpAMD64VPSUBSBMasked256 + OpAMD64VPSUBSBMasked512 + OpAMD64VPSUBSW128 + OpAMD64VPSUBSW256 + OpAMD64VPSUBSW512 + OpAMD64VPSUBSWMasked128 + OpAMD64VPSUBSWMasked256 + OpAMD64VPSUBSWMasked512 + OpAMD64VPSUBUSB128 + OpAMD64VPSUBUSB256 + OpAMD64VPSUBUSB512 + OpAMD64VPSUBUSBMasked128 + OpAMD64VPSUBUSBMasked256 + OpAMD64VPSUBUSBMasked512 + OpAMD64VPSUBUSW128 + OpAMD64VPSUBUSW256 + OpAMD64VPSUBUSW512 + OpAMD64VPSUBUSWMasked128 + OpAMD64VPSUBUSWMasked256 + OpAMD64VPSUBUSWMasked512 + OpAMD64VPSUBW128 + OpAMD64VPSUBW256 + OpAMD64VPSUBW512 + OpAMD64VPSUBWMasked128 + OpAMD64VPSUBWMasked256 + OpAMD64VPSUBWMasked512 + OpAMD64VPUNPCKHDQ128 + OpAMD64VPUNPCKHDQ256 + OpAMD64VPUNPCKHDQ512 + OpAMD64VPUNPCKHQDQ128 + OpAMD64VPUNPCKHQDQ256 + OpAMD64VPUNPCKHQDQ512 + OpAMD64VPUNPCKHWD128 + OpAMD64VPUNPCKHWD256 + OpAMD64VPUNPCKHWD512 + OpAMD64VPUNPCKLDQ128 + OpAMD64VPUNPCKLDQ256 + OpAMD64VPUNPCKLDQ512 + OpAMD64VPUNPCKLQDQ128 + OpAMD64VPUNPCKLQDQ256 + OpAMD64VPUNPCKLQDQ512 + OpAMD64VPUNPCKLWD128 + OpAMD64VPUNPCKLWD256 + OpAMD64VPUNPCKLWD512 + OpAMD64VPXOR128 + OpAMD64VPXOR256 + OpAMD64VPXORD512 + OpAMD64VPXORDMasked128 + OpAMD64VPXORDMasked256 + OpAMD64VPXORDMasked512 + OpAMD64VPXORQ512 + OpAMD64VPXORQMasked128 + OpAMD64VPXORQMasked256 + OpAMD64VPXORQMasked512 + OpAMD64VRCP14PD128 + OpAMD64VRCP14PD256 + OpAMD64VRCP14PD512 + OpAMD64VRCP14PDMasked128 + OpAMD64VRCP14PDMasked256 + OpAMD64VRCP14PDMasked512 + OpAMD64VRCP14PS512 + OpAMD64VRCP14PSMasked128 + OpAMD64VRCP14PSMasked256 + OpAMD64VRCP14PSMasked512 + OpAMD64VRCPPS128 + OpAMD64VRCPPS256 + OpAMD64VRSQRT14PD128 + OpAMD64VRSQRT14PD256 + OpAMD64VRSQRT14PD512 + OpAMD64VRSQRT14PDMasked128 + OpAMD64VRSQRT14PDMasked256 + OpAMD64VRSQRT14PDMasked512 + OpAMD64VRSQRT14PS512 + OpAMD64VRSQRT14PSMasked128 + OpAMD64VRSQRT14PSMasked256 + OpAMD64VRSQRT14PSMasked512 + OpAMD64VRSQRTPS128 + OpAMD64VRSQRTPS256 + OpAMD64VSCALEFPD128 + OpAMD64VSCALEFPD256 + OpAMD64VSCALEFPD512 + OpAMD64VSCALEFPDMasked128 + OpAMD64VSCALEFPDMasked256 + OpAMD64VSCALEFPDMasked512 + OpAMD64VSCALEFPS128 + OpAMD64VSCALEFPS256 + OpAMD64VSCALEFPS512 + OpAMD64VSCALEFPSMasked128 + OpAMD64VSCALEFPSMasked256 + OpAMD64VSCALEFPSMasked512 + OpAMD64VSQRTPD128 + OpAMD64VSQRTPD256 + OpAMD64VSQRTPD512 + OpAMD64VSQRTPDMasked128 + OpAMD64VSQRTPDMasked256 + OpAMD64VSQRTPDMasked512 + OpAMD64VSQRTPS128 + OpAMD64VSQRTPS256 + OpAMD64VSQRTPS512 + OpAMD64VSQRTPSMasked128 + OpAMD64VSQRTPSMasked256 + OpAMD64VSQRTPSMasked512 + OpAMD64VSUBPD128 + OpAMD64VSUBPD256 + OpAMD64VSUBPD512 + OpAMD64VSUBPDMasked128 + OpAMD64VSUBPDMasked256 + OpAMD64VSUBPDMasked512 + OpAMD64VSUBPS128 + OpAMD64VSUBPS256 + OpAMD64VSUBPS512 + OpAMD64VSUBPSMasked128 + OpAMD64VSUBPSMasked256 + OpAMD64VSUBPSMasked512 + OpAMD64SHA1RNDS4128 + OpAMD64VAESKEYGENASSIST128 + OpAMD64VCMPPD128 + OpAMD64VCMPPD256 + OpAMD64VCMPPD512 + OpAMD64VCMPPDMasked128 + OpAMD64VCMPPDMasked256 + OpAMD64VCMPPDMasked512 + OpAMD64VCMPPS128 + OpAMD64VCMPPS256 + OpAMD64VCMPPS512 + OpAMD64VCMPPSMasked128 + OpAMD64VCMPPSMasked256 + OpAMD64VCMPPSMasked512 + OpAMD64VEXTRACTF64X4256 + OpAMD64VEXTRACTF128128 + OpAMD64VEXTRACTI64X4256 + OpAMD64VEXTRACTI128128 + OpAMD64VGF2P8AFFINEINVQB128 + OpAMD64VGF2P8AFFINEINVQB256 + OpAMD64VGF2P8AFFINEINVQB512 + OpAMD64VGF2P8AFFINEINVQBMasked128 + OpAMD64VGF2P8AFFINEINVQBMasked256 + OpAMD64VGF2P8AFFINEINVQBMasked512 + OpAMD64VGF2P8AFFINEQB128 + OpAMD64VGF2P8AFFINEQB256 + OpAMD64VGF2P8AFFINEQB512 + OpAMD64VGF2P8AFFINEQBMasked128 + OpAMD64VGF2P8AFFINEQBMasked256 + OpAMD64VGF2P8AFFINEQBMasked512 + OpAMD64VINSERTF64X4512 + OpAMD64VINSERTF128256 + OpAMD64VINSERTI64X4512 + OpAMD64VINSERTI128256 + OpAMD64VPALIGNR128 + OpAMD64VPALIGNR256 + OpAMD64VPALIGNR512 + OpAMD64VPALIGNRMasked128 + OpAMD64VPALIGNRMasked256 + OpAMD64VPALIGNRMasked512 + OpAMD64VPCLMULQDQ128 + OpAMD64VPCLMULQDQ256 + OpAMD64VPCLMULQDQ512 + OpAMD64VPCMPB512 + OpAMD64VPCMPBMasked128 + OpAMD64VPCMPBMasked256 + OpAMD64VPCMPBMasked512 + OpAMD64VPCMPD512 + OpAMD64VPCMPDMasked128 + OpAMD64VPCMPDMasked256 + OpAMD64VPCMPDMasked512 + OpAMD64VPCMPQ512 + OpAMD64VPCMPQMasked128 + OpAMD64VPCMPQMasked256 + OpAMD64VPCMPQMasked512 + OpAMD64VPCMPUB512 + OpAMD64VPCMPUBMasked128 + OpAMD64VPCMPUBMasked256 + OpAMD64VPCMPUBMasked512 + OpAMD64VPCMPUD512 + OpAMD64VPCMPUDMasked128 + OpAMD64VPCMPUDMasked256 + OpAMD64VPCMPUDMasked512 + OpAMD64VPCMPUQ512 + OpAMD64VPCMPUQMasked128 + OpAMD64VPCMPUQMasked256 + OpAMD64VPCMPUQMasked512 + OpAMD64VPCMPUW512 + OpAMD64VPCMPUWMasked128 + OpAMD64VPCMPUWMasked256 + OpAMD64VPCMPUWMasked512 + OpAMD64VPCMPW512 + OpAMD64VPCMPWMasked128 + OpAMD64VPCMPWMasked256 + OpAMD64VPCMPWMasked512 + OpAMD64VPERM2F128256 + OpAMD64VPERM2I128256 + OpAMD64VPEXTRB128 + OpAMD64VPEXTRD128 + OpAMD64VPEXTRQ128 + OpAMD64VPEXTRW128 + OpAMD64VPINSRB128 + OpAMD64VPINSRD128 + OpAMD64VPINSRQ128 + OpAMD64VPINSRW128 + OpAMD64VPROLD128 + OpAMD64VPROLD256 + OpAMD64VPROLD512 + OpAMD64VPROLDMasked128 + OpAMD64VPROLDMasked256 + OpAMD64VPROLDMasked512 + OpAMD64VPROLQ128 + OpAMD64VPROLQ256 + OpAMD64VPROLQ512 + OpAMD64VPROLQMasked128 + OpAMD64VPROLQMasked256 + OpAMD64VPROLQMasked512 + OpAMD64VPRORD128 + OpAMD64VPRORD256 + OpAMD64VPRORD512 + OpAMD64VPRORDMasked128 + OpAMD64VPRORDMasked256 + OpAMD64VPRORDMasked512 + OpAMD64VPRORQ128 + OpAMD64VPRORQ256 + OpAMD64VPRORQ512 + OpAMD64VPRORQMasked128 + OpAMD64VPRORQMasked256 + OpAMD64VPRORQMasked512 + OpAMD64VPSHLDD128 + OpAMD64VPSHLDD256 + OpAMD64VPSHLDD512 + OpAMD64VPSHLDDMasked128 + OpAMD64VPSHLDDMasked256 + OpAMD64VPSHLDDMasked512 + OpAMD64VPSHLDQ128 + OpAMD64VPSHLDQ256 + OpAMD64VPSHLDQ512 + OpAMD64VPSHLDQMasked128 + OpAMD64VPSHLDQMasked256 + OpAMD64VPSHLDQMasked512 + OpAMD64VPSHLDW128 + OpAMD64VPSHLDW256 + OpAMD64VPSHLDW512 + OpAMD64VPSHLDWMasked128 + OpAMD64VPSHLDWMasked256 + OpAMD64VPSHLDWMasked512 + OpAMD64VPSHRDD128 + OpAMD64VPSHRDD256 + OpAMD64VPSHRDD512 + OpAMD64VPSHRDDMasked128 + OpAMD64VPSHRDDMasked256 + OpAMD64VPSHRDDMasked512 + OpAMD64VPSHRDQ128 + OpAMD64VPSHRDQ256 + OpAMD64VPSHRDQ512 + OpAMD64VPSHRDQMasked128 + OpAMD64VPSHRDQMasked256 + OpAMD64VPSHRDQMasked512 + OpAMD64VPSHRDW128 + OpAMD64VPSHRDW256 + OpAMD64VPSHRDW512 + OpAMD64VPSHRDWMasked128 + OpAMD64VPSHRDWMasked256 + OpAMD64VPSHRDWMasked512 + OpAMD64VPSHUFD128 + OpAMD64VPSHUFD256 + OpAMD64VPSHUFD512 + OpAMD64VPSHUFDMasked128 + OpAMD64VPSHUFDMasked256 + OpAMD64VPSHUFDMasked512 + OpAMD64VPSHUFHW128 + OpAMD64VPSHUFHW256 + OpAMD64VPSHUFHW512 + OpAMD64VPSHUFHWMasked128 + OpAMD64VPSHUFHWMasked256 + OpAMD64VPSHUFHWMasked512 + OpAMD64VPSHUFLW128 + OpAMD64VPSHUFLW256 + OpAMD64VPSHUFLW512 + OpAMD64VPSHUFLWMasked128 + OpAMD64VPSHUFLWMasked256 + OpAMD64VPSHUFLWMasked512 + OpAMD64VPSLLD128const + OpAMD64VPSLLD256const + OpAMD64VPSLLD512const + OpAMD64VPSLLDMasked128const + OpAMD64VPSLLDMasked256const + OpAMD64VPSLLDMasked512const + OpAMD64VPSLLQ128const + OpAMD64VPSLLQ256const + OpAMD64VPSLLQ512const + OpAMD64VPSLLQMasked128const + OpAMD64VPSLLQMasked256const + OpAMD64VPSLLQMasked512const + OpAMD64VPSLLW128const + OpAMD64VPSLLW256const + OpAMD64VPSLLW512const + OpAMD64VPSLLWMasked128const + OpAMD64VPSLLWMasked256const + OpAMD64VPSLLWMasked512const + OpAMD64VPSRAD128const + OpAMD64VPSRAD256const + OpAMD64VPSRAD512const + OpAMD64VPSRADMasked128const + OpAMD64VPSRADMasked256const + OpAMD64VPSRADMasked512const + OpAMD64VPSRAQ128const + OpAMD64VPSRAQ256const + OpAMD64VPSRAQ512const + OpAMD64VPSRAQMasked128const + OpAMD64VPSRAQMasked256const + OpAMD64VPSRAQMasked512const + OpAMD64VPSRAW128const + OpAMD64VPSRAW256const + OpAMD64VPSRAW512const + OpAMD64VPSRAWMasked128const + OpAMD64VPSRAWMasked256const + OpAMD64VPSRAWMasked512const + OpAMD64VPSRLD128const + OpAMD64VPSRLD256const + OpAMD64VPSRLD512const + OpAMD64VPSRLDMasked128const + OpAMD64VPSRLDMasked256const + OpAMD64VPSRLDMasked512const + OpAMD64VPSRLQ128const + OpAMD64VPSRLQ256const + OpAMD64VPSRLQ512const + OpAMD64VPSRLQMasked128const + OpAMD64VPSRLQMasked256const + OpAMD64VPSRLQMasked512const + OpAMD64VPSRLW128const + OpAMD64VPSRLW256const + OpAMD64VPSRLW512const + OpAMD64VPSRLWMasked128const + OpAMD64VPSRLWMasked256const + OpAMD64VPSRLWMasked512const + OpAMD64VPTERNLOGD128 + OpAMD64VPTERNLOGD256 + OpAMD64VPTERNLOGD512 + OpAMD64VPTERNLOGQ128 + OpAMD64VPTERNLOGQ256 + OpAMD64VPTERNLOGQ512 + OpAMD64VREDUCEPD128 + OpAMD64VREDUCEPD256 + OpAMD64VREDUCEPD512 + OpAMD64VREDUCEPDMasked128 + OpAMD64VREDUCEPDMasked256 + OpAMD64VREDUCEPDMasked512 + OpAMD64VREDUCEPS128 + OpAMD64VREDUCEPS256 + OpAMD64VREDUCEPS512 + OpAMD64VREDUCEPSMasked128 + OpAMD64VREDUCEPSMasked256 + OpAMD64VREDUCEPSMasked512 + OpAMD64VRNDSCALEPD128 + OpAMD64VRNDSCALEPD256 + OpAMD64VRNDSCALEPD512 + OpAMD64VRNDSCALEPDMasked128 + OpAMD64VRNDSCALEPDMasked256 + OpAMD64VRNDSCALEPDMasked512 + OpAMD64VRNDSCALEPS128 + OpAMD64VRNDSCALEPS256 + OpAMD64VRNDSCALEPS512 + OpAMD64VRNDSCALEPSMasked128 + OpAMD64VRNDSCALEPSMasked256 + OpAMD64VRNDSCALEPSMasked512 + OpAMD64VROUNDPD128 + OpAMD64VROUNDPD256 + OpAMD64VROUNDPS128 + OpAMD64VROUNDPS256 + OpAMD64VSHUFPD128 + OpAMD64VSHUFPD256 + OpAMD64VSHUFPD512 + OpAMD64VSHUFPS128 + OpAMD64VSHUFPS256 + OpAMD64VSHUFPS512 + OpAMD64VADDPD128load + OpAMD64VADDPD256load + OpAMD64VADDPD512load + OpAMD64VADDPDMasked128load + OpAMD64VADDPDMasked256load + OpAMD64VADDPDMasked512load + OpAMD64VADDPS128load + OpAMD64VADDPS256load + OpAMD64VADDPS512load + OpAMD64VADDPSMasked128load + OpAMD64VADDPSMasked256load + OpAMD64VADDPSMasked512load + OpAMD64VADDSUBPD128load + OpAMD64VADDSUBPD256load + OpAMD64VADDSUBPS128load + OpAMD64VADDSUBPS256load + OpAMD64VAESDEC128load + OpAMD64VAESDEC256load + OpAMD64VAESDECLAST128load + OpAMD64VAESDECLAST256load + OpAMD64VAESENC128load + OpAMD64VAESENC256load + OpAMD64VAESENCLAST128load + OpAMD64VAESENCLAST256load + OpAMD64VAESIMC128load + OpAMD64VBROADCASTSD256load + OpAMD64VBROADCASTSD512load + OpAMD64VBROADCASTSDMasked256load + OpAMD64VBROADCASTSDMasked512load + OpAMD64VBROADCASTSS128load + OpAMD64VBROADCASTSS256load + OpAMD64VBROADCASTSS512load + OpAMD64VBROADCASTSSMasked128load + OpAMD64VBROADCASTSSMasked256load + OpAMD64VBROADCASTSSMasked512load + OpAMD64VCVTDQ2PD256load + OpAMD64VCVTDQ2PD512load + OpAMD64VCVTDQ2PDMasked256load + OpAMD64VCVTDQ2PDMasked512load + OpAMD64VCVTDQ2PS128load + OpAMD64VCVTDQ2PS256load + OpAMD64VCVTDQ2PS512load + OpAMD64VCVTDQ2PSMasked128load + OpAMD64VCVTDQ2PSMasked256load + OpAMD64VCVTDQ2PSMasked512load + OpAMD64VCVTPD2PS256load + OpAMD64VCVTPD2PSMasked256load + OpAMD64VCVTPD2PSX128load + OpAMD64VCVTPD2PSXMasked128load + OpAMD64VCVTPD2PSY128load + OpAMD64VCVTPD2PSYMasked128load + OpAMD64VCVTPS2PD256load + OpAMD64VCVTPS2PD512load + OpAMD64VCVTPS2PDMasked256load + OpAMD64VCVTPS2PDMasked512load + OpAMD64VCVTQQ2PD128load + OpAMD64VCVTQQ2PD256load + OpAMD64VCVTQQ2PD512load + OpAMD64VCVTQQ2PDMasked128load + OpAMD64VCVTQQ2PDMasked256load + OpAMD64VCVTQQ2PDMasked512load + OpAMD64VCVTQQ2PS256load + OpAMD64VCVTQQ2PSMasked256load + OpAMD64VCVTQQ2PSX128load + OpAMD64VCVTQQ2PSXMasked128load + OpAMD64VCVTQQ2PSY128load + OpAMD64VCVTQQ2PSYMasked128load + OpAMD64VCVTTPD2DQ256load + OpAMD64VCVTTPD2DQMasked256load + OpAMD64VCVTTPD2DQX128load + OpAMD64VCVTTPD2DQXMasked128load + OpAMD64VCVTTPD2DQY128load + OpAMD64VCVTTPD2DQYMasked128load + OpAMD64VCVTTPD2QQ128load + OpAMD64VCVTTPD2QQ256load + OpAMD64VCVTTPD2QQ512load + OpAMD64VCVTTPD2QQMasked128load + OpAMD64VCVTTPD2QQMasked256load + OpAMD64VCVTTPD2QQMasked512load + OpAMD64VCVTTPD2UDQ256load + OpAMD64VCVTTPD2UDQMasked256load + OpAMD64VCVTTPD2UDQX128load + OpAMD64VCVTTPD2UDQXMasked128load + OpAMD64VCVTTPD2UDQY128load + OpAMD64VCVTTPD2UDQYMasked128load + OpAMD64VCVTTPD2UQQ128load + OpAMD64VCVTTPD2UQQ256load + OpAMD64VCVTTPD2UQQ512load + OpAMD64VCVTTPD2UQQMasked128load + OpAMD64VCVTTPD2UQQMasked256load + OpAMD64VCVTTPD2UQQMasked512load + OpAMD64VCVTTPS2DQ128load + OpAMD64VCVTTPS2DQ256load + OpAMD64VCVTTPS2DQ512load + OpAMD64VCVTTPS2DQMasked128load + OpAMD64VCVTTPS2DQMasked256load + OpAMD64VCVTTPS2DQMasked512load + OpAMD64VCVTTPS2QQ256load + OpAMD64VCVTTPS2QQ512load + OpAMD64VCVTTPS2QQMasked256load + OpAMD64VCVTTPS2QQMasked512load + OpAMD64VCVTTPS2UDQ128load + OpAMD64VCVTTPS2UDQ256load + OpAMD64VCVTTPS2UDQ512load + OpAMD64VCVTTPS2UDQMasked128load + OpAMD64VCVTTPS2UDQMasked256load + OpAMD64VCVTTPS2UDQMasked512load + OpAMD64VCVTTPS2UQQ256load + OpAMD64VCVTTPS2UQQ512load + OpAMD64VCVTTPS2UQQMasked256load + OpAMD64VCVTTPS2UQQMasked512load + OpAMD64VCVTUDQ2PD256load + OpAMD64VCVTUDQ2PD512load + OpAMD64VCVTUDQ2PDMasked256load + OpAMD64VCVTUDQ2PDMasked512load + OpAMD64VCVTUDQ2PS128load + OpAMD64VCVTUDQ2PS256load + OpAMD64VCVTUDQ2PS512load + OpAMD64VCVTUDQ2PSMasked128load + OpAMD64VCVTUDQ2PSMasked256load + OpAMD64VCVTUDQ2PSMasked512load + OpAMD64VCVTUQQ2PD128load + OpAMD64VCVTUQQ2PD256load + OpAMD64VCVTUQQ2PD512load + OpAMD64VCVTUQQ2PDMasked128load + OpAMD64VCVTUQQ2PDMasked256load + OpAMD64VCVTUQQ2PDMasked512load + OpAMD64VCVTUQQ2PS256load + OpAMD64VCVTUQQ2PSMasked256load + OpAMD64VCVTUQQ2PSX128load + OpAMD64VCVTUQQ2PSXMasked128load + OpAMD64VCVTUQQ2PSY128load + OpAMD64VCVTUQQ2PSYMasked128load + OpAMD64VDIVPD128load + OpAMD64VDIVPD256load + OpAMD64VDIVPD512load + OpAMD64VDIVPDMasked128load + OpAMD64VDIVPDMasked256load + OpAMD64VDIVPDMasked512load + OpAMD64VDIVPS128load + OpAMD64VDIVPS256load + OpAMD64VDIVPS512load + OpAMD64VDIVPSMasked128load + OpAMD64VDIVPSMasked256load + OpAMD64VDIVPSMasked512load + OpAMD64VEXPANDPDMasked128load + OpAMD64VEXPANDPDMasked256load + OpAMD64VEXPANDPSMasked128load + OpAMD64VEXPANDPSMasked256load + OpAMD64VFMADD213PD128load + OpAMD64VFMADD213PD256load + OpAMD64VFMADD213PD512load + OpAMD64VFMADD213PDMasked128load + OpAMD64VFMADD213PDMasked256load + OpAMD64VFMADD213PDMasked512load + OpAMD64VFMADD213PS128load + OpAMD64VFMADD213PS256load + OpAMD64VFMADD213PS512load + OpAMD64VFMADD213PSMasked128load + OpAMD64VFMADD213PSMasked256load + OpAMD64VFMADD213PSMasked512load + OpAMD64VFMADDSUB213PD128load + OpAMD64VFMADDSUB213PD256load + OpAMD64VFMADDSUB213PD512load + OpAMD64VFMADDSUB213PDMasked128load + OpAMD64VFMADDSUB213PDMasked256load + OpAMD64VFMADDSUB213PDMasked512load + OpAMD64VFMADDSUB213PS128load + OpAMD64VFMADDSUB213PS256load + OpAMD64VFMADDSUB213PS512load + OpAMD64VFMADDSUB213PSMasked128load + OpAMD64VFMADDSUB213PSMasked256load + OpAMD64VFMADDSUB213PSMasked512load + OpAMD64VFMSUBADD213PD128load + OpAMD64VFMSUBADD213PD256load + OpAMD64VFMSUBADD213PD512load + OpAMD64VFMSUBADD213PDMasked128load + OpAMD64VFMSUBADD213PDMasked256load + OpAMD64VFMSUBADD213PDMasked512load + OpAMD64VFMSUBADD213PS128load + OpAMD64VFMSUBADD213PS256load + OpAMD64VFMSUBADD213PS512load + OpAMD64VFMSUBADD213PSMasked128load + OpAMD64VFMSUBADD213PSMasked256load + OpAMD64VFMSUBADD213PSMasked512load + OpAMD64VGF2P8MULB128load + OpAMD64VGF2P8MULB256load + OpAMD64VGF2P8MULBMasked128load + OpAMD64VGF2P8MULBMasked256load + OpAMD64VHADDPD128load + OpAMD64VHADDPD256load + OpAMD64VHADDPS128load + OpAMD64VHADDPS256load + OpAMD64VHSUBPD128load + OpAMD64VHSUBPD256load + OpAMD64VHSUBPS128load + OpAMD64VHSUBPS256load + OpAMD64VMAXPD128load + OpAMD64VMAXPD256load + OpAMD64VMAXPD512load + OpAMD64VMAXPDMasked128load + OpAMD64VMAXPDMasked256load + OpAMD64VMAXPDMasked512load + OpAMD64VMAXPS128load + OpAMD64VMAXPS256load + OpAMD64VMAXPS512load + OpAMD64VMAXPSMasked128load + OpAMD64VMAXPSMasked256load + OpAMD64VMAXPSMasked512load + OpAMD64VMINPD128load + OpAMD64VMINPD256load + OpAMD64VMINPD512load + OpAMD64VMINPDMasked128load + OpAMD64VMINPDMasked256load + OpAMD64VMINPDMasked512load + OpAMD64VMINPS128load + OpAMD64VMINPS256load + OpAMD64VMINPS512load + OpAMD64VMINPSMasked128load + OpAMD64VMINPSMasked256load + OpAMD64VMINPSMasked512load + OpAMD64VMULPD128load + OpAMD64VMULPD256load + OpAMD64VMULPD512load + OpAMD64VMULPDMasked128load + OpAMD64VMULPDMasked256load + OpAMD64VMULPDMasked512load + OpAMD64VMULPS128load + OpAMD64VMULPS256load + OpAMD64VMULPS512load + OpAMD64VMULPSMasked128load + OpAMD64VMULPSMasked256load + OpAMD64VMULPSMasked512load + OpAMD64VPABSB128load + OpAMD64VPABSB256load + OpAMD64VPABSBMasked128load + OpAMD64VPABSBMasked256load + OpAMD64VPABSD128load + OpAMD64VPABSD256load + OpAMD64VPABSD512load + OpAMD64VPABSDMasked128load + OpAMD64VPABSDMasked256load + OpAMD64VPABSDMasked512load + OpAMD64VPABSQ128load + OpAMD64VPABSQ256load + OpAMD64VPABSQ512load + OpAMD64VPABSQMasked128load + OpAMD64VPABSQMasked256load + OpAMD64VPABSQMasked512load + OpAMD64VPABSW128load + OpAMD64VPABSW256load + OpAMD64VPABSWMasked128load + OpAMD64VPABSWMasked256load + OpAMD64VPACKSSDW128load + OpAMD64VPACKSSDW256load + OpAMD64VPACKSSDW512load + OpAMD64VPACKSSDWMasked128load + OpAMD64VPACKSSDWMasked256load + OpAMD64VPACKSSDWMasked512load + OpAMD64VPACKUSDW128load + OpAMD64VPACKUSDW256load + OpAMD64VPACKUSDW512load + OpAMD64VPACKUSDWMasked128load + OpAMD64VPACKUSDWMasked256load + OpAMD64VPACKUSDWMasked512load + OpAMD64VPADDB128load + OpAMD64VPADDB256load + OpAMD64VPADDBMasked128load + OpAMD64VPADDBMasked256load + OpAMD64VPADDD128load + OpAMD64VPADDD256load + OpAMD64VPADDD512load + OpAMD64VPADDDMasked128load + OpAMD64VPADDDMasked256load + OpAMD64VPADDDMasked512load + OpAMD64VPADDQ128load + OpAMD64VPADDQ256load + OpAMD64VPADDQ512load + OpAMD64VPADDQMasked128load + OpAMD64VPADDQMasked256load + OpAMD64VPADDQMasked512load + OpAMD64VPADDSB128load + OpAMD64VPADDSB256load + OpAMD64VPADDSBMasked128load + OpAMD64VPADDSBMasked256load + OpAMD64VPADDSW128load + OpAMD64VPADDSW256load + OpAMD64VPADDSWMasked128load + OpAMD64VPADDSWMasked256load + OpAMD64VPADDUSB128load + OpAMD64VPADDUSB256load + OpAMD64VPADDUSBMasked128load + OpAMD64VPADDUSBMasked256load + OpAMD64VPADDUSW128load + OpAMD64VPADDUSW256load + OpAMD64VPADDUSWMasked128load + OpAMD64VPADDUSWMasked256load + OpAMD64VPADDW128load + OpAMD64VPADDW256load + OpAMD64VPADDWMasked128load + OpAMD64VPADDWMasked256load + OpAMD64VPAND128load + OpAMD64VPAND256load + OpAMD64VPANDD512load + OpAMD64VPANDDMasked128load + OpAMD64VPANDDMasked256load + OpAMD64VPANDDMasked512load + OpAMD64VPANDN128load + OpAMD64VPANDN256load + OpAMD64VPANDND512load + OpAMD64VPANDNDMasked128load + OpAMD64VPANDNDMasked256load + OpAMD64VPANDNDMasked512load + OpAMD64VPANDNQ512load + OpAMD64VPANDNQMasked128load + OpAMD64VPANDNQMasked256load + OpAMD64VPANDNQMasked512load + OpAMD64VPANDQ512load + OpAMD64VPANDQMasked128load + OpAMD64VPANDQMasked256load + OpAMD64VPANDQMasked512load + OpAMD64VPAVGB128load + OpAMD64VPAVGB256load + OpAMD64VPAVGBMasked128load + OpAMD64VPAVGBMasked256load + OpAMD64VPAVGW128load + OpAMD64VPAVGW256load + OpAMD64VPAVGWMasked128load + OpAMD64VPAVGWMasked256load + OpAMD64VPBLENDMDMasked512load + OpAMD64VPBLENDMQMasked512load + OpAMD64VPBROADCASTB128load + OpAMD64VPBROADCASTB256load + OpAMD64VPBROADCASTB512load + OpAMD64VPBROADCASTBMasked128load + OpAMD64VPBROADCASTBMasked256load + OpAMD64VPBROADCASTBMasked512load + OpAMD64VPBROADCASTD128load + OpAMD64VPBROADCASTD256load + OpAMD64VPBROADCASTD512load + OpAMD64VPBROADCASTDMasked128load + OpAMD64VPBROADCASTDMasked256load + OpAMD64VPBROADCASTDMasked512load + OpAMD64VPBROADCASTQ128load + OpAMD64VPBROADCASTQ256load + OpAMD64VPBROADCASTQ512load + OpAMD64VPBROADCASTQMasked128load + OpAMD64VPBROADCASTQMasked256load + OpAMD64VPBROADCASTQMasked512load + OpAMD64VPBROADCASTW128load + OpAMD64VPBROADCASTW256load + OpAMD64VPCMPEQB128load + OpAMD64VPCMPEQB256load + OpAMD64VPCMPEQD128load + OpAMD64VPCMPEQD256load + OpAMD64VPCMPEQD512load + OpAMD64VPCMPEQQ128load + OpAMD64VPCMPEQQ256load + OpAMD64VPCMPEQQ512load + OpAMD64VPCMPEQW128load + OpAMD64VPCMPEQW256load + OpAMD64VPCMPGTB128load + OpAMD64VPCMPGTB256load + OpAMD64VPCMPGTD128load + OpAMD64VPCMPGTD256load + OpAMD64VPCMPGTD512load + OpAMD64VPCMPGTQ128load + OpAMD64VPCMPGTQ256load + OpAMD64VPCMPGTQ512load + OpAMD64VPCMPGTW128load + OpAMD64VPCMPGTW256load + OpAMD64VPDPWSSD128load + OpAMD64VPDPWSSD256load + OpAMD64VPDPWSSD512load + OpAMD64VPDPWSSDMasked128load + OpAMD64VPDPWSSDMasked256load + OpAMD64VPDPWSSDMasked512load + OpAMD64VPERMB128load + OpAMD64VPERMB256load + OpAMD64VPERMBMasked128load + OpAMD64VPERMBMasked256load + OpAMD64VPERMD256load + OpAMD64VPERMD512load + OpAMD64VPERMDMasked256load + OpAMD64VPERMDMasked512load + OpAMD64VPERMI2B128load + OpAMD64VPERMI2B256load + OpAMD64VPERMI2BMasked128load + OpAMD64VPERMI2BMasked256load + OpAMD64VPERMI2D128load + OpAMD64VPERMI2D256load + OpAMD64VPERMI2D512load + OpAMD64VPERMI2DMasked128load + OpAMD64VPERMI2DMasked256load + OpAMD64VPERMI2DMasked512load + OpAMD64VPERMI2PD128load + OpAMD64VPERMI2PD256load + OpAMD64VPERMI2PD512load + OpAMD64VPERMI2PDMasked128load + OpAMD64VPERMI2PDMasked256load + OpAMD64VPERMI2PDMasked512load + OpAMD64VPERMI2PS128load + OpAMD64VPERMI2PS256load + OpAMD64VPERMI2PS512load + OpAMD64VPERMI2PSMasked128load + OpAMD64VPERMI2PSMasked256load + OpAMD64VPERMI2PSMasked512load + OpAMD64VPERMI2Q128load + OpAMD64VPERMI2Q256load + OpAMD64VPERMI2Q512load + OpAMD64VPERMI2QMasked128load + OpAMD64VPERMI2QMasked256load + OpAMD64VPERMI2QMasked512load + OpAMD64VPERMI2W128load + OpAMD64VPERMI2W256load + OpAMD64VPERMI2WMasked128load + OpAMD64VPERMI2WMasked256load + OpAMD64VPERMPD256load + OpAMD64VPERMPD512load + OpAMD64VPERMPDMasked256load + OpAMD64VPERMPDMasked512load + OpAMD64VPERMPS256load + OpAMD64VPERMPS512load + OpAMD64VPERMPSMasked256load + OpAMD64VPERMPSMasked512load + OpAMD64VPERMQ256load + OpAMD64VPERMQ512load + OpAMD64VPERMQMasked256load + OpAMD64VPERMQMasked512load + OpAMD64VPERMW128load + OpAMD64VPERMW256load + OpAMD64VPERMWMasked128load + OpAMD64VPERMWMasked256load + OpAMD64VPEXPANDBMasked128load + OpAMD64VPEXPANDBMasked256load + OpAMD64VPEXPANDDMasked128load + OpAMD64VPEXPANDDMasked256load + OpAMD64VPEXPANDQMasked128load + OpAMD64VPEXPANDQMasked256load + OpAMD64VPEXPANDWMasked128load + OpAMD64VPEXPANDWMasked256load + OpAMD64VPHADDD128load + OpAMD64VPHADDD256load + OpAMD64VPHADDSW128load + OpAMD64VPHADDSW256load + OpAMD64VPHADDW128load + OpAMD64VPHADDW256load + OpAMD64VPHSUBD128load + OpAMD64VPHSUBD256load + OpAMD64VPHSUBSW128load + OpAMD64VPHSUBSW256load + OpAMD64VPHSUBW128load + OpAMD64VPHSUBW256load + OpAMD64VPLZCNTD128load + OpAMD64VPLZCNTD256load + OpAMD64VPLZCNTD512load + OpAMD64VPLZCNTDMasked128load + OpAMD64VPLZCNTDMasked256load + OpAMD64VPLZCNTDMasked512load + OpAMD64VPLZCNTQ128load + OpAMD64VPLZCNTQ256load + OpAMD64VPLZCNTQ512load + OpAMD64VPLZCNTQMasked128load + OpAMD64VPLZCNTQMasked256load + OpAMD64VPLZCNTQMasked512load + OpAMD64VPMADDUBSW128load + OpAMD64VPMADDUBSW256load + OpAMD64VPMADDUBSWMasked128load + OpAMD64VPMADDUBSWMasked256load + OpAMD64VPMADDWD128load + OpAMD64VPMADDWD256load + OpAMD64VPMADDWDMasked128load + OpAMD64VPMADDWDMasked256load + OpAMD64VPMAXSB128load + OpAMD64VPMAXSB256load + OpAMD64VPMAXSBMasked128load + OpAMD64VPMAXSBMasked256load + OpAMD64VPMAXSD128load + OpAMD64VPMAXSD256load + OpAMD64VPMAXSD512load + OpAMD64VPMAXSDMasked128load + OpAMD64VPMAXSDMasked256load + OpAMD64VPMAXSDMasked512load + OpAMD64VPMAXSQ128load + OpAMD64VPMAXSQ256load + OpAMD64VPMAXSQ512load + OpAMD64VPMAXSQMasked128load + OpAMD64VPMAXSQMasked256load + OpAMD64VPMAXSQMasked512load + OpAMD64VPMAXSW128load + OpAMD64VPMAXSW256load + OpAMD64VPMAXSWMasked128load + OpAMD64VPMAXSWMasked256load + OpAMD64VPMAXUB128load + OpAMD64VPMAXUB256load + OpAMD64VPMAXUBMasked128load + OpAMD64VPMAXUBMasked256load + OpAMD64VPMAXUD128load + OpAMD64VPMAXUD256load + OpAMD64VPMAXUD512load + OpAMD64VPMAXUDMasked128load + OpAMD64VPMAXUDMasked256load + OpAMD64VPMAXUDMasked512load + OpAMD64VPMAXUQ128load + OpAMD64VPMAXUQ256load + OpAMD64VPMAXUQ512load + OpAMD64VPMAXUQMasked128load + OpAMD64VPMAXUQMasked256load + OpAMD64VPMAXUQMasked512load + OpAMD64VPMAXUW128load + OpAMD64VPMAXUW256load + OpAMD64VPMAXUWMasked128load + OpAMD64VPMAXUWMasked256load + OpAMD64VPMINSB128load + OpAMD64VPMINSB256load + OpAMD64VPMINSBMasked128load + OpAMD64VPMINSBMasked256load + OpAMD64VPMINSD128load + OpAMD64VPMINSD256load + OpAMD64VPMINSD512load + OpAMD64VPMINSDMasked128load + OpAMD64VPMINSDMasked256load + OpAMD64VPMINSDMasked512load + OpAMD64VPMINSQ128load + OpAMD64VPMINSQ256load + OpAMD64VPMINSQ512load + OpAMD64VPMINSQMasked128load + OpAMD64VPMINSQMasked256load + OpAMD64VPMINSQMasked512load + OpAMD64VPMINSW128load + OpAMD64VPMINSW256load + OpAMD64VPMINSWMasked128load + OpAMD64VPMINSWMasked256load + OpAMD64VPMINUB128load + OpAMD64VPMINUB256load + OpAMD64VPMINUBMasked128load + OpAMD64VPMINUBMasked256load + OpAMD64VPMINUD128load + OpAMD64VPMINUD256load + OpAMD64VPMINUD512load + OpAMD64VPMINUDMasked128load + OpAMD64VPMINUDMasked256load + OpAMD64VPMINUDMasked512load + OpAMD64VPMINUQ128load + OpAMD64VPMINUQ256load + OpAMD64VPMINUQ512load + OpAMD64VPMINUQMasked128load + OpAMD64VPMINUQMasked256load + OpAMD64VPMINUQMasked512load + OpAMD64VPMINUW128load + OpAMD64VPMINUW256load + OpAMD64VPMINUWMasked128load + OpAMD64VPMINUWMasked256load + OpAMD64VPMOVSXBD128load + OpAMD64VPMOVSXBD256load + OpAMD64VPMOVSXBD512load + OpAMD64VPMOVSXBDMasked128load + OpAMD64VPMOVSXBDMasked256load + OpAMD64VPMOVSXBDMasked512load + OpAMD64VPMOVSXBQ128load + OpAMD64VPMOVSXBQ256load + OpAMD64VPMOVSXBQ512load + OpAMD64VPMOVSXBQMasked256load + OpAMD64VPMOVSXBQMasked512load + OpAMD64VPMOVSXBW128load + OpAMD64VPMOVSXBW256load + OpAMD64VPMOVSXBW512load + OpAMD64VPMOVSXBWMasked128load + OpAMD64VPMOVSXBWMasked256load + OpAMD64VPMOVSXBWMasked512load + OpAMD64VPMOVSXDQ128load + OpAMD64VPMOVSXDQ256load + OpAMD64VPMOVSXDQ512load + OpAMD64VPMOVSXDQMasked128load + OpAMD64VPMOVSXDQMasked256load + OpAMD64VPMOVSXDQMasked512load + OpAMD64VPMOVSXWD128load + OpAMD64VPMOVSXWD256load + OpAMD64VPMOVSXWD512load + OpAMD64VPMOVSXWDMasked128load + OpAMD64VPMOVSXWDMasked256load + OpAMD64VPMOVSXWDMasked512load + OpAMD64VPMOVSXWQ128load + OpAMD64VPMOVSXWQ256load + OpAMD64VPMOVSXWQ512load + OpAMD64VPMOVSXWQMasked128load + OpAMD64VPMOVSXWQMasked256load + OpAMD64VPMOVSXWQMasked512load + OpAMD64VPMOVZXBD128load + OpAMD64VPMOVZXBD256load + OpAMD64VPMOVZXBD512load + OpAMD64VPMOVZXBDMasked128load + OpAMD64VPMOVZXBDMasked256load + OpAMD64VPMOVZXBDMasked512load + OpAMD64VPMOVZXBQ128load + OpAMD64VPMOVZXBQ256load + OpAMD64VPMOVZXBQ512load + OpAMD64VPMOVZXBQMasked256load + OpAMD64VPMOVZXBQMasked512load + OpAMD64VPMOVZXBW128load + OpAMD64VPMOVZXBW256load + OpAMD64VPMOVZXBW512load + OpAMD64VPMOVZXBWMasked128load + OpAMD64VPMOVZXBWMasked256load + OpAMD64VPMOVZXBWMasked512load + OpAMD64VPMOVZXDQ128load + OpAMD64VPMOVZXDQ256load + OpAMD64VPMOVZXDQ512load + OpAMD64VPMOVZXDQMasked128load + OpAMD64VPMOVZXDQMasked256load + OpAMD64VPMOVZXDQMasked512load + OpAMD64VPMOVZXWD128load + OpAMD64VPMOVZXWD256load + OpAMD64VPMOVZXWD512load + OpAMD64VPMOVZXWDMasked128load + OpAMD64VPMOVZXWDMasked256load + OpAMD64VPMOVZXWDMasked512load + OpAMD64VPMOVZXWQ128load + OpAMD64VPMOVZXWQ256load + OpAMD64VPMOVZXWQ512load + OpAMD64VPMOVZXWQMasked128load + OpAMD64VPMOVZXWQMasked256load + OpAMD64VPMOVZXWQMasked512load + OpAMD64VPMULDQ128load + OpAMD64VPMULDQ256load + OpAMD64VPMULHUW128load + OpAMD64VPMULHUW256load + OpAMD64VPMULHUWMasked128load + OpAMD64VPMULHUWMasked256load + OpAMD64VPMULHW128load + OpAMD64VPMULHW256load + OpAMD64VPMULHWMasked128load + OpAMD64VPMULHWMasked256load + OpAMD64VPMULLD128load + OpAMD64VPMULLD256load + OpAMD64VPMULLD512load + OpAMD64VPMULLDMasked128load + OpAMD64VPMULLDMasked256load + OpAMD64VPMULLDMasked512load + OpAMD64VPMULLQ128load + OpAMD64VPMULLQ256load + OpAMD64VPMULLQ512load + OpAMD64VPMULLQMasked128load + OpAMD64VPMULLQMasked256load + OpAMD64VPMULLQMasked512load + OpAMD64VPMULLW128load + OpAMD64VPMULLW256load + OpAMD64VPMULLWMasked128load + OpAMD64VPMULLWMasked256load + OpAMD64VPMULUDQ128load + OpAMD64VPMULUDQ256load + OpAMD64VPOPCNTB128load + OpAMD64VPOPCNTB256load + OpAMD64VPOPCNTBMasked128load + OpAMD64VPOPCNTBMasked256load + OpAMD64VPOPCNTD128load + OpAMD64VPOPCNTD256load + OpAMD64VPOPCNTD512load + OpAMD64VPOPCNTDMasked128load + OpAMD64VPOPCNTDMasked256load + OpAMD64VPOPCNTDMasked512load + OpAMD64VPOPCNTQ128load + OpAMD64VPOPCNTQ256load + OpAMD64VPOPCNTQ512load + OpAMD64VPOPCNTQMasked128load + OpAMD64VPOPCNTQMasked256load + OpAMD64VPOPCNTQMasked512load + OpAMD64VPOPCNTW128load + OpAMD64VPOPCNTW256load + OpAMD64VPOPCNTWMasked128load + OpAMD64VPOPCNTWMasked256load + OpAMD64VPOR128load + OpAMD64VPOR256load + OpAMD64VPORD512load + OpAMD64VPORDMasked128load + OpAMD64VPORDMasked256load + OpAMD64VPORDMasked512load + OpAMD64VPORQ512load + OpAMD64VPORQMasked128load + OpAMD64VPORQMasked256load + OpAMD64VPORQMasked512load + OpAMD64VPROLVD128load + OpAMD64VPROLVD256load + OpAMD64VPROLVD512load + OpAMD64VPROLVDMasked128load + OpAMD64VPROLVDMasked256load + OpAMD64VPROLVDMasked512load + OpAMD64VPROLVQ128load + OpAMD64VPROLVQ256load + OpAMD64VPROLVQ512load + OpAMD64VPROLVQMasked128load + OpAMD64VPROLVQMasked256load + OpAMD64VPROLVQMasked512load + OpAMD64VPRORVD128load + OpAMD64VPRORVD256load + OpAMD64VPRORVD512load + OpAMD64VPRORVDMasked128load + OpAMD64VPRORVDMasked256load + OpAMD64VPRORVDMasked512load + OpAMD64VPRORVQ128load + OpAMD64VPRORVQ256load + OpAMD64VPRORVQ512load + OpAMD64VPRORVQMasked128load + OpAMD64VPRORVQMasked256load + OpAMD64VPRORVQMasked512load + OpAMD64VPSADBW128load + OpAMD64VPSADBW256load + OpAMD64VPSHLDVD128load + OpAMD64VPSHLDVD256load + OpAMD64VPSHLDVD512load + OpAMD64VPSHLDVDMasked128load + OpAMD64VPSHLDVDMasked256load + OpAMD64VPSHLDVDMasked512load + OpAMD64VPSHLDVQ128load + OpAMD64VPSHLDVQ256load + OpAMD64VPSHLDVQ512load + OpAMD64VPSHLDVQMasked128load + OpAMD64VPSHLDVQMasked256load + OpAMD64VPSHLDVQMasked512load + OpAMD64VPSHLDVW128load + OpAMD64VPSHLDVW256load + OpAMD64VPSHLDVWMasked128load + OpAMD64VPSHLDVWMasked256load + OpAMD64VPSHRDVD128load + OpAMD64VPSHRDVD256load + OpAMD64VPSHRDVD512load + OpAMD64VPSHRDVDMasked128load + OpAMD64VPSHRDVDMasked256load + OpAMD64VPSHRDVDMasked512load + OpAMD64VPSHRDVQ128load + OpAMD64VPSHRDVQ256load + OpAMD64VPSHRDVQ512load + OpAMD64VPSHRDVQMasked128load + OpAMD64VPSHRDVQMasked256load + OpAMD64VPSHRDVQMasked512load + OpAMD64VPSHRDVW128load + OpAMD64VPSHRDVW256load + OpAMD64VPSHRDVWMasked128load + OpAMD64VPSHRDVWMasked256load + OpAMD64VPSHUFB128load + OpAMD64VPSHUFB256load + OpAMD64VPSHUFBMasked128load + OpAMD64VPSHUFBMasked256load + OpAMD64VPSIGNB128load + OpAMD64VPSIGNB256load + OpAMD64VPSIGND128load + OpAMD64VPSIGND256load + OpAMD64VPSIGNW128load + OpAMD64VPSIGNW256load + OpAMD64VPSLLVD128load + OpAMD64VPSLLVD256load + OpAMD64VPSLLVD512load + OpAMD64VPSLLVDMasked128load + OpAMD64VPSLLVDMasked256load + OpAMD64VPSLLVDMasked512load + OpAMD64VPSLLVQ128load + OpAMD64VPSLLVQ256load + OpAMD64VPSLLVQ512load + OpAMD64VPSLLVQMasked128load + OpAMD64VPSLLVQMasked256load + OpAMD64VPSLLVQMasked512load + OpAMD64VPSLLVW128load + OpAMD64VPSLLVW256load + OpAMD64VPSLLVWMasked128load + OpAMD64VPSLLVWMasked256load + OpAMD64VPSRAVD128load + OpAMD64VPSRAVD256load + OpAMD64VPSRAVD512load + OpAMD64VPSRAVDMasked128load + OpAMD64VPSRAVDMasked256load + OpAMD64VPSRAVDMasked512load + OpAMD64VPSRAVQ128load + OpAMD64VPSRAVQ256load + OpAMD64VPSRAVQ512load + OpAMD64VPSRAVQMasked128load + OpAMD64VPSRAVQMasked256load + OpAMD64VPSRAVQMasked512load + OpAMD64VPSRAVW128load + OpAMD64VPSRAVW256load + OpAMD64VPSRAVWMasked128load + OpAMD64VPSRAVWMasked256load + OpAMD64VPSRLVD128load + OpAMD64VPSRLVD256load + OpAMD64VPSRLVD512load + OpAMD64VPSRLVDMasked128load + OpAMD64VPSRLVDMasked256load + OpAMD64VPSRLVDMasked512load + OpAMD64VPSRLVQ128load + OpAMD64VPSRLVQ256load + OpAMD64VPSRLVQ512load + OpAMD64VPSRLVQMasked128load + OpAMD64VPSRLVQMasked256load + OpAMD64VPSRLVQMasked512load + OpAMD64VPSRLVW128load + OpAMD64VPSRLVW256load + OpAMD64VPSRLVWMasked128load + OpAMD64VPSRLVWMasked256load + OpAMD64VPSUBB128load + OpAMD64VPSUBB256load + OpAMD64VPSUBBMasked128load + OpAMD64VPSUBBMasked256load + OpAMD64VPSUBD128load + OpAMD64VPSUBD256load + OpAMD64VPSUBD512load + OpAMD64VPSUBDMasked128load + OpAMD64VPSUBDMasked256load + OpAMD64VPSUBDMasked512load + OpAMD64VPSUBQ128load + OpAMD64VPSUBQ256load + OpAMD64VPSUBQ512load + OpAMD64VPSUBQMasked128load + OpAMD64VPSUBQMasked256load + OpAMD64VPSUBQMasked512load + OpAMD64VPSUBSB128load + OpAMD64VPSUBSB256load + OpAMD64VPSUBSBMasked128load + OpAMD64VPSUBSBMasked256load + OpAMD64VPSUBSW128load + OpAMD64VPSUBSW256load + OpAMD64VPSUBSWMasked128load + OpAMD64VPSUBSWMasked256load + OpAMD64VPSUBUSB128load + OpAMD64VPSUBUSB256load + OpAMD64VPSUBUSBMasked128load + OpAMD64VPSUBUSBMasked256load + OpAMD64VPSUBUSW128load + OpAMD64VPSUBUSW256load + OpAMD64VPSUBUSWMasked128load + OpAMD64VPSUBUSWMasked256load + OpAMD64VPSUBW128load + OpAMD64VPSUBW256load + OpAMD64VPSUBWMasked128load + OpAMD64VPSUBWMasked256load + OpAMD64VPUNPCKHDQ128load + OpAMD64VPUNPCKHDQ256load + OpAMD64VPUNPCKHDQ512load + OpAMD64VPUNPCKHQDQ128load + OpAMD64VPUNPCKHQDQ256load + OpAMD64VPUNPCKHQDQ512load + OpAMD64VPUNPCKHWD128load + OpAMD64VPUNPCKHWD256load + OpAMD64VPUNPCKLDQ128load + OpAMD64VPUNPCKLDQ256load + OpAMD64VPUNPCKLDQ512load + OpAMD64VPUNPCKLQDQ128load + OpAMD64VPUNPCKLQDQ256load + OpAMD64VPUNPCKLQDQ512load + OpAMD64VPUNPCKLWD128load + OpAMD64VPUNPCKLWD256load + OpAMD64VPXOR128load + OpAMD64VPXOR256load + OpAMD64VPXORD512load + OpAMD64VPXORDMasked128load + OpAMD64VPXORDMasked256load + OpAMD64VPXORDMasked512load + OpAMD64VPXORQ512load + OpAMD64VPXORQMasked128load + OpAMD64VPXORQMasked256load + OpAMD64VPXORQMasked512load + OpAMD64VRCP14PD128load + OpAMD64VRCP14PD256load + OpAMD64VRCP14PD512load + OpAMD64VRCP14PDMasked128load + OpAMD64VRCP14PDMasked256load + OpAMD64VRCP14PDMasked512load + OpAMD64VRCP14PS512load + OpAMD64VRCP14PSMasked128load + OpAMD64VRCP14PSMasked256load + OpAMD64VRCP14PSMasked512load + OpAMD64VRCPPS128load + OpAMD64VRCPPS256load + OpAMD64VRSQRT14PD128load + OpAMD64VRSQRT14PD256load + OpAMD64VRSQRT14PD512load + OpAMD64VRSQRT14PDMasked128load + OpAMD64VRSQRT14PDMasked256load + OpAMD64VRSQRT14PDMasked512load + OpAMD64VRSQRT14PS512load + OpAMD64VRSQRT14PSMasked128load + OpAMD64VRSQRT14PSMasked256load + OpAMD64VRSQRT14PSMasked512load + OpAMD64VRSQRTPS128load + OpAMD64VRSQRTPS256load + OpAMD64VSCALEFPD128load + OpAMD64VSCALEFPD256load + OpAMD64VSCALEFPD512load + OpAMD64VSCALEFPDMasked128load + OpAMD64VSCALEFPDMasked256load + OpAMD64VSCALEFPDMasked512load + OpAMD64VSCALEFPS128load + OpAMD64VSCALEFPS256load + OpAMD64VSCALEFPS512load + OpAMD64VSCALEFPSMasked128load + OpAMD64VSCALEFPSMasked256load + OpAMD64VSCALEFPSMasked512load + OpAMD64VSQRTPD128load + OpAMD64VSQRTPD256load + OpAMD64VSQRTPD512load + OpAMD64VSQRTPDMasked128load + OpAMD64VSQRTPDMasked256load + OpAMD64VSQRTPDMasked512load + OpAMD64VSQRTPS128load + OpAMD64VSQRTPS256load + OpAMD64VSQRTPS512load + OpAMD64VSQRTPSMasked128load + OpAMD64VSQRTPSMasked256load + OpAMD64VSQRTPSMasked512load + OpAMD64VSUBPD128load + OpAMD64VSUBPD256load + OpAMD64VSUBPD512load + OpAMD64VSUBPDMasked128load + OpAMD64VSUBPDMasked256load + OpAMD64VSUBPDMasked512load + OpAMD64VSUBPS128load + OpAMD64VSUBPS256load + OpAMD64VSUBPS512load + OpAMD64VSUBPSMasked128load + OpAMD64VSUBPSMasked256load + OpAMD64VSUBPSMasked512load + OpAMD64VAESKEYGENASSIST128load + OpAMD64VCMPPD128load + OpAMD64VCMPPD256load + OpAMD64VCMPPD512load + OpAMD64VCMPPDMasked128load + OpAMD64VCMPPDMasked256load + OpAMD64VCMPPDMasked512load + OpAMD64VCMPPS128load + OpAMD64VCMPPS256load + OpAMD64VCMPPS512load + OpAMD64VCMPPSMasked128load + OpAMD64VCMPPSMasked256load + OpAMD64VCMPPSMasked512load + OpAMD64VGF2P8AFFINEINVQB128load + OpAMD64VGF2P8AFFINEINVQB256load + OpAMD64VGF2P8AFFINEINVQB512load + OpAMD64VGF2P8AFFINEINVQBMasked128load + OpAMD64VGF2P8AFFINEINVQBMasked256load + OpAMD64VGF2P8AFFINEINVQBMasked512load + OpAMD64VGF2P8AFFINEQB128load + OpAMD64VGF2P8AFFINEQB256load + OpAMD64VGF2P8AFFINEQB512load + OpAMD64VGF2P8AFFINEQBMasked128load + OpAMD64VGF2P8AFFINEQBMasked256load + OpAMD64VGF2P8AFFINEQBMasked512load + OpAMD64VINSERTF64X4512load + OpAMD64VINSERTF128256load + OpAMD64VINSERTI64X4512load + OpAMD64VINSERTI128256load + OpAMD64VPALIGNR128load + OpAMD64VPALIGNR256load + OpAMD64VPALIGNRMasked128load + OpAMD64VPALIGNRMasked256load + OpAMD64VPCLMULQDQ128load + OpAMD64VPCLMULQDQ256load + OpAMD64VPCMPBMasked128load + OpAMD64VPCMPBMasked256load + OpAMD64VPCMPD512load + OpAMD64VPCMPDMasked128load + OpAMD64VPCMPDMasked256load + OpAMD64VPCMPDMasked512load + OpAMD64VPCMPQ512load + OpAMD64VPCMPQMasked128load + OpAMD64VPCMPQMasked256load + OpAMD64VPCMPQMasked512load + OpAMD64VPCMPUBMasked128load + OpAMD64VPCMPUBMasked256load + OpAMD64VPCMPUD512load + OpAMD64VPCMPUDMasked128load + OpAMD64VPCMPUDMasked256load + OpAMD64VPCMPUDMasked512load + OpAMD64VPCMPUQ512load + OpAMD64VPCMPUQMasked128load + OpAMD64VPCMPUQMasked256load + OpAMD64VPCMPUQMasked512load + OpAMD64VPCMPUWMasked128load + OpAMD64VPCMPUWMasked256load + OpAMD64VPCMPWMasked128load + OpAMD64VPCMPWMasked256load + OpAMD64VPERM2F128256load + OpAMD64VPERM2I128256load + OpAMD64VPROLD128load + OpAMD64VPROLD256load + OpAMD64VPROLD512load + OpAMD64VPROLDMasked128load + OpAMD64VPROLDMasked256load + OpAMD64VPROLDMasked512load + OpAMD64VPROLQ128load + OpAMD64VPROLQ256load + OpAMD64VPROLQ512load + OpAMD64VPROLQMasked128load + OpAMD64VPROLQMasked256load + OpAMD64VPROLQMasked512load + OpAMD64VPRORD128load + OpAMD64VPRORD256load + OpAMD64VPRORD512load + OpAMD64VPRORDMasked128load + OpAMD64VPRORDMasked256load + OpAMD64VPRORDMasked512load + OpAMD64VPRORQ128load + OpAMD64VPRORQ256load + OpAMD64VPRORQ512load + OpAMD64VPRORQMasked128load + OpAMD64VPRORQMasked256load + OpAMD64VPRORQMasked512load + OpAMD64VPSHLDD128load + OpAMD64VPSHLDD256load + OpAMD64VPSHLDD512load + OpAMD64VPSHLDDMasked128load + OpAMD64VPSHLDDMasked256load + OpAMD64VPSHLDDMasked512load + OpAMD64VPSHLDQ128load + OpAMD64VPSHLDQ256load + OpAMD64VPSHLDQ512load + OpAMD64VPSHLDQMasked128load + OpAMD64VPSHLDQMasked256load + OpAMD64VPSHLDQMasked512load + OpAMD64VPSHLDW128load + OpAMD64VPSHLDW256load + OpAMD64VPSHLDWMasked128load + OpAMD64VPSHLDWMasked256load + OpAMD64VPSHRDD128load + OpAMD64VPSHRDD256load + OpAMD64VPSHRDD512load + OpAMD64VPSHRDDMasked128load + OpAMD64VPSHRDDMasked256load + OpAMD64VPSHRDDMasked512load + OpAMD64VPSHRDQ128load + OpAMD64VPSHRDQ256load + OpAMD64VPSHRDQ512load + OpAMD64VPSHRDQMasked128load + OpAMD64VPSHRDQMasked256load + OpAMD64VPSHRDQMasked512load + OpAMD64VPSHRDW128load + OpAMD64VPSHRDW256load + OpAMD64VPSHRDWMasked128load + OpAMD64VPSHRDWMasked256load + OpAMD64VPSHUFD128load + OpAMD64VPSHUFD256load + OpAMD64VPSHUFD512load + OpAMD64VPSHUFDMasked128load + OpAMD64VPSHUFDMasked256load + OpAMD64VPSHUFDMasked512load + OpAMD64VPSHUFHW128load + OpAMD64VPSHUFHW256load + OpAMD64VPSHUFHWMasked128load + OpAMD64VPSHUFHWMasked256load + OpAMD64VPSHUFLW128load + OpAMD64VPSHUFLW256load + OpAMD64VPSHUFLWMasked128load + OpAMD64VPSHUFLWMasked256load + OpAMD64VPSLLD512constload + OpAMD64VPSLLDMasked128constload + OpAMD64VPSLLDMasked256constload + OpAMD64VPSLLDMasked512constload + OpAMD64VPSLLQ512constload + OpAMD64VPSLLQMasked128constload + OpAMD64VPSLLQMasked256constload + OpAMD64VPSLLQMasked512constload + OpAMD64VPSLLWMasked128constload + OpAMD64VPSLLWMasked256constload + OpAMD64VPSRAD512constload + OpAMD64VPSRADMasked128constload + OpAMD64VPSRADMasked256constload + OpAMD64VPSRADMasked512constload + OpAMD64VPSRAQ128constload + OpAMD64VPSRAQ256constload + OpAMD64VPSRAQ512constload + OpAMD64VPSRAQMasked128constload + OpAMD64VPSRAQMasked256constload + OpAMD64VPSRAQMasked512constload + OpAMD64VPSRAWMasked128constload + OpAMD64VPSRAWMasked256constload + OpAMD64VPSRLD512constload + OpAMD64VPSRLDMasked128constload + OpAMD64VPSRLDMasked256constload + OpAMD64VPSRLDMasked512constload + OpAMD64VPSRLQ512constload + OpAMD64VPSRLQMasked128constload + OpAMD64VPSRLQMasked256constload + OpAMD64VPSRLQMasked512constload + OpAMD64VPSRLWMasked128constload + OpAMD64VPSRLWMasked256constload + OpAMD64VPTERNLOGD128load + OpAMD64VPTERNLOGD256load + OpAMD64VPTERNLOGD512load + OpAMD64VPTERNLOGQ128load + OpAMD64VPTERNLOGQ256load + OpAMD64VPTERNLOGQ512load + OpAMD64VREDUCEPD128load + OpAMD64VREDUCEPD256load + OpAMD64VREDUCEPD512load + OpAMD64VREDUCEPDMasked128load + OpAMD64VREDUCEPDMasked256load + OpAMD64VREDUCEPDMasked512load + OpAMD64VREDUCEPS128load + OpAMD64VREDUCEPS256load + OpAMD64VREDUCEPS512load + OpAMD64VREDUCEPSMasked128load + OpAMD64VREDUCEPSMasked256load + OpAMD64VREDUCEPSMasked512load + OpAMD64VRNDSCALEPD128load + OpAMD64VRNDSCALEPD256load + OpAMD64VRNDSCALEPD512load + OpAMD64VRNDSCALEPDMasked128load + OpAMD64VRNDSCALEPDMasked256load + OpAMD64VRNDSCALEPDMasked512load + OpAMD64VRNDSCALEPS128load + OpAMD64VRNDSCALEPS256load + OpAMD64VRNDSCALEPS512load + OpAMD64VRNDSCALEPSMasked128load + OpAMD64VRNDSCALEPSMasked256load + OpAMD64VRNDSCALEPSMasked512load + OpAMD64VROUNDPD128load + OpAMD64VROUNDPD256load + OpAMD64VROUNDPS128load + OpAMD64VROUNDPS256load + OpAMD64VSHUFPD128load + OpAMD64VSHUFPD256load + OpAMD64VSHUFPD512load + OpAMD64VSHUFPS128load + OpAMD64VSHUFPS256load + OpAMD64VSHUFPS512load + OpAMD64VADDPDMasked128Merging + OpAMD64VADDPDMasked256Merging + OpAMD64VADDPDMasked512Merging + OpAMD64VADDPSMasked128Merging + OpAMD64VADDPSMasked256Merging + OpAMD64VADDPSMasked512Merging + OpAMD64VBROADCASTSDMasked256Merging + OpAMD64VBROADCASTSDMasked512Merging + OpAMD64VBROADCASTSSMasked128Merging + OpAMD64VBROADCASTSSMasked256Merging + OpAMD64VBROADCASTSSMasked512Merging + OpAMD64VCVTDQ2PDMasked256Merging + OpAMD64VCVTDQ2PDMasked512Merging + OpAMD64VCVTDQ2PSMasked128Merging + OpAMD64VCVTDQ2PSMasked256Merging + OpAMD64VCVTDQ2PSMasked512Merging + OpAMD64VCVTPD2PSMasked256Merging + OpAMD64VCVTPD2PSXMasked128Merging + OpAMD64VCVTPD2PSYMasked128Merging + OpAMD64VCVTPS2PDMasked256Merging + OpAMD64VCVTPS2PDMasked512Merging + OpAMD64VCVTQQ2PDMasked128Merging + OpAMD64VCVTQQ2PDMasked256Merging + OpAMD64VCVTQQ2PDMasked512Merging + OpAMD64VCVTQQ2PSMasked256Merging + OpAMD64VCVTQQ2PSXMasked128Merging + OpAMD64VCVTQQ2PSYMasked128Merging + OpAMD64VCVTTPD2DQMasked256Merging + OpAMD64VCVTTPD2DQXMasked128Merging + OpAMD64VCVTTPD2DQYMasked128Merging + OpAMD64VCVTTPD2QQMasked128Merging + OpAMD64VCVTTPD2QQMasked256Merging + OpAMD64VCVTTPD2QQMasked512Merging + OpAMD64VCVTTPD2UDQMasked256Merging + OpAMD64VCVTTPD2UDQXMasked128Merging + OpAMD64VCVTTPD2UDQYMasked128Merging + OpAMD64VCVTTPD2UQQMasked128Merging + OpAMD64VCVTTPD2UQQMasked256Merging + OpAMD64VCVTTPD2UQQMasked512Merging + OpAMD64VCVTTPS2DQMasked128Merging + OpAMD64VCVTTPS2DQMasked256Merging + OpAMD64VCVTTPS2DQMasked512Merging + OpAMD64VCVTTPS2QQMasked256Merging + OpAMD64VCVTTPS2QQMasked512Merging + OpAMD64VCVTTPS2UDQMasked128Merging + OpAMD64VCVTTPS2UDQMasked256Merging + OpAMD64VCVTTPS2UDQMasked512Merging + OpAMD64VCVTTPS2UQQMasked256Merging + OpAMD64VCVTTPS2UQQMasked512Merging + OpAMD64VCVTUDQ2PDMasked256Merging + OpAMD64VCVTUDQ2PDMasked512Merging + OpAMD64VCVTUDQ2PSMasked128Merging + OpAMD64VCVTUDQ2PSMasked256Merging + OpAMD64VCVTUDQ2PSMasked512Merging + OpAMD64VCVTUQQ2PDMasked128Merging + OpAMD64VCVTUQQ2PDMasked256Merging + OpAMD64VCVTUQQ2PDMasked512Merging + OpAMD64VCVTUQQ2PSMasked256Merging + OpAMD64VCVTUQQ2PSXMasked128Merging + OpAMD64VCVTUQQ2PSYMasked128Merging + OpAMD64VDIVPDMasked128Merging + OpAMD64VDIVPDMasked256Merging + OpAMD64VDIVPDMasked512Merging + OpAMD64VDIVPSMasked128Merging + OpAMD64VDIVPSMasked256Merging + OpAMD64VDIVPSMasked512Merging + OpAMD64VGF2P8MULBMasked128Merging + OpAMD64VGF2P8MULBMasked256Merging + OpAMD64VGF2P8MULBMasked512Merging + OpAMD64VMAXPDMasked128Merging + OpAMD64VMAXPDMasked256Merging + OpAMD64VMAXPDMasked512Merging + OpAMD64VMAXPSMasked128Merging + OpAMD64VMAXPSMasked256Merging + OpAMD64VMAXPSMasked512Merging + OpAMD64VMINPDMasked128Merging + OpAMD64VMINPDMasked256Merging + OpAMD64VMINPDMasked512Merging + OpAMD64VMINPSMasked128Merging + OpAMD64VMINPSMasked256Merging + OpAMD64VMINPSMasked512Merging + OpAMD64VMULPDMasked128Merging + OpAMD64VMULPDMasked256Merging + OpAMD64VMULPDMasked512Merging + OpAMD64VMULPSMasked128Merging + OpAMD64VMULPSMasked256Merging + OpAMD64VMULPSMasked512Merging + OpAMD64VPABSBMasked128Merging + OpAMD64VPABSBMasked256Merging + OpAMD64VPABSBMasked512Merging + OpAMD64VPABSDMasked128Merging + OpAMD64VPABSDMasked256Merging + OpAMD64VPABSDMasked512Merging + OpAMD64VPABSQMasked128Merging + OpAMD64VPABSQMasked256Merging + OpAMD64VPABSQMasked512Merging + OpAMD64VPABSWMasked128Merging + OpAMD64VPABSWMasked256Merging + OpAMD64VPABSWMasked512Merging + OpAMD64VPACKSSDWMasked128Merging + OpAMD64VPACKSSDWMasked256Merging + OpAMD64VPACKSSDWMasked512Merging + OpAMD64VPACKUSDWMasked128Merging + OpAMD64VPACKUSDWMasked256Merging + OpAMD64VPACKUSDWMasked512Merging + OpAMD64VPADDBMasked128Merging + OpAMD64VPADDBMasked256Merging + OpAMD64VPADDBMasked512Merging + OpAMD64VPADDDMasked128Merging + OpAMD64VPADDDMasked256Merging + OpAMD64VPADDDMasked512Merging + OpAMD64VPADDQMasked128Merging + OpAMD64VPADDQMasked256Merging + OpAMD64VPADDQMasked512Merging + OpAMD64VPADDSBMasked128Merging + OpAMD64VPADDSBMasked256Merging + OpAMD64VPADDSBMasked512Merging + OpAMD64VPADDSWMasked128Merging + OpAMD64VPADDSWMasked256Merging + OpAMD64VPADDSWMasked512Merging + OpAMD64VPADDUSBMasked128Merging + OpAMD64VPADDUSBMasked256Merging + OpAMD64VPADDUSBMasked512Merging + OpAMD64VPADDUSWMasked128Merging + OpAMD64VPADDUSWMasked256Merging + OpAMD64VPADDUSWMasked512Merging + OpAMD64VPADDWMasked128Merging + OpAMD64VPADDWMasked256Merging + OpAMD64VPADDWMasked512Merging + OpAMD64VPANDDMasked128Merging + OpAMD64VPANDDMasked256Merging + OpAMD64VPANDDMasked512Merging + OpAMD64VPANDQMasked128Merging + OpAMD64VPANDQMasked256Merging + OpAMD64VPANDQMasked512Merging + OpAMD64VPAVGBMasked128Merging + OpAMD64VPAVGBMasked256Merging + OpAMD64VPAVGBMasked512Merging + OpAMD64VPAVGWMasked128Merging + OpAMD64VPAVGWMasked256Merging + OpAMD64VPAVGWMasked512Merging + OpAMD64VPBROADCASTBMasked128Merging + OpAMD64VPBROADCASTBMasked256Merging + OpAMD64VPBROADCASTBMasked512Merging + OpAMD64VPBROADCASTDMasked128Merging + OpAMD64VPBROADCASTDMasked256Merging + OpAMD64VPBROADCASTDMasked512Merging + OpAMD64VPBROADCASTQMasked128Merging + OpAMD64VPBROADCASTQMasked256Merging + OpAMD64VPBROADCASTQMasked512Merging + OpAMD64VPBROADCASTWMasked128Merging + OpAMD64VPBROADCASTWMasked256Merging + OpAMD64VPBROADCASTWMasked512Merging + OpAMD64VPLZCNTDMasked128Merging + OpAMD64VPLZCNTDMasked256Merging + OpAMD64VPLZCNTDMasked512Merging + OpAMD64VPLZCNTQMasked128Merging + OpAMD64VPLZCNTQMasked256Merging + OpAMD64VPLZCNTQMasked512Merging + OpAMD64VPMADDUBSWMasked128Merging + OpAMD64VPMADDUBSWMasked256Merging + OpAMD64VPMADDUBSWMasked512Merging + OpAMD64VPMADDWDMasked128Merging + OpAMD64VPMADDWDMasked256Merging + OpAMD64VPMADDWDMasked512Merging + OpAMD64VPMAXSBMasked128Merging + OpAMD64VPMAXSBMasked256Merging + OpAMD64VPMAXSBMasked512Merging + OpAMD64VPMAXSDMasked128Merging + OpAMD64VPMAXSDMasked256Merging + OpAMD64VPMAXSDMasked512Merging + OpAMD64VPMAXSQMasked128Merging + OpAMD64VPMAXSQMasked256Merging + OpAMD64VPMAXSQMasked512Merging + OpAMD64VPMAXSWMasked128Merging + OpAMD64VPMAXSWMasked256Merging + OpAMD64VPMAXSWMasked512Merging + OpAMD64VPMAXUBMasked128Merging + OpAMD64VPMAXUBMasked256Merging + OpAMD64VPMAXUBMasked512Merging + OpAMD64VPMAXUDMasked128Merging + OpAMD64VPMAXUDMasked256Merging + OpAMD64VPMAXUDMasked512Merging + OpAMD64VPMAXUQMasked128Merging + OpAMD64VPMAXUQMasked256Merging + OpAMD64VPMAXUQMasked512Merging + OpAMD64VPMAXUWMasked128Merging + OpAMD64VPMAXUWMasked256Merging + OpAMD64VPMAXUWMasked512Merging + OpAMD64VPMINSBMasked128Merging + OpAMD64VPMINSBMasked256Merging + OpAMD64VPMINSBMasked512Merging + OpAMD64VPMINSDMasked128Merging + OpAMD64VPMINSDMasked256Merging + OpAMD64VPMINSDMasked512Merging + OpAMD64VPMINSQMasked128Merging + OpAMD64VPMINSQMasked256Merging + OpAMD64VPMINSQMasked512Merging + OpAMD64VPMINSWMasked128Merging + OpAMD64VPMINSWMasked256Merging + OpAMD64VPMINSWMasked512Merging + OpAMD64VPMINUBMasked128Merging + OpAMD64VPMINUBMasked256Merging + OpAMD64VPMINUBMasked512Merging + OpAMD64VPMINUDMasked128Merging + OpAMD64VPMINUDMasked256Merging + OpAMD64VPMINUDMasked512Merging + OpAMD64VPMINUQMasked128Merging + OpAMD64VPMINUQMasked256Merging + OpAMD64VPMINUQMasked512Merging + OpAMD64VPMINUWMasked128Merging + OpAMD64VPMINUWMasked256Merging + OpAMD64VPMINUWMasked512Merging + OpAMD64VPMOVDBMasked128_128Merging + OpAMD64VPMOVDBMasked128_256Merging + OpAMD64VPMOVDBMasked128_512Merging + OpAMD64VPMOVDWMasked128_128Merging + OpAMD64VPMOVDWMasked128_256Merging + OpAMD64VPMOVDWMasked256Merging + OpAMD64VPMOVQBMasked128_128Merging + OpAMD64VPMOVQBMasked128_256Merging + OpAMD64VPMOVQBMasked128_512Merging + OpAMD64VPMOVQDMasked128_128Merging + OpAMD64VPMOVQDMasked128_256Merging + OpAMD64VPMOVQDMasked256Merging + OpAMD64VPMOVQWMasked128_128Merging + OpAMD64VPMOVQWMasked128_256Merging + OpAMD64VPMOVQWMasked128_512Merging + OpAMD64VPMOVSDBMasked128_128Merging + OpAMD64VPMOVSDBMasked128_256Merging + OpAMD64VPMOVSDBMasked128_512Merging + OpAMD64VPMOVSDWMasked128_128Merging + OpAMD64VPMOVSDWMasked128_256Merging + OpAMD64VPMOVSDWMasked256Merging + OpAMD64VPMOVSQBMasked128_128Merging + OpAMD64VPMOVSQBMasked128_256Merging + OpAMD64VPMOVSQBMasked128_512Merging + OpAMD64VPMOVSQDMasked128_128Merging + OpAMD64VPMOVSQDMasked128_256Merging + OpAMD64VPMOVSQDMasked256Merging + OpAMD64VPMOVSQWMasked128_128Merging + OpAMD64VPMOVSQWMasked128_256Merging + OpAMD64VPMOVSQWMasked128_512Merging + OpAMD64VPMOVSWBMasked128_128Merging + OpAMD64VPMOVSWBMasked128_256Merging + OpAMD64VPMOVSWBMasked256Merging + OpAMD64VPMOVSXBDMasked128Merging + OpAMD64VPMOVSXBDMasked256Merging + OpAMD64VPMOVSXBDMasked512Merging + OpAMD64VPMOVSXBQMasked128Merging + OpAMD64VPMOVSXBQMasked256Merging + OpAMD64VPMOVSXBQMasked512Merging + OpAMD64VPMOVSXBWMasked128Merging + OpAMD64VPMOVSXBWMasked256Merging + OpAMD64VPMOVSXBWMasked512Merging + OpAMD64VPMOVSXDQMasked128Merging + OpAMD64VPMOVSXDQMasked256Merging + OpAMD64VPMOVSXDQMasked512Merging + OpAMD64VPMOVSXWDMasked128Merging + OpAMD64VPMOVSXWDMasked256Merging + OpAMD64VPMOVSXWDMasked512Merging + OpAMD64VPMOVSXWQMasked128Merging + OpAMD64VPMOVSXWQMasked256Merging + OpAMD64VPMOVSXWQMasked512Merging + OpAMD64VPMOVUSDBMasked128_128Merging + OpAMD64VPMOVUSDBMasked128_256Merging + OpAMD64VPMOVUSDBMasked128_512Merging + OpAMD64VPMOVUSDWMasked128_128Merging + OpAMD64VPMOVUSDWMasked128_256Merging + OpAMD64VPMOVUSDWMasked256Merging + OpAMD64VPMOVUSQBMasked128_128Merging + OpAMD64VPMOVUSQBMasked128_256Merging + OpAMD64VPMOVUSQBMasked128_512Merging + OpAMD64VPMOVUSQDMasked128_128Merging + OpAMD64VPMOVUSQDMasked128_256Merging + OpAMD64VPMOVUSQDMasked256Merging + OpAMD64VPMOVUSQWMasked128_128Merging + OpAMD64VPMOVUSQWMasked128_256Merging + OpAMD64VPMOVUSQWMasked128_512Merging + OpAMD64VPMOVUSWBMasked128_128Merging + OpAMD64VPMOVUSWBMasked128_256Merging + OpAMD64VPMOVUSWBMasked256Merging + OpAMD64VPMOVWBMasked128_128Merging + OpAMD64VPMOVWBMasked128_256Merging + OpAMD64VPMOVWBMasked256Merging + OpAMD64VPMOVZXBDMasked128Merging + OpAMD64VPMOVZXBDMasked256Merging + OpAMD64VPMOVZXBDMasked512Merging + OpAMD64VPMOVZXBQMasked128Merging + OpAMD64VPMOVZXBQMasked256Merging + OpAMD64VPMOVZXBQMasked512Merging + OpAMD64VPMOVZXBWMasked128Merging + OpAMD64VPMOVZXBWMasked256Merging + OpAMD64VPMOVZXBWMasked512Merging + OpAMD64VPMOVZXDQMasked128Merging + OpAMD64VPMOVZXDQMasked256Merging + OpAMD64VPMOVZXDQMasked512Merging + OpAMD64VPMOVZXWDMasked128Merging + OpAMD64VPMOVZXWDMasked256Merging + OpAMD64VPMOVZXWDMasked512Merging + OpAMD64VPMOVZXWQMasked128Merging + OpAMD64VPMOVZXWQMasked256Merging + OpAMD64VPMOVZXWQMasked512Merging + OpAMD64VPMULHUWMasked128Merging + OpAMD64VPMULHUWMasked256Merging + OpAMD64VPMULHUWMasked512Merging + OpAMD64VPMULHWMasked128Merging + OpAMD64VPMULHWMasked256Merging + OpAMD64VPMULHWMasked512Merging + OpAMD64VPMULLDMasked128Merging + OpAMD64VPMULLDMasked256Merging + OpAMD64VPMULLDMasked512Merging + OpAMD64VPMULLQMasked128Merging + OpAMD64VPMULLQMasked256Merging + OpAMD64VPMULLQMasked512Merging + OpAMD64VPMULLWMasked128Merging + OpAMD64VPMULLWMasked256Merging + OpAMD64VPMULLWMasked512Merging + OpAMD64VPOPCNTBMasked128Merging + OpAMD64VPOPCNTBMasked256Merging + OpAMD64VPOPCNTBMasked512Merging + OpAMD64VPOPCNTDMasked128Merging + OpAMD64VPOPCNTDMasked256Merging + OpAMD64VPOPCNTDMasked512Merging + OpAMD64VPOPCNTQMasked128Merging + OpAMD64VPOPCNTQMasked256Merging + OpAMD64VPOPCNTQMasked512Merging + OpAMD64VPOPCNTWMasked128Merging + OpAMD64VPOPCNTWMasked256Merging + OpAMD64VPOPCNTWMasked512Merging + OpAMD64VPORDMasked128Merging + OpAMD64VPORDMasked256Merging + OpAMD64VPORDMasked512Merging + OpAMD64VPORQMasked128Merging + OpAMD64VPORQMasked256Merging + OpAMD64VPORQMasked512Merging + OpAMD64VPROLVDMasked128Merging + OpAMD64VPROLVDMasked256Merging + OpAMD64VPROLVDMasked512Merging + OpAMD64VPROLVQMasked128Merging + OpAMD64VPROLVQMasked256Merging + OpAMD64VPROLVQMasked512Merging + OpAMD64VPRORVDMasked128Merging + OpAMD64VPRORVDMasked256Merging + OpAMD64VPRORVDMasked512Merging + OpAMD64VPRORVQMasked128Merging + OpAMD64VPRORVQMasked256Merging + OpAMD64VPRORVQMasked512Merging + OpAMD64VPSHUFBMasked128Merging + OpAMD64VPSHUFBMasked256Merging + OpAMD64VPSHUFBMasked512Merging + OpAMD64VPSLLVDMasked128Merging + OpAMD64VPSLLVDMasked256Merging + OpAMD64VPSLLVDMasked512Merging + OpAMD64VPSLLVQMasked128Merging + OpAMD64VPSLLVQMasked256Merging + OpAMD64VPSLLVQMasked512Merging + OpAMD64VPSLLVWMasked128Merging + OpAMD64VPSLLVWMasked256Merging + OpAMD64VPSLLVWMasked512Merging + OpAMD64VPSRAVDMasked128Merging + OpAMD64VPSRAVDMasked256Merging + OpAMD64VPSRAVDMasked512Merging + OpAMD64VPSRAVQMasked128Merging + OpAMD64VPSRAVQMasked256Merging + OpAMD64VPSRAVQMasked512Merging + OpAMD64VPSRAVWMasked128Merging + OpAMD64VPSRAVWMasked256Merging + OpAMD64VPSRAVWMasked512Merging + OpAMD64VPSRLVDMasked128Merging + OpAMD64VPSRLVDMasked256Merging + OpAMD64VPSRLVDMasked512Merging + OpAMD64VPSRLVQMasked128Merging + OpAMD64VPSRLVQMasked256Merging + OpAMD64VPSRLVQMasked512Merging + OpAMD64VPSRLVWMasked128Merging + OpAMD64VPSRLVWMasked256Merging + OpAMD64VPSRLVWMasked512Merging + OpAMD64VPSUBBMasked128Merging + OpAMD64VPSUBBMasked256Merging + OpAMD64VPSUBBMasked512Merging + OpAMD64VPSUBDMasked128Merging + OpAMD64VPSUBDMasked256Merging + OpAMD64VPSUBDMasked512Merging + OpAMD64VPSUBQMasked128Merging + OpAMD64VPSUBQMasked256Merging + OpAMD64VPSUBQMasked512Merging + OpAMD64VPSUBSBMasked128Merging + OpAMD64VPSUBSBMasked256Merging + OpAMD64VPSUBSBMasked512Merging + OpAMD64VPSUBSWMasked128Merging + OpAMD64VPSUBSWMasked256Merging + OpAMD64VPSUBSWMasked512Merging + OpAMD64VPSUBUSBMasked128Merging + OpAMD64VPSUBUSBMasked256Merging + OpAMD64VPSUBUSBMasked512Merging + OpAMD64VPSUBUSWMasked128Merging + OpAMD64VPSUBUSWMasked256Merging + OpAMD64VPSUBUSWMasked512Merging + OpAMD64VPSUBWMasked128Merging + OpAMD64VPSUBWMasked256Merging + OpAMD64VPSUBWMasked512Merging + OpAMD64VPXORDMasked128Merging + OpAMD64VPXORDMasked256Merging + OpAMD64VPXORDMasked512Merging + OpAMD64VPXORQMasked128Merging + OpAMD64VPXORQMasked256Merging + OpAMD64VPXORQMasked512Merging + OpAMD64VRCP14PDMasked128Merging + OpAMD64VRCP14PDMasked256Merging + OpAMD64VRCP14PDMasked512Merging + OpAMD64VRCP14PSMasked128Merging + OpAMD64VRCP14PSMasked256Merging + OpAMD64VRCP14PSMasked512Merging + OpAMD64VRSQRT14PDMasked128Merging + OpAMD64VRSQRT14PDMasked256Merging + OpAMD64VRSQRT14PDMasked512Merging + OpAMD64VRSQRT14PSMasked128Merging + OpAMD64VRSQRT14PSMasked256Merging + OpAMD64VRSQRT14PSMasked512Merging + OpAMD64VSCALEFPDMasked128Merging + OpAMD64VSCALEFPDMasked256Merging + OpAMD64VSCALEFPDMasked512Merging + OpAMD64VSCALEFPSMasked128Merging + OpAMD64VSCALEFPSMasked256Merging + OpAMD64VSCALEFPSMasked512Merging + OpAMD64VSQRTPDMasked128Merging + OpAMD64VSQRTPDMasked256Merging + OpAMD64VSQRTPDMasked512Merging + OpAMD64VSQRTPSMasked128Merging + OpAMD64VSQRTPSMasked256Merging + OpAMD64VSQRTPSMasked512Merging + OpAMD64VSUBPDMasked128Merging + OpAMD64VSUBPDMasked256Merging + OpAMD64VSUBPDMasked512Merging + OpAMD64VSUBPSMasked128Merging + OpAMD64VSUBPSMasked256Merging + OpAMD64VSUBPSMasked512Merging + OpAMD64VPROLDMasked128Merging + OpAMD64VPROLDMasked256Merging + OpAMD64VPROLDMasked512Merging + OpAMD64VPROLQMasked128Merging + OpAMD64VPROLQMasked256Merging + OpAMD64VPROLQMasked512Merging + OpAMD64VPRORDMasked128Merging + OpAMD64VPRORDMasked256Merging + OpAMD64VPRORDMasked512Merging + OpAMD64VPRORQMasked128Merging + OpAMD64VPRORQMasked256Merging + OpAMD64VPRORQMasked512Merging + OpAMD64VPSHUFDMasked128Merging + OpAMD64VPSHUFDMasked256Merging + OpAMD64VPSHUFDMasked512Merging + OpAMD64VPSHUFHWMasked128Merging + OpAMD64VPSHUFHWMasked256Merging + OpAMD64VPSHUFHWMasked512Merging + OpAMD64VPSHUFLWMasked128Merging + OpAMD64VPSHUFLWMasked256Merging + OpAMD64VPSHUFLWMasked512Merging + OpAMD64VPSLLDMasked128constMerging + OpAMD64VPSLLDMasked256constMerging + OpAMD64VPSLLDMasked512constMerging + OpAMD64VPSLLQMasked128constMerging + OpAMD64VPSLLQMasked256constMerging + OpAMD64VPSLLQMasked512constMerging + OpAMD64VPSLLWMasked128constMerging + OpAMD64VPSLLWMasked256constMerging + OpAMD64VPSLLWMasked512constMerging + OpAMD64VPSRADMasked128constMerging + OpAMD64VPSRADMasked256constMerging + OpAMD64VPSRADMasked512constMerging + OpAMD64VPSRAQMasked128constMerging + OpAMD64VPSRAQMasked256constMerging + OpAMD64VPSRAQMasked512constMerging + OpAMD64VPSRAWMasked128constMerging + OpAMD64VPSRAWMasked256constMerging + OpAMD64VPSRAWMasked512constMerging + OpAMD64VPSRLDMasked128constMerging + OpAMD64VPSRLDMasked256constMerging + OpAMD64VPSRLDMasked512constMerging + OpAMD64VPSRLQMasked128constMerging + OpAMD64VPSRLQMasked256constMerging + OpAMD64VPSRLQMasked512constMerging + OpAMD64VPSRLWMasked128constMerging + OpAMD64VPSRLWMasked256constMerging + OpAMD64VPSRLWMasked512constMerging + OpAMD64VREDUCEPDMasked128Merging + OpAMD64VREDUCEPDMasked256Merging + OpAMD64VREDUCEPDMasked512Merging + OpAMD64VREDUCEPSMasked128Merging + OpAMD64VREDUCEPSMasked256Merging + OpAMD64VREDUCEPSMasked512Merging + OpAMD64VRNDSCALEPDMasked128Merging + OpAMD64VRNDSCALEPDMasked256Merging + OpAMD64VRNDSCALEPDMasked512Merging + OpAMD64VRNDSCALEPSMasked128Merging + OpAMD64VRNDSCALEPSMasked256Merging + OpAMD64VRNDSCALEPSMasked512Merging OpARMADD OpARMADDconst @@ -1182,6 +4389,7 @@ const ( OpARMADDSconst OpARMADC OpARMADCconst + OpARMADCS OpARMSUBS OpARMSUBSconst OpARMRSBSconst @@ -1406,6 +4614,7 @@ const ( OpARMSRAcond OpARMCALLstatic OpARMCALLtail + OpARMCALLtailinter OpARMCALLclosure OpARMCALLinter OpARMLoweredNilCheck @@ -1486,6 +4695,7 @@ const ( OpARM64NEGSflags OpARM64NGCzerocarry OpARM64FABSD + OpARM64FABSS OpARM64FNEGS OpARM64FNEGD OpARM64FSQRTD @@ -1612,11 +4822,13 @@ const ( OpARM64MOVDload OpARM64FMOVSload OpARM64FMOVDload + OpARM64FMOVQload OpARM64LDP OpARM64LDPW OpARM64LDPSW OpARM64FLDPD OpARM64FLDPS + OpARM64FLDPQ OpARM64MOVDloadidx OpARM64MOVWloadidx OpARM64MOVWUloadidx @@ -1639,10 +4851,12 @@ const ( OpARM64MOVDstore OpARM64FMOVSstore OpARM64FMOVDstore + OpARM64FMOVQstore OpARM64STP OpARM64STPW OpARM64FSTPD OpARM64FSTPS + OpARM64FSTPQ OpARM64MOVBstoreidx OpARM64MOVHstoreidx OpARM64MOVWstoreidx @@ -1689,6 +4903,11 @@ const ( OpARM64FRINTND OpARM64FRINTPD OpARM64FRINTZD + OpARM64FRINTAS + OpARM64FRINTMS + OpARM64FRINTNS + OpARM64FRINTPS + OpARM64FRINTZS OpARM64CSEL OpARM64CSEL0 OpARM64CSINC @@ -1705,9 +4924,11 @@ const ( OpARM64CCMNWconst OpARM64CALLstatic OpARM64CALLtail + OpARM64CALLtailinter OpARM64CALLclosure OpARM64CALLinter OpARM64LoweredNilCheck + OpARM64LoweredMemEq OpARM64Equal OpARM64NotEqual OpARM64LessThan @@ -1777,12 +4998,320 @@ const ( OpARM64PRFM OpARM64DMB OpARM64ZERO + OpARM64VMOVI16B + OpARM64VABS2D + OpARM64VABS4S + OpARM64VABS8H + OpARM64VABS16B + OpARM64VADD2D + OpARM64VADD4S + OpARM64VADD8H + OpARM64VADD16B + OpARM64VADDP2D + OpARM64VADDP4S + OpARM64VADDP8H + OpARM64VADDV4S + OpARM64VADDV8H + OpARM64VADDV16B + OpARM64VAND16B + OpARM64VBIC16B + OpARM64VBIF16B + OpARM64VBIT16B + OpARM64VCLS4S + OpARM64VCLS8H + OpARM64VCLS16B + OpARM64VCLZ4S + OpARM64VCLZ8H + OpARM64VCLZ16B + OpARM64VCMEQ2D + OpARM64VCMEQ4S + OpARM64VCMEQ8H + OpARM64VCMEQ16B + OpARM64VCMGE2D + OpARM64VCMGE4S + OpARM64VCMGE8H + OpARM64VCMGE16B + OpARM64VCMGT2D + OpARM64VCMGT4S + OpARM64VCMGT8H + OpARM64VCMGT16B + OpARM64VCMHI2D + OpARM64VCMHI4S + OpARM64VCMHI8H + OpARM64VCMHI16B + OpARM64VCMHS2D + OpARM64VCMHS4S + OpARM64VCMHS8H + OpARM64VCMHS16B + OpARM64VCNT16B + OpARM64VEOR16B + OpARM64VFABS2D + OpARM64VFABS4S + OpARM64VFADD2D + OpARM64VFADD4S + OpARM64VFADDP2D + OpARM64VFADDP4S + OpARM64VFCMEQ2D + OpARM64VFCMEQ4S + OpARM64VFCMGE2D + OpARM64VFCMGE4S + OpARM64VFCMGT2D + OpARM64VFCMGT4S + OpARM64VFCVTL2_4S + OpARM64VFCVTL4S + OpARM64VFCVTN2D + OpARM64VFCVTN2_2D + OpARM64VFCVTZS2D + OpARM64VFCVTZS4S + OpARM64VFCVTZU2D + OpARM64VFCVTZU4S + OpARM64VFDIV2D + OpARM64VFDIV4S + OpARM64VFMAX2D + OpARM64VFMAX4S + OpARM64VFMAXV4S + OpARM64VFMIN2D + OpARM64VFMIN4S + OpARM64VFMINV4S + OpARM64VFMLA2D + OpARM64VFMLA4S + OpARM64VFMUL2D + OpARM64VFMUL4S + OpARM64VFNEG2D + OpARM64VFNEG4S + OpARM64VFRINTM2D + OpARM64VFRINTM4S + OpARM64VFRINTN2D + OpARM64VFRINTN4S + OpARM64VFRINTP2D + OpARM64VFRINTP4S + OpARM64VFRINTZ2D + OpARM64VFRINTZ4S + OpARM64VFSQRT2D + OpARM64VFSQRT4S + OpARM64VFSUB2D + OpARM64VFSUB4S + OpARM64VMLA4S + OpARM64VMLA8H + OpARM64VMLA16B + OpARM64VMUL4S + OpARM64VMUL8H + OpARM64VMUL16B + OpARM64VNEG2D + OpARM64VNEG4S + OpARM64VNEG8H + OpARM64VNEG16B + OpARM64VNOT16B + OpARM64VORN16B + OpARM64VORR16B + OpARM64VPMULL2D + OpARM64VPMULL2_2D + OpARM64VSCVTF2D + OpARM64VSCVTF4S + OpARM64VSMAX4S + OpARM64VSMAX8H + OpARM64VSMAX16B + OpARM64VSMAXV4S + OpARM64VSMAXV8H + OpARM64VSMAXV16B + OpARM64VSMIN4S + OpARM64VSMIN8H + OpARM64VSMIN16B + OpARM64VSMINV4S + OpARM64VSMINV8H + OpARM64VSMINV16B + OpARM64VSMULL2_4S + OpARM64VSMULL2_8H + OpARM64VSMULL2_16B + OpARM64VSMULL4S + OpARM64VSMULL8H + OpARM64VSMULL16B + OpARM64VSQADD2D + OpARM64VSQADD4S + OpARM64VSQADD8H + OpARM64VSQADD16B + OpARM64VSQSHL2D + OpARM64VSQSHL4S + OpARM64VSQSHL8H + OpARM64VSQSHL16B + OpARM64VSQSUB2D + OpARM64VSQSUB4S + OpARM64VSQSUB8H + OpARM64VSQSUB16B + OpARM64VSQXTN2D + OpARM64VSQXTN2_2D + OpARM64VSQXTN2_4S + OpARM64VSQXTN2_8H + OpARM64VSQXTN4S + OpARM64VSQXTN8H + OpARM64VSQXTUN2D + OpARM64VSQXTUN2_2D + OpARM64VSQXTUN2_4S + OpARM64VSQXTUN2_8H + OpARM64VSQXTUN4S + OpARM64VSQXTUN8H + OpARM64VSRHADD4S + OpARM64VSRHADD8H + OpARM64VSRHADD16B + OpARM64VSSHL2D + OpARM64VSSHL4S + OpARM64VSSHL8H + OpARM64VSSHL16B + OpARM64VSUB2D + OpARM64VSUB4S + OpARM64VSUB8H + OpARM64VSUB16B + OpARM64VSXTL2_4S + OpARM64VSXTL2_8H + OpARM64VSXTL2_16B + OpARM64VSXTL4S + OpARM64VSXTL8H + OpARM64VSXTL16B + OpARM64VTBL16B + OpARM64VTBX16B + OpARM64VTRN12D + OpARM64VTRN14S + OpARM64VTRN18H + OpARM64VTRN22D + OpARM64VTRN24S + OpARM64VTRN28H + OpARM64VTRN116B + OpARM64VTRN216B + OpARM64VUCVTF2D + OpARM64VUCVTF4S + OpARM64VUMAX4S + OpARM64VUMAX8H + OpARM64VUMAX16B + OpARM64VUMAXV4S + OpARM64VUMAXV8H + OpARM64VUMAXV16B + OpARM64VUMIN4S + OpARM64VUMIN8H + OpARM64VUMIN16B + OpARM64VUMINV4S + OpARM64VUMINV8H + OpARM64VUMINV16B + OpARM64VUMULL2_4S + OpARM64VUMULL2_8H + OpARM64VUMULL2_16B + OpARM64VUMULL4S + OpARM64VUMULL8H + OpARM64VUMULL16B + OpARM64VUQADD2D + OpARM64VUQADD4S + OpARM64VUQADD8H + OpARM64VUQADD16B + OpARM64VUQSHL2D + OpARM64VUQSHL4S + OpARM64VUQSHL8H + OpARM64VUQSHL16B + OpARM64VUQSUB2D + OpARM64VUQSUB4S + OpARM64VUQSUB8H + OpARM64VUQSUB16B + OpARM64VUQXTN2D + OpARM64VUQXTN2_2D + OpARM64VUQXTN2_4S + OpARM64VUQXTN2_8H + OpARM64VUQXTN4S + OpARM64VUQXTN8H + OpARM64VURHADD4S + OpARM64VURHADD8H + OpARM64VURHADD16B + OpARM64VUSHL2D + OpARM64VUSHL4S + OpARM64VUSHL8H + OpARM64VUSHL16B + OpARM64VUXTL2_4S + OpARM64VUXTL2_8H + OpARM64VUXTL2_16B + OpARM64VUXTL4S + OpARM64VUXTL8H + OpARM64VUXTL16B + OpARM64VUZP12D + OpARM64VUZP14S + OpARM64VUZP18H + OpARM64VUZP22D + OpARM64VUZP24S + OpARM64VUZP28H + OpARM64VUZP116B + OpARM64VUZP216B + OpARM64VXTN2D + OpARM64VXTN2_2D + OpARM64VXTN2_4S + OpARM64VXTN2_8H + OpARM64VXTN4S + OpARM64VXTN8H + OpARM64VZIP12D + OpARM64VZIP14S + OpARM64VZIP18H + OpARM64VZIP22D + OpARM64VZIP24S + OpARM64VZIP28H + OpARM64VZIP116B + OpARM64VZIP216B + OpARM64VDUPBbcast + OpARM64VDUPDbcast + OpARM64VDUPDextr + OpARM64VDUPHbcast + OpARM64VDUPSbcast + OpARM64VDUPSextr + OpARM64VEXT16B + OpARM64VMOVBextr + OpARM64VMOVBins + OpARM64VMOVDextr + OpARM64VMOVDins + OpARM64VMOVDins0 + OpARM64VMOVHextr + OpARM64VMOVHins + OpARM64VMOVSextr + OpARM64VMOVSins + OpARM64VMOVSins0 + OpARM64VSHL2D + OpARM64VSHL4S + OpARM64VSHL8H + OpARM64VSHL16B + OpARM64VSHRN2D + OpARM64VSHRN2_2D + OpARM64VSHRN2_4S + OpARM64VSHRN2_8H + OpARM64VSHRN4S + OpARM64VSHRN8H + OpARM64VSQSHL2Dconst + OpARM64VSQSHL4Sconst + OpARM64VSQSHL8Hconst + OpARM64VSQSHL16Bconst + OpARM64VSSHLL2_4S + OpARM64VSSHLL2_8H + OpARM64VSSHLL2_16B + OpARM64VSSHLL4S + OpARM64VSSHLL8H + OpARM64VSSHLL16B + OpARM64VSSHR2D + OpARM64VSSHR4S + OpARM64VSSHR8H + OpARM64VSSHR16B + OpARM64VUQSHL2Dconst + OpARM64VUQSHL4Sconst + OpARM64VUQSHL8Hconst + OpARM64VUQSHL16Bconst + OpARM64VUSHLL2_4S + OpARM64VUSHLL2_8H + OpARM64VUSHLL2_16B + OpARM64VUSHLL4S + OpARM64VUSHLL8H + OpARM64VUSHLL16B + OpARM64VUSHR2D + OpARM64VUSHR4S + OpARM64VUSHR8H + OpARM64VUSHR16B OpLOONG64NEGV OpLOONG64NEGF OpLOONG64NEGD OpLOONG64SQRTD OpLOONG64SQRTF + OpLOONG64ABSF OpLOONG64ABSD OpLOONG64CLZW OpLOONG64CLZV @@ -1812,6 +5341,8 @@ const ( OpLOONG64DIVVU OpLOONG64REMV OpLOONG64REMVU + OpLOONG64MULWVW + OpLOONG64MULWVWU OpLOONG64ADDF OpLOONG64ADDD OpLOONG64SUBF @@ -1929,10 +5460,15 @@ const ( OpLOONG64TRUNCDV OpLOONG64MOVFD OpLOONG64MOVDF + OpLOONG64FRINTND + OpLOONG64FRINTMD + OpLOONG64FRINTPD + OpLOONG64FRINTZD OpLOONG64LoweredRound32F OpLOONG64LoweredRound64F OpLOONG64CALLstatic OpLOONG64CALLtail + OpLOONG64CALLtailinter OpLOONG64CALLclosure OpLOONG64CALLinter OpLOONG64LoweredZero @@ -2004,7 +5540,6 @@ const ( OpMIPSXOR OpMIPSXORconst OpMIPSNOR - OpMIPSNORconst OpMIPSNEG OpMIPSNEGF OpMIPSNEGD @@ -2067,6 +5602,7 @@ const ( OpMIPSMOVDF OpMIPSCALLstatic OpMIPSCALLtail + OpMIPSCALLtailinter OpMIPSCALLclosure OpMIPSCALLinter OpMIPSLoweredAtomicLoad8 @@ -2120,10 +5656,10 @@ const ( OpMIPS64XOR OpMIPS64XORconst OpMIPS64NOR - OpMIPS64NORconst OpMIPS64NEGV OpMIPS64NEGF OpMIPS64NEGD + OpMIPS64ABSF OpMIPS64ABSD OpMIPS64SQRTD OpMIPS64SQRTF @@ -2187,6 +5723,7 @@ const ( OpMIPS64MOVDF OpMIPS64CALLstatic OpMIPS64CALLtail + OpMIPS64CALLtailinter OpMIPS64CALLclosure OpMIPS64CALLinter OpMIPS64DUFFZERO @@ -2429,6 +5966,7 @@ const ( OpPPC64LoweredRound64F OpPPC64CALLstatic OpPPC64CALLtail + OpPPC64CALLtailinter OpPPC64CALLclosure OpPPC64CALLinter OpPPC64LoweredZero @@ -2491,6 +6029,8 @@ const ( OpRISCV64REMUW OpRISCV64MOVaddr OpRISCV64MOVDconst + OpRISCV64FMOVDconst + OpRISCV64FMOVFconst OpRISCV64MOVBload OpRISCV64MOVHload OpRISCV64MOVWload @@ -2566,6 +6106,7 @@ const ( OpRISCV64LoweredRound64F OpRISCV64CALLstatic OpRISCV64CALLtail + OpRISCV64CALLtailinter OpRISCV64CALLclosure OpRISCV64CALLinter OpRISCV64LoweredZero @@ -2605,6 +6146,7 @@ const ( OpRISCV64FNMADDS OpRISCV64FNMSUBS OpRISCV64FSQRTS + OpRISCV64FABSS OpRISCV64FNEGS OpRISCV64FMVSX OpRISCV64FMVXS @@ -2650,6 +6192,8 @@ const ( OpRISCV64LoweredFMAXD OpRISCV64FCLASSS OpRISCV64FCLASSD + OpRISCV64CZEROEQZ + OpRISCV64CZERONEZ OpS390XFADDS OpS390XFADD @@ -2843,6 +6387,7 @@ const ( OpS390XCLEAR OpS390XCALLstatic OpS390XCALLtail + OpS390XCALLtailinter OpS390XCALLclosure OpS390XCALLinter OpS390XInvertFlags @@ -2898,6 +6443,7 @@ const ( OpWasmLoweredStaticCall OpWasmLoweredTailCall + OpWasmLoweredTailCallInter OpWasmLoweredClosureCall OpWasmLoweredInterCall OpWasmLoweredAddr @@ -2910,6 +6456,7 @@ const ( OpWasmLoweredWB OpWasmLoweredConvert OpWasmSelect + OpWasmSelectV OpWasmI64Load8U OpWasmI64Load8S OpWasmI64Load16U @@ -2928,6 +6475,9 @@ const ( OpWasmI64Const OpWasmF32Const OpWasmF64Const + OpWasmV128Load + OpWasmV128Store + OpWasmV128Zero OpWasmI64Eqz OpWasmI64Eq OpWasmI64Ne @@ -3007,7 +6557,208 @@ const ( OpWasmI32Rotl OpWasmI64Rotl OpWasmI64Popcnt + OpWasmI8x16AllTrue + OpWasmV128AnyTrue + OpWasmI16x8AllTrue + OpWasmI16x8Q15MulrSatS + OpWasmI16x8RelaxedQ15MulrS + OpWasmI32x4AllTrue + OpWasmF32x4Pmax + OpWasmF32x4Pmin + OpWasmF32x4RelaxedMax + OpWasmF32x4RelaxedMin + OpWasmI64x2AllTrue + OpWasmF64x2Pmax + OpWasmF64x2Pmin + OpWasmF64x2RelaxedMax + OpWasmF64x2RelaxedMin + OpWasmI8x16Abs + OpWasmI16x8Abs + OpWasmI32x4Abs + OpWasmF32x4Abs + OpWasmI64x2Abs + OpWasmF64x2Abs + OpWasmI8x16Add + OpWasmI16x8Add + OpWasmI32x4Add + OpWasmF32x4Add + OpWasmI64x2Add + OpWasmF64x2Add + OpWasmI8x16AddSatS + OpWasmI8x16AddSatU + OpWasmI16x8AddSatS + OpWasmI16x8AddSatU + OpWasmV128And + OpWasmV128Andnot + OpWasmI8x16AvgrU + OpWasmI16x8AvgrU + OpWasmV128Bitselect + OpWasmI8x16Splat + OpWasmI16x8Splat + OpWasmI32x4Splat + OpWasmF32x4Splat + OpWasmI64x2Splat + OpWasmF64x2Splat + OpWasmF32x4Ceil + OpWasmF64x2Ceil + OpWasmF64x2ConvertLowI32x4S + OpWasmF64x2ConvertLowI32x4U + OpWasmF32x4ConvertI32x4S + OpWasmF32x4ConvertI32x4U + OpWasmI32x4TruncSatF32x4S + OpWasmI32x4TruncSatF32x4U + OpWasmF32x4Div + OpWasmF64x2Div + OpWasmI8x16Eq + OpWasmI16x8Eq + OpWasmI32x4Eq + OpWasmF32x4Eq + OpWasmI64x2Eq + OpWasmF64x2Eq + OpWasmI64x2ExtendHighI32x4S + OpWasmI64x2ExtendHighI32x4U + OpWasmI32x4ExtendHighI16x8S + OpWasmI32x4ExtendHighI16x8U + OpWasmI16x8ExtendHighI8x16S + OpWasmI16x8ExtendHighI8x16U + OpWasmI64x2ExtendLowI32x4S + OpWasmI64x2ExtendLowI32x4U + OpWasmI32x4ExtendLowI16x8S + OpWasmI32x4ExtendLowI16x8U + OpWasmI16x8ExtendLowI8x16S + OpWasmI16x8ExtendLowI8x16U + OpWasmF32x4Floor + OpWasmF64x2Floor + OpWasmI8x16ExtractLaneS + OpWasmI8x16ExtractLaneU + OpWasmI16x8ExtractLaneS + OpWasmI16x8ExtractLaneU + OpWasmI32x4ExtractLane + OpWasmF32x4ExtractLane + OpWasmI64x2ExtractLane + OpWasmF64x2ExtractLane + OpWasmI8x16GtS + OpWasmI8x16GtU + OpWasmI16x8GtS + OpWasmI16x8GtU + OpWasmI32x4GtS + OpWasmI32x4GtU + OpWasmF32x4Gt + OpWasmI64x2GtS + OpWasmF64x2Gt + OpWasmI8x16GeS + OpWasmI8x16GeU + OpWasmI16x8GeS + OpWasmI16x8GeU + OpWasmI32x4GeS + OpWasmI32x4GeU + OpWasmF32x4Ge + OpWasmI64x2GeS + OpWasmF64x2Ge + OpWasmI8x16LtS + OpWasmI8x16LtU + OpWasmI16x8LtS + OpWasmI16x8LtU + OpWasmI32x4LtS + OpWasmI32x4LtU + OpWasmF32x4Lt + OpWasmI64x2LtS + OpWasmF64x2Lt + OpWasmI8x16LeS + OpWasmI8x16LeU + OpWasmI16x8LeS + OpWasmI16x8LeU + OpWasmI32x4LeS + OpWasmI32x4LeU + OpWasmF32x4Le + OpWasmI64x2LeS + OpWasmF64x2Le + OpWasmI8x16Swizzle + OpWasmI8x16MaxS + OpWasmI8x16MaxU + OpWasmI16x8MaxS + OpWasmI16x8MaxU + OpWasmI32x4MaxS + OpWasmI32x4MaxU + OpWasmF32x4Max + OpWasmF64x2Max + OpWasmI8x16MinS + OpWasmI8x16MinU + OpWasmI16x8MinS + OpWasmI16x8MinU + OpWasmI32x4MinS + OpWasmI32x4MinU + OpWasmF32x4Min + OpWasmF64x2Min + OpWasmI16x8Mul + OpWasmI32x4Mul + OpWasmF32x4Mul + OpWasmI64x2Mul + OpWasmF64x2Mul + OpWasmI16x8ExtmulHighI8x16S + OpWasmI16x8ExtmulHighI8x16U + OpWasmI32x4ExtmulHighI16x8S + OpWasmI32x4ExtmulHighI16x8U + OpWasmI64x2ExtmulHighI32x4S + OpWasmI64x2ExtmulHighI32x4U + OpWasmI16x8ExtmulLowI8x16S + OpWasmI16x8ExtmulLowI8x16U + OpWasmI32x4ExtmulLowI16x8S + OpWasmI32x4ExtmulLowI16x8U + OpWasmI64x2ExtmulLowI32x4S + OpWasmI64x2ExtmulLowI32x4U + OpWasmI8x16Neg + OpWasmI16x8Neg + OpWasmI32x4Neg + OpWasmF32x4Neg + OpWasmI64x2Neg + OpWasmF64x2Neg + OpWasmV128Not + OpWasmI8x16Ne + OpWasmI16x8Ne + OpWasmI32x4Ne + OpWasmF32x4Ne + OpWasmI64x2Ne + OpWasmF64x2Ne + OpWasmI8x16Popcnt + OpWasmV128Or + OpWasmF32x4Nearest + OpWasmF64x2Nearest + OpWasmI8x16ReplaceLane + OpWasmI16x8ReplaceLane + OpWasmI32x4ReplaceLane + OpWasmF32x4ReplaceLane + OpWasmI64x2ReplaceLane + OpWasmF64x2ReplaceLane + OpWasmI8x16Shl + OpWasmI16x8Shl + OpWasmI32x4Shl + OpWasmI64x2Shl + OpWasmI8x16ShrS + OpWasmI8x16ShrU + OpWasmI16x8ShrS + OpWasmI16x8ShrU + OpWasmI32x4ShrS + OpWasmI32x4ShrU + OpWasmI64x2ShrS + OpWasmI64x2ShrU + OpWasmF32x4Sqrt + OpWasmF64x2Sqrt + OpWasmI8x16Sub + OpWasmI16x8Sub + OpWasmI32x4Sub + OpWasmF32x4Sub + OpWasmI64x2Sub + OpWasmF64x2Sub + OpWasmI8x16SubSatS + OpWasmI8x16SubSatU + OpWasmI16x8SubSatS + OpWasmI16x8SubSatU + OpWasmF32x4Trunc + OpWasmF64x2Trunc + OpWasmV128Xor + OpLast OpAdd8 OpAdd16 OpAdd32 @@ -3243,6 +6994,14 @@ const ( OpLoad OpDereference OpStore + OpLoadMasked8 + OpLoadMasked16 + OpLoadMasked32 + OpLoadMasked64 + OpStoreMasked8 + OpStoreMasked16 + OpStoreMasked32 + OpStoreMasked64 OpMove OpZero OpStoreWB @@ -3257,10 +7016,12 @@ const ( OpStaticCall OpInterCall OpTailCall + OpTailCallInter OpClosureLECall OpStaticLECall OpInterLECall OpTailLECall + OpTailLECallInter OpSignExt8to16 OpSignExt8to32 OpSignExt8to64 @@ -3318,7 +7079,6 @@ const ( OpIData OpStructMake OpStructSelect - OpArrayMake0 OpArrayMake1 OpArraySelect OpStoreReg @@ -3334,6 +7094,7 @@ const ( OpInt64Lo OpAdd32carry OpAdd32withcarry + OpAdd32carrywithcarry OpSub32carry OpSub32withcarry OpAdd64carry @@ -3408,6 +7169,1607 @@ const ( OpClobberReg OpPrefetchCache OpPrefetchCacheStreamed + OpMemEq + OpEmpty + OpZeroSIMD + OpCvt16toMask8x16 + OpCvt32toMask8x32 + OpCvt64toMask8x64 + OpCvt8toMask16x8 + OpCvt16toMask16x16 + OpCvt32toMask16x32 + OpCvt8toMask32x4 + OpCvt8toMask32x8 + OpCvt16toMask32x16 + OpCvt8toMask64x2 + OpCvt8toMask64x4 + OpCvt8toMask64x8 + OpCvtMask8x16to16 + OpCvtMask8x32to32 + OpCvtMask8x64to64 + OpCvtMask16x8to8 + OpCvtMask16x16to16 + OpCvtMask16x32to32 + OpCvtMask32x4to8 + OpCvtMask32x8to8 + OpCvtMask32x16to16 + OpCvtMask64x2to8 + OpCvtMask64x4to8 + OpCvtMask64x8to8 + OpIsZeroVec + OpIsNaNFloat32x4 + OpIsNaNFloat32x8 + OpIsNaNFloat32x16 + OpIsNaNFloat64x2 + OpIsNaNFloat64x4 + OpIsNaNFloat64x8 + OpAESDecryptLastRoundUint8x16 + OpAESDecryptLastRoundUint8x32 + OpAESDecryptLastRoundUint8x64 + OpAESDecryptOneRoundUint8x16 + OpAESDecryptOneRoundUint8x32 + OpAESDecryptOneRoundUint8x64 + OpAESEncryptLastRoundUint8x16 + OpAESEncryptLastRoundUint8x32 + OpAESEncryptLastRoundUint8x64 + OpAESEncryptOneRoundUint8x16 + OpAESEncryptOneRoundUint8x32 + OpAESEncryptOneRoundUint8x64 + OpAESInvMixColumnsUint32x4 + OpAbsFloat32x4 + OpAbsFloat64x2 + OpAbsInt8x16 + OpAbsInt8x32 + OpAbsInt8x64 + OpAbsInt16x8 + OpAbsInt16x16 + OpAbsInt16x32 + OpAbsInt32x4 + OpAbsInt32x8 + OpAbsInt32x16 + OpAbsInt64x2 + OpAbsInt64x4 + OpAbsInt64x8 + OpAddFloat32x4 + OpAddFloat32x8 + OpAddFloat32x16 + OpAddFloat64x2 + OpAddFloat64x4 + OpAddFloat64x8 + OpAddInt8x16 + OpAddInt8x32 + OpAddInt8x64 + OpAddInt16x8 + OpAddInt16x16 + OpAddInt16x32 + OpAddInt32x4 + OpAddInt32x8 + OpAddInt32x16 + OpAddInt64x2 + OpAddInt64x4 + OpAddInt64x8 + OpAddOddSubEvenFloat32x4 + OpAddOddSubEvenFloat32x8 + OpAddOddSubEvenFloat64x2 + OpAddOddSubEvenFloat64x4 + OpAddSaturatedInt8x16 + OpAddSaturatedInt8x32 + OpAddSaturatedInt8x64 + OpAddSaturatedInt16x8 + OpAddSaturatedInt16x16 + OpAddSaturatedInt16x32 + OpAddSaturatedInt32x4 + OpAddSaturatedInt64x2 + OpAddSaturatedUint8x16 + OpAddSaturatedUint8x32 + OpAddSaturatedUint8x64 + OpAddSaturatedUint16x8 + OpAddSaturatedUint16x16 + OpAddSaturatedUint16x32 + OpAddSaturatedUint32x4 + OpAddSaturatedUint64x2 + OpAddUint8x16 + OpAddUint8x32 + OpAddUint8x64 + OpAddUint16x8 + OpAddUint16x16 + OpAddUint16x32 + OpAddUint32x4 + OpAddUint32x8 + OpAddUint32x16 + OpAddUint64x2 + OpAddUint64x4 + OpAddUint64x8 + OpAndInt8x16 + OpAndInt8x32 + OpAndInt8x64 + OpAndInt16x8 + OpAndInt16x16 + OpAndInt16x32 + OpAndInt32x4 + OpAndInt32x8 + OpAndInt32x16 + OpAndInt64x2 + OpAndInt64x4 + OpAndInt64x8 + OpAndNotInt8x16 + OpAndNotInt8x32 + OpAndNotInt8x64 + OpAndNotInt16x8 + OpAndNotInt16x16 + OpAndNotInt16x32 + OpAndNotInt32x4 + OpAndNotInt32x8 + OpAndNotInt32x16 + OpAndNotInt64x2 + OpAndNotInt64x4 + OpAndNotInt64x8 + OpAndNotUint8x16 + OpAndNotUint8x32 + OpAndNotUint8x64 + OpAndNotUint16x8 + OpAndNotUint16x16 + OpAndNotUint16x32 + OpAndNotUint32x4 + OpAndNotUint32x8 + OpAndNotUint32x16 + OpAndNotUint64x2 + OpAndNotUint64x4 + OpAndNotUint64x8 + OpAndUint8x16 + OpAndUint8x32 + OpAndUint8x64 + OpAndUint16x8 + OpAndUint16x16 + OpAndUint16x32 + OpAndUint32x4 + OpAndUint32x8 + OpAndUint32x16 + OpAndUint64x2 + OpAndUint64x4 + OpAndUint64x8 + OpAverageInt8x16 + OpAverageInt16x8 + OpAverageInt32x4 + OpAverageUint8x16 + OpAverageUint8x32 + OpAverageUint8x64 + OpAverageUint16x8 + OpAverageUint16x16 + OpAverageUint16x32 + OpAverageUint32x4 + OpBitSelectInt8x16 + OpBitSelectInt16x8 + OpBitSelectInt32x4 + OpBitSelectInt64x2 + OpBitSelectUint8x16 + OpBitSelectUint16x8 + OpBitSelectUint32x4 + OpBitSelectUint64x2 + OpBroadcastFloat32x4 + OpBroadcastFloat64x2 + OpBroadcastInt8x16 + OpBroadcastInt16x8 + OpBroadcastInt32x4 + OpBroadcastInt64x2 + OpCeilFloat32x4 + OpCeilFloat32x8 + OpCeilFloat64x2 + OpCeilFloat64x4 + OpCompressFloat32x4 + OpCompressFloat32x8 + OpCompressFloat32x16 + OpCompressFloat64x2 + OpCompressFloat64x4 + OpCompressFloat64x8 + OpCompressInt8x16 + OpCompressInt8x32 + OpCompressInt8x64 + OpCompressInt16x8 + OpCompressInt16x16 + OpCompressInt16x32 + OpCompressInt32x4 + OpCompressInt32x8 + OpCompressInt32x16 + OpCompressInt64x2 + OpCompressInt64x4 + OpCompressInt64x8 + OpCompressUint8x16 + OpCompressUint8x32 + OpCompressUint8x64 + OpCompressUint16x8 + OpCompressUint16x16 + OpCompressUint16x32 + OpCompressUint32x4 + OpCompressUint32x8 + OpCompressUint32x16 + OpCompressUint64x2 + OpCompressUint64x4 + OpCompressUint64x8 + OpConcatAddPairsFloat32x4 + OpConcatAddPairsFloat64x2 + OpConcatAddPairsGroupedFloat32x8 + OpConcatAddPairsGroupedFloat64x4 + OpConcatAddPairsGroupedInt16x16 + OpConcatAddPairsGroupedInt32x8 + OpConcatAddPairsGroupedUint16x16 + OpConcatAddPairsGroupedUint32x8 + OpConcatAddPairsInt16x8 + OpConcatAddPairsInt32x4 + OpConcatAddPairsInt64x2 + OpConcatAddPairsSaturatedGroupedInt16x16 + OpConcatAddPairsSaturatedInt16x8 + OpConcatAddPairsUint16x8 + OpConcatAddPairsUint32x4 + OpConcatAddPairsUint64x2 + OpConcatEvenInt8x16 + OpConcatEvenInt16x8 + OpConcatEvenInt32x4 + OpConcatEvenInt64x2 + OpConcatEvenUint8x16 + OpConcatEvenUint16x8 + OpConcatEvenUint32x4 + OpConcatEvenUint64x2 + OpConcatOddInt8x16 + OpConcatOddInt16x8 + OpConcatOddInt32x4 + OpConcatOddInt64x2 + OpConcatOddUint8x16 + OpConcatOddUint16x8 + OpConcatOddUint32x4 + OpConcatOddUint64x2 + OpConcatPermuteFloat32x4 + OpConcatPermuteFloat32x8 + OpConcatPermuteFloat32x16 + OpConcatPermuteFloat64x2 + OpConcatPermuteFloat64x4 + OpConcatPermuteFloat64x8 + OpConcatPermuteInt8x16 + OpConcatPermuteInt8x32 + OpConcatPermuteInt8x64 + OpConcatPermuteInt16x8 + OpConcatPermuteInt16x16 + OpConcatPermuteInt16x32 + OpConcatPermuteInt32x4 + OpConcatPermuteInt32x8 + OpConcatPermuteInt32x16 + OpConcatPermuteInt64x2 + OpConcatPermuteInt64x4 + OpConcatPermuteInt64x8 + OpConcatPermuteUint8x16 + OpConcatPermuteUint8x32 + OpConcatPermuteUint8x64 + OpConcatPermuteUint16x8 + OpConcatPermuteUint16x16 + OpConcatPermuteUint16x32 + OpConcatPermuteUint32x4 + OpConcatPermuteUint32x8 + OpConcatPermuteUint32x16 + OpConcatPermuteUint64x2 + OpConcatPermuteUint64x4 + OpConcatPermuteUint64x8 + OpConcatSubPairsFloat32x4 + OpConcatSubPairsFloat64x2 + OpConcatSubPairsGroupedFloat32x8 + OpConcatSubPairsGroupedFloat64x4 + OpConcatSubPairsGroupedInt16x16 + OpConcatSubPairsGroupedInt32x8 + OpConcatSubPairsGroupedUint16x16 + OpConcatSubPairsGroupedUint32x8 + OpConcatSubPairsInt16x8 + OpConcatSubPairsInt32x4 + OpConcatSubPairsSaturatedGroupedInt16x16 + OpConcatSubPairsSaturatedInt16x8 + OpConcatSubPairsUint16x8 + OpConcatSubPairsUint32x4 + OpConvertLo2ToFloat64Float32x4 + OpConvertLo2ToFloat64Int32x4 + OpConvertLo2ToFloat64Uint32x4 + OpConvertToFloat32Float64x2 + OpConvertToFloat32Float64x4 + OpConvertToFloat32Float64x8 + OpConvertToFloat32Int32x4 + OpConvertToFloat32Int32x8 + OpConvertToFloat32Int32x16 + OpConvertToFloat32Int64x2 + OpConvertToFloat32Int64x4 + OpConvertToFloat32Int64x8 + OpConvertToFloat32Uint32x4 + OpConvertToFloat32Uint32x8 + OpConvertToFloat32Uint32x16 + OpConvertToFloat32Uint64x2 + OpConvertToFloat32Uint64x4 + OpConvertToFloat32Uint64x8 + OpConvertToFloat64Float32x4 + OpConvertToFloat64Float32x8 + OpConvertToFloat64Int32x4 + OpConvertToFloat64Int32x8 + OpConvertToFloat64Int64x2 + OpConvertToFloat64Int64x4 + OpConvertToFloat64Int64x8 + OpConvertToFloat64Uint32x4 + OpConvertToFloat64Uint32x8 + OpConvertToFloat64Uint64x2 + OpConvertToFloat64Uint64x4 + OpConvertToFloat64Uint64x8 + OpConvertToInt32Float32x4 + OpConvertToInt32Float32x8 + OpConvertToInt32Float32x16 + OpConvertToInt32Float64x2 + OpConvertToInt32Float64x4 + OpConvertToInt32Float64x8 + OpConvertToInt64Float32x4 + OpConvertToInt64Float32x8 + OpConvertToInt64Float64x2 + OpConvertToInt64Float64x4 + OpConvertToInt64Float64x8 + OpConvertToUint32Float32x4 + OpConvertToUint32Float32x8 + OpConvertToUint32Float32x16 + OpConvertToUint32Float64x2 + OpConvertToUint32Float64x4 + OpConvertToUint32Float64x8 + OpConvertToUint64Float32x4 + OpConvertToUint64Float32x8 + OpConvertToUint64Float64x2 + OpConvertToUint64Float64x4 + OpConvertToUint64Float64x8 + OpDivFloat32x4 + OpDivFloat32x8 + OpDivFloat32x16 + OpDivFloat64x2 + OpDivFloat64x4 + OpDivFloat64x8 + OpDotProductPairsInt16x8 + OpDotProductPairsInt16x16 + OpDotProductPairsInt16x32 + OpDotProductPairsSaturatedUint8x16 + OpDotProductPairsSaturatedUint8x32 + OpDotProductPairsSaturatedUint8x64 + OpEqualFloat32x4 + OpEqualFloat32x8 + OpEqualFloat32x16 + OpEqualFloat64x2 + OpEqualFloat64x4 + OpEqualFloat64x8 + OpEqualInt8x16 + OpEqualInt8x32 + OpEqualInt8x64 + OpEqualInt16x8 + OpEqualInt16x16 + OpEqualInt16x32 + OpEqualInt32x4 + OpEqualInt32x8 + OpEqualInt32x16 + OpEqualInt64x2 + OpEqualInt64x4 + OpEqualInt64x8 + OpEqualUint8x16 + OpEqualUint8x32 + OpEqualUint8x64 + OpEqualUint16x8 + OpEqualUint16x16 + OpEqualUint16x32 + OpEqualUint32x4 + OpEqualUint32x8 + OpEqualUint32x16 + OpEqualUint64x2 + OpEqualUint64x4 + OpEqualUint64x8 + OpExpandFloat32x4 + OpExpandFloat32x8 + OpExpandFloat32x16 + OpExpandFloat64x2 + OpExpandFloat64x4 + OpExpandFloat64x8 + OpExpandInt8x16 + OpExpandInt8x32 + OpExpandInt8x64 + OpExpandInt16x8 + OpExpandInt16x16 + OpExpandInt16x32 + OpExpandInt32x4 + OpExpandInt32x8 + OpExpandInt32x16 + OpExpandInt64x2 + OpExpandInt64x4 + OpExpandInt64x8 + OpExpandUint8x16 + OpExpandUint8x32 + OpExpandUint8x64 + OpExpandUint16x8 + OpExpandUint16x16 + OpExpandUint16x32 + OpExpandUint32x4 + OpExpandUint32x8 + OpExpandUint32x16 + OpExpandUint64x2 + OpExpandUint64x4 + OpExpandUint64x8 + OpExtendHi2ToInt64Int32x4 + OpExtendHi2ToUint64Uint32x4 + OpExtendHi4ToInt32Int16x8 + OpExtendHi4ToUint32Uint16x8 + OpExtendHi8ToInt16Int8x16 + OpExtendHi8ToUint16Uint8x16 + OpExtendLo2ToInt64Int8x16 + OpExtendLo2ToInt64Int16x8 + OpExtendLo2ToInt64Int32x4 + OpExtendLo2ToUint64Uint8x16 + OpExtendLo2ToUint64Uint16x8 + OpExtendLo2ToUint64Uint32x4 + OpExtendLo4ToInt32Int8x16 + OpExtendLo4ToInt32Int16x8 + OpExtendLo4ToInt64Int8x16 + OpExtendLo4ToInt64Int16x8 + OpExtendLo4ToUint32Uint8x16 + OpExtendLo4ToUint32Uint16x8 + OpExtendLo4ToUint64Uint8x16 + OpExtendLo4ToUint64Uint16x8 + OpExtendLo8ToInt16Int8x16 + OpExtendLo8ToInt32Int8x16 + OpExtendLo8ToInt64Int8x16 + OpExtendLo8ToUint16Uint8x16 + OpExtendLo8ToUint32Uint8x16 + OpExtendLo8ToUint64Uint8x16 + OpExtendToInt16Int8x16 + OpExtendToInt16Int8x32 + OpExtendToInt32Int8x16 + OpExtendToInt32Int16x8 + OpExtendToInt32Int16x16 + OpExtendToInt64Int16x8 + OpExtendToInt64Int32x4 + OpExtendToInt64Int32x8 + OpExtendToUint16Uint8x16 + OpExtendToUint16Uint8x32 + OpExtendToUint32Uint8x16 + OpExtendToUint32Uint16x8 + OpExtendToUint32Uint16x16 + OpExtendToUint64Uint16x8 + OpExtendToUint64Uint32x4 + OpExtendToUint64Uint32x8 + OpFloorFloat32x4 + OpFloorFloat32x8 + OpFloorFloat64x2 + OpFloorFloat64x4 + OpGaloisFieldMulUint8x16 + OpGaloisFieldMulUint8x32 + OpGaloisFieldMulUint8x64 + OpGetHiFloat32x8 + OpGetHiFloat32x16 + OpGetHiFloat64x4 + OpGetHiFloat64x8 + OpGetHiInt8x32 + OpGetHiInt8x64 + OpGetHiInt16x16 + OpGetHiInt16x32 + OpGetHiInt32x8 + OpGetHiInt32x16 + OpGetHiInt64x4 + OpGetHiInt64x8 + OpGetHiUint8x32 + OpGetHiUint8x64 + OpGetHiUint16x16 + OpGetHiUint16x32 + OpGetHiUint32x8 + OpGetHiUint32x16 + OpGetHiUint64x4 + OpGetHiUint64x8 + OpGetLoFloat32x8 + OpGetLoFloat32x16 + OpGetLoFloat64x4 + OpGetLoFloat64x8 + OpGetLoInt8x32 + OpGetLoInt8x64 + OpGetLoInt16x16 + OpGetLoInt16x32 + OpGetLoInt32x8 + OpGetLoInt32x16 + OpGetLoInt64x4 + OpGetLoInt64x8 + OpGetLoUint8x32 + OpGetLoUint8x64 + OpGetLoUint16x16 + OpGetLoUint16x32 + OpGetLoUint32x8 + OpGetLoUint32x16 + OpGetLoUint64x4 + OpGetLoUint64x8 + OpGreaterEqualFloat32x4 + OpGreaterEqualFloat32x8 + OpGreaterEqualFloat32x16 + OpGreaterEqualFloat64x2 + OpGreaterEqualFloat64x4 + OpGreaterEqualFloat64x8 + OpGreaterEqualInt8x16 + OpGreaterEqualInt8x64 + OpGreaterEqualInt16x8 + OpGreaterEqualInt16x32 + OpGreaterEqualInt32x4 + OpGreaterEqualInt32x16 + OpGreaterEqualInt64x2 + OpGreaterEqualInt64x8 + OpGreaterEqualUint8x16 + OpGreaterEqualUint8x64 + OpGreaterEqualUint16x8 + OpGreaterEqualUint16x32 + OpGreaterEqualUint32x4 + OpGreaterEqualUint32x16 + OpGreaterEqualUint64x2 + OpGreaterEqualUint64x8 + OpGreaterFloat32x4 + OpGreaterFloat32x8 + OpGreaterFloat32x16 + OpGreaterFloat64x2 + OpGreaterFloat64x4 + OpGreaterFloat64x8 + OpGreaterInt8x16 + OpGreaterInt8x32 + OpGreaterInt8x64 + OpGreaterInt16x8 + OpGreaterInt16x16 + OpGreaterInt16x32 + OpGreaterInt32x4 + OpGreaterInt32x8 + OpGreaterInt32x16 + OpGreaterInt64x2 + OpGreaterInt64x4 + OpGreaterInt64x8 + OpGreaterUint8x16 + OpGreaterUint8x64 + OpGreaterUint16x8 + OpGreaterUint16x32 + OpGreaterUint32x4 + OpGreaterUint32x16 + OpGreaterUint64x2 + OpGreaterUint64x8 + OpInterleaveEvenInt8x16 + OpInterleaveEvenInt16x8 + OpInterleaveEvenInt32x4 + OpInterleaveEvenInt64x2 + OpInterleaveEvenUint8x16 + OpInterleaveEvenUint16x8 + OpInterleaveEvenUint32x4 + OpInterleaveEvenUint64x2 + OpInterleaveHiGroupedInt16x16 + OpInterleaveHiGroupedInt16x32 + OpInterleaveHiGroupedInt32x8 + OpInterleaveHiGroupedInt32x16 + OpInterleaveHiGroupedInt64x4 + OpInterleaveHiGroupedInt64x8 + OpInterleaveHiGroupedUint16x16 + OpInterleaveHiGroupedUint16x32 + OpInterleaveHiGroupedUint32x8 + OpInterleaveHiGroupedUint32x16 + OpInterleaveHiGroupedUint64x4 + OpInterleaveHiGroupedUint64x8 + OpInterleaveHiInt8x16 + OpInterleaveHiInt16x8 + OpInterleaveHiInt32x4 + OpInterleaveHiInt64x2 + OpInterleaveHiUint8x16 + OpInterleaveHiUint16x8 + OpInterleaveHiUint32x4 + OpInterleaveHiUint64x2 + OpInterleaveLoGroupedInt16x16 + OpInterleaveLoGroupedInt16x32 + OpInterleaveLoGroupedInt32x8 + OpInterleaveLoGroupedInt32x16 + OpInterleaveLoGroupedInt64x4 + OpInterleaveLoGroupedInt64x8 + OpInterleaveLoGroupedUint16x16 + OpInterleaveLoGroupedUint16x32 + OpInterleaveLoGroupedUint32x8 + OpInterleaveLoGroupedUint32x16 + OpInterleaveLoGroupedUint64x4 + OpInterleaveLoGroupedUint64x8 + OpInterleaveLoInt8x16 + OpInterleaveLoInt16x8 + OpInterleaveLoInt32x4 + OpInterleaveLoInt64x2 + OpInterleaveLoUint8x16 + OpInterleaveLoUint16x8 + OpInterleaveLoUint32x4 + OpInterleaveLoUint64x2 + OpInterleaveOddInt8x16 + OpInterleaveOddInt16x8 + OpInterleaveOddInt32x4 + OpInterleaveOddInt64x2 + OpInterleaveOddUint8x16 + OpInterleaveOddUint16x8 + OpInterleaveOddUint32x4 + OpInterleaveOddUint64x2 + OpLeadingSignBitsInt8x16 + OpLeadingSignBitsInt16x8 + OpLeadingSignBitsInt32x4 + OpLeadingSignBitsUint8x16 + OpLeadingSignBitsUint16x8 + OpLeadingSignBitsUint32x4 + OpLeadingZerosInt8x16 + OpLeadingZerosInt16x8 + OpLeadingZerosInt32x4 + OpLeadingZerosInt32x8 + OpLeadingZerosInt32x16 + OpLeadingZerosInt64x2 + OpLeadingZerosInt64x4 + OpLeadingZerosInt64x8 + OpLeadingZerosUint8x16 + OpLeadingZerosUint16x8 + OpLeadingZerosUint32x4 + OpLeadingZerosUint32x8 + OpLeadingZerosUint32x16 + OpLeadingZerosUint64x2 + OpLeadingZerosUint64x4 + OpLeadingZerosUint64x8 + OpLessEqualFloat32x4 + OpLessEqualFloat32x8 + OpLessEqualFloat32x16 + OpLessEqualFloat64x2 + OpLessEqualFloat64x4 + OpLessEqualFloat64x8 + OpLessEqualInt8x16 + OpLessEqualInt8x64 + OpLessEqualInt16x8 + OpLessEqualInt16x32 + OpLessEqualInt32x4 + OpLessEqualInt32x16 + OpLessEqualInt64x2 + OpLessEqualInt64x8 + OpLessEqualUint8x16 + OpLessEqualUint8x64 + OpLessEqualUint16x8 + OpLessEqualUint16x32 + OpLessEqualUint32x4 + OpLessEqualUint32x16 + OpLessEqualUint64x8 + OpLessFloat32x4 + OpLessFloat32x8 + OpLessFloat32x16 + OpLessFloat64x2 + OpLessFloat64x4 + OpLessFloat64x8 + OpLessInt8x16 + OpLessInt8x64 + OpLessInt16x8 + OpLessInt16x32 + OpLessInt32x4 + OpLessInt32x16 + OpLessInt64x2 + OpLessInt64x8 + OpLessUint8x16 + OpLessUint8x64 + OpLessUint16x8 + OpLessUint16x32 + OpLessUint32x4 + OpLessUint32x16 + OpLessUint64x8 + OpLookupOrZeroInt8x16 + OpLookupOrZeroUint8x16 + OpMaxFloat32x4 + OpMaxFloat32x8 + OpMaxFloat32x16 + OpMaxFloat64x2 + OpMaxFloat64x4 + OpMaxFloat64x8 + OpMaxInt8x16 + OpMaxInt8x32 + OpMaxInt8x64 + OpMaxInt16x8 + OpMaxInt16x16 + OpMaxInt16x32 + OpMaxInt32x4 + OpMaxInt32x8 + OpMaxInt32x16 + OpMaxInt64x2 + OpMaxInt64x4 + OpMaxInt64x8 + OpMaxUint8x16 + OpMaxUint8x32 + OpMaxUint8x64 + OpMaxUint16x8 + OpMaxUint16x16 + OpMaxUint16x32 + OpMaxUint32x4 + OpMaxUint32x8 + OpMaxUint32x16 + OpMaxUint64x2 + OpMaxUint64x4 + OpMaxUint64x8 + OpMinFloat32x4 + OpMinFloat32x8 + OpMinFloat32x16 + OpMinFloat64x2 + OpMinFloat64x4 + OpMinFloat64x8 + OpMinInt8x16 + OpMinInt8x32 + OpMinInt8x64 + OpMinInt16x8 + OpMinInt16x16 + OpMinInt16x32 + OpMinInt32x4 + OpMinInt32x8 + OpMinInt32x16 + OpMinInt64x2 + OpMinInt64x4 + OpMinInt64x8 + OpMinUint8x16 + OpMinUint8x32 + OpMinUint8x64 + OpMinUint16x8 + OpMinUint16x16 + OpMinUint16x32 + OpMinUint32x4 + OpMinUint32x8 + OpMinUint32x16 + OpMinUint64x2 + OpMinUint64x4 + OpMinUint64x8 + OpMulAddEvenSubOddFloat32x4 + OpMulAddEvenSubOddFloat32x8 + OpMulAddEvenSubOddFloat32x16 + OpMulAddEvenSubOddFloat64x2 + OpMulAddEvenSubOddFloat64x4 + OpMulAddEvenSubOddFloat64x8 + OpMulAddFloat32x4 + OpMulAddFloat32x8 + OpMulAddFloat32x16 + OpMulAddFloat64x2 + OpMulAddFloat64x4 + OpMulAddFloat64x8 + OpMulAddInt8x16 + OpMulAddInt16x8 + OpMulAddInt32x4 + OpMulAddOddSubEvenFloat32x4 + OpMulAddOddSubEvenFloat32x8 + OpMulAddOddSubEvenFloat32x16 + OpMulAddOddSubEvenFloat64x2 + OpMulAddOddSubEvenFloat64x4 + OpMulAddOddSubEvenFloat64x8 + OpMulAddUint8x16 + OpMulAddUint16x8 + OpMulAddUint32x4 + OpMulFloat32x4 + OpMulFloat32x8 + OpMulFloat32x16 + OpMulFloat64x2 + OpMulFloat64x4 + OpMulFloat64x8 + OpMulHighInt16x8 + OpMulHighInt16x16 + OpMulHighInt16x32 + OpMulHighUint16x8 + OpMulHighUint16x16 + OpMulHighUint16x32 + OpMulInt8x16 + OpMulInt16x8 + OpMulInt16x16 + OpMulInt16x32 + OpMulInt32x4 + OpMulInt32x8 + OpMulInt32x16 + OpMulInt64x2 + OpMulInt64x4 + OpMulInt64x8 + OpMulSignInt8x16 + OpMulSignInt8x32 + OpMulSignInt16x8 + OpMulSignInt16x16 + OpMulSignInt32x4 + OpMulSignInt32x8 + OpMulUint8x16 + OpMulUint16x8 + OpMulUint16x16 + OpMulUint16x32 + OpMulUint32x4 + OpMulUint32x8 + OpMulUint32x16 + OpMulUint64x2 + OpMulUint64x4 + OpMulUint64x8 + OpMulWidenEvenInt32x4 + OpMulWidenEvenInt32x8 + OpMulWidenEvenUint32x4 + OpMulWidenEvenUint32x8 + OpMulWidenHiInt8x16 + OpMulWidenHiInt16x8 + OpMulWidenHiInt32x4 + OpMulWidenHiUint8x16 + OpMulWidenHiUint16x8 + OpMulWidenHiUint32x4 + OpMulWidenLoInt8x16 + OpMulWidenLoInt16x8 + OpMulWidenLoInt32x4 + OpMulWidenLoUint8x16 + OpMulWidenLoUint16x8 + OpMulWidenLoUint32x4 + OpNegFloat32x4 + OpNegFloat64x2 + OpNegInt8x16 + OpNegInt16x8 + OpNegInt32x4 + OpNegInt64x2 + OpNotEqualFloat32x4 + OpNotEqualFloat32x8 + OpNotEqualFloat32x16 + OpNotEqualFloat64x2 + OpNotEqualFloat64x4 + OpNotEqualFloat64x8 + OpNotEqualInt8x16 + OpNotEqualInt8x64 + OpNotEqualInt16x8 + OpNotEqualInt16x32 + OpNotEqualInt32x4 + OpNotEqualInt32x16 + OpNotEqualInt64x2 + OpNotEqualInt64x8 + OpNotEqualUint8x16 + OpNotEqualUint8x64 + OpNotEqualUint16x8 + OpNotEqualUint16x32 + OpNotEqualUint32x4 + OpNotEqualUint32x16 + OpNotEqualUint64x2 + OpNotEqualUint64x8 + OpNotInt8x16 + OpNotInt16x8 + OpNotInt32x4 + OpNotInt64x2 + OpNotUint8x16 + OpNotUint16x8 + OpNotUint32x4 + OpNotUint64x2 + OpOnesCountInt8x16 + OpOnesCountInt8x32 + OpOnesCountInt8x64 + OpOnesCountInt16x8 + OpOnesCountInt16x16 + OpOnesCountInt16x32 + OpOnesCountInt32x4 + OpOnesCountInt32x8 + OpOnesCountInt32x16 + OpOnesCountInt64x2 + OpOnesCountInt64x4 + OpOnesCountInt64x8 + OpOnesCountUint8x16 + OpOnesCountUint8x32 + OpOnesCountUint8x64 + OpOnesCountUint16x8 + OpOnesCountUint16x16 + OpOnesCountUint16x32 + OpOnesCountUint32x4 + OpOnesCountUint32x8 + OpOnesCountUint32x16 + OpOnesCountUint64x2 + OpOnesCountUint64x4 + OpOnesCountUint64x8 + OpOrInt8x16 + OpOrInt8x32 + OpOrInt8x64 + OpOrInt16x8 + OpOrInt16x16 + OpOrInt16x32 + OpOrInt32x4 + OpOrInt32x8 + OpOrInt32x16 + OpOrInt64x2 + OpOrInt64x4 + OpOrInt64x8 + OpOrNotInt8x16 + OpOrNotInt16x8 + OpOrNotInt32x4 + OpOrNotInt64x2 + OpOrNotUint8x16 + OpOrNotUint16x8 + OpOrNotUint32x4 + OpOrNotUint64x2 + OpOrUint8x16 + OpOrUint8x32 + OpOrUint8x64 + OpOrUint16x8 + OpOrUint16x16 + OpOrUint16x32 + OpOrUint32x4 + OpOrUint32x8 + OpOrUint32x16 + OpOrUint64x2 + OpOrUint64x4 + OpOrUint64x8 + OpPermuteFloat32x8 + OpPermuteFloat32x16 + OpPermuteFloat64x4 + OpPermuteFloat64x8 + OpPermuteInt8x16 + OpPermuteInt8x32 + OpPermuteInt8x64 + OpPermuteInt16x8 + OpPermuteInt16x16 + OpPermuteInt16x32 + OpPermuteInt32x8 + OpPermuteInt32x16 + OpPermuteInt64x4 + OpPermuteInt64x8 + OpPermuteOrZeroGroupedInt8x32 + OpPermuteOrZeroGroupedInt8x64 + OpPermuteOrZeroGroupedUint8x32 + OpPermuteOrZeroGroupedUint8x64 + OpPermuteOrZeroInt8x16 + OpPermuteOrZeroUint8x16 + OpPermuteUint8x16 + OpPermuteUint8x32 + OpPermuteUint8x64 + OpPermuteUint16x8 + OpPermuteUint16x16 + OpPermuteUint16x32 + OpPermuteUint32x8 + OpPermuteUint32x16 + OpPermuteUint64x4 + OpPermuteUint64x8 + OpReciprocalFloat32x4 + OpReciprocalFloat32x8 + OpReciprocalFloat32x16 + OpReciprocalFloat64x2 + OpReciprocalFloat64x4 + OpReciprocalFloat64x8 + OpReciprocalSqrtFloat32x4 + OpReciprocalSqrtFloat32x8 + OpReciprocalSqrtFloat32x16 + OpReciprocalSqrtFloat64x2 + OpReciprocalSqrtFloat64x4 + OpReciprocalSqrtFloat64x8 + OpRotateAllLeftVarInt8x16 + OpRotateAllLeftVarInt16x8 + OpRotateAllLeftVarInt32x4 + OpRotateAllLeftVarInt64x2 + OpRotateAllLeftVarUint8x16 + OpRotateAllLeftVarUint16x8 + OpRotateAllLeftVarUint32x4 + OpRotateAllLeftVarUint64x2 + OpRotateAllRightVarInt8x16 + OpRotateAllRightVarInt16x8 + OpRotateAllRightVarInt32x4 + OpRotateAllRightVarInt64x2 + OpRotateAllRightVarUint8x16 + OpRotateAllRightVarUint16x8 + OpRotateAllRightVarUint32x4 + OpRotateAllRightVarUint64x2 + OpRotateLeftInt32x4 + OpRotateLeftInt32x8 + OpRotateLeftInt32x16 + OpRotateLeftInt64x2 + OpRotateLeftInt64x4 + OpRotateLeftInt64x8 + OpRotateLeftUint32x4 + OpRotateLeftUint32x8 + OpRotateLeftUint32x16 + OpRotateLeftUint64x2 + OpRotateLeftUint64x4 + OpRotateLeftUint64x8 + OpRotateRightInt32x4 + OpRotateRightInt32x8 + OpRotateRightInt32x16 + OpRotateRightInt64x2 + OpRotateRightInt64x4 + OpRotateRightInt64x8 + OpRotateRightUint32x4 + OpRotateRightUint32x8 + OpRotateRightUint32x16 + OpRotateRightUint64x2 + OpRotateRightUint64x4 + OpRotateRightUint64x8 + OpRoundFloat32x4 + OpRoundFloat32x8 + OpRoundFloat64x2 + OpRoundFloat64x4 + OpSHA1Message1Uint32x4 + OpSHA1Message2Uint32x4 + OpSHA1NextEUint32x4 + OpSHA256Message1Uint32x4 + OpSHA256Message2Uint32x4 + OpSHA256TwoRoundsUint32x4 + OpSaturateToInt8Int16x8 + OpSaturateToInt8Int16x16 + OpSaturateToInt8Int16x32 + OpSaturateToInt8Int32x4 + OpSaturateToInt8Int32x8 + OpSaturateToInt8Int32x16 + OpSaturateToInt8Int64x2 + OpSaturateToInt8Int64x4 + OpSaturateToInt8Int64x8 + OpSaturateToInt16ConcatGroupedInt32x8 + OpSaturateToInt16ConcatGroupedInt32x16 + OpSaturateToInt16ConcatInt32x4 + OpSaturateToInt16Int32x4 + OpSaturateToInt16Int32x8 + OpSaturateToInt16Int32x16 + OpSaturateToInt16Int64x2 + OpSaturateToInt16Int64x4 + OpSaturateToInt16Int64x8 + OpSaturateToInt32Int64x2 + OpSaturateToInt32Int64x4 + OpSaturateToInt32Int64x8 + OpSaturateToUint8Int16x8 + OpSaturateToUint8Uint16x8 + OpSaturateToUint8Uint16x16 + OpSaturateToUint8Uint16x32 + OpSaturateToUint8Uint32x4 + OpSaturateToUint8Uint32x8 + OpSaturateToUint8Uint32x16 + OpSaturateToUint8Uint64x2 + OpSaturateToUint8Uint64x4 + OpSaturateToUint8Uint64x8 + OpSaturateToUint16ConcatGroupedInt32x8 + OpSaturateToUint16ConcatGroupedInt32x16 + OpSaturateToUint16ConcatInt32x4 + OpSaturateToUint16Int32x4 + OpSaturateToUint16Uint32x4 + OpSaturateToUint16Uint32x8 + OpSaturateToUint16Uint32x16 + OpSaturateToUint16Uint64x2 + OpSaturateToUint16Uint64x4 + OpSaturateToUint16Uint64x8 + OpSaturateToUint32Int64x2 + OpSaturateToUint32Uint64x2 + OpSaturateToUint32Uint64x4 + OpSaturateToUint32Uint64x8 + OpScaleFloat32x4 + OpScaleFloat32x8 + OpScaleFloat32x16 + OpScaleFloat64x2 + OpScaleFloat64x4 + OpScaleFloat64x8 + OpSetHiFloat32x8 + OpSetHiFloat32x16 + OpSetHiFloat64x4 + OpSetHiFloat64x8 + OpSetHiInt8x32 + OpSetHiInt8x64 + OpSetHiInt16x16 + OpSetHiInt16x32 + OpSetHiInt32x8 + OpSetHiInt32x16 + OpSetHiInt64x4 + OpSetHiInt64x8 + OpSetHiUint8x32 + OpSetHiUint8x64 + OpSetHiUint16x16 + OpSetHiUint16x32 + OpSetHiUint32x8 + OpSetHiUint32x16 + OpSetHiUint64x4 + OpSetHiUint64x8 + OpSetLoFloat32x8 + OpSetLoFloat32x16 + OpSetLoFloat64x4 + OpSetLoFloat64x8 + OpSetLoInt8x32 + OpSetLoInt8x64 + OpSetLoInt16x16 + OpSetLoInt16x32 + OpSetLoInt32x8 + OpSetLoInt32x16 + OpSetLoInt64x4 + OpSetLoInt64x8 + OpSetLoUint8x32 + OpSetLoUint8x64 + OpSetLoUint16x16 + OpSetLoUint16x32 + OpSetLoUint32x8 + OpSetLoUint32x16 + OpSetLoUint64x4 + OpSetLoUint64x8 + OpShiftAllLeftInt8x16 + OpShiftAllLeftInt16x8 + OpShiftAllLeftInt16x16 + OpShiftAllLeftInt16x32 + OpShiftAllLeftInt32x4 + OpShiftAllLeftInt32x8 + OpShiftAllLeftInt32x16 + OpShiftAllLeftInt64x2 + OpShiftAllLeftInt64x4 + OpShiftAllLeftInt64x8 + OpShiftAllLeftUint8x16 + OpShiftAllLeftUint16x8 + OpShiftAllLeftUint16x16 + OpShiftAllLeftUint16x32 + OpShiftAllLeftUint32x4 + OpShiftAllLeftUint32x8 + OpShiftAllLeftUint32x16 + OpShiftAllLeftUint64x2 + OpShiftAllLeftUint64x4 + OpShiftAllLeftUint64x8 + OpShiftAllRightInt8x16 + OpShiftAllRightInt16x8 + OpShiftAllRightInt16x16 + OpShiftAllRightInt16x32 + OpShiftAllRightInt32x4 + OpShiftAllRightInt32x8 + OpShiftAllRightInt32x16 + OpShiftAllRightInt64x2 + OpShiftAllRightInt64x4 + OpShiftAllRightInt64x8 + OpShiftAllRightUint8x16 + OpShiftAllRightUint16x8 + OpShiftAllRightUint16x16 + OpShiftAllRightUint16x32 + OpShiftAllRightUint32x4 + OpShiftAllRightUint32x8 + OpShiftAllRightUint32x16 + OpShiftAllRightUint64x2 + OpShiftAllRightUint64x4 + OpShiftAllRightUint64x8 + OpShiftInt8x16 + OpShiftInt16x8 + OpShiftInt32x4 + OpShiftInt64x2 + OpShiftLeftConcatMod16Int16x8 + OpShiftLeftConcatMod16Int16x16 + OpShiftLeftConcatMod16Int16x32 + OpShiftLeftConcatMod16Uint16x8 + OpShiftLeftConcatMod16Uint16x16 + OpShiftLeftConcatMod16Uint16x32 + OpShiftLeftConcatMod32Int32x4 + OpShiftLeftConcatMod32Int32x8 + OpShiftLeftConcatMod32Int32x16 + OpShiftLeftConcatMod32Uint32x4 + OpShiftLeftConcatMod32Uint32x8 + OpShiftLeftConcatMod32Uint32x16 + OpShiftLeftConcatMod64Int64x2 + OpShiftLeftConcatMod64Int64x4 + OpShiftLeftConcatMod64Int64x8 + OpShiftLeftConcatMod64Uint64x2 + OpShiftLeftConcatMod64Uint64x4 + OpShiftLeftConcatMod64Uint64x8 + OpShiftLeftInt16x8 + OpShiftLeftInt16x16 + OpShiftLeftInt16x32 + OpShiftLeftInt32x4 + OpShiftLeftInt32x8 + OpShiftLeftInt32x16 + OpShiftLeftInt64x2 + OpShiftLeftInt64x4 + OpShiftLeftInt64x8 + OpShiftLeftUint16x8 + OpShiftLeftUint16x16 + OpShiftLeftUint16x32 + OpShiftLeftUint32x4 + OpShiftLeftUint32x8 + OpShiftLeftUint32x16 + OpShiftLeftUint64x2 + OpShiftLeftUint64x4 + OpShiftLeftUint64x8 + OpShiftRightConcatMod16Int16x8 + OpShiftRightConcatMod16Int16x16 + OpShiftRightConcatMod16Int16x32 + OpShiftRightConcatMod16Uint16x8 + OpShiftRightConcatMod16Uint16x16 + OpShiftRightConcatMod16Uint16x32 + OpShiftRightConcatMod32Int32x4 + OpShiftRightConcatMod32Int32x8 + OpShiftRightConcatMod32Int32x16 + OpShiftRightConcatMod32Uint32x4 + OpShiftRightConcatMod32Uint32x8 + OpShiftRightConcatMod32Uint32x16 + OpShiftRightConcatMod64Int64x2 + OpShiftRightConcatMod64Int64x4 + OpShiftRightConcatMod64Int64x8 + OpShiftRightConcatMod64Uint64x2 + OpShiftRightConcatMod64Uint64x4 + OpShiftRightConcatMod64Uint64x8 + OpShiftRightInt16x8 + OpShiftRightInt16x16 + OpShiftRightInt16x32 + OpShiftRightInt32x4 + OpShiftRightInt32x8 + OpShiftRightInt32x16 + OpShiftRightInt64x2 + OpShiftRightInt64x4 + OpShiftRightInt64x8 + OpShiftRightUint16x8 + OpShiftRightUint16x16 + OpShiftRightUint16x32 + OpShiftRightUint32x4 + OpShiftRightUint32x8 + OpShiftRightUint32x16 + OpShiftRightUint64x2 + OpShiftRightUint64x4 + OpShiftRightUint64x8 + OpShiftSaturatedInt8x16 + OpShiftSaturatedInt16x8 + OpShiftSaturatedInt32x4 + OpShiftSaturatedInt64x2 + OpShiftSaturatedUint8x16 + OpShiftSaturatedUint16x8 + OpShiftSaturatedUint32x4 + OpShiftSaturatedUint64x2 + OpShiftUint8x16 + OpShiftUint16x8 + OpShiftUint32x4 + OpShiftUint64x2 + OpSqrtFloat32x4 + OpSqrtFloat32x8 + OpSqrtFloat32x16 + OpSqrtFloat64x2 + OpSqrtFloat64x4 + OpSqrtFloat64x8 + OpSubFloat32x4 + OpSubFloat32x8 + OpSubFloat32x16 + OpSubFloat64x2 + OpSubFloat64x4 + OpSubFloat64x8 + OpSubInt8x16 + OpSubInt8x32 + OpSubInt8x64 + OpSubInt16x8 + OpSubInt16x16 + OpSubInt16x32 + OpSubInt32x4 + OpSubInt32x8 + OpSubInt32x16 + OpSubInt64x2 + OpSubInt64x4 + OpSubInt64x8 + OpSubSaturatedInt8x16 + OpSubSaturatedInt8x32 + OpSubSaturatedInt8x64 + OpSubSaturatedInt16x8 + OpSubSaturatedInt16x16 + OpSubSaturatedInt16x32 + OpSubSaturatedInt32x4 + OpSubSaturatedInt64x2 + OpSubSaturatedUint8x16 + OpSubSaturatedUint8x32 + OpSubSaturatedUint8x64 + OpSubSaturatedUint16x8 + OpSubSaturatedUint16x16 + OpSubSaturatedUint16x32 + OpSubSaturatedUint32x4 + OpSubSaturatedUint64x2 + OpSubUint8x16 + OpSubUint8x32 + OpSubUint8x64 + OpSubUint16x8 + OpSubUint16x16 + OpSubUint16x32 + OpSubUint32x4 + OpSubUint32x8 + OpSubUint32x16 + OpSubUint64x2 + OpSubUint64x4 + OpSubUint64x8 + OpSumOf8AbsDiffUint8x16 + OpSumOf8AbsDiffUint8x32 + OpSumOf8AbsDiffUint8x64 + OpTruncFloat32x4 + OpTruncFloat32x8 + OpTruncFloat64x2 + OpTruncFloat64x4 + OpTruncToInt8Int16x8 + OpTruncToInt8Int16x16 + OpTruncToInt8Int16x32 + OpTruncToInt8Int32x4 + OpTruncToInt8Int32x8 + OpTruncToInt8Int32x16 + OpTruncToInt8Int64x2 + OpTruncToInt8Int64x4 + OpTruncToInt8Int64x8 + OpTruncToInt16Int32x4 + OpTruncToInt16Int32x8 + OpTruncToInt16Int32x16 + OpTruncToInt16Int64x2 + OpTruncToInt16Int64x4 + OpTruncToInt16Int64x8 + OpTruncToInt32Int64x2 + OpTruncToInt32Int64x4 + OpTruncToInt32Int64x8 + OpTruncToUint8Uint16x8 + OpTruncToUint8Uint16x16 + OpTruncToUint8Uint16x32 + OpTruncToUint8Uint32x4 + OpTruncToUint8Uint32x8 + OpTruncToUint8Uint32x16 + OpTruncToUint8Uint64x2 + OpTruncToUint8Uint64x4 + OpTruncToUint8Uint64x8 + OpTruncToUint16Uint32x4 + OpTruncToUint16Uint32x8 + OpTruncToUint16Uint32x16 + OpTruncToUint16Uint64x2 + OpTruncToUint16Uint64x4 + OpTruncToUint16Uint64x8 + OpTruncToUint32Uint64x2 + OpTruncToUint32Uint64x4 + OpTruncToUint32Uint64x8 + OpXorInt8x16 + OpXorInt8x32 + OpXorInt8x64 + OpXorInt16x8 + OpXorInt16x16 + OpXorInt16x32 + OpXorInt32x4 + OpXorInt32x8 + OpXorInt32x16 + OpXorInt64x2 + OpXorInt64x4 + OpXorInt64x8 + OpXorUint8x16 + OpXorUint8x32 + OpXorUint8x64 + OpXorUint16x8 + OpXorUint16x16 + OpXorUint16x32 + OpXorUint32x4 + OpXorUint32x8 + OpXorUint32x16 + OpXorUint64x2 + OpXorUint64x4 + OpXorUint64x8 + OpbitSelectInt8x16 + OpbitSelectNotInt8x16 + OpblendInt8x16 + OpblendInt8x32 + OpblendMaskedInt8x64 + OpblendMaskedInt16x32 + OpblendMaskedInt32x16 + OpblendMaskedInt64x8 + Opbroadcast1To2Float64x2 + Opbroadcast1To2Int64x2 + Opbroadcast1To2MaskedFloat64x2 + Opbroadcast1To2MaskedInt64x2 + Opbroadcast1To2MaskedUint64x2 + Opbroadcast1To2Uint64x2 + Opbroadcast1To4Float32x4 + Opbroadcast1To4Float64x2 + Opbroadcast1To4Int32x4 + Opbroadcast1To4Int64x2 + Opbroadcast1To4MaskedFloat32x4 + Opbroadcast1To4MaskedFloat64x2 + Opbroadcast1To4MaskedInt32x4 + Opbroadcast1To4MaskedInt64x2 + Opbroadcast1To4MaskedUint32x4 + Opbroadcast1To4MaskedUint64x2 + Opbroadcast1To4Uint32x4 + Opbroadcast1To4Uint64x2 + Opbroadcast1To8Float32x4 + Opbroadcast1To8Float64x2 + Opbroadcast1To8Int16x8 + Opbroadcast1To8Int32x4 + Opbroadcast1To8Int64x2 + Opbroadcast1To8MaskedFloat32x4 + Opbroadcast1To8MaskedFloat64x2 + Opbroadcast1To8MaskedInt16x8 + Opbroadcast1To8MaskedInt32x4 + Opbroadcast1To8MaskedInt64x2 + Opbroadcast1To8MaskedUint16x8 + Opbroadcast1To8MaskedUint32x4 + Opbroadcast1To8MaskedUint64x2 + Opbroadcast1To8Uint16x8 + Opbroadcast1To8Uint32x4 + Opbroadcast1To8Uint64x2 + Opbroadcast1To16Float32x4 + Opbroadcast1To16Int8x16 + Opbroadcast1To16Int16x8 + Opbroadcast1To16Int32x4 + Opbroadcast1To16MaskedFloat32x4 + Opbroadcast1To16MaskedInt8x16 + Opbroadcast1To16MaskedInt16x8 + Opbroadcast1To16MaskedInt32x4 + Opbroadcast1To16MaskedUint8x16 + Opbroadcast1To16MaskedUint16x8 + Opbroadcast1To16MaskedUint32x4 + Opbroadcast1To16Uint8x16 + Opbroadcast1To16Uint16x8 + Opbroadcast1To16Uint32x4 + Opbroadcast1To32Int8x16 + Opbroadcast1To32Int16x8 + Opbroadcast1To32MaskedInt8x16 + Opbroadcast1To32MaskedInt16x8 + Opbroadcast1To32MaskedUint8x16 + Opbroadcast1To32MaskedUint16x8 + Opbroadcast1To32Uint8x16 + Opbroadcast1To32Uint16x8 + Opbroadcast1To64Int8x16 + Opbroadcast1To64MaskedInt8x16 + Opbroadcast1To64MaskedUint8x16 + Opbroadcast1To64Uint8x16 + OpcarrylessMultiplyWidenLoUint64x2 + OpreduceMaxFloat32x4 + OpreduceMaxInt8x16 + OpreduceMaxInt16x8 + OpreduceMaxInt32x4 + OpreduceMaxUint8x16 + OpreduceMaxUint16x8 + OpreduceMaxUint32x4 + OpreduceMinFloat32x4 + OpreduceMinInt8x16 + OpreduceMinInt16x8 + OpreduceMinInt32x4 + OpreduceMinUint8x16 + OpreduceMinUint16x8 + OpreduceMinUint32x4 + OpreduceSumInt8x16 + OpreduceSumInt16x8 + OpreduceSumInt32x4 + OpreduceSumUint8x16 + OpreduceSumUint16x8 + OpreduceSumUint32x4 + OpAESRoundKeyGenAssistUint32x4 + OpCeilScaledFloat32x4 + OpCeilScaledFloat32x8 + OpCeilScaledFloat32x16 + OpCeilScaledFloat64x2 + OpCeilScaledFloat64x4 + OpCeilScaledFloat64x8 + OpCeilScaledResidueFloat32x4 + OpCeilScaledResidueFloat32x8 + OpCeilScaledResidueFloat32x16 + OpCeilScaledResidueFloat64x2 + OpCeilScaledResidueFloat64x4 + OpCeilScaledResidueFloat64x8 + OpConcatPermute128ScalarsFloat32x8 + OpConcatPermute128ScalarsFloat64x4 + OpConcatPermute128ScalarsInt8x32 + OpConcatPermute128ScalarsInt16x16 + OpConcatPermute128ScalarsInt32x8 + OpConcatPermute128ScalarsInt64x4 + OpConcatPermute128ScalarsUint8x32 + OpConcatPermute128ScalarsUint16x16 + OpConcatPermute128ScalarsUint32x8 + OpConcatPermute128ScalarsUint64x4 + OpConcatShiftBytesRightGroupedUint8x32 + OpConcatShiftBytesRightGroupedUint8x64 + OpConcatShiftBytesRightUint8x16 + OpFloorScaledFloat32x4 + OpFloorScaledFloat32x8 + OpFloorScaledFloat32x16 + OpFloorScaledFloat64x2 + OpFloorScaledFloat64x4 + OpFloorScaledFloat64x8 + OpFloorScaledResidueFloat32x4 + OpFloorScaledResidueFloat32x8 + OpFloorScaledResidueFloat32x16 + OpFloorScaledResidueFloat64x2 + OpFloorScaledResidueFloat64x4 + OpFloorScaledResidueFloat64x8 + OpGaloisFieldAffineTransformInverseUint8x16 + OpGaloisFieldAffineTransformInverseUint8x32 + OpGaloisFieldAffineTransformInverseUint8x64 + OpGaloisFieldAffineTransformUint8x16 + OpGaloisFieldAffineTransformUint8x32 + OpGaloisFieldAffineTransformUint8x64 + OpGetElemFloat32x4 + OpGetElemFloat64x2 + OpGetElemInt8x16 + OpGetElemInt16x8 + OpGetElemInt32x4 + OpGetElemInt64x2 + OpGetElemUint8x16 + OpGetElemUint16x8 + OpGetElemUint32x4 + OpGetElemUint64x2 + OpRoundScaledFloat32x4 + OpRoundScaledFloat32x8 + OpRoundScaledFloat32x16 + OpRoundScaledFloat64x2 + OpRoundScaledFloat64x4 + OpRoundScaledFloat64x8 + OpRoundScaledResidueFloat32x4 + OpRoundScaledResidueFloat32x8 + OpRoundScaledResidueFloat32x16 + OpRoundScaledResidueFloat64x2 + OpRoundScaledResidueFloat64x4 + OpRoundScaledResidueFloat64x8 + OpSHA1FourRoundsUint32x4 + OpSetElemFloat32x4 + OpSetElemFloat64x2 + OpSetElemInt8x16 + OpSetElemInt16x8 + OpSetElemInt32x4 + OpSetElemInt64x2 + OpSetElemUint8x16 + OpSetElemUint16x8 + OpSetElemUint32x4 + OpSetElemUint64x2 + OpShiftAllLeftConcatMod16Int16x8 + OpShiftAllLeftConcatMod16Int16x16 + OpShiftAllLeftConcatMod16Int16x32 + OpShiftAllLeftConcatMod16Uint16x8 + OpShiftAllLeftConcatMod16Uint16x16 + OpShiftAllLeftConcatMod16Uint16x32 + OpShiftAllLeftConcatMod32Int32x4 + OpShiftAllLeftConcatMod32Int32x8 + OpShiftAllLeftConcatMod32Int32x16 + OpShiftAllLeftConcatMod32Uint32x4 + OpShiftAllLeftConcatMod32Uint32x8 + OpShiftAllLeftConcatMod32Uint32x16 + OpShiftAllLeftConcatMod64Int64x2 + OpShiftAllLeftConcatMod64Int64x4 + OpShiftAllLeftConcatMod64Int64x8 + OpShiftAllLeftConcatMod64Uint64x2 + OpShiftAllLeftConcatMod64Uint64x4 + OpShiftAllLeftConcatMod64Uint64x8 + OpShiftAllRightConcatMod16Int16x8 + OpShiftAllRightConcatMod16Int16x16 + OpShiftAllRightConcatMod16Int16x32 + OpShiftAllRightConcatMod16Uint16x8 + OpShiftAllRightConcatMod16Uint16x16 + OpShiftAllRightConcatMod16Uint16x32 + OpShiftAllRightConcatMod32Int32x4 + OpShiftAllRightConcatMod32Int32x8 + OpShiftAllRightConcatMod32Int32x16 + OpShiftAllRightConcatMod32Uint32x4 + OpShiftAllRightConcatMod32Uint32x8 + OpShiftAllRightConcatMod32Uint32x16 + OpShiftAllRightConcatMod64Int64x2 + OpShiftAllRightConcatMod64Int64x4 + OpShiftAllRightConcatMod64Int64x8 + OpShiftAllRightConcatMod64Uint64x2 + OpShiftAllRightConcatMod64Uint64x4 + OpShiftAllRightConcatMod64Uint64x8 + OpTruncScaledFloat32x4 + OpTruncScaledFloat32x8 + OpTruncScaledFloat32x16 + OpTruncScaledFloat64x2 + OpTruncScaledFloat64x4 + OpTruncScaledFloat64x8 + OpTruncScaledResidueFloat32x4 + OpTruncScaledResidueFloat32x8 + OpTruncScaledResidueFloat32x16 + OpTruncScaledResidueFloat64x2 + OpTruncScaledResidueFloat64x4 + OpTruncScaledResidueFloat64x8 + OpcarrylessMultiplyUint64x2 + OpcarrylessMultiplyUint64x4 + OpcarrylessMultiplyUint64x8 + OpconcatSelectedConstantFloat32x4 + OpconcatSelectedConstantFloat64x2 + OpconcatSelectedConstantGroupedFloat32x8 + OpconcatSelectedConstantGroupedFloat32x16 + OpconcatSelectedConstantGroupedFloat64x4 + OpconcatSelectedConstantGroupedFloat64x8 + OpconcatSelectedConstantGroupedInt32x8 + OpconcatSelectedConstantGroupedInt32x16 + OpconcatSelectedConstantGroupedInt64x4 + OpconcatSelectedConstantGroupedInt64x8 + OpconcatSelectedConstantGroupedUint32x8 + OpconcatSelectedConstantGroupedUint32x16 + OpconcatSelectedConstantGroupedUint64x4 + OpconcatSelectedConstantGroupedUint64x8 + OpconcatSelectedConstantInt32x4 + OpconcatSelectedConstantInt64x2 + OpconcatSelectedConstantUint32x4 + OpconcatSelectedConstantUint64x2 + OppermuteScalarsGroupedInt32x8 + OppermuteScalarsGroupedInt32x16 + OppermuteScalarsGroupedUint32x8 + OppermuteScalarsGroupedUint32x16 + OppermuteScalarsHiGroupedInt16x16 + OppermuteScalarsHiGroupedInt16x32 + OppermuteScalarsHiGroupedUint16x16 + OppermuteScalarsHiGroupedUint16x32 + OppermuteScalarsHiInt16x8 + OppermuteScalarsHiUint16x8 + OppermuteScalarsInt32x4 + OppermuteScalarsLoGroupedInt16x16 + OppermuteScalarsLoGroupedInt16x32 + OppermuteScalarsLoGroupedUint16x16 + OppermuteScalarsLoGroupedUint16x32 + OppermuteScalarsLoInt16x8 + OppermuteScalarsLoUint16x8 + OppermuteScalarsUint32x4 + OpternInt32x4 + OpternInt32x8 + OpternInt32x16 + OpternInt64x2 + OpternInt64x4 + OpternInt64x8 + OpternUint32x4 + OpternUint32x8 + OpternUint32x16 + OpternUint64x2 + OpternUint64x4 + OpternUint64x8 ) var opcodeTable = [...]opInfo{ @@ -3418,14 +8780,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3434,14 +8797,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3449,14 +8813,15 @@ var opcodeTable = [...]opInfo{ name: "SUBSS", argLen: 2, resultInArg0: true, + earlyOk: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3464,14 +8829,15 @@ var opcodeTable = [...]opInfo{ name: "SUBSD", argLen: 2, resultInArg0: true, + earlyOk: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3480,14 +8846,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3496,14 +8863,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3511,14 +8879,15 @@ var opcodeTable = [...]opInfo{ name: "DIVSS", argLen: 2, resultInArg0: true, + earlyOk: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3526,14 +8895,15 @@ var opcodeTable = [...]opInfo{ name: "DIVSD", argLen: 2, resultInArg0: true, + earlyOk: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3542,14 +8912,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3558,14 +8929,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3574,10 +8946,11 @@ var opcodeTable = [...]opInfo{ auxType: auxFloat32, argLen: 0, rematerializeable: true, + earlyOk: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3586,74 +8959,79 @@ var opcodeTable = [...]opInfo{ auxType: auxFloat64, argLen: 0, rematerializeable: true, + earlyOk: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "MOVSSloadidx1", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVSS, + name: "MOVSSloadidx1", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "MOVSSloadidx4", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVSS, + name: "MOVSSloadidx4", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "MOVSDloadidx1", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVSD, + name: "MOVSDloadidx1", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "MOVSDloadidx8", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVSD, + name: "MOVSDloadidx8", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3662,12 +9040,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -3676,68 +9055,73 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVSSstoreidx1", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVSS, + name: "MOVSSstoreidx1", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVSSstoreidx4", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVSS, + name: "MOVSSstoreidx4", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVSDstoreidx1", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVSD, + name: "MOVSDstoreidx1", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVSDstoreidx8", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVSD, + name: "MOVSDstoreidx8", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -3747,15 +9131,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3765,15 +9150,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3783,15 +9169,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3801,15 +9188,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3819,15 +9207,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3837,15 +9226,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3855,15 +9245,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3873,15 +9264,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -3890,14 +9282,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, clobberFlags: true, + earlyOk: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {1, 239}, // AX CX DX BX BP SI DI - {0, 255}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -3906,13 +9299,14 @@ var opcodeTable = [...]opInfo{ auxType: auxInt32, argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -3921,15 +9315,16 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {1, 0}, - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -3941,11 +9336,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {1, 0}, - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -3958,11 +9353,29 @@ var opcodeTable = [...]opInfo{ asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + }, + }, + }, + { + name: "ADCLcarry", + argLen: 3, + commutative: true, + resultInArg0: true, + clobberFlags: true, + asm: x86.AADCL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -3975,10 +9388,10 @@ var opcodeTable = [...]opInfo{ asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -3987,14 +9400,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4004,13 +9418,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4021,12 +9436,12 @@ var opcodeTable = [...]opInfo{ asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {1, 0}, - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4038,11 +9453,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {1, 0}, - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4054,11 +9469,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4071,10 +9486,10 @@ var opcodeTable = [...]opInfo{ asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4084,14 +9499,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4100,13 +9516,14 @@ var opcodeTable = [...]opInfo{ auxType: auxInt32, argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.AIMUL3L, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4115,16 +9532,17 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, clobberFlags: true, + earlyOk: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, - clobbers: 4, // DX + clobbers: regMask{v1: 4, v2: 0}, // DX outputs: []outputInfo{ - {1, 0}, - {0, 1}, // AX + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -4133,15 +9551,16 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, clobberFlags: true, + earlyOk: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -4150,15 +9569,16 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, clobberFlags: true, + earlyOk: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -4167,15 +9587,16 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, clobberFlags: true, + earlyOk: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ - {0, 4}, // DX - {1, 1}, // AX + {0, regMask{v1: 4, v2: 0}}, // DX + {1, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -4185,13 +9606,14 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4203,12 +9625,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 251}, // AX CX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI }, - clobbers: 4, // DX + clobbers: regMask{v1: 4, v2: 0}, // DX outputs: []outputInfo{ - {0, 1}, // AX + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -4220,12 +9642,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 251}, // AX CX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI }, - clobbers: 4, // DX + clobbers: regMask{v1: 4, v2: 0}, // DX outputs: []outputInfo{ - {0, 1}, // AX + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -4236,12 +9658,12 @@ var opcodeTable = [...]opInfo{ asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 251}, // AX CX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI }, - clobbers: 4, // DX + clobbers: regMask{v1: 4, v2: 0}, // DX outputs: []outputInfo{ - {0, 1}, // AX + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -4252,12 +9674,12 @@ var opcodeTable = [...]opInfo{ asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 251}, // AX CX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI }, - clobbers: 4, // DX + clobbers: regMask{v1: 4, v2: 0}, // DX outputs: []outputInfo{ - {0, 1}, // AX + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -4269,12 +9691,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 251}, // AX CX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -4286,12 +9708,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 251}, // AX CX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -4302,12 +9724,12 @@ var opcodeTable = [...]opInfo{ asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 251}, // AX CX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -4318,12 +9740,12 @@ var opcodeTable = [...]opInfo{ asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 251}, // AX CX BX SP BP SI DI + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -4333,14 +9755,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4350,13 +9773,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4366,14 +9790,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4383,13 +9808,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4399,14 +9825,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4416,13 +9843,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4432,8 +9860,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI - {1, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4443,8 +9871,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI - {1, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4454,8 +9882,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI - {1, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4466,7 +9894,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4477,7 +9905,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4488,7 +9916,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4497,12 +9925,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -4511,12 +9940,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -4525,12 +9955,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -4539,11 +9970,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -4552,11 +9984,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -4565,33 +9998,36 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "UCOMISS", - argLen: 2, - asm: x86.AUCOMISS, + name: "UCOMISS", + argLen: 2, + earlyOk: true, + asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "UCOMISD", - argLen: 2, - asm: x86.AUCOMISD, + name: "UCOMISD", + argLen: 2, + earlyOk: true, + asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -4602,8 +10038,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI - {1, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4614,8 +10050,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI - {1, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4626,8 +10062,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI - {1, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4638,7 +10074,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4649,7 +10085,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4660,7 +10096,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -4669,14 +10105,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4686,13 +10123,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4701,14 +10139,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4717,14 +10156,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4733,14 +10173,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4750,13 +10191,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4766,13 +10208,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4782,13 +10225,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4797,14 +10241,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4813,14 +10258,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4829,14 +10275,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4846,13 +10293,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4862,13 +10310,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4878,13 +10327,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4893,14 +10343,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4909,14 +10360,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4925,14 +10377,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 239}, // AX CX DX BX BP SI DI + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4942,13 +10395,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4958,13 +10412,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4974,13 +10429,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -4991,15 +10447,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5010,15 +10467,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5029,15 +10487,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5048,15 +10507,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5067,15 +10527,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5086,15 +10547,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5104,16 +10566,17 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5123,16 +10586,17 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5142,16 +10606,17 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5161,16 +10626,17 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5180,16 +10646,17 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5199,16 +10666,17 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {1, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5217,13 +10685,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5231,13 +10700,14 @@ var opcodeTable = [...]opInfo{ name: "NOTL", argLen: 1, resultInArg0: true, + earlyOk: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5245,13 +10715,14 @@ var opcodeTable = [...]opInfo{ name: "BSFL", argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5259,13 +10730,14 @@ var opcodeTable = [...]opInfo{ name: "BSFW", argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.ABSFW, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5273,12 +10745,13 @@ var opcodeTable = [...]opInfo{ name: "LoweredCtz32", argLen: 1, clobberFlags: true, + earlyOk: true, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5287,13 +10760,14 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultNotInArgs: true, clobberFlags: true, + earlyOk: true, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5301,13 +10775,14 @@ var opcodeTable = [...]opInfo{ name: "BSRL", argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5315,13 +10790,14 @@ var opcodeTable = [...]opInfo{ name: "BSRW", argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.ABSRW, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5329,159 +10805,174 @@ var opcodeTable = [...]opInfo{ name: "BSWAPL", argLen: 1, resultInArg0: true, + earlyOk: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SQRTSD", - argLen: 1, - asm: x86.ASQRTSD, + name: "SQRTSD", + argLen: 1, + earlyOk: true, + asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "SQRTSS", - argLen: 1, - asm: x86.ASQRTSS, + name: "SQRTSS", + argLen: 1, + earlyOk: true, + asm: x86.ASQRTSS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "SBBLcarrymask", - argLen: 1, - asm: x86.ASBBL, + name: "SBBLcarrymask", + argLen: 1, + earlyOk: true, + asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETEQ", - argLen: 1, - asm: x86.ASETEQ, + name: "SETEQ", + argLen: 1, + earlyOk: true, + asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETNE", - argLen: 1, - asm: x86.ASETNE, + name: "SETNE", + argLen: 1, + earlyOk: true, + asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETL", - argLen: 1, - asm: x86.ASETLT, + name: "SETL", + argLen: 1, + earlyOk: true, + asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETLE", - argLen: 1, - asm: x86.ASETLE, + name: "SETLE", + argLen: 1, + earlyOk: true, + asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETG", - argLen: 1, - asm: x86.ASETGT, + name: "SETG", + argLen: 1, + earlyOk: true, + asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETGE", - argLen: 1, - asm: x86.ASETGE, + name: "SETGE", + argLen: 1, + earlyOk: true, + asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETB", - argLen: 1, - asm: x86.ASETCS, + name: "SETB", + argLen: 1, + earlyOk: true, + asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETBE", - argLen: 1, - asm: x86.ASETLS, + name: "SETBE", + argLen: 1, + earlyOk: true, + asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETA", - argLen: 1, - asm: x86.ASETHI, + name: "SETA", + argLen: 1, + earlyOk: true, + asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETAE", - argLen: 1, - asm: x86.ASETCC, + name: "SETAE", + argLen: 1, + earlyOk: true, + asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETO", - argLen: 1, - asm: x86.ASETOS, + name: "SETO", + argLen: 1, + earlyOk: true, + asm: x86.ASETOS, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5489,11 +10980,12 @@ var opcodeTable = [...]opInfo{ name: "SETEQF", argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.ASETEQ, reg: regInfo{ - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 238}, // CX DX BX BP SI DI + {0, regMask{v1: 238, v2: 0}}, // CX DX BX BP SI DI }, }, }, @@ -5501,103 +10993,112 @@ var opcodeTable = [...]opInfo{ name: "SETNEF", argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.ASETNE, reg: regInfo{ - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 238}, // CX DX BX BP SI DI + {0, regMask{v1: 238, v2: 0}}, // CX DX BX BP SI DI }, }, }, { - name: "SETORD", - argLen: 1, - asm: x86.ASETPC, + name: "SETORD", + argLen: 1, + earlyOk: true, + asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETNAN", - argLen: 1, - asm: x86.ASETPS, + name: "SETNAN", + argLen: 1, + earlyOk: true, + asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETGF", - argLen: 1, - asm: x86.ASETHI, + name: "SETGF", + argLen: 1, + earlyOk: true, + asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "SETGEF", - argLen: 1, - asm: x86.ASETCC, + name: "SETGEF", + argLen: 1, + earlyOk: true, + asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "MOVBLSX", - argLen: 1, - asm: x86.AMOVBLSX, + name: "MOVBLSX", + argLen: 1, + earlyOk: true, + asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "MOVBLZX", - argLen: 1, - asm: x86.AMOVBLZX, + name: "MOVBLZX", + argLen: 1, + earlyOk: true, + asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "MOVWLSX", - argLen: 1, - asm: x86.AMOVWLSX, + name: "MOVWLSX", + argLen: 1, + earlyOk: true, + asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "MOVWLZX", - argLen: 1, - asm: x86.AMOVWLZX, + name: "MOVWLZX", + argLen: 1, + earlyOk: true, + asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5606,88 +11107,95 @@ var opcodeTable = [...]opInfo{ auxType: auxInt32, argLen: 0, rematerializeable: true, + earlyOk: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "CVTTSD2SL", - argLen: 1, - asm: x86.ACVTTSD2SL, + name: "CVTTSD2SL", + argLen: 1, + earlyOk: true, + asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "CVTTSS2SL", - argLen: 1, - asm: x86.ACVTTSS2SL, + name: "CVTTSS2SL", + argLen: 1, + earlyOk: true, + asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "CVTSL2SS", - argLen: 1, - asm: x86.ACVTSL2SS, + name: "CVTSL2SS", + argLen: 1, + earlyOk: true, + asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "CVTSL2SD", - argLen: 1, - asm: x86.ACVTSL2SD, + name: "CVTSL2SD", + argLen: 1, + earlyOk: true, + asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "CVTSD2SS", - argLen: 1, - asm: x86.ACVTSD2SS, + name: "CVTSD2SS", + argLen: 1, + earlyOk: true, + asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "CVTSS2SD", - argLen: 1, - asm: x86.ACVTSS2SD, + name: "CVTSS2SD", + argLen: 1, + earlyOk: true, + asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -5696,14 +11204,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 - {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 + {1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -5712,13 +11221,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 1, rematerializeable: true, + earlyOk: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5727,14 +11237,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, commutative: true, + earlyOk: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5742,14 +11253,15 @@ var opcodeTable = [...]opInfo{ name: "LEAL2", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5757,14 +11269,15 @@ var opcodeTable = [...]opInfo{ name: "LEAL4", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5772,14 +11285,15 @@ var opcodeTable = [...]opInfo{ name: "LEAL8", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5788,14 +11302,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5804,14 +11319,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5820,14 +11336,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5836,14 +11353,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5852,14 +11370,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -5868,12 +11387,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -5882,12 +11402,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -5896,12 +11417,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -5911,12 +11433,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -5926,12 +11449,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -5941,12 +11465,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -5956,12 +11481,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -5971,12 +11497,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -5985,13 +11512,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6000,13 +11528,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6015,13 +11544,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6030,13 +11560,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6045,13 +11576,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6061,11 +11593,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6075,11 +11608,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6089,11 +11623,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6103,11 +11638,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6116,12 +11652,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6130,12 +11667,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6144,12 +11682,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6158,168 +11697,185 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVBloadidx1", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.AMOVBLZX, + name: "MOVBloadidx1", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "MOVWloadidx1", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.AMOVWLZX, + name: "MOVWloadidx1", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "MOVWloadidx2", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVWLZX, + name: "MOVWloadidx2", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "MOVLloadidx1", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.AMOVL, + name: "MOVLloadidx1", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "MOVLloadidx4", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVL, + name: "MOVLloadidx4", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "MOVBstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVB, + name: "MOVBstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVWstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVW, + name: "MOVWstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVWstoreidx2", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVW, + name: "MOVWstoreidx2", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVLstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVL, + name: "MOVLstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVLstoreidx4", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVL, + name: "MOVLstoreidx4", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {2, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {2, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6328,11 +11884,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6341,11 +11898,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6354,76 +11912,82 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVBstoreconstidx1", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymWrite, - asm: x86.AMOVB, + name: "MOVBstoreconstidx1", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVWstoreconstidx1", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymWrite, - asm: x86.AMOVW, + name: "MOVWstoreconstidx1", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVWstoreconstidx2", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymWrite, - asm: x86.AMOVW, + name: "MOVWstoreconstidx2", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVLstoreconstidx1", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymWrite, - asm: x86.AMOVL, + name: "MOVLstoreconstidx1", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, { - name: "MOVLstoreconstidx4", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymWrite, - asm: x86.AMOVL, + name: "MOVLstoreconstidx4", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {1, 255}, // AX CX DX BX SP BP SI DI - {0, 65791}, // AX CX DX BX SP BP SI DI SB + {1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB }, }, }, @@ -6432,25 +11996,27 @@ var opcodeTable = [...]opInfo{ auxType: auxInt64, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 128}, // DI - {1, 1}, // AX + {0, regMask{v1: 128, v2: 0}}, // DI + {1, regMask{v1: 1, v2: 0}}, // AX }, - clobbers: 130, // CX DI + clobbers: regMask{v1: 130, v2: 0}, // CX DI }, }, { name: "REPSTOSL", argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 128}, // DI - {1, 2}, // CX - {2, 1}, // AX + {0, regMask{v1: 128, v2: 0}}, // DI + {1, regMask{v1: 2, v2: 0}}, // CX + {2, regMask{v1: 1, v2: 0}}, // AX }, - clobbers: 130, // CX DI + clobbers: regMask{v1: 130, v2: 0}, // CX DI }, }, { @@ -6460,7 +12026,7 @@ var opcodeTable = [...]opInfo{ clobberFlags: true, call: true, reg: regInfo{ - clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 + clobbers: regMask{v1: 65519, v2: 0}, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { @@ -6471,7 +12037,21 @@ var opcodeTable = [...]opInfo{ call: true, tailCall: true, reg: regInfo{ - clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 + clobbers: regMask{v1: 65519, v2: 0}, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 + }, + }, + { + name: "CALLtailinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + }, + clobbers: regMask{v1: 65519, v2: 0}, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { @@ -6482,10 +12062,10 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {1, 4}, // DX - {0, 255}, // AX CX DX BX SP BP SI DI + {1, regMask{v1: 4, v2: 0}}, // DX + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, - clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 + clobbers: regMask{v1: 65519, v2: 0}, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { @@ -6496,9 +12076,9 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, - clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 + clobbers: regMask{v1: 65519, v2: 0}, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { @@ -6508,12 +12088,14 @@ var opcodeTable = [...]opInfo{ clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, reg: regInfo{ inputs: []inputInfo{ - {0, 128}, // DI - {1, 64}, // SI + {0, regMask{v1: 128, v2: 0}}, // DI + {1, regMask{v1: 64, v2: 0}}, // SI }, - clobbers: 194, // CX SI DI + clobbers: regMask{v1: 194, v2: 0}, // CX SI DI }, }, { @@ -6521,13 +12103,15 @@ var opcodeTable = [...]opInfo{ argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, reg: regInfo{ inputs: []inputInfo{ - {0, 128}, // DI - {1, 64}, // SI - {2, 2}, // CX + {0, regMask{v1: 128, v2: 0}}, // DI + {1, regMask{v1: 64, v2: 0}}, // SI + {2, regMask{v1: 2, v2: 0}}, // CX }, - clobbers: 194, // CX SI DI + clobbers: regMask{v1: 194, v2: 0}, // CX SI DI }, }, { @@ -6540,7 +12124,7 @@ var opcodeTable = [...]opInfo{ argLen: 1, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -6550,7 +12134,7 @@ var opcodeTable = [...]opInfo{ zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -6560,7 +12144,7 @@ var opcodeTable = [...]opInfo{ rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -6570,7 +12154,7 @@ var opcodeTable = [...]opInfo{ rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -6582,7 +12166,7 @@ var opcodeTable = [...]opInfo{ faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 255}, // AX CX DX BX SP BP SI DI + {0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI }, }, }, @@ -6592,9 +12176,9 @@ var opcodeTable = [...]opInfo{ argLen: 1, clobberFlags: true, reg: regInfo{ - clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7 + clobbers: regMask{v1: 65280, v2: 0}, // X0 X1 X2 X3 X4 X5 X6 X7 outputs: []outputInfo{ - {0, 128}, // DI + {0, regMask{v1: 128, v2: 0}}, // DI }, }, }, @@ -6605,8 +12189,8 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI - {1, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI + {1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -6617,7 +12201,7 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -6628,7 +12212,7 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -6646,9 +12230,9 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 15}, // AX CX DX BX - {1, 15}, // AX CX DX BX - {2, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 15, v2: 0}}, // AX CX DX BX + {1, regMask{v1: 15, v2: 0}}, // AX CX DX BX + {2, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -6659,8 +12243,8 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 15}, // AX CX DX BX - {1, 15}, // AX CX DX BX + {0, regMask{v1: 15, v2: 0}}, // AX CX DX BX + {1, regMask{v1: 15, v2: 0}}, // AX CX DX BX }, }, }, @@ -6693,9 +12277,10 @@ var opcodeTable = [...]opInfo{ name: "MOVSSconst1", auxType: auxFloat32, argLen: 0, + earlyOk: true, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, @@ -6703,35 +12288,38 @@ var opcodeTable = [...]opInfo{ name: "MOVSDconst1", auxType: auxFloat64, argLen: 0, + earlyOk: true, reg: regInfo{ outputs: []outputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, }, }, { - name: "MOVSSconst2", - argLen: 1, - asm: x86.AMOVSS, + name: "MOVSSconst2", + argLen: 1, + earlyOk: true, + asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { - name: "MOVSDconst2", - argLen: 1, - asm: x86.AMOVSD, + name: "MOVSDconst2", + argLen: 1, + earlyOk: true, + asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 239}, // AX CX DX BX BP SI DI + {0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ - {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 + {0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, @@ -6741,14 +12329,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6757,14 +12346,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6772,14 +12362,15 @@ var opcodeTable = [...]opInfo{ name: "SUBSS", argLen: 2, resultInArg0: true, + earlyOk: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6787,14 +12378,15 @@ var opcodeTable = [...]opInfo{ name: "SUBSD", argLen: 2, resultInArg0: true, + earlyOk: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6803,14 +12395,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6819,14 +12412,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6834,14 +12428,15 @@ var opcodeTable = [...]opInfo{ name: "DIVSS", argLen: 2, resultInArg0: true, + earlyOk: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6849,14 +12444,15 @@ var opcodeTable = [...]opInfo{ name: "DIVSD", argLen: 2, resultInArg0: true, + earlyOk: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6865,14 +12461,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6881,14 +12478,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6897,10 +12495,11 @@ var opcodeTable = [...]opInfo{ auxType: auxFloat32, argLen: 0, rematerializeable: true, + earlyOk: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6909,78 +12508,83 @@ var opcodeTable = [...]opInfo{ auxType: auxFloat64, argLen: 0, rematerializeable: true, + earlyOk: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVSSloadidx1", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVSS, - scale: 1, + name: "MOVSSloadidx1", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVSS, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVSSloadidx4", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVSS, - scale: 4, + name: "MOVSSloadidx4", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVSS, + scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVSDloadidx1", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVSD, - scale: 1, + name: "MOVSDloadidx1", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVSD, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVSDloadidx8", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVSD, - scale: 8, + name: "MOVSDloadidx8", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVSD, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -6989,12 +12593,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, @@ -7003,72 +12608,77 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { - name: "MOVSSstoreidx1", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVSS, - scale: 1, + name: "MOVSSstoreidx1", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVSS, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { - name: "MOVSSstoreidx4", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVSS, - scale: 4, + name: "MOVSSstoreidx4", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVSS, + scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { - name: "MOVSDstoreidx1", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVSD, - scale: 1, + name: "MOVSDstoreidx1", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVSD, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { - name: "MOVSDstoreidx8", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVSD, - scale: 8, + name: "MOVSDstoreidx8", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVSD, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, @@ -7078,15 +12688,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7096,15 +12707,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7114,15 +12726,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7132,15 +12745,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7150,15 +12764,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7168,15 +12783,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7186,15 +12802,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7204,15 +12821,16 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7221,17 +12839,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7240,17 +12859,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7259,17 +12879,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7278,17 +12899,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7297,17 +12919,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7316,17 +12939,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7335,17 +12959,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7354,17 +12979,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7373,17 +12999,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AMULSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7392,17 +13019,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AMULSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7411,17 +13039,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AMULSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7430,17 +13059,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AMULSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7449,17 +13079,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ADIVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7468,17 +13099,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ADIVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7487,17 +13119,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ADIVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7506,17 +13139,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, resultInArg0: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ADIVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -7525,14 +13159,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, clobberFlags: true, + earlyOk: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7541,14 +13176,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, clobberFlags: true, + earlyOk: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7557,13 +13193,14 @@ var opcodeTable = [...]opInfo{ auxType: auxInt32, argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7572,13 +13209,14 @@ var opcodeTable = [...]opInfo{ auxType: auxInt32, argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7588,11 +13226,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -7602,11 +13241,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -7615,14 +13255,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7631,14 +13272,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7648,13 +13290,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7664,13 +13307,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7680,14 +13324,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7697,14 +13342,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7713,13 +13359,14 @@ var opcodeTable = [...]opInfo{ auxType: auxInt32, argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.AIMUL3Q, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7728,13 +13375,14 @@ var opcodeTable = [...]opInfo{ auxType: auxInt32, argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.AIMUL3L, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7746,13 +13394,13 @@ var opcodeTable = [...]opInfo{ asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 4, // DX + clobbers: regMask{v1: 4, v2: 0}, // DX outputs: []outputInfo{ - {1, 0}, - {0, 1}, // AX + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -7764,13 +13412,13 @@ var opcodeTable = [...]opInfo{ asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 4, // DX + clobbers: regMask{v1: 4, v2: 0}, // DX outputs: []outputInfo{ - {1, 0}, - {0, 1}, // AX + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -7778,15 +13426,16 @@ var opcodeTable = [...]opInfo{ name: "HMULQ", argLen: 2, clobberFlags: true, + earlyOk: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -7794,15 +13443,16 @@ var opcodeTable = [...]opInfo{ name: "HMULL", argLen: 2, clobberFlags: true, + earlyOk: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -7810,15 +13460,16 @@ var opcodeTable = [...]opInfo{ name: "HMULQU", argLen: 2, clobberFlags: true, + earlyOk: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -7826,15 +13477,16 @@ var opcodeTable = [...]opInfo{ name: "HMULLU", argLen: 2, clobberFlags: true, + earlyOk: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -7844,13 +13496,14 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7862,12 +13515,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AIDIVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 1}, // AX - {1, 4}, // DX + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -7879,12 +13532,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 1}, // AX - {1, 4}, // DX + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -7896,12 +13549,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 1}, // AX - {1, 4}, // DX + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -7912,12 +13565,12 @@ var opcodeTable = [...]opInfo{ asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 1}, // AX - {1, 4}, // DX + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -7928,12 +13581,12 @@ var opcodeTable = [...]opInfo{ asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 1}, // AX - {1, 4}, // DX + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -7944,12 +13597,12 @@ var opcodeTable = [...]opInfo{ asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 1}, // AX - {1, 4}, // DX + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -7960,11 +13613,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7976,11 +13629,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -7992,11 +13645,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8008,12 +13661,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8025,12 +13678,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AADCQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8042,11 +13695,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8058,11 +13711,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AADCQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8073,12 +13726,12 @@ var opcodeTable = [...]opInfo{ asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8089,12 +13742,12 @@ var opcodeTable = [...]opInfo{ asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8106,11 +13759,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8122,11 +13775,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8135,15 +13788,16 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, clobberFlags: true, + earlyOk: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // AX - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 4}, // DX - {1, 1}, // AX + {0, regMask{v1: 4, v2: 0}}, // DX + {1, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -8154,13 +13808,13 @@ var opcodeTable = [...]opInfo{ asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // DX - {1, 1}, // AX - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 4, v2: 0}}, // DX + {1, regMask{v1: 1, v2: 0}}, // AX + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 1}, // AX - {1, 4}, // DX + {0, regMask{v1: 1, v2: 0}}, // AX + {1, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -8170,14 +13824,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8187,14 +13842,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8204,13 +13860,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8220,13 +13877,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8236,11 +13894,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8250,11 +13909,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8264,14 +13924,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8281,14 +13942,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8298,13 +13960,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8314,13 +13977,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8330,11 +13994,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8344,11 +14009,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8358,14 +14024,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8375,14 +14042,15 @@ var opcodeTable = [...]opInfo{ commutative: true, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8392,13 +14060,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8408,13 +14077,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8424,11 +14094,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8438,11 +14109,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8452,8 +14124,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8463,8 +14135,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8474,8 +14146,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8485,8 +14157,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8497,7 +14169,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8508,7 +14180,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8519,7 +14191,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8530,7 +14202,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8539,12 +14211,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8553,12 +14226,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8567,12 +14241,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8581,12 +14256,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8595,11 +14271,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8608,11 +14285,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8621,11 +14299,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8634,222 +14313,245 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPQloadidx8", - auxType: auxSymOff, - argLen: 4, - symEffect: SymRead, - asm: x86.ACMPQ, - scale: 8, + name: "CMPQloadidx8", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.ACMPQ, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPQloadidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymRead, - asm: x86.ACMPQ, - scale: 1, + name: "CMPQloadidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.ACMPQ, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPLloadidx4", - auxType: auxSymOff, - argLen: 4, - symEffect: SymRead, - asm: x86.ACMPL, - scale: 4, + name: "CMPLloadidx4", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.ACMPL, + scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPLloadidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymRead, - asm: x86.ACMPL, - scale: 1, + name: "CMPLloadidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.ACMPL, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPWloadidx2", - auxType: auxSymOff, - argLen: 4, - symEffect: SymRead, - asm: x86.ACMPW, - scale: 2, + name: "CMPWloadidx2", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.ACMPW, + scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPWloadidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymRead, - asm: x86.ACMPW, - scale: 1, + name: "CMPWloadidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.ACMPW, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPBloadidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymRead, - asm: x86.ACMPB, - scale: 1, + name: "CMPBloadidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.ACMPB, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPQconstloadidx8", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymRead, - asm: x86.ACMPQ, - scale: 8, + name: "CMPQconstloadidx8", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.ACMPQ, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPQconstloadidx1", - auxType: auxSymValAndOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.ACMPQ, - scale: 1, + name: "CMPQconstloadidx1", + auxType: auxSymValAndOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.ACMPQ, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPLconstloadidx4", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymRead, - asm: x86.ACMPL, - scale: 4, + name: "CMPLconstloadidx4", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.ACMPL, + scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPLconstloadidx1", - auxType: auxSymValAndOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.ACMPL, - scale: 1, + name: "CMPLconstloadidx1", + auxType: auxSymValAndOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.ACMPL, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPWconstloadidx2", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymRead, - asm: x86.ACMPW, - scale: 2, + name: "CMPWconstloadidx2", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.ACMPW, + scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPWconstloadidx1", - auxType: auxSymValAndOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.ACMPW, - scale: 1, + name: "CMPWconstloadidx1", + auxType: auxSymValAndOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.ACMPW, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "CMPBconstloadidx1", - auxType: auxSymValAndOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.ACMPB, - scale: 1, + name: "CMPBconstloadidx1", + auxType: auxSymValAndOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.ACMPB, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8859,8 +14561,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -8870,8 +14572,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -8881,8 +14583,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ABTL, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8892,8 +14594,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ABTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8902,14 +14604,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ABTCL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8918,14 +14621,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8934,14 +14638,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ABTRL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8950,14 +14655,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8966,14 +14672,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ABTSL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8982,14 +14689,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -8997,10 +14705,11 @@ var opcodeTable = [...]opInfo{ name: "BTLconst", auxType: auxInt8, argLen: 1, + earlyOk: true, asm: x86.ABTL, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9008,10 +14717,11 @@ var opcodeTable = [...]opInfo{ name: "BTQconst", auxType: auxInt8, argLen: 1, + earlyOk: true, asm: x86.ABTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9021,13 +14731,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9037,13 +14748,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9053,13 +14765,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9069,11 +14782,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -9083,11 +14797,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -9097,11 +14812,12 @@ var opcodeTable = [...]opInfo{ argLen: 2, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -9112,8 +14828,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9124,8 +14840,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9136,8 +14852,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9148,8 +14864,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9160,7 +14876,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9171,7 +14887,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9182,7 +14898,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9193,7 +14909,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9202,14 +14918,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9218,14 +14935,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9235,13 +14953,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9251,13 +14970,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9266,14 +14986,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9282,14 +15003,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9298,14 +15020,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9314,14 +15037,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9331,13 +15055,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9347,13 +15072,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9363,13 +15089,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9379,13 +15106,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9394,14 +15122,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9410,14 +15139,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9426,14 +15156,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9442,14 +15173,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9459,13 +15191,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9475,13 +15208,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9491,13 +15225,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9507,47 +15242,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - }, - outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - }, - }, - }, - { - name: "SHRDQ", - argLen: 3, - resultInArg0: true, - clobberFlags: true, - asm: x86.ASHRQ, - reg: regInfo{ - inputs: []inputInfo{ - {2, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - }, - outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - }, - }, - }, - { - name: "SHLDQ", - argLen: 3, - resultInArg0: true, - clobberFlags: true, - asm: x86.ASHLQ, - reg: regInfo{ - inputs: []inputInfo{ - {2, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9556,14 +15258,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9572,14 +15275,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9588,14 +15292,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9604,14 +15309,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9620,14 +15326,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ARORQ, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9636,14 +15343,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ARORL, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9652,14 +15360,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ARORW, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9668,14 +15377,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ARORB, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // CX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 2, v2: 0}}, // CX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9685,13 +15395,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9701,13 +15412,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9717,13 +15429,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9733,13 +15446,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9750,15 +15464,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9769,15 +15484,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9788,15 +15504,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9807,15 +15524,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9826,15 +15544,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9845,15 +15564,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9864,15 +15584,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9883,15 +15604,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9902,15 +15624,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9921,15 +15644,16 @@ var opcodeTable = [...]opInfo{ resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9939,17 +15663,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9959,17 +15684,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9979,17 +15705,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -9999,17 +15726,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10019,17 +15747,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10039,17 +15768,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10059,17 +15789,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10079,17 +15810,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10099,17 +15831,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10119,17 +15852,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.ASUBQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10139,17 +15873,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10159,17 +15894,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10179,17 +15915,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10199,17 +15936,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10219,17 +15957,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10239,17 +15978,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10259,17 +15999,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10279,17 +16020,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10299,17 +16041,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10319,17 +16062,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10339,17 +16083,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10359,17 +16104,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10379,17 +16125,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10399,17 +16146,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10419,17 +16167,18 @@ var opcodeTable = [...]opInfo{ argLen: 4, resultInArg0: true, clobberFlags: true, + addrSinkArg1: true, symEffect: SymRead, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -10439,12 +16188,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10454,12 +16204,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10469,12 +16220,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10484,12 +16236,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10499,12 +16252,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10514,12 +16268,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10529,12 +16284,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10544,12 +16300,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10559,12 +16316,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10574,12 +16332,13 @@ var opcodeTable = [...]opInfo{ argLen: 3, clobberFlags: true, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10588,14 +16347,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10604,14 +16364,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10620,14 +16381,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10636,14 +16398,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10652,14 +16415,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10668,14 +16432,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10684,14 +16449,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10700,14 +16466,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10716,14 +16483,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10732,14 +16500,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10748,14 +16517,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10764,14 +16534,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10780,14 +16551,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10796,14 +16568,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10812,14 +16585,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10828,14 +16602,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10844,14 +16619,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10860,14 +16636,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10876,14 +16653,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10892,14 +16670,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10908,14 +16687,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10924,14 +16704,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10940,14 +16721,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10956,14 +16738,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10972,14 +16755,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10988,13 +16772,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11003,13 +16788,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11018,13 +16804,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11033,13 +16820,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11048,13 +16836,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11063,13 +16852,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11078,13 +16868,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11093,13 +16884,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11108,13 +16900,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11123,13 +16916,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11138,13 +16932,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11153,13 +16948,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11168,13 +16964,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11183,13 +16980,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11198,13 +16996,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11213,13 +17012,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11228,13 +17028,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11243,13 +17044,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11258,13 +17060,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11273,13 +17076,14 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, + addrSinkArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11288,13 +17092,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ANEGQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11303,13 +17108,14 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, clobberFlags: true, + earlyOk: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11317,13 +17123,14 @@ var opcodeTable = [...]opInfo{ name: "NOTQ", argLen: 1, resultInArg0: true, + earlyOk: true, asm: x86.ANOTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11331,27 +17138,29 @@ var opcodeTable = [...]opInfo{ name: "NOTL", argLen: 1, resultInArg0: true, + earlyOk: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "BSFQ", - argLen: 1, - asm: x86.ABSFQ, + name: "BSFQ", + argLen: 1, + earlyOk: true, + asm: x86.ABSFQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11359,27 +17168,29 @@ var opcodeTable = [...]opInfo{ name: "BSFL", argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "BSRQ", - argLen: 1, - asm: x86.ABSRQ, + name: "BSRQ", + argLen: 1, + earlyOk: true, + asm: x86.ABSRQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11387,13 +17198,14 @@ var opcodeTable = [...]opInfo{ name: "BSRL", argLen: 1, clobberFlags: true, + earlyOk: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11401,14 +17213,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQEQ", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11416,14 +17229,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQNE", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11431,14 +17245,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQLT", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQLT, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11446,14 +17261,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQGT", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQGT, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11461,14 +17277,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQLE", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQLE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11476,14 +17293,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQGE", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQGE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11491,14 +17309,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQLS", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQLS, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11506,14 +17325,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQHI", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQHI, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11521,14 +17341,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQCC", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQCC, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11536,14 +17357,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQCS", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQCS, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11551,14 +17373,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLEQ", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11566,14 +17389,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLNE", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11581,14 +17405,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLLT", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLLT, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11596,14 +17421,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLGT", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLGT, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11611,14 +17437,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLLE", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLLE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11626,14 +17453,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLGE", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLGE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11641,14 +17469,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLLS", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLLS, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11656,14 +17485,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLHI", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLHI, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11671,14 +17501,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLCC", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLCC, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11686,14 +17517,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLCS", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLCS, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11701,14 +17533,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWEQ", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11716,14 +17549,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWNE", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11731,14 +17565,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWLT", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWLT, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11746,14 +17581,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWGT", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWGT, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11761,14 +17597,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWLE", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWLE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11776,14 +17613,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWGE", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWGE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11791,14 +17629,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWLS", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWLS, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11806,14 +17645,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWHI", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWHI, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11821,14 +17661,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWCC", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11836,14 +17677,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWCS", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWCS, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11852,14 +17694,15 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, needIntTemp: true, + earlyOk: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11867,14 +17710,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQNEF", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11882,14 +17726,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQGTF", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQHI, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11897,14 +17742,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVQGEF", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVQCC, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11913,14 +17759,15 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, needIntTemp: true, + earlyOk: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11928,14 +17775,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLNEF", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11943,14 +17791,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLGTF", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLHI, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11958,14 +17807,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVLGEF", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVLCC, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11974,14 +17824,15 @@ var opcodeTable = [...]opInfo{ argLen: 3, resultInArg0: true, needIntTemp: true, + earlyOk: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -11989,14 +17840,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWNEF", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12004,14 +17856,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWGTF", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWHI, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12019,14 +17872,15 @@ var opcodeTable = [...]opInfo{ name: "CMOVWGEF", argLen: 3, resultInArg0: true, + earlyOk: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12034,13 +17888,14 @@ var opcodeTable = [...]opInfo{ name: "BSWAPQ", argLen: 1, resultInArg0: true, + earlyOk: true, asm: x86.ABSWAPQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12048,13 +17903,14 @@ var opcodeTable = [...]opInfo{ name: "BSWAPL", argLen: 1, resultInArg0: true, + earlyOk: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12065,10 +17921,10 @@ var opcodeTable = [...]opInfo{ asm: x86.APOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12079,36 +17935,38 @@ var opcodeTable = [...]opInfo{ asm: x86.APOPCNTL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SQRTSD", - argLen: 1, - asm: x86.ASQRTSD, + name: "SQRTSD", + argLen: 1, + earlyOk: true, + asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SQRTSS", - argLen: 1, - asm: x86.ASQRTSS, + name: "SQRTSS", + argLen: 1, + earlyOk: true, + asm: x86.ASQRTSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -12119,10 +17977,24 @@ var opcodeTable = [...]opInfo{ asm: x86.AROUNDSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "ROUNDSS", + auxType: auxInt8, + argLen: 1, + asm: x86.AROUNDSS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -12131,12 +18003,13 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, zeroWidth: true, + earlyOk: true, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -12145,12 +18018,13 @@ var opcodeTable = [...]opInfo{ argLen: 1, resultInArg0: true, zeroWidth: true, + earlyOk: true, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -12161,12 +18035,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AVFMADD231SS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -12177,12 +18051,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AVFMADD231SD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -12190,14 +18064,15 @@ var opcodeTable = [...]opInfo{ name: "MINSD", argLen: 2, resultInArg0: true, + earlyOk: true, asm: x86.AMINSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -12205,144 +18080,158 @@ var opcodeTable = [...]opInfo{ name: "MINSS", argLen: 2, resultInArg0: true, + earlyOk: true, asm: x86.AMINSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SBBQcarrymask", - argLen: 1, - asm: x86.ASBBQ, + name: "SBBQcarrymask", + argLen: 1, + earlyOk: true, + asm: x86.ASBBQ, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SBBLcarrymask", - argLen: 1, - asm: x86.ASBBL, + name: "SBBLcarrymask", + argLen: 1, + earlyOk: true, + asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETEQ", - argLen: 1, - asm: x86.ASETEQ, + name: "SETEQ", + argLen: 1, + earlyOk: true, + asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETNE", - argLen: 1, - asm: x86.ASETNE, + name: "SETNE", + argLen: 1, + earlyOk: true, + asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETL", - argLen: 1, - asm: x86.ASETLT, + name: "SETL", + argLen: 1, + earlyOk: true, + asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETLE", - argLen: 1, - asm: x86.ASETLE, + name: "SETLE", + argLen: 1, + earlyOk: true, + asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETG", - argLen: 1, - asm: x86.ASETGT, + name: "SETG", + argLen: 1, + earlyOk: true, + asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETGE", - argLen: 1, - asm: x86.ASETGE, + name: "SETGE", + argLen: 1, + earlyOk: true, + asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETB", - argLen: 1, - asm: x86.ASETCS, + name: "SETB", + argLen: 1, + earlyOk: true, + asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETBE", - argLen: 1, - asm: x86.ASETLS, + name: "SETBE", + argLen: 1, + earlyOk: true, + asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETA", - argLen: 1, - asm: x86.ASETHI, + name: "SETA", + argLen: 1, + earlyOk: true, + asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETAE", - argLen: 1, - asm: x86.ASETCC, + name: "SETAE", + argLen: 1, + earlyOk: true, + asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETO", - argLen: 1, - asm: x86.ASETOS, + name: "SETO", + argLen: 1, + earlyOk: true, + asm: x86.ASETOS, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12351,11 +18240,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.ASETEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12364,11 +18254,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.ASETNE, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12377,11 +18268,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.ASETLT, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12390,11 +18282,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.ASETLE, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12403,11 +18296,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.ASETGT, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12416,11 +18310,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.ASETGE, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12429,11 +18324,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.ASETCS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12442,11 +18338,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.ASETLS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12455,11 +18352,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.ASETHI, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12468,161 +18366,182 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.ASETCC, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "SETEQstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.ASETEQ, - scale: 1, + name: "SETEQstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.ASETEQ, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "SETNEstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.ASETNE, - scale: 1, + name: "SETNEstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.ASETNE, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "SETLstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.ASETLT, - scale: 1, + name: "SETLstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.ASETLT, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "SETLEstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.ASETLE, - scale: 1, + name: "SETLEstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.ASETLE, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "SETGstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.ASETGT, - scale: 1, + name: "SETGstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.ASETGT, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "SETGEstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.ASETGE, - scale: 1, + name: "SETGEstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.ASETGE, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "SETBstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.ASETCS, - scale: 1, + name: "SETBstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.ASETCS, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "SETBEstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.ASETLS, - scale: 1, + name: "SETBEstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.ASETLS, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "SETAstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.ASETHI, - scale: 1, + name: "SETAstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.ASETHI, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "SETAEstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.ASETCC, - scale: 1, + name: "SETAEstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.ASETCC, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12631,10 +18550,11 @@ var opcodeTable = [...]opInfo{ argLen: 1, clobberFlags: true, needIntTemp: true, + earlyOk: true, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12643,128 +18563,139 @@ var opcodeTable = [...]opInfo{ argLen: 1, clobberFlags: true, needIntTemp: true, + earlyOk: true, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETORD", - argLen: 1, - asm: x86.ASETPC, + name: "SETORD", + argLen: 1, + earlyOk: true, + asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETNAN", - argLen: 1, - asm: x86.ASETPS, + name: "SETNAN", + argLen: 1, + earlyOk: true, + asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETGF", - argLen: 1, - asm: x86.ASETHI, + name: "SETGF", + argLen: 1, + earlyOk: true, + asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SETGEF", - argLen: 1, - asm: x86.ASETCC, + name: "SETGEF", + argLen: 1, + earlyOk: true, + asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVBQSX", - argLen: 1, - asm: x86.AMOVBQSX, + name: "MOVBQSX", + argLen: 1, + earlyOk: true, + asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVBQZX", - argLen: 1, - asm: x86.AMOVBLZX, + name: "MOVBQZX", + argLen: 1, + earlyOk: true, + asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVWQSX", - argLen: 1, - asm: x86.AMOVWQSX, + name: "MOVWQSX", + argLen: 1, + earlyOk: true, + asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVWQZX", - argLen: 1, - asm: x86.AMOVWLZX, + name: "MOVWQZX", + argLen: 1, + earlyOk: true, + asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVLQSX", - argLen: 1, - asm: x86.AMOVLQSX, + name: "MOVLQSX", + argLen: 1, + earlyOk: true, + asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVLQZX", - argLen: 1, - asm: x86.AMOVL, + name: "MOVLQZX", + argLen: 1, + earlyOk: true, + asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12773,10 +18704,11 @@ var opcodeTable = [...]opInfo{ auxType: auxInt32, argLen: 0, rematerializeable: true, + earlyOk: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12785,188 +18717,203 @@ var opcodeTable = [...]opInfo{ auxType: auxInt64, argLen: 0, rematerializeable: true, + earlyOk: true, asm: x86.AMOVQ, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "CVTTSD2SL", - argLen: 1, - asm: x86.ACVTTSD2SL, + name: "CVTTSD2SL", + argLen: 1, + earlyOk: true, + asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "CVTTSD2SQ", - argLen: 1, - asm: x86.ACVTTSD2SQ, + name: "CVTTSD2SQ", + argLen: 1, + earlyOk: true, + asm: x86.ACVTTSD2SQ, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "CVTTSS2SL", - argLen: 1, - asm: x86.ACVTTSS2SL, + name: "CVTTSS2SL", + argLen: 1, + earlyOk: true, + asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "CVTTSS2SQ", - argLen: 1, - asm: x86.ACVTTSS2SQ, + name: "CVTTSS2SQ", + argLen: 1, + earlyOk: true, + asm: x86.ACVTTSS2SQ, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "CVTSL2SS", - argLen: 1, - asm: x86.ACVTSL2SS, + name: "CVTSL2SS", + argLen: 1, + earlyOk: true, + asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CVTSL2SD", - argLen: 1, - asm: x86.ACVTSL2SD, + name: "CVTSL2SD", + argLen: 1, + earlyOk: true, + asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CVTSQ2SS", - argLen: 1, - asm: x86.ACVTSQ2SS, + name: "CVTSQ2SS", + argLen: 1, + earlyOk: true, + asm: x86.ACVTSQ2SS, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CVTSQ2SD", - argLen: 1, - asm: x86.ACVTSQ2SD, + name: "CVTSQ2SD", + argLen: 1, + earlyOk: true, + asm: x86.ACVTSQ2SD, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CVTSD2SS", - argLen: 1, - asm: x86.ACVTSD2SS, + name: "CVTSD2SS", + argLen: 1, + earlyOk: true, + asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CVTSS2SD", - argLen: 1, - asm: x86.ACVTSS2SD, + name: "CVTSS2SD", + argLen: 1, + earlyOk: true, + asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVQi2f", - argLen: 1, + name: "MOVQi2f", + argLen: 1, + earlyOk: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVQf2i", - argLen: 1, + name: "MOVQf2i", + argLen: 1, + earlyOk: true, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVLi2f", - argLen: 1, + name: "MOVLi2f", + argLen: 1, + earlyOk: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVLf2i", - argLen: 1, + name: "MOVLf2i", + argLen: 1, + earlyOk: true, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -12975,14 +18922,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -12991,14 +18939,15 @@ var opcodeTable = [...]opInfo{ argLen: 2, commutative: true, resultInArg0: true, + earlyOk: true, asm: x86.APOR, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -13007,14 +18956,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 1, rematerializeable: true, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13023,14 +18973,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 1, rematerializeable: true, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13039,14 +18990,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 1, rematerializeable: true, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13055,16 +19007,17 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, commutative: true, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13073,16 +19026,17 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, commutative: true, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13091,16 +19045,17 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, commutative: true, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAW, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13108,16 +19063,17 @@ var opcodeTable = [...]opInfo{ name: "LEAQ2", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAQ, scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13125,16 +19081,17 @@ var opcodeTable = [...]opInfo{ name: "LEAL2", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAL, scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13142,16 +19099,17 @@ var opcodeTable = [...]opInfo{ name: "LEAW2", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAW, scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13159,16 +19117,17 @@ var opcodeTable = [...]opInfo{ name: "LEAQ4", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAQ, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13176,16 +19135,17 @@ var opcodeTable = [...]opInfo{ name: "LEAL4", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13193,16 +19153,17 @@ var opcodeTable = [...]opInfo{ name: "LEAW4", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAW, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13210,16 +19171,17 @@ var opcodeTable = [...]opInfo{ name: "LEAQ8", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13227,16 +19189,17 @@ var opcodeTable = [...]opInfo{ name: "LEAL8", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13244,16 +19207,17 @@ var opcodeTable = [...]opInfo{ name: "LEAW8", auxType: auxSymOff, argLen: 2, + earlyOk: true, symEffect: SymAddr, asm: x86.ALEAW, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13262,14 +19226,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13278,14 +19243,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13294,14 +19260,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13310,14 +19277,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13326,14 +19294,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13342,14 +19311,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13358,14 +19328,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13374,12 +19345,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13388,12 +19360,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13402,12 +19375,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13416,12 +19390,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13430,14 +19405,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -13446,276 +19422,301 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { - name: "MOVBloadidx1", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.AMOVBLZX, - scale: 1, + name: "MOVBloadidx1", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.AMOVBLZX, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVWloadidx1", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.AMOVWLZX, - scale: 1, + name: "MOVWloadidx1", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.AMOVWLZX, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVWloadidx2", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVWLZX, - scale: 2, + name: "MOVWloadidx2", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVWLZX, + scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVLloadidx1", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.AMOVL, - scale: 1, + name: "MOVLloadidx1", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.AMOVL, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVLloadidx4", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVL, - scale: 4, + name: "MOVLloadidx4", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVL, + scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVLloadidx8", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVL, - scale: 8, + name: "MOVLloadidx8", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVL, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVQloadidx1", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.AMOVQ, - scale: 1, + name: "MOVQloadidx1", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.AMOVQ, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVQloadidx8", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVQ, - scale: 8, + name: "MOVQloadidx8", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVQ, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVBstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVB, - scale: 1, + name: "MOVBstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVB, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVWstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVW, - scale: 1, + name: "MOVWstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVW, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVWstoreidx2", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVW, - scale: 2, + name: "MOVWstoreidx2", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVW, + scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVLstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVL, - scale: 1, + name: "MOVLstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVL, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVLstoreidx4", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVL, - scale: 4, + name: "MOVLstoreidx4", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVL, + scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVLstoreidx8", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVL, - scale: 8, + name: "MOVLstoreidx8", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVL, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVQstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVQ, - scale: 1, + name: "MOVQstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVQ, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVQstoreidx8", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVQ, - scale: 8, + name: "MOVQstoreidx8", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVQ, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13724,11 +19725,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13737,11 +19739,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13750,11 +19753,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13763,11 +19767,12 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13776,113 +19781,125 @@ var opcodeTable = [...]opInfo{ auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVBstoreconstidx1", - auxType: auxSymValAndOff, - argLen: 3, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVB, - scale: 1, + name: "MOVBstoreconstidx1", + auxType: auxSymValAndOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVB, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVWstoreconstidx1", - auxType: auxSymValAndOff, - argLen: 3, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVW, - scale: 1, + name: "MOVWstoreconstidx1", + auxType: auxSymValAndOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVW, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVWstoreconstidx2", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymWrite, - asm: x86.AMOVW, - scale: 2, + name: "MOVWstoreconstidx2", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVW, + scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVLstoreconstidx1", - auxType: auxSymValAndOff, - argLen: 3, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVL, - scale: 1, + name: "MOVLstoreconstidx1", + auxType: auxSymValAndOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVL, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVLstoreconstidx4", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymWrite, - asm: x86.AMOVL, - scale: 4, + name: "MOVLstoreconstidx4", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVL, + scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVQstoreconstidx1", - auxType: auxSymValAndOff, - argLen: 3, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVQ, - scale: 1, + name: "MOVQstoreconstidx1", + auxType: auxSymValAndOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVQ, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVQstoreconstidx8", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymWrite, - asm: x86.AMOVQ, - scale: 8, + name: "MOVQstoreconstidx8", + auxType: auxSymValAndOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVQ, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13891,9 +19908,10 @@ var opcodeTable = [...]opInfo{ auxType: auxInt64, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -13904,9 +19922,10 @@ var opcodeTable = [...]opInfo{ clobberFlags: true, needIntTemp: true, faultOnNilArg0: true, + addrSinkArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbersArg0: true, }, @@ -13915,13 +19934,14 @@ var opcodeTable = [...]opInfo{ name: "REPSTOSQ", argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 128}, // DI - {1, 2}, // CX - {2, 1}, // AX + {0, regMask{v1: 128, v2: 0}}, // DI + {1, regMask{v1: 2, v2: 0}}, // CX + {2, regMask{v1: 1, v2: 0}}, // AX }, - clobbers: 130, // CX DI + clobbers: regMask{v1: 130, v2: 0}, // CX DI }, }, { @@ -13931,7 +19951,7 @@ var opcodeTable = [...]opInfo{ clobberFlags: true, call: true, reg: regInfo{ - clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + clobbers: regMask{v1: 71776116913733615, v2: 0}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7 }, }, { @@ -13942,7 +19962,21 @@ var opcodeTable = [...]opInfo{ call: true, tailCall: true, reg: regInfo{ - clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + clobbers: regMask{v1: 71776116913733615, v2: 0}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7 + }, + }, + { + name: "CALLtailinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + }, + clobbers: regMask{v1: 71776116913733615, v2: 0}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7 }, }, { @@ -13953,10 +19987,10 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {1, 4}, // DX - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 4, v2: 0}}, // DX + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + clobbers: regMask{v1: 71776116913733615, v2: 0}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7 }, }, { @@ -13967,9 +20001,9 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + clobbers: regMask{v1: 71776116913733615, v2: 0}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7 }, }, { @@ -13978,12 +20012,14 @@ var opcodeTable = [...]opInfo{ argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 1073741824, // X14 + clobbers: regMask{v1: 1073741824, v2: 0}, // X14 }, }, { @@ -13994,12 +20030,14 @@ var opcodeTable = [...]opInfo{ needIntTemp: true, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 1073741824, // X14 + clobbers: regMask{v1: 1073741824, v2: 0}, // X14 clobbersArg0: true, clobbersArg1: true, }, @@ -14009,13 +20047,15 @@ var opcodeTable = [...]opInfo{ argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, reg: regInfo{ inputs: []inputInfo{ - {0, 128}, // DI - {1, 64}, // SI - {2, 2}, // CX + {0, regMask{v1: 128, v2: 0}}, // DI + {1, regMask{v1: 64, v2: 0}}, // SI + {2, regMask{v1: 2, v2: 0}}, // CX }, - clobbers: 194, // CX SI DI + clobbers: regMask{v1: 194, v2: 0}, // CX SI DI }, }, { @@ -14028,7 +20068,7 @@ var opcodeTable = [...]opInfo{ argLen: 1, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14038,7 +20078,7 @@ var opcodeTable = [...]opInfo{ zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ - {0, 4}, // DX + {0, regMask{v1: 4, v2: 0}}, // DX }, }, }, @@ -14048,7 +20088,7 @@ var opcodeTable = [...]opInfo{ rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14058,7 +20098,7 @@ var opcodeTable = [...]opInfo{ rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14070,7 +20110,7 @@ var opcodeTable = [...]opInfo{ faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14080,9 +20120,9 @@ var opcodeTable = [...]opInfo{ argLen: 1, clobberFlags: true, reg: regInfo{ - clobbers: 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + clobbers: regMask{v1: 71776116913668096, v2: 0}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7 outputs: []outputInfo{ - {0, 2048}, // R11 + {0, regMask{v1: 2048, v2: 0}}, // R11 }, }, }, @@ -14094,7 +20134,7 @@ var opcodeTable = [...]opInfo{ symEffect: SymNone, reg: regInfo{ outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14105,8 +20145,8 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14117,7 +20157,7 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14128,7 +20168,7 @@ var opcodeTable = [...]opInfo{ call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14173,10 +20213,10 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14189,10 +20229,10 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14205,10 +20245,10 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14223,11 +20263,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AXCHGB, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14242,11 +20282,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AXCHGL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14261,11 +20301,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AXCHGQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14281,11 +20321,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AXADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14301,11 +20341,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AXADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14330,14 +20370,14 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPXCHGL, reg: regInfo{ inputs: []inputInfo{ - {1, 1}, // AX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 1, v2: 0}}, // AX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14352,14 +20392,14 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPXCHGQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1}, // AX - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 1, v2: 0}}, // AX + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, - clobbers: 1, // AX + clobbers: regMask{v1: 1, v2: 0}, // AX outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14374,8 +20414,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDB, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14390,8 +20430,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14406,8 +20446,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14422,8 +20462,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AORB, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14438,8 +20478,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14454,8 +20494,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14473,12 +20513,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 1}, // AX + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -14496,12 +20536,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 1}, // AX + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -14519,12 +20559,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 1}, // AX + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -14542,12 +20582,12 @@ var opcodeTable = [...]opInfo{ asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 1}, // AX + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 1, v2: 0}}, // AX }, }, }, @@ -14558,7 +20598,7 @@ var opcodeTable = [...]opInfo{ asm: x86.APREFETCHT0, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14569,7 +20609,7 @@ var opcodeTable = [...]opInfo{ asm: x86.APREFETCHNTA, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14580,11 +20620,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDNQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14595,11 +20635,11 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDNL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14610,10 +20650,10 @@ var opcodeTable = [...]opInfo{ asm: x86.ABLSIQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14624,10 +20664,10 @@ var opcodeTable = [...]opInfo{ asm: x86.ABLSIL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14638,10 +20678,10 @@ var opcodeTable = [...]opInfo{ asm: x86.ABLSMSKQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14652,10 +20692,10 @@ var opcodeTable = [...]opInfo{ asm: x86.ABLSMSKL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14665,11 +20705,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ABLSRQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14679,11 +20719,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ABLSRL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {1, 0}, - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14694,10 +20734,10 @@ var opcodeTable = [...]opInfo{ asm: x86.ATZCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14708,10 +20748,10 @@ var opcodeTable = [...]opInfo{ asm: x86.ATZCNTL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14722,10 +20762,10 @@ var opcodeTable = [...]opInfo{ asm: x86.ALZCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14736,10 +20776,10 @@ var opcodeTable = [...]opInfo{ asm: x86.ALZCNTL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14748,12 +20788,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVBEW, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14762,14 +20803,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14778,12 +20820,13 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14792,14 +20835,15 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -14808,207 +20852,225 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymWrite, asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVBELloadidx1", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.AMOVBEL, - scale: 1, + name: "MOVBELloadidx1", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.AMOVBEL, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVBELloadidx4", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVBEL, - scale: 4, + name: "MOVBELloadidx4", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVBEL, + scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVBELloadidx8", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVBEL, - scale: 8, + name: "MOVBELloadidx8", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVBEL, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVBEQloadidx1", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: x86.AMOVBEQ, - scale: 1, + name: "MOVBEQloadidx1", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: x86.AMOVBEQ, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVBEQloadidx8", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AMOVBEQ, - scale: 8, + name: "MOVBEQloadidx8", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: x86.AMOVBEQ, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MOVBEWstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVBEW, - scale: 1, + name: "MOVBEWstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVBEW, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVBEWstoreidx2", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVBEW, - scale: 2, + name: "MOVBEWstoreidx2", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVBEW, + scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVBELstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVBEL, - scale: 1, + name: "MOVBELstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVBEL, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVBELstoreidx4", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVBEL, - scale: 4, + name: "MOVBELstoreidx4", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVBEL, + scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVBELstoreidx8", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVBEL, - scale: 8, + name: "MOVBELstoreidx8", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVBEL, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVBEQstoreidx1", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: x86.AMOVBEQ, - scale: 1, + name: "MOVBEQstoreidx1", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: x86.AMOVBEQ, + scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { - name: "MOVBEQstoreidx8", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: x86.AMOVBEQ, - scale: 8, + name: "MOVBEQstoreidx8", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: x86.AMOVBEQ, + scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -15018,11 +21080,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15032,11 +21094,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15046,11 +21108,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15060,11 +21122,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15074,11 +21136,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15088,11 +21150,11 @@ var opcodeTable = [...]opInfo{ asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15101,15 +21163,16 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15118,15 +21181,16 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15135,15 +21199,16 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15152,15 +21217,16 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15169,15 +21235,16 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15186,15 +21253,16 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15203,17 +21271,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15222,17 +21291,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15241,17 +21311,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15260,17 +21331,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASARXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15279,17 +21351,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASARXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15298,17 +21371,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15317,17 +21391,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15336,17 +21411,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15355,17 +21431,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15374,17 +21451,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15393,17 +21471,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15412,17 +21491,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15431,17 +21511,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15450,17 +21531,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15469,17 +21551,18 @@ var opcodeTable = [...]opInfo{ auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, + addrSinkArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, @@ -15490,11 +21573,11 @@ var opcodeTable = [...]opInfo{ asm: x86.APUNPCKLBW, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -15505,10 +21588,10 @@ var opcodeTable = [...]opInfo{ asm: x86.APSHUFLW, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -15519,10 +21602,10 @@ var opcodeTable = [...]opInfo{ asm: x86.APSHUFB, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -15532,10 +21615,10 @@ var opcodeTable = [...]opInfo{ asm: x86.AVPBROADCASTB, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -15546,11 +21629,11 @@ var opcodeTable = [...]opInfo{ asm: x86.APSIGNB, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -15562,11 +21645,11 @@ var opcodeTable = [...]opInfo{ asm: x86.APCMPEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, @@ -15576,27303 +21659,94567 @@ var opcodeTable = [...]opInfo{ asm: x86.APMOVMSKB, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, - { - name: "ADD", - argLen: 2, - commutative: true, - asm: arm.AADD, + name: "VMOVDQUload128", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVDQU, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDconst", - auxType: auxInt32, - argLen: 1, - asm: arm.AADD, + name: "VMOVDQUstore128", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVMOVDQU, reg: regInfo{ inputs: []inputInfo{ - {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { - name: "SUB", - argLen: 2, - asm: arm.ASUB, + name: "VMOVDQUload256", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVDQU, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ASUB, + name: "VMOVDQUstore256", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVMOVDQU, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { - name: "RSB", - argLen: 2, - asm: arm.ARSB, + name: "VMOVDQUload512", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVDQU64, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSBconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ARSB, + name: "VMOVDQUstore512", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVMOVDQU64, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MUL", - argLen: 2, - commutative: true, - asm: arm.AMUL, + name: "VPMASK32load128", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVPMASKMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "HMUL", - argLen: 2, - commutative: true, - asm: arm.AMULL, + name: "VPMASK32store128", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVPMASKMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { - name: "HMULU", - argLen: 2, - commutative: true, - asm: arm.AMULLU, + name: "VPMASK64load128", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVPMASKMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CALLudiv", - argLen: 2, - clobberFlags: true, + name: "VPMASK64store128", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVPMASKMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 1}, // R0 - }, - clobbers: 20492, // R2 R3 R12 R14 - outputs: []outputInfo{ - {0, 1}, // R0 - {1, 2}, // R1 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { - name: "ADDS", - argLen: 2, - commutative: true, - asm: arm.AADD, + name: "VPMASK32load256", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVPMASKMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSconst", - auxType: auxInt32, - argLen: 1, - asm: arm.AADD, + name: "VPMASK32store256", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVPMASKMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, - outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { - name: "ADC", - argLen: 3, - commutative: true, - asm: arm.AADC, + name: "VPMASK64load256", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVPMASKMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADCconst", - auxType: auxInt32, - argLen: 2, - asm: arm.AADC, + name: "VPMASK64store256", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVPMASKMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { - name: "SUBS", - argLen: 2, - asm: arm.ASUB, + name: "VPMASK8load512", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVDQU8, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBSconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ASUB, + name: "VPMASK8store512", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVMOVDQU8, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, - outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSBSconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ARSB, + name: "VPMASK16load512", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVDQU16, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SBC", - argLen: 3, - asm: arm.ASBC, + name: "VPMASK16store512", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVMOVDQU16, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SBCconst", - auxType: auxInt32, - argLen: 2, - asm: arm.ASBC, + name: "VPMASK32load512", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVDQU32, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSCconst", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSC, + name: "VPMASK32store512", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVMOVDQU32, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULLU", - argLen: 2, - commutative: true, - asm: arm.AMULLU, + name: "VPMASK64load512", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVDQU64, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULA", - argLen: 3, - asm: arm.AMULA, + name: "VPMASK64store512", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVMOVDQU64, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULS", - argLen: 3, - asm: arm.AMULS, + name: "VPMOVMToVec8x16", + argLen: 1, + asm: x86.AVPMOVM2B, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDF", - argLen: 2, - commutative: true, - asm: arm.AADDF, + name: "VPMOVMToVec8x32", + argLen: 1, + asm: x86.AVPMOVM2B, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDD", - argLen: 2, - commutative: true, - asm: arm.AADDD, + name: "VPMOVMToVec8x64", + argLen: 1, + asm: x86.AVPMOVM2B, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBF", - argLen: 2, - asm: arm.ASUBF, + name: "VPMOVMToVec16x8", + argLen: 1, + asm: x86.AVPMOVM2W, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBD", - argLen: 2, - asm: arm.ASUBD, + name: "VPMOVMToVec16x16", + argLen: 1, + asm: x86.AVPMOVM2W, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULF", - argLen: 2, - commutative: true, - asm: arm.AMULF, + name: "VPMOVMToVec16x32", + argLen: 1, + asm: x86.AVPMOVM2W, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULD", - argLen: 2, - commutative: true, - asm: arm.AMULD, + name: "VPMOVMToVec32x4", + argLen: 1, + asm: x86.AVPMOVM2D, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NMULF", - argLen: 2, - commutative: true, - asm: arm.ANMULF, + name: "VPMOVMToVec32x8", + argLen: 1, + asm: x86.AVPMOVM2D, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NMULD", - argLen: 2, - commutative: true, - asm: arm.ANMULD, + name: "VPMOVMToVec32x16", + argLen: 1, + asm: x86.AVPMOVM2D, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVF", - argLen: 2, - asm: arm.ADIVF, + name: "VPMOVMToVec64x2", + argLen: 1, + asm: x86.AVPMOVM2Q, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVD", - argLen: 2, - asm: arm.ADIVD, + name: "VPMOVMToVec64x4", + argLen: 1, + asm: x86.AVPMOVM2Q, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULAF", - argLen: 3, - resultInArg0: true, - asm: arm.AMULAF, + name: "VPMOVMToVec64x8", + argLen: 1, + asm: x86.AVPMOVM2Q, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULAD", - argLen: 3, - resultInArg0: true, - asm: arm.AMULAD, + name: "VPMOVVec8x16ToM", + argLen: 1, + asm: x86.AVPMOVB2M, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MULSF", - argLen: 3, - resultInArg0: true, - asm: arm.AMULSF, + name: "VPMOVVec8x32ToM", + argLen: 1, + asm: x86.AVPMOVB2M, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MULSD", - argLen: 3, - resultInArg0: true, - asm: arm.AMULSD, + name: "VPMOVVec8x64ToM", + argLen: 1, + asm: x86.AVPMOVB2M, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMULAD", - argLen: 3, - resultInArg0: true, - asm: arm.AFMULAD, + name: "VPMOVVec16x8ToM", + argLen: 1, + asm: x86.AVPMOVW2M, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: arm.AAND, + name: "VPMOVVec16x16ToM", + argLen: 1, + asm: x86.AVPMOVW2M, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ANDconst", - auxType: auxInt32, - argLen: 1, - asm: arm.AAND, + name: "VPMOVVec16x32ToM", + argLen: 1, + asm: x86.AVPMOVW2M, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: arm.AORR, + name: "VPMOVVec32x4ToM", + argLen: 1, + asm: x86.AVPMOVD2M, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ORconst", - auxType: auxInt32, - argLen: 1, - asm: arm.AORR, + name: "VPMOVVec32x8ToM", + argLen: 1, + asm: x86.AVPMOVD2M, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: arm.AEOR, + name: "VPMOVVec32x16ToM", + argLen: 1, + asm: x86.AVPMOVD2M, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "XORconst", - auxType: auxInt32, - argLen: 1, - asm: arm.AEOR, + name: "VPMOVVec64x2ToM", + argLen: 1, + asm: x86.AVPMOVQ2M, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "BIC", - argLen: 2, - asm: arm.ABIC, + name: "VPMOVVec64x4ToM", + argLen: 1, + asm: x86.AVPMOVQ2M, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "BICconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ABIC, + name: "VPMOVVec64x8ToM", + argLen: 1, + asm: x86.AVPMOVQ2M, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "BFX", - auxType: auxInt32, - argLen: 1, - asm: arm.ABFX, + name: "VPMOVMSKB128", + argLen: 1, + asm: x86.AVPMOVMSKB, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "BFXU", - auxType: auxInt32, - argLen: 1, - asm: arm.ABFXU, + name: "VPMOVMSKB256", + argLen: 1, + asm: x86.AVPMOVMSKB, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "MVN", + name: "VMOVMSKPS128", argLen: 1, - asm: arm.AMVN, + asm: x86.AVMOVMSKPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "NEGF", + name: "VMOVMSKPS256", argLen: 1, - asm: arm.ANEGF, + asm: x86.AVMOVMSKPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "NEGD", + name: "VMOVMSKPD128", argLen: 1, - asm: arm.ANEGD, + asm: x86.AVMOVMSKPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SQRTD", + name: "VMOVMSKPD256", argLen: 1, - asm: arm.ASQRTD, + asm: x86.AVMOVMSKPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "SQRTF", - argLen: 1, - asm: arm.ASQRTF, + name: "Zero128", + argLen: 0, + zeroWidth: true, + fixedReg: true, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147483648, v2: 0}}, // X15 }, }, }, { - name: "ABSD", - argLen: 1, - asm: arm.AABSD, + name: "Zero256", + argLen: 0, + asm: x86.AVPXOR, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, + }, + }, + { + name: "Zero512", + argLen: 0, + asm: x86.AVPXORQ, + reg: regInfo{ outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CLZ", + name: "VMOVSDf2v", argLen: 1, - asm: arm.ACLZ, + asm: x86.AVMOVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REV", + name: "VMOVSSf2v", argLen: 1, - asm: arm.AREV, + asm: x86.AVMOVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REV16", + name: "VMOVQ", argLen: 1, - asm: arm.AREV16, + asm: x86.AVMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RBIT", + name: "VMOVD", argLen: 1, - asm: arm.ARBIT, + asm: x86.AVMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLL", - argLen: 2, - asm: arm.ASLL, + name: "VMOVQload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLLconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ASLL, + name: "VMOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRL", - argLen: 2, - asm: arm.ASRL, + name: "VMOVSSload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ASRL, + name: "VMOVSDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRA", - argLen: 2, - asm: arm.ASRA, + name: "VMOVSSconst", + auxType: auxFloat32, + argLen: 0, + rematerializeable: true, + asm: x86.AVMOVSS, reg: regInfo{ - inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRAconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ASRA, + name: "VMOVSDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: x86.AVMOVSD, reg: regInfo{ - inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRR", - argLen: 2, + name: "VZEROUPPER", + argLen: 1, + asm: x86.AVZEROUPPER, + reg: regInfo{ + clobbers: regMask{v1: 2147418112, v2: 0}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + { + name: "VZEROALL", + argLen: 1, + asm: x86.AVZEROALL, + reg: regInfo{ + clobbers: regMask{v1: 2147418112, v2: 0}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + { + name: "KMOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AKMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SRRconst", - auxType: auxInt32, - argLen: 1, + name: "KMOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AKMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADDshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "KMOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AKMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADDshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "KMOVQload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AKMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADDshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "KMOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AKMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { - name: "SUBshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "KMOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AKMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { - name: "SUBshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "KMOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AKMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { - name: "SUBshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "KMOVQstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AKMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { - name: "RSBshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "KMOVQk", + argLen: 1, + asm: x86.AKMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "RSBshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "KMOVDk", + argLen: 1, + asm: x86.AKMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "RSBshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "KMOVWk", + argLen: 1, + asm: x86.AKMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ANDshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.AAND, + name: "KMOVBk", + argLen: 1, + asm: x86.AKMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ANDshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.AAND, + name: "KMOVQi", + argLen: 1, + asm: x86.AKMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "ANDshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.AAND, + name: "KMOVDi", + argLen: 1, + asm: x86.AKMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "ORshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.AORR, + name: "KMOVWi", + argLen: 1, + asm: x86.AKMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "ORshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.AORR, + name: "KMOVBi", + argLen: 1, + asm: x86.AKMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "ORshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.AORR, + name: "KANDB", + argLen: 2, + asm: x86.AKANDB, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "XORshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.AEOR, + name: "KANDW", + argLen: 2, + asm: x86.AKANDW, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "XORshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.AEOR, + name: "KANDD", + argLen: 2, + asm: x86.AKANDD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "XORshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.AEOR, + name: "KANDQ", + argLen: 2, + asm: x86.AKANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "XORshiftRR", - auxType: auxInt32, - argLen: 2, - asm: arm.AEOR, + name: "KORB", + argLen: 2, + asm: x86.AKORB, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "BICshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ABIC, + name: "KORW", + argLen: 2, + asm: x86.AKORW, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "BICshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ABIC, + name: "KORD", + argLen: 2, + asm: x86.AKORD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "BICshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ABIC, + name: "KORQ", + argLen: 2, + asm: x86.AKORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MVNshiftLL", - auxType: auxInt32, - argLen: 1, - asm: arm.AMVN, + name: "KXORB", + argLen: 2, + asm: x86.AKXORB, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MVNshiftRL", - auxType: auxInt32, - argLen: 1, - asm: arm.AMVN, + name: "KXORW", + argLen: 2, + asm: x86.AKXORW, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MVNshiftRA", - auxType: auxInt32, - argLen: 1, - asm: arm.AMVN, + name: "KXORD", + argLen: 2, + asm: x86.AKXORD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADCshiftLL", - auxType: auxInt32, - argLen: 3, - asm: arm.AADC, + name: "KXORQ", + argLen: 2, + asm: x86.AKXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADCshiftRL", - auxType: auxInt32, - argLen: 3, - asm: arm.AADC, + name: "KXNORB", + argLen: 2, + asm: x86.AKXNORB, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADCshiftRA", - auxType: auxInt32, - argLen: 3, - asm: arm.AADC, + name: "KXNORW", + argLen: 2, + asm: x86.AKXNORW, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SBCshiftLL", - auxType: auxInt32, - argLen: 3, - asm: arm.ASBC, + name: "KXNORD", + argLen: 2, + asm: x86.AKXNORD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SBCshiftRL", - auxType: auxInt32, - argLen: 3, - asm: arm.ASBC, + name: "KXNORQ", + argLen: 2, + asm: x86.AKXNORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SBCshiftRA", - auxType: auxInt32, - argLen: 3, - asm: arm.ASBC, + name: "VPTEST", + argLen: 2, + clobberFlags: true, + asm: x86.AVPTEST, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - }, - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { - name: "RSCshiftLL", - auxType: auxInt32, - argLen: 3, - asm: arm.ARSC, + name: "SHA1MSG1128", + argLen: 2, + resultInArg0: true, + asm: x86.ASHA1MSG1, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSCshiftRL", - auxType: auxInt32, - argLen: 3, - asm: arm.ARSC, + name: "SHA1MSG2128", + argLen: 2, + resultInArg0: true, + asm: x86.ASHA1MSG2, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSCshiftRA", - auxType: auxInt32, - argLen: 3, - asm: arm.ARSC, + name: "SHA1NEXTE128", + argLen: 2, + resultInArg0: true, + asm: x86.ASHA1NEXTE, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "SHA256MSG1128", + argLen: 2, + resultInArg0: true, + asm: x86.ASHA256MSG1, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "SHA256MSG2128", + argLen: 2, + resultInArg0: true, + asm: x86.ASHA256MSG2, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "SHA256RNDS2128", + argLen: 3, + resultInArg0: true, + asm: x86.ASHA256RNDS2, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, regMask{v1: 65536, v2: 0}}, // X0 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "VADDPD128", + argLen: 2, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "VADDPD256", + argLen: 2, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "VADDPD512", + argLen: 2, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSBSshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "VADDPDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSBSshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "VADDPDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSBSshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "VADDPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDshiftLLreg", - argLen: 3, - asm: arm.AADD, + name: "VADDPS128", + argLen: 2, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftRLreg", - argLen: 3, - asm: arm.AADD, + name: "VADDPS256", + argLen: 2, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftRAreg", - argLen: 3, - asm: arm.AADD, + name: "VADDPS512", + argLen: 2, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBshiftLLreg", - argLen: 3, - asm: arm.ASUB, + name: "VADDPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBshiftRLreg", - argLen: 3, - asm: arm.ASUB, + name: "VADDPSMasked256", + argLen: 3, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBshiftRAreg", - argLen: 3, - asm: arm.ASUB, + name: "VADDPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSBshiftLLreg", - argLen: 3, - asm: arm.ARSB, + name: "VADDSUBPD128", + argLen: 2, + asm: x86.AVADDSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBshiftRLreg", - argLen: 3, - asm: arm.ARSB, + name: "VADDSUBPD256", + argLen: 2, + asm: x86.AVADDSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBshiftRAreg", - argLen: 3, - asm: arm.ARSB, + name: "VADDSUBPS128", + argLen: 2, + asm: x86.AVADDSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftLLreg", - argLen: 3, - asm: arm.AAND, + name: "VADDSUBPS256", + argLen: 2, + asm: x86.AVADDSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRLreg", - argLen: 3, - asm: arm.AAND, + name: "VAESDEC128", + argLen: 2, + asm: x86.AVAESDEC, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRAreg", - argLen: 3, - asm: arm.AAND, + name: "VAESDEC256", + argLen: 2, + asm: x86.AVAESDEC, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftLLreg", - argLen: 3, - asm: arm.AORR, + name: "VAESDEC512", + argLen: 2, + asm: x86.AVAESDEC, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORshiftRLreg", - argLen: 3, - asm: arm.AORR, + name: "VAESDECLAST128", + argLen: 2, + asm: x86.AVAESDECLAST, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftRAreg", - argLen: 3, - asm: arm.AORR, + name: "VAESDECLAST256", + argLen: 2, + asm: x86.AVAESDECLAST, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftLLreg", - argLen: 3, - asm: arm.AEOR, + name: "VAESDECLAST512", + argLen: 2, + asm: x86.AVAESDECLAST, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORshiftRLreg", - argLen: 3, - asm: arm.AEOR, + name: "VAESENC128", + argLen: 2, + asm: x86.AVAESENC, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftRAreg", - argLen: 3, - asm: arm.AEOR, + name: "VAESENC256", + argLen: 2, + asm: x86.AVAESENC, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftLLreg", - argLen: 3, - asm: arm.ABIC, + name: "VAESENC512", + argLen: 2, + asm: x86.AVAESENC, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BICshiftRLreg", - argLen: 3, - asm: arm.ABIC, + name: "VAESENCLAST128", + argLen: 2, + asm: x86.AVAESENCLAST, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftRAreg", - argLen: 3, - asm: arm.ABIC, + name: "VAESENCLAST256", + argLen: 2, + asm: x86.AVAESENCLAST, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftLLreg", + name: "VAESENCLAST512", argLen: 2, - asm: arm.AMVN, + asm: x86.AVAESENCLAST, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MVNshiftRLreg", - argLen: 2, - asm: arm.AMVN, + name: "VAESIMC128", + argLen: 1, + asm: x86.AVAESIMC, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftRAreg", - argLen: 2, - asm: arm.AMVN, + name: "VBROADCASTSD256", + argLen: 1, + asm: x86.AVBROADCASTSD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADCshiftLLreg", - argLen: 4, - asm: arm.AADC, + name: "VBROADCASTSD512", + argLen: 1, + asm: x86.AVBROADCASTSD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADCshiftRLreg", - argLen: 4, - asm: arm.AADC, + name: "VBROADCASTSDMasked256", + argLen: 2, + asm: x86.AVBROADCASTSD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADCshiftRAreg", - argLen: 4, - asm: arm.AADC, + name: "VBROADCASTSDMasked512", + argLen: 2, + asm: x86.AVBROADCASTSD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SBCshiftLLreg", - argLen: 4, - asm: arm.ASBC, + name: "VBROADCASTSS128", + argLen: 1, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SBCshiftRLreg", - argLen: 4, - asm: arm.ASBC, + name: "VBROADCASTSS256", + argLen: 1, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SBCshiftRAreg", - argLen: 4, - asm: arm.ASBC, + name: "VBROADCASTSS512", + argLen: 1, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSCshiftLLreg", - argLen: 4, - asm: arm.ARSC, + name: "VBROADCASTSSMasked128", + argLen: 2, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSCshiftRLreg", - argLen: 4, - asm: arm.ARSC, + name: "VBROADCASTSSMasked256", + argLen: 2, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSCshiftRAreg", - argLen: 4, - asm: arm.ARSC, + name: "VBROADCASTSSMasked512", + argLen: 2, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDSshiftLLreg", - argLen: 3, - asm: arm.AADD, + name: "VCOMPRESSPDMasked128", + argLen: 2, + asm: x86.AVCOMPRESSPD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDSshiftRLreg", - argLen: 3, - asm: arm.AADD, + name: "VCOMPRESSPDMasked256", + argLen: 2, + asm: x86.AVCOMPRESSPD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDSshiftRAreg", - argLen: 3, - asm: arm.AADD, + name: "VCOMPRESSPDMasked512", + argLen: 2, + asm: x86.AVCOMPRESSPD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBSshiftLLreg", - argLen: 3, - asm: arm.ASUB, + name: "VCOMPRESSPSMasked128", + argLen: 2, + asm: x86.AVCOMPRESSPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBSshiftRLreg", - argLen: 3, - asm: arm.ASUB, + name: "VCOMPRESSPSMasked256", + argLen: 2, + asm: x86.AVCOMPRESSPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBSshiftRAreg", - argLen: 3, - asm: arm.ASUB, + name: "VCOMPRESSPSMasked512", + argLen: 2, + asm: x86.AVCOMPRESSPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSBSshiftLLreg", - argLen: 3, - asm: arm.ARSB, + name: "VCVTDQ2PD256", + argLen: 1, + asm: x86.AVCVTDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBSshiftRLreg", - argLen: 3, - asm: arm.ARSB, + name: "VCVTDQ2PD512", + argLen: 1, + asm: x86.AVCVTDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RSBSshiftRAreg", - argLen: 3, - asm: arm.ARSB, + name: "VCVTDQ2PDMasked256", + argLen: 2, + asm: x86.AVCVTDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMP", + name: "VCVTDQ2PDMasked512", argLen: 2, - asm: arm.ACMP, + asm: x86.AVCVTDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ACMP, + name: "VCVTDQ2PS128", + argLen: 1, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMN", - argLen: 2, - commutative: true, - asm: arm.ACMN, + name: "VCVTDQ2PS256", + argLen: 1, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ACMN, + name: "VCVTDQ2PS512", + argLen: 1, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TST", - argLen: 2, - commutative: true, - asm: arm.ATST, + name: "VCVTDQ2PSMasked128", + argLen: 2, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ATST, + name: "VCVTDQ2PSMasked256", + argLen: 2, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TEQ", - argLen: 2, - commutative: true, - asm: arm.ATEQ, + name: "VCVTDQ2PSMasked512", + argLen: 2, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TEQconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ATEQ, + name: "VCVTPD2PS256", + argLen: 1, + asm: x86.AVCVTPD2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPF", + name: "VCVTPD2PSMasked256", argLen: 2, - asm: arm.ACMPF, + asm: x86.AVCVTPD2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPD", - argLen: 2, - asm: arm.ACMPD, + name: "VCVTPD2PSX128", + argLen: 1, + asm: x86.AVCVTPD2PSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMP, + name: "VCVTPD2PSXMasked128", + argLen: 2, + asm: x86.AVCVTPD2PSX, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMP, + name: "VCVTPD2PSY128", + argLen: 1, + asm: x86.AVCVTPD2PSY, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMP, + name: "VCVTPD2PSYMasked128", + argLen: 2, + asm: x86.AVCVTPD2PSY, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMNshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMN, + name: "VCVTPS2PD256", + argLen: 1, + asm: x86.AVCVTPS2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMN, + name: "VCVTPS2PD512", + argLen: 1, + asm: x86.AVCVTPS2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMNshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMN, + name: "VCVTPS2PDMasked256", + argLen: 2, + asm: x86.AVCVTPS2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ATST, + name: "VCVTPS2PDMasked512", + argLen: 2, + asm: x86.AVCVTPS2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ATST, + name: "VCVTQQ2PD128", + argLen: 1, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ATST, + name: "VCVTQQ2PD256", + argLen: 1, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TEQshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ATEQ, + name: "VCVTQQ2PD512", + argLen: 1, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TEQshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ATEQ, + name: "VCVTQQ2PDMasked128", + argLen: 2, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TEQshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ATEQ, + name: "VCVTQQ2PDMasked256", + argLen: 2, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPshiftLLreg", - argLen: 3, - asm: arm.ACMP, + name: "VCVTQQ2PDMasked512", + argLen: 2, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPshiftRLreg", - argLen: 3, - asm: arm.ACMP, + name: "VCVTQQ2PS256", + argLen: 1, + asm: x86.AVCVTQQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPshiftRAreg", - argLen: 3, - asm: arm.ACMP, + name: "VCVTQQ2PSMasked256", + argLen: 2, + asm: x86.AVCVTQQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMNshiftLLreg", - argLen: 3, - asm: arm.ACMN, + name: "VCVTQQ2PSX128", + argLen: 1, + asm: x86.AVCVTQQ2PSX, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMNshiftRLreg", - argLen: 3, - asm: arm.ACMN, + name: "VCVTQQ2PSXMasked128", + argLen: 2, + asm: x86.AVCVTQQ2PSX, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMNshiftRAreg", - argLen: 3, - asm: arm.ACMN, + name: "VCVTQQ2PSY128", + argLen: 1, + asm: x86.AVCVTQQ2PSY, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTshiftLLreg", - argLen: 3, - asm: arm.ATST, + name: "VCVTQQ2PSYMasked128", + argLen: 2, + asm: x86.AVCVTQQ2PSY, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTshiftRLreg", - argLen: 3, - asm: arm.ATST, + name: "VCVTTPD2DQ256", + argLen: 1, + asm: x86.AVCVTTPD2DQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTshiftRAreg", - argLen: 3, - asm: arm.ATST, + name: "VCVTTPD2DQMasked256", + argLen: 2, + asm: x86.AVCVTTPD2DQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TEQshiftLLreg", - argLen: 3, - asm: arm.ATEQ, + name: "VCVTTPD2DQX128", + argLen: 1, + asm: x86.AVCVTTPD2DQX, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TEQshiftRLreg", - argLen: 3, - asm: arm.ATEQ, + name: "VCVTTPD2DQXMasked128", + argLen: 2, + asm: x86.AVCVTTPD2DQX, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TEQshiftRAreg", - argLen: 3, - asm: arm.ATEQ, + name: "VCVTTPD2DQY128", + argLen: 1, + asm: x86.AVCVTTPD2DQY, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPF0", - argLen: 1, - asm: arm.ACMPF, + name: "VCVTTPD2DQYMasked128", + argLen: 2, + asm: x86.AVCVTTPD2DQY, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPD0", + name: "VCVTTPD2QQ128", argLen: 1, - asm: arm.ACMPD, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWconst", - auxType: auxInt32, - argLen: 0, - rematerializeable: true, - asm: arm.AMOVW, + name: "VCVTTPD2QQ256", + argLen: 1, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: arm.AMOVF, + name: "VCVTTPD2QQ512", + argLen: 1, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: arm.AMOVD, + name: "VCVTTPD2QQMasked128", + argLen: 2, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: arm.AMOVW, + name: "VCVTTPD2QQMasked256", + argLen: 2, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294975488}, // SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVB, + name: "VCVTTPD2QQMasked512", + argLen: 2, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVBU, + name: "VCVTTPD2UDQ256", + argLen: 1, + asm: x86.AVCVTTPD2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVH, + name: "VCVTTPD2UDQMasked256", + argLen: 2, + asm: x86.AVCVTTPD2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVHU, + name: "VCVTTPD2UDQX128", + argLen: 1, + asm: x86.AVCVTTPD2UDQX, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVW, + name: "VCVTTPD2UDQXMasked128", + argLen: 2, + asm: x86.AVCVTTPD2UDQX, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVF, + name: "VCVTTPD2UDQY128", + argLen: 1, + asm: x86.AVCVTTPD2UDQY, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVD, + name: "VCVTTPD2UDQYMasked128", + argLen: 2, + asm: x86.AVCVTTPD2UDQY, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm.AMOVB, + name: "VCVTTPD2UQQ128", + argLen: 1, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - }, - }, - { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm.AMOVH, - reg: regInfo{ - inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm.AMOVW, + name: "VCVTTPD2UQQ256", + argLen: 1, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - }, - }, - { - name: "MOVFstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm.AMOVF, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm.AMOVD, + name: "VCVTTPD2UQQ512", + argLen: 1, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWloadidx", - argLen: 3, - asm: arm.AMOVW, + name: "VCVTTPD2UQQMasked128", + argLen: 2, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWloadshiftLL", - auxType: auxInt32, - argLen: 3, - asm: arm.AMOVW, + name: "VCVTTPD2UQQMasked256", + argLen: 2, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWloadshiftRL", - auxType: auxInt32, - argLen: 3, - asm: arm.AMOVW, + name: "VCVTTPD2UQQMasked512", + argLen: 2, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWloadshiftRA", - auxType: auxInt32, - argLen: 3, - asm: arm.AMOVW, + name: "VCVTTPS2DQ128", + argLen: 1, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUloadidx", - argLen: 3, - asm: arm.AMOVBU, + name: "VCVTTPS2DQ256", + argLen: 1, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBloadidx", - argLen: 3, - asm: arm.AMOVB, + name: "VCVTTPS2DQ512", + argLen: 1, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUloadidx", - argLen: 3, - asm: arm.AMOVHU, + name: "VCVTTPS2DQMasked128", + argLen: 2, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHloadidx", - argLen: 3, - asm: arm.AMOVH, + name: "VCVTTPS2DQMasked256", + argLen: 2, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstoreidx", - argLen: 4, - asm: arm.AMOVW, + name: "VCVTTPS2DQMasked512", + argLen: 2, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - }, - }, - { - name: "MOVWstoreshiftLL", - auxType: auxInt32, - argLen: 4, - asm: arm.AMOVW, - reg: regInfo{ - inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstoreshiftRL", - auxType: auxInt32, - argLen: 4, - asm: arm.AMOVW, + name: "VCVTTPS2QQ256", + argLen: 1, + asm: x86.AVCVTTPS2QQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstoreshiftRA", - auxType: auxInt32, - argLen: 4, - asm: arm.AMOVW, + name: "VCVTTPS2QQ512", + argLen: 1, + asm: x86.AVCVTTPS2QQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstoreidx", - argLen: 4, - asm: arm.AMOVB, + name: "VCVTTPS2QQMasked256", + argLen: 2, + asm: x86.AVCVTTPS2QQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstoreidx", - argLen: 4, - asm: arm.AMOVH, + name: "VCVTTPS2QQMasked512", + argLen: 2, + asm: x86.AVCVTTPS2QQ, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBreg", + name: "VCVTTPS2UDQ128", argLen: 1, - asm: arm.AMOVBS, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBUreg", + name: "VCVTTPS2UDQ256", argLen: 1, - asm: arm.AMOVBU, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHreg", + name: "VCVTTPS2UDQ512", argLen: 1, - asm: arm.AMOVHS, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: arm.AMOVHU, + name: "VCVTTPS2UDQMasked128", + argLen: 2, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: arm.AMOVW, + name: "VCVTTPS2UDQMasked256", + argLen: 2, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWnop", - argLen: 1, - resultInArg0: true, + name: "VCVTTPS2UDQMasked512", + argLen: 2, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWF", + name: "VCVTTPS2UQQ256", argLen: 1, - asm: arm.AMOVWF, + asm: x86.AVCVTTPS2UQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWD", + name: "VCVTTPS2UQQ512", argLen: 1, - asm: arm.AMOVWD, + asm: x86.AVCVTTPS2UQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUF", - argLen: 1, - asm: arm.AMOVWF, + name: "VCVTTPS2UQQMasked256", + argLen: 2, + asm: x86.AVCVTTPS2UQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUD", - argLen: 1, - asm: arm.AMOVWD, + name: "VCVTTPS2UQQMasked512", + argLen: 2, + asm: x86.AVCVTTPS2UQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFW", + name: "VCVTUDQ2PD256", argLen: 1, - asm: arm.AMOVFW, + asm: x86.AVCVTUDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDW", + name: "VCVTUDQ2PD512", argLen: 1, - asm: arm.AMOVDW, + asm: x86.AVCVTUDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFWU", - argLen: 1, - asm: arm.AMOVFW, + name: "VCVTUDQ2PDMasked256", + argLen: 2, + asm: x86.AVCVTUDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDWU", - argLen: 1, - asm: arm.AMOVDW, + name: "VCVTUDQ2PDMasked512", + argLen: 2, + asm: x86.AVCVTUDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFD", + name: "VCVTUDQ2PS128", argLen: 1, - asm: arm.AMOVFD, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDF", + name: "VCVTUDQ2PS256", argLen: 1, - asm: arm.AMOVDF, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMOVWHSconst", - auxType: auxInt32, - argLen: 2, - resultInArg0: true, - asm: arm.AMOVW, + name: "VCVTUDQ2PS512", + argLen: 1, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMOVWLSconst", - auxType: auxInt32, - argLen: 2, - resultInArg0: true, - asm: arm.AMOVW, + name: "VCVTUDQ2PSMasked128", + argLen: 2, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAcond", - argLen: 3, - asm: arm.ASRA, + name: "VCVTUDQ2PSMasked256", + argLen: 2, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - reg: regInfo{ - clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - }, - { - name: "CALLtail", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - tailCall: true, - reg: regInfo{ - clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - }, - { - name: "CALLclosure", - auxType: auxCallOff, - argLen: 3, - clobberFlags: true, - call: true, + name: "VCVTUDQ2PSMasked512", + argLen: 2, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {1, 128}, // R7 - {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - }, - { - name: "CALLinter", - auxType: auxCallOff, - argLen: 2, - clobberFlags: true, - call: true, - reg: regInfo{ - inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VCVTUQQ2PD128", + argLen: 1, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "Equal", + name: "VCVTUQQ2PD256", argLen: 1, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NotEqual", + name: "VCVTUQQ2PD512", argLen: 1, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LessThan", - argLen: 1, + name: "VCVTUQQ2PDMasked128", + argLen: 2, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LessEqual", - argLen: 1, + name: "VCVTUQQ2PDMasked256", + argLen: 2, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "GreaterThan", - argLen: 1, + name: "VCVTUQQ2PDMasked512", + argLen: 2, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "GreaterEqual", + name: "VCVTUQQ2PS256", argLen: 1, + asm: x86.AVCVTUQQ2PS, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LessThanU", - argLen: 1, + name: "VCVTUQQ2PSMasked256", + argLen: 2, + asm: x86.AVCVTUQQ2PS, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LessEqualU", + name: "VCVTUQQ2PSX128", argLen: 1, + asm: x86.AVCVTUQQ2PSX, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "GreaterThanU", - argLen: 1, + name: "VCVTUQQ2PSXMasked128", + argLen: 2, + asm: x86.AVCVTUQQ2PSX, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "GreaterEqualU", + name: "VCVTUQQ2PSY128", argLen: 1, + asm: x86.AVCVTUQQ2PSY, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DUFFZERO", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, + name: "VCVTUQQ2PSYMasked128", + argLen: 2, + asm: x86.AVCVTUQQ2PSY, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 1}, // R0 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 20482, // R1 R12 R14 }, }, { - name: "DUFFCOPY", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VDIVPD128", + argLen: 2, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 2}, // R1 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 20487, // R0 R1 R2 R12 R14 }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, + name: "VDIVPD256", + argLen: 2, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2, // R1 }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VDIVPD512", + argLen: 2, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 2}, // R1 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 6, // R1 R2 - }, - }, - { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, - reg: regInfo{ outputs: []outputInfo{ - {0, 128}, // R7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VDIVPDMasked128", + argLen: 3, + asm: x86.AVDIVPD, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VDIVPDMasked256", + argLen: 3, + asm: x86.AVDIVPD, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsRR", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VDIVPDMasked512", + argLen: 3, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 - {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsRC", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VDIVPS128", + argLen: 2, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicBoundsCR", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VDIVPS256", + argLen: 2, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicBoundsCC", - auxType: auxPanicBoundsCC, - argLen: 1, - call: true, - reg: regInfo{}, - }, - { - name: "LoweredPanicExtendRR", - auxType: auxInt64, - argLen: 4, - call: true, + name: "VDIVPS512", + argLen: 2, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 15}, // R0 R1 R2 R3 - {1, 15}, // R0 R1 R2 R3 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicExtendRC", - auxType: auxPanicBoundsC, - argLen: 3, - call: true, + name: "VDIVPSMasked128", + argLen: 3, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 15}, // R0 R1 R2 R3 - {1, 15}, // R0 R1 R2 R3 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - }, - }, - { - name: "FlagConstant", - auxType: auxFlagConstant, - argLen: 0, - reg: regInfo{}, - }, - { - name: "InvertFlags", - argLen: 1, - reg: regInfo{}, - }, - { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, - reg: regInfo{ - clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 outputs: []outputInfo{ - {0, 256}, // R8 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, - { - name: "ADCSflags", - argLen: 3, - commutative: true, - asm: arm64.AADCS, + name: "VDIVPSMasked256", + argLen: 3, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADCzerocarry", - argLen: 1, - asm: arm64.AADC, + name: "VDIVPSMasked512", + argLen: 3, + asm: x86.AVDIVPS, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADD", - argLen: 2, - commutative: true, - asm: arm64.AADD, + name: "VEXPANDPDMasked128", + argLen: 2, + asm: x86.AVEXPANDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AADD, + name: "VEXPANDPDMasked256", + argLen: 2, + asm: x86.AVEXPANDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1476395007}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDSconstflags", - auxType: auxInt64, - argLen: 1, - asm: arm64.AADDS, + name: "VEXPANDPDMasked512", + argLen: 2, + asm: x86.AVEXPANDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDSflags", - argLen: 2, - commutative: true, - asm: arm64.AADDS, + name: "VEXPANDPSMasked128", + argLen: 2, + asm: x86.AVEXPANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUB", + name: "VEXPANDPSMasked256", argLen: 2, - asm: arm64.ASUB, + asm: x86.AVEXPANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ASUB, + name: "VEXPANDPSMasked512", + argLen: 2, + asm: x86.AVEXPANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SBCSflags", - argLen: 3, - asm: arm64.ASBCS, + name: "VFMADD213PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSflags", - argLen: 2, - asm: arm64.ASUBS, + name: "VFMADD213PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MUL", - argLen: 2, - commutative: true, - asm: arm64.AMUL, + name: "VFMADD213PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULW", - argLen: 2, - commutative: true, - asm: arm64.AMULW, + name: "VFMADD213PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MNEG", - argLen: 2, - commutative: true, - asm: arm64.AMNEG, + name: "VFMADD213PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MNEGW", - argLen: 2, - commutative: true, - asm: arm64.AMNEGW, + name: "VFMADD213PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULH", - argLen: 2, - commutative: true, - asm: arm64.ASMULH, + name: "VFMADD213PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UMULH", - argLen: 2, - commutative: true, - asm: arm64.AUMULH, + name: "VFMADD213PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULL", - argLen: 2, - commutative: true, - asm: arm64.ASMULL, + name: "VFMADD213PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "UMULL", - argLen: 2, - commutative: true, - asm: arm64.AUMULL, + name: "VFMADD213PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIV", - argLen: 2, - asm: arm64.ASDIV, + name: "VFMADD213PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "UDIV", - argLen: 2, - asm: arm64.AUDIV, + name: "VFMADD213PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVW", - argLen: 2, - asm: arm64.ASDIVW, + name: "VFMADDSUB213PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UDIVW", - argLen: 2, - asm: arm64.AUDIVW, + name: "VFMADDSUB213PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOD", - argLen: 2, - asm: arm64.AREM, + name: "VFMADDSUB213PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "UMOD", - argLen: 2, - asm: arm64.AUREM, + name: "VFMADDSUB213PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MODW", - argLen: 2, - asm: arm64.AREMW, + name: "VFMADDSUB213PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "UMODW", - argLen: 2, - asm: arm64.AUREMW, + name: "VFMADDSUB213PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FADDS", - argLen: 2, - commutative: true, - asm: arm64.AFADDS, + name: "VFMADDSUB213PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FADDD", - argLen: 2, - commutative: true, - asm: arm64.AFADDD, + name: "VFMADDSUB213PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FSUBS", - argLen: 2, - asm: arm64.AFSUBS, + name: "VFMADDSUB213PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSUBD", - argLen: 2, - asm: arm64.AFSUBD, + name: "VFMADDSUB213PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMULS", - argLen: 2, - commutative: true, - asm: arm64.AFMULS, + name: "VFMADDSUB213PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMULD", - argLen: 2, - commutative: true, - asm: arm64.AFMULD, + name: "VFMADDSUB213PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNMULS", - argLen: 2, - commutative: true, - asm: arm64.AFNMULS, + name: "VFMSUBADD213PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMULD", - argLen: 2, - commutative: true, - asm: arm64.AFNMULD, + name: "VFMSUBADD213PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FDIVS", - argLen: 2, - asm: arm64.AFDIVS, + name: "VFMSUBADD213PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FDIVD", - argLen: 2, - asm: arm64.AFDIVD, + name: "VFMSUBADD213PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: arm64.AAND, + name: "VFMSUBADD213PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AAND, + name: "VFMSUBADD213PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: arm64.AORR, + name: "VFMSUBADD213PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AORR, + name: "VFMSUBADD213PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: arm64.AEOR, + name: "VFMSUBADD213PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AEOR, + name: "VFMSUBADD213PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BIC", - argLen: 2, - asm: arm64.ABIC, + name: "VFMSUBADD213PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "EON", - argLen: 2, - asm: arm64.AEON, + name: "VFMSUBADD213PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORN", + name: "VGF2P8MULB128", argLen: 2, - asm: arm64.AORN, + asm: x86.AVGF2P8MULB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MVN", - argLen: 1, - asm: arm64.AMVN, + name: "VGF2P8MULB256", + argLen: 2, + asm: x86.AVGF2P8MULB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEG", - argLen: 1, - asm: arm64.ANEG, + name: "VGF2P8MULB512", + argLen: 2, + asm: x86.AVGF2P8MULB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGSflags", - argLen: 1, - asm: arm64.ANEGS, + name: "VGF2P8MULBMasked128", + argLen: 3, + asm: x86.AVGF2P8MULB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NGCzerocarry", - argLen: 1, - asm: arm64.ANGC, + name: "VGF2P8MULBMasked256", + argLen: 3, + asm: x86.AVGF2P8MULB, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FABSD", - argLen: 1, - asm: arm64.AFABSD, + name: "VGF2P8MULBMasked512", + argLen: 3, + asm: x86.AVGF2P8MULB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNEGS", - argLen: 1, - asm: arm64.AFNEGS, + name: "VHADDPD128", + argLen: 2, + asm: x86.AVHADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNEGD", - argLen: 1, - asm: arm64.AFNEGD, + name: "VHADDPD256", + argLen: 2, + asm: x86.AVHADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FSQRTD", - argLen: 1, - asm: arm64.AFSQRTD, + name: "VHADDPS128", + argLen: 2, + asm: x86.AVHADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FSQRTS", - argLen: 1, - asm: arm64.AFSQRTS, + name: "VHADDPS256", + argLen: 2, + asm: x86.AVHADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMIND", + name: "VHSUBPD128", argLen: 2, - asm: arm64.AFMIND, + asm: x86.AVHSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMINS", + name: "VHSUBPD256", argLen: 2, - asm: arm64.AFMINS, + asm: x86.AVHSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMAXD", + name: "VHSUBPS128", argLen: 2, - asm: arm64.AFMAXD, + asm: x86.AVHSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMAXS", + name: "VHSUBPS256", argLen: 2, - asm: arm64.AFMAXS, + asm: x86.AVHSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REV", - argLen: 1, - asm: arm64.AREV, + name: "VMAXPD128", + argLen: 2, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REVW", - argLen: 1, - asm: arm64.AREVW, + name: "VMAXPD256", + argLen: 2, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REV16", - argLen: 1, - asm: arm64.AREV16, + name: "VMAXPD512", + argLen: 2, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "REV16W", - argLen: 1, - asm: arm64.AREV16W, + name: "VMAXPDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RBIT", - argLen: 1, - asm: arm64.ARBIT, + name: "VMAXPDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RBITW", - argLen: 1, - asm: arm64.ARBITW, + name: "VMAXPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CLZ", - argLen: 1, - asm: arm64.ACLZ, + name: "VMAXPS128", + argLen: 2, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLZW", - argLen: 1, - asm: arm64.ACLZW, + name: "VMAXPS256", + argLen: 2, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "VCNT", - argLen: 1, - asm: arm64.AVCNT, + name: "VMAXPS512", + argLen: 2, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "VUADDLV", - argLen: 1, - asm: arm64.AVUADDLV, + name: "VMAXPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredRound32F", - argLen: 1, - resultInArg0: true, - zeroWidth: true, + name: "VMAXPSMasked256", + argLen: 3, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredRound64F", - argLen: 1, - resultInArg0: true, - zeroWidth: true, + name: "VMAXPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMADDS", - argLen: 3, - asm: arm64.AFMADDS, + name: "VMINPD128", + argLen: 2, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMADDD", - argLen: 3, - asm: arm64.AFMADDD, + name: "VMINPD256", + argLen: 2, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMADDS", - argLen: 3, - asm: arm64.AFNMADDS, + name: "VMINPD512", + argLen: 2, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNMADDD", - argLen: 3, - asm: arm64.AFNMADDD, + name: "VMINPDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMSUBS", - argLen: 3, - asm: arm64.AFMSUBS, + name: "VMINPDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMSUBD", - argLen: 3, - asm: arm64.AFMSUBD, + name: "VMINPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNMSUBS", - argLen: 3, - asm: arm64.AFNMSUBS, + name: "VMINPS128", + argLen: 2, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMSUBD", - argLen: 3, - asm: arm64.AFNMSUBD, + name: "VMINPS256", + argLen: 2, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MADD", - argLen: 3, - asm: arm64.AMADD, + name: "VMINPS512", + argLen: 2, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MADDW", - argLen: 3, - asm: arm64.AMADDW, + name: "VMINPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MSUB", - argLen: 3, - asm: arm64.AMSUB, + name: "VMINPSMasked256", + argLen: 3, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MSUBW", - argLen: 3, - asm: arm64.AMSUBW, + name: "VMINPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLL", + name: "VMOVDQU8Masked128", argLen: 2, - asm: arm64.ALSL, + asm: x86.AVMOVDQU8, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLLconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ALSL, + name: "VMOVDQU8Masked256", + argLen: 2, + asm: x86.AVMOVDQU8, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRL", + name: "VMOVDQU8Masked512", argLen: 2, - asm: arm64.ALSR, + asm: x86.AVMOVDQU8, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRLconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ALSR, + name: "VMOVDQU16Masked128", + argLen: 2, + asm: x86.AVMOVDQU16, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRA", + name: "VMOVDQU16Masked256", argLen: 2, - asm: arm64.AASR, + asm: x86.AVMOVDQU16, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AASR, + name: "VMOVDQU16Masked512", + argLen: 2, + asm: x86.AVMOVDQU16, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ROR", + name: "VMOVDQU32Masked128", argLen: 2, - asm: arm64.AROR, + asm: x86.AVMOVDQU32, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RORW", + name: "VMOVDQU32Masked256", argLen: 2, - asm: arm64.ARORW, + asm: x86.AVMOVDQU32, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RORconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AROR, + name: "VMOVDQU32Masked512", + argLen: 2, + asm: x86.AVMOVDQU32, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RORWconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ARORW, + name: "VMOVDQU64Masked128", + argLen: 2, + asm: x86.AVMOVDQU64, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "EXTRconst", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEXTR, + name: "VMOVDQU64Masked256", + argLen: 2, + asm: x86.AVMOVDQU64, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "EXTRWconst", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEXTRW, + name: "VMOVDQU64Masked512", + argLen: 2, + asm: x86.AVMOVDQU64, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMP", - argLen: 2, - asm: arm64.ACMP, + name: "VMULPD128", + argLen: 2, + commutative: true, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ACMP, + name: "VMULPD256", + argLen: 2, + commutative: true, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPW", - argLen: 2, - asm: arm64.ACMPW, + name: "VMULPD512", + argLen: 2, + commutative: true, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPWconst", - auxType: auxInt32, - argLen: 1, - asm: arm64.ACMPW, + name: "VMULPDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMN", - argLen: 2, + name: "VMULPDMasked256", + argLen: 3, commutative: true, - asm: arm64.ACMN, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMNconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ACMN, + name: "VMULPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMNW", + name: "VMULPS128", argLen: 2, commutative: true, - asm: arm64.ACMNW, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNWconst", - auxType: auxInt32, - argLen: 1, - asm: arm64.ACMNW, + name: "VMULPS256", + argLen: 2, + commutative: true, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TST", + name: "VMULPS512", argLen: 2, commutative: true, - asm: arm64.ATST, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ATST, + name: "VMULPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTW", - argLen: 2, + name: "VMULPSMasked256", + argLen: 3, commutative: true, - asm: arm64.ATSTW, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTWconst", - auxType: auxInt32, - argLen: 1, - asm: arm64.ATSTW, + name: "VMULPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCMPS", - argLen: 2, - asm: arm64.AFCMPS, + name: "VPABSB128", + argLen: 1, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCMPD", - argLen: 2, - asm: arm64.AFCMPD, + name: "VPABSB256", + argLen: 1, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCMPS0", + name: "VPABSB512", argLen: 1, - asm: arm64.AFCMPS, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCMPD0", - argLen: 1, - asm: arm64.AFCMPD, + name: "VPABSBMasked128", + argLen: 2, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MVNshiftLL", - auxType: auxInt64, - argLen: 1, - asm: arm64.AMVN, + name: "VPABSBMasked256", + argLen: 2, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MVNshiftRL", - auxType: auxInt64, - argLen: 1, - asm: arm64.AMVN, + name: "VPABSBMasked512", + argLen: 2, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MVNshiftRA", - auxType: auxInt64, - argLen: 1, - asm: arm64.AMVN, + name: "VPABSD128", + argLen: 1, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftRO", - auxType: auxInt64, - argLen: 1, - asm: arm64.AMVN, + name: "VPABSD256", + argLen: 1, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGshiftLL", - auxType: auxInt64, - argLen: 1, - asm: arm64.ANEG, + name: "VPABSD512", + argLen: 1, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGshiftRL", - auxType: auxInt64, - argLen: 1, - asm: arm64.ANEG, + name: "VPABSDMasked128", + argLen: 2, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGshiftRA", - auxType: auxInt64, - argLen: 1, - asm: arm64.ANEG, + name: "VPABSDMasked256", + argLen: 2, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AADD, + name: "VPABSDMasked512", + argLen: 2, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AADD, + name: "VPABSQ128", + argLen: 1, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AADD, + name: "VPABSQ256", + argLen: 1, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ASUB, + name: "VPABSQ512", + argLen: 1, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ASUB, + name: "VPABSQMasked128", + argLen: 2, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.ASUB, + name: "VPABSQMasked256", + argLen: 2, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AAND, + name: "VPABSQMasked512", + argLen: 2, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AAND, + name: "VPABSW128", + argLen: 1, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AAND, + name: "VPABSW256", + argLen: 1, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.AAND, + name: "VPABSW512", + argLen: 1, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORR, + name: "VPABSWMasked128", + argLen: 2, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORR, + name: "VPABSWMasked256", + argLen: 2, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORR, + name: "VPABSWMasked512", + argLen: 2, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORR, + name: "VPACKSSDW128", + argLen: 2, + asm: x86.AVPACKSSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEOR, + name: "VPACKSSDW256", + argLen: 2, + asm: x86.AVPACKSSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEOR, + name: "VPACKSSDW512", + argLen: 2, + asm: x86.AVPACKSSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEOR, + name: "VPACKSSDWMasked128", + argLen: 3, + asm: x86.AVPACKSSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEOR, + name: "VPACKSSDWMasked256", + argLen: 3, + asm: x86.AVPACKSSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BICshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ABIC, + name: "VPACKSSDWMasked512", + argLen: 3, + asm: x86.AVPACKSSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BICshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ABIC, + name: "VPACKUSDW128", + argLen: 2, + asm: x86.AVPACKUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.ABIC, + name: "VPACKUSDW256", + argLen: 2, + asm: x86.AVPACKUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.ABIC, + name: "VPACKUSDW512", + argLen: 2, + asm: x86.AVPACKUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "EONshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEON, + name: "VPACKUSDWMasked128", + argLen: 3, + asm: x86.AVPACKUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "EONshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEON, + name: "VPACKUSDWMasked256", + argLen: 3, + asm: x86.AVPACKUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "EONshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEON, + name: "VPACKUSDWMasked512", + argLen: 3, + asm: x86.AVPACKUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "EONshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEON, + name: "VPADDB128", + argLen: 2, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORNshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORN, + name: "VPADDB256", + argLen: 2, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORNshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORN, + name: "VPADDB512", + argLen: 2, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORNshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORN, + name: "VPADDBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORNshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORN, + name: "VPADDBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMP, + name: "VPADDBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMP, + name: "VPADDD128", + argLen: 2, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMP, + name: "VPADDD256", + argLen: 2, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMN, + name: "VPADDD512", + argLen: 2, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMNshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMN, + name: "VPADDDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMNshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMN, + name: "VPADDDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ATST, + name: "VPADDDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TSTshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ATST, + name: "VPADDQ128", + argLen: 2, + commutative: true, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.ATST, + name: "VPADDQ256", + argLen: 2, + commutative: true, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.ATST, + name: "VPADDQ512", + argLen: 2, + commutative: true, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BFI", - auxType: auxARM64BitField, - argLen: 2, - resultInArg0: true, - asm: arm64.ABFI, + name: "VPADDQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BFXIL", - auxType: auxARM64BitField, - argLen: 2, - resultInArg0: true, - asm: arm64.ABFXIL, + name: "VPADDQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SBFIZ", - auxType: auxARM64BitField, - argLen: 1, - asm: arm64.ASBFIZ, + name: "VPADDQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SBFX", - auxType: auxARM64BitField, - argLen: 1, - asm: arm64.ASBFX, + name: "VPADDSB128", + argLen: 2, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UBFIZ", - auxType: auxARM64BitField, - argLen: 1, - asm: arm64.AUBFIZ, + name: "VPADDSB256", + argLen: 2, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UBFX", - auxType: auxARM64BitField, - argLen: 1, - asm: arm64.AUBFX, + name: "VPADDSB512", + argLen: 2, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: arm64.AMOVD, + name: "VPADDSBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: arm64.AFMOVS, + name: "VPADDSBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: arm64.AFMOVD, + name: "VPADDSBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: arm64.AMOVD, + name: "VPADDSW128", + argLen: 2, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517632}, // SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVB, + name: "VPADDSW256", + argLen: 2, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVBU, + name: "VPADDSW512", + argLen: 2, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVH, + name: "VPADDSWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVHU, + name: "VPADDSWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVW, + name: "VPADDSWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVWU, + name: "VPADDUSB128", + argLen: 2, + commutative: true, + asm: x86.AVPADDUSB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVD, + name: "VPADDUSB256", + argLen: 2, + commutative: true, + asm: x86.AVPADDUSB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AFMOVS, + name: "VPADDUSB512", + argLen: 2, + commutative: true, + asm: x86.AVPADDUSB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AFMOVD, + name: "VPADDUSBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDUSB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LDP", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.ALDP, + name: "VPADDUSBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDUSB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LDPW", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.ALDPW, + name: "VPADDUSBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDUSB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LDPSW", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.ALDPSW, + name: "VPADDUSW128", + argLen: 2, + commutative: true, + asm: x86.AVPADDUSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FLDPD", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AFLDPD, + name: "VPADDUSW256", + argLen: 2, + commutative: true, + asm: x86.AVPADDUSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FLDPS", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AFLDPS, + name: "VPADDUSW512", + argLen: 2, + commutative: true, + asm: x86.AVPADDUSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDloadidx", - argLen: 3, - asm: arm64.AMOVD, + name: "VPADDUSWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDUSW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWloadidx", - argLen: 3, - asm: arm64.AMOVW, + name: "VPADDUSWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDUSW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUloadidx", - argLen: 3, - asm: arm64.AMOVWU, + name: "VPADDUSWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDUSW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHloadidx", - argLen: 3, - asm: arm64.AMOVH, + name: "VPADDW128", + argLen: 2, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUloadidx", - argLen: 3, - asm: arm64.AMOVHU, + name: "VPADDW256", + argLen: 2, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBloadidx", - argLen: 3, - asm: arm64.AMOVB, + name: "VPADDW512", + argLen: 2, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBUloadidx", - argLen: 3, - asm: arm64.AMOVBU, + name: "VPADDWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSloadidx", - argLen: 3, - asm: arm64.AFMOVS, + name: "VPADDWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDloadidx", - argLen: 3, - asm: arm64.AFMOVD, + name: "VPADDWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHloadidx2", - argLen: 3, - asm: arm64.AMOVH, + name: "VPAND128", + argLen: 2, + commutative: true, + asm: x86.AVPAND, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUloadidx2", - argLen: 3, - asm: arm64.AMOVHU, + name: "VPAND256", + argLen: 2, + commutative: true, + asm: x86.AVPAND, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWloadidx4", - argLen: 3, - asm: arm64.AMOVW, + name: "VPANDD512", + argLen: 2, + commutative: true, + asm: x86.AVPANDD, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUloadidx4", - argLen: 3, - asm: arm64.AMOVWU, + name: "VPANDDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPANDD, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDloadidx8", - argLen: 3, - asm: arm64.AMOVD, + name: "VPANDDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPANDD, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSloadidx4", - argLen: 3, - asm: arm64.AFMOVS, + name: "VPANDDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPANDD, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDloadidx8", - argLen: 3, - asm: arm64.AFMOVD, + name: "VPANDN128", + argLen: 2, + asm: x86.AVPANDN, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AMOVB, + name: "VPANDN256", + argLen: 2, + asm: x86.AVPANDN, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AMOVH, + name: "VPANDND512", + argLen: 2, + asm: x86.AVPANDND, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AMOVW, + name: "VPANDNDMasked128", + argLen: 3, + asm: x86.AVPANDND, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AMOVD, + name: "VPANDNDMasked256", + argLen: 3, + asm: x86.AVPANDND, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AFMOVS, + name: "VPANDNDMasked512", + argLen: 3, + asm: x86.AVPANDND, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AFMOVD, + name: "VPANDNQ512", + argLen: 2, + asm: x86.AVPANDNQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "STP", - auxType: auxSymOff, - argLen: 4, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.ASTP, + name: "VPANDNQMasked128", + argLen: 3, + asm: x86.AVPANDNQ, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "STPW", - auxType: auxSymOff, - argLen: 4, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.ASTPW, + name: "VPANDNQMasked256", + argLen: 3, + asm: x86.AVPANDNQ, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSTPD", - auxType: auxSymOff, - argLen: 4, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AFSTPD, + name: "VPANDNQMasked512", + argLen: 3, + asm: x86.AVPANDNQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSTPS", - auxType: auxSymOff, - argLen: 4, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AFSTPS, + name: "VPANDQ512", + argLen: 2, + commutative: true, + asm: x86.AVPANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstoreidx", - argLen: 4, - asm: arm64.AMOVB, + name: "VPANDQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPANDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstoreidx", - argLen: 4, - asm: arm64.AMOVH, + name: "VPANDQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPANDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstoreidx", - argLen: 4, - asm: arm64.AMOVW, + name: "VPANDQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPANDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstoreidx", - argLen: 4, - asm: arm64.AMOVD, + name: "VPAVGB128", + argLen: 2, + commutative: true, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSstoreidx", - argLen: 4, - asm: arm64.AFMOVS, + name: "VPAVGB256", + argLen: 2, + commutative: true, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDstoreidx", - argLen: 4, - asm: arm64.AFMOVD, + name: "VPAVGB512", + argLen: 2, + commutative: true, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstoreidx2", - argLen: 4, - asm: arm64.AMOVH, + name: "VPAVGBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstoreidx4", - argLen: 4, - asm: arm64.AMOVW, + name: "VPAVGBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstoreidx8", - argLen: 4, - asm: arm64.AMOVD, + name: "VPAVGBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSstoreidx4", - argLen: 4, - asm: arm64.AFMOVS, + name: "VPAVGW128", + argLen: 2, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDstoreidx8", - argLen: 4, - asm: arm64.AFMOVD, + name: "VPAVGW256", + argLen: 2, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDgpfp", - argLen: 1, - asm: arm64.AFMOVD, + name: "VPAVGW512", + argLen: 2, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDfpgp", - argLen: 1, - asm: arm64.AFMOVD, + name: "VPAVGWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSgpfp", - argLen: 1, - asm: arm64.AFMOVS, + name: "VPAVGWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSfpgp", - argLen: 1, - asm: arm64.AFMOVS, + name: "VPAVGWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: arm64.AMOVB, + name: "VPBLENDMBMasked512", + argLen: 3, + asm: x86.AVPBLENDMB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBUreg", - argLen: 1, - asm: arm64.AMOVBU, + name: "VPBLENDMDMasked512", + argLen: 3, + asm: x86.AVPBLENDMD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: arm64.AMOVH, + name: "VPBLENDMQMasked512", + argLen: 3, + asm: x86.AVPBLENDMQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: arm64.AMOVHU, + name: "VPBLENDMWMasked512", + argLen: 3, + asm: x86.AVPBLENDMW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: arm64.AMOVW, + name: "VPBLENDVB128", + argLen: 3, + asm: x86.AVPBLENDVB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWUreg", - argLen: 1, - asm: arm64.AMOVWU, + name: "VPBLENDVB256", + argLen: 3, + asm: x86.AVPBLENDVB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDreg", + name: "VPBROADCASTB128", argLen: 1, - asm: arm64.AMOVD, + asm: x86.AVPBROADCASTB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDnop", - argLen: 1, - resultInArg0: true, + name: "VPBROADCASTB256", + argLen: 1, + asm: x86.AVPBROADCASTB, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SCVTFWS", + name: "VPBROADCASTB512", argLen: 1, - asm: arm64.ASCVTFWS, + asm: x86.AVPBROADCASTB, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SCVTFWD", - argLen: 1, - asm: arm64.ASCVTFWD, + name: "VPBROADCASTBMasked128", + argLen: 2, + asm: x86.AVPBROADCASTB, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "UCVTFWS", - argLen: 1, - asm: arm64.AUCVTFWS, + name: "VPBROADCASTBMasked256", + argLen: 2, + asm: x86.AVPBROADCASTB, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "UCVTFWD", - argLen: 1, - asm: arm64.AUCVTFWD, + name: "VPBROADCASTBMasked512", + argLen: 2, + asm: x86.AVPBROADCASTB, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SCVTFS", + name: "VPBROADCASTD128", argLen: 1, - asm: arm64.ASCVTFS, + asm: x86.AVPBROADCASTD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SCVTFD", + name: "VPBROADCASTD256", argLen: 1, - asm: arm64.ASCVTFD, + asm: x86.AVPBROADCASTD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UCVTFS", + name: "VPBROADCASTD512", argLen: 1, - asm: arm64.AUCVTFS, + asm: x86.AVPBROADCASTD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "UCVTFD", - argLen: 1, - asm: arm64.AUCVTFD, + name: "VPBROADCASTDMasked128", + argLen: 2, + asm: x86.AVPBROADCASTD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTZSSW", - argLen: 1, - asm: arm64.AFCVTZSSW, + name: "VPBROADCASTDMasked256", + argLen: 2, + asm: x86.AVPBROADCASTD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTZSDW", - argLen: 1, - asm: arm64.AFCVTZSDW, + name: "VPBROADCASTDMasked512", + argLen: 2, + asm: x86.AVPBROADCASTD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTZUSW", + name: "VPBROADCASTQ128", argLen: 1, - asm: arm64.AFCVTZUSW, + asm: x86.AVPBROADCASTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTZUDW", + name: "VPBROADCASTQ256", argLen: 1, - asm: arm64.AFCVTZUDW, + asm: x86.AVPBROADCASTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTZSS", + name: "VPBROADCASTQ512", argLen: 1, - asm: arm64.AFCVTZSS, + asm: x86.AVPBROADCASTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTZSD", - argLen: 1, - asm: arm64.AFCVTZSD, + name: "VPBROADCASTQMasked128", + argLen: 2, + asm: x86.AVPBROADCASTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTZUS", - argLen: 1, - asm: arm64.AFCVTZUS, + name: "VPBROADCASTQMasked256", + argLen: 2, + asm: x86.AVPBROADCASTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTZUD", - argLen: 1, - asm: arm64.AFCVTZUD, + name: "VPBROADCASTQMasked512", + argLen: 2, + asm: x86.AVPBROADCASTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTSD", + name: "VPBROADCASTW128", argLen: 1, - asm: arm64.AFCVTSD, + asm: x86.AVPBROADCASTW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTDS", + name: "VPBROADCASTW256", argLen: 1, - asm: arm64.AFCVTDS, + asm: x86.AVPBROADCASTW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FRINTAD", + name: "VPBROADCASTW512", argLen: 1, - asm: arm64.AFRINTAD, + asm: x86.AVPBROADCASTW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FRINTMD", - argLen: 1, - asm: arm64.AFRINTMD, + name: "VPBROADCASTWMasked128", + argLen: 2, + asm: x86.AVPBROADCASTW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FRINTND", - argLen: 1, - asm: arm64.AFRINTND, + name: "VPBROADCASTWMasked256", + argLen: 2, + asm: x86.AVPBROADCASTW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FRINTPD", - argLen: 1, - asm: arm64.AFRINTPD, + name: "VPBROADCASTWMasked512", + argLen: 2, + asm: x86.AVPBROADCASTW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FRINTZD", - argLen: 1, - asm: arm64.AFRINTZD, + name: "VPCMPEQB128", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CSEL", - auxType: auxCCop, - argLen: 3, - asm: arm64.ACSEL, + name: "VPCMPEQB256", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CSEL0", - auxType: auxCCop, - argLen: 2, - asm: arm64.ACSEL, + name: "VPCMPEQB512", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CSINC", - auxType: auxCCop, - argLen: 3, - asm: arm64.ACSINC, + name: "VPCMPEQD128", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CSINV", - auxType: auxCCop, - argLen: 3, - asm: arm64.ACSINV, + name: "VPCMPEQD256", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CSNEG", - auxType: auxCCop, - argLen: 3, - asm: arm64.ACSNEG, + name: "VPCMPEQD512", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CSETM", - auxType: auxCCop, - argLen: 1, - asm: arm64.ACSETM, + name: "VPCMPEQQ128", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQQ, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CCMP", - auxType: auxARM64ConditionalParams, - argLen: 3, - asm: arm64.ACCMP, + name: "VPCMPEQQ256", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CCMN", - auxType: auxARM64ConditionalParams, - argLen: 3, - asm: arm64.ACCMN, + name: "VPCMPEQQ512", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CCMPconst", - auxType: auxARM64ConditionalParams, - argLen: 2, - asm: arm64.ACCMP, + name: "VPCMPEQW128", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CCMNconst", - auxType: auxARM64ConditionalParams, - argLen: 2, - asm: arm64.ACCMN, + name: "VPCMPEQW256", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CCMPW", - auxType: auxARM64ConditionalParams, - argLen: 3, - asm: arm64.ACCMPW, + name: "VPCMPEQW512", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CCMNW", - auxType: auxARM64ConditionalParams, - argLen: 3, - asm: arm64.ACCMNW, + name: "VPCMPGTB128", + argLen: 2, + asm: x86.AVPCMPGTB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CCMPWconst", - auxType: auxARM64ConditionalParams, - argLen: 2, - asm: arm64.ACCMPW, + name: "VPCMPGTB256", + argLen: 2, + asm: x86.AVPCMPGTB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CCMNWconst", - auxType: auxARM64ConditionalParams, - argLen: 2, - asm: arm64.ACCMNW, + name: "VPCMPGTB512", + argLen: 2, + asm: x86.AVPCMPGTB, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, - reg: regInfo{ - clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, - { - name: "CALLtail", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, - tailCall: true, + name: "VPCMPGTD128", + argLen: 2, + asm: x86.AVPCMPGTD, reg: regInfo{ - clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPCMPGTD256", + argLen: 2, + asm: x86.AVPCMPGTD, reg: regInfo{ inputs: []inputInfo{ - {1, 33554432}, // R26 - {0, 1409286143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPCMPGTD512", + argLen: 2, + asm: x86.AVPCMPGTD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, - clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VPCMPGTQ128", + argLen: 2, + asm: x86.AVPCMPGTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "Equal", - argLen: 1, + name: "VPCMPGTQ256", + argLen: 2, + asm: x86.AVPCMPGTQ, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NotEqual", - argLen: 1, + name: "VPCMPGTQ512", + argLen: 2, + asm: x86.AVPCMPGTQ, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LessThan", - argLen: 1, + name: "VPCMPGTW128", + argLen: 2, + asm: x86.AVPCMPGTW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessEqual", - argLen: 1, + name: "VPCMPGTW256", + argLen: 2, + asm: x86.AVPCMPGTW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterThan", - argLen: 1, + name: "VPCMPGTW512", + argLen: 2, + asm: x86.AVPCMPGTW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "GreaterEqual", - argLen: 1, + name: "VPCOMPRESSBMasked128", + argLen: 2, + asm: x86.AVPCOMPRESSB, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LessThanU", - argLen: 1, + name: "VPCOMPRESSBMasked256", + argLen: 2, + asm: x86.AVPCOMPRESSB, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LessEqualU", - argLen: 1, + name: "VPCOMPRESSBMasked512", + argLen: 2, + asm: x86.AVPCOMPRESSB, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "GreaterThanU", - argLen: 1, + name: "VPCOMPRESSDMasked128", + argLen: 2, + asm: x86.AVPCOMPRESSD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "GreaterEqualU", - argLen: 1, + name: "VPCOMPRESSDMasked256", + argLen: 2, + asm: x86.AVPCOMPRESSD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LessThanF", - argLen: 1, + name: "VPCOMPRESSDMasked512", + argLen: 2, + asm: x86.AVPCOMPRESSD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LessEqualF", - argLen: 1, + name: "VPCOMPRESSQMasked128", + argLen: 2, + asm: x86.AVPCOMPRESSQ, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "GreaterThanF", - argLen: 1, + name: "VPCOMPRESSQMasked256", + argLen: 2, + asm: x86.AVPCOMPRESSQ, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "GreaterEqualF", - argLen: 1, + name: "VPCOMPRESSQMasked512", + argLen: 2, + asm: x86.AVPCOMPRESSQ, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NotLessThanF", - argLen: 1, + name: "VPCOMPRESSWMasked128", + argLen: 2, + asm: x86.AVPCOMPRESSW, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NotLessEqualF", - argLen: 1, + name: "VPCOMPRESSWMasked256", + argLen: 2, + asm: x86.AVPCOMPRESSW, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NotGreaterThanF", - argLen: 1, + name: "VPCOMPRESSWMasked512", + argLen: 2, + asm: x86.AVPCOMPRESSW, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NotGreaterEqualF", - argLen: 1, + name: "VPDPWSSD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessThanNoov", - argLen: 1, + name: "VPDPWSSD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterEqualNoov", - argLen: 1, + name: "VPDPWSSD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 2, - faultOnNilArg0: true, + name: "VPDPWSSDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredZeroLoop", - auxType: auxInt64, - argLen: 2, - needIntTemp: true, - faultOnNilArg0: true, + name: "VPDPWSSDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbersArg0: true, }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPDPWSSDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ inputs: []inputInfo{ - {0, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30 - {1, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 422212481843200, // R25 F16 F17 }, }, { - name: "LoweredMoveLoop", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPERMB128", + argLen: 2, + asm: x86.AVPERMB, reg: regInfo{ inputs: []inputInfo{ - {0, 310378495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R26 R30 - {1, 310378495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R26 R30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 422212490231808, // R24 R25 F16 F17 - clobbersArg0: true, - clobbersArg1: true, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "VPERMB256", + argLen: 2, + asm: x86.AVPERMB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 33554432}, // R26 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VPERMB512", + argLen: 2, + asm: x86.AVPERMB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VPERMBMasked128", + argLen: 3, + asm: x86.AVPERMB, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FlagConstant", - auxType: auxFlagConstant, - argLen: 0, - reg: regInfo{}, - }, - { - name: "InvertFlags", - argLen: 1, - reg: regInfo{}, - }, - { - name: "LDAR", - argLen: 2, - faultOnNilArg0: true, - asm: arm64.ALDAR, + name: "VPERMBMasked256", + argLen: 3, + asm: x86.AVPERMB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LDARB", - argLen: 2, - faultOnNilArg0: true, - asm: arm64.ALDARB, + name: "VPERMBMasked512", + argLen: 3, + asm: x86.AVPERMB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LDARW", - argLen: 2, - faultOnNilArg0: true, - asm: arm64.ALDARW, + name: "VPERMD256", + argLen: 2, + asm: x86.AVPERMD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "STLRB", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: arm64.ASTLRB, + name: "VPERMD512", + argLen: 2, + asm: x86.AVPERMD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "STLR", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: arm64.ASTLR, + name: "VPERMDMasked256", + argLen: 3, + asm: x86.AVPERMD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "STLRW", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: arm64.ASTLRW, + name: "VPERMDMasked512", + argLen: 3, + asm: x86.AVPERMD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2B128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2B, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2B256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2B, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange8", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2B512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2B, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange64Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPERMI2BMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2B, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange32Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPERMI2BMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2B, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange8Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2BMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2B, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAdd64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2D128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2D, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAdd32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2D256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2D, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAdd64Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPERMI2D512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2D, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAdd32Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPERMI2DMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2D, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas64", - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2DMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2D, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas32", - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2DMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2D, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas64Variant", - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2PD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas32Variant", - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2PD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd8", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AAND, + name: "VPERMI2PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2PD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr8", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AORR, + name: "VPERMI2PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2PD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd64", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AAND, + name: "VPERMI2PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2PD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr64", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AORR, + name: "VPERMI2PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2PD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd32", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AAND, + name: "VPERMI2PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2PS, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr32", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AORR, + name: "VPERMI2PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2PS, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd8Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2PS, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr8Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPERMI2PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2PS, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd64Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2PS, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr64Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPERMI2PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2PS, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd32Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPERMI2Q128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2Q, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr32Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPERMI2Q256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2Q, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "VPERMI2Q512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2Q, reg: regInfo{ - clobbers: 9223372034975924224, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 16777216}, // R25 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsRR", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPERMI2QMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2Q, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 - {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsRC", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VPERMI2QMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2Q, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCR", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VPERMI2QMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2Q, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCC", - auxType: auxPanicBoundsCC, - argLen: 1, - call: true, - reg: regInfo{}, - }, - { - name: "PRFM", - auxType: auxInt64, - argLen: 2, - hasSideEffects: true, - asm: arm64.APRFM, + name: "VPERMI2W128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2W, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DMB", - auxType: auxInt64, - argLen: 1, - hasSideEffects: true, - asm: arm64.ADMB, - reg: regInfo{}, - }, - { - name: "ZERO", - argLen: 0, - zeroWidth: true, - fixedReg: true, - reg: regInfo{}, - }, - - { - name: "NEGV", - argLen: 1, + name: "VPERMI2W256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2W, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGF", - argLen: 1, - asm: loong64.ANEGF, + name: "VPERMI2W512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPERMI2W, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGD", - argLen: 1, - asm: loong64.ANEGD, + name: "VPERMI2WMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2W, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SQRTD", - argLen: 1, - asm: loong64.ASQRTD, + name: "VPERMI2WMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2W, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SQRTF", - argLen: 1, - asm: loong64.ASQRTF, + name: "VPERMI2WMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPERMI2W, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ABSD", - argLen: 1, - asm: loong64.AABSD, + name: "VPERMPD256", + argLen: 2, + asm: x86.AVPERMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CLZW", - argLen: 1, - asm: loong64.ACLZW, + name: "VPERMPD512", + argLen: 2, + asm: x86.AVPERMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CLZV", - argLen: 1, - asm: loong64.ACLZV, + name: "VPERMPDMasked256", + argLen: 3, + asm: x86.AVPERMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CTZW", - argLen: 1, - asm: loong64.ACTZW, + name: "VPERMPDMasked512", + argLen: 3, + asm: x86.AVPERMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CTZV", - argLen: 1, - asm: loong64.ACTZV, + name: "VPERMPS256", + argLen: 2, + asm: x86.AVPERMPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REVB2H", - argLen: 1, - asm: loong64.AREVB2H, + name: "VPERMPS512", + argLen: 2, + asm: x86.AVPERMPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "REVB2W", - argLen: 1, - asm: loong64.AREVB2W, + name: "VPERMPSMasked256", + argLen: 3, + asm: x86.AVPERMPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "REVB4H", - argLen: 1, - asm: loong64.AREVB4H, + name: "VPERMPSMasked512", + argLen: 3, + asm: x86.AVPERMPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "REVBV", - argLen: 1, - asm: loong64.AREVBV, + name: "VPERMQ256", + argLen: 2, + asm: x86.AVPERMQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BITREV4B", - argLen: 1, - asm: loong64.ABITREV4B, + name: "VPERMQ512", + argLen: 2, + asm: x86.AVPERMQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BITREVW", - argLen: 1, - asm: loong64.ABITREVW, + name: "VPERMQMasked256", + argLen: 3, + asm: x86.AVPERMQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BITREVV", - argLen: 1, - asm: loong64.ABITREVV, + name: "VPERMQMasked512", + argLen: 3, + asm: x86.AVPERMQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "VPCNT64", - argLen: 1, - asm: loong64.AVPCNTV, + name: "VPERMW128", + argLen: 2, + asm: x86.AVPERMW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "VPCNT32", - argLen: 1, - asm: loong64.AVPCNTW, + name: "VPERMW256", + argLen: 2, + asm: x86.AVPERMW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "VPCNT16", - argLen: 1, - asm: loong64.AVPCNTH, + name: "VPERMW512", + argLen: 2, + asm: x86.AVPERMW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDV", - argLen: 2, - commutative: true, - asm: loong64.AADDVU, + name: "VPERMWMasked128", + argLen: 3, + asm: x86.AVPERMW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AADDVU, + name: "VPERMWMasked256", + argLen: 3, + asm: x86.AVPERMW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDV16const", - auxType: auxInt64, - argLen: 1, - asm: loong64.AADDV16, + name: "VPERMWMasked512", + argLen: 3, + asm: x86.AVPERMW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBV", + name: "VPEXPANDBMasked128", argLen: 2, - asm: loong64.ASUBVU, + asm: x86.AVPEXPANDB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASUBVU, + name: "VPEXPANDBMasked256", + argLen: 2, + asm: x86.AVPEXPANDB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULV", - argLen: 2, - commutative: true, - asm: loong64.AMULV, + name: "VPEXPANDBMasked512", + argLen: 2, + asm: x86.AVPEXPANDB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULHV", - argLen: 2, - commutative: true, - asm: loong64.AMULHV, + name: "VPEXPANDDMasked128", + argLen: 2, + asm: x86.AVPEXPANDD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULHVU", - argLen: 2, - commutative: true, - asm: loong64.AMULHVU, + name: "VPEXPANDDMasked256", + argLen: 2, + asm: x86.AVPEXPANDD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULH", - argLen: 2, - commutative: true, - asm: loong64.AMULH, + name: "VPEXPANDDMasked512", + argLen: 2, + asm: x86.AVPEXPANDD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULHU", - argLen: 2, - commutative: true, - asm: loong64.AMULHU, + name: "VPEXPANDQMasked128", + argLen: 2, + asm: x86.AVPEXPANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVV", + name: "VPEXPANDQMasked256", argLen: 2, - asm: loong64.ADIVV, + asm: x86.AVPEXPANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVVU", + name: "VPEXPANDQMasked512", argLen: 2, - asm: loong64.ADIVVU, + asm: x86.AVPEXPANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "REMV", + name: "VPEXPANDWMasked128", argLen: 2, - asm: loong64.AREMV, + asm: x86.AVPEXPANDW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "REMVU", + name: "VPEXPANDWMasked256", argLen: 2, - asm: loong64.AREMVU, + asm: x86.AVPEXPANDW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDF", - argLen: 2, - commutative: true, - asm: loong64.AADDF, + name: "VPEXPANDWMasked512", + argLen: 2, + asm: x86.AVPEXPANDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDD", - argLen: 2, - commutative: true, - asm: loong64.AADDD, + name: "VPHADDD128", + argLen: 2, + asm: x86.AVPHADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBF", + name: "VPHADDD256", argLen: 2, - asm: loong64.ASUBF, + asm: x86.AVPHADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBD", + name: "VPHADDSW128", argLen: 2, - asm: loong64.ASUBD, + asm: x86.AVPHADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULF", - argLen: 2, - commutative: true, - asm: loong64.AMULF, + name: "VPHADDSW256", + argLen: 2, + asm: x86.AVPHADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULD", - argLen: 2, - commutative: true, - asm: loong64.AMULD, + name: "VPHADDW128", + argLen: 2, + asm: x86.AVPHADDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVF", + name: "VPHADDW256", argLen: 2, - asm: loong64.ADIVF, + asm: x86.AVPHADDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVD", + name: "VPHSUBD128", argLen: 2, - asm: loong64.ADIVD, + asm: x86.AVPHSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: loong64.AAND, + name: "VPHSUBD256", + argLen: 2, + asm: x86.AVPHSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AAND, + name: "VPHSUBSW128", + argLen: 2, + asm: x86.AVPHSUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: loong64.AOR, + name: "VPHSUBSW256", + argLen: 2, + asm: x86.AVPHSUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AOR, + name: "VPHSUBW128", + argLen: 2, + asm: x86.AVPHSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: loong64.AXOR, + name: "VPHSUBW256", + argLen: 2, + asm: x86.AVPHSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AXOR, + name: "VPLZCNTD128", + argLen: 1, + asm: x86.AVPLZCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NOR", - argLen: 2, - commutative: true, - asm: loong64.ANOR, + name: "VPLZCNTD256", + argLen: 1, + asm: x86.AVPLZCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NORconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ANOR, + name: "VPLZCNTD512", + argLen: 1, + asm: x86.AVPLZCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDN", + name: "VPLZCNTDMasked128", argLen: 2, - asm: loong64.AANDN, + asm: x86.AVPLZCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORN", + name: "VPLZCNTDMasked256", argLen: 2, - asm: loong64.AORN, + asm: x86.AVPLZCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMADDF", - argLen: 3, - commutative: true, - asm: loong64.AFMADDF, + name: "VPLZCNTDMasked512", + argLen: 2, + asm: x86.AVPLZCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMADDD", - argLen: 3, - commutative: true, - asm: loong64.AFMADDD, + name: "VPLZCNTQ128", + argLen: 1, + asm: x86.AVPLZCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMSUBF", - argLen: 3, - commutative: true, - asm: loong64.AFMSUBF, + name: "VPLZCNTQ256", + argLen: 1, + asm: x86.AVPLZCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMSUBD", - argLen: 3, - commutative: true, - asm: loong64.AFMSUBD, + name: "VPLZCNTQ512", + argLen: 1, + asm: x86.AVPLZCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNMADDF", - argLen: 3, - commutative: true, - asm: loong64.AFNMADDF, + name: "VPLZCNTQMasked128", + argLen: 2, + asm: x86.AVPLZCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNMADDD", - argLen: 3, - commutative: true, - asm: loong64.AFNMADDD, + name: "VPLZCNTQMasked256", + argLen: 2, + asm: x86.AVPLZCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNMSUBF", - argLen: 3, - commutative: true, - asm: loong64.AFNMSUBF, + name: "VPLZCNTQMasked512", + argLen: 2, + asm: x86.AVPLZCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNMSUBD", - argLen: 3, - commutative: true, - asm: loong64.AFNMSUBD, + name: "VPMADDUBSW128", + argLen: 2, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMINF", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: loong64.AFMINF, + name: "VPMADDUBSW256", + argLen: 2, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMIND", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: loong64.AFMIND, + name: "VPMADDUBSW512", + argLen: 2, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMAXF", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: loong64.AFMAXF, + name: "VPMADDUBSWMasked128", + argLen: 3, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMAXD", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: loong64.AFMAXD, + name: "VPMADDUBSWMasked256", + argLen: 3, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MASKEQZ", - argLen: 2, - asm: loong64.AMASKEQZ, + name: "VPMADDUBSWMasked512", + argLen: 3, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MASKNEZ", + name: "VPMADDWD128", argLen: 2, - asm: loong64.AMASKNEZ, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCOPYSGD", + name: "VPMADDWD256", argLen: 2, - asm: loong64.AFCOPYSGD, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLL", + name: "VPMADDWD512", argLen: 2, - asm: loong64.ASLL, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLLV", - argLen: 2, - asm: loong64.ASLLV, + name: "VPMADDWDMasked128", + argLen: 3, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLLconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASLL, + name: "VPMADDWDMasked256", + argLen: 3, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLLVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASLLV, + name: "VPMADDWDMasked512", + argLen: 3, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRL", - argLen: 2, - asm: loong64.ASRL, + name: "VPMAXSB128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLV", - argLen: 2, - asm: loong64.ASRLV, + name: "VPMAXSB256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASRL, + name: "VPMAXSB512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRLVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASRLV, + name: "VPMAXSBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRA", - argLen: 2, - asm: loong64.ASRA, + name: "VPMAXSBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAV", - argLen: 2, - asm: loong64.ASRAV, + name: "VPMAXSBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASRA, + name: "VPMAXSD128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRAVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASRAV, + name: "VPMAXSD256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ROTR", - argLen: 2, - asm: loong64.AROTR, + name: "VPMAXSD512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ROTRV", - argLen: 2, - asm: loong64.AROTRV, + name: "VPMAXSDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ROTRconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AROTR, + name: "VPMAXSDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ROTRVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AROTRV, + name: "VPMAXSDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SGT", - argLen: 2, - asm: loong64.ASGT, + name: "VPMAXSQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SGTconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASGT, + name: "VPMAXSQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SGTU", - argLen: 2, - asm: loong64.ASGTU, + name: "VPMAXSQ512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SGTUconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASGTU, + name: "VPMAXSQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPEQF", - argLen: 2, - asm: loong64.ACMPEQF, + name: "VPMAXSQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPEQD", - argLen: 2, - asm: loong64.ACMPEQD, + name: "VPMAXSQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPGEF", - argLen: 2, - asm: loong64.ACMPGEF, + name: "VPMAXSW128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPGED", - argLen: 2, - asm: loong64.ACMPGED, + name: "VPMAXSW256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPGTF", - argLen: 2, - asm: loong64.ACMPGTF, + name: "VPMAXSW512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPGTD", - argLen: 2, - asm: loong64.ACMPGTD, + name: "VPMAXSWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BSTRPICKW", - auxType: auxInt64, - argLen: 1, - asm: loong64.ABSTRPICKW, + name: "VPMAXSWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BSTRPICKV", - auxType: auxInt64, - argLen: 1, - asm: loong64.ABSTRPICKV, + name: "VPMAXSWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: loong64.AMOVV, + name: "VPMAXUB128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: loong64.AMOVF, + name: "VPMAXUB256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: loong64.AMOVD, + name: "VPMAXUB512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: loong64.AMOVV, + name: "VPMAXUBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018427387908}, // SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVB, + name: "VPMAXUBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVBU, + name: "VPMAXUBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVH, + name: "VPMAXUD128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVHU, + name: "VPMAXUD256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVW, + name: "VPMAXUD512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVWU, + name: "VPMAXUDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVV, + name: "VPMAXUDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVF, + name: "VPMAXUDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVD, + name: "VPMAXUQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVloadidx", - argLen: 3, - asm: loong64.AMOVV, + name: "VPMAXUQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWloadidx", - argLen: 3, - asm: loong64.AMOVW, + name: "VPMAXUQ512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUloadidx", - argLen: 3, - asm: loong64.AMOVWU, + name: "VPMAXUQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHloadidx", - argLen: 3, - asm: loong64.AMOVH, + name: "VPMAXUQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUloadidx", - argLen: 3, - asm: loong64.AMOVHU, + name: "VPMAXUQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBloadidx", - argLen: 3, - asm: loong64.AMOVB, + name: "VPMAXUW128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUloadidx", - argLen: 3, - asm: loong64.AMOVBU, + name: "VPMAXUW256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFloadidx", - argLen: 3, - asm: loong64.AMOVF, + name: "VPMAXUW512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDloadidx", - argLen: 3, - asm: loong64.AMOVD, + name: "VPMAXUWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVB, + name: "VPMAXUWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVH, + name: "VPMAXUWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVW, + name: "VPMINSB128", + argLen: 2, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVV, + name: "VPMINSB256", + argLen: 2, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVF, + name: "VPMINSB512", + argLen: 2, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVD, + name: "VPMINSBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstoreidx", - argLen: 4, - asm: loong64.AMOVB, + name: "VPMINSBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstoreidx", - argLen: 4, - asm: loong64.AMOVH, + name: "VPMINSBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstoreidx", - argLen: 4, - asm: loong64.AMOVW, + name: "VPMINSD128", + argLen: 2, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVstoreidx", - argLen: 4, - asm: loong64.AMOVV, + name: "VPMINSD256", + argLen: 2, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFstoreidx", - argLen: 4, - asm: loong64.AMOVF, + name: "VPMINSD512", + argLen: 2, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstoreidx", - argLen: 4, - asm: loong64.AMOVD, + name: "VPMINSDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWfpgp", - argLen: 1, - asm: loong64.AMOVW, + name: "VPMINSDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWgpfp", - argLen: 1, - asm: loong64.AMOVW, + name: "VPMINSDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ inputs: []inputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVfpgp", - argLen: 1, - asm: loong64.AMOVV, + name: "VPMINSQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVgpfp", - argLen: 1, - asm: loong64.AMOVV, + name: "VPMINSQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: loong64.AMOVB, + name: "VPMINSQ512", + argLen: 2, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBUreg", - argLen: 1, - asm: loong64.AMOVBU, + name: "VPMINSQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: loong64.AMOVH, + name: "VPMINSQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: loong64.AMOVHU, + name: "VPMINSQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: loong64.AMOVW, + name: "VPMINSW128", + argLen: 2, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWUreg", - argLen: 1, - asm: loong64.AMOVWU, + name: "VPMINSW256", + argLen: 2, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVreg", - argLen: 1, - asm: loong64.AMOVV, + name: "VPMINSW512", + argLen: 2, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVnop", - argLen: 1, - resultInArg0: true, + name: "VPMINSWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWF", - argLen: 1, - asm: loong64.AMOVWF, + name: "VPMINSWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWD", - argLen: 1, - asm: loong64.AMOVWD, + name: "VPMINSWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVF", - argLen: 1, - asm: loong64.AMOVVF, + name: "VPMINUB128", + argLen: 2, + commutative: true, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVD", - argLen: 1, - asm: loong64.AMOVVD, + name: "VPMINUB256", + argLen: 2, + commutative: true, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TRUNCFW", - argLen: 1, - asm: loong64.ATRUNCFW, + name: "VPMINUB512", + argLen: 2, + commutative: true, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TRUNCDW", - argLen: 1, - asm: loong64.ATRUNCDW, + name: "VPMINUBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TRUNCFV", - argLen: 1, - asm: loong64.ATRUNCFV, + name: "VPMINUBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TRUNCDV", - argLen: 1, - asm: loong64.ATRUNCDV, + name: "VPMINUBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFD", - argLen: 1, - asm: loong64.AMOVFD, + name: "VPMINUD128", + argLen: 2, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDF", - argLen: 1, - asm: loong64.AMOVDF, + name: "VPMINUD256", + argLen: 2, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredRound32F", - argLen: 1, - resultInArg0: true, + name: "VPMINUD512", + argLen: 2, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredRound64F", - argLen: 1, - resultInArg0: true, + name: "VPMINUDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPMINUDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ - clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, }, }, { - name: "CALLtail", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, - tailCall: true, + name: "VPMINUDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ - clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPMINUQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {1, 268435456}, // R29 - {0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPMINUQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 2, - faultOnNilArg0: true, + name: "VPMINUQ512", + argLen: 2, + commutative: true, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredZeroLoop", - auxType: auxInt64, - argLen: 2, - needIntTemp: true, - faultOnNilArg0: true, + name: "VPMINUQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbersArg0: true, }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPMINUQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1071120376}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R21 R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1071120376}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 524288, // R20 }, }, { - name: "LoweredMoveLoop", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPMINUQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1070071800}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1070071800}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 1572864, // R20 R21 - clobbersArg0: true, - clobbersArg1: true, }, }, { - name: "LoweredAtomicLoad8", - argLen: 2, - faultOnNilArg0: true, + name: "VPMINUW128", + argLen: 2, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicLoad32", - argLen: 2, - faultOnNilArg0: true, + name: "VPMINUW256", + argLen: 2, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicLoad64", - argLen: 2, - faultOnNilArg0: true, + name: "VPMINUW512", + argLen: 2, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMINUWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMINUWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore64", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMINUWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore8Variant", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVDB128_128", + argLen: 1, + asm: x86.AVPMOVDB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore32Variant", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVDB128_256", + argLen: 1, + asm: x86.AVPMOVDB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore64Variant", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVDB128_512", + argLen: 1, + asm: x86.AVPMOVDB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVDBMasked128_128", + argLen: 2, + asm: x86.AVPMOVDB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVDBMasked128_256", + argLen: 2, + asm: x86.AVPMOVDB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange8Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVDBMasked128_512", + argLen: 2, + asm: x86.AVPMOVDB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAdd32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVDW128_128", + argLen: 1, + asm: x86.AVPMOVDW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAdd64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVDW128_256", + argLen: 1, + asm: x86.AVPMOVDW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas32", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMOVDW256", + argLen: 1, + asm: x86.AVPMOVDW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas64", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMOVDWMasked128_128", + argLen: 2, + asm: x86.AVPMOVDW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas64Variant", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMOVDWMasked128_256", + argLen: 2, + asm: x86.AVPMOVDW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas32Variant", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMOVDWMasked256", + argLen: 2, + asm: x86.AVPMOVDW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMANDDBW, + name: "VPMOVQB128_128", + argLen: 1, + asm: x86.AVPMOVQB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMORDBW, + name: "VPMOVQB128_256", + argLen: 1, + asm: x86.AVPMOVQB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd32value", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMANDDBW, + name: "VPMOVQB128_512", + argLen: 1, + asm: x86.AVPMOVQB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd64value", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMANDDBV, + name: "VPMOVQBMasked128_128", + argLen: 2, + asm: x86.AVPMOVQB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr32value", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMORDBW, + name: "VPMOVQBMasked128_256", + argLen: 2, + asm: x86.AVPMOVQB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr64value", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMORDBV, + name: "VPMOVQBMasked128_512", + argLen: 2, + asm: x86.AVPMOVQB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VPMOVQD128_128", + argLen: 1, + asm: x86.AVPMOVQD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FPFlagTrue", + name: "VPMOVQD128_256", argLen: 1, + asm: x86.AVPMOVQD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FPFlagFalse", + name: "VPMOVQD256", argLen: 1, + asm: x86.AVPMOVQD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "VPMOVQDMasked128_128", + argLen: 2, + asm: x86.AVPMOVQD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 268435456}, // R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VPMOVQDMasked128_256", + argLen: 2, + asm: x86.AVPMOVQD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VPMOVQDMasked256", + argLen: 2, + asm: x86.AVPMOVQD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "VPMOVQW128_128", + argLen: 1, + asm: x86.AVPMOVQW, reg: regInfo{ - clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 268435456}, // R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPubBarrier", - argLen: 1, - hasSideEffects: true, - asm: loong64.ADBAR, - reg: regInfo{}, - }, - { - name: "LoweredPanicBoundsRR", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPMOVQW128_256", + argLen: 1, + asm: x86.AVPMOVQW, reg: regInfo{ inputs: []inputInfo{ - {0, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 - {1, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsRC", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VPMOVQW128_512", + argLen: 1, + asm: x86.AVPMOVQW, reg: regInfo{ inputs: []inputInfo{ - {0, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCR", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VPMOVQWMasked128_128", + argLen: 2, + asm: x86.AVPMOVQW, reg: regInfo{ inputs: []inputInfo{ - {0, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCC", - auxType: auxPanicBoundsCC, - argLen: 1, - call: true, - reg: regInfo{}, - }, - { - name: "PRELD", - auxType: auxInt64, - argLen: 2, - hasSideEffects: true, - asm: loong64.APRELD, + name: "VPMOVQWMasked128_256", + argLen: 2, + asm: x86.AVPMOVQW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "PRELDX", - auxType: auxInt64, - argLen: 2, - hasSideEffects: true, - asm: loong64.APRELDX, + name: "VPMOVQWMasked128_512", + argLen: 2, + asm: x86.AVPMOVQW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDshiftLLV", - auxType: auxInt64, - argLen: 2, - asm: loong64.AALSLV, + name: "VPMOVSDB128_128", + argLen: 1, + asm: x86.AVPMOVSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ZERO", - argLen: 0, - zeroWidth: true, - fixedReg: true, - reg: regInfo{}, - }, - - { - name: "ADD", - argLen: 2, - commutative: true, - asm: mips.AADDU, + name: "VPMOVSDB128_256", + argLen: 1, + asm: x86.AVPMOVSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDconst", - auxType: auxInt32, - argLen: 1, - asm: mips.AADDU, + name: "VPMOVSDB128_512", + argLen: 1, + asm: x86.AVPMOVSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUB", + name: "VPMOVSDBMasked128_128", argLen: 2, - asm: mips.ASUBU, + asm: x86.AVPMOVSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ASUBU, + name: "VPMOVSDBMasked128_256", + argLen: 2, + asm: x86.AVPMOVSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MUL", - argLen: 2, - commutative: true, - asm: mips.AMUL, + name: "VPMOVSDBMasked128_512", + argLen: 2, + asm: x86.AVPMOVSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 105553116266496, // HI LO outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULT", - argLen: 2, - commutative: true, - asm: mips.AMUL, + name: "VPMOVSDW128_128", + argLen: 1, + asm: x86.AVPMOVSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35184372088832}, // HI - {1, 70368744177664}, // LO + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULTU", - argLen: 2, - commutative: true, - asm: mips.AMULU, + name: "VPMOVSDW128_256", + argLen: 1, + asm: x86.AVPMOVSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35184372088832}, // HI - {1, 70368744177664}, // LO + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIV", - argLen: 2, - asm: mips.ADIV, + name: "VPMOVSDW256", + argLen: 1, + asm: x86.AVPMOVSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35184372088832}, // HI - {1, 70368744177664}, // LO + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVU", + name: "VPMOVSDWMasked128_128", argLen: 2, - asm: mips.ADIVU, + asm: x86.AVPMOVSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35184372088832}, // HI - {1, 70368744177664}, // LO + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDF", - argLen: 2, - commutative: true, - asm: mips.AADDF, + name: "VPMOVSDWMasked128_256", + argLen: 2, + asm: x86.AVPMOVSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDD", - argLen: 2, - commutative: true, - asm: mips.AADDD, + name: "VPMOVSDWMasked256", + argLen: 2, + asm: x86.AVPMOVSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBF", - argLen: 2, - asm: mips.ASUBF, + name: "VPMOVSQB128_128", + argLen: 1, + asm: x86.AVPMOVSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBD", - argLen: 2, - asm: mips.ASUBD, + name: "VPMOVSQB128_256", + argLen: 1, + asm: x86.AVPMOVSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULF", - argLen: 2, - commutative: true, - asm: mips.AMULF, + name: "VPMOVSQB128_512", + argLen: 1, + asm: x86.AVPMOVSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULD", - argLen: 2, - commutative: true, - asm: mips.AMULD, + name: "VPMOVSQBMasked128_128", + argLen: 2, + asm: x86.AVPMOVSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVF", + name: "VPMOVSQBMasked128_256", argLen: 2, - asm: mips.ADIVF, + asm: x86.AVPMOVSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVD", + name: "VPMOVSQBMasked128_512", argLen: 2, - asm: mips.ADIVD, + asm: x86.AVPMOVSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: mips.AAND, + name: "VPMOVSQD128_128", + argLen: 1, + asm: x86.AVPMOVSQD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDconst", - auxType: auxInt32, - argLen: 1, - asm: mips.AAND, + name: "VPMOVSQD128_256", + argLen: 1, + asm: x86.AVPMOVSQD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: mips.AOR, + name: "VPMOVSQD256", + argLen: 1, + asm: x86.AVPMOVSQD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORconst", - auxType: auxInt32, - argLen: 1, - asm: mips.AOR, + name: "VPMOVSQDMasked128_128", + argLen: 2, + asm: x86.AVPMOVSQD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: mips.AXOR, + name: "VPMOVSQDMasked128_256", + argLen: 2, + asm: x86.AVPMOVSQD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORconst", - auxType: auxInt32, - argLen: 1, - asm: mips.AXOR, + name: "VPMOVSQDMasked256", + argLen: 2, + asm: x86.AVPMOVSQD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NOR", - argLen: 2, - commutative: true, - asm: mips.ANOR, + name: "VPMOVSQW128_128", + argLen: 1, + asm: x86.AVPMOVSQW, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NORconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ANOR, + name: "VPMOVSQW128_256", + argLen: 1, + asm: x86.AVPMOVSQW, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEG", + name: "VPMOVSQW128_512", argLen: 1, + asm: x86.AVPMOVSQW, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGF", - argLen: 1, - asm: mips.ANEGF, + name: "VPMOVSQWMasked128_128", + argLen: 2, + asm: x86.AVPMOVSQW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGD", - argLen: 1, - asm: mips.ANEGD, + name: "VPMOVSQWMasked128_256", + argLen: 2, + asm: x86.AVPMOVSQW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ABSD", - argLen: 1, - asm: mips.AABSD, + name: "VPMOVSQWMasked128_512", + argLen: 2, + asm: x86.AVPMOVSQW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SQRTD", + name: "VPMOVSWB128_128", argLen: 1, - asm: mips.ASQRTD, + asm: x86.AVPMOVSWB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SQRTF", + name: "VPMOVSWB128_256", argLen: 1, - asm: mips.ASQRTF, + asm: x86.AVPMOVSWB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLL", - argLen: 2, - asm: mips.ASLL, + name: "VPMOVSWB256", + argLen: 1, + asm: x86.AVPMOVSWB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLLconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ASLL, + name: "VPMOVSWBMasked128_128", + argLen: 2, + asm: x86.AVPMOVSWB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRL", + name: "VPMOVSWBMasked128_256", argLen: 2, - asm: mips.ASRL, + asm: x86.AVPMOVSWB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRLconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ASRL, + name: "VPMOVSWBMasked256", + argLen: 2, + asm: x86.AVPMOVSWB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRA", - argLen: 2, - asm: mips.ASRA, + name: "VPMOVSXBD128", + argLen: 1, + asm: x86.AVPMOVSXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRAconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ASRA, + name: "VPMOVSXBD256", + argLen: 1, + asm: x86.AVPMOVSXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLZ", + name: "VPMOVSXBD512", argLen: 1, - asm: mips.ACLZ, + asm: x86.AVPMOVSXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SGT", + name: "VPMOVSXBDMasked128", argLen: 2, - asm: mips.ASGT, + asm: x86.AVPMOVSXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SGTconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ASGT, + name: "VPMOVSXBDMasked256", + argLen: 2, + asm: x86.AVPMOVSXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SGTzero", - argLen: 1, - asm: mips.ASGT, + name: "VPMOVSXBDMasked512", + argLen: 2, + asm: x86.AVPMOVSXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SGTU", - argLen: 2, - asm: mips.ASGTU, + name: "VPMOVSXBQ128", + argLen: 1, + asm: x86.AVPMOVSXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGTUconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ASGTU, + name: "VPMOVSXBQ256", + argLen: 1, + asm: x86.AVPMOVSXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGTUzero", + name: "VPMOVSXBQ512", argLen: 1, - asm: mips.ASGTU, + asm: x86.AVPMOVSXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPEQF", + name: "VPMOVSXBQMasked128", argLen: 2, - asm: mips.ACMPEQF, + asm: x86.AVPMOVSXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPEQD", + name: "VPMOVSXBQMasked256", argLen: 2, - asm: mips.ACMPEQD, + asm: x86.AVPMOVSXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPGEF", + name: "VPMOVSXBQMasked512", argLen: 2, - asm: mips.ACMPGEF, + asm: x86.AVPMOVSXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPGED", - argLen: 2, - asm: mips.ACMPGED, + name: "VPMOVSXBW128", + argLen: 1, + asm: x86.AVPMOVSXBW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPGTF", - argLen: 2, - asm: mips.ACMPGTF, + name: "VPMOVSXBW256", + argLen: 1, + asm: x86.AVPMOVSXBW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPGTD", - argLen: 2, - asm: mips.ACMPGTD, + name: "VPMOVSXBW512", + argLen: 1, + asm: x86.AVPMOVSXBW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWconst", - auxType: auxInt32, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVW, + name: "VPMOVSXBWMasked128", + argLen: 2, + asm: x86.AVPMOVSXBW, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFconst", - auxType: auxFloat32, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVF, + name: "VPMOVSXBWMasked256", + argLen: 2, + asm: x86.AVPMOVSXBW, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVD, + name: "VPMOVSXBWMasked512", + argLen: 2, + asm: x86.AVPMOVSXBW, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: mips.AMOVW, + name: "VPMOVSXDQ128", + argLen: 1, + asm: x86.AVPMOVSXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140737555464192}, // SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVB, + name: "VPMOVSXDQ256", + argLen: 1, + asm: x86.AVPMOVSXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVBU, + name: "VPMOVSXDQ512", + argLen: 1, + asm: x86.AVPMOVSXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVH, + name: "VPMOVSXDQMasked128", + argLen: 2, + asm: x86.AVPMOVSXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVHU, + name: "VPMOVSXDQMasked256", + argLen: 2, + asm: x86.AVPMOVSXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVW, + name: "VPMOVSXDQMasked512", + argLen: 2, + asm: x86.AVPMOVSXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVF, + name: "VPMOVSXWD128", + argLen: 1, + asm: x86.AVPMOVSXWD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVD, + name: "VPMOVSXWD256", + argLen: 1, + asm: x86.AVPMOVSXWD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVB, + name: "VPMOVSXWD512", + argLen: 1, + asm: x86.AVPMOVSXWD, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVH, + name: "VPMOVSXWDMasked128", + argLen: 2, + asm: x86.AVPMOVSXWD, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVW, + name: "VPMOVSXWDMasked256", + argLen: 2, + asm: x86.AVPMOVSXWD, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVF, + name: "VPMOVSXWDMasked512", + argLen: 2, + asm: x86.AVPMOVSXWD, reg: regInfo{ inputs: []inputInfo{ - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVD, + name: "VPMOVSXWQ128", + argLen: 1, + asm: x86.AVPMOVSXWQ, reg: regInfo{ inputs: []inputInfo{ - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVB, + name: "VPMOVSXWQ256", + argLen: 1, + asm: x86.AVPMOVSXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVH, + name: "VPMOVSXWQ512", + argLen: 1, + asm: x86.AVPMOVSXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVW, + name: "VPMOVSXWQMasked128", + argLen: 2, + asm: x86.AVPMOVSXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWfpgp", - argLen: 1, - asm: mips.AMOVW, + name: "VPMOVSXWQMasked256", + argLen: 2, + asm: x86.AVPMOVSXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWgpfp", - argLen: 1, - asm: mips.AMOVW, + name: "VPMOVSXWQMasked512", + argLen: 2, + asm: x86.AVPMOVSXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBreg", + name: "VPMOVUSDB128_128", argLen: 1, - asm: mips.AMOVB, + asm: x86.AVPMOVUSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBUreg", + name: "VPMOVUSDB128_256", argLen: 1, - asm: mips.AMOVBU, + asm: x86.AVPMOVUSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHreg", + name: "VPMOVUSDB128_512", argLen: 1, - asm: mips.AMOVH, + asm: x86.AVPMOVUSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: mips.AMOVHU, + name: "VPMOVUSDBMasked128_128", + argLen: 2, + asm: x86.AVPMOVUSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: mips.AMOVW, + name: "VPMOVUSDBMasked128_256", + argLen: 2, + asm: x86.AVPMOVUSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWnop", - argLen: 1, - resultInArg0: true, + name: "VPMOVUSDBMasked128_512", + argLen: 2, + asm: x86.AVPMOVUSDB, reg: regInfo{ inputs: []inputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMOVZ", - argLen: 3, - resultInArg0: true, - asm: mips.ACMOVZ, + name: "VPMOVUSDW128_128", + argLen: 1, + asm: x86.AVPMOVUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 - {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 - {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMOVZzero", - argLen: 2, - resultInArg0: true, - asm: mips.ACMOVZ, + name: "VPMOVUSDW128_256", + argLen: 1, + asm: x86.AVPMOVUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWF", + name: "VPMOVUSDW256", argLen: 1, - asm: mips.AMOVWF, + asm: x86.AVPMOVUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWD", - argLen: 1, - asm: mips.AMOVWD, + name: "VPMOVUSDWMasked128_128", + argLen: 2, + asm: x86.AVPMOVUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TRUNCFW", - argLen: 1, - asm: mips.ATRUNCFW, + name: "VPMOVUSDWMasked128_256", + argLen: 2, + asm: x86.AVPMOVUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TRUNCDW", - argLen: 1, - asm: mips.ATRUNCDW, + name: "VPMOVUSDWMasked256", + argLen: 2, + asm: x86.AVPMOVUSDW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFD", + name: "VPMOVUSQB128_128", argLen: 1, - asm: mips.AMOVFD, + asm: x86.AVPMOVUSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDF", + name: "VPMOVUSQB128_256", argLen: 1, - asm: mips.AMOVDF, + asm: x86.AVPMOVUSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - reg: regInfo{ - clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO - }, - }, - { - name: "CALLtail", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - tailCall: true, - reg: regInfo{ - clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO - }, - }, - { - name: "CALLclosure", - auxType: auxCallOff, - argLen: 3, - clobberFlags: true, - call: true, + name: "VPMOVUSQB128_512", + argLen: 1, + asm: x86.AVPMOVUSQB, reg: regInfo{ inputs: []inputInfo{ - {1, 4194304}, // R22 - {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: 2, - clobberFlags: true, - call: true, + name: "VPMOVUSQBMasked128_128", + argLen: 2, + asm: x86.AVPMOVUSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { - name: "LoweredAtomicLoad8", - argLen: 2, - faultOnNilArg0: true, + name: "VPMOVUSQBMasked128_256", + argLen: 2, + asm: x86.AVPMOVUSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicLoad32", - argLen: 2, - faultOnNilArg0: true, + name: "VPMOVUSQBMasked128_512", + argLen: 2, + asm: x86.AVPMOVUSQB, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVUSQD128_128", + argLen: 1, + asm: x86.AVPMOVUSQD, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVUSQD128_256", + argLen: 1, + asm: x86.AVPMOVUSQD, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStorezero", - argLen: 2, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMOVUSQD256", + argLen: 1, + asm: x86.AVPMOVUSQD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMOVUSQDMasked128_128", + argLen: 2, + asm: x86.AVPMOVUSQD, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAdd", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMOVUSQDMasked128_256", + argLen: 2, + asm: x86.AVPMOVUSQD, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAddconst", - auxType: auxInt32, - argLen: 2, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMOVUSQDMasked256", + argLen: 2, + asm: x86.AVPMOVUSQD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMOVUSQW128_128", + argLen: 1, + asm: x86.AVPMOVUSQW, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: mips.AAND, + name: "VPMOVUSQW128_256", + argLen: 1, + asm: x86.AVPMOVUSQW, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: mips.AOR, + name: "VPMOVUSQW128_512", + argLen: 1, + asm: x86.AVPMOVUSQW, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredZero", - auxType: auxInt32, - argLen: 3, - faultOnNilArg0: true, + name: "VPMOVUSQWMasked128_128", + argLen: 2, + asm: x86.AVPMOVUSQW, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2, // R1 }, }, { - name: "LoweredMove", - auxType: auxInt32, - argLen: 4, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPMOVUSQWMasked128_256", + argLen: 2, + asm: x86.AVPMOVUSQW, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 2}, // R1 - {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 6, // R1 R2 }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VPMOVUSQWMasked128_512", + argLen: 2, + asm: x86.AVPMOVUSQW, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FPFlagTrue", + name: "VPMOVUSWB128_128", argLen: 1, + asm: x86.AVPMOVUSWB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FPFlagFalse", + name: "VPMOVUSWB128_256", argLen: 1, + asm: x86.AVPMOVUSWB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "VPMOVUSWB256", + argLen: 1, + asm: x86.AVPMOVUSWB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 4194304}, // R22 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VPMOVUSWBMasked128_128", + argLen: 2, + asm: x86.AVPMOVUSWB, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VPMOVUSWBMasked128_256", + argLen: 2, + asm: x86.AVPMOVUSWB, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "VPMOVUSWBMasked256", + argLen: 2, + asm: x86.AVPMOVUSWB, reg: regInfo{ - clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 16777216}, // R25 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPubBarrier", - argLen: 1, - hasSideEffects: true, - asm: mips.ASYNC, - reg: regInfo{}, - }, - { - name: "LoweredPanicBoundsRR", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPMOVWB128_128", + argLen: 1, + asm: x86.AVPMOVWB, reg: regInfo{ inputs: []inputInfo{ - {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 - {1, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsRC", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VPMOVWB128_256", + argLen: 1, + asm: x86.AVPMOVWB, reg: regInfo{ inputs: []inputInfo{ - {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCR", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VPMOVWB256", + argLen: 1, + asm: x86.AVPMOVWB, reg: regInfo{ inputs: []inputInfo{ - {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCC", - auxType: auxPanicBoundsCC, - argLen: 1, - call: true, - reg: regInfo{}, - }, - { - name: "LoweredPanicExtendRR", - auxType: auxInt64, - argLen: 4, - call: true, + name: "VPMOVWBMasked128_128", + argLen: 2, + asm: x86.AVPMOVWB, reg: regInfo{ inputs: []inputInfo{ - {0, 30}, // R1 R2 R3 R4 - {1, 30}, // R1 R2 R3 R4 - {2, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicExtendRC", - auxType: auxPanicBoundsC, - argLen: 3, - call: true, + name: "VPMOVWBMasked128_256", + argLen: 2, + asm: x86.AVPMOVWB, reg: regInfo{ inputs: []inputInfo{ - {0, 30}, // R1 R2 R3 R4 - {1, 30}, // R1 R2 R3 R4 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, - { - name: "ADDV", - argLen: 2, - commutative: true, - asm: mips.AADDVU, + name: "VPMOVWBMasked256", + argLen: 2, + asm: x86.AVPMOVWB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDVconst", - auxType: auxInt64, - argLen: 1, - asm: mips.AADDVU, + name: "VPMOVZXBD128", + argLen: 1, + asm: x86.AVPMOVZXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBV", - argLen: 2, - asm: mips.ASUBVU, + name: "VPMOVZXBD256", + argLen: 1, + asm: x86.AVPMOVZXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBVconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASUBVU, + name: "VPMOVZXBD512", + argLen: 1, + asm: x86.AVPMOVZXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULV", - argLen: 2, - commutative: true, - asm: mips.AMULV, + name: "VPMOVZXBDMasked128", + argLen: 2, + asm: x86.AVPMOVZXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504606846976}, // HI - {1, 2305843009213693952}, // LO + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULVU", - argLen: 2, - commutative: true, - asm: mips.AMULVU, + name: "VPMOVZXBDMasked256", + argLen: 2, + asm: x86.AVPMOVZXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504606846976}, // HI - {1, 2305843009213693952}, // LO + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVV", + name: "VPMOVZXBDMasked512", argLen: 2, - asm: mips.ADIVV, + asm: x86.AVPMOVZXBD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504606846976}, // HI - {1, 2305843009213693952}, // LO + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVVU", - argLen: 2, - asm: mips.ADIVVU, + name: "VPMOVZXBQ128", + argLen: 1, + asm: x86.AVPMOVZXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504606846976}, // HI - {1, 2305843009213693952}, // LO + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDF", - argLen: 2, - commutative: true, - asm: mips.AADDF, + name: "VPMOVZXBQ256", + argLen: 1, + asm: x86.AVPMOVZXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDD", - argLen: 2, - commutative: true, - asm: mips.AADDD, + name: "VPMOVZXBQ512", + argLen: 1, + asm: x86.AVPMOVZXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBF", + name: "VPMOVZXBQMasked128", argLen: 2, - asm: mips.ASUBF, + asm: x86.AVPMOVZXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBD", + name: "VPMOVZXBQMasked256", argLen: 2, - asm: mips.ASUBD, + asm: x86.AVPMOVZXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULF", - argLen: 2, - commutative: true, - asm: mips.AMULF, + name: "VPMOVZXBQMasked512", + argLen: 2, + asm: x86.AVPMOVZXBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULD", - argLen: 2, - commutative: true, - asm: mips.AMULD, + name: "VPMOVZXBW128", + argLen: 1, + asm: x86.AVPMOVZXBW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVF", - argLen: 2, - asm: mips.ADIVF, + name: "VPMOVZXBW256", + argLen: 1, + asm: x86.AVPMOVZXBW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVD", - argLen: 2, - asm: mips.ADIVD, + name: "VPMOVZXBW512", + argLen: 1, + asm: x86.AVPMOVZXBW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: mips.AAND, + name: "VPMOVZXBWMasked128", + argLen: 2, + asm: x86.AVPMOVZXBW, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDconst", - auxType: auxInt64, - argLen: 1, - asm: mips.AAND, + name: "VPMOVZXBWMasked256", + argLen: 2, + asm: x86.AVPMOVZXBW, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: mips.AOR, + name: "VPMOVZXBWMasked512", + argLen: 2, + asm: x86.AVPMOVZXBW, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORconst", - auxType: auxInt64, - argLen: 1, - asm: mips.AOR, + name: "VPMOVZXDQ128", + argLen: 1, + asm: x86.AVPMOVZXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: mips.AXOR, + name: "VPMOVZXDQ256", + argLen: 1, + asm: x86.AVPMOVZXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORconst", - auxType: auxInt64, - argLen: 1, - asm: mips.AXOR, + name: "VPMOVZXDQ512", + argLen: 1, + asm: x86.AVPMOVZXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NOR", - argLen: 2, - commutative: true, - asm: mips.ANOR, + name: "VPMOVZXDQMasked128", + argLen: 2, + asm: x86.AVPMOVZXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NORconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ANOR, + name: "VPMOVZXDQMasked256", + argLen: 2, + asm: x86.AVPMOVZXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGV", - argLen: 1, + name: "VPMOVZXDQMasked512", + argLen: 2, + asm: x86.AVPMOVZXDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGF", + name: "VPMOVZXWD128", argLen: 1, - asm: mips.ANEGF, + asm: x86.AVPMOVZXWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGD", + name: "VPMOVZXWD256", argLen: 1, - asm: mips.ANEGD, + asm: x86.AVPMOVZXWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ABSD", + name: "VPMOVZXWD512", argLen: 1, - asm: mips.AABSD, + asm: x86.AVPMOVZXWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SQRTD", - argLen: 1, - asm: mips.ASQRTD, + name: "VPMOVZXWDMasked128", + argLen: 2, + asm: x86.AVPMOVZXWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SQRTF", - argLen: 1, - asm: mips.ASQRTF, + name: "VPMOVZXWDMasked256", + argLen: 2, + asm: x86.AVPMOVZXWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLLV", + name: "VPMOVZXWDMasked512", argLen: 2, - asm: mips.ASLLV, + asm: x86.AVPMOVZXWD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLLVconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASLLV, + name: "VPMOVZXWQ128", + argLen: 1, + asm: x86.AVPMOVZXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLV", - argLen: 2, - asm: mips.ASRLV, + name: "VPMOVZXWQ256", + argLen: 1, + asm: x86.AVPMOVZXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLVconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASRLV, + name: "VPMOVZXWQ512", + argLen: 1, + asm: x86.AVPMOVZXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAV", + name: "VPMOVZXWQMasked128", argLen: 2, - asm: mips.ASRAV, + asm: x86.AVPMOVZXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAVconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASRAV, + name: "VPMOVZXWQMasked256", + argLen: 2, + asm: x86.AVPMOVZXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SGT", + name: "VPMOVZXWQMasked512", argLen: 2, - asm: mips.ASGT, + asm: x86.AVPMOVZXWQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SGTconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASGT, + name: "VPMULDQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMULDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGTU", - argLen: 2, - asm: mips.ASGTU, + name: "VPMULDQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMULDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGTUconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASGTU, + name: "VPMULHUW128", + argLen: 2, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPEQF", - argLen: 2, - asm: mips.ACMPEQF, + name: "VPMULHUW256", + argLen: 2, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPEQD", - argLen: 2, - asm: mips.ACMPEQD, + name: "VPMULHUW512", + argLen: 2, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPGEF", - argLen: 2, - asm: mips.ACMPGEF, + name: "VPMULHUWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPGED", - argLen: 2, - asm: mips.ACMPGED, + name: "VPMULHUWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPGTF", - argLen: 2, - asm: mips.ACMPGTF, + name: "VPMULHUWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPGTD", - argLen: 2, - asm: mips.ACMPGTD, + name: "VPMULHW128", + argLen: 2, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVV, + name: "VPMULHW256", + argLen: 2, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVF, + name: "VPMULHW512", + argLen: 2, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVD, + name: "VPMULHWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: mips.AMOVV, + name: "VPMULHWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018460942336}, // SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVB, + name: "VPMULHWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVBU, + name: "VPMULLD128", + argLen: 2, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVH, + name: "VPMULLD256", + argLen: 2, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVHU, + name: "VPMULLD512", + argLen: 2, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVW, + name: "VPMULLDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVWU, + name: "VPMULLDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVV, + name: "VPMULLDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVF, + name: "VPMULLQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVD, + name: "VPMULLQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVB, + name: "VPMULLQ512", + argLen: 2, + commutative: true, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVH, + name: "VPMULLQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVW, + name: "VPMULLQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVV, + name: "VPMULLQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVF, + name: "VPMULLW128", + argLen: 2, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVD, + name: "VPMULLW256", + argLen: 2, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ZERO", - argLen: 0, - zeroWidth: true, - fixedReg: true, - reg: regInfo{}, - }, - { - name: "MOVWfpgp", - argLen: 1, - asm: mips.AMOVW, + name: "VPMULLW512", + argLen: 2, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWgpfp", - argLen: 1, - asm: mips.AMOVW, + name: "VPMULLWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVfpgp", - argLen: 1, - asm: mips.AMOVV, + name: "VPMULLWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVgpfp", - argLen: 1, - asm: mips.AMOVV, + name: "VPMULLWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: mips.AMOVB, + name: "VPMULUDQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMULUDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUreg", - argLen: 1, - asm: mips.AMOVBU, + name: "VPMULUDQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMULUDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHreg", + name: "VPOPCNTB128", argLen: 1, - asm: mips.AMOVH, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUreg", + name: "VPOPCNTB256", argLen: 1, - asm: mips.AMOVHU, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWreg", + name: "VPOPCNTB512", argLen: 1, - asm: mips.AMOVW, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUreg", - argLen: 1, - asm: mips.AMOVWU, + name: "VPOPCNTBMasked128", + argLen: 2, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVreg", - argLen: 1, - asm: mips.AMOVV, + name: "VPOPCNTBMasked256", + argLen: 2, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVnop", - argLen: 1, - resultInArg0: true, + name: "VPOPCNTBMasked512", + argLen: 2, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWF", + name: "VPOPCNTD128", argLen: 1, - asm: mips.AMOVWF, + asm: x86.AVPOPCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWD", + name: "VPOPCNTD256", argLen: 1, - asm: mips.AMOVWD, + asm: x86.AVPOPCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVF", + name: "VPOPCNTD512", argLen: 1, - asm: mips.AMOVVF, + asm: x86.AVPOPCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVVD", - argLen: 1, - asm: mips.AMOVVD, + name: "VPOPCNTDMasked128", + argLen: 2, + asm: x86.AVPOPCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TRUNCFW", - argLen: 1, - asm: mips.ATRUNCFW, + name: "VPOPCNTDMasked256", + argLen: 2, + asm: x86.AVPOPCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TRUNCDW", - argLen: 1, - asm: mips.ATRUNCDW, + name: "VPOPCNTDMasked512", + argLen: 2, + asm: x86.AVPOPCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TRUNCFV", + name: "VPOPCNTQ128", argLen: 1, - asm: mips.ATRUNCFV, + asm: x86.AVPOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "TRUNCDV", + name: "VPOPCNTQ256", argLen: 1, - asm: mips.ATRUNCDV, + asm: x86.AVPOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVFD", + name: "VPOPCNTQ512", argLen: 1, - asm: mips.AMOVFD, + asm: x86.AVPOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDF", - argLen: 1, - asm: mips.AMOVDF, + name: "VPOPCNTQMasked128", + argLen: 2, + asm: x86.AVPOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, + name: "VPOPCNTQMasked256", + argLen: 2, + asm: x86.AVPOPCNTQ, reg: regInfo{ - clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, }, }, { - name: "CALLtail", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - tailCall: true, + name: "VPOPCNTQMasked512", + argLen: 2, + asm: x86.AVPOPCNTQ, reg: regInfo{ - clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, - argLen: 3, - clobberFlags: true, - call: true, + name: "VPOPCNTW128", + argLen: 1, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {1, 4194304}, // R22 - {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: 2, - clobberFlags: true, - call: true, + name: "VPOPCNTW256", + argLen: 1, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { - name: "DUFFZERO", - auxType: auxInt64, - argLen: 2, - faultOnNilArg0: true, + name: "VPOPCNTW512", + argLen: 1, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 134217730, // R1 R31 }, }, { - name: "DUFFCOPY", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPOPCNTWMasked128", + argLen: 2, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 2}, // R1 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 134217734, // R1 R2 R31 }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, + name: "VPOPCNTWMasked256", + argLen: 2, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2, // R1 }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPOPCNTWMasked512", + argLen: 2, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 2}, // R1 - {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 6, // R1 R2 }, }, { - name: "LoweredAtomicAnd32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: mips.AAND, + name: "VPOR128", + argLen: 2, + commutative: true, + asm: x86.AVPOR, reg: regInfo{ inputs: []inputInfo{ - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicOr32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: mips.AOR, + name: "VPOR256", + argLen: 2, + commutative: true, + asm: x86.AVPOR, reg: regInfo{ inputs: []inputInfo{ - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicLoad8", - argLen: 2, - faultOnNilArg0: true, + name: "VPORD512", + argLen: 2, + commutative: true, + asm: x86.AVPORD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicLoad32", - argLen: 2, - faultOnNilArg0: true, + name: "VPORDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPORD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicLoad64", - argLen: 2, - faultOnNilArg0: true, + name: "VPORDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPORD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPORDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPORD, reg: regInfo{ inputs: []inputInfo{ - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPORQ512", + argLen: 2, + commutative: true, + asm: x86.AVPORQ, reg: regInfo{ inputs: []inputInfo{ - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore64", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPORQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPORQ, reg: regInfo{ inputs: []inputInfo{ - {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStorezero32", - argLen: 2, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPORQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStorezero64", - argLen: 2, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPORQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPROLVD128", + argLen: 2, + asm: x86.AVPROLVD, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPROLVD256", + argLen: 2, + asm: x86.AVPROLVD, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAdd32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPROLVD512", + argLen: 2, + asm: x86.AVPROLVD, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAdd64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPROLVDMasked128", + argLen: 3, + asm: x86.AVPROLVD, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAddconst32", - auxType: auxInt32, - argLen: 2, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPROLVDMasked256", + argLen: 3, + asm: x86.AVPROLVD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAddconst64", - auxType: auxInt64, - argLen: 2, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPROLVDMasked512", + argLen: 3, + asm: x86.AVPROLVD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas32", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPROLVQ128", + argLen: 2, + asm: x86.AVPROLVQ, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas64", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPROLVQ256", + argLen: 2, + asm: x86.AVPROLVQ, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VPROLVQ512", + argLen: 2, + asm: x86.AVPROLVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FPFlagTrue", - argLen: 1, + name: "VPROLVQMasked128", + argLen: 3, + asm: x86.AVPROLVQ, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FPFlagFalse", - argLen: 1, + name: "VPROLVQMasked256", + argLen: 3, + asm: x86.AVPROLVQ, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "VPROLVQMasked512", + argLen: 3, + asm: x86.AVPROLVQ, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 4194304}, // R22 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VPRORVD128", + argLen: 2, + asm: x86.AVPRORVD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VPRORVD256", + argLen: 2, + asm: x86.AVPRORVD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "VPRORVD512", + argLen: 2, + asm: x86.AVPRORVD, reg: regInfo{ - clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 16777216}, // R25 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPubBarrier", - argLen: 1, - hasSideEffects: true, - asm: mips.ASYNC, - reg: regInfo{}, - }, - { - name: "LoweredPanicBoundsRR", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPRORVDMasked128", + argLen: 3, + asm: x86.AVPRORVD, reg: regInfo{ inputs: []inputInfo{ - {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 - {1, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsRC", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VPRORVDMasked256", + argLen: 3, + asm: x86.AVPRORVD, reg: regInfo{ inputs: []inputInfo{ - {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - }, - }, - { - name: "LoweredPanicBoundsCR", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, - reg: regInfo{ - inputs: []inputInfo{ - {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCC", - auxType: auxPanicBoundsCC, - argLen: 1, - call: true, - reg: regInfo{}, - }, - - { - name: "ADD", - argLen: 2, - commutative: true, - asm: ppc64.AADD, + name: "VPRORVDMasked512", + argLen: 3, + asm: x86.AVPRORVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDCC", - argLen: 2, - commutative: true, - asm: ppc64.AADDCC, + name: "VPRORVQ128", + argLen: 2, + asm: x86.AVPRORVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AADD, + name: "VPRORVQ256", + argLen: 2, + asm: x86.AVPRORVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDCCconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AADDCCC, + name: "VPRORVQ512", + argLen: 2, + asm: x86.AVPRORVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FADD", - argLen: 2, - commutative: true, - asm: ppc64.AFADD, + name: "VPRORVQMasked128", + argLen: 3, + asm: x86.AVPRORVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FADDS", - argLen: 2, - commutative: true, - asm: ppc64.AFADDS, + name: "VPRORVQMasked256", + argLen: 3, + asm: x86.AVPRORVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUB", - argLen: 2, - asm: ppc64.ASUB, + name: "VPRORVQMasked512", + argLen: 3, + asm: x86.AVPRORVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBCC", + name: "VPSADBW128", argLen: 2, - asm: ppc64.ASUBCC, + asm: x86.AVPSADBW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBFCconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASUBC, + name: "VPSADBW256", + argLen: 2, + asm: x86.AVPSADBW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FSUB", + name: "VPSADBW512", argLen: 2, - asm: ppc64.AFSUB, + asm: x86.AVPSADBW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSUBS", - argLen: 2, - asm: ppc64.AFSUBS, + name: "VPSHLDVD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHLDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XSMINJDP", - argLen: 2, - asm: ppc64.AXSMINJDP, + name: "VPSHLDVD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHLDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XSMAXJDP", - argLen: 2, - asm: ppc64.AXSMAXJDP, + name: "VPSHLDVD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHLDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULLD", - argLen: 2, - commutative: true, - asm: ppc64.AMULLD, + name: "VPSHLDVDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHLDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULLW", - argLen: 2, - commutative: true, - asm: ppc64.AMULLW, + name: "VPSHLDVDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHLDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULLDconst", - auxType: auxInt32, - argLen: 1, - asm: ppc64.AMULLD, + name: "VPSHLDVDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHLDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULLWconst", - auxType: auxInt32, - argLen: 1, - asm: ppc64.AMULLW, + name: "VPSHLDVQ128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHLDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MADDLD", - argLen: 3, - asm: ppc64.AMADDLD, + name: "VPSHLDVQ256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHLDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULHD", - argLen: 2, - commutative: true, - asm: ppc64.AMULHD, + name: "VPSHLDVQ512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHLDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULHW", - argLen: 2, - commutative: true, - asm: ppc64.AMULHW, + name: "VPSHLDVQMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHLDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULHDU", - argLen: 2, - commutative: true, - asm: ppc64.AMULHDU, + name: "VPSHLDVQMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHLDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULHDUCC", - argLen: 2, - commutative: true, - asm: ppc64.AMULHDUCC, + name: "VPSHLDVQMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHLDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULHWU", - argLen: 2, - commutative: true, - asm: ppc64.AMULHWU, + name: "VPSHLDVW128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHLDVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMUL", - argLen: 2, - commutative: true, - asm: ppc64.AFMUL, + name: "VPSHLDVW256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHLDVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMULS", - argLen: 2, - commutative: true, - asm: ppc64.AFMULS, + name: "VPSHLDVW512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHLDVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMADD", - argLen: 3, - asm: ppc64.AFMADD, + name: "VPSHLDVWMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHLDVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMADDS", - argLen: 3, - asm: ppc64.AFMADDS, + name: "VPSHLDVWMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHLDVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMSUB", - argLen: 3, - asm: ppc64.AFMSUB, + name: "VPSHLDVWMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHLDVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMSUBS", - argLen: 3, - asm: ppc64.AFMSUBS, + name: "VPSHRDVD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHRDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAD", - argLen: 2, - asm: ppc64.ASRAD, + name: "VPSHRDVD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHRDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAW", - argLen: 2, - asm: ppc64.ASRAW, + name: "VPSHRDVD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHRDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRD", - argLen: 2, - asm: ppc64.ASRD, + name: "VPSHRDVDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHRDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRW", - argLen: 2, - asm: ppc64.ASRW, + name: "VPSHRDVDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHRDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLD", - argLen: 2, - asm: ppc64.ASLD, + name: "VPSHRDVDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHRDVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLW", - argLen: 2, - asm: ppc64.ASLW, + name: "VPSHRDVQ128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHRDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ROTL", - argLen: 2, - asm: ppc64.AROTL, + name: "VPSHRDVQ256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHRDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ROTLW", - argLen: 2, - asm: ppc64.AROTLW, + name: "VPSHRDVQ512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHRDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CLRLSLWI", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ACLRLSLWI, + name: "VPSHRDVQMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHRDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CLRLSLDI", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ACLRLSLDI, + name: "VPSHRDVQMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHRDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDC", - argLen: 2, - commutative: true, - asm: ppc64.AADDC, + name: "VPSHRDVQMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHRDVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBC", - argLen: 2, - asm: ppc64.ASUBC, + name: "VPSHRDVW128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHRDVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDCconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AADDC, + name: "VPSHRDVW256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHRDVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBCconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASUBC, + name: "VPSHRDVW512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHRDVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDE", - argLen: 3, - commutative: true, - asm: ppc64.AADDE, + name: "VPSHRDVWMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHRDVW, reg: regInfo{ inputs: []inputInfo{ - {2, 9223372036854775808}, // XER - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDZE", - argLen: 2, - asm: ppc64.AADDZE, + name: "VPSHRDVWMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHRDVW, reg: regInfo{ inputs: []inputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBE", - argLen: 3, - asm: ppc64.ASUBE, + name: "VPSHRDVWMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHRDVW, reg: regInfo{ inputs: []inputInfo{ - {2, 9223372036854775808}, // XER - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDZEzero", - argLen: 1, - asm: ppc64.AADDZE, + name: "VPSHUFB128", + argLen: 2, + asm: x86.AVPSHUFB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372036854775808}, // XER + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBZEzero", - argLen: 1, - asm: ppc64.ASUBZE, + name: "VPSHUFB256", + argLen: 2, + asm: x86.AVPSHUFB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372036854775808}, // XER + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRADconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASRAD, + name: "VPSHUFB512", + argLen: 2, + asm: x86.AVPSHUFB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAWconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASRAW, + name: "VPSHUFBMasked128", + argLen: 3, + asm: x86.AVPSHUFB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRDconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASRD, + name: "VPSHUFBMasked256", + argLen: 3, + asm: x86.AVPSHUFB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRWconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASRW, + name: "VPSHUFBMasked512", + argLen: 3, + asm: x86.AVPSHUFB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLDconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASLD, + name: "VPSIGNB128", + argLen: 2, + asm: x86.AVPSIGNB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLWconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASLW, + name: "VPSIGNB256", + argLen: 2, + asm: x86.AVPSIGNB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ROTLconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AROTL, + name: "VPSIGND128", + argLen: 2, + asm: x86.AVPSIGND, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ROTLWconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AROTLW, + name: "VPSIGND256", + argLen: 2, + asm: x86.AVPSIGND, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "EXTSWSLconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AEXTSWSLI, + name: "VPSIGNW128", + argLen: 2, + asm: x86.AVPSIGNW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RLWINM", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ARLWNM, + name: "VPSIGNW256", + argLen: 2, + asm: x86.AVPSIGNW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RLWNM", - auxType: auxInt64, - argLen: 2, - asm: ppc64.ARLWNM, + name: "VPSLLD128", + argLen: 2, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RLWMI", - auxType: auxInt64, - argLen: 2, - resultInArg0: true, - asm: ppc64.ARLWMI, + name: "VPSLLD256", + argLen: 2, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RLDICL", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ARLDICL, + name: "VPSLLD512", + argLen: 2, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RLDICLCC", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ARLDICLCC, + name: "VPSLLDMasked128", + argLen: 3, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RLDICR", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ARLDICR, + name: "VPSLLDMasked256", + argLen: 3, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CNTLZD", - argLen: 1, - asm: ppc64.ACNTLZD, + name: "VPSLLDMasked512", + argLen: 3, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CNTLZDCC", - argLen: 1, - asm: ppc64.ACNTLZDCC, + name: "VPSLLQ128", + argLen: 2, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CNTLZW", - argLen: 1, - asm: ppc64.ACNTLZW, + name: "VPSLLQ256", + argLen: 2, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CNTTZD", - argLen: 1, - asm: ppc64.ACNTTZD, + name: "VPSLLQ512", + argLen: 2, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CNTTZW", - argLen: 1, - asm: ppc64.ACNTTZW, + name: "VPSLLQMasked128", + argLen: 3, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "POPCNTD", - argLen: 1, - asm: ppc64.APOPCNTD, + name: "VPSLLQMasked256", + argLen: 3, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "POPCNTW", - argLen: 1, - asm: ppc64.APOPCNTW, + name: "VPSLLQMasked512", + argLen: 3, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "POPCNTB", - argLen: 1, - asm: ppc64.APOPCNTB, + name: "VPSLLVD128", + argLen: 2, + asm: x86.AVPSLLVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FDIV", + name: "VPSLLVD256", argLen: 2, - asm: ppc64.AFDIV, + asm: x86.AVPSLLVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FDIVS", + name: "VPSLLVD512", argLen: 2, - asm: ppc64.AFDIVS, + asm: x86.AVPSLLVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVD", - argLen: 2, - asm: ppc64.ADIVD, + name: "VPSLLVDMasked128", + argLen: 3, + asm: x86.AVPSLLVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVW", - argLen: 2, - asm: ppc64.ADIVW, + name: "VPSLLVDMasked256", + argLen: 3, + asm: x86.AVPSLLVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVDU", + name: "VPSLLVDMasked512", + argLen: 3, + asm: x86.AVPSLLVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVQ128", argLen: 2, - asm: ppc64.ADIVDU, + asm: x86.AVPSLLVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVWU", + name: "VPSLLVQ256", argLen: 2, - asm: ppc64.ADIVWU, + asm: x86.AVPSLLVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MODUD", + name: "VPSLLVQ512", argLen: 2, - asm: ppc64.AMODUD, + asm: x86.AVPSLLVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MODSD", + name: "VPSLLVQMasked128", + argLen: 3, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVQMasked256", + argLen: 3, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVQMasked512", + argLen: 3, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVW128", argLen: 2, - asm: ppc64.AMODSD, + asm: x86.AVPSLLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MODUW", + name: "VPSLLVW256", argLen: 2, - asm: ppc64.AMODUW, + asm: x86.AVPSLLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MODSW", + name: "VPSLLVW512", argLen: 2, - asm: ppc64.AMODSW, + asm: x86.AVPSLLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCTIDZ", - argLen: 1, - asm: ppc64.AFCTIDZ, + name: "VPSLLVWMasked128", + argLen: 3, + asm: x86.AVPSLLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCTIWZ", - argLen: 1, - asm: ppc64.AFCTIWZ, + name: "VPSLLVWMasked256", + argLen: 3, + asm: x86.AVPSLLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCFID", - argLen: 1, - asm: ppc64.AFCFID, + name: "VPSLLVWMasked512", + argLen: 3, + asm: x86.AVPSLLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCFIDS", - argLen: 1, - asm: ppc64.AFCFIDS, + name: "VPSLLW128", + argLen: 2, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FRSP", - argLen: 1, - asm: ppc64.AFRSP, + name: "VPSLLW256", + argLen: 2, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MFVSRD", - argLen: 1, - asm: ppc64.AMFVSRD, + name: "VPSLLW512", + argLen: 2, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MTVSRD", - argLen: 1, - asm: ppc64.AMTVSRD, + name: "VPSLLWMasked128", + argLen: 3, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: ppc64.AAND, + name: "VPSLLWMasked256", + argLen: 3, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDN", + name: "VPSLLWMasked512", + argLen: 3, + asm: x86.AVPSLLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAD128", argLen: 2, - asm: ppc64.AANDN, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDNCC", + name: "VPSRAD256", argLen: 2, - asm: ppc64.AANDNCC, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDCC", - argLen: 2, - commutative: true, - asm: ppc64.AANDCC, + name: "VPSRAD512", + argLen: 2, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: ppc64.AOR, + name: "VPSRADMasked128", + argLen: 3, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORN", - argLen: 2, - asm: ppc64.AORN, + name: "VPSRADMasked256", + argLen: 3, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORCC", - argLen: 2, - commutative: true, - asm: ppc64.AORCC, + name: "VPSRADMasked512", + argLen: 3, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NOR", - argLen: 2, - commutative: true, - asm: ppc64.ANOR, + name: "VPSRAQ128", + argLen: 2, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NORCC", - argLen: 2, - commutative: true, - asm: ppc64.ANORCC, + name: "VPSRAQ256", + argLen: 2, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: ppc64.AXOR, + name: "VPSRAQ512", + argLen: 2, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORCC", - argLen: 2, - commutative: true, - asm: ppc64.AXORCC, + name: "VPSRAQMasked128", + argLen: 3, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "EQV", - argLen: 2, - commutative: true, - asm: ppc64.AEQV, + name: "VPSRAQMasked256", + argLen: 3, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEG", - argLen: 1, - asm: ppc64.ANEG, + name: "VPSRAQMasked512", + argLen: 3, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGCC", - argLen: 1, - asm: ppc64.ANEGCC, + name: "VPSRAVD128", + argLen: 2, + asm: x86.AVPSRAVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BRD", - argLen: 1, - asm: ppc64.ABRD, + name: "VPSRAVD256", + argLen: 2, + asm: x86.AVPSRAVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BRW", - argLen: 1, - asm: ppc64.ABRW, + name: "VPSRAVD512", + argLen: 2, + asm: x86.AVPSRAVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "BRH", - argLen: 1, - asm: ppc64.ABRH, + name: "VPSRAVDMasked128", + argLen: 3, + asm: x86.AVPSRAVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNEG", - argLen: 1, - asm: ppc64.AFNEG, + name: "VPSRAVDMasked256", + argLen: 3, + asm: x86.AVPSRAVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSQRT", - argLen: 1, - asm: ppc64.AFSQRT, + name: "VPSRAVDMasked512", + argLen: 3, + asm: x86.AVPSRAVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSQRTS", - argLen: 1, - asm: ppc64.AFSQRTS, + name: "VPSRAVQ128", + argLen: 2, + asm: x86.AVPSRAVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FFLOOR", - argLen: 1, - asm: ppc64.AFRIM, + name: "VPSRAVQ256", + argLen: 2, + asm: x86.AVPSRAVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCEIL", - argLen: 1, - asm: ppc64.AFRIP, + name: "VPSRAVQ512", + argLen: 2, + asm: x86.AVPSRAVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FTRUNC", - argLen: 1, - asm: ppc64.AFRIZ, + name: "VPSRAVQMasked128", + argLen: 3, + asm: x86.AVPSRAVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FROUND", - argLen: 1, - asm: ppc64.AFRIN, + name: "VPSRAVQMasked256", + argLen: 3, + asm: x86.AVPSRAVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FABS", - argLen: 1, - asm: ppc64.AFABS, + name: "VPSRAVQMasked512", + argLen: 3, + asm: x86.AVPSRAVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNABS", - argLen: 1, - asm: ppc64.AFNABS, + name: "VPSRAVW128", + argLen: 2, + asm: x86.AVPSRAVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCPSGN", + name: "VPSRAVW256", argLen: 2, - asm: ppc64.AFCPSGN, + asm: x86.AVPSRAVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AOR, + name: "VPSRAVW512", + argLen: 2, + asm: x86.AVPSRAVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AXOR, + name: "VPSRAVWMasked128", + argLen: 3, + asm: x86.AVPSRAVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDCCconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AANDCC, + name: "VPSRAVWMasked256", + argLen: 3, + asm: x86.AVPSRAVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDconst", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, - asm: ppc64.AANDCC, + name: "VPSRAVWMasked512", + argLen: 3, + asm: x86.AVPSRAVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: ppc64.AMOVB, + name: "VPSRAW128", + argLen: 2, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBZreg", - argLen: 1, - asm: ppc64.AMOVBZ, + name: "VPSRAW256", + argLen: 2, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: ppc64.AMOVH, + name: "VPSRAW512", + argLen: 2, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHZreg", - argLen: 1, - asm: ppc64.AMOVHZ, + name: "VPSRAWMasked128", + argLen: 3, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: ppc64.AMOVW, + name: "VPSRAWMasked256", + argLen: 3, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWZreg", - argLen: 1, - asm: ppc64.AMOVWZ, + name: "VPSRAWMasked512", + argLen: 3, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVBZ, + name: "VPSRLD128", + argLen: 2, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVH, + name: "VPSRLD256", + argLen: 2, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVHZ, + name: "VPSRLD512", + argLen: 2, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVW, + name: "VPSRLDMasked128", + argLen: 3, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVWZ, + name: "VPSRLDMasked256", + argLen: 3, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVD, + name: "VPSRLDMasked512", + argLen: 3, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDBRload", - argLen: 2, - faultOnNilArg0: true, - asm: ppc64.AMOVDBR, + name: "VPSRLQ128", + argLen: 2, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWBRload", - argLen: 2, - faultOnNilArg0: true, - asm: ppc64.AMOVWBR, + name: "VPSRLQ256", + argLen: 2, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHBRload", - argLen: 2, - faultOnNilArg0: true, - asm: ppc64.AMOVHBR, + name: "VPSRLQ512", + argLen: 2, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBZloadidx", + name: "VPSRLQMasked128", argLen: 3, - asm: ppc64.AMOVBZ, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHloadidx", + name: "VPSRLQMasked256", argLen: 3, - asm: ppc64.AMOVH, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHZloadidx", + name: "VPSRLQMasked512", argLen: 3, - asm: ppc64.AMOVHZ, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWloadidx", - argLen: 3, - asm: ppc64.AMOVW, + name: "VPSRLVD128", + argLen: 2, + asm: x86.AVPSRLVD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWZloadidx", - argLen: 3, - asm: ppc64.AMOVWZ, + name: "VPSRLVD256", + argLen: 2, + asm: x86.AVPSRLVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSRLVD512", + argLen: 2, + asm: x86.AVPSRLVD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDloadidx", + name: "VPSRLVDMasked128", argLen: 3, - asm: ppc64.AMOVD, + asm: x86.AVPSRLVD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHBRloadidx", + name: "VPSRLVDMasked256", argLen: 3, - asm: ppc64.AMOVHBR, + asm: x86.AVPSRLVD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWBRloadidx", + name: "VPSRLVDMasked512", argLen: 3, - asm: ppc64.AMOVWBR, + asm: x86.AVPSRLVD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDBRloadidx", - argLen: 3, - asm: ppc64.AMOVDBR, + name: "VPSRLVQ128", + argLen: 2, + asm: x86.AVPSRLVQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDloadidx", - argLen: 3, - asm: ppc64.AFMOVD, + name: "VPSRLVQ256", + argLen: 2, + asm: x86.AVPSRLVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSloadidx", - argLen: 3, - asm: ppc64.AFMOVS, + name: "VPSRLVQ512", + argLen: 2, + asm: x86.AVPSRLVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DCBT", - auxType: auxInt64, - argLen: 2, - hasSideEffects: true, - asm: ppc64.ADCBT, + name: "VPSRLVQMasked128", + argLen: 3, + asm: x86.AVPSRLVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDBRstore", - argLen: 3, - faultOnNilArg0: true, - asm: ppc64.AMOVDBR, + name: "VPSRLVQMasked256", + argLen: 3, + asm: x86.AVPSRLVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWBRstore", - argLen: 3, - faultOnNilArg0: true, - asm: ppc64.AMOVWBR, + name: "VPSRLVQMasked512", + argLen: 3, + asm: x86.AVPSRLVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHBRstore", - argLen: 3, - faultOnNilArg0: true, - asm: ppc64.AMOVHBR, + name: "VPSRLVW128", + argLen: 2, + asm: x86.AVPSRLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AFMOVD, + name: "VPSRLVW256", + argLen: 2, + asm: x86.AVPSRLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AFMOVS, + name: "VPSRLVW512", + argLen: 2, + asm: x86.AVPSRLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVB, + name: "VPSRLVWMasked128", + argLen: 3, + asm: x86.AVPSRLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVH, + name: "VPSRLVWMasked256", + argLen: 3, + asm: x86.AVPSRLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVW, + name: "VPSRLVWMasked512", + argLen: 3, + asm: x86.AVPSRLVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVD, + name: "VPSRLW128", + argLen: 2, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AFMOVD, + name: "VPSRLW256", + argLen: 2, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AFMOVS, + name: "VPSRLW512", + argLen: 2, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstoreidx", - argLen: 4, - asm: ppc64.AMOVB, + name: "VPSRLWMasked128", + argLen: 3, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstoreidx", - argLen: 4, - asm: ppc64.AMOVH, + name: "VPSRLWMasked256", + argLen: 3, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstoreidx", - argLen: 4, - asm: ppc64.AMOVW, + name: "VPSRLWMasked512", + argLen: 3, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstoreidx", - argLen: 4, - asm: ppc64.AMOVD, + name: "VPSUBB128", + argLen: 2, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDstoreidx", - argLen: 4, - asm: ppc64.AFMOVD, + name: "VPSUBB256", + argLen: 2, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSstoreidx", - argLen: 4, - asm: ppc64.AFMOVS, + name: "VPSUBB512", + argLen: 2, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHBRstoreidx", - argLen: 4, - asm: ppc64.AMOVHBR, + name: "VPSUBBMasked128", + argLen: 3, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWBRstoreidx", - argLen: 4, - asm: ppc64.AMOVWBR, + name: "VPSUBBMasked256", + argLen: 3, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDBRstoreidx", - argLen: 4, - asm: ppc64.AMOVDBR, + name: "VPSUBBMasked512", + argLen: 3, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVB, + name: "VPSUBD128", + argLen: 2, + asm: x86.AVPSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVH, + name: "VPSUBD256", + argLen: 2, + asm: x86.AVPSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVW, + name: "VPSUBD512", + argLen: 2, + asm: x86.AVPSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVD, + name: "VPSUBDMasked128", + argLen: 3, + asm: x86.AVPSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: ppc64.AMOVD, + name: "VPSUBDMasked256", + argLen: 3, + asm: x86.AVPSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: ppc64.AMOVD, + name: "VPSUBDMasked512", + argLen: 3, + asm: x86.AVPSUBD, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: ppc64.AFMOVD, + name: "VPSUBQ128", + argLen: 2, + asm: x86.AVPSUBQ, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSconst", - auxType: auxFloat32, - argLen: 0, - rematerializeable: true, - asm: ppc64.AFMOVS, + name: "VPSUBQ256", + argLen: 2, + asm: x86.AVPSUBQ, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCMPU", + name: "VPSUBQ512", argLen: 2, - asm: ppc64.AFCMPU, + asm: x86.AVPSUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMP", - argLen: 2, - asm: ppc64.ACMP, + name: "VPSUBQMasked128", + argLen: 3, + asm: x86.AVPSUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPU", - argLen: 2, - asm: ppc64.ACMPU, + name: "VPSUBQMasked256", + argLen: 3, + asm: x86.AVPSUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPW", - argLen: 2, - asm: ppc64.ACMPW, + name: "VPSUBQMasked512", + argLen: 3, + asm: x86.AVPSUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPWU", + name: "VPSUBSB128", argLen: 2, - asm: ppc64.ACMPWU, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ACMP, + name: "VPSUBSB256", + argLen: 2, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPUconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ACMPU, + name: "VPSUBSB512", + argLen: 2, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPWconst", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ACMPW, + name: "VPSUBSBMasked128", + argLen: 3, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPWUconst", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ACMPWU, + name: "VPSUBSBMasked256", + argLen: 3, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ISEL", - auxType: auxInt32, - argLen: 3, - asm: ppc64.AISEL, + name: "VPSUBSBMasked512", + argLen: 3, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ISELZ", - auxType: auxInt32, - argLen: 2, - asm: ppc64.AISEL, + name: "VPSUBSW128", + argLen: 2, + asm: x86.AVPSUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SETBC", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ASETBC, + name: "VPSUBSW256", + argLen: 2, + asm: x86.AVPSUBSW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SETBCR", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ASETBCR, + name: "VPSUBSW512", + argLen: 2, + asm: x86.AVPSUBSW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "Equal", - argLen: 1, + name: "VPSUBSWMasked128", + argLen: 3, + asm: x86.AVPSUBSW, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NotEqual", - argLen: 1, + name: "VPSUBSWMasked256", + argLen: 3, + asm: x86.AVPSUBSW, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LessThan", - argLen: 1, + name: "VPSUBSWMasked512", + argLen: 3, + asm: x86.AVPSUBSW, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FLessThan", - argLen: 1, + name: "VPSUBUSB128", + argLen: 2, + asm: x86.AVPSUBUSB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessEqual", - argLen: 1, + name: "VPSUBUSB256", + argLen: 2, + asm: x86.AVPSUBUSB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FLessEqual", - argLen: 1, + name: "VPSUBUSB512", + argLen: 2, + asm: x86.AVPSUBUSB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "GreaterThan", - argLen: 1, + name: "VPSUBUSBMasked128", + argLen: 3, + asm: x86.AVPSUBUSB, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FGreaterThan", - argLen: 1, + name: "VPSUBUSBMasked256", + argLen: 3, + asm: x86.AVPSUBUSB, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "GreaterEqual", - argLen: 1, + name: "VPSUBUSBMasked512", + argLen: 3, + asm: x86.AVPSUBUSB, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FGreaterEqual", - argLen: 1, + name: "VPSUBUSW128", + argLen: 2, + asm: x86.AVPSUBUSW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "VPSUBUSW256", + argLen: 2, + asm: x86.AVPSUBUSW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, outputs: []outputInfo{ - {0, 2048}, // R11 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VPSUBUSW512", + argLen: 2, + asm: x86.AVPSUBUSW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VPSUBUSWMasked128", + argLen: 3, + asm: x86.AVPSUBUSW, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - clobberFlags: true, - nilCheck: true, - faultOnNilArg0: true, + name: "VPSUBUSWMasked256", + argLen: 3, + asm: x86.AVPSUBUSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2147483648, // R31 }, }, { - name: "LoweredRound32F", - argLen: 1, - resultInArg0: true, - zeroWidth: true, + name: "VPSUBUSWMasked512", + argLen: 3, + asm: x86.AVPSUBUSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredRound64F", - argLen: 1, - resultInArg0: true, - zeroWidth: true, + name: "VPSUBW128", + argLen: 2, + asm: x86.AVPSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPSUBW256", + argLen: 2, + asm: x86.AVPSUBW, reg: regInfo{ - clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, }, }, { - name: "CALLtail", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, - tailCall: true, + name: "VPSUBW512", + argLen: 2, + asm: x86.AVPSUBW, reg: regInfo{ - clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPSUBWMasked128", + argLen: 3, + asm: x86.AVPSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 4096}, // R12 - {1, 2048}, // R11 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPSUBWMasked256", + argLen: 3, + asm: x86.AVPSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 4096}, // R12 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, - unsafePoint: true, + name: "VPSUBWMasked512", + argLen: 3, + asm: x86.AVPSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R20 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 1048576, // R20 }, }, { - name: "LoweredZeroShort", - auxType: auxInt64, - argLen: 2, - faultOnNilArg0: true, - unsafePoint: true, + name: "VPUNPCKHDQ128", + argLen: 2, + asm: x86.AVPUNPCKHDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredQuadZeroShort", - auxType: auxInt64, - argLen: 2, - faultOnNilArg0: true, - unsafePoint: true, + name: "VPUNPCKHDQ256", + argLen: 2, + asm: x86.AVPUNPCKHDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredQuadZero", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, - unsafePoint: true, + name: "VPUNPCKHDQ512", + argLen: 2, + asm: x86.AVPUNPCKHDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R20 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 1048576, // R20 }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, - unsafePoint: true, + name: "VPUNPCKHQDQ128", + argLen: 2, + asm: x86.AVPUNPCKHQDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R20 - {1, 2097152}, // R21 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 3145728, // R20 R21 }, }, { - name: "LoweredMoveShort", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, - unsafePoint: true, + name: "VPUNPCKHQDQ256", + argLen: 2, + asm: x86.AVPUNPCKHQDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredQuadMove", - auxType: auxInt64, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, - unsafePoint: true, + name: "VPUNPCKHQDQ512", + argLen: 2, + asm: x86.AVPUNPCKHQDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R20 - {1, 2097152}, // R21 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 3145728, // R20 R21 }, }, { - name: "LoweredQuadMoveShort", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, - unsafePoint: true, + name: "VPUNPCKHWD128", + argLen: 2, + asm: x86.AVPUNPCKHWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicStore8", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPUNPCKHWD256", + argLen: 2, + asm: x86.AVPUNPCKHWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicStore32", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPUNPCKHWD512", + argLen: 2, + asm: x86.AVPUNPCKHWD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore64", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPUNPCKLDQ128", + argLen: 2, + asm: x86.AVPUNPCKLDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicLoad8", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, + name: "VPUNPCKLDQ256", + argLen: 2, + asm: x86.AVPUNPCKLDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicLoad32", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, + name: "VPUNPCKLDQ512", + argLen: 2, + asm: x86.AVPUNPCKLDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicLoad64", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, + name: "VPUNPCKLQDQ128", + argLen: 2, + asm: x86.AVPUNPCKLQDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicLoadPtr", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, + name: "VPUNPCKLQDQ256", + argLen: 2, + asm: x86.AVPUNPCKLQDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAdd32", - argLen: 3, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPUNPCKLQDQ512", + argLen: 2, + asm: x86.AVPUNPCKLQDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAdd64", - argLen: 3, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPUNPCKLWD128", + argLen: 2, + asm: x86.AVPUNPCKLWD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange8", - argLen: 3, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPUNPCKLWD256", + argLen: 2, + asm: x86.AVPUNPCKLWD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange32", - argLen: 3, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPUNPCKLWD512", + argLen: 2, + asm: x86.AVPUNPCKLWD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange64", - argLen: 3, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPXOR128", + argLen: 2, + commutative: true, + asm: x86.AVPXOR, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicCas64", - auxType: auxInt64, - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPXOR256", + argLen: 2, + commutative: true, + asm: x86.AVPXOR, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicCas32", - auxType: auxInt64, - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPXORD512", + argLen: 2, + commutative: true, + asm: x86.AVPXORD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicAnd8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: ppc64.AAND, + name: "VPXORDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPXORD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - }, - }, - { - name: "LoweredAtomicAnd32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: ppc64.AAND, - reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: ppc64.AOR, + name: "VPXORDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPXORD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicOr32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: ppc64.AOR, + name: "VPXORDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPXORD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - }, - }, - { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, - reg: regInfo{ - clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER outputs: []outputInfo{ - {0, 536870912}, // R29 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPubBarrier", - argLen: 1, - hasSideEffects: true, - asm: ppc64.ALWSYNC, - reg: regInfo{}, - }, - { - name: "LoweredPanicBoundsRR", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPXORQ512", + argLen: 2, + commutative: true, + asm: x86.AVPXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1016}, // R3 R4 R5 R6 R7 R8 R9 - {1, 1016}, // R3 R4 R5 R6 R7 R8 R9 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - }, - }, - { - name: "LoweredPanicBoundsRC", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, - reg: regInfo{ - inputs: []inputInfo{ - {0, 1016}, // R3 R4 R5 R6 R7 R8 R9 + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCR", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VPXORQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1016}, // R3 R4 R5 R6 R7 R8 R9 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCC", - auxType: auxPanicBoundsCC, - argLen: 1, - call: true, - reg: regInfo{}, - }, - { - name: "InvertFlags", - argLen: 1, - reg: regInfo{}, - }, - { - name: "FlagEQ", - argLen: 0, - reg: regInfo{}, - }, - { - name: "FlagLT", - argLen: 0, - reg: regInfo{}, - }, - { - name: "FlagGT", - argLen: 0, - reg: regInfo{}, - }, - - { - name: "ADD", - argLen: 2, + name: "VPXORQMasked256", + argLen: 3, commutative: true, - asm: riscv.AADD, + asm: x86.AVPXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDI", - auxType: auxInt64, - argLen: 1, - asm: riscv.AADDI, + name: "VPXORQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDIW", - auxType: auxInt64, - argLen: 1, - asm: riscv.AADDIW, + name: "VRCP14PD128", + argLen: 1, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEG", + name: "VRCP14PD256", argLen: 1, - asm: riscv.ANEG, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGW", + name: "VRCP14PD512", argLen: 1, - asm: riscv.ANEGW, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUB", + name: "VRCP14PDMasked128", argLen: 2, - asm: riscv.ASUB, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBW", + name: "VRCP14PDMasked256", argLen: 2, - asm: riscv.ASUBW, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MUL", - argLen: 2, - commutative: true, - asm: riscv.AMUL, + name: "VRCP14PDMasked512", + argLen: 2, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULW", - argLen: 2, - commutative: true, - asm: riscv.AMULW, + name: "VRCP14PS512", + argLen: 1, + asm: x86.AVRCP14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULH", - argLen: 2, - commutative: true, - asm: riscv.AMULH, + name: "VRCP14PSMasked128", + argLen: 2, + asm: x86.AVRCP14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULHU", - argLen: 2, - commutative: true, - asm: riscv.AMULHU, + name: "VRCP14PSMasked256", + argLen: 2, + asm: x86.AVRCP14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredMuluhilo", - argLen: 2, - resultNotInArgs: true, + name: "VRCP14PSMasked512", + argLen: 2, + asm: x86.AVRCP14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredMuluover", - argLen: 2, - resultNotInArgs: true, + name: "VRCPPS128", + argLen: 1, + asm: x86.AVRCPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIV", - argLen: 2, - asm: riscv.ADIV, + name: "VRCPPS256", + argLen: 1, + asm: x86.AVRCPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVU", - argLen: 2, - asm: riscv.ADIVU, + name: "VRSQRT14PD128", + argLen: 1, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVW", - argLen: 2, - asm: riscv.ADIVW, + name: "VRSQRT14PD256", + argLen: 1, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVUW", - argLen: 2, - asm: riscv.ADIVUW, + name: "VRSQRT14PD512", + argLen: 1, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "REM", + name: "VRSQRT14PDMasked128", argLen: 2, - asm: riscv.AREM, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "REMU", + name: "VRSQRT14PDMasked256", argLen: 2, - asm: riscv.AREMU, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "REMW", + name: "VRSQRT14PDMasked512", argLen: 2, - asm: riscv.AREMW, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "REMUW", - argLen: 2, - asm: riscv.AREMUW, + name: "VRSQRT14PS512", + argLen: 1, + asm: x86.AVRSQRT14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: riscv.AMOV, + name: "VRSQRT14PSMasked128", + argLen: 2, + asm: x86.AVRSQRT14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: riscv.AMOV, + name: "VRSQRT14PSMasked256", + argLen: 2, + asm: x86.AVRSQRT14PS, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVB, + name: "VRSQRT14PSMasked512", + argLen: 2, + asm: x86.AVRSQRT14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVH, + name: "VRSQRTPS128", + argLen: 1, + asm: x86.AVRSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVW, + name: "VRSQRTPS256", + argLen: 1, + asm: x86.AVRSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOV, + name: "VSCALEFPD128", + argLen: 2, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVBU, + name: "VSCALEFPD256", + argLen: 2, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVHU, + name: "VSCALEFPD512", + argLen: 2, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVWU, + name: "VSCALEFPDMasked128", + argLen: 3, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVB, + name: "VSCALEFPDMasked256", + argLen: 3, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVH, + name: "VSCALEFPDMasked512", + argLen: 3, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVW, + name: "VSCALEFPS128", + argLen: 2, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOV, + name: "VSCALEFPS256", + argLen: 2, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVB, + name: "VSCALEFPS512", + argLen: 2, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVH, + name: "VSCALEFPSMasked128", + argLen: 3, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVW, + name: "VSCALEFPSMasked256", + argLen: 3, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOV, + name: "VSCALEFPSMasked512", + argLen: 3, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBreg", + name: "VSQRTPD128", argLen: 1, - asm: riscv.AMOVB, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHreg", + name: "VSQRTPD256", argLen: 1, - asm: riscv.AMOVH, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWreg", + name: "VSQRTPD512", argLen: 1, - asm: riscv.AMOVW, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDreg", - argLen: 1, - asm: riscv.AMOV, + name: "VSQRTPDMasked128", + argLen: 2, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBUreg", - argLen: 1, - asm: riscv.AMOVBU, + name: "VSQRTPDMasked256", + argLen: 2, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: riscv.AMOVHU, + name: "VSQRTPDMasked512", + argLen: 2, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWUreg", + name: "VSQRTPS128", argLen: 1, - asm: riscv.AMOVWU, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDnop", - argLen: 1, - resultInArg0: true, + name: "VSQRTPS256", + argLen: 1, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLL", - argLen: 2, - asm: riscv.ASLL, + name: "VSQRTPS512", + argLen: 1, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLLW", + name: "VSQRTPSMasked128", argLen: 2, - asm: riscv.ASLLW, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRA", + name: "VSQRTPSMasked256", argLen: 2, - asm: riscv.ASRA, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAW", + name: "VSQRTPSMasked512", argLen: 2, - asm: riscv.ASRAW, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRL", + name: "VSUBPD128", argLen: 2, - asm: riscv.ASRL, + asm: x86.AVSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLW", + name: "VSUBPD256", argLen: 2, - asm: riscv.ASRLW, + asm: x86.AVSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLLI", - auxType: auxInt64, - argLen: 1, - asm: riscv.ASLLI, + name: "VSUBPD512", + argLen: 2, + asm: x86.AVSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLLIW", - auxType: auxInt64, - argLen: 1, - asm: riscv.ASLLIW, + name: "VSUBPDMasked128", + argLen: 3, + asm: x86.AVSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAI", - auxType: auxInt64, - argLen: 1, - asm: riscv.ASRAI, + name: "VSUBPDMasked256", + argLen: 3, + asm: x86.AVSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAIW", - auxType: auxInt64, - argLen: 1, - asm: riscv.ASRAIW, + name: "VSUBPDMasked512", + argLen: 3, + asm: x86.AVSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRLI", - auxType: auxInt64, - argLen: 1, - asm: riscv.ASRLI, + name: "VSUBPS128", + argLen: 2, + asm: x86.AVSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLIW", - auxType: auxInt64, - argLen: 1, - asm: riscv.ASRLIW, + name: "VSUBPS256", + argLen: 2, + asm: x86.AVSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SH1ADD", + name: "VSUBPS512", argLen: 2, - asm: riscv.ASH1ADD, + asm: x86.AVSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SH2ADD", - argLen: 2, - asm: riscv.ASH2ADD, + name: "VSUBPSMasked128", + argLen: 3, + asm: x86.AVSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SH3ADD", - argLen: 2, - asm: riscv.ASH3ADD, + name: "VSUBPSMasked256", + argLen: 3, + asm: x86.AVSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: riscv.AAND, + name: "VSUBPSMasked512", + argLen: 3, + asm: x86.AVSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDN", - argLen: 2, - asm: riscv.AANDN, + name: "SHA1RNDS4128", + auxType: auxUInt8, + argLen: 2, + resultInArg0: true, + asm: x86.ASHA1RNDS4, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDI", - auxType: auxInt64, + name: "VAESKEYGENASSIST128", + auxType: auxUInt8, argLen: 1, - asm: riscv.AANDI, + asm: x86.AVAESKEYGENASSIST, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLZ", - argLen: 1, - asm: riscv.ACLZ, + name: "VCMPPD128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLZW", - argLen: 1, - asm: riscv.ACLZW, + name: "VCMPPD256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CPOP", - argLen: 1, - asm: riscv.ACPOP, + name: "VCMPPD512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CPOPW", - argLen: 1, - asm: riscv.ACPOPW, + name: "VCMPPDMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CTZ", - argLen: 1, - asm: riscv.ACTZ, + name: "VCMPPDMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CTZW", - argLen: 1, - asm: riscv.ACTZW, + name: "VCMPPDMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "NOT", - argLen: 1, - asm: riscv.ANOT, + name: "VCMPPS128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: riscv.AOR, + name: "VCMPPS256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORN", - argLen: 2, - asm: riscv.AORN, + name: "VCMPPS512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ORI", - auxType: auxInt64, - argLen: 1, - asm: riscv.AORI, + name: "VCMPPSMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "REV8", - argLen: 1, - asm: riscv.AREV8, + name: "VCMPPSMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ROL", - argLen: 2, - asm: riscv.AROL, + name: "VCMPPSMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ROLW", - argLen: 2, - asm: riscv.AROLW, + name: "VEXTRACTF64X4256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVEXTRACTF64X4, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ROR", - argLen: 2, - asm: riscv.AROR, + name: "VEXTRACTF128128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVEXTRACTF128, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RORI", - auxType: auxInt64, + name: "VEXTRACTI64X4256", + auxType: auxUInt8, argLen: 1, - asm: riscv.ARORI, + asm: x86.AVEXTRACTI64X4, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RORIW", - auxType: auxInt64, + name: "VEXTRACTI128128", + auxType: auxUInt8, argLen: 1, - asm: riscv.ARORIW, + asm: x86.AVEXTRACTI128, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RORW", - argLen: 2, - asm: riscv.ARORW, + name: "VGF2P8AFFINEINVQB128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVGF2P8AFFINEINVQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XNOR", - argLen: 2, - commutative: true, - asm: riscv.AXNOR, + name: "VGF2P8AFFINEINVQB256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVGF2P8AFFINEINVQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: riscv.AXOR, + name: "VGF2P8AFFINEINVQB512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVGF2P8AFFINEINVQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORI", - auxType: auxInt64, - argLen: 1, - asm: riscv.AXORI, + name: "VGF2P8AFFINEINVQBMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVGF2P8AFFINEINVQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MIN", - argLen: 2, - commutative: true, - asm: riscv.AMIN, + name: "VGF2P8AFFINEINVQBMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVGF2P8AFFINEINVQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MAX", - argLen: 2, - commutative: true, - asm: riscv.AMAX, + name: "VGF2P8AFFINEINVQBMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVGF2P8AFFINEINVQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MINU", - argLen: 2, - commutative: true, - asm: riscv.AMINU, + name: "VGF2P8AFFINEQB128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVGF2P8AFFINEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MAXU", - argLen: 2, - commutative: true, - asm: riscv.AMAXU, + name: "VGF2P8AFFINEQB256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVGF2P8AFFINEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SEQZ", - argLen: 1, - asm: riscv.ASEQZ, + name: "VGF2P8AFFINEQB512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVGF2P8AFFINEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SNEZ", - argLen: 1, - asm: riscv.ASNEZ, + name: "VGF2P8AFFINEQBMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVGF2P8AFFINEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLT", - argLen: 2, - asm: riscv.ASLT, + name: "VGF2P8AFFINEQBMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVGF2P8AFFINEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLTI", - auxType: auxInt64, - argLen: 1, - asm: riscv.ASLTI, + name: "VGF2P8AFFINEQBMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVGF2P8AFFINEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLTU", - argLen: 2, - asm: riscv.ASLTU, + name: "VINSERTF64X4512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVINSERTF64X4, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLTIU", - auxType: auxInt64, - argLen: 1, - asm: riscv.ASLTIU, + name: "VINSERTF128256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVINSERTF128, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredRound32F", - argLen: 1, - resultInArg0: true, + name: "VINSERTI64X4512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVINSERTI64X4, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredRound64F", - argLen: 1, - resultInArg0: true, + name: "VINSERTI128256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVINSERTI128, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: -1, - call: true, - reg: regInfo{ - clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, - { - name: "CALLtail", - auxType: auxCallOff, - argLen: -1, - call: true, - tailCall: true, - reg: regInfo{ - clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, - { - name: "CALLclosure", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "VPALIGNR128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPALIGNR, reg: regInfo{ inputs: []inputInfo{ - {1, 33554432}, // X26 - {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "VPALIGNR256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPALIGNR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "LoweredZero", - auxType: auxSymValAndOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, + name: "VPALIGNR512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPALIGNR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredZeroLoop", - auxType: auxSymValAndOff, - argLen: 2, - needIntTemp: true, - faultOnNilArg0: true, - symEffect: SymWrite, + name: "VPALIGNRMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPALIGNR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbersArg0: true, }, }, { - name: "LoweredMove", - auxType: auxSymValAndOff, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, - symEffect: SymWrite, + name: "VPALIGNRMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPALIGNR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632928}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632928}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 16, // X5 }, }, { - name: "LoweredMoveLoop", - auxType: auxSymValAndOff, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, - symEffect: SymWrite, + name: "VPALIGNRMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPALIGNR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632896}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632896}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 48, // X5 X6 - clobbersArg0: true, - clobbersArg1: true, }, }, { - name: "LoweredAtomicLoad8", - argLen: 2, - faultOnNilArg0: true, + name: "VPCLMULQDQ128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPCLMULQDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicLoad32", - argLen: 2, - faultOnNilArg0: true, + name: "VPCLMULQDQ256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPCLMULQDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicLoad64", - argLen: 2, - faultOnNilArg0: true, + name: "VPCLMULQDQ512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPCLMULQDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicStore8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPCMPB512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPCMPB, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicStore32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPCMPBMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPB, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicStore64", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPCMPBMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPB, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicExchange32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPCMPBMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicExchange64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPCMPD512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPCMPD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicAdd32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPCMPDMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicAdd64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPCMPDMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicCas32", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPCMPDMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicCas64", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPCMPQ512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPCMPQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicAnd32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: riscv.AAMOANDW, + name: "VPCMPQMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicOr32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: riscv.AAMOORW, + name: "VPCMPQMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VPCMPQMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - }, - }, - { - name: "LoweredGetClosurePtr", - argLen: 0, - reg: regInfo{ outputs: []outputInfo{ - {0, 33554432}, // X26 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VPCMPUB512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPCMPUB, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VPCMPUBMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUB, reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "VPCMPUBMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUB, reg: regInfo{ - clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 8388608}, // X24 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPubBarrier", - argLen: 1, - hasSideEffects: true, - asm: riscv.AFENCE, - reg: regInfo{}, - }, - { - name: "LoweredPanicBoundsRR", - auxType: auxInt64, + name: "VPCMPUBMasked512", + auxType: auxUInt8, argLen: 3, - call: true, + asm: x86.AVPCMPUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 - {1, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPanicBoundsRC", - auxType: auxPanicBoundsC, + name: "VPCMPUD512", + auxType: auxUInt8, argLen: 2, - call: true, + asm: x86.AVPCMPUD, reg: regInfo{ inputs: []inputInfo{ - {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPanicBoundsCR", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VPCMPUDMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUD, reg: regInfo{ inputs: []inputInfo{ - {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPanicBoundsCC", - auxType: auxPanicBoundsCC, - argLen: 1, - call: true, - reg: regInfo{}, - }, - { - name: "FADDS", - argLen: 2, - commutative: true, - asm: riscv.AFADDS, + name: "VPCMPUDMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FSUBS", - argLen: 2, - asm: riscv.AFSUBS, + name: "VPCMPUDMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMULS", - argLen: 2, - commutative: true, - asm: riscv.AFMULS, + name: "VPCMPUQ512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPCMPUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FDIVS", - argLen: 2, - asm: riscv.AFDIVS, + name: "VPCMPUQMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMADDS", - argLen: 3, - commutative: true, - asm: riscv.AFMADDS, + name: "VPCMPUQMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMSUBS", - argLen: 3, - commutative: true, - asm: riscv.AFMSUBS, + name: "VPCMPUQMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FNMADDS", - argLen: 3, - commutative: true, - asm: riscv.AFNMADDS, + name: "VPCMPUW512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPCMPUW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FNMSUBS", - argLen: 3, - commutative: true, - asm: riscv.AFNMSUBS, + name: "VPCMPUWMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FSQRTS", - argLen: 1, - asm: riscv.AFSQRTS, + name: "VPCMPUWMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FNEGS", - argLen: 1, - asm: riscv.AFNEGS, + name: "VPCMPUWMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPUW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMVSX", - argLen: 1, - asm: riscv.AFMVSX, + name: "VPCMPW512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPCMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMVXS", - argLen: 1, - asm: riscv.AFMVXS, + name: "VPCMPWMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FCVTSW", - argLen: 1, - asm: riscv.AFCVTSW, + name: "VPCMPWMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FCVTSL", - argLen: 1, - asm: riscv.AFCVTSL, + name: "VPCMPWMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPCMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FCVTWS", - argLen: 1, - asm: riscv.AFCVTWS, + name: "VPERM2F128256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPERM2F128, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTLS", - argLen: 1, - asm: riscv.AFCVTLS, + name: "VPERM2I128256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPERM2I128, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVF, + name: "VPEXTRB128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPEXTRB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "FMOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVF, + name: "VPEXTRD128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPEXTRD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "FEQS", - argLen: 2, - commutative: true, - asm: riscv.AFEQS, + name: "VPEXTRQ128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPEXTRQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "FNES", - argLen: 2, - commutative: true, - asm: riscv.AFNES, + name: "VPEXTRW128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPEXTRW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { - name: "FLTS", - argLen: 2, - asm: riscv.AFLTS, + name: "VPINSRB128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPINSRB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FLES", - argLen: 2, - asm: riscv.AFLES, + name: "VPINSRD128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPINSRD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredFMAXS", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: riscv.AFMAXS, + name: "VPINSRQ128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPINSRQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredFMINS", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: riscv.AFMINS, + name: "VPINSRW128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPINSRW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FADDD", - argLen: 2, - commutative: true, - asm: riscv.AFADDD, + name: "VPROLD128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPROLD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSUBD", - argLen: 2, - asm: riscv.AFSUBD, + name: "VPROLD256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPROLD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMULD", - argLen: 2, - commutative: true, - asm: riscv.AFMULD, + name: "VPROLD512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPROLD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FDIVD", - argLen: 2, - asm: riscv.AFDIVD, + name: "VPROLDMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPROLD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMADDD", - argLen: 3, - commutative: true, - asm: riscv.AFMADDD, + name: "VPROLDMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPROLD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMSUBD", - argLen: 3, - commutative: true, - asm: riscv.AFMSUBD, + name: "VPROLDMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPROLD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNMADDD", - argLen: 3, - commutative: true, - asm: riscv.AFNMADDD, + name: "VPROLQ128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPROLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNMSUBD", - argLen: 3, - commutative: true, - asm: riscv.AFNMSUBD, + name: "VPROLQ256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPROLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSQRTD", - argLen: 1, - asm: riscv.AFSQRTD, + name: "VPROLQ512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPROLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNEGD", - argLen: 1, - asm: riscv.AFNEGD, + name: "VPROLQMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPROLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FABSD", - argLen: 1, - asm: riscv.AFABSD, + name: "VPROLQMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPROLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSGNJD", - argLen: 2, - asm: riscv.AFSGNJD, + name: "VPROLQMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPROLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMVDX", - argLen: 1, - asm: riscv.AFMVDX, + name: "VPRORD128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPRORD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMVXD", - argLen: 1, - asm: riscv.AFMVXD, + name: "VPRORD256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPRORD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTDW", - argLen: 1, - asm: riscv.AFCVTDW, + name: "VPRORD512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPRORD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTDL", - argLen: 1, - asm: riscv.AFCVTDL, + name: "VPRORDMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPRORD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTWD", - argLen: 1, - asm: riscv.AFCVTWD, + name: "VPRORDMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPRORD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTLD", - argLen: 1, - asm: riscv.AFCVTLD, + name: "VPRORDMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPRORD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTDS", - argLen: 1, - asm: riscv.AFCVTDS, + name: "VPRORQ128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPRORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCVTSD", - argLen: 1, - asm: riscv.AFCVTSD, + name: "VPRORQ256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPRORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVD, + name: "VPRORQ512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPRORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVD, + name: "VPRORQMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPRORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FEQD", - argLen: 2, - commutative: true, - asm: riscv.AFEQD, + name: "VPRORQMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPRORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNED", - argLen: 2, - commutative: true, - asm: riscv.AFNED, + name: "VPRORQMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPRORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FLTD", - argLen: 2, - asm: riscv.AFLTD, + name: "VPSHLDD128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHLDD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FLED", - argLen: 2, - asm: riscv.AFLED, + name: "VPSHLDD256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHLDD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredFMIND", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: riscv.AFMIND, + name: "VPSHLDD512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHLDD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredFMAXD", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: riscv.AFMAXD, + name: "VPSHLDDMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHLDD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCLASSS", - argLen: 1, - asm: riscv.AFCLASSS, + name: "VPSHLDDMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHLDD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FCLASSD", - argLen: 1, - asm: riscv.AFCLASSD, + name: "VPSHLDDMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHLDD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, - { - name: "FADDS", - argLen: 2, - commutative: true, - resultInArg0: true, - asm: s390x.AFADDS, + name: "VPSHLDQ128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHLDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FADD", - argLen: 2, - commutative: true, - resultInArg0: true, - asm: s390x.AFADD, + name: "VPSHLDQ256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHLDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSUBS", - argLen: 2, - resultInArg0: true, - asm: s390x.AFSUBS, + name: "VPSHLDQ512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHLDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSUB", - argLen: 2, - resultInArg0: true, - asm: s390x.AFSUB, + name: "VPSHLDQMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHLDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMULS", - argLen: 2, - commutative: true, - resultInArg0: true, - asm: s390x.AFMULS, + name: "VPSHLDQMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHLDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMUL", - argLen: 2, - commutative: true, - resultInArg0: true, - asm: s390x.AFMUL, + name: "VPSHLDQMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHLDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FDIVS", - argLen: 2, - resultInArg0: true, - asm: s390x.AFDIVS, + name: "VPSHLDW128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHLDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FDIV", - argLen: 2, - resultInArg0: true, - asm: s390x.AFDIV, + name: "VPSHLDW256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHLDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNEGS", - argLen: 1, - clobberFlags: true, - asm: s390x.AFNEGS, + name: "VPSHLDW512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHLDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FNEG", - argLen: 1, - clobberFlags: true, - asm: s390x.AFNEG, + name: "VPSHLDWMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHLDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMADDS", - argLen: 3, - resultInArg0: true, - asm: s390x.AFMADDS, + name: "VPSHLDWMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHLDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMADD", - argLen: 3, - resultInArg0: true, - asm: s390x.AFMADD, + name: "VPSHLDWMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHLDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMSUBS", - argLen: 3, - resultInArg0: true, - asm: s390x.AFMSUBS, + name: "VPSHRDD128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHRDD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMSUB", - argLen: 3, - resultInArg0: true, - asm: s390x.AFMSUB, + name: "VPSHRDD256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHRDD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LPDFR", - argLen: 1, - asm: s390x.ALPDFR, + name: "VPSHRDD512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHRDD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LNDFR", - argLen: 1, - asm: s390x.ALNDFR, + name: "VPSHRDDMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHRDD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CPSDR", - argLen: 2, - asm: s390x.ACPSDR, + name: "VPSHRDDMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHRDD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "WFMAXDB", - argLen: 2, - asm: s390x.AWFMAXDB, + name: "VPSHRDDMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHRDD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "WFMAXSB", - argLen: 2, - asm: s390x.AWFMAXSB, + name: "VPSHRDQ128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHRDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "WFMINDB", - argLen: 2, - asm: s390x.AWFMINDB, + name: "VPSHRDQ256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHRDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "WFMINSB", - argLen: 2, - asm: s390x.AWFMINSB, + name: "VPSHRDQ512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHRDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FIDBR", - auxType: auxInt8, - argLen: 1, - asm: s390x.AFIDBR, + name: "VPSHRDQMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHRDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AFMOVS, + name: "VPSHRDQMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHRDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AFMOVD, + name: "VPSHRDQMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHRDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSconst", - auxType: auxFloat32, - argLen: 0, - rematerializeable: true, - asm: s390x.AFMOVS, + name: "VPSHRDW128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHRDW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: s390x.AFMOVD, + name: "VPSHRDW256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHRDW, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSloadidx", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: s390x.AFMOVS, + name: "VPSHRDW512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHRDW, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDloadidx", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: s390x.AFMOVD, + name: "VPSHRDWMasked128", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHRDW, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AFMOVS, + name: "VPSHRDWMasked256", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHRDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AFMOVD, + name: "VPSHRDWMasked512", + auxType: auxUInt8, + argLen: 3, + asm: x86.AVPSHRDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FMOVSstoreidx", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: s390x.AFMOVS, + name: "VPSHUFD128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSHUFD, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDstoreidx", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: s390x.AFMOVD, + name: "VPSHUFD256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSHUFD, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADD", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AADD, + name: "VPSHUFD512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSHUFD, reg: regInfo{ inputs: []inputInfo{ - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDW", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AADDW, + name: "VPSHUFDMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHUFD, reg: regInfo{ inputs: []inputInfo{ - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDconst", - auxType: auxInt32, - argLen: 1, - clobberFlags: true, - asm: s390x.AADD, + name: "VPSHUFDMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHUFD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDWconst", - auxType: auxInt32, - argLen: 1, - clobberFlags: true, - asm: s390x.AADDW, + name: "VPSHUFDMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHUFD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AADD, + name: "VPSHUFHW128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSHUFHW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AADDW, + name: "VPSHUFHW256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSHUFHW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUB", - argLen: 2, - clobberFlags: true, - asm: s390x.ASUB, + name: "VPSHUFHW512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSHUFHW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBW", - argLen: 2, - clobberFlags: true, - asm: s390x.ASUBW, + name: "VPSHUFHWMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHUFHW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ASUB, + name: "VPSHUFHWMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHUFHW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBWconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ASUBW, + name: "VPSHUFHWMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHUFHW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.ASUB, + name: "VPSHUFLW128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSHUFLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.ASUBW, + name: "VPSHUFLW256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSHUFLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULLD", - argLen: 2, - commutative: true, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULLD, + name: "VPSHUFLW512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSHUFLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULLW", - argLen: 2, - commutative: true, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULLW, + name: "VPSHUFLWMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHUFLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULLDconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULLD, + name: "VPSHUFLWMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHUFLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULLWconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULLW, + name: "VPSHUFLWMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSHUFLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULLDload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AMULLD, + name: "VPSLLD128const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULLWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AMULLW, + name: "VPSLLD256const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULHD", - argLen: 2, - commutative: true, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULHD, + name: "VPSLLD512const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MULHDU", - argLen: 2, - commutative: true, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULHDU, + name: "VPSLLDMasked128const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVD", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ADIVD, + name: "VPSLLDMasked256const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVW", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ADIVW, + name: "VPSLLDMasked512const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSLLD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "DIVDU", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ADIVDU, + name: "VPSLLQ128const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVWU", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ADIVWU, + name: "VPSLLQ256const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MODD", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMODD, + name: "VPSLLQ512const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MODW", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMODW, + name: "VPSLLQMasked128const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MODDU", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMODDU, + name: "VPSLLQMasked256const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MODWU", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMODWU, + name: "VPSLLQMasked512const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSLLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AAND, + name: "VPSLLW128const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDW", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AANDW, + name: "VPSLLW256const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDconst", - auxType: auxInt64, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AAND, + name: "VPSLLW512const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDWconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AANDW, + name: "VPSLLWMasked128const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AAND, + name: "VPSLLWMasked256const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ANDWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AANDW, + name: "VPSLLWMasked512const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSLLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AOR, + name: "VPSRAD128const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORW", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AORW, + name: "VPSRAD256const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORconst", - auxType: auxInt64, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AOR, + name: "VPSRAD512const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORWconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AORW, + name: "VPSRADMasked128const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AOR, + name: "VPSRADMasked256const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ORWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AORW, + name: "VPSRADMasked512const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRAD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AXOR, + name: "VPSRAQ128const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORW", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AXORW, + name: "VPSRAQ256const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORconst", - auxType: auxInt64, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AXOR, + name: "VPSRAQ512const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORWconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AXORW, + name: "VPSRAQMasked128const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AXOR, + name: "VPSRAQMasked256const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "XORWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AXORW, + name: "VPSRAQMasked512const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "ADDC", - argLen: 2, - commutative: true, - asm: s390x.AADDC, + name: "VPSRAW128const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDCconst", - auxType: auxInt16, + name: "VPSRAW256const", + auxType: auxUInt8, argLen: 1, - asm: s390x.AADDC, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDE", - argLen: 3, - commutative: true, - resultInArg0: true, - asm: s390x.AADDE, + name: "VPSRAW512const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBC", - argLen: 2, - asm: s390x.ASUBC, + name: "VPSRAWMasked128const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SUBE", - argLen: 3, - resultInArg0: true, - asm: s390x.ASUBE, + name: "VPSRAWMasked256const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMP", - argLen: 2, - asm: s390x.ACMP, + name: "VPSRAWMasked512const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRAW, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPW", - argLen: 2, - asm: s390x.ACMPW, + name: "VPSRLD128const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPU", - argLen: 2, - asm: s390x.ACMPU, + name: "VPSRLD256const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPWU", - argLen: 2, - asm: s390x.ACMPWU, + name: "VPSRLD512const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPconst", - auxType: auxInt32, - argLen: 1, - asm: s390x.ACMP, + name: "VPSRLDMasked128const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPWconst", - auxType: auxInt32, - argLen: 1, - asm: s390x.ACMPW, + name: "VPSRLDMasked256const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPUconst", - auxType: auxInt32, - argLen: 1, - asm: s390x.ACMPU, + name: "VPSRLDMasked512const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRLD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CMPWUconst", - auxType: auxInt32, + name: "VPSRLQ128const", + auxType: auxUInt8, argLen: 1, - asm: s390x.ACMPWU, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCMPS", - argLen: 2, - asm: s390x.ACEBR, + name: "VPSRLQ256const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCMP", - argLen: 2, - asm: s390x.AFCMPU, + name: "VPSRLQ512const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LTDBR", - argLen: 1, - asm: s390x.ALTDBR, + name: "VPSRLQMasked128const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LTEBR", - argLen: 1, - asm: s390x.ALTEBR, + name: "VPSRLQMasked256const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLD", - argLen: 2, - asm: s390x.ASLD, + name: "VPSRLQMasked512const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRLQ, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SLW", - argLen: 2, - asm: s390x.ASLW, + name: "VPSRLW128const", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLDconst", + name: "VPSRLW256const", auxType: auxUInt8, argLen: 1, - asm: s390x.ASLD, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLWconst", + name: "VPSRLW512const", auxType: auxUInt8, argLen: 1, - asm: s390x.ASLW, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRD", - argLen: 2, - asm: s390x.ASRD, + name: "VPSRLWMasked128const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRW", - argLen: 2, - asm: s390x.ASRW, + name: "VPSRLWMasked256const", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRDconst", + name: "VPSRLWMasked512const", auxType: auxUInt8, - argLen: 1, - asm: s390x.ASRD, + argLen: 2, + asm: x86.AVPSRLW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRWconst", - auxType: auxUInt8, - argLen: 1, - asm: s390x.ASRW, + name: "VPTERNLOGD128", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPTERNLOGD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAD", - argLen: 2, - clobberFlags: true, - asm: s390x.ASRAD, + name: "VPTERNLOGD256", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPTERNLOGD, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAW", - argLen: 2, - clobberFlags: true, - asm: s390x.ASRAW, + name: "VPTERNLOGD512", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPTERNLOGD, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRADconst", + name: "VPTERNLOGQ128", auxType: auxUInt8, - argLen: 1, - clobberFlags: true, - asm: s390x.ASRAD, + argLen: 3, + resultInArg0: true, + asm: x86.AVPTERNLOGQ, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SRAWconst", + name: "VPTERNLOGQ256", auxType: auxUInt8, - argLen: 1, - clobberFlags: true, - asm: s390x.ASRAW, + argLen: 3, + resultInArg0: true, + asm: x86.AVPTERNLOGQ, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RLLG", - argLen: 2, - asm: s390x.ARLLG, + name: "VPTERNLOGQ512", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPTERNLOGQ, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RLL", - argLen: 2, - asm: s390x.ARLL, + name: "VREDUCEPD128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RLLconst", + name: "VREDUCEPD256", auxType: auxUInt8, argLen: 1, - asm: s390x.ARLL, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RXSBG", - auxType: auxS390XRotateParams, - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ARXSBG, + name: "VREDUCEPD512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "RISBGZ", - auxType: auxS390XRotateParams, - argLen: 1, - clobberFlags: true, - asm: s390x.ARISBGZ, + name: "VREDUCEPDMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEG", - argLen: 1, - clobberFlags: true, - asm: s390x.ANEG, + name: "VREDUCEPDMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NEGW", - argLen: 1, - clobberFlags: true, - asm: s390x.ANEGW, + name: "VREDUCEPDMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NOT", - argLen: 1, - resultInArg0: true, - clobberFlags: true, + name: "VREDUCEPS128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "NOTW", - argLen: 1, - resultInArg0: true, - clobberFlags: true, + name: "VREDUCEPS256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSQRT", - argLen: 1, - asm: s390x.AFSQRT, + name: "VREDUCEPS512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FSQRTS", - argLen: 1, - asm: s390x.AFSQRTS, + name: "VREDUCEPSMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LOCGR", - auxType: auxS390XCCMask, - argLen: 3, - resultInArg0: true, - asm: s390x.ALOCGR, + name: "VREDUCEPSMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: s390x.AMOVB, + name: "VREDUCEPSMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBZreg", - argLen: 1, - asm: s390x.AMOVBZ, + name: "VRNDSCALEPD128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: s390x.AMOVH, + name: "VRNDSCALEPD256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHZreg", - argLen: 1, - asm: s390x.AMOVHZ, + name: "VRNDSCALEPD512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: s390x.AMOVW, + name: "VRNDSCALEPDMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWZreg", - argLen: 1, - asm: s390x.AMOVWZ, + name: "VRNDSCALEPDMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: s390x.AMOVD, + name: "VRNDSCALEPDMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVRNDSCALEPD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LDGR", - argLen: 1, - asm: s390x.ALDGR, + name: "VRNDSCALEPS128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LGDR", - argLen: 1, - asm: s390x.ALGDR, + name: "VRNDSCALEPS256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CFDBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACFDBRA, + name: "VRNDSCALEPS512", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CGDBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACGDBRA, + name: "VRNDSCALEPSMasked128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CFEBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACFEBRA, + name: "VRNDSCALEPSMasked256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CGEBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACGEBRA, + name: "VRNDSCALEPSMasked512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CEFBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACEFBRA, + name: "VROUNDPD128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVROUNDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CDFBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACDFBRA, + name: "VROUNDPD256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVROUNDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CEGBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACEGBRA, + name: "VROUNDPS128", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVROUNDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CDGBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACDGBRA, + name: "VROUNDPS256", + auxType: auxUInt8, + argLen: 1, + asm: x86.AVROUNDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLFEBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACLFEBR, + name: "VSHUFPD128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVSHUFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLFDBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACLFDBR, + name: "VSHUFPD256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVSHUFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLGEBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACLGEBR, + name: "VSHUFPD512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVSHUFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CLGDBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACLGDBR, + name: "VSHUFPS128", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVSHUFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CELFBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACELFBR, + name: "VSHUFPS256", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVSHUFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CDLFBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACDLFBR, + name: "VSHUFPS512", + auxType: auxUInt8, + argLen: 2, + asm: x86.AVSHUFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CELGBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACELGBR, + name: "VADDPD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CDLGBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACDLGBR, + name: "VADDPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LEDBR", - argLen: 1, - asm: s390x.ALEDBR, + name: "VADDPD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LDEBR", - argLen: 1, - asm: s390x.ALDEBR, + name: "VADDPDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, + name: "VADDPDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4295000064}, // SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDaddridx", + name: "VADDPDMasked512load", auxType: auxSymOff, - argLen: 2, - symEffect: SymAddr, + argLen: 4, + symEffect: SymRead, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4295000064}, // SP SB - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVBZ, + name: "VADDPS128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVB, + name: "VADDPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVHZ, + name: "VADDPS512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVH, + name: "VADDPSMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVWZ, + name: "VADDPSMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVW, + name: "VADDPSMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVD, + name: "VADDSUBPD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVADDSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWBR", - argLen: 1, - asm: s390x.AMOVWBR, + name: "VADDSUBPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVADDSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDBR", - argLen: 1, - asm: s390x.AMOVDBR, + name: "VADDSUBPS128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVADDSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHBRload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVHBR, + name: "VADDSUBPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVADDSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWBRload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVWBR, + name: "VAESDEC128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVAESDEC, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDBRload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVDBR, + name: "VAESDEC256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVAESDEC, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVB, + name: "VAESDECLAST128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVAESDECLAST, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVH, + name: "VAESDECLAST256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVAESDECLAST, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVW, + name: "VAESENC128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVAESENC, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVD, + name: "VAESENC256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVAESENC, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHBRstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVHBR, + name: "VAESENCLAST128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVAESENCLAST, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWBRstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVWBR, + name: "VAESENCLAST256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVAESENCLAST, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDBRstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVDBR, + name: "VAESIMC128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVAESIMC, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVC", - auxType: auxSymValAndOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, - symEffect: SymNone, - asm: s390x.AMVC, + name: "VBROADCASTSD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVBROADCASTSD, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBZloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVBZ, + name: "VBROADCASTSD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVBROADCASTSD, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVB, + name: "VBROADCASTSDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVBROADCASTSD, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHZloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVHZ, + name: "VBROADCASTSDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVBROADCASTSD, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVH, + name: "VBROADCASTSS128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWZloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVWZ, + name: "VBROADCASTSS256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVW, + name: "VBROADCASTSS512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVD, + name: "VBROADCASTSSMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHBRloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVHBR, + name: "VBROADCASTSSMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWBRloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVWBR, + name: "VBROADCASTSSMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVBROADCASTSS, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDBRloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVDBR, + name: "VCVTDQ2PD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVB, + name: "VCVTDQ2PD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVH, + name: "VCVTDQ2PDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVW, + name: "VCVTDQ2PDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVD, + name: "VCVTDQ2PS128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHBRstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVHBR, + name: "VCVTDQ2PS256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWBRstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVWBR, + name: "VCVTDQ2PS512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDBRstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVDBR, + name: "VCVTDQ2PSMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBstoreconst", - auxType: auxSymValAndOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVB, + name: "VCVTDQ2PSMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVHstoreconst", - auxType: auxSymValAndOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVH, + name: "VCVTDQ2PSMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWstoreconst", - auxType: auxSymValAndOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVW, + name: "VCVTPD2PS256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTPD2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDstoreconst", - auxType: auxSymValAndOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVD, + name: "VCVTPD2PSMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTPD2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "CLEAR", - auxType: auxSymValAndOff, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ACLEAR, + name: "VCVTPD2PSX128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTPD2PSX, reg: regInfo{ inputs: []inputInfo{ - {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - reg: regInfo{ - clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - }, - { - name: "CALLtail", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - tailCall: true, + name: "VCVTPD2PSXMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTPD2PSX, reg: regInfo{ - clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, - argLen: 3, - clobberFlags: true, - call: true, + name: "VCVTPD2PSY128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTPD2PSY, reg: regInfo{ inputs: []inputInfo{ - {1, 4096}, // R12 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: 2, - clobberFlags: true, - call: true, + name: "VCVTPD2PSYMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTPD2PSY, reg: regInfo{ inputs: []inputInfo{ - {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "InvertFlags", - argLen: 1, - reg: regInfo{}, - }, - { - name: "LoweredGetG", - argLen: 1, + name: "VCVTPS2PD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTPS2PD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "VCVTPS2PD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTPS2PD, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, outputs: []outputInfo{ - {0, 4096}, // R12 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VCVTPS2PDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTPS2PD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VCVTPS2PDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTPS2PD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - clobberFlags: true, - nilCheck: true, - faultOnNilArg0: true, + name: "VCVTQQ2PD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredRound32F", - argLen: 1, - resultInArg0: true, - zeroWidth: true, + name: "VCVTQQ2PD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredRound64F", - argLen: 1, - resultInArg0: true, - zeroWidth: true, + name: "VCVTQQ2PD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "VCVTQQ2PDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTQQ2PD, reg: regInfo{ - clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, outputs: []outputInfo{ - {0, 512}, // R9 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsRR", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VCVTQQ2PDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 - {1, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsRC", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VCVTQQ2PDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCR", - auxType: auxPanicBoundsC, - argLen: 2, - call: true, + name: "VCVTQQ2PS256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTQQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredPanicBoundsCC", - auxType: auxPanicBoundsCC, - argLen: 1, - call: true, - reg: regInfo{}, - }, - { - name: "FlagEQ", - argLen: 0, - reg: regInfo{}, - }, - { - name: "FlagLT", - argLen: 0, - reg: regInfo{}, - }, - { - name: "FlagGT", - argLen: 0, - reg: regInfo{}, - }, - { - name: "FlagOV", - argLen: 0, - reg: regInfo{}, - }, - { - name: "SYNC", - argLen: 1, - asm: s390x.ASYNC, - reg: regInfo{}, - }, - { - name: "MOVBZatomicload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVBZ, + name: "VCVTQQ2PSMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTQQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWZatomicload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVWZ, + name: "VCVTQQ2PSX128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTQQ2PSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDatomicload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVD, + name: "VCVTQQ2PSXMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTQQ2PSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVBatomicstore", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymWrite, - asm: s390x.AMOVB, + name: "VCVTQQ2PSY128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTQQ2PSY, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVWatomicstore", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymWrite, - asm: s390x.AMOVW, + name: "VCVTQQ2PSYMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTQQ2PSY, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MOVDatomicstore", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymWrite, - asm: s390x.AMOVD, + name: "VCVTTPD2DQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2DQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LAA", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ALAA, + name: "VCVTTPD2DQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2DQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LAAG", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ALAAG, + name: "VCVTTPD2DQX128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2DQX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "AddTupleFirst32", - argLen: 2, - reg: regInfo{}, - }, - { - name: "AddTupleFirst64", - argLen: 2, - reg: regInfo{}, - }, - { - name: "LAN", - argLen: 3, - clobberFlags: true, - hasSideEffects: true, - asm: s390x.ALAN, + name: "VCVTTPD2DQXMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2DQX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LANfloor", - argLen: 3, - clobberFlags: true, - hasSideEffects: true, - asm: s390x.ALAN, + name: "VCVTTPD2DQY128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2DQY, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2, // R1 }, }, { - name: "LAO", - argLen: 3, - clobberFlags: true, - hasSideEffects: true, - asm: s390x.ALAO, + name: "VCVTTPD2DQYMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2DQY, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LAOfloor", - argLen: 3, - clobberFlags: true, - hasSideEffects: true, - asm: s390x.ALAO, + name: "VCVTTPD2QQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2, // R1 }, }, { - name: "LoweredAtomicCas32", - auxType: auxSymOff, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ACS, + name: "VCVTTPD2QQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1}, // R0 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, - clobbers: 1, // R0 outputs: []outputInfo{ - {1, 0}, - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicCas64", - auxType: auxSymOff, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ACSG, + name: "VCVTTPD2QQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ inputs: []inputInfo{ - {1, 1}, // R0 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, - clobbers: 1, // R0 outputs: []outputInfo{ - {1, 0}, - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange32", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ACS, + name: "VCVTTPD2QQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {1, 0}, - {0, 1}, // R0 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredAtomicExchange64", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ACSG, + name: "VCVTTPD2QQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {1, 0}, - {0, 1}, // R0 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "FLOGR", - argLen: 1, - clobberFlags: true, - asm: s390x.AFLOGR, + name: "VCVTTPD2QQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, - clobbers: 2, // R1 outputs: []outputInfo{ - {0, 1}, // R0 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "POPCNT", - argLen: 1, - clobberFlags: true, - asm: s390x.APOPCNT, + name: "VCVTTPD2UDQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "MLGR", - argLen: 2, - asm: s390x.AMLGR, + name: "VCVTTPD2UDQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 8}, // R3 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4}, // R2 - {1, 8}, // R3 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "SumBytes2", - argLen: 1, - reg: regInfo{}, - }, - { - name: "SumBytes4", - argLen: 1, - reg: regInfo{}, - }, - { - name: "SumBytes8", - argLen: 1, - reg: regInfo{}, - }, - { - name: "STMG2", - auxType: auxSymOff, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMG, + name: "VCVTTPD2UDQX128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQX, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "STMG3", - auxType: auxSymOff, - argLen: 5, - clobberFlags: true, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMG, + name: "VCVTTPD2UDQXMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQX, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {3, 8}, // R3 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "STMG4", - auxType: auxSymOff, - argLen: 6, - clobberFlags: true, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMG, + name: "VCVTTPD2UDQY128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQY, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {3, 8}, // R3 - {4, 16}, // R4 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "STM2", - auxType: auxSymOff, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMY, + name: "VCVTTPD2UDQYMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQY, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "STM3", - auxType: auxSymOff, - argLen: 5, - clobberFlags: true, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMY, + name: "VCVTTPD2UQQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {3, 8}, // R3 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "STM4", - auxType: auxSymOff, - argLen: 6, - clobberFlags: true, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMY, + name: "VCVTTPD2UQQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {3, 8}, // R3 - {4, 16}, // R4 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VCVTTPD2UQQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 4}, // R2 - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 6, // R1 R2 }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, + name: "VCVTTPD2UQQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 2, // R1 - }, - }, - - { - name: "LoweredStaticCall", - auxType: auxCallOff, - argLen: 1, - call: true, - reg: regInfo{ - clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g - }, - }, - { - name: "LoweredTailCall", - auxType: auxCallOff, - argLen: 1, - call: true, - tailCall: true, - reg: regInfo{ - clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { - name: "LoweredClosureCall", - auxType: auxCallOff, - argLen: 3, - call: true, + name: "VCVTTPD2UQQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 - {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { - name: "LoweredInterCall", - auxType: auxCallOff, - argLen: 2, - call: true, + name: "VCVTTPD2UQQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, - clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { - name: "LoweredAddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, + name: "VCVTTPS2DQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 3, + name: "VCVTTPS2DQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 - {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 2, + name: "VCVTTPS2DQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, - }, - }, - { - name: "LoweredGetClosurePtr", - argLen: 0, - reg: regInfo{ outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VCVTTPS2DQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VCVTTPS2DQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VCVTTPS2DQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2DQ, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, - }, - }, - { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - reg: regInfo{ - clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "LoweredConvert", - argLen: 2, + name: "VCVTTPS2QQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "Select", - argLen: 3, - asm: wasm.ASelect, + name: "VCVTTPS2QQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Load8U", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load8U, + name: "VCVTTPS2QQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Load8S", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load8S, + name: "VCVTTPS2QQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2QQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Load16U", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load16U, + name: "VCVTTPS2UDQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Load16S", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load16S, + name: "VCVTTPS2UDQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Load32U", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load32U, + name: "VCVTTPS2UDQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Load32S", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load32S, + name: "VCVTTPS2UDQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Load", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load, + name: "VCVTTPS2UDQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Store8", - auxType: auxInt64, - argLen: 3, - asm: wasm.AI64Store8, + name: "VCVTTPS2UDQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Store16", - auxType: auxInt64, - argLen: 3, - asm: wasm.AI64Store16, + name: "VCVTTPS2UQQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2UQQ, reg: regInfo{ inputs: []inputInfo{ - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Store32", - auxType: auxInt64, - argLen: 3, - asm: wasm.AI64Store32, + name: "VCVTTPS2UQQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2UQQ, reg: regInfo{ inputs: []inputInfo{ - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Store", - auxType: auxInt64, - argLen: 3, - asm: wasm.AI64Store, + name: "VCVTTPS2UQQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2UQQ, reg: regInfo{ inputs: []inputInfo{ - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Load", - auxType: auxInt64, - argLen: 2, - asm: wasm.AF32Load, + name: "VCVTTPS2UQQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2UQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Load", - auxType: auxInt64, - argLen: 2, - asm: wasm.AF64Load, + name: "VCVTUDQ2PD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Store", - auxType: auxInt64, - argLen: 3, - asm: wasm.AF32Store, + name: "VCVTUDQ2PD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Store", - auxType: auxInt64, - argLen: 3, - asm: wasm.AF64Store, + name: "VCVTUDQ2PDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUDQ2PD, reg: regInfo{ inputs: []inputInfo{ - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Const", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, + name: "VCVTUDQ2PDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUDQ2PD, reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Const", - auxType: auxFloat32, - argLen: 0, - rematerializeable: true, + name: "VCVTUDQ2PS128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Const", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, + name: "VCVTUDQ2PS256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Eqz", - argLen: 1, - asm: wasm.AI64Eqz, + name: "VCVTUDQ2PS512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Eq", - argLen: 2, - asm: wasm.AI64Eq, + name: "VCVTUDQ2PSMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Ne", - argLen: 2, - asm: wasm.AI64Ne, + name: "VCVTUDQ2PSMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64LtS", - argLen: 2, - asm: wasm.AI64LtS, + name: "VCVTUDQ2PSMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUDQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64LtU", - argLen: 2, - asm: wasm.AI64LtU, + name: "VCVTUQQ2PD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64GtS", - argLen: 2, - asm: wasm.AI64GtS, + name: "VCVTUQQ2PD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64GtU", - argLen: 2, - asm: wasm.AI64GtU, + name: "VCVTUQQ2PD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64LeS", - argLen: 2, - asm: wasm.AI64LeS, + name: "VCVTUQQ2PDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64LeU", - argLen: 2, - asm: wasm.AI64LeU, + name: "VCVTUQQ2PDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64GeS", - argLen: 2, - asm: wasm.AI64GeS, + name: "VCVTUQQ2PDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64GeU", - argLen: 2, - asm: wasm.AI64GeU, + name: "VCVTUQQ2PS256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Eq", - argLen: 2, - asm: wasm.AF32Eq, + name: "VCVTUQQ2PSMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Ne", - argLen: 2, - asm: wasm.AF32Ne, + name: "VCVTUQQ2PSX128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Lt", - argLen: 2, - asm: wasm.AF32Lt, + name: "VCVTUQQ2PSXMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Gt", - argLen: 2, - asm: wasm.AF32Gt, + name: "VCVTUQQ2PSY128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PSY, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Le", - argLen: 2, - asm: wasm.AF32Le, + name: "VCVTUQQ2PSYMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTUQQ2PSY, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Ge", - argLen: 2, - asm: wasm.AF32Ge, + name: "VDIVPD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F64Eq", - argLen: 2, - asm: wasm.AF64Eq, + name: "VDIVPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F64Ne", - argLen: 2, - asm: wasm.AF64Ne, + name: "VDIVPD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Lt", - argLen: 2, - asm: wasm.AF64Lt, + name: "VDIVPDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Gt", - argLen: 2, - asm: wasm.AF64Gt, + name: "VDIVPDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Le", - argLen: 2, - asm: wasm.AF64Le, + name: "VDIVPDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Ge", - argLen: 2, - asm: wasm.AF64Ge, + name: "VDIVPS128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I64Add", - argLen: 2, - asm: wasm.AI64Add, + name: "VDIVPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I64AddConst", - auxType: auxInt64, - argLen: 1, - asm: wasm.AI64Add, + name: "VDIVPS512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Sub", - argLen: 2, - asm: wasm.AI64Sub, + name: "VDIVPSMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Mul", - argLen: 2, - asm: wasm.AI64Mul, + name: "VDIVPSMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64DivS", - argLen: 2, - asm: wasm.AI64DivS, + name: "VDIVPSMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64DivU", - argLen: 2, - asm: wasm.AI64DivU, + name: "VEXPANDPDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVEXPANDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64RemS", - argLen: 2, - asm: wasm.AI64RemS, + name: "VEXPANDPDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVEXPANDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64RemU", - argLen: 2, - asm: wasm.AI64RemU, + name: "VEXPANDPSMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVEXPANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64And", - argLen: 2, - asm: wasm.AI64And, + name: "VEXPANDPSMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVEXPANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Or", - argLen: 2, - asm: wasm.AI64Or, + name: "VFMADD213PD128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I64Xor", - argLen: 2, - asm: wasm.AI64Xor, + name: "VFMADD213PD256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I64Shl", - argLen: 2, - asm: wasm.AI64Shl, + name: "VFMADD213PD512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64ShrS", - argLen: 2, - asm: wasm.AI64ShrS, + name: "VFMADD213PDMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64ShrU", - argLen: 2, - asm: wasm.AI64ShrU, + name: "VFMADD213PDMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Neg", - argLen: 1, - asm: wasm.AF32Neg, + name: "VFMADD213PDMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Add", - argLen: 2, - asm: wasm.AF32Add, + name: "VFMADD213PS128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F32Sub", - argLen: 2, - asm: wasm.AF32Sub, + name: "VFMADD213PS256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F32Mul", - argLen: 2, - asm: wasm.AF32Mul, + name: "VFMADD213PS512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Div", - argLen: 2, - asm: wasm.AF32Div, + name: "VFMADD213PSMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Neg", - argLen: 1, - asm: wasm.AF64Neg, + name: "VFMADD213PSMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Add", - argLen: 2, - asm: wasm.AF64Add, + name: "VFMADD213PSMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Sub", - argLen: 2, - asm: wasm.AF64Sub, + name: "VFMADDSUB213PD128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F64Mul", - argLen: 2, - asm: wasm.AF64Mul, + name: "VFMADDSUB213PD256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F64Div", - argLen: 2, - asm: wasm.AF64Div, + name: "VFMADDSUB213PD512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64TruncSatF64S", - argLen: 1, - asm: wasm.AI64TruncSatF64S, + name: "VFMADDSUB213PDMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64TruncSatF64U", - argLen: 1, - asm: wasm.AI64TruncSatF64U, + name: "VFMADDSUB213PDMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64TruncSatF32S", - argLen: 1, - asm: wasm.AI64TruncSatF32S, + name: "VFMADDSUB213PDMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64TruncSatF32U", - argLen: 1, - asm: wasm.AI64TruncSatF32U, + name: "VFMADDSUB213PS128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F32ConvertI64S", - argLen: 1, - asm: wasm.AF32ConvertI64S, + name: "VFMADDSUB213PS256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F32ConvertI64U", - argLen: 1, - asm: wasm.AF32ConvertI64U, + name: "VFMADDSUB213PS512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64ConvertI64S", - argLen: 1, - asm: wasm.AF64ConvertI64S, + name: "VFMADDSUB213PSMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64ConvertI64U", - argLen: 1, - asm: wasm.AF64ConvertI64U, + name: "VFMADDSUB213PSMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32DemoteF64", - argLen: 1, - asm: wasm.AF32DemoteF64, + name: "VFMADDSUB213PSMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64PromoteF32", - argLen: 1, - asm: wasm.AF64PromoteF32, + name: "VFMSUBADD213PD128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I64Extend8S", - argLen: 1, - asm: wasm.AI64Extend8S, + name: "VFMSUBADD213PD256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I64Extend16S", - argLen: 1, - asm: wasm.AI64Extend16S, + name: "VFMSUBADD213PD512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "I64Extend32S", - argLen: 1, - asm: wasm.AI64Extend32S, + name: "VFMSUBADD213PDMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Sqrt", - argLen: 1, - asm: wasm.AF32Sqrt, + name: "VFMSUBADD213PDMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Trunc", - argLen: 1, - asm: wasm.AF32Trunc, + name: "VFMSUBADD213PDMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Ceil", - argLen: 1, - asm: wasm.AF32Ceil, + name: "VFMSUBADD213PS128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F32Floor", - argLen: 1, - asm: wasm.AF32Floor, + name: "VFMSUBADD213PS256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F32Nearest", - argLen: 1, - asm: wasm.AF32Nearest, + name: "VFMSUBADD213PS512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Abs", - argLen: 1, - asm: wasm.AF32Abs, + name: "VFMSUBADD213PSMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F32Copysign", - argLen: 2, - asm: wasm.AF32Copysign, + name: "VFMSUBADD213PSMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Sqrt", - argLen: 1, - asm: wasm.AF64Sqrt, + name: "VFMSUBADD213PSMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Trunc", - argLen: 1, - asm: wasm.AF64Trunc, + name: "VGF2P8MULB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVGF2P8MULB, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Ceil", - argLen: 1, - asm: wasm.AF64Ceil, + name: "VGF2P8MULB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVGF2P8MULB, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Floor", - argLen: 1, - asm: wasm.AF64Floor, + name: "VGF2P8MULBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVGF2P8MULB, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Nearest", - argLen: 1, - asm: wasm.AF64Nearest, + name: "VGF2P8MULBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVGF2P8MULB, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 }, }, }, { - name: "F64Abs", - argLen: 1, - asm: wasm.AF64Abs, + name: "VHADDPD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVHADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "F64Copysign", - argLen: 2, - asm: wasm.AF64Copysign, + name: "VHADDPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVHADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I64Ctz", - argLen: 1, - asm: wasm.AI64Ctz, + name: "VHADDPS128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVHADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I64Clz", - argLen: 1, - asm: wasm.AI64Clz, + name: "VHADDPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVHADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I32Rotl", - argLen: 2, - asm: wasm.AI32Rotl, + name: "VHSUBPD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVHSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I64Rotl", - argLen: 2, - asm: wasm.AI64Rotl, + name: "VHSUBPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVHSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "I64Popcnt", - argLen: 1, - asm: wasm.AI64Popcnt, + name: "VHSUBPS128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVHSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, - - { - name: "Add8", - argLen: 2, - commutative: true, - generic: true, - }, { - name: "Add16", - argLen: 2, - commutative: true, - generic: true, + name: "VHSUBPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVHSUBPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, }, { - name: "Add32", - argLen: 2, - commutative: true, - generic: true, + name: "VMAXPD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMAXPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, }, { - name: "Add64", - argLen: 2, - commutative: true, - generic: true, + name: "VMAXPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMAXPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, }, { - name: "AddPtr", - argLen: 2, - generic: true, + name: "VMAXPD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMAXPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, }, { - name: "Add32F", - argLen: 2, - commutative: true, - generic: true, + name: "VMAXPDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMAXPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, }, { - name: "Add64F", - argLen: 2, - commutative: true, - generic: true, + name: "VMAXPDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMAXPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, }, { - name: "Sub8", - argLen: 2, - generic: true, + name: "VMAXPDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMAXPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, }, { - name: "Sub16", - argLen: 2, - generic: true, + name: "VMAXPS128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMAXPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, }, { - name: "Sub32", - argLen: 2, - generic: true, + name: "VMAXPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMAXPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, }, { - name: "Sub64", - argLen: 2, - generic: true, + name: "VMAXPS512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMAXPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, }, { - name: "SubPtr", - argLen: 2, - generic: true, + name: "VMAXPSMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMAXPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, }, { - name: "Sub32F", - argLen: 2, - generic: true, + name: "VMAXPSMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMAXPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, }, { - name: "Sub64F", - argLen: 2, - generic: true, + name: "VMAXPSMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMAXPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, }, { - name: "Mul8", - argLen: 2, - commutative: true, - generic: true, + name: "VMINPD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMINPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, }, { - name: "Mul16", - argLen: 2, - commutative: true, - generic: true, + name: "VMINPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMINPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, }, { - name: "Mul32", - argLen: 2, - commutative: true, - generic: true, - }, + name: "VMINPD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMINPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMINPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMINPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMINPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPS128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMINPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VMINPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMINPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VMINPS512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMINPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPSMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMINPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPSMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMINPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPSMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMINPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMULPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VMULPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMULPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VMULPD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMULPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMULPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMULPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMULPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPS128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMULPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VMULPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMULPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VMULPS512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVMULPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPSMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMULPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPSMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMULPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPSMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVMULPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSB128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPABSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPABSB256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPABSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPABSBMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPABSB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSBMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPABSB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPABSD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPABSD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPABSD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPABSD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPABSD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPABSQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPABSQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPABSQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPABSQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPABSQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPABSQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSW128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPABSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPABSW256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPABSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPABSWMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPABSW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSWMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPABSW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKSSDW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPACKSSDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPACKSSDW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPACKSSDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPACKSSDW512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPACKSSDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKSSDWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPACKSSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKSSDWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPACKSSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKSSDWMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPACKSSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKUSDW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPACKUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPACKUSDW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPACKUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPACKUSDW512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPACKUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKUSDWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPACKUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKUSDWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPACKUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKUSDWMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPACKUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDSB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDSB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDSBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDSBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDSW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDSW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDSWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDSWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDUSB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDUSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDUSB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDUSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDUSBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDUSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDUSBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDUSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDUSW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDUSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDUSW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDUSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDUSWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDUSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDUSWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDUSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPADDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPADDWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPADDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAND128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPAND256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPANDD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPANDD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDN128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPANDN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPANDN256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPANDN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPANDND512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPANDND, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDNDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDND, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDNDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDND, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDNDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDND, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDNQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPANDNQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDNQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDNQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDNQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDNQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDNQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDNQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAVGB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPAVGB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPAVGB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPAVGB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPAVGBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPAVGB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAVGBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPAVGB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAVGW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPAVGW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPAVGW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPAVGW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPAVGWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPAVGW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAVGWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPAVGW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBLENDMDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPBLENDMD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBLENDMQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPBLENDMQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTB128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPBROADCASTB256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPBROADCASTB512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTBMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPBROADCASTB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTBMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPBROADCASTB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTBMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPBROADCASTB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPBROADCASTD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPBROADCASTD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPBROADCASTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPBROADCASTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPBROADCASTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPBROADCASTQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPBROADCASTQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPBROADCASTQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPBROADCASTQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPBROADCASTQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTW128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPBROADCASTW256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPBROADCASTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPEQB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPEQB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPEQB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPEQB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPEQD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPEQD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPEQD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPEQD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPEQQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPEQQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPEQQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPEQQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPEQQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPEQQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPEQW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPEQW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPEQW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPEQW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPGTB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPGTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPGTB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPGTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPGTD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPGTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPGTD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPGTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPGTD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPGTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPGTQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPGTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPGTQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPGTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPGTQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPGTQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPGTW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPGTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCMPGTW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPGTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPDPWSSD128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPDPWSSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPDPWSSD256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPDPWSSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPDPWSSD512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPDPWSSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPDPWSSDMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPDPWSSD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPDPWSSDMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPDPWSSD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPDPWSSDMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPDPWSSD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPERMD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2B128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2B, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2B256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2B, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2BMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2B, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2BMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2B, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2D128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2D, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2D256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2D, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2D512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2D, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2DMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2D, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2DMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2D, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2DMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2D, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PD128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PD256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PD512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PDMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PDMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PDMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PS128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PS256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PS512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PSMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PSMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2PSMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2PS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2Q128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2Q, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2Q256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2Q, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2Q512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2Q, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2QMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2Q, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2QMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2Q, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2QMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2Q, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2W128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2W, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2W256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2W, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2WMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2W, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMI2WMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPERMI2W, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMPD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMPDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMPDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPERMPS512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMPSMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMPSMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERMW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPERMWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPERMW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPEXPANDBMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPEXPANDB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPEXPANDBMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPEXPANDB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPEXPANDDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPEXPANDD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPEXPANDDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPEXPANDD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPEXPANDQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPEXPANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPEXPANDQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPEXPANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPEXPANDWMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPEXPANDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPEXPANDWMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPEXPANDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPHADDD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHADDD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHADDSW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHADDSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHADDSW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHADDSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHADDW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHADDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHADDW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHADDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHSUBD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHSUBD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHSUBSW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHSUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHSUBSW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHSUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHSUBW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHSUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPHSUBW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPHSUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPLZCNTD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPLZCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPLZCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPLZCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPLZCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPLZCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPLZCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPLZCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPLZCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPLZCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPLZCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPLZCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPLZCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMADDUBSW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMADDUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMADDUBSW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMADDUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMADDUBSWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMADDUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMADDUBSWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMADDUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMADDWD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMADDWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMADDWD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMADDWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMADDWDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMADDWD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMADDWDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMADDWD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXSB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXSBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXSD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXSD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXSD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXSQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXSQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXSQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXSQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXSQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXSQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXSW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXSWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXUB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXUBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXUB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXUB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXUD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXUD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXUD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXUD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXUD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXUD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXUD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXUD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXUQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXUQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXUQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXUQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXUQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXUQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXUW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMAXUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMAXUWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXUW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMAXUW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINSB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINSBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINSD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINSD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINSD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINSQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINSQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINSQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINSQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINSQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINSQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINSW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINSWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINUB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINUBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINUB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINUB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINUD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINUD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINUD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINUD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINUD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINUD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINUD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINUD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINUQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINUQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINUQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINUQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINUQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINUQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINUW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMINUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMINUWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINUW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMINUW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXBD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXBD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXBD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXBD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXBD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXBQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXBQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBW128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXBW256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXBW512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBWMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBWMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBWMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXDQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXDQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXDQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXDQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXDQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXDQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXWD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXWD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXWD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXWD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXWD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXWQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVSXWQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVSXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVSXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXBD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXBD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXBD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXBD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXBD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXBQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXBQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBW128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXBW256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXBW512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBWMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBWMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBWMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXDQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXDQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXDQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXDQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXDQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXDQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXWD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXWD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXWD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXWD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXWD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXWQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMOVZXWQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPMOVZXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMOVZXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULDQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULDQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULHUW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULHUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULHUW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULHUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULHUWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULHUW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULHUWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULHUW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULHW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULHW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULHW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULHW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULHWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULHW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULHWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULHW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULLD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULLD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULLW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULLWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULUDQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULUDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPMULUDQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPMULUDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPOPCNTB128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPOPCNTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTB256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPOPCNTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTBMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOPCNTB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTBMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOPCNTB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPOPCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPOPCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPOPCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOPCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOPCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOPCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTW128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPOPCNTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTW256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPOPCNTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTWMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOPCNTW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTWMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOPCNTW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOR128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPOR256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPORD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPORD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPORD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPORD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPORD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPORQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPORQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPORQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPORQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPROLVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPROLVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPROLVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPROLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPROLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPROLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPRORVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPRORVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPRORVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPRORVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPRORVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPRORVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSADBW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSADBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSADBW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSADBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSHLDVD128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVD256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVD512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVDMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVDMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVDMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVQ128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVQ256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVQ512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVQMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVQMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVQMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVW128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVW256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVWMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDVWMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHLDVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVD128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVD256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVD512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVDMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVDMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVDMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVQ128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVQ256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVQ512load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVQMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVQMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVQMasked512load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVW128load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVW256load", + auxType: auxSymOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVWMasked128load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDVWMasked256load", + auxType: auxSymOff, + argLen: 5, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPSHRDVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHUFB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSHUFB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHUFB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSHUFBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHUFB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHUFB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSIGNB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSIGNB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSIGNB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSIGNB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSIGND128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSIGND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSIGND256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSIGND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSIGNW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSIGNW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSIGNW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSIGNW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSLLVD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSLLVD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSLLVD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSLLVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSLLVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSLLVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSLLVQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSLLVQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSLLVW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSLLVW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSRAVD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSRAVD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRAVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRAVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRAVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRAVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRAVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRAVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRAVW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRAVW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSRLVD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSRLVD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRLVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRLVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRLVD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSRLVQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSRLVQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRLVW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSRLVW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBSB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBSB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBSBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBSBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBSW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBSW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBSWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBSWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBUSB128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBUSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBUSB256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBUSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBUSBMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBUSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBUSBMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBUSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBUSW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBUSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBUSW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBUSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBUSWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBUSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBUSWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBUSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBW128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBW256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSUBWMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBWMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSUBW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPUNPCKHDQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKHDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKHDQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKHDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKHDQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKHDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPUNPCKHQDQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKHQDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKHQDQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKHQDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKHQDQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKHQDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPUNPCKHWD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKHWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKHWD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKHWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKLDQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKLDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKLDQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKLDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKLDQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKLDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPUNPCKLQDQ128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKLQDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKLQDQ256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKLQDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKLQDQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKLQDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPUNPCKLWD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKLWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPUNPCKLWD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPUNPCKLWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPXOR128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPXOR256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPXORD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPXORD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPXORD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPXORD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPXORD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORQ512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPXORQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORQMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPXORQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORQMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPXORQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORQMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPXORQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRCP14PD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRCP14PD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRCP14PD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRCP14PD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRCP14PD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRCP14PD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PS512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRCP14PS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PSMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRCP14PS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PSMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRCP14PS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PSMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRCP14PS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCPPS128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRCPPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VRCPPS256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRCPPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VRSQRT14PD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRSQRT14PD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRSQRT14PD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRSQRT14PD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRSQRT14PD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRSQRT14PD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRSQRT14PD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PS512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRSQRT14PS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PSMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRSQRT14PS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PSMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRSQRT14PS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PSMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRSQRT14PS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRTPS128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VRSQRTPS256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSCALEFPD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSCALEFPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSCALEFPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSCALEFPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSCALEFPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSCALEFPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSCALEFPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPS128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSCALEFPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSCALEFPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPS512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSCALEFPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPSMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSCALEFPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPSMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSCALEFPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPSMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSCALEFPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPD128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVSQRTPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSQRTPD256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVSQRTPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSQRTPD512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVSQRTPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPDMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSQRTPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPDMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSQRTPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPDMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSQRTPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPS128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSQRTPS256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSQRTPS512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPSMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPSMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPSMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPD128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSUBPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSUBPD256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSUBPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSUBPD512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSUBPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPDMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSUBPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPDMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSUBPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPDMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSUBPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPS128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSUBPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSUBPS256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSUBPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSUBPS512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSUBPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPSMasked128load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSUBPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPSMasked256load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSUBPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPSMasked512load", + auxType: auxSymOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVSUBPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VAESKEYGENASSIST128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVAESKEYGENASSIST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VCMPPD128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCMPPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VCMPPD256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCMPPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VCMPPD512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCMPPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VCMPPDMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVCMPPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VCMPPDMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVCMPPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VCMPPDMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVCMPPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VCMPPS128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCMPPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VCMPPS256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCMPPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VCMPPS512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCMPPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VCMPPSMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVCMPPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VCMPPSMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVCMPPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VCMPPSMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVCMPPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VGF2P8AFFINEINVQB128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEINVQB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEINVQB256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEINVQB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEINVQB512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEINVQB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEINVQBMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEINVQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEINVQBMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEINVQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEINVQBMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEINVQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEQB128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEQB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEQB256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEQB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEQB512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEQB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEQBMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEQBMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8AFFINEQBMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVGF2P8AFFINEQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VINSERTF64X4512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVINSERTF64X4, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VINSERTF128256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVINSERTF128, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VINSERTI64X4512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVINSERTI64X4, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VINSERTI128256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVINSERTI128, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPALIGNR128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPALIGNR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPALIGNR256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPALIGNR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPALIGNRMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPALIGNR, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPALIGNRMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPALIGNR, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPCLMULQDQ128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCLMULQDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPCLMULQDQ256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCLMULQDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPCMPBMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPBMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPD512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPDMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPDMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPDMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPQ512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPQMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPQMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPQMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUBMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPUB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUBMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPUB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUD512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPUD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUDMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPUD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUDMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPUD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUDMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPUD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUQ512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPCMPUQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUQMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPUQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUQMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPUQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUQMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPUQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUWMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPUW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPUWMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPUW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPWMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPCMPWMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPCMPW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + }, + }, + }, + { + name: "VPERM2F128256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERM2F128, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPERM2I128256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPERM2I128, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPROLD128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPROLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLD256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPROLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLD512load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPROLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLDMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLDMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLDMasked512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLQ128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPROLQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLQ256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPROLQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLQ512load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPROLQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLQMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLQMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLQMasked512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPROLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORD128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPRORD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORD256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPRORD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORD512load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPRORD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORDMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORDMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORDMasked512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORQ128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPRORQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORQ256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPRORQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORQ512load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPRORQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORQMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORQMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORQMasked512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPRORQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDD128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHLDD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDD256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHLDD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDD512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHLDD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDDMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHLDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDDMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHLDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDDMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHLDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDQ128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHLDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDQ256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHLDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDQ512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHLDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDQMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHLDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDQMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHLDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDQMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHLDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDW128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHLDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDW256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHLDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDWMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHLDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHLDWMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHLDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDD128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHRDD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDD256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHRDD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDD512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHRDD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDDMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHRDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDDMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHRDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDDMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHRDD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDQ128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHRDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDQ256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHRDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDQ512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHRDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDQMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHRDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDQMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHRDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDQMasked512load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHRDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDW128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHRDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDW256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHRDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDWMasked128load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHRDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHRDWMasked256load", + auxType: auxSymValAndOff, + argLen: 4, + symEffect: SymRead, + asm: x86.AVPSHRDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFD128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSHUFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSHUFD256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSHUFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSHUFD512load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSHUFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFDMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHUFD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFDMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHUFD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFDMasked512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHUFD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFHW128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSHUFHW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSHUFHW256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSHUFHW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSHUFHWMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHUFHW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFHWMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHUFHW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFLW128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSHUFLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSHUFLW256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSHUFLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VPSHUFLWMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHUFLW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFLWMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSHUFLW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLD512constload", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSLLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLDMasked128constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLDMasked256constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLDMasked512constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLQ512constload", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSLLQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLQMasked128constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLQMasked256constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLQMasked512constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLWMasked128constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLWMasked256constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSLLW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAD512constload", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSRAD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRADMasked128constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRADMasked256constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRADMasked512constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAQ128constload", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSRAQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAQ256constload", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSRAQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAQ512constload", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSRAQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAQMasked128constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAQMasked256constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAQMasked512constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAWMasked128constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAWMasked256constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRAW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLD512constload", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSRLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLDMasked128constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLDMasked256constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLDMasked512constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLQ512constload", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVPSRLQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLQMasked128constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLQMasked256constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLQMasked512constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLWMasked128constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLWMasked256constload", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVPSRLW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPTERNLOGD128load", + auxType: auxSymValAndOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPTERNLOGD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPTERNLOGD256load", + auxType: auxSymValAndOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPTERNLOGD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPTERNLOGD512load", + auxType: auxSymValAndOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPTERNLOGD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPTERNLOGQ128load", + auxType: auxSymValAndOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPTERNLOGQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPTERNLOGQ256load", + auxType: auxSymValAndOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPTERNLOGQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPTERNLOGQ512load", + auxType: auxSymValAndOff, + argLen: 4, + resultInArg0: true, + symEffect: SymRead, + asm: x86.AVPTERNLOGQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPD128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVREDUCEPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPD256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVREDUCEPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPD512load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVREDUCEPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPDMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVREDUCEPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPDMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVREDUCEPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPDMasked512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVREDUCEPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPS128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVREDUCEPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPS256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVREDUCEPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPS512load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVREDUCEPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPSMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVREDUCEPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPSMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVREDUCEPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPSMasked512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVREDUCEPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPD128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRNDSCALEPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPD256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRNDSCALEPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPD512load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRNDSCALEPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPDMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRNDSCALEPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPDMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRNDSCALEPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPDMasked512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRNDSCALEPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPS128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRNDSCALEPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPS256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRNDSCALEPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPS512load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVRNDSCALEPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPSMasked128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRNDSCALEPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPSMasked256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRNDSCALEPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPSMasked512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVRNDSCALEPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VROUNDPD128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVROUNDPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VROUNDPD256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVROUNDPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VROUNDPS128load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVROUNDPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VROUNDPS256load", + auxType: auxSymValAndOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVROUNDPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSHUFPD128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSHUFPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSHUFPD256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSHUFPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSHUFPD512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSHUFPD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSHUFPS128load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSHUFPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSHUFPS256load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSHUFPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VSHUFPS512load", + auxType: auxSymValAndOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVSHUFPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VADDPDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVADDPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VADDPDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVADDPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VADDPDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVADDPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VADDPSMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVADDPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VADDPSMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVADDPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VADDPSMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVADDPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VBROADCASTSDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVBROADCASTSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VBROADCASTSDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVBROADCASTSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VBROADCASTSSMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVBROADCASTSS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VBROADCASTSSMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVBROADCASTSS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VBROADCASTSSMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVBROADCASTSS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTDQ2PDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTDQ2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTDQ2PDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTDQ2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTDQ2PSMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTDQ2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTDQ2PSMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTDQ2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTDQ2PSMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTDQ2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTPD2PSMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTPD2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTPD2PSXMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTPD2PSX, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTPD2PSYMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTPD2PSY, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTPS2PDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTPS2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTPS2PDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTPS2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTQQ2PDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTQQ2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTQQ2PDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTQQ2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTQQ2PDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTQQ2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTQQ2PSMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTQQ2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTQQ2PSXMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTQQ2PSX, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTQQ2PSYMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTQQ2PSY, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2DQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2DQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2DQXMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2DQX, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2DQYMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2DQY, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQXMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UDQX, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQYMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UDQY, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UQQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UQQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UQQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2DQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2DQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2DQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2DQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2DQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2DQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2QQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2QQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUDQ2PDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUDQ2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUDQ2PDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUDQ2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUDQ2PSMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUDQ2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUDQ2PSMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUDQ2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUDQ2PSMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUDQ2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUQQ2PDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUQQ2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUQQ2PDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUQQ2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUQQ2PDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUQQ2PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUQQ2PSMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUQQ2PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUQQ2PSXMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUQQ2PSX, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTUQQ2PSYMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTUQQ2PSY, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VDIVPDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVDIVPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VDIVPDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVDIVPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VDIVPDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVDIVPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VDIVPSMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVDIVPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VDIVPSMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVDIVPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VDIVPSMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVDIVPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8MULBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVGF2P8MULB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8MULBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVGF2P8MULB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VGF2P8MULBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVGF2P8MULB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMAXPDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMAXPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMAXPDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMAXPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMAXPDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMAXPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMAXPSMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMAXPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMAXPSMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMAXPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMAXPSMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMAXPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMINPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMINPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMINPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPSMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMINPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPSMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMINPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMINPSMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMINPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMULPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMULPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMULPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPSMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMULPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPSMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMULPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VMULPSMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVMULPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSBMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSBMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSBMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSWMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSWMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPABSWMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPABSW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKSSDWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPACKSSDW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKSSDWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPACKSSDW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKSSDWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPACKSSDW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKUSDWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPACKUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKUSDWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPACKUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPACKUSDWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPACKUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDSBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDSBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDSBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDSWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDSWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDSWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDUSBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDUSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDUSBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDUSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDUSBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDUSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDUSWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDUSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDUSWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDUSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDUSWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDUSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPADDWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPADDW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPANDD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPANDD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPANDD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPANDQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAVGBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPAVGB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAVGBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPAVGB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAVGBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPAVGB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAVGWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPAVGW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAVGWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPAVGW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPAVGWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPAVGW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTBMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTBMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTBMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTWMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTWMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPBROADCASTWMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPBROADCASTW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPLZCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPLZCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPLZCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPLZCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPLZCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPLZCNTQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPLZCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMADDUBSWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMADDUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMADDUBSWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMADDUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMADDUBSWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMADDUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMADDWDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMADDWD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMADDWDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMADDWD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMADDWDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMADDWD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXSWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMAXUWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMAXUW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINSWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMINUWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMINUW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVDBMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVDBMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVDBMasked128_512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVDWMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVDWMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVDWMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVQBMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVQBMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVQBMasked128_512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVQDMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVQD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVQDMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVQD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVQDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVQD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVQWMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVQW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVQWMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVQW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVQWMasked128_512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVQW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSDBMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSDBMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSDBMasked128_512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSDWMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSDWMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSDWMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSQBMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSQBMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSQBMasked128_512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSQDMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSQD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSQDMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSQD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSQDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSQD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSQWMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSQW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSQWMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSQW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSQWMasked128_512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSQW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSWBMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSWB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSWBMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSWB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSWBMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSWB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXBD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXBD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXBD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBWMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXBW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBWMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXBW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXBWMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXBW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXDQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXDQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXDQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXWD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXWD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXWD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVSXWQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVSXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSDBMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSDBMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSDBMasked128_512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSDB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSDWMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSDWMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSDWMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSDW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSQBMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSQBMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSQBMasked128_512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSQB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSQDMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSQD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSQDMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSQD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSQDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSQD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSQWMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSQW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSQWMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSQW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSQWMasked128_512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSQW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSWBMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSWB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSWBMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSWB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVUSWBMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVUSWB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVWBMasked128_128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVWB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVWBMasked128_256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVWB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVWBMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVWB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXBD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXBD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXBD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXBQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBWMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXBW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBWMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXBW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXBWMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXBW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXDQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXDQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXDQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXWD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXWD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXWD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMOVZXWQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPMOVZXWQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULHUWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULHUW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULHUWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULHUW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULHUWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULHUW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULHWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULHW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULHWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULHW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULHWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULHW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULLQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULLQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULLQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPMULLWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTBMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTBMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTBMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTB, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTWMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTWMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPOPCNTWMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVPOPCNTW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPORD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPORD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPORD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPORQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPORQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPORQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPORQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPROLVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPROLVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPROLVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPROLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPROLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLVQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPROLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPRORVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPRORVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPRORVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPRORVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPRORVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORVQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPRORVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHUFB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHUFB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSHUFB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSLLVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSLLVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSLLVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSLLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSLLVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSLLVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLVWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSLLVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRAVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRAVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRAVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRAVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRAVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRAVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRAVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRAVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAVWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRAVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRLVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRLVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRLVD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRLVQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRLVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRLVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLVWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSRLVW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBSBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBSBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBSBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBSWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBSWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBSWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBUSBMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBUSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBUSBMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBUSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBUSBMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBUSB, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBUSWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBUSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBUSWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBUSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBUSWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBUSW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBWMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBWMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSUBWMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPSUBW, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPXORD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPXORD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPXORD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORQMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPXORQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORQMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPXORQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPXORQMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVPXORQ, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRCP14PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRCP14PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRCP14PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PSMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRCP14PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PSMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRCP14PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRCP14PSMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRCP14PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRSQRT14PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRSQRT14PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRSQRT14PD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PSMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRSQRT14PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PSMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRSQRT14PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRSQRT14PSMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVRSQRT14PS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSCALEFPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSCALEFPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSCALEFPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPSMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSCALEFPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPSMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSCALEFPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSCALEFPSMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSCALEFPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPDMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVSQRTPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPDMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVSQRTPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPDMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVSQRTPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPSMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPSMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSQRTPSMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVSQRTPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPDMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSUBPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPDMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSUBPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPDMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSUBPD, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPSMasked128Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSUBPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPSMasked256Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSUBPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VSUBPSMasked512Merging", + argLen: 4, + resultInArg0: true, + asm: x86.AVSUBPS, + reg: regInfo{ + inputs: []inputInfo{ + {3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLDMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPROLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLDMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPROLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLDMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPROLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLQMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPROLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLQMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPROLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPROLQMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPROLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORDMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPRORD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORDMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPRORD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORDMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPRORD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORQMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPRORQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORQMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPRORQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPRORQMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPRORQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFDMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHUFD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFDMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHUFD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFDMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHUFD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFHWMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHUFHW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFHWMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHUFHW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFHWMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHUFHW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFLWMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHUFLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFLWMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHUFLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSHUFLWMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSHUFLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLDMasked128constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSLLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLDMasked256constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSLLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLDMasked512constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSLLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLQMasked128constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSLLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLQMasked256constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSLLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLQMasked512constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSLLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLWMasked128constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSLLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLWMasked256constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSLLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSLLWMasked512constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSLLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRADMasked128constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRAD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRADMasked256constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRAD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRADMasked512constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRAD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAQMasked128constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRAQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAQMasked256constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRAQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAQMasked512constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRAQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAWMasked128constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRAW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAWMasked256constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRAW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRAWMasked512constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRAW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLDMasked128constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLDMasked256constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLDMasked512constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRLD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLQMasked128constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLQMasked256constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLQMasked512constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRLQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLWMasked128constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLWMasked256constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VPSRLWMasked512constMerging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVPSRLW, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPDMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVREDUCEPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPDMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVREDUCEPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPDMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVREDUCEPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPSMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVREDUCEPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPSMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVREDUCEPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VREDUCEPSMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVREDUCEPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPDMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVRNDSCALEPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPDMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVRNDSCALEPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPDMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVRNDSCALEPD, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPSMasked128Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVRNDSCALEPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPSMasked256Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVRNDSCALEPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VRNDSCALEPSMasked512Merging", + auxType: auxUInt8, + argLen: 3, + resultInArg0: true, + asm: x86.AVRNDSCALEPS, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7 + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + + { + name: "ADD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 30719, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUB", + argLen: 2, + earlyOk: true, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSB", + argLen: 2, + earlyOk: true, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MUL", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "HMUL", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "HMULU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AMULLU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "CALLudiv", + argLen: 2, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2, v2: 0}}, // R1 + {1, regMask{v1: 1, v2: 0}}, // R0 + }, + clobbers: regMask{v1: 20492, v2: 0}, // R2 R3 R12 R14 + outputs: []outputInfo{ + {0, regMask{v1: 1, v2: 0}}, // R0 + {1, regMask{v1: 2, v2: 0}}, // R1 + }, + }, + }, + { + name: "ADDS", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDSconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADC", + argLen: 3, + commutative: true, + earlyOk: true, + asm: arm.AADC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADCconst", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AADC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADCS", + argLen: 3, + commutative: true, + asm: arm.AADC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBS", + argLen: 2, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBSconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBSconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SBC", + argLen: 3, + asm: arm.ASBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SBCconst", + auxType: auxInt32, + argLen: 2, + asm: arm.ASBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSCconst", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MULLU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AMULLU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MULA", + argLen: 3, + earlyOk: true, + asm: arm.AMULA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MULS", + argLen: 3, + earlyOk: true, + asm: arm.AMULS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDF", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AADDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "ADDD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "SUBF", + argLen: 2, + earlyOk: true, + asm: arm.ASUBF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "SUBD", + argLen: 2, + earlyOk: true, + asm: arm.ASUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MULF", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AMULF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MULD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "NMULF", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.ANMULF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "NMULD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.ANMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "DIVF", + argLen: 2, + earlyOk: true, + asm: arm.ADIVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + earlyOk: true, + asm: arm.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MULAF", + argLen: 3, + resultInArg0: true, + earlyOk: true, + asm: arm.AMULAF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MULAD", + argLen: 3, + resultInArg0: true, + earlyOk: true, + asm: arm.AMULAD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MULSF", + argLen: 3, + resultInArg0: true, + earlyOk: true, + asm: arm.AMULSF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MULSD", + argLen: 3, + resultInArg0: true, + earlyOk: true, + asm: arm.AMULSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMULAD", + argLen: 3, + resultInArg0: true, + asm: arm.AFMULAD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "BIC", + argLen: 2, + earlyOk: true, + asm: arm.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "BICconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "BFX", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.ABFX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "BFXU", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.ABFXU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MVN", + argLen: 1, + earlyOk: true, + asm: arm.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "NEGF", + argLen: 1, + earlyOk: true, + asm: arm.ANEGF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "NEGD", + argLen: 1, + earlyOk: true, + asm: arm.ANEGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "SQRTD", + argLen: 1, + earlyOk: true, + asm: arm.ASQRTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "SQRTF", + argLen: 1, + earlyOk: true, + asm: arm.ASQRTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "ABSD", + argLen: 1, + earlyOk: true, + asm: arm.AABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CLZ", + argLen: 1, + earlyOk: true, + asm: arm.ACLZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "REV", + argLen: 1, + earlyOk: true, + asm: arm.AREV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "REV16", + argLen: 1, + earlyOk: true, + asm: arm.AREV16, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RBIT", + argLen: 1, + earlyOk: true, + asm: arm.ARBIT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SLL", + argLen: 2, + earlyOk: true, + asm: arm.ASLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SLLconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.ASLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SRL", + argLen: 2, + earlyOk: true, + asm: arm.ASRL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SRLconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.ASRL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SRA", + argLen: 2, + earlyOk: true, + asm: arm.ASRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SRAconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.ASRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SRR", + argLen: 2, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SRRconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDshiftLL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDshiftRL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDshiftRA", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBshiftLL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBshiftRL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBshiftRA", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBshiftLL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBshiftRL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBshiftRA", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ANDshiftLL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ANDshiftRL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ANDshiftRA", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ORshiftLL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ORshiftRL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ORshiftRA", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "XORshiftLL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "XORshiftRL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "XORshiftRA", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "XORshiftRR", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "BICshiftLL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "BICshiftRL", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "BICshiftRA", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: arm.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MVNshiftLL", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MVNshiftRL", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MVNshiftRA", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: arm.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADCshiftLL", + auxType: auxInt32, + argLen: 3, + earlyOk: true, + asm: arm.AADC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADCshiftRL", + auxType: auxInt32, + argLen: 3, + earlyOk: true, + asm: arm.AADC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADCshiftRA", + auxType: auxInt32, + argLen: 3, + earlyOk: true, + asm: arm.AADC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SBCshiftLL", + auxType: auxInt32, + argLen: 3, + earlyOk: true, + asm: arm.ASBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SBCshiftRL", + auxType: auxInt32, + argLen: 3, + earlyOk: true, + asm: arm.ASBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SBCshiftRA", + auxType: auxInt32, + argLen: 3, + earlyOk: true, + asm: arm.ASBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSCshiftLL", + auxType: auxInt32, + argLen: 3, + earlyOk: true, + asm: arm.ARSC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSCshiftRL", + auxType: auxInt32, + argLen: 3, + earlyOk: true, + asm: arm.ARSC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSCshiftRA", + auxType: auxInt32, + argLen: 3, + earlyOk: true, + asm: arm.ARSC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDSshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDSshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDSshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBSshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBSshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBSshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBSshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBSshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBSshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDshiftLLreg", + argLen: 3, + earlyOk: true, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDshiftRLreg", + argLen: 3, + earlyOk: true, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDshiftRAreg", + argLen: 3, + earlyOk: true, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBshiftLLreg", + argLen: 3, + earlyOk: true, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBshiftRLreg", + argLen: 3, + earlyOk: true, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBshiftRAreg", + argLen: 3, + earlyOk: true, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBshiftLLreg", + argLen: 3, + earlyOk: true, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBshiftRLreg", + argLen: 3, + earlyOk: true, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBshiftRAreg", + argLen: 3, + earlyOk: true, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ANDshiftLLreg", + argLen: 3, + earlyOk: true, + asm: arm.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ANDshiftRLreg", + argLen: 3, + earlyOk: true, + asm: arm.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ANDshiftRAreg", + argLen: 3, + earlyOk: true, + asm: arm.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ORshiftLLreg", + argLen: 3, + earlyOk: true, + asm: arm.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ORshiftRLreg", + argLen: 3, + earlyOk: true, + asm: arm.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ORshiftRAreg", + argLen: 3, + earlyOk: true, + asm: arm.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "XORshiftLLreg", + argLen: 3, + earlyOk: true, + asm: arm.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "XORshiftRLreg", + argLen: 3, + earlyOk: true, + asm: arm.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "XORshiftRAreg", + argLen: 3, + earlyOk: true, + asm: arm.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "BICshiftLLreg", + argLen: 3, + earlyOk: true, + asm: arm.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "BICshiftRLreg", + argLen: 3, + earlyOk: true, + asm: arm.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "BICshiftRAreg", + argLen: 3, + earlyOk: true, + asm: arm.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MVNshiftLLreg", + argLen: 2, + earlyOk: true, + asm: arm.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MVNshiftRLreg", + argLen: 2, + earlyOk: true, + asm: arm.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MVNshiftRAreg", + argLen: 2, + earlyOk: true, + asm: arm.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADCshiftLLreg", + argLen: 4, + earlyOk: true, + asm: arm.AADC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADCshiftRLreg", + argLen: 4, + earlyOk: true, + asm: arm.AADC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADCshiftRAreg", + argLen: 4, + earlyOk: true, + asm: arm.AADC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SBCshiftLLreg", + argLen: 4, + earlyOk: true, + asm: arm.ASBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SBCshiftRLreg", + argLen: 4, + earlyOk: true, + asm: arm.ASBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SBCshiftRAreg", + argLen: 4, + earlyOk: true, + asm: arm.ASBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSCshiftLLreg", + argLen: 4, + earlyOk: true, + asm: arm.ARSC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSCshiftRLreg", + argLen: 4, + earlyOk: true, + asm: arm.ARSC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSCshiftRAreg", + argLen: 4, + earlyOk: true, + asm: arm.ARSC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDSshiftLLreg", + argLen: 3, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDSshiftRLreg", + argLen: 3, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "ADDSshiftRAreg", + argLen: 3, + asm: arm.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBSshiftLLreg", + argLen: 3, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBSshiftRLreg", + argLen: 3, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SUBSshiftRAreg", + argLen: 3, + asm: arm.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBSshiftLLreg", + argLen: 3, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBSshiftRLreg", + argLen: 3, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "RSBSshiftRAreg", + argLen: 3, + asm: arm.ARSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "CMP", + argLen: 2, + asm: arm.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "CMPconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "CMN", + argLen: 2, + commutative: true, + asm: arm.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "CMNconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "TST", + argLen: 2, + commutative: true, + asm: arm.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "TSTconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "TEQ", + argLen: 2, + commutative: true, + asm: arm.ATEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "TEQconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ATEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "CMPF", + argLen: 2, + asm: arm.ACMPF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CMPD", + argLen: 2, + asm: arm.ACMPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CMPshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "CMPshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "CMPshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "CMNshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "CMNshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "CMNshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "TSTshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "TSTshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "TSTshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "TEQshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ATEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "TEQshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ATEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "TEQshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ATEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "CMPshiftLLreg", + argLen: 3, + asm: arm.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "CMPshiftRLreg", + argLen: 3, + asm: arm.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "CMPshiftRAreg", + argLen: 3, + asm: arm.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "CMNshiftLLreg", + argLen: 3, + asm: arm.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "CMNshiftRLreg", + argLen: 3, + asm: arm.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "CMNshiftRAreg", + argLen: 3, + asm: arm.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "TSTshiftLLreg", + argLen: 3, + asm: arm.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "TSTshiftRLreg", + argLen: 3, + asm: arm.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "TSTshiftRAreg", + argLen: 3, + asm: arm.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "TEQshiftLLreg", + argLen: 3, + asm: arm.ATEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "TEQshiftRLreg", + argLen: 3, + asm: arm.ATEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "TEQshiftRAreg", + argLen: 3, + asm: arm.ATEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "CMPF0", + argLen: 1, + asm: arm.ACMPF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CMPD0", + argLen: 1, + asm: arm.ACMPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVWconst", + auxType: auxInt32, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: arm.AMOVW, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVFconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: arm.AMOVF, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: arm.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVWaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + earlyOk: true, + symEffect: SymAddr, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294975488, v2: 0}}, // SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVFload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + }, + }, + { + name: "MOVFstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVWloadidx", + argLen: 3, + addrSinkArg0: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVWloadshiftLL", + auxType: auxInt32, + argLen: 3, + addrSinkArg0: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVWloadshiftRL", + auxType: auxInt32, + argLen: 3, + addrSinkArg0: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVWloadshiftRA", + auxType: auxInt32, + argLen: 3, + addrSinkArg0: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVBUloadidx", + argLen: 3, + addrSinkArg0: true, + asm: arm.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVBloadidx", + argLen: 3, + addrSinkArg0: true, + asm: arm.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVHUloadidx", + argLen: 3, + addrSinkArg0: true, + asm: arm.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVHloadidx", + argLen: 3, + addrSinkArg0: true, + asm: arm.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVWstoreidx", + argLen: 4, + addrSinkArg0: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + }, + }, + { + name: "MOVWstoreshiftLL", + auxType: auxInt32, + argLen: 4, + addrSinkArg0: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + }, + }, + { + name: "MOVWstoreshiftRL", + auxType: auxInt32, + argLen: 4, + addrSinkArg0: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + }, + }, + { + name: "MOVWstoreshiftRA", + auxType: auxInt32, + argLen: 4, + addrSinkArg0: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + }, + }, + { + name: "MOVBstoreidx", + argLen: 4, + addrSinkArg0: true, + asm: arm.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + }, + }, + { + name: "MOVHstoreidx", + argLen: 4, + addrSinkArg0: true, + asm: arm.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + earlyOk: true, + asm: arm.AMOVBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVBUreg", + argLen: 1, + earlyOk: true, + asm: arm.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + earlyOk: true, + asm: arm.AMOVHS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVHUreg", + argLen: 1, + earlyOk: true, + asm: arm.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + earlyOk: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVWnop", + argLen: 1, + resultInArg0: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVWF", + argLen: 1, + earlyOk: true, + asm: arm.AMOVWF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2147483648, v2: 0}, // F15 + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVWD", + argLen: 1, + earlyOk: true, + asm: arm.AMOVWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2147483648, v2: 0}, // F15 + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVWUF", + argLen: 1, + earlyOk: true, + asm: arm.AMOVWF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2147483648, v2: 0}, // F15 + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVWUD", + argLen: 1, + earlyOk: true, + asm: arm.AMOVWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2147483648, v2: 0}, // F15 + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVFW", + argLen: 1, + earlyOk: true, + asm: arm.AMOVFW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + clobbers: regMask{v1: 2147483648, v2: 0}, // F15 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVDW", + argLen: 1, + earlyOk: true, + asm: arm.AMOVDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + clobbers: regMask{v1: 2147483648, v2: 0}, // F15 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVFWU", + argLen: 1, + earlyOk: true, + asm: arm.AMOVFW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + clobbers: regMask{v1: 2147483648, v2: 0}, // F15 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVDWU", + argLen: 1, + earlyOk: true, + asm: arm.AMOVDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + clobbers: regMask{v1: 2147483648, v2: 0}, // F15 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MOVFD", + argLen: 1, + earlyOk: true, + asm: arm.AMOVFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVDF", + argLen: 1, + earlyOk: true, + asm: arm.AMOVDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CMOVWHSconst", + auxType: auxInt32, + argLen: 2, + resultInArg0: true, + earlyOk: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "CMOVWLSconst", + auxType: auxInt32, + argLen: 2, + resultInArg0: true, + earlyOk: true, + asm: arm.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "SRAcond", + argLen: 3, + earlyOk: true, + asm: arm.ASRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: regMask{v1: 4294924287, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: regMask{v1: 4294924287, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLtailinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 4294924287, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: 3, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 128, v2: 0}}, // R7 + {0, regMask{v1: 29695, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 + }, + clobbers: regMask{v1: 4294924287, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 4294924287, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + }, + }, + { + name: "Equal", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "NotEqual", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "LessThan", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "LessEqual", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "GreaterThan", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "GreaterEqual", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "LessThanU", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "LessEqualU", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "GreaterThanU", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "GreaterEqualU", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "DUFFZERO", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2, v2: 0}}, // R1 + {1, regMask{v1: 1, v2: 0}}, // R0 + }, + clobbers: regMask{v1: 20482, v2: 0}, // R1 R12 R14 + }, + }, + { + name: "DUFFCOPY", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4, v2: 0}}, // R2 + {1, regMask{v1: 2, v2: 0}}, // R1 + }, + clobbers: regMask{v1: 20487, v2: 0}, // R0 R1 R2 R12 R14 + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2, v2: 0}}, // R1 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2, v2: 0}, // R1 + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4, v2: 0}}, // R2 + {1, regMask{v1: 2, v2: 0}}, // R1 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 6, v2: 0}, // R1 R2 + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 128, v2: 0}}, // R7 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "LoweredPanicBoundsRR", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 5119, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 + {1, regMask{v1: 5119, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 + }, + }, + }, + { + name: "LoweredPanicBoundsRC", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 5119, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 + }, + }, + }, + { + name: "LoweredPanicBoundsCR", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 5119, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 + }, + }, + }, + { + name: "LoweredPanicBoundsCC", + auxType: auxPanicBoundsCC, + argLen: 1, + call: true, + reg: regInfo{}, + }, + { + name: "LoweredPanicExtendRR", + auxType: auxInt64, + argLen: 4, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 15, v2: 0}}, // R0 R1 R2 R3 + {1, regMask{v1: 15, v2: 0}}, // R0 R1 R2 R3 + {2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "LoweredPanicExtendRC", + auxType: auxPanicBoundsC, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 15, v2: 0}}, // R0 R1 R2 R3 + {1, regMask{v1: 15, v2: 0}}, // R0 R1 R2 R3 + }, + }, + }, + { + name: "FlagConstant", + auxType: auxFlagConstant, + argLen: 0, + reg: regInfo{}, + }, + { + name: "InvertFlags", + argLen: 1, + reg: regInfo{}, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: regMask{v1: 4294922240, v2: 0}, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + outputs: []outputInfo{ + {0, regMask{v1: 256, v2: 0}}, // R8 + }, + }, + }, + + { + name: "ADCSflags", + argLen: 3, + commutative: true, + asm: arm64.AADCS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ADCzerocarry", + argLen: 1, + earlyOk: true, + asm: arm64.AADC, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ADD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ADDconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1476395007, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ADDSconstflags", + auxType: auxInt64, + argLen: 1, + asm: arm64.AADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ADDSflags", + argLen: 2, + commutative: true, + asm: arm64.AADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SUB", + argLen: 2, + earlyOk: true, + asm: arm64.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SUBconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SBCSflags", + argLen: 3, + asm: arm64.ASBCS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SUBSflags", + argLen: 2, + asm: arm64.ASUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MUL", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MULW", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AMULW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MNEG", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AMNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MNEGW", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AMNEGW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MULH", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.ASMULH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "UMULH", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AUMULH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MULL", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.ASMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "UMULL", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AUMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "DIV", + argLen: 2, + earlyOk: true, + asm: arm64.ASDIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "UDIV", + argLen: 2, + earlyOk: true, + asm: arm64.AUDIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "DIVW", + argLen: 2, + earlyOk: true, + asm: arm64.ASDIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "UDIVW", + argLen: 2, + earlyOk: true, + asm: arm64.AUDIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOD", + argLen: 2, + earlyOk: true, + asm: arm64.AREM, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "UMOD", + argLen: 2, + earlyOk: true, + asm: arm64.AUREM, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MODW", + argLen: 2, + earlyOk: true, + asm: arm64.AREMW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "UMODW", + argLen: 2, + earlyOk: true, + asm: arm64.AUREMW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FADDS", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AFADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FADDD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AFADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSUBS", + argLen: 2, + earlyOk: true, + asm: arm64.AFSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSUBD", + argLen: 2, + earlyOk: true, + asm: arm64.AFSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMULS", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AFMULS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMULD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AFMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMULS", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AFNMULS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMULD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AFNMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FDIVS", + argLen: 2, + earlyOk: true, + asm: arm64.AFDIVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FDIVD", + argLen: 2, + earlyOk: true, + asm: arm64.AFDIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: arm64.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "BIC", + argLen: 2, + earlyOk: true, + asm: arm64.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "EON", + argLen: 2, + earlyOk: true, + asm: arm64.AEON, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ORN", + argLen: 2, + earlyOk: true, + asm: arm64.AORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MVN", + argLen: 1, + earlyOk: true, + asm: arm64.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NEG", + argLen: 1, + earlyOk: true, + asm: arm64.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NEGSflags", + argLen: 1, + asm: arm64.ANEGS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NGCzerocarry", + argLen: 1, + earlyOk: true, + asm: arm64.ANGC, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FABSD", + argLen: 1, + earlyOk: true, + asm: arm64.AFABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FABSS", + argLen: 1, + earlyOk: true, + asm: arm64.AFABSS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNEGS", + argLen: 1, + earlyOk: true, + asm: arm64.AFNEGS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNEGD", + argLen: 1, + earlyOk: true, + asm: arm64.AFNEGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSQRTD", + argLen: 1, + earlyOk: true, + asm: arm64.AFSQRTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSQRTS", + argLen: 1, + earlyOk: true, + asm: arm64.AFSQRTS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMIND", + argLen: 2, + earlyOk: true, + asm: arm64.AFMIND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMINS", + argLen: 2, + earlyOk: true, + asm: arm64.AFMINS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMAXD", + argLen: 2, + earlyOk: true, + asm: arm64.AFMAXD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMAXS", + argLen: 2, + earlyOk: true, + asm: arm64.AFMAXS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "REV", + argLen: 1, + earlyOk: true, + asm: arm64.AREV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "REVW", + argLen: 1, + earlyOk: true, + asm: arm64.AREVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "REV16", + argLen: 1, + earlyOk: true, + asm: arm64.AREV16, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "REV16W", + argLen: 1, + earlyOk: true, + asm: arm64.AREV16W, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "RBIT", + argLen: 1, + earlyOk: true, + asm: arm64.ARBIT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "RBITW", + argLen: 1, + earlyOk: true, + asm: arm64.ARBITW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "CLZ", + argLen: 1, + earlyOk: true, + asm: arm64.ACLZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "CLZW", + argLen: 1, + earlyOk: true, + asm: arm64.ACLZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "VCNT", + argLen: 1, + earlyOk: true, + asm: arm64.AVCNT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUADDLV", + argLen: 1, + earlyOk: true, + asm: arm64.AVUADDLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LoweredRound32F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LoweredRound64F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMADDS", + argLen: 3, + earlyOk: true, + asm: arm64.AFMADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMADDD", + argLen: 3, + earlyOk: true, + asm: arm64.AFMADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMADDS", + argLen: 3, + earlyOk: true, + asm: arm64.AFNMADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMADDD", + argLen: 3, + earlyOk: true, + asm: arm64.AFNMADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMSUBS", + argLen: 3, + earlyOk: true, + asm: arm64.AFMSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMSUBD", + argLen: 3, + earlyOk: true, + asm: arm64.AFMSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMSUBS", + argLen: 3, + earlyOk: true, + asm: arm64.AFNMSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMSUBD", + argLen: 3, + earlyOk: true, + asm: arm64.AFNMSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MADD", + argLen: 3, + earlyOk: true, + asm: arm64.AMADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MADDW", + argLen: 3, + earlyOk: true, + asm: arm64.AMADDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MSUB", + argLen: 3, + earlyOk: true, + asm: arm64.AMSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MSUBW", + argLen: 3, + earlyOk: true, + asm: arm64.AMSUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SLL", + argLen: 2, + earlyOk: true, + asm: arm64.ALSL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SLLconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.ALSL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SRL", + argLen: 2, + earlyOk: true, + asm: arm64.ALSR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SRLconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.ALSR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SRA", + argLen: 2, + earlyOk: true, + asm: arm64.AASR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SRAconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.AASR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ROR", + argLen: 2, + earlyOk: true, + asm: arm64.AROR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "RORW", + argLen: 2, + earlyOk: true, + asm: arm64.ARORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "RORconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.AROR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "RORWconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.ARORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "EXTRconst", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AEXTR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "EXTRWconst", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AEXTRW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "CMP", + argLen: 2, + asm: arm64.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMPconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMPW", + argLen: 2, + asm: arm64.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMPWconst", + auxType: auxInt32, + argLen: 1, + asm: arm64.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMN", + argLen: 2, + commutative: true, + asm: arm64.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMNconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMNW", + argLen: 2, + commutative: true, + asm: arm64.ACMNW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMNWconst", + auxType: auxInt32, + argLen: 1, + asm: arm64.ACMNW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "TST", + argLen: 2, + commutative: true, + asm: arm64.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "TSTconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "TSTW", + argLen: 2, + commutative: true, + asm: arm64.ATSTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "TSTWconst", + auxType: auxInt32, + argLen: 1, + asm: arm64.ATSTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "FCMPS", + argLen: 2, + asm: arm64.AFCMPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCMPD", + argLen: 2, + asm: arm64.AFCMPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCMPS0", + argLen: 1, + asm: arm64.AFCMPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCMPD0", + argLen: 1, + asm: arm64.AFCMPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MVNshiftLL", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MVNshiftRL", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MVNshiftRA", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MVNshiftRO", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.AMVN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NEGshiftLL", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NEGshiftRL", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NEGshiftRA", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: arm64.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ADDshiftLL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ADDshiftRL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ADDshiftRA", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SUBshiftLL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SUBshiftRL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SUBshiftRA", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ANDshiftLL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ANDshiftRL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ANDshiftRA", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ANDshiftRO", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ORshiftLL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ORshiftRL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ORshiftRA", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ORshiftRO", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "XORshiftLL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "XORshiftRL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "XORshiftRA", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "XORshiftRO", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "BICshiftLL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "BICshiftRL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "BICshiftRA", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "BICshiftRO", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.ABIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "EONshiftLL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AEON, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "EONshiftRL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AEON, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "EONshiftRA", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AEON, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "EONshiftRO", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AEON, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ORNshiftLL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ORNshiftRL", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ORNshiftRA", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "ORNshiftRO", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: arm64.AORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "CMPshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMPshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMPshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMNshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMNshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CMNshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "TSTshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "TSTshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "TSTshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "TSTshiftRO", + auxType: auxInt64, + argLen: 2, + asm: arm64.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "BFI", + auxType: auxARM64BitField, + argLen: 2, + resultInArg0: true, + earlyOk: true, + asm: arm64.ABFI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "BFXIL", + auxType: auxARM64BitField, + argLen: 2, + resultInArg0: true, + earlyOk: true, + asm: arm64.ABFXIL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SBFIZ", + auxType: auxARM64BitField, + argLen: 1, + earlyOk: true, + asm: arm64.ASBFIZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SBFX", + auxType: auxARM64BitField, + argLen: 1, + earlyOk: true, + asm: arm64.ASBFX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "UBFIZ", + auxType: auxARM64BitField, + argLen: 1, + earlyOk: true, + asm: arm64.AUBFIZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "UBFX", + auxType: auxARM64BitField, + argLen: 1, + earlyOk: true, + asm: arm64.AUBFX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: arm64.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FMOVSconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: arm64.AFMOVS, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: arm64.AFMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + earlyOk: true, + symEffect: SymAddr, + asm: arm64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037928517632, v2: 0}}, // SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVWUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FMOVSload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVQload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AFMOVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LDP", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.ALDP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "LDPW", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.ALDPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "LDPSW", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.ALDPSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "FLDPD", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AFLDPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FLDPS", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AFLDPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FLDPQ", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: arm64.AFLDPQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVWloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVWUloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVHloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVHUloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVBloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVBUloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FMOVSloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVHloadidx2", + argLen: 3, + addrSinkArg0: true, + asm: arm64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVHUloadidx2", + argLen: 3, + addrSinkArg0: true, + asm: arm64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVWloadidx4", + argLen: 3, + addrSinkArg0: true, + asm: arm64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVWUloadidx4", + argLen: 3, + addrSinkArg0: true, + asm: arm64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVDloadidx8", + argLen: 3, + addrSinkArg0: true, + asm: arm64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FMOVSloadidx4", + argLen: 3, + addrSinkArg0: true, + asm: arm64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDloadidx8", + argLen: 3, + addrSinkArg0: true, + asm: arm64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "FMOVSstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVQstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.AFMOVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "STP", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.ASTP, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "STPW", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.ASTPW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "FSTPD", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.AFSTPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSTPS", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.AFSTPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSTPQ", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: arm64.AFSTPQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "MOVHstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "MOVWstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "MOVDstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "FMOVSstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: arm64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVHstoreidx2", + argLen: 4, + addrSinkArg0: true, + asm: arm64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "MOVWstoreidx4", + argLen: 4, + addrSinkArg0: true, + asm: arm64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "MOVDstoreidx8", + argLen: 4, + addrSinkArg0: true, + asm: arm64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "FMOVSstoreidx4", + argLen: 4, + addrSinkArg0: true, + asm: arm64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDstoreidx8", + argLen: 4, + addrSinkArg0: true, + asm: arm64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDgpfp", + argLen: 1, + earlyOk: true, + asm: arm64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDfpgp", + argLen: 1, + earlyOk: true, + asm: arm64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FMOVSgpfp", + argLen: 1, + earlyOk: true, + asm: arm64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVSfpgp", + argLen: 1, + earlyOk: true, + asm: arm64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + earlyOk: true, + asm: arm64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVBUreg", + argLen: 1, + earlyOk: true, + asm: arm64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + earlyOk: true, + asm: arm64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVHUreg", + argLen: 1, + earlyOk: true, + asm: arm64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + earlyOk: true, + asm: arm64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVWUreg", + argLen: 1, + earlyOk: true, + asm: arm64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVDreg", + argLen: 1, + earlyOk: true, + asm: arm64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "MOVDnop", + argLen: 1, + resultInArg0: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "SCVTFWS", + argLen: 1, + earlyOk: true, + asm: arm64.ASCVTFWS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SCVTFWD", + argLen: 1, + earlyOk: true, + asm: arm64.ASCVTFWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "UCVTFWS", + argLen: 1, + earlyOk: true, + asm: arm64.AUCVTFWS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "UCVTFWD", + argLen: 1, + earlyOk: true, + asm: arm64.AUCVTFWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SCVTFS", + argLen: 1, + earlyOk: true, + asm: arm64.ASCVTFS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SCVTFD", + argLen: 1, + earlyOk: true, + asm: arm64.ASCVTFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "UCVTFS", + argLen: 1, + earlyOk: true, + asm: arm64.AUCVTFS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "UCVTFD", + argLen: 1, + earlyOk: true, + asm: arm64.AUCVTFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTZSSW", + argLen: 1, + earlyOk: true, + asm: arm64.AFCVTZSSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FCVTZSDW", + argLen: 1, + earlyOk: true, + asm: arm64.AFCVTZSDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FCVTZUSW", + argLen: 1, + earlyOk: true, + asm: arm64.AFCVTZUSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FCVTZUDW", + argLen: 1, + earlyOk: true, + asm: arm64.AFCVTZUDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FCVTZSS", + argLen: 1, + earlyOk: true, + asm: arm64.AFCVTZSS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FCVTZSD", + argLen: 1, + earlyOk: true, + asm: arm64.AFCVTZSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FCVTZUS", + argLen: 1, + earlyOk: true, + asm: arm64.AFCVTZUS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FCVTZUD", + argLen: 1, + earlyOk: true, + asm: arm64.AFCVTZUD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FCVTSD", + argLen: 1, + earlyOk: true, + asm: arm64.AFCVTSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTDS", + argLen: 1, + earlyOk: true, + asm: arm64.AFCVTDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTAD", + argLen: 1, + earlyOk: true, + asm: arm64.AFRINTAD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTMD", + argLen: 1, + earlyOk: true, + asm: arm64.AFRINTMD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTND", + argLen: 1, + earlyOk: true, + asm: arm64.AFRINTND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTPD", + argLen: 1, + earlyOk: true, + asm: arm64.AFRINTPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTZD", + argLen: 1, + earlyOk: true, + asm: arm64.AFRINTZD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTAS", + argLen: 1, + earlyOk: true, + asm: arm64.AFRINTAS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTMS", + argLen: 1, + earlyOk: true, + asm: arm64.AFRINTMS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTNS", + argLen: 1, + earlyOk: true, + asm: arm64.AFRINTNS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTPS", + argLen: 1, + earlyOk: true, + asm: arm64.AFRINTPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTZS", + argLen: 1, + earlyOk: true, + asm: arm64.AFRINTZS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CSEL", + auxType: auxCCop, + argLen: 3, + earlyOk: true, + asm: arm64.ACSEL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "CSEL0", + auxType: auxCCop, + argLen: 2, + earlyOk: true, + asm: arm64.ACSEL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "CSINC", + auxType: auxCCop, + argLen: 3, + earlyOk: true, + asm: arm64.ACSINC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "CSINV", + auxType: auxCCop, + argLen: 3, + earlyOk: true, + asm: arm64.ACSINV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "CSNEG", + auxType: auxCCop, + argLen: 3, + earlyOk: true, + asm: arm64.ACSNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "CSETM", + auxType: auxCCop, + argLen: 1, + earlyOk: true, + asm: arm64.ACSETM, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "CCMP", + auxType: auxARM64ConditionalParams, + argLen: 3, + asm: arm64.ACCMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CCMN", + auxType: auxARM64ConditionalParams, + argLen: 3, + asm: arm64.ACCMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CCMPconst", + auxType: auxARM64ConditionalParams, + argLen: 2, + asm: arm64.ACCMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CCMNconst", + auxType: auxARM64ConditionalParams, + argLen: 2, + asm: arm64.ACCMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CCMPW", + auxType: auxARM64ConditionalParams, + argLen: 3, + asm: arm64.ACCMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CCMNW", + auxType: auxARM64ConditionalParams, + argLen: 3, + asm: arm64.ACCMNW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CCMPWconst", + auxType: auxARM64ConditionalParams, + argLen: 2, + asm: arm64.ACCMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CCMNWconst", + auxType: auxARM64ConditionalParams, + argLen: 2, + asm: arm64.ACCMNW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLtailinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 33554432, v2: 0}}, // R26 + {0, regMask{v1: 1409286143, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP + }, + clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + }, + }, + { + name: "LoweredMemEq", + argLen: 4, + clobberFlags: true, + call: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1, v2: 0}}, // R0 + {1, regMask{v1: 2, v2: 0}}, // R1 + {2, regMask{v1: 4, v2: 0}}, // R2 + }, + clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + outputs: []outputInfo{ + {0, regMask{v1: 1, v2: 0}}, // R0 + }, + }, + }, + { + name: "Equal", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NotEqual", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LessThan", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LessEqual", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "GreaterThan", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "GreaterEqual", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LessThanU", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LessEqualU", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "GreaterThanU", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "GreaterEqualU", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LessThanF", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LessEqualF", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "GreaterThanF", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "GreaterEqualF", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NotLessThanF", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NotLessEqualF", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NotGreaterThanF", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "NotGreaterEqualF", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LessThanNoov", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "GreaterEqualNoov", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredZeroLoop", + auxType: auxInt64, + argLen: 2, + needIntTemp: true, + faultOnNilArg0: true, + addrSinkArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + clobbersArg0: true, + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 318767103, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30 + {1, regMask{v1: 318767103, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30 + }, + clobbers: regMask{v1: 422212481843200, v2: 0}, // R25 F16 F17 + }, + }, + { + name: "LoweredMoveLoop", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 310378495, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R26 R30 + {1, regMask{v1: 310378495, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R26 R30 + }, + clobbers: regMask{v1: 422212490231808, v2: 0}, // R24 R25 F16 F17 + clobbersArg0: true, + clobbersArg1: true, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 33554432, v2: 0}}, // R26 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "FlagConstant", + auxType: auxFlagConstant, + argLen: 0, + reg: regInfo{}, + }, + { + name: "InvertFlags", + argLen: 1, + reg: regInfo{}, + }, + { + name: "LDAR", + argLen: 2, + faultOnNilArg0: true, + asm: arm64.ALDAR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LDARB", + argLen: 2, + faultOnNilArg0: true, + asm: arm64.ALDARB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LDARW", + argLen: 2, + faultOnNilArg0: true, + asm: arm64.ALDARW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "STLRB", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: arm64.ASTLRB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "STLR", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: arm64.ASTLR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "STLRW", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: arm64.ASTLRW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicExchange8", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicExchange64Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicExchange32Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicExchange8Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicAdd64Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicAdd32Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicCas64", + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicCas32", + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicCas64Variant", + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicCas32Variant", + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicAnd8", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicOr8", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicAnd64", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicOr64", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicAnd32", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicOr32", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AORR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicAnd8Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicOr8Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicAnd64Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicOr64Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicAnd32Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredAtomicOr32Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 939524095, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: regMask{v1: 9223372034975924224, v2: 0}, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + outputs: []outputInfo{ + {0, regMask{v1: 16777216, v2: 0}}, // R25 + }, + }, + }, + { + name: "LoweredPanicBoundsRR", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredPanicBoundsRC", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredPanicBoundsCR", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredPanicBoundsCC", + auxType: auxPanicBoundsCC, + argLen: 1, + call: true, + reg: regInfo{}, + }, + { + name: "PRFM", + auxType: auxInt64, + argLen: 2, + hasSideEffects: true, + asm: arm64.APRFM, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + }, + }, + { + name: "DMB", + auxType: auxInt64, + argLen: 1, + hasSideEffects: true, + asm: arm64.ADMB, + reg: regInfo{}, + }, + { + name: "ZERO", + argLen: 0, + zeroWidth: true, + fixedReg: true, + earlyOk: true, + reg: regInfo{}, + }, + { + name: "VMOVI16B", + auxType: auxUInt8, + argLen: 0, + asm: arm64.AVMOVI, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VABS2D", + argLen: 1, + asm: arm64.AVABS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VABS4S", + argLen: 1, + asm: arm64.AVABS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VABS8H", + argLen: 1, + asm: arm64.AVABS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VABS16B", + argLen: 1, + asm: arm64.AVABS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VADD2D", + argLen: 2, + commutative: true, + asm: arm64.AVADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VADD4S", + argLen: 2, + commutative: true, + asm: arm64.AVADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VADD8H", + argLen: 2, + commutative: true, + asm: arm64.AVADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VADD16B", + argLen: 2, + commutative: true, + asm: arm64.AVADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VADDP2D", + argLen: 2, + asm: arm64.AVADDP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VADDP4S", + argLen: 2, + asm: arm64.AVADDP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VADDP8H", + argLen: 2, + asm: arm64.AVADDP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VADDV4S", + argLen: 1, + asm: arm64.AVADDV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VADDV8H", + argLen: 1, + asm: arm64.AVADDV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VADDV16B", + argLen: 1, + asm: arm64.AVADDV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VAND16B", + argLen: 2, + commutative: true, + asm: arm64.AVAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VBIC16B", + argLen: 2, + asm: arm64.AVBIC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VBIF16B", + argLen: 3, + resultInArg0: true, + asm: arm64.AVBIF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VBIT16B", + argLen: 3, + resultInArg0: true, + asm: arm64.AVBIT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCLS4S", + argLen: 1, + asm: arm64.AVCLS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCLS8H", + argLen: 1, + asm: arm64.AVCLS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCLS16B", + argLen: 1, + asm: arm64.AVCLS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCLZ4S", + argLen: 1, + asm: arm64.AVCLZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCLZ8H", + argLen: 1, + asm: arm64.AVCLZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCLZ16B", + argLen: 1, + asm: arm64.AVCLZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMEQ2D", + argLen: 2, + commutative: true, + asm: arm64.AVCMEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMEQ4S", + argLen: 2, + commutative: true, + asm: arm64.AVCMEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMEQ8H", + argLen: 2, + commutative: true, + asm: arm64.AVCMEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMEQ16B", + argLen: 2, + commutative: true, + asm: arm64.AVCMEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMGE2D", + argLen: 2, + asm: arm64.AVCMGE, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMGE4S", + argLen: 2, + asm: arm64.AVCMGE, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMGE8H", + argLen: 2, + asm: arm64.AVCMGE, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMGE16B", + argLen: 2, + asm: arm64.AVCMGE, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMGT2D", + argLen: 2, + asm: arm64.AVCMGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMGT4S", + argLen: 2, + asm: arm64.AVCMGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMGT8H", + argLen: 2, + asm: arm64.AVCMGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMGT16B", + argLen: 2, + asm: arm64.AVCMGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMHI2D", + argLen: 2, + asm: arm64.AVCMHI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMHI4S", + argLen: 2, + asm: arm64.AVCMHI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMHI8H", + argLen: 2, + asm: arm64.AVCMHI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMHI16B", + argLen: 2, + asm: arm64.AVCMHI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMHS2D", + argLen: 2, + asm: arm64.AVCMHS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMHS4S", + argLen: 2, + asm: arm64.AVCMHS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMHS8H", + argLen: 2, + asm: arm64.AVCMHS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCMHS16B", + argLen: 2, + asm: arm64.AVCMHS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VCNT16B", + argLen: 1, + asm: arm64.AVCNT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VEOR16B", + argLen: 2, + commutative: true, + asm: arm64.AVEOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFABS2D", + argLen: 1, + asm: arm64.AVFABS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFABS4S", + argLen: 1, + asm: arm64.AVFABS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFADD2D", + argLen: 2, + commutative: true, + asm: arm64.AVFADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFADD4S", + argLen: 2, + commutative: true, + asm: arm64.AVFADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFADDP2D", + argLen: 2, + asm: arm64.AVFADDP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFADDP4S", + argLen: 2, + asm: arm64.AVFADDP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCMEQ2D", + argLen: 2, + commutative: true, + asm: arm64.AVFCMEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCMEQ4S", + argLen: 2, + commutative: true, + asm: arm64.AVFCMEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCMGE2D", + argLen: 2, + asm: arm64.AVFCMGE, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCMGE4S", + argLen: 2, + asm: arm64.AVFCMGE, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCMGT2D", + argLen: 2, + asm: arm64.AVFCMGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCMGT4S", + argLen: 2, + asm: arm64.AVFCMGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCVTL2_4S", + argLen: 1, + asm: arm64.AVFCVTL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCVTL4S", + argLen: 1, + asm: arm64.AVFCVTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCVTN2D", + argLen: 1, + asm: arm64.AVFCVTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCVTN2_2D", + argLen: 2, + resultInArg0: true, + asm: arm64.AVFCVTN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCVTZS2D", + argLen: 1, + asm: arm64.AVFCVTZS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCVTZS4S", + argLen: 1, + asm: arm64.AVFCVTZS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCVTZU2D", + argLen: 1, + asm: arm64.AVFCVTZU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFCVTZU4S", + argLen: 1, + asm: arm64.AVFCVTZU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFDIV2D", + argLen: 2, + asm: arm64.AVFDIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFDIV4S", + argLen: 2, + asm: arm64.AVFDIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFMAX2D", + argLen: 2, + commutative: true, + asm: arm64.AVFMAX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFMAX4S", + argLen: 2, + commutative: true, + asm: arm64.AVFMAX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFMAXV4S", + argLen: 1, + asm: arm64.AVFMAXV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFMIN2D", + argLen: 2, + commutative: true, + asm: arm64.AVFMIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFMIN4S", + argLen: 2, + commutative: true, + asm: arm64.AVFMIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFMINV4S", + argLen: 1, + asm: arm64.AVFMINV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFMLA2D", + argLen: 3, + resultInArg0: true, + asm: arm64.AVFMLA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFMLA4S", + argLen: 3, + resultInArg0: true, + asm: arm64.AVFMLA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFMUL2D", + argLen: 2, + commutative: true, + asm: arm64.AVFMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFMUL4S", + argLen: 2, + commutative: true, + asm: arm64.AVFMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFNEG2D", + argLen: 1, + asm: arm64.AVFNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFNEG4S", + argLen: 1, + asm: arm64.AVFNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFRINTM2D", + argLen: 1, + asm: arm64.AVFRINTM, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFRINTM4S", + argLen: 1, + asm: arm64.AVFRINTM, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFRINTN2D", + argLen: 1, + asm: arm64.AVFRINTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFRINTN4S", + argLen: 1, + asm: arm64.AVFRINTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFRINTP2D", + argLen: 1, + asm: arm64.AVFRINTP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFRINTP4S", + argLen: 1, + asm: arm64.AVFRINTP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFRINTZ2D", + argLen: 1, + asm: arm64.AVFRINTZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFRINTZ4S", + argLen: 1, + asm: arm64.AVFRINTZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFSQRT2D", + argLen: 1, + asm: arm64.AVFSQRT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFSQRT4S", + argLen: 1, + asm: arm64.AVFSQRT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFSUB2D", + argLen: 2, + asm: arm64.AVFSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VFSUB4S", + argLen: 2, + asm: arm64.AVFSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMLA4S", + argLen: 3, + resultInArg0: true, + asm: arm64.AVMLA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMLA8H", + argLen: 3, + resultInArg0: true, + asm: arm64.AVMLA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMLA16B", + argLen: 3, + resultInArg0: true, + asm: arm64.AVMLA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMUL4S", + argLen: 2, + commutative: true, + asm: arm64.AVMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMUL8H", + argLen: 2, + commutative: true, + asm: arm64.AVMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMUL16B", + argLen: 2, + commutative: true, + asm: arm64.AVMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VNEG2D", + argLen: 1, + asm: arm64.AVNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VNEG4S", + argLen: 1, + asm: arm64.AVNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VNEG8H", + argLen: 1, + asm: arm64.AVNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VNEG16B", + argLen: 1, + asm: arm64.AVNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VNOT16B", + argLen: 1, + asm: arm64.AVNOT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VORN16B", + argLen: 2, + asm: arm64.AVORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VORR16B", + argLen: 2, + commutative: true, + asm: arm64.AVORR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VPMULL2D", + argLen: 2, + commutative: true, + asm: arm64.AVPMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VPMULL2_2D", + argLen: 2, + commutative: true, + asm: arm64.AVPMULL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSCVTF2D", + argLen: 1, + asm: arm64.AVSCVTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSCVTF4S", + argLen: 1, + asm: arm64.AVSCVTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMAX4S", + argLen: 2, + commutative: true, + asm: arm64.AVSMAX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMAX8H", + argLen: 2, + commutative: true, + asm: arm64.AVSMAX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMAX16B", + argLen: 2, + commutative: true, + asm: arm64.AVSMAX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMAXV4S", + argLen: 1, + asm: arm64.AVSMAXV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMAXV8H", + argLen: 1, + asm: arm64.AVSMAXV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMAXV16B", + argLen: 1, + asm: arm64.AVSMAXV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMIN4S", + argLen: 2, + commutative: true, + asm: arm64.AVSMIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMIN8H", + argLen: 2, + commutative: true, + asm: arm64.AVSMIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMIN16B", + argLen: 2, + commutative: true, + asm: arm64.AVSMIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMINV4S", + argLen: 1, + asm: arm64.AVSMINV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMINV8H", + argLen: 1, + asm: arm64.AVSMINV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMINV16B", + argLen: 1, + asm: arm64.AVSMINV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMULL2_4S", + argLen: 2, + commutative: true, + asm: arm64.AVSMULL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMULL2_8H", + argLen: 2, + commutative: true, + asm: arm64.AVSMULL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMULL2_16B", + argLen: 2, + commutative: true, + asm: arm64.AVSMULL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMULL4S", + argLen: 2, + commutative: true, + asm: arm64.AVSMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMULL8H", + argLen: 2, + commutative: true, + asm: arm64.AVSMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSMULL16B", + argLen: 2, + commutative: true, + asm: arm64.AVSMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQADD2D", + argLen: 2, + commutative: true, + asm: arm64.AVSQADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQADD4S", + argLen: 2, + commutative: true, + asm: arm64.AVSQADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQADD8H", + argLen: 2, + commutative: true, + asm: arm64.AVSQADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQADD16B", + argLen: 2, + commutative: true, + asm: arm64.AVSQADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSHL2D", + argLen: 2, + asm: arm64.AVSQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSHL4S", + argLen: 2, + asm: arm64.AVSQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSHL8H", + argLen: 2, + asm: arm64.AVSQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSHL16B", + argLen: 2, + asm: arm64.AVSQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSUB2D", + argLen: 2, + asm: arm64.AVSQSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSUB4S", + argLen: 2, + asm: arm64.AVSQSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSUB8H", + argLen: 2, + asm: arm64.AVSQSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSUB16B", + argLen: 2, + asm: arm64.AVSQSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTN2D", + argLen: 1, + asm: arm64.AVSQXTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTN2_2D", + argLen: 2, + resultInArg0: true, + asm: arm64.AVSQXTN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTN2_4S", + argLen: 2, + resultInArg0: true, + asm: arm64.AVSQXTN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTN2_8H", + argLen: 2, + resultInArg0: true, + asm: arm64.AVSQXTN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTN4S", + argLen: 1, + asm: arm64.AVSQXTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTN8H", + argLen: 1, + asm: arm64.AVSQXTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTUN2D", + argLen: 1, + asm: arm64.AVSQXTUN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTUN2_2D", + argLen: 2, + resultInArg0: true, + asm: arm64.AVSQXTUN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTUN2_4S", + argLen: 2, + resultInArg0: true, + asm: arm64.AVSQXTUN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTUN2_8H", + argLen: 2, + resultInArg0: true, + asm: arm64.AVSQXTUN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTUN4S", + argLen: 1, + asm: arm64.AVSQXTUN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQXTUN8H", + argLen: 1, + asm: arm64.AVSQXTUN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSRHADD4S", + argLen: 2, + commutative: true, + asm: arm64.AVSRHADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSRHADD8H", + argLen: 2, + commutative: true, + asm: arm64.AVSRHADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSRHADD16B", + argLen: 2, + commutative: true, + asm: arm64.AVSRHADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHL2D", + argLen: 2, + asm: arm64.AVSSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHL4S", + argLen: 2, + asm: arm64.AVSSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHL8H", + argLen: 2, + asm: arm64.AVSSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHL16B", + argLen: 2, + asm: arm64.AVSSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSUB2D", + argLen: 2, + asm: arm64.AVSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSUB4S", + argLen: 2, + asm: arm64.AVSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSUB8H", + argLen: 2, + asm: arm64.AVSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSUB16B", + argLen: 2, + asm: arm64.AVSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSXTL2_4S", + argLen: 1, + asm: arm64.AVSXTL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSXTL2_8H", + argLen: 1, + asm: arm64.AVSXTL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSXTL2_16B", + argLen: 1, + asm: arm64.AVSXTL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSXTL4S", + argLen: 1, + asm: arm64.AVSXTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSXTL8H", + argLen: 1, + asm: arm64.AVSXTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSXTL16B", + argLen: 1, + asm: arm64.AVSXTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VTBL16B", + argLen: 2, + asm: arm64.AVTBL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VTBX16B", + argLen: 3, + resultInArg0: true, + asm: arm64.AVTBX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VTRN12D", + argLen: 2, + asm: arm64.AVTRN1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VTRN14S", + argLen: 2, + asm: arm64.AVTRN1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VTRN18H", + argLen: 2, + asm: arm64.AVTRN1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VTRN22D", + argLen: 2, + asm: arm64.AVTRN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VTRN24S", + argLen: 2, + asm: arm64.AVTRN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VTRN28H", + argLen: 2, + asm: arm64.AVTRN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VTRN116B", + argLen: 2, + asm: arm64.AVTRN1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VTRN216B", + argLen: 2, + asm: arm64.AVTRN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUCVTF2D", + argLen: 1, + asm: arm64.AVUCVTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUCVTF4S", + argLen: 1, + asm: arm64.AVUCVTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMAX4S", + argLen: 2, + commutative: true, + asm: arm64.AVUMAX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMAX8H", + argLen: 2, + commutative: true, + asm: arm64.AVUMAX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMAX16B", + argLen: 2, + commutative: true, + asm: arm64.AVUMAX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMAXV4S", + argLen: 1, + asm: arm64.AVUMAXV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMAXV8H", + argLen: 1, + asm: arm64.AVUMAXV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMAXV16B", + argLen: 1, + asm: arm64.AVUMAXV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMIN4S", + argLen: 2, + commutative: true, + asm: arm64.AVUMIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMIN8H", + argLen: 2, + commutative: true, + asm: arm64.AVUMIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMIN16B", + argLen: 2, + commutative: true, + asm: arm64.AVUMIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMINV4S", + argLen: 1, + asm: arm64.AVUMINV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMINV8H", + argLen: 1, + asm: arm64.AVUMINV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMINV16B", + argLen: 1, + asm: arm64.AVUMINV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMULL2_4S", + argLen: 2, + commutative: true, + asm: arm64.AVUMULL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMULL2_8H", + argLen: 2, + commutative: true, + asm: arm64.AVUMULL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMULL2_16B", + argLen: 2, + commutative: true, + asm: arm64.AVUMULL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMULL4S", + argLen: 2, + commutative: true, + asm: arm64.AVUMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMULL8H", + argLen: 2, + commutative: true, + asm: arm64.AVUMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUMULL16B", + argLen: 2, + commutative: true, + asm: arm64.AVUMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQADD2D", + argLen: 2, + commutative: true, + asm: arm64.AVUQADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQADD4S", + argLen: 2, + commutative: true, + asm: arm64.AVUQADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQADD8H", + argLen: 2, + commutative: true, + asm: arm64.AVUQADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQADD16B", + argLen: 2, + commutative: true, + asm: arm64.AVUQADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSHL2D", + argLen: 2, + asm: arm64.AVUQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSHL4S", + argLen: 2, + asm: arm64.AVUQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSHL8H", + argLen: 2, + asm: arm64.AVUQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSHL16B", + argLen: 2, + asm: arm64.AVUQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSUB2D", + argLen: 2, + asm: arm64.AVUQSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSUB4S", + argLen: 2, + asm: arm64.AVUQSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSUB8H", + argLen: 2, + asm: arm64.AVUQSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSUB16B", + argLen: 2, + asm: arm64.AVUQSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQXTN2D", + argLen: 1, + asm: arm64.AVUQXTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQXTN2_2D", + argLen: 2, + resultInArg0: true, + asm: arm64.AVUQXTN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQXTN2_4S", + argLen: 2, + resultInArg0: true, + asm: arm64.AVUQXTN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQXTN2_8H", + argLen: 2, + resultInArg0: true, + asm: arm64.AVUQXTN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQXTN4S", + argLen: 1, + asm: arm64.AVUQXTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQXTN8H", + argLen: 1, + asm: arm64.AVUQXTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VURHADD4S", + argLen: 2, + commutative: true, + asm: arm64.AVURHADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VURHADD8H", + argLen: 2, + commutative: true, + asm: arm64.AVURHADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VURHADD16B", + argLen: 2, + commutative: true, + asm: arm64.AVURHADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHL2D", + argLen: 2, + asm: arm64.AVUSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHL4S", + argLen: 2, + asm: arm64.AVUSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHL8H", + argLen: 2, + asm: arm64.AVUSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHL16B", + argLen: 2, + asm: arm64.AVUSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUXTL2_4S", + argLen: 1, + asm: arm64.AVUXTL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUXTL2_8H", + argLen: 1, + asm: arm64.AVUXTL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUXTL2_16B", + argLen: 1, + asm: arm64.AVUXTL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUXTL4S", + argLen: 1, + asm: arm64.AVUXTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUXTL8H", + argLen: 1, + asm: arm64.AVUXTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUXTL16B", + argLen: 1, + asm: arm64.AVUXTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUZP12D", + argLen: 2, + asm: arm64.AVUZP1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUZP14S", + argLen: 2, + asm: arm64.AVUZP1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUZP18H", + argLen: 2, + asm: arm64.AVUZP1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUZP22D", + argLen: 2, + asm: arm64.AVUZP2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUZP24S", + argLen: 2, + asm: arm64.AVUZP2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUZP28H", + argLen: 2, + asm: arm64.AVUZP2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUZP116B", + argLen: 2, + asm: arm64.AVUZP1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUZP216B", + argLen: 2, + asm: arm64.AVUZP2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VXTN2D", + argLen: 1, + asm: arm64.AVXTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VXTN2_2D", + argLen: 2, + resultInArg0: true, + asm: arm64.AVXTN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VXTN2_4S", + argLen: 2, + resultInArg0: true, + asm: arm64.AVXTN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VXTN2_8H", + argLen: 2, + resultInArg0: true, + asm: arm64.AVXTN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VXTN4S", + argLen: 1, + asm: arm64.AVXTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VXTN8H", + argLen: 1, + asm: arm64.AVXTN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VZIP12D", + argLen: 2, + asm: arm64.AVZIP1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VZIP14S", + argLen: 2, + asm: arm64.AVZIP1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VZIP18H", + argLen: 2, + asm: arm64.AVZIP1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VZIP22D", + argLen: 2, + asm: arm64.AVZIP2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VZIP24S", + argLen: 2, + asm: arm64.AVZIP2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VZIP28H", + argLen: 2, + asm: arm64.AVZIP2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VZIP116B", + argLen: 2, + asm: arm64.AVZIP1, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VZIP216B", + argLen: 2, + asm: arm64.AVZIP2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VDUPBbcast", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVDUP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VDUPDbcast", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVDUP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VDUPDextr", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVDUP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VDUPHbcast", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVDUP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VDUPSbcast", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVDUP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VDUPSextr", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVDUP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VEXT16B", + auxType: auxUInt8, + argLen: 2, + asm: arm64.AVEXT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMOVBextr", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "VMOVBins", + auxType: auxUInt8, + argLen: 2, + resultInArg0: true, + asm: arm64.AVMOV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMOVDextr", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "VMOVDins", + auxType: auxUInt8, + argLen: 2, + resultInArg0: true, + asm: arm64.AVMOV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMOVDins0", + auxType: auxUInt8, + argLen: 2, + resultInArg0: true, + asm: arm64.AVMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMOVHextr", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "VMOVHins", + auxType: auxUInt8, + argLen: 2, + resultInArg0: true, + asm: arm64.AVMOV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMOVSextr", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, + { + name: "VMOVSins", + auxType: auxUInt8, + argLen: 2, + resultInArg0: true, + asm: arm64.AVMOV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VMOVSins0", + auxType: auxUInt8, + argLen: 2, + resultInArg0: true, + asm: arm64.AVMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSHL2D", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSHL4S", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSHL8H", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSHL16B", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSHRN2D", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSHRN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSHRN2_2D", + auxType: auxUInt8, + argLen: 2, + resultInArg0: true, + asm: arm64.AVSHRN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSHRN2_4S", + auxType: auxUInt8, + argLen: 2, + resultInArg0: true, + asm: arm64.AVSHRN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSHRN2_8H", + auxType: auxUInt8, + argLen: 2, + resultInArg0: true, + asm: arm64.AVSHRN2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSHRN4S", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSHRN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSHRN8H", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSHRN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSHL2Dconst", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSHL4Sconst", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSHL8Hconst", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSQSHL16Bconst", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHLL2_4S", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSSHLL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHLL2_8H", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSSHLL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHLL2_16B", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSSHLL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHLL4S", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSSHLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHLL8H", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSSHLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHLL16B", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSSHLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHR2D", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSSHR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHR4S", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSSHR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHR8H", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSSHR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VSSHR16B", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVSSHR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSHL2Dconst", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSHL4Sconst", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSHL8Hconst", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUQSHL16Bconst", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUQSHL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHLL2_4S", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUSHLL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHLL2_8H", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUSHLL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHLL2_16B", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUSHLL2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHLL4S", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUSHLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHLL8H", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUSHLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHLL16B", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUSHLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHR2D", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUSHR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHR4S", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUSHR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHR8H", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUSHR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VUSHR16B", + auxType: auxUInt8, + argLen: 1, + asm: arm64.AVUSHR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + + { + name: "NEGV", + argLen: 1, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NEGF", + argLen: 1, + earlyOk: true, + asm: loong64.ANEGF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "NEGD", + argLen: 1, + earlyOk: true, + asm: loong64.ANEGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SQRTD", + argLen: 1, + earlyOk: true, + asm: loong64.ASQRTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SQRTF", + argLen: 1, + earlyOk: true, + asm: loong64.ASQRTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ABSF", + argLen: 1, + earlyOk: true, + asm: loong64.AABSF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ABSD", + argLen: 1, + earlyOk: true, + asm: loong64.AABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CLZW", + argLen: 1, + earlyOk: true, + asm: loong64.ACLZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "CLZV", + argLen: 1, + earlyOk: true, + asm: loong64.ACLZV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "CTZW", + argLen: 1, + earlyOk: true, + asm: loong64.ACTZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "CTZV", + argLen: 1, + earlyOk: true, + asm: loong64.ACTZV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "REVB2H", + argLen: 1, + earlyOk: true, + asm: loong64.AREVB2H, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "REVB2W", + argLen: 1, + earlyOk: true, + asm: loong64.AREVB2W, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "REVB4H", + argLen: 1, + earlyOk: true, + asm: loong64.AREVB4H, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "REVBV", + argLen: 1, + earlyOk: true, + asm: loong64.AREVBV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "BITREV4B", + argLen: 1, + earlyOk: true, + asm: loong64.ABITREV4B, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "BITREVW", + argLen: 1, + earlyOk: true, + asm: loong64.ABITREVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "BITREVV", + argLen: 1, + earlyOk: true, + asm: loong64.ABITREVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "VPCNT64", + argLen: 1, + asm: loong64.AVPCNTV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VPCNT32", + argLen: 1, + asm: loong64.AVPCNTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "VPCNT16", + argLen: 1, + asm: loong64.AVPCNTH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ADDV", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ADDVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741820, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ADDV16const", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.AADDV16, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741820, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SUBV", + argLen: 2, + earlyOk: true, + asm: loong64.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SUBVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MULV", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AMULV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MULHV", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AMULHV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MULHVU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AMULHVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MULH", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AMULH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MULHU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AMULHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "DIVV", + argLen: 2, + asm: loong64.ADIVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "DIVVU", + argLen: 2, + asm: loong64.ADIVVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "REMV", + argLen: 2, + asm: loong64.AREMV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "REMVU", + argLen: 2, + asm: loong64.AREMVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MULWVW", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AMULWVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MULWVWU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AMULWVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ADDF", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AADDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ADDD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SUBF", + argLen: 2, + earlyOk: true, + asm: loong64.ASUBF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SUBD", + argLen: 2, + earlyOk: true, + asm: loong64.ASUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MULF", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AMULF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MULD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "DIVF", + argLen: 2, + asm: loong64.ADIVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + asm: loong64.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: loong64.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NORconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ANDN", + argLen: 2, + earlyOk: true, + asm: loong64.AANDN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ORN", + argLen: 2, + earlyOk: true, + asm: loong64.AORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "FMADDF", + argLen: 3, + commutative: true, + earlyOk: true, + asm: loong64.AFMADDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMADDD", + argLen: 3, + commutative: true, + earlyOk: true, + asm: loong64.AFMADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMSUBF", + argLen: 3, + commutative: true, + earlyOk: true, + asm: loong64.AFMSUBF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMSUBD", + argLen: 3, + commutative: true, + earlyOk: true, + asm: loong64.AFMSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMADDF", + argLen: 3, + commutative: true, + earlyOk: true, + asm: loong64.AFNMADDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMADDD", + argLen: 3, + commutative: true, + earlyOk: true, + asm: loong64.AFNMADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMSUBF", + argLen: 3, + commutative: true, + earlyOk: true, + asm: loong64.AFNMSUBF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMSUBD", + argLen: 3, + commutative: true, + earlyOk: true, + asm: loong64.AFNMSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMINF", + argLen: 2, + commutative: true, + resultNotInArgs: true, + earlyOk: true, + asm: loong64.AFMINF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMIND", + argLen: 2, + commutative: true, + resultNotInArgs: true, + earlyOk: true, + asm: loong64.AFMIND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMAXF", + argLen: 2, + commutative: true, + resultNotInArgs: true, + earlyOk: true, + asm: loong64.AFMAXF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMAXD", + argLen: 2, + commutative: true, + resultNotInArgs: true, + earlyOk: true, + asm: loong64.AFMAXD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MASKEQZ", + argLen: 2, + earlyOk: true, + asm: loong64.AMASKEQZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MASKNEZ", + argLen: 2, + earlyOk: true, + asm: loong64.AMASKNEZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "FCOPYSGD", + argLen: 2, + earlyOk: true, + asm: loong64.AFCOPYSGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SLL", + argLen: 2, + earlyOk: true, + asm: loong64.ASLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SLLV", + argLen: 2, + earlyOk: true, + asm: loong64.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SLLconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ASLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SLLVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRL", + argLen: 2, + earlyOk: true, + asm: loong64.ASRL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRLV", + argLen: 2, + earlyOk: true, + asm: loong64.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRLconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ASRL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRLVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRA", + argLen: 2, + earlyOk: true, + asm: loong64.ASRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRAV", + argLen: 2, + earlyOk: true, + asm: loong64.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRAconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ASRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRAVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ROTR", + argLen: 2, + earlyOk: true, + asm: loong64.AROTR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ROTRV", + argLen: 2, + earlyOk: true, + asm: loong64.AROTRV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ROTRconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.AROTR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ROTRVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.AROTRV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGT", + argLen: 2, + earlyOk: true, + asm: loong64.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGTconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGTU", + argLen: 2, + earlyOk: true, + asm: loong64.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGTUconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "CMPEQF", + argLen: 2, + asm: loong64.ACMPEQF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPEQD", + argLen: 2, + asm: loong64.ACMPEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGEF", + argLen: 2, + asm: loong64.ACMPGEF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGED", + argLen: 2, + asm: loong64.ACMPGED, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGTF", + argLen: 2, + asm: loong64.ACMPGTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGTD", + argLen: 2, + asm: loong64.ACMPGTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "BSTRPICKW", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ABSTRPICKW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "BSTRPICKV", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: loong64.ABSTRPICKV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: loong64.AMOVV, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVFconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: loong64.AMOVF, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: loong64.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + earlyOk: true, + symEffect: SymAddr, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018427387908, v2: 0}}, // SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: loong64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: loong64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: loong64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVFload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: loong64.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: loong64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVloadidx", + argLen: 3, + addrSinkArg0: true, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWloadidx", + argLen: 3, + addrSinkArg0: true, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWUloadidx", + argLen: 3, + addrSinkArg0: true, + asm: loong64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHloadidx", + argLen: 3, + addrSinkArg0: true, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHUloadidx", + argLen: 3, + addrSinkArg0: true, + asm: loong64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBloadidx", + argLen: 3, + addrSinkArg0: true, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBUloadidx", + argLen: 3, + addrSinkArg0: true, + asm: loong64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVFloadidx", + argLen: 3, + addrSinkArg0: true, + asm: loong64.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDloadidx", + argLen: 3, + addrSinkArg0: true, + asm: loong64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVVstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVFstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstoreidx", + argLen: 4, + addrSinkArg0: true, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVHstoreidx", + argLen: 4, + addrSinkArg0: true, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVWstoreidx", + argLen: 4, + addrSinkArg0: true, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVVstoreidx", + argLen: 4, + addrSinkArg0: true, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVFstoreidx", + argLen: 4, + addrSinkArg0: true, + asm: loong64.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDstoreidx", + argLen: 4, + addrSinkArg0: true, + asm: loong64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVWfpgp", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWgpfp", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVfpgp", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVgpfp", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBUreg", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHUreg", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWUreg", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVreg", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVnop", + argLen: 1, + resultInArg0: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWF", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVWF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVWD", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVF", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVD", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCFW", + argLen: 1, + earlyOk: true, + asm: loong64.ATRUNCFW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCDW", + argLen: 1, + earlyOk: true, + asm: loong64.ATRUNCDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCFV", + argLen: 1, + earlyOk: true, + asm: loong64.ATRUNCFV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCDV", + argLen: 1, + earlyOk: true, + asm: loong64.ATRUNCDV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVFD", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDF", + argLen: 1, + earlyOk: true, + asm: loong64.AMOVDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTND", + argLen: 1, + asm: loong64.AVFRINTRNED, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTMD", + argLen: 1, + asm: loong64.AVFRINTRMD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTPD", + argLen: 1, + asm: loong64.AVFRINTRPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FRINTZD", + argLen: 1, + asm: loong64.AVFRINTRZD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LoweredRound32F", + argLen: 1, + resultInArg0: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LoweredRound64F", + argLen: 1, + resultInArg0: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: regMask{v1: 4611686018427387896, v2: 0}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: regMask{v1: 4611686018427387896, v2: 0}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLtailinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: regMask{v1: 4611686018427387896, v2: 0}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 268435456, v2: 0}}, // R29 + {0, regMask{v1: 1071644668, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: regMask{v1: 4611686018427387896, v2: 0}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: regMask{v1: 4611686018427387896, v2: 0}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredZeroLoop", + auxType: auxInt64, + argLen: 2, + needIntTemp: true, + faultOnNilArg0: true, + addrSinkArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: regMask{v1: 2305843009213693952, v2: 0}, // F31 + clobbersArg0: true, + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1067450360, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1067450360, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: regMask{v1: 4194304, v2: 0}, // R23 + }, + }, + { + name: "LoweredMoveLoop", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1059061752, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1059061752, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R25 R26 R27 R28 R29 R31 + }, + clobbers: regMask{v1: 12582912, v2: 0}, // R23 R24 + clobbersArg0: true, + clobbersArg1: true, + }, + }, + { + name: "LoweredAtomicLoad8", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad64", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicStore8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore64", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore8Variant", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore32Variant", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore64Variant", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicExchange8Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicCas32", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicCas64", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicCas64Variant", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicCas32Variant", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAnd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMANDDBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicOr32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMORDBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicAnd32value", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMANDDBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAnd64value", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMANDDBV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicOr32value", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMORDBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicOr64value", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMORDBV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "FPFlagTrue", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "FPFlagFalse", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 268435456, v2: 0}}, // R29 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: regMask{v1: 4611686017353646082, v2: 0}, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + outputs: []outputInfo{ + {0, regMask{v1: 268435456, v2: 0}}, // R29 + }, + }, + }, + { + name: "LoweredPubBarrier", + argLen: 1, + hasSideEffects: true, + asm: loong64.ADBAR, + reg: regInfo{}, + }, + { + name: "LoweredPanicBoundsRR", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 524280, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 + {1, regMask{v1: 524280, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 + }, + }, + }, + { + name: "LoweredPanicBoundsRC", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 524280, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 + }, + }, + }, + { + name: "LoweredPanicBoundsCR", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 524280, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 + }, + }, + }, + { + name: "LoweredPanicBoundsCC", + auxType: auxPanicBoundsCC, + argLen: 1, + call: true, + reg: regInfo{}, + }, + { + name: "PRELD", + auxType: auxInt64, + argLen: 2, + hasSideEffects: true, + asm: loong64.APRELD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741820, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "PRELDX", + auxType: auxInt64, + argLen: 2, + hasSideEffects: true, + asm: loong64.APRELDX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741820, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ADDshiftLLV", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: loong64.AALSLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ZERO", + argLen: 0, + zeroWidth: true, + fixedReg: true, + earlyOk: true, + reg: regInfo{}, + }, + + { + name: "ADD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AADDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "ADDconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: mips.AADDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 536870910, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SUB", + argLen: 2, + earlyOk: true, + asm: mips.ASUBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SUBconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: mips.ASUBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MUL", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + clobbers: regMask{v1: 105553116266496, v2: 0}, // HI LO + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MULT", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + clobbers: regMask{v1: 105553116266496, v2: 0}, // HI LO + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MULTU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AMULU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + clobbers: regMask{v1: 105553116266496, v2: 0}, // HI LO + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "DIV", + argLen: 2, + asm: mips.ADIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + clobbers: regMask{v1: 105553116266496, v2: 0}, // HI LO + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "DIVU", + argLen: 2, + asm: mips.ADIVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + clobbers: regMask{v1: 105553116266496, v2: 0}, // HI LO + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "ADDF", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AADDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "ADDD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "SUBF", + argLen: 2, + earlyOk: true, + asm: mips.ASUBF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "SUBD", + argLen: 2, + earlyOk: true, + asm: mips.ASUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MULF", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AMULF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MULD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "DIVF", + argLen: 2, + earlyOk: true, + asm: mips.ADIVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + earlyOk: true, + asm: mips.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: mips.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: mips.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: mips.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "NOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "NEG", + argLen: 1, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "NEGF", + argLen: 1, + earlyOk: true, + asm: mips.ANEGF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "NEGD", + argLen: 1, + earlyOk: true, + asm: mips.ANEGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "ABSD", + argLen: 1, + earlyOk: true, + asm: mips.AABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "SQRTD", + argLen: 1, + earlyOk: true, + asm: mips.ASQRTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "SQRTF", + argLen: 1, + earlyOk: true, + asm: mips.ASQRTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "SLL", + argLen: 2, + earlyOk: true, + asm: mips.ASLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SLLconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: mips.ASLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SRL", + argLen: 2, + earlyOk: true, + asm: mips.ASRL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SRLconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: mips.ASRL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SRA", + argLen: 2, + earlyOk: true, + asm: mips.ASRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SRAconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: mips.ASRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "CLZ", + argLen: 1, + earlyOk: true, + asm: mips.ACLZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SGT", + argLen: 2, + earlyOk: true, + asm: mips.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SGTconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: mips.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SGTzero", + argLen: 1, + earlyOk: true, + asm: mips.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SGTU", + argLen: 2, + earlyOk: true, + asm: mips.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SGTUconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: mips.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "SGTUzero", + argLen: 1, + earlyOk: true, + asm: mips.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "CMPEQF", + argLen: 2, + asm: mips.ACMPEQF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "CMPEQD", + argLen: 2, + asm: mips.ACMPEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "CMPGEF", + argLen: 2, + asm: mips.ACMPGEF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "CMPGED", + argLen: 2, + asm: mips.ACMPGED, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "CMPGTF", + argLen: 2, + asm: mips.ACMPGTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "CMPGTD", + argLen: 2, + asm: mips.ACMPGTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVWconst", + auxType: auxInt32, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: mips.AMOVW, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVFconst", + auxType: auxFloat32, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: mips.AMOVF, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: mips.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVWaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + earlyOk: true, + symEffect: SymAddr, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140737555464192, v2: 0}}, // SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVFload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVFstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVBstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVHstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVWstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVWfpgp", + argLen: 1, + earlyOk: true, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVWgpfp", + argLen: 1, + earlyOk: true, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVBUreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVHUreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVWnop", + argLen: 1, + resultInArg0: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "CMOVZ", + argLen: 3, + resultInArg0: true, + earlyOk: true, + asm: mips.ACMOVZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {2, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "CMOVZzero", + argLen: 2, + resultInArg0: true, + earlyOk: true, + asm: mips.ACMOVZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVWF", + argLen: 1, + earlyOk: true, + asm: mips.AMOVWF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVWD", + argLen: 1, + earlyOk: true, + asm: mips.AMOVWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "TRUNCFW", + argLen: 1, + earlyOk: true, + asm: mips.ATRUNCFW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "TRUNCDW", + argLen: 1, + earlyOk: true, + asm: mips.ATRUNCDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVFD", + argLen: 1, + earlyOk: true, + asm: mips.AMOVFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVDF", + argLen: 1, + earlyOk: true, + asm: mips.AMOVDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: regMask{v1: 140737421246462, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: regMask{v1: 140737421246462, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + }, + }, + { + name: "CALLtailinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + clobbers: regMask{v1: 140737421246462, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: 3, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 4194304, v2: 0}}, // R22 + {0, regMask{v1: 402653182, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 + }, + clobbers: regMask{v1: 140737421246462, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + clobbers: regMask{v1: 140737421246462, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + }, + }, + { + name: "LoweredAtomicLoad8", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicStore8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStorezero", + argLen: 2, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicExchange", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicAddconst", + auxType: auxInt32, + argLen: 2, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicCas", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicAnd", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: mips.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicOr", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: mips.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "LoweredZero", + auxType: auxInt32, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2, v2: 0}}, // R1 + {1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + clobbers: regMask{v1: 2, v2: 0}, // R1 + }, + }, + { + name: "LoweredMove", + auxType: auxInt32, + argLen: 4, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4, v2: 0}}, // R2 + {1, regMask{v1: 2, v2: 0}}, // R1 + {2, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + clobbers: regMask{v1: 6, v2: 0}, // R1 R2 + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + }, + }, + { + name: "FPFlagTrue", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "FPFlagFalse", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 4194304, v2: 0}}, // R22 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: regMask{v1: 140737219919872, v2: 0}, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + outputs: []outputInfo{ + {0, regMask{v1: 16777216, v2: 0}}, // R25 + }, + }, + }, + { + name: "LoweredPubBarrier", + argLen: 1, + hasSideEffects: true, + asm: mips.ASYNC, + reg: regInfo{}, + }, + { + name: "LoweredPanicBoundsRR", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + {1, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + }, + }, + }, + { + name: "LoweredPanicBoundsRC", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + }, + }, + }, + { + name: "LoweredPanicBoundsCR", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + }, + }, + }, + { + name: "LoweredPanicBoundsCC", + auxType: auxPanicBoundsCC, + argLen: 1, + call: true, + reg: regInfo{}, + }, + { + name: "LoweredPanicExtendRR", + auxType: auxInt64, + argLen: 4, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 30, v2: 0}}, // R1 R2 R3 R4 + {1, regMask{v1: 30, v2: 0}}, // R1 R2 R3 R4 + {2, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + }, + }, + }, + { + name: "LoweredPanicExtendRC", + auxType: auxPanicBoundsC, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 30, v2: 0}}, // R1 R2 R3 R4 + {1, regMask{v1: 30, v2: 0}}, // R1 R2 R3 R4 + }, + }, + }, + + { + name: "ADDV", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "ADDVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: mips.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 268435454, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SUBV", + argLen: 2, + earlyOk: true, + asm: mips.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SUBVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: mips.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MULV", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AMULV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + clobbers: regMask{v1: 3458764513820540928, v2: 0}, // HI LO + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MULVU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AMULVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + clobbers: regMask{v1: 3458764513820540928, v2: 0}, // HI LO + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "DIVV", + argLen: 2, + asm: mips.ADIVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + clobbers: regMask{v1: 3458764513820540928, v2: 0}, // HI LO + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "DIVVU", + argLen: 2, + asm: mips.ADIVVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + clobbers: regMask{v1: 3458764513820540928, v2: 0}, // HI LO + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "ADDF", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AADDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ADDD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SUBF", + argLen: 2, + earlyOk: true, + asm: mips.ASUBF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SUBD", + argLen: 2, + earlyOk: true, + asm: mips.ASUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MULF", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AMULF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MULD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "DIVF", + argLen: 2, + earlyOk: true, + asm: mips.ADIVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + earlyOk: true, + asm: mips.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: mips.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: mips.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: mips.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "NOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: mips.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "NEGV", + argLen: 1, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "NEGF", + argLen: 1, + earlyOk: true, + asm: mips.ANEGF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "NEGD", + argLen: 1, + earlyOk: true, + asm: mips.ANEGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ABSF", + argLen: 1, + earlyOk: true, + asm: mips.AABSF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ABSD", + argLen: 1, + earlyOk: true, + asm: mips.AABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SQRTD", + argLen: 1, + earlyOk: true, + asm: mips.ASQRTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SQRTF", + argLen: 1, + earlyOk: true, + asm: mips.ASQRTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SLLV", + argLen: 2, + earlyOk: true, + asm: mips.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SLLVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: mips.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SRLV", + argLen: 2, + earlyOk: true, + asm: mips.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SRLVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: mips.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SRAV", + argLen: 2, + earlyOk: true, + asm: mips.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SRAVconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: mips.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SGT", + argLen: 2, + earlyOk: true, + asm: mips.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SGTconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: mips.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SGTU", + argLen: 2, + earlyOk: true, + asm: mips.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SGTUconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: mips.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "CMPEQF", + argLen: 2, + asm: mips.ACMPEQF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPEQD", + argLen: 2, + asm: mips.ACMPEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGEF", + argLen: 2, + asm: mips.ACMPGEF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGED", + argLen: 2, + asm: mips.ACMPGED, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGTF", + argLen: 2, + asm: mips.ACMPGTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGTD", + argLen: 2, + asm: mips.ACMPGTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: mips.AMOVV, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVFconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: mips.AMOVF, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: mips.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + earlyOk: true, + symEffect: SymAddr, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018460942336, v2: 0}}, // SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVVload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVFload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: mips.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVVstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVFstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: mips.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ZERO", + argLen: 0, + zeroWidth: true, + fixedReg: true, + earlyOk: true, + reg: regInfo{}, + }, + { + name: "MOVWfpgp", + argLen: 1, + earlyOk: true, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWgpfp", + argLen: 1, + earlyOk: true, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVfpgp", + argLen: 1, + earlyOk: true, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVVgpfp", + argLen: 1, + earlyOk: true, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVBUreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVHUreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWUreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVVreg", + argLen: 1, + earlyOk: true, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVVnop", + argLen: 1, + resultInArg0: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWF", + argLen: 1, + earlyOk: true, + asm: mips.AMOVWF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVWD", + argLen: 1, + earlyOk: true, + asm: mips.AMOVWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVF", + argLen: 1, + earlyOk: true, + asm: mips.AMOVVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVD", + argLen: 1, + earlyOk: true, + asm: mips.AMOVVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCFW", + argLen: 1, + earlyOk: true, + asm: mips.ATRUNCFW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCDW", + argLen: 1, + earlyOk: true, + asm: mips.ATRUNCDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCFV", + argLen: 1, + earlyOk: true, + asm: mips.ATRUNCFV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCDV", + argLen: 1, + earlyOk: true, + asm: mips.ATRUNCDV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVFD", + argLen: 1, + earlyOk: true, + asm: mips.AMOVFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDF", + argLen: 1, + earlyOk: true, + asm: mips.AMOVDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: regMask{v1: 4611686018393833470, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: regMask{v1: 4611686018393833470, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + }, + }, + { + name: "CALLtailinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + clobbers: regMask{v1: 4611686018393833470, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: 3, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 4194304, v2: 0}}, // R22 + {0, regMask{v1: 201326590, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 + }, + clobbers: regMask{v1: 4611686018393833470, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + clobbers: regMask{v1: 4611686018393833470, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + }, + }, + { + name: "DUFFZERO", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + clobbers: regMask{v1: 134217730, v2: 0}, // R1 R31 + }, + }, + { + name: "DUFFCOPY", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4, v2: 0}}, // R2 + {1, regMask{v1: 2, v2: 0}}, // R1 + }, + clobbers: regMask{v1: 134217734, v2: 0}, // R1 R2 R31 + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2, v2: 0}}, // R1 + {1, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + clobbers: regMask{v1: 2, v2: 0}, // R1 + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4, v2: 0}}, // R2 + {1, regMask{v1: 2, v2: 0}}, // R1 + {2, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + clobbers: regMask{v1: 6, v2: 0}, // R1 R2 + }, + }, + { + name: "LoweredAtomicAnd32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: mips.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicOr32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: mips.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicLoad8", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad64", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicStore8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore64", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStorezero32", + argLen: 2, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStorezero64", + argLen: 2, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicAddconst32", + auxType: auxInt32, + argLen: 2, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicAddconst64", + auxType: auxInt64, + argLen: 2, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicCas32", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {2, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicCas64", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {2, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + }, + }, + { + name: "FPFlagTrue", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "FPFlagFalse", + argLen: 1, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 4194304, v2: 0}}, // R22 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: regMask{v1: 4611686018293170176, v2: 0}, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + outputs: []outputInfo{ + {0, regMask{v1: 16777216, v2: 0}}, // R25 + }, + }, + }, + { + name: "LoweredPubBarrier", + argLen: 1, + hasSideEffects: true, + asm: mips.ASYNC, + reg: regInfo{}, + }, + { + name: "LoweredPanicBoundsRR", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + {1, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + }, + }, + }, + { + name: "LoweredPanicBoundsRC", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + }, + }, + }, + { + name: "LoweredPanicBoundsCR", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 + }, + }, + }, + { + name: "LoweredPanicBoundsCC", + auxType: auxPanicBoundsCC, + argLen: 1, + call: true, + reg: regInfo{}, + }, + + { + name: "ADD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDCC", + argLen: 2, + commutative: true, + asm: ppc64.AADDCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDCCconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AADDCCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FADD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AFADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FADDS", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AFADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "SUB", + argLen: 2, + earlyOk: true, + asm: ppc64.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBCC", + argLen: 2, + asm: ppc64.ASUBCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBFCconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ASUBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FSUB", + argLen: 2, + earlyOk: true, + asm: ppc64.AFSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FSUBS", + argLen: 2, + earlyOk: true, + asm: ppc64.AFSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "XSMINJDP", + argLen: 2, + earlyOk: true, + asm: ppc64.AXSMINJDP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "XSMAXJDP", + argLen: 2, + earlyOk: true, + asm: ppc64.AXSMAXJDP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "MULLD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULLW", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULLDconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: ppc64.AMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULLWconst", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: ppc64.AMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MADDLD", + argLen: 3, + earlyOk: true, + asm: ppc64.AMADDLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULHD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AMULHD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULHW", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AMULHW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULHDU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AMULHDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULHDUCC", + argLen: 2, + commutative: true, + asm: ppc64.AMULHDUCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULHWU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AMULHWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMUL", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AFMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMULS", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AFMULS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMADD", + argLen: 3, + earlyOk: true, + asm: ppc64.AFMADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMADDS", + argLen: 3, + earlyOk: true, + asm: ppc64.AFMADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMSUB", + argLen: 3, + earlyOk: true, + asm: ppc64.AFMSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMSUBS", + argLen: 3, + earlyOk: true, + asm: ppc64.AFMSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "SRAD", + argLen: 2, + earlyOk: true, + asm: ppc64.ASRAD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRAW", + argLen: 2, + earlyOk: true, + asm: ppc64.ASRAW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRD", + argLen: 2, + earlyOk: true, + asm: ppc64.ASRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRW", + argLen: 2, + earlyOk: true, + asm: ppc64.ASRW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SLD", + argLen: 2, + earlyOk: true, + asm: ppc64.ASLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SLW", + argLen: 2, + earlyOk: true, + asm: ppc64.ASLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ROTL", + argLen: 2, + earlyOk: true, + asm: ppc64.AROTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ROTLW", + argLen: 2, + earlyOk: true, + asm: ppc64.AROTLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CLRLSLWI", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: ppc64.ACLRLSLWI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CLRLSLDI", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: ppc64.ACLRLSLDI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDC", + argLen: 2, + commutative: true, + asm: ppc64.AADDC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {1, regMask{v1: 9223372036854775808, v2: 0}}, // XER + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBC", + argLen: 2, + asm: ppc64.ASUBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {1, regMask{v1: 9223372036854775808, v2: 0}}, // XER + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDCconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AADDC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {1, regMask{v1: 9223372036854775808, v2: 0}}, // XER + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBCconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ASUBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {1, regMask{v1: 9223372036854775808, v2: 0}}, // XER + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDE", + argLen: 3, + commutative: true, + asm: ppc64.AADDE, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 9223372036854775808, v2: 0}}, // XER + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {1, regMask{v1: 9223372036854775808, v2: 0}}, // XER + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDZE", + argLen: 2, + asm: ppc64.AADDZE, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 9223372036854775808, v2: 0}}, // XER + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {1, regMask{v1: 9223372036854775808, v2: 0}}, // XER + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBE", + argLen: 3, + asm: ppc64.ASUBE, + reg: regInfo{ + inputs: []inputInfo{ + {2, regMask{v1: 9223372036854775808, v2: 0}}, // XER + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {1, regMask{v1: 9223372036854775808, v2: 0}}, // XER + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDZEzero", + argLen: 1, + earlyOk: true, + asm: ppc64.AADDZE, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372036854775808, v2: 0}}, // XER + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBZEzero", + argLen: 1, + earlyOk: true, + asm: ppc64.ASUBZE, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372036854775808, v2: 0}}, // XER + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRADconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.ASRAD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRAWconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.ASRAW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRDconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.ASRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRWconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.ASRW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SLDconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.ASLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SLWconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.ASLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ROTLconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.AROTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ROTLWconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.AROTLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "EXTSWSLconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.AEXTSWSLI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLWINM", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.ARLWNM, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLWNM", + auxType: auxInt64, + argLen: 2, + earlyOk: true, + asm: ppc64.ARLWNM, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLWMI", + auxType: auxInt64, + argLen: 2, + resultInArg0: true, + earlyOk: true, + asm: ppc64.ARLWMI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLDICL", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.ARLDICL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLDICLCC", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ARLDICLCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLDICR", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.ARLDICR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CNTLZD", + argLen: 1, + earlyOk: true, + asm: ppc64.ACNTLZD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CNTLZDCC", + argLen: 1, + asm: ppc64.ACNTLZDCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CNTLZW", + argLen: 1, + earlyOk: true, + asm: ppc64.ACNTLZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CNTTZD", + argLen: 1, + earlyOk: true, + asm: ppc64.ACNTTZD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CNTTZW", + argLen: 1, + earlyOk: true, + asm: ppc64.ACNTTZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "POPCNTD", + argLen: 1, + earlyOk: true, + asm: ppc64.APOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "POPCNTW", + argLen: 1, + earlyOk: true, + asm: ppc64.APOPCNTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "POPCNTB", + argLen: 1, + earlyOk: true, + asm: ppc64.APOPCNTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FDIV", + argLen: 2, + earlyOk: true, + asm: ppc64.AFDIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FDIVS", + argLen: 2, + earlyOk: true, + asm: ppc64.AFDIVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + asm: ppc64.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "DIVW", + argLen: 2, + asm: ppc64.ADIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "DIVDU", + argLen: 2, + asm: ppc64.ADIVDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "DIVWU", + argLen: 2, + asm: ppc64.ADIVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MODUD", + argLen: 2, + asm: ppc64.AMODUD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MODSD", + argLen: 2, + asm: ppc64.AMODSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MODUW", + argLen: 2, + asm: ppc64.AMODUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MODSW", + argLen: 2, + asm: ppc64.AMODSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FCTIDZ", + argLen: 1, + earlyOk: true, + asm: ppc64.AFCTIDZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCTIWZ", + argLen: 1, + earlyOk: true, + asm: ppc64.AFCTIWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCFID", + argLen: 1, + earlyOk: true, + asm: ppc64.AFCFID, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCFIDS", + argLen: 1, + earlyOk: true, + asm: ppc64.AFCFIDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FRSP", + argLen: 1, + earlyOk: true, + asm: ppc64.AFRSP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "MFVSRD", + argLen: 1, + earlyOk: true, + asm: ppc64.AMFVSRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MTVSRD", + argLen: 1, + earlyOk: true, + asm: ppc64.AMTVSRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ANDN", + argLen: 2, + earlyOk: true, + asm: ppc64.AANDN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ANDNCC", + argLen: 2, + asm: ppc64.AANDNCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ANDCC", + argLen: 2, + commutative: true, + asm: ppc64.AANDCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ORN", + argLen: 2, + earlyOk: true, + asm: ppc64.AORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ORCC", + argLen: 2, + commutative: true, + asm: ppc64.AORCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "NOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "NORCC", + argLen: 2, + commutative: true, + asm: ppc64.ANORCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "XORCC", + argLen: 2, + commutative: true, + asm: ppc64.AXORCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "EQV", + argLen: 2, + commutative: true, + earlyOk: true, + asm: ppc64.AEQV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "NEG", + argLen: 1, + earlyOk: true, + asm: ppc64.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "NEGCC", + argLen: 1, + asm: ppc64.ANEGCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "BRD", + argLen: 1, + earlyOk: true, + asm: ppc64.ABRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "BRW", + argLen: 1, + earlyOk: true, + asm: ppc64.ABRW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "BRH", + argLen: 1, + earlyOk: true, + asm: ppc64.ABRH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FNEG", + argLen: 1, + earlyOk: true, + asm: ppc64.AFNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FSQRT", + argLen: 1, + earlyOk: true, + asm: ppc64.AFSQRT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FSQRTS", + argLen: 1, + earlyOk: true, + asm: ppc64.AFSQRTS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FFLOOR", + argLen: 1, + earlyOk: true, + asm: ppc64.AFRIM, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCEIL", + argLen: 1, + earlyOk: true, + asm: ppc64.AFRIP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FTRUNC", + argLen: 1, + earlyOk: true, + asm: ppc64.AFRIZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FROUND", + argLen: 1, + earlyOk: true, + asm: ppc64.AFRIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FABS", + argLen: 1, + earlyOk: true, + asm: ppc64.AFABS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FNABS", + argLen: 1, + earlyOk: true, + asm: ppc64.AFNABS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCPSGN", + argLen: 2, + earlyOk: true, + asm: ppc64.AFCPSGN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ANDCCconst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: ppc64.AANDCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: ppc64.AANDCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + earlyOk: true, + asm: ppc64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVBZreg", + argLen: 1, + earlyOk: true, + asm: ppc64.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + earlyOk: true, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHZreg", + argLen: 1, + earlyOk: true, + asm: ppc64.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + earlyOk: true, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWZreg", + argLen: 1, + earlyOk: true, + asm: ppc64.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVBZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDBRload", + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + asm: ppc64.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWBRload", + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + asm: ppc64.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHBRload", + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + asm: ppc64.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVBZloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHZloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWZloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHBRloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWBRloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDBRloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMOVDloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMOVSloadidx", + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "DCBT", + auxType: auxInt64, + argLen: 2, + hasSideEffects: true, + asm: ppc64.ADCBT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDBRstore", + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + asm: ppc64.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWBRstore", + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + asm: ppc64.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHBRstore", + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + asm: ppc64.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: ppc64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMOVSload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: ppc64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: ppc64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMOVSstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: ppc64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "MOVBstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMOVDstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMOVSstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "MOVHBRstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWBRstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDBRstoreidx", + argLen: 4, + addrSinkArg0: true, + addrSinkArg1: true, + asm: ppc64.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVBstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + earlyOk: true, + symEffect: SymAddr, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: ppc64.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: ppc64.AFMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMOVSconst", + auxType: auxFloat32, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: ppc64.AFMOVS, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCMPU", + argLen: 2, + asm: ppc64.AFCMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "CMP", + argLen: 2, + asm: ppc64.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPU", + argLen: 2, + asm: ppc64.ACMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPW", + argLen: 2, + asm: ppc64.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPWU", + argLen: 2, + asm: ppc64.ACMPWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPUconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ACMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPWconst", + auxType: auxInt32, + argLen: 1, + asm: ppc64.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPWUconst", + auxType: auxInt32, + argLen: 1, + asm: ppc64.ACMPWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ISEL", + auxType: auxInt32, + argLen: 3, + earlyOk: true, + asm: ppc64.AISEL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ISELZ", + auxType: auxInt32, + argLen: 2, + earlyOk: true, + asm: ppc64.AISEL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SETBC", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: ppc64.ASETBC, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SETBCR", + auxType: auxInt32, + argLen: 1, + earlyOk: true, + asm: ppc64.ASETBCR, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "Equal", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "NotEqual", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LessThan", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FLessThan", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LessEqual", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FLessEqual", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "GreaterThan", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FGreaterThan", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "GreaterEqual", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FGreaterEqual", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 2048, v2: 0}}, // R11 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + clobberFlags: true, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: regMask{v1: 2147483648, v2: 0}, // R31 + }, + }, + { + name: "LoweredRound32F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "LoweredRound64F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: regMask{v1: 18446744071562059768, v2: 0}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: regMask{v1: 18446744071562059768, v2: 0}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + }, + }, + { + name: "CALLtailinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4096, v2: 0}}, // R12 + }, + clobbers: regMask{v1: 18446744071562059768, v2: 0}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4096, v2: 0}}, // R12 + {1, regMask{v1: 2048, v2: 0}}, // R11 + }, + clobbers: regMask{v1: 18446744071562059768, v2: 0}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4096, v2: 0}}, // R12 + }, + clobbers: regMask{v1: 18446744071562059768, v2: 0}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1048576, v2: 0}}, // R20 + }, + clobbers: regMask{v1: 1048576, v2: 0}, // R20 + }, + }, + { + name: "LoweredZeroShort", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredQuadZeroShort", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredQuadZero", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1048576, v2: 0}}, // R20 + }, + clobbers: regMask{v1: 1048576, v2: 0}, // R20 + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1048576, v2: 0}}, // R20 + {1, regMask{v1: 2097152, v2: 0}}, // R21 + }, + clobbers: regMask{v1: 3145728, v2: 0}, // R20 R21 + }, + }, + { + name: "LoweredMoveShort", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredQuadMove", + auxType: auxInt64, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1048576, v2: 0}}, // R20 + {1, regMask{v1: 2097152, v2: 0}}, // R21 + }, + clobbers: regMask{v1: 3145728, v2: 0}, // R20 R21 + }, + }, + { + name: "LoweredQuadMoveShort", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicStore8", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicStore32", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicStore64", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicLoad8", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicLoad64", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicLoadPtr", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicExchange8", + argLen: 3, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicCas64", + auxType: auxInt64, + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicCas32", + auxType: auxInt64, + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicAnd8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: ppc64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicAnd32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: ppc64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicOr8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: ppc64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicOr32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: ppc64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: regMask{v1: 18446744072632408064, v2: 0}, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + outputs: []outputInfo{ + {0, regMask{v1: 536870912, v2: 0}}, // R29 + }, + }, + }, + { + name: "LoweredPubBarrier", + argLen: 1, + hasSideEffects: true, + asm: ppc64.ALWSYNC, + reg: regInfo{}, + }, + { + name: "LoweredPanicBoundsRR", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1016, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 + {1, regMask{v1: 1016, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 + }, + }, + }, + { + name: "LoweredPanicBoundsRC", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1016, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 + }, + }, + }, + { + name: "LoweredPanicBoundsCR", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1016, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 + }, + }, + }, + { + name: "LoweredPanicBoundsCC", + auxType: auxPanicBoundsCC, + argLen: 1, + call: true, + reg: regInfo{}, + }, + { + name: "InvertFlags", + argLen: 1, + reg: regInfo{}, + }, + { + name: "FlagEQ", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagLT", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagGT", + argLen: 0, + reg: regInfo{}, + }, + + { + name: "ADD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ADDI", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.AADDI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ADDIW", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.AADDIW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "NEG", + argLen: 1, + earlyOk: true, + asm: riscv.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "NEGW", + argLen: 1, + earlyOk: true, + asm: riscv.ANEGW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SUB", + argLen: 2, + earlyOk: true, + asm: riscv.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SUBW", + argLen: 2, + earlyOk: true, + asm: riscv.ASUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MUL", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MULW", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AMULW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MULH", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AMULH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MULHU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AMULHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredMuluhilo", + argLen: 2, + resultNotInArgs: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredMuluover", + argLen: 2, + resultNotInArgs: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "DIV", + argLen: 2, + earlyOk: true, + asm: riscv.ADIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "DIVU", + argLen: 2, + earlyOk: true, + asm: riscv.ADIVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "DIVW", + argLen: 2, + earlyOk: true, + asm: riscv.ADIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "DIVUW", + argLen: 2, + earlyOk: true, + asm: riscv.ADIVUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "REM", + argLen: 2, + earlyOk: true, + asm: riscv.AREM, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "REMU", + argLen: 2, + earlyOk: true, + asm: riscv.AREMU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "REMW", + argLen: 2, + earlyOk: true, + asm: riscv.AREMW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "REMUW", + argLen: 2, + earlyOk: true, + asm: riscv.AREMUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + earlyOk: true, + symEffect: SymAddr, + asm: riscv.AMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: riscv.AMOV, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FMOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: riscv.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVFconst", + auxType: auxFloat32, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: riscv.AMOVF, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: riscv.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: riscv.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: riscv.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: riscv.AMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: riscv.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: riscv.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVWUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: riscv.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1006632946, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1006632946, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1006632946, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: riscv.AMOV, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1006632946, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVBstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVHstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVWstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVDstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: riscv.AMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + earlyOk: true, + asm: riscv.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + earlyOk: true, + asm: riscv.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + earlyOk: true, + asm: riscv.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVDreg", + argLen: 1, + earlyOk: true, + asm: riscv.AMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVBUreg", + argLen: 1, + earlyOk: true, + asm: riscv.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVHUreg", + argLen: 1, + earlyOk: true, + asm: riscv.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVWUreg", + argLen: 1, + earlyOk: true, + asm: riscv.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVDnop", + argLen: 1, + resultInArg0: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLL", + argLen: 2, + earlyOk: true, + asm: riscv.ASLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLLW", + argLen: 2, + earlyOk: true, + asm: riscv.ASLLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRA", + argLen: 2, + earlyOk: true, + asm: riscv.ASRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRAW", + argLen: 2, + earlyOk: true, + asm: riscv.ASRAW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRL", + argLen: 2, + earlyOk: true, + asm: riscv.ASRL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRLW", + argLen: 2, + earlyOk: true, + asm: riscv.ASRLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLLI", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.ASLLI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLLIW", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.ASLLIW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRAI", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.ASRAI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRAIW", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.ASRAIW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRLI", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.ASRLI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRLIW", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.ASRLIW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SH1ADD", + argLen: 2, + earlyOk: true, + asm: riscv.ASH1ADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SH2ADD", + argLen: 2, + earlyOk: true, + asm: riscv.ASH2ADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SH3ADD", + argLen: 2, + earlyOk: true, + asm: riscv.ASH3ADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ANDN", + argLen: 2, + earlyOk: true, + asm: riscv.AANDN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ANDI", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.AANDI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CLZ", + argLen: 1, + earlyOk: true, + asm: riscv.ACLZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CLZW", + argLen: 1, + earlyOk: true, + asm: riscv.ACLZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CPOP", + argLen: 1, + asm: riscv.ACPOP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CPOPW", + argLen: 1, + asm: riscv.ACPOPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CTZ", + argLen: 1, + earlyOk: true, + asm: riscv.ACTZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CTZW", + argLen: 1, + earlyOk: true, + asm: riscv.ACTZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "NOT", + argLen: 1, + earlyOk: true, + asm: riscv.ANOT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ORN", + argLen: 2, + earlyOk: true, + asm: riscv.AORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ORI", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.AORI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "REV8", + argLen: 1, + earlyOk: true, + asm: riscv.AREV8, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ROL", + argLen: 2, + earlyOk: true, + asm: riscv.AROL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ROLW", + argLen: 2, + earlyOk: true, + asm: riscv.AROLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ROR", + argLen: 2, + earlyOk: true, + asm: riscv.AROR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "RORI", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.ARORI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "RORIW", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.ARORIW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "RORW", + argLen: 2, + earlyOk: true, + asm: riscv.ARORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "XNOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AXNOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "XORI", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.AXORI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MIN", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AMIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MAX", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AMAX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MINU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AMINU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MAXU", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AMAXU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SEQZ", + argLen: 1, + earlyOk: true, + asm: riscv.ASEQZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SNEZ", + argLen: 1, + earlyOk: true, + asm: riscv.ASNEZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLT", + argLen: 2, + earlyOk: true, + asm: riscv.ASLT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLTI", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.ASLTI, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLTU", + argLen: 2, + earlyOk: true, + asm: riscv.ASLTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLTIU", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: riscv.ASLTIU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredRound32F", + argLen: 1, + resultInArg0: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LoweredRound64F", + argLen: 1, + resultInArg0: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: -1, + call: true, + reg: regInfo{ + clobbers: regMask{v1: 9223372035781033968, v2: 0}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: -1, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: regMask{v1: 9223372035781033968, v2: 0}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLtailinter", + auxType: auxCallOff, + argLen: -1, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632928, v2: 0}}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + clobbers: regMask{v1: 9223372035781033968, v2: 0}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: -1, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 33554432, v2: 0}}, // X26 + {0, regMask{v1: 1006632930, v2: 0}}, // SP X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + clobbers: regMask{v1: 9223372035781033968, v2: 0}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: -1, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632928, v2: 0}}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + clobbers: regMask{v1: 9223372035781033968, v2: 0}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "LoweredZero", + auxType: auxSizeAndAlign, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredZeroLoop", + auxType: auxSizeAndAlign, + argLen: 2, + needIntTemp: true, + faultOnNilArg0: true, + addrSinkArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + clobbersArg0: true, + }, + }, + { + name: "LoweredMove", + auxType: auxSizeAndAlign, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632928, v2: 0}}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632928, v2: 0}}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + clobbers: regMask{v1: 16, v2: 0}, // X5 + }, + }, + { + name: "LoweredMoveLoop", + auxType: auxSizeAndAlign, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632896, v2: 0}}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632896, v2: 0}}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + clobbers: regMask{v1: 48, v2: 0}, // X5 X6 + clobbersArg0: true, + clobbersArg1: true, + }, + }, + { + name: "LoweredAtomicLoad8", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicLoad64", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicStore8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1006632946, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "LoweredAtomicStore32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1006632946, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "LoweredAtomicStore64", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1006632946, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741808, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741808, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741808, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741808, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicCas32", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741808, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {2, regMask{v1: 1073741808, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicCas64", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741808, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {2, regMask{v1: 1073741808, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicAnd32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: riscv.AAMOANDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741808, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + }, + }, + { + name: "LoweredAtomicOr32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: riscv.AAMOORW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1073741808, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632946, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 33554432, v2: 0}}, // X26 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: regMask{v1: 9223372034707292160, v2: 0}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + outputs: []outputInfo{ + {0, regMask{v1: 8388608, v2: 0}}, // X24 + }, + }, + }, + { + name: "LoweredPubBarrier", + argLen: 1, + hasSideEffects: true, + asm: riscv.AFENCE, + reg: regInfo{}, + }, + { + name: "LoweredPanicBoundsRR", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1048560, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 + {1, regMask{v1: 1048560, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 + }, + }, + }, + { + name: "LoweredPanicBoundsRC", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1048560, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 + }, + }, + }, + { + name: "LoweredPanicBoundsCR", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1048560, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 + }, + }, + }, + { + name: "LoweredPanicBoundsCC", + auxType: auxPanicBoundsCC, + argLen: 1, + call: true, + reg: regInfo{}, + }, + { + name: "FADDS", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AFADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSUBS", + argLen: 2, + earlyOk: true, + asm: riscv.AFSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMULS", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AFMULS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FDIVS", + argLen: 2, + earlyOk: true, + asm: riscv.AFDIVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMADDS", + argLen: 3, + commutative: true, + earlyOk: true, + asm: riscv.AFMADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMSUBS", + argLen: 3, + commutative: true, + earlyOk: true, + asm: riscv.AFMSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMADDS", + argLen: 3, + commutative: true, + earlyOk: true, + asm: riscv.AFNMADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMSUBS", + argLen: 3, + commutative: true, + earlyOk: true, + asm: riscv.AFNMSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSQRTS", + argLen: 1, + earlyOk: true, + asm: riscv.AFSQRTS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FABSS", + argLen: 1, + earlyOk: true, + asm: riscv.AFABSS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNEGS", + argLen: 1, + earlyOk: true, + asm: riscv.AFNEGS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMVSX", + argLen: 1, + earlyOk: true, + asm: riscv.AFMVSX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMVXS", + argLen: 1, + earlyOk: true, + asm: riscv.AFMVXS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FCVTSW", + argLen: 1, + earlyOk: true, + asm: riscv.AFCVTSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTSL", + argLen: 1, + earlyOk: true, + asm: riscv.AFCVTSL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTWS", + argLen: 1, + earlyOk: true, + asm: riscv.AFCVTWS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FCVTLS", + argLen: 1, + earlyOk: true, + asm: riscv.AFCVTLS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FMOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: riscv.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FEQS", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AFEQS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FNES", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AFNES, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FLTS", + argLen: 2, + earlyOk: true, + asm: riscv.AFLTS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FLES", + argLen: 2, + earlyOk: true, + asm: riscv.AFLES, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredFMAXS", + argLen: 2, + commutative: true, + resultNotInArgs: true, + earlyOk: true, + asm: riscv.AFMAXS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LoweredFMINS", + argLen: 2, + commutative: true, + resultNotInArgs: true, + earlyOk: true, + asm: riscv.AFMINS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FADDD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AFADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSUBD", + argLen: 2, + earlyOk: true, + asm: riscv.AFSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMULD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AFMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FDIVD", + argLen: 2, + earlyOk: true, + asm: riscv.AFDIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMADDD", + argLen: 3, + commutative: true, + earlyOk: true, + asm: riscv.AFMADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMSUBD", + argLen: 3, + commutative: true, + earlyOk: true, + asm: riscv.AFMSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMADDD", + argLen: 3, + commutative: true, + earlyOk: true, + asm: riscv.AFNMADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMSUBD", + argLen: 3, + commutative: true, + earlyOk: true, + asm: riscv.AFNMSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSQRTD", + argLen: 1, + earlyOk: true, + asm: riscv.AFSQRTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNEGD", + argLen: 1, + earlyOk: true, + asm: riscv.AFNEGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FABSD", + argLen: 1, + earlyOk: true, + asm: riscv.AFABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSGNJD", + argLen: 2, + earlyOk: true, + asm: riscv.AFSGNJD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMVDX", + argLen: 1, + earlyOk: true, + asm: riscv.AFMVDX, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMVXD", + argLen: 1, + earlyOk: true, + asm: riscv.AFMVXD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FCVTDW", + argLen: 1, + earlyOk: true, + asm: riscv.AFCVTDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTDL", + argLen: 1, + earlyOk: true, + asm: riscv.AFCVTDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTWD", + argLen: 1, + earlyOk: true, + asm: riscv.AFCVTWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FCVTLD", + argLen: 1, + earlyOk: true, + asm: riscv.AFCVTLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FCVTDS", + argLen: 1, + earlyOk: true, + asm: riscv.AFCVTDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTSD", + argLen: 1, + earlyOk: true, + asm: riscv.AFCVTSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: riscv.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FEQD", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AFEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FNED", + argLen: 2, + commutative: true, + earlyOk: true, + asm: riscv.AFNED, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FLTD", + argLen: 2, + earlyOk: true, + asm: riscv.AFLTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FLED", + argLen: 2, + earlyOk: true, + asm: riscv.AFLED, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredFMIND", + argLen: 2, + commutative: true, + resultNotInArgs: true, + earlyOk: true, + asm: riscv.AFMIND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LoweredFMAXD", + argLen: 2, + commutative: true, + resultNotInArgs: true, + earlyOk: true, + asm: riscv.AFMAXD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCLASSS", + argLen: 1, + earlyOk: true, + asm: riscv.AFCLASSS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FCLASSD", + argLen: 1, + earlyOk: true, + asm: riscv.AFCLASSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CZEROEQZ", + argLen: 2, + asm: riscv.ACZEROEQZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CZERONEZ", + argLen: 2, + asm: riscv.ACZERONEZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + + { + name: "FADDS", + argLen: 2, + commutative: true, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FADD", + argLen: 2, + commutative: true, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FSUBS", + argLen: 2, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FSUB", + argLen: 2, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMULS", + argLen: 2, + commutative: true, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFMULS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMUL", + argLen: 2, + commutative: true, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FDIVS", + argLen: 2, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFDIVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FDIV", + argLen: 2, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFDIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FNEGS", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.AFNEGS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FNEG", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.AFNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMADDS", + argLen: 3, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFMADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMADD", + argLen: 3, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFMADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMSUBS", + argLen: 3, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFMSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMSUB", + argLen: 3, + resultInArg0: true, + earlyOk: true, + asm: s390x.AFMSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LPDFR", + argLen: 1, + earlyOk: true, + asm: s390x.ALPDFR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LNDFR", + argLen: 1, + earlyOk: true, + asm: s390x.ALNDFR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CPSDR", + argLen: 2, + earlyOk: true, + asm: s390x.ACPSDR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "WFMAXDB", + argLen: 2, + earlyOk: true, + asm: s390x.AWFMAXDB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "WFMAXSB", + argLen: 2, + earlyOk: true, + asm: s390x.AWFMAXSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "WFMINDB", + argLen: 2, + earlyOk: true, + asm: s390x.AWFMINDB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "WFMINSB", + argLen: 2, + earlyOk: true, + asm: s390x.AWFMINSB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FIDBR", + auxType: auxInt8, + argLen: 1, + earlyOk: true, + asm: s390x.AFIDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVSload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVSconst", + auxType: auxFloat32, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: s390x.AFMOVS, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: s390x.AFMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVSloadidx", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVDloadidx", + auxType: auxSymOff, + argLen: 3, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVSstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVSstoreidx", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVDstoreidx", + auxType: auxSymOff, + argLen: 4, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "ADD", + argLen: 2, + commutative: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDW", + argLen: 2, + commutative: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AADDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDconst", + auxType: auxInt32, + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDWconst", + auxType: auxInt32, + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.AADDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AADDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUB", + argLen: 2, + clobberFlags: true, + earlyOk: true, + asm: s390x.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBW", + argLen: 2, + clobberFlags: true, + earlyOk: true, + asm: s390x.ASUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBWconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.ASUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.ASUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLD", + argLen: 2, + commutative: true, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLW", + argLen: 2, + commutative: true, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLDconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLWconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLDload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULHD", + argLen: 2, + commutative: true, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AMULHD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2048, v2: 0}, // R11 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MULHDU", + argLen: 2, + commutative: true, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AMULHDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2048, v2: 0}, // R11 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2048, v2: 0}, // R11 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "DIVW", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ADIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2048, v2: 0}, // R11 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "DIVDU", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ADIVDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2048, v2: 0}, // R11 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "DIVWU", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ADIVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2048, v2: 0}, // R11 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MODD", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMODD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2048, v2: 0}, // R11 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MODW", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMODW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2048, v2: 0}, // R11 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MODDU", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMODDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2048, v2: 0}, // R11 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MODWU", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMODWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: regMask{v1: 2048, v2: 0}, // R11 + outputs: []outputInfo{ + {0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ANDW", + argLen: 2, + commutative: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AANDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ANDWconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AANDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ANDload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ANDWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AANDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ORW", + argLen: 2, + commutative: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt64, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ORWconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ORload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ORWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XORW", + argLen: 2, + commutative: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AXORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt64, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XORWconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.AXORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XORload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XORWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AXORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDC", + argLen: 2, + commutative: true, + asm: s390x.AADDC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDCconst", + auxType: auxInt16, + argLen: 1, + asm: s390x.AADDC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDE", + argLen: 3, + commutative: true, + resultInArg0: true, + asm: s390x.AADDE, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBC", + argLen: 2, + asm: s390x.ASUBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBE", + argLen: 3, + resultInArg0: true, + asm: s390x.ASUBE, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CMP", + argLen: 2, + asm: s390x.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPW", + argLen: 2, + asm: s390x.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPU", + argLen: 2, + asm: s390x.ACMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPWU", + argLen: 2, + asm: s390x.ACMPWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPconst", + auxType: auxInt32, + argLen: 1, + asm: s390x.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPWconst", + auxType: auxInt32, + argLen: 1, + asm: s390x.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPUconst", + auxType: auxInt32, + argLen: 1, + asm: s390x.ACMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPWUconst", + auxType: auxInt32, + argLen: 1, + asm: s390x.ACMPWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "FCMPS", + argLen: 2, + asm: s390x.ACEBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FCMP", + argLen: 2, + asm: s390x.AFCMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LTDBR", + argLen: 1, + asm: s390x.ALTDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LTEBR", + argLen: 1, + asm: s390x.ALTEBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "SLD", + argLen: 2, + earlyOk: true, + asm: s390x.ASLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SLW", + argLen: 2, + earlyOk: true, + asm: s390x.ASLW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SLDconst", + auxType: auxUInt8, + argLen: 1, + earlyOk: true, + asm: s390x.ASLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SLWconst", + auxType: auxUInt8, + argLen: 1, + earlyOk: true, + asm: s390x.ASLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRD", + argLen: 2, + earlyOk: true, + asm: s390x.ASRD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRW", + argLen: 2, + earlyOk: true, + asm: s390x.ASRW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRDconst", + auxType: auxUInt8, + argLen: 1, + earlyOk: true, + asm: s390x.ASRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRWconst", + auxType: auxUInt8, + argLen: 1, + earlyOk: true, + asm: s390x.ASRW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRAD", + argLen: 2, + clobberFlags: true, + earlyOk: true, + asm: s390x.ASRAD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRAW", + argLen: 2, + clobberFlags: true, + earlyOk: true, + asm: s390x.ASRAW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRADconst", + auxType: auxUInt8, + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ASRAD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRAWconst", + auxType: auxUInt8, + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ASRAW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "RLLG", + argLen: 2, + earlyOk: true, + asm: s390x.ARLLG, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "RLL", + argLen: 2, + earlyOk: true, + asm: s390x.ARLL, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "RLLconst", + auxType: auxUInt8, + argLen: 1, + earlyOk: true, + asm: s390x.ARLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "RXSBG", + auxType: auxS390XRotateParams, + argLen: 2, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + asm: s390x.ARXSBG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "RISBGZ", + auxType: auxS390XRotateParams, + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ARISBGZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "NEG", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "NEGW", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ANEGW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "NOT", + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "NOTW", + argLen: 1, + resultInArg0: true, + clobberFlags: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "FSQRT", + argLen: 1, + earlyOk: true, + asm: s390x.AFSQRT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FSQRTS", + argLen: 1, + earlyOk: true, + asm: s390x.AFSQRTS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LOCGR", + auxType: auxS390XCCMask, + argLen: 3, + resultInArg0: true, + earlyOk: true, + asm: s390x.ALOCGR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + earlyOk: true, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBZreg", + argLen: 1, + earlyOk: true, + asm: s390x.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + earlyOk: true, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHZreg", + argLen: 1, + earlyOk: true, + asm: s390x.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + earlyOk: true, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWZreg", + argLen: 1, + earlyOk: true, + asm: s390x.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + asm: s390x.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LDGR", + argLen: 1, + earlyOk: true, + asm: s390x.ALDGR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LGDR", + argLen: 1, + earlyOk: true, + asm: s390x.ALGDR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CFDBRA", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACFDBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CGDBRA", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACGDBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CFEBRA", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACFEBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CGEBRA", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACGEBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CEFBRA", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACEFBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CDFBRA", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACDFBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CEGBRA", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACEGBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CDGBRA", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACDGBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CLFEBR", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACLFEBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CLFDBR", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACLFDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CLGEBR", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACLGEBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CLGDBR", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACLGDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CELFBR", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACELFBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CDLFBR", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACDLFBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CELGBR", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACELGBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CDLGBR", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.ACDLGBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LEDBR", + argLen: 1, + earlyOk: true, + asm: s390x.ALEDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LDEBR", + argLen: 1, + earlyOk: true, + asm: s390x.ALDEBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVDaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + earlyOk: true, + symEffect: SymAddr, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295000064, v2: 0}}, // SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDaddridx", + auxType: auxSymOff, + argLen: 2, + earlyOk: true, + symEffect: SymAddr, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295000064, v2: 0}}, // SP SB + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWBR", + argLen: 1, + earlyOk: true, + asm: s390x.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDBR", + argLen: 1, + earlyOk: true, + asm: s390x.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHBRload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWBRload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDBRload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymRead, + asm: s390x.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVHBRstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVWBRstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVDBRstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MVC", + auxType: auxSymValAndOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + symEffect: SymNone, + asm: s390x.AMVC, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVBZloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHZloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWZloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHBRloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWBRloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDBRloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymRead, + asm: s390x.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVHstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVWstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVDstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVHBRstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: s390x.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVWBRstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: s390x.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVDBRstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + addrSinkArg0: true, + addrSinkArg1: true, + symEffect: SymWrite, + asm: s390x.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVBstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + }, + }, + { + name: "MOVHstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + }, + }, + { + name: "MOVWstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + }, + }, + { + name: "MOVDstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + }, + }, + { + name: "CLEAR", + auxType: auxSymValAndOff, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.ACLEAR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: regMask{v1: 4294933503, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: regMask{v1: 4294933503, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLtailinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + clobbers: regMask{v1: 4294933503, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 4096, v2: 0}}, // R12 + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: regMask{v1: 4294933503, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + clobbers: regMask{v1: 4294933503, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "InvertFlags", + argLen: 1, + reg: regInfo{}, + }, + { + name: "LoweredGetG", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 4096, v2: 0}}, // R12 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + clobberFlags: true, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "LoweredRound32F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LoweredRound64F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, + earlyOk: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: regMask{v1: 4294918146, v2: 0}, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + outputs: []outputInfo{ + {0, regMask{v1: 512, v2: 0}}, // R9 + }, + }, + }, + { + name: "LoweredPanicBoundsRR", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 7167, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 + {1, regMask{v1: 7167, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 + }, + }, + }, + { + name: "LoweredPanicBoundsRC", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 7167, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 + }, + }, + }, + { + name: "LoweredPanicBoundsCR", + auxType: auxPanicBoundsC, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 7167, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 + }, + }, + }, + { + name: "LoweredPanicBoundsCC", + auxType: auxPanicBoundsCC, + argLen: 1, + call: true, + reg: regInfo{}, + }, + { + name: "FlagEQ", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagLT", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagGT", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagOV", + argLen: 0, + reg: regInfo{}, + }, + { + name: "SYNC", + argLen: 1, + asm: s390x.ASYNC, + reg: regInfo{}, + }, + { + name: "MOVBZatomicload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWZatomicload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDatomicload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBatomicstore", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymWrite, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVWatomicstore", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymWrite, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVDatomicstore", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymWrite, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "LAA", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ALAA, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LAAG", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ALAAG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "AddTupleFirst32", + argLen: 2, + reg: regInfo{}, + }, + { + name: "AddTupleFirst64", + argLen: 2, + reg: regInfo{}, + }, + { + name: "LAN", + argLen: 3, + clobberFlags: true, + hasSideEffects: true, + asm: s390x.ALAN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "LANfloor", + argLen: 3, + clobberFlags: true, + hasSideEffects: true, + asm: s390x.ALAN, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2, v2: 0}}, // R1 + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: regMask{v1: 2, v2: 0}, // R1 + }, + }, + { + name: "LAO", + argLen: 3, + clobberFlags: true, + hasSideEffects: true, + asm: s390x.ALAO, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "LAOfloor", + argLen: 3, + clobberFlags: true, + hasSideEffects: true, + asm: s390x.ALAO, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2, v2: 0}}, // R1 + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: regMask{v1: 2, v2: 0}, // R1 + }, + }, + { + name: "LoweredAtomicCas32", + auxType: auxSymOff, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ACS, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1, v2: 0}}, // R0 + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: regMask{v1: 1, v2: 0}, // R0 + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LoweredAtomicCas64", + auxType: auxSymOff, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ACSG, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 1, v2: 0}}, // R0 + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: regMask{v1: 1, v2: 0}, // R0 + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LoweredAtomicExchange32", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ACS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 1, v2: 0}}, // R0 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ACSG, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {1, regMask{v1: 0, v2: 0}}, + {0, regMask{v1: 1, v2: 0}}, // R0 + }, + }, + }, + { + name: "FLOGR", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.AFLOGR, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + clobbers: regMask{v1: 2, v2: 0}, // R1 + outputs: []outputInfo{ + {0, regMask{v1: 1, v2: 0}}, // R0 + }, + }, + }, + { + name: "POPCNT", + argLen: 1, + clobberFlags: true, + earlyOk: true, + asm: s390x.APOPCNT, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MLGR", + argLen: 2, + earlyOk: true, + asm: s390x.AMLGR, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 8, v2: 0}}, // R3 + {0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4, v2: 0}}, // R2 + {1, regMask{v1: 8, v2: 0}}, // R3 + }, + }, + }, + { + name: "SumBytes2", + argLen: 1, + earlyOk: true, + reg: regInfo{}, + }, + { + name: "SumBytes4", + argLen: 1, + earlyOk: true, + reg: regInfo{}, + }, + { + name: "SumBytes8", + argLen: 1, + earlyOk: true, + reg: regInfo{}, + }, + { + name: "STMG2", + auxType: auxSymOff, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMG, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 2, v2: 0}}, // R1 + {2, regMask{v1: 4, v2: 0}}, // R2 + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "STMG3", + auxType: auxSymOff, + argLen: 5, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMG, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 2, v2: 0}}, // R1 + {2, regMask{v1: 4, v2: 0}}, // R2 + {3, regMask{v1: 8, v2: 0}}, // R3 + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "STMG4", + auxType: auxSymOff, + argLen: 6, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMG, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 2, v2: 0}}, // R1 + {2, regMask{v1: 4, v2: 0}}, // R2 + {3, regMask{v1: 8, v2: 0}}, // R3 + {4, regMask{v1: 16, v2: 0}}, // R4 + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "STM2", + auxType: auxSymOff, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMY, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 2, v2: 0}}, // R1 + {2, regMask{v1: 4, v2: 0}}, // R2 + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "STM3", + auxType: auxSymOff, + argLen: 5, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMY, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 2, v2: 0}}, // R1 + {2, regMask{v1: 4, v2: 0}}, // R2 + {3, regMask{v1: 8, v2: 0}}, // R3 + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "STM4", + auxType: auxSymOff, + argLen: 6, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMY, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 2, v2: 0}}, // R1 + {2, regMask{v1: 4, v2: 0}}, // R2 + {3, regMask{v1: 8, v2: 0}}, // R3 + {4, regMask{v1: 16, v2: 0}}, // R4 + {0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2, v2: 0}}, // R1 + {1, regMask{v1: 4, v2: 0}}, // R2 + {2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: regMask{v1: 6, v2: 0}, // R1 R2 + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 2, v2: 0}}, // R1 + {1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: regMask{v1: 2, v2: 0}, // R1 + }, + }, + + { + name: "LoweredStaticCall", + auxType: auxCallOff, + argLen: 1, + call: true, + reg: regInfo{ + clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g + }, + }, + { + name: "LoweredTailCall", + auxType: auxCallOff, + argLen: 1, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g + }, + }, + { + name: "LoweredTailCallInter", + auxType: auxCallOff, + argLen: 2, + call: true, + tailCall: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g + }, + }, + { + name: "LoweredClosureCall", + auxType: auxCallOff, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g + }, + }, + { + name: "LoweredInterCall", + auxType: auxCallOff, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g + }, + }, + { + name: "LoweredAddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + earlyOk: true, + symEffect: SymAddr, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 3, + addrSinkArg0: true, + addrSinkArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + reg: regInfo{ + clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredConvert", + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "Select", + argLen: 3, + earlyOk: true, + asm: wasm.ASelect, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {2, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "SelectV", + argLen: 3, + earlyOk: true, + asm: wasm.ASelect, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {2, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64Load8U", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + asm: wasm.AI64Load8U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load8S", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + asm: wasm.AI64Load8S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load16U", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + asm: wasm.AI64Load16U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load16S", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + asm: wasm.AI64Load16S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load32U", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + asm: wasm.AI64Load32U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load32S", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + asm: wasm.AI64Load32S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + asm: wasm.AI64Load, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Store8", + auxType: auxInt64, + argLen: 3, + addrSinkArg0: true, + asm: wasm.AI64Store8, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "I64Store16", + auxType: auxInt64, + argLen: 3, + addrSinkArg0: true, + asm: wasm.AI64Store16, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "I64Store32", + auxType: auxInt64, + argLen: 3, + addrSinkArg0: true, + asm: wasm.AI64Store32, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "I64Store", + auxType: auxInt64, + argLen: 3, + addrSinkArg0: true, + asm: wasm.AI64Store, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "F32Load", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + asm: wasm.AF32Load, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64Load", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + asm: wasm.AF64Load, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F32Store", + auxType: auxInt64, + argLen: 3, + addrSinkArg0: true, + asm: wasm.AF32Store, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "F64Store", + auxType: auxInt64, + argLen: 3, + addrSinkArg0: true, + asm: wasm.AF64Store, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "I64Const", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Const", + auxType: auxFloat32, + argLen: 0, + rematerializeable: true, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64Const", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + earlyOk: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "V128Load", + auxType: auxInt64, + argLen: 2, + addrSinkArg0: true, + asm: wasm.AV128Load, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "V128Store", + auxType: auxInt64, + argLen: 3, + addrSinkArg0: true, + asm: wasm.AV128Store, + reg: regInfo{ + inputs: []inputInfo{ + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "V128Zero", + argLen: 0, + asm: wasm.AV128Const, + reg: regInfo{ + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64Eqz", + argLen: 1, + earlyOk: true, + asm: wasm.AI64Eqz, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Eq", + argLen: 2, + earlyOk: true, + asm: wasm.AI64Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Ne", + argLen: 2, + earlyOk: true, + asm: wasm.AI64Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64LtS", + argLen: 2, + earlyOk: true, + asm: wasm.AI64LtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64LtU", + argLen: 2, + earlyOk: true, + asm: wasm.AI64LtU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64GtS", + argLen: 2, + earlyOk: true, + asm: wasm.AI64GtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64GtU", + argLen: 2, + earlyOk: true, + asm: wasm.AI64GtU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64LeS", + argLen: 2, + earlyOk: true, + asm: wasm.AI64LeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64LeU", + argLen: 2, + earlyOk: true, + asm: wasm.AI64LeU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64GeS", + argLen: 2, + earlyOk: true, + asm: wasm.AI64GeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64GeU", + argLen: 2, + earlyOk: true, + asm: wasm.AI64GeU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Eq", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Ne", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Lt", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Lt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Gt", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Gt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Le", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Le, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Ge", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Ge, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Eq", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Ne", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Lt", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Lt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Gt", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Gt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Le", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Le, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Ge", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Ge, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Add", + argLen: 2, + earlyOk: true, + asm: wasm.AI64Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64AddConst", + auxType: auxInt64, + argLen: 1, + earlyOk: true, + asm: wasm.AI64Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Sub", + argLen: 2, + earlyOk: true, + asm: wasm.AI64Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Mul", + argLen: 2, + earlyOk: true, + asm: wasm.AI64Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64DivS", + argLen: 2, + asm: wasm.AI64DivS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64DivU", + argLen: 2, + asm: wasm.AI64DivU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64RemS", + argLen: 2, + asm: wasm.AI64RemS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64RemU", + argLen: 2, + asm: wasm.AI64RemU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64And", + argLen: 2, + earlyOk: true, + asm: wasm.AI64And, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Or", + argLen: 2, + earlyOk: true, + asm: wasm.AI64Or, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Xor", + argLen: 2, + earlyOk: true, + asm: wasm.AI64Xor, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Shl", + argLen: 2, + earlyOk: true, + asm: wasm.AI64Shl, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64ShrS", + argLen: 2, + earlyOk: true, + asm: wasm.AI64ShrS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64ShrU", + argLen: 2, + earlyOk: true, + asm: wasm.AI64ShrU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Neg", + argLen: 1, + earlyOk: true, + asm: wasm.AF32Neg, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Add", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Sub", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Mul", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Div", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Div, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64Neg", + argLen: 1, + earlyOk: true, + asm: wasm.AF64Neg, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Add", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Sub", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Mul", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Div", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Div, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "I64TruncSatF64S", + argLen: 1, + earlyOk: true, + asm: wasm.AI64TruncSatF64S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64TruncSatF64U", + argLen: 1, + earlyOk: true, + asm: wasm.AI64TruncSatF64U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64TruncSatF32S", + argLen: 1, + earlyOk: true, + asm: wasm.AI64TruncSatF32S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64TruncSatF32U", + argLen: 1, + earlyOk: true, + asm: wasm.AI64TruncSatF32U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32ConvertI64S", + argLen: 1, + earlyOk: true, + asm: wasm.AF32ConvertI64S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32ConvertI64U", + argLen: 1, + earlyOk: true, + asm: wasm.AF32ConvertI64U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64ConvertI64S", + argLen: 1, + earlyOk: true, + asm: wasm.AF64ConvertI64S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64ConvertI64U", + argLen: 1, + earlyOk: true, + asm: wasm.AF64ConvertI64U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F32DemoteF64", + argLen: 1, + earlyOk: true, + asm: wasm.AF32DemoteF64, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64PromoteF32", + argLen: 1, + earlyOk: true, + asm: wasm.AF64PromoteF32, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "I64Extend8S", + argLen: 1, + earlyOk: true, + asm: wasm.AI64Extend8S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Extend16S", + argLen: 1, + earlyOk: true, + asm: wasm.AI64Extend16S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Extend32S", + argLen: 1, + earlyOk: true, + asm: wasm.AI64Extend32S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Sqrt", + argLen: 1, + earlyOk: true, + asm: wasm.AF32Sqrt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Trunc", + argLen: 1, + earlyOk: true, + asm: wasm.AF32Trunc, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Ceil", + argLen: 1, + earlyOk: true, + asm: wasm.AF32Ceil, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Floor", + argLen: 1, + earlyOk: true, + asm: wasm.AF32Floor, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Nearest", + argLen: 1, + earlyOk: true, + asm: wasm.AF32Nearest, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Abs", + argLen: 1, + earlyOk: true, + asm: wasm.AF32Abs, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Copysign", + argLen: 2, + earlyOk: true, + asm: wasm.AF32Copysign, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64Sqrt", + argLen: 1, + earlyOk: true, + asm: wasm.AF64Sqrt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Trunc", + argLen: 1, + earlyOk: true, + asm: wasm.AF64Trunc, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Ceil", + argLen: 1, + earlyOk: true, + asm: wasm.AF64Ceil, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Floor", + argLen: 1, + earlyOk: true, + asm: wasm.AF64Floor, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Nearest", + argLen: 1, + earlyOk: true, + asm: wasm.AF64Nearest, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Abs", + argLen: 1, + earlyOk: true, + asm: wasm.AF64Abs, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Copysign", + argLen: 2, + earlyOk: true, + asm: wasm.AF64Copysign, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "I64Ctz", + argLen: 1, + earlyOk: true, + asm: wasm.AI64Ctz, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Clz", + argLen: 1, + earlyOk: true, + asm: wasm.AI64Clz, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I32Rotl", + argLen: 2, + earlyOk: true, + asm: wasm.AI32Rotl, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Rotl", + argLen: 2, + earlyOk: true, + asm: wasm.AI64Rotl, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Popcnt", + argLen: 1, + earlyOk: true, + asm: wasm.AI64Popcnt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I8x16AllTrue", + argLen: 1, + asm: wasm.AI8x16AllTrue, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "V128AnyTrue", + argLen: 1, + asm: wasm.AV128AnyTrue, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8AllTrue", + argLen: 1, + asm: wasm.AI16x8AllTrue, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8Q15MulrSatS", + argLen: 2, + asm: wasm.AI16x8Q15MulrSatS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8RelaxedQ15MulrS", + argLen: 2, + asm: wasm.AI16x8RelaxedQ15MulrS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4AllTrue", + argLen: 1, + asm: wasm.AI32x4AllTrue, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Pmax", + argLen: 2, + commutative: true, + asm: wasm.AF32x4Pmax, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Pmin", + argLen: 2, + commutative: true, + asm: wasm.AF32x4Pmin, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4RelaxedMax", + argLen: 2, + commutative: true, + asm: wasm.AF32x4RelaxedMax, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4RelaxedMin", + argLen: 2, + commutative: true, + asm: wasm.AF32x4RelaxedMin, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2AllTrue", + argLen: 1, + asm: wasm.AI64x2AllTrue, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Pmax", + argLen: 2, + commutative: true, + asm: wasm.AF64x2Pmax, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Pmin", + argLen: 2, + commutative: true, + asm: wasm.AF64x2Pmin, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2RelaxedMax", + argLen: 2, + commutative: true, + asm: wasm.AF64x2RelaxedMax, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2RelaxedMin", + argLen: 2, + commutative: true, + asm: wasm.AF64x2RelaxedMin, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16Abs", + argLen: 1, + asm: wasm.AI8x16Abs, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8Abs", + argLen: 1, + asm: wasm.AI16x8Abs, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4Abs", + argLen: 1, + asm: wasm.AI32x4Abs, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Abs", + argLen: 1, + asm: wasm.AF32x4Abs, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2Abs", + argLen: 1, + asm: wasm.AI64x2Abs, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Abs", + argLen: 1, + asm: wasm.AF64x2Abs, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16Add", + argLen: 2, + commutative: true, + asm: wasm.AI8x16Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8Add", + argLen: 2, + commutative: true, + asm: wasm.AI16x8Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4Add", + argLen: 2, + commutative: true, + asm: wasm.AI32x4Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Add", + argLen: 2, + commutative: true, + asm: wasm.AF32x4Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2Add", + argLen: 2, + commutative: true, + asm: wasm.AI64x2Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Add", + argLen: 2, + commutative: true, + asm: wasm.AF64x2Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16AddSatS", + argLen: 2, + commutative: true, + asm: wasm.AI8x16AddSatS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16AddSatU", + argLen: 2, + commutative: true, + asm: wasm.AI8x16AddSatU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8AddSatS", + argLen: 2, + commutative: true, + asm: wasm.AI16x8AddSatS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8AddSatU", + argLen: 2, + commutative: true, + asm: wasm.AI16x8AddSatU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "V128And", + argLen: 2, + commutative: true, + asm: wasm.AV128And, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "V128Andnot", + argLen: 2, + asm: wasm.AV128Andnot, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16AvgrU", + argLen: 2, + commutative: true, + asm: wasm.AI8x16AvgrU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8AvgrU", + argLen: 2, + commutative: true, + asm: wasm.AI16x8AvgrU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "V128Bitselect", + argLen: 3, + asm: wasm.AV128Bitselect, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {2, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16Splat", + argLen: 1, + asm: wasm.AI8x16Splat, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8Splat", + argLen: 1, + asm: wasm.AI16x8Splat, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4Splat", + argLen: 1, + asm: wasm.AI32x4Splat, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Splat", + argLen: 1, + asm: wasm.AF32x4Splat, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2Splat", + argLen: 1, + asm: wasm.AI64x2Splat, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Splat", + argLen: 1, + asm: wasm.AF64x2Splat, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Ceil", + argLen: 1, + asm: wasm.AF32x4Ceil, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Ceil", + argLen: 1, + asm: wasm.AF64x2Ceil, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2ConvertLowI32x4S", + argLen: 1, + asm: wasm.AF64x2ConvertLowI32x4S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2ConvertLowI32x4U", + argLen: 1, + asm: wasm.AF64x2ConvertLowI32x4U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4ConvertI32x4S", + argLen: 1, + asm: wasm.AF32x4ConvertI32x4S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4ConvertI32x4U", + argLen: 1, + asm: wasm.AF32x4ConvertI32x4U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4TruncSatF32x4S", + argLen: 1, + asm: wasm.AI32x4TruncSatF32x4S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4TruncSatF32x4U", + argLen: 1, + asm: wasm.AI32x4TruncSatF32x4U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Div", + argLen: 2, + asm: wasm.AF32x4Div, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Div", + argLen: 2, + asm: wasm.AF64x2Div, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16Eq", + argLen: 2, + commutative: true, + asm: wasm.AI8x16Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8Eq", + argLen: 2, + commutative: true, + asm: wasm.AI16x8Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4Eq", + argLen: 2, + commutative: true, + asm: wasm.AI32x4Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Eq", + argLen: 2, + commutative: true, + asm: wasm.AF32x4Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2Eq", + argLen: 2, + commutative: true, + asm: wasm.AI64x2Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Eq", + argLen: 2, + commutative: true, + asm: wasm.AF64x2Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ExtendHighI32x4S", + argLen: 1, + asm: wasm.AI64x2ExtendHighI32x4S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ExtendHighI32x4U", + argLen: 1, + asm: wasm.AI64x2ExtendHighI32x4U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ExtendHighI16x8S", + argLen: 1, + asm: wasm.AI32x4ExtendHighI16x8S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ExtendHighI16x8U", + argLen: 1, + asm: wasm.AI32x4ExtendHighI16x8U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ExtendHighI8x16S", + argLen: 1, + asm: wasm.AI16x8ExtendHighI8x16S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ExtendHighI8x16U", + argLen: 1, + asm: wasm.AI16x8ExtendHighI8x16U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ExtendLowI32x4S", + argLen: 1, + asm: wasm.AI64x2ExtendLowI32x4S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ExtendLowI32x4U", + argLen: 1, + asm: wasm.AI64x2ExtendLowI32x4U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ExtendLowI16x8S", + argLen: 1, + asm: wasm.AI32x4ExtendLowI16x8S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ExtendLowI16x8U", + argLen: 1, + asm: wasm.AI32x4ExtendLowI16x8U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ExtendLowI8x16S", + argLen: 1, + asm: wasm.AI16x8ExtendLowI8x16S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ExtendLowI8x16U", + argLen: 1, + asm: wasm.AI16x8ExtendLowI8x16U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Floor", + argLen: 1, + asm: wasm.AF32x4Floor, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Floor", + argLen: 1, + asm: wasm.AF64x2Floor, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16ExtractLaneS", + auxType: auxUInt8, + argLen: 1, + asm: wasm.AI8x16ExtractLaneS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I8x16ExtractLaneU", + auxType: auxUInt8, + argLen: 1, + asm: wasm.AI8x16ExtractLaneU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I16x8ExtractLaneS", + auxType: auxUInt8, + argLen: 1, + asm: wasm.AI16x8ExtractLaneS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I16x8ExtractLaneU", + auxType: auxUInt8, + argLen: 1, + asm: wasm.AI16x8ExtractLaneU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I32x4ExtractLane", + auxType: auxUInt8, + argLen: 1, + asm: wasm.AI32x4ExtractLane, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32x4ExtractLane", + auxType: auxUInt8, + argLen: 1, + asm: wasm.AF32x4ExtractLane, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "I64x2ExtractLane", + auxType: auxUInt8, + argLen: 1, + asm: wasm.AI64x2ExtractLane, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64x2ExtractLane", + auxType: auxUInt8, + argLen: 1, + asm: wasm.AF64x2ExtractLane, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "I8x16GtS", + argLen: 2, + asm: wasm.AI8x16GtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16GtU", + argLen: 2, + asm: wasm.AI8x16GtU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8GtS", + argLen: 2, + asm: wasm.AI16x8GtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8GtU", + argLen: 2, + asm: wasm.AI16x8GtU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4GtS", + argLen: 2, + asm: wasm.AI32x4GtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4GtU", + argLen: 2, + asm: wasm.AI32x4GtU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Gt", + argLen: 2, + asm: wasm.AF32x4Gt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2GtS", + argLen: 2, + asm: wasm.AI64x2GtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Gt", + argLen: 2, + asm: wasm.AF64x2Gt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16GeS", + argLen: 2, + asm: wasm.AI8x16GeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16GeU", + argLen: 2, + asm: wasm.AI8x16GeU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8GeS", + argLen: 2, + asm: wasm.AI16x8GeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8GeU", + argLen: 2, + asm: wasm.AI16x8GeU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4GeS", + argLen: 2, + asm: wasm.AI32x4GeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4GeU", + argLen: 2, + asm: wasm.AI32x4GeU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Ge", + argLen: 2, + asm: wasm.AF32x4Ge, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2GeS", + argLen: 2, + asm: wasm.AI64x2GeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Ge", + argLen: 2, + asm: wasm.AF64x2Ge, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16LtS", + argLen: 2, + asm: wasm.AI8x16LtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16LtU", + argLen: 2, + asm: wasm.AI8x16LtU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8LtS", + argLen: 2, + asm: wasm.AI16x8LtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8LtU", + argLen: 2, + asm: wasm.AI16x8LtU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4LtS", + argLen: 2, + asm: wasm.AI32x4LtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4LtU", + argLen: 2, + asm: wasm.AI32x4LtU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Lt", + argLen: 2, + asm: wasm.AF32x4Lt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2LtS", + argLen: 2, + asm: wasm.AI64x2LtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Lt", + argLen: 2, + asm: wasm.AF64x2Lt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16LeS", + argLen: 2, + asm: wasm.AI8x16LeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16LeU", + argLen: 2, + asm: wasm.AI8x16LeU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8LeS", + argLen: 2, + asm: wasm.AI16x8LeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8LeU", + argLen: 2, + asm: wasm.AI16x8LeU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4LeS", + argLen: 2, + asm: wasm.AI32x4LeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4LeU", + argLen: 2, + asm: wasm.AI32x4LeU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Le", + argLen: 2, + asm: wasm.AF32x4Le, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2LeS", + argLen: 2, + asm: wasm.AI64x2LeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Le", + argLen: 2, + asm: wasm.AF64x2Le, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16Swizzle", + argLen: 2, + asm: wasm.AI8x16Swizzle, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16MaxS", + argLen: 2, + commutative: true, + asm: wasm.AI8x16MaxS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16MaxU", + argLen: 2, + commutative: true, + asm: wasm.AI8x16MaxU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8MaxS", + argLen: 2, + commutative: true, + asm: wasm.AI16x8MaxS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8MaxU", + argLen: 2, + commutative: true, + asm: wasm.AI16x8MaxU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4MaxS", + argLen: 2, + commutative: true, + asm: wasm.AI32x4MaxS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4MaxU", + argLen: 2, + commutative: true, + asm: wasm.AI32x4MaxU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Max", + argLen: 2, + commutative: true, + asm: wasm.AF32x4Max, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Max", + argLen: 2, + commutative: true, + asm: wasm.AF64x2Max, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16MinS", + argLen: 2, + commutative: true, + asm: wasm.AI8x16MinS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16MinU", + argLen: 2, + commutative: true, + asm: wasm.AI8x16MinU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8MinS", + argLen: 2, + commutative: true, + asm: wasm.AI16x8MinS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8MinU", + argLen: 2, + commutative: true, + asm: wasm.AI16x8MinU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4MinS", + argLen: 2, + commutative: true, + asm: wasm.AI32x4MinS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4MinU", + argLen: 2, + commutative: true, + asm: wasm.AI32x4MinU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Min", + argLen: 2, + commutative: true, + asm: wasm.AF32x4Min, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Min", + argLen: 2, + commutative: true, + asm: wasm.AF64x2Min, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8Mul", + argLen: 2, + commutative: true, + asm: wasm.AI16x8Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4Mul", + argLen: 2, + commutative: true, + asm: wasm.AI32x4Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Mul", + argLen: 2, + commutative: true, + asm: wasm.AF32x4Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2Mul", + argLen: 2, + commutative: true, + asm: wasm.AI64x2Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Mul", + argLen: 2, + commutative: true, + asm: wasm.AF64x2Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ExtmulHighI8x16S", + argLen: 2, + commutative: true, + asm: wasm.AI16x8ExtmulHighI8x16S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ExtmulHighI8x16U", + argLen: 2, + commutative: true, + asm: wasm.AI16x8ExtmulHighI8x16U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ExtmulHighI16x8S", + argLen: 2, + commutative: true, + asm: wasm.AI32x4ExtmulHighI16x8S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ExtmulHighI16x8U", + argLen: 2, + commutative: true, + asm: wasm.AI32x4ExtmulHighI16x8U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ExtmulHighI32x4S", + argLen: 2, + commutative: true, + asm: wasm.AI64x2ExtmulHighI32x4S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ExtmulHighI32x4U", + argLen: 2, + commutative: true, + asm: wasm.AI64x2ExtmulHighI32x4U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ExtmulLowI8x16S", + argLen: 2, + commutative: true, + asm: wasm.AI16x8ExtmulLowI8x16S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ExtmulLowI8x16U", + argLen: 2, + commutative: true, + asm: wasm.AI16x8ExtmulLowI8x16U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ExtmulLowI16x8S", + argLen: 2, + commutative: true, + asm: wasm.AI32x4ExtmulLowI16x8S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ExtmulLowI16x8U", + argLen: 2, + commutative: true, + asm: wasm.AI32x4ExtmulLowI16x8U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ExtmulLowI32x4S", + argLen: 2, + commutative: true, + asm: wasm.AI64x2ExtmulLowI32x4S, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ExtmulLowI32x4U", + argLen: 2, + commutative: true, + asm: wasm.AI64x2ExtmulLowI32x4U, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16Neg", + argLen: 1, + asm: wasm.AI8x16Neg, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8Neg", + argLen: 1, + asm: wasm.AI16x8Neg, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4Neg", + argLen: 1, + asm: wasm.AI32x4Neg, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Neg", + argLen: 1, + asm: wasm.AF32x4Neg, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2Neg", + argLen: 1, + asm: wasm.AI64x2Neg, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Neg", + argLen: 1, + asm: wasm.AF64x2Neg, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "V128Not", + argLen: 1, + asm: wasm.AV128Not, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16Ne", + argLen: 2, + commutative: true, + asm: wasm.AI8x16Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8Ne", + argLen: 2, + commutative: true, + asm: wasm.AI16x8Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4Ne", + argLen: 2, + commutative: true, + asm: wasm.AI32x4Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Ne", + argLen: 2, + commutative: true, + asm: wasm.AF32x4Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2Ne", + argLen: 2, + commutative: true, + asm: wasm.AI64x2Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Ne", + argLen: 2, + commutative: true, + asm: wasm.AF64x2Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16Popcnt", + argLen: 1, + asm: wasm.AI8x16Popcnt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "V128Or", + argLen: 2, + commutative: true, + asm: wasm.AV128Or, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Nearest", + argLen: 1, + asm: wasm.AF32x4Nearest, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Nearest", + argLen: 1, + asm: wasm.AF64x2Nearest, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16ReplaceLane", + auxType: auxUInt8, + argLen: 2, + asm: wasm.AI8x16ReplaceLane, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ReplaceLane", + auxType: auxUInt8, + argLen: 2, + asm: wasm.AI16x8ReplaceLane, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ReplaceLane", + auxType: auxUInt8, + argLen: 2, + asm: wasm.AI32x4ReplaceLane, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4ReplaceLane", + auxType: auxUInt8, + argLen: 2, + asm: wasm.AF32x4ReplaceLane, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ReplaceLane", + auxType: auxUInt8, + argLen: 2, + asm: wasm.AI64x2ReplaceLane, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2ReplaceLane", + auxType: auxUInt8, + argLen: 2, + asm: wasm.AF64x2ReplaceLane, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16Shl", + argLen: 2, + asm: wasm.AI8x16Shl, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8Shl", + argLen: 2, + asm: wasm.AI16x8Shl, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4Shl", + argLen: 2, + asm: wasm.AI32x4Shl, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2Shl", + argLen: 2, + asm: wasm.AI64x2Shl, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16ShrS", + argLen: 2, + asm: wasm.AI8x16ShrS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16ShrU", + argLen: 2, + asm: wasm.AI8x16ShrU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ShrS", + argLen: 2, + asm: wasm.AI16x8ShrS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8ShrU", + argLen: 2, + asm: wasm.AI16x8ShrU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ShrS", + argLen: 2, + asm: wasm.AI32x4ShrS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4ShrU", + argLen: 2, + asm: wasm.AI32x4ShrU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ShrS", + argLen: 2, + asm: wasm.AI64x2ShrS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2ShrU", + argLen: 2, + asm: wasm.AI64x2ShrU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Sqrt", + argLen: 1, + asm: wasm.AF32x4Sqrt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Sqrt", + argLen: 1, + asm: wasm.AF64x2Sqrt, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16Sub", + argLen: 2, + asm: wasm.AI8x16Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8Sub", + argLen: 2, + asm: wasm.AI16x8Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I32x4Sub", + argLen: 2, + asm: wasm.AI32x4Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Sub", + argLen: 2, + asm: wasm.AF32x4Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I64x2Sub", + argLen: 2, + asm: wasm.AI64x2Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Sub", + argLen: 2, + asm: wasm.AF64x2Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16SubSatS", + argLen: 2, + asm: wasm.AI8x16SubSatS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I8x16SubSatU", + argLen: 2, + asm: wasm.AI8x16SubSatU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8SubSatS", + argLen: 2, + asm: wasm.AI16x8SubSatS, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "I16x8SubSatU", + argLen: 2, + asm: wasm.AI16x8SubSatU, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F32x4Trunc", + argLen: 1, + asm: wasm.AF32x4Trunc, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "F64x2Trunc", + argLen: 1, + asm: wasm.AF64x2Trunc, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + { + name: "V128Xor", + argLen: 2, + commutative: true, + asm: wasm.AV128Xor, + reg: regInfo{ + inputs: []inputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + {1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + outputs: []outputInfo{ + {0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 + }, + }, + }, + + { + name: "Last", + argLen: -1, + generic: true, + }, + { + name: "Add8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddPtr", + argLen: 2, + generic: true, + }, + { + name: "Add32F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add64F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Sub8", + argLen: 2, + generic: true, + }, + { + name: "Sub16", + argLen: 2, + generic: true, + }, + { + name: "Sub32", + argLen: 2, + generic: true, + }, + { + name: "Sub64", + argLen: 2, + generic: true, + }, + { + name: "SubPtr", + argLen: 2, + generic: true, + }, + { + name: "Sub32F", + argLen: 2, + generic: true, + }, + { + name: "Sub64F", + argLen: 2, + generic: true, + }, + { + name: "Mul8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul32F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul64F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Div32F", + argLen: 2, + generic: true, + }, + { + name: "Div64F", + argLen: 2, + generic: true, + }, + { + name: "Hmul32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Hmul32u", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Hmul64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Hmul64u", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul32uhilo", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul64uhilo", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul32uover", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul64uover", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Avg32u", + argLen: 2, + generic: true, + }, + { + name: "Avg64u", + argLen: 2, + generic: true, + }, + { + name: "Div8", + argLen: 2, + generic: true, + }, + { + name: "Div8u", + argLen: 2, + generic: true, + }, + { + name: "Div16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Div16u", + argLen: 2, + generic: true, + }, + { + name: "Div32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Div32u", + argLen: 2, + generic: true, + }, + { + name: "Div64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Div64u", + argLen: 2, + generic: true, + }, + { + name: "Div128u", + argLen: 3, + generic: true, + }, + { + name: "Mod8", + argLen: 2, + generic: true, + }, + { + name: "Mod8u", + argLen: 2, + generic: true, + }, + { + name: "Mod16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Mod16u", + argLen: 2, + generic: true, + }, + { + name: "Mod32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Mod32u", + argLen: 2, + generic: true, + }, + { + name: "Mod64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Mod64u", + argLen: 2, + generic: true, + }, + { + name: "And8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "And16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "And32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "And64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Lsh8x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh8x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh8x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh8x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh16x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh16x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh16x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh16x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh32x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh32x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh32x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh32x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh64x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh64x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh64x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh64x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Eq8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqPtr", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqInter", + argLen: 2, + generic: true, + }, + { + name: "EqSlice", + argLen: 2, + generic: true, + }, + { + name: "Eq32F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq64F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NeqPtr", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NeqInter", + argLen: 2, + generic: true, + }, + { + name: "NeqSlice", + argLen: 2, + generic: true, + }, + { + name: "Neq32F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq64F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Less8", + argLen: 2, + generic: true, + }, + { + name: "Less8U", + argLen: 2, + generic: true, + }, + { + name: "Less16", + argLen: 2, + generic: true, + }, + { + name: "Less16U", + argLen: 2, + generic: true, + }, + { + name: "Less32", + argLen: 2, + generic: true, + }, + { + name: "Less32U", + argLen: 2, + generic: true, + }, + { + name: "Less64", + argLen: 2, + generic: true, + }, + { + name: "Less64U", + argLen: 2, + generic: true, + }, + { + name: "Less32F", + argLen: 2, + generic: true, + }, + { + name: "Less64F", + argLen: 2, + generic: true, + }, + { + name: "Leq8", + argLen: 2, + generic: true, + }, + { + name: "Leq8U", + argLen: 2, + generic: true, + }, + { + name: "Leq16", + argLen: 2, + generic: true, + }, + { + name: "Leq16U", + argLen: 2, + generic: true, + }, + { + name: "Leq32", + argLen: 2, + generic: true, + }, + { + name: "Leq32U", + argLen: 2, + generic: true, + }, + { + name: "Leq64", + argLen: 2, + generic: true, + }, + { + name: "Leq64U", + argLen: 2, + generic: true, + }, + { + name: "Leq32F", + argLen: 2, + generic: true, + }, + { + name: "Leq64F", + argLen: 2, + generic: true, + }, + { + name: "CondSelect", + argLen: 3, + generic: true, + }, + { + name: "AndB", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrB", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqB", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NeqB", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Not", + argLen: 1, + generic: true, + }, + { + name: "Neg8", + argLen: 1, + generic: true, + }, + { + name: "Neg16", + argLen: 1, + generic: true, + }, + { + name: "Neg32", + argLen: 1, + generic: true, + }, + { + name: "Neg64", + argLen: 1, + generic: true, + }, + { + name: "Neg32F", + argLen: 1, + generic: true, + }, + { + name: "Neg64F", + argLen: 1, + generic: true, + }, + { + name: "Com8", + argLen: 1, + generic: true, + }, + { + name: "Com16", + argLen: 1, + generic: true, + }, + { + name: "Com32", + argLen: 1, + generic: true, + }, + { + name: "Com64", + argLen: 1, + generic: true, + }, + { + name: "Ctz8", + argLen: 1, + generic: true, + }, + { + name: "Ctz16", + argLen: 1, + generic: true, + }, + { + name: "Ctz32", + argLen: 1, + generic: true, + }, + { + name: "Ctz64", + argLen: 1, + generic: true, + }, + { + name: "Ctz64On32", + argLen: 2, + generic: true, + }, + { + name: "Ctz8NonZero", + argLen: 1, + generic: true, + }, + { + name: "Ctz16NonZero", + argLen: 1, + generic: true, + }, + { + name: "Ctz32NonZero", + argLen: 1, + generic: true, + }, + { + name: "Ctz64NonZero", + argLen: 1, + generic: true, + }, + { + name: "BitLen8", + argLen: 1, + generic: true, + }, + { + name: "BitLen16", + argLen: 1, + generic: true, + }, + { + name: "BitLen32", + argLen: 1, + generic: true, + }, + { + name: "BitLen64", + argLen: 1, + generic: true, + }, + { + name: "Bswap16", + argLen: 1, + generic: true, + }, + { + name: "Bswap32", + argLen: 1, + generic: true, + }, + { + name: "Bswap64", + argLen: 1, + generic: true, + }, + { + name: "BitRev8", + argLen: 1, + generic: true, + }, + { + name: "BitRev16", + argLen: 1, + generic: true, + }, + { + name: "BitRev32", + argLen: 1, + generic: true, + }, + { + name: "BitRev64", + argLen: 1, + generic: true, + }, + { + name: "PopCount8", + argLen: 1, + generic: true, + }, + { + name: "PopCount16", + argLen: 1, + generic: true, + }, + { + name: "PopCount32", + argLen: 1, + generic: true, + }, + { + name: "PopCount64", + argLen: 1, + generic: true, + }, + { + name: "RotateLeft64", + argLen: 2, + generic: true, + }, + { + name: "RotateLeft32", + argLen: 2, + generic: true, + }, + { + name: "RotateLeft16", + argLen: 2, + generic: true, + }, + { + name: "RotateLeft8", + argLen: 2, + generic: true, + }, + { + name: "Sqrt", + argLen: 1, + generic: true, + }, + { + name: "Sqrt32", + argLen: 1, + generic: true, + }, + { + name: "Floor", + argLen: 1, + generic: true, + }, + { + name: "Ceil", + argLen: 1, + generic: true, + }, + { + name: "Trunc", + argLen: 1, + generic: true, + }, + { + name: "Round", + argLen: 1, + generic: true, + }, + { + name: "RoundToEven", + argLen: 1, + generic: true, + }, + { + name: "Abs", + argLen: 1, + generic: true, + }, + { + name: "Copysign", + argLen: 2, + generic: true, + }, + { + name: "Min64", + argLen: 2, + generic: true, + }, + { + name: "Max64", + argLen: 2, + generic: true, + }, + { + name: "Min64u", + argLen: 2, + generic: true, + }, + { + name: "Max64u", + argLen: 2, + generic: true, + }, + { + name: "Min64F", + argLen: 2, + generic: true, + }, + { + name: "Min32F", + argLen: 2, + generic: true, + }, + { + name: "Max64F", + argLen: 2, + generic: true, + }, + { + name: "Max32F", + argLen: 2, + generic: true, + }, + { + name: "FMA", + argLen: 3, + generic: true, + }, + { + name: "Phi", + argLen: -1, + zeroWidth: true, + generic: true, + }, + { + name: "Copy", + argLen: 1, + generic: true, + }, + { + name: "Convert", + argLen: 2, + resultInArg0: true, + zeroWidth: true, + generic: true, + }, + { + name: "ConstBool", + auxType: auxBool, + argLen: 0, + generic: true, + }, + { + name: "ConstString", + auxType: auxString, + argLen: 0, + generic: true, + }, + { + name: "ConstNil", + argLen: 0, + generic: true, + }, + { + name: "Const8", + auxType: auxInt8, + argLen: 0, + generic: true, + }, + { + name: "Const16", + auxType: auxInt16, + argLen: 0, + generic: true, + }, + { + name: "Const32", + auxType: auxInt32, + argLen: 0, + generic: true, + }, + { + name: "Const64", + auxType: auxInt64, + argLen: 0, + generic: true, + }, + { + name: "Const32F", + auxType: auxFloat32, + argLen: 0, + generic: true, + }, + { + name: "Const64F", + auxType: auxFloat64, + argLen: 0, + generic: true, + }, + { + name: "ConstInterface", + argLen: 0, + generic: true, + }, + { + name: "ConstSlice", + argLen: 0, + generic: true, + }, + { + name: "InitMem", + argLen: 0, + zeroWidth: true, + generic: true, + }, + { + name: "Arg", + auxType: auxSymOff, + argLen: 0, + zeroWidth: true, + symEffect: SymRead, + generic: true, + }, + { + name: "ArgIntReg", + auxType: auxNameOffsetInt8, + argLen: 0, + zeroWidth: true, + generic: true, + }, + { + name: "ArgFloatReg", + auxType: auxNameOffsetInt8, + argLen: 0, + zeroWidth: true, + generic: true, + }, + { + name: "Addr", + auxType: auxSym, + argLen: 1, + symEffect: SymAddr, + generic: true, + }, + { + name: "LocalAddr", + auxType: auxSym, + argLen: 2, + symEffect: SymAddr, + generic: true, + }, + { + name: "SP", + argLen: 0, + zeroWidth: true, + fixedReg: true, + generic: true, + }, + { + name: "SB", + argLen: 0, + zeroWidth: true, + fixedReg: true, + generic: true, + }, + { + name: "SPanchored", + argLen: 2, + zeroWidth: true, + generic: true, + }, + { + name: "Load", + argLen: 2, + generic: true, + }, + { + name: "Dereference", + argLen: 2, + generic: true, + }, + { + name: "Store", + auxType: auxTyp, + argLen: 3, + generic: true, + }, + { + name: "LoadMasked8", + argLen: 3, + generic: true, + }, + { + name: "LoadMasked16", + argLen: 3, + generic: true, + }, + { + name: "LoadMasked32", + argLen: 3, + generic: true, + }, + { + name: "LoadMasked64", + argLen: 3, + generic: true, + }, + { + name: "StoreMasked8", + auxType: auxTyp, + argLen: 4, + generic: true, + }, + { + name: "StoreMasked16", + auxType: auxTyp, + argLen: 4, + generic: true, + }, + { + name: "StoreMasked32", + auxType: auxTyp, + argLen: 4, + generic: true, + }, + { + name: "StoreMasked64", + auxType: auxTyp, + argLen: 4, + generic: true, + }, + { + name: "Move", + auxType: auxTypSize, + argLen: 3, + generic: true, + }, + { + name: "Zero", + auxType: auxTypSize, + argLen: 2, + generic: true, + }, + { + name: "StoreWB", + auxType: auxTyp, + argLen: 3, + generic: true, + }, + { + name: "MoveWB", + auxType: auxTypSize, + argLen: 3, + generic: true, + }, + { + name: "ZeroWB", + auxType: auxTypSize, + argLen: 2, + generic: true, + }, + { + name: "WBend", + argLen: 1, + generic: true, + }, + { + name: "WB", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "HasCPUFeature", + auxType: auxSym, + argLen: 0, + symEffect: SymNone, + generic: true, + }, + { + name: "PanicBounds", + auxType: auxInt64, + argLen: 3, + call: true, + generic: true, + }, + { + name: "PanicExtend", + auxType: auxInt64, + argLen: 4, + call: true, + generic: true, + }, + { + name: "ClosureCall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "StaticCall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "InterCall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "TailCall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "TailCallInter", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "ClosureLECall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "StaticLECall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "InterLECall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "TailLECall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "TailLECallInter", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "SignExt8to16", + argLen: 1, + generic: true, + }, + { + name: "SignExt8to32", + argLen: 1, + generic: true, + }, + { + name: "SignExt8to64", + argLen: 1, + generic: true, + }, + { + name: "SignExt16to32", + argLen: 1, + generic: true, + }, + { + name: "SignExt16to64", + argLen: 1, + generic: true, + }, + { + name: "SignExt32to64", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt8to16", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt8to32", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt8to64", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt16to32", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt16to64", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt32to64", + argLen: 1, + generic: true, + }, + { + name: "Trunc16to8", + argLen: 1, + generic: true, + }, + { + name: "Trunc32to8", + argLen: 1, + generic: true, + }, + { + name: "Trunc32to16", + argLen: 1, + generic: true, + }, + { + name: "Trunc64to8", + argLen: 1, + generic: true, + }, + { + name: "Trunc64to16", + argLen: 1, + generic: true, + }, + { + name: "Trunc64to32", + argLen: 1, + generic: true, + }, + { + name: "Cvt32to32F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32to64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64to32F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64to64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto32", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto64", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto32", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto64", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto32F", + argLen: 1, + generic: true, + }, + { + name: "CvtBoolToUint8", + argLen: 1, + generic: true, + }, + { + name: "Round32F", + argLen: 1, + generic: true, + }, + { + name: "Round64F", + argLen: 1, + generic: true, + }, + { + name: "IsNonNil", + argLen: 1, + generic: true, + }, + { + name: "IsInBounds", + argLen: 2, + generic: true, + }, + { + name: "IsSliceInBounds", + argLen: 2, + generic: true, + }, + { + name: "NilCheck", + argLen: 2, + nilCheck: true, + generic: true, + }, + { + name: "GetG", + argLen: 1, + zeroWidth: true, + generic: true, + }, + { + name: "GetClosurePtr", + argLen: 0, + generic: true, + }, + { + name: "GetCallerPC", + argLen: 0, + generic: true, + }, + { + name: "GetCallerSP", + argLen: 1, + generic: true, + }, + { + name: "PtrIndex", + argLen: 2, + generic: true, + }, + { + name: "OffPtr", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "SliceMake", + argLen: 3, + generic: true, + }, + { + name: "SlicePtr", + argLen: 1, + generic: true, + }, + { + name: "SliceLen", + argLen: 1, + generic: true, + }, + { + name: "SliceCap", + argLen: 1, + generic: true, + }, + { + name: "SlicePtrUnchecked", + argLen: 1, + generic: true, + }, + { + name: "ComplexMake", + argLen: 2, + generic: true, + }, + { + name: "ComplexReal", + argLen: 1, + generic: true, + }, + { + name: "ComplexImag", + argLen: 1, + generic: true, + }, + { + name: "StringMake", + argLen: 2, + generic: true, + }, + { + name: "StringPtr", + argLen: 1, + generic: true, + }, + { + name: "StringLen", + argLen: 1, + generic: true, + }, + { + name: "IMake", + argLen: 2, + generic: true, + }, + { + name: "ITab", + argLen: 1, + generic: true, + }, + { + name: "IData", + argLen: 1, + generic: true, + }, + { + name: "StructMake", + argLen: -1, + generic: true, + }, + { + name: "StructSelect", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "ArrayMake1", + argLen: 1, + generic: true, + }, + { + name: "ArraySelect", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "StoreReg", + argLen: 1, + generic: true, + }, + { + name: "LoadReg", + argLen: 1, + generic: true, + }, + { + name: "FwdRef", + auxType: auxSym, + argLen: 0, + symEffect: SymNone, + generic: true, + }, + { + name: "Unknown", + argLen: 0, + generic: true, + }, + { + name: "VarDef", + auxType: auxSym, + argLen: 1, + zeroWidth: true, + symEffect: SymNone, + generic: true, + }, + { + name: "VarLive", + auxType: auxSym, + argLen: 1, + zeroWidth: true, + symEffect: SymRead, + generic: true, + }, + { + name: "KeepAlive", + argLen: 2, + zeroWidth: true, + generic: true, + }, + { + name: "InlMark", + auxType: auxInt32, + argLen: 1, + generic: true, + }, + { + name: "Int64Make", + argLen: 2, + generic: true, + }, + { + name: "Int64Hi", + argLen: 1, + generic: true, + }, + { + name: "Int64Lo", + argLen: 1, + generic: true, + }, + { + name: "Add32carry", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add32withcarry", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "Add32carrywithcarry", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "Sub32carry", + argLen: 2, + generic: true, + }, + { + name: "Sub32withcarry", + argLen: 3, + generic: true, + }, + { + name: "Add64carry", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "Sub64borrow", + argLen: 3, + generic: true, + }, + { + name: "Signmask", + argLen: 1, + generic: true, + }, + { + name: "Zeromask", + argLen: 1, + generic: true, + }, + { + name: "Slicemask", + argLen: 1, + generic: true, + }, + { + name: "SpectreIndex", + argLen: 2, + generic: true, + }, + { + name: "SpectreSliceIndex", + argLen: 2, + generic: true, + }, + { + name: "Cvt32Uto32F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Uto64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto32U", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto32U", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Uto32F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Uto64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto64U", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto64U", + argLen: 1, + generic: true, + }, + { + name: "Select0", + argLen: 1, + zeroWidth: true, + generic: true, + }, + { + name: "Select1", + argLen: 1, + zeroWidth: true, + generic: true, + }, + { + name: "MakeTuple", + argLen: 2, + generic: true, + }, + { + name: "SelectN", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "SelectNAddr", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "MakeResult", + argLen: -1, + generic: true, + }, + { + name: "AtomicLoad8", + argLen: 2, + generic: true, + }, + { + name: "AtomicLoad32", + argLen: 2, + generic: true, + }, + { + name: "AtomicLoad64", + argLen: 2, + generic: true, + }, + { + name: "AtomicLoadPtr", + argLen: 2, + generic: true, + }, + { + name: "AtomicLoadAcq32", + argLen: 2, + generic: true, + }, + { + name: "AtomicLoadAcq64", + argLen: 2, + generic: true, + }, + { + name: "AtomicStore8", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStore32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStore64", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStorePtrNoWB", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStoreRel32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStoreRel64", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange8", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange64", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAdd32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAdd64", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicCompareAndSwap32", + argLen: 4, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicCompareAndSwap64", + argLen: 4, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicCompareAndSwapRel32", + argLen: 4, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd8", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr8", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd64value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd32value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd8value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr64value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr32value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr8value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStore8Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStore32Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStore64Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAdd32Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAdd64Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange8Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange32Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange64Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicCompareAndSwap32Variant", + argLen: 4, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicCompareAndSwap64Variant", + argLen: 4, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd64valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr64valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd32valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr32valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd8valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr8valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "PubBarrier", + argLen: 1, + hasSideEffects: true, + generic: true, + }, + { + name: "Clobber", + auxType: auxSymOff, + argLen: 0, + symEffect: SymNone, + generic: true, + }, + { + name: "ClobberReg", + argLen: 0, + generic: true, + }, + { + name: "PrefetchCache", + argLen: 2, + hasSideEffects: true, + generic: true, + }, + { + name: "PrefetchCacheStreamed", + argLen: 2, + hasSideEffects: true, + generic: true, + }, + { + name: "MemEq", + argLen: 4, + commutative: true, + generic: true, + }, + { + name: "Empty", + argLen: 0, + generic: true, + }, + { + name: "ZeroSIMD", + argLen: 0, + generic: true, + }, + { + name: "Cvt16toMask8x16", + argLen: 1, + generic: true, + }, + { + name: "Cvt32toMask8x32", + argLen: 1, + generic: true, + }, + { + name: "Cvt64toMask8x64", + argLen: 1, + generic: true, + }, + { + name: "Cvt8toMask16x8", + argLen: 1, + generic: true, + }, + { + name: "Cvt16toMask16x16", + argLen: 1, + generic: true, + }, + { + name: "Cvt32toMask16x32", + argLen: 1, + generic: true, + }, + { + name: "Cvt8toMask32x4", + argLen: 1, + generic: true, + }, + { + name: "Cvt8toMask32x8", + argLen: 1, + generic: true, + }, + { + name: "Cvt16toMask32x16", + argLen: 1, + generic: true, + }, + { + name: "Cvt8toMask64x2", + argLen: 1, + generic: true, + }, + { + name: "Cvt8toMask64x4", + argLen: 1, + generic: true, + }, + { + name: "Cvt8toMask64x8", + argLen: 1, + generic: true, + }, + { + name: "CvtMask8x16to16", + argLen: 1, + generic: true, + }, + { + name: "CvtMask8x32to32", + argLen: 1, + generic: true, + }, + { + name: "CvtMask8x64to64", + argLen: 1, + generic: true, + }, + { + name: "CvtMask16x8to8", + argLen: 1, + generic: true, + }, + { + name: "CvtMask16x16to16", + argLen: 1, + generic: true, + }, + { + name: "CvtMask16x32to32", + argLen: 1, + generic: true, + }, + { + name: "CvtMask32x4to8", + argLen: 1, + generic: true, + }, + { + name: "CvtMask32x8to8", + argLen: 1, + generic: true, + }, + { + name: "CvtMask32x16to16", + argLen: 1, + generic: true, + }, + { + name: "CvtMask64x2to8", + argLen: 1, + generic: true, + }, + { + name: "CvtMask64x4to8", + argLen: 1, + generic: true, + }, + { + name: "CvtMask64x8to8", + argLen: 1, + generic: true, + }, + { + name: "IsZeroVec", + argLen: 1, + generic: true, + }, + { + name: "IsNaNFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "IsNaNFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "IsNaNFloat32x16", + argLen: 1, + generic: true, + }, + { + name: "IsNaNFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "IsNaNFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "IsNaNFloat64x8", + argLen: 1, + generic: true, + }, + { + name: "AESDecryptLastRoundUint8x16", + argLen: 2, + generic: true, + }, + { + name: "AESDecryptLastRoundUint8x32", + argLen: 2, + generic: true, + }, + { + name: "AESDecryptLastRoundUint8x64", + argLen: 2, + generic: true, + }, + { + name: "AESDecryptOneRoundUint8x16", + argLen: 2, + generic: true, + }, + { + name: "AESDecryptOneRoundUint8x32", + argLen: 2, + generic: true, + }, + { + name: "AESDecryptOneRoundUint8x64", + argLen: 2, + generic: true, + }, + { + name: "AESEncryptLastRoundUint8x16", + argLen: 2, + generic: true, + }, + { + name: "AESEncryptLastRoundUint8x32", + argLen: 2, + generic: true, + }, + { + name: "AESEncryptLastRoundUint8x64", + argLen: 2, + generic: true, + }, + { + name: "AESEncryptOneRoundUint8x16", + argLen: 2, + generic: true, + }, + { + name: "AESEncryptOneRoundUint8x32", + argLen: 2, + generic: true, + }, + { + name: "AESEncryptOneRoundUint8x64", + argLen: 2, + generic: true, + }, + { + name: "AESInvMixColumnsUint32x4", + argLen: 1, + generic: true, + }, + { + name: "AbsFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "AbsFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "AbsInt8x16", + argLen: 1, + generic: true, + }, + { + name: "AbsInt8x32", + argLen: 1, + generic: true, + }, + { + name: "AbsInt8x64", + argLen: 1, + generic: true, + }, + { + name: "AbsInt16x8", + argLen: 1, + generic: true, + }, + { + name: "AbsInt16x16", + argLen: 1, + generic: true, + }, + { + name: "AbsInt16x32", + argLen: 1, + generic: true, + }, + { + name: "AbsInt32x4", + argLen: 1, + generic: true, + }, + { + name: "AbsInt32x8", + argLen: 1, + generic: true, + }, + { + name: "AbsInt32x16", + argLen: 1, + generic: true, + }, + { + name: "AbsInt64x2", + argLen: 1, + generic: true, + }, + { + name: "AbsInt64x4", + argLen: 1, + generic: true, + }, + { + name: "AbsInt64x8", + argLen: 1, + generic: true, + }, + { + name: "AddFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddOddSubEvenFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "AddOddSubEvenFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "AddOddSubEvenFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "AddOddSubEvenFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "AddSaturatedInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedUint8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedUint8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSaturatedUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt8x16", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt8x32", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt8x64", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt16x8", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt16x16", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt16x32", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt32x4", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt32x8", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt32x16", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt64x2", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt64x4", + argLen: 2, + generic: true, + }, + { + name: "AndNotInt64x8", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint8x16", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint8x32", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint8x64", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint16x8", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint16x16", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint16x32", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint32x4", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint32x8", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint32x16", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint64x2", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint64x4", + argLen: 2, + generic: true, + }, + { + name: "AndNotUint64x8", + argLen: 2, + generic: true, + }, + { + name: "AndUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageUint8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageUint8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "BitSelectInt8x16", + argLen: 3, + generic: true, + }, + { + name: "BitSelectInt16x8", + argLen: 3, + generic: true, + }, + { + name: "BitSelectInt32x4", + argLen: 3, + generic: true, + }, + { + name: "BitSelectInt64x2", + argLen: 3, + generic: true, + }, + { + name: "BitSelectUint8x16", + argLen: 3, + generic: true, + }, + { + name: "BitSelectUint16x8", + argLen: 3, + generic: true, + }, + { + name: "BitSelectUint32x4", + argLen: 3, + generic: true, + }, + { + name: "BitSelectUint64x2", + argLen: 3, + generic: true, + }, + { + name: "BroadcastFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "BroadcastFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "BroadcastInt8x16", + argLen: 1, + generic: true, + }, + { + name: "BroadcastInt16x8", + argLen: 1, + generic: true, + }, + { + name: "BroadcastInt32x4", + argLen: 1, + generic: true, + }, + { + name: "BroadcastInt64x2", + argLen: 1, + generic: true, + }, + { + name: "CeilFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "CeilFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "CeilFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "CeilFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "CompressFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "CompressFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "CompressFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "CompressFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "CompressFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "CompressFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "CompressInt8x16", + argLen: 2, + generic: true, + }, + { + name: "CompressInt8x32", + argLen: 2, + generic: true, + }, + { + name: "CompressInt8x64", + argLen: 2, + generic: true, + }, + { + name: "CompressInt16x8", + argLen: 2, + generic: true, + }, + { + name: "CompressInt16x16", + argLen: 2, + generic: true, + }, + { + name: "CompressInt16x32", + argLen: 2, + generic: true, + }, + { + name: "CompressInt32x4", + argLen: 2, + generic: true, + }, + { + name: "CompressInt32x8", + argLen: 2, + generic: true, + }, + { + name: "CompressInt32x16", + argLen: 2, + generic: true, + }, + { + name: "CompressInt64x2", + argLen: 2, + generic: true, + }, + { + name: "CompressInt64x4", + argLen: 2, + generic: true, + }, + { + name: "CompressInt64x8", + argLen: 2, + generic: true, + }, + { + name: "CompressUint8x16", + argLen: 2, + generic: true, + }, + { + name: "CompressUint8x32", + argLen: 2, + generic: true, + }, + { + name: "CompressUint8x64", + argLen: 2, + generic: true, + }, + { + name: "CompressUint16x8", + argLen: 2, + generic: true, + }, + { + name: "CompressUint16x16", + argLen: 2, + generic: true, + }, + { + name: "CompressUint16x32", + argLen: 2, + generic: true, + }, + { + name: "CompressUint32x4", + argLen: 2, + generic: true, + }, + { + name: "CompressUint32x8", + argLen: 2, + generic: true, + }, + { + name: "CompressUint32x16", + argLen: 2, + generic: true, + }, + { + name: "CompressUint64x2", + argLen: 2, + generic: true, + }, + { + name: "CompressUint64x4", + argLen: 2, + generic: true, + }, + { + name: "CompressUint64x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsGroupedFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsGroupedFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsGroupedInt16x16", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsGroupedInt32x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsGroupedUint16x16", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsGroupedUint32x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsInt32x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsInt64x2", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsSaturatedGroupedInt16x16", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsSaturatedInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsUint16x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsUint32x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatAddPairsUint64x2", + argLen: 2, + generic: true, + }, + { + name: "ConcatEvenInt8x16", + argLen: 2, + generic: true, + }, + { + name: "ConcatEvenInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatEvenInt32x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatEvenInt64x2", + argLen: 2, + generic: true, + }, + { + name: "ConcatEvenUint8x16", + argLen: 2, + generic: true, + }, + { + name: "ConcatEvenUint16x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatEvenUint32x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatEvenUint64x2", + argLen: 2, + generic: true, + }, + { + name: "ConcatOddInt8x16", + argLen: 2, + generic: true, + }, + { + name: "ConcatOddInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatOddInt32x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatOddInt64x2", + argLen: 2, + generic: true, + }, + { + name: "ConcatOddUint8x16", + argLen: 2, + generic: true, + }, + { + name: "ConcatOddUint16x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatOddUint32x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatOddUint64x2", + argLen: 2, + generic: true, + }, + { + name: "ConcatPermuteFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt8x16", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt8x32", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt8x64", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt16x8", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt16x16", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt16x32", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt32x4", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt32x8", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt32x16", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt64x2", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt64x4", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteInt64x8", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint8x16", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint8x32", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint8x64", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint16x8", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint16x16", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint16x32", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint32x4", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint32x8", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint32x16", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint64x2", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint64x4", + argLen: 3, + generic: true, + }, + { + name: "ConcatPermuteUint64x8", + argLen: 3, + generic: true, + }, + { + name: "ConcatSubPairsFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsGroupedFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsGroupedFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsGroupedInt16x16", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsGroupedInt32x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsGroupedUint16x16", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsGroupedUint32x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsInt32x4", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsSaturatedGroupedInt16x16", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsSaturatedInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsUint16x8", + argLen: 2, + generic: true, + }, + { + name: "ConcatSubPairsUint32x4", + argLen: 2, + generic: true, + }, + { + name: "ConvertLo2ToFloat64Float32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertLo2ToFloat64Int32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertLo2ToFloat64Uint32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Float64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Float64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Float64x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Int32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Int32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Int32x16", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Int64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Int64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Int64x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Uint32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Uint32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Uint32x16", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Uint64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Uint64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat32Uint64x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Float32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Float32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Int32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Int32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Int64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Int64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Int64x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Uint32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Uint32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Uint64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Uint64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToFloat64Uint64x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt32Float32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt32Float32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt32Float32x16", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt32Float64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt32Float64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt32Float64x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt64Float32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt64Float32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt64Float64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt64Float64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt64Float64x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint32Float32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint32Float32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint32Float32x16", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint32Float64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint32Float64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint32Float64x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint64Float32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint64Float32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint64Float64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint64Float64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint64Float64x8", + argLen: 1, + generic: true, + }, + { + name: "DivFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "DivFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "DivFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "DivFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "DivFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "DivFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "DotProductPairsInt16x8", + argLen: 2, + generic: true, + }, + { + name: "DotProductPairsInt16x16", + argLen: 2, + generic: true, + }, + { + name: "DotProductPairsInt16x32", + argLen: 2, + generic: true, + }, + { + name: "DotProductPairsSaturatedUint8x16", + argLen: 2, + generic: true, + }, + { + name: "DotProductPairsSaturatedUint8x32", + argLen: 2, + generic: true, + }, + { + name: "DotProductPairsSaturatedUint8x64", + argLen: 2, + generic: true, + }, + { + name: "EqualFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "ExpandFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "ExpandFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "ExpandFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "ExpandFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "ExpandFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "ExpandFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt8x16", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt8x32", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt8x64", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt16x16", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt16x32", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt32x4", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt32x8", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt32x16", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt64x2", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt64x4", + argLen: 2, + generic: true, + }, + { + name: "ExpandInt64x8", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint8x16", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint8x32", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint8x64", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint16x8", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint16x16", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint16x32", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint32x4", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint32x8", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint32x16", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint64x2", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint64x4", + argLen: 2, + generic: true, + }, + { + name: "ExpandUint64x8", + argLen: 2, + generic: true, + }, + { + name: "ExtendHi2ToInt64Int32x4", + argLen: 1, + generic: true, + }, + { + name: "ExtendHi2ToUint64Uint32x4", + argLen: 1, + generic: true, + }, + { + name: "ExtendHi4ToInt32Int16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendHi4ToUint32Uint16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendHi8ToInt16Int8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendHi8ToUint16Uint8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo2ToInt64Int8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo2ToInt64Int16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo2ToInt64Int32x4", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo2ToUint64Uint8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo2ToUint64Uint16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo2ToUint64Uint32x4", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo4ToInt32Int8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo4ToInt32Int16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo4ToInt64Int8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo4ToInt64Int16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo4ToUint32Uint8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo4ToUint32Uint16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo4ToUint64Uint8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo4ToUint64Uint16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo8ToInt16Int8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo8ToInt32Int8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo8ToInt64Int8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo8ToUint16Uint8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo8ToUint32Uint8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendLo8ToUint64Uint8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendToInt16Int8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendToInt16Int8x32", + argLen: 1, + generic: true, + }, + { + name: "ExtendToInt32Int8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendToInt32Int16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendToInt32Int16x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendToInt64Int16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendToInt64Int32x4", + argLen: 1, + generic: true, + }, + { + name: "ExtendToInt64Int32x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendToUint16Uint8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendToUint16Uint8x32", + argLen: 1, + generic: true, + }, + { + name: "ExtendToUint32Uint8x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendToUint32Uint16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendToUint32Uint16x16", + argLen: 1, + generic: true, + }, + { + name: "ExtendToUint64Uint16x8", + argLen: 1, + generic: true, + }, + { + name: "ExtendToUint64Uint32x4", + argLen: 1, + generic: true, + }, + { + name: "ExtendToUint64Uint32x8", + argLen: 1, + generic: true, + }, + { + name: "FloorFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "FloorFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "FloorFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "FloorFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "GaloisFieldMulUint8x16", + argLen: 2, + generic: true, + }, + { + name: "GaloisFieldMulUint8x32", + argLen: 2, + generic: true, + }, + { + name: "GaloisFieldMulUint8x64", + argLen: 2, + generic: true, + }, + { + name: "GetHiFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "GetHiFloat32x16", + argLen: 1, + generic: true, + }, + { + name: "GetHiFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "GetHiFloat64x8", + argLen: 1, + generic: true, + }, + { + name: "GetHiInt8x32", + argLen: 1, + generic: true, + }, + { + name: "GetHiInt8x64", + argLen: 1, + generic: true, + }, + { + name: "GetHiInt16x16", + argLen: 1, + generic: true, + }, + { + name: "GetHiInt16x32", + argLen: 1, + generic: true, + }, + { + name: "GetHiInt32x8", + argLen: 1, + generic: true, + }, + { + name: "GetHiInt32x16", + argLen: 1, + generic: true, + }, + { + name: "GetHiInt64x4", + argLen: 1, + generic: true, + }, + { + name: "GetHiInt64x8", + argLen: 1, + generic: true, + }, + { + name: "GetHiUint8x32", + argLen: 1, + generic: true, + }, + { + name: "GetHiUint8x64", + argLen: 1, + generic: true, + }, + { + name: "GetHiUint16x16", + argLen: 1, + generic: true, + }, + { + name: "GetHiUint16x32", + argLen: 1, + generic: true, + }, + { + name: "GetHiUint32x8", + argLen: 1, + generic: true, + }, + { + name: "GetHiUint32x16", + argLen: 1, + generic: true, + }, + { + name: "GetHiUint64x4", + argLen: 1, + generic: true, + }, + { + name: "GetHiUint64x8", + argLen: 1, + generic: true, + }, + { + name: "GetLoFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "GetLoFloat32x16", + argLen: 1, + generic: true, + }, + { + name: "GetLoFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "GetLoFloat64x8", + argLen: 1, + generic: true, + }, + { + name: "GetLoInt8x32", + argLen: 1, + generic: true, + }, + { + name: "GetLoInt8x64", + argLen: 1, + generic: true, + }, + { + name: "GetLoInt16x16", + argLen: 1, + generic: true, + }, + { + name: "GetLoInt16x32", + argLen: 1, + generic: true, + }, + { + name: "GetLoInt32x8", + argLen: 1, + generic: true, + }, + { + name: "GetLoInt32x16", + argLen: 1, + generic: true, + }, + { + name: "GetLoInt64x4", + argLen: 1, + generic: true, + }, + { + name: "GetLoInt64x8", + argLen: 1, + generic: true, + }, + { + name: "GetLoUint8x32", + argLen: 1, + generic: true, + }, + { + name: "GetLoUint8x64", + argLen: 1, + generic: true, + }, + { + name: "GetLoUint16x16", + argLen: 1, + generic: true, + }, + { + name: "GetLoUint16x32", + argLen: 1, + generic: true, + }, + { + name: "GetLoUint32x8", + argLen: 1, + generic: true, + }, + { + name: "GetLoUint32x16", + argLen: 1, + generic: true, + }, + { + name: "GetLoUint64x4", + argLen: 1, + generic: true, + }, + { + name: "GetLoUint64x8", + argLen: 1, + generic: true, + }, + { + name: "GreaterEqualFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt8x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt8x64", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt16x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt16x32", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt32x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt32x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt64x2", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt64x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint8x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint8x64", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint16x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint16x32", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint32x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint32x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint64x2", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint64x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "GreaterFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt8x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt8x32", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt8x64", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt16x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt16x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt16x32", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt32x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt32x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt32x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt64x2", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt64x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterInt64x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterUint8x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterUint8x64", + argLen: 2, + generic: true, + }, + { + name: "GreaterUint16x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterUint16x32", + argLen: 2, + generic: true, + }, + { + name: "GreaterUint32x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterUint32x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterUint64x2", + argLen: 2, + generic: true, + }, + { + name: "GreaterUint64x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveEvenInt8x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveEvenInt16x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveEvenInt32x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveEvenInt64x2", + argLen: 2, + generic: true, + }, + { + name: "InterleaveEvenUint8x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveEvenUint16x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveEvenUint32x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveEvenUint64x2", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedInt16x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedInt16x32", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedInt32x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedInt32x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedInt64x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedInt64x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedUint16x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedUint16x32", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedUint32x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedUint32x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedUint64x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiGroupedUint64x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiInt8x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiInt16x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiInt32x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiInt64x2", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiUint8x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiUint16x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiUint32x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveHiUint64x2", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedInt16x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedInt16x32", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedInt32x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedInt32x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedInt64x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedInt64x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedUint16x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedUint16x32", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedUint32x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedUint32x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedUint64x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoGroupedUint64x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoInt8x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoInt16x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoInt32x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoInt64x2", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoUint8x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoUint16x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoUint32x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveLoUint64x2", + argLen: 2, + generic: true, + }, + { + name: "InterleaveOddInt8x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveOddInt16x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveOddInt32x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveOddInt64x2", + argLen: 2, + generic: true, + }, + { + name: "InterleaveOddUint8x16", + argLen: 2, + generic: true, + }, + { + name: "InterleaveOddUint16x8", + argLen: 2, + generic: true, + }, + { + name: "InterleaveOddUint32x4", + argLen: 2, + generic: true, + }, + { + name: "InterleaveOddUint64x2", + argLen: 2, + generic: true, + }, + { + name: "LeadingSignBitsInt8x16", + argLen: 1, + generic: true, + }, + { + name: "LeadingSignBitsInt16x8", + argLen: 1, + generic: true, + }, + { + name: "LeadingSignBitsInt32x4", + argLen: 1, + generic: true, + }, + { + name: "LeadingSignBitsUint8x16", + argLen: 1, + generic: true, + }, + { + name: "LeadingSignBitsUint16x8", + argLen: 1, + generic: true, + }, + { + name: "LeadingSignBitsUint32x4", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosInt8x16", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosInt16x8", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosInt32x4", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosInt32x8", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosInt32x16", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosInt64x2", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosInt64x4", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosInt64x8", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosUint8x16", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosUint16x8", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosUint32x4", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosUint32x8", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosUint32x16", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosUint64x2", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosUint64x4", + argLen: 1, + generic: true, + }, + { + name: "LeadingZerosUint64x8", + argLen: 1, + generic: true, + }, + { + name: "LessEqualFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt8x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt8x64", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt16x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt16x32", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt32x4", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt32x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt64x2", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt64x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint8x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint8x64", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint16x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint16x32", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint32x4", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint32x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint64x8", + argLen: 2, + generic: true, + }, + { + name: "LessFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "LessFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "LessFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "LessFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "LessFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "LessFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "LessInt8x16", + argLen: 2, + generic: true, + }, + { + name: "LessInt8x64", + argLen: 2, + generic: true, + }, + { + name: "LessInt16x8", + argLen: 2, + generic: true, + }, + { + name: "LessInt16x32", + argLen: 2, + generic: true, + }, + { + name: "LessInt32x4", + argLen: 2, + generic: true, + }, + { + name: "LessInt32x16", + argLen: 2, + generic: true, + }, + { + name: "LessInt64x2", + argLen: 2, + generic: true, + }, + { + name: "LessInt64x8", + argLen: 2, + generic: true, + }, + { + name: "LessUint8x16", + argLen: 2, + generic: true, + }, + { + name: "LessUint8x64", + argLen: 2, + generic: true, + }, + { + name: "LessUint16x8", + argLen: 2, + generic: true, + }, + { + name: "LessUint16x32", + argLen: 2, + generic: true, + }, + { + name: "LessUint32x4", + argLen: 2, + generic: true, + }, + { + name: "LessUint32x16", + argLen: 2, + generic: true, + }, + { + name: "LessUint64x8", + argLen: 2, + generic: true, + }, + { + name: "LookupOrZeroInt8x16", + argLen: 2, + generic: true, + }, + { + name: "LookupOrZeroUint8x16", + argLen: 2, + generic: true, + }, + { + name: "MaxFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MaxUint64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulAddEvenSubOddFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "MulAddEvenSubOddFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "MulAddEvenSubOddFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "MulAddEvenSubOddFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "MulAddEvenSubOddFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "MulAddEvenSubOddFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "MulAddFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "MulAddFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "MulAddFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "MulAddFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "MulAddFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "MulAddFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "MulAddInt8x16", + argLen: 3, + generic: true, + }, + { + name: "MulAddInt16x8", + argLen: 3, + generic: true, + }, + { + name: "MulAddInt32x4", + argLen: 3, + generic: true, + }, + { + name: "MulAddOddSubEvenFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "MulAddOddSubEvenFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "MulAddOddSubEvenFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "MulAddOddSubEvenFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "MulAddOddSubEvenFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "MulAddOddSubEvenFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "MulAddUint8x16", + argLen: 3, + generic: true, + }, + { + name: "MulAddUint16x8", + argLen: 3, + generic: true, + }, + { + name: "MulAddUint32x4", + argLen: 3, + generic: true, + }, + { + name: "MulFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulSignInt8x16", + argLen: 2, + generic: true, + }, + { + name: "MulSignInt8x32", + argLen: 2, + generic: true, + }, + { + name: "MulSignInt16x8", + argLen: 2, + generic: true, + }, + { + name: "MulSignInt16x16", + argLen: 2, + generic: true, + }, + { + name: "MulSignInt32x4", + argLen: 2, + generic: true, + }, + { + name: "MulSignInt32x8", + argLen: 2, + generic: true, + }, + { + name: "MulUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulUint32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulUint64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenEvenInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenEvenInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenEvenUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenEvenUint32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenHiInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenHiInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenHiInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenHiUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenHiUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenHiUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenLoInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenLoInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenLoInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenLoUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenLoUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulWidenLoUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NegFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "NegFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "NegInt8x16", + argLen: 1, + generic: true, + }, + { + name: "NegInt16x8", + argLen: 1, + generic: true, + }, + { + name: "NegInt32x4", + argLen: 1, + generic: true, + }, + { + name: "NegInt64x2", + argLen: 1, + generic: true, + }, + { + name: "NotEqualFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotInt8x16", + argLen: 1, + generic: true, + }, + { + name: "NotInt16x8", + argLen: 1, + generic: true, + }, + { + name: "NotInt32x4", + argLen: 1, + generic: true, + }, + { + name: "NotInt64x2", + argLen: 1, + generic: true, + }, + { + name: "NotUint8x16", + argLen: 1, + generic: true, + }, + { + name: "NotUint16x8", + argLen: 1, + generic: true, + }, + { + name: "NotUint32x4", + argLen: 1, + generic: true, + }, + { + name: "NotUint64x2", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt8x16", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt8x32", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt8x64", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt16x8", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt16x16", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt16x32", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt32x4", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt32x8", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt32x16", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt64x2", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt64x4", + argLen: 1, + generic: true, + }, + { + name: "OnesCountInt64x8", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint8x16", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint8x32", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint8x64", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint16x8", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint16x16", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint16x32", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint32x4", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint32x8", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint32x16", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint64x2", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint64x4", + argLen: 1, + generic: true, + }, + { + name: "OnesCountUint64x8", + argLen: 1, + generic: true, + }, + { + name: "OrInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrNotInt8x16", + argLen: 2, + generic: true, + }, + { + name: "OrNotInt16x8", + argLen: 2, + generic: true, + }, + { + name: "OrNotInt32x4", + argLen: 2, + generic: true, + }, + { + name: "OrNotInt64x2", + argLen: 2, + generic: true, + }, + { + name: "OrNotUint8x16", + argLen: 2, + generic: true, + }, + { + name: "OrNotUint16x8", + argLen: 2, + generic: true, + }, + { + name: "OrNotUint32x4", + argLen: 2, + generic: true, + }, + { + name: "OrNotUint64x2", + argLen: 2, + generic: true, + }, + { + name: "OrUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PermuteFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "PermuteFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "PermuteFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "PermuteFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "PermuteInt8x16", + argLen: 2, + generic: true, + }, + { + name: "PermuteInt8x32", + argLen: 2, + generic: true, + }, + { + name: "PermuteInt8x64", + argLen: 2, + generic: true, + }, + { + name: "PermuteInt16x8", + argLen: 2, + generic: true, + }, + { + name: "PermuteInt16x16", + argLen: 2, + generic: true, + }, + { + name: "PermuteInt16x32", + argLen: 2, + generic: true, + }, + { + name: "PermuteInt32x8", + argLen: 2, + generic: true, + }, + { + name: "PermuteInt32x16", + argLen: 2, + generic: true, + }, + { + name: "PermuteInt64x4", + argLen: 2, + generic: true, + }, + { + name: "PermuteInt64x8", + argLen: 2, + generic: true, + }, + { + name: "PermuteOrZeroGroupedInt8x32", + argLen: 2, + generic: true, + }, + { + name: "PermuteOrZeroGroupedInt8x64", + argLen: 2, + generic: true, + }, + { + name: "PermuteOrZeroGroupedUint8x32", + argLen: 2, + generic: true, + }, + { + name: "PermuteOrZeroGroupedUint8x64", + argLen: 2, + generic: true, + }, + { + name: "PermuteOrZeroInt8x16", + argLen: 2, + generic: true, + }, + { + name: "PermuteOrZeroUint8x16", + argLen: 2, + generic: true, + }, + { + name: "PermuteUint8x16", + argLen: 2, + generic: true, + }, + { + name: "PermuteUint8x32", + argLen: 2, + generic: true, + }, + { + name: "PermuteUint8x64", + argLen: 2, + generic: true, + }, + { + name: "PermuteUint16x8", + argLen: 2, + generic: true, + }, + { + name: "PermuteUint16x16", + argLen: 2, + generic: true, + }, + { + name: "PermuteUint16x32", + argLen: 2, + generic: true, + }, + { + name: "PermuteUint32x8", + argLen: 2, + generic: true, + }, + { + name: "PermuteUint32x16", + argLen: 2, + generic: true, + }, + { + name: "PermuteUint64x4", + argLen: 2, + generic: true, + }, + { + name: "PermuteUint64x8", + argLen: 2, + generic: true, + }, + { + name: "ReciprocalFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalFloat32x16", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalFloat64x8", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalSqrtFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalSqrtFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalSqrtFloat32x16", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalSqrtFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalSqrtFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "ReciprocalSqrtFloat64x8", + argLen: 1, + generic: true, + }, + { + name: "RotateAllLeftVarInt8x16", + argLen: 2, + generic: true, + }, + { + name: "RotateAllLeftVarInt16x8", + argLen: 2, + generic: true, + }, + { + name: "RotateAllLeftVarInt32x4", + argLen: 2, + generic: true, + }, + { + name: "RotateAllLeftVarInt64x2", + argLen: 2, + generic: true, + }, + { + name: "RotateAllLeftVarUint8x16", + argLen: 2, + generic: true, + }, + { + name: "RotateAllLeftVarUint16x8", + argLen: 2, + generic: true, + }, + { + name: "RotateAllLeftVarUint32x4", + argLen: 2, + generic: true, + }, + { + name: "RotateAllLeftVarUint64x2", + argLen: 2, + generic: true, + }, + { + name: "RotateAllRightVarInt8x16", + argLen: 2, + generic: true, + }, + { + name: "RotateAllRightVarInt16x8", + argLen: 2, + generic: true, + }, + { + name: "RotateAllRightVarInt32x4", + argLen: 2, + generic: true, + }, + { + name: "RotateAllRightVarInt64x2", + argLen: 2, + generic: true, + }, + { + name: "RotateAllRightVarUint8x16", + argLen: 2, + generic: true, + }, + { + name: "RotateAllRightVarUint16x8", + argLen: 2, + generic: true, + }, + { + name: "RotateAllRightVarUint32x4", + argLen: 2, + generic: true, + }, + { + name: "RotateAllRightVarUint64x2", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftInt32x4", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftInt32x8", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftInt32x16", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftInt64x2", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftInt64x4", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftInt64x8", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftUint32x4", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftUint32x8", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftUint32x16", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftUint64x2", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftUint64x4", + argLen: 2, + generic: true, + }, + { + name: "RotateLeftUint64x8", + argLen: 2, + generic: true, + }, + { + name: "RotateRightInt32x4", + argLen: 2, + generic: true, + }, + { + name: "RotateRightInt32x8", + argLen: 2, + generic: true, + }, + { + name: "RotateRightInt32x16", + argLen: 2, + generic: true, + }, + { + name: "RotateRightInt64x2", + argLen: 2, + generic: true, + }, + { + name: "RotateRightInt64x4", + argLen: 2, + generic: true, + }, + { + name: "RotateRightInt64x8", + argLen: 2, + generic: true, + }, + { + name: "RotateRightUint32x4", + argLen: 2, + generic: true, + }, + { + name: "RotateRightUint32x8", + argLen: 2, + generic: true, + }, + { + name: "RotateRightUint32x16", + argLen: 2, + generic: true, + }, + { + name: "RotateRightUint64x2", + argLen: 2, + generic: true, + }, + { + name: "RotateRightUint64x4", + argLen: 2, + generic: true, + }, + { + name: "RotateRightUint64x8", + argLen: 2, + generic: true, + }, + { + name: "RoundFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "RoundFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "RoundFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "RoundFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "SHA1Message1Uint32x4", + argLen: 2, + generic: true, + }, + { + name: "SHA1Message2Uint32x4", + argLen: 2, + generic: true, + }, + { + name: "SHA1NextEUint32x4", + argLen: 2, + generic: true, + }, + { + name: "SHA256Message1Uint32x4", + argLen: 2, + generic: true, + }, + { + name: "SHA256Message2Uint32x4", + argLen: 2, + generic: true, + }, + { + name: "SHA256TwoRoundsUint32x4", + argLen: 3, + generic: true, + }, + { + name: "SaturateToInt8Int16x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt8Int16x16", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt8Int16x32", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt8Int32x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt8Int32x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt8Int32x16", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt8Int64x2", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt8Int64x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt8Int64x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt16ConcatGroupedInt32x8", + argLen: 2, + generic: true, + }, + { + name: "SaturateToInt16ConcatGroupedInt32x16", + argLen: 2, + generic: true, + }, + { + name: "SaturateToInt16ConcatInt32x4", + argLen: 2, + generic: true, + }, + { + name: "SaturateToInt16Int32x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt16Int32x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt16Int32x16", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt16Int64x2", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt16Int64x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt16Int64x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt32Int64x2", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt32Int64x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToInt32Int64x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint8Int16x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint8Uint16x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint8Uint16x16", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint8Uint16x32", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint8Uint32x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint8Uint32x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint8Uint32x16", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint8Uint64x2", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint8Uint64x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint8Uint64x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint16ConcatGroupedInt32x8", + argLen: 2, + generic: true, + }, + { + name: "SaturateToUint16ConcatGroupedInt32x16", + argLen: 2, + generic: true, + }, + { + name: "SaturateToUint16ConcatInt32x4", + argLen: 2, + generic: true, + }, + { + name: "SaturateToUint16Int32x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint16Uint32x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint16Uint32x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint16Uint32x16", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint16Uint64x2", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint16Uint64x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint16Uint64x8", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint32Int64x2", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint32Uint64x2", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint32Uint64x4", + argLen: 1, + generic: true, + }, + { + name: "SaturateToUint32Uint64x8", + argLen: 1, + generic: true, + }, + { + name: "ScaleFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "ScaleFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "ScaleFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "ScaleFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "ScaleFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "ScaleFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "SetHiFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "SetHiFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "SetHiFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "SetHiFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "SetHiInt8x32", + argLen: 2, + generic: true, + }, + { + name: "SetHiInt8x64", + argLen: 2, + generic: true, + }, + { + name: "SetHiInt16x16", + argLen: 2, + generic: true, + }, + { + name: "SetHiInt16x32", + argLen: 2, + generic: true, + }, + { + name: "SetHiInt32x8", + argLen: 2, + generic: true, + }, + { + name: "SetHiInt32x16", + argLen: 2, + generic: true, + }, + { + name: "SetHiInt64x4", + argLen: 2, + generic: true, + }, + { + name: "SetHiInt64x8", + argLen: 2, + generic: true, + }, + { + name: "SetHiUint8x32", + argLen: 2, + generic: true, + }, + { + name: "SetHiUint8x64", + argLen: 2, + generic: true, + }, + { + name: "SetHiUint16x16", + argLen: 2, + generic: true, + }, + { + name: "SetHiUint16x32", + argLen: 2, + generic: true, + }, + { + name: "SetHiUint32x8", + argLen: 2, + generic: true, + }, + { + name: "SetHiUint32x16", + argLen: 2, + generic: true, + }, + { + name: "SetHiUint64x4", + argLen: 2, + generic: true, + }, + { + name: "SetHiUint64x8", + argLen: 2, + generic: true, + }, { - name: "Mul64", - argLen: 2, - commutative: true, - generic: true, + name: "SetLoFloat32x8", + argLen: 2, + generic: true, }, { - name: "Mul32F", - argLen: 2, - commutative: true, - generic: true, + name: "SetLoFloat32x16", + argLen: 2, + generic: true, }, { - name: "Mul64F", - argLen: 2, - commutative: true, - generic: true, + name: "SetLoFloat64x4", + argLen: 2, + generic: true, }, { - name: "Div32F", + name: "SetLoFloat64x8", argLen: 2, generic: true, }, { - name: "Div64F", + name: "SetLoInt8x32", argLen: 2, generic: true, }, { - name: "Hmul32", - argLen: 2, - commutative: true, - generic: true, + name: "SetLoInt8x64", + argLen: 2, + generic: true, }, { - name: "Hmul32u", - argLen: 2, - commutative: true, - generic: true, + name: "SetLoInt16x16", + argLen: 2, + generic: true, }, { - name: "Hmul64", - argLen: 2, - commutative: true, - generic: true, + name: "SetLoInt16x32", + argLen: 2, + generic: true, }, { - name: "Hmul64u", - argLen: 2, - commutative: true, - generic: true, + name: "SetLoInt32x8", + argLen: 2, + generic: true, }, { - name: "Mul32uhilo", - argLen: 2, - commutative: true, - generic: true, + name: "SetLoInt32x16", + argLen: 2, + generic: true, }, { - name: "Mul64uhilo", - argLen: 2, - commutative: true, - generic: true, + name: "SetLoInt64x4", + argLen: 2, + generic: true, }, { - name: "Mul32uover", - argLen: 2, - commutative: true, - generic: true, + name: "SetLoInt64x8", + argLen: 2, + generic: true, + }, + { + name: "SetLoUint8x32", + argLen: 2, + generic: true, + }, + { + name: "SetLoUint8x64", + argLen: 2, + generic: true, + }, + { + name: "SetLoUint16x16", + argLen: 2, + generic: true, + }, + { + name: "SetLoUint16x32", + argLen: 2, + generic: true, + }, + { + name: "SetLoUint32x8", + argLen: 2, + generic: true, + }, + { + name: "SetLoUint32x16", + argLen: 2, + generic: true, + }, + { + name: "SetLoUint64x4", + argLen: 2, + generic: true, + }, + { + name: "SetLoUint64x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftInt8x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftInt16x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftInt16x32", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftInt32x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftInt32x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftInt32x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftInt64x2", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftInt64x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftInt64x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftUint8x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftUint16x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftUint16x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftUint16x32", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftUint32x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftUint32x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftUint32x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftUint64x2", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftUint64x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllLeftUint64x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightInt8x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightInt16x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightInt16x32", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightInt32x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightInt32x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightInt32x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightInt64x2", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightInt64x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightInt64x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightUint8x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightUint16x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightUint16x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightUint16x32", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightUint32x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightUint32x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightUint32x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightUint64x2", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightUint64x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftAllRightUint64x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftInt8x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftInt32x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftInt64x2", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftConcatMod16Int16x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod16Int16x16", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod16Int16x32", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod16Uint16x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod16Uint16x16", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod16Uint16x32", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod32Int32x4", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod32Int32x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod32Int32x16", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod32Uint32x4", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod32Uint32x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod32Uint32x16", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod64Int64x2", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod64Int64x4", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod64Int64x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod64Uint64x2", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod64Uint64x4", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftConcatMod64Uint64x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftLeftInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftInt16x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftInt16x32", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftInt32x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftInt32x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftInt32x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftInt64x2", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftInt64x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftInt64x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftUint16x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftUint16x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftUint16x32", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftUint32x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftUint32x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftUint32x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftUint64x2", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftUint64x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftLeftUint64x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftRightConcatMod16Int16x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod16Int16x16", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod16Int16x32", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod16Uint16x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod16Uint16x16", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod16Uint16x32", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod32Int32x4", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod32Int32x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod32Int32x16", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod32Uint32x4", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod32Uint32x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod32Uint32x16", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod64Int64x2", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod64Int64x4", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod64Int64x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod64Uint64x2", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod64Uint64x4", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightConcatMod64Uint64x8", + argLen: 3, + generic: true, + }, + { + name: "ShiftRightInt16x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftRightInt16x16", + argLen: 2, + generic: true, + }, + { + name: "ShiftRightInt16x32", + argLen: 2, + generic: true, + }, + { + name: "ShiftRightInt32x4", + argLen: 2, + generic: true, + }, + { + name: "ShiftRightInt32x8", + argLen: 2, + generic: true, + }, + { + name: "ShiftRightInt32x16", + argLen: 2, + generic: true, }, { - name: "Mul64uover", - argLen: 2, - commutative: true, - generic: true, + name: "ShiftRightInt64x2", + argLen: 2, + generic: true, }, { - name: "Avg32u", + name: "ShiftRightInt64x4", argLen: 2, generic: true, }, { - name: "Avg64u", + name: "ShiftRightInt64x8", argLen: 2, generic: true, }, { - name: "Div8", + name: "ShiftRightUint16x8", argLen: 2, generic: true, }, { - name: "Div8u", + name: "ShiftRightUint16x16", argLen: 2, generic: true, }, { - name: "Div16", - auxType: auxBool, + name: "ShiftRightUint16x32", argLen: 2, generic: true, }, { - name: "Div16u", + name: "ShiftRightUint32x4", argLen: 2, generic: true, }, { - name: "Div32", - auxType: auxBool, + name: "ShiftRightUint32x8", argLen: 2, generic: true, }, { - name: "Div32u", + name: "ShiftRightUint32x16", argLen: 2, generic: true, }, { - name: "Div64", - auxType: auxBool, + name: "ShiftRightUint64x2", argLen: 2, generic: true, }, { - name: "Div64u", + name: "ShiftRightUint64x4", argLen: 2, generic: true, }, { - name: "Div128u", - argLen: 3, + name: "ShiftRightUint64x8", + argLen: 2, generic: true, }, { - name: "Mod8", + name: "ShiftSaturatedInt8x16", argLen: 2, generic: true, }, { - name: "Mod8u", + name: "ShiftSaturatedInt16x8", argLen: 2, generic: true, }, { - name: "Mod16", - auxType: auxBool, + name: "ShiftSaturatedInt32x4", argLen: 2, generic: true, }, { - name: "Mod16u", + name: "ShiftSaturatedInt64x2", argLen: 2, generic: true, }, { - name: "Mod32", - auxType: auxBool, + name: "ShiftSaturatedUint8x16", argLen: 2, generic: true, }, { - name: "Mod32u", + name: "ShiftSaturatedUint16x8", argLen: 2, generic: true, }, { - name: "Mod64", - auxType: auxBool, + name: "ShiftSaturatedUint32x4", argLen: 2, generic: true, }, { - name: "Mod64u", + name: "ShiftSaturatedUint64x2", argLen: 2, generic: true, }, { - name: "And8", - argLen: 2, - commutative: true, - generic: true, + name: "ShiftUint8x16", + argLen: 2, + generic: true, }, { - name: "And16", - argLen: 2, - commutative: true, - generic: true, + name: "ShiftUint16x8", + argLen: 2, + generic: true, }, { - name: "And32", - argLen: 2, - commutative: true, - generic: true, + name: "ShiftUint32x4", + argLen: 2, + generic: true, }, { - name: "And64", - argLen: 2, - commutative: true, - generic: true, + name: "ShiftUint64x2", + argLen: 2, + generic: true, }, { - name: "Or8", - argLen: 2, - commutative: true, - generic: true, + name: "SqrtFloat32x4", + argLen: 1, + generic: true, }, { - name: "Or16", - argLen: 2, - commutative: true, - generic: true, + name: "SqrtFloat32x8", + argLen: 1, + generic: true, }, { - name: "Or32", - argLen: 2, - commutative: true, - generic: true, + name: "SqrtFloat32x16", + argLen: 1, + generic: true, }, { - name: "Or64", - argLen: 2, - commutative: true, - generic: true, + name: "SqrtFloat64x2", + argLen: 1, + generic: true, }, { - name: "Xor8", - argLen: 2, - commutative: true, - generic: true, + name: "SqrtFloat64x4", + argLen: 1, + generic: true, }, { - name: "Xor16", - argLen: 2, - commutative: true, - generic: true, + name: "SqrtFloat64x8", + argLen: 1, + generic: true, }, { - name: "Xor32", - argLen: 2, - commutative: true, - generic: true, + name: "SubFloat32x4", + argLen: 2, + generic: true, }, { - name: "Xor64", - argLen: 2, - commutative: true, - generic: true, + name: "SubFloat32x8", + argLen: 2, + generic: true, }, { - name: "Lsh8x8", - auxType: auxBool, + name: "SubFloat32x16", argLen: 2, generic: true, }, { - name: "Lsh8x16", - auxType: auxBool, + name: "SubFloat64x2", argLen: 2, generic: true, }, { - name: "Lsh8x32", - auxType: auxBool, + name: "SubFloat64x4", argLen: 2, generic: true, }, { - name: "Lsh8x64", - auxType: auxBool, + name: "SubFloat64x8", argLen: 2, generic: true, }, { - name: "Lsh16x8", - auxType: auxBool, + name: "SubInt8x16", argLen: 2, generic: true, }, { - name: "Lsh16x16", - auxType: auxBool, + name: "SubInt8x32", argLen: 2, generic: true, }, { - name: "Lsh16x32", - auxType: auxBool, + name: "SubInt8x64", argLen: 2, generic: true, }, { - name: "Lsh16x64", - auxType: auxBool, + name: "SubInt16x8", argLen: 2, generic: true, }, { - name: "Lsh32x8", - auxType: auxBool, + name: "SubInt16x16", argLen: 2, generic: true, }, { - name: "Lsh32x16", - auxType: auxBool, + name: "SubInt16x32", argLen: 2, generic: true, }, { - name: "Lsh32x32", - auxType: auxBool, + name: "SubInt32x4", argLen: 2, generic: true, }, { - name: "Lsh32x64", - auxType: auxBool, + name: "SubInt32x8", argLen: 2, generic: true, }, { - name: "Lsh64x8", - auxType: auxBool, + name: "SubInt32x16", argLen: 2, generic: true, }, { - name: "Lsh64x16", - auxType: auxBool, + name: "SubInt64x2", argLen: 2, generic: true, }, { - name: "Lsh64x32", - auxType: auxBool, + name: "SubInt64x4", argLen: 2, generic: true, }, { - name: "Lsh64x64", - auxType: auxBool, + name: "SubInt64x8", argLen: 2, generic: true, }, { - name: "Rsh8x8", - auxType: auxBool, + name: "SubSaturatedInt8x16", argLen: 2, generic: true, }, { - name: "Rsh8x16", - auxType: auxBool, + name: "SubSaturatedInt8x32", argLen: 2, generic: true, }, { - name: "Rsh8x32", - auxType: auxBool, + name: "SubSaturatedInt8x64", argLen: 2, generic: true, }, { - name: "Rsh8x64", - auxType: auxBool, + name: "SubSaturatedInt16x8", argLen: 2, generic: true, }, { - name: "Rsh16x8", - auxType: auxBool, + name: "SubSaturatedInt16x16", argLen: 2, generic: true, }, { - name: "Rsh16x16", - auxType: auxBool, + name: "SubSaturatedInt16x32", argLen: 2, generic: true, }, { - name: "Rsh16x32", - auxType: auxBool, + name: "SubSaturatedInt32x4", argLen: 2, generic: true, }, { - name: "Rsh16x64", - auxType: auxBool, + name: "SubSaturatedInt64x2", argLen: 2, generic: true, }, { - name: "Rsh32x8", - auxType: auxBool, + name: "SubSaturatedUint8x16", argLen: 2, generic: true, }, { - name: "Rsh32x16", - auxType: auxBool, + name: "SubSaturatedUint8x32", argLen: 2, generic: true, }, { - name: "Rsh32x32", - auxType: auxBool, + name: "SubSaturatedUint8x64", argLen: 2, generic: true, }, { - name: "Rsh32x64", - auxType: auxBool, + name: "SubSaturatedUint16x8", argLen: 2, generic: true, }, { - name: "Rsh64x8", - auxType: auxBool, + name: "SubSaturatedUint16x16", argLen: 2, generic: true, }, { - name: "Rsh64x16", - auxType: auxBool, + name: "SubSaturatedUint16x32", argLen: 2, generic: true, }, { - name: "Rsh64x32", - auxType: auxBool, + name: "SubSaturatedUint32x4", argLen: 2, generic: true, }, { - name: "Rsh64x64", - auxType: auxBool, + name: "SubSaturatedUint64x2", argLen: 2, generic: true, }, { - name: "Rsh8Ux8", - auxType: auxBool, + name: "SubUint8x16", argLen: 2, generic: true, }, { - name: "Rsh8Ux16", - auxType: auxBool, + name: "SubUint8x32", argLen: 2, generic: true, }, { - name: "Rsh8Ux32", - auxType: auxBool, + name: "SubUint8x64", argLen: 2, generic: true, }, { - name: "Rsh8Ux64", - auxType: auxBool, + name: "SubUint16x8", argLen: 2, generic: true, }, { - name: "Rsh16Ux8", - auxType: auxBool, + name: "SubUint16x16", argLen: 2, generic: true, }, { - name: "Rsh16Ux16", - auxType: auxBool, + name: "SubUint16x32", argLen: 2, generic: true, }, { - name: "Rsh16Ux32", - auxType: auxBool, + name: "SubUint32x4", argLen: 2, generic: true, }, { - name: "Rsh16Ux64", - auxType: auxBool, + name: "SubUint32x8", argLen: 2, generic: true, }, { - name: "Rsh32Ux8", - auxType: auxBool, + name: "SubUint32x16", argLen: 2, generic: true, }, { - name: "Rsh32Ux16", - auxType: auxBool, + name: "SubUint64x2", argLen: 2, generic: true, }, { - name: "Rsh32Ux32", - auxType: auxBool, + name: "SubUint64x4", argLen: 2, generic: true, }, { - name: "Rsh32Ux64", - auxType: auxBool, + name: "SubUint64x8", argLen: 2, generic: true, }, { - name: "Rsh64Ux8", - auxType: auxBool, + name: "SumOf8AbsDiffUint8x16", argLen: 2, generic: true, }, { - name: "Rsh64Ux16", - auxType: auxBool, + name: "SumOf8AbsDiffUint8x32", argLen: 2, generic: true, }, { - name: "Rsh64Ux32", - auxType: auxBool, + name: "SumOf8AbsDiffUint8x64", argLen: 2, generic: true, }, { - name: "Rsh64Ux64", - auxType: auxBool, - argLen: 2, + name: "TruncFloat32x4", + argLen: 1, generic: true, }, { - name: "Eq8", - argLen: 2, - commutative: true, - generic: true, + name: "TruncFloat32x8", + argLen: 1, + generic: true, }, { - name: "Eq16", - argLen: 2, - commutative: true, - generic: true, + name: "TruncFloat64x2", + argLen: 1, + generic: true, }, { - name: "Eq32", - argLen: 2, - commutative: true, - generic: true, + name: "TruncFloat64x4", + argLen: 1, + generic: true, }, { - name: "Eq64", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt8Int16x8", + argLen: 1, + generic: true, }, { - name: "EqPtr", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt8Int16x16", + argLen: 1, + generic: true, }, { - name: "EqInter", - argLen: 2, + name: "TruncToInt8Int16x32", + argLen: 1, generic: true, }, { - name: "EqSlice", - argLen: 2, + name: "TruncToInt8Int32x4", + argLen: 1, generic: true, }, { - name: "Eq32F", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt8Int32x8", + argLen: 1, + generic: true, }, { - name: "Eq64F", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt8Int32x16", + argLen: 1, + generic: true, }, { - name: "Neq8", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt8Int64x2", + argLen: 1, + generic: true, }, { - name: "Neq16", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt8Int64x4", + argLen: 1, + generic: true, }, { - name: "Neq32", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt8Int64x8", + argLen: 1, + generic: true, }, { - name: "Neq64", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt16Int32x4", + argLen: 1, + generic: true, }, { - name: "NeqPtr", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt16Int32x8", + argLen: 1, + generic: true, }, { - name: "NeqInter", - argLen: 2, + name: "TruncToInt16Int32x16", + argLen: 1, generic: true, }, { - name: "NeqSlice", - argLen: 2, + name: "TruncToInt16Int64x2", + argLen: 1, generic: true, }, { - name: "Neq32F", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt16Int64x4", + argLen: 1, + generic: true, }, { - name: "Neq64F", - argLen: 2, - commutative: true, - generic: true, + name: "TruncToInt16Int64x8", + argLen: 1, + generic: true, }, { - name: "Less8", - argLen: 2, + name: "TruncToInt32Int64x2", + argLen: 1, generic: true, }, { - name: "Less8U", - argLen: 2, + name: "TruncToInt32Int64x4", + argLen: 1, generic: true, }, { - name: "Less16", - argLen: 2, + name: "TruncToInt32Int64x8", + argLen: 1, generic: true, }, { - name: "Less16U", - argLen: 2, + name: "TruncToUint8Uint16x8", + argLen: 1, generic: true, }, { - name: "Less32", - argLen: 2, + name: "TruncToUint8Uint16x16", + argLen: 1, generic: true, }, { - name: "Less32U", - argLen: 2, + name: "TruncToUint8Uint16x32", + argLen: 1, generic: true, }, { - name: "Less64", - argLen: 2, + name: "TruncToUint8Uint32x4", + argLen: 1, generic: true, }, { - name: "Less64U", - argLen: 2, + name: "TruncToUint8Uint32x8", + argLen: 1, generic: true, }, { - name: "Less32F", - argLen: 2, + name: "TruncToUint8Uint32x16", + argLen: 1, generic: true, }, { - name: "Less64F", - argLen: 2, + name: "TruncToUint8Uint64x2", + argLen: 1, generic: true, }, { - name: "Leq8", - argLen: 2, + name: "TruncToUint8Uint64x4", + argLen: 1, generic: true, }, { - name: "Leq8U", - argLen: 2, + name: "TruncToUint8Uint64x8", + argLen: 1, generic: true, }, { - name: "Leq16", - argLen: 2, + name: "TruncToUint16Uint32x4", + argLen: 1, generic: true, }, { - name: "Leq16U", - argLen: 2, + name: "TruncToUint16Uint32x8", + argLen: 1, generic: true, }, { - name: "Leq32", - argLen: 2, + name: "TruncToUint16Uint32x16", + argLen: 1, generic: true, }, { - name: "Leq32U", - argLen: 2, + name: "TruncToUint16Uint64x2", + argLen: 1, generic: true, }, { - name: "Leq64", - argLen: 2, + name: "TruncToUint16Uint64x4", + argLen: 1, generic: true, }, { - name: "Leq64U", - argLen: 2, + name: "TruncToUint16Uint64x8", + argLen: 1, generic: true, }, { - name: "Leq32F", - argLen: 2, + name: "TruncToUint32Uint64x2", + argLen: 1, generic: true, }, { - name: "Leq64F", - argLen: 2, + name: "TruncToUint32Uint64x4", + argLen: 1, generic: true, }, { - name: "CondSelect", - argLen: 3, + name: "TruncToUint32Uint64x8", + argLen: 1, generic: true, }, { - name: "AndB", + name: "XorInt8x16", argLen: 2, commutative: true, generic: true, }, { - name: "OrB", + name: "XorInt8x32", argLen: 2, commutative: true, generic: true, }, { - name: "EqB", + name: "XorInt8x64", argLen: 2, commutative: true, generic: true, }, { - name: "NeqB", + name: "XorInt16x8", argLen: 2, commutative: true, generic: true, }, { - name: "Not", + name: "XorInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "XorUint64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "bitSelectInt8x16", + argLen: 3, + generic: true, + }, + { + name: "bitSelectNotInt8x16", + argLen: 3, + generic: true, + }, + { + name: "blendInt8x16", + argLen: 3, + generic: true, + }, + { + name: "blendInt8x32", + argLen: 3, + generic: true, + }, + { + name: "blendMaskedInt8x64", + argLen: 3, + generic: true, + }, + { + name: "blendMaskedInt16x32", + argLen: 3, + generic: true, + }, + { + name: "blendMaskedInt32x16", + argLen: 3, + generic: true, + }, + { + name: "blendMaskedInt64x8", + argLen: 3, + generic: true, + }, + { + name: "broadcast1To2Float64x2", argLen: 1, generic: true, }, { - name: "Neg8", + name: "broadcast1To2Int64x2", argLen: 1, generic: true, }, { - name: "Neg16", + name: "broadcast1To2MaskedFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "broadcast1To2MaskedInt64x2", + argLen: 2, + generic: true, + }, + { + name: "broadcast1To2MaskedUint64x2", + argLen: 2, + generic: true, + }, + { + name: "broadcast1To2Uint64x2", argLen: 1, generic: true, }, { - name: "Neg32", + name: "broadcast1To4Float32x4", argLen: 1, generic: true, }, { - name: "Neg64", + name: "broadcast1To4Float64x2", argLen: 1, generic: true, }, { - name: "Neg32F", + name: "broadcast1To4Int32x4", argLen: 1, generic: true, }, { - name: "Neg64F", + name: "broadcast1To4Int64x2", argLen: 1, generic: true, }, { - name: "Com8", - argLen: 1, + name: "broadcast1To4MaskedFloat32x4", + argLen: 2, generic: true, }, { - name: "Com16", - argLen: 1, + name: "broadcast1To4MaskedFloat64x2", + argLen: 2, generic: true, }, { - name: "Com32", - argLen: 1, + name: "broadcast1To4MaskedInt32x4", + argLen: 2, generic: true, }, { - name: "Com64", - argLen: 1, + name: "broadcast1To4MaskedInt64x2", + argLen: 2, generic: true, }, { - name: "Ctz8", - argLen: 1, + name: "broadcast1To4MaskedUint32x4", + argLen: 2, generic: true, }, { - name: "Ctz16", - argLen: 1, + name: "broadcast1To4MaskedUint64x2", + argLen: 2, generic: true, }, { - name: "Ctz32", + name: "broadcast1To4Uint32x4", argLen: 1, generic: true, }, { - name: "Ctz64", + name: "broadcast1To4Uint64x2", argLen: 1, generic: true, }, { - name: "Ctz64On32", - argLen: 2, + name: "broadcast1To8Float32x4", + argLen: 1, generic: true, }, { - name: "Ctz8NonZero", + name: "broadcast1To8Float64x2", argLen: 1, generic: true, }, { - name: "Ctz16NonZero", + name: "broadcast1To8Int16x8", argLen: 1, generic: true, }, { - name: "Ctz32NonZero", + name: "broadcast1To8Int32x4", argLen: 1, generic: true, }, { - name: "Ctz64NonZero", + name: "broadcast1To8Int64x2", argLen: 1, generic: true, }, { - name: "BitLen8", - argLen: 1, + name: "broadcast1To8MaskedFloat32x4", + argLen: 2, generic: true, }, { - name: "BitLen16", - argLen: 1, + name: "broadcast1To8MaskedFloat64x2", + argLen: 2, generic: true, }, { - name: "BitLen32", - argLen: 1, + name: "broadcast1To8MaskedInt16x8", + argLen: 2, generic: true, }, { - name: "BitLen64", - argLen: 1, + name: "broadcast1To8MaskedInt32x4", + argLen: 2, generic: true, }, { - name: "Bswap16", - argLen: 1, + name: "broadcast1To8MaskedInt64x2", + argLen: 2, generic: true, }, { - name: "Bswap32", - argLen: 1, + name: "broadcast1To8MaskedUint16x8", + argLen: 2, generic: true, }, { - name: "Bswap64", - argLen: 1, + name: "broadcast1To8MaskedUint32x4", + argLen: 2, generic: true, }, { - name: "BitRev8", - argLen: 1, + name: "broadcast1To8MaskedUint64x2", + argLen: 2, generic: true, }, { - name: "BitRev16", + name: "broadcast1To8Uint16x8", argLen: 1, generic: true, }, { - name: "BitRev32", + name: "broadcast1To8Uint32x4", argLen: 1, generic: true, }, { - name: "BitRev64", + name: "broadcast1To8Uint64x2", argLen: 1, generic: true, }, { - name: "PopCount8", + name: "broadcast1To16Float32x4", argLen: 1, generic: true, }, { - name: "PopCount16", + name: "broadcast1To16Int8x16", argLen: 1, generic: true, }, { - name: "PopCount32", + name: "broadcast1To16Int16x8", argLen: 1, generic: true, }, { - name: "PopCount64", + name: "broadcast1To16Int32x4", argLen: 1, generic: true, }, { - name: "RotateLeft64", + name: "broadcast1To16MaskedFloat32x4", argLen: 2, generic: true, }, { - name: "RotateLeft32", + name: "broadcast1To16MaskedInt8x16", argLen: 2, generic: true, }, { - name: "RotateLeft16", + name: "broadcast1To16MaskedInt16x8", argLen: 2, generic: true, }, { - name: "RotateLeft8", + name: "broadcast1To16MaskedInt32x4", argLen: 2, generic: true, }, { - name: "Sqrt", - argLen: 1, + name: "broadcast1To16MaskedUint8x16", + argLen: 2, generic: true, }, { - name: "Sqrt32", - argLen: 1, + name: "broadcast1To16MaskedUint16x8", + argLen: 2, generic: true, }, { - name: "Floor", - argLen: 1, + name: "broadcast1To16MaskedUint32x4", + argLen: 2, generic: true, }, { - name: "Ceil", + name: "broadcast1To16Uint8x16", argLen: 1, generic: true, }, { - name: "Trunc", + name: "broadcast1To16Uint16x8", argLen: 1, generic: true, }, { - name: "Round", + name: "broadcast1To16Uint32x4", argLen: 1, generic: true, }, { - name: "RoundToEven", + name: "broadcast1To32Int8x16", argLen: 1, generic: true, }, { - name: "Abs", + name: "broadcast1To32Int16x8", argLen: 1, generic: true, }, { - name: "Copysign", + name: "broadcast1To32MaskedInt8x16", argLen: 2, generic: true, }, { - name: "Min64", + name: "broadcast1To32MaskedInt16x8", argLen: 2, generic: true, }, { - name: "Max64", + name: "broadcast1To32MaskedUint8x16", argLen: 2, generic: true, }, { - name: "Min64u", + name: "broadcast1To32MaskedUint16x8", argLen: 2, generic: true, }, { - name: "Max64u", - argLen: 2, + name: "broadcast1To32Uint8x16", + argLen: 1, generic: true, }, { - name: "Min64F", - argLen: 2, + name: "broadcast1To32Uint16x8", + argLen: 1, generic: true, }, { - name: "Min32F", - argLen: 2, + name: "broadcast1To64Int8x16", + argLen: 1, generic: true, }, { - name: "Max64F", + name: "broadcast1To64MaskedInt8x16", argLen: 2, generic: true, }, { - name: "Max32F", + name: "broadcast1To64MaskedUint8x16", argLen: 2, generic: true, }, { - name: "FMA", - argLen: 3, + name: "broadcast1To64Uint8x16", + argLen: 1, generic: true, }, { - name: "Phi", - argLen: -1, - zeroWidth: true, - generic: true, + name: "carrylessMultiplyWidenLoUint64x2", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Copy", + name: "reduceMaxFloat32x4", argLen: 1, generic: true, }, { - name: "Convert", - argLen: 2, - resultInArg0: true, - zeroWidth: true, - generic: true, + name: "reduceMaxInt8x16", + argLen: 1, + generic: true, }, { - name: "ConstBool", - auxType: auxBool, - argLen: 0, + name: "reduceMaxInt16x8", + argLen: 1, generic: true, }, { - name: "ConstString", - auxType: auxString, - argLen: 0, + name: "reduceMaxInt32x4", + argLen: 1, generic: true, }, { - name: "ConstNil", - argLen: 0, + name: "reduceMaxUint8x16", + argLen: 1, generic: true, }, { - name: "Const8", - auxType: auxInt8, - argLen: 0, + name: "reduceMaxUint16x8", + argLen: 1, generic: true, }, { - name: "Const16", - auxType: auxInt16, - argLen: 0, + name: "reduceMaxUint32x4", + argLen: 1, generic: true, }, { - name: "Const32", - auxType: auxInt32, - argLen: 0, + name: "reduceMinFloat32x4", + argLen: 1, generic: true, }, { - name: "Const64", - auxType: auxInt64, - argLen: 0, + name: "reduceMinInt8x16", + argLen: 1, generic: true, }, { - name: "Const32F", - auxType: auxFloat32, - argLen: 0, + name: "reduceMinInt16x8", + argLen: 1, generic: true, }, { - name: "Const64F", - auxType: auxFloat64, - argLen: 0, + name: "reduceMinInt32x4", + argLen: 1, generic: true, }, { - name: "ConstInterface", - argLen: 0, + name: "reduceMinUint8x16", + argLen: 1, generic: true, }, { - name: "ConstSlice", - argLen: 0, + name: "reduceMinUint16x8", + argLen: 1, generic: true, }, { - name: "InitMem", - argLen: 0, - zeroWidth: true, - generic: true, + name: "reduceMinUint32x4", + argLen: 1, + generic: true, }, { - name: "Arg", - auxType: auxSymOff, - argLen: 0, - zeroWidth: true, - symEffect: SymRead, - generic: true, + name: "reduceSumInt8x16", + argLen: 1, + generic: true, }, { - name: "ArgIntReg", - auxType: auxNameOffsetInt8, - argLen: 0, - zeroWidth: true, - generic: true, + name: "reduceSumInt16x8", + argLen: 1, + generic: true, }, { - name: "ArgFloatReg", - auxType: auxNameOffsetInt8, - argLen: 0, - zeroWidth: true, - generic: true, + name: "reduceSumInt32x4", + argLen: 1, + generic: true, }, { - name: "Addr", - auxType: auxSym, - argLen: 1, - symEffect: SymAddr, - generic: true, + name: "reduceSumUint8x16", + argLen: 1, + generic: true, }, { - name: "LocalAddr", - auxType: auxSym, - argLen: 2, - symEffect: SymAddr, - generic: true, + name: "reduceSumUint16x8", + argLen: 1, + generic: true, }, { - name: "SP", - argLen: 0, - zeroWidth: true, - fixedReg: true, - generic: true, + name: "reduceSumUint32x4", + argLen: 1, + generic: true, }, { - name: "SB", - argLen: 0, - zeroWidth: true, - fixedReg: true, - generic: true, + name: "AESRoundKeyGenAssistUint32x4", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "SPanchored", - argLen: 2, - zeroWidth: true, - generic: true, + name: "CeilScaledFloat32x4", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "Load", - argLen: 2, + name: "CeilScaledFloat32x8", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "Dereference", - argLen: 2, + name: "CeilScaledFloat32x16", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "Store", - auxType: auxTyp, - argLen: 3, + name: "CeilScaledFloat64x2", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "Move", - auxType: auxTypSize, - argLen: 3, + name: "CeilScaledFloat64x4", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "Zero", - auxType: auxTypSize, - argLen: 2, + name: "CeilScaledFloat64x8", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "StoreWB", - auxType: auxTyp, - argLen: 3, + name: "CeilScaledResidueFloat32x4", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "MoveWB", - auxType: auxTypSize, - argLen: 3, + name: "CeilScaledResidueFloat32x8", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "ZeroWB", - auxType: auxTypSize, - argLen: 2, + name: "CeilScaledResidueFloat32x16", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "WBend", + name: "CeilScaledResidueFloat64x2", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "WB", - auxType: auxInt64, + name: "CeilScaledResidueFloat64x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "HasCPUFeature", - auxType: auxSym, - argLen: 0, - symEffect: SymNone, - generic: true, + name: "CeilScaledResidueFloat64x8", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "PanicBounds", - auxType: auxInt64, - argLen: 3, - call: true, + name: "ConcatPermute128ScalarsFloat32x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "PanicExtend", - auxType: auxInt64, - argLen: 4, - call: true, + name: "ConcatPermute128ScalarsFloat64x4", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "ClosureCall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "ConcatPermute128ScalarsInt8x32", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "StaticCall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "ConcatPermute128ScalarsInt16x16", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "InterCall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "ConcatPermute128ScalarsInt32x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "TailCall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "ConcatPermute128ScalarsInt64x4", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "ClosureLECall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "ConcatPermute128ScalarsUint8x32", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "StaticLECall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "ConcatPermute128ScalarsUint16x16", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "InterLECall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "ConcatPermute128ScalarsUint32x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "TailLECall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "ConcatPermute128ScalarsUint64x4", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "SignExt8to16", - argLen: 1, + name: "ConcatShiftBytesRightGroupedUint8x32", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "SignExt8to32", + name: "ConcatShiftBytesRightGroupedUint8x64", + auxType: auxUInt8, + argLen: 2, + generic: true, + }, + { + name: "ConcatShiftBytesRightUint8x16", + auxType: auxUInt8, + argLen: 2, + generic: true, + }, + { + name: "FloorScaledFloat32x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "SignExt8to64", + name: "FloorScaledFloat32x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "SignExt16to32", + name: "FloorScaledFloat32x16", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "SignExt16to64", + name: "FloorScaledFloat64x2", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "SignExt32to64", + name: "FloorScaledFloat64x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "ZeroExt8to16", + name: "FloorScaledFloat64x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "ZeroExt8to32", + name: "FloorScaledResidueFloat32x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "ZeroExt8to64", + name: "FloorScaledResidueFloat32x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "ZeroExt16to32", + name: "FloorScaledResidueFloat32x16", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "ZeroExt16to64", + name: "FloorScaledResidueFloat64x2", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "ZeroExt32to64", + name: "FloorScaledResidueFloat64x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Trunc16to8", + name: "FloorScaledResidueFloat64x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Trunc32to8", + name: "GaloisFieldAffineTransformInverseUint8x16", + auxType: auxUInt8, + argLen: 2, + generic: true, + }, + { + name: "GaloisFieldAffineTransformInverseUint8x32", + auxType: auxUInt8, + argLen: 2, + generic: true, + }, + { + name: "GaloisFieldAffineTransformInverseUint8x64", + auxType: auxUInt8, + argLen: 2, + generic: true, + }, + { + name: "GaloisFieldAffineTransformUint8x16", + auxType: auxUInt8, + argLen: 2, + generic: true, + }, + { + name: "GaloisFieldAffineTransformUint8x32", + auxType: auxUInt8, + argLen: 2, + generic: true, + }, + { + name: "GaloisFieldAffineTransformUint8x64", + auxType: auxUInt8, + argLen: 2, + generic: true, + }, + { + name: "GetElemFloat32x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Trunc32to16", + name: "GetElemFloat64x2", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Trunc64to8", + name: "GetElemInt8x16", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Trunc64to16", + name: "GetElemInt16x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Trunc64to32", + name: "GetElemInt32x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt32to32F", + name: "GetElemInt64x2", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt32to64F", + name: "GetElemUint8x16", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt64to32F", + name: "GetElemUint16x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt64to64F", + name: "GetElemUint32x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt32Fto32", + name: "GetElemUint64x2", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt32Fto64", + name: "RoundScaledFloat32x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt64Fto32", + name: "RoundScaledFloat32x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt64Fto64", + name: "RoundScaledFloat32x16", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt32Fto64F", + name: "RoundScaledFloat64x2", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt64Fto32F", + name: "RoundScaledFloat64x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "CvtBoolToUint8", + name: "RoundScaledFloat64x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Round32F", + name: "RoundScaledResidueFloat32x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Round64F", + name: "RoundScaledResidueFloat32x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "IsNonNil", + name: "RoundScaledResidueFloat32x16", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "IsInBounds", - argLen: 2, + name: "RoundScaledResidueFloat64x2", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "IsSliceInBounds", - argLen: 2, + name: "RoundScaledResidueFloat64x4", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "NilCheck", - argLen: 2, - nilCheck: true, - generic: true, + name: "RoundScaledResidueFloat64x8", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "GetG", - argLen: 1, - zeroWidth: true, - generic: true, + name: "SHA1FourRoundsUint32x4", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "GetClosurePtr", - argLen: 0, + name: "SetElemFloat32x4", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "GetCallerPC", - argLen: 0, + name: "SetElemFloat64x2", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "GetCallerSP", - argLen: 1, + name: "SetElemInt8x16", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "PtrIndex", + name: "SetElemInt16x8", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "OffPtr", - auxType: auxInt64, - argLen: 1, + name: "SetElemInt32x4", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "SliceMake", - argLen: 3, + name: "SetElemInt64x2", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "SlicePtr", - argLen: 1, + name: "SetElemUint8x16", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "SliceLen", - argLen: 1, + name: "SetElemUint16x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "SliceCap", - argLen: 1, + name: "SetElemUint32x4", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "SlicePtrUnchecked", - argLen: 1, + name: "SetElemUint64x2", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "ComplexMake", + name: "ShiftAllLeftConcatMod16Int16x8", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "ComplexReal", - argLen: 1, + name: "ShiftAllLeftConcatMod16Int16x16", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "ComplexImag", - argLen: 1, + name: "ShiftAllLeftConcatMod16Int16x32", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "StringMake", + name: "ShiftAllLeftConcatMod16Uint16x8", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "StringPtr", - argLen: 1, + name: "ShiftAllLeftConcatMod16Uint16x16", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "StringLen", - argLen: 1, + name: "ShiftAllLeftConcatMod16Uint16x32", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "IMake", + name: "ShiftAllLeftConcatMod32Int32x4", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "ITab", - argLen: 1, + name: "ShiftAllLeftConcatMod32Int32x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "IData", - argLen: 1, + name: "ShiftAllLeftConcatMod32Int32x16", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "StructMake", - argLen: -1, + name: "ShiftAllLeftConcatMod32Uint32x4", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "StructSelect", - auxType: auxInt64, - argLen: 1, + name: "ShiftAllLeftConcatMod32Uint32x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "ArrayMake0", - argLen: 0, + name: "ShiftAllLeftConcatMod32Uint32x16", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "ArrayMake1", - argLen: 1, + name: "ShiftAllLeftConcatMod64Int64x2", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "ArraySelect", - auxType: auxInt64, - argLen: 1, + name: "ShiftAllLeftConcatMod64Int64x4", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "StoreReg", - argLen: 1, + name: "ShiftAllLeftConcatMod64Int64x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "LoadReg", - argLen: 1, + name: "ShiftAllLeftConcatMod64Uint64x2", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "FwdRef", - auxType: auxSym, - argLen: 0, - symEffect: SymNone, - generic: true, + name: "ShiftAllLeftConcatMod64Uint64x4", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "Unknown", - argLen: 0, + name: "ShiftAllLeftConcatMod64Uint64x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "VarDef", - auxType: auxSym, - argLen: 1, - zeroWidth: true, - symEffect: SymNone, - generic: true, + name: "ShiftAllRightConcatMod16Int16x8", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "VarLive", - auxType: auxSym, - argLen: 1, - zeroWidth: true, - symEffect: SymRead, - generic: true, + name: "ShiftAllRightConcatMod16Int16x16", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "KeepAlive", - argLen: 2, - zeroWidth: true, - generic: true, + name: "ShiftAllRightConcatMod16Int16x32", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "InlMark", - auxType: auxInt32, - argLen: 1, + name: "ShiftAllRightConcatMod16Uint16x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "Int64Make", + name: "ShiftAllRightConcatMod16Uint16x16", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "Int64Hi", - argLen: 1, + name: "ShiftAllRightConcatMod16Uint16x32", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "Int64Lo", - argLen: 1, + name: "ShiftAllRightConcatMod32Int32x4", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "Add32carry", - argLen: 2, - commutative: true, - generic: true, + name: "ShiftAllRightConcatMod32Int32x8", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "Add32withcarry", - argLen: 3, - commutative: true, - generic: true, + name: "ShiftAllRightConcatMod32Int32x16", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "Sub32carry", + name: "ShiftAllRightConcatMod32Uint32x4", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "Sub32withcarry", - argLen: 3, + name: "ShiftAllRightConcatMod32Uint32x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "Add64carry", - argLen: 3, - commutative: true, - generic: true, + name: "ShiftAllRightConcatMod32Uint32x16", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "Sub64borrow", - argLen: 3, + name: "ShiftAllRightConcatMod64Int64x2", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "Signmask", - argLen: 1, + name: "ShiftAllRightConcatMod64Int64x4", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "Zeromask", - argLen: 1, + name: "ShiftAllRightConcatMod64Int64x8", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "Slicemask", - argLen: 1, + name: "ShiftAllRightConcatMod64Uint64x2", + auxType: auxUInt8, + argLen: 2, generic: true, }, { - name: "SpectreIndex", + name: "ShiftAllRightConcatMod64Uint64x4", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "SpectreSliceIndex", + name: "ShiftAllRightConcatMod64Uint64x8", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "Cvt32Uto32F", + name: "TruncScaledFloat32x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt32Uto64F", + name: "TruncScaledFloat32x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt32Fto32U", + name: "TruncScaledFloat32x16", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt64Fto32U", + name: "TruncScaledFloat64x2", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt64Uto32F", + name: "TruncScaledFloat64x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt64Uto64F", + name: "TruncScaledFloat64x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt32Fto64U", + name: "TruncScaledResidueFloat32x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Cvt64Fto64U", + name: "TruncScaledResidueFloat32x8", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "Select0", - argLen: 1, - zeroWidth: true, - generic: true, - }, - { - name: "Select1", - argLen: 1, - zeroWidth: true, - generic: true, - }, - { - name: "MakeTuple", - argLen: 2, + name: "TruncScaledResidueFloat32x16", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "SelectN", - auxType: auxInt64, + name: "TruncScaledResidueFloat64x2", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "SelectNAddr", - auxType: auxInt64, + name: "TruncScaledResidueFloat64x4", + auxType: auxUInt8, argLen: 1, generic: true, }, { - name: "MakeResult", - argLen: -1, + name: "TruncScaledResidueFloat64x8", + auxType: auxUInt8, + argLen: 1, generic: true, }, { - name: "AtomicLoad8", + name: "carrylessMultiplyUint64x2", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "AtomicLoad32", + name: "carrylessMultiplyUint64x4", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "AtomicLoad64", + name: "carrylessMultiplyUint64x8", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "AtomicLoadPtr", + name: "concatSelectedConstantFloat32x4", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "AtomicLoadAcq32", + name: "concatSelectedConstantFloat64x2", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "AtomicLoadAcq64", + name: "concatSelectedConstantGroupedFloat32x8", + auxType: auxUInt8, argLen: 2, generic: true, }, { - name: "AtomicStore8", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedFloat32x16", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStore32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedFloat64x4", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStore64", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedFloat64x8", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStorePtrNoWB", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedInt32x8", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStoreRel32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedInt32x16", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStoreRel64", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedInt64x4", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicExchange8", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedInt64x8", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicExchange32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedUint32x8", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicExchange64", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedUint32x16", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicAdd32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedUint64x4", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicAdd64", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantGroupedUint64x8", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicCompareAndSwap32", - argLen: 4, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantInt32x4", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicCompareAndSwap64", - argLen: 4, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantInt64x2", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicCompareAndSwapRel32", - argLen: 4, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantUint32x4", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicAnd8", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "concatSelectedConstantUint64x2", + auxType: auxUInt8, + argLen: 2, + generic: true, }, { - name: "AtomicOr8", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsGroupedInt32x8", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAnd32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsGroupedInt32x16", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicOr32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsGroupedUint32x8", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAnd64value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsGroupedUint32x16", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAnd32value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsHiGroupedInt16x16", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAnd8value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsHiGroupedInt16x32", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicOr64value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsHiGroupedUint16x16", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicOr32value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsHiGroupedUint16x32", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicOr8value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsHiInt16x8", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicStore8Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsHiUint16x8", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicStore32Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsInt32x4", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicStore64Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsLoGroupedInt16x16", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAdd32Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsLoGroupedInt16x32", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAdd64Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsLoGroupedUint16x16", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicExchange8Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsLoGroupedUint16x32", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicExchange32Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsLoInt16x8", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicExchange64Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "permuteScalarsLoUint16x8", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicCompareAndSwap32Variant", - argLen: 4, - hasSideEffects: true, - generic: true, + name: "permuteScalarsUint32x4", + auxType: auxUInt8, + argLen: 1, + generic: true, }, { - name: "AtomicCompareAndSwap64Variant", - argLen: 4, - hasSideEffects: true, - generic: true, + name: "ternInt32x4", + auxType: auxUInt8, + argLen: 3, + generic: true, }, { - name: "AtomicAnd64valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "ternInt32x8", + auxType: auxUInt8, + argLen: 3, + generic: true, }, { - name: "AtomicOr64valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "ternInt32x16", + auxType: auxUInt8, + argLen: 3, + generic: true, }, { - name: "AtomicAnd32valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "ternInt64x2", + auxType: auxUInt8, + argLen: 3, + generic: true, }, { - name: "AtomicOr32valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "ternInt64x4", + auxType: auxUInt8, + argLen: 3, + generic: true, }, { - name: "AtomicAnd8valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "ternInt64x8", + auxType: auxUInt8, + argLen: 3, + generic: true, }, { - name: "AtomicOr8valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "ternUint32x4", + auxType: auxUInt8, + argLen: 3, + generic: true, }, { - name: "PubBarrier", - argLen: 1, - hasSideEffects: true, - generic: true, + name: "ternUint32x8", + auxType: auxUInt8, + argLen: 3, + generic: true, }, { - name: "Clobber", - auxType: auxSymOff, - argLen: 0, - symEffect: SymNone, - generic: true, + name: "ternUint32x16", + auxType: auxUInt8, + argLen: 3, + generic: true, }, { - name: "ClobberReg", - argLen: 0, + name: "ternUint64x2", + auxType: auxUInt8, + argLen: 3, generic: true, }, { - name: "PrefetchCache", - argLen: 2, - hasSideEffects: true, - generic: true, + name: "ternUint64x4", + auxType: auxUInt8, + argLen: 3, + generic: true, }, { - name: "PrefetchCacheStreamed", - argLen: 2, - hasSideEffects: true, - generic: true, + name: "ternUint64x8", + auxType: auxUInt8, + argLen: 3, + generic: true, }, } @@ -42907,9 +116254,9 @@ var registers386 = [...]Register{ } var paramIntReg386 = []int8(nil) var paramFloatReg386 = []int8(nil) -var gpRegMask386 = regMask(239) -var fpRegMask386 = regMask(65280) -var specialRegMask386 = regMask(0) +var gpRegMask386 = regMask{v1: 239, v2: 0} +var fpRegMask386 = regMask{v1: 65280, v2: 0} +var specialRegMask386 = regMask{v1: 0, v2: 0} var framepointerReg386 = int8(5) var linkReg386 = int8(-1) var registersAMD64 = [...]Register{ @@ -42945,13 +116292,38 @@ var registersAMD64 = [...]Register{ {29, x86.REG_X13, "X13"}, {30, x86.REG_X14, "X14"}, {31, x86.REG_X15, "X15"}, - {32, 0, "SB"}, + {32, x86.REG_X16, "X16"}, + {33, x86.REG_X17, "X17"}, + {34, x86.REG_X18, "X18"}, + {35, x86.REG_X19, "X19"}, + {36, x86.REG_X20, "X20"}, + {37, x86.REG_X21, "X21"}, + {38, x86.REG_X22, "X22"}, + {39, x86.REG_X23, "X23"}, + {40, x86.REG_X24, "X24"}, + {41, x86.REG_X25, "X25"}, + {42, x86.REG_X26, "X26"}, + {43, x86.REG_X27, "X27"}, + {44, x86.REG_X28, "X28"}, + {45, x86.REG_X29, "X29"}, + {46, x86.REG_X30, "X30"}, + {47, x86.REG_X31, "X31"}, + {48, x86.REG_K0, "K0"}, + {49, x86.REG_K1, "K1"}, + {50, x86.REG_K2, "K2"}, + {51, x86.REG_K3, "K3"}, + {52, x86.REG_K4, "K4"}, + {53, x86.REG_K5, "K5"}, + {54, x86.REG_K6, "K6"}, + {55, x86.REG_K7, "K7"}, + {56, 0, "SB"}, } var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11} var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30} -var gpRegMaskAMD64 = regMask(49135) -var fpRegMaskAMD64 = regMask(2147418112) -var specialRegMaskAMD64 = regMask(2147483648) +var gpRegMaskAMD64 = regMask{v1: 49135, v2: 0} +var fpRegMaskAMD64 = regMask{v1: 2147418112, v2: 0} +var simdRegMaskAMD64 = regMask{v1: 2147418112, v2: 0} +var specialRegMaskAMD64 = regMask{v1: 71776114766249984, v2: 0} var framepointerRegAMD64 = int8(5) var linkRegAMD64 = int8(-1) var registersARM = [...]Register{ @@ -42991,9 +116363,9 @@ var registersARM = [...]Register{ } var paramIntRegARM = []int8(nil) var paramFloatRegARM = []int8(nil) -var gpRegMaskARM = regMask(21503) -var fpRegMaskARM = regMask(4294901760) -var specialRegMaskARM = regMask(0) +var gpRegMaskARM = regMask{v1: 21503, v2: 0} +var fpRegMaskARM = regMask{v1: 4294901760, v2: 0} +var specialRegMaskARM = regMask{v1: 0, v2: 0} var framepointerRegARM = int8(-1) var linkRegARM = int8(14) var registersARM64 = [...]Register{ @@ -43064,9 +116436,10 @@ var registersARM64 = [...]Register{ } var paramIntRegARM64 = []int8{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} var paramFloatRegARM64 = []int8{31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46} -var gpRegMaskARM64 = regMask(335544319) -var fpRegMaskARM64 = regMask(9223372034707292160) -var specialRegMaskARM64 = regMask(0) +var gpRegMaskARM64 = regMask{v1: 335544319, v2: 0} +var fpRegMaskARM64 = regMask{v1: 9223372034707292160, v2: 0} +var simdRegMaskARM64 = regMask{v1: 9223372034707292160, v2: 0} +var specialRegMaskARM64 = regMask{v1: 0, v2: 0} var framepointerRegARM64 = int8(-1) var linkRegARM64 = int8(28) var registersLOONG64 = [...]Register{ @@ -43136,9 +116509,9 @@ var registersLOONG64 = [...]Register{ } var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18} var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45} -var gpRegMaskLOONG64 = regMask(1071644664) -var fpRegMaskLOONG64 = regMask(4611686017353646080) -var specialRegMaskLOONG64 = regMask(0) +var gpRegMaskLOONG64 = regMask{v1: 1071644664, v2: 0} +var fpRegMaskLOONG64 = regMask{v1: 4611686017353646080, v2: 0} +var specialRegMaskLOONG64 = regMask{v1: 0, v2: 0} var framepointerRegLOONG64 = int8(-1) var linkRegLOONG64 = int8(1) var registersMIPS = [...]Register{ @@ -43193,9 +116566,9 @@ var registersMIPS = [...]Register{ } var paramIntRegMIPS = []int8(nil) var paramFloatRegMIPS = []int8(nil) -var gpRegMaskMIPS = regMask(335544318) -var fpRegMaskMIPS = regMask(35183835217920) -var specialRegMaskMIPS = regMask(105553116266496) +var gpRegMaskMIPS = regMask{v1: 335544318, v2: 0} +var fpRegMaskMIPS = regMask{v1: 35183835217920, v2: 0} +var specialRegMaskMIPS = regMask{v1: 105553116266496, v2: 0} var framepointerRegMIPS = int8(-1) var linkRegMIPS = int8(28) var registersMIPS64 = [...]Register{ @@ -43265,9 +116638,9 @@ var registersMIPS64 = [...]Register{ } var paramIntRegMIPS64 = []int8(nil) var paramFloatRegMIPS64 = []int8(nil) -var gpRegMaskMIPS64 = regMask(167772158) -var fpRegMaskMIPS64 = regMask(1152921504338411520) -var specialRegMaskMIPS64 = regMask(3458764513820540928) +var gpRegMaskMIPS64 = regMask{v1: 167772158, v2: 0} +var fpRegMaskMIPS64 = regMask{v1: 1152921504338411520, v2: 0} +var specialRegMaskMIPS64 = regMask{v1: 3458764513820540928, v2: 0} var framepointerRegMIPS64 = int8(-1) var linkRegMIPS64 = int8(27) var registersPPC64 = [...]Register{ @@ -43338,9 +116711,9 @@ var registersPPC64 = [...]Register{ } var paramIntRegPPC64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 17} var paramFloatRegPPC64 = []int8{33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44} -var gpRegMaskPPC64 = regMask(1073733624) -var fpRegMaskPPC64 = regMask(9223372032559808512) -var specialRegMaskPPC64 = regMask(9223372036854775808) +var gpRegMaskPPC64 = regMask{v1: 1073733624, v2: 0} +var fpRegMaskPPC64 = regMask{v1: 9223372032559808512, v2: 0} +var specialRegMaskPPC64 = regMask{v1: 9223372036854775808, v2: 0} var framepointerRegPPC64 = int8(-1) var linkRegPPC64 = int8(-1) var registersRISCV64 = [...]Register{ @@ -43411,9 +116784,9 @@ var registersRISCV64 = [...]Register{ } var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22} var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54} -var gpRegMaskRISCV64 = regMask(1006632944) -var fpRegMaskRISCV64 = regMask(9223372034707292160) -var specialRegMaskRISCV64 = regMask(0) +var gpRegMaskRISCV64 = regMask{v1: 1006632944, v2: 0} +var fpRegMaskRISCV64 = regMask{v1: 9223372034707292160, v2: 0} +var specialRegMaskRISCV64 = regMask{v1: 0, v2: 0} var framepointerRegRISCV64 = int8(-1) var linkRegRISCV64 = int8(0) var registersS390X = [...]Register{ @@ -43451,11 +116824,11 @@ var registersS390X = [...]Register{ {31, s390x.REG_F15, "F15"}, {32, 0, "SB"}, } -var paramIntRegS390X = []int8(nil) -var paramFloatRegS390X = []int8(nil) -var gpRegMaskS390X = regMask(23551) -var fpRegMaskS390X = regMask(4294901760) -var specialRegMaskS390X = regMask(0) +var paramIntRegS390X = []int8{2, 3, 4, 5, 6, 7, 8, 9} +var paramFloatRegS390X = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31} +var gpRegMaskS390X = regMask{v1: 23551, v2: 0} +var fpRegMaskS390X = regMask{v1: 4294901760, v2: 0} +var specialRegMaskS390X = regMask{v1: 0, v2: 0} var framepointerRegS390X = int8(-1) var linkRegS390X = int8(14) var registersWasm = [...]Register{ @@ -43507,16 +116880,33 @@ var registersWasm = [...]Register{ {45, wasm.REG_F29, "F29"}, {46, wasm.REG_F30, "F30"}, {47, wasm.REG_F31, "F31"}, - {48, wasm.REGSP, "SP"}, - {49, wasm.REGG, "g"}, - {50, 0, "SB"}, + {48, wasm.REG_V0, "V0"}, + {49, wasm.REG_V1, "V1"}, + {50, wasm.REG_V2, "V2"}, + {51, wasm.REG_V3, "V3"}, + {52, wasm.REG_V4, "V4"}, + {53, wasm.REG_V5, "V5"}, + {54, wasm.REG_V6, "V6"}, + {55, wasm.REG_V7, "V7"}, + {56, wasm.REG_V8, "V8"}, + {57, wasm.REG_V9, "V9"}, + {58, wasm.REG_V10, "V10"}, + {59, wasm.REG_V11, "V11"}, + {60, wasm.REG_V12, "V12"}, + {61, wasm.REG_V13, "V13"}, + {62, wasm.REG_V14, "V14"}, + {63, wasm.REG_V15, "V15"}, + {64, wasm.REGSP, "SP"}, + {65, wasm.REGG, "g"}, + {66, 0, "SB"}, } var paramIntRegWasm = []int8(nil) var paramFloatRegWasm = []int8(nil) -var gpRegMaskWasm = regMask(65535) -var fpRegMaskWasm = regMask(281474976645120) -var fp32RegMaskWasm = regMask(4294901760) -var fp64RegMaskWasm = regMask(281470681743360) -var specialRegMaskWasm = regMask(0) +var gpRegMaskWasm = regMask{v1: 65535, v2: 0} +var fpRegMaskWasm = regMask{v1: 281474976645120, v2: 0} +var fp32RegMaskWasm = regMask{v1: 4294901760, v2: 0} +var fp64RegMaskWasm = regMask{v1: 281470681743360, v2: 0} +var simdRegMaskWasm = regMask{v1: 18446462598732840960, v2: 0} +var specialRegMaskWasm = regMask{v1: 0, v2: 0} var framepointerRegWasm = int8(-1) var linkRegWasm = int8(-1) diff --git a/src/cmd/compile/internal/ssa/opt.go b/src/cmd/compile/internal/ssa/opt.go index 0f15c3db4a7ddb..9f155e6179b7e6 100644 --- a/src/cmd/compile/internal/ssa/opt.go +++ b/src/cmd/compile/internal/ssa/opt.go @@ -8,3 +8,11 @@ package ssa func opt(f *Func) { applyRewrite(f, rewriteBlockgeneric, rewriteValuegeneric, removeDeadValues) } + +func divisible(f *Func) { + applyRewrite(f, rewriteBlockdivisible, rewriteValuedivisible, removeDeadValues) +} + +func divmod(f *Func) { + applyRewrite(f, rewriteBlockdivmod, rewriteValuedivmod, removeDeadValues) +} diff --git a/src/cmd/compile/internal/ssa/pair.go b/src/cmd/compile/internal/ssa/pair.go index 83d7e476dd9c20..be524dc0a6c554 100644 --- a/src/cmd/compile/internal/ssa/pair.go +++ b/src/cmd/compile/internal/ssa/pair.go @@ -7,6 +7,7 @@ package ssa import ( "cmd/compile/internal/ir" "cmd/compile/internal/types" + "cmd/internal/obj" "slices" ) @@ -206,12 +207,183 @@ func pairLoads(f *Func) { i++ // Skip y next time around the loop. } } + + // Try to pair a load with a load from a subsequent block. + // Note that this is always safe to do if the memory arguments match. + // (But see the memory barrier case below.) + type nextBlockKey struct { + op Op + ptr ID + mem ID + auxInt int64 + aux any + } + nextBlock := map[nextBlockKey]*Value{} + for _, b := range f.Blocks { + if memoryBarrierTest(b) { + // TODO: Do we really need to skip write barrier test blocks? + // type T struct { + // a *byte + // b int + // } + // func f(t *T) int { + // r := t.b + // t.a = nil + // return r + // } + // This would issue a single LDP for both the t.a and t.b fields, + // *before* we check the write barrier flag. (We load the t.a field + // to put it in the write barrier buffer.) Not sure if that is ok. + continue + } + // Find loads in the next block(s) that we can move to this one. + // TODO: could maybe look further than just one successor hop. + clear(nextBlock) + for _, e := range b.Succs { + if len(e.b.Preds) > 1 { + continue + } + for _, v := range e.b.Values { + info := pairableLoads[v.Op] + if info.width == 0 { + continue + } + if !offsetOk(v.Aux, v.AuxInt, info.width) { + continue // not advisable + } + nextBlock[nextBlockKey{op: v.Op, ptr: v.Args[0].ID, mem: v.Args[1].ID, auxInt: v.AuxInt, aux: v.Aux}] = v + } + } + if len(nextBlock) == 0 { + continue + } + // don't move too many loads. Each requires a register across a basic block boundary. + const maxMoved = 4 + nMoved := 0 + for i := len(b.Values) - 1; i >= 0 && nMoved < maxMoved; i-- { + x := b.Values[i] + info := pairableLoads[x.Op] + if info.width == 0 { + continue + } + if !offsetOk(x.Aux, x.AuxInt, info.width) { + continue // not advisable + } + key := nextBlockKey{op: x.Op, ptr: x.Args[0].ID, mem: x.Args[1].ID, auxInt: x.AuxInt + info.width, aux: x.Aux} + if y := nextBlock[key]; y != nil { + delete(nextBlock, key) + + // Make the 2-register load. + load := b.NewValue2IA(x.Pos, info.pair, types.NewTuple(x.Type, y.Type), x.AuxInt, x.Aux, x.Args[0], x.Args[1]) + + // Modify x to be (Select0 load). + x.reset(OpSelect0) + x.SetArgs1(load) + // Modify y to be (Copy (Select1 load)). + // Note: the Select* needs to live in the load's block, not y's block. + y.reset(OpCopy) + y.SetArgs1(b.NewValue1(y.Pos, OpSelect1, y.Type, load)) + nMoved++ + continue + } + key.auxInt = x.AuxInt - info.width + if y := nextBlock[key]; y != nil { + delete(nextBlock, key) + + // Make the 2-register load. + load := b.NewValue2IA(x.Pos, info.pair, types.NewTuple(y.Type, x.Type), y.AuxInt, x.Aux, x.Args[0], x.Args[1]) + + // Modify x to be (Select1 load). + x.reset(OpSelect1) + x.SetArgs1(load) + // Modify y to be (Copy (Select0 load)). + y.reset(OpCopy) + y.SetArgs1(b.NewValue1(y.Pos, OpSelect0, y.Type, load)) + nMoved++ + continue + } + } + } } +func memoryBarrierTest(b *Block) bool { + if b.Kind != BlockARM64NZW { + return false + } + c := b.Controls[0] + if c.Op != OpARM64MOVWUload { + return false + } + if globl, ok := c.Aux.(*obj.LSym); ok { + return globl.Name == "runtime.writeBarrier" + } + return false +} + +// pairStores merges store instructions. +// It collects stores into a buffer where they can be freely reordered. +// When encountering an instruction that cannot be added to the buffer, +// it pairs the accumulated stores, flushes the buffer, and continues processing. func pairStores(f *Func) { last := f.Cache.allocBoolSlice(f.NumValues()) defer f.Cache.freeBoolSlice(last) + // memChain contains a list of stores with the same ptr/aux pair and + // nonoverlapping write ranges [AuxInt:AuxInt+writeSize]. All of the + // elements of memChain can be reordered with each other. + memChain := []*Value{} + + // Limit of length of memChain array. + // This keeps us in O(n) territory. + limit := 100 + + // flushMemChain sorts the stores in memChain and merges them when possible. + // Then it flushes memChain. + flushMemChain := func() { + if len(memChain) < 2 { + memChain = memChain[:0] + return + } + + // Sort in increasing AuxInt to put pairable stores together. + slices.SortFunc(memChain, func(x, y *Value) int { + return int(x.AuxInt - y.AuxInt) + }) + + lastIdx := len(memChain) - 1 + for i := 0; i < lastIdx; i++ { + v := memChain[i] + w := memChain[i+1] + info := pairableStores[v.Op] + + off := v.AuxInt + mem := v.MemoryArg() + aux := v.Aux + pos := v.Pos + wmem := w.MemoryArg() + + if w.Op == v.Op && w.AuxInt == off+info.width { + // Arguments for the merged store: ptr, val1, val2, mem. + args := []*Value{v.Args[0], v.Args[1], w.Args[1], mem} + + v.reset(info.pair) + v.AddArgs(args...) + v.Aux = aux + v.AuxInt = off + v.Pos = pos + + // Make w just a memory copy. + w.reset(OpCopy) + w.SetArgs1(wmem) + + // Skip merged store (w) + i++ + } + } + + memChain = memChain[:0] + } + // prevStore returns the previous store in the // same block, or nil if there are none. prevStore := func(v *Value) *Value { @@ -225,7 +397,28 @@ func pairStores(f *Func) { return m } + // storeWidth returns the width of store, + // or 0 if it is not a store this pass understands. + storeWidth := func(op Op) int64 { + var width int64 + switch op { + case OpARM64MOVDstore, OpARM64FMOVDstore: + width = 8 + case OpARM64MOVWstore, OpARM64FMOVSstore: + width = 4 + case OpARM64MOVHstore: + width = 2 + case OpARM64MOVBstore: + width = 1 + default: + width = 0 + } + return width + } + for _, b := range f.Blocks { + memChain = memChain[:0] + // Find last store in block, so we can // walk the stores last to first. // Last to first helps ensure that the rewrites we @@ -250,110 +443,46 @@ func pairStores(f *Func) { } } - // Check all stores, from last to first. - memCheck: + // Iterate over memory stores, accumulating them in memChain for potential merging. + // Flush the chain when reordering is unsafe or a conflict is detected. for v := lastMem; v != nil; v = prevStore(v) { - info := pairableStores[v.Op] - if info.width == 0 { - continue // Not pairable. + writeSize := storeWidth(v.Op) + + if writeSize == 0 { + // We can't reorder stores with calls or other instructions + // with writeSize == 0. + flushMemChain() + continue } - if !offsetOk(v.Aux, v.AuxInt, info.width) { - continue // Not advisable to pair. + if v.Uses != 1 && len(memChain) > 0 || + len(memChain) > 0 && (v.Args[0] != memChain[0].Args[0] || v.Aux != memChain[0].Aux) || + len(memChain) == limit { + // If v has multiple uses and it is not the latest store in the chain, + // we cannot merge it with other store instructions. + // If v has a different base pointer or Aux value from the current chain, + // we need to flush memChain and start a new one with v. + // If memChain length limit is exceeded, we also need to flush the chain + // and start a new one with v. + // Only look back so far. + // This keeps us in O(n) territory, and it + // also prevents us from keeping values + // in registers for too long (and thus + // needing to spill them). + flushMemChain() } - ptr := v.Args[0] - val := v.Args[1] - mem := v.Args[2] - off := v.AuxInt - aux := v.Aux - // Look for earlier store we can combine with. - lowerOk := true - higherOk := true - count := 10 // max lookback distance - for w := prevStore(v); w != nil; w = prevStore(w) { - if w.Uses != 1 { - // We can't combine stores if the earlier - // store has any use besides the next one - // in the store chain. - // (Unless we could check the aliasing of - // all those other uses.) - continue memCheck - } - if w.Op == v.Op && - w.Args[0] == ptr && - w.Aux == aux && - (lowerOk && w.AuxInt == off-info.width || higherOk && w.AuxInt == off+info.width) { - // This op is mergeable with v. - - // Commit point. - - // ptr val1 val2 mem - args := []*Value{ptr, val, w.Args[1], mem} - if w.AuxInt == off-info.width { - args[1], args[2] = args[2], args[1] - off -= info.width - } - v.reset(info.pair) - v.AddArgs(args...) - v.Aux = aux - v.AuxInt = off - v.Pos = w.Pos // take position of earlier of the two stores (TODO: not really working?) - - // Make w just a memory copy. - wmem := w.MemoryArg() - w.reset(OpCopy) - w.SetArgs1(wmem) - continue memCheck - } - if count--; count == 0 { - // Only look back so far. - // This keeps us in O(n) territory, and it - // also prevents us from keeping values - // in registers for too long (and thus - // needing to spill them). - continue memCheck - } - // We're now looking at a store w which is currently - // between the store v that we're intending to merge into, - // and the store we'll eventually find to merge with it. - // Make sure this store doesn't alias with the one - // we'll be moving. - var width int64 - switch w.Op { - case OpARM64MOVDstore, OpARM64FMOVDstore: - width = 8 - case OpARM64MOVWstore, OpARM64FMOVSstore: - width = 4 - case OpARM64MOVHstore: - width = 2 - case OpARM64MOVBstore: - width = 1 - case OpCopy: - continue // this was a store we merged earlier - default: - // Can't reorder with any other memory operations. - // (atomics, calls, ...) - continue memCheck - } - - // We only allow reordering with respect to other - // writes to the same pointer and aux, so we can - // compute the exact the aliasing relationship. - if w.Args[0] != ptr || w.Aux != aux { - continue memCheck - } - if overlap(w.AuxInt, width, off-info.width, info.width) { - // Aliases with slot before v's location. - lowerOk = false - } - if overlap(w.AuxInt, width, off+info.width, info.width) { - // Aliases with slot after v's location. - higherOk = false - } - if !higherOk && !lowerOk { - continue memCheck + for _, w := range memChain { + wWriteSize := storeWidth(w.Op) + if overlap(w.AuxInt, wWriteSize, v.AuxInt, writeSize) { + // Aliases with w's location. + // Flush the chain and start a new one with v. + flushMemChain() + break } } + + memChain = append(memChain, v) } + flushMemChain() } } diff --git a/src/cmd/compile/internal/ssa/poset.go b/src/cmd/compile/internal/ssa/poset.go index f4f75fbe09d8c7..7754f02aa7d01f 100644 --- a/src/cmd/compile/internal/ssa/poset.go +++ b/src/cmd/compile/internal/ssa/poset.go @@ -18,8 +18,20 @@ const uintSize = 32 << (^uint(0) >> 63) // 32 or 64 // bitset is a bit array for dense indexes. type bitset []uint +func computeBitsetSize(n int) int { + return (n + uintSize - 1) / uintSize +} + func newBitset(n int) bitset { - return make(bitset, (n+uintSize-1)/uintSize) + return make(bitset, computeBitsetSize(n)) +} + +func (c *Cache) allocBitset(n int) bitset { + return bitset(c.allocUintSlice(computeBitsetSize(n))) +} + +func (c *Cache) freeBitset(bs bitset) { + c.freeUintSlice([]uint(bs)) } func (bs bitset) Reset() { diff --git a/src/cmd/compile/internal/ssa/prove.go b/src/cmd/compile/internal/ssa/prove.go index c9bce23b286476..49925904792531 100644 --- a/src/cmd/compile/internal/ssa/prove.go +++ b/src/cmd/compile/internal/ssa/prove.go @@ -7,9 +7,12 @@ package ssa import ( "cmd/compile/internal/types" "cmd/internal/src" + "cmp" "fmt" "math" "math/bits" + "slices" + "strings" ) type branch int @@ -130,7 +133,7 @@ type limit struct { } func (l limit) String() string { - return fmt.Sprintf("sm,SM,um,UM=%d,%d,%d,%d", l.min, l.max, l.umin, l.umax) + return fmt.Sprintf("sm,SM=%d,%d um,UM=%d,%d", l.min, l.max, l.umin, l.umax) } func (l limit) intersect(l2 limit) limit { @@ -169,6 +172,9 @@ func (l limit) unsignedMinMax(minimum, maximum uint64) limit { func (l limit) nonzero() bool { return l.min > 0 || l.umin > 0 || l.max < 0 } +func (l limit) maybeZero() bool { + return !l.nonzero() +} func (l limit) nonnegative() bool { return l.min >= 0 } @@ -244,10 +250,72 @@ func fitsInBitsU(x uint64, b uint) bool { return x>>b == 0 } +func noLimit() limit { + return noLimitForBitsize(64) +} + +func noLimitForBitsize(bitsize uint) limit { + return limit{min: -(1 << (bitsize - 1)), max: 1<<(bitsize-1) - 1, umin: 0, umax: 1< 0 { + f.Cache.freeUintSlice(ft.reusedTopoSortScoresTable) + } } // addSlicesOfSameLen finds the slices that are in the same block and whose Op @@ -1439,9 +1571,8 @@ func getSliceInfo(vp *Value) (inf sliceInfo) { // its negation. If either leads to a contradiction, it can trim that // successor. func prove(f *Func) { - // Find induction variables. Currently, findIndVars - // is limited to one induction variable per block. - var indVars map[*Block]indVar + // Find induction variables. + var indVars map[*Block][]indVar for _, v := range findIndVar(f) { ind := v.ind if len(ind.Args) != 2 { @@ -1454,132 +1585,16 @@ func prove(f *Func) { nxt.Uses == 1) { // 1 used by induction // ind or nxt is used inside the loop, add it for the facts table if indVars == nil { - indVars = make(map[*Block]indVar) + indVars = make(map[*Block][]indVar) } - indVars[v.entry] = v + indVars[v.entry] = append(indVars[v.entry], v) continue } else { // Since this induction variable is not used for anything but counting the iterations, // no point in putting it into the facts table. } - // try to rewrite to a downward counting loop checking against start if the - // loop body does not depend on ind or nxt and end is known before the loop. - // This reduces pressure on the register allocator because this does not need - // to use end on each iteration anymore. We compare against the start constant instead. - // That means this code: - // - // loop: - // ind = (Phi (Const [x]) nxt), - // if ind < end - // then goto enter_loop - // else goto exit_loop - // - // enter_loop: - // do something without using ind nor nxt - // nxt = inc + ind - // goto loop - // - // exit_loop: - // - // is rewritten to: - // - // loop: - // ind = (Phi end nxt) - // if (Const [x]) < ind - // then goto enter_loop - // else goto exit_loop - // - // enter_loop: - // do something without using ind nor nxt - // nxt = ind - inc - // goto loop - // - // exit_loop: - // - // this is better because it only requires to keep ind then nxt alive while looping, - // while the original form keeps ind then nxt and end alive - start, end := v.min, v.max - if v.flags&indVarCountDown != 0 { - start, end = end, start - } - - if !start.isGenericIntConst() { - // if start is not a constant we would be winning nothing from inverting the loop - continue - } - if end.isGenericIntConst() { - // TODO: if both start and end are constants we should rewrite such that the comparison - // is against zero and nxt is ++ or -- operation - // That means: - // for i := 2; i < 11; i += 2 { - // should be rewritten to: - // for i := 5; 0 < i; i-- { - continue - } - - if end.Block == ind.Block { - // we can't rewrite loops where the condition depends on the loop body - // this simple check is forced to work because if this is true a Phi in ind.Block must exist - continue - } - - check := ind.Block.Controls[0] - // invert the check - check.Args[0], check.Args[1] = check.Args[1], check.Args[0] - - // swap start and end in the loop - for i, v := range check.Args { - if v != end { - continue - } - - check.SetArg(i, start) - goto replacedEnd - } - panic(fmt.Sprintf("unreachable, ind: %v, start: %v, end: %v", ind, start, end)) - replacedEnd: - - for i, v := range ind.Args { - if v != start { - continue - } - - ind.SetArg(i, end) - goto replacedStart - } - panic(fmt.Sprintf("unreachable, ind: %v, start: %v, end: %v", ind, start, end)) - replacedStart: - - if nxt.Args[0] != ind { - // unlike additions subtractions are not commutative so be sure we get it right - nxt.Args[0], nxt.Args[1] = nxt.Args[1], nxt.Args[0] - } - - switch nxt.Op { - case OpAdd8: - nxt.Op = OpSub8 - case OpAdd16: - nxt.Op = OpSub16 - case OpAdd32: - nxt.Op = OpSub32 - case OpAdd64: - nxt.Op = OpSub64 - case OpSub8: - nxt.Op = OpAdd8 - case OpSub16: - nxt.Op = OpAdd16 - case OpSub32: - nxt.Op = OpAdd32 - case OpSub64: - nxt.Op = OpAdd64 - default: - panic("unreachable") - } - - if f.pass.debug > 0 { - f.Warnl(ind.Pos, "Inverted loop iteration") - } + maybeRewriteLoopToDownwardCountingLoop(f, v) } ft := newFactsTable(f) @@ -1624,7 +1639,7 @@ func prove(f *Func) { type walkState int const ( descend walkState = iota - simplify + restore ) // work maintains the DFS stack. type bp struct { @@ -1662,7 +1677,7 @@ func prove(f *Func) { // Entering the block, add facts about the induction variable // that is bound to this block. - if iv, ok := indVars[node.block]; ok { + for _, iv := range indVars[node.block] { addIndVarRestrictions(ft, parent, iv) } @@ -1687,12 +1702,23 @@ func prove(f *Func) { // taking this branch. We'll restore // ft when we unwind. - // Add facts about the values in the current block. - addLocalFacts(ft, node.block) + ft.topoSortValuesInBlock(node.block) + + for _, v := range node.block.Values { + ft.flowLimit(v) + // constant fold arguments before addValueFact to avoid v's v.Args learned facts time traveling into v's arguments. + // in other words if v teaches us something about it's arguments, + // we can't use that to optimize v's arguments since v hasn't ran yet. + ft.constantFoldArguments(v) + ft.addValueFact(node.block, v) + ft.simplifyValue(node.block, v) + } + + ft.simplifyBlock(sdom, node.block) work = append(work, bp{ block: node.block, - state: simplify, + state: restore, }) for s := sdom.Child(node.block); s != nil; s = sdom.Sibling(s) { work = append(work, bp{ @@ -1701,8 +1727,7 @@ func prove(f *Func) { }) } - case simplify: - simplifyBlock(sdom, ft, node.block) + case restore: ft.restore() } } @@ -1733,20 +1758,19 @@ func initLimit(v *Value) limit { case OpConstNil: return limit{min: 0, max: 0, umin: 0, umax: 0} case OpAddr, OpLocalAddr: // TODO: others? - l := noLimit + l := noLimit() l.umin = 1 return l default: - return noLimit + return noLimit() } } if !v.Type.IsInteger() { - return noLimit + return noLimit() } // Default limits based on type. - bitsize := v.Type.Size() * 8 - lim := limit{min: -(1 << (bitsize - 1)), max: 1<<(bitsize-1) - 1, umin: 0, umax: 1<= 0 { + // Shift of negative makes a value closer to 0 (greater), + // so if a.min is negative, v.min is a.min>>b.min instead of a.min>>b.max, + // and similarly if a.max is negative, v.max is a.max>>b.max. + // Easier to compute min and max of both than to write sign logic. + vmin := min(a.min>>b.min, a.min>>b.max) + vmax := max(a.max>>b.min, a.max>>b.max) + ft.signedMinMax(v, vmin, vmax) + } + case OpRsh64Ux64, OpRsh64Ux32, OpRsh64Ux16, OpRsh64Ux8, + OpRsh32Ux64, OpRsh32Ux32, OpRsh32Ux16, OpRsh32Ux8, + OpRsh16Ux64, OpRsh16Ux32, OpRsh16Ux16, OpRsh16Ux8, + OpRsh8Ux64, OpRsh8Ux32, OpRsh8Ux16, OpRsh8Ux8: a := ft.limits[v.Args[0].ID] b := ft.limits[v.Args[1].ID] - // Underflow in the arithmetic below is ok, it gives to MaxUint64 which does nothing to the limit. - return ft.unsignedMax(v, min(a.umax, b.umax-1)) + if b.min >= 0 { + ft.unsignedMinMax(v, a.umin>>b.max, a.umax>>b.min) + } case OpDiv64, OpDiv32, OpDiv16, OpDiv8: a := ft.limits[v.Args[0].ID] b := ft.limits[v.Args[1].ID] @@ -1978,99 +1973,20 @@ func (ft *factsTable) flowLimit(v *Value) bool { case OpDiv64u, OpDiv32u, OpDiv16u, OpDiv8u: a := ft.limits[v.Args[0].ID] b := ft.limits[v.Args[1].ID] - lim := noLimit + lim := noLimit() if b.umax > 0 { lim = lim.unsignedMin(a.umin / b.umax) } if b.umin > 0 { lim = lim.unsignedMax(a.umax / b.umin) } - return ft.newLimit(v, lim) + ft.newLimit(v, lim) + case OpMod64, OpMod32, OpMod16, OpMod8: + ft.modLimit(true, v, v.Args[0], v.Args[1]) + case OpMod64u, OpMod32u, OpMod16u, OpMod8u: + ft.modLimit(false, v, v.Args[0], v.Args[1]) case OpPhi: - { - // Work around for go.dev/issue/68857, look for min(x, y) and max(x, y). - b := v.Block - if len(b.Preds) != 2 { - goto notMinNorMax - } - // FIXME: this code searches for the following losange pattern - // because that what ssagen produce for min and max builtins: - // conditionBlock → (firstBlock, secondBlock) → v.Block - // there are three non losange equivalent constructions - // we could match for, but I didn't bother: - // conditionBlock → (v.Block, secondBlock → v.Block) - // conditionBlock → (firstBlock → v.Block, v.Block) - // conditionBlock → (v.Block, v.Block) - firstBlock, secondBlock := b.Preds[0].b, b.Preds[1].b - if firstBlock.Kind != BlockPlain || secondBlock.Kind != BlockPlain { - goto notMinNorMax - } - if len(firstBlock.Preds) != 1 || len(secondBlock.Preds) != 1 { - goto notMinNorMax - } - conditionBlock := firstBlock.Preds[0].b - if conditionBlock != secondBlock.Preds[0].b { - goto notMinNorMax - } - if conditionBlock.Kind != BlockIf { - goto notMinNorMax - } - - less := conditionBlock.Controls[0] - var unsigned bool - switch less.Op { - case OpLess64U, OpLess32U, OpLess16U, OpLess8U, - OpLeq64U, OpLeq32U, OpLeq16U, OpLeq8U: - unsigned = true - case OpLess64, OpLess32, OpLess16, OpLess8, - OpLeq64, OpLeq32, OpLeq16, OpLeq8: - default: - goto notMinNorMax - } - small, big := less.Args[0], less.Args[1] - truev, falsev := v.Args[0], v.Args[1] - if conditionBlock.Succs[0].b == secondBlock { - truev, falsev = falsev, truev - } - - bigl, smalll := ft.limits[big.ID], ft.limits[small.ID] - if truev == big { - if falsev == small { - // v := big if small <¿=? big else small - if unsigned { - maximum := max(bigl.umax, smalll.umax) - minimum := max(bigl.umin, smalll.umin) - return ft.unsignedMinMax(v, minimum, maximum) - } else { - maximum := max(bigl.max, smalll.max) - minimum := max(bigl.min, smalll.min) - return ft.signedMinMax(v, minimum, maximum) - } - } else { - goto notMinNorMax - } - } else if truev == small { - if falsev == big { - // v := small if small <¿=? big else big - if unsigned { - maximum := min(bigl.umax, smalll.umax) - minimum := min(bigl.umin, smalll.umin) - return ft.unsignedMinMax(v, minimum, maximum) - } else { - maximum := min(bigl.max, smalll.max) - minimum := min(bigl.min, smalll.min) - return ft.signedMinMax(v, minimum, maximum) - } - } else { - goto notMinNorMax - } - } else { - goto notMinNorMax - } - } - notMinNorMax: - // Compute the union of all the input phis. // Often this will convey no information, because the block // is not dominated by its predecessors and hence the @@ -2088,35 +2004,8 @@ func (ft *factsTable) flowLimit(v *Value) bool { l.umin = min(l.umin, l2.umin) l.umax = max(l.umax, l2.umax) } - return ft.newLimit(v, l) - } - return false -} - -// See if we can get any facts because v is the result of signed mod by a constant. -// The mod operation has already been rewritten, so we have to try and reconstruct it. -// -// x % d -// -// is rewritten as -// -// x - (x / d) * d -// -// furthermore, the divide itself gets rewritten. If d is a power of 2 (d == 1<> k) << k -// = (x + adj) & (-1<= slicelen - index >= K // -// Note that "index" is not useed for indexing in this pattern, but +// Note that "index" is not used for indexing in this pattern, but // in the motivating example (chunked slice iteration) it is. -func (ft *factsTable) detectSliceLenRelation(v *Value) (inferred bool) { +func (ft *factsTable) detectSliceLenRelation(v *Value) { if v.Op != OpSub64 { - return false + return } - if !(v.Args[0].Op == OpSliceLen || v.Args[0].Op == OpSliceCap) { - return false + if !(v.Args[0].Op == OpSliceLen || v.Args[0].Op == OpStringLen || v.Args[0].Op == OpSliceCap) { + return } - slice := v.Args[0].Args[0] index := v.Args[1] + if !ft.isNonNegative(index) { + return + } + slice := v.Args[0].Args[0] for o := ft.orderings[index.ID]; o != nil; o = o.next { if o.d != signed { @@ -2154,10 +2046,13 @@ func (ft *factsTable) detectSliceLenRelation(v *Value) (inferred bool) { continue } var lenOffset *Value - if bound := ow.Args[0]; bound.Op == OpSliceLen && bound.Args[0] == slice { + if bound := ow.Args[0]; (bound.Op == OpSliceLen || bound.Op == OpStringLen) && bound.Args[0] == slice { lenOffset = ow.Args[1] - } else if bound := ow.Args[1]; bound.Op == OpSliceLen && bound.Args[0] == slice { - lenOffset = ow.Args[0] + } else if bound := ow.Args[1]; (bound.Op == OpSliceLen || bound.Op == OpStringLen) && bound.Args[0] == slice { + // Do not infer K - slicelen, see issue #76709. + if ow.Op == OpAdd64 { + lenOffset = ow.Args[0] + } } if lenOffset == nil || lenOffset.Op != OpConst64 { continue @@ -2175,107 +2070,136 @@ func (ft *factsTable) detectSliceLenRelation(v *Value) (inferred bool) { if K < 0 { // We hate thinking about overflow continue } - inferred = inferred || ft.signedMin(v, K) + ft.signedMin(v, K) } - return inferred } -func (ft *factsTable) detectSignedModByPowerOfTwo(v *Value) bool { - // We're looking for: - // - // x % d == - // x - (x / d) * d - // - // which for d a power of 2, d == 1<>(w-1))>>>(w-k)) & (-1<= 1 in the signed domain? + var vSignedMinOne bool + + // Signed optimizations + if _, ok := safeSub(xLim.min, yLim.max, width); ok { + // Large abs negative y can also overflow + if _, ok := safeSub(xLim.max, yLim.min, width); ok { + // x-y won't overflow + + // Subtracting a positive non-zero number only makes + // things smaller. If it's positive or zero, it might + // also do nothing (x-0 == v). + if yLim.min > 0 { + ft.update(v.Block, v, x, signed, lt) + } else if yLim.min == 0 { + ft.update(v.Block, v, x, signed, lt|eq) + } + + // Subtracting a number from a bigger one + // can't go below 1. If the numbers might be + // equal, then it can't go below 0. + // + // This requires the overflow checks because + // large negative y can cause an overflow. + if ft.orderS.Ordered(y, x) { + ft.signedMin(v, 1) + vSignedMinOne = true + } else if ft.orderS.OrderedOrEqual(y, x) { + ft.setNonNegative(v) + } + } + } + + // Unsigned optimizations + if _, ok := safeSubU(xLim.umin, yLim.umax, width); ok { + if yLim.umin > 0 { + ft.update(v.Block, v, x, unsigned, lt) + } else { + ft.update(v.Block, v, x, unsigned, lt|eq) + } + } + + // Proving v >= 1 in the signed domain automatically + // proves it in the unsigned domain, so we can skip it. // - // w = bit width of x. - // (>> = signed shift, >>> = unsigned shift). - // See ./_gen/generic.rules, search for "Signed divide by power of 2". + // We don't need overflow checks here, since if y < x, + // then x-y can never overflow for uint. + if !vSignedMinOne && ft.orderU.Ordered(y, x) { + ft.unsignedMin(v, 1) + } +} - var w int64 - var addOp, andOp, constOp, sshiftOp, ushiftOp Op +// x%d has been rewritten to x - (x/d)*d. +func (ft *factsTable) detectMod(v *Value) { + var opDiv, opDivU, opMul, opConst Op switch v.Op { case OpSub64: - w = 64 - addOp = OpAdd64 - andOp = OpAnd64 - constOp = OpConst64 - sshiftOp = OpRsh64x64 - ushiftOp = OpRsh64Ux64 + opDiv = OpDiv64 + opDivU = OpDiv64u + opMul = OpMul64 + opConst = OpConst64 case OpSub32: - w = 32 - addOp = OpAdd32 - andOp = OpAnd32 - constOp = OpConst32 - sshiftOp = OpRsh32x64 - ushiftOp = OpRsh32Ux64 + opDiv = OpDiv32 + opDivU = OpDiv32u + opMul = OpMul32 + opConst = OpConst32 case OpSub16: - w = 16 - addOp = OpAdd16 - andOp = OpAnd16 - constOp = OpConst16 - sshiftOp = OpRsh16x64 - ushiftOp = OpRsh16Ux64 + opDiv = OpDiv16 + opDivU = OpDiv16u + opMul = OpMul16 + opConst = OpConst16 case OpSub8: - w = 8 - addOp = OpAdd8 - andOp = OpAnd8 - constOp = OpConst8 - sshiftOp = OpRsh8x64 - ushiftOp = OpRsh8Ux64 - default: - return false + opDiv = OpDiv8 + opDivU = OpDiv8u + opMul = OpMul8 + opConst = OpConst8 } - x := v.Args[0] - and := v.Args[1] - if and.Op != andOp { - return false - } - var add, mask *Value - if and.Args[0].Op == addOp && and.Args[1].Op == constOp { - add = and.Args[0] - mask = and.Args[1] - } else if and.Args[1].Op == addOp && and.Args[0].Op == constOp { - add = and.Args[1] - mask = and.Args[0] - } else { - return false - } - var ushift *Value - if add.Args[0] == x { - ushift = add.Args[1] - } else if add.Args[1] == x { - ushift = add.Args[0] - } else { - return false - } - if ushift.Op != ushiftOp { - return false - } - if ushift.Args[1].Op != OpConst64 { - return false - } - k := w - ushift.Args[1].AuxInt // Now we know k! - d := int64(1) << k // divisor - sshift := ushift.Args[0] - if sshift.Op != sshiftOp { - return false - } - if sshift.Args[0] != x { - return false + mul := v.Args[1] + if mul.Op != opMul { + return } - if sshift.Args[1].Op != OpConst64 || sshift.Args[1].AuxInt != w-1 { - return false + div, con := mul.Args[0], mul.Args[1] + if div.Op == opConst { + div, con = con, div } - if mask.AuxInt != -d { - return false + if con.Op != opConst || (div.Op != opDiv && div.Op != opDivU) || div.Args[0] != v.Args[0] || div.Args[1].Op != opConst || div.Args[1].AuxInt != con.AuxInt { + return } + ft.modLimit(div.Op == opDiv, v, v.Args[0], con) +} - // All looks ok. x % d is at most +/- d-1. - return ft.signedMinMax(v, -d+1, d-1) +// modLimit sets v with facts derived from v = p % q. +func (ft *factsTable) modLimit(signed bool, v, p, q *Value) { + a := ft.limits[p.ID] + b := ft.limits[q.ID] + if signed { + if a.min < 0 && b.min > 0 { + ft.signedMinMax(v, -(b.max - 1), b.max-1) + return + } + if !(a.nonnegative() && b.nonnegative()) { + // TODO: we could handle signed limits but I didn't bother. + return + } + if a.min >= 0 && b.min > 0 { + ft.setNonNegative(v) + } + } + // Underflow in the arithmetic below is ok, it gives to MaxUint64 which does nothing to the limit. + ft.unsignedMax(v, min(a.umax, b.umax-1)) } // getBranch returns the range restrictions added by p @@ -2412,7 +2336,7 @@ func unsignedSubUnderflows(a, b uint64) bool { // iteration where the index is not directly compared to the length. // if isReslice, then delta can be equal to K. func checkForChunkedIndexBounds(ft *factsTable, b *Block, index, bound *Value, isReslice bool) bool { - if bound.Op != OpSliceLen && bound.Op != OpSliceCap { + if bound.Op != OpSliceLen && bound.Op != OpStringLen && bound.Op != OpSliceCap { return false } @@ -2447,9 +2371,9 @@ func checkForChunkedIndexBounds(ft *factsTable, b *Block, index, bound *Value, i } if ow := o.w; ow.Op == OpAdd64 { var lenOffset *Value - if bound := ow.Args[0]; bound.Op == OpSliceLen && bound.Args[0] == slice { + if bound := ow.Args[0]; (bound.Op == OpSliceLen || bound.Op == OpStringLen) && bound.Args[0] == slice { lenOffset = ow.Args[1] - } else if bound := ow.Args[1]; bound.Op == OpSliceLen && bound.Args[0] == slice { + } else if bound := ow.Args[1]; (bound.Op == OpSliceLen || bound.Op == OpStringLen) && bound.Args[0] == slice { lenOffset = ow.Args[0] } if lenOffset == nil || lenOffset.Op != OpConst64 { @@ -2477,134 +2401,172 @@ func checkForChunkedIndexBounds(ft *factsTable, b *Block, index, bound *Value, i return false } -func addLocalFacts(ft *factsTable, b *Block) { - // Propagate constant ranges among values in this block. - // We do this before the second loop so that we have the - // most up-to-date constant bounds for isNonNegative calls. - for { - changed := false - for _, v := range b.Values { - changed = ft.flowLimit(v) || changed +func (ft *factsTable) addValueFact(b *Block, v *Value) { + switch v.Op { + case OpAdd64, OpAdd32, OpAdd16, OpAdd8: + x := ft.limits[v.Args[0].ID] + y := ft.limits[v.Args[1].ID] + if !unsignedAddOverflows(x.umax, y.umax, v.Type) { + r := gt + if x.maybeZero() { + r |= eq + } + ft.update(b, v, v.Args[1], unsigned, r) + r = gt + if y.maybeZero() { + r |= eq + } + ft.update(b, v, v.Args[0], unsigned, r) } - if !changed { - break + if x.min >= 0 && !signedAddOverflowsOrUnderflows(x.max, y.max, v.Type) { + r := gt + if x.maybeZero() { + r |= eq + } + ft.update(b, v, v.Args[1], signed, r) } - } - - // Add facts about individual operations. - for _, v := range b.Values { - // FIXME(go.dev/issue/68857): this loop only set up limits properly when b.Values is in topological order. - // flowLimit can also depend on limits given by this loop which right now is not handled. - switch v.Op { - case OpAdd64, OpAdd32, OpAdd16, OpAdd8: - x := ft.limits[v.Args[0].ID] - y := ft.limits[v.Args[1].ID] - if !unsignedAddOverflows(x.umax, y.umax, v.Type) { - r := gt - if !x.nonzero() { - r |= eq - } - ft.update(b, v, v.Args[1], unsigned, r) - r = gt - if !y.nonzero() { - r |= eq - } - ft.update(b, v, v.Args[0], unsigned, r) + if y.min >= 0 && !signedAddOverflowsOrUnderflows(x.max, y.max, v.Type) { + r := gt + if y.maybeZero() { + r |= eq } - if x.min >= 0 && !signedAddOverflowsOrUnderflows(x.max, y.max, v.Type) { - r := gt - if !x.nonzero() { - r |= eq - } - ft.update(b, v, v.Args[1], signed, r) + ft.update(b, v, v.Args[0], signed, r) + } + if x.max <= 0 && !signedAddOverflowsOrUnderflows(x.min, y.min, v.Type) { + r := lt + if x.maybeZero() { + r |= eq } - if y.min >= 0 && !signedAddOverflowsOrUnderflows(x.max, y.max, v.Type) { - r := gt - if !y.nonzero() { - r |= eq - } - ft.update(b, v, v.Args[0], signed, r) + ft.update(b, v, v.Args[1], signed, r) + } + if y.max <= 0 && !signedAddOverflowsOrUnderflows(x.min, y.min, v.Type) { + r := lt + if y.maybeZero() { + r |= eq } - if x.max <= 0 && !signedAddOverflowsOrUnderflows(x.min, y.min, v.Type) { - r := lt - if !x.nonzero() { - r |= eq - } - ft.update(b, v, v.Args[1], signed, r) + ft.update(b, v, v.Args[0], signed, r) + } + case OpSub64, OpSub32, OpSub16, OpSub8: + x := ft.limits[v.Args[0].ID] + y := ft.limits[v.Args[1].ID] + if !unsignedSubUnderflows(x.umin, y.umax) { + r := lt + if y.maybeZero() { + r |= eq } - if y.max <= 0 && !signedAddOverflowsOrUnderflows(x.min, y.min, v.Type) { - r := lt - if !y.nonzero() { - r |= eq - } - ft.update(b, v, v.Args[0], signed, r) - } - case OpSub64, OpSub32, OpSub16, OpSub8: - x := ft.limits[v.Args[0].ID] - y := ft.limits[v.Args[1].ID] - if !unsignedSubUnderflows(x.umin, y.umax) { - r := lt - if !y.nonzero() { - r |= eq + ft.update(b, v, v.Args[0], unsigned, r) + } + // FIXME: we could also do signed facts but the overflow checks are much trickier and I don't need it yet. + case OpAnd64, OpAnd32, OpAnd16, OpAnd8: + ft.update(b, v, v.Args[0], unsigned, lt|eq) + ft.update(b, v, v.Args[1], unsigned, lt|eq) + if ft.isNonNegative(v.Args[0]) { + ft.update(b, v, v.Args[0], signed, lt|eq) + } + if ft.isNonNegative(v.Args[1]) { + ft.update(b, v, v.Args[1], signed, lt|eq) + } + case OpOr64, OpOr32, OpOr16, OpOr8: + // TODO: investigate how to always add facts without much slowdown, see issue #57959 + //ft.update(b, v, v.Args[0], unsigned, gt|eq) + //ft.update(b, v, v.Args[1], unsigned, gt|eq) + case OpDiv64, OpDiv32, OpDiv16, OpDiv8: + if !ft.isNonNegative(v.Args[1]) { + break + } + fallthrough + case OpRsh8x64, OpRsh8x32, OpRsh8x16, OpRsh8x8, + OpRsh16x64, OpRsh16x32, OpRsh16x16, OpRsh16x8, + OpRsh32x64, OpRsh32x32, OpRsh32x16, OpRsh32x8, + OpRsh64x64, OpRsh64x32, OpRsh64x16, OpRsh64x8: + if !ft.isNonNegative(v.Args[0]) { + break + } + fallthrough + case OpDiv64u, OpDiv32u, OpDiv16u, OpDiv8u, + OpRsh8Ux64, OpRsh8Ux32, OpRsh8Ux16, OpRsh8Ux8, + OpRsh16Ux64, OpRsh16Ux32, OpRsh16Ux16, OpRsh16Ux8, + OpRsh32Ux64, OpRsh32Ux32, OpRsh32Ux16, OpRsh32Ux8, + OpRsh64Ux64, OpRsh64Ux32, OpRsh64Ux16, OpRsh64Ux8: + switch add := v.Args[0]; add.Op { + // round-up division pattern; given: + // v = (x + y) / z + // if y < z then v <= x + case OpAdd64, OpAdd32, OpAdd16, OpAdd8: + z := v.Args[1] + zl := ft.limits[z.ID] + var uminDivisor uint64 + switch v.Op { + case OpDiv64u, OpDiv32u, OpDiv16u, OpDiv8u, + OpDiv64, OpDiv32, OpDiv16, OpDiv8: + uminDivisor = zl.umin + case OpRsh8Ux64, OpRsh8Ux32, OpRsh8Ux16, OpRsh8Ux8, + OpRsh16Ux64, OpRsh16Ux32, OpRsh16Ux16, OpRsh16Ux8, + OpRsh32Ux64, OpRsh32Ux32, OpRsh32Ux16, OpRsh32Ux8, + OpRsh64Ux64, OpRsh64Ux32, OpRsh64Ux16, OpRsh64Ux8, + OpRsh8x64, OpRsh8x32, OpRsh8x16, OpRsh8x8, + OpRsh16x64, OpRsh16x32, OpRsh16x16, OpRsh16x8, + OpRsh32x64, OpRsh32x32, OpRsh32x16, OpRsh32x8, + OpRsh64x64, OpRsh64x32, OpRsh64x16, OpRsh64x8: + uminDivisor = 1 << zl.umin + default: + panic("unreachable") + } + + x := add.Args[0] + xl := ft.limits[x.ID] + y := add.Args[1] + yl := ft.limits[y.ID] + if !unsignedAddOverflows(xl.umax, yl.umax, add.Type) { + if xl.umax < uminDivisor { + ft.update(b, v, y, unsigned, lt|eq) } - ft.update(b, v, v.Args[0], unsigned, r) - } - // FIXME: we could also do signed facts but the overflow checks are much trickier and I don't need it yet. - case OpAnd64, OpAnd32, OpAnd16, OpAnd8: - ft.update(b, v, v.Args[0], unsigned, lt|eq) - ft.update(b, v, v.Args[1], unsigned, lt|eq) - if ft.isNonNegative(v.Args[0]) { - ft.update(b, v, v.Args[0], signed, lt|eq) - } - if ft.isNonNegative(v.Args[1]) { - ft.update(b, v, v.Args[1], signed, lt|eq) - } - case OpOr64, OpOr32, OpOr16, OpOr8: - // TODO: investigate how to always add facts without much slowdown, see issue #57959 - //ft.update(b, v, v.Args[0], unsigned, gt|eq) - //ft.update(b, v, v.Args[1], unsigned, gt|eq) - case OpDiv64u, OpDiv32u, OpDiv16u, OpDiv8u, - OpRsh8Ux64, OpRsh8Ux32, OpRsh8Ux16, OpRsh8Ux8, - OpRsh16Ux64, OpRsh16Ux32, OpRsh16Ux16, OpRsh16Ux8, - OpRsh32Ux64, OpRsh32Ux32, OpRsh32Ux16, OpRsh32Ux8, - OpRsh64Ux64, OpRsh64Ux32, OpRsh64Ux16, OpRsh64Ux8: - ft.update(b, v, v.Args[0], unsigned, lt|eq) - case OpMod64u, OpMod32u, OpMod16u, OpMod8u: - ft.update(b, v, v.Args[0], unsigned, lt|eq) - // Note: we have to be careful that this doesn't imply - // that the modulus is >0, which isn't true until *after* - // the mod instruction executes (and thus panics if the - // modulus is 0). See issue 67625. - ft.update(b, v, v.Args[1], unsigned, lt) - case OpStringLen: - if v.Args[0].Op == OpStringMake { - ft.update(b, v, v.Args[0].Args[1], signed, eq) - } - case OpSliceLen: - if v.Args[0].Op == OpSliceMake { - ft.update(b, v, v.Args[0].Args[1], signed, eq) - } - case OpSliceCap: - if v.Args[0].Op == OpSliceMake { - ft.update(b, v, v.Args[0].Args[2], signed, eq) - } - case OpIsInBounds: - if checkForChunkedIndexBounds(ft, b, v.Args[0], v.Args[1], false) { - if b.Func.pass.debug > 0 { - b.Func.Warnl(v.Pos, "Proved %s for blocked indexing", v.Op) + if yl.umax < uminDivisor { + ft.update(b, v, x, unsigned, lt|eq) } - ft.booleanTrue(v) } - case OpIsSliceInBounds: - if checkForChunkedIndexBounds(ft, b, v.Args[0], v.Args[1], true) { - if b.Func.pass.debug > 0 { - b.Func.Warnl(v.Pos, "Proved %s for blocked reslicing", v.Op) - } - ft.booleanTrue(v) + } + ft.update(b, v, v.Args[0], unsigned, lt|eq) + case OpMod64, OpMod32, OpMod16, OpMod8: + if !ft.isNonNegative(v.Args[0]) || !ft.isNonNegative(v.Args[1]) { + break + } + fallthrough + case OpMod64u, OpMod32u, OpMod16u, OpMod8u: + ft.update(b, v, v.Args[0], unsigned, lt|eq) + // Note: we have to be careful that this doesn't imply + // that the modulus is >0, which isn't true until *after* + // the mod instruction executes (and thus panics if the + // modulus is 0). See issue 67625. + ft.update(b, v, v.Args[1], unsigned, lt) + case OpStringLen: + if v.Args[0].Op == OpStringMake { + ft.update(b, v, v.Args[0].Args[1], signed, eq) + } + case OpSliceLen: + if v.Args[0].Op == OpSliceMake { + ft.update(b, v, v.Args[0].Args[1], signed, eq) + } + case OpSliceCap: + if v.Args[0].Op == OpSliceMake { + ft.update(b, v, v.Args[0].Args[2], signed, eq) + } + case OpIsInBounds: + if checkForChunkedIndexBounds(ft, b, v.Args[0], v.Args[1], false) { + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Proved %s for blocked indexing", v.Op) + } + ft.booleanTrue(v) + } + case OpIsSliceInBounds: + if checkForChunkedIndexBounds(ft, b, v.Args[0], v.Args[1], true) { + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Proved %s for blocked reslicing", v.Op) } - case OpPhi: - addLocalFactsPhi(ft, v) + ft.booleanTrue(v) } + case OpPhi: + addLocalFactsPhi(ft, v) } } @@ -2683,189 +2645,377 @@ func addLocalFactsPhi(ft *factsTable, v *Value) { ft.update(b, v, y, dom, rel) } -var ctzNonZeroOp = map[Op]Op{OpCtz8: OpCtz8NonZero, OpCtz16: OpCtz16NonZero, OpCtz32: OpCtz32NonZero, OpCtz64: OpCtz64NonZero} +var ctzNonZeroOp = map[Op]Op{ + OpCtz8: OpCtz8NonZero, + OpCtz16: OpCtz16NonZero, + OpCtz32: OpCtz32NonZero, + OpCtz64: OpCtz64NonZero, +} var mostNegativeDividend = map[Op]int64{ OpDiv16: -1 << 15, OpMod16: -1 << 15, OpDiv32: -1 << 31, OpMod32: -1 << 31, OpDiv64: -1 << 63, - OpMod64: -1 << 63} - -// simplifyBlock simplifies some constant values in b and evaluates -// branches to non-uniquely dominated successors of b. -func simplifyBlock(sdom SparseTree, ft *factsTable, b *Block) { - for _, v := range b.Values { - switch v.Op { - case OpSlicemask: - // Replace OpSlicemask operations in b with constants where possible. - cap := v.Args[0] - x, delta := isConstDelta(cap) - if x != nil { - // slicemask(x + y) - // if x is larger than -y (y is negative), then slicemask is -1. - lim := ft.limits[x.ID] - if lim.umin > uint64(-delta) { - if cap.Op == OpAdd64 { - v.reset(OpConst64) - } else { - v.reset(OpConst32) - } - if b.Func.pass.debug > 0 { - b.Func.Warnl(v.Pos, "Proved slicemask not needed") - } - v.AuxInt = -1 - } - break - } - lim := ft.limits[cap.ID] - if lim.umin > 0 { - if cap.Type.Size() == 8 { + OpMod64: -1 << 63, +} +var unsignedOp = map[Op]Op{ + OpDiv8: OpDiv8u, + OpDiv16: OpDiv16u, + OpDiv32: OpDiv32u, + OpDiv64: OpDiv64u, + OpMod8: OpMod8u, + OpMod16: OpMod16u, + OpMod32: OpMod32u, + OpMod64: OpMod64u, + OpRsh8x8: OpRsh8Ux8, + OpRsh8x16: OpRsh8Ux16, + OpRsh8x32: OpRsh8Ux32, + OpRsh8x64: OpRsh8Ux64, + OpRsh16x8: OpRsh16Ux8, + OpRsh16x16: OpRsh16Ux16, + OpRsh16x32: OpRsh16Ux32, + OpRsh16x64: OpRsh16Ux64, + OpRsh32x8: OpRsh32Ux8, + OpRsh32x16: OpRsh32Ux16, + OpRsh32x32: OpRsh32Ux32, + OpRsh32x64: OpRsh32Ux64, + OpRsh64x8: OpRsh64Ux8, + OpRsh64x16: OpRsh64Ux16, + OpRsh64x32: OpRsh64Ux32, + OpRsh64x64: OpRsh64Ux64, +} + +var bytesizeToConst = [...]Op{ + 8 / 8: OpConst8, + 16 / 8: OpConst16, + 32 / 8: OpConst32, + 64 / 8: OpConst64, +} +var bytesizeToNeq = [...]Op{ + 8 / 8: OpNeq8, + 16 / 8: OpNeq16, + 32 / 8: OpNeq32, + 64 / 8: OpNeq64, +} +var bytesizeToAnd = [...]Op{ + 8 / 8: OpAnd8, + 16 / 8: OpAnd16, + 32 / 8: OpAnd32, + 64 / 8: OpAnd64, +} + +var invertEqNeqOp = map[Op]Op{ + OpEq8: OpNeq8, + OpNeq8: OpEq8, + + OpEq16: OpNeq16, + OpNeq16: OpEq16, + + OpEq32: OpNeq32, + OpNeq32: OpEq32, + + OpEq64: OpNeq64, + OpNeq64: OpEq64, +} + +func (ft *factsTable) simplifyValue(b *Block, v *Value) { + switch v.Op { + case OpStaticLECall: + if b.Func.pass.debug > 0 && len(v.Args) == 2 { + fn := auxToCall(v.Aux).Fn + if fn != nil && strings.Contains(fn.String(), "prove") { + // Print bounds of any argument to single-arg function with "prove" in name, + // for debugging and especially for test/prove.go. + // (v.Args[1] is mem). + x := v.Args[0] + b.Func.Warnl(v.Pos, "Proved %v (%v)", ft.limits[x.ID], x) + } + } + case OpSlicemask: + // Replace OpSlicemask operations in b with constants where possible. + cap := v.Args[0] + x, delta := isConstDelta(cap) + if x != nil { + // slicemask(x + y) + // if x is larger than -y (y is negative), then slicemask is -1. + lim := ft.limits[x.ID] + if lim.umin > uint64(-delta) { + if v.Type.Size() == 8 { v.reset(OpConst64) } else { v.reset(OpConst32) } if b.Func.pass.debug > 0 { - b.Func.Warnl(v.Pos, "Proved slicemask not needed (by limit)") + b.Func.Warnl(v.Pos, "Proved slicemask not needed") } v.AuxInt = -1 } + break + } + lim := ft.limits[cap.ID] + if lim.umin > 0 { + if v.Type.Size() == 8 { + v.reset(OpConst64) + } else { + v.reset(OpConst32) + } + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Proved slicemask not needed (by limit)") + } + v.AuxInt = -1 + } - case OpCtz8, OpCtz16, OpCtz32, OpCtz64: - // On some architectures, notably amd64, we can generate much better - // code for CtzNN if we know that the argument is non-zero. - // Capture that information here for use in arch-specific optimizations. - x := v.Args[0] - lim := ft.limits[x.ID] - if lim.umin > 0 || lim.min > 0 || lim.max < 0 { - if b.Func.pass.debug > 0 { - b.Func.Warnl(v.Pos, "Proved %v non-zero", v.Op) - } - v.Op = ctzNonZeroOp[v.Op] - } - case OpRsh8x8, OpRsh8x16, OpRsh8x32, OpRsh8x64, - OpRsh16x8, OpRsh16x16, OpRsh16x32, OpRsh16x64, - OpRsh32x8, OpRsh32x16, OpRsh32x32, OpRsh32x64, - OpRsh64x8, OpRsh64x16, OpRsh64x32, OpRsh64x64: - // Check whether, for a >> b, we know that a is non-negative - // and b is all of a's bits except the MSB. If so, a is shifted to zero. - bits := 8 * v.Args[0].Type.Size() - if v.Args[1].isGenericIntConst() && v.Args[1].AuxInt >= bits-1 && ft.isNonNegative(v.Args[0]) { - if b.Func.pass.debug > 0 { - b.Func.Warnl(v.Pos, "Proved %v shifts to zero", v.Op) - } - switch bits { - case 64: - v.reset(OpConst64) - case 32: - v.reset(OpConst32) - case 16: - v.reset(OpConst16) - case 8: - v.reset(OpConst8) - default: - panic("unexpected integer size") - } - v.AuxInt = 0 - break // Be sure not to fallthrough - this is no longer OpRsh. + case OpCtz8, OpCtz16, OpCtz32, OpCtz64: + // On some architectures, notably amd64, we can generate much better + // code for CtzNN if we know that the argument is non-zero. + // Capture that information here for use in arch-specific optimizations. + x := v.Args[0] + lim := ft.limits[x.ID] + if lim.umin > 0 || lim.min > 0 || lim.max < 0 { + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Proved %v non-zero", v.Op) } - // If the Rsh hasn't been replaced with 0, still check if it is bounded. - fallthrough - case OpLsh8x8, OpLsh8x16, OpLsh8x32, OpLsh8x64, - OpLsh16x8, OpLsh16x16, OpLsh16x32, OpLsh16x64, - OpLsh32x8, OpLsh32x16, OpLsh32x32, OpLsh32x64, - OpLsh64x8, OpLsh64x16, OpLsh64x32, OpLsh64x64, - OpRsh8Ux8, OpRsh8Ux16, OpRsh8Ux32, OpRsh8Ux64, - OpRsh16Ux8, OpRsh16Ux16, OpRsh16Ux32, OpRsh16Ux64, - OpRsh32Ux8, OpRsh32Ux16, OpRsh32Ux32, OpRsh32Ux64, - OpRsh64Ux8, OpRsh64Ux16, OpRsh64Ux32, OpRsh64Ux64: - // Check whether, for a << b, we know that b - // is strictly less than the number of bits in a. - by := v.Args[1] - lim := ft.limits[by.ID] - bits := 8 * v.Args[0].Type.Size() - if lim.umax < uint64(bits) || (lim.max < bits && ft.isNonNegative(by)) { - v.AuxInt = 1 // see shiftIsBounded - if b.Func.pass.debug > 0 && !by.isGenericIntConst() { - b.Func.Warnl(v.Pos, "Proved %v bounded", v.Op) - } + v.Op = ctzNonZeroOp[v.Op] + } + case OpRsh8x8, OpRsh8x16, OpRsh8x32, OpRsh8x64, + OpRsh16x8, OpRsh16x16, OpRsh16x32, OpRsh16x64, + OpRsh32x8, OpRsh32x16, OpRsh32x32, OpRsh32x64, + OpRsh64x8, OpRsh64x16, OpRsh64x32, OpRsh64x64: + if ft.isNonNegative(v.Args[0]) { + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Proved %v is unsigned", v.Op) } - case OpDiv16, OpDiv32, OpDiv64, OpMod16, OpMod32, OpMod64: - // On amd64 and 386 fix-up code can be avoided if we know - // the divisor is not -1 or the dividend > MinIntNN. - // Don't modify AuxInt on other architectures, - // as that can interfere with CSE. + v.Op = unsignedOp[v.Op] + } + fallthrough + case OpLsh8x8, OpLsh8x16, OpLsh8x32, OpLsh8x64, + OpLsh16x8, OpLsh16x16, OpLsh16x32, OpLsh16x64, + OpLsh32x8, OpLsh32x16, OpLsh32x32, OpLsh32x64, + OpLsh64x8, OpLsh64x16, OpLsh64x32, OpLsh64x64, + OpRsh8Ux8, OpRsh8Ux16, OpRsh8Ux32, OpRsh8Ux64, + OpRsh16Ux8, OpRsh16Ux16, OpRsh16Ux32, OpRsh16Ux64, + OpRsh32Ux8, OpRsh32Ux16, OpRsh32Ux32, OpRsh32Ux64, + OpRsh64Ux8, OpRsh64Ux16, OpRsh64Ux32, OpRsh64Ux64: + // Check whether, for a << b, we know that b + // is strictly less than the number of bits in a. + by := v.Args[1] + lim := ft.limits[by.ID] + bits := 8 * v.Args[0].Type.Size() + if lim.umax < uint64(bits) || (lim.max < bits && ft.isNonNegative(by)) { + v.AuxInt = 1 // see shiftIsBounded + if b.Func.pass.debug > 0 && !by.isGenericIntConst() { + b.Func.Warnl(v.Pos, "Proved %v bounded", v.Op) + } + } + case OpDiv8, OpDiv16, OpDiv32, OpDiv64, OpMod8, OpMod16, OpMod32, OpMod64: + p, q := ft.limits[v.Args[0].ID], ft.limits[v.Args[1].ID] // p/q + if p.nonnegative() && q.nonnegative() { + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Proved %v is unsigned", v.Op) + } + v.Op = unsignedOp[v.Op] + v.AuxInt = 0 + break + } + // Fixup code can be avoided on x86 if we know + // the divisor is not -1 or the dividend > MinIntNN. + if v.Op != OpDiv8 && v.Op != OpMod8 && (q.max < -1 || q.min > -1 || p.min > mostNegativeDividend[v.Op]) { + // See DivisionNeedsFixUp in rewrite.go. + // v.AuxInt = 1 means we have proved that the divisor is not -1 + // or that the dividend is not the most negative integer, + // so we do not need to add fix-up code. + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Proved %v does not need fix-up", v.Op) + } + // Only usable on amd64 and 386, and only for ≥ 16-bit ops. + // Don't modify AuxInt on other architectures, as that can interfere with CSE. + // (Print the debug info above always, so that test/prove.go can be + // checked on non-x86 systems.) // TODO: add other architectures? - if b.Func.Config.arch != "386" && b.Func.Config.arch != "amd64" { + if b.Func.Config.arch == "386" || b.Func.Config.arch == "amd64" { + v.AuxInt = 1 + } + } + case OpMul64, OpMul32, OpMul16, OpMul8: + if vl := ft.limits[v.ID]; vl.min == vl.max || vl.umin == vl.umax { + // v is going to be constant folded away; don't "optimize" it. + break + } + x := v.Args[0] + xl := ft.limits[x.ID] + y := v.Args[1] + yl := ft.limits[y.ID] + if xl.umin == xl.umax && isPowerOfTwo(xl.umin) || + xl.min == xl.max && isPowerOfTwo(xl.min) || + yl.umin == yl.umax && isPowerOfTwo(yl.umin) || + yl.min == yl.max && isPowerOfTwo(yl.min) { + // 0,1 * a power of two is better done as a shift + break + } + switch xOne, yOne := xl.umax <= 1, yl.umax <= 1; { + case xOne && yOne: + v.Op = bytesizeToAnd[v.Type.Size()] + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Rewrote Mul %v into And", v) + } + case yOne && b.Func.Config.haveCondSelect: + x, y = y, x + fallthrough + case xOne && b.Func.Config.haveCondSelect: + if !canCondSelect(v, b.Func.Config.arch, nil) { break } - divr := v.Args[1] - divrLim := ft.limits[divr.ID] - divd := v.Args[0] - divdLim := ft.limits[divd.ID] - if divrLim.max < -1 || divrLim.min > -1 || divdLim.min > mostNegativeDividend[v.Op] { - // See DivisionNeedsFixUp in rewrite.go. - // v.AuxInt = 1 means we have proved both that the divisor is not -1 - // and that the dividend is not the most negative integer, - // so we do not need to add fix-up code. - v.AuxInt = 1 - if b.Func.pass.debug > 0 { - b.Func.Warnl(v.Pos, "Proved %v does not need fix-up", v.Op) - } + zero := b.Func.constVal(bytesizeToConst[v.Type.Size()], v.Type, 0, true) + ft.initLimitForNewValue(zero) + check := b.NewValue2(v.Pos, bytesizeToNeq[v.Type.Size()], types.Types[types.TBOOL], zero, x) + ft.initLimitForNewValue(check) + v.reset(OpCondSelect) + v.AddArg3(y, zero, check) + + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Rewrote Mul %v into CondSelect; %v is bool", v, x) + } + } + case OpEq64, OpEq32, OpEq16, OpEq8, + OpNeq64, OpNeq32, OpNeq16, OpNeq8: + // Canonicalize: + // [0,1] != 1 → [0,1] == 0 + // [0,1] == 1 → [0,1] != 0 + // Comparison with zero often encode smaller. + xPos, yPos := 0, 1 + x, y := v.Args[xPos], v.Args[yPos] + xl, yl := ft.limits[x.ID], ft.limits[y.ID] + xConst, xIsConst := xl.constValue() + yConst, yIsConst := yl.constValue() + switch { + case xIsConst && yIsConst: + case xIsConst: + xPos, yPos = yPos, xPos + x, y = y, x + xl, yl = yl, xl + xConst, yConst = yConst, xConst + fallthrough + case yIsConst: + if yConst != 1 || + xl.umax > 1 { + break + } + zero := b.Func.constVal(bytesizeToConst[x.Type.Size()], x.Type, 0, true) + ft.initLimitForNewValue(zero) + oldOp := v.Op + v.Op = invertEqNeqOp[v.Op] + v.SetArg(yPos, zero) + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Rewrote %v (%v) %v argument is boolean-like; rewrote to %v against 0", v, oldOp, x, v.Op) } } - // Fold provable constant results. - // Helps in cases where we reuse a value after branching on its equality. - for i, arg := range v.Args { - lim := ft.limits[arg.ID] - var constValue int64 - switch { - case lim.min == lim.max: - constValue = lim.min - case lim.umin == lim.umax: - constValue = int64(lim.umin) - default: - continue + case OpAnd64, OpAnd32, OpAnd16, OpAnd8: + x, y := v.Args[0], v.Args[1] + xl, yl := ft.limits[x.ID], ft.limits[y.ID] + xConst, xIsConst := xl.constValue() + yConst, yIsConst := yl.constValue() + // Remove no-op Ands + switch { + case xIsConst && yIsConst: + case xIsConst: + x, y = y, x + xl, yl = yl, xl + xConst, yConst = yConst, xConst + fallthrough + case yIsConst: + knownBits, fixedLen := xl.unsignedFixedLeadingBits() + varyingLen := 64 - fixedLen + wantBits := knownBits | (uint64(1)< 0 { + b.Func.Warnl(v.Pos, "Proved %v is a no-op %v", v, oldOp) } - typ := arg.Type - f := b.Func - var c *Value - switch { - case typ.IsBoolean(): - c = f.ConstBool(typ, constValue != 0) - case typ.IsInteger() && typ.Size() == 1: - c = f.ConstInt8(typ, int8(constValue)) - case typ.IsInteger() && typ.Size() == 2: - c = f.ConstInt16(typ, int16(constValue)) - case typ.IsInteger() && typ.Size() == 4: - c = f.ConstInt32(typ, int32(constValue)) - case typ.IsInteger() && typ.Size() == 8: - c = f.ConstInt64(typ, constValue) - case typ.IsPtrShaped(): - if constValue == 0 { - c = f.ConstNil(typ) - } else { - // Not sure how this might happen, but if it - // does, just skip it. - continue - } - default: + } + case OpOr64, OpOr32, OpOr16, OpOr8: + x, y := v.Args[0], v.Args[1] + xl, yl := ft.limits[x.ID], ft.limits[y.ID] + xConst, xIsConst := xl.constValue() + yConst, yIsConst := yl.constValue() + // Remove no-op Ors + switch { + case xIsConst && yIsConst: + case xIsConst: + x, y = y, x + xl, yl = yl, xl + xConst, yConst = yConst, xConst + fallthrough + case yIsConst: + wantBits, _ := xl.unsignedFixedLeadingBits() + // wantBits has the fixed bits and the worst case bits (unset) for the varying bits + // if after oring it with y it isn't modified we know the or is always a no-op. + if wantBits|uint64(yConst) != wantBits { + break + } + + oldOp := v.Op + v.copyOf(x) + if b.Func.pass.debug > 0 { + b.Func.Warnl(v.Pos, "Proved %v is a no-op %v", v, oldOp) + } + } + } +} + +func (ft *factsTable) constantFoldArguments(v *Value) { + for i, arg := range v.Args { + lim := ft.limits[arg.ID] + constValue, ok := lim.constValue() + if !ok { + continue + } + switch arg.Op { + case OpConst64, OpConst32, OpConst16, OpConst8, OpConstBool, OpConstNil: + continue + } + typ := arg.Type + f := v.Block.Func + var c *Value + switch { + case typ.IsBoolean(): + c = f.ConstBool(typ, constValue != 0) + case typ.IsInteger() && typ.Size() == 1: + c = f.ConstInt8(typ, int8(constValue)) + case typ.IsInteger() && typ.Size() == 2: + c = f.ConstInt16(typ, int16(constValue)) + case typ.IsInteger() && typ.Size() == 4: + c = f.ConstInt32(typ, int32(constValue)) + case typ.IsInteger() && typ.Size() == 8: + c = f.ConstInt64(typ, constValue) + case typ.IsPtrShaped(): + if constValue == 0 { + c = f.ConstNil(typ) + } else { // Not sure how this might happen, but if it // does, just skip it. continue } - v.SetArg(i, c) - ft.initLimitForNewValue(c) - if b.Func.pass.debug > 1 { - b.Func.Warnl(v.Pos, "Proved %v's arg %d (%v) is constant %d", v, i, arg, constValue) - } + default: + // Not sure how this might happen, but if it + // does, just skip it. + continue + } + v.SetArg(i, c) + ft.initLimitForNewValue(c) + if f.pass.debug > 1 { + f.Warnl(v.Pos, "Proved %v's arg %d (%v) is constant %d", v, i, arg, constValue) } } +} +func (ft *factsTable) simplifyBlock(sdom SparseTree, b *Block) { if b.Kind != BlockIf { return } @@ -2901,7 +3051,7 @@ func simplifyBlock(sdom SparseTree, ft *factsTable, b *Block) { func removeBranch(b *Block, branch branch) { c := b.Controls[0] - if b.Func.pass.debug > 0 { + if c != nil && b.Func.pass.debug > 0 { verb := "Proved" if branch == positive { verb = "Disproved" @@ -2973,3 +3123,55 @@ func isCleanExt(v *Value) bool { } return false } + +func getDependencyScore(scores []uint, v *Value) (score uint) { + if score = scores[v.ID]; score != 0 { + return score + } + defer func() { + scores[v.ID] = score + }() + if v.Op == OpPhi { + return 1 + } + score = 2 // NIT(@Jorropo): always order phis first to make GOSSAFUNC pretty. + for _, a := range v.Args { + if a.Block != v.Block { + continue + } + score = max(score, getDependencyScore(scores, a)+1) + } + return score +} + +// topoSortValuesInBlock ensure ranging over b.Values visit values before they are being used. +// It does not consider dependencies with other blocks; thus Phi nodes are considered to not have any dependencies. +// The result is always deterministic and does not depend on the previous slice ordering. +func (ft *factsTable) topoSortValuesInBlock(b *Block) { + f := b.Func + want := f.NumValues() + + scores := ft.reusedTopoSortScoresTable + if want <= cap(scores) { + scores = scores[:want] + } else { + if cap(scores) > 0 { + f.Cache.freeUintSlice(scores) + } + scores = f.Cache.allocUintSlice(want) + ft.reusedTopoSortScoresTable = scores + } + + for _, v := range b.Values { + scores[v.ID] = 0 // sentinel + } + + slices.SortFunc(b.Values, func(a, b *Value) int { + dependencyScoreA := getDependencyScore(scores, a) + dependencyScoreB := getDependencyScore(scores, b) + if dependencyScoreA != dependencyScoreB { + return cmp.Compare(dependencyScoreA, dependencyScoreB) + } + return cmp.Compare(a.ID, b.ID) + }) +} diff --git a/src/cmd/compile/internal/ssa/prove_test.go b/src/cmd/compile/internal/ssa/prove_test.go new file mode 100644 index 00000000000000..42a60dcb40d11b --- /dev/null +++ b/src/cmd/compile/internal/ssa/prove_test.go @@ -0,0 +1,87 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "math" + "math/bits" + "testing" +) + +func testLimitUnaryOpSigned8(t *testing.T, opName string, initLimit limit, op func(l limit, bitsize uint) limit, opImpl func(int8) int8) { + for min := math.MinInt8; min <= math.MaxInt8; min++ { + for max := min; max <= math.MaxInt8; max++ { + realSmallest, realBiggest := int8(math.MaxInt8), int8(math.MinInt8) + for i := min; i <= max; i++ { + result := opImpl(int8(i)) + if result < realSmallest { + realSmallest = result + } + if result > realBiggest { + realBiggest = result + } + } + + l := limit{int64(min), int64(max), 0, math.MaxUint64} + l = op(l, 8) + l = l.intersect(initLimit) // We assume this is gonna be used by newLimit which is seeded by the op size already. + + if l.min != int64(realSmallest) || l.max != int64(realBiggest) { + t.Errorf("%s(%d..%d) = %d..%d; want %d..%d", opName, min, max, l.min, l.max, realSmallest, realBiggest) + } + } + } +} + +func testLimitUnaryOpUnsigned8(t *testing.T, opName string, initLimit limit, op func(l limit, bitsize uint) limit, opImpl func(uint8) uint8) { + for min := 0; min <= math.MaxUint8; min++ { + for max := min; max <= math.MaxUint8; max++ { + realSmallest, realBiggest := uint8(math.MaxUint8), uint8(0) + for i := min; i <= max; i++ { + result := opImpl(uint8(i)) + if result < realSmallest { + realSmallest = result + } + if result > realBiggest { + realBiggest = result + } + } + + l := limit{math.MinInt64, math.MaxInt64, uint64(min), uint64(max)} + l = op(l, 8) + l = l.intersect(initLimit) // We assume this is gonna be used by newLimit which is seeded by the op size already. + + if l.umin != uint64(realSmallest) || l.umax != uint64(realBiggest) { + t.Errorf("%s(%d..%d) = %d..%d; want %d..%d", opName, min, max, l.umin, l.umax, realSmallest, realBiggest) + } + } + } +} + +func TestLimitNegSigned(t *testing.T) { + testLimitUnaryOpSigned8(t, "neg", noLimitForBitsize(8), limit.neg, func(x int8) int8 { return -x }) +} +func TestLimitNegUnsigned(t *testing.T) { + testLimitUnaryOpUnsigned8(t, "neg", noLimitForBitsize(8), limit.neg, func(x uint8) uint8 { return -x }) +} + +func TestLimitComSigned(t *testing.T) { + testLimitUnaryOpSigned8(t, "com", noLimitForBitsize(8), limit.com, func(x int8) int8 { return ^x }) +} +func TestLimitComUnsigned(t *testing.T) { + testLimitUnaryOpUnsigned8(t, "com", noLimitForBitsize(8), limit.com, func(x uint8) uint8 { return ^x }) +} + +func TestLimitCtzUnsigned(t *testing.T) { + testLimitUnaryOpUnsigned8(t, "ctz", limit{-128, 127, 0, 8}, limit.ctz, func(x uint8) uint8 { return uint8(bits.TrailingZeros8(x)) }) +} + +func TestLimitBitlenUnsigned(t *testing.T) { + testLimitUnaryOpUnsigned8(t, "bitlen", limit{-128, 127, 0, 8}, limit.bitlen, func(x uint8) uint8 { return uint8(bits.Len8(x)) }) +} + +func TestLimitPopcountUnsigned(t *testing.T) { + testLimitUnaryOpUnsigned8(t, "popcount", limit{-128, 127, 0, 8}, limit.popcount, func(x uint8) uint8 { return uint8(bits.OnesCount8(x)) }) +} diff --git a/src/cmd/compile/internal/ssa/regalloc.go b/src/cmd/compile/internal/ssa/regalloc.go index 0009de4fa69608..b2aea339cd8db6 100644 --- a/src/cmd/compile/internal/ssa/regalloc.go +++ b/src/cmd/compile/internal/ssa/regalloc.go @@ -119,10 +119,12 @@ import ( "cmd/compile/internal/types" "cmd/internal/src" "cmd/internal/sys" + "cmp" "fmt" "internal/buildcfg" "math" "math/bits" + "slices" "unsafe" ) @@ -163,16 +165,72 @@ var noRegisters [32]register = [32]register{ } // A regMask encodes a set of machine registers. -// TODO: regMask -> regSet? -type regMask uint64 +type regMask struct { + v1, v2 uint64 +} + +func (r regMask) intersect(s regMask) regMask { + return regMask{r.v1 & s.v1, r.v2 & s.v2} +} + +func (r regMask) union(s regMask) regMask { + return regMask{r.v1 | s.v1, r.v2 | s.v2} +} + +func (r regMask) minus(s regMask) regMask { + return regMask{r.v1 &^ s.v1, r.v2 &^ s.v2} +} + +func (r regMask) empty() bool { + return r.v1 == 0 && r.v2 == 0 +} + +func (r regMask) pickReg() register { + if r.empty() { + panic("can't pick a register from an empty set") + } + // pick the lowest one + if r.v1 != 0 { + return register(bits.TrailingZeros64(r.v1)) + } + return register(bits.TrailingZeros64(r.v2) + 64) +} + +func regMaskAt(i register) regMask { + if i < 64 { + return regMask{v1: 1 << i} + } + return regMask{v2: 1 << (i - 64)} +} + +func (r regMask) addReg(i register) regMask { + if i < 64 { + return regMask{r.v1 | 1<>i)&1 != 0 + } + return (r.v2>>(i-64))&1 != 0 +} func (m regMask) String() string { s := "" - for r := register(0); m != 0; r++ { - if m>>r&1 == 0 { + for r := register(0); !m.empty(); r++ { + if !m.hasReg(r) { continue } - m &^= regMask(1) << r + m = m.removeReg(r) if s != "" { s += " " } @@ -181,17 +239,13 @@ func (m regMask) String() string { return s } -func (m regMask) contains(r register) bool { - return m>>r&1 != 0 -} - func (s *regAllocState) RegMaskString(m regMask) string { str := "" - for r := register(0); m != 0; r++ { - if m>>r&1 == 0 { + for r := register(0); !m.empty(); r++ { + if !m.hasReg(r) { continue } - m &^= regMask(1) << r + m = m.removeReg(r) if str != "" { str += " " } @@ -202,16 +256,19 @@ func (s *regAllocState) RegMaskString(m regMask) string { // countRegs returns the number of set bits in the register mask. func countRegs(r regMask) int { - return bits.OnesCount64(uint64(r)) + return bits.OnesCount64(r.v1) + bits.OnesCount64(r.v2) } -// pickReg picks an arbitrary register from the register mask. -func pickReg(r regMask) register { - if r == 0 { - panic("can't pick a register from an empty set") +// pickReg picks a register from the register mask. +func (s *regAllocState) pickReg(rm regMask) register { + if s.f.Config.ctxt.Arch.Arch == sys.ArchRISCV64 { + // Prefer x8-x15 and f8-f15 to enable increased use of compressed instructions. + riscv64CompressedMask := rm.intersect(regMask{v1: 0x0000ff000000ff00}) + if !riscv64CompressedMask.empty() { + rm = riscv64CompressedMask + } } - // pick the lowest one - return register(bits.TrailingZeros64(uint64(r))) + return rm.pickReg() } type use struct { @@ -354,7 +411,7 @@ type startReg struct { // freeReg frees up register r. Any current user of r is kicked out. func (s *regAllocState) freeReg(r register) { - if !s.allocatable.contains(r) && !s.isGReg(r) { + if !s.allocatable.hasReg(r) && !s.isGReg(r) { return } v := s.regs[r].v @@ -367,23 +424,23 @@ func (s *regAllocState) freeReg(r register) { fmt.Printf("freeReg %s (dump %s/%s)\n", &s.registers[r], v, s.regs[r].c) } s.regs[r] = regState{} - s.values[v.ID].regs &^= regMask(1) << r - s.used &^= regMask(1) << r + s.values[v.ID].regs = s.values[v.ID].regs.removeReg(r) + s.used = s.used.removeReg(r) } // freeRegs frees up all registers listed in m. func (s *regAllocState) freeRegs(m regMask) { - for m&s.used != 0 { - s.freeReg(pickReg(m & s.used)) + for !m.intersect(s.used).empty() { + s.freeReg(s.pickReg(m.intersect(s.used))) } } // clobberRegs inserts instructions that clobber registers listed in m. func (s *regAllocState) clobberRegs(m regMask) { - m &= s.allocatable & s.f.Config.gpRegMask // only integer register can contain pointers, only clobber them - for m != 0 { - r := pickReg(m) - m &^= 1 << r + m = m.intersect(s.allocatable.intersect(s.f.Config.gpRegMask)) // only integer register can contain pointers, only clobber them + for !m.empty() { + r := s.pickReg(m) + m = m.removeReg(r) x := s.curBlock.NewValue0(src.NoXPos, OpClobberReg, types.TypeVoid) s.f.setHome(x, &s.registers[r]) } @@ -414,18 +471,18 @@ func (s *regAllocState) assignReg(r register, v *Value, c *Value) { fmt.Printf("assignReg %s %s/%s\n", &s.registers[r], v, c) } // Allocate v to r. - s.values[v.ID].regs |= regMask(1) << r + s.values[v.ID].regs = s.values[v.ID].regs.addReg(r) s.f.setHome(c, &s.registers[r]) // Allocate r to v. - if !s.allocatable.contains(r) && !s.isGReg(r) { + if !s.allocatable.hasReg(r) && !s.isGReg(r) { return } if s.regs[r].v != nil { s.f.Fatalf("tried to assign register %d to %s/%s but it is already used by %s", r, v, c, s.regs[r].v) } s.regs[r] = regState{v, c} - s.used |= regMask(1) << r + s.used = s.used.addReg(r) } // allocReg chooses a register from the set of registers in mask. @@ -436,16 +493,16 @@ func (s *regAllocState) allocReg(mask regMask, v *Value) register { return noRegister } - mask &= s.allocatable - mask &^= s.nospill - if mask == 0 { + mask = mask.intersect(s.allocatable) + mask = mask.minus(s.nospill) + if mask.empty() { s.f.Fatalf("no register available for %s", v.LongString()) } // Pick an unused register if one is available. - if mask&^s.used != 0 { - r := pickReg(mask &^ s.used) - s.usedSinceBlockStart |= regMask(1) << r + if !mask.minus(s.used).empty() { + r := s.pickReg(mask.minus(s.used)) + s.usedSinceBlockStart = s.usedSinceBlockStart.addReg(r) return r } @@ -462,7 +519,7 @@ func (s *regAllocState) allocReg(mask regMask, v *Value) register { var r register maxuse := int32(-1) for t := register(0); t < s.numRegs; t++ { - if mask>>t&1 == 0 { + if !mask.hasReg(t) { continue } v := s.regs[t].v @@ -488,10 +545,10 @@ func (s *regAllocState) allocReg(mask regMask, v *Value) register { // Try to move it around before kicking out, if there is a free register. // We generate a Copy and record it. It will be deleted if never used. v2 := s.regs[r].v - m := s.compatRegs(v2.Type) &^ s.used &^ s.tmpused &^ (regMask(1) << r) - if m != 0 && !s.values[v2.ID].rematerializeable && countRegs(s.values[v2.ID].regs) == 1 { - s.usedSinceBlockStart |= regMask(1) << r - r2 := pickReg(m) + m := s.compatRegs(v2.Type).minus(s.used).minus(s.tmpused).removeReg(r) + if !m.empty() && !s.values[v2.ID].rematerializeable && countRegs(s.values[v2.ID].regs) == 1 { + s.usedSinceBlockStart = s.usedSinceBlockStart.addReg(r) + r2 := s.pickReg(m) c := s.curBlock.NewValue1(v2.Pos, OpCopy, v2.Type, s.regs[r].c) s.copies[c] = false if s.f.pass.debug > regDebug { @@ -504,17 +561,17 @@ func (s *regAllocState) allocReg(mask regMask, v *Value) register { // If the evicted register isn't used between the start of the block // and now then there is no reason to even request it on entry. We can // drop from startRegs in that case. - if s.usedSinceBlockStart&(regMask(1)< regDebug { fmt.Printf("dropped from startRegs: %s\n", &s.registers[r]) } - s.startRegsMask &^= regMask(1) << r + s.startRegsMask = s.startRegsMask.removeReg(r) } } s.freeReg(r) - s.usedSinceBlockStart |= regMask(1) << r + s.usedSinceBlockStart = s.usedSinceBlockStart.addReg(r) return r } @@ -560,25 +617,25 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, pos vi := &s.values[v.ID] pos = pos.WithNotStmt() // Check if v is already in a requested register. - if mask&vi.regs != 0 { - mask &= vi.regs - r := pickReg(mask) - if mask.contains(s.SPReg) { + if !mask.intersect(vi.regs).empty() { + mask = mask.intersect(vi.regs) + r := s.pickReg(mask) + if mask.hasReg(s.SPReg) { // Prefer the stack pointer if it is allowed. // (Needed because the op might have an Aux symbol // that needs SP as its base.) r = s.SPReg } - if !s.allocatable.contains(r) { + if !s.allocatable.hasReg(r) { return v // v is in a fixed register } if s.regs[r].v != v || s.regs[r].c == nil { panic("bad register state") } if nospill { - s.nospill |= regMask(1) << r + s.nospill = s.nospill.addReg(r) } - s.usedSinceBlockStart |= regMask(1) << r + s.usedSinceBlockStart = s.usedSinceBlockStart.addReg(r) return s.regs[r].c } @@ -592,19 +649,20 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, pos // Allocate v to the new register. var c *Value - if vi.regs != 0 { + if !vi.regs.empty() { // Copy from a register that v is already in. - r2 := pickReg(vi.regs) var current *Value - if !s.allocatable.contains(r2) { - current = v // v is in a fixed register + if !vi.regs.minus(s.allocatable).empty() { + // v is in a fixed register, prefer that + current = v } else { + r2 := s.pickReg(vi.regs) if s.regs[r2].v != v { panic("bad register state") } current = s.regs[r2].c + s.usedSinceBlockStart = s.usedSinceBlockStart.addReg(r2) } - s.usedSinceBlockStart |= regMask(1) << r2 c = s.curBlock.NewValue1(pos, OpCopy, v.Type, current) } else if v.rematerializeable() { // Rematerialize instead of loading from the spill location. @@ -617,7 +675,7 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, pos // Because GP and FP masks do not overlap, mask & outputMask == 0 // detects this situation thoroughly. sourceMask := s.regspec(c).outputs[0].regs - if mask&sourceMask == 0 && !onWasmStack { + if mask.intersect(sourceMask).empty() && !onWasmStack { s.setOrig(c, v) s.assignReg(s.allocReg(sourceMask, v), v, c) // v.Type for the new OpCopy is likely wrong and it might delay the problem @@ -639,6 +697,15 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, pos s.f.Warnl(vi.spill.Pos, "load spill for %v from %v", v, spill) } c = s.curBlock.NewValue1(pos, OpLoadReg, v.Type, spill) + sourceMask := s.compatRegs(v.Type) + if !sourceMask.hasReg(r) && !onWasmStack { + // Assign a temporary register that can be copied to the desired destination; + // this at least works where it is currently a problem (x86). + // This happens processing e.g. ASAN/TSAN with SIMD *simdtype methods. + s.setOrig(c, v) + s.assignReg(s.allocReg(sourceMask, v), v, c) + c = s.curBlock.NewValue1(pos, OpCopy, v.Type, c) + } } s.setOrig(c, v) @@ -653,7 +720,7 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, pos s.f.Fatalf("allocValToReg.OpLoadReg targeting g: " + c.LongString()) } if nospill { - s.nospill |= regMask(1) << r + s.nospill = s.nospill.addReg(r) } return c } @@ -680,7 +747,7 @@ func (s *regAllocState) init(f *Func) { s.f = f s.f.RegAlloc = s.f.Cache.locs[:0] s.registers = f.Config.registers - if nr := len(s.registers); nr == 0 || nr > int(noRegister) || nr > int(unsafe.Sizeof(regMask(0))*8) { + if nr := len(s.registers); nr == 0 || nr > int(noRegister) || nr > int(unsafe.Sizeof(regMask{})*8) { s.f.Fatalf("bad number of registers: %d", nr) } else { s.numRegs = register(nr) @@ -715,22 +782,22 @@ func (s *regAllocState) init(f *Func) { } // Figure out which registers we're allowed to use. - s.allocatable = s.f.Config.gpRegMask | s.f.Config.fpRegMask | s.f.Config.specialRegMask - s.allocatable &^= 1 << s.SPReg - s.allocatable &^= 1 << s.SBReg + s.allocatable = s.f.Config.gpRegMask.union(s.f.Config.fpRegMask).union(s.f.Config.specialRegMask).union(s.f.Config.simdRegMask) + s.allocatable = s.allocatable.removeReg(s.SPReg) + s.allocatable = s.allocatable.removeReg(s.SBReg) if s.f.Config.hasGReg { - s.allocatable &^= 1 << s.GReg + s.allocatable = s.allocatable.removeReg(s.GReg) } if s.ZeroIntReg != noRegister { - s.allocatable &^= 1 << s.ZeroIntReg + s.allocatable = s.allocatable.removeReg(s.ZeroIntReg) } if buildcfg.FramePointerEnabled && s.f.Config.FPReg >= 0 { - s.allocatable &^= 1 << uint(s.f.Config.FPReg) + s.allocatable = s.allocatable.removeReg(register(s.f.Config.FPReg)) } if s.f.Config.LinkReg != -1 { if isLeaf(f) { // Leaf functions don't save/restore the link register. - s.allocatable &^= 1 << uint(s.f.Config.LinkReg) + s.allocatable = s.allocatable.removeReg(register(s.f.Config.LinkReg)) } } if s.f.Config.ctxt.Flag_dynlink { @@ -742,19 +809,19 @@ func (s *regAllocState) init(f *Func) { // in the rewrite rules so we always have a free register // available for global load/stores. See _gen/386.rules (search for Flag_shared). case "amd64": - s.allocatable &^= 1 << 15 // R15 + s.allocatable = s.allocatable.removeReg(15) // R15 case "arm": - s.allocatable &^= 1 << 9 // R9 + s.allocatable = s.allocatable.removeReg(9) // R9 case "arm64": // nothing to do case "loong64": // R2 (aka TP) already reserved. // nothing to do - case "ppc64le": // R2 already reserved. + case "ppc64", "ppc64le": // R2 already reserved. // nothing to do case "riscv64": // X3 (aka GP) and X4 (aka TP) already reserved. // nothing to do case "s390x": - s.allocatable &^= 1 << 11 // R11 + s.allocatable = s.allocatable.removeReg(11) // R11 default: s.f.fe.Fatalf(src.NoXPos, "arch %s not implemented", s.f.Config.arch) } @@ -894,7 +961,15 @@ func (s *regAllocState) dropIfUnused(v *Value) { } vi := &s.values[v.ID] r := vi.uses - if r == nil || (!opcodeTable[v.Op].fixedReg && r.dist > s.nextCall[s.curIdx]) { + nextCall := s.nextCall[s.curIdx] + if opcodeTable[v.Op].call { + if s.curIdx == len(s.nextCall)-1 { + nextCall = math.MaxInt32 + } else { + nextCall = s.nextCall[s.curIdx+1] + } + } + if r == nil || (!opcodeTable[v.Op].fixedReg && r.dist > nextCall) { s.freeRegs(vi.regs) } } @@ -926,12 +1001,20 @@ func (s *regAllocState) setState(regs []endReg) { func (s *regAllocState) compatRegs(t *types.Type) regMask { var m regMask if t.IsTuple() || t.IsFlags() { - return 0 + return regMask{} + } + if t.IsSIMD() { + if t.Size() > 8 { + return s.f.Config.simdRegMask.intersect(s.allocatable) + } else { + // K mask + return s.f.Config.gpRegMask.intersect(s.allocatable) + } } if t.IsFloat() || t == types.TypeInt128 { - if t.Kind() == types.TFLOAT32 && s.f.Config.fp32RegMask != 0 { + if t.Kind() == types.TFLOAT32 && !s.f.Config.fp32RegMask.empty() { m = s.f.Config.fp32RegMask - } else if t.Kind() == types.TFLOAT64 && s.f.Config.fp64RegMask != 0 { + } else if t.Kind() == types.TFLOAT64 && !s.f.Config.fp64RegMask.empty() { m = s.f.Config.fp64RegMask } else { m = s.f.Config.fpRegMask @@ -939,7 +1022,7 @@ func (s *regAllocState) compatRegs(t *types.Type) regMask { } else { m = s.f.Config.gpRegMask } - return m & s.allocatable + return m.intersect(s.allocatable) } // regspec returns the regInfo for operation op. @@ -949,16 +1032,16 @@ func (s *regAllocState) regspec(v *Value) regInfo { // OpConvert is a generic op, so it doesn't have a // register set in the static table. It can use any // allocatable integer register. - m := s.allocatable & s.f.Config.gpRegMask + m := s.allocatable.intersect(s.f.Config.gpRegMask) return regInfo{inputs: []inputInfo{{regs: m}}, outputs: []outputInfo{{regs: m}}} } if op == OpArgIntReg { reg := v.Block.Func.Config.intParamRegs[v.AuxInt8()] - return regInfo{outputs: []outputInfo{{regs: 1 << uint(reg)}}} + return regInfo{outputs: []outputInfo{{regs: regMaskAt(register(reg))}}} } if op == OpArgFloatReg { reg := v.Block.Func.Config.floatParamRegs[v.AuxInt8()] - return regInfo{outputs: []outputInfo{{regs: 1 << uint(reg)}}} + return regInfo{outputs: []outputInfo{{regs: regMaskAt(register(reg))}}} } if op.IsCall() { if ac, ok := v.Aux.(*AuxCall); ok && ac.reg != nil { @@ -1006,16 +1089,18 @@ func (s *regAllocState) regalloc(f *Func) { fmt.Printf("Begin processing block %v\n", b) } s.curBlock = b - s.startRegsMask = 0 - s.usedSinceBlockStart = 0 + s.startRegsMask = regMask{} + s.usedSinceBlockStart = regMask{} clear(desiredSecondReg) // Initialize regValLiveSet and uses fields for this block. // Walk backwards through the block doing liveness analysis. regValLiveSet.clear() - for _, e := range s.live[b.ID] { - s.addUse(e.ID, int32(len(b.Values))+e.dist, e.pos) // pseudo-uses from beyond end of block - regValLiveSet.add(e.ID) + if s.live != nil { + for _, e := range s.live[b.ID] { + s.addUse(e.ID, int32(len(b.Values))+e.dist, e.pos) // pseudo-uses from beyond end of block + regValLiveSet.add(e.ID) + } } for _, v := range b.ControlValues() { if s.values[v.ID].needReg { @@ -1023,8 +1108,11 @@ func (s *regAllocState) regalloc(f *Func) { regValLiveSet.add(v.ID) } } - if len(s.nextCall) < len(b.Values) { - s.nextCall = append(s.nextCall, make([]int32, len(b.Values)-len(s.nextCall))...) + if cap(s.nextCall) < len(b.Values) { + c := cap(s.nextCall) + s.nextCall = append(s.nextCall[:c], make([]int32, len(b.Values)-c)...) + } else { + s.nextCall = s.nextCall[:len(b.Values)] } var nextCall int32 = math.MaxInt32 for i := len(b.Values) - 1; i >= 0; i-- { @@ -1181,10 +1269,10 @@ func (s *regAllocState) regalloc(f *Func) { a := v.Args[idx] // Some instructions target not-allocatable registers. // They're not suitable for further (phi-function) allocation. - m := s.values[a.ID].regs &^ phiUsed & s.allocatable - if m != 0 { - r := pickReg(m) - phiUsed |= regMask(1) << r + m := s.values[a.ID].regs.minus(phiUsed).intersect(s.allocatable) + if !m.empty() { + r := s.pickReg(m) + phiUsed = phiUsed.addReg(r) phiRegs = append(phiRegs, r) } else { phiRegs = append(phiRegs, noRegister) @@ -1210,9 +1298,9 @@ func (s *regAllocState) regalloc(f *Func) { // Pick a free register. At this point some registers used in the predecessor // block may have been deallocated. Those are the ones used for Phis. Exclude // them (and they are not going to be helpful anyway). - m := s.compatRegs(a.Type) &^ s.used &^ phiUsed - if m != 0 && !s.values[a.ID].rematerializeable && countRegs(s.values[a.ID].regs) == 1 { - r2 := pickReg(m) + m := s.compatRegs(a.Type).minus(s.used).minus(phiUsed) + if !m.empty() && !s.values[a.ID].rematerializeable && countRegs(s.values[a.ID].regs) == 1 { + r2 := s.pickReg(m) c := p.NewValue1(a.Pos, OpCopy, a.Type, s.regs[r].c) s.copies[c] = false if s.f.pass.debug > regDebug { @@ -1238,7 +1326,7 @@ func (s *regAllocState) regalloc(f *Func) { if phiRegs[i] != noRegister { continue } - m := s.compatRegs(v.Type) &^ phiUsed &^ s.used + m := s.compatRegs(v.Type).minus(phiUsed).minus(s.used) // If one of the other inputs of v is in a register, and the register is available, // select this register, which can save some unnecessary copies. for i, pe := range b.Preds { @@ -1252,15 +1340,15 @@ func (s *regAllocState) regalloc(f *Func) { break } } - if ri != noRegister && m>>ri&1 != 0 { - m = regMask(1) << ri + if ri != noRegister && m.hasReg(ri) { + m = regMaskAt(ri) break } } - if m != 0 { - r := pickReg(m) + if !m.empty() { + r := s.pickReg(m) phiRegs[i] = r - phiUsed |= regMask(1) << r + phiUsed = phiUsed.addReg(r) } } @@ -1282,7 +1370,7 @@ func (s *regAllocState) regalloc(f *Func) { // Deallocate any values which are no longer live. Phis are excluded. for r := register(0); r < s.numRegs; r++ { - if phiUsed>>r&1 != 0 { + if phiUsed.hasReg(r) { continue } v := s.regs[r].v @@ -1301,13 +1389,13 @@ func (s *regAllocState) regalloc(f *Func) { if v == nil { continue } - if phiUsed>>r&1 != 0 { + if phiUsed.hasReg(r) { // Skip registers that phis used, we'll handle those // specially during merge edge processing. continue } regList = append(regList, startReg{r, v, s.regs[r].c, s.values[v.ID].uses.pos}) - s.startRegsMask |= regMask(1) << r + s.startRegsMask = s.startRegsMask.addReg(r) } s.startRegs[b.ID] = make([]startReg, len(regList)) copy(s.startRegs[b.ID], regList) @@ -1335,7 +1423,9 @@ func (s *regAllocState) regalloc(f *Func) { } // Load static desired register info at the end of the block. - desired.copy(&s.desired[b.ID]) + if s.desired != nil { + desired.copy(&s.desired[b.ID]) + } // Check actual assigned registers at the start of the next block(s). // Dynamically assigned registers will trump the static @@ -1377,7 +1467,7 @@ func (s *regAllocState) regalloc(f *Func) { } } // Walk values backwards computing desired register info. - // See computeLive for more comments. + // See computeDesired for more comments. for i := len(oldSched) - 1; i >= 0; i-- { v := oldSched[i] prefs := desired.remove(v.ID) @@ -1388,7 +1478,7 @@ func (s *regAllocState) regalloc(f *Func) { continue } desired.clobber(j.regs) - desired.add(v.Args[j.idx].ID, pickReg(j.regs)) + desired.add(v.Args[j.idx].ID, s.pickReg(j.regs)) } if opcodeTable[v.Op].resultInArg0 || v.Op == OpAMD64ADDQconst || v.Op == OpAMD64ADDLconst || v.Op == OpSelect0 { if opcodeTable[v.Op].commutative { @@ -1432,6 +1522,13 @@ func (s *regAllocState) regalloc(f *Func) { s.sb = v.ID case OpARM64ZERO, OpLOONG64ZERO, OpMIPS64ZERO: s.assignReg(s.ZeroIntReg, v, v) + case OpAMD64Zero128, OpAMD64Zero256, OpAMD64Zero512: + regspec := s.regspec(v) + m := regspec.outputs[0].regs + if countRegs(m) != 1 { + f.Fatalf("bad fixed-register op %s", v) + } + s.assignReg(s.pickReg(m), v, v) default: f.Fatalf("unknown fixed-register op %s", v) } @@ -1479,7 +1576,7 @@ func (s *regAllocState) regalloc(f *Func) { s.advanceUses(v) a := v.Args[0] vi := &s.values[a.ID] - if vi.regs == 0 && !vi.rematerializeable { + if vi.regs.empty() && !vi.rematerializeable { // Use the spill location. // This forces later liveness analysis to make the // value live at this point. @@ -1554,7 +1651,7 @@ func (s *regAllocState) regalloc(f *Func) { } for _, i := range regspec.inputs { mask := i.regs - if countRegs(mask) == 1 && mask&s.values[v.Args[i.idx].ID].regs != 0 { + if countRegs(mask) == 1 && !mask.intersect(s.values[v.Args[i.idx].ID].regs).empty() { args[i.idx] = s.allocValToReg(v.Args[i.idx], mask, true, v.Pos) } } @@ -1571,14 +1668,14 @@ func (s *regAllocState) regalloc(f *Func) { continue // already allocated } mask := i.regs - if countRegs(mask) == 1 && mask&^s.used != 0 { + if countRegs(mask) == 1 && !mask.minus(s.used).empty() { args[i.idx] = s.allocValToReg(v.Args[i.idx], mask, true, v.Pos) // If the input is in other registers that will be clobbered by v, // or the input is dead, free the registers. This may make room // for other inputs. oldregs := s.values[v.Args[i.idx].ID].regs - if oldregs&^regspec.clobbers == 0 || !s.liveAfterCurrentInstruction(v.Args[i.idx]) { - s.freeRegs(oldregs &^ mask &^ s.nospill) + if oldregs.minus(regspec.clobbers).empty() || !s.liveAfterCurrentInstruction(v.Args[i.idx]) { + s.freeRegs(oldregs.minus(mask).minus(s.nospill)) freed = true } } @@ -1594,30 +1691,30 @@ func (s *regAllocState) regalloc(f *Func) { continue // already allocated } mask := i.regs - if mask&s.values[v.Args[i.idx].ID].regs == 0 { + if mask.intersect(s.values[v.Args[i.idx].ID].regs).empty() { // Need a new register for the input. - mask &= s.allocatable - mask &^= s.nospill + mask = mask.intersect(s.allocatable) + mask = mask.minus(s.nospill) // Used desired register if available. if i.idx < 3 { for _, r := range dinfo[idx].in[i.idx] { - if r != noRegister && (mask&^s.used)>>r&1 != 0 { + if r != noRegister && mask.minus(s.used).hasReg(r) { // Desired register is allowed and unused. - mask = regMask(1) << r + mask = regMaskAt(r) break } } } // Avoid registers we're saving for other values. - if mask&^desired.avoid != 0 { - mask &^= desired.avoid + if !mask.minus(desired.avoid).empty() { + mask = mask.minus(desired.avoid) } } - if mask&s.values[v.Args[i.idx].ID].regs&(1<>r&1 != 0 { - m = regMask(1) << r + if r != noRegister && m.intersect(regspec.outputs[0].regs).hasReg(r) { + m = regMaskAt(r) args[0] = s.allocValToReg(v.Args[0], m, true, v.Pos) // Note: we update args[0] so the instruction will // use the register copy we just made. @@ -1678,8 +1775,8 @@ func (s *regAllocState) regalloc(f *Func) { // Try to copy input to its desired location & use its old // location as the result register. for _, r := range dinfo[idx].in[0] { - if r != noRegister && m>>r&1 != 0 { - m = regMask(1) << r + if r != noRegister && m.hasReg(r) { + m = regMaskAt(r) c := s.allocValToReg(v.Args[0], m, true, v.Pos) s.copies[c] = false // Note: no update to args[0] so the instruction will @@ -1689,8 +1786,8 @@ func (s *regAllocState) regalloc(f *Func) { } if opcodeTable[v.Op].commutative { for _, r := range dinfo[idx].in[1] { - if r != noRegister && m>>r&1 != 0 { - m = regMask(1) << r + if r != noRegister && m.hasReg(r) { + m = regMaskAt(r) c := s.allocValToReg(v.Args[1], m, true, v.Pos) s.copies[c] = false args[0], args[1] = args[1], args[0] @@ -1700,8 +1797,8 @@ func (s *regAllocState) regalloc(f *Func) { } // Avoid future fixed uses if we can. - if m&^desired.avoid != 0 { - m &^= desired.avoid + if !m.minus(desired.avoid).empty() { + m = m.minus(desired.avoid) } // Save input 0 to a new register so we can clobber it. c := s.allocValToReg(v.Args[0], m, true, v.Pos) @@ -1710,7 +1807,7 @@ func (s *regAllocState) regalloc(f *Func) { // Normally we use the register of the old copy of input 0 as the target. // However, if input 0 is already in its desired register then we use // the register of the new copy instead. - if regspec.outputs[0].regs>>s.f.getHome(c.ID).(*Register).num&1 != 0 { + if regspec.outputs[0].regs.hasReg(register(s.f.getHome(c.ID).(*Register).num)) { if rp, ok := s.f.getHome(args[0].ID).(*Register); ok { r := register(rp.num) for _, r2 := range dinfo[idx].in[0] { @@ -1740,8 +1837,8 @@ func (s *regAllocState) regalloc(f *Func) { continue } // Possible new registers to copy into. - m := s.compatRegs(v.Args[i].Type) &^ s.used - if m == 0 { + m := s.compatRegs(v.Args[i].Type).minus(s.used) + if m.empty() { // No free registers. In this case we'll just clobber the // input and future uses of that input must use a restore. // TODO(khr): We should really do this like allocReg does it, @@ -1760,24 +1857,24 @@ func (s *regAllocState) regalloc(f *Func) { // (Not all instructions need that distinct part, but it is conservative.) // We also ensure it is not any of the single-choice output registers. if opcodeTable[v.Op].needIntTemp { - m := s.allocatable & s.f.Config.gpRegMask + m := s.allocatable.intersect(s.f.Config.gpRegMask) for _, out := range regspec.outputs { if countRegs(out.regs) == 1 { - m &^= out.regs + m = m.minus(out.regs) } } - if m&^desired.avoid&^s.nospill != 0 { - m &^= desired.avoid + if !m.minus(desired.avoid).minus(s.nospill).empty() { + m = m.minus(desired.avoid) } tmpReg = s.allocReg(m, &tmpVal) - s.nospill |= regMask(1) << tmpReg - s.tmpused |= regMask(1) << tmpReg + s.nospill = s.nospill.addReg(tmpReg) + s.tmpused = s.tmpused.addReg(tmpReg) } if regspec.clobbersArg0 { s.freeReg(register(s.f.getHome(args[0].ID).(*Register).num)) } - if regspec.clobbersArg1 { + if regspec.clobbersArg1 && !(regspec.clobbersArg0 && s.f.getHome(args[0].ID) == s.f.getHome(args[1].ID)) { s.freeReg(register(s.f.getHome(args[1].ID).(*Register).num)) } @@ -1787,7 +1884,7 @@ func (s *regAllocState) regalloc(f *Func) { // same register as a dying input. if !opcodeTable[v.Op].resultNotInArgs { s.tmpused = s.nospill - s.nospill = 0 + s.nospill = regMask{} s.advanceUses(v) // frees any registers holding args that are no longer live } @@ -1795,10 +1892,10 @@ func (s *regAllocState) regalloc(f *Func) { if s.doClobber && v.Op.IsCall() { // clobber registers that are marked as clobber in regmask, but // don't clobber inputs. - s.clobberRegs(regspec.clobbers &^ s.tmpused &^ s.nospill) + s.clobberRegs(regspec.clobbers.minus(s.tmpused).minus(s.nospill)) } s.freeRegs(regspec.clobbers) - s.tmpused |= regspec.clobbers + s.tmpused = s.tmpused.union(regspec.clobbers) // Pick registers for outputs. { @@ -1808,24 +1905,24 @@ func (s *regAllocState) regalloc(f *Func) { if tmpReg != noRegister { // Ensure output registers are distinct from the temporary register. // (Not all instructions need that distinct part, but it is conservative.) - used |= regMask(1) << tmpReg + used = used.addReg(tmpReg) } for _, out := range regspec.outputs { - if out.regs == 0 { + if out.regs.empty() { continue } - mask := out.regs & s.allocatable &^ used - if mask == 0 { + mask := out.regs.intersect(s.allocatable).minus(used) + if mask.empty() { s.f.Fatalf("can't find any output register %s", v.LongString()) } if opcodeTable[v.Op].resultInArg0 && out.idx == 0 { if !opcodeTable[v.Op].commutative { // Output must use the same register as input 0. r := register(s.f.getHome(args[0].ID).(*Register).num) - if mask>>r&1 == 0 { + if !mask.hasReg(r) { s.f.Fatalf("resultInArg0 value's input %v cannot be an output of %s", s.f.getHome(args[0].ID).(*Register), v.LongString()) } - mask = regMask(1) << r + mask = regMaskAt(r) } else { // Output must use the same register as input 0 or 1. r0 := register(s.f.getHome(args[0].ID).(*Register).num) @@ -1833,8 +1930,8 @@ func (s *regAllocState) regalloc(f *Func) { // Check r0 and r1 for desired output register. found := false for _, r := range dinfo[idx].out { - if (r == r0 || r == r1) && (mask&^s.used)>>r&1 != 0 { - mask = regMask(1) << r + if (r == r0 || r == r1) && mask.minus(s.used).hasReg(r) { + mask = regMaskAt(r) found = true if r == r1 { args[0], args[1] = args[1], args[0] @@ -1844,15 +1941,15 @@ func (s *regAllocState) regalloc(f *Func) { } if !found { // Neither are desired, pick r0. - mask = regMask(1) << r0 + mask = regMaskAt(r0) } } } if out.idx == 0 { // desired registers only apply to the first element of a tuple result for _, r := range dinfo[idx].out { - if r != noRegister && (mask&^s.used)>>r&1 != 0 { + if r != noRegister && mask.minus(s.used).hasReg(r) { // Desired register is allowed and unused. - mask = regMask(1) << r + mask = regMaskAt(r) break } } @@ -1860,25 +1957,25 @@ func (s *regAllocState) regalloc(f *Func) { if out.idx == 1 { if prefs, ok := desiredSecondReg[v.ID]; ok { for _, r := range prefs { - if r != noRegister && (mask&^s.used)>>r&1 != 0 { + if r != noRegister && mask.minus(s.used).hasReg(r) { // Desired register is allowed and unused. - mask = regMask(1) << r + mask = regMaskAt(r) break } } } } // Avoid registers we're saving for other values. - if mask&^desired.avoid&^s.nospill&^s.used != 0 { - mask &^= desired.avoid + if !mask.minus(desired.avoid).minus(s.nospill).minus(s.used).empty() { + mask = mask.minus(desired.avoid) } r := s.allocReg(mask, v) if out.idx > maxOutIdx { maxOutIdx = out.idx } outRegs[out.idx] = r - used |= regMask(1) << r - s.tmpused |= regMask(1) << r + used = used.addReg(r) + s.tmpused = s.tmpused.addReg(r) } // Record register choices if v.Type.IsTuple() { @@ -1916,10 +2013,10 @@ func (s *regAllocState) regalloc(f *Func) { // deallocate dead args, if we have not done so if opcodeTable[v.Op].resultNotInArgs { - s.nospill = 0 + s.nospill = regMask{} s.advanceUses(v) // frees any registers holding args that are no longer live } - s.tmpused = 0 + s.tmpused = regMask{} // Issue the Value itself. for i, a := range args { @@ -1982,7 +2079,27 @@ func (s *regAllocState) regalloc(f *Func) { goto badloop } - // TODO: sort by distance, pick the closest ones? + // Look into target block, find Phi arguments that come from b. + phiArgs := regValLiveSet // reuse this space + phiArgs.clear() + for _, v := range b.Succs[0].b.Values { + if v.Op == OpPhi { + phiArgs.add(v.Args[b.Succs[0].i].ID) + } + } + + // Get mask of all registers that might be used soon in the destination. + // We don't want to kick values out of these registers, but we will + // kick out an unlikely-to-be-used value for a likely-to-be-used one. + var likelyUsedRegs regMask + for _, live := range s.live[b.ID] { + if live.dist < unlikelyDistance { + likelyUsedRegs = likelyUsedRegs.union(s.values[live.ID].regs) + } + } + // Promote values we're going to use soon in the destination to registers. + // Note that this iterates nearest-use first, as we sorted + // live lists by distance in computeLive. for _, live := range s.live[b.ID] { if live.dist >= unlikelyDistance { // Don't preload anything live after the loop. @@ -1990,14 +2107,41 @@ func (s *regAllocState) regalloc(f *Func) { } vid := live.ID vi := &s.values[vid] - if vi.regs != 0 { + v := s.orig[vid] + if phiArgs.contains(vid) { + // A phi argument needs its value in a regular register, + // as returned by compatRegs. Being in a fixed register + // (e.g. the zero register) or being easily + // rematerializeable isn't enough. + if !vi.regs.intersect(s.compatRegs(v.Type)).empty() { + continue + } + } else { + if !vi.regs.empty() { + continue + } + if vi.rematerializeable { + // TODO: maybe we should not skip rematerializeable + // values here. One rematerialization outside the loop + // is better than N in the loop. But rematerializations + // are cheap, and spilling another value may not be. + // And we don't want to materialize the zero register + // into a different register when it is just the + // argument to a store. + continue + } + } + if vi.rematerializeable && s.f.Config.ctxt.Arch.Arch == sys.ArchWasm { continue } - if vi.rematerializeable { + // Registers we could load v into. + // Don't kick out other likely-used values. + m := s.compatRegs(v.Type).minus(likelyUsedRegs) + if m.empty() { + // To many likely-used values to give them all a register. continue } - v := s.orig[vid] - m := s.compatRegs(v.Type) &^ s.used + // Used desired register if available. outerloop: for _, e := range desired.entries { @@ -2005,18 +2149,17 @@ func (s *regAllocState) regalloc(f *Func) { continue } for _, r := range e.regs { - if r != noRegister && m>>r&1 != 0 { - m = regMask(1) << r + if r != noRegister && m.hasReg(r) { + m = regMaskAt(r) break outerloop } } } - if m&^desired.avoid != 0 { - m &^= desired.avoid - } - if m != 0 { - s.allocValToReg(v, m, false, b.Pos) + if !m.minus(desired.avoid).empty() { + m = m.minus(desired.avoid) } + s.allocValToReg(v, m, false, b.Pos) + likelyUsedRegs = likelyUsedRegs.union(s.values[v.ID].regs) } } badloop: @@ -2044,8 +2187,10 @@ func (s *regAllocState) regalloc(f *Func) { if checkEnabled { regValLiveSet.clear() - for _, x := range s.live[b.ID] { - regValLiveSet.add(x.ID) + if s.live != nil { + for _, x := range s.live[b.ID] { + regValLiveSet.add(x.ID) + } } for r := register(0); r < s.numRegs; r++ { v := s.regs[r].v @@ -2062,37 +2207,39 @@ func (s *regAllocState) regalloc(f *Func) { // isn't in a register, generate a use for the spill location. // We need to remember this information so that // the liveness analysis in stackalloc is correct. - for _, e := range s.live[b.ID] { - vi := &s.values[e.ID] - if vi.regs != 0 { - // in a register, we'll use that source for the merge. - continue - } - if vi.rematerializeable { - // we'll rematerialize during the merge. - continue - } - if s.f.pass.debug > regDebug { - fmt.Printf("live-at-end spill for %s at %s\n", s.orig[e.ID], b) + if s.live != nil { + for _, e := range s.live[b.ID] { + vi := &s.values[e.ID] + if !vi.regs.empty() { + // in a register, we'll use that source for the merge. + continue + } + if vi.rematerializeable { + // we'll rematerialize during the merge. + continue + } + if s.f.pass.debug > regDebug { + fmt.Printf("live-at-end spill for %s at %s\n", s.orig[e.ID], b) + } + spill := s.makeSpill(s.orig[e.ID], b) + s.spillLive[b.ID] = append(s.spillLive[b.ID], spill.ID) } - spill := s.makeSpill(s.orig[e.ID], b) - s.spillLive[b.ID] = append(s.spillLive[b.ID], spill.ID) - } - // Clear any final uses. - // All that is left should be the pseudo-uses added for values which - // are live at the end of b. - for _, e := range s.live[b.ID] { - u := s.values[e.ID].uses - if u == nil { - f.Fatalf("live at end, no uses v%d", e.ID) - } - if u.next != nil { - f.Fatalf("live at end, too many uses v%d", e.ID) + // Clear any final uses. + // All that is left should be the pseudo-uses added for values which + // are live at the end of b. + for _, e := range s.live[b.ID] { + u := s.values[e.ID].uses + if u == nil { + f.Fatalf("live at end, no uses v%d", e.ID) + } + if u.next != nil { + f.Fatalf("live at end, too many uses v%d", e.ID) + } + s.values[e.ID].uses = nil + u.next = s.freeUseRecords + s.freeUseRecords = u } - s.values[e.ID].uses = nil - u.next = s.freeUseRecords - s.freeUseRecords = u } // allocReg may have dropped registers from startRegsMask that @@ -2104,7 +2251,7 @@ func (s *regAllocState) regalloc(f *Func) { if c := countRegs(s.startRegsMask); c != len(s.startRegs[b.ID]) { regs := make([]startReg, 0, c) for _, sr := range s.startRegs[b.ID] { - if s.startRegsMask&(regMask(1)< bestDepth { // Don't push the spill into a deeper loop. @@ -2355,10 +2502,10 @@ func (e *edgeState) setup(idx int, srcReg []endReg, dstReg []startReg, stacklive clear(e.cache) e.cachedVals = e.cachedVals[:0] clear(e.contents) - e.usedRegs = 0 - e.uniqueRegs = 0 - e.finalRegs = 0 - e.rematerializeableRegs = 0 + e.usedRegs = regMask{} + e.uniqueRegs = regMask{} + e.finalRegs = regMask{} + e.rematerializeableRegs = regMask{} // Live registers can be sources. for _, x := range srcReg { @@ -2565,7 +2712,7 @@ func (e *edgeState) processDest(loc Location, vid ID, splice **Value, pos src.XP // Instead of setting the wrong register for the rematerialized v, we should find the right register // for it and emit an additional copy to move to the desired register. // For #70451. - if e.s.regspec(v).outputs[0].regs®Mask(1< regDebug { @@ -2696,15 +2843,15 @@ func (e *edgeState) erase(loc Location) { // Update register masks. if r, ok := loc.(*Register); ok { - e.usedRegs &^= regMask(1) << uint(r.num) + e.usedRegs = e.usedRegs.removeReg(register(r.num)) if cr.final { - e.finalRegs &^= regMask(1) << uint(r.num) + e.finalRegs = e.finalRegs.removeReg(register(r.num)) } - e.rematerializeableRegs &^= regMask(1) << uint(r.num) + e.rematerializeableRegs = e.rematerializeableRegs.removeReg(register(r.num)) } if len(a) == 1 { if r, ok := e.s.f.getHome(a[0].ID).(*Register); ok { - e.uniqueRegs |= regMask(1) << uint(r.num) + e.uniqueRegs = e.uniqueRegs.addReg(register(r.num)) } } } @@ -2719,21 +2866,21 @@ func (e *edgeState) findRegFor(typ *types.Type) Location { // 2) a non-unique register not holding a final value // 3) a non-unique register // 4) a register holding a rematerializeable value - x := m &^ e.usedRegs - if x != 0 { - return &e.s.registers[pickReg(x)] + x := m.minus(e.usedRegs) + if !x.empty() { + return &e.s.registers[e.s.pickReg(x)] } - x = m &^ e.uniqueRegs &^ e.finalRegs - if x != 0 { - return &e.s.registers[pickReg(x)] + x = m.minus(e.uniqueRegs).minus(e.finalRegs) + if !x.empty() { + return &e.s.registers[e.s.pickReg(x)] } - x = m &^ e.uniqueRegs - if x != 0 { - return &e.s.registers[pickReg(x)] + x = m.minus(e.uniqueRegs) + if !x.empty() { + return &e.s.registers[e.s.pickReg(x)] } - x = m & e.rematerializeableRegs - if x != 0 { - return &e.s.registers[pickReg(x)] + x = m.intersect(e.rematerializeableRegs) + if !x.empty() { + return &e.s.registers[e.s.pickReg(x)] } // No register is available. @@ -2741,7 +2888,7 @@ func (e *edgeState) findRegFor(typ *types.Type) Location { for _, vid := range e.cachedVals { a := e.cache[vid] for _, c := range a { - if r, ok := e.s.f.getHome(c.ID).(*Register); ok && m>>uint(r.num)&1 != 0 { + if r, ok := e.s.f.getHome(c.ID).(*Register); ok && m.hasReg(register(r.num)) { if !c.rematerializeable() { x := e.p.NewValue1(c.Pos, OpStoreReg, c.Type, c) // Allocate a temp location to spill a register to. @@ -2796,16 +2943,18 @@ type liveInfo struct { // computeLive computes a map from block ID to a list of value IDs live at the end // of that block. Together with the value ID is a count of how many instructions // to the next use of that value. The resulting map is stored in s.live. -// computeLive also computes the desired register information at the end of each block. -// This desired register information is stored in s.desired. -// TODO: this could be quadratic if lots of variables are live across lots of -// basic blocks. Figure out a way to make this function (or, more precisely, the user -// of this function) require only linear size & time. func (s *regAllocState) computeLive() { f := s.f + // single block functions do not have variables that are live across + // branches + if len(f.Blocks) == 1 { + return + } + po := f.postorder() s.live = make([][]liveInfo, f.NumBlocks()) s.desired = make([]desiredState, f.NumBlocks()) - var phis []*Value + s.loopnest = f.loopnest() + rematIDs := make([]ID, 0, 64) live := f.newSparseMapPos(f.NumValues()) @@ -2813,31 +2962,63 @@ func (s *regAllocState) computeLive() { t := f.newSparseMapPos(f.NumValues()) defer f.retSparseMapPos(t) - // Keep track of which value we want in each register. - var desired desiredState - - // Instead of iterating over f.Blocks, iterate over their postordering. - // Liveness information flows backward, so starting at the end - // increases the probability that we will stabilize quickly. - // TODO: Do a better job yet. Here's one possibility: - // Calculate the dominator tree and locate all strongly connected components. - // If a value is live in one block of an SCC, it is live in all. - // Walk the dominator tree from end to beginning, just once, treating SCC - // components as single blocks, duplicated calculated liveness information - // out to all of them. - po := f.postorder() - s.loopnest = f.loopnest() s.loopnest.computeUnavoidableCalls() + + // Liveness analysis. + // This is an adapted version of the algorithm described in chapter 2.4.2 + // of Fabrice Rastello's On Sparse Intermediate Representations. + // https://web.archive.org/web/20240417212122if_/https://inria.hal.science/hal-00761555/file/habilitation.pdf#section.50 + // + // For our implementation, we fall back to a traditional iterative algorithm when we encounter + // Irreducible CFGs. They are very uncommon in Go code because they need to be constructed with + // gotos and our current loopnest definition does not compute all the information that + // we'd need to compute the loop ancestors for that step of the algorithm. + // + // Additionally, instead of only considering non-loop successors in the initial DFS phase, + // we compute the liveout as the union of all successors. This larger liveout set is a subset + // of the final liveout for the block and adding this information in the DFS phase means that + // we get slightly more accurate distance information. + var loopLiveIn map[*loop][]liveInfo + var numCalls []int32 + if len(s.loopnest.loops) > 0 && !s.loopnest.hasIrreducible { + loopLiveIn = make(map[*loop][]liveInfo) + numCalls = f.Cache.allocInt32Slice(f.NumBlocks()) + defer f.Cache.freeInt32Slice(numCalls) + } + for { changed := false for _, b := range po { // Start with known live values at the end of the block. - // Add len(b.Values) to adjust from end-of-block distance - // to beginning-of-block distance. live.clear() for _, e := range s.live[b.ID] { - live.set(e.ID, e.dist+int32(len(b.Values)), e.pos) + live.set(e.ID, e.dist, e.pos) + } + update := false + // arguments to phi nodes are live at this blocks out + for _, e := range b.Succs { + succ := e.b + delta := branchDistance(b, succ) + for _, v := range succ.Values { + if v.Op != OpPhi { + break + } + arg := v.Args[e.i] + if s.values[arg.ID].needReg && (!live.contains(arg.ID) || delta < live.get(arg.ID)) { + live.set(arg.ID, delta, v.Pos) + update = true + } + } + } + if update { + s.live[b.ID] = updateLive(live, s.live[b.ID]) + } + // Add len(b.Values) to adjust from end-of-block distance + // to beginning-of-block distance. + c := live.contents() + for i := range c { + c[i].val += int32(len(b.Values)) } // Mark control values as live @@ -2847,18 +3028,16 @@ func (s *regAllocState) computeLive() { } } - // Propagate backwards to the start of the block - // Assumes Values have been scheduled. - phis = phis[:0] for i := len(b.Values) - 1; i >= 0; i-- { v := b.Values[i] live.remove(v.ID) if v.Op == OpPhi { - // save phi ops for later - phis = append(phis, v) continue } if opcodeTable[v.Op].call { + if numCalls != nil { + numCalls[b.ID]++ + } rematIDs = rematIDs[:0] c := live.contents() for i := range c { @@ -2881,63 +3060,19 @@ func (s *regAllocState) computeLive() { } } } - // Propagate desired registers backwards. - desired.copy(&s.desired[b.ID]) - for i := len(b.Values) - 1; i >= 0; i-- { - v := b.Values[i] - prefs := desired.remove(v.ID) - if v.Op == OpPhi { - // TODO: if v is a phi, save desired register for phi inputs. - // For now, we just drop it and don't propagate - // desired registers back though phi nodes. - continue - } - regspec := s.regspec(v) - // Cancel desired registers if they get clobbered. - desired.clobber(regspec.clobbers) - // Update desired registers if there are any fixed register inputs. - for _, j := range regspec.inputs { - if countRegs(j.regs) != 1 { - continue - } - desired.clobber(j.regs) - desired.add(v.Args[j.idx].ID, pickReg(j.regs)) - } - // Set desired register of input 0 if this is a 2-operand instruction. - if opcodeTable[v.Op].resultInArg0 || v.Op == OpAMD64ADDQconst || v.Op == OpAMD64ADDLconst || v.Op == OpSelect0 { - // ADDQconst is added here because we want to treat it as resultInArg0 for - // the purposes of desired registers, even though it is not an absolute requirement. - // This is because we'd rather implement it as ADDQ instead of LEAQ. - // Same for ADDLconst - // Select0 is added here to propagate the desired register to the tuple-generating instruction. - if opcodeTable[v.Op].commutative { - desired.addList(v.Args[1].ID, prefs) - } - desired.addList(v.Args[0].ID, prefs) + // This is a loop header, save our live-in so that + // we can use it to fill in the loop bodies later + if loopLiveIn != nil { + loop := s.loopnest.b2l[b.ID] + if loop != nil && loop.header.ID == b.ID { + loopLiveIn[loop] = updateLive(live, nil) } } - // For each predecessor of b, expand its list of live-at-end values. - // invariant: live contains the values live at the start of b (excluding phi inputs) - for i, e := range b.Preds { + // invariant: live contains the values live at the start of b + for _, e := range b.Preds { p := e.b - // Compute additional distance for the edge. - // Note: delta must be at least 1 to distinguish the control - // value use from the first user in a successor block. - delta := int32(normalDistance) - if len(p.Succs) == 2 { - if p.Succs[0].b == b && p.Likely == BranchLikely || - p.Succs[1].b == b && p.Likely == BranchUnlikely { - delta = likelyDistance - } - if p.Succs[0].b == b && p.Likely == BranchUnlikely || - p.Succs[1].b == b && p.Likely == BranchLikely { - delta = unlikelyDistance - } - } - - // Update any desired registers at the end of p. - s.desired[p.ID].merge(&desired) + delta := branchDistance(p, b) // Start t off with the previously known live values at the end of p. t.clear() @@ -2954,68 +3089,336 @@ func (s *regAllocState) computeLive() { t.set(e.key, d, e.pos) } } - // Also add the correct arg from the saved phi values. - // All phis are at distance delta (we consider them - // simultaneously happening at the start of the block). - for _, v := range phis { - id := v.Args[i].ID - if s.values[id].needReg && (!t.contains(id) || delta < t.get(id)) { - update = true - t.set(id, delta, v.Pos) - } - } if !update { continue } - // The live set has changed, update it. - l := s.live[p.ID][:0] - if cap(l) < t.size() { - l = make([]liveInfo, 0, t.size()) - } - for _, e := range t.contents() { - l = append(l, liveInfo{e.key, e.val, e.pos}) - } - s.live[p.ID] = l + s.live[p.ID] = updateLive(t, s.live[p.ID]) changed = true } } + // Doing a traditional iterative algorithm and have run + // out of changes if !changed { break } + + // Doing a pre-pass and will fill in the liveness information + // later + if loopLiveIn != nil { + break + } + // For loopless code, we have full liveness info after a single + // iteration + if len(s.loopnest.loops) == 0 { + break + } } if f.pass.debug > regDebug { - fmt.Println("live values at end of each block") - for _, b := range f.Blocks { - fmt.Printf(" %s:", b) - for _, x := range s.live[b.ID] { - fmt.Printf(" v%d(%d)", x.ID, x.dist) - for _, e := range s.desired[b.ID].entries { - if e.ID != x.ID { + s.debugPrintLive("after dfs walk", f, s.live, s.desired) + } + + // irreducible CFGs and functions without loops are already + // done, compute their desired registers and return + if loopLiveIn == nil { + s.computeDesired() + return + } + + // Walk the loopnest from outer to inner, adding + // all live-in values from their parent. Instead of + // a recursive algorithm, iterate in depth order. + // TODO(dmo): can we permute the loopnest? can we avoid this copy? + loops := slices.Clone(s.loopnest.loops) + slices.SortFunc(loops, func(a, b *loop) int { + return cmp.Compare(a.depth, b.depth) + }) + + loopset := f.newSparseMapPos(f.NumValues()) + defer f.retSparseMapPos(loopset) + for _, loop := range loops { + if loop.outer == nil { + continue + } + livein := loopLiveIn[loop] + loopset.clear() + for _, l := range livein { + loopset.set(l.ID, l.dist, l.pos) + } + update := false + for _, l := range loopLiveIn[loop.outer] { + if !loopset.contains(l.ID) { + loopset.set(l.ID, l.dist, l.pos) + update = true + } + } + if update { + loopLiveIn[loop] = updateLive(loopset, livein) + } + } + // unknownDistance is a sentinel value for when we know a variable + // is live at any given block, but we do not yet know how far until it's next + // use. The distance will be computed later. + const unknownDistance = -1 + + // add live-in values of the loop headers to their children. + // This includes the loop headers themselves, since they can have values + // that die in the middle of the block and aren't live-out + for _, b := range po { + loop := s.loopnest.b2l[b.ID] + if loop == nil { + continue + } + headerLive := loopLiveIn[loop] + loopset.clear() + for _, l := range s.live[b.ID] { + loopset.set(l.ID, l.dist, l.pos) + } + update := false + for _, l := range headerLive { + if !loopset.contains(l.ID) { + loopset.set(l.ID, unknownDistance, src.NoXPos) + update = true + } + } + if update { + s.live[b.ID] = updateLive(loopset, s.live[b.ID]) + } + } + if f.pass.debug > regDebug { + s.debugPrintLive("after live loop prop", f, s.live, s.desired) + } + // Filling in liveness from loops leaves some blocks with no distance information + // Run over them and fill in the information from their successors. + // To stabilize faster, we quit when no block has missing values and we only + // look at blocks that still have missing values in subsequent iterations + unfinishedBlocks := f.Cache.allocBlockSlice(len(po)) + defer f.Cache.freeBlockSlice(unfinishedBlocks) + copy(unfinishedBlocks, po) + + for len(unfinishedBlocks) > 0 { + n := 0 + for _, b := range unfinishedBlocks { + live.clear() + unfinishedValues := 0 + for _, l := range s.live[b.ID] { + if l.dist == unknownDistance { + unfinishedValues++ + } + live.set(l.ID, l.dist, l.pos) + } + update := false + for _, e := range b.Succs { + succ := e.b + for _, l := range s.live[succ.ID] { + if !live.contains(l.ID) || l.dist == unknownDistance { continue } - fmt.Printf("[") - first := true - for _, r := range e.regs { - if r == noRegister { - continue - } - if !first { - fmt.Printf(",") - } - fmt.Print(&s.registers[r]) - first = false + dist := int32(len(succ.Values)) + l.dist + branchDistance(b, succ) + dist += numCalls[succ.ID] * unlikelyDistance + val := live.get(l.ID) + switch { + case val == unknownDistance: + unfinishedValues-- + fallthrough + case dist < val: + update = true + live.set(l.ID, dist, l.pos) + } + } + } + if update { + s.live[b.ID] = updateLive(live, s.live[b.ID]) + } + if unfinishedValues > 0 { + unfinishedBlocks[n] = b + n++ + } + } + unfinishedBlocks = unfinishedBlocks[:n] + } + + // Sort live values in order of their nearest next use. + // Useful for promoting values to registers, nearest use first. + for _, b := range f.Blocks { + slices.SortFunc(s.live[b.ID], func(a, b liveInfo) int { + if a.dist != b.dist { + return cmp.Compare(a.dist, b.dist) + } + return cmp.Compare(a.ID, b.ID) // for deterministic sorting + }) + } + + s.computeDesired() + + if f.pass.debug > regDebug { + s.debugPrintLive("final", f, s.live, s.desired) + } +} + +// computeDesired computes the desired register information at the end of each block. +// It is essentially a liveness analysis on machine registers instead of SSA values +// The desired register information is stored in s.desired. +func (s *regAllocState) computeDesired() { + + // TODO: Can we speed this up using the liveness information we have already + // from computeLive? + var desired desiredState + f := s.f + po := f.postorder() + maxPreds := 0 + for _, b := range f.Blocks { + maxPreds = max(maxPreds, len(b.Preds)) + } + // phiPrefs[i] collects desired registers for phi inputs coming from b.Preds[i]. + phiPrefs := make([]desiredState, maxPreds) + for { + changed := false + for _, b := range po { + desired.copy(&s.desired[b.ID]) + for i := range b.Preds { + phiPrefs[i].reset() + } + var headerLoop *loop // loop whose header is b, if any + if l := s.loopnest.b2l[b.ID]; l != nil && l.header == b { + headerLoop = l + } + // Process non-phis, then phis. + i := len(b.Values) - 1 + for ; i >= 0; i-- { + v := b.Values[i] + if v.Op == OpPhi { + break + } + prefs := desired.remove(v.ID) + regspec := s.regspec(v) + // Cancel desired registers if they get clobbered. + desired.clobber(regspec.clobbers) + // Update desired registers if there are any fixed register inputs. + for _, j := range regspec.inputs { + if countRegs(j.regs) != 1 { + continue + } + desired.clobber(j.regs) + desired.add(v.Args[j.idx].ID, s.pickReg(j.regs)) + } + // Set desired register of input 0 if this is a 2-operand instruction. + if opcodeTable[v.Op].resultInArg0 || v.Op == OpAMD64ADDQconst || v.Op == OpAMD64ADDLconst || v.Op == OpSelect0 { + // ADDQconst is added here because we want to treat it as resultInArg0 for + // the purposes of desired registers, even though it is not an absolute requirement. + // This is because we'd rather implement it as ADDQ instead of LEAQ. + // Same for ADDLconst + // Select0 is added here to propagate the desired register to the tuple-generating instruction. + if opcodeTable[v.Op].commutative { + desired.addList(v.Args[1].ID, prefs) + } + desired.addList(v.Args[0].ID, prefs) + } + } + for ; i >= 0; i-- { + v := b.Values[i] + prefs := desired.remove(v.ID) + if prefs[0] == noRegister { + continue + } + // Phi desires go to phiPrefs (per-pred), so drop them from desired.avoid. + // The merge below re-adds any bits other entries still need. + for _, r := range prefs { + if r != noRegister { + desired.avoid = desired.avoid.minus(regMaskAt(r)) + } + } + // Propagate v's desired registers back to its args. + for pidx, a := range v.Args { + if headerLoop != nil && s.loopnest.b2l[b.Preds[pidx].b.ID] == headerLoop { + // Skip direct back-edges to avoid pessimizing the loop body to skip a single reg-reg move. + // We check only the immediate loop; it is simple and empirically sufficient. + continue } - fmt.Printf("]") + phiPrefs[pidx].addList(a.ID, prefs) } } - if avoid := s.desired[b.ID].avoid; avoid != 0 { - fmt.Printf(" avoid=%v", s.RegMaskString(avoid)) + for pidx, e := range b.Preds { + p := e.b + changed = s.desired[p.ID].merge(&desired) || changed + changed = s.desired[p.ID].merge(&phiPrefs[pidx]) || changed } - fmt.Println() + } + if !changed || (!s.loopnest.hasIrreducible && len(s.loopnest.loops) == 0) { + break + } + } +} + +// updateLive updates a given liveInfo slice with the contents of t +func updateLive(t *sparseMapPos, live []liveInfo) []liveInfo { + live = live[:0] + if cap(live) < t.size() { + live = make([]liveInfo, 0, t.size()) + } + for _, e := range t.contents() { + live = append(live, liveInfo{e.key, e.val, e.pos}) + } + return live +} + +// branchDistance calculates the distance between a block and a +// successor in pseudo-instructions. This is used to indicate +// likeliness +func branchDistance(b *Block, s *Block) int32 { + if len(b.Succs) == 2 { + if b.Succs[0].b == s && b.Likely == BranchLikely || + b.Succs[1].b == s && b.Likely == BranchUnlikely { + return likelyDistance + } + if b.Succs[0].b == s && b.Likely == BranchUnlikely || + b.Succs[1].b == s && b.Likely == BranchLikely { + return unlikelyDistance } } + // Note: the branch distance must be at least 1 to distinguish the control + // value use from the first user in a successor block. + return normalDistance +} + +func (s *regAllocState) debugPrintLive(stage string, f *Func, live [][]liveInfo, desired []desiredState) { + fmt.Printf("%s: live values at end of each block: %s\n", stage, f.Name) + for _, b := range f.Blocks { + s.debugPrintLiveBlock(b, live[b.ID], &desired[b.ID]) + } +} + +func (s *regAllocState) debugPrintLiveBlock(b *Block, live []liveInfo, desired *desiredState) { + fmt.Printf(" %s:", b) + slices.SortFunc(live, func(a, b liveInfo) int { + return cmp.Compare(a.ID, b.ID) + }) + for _, x := range live { + fmt.Printf(" v%d(%d)", x.ID, x.dist) + for _, e := range desired.entries { + if e.ID != x.ID { + continue + } + fmt.Printf("[") + first := true + for _, r := range e.regs { + if r == noRegister { + continue + } + if !first { + fmt.Printf(",") + } + fmt.Print(&s.registers[r]) + first = false + } + fmt.Printf("]") + } + } + if avoid := desired.avoid; !avoid.empty() { + fmt.Printf(" avoid=%v", s.RegMaskString(avoid)) + } + fmt.Println() } // A desiredState represents desired register assignments. @@ -3052,7 +3455,7 @@ func (d *desiredState) get(vid ID) [4]register { // add records that we'd like value vid to be in register r. func (d *desiredState) add(vid ID, r register) { - d.avoid |= regMask(1) << r + d.avoid = d.avoid.addReg(r) for i := range d.entries { e := &d.entries[i] if e.ID != vid { @@ -3093,7 +3496,7 @@ func (d *desiredState) clobber(m regMask) { e := &d.entries[i] j := 0 for _, r := range e.regs { - if r != noRegister && m>>r&1 == 0 { + if r != noRegister && !m.hasReg(r) { e.regs[j] = r j++ } @@ -3109,7 +3512,13 @@ func (d *desiredState) clobber(m regMask) { } i++ } - d.avoid &^= m + d.avoid = d.avoid.minus(m) +} + +// reset prepares d for re-use. +func (d *desiredState) reset() { + d.entries = d.entries[:0] + d.avoid = regMask{} } // copy copies a desired state from another desiredState x. @@ -3131,14 +3540,17 @@ func (d *desiredState) remove(vid ID) [4]register { return [4]register{noRegister, noRegister, noRegister, noRegister} } -// merge merges another desired state x into d. -func (d *desiredState) merge(x *desiredState) { - d.avoid |= x.avoid +// merge merges another desired state x into d. Returns whether the set has +// changed +func (d *desiredState) merge(x *desiredState) bool { + oldAvoid := d.avoid + d.avoid = d.avoid.union(x.avoid) // There should only be a few desired registers, so // linear insert is ok. for _, e := range x.entries { d.addList(e.ID, e.regs) } + return oldAvoid != d.avoid } // computeUnavoidableCalls computes the containsUnavoidableCall fields in the loop nest. diff --git a/src/cmd/compile/internal/ssa/regalloc_test.go b/src/cmd/compile/internal/ssa/regalloc_test.go index 12f5820f1ff81d..1fd06a34cc1f9a 100644 --- a/src/cmd/compile/internal/ssa/regalloc_test.go +++ b/src/cmd/compile/internal/ssa/regalloc_test.go @@ -346,3 +346,191 @@ func TestRematerializeableRegCompatible(t *testing.T) { t.Errorf("Expects an Copy to be issued, but got: %+v", f.f) } } + +func TestPreload(t *testing.T) { + c := testConfig(t) + // amd64 has 13 general registers. We use 1 for ptr and 12 for x0-11. + // They all contain live values at the end of the entry block. + f := c.Fun("entry", + Bloc("entry", + Valu("ptr", OpArgIntReg, c.config.Types.Int8.PtrTo(), 0, &AuxNameOffset{Name: c.Temp(c.config.Types.Int8.PtrTo()), Offset: 0}), + Valu("mem", OpInitMem, types.TypeMem, 0, nil), + Valu("x0", OpAMD64MOVBload, c.config.Types.Int8, 0, nil, "ptr", "mem"), + Valu("x1", OpAMD64MOVBload, c.config.Types.Int8, 1, nil, "ptr", "mem"), + Valu("x2", OpAMD64MOVBload, c.config.Types.Int8, 2, nil, "ptr", "mem"), + Valu("x3", OpAMD64MOVBload, c.config.Types.Int8, 3, nil, "ptr", "mem"), + Valu("x4", OpAMD64MOVBload, c.config.Types.Int8, 4, nil, "ptr", "mem"), + Valu("x5", OpAMD64MOVBload, c.config.Types.Int8, 5, nil, "ptr", "mem"), + Valu("x6", OpAMD64MOVBload, c.config.Types.Int8, 6, nil, "ptr", "mem"), + Valu("x7", OpAMD64MOVBload, c.config.Types.Int8, 7, nil, "ptr", "mem"), + Valu("x8", OpAMD64MOVBload, c.config.Types.Int8, 8, nil, "ptr", "mem"), + Valu("x9", OpAMD64MOVBload, c.config.Types.Int8, 9, nil, "ptr", "mem"), + Valu("x10", OpAMD64MOVBload, c.config.Types.Int8, 10, nil, "ptr", "mem"), + Valu("x11", OpAMD64MOVBload, c.config.Types.Int8, 11, nil, "ptr", "mem"), + Valu("init", OpAMD64MOVQconst, c.config.Types.Int64, 0, nil), + Goto("loopHead"), + ), + Bloc("loopHead", + Valu("phi", OpPhi, c.config.Types.Int64, 0, nil, "init", "next"), + Valu("test", OpAMD64CMPQconst, types.TypeFlags, 10, nil, "phi"), + Lt("test", "loopBody", "exit"), + ), + Bloc("loopBody", + Valu("next", OpAMD64ADDQconst, c.config.Types.Int64, 1, nil, "phi"), + Goto("loopHead"), + ), + Bloc("exit", + Valu("m0", OpAMD64MOVBstore, types.TypeMem, 0, nil, "ptr", "x0", "mem"), + Valu("m1", OpAMD64MOVBstore, types.TypeMem, 1, nil, "ptr", "x1", "m0"), + Valu("m2", OpAMD64MOVBstore, types.TypeMem, 2, nil, "ptr", "x2", "m1"), + Valu("m3", OpAMD64MOVBstore, types.TypeMem, 3, nil, "ptr", "x3", "m2"), + Valu("m4", OpAMD64MOVBstore, types.TypeMem, 4, nil, "ptr", "x4", "m3"), + Valu("m5", OpAMD64MOVBstore, types.TypeMem, 5, nil, "ptr", "x5", "m4"), + Valu("m6", OpAMD64MOVBstore, types.TypeMem, 6, nil, "ptr", "x6", "m5"), + Valu("m7", OpAMD64MOVBstore, types.TypeMem, 7, nil, "ptr", "x7", "m6"), + Valu("m8", OpAMD64MOVBstore, types.TypeMem, 8, nil, "ptr", "x8", "m7"), + Valu("m9", OpAMD64MOVBstore, types.TypeMem, 9, nil, "ptr", "x9", "m8"), + Valu("m10", OpAMD64MOVBstore, types.TypeMem, 10, nil, "ptr", "x10", "m9"), + Valu("m11", OpAMD64MOVBstore, types.TypeMem, 11, nil, "ptr", "x11", "m10"), + Ret("m11"), + ), + ) + f.f.Blocks[1].Likely = BranchLikely + regalloc(f.f) + checkFunc(f.f) + + v := f.values["phi"] + loc := f.f.RegAlloc[v.ID] + if _, ok := loc.(*Register); !ok { + t.Errorf("Expects to use a register for phi, but got: %s\n%v", loc, f.f) + } +} + +// TestStartRegsDrop tests dropping physical register bits from startRegs preventing +// unnecessary OpLoadReg on edges, such as edge right->merge in this example. +// +// entry -> left (no pressure) -> merge (startRegs updated) -> exit +// -> right (pressure) -> +func TestStartRegsDrop(t *testing.T) { + c := testConfig(t) + + f := c.Fun("entry", + Bloc("entry", + Valu("mem", OpInitMem, types.TypeMem, 0, nil), + Valu("ptr", OpArg, c.config.Types.Int64.PtrTo(), 0, c.Temp(c.config.Types.Int64)), + // Non-phi values that will be originally in registers and get into startRegs[merge] + Valu("u0", OpAMD64MOVQload, c.config.Types.Int64, 100, nil, "ptr", "mem"), + Valu("u1", OpAMD64MOVQload, c.config.Types.Int64, 108, nil, "ptr", "mem"), + Valu("u2", OpAMD64MOVQload, c.config.Types.Int64, 116, nil, "ptr", "mem"), + Valu("u3", OpAMD64MOVQload, c.config.Types.Int64, 124, nil, "ptr", "mem"), + Valu("u4", OpAMD64MOVQload, c.config.Types.Int64, 132, nil, "ptr", "mem"), + Valu("u5", OpAMD64MOVQload, c.config.Types.Int64, 140, nil, "ptr", "mem"), + Valu("u6", OpAMD64MOVQload, c.config.Types.Int64, 148, nil, "ptr", "mem"), + Valu("u7", OpAMD64MOVQload, c.config.Types.Int64, 156, nil, "ptr", "mem"), + // Some phi value + Valu("v0", OpAMD64MOVQload, c.config.Types.Int64, 0, nil, "ptr", "mem"), + // Branch + Valu("cond", OpAMD64MOVLconst, c.config.Types.Int32, 1, nil), + Valu("test", OpAMD64TESTL, types.TypeFlags, 0, nil, "cond", "cond"), + Eq("test", "left", "right"), + ), + Bloc("left", + // No register pressure - values stay in their original registers + // This is the "primary" predecessor of merge block (less spill live) + Goto("merge"), + ), + Bloc("right", + // Create some register pressure. We want to make difference in this block's endRegs, + // so that at shuffle stage, the updated startRegs of merge block will be measurable. + Valu("r0", OpAMD64MOVQload, c.config.Types.Int64, 200, nil, "ptr", "mem"), + Valu("r1", OpAMD64MOVQload, c.config.Types.Int64, 208, nil, "ptr", "mem"), + Valu("r2", OpAMD64MOVQload, c.config.Types.Int64, 216, nil, "ptr", "mem"), + Valu("r3", OpAMD64MOVQload, c.config.Types.Int64, 224, nil, "ptr", "mem"), + Valu("r4", OpAMD64MOVQload, c.config.Types.Int64, 232, nil, "ptr", "mem"), + Valu("r5", OpAMD64MOVQload, c.config.Types.Int64, 240, nil, "ptr", "mem"), + Valu("r6", OpAMD64MOVQload, c.config.Types.Int64, 248, nil, "ptr", "mem"), + Valu("r7", OpAMD64MOVQload, c.config.Types.Int64, 256, nil, "ptr", "mem"), + Valu("r8", OpAMD64MOVQload, c.config.Types.Int64, 264, nil, "ptr", "mem"), + Valu("r9", OpAMD64MOVQload, c.config.Types.Int64, 272, nil, "ptr", "mem"), + Valu("r10", OpAMD64MOVQload, c.config.Types.Int64, 280, nil, "ptr", "mem"), + Valu("r11", OpAMD64MOVQload, c.config.Types.Int64, 288, nil, "ptr", "mem"), + Valu("r12", OpAMD64MOVQload, c.config.Types.Int64, 296, nil, "ptr", "mem"), + Valu("r13", OpAMD64MOVQload, c.config.Types.Int64, 304, nil, "ptr", "mem"), + Valu("r14", OpAMD64MOVQload, c.config.Types.Int64, 312, nil, "ptr", "mem"), + Valu("r15", OpAMD64MOVQload, c.config.Types.Int64, 320, nil, "ptr", "mem"), + Valu("sum0", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "r0", "r1"), + Valu("sum1", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "r2", "r3"), + Valu("sum2", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "r4", "r5"), + Valu("sum3", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "r6", "r7"), + Valu("sum4", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "r8", "r9"), + Valu("sum5", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "r10", "r11"), + Valu("sum6", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "r12", "r13"), + Valu("sum7", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "r14", "r15"), + Valu("store0", OpAMD64MOVQstore, types.TypeMem, 400, nil, "ptr", "sum0", "mem"), + Valu("store1", OpAMD64MOVQstore, types.TypeMem, 408, nil, "ptr", "sum1", "store0"), + Valu("store2", OpAMD64MOVQstore, types.TypeMem, 416, nil, "ptr", "sum2", "store1"), + Valu("store3", OpAMD64MOVQstore, types.TypeMem, 424, nil, "ptr", "sum3", "store2"), + Valu("store4", OpAMD64MOVQstore, types.TypeMem, 432, nil, "ptr", "sum4", "store3"), + Valu("store5", OpAMD64MOVQstore, types.TypeMem, 440, nil, "ptr", "sum5", "store4"), + Valu("store6", OpAMD64MOVQstore, types.TypeMem, 448, nil, "ptr", "sum6", "store5"), + Valu("store7", OpAMD64MOVQstore, types.TypeMem, 456, nil, "ptr", "sum7", "store6"), + Goto("merge"), + ), + Bloc("merge", + // One phi (for v0) + Valu("p0", OpPhi, c.config.Types.Int64, 0, nil, "v0", "v0"), + // New values to evict the most distant uses in the end of this block + Valu("n0", OpAMD64MOVQload, c.config.Types.Int64, 500, nil, "ptr", "mem"), + Valu("n1", OpAMD64MOVQload, c.config.Types.Int64, 508, nil, "ptr", "mem"), + Valu("n2", OpAMD64MOVQload, c.config.Types.Int64, 516, nil, "ptr", "mem"), + Valu("n3", OpAMD64MOVQload, c.config.Types.Int64, 524, nil, "ptr", "mem"), + Valu("n4", OpAMD64MOVQload, c.config.Types.Int64, 532, nil, "ptr", "mem"), + Valu("n5", OpAMD64MOVQload, c.config.Types.Int64, 540, nil, "ptr", "mem"), + Valu("n6", OpAMD64MOVQload, c.config.Types.Int64, 548, nil, "ptr", "mem"), + Valu("n7", OpAMD64MOVQload, c.config.Types.Int64, 556, nil, "ptr", "mem"), + Valu("n8", OpAMD64MOVQload, c.config.Types.Int64, 564, nil, "ptr", "mem"), + Valu("n9", OpAMD64MOVQload, c.config.Types.Int64, 572, nil, "ptr", "mem"), + Valu("n10", OpAMD64MOVQload, c.config.Types.Int64, 580, nil, "ptr", "mem"), + Valu("n11", OpAMD64MOVQload, c.config.Types.Int64, 588, nil, "ptr", "mem"), + Valu("n12", OpAMD64MOVQload, c.config.Types.Int64, 596, nil, "ptr", "mem"), + Valu("n13", OpAMD64MOVQload, c.config.Types.Int64, 604, nil, "ptr", "mem"), + // Normal uses before we start to evict / clean up startRegs mask + Valu("a0", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "n0", "n1"), + Valu("a1", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "n2", "n3"), + Valu("a2", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "n4", "n5"), + Valu("a3", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "n6", "n7"), + Valu("a4", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "n8", "n9"), + Valu("a5", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "n10", "n11"), + Valu("a6", OpAMD64ADDQ, c.config.Types.Int64, 0, nil, "n12", "n13"), + Valu("s0", OpAMD64MOVQstore, types.TypeMem, 0, nil, "ptr", "a0", "mem"), + Valu("s1", OpAMD64MOVQstore, types.TypeMem, 8, nil, "ptr", "a1", "s0"), + Valu("s2", OpAMD64MOVQstore, types.TypeMem, 16, nil, "ptr", "a2", "s1"), + Valu("s3", OpAMD64MOVQstore, types.TypeMem, 24, nil, "ptr", "a3", "s2"), + Valu("s4", OpAMD64MOVQstore, types.TypeMem, 32, nil, "ptr", "a4", "s3"), + Valu("s5", OpAMD64MOVQstore, types.TypeMem, 40, nil, "ptr", "a5", "s4"), + Valu("s6", OpAMD64MOVQstore, types.TypeMem, 48, nil, "ptr", "a6", "s5"), + // The distant uses - to be evicted and cleaned up from the startRegs mask + Valu("t0", OpAMD64MOVQstore, types.TypeMem, 100, nil, "ptr", "u0", "s6"), + Valu("t1", OpAMD64MOVQstore, types.TypeMem, 108, nil, "ptr", "u1", "t0"), + Valu("t2", OpAMD64MOVQstore, types.TypeMem, 116, nil, "ptr", "u2", "t1"), + Valu("t3", OpAMD64MOVQstore, types.TypeMem, 124, nil, "ptr", "u3", "t2"), + Valu("t4", OpAMD64MOVQstore, types.TypeMem, 132, nil, "ptr", "u4", "t3"), + Valu("t5", OpAMD64MOVQstore, types.TypeMem, 140, nil, "ptr", "u5", "t4"), + Valu("t6", OpAMD64MOVQstore, types.TypeMem, 148, nil, "ptr", "u6", "t5"), + Valu("t7", OpAMD64MOVQstore, types.TypeMem, 156, nil, "ptr", "u7", "t6"), + Exit("t7"), + ), + ) + + regalloc(f.f) + checkFunc(f.f) + + leftLoadCount := numOps(f.blocks["left"], OpLoadReg) + rightLoadCount := numOps(f.blocks["right"], OpLoadReg) + t.Logf("OpLoadReg count in left: %d, right: %d", leftLoadCount, rightLoadCount) + + // Without startRegs mask cleanup we would have some dead LoadRegs added by shuffle + if rightLoadCount > 8 { + t.Errorf("expected <= 8 OpLoadReg in right block (got %d)", rightLoadCount) + } +} diff --git a/src/cmd/compile/internal/ssa/rewrite.go b/src/cmd/compile/internal/ssa/rewrite.go index 9ea735a67d4b7f..78a576df514a18 100644 --- a/src/cmd/compile/internal/ssa/rewrite.go +++ b/src/cmd/compile/internal/ssa/rewrite.go @@ -57,11 +57,15 @@ func applyRewrite(f *Func, rb blockRewriter, rv valueRewriter, deadcode deadValu var iters int var states map[string]bool for { + if debug > 1 { + fmt.Printf("%s: iter %d\n", f.pass.name, iters) + } change := false deadChange := false for _, b := range f.Blocks { var b0 *Block if debug > 1 { + fmt.Printf("%s: start block\n", f.pass.name) b0 = new(Block) *b0 = *b b0.Succs = append([]Edge{}, b.Succs...) // make a new copy, not aliasing @@ -79,6 +83,9 @@ func applyRewrite(f *Func, rb blockRewriter, rv valueRewriter, deadcode deadValu } } for j, v := range b.Values { + if debug > 1 { + fmt.Printf("%s: consider %v\n", f.pass.name, v.LongString()) + } var v0 *Value if debug > 1 { v0 = new(Value) @@ -473,7 +480,7 @@ func isSpecializedMalloc(aux Aux) bool { name := fn.String() return strings.HasPrefix(name, "runtime.mallocgcSmallNoScanSC") || strings.HasPrefix(name, "runtime.mallocgcSmallScanNoHeaderSC") || - strings.HasPrefix(name, "runtime.mallocTiny") + strings.HasPrefix(name, "runtime.mallocgcTinySC") } // canLoadUnaligned reports if the architecture supports unaligned load operations. @@ -511,22 +518,17 @@ func log32(n int32) int64 { return log32u(uint32(n)) } func log64(n int64) int64 { return log64u(uint64(n)) } // logXu returns the logarithm of n base 2. -// n must be a power of 2 (isUnsignedPowerOfTwo returns true) +// n must be a power of 2 (isPowerOfTwo returns true) func log8u(n uint8) int64 { return int64(bits.Len8(n)) - 1 } func log16u(n uint16) int64 { return int64(bits.Len16(n)) - 1 } func log32u(n uint32) int64 { return int64(bits.Len32(n)) - 1 } func log64u(n uint64) int64 { return int64(bits.Len64(n)) - 1 } // isPowerOfTwoX functions report whether n is a power of 2. -func isPowerOfTwo[T int8 | int16 | int32 | int64](n T) bool { +func isPowerOfTwo[T int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64](n T) bool { return n > 0 && n&(n-1) == 0 } -// isUnsignedPowerOfTwo reports whether n is an unsigned power of 2. -func isUnsignedPowerOfTwo[T uint8 | uint16 | uint32 | uint64](n T) bool { - return n != 0 && n&(n-1) == 0 -} - // is32Bit reports whether n can be represented as a signed 32 bit integer. func is32Bit(n int64) bool { return n == int64(int32(n)) @@ -679,6 +681,9 @@ func auxIntToInt64(i int64) int64 { func auxIntToUint8(i int64) uint8 { return uint8(i) } +func auxIntToUint64(i int64) uint64 { + return uint64(i) +} func auxIntToFloat32(i int64) float32 { return float32(math.Float64frombits(uint64(i))) } @@ -731,6 +736,9 @@ func int64ToAuxInt(i int64) int64 { func uint8ToAuxInt(i uint8) int64 { return int64(int8(i)) } +func uint64ToAuxInt(i uint64) int64 { + return int64(i) +} func float32ToAuxInt(f float32) int64 { return int64(math.Float64bits(float64(f))) } @@ -757,6 +765,7 @@ func arm64ConditionalParamsToAuxInt(v arm64ConditionalParams) int64 { i |= int64(v.cond) return i } + func flagConstantToAuxInt(x flagConstant) int64 { return int64(x) } @@ -785,6 +794,14 @@ func (stringAux) CanBeAnSSAAux() {} func auxToString(i Aux) string { return string(i.(stringAux)) } + +type int64Aux int64 + +func (int64Aux) CanBeAnSSAAux() {} + +func int64ToAux(v int64) Aux { + return int64Aux(v) +} func auxToSym(i Aux) Sym { // TODO: kind of a hack - allows nil interface through s, _ := i.(Sym) @@ -941,7 +958,8 @@ func disjointTypes(t1 *types.Type, t2 *types.Type) bool { } if !t1.IsPtr() || !t2.IsPtr() { - panic("disjointTypes: one of arguments is not a pointer") + // Treat non-pointer types (such as TFUNC, TMAP, uintptr) conservatively. + return false } t1 = t1.Elem() @@ -1101,6 +1119,20 @@ func flagArg(v *Value) *Value { return v.Args[0] } +// amd64CapAVXShift caps an AMD64 AVX vector shift amount c so that over-shifts +// always result in 0. +// +// These instructions have room for an 8-bit immediate and any value larger than +// the element width will result in 0 or -1 (for an arithmetic right shift). +// Thus, we simply cap this at 255. +func amd64CapAVXShift(auxInt int64) uint8 { + u := auxIntToUint64(auxInt) + if u > 255 { + return 255 + } + return uint8(u) +} + // arm64Negate finds the complement to an ARM64 condition code, // for example !Equal -> NotEqual or !LessThan -> GreaterEqual // @@ -1255,10 +1287,8 @@ func logRule(s string) { } ruleFile = w } - _, err := fmt.Fprintln(ruleFile, s) - if err != nil { - panic(err) - } + // Ignore errors in case of multiple processes fighting over the file. + fmt.Fprintln(ruleFile, s) } var ruleFile io.Writer @@ -1350,7 +1380,7 @@ func overlap(offset1, size1, offset2, size2 int64) bool { // check if value zeroes out upper 32-bit of 64-bit register. // depth limits recursion depth. In AMD64.rules 3 is used as limit, // because it catches same amount of cases as 4. -func zeroUpper32Bits(x *Value, depth int) bool { +func ZeroUpper32Bits(x *Value, depth int) bool { if x.Type.IsSigned() && x.Type.Size() < 8 { // If the value is signed, it might get re-sign-extended // during spill and restore. See issue 68227. @@ -1367,6 +1397,8 @@ func zeroUpper32Bits(x *Value, depth int) bool { OpAMD64SHRL, OpAMD64SHRLconst, OpAMD64SARL, OpAMD64SARLconst, OpAMD64SHLL, OpAMD64SHLLconst: return true + case OpAMD64MOVQconst: + return uint64(uint32(x.AuxInt)) == uint64(x.AuxInt) case OpARM64REV16W, OpARM64REVW, OpARM64RBITW, OpARM64CLZW, OpARM64EXTRWconst, OpARM64MULW, OpARM64MNEGW, OpARM64UDIVW, OpARM64DIVW, OpARM64UMODW, OpARM64MADDW, OpARM64MSUBW, OpARM64RORW, OpARM64RORWconst: @@ -1382,7 +1414,7 @@ func zeroUpper32Bits(x *Value, depth int) bool { return false } for i := range x.Args { - if !zeroUpper32Bits(x.Args[i], depth-1) { + if !ZeroUpper32Bits(x.Args[i], depth-1) { return false } } @@ -1392,14 +1424,16 @@ func zeroUpper32Bits(x *Value, depth int) bool { return false } -// zeroUpper48Bits is similar to zeroUpper32Bits, but for upper 48 bits. -func zeroUpper48Bits(x *Value, depth int) bool { +// ZeroUpper48Bits is similar to ZeroUpper32Bits, but for upper 48 bits. +func ZeroUpper48Bits(x *Value, depth int) bool { if x.Type.IsSigned() && x.Type.Size() < 8 { return false } switch x.Op { case OpAMD64MOVWQZX, OpAMD64MOVWload, OpAMD64MOVWloadidx1, OpAMD64MOVWloadidx2: return true + case OpAMD64MOVQconst, OpAMD64MOVLconst: + return uint64(uint16(x.AuxInt)) == uint64(x.AuxInt) case OpArg: // note: but not ArgIntReg return x.Type.Size() == 2 && x.Block.Func.Config.arch == "amd64" case OpPhi, OpSelect0, OpSelect1: @@ -1409,7 +1443,7 @@ func zeroUpper48Bits(x *Value, depth int) bool { return false } for i := range x.Args { - if !zeroUpper48Bits(x.Args[i], depth-1) { + if !ZeroUpper48Bits(x.Args[i], depth-1) { return false } } @@ -1419,14 +1453,16 @@ func zeroUpper48Bits(x *Value, depth int) bool { return false } -// zeroUpper56Bits is similar to zeroUpper32Bits, but for upper 56 bits. -func zeroUpper56Bits(x *Value, depth int) bool { +// ZeroUpper56Bits is similar to ZeroUpper32Bits, but for upper 56 bits. +func ZeroUpper56Bits(x *Value, depth int) bool { if x.Type.IsSigned() && x.Type.Size() < 8 { return false } switch x.Op { case OpAMD64MOVBQZX, OpAMD64MOVBload, OpAMD64MOVBloadidx1: return true + case OpAMD64MOVQconst, OpAMD64MOVLconst: + return uint64(uint8(x.AuxInt)) == uint64(x.AuxInt) case OpArg: // note: but not ArgIntReg return x.Type.Size() == 1 && x.Block.Func.Config.arch == "amd64" case OpPhi, OpSelect0, OpSelect1: @@ -1436,7 +1472,7 @@ func zeroUpper56Bits(x *Value, depth int) bool { return false } for i := range x.Args { - if !zeroUpper56Bits(x.Args[i], depth-1) { + if !ZeroUpper56Bits(x.Args[i], depth-1) { return false } } @@ -1476,11 +1512,13 @@ func isInlinableMemmove(dst, src *Value, sz int64, c *Config) bool { return sz <= 16 || (sz < 1024 && disjoint(dst, sz, src, sz)) case "arm64": return sz <= 64 || (sz <= 1024 && disjoint(dst, sz, src, sz)) + case "loong64": + return sz <= 16 || (sz <= 64 && disjoint(dst, sz, src, sz)) case "386": return sz <= 8 case "s390x", "ppc64", "ppc64le": return sz <= 8 || disjoint(dst, sz, src, sz) - case "arm", "loong64", "mips", "mips64", "mipsle", "mips64le": + case "arm", "mips", "mips64", "mipsle", "mips64le": return sz <= 4 } return false @@ -1946,7 +1984,7 @@ func arm64BFWidth(mask, rshift int64) int64 { return nto(shiftedMask) } -// encodes condition code and NZCV flags into auxint. +// encodes condition code and NZCV flags into result. func arm64ConditionalParamsAuxInt(cond Op, nzcv uint8) arm64ConditionalParams { if cond < OpARM64Equal || cond > OpARM64GreaterEqualU { panic("Wrong conditional operation") @@ -2163,11 +2201,11 @@ func rewriteFixedLoad(v *Value, sym Sym, sb *Value, off int64) *Value { return v case "Hash": v.reset(OpConst32) - v.AuxInt = int64(types.TypeHash(t)) + v.AuxInt = int64(int32(types.TypeHash(t))) return v case "Kind_": v.reset(OpConst8) - v.AuxInt = int64(reflectdata.ABIKindOfType(t)) + v.AuxInt = int64(int8(reflectdata.ABIKindOfType(t))) return v case "GCData": gcdata, _ := reflectdata.GCSym(t, true) @@ -2619,55 +2657,57 @@ func rewriteStructStore(v *Value) *Value { return mem } -// isDirectType reports whether v represents a type +// isDirectAndComparableType reports whether v represents a type // (a *runtime._type) whose value is stored directly in an -// interface (i.e., is pointer or pointer-like). -func isDirectType(v *Value) bool { - return isDirectType1(v) +// interface (i.e., is pointer or pointer-like) and is comparable. +func isDirectAndComparableType(v *Value) bool { + return isDirectAndComparableType1(v) } // v is a type -func isDirectType1(v *Value) bool { +func isDirectAndComparableType1(v *Value) bool { switch v.Op { case OpITab: - return isDirectType2(v.Args[0]) + return isDirectAndComparableType2(v.Args[0]) case OpAddr: lsym := v.Aux.(*obj.LSym) if ti := lsym.TypeInfo(); ti != nil { - return types.IsDirectIface(ti.Type.(*types.Type)) + t := ti.Type.(*types.Type) + return types.IsDirectIface(t) && types.IsComparable(t) } } return false } // v is an empty interface -func isDirectType2(v *Value) bool { +func isDirectAndComparableType2(v *Value) bool { switch v.Op { case OpIMake: - return isDirectType1(v.Args[0]) + return isDirectAndComparableType1(v.Args[0]) } return false } -// isDirectIface reports whether v represents an itab +// isDirectAndComparableIface reports whether v represents an itab // (a *runtime._itab) for a type whose value is stored directly -// in an interface (i.e., is pointer or pointer-like). -func isDirectIface(v *Value) bool { - return isDirectIface1(v, 9) +// in an interface (i.e., is pointer or pointer-like) and is comparable. +func isDirectAndComparableIface(v *Value) bool { + return isDirectAndComparableIface1(v, 9) } // v is an itab -func isDirectIface1(v *Value, depth int) bool { +func isDirectAndComparableIface1(v *Value, depth int) bool { if depth == 0 { return false } switch v.Op { case OpITab: - return isDirectIface2(v.Args[0], depth-1) + return isDirectAndComparableIface2(v.Args[0], depth-1) case OpAddr: lsym := v.Aux.(*obj.LSym) if ii := lsym.ItabInfo(); ii != nil { - return types.IsDirectIface(ii.Type.(*types.Type)) + t := ii.Type.(*types.Type) + return types.IsDirectIface(t) && types.IsComparable(t) } case OpConstNil: // We can treat this as direct, because if the itab is @@ -2678,16 +2718,16 @@ func isDirectIface1(v *Value, depth int) bool { } // v is an interface -func isDirectIface2(v *Value, depth int) bool { +func isDirectAndComparableIface2(v *Value, depth int) bool { if depth == 0 { return false } switch v.Op { case OpIMake: - return isDirectIface1(v.Args[0], depth-1) + return isDirectAndComparableIface1(v.Args[0], depth-1) case OpPhi: for _, a := range v.Args { - if !isDirectIface2(a, depth-1) { + if !isDirectAndComparableIface2(a, depth-1) { return false } } @@ -2764,3 +2804,98 @@ func panicBoundsCCToAux(p PanicBoundsCC) Aux { func isDictArgSym(sym Sym) bool { return sym.(*ir.Name).Sym().Name == typecheck.LocalDictName } + +// When v is (IMake typ (StructMake ...)), convert to +// (IMake typ arg) where arg is the pointer-y argument to +// the StructMake (there must be exactly one). +func imakeOfStructMake(v *Value) *Value { + var arg *Value + for _, a := range v.Args[1].Args { + if a.Type.Size() > 0 { + arg = a + break + } + } + return v.Block.NewValue2(v.Pos, OpIMake, v.Type, v.Args[0], arg) +} + +// bool2int converts bool to int: true to 1, false to 0 +func bool2int(x bool) int { + var b int + if x { + b = 1 + } + return b +} + +// rewriteCondSelectIntoMath reports whether x OP (y * constant) should be used instead of a CondSelect. +// x arbitrary, y in [0,1] +func rewriteCondSelectIntoMath(config *Config, op Op, constant int64) bool { + switch config.arch { + case "amd64": + if constant == 1 { + return true + } + switch op { + case OpAdd64, OpAdd32, OpAdd16, OpAdd8: + switch constant { + case 2, 4, 8: + // Implemented with LEA a + b * displacement form + return true + } + } + case "arm64": + switch op { + case OpAdd64, OpAdd32, OpAdd16, OpAdd8: + if constant == 1 { + return false // better done as CSINC + } + fallthrough + case OpSub64, OpSub32, OpSub16, OpSub8, + OpAnd64, OpAnd32, OpAnd16, OpAnd8, + OpOr64, OpOr32, OpOr16, OpOr8, + OpXor64, OpXor32, OpXor16, OpXor8: + // Implemented using an inline LSL + return isPowerOfTwo(uint64(constant)) + default: + if constant == 1 { + return true + } + } + default: + // TODO: fine tune for other architectures. + return constant == 1 + } + return false +} + +func addToSub(op Op) Op { + switch op { + case OpAdd64: + return OpSub64 + case OpAdd32: + return OpSub32 + case OpAdd16: + return OpSub16 + case OpAdd8: + return OpSub8 + default: + panic(fmt.Sprintf("unexpected op %v", op)) + } +} + +func modularMultiplicativeInverse(x uint64) (y uint64) { + if x%2 != 1 { + panic("even numbers in a power-of-two modulus do not have a multiplicative inverse") + } + // we start with 3 bits of precision because each odd number is its own multiplicative inverse mod 8 + y = x // 3 bits + + // now use the Newton-Raphson method to double the number of correct bits in each iteration. + y *= 2 - x*y // 6 bits + y *= 2 - x*y // 12 bits + y *= 2 - x*y // 24 bits + y *= 2 - x*y // 48 bits + y *= 2 - x*y // 96 bits; good enough + return +} diff --git a/src/cmd/compile/internal/ssa/rewrite386.go b/src/cmd/compile/internal/ssa/rewrite386.go index 0495438710659e..1f7fd65d2d8e2e 100644 --- a/src/cmd/compile/internal/ssa/rewrite386.go +++ b/src/cmd/compile/internal/ssa/rewrite386.go @@ -257,6 +257,9 @@ func rewriteValue386(v *Value) bool { case OpAdd32carry: v.Op = Op386ADDLcarry return true + case OpAdd32carrywithcarry: + v.Op = Op386ADCLcarry + return true case OpAdd32withcarry: v.Op = Op386ADCL return true @@ -689,6 +692,9 @@ func rewriteValue386(v *Value) bool { case OpTailCall: v.Op = Op386CALLtail return true + case OpTailCallInter: + v.Op = Op386CALLtailinter + return true case OpTrunc16to8: v.Op = OpCopy return true diff --git a/src/cmd/compile/internal/ssa/rewrite386splitload.go b/src/cmd/compile/internal/ssa/rewrite386splitload.go index a8bd6aaff443e3..c7f290a02081be 100644 --- a/src/cmd/compile/internal/ssa/rewrite386splitload.go +++ b/src/cmd/compile/internal/ssa/rewrite386splitload.go @@ -46,9 +46,8 @@ func rewriteValue386splitload_Op386CMPBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPBload {sym} [off] ptr x mem) - // result: (CMPB (MOVBload {sym} [off] ptr mem) x) + // result: (CMPB (MOVBload {sym} [off] ptr mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -56,7 +55,7 @@ func rewriteValue386splitload_Op386CMPBload(v *Value) bool { x := v_1 mem := v_2 v.reset(Op386CMPB) - v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8) + v0 := b.NewValue0(v.Pos, Op386MOVBload, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) @@ -91,9 +90,8 @@ func rewriteValue386splitload_Op386CMPLload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPLload {sym} [off] ptr x mem) - // result: (CMPL (MOVLload {sym} [off] ptr mem) x) + // result: (CMPL (MOVLload {sym} [off] ptr mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -101,7 +99,7 @@ func rewriteValue386splitload_Op386CMPLload(v *Value) bool { x := v_1 mem := v_2 v.reset(Op386CMPL) - v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) + v0 := b.NewValue0(v.Pos, Op386MOVLload, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) @@ -136,9 +134,8 @@ func rewriteValue386splitload_Op386CMPWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPWload {sym} [off] ptr x mem) - // result: (CMPW (MOVWload {sym} [off] ptr mem) x) + // result: (CMPW (MOVWload {sym} [off] ptr mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -146,7 +143,7 @@ func rewriteValue386splitload_Op386CMPWload(v *Value) bool { x := v_1 mem := v_2 v.reset(Op386CMPW) - v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) + v0 := b.NewValue0(v.Pos, Op386MOVWload, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go index e702925f5f3bac..e37459035b8b0d 100644 --- a/src/cmd/compile/internal/ssa/rewriteAMD64.go +++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go @@ -10,6 +10,48 @@ import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { + case OpAESDecryptLastRoundUint8x16: + v.Op = OpAMD64VAESDECLAST128 + return true + case OpAESDecryptLastRoundUint8x32: + v.Op = OpAMD64VAESDECLAST256 + return true + case OpAESDecryptLastRoundUint8x64: + v.Op = OpAMD64VAESDECLAST512 + return true + case OpAESDecryptOneRoundUint8x16: + v.Op = OpAMD64VAESDEC128 + return true + case OpAESDecryptOneRoundUint8x32: + v.Op = OpAMD64VAESDEC256 + return true + case OpAESDecryptOneRoundUint8x64: + v.Op = OpAMD64VAESDEC512 + return true + case OpAESEncryptLastRoundUint8x16: + v.Op = OpAMD64VAESENCLAST128 + return true + case OpAESEncryptLastRoundUint8x32: + v.Op = OpAMD64VAESENCLAST256 + return true + case OpAESEncryptLastRoundUint8x64: + v.Op = OpAMD64VAESENCLAST512 + return true + case OpAESEncryptOneRoundUint8x16: + v.Op = OpAMD64VAESENC128 + return true + case OpAESEncryptOneRoundUint8x32: + v.Op = OpAMD64VAESENC256 + return true + case OpAESEncryptOneRoundUint8x64: + v.Op = OpAMD64VAESENC512 + return true + case OpAESInvMixColumnsUint32x4: + v.Op = OpAMD64VAESIMC128 + return true + case OpAESRoundKeyGenAssistUint32x4: + v.Op = OpAMD64VAESKEYGENASSIST128 + return true case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ(v) case OpAMD64ADCQconst: @@ -180,6 +222,8 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64CMPXCHGLlock(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock(v) + case OpAMD64CVTSD2SS: + return rewriteValueAMD64_OpAMD64CVTSD2SS(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD(v) case OpAMD64DIVSDload: @@ -196,6 +240,18 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64HMULQ(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU(v) + case OpAMD64KANDB: + return rewriteValueAMD64_OpAMD64KANDB(v) + case OpAMD64KANDW: + return rewriteValueAMD64_OpAMD64KANDW(v) + case OpAMD64KMOVBk: + return rewriteValueAMD64_OpAMD64KMOVBk(v) + case OpAMD64KMOVDk: + return rewriteValueAMD64_OpAMD64KMOVDk(v) + case OpAMD64KMOVQk: + return rewriteValueAMD64_OpAMD64KMOVQk(v) + case OpAMD64KMOVWk: + return rewriteValueAMD64_OpAMD64KMOVWk(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL(v) case OpAMD64LEAL1: @@ -508,6 +564,2484 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) + case OpAMD64VADDPD128: + return rewriteValueAMD64_OpAMD64VADDPD128(v) + case OpAMD64VADDPD256: + return rewriteValueAMD64_OpAMD64VADDPD256(v) + case OpAMD64VADDPD512: + return rewriteValueAMD64_OpAMD64VADDPD512(v) + case OpAMD64VADDPDMasked128: + return rewriteValueAMD64_OpAMD64VADDPDMasked128(v) + case OpAMD64VADDPDMasked256: + return rewriteValueAMD64_OpAMD64VADDPDMasked256(v) + case OpAMD64VADDPDMasked512: + return rewriteValueAMD64_OpAMD64VADDPDMasked512(v) + case OpAMD64VADDPS128: + return rewriteValueAMD64_OpAMD64VADDPS128(v) + case OpAMD64VADDPS256: + return rewriteValueAMD64_OpAMD64VADDPS256(v) + case OpAMD64VADDPS512: + return rewriteValueAMD64_OpAMD64VADDPS512(v) + case OpAMD64VADDPSMasked128: + return rewriteValueAMD64_OpAMD64VADDPSMasked128(v) + case OpAMD64VADDPSMasked256: + return rewriteValueAMD64_OpAMD64VADDPSMasked256(v) + case OpAMD64VADDPSMasked512: + return rewriteValueAMD64_OpAMD64VADDPSMasked512(v) + case OpAMD64VADDSUBPD128: + return rewriteValueAMD64_OpAMD64VADDSUBPD128(v) + case OpAMD64VADDSUBPD256: + return rewriteValueAMD64_OpAMD64VADDSUBPD256(v) + case OpAMD64VADDSUBPS128: + return rewriteValueAMD64_OpAMD64VADDSUBPS128(v) + case OpAMD64VADDSUBPS256: + return rewriteValueAMD64_OpAMD64VADDSUBPS256(v) + case OpAMD64VAESDEC128: + return rewriteValueAMD64_OpAMD64VAESDEC128(v) + case OpAMD64VAESDEC256: + return rewriteValueAMD64_OpAMD64VAESDEC256(v) + case OpAMD64VAESDECLAST128: + return rewriteValueAMD64_OpAMD64VAESDECLAST128(v) + case OpAMD64VAESDECLAST256: + return rewriteValueAMD64_OpAMD64VAESDECLAST256(v) + case OpAMD64VAESENC128: + return rewriteValueAMD64_OpAMD64VAESENC128(v) + case OpAMD64VAESENC256: + return rewriteValueAMD64_OpAMD64VAESENC256(v) + case OpAMD64VAESENCLAST128: + return rewriteValueAMD64_OpAMD64VAESENCLAST128(v) + case OpAMD64VAESENCLAST256: + return rewriteValueAMD64_OpAMD64VAESENCLAST256(v) + case OpAMD64VAESIMC128: + return rewriteValueAMD64_OpAMD64VAESIMC128(v) + case OpAMD64VAESKEYGENASSIST128: + return rewriteValueAMD64_OpAMD64VAESKEYGENASSIST128(v) + case OpAMD64VBROADCASTSD256: + return rewriteValueAMD64_OpAMD64VBROADCASTSD256(v) + case OpAMD64VBROADCASTSD512: + return rewriteValueAMD64_OpAMD64VBROADCASTSD512(v) + case OpAMD64VBROADCASTSDMasked256: + return rewriteValueAMD64_OpAMD64VBROADCASTSDMasked256(v) + case OpAMD64VBROADCASTSDMasked512: + return rewriteValueAMD64_OpAMD64VBROADCASTSDMasked512(v) + case OpAMD64VBROADCASTSS128: + return rewriteValueAMD64_OpAMD64VBROADCASTSS128(v) + case OpAMD64VBROADCASTSS256: + return rewriteValueAMD64_OpAMD64VBROADCASTSS256(v) + case OpAMD64VBROADCASTSS512: + return rewriteValueAMD64_OpAMD64VBROADCASTSS512(v) + case OpAMD64VBROADCASTSSMasked128: + return rewriteValueAMD64_OpAMD64VBROADCASTSSMasked128(v) + case OpAMD64VBROADCASTSSMasked256: + return rewriteValueAMD64_OpAMD64VBROADCASTSSMasked256(v) + case OpAMD64VBROADCASTSSMasked512: + return rewriteValueAMD64_OpAMD64VBROADCASTSSMasked512(v) + case OpAMD64VCMPPD128: + return rewriteValueAMD64_OpAMD64VCMPPD128(v) + case OpAMD64VCMPPD256: + return rewriteValueAMD64_OpAMD64VCMPPD256(v) + case OpAMD64VCMPPD512: + return rewriteValueAMD64_OpAMD64VCMPPD512(v) + case OpAMD64VCMPPDMasked128: + return rewriteValueAMD64_OpAMD64VCMPPDMasked128(v) + case OpAMD64VCMPPDMasked256: + return rewriteValueAMD64_OpAMD64VCMPPDMasked256(v) + case OpAMD64VCMPPDMasked512: + return rewriteValueAMD64_OpAMD64VCMPPDMasked512(v) + case OpAMD64VCMPPS128: + return rewriteValueAMD64_OpAMD64VCMPPS128(v) + case OpAMD64VCMPPS256: + return rewriteValueAMD64_OpAMD64VCMPPS256(v) + case OpAMD64VCMPPS512: + return rewriteValueAMD64_OpAMD64VCMPPS512(v) + case OpAMD64VCMPPSMasked128: + return rewriteValueAMD64_OpAMD64VCMPPSMasked128(v) + case OpAMD64VCMPPSMasked256: + return rewriteValueAMD64_OpAMD64VCMPPSMasked256(v) + case OpAMD64VCMPPSMasked512: + return rewriteValueAMD64_OpAMD64VCMPPSMasked512(v) + case OpAMD64VCVTDQ2PD256: + return rewriteValueAMD64_OpAMD64VCVTDQ2PD256(v) + case OpAMD64VCVTDQ2PD512: + return rewriteValueAMD64_OpAMD64VCVTDQ2PD512(v) + case OpAMD64VCVTDQ2PDMasked256: + return rewriteValueAMD64_OpAMD64VCVTDQ2PDMasked256(v) + case OpAMD64VCVTDQ2PDMasked512: + return rewriteValueAMD64_OpAMD64VCVTDQ2PDMasked512(v) + case OpAMD64VCVTDQ2PS128: + return rewriteValueAMD64_OpAMD64VCVTDQ2PS128(v) + case OpAMD64VCVTDQ2PS256: + return rewriteValueAMD64_OpAMD64VCVTDQ2PS256(v) + case OpAMD64VCVTDQ2PS512: + return rewriteValueAMD64_OpAMD64VCVTDQ2PS512(v) + case OpAMD64VCVTDQ2PSMasked128: + return rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked128(v) + case OpAMD64VCVTDQ2PSMasked256: + return rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked256(v) + case OpAMD64VCVTDQ2PSMasked512: + return rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked512(v) + case OpAMD64VCVTPD2PS256: + return rewriteValueAMD64_OpAMD64VCVTPD2PS256(v) + case OpAMD64VCVTPD2PSMasked256: + return rewriteValueAMD64_OpAMD64VCVTPD2PSMasked256(v) + case OpAMD64VCVTPD2PSX128: + return rewriteValueAMD64_OpAMD64VCVTPD2PSX128(v) + case OpAMD64VCVTPD2PSXMasked128: + return rewriteValueAMD64_OpAMD64VCVTPD2PSXMasked128(v) + case OpAMD64VCVTPD2PSY128: + return rewriteValueAMD64_OpAMD64VCVTPD2PSY128(v) + case OpAMD64VCVTPD2PSYMasked128: + return rewriteValueAMD64_OpAMD64VCVTPD2PSYMasked128(v) + case OpAMD64VCVTPS2PD256: + return rewriteValueAMD64_OpAMD64VCVTPS2PD256(v) + case OpAMD64VCVTPS2PD512: + return rewriteValueAMD64_OpAMD64VCVTPS2PD512(v) + case OpAMD64VCVTPS2PDMasked256: + return rewriteValueAMD64_OpAMD64VCVTPS2PDMasked256(v) + case OpAMD64VCVTPS2PDMasked512: + return rewriteValueAMD64_OpAMD64VCVTPS2PDMasked512(v) + case OpAMD64VCVTQQ2PD128: + return rewriteValueAMD64_OpAMD64VCVTQQ2PD128(v) + case OpAMD64VCVTQQ2PD256: + return rewriteValueAMD64_OpAMD64VCVTQQ2PD256(v) + case OpAMD64VCVTQQ2PD512: + return rewriteValueAMD64_OpAMD64VCVTQQ2PD512(v) + case OpAMD64VCVTQQ2PDMasked128: + return rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked128(v) + case OpAMD64VCVTQQ2PDMasked256: + return rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked256(v) + case OpAMD64VCVTQQ2PDMasked512: + return rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked512(v) + case OpAMD64VCVTQQ2PS256: + return rewriteValueAMD64_OpAMD64VCVTQQ2PS256(v) + case OpAMD64VCVTQQ2PSMasked256: + return rewriteValueAMD64_OpAMD64VCVTQQ2PSMasked256(v) + case OpAMD64VCVTQQ2PSX128: + return rewriteValueAMD64_OpAMD64VCVTQQ2PSX128(v) + case OpAMD64VCVTQQ2PSXMasked128: + return rewriteValueAMD64_OpAMD64VCVTQQ2PSXMasked128(v) + case OpAMD64VCVTQQ2PSY128: + return rewriteValueAMD64_OpAMD64VCVTQQ2PSY128(v) + case OpAMD64VCVTQQ2PSYMasked128: + return rewriteValueAMD64_OpAMD64VCVTQQ2PSYMasked128(v) + case OpAMD64VCVTTPD2DQ256: + return rewriteValueAMD64_OpAMD64VCVTTPD2DQ256(v) + case OpAMD64VCVTTPD2DQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPD2DQMasked256(v) + case OpAMD64VCVTTPD2DQX128: + return rewriteValueAMD64_OpAMD64VCVTTPD2DQX128(v) + case OpAMD64VCVTTPD2DQXMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2DQXMasked128(v) + case OpAMD64VCVTTPD2DQY128: + return rewriteValueAMD64_OpAMD64VCVTTPD2DQY128(v) + case OpAMD64VCVTTPD2DQYMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2DQYMasked128(v) + case OpAMD64VCVTTPD2QQ128: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQ128(v) + case OpAMD64VCVTTPD2QQ256: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQ256(v) + case OpAMD64VCVTTPD2QQ512: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQ512(v) + case OpAMD64VCVTTPD2QQMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked128(v) + case OpAMD64VCVTTPD2QQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked256(v) + case OpAMD64VCVTTPD2QQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked512(v) + case OpAMD64VCVTTPD2UDQ256: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQ256(v) + case OpAMD64VCVTTPD2UDQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQMasked256(v) + case OpAMD64VCVTTPD2UDQX128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQX128(v) + case OpAMD64VCVTTPD2UDQXMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQXMasked128(v) + case OpAMD64VCVTTPD2UDQY128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQY128(v) + case OpAMD64VCVTTPD2UDQYMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQYMasked128(v) + case OpAMD64VCVTTPD2UQQ128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQ128(v) + case OpAMD64VCVTTPD2UQQ256: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQ256(v) + case OpAMD64VCVTTPD2UQQ512: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQ512(v) + case OpAMD64VCVTTPD2UQQMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked128(v) + case OpAMD64VCVTTPD2UQQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked256(v) + case OpAMD64VCVTTPD2UQQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked512(v) + case OpAMD64VCVTTPS2DQ128: + return rewriteValueAMD64_OpAMD64VCVTTPS2DQ128(v) + case OpAMD64VCVTTPS2DQ256: + return rewriteValueAMD64_OpAMD64VCVTTPS2DQ256(v) + case OpAMD64VCVTTPS2DQ512: + return rewriteValueAMD64_OpAMD64VCVTTPS2DQ512(v) + case OpAMD64VCVTTPS2DQMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked128(v) + case OpAMD64VCVTTPS2DQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked256(v) + case OpAMD64VCVTTPS2DQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked512(v) + case OpAMD64VCVTTPS2QQ256: + return rewriteValueAMD64_OpAMD64VCVTTPS2QQ256(v) + case OpAMD64VCVTTPS2QQ512: + return rewriteValueAMD64_OpAMD64VCVTTPS2QQ512(v) + case OpAMD64VCVTTPS2QQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPS2QQMasked256(v) + case OpAMD64VCVTTPS2QQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPS2QQMasked512(v) + case OpAMD64VCVTTPS2UDQ128: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQ128(v) + case OpAMD64VCVTTPS2UDQ256: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQ256(v) + case OpAMD64VCVTTPS2UDQ512: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQ512(v) + case OpAMD64VCVTTPS2UDQMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked128(v) + case OpAMD64VCVTTPS2UDQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked256(v) + case OpAMD64VCVTTPS2UDQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked512(v) + case OpAMD64VCVTTPS2UQQ256: + return rewriteValueAMD64_OpAMD64VCVTTPS2UQQ256(v) + case OpAMD64VCVTTPS2UQQ512: + return rewriteValueAMD64_OpAMD64VCVTTPS2UQQ512(v) + case OpAMD64VCVTTPS2UQQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPS2UQQMasked256(v) + case OpAMD64VCVTTPS2UQQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPS2UQQMasked512(v) + case OpAMD64VCVTUDQ2PD256: + return rewriteValueAMD64_OpAMD64VCVTUDQ2PD256(v) + case OpAMD64VCVTUDQ2PD512: + return rewriteValueAMD64_OpAMD64VCVTUDQ2PD512(v) + case OpAMD64VCVTUDQ2PDMasked256: + return rewriteValueAMD64_OpAMD64VCVTUDQ2PDMasked256(v) + case OpAMD64VCVTUDQ2PDMasked512: + return rewriteValueAMD64_OpAMD64VCVTUDQ2PDMasked512(v) + case OpAMD64VCVTUDQ2PS128: + return rewriteValueAMD64_OpAMD64VCVTUDQ2PS128(v) + case OpAMD64VCVTUDQ2PS256: + return rewriteValueAMD64_OpAMD64VCVTUDQ2PS256(v) + case OpAMD64VCVTUDQ2PS512: + return rewriteValueAMD64_OpAMD64VCVTUDQ2PS512(v) + case OpAMD64VCVTUDQ2PSMasked128: + return rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked128(v) + case OpAMD64VCVTUDQ2PSMasked256: + return rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked256(v) + case OpAMD64VCVTUDQ2PSMasked512: + return rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked512(v) + case OpAMD64VCVTUQQ2PD128: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PD128(v) + case OpAMD64VCVTUQQ2PD256: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PD256(v) + case OpAMD64VCVTUQQ2PD512: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PD512(v) + case OpAMD64VCVTUQQ2PDMasked128: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked128(v) + case OpAMD64VCVTUQQ2PDMasked256: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked256(v) + case OpAMD64VCVTUQQ2PDMasked512: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked512(v) + case OpAMD64VCVTUQQ2PS256: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PS256(v) + case OpAMD64VCVTUQQ2PSMasked256: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PSMasked256(v) + case OpAMD64VCVTUQQ2PSX128: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PSX128(v) + case OpAMD64VCVTUQQ2PSXMasked128: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PSXMasked128(v) + case OpAMD64VCVTUQQ2PSY128: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PSY128(v) + case OpAMD64VCVTUQQ2PSYMasked128: + return rewriteValueAMD64_OpAMD64VCVTUQQ2PSYMasked128(v) + case OpAMD64VDIVPD128: + return rewriteValueAMD64_OpAMD64VDIVPD128(v) + case OpAMD64VDIVPD256: + return rewriteValueAMD64_OpAMD64VDIVPD256(v) + case OpAMD64VDIVPD512: + return rewriteValueAMD64_OpAMD64VDIVPD512(v) + case OpAMD64VDIVPDMasked128: + return rewriteValueAMD64_OpAMD64VDIVPDMasked128(v) + case OpAMD64VDIVPDMasked256: + return rewriteValueAMD64_OpAMD64VDIVPDMasked256(v) + case OpAMD64VDIVPDMasked512: + return rewriteValueAMD64_OpAMD64VDIVPDMasked512(v) + case OpAMD64VDIVPS128: + return rewriteValueAMD64_OpAMD64VDIVPS128(v) + case OpAMD64VDIVPS256: + return rewriteValueAMD64_OpAMD64VDIVPS256(v) + case OpAMD64VDIVPS512: + return rewriteValueAMD64_OpAMD64VDIVPS512(v) + case OpAMD64VDIVPSMasked128: + return rewriteValueAMD64_OpAMD64VDIVPSMasked128(v) + case OpAMD64VDIVPSMasked256: + return rewriteValueAMD64_OpAMD64VDIVPSMasked256(v) + case OpAMD64VDIVPSMasked512: + return rewriteValueAMD64_OpAMD64VDIVPSMasked512(v) + case OpAMD64VEXPANDPDMasked128: + return rewriteValueAMD64_OpAMD64VEXPANDPDMasked128(v) + case OpAMD64VEXPANDPDMasked256: + return rewriteValueAMD64_OpAMD64VEXPANDPDMasked256(v) + case OpAMD64VEXPANDPSMasked128: + return rewriteValueAMD64_OpAMD64VEXPANDPSMasked128(v) + case OpAMD64VEXPANDPSMasked256: + return rewriteValueAMD64_OpAMD64VEXPANDPSMasked256(v) + case OpAMD64VFMADD213PD128: + return rewriteValueAMD64_OpAMD64VFMADD213PD128(v) + case OpAMD64VFMADD213PD256: + return rewriteValueAMD64_OpAMD64VFMADD213PD256(v) + case OpAMD64VFMADD213PD512: + return rewriteValueAMD64_OpAMD64VFMADD213PD512(v) + case OpAMD64VFMADD213PDMasked128: + return rewriteValueAMD64_OpAMD64VFMADD213PDMasked128(v) + case OpAMD64VFMADD213PDMasked256: + return rewriteValueAMD64_OpAMD64VFMADD213PDMasked256(v) + case OpAMD64VFMADD213PDMasked512: + return rewriteValueAMD64_OpAMD64VFMADD213PDMasked512(v) + case OpAMD64VFMADD213PS128: + return rewriteValueAMD64_OpAMD64VFMADD213PS128(v) + case OpAMD64VFMADD213PS256: + return rewriteValueAMD64_OpAMD64VFMADD213PS256(v) + case OpAMD64VFMADD213PS512: + return rewriteValueAMD64_OpAMD64VFMADD213PS512(v) + case OpAMD64VFMADD213PSMasked128: + return rewriteValueAMD64_OpAMD64VFMADD213PSMasked128(v) + case OpAMD64VFMADD213PSMasked256: + return rewriteValueAMD64_OpAMD64VFMADD213PSMasked256(v) + case OpAMD64VFMADD213PSMasked512: + return rewriteValueAMD64_OpAMD64VFMADD213PSMasked512(v) + case OpAMD64VFMADDSUB213PD128: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PD128(v) + case OpAMD64VFMADDSUB213PD256: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PD256(v) + case OpAMD64VFMADDSUB213PD512: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PD512(v) + case OpAMD64VFMADDSUB213PDMasked128: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PDMasked128(v) + case OpAMD64VFMADDSUB213PDMasked256: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PDMasked256(v) + case OpAMD64VFMADDSUB213PDMasked512: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PDMasked512(v) + case OpAMD64VFMADDSUB213PS128: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PS128(v) + case OpAMD64VFMADDSUB213PS256: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PS256(v) + case OpAMD64VFMADDSUB213PS512: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PS512(v) + case OpAMD64VFMADDSUB213PSMasked128: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PSMasked128(v) + case OpAMD64VFMADDSUB213PSMasked256: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PSMasked256(v) + case OpAMD64VFMADDSUB213PSMasked512: + return rewriteValueAMD64_OpAMD64VFMADDSUB213PSMasked512(v) + case OpAMD64VFMSUBADD213PD128: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PD128(v) + case OpAMD64VFMSUBADD213PD256: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PD256(v) + case OpAMD64VFMSUBADD213PD512: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PD512(v) + case OpAMD64VFMSUBADD213PDMasked128: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PDMasked128(v) + case OpAMD64VFMSUBADD213PDMasked256: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PDMasked256(v) + case OpAMD64VFMSUBADD213PDMasked512: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PDMasked512(v) + case OpAMD64VFMSUBADD213PS128: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PS128(v) + case OpAMD64VFMSUBADD213PS256: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PS256(v) + case OpAMD64VFMSUBADD213PS512: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PS512(v) + case OpAMD64VFMSUBADD213PSMasked128: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PSMasked128(v) + case OpAMD64VFMSUBADD213PSMasked256: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PSMasked256(v) + case OpAMD64VFMSUBADD213PSMasked512: + return rewriteValueAMD64_OpAMD64VFMSUBADD213PSMasked512(v) + case OpAMD64VGF2P8AFFINEINVQB128: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQB128(v) + case OpAMD64VGF2P8AFFINEINVQB256: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQB256(v) + case OpAMD64VGF2P8AFFINEINVQB512: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQB512(v) + case OpAMD64VGF2P8AFFINEINVQBMasked128: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQBMasked128(v) + case OpAMD64VGF2P8AFFINEINVQBMasked256: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQBMasked256(v) + case OpAMD64VGF2P8AFFINEINVQBMasked512: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQBMasked512(v) + case OpAMD64VGF2P8AFFINEQB128: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEQB128(v) + case OpAMD64VGF2P8AFFINEQB256: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEQB256(v) + case OpAMD64VGF2P8AFFINEQB512: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEQB512(v) + case OpAMD64VGF2P8AFFINEQBMasked128: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEQBMasked128(v) + case OpAMD64VGF2P8AFFINEQBMasked256: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEQBMasked256(v) + case OpAMD64VGF2P8AFFINEQBMasked512: + return rewriteValueAMD64_OpAMD64VGF2P8AFFINEQBMasked512(v) + case OpAMD64VGF2P8MULB128: + return rewriteValueAMD64_OpAMD64VGF2P8MULB128(v) + case OpAMD64VGF2P8MULB256: + return rewriteValueAMD64_OpAMD64VGF2P8MULB256(v) + case OpAMD64VGF2P8MULBMasked128: + return rewriteValueAMD64_OpAMD64VGF2P8MULBMasked128(v) + case OpAMD64VGF2P8MULBMasked256: + return rewriteValueAMD64_OpAMD64VGF2P8MULBMasked256(v) + case OpAMD64VHADDPD128: + return rewriteValueAMD64_OpAMD64VHADDPD128(v) + case OpAMD64VHADDPD256: + return rewriteValueAMD64_OpAMD64VHADDPD256(v) + case OpAMD64VHADDPS128: + return rewriteValueAMD64_OpAMD64VHADDPS128(v) + case OpAMD64VHADDPS256: + return rewriteValueAMD64_OpAMD64VHADDPS256(v) + case OpAMD64VHSUBPD128: + return rewriteValueAMD64_OpAMD64VHSUBPD128(v) + case OpAMD64VHSUBPD256: + return rewriteValueAMD64_OpAMD64VHSUBPD256(v) + case OpAMD64VHSUBPS128: + return rewriteValueAMD64_OpAMD64VHSUBPS128(v) + case OpAMD64VHSUBPS256: + return rewriteValueAMD64_OpAMD64VHSUBPS256(v) + case OpAMD64VINSERTF128256: + return rewriteValueAMD64_OpAMD64VINSERTF128256(v) + case OpAMD64VINSERTF64X4512: + return rewriteValueAMD64_OpAMD64VINSERTF64X4512(v) + case OpAMD64VINSERTI128256: + return rewriteValueAMD64_OpAMD64VINSERTI128256(v) + case OpAMD64VINSERTI64X4512: + return rewriteValueAMD64_OpAMD64VINSERTI64X4512(v) + case OpAMD64VMAXPD128: + return rewriteValueAMD64_OpAMD64VMAXPD128(v) + case OpAMD64VMAXPD256: + return rewriteValueAMD64_OpAMD64VMAXPD256(v) + case OpAMD64VMAXPD512: + return rewriteValueAMD64_OpAMD64VMAXPD512(v) + case OpAMD64VMAXPDMasked128: + return rewriteValueAMD64_OpAMD64VMAXPDMasked128(v) + case OpAMD64VMAXPDMasked256: + return rewriteValueAMD64_OpAMD64VMAXPDMasked256(v) + case OpAMD64VMAXPDMasked512: + return rewriteValueAMD64_OpAMD64VMAXPDMasked512(v) + case OpAMD64VMAXPS128: + return rewriteValueAMD64_OpAMD64VMAXPS128(v) + case OpAMD64VMAXPS256: + return rewriteValueAMD64_OpAMD64VMAXPS256(v) + case OpAMD64VMAXPS512: + return rewriteValueAMD64_OpAMD64VMAXPS512(v) + case OpAMD64VMAXPSMasked128: + return rewriteValueAMD64_OpAMD64VMAXPSMasked128(v) + case OpAMD64VMAXPSMasked256: + return rewriteValueAMD64_OpAMD64VMAXPSMasked256(v) + case OpAMD64VMAXPSMasked512: + return rewriteValueAMD64_OpAMD64VMAXPSMasked512(v) + case OpAMD64VMINPD128: + return rewriteValueAMD64_OpAMD64VMINPD128(v) + case OpAMD64VMINPD256: + return rewriteValueAMD64_OpAMD64VMINPD256(v) + case OpAMD64VMINPD512: + return rewriteValueAMD64_OpAMD64VMINPD512(v) + case OpAMD64VMINPDMasked128: + return rewriteValueAMD64_OpAMD64VMINPDMasked128(v) + case OpAMD64VMINPDMasked256: + return rewriteValueAMD64_OpAMD64VMINPDMasked256(v) + case OpAMD64VMINPDMasked512: + return rewriteValueAMD64_OpAMD64VMINPDMasked512(v) + case OpAMD64VMINPS128: + return rewriteValueAMD64_OpAMD64VMINPS128(v) + case OpAMD64VMINPS256: + return rewriteValueAMD64_OpAMD64VMINPS256(v) + case OpAMD64VMINPS512: + return rewriteValueAMD64_OpAMD64VMINPS512(v) + case OpAMD64VMINPSMasked128: + return rewriteValueAMD64_OpAMD64VMINPSMasked128(v) + case OpAMD64VMINPSMasked256: + return rewriteValueAMD64_OpAMD64VMINPSMasked256(v) + case OpAMD64VMINPSMasked512: + return rewriteValueAMD64_OpAMD64VMINPSMasked512(v) + case OpAMD64VMOVD: + return rewriteValueAMD64_OpAMD64VMOVD(v) + case OpAMD64VMOVDQU16Masked128: + return rewriteValueAMD64_OpAMD64VMOVDQU16Masked128(v) + case OpAMD64VMOVDQU16Masked256: + return rewriteValueAMD64_OpAMD64VMOVDQU16Masked256(v) + case OpAMD64VMOVDQU16Masked512: + return rewriteValueAMD64_OpAMD64VMOVDQU16Masked512(v) + case OpAMD64VMOVDQU32Masked128: + return rewriteValueAMD64_OpAMD64VMOVDQU32Masked128(v) + case OpAMD64VMOVDQU32Masked256: + return rewriteValueAMD64_OpAMD64VMOVDQU32Masked256(v) + case OpAMD64VMOVDQU32Masked512: + return rewriteValueAMD64_OpAMD64VMOVDQU32Masked512(v) + case OpAMD64VMOVDQU64Masked128: + return rewriteValueAMD64_OpAMD64VMOVDQU64Masked128(v) + case OpAMD64VMOVDQU64Masked256: + return rewriteValueAMD64_OpAMD64VMOVDQU64Masked256(v) + case OpAMD64VMOVDQU64Masked512: + return rewriteValueAMD64_OpAMD64VMOVDQU64Masked512(v) + case OpAMD64VMOVDQU8Masked128: + return rewriteValueAMD64_OpAMD64VMOVDQU8Masked128(v) + case OpAMD64VMOVDQU8Masked256: + return rewriteValueAMD64_OpAMD64VMOVDQU8Masked256(v) + case OpAMD64VMOVDQU8Masked512: + return rewriteValueAMD64_OpAMD64VMOVDQU8Masked512(v) + case OpAMD64VMOVDQUload128: + return rewriteValueAMD64_OpAMD64VMOVDQUload128(v) + case OpAMD64VMOVDQUload256: + return rewriteValueAMD64_OpAMD64VMOVDQUload256(v) + case OpAMD64VMOVDQUload512: + return rewriteValueAMD64_OpAMD64VMOVDQUload512(v) + case OpAMD64VMOVDQUstore128: + return rewriteValueAMD64_OpAMD64VMOVDQUstore128(v) + case OpAMD64VMOVDQUstore256: + return rewriteValueAMD64_OpAMD64VMOVDQUstore256(v) + case OpAMD64VMOVDQUstore512: + return rewriteValueAMD64_OpAMD64VMOVDQUstore512(v) + case OpAMD64VMOVQ: + return rewriteValueAMD64_OpAMD64VMOVQ(v) + case OpAMD64VMOVSDf2v: + return rewriteValueAMD64_OpAMD64VMOVSDf2v(v) + case OpAMD64VMOVSSf2v: + return rewriteValueAMD64_OpAMD64VMOVSSf2v(v) + case OpAMD64VMULPD128: + return rewriteValueAMD64_OpAMD64VMULPD128(v) + case OpAMD64VMULPD256: + return rewriteValueAMD64_OpAMD64VMULPD256(v) + case OpAMD64VMULPD512: + return rewriteValueAMD64_OpAMD64VMULPD512(v) + case OpAMD64VMULPDMasked128: + return rewriteValueAMD64_OpAMD64VMULPDMasked128(v) + case OpAMD64VMULPDMasked256: + return rewriteValueAMD64_OpAMD64VMULPDMasked256(v) + case OpAMD64VMULPDMasked512: + return rewriteValueAMD64_OpAMD64VMULPDMasked512(v) + case OpAMD64VMULPS128: + return rewriteValueAMD64_OpAMD64VMULPS128(v) + case OpAMD64VMULPS256: + return rewriteValueAMD64_OpAMD64VMULPS256(v) + case OpAMD64VMULPS512: + return rewriteValueAMD64_OpAMD64VMULPS512(v) + case OpAMD64VMULPSMasked128: + return rewriteValueAMD64_OpAMD64VMULPSMasked128(v) + case OpAMD64VMULPSMasked256: + return rewriteValueAMD64_OpAMD64VMULPSMasked256(v) + case OpAMD64VMULPSMasked512: + return rewriteValueAMD64_OpAMD64VMULPSMasked512(v) + case OpAMD64VPABSB128: + return rewriteValueAMD64_OpAMD64VPABSB128(v) + case OpAMD64VPABSB256: + return rewriteValueAMD64_OpAMD64VPABSB256(v) + case OpAMD64VPABSBMasked128: + return rewriteValueAMD64_OpAMD64VPABSBMasked128(v) + case OpAMD64VPABSBMasked256: + return rewriteValueAMD64_OpAMD64VPABSBMasked256(v) + case OpAMD64VPABSD128: + return rewriteValueAMD64_OpAMD64VPABSD128(v) + case OpAMD64VPABSD256: + return rewriteValueAMD64_OpAMD64VPABSD256(v) + case OpAMD64VPABSD512: + return rewriteValueAMD64_OpAMD64VPABSD512(v) + case OpAMD64VPABSDMasked128: + return rewriteValueAMD64_OpAMD64VPABSDMasked128(v) + case OpAMD64VPABSDMasked256: + return rewriteValueAMD64_OpAMD64VPABSDMasked256(v) + case OpAMD64VPABSDMasked512: + return rewriteValueAMD64_OpAMD64VPABSDMasked512(v) + case OpAMD64VPABSQ128: + return rewriteValueAMD64_OpAMD64VPABSQ128(v) + case OpAMD64VPABSQ256: + return rewriteValueAMD64_OpAMD64VPABSQ256(v) + case OpAMD64VPABSQ512: + return rewriteValueAMD64_OpAMD64VPABSQ512(v) + case OpAMD64VPABSQMasked128: + return rewriteValueAMD64_OpAMD64VPABSQMasked128(v) + case OpAMD64VPABSQMasked256: + return rewriteValueAMD64_OpAMD64VPABSQMasked256(v) + case OpAMD64VPABSQMasked512: + return rewriteValueAMD64_OpAMD64VPABSQMasked512(v) + case OpAMD64VPABSW128: + return rewriteValueAMD64_OpAMD64VPABSW128(v) + case OpAMD64VPABSW256: + return rewriteValueAMD64_OpAMD64VPABSW256(v) + case OpAMD64VPABSWMasked128: + return rewriteValueAMD64_OpAMD64VPABSWMasked128(v) + case OpAMD64VPABSWMasked256: + return rewriteValueAMD64_OpAMD64VPABSWMasked256(v) + case OpAMD64VPACKSSDW128: + return rewriteValueAMD64_OpAMD64VPACKSSDW128(v) + case OpAMD64VPACKSSDW256: + return rewriteValueAMD64_OpAMD64VPACKSSDW256(v) + case OpAMD64VPACKSSDW512: + return rewriteValueAMD64_OpAMD64VPACKSSDW512(v) + case OpAMD64VPACKSSDWMasked128: + return rewriteValueAMD64_OpAMD64VPACKSSDWMasked128(v) + case OpAMD64VPACKSSDWMasked256: + return rewriteValueAMD64_OpAMD64VPACKSSDWMasked256(v) + case OpAMD64VPACKSSDWMasked512: + return rewriteValueAMD64_OpAMD64VPACKSSDWMasked512(v) + case OpAMD64VPACKUSDW128: + return rewriteValueAMD64_OpAMD64VPACKUSDW128(v) + case OpAMD64VPACKUSDW256: + return rewriteValueAMD64_OpAMD64VPACKUSDW256(v) + case OpAMD64VPACKUSDW512: + return rewriteValueAMD64_OpAMD64VPACKUSDW512(v) + case OpAMD64VPACKUSDWMasked128: + return rewriteValueAMD64_OpAMD64VPACKUSDWMasked128(v) + case OpAMD64VPACKUSDWMasked256: + return rewriteValueAMD64_OpAMD64VPACKUSDWMasked256(v) + case OpAMD64VPACKUSDWMasked512: + return rewriteValueAMD64_OpAMD64VPACKUSDWMasked512(v) + case OpAMD64VPADDB128: + return rewriteValueAMD64_OpAMD64VPADDB128(v) + case OpAMD64VPADDB256: + return rewriteValueAMD64_OpAMD64VPADDB256(v) + case OpAMD64VPADDBMasked128: + return rewriteValueAMD64_OpAMD64VPADDBMasked128(v) + case OpAMD64VPADDBMasked256: + return rewriteValueAMD64_OpAMD64VPADDBMasked256(v) + case OpAMD64VPADDD128: + return rewriteValueAMD64_OpAMD64VPADDD128(v) + case OpAMD64VPADDD256: + return rewriteValueAMD64_OpAMD64VPADDD256(v) + case OpAMD64VPADDD512: + return rewriteValueAMD64_OpAMD64VPADDD512(v) + case OpAMD64VPADDDMasked128: + return rewriteValueAMD64_OpAMD64VPADDDMasked128(v) + case OpAMD64VPADDDMasked256: + return rewriteValueAMD64_OpAMD64VPADDDMasked256(v) + case OpAMD64VPADDDMasked512: + return rewriteValueAMD64_OpAMD64VPADDDMasked512(v) + case OpAMD64VPADDQ128: + return rewriteValueAMD64_OpAMD64VPADDQ128(v) + case OpAMD64VPADDQ256: + return rewriteValueAMD64_OpAMD64VPADDQ256(v) + case OpAMD64VPADDQ512: + return rewriteValueAMD64_OpAMD64VPADDQ512(v) + case OpAMD64VPADDQMasked128: + return rewriteValueAMD64_OpAMD64VPADDQMasked128(v) + case OpAMD64VPADDQMasked256: + return rewriteValueAMD64_OpAMD64VPADDQMasked256(v) + case OpAMD64VPADDQMasked512: + return rewriteValueAMD64_OpAMD64VPADDQMasked512(v) + case OpAMD64VPADDSB128: + return rewriteValueAMD64_OpAMD64VPADDSB128(v) + case OpAMD64VPADDSB256: + return rewriteValueAMD64_OpAMD64VPADDSB256(v) + case OpAMD64VPADDSBMasked128: + return rewriteValueAMD64_OpAMD64VPADDSBMasked128(v) + case OpAMD64VPADDSBMasked256: + return rewriteValueAMD64_OpAMD64VPADDSBMasked256(v) + case OpAMD64VPADDSW128: + return rewriteValueAMD64_OpAMD64VPADDSW128(v) + case OpAMD64VPADDSW256: + return rewriteValueAMD64_OpAMD64VPADDSW256(v) + case OpAMD64VPADDSWMasked128: + return rewriteValueAMD64_OpAMD64VPADDSWMasked128(v) + case OpAMD64VPADDSWMasked256: + return rewriteValueAMD64_OpAMD64VPADDSWMasked256(v) + case OpAMD64VPADDUSB128: + return rewriteValueAMD64_OpAMD64VPADDUSB128(v) + case OpAMD64VPADDUSB256: + return rewriteValueAMD64_OpAMD64VPADDUSB256(v) + case OpAMD64VPADDUSBMasked128: + return rewriteValueAMD64_OpAMD64VPADDUSBMasked128(v) + case OpAMD64VPADDUSBMasked256: + return rewriteValueAMD64_OpAMD64VPADDUSBMasked256(v) + case OpAMD64VPADDUSW128: + return rewriteValueAMD64_OpAMD64VPADDUSW128(v) + case OpAMD64VPADDUSW256: + return rewriteValueAMD64_OpAMD64VPADDUSW256(v) + case OpAMD64VPADDUSWMasked128: + return rewriteValueAMD64_OpAMD64VPADDUSWMasked128(v) + case OpAMD64VPADDUSWMasked256: + return rewriteValueAMD64_OpAMD64VPADDUSWMasked256(v) + case OpAMD64VPADDW128: + return rewriteValueAMD64_OpAMD64VPADDW128(v) + case OpAMD64VPADDW256: + return rewriteValueAMD64_OpAMD64VPADDW256(v) + case OpAMD64VPADDWMasked128: + return rewriteValueAMD64_OpAMD64VPADDWMasked128(v) + case OpAMD64VPADDWMasked256: + return rewriteValueAMD64_OpAMD64VPADDWMasked256(v) + case OpAMD64VPALIGNR128: + return rewriteValueAMD64_OpAMD64VPALIGNR128(v) + case OpAMD64VPALIGNR256: + return rewriteValueAMD64_OpAMD64VPALIGNR256(v) + case OpAMD64VPALIGNRMasked128: + return rewriteValueAMD64_OpAMD64VPALIGNRMasked128(v) + case OpAMD64VPALIGNRMasked256: + return rewriteValueAMD64_OpAMD64VPALIGNRMasked256(v) + case OpAMD64VPAND128: + return rewriteValueAMD64_OpAMD64VPAND128(v) + case OpAMD64VPAND256: + return rewriteValueAMD64_OpAMD64VPAND256(v) + case OpAMD64VPANDD512: + return rewriteValueAMD64_OpAMD64VPANDD512(v) + case OpAMD64VPANDDMasked128: + return rewriteValueAMD64_OpAMD64VPANDDMasked128(v) + case OpAMD64VPANDDMasked256: + return rewriteValueAMD64_OpAMD64VPANDDMasked256(v) + case OpAMD64VPANDDMasked512: + return rewriteValueAMD64_OpAMD64VPANDDMasked512(v) + case OpAMD64VPANDN128: + return rewriteValueAMD64_OpAMD64VPANDN128(v) + case OpAMD64VPANDN256: + return rewriteValueAMD64_OpAMD64VPANDN256(v) + case OpAMD64VPANDND512: + return rewriteValueAMD64_OpAMD64VPANDND512(v) + case OpAMD64VPANDNDMasked128: + return rewriteValueAMD64_OpAMD64VPANDNDMasked128(v) + case OpAMD64VPANDNDMasked256: + return rewriteValueAMD64_OpAMD64VPANDNDMasked256(v) + case OpAMD64VPANDNDMasked512: + return rewriteValueAMD64_OpAMD64VPANDNDMasked512(v) + case OpAMD64VPANDNQ512: + return rewriteValueAMD64_OpAMD64VPANDNQ512(v) + case OpAMD64VPANDNQMasked128: + return rewriteValueAMD64_OpAMD64VPANDNQMasked128(v) + case OpAMD64VPANDNQMasked256: + return rewriteValueAMD64_OpAMD64VPANDNQMasked256(v) + case OpAMD64VPANDNQMasked512: + return rewriteValueAMD64_OpAMD64VPANDNQMasked512(v) + case OpAMD64VPANDQ512: + return rewriteValueAMD64_OpAMD64VPANDQ512(v) + case OpAMD64VPANDQMasked128: + return rewriteValueAMD64_OpAMD64VPANDQMasked128(v) + case OpAMD64VPANDQMasked256: + return rewriteValueAMD64_OpAMD64VPANDQMasked256(v) + case OpAMD64VPANDQMasked512: + return rewriteValueAMD64_OpAMD64VPANDQMasked512(v) + case OpAMD64VPAVGB128: + return rewriteValueAMD64_OpAMD64VPAVGB128(v) + case OpAMD64VPAVGB256: + return rewriteValueAMD64_OpAMD64VPAVGB256(v) + case OpAMD64VPAVGBMasked128: + return rewriteValueAMD64_OpAMD64VPAVGBMasked128(v) + case OpAMD64VPAVGBMasked256: + return rewriteValueAMD64_OpAMD64VPAVGBMasked256(v) + case OpAMD64VPAVGW128: + return rewriteValueAMD64_OpAMD64VPAVGW128(v) + case OpAMD64VPAVGW256: + return rewriteValueAMD64_OpAMD64VPAVGW256(v) + case OpAMD64VPAVGWMasked128: + return rewriteValueAMD64_OpAMD64VPAVGWMasked128(v) + case OpAMD64VPAVGWMasked256: + return rewriteValueAMD64_OpAMD64VPAVGWMasked256(v) + case OpAMD64VPBLENDMBMasked512: + return rewriteValueAMD64_OpAMD64VPBLENDMBMasked512(v) + case OpAMD64VPBLENDMDMasked512: + return rewriteValueAMD64_OpAMD64VPBLENDMDMasked512(v) + case OpAMD64VPBLENDMQMasked512: + return rewriteValueAMD64_OpAMD64VPBLENDMQMasked512(v) + case OpAMD64VPBLENDMWMasked512: + return rewriteValueAMD64_OpAMD64VPBLENDMWMasked512(v) + case OpAMD64VPBLENDVB128: + return rewriteValueAMD64_OpAMD64VPBLENDVB128(v) + case OpAMD64VPBLENDVB256: + return rewriteValueAMD64_OpAMD64VPBLENDVB256(v) + case OpAMD64VPBROADCASTB128: + return rewriteValueAMD64_OpAMD64VPBROADCASTB128(v) + case OpAMD64VPBROADCASTB256: + return rewriteValueAMD64_OpAMD64VPBROADCASTB256(v) + case OpAMD64VPBROADCASTB512: + return rewriteValueAMD64_OpAMD64VPBROADCASTB512(v) + case OpAMD64VPBROADCASTBMasked128: + return rewriteValueAMD64_OpAMD64VPBROADCASTBMasked128(v) + case OpAMD64VPBROADCASTBMasked256: + return rewriteValueAMD64_OpAMD64VPBROADCASTBMasked256(v) + case OpAMD64VPBROADCASTBMasked512: + return rewriteValueAMD64_OpAMD64VPBROADCASTBMasked512(v) + case OpAMD64VPBROADCASTD128: + return rewriteValueAMD64_OpAMD64VPBROADCASTD128(v) + case OpAMD64VPBROADCASTD256: + return rewriteValueAMD64_OpAMD64VPBROADCASTD256(v) + case OpAMD64VPBROADCASTD512: + return rewriteValueAMD64_OpAMD64VPBROADCASTD512(v) + case OpAMD64VPBROADCASTDMasked128: + return rewriteValueAMD64_OpAMD64VPBROADCASTDMasked128(v) + case OpAMD64VPBROADCASTDMasked256: + return rewriteValueAMD64_OpAMD64VPBROADCASTDMasked256(v) + case OpAMD64VPBROADCASTDMasked512: + return rewriteValueAMD64_OpAMD64VPBROADCASTDMasked512(v) + case OpAMD64VPBROADCASTQ128: + return rewriteValueAMD64_OpAMD64VPBROADCASTQ128(v) + case OpAMD64VPBROADCASTQ256: + return rewriteValueAMD64_OpAMD64VPBROADCASTQ256(v) + case OpAMD64VPBROADCASTQ512: + return rewriteValueAMD64_OpAMD64VPBROADCASTQ512(v) + case OpAMD64VPBROADCASTQMasked128: + return rewriteValueAMD64_OpAMD64VPBROADCASTQMasked128(v) + case OpAMD64VPBROADCASTQMasked256: + return rewriteValueAMD64_OpAMD64VPBROADCASTQMasked256(v) + case OpAMD64VPBROADCASTQMasked512: + return rewriteValueAMD64_OpAMD64VPBROADCASTQMasked512(v) + case OpAMD64VPBROADCASTW128: + return rewriteValueAMD64_OpAMD64VPBROADCASTW128(v) + case OpAMD64VPBROADCASTW256: + return rewriteValueAMD64_OpAMD64VPBROADCASTW256(v) + case OpAMD64VPBROADCASTW512: + return rewriteValueAMD64_OpAMD64VPBROADCASTW512(v) + case OpAMD64VPCLMULQDQ128: + return rewriteValueAMD64_OpAMD64VPCLMULQDQ128(v) + case OpAMD64VPCLMULQDQ256: + return rewriteValueAMD64_OpAMD64VPCLMULQDQ256(v) + case OpAMD64VPCMPBMasked128: + return rewriteValueAMD64_OpAMD64VPCMPBMasked128(v) + case OpAMD64VPCMPBMasked256: + return rewriteValueAMD64_OpAMD64VPCMPBMasked256(v) + case OpAMD64VPCMPD512: + return rewriteValueAMD64_OpAMD64VPCMPD512(v) + case OpAMD64VPCMPDMasked128: + return rewriteValueAMD64_OpAMD64VPCMPDMasked128(v) + case OpAMD64VPCMPDMasked256: + return rewriteValueAMD64_OpAMD64VPCMPDMasked256(v) + case OpAMD64VPCMPDMasked512: + return rewriteValueAMD64_OpAMD64VPCMPDMasked512(v) + case OpAMD64VPCMPEQB128: + return rewriteValueAMD64_OpAMD64VPCMPEQB128(v) + case OpAMD64VPCMPEQB256: + return rewriteValueAMD64_OpAMD64VPCMPEQB256(v) + case OpAMD64VPCMPEQD128: + return rewriteValueAMD64_OpAMD64VPCMPEQD128(v) + case OpAMD64VPCMPEQD256: + return rewriteValueAMD64_OpAMD64VPCMPEQD256(v) + case OpAMD64VPCMPEQD512: + return rewriteValueAMD64_OpAMD64VPCMPEQD512(v) + case OpAMD64VPCMPEQQ128: + return rewriteValueAMD64_OpAMD64VPCMPEQQ128(v) + case OpAMD64VPCMPEQQ256: + return rewriteValueAMD64_OpAMD64VPCMPEQQ256(v) + case OpAMD64VPCMPEQQ512: + return rewriteValueAMD64_OpAMD64VPCMPEQQ512(v) + case OpAMD64VPCMPEQW128: + return rewriteValueAMD64_OpAMD64VPCMPEQW128(v) + case OpAMD64VPCMPEQW256: + return rewriteValueAMD64_OpAMD64VPCMPEQW256(v) + case OpAMD64VPCMPGTB128: + return rewriteValueAMD64_OpAMD64VPCMPGTB128(v) + case OpAMD64VPCMPGTB256: + return rewriteValueAMD64_OpAMD64VPCMPGTB256(v) + case OpAMD64VPCMPGTD128: + return rewriteValueAMD64_OpAMD64VPCMPGTD128(v) + case OpAMD64VPCMPGTD256: + return rewriteValueAMD64_OpAMD64VPCMPGTD256(v) + case OpAMD64VPCMPGTD512: + return rewriteValueAMD64_OpAMD64VPCMPGTD512(v) + case OpAMD64VPCMPGTQ128: + return rewriteValueAMD64_OpAMD64VPCMPGTQ128(v) + case OpAMD64VPCMPGTQ256: + return rewriteValueAMD64_OpAMD64VPCMPGTQ256(v) + case OpAMD64VPCMPGTQ512: + return rewriteValueAMD64_OpAMD64VPCMPGTQ512(v) + case OpAMD64VPCMPGTW128: + return rewriteValueAMD64_OpAMD64VPCMPGTW128(v) + case OpAMD64VPCMPGTW256: + return rewriteValueAMD64_OpAMD64VPCMPGTW256(v) + case OpAMD64VPCMPQ512: + return rewriteValueAMD64_OpAMD64VPCMPQ512(v) + case OpAMD64VPCMPQMasked128: + return rewriteValueAMD64_OpAMD64VPCMPQMasked128(v) + case OpAMD64VPCMPQMasked256: + return rewriteValueAMD64_OpAMD64VPCMPQMasked256(v) + case OpAMD64VPCMPQMasked512: + return rewriteValueAMD64_OpAMD64VPCMPQMasked512(v) + case OpAMD64VPCMPUBMasked128: + return rewriteValueAMD64_OpAMD64VPCMPUBMasked128(v) + case OpAMD64VPCMPUBMasked256: + return rewriteValueAMD64_OpAMD64VPCMPUBMasked256(v) + case OpAMD64VPCMPUD512: + return rewriteValueAMD64_OpAMD64VPCMPUD512(v) + case OpAMD64VPCMPUDMasked128: + return rewriteValueAMD64_OpAMD64VPCMPUDMasked128(v) + case OpAMD64VPCMPUDMasked256: + return rewriteValueAMD64_OpAMD64VPCMPUDMasked256(v) + case OpAMD64VPCMPUDMasked512: + return rewriteValueAMD64_OpAMD64VPCMPUDMasked512(v) + case OpAMD64VPCMPUQ512: + return rewriteValueAMD64_OpAMD64VPCMPUQ512(v) + case OpAMD64VPCMPUQMasked128: + return rewriteValueAMD64_OpAMD64VPCMPUQMasked128(v) + case OpAMD64VPCMPUQMasked256: + return rewriteValueAMD64_OpAMD64VPCMPUQMasked256(v) + case OpAMD64VPCMPUQMasked512: + return rewriteValueAMD64_OpAMD64VPCMPUQMasked512(v) + case OpAMD64VPCMPUWMasked128: + return rewriteValueAMD64_OpAMD64VPCMPUWMasked128(v) + case OpAMD64VPCMPUWMasked256: + return rewriteValueAMD64_OpAMD64VPCMPUWMasked256(v) + case OpAMD64VPCMPWMasked128: + return rewriteValueAMD64_OpAMD64VPCMPWMasked128(v) + case OpAMD64VPCMPWMasked256: + return rewriteValueAMD64_OpAMD64VPCMPWMasked256(v) + case OpAMD64VPDPWSSD128: + return rewriteValueAMD64_OpAMD64VPDPWSSD128(v) + case OpAMD64VPDPWSSD256: + return rewriteValueAMD64_OpAMD64VPDPWSSD256(v) + case OpAMD64VPDPWSSD512: + return rewriteValueAMD64_OpAMD64VPDPWSSD512(v) + case OpAMD64VPDPWSSDMasked128: + return rewriteValueAMD64_OpAMD64VPDPWSSDMasked128(v) + case OpAMD64VPDPWSSDMasked256: + return rewriteValueAMD64_OpAMD64VPDPWSSDMasked256(v) + case OpAMD64VPDPWSSDMasked512: + return rewriteValueAMD64_OpAMD64VPDPWSSDMasked512(v) + case OpAMD64VPERM2F128256: + return rewriteValueAMD64_OpAMD64VPERM2F128256(v) + case OpAMD64VPERM2I128256: + return rewriteValueAMD64_OpAMD64VPERM2I128256(v) + case OpAMD64VPERMB128: + return rewriteValueAMD64_OpAMD64VPERMB128(v) + case OpAMD64VPERMB256: + return rewriteValueAMD64_OpAMD64VPERMB256(v) + case OpAMD64VPERMBMasked128: + return rewriteValueAMD64_OpAMD64VPERMBMasked128(v) + case OpAMD64VPERMBMasked256: + return rewriteValueAMD64_OpAMD64VPERMBMasked256(v) + case OpAMD64VPERMD256: + return rewriteValueAMD64_OpAMD64VPERMD256(v) + case OpAMD64VPERMD512: + return rewriteValueAMD64_OpAMD64VPERMD512(v) + case OpAMD64VPERMDMasked256: + return rewriteValueAMD64_OpAMD64VPERMDMasked256(v) + case OpAMD64VPERMDMasked512: + return rewriteValueAMD64_OpAMD64VPERMDMasked512(v) + case OpAMD64VPERMI2B128: + return rewriteValueAMD64_OpAMD64VPERMI2B128(v) + case OpAMD64VPERMI2B256: + return rewriteValueAMD64_OpAMD64VPERMI2B256(v) + case OpAMD64VPERMI2BMasked128: + return rewriteValueAMD64_OpAMD64VPERMI2BMasked128(v) + case OpAMD64VPERMI2BMasked256: + return rewriteValueAMD64_OpAMD64VPERMI2BMasked256(v) + case OpAMD64VPERMI2D128: + return rewriteValueAMD64_OpAMD64VPERMI2D128(v) + case OpAMD64VPERMI2D256: + return rewriteValueAMD64_OpAMD64VPERMI2D256(v) + case OpAMD64VPERMI2D512: + return rewriteValueAMD64_OpAMD64VPERMI2D512(v) + case OpAMD64VPERMI2DMasked128: + return rewriteValueAMD64_OpAMD64VPERMI2DMasked128(v) + case OpAMD64VPERMI2DMasked256: + return rewriteValueAMD64_OpAMD64VPERMI2DMasked256(v) + case OpAMD64VPERMI2DMasked512: + return rewriteValueAMD64_OpAMD64VPERMI2DMasked512(v) + case OpAMD64VPERMI2PD128: + return rewriteValueAMD64_OpAMD64VPERMI2PD128(v) + case OpAMD64VPERMI2PD256: + return rewriteValueAMD64_OpAMD64VPERMI2PD256(v) + case OpAMD64VPERMI2PD512: + return rewriteValueAMD64_OpAMD64VPERMI2PD512(v) + case OpAMD64VPERMI2PDMasked128: + return rewriteValueAMD64_OpAMD64VPERMI2PDMasked128(v) + case OpAMD64VPERMI2PDMasked256: + return rewriteValueAMD64_OpAMD64VPERMI2PDMasked256(v) + case OpAMD64VPERMI2PDMasked512: + return rewriteValueAMD64_OpAMD64VPERMI2PDMasked512(v) + case OpAMD64VPERMI2PS128: + return rewriteValueAMD64_OpAMD64VPERMI2PS128(v) + case OpAMD64VPERMI2PS256: + return rewriteValueAMD64_OpAMD64VPERMI2PS256(v) + case OpAMD64VPERMI2PS512: + return rewriteValueAMD64_OpAMD64VPERMI2PS512(v) + case OpAMD64VPERMI2PSMasked128: + return rewriteValueAMD64_OpAMD64VPERMI2PSMasked128(v) + case OpAMD64VPERMI2PSMasked256: + return rewriteValueAMD64_OpAMD64VPERMI2PSMasked256(v) + case OpAMD64VPERMI2PSMasked512: + return rewriteValueAMD64_OpAMD64VPERMI2PSMasked512(v) + case OpAMD64VPERMI2Q128: + return rewriteValueAMD64_OpAMD64VPERMI2Q128(v) + case OpAMD64VPERMI2Q256: + return rewriteValueAMD64_OpAMD64VPERMI2Q256(v) + case OpAMD64VPERMI2Q512: + return rewriteValueAMD64_OpAMD64VPERMI2Q512(v) + case OpAMD64VPERMI2QMasked128: + return rewriteValueAMD64_OpAMD64VPERMI2QMasked128(v) + case OpAMD64VPERMI2QMasked256: + return rewriteValueAMD64_OpAMD64VPERMI2QMasked256(v) + case OpAMD64VPERMI2QMasked512: + return rewriteValueAMD64_OpAMD64VPERMI2QMasked512(v) + case OpAMD64VPERMI2W128: + return rewriteValueAMD64_OpAMD64VPERMI2W128(v) + case OpAMD64VPERMI2W256: + return rewriteValueAMD64_OpAMD64VPERMI2W256(v) + case OpAMD64VPERMI2WMasked128: + return rewriteValueAMD64_OpAMD64VPERMI2WMasked128(v) + case OpAMD64VPERMI2WMasked256: + return rewriteValueAMD64_OpAMD64VPERMI2WMasked256(v) + case OpAMD64VPERMPD256: + return rewriteValueAMD64_OpAMD64VPERMPD256(v) + case OpAMD64VPERMPD512: + return rewriteValueAMD64_OpAMD64VPERMPD512(v) + case OpAMD64VPERMPDMasked256: + return rewriteValueAMD64_OpAMD64VPERMPDMasked256(v) + case OpAMD64VPERMPDMasked512: + return rewriteValueAMD64_OpAMD64VPERMPDMasked512(v) + case OpAMD64VPERMPS256: + return rewriteValueAMD64_OpAMD64VPERMPS256(v) + case OpAMD64VPERMPS512: + return rewriteValueAMD64_OpAMD64VPERMPS512(v) + case OpAMD64VPERMPSMasked256: + return rewriteValueAMD64_OpAMD64VPERMPSMasked256(v) + case OpAMD64VPERMPSMasked512: + return rewriteValueAMD64_OpAMD64VPERMPSMasked512(v) + case OpAMD64VPERMQ256: + return rewriteValueAMD64_OpAMD64VPERMQ256(v) + case OpAMD64VPERMQ512: + return rewriteValueAMD64_OpAMD64VPERMQ512(v) + case OpAMD64VPERMQMasked256: + return rewriteValueAMD64_OpAMD64VPERMQMasked256(v) + case OpAMD64VPERMQMasked512: + return rewriteValueAMD64_OpAMD64VPERMQMasked512(v) + case OpAMD64VPERMW128: + return rewriteValueAMD64_OpAMD64VPERMW128(v) + case OpAMD64VPERMW256: + return rewriteValueAMD64_OpAMD64VPERMW256(v) + case OpAMD64VPERMWMasked128: + return rewriteValueAMD64_OpAMD64VPERMWMasked128(v) + case OpAMD64VPERMWMasked256: + return rewriteValueAMD64_OpAMD64VPERMWMasked256(v) + case OpAMD64VPEXPANDBMasked128: + return rewriteValueAMD64_OpAMD64VPEXPANDBMasked128(v) + case OpAMD64VPEXPANDBMasked256: + return rewriteValueAMD64_OpAMD64VPEXPANDBMasked256(v) + case OpAMD64VPEXPANDDMasked128: + return rewriteValueAMD64_OpAMD64VPEXPANDDMasked128(v) + case OpAMD64VPEXPANDDMasked256: + return rewriteValueAMD64_OpAMD64VPEXPANDDMasked256(v) + case OpAMD64VPEXPANDQMasked128: + return rewriteValueAMD64_OpAMD64VPEXPANDQMasked128(v) + case OpAMD64VPEXPANDQMasked256: + return rewriteValueAMD64_OpAMD64VPEXPANDQMasked256(v) + case OpAMD64VPEXPANDWMasked128: + return rewriteValueAMD64_OpAMD64VPEXPANDWMasked128(v) + case OpAMD64VPEXPANDWMasked256: + return rewriteValueAMD64_OpAMD64VPEXPANDWMasked256(v) + case OpAMD64VPHADDD128: + return rewriteValueAMD64_OpAMD64VPHADDD128(v) + case OpAMD64VPHADDD256: + return rewriteValueAMD64_OpAMD64VPHADDD256(v) + case OpAMD64VPHADDSW128: + return rewriteValueAMD64_OpAMD64VPHADDSW128(v) + case OpAMD64VPHADDSW256: + return rewriteValueAMD64_OpAMD64VPHADDSW256(v) + case OpAMD64VPHADDW128: + return rewriteValueAMD64_OpAMD64VPHADDW128(v) + case OpAMD64VPHADDW256: + return rewriteValueAMD64_OpAMD64VPHADDW256(v) + case OpAMD64VPHSUBD128: + return rewriteValueAMD64_OpAMD64VPHSUBD128(v) + case OpAMD64VPHSUBD256: + return rewriteValueAMD64_OpAMD64VPHSUBD256(v) + case OpAMD64VPHSUBSW128: + return rewriteValueAMD64_OpAMD64VPHSUBSW128(v) + case OpAMD64VPHSUBSW256: + return rewriteValueAMD64_OpAMD64VPHSUBSW256(v) + case OpAMD64VPHSUBW128: + return rewriteValueAMD64_OpAMD64VPHSUBW128(v) + case OpAMD64VPHSUBW256: + return rewriteValueAMD64_OpAMD64VPHSUBW256(v) + case OpAMD64VPINSRD128: + return rewriteValueAMD64_OpAMD64VPINSRD128(v) + case OpAMD64VPINSRQ128: + return rewriteValueAMD64_OpAMD64VPINSRQ128(v) + case OpAMD64VPLZCNTD128: + return rewriteValueAMD64_OpAMD64VPLZCNTD128(v) + case OpAMD64VPLZCNTD256: + return rewriteValueAMD64_OpAMD64VPLZCNTD256(v) + case OpAMD64VPLZCNTD512: + return rewriteValueAMD64_OpAMD64VPLZCNTD512(v) + case OpAMD64VPLZCNTDMasked128: + return rewriteValueAMD64_OpAMD64VPLZCNTDMasked128(v) + case OpAMD64VPLZCNTDMasked256: + return rewriteValueAMD64_OpAMD64VPLZCNTDMasked256(v) + case OpAMD64VPLZCNTDMasked512: + return rewriteValueAMD64_OpAMD64VPLZCNTDMasked512(v) + case OpAMD64VPLZCNTQ128: + return rewriteValueAMD64_OpAMD64VPLZCNTQ128(v) + case OpAMD64VPLZCNTQ256: + return rewriteValueAMD64_OpAMD64VPLZCNTQ256(v) + case OpAMD64VPLZCNTQ512: + return rewriteValueAMD64_OpAMD64VPLZCNTQ512(v) + case OpAMD64VPLZCNTQMasked128: + return rewriteValueAMD64_OpAMD64VPLZCNTQMasked128(v) + case OpAMD64VPLZCNTQMasked256: + return rewriteValueAMD64_OpAMD64VPLZCNTQMasked256(v) + case OpAMD64VPLZCNTQMasked512: + return rewriteValueAMD64_OpAMD64VPLZCNTQMasked512(v) + case OpAMD64VPMADDUBSW128: + return rewriteValueAMD64_OpAMD64VPMADDUBSW128(v) + case OpAMD64VPMADDUBSW256: + return rewriteValueAMD64_OpAMD64VPMADDUBSW256(v) + case OpAMD64VPMADDUBSWMasked128: + return rewriteValueAMD64_OpAMD64VPMADDUBSWMasked128(v) + case OpAMD64VPMADDUBSWMasked256: + return rewriteValueAMD64_OpAMD64VPMADDUBSWMasked256(v) + case OpAMD64VPMADDWD128: + return rewriteValueAMD64_OpAMD64VPMADDWD128(v) + case OpAMD64VPMADDWD256: + return rewriteValueAMD64_OpAMD64VPMADDWD256(v) + case OpAMD64VPMADDWDMasked128: + return rewriteValueAMD64_OpAMD64VPMADDWDMasked128(v) + case OpAMD64VPMADDWDMasked256: + return rewriteValueAMD64_OpAMD64VPMADDWDMasked256(v) + case OpAMD64VPMAXSB128: + return rewriteValueAMD64_OpAMD64VPMAXSB128(v) + case OpAMD64VPMAXSB256: + return rewriteValueAMD64_OpAMD64VPMAXSB256(v) + case OpAMD64VPMAXSBMasked128: + return rewriteValueAMD64_OpAMD64VPMAXSBMasked128(v) + case OpAMD64VPMAXSBMasked256: + return rewriteValueAMD64_OpAMD64VPMAXSBMasked256(v) + case OpAMD64VPMAXSD128: + return rewriteValueAMD64_OpAMD64VPMAXSD128(v) + case OpAMD64VPMAXSD256: + return rewriteValueAMD64_OpAMD64VPMAXSD256(v) + case OpAMD64VPMAXSD512: + return rewriteValueAMD64_OpAMD64VPMAXSD512(v) + case OpAMD64VPMAXSDMasked128: + return rewriteValueAMD64_OpAMD64VPMAXSDMasked128(v) + case OpAMD64VPMAXSDMasked256: + return rewriteValueAMD64_OpAMD64VPMAXSDMasked256(v) + case OpAMD64VPMAXSDMasked512: + return rewriteValueAMD64_OpAMD64VPMAXSDMasked512(v) + case OpAMD64VPMAXSQ128: + return rewriteValueAMD64_OpAMD64VPMAXSQ128(v) + case OpAMD64VPMAXSQ256: + return rewriteValueAMD64_OpAMD64VPMAXSQ256(v) + case OpAMD64VPMAXSQ512: + return rewriteValueAMD64_OpAMD64VPMAXSQ512(v) + case OpAMD64VPMAXSQMasked128: + return rewriteValueAMD64_OpAMD64VPMAXSQMasked128(v) + case OpAMD64VPMAXSQMasked256: + return rewriteValueAMD64_OpAMD64VPMAXSQMasked256(v) + case OpAMD64VPMAXSQMasked512: + return rewriteValueAMD64_OpAMD64VPMAXSQMasked512(v) + case OpAMD64VPMAXSW128: + return rewriteValueAMD64_OpAMD64VPMAXSW128(v) + case OpAMD64VPMAXSW256: + return rewriteValueAMD64_OpAMD64VPMAXSW256(v) + case OpAMD64VPMAXSWMasked128: + return rewriteValueAMD64_OpAMD64VPMAXSWMasked128(v) + case OpAMD64VPMAXSWMasked256: + return rewriteValueAMD64_OpAMD64VPMAXSWMasked256(v) + case OpAMD64VPMAXUB128: + return rewriteValueAMD64_OpAMD64VPMAXUB128(v) + case OpAMD64VPMAXUB256: + return rewriteValueAMD64_OpAMD64VPMAXUB256(v) + case OpAMD64VPMAXUBMasked128: + return rewriteValueAMD64_OpAMD64VPMAXUBMasked128(v) + case OpAMD64VPMAXUBMasked256: + return rewriteValueAMD64_OpAMD64VPMAXUBMasked256(v) + case OpAMD64VPMAXUD128: + return rewriteValueAMD64_OpAMD64VPMAXUD128(v) + case OpAMD64VPMAXUD256: + return rewriteValueAMD64_OpAMD64VPMAXUD256(v) + case OpAMD64VPMAXUD512: + return rewriteValueAMD64_OpAMD64VPMAXUD512(v) + case OpAMD64VPMAXUDMasked128: + return rewriteValueAMD64_OpAMD64VPMAXUDMasked128(v) + case OpAMD64VPMAXUDMasked256: + return rewriteValueAMD64_OpAMD64VPMAXUDMasked256(v) + case OpAMD64VPMAXUDMasked512: + return rewriteValueAMD64_OpAMD64VPMAXUDMasked512(v) + case OpAMD64VPMAXUQ128: + return rewriteValueAMD64_OpAMD64VPMAXUQ128(v) + case OpAMD64VPMAXUQ256: + return rewriteValueAMD64_OpAMD64VPMAXUQ256(v) + case OpAMD64VPMAXUQ512: + return rewriteValueAMD64_OpAMD64VPMAXUQ512(v) + case OpAMD64VPMAXUQMasked128: + return rewriteValueAMD64_OpAMD64VPMAXUQMasked128(v) + case OpAMD64VPMAXUQMasked256: + return rewriteValueAMD64_OpAMD64VPMAXUQMasked256(v) + case OpAMD64VPMAXUQMasked512: + return rewriteValueAMD64_OpAMD64VPMAXUQMasked512(v) + case OpAMD64VPMAXUW128: + return rewriteValueAMD64_OpAMD64VPMAXUW128(v) + case OpAMD64VPMAXUW256: + return rewriteValueAMD64_OpAMD64VPMAXUW256(v) + case OpAMD64VPMAXUWMasked128: + return rewriteValueAMD64_OpAMD64VPMAXUWMasked128(v) + case OpAMD64VPMAXUWMasked256: + return rewriteValueAMD64_OpAMD64VPMAXUWMasked256(v) + case OpAMD64VPMINSB128: + return rewriteValueAMD64_OpAMD64VPMINSB128(v) + case OpAMD64VPMINSB256: + return rewriteValueAMD64_OpAMD64VPMINSB256(v) + case OpAMD64VPMINSBMasked128: + return rewriteValueAMD64_OpAMD64VPMINSBMasked128(v) + case OpAMD64VPMINSBMasked256: + return rewriteValueAMD64_OpAMD64VPMINSBMasked256(v) + case OpAMD64VPMINSD128: + return rewriteValueAMD64_OpAMD64VPMINSD128(v) + case OpAMD64VPMINSD256: + return rewriteValueAMD64_OpAMD64VPMINSD256(v) + case OpAMD64VPMINSD512: + return rewriteValueAMD64_OpAMD64VPMINSD512(v) + case OpAMD64VPMINSDMasked128: + return rewriteValueAMD64_OpAMD64VPMINSDMasked128(v) + case OpAMD64VPMINSDMasked256: + return rewriteValueAMD64_OpAMD64VPMINSDMasked256(v) + case OpAMD64VPMINSDMasked512: + return rewriteValueAMD64_OpAMD64VPMINSDMasked512(v) + case OpAMD64VPMINSQ128: + return rewriteValueAMD64_OpAMD64VPMINSQ128(v) + case OpAMD64VPMINSQ256: + return rewriteValueAMD64_OpAMD64VPMINSQ256(v) + case OpAMD64VPMINSQ512: + return rewriteValueAMD64_OpAMD64VPMINSQ512(v) + case OpAMD64VPMINSQMasked128: + return rewriteValueAMD64_OpAMD64VPMINSQMasked128(v) + case OpAMD64VPMINSQMasked256: + return rewriteValueAMD64_OpAMD64VPMINSQMasked256(v) + case OpAMD64VPMINSQMasked512: + return rewriteValueAMD64_OpAMD64VPMINSQMasked512(v) + case OpAMD64VPMINSW128: + return rewriteValueAMD64_OpAMD64VPMINSW128(v) + case OpAMD64VPMINSW256: + return rewriteValueAMD64_OpAMD64VPMINSW256(v) + case OpAMD64VPMINSWMasked128: + return rewriteValueAMD64_OpAMD64VPMINSWMasked128(v) + case OpAMD64VPMINSWMasked256: + return rewriteValueAMD64_OpAMD64VPMINSWMasked256(v) + case OpAMD64VPMINUB128: + return rewriteValueAMD64_OpAMD64VPMINUB128(v) + case OpAMD64VPMINUB256: + return rewriteValueAMD64_OpAMD64VPMINUB256(v) + case OpAMD64VPMINUBMasked128: + return rewriteValueAMD64_OpAMD64VPMINUBMasked128(v) + case OpAMD64VPMINUBMasked256: + return rewriteValueAMD64_OpAMD64VPMINUBMasked256(v) + case OpAMD64VPMINUD128: + return rewriteValueAMD64_OpAMD64VPMINUD128(v) + case OpAMD64VPMINUD256: + return rewriteValueAMD64_OpAMD64VPMINUD256(v) + case OpAMD64VPMINUD512: + return rewriteValueAMD64_OpAMD64VPMINUD512(v) + case OpAMD64VPMINUDMasked128: + return rewriteValueAMD64_OpAMD64VPMINUDMasked128(v) + case OpAMD64VPMINUDMasked256: + return rewriteValueAMD64_OpAMD64VPMINUDMasked256(v) + case OpAMD64VPMINUDMasked512: + return rewriteValueAMD64_OpAMD64VPMINUDMasked512(v) + case OpAMD64VPMINUQ128: + return rewriteValueAMD64_OpAMD64VPMINUQ128(v) + case OpAMD64VPMINUQ256: + return rewriteValueAMD64_OpAMD64VPMINUQ256(v) + case OpAMD64VPMINUQ512: + return rewriteValueAMD64_OpAMD64VPMINUQ512(v) + case OpAMD64VPMINUQMasked128: + return rewriteValueAMD64_OpAMD64VPMINUQMasked128(v) + case OpAMD64VPMINUQMasked256: + return rewriteValueAMD64_OpAMD64VPMINUQMasked256(v) + case OpAMD64VPMINUQMasked512: + return rewriteValueAMD64_OpAMD64VPMINUQMasked512(v) + case OpAMD64VPMINUW128: + return rewriteValueAMD64_OpAMD64VPMINUW128(v) + case OpAMD64VPMINUW256: + return rewriteValueAMD64_OpAMD64VPMINUW256(v) + case OpAMD64VPMINUWMasked128: + return rewriteValueAMD64_OpAMD64VPMINUWMasked128(v) + case OpAMD64VPMINUWMasked256: + return rewriteValueAMD64_OpAMD64VPMINUWMasked256(v) + case OpAMD64VPMOVSXBD128: + return rewriteValueAMD64_OpAMD64VPMOVSXBD128(v) + case OpAMD64VPMOVSXBD256: + return rewriteValueAMD64_OpAMD64VPMOVSXBD256(v) + case OpAMD64VPMOVSXBD512: + return rewriteValueAMD64_OpAMD64VPMOVSXBD512(v) + case OpAMD64VPMOVSXBDMasked128: + return rewriteValueAMD64_OpAMD64VPMOVSXBDMasked128(v) + case OpAMD64VPMOVSXBDMasked256: + return rewriteValueAMD64_OpAMD64VPMOVSXBDMasked256(v) + case OpAMD64VPMOVSXBDMasked512: + return rewriteValueAMD64_OpAMD64VPMOVSXBDMasked512(v) + case OpAMD64VPMOVSXBQ128: + return rewriteValueAMD64_OpAMD64VPMOVSXBQ128(v) + case OpAMD64VPMOVSXBQ256: + return rewriteValueAMD64_OpAMD64VPMOVSXBQ256(v) + case OpAMD64VPMOVSXBQ512: + return rewriteValueAMD64_OpAMD64VPMOVSXBQ512(v) + case OpAMD64VPMOVSXBQMasked256: + return rewriteValueAMD64_OpAMD64VPMOVSXBQMasked256(v) + case OpAMD64VPMOVSXBQMasked512: + return rewriteValueAMD64_OpAMD64VPMOVSXBQMasked512(v) + case OpAMD64VPMOVSXBW128: + return rewriteValueAMD64_OpAMD64VPMOVSXBW128(v) + case OpAMD64VPMOVSXBW256: + return rewriteValueAMD64_OpAMD64VPMOVSXBW256(v) + case OpAMD64VPMOVSXBW512: + return rewriteValueAMD64_OpAMD64VPMOVSXBW512(v) + case OpAMD64VPMOVSXBWMasked128: + return rewriteValueAMD64_OpAMD64VPMOVSXBWMasked128(v) + case OpAMD64VPMOVSXBWMasked256: + return rewriteValueAMD64_OpAMD64VPMOVSXBWMasked256(v) + case OpAMD64VPMOVSXBWMasked512: + return rewriteValueAMD64_OpAMD64VPMOVSXBWMasked512(v) + case OpAMD64VPMOVSXDQ128: + return rewriteValueAMD64_OpAMD64VPMOVSXDQ128(v) + case OpAMD64VPMOVSXDQ256: + return rewriteValueAMD64_OpAMD64VPMOVSXDQ256(v) + case OpAMD64VPMOVSXDQ512: + return rewriteValueAMD64_OpAMD64VPMOVSXDQ512(v) + case OpAMD64VPMOVSXDQMasked128: + return rewriteValueAMD64_OpAMD64VPMOVSXDQMasked128(v) + case OpAMD64VPMOVSXDQMasked256: + return rewriteValueAMD64_OpAMD64VPMOVSXDQMasked256(v) + case OpAMD64VPMOVSXDQMasked512: + return rewriteValueAMD64_OpAMD64VPMOVSXDQMasked512(v) + case OpAMD64VPMOVSXWD128: + return rewriteValueAMD64_OpAMD64VPMOVSXWD128(v) + case OpAMD64VPMOVSXWD256: + return rewriteValueAMD64_OpAMD64VPMOVSXWD256(v) + case OpAMD64VPMOVSXWD512: + return rewriteValueAMD64_OpAMD64VPMOVSXWD512(v) + case OpAMD64VPMOVSXWDMasked128: + return rewriteValueAMD64_OpAMD64VPMOVSXWDMasked128(v) + case OpAMD64VPMOVSXWDMasked256: + return rewriteValueAMD64_OpAMD64VPMOVSXWDMasked256(v) + case OpAMD64VPMOVSXWDMasked512: + return rewriteValueAMD64_OpAMD64VPMOVSXWDMasked512(v) + case OpAMD64VPMOVSXWQ128: + return rewriteValueAMD64_OpAMD64VPMOVSXWQ128(v) + case OpAMD64VPMOVSXWQ256: + return rewriteValueAMD64_OpAMD64VPMOVSXWQ256(v) + case OpAMD64VPMOVSXWQ512: + return rewriteValueAMD64_OpAMD64VPMOVSXWQ512(v) + case OpAMD64VPMOVSXWQMasked128: + return rewriteValueAMD64_OpAMD64VPMOVSXWQMasked128(v) + case OpAMD64VPMOVSXWQMasked256: + return rewriteValueAMD64_OpAMD64VPMOVSXWQMasked256(v) + case OpAMD64VPMOVSXWQMasked512: + return rewriteValueAMD64_OpAMD64VPMOVSXWQMasked512(v) + case OpAMD64VPMOVVec16x16ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec16x16ToM(v) + case OpAMD64VPMOVVec16x32ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec16x32ToM(v) + case OpAMD64VPMOVVec16x8ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec16x8ToM(v) + case OpAMD64VPMOVVec32x16ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec32x16ToM(v) + case OpAMD64VPMOVVec32x4ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec32x4ToM(v) + case OpAMD64VPMOVVec32x8ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec32x8ToM(v) + case OpAMD64VPMOVVec64x2ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec64x2ToM(v) + case OpAMD64VPMOVVec64x4ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec64x4ToM(v) + case OpAMD64VPMOVVec64x8ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec64x8ToM(v) + case OpAMD64VPMOVVec8x16ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec8x16ToM(v) + case OpAMD64VPMOVVec8x32ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec8x32ToM(v) + case OpAMD64VPMOVVec8x64ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec8x64ToM(v) + case OpAMD64VPMOVZXBD128: + return rewriteValueAMD64_OpAMD64VPMOVZXBD128(v) + case OpAMD64VPMOVZXBD256: + return rewriteValueAMD64_OpAMD64VPMOVZXBD256(v) + case OpAMD64VPMOVZXBD512: + return rewriteValueAMD64_OpAMD64VPMOVZXBD512(v) + case OpAMD64VPMOVZXBDMasked128: + return rewriteValueAMD64_OpAMD64VPMOVZXBDMasked128(v) + case OpAMD64VPMOVZXBDMasked256: + return rewriteValueAMD64_OpAMD64VPMOVZXBDMasked256(v) + case OpAMD64VPMOVZXBDMasked512: + return rewriteValueAMD64_OpAMD64VPMOVZXBDMasked512(v) + case OpAMD64VPMOVZXBQ128: + return rewriteValueAMD64_OpAMD64VPMOVZXBQ128(v) + case OpAMD64VPMOVZXBQ256: + return rewriteValueAMD64_OpAMD64VPMOVZXBQ256(v) + case OpAMD64VPMOVZXBQ512: + return rewriteValueAMD64_OpAMD64VPMOVZXBQ512(v) + case OpAMD64VPMOVZXBQMasked256: + return rewriteValueAMD64_OpAMD64VPMOVZXBQMasked256(v) + case OpAMD64VPMOVZXBQMasked512: + return rewriteValueAMD64_OpAMD64VPMOVZXBQMasked512(v) + case OpAMD64VPMOVZXBW128: + return rewriteValueAMD64_OpAMD64VPMOVZXBW128(v) + case OpAMD64VPMOVZXBW256: + return rewriteValueAMD64_OpAMD64VPMOVZXBW256(v) + case OpAMD64VPMOVZXBW512: + return rewriteValueAMD64_OpAMD64VPMOVZXBW512(v) + case OpAMD64VPMOVZXBWMasked128: + return rewriteValueAMD64_OpAMD64VPMOVZXBWMasked128(v) + case OpAMD64VPMOVZXBWMasked256: + return rewriteValueAMD64_OpAMD64VPMOVZXBWMasked256(v) + case OpAMD64VPMOVZXBWMasked512: + return rewriteValueAMD64_OpAMD64VPMOVZXBWMasked512(v) + case OpAMD64VPMOVZXDQ128: + return rewriteValueAMD64_OpAMD64VPMOVZXDQ128(v) + case OpAMD64VPMOVZXDQ256: + return rewriteValueAMD64_OpAMD64VPMOVZXDQ256(v) + case OpAMD64VPMOVZXDQ512: + return rewriteValueAMD64_OpAMD64VPMOVZXDQ512(v) + case OpAMD64VPMOVZXDQMasked128: + return rewriteValueAMD64_OpAMD64VPMOVZXDQMasked128(v) + case OpAMD64VPMOVZXDQMasked256: + return rewriteValueAMD64_OpAMD64VPMOVZXDQMasked256(v) + case OpAMD64VPMOVZXDQMasked512: + return rewriteValueAMD64_OpAMD64VPMOVZXDQMasked512(v) + case OpAMD64VPMOVZXWD128: + return rewriteValueAMD64_OpAMD64VPMOVZXWD128(v) + case OpAMD64VPMOVZXWD256: + return rewriteValueAMD64_OpAMD64VPMOVZXWD256(v) + case OpAMD64VPMOVZXWD512: + return rewriteValueAMD64_OpAMD64VPMOVZXWD512(v) + case OpAMD64VPMOVZXWDMasked128: + return rewriteValueAMD64_OpAMD64VPMOVZXWDMasked128(v) + case OpAMD64VPMOVZXWDMasked256: + return rewriteValueAMD64_OpAMD64VPMOVZXWDMasked256(v) + case OpAMD64VPMOVZXWDMasked512: + return rewriteValueAMD64_OpAMD64VPMOVZXWDMasked512(v) + case OpAMD64VPMOVZXWQ128: + return rewriteValueAMD64_OpAMD64VPMOVZXWQ128(v) + case OpAMD64VPMOVZXWQ256: + return rewriteValueAMD64_OpAMD64VPMOVZXWQ256(v) + case OpAMD64VPMOVZXWQ512: + return rewriteValueAMD64_OpAMD64VPMOVZXWQ512(v) + case OpAMD64VPMOVZXWQMasked128: + return rewriteValueAMD64_OpAMD64VPMOVZXWQMasked128(v) + case OpAMD64VPMOVZXWQMasked256: + return rewriteValueAMD64_OpAMD64VPMOVZXWQMasked256(v) + case OpAMD64VPMOVZXWQMasked512: + return rewriteValueAMD64_OpAMD64VPMOVZXWQMasked512(v) + case OpAMD64VPMULDQ128: + return rewriteValueAMD64_OpAMD64VPMULDQ128(v) + case OpAMD64VPMULDQ256: + return rewriteValueAMD64_OpAMD64VPMULDQ256(v) + case OpAMD64VPMULHUW128: + return rewriteValueAMD64_OpAMD64VPMULHUW128(v) + case OpAMD64VPMULHUW256: + return rewriteValueAMD64_OpAMD64VPMULHUW256(v) + case OpAMD64VPMULHUWMasked128: + return rewriteValueAMD64_OpAMD64VPMULHUWMasked128(v) + case OpAMD64VPMULHUWMasked256: + return rewriteValueAMD64_OpAMD64VPMULHUWMasked256(v) + case OpAMD64VPMULHW128: + return rewriteValueAMD64_OpAMD64VPMULHW128(v) + case OpAMD64VPMULHW256: + return rewriteValueAMD64_OpAMD64VPMULHW256(v) + case OpAMD64VPMULHWMasked128: + return rewriteValueAMD64_OpAMD64VPMULHWMasked128(v) + case OpAMD64VPMULHWMasked256: + return rewriteValueAMD64_OpAMD64VPMULHWMasked256(v) + case OpAMD64VPMULLD128: + return rewriteValueAMD64_OpAMD64VPMULLD128(v) + case OpAMD64VPMULLD256: + return rewriteValueAMD64_OpAMD64VPMULLD256(v) + case OpAMD64VPMULLD512: + return rewriteValueAMD64_OpAMD64VPMULLD512(v) + case OpAMD64VPMULLDMasked128: + return rewriteValueAMD64_OpAMD64VPMULLDMasked128(v) + case OpAMD64VPMULLDMasked256: + return rewriteValueAMD64_OpAMD64VPMULLDMasked256(v) + case OpAMD64VPMULLDMasked512: + return rewriteValueAMD64_OpAMD64VPMULLDMasked512(v) + case OpAMD64VPMULLQ128: + return rewriteValueAMD64_OpAMD64VPMULLQ128(v) + case OpAMD64VPMULLQ256: + return rewriteValueAMD64_OpAMD64VPMULLQ256(v) + case OpAMD64VPMULLQ512: + return rewriteValueAMD64_OpAMD64VPMULLQ512(v) + case OpAMD64VPMULLQMasked128: + return rewriteValueAMD64_OpAMD64VPMULLQMasked128(v) + case OpAMD64VPMULLQMasked256: + return rewriteValueAMD64_OpAMD64VPMULLQMasked256(v) + case OpAMD64VPMULLQMasked512: + return rewriteValueAMD64_OpAMD64VPMULLQMasked512(v) + case OpAMD64VPMULLW128: + return rewriteValueAMD64_OpAMD64VPMULLW128(v) + case OpAMD64VPMULLW256: + return rewriteValueAMD64_OpAMD64VPMULLW256(v) + case OpAMD64VPMULLWMasked128: + return rewriteValueAMD64_OpAMD64VPMULLWMasked128(v) + case OpAMD64VPMULLWMasked256: + return rewriteValueAMD64_OpAMD64VPMULLWMasked256(v) + case OpAMD64VPMULUDQ128: + return rewriteValueAMD64_OpAMD64VPMULUDQ128(v) + case OpAMD64VPMULUDQ256: + return rewriteValueAMD64_OpAMD64VPMULUDQ256(v) + case OpAMD64VPOPCNTB128: + return rewriteValueAMD64_OpAMD64VPOPCNTB128(v) + case OpAMD64VPOPCNTB256: + return rewriteValueAMD64_OpAMD64VPOPCNTB256(v) + case OpAMD64VPOPCNTBMasked128: + return rewriteValueAMD64_OpAMD64VPOPCNTBMasked128(v) + case OpAMD64VPOPCNTBMasked256: + return rewriteValueAMD64_OpAMD64VPOPCNTBMasked256(v) + case OpAMD64VPOPCNTD128: + return rewriteValueAMD64_OpAMD64VPOPCNTD128(v) + case OpAMD64VPOPCNTD256: + return rewriteValueAMD64_OpAMD64VPOPCNTD256(v) + case OpAMD64VPOPCNTD512: + return rewriteValueAMD64_OpAMD64VPOPCNTD512(v) + case OpAMD64VPOPCNTDMasked128: + return rewriteValueAMD64_OpAMD64VPOPCNTDMasked128(v) + case OpAMD64VPOPCNTDMasked256: + return rewriteValueAMD64_OpAMD64VPOPCNTDMasked256(v) + case OpAMD64VPOPCNTDMasked512: + return rewriteValueAMD64_OpAMD64VPOPCNTDMasked512(v) + case OpAMD64VPOPCNTQ128: + return rewriteValueAMD64_OpAMD64VPOPCNTQ128(v) + case OpAMD64VPOPCNTQ256: + return rewriteValueAMD64_OpAMD64VPOPCNTQ256(v) + case OpAMD64VPOPCNTQ512: + return rewriteValueAMD64_OpAMD64VPOPCNTQ512(v) + case OpAMD64VPOPCNTQMasked128: + return rewriteValueAMD64_OpAMD64VPOPCNTQMasked128(v) + case OpAMD64VPOPCNTQMasked256: + return rewriteValueAMD64_OpAMD64VPOPCNTQMasked256(v) + case OpAMD64VPOPCNTQMasked512: + return rewriteValueAMD64_OpAMD64VPOPCNTQMasked512(v) + case OpAMD64VPOPCNTW128: + return rewriteValueAMD64_OpAMD64VPOPCNTW128(v) + case OpAMD64VPOPCNTW256: + return rewriteValueAMD64_OpAMD64VPOPCNTW256(v) + case OpAMD64VPOPCNTWMasked128: + return rewriteValueAMD64_OpAMD64VPOPCNTWMasked128(v) + case OpAMD64VPOPCNTWMasked256: + return rewriteValueAMD64_OpAMD64VPOPCNTWMasked256(v) + case OpAMD64VPOR128: + return rewriteValueAMD64_OpAMD64VPOR128(v) + case OpAMD64VPOR256: + return rewriteValueAMD64_OpAMD64VPOR256(v) + case OpAMD64VPORD512: + return rewriteValueAMD64_OpAMD64VPORD512(v) + case OpAMD64VPORDMasked128: + return rewriteValueAMD64_OpAMD64VPORDMasked128(v) + case OpAMD64VPORDMasked256: + return rewriteValueAMD64_OpAMD64VPORDMasked256(v) + case OpAMD64VPORDMasked512: + return rewriteValueAMD64_OpAMD64VPORDMasked512(v) + case OpAMD64VPORQ512: + return rewriteValueAMD64_OpAMD64VPORQ512(v) + case OpAMD64VPORQMasked128: + return rewriteValueAMD64_OpAMD64VPORQMasked128(v) + case OpAMD64VPORQMasked256: + return rewriteValueAMD64_OpAMD64VPORQMasked256(v) + case OpAMD64VPORQMasked512: + return rewriteValueAMD64_OpAMD64VPORQMasked512(v) + case OpAMD64VPROLD128: + return rewriteValueAMD64_OpAMD64VPROLD128(v) + case OpAMD64VPROLD256: + return rewriteValueAMD64_OpAMD64VPROLD256(v) + case OpAMD64VPROLD512: + return rewriteValueAMD64_OpAMD64VPROLD512(v) + case OpAMD64VPROLDMasked128: + return rewriteValueAMD64_OpAMD64VPROLDMasked128(v) + case OpAMD64VPROLDMasked256: + return rewriteValueAMD64_OpAMD64VPROLDMasked256(v) + case OpAMD64VPROLDMasked512: + return rewriteValueAMD64_OpAMD64VPROLDMasked512(v) + case OpAMD64VPROLQ128: + return rewriteValueAMD64_OpAMD64VPROLQ128(v) + case OpAMD64VPROLQ256: + return rewriteValueAMD64_OpAMD64VPROLQ256(v) + case OpAMD64VPROLQ512: + return rewriteValueAMD64_OpAMD64VPROLQ512(v) + case OpAMD64VPROLQMasked128: + return rewriteValueAMD64_OpAMD64VPROLQMasked128(v) + case OpAMD64VPROLQMasked256: + return rewriteValueAMD64_OpAMD64VPROLQMasked256(v) + case OpAMD64VPROLQMasked512: + return rewriteValueAMD64_OpAMD64VPROLQMasked512(v) + case OpAMD64VPROLVD128: + return rewriteValueAMD64_OpAMD64VPROLVD128(v) + case OpAMD64VPROLVD256: + return rewriteValueAMD64_OpAMD64VPROLVD256(v) + case OpAMD64VPROLVD512: + return rewriteValueAMD64_OpAMD64VPROLVD512(v) + case OpAMD64VPROLVDMasked128: + return rewriteValueAMD64_OpAMD64VPROLVDMasked128(v) + case OpAMD64VPROLVDMasked256: + return rewriteValueAMD64_OpAMD64VPROLVDMasked256(v) + case OpAMD64VPROLVDMasked512: + return rewriteValueAMD64_OpAMD64VPROLVDMasked512(v) + case OpAMD64VPROLVQ128: + return rewriteValueAMD64_OpAMD64VPROLVQ128(v) + case OpAMD64VPROLVQ256: + return rewriteValueAMD64_OpAMD64VPROLVQ256(v) + case OpAMD64VPROLVQ512: + return rewriteValueAMD64_OpAMD64VPROLVQ512(v) + case OpAMD64VPROLVQMasked128: + return rewriteValueAMD64_OpAMD64VPROLVQMasked128(v) + case OpAMD64VPROLVQMasked256: + return rewriteValueAMD64_OpAMD64VPROLVQMasked256(v) + case OpAMD64VPROLVQMasked512: + return rewriteValueAMD64_OpAMD64VPROLVQMasked512(v) + case OpAMD64VPRORD128: + return rewriteValueAMD64_OpAMD64VPRORD128(v) + case OpAMD64VPRORD256: + return rewriteValueAMD64_OpAMD64VPRORD256(v) + case OpAMD64VPRORD512: + return rewriteValueAMD64_OpAMD64VPRORD512(v) + case OpAMD64VPRORDMasked128: + return rewriteValueAMD64_OpAMD64VPRORDMasked128(v) + case OpAMD64VPRORDMasked256: + return rewriteValueAMD64_OpAMD64VPRORDMasked256(v) + case OpAMD64VPRORDMasked512: + return rewriteValueAMD64_OpAMD64VPRORDMasked512(v) + case OpAMD64VPRORQ128: + return rewriteValueAMD64_OpAMD64VPRORQ128(v) + case OpAMD64VPRORQ256: + return rewriteValueAMD64_OpAMD64VPRORQ256(v) + case OpAMD64VPRORQ512: + return rewriteValueAMD64_OpAMD64VPRORQ512(v) + case OpAMD64VPRORQMasked128: + return rewriteValueAMD64_OpAMD64VPRORQMasked128(v) + case OpAMD64VPRORQMasked256: + return rewriteValueAMD64_OpAMD64VPRORQMasked256(v) + case OpAMD64VPRORQMasked512: + return rewriteValueAMD64_OpAMD64VPRORQMasked512(v) + case OpAMD64VPRORVD128: + return rewriteValueAMD64_OpAMD64VPRORVD128(v) + case OpAMD64VPRORVD256: + return rewriteValueAMD64_OpAMD64VPRORVD256(v) + case OpAMD64VPRORVD512: + return rewriteValueAMD64_OpAMD64VPRORVD512(v) + case OpAMD64VPRORVDMasked128: + return rewriteValueAMD64_OpAMD64VPRORVDMasked128(v) + case OpAMD64VPRORVDMasked256: + return rewriteValueAMD64_OpAMD64VPRORVDMasked256(v) + case OpAMD64VPRORVDMasked512: + return rewriteValueAMD64_OpAMD64VPRORVDMasked512(v) + case OpAMD64VPRORVQ128: + return rewriteValueAMD64_OpAMD64VPRORVQ128(v) + case OpAMD64VPRORVQ256: + return rewriteValueAMD64_OpAMD64VPRORVQ256(v) + case OpAMD64VPRORVQ512: + return rewriteValueAMD64_OpAMD64VPRORVQ512(v) + case OpAMD64VPRORVQMasked128: + return rewriteValueAMD64_OpAMD64VPRORVQMasked128(v) + case OpAMD64VPRORVQMasked256: + return rewriteValueAMD64_OpAMD64VPRORVQMasked256(v) + case OpAMD64VPRORVQMasked512: + return rewriteValueAMD64_OpAMD64VPRORVQMasked512(v) + case OpAMD64VPSADBW128: + return rewriteValueAMD64_OpAMD64VPSADBW128(v) + case OpAMD64VPSADBW256: + return rewriteValueAMD64_OpAMD64VPSADBW256(v) + case OpAMD64VPSHLDD128: + return rewriteValueAMD64_OpAMD64VPSHLDD128(v) + case OpAMD64VPSHLDD256: + return rewriteValueAMD64_OpAMD64VPSHLDD256(v) + case OpAMD64VPSHLDD512: + return rewriteValueAMD64_OpAMD64VPSHLDD512(v) + case OpAMD64VPSHLDDMasked128: + return rewriteValueAMD64_OpAMD64VPSHLDDMasked128(v) + case OpAMD64VPSHLDDMasked256: + return rewriteValueAMD64_OpAMD64VPSHLDDMasked256(v) + case OpAMD64VPSHLDDMasked512: + return rewriteValueAMD64_OpAMD64VPSHLDDMasked512(v) + case OpAMD64VPSHLDQ128: + return rewriteValueAMD64_OpAMD64VPSHLDQ128(v) + case OpAMD64VPSHLDQ256: + return rewriteValueAMD64_OpAMD64VPSHLDQ256(v) + case OpAMD64VPSHLDQ512: + return rewriteValueAMD64_OpAMD64VPSHLDQ512(v) + case OpAMD64VPSHLDQMasked128: + return rewriteValueAMD64_OpAMD64VPSHLDQMasked128(v) + case OpAMD64VPSHLDQMasked256: + return rewriteValueAMD64_OpAMD64VPSHLDQMasked256(v) + case OpAMD64VPSHLDQMasked512: + return rewriteValueAMD64_OpAMD64VPSHLDQMasked512(v) + case OpAMD64VPSHLDVD128: + return rewriteValueAMD64_OpAMD64VPSHLDVD128(v) + case OpAMD64VPSHLDVD256: + return rewriteValueAMD64_OpAMD64VPSHLDVD256(v) + case OpAMD64VPSHLDVD512: + return rewriteValueAMD64_OpAMD64VPSHLDVD512(v) + case OpAMD64VPSHLDVDMasked128: + return rewriteValueAMD64_OpAMD64VPSHLDVDMasked128(v) + case OpAMD64VPSHLDVDMasked256: + return rewriteValueAMD64_OpAMD64VPSHLDVDMasked256(v) + case OpAMD64VPSHLDVDMasked512: + return rewriteValueAMD64_OpAMD64VPSHLDVDMasked512(v) + case OpAMD64VPSHLDVQ128: + return rewriteValueAMD64_OpAMD64VPSHLDVQ128(v) + case OpAMD64VPSHLDVQ256: + return rewriteValueAMD64_OpAMD64VPSHLDVQ256(v) + case OpAMD64VPSHLDVQ512: + return rewriteValueAMD64_OpAMD64VPSHLDVQ512(v) + case OpAMD64VPSHLDVQMasked128: + return rewriteValueAMD64_OpAMD64VPSHLDVQMasked128(v) + case OpAMD64VPSHLDVQMasked256: + return rewriteValueAMD64_OpAMD64VPSHLDVQMasked256(v) + case OpAMD64VPSHLDVQMasked512: + return rewriteValueAMD64_OpAMD64VPSHLDVQMasked512(v) + case OpAMD64VPSHLDVW128: + return rewriteValueAMD64_OpAMD64VPSHLDVW128(v) + case OpAMD64VPSHLDVW256: + return rewriteValueAMD64_OpAMD64VPSHLDVW256(v) + case OpAMD64VPSHLDVWMasked128: + return rewriteValueAMD64_OpAMD64VPSHLDVWMasked128(v) + case OpAMD64VPSHLDVWMasked256: + return rewriteValueAMD64_OpAMD64VPSHLDVWMasked256(v) + case OpAMD64VPSHLDW128: + return rewriteValueAMD64_OpAMD64VPSHLDW128(v) + case OpAMD64VPSHLDW256: + return rewriteValueAMD64_OpAMD64VPSHLDW256(v) + case OpAMD64VPSHLDWMasked128: + return rewriteValueAMD64_OpAMD64VPSHLDWMasked128(v) + case OpAMD64VPSHLDWMasked256: + return rewriteValueAMD64_OpAMD64VPSHLDWMasked256(v) + case OpAMD64VPSHRDD128: + return rewriteValueAMD64_OpAMD64VPSHRDD128(v) + case OpAMD64VPSHRDD256: + return rewriteValueAMD64_OpAMD64VPSHRDD256(v) + case OpAMD64VPSHRDD512: + return rewriteValueAMD64_OpAMD64VPSHRDD512(v) + case OpAMD64VPSHRDDMasked128: + return rewriteValueAMD64_OpAMD64VPSHRDDMasked128(v) + case OpAMD64VPSHRDDMasked256: + return rewriteValueAMD64_OpAMD64VPSHRDDMasked256(v) + case OpAMD64VPSHRDDMasked512: + return rewriteValueAMD64_OpAMD64VPSHRDDMasked512(v) + case OpAMD64VPSHRDQ128: + return rewriteValueAMD64_OpAMD64VPSHRDQ128(v) + case OpAMD64VPSHRDQ256: + return rewriteValueAMD64_OpAMD64VPSHRDQ256(v) + case OpAMD64VPSHRDQ512: + return rewriteValueAMD64_OpAMD64VPSHRDQ512(v) + case OpAMD64VPSHRDQMasked128: + return rewriteValueAMD64_OpAMD64VPSHRDQMasked128(v) + case OpAMD64VPSHRDQMasked256: + return rewriteValueAMD64_OpAMD64VPSHRDQMasked256(v) + case OpAMD64VPSHRDQMasked512: + return rewriteValueAMD64_OpAMD64VPSHRDQMasked512(v) + case OpAMD64VPSHRDVD128: + return rewriteValueAMD64_OpAMD64VPSHRDVD128(v) + case OpAMD64VPSHRDVD256: + return rewriteValueAMD64_OpAMD64VPSHRDVD256(v) + case OpAMD64VPSHRDVD512: + return rewriteValueAMD64_OpAMD64VPSHRDVD512(v) + case OpAMD64VPSHRDVDMasked128: + return rewriteValueAMD64_OpAMD64VPSHRDVDMasked128(v) + case OpAMD64VPSHRDVDMasked256: + return rewriteValueAMD64_OpAMD64VPSHRDVDMasked256(v) + case OpAMD64VPSHRDVDMasked512: + return rewriteValueAMD64_OpAMD64VPSHRDVDMasked512(v) + case OpAMD64VPSHRDVQ128: + return rewriteValueAMD64_OpAMD64VPSHRDVQ128(v) + case OpAMD64VPSHRDVQ256: + return rewriteValueAMD64_OpAMD64VPSHRDVQ256(v) + case OpAMD64VPSHRDVQ512: + return rewriteValueAMD64_OpAMD64VPSHRDVQ512(v) + case OpAMD64VPSHRDVQMasked128: + return rewriteValueAMD64_OpAMD64VPSHRDVQMasked128(v) + case OpAMD64VPSHRDVQMasked256: + return rewriteValueAMD64_OpAMD64VPSHRDVQMasked256(v) + case OpAMD64VPSHRDVQMasked512: + return rewriteValueAMD64_OpAMD64VPSHRDVQMasked512(v) + case OpAMD64VPSHRDVW128: + return rewriteValueAMD64_OpAMD64VPSHRDVW128(v) + case OpAMD64VPSHRDVW256: + return rewriteValueAMD64_OpAMD64VPSHRDVW256(v) + case OpAMD64VPSHRDVWMasked128: + return rewriteValueAMD64_OpAMD64VPSHRDVWMasked128(v) + case OpAMD64VPSHRDVWMasked256: + return rewriteValueAMD64_OpAMD64VPSHRDVWMasked256(v) + case OpAMD64VPSHRDW128: + return rewriteValueAMD64_OpAMD64VPSHRDW128(v) + case OpAMD64VPSHRDW256: + return rewriteValueAMD64_OpAMD64VPSHRDW256(v) + case OpAMD64VPSHRDWMasked128: + return rewriteValueAMD64_OpAMD64VPSHRDWMasked128(v) + case OpAMD64VPSHRDWMasked256: + return rewriteValueAMD64_OpAMD64VPSHRDWMasked256(v) + case OpAMD64VPSHUFB128: + return rewriteValueAMD64_OpAMD64VPSHUFB128(v) + case OpAMD64VPSHUFB256: + return rewriteValueAMD64_OpAMD64VPSHUFB256(v) + case OpAMD64VPSHUFBMasked128: + return rewriteValueAMD64_OpAMD64VPSHUFBMasked128(v) + case OpAMD64VPSHUFBMasked256: + return rewriteValueAMD64_OpAMD64VPSHUFBMasked256(v) + case OpAMD64VPSHUFD128: + return rewriteValueAMD64_OpAMD64VPSHUFD128(v) + case OpAMD64VPSHUFD256: + return rewriteValueAMD64_OpAMD64VPSHUFD256(v) + case OpAMD64VPSHUFD512: + return rewriteValueAMD64_OpAMD64VPSHUFD512(v) + case OpAMD64VPSHUFDMasked128: + return rewriteValueAMD64_OpAMD64VPSHUFDMasked128(v) + case OpAMD64VPSHUFDMasked256: + return rewriteValueAMD64_OpAMD64VPSHUFDMasked256(v) + case OpAMD64VPSHUFDMasked512: + return rewriteValueAMD64_OpAMD64VPSHUFDMasked512(v) + case OpAMD64VPSHUFHW128: + return rewriteValueAMD64_OpAMD64VPSHUFHW128(v) + case OpAMD64VPSHUFHW256: + return rewriteValueAMD64_OpAMD64VPSHUFHW256(v) + case OpAMD64VPSHUFHWMasked128: + return rewriteValueAMD64_OpAMD64VPSHUFHWMasked128(v) + case OpAMD64VPSHUFHWMasked256: + return rewriteValueAMD64_OpAMD64VPSHUFHWMasked256(v) + case OpAMD64VPSHUFLW128: + return rewriteValueAMD64_OpAMD64VPSHUFLW128(v) + case OpAMD64VPSHUFLW256: + return rewriteValueAMD64_OpAMD64VPSHUFLW256(v) + case OpAMD64VPSHUFLWMasked128: + return rewriteValueAMD64_OpAMD64VPSHUFLWMasked128(v) + case OpAMD64VPSHUFLWMasked256: + return rewriteValueAMD64_OpAMD64VPSHUFLWMasked256(v) + case OpAMD64VPSIGNB128: + return rewriteValueAMD64_OpAMD64VPSIGNB128(v) + case OpAMD64VPSIGNB256: + return rewriteValueAMD64_OpAMD64VPSIGNB256(v) + case OpAMD64VPSIGND128: + return rewriteValueAMD64_OpAMD64VPSIGND128(v) + case OpAMD64VPSIGND256: + return rewriteValueAMD64_OpAMD64VPSIGND256(v) + case OpAMD64VPSIGNW128: + return rewriteValueAMD64_OpAMD64VPSIGNW128(v) + case OpAMD64VPSIGNW256: + return rewriteValueAMD64_OpAMD64VPSIGNW256(v) + case OpAMD64VPSLLD128: + return rewriteValueAMD64_OpAMD64VPSLLD128(v) + case OpAMD64VPSLLD128const: + return rewriteValueAMD64_OpAMD64VPSLLD128const(v) + case OpAMD64VPSLLD256: + return rewriteValueAMD64_OpAMD64VPSLLD256(v) + case OpAMD64VPSLLD256const: + return rewriteValueAMD64_OpAMD64VPSLLD256const(v) + case OpAMD64VPSLLD512: + return rewriteValueAMD64_OpAMD64VPSLLD512(v) + case OpAMD64VPSLLD512const: + return rewriteValueAMD64_OpAMD64VPSLLD512const(v) + case OpAMD64VPSLLDMasked128: + return rewriteValueAMD64_OpAMD64VPSLLDMasked128(v) + case OpAMD64VPSLLDMasked128const: + return rewriteValueAMD64_OpAMD64VPSLLDMasked128const(v) + case OpAMD64VPSLLDMasked256: + return rewriteValueAMD64_OpAMD64VPSLLDMasked256(v) + case OpAMD64VPSLLDMasked256const: + return rewriteValueAMD64_OpAMD64VPSLLDMasked256const(v) + case OpAMD64VPSLLDMasked512: + return rewriteValueAMD64_OpAMD64VPSLLDMasked512(v) + case OpAMD64VPSLLDMasked512const: + return rewriteValueAMD64_OpAMD64VPSLLDMasked512const(v) + case OpAMD64VPSLLQ128: + return rewriteValueAMD64_OpAMD64VPSLLQ128(v) + case OpAMD64VPSLLQ128const: + return rewriteValueAMD64_OpAMD64VPSLLQ128const(v) + case OpAMD64VPSLLQ256: + return rewriteValueAMD64_OpAMD64VPSLLQ256(v) + case OpAMD64VPSLLQ256const: + return rewriteValueAMD64_OpAMD64VPSLLQ256const(v) + case OpAMD64VPSLLQ512: + return rewriteValueAMD64_OpAMD64VPSLLQ512(v) + case OpAMD64VPSLLQ512const: + return rewriteValueAMD64_OpAMD64VPSLLQ512const(v) + case OpAMD64VPSLLQMasked128: + return rewriteValueAMD64_OpAMD64VPSLLQMasked128(v) + case OpAMD64VPSLLQMasked128const: + return rewriteValueAMD64_OpAMD64VPSLLQMasked128const(v) + case OpAMD64VPSLLQMasked256: + return rewriteValueAMD64_OpAMD64VPSLLQMasked256(v) + case OpAMD64VPSLLQMasked256const: + return rewriteValueAMD64_OpAMD64VPSLLQMasked256const(v) + case OpAMD64VPSLLQMasked512: + return rewriteValueAMD64_OpAMD64VPSLLQMasked512(v) + case OpAMD64VPSLLQMasked512const: + return rewriteValueAMD64_OpAMD64VPSLLQMasked512const(v) + case OpAMD64VPSLLVD128: + return rewriteValueAMD64_OpAMD64VPSLLVD128(v) + case OpAMD64VPSLLVD256: + return rewriteValueAMD64_OpAMD64VPSLLVD256(v) + case OpAMD64VPSLLVD512: + return rewriteValueAMD64_OpAMD64VPSLLVD512(v) + case OpAMD64VPSLLVDMasked128: + return rewriteValueAMD64_OpAMD64VPSLLVDMasked128(v) + case OpAMD64VPSLLVDMasked256: + return rewriteValueAMD64_OpAMD64VPSLLVDMasked256(v) + case OpAMD64VPSLLVDMasked512: + return rewriteValueAMD64_OpAMD64VPSLLVDMasked512(v) + case OpAMD64VPSLLVQ128: + return rewriteValueAMD64_OpAMD64VPSLLVQ128(v) + case OpAMD64VPSLLVQ256: + return rewriteValueAMD64_OpAMD64VPSLLVQ256(v) + case OpAMD64VPSLLVQ512: + return rewriteValueAMD64_OpAMD64VPSLLVQ512(v) + case OpAMD64VPSLLVQMasked128: + return rewriteValueAMD64_OpAMD64VPSLLVQMasked128(v) + case OpAMD64VPSLLVQMasked256: + return rewriteValueAMD64_OpAMD64VPSLLVQMasked256(v) + case OpAMD64VPSLLVQMasked512: + return rewriteValueAMD64_OpAMD64VPSLLVQMasked512(v) + case OpAMD64VPSLLVW128: + return rewriteValueAMD64_OpAMD64VPSLLVW128(v) + case OpAMD64VPSLLVW256: + return rewriteValueAMD64_OpAMD64VPSLLVW256(v) + case OpAMD64VPSLLVWMasked128: + return rewriteValueAMD64_OpAMD64VPSLLVWMasked128(v) + case OpAMD64VPSLLVWMasked256: + return rewriteValueAMD64_OpAMD64VPSLLVWMasked256(v) + case OpAMD64VPSLLW128: + return rewriteValueAMD64_OpAMD64VPSLLW128(v) + case OpAMD64VPSLLW128const: + return rewriteValueAMD64_OpAMD64VPSLLW128const(v) + case OpAMD64VPSLLW256: + return rewriteValueAMD64_OpAMD64VPSLLW256(v) + case OpAMD64VPSLLW256const: + return rewriteValueAMD64_OpAMD64VPSLLW256const(v) + case OpAMD64VPSLLW512: + return rewriteValueAMD64_OpAMD64VPSLLW512(v) + case OpAMD64VPSLLW512const: + return rewriteValueAMD64_OpAMD64VPSLLW512const(v) + case OpAMD64VPSLLWMasked128: + return rewriteValueAMD64_OpAMD64VPSLLWMasked128(v) + case OpAMD64VPSLLWMasked128const: + return rewriteValueAMD64_OpAMD64VPSLLWMasked128const(v) + case OpAMD64VPSLLWMasked256: + return rewriteValueAMD64_OpAMD64VPSLLWMasked256(v) + case OpAMD64VPSLLWMasked256const: + return rewriteValueAMD64_OpAMD64VPSLLWMasked256const(v) + case OpAMD64VPSLLWMasked512: + return rewriteValueAMD64_OpAMD64VPSLLWMasked512(v) + case OpAMD64VPSLLWMasked512const: + return rewriteValueAMD64_OpAMD64VPSLLWMasked512const(v) + case OpAMD64VPSRAD128: + return rewriteValueAMD64_OpAMD64VPSRAD128(v) + case OpAMD64VPSRAD128const: + return rewriteValueAMD64_OpAMD64VPSRAD128const(v) + case OpAMD64VPSRAD256: + return rewriteValueAMD64_OpAMD64VPSRAD256(v) + case OpAMD64VPSRAD256const: + return rewriteValueAMD64_OpAMD64VPSRAD256const(v) + case OpAMD64VPSRAD512: + return rewriteValueAMD64_OpAMD64VPSRAD512(v) + case OpAMD64VPSRAD512const: + return rewriteValueAMD64_OpAMD64VPSRAD512const(v) + case OpAMD64VPSRADMasked128: + return rewriteValueAMD64_OpAMD64VPSRADMasked128(v) + case OpAMD64VPSRADMasked128const: + return rewriteValueAMD64_OpAMD64VPSRADMasked128const(v) + case OpAMD64VPSRADMasked256: + return rewriteValueAMD64_OpAMD64VPSRADMasked256(v) + case OpAMD64VPSRADMasked256const: + return rewriteValueAMD64_OpAMD64VPSRADMasked256const(v) + case OpAMD64VPSRADMasked512: + return rewriteValueAMD64_OpAMD64VPSRADMasked512(v) + case OpAMD64VPSRADMasked512const: + return rewriteValueAMD64_OpAMD64VPSRADMasked512const(v) + case OpAMD64VPSRAQ128: + return rewriteValueAMD64_OpAMD64VPSRAQ128(v) + case OpAMD64VPSRAQ128const: + return rewriteValueAMD64_OpAMD64VPSRAQ128const(v) + case OpAMD64VPSRAQ256: + return rewriteValueAMD64_OpAMD64VPSRAQ256(v) + case OpAMD64VPSRAQ256const: + return rewriteValueAMD64_OpAMD64VPSRAQ256const(v) + case OpAMD64VPSRAQ512: + return rewriteValueAMD64_OpAMD64VPSRAQ512(v) + case OpAMD64VPSRAQ512const: + return rewriteValueAMD64_OpAMD64VPSRAQ512const(v) + case OpAMD64VPSRAQMasked128: + return rewriteValueAMD64_OpAMD64VPSRAQMasked128(v) + case OpAMD64VPSRAQMasked128const: + return rewriteValueAMD64_OpAMD64VPSRAQMasked128const(v) + case OpAMD64VPSRAQMasked256: + return rewriteValueAMD64_OpAMD64VPSRAQMasked256(v) + case OpAMD64VPSRAQMasked256const: + return rewriteValueAMD64_OpAMD64VPSRAQMasked256const(v) + case OpAMD64VPSRAQMasked512: + return rewriteValueAMD64_OpAMD64VPSRAQMasked512(v) + case OpAMD64VPSRAQMasked512const: + return rewriteValueAMD64_OpAMD64VPSRAQMasked512const(v) + case OpAMD64VPSRAVD128: + return rewriteValueAMD64_OpAMD64VPSRAVD128(v) + case OpAMD64VPSRAVD256: + return rewriteValueAMD64_OpAMD64VPSRAVD256(v) + case OpAMD64VPSRAVD512: + return rewriteValueAMD64_OpAMD64VPSRAVD512(v) + case OpAMD64VPSRAVDMasked128: + return rewriteValueAMD64_OpAMD64VPSRAVDMasked128(v) + case OpAMD64VPSRAVDMasked256: + return rewriteValueAMD64_OpAMD64VPSRAVDMasked256(v) + case OpAMD64VPSRAVDMasked512: + return rewriteValueAMD64_OpAMD64VPSRAVDMasked512(v) + case OpAMD64VPSRAVQ128: + return rewriteValueAMD64_OpAMD64VPSRAVQ128(v) + case OpAMD64VPSRAVQ256: + return rewriteValueAMD64_OpAMD64VPSRAVQ256(v) + case OpAMD64VPSRAVQ512: + return rewriteValueAMD64_OpAMD64VPSRAVQ512(v) + case OpAMD64VPSRAVQMasked128: + return rewriteValueAMD64_OpAMD64VPSRAVQMasked128(v) + case OpAMD64VPSRAVQMasked256: + return rewriteValueAMD64_OpAMD64VPSRAVQMasked256(v) + case OpAMD64VPSRAVQMasked512: + return rewriteValueAMD64_OpAMD64VPSRAVQMasked512(v) + case OpAMD64VPSRAVW128: + return rewriteValueAMD64_OpAMD64VPSRAVW128(v) + case OpAMD64VPSRAVW256: + return rewriteValueAMD64_OpAMD64VPSRAVW256(v) + case OpAMD64VPSRAVWMasked128: + return rewriteValueAMD64_OpAMD64VPSRAVWMasked128(v) + case OpAMD64VPSRAVWMasked256: + return rewriteValueAMD64_OpAMD64VPSRAVWMasked256(v) + case OpAMD64VPSRAW128: + return rewriteValueAMD64_OpAMD64VPSRAW128(v) + case OpAMD64VPSRAW128const: + return rewriteValueAMD64_OpAMD64VPSRAW128const(v) + case OpAMD64VPSRAW256: + return rewriteValueAMD64_OpAMD64VPSRAW256(v) + case OpAMD64VPSRAW256const: + return rewriteValueAMD64_OpAMD64VPSRAW256const(v) + case OpAMD64VPSRAW512: + return rewriteValueAMD64_OpAMD64VPSRAW512(v) + case OpAMD64VPSRAW512const: + return rewriteValueAMD64_OpAMD64VPSRAW512const(v) + case OpAMD64VPSRAWMasked128: + return rewriteValueAMD64_OpAMD64VPSRAWMasked128(v) + case OpAMD64VPSRAWMasked128const: + return rewriteValueAMD64_OpAMD64VPSRAWMasked128const(v) + case OpAMD64VPSRAWMasked256: + return rewriteValueAMD64_OpAMD64VPSRAWMasked256(v) + case OpAMD64VPSRAWMasked256const: + return rewriteValueAMD64_OpAMD64VPSRAWMasked256const(v) + case OpAMD64VPSRAWMasked512: + return rewriteValueAMD64_OpAMD64VPSRAWMasked512(v) + case OpAMD64VPSRAWMasked512const: + return rewriteValueAMD64_OpAMD64VPSRAWMasked512const(v) + case OpAMD64VPSRLD128: + return rewriteValueAMD64_OpAMD64VPSRLD128(v) + case OpAMD64VPSRLD128const: + return rewriteValueAMD64_OpAMD64VPSRLD128const(v) + case OpAMD64VPSRLD256: + return rewriteValueAMD64_OpAMD64VPSRLD256(v) + case OpAMD64VPSRLD256const: + return rewriteValueAMD64_OpAMD64VPSRLD256const(v) + case OpAMD64VPSRLD512: + return rewriteValueAMD64_OpAMD64VPSRLD512(v) + case OpAMD64VPSRLD512const: + return rewriteValueAMD64_OpAMD64VPSRLD512const(v) + case OpAMD64VPSRLDMasked128: + return rewriteValueAMD64_OpAMD64VPSRLDMasked128(v) + case OpAMD64VPSRLDMasked128const: + return rewriteValueAMD64_OpAMD64VPSRLDMasked128const(v) + case OpAMD64VPSRLDMasked256: + return rewriteValueAMD64_OpAMD64VPSRLDMasked256(v) + case OpAMD64VPSRLDMasked256const: + return rewriteValueAMD64_OpAMD64VPSRLDMasked256const(v) + case OpAMD64VPSRLDMasked512: + return rewriteValueAMD64_OpAMD64VPSRLDMasked512(v) + case OpAMD64VPSRLDMasked512const: + return rewriteValueAMD64_OpAMD64VPSRLDMasked512const(v) + case OpAMD64VPSRLQ128: + return rewriteValueAMD64_OpAMD64VPSRLQ128(v) + case OpAMD64VPSRLQ128const: + return rewriteValueAMD64_OpAMD64VPSRLQ128const(v) + case OpAMD64VPSRLQ256: + return rewriteValueAMD64_OpAMD64VPSRLQ256(v) + case OpAMD64VPSRLQ256const: + return rewriteValueAMD64_OpAMD64VPSRLQ256const(v) + case OpAMD64VPSRLQ512: + return rewriteValueAMD64_OpAMD64VPSRLQ512(v) + case OpAMD64VPSRLQ512const: + return rewriteValueAMD64_OpAMD64VPSRLQ512const(v) + case OpAMD64VPSRLQMasked128: + return rewriteValueAMD64_OpAMD64VPSRLQMasked128(v) + case OpAMD64VPSRLQMasked128const: + return rewriteValueAMD64_OpAMD64VPSRLQMasked128const(v) + case OpAMD64VPSRLQMasked256: + return rewriteValueAMD64_OpAMD64VPSRLQMasked256(v) + case OpAMD64VPSRLQMasked256const: + return rewriteValueAMD64_OpAMD64VPSRLQMasked256const(v) + case OpAMD64VPSRLQMasked512: + return rewriteValueAMD64_OpAMD64VPSRLQMasked512(v) + case OpAMD64VPSRLQMasked512const: + return rewriteValueAMD64_OpAMD64VPSRLQMasked512const(v) + case OpAMD64VPSRLVD128: + return rewriteValueAMD64_OpAMD64VPSRLVD128(v) + case OpAMD64VPSRLVD256: + return rewriteValueAMD64_OpAMD64VPSRLVD256(v) + case OpAMD64VPSRLVD512: + return rewriteValueAMD64_OpAMD64VPSRLVD512(v) + case OpAMD64VPSRLVDMasked128: + return rewriteValueAMD64_OpAMD64VPSRLVDMasked128(v) + case OpAMD64VPSRLVDMasked256: + return rewriteValueAMD64_OpAMD64VPSRLVDMasked256(v) + case OpAMD64VPSRLVDMasked512: + return rewriteValueAMD64_OpAMD64VPSRLVDMasked512(v) + case OpAMD64VPSRLVQ128: + return rewriteValueAMD64_OpAMD64VPSRLVQ128(v) + case OpAMD64VPSRLVQ256: + return rewriteValueAMD64_OpAMD64VPSRLVQ256(v) + case OpAMD64VPSRLVQ512: + return rewriteValueAMD64_OpAMD64VPSRLVQ512(v) + case OpAMD64VPSRLVQMasked128: + return rewriteValueAMD64_OpAMD64VPSRLVQMasked128(v) + case OpAMD64VPSRLVQMasked256: + return rewriteValueAMD64_OpAMD64VPSRLVQMasked256(v) + case OpAMD64VPSRLVQMasked512: + return rewriteValueAMD64_OpAMD64VPSRLVQMasked512(v) + case OpAMD64VPSRLVW128: + return rewriteValueAMD64_OpAMD64VPSRLVW128(v) + case OpAMD64VPSRLVW256: + return rewriteValueAMD64_OpAMD64VPSRLVW256(v) + case OpAMD64VPSRLVWMasked128: + return rewriteValueAMD64_OpAMD64VPSRLVWMasked128(v) + case OpAMD64VPSRLVWMasked256: + return rewriteValueAMD64_OpAMD64VPSRLVWMasked256(v) + case OpAMD64VPSRLW128: + return rewriteValueAMD64_OpAMD64VPSRLW128(v) + case OpAMD64VPSRLW128const: + return rewriteValueAMD64_OpAMD64VPSRLW128const(v) + case OpAMD64VPSRLW256: + return rewriteValueAMD64_OpAMD64VPSRLW256(v) + case OpAMD64VPSRLW256const: + return rewriteValueAMD64_OpAMD64VPSRLW256const(v) + case OpAMD64VPSRLW512: + return rewriteValueAMD64_OpAMD64VPSRLW512(v) + case OpAMD64VPSRLW512const: + return rewriteValueAMD64_OpAMD64VPSRLW512const(v) + case OpAMD64VPSRLWMasked128: + return rewriteValueAMD64_OpAMD64VPSRLWMasked128(v) + case OpAMD64VPSRLWMasked128const: + return rewriteValueAMD64_OpAMD64VPSRLWMasked128const(v) + case OpAMD64VPSRLWMasked256: + return rewriteValueAMD64_OpAMD64VPSRLWMasked256(v) + case OpAMD64VPSRLWMasked256const: + return rewriteValueAMD64_OpAMD64VPSRLWMasked256const(v) + case OpAMD64VPSRLWMasked512: + return rewriteValueAMD64_OpAMD64VPSRLWMasked512(v) + case OpAMD64VPSRLWMasked512const: + return rewriteValueAMD64_OpAMD64VPSRLWMasked512const(v) + case OpAMD64VPSUBB128: + return rewriteValueAMD64_OpAMD64VPSUBB128(v) + case OpAMD64VPSUBB256: + return rewriteValueAMD64_OpAMD64VPSUBB256(v) + case OpAMD64VPSUBBMasked128: + return rewriteValueAMD64_OpAMD64VPSUBBMasked128(v) + case OpAMD64VPSUBBMasked256: + return rewriteValueAMD64_OpAMD64VPSUBBMasked256(v) + case OpAMD64VPSUBD128: + return rewriteValueAMD64_OpAMD64VPSUBD128(v) + case OpAMD64VPSUBD256: + return rewriteValueAMD64_OpAMD64VPSUBD256(v) + case OpAMD64VPSUBD512: + return rewriteValueAMD64_OpAMD64VPSUBD512(v) + case OpAMD64VPSUBDMasked128: + return rewriteValueAMD64_OpAMD64VPSUBDMasked128(v) + case OpAMD64VPSUBDMasked256: + return rewriteValueAMD64_OpAMD64VPSUBDMasked256(v) + case OpAMD64VPSUBDMasked512: + return rewriteValueAMD64_OpAMD64VPSUBDMasked512(v) + case OpAMD64VPSUBQ128: + return rewriteValueAMD64_OpAMD64VPSUBQ128(v) + case OpAMD64VPSUBQ256: + return rewriteValueAMD64_OpAMD64VPSUBQ256(v) + case OpAMD64VPSUBQ512: + return rewriteValueAMD64_OpAMD64VPSUBQ512(v) + case OpAMD64VPSUBQMasked128: + return rewriteValueAMD64_OpAMD64VPSUBQMasked128(v) + case OpAMD64VPSUBQMasked256: + return rewriteValueAMD64_OpAMD64VPSUBQMasked256(v) + case OpAMD64VPSUBQMasked512: + return rewriteValueAMD64_OpAMD64VPSUBQMasked512(v) + case OpAMD64VPSUBSB128: + return rewriteValueAMD64_OpAMD64VPSUBSB128(v) + case OpAMD64VPSUBSB256: + return rewriteValueAMD64_OpAMD64VPSUBSB256(v) + case OpAMD64VPSUBSBMasked128: + return rewriteValueAMD64_OpAMD64VPSUBSBMasked128(v) + case OpAMD64VPSUBSBMasked256: + return rewriteValueAMD64_OpAMD64VPSUBSBMasked256(v) + case OpAMD64VPSUBSW128: + return rewriteValueAMD64_OpAMD64VPSUBSW128(v) + case OpAMD64VPSUBSW256: + return rewriteValueAMD64_OpAMD64VPSUBSW256(v) + case OpAMD64VPSUBSWMasked128: + return rewriteValueAMD64_OpAMD64VPSUBSWMasked128(v) + case OpAMD64VPSUBSWMasked256: + return rewriteValueAMD64_OpAMD64VPSUBSWMasked256(v) + case OpAMD64VPSUBUSB128: + return rewriteValueAMD64_OpAMD64VPSUBUSB128(v) + case OpAMD64VPSUBUSB256: + return rewriteValueAMD64_OpAMD64VPSUBUSB256(v) + case OpAMD64VPSUBUSBMasked128: + return rewriteValueAMD64_OpAMD64VPSUBUSBMasked128(v) + case OpAMD64VPSUBUSBMasked256: + return rewriteValueAMD64_OpAMD64VPSUBUSBMasked256(v) + case OpAMD64VPSUBUSW128: + return rewriteValueAMD64_OpAMD64VPSUBUSW128(v) + case OpAMD64VPSUBUSW256: + return rewriteValueAMD64_OpAMD64VPSUBUSW256(v) + case OpAMD64VPSUBUSWMasked128: + return rewriteValueAMD64_OpAMD64VPSUBUSWMasked128(v) + case OpAMD64VPSUBUSWMasked256: + return rewriteValueAMD64_OpAMD64VPSUBUSWMasked256(v) + case OpAMD64VPSUBW128: + return rewriteValueAMD64_OpAMD64VPSUBW128(v) + case OpAMD64VPSUBW256: + return rewriteValueAMD64_OpAMD64VPSUBW256(v) + case OpAMD64VPSUBWMasked128: + return rewriteValueAMD64_OpAMD64VPSUBWMasked128(v) + case OpAMD64VPSUBWMasked256: + return rewriteValueAMD64_OpAMD64VPSUBWMasked256(v) + case OpAMD64VPTERNLOGD128: + return rewriteValueAMD64_OpAMD64VPTERNLOGD128(v) + case OpAMD64VPTERNLOGD256: + return rewriteValueAMD64_OpAMD64VPTERNLOGD256(v) + case OpAMD64VPTERNLOGD512: + return rewriteValueAMD64_OpAMD64VPTERNLOGD512(v) + case OpAMD64VPTERNLOGQ128: + return rewriteValueAMD64_OpAMD64VPTERNLOGQ128(v) + case OpAMD64VPTERNLOGQ256: + return rewriteValueAMD64_OpAMD64VPTERNLOGQ256(v) + case OpAMD64VPTERNLOGQ512: + return rewriteValueAMD64_OpAMD64VPTERNLOGQ512(v) + case OpAMD64VPUNPCKHDQ128: + return rewriteValueAMD64_OpAMD64VPUNPCKHDQ128(v) + case OpAMD64VPUNPCKHDQ256: + return rewriteValueAMD64_OpAMD64VPUNPCKHDQ256(v) + case OpAMD64VPUNPCKHDQ512: + return rewriteValueAMD64_OpAMD64VPUNPCKHDQ512(v) + case OpAMD64VPUNPCKHQDQ128: + return rewriteValueAMD64_OpAMD64VPUNPCKHQDQ128(v) + case OpAMD64VPUNPCKHQDQ256: + return rewriteValueAMD64_OpAMD64VPUNPCKHQDQ256(v) + case OpAMD64VPUNPCKHQDQ512: + return rewriteValueAMD64_OpAMD64VPUNPCKHQDQ512(v) + case OpAMD64VPUNPCKHWD128: + return rewriteValueAMD64_OpAMD64VPUNPCKHWD128(v) + case OpAMD64VPUNPCKHWD256: + return rewriteValueAMD64_OpAMD64VPUNPCKHWD256(v) + case OpAMD64VPUNPCKLDQ128: + return rewriteValueAMD64_OpAMD64VPUNPCKLDQ128(v) + case OpAMD64VPUNPCKLDQ256: + return rewriteValueAMD64_OpAMD64VPUNPCKLDQ256(v) + case OpAMD64VPUNPCKLDQ512: + return rewriteValueAMD64_OpAMD64VPUNPCKLDQ512(v) + case OpAMD64VPUNPCKLQDQ128: + return rewriteValueAMD64_OpAMD64VPUNPCKLQDQ128(v) + case OpAMD64VPUNPCKLQDQ256: + return rewriteValueAMD64_OpAMD64VPUNPCKLQDQ256(v) + case OpAMD64VPUNPCKLQDQ512: + return rewriteValueAMD64_OpAMD64VPUNPCKLQDQ512(v) + case OpAMD64VPUNPCKLWD128: + return rewriteValueAMD64_OpAMD64VPUNPCKLWD128(v) + case OpAMD64VPUNPCKLWD256: + return rewriteValueAMD64_OpAMD64VPUNPCKLWD256(v) + case OpAMD64VPXOR128: + return rewriteValueAMD64_OpAMD64VPXOR128(v) + case OpAMD64VPXOR256: + return rewriteValueAMD64_OpAMD64VPXOR256(v) + case OpAMD64VPXORD512: + return rewriteValueAMD64_OpAMD64VPXORD512(v) + case OpAMD64VPXORDMasked128: + return rewriteValueAMD64_OpAMD64VPXORDMasked128(v) + case OpAMD64VPXORDMasked256: + return rewriteValueAMD64_OpAMD64VPXORDMasked256(v) + case OpAMD64VPXORDMasked512: + return rewriteValueAMD64_OpAMD64VPXORDMasked512(v) + case OpAMD64VPXORQ512: + return rewriteValueAMD64_OpAMD64VPXORQ512(v) + case OpAMD64VPXORQMasked128: + return rewriteValueAMD64_OpAMD64VPXORQMasked128(v) + case OpAMD64VPXORQMasked256: + return rewriteValueAMD64_OpAMD64VPXORQMasked256(v) + case OpAMD64VPXORQMasked512: + return rewriteValueAMD64_OpAMD64VPXORQMasked512(v) + case OpAMD64VRCP14PD128: + return rewriteValueAMD64_OpAMD64VRCP14PD128(v) + case OpAMD64VRCP14PD256: + return rewriteValueAMD64_OpAMD64VRCP14PD256(v) + case OpAMD64VRCP14PD512: + return rewriteValueAMD64_OpAMD64VRCP14PD512(v) + case OpAMD64VRCP14PDMasked128: + return rewriteValueAMD64_OpAMD64VRCP14PDMasked128(v) + case OpAMD64VRCP14PDMasked256: + return rewriteValueAMD64_OpAMD64VRCP14PDMasked256(v) + case OpAMD64VRCP14PDMasked512: + return rewriteValueAMD64_OpAMD64VRCP14PDMasked512(v) + case OpAMD64VRCP14PS512: + return rewriteValueAMD64_OpAMD64VRCP14PS512(v) + case OpAMD64VRCP14PSMasked128: + return rewriteValueAMD64_OpAMD64VRCP14PSMasked128(v) + case OpAMD64VRCP14PSMasked256: + return rewriteValueAMD64_OpAMD64VRCP14PSMasked256(v) + case OpAMD64VRCP14PSMasked512: + return rewriteValueAMD64_OpAMD64VRCP14PSMasked512(v) + case OpAMD64VRCPPS128: + return rewriteValueAMD64_OpAMD64VRCPPS128(v) + case OpAMD64VRCPPS256: + return rewriteValueAMD64_OpAMD64VRCPPS256(v) + case OpAMD64VREDUCEPD128: + return rewriteValueAMD64_OpAMD64VREDUCEPD128(v) + case OpAMD64VREDUCEPD256: + return rewriteValueAMD64_OpAMD64VREDUCEPD256(v) + case OpAMD64VREDUCEPD512: + return rewriteValueAMD64_OpAMD64VREDUCEPD512(v) + case OpAMD64VREDUCEPDMasked128: + return rewriteValueAMD64_OpAMD64VREDUCEPDMasked128(v) + case OpAMD64VREDUCEPDMasked256: + return rewriteValueAMD64_OpAMD64VREDUCEPDMasked256(v) + case OpAMD64VREDUCEPDMasked512: + return rewriteValueAMD64_OpAMD64VREDUCEPDMasked512(v) + case OpAMD64VREDUCEPS128: + return rewriteValueAMD64_OpAMD64VREDUCEPS128(v) + case OpAMD64VREDUCEPS256: + return rewriteValueAMD64_OpAMD64VREDUCEPS256(v) + case OpAMD64VREDUCEPS512: + return rewriteValueAMD64_OpAMD64VREDUCEPS512(v) + case OpAMD64VREDUCEPSMasked128: + return rewriteValueAMD64_OpAMD64VREDUCEPSMasked128(v) + case OpAMD64VREDUCEPSMasked256: + return rewriteValueAMD64_OpAMD64VREDUCEPSMasked256(v) + case OpAMD64VREDUCEPSMasked512: + return rewriteValueAMD64_OpAMD64VREDUCEPSMasked512(v) + case OpAMD64VRNDSCALEPD128: + return rewriteValueAMD64_OpAMD64VRNDSCALEPD128(v) + case OpAMD64VRNDSCALEPD256: + return rewriteValueAMD64_OpAMD64VRNDSCALEPD256(v) + case OpAMD64VRNDSCALEPD512: + return rewriteValueAMD64_OpAMD64VRNDSCALEPD512(v) + case OpAMD64VRNDSCALEPDMasked128: + return rewriteValueAMD64_OpAMD64VRNDSCALEPDMasked128(v) + case OpAMD64VRNDSCALEPDMasked256: + return rewriteValueAMD64_OpAMD64VRNDSCALEPDMasked256(v) + case OpAMD64VRNDSCALEPDMasked512: + return rewriteValueAMD64_OpAMD64VRNDSCALEPDMasked512(v) + case OpAMD64VRNDSCALEPS128: + return rewriteValueAMD64_OpAMD64VRNDSCALEPS128(v) + case OpAMD64VRNDSCALEPS256: + return rewriteValueAMD64_OpAMD64VRNDSCALEPS256(v) + case OpAMD64VRNDSCALEPS512: + return rewriteValueAMD64_OpAMD64VRNDSCALEPS512(v) + case OpAMD64VRNDSCALEPSMasked128: + return rewriteValueAMD64_OpAMD64VRNDSCALEPSMasked128(v) + case OpAMD64VRNDSCALEPSMasked256: + return rewriteValueAMD64_OpAMD64VRNDSCALEPSMasked256(v) + case OpAMD64VRNDSCALEPSMasked512: + return rewriteValueAMD64_OpAMD64VRNDSCALEPSMasked512(v) + case OpAMD64VROUNDPD128: + return rewriteValueAMD64_OpAMD64VROUNDPD128(v) + case OpAMD64VROUNDPD256: + return rewriteValueAMD64_OpAMD64VROUNDPD256(v) + case OpAMD64VROUNDPS128: + return rewriteValueAMD64_OpAMD64VROUNDPS128(v) + case OpAMD64VROUNDPS256: + return rewriteValueAMD64_OpAMD64VROUNDPS256(v) + case OpAMD64VRSQRT14PD128: + return rewriteValueAMD64_OpAMD64VRSQRT14PD128(v) + case OpAMD64VRSQRT14PD256: + return rewriteValueAMD64_OpAMD64VRSQRT14PD256(v) + case OpAMD64VRSQRT14PD512: + return rewriteValueAMD64_OpAMD64VRSQRT14PD512(v) + case OpAMD64VRSQRT14PDMasked128: + return rewriteValueAMD64_OpAMD64VRSQRT14PDMasked128(v) + case OpAMD64VRSQRT14PDMasked256: + return rewriteValueAMD64_OpAMD64VRSQRT14PDMasked256(v) + case OpAMD64VRSQRT14PDMasked512: + return rewriteValueAMD64_OpAMD64VRSQRT14PDMasked512(v) + case OpAMD64VRSQRT14PS512: + return rewriteValueAMD64_OpAMD64VRSQRT14PS512(v) + case OpAMD64VRSQRT14PSMasked128: + return rewriteValueAMD64_OpAMD64VRSQRT14PSMasked128(v) + case OpAMD64VRSQRT14PSMasked256: + return rewriteValueAMD64_OpAMD64VRSQRT14PSMasked256(v) + case OpAMD64VRSQRT14PSMasked512: + return rewriteValueAMD64_OpAMD64VRSQRT14PSMasked512(v) + case OpAMD64VRSQRTPS128: + return rewriteValueAMD64_OpAMD64VRSQRTPS128(v) + case OpAMD64VRSQRTPS256: + return rewriteValueAMD64_OpAMD64VRSQRTPS256(v) + case OpAMD64VSCALEFPD128: + return rewriteValueAMD64_OpAMD64VSCALEFPD128(v) + case OpAMD64VSCALEFPD256: + return rewriteValueAMD64_OpAMD64VSCALEFPD256(v) + case OpAMD64VSCALEFPD512: + return rewriteValueAMD64_OpAMD64VSCALEFPD512(v) + case OpAMD64VSCALEFPDMasked128: + return rewriteValueAMD64_OpAMD64VSCALEFPDMasked128(v) + case OpAMD64VSCALEFPDMasked256: + return rewriteValueAMD64_OpAMD64VSCALEFPDMasked256(v) + case OpAMD64VSCALEFPDMasked512: + return rewriteValueAMD64_OpAMD64VSCALEFPDMasked512(v) + case OpAMD64VSCALEFPS128: + return rewriteValueAMD64_OpAMD64VSCALEFPS128(v) + case OpAMD64VSCALEFPS256: + return rewriteValueAMD64_OpAMD64VSCALEFPS256(v) + case OpAMD64VSCALEFPS512: + return rewriteValueAMD64_OpAMD64VSCALEFPS512(v) + case OpAMD64VSCALEFPSMasked128: + return rewriteValueAMD64_OpAMD64VSCALEFPSMasked128(v) + case OpAMD64VSCALEFPSMasked256: + return rewriteValueAMD64_OpAMD64VSCALEFPSMasked256(v) + case OpAMD64VSCALEFPSMasked512: + return rewriteValueAMD64_OpAMD64VSCALEFPSMasked512(v) + case OpAMD64VSHUFPD128: + return rewriteValueAMD64_OpAMD64VSHUFPD128(v) + case OpAMD64VSHUFPD256: + return rewriteValueAMD64_OpAMD64VSHUFPD256(v) + case OpAMD64VSHUFPD512: + return rewriteValueAMD64_OpAMD64VSHUFPD512(v) + case OpAMD64VSHUFPS128: + return rewriteValueAMD64_OpAMD64VSHUFPS128(v) + case OpAMD64VSHUFPS256: + return rewriteValueAMD64_OpAMD64VSHUFPS256(v) + case OpAMD64VSHUFPS512: + return rewriteValueAMD64_OpAMD64VSHUFPS512(v) + case OpAMD64VSQRTPD128: + return rewriteValueAMD64_OpAMD64VSQRTPD128(v) + case OpAMD64VSQRTPD256: + return rewriteValueAMD64_OpAMD64VSQRTPD256(v) + case OpAMD64VSQRTPD512: + return rewriteValueAMD64_OpAMD64VSQRTPD512(v) + case OpAMD64VSQRTPDMasked128: + return rewriteValueAMD64_OpAMD64VSQRTPDMasked128(v) + case OpAMD64VSQRTPDMasked256: + return rewriteValueAMD64_OpAMD64VSQRTPDMasked256(v) + case OpAMD64VSQRTPDMasked512: + return rewriteValueAMD64_OpAMD64VSQRTPDMasked512(v) + case OpAMD64VSQRTPS128: + return rewriteValueAMD64_OpAMD64VSQRTPS128(v) + case OpAMD64VSQRTPS256: + return rewriteValueAMD64_OpAMD64VSQRTPS256(v) + case OpAMD64VSQRTPS512: + return rewriteValueAMD64_OpAMD64VSQRTPS512(v) + case OpAMD64VSQRTPSMasked128: + return rewriteValueAMD64_OpAMD64VSQRTPSMasked128(v) + case OpAMD64VSQRTPSMasked256: + return rewriteValueAMD64_OpAMD64VSQRTPSMasked256(v) + case OpAMD64VSQRTPSMasked512: + return rewriteValueAMD64_OpAMD64VSQRTPSMasked512(v) + case OpAMD64VSUBPD128: + return rewriteValueAMD64_OpAMD64VSUBPD128(v) + case OpAMD64VSUBPD256: + return rewriteValueAMD64_OpAMD64VSUBPD256(v) + case OpAMD64VSUBPD512: + return rewriteValueAMD64_OpAMD64VSUBPD512(v) + case OpAMD64VSUBPDMasked128: + return rewriteValueAMD64_OpAMD64VSUBPDMasked128(v) + case OpAMD64VSUBPDMasked256: + return rewriteValueAMD64_OpAMD64VSUBPDMasked256(v) + case OpAMD64VSUBPDMasked512: + return rewriteValueAMD64_OpAMD64VSUBPDMasked512(v) + case OpAMD64VSUBPS128: + return rewriteValueAMD64_OpAMD64VSUBPS128(v) + case OpAMD64VSUBPS256: + return rewriteValueAMD64_OpAMD64VSUBPS256(v) + case OpAMD64VSUBPS512: + return rewriteValueAMD64_OpAMD64VSUBPS512(v) + case OpAMD64VSUBPSMasked128: + return rewriteValueAMD64_OpAMD64VSUBPSMasked128(v) + case OpAMD64VSUBPSMasked256: + return rewriteValueAMD64_OpAMD64VSUBPSMasked256(v) + case OpAMD64VSUBPSMasked512: + return rewriteValueAMD64_OpAMD64VSUBPSMasked512(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock(v) case OpAMD64XADDQlock: @@ -536,6 +3070,42 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64XORQload(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify(v) + case OpAbsInt16x16: + v.Op = OpAMD64VPABSW256 + return true + case OpAbsInt16x32: + v.Op = OpAMD64VPABSW512 + return true + case OpAbsInt16x8: + v.Op = OpAMD64VPABSW128 + return true + case OpAbsInt32x16: + v.Op = OpAMD64VPABSD512 + return true + case OpAbsInt32x4: + v.Op = OpAMD64VPABSD128 + return true + case OpAbsInt32x8: + v.Op = OpAMD64VPABSD256 + return true + case OpAbsInt64x2: + v.Op = OpAMD64VPABSQ128 + return true + case OpAbsInt64x4: + v.Op = OpAMD64VPABSQ256 + return true + case OpAbsInt64x8: + v.Op = OpAMD64VPABSQ512 + return true + case OpAbsInt8x16: + v.Op = OpAMD64VPABSB128 + return true + case OpAbsInt8x32: + v.Op = OpAMD64VPABSB256 + return true + case OpAbsInt8x64: + v.Op = OpAMD64VPABSB512 + return true case OpAdd16: v.Op = OpAMD64ADDL return true @@ -554,9 +3124,147 @@ func rewriteValueAMD64(v *Value) bool { case OpAdd8: v.Op = OpAMD64ADDL return true + case OpAddFloat32x16: + v.Op = OpAMD64VADDPS512 + return true + case OpAddFloat32x4: + v.Op = OpAMD64VADDPS128 + return true + case OpAddFloat32x8: + v.Op = OpAMD64VADDPS256 + return true + case OpAddFloat64x2: + v.Op = OpAMD64VADDPD128 + return true + case OpAddFloat64x4: + v.Op = OpAMD64VADDPD256 + return true + case OpAddFloat64x8: + v.Op = OpAMD64VADDPD512 + return true + case OpAddInt16x16: + v.Op = OpAMD64VPADDW256 + return true + case OpAddInt16x32: + v.Op = OpAMD64VPADDW512 + return true + case OpAddInt16x8: + v.Op = OpAMD64VPADDW128 + return true + case OpAddInt32x16: + v.Op = OpAMD64VPADDD512 + return true + case OpAddInt32x4: + v.Op = OpAMD64VPADDD128 + return true + case OpAddInt32x8: + v.Op = OpAMD64VPADDD256 + return true + case OpAddInt64x2: + v.Op = OpAMD64VPADDQ128 + return true + case OpAddInt64x4: + v.Op = OpAMD64VPADDQ256 + return true + case OpAddInt64x8: + v.Op = OpAMD64VPADDQ512 + return true + case OpAddInt8x16: + v.Op = OpAMD64VPADDB128 + return true + case OpAddInt8x32: + v.Op = OpAMD64VPADDB256 + return true + case OpAddInt8x64: + v.Op = OpAMD64VPADDB512 + return true + case OpAddOddSubEvenFloat32x4: + v.Op = OpAMD64VADDSUBPS128 + return true + case OpAddOddSubEvenFloat32x8: + v.Op = OpAMD64VADDSUBPS256 + return true + case OpAddOddSubEvenFloat64x2: + v.Op = OpAMD64VADDSUBPD128 + return true + case OpAddOddSubEvenFloat64x4: + v.Op = OpAMD64VADDSUBPD256 + return true case OpAddPtr: v.Op = OpAMD64ADDQ return true + case OpAddSaturatedInt16x16: + v.Op = OpAMD64VPADDSW256 + return true + case OpAddSaturatedInt16x32: + v.Op = OpAMD64VPADDSW512 + return true + case OpAddSaturatedInt16x8: + v.Op = OpAMD64VPADDSW128 + return true + case OpAddSaturatedInt8x16: + v.Op = OpAMD64VPADDSB128 + return true + case OpAddSaturatedInt8x32: + v.Op = OpAMD64VPADDSB256 + return true + case OpAddSaturatedInt8x64: + v.Op = OpAMD64VPADDSB512 + return true + case OpAddSaturatedUint16x16: + v.Op = OpAMD64VPADDUSW256 + return true + case OpAddSaturatedUint16x32: + v.Op = OpAMD64VPADDUSW512 + return true + case OpAddSaturatedUint16x8: + v.Op = OpAMD64VPADDUSW128 + return true + case OpAddSaturatedUint8x16: + v.Op = OpAMD64VPADDUSB128 + return true + case OpAddSaturatedUint8x32: + v.Op = OpAMD64VPADDUSB256 + return true + case OpAddSaturatedUint8x64: + v.Op = OpAMD64VPADDUSB512 + return true + case OpAddUint16x16: + v.Op = OpAMD64VPADDW256 + return true + case OpAddUint16x32: + v.Op = OpAMD64VPADDW512 + return true + case OpAddUint16x8: + v.Op = OpAMD64VPADDW128 + return true + case OpAddUint32x16: + v.Op = OpAMD64VPADDD512 + return true + case OpAddUint32x4: + v.Op = OpAMD64VPADDD128 + return true + case OpAddUint32x8: + v.Op = OpAMD64VPADDD256 + return true + case OpAddUint64x2: + v.Op = OpAMD64VPADDQ128 + return true + case OpAddUint64x4: + v.Op = OpAMD64VPADDQ256 + return true + case OpAddUint64x8: + v.Op = OpAMD64VPADDQ512 + return true + case OpAddUint8x16: + v.Op = OpAMD64VPADDB128 + return true + case OpAddUint8x32: + v.Op = OpAMD64VPADDB256 + return true + case OpAddUint8x64: + v.Op = OpAMD64VPADDB512 + return true case OpAddr: return rewriteValueAMD64_OpAddr(v) case OpAnd16: @@ -574,6 +3282,150 @@ func rewriteValueAMD64(v *Value) bool { case OpAndB: v.Op = OpAMD64ANDL return true + case OpAndInt16x16: + v.Op = OpAMD64VPAND256 + return true + case OpAndInt16x32: + v.Op = OpAMD64VPANDD512 + return true + case OpAndInt16x8: + v.Op = OpAMD64VPAND128 + return true + case OpAndInt32x16: + v.Op = OpAMD64VPANDD512 + return true + case OpAndInt32x4: + v.Op = OpAMD64VPAND128 + return true + case OpAndInt32x8: + v.Op = OpAMD64VPAND256 + return true + case OpAndInt64x2: + v.Op = OpAMD64VPAND128 + return true + case OpAndInt64x4: + v.Op = OpAMD64VPAND256 + return true + case OpAndInt64x8: + v.Op = OpAMD64VPANDQ512 + return true + case OpAndInt8x16: + v.Op = OpAMD64VPAND128 + return true + case OpAndInt8x32: + v.Op = OpAMD64VPAND256 + return true + case OpAndInt8x64: + v.Op = OpAMD64VPANDD512 + return true + case OpAndNotInt16x16: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotInt16x32: + v.Op = OpAMD64VPANDND512 + return true + case OpAndNotInt16x8: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotInt32x16: + v.Op = OpAMD64VPANDND512 + return true + case OpAndNotInt32x4: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotInt32x8: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotInt64x2: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotInt64x4: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotInt64x8: + v.Op = OpAMD64VPANDNQ512 + return true + case OpAndNotInt8x16: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotInt8x32: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotInt8x64: + v.Op = OpAMD64VPANDND512 + return true + case OpAndNotUint16x16: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotUint16x32: + v.Op = OpAMD64VPANDND512 + return true + case OpAndNotUint16x8: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotUint32x16: + v.Op = OpAMD64VPANDND512 + return true + case OpAndNotUint32x4: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotUint32x8: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotUint64x2: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotUint64x4: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotUint64x8: + v.Op = OpAMD64VPANDNQ512 + return true + case OpAndNotUint8x16: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotUint8x32: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotUint8x64: + v.Op = OpAMD64VPANDND512 + return true + case OpAndUint16x16: + v.Op = OpAMD64VPAND256 + return true + case OpAndUint16x32: + v.Op = OpAMD64VPANDD512 + return true + case OpAndUint16x8: + v.Op = OpAMD64VPAND128 + return true + case OpAndUint32x16: + v.Op = OpAMD64VPANDD512 + return true + case OpAndUint32x4: + v.Op = OpAMD64VPAND128 + return true + case OpAndUint32x8: + v.Op = OpAMD64VPAND256 + return true + case OpAndUint64x2: + v.Op = OpAMD64VPAND128 + return true + case OpAndUint64x4: + v.Op = OpAMD64VPAND256 + return true + case OpAndUint64x8: + v.Op = OpAMD64VPANDQ512 + return true + case OpAndUint8x16: + v.Op = OpAMD64VPAND128 + return true + case OpAndUint8x32: + v.Op = OpAMD64VPAND256 + return true + case OpAndUint8x64: + v.Op = OpAMD64VPANDD512 + return true case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32(v) case OpAtomicAdd64: @@ -620,6 +3472,24 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAtomicStore8(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB(v) + case OpAverageUint16x16: + v.Op = OpAMD64VPAVGW256 + return true + case OpAverageUint16x32: + v.Op = OpAMD64VPAVGW512 + return true + case OpAverageUint16x8: + v.Op = OpAMD64VPAVGW128 + return true + case OpAverageUint8x16: + v.Op = OpAMD64VPAVGB128 + return true + case OpAverageUint8x32: + v.Op = OpAMD64VPAVGB256 + return true + case OpAverageUint8x64: + v.Op = OpAMD64VPAVGB512 + return true case OpAvg64u: v.Op = OpAMD64AVGQU return true @@ -641,6 +3511,38 @@ func rewriteValueAMD64(v *Value) bool { return true case OpCeil: return rewriteValueAMD64_OpCeil(v) + case OpCeilFloat32x4: + return rewriteValueAMD64_OpCeilFloat32x4(v) + case OpCeilFloat32x8: + return rewriteValueAMD64_OpCeilFloat32x8(v) + case OpCeilFloat64x2: + return rewriteValueAMD64_OpCeilFloat64x2(v) + case OpCeilFloat64x4: + return rewriteValueAMD64_OpCeilFloat64x4(v) + case OpCeilScaledFloat32x16: + return rewriteValueAMD64_OpCeilScaledFloat32x16(v) + case OpCeilScaledFloat32x4: + return rewriteValueAMD64_OpCeilScaledFloat32x4(v) + case OpCeilScaledFloat32x8: + return rewriteValueAMD64_OpCeilScaledFloat32x8(v) + case OpCeilScaledFloat64x2: + return rewriteValueAMD64_OpCeilScaledFloat64x2(v) + case OpCeilScaledFloat64x4: + return rewriteValueAMD64_OpCeilScaledFloat64x4(v) + case OpCeilScaledFloat64x8: + return rewriteValueAMD64_OpCeilScaledFloat64x8(v) + case OpCeilScaledResidueFloat32x16: + return rewriteValueAMD64_OpCeilScaledResidueFloat32x16(v) + case OpCeilScaledResidueFloat32x4: + return rewriteValueAMD64_OpCeilScaledResidueFloat32x4(v) + case OpCeilScaledResidueFloat32x8: + return rewriteValueAMD64_OpCeilScaledResidueFloat32x8(v) + case OpCeilScaledResidueFloat64x2: + return rewriteValueAMD64_OpCeilScaledResidueFloat64x2(v) + case OpCeilScaledResidueFloat64x4: + return rewriteValueAMD64_OpCeilScaledResidueFloat64x4(v) + case OpCeilScaledResidueFloat64x8: + return rewriteValueAMD64_OpCeilScaledResidueFloat64x8(v) case OpClosureCall: v.Op = OpAMD64CALLclosure return true @@ -656,6 +3558,279 @@ func rewriteValueAMD64(v *Value) bool { case OpCom8: v.Op = OpAMD64NOTL return true + case OpCompressFloat32x16: + return rewriteValueAMD64_OpCompressFloat32x16(v) + case OpCompressFloat32x4: + return rewriteValueAMD64_OpCompressFloat32x4(v) + case OpCompressFloat32x8: + return rewriteValueAMD64_OpCompressFloat32x8(v) + case OpCompressFloat64x2: + return rewriteValueAMD64_OpCompressFloat64x2(v) + case OpCompressFloat64x4: + return rewriteValueAMD64_OpCompressFloat64x4(v) + case OpCompressFloat64x8: + return rewriteValueAMD64_OpCompressFloat64x8(v) + case OpCompressInt16x16: + return rewriteValueAMD64_OpCompressInt16x16(v) + case OpCompressInt16x32: + return rewriteValueAMD64_OpCompressInt16x32(v) + case OpCompressInt16x8: + return rewriteValueAMD64_OpCompressInt16x8(v) + case OpCompressInt32x16: + return rewriteValueAMD64_OpCompressInt32x16(v) + case OpCompressInt32x4: + return rewriteValueAMD64_OpCompressInt32x4(v) + case OpCompressInt32x8: + return rewriteValueAMD64_OpCompressInt32x8(v) + case OpCompressInt64x2: + return rewriteValueAMD64_OpCompressInt64x2(v) + case OpCompressInt64x4: + return rewriteValueAMD64_OpCompressInt64x4(v) + case OpCompressInt64x8: + return rewriteValueAMD64_OpCompressInt64x8(v) + case OpCompressInt8x16: + return rewriteValueAMD64_OpCompressInt8x16(v) + case OpCompressInt8x32: + return rewriteValueAMD64_OpCompressInt8x32(v) + case OpCompressInt8x64: + return rewriteValueAMD64_OpCompressInt8x64(v) + case OpCompressUint16x16: + return rewriteValueAMD64_OpCompressUint16x16(v) + case OpCompressUint16x32: + return rewriteValueAMD64_OpCompressUint16x32(v) + case OpCompressUint16x8: + return rewriteValueAMD64_OpCompressUint16x8(v) + case OpCompressUint32x16: + return rewriteValueAMD64_OpCompressUint32x16(v) + case OpCompressUint32x4: + return rewriteValueAMD64_OpCompressUint32x4(v) + case OpCompressUint32x8: + return rewriteValueAMD64_OpCompressUint32x8(v) + case OpCompressUint64x2: + return rewriteValueAMD64_OpCompressUint64x2(v) + case OpCompressUint64x4: + return rewriteValueAMD64_OpCompressUint64x4(v) + case OpCompressUint64x8: + return rewriteValueAMD64_OpCompressUint64x8(v) + case OpCompressUint8x16: + return rewriteValueAMD64_OpCompressUint8x16(v) + case OpCompressUint8x32: + return rewriteValueAMD64_OpCompressUint8x32(v) + case OpCompressUint8x64: + return rewriteValueAMD64_OpCompressUint8x64(v) + case OpConcatAddPairsFloat32x4: + v.Op = OpAMD64VHADDPS128 + return true + case OpConcatAddPairsFloat64x2: + v.Op = OpAMD64VHADDPD128 + return true + case OpConcatAddPairsGroupedFloat32x8: + v.Op = OpAMD64VHADDPS256 + return true + case OpConcatAddPairsGroupedFloat64x4: + v.Op = OpAMD64VHADDPD256 + return true + case OpConcatAddPairsGroupedInt16x16: + v.Op = OpAMD64VPHADDW256 + return true + case OpConcatAddPairsGroupedInt32x8: + v.Op = OpAMD64VPHADDD256 + return true + case OpConcatAddPairsGroupedUint16x16: + v.Op = OpAMD64VPHADDW256 + return true + case OpConcatAddPairsGroupedUint32x8: + v.Op = OpAMD64VPHADDD256 + return true + case OpConcatAddPairsInt16x8: + v.Op = OpAMD64VPHADDW128 + return true + case OpConcatAddPairsInt32x4: + v.Op = OpAMD64VPHADDD128 + return true + case OpConcatAddPairsSaturatedGroupedInt16x16: + v.Op = OpAMD64VPHADDSW256 + return true + case OpConcatAddPairsSaturatedInt16x8: + v.Op = OpAMD64VPHADDSW128 + return true + case OpConcatAddPairsUint16x8: + v.Op = OpAMD64VPHADDW128 + return true + case OpConcatAddPairsUint32x4: + v.Op = OpAMD64VPHADDD128 + return true + case OpConcatPermute128ScalarsFloat32x8: + v.Op = OpAMD64VPERM2F128256 + return true + case OpConcatPermute128ScalarsFloat64x4: + v.Op = OpAMD64VPERM2F128256 + return true + case OpConcatPermute128ScalarsInt16x16: + v.Op = OpAMD64VPERM2I128256 + return true + case OpConcatPermute128ScalarsInt32x8: + v.Op = OpAMD64VPERM2I128256 + return true + case OpConcatPermute128ScalarsInt64x4: + v.Op = OpAMD64VPERM2I128256 + return true + case OpConcatPermute128ScalarsInt8x32: + v.Op = OpAMD64VPERM2I128256 + return true + case OpConcatPermute128ScalarsUint16x16: + v.Op = OpAMD64VPERM2I128256 + return true + case OpConcatPermute128ScalarsUint32x8: + v.Op = OpAMD64VPERM2I128256 + return true + case OpConcatPermute128ScalarsUint64x4: + v.Op = OpAMD64VPERM2I128256 + return true + case OpConcatPermute128ScalarsUint8x32: + v.Op = OpAMD64VPERM2I128256 + return true + case OpConcatPermuteFloat32x16: + v.Op = OpAMD64VPERMI2PS512 + return true + case OpConcatPermuteFloat32x4: + v.Op = OpAMD64VPERMI2PS128 + return true + case OpConcatPermuteFloat32x8: + v.Op = OpAMD64VPERMI2PS256 + return true + case OpConcatPermuteFloat64x2: + v.Op = OpAMD64VPERMI2PD128 + return true + case OpConcatPermuteFloat64x4: + v.Op = OpAMD64VPERMI2PD256 + return true + case OpConcatPermuteFloat64x8: + v.Op = OpAMD64VPERMI2PD512 + return true + case OpConcatPermuteInt16x16: + v.Op = OpAMD64VPERMI2W256 + return true + case OpConcatPermuteInt16x32: + v.Op = OpAMD64VPERMI2W512 + return true + case OpConcatPermuteInt16x8: + v.Op = OpAMD64VPERMI2W128 + return true + case OpConcatPermuteInt32x16: + v.Op = OpAMD64VPERMI2D512 + return true + case OpConcatPermuteInt32x4: + v.Op = OpAMD64VPERMI2D128 + return true + case OpConcatPermuteInt32x8: + v.Op = OpAMD64VPERMI2D256 + return true + case OpConcatPermuteInt64x2: + v.Op = OpAMD64VPERMI2Q128 + return true + case OpConcatPermuteInt64x4: + v.Op = OpAMD64VPERMI2Q256 + return true + case OpConcatPermuteInt64x8: + v.Op = OpAMD64VPERMI2Q512 + return true + case OpConcatPermuteInt8x16: + v.Op = OpAMD64VPERMI2B128 + return true + case OpConcatPermuteInt8x32: + v.Op = OpAMD64VPERMI2B256 + return true + case OpConcatPermuteInt8x64: + v.Op = OpAMD64VPERMI2B512 + return true + case OpConcatPermuteUint16x16: + v.Op = OpAMD64VPERMI2W256 + return true + case OpConcatPermuteUint16x32: + v.Op = OpAMD64VPERMI2W512 + return true + case OpConcatPermuteUint16x8: + v.Op = OpAMD64VPERMI2W128 + return true + case OpConcatPermuteUint32x16: + v.Op = OpAMD64VPERMI2D512 + return true + case OpConcatPermuteUint32x4: + v.Op = OpAMD64VPERMI2D128 + return true + case OpConcatPermuteUint32x8: + v.Op = OpAMD64VPERMI2D256 + return true + case OpConcatPermuteUint64x2: + v.Op = OpAMD64VPERMI2Q128 + return true + case OpConcatPermuteUint64x4: + v.Op = OpAMD64VPERMI2Q256 + return true + case OpConcatPermuteUint64x8: + v.Op = OpAMD64VPERMI2Q512 + return true + case OpConcatPermuteUint8x16: + v.Op = OpAMD64VPERMI2B128 + return true + case OpConcatPermuteUint8x32: + v.Op = OpAMD64VPERMI2B256 + return true + case OpConcatPermuteUint8x64: + v.Op = OpAMD64VPERMI2B512 + return true + case OpConcatShiftBytesRightGroupedUint8x32: + v.Op = OpAMD64VPALIGNR256 + return true + case OpConcatShiftBytesRightGroupedUint8x64: + v.Op = OpAMD64VPALIGNR512 + return true + case OpConcatShiftBytesRightUint8x16: + v.Op = OpAMD64VPALIGNR128 + return true + case OpConcatSubPairsFloat32x4: + v.Op = OpAMD64VHSUBPS128 + return true + case OpConcatSubPairsFloat64x2: + v.Op = OpAMD64VHSUBPD128 + return true + case OpConcatSubPairsGroupedFloat32x8: + v.Op = OpAMD64VHSUBPS256 + return true + case OpConcatSubPairsGroupedFloat64x4: + v.Op = OpAMD64VHSUBPD256 + return true + case OpConcatSubPairsGroupedInt16x16: + v.Op = OpAMD64VPHSUBW256 + return true + case OpConcatSubPairsGroupedInt32x8: + v.Op = OpAMD64VPHSUBD256 + return true + case OpConcatSubPairsGroupedUint16x16: + v.Op = OpAMD64VPHSUBW256 + return true + case OpConcatSubPairsGroupedUint32x8: + v.Op = OpAMD64VPHSUBD256 + return true + case OpConcatSubPairsInt16x8: + v.Op = OpAMD64VPHSUBW128 + return true + case OpConcatSubPairsInt32x4: + v.Op = OpAMD64VPHSUBD128 + return true + case OpConcatSubPairsSaturatedGroupedInt16x16: + v.Op = OpAMD64VPHSUBSW256 + return true + case OpConcatSubPairsSaturatedInt16x8: + v.Op = OpAMD64VPHSUBSW128 + return true + case OpConcatSubPairsUint16x8: + v.Op = OpAMD64VPHSUBW128 + return true + case OpConcatSubPairsUint32x4: + v.Op = OpAMD64VPHSUBD128 + return true case OpCondSelect: return rewriteValueAMD64_OpCondSelect(v) case OpConst16: @@ -678,6 +3853,153 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpConstBool(v) case OpConstNil: return rewriteValueAMD64_OpConstNil(v) + case OpConvertToFloat32Float64x2: + v.Op = OpAMD64VCVTPD2PSX128 + return true + case OpConvertToFloat32Float64x4: + v.Op = OpAMD64VCVTPD2PSY128 + return true + case OpConvertToFloat32Float64x8: + v.Op = OpAMD64VCVTPD2PS256 + return true + case OpConvertToFloat32Int32x16: + v.Op = OpAMD64VCVTDQ2PS512 + return true + case OpConvertToFloat32Int32x4: + v.Op = OpAMD64VCVTDQ2PS128 + return true + case OpConvertToFloat32Int32x8: + v.Op = OpAMD64VCVTDQ2PS256 + return true + case OpConvertToFloat32Int64x2: + v.Op = OpAMD64VCVTQQ2PSX128 + return true + case OpConvertToFloat32Int64x4: + v.Op = OpAMD64VCVTQQ2PSY128 + return true + case OpConvertToFloat32Int64x8: + v.Op = OpAMD64VCVTQQ2PS256 + return true + case OpConvertToFloat32Uint32x16: + v.Op = OpAMD64VCVTUDQ2PS512 + return true + case OpConvertToFloat32Uint32x4: + v.Op = OpAMD64VCVTUDQ2PS128 + return true + case OpConvertToFloat32Uint32x8: + v.Op = OpAMD64VCVTUDQ2PS256 + return true + case OpConvertToFloat32Uint64x2: + v.Op = OpAMD64VCVTUQQ2PSX128 + return true + case OpConvertToFloat32Uint64x4: + v.Op = OpAMD64VCVTUQQ2PSY128 + return true + case OpConvertToFloat32Uint64x8: + v.Op = OpAMD64VCVTUQQ2PS256 + return true + case OpConvertToFloat64Float32x4: + v.Op = OpAMD64VCVTPS2PD256 + return true + case OpConvertToFloat64Float32x8: + v.Op = OpAMD64VCVTPS2PD512 + return true + case OpConvertToFloat64Int32x4: + v.Op = OpAMD64VCVTDQ2PD256 + return true + case OpConvertToFloat64Int32x8: + v.Op = OpAMD64VCVTDQ2PD512 + return true + case OpConvertToFloat64Int64x2: + v.Op = OpAMD64VCVTQQ2PD128 + return true + case OpConvertToFloat64Int64x4: + v.Op = OpAMD64VCVTQQ2PD256 + return true + case OpConvertToFloat64Int64x8: + v.Op = OpAMD64VCVTQQ2PD512 + return true + case OpConvertToFloat64Uint32x4: + v.Op = OpAMD64VCVTUDQ2PD256 + return true + case OpConvertToFloat64Uint32x8: + v.Op = OpAMD64VCVTUDQ2PD512 + return true + case OpConvertToFloat64Uint64x2: + v.Op = OpAMD64VCVTUQQ2PD128 + return true + case OpConvertToFloat64Uint64x4: + v.Op = OpAMD64VCVTUQQ2PD256 + return true + case OpConvertToFloat64Uint64x8: + v.Op = OpAMD64VCVTUQQ2PD512 + return true + case OpConvertToInt32Float32x16: + v.Op = OpAMD64VCVTTPS2DQ512 + return true + case OpConvertToInt32Float32x4: + v.Op = OpAMD64VCVTTPS2DQ128 + return true + case OpConvertToInt32Float32x8: + v.Op = OpAMD64VCVTTPS2DQ256 + return true + case OpConvertToInt32Float64x2: + v.Op = OpAMD64VCVTTPD2DQX128 + return true + case OpConvertToInt32Float64x4: + v.Op = OpAMD64VCVTTPD2DQY128 + return true + case OpConvertToInt32Float64x8: + v.Op = OpAMD64VCVTTPD2DQ256 + return true + case OpConvertToInt64Float32x4: + v.Op = OpAMD64VCVTTPS2QQ256 + return true + case OpConvertToInt64Float32x8: + v.Op = OpAMD64VCVTTPS2QQ512 + return true + case OpConvertToInt64Float64x2: + v.Op = OpAMD64VCVTTPD2QQ128 + return true + case OpConvertToInt64Float64x4: + v.Op = OpAMD64VCVTTPD2QQ256 + return true + case OpConvertToInt64Float64x8: + v.Op = OpAMD64VCVTTPD2QQ512 + return true + case OpConvertToUint32Float32x16: + v.Op = OpAMD64VCVTTPS2UDQ512 + return true + case OpConvertToUint32Float32x4: + v.Op = OpAMD64VCVTTPS2UDQ128 + return true + case OpConvertToUint32Float32x8: + v.Op = OpAMD64VCVTTPS2UDQ256 + return true + case OpConvertToUint32Float64x2: + v.Op = OpAMD64VCVTTPD2UDQX128 + return true + case OpConvertToUint32Float64x4: + v.Op = OpAMD64VCVTTPD2UDQY128 + return true + case OpConvertToUint32Float64x8: + v.Op = OpAMD64VCVTTPD2UDQ256 + return true + case OpConvertToUint64Float32x4: + v.Op = OpAMD64VCVTTPS2UQQ256 + return true + case OpConvertToUint64Float32x8: + v.Op = OpAMD64VCVTTPS2UQQ512 + return true + case OpConvertToUint64Float64x2: + v.Op = OpAMD64VCVTTPD2UQQ128 + return true + case OpConvertToUint64Float64x4: + v.Op = OpAMD64VCVTTPD2UQQ256 + return true + case OpConvertToUint64Float64x8: + v.Op = OpAMD64VCVTTPD2UQQ512 + return true case OpCtz16: return rewriteValueAMD64_OpCtz16(v) case OpCtz16NonZero: @@ -694,6 +4016,12 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpCtz8(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero(v) + case OpCvt16toMask16x16: + return rewriteValueAMD64_OpCvt16toMask16x16(v) + case OpCvt16toMask32x16: + return rewriteValueAMD64_OpCvt16toMask32x16(v) + case OpCvt16toMask8x16: + return rewriteValueAMD64_OpCvt16toMask8x16(v) case OpCvt32Fto32: return rewriteValueAMD64_OpCvt32Fto32(v) case OpCvt32Fto64: @@ -707,6 +4035,10 @@ func rewriteValueAMD64(v *Value) bool { case OpCvt32to64F: v.Op = OpAMD64CVTSL2SD return true + case OpCvt32toMask16x32: + return rewriteValueAMD64_OpCvt32toMask16x32(v) + case OpCvt32toMask8x32: + return rewriteValueAMD64_OpCvt32toMask8x32(v) case OpCvt64Fto32: return rewriteValueAMD64_OpCvt64Fto32(v) case OpCvt64Fto32F: @@ -720,9 +4052,53 @@ func rewriteValueAMD64(v *Value) bool { case OpCvt64to64F: v.Op = OpAMD64CVTSQ2SD return true + case OpCvt64toMask8x64: + return rewriteValueAMD64_OpCvt64toMask8x64(v) + case OpCvt8toMask16x8: + return rewriteValueAMD64_OpCvt8toMask16x8(v) + case OpCvt8toMask32x4: + return rewriteValueAMD64_OpCvt8toMask32x4(v) + case OpCvt8toMask32x8: + return rewriteValueAMD64_OpCvt8toMask32x8(v) + case OpCvt8toMask64x2: + return rewriteValueAMD64_OpCvt8toMask64x2(v) + case OpCvt8toMask64x4: + return rewriteValueAMD64_OpCvt8toMask64x4(v) + case OpCvt8toMask64x8: + return rewriteValueAMD64_OpCvt8toMask64x8(v) case OpCvtBoolToUint8: v.Op = OpCopy return true + case OpCvtMask16x16to16: + return rewriteValueAMD64_OpCvtMask16x16to16(v) + case OpCvtMask16x32to32: + return rewriteValueAMD64_OpCvtMask16x32to32(v) + case OpCvtMask16x8to8: + return rewriteValueAMD64_OpCvtMask16x8to8(v) + case OpCvtMask32x16to16: + return rewriteValueAMD64_OpCvtMask32x16to16(v) + case OpCvtMask32x4to8: + v.Op = OpAMD64VMOVMSKPS128 + return true + case OpCvtMask32x8to8: + v.Op = OpAMD64VMOVMSKPS256 + return true + case OpCvtMask64x2to8: + v.Op = OpAMD64VMOVMSKPD128 + return true + case OpCvtMask64x4to8: + v.Op = OpAMD64VMOVMSKPD256 + return true + case OpCvtMask64x8to8: + return rewriteValueAMD64_OpCvtMask64x8to8(v) + case OpCvtMask8x16to16: + v.Op = OpAMD64VPMOVMSKB128 + return true + case OpCvtMask8x32to32: + v.Op = OpAMD64VPMOVMSKB256 + return true + case OpCvtMask8x64to64: + return rewriteValueAMD64_OpCvtMask8x64to64(v) case OpDiv128u: v.Op = OpAMD64DIVQU2 return true @@ -748,6 +4124,42 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpDiv8(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u(v) + case OpDivFloat32x16: + v.Op = OpAMD64VDIVPS512 + return true + case OpDivFloat32x4: + v.Op = OpAMD64VDIVPS128 + return true + case OpDivFloat32x8: + v.Op = OpAMD64VDIVPS256 + return true + case OpDivFloat64x2: + v.Op = OpAMD64VDIVPD128 + return true + case OpDivFloat64x4: + v.Op = OpAMD64VDIVPD256 + return true + case OpDivFloat64x8: + v.Op = OpAMD64VDIVPD512 + return true + case OpDotProductPairsInt16x16: + v.Op = OpAMD64VPMADDWD256 + return true + case OpDotProductPairsInt16x32: + v.Op = OpAMD64VPMADDWD512 + return true + case OpDotProductPairsInt16x8: + v.Op = OpAMD64VPMADDWD128 + return true + case OpDotProductPairsSaturatedUint8x16: + v.Op = OpAMD64VPMADDUBSW128 + return true + case OpDotProductPairsSaturatedUint8x32: + v.Op = OpAMD64VPMADDUBSW256 + return true + case OpDotProductPairsSaturatedUint8x64: + v.Op = OpAMD64VPMADDUBSW512 + return true case OpEq16: return rewriteValueAMD64_OpEq16(v) case OpEq32: @@ -764,10 +4176,313 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpEqB(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr(v) + case OpEqualFloat32x16: + return rewriteValueAMD64_OpEqualFloat32x16(v) + case OpEqualFloat32x4: + return rewriteValueAMD64_OpEqualFloat32x4(v) + case OpEqualFloat32x8: + return rewriteValueAMD64_OpEqualFloat32x8(v) + case OpEqualFloat64x2: + return rewriteValueAMD64_OpEqualFloat64x2(v) + case OpEqualFloat64x4: + return rewriteValueAMD64_OpEqualFloat64x4(v) + case OpEqualFloat64x8: + return rewriteValueAMD64_OpEqualFloat64x8(v) + case OpEqualInt16x16: + v.Op = OpAMD64VPCMPEQW256 + return true + case OpEqualInt16x32: + return rewriteValueAMD64_OpEqualInt16x32(v) + case OpEqualInt16x8: + v.Op = OpAMD64VPCMPEQW128 + return true + case OpEqualInt32x16: + return rewriteValueAMD64_OpEqualInt32x16(v) + case OpEqualInt32x4: + v.Op = OpAMD64VPCMPEQD128 + return true + case OpEqualInt32x8: + v.Op = OpAMD64VPCMPEQD256 + return true + case OpEqualInt64x2: + v.Op = OpAMD64VPCMPEQQ128 + return true + case OpEqualInt64x4: + v.Op = OpAMD64VPCMPEQQ256 + return true + case OpEqualInt64x8: + return rewriteValueAMD64_OpEqualInt64x8(v) + case OpEqualInt8x16: + v.Op = OpAMD64VPCMPEQB128 + return true + case OpEqualInt8x32: + v.Op = OpAMD64VPCMPEQB256 + return true + case OpEqualInt8x64: + return rewriteValueAMD64_OpEqualInt8x64(v) + case OpEqualUint16x16: + v.Op = OpAMD64VPCMPEQW256 + return true + case OpEqualUint16x32: + return rewriteValueAMD64_OpEqualUint16x32(v) + case OpEqualUint16x8: + v.Op = OpAMD64VPCMPEQW128 + return true + case OpEqualUint32x16: + return rewriteValueAMD64_OpEqualUint32x16(v) + case OpEqualUint32x4: + v.Op = OpAMD64VPCMPEQD128 + return true + case OpEqualUint32x8: + v.Op = OpAMD64VPCMPEQD256 + return true + case OpEqualUint64x2: + v.Op = OpAMD64VPCMPEQQ128 + return true + case OpEqualUint64x4: + v.Op = OpAMD64VPCMPEQQ256 + return true + case OpEqualUint64x8: + return rewriteValueAMD64_OpEqualUint64x8(v) + case OpEqualUint8x16: + v.Op = OpAMD64VPCMPEQB128 + return true + case OpEqualUint8x32: + v.Op = OpAMD64VPCMPEQB256 + return true + case OpEqualUint8x64: + return rewriteValueAMD64_OpEqualUint8x64(v) + case OpExpandFloat32x16: + return rewriteValueAMD64_OpExpandFloat32x16(v) + case OpExpandFloat32x4: + return rewriteValueAMD64_OpExpandFloat32x4(v) + case OpExpandFloat32x8: + return rewriteValueAMD64_OpExpandFloat32x8(v) + case OpExpandFloat64x2: + return rewriteValueAMD64_OpExpandFloat64x2(v) + case OpExpandFloat64x4: + return rewriteValueAMD64_OpExpandFloat64x4(v) + case OpExpandFloat64x8: + return rewriteValueAMD64_OpExpandFloat64x8(v) + case OpExpandInt16x16: + return rewriteValueAMD64_OpExpandInt16x16(v) + case OpExpandInt16x32: + return rewriteValueAMD64_OpExpandInt16x32(v) + case OpExpandInt16x8: + return rewriteValueAMD64_OpExpandInt16x8(v) + case OpExpandInt32x16: + return rewriteValueAMD64_OpExpandInt32x16(v) + case OpExpandInt32x4: + return rewriteValueAMD64_OpExpandInt32x4(v) + case OpExpandInt32x8: + return rewriteValueAMD64_OpExpandInt32x8(v) + case OpExpandInt64x2: + return rewriteValueAMD64_OpExpandInt64x2(v) + case OpExpandInt64x4: + return rewriteValueAMD64_OpExpandInt64x4(v) + case OpExpandInt64x8: + return rewriteValueAMD64_OpExpandInt64x8(v) + case OpExpandInt8x16: + return rewriteValueAMD64_OpExpandInt8x16(v) + case OpExpandInt8x32: + return rewriteValueAMD64_OpExpandInt8x32(v) + case OpExpandInt8x64: + return rewriteValueAMD64_OpExpandInt8x64(v) + case OpExpandUint16x16: + return rewriteValueAMD64_OpExpandUint16x16(v) + case OpExpandUint16x32: + return rewriteValueAMD64_OpExpandUint16x32(v) + case OpExpandUint16x8: + return rewriteValueAMD64_OpExpandUint16x8(v) + case OpExpandUint32x16: + return rewriteValueAMD64_OpExpandUint32x16(v) + case OpExpandUint32x4: + return rewriteValueAMD64_OpExpandUint32x4(v) + case OpExpandUint32x8: + return rewriteValueAMD64_OpExpandUint32x8(v) + case OpExpandUint64x2: + return rewriteValueAMD64_OpExpandUint64x2(v) + case OpExpandUint64x4: + return rewriteValueAMD64_OpExpandUint64x4(v) + case OpExpandUint64x8: + return rewriteValueAMD64_OpExpandUint64x8(v) + case OpExpandUint8x16: + return rewriteValueAMD64_OpExpandUint8x16(v) + case OpExpandUint8x32: + return rewriteValueAMD64_OpExpandUint8x32(v) + case OpExpandUint8x64: + return rewriteValueAMD64_OpExpandUint8x64(v) + case OpExtendLo2ToInt64Int16x8: + v.Op = OpAMD64VPMOVSXWQ128 + return true + case OpExtendLo2ToInt64Int32x4: + v.Op = OpAMD64VPMOVSXDQ128 + return true + case OpExtendLo2ToInt64Int8x16: + v.Op = OpAMD64VPMOVSXBQ128 + return true + case OpExtendLo2ToUint64Uint16x8: + v.Op = OpAMD64VPMOVZXWQ128 + return true + case OpExtendLo2ToUint64Uint32x4: + v.Op = OpAMD64VPMOVZXDQ128 + return true + case OpExtendLo2ToUint64Uint8x16: + v.Op = OpAMD64VPMOVZXBQ128 + return true + case OpExtendLo4ToInt32Int16x8: + v.Op = OpAMD64VPMOVSXWD128 + return true + case OpExtendLo4ToInt32Int8x16: + v.Op = OpAMD64VPMOVSXBD128 + return true + case OpExtendLo4ToInt64Int16x8: + v.Op = OpAMD64VPMOVSXWQ256 + return true + case OpExtendLo4ToInt64Int8x16: + v.Op = OpAMD64VPMOVSXBQ256 + return true + case OpExtendLo4ToUint32Uint16x8: + v.Op = OpAMD64VPMOVZXWD128 + return true + case OpExtendLo4ToUint32Uint8x16: + v.Op = OpAMD64VPMOVZXBD128 + return true + case OpExtendLo4ToUint64Uint16x8: + v.Op = OpAMD64VPMOVZXWQ256 + return true + case OpExtendLo4ToUint64Uint8x16: + v.Op = OpAMD64VPMOVZXBQ256 + return true + case OpExtendLo8ToInt16Int8x16: + v.Op = OpAMD64VPMOVSXBW128 + return true + case OpExtendLo8ToInt32Int8x16: + v.Op = OpAMD64VPMOVSXBD256 + return true + case OpExtendLo8ToInt64Int8x16: + v.Op = OpAMD64VPMOVSXBQ512 + return true + case OpExtendLo8ToUint16Uint8x16: + v.Op = OpAMD64VPMOVZXBW128 + return true + case OpExtendLo8ToUint32Uint8x16: + v.Op = OpAMD64VPMOVZXBD256 + return true + case OpExtendLo8ToUint64Uint8x16: + v.Op = OpAMD64VPMOVZXBQ512 + return true + case OpExtendToInt16Int8x16: + v.Op = OpAMD64VPMOVSXBW256 + return true + case OpExtendToInt16Int8x32: + v.Op = OpAMD64VPMOVSXBW512 + return true + case OpExtendToInt32Int16x16: + v.Op = OpAMD64VPMOVSXWD512 + return true + case OpExtendToInt32Int16x8: + v.Op = OpAMD64VPMOVSXWD256 + return true + case OpExtendToInt32Int8x16: + v.Op = OpAMD64VPMOVSXBD512 + return true + case OpExtendToInt64Int16x8: + v.Op = OpAMD64VPMOVSXWQ512 + return true + case OpExtendToInt64Int32x4: + v.Op = OpAMD64VPMOVSXDQ256 + return true + case OpExtendToInt64Int32x8: + v.Op = OpAMD64VPMOVSXDQ512 + return true + case OpExtendToUint16Uint8x16: + v.Op = OpAMD64VPMOVZXBW256 + return true + case OpExtendToUint16Uint8x32: + v.Op = OpAMD64VPMOVZXBW512 + return true + case OpExtendToUint32Uint16x16: + v.Op = OpAMD64VPMOVZXWD512 + return true + case OpExtendToUint32Uint16x8: + v.Op = OpAMD64VPMOVZXWD256 + return true + case OpExtendToUint32Uint8x16: + v.Op = OpAMD64VPMOVZXBD512 + return true + case OpExtendToUint64Uint16x8: + v.Op = OpAMD64VPMOVZXWQ512 + return true + case OpExtendToUint64Uint32x4: + v.Op = OpAMD64VPMOVZXDQ256 + return true + case OpExtendToUint64Uint32x8: + v.Op = OpAMD64VPMOVZXDQ512 + return true case OpFMA: return rewriteValueAMD64_OpFMA(v) case OpFloor: return rewriteValueAMD64_OpFloor(v) + case OpFloorFloat32x4: + return rewriteValueAMD64_OpFloorFloat32x4(v) + case OpFloorFloat32x8: + return rewriteValueAMD64_OpFloorFloat32x8(v) + case OpFloorFloat64x2: + return rewriteValueAMD64_OpFloorFloat64x2(v) + case OpFloorFloat64x4: + return rewriteValueAMD64_OpFloorFloat64x4(v) + case OpFloorScaledFloat32x16: + return rewriteValueAMD64_OpFloorScaledFloat32x16(v) + case OpFloorScaledFloat32x4: + return rewriteValueAMD64_OpFloorScaledFloat32x4(v) + case OpFloorScaledFloat32x8: + return rewriteValueAMD64_OpFloorScaledFloat32x8(v) + case OpFloorScaledFloat64x2: + return rewriteValueAMD64_OpFloorScaledFloat64x2(v) + case OpFloorScaledFloat64x4: + return rewriteValueAMD64_OpFloorScaledFloat64x4(v) + case OpFloorScaledFloat64x8: + return rewriteValueAMD64_OpFloorScaledFloat64x8(v) + case OpFloorScaledResidueFloat32x16: + return rewriteValueAMD64_OpFloorScaledResidueFloat32x16(v) + case OpFloorScaledResidueFloat32x4: + return rewriteValueAMD64_OpFloorScaledResidueFloat32x4(v) + case OpFloorScaledResidueFloat32x8: + return rewriteValueAMD64_OpFloorScaledResidueFloat32x8(v) + case OpFloorScaledResidueFloat64x2: + return rewriteValueAMD64_OpFloorScaledResidueFloat64x2(v) + case OpFloorScaledResidueFloat64x4: + return rewriteValueAMD64_OpFloorScaledResidueFloat64x4(v) + case OpFloorScaledResidueFloat64x8: + return rewriteValueAMD64_OpFloorScaledResidueFloat64x8(v) + case OpGaloisFieldAffineTransformInverseUint8x16: + v.Op = OpAMD64VGF2P8AFFINEINVQB128 + return true + case OpGaloisFieldAffineTransformInverseUint8x32: + v.Op = OpAMD64VGF2P8AFFINEINVQB256 + return true + case OpGaloisFieldAffineTransformInverseUint8x64: + v.Op = OpAMD64VGF2P8AFFINEINVQB512 + return true + case OpGaloisFieldAffineTransformUint8x16: + v.Op = OpAMD64VGF2P8AFFINEQB128 + return true + case OpGaloisFieldAffineTransformUint8x32: + v.Op = OpAMD64VGF2P8AFFINEQB256 + return true + case OpGaloisFieldAffineTransformUint8x64: + v.Op = OpAMD64VGF2P8AFFINEQB512 + return true + case OpGaloisFieldMulUint8x16: + v.Op = OpAMD64VGF2P8MULB128 + return true + case OpGaloisFieldMulUint8x32: + v.Op = OpAMD64VGF2P8MULB256 + return true + case OpGaloisFieldMulUint8x64: + v.Op = OpAMD64VGF2P8MULB512 + return true case OpGetCallerPC: v.Op = OpAMD64LoweredGetCallerPC return true @@ -777,8 +4492,198 @@ func rewriteValueAMD64(v *Value) bool { case OpGetClosurePtr: v.Op = OpAMD64LoweredGetClosurePtr return true + case OpGetElemFloat32x4: + v.Op = OpAMD64VPEXTRD128 + return true + case OpGetElemFloat64x2: + v.Op = OpAMD64VPEXTRQ128 + return true + case OpGetElemInt16x8: + v.Op = OpAMD64VPEXTRW128 + return true + case OpGetElemInt32x4: + v.Op = OpAMD64VPEXTRD128 + return true + case OpGetElemInt64x2: + v.Op = OpAMD64VPEXTRQ128 + return true + case OpGetElemInt8x16: + v.Op = OpAMD64VPEXTRB128 + return true + case OpGetElemUint16x8: + v.Op = OpAMD64VPEXTRW128 + return true + case OpGetElemUint32x4: + v.Op = OpAMD64VPEXTRD128 + return true + case OpGetElemUint64x2: + v.Op = OpAMD64VPEXTRQ128 + return true + case OpGetElemUint8x16: + v.Op = OpAMD64VPEXTRB128 + return true case OpGetG: return rewriteValueAMD64_OpGetG(v) + case OpGetHiFloat32x16: + return rewriteValueAMD64_OpGetHiFloat32x16(v) + case OpGetHiFloat32x8: + return rewriteValueAMD64_OpGetHiFloat32x8(v) + case OpGetHiFloat64x4: + return rewriteValueAMD64_OpGetHiFloat64x4(v) + case OpGetHiFloat64x8: + return rewriteValueAMD64_OpGetHiFloat64x8(v) + case OpGetHiInt16x16: + return rewriteValueAMD64_OpGetHiInt16x16(v) + case OpGetHiInt16x32: + return rewriteValueAMD64_OpGetHiInt16x32(v) + case OpGetHiInt32x16: + return rewriteValueAMD64_OpGetHiInt32x16(v) + case OpGetHiInt32x8: + return rewriteValueAMD64_OpGetHiInt32x8(v) + case OpGetHiInt64x4: + return rewriteValueAMD64_OpGetHiInt64x4(v) + case OpGetHiInt64x8: + return rewriteValueAMD64_OpGetHiInt64x8(v) + case OpGetHiInt8x32: + return rewriteValueAMD64_OpGetHiInt8x32(v) + case OpGetHiInt8x64: + return rewriteValueAMD64_OpGetHiInt8x64(v) + case OpGetHiUint16x16: + return rewriteValueAMD64_OpGetHiUint16x16(v) + case OpGetHiUint16x32: + return rewriteValueAMD64_OpGetHiUint16x32(v) + case OpGetHiUint32x16: + return rewriteValueAMD64_OpGetHiUint32x16(v) + case OpGetHiUint32x8: + return rewriteValueAMD64_OpGetHiUint32x8(v) + case OpGetHiUint64x4: + return rewriteValueAMD64_OpGetHiUint64x4(v) + case OpGetHiUint64x8: + return rewriteValueAMD64_OpGetHiUint64x8(v) + case OpGetHiUint8x32: + return rewriteValueAMD64_OpGetHiUint8x32(v) + case OpGetHiUint8x64: + return rewriteValueAMD64_OpGetHiUint8x64(v) + case OpGetLoFloat32x16: + return rewriteValueAMD64_OpGetLoFloat32x16(v) + case OpGetLoFloat32x8: + return rewriteValueAMD64_OpGetLoFloat32x8(v) + case OpGetLoFloat64x4: + return rewriteValueAMD64_OpGetLoFloat64x4(v) + case OpGetLoFloat64x8: + return rewriteValueAMD64_OpGetLoFloat64x8(v) + case OpGetLoInt16x16: + return rewriteValueAMD64_OpGetLoInt16x16(v) + case OpGetLoInt16x32: + return rewriteValueAMD64_OpGetLoInt16x32(v) + case OpGetLoInt32x16: + return rewriteValueAMD64_OpGetLoInt32x16(v) + case OpGetLoInt32x8: + return rewriteValueAMD64_OpGetLoInt32x8(v) + case OpGetLoInt64x4: + return rewriteValueAMD64_OpGetLoInt64x4(v) + case OpGetLoInt64x8: + return rewriteValueAMD64_OpGetLoInt64x8(v) + case OpGetLoInt8x32: + return rewriteValueAMD64_OpGetLoInt8x32(v) + case OpGetLoInt8x64: + return rewriteValueAMD64_OpGetLoInt8x64(v) + case OpGetLoUint16x16: + return rewriteValueAMD64_OpGetLoUint16x16(v) + case OpGetLoUint16x32: + return rewriteValueAMD64_OpGetLoUint16x32(v) + case OpGetLoUint32x16: + return rewriteValueAMD64_OpGetLoUint32x16(v) + case OpGetLoUint32x8: + return rewriteValueAMD64_OpGetLoUint32x8(v) + case OpGetLoUint64x4: + return rewriteValueAMD64_OpGetLoUint64x4(v) + case OpGetLoUint64x8: + return rewriteValueAMD64_OpGetLoUint64x8(v) + case OpGetLoUint8x32: + return rewriteValueAMD64_OpGetLoUint8x32(v) + case OpGetLoUint8x64: + return rewriteValueAMD64_OpGetLoUint8x64(v) + case OpGreaterEqualFloat32x16: + return rewriteValueAMD64_OpGreaterEqualFloat32x16(v) + case OpGreaterEqualFloat32x4: + return rewriteValueAMD64_OpGreaterEqualFloat32x4(v) + case OpGreaterEqualFloat32x8: + return rewriteValueAMD64_OpGreaterEqualFloat32x8(v) + case OpGreaterEqualFloat64x2: + return rewriteValueAMD64_OpGreaterEqualFloat64x2(v) + case OpGreaterEqualFloat64x4: + return rewriteValueAMD64_OpGreaterEqualFloat64x4(v) + case OpGreaterEqualFloat64x8: + return rewriteValueAMD64_OpGreaterEqualFloat64x8(v) + case OpGreaterEqualInt16x32: + return rewriteValueAMD64_OpGreaterEqualInt16x32(v) + case OpGreaterEqualInt32x16: + return rewriteValueAMD64_OpGreaterEqualInt32x16(v) + case OpGreaterEqualInt64x8: + return rewriteValueAMD64_OpGreaterEqualInt64x8(v) + case OpGreaterEqualInt8x64: + return rewriteValueAMD64_OpGreaterEqualInt8x64(v) + case OpGreaterEqualUint16x32: + return rewriteValueAMD64_OpGreaterEqualUint16x32(v) + case OpGreaterEqualUint32x16: + return rewriteValueAMD64_OpGreaterEqualUint32x16(v) + case OpGreaterEqualUint64x8: + return rewriteValueAMD64_OpGreaterEqualUint64x8(v) + case OpGreaterEqualUint8x64: + return rewriteValueAMD64_OpGreaterEqualUint8x64(v) + case OpGreaterFloat32x16: + return rewriteValueAMD64_OpGreaterFloat32x16(v) + case OpGreaterFloat32x4: + return rewriteValueAMD64_OpGreaterFloat32x4(v) + case OpGreaterFloat32x8: + return rewriteValueAMD64_OpGreaterFloat32x8(v) + case OpGreaterFloat64x2: + return rewriteValueAMD64_OpGreaterFloat64x2(v) + case OpGreaterFloat64x4: + return rewriteValueAMD64_OpGreaterFloat64x4(v) + case OpGreaterFloat64x8: + return rewriteValueAMD64_OpGreaterFloat64x8(v) + case OpGreaterInt16x16: + v.Op = OpAMD64VPCMPGTW256 + return true + case OpGreaterInt16x32: + return rewriteValueAMD64_OpGreaterInt16x32(v) + case OpGreaterInt16x8: + v.Op = OpAMD64VPCMPGTW128 + return true + case OpGreaterInt32x16: + return rewriteValueAMD64_OpGreaterInt32x16(v) + case OpGreaterInt32x4: + v.Op = OpAMD64VPCMPGTD128 + return true + case OpGreaterInt32x8: + v.Op = OpAMD64VPCMPGTD256 + return true + case OpGreaterInt64x2: + v.Op = OpAMD64VPCMPGTQ128 + return true + case OpGreaterInt64x4: + v.Op = OpAMD64VPCMPGTQ256 + return true + case OpGreaterInt64x8: + return rewriteValueAMD64_OpGreaterInt64x8(v) + case OpGreaterInt8x16: + v.Op = OpAMD64VPCMPGTB128 + return true + case OpGreaterInt8x32: + v.Op = OpAMD64VPCMPGTB256 + return true + case OpGreaterInt8x64: + return rewriteValueAMD64_OpGreaterInt8x64(v) + case OpGreaterUint16x32: + return rewriteValueAMD64_OpGreaterUint16x32(v) + case OpGreaterUint32x16: + return rewriteValueAMD64_OpGreaterUint32x16(v) + case OpGreaterUint64x8: + return rewriteValueAMD64_OpGreaterUint64x8(v) + case OpGreaterUint8x64: + return rewriteValueAMD64_OpGreaterUint8x64(v) case OpHasCPUFeature: return rewriteValueAMD64_OpHasCPUFeature(v) case OpHmul32: @@ -796,12 +4701,170 @@ func rewriteValueAMD64(v *Value) bool { case OpInterCall: v.Op = OpAMD64CALLinter return true + case OpInterleaveHiGroupedInt16x16: + v.Op = OpAMD64VPUNPCKHWD256 + return true + case OpInterleaveHiGroupedInt16x32: + v.Op = OpAMD64VPUNPCKHWD512 + return true + case OpInterleaveHiGroupedInt32x16: + v.Op = OpAMD64VPUNPCKHDQ512 + return true + case OpInterleaveHiGroupedInt32x8: + v.Op = OpAMD64VPUNPCKHDQ256 + return true + case OpInterleaveHiGroupedInt64x4: + v.Op = OpAMD64VPUNPCKHQDQ256 + return true + case OpInterleaveHiGroupedInt64x8: + v.Op = OpAMD64VPUNPCKHQDQ512 + return true + case OpInterleaveHiGroupedUint16x16: + v.Op = OpAMD64VPUNPCKHWD256 + return true + case OpInterleaveHiGroupedUint16x32: + v.Op = OpAMD64VPUNPCKHWD512 + return true + case OpInterleaveHiGroupedUint32x16: + v.Op = OpAMD64VPUNPCKHDQ512 + return true + case OpInterleaveHiGroupedUint32x8: + v.Op = OpAMD64VPUNPCKHDQ256 + return true + case OpInterleaveHiGroupedUint64x4: + v.Op = OpAMD64VPUNPCKHQDQ256 + return true + case OpInterleaveHiGroupedUint64x8: + v.Op = OpAMD64VPUNPCKHQDQ512 + return true + case OpInterleaveHiInt16x8: + v.Op = OpAMD64VPUNPCKHWD128 + return true + case OpInterleaveHiInt32x4: + v.Op = OpAMD64VPUNPCKHDQ128 + return true + case OpInterleaveHiInt64x2: + v.Op = OpAMD64VPUNPCKHQDQ128 + return true + case OpInterleaveHiUint16x8: + v.Op = OpAMD64VPUNPCKHWD128 + return true + case OpInterleaveHiUint32x4: + v.Op = OpAMD64VPUNPCKHDQ128 + return true + case OpInterleaveHiUint64x2: + v.Op = OpAMD64VPUNPCKHQDQ128 + return true + case OpInterleaveLoGroupedInt16x16: + v.Op = OpAMD64VPUNPCKLWD256 + return true + case OpInterleaveLoGroupedInt16x32: + v.Op = OpAMD64VPUNPCKLWD512 + return true + case OpInterleaveLoGroupedInt32x16: + v.Op = OpAMD64VPUNPCKLDQ512 + return true + case OpInterleaveLoGroupedInt32x8: + v.Op = OpAMD64VPUNPCKLDQ256 + return true + case OpInterleaveLoGroupedInt64x4: + v.Op = OpAMD64VPUNPCKLQDQ256 + return true + case OpInterleaveLoGroupedInt64x8: + v.Op = OpAMD64VPUNPCKLQDQ512 + return true + case OpInterleaveLoGroupedUint16x16: + v.Op = OpAMD64VPUNPCKLWD256 + return true + case OpInterleaveLoGroupedUint16x32: + v.Op = OpAMD64VPUNPCKLWD512 + return true + case OpInterleaveLoGroupedUint32x16: + v.Op = OpAMD64VPUNPCKLDQ512 + return true + case OpInterleaveLoGroupedUint32x8: + v.Op = OpAMD64VPUNPCKLDQ256 + return true + case OpInterleaveLoGroupedUint64x4: + v.Op = OpAMD64VPUNPCKLQDQ256 + return true + case OpInterleaveLoGroupedUint64x8: + v.Op = OpAMD64VPUNPCKLQDQ512 + return true + case OpInterleaveLoInt16x8: + v.Op = OpAMD64VPUNPCKLWD128 + return true + case OpInterleaveLoInt32x4: + v.Op = OpAMD64VPUNPCKLDQ128 + return true + case OpInterleaveLoInt64x2: + v.Op = OpAMD64VPUNPCKLQDQ128 + return true + case OpInterleaveLoUint16x8: + v.Op = OpAMD64VPUNPCKLWD128 + return true + case OpInterleaveLoUint32x4: + v.Op = OpAMD64VPUNPCKLDQ128 + return true + case OpInterleaveLoUint64x2: + v.Op = OpAMD64VPUNPCKLQDQ128 + return true case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds(v) + case OpIsNaNFloat32x16: + return rewriteValueAMD64_OpIsNaNFloat32x16(v) + case OpIsNaNFloat32x4: + return rewriteValueAMD64_OpIsNaNFloat32x4(v) + case OpIsNaNFloat32x8: + return rewriteValueAMD64_OpIsNaNFloat32x8(v) + case OpIsNaNFloat64x2: + return rewriteValueAMD64_OpIsNaNFloat64x2(v) + case OpIsNaNFloat64x4: + return rewriteValueAMD64_OpIsNaNFloat64x4(v) + case OpIsNaNFloat64x8: + return rewriteValueAMD64_OpIsNaNFloat64x8(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds(v) + case OpIsZeroVec: + return rewriteValueAMD64_OpIsZeroVec(v) + case OpLeadingZerosInt32x16: + v.Op = OpAMD64VPLZCNTD512 + return true + case OpLeadingZerosInt32x4: + v.Op = OpAMD64VPLZCNTD128 + return true + case OpLeadingZerosInt32x8: + v.Op = OpAMD64VPLZCNTD256 + return true + case OpLeadingZerosInt64x2: + v.Op = OpAMD64VPLZCNTQ128 + return true + case OpLeadingZerosInt64x4: + v.Op = OpAMD64VPLZCNTQ256 + return true + case OpLeadingZerosInt64x8: + v.Op = OpAMD64VPLZCNTQ512 + return true + case OpLeadingZerosUint32x16: + v.Op = OpAMD64VPLZCNTD512 + return true + case OpLeadingZerosUint32x4: + v.Op = OpAMD64VPLZCNTD128 + return true + case OpLeadingZerosUint32x8: + v.Op = OpAMD64VPLZCNTD256 + return true + case OpLeadingZerosUint64x2: + v.Op = OpAMD64VPLZCNTQ128 + return true + case OpLeadingZerosUint64x4: + v.Op = OpAMD64VPLZCNTQ256 + return true + case OpLeadingZerosUint64x8: + v.Op = OpAMD64VPLZCNTQ512 + return true case OpLeq16: return rewriteValueAMD64_OpLeq16(v) case OpLeq16U: @@ -842,8 +4905,72 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpLess8(v) case OpLess8U: return rewriteValueAMD64_OpLess8U(v) + case OpLessEqualFloat32x16: + return rewriteValueAMD64_OpLessEqualFloat32x16(v) + case OpLessEqualFloat32x4: + return rewriteValueAMD64_OpLessEqualFloat32x4(v) + case OpLessEqualFloat32x8: + return rewriteValueAMD64_OpLessEqualFloat32x8(v) + case OpLessEqualFloat64x2: + return rewriteValueAMD64_OpLessEqualFloat64x2(v) + case OpLessEqualFloat64x4: + return rewriteValueAMD64_OpLessEqualFloat64x4(v) + case OpLessEqualFloat64x8: + return rewriteValueAMD64_OpLessEqualFloat64x8(v) + case OpLessEqualInt16x32: + return rewriteValueAMD64_OpLessEqualInt16x32(v) + case OpLessEqualInt32x16: + return rewriteValueAMD64_OpLessEqualInt32x16(v) + case OpLessEqualInt64x8: + return rewriteValueAMD64_OpLessEqualInt64x8(v) + case OpLessEqualInt8x64: + return rewriteValueAMD64_OpLessEqualInt8x64(v) + case OpLessEqualUint16x32: + return rewriteValueAMD64_OpLessEqualUint16x32(v) + case OpLessEqualUint32x16: + return rewriteValueAMD64_OpLessEqualUint32x16(v) + case OpLessEqualUint64x8: + return rewriteValueAMD64_OpLessEqualUint64x8(v) + case OpLessEqualUint8x64: + return rewriteValueAMD64_OpLessEqualUint8x64(v) + case OpLessFloat32x16: + return rewriteValueAMD64_OpLessFloat32x16(v) + case OpLessFloat32x4: + return rewriteValueAMD64_OpLessFloat32x4(v) + case OpLessFloat32x8: + return rewriteValueAMD64_OpLessFloat32x8(v) + case OpLessFloat64x2: + return rewriteValueAMD64_OpLessFloat64x2(v) + case OpLessFloat64x4: + return rewriteValueAMD64_OpLessFloat64x4(v) + case OpLessFloat64x8: + return rewriteValueAMD64_OpLessFloat64x8(v) + case OpLessInt16x32: + return rewriteValueAMD64_OpLessInt16x32(v) + case OpLessInt32x16: + return rewriteValueAMD64_OpLessInt32x16(v) + case OpLessInt64x8: + return rewriteValueAMD64_OpLessInt64x8(v) + case OpLessInt8x64: + return rewriteValueAMD64_OpLessInt8x64(v) + case OpLessUint16x32: + return rewriteValueAMD64_OpLessUint16x32(v) + case OpLessUint32x16: + return rewriteValueAMD64_OpLessUint32x16(v) + case OpLessUint64x8: + return rewriteValueAMD64_OpLessUint64x8(v) + case OpLessUint8x64: + return rewriteValueAMD64_OpLessUint8x64(v) case OpLoad: return rewriteValueAMD64_OpLoad(v) + case OpLoadMasked16: + return rewriteValueAMD64_OpLoadMasked16(v) + case OpLoadMasked32: + return rewriteValueAMD64_OpLoadMasked32(v) + case OpLoadMasked64: + return rewriteValueAMD64_OpLoadMasked64(v) + case OpLoadMasked8: + return rewriteValueAMD64_OpLoadMasked8(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr(v) case OpLsh16x16: @@ -882,10 +5009,190 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpMax32F(v) case OpMax64F: return rewriteValueAMD64_OpMax64F(v) + case OpMaxFloat32x16: + v.Op = OpAMD64VMAXPS512 + return true + case OpMaxFloat32x4: + v.Op = OpAMD64VMAXPS128 + return true + case OpMaxFloat32x8: + v.Op = OpAMD64VMAXPS256 + return true + case OpMaxFloat64x2: + v.Op = OpAMD64VMAXPD128 + return true + case OpMaxFloat64x4: + v.Op = OpAMD64VMAXPD256 + return true + case OpMaxFloat64x8: + v.Op = OpAMD64VMAXPD512 + return true + case OpMaxInt16x16: + v.Op = OpAMD64VPMAXSW256 + return true + case OpMaxInt16x32: + v.Op = OpAMD64VPMAXSW512 + return true + case OpMaxInt16x8: + v.Op = OpAMD64VPMAXSW128 + return true + case OpMaxInt32x16: + v.Op = OpAMD64VPMAXSD512 + return true + case OpMaxInt32x4: + v.Op = OpAMD64VPMAXSD128 + return true + case OpMaxInt32x8: + v.Op = OpAMD64VPMAXSD256 + return true + case OpMaxInt64x2: + v.Op = OpAMD64VPMAXSQ128 + return true + case OpMaxInt64x4: + v.Op = OpAMD64VPMAXSQ256 + return true + case OpMaxInt64x8: + v.Op = OpAMD64VPMAXSQ512 + return true + case OpMaxInt8x16: + v.Op = OpAMD64VPMAXSB128 + return true + case OpMaxInt8x32: + v.Op = OpAMD64VPMAXSB256 + return true + case OpMaxInt8x64: + v.Op = OpAMD64VPMAXSB512 + return true + case OpMaxUint16x16: + v.Op = OpAMD64VPMAXUW256 + return true + case OpMaxUint16x32: + v.Op = OpAMD64VPMAXUW512 + return true + case OpMaxUint16x8: + v.Op = OpAMD64VPMAXUW128 + return true + case OpMaxUint32x16: + v.Op = OpAMD64VPMAXUD512 + return true + case OpMaxUint32x4: + v.Op = OpAMD64VPMAXUD128 + return true + case OpMaxUint32x8: + v.Op = OpAMD64VPMAXUD256 + return true + case OpMaxUint64x2: + v.Op = OpAMD64VPMAXUQ128 + return true + case OpMaxUint64x4: + v.Op = OpAMD64VPMAXUQ256 + return true + case OpMaxUint64x8: + v.Op = OpAMD64VPMAXUQ512 + return true + case OpMaxUint8x16: + v.Op = OpAMD64VPMAXUB128 + return true + case OpMaxUint8x32: + v.Op = OpAMD64VPMAXUB256 + return true + case OpMaxUint8x64: + v.Op = OpAMD64VPMAXUB512 + return true case OpMin32F: return rewriteValueAMD64_OpMin32F(v) case OpMin64F: return rewriteValueAMD64_OpMin64F(v) + case OpMinFloat32x16: + v.Op = OpAMD64VMINPS512 + return true + case OpMinFloat32x4: + v.Op = OpAMD64VMINPS128 + return true + case OpMinFloat32x8: + v.Op = OpAMD64VMINPS256 + return true + case OpMinFloat64x2: + v.Op = OpAMD64VMINPD128 + return true + case OpMinFloat64x4: + v.Op = OpAMD64VMINPD256 + return true + case OpMinFloat64x8: + v.Op = OpAMD64VMINPD512 + return true + case OpMinInt16x16: + v.Op = OpAMD64VPMINSW256 + return true + case OpMinInt16x32: + v.Op = OpAMD64VPMINSW512 + return true + case OpMinInt16x8: + v.Op = OpAMD64VPMINSW128 + return true + case OpMinInt32x16: + v.Op = OpAMD64VPMINSD512 + return true + case OpMinInt32x4: + v.Op = OpAMD64VPMINSD128 + return true + case OpMinInt32x8: + v.Op = OpAMD64VPMINSD256 + return true + case OpMinInt64x2: + v.Op = OpAMD64VPMINSQ128 + return true + case OpMinInt64x4: + v.Op = OpAMD64VPMINSQ256 + return true + case OpMinInt64x8: + v.Op = OpAMD64VPMINSQ512 + return true + case OpMinInt8x16: + v.Op = OpAMD64VPMINSB128 + return true + case OpMinInt8x32: + v.Op = OpAMD64VPMINSB256 + return true + case OpMinInt8x64: + v.Op = OpAMD64VPMINSB512 + return true + case OpMinUint16x16: + v.Op = OpAMD64VPMINUW256 + return true + case OpMinUint16x32: + v.Op = OpAMD64VPMINUW512 + return true + case OpMinUint16x8: + v.Op = OpAMD64VPMINUW128 + return true + case OpMinUint32x16: + v.Op = OpAMD64VPMINUD512 + return true + case OpMinUint32x4: + v.Op = OpAMD64VPMINUD128 + return true + case OpMinUint32x8: + v.Op = OpAMD64VPMINUD256 + return true + case OpMinUint64x2: + v.Op = OpAMD64VPMINUQ128 + return true + case OpMinUint64x4: + v.Op = OpAMD64VPMINUQ256 + return true + case OpMinUint64x8: + v.Op = OpAMD64VPMINUQ512 + return true + case OpMinUint8x16: + v.Op = OpAMD64VPMINUB128 + return true + case OpMinUint8x32: + v.Op = OpAMD64VPMINUB256 + return true + case OpMinUint8x64: + v.Op = OpAMD64VPMINUB512 + return true case OpMod16: return rewriteValueAMD64_OpMod16(v) case OpMod16u: @@ -925,6 +5232,180 @@ func rewriteValueAMD64(v *Value) bool { case OpMul8: v.Op = OpAMD64MULL return true + case OpMulAddEvenSubOddFloat32x16: + v.Op = OpAMD64VFMADDSUB213PS512 + return true + case OpMulAddEvenSubOddFloat32x4: + v.Op = OpAMD64VFMADDSUB213PS128 + return true + case OpMulAddEvenSubOddFloat32x8: + v.Op = OpAMD64VFMADDSUB213PS256 + return true + case OpMulAddEvenSubOddFloat64x2: + v.Op = OpAMD64VFMADDSUB213PD128 + return true + case OpMulAddEvenSubOddFloat64x4: + v.Op = OpAMD64VFMADDSUB213PD256 + return true + case OpMulAddEvenSubOddFloat64x8: + v.Op = OpAMD64VFMADDSUB213PD512 + return true + case OpMulAddFloat32x16: + v.Op = OpAMD64VFMADD213PS512 + return true + case OpMulAddFloat32x4: + v.Op = OpAMD64VFMADD213PS128 + return true + case OpMulAddFloat32x8: + v.Op = OpAMD64VFMADD213PS256 + return true + case OpMulAddFloat64x2: + v.Op = OpAMD64VFMADD213PD128 + return true + case OpMulAddFloat64x4: + v.Op = OpAMD64VFMADD213PD256 + return true + case OpMulAddFloat64x8: + v.Op = OpAMD64VFMADD213PD512 + return true + case OpMulAddOddSubEvenFloat32x16: + v.Op = OpAMD64VFMSUBADD213PS512 + return true + case OpMulAddOddSubEvenFloat32x4: + v.Op = OpAMD64VFMSUBADD213PS128 + return true + case OpMulAddOddSubEvenFloat32x8: + v.Op = OpAMD64VFMSUBADD213PS256 + return true + case OpMulAddOddSubEvenFloat64x2: + v.Op = OpAMD64VFMSUBADD213PD128 + return true + case OpMulAddOddSubEvenFloat64x4: + v.Op = OpAMD64VFMSUBADD213PD256 + return true + case OpMulAddOddSubEvenFloat64x8: + v.Op = OpAMD64VFMSUBADD213PD512 + return true + case OpMulFloat32x16: + v.Op = OpAMD64VMULPS512 + return true + case OpMulFloat32x4: + v.Op = OpAMD64VMULPS128 + return true + case OpMulFloat32x8: + v.Op = OpAMD64VMULPS256 + return true + case OpMulFloat64x2: + v.Op = OpAMD64VMULPD128 + return true + case OpMulFloat64x4: + v.Op = OpAMD64VMULPD256 + return true + case OpMulFloat64x8: + v.Op = OpAMD64VMULPD512 + return true + case OpMulHighInt16x16: + v.Op = OpAMD64VPMULHW256 + return true + case OpMulHighInt16x32: + v.Op = OpAMD64VPMULHW512 + return true + case OpMulHighInt16x8: + v.Op = OpAMD64VPMULHW128 + return true + case OpMulHighUint16x16: + v.Op = OpAMD64VPMULHUW256 + return true + case OpMulHighUint16x32: + v.Op = OpAMD64VPMULHUW512 + return true + case OpMulHighUint16x8: + v.Op = OpAMD64VPMULHUW128 + return true + case OpMulInt16x16: + v.Op = OpAMD64VPMULLW256 + return true + case OpMulInt16x32: + v.Op = OpAMD64VPMULLW512 + return true + case OpMulInt16x8: + v.Op = OpAMD64VPMULLW128 + return true + case OpMulInt32x16: + v.Op = OpAMD64VPMULLD512 + return true + case OpMulInt32x4: + v.Op = OpAMD64VPMULLD128 + return true + case OpMulInt32x8: + v.Op = OpAMD64VPMULLD256 + return true + case OpMulInt64x2: + v.Op = OpAMD64VPMULLQ128 + return true + case OpMulInt64x4: + v.Op = OpAMD64VPMULLQ256 + return true + case OpMulInt64x8: + v.Op = OpAMD64VPMULLQ512 + return true + case OpMulSignInt16x16: + v.Op = OpAMD64VPSIGNW256 + return true + case OpMulSignInt16x8: + v.Op = OpAMD64VPSIGNW128 + return true + case OpMulSignInt32x4: + v.Op = OpAMD64VPSIGND128 + return true + case OpMulSignInt32x8: + v.Op = OpAMD64VPSIGND256 + return true + case OpMulSignInt8x16: + v.Op = OpAMD64VPSIGNB128 + return true + case OpMulSignInt8x32: + v.Op = OpAMD64VPSIGNB256 + return true + case OpMulUint16x16: + v.Op = OpAMD64VPMULLW256 + return true + case OpMulUint16x32: + v.Op = OpAMD64VPMULLW512 + return true + case OpMulUint16x8: + v.Op = OpAMD64VPMULLW128 + return true + case OpMulUint32x16: + v.Op = OpAMD64VPMULLD512 + return true + case OpMulUint32x4: + v.Op = OpAMD64VPMULLD128 + return true + case OpMulUint32x8: + v.Op = OpAMD64VPMULLD256 + return true + case OpMulUint64x2: + v.Op = OpAMD64VPMULLQ128 + return true + case OpMulUint64x4: + v.Op = OpAMD64VPMULLQ256 + return true + case OpMulUint64x8: + v.Op = OpAMD64VPMULLQ512 + return true + case OpMulWidenEvenInt32x4: + v.Op = OpAMD64VPMULDQ128 + return true + case OpMulWidenEvenInt32x8: + v.Op = OpAMD64VPMULDQ256 + return true + case OpMulWidenEvenUint32x4: + v.Op = OpAMD64VPMULUDQ128 + return true + case OpMulWidenEvenUint32x8: + v.Op = OpAMD64VPMULUDQ256 + return true case OpNeg16: v.Op = OpAMD64NEGL return true @@ -962,8 +5443,108 @@ func rewriteValueAMD64(v *Value) bool { return true case OpNot: return rewriteValueAMD64_OpNot(v) + case OpNotEqualFloat32x16: + return rewriteValueAMD64_OpNotEqualFloat32x16(v) + case OpNotEqualFloat32x4: + return rewriteValueAMD64_OpNotEqualFloat32x4(v) + case OpNotEqualFloat32x8: + return rewriteValueAMD64_OpNotEqualFloat32x8(v) + case OpNotEqualFloat64x2: + return rewriteValueAMD64_OpNotEqualFloat64x2(v) + case OpNotEqualFloat64x4: + return rewriteValueAMD64_OpNotEqualFloat64x4(v) + case OpNotEqualFloat64x8: + return rewriteValueAMD64_OpNotEqualFloat64x8(v) + case OpNotEqualInt16x32: + return rewriteValueAMD64_OpNotEqualInt16x32(v) + case OpNotEqualInt32x16: + return rewriteValueAMD64_OpNotEqualInt32x16(v) + case OpNotEqualInt64x8: + return rewriteValueAMD64_OpNotEqualInt64x8(v) + case OpNotEqualInt8x64: + return rewriteValueAMD64_OpNotEqualInt8x64(v) + case OpNotEqualUint16x32: + return rewriteValueAMD64_OpNotEqualUint16x32(v) + case OpNotEqualUint32x16: + return rewriteValueAMD64_OpNotEqualUint32x16(v) + case OpNotEqualUint64x8: + return rewriteValueAMD64_OpNotEqualUint64x8(v) + case OpNotEqualUint8x64: + return rewriteValueAMD64_OpNotEqualUint8x64(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr(v) + case OpOnesCountInt16x16: + v.Op = OpAMD64VPOPCNTW256 + return true + case OpOnesCountInt16x32: + v.Op = OpAMD64VPOPCNTW512 + return true + case OpOnesCountInt16x8: + v.Op = OpAMD64VPOPCNTW128 + return true + case OpOnesCountInt32x16: + v.Op = OpAMD64VPOPCNTD512 + return true + case OpOnesCountInt32x4: + v.Op = OpAMD64VPOPCNTD128 + return true + case OpOnesCountInt32x8: + v.Op = OpAMD64VPOPCNTD256 + return true + case OpOnesCountInt64x2: + v.Op = OpAMD64VPOPCNTQ128 + return true + case OpOnesCountInt64x4: + v.Op = OpAMD64VPOPCNTQ256 + return true + case OpOnesCountInt64x8: + v.Op = OpAMD64VPOPCNTQ512 + return true + case OpOnesCountInt8x16: + v.Op = OpAMD64VPOPCNTB128 + return true + case OpOnesCountInt8x32: + v.Op = OpAMD64VPOPCNTB256 + return true + case OpOnesCountInt8x64: + v.Op = OpAMD64VPOPCNTB512 + return true + case OpOnesCountUint16x16: + v.Op = OpAMD64VPOPCNTW256 + return true + case OpOnesCountUint16x32: + v.Op = OpAMD64VPOPCNTW512 + return true + case OpOnesCountUint16x8: + v.Op = OpAMD64VPOPCNTW128 + return true + case OpOnesCountUint32x16: + v.Op = OpAMD64VPOPCNTD512 + return true + case OpOnesCountUint32x4: + v.Op = OpAMD64VPOPCNTD128 + return true + case OpOnesCountUint32x8: + v.Op = OpAMD64VPOPCNTD256 + return true + case OpOnesCountUint64x2: + v.Op = OpAMD64VPOPCNTQ128 + return true + case OpOnesCountUint64x4: + v.Op = OpAMD64VPOPCNTQ256 + return true + case OpOnesCountUint64x8: + v.Op = OpAMD64VPOPCNTQ512 + return true + case OpOnesCountUint8x16: + v.Op = OpAMD64VPOPCNTB128 + return true + case OpOnesCountUint8x32: + v.Op = OpAMD64VPOPCNTB256 + return true + case OpOnesCountUint8x64: + v.Op = OpAMD64VPOPCNTB512 + return true case OpOr16: v.Op = OpAMD64ORL return true @@ -979,9 +5560,171 @@ func rewriteValueAMD64(v *Value) bool { case OpOrB: v.Op = OpAMD64ORL return true + case OpOrInt16x16: + v.Op = OpAMD64VPOR256 + return true + case OpOrInt16x32: + v.Op = OpAMD64VPORD512 + return true + case OpOrInt16x8: + v.Op = OpAMD64VPOR128 + return true + case OpOrInt32x16: + v.Op = OpAMD64VPORD512 + return true + case OpOrInt32x4: + v.Op = OpAMD64VPOR128 + return true + case OpOrInt32x8: + v.Op = OpAMD64VPOR256 + return true + case OpOrInt64x2: + v.Op = OpAMD64VPOR128 + return true + case OpOrInt64x4: + v.Op = OpAMD64VPOR256 + return true + case OpOrInt64x8: + v.Op = OpAMD64VPORQ512 + return true + case OpOrInt8x16: + v.Op = OpAMD64VPOR128 + return true + case OpOrInt8x32: + v.Op = OpAMD64VPOR256 + return true + case OpOrInt8x64: + v.Op = OpAMD64VPORD512 + return true + case OpOrUint16x16: + v.Op = OpAMD64VPOR256 + return true + case OpOrUint16x32: + v.Op = OpAMD64VPORD512 + return true + case OpOrUint16x8: + v.Op = OpAMD64VPOR128 + return true + case OpOrUint32x16: + v.Op = OpAMD64VPORD512 + return true + case OpOrUint32x4: + v.Op = OpAMD64VPOR128 + return true + case OpOrUint32x8: + v.Op = OpAMD64VPOR256 + return true + case OpOrUint64x2: + v.Op = OpAMD64VPOR128 + return true + case OpOrUint64x4: + v.Op = OpAMD64VPOR256 + return true + case OpOrUint64x8: + v.Op = OpAMD64VPORQ512 + return true + case OpOrUint8x16: + v.Op = OpAMD64VPOR128 + return true + case OpOrUint8x32: + v.Op = OpAMD64VPOR256 + return true + case OpOrUint8x64: + v.Op = OpAMD64VPORD512 + return true case OpPanicBounds: v.Op = OpAMD64LoweredPanicBoundsRR return true + case OpPermuteFloat32x16: + v.Op = OpAMD64VPERMPS512 + return true + case OpPermuteFloat32x8: + v.Op = OpAMD64VPERMPS256 + return true + case OpPermuteFloat64x4: + v.Op = OpAMD64VPERMPD256 + return true + case OpPermuteFloat64x8: + v.Op = OpAMD64VPERMPD512 + return true + case OpPermuteInt16x16: + v.Op = OpAMD64VPERMW256 + return true + case OpPermuteInt16x32: + v.Op = OpAMD64VPERMW512 + return true + case OpPermuteInt16x8: + v.Op = OpAMD64VPERMW128 + return true + case OpPermuteInt32x16: + v.Op = OpAMD64VPERMD512 + return true + case OpPermuteInt32x8: + v.Op = OpAMD64VPERMD256 + return true + case OpPermuteInt64x4: + v.Op = OpAMD64VPERMQ256 + return true + case OpPermuteInt64x8: + v.Op = OpAMD64VPERMQ512 + return true + case OpPermuteInt8x16: + v.Op = OpAMD64VPERMB128 + return true + case OpPermuteInt8x32: + v.Op = OpAMD64VPERMB256 + return true + case OpPermuteInt8x64: + v.Op = OpAMD64VPERMB512 + return true + case OpPermuteOrZeroGroupedInt8x32: + v.Op = OpAMD64VPSHUFB256 + return true + case OpPermuteOrZeroGroupedInt8x64: + v.Op = OpAMD64VPSHUFB512 + return true + case OpPermuteOrZeroGroupedUint8x32: + v.Op = OpAMD64VPSHUFB256 + return true + case OpPermuteOrZeroGroupedUint8x64: + v.Op = OpAMD64VPSHUFB512 + return true + case OpPermuteOrZeroInt8x16: + v.Op = OpAMD64VPSHUFB128 + return true + case OpPermuteOrZeroUint8x16: + v.Op = OpAMD64VPSHUFB128 + return true + case OpPermuteUint16x16: + v.Op = OpAMD64VPERMW256 + return true + case OpPermuteUint16x32: + v.Op = OpAMD64VPERMW512 + return true + case OpPermuteUint16x8: + v.Op = OpAMD64VPERMW128 + return true + case OpPermuteUint32x16: + v.Op = OpAMD64VPERMD512 + return true + case OpPermuteUint32x8: + v.Op = OpAMD64VPERMD256 + return true + case OpPermuteUint64x4: + v.Op = OpAMD64VPERMQ256 + return true + case OpPermuteUint64x8: + v.Op = OpAMD64VPERMQ512 + return true + case OpPermuteUint8x16: + v.Op = OpAMD64VPERMB128 + return true + case OpPermuteUint8x32: + v.Op = OpAMD64VPERMB256 + return true + case OpPermuteUint8x64: + v.Op = OpAMD64VPERMB512 + return true case OpPopCount16: return rewriteValueAMD64_OpPopCount16(v) case OpPopCount32: @@ -998,6 +5741,42 @@ func rewriteValueAMD64(v *Value) bool { case OpPrefetchCacheStreamed: v.Op = OpAMD64PrefetchNTA return true + case OpReciprocalFloat32x16: + v.Op = OpAMD64VRCP14PS512 + return true + case OpReciprocalFloat32x4: + v.Op = OpAMD64VRCPPS128 + return true + case OpReciprocalFloat32x8: + v.Op = OpAMD64VRCPPS256 + return true + case OpReciprocalFloat64x2: + v.Op = OpAMD64VRCP14PD128 + return true + case OpReciprocalFloat64x4: + v.Op = OpAMD64VRCP14PD256 + return true + case OpReciprocalFloat64x8: + v.Op = OpAMD64VRCP14PD512 + return true + case OpReciprocalSqrtFloat32x16: + v.Op = OpAMD64VRSQRT14PS512 + return true + case OpReciprocalSqrtFloat32x4: + v.Op = OpAMD64VRSQRTPS128 + return true + case OpReciprocalSqrtFloat32x8: + v.Op = OpAMD64VRSQRTPS256 + return true + case OpReciprocalSqrtFloat64x2: + v.Op = OpAMD64VRSQRT14PD128 + return true + case OpReciprocalSqrtFloat64x4: + v.Op = OpAMD64VRSQRT14PD256 + return true + case OpReciprocalSqrtFloat64x8: + v.Op = OpAMD64VRSQRT14PD512 + return true case OpRotateLeft16: v.Op = OpAMD64ROLW return true @@ -1010,12 +5789,116 @@ func rewriteValueAMD64(v *Value) bool { case OpRotateLeft8: v.Op = OpAMD64ROLB return true + case OpRotateLeftInt32x16: + v.Op = OpAMD64VPROLVD512 + return true + case OpRotateLeftInt32x4: + v.Op = OpAMD64VPROLVD128 + return true + case OpRotateLeftInt32x8: + v.Op = OpAMD64VPROLVD256 + return true + case OpRotateLeftInt64x2: + v.Op = OpAMD64VPROLVQ128 + return true + case OpRotateLeftInt64x4: + v.Op = OpAMD64VPROLVQ256 + return true + case OpRotateLeftInt64x8: + v.Op = OpAMD64VPROLVQ512 + return true + case OpRotateLeftUint32x16: + v.Op = OpAMD64VPROLVD512 + return true + case OpRotateLeftUint32x4: + v.Op = OpAMD64VPROLVD128 + return true + case OpRotateLeftUint32x8: + v.Op = OpAMD64VPROLVD256 + return true + case OpRotateLeftUint64x2: + v.Op = OpAMD64VPROLVQ128 + return true + case OpRotateLeftUint64x4: + v.Op = OpAMD64VPROLVQ256 + return true + case OpRotateLeftUint64x8: + v.Op = OpAMD64VPROLVQ512 + return true + case OpRotateRightInt32x16: + v.Op = OpAMD64VPRORVD512 + return true + case OpRotateRightInt32x4: + v.Op = OpAMD64VPRORVD128 + return true + case OpRotateRightInt32x8: + v.Op = OpAMD64VPRORVD256 + return true + case OpRotateRightInt64x2: + v.Op = OpAMD64VPRORVQ128 + return true + case OpRotateRightInt64x4: + v.Op = OpAMD64VPRORVQ256 + return true + case OpRotateRightInt64x8: + v.Op = OpAMD64VPRORVQ512 + return true + case OpRotateRightUint32x16: + v.Op = OpAMD64VPRORVD512 + return true + case OpRotateRightUint32x4: + v.Op = OpAMD64VPRORVD128 + return true + case OpRotateRightUint32x8: + v.Op = OpAMD64VPRORVD256 + return true + case OpRotateRightUint64x2: + v.Op = OpAMD64VPRORVQ128 + return true + case OpRotateRightUint64x4: + v.Op = OpAMD64VPRORVQ256 + return true + case OpRotateRightUint64x8: + v.Op = OpAMD64VPRORVQ512 + return true case OpRound32F: v.Op = OpAMD64LoweredRound32F return true case OpRound64F: v.Op = OpAMD64LoweredRound64F return true + case OpRoundFloat32x4: + return rewriteValueAMD64_OpRoundFloat32x4(v) + case OpRoundFloat32x8: + return rewriteValueAMD64_OpRoundFloat32x8(v) + case OpRoundFloat64x2: + return rewriteValueAMD64_OpRoundFloat64x2(v) + case OpRoundFloat64x4: + return rewriteValueAMD64_OpRoundFloat64x4(v) + case OpRoundScaledFloat32x16: + return rewriteValueAMD64_OpRoundScaledFloat32x16(v) + case OpRoundScaledFloat32x4: + return rewriteValueAMD64_OpRoundScaledFloat32x4(v) + case OpRoundScaledFloat32x8: + return rewriteValueAMD64_OpRoundScaledFloat32x8(v) + case OpRoundScaledFloat64x2: + return rewriteValueAMD64_OpRoundScaledFloat64x2(v) + case OpRoundScaledFloat64x4: + return rewriteValueAMD64_OpRoundScaledFloat64x4(v) + case OpRoundScaledFloat64x8: + return rewriteValueAMD64_OpRoundScaledFloat64x8(v) + case OpRoundScaledResidueFloat32x16: + return rewriteValueAMD64_OpRoundScaledResidueFloat32x16(v) + case OpRoundScaledResidueFloat32x4: + return rewriteValueAMD64_OpRoundScaledResidueFloat32x4(v) + case OpRoundScaledResidueFloat32x8: + return rewriteValueAMD64_OpRoundScaledResidueFloat32x8(v) + case OpRoundScaledResidueFloat64x2: + return rewriteValueAMD64_OpRoundScaledResidueFloat64x2(v) + case OpRoundScaledResidueFloat64x4: + return rewriteValueAMD64_OpRoundScaledResidueFloat64x4(v) + case OpRoundScaledResidueFloat64x8: + return rewriteValueAMD64_OpRoundScaledResidueFloat64x8(v) case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven(v) case OpRsh16Ux16: @@ -1082,12 +5965,719 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8(v) + case OpSHA1FourRoundsUint32x4: + v.Op = OpAMD64SHA1RNDS4128 + return true + case OpSHA1Message1Uint32x4: + v.Op = OpAMD64SHA1MSG1128 + return true + case OpSHA1Message2Uint32x4: + v.Op = OpAMD64SHA1MSG2128 + return true + case OpSHA1NextEUint32x4: + v.Op = OpAMD64SHA1NEXTE128 + return true + case OpSHA256Message1Uint32x4: + v.Op = OpAMD64SHA256MSG1128 + return true + case OpSHA256Message2Uint32x4: + v.Op = OpAMD64SHA256MSG2128 + return true + case OpSHA256TwoRoundsUint32x4: + v.Op = OpAMD64SHA256RNDS2128 + return true + case OpSaturateToInt16ConcatGroupedInt32x16: + v.Op = OpAMD64VPACKSSDW512 + return true + case OpSaturateToInt16ConcatGroupedInt32x8: + v.Op = OpAMD64VPACKSSDW256 + return true + case OpSaturateToInt16ConcatInt32x4: + v.Op = OpAMD64VPACKSSDW128 + return true + case OpSaturateToInt16Int32x16: + v.Op = OpAMD64VPMOVSDW256 + return true + case OpSaturateToInt16Int32x4: + v.Op = OpAMD64VPMOVSDW128_128 + return true + case OpSaturateToInt16Int32x8: + v.Op = OpAMD64VPMOVSDW128_256 + return true + case OpSaturateToInt16Int64x2: + v.Op = OpAMD64VPMOVSQW128_128 + return true + case OpSaturateToInt16Int64x4: + v.Op = OpAMD64VPMOVSQW128_256 + return true + case OpSaturateToInt16Int64x8: + v.Op = OpAMD64VPMOVSQW128_512 + return true + case OpSaturateToInt32Int64x2: + v.Op = OpAMD64VPMOVSQD128_128 + return true + case OpSaturateToInt32Int64x4: + v.Op = OpAMD64VPMOVSQD128_256 + return true + case OpSaturateToInt32Int64x8: + v.Op = OpAMD64VPMOVSQD256 + return true + case OpSaturateToInt8Int16x16: + v.Op = OpAMD64VPMOVSWB128_256 + return true + case OpSaturateToInt8Int16x32: + v.Op = OpAMD64VPMOVSWB256 + return true + case OpSaturateToInt8Int16x8: + v.Op = OpAMD64VPMOVSWB128_128 + return true + case OpSaturateToInt8Int32x16: + v.Op = OpAMD64VPMOVSDB128_512 + return true + case OpSaturateToInt8Int32x4: + v.Op = OpAMD64VPMOVSDB128_128 + return true + case OpSaturateToInt8Int32x8: + v.Op = OpAMD64VPMOVSDB128_256 + return true + case OpSaturateToInt8Int64x2: + v.Op = OpAMD64VPMOVSQB128_128 + return true + case OpSaturateToInt8Int64x4: + v.Op = OpAMD64VPMOVSQB128_256 + return true + case OpSaturateToInt8Int64x8: + v.Op = OpAMD64VPMOVSQB128_512 + return true + case OpSaturateToUint16ConcatGroupedInt32x16: + v.Op = OpAMD64VPACKUSDW512 + return true + case OpSaturateToUint16ConcatGroupedInt32x8: + v.Op = OpAMD64VPACKUSDW256 + return true + case OpSaturateToUint16ConcatInt32x4: + v.Op = OpAMD64VPACKUSDW128 + return true + case OpSaturateToUint16Uint32x16: + v.Op = OpAMD64VPMOVUSDW256 + return true + case OpSaturateToUint16Uint32x4: + v.Op = OpAMD64VPMOVUSDW128_128 + return true + case OpSaturateToUint16Uint32x8: + v.Op = OpAMD64VPMOVUSDW128_256 + return true + case OpSaturateToUint16Uint64x2: + v.Op = OpAMD64VPMOVUSQW128_128 + return true + case OpSaturateToUint16Uint64x4: + v.Op = OpAMD64VPMOVUSQW128_256 + return true + case OpSaturateToUint16Uint64x8: + v.Op = OpAMD64VPMOVUSQW128_512 + return true + case OpSaturateToUint32Uint64x2: + v.Op = OpAMD64VPMOVUSQD128_128 + return true + case OpSaturateToUint32Uint64x4: + v.Op = OpAMD64VPMOVUSQD128_256 + return true + case OpSaturateToUint32Uint64x8: + v.Op = OpAMD64VPMOVUSQD256 + return true + case OpSaturateToUint8Uint16x16: + v.Op = OpAMD64VPMOVUSWB128_256 + return true + case OpSaturateToUint8Uint16x32: + v.Op = OpAMD64VPMOVUSWB256 + return true + case OpSaturateToUint8Uint16x8: + v.Op = OpAMD64VPMOVUSWB128_128 + return true + case OpSaturateToUint8Uint32x16: + v.Op = OpAMD64VPMOVUSDB128_512 + return true + case OpSaturateToUint8Uint32x4: + v.Op = OpAMD64VPMOVUSDB128_128 + return true + case OpSaturateToUint8Uint32x8: + v.Op = OpAMD64VPMOVUSDB128_256 + return true + case OpSaturateToUint8Uint64x2: + v.Op = OpAMD64VPMOVUSQB128_128 + return true + case OpSaturateToUint8Uint64x4: + v.Op = OpAMD64VPMOVUSQB128_256 + return true + case OpSaturateToUint8Uint64x8: + v.Op = OpAMD64VPMOVUSQB128_512 + return true + case OpScaleFloat32x16: + v.Op = OpAMD64VSCALEFPS512 + return true + case OpScaleFloat32x4: + v.Op = OpAMD64VSCALEFPS128 + return true + case OpScaleFloat32x8: + v.Op = OpAMD64VSCALEFPS256 + return true + case OpScaleFloat64x2: + v.Op = OpAMD64VSCALEFPD128 + return true + case OpScaleFloat64x4: + v.Op = OpAMD64VSCALEFPD256 + return true + case OpScaleFloat64x8: + v.Op = OpAMD64VSCALEFPD512 + return true case OpSelect0: return rewriteValueAMD64_OpSelect0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1(v) case OpSelectN: return rewriteValueAMD64_OpSelectN(v) + case OpSetElemFloat32x4: + v.Op = OpAMD64VPINSRD128 + return true + case OpSetElemFloat64x2: + v.Op = OpAMD64VPINSRQ128 + return true + case OpSetElemInt16x8: + v.Op = OpAMD64VPINSRW128 + return true + case OpSetElemInt32x4: + v.Op = OpAMD64VPINSRD128 + return true + case OpSetElemInt64x2: + v.Op = OpAMD64VPINSRQ128 + return true + case OpSetElemInt8x16: + v.Op = OpAMD64VPINSRB128 + return true + case OpSetElemUint16x8: + v.Op = OpAMD64VPINSRW128 + return true + case OpSetElemUint32x4: + v.Op = OpAMD64VPINSRD128 + return true + case OpSetElemUint64x2: + v.Op = OpAMD64VPINSRQ128 + return true + case OpSetElemUint8x16: + v.Op = OpAMD64VPINSRB128 + return true + case OpSetHiFloat32x16: + return rewriteValueAMD64_OpSetHiFloat32x16(v) + case OpSetHiFloat32x8: + return rewriteValueAMD64_OpSetHiFloat32x8(v) + case OpSetHiFloat64x4: + return rewriteValueAMD64_OpSetHiFloat64x4(v) + case OpSetHiFloat64x8: + return rewriteValueAMD64_OpSetHiFloat64x8(v) + case OpSetHiInt16x16: + return rewriteValueAMD64_OpSetHiInt16x16(v) + case OpSetHiInt16x32: + return rewriteValueAMD64_OpSetHiInt16x32(v) + case OpSetHiInt32x16: + return rewriteValueAMD64_OpSetHiInt32x16(v) + case OpSetHiInt32x8: + return rewriteValueAMD64_OpSetHiInt32x8(v) + case OpSetHiInt64x4: + return rewriteValueAMD64_OpSetHiInt64x4(v) + case OpSetHiInt64x8: + return rewriteValueAMD64_OpSetHiInt64x8(v) + case OpSetHiInt8x32: + return rewriteValueAMD64_OpSetHiInt8x32(v) + case OpSetHiInt8x64: + return rewriteValueAMD64_OpSetHiInt8x64(v) + case OpSetHiUint16x16: + return rewriteValueAMD64_OpSetHiUint16x16(v) + case OpSetHiUint16x32: + return rewriteValueAMD64_OpSetHiUint16x32(v) + case OpSetHiUint32x16: + return rewriteValueAMD64_OpSetHiUint32x16(v) + case OpSetHiUint32x8: + return rewriteValueAMD64_OpSetHiUint32x8(v) + case OpSetHiUint64x4: + return rewriteValueAMD64_OpSetHiUint64x4(v) + case OpSetHiUint64x8: + return rewriteValueAMD64_OpSetHiUint64x8(v) + case OpSetHiUint8x32: + return rewriteValueAMD64_OpSetHiUint8x32(v) + case OpSetHiUint8x64: + return rewriteValueAMD64_OpSetHiUint8x64(v) + case OpSetLoFloat32x16: + return rewriteValueAMD64_OpSetLoFloat32x16(v) + case OpSetLoFloat32x8: + return rewriteValueAMD64_OpSetLoFloat32x8(v) + case OpSetLoFloat64x4: + return rewriteValueAMD64_OpSetLoFloat64x4(v) + case OpSetLoFloat64x8: + return rewriteValueAMD64_OpSetLoFloat64x8(v) + case OpSetLoInt16x16: + return rewriteValueAMD64_OpSetLoInt16x16(v) + case OpSetLoInt16x32: + return rewriteValueAMD64_OpSetLoInt16x32(v) + case OpSetLoInt32x16: + return rewriteValueAMD64_OpSetLoInt32x16(v) + case OpSetLoInt32x8: + return rewriteValueAMD64_OpSetLoInt32x8(v) + case OpSetLoInt64x4: + return rewriteValueAMD64_OpSetLoInt64x4(v) + case OpSetLoInt64x8: + return rewriteValueAMD64_OpSetLoInt64x8(v) + case OpSetLoInt8x32: + return rewriteValueAMD64_OpSetLoInt8x32(v) + case OpSetLoInt8x64: + return rewriteValueAMD64_OpSetLoInt8x64(v) + case OpSetLoUint16x16: + return rewriteValueAMD64_OpSetLoUint16x16(v) + case OpSetLoUint16x32: + return rewriteValueAMD64_OpSetLoUint16x32(v) + case OpSetLoUint32x16: + return rewriteValueAMD64_OpSetLoUint32x16(v) + case OpSetLoUint32x8: + return rewriteValueAMD64_OpSetLoUint32x8(v) + case OpSetLoUint64x4: + return rewriteValueAMD64_OpSetLoUint64x4(v) + case OpSetLoUint64x8: + return rewriteValueAMD64_OpSetLoUint64x8(v) + case OpSetLoUint8x32: + return rewriteValueAMD64_OpSetLoUint8x32(v) + case OpSetLoUint8x64: + return rewriteValueAMD64_OpSetLoUint8x64(v) + case OpShiftAllLeftConcatMod16Int16x16: + v.Op = OpAMD64VPSHLDW256 + return true + case OpShiftAllLeftConcatMod16Int16x32: + v.Op = OpAMD64VPSHLDW512 + return true + case OpShiftAllLeftConcatMod16Int16x8: + v.Op = OpAMD64VPSHLDW128 + return true + case OpShiftAllLeftConcatMod16Uint16x16: + v.Op = OpAMD64VPSHLDW256 + return true + case OpShiftAllLeftConcatMod16Uint16x32: + v.Op = OpAMD64VPSHLDW512 + return true + case OpShiftAllLeftConcatMod16Uint16x8: + v.Op = OpAMD64VPSHLDW128 + return true + case OpShiftAllLeftConcatMod32Int32x16: + v.Op = OpAMD64VPSHLDD512 + return true + case OpShiftAllLeftConcatMod32Int32x4: + v.Op = OpAMD64VPSHLDD128 + return true + case OpShiftAllLeftConcatMod32Int32x8: + v.Op = OpAMD64VPSHLDD256 + return true + case OpShiftAllLeftConcatMod32Uint32x16: + v.Op = OpAMD64VPSHLDD512 + return true + case OpShiftAllLeftConcatMod32Uint32x4: + v.Op = OpAMD64VPSHLDD128 + return true + case OpShiftAllLeftConcatMod32Uint32x8: + v.Op = OpAMD64VPSHLDD256 + return true + case OpShiftAllLeftConcatMod64Int64x2: + v.Op = OpAMD64VPSHLDQ128 + return true + case OpShiftAllLeftConcatMod64Int64x4: + v.Op = OpAMD64VPSHLDQ256 + return true + case OpShiftAllLeftConcatMod64Int64x8: + v.Op = OpAMD64VPSHLDQ512 + return true + case OpShiftAllLeftConcatMod64Uint64x2: + v.Op = OpAMD64VPSHLDQ128 + return true + case OpShiftAllLeftConcatMod64Uint64x4: + v.Op = OpAMD64VPSHLDQ256 + return true + case OpShiftAllLeftConcatMod64Uint64x8: + v.Op = OpAMD64VPSHLDQ512 + return true + case OpShiftAllLeftInt16x16: + v.Op = OpAMD64VPSLLW256 + return true + case OpShiftAllLeftInt16x32: + v.Op = OpAMD64VPSLLW512 + return true + case OpShiftAllLeftInt16x8: + v.Op = OpAMD64VPSLLW128 + return true + case OpShiftAllLeftInt32x16: + v.Op = OpAMD64VPSLLD512 + return true + case OpShiftAllLeftInt32x4: + v.Op = OpAMD64VPSLLD128 + return true + case OpShiftAllLeftInt32x8: + v.Op = OpAMD64VPSLLD256 + return true + case OpShiftAllLeftInt64x2: + v.Op = OpAMD64VPSLLQ128 + return true + case OpShiftAllLeftInt64x4: + v.Op = OpAMD64VPSLLQ256 + return true + case OpShiftAllLeftInt64x8: + v.Op = OpAMD64VPSLLQ512 + return true + case OpShiftAllLeftUint16x16: + v.Op = OpAMD64VPSLLW256 + return true + case OpShiftAllLeftUint16x32: + v.Op = OpAMD64VPSLLW512 + return true + case OpShiftAllLeftUint16x8: + v.Op = OpAMD64VPSLLW128 + return true + case OpShiftAllLeftUint32x16: + v.Op = OpAMD64VPSLLD512 + return true + case OpShiftAllLeftUint32x4: + v.Op = OpAMD64VPSLLD128 + return true + case OpShiftAllLeftUint32x8: + v.Op = OpAMD64VPSLLD256 + return true + case OpShiftAllLeftUint64x2: + v.Op = OpAMD64VPSLLQ128 + return true + case OpShiftAllLeftUint64x4: + v.Op = OpAMD64VPSLLQ256 + return true + case OpShiftAllLeftUint64x8: + v.Op = OpAMD64VPSLLQ512 + return true + case OpShiftAllRightConcatMod16Int16x16: + v.Op = OpAMD64VPSHRDW256 + return true + case OpShiftAllRightConcatMod16Int16x32: + v.Op = OpAMD64VPSHRDW512 + return true + case OpShiftAllRightConcatMod16Int16x8: + v.Op = OpAMD64VPSHRDW128 + return true + case OpShiftAllRightConcatMod16Uint16x16: + v.Op = OpAMD64VPSHRDW256 + return true + case OpShiftAllRightConcatMod16Uint16x32: + v.Op = OpAMD64VPSHRDW512 + return true + case OpShiftAllRightConcatMod16Uint16x8: + v.Op = OpAMD64VPSHRDW128 + return true + case OpShiftAllRightConcatMod32Int32x16: + v.Op = OpAMD64VPSHRDD512 + return true + case OpShiftAllRightConcatMod32Int32x4: + v.Op = OpAMD64VPSHRDD128 + return true + case OpShiftAllRightConcatMod32Int32x8: + v.Op = OpAMD64VPSHRDD256 + return true + case OpShiftAllRightConcatMod32Uint32x16: + v.Op = OpAMD64VPSHRDD512 + return true + case OpShiftAllRightConcatMod32Uint32x4: + v.Op = OpAMD64VPSHRDD128 + return true + case OpShiftAllRightConcatMod32Uint32x8: + v.Op = OpAMD64VPSHRDD256 + return true + case OpShiftAllRightConcatMod64Int64x2: + v.Op = OpAMD64VPSHRDQ128 + return true + case OpShiftAllRightConcatMod64Int64x4: + v.Op = OpAMD64VPSHRDQ256 + return true + case OpShiftAllRightConcatMod64Int64x8: + v.Op = OpAMD64VPSHRDQ512 + return true + case OpShiftAllRightConcatMod64Uint64x2: + v.Op = OpAMD64VPSHRDQ128 + return true + case OpShiftAllRightConcatMod64Uint64x4: + v.Op = OpAMD64VPSHRDQ256 + return true + case OpShiftAllRightConcatMod64Uint64x8: + v.Op = OpAMD64VPSHRDQ512 + return true + case OpShiftAllRightInt16x16: + v.Op = OpAMD64VPSRAW256 + return true + case OpShiftAllRightInt16x32: + v.Op = OpAMD64VPSRAW512 + return true + case OpShiftAllRightInt16x8: + v.Op = OpAMD64VPSRAW128 + return true + case OpShiftAllRightInt32x16: + v.Op = OpAMD64VPSRAD512 + return true + case OpShiftAllRightInt32x4: + v.Op = OpAMD64VPSRAD128 + return true + case OpShiftAllRightInt32x8: + v.Op = OpAMD64VPSRAD256 + return true + case OpShiftAllRightInt64x2: + v.Op = OpAMD64VPSRAQ128 + return true + case OpShiftAllRightInt64x4: + v.Op = OpAMD64VPSRAQ256 + return true + case OpShiftAllRightInt64x8: + v.Op = OpAMD64VPSRAQ512 + return true + case OpShiftAllRightUint16x16: + v.Op = OpAMD64VPSRLW256 + return true + case OpShiftAllRightUint16x32: + v.Op = OpAMD64VPSRLW512 + return true + case OpShiftAllRightUint16x8: + v.Op = OpAMD64VPSRLW128 + return true + case OpShiftAllRightUint32x16: + v.Op = OpAMD64VPSRLD512 + return true + case OpShiftAllRightUint32x4: + v.Op = OpAMD64VPSRLD128 + return true + case OpShiftAllRightUint32x8: + v.Op = OpAMD64VPSRLD256 + return true + case OpShiftAllRightUint64x2: + v.Op = OpAMD64VPSRLQ128 + return true + case OpShiftAllRightUint64x4: + v.Op = OpAMD64VPSRLQ256 + return true + case OpShiftAllRightUint64x8: + v.Op = OpAMD64VPSRLQ512 + return true + case OpShiftLeftConcatMod16Int16x16: + v.Op = OpAMD64VPSHLDVW256 + return true + case OpShiftLeftConcatMod16Int16x32: + v.Op = OpAMD64VPSHLDVW512 + return true + case OpShiftLeftConcatMod16Int16x8: + v.Op = OpAMD64VPSHLDVW128 + return true + case OpShiftLeftConcatMod16Uint16x16: + v.Op = OpAMD64VPSHLDVW256 + return true + case OpShiftLeftConcatMod16Uint16x32: + v.Op = OpAMD64VPSHLDVW512 + return true + case OpShiftLeftConcatMod16Uint16x8: + v.Op = OpAMD64VPSHLDVW128 + return true + case OpShiftLeftConcatMod32Int32x16: + v.Op = OpAMD64VPSHLDVD512 + return true + case OpShiftLeftConcatMod32Int32x4: + v.Op = OpAMD64VPSHLDVD128 + return true + case OpShiftLeftConcatMod32Int32x8: + v.Op = OpAMD64VPSHLDVD256 + return true + case OpShiftLeftConcatMod32Uint32x16: + v.Op = OpAMD64VPSHLDVD512 + return true + case OpShiftLeftConcatMod32Uint32x4: + v.Op = OpAMD64VPSHLDVD128 + return true + case OpShiftLeftConcatMod32Uint32x8: + v.Op = OpAMD64VPSHLDVD256 + return true + case OpShiftLeftConcatMod64Int64x2: + v.Op = OpAMD64VPSHLDVQ128 + return true + case OpShiftLeftConcatMod64Int64x4: + v.Op = OpAMD64VPSHLDVQ256 + return true + case OpShiftLeftConcatMod64Int64x8: + v.Op = OpAMD64VPSHLDVQ512 + return true + case OpShiftLeftConcatMod64Uint64x2: + v.Op = OpAMD64VPSHLDVQ128 + return true + case OpShiftLeftConcatMod64Uint64x4: + v.Op = OpAMD64VPSHLDVQ256 + return true + case OpShiftLeftConcatMod64Uint64x8: + v.Op = OpAMD64VPSHLDVQ512 + return true + case OpShiftLeftInt16x16: + v.Op = OpAMD64VPSLLVW256 + return true + case OpShiftLeftInt16x32: + v.Op = OpAMD64VPSLLVW512 + return true + case OpShiftLeftInt16x8: + v.Op = OpAMD64VPSLLVW128 + return true + case OpShiftLeftInt32x16: + v.Op = OpAMD64VPSLLVD512 + return true + case OpShiftLeftInt32x4: + v.Op = OpAMD64VPSLLVD128 + return true + case OpShiftLeftInt32x8: + v.Op = OpAMD64VPSLLVD256 + return true + case OpShiftLeftInt64x2: + v.Op = OpAMD64VPSLLVQ128 + return true + case OpShiftLeftInt64x4: + v.Op = OpAMD64VPSLLVQ256 + return true + case OpShiftLeftInt64x8: + v.Op = OpAMD64VPSLLVQ512 + return true + case OpShiftLeftUint16x16: + v.Op = OpAMD64VPSLLVW256 + return true + case OpShiftLeftUint16x32: + v.Op = OpAMD64VPSLLVW512 + return true + case OpShiftLeftUint16x8: + v.Op = OpAMD64VPSLLVW128 + return true + case OpShiftLeftUint32x16: + v.Op = OpAMD64VPSLLVD512 + return true + case OpShiftLeftUint32x4: + v.Op = OpAMD64VPSLLVD128 + return true + case OpShiftLeftUint32x8: + v.Op = OpAMD64VPSLLVD256 + return true + case OpShiftLeftUint64x2: + v.Op = OpAMD64VPSLLVQ128 + return true + case OpShiftLeftUint64x4: + v.Op = OpAMD64VPSLLVQ256 + return true + case OpShiftLeftUint64x8: + v.Op = OpAMD64VPSLLVQ512 + return true + case OpShiftRightConcatMod16Int16x16: + v.Op = OpAMD64VPSHRDVW256 + return true + case OpShiftRightConcatMod16Int16x32: + v.Op = OpAMD64VPSHRDVW512 + return true + case OpShiftRightConcatMod16Int16x8: + v.Op = OpAMD64VPSHRDVW128 + return true + case OpShiftRightConcatMod16Uint16x16: + v.Op = OpAMD64VPSHRDVW256 + return true + case OpShiftRightConcatMod16Uint16x32: + v.Op = OpAMD64VPSHRDVW512 + return true + case OpShiftRightConcatMod16Uint16x8: + v.Op = OpAMD64VPSHRDVW128 + return true + case OpShiftRightConcatMod32Int32x16: + v.Op = OpAMD64VPSHRDVD512 + return true + case OpShiftRightConcatMod32Int32x4: + v.Op = OpAMD64VPSHRDVD128 + return true + case OpShiftRightConcatMod32Int32x8: + v.Op = OpAMD64VPSHRDVD256 + return true + case OpShiftRightConcatMod32Uint32x16: + v.Op = OpAMD64VPSHRDVD512 + return true + case OpShiftRightConcatMod32Uint32x4: + v.Op = OpAMD64VPSHRDVD128 + return true + case OpShiftRightConcatMod32Uint32x8: + v.Op = OpAMD64VPSHRDVD256 + return true + case OpShiftRightConcatMod64Int64x2: + v.Op = OpAMD64VPSHRDVQ128 + return true + case OpShiftRightConcatMod64Int64x4: + v.Op = OpAMD64VPSHRDVQ256 + return true + case OpShiftRightConcatMod64Int64x8: + v.Op = OpAMD64VPSHRDVQ512 + return true + case OpShiftRightConcatMod64Uint64x2: + v.Op = OpAMD64VPSHRDVQ128 + return true + case OpShiftRightConcatMod64Uint64x4: + v.Op = OpAMD64VPSHRDVQ256 + return true + case OpShiftRightConcatMod64Uint64x8: + v.Op = OpAMD64VPSHRDVQ512 + return true + case OpShiftRightInt16x16: + v.Op = OpAMD64VPSRAVW256 + return true + case OpShiftRightInt16x32: + v.Op = OpAMD64VPSRAVW512 + return true + case OpShiftRightInt16x8: + v.Op = OpAMD64VPSRAVW128 + return true + case OpShiftRightInt32x16: + v.Op = OpAMD64VPSRAVD512 + return true + case OpShiftRightInt32x4: + v.Op = OpAMD64VPSRAVD128 + return true + case OpShiftRightInt32x8: + v.Op = OpAMD64VPSRAVD256 + return true + case OpShiftRightInt64x2: + v.Op = OpAMD64VPSRAVQ128 + return true + case OpShiftRightInt64x4: + v.Op = OpAMD64VPSRAVQ256 + return true + case OpShiftRightInt64x8: + v.Op = OpAMD64VPSRAVQ512 + return true + case OpShiftRightUint16x16: + v.Op = OpAMD64VPSRLVW256 + return true + case OpShiftRightUint16x32: + v.Op = OpAMD64VPSRLVW512 + return true + case OpShiftRightUint16x8: + v.Op = OpAMD64VPSRLVW128 + return true + case OpShiftRightUint32x16: + v.Op = OpAMD64VPSRLVD512 + return true + case OpShiftRightUint32x4: + v.Op = OpAMD64VPSRLVD128 + return true + case OpShiftRightUint32x8: + v.Op = OpAMD64VPSRLVD256 + return true + case OpShiftRightUint64x2: + v.Op = OpAMD64VPSRLVQ128 + return true + case OpShiftRightUint64x4: + v.Op = OpAMD64VPSRLVQ256 + return true + case OpShiftRightUint64x8: + v.Op = OpAMD64VPSRLVQ512 + return true case OpSignExt16to32: v.Op = OpAMD64MOVWQSX return true @@ -1118,11 +6708,37 @@ func rewriteValueAMD64(v *Value) bool { case OpSqrt32: v.Op = OpAMD64SQRTSS return true + case OpSqrtFloat32x16: + v.Op = OpAMD64VSQRTPS512 + return true + case OpSqrtFloat32x4: + v.Op = OpAMD64VSQRTPS128 + return true + case OpSqrtFloat32x8: + v.Op = OpAMD64VSQRTPS256 + return true + case OpSqrtFloat64x2: + v.Op = OpAMD64VSQRTPD128 + return true + case OpSqrtFloat64x4: + v.Op = OpAMD64VSQRTPD256 + return true + case OpSqrtFloat64x8: + v.Op = OpAMD64VSQRTPD512 + return true case OpStaticCall: v.Op = OpAMD64CALLstatic return true case OpStore: return rewriteValueAMD64_OpStore(v) + case OpStoreMasked16: + return rewriteValueAMD64_OpStoreMasked16(v) + case OpStoreMasked32: + return rewriteValueAMD64_OpStoreMasked32(v) + case OpStoreMasked64: + return rewriteValueAMD64_OpStoreMasked64(v) + case OpStoreMasked8: + return rewriteValueAMD64_OpStoreMasked8(v) case OpSub16: v.Op = OpAMD64SUBL return true @@ -1141,12 +6757,150 @@ func rewriteValueAMD64(v *Value) bool { case OpSub8: v.Op = OpAMD64SUBL return true + case OpSubFloat32x16: + v.Op = OpAMD64VSUBPS512 + return true + case OpSubFloat32x4: + v.Op = OpAMD64VSUBPS128 + return true + case OpSubFloat32x8: + v.Op = OpAMD64VSUBPS256 + return true + case OpSubFloat64x2: + v.Op = OpAMD64VSUBPD128 + return true + case OpSubFloat64x4: + v.Op = OpAMD64VSUBPD256 + return true + case OpSubFloat64x8: + v.Op = OpAMD64VSUBPD512 + return true + case OpSubInt16x16: + v.Op = OpAMD64VPSUBW256 + return true + case OpSubInt16x32: + v.Op = OpAMD64VPSUBW512 + return true + case OpSubInt16x8: + v.Op = OpAMD64VPSUBW128 + return true + case OpSubInt32x16: + v.Op = OpAMD64VPSUBD512 + return true + case OpSubInt32x4: + v.Op = OpAMD64VPSUBD128 + return true + case OpSubInt32x8: + v.Op = OpAMD64VPSUBD256 + return true + case OpSubInt64x2: + v.Op = OpAMD64VPSUBQ128 + return true + case OpSubInt64x4: + v.Op = OpAMD64VPSUBQ256 + return true + case OpSubInt64x8: + v.Op = OpAMD64VPSUBQ512 + return true + case OpSubInt8x16: + v.Op = OpAMD64VPSUBB128 + return true + case OpSubInt8x32: + v.Op = OpAMD64VPSUBB256 + return true + case OpSubInt8x64: + v.Op = OpAMD64VPSUBB512 + return true case OpSubPtr: v.Op = OpAMD64SUBQ return true + case OpSubSaturatedInt16x16: + v.Op = OpAMD64VPSUBSW256 + return true + case OpSubSaturatedInt16x32: + v.Op = OpAMD64VPSUBSW512 + return true + case OpSubSaturatedInt16x8: + v.Op = OpAMD64VPSUBSW128 + return true + case OpSubSaturatedInt8x16: + v.Op = OpAMD64VPSUBSB128 + return true + case OpSubSaturatedInt8x32: + v.Op = OpAMD64VPSUBSB256 + return true + case OpSubSaturatedInt8x64: + v.Op = OpAMD64VPSUBSB512 + return true + case OpSubSaturatedUint16x16: + v.Op = OpAMD64VPSUBUSW256 + return true + case OpSubSaturatedUint16x32: + v.Op = OpAMD64VPSUBUSW512 + return true + case OpSubSaturatedUint16x8: + v.Op = OpAMD64VPSUBUSW128 + return true + case OpSubSaturatedUint8x16: + v.Op = OpAMD64VPSUBUSB128 + return true + case OpSubSaturatedUint8x32: + v.Op = OpAMD64VPSUBUSB256 + return true + case OpSubSaturatedUint8x64: + v.Op = OpAMD64VPSUBUSB512 + return true + case OpSubUint16x16: + v.Op = OpAMD64VPSUBW256 + return true + case OpSubUint16x32: + v.Op = OpAMD64VPSUBW512 + return true + case OpSubUint16x8: + v.Op = OpAMD64VPSUBW128 + return true + case OpSubUint32x16: + v.Op = OpAMD64VPSUBD512 + return true + case OpSubUint32x4: + v.Op = OpAMD64VPSUBD128 + return true + case OpSubUint32x8: + v.Op = OpAMD64VPSUBD256 + return true + case OpSubUint64x2: + v.Op = OpAMD64VPSUBQ128 + return true + case OpSubUint64x4: + v.Op = OpAMD64VPSUBQ256 + return true + case OpSubUint64x8: + v.Op = OpAMD64VPSUBQ512 + return true + case OpSubUint8x16: + v.Op = OpAMD64VPSUBB128 + return true + case OpSubUint8x32: + v.Op = OpAMD64VPSUBB256 + return true + case OpSubUint8x64: + v.Op = OpAMD64VPSUBB512 + return true + case OpSumOf8AbsDiffUint8x16: + v.Op = OpAMD64VPSADBW128 + return true + case OpSumOf8AbsDiffUint8x32: + v.Op = OpAMD64VPSADBW256 + return true + case OpSumOf8AbsDiffUint8x64: + v.Op = OpAMD64VPSADBW512 + return true case OpTailCall: v.Op = OpAMD64CALLtail return true + case OpTailCallInter: + v.Op = OpAMD64CALLtailinter + return true case OpTrunc: return rewriteValueAMD64_OpTrunc(v) case OpTrunc16to8: @@ -1167,6 +6921,146 @@ func rewriteValueAMD64(v *Value) bool { case OpTrunc64to8: v.Op = OpCopy return true + case OpTruncFloat32x4: + return rewriteValueAMD64_OpTruncFloat32x4(v) + case OpTruncFloat32x8: + return rewriteValueAMD64_OpTruncFloat32x8(v) + case OpTruncFloat64x2: + return rewriteValueAMD64_OpTruncFloat64x2(v) + case OpTruncFloat64x4: + return rewriteValueAMD64_OpTruncFloat64x4(v) + case OpTruncScaledFloat32x16: + return rewriteValueAMD64_OpTruncScaledFloat32x16(v) + case OpTruncScaledFloat32x4: + return rewriteValueAMD64_OpTruncScaledFloat32x4(v) + case OpTruncScaledFloat32x8: + return rewriteValueAMD64_OpTruncScaledFloat32x8(v) + case OpTruncScaledFloat64x2: + return rewriteValueAMD64_OpTruncScaledFloat64x2(v) + case OpTruncScaledFloat64x4: + return rewriteValueAMD64_OpTruncScaledFloat64x4(v) + case OpTruncScaledFloat64x8: + return rewriteValueAMD64_OpTruncScaledFloat64x8(v) + case OpTruncScaledResidueFloat32x16: + return rewriteValueAMD64_OpTruncScaledResidueFloat32x16(v) + case OpTruncScaledResidueFloat32x4: + return rewriteValueAMD64_OpTruncScaledResidueFloat32x4(v) + case OpTruncScaledResidueFloat32x8: + return rewriteValueAMD64_OpTruncScaledResidueFloat32x8(v) + case OpTruncScaledResidueFloat64x2: + return rewriteValueAMD64_OpTruncScaledResidueFloat64x2(v) + case OpTruncScaledResidueFloat64x4: + return rewriteValueAMD64_OpTruncScaledResidueFloat64x4(v) + case OpTruncScaledResidueFloat64x8: + return rewriteValueAMD64_OpTruncScaledResidueFloat64x8(v) + case OpTruncToInt16Int32x16: + v.Op = OpAMD64VPMOVDW256 + return true + case OpTruncToInt16Int32x4: + v.Op = OpAMD64VPMOVDW128_128 + return true + case OpTruncToInt16Int32x8: + v.Op = OpAMD64VPMOVDW128_256 + return true + case OpTruncToInt16Int64x2: + v.Op = OpAMD64VPMOVQW128_128 + return true + case OpTruncToInt16Int64x4: + v.Op = OpAMD64VPMOVQW128_256 + return true + case OpTruncToInt16Int64x8: + v.Op = OpAMD64VPMOVQW128_512 + return true + case OpTruncToInt32Int64x2: + v.Op = OpAMD64VPMOVQD128_128 + return true + case OpTruncToInt32Int64x4: + v.Op = OpAMD64VPMOVQD128_256 + return true + case OpTruncToInt32Int64x8: + v.Op = OpAMD64VPMOVQD256 + return true + case OpTruncToInt8Int16x16: + v.Op = OpAMD64VPMOVWB128_256 + return true + case OpTruncToInt8Int16x32: + v.Op = OpAMD64VPMOVWB256 + return true + case OpTruncToInt8Int16x8: + v.Op = OpAMD64VPMOVWB128_128 + return true + case OpTruncToInt8Int32x16: + v.Op = OpAMD64VPMOVDB128_512 + return true + case OpTruncToInt8Int32x4: + v.Op = OpAMD64VPMOVDB128_128 + return true + case OpTruncToInt8Int32x8: + v.Op = OpAMD64VPMOVDB128_256 + return true + case OpTruncToInt8Int64x2: + v.Op = OpAMD64VPMOVQB128_128 + return true + case OpTruncToInt8Int64x4: + v.Op = OpAMD64VPMOVQB128_256 + return true + case OpTruncToInt8Int64x8: + v.Op = OpAMD64VPMOVQB128_512 + return true + case OpTruncToUint16Uint32x16: + v.Op = OpAMD64VPMOVDW256 + return true + case OpTruncToUint16Uint32x4: + v.Op = OpAMD64VPMOVDW128_128 + return true + case OpTruncToUint16Uint32x8: + v.Op = OpAMD64VPMOVDW128_256 + return true + case OpTruncToUint16Uint64x2: + v.Op = OpAMD64VPMOVQW128_128 + return true + case OpTruncToUint16Uint64x4: + v.Op = OpAMD64VPMOVQW128_256 + return true + case OpTruncToUint16Uint64x8: + v.Op = OpAMD64VPMOVQW128_512 + return true + case OpTruncToUint32Uint64x2: + v.Op = OpAMD64VPMOVQD128_128 + return true + case OpTruncToUint32Uint64x4: + v.Op = OpAMD64VPMOVQD128_256 + return true + case OpTruncToUint32Uint64x8: + v.Op = OpAMD64VPMOVQD256 + return true + case OpTruncToUint8Uint16x16: + v.Op = OpAMD64VPMOVWB128_256 + return true + case OpTruncToUint8Uint16x32: + v.Op = OpAMD64VPMOVWB256 + return true + case OpTruncToUint8Uint16x8: + v.Op = OpAMD64VPMOVWB128_128 + return true + case OpTruncToUint8Uint32x16: + v.Op = OpAMD64VPMOVDB128_512 + return true + case OpTruncToUint8Uint32x4: + v.Op = OpAMD64VPMOVDB128_128 + return true + case OpTruncToUint8Uint32x8: + v.Op = OpAMD64VPMOVDB128_256 + return true + case OpTruncToUint8Uint64x2: + v.Op = OpAMD64VPMOVQB128_128 + return true + case OpTruncToUint8Uint64x4: + v.Op = OpAMD64VPMOVQB128_256 + return true + case OpTruncToUint8Uint64x8: + v.Op = OpAMD64VPMOVQB128_512 + return true case OpWB: v.Op = OpAMD64LoweredWB return true @@ -1182,18 +7076,90 @@ func rewriteValueAMD64(v *Value) bool { case OpXor8: v.Op = OpAMD64XORL return true - case OpZero: - return rewriteValueAMD64_OpZero(v) - case OpZeroExt16to32: - v.Op = OpAMD64MOVWQZX + case OpXorInt16x16: + v.Op = OpAMD64VPXOR256 return true - case OpZeroExt16to64: - v.Op = OpAMD64MOVWQZX + case OpXorInt16x32: + v.Op = OpAMD64VPXORD512 return true - case OpZeroExt32to64: - v.Op = OpAMD64MOVLQZX + case OpXorInt16x8: + v.Op = OpAMD64VPXOR128 return true - case OpZeroExt8to16: + case OpXorInt32x16: + v.Op = OpAMD64VPXORD512 + return true + case OpXorInt32x4: + v.Op = OpAMD64VPXOR128 + return true + case OpXorInt32x8: + v.Op = OpAMD64VPXOR256 + return true + case OpXorInt64x2: + v.Op = OpAMD64VPXOR128 + return true + case OpXorInt64x4: + v.Op = OpAMD64VPXOR256 + return true + case OpXorInt64x8: + v.Op = OpAMD64VPXORQ512 + return true + case OpXorInt8x16: + v.Op = OpAMD64VPXOR128 + return true + case OpXorInt8x32: + v.Op = OpAMD64VPXOR256 + return true + case OpXorInt8x64: + v.Op = OpAMD64VPXORD512 + return true + case OpXorUint16x16: + v.Op = OpAMD64VPXOR256 + return true + case OpXorUint16x32: + v.Op = OpAMD64VPXORD512 + return true + case OpXorUint16x8: + v.Op = OpAMD64VPXOR128 + return true + case OpXorUint32x16: + v.Op = OpAMD64VPXORD512 + return true + case OpXorUint32x4: + v.Op = OpAMD64VPXOR128 + return true + case OpXorUint32x8: + v.Op = OpAMD64VPXOR256 + return true + case OpXorUint64x2: + v.Op = OpAMD64VPXOR128 + return true + case OpXorUint64x4: + v.Op = OpAMD64VPXOR256 + return true + case OpXorUint64x8: + v.Op = OpAMD64VPXORQ512 + return true + case OpXorUint8x16: + v.Op = OpAMD64VPXOR128 + return true + case OpXorUint8x32: + v.Op = OpAMD64VPXOR256 + return true + case OpXorUint8x64: + v.Op = OpAMD64VPXORD512 + return true + case OpZero: + return rewriteValueAMD64_OpZero(v) + case OpZeroExt16to32: + v.Op = OpAMD64MOVWQZX + return true + case OpZeroExt16to64: + v.Op = OpAMD64MOVWQZX + return true + case OpZeroExt32to64: + v.Op = OpAMD64MOVLQZX + return true + case OpZeroExt8to16: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to32: @@ -1202,6 +7168,325 @@ func rewriteValueAMD64(v *Value) bool { case OpZeroExt8to64: v.Op = OpAMD64MOVBQZX return true + case OpZeroSIMD: + return rewriteValueAMD64_OpZeroSIMD(v) + case OpblendInt8x16: + v.Op = OpAMD64VPBLENDVB128 + return true + case OpblendInt8x32: + v.Op = OpAMD64VPBLENDVB256 + return true + case OpblendMaskedInt16x32: + return rewriteValueAMD64_OpblendMaskedInt16x32(v) + case OpblendMaskedInt32x16: + return rewriteValueAMD64_OpblendMaskedInt32x16(v) + case OpblendMaskedInt64x8: + return rewriteValueAMD64_OpblendMaskedInt64x8(v) + case OpblendMaskedInt8x64: + return rewriteValueAMD64_OpblendMaskedInt8x64(v) + case Opbroadcast1To16Float32x4: + v.Op = OpAMD64VBROADCASTSS512 + return true + case Opbroadcast1To16Int16x8: + v.Op = OpAMD64VPBROADCASTW256 + return true + case Opbroadcast1To16Int32x4: + v.Op = OpAMD64VPBROADCASTD512 + return true + case Opbroadcast1To16Int8x16: + v.Op = OpAMD64VPBROADCASTB128 + return true + case Opbroadcast1To16MaskedFloat32x4: + return rewriteValueAMD64_Opbroadcast1To16MaskedFloat32x4(v) + case Opbroadcast1To16MaskedInt16x8: + return rewriteValueAMD64_Opbroadcast1To16MaskedInt16x8(v) + case Opbroadcast1To16MaskedInt32x4: + return rewriteValueAMD64_Opbroadcast1To16MaskedInt32x4(v) + case Opbroadcast1To16MaskedInt8x16: + return rewriteValueAMD64_Opbroadcast1To16MaskedInt8x16(v) + case Opbroadcast1To16MaskedUint16x8: + return rewriteValueAMD64_Opbroadcast1To16MaskedUint16x8(v) + case Opbroadcast1To16MaskedUint32x4: + return rewriteValueAMD64_Opbroadcast1To16MaskedUint32x4(v) + case Opbroadcast1To16MaskedUint8x16: + return rewriteValueAMD64_Opbroadcast1To16MaskedUint8x16(v) + case Opbroadcast1To16Uint16x8: + v.Op = OpAMD64VPBROADCASTW256 + return true + case Opbroadcast1To16Uint32x4: + v.Op = OpAMD64VPBROADCASTD512 + return true + case Opbroadcast1To16Uint8x16: + v.Op = OpAMD64VPBROADCASTB128 + return true + case Opbroadcast1To2Float64x2: + v.Op = OpAMD64VPBROADCASTQ128 + return true + case Opbroadcast1To2Int64x2: + v.Op = OpAMD64VPBROADCASTQ128 + return true + case Opbroadcast1To2MaskedFloat64x2: + return rewriteValueAMD64_Opbroadcast1To2MaskedFloat64x2(v) + case Opbroadcast1To2MaskedInt64x2: + return rewriteValueAMD64_Opbroadcast1To2MaskedInt64x2(v) + case Opbroadcast1To2MaskedUint64x2: + return rewriteValueAMD64_Opbroadcast1To2MaskedUint64x2(v) + case Opbroadcast1To2Uint64x2: + v.Op = OpAMD64VPBROADCASTQ128 + return true + case Opbroadcast1To32Int16x8: + v.Op = OpAMD64VPBROADCASTW512 + return true + case Opbroadcast1To32Int8x16: + v.Op = OpAMD64VPBROADCASTB256 + return true + case Opbroadcast1To32MaskedInt16x8: + return rewriteValueAMD64_Opbroadcast1To32MaskedInt16x8(v) + case Opbroadcast1To32MaskedInt8x16: + return rewriteValueAMD64_Opbroadcast1To32MaskedInt8x16(v) + case Opbroadcast1To32MaskedUint16x8: + return rewriteValueAMD64_Opbroadcast1To32MaskedUint16x8(v) + case Opbroadcast1To32MaskedUint8x16: + return rewriteValueAMD64_Opbroadcast1To32MaskedUint8x16(v) + case Opbroadcast1To32Uint16x8: + v.Op = OpAMD64VPBROADCASTW512 + return true + case Opbroadcast1To32Uint8x16: + v.Op = OpAMD64VPBROADCASTB256 + return true + case Opbroadcast1To4Float32x4: + v.Op = OpAMD64VBROADCASTSS128 + return true + case Opbroadcast1To4Float64x2: + v.Op = OpAMD64VBROADCASTSD256 + return true + case Opbroadcast1To4Int32x4: + v.Op = OpAMD64VPBROADCASTD128 + return true + case Opbroadcast1To4Int64x2: + v.Op = OpAMD64VPBROADCASTQ256 + return true + case Opbroadcast1To4MaskedFloat32x4: + return rewriteValueAMD64_Opbroadcast1To4MaskedFloat32x4(v) + case Opbroadcast1To4MaskedFloat64x2: + return rewriteValueAMD64_Opbroadcast1To4MaskedFloat64x2(v) + case Opbroadcast1To4MaskedInt32x4: + return rewriteValueAMD64_Opbroadcast1To4MaskedInt32x4(v) + case Opbroadcast1To4MaskedInt64x2: + return rewriteValueAMD64_Opbroadcast1To4MaskedInt64x2(v) + case Opbroadcast1To4MaskedUint32x4: + return rewriteValueAMD64_Opbroadcast1To4MaskedUint32x4(v) + case Opbroadcast1To4MaskedUint64x2: + return rewriteValueAMD64_Opbroadcast1To4MaskedUint64x2(v) + case Opbroadcast1To4Uint32x4: + v.Op = OpAMD64VPBROADCASTD128 + return true + case Opbroadcast1To4Uint64x2: + v.Op = OpAMD64VPBROADCASTQ256 + return true + case Opbroadcast1To64Int8x16: + v.Op = OpAMD64VPBROADCASTB512 + return true + case Opbroadcast1To64MaskedInt8x16: + return rewriteValueAMD64_Opbroadcast1To64MaskedInt8x16(v) + case Opbroadcast1To64MaskedUint8x16: + return rewriteValueAMD64_Opbroadcast1To64MaskedUint8x16(v) + case Opbroadcast1To64Uint8x16: + v.Op = OpAMD64VPBROADCASTB512 + return true + case Opbroadcast1To8Float32x4: + v.Op = OpAMD64VBROADCASTSS256 + return true + case Opbroadcast1To8Float64x2: + v.Op = OpAMD64VBROADCASTSD512 + return true + case Opbroadcast1To8Int16x8: + v.Op = OpAMD64VPBROADCASTW128 + return true + case Opbroadcast1To8Int32x4: + v.Op = OpAMD64VPBROADCASTD256 + return true + case Opbroadcast1To8Int64x2: + v.Op = OpAMD64VPBROADCASTQ512 + return true + case Opbroadcast1To8MaskedFloat32x4: + return rewriteValueAMD64_Opbroadcast1To8MaskedFloat32x4(v) + case Opbroadcast1To8MaskedFloat64x2: + return rewriteValueAMD64_Opbroadcast1To8MaskedFloat64x2(v) + case Opbroadcast1To8MaskedInt16x8: + return rewriteValueAMD64_Opbroadcast1To8MaskedInt16x8(v) + case Opbroadcast1To8MaskedInt32x4: + return rewriteValueAMD64_Opbroadcast1To8MaskedInt32x4(v) + case Opbroadcast1To8MaskedInt64x2: + return rewriteValueAMD64_Opbroadcast1To8MaskedInt64x2(v) + case Opbroadcast1To8MaskedUint16x8: + return rewriteValueAMD64_Opbroadcast1To8MaskedUint16x8(v) + case Opbroadcast1To8MaskedUint32x4: + return rewriteValueAMD64_Opbroadcast1To8MaskedUint32x4(v) + case Opbroadcast1To8MaskedUint64x2: + return rewriteValueAMD64_Opbroadcast1To8MaskedUint64x2(v) + case Opbroadcast1To8Uint16x8: + v.Op = OpAMD64VPBROADCASTW128 + return true + case Opbroadcast1To8Uint32x4: + v.Op = OpAMD64VPBROADCASTD256 + return true + case Opbroadcast1To8Uint64x2: + v.Op = OpAMD64VPBROADCASTQ512 + return true + case OpcarrylessMultiplyUint64x2: + v.Op = OpAMD64VPCLMULQDQ128 + return true + case OpcarrylessMultiplyUint64x4: + v.Op = OpAMD64VPCLMULQDQ256 + return true + case OpcarrylessMultiplyUint64x8: + v.Op = OpAMD64VPCLMULQDQ512 + return true + case OpconcatSelectedConstantFloat32x4: + v.Op = OpAMD64VSHUFPS128 + return true + case OpconcatSelectedConstantFloat64x2: + v.Op = OpAMD64VSHUFPD128 + return true + case OpconcatSelectedConstantGroupedFloat32x16: + v.Op = OpAMD64VSHUFPS512 + return true + case OpconcatSelectedConstantGroupedFloat32x8: + v.Op = OpAMD64VSHUFPS256 + return true + case OpconcatSelectedConstantGroupedFloat64x4: + v.Op = OpAMD64VSHUFPD256 + return true + case OpconcatSelectedConstantGroupedFloat64x8: + v.Op = OpAMD64VSHUFPD512 + return true + case OpconcatSelectedConstantGroupedInt32x16: + v.Op = OpAMD64VSHUFPS512 + return true + case OpconcatSelectedConstantGroupedInt32x8: + v.Op = OpAMD64VSHUFPS256 + return true + case OpconcatSelectedConstantGroupedInt64x4: + v.Op = OpAMD64VSHUFPD256 + return true + case OpconcatSelectedConstantGroupedInt64x8: + v.Op = OpAMD64VSHUFPD512 + return true + case OpconcatSelectedConstantGroupedUint32x16: + v.Op = OpAMD64VSHUFPS512 + return true + case OpconcatSelectedConstantGroupedUint32x8: + v.Op = OpAMD64VSHUFPS256 + return true + case OpconcatSelectedConstantGroupedUint64x4: + v.Op = OpAMD64VSHUFPD256 + return true + case OpconcatSelectedConstantGroupedUint64x8: + v.Op = OpAMD64VSHUFPD512 + return true + case OpconcatSelectedConstantInt32x4: + v.Op = OpAMD64VSHUFPS128 + return true + case OpconcatSelectedConstantInt64x2: + v.Op = OpAMD64VSHUFPD128 + return true + case OpconcatSelectedConstantUint32x4: + v.Op = OpAMD64VSHUFPS128 + return true + case OpconcatSelectedConstantUint64x2: + v.Op = OpAMD64VSHUFPD128 + return true + case OppermuteScalarsGroupedInt32x16: + v.Op = OpAMD64VPSHUFD512 + return true + case OppermuteScalarsGroupedInt32x8: + v.Op = OpAMD64VPSHUFD256 + return true + case OppermuteScalarsGroupedUint32x16: + v.Op = OpAMD64VPSHUFD512 + return true + case OppermuteScalarsGroupedUint32x8: + v.Op = OpAMD64VPSHUFD256 + return true + case OppermuteScalarsHiGroupedInt16x16: + v.Op = OpAMD64VPSHUFHW256 + return true + case OppermuteScalarsHiGroupedInt16x32: + v.Op = OpAMD64VPSHUFHW512 + return true + case OppermuteScalarsHiGroupedUint16x16: + v.Op = OpAMD64VPSHUFHW256 + return true + case OppermuteScalarsHiGroupedUint16x32: + v.Op = OpAMD64VPSHUFHW512 + return true + case OppermuteScalarsHiInt16x8: + v.Op = OpAMD64VPSHUFHW128 + return true + case OppermuteScalarsHiUint16x8: + v.Op = OpAMD64VPSHUFHW128 + return true + case OppermuteScalarsInt32x4: + v.Op = OpAMD64VPSHUFD128 + return true + case OppermuteScalarsLoGroupedInt16x16: + v.Op = OpAMD64VPSHUFLW256 + return true + case OppermuteScalarsLoGroupedInt16x32: + v.Op = OpAMD64VPSHUFLW512 + return true + case OppermuteScalarsLoGroupedUint16x16: + v.Op = OpAMD64VPSHUFLW256 + return true + case OppermuteScalarsLoGroupedUint16x32: + v.Op = OpAMD64VPSHUFLW512 + return true + case OppermuteScalarsLoInt16x8: + v.Op = OpAMD64VPSHUFLW128 + return true + case OppermuteScalarsLoUint16x8: + v.Op = OpAMD64VPSHUFLW128 + return true + case OppermuteScalarsUint32x4: + v.Op = OpAMD64VPSHUFD128 + return true + case OpternInt32x16: + v.Op = OpAMD64VPTERNLOGD512 + return true + case OpternInt32x4: + v.Op = OpAMD64VPTERNLOGD128 + return true + case OpternInt32x8: + v.Op = OpAMD64VPTERNLOGD256 + return true + case OpternInt64x2: + v.Op = OpAMD64VPTERNLOGQ128 + return true + case OpternInt64x4: + v.Op = OpAMD64VPTERNLOGQ256 + return true + case OpternInt64x8: + v.Op = OpAMD64VPTERNLOGQ512 + return true + case OpternUint32x16: + v.Op = OpAMD64VPTERNLOGD512 + return true + case OpternUint32x4: + v.Op = OpAMD64VPTERNLOGD128 + return true + case OpternUint32x8: + v.Op = OpAMD64VPTERNLOGD256 + return true + case OpternUint64x2: + v.Op = OpAMD64VPTERNLOGQ128 + return true + case OpternUint64x4: + v.Op = OpAMD64VPTERNLOGQ256 + return true + case OpternUint64x8: + v.Op = OpAMD64VPTERNLOGQ512 + return true } return false } @@ -1209,6 +7494,8 @@ func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [int32(c)] carry) @@ -1242,11 +7529,34 @@ func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { v.AddArg2(x, y) return true } + // match: (ADCQ x y (InvertFlags f)) + // result: (ADCQ x y (Select1 (NEGLflags (MOVBQZX (SETA f))))) + for { + x := v_0 + y := v_1 + if v_2.Op != OpAMD64InvertFlags { + break + } + f := v_2.Args[0] + v.reset(OpAMD64ADCQ) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, types.Types[types.TUINT32]) + v3 := b.NewValue0(v.Pos, OpAMD64SETA, types.Types[types.TUINT8]) + v3.AddArg(f) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg3(x, y, v0) + return true + } return false } func rewriteValueAMD64_OpAMD64ADCQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { @@ -1260,6 +7570,28 @@ func rewriteValueAMD64_OpAMD64ADCQconst(v *Value) bool { v.AddArg(x) return true } + // match: (ADCQconst x [c] (InvertFlags f)) + // result: (ADCQconst x [c] (Select1 (NEGLflags (MOVBQZX (SETA f))))) + for { + c := auxIntToInt32(v.AuxInt) + x := v_0 + if v_1.Op != OpAMD64InvertFlags { + break + } + f := v_1.Args[0] + v.reset(OpAMD64ADCQconst) + v.AuxInt = int32ToAuxInt(c) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, types.Types[types.TUINT32]) + v3 := b.NewValue0(v.Pos, OpAMD64SETA, types.Types[types.TUINT8]) + v3.AddArg(f) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } return false } func rewriteValueAMD64_OpAMD64ADDL(v *Value) bool { @@ -1585,15 +7917,13 @@ func rewriteValueAMD64_OpAMD64ADDLconst(v *Value) bool { v.AddArg2(x, y) return true } - // match: (ADDLconst [c] x) - // cond: c==0 + // match: (ADDLconst [0] x) // result: x for { - c := auxIntToInt32(v.AuxInt) - x := v_0 - if !(c == 0) { + if auxIntToInt32(v.AuxInt) != 0 { break } + x := v_0 v.copyOf(x) return true } @@ -2824,27 +9154,23 @@ func rewriteValueAMD64_OpAMD64ANDLconst(v *Value) bool { v.AddArg(x) return true } - // match: (ANDLconst [c] _) - // cond: c==0 + // match: (ANDLconst [0] _) // result: (MOVLconst [0]) for { - c := auxIntToInt32(v.AuxInt) - if !(c == 0) { + if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } - // match: (ANDLconst [c] x) - // cond: c==-1 + // match: (ANDLconst [-1] x) // result: x for { - c := auxIntToInt32(v.AuxInt) - x := v_0 - if !(c == -1) { + if auxIntToInt32(v.AuxInt) != -1 { break } + x := v_0 v.copyOf(x) return true } @@ -3105,7 +9431,7 @@ func rewriteValueAMD64_OpAMD64ANDQ(v *Value) bool { break } // match: (ANDQ (MOVQconst [c]) x) - // cond: isUnsignedPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31 + // cond: isPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31 // result: (BTRQconst [int8(log64u(uint64(^c)))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { @@ -3114,7 +9440,7 @@ func rewriteValueAMD64_OpAMD64ANDQ(v *Value) bool { } c := auxIntToInt64(v_0.AuxInt) x := v_1 - if !(isUnsignedPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31) { + if !(isPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31) { continue } v.reset(OpAMD64BTRQconst) @@ -3273,13 +9599,13 @@ func rewriteValueAMD64_OpAMD64ANDQconst(v *Value) bool { return true } // match: (ANDQconst [0] _) - // result: (MOVQconst [0]) + // result: (MOVLconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(0) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } // match: (ANDQconst [-1] x) @@ -4244,403 +10570,1255 @@ func rewriteValueAMD64_OpAMD64CMOVLEQ(v *Value) bool { } break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVLGE(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (CMOVLGE x y (InvertFlags cond)) - // result: (CMOVLLE x y cond) + // match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLNE yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVLLE) - v.AddArg3(x, y, cond) - return true - } - // match: (CMOVLGE _ x (FlagEQ)) - // result: x - for { - x := v_1 - if v_2.Op != OpAMD64FlagEQ { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNE) + v.AddArg3(yes, no, flags) + return true } - v.copyOf(x) - return true + break } - // match: (CMOVLGE _ x (FlagGT_UGT)) - // result: x + // match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLEQ yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLGE _ x (FlagGT_ULT)) - // result: x + // match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLGE y _ (FlagLT_ULT)) - // result: y + // match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLE yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLGE y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGT yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLGE x y c:(CMPQconst [128] z)) - // cond: c.Uses == 1 - // result: (CMOVLGT x y (CMPQconst [127] z)) + // match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLT yes no flags) for { - x := v_0 - y := v_1 - c := v_2 - if c.Op != OpAMD64CMPQconst || auxIntToInt32(c.AuxInt) != 128 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - z := c.Args[0] - if !(c.Uses == 1) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMOVLGT) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(z) - v.AddArg3(x, y, v0) - return true + break } - // match: (CMOVLGE x y c:(CMPLconst [128] z)) - // cond: c.Uses == 1 - // result: (CMOVLGT x y (CMPLconst [127] z)) + // match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLS yes no flags) for { - x := v_0 - y := v_1 - c := v_2 - if c.Op != OpAMD64CMPLconst || auxIntToInt32(c.AuxInt) != 128 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - z := c.Args[0] - if !(c.Uses == 1) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMOVLGT) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(z) - v.AddArg3(x, y, v0) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVLGT(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVLGT x y (InvertFlags cond)) - // result: (CMOVLLT x y cond) + // match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCC yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVLLT) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCC) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLGT y _ (FlagEQ)) - // result: y + // match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCS yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLGT _ x (FlagGT_UGT)) - // result: x + // match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLHI yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLHI) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLGT _ x (FlagGT_ULT)) - // result: x + // match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLNE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLGT y _ (FlagLT_ULT)) - // result: y + // match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLEQ yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLGT y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGE yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGE) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVLHI(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVLHI x y (InvertFlags cond)) - // result: (CMOVLCS x y cond) + // match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLE yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVLCS) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLHI y _ (FlagEQ)) - // result: y + // match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGT yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLHI _ x (FlagGT_UGT)) - // result: x + // match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLT yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLHI y _ (FlagGT_ULT)) - // result: y + // match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLS yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLHI y _ (FlagLT_ULT)) - // result: y + // match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCC yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCC) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLHI _ x (FlagLT_UGT)) - // result: x + // match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCS yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCS) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVLLE(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVLLE x y (InvertFlags cond)) - // result: (CMOVLGE x y cond) + // match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLHI yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVLGE) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLHI) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLLE _ x (FlagEQ)) - // result: x + // match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLNE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true - } - // match: (CMOVLLE y _ (FlagGT_UGT)) - // result: y + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNE) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLEQ yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLLE y _ (FlagGT_ULT)) - // result: y + // match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGE yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLLE _ x (FlagLT_ULT)) - // result: x + // match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLLE _ x (FlagLT_UGT)) - // result: x + // match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGT yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGT) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVLLS(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVLLS x y (InvertFlags cond)) - // result: (CMOVLCC x y cond) + // match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLT yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVLCC) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLLS _ x (FlagEQ)) - // result: x + // match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLS yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLLS y _ (FlagGT_UGT)) - // result: y + // match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCC yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCC) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLLS _ x (FlagGT_ULT)) - // result: x + // match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCS yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLLS _ x (FlagLT_ULT)) - // result: x + // match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLHI yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLHI) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVLLS y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLEQ yes no t:(TESTB s:(SETEQ flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLNE yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNE) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVLEQ yes no t:(TESTB s:(SETNE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLEQ yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQ) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVLEQ yes no t:(TESTB s:(SETL flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLGE yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGE) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVLEQ yes no t:(TESTB s:(SETG flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLLE yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLE) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVLEQ yes no t:(TESTB s:(SETLE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLGT yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGT) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVLEQ yes no t:(TESTB s:(SETGE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLLT yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLT) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVLEQ yes no t:(TESTB s:(SETA flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLLS yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLS) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVLEQ yes no t:(TESTB s:(SETB flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLCC yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCC) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVLEQ yes no t:(TESTB s:(SETAE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLCS yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCS) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVLEQ yes no t:(TESTB s:(SETBE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLHI yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLHI) + v.AddArg3(yes, no, flags) + return true + } + break } return false } -func rewriteValueAMD64_OpAMD64CMOVLLT(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVLGE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (CMOVLLT x y (InvertFlags cond)) - // result: (CMOVLGT x y cond) + // match: (CMOVLGE x y (InvertFlags cond)) + // result: (CMOVLLE x y cond) for { x := v_0 y := v_1 @@ -4648,63 +11826,63 @@ func rewriteValueAMD64_OpAMD64CMOVLLT(v *Value) bool { break } cond := v_2.Args[0] - v.reset(OpAMD64CMOVLGT) + v.reset(OpAMD64CMOVLLE) v.AddArg3(x, y, cond) return true } - // match: (CMOVLLT y _ (FlagEQ)) - // result: y + // match: (CMOVLGE _ x (FlagEQ)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagEQ { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVLLT y _ (FlagGT_UGT)) - // result: y + // match: (CMOVLGE _ x (FlagGT_UGT)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVLLT y _ (FlagGT_ULT)) - // result: y + // match: (CMOVLGE _ x (FlagGT_ULT)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVLLT _ x (FlagLT_ULT)) - // result: x + // match: (CMOVLGE y _ (FlagLT_ULT)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVLLT _ x (FlagLT_UGT)) - // result: x + // match: (CMOVLGE y _ (FlagLT_UGT)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVLLT x y c:(CMPQconst [128] z)) + // match: (CMOVLGE x y c:(CMPQconst [128] z)) // cond: c.Uses == 1 - // result: (CMOVLLE x y (CMPQconst [127] z)) + // result: (CMOVLGT x y (CMPQconst [127] z)) for { x := v_0 y := v_1 @@ -4716,16 +11894,16 @@ func rewriteValueAMD64_OpAMD64CMOVLLT(v *Value) bool { if !(c.Uses == 1) { break } - v.reset(OpAMD64CMOVLLE) + v.reset(OpAMD64CMOVLGT) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(127) v0.AddArg(z) v.AddArg3(x, y, v0) return true } - // match: (CMOVLLT x y c:(CMPLconst [128] z)) + // match: (CMOVLGE x y c:(CMPLconst [128] z)) // cond: c.Uses == 1 - // result: (CMOVLLE x y (CMPLconst [127] z)) + // result: (CMOVLGT x y (CMPLconst [127] z)) for { x := v_0 y := v_1 @@ -4737,7 +11915,7 @@ func rewriteValueAMD64_OpAMD64CMOVLLT(v *Value) bool { if !(c.Uses == 1) { break } - v.reset(OpAMD64CMOVLLE) + v.reset(OpAMD64CMOVLGT) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(127) v0.AddArg(z) @@ -4746,13 +11924,12 @@ func rewriteValueAMD64_OpAMD64CMOVLLT(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64CMOVLNE(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVLGT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (CMOVLNE x y (InvertFlags cond)) - // result: (CMOVLNE x y cond) + // match: (CMOVLGT x y (InvertFlags cond)) + // result: (CMOVLLT x y cond) for { x := v_0 y := v_1 @@ -4760,11 +11937,11 @@ func rewriteValueAMD64_OpAMD64CMOVLNE(v *Value) bool { break } cond := v_2.Args[0] - v.reset(OpAMD64CMOVLNE) + v.reset(OpAMD64CMOVLLT) v.AddArg3(x, y, cond) return true } - // match: (CMOVLNE y _ (FlagEQ)) + // match: (CMOVLGT y _ (FlagEQ)) // result: y for { y := v_0 @@ -4774,7 +11951,7 @@ func rewriteValueAMD64_OpAMD64CMOVLNE(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVLNE _ x (FlagGT_UGT)) + // match: (CMOVLGT _ x (FlagGT_UGT)) // result: x for { x := v_1 @@ -4784,7 +11961,7 @@ func rewriteValueAMD64_OpAMD64CMOVLNE(v *Value) bool { v.copyOf(x) return true } - // match: (CMOVLNE _ x (FlagGT_ULT)) + // match: (CMOVLGT _ x (FlagGT_ULT)) // result: x for { x := v_1 @@ -4794,90 +11971,34 @@ func rewriteValueAMD64_OpAMD64CMOVLNE(v *Value) bool { v.copyOf(x) return true } - // match: (CMOVLNE _ x (FlagLT_ULT)) - // result: x + // match: (CMOVLGT y _ (FlagLT_ULT)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVLNE _ x (FlagLT_UGT)) - // result: x + // match: (CMOVLGT y _ (FlagLT_UGT)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVLNE x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) - // result: (CMOVLNE x y (Select1 blsr)) - for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64TESTQ { - break - } - _ = v_2.Args[1] - v_2_0 := v_2.Args[0] - v_2_1 := v_2.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { - s := v_2_0 - if s.Op != OpSelect0 { - continue - } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { - continue - } - v.reset(OpAMD64CMOVLNE) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - v.AddArg3(x, y, v0) - return true - } - break - } - // match: (CMOVLNE x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) - // result: (CMOVLNE x y (Select1 blsr)) - for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64TESTL { - break - } - _ = v_2.Args[1] - v_2_0 := v_2.Args[0] - v_2_1 := v_2.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { - s := v_2_0 - if s.Op != OpSelect0 { - continue - } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRL || s != v_2_1 { - continue - } - v.reset(OpAMD64CMOVLNE) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - v.AddArg3(x, y, v0) - return true - } - break - } return false } -func rewriteValueAMD64_OpAMD64CMOVQCC(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVLHI(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (CMOVQCC x y (InvertFlags cond)) - // result: (CMOVQLS x y cond) + // match: (CMOVLHI x y (InvertFlags cond)) + // result: (CMOVLCS x y cond) for { x := v_0 y := v_1 @@ -4885,21 +12006,21 @@ func rewriteValueAMD64_OpAMD64CMOVQCC(v *Value) bool { break } cond := v_2.Args[0] - v.reset(OpAMD64CMOVQLS) + v.reset(OpAMD64CMOVLCS) v.AddArg3(x, y, cond) return true } - // match: (CMOVQCC _ x (FlagEQ)) - // result: x + // match: (CMOVLHI y _ (FlagEQ)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagEQ { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVQCC _ x (FlagGT_UGT)) + // match: (CMOVLHI _ x (FlagGT_UGT)) // result: x for { x := v_1 @@ -4909,7 +12030,7 @@ func rewriteValueAMD64_OpAMD64CMOVQCC(v *Value) bool { v.copyOf(x) return true } - // match: (CMOVQCC y _ (FlagGT_ULT)) + // match: (CMOVLHI y _ (FlagGT_ULT)) // result: y for { y := v_0 @@ -4919,7 +12040,7 @@ func rewriteValueAMD64_OpAMD64CMOVQCC(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVQCC y _ (FlagLT_ULT)) + // match: (CMOVLHI y _ (FlagLT_ULT)) // result: y for { y := v_0 @@ -4929,7 +12050,7 @@ func rewriteValueAMD64_OpAMD64CMOVQCC(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVQCC _ x (FlagLT_UGT)) + // match: (CMOVLHI _ x (FlagLT_UGT)) // result: x for { x := v_1 @@ -4941,12 +12062,12 @@ func rewriteValueAMD64_OpAMD64CMOVQCC(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64CMOVQCS(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVLLE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (CMOVQCS x y (InvertFlags cond)) - // result: (CMOVQHI x y cond) + // match: (CMOVLLE x y (InvertFlags cond)) + // result: (CMOVLGE x y cond) for { x := v_0 y := v_1 @@ -4954,21 +12075,21 @@ func rewriteValueAMD64_OpAMD64CMOVQCS(v *Value) bool { break } cond := v_2.Args[0] - v.reset(OpAMD64CMOVQHI) + v.reset(OpAMD64CMOVLGE) v.AddArg3(x, y, cond) return true } - // match: (CMOVQCS y _ (FlagEQ)) - // result: y + // match: (CMOVLLE _ x (FlagEQ)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagEQ { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVQCS y _ (FlagGT_UGT)) + // match: (CMOVLLE y _ (FlagGT_UGT)) // result: y for { y := v_0 @@ -4978,17 +12099,17 @@ func rewriteValueAMD64_OpAMD64CMOVQCS(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVQCS _ x (FlagGT_ULT)) - // result: x + // match: (CMOVLLE y _ (FlagGT_ULT)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVQCS _ x (FlagLT_ULT)) + // match: (CMOVLLE _ x (FlagLT_ULT)) // result: x for { x := v_1 @@ -4998,25 +12119,24 @@ func rewriteValueAMD64_OpAMD64CMOVQCS(v *Value) bool { v.copyOf(x) return true } - // match: (CMOVQCS y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLLE _ x (FlagLT_UGT)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } - v.copyOf(y) + v.copyOf(x) return true } return false } -func rewriteValueAMD64_OpAMD64CMOVQEQ(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVLLS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (CMOVQEQ x y (InvertFlags cond)) - // result: (CMOVQEQ x y cond) + // match: (CMOVLLS x y (InvertFlags cond)) + // result: (CMOVLCC x y cond) for { x := v_0 y := v_1 @@ -5024,11 +12144,11 @@ func rewriteValueAMD64_OpAMD64CMOVQEQ(v *Value) bool { break } cond := v_2.Args[0] - v.reset(OpAMD64CMOVQEQ) + v.reset(OpAMD64CMOVLCC) v.AddArg3(x, y, cond) return true } - // match: (CMOVQEQ _ x (FlagEQ)) + // match: (CMOVLLS _ x (FlagEQ)) // result: x for { x := v_1 @@ -5038,7 +12158,7 @@ func rewriteValueAMD64_OpAMD64CMOVQEQ(v *Value) bool { v.copyOf(x) return true } - // match: (CMOVQEQ y _ (FlagGT_UGT)) + // match: (CMOVLLS y _ (FlagGT_UGT)) // result: y for { y := v_0 @@ -5048,27 +12168,27 @@ func rewriteValueAMD64_OpAMD64CMOVQEQ(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVQEQ y _ (FlagGT_ULT)) - // result: y + // match: (CMOVLLS _ x (FlagGT_ULT)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVQEQ y _ (FlagLT_ULT)) - // result: y + // match: (CMOVLLS _ x (FlagLT_ULT)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVQEQ y _ (FlagLT_UGT)) + // match: (CMOVLLS y _ (FlagLT_UGT)) // result: y for { y := v_0 @@ -5078,117 +12198,15 @@ func rewriteValueAMD64_OpAMD64CMOVQEQ(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVQEQ x _ (Select1 (BSFQ (ORQconst [c] _)))) - // cond: c != 0 - // result: x - for { - x := v_0 - if v_2.Op != OpSelect1 { - break - } - v_2_0 := v_2.Args[0] - if v_2_0.Op != OpAMD64BSFQ { - break - } - v_2_0_0 := v_2_0.Args[0] - if v_2_0_0.Op != OpAMD64ORQconst { - break - } - c := auxIntToInt32(v_2_0_0.AuxInt) - if !(c != 0) { - break - } - v.copyOf(x) - return true - } - // match: (CMOVQEQ x _ (Select1 (BSRQ (ORQconst [c] _)))) - // cond: c != 0 - // result: x - for { - x := v_0 - if v_2.Op != OpSelect1 { - break - } - v_2_0 := v_2.Args[0] - if v_2_0.Op != OpAMD64BSRQ { - break - } - v_2_0_0 := v_2_0.Args[0] - if v_2_0_0.Op != OpAMD64ORQconst { - break - } - c := auxIntToInt32(v_2_0_0.AuxInt) - if !(c != 0) { - break - } - v.copyOf(x) - return true - } - // match: (CMOVQEQ x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) - // result: (CMOVQEQ x y (Select1 blsr)) - for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64TESTQ { - break - } - _ = v_2.Args[1] - v_2_0 := v_2.Args[0] - v_2_1 := v_2.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { - s := v_2_0 - if s.Op != OpSelect0 { - continue - } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { - continue - } - v.reset(OpAMD64CMOVQEQ) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - v.AddArg3(x, y, v0) - return true - } - break - } - // match: (CMOVQEQ x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) - // result: (CMOVQEQ x y (Select1 blsr)) - for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64TESTL { - break - } - _ = v_2.Args[1] - v_2_0 := v_2.Args[0] - v_2_1 := v_2.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { - s := v_2_0 - if s.Op != OpSelect0 { - continue - } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRL || s != v_2_1 { - continue - } - v.reset(OpAMD64CMOVQEQ) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - v.AddArg3(x, y, v0) - return true - } - break - } return false } -func rewriteValueAMD64_OpAMD64CMOVQGE(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVLLT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (CMOVQGE x y (InvertFlags cond)) - // result: (CMOVQLE x y cond) + // match: (CMOVLLT x y (InvertFlags cond)) + // result: (CMOVLGT x y cond) for { x := v_0 y := v_1 @@ -5196,63 +12214,63 @@ func rewriteValueAMD64_OpAMD64CMOVQGE(v *Value) bool { break } cond := v_2.Args[0] - v.reset(OpAMD64CMOVQLE) + v.reset(OpAMD64CMOVLGT) v.AddArg3(x, y, cond) return true } - // match: (CMOVQGE _ x (FlagEQ)) - // result: x + // match: (CMOVLLT y _ (FlagEQ)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagEQ { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVQGE _ x (FlagGT_UGT)) - // result: x + // match: (CMOVLLT y _ (FlagGT_UGT)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVQGE _ x (FlagGT_ULT)) - // result: x + // match: (CMOVLLT y _ (FlagGT_ULT)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVQGE y _ (FlagLT_ULT)) - // result: y + // match: (CMOVLLT _ x (FlagLT_ULT)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVQGE y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLLT _ x (FlagLT_UGT)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVQGE x y c:(CMPQconst [128] z)) + // match: (CMOVLLT x y c:(CMPQconst [128] z)) // cond: c.Uses == 1 - // result: (CMOVQGT x y (CMPQconst [127] z)) + // result: (CMOVLLE x y (CMPQconst [127] z)) for { x := v_0 y := v_1 @@ -5264,16 +12282,16 @@ func rewriteValueAMD64_OpAMD64CMOVQGE(v *Value) bool { if !(c.Uses == 1) { break } - v.reset(OpAMD64CMOVQGT) + v.reset(OpAMD64CMOVLLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(127) v0.AddArg(z) v.AddArg3(x, y, v0) return true } - // match: (CMOVQGE x y c:(CMPLconst [128] z)) + // match: (CMOVLLT x y c:(CMPLconst [128] z)) // cond: c.Uses == 1 - // result: (CMOVQGT x y (CMPLconst [127] z)) + // result: (CMOVLLE x y (CMPLconst [127] z)) for { x := v_0 y := v_1 @@ -5285,7 +12303,7 @@ func rewriteValueAMD64_OpAMD64CMOVQGE(v *Value) bool { if !(c.Uses == 1) { break } - v.reset(OpAMD64CMOVQGT) + v.reset(OpAMD64CMOVLLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(127) v0.AddArg(z) @@ -5294,12 +12312,13 @@ func rewriteValueAMD64_OpAMD64CMOVQGE(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64CMOVQGT(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVLNE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (CMOVQGT x y (InvertFlags cond)) - // result: (CMOVQLT x y cond) + b := v.Block + // match: (CMOVLNE x y (InvertFlags cond)) + // result: (CMOVLNE x y cond) for { x := v_0 y := v_1 @@ -5307,11 +12326,11 @@ func rewriteValueAMD64_OpAMD64CMOVQGT(v *Value) bool { break } cond := v_2.Args[0] - v.reset(OpAMD64CMOVQLT) + v.reset(OpAMD64CMOVLNE) v.AddArg3(x, y, cond) return true } - // match: (CMOVQGT y _ (FlagEQ)) + // match: (CMOVLNE y _ (FlagEQ)) // result: y for { y := v_0 @@ -5321,7 +12340,7 @@ func rewriteValueAMD64_OpAMD64CMOVQGT(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVQGT _ x (FlagGT_UGT)) + // match: (CMOVLNE _ x (FlagGT_UGT)) // result: x for { x := v_1 @@ -5331,7 +12350,7 @@ func rewriteValueAMD64_OpAMD64CMOVQGT(v *Value) bool { v.copyOf(x) return true } - // match: (CMOVQGT _ x (FlagGT_ULT)) + // match: (CMOVLNE _ x (FlagGT_ULT)) // result: x for { x := v_1 @@ -5341,824 +12360,1826 @@ func rewriteValueAMD64_OpAMD64CMOVQGT(v *Value) bool { v.copyOf(x) return true } - // match: (CMOVQGT y _ (FlagLT_ULT)) - // result: y + // match: (CMOVLNE _ x (FlagLT_ULT)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVQGT y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLNE _ x (FlagLT_UGT)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } - v.copyOf(y) + v.copyOf(x) return true } - return false -} -func rewriteValueAMD64_OpAMD64CMOVQHI(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVQHI x y (InvertFlags cond)) - // result: (CMOVQCS x y cond) + // match: (CMOVLNE x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) + // result: (CMOVLNE x y (Select1 blsr)) for { x := v_0 y := v_1 - if v_2.Op != OpAMD64InvertFlags { + if v_2.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVQCS) - v.AddArg3(x, y, cond) - return true + _ = v_2.Args[1] + v_2_0 := v_2.Args[0] + v_2_1 := v_2.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { + s := v_2_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { + continue + } + v.reset(OpAMD64CMOVLNE) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + v.AddArg3(x, y, v0) + return true + } + break } - // match: (CMOVQHI y _ (FlagEQ)) - // result: y + // match: (CMOVLNE x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) + // result: (CMOVLNE x y (Select1 blsr)) for { - y := v_0 - if v_2.Op != OpAMD64FlagEQ { + x := v_0 + y := v_1 + if v_2.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = v_2.Args[1] + v_2_0 := v_2.Args[0] + v_2_1 := v_2.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { + s := v_2_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRL || s != v_2_1 { + continue + } + v.reset(OpAMD64CMOVLNE) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + v.AddArg3(x, y, v0) + return true + } + break } - // match: (CMOVQHI _ x (FlagGT_UGT)) - // result: x + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLEQ yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQHI y _ (FlagGT_ULT)) - // result: y + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLNE yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQHI y _ (FlagLT_ULT)) - // result: y + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLT yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQHI _ x (FlagLT_UGT)) - // result: x + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGT yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGT) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVQLE(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVQLE x y (InvertFlags cond)) - // result: (CMOVQGE x y cond) + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLE yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVQGE) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLE _ x (FlagEQ)) - // result: x + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLE y _ (FlagGT_UGT)) - // result: y + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLHI yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLHI) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLE y _ (FlagGT_ULT)) - // result: y + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCS yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLE _ x (FlagLT_ULT)) - // result: x + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCC yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCC) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLE _ x (FlagLT_UGT)) - // result: x + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLS yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLS) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVQLS(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVQLS x y (InvertFlags cond)) - // result: (CMOVQCC x y cond) + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLEQF yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVQCC) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLS _ x (FlagEQ)) - // result: x + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLNEF yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNEF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLS y _ (FlagGT_UGT)) - // result: y + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGTF yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGTF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLS _ x (FlagGT_ULT)) - // result: x + // match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGEF yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGEF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLS _ x (FlagLT_ULT)) - // result: x + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLEQ yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLS y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLNE yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64CMOVQLT(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (CMOVQLT x y (InvertFlags cond)) - // result: (CMOVQGT x y cond) - for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNE) + v.AddArg3(yes, no, flags) + return true } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVQGT) - v.AddArg3(x, y, cond) - return true + break } - // match: (CMOVQLT y _ (FlagEQ)) - // result: y + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLT yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLT y _ (FlagGT_UGT)) - // result: y + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGT yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLT y _ (FlagGT_ULT)) - // result: y + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLE yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLT _ x (FlagLT_ULT)) - // result: x + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLT _ x (FlagLT_UGT)) - // result: x + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLHI yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLHI) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQLT x y c:(CMPQconst [128] z)) - // cond: c.Uses == 1 - // result: (CMOVQLE x y (CMPQconst [127] z)) + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCS yes no flags) for { - x := v_0 - y := v_1 - c := v_2 - if c.Op != OpAMD64CMPQconst || auxIntToInt32(c.AuxInt) != 128 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - z := c.Args[0] - if !(c.Uses == 1) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMOVQLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(z) - v.AddArg3(x, y, v0) - return true + break } - // match: (CMOVQLT x y c:(CMPLconst [128] z)) - // cond: c.Uses == 1 - // result: (CMOVQLE x y (CMPLconst [127] z)) + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCC yes no flags) for { - x := v_0 - y := v_1 - c := v_2 - if c.Op != OpAMD64CMPLconst || auxIntToInt32(c.AuxInt) != 128 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - z := c.Args[0] - if !(c.Uses == 1) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCC) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMOVQLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(z) - v.AddArg3(x, y, v0) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVQNE(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (CMOVQNE x y (InvertFlags cond)) - // result: (CMOVQNE x y cond) + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLS yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVQNE) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQNE y _ (FlagEQ)) - // result: y + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLEQF yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQNE _ x (FlagGT_UGT)) - // result: x + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLNEF yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNEF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQNE _ x (FlagGT_ULT)) - // result: x + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGTF yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGTF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQNE _ x (FlagLT_ULT)) - // result: x + // match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGEF yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGEF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQNE _ x (FlagLT_UGT)) - // result: x + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLEQ yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVQNE x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) - // result: (CMOVQNE x y (Select1 blsr)) + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLNE yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64TESTQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - _ = v_2.Args[1] - v_2_0 := v_2.Args[0] - v_2_1 := v_2.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { - s := v_2_0 - if s.Op != OpSelect0 { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { + s := x.Args[0] + if s.Op != OpAMD64SETNE { continue } - v.reset(OpAMD64CMOVQNE) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - v.AddArg3(x, y, v0) + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNE) + v.AddArg3(yes, no, flags) return true } break } - // match: (CMOVQNE x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) - // result: (CMOVQNE x y (Select1 blsr)) + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLT yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64TESTL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - _ = v_2.Args[1] - v_2_0 := v_2.Args[0] - v_2_1 := v_2.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { - s := v_2_0 - if s.Op != OpSelect0 { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRL || s != v_2_1 { + s := x.Args[0] + if s.Op != OpAMD64SETL { continue } - v.reset(OpAMD64CMOVQNE) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - v.AddArg3(x, y, v0) + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLT) + v.AddArg3(yes, no, flags) return true } break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVWCC(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVWCC x y (InvertFlags cond)) - // result: (CMOVWLS x y cond) + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGT yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVWLS) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWCC _ x (FlagEQ)) - // result: x + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWCC _ x (FlagGT_UGT)) - // result: x + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWCC y _ (FlagGT_ULT)) - // result: y + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLHI yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLHI) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWCC y _ (FlagLT_ULT)) - // result: y + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCS yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWCC _ x (FlagLT_UGT)) - // result: x + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLCC yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCC) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVWCS(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVWCS x y (InvertFlags cond)) - // result: (CMOVWHI x y cond) + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLLS yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVWHI) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWCS y _ (FlagEQ)) - // result: y + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLEQF yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWCS y _ (FlagGT_UGT)) - // result: y + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLNEF yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNEF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWCS _ x (FlagGT_ULT)) - // result: x + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGTF yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGTF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWCS _ x (FlagLT_ULT)) - // result: x + // match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVLGEF yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGEF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWCS y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLNE yes no t:(TESTB s:(SETEQ flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLEQ yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVWEQ(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVWEQ x y (InvertFlags cond)) - // result: (CMOVWEQ x y cond) + // match: (CMOVLNE yes no t:(TESTB s:(SETNE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLNE yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVWEQ) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWEQ _ x (FlagEQ)) - // result: x + // match: (CMOVLNE yes no t:(TESTB s:(SETL flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLLT yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(x) - return true - } - // match: (CMOVWEQ y _ (FlagGT_UGT)) - // result: y - for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_UGT { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLT) + v.AddArg3(yes, no, flags) + return true } - v.copyOf(y) - return true + break } - // match: (CMOVWEQ y _ (FlagGT_ULT)) - // result: y + // match: (CMOVLNE yes no t:(TESTB s:(SETG flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLGT yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(y) - return true - } - // match: (CMOVWEQ y _ (FlagLT_ULT)) - // result: y - for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_ULT { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGT) + v.AddArg3(yes, no, flags) + return true } - v.copyOf(y) - return true + break } - // match: (CMOVWEQ y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLNE yes no t:(TESTB s:(SETLE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLLE yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64CMOVWGE(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVWGE x y (InvertFlags cond)) - // result: (CMOVWLE x y cond) - for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLE) + v.AddArg3(yes, no, flags) + return true } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVWLE) - v.AddArg3(x, y, cond) - return true + break } - // match: (CMOVWGE _ x (FlagEQ)) - // result: x + // match: (CMOVLNE yes no t:(TESTB s:(SETGE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLGE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(x) - return true - } - // match: (CMOVWGE _ x (FlagGT_UGT)) - // result: x - for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_UGT { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGE) + v.AddArg3(yes, no, flags) + return true } - v.copyOf(x) - return true + break } - // match: (CMOVWGE _ x (FlagGT_ULT)) - // result: x + // match: (CMOVLNE yes no t:(TESTB s:(SETA flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLHI yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(x) - return true - } - // match: (CMOVWGE y _ (FlagLT_ULT)) - // result: y - for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_ULT { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLHI) + v.AddArg3(yes, no, flags) + return true } - v.copyOf(y) - return true + break } - // match: (CMOVWGE y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLNE yes no t:(TESTB s:(SETB flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLCS yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCS) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMOVWGT(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVWGT x y (InvertFlags cond)) - // result: (CMOVWLT x y cond) + // match: (CMOVLNE yes no t:(TESTB s:(SETAE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLCC yes no flags) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVWLT) - v.AddArg3(x, y, cond) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLCC) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWGT y _ (FlagEQ)) - // result: y + // match: (CMOVLNE yes no t:(TESTB s:(SETBE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLLS yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagEQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLLS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWGT _ x (FlagGT_UGT)) - // result: x + // match: (CMOVLNE yes no t:(TESTB s:(SETEQF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLEQF yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLEQF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWGT _ x (FlagGT_ULT)) - // result: x + // match: (CMOVLNE yes no t:(TESTB s:(SETNEF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLNEF yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLNEF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWGT y _ (FlagLT_ULT)) - // result: y + // match: (CMOVLNE yes no t:(TESTB s:(SETGF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLGTF yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGTF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWGT y _ (FlagLT_UGT)) - // result: y + // match: (CMOVLNE yes no t:(TESTB s:(SETGEF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVLGEF yes no flags) for { - y := v_0 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVLGEF) + v.AddArg3(yes, no, flags) + return true + } + break } return false } -func rewriteValueAMD64_OpAMD64CMOVWHI(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVQCC(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (CMOVWHI x y (InvertFlags cond)) - // result: (CMOVWCS x y cond) + // match: (CMOVQCC x y (InvertFlags cond)) + // result: (CMOVQLS x y cond) for { x := v_0 y := v_1 @@ -6166,21 +14187,21 @@ func rewriteValueAMD64_OpAMD64CMOVWHI(v *Value) bool { break } cond := v_2.Args[0] - v.reset(OpAMD64CMOVWCS) + v.reset(OpAMD64CMOVQLS) v.AddArg3(x, y, cond) return true } - // match: (CMOVWHI y _ (FlagEQ)) - // result: y + // match: (CMOVQCC _ x (FlagEQ)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagEQ { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVWHI _ x (FlagGT_UGT)) + // match: (CMOVQCC _ x (FlagGT_UGT)) // result: x for { x := v_1 @@ -6190,7 +14211,7 @@ func rewriteValueAMD64_OpAMD64CMOVWHI(v *Value) bool { v.copyOf(x) return true } - // match: (CMOVWHI y _ (FlagGT_ULT)) + // match: (CMOVQCC y _ (FlagGT_ULT)) // result: y for { y := v_0 @@ -6200,7 +14221,7 @@ func rewriteValueAMD64_OpAMD64CMOVWHI(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVWHI y _ (FlagLT_ULT)) + // match: (CMOVQCC y _ (FlagLT_ULT)) // result: y for { y := v_0 @@ -6210,7 +14231,7 @@ func rewriteValueAMD64_OpAMD64CMOVWHI(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVWHI _ x (FlagLT_UGT)) + // match: (CMOVQCC _ x (FlagLT_UGT)) // result: x for { x := v_1 @@ -6222,12 +14243,12 @@ func rewriteValueAMD64_OpAMD64CMOVWHI(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64CMOVWLE(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVQCS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (CMOVWLE x y (InvertFlags cond)) - // result: (CMOVWGE x y cond) + // match: (CMOVQCS x y (InvertFlags cond)) + // result: (CMOVQHI x y cond) for { x := v_0 y := v_1 @@ -6235,21 +14256,21 @@ func rewriteValueAMD64_OpAMD64CMOVWLE(v *Value) bool { break } cond := v_2.Args[0] - v.reset(OpAMD64CMOVWGE) + v.reset(OpAMD64CMOVQHI) v.AddArg3(x, y, cond) return true } - // match: (CMOVWLE _ x (FlagEQ)) - // result: x + // match: (CMOVQCS y _ (FlagEQ)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagEQ { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVWLE y _ (FlagGT_UGT)) + // match: (CMOVQCS y _ (FlagGT_UGT)) // result: y for { y := v_0 @@ -6259,17 +14280,17 @@ func rewriteValueAMD64_OpAMD64CMOVWLE(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVWLE y _ (FlagGT_ULT)) - // result: y + // match: (CMOVQCS _ x (FlagGT_ULT)) + // result: x for { - y := v_0 + x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVWLE _ x (FlagLT_ULT)) + // match: (CMOVQCS _ x (FlagLT_ULT)) // result: x for { x := v_1 @@ -6279,24 +14300,25 @@ func rewriteValueAMD64_OpAMD64CMOVWLE(v *Value) bool { v.copyOf(x) return true } - // match: (CMOVWLE _ x (FlagLT_UGT)) - // result: x + // match: (CMOVQCS y _ (FlagLT_UGT)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } - v.copyOf(x) + v.copyOf(y) return true } return false } -func rewriteValueAMD64_OpAMD64CMOVWLS(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVQEQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (CMOVWLS x y (InvertFlags cond)) - // result: (CMOVWCC x y cond) + b := v.Block + // match: (CMOVQEQ x y (InvertFlags cond)) + // result: (CMOVQEQ x y cond) for { x := v_0 y := v_1 @@ -6304,11 +14326,11 @@ func rewriteValueAMD64_OpAMD64CMOVWLS(v *Value) bool { break } cond := v_2.Args[0] - v.reset(OpAMD64CMOVWCC) + v.reset(OpAMD64CMOVQEQ) v.AddArg3(x, y, cond) return true } - // match: (CMOVWLS _ x (FlagEQ)) + // match: (CMOVQEQ _ x (FlagEQ)) // result: x for { x := v_1 @@ -6318,7 +14340,7 @@ func rewriteValueAMD64_OpAMD64CMOVWLS(v *Value) bool { v.copyOf(x) return true } - // match: (CMOVWLS y _ (FlagGT_UGT)) + // match: (CMOVQEQ y _ (FlagGT_UGT)) // result: y for { y := v_0 @@ -6328,27 +14350,27 @@ func rewriteValueAMD64_OpAMD64CMOVWLS(v *Value) bool { v.copyOf(y) return true } - // match: (CMOVWLS _ x (FlagGT_ULT)) - // result: x + // match: (CMOVQEQ y _ (FlagGT_ULT)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVWLS _ x (FlagLT_ULT)) - // result: x + // match: (CMOVQEQ y _ (FlagLT_ULT)) + // result: y for { - x := v_1 + y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } - v.copyOf(x) + v.copyOf(y) return true } - // match: (CMOVWLS y _ (FlagLT_UGT)) + // match: (CMOVQEQ y _ (FlagLT_UGT)) // result: y for { y := v_0 @@ -6358,6371 +14380,8070 @@ func rewriteValueAMD64_OpAMD64CMOVWLS(v *Value) bool { v.copyOf(y) return true } - return false -} -func rewriteValueAMD64_OpAMD64CMOVWLT(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVWLT x y (InvertFlags cond)) - // result: (CMOVWGT x y cond) + // match: (CMOVQEQ x _ (Select1 (BSFQ (ORQconst [c] _)))) + // cond: c != 0 + // result: x for { x := v_0 - y := v_1 - if v_2.Op != OpAMD64InvertFlags { + if v_2.Op != OpSelect1 { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVWGT) - v.AddArg3(x, y, cond) - return true - } - // match: (CMOVWLT y _ (FlagEQ)) - // result: y - for { - y := v_0 - if v_2.Op != OpAMD64FlagEQ { + v_2_0 := v_2.Args[0] + if v_2_0.Op != OpAMD64BSFQ { break } - v.copyOf(y) - return true - } - // match: (CMOVWLT y _ (FlagGT_UGT)) - // result: y - for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_UGT { + v_2_0_0 := v_2_0.Args[0] + if v_2_0_0.Op != OpAMD64ORQconst { break } - v.copyOf(y) - return true - } - // match: (CMOVWLT y _ (FlagGT_ULT)) - // result: y - for { - y := v_0 - if v_2.Op != OpAMD64FlagGT_ULT { + c := auxIntToInt32(v_2_0_0.AuxInt) + if !(c != 0) { break } - v.copyOf(y) + v.copyOf(x) return true } - // match: (CMOVWLT _ x (FlagLT_ULT)) + // match: (CMOVQEQ x _ (Select1 (BSRQ (ORQconst [c] _)))) + // cond: c != 0 // result: x for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_ULT { + x := v_0 + if v_2.Op != OpSelect1 { break } - v.copyOf(x) - return true - } - // match: (CMOVWLT _ x (FlagLT_UGT)) - // result: x - for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_UGT { + v_2_0 := v_2.Args[0] + if v_2_0.Op != OpAMD64BSRQ { + break + } + v_2_0_0 := v_2_0.Args[0] + if v_2_0_0.Op != OpAMD64ORQconst { + break + } + c := auxIntToInt32(v_2_0_0.AuxInt) + if !(c != 0) { break } v.copyOf(x) return true } - return false -} -func rewriteValueAMD64_OpAMD64CMOVWNE(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMOVWNE x y (InvertFlags cond)) - // result: (CMOVWNE x y cond) + // match: (CMOVQEQ x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) + // result: (CMOVQEQ x y (Select1 blsr)) for { x := v_0 y := v_1 - if v_2.Op != OpAMD64InvertFlags { + if v_2.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - v.reset(OpAMD64CMOVWNE) - v.AddArg3(x, y, cond) - return true + _ = v_2.Args[1] + v_2_0 := v_2.Args[0] + v_2_1 := v_2.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { + s := v_2_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { + continue + } + v.reset(OpAMD64CMOVQEQ) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + v.AddArg3(x, y, v0) + return true + } + break } - // match: (CMOVWNE y _ (FlagEQ)) - // result: y + // match: (CMOVQEQ x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) + // result: (CMOVQEQ x y (Select1 blsr)) for { - y := v_0 - if v_2.Op != OpAMD64FlagEQ { + x := v_0 + y := v_1 + if v_2.Op != OpAMD64TESTL { break } - v.copyOf(y) - return true + _ = v_2.Args[1] + v_2_0 := v_2.Args[0] + v_2_1 := v_2.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { + s := v_2_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRL || s != v_2_1 { + continue + } + v.reset(OpAMD64CMOVQEQ) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + v.AddArg3(x, y, v0) + return true + } + break } - // match: (CMOVWNE _ x (FlagGT_UGT)) - // result: x + // match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQNE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQNE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWNE _ x (FlagGT_ULT)) - // result: x + // match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQEQ yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagGT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWNE _ x (FlagLT_ULT)) - // result: x + // match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_ULT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMOVWNE _ x (FlagLT_UGT)) - // result: x + // match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLE yes no flags) for { - x := v_1 - if v_2.Op != OpAMD64FlagLT_UGT { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLE) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPB(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (CMPB x (MOVLconst [c])) - // result: (CMPBconst x [int8(c)]) + // match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGT yes no flags) for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64CMPBconst) - v.AuxInt = int8ToAuxInt(int8(c)) - v.AddArg(x) - return true - } - // match: (CMPB (MOVLconst [c]) x) - // result: (InvertFlags (CMPBconst x [int8(c)])) - for { - if v_0.Op != OpAMD64MOVLconst { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGT) + v.AddArg3(yes, no, flags) + return true } - c := auxIntToInt32(v_0.AuxInt) - x := v_1 - v.reset(OpAMD64InvertFlags) - v0 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(c)) - v0.AddArg(x) - v.AddArg(v0) - return true + break } - // match: (CMPB x y) - // cond: canonLessThan(x,y) - // result: (InvertFlags (CMPB y x)) + // match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLT yes no flags) for { - x := v_0 - y := v_1 - if !(canonLessThan(x, y)) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64InvertFlags) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(y, x) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMPB l:(MOVBload {sym} [off] ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (CMPBload {sym} [off] ptr x mem) + // match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLS yes no flags) for { - l := v_0 - if l.Op != OpAMD64MOVBload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPBload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + break } - // match: (CMPB x l:(MOVBload {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (InvertFlags (CMPBload {sym} [off] ptr x mem)) + // match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCC yes no flags) for { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVBload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCC) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64InvertFlags) - v0 := b.NewValue0(l.Pos, OpAMD64CMPBload, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg3(ptr, x, mem) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPBconst(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (CMPBconst (MOVLconst [x]) [y]) - // cond: int8(x)==y - // result: (FlagEQ) + // match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCS yes no flags) for { - y := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - x := auxIntToInt32(v_0.AuxInt) - if !(int8(x) == y) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagEQ) - return true + break } - // match: (CMPBconst (MOVLconst [x]) [y]) - // cond: int8(x)uint8(y) - // result: (FlagLT_UGT) + // match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQNE yes no flags) for { - y := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - x := auxIntToInt32(v_0.AuxInt) - if !(int8(x) < y && uint8(x) > uint8(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQNE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagLT_UGT) - return true + break } - // match: (CMPBconst (MOVLconst [x]) [y]) - // cond: int8(x)>y && uint8(x) y && uint8(x) < uint8(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQ) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagGT_ULT) - return true + break } - // match: (CMPBconst (MOVLconst [x]) [y]) - // cond: int8(x)>y && uint8(x)>uint8(y) - // result: (FlagGT_UGT) + // match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGE yes no flags) for { - y := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - x := auxIntToInt32(v_0.AuxInt) - if !(int8(x) > y && uint8(x) > uint8(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagGT_UGT) - return true + break } - // match: (CMPBconst (ANDLconst _ [m]) [n]) - // cond: 0 <= int8(m) && int8(m) < n - // result: (FlagLT_ULT) + // match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLE yes no flags) for { - n := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ANDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - m := auxIntToInt32(v_0.AuxInt) - if !(0 <= int8(m) && int8(m) < n) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagLT_ULT) - return true + break } - // match: (CMPBconst a:(ANDL x y) [0]) - // cond: a.Uses == 1 - // result: (TESTB x y) + // match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGT yes no flags) for { - if auxIntToInt8(v.AuxInt) != 0 { - break - } - a := v_0 - if a.Op != OpAMD64ANDL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - y := a.Args[1] - x := a.Args[0] - if !(a.Uses == 1) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64TESTB) - v.AddArg2(x, y) - return true + break } - // match: (CMPBconst a:(ANDLconst [c] x) [0]) - // cond: a.Uses == 1 - // result: (TESTBconst [int8(c)] x) + // match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLT yes no flags) for { - if auxIntToInt8(v.AuxInt) != 0 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - a := v_0 - if a.Op != OpAMD64ANDLconst { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLT) + v.AddArg3(yes, no, flags) + return true } - c := auxIntToInt32(a.AuxInt) - x := a.Args[0] - if !(a.Uses == 1) { + break + } + // match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLS yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64TESTBconst) - v.AuxInt = int8ToAuxInt(int8(c)) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMPBconst x [0]) - // result: (TESTB x x) + // match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCC yes no flags) for { - if auxIntToInt8(v.AuxInt) != 0 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - x := v_0 - v.reset(OpAMD64TESTB) - v.AddArg2(x, x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCC) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) - // cond: l.Uses == 1 && clobber(l) - // result: @l.Block (CMPBconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCS yes no flags) for { - c := auxIntToInt8(v.AuxInt) - l := v_0 - if l.Op != OpAMD64MOVBload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(l.Uses == 1 && clobber(l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCS) + v.AddArg3(yes, no, flags) + return true } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) - v.copyOf(v0) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) - // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) + // match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQHI yes no flags) for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQHI) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPBconstload) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(sym) - v.AddArg2(base, mem) - return true + break } - // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) + // match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQNE yes no flags) for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQNE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPBconstload) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (CMPBload [off1+off2] {sym} base val mem) + // match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQEQ yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQ) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPBload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) - return true + break } - // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPBload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) - return true + break } - // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) - // result: (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) + // match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLE yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - c := auxIntToInt32(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64CMPBconstload) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLE) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (CMPL x (MOVLconst [c])) - // result: (CMPLconst x [c]) + // match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGT yes no flags) for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64CMPLconst) - v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMPL (MOVLconst [c]) x) - // result: (InvertFlags (CMPLconst x [c])) + // match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLT yes no flags) for { - if v_0.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - c := auxIntToInt32(v_0.AuxInt) - x := v_1 - v.reset(OpAMD64InvertFlags) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(c) - v0.AddArg(x) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMPL x y) - // cond: canonLessThan(x,y) - // result: (InvertFlags (CMPL y x)) + // match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLS yes no flags) for { - x := v_0 - y := v_1 - if !(canonLessThan(x, y)) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64InvertFlags) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) - v0.AddArg2(y, x) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (CMPLload {sym} [off] ptr x mem) + // match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCC yes no flags) for { - l := v_0 - if l.Op != OpAMD64MOVLload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCC) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + break } - // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) + // match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCS yes no flags) for { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVLload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64InvertFlags) - v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg3(ptr, x, mem) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPLconst(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (CMPLconst (MOVLconst [x]) [y]) - // cond: x==y - // result: (FlagEQ) + // match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQHI yes no flags) for { - y := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - x := auxIntToInt32(v_0.AuxInt) - if !(x == y) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQHI) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagEQ) - return true + break } - // match: (CMPLconst (MOVLconst [x]) [y]) - // cond: xuint32(y) - // result: (FlagLT_UGT) + // match: (CMOVQEQ yes no t:(TESTB s:(SETNE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQEQ yes no flags) for { - y := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - x := auxIntToInt32(v_0.AuxInt) - if !(x < y && uint32(x) > uint32(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQ) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagLT_UGT) - return true + break } - // match: (CMPLconst (MOVLconst [x]) [y]) - // cond: x>y && uint32(x) y && uint32(x) < uint32(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagGT_ULT) - return true + break } - // match: (CMPLconst (MOVLconst [x]) [y]) - // cond: x>y && uint32(x)>uint32(y) - // result: (FlagGT_UGT) + // match: (CMOVQEQ yes no t:(TESTB s:(SETG flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQLE yes no flags) for { - y := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - x := auxIntToInt32(v_0.AuxInt) - if !(x > y && uint32(x) > uint32(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagGT_UGT) - return true + break } - // match: (CMPLconst (SHRLconst _ [c]) [n]) - // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) - // result: (FlagLT_UGT) + // match: (CMOVQHI _ x (FlagGT_UGT)) + // result: x for { - if v_0.Op != OpAMD64MOVQconst { - break - } - x := auxIntToInt64(v_0.AuxInt) - if v_1.Op != OpAMD64MOVQconst { - break - } - y := auxIntToInt64(v_1.AuxInt) - if !(x < y && uint64(x) > uint64(y)) { + x := v_1 + if v_2.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64FlagLT_UGT) + v.copyOf(x) return true } - // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) - // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { + y := v_0 + if v_2.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64FlagGT_ULT) + v.copyOf(y) return true } - // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) - // cond: x>y && uint64(x)>uint64(y) - // result: (FlagGT_UGT) + // match: (CMOVQHI y _ (FlagLT_ULT)) + // result: y for { - if v_0.Op != OpAMD64MOVQconst { - break - } - x := auxIntToInt64(v_0.AuxInt) - if v_1.Op != OpAMD64MOVQconst { - break - } - y := auxIntToInt64(v_1.AuxInt) - if !(x > y && uint64(x) > uint64(y)) { + y := v_0 + if v_2.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64FlagGT_UGT) + v.copyOf(y) return true } - // match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (CMPQload {sym} [off] ptr x mem) + // match: (CMOVQHI _ x (FlagLT_UGT)) + // result: x for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { + if v_2.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64CMPQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(x) return true } - // match: (CMPQ x l:(MOVQload {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (InvertFlags (CMPQload {sym} [off] ptr x mem)) + return false +} +func rewriteValueAMD64_OpAMD64CMOVQLE(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMOVQLE x y (InvertFlags cond)) + // result: (CMOVQGE x y cond) for { x := v_0 - l := v_1 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { + y := v_1 + if v_2.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64InvertFlags) - v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg3(ptr, x, mem) - v.AddArg(v0) + cond := v_2.Args[0] + v.reset(OpAMD64CMOVQGE) + v.AddArg3(x, y, cond) return true } - return false -} -func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (CMPQconst (MOVQconst [x]) [y]) - // cond: x==int64(y) - // result: (FlagEQ) + // match: (CMOVQLE _ x (FlagEQ)) + // result: x for { - y := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { - break - } - x := auxIntToInt64(v_0.AuxInt) - if !(x == int64(y)) { + x := v_1 + if v_2.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64FlagEQ) + v.copyOf(x) return true } - // match: (CMPQconst (MOVQconst [x]) [y]) - // cond: xuint64(int64(y)) - // result: (FlagLT_UGT) + // match: (CMOVQLE y _ (FlagGT_ULT)) + // result: y for { - y := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { - break - } - x := auxIntToInt64(v_0.AuxInt) - if !(x < int64(y) && uint64(x) > uint64(int64(y))) { + y := v_0 + if v_2.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64FlagLT_UGT) + v.copyOf(y) return true } - // match: (CMPQconst (MOVQconst [x]) [y]) - // cond: x>int64(y) && uint64(x) int64(y) && uint64(x) < uint64(int64(y))) { + x := v_1 + if v_2.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64FlagGT_ULT) + v.copyOf(x) return true } - // match: (CMPQconst (MOVQconst [x]) [y]) - // cond: x>int64(y) && uint64(x)>uint64(int64(y)) - // result: (FlagGT_UGT) + // match: (CMOVQLE _ x (FlagLT_UGT)) + // result: x for { - y := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { - break - } - x := auxIntToInt64(v_0.AuxInt) - if !(x > int64(y) && uint64(x) > uint64(int64(y))) { + x := v_1 + if v_2.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64FlagGT_UGT) + v.copyOf(x) return true } - // match: (CMPQconst (MOVBQZX _) [c]) - // cond: 0xFF < c - // result: (FlagLT_ULT) + return false +} +func rewriteValueAMD64_OpAMD64CMOVQLS(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMOVQLS x y (InvertFlags cond)) + // result: (CMOVQCC x y cond) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { + x := v_0 + y := v_1 + if v_2.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64FlagLT_ULT) + cond := v_2.Args[0] + v.reset(OpAMD64CMOVQCC) + v.AddArg3(x, y, cond) return true } - // match: (CMPQconst (MOVWQZX _) [c]) - // cond: 0xFFFF < c - // result: (FlagLT_ULT) + // match: (CMOVQLS _ x (FlagEQ)) + // result: x for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { + x := v_1 + if v_2.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64FlagLT_ULT) + v.copyOf(x) return true } - // match: (CMPQconst (SHRQconst _ [c]) [n]) - // cond: 0 <= n && 0 < c && c <= 64 && (1< blsr)) for { - if v_0.Op != OpAMD64MOVLconst { + x := v_0 + y := v_1 + if v_2.Op != OpAMD64TESTQ { break } - c := auxIntToInt32(v_0.AuxInt) - x := v_1 - v.reset(OpAMD64InvertFlags) - v0 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v0.AuxInt = int16ToAuxInt(int16(c)) - v0.AddArg(x) - v.AddArg(v0) - return true + _ = v_2.Args[1] + v_2_0 := v_2.Args[0] + v_2_1 := v_2.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { + s := v_2_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { + continue + } + v.reset(OpAMD64CMOVQNE) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + v.AddArg3(x, y, v0) + return true + } + break } - // match: (CMPW x y) - // cond: canonLessThan(x,y) - // result: (InvertFlags (CMPW y x)) + // match: (CMOVQNE x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) + // result: (CMOVQNE x y (Select1 blsr)) for { x := v_0 y := v_1 - if !(canonLessThan(x, y)) { + if v_2.Op != OpAMD64TESTL { break } - v.reset(OpAMD64InvertFlags) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) - v0.AddArg2(y, x) - v.AddArg(v0) - return true + _ = v_2.Args[1] + v_2_0 := v_2.Args[0] + v_2_1 := v_2.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { + s := v_2_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRL || s != v_2_1 { + continue + } + v.reset(OpAMD64CMOVQNE) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + v.AddArg3(x, y, v0) + return true + } + break } - // match: (CMPW l:(MOVWload {sym} [off] ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (CMPWload {sym} [off] ptr x mem) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQEQ yes no flags) for { - l := v_0 - if l.Op != OpAMD64MOVWload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQ) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPWload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + break } - // match: (CMPW x l:(MOVWload {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (InvertFlags (CMPWload {sym} [off] ptr x mem)) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQNE yes no flags) for { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVWload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQNE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64InvertFlags) - v0 := b.NewValue0(l.Pos, OpAMD64CMPWload, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg3(ptr, x, mem) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPWconst(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (CMPWconst (MOVLconst [x]) [y]) - // cond: int16(x)==y - // result: (FlagEQ) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLT yes no flags) for { - y := auxIntToInt16(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - x := auxIntToInt32(v_0.AuxInt) - if !(int16(x) == y) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagEQ) - return true + break } - // match: (CMPWconst (MOVLconst [x]) [y]) - // cond: int16(x)uint16(y) - // result: (FlagLT_UGT) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLE yes no flags) for { - y := auxIntToInt16(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - x := auxIntToInt32(v_0.AuxInt) - if !(int16(x) < y && uint16(x) > uint16(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagLT_UGT) - return true + break } - // match: (CMPWconst (MOVLconst [x]) [y]) - // cond: int16(x)>y && uint16(x) y && uint16(x) < uint16(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagGT_ULT) - return true + break } - // match: (CMPWconst (MOVLconst [x]) [y]) - // cond: int16(x)>y && uint16(x)>uint16(y) - // result: (FlagGT_UGT) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQHI yes no flags) for { - y := auxIntToInt16(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - x := auxIntToInt32(v_0.AuxInt) - if !(int16(x) > y && uint16(x) > uint16(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQHI) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagGT_UGT) - return true + break } - // match: (CMPWconst (ANDLconst _ [m]) [n]) - // cond: 0 <= int16(m) && int16(m) < n - // result: (FlagLT_ULT) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCS yes no flags) for { - n := auxIntToInt16(v.AuxInt) - if v_0.Op != OpAMD64ANDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - m := auxIntToInt32(v_0.AuxInt) - if !(0 <= int16(m) && int16(m) < n) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64FlagLT_ULT) - return true + break } - // match: (CMPWconst a:(ANDL x y) [0]) - // cond: a.Uses == 1 - // result: (TESTW x y) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCC yes no flags) for { - if auxIntToInt16(v.AuxInt) != 0 { - break - } - a := v_0 - if a.Op != OpAMD64ANDL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - y := a.Args[1] - x := a.Args[0] - if !(a.Uses == 1) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCC) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64TESTW) - v.AddArg2(x, y) - return true + break } - // match: (CMPWconst a:(ANDLconst [c] x) [0]) - // cond: a.Uses == 1 - // result: (TESTWconst [int16(c)] x) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLS yes no flags) for { - if auxIntToInt16(v.AuxInt) != 0 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - a := v_0 - if a.Op != OpAMD64ANDLconst { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLS) + v.AddArg3(yes, no, flags) + return true } - c := auxIntToInt32(a.AuxInt) - x := a.Args[0] - if !(a.Uses == 1) { + break + } + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQEQF yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64TESTWconst) - v.AuxInt = int16ToAuxInt(int16(c)) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMPWconst x [0]) - // result: (TESTW x x) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQNEF yes no flags) for { - if auxIntToInt16(v.AuxInt) != 0 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - x := v_0 - v.reset(OpAMD64TESTW) - v.AddArg2(x, x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQNEF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) - // cond: l.Uses == 1 && clobber(l) - // result: @l.Block (CMPWconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGTF yes no flags) for { - c := auxIntToInt16(v.AuxInt) - l := v_0 - if l.Op != OpAMD64MOVWload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(l.Uses == 1 && clobber(l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGTF) + v.AddArg3(yes, no, flags) + return true } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) - v.copyOf(v0) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) - // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) + // match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGEF yes no flags) for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGEF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPWconstload) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(sym) - v.AddArg2(base, mem) - return true + break } - // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQEQ yes no flags) for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQ) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPWconstload) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (CMPWload [off1+off2] {sym} base val mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQNE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQNE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPWload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) - return true + break } - // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLT yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPWload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) - return true + break } - // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) - // result: (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGT yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - c := auxIntToInt32(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64CMPWconstload) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGT) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPXCHGLlock(v *Value) bool { - v_3 := v.Args[3] - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - old := v_1 - new_ := v_2 - mem := v_3 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPXCHGLlock) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg4(ptr, old, new_, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64CMPXCHGQlock(v *Value) bool { - v_3 := v.Args[3] - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - old := v_1 - new_ := v_2 - mem := v_3 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64CMPXCHGQlock) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg4(ptr, old, new_, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64DIVSD(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (DIVSDload x [off] {sym} ptr mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQHI yes no flags) for { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVSDload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQHI) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64DIVSDload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (DIVSDload [off1+off2] {sym} val base mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCS yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64DIVSDload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) - return true + break } - // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCC yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCC) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64DIVSDload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64DIVSS(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (DIVSSload x [off] {sym} ptr mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLS yes no flags) for { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVSSload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64DIVSSload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (DIVSSload [off1+off2] {sym} val base mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQEQF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64DIVSSload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) - return true + break } - // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQNEF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQNEF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64DIVSSload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64HMULL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (HMULL x y) - // cond: !x.rematerializeable() && y.rematerializeable() - // result: (HMULL y x) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGTF yes no flags) for { - x := v_0 - y := v_1 - if !(!x.rematerializeable() && y.rematerializeable()) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64HMULL) - v.AddArg2(y, x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGTF) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64HMULLU(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (HMULLU x y) - // cond: !x.rematerializeable() && y.rematerializeable() - // result: (HMULLU y x) + // match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGEF yes no flags) for { - x := v_0 - y := v_1 - if !(!x.rematerializeable() && y.rematerializeable()) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64HMULLU) - v.AddArg2(y, x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGEF) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64HMULQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (HMULQ x y) - // cond: !x.rematerializeable() && y.rematerializeable() - // result: (HMULQ y x) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQEQ yes no flags) for { - x := v_0 - y := v_1 - if !(!x.rematerializeable() && y.rematerializeable()) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64HMULQ) - v.AddArg2(y, x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64HMULQU(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (HMULQU x y) - // cond: !x.rematerializeable() && y.rematerializeable() - // result: (HMULQU y x) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQNE yes no flags) for { - x := v_0 - y := v_1 - if !(!x.rematerializeable() && y.rematerializeable()) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64HMULQU) - v.AddArg2(y, x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQNE) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64LEAL(v *Value) bool { - v_0 := v.Args[0] - // match: (LEAL [c] {s} (ADDLconst [d] x)) - // cond: is32Bit(int64(c)+int64(d)) - // result: (LEAL [c+d] {s} x) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLT yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(is32Bit(int64(c) + int64(d))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAL) - v.AuxInt = int32ToAuxInt(c + d) - v.Aux = symToAux(s) - v.AddArg(x) - return true + break } - // match: (LEAL [c] {s} (ADDL x y)) - // cond: x.Op != OpSB && y.Op != OpSB - // result: (LEAL1 [c] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGT yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - y := v_0_1 - if !(x.Op != OpSB && y.Op != OpSB) { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - v.reset(OpAMD64LEAL1) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGT) + v.AddArg3(yes, no, flags) return true } break } - return false -} -func rewriteValueAMD64_OpAMD64LEAL1(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) - // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB - // result: (LEAL1 [c+d] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLE yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64ADDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - y := v_1 - if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { + s := x.Args[0] + if s.Op != OpAMD64SETLE { continue } - v.reset(OpAMD64LEAL1) - v.AuxInt = int32ToAuxInt(c + d) - v.Aux = symToAux(s) - v.AddArg2(x, y) + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLE) + v.AddArg3(yes, no, flags) return true } break } - // match: (LEAL1 [c] {s} x z:(ADDL y y)) - // cond: x != z - // result: (LEAL2 [c] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGE yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - z := v_1 - if z.Op != OpAMD64ADDL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - y := z.Args[1] - if y != z.Args[0] || !(x != z) { + s := x.Args[0] + if s.Op != OpAMD64SETGE { continue } - v.reset(OpAMD64LEAL2) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGE) + v.AddArg3(yes, no, flags) return true } break } - // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) - // result: (LEAL4 [c] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQHI yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - y := v_1.Args[0] - v.reset(OpAMD64LEAL4) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQHI) + v.AddArg3(yes, no, flags) return true } break } - // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) - // result: (LEAL8 [c] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCS yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - y := v_1.Args[0] - v.reset(OpAMD64LEAL8) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCS) + v.AddArg3(yes, no, flags) return true } break } - return false -} -func rewriteValueAMD64_OpAMD64LEAL2(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) - // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB - // result: (LEAL2 [c+d] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQCC yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - y := v_1 - if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCC) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAL2) - v.AuxInt = int32ToAuxInt(c + d) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true + break } - // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) - // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB - // result: (LEAL2 [c+2*d] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQLS yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64ADDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - d := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAL2) - v.AuxInt = int32ToAuxInt(c + 2*d) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true + break } - // match: (LEAL2 [c] {s} x z:(ADDL y y)) - // cond: x != z - // result: (LEAL4 [c] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQEQF yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - z := v_1 - if z.Op != OpAMD64ADDL { - break - } - y := z.Args[1] - if y != z.Args[0] || !(x != z) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64LEAL4) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true - } - // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) - // result: (LEAL8 [c] {s} x y) - for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAL8) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true - } - // match: (LEAL2 [0] {s} (ADDL x x) x) - // cond: s == nil - // result: (SHLLconst [2] x) - for { - if auxIntToInt32(v.AuxInt) != 0 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDL { - break - } - x := v_0.Args[1] - if x != v_0.Args[0] || x != v_1 || !(s == nil) { - break - } - v.reset(OpAMD64SHLLconst) - v.AuxInt = int8ToAuxInt(2) - v.AddArg(x) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64LEAL4(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) - // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB - // result: (LEAL4 [c+d] {s} x y) - for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDLconst { - break - } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - y := v_1 - if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { - break - } - v.reset(OpAMD64LEAL4) - v.AuxInt = int32ToAuxInt(c + d) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true - } - // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) - // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB - // result: (LEAL4 [c+4*d] {s} x y) - for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - d := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAL4) - v.AuxInt = int32ToAuxInt(c + 4*d) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true + break } - // match: (LEAL4 [c] {s} x z:(ADDL y y)) - // cond: x != z - // result: (LEAL8 [c] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQNEF yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - z := v_1 - if z.Op != OpAMD64ADDL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - y := z.Args[1] - if y != z.Args[0] || !(x != z) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQNEF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAL8) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64LEAL8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) - // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB - // result: (LEAL8 [c+d] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGTF yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - y := v_1 - if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGTF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAL8) - v.AuxInt = int32ToAuxInt(c + d) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true + break } - // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) - // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB - // result: (LEAL8 [c+8*d] {s} x y) + // match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVQGEF yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64ADDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - d := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGEF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAL8) - v.AuxInt = int32ToAuxInt(c + 8*d) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { - v_0 := v.Args[0] - // match: (LEAQ [c] {s} (ADDQconst [d] x)) - // cond: is32Bit(int64(c)+int64(d)) - // result: (LEAQ [c+d] {s} x) + // match: (CMOVQNE yes no t:(TESTB s:(SETEQ flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQEQ yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(is32Bit(int64(c) + int64(d))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQEQ) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ) - v.AuxInt = int32ToAuxInt(c + d) - v.Aux = symToAux(s) - v.AddArg(x) - return true + break } - // match: (LEAQ [c] {s} (ADDQ x y)) - // cond: x.Op != OpSB && y.Op != OpSB - // result: (LEAQ1 [c] {s} x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETNE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQNE yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - y := v_0_1 - if !(x.Op != OpSB && y.Op != OpSB) { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNE { continue } - v.reset(OpAMD64LEAQ1) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQNE) + v.AddArg3(yes, no, flags) return true } break } - // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) + // match: (CMOVQNE yes no t:(TESTB s:(SETL flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQLT yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - x := v_0.Args[0] - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg(x) - return true + break } - // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETG flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQGT yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ1 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - y := v_0.Args[1] - x := v_0.Args[0] - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ1) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(x, y) - return true + break } - // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETLE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQLE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ2 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - y := v_0.Args[1] - x := v_0.Args[0] - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ2) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(x, y) - return true + break } - // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETGE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQGE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ4 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - y := v_0.Args[1] - x := v_0.Args[0] - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ4) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(x, y) - return true + break } - // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETA flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQHI yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ8 { - break - } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - y := v_0.Args[1] - x := v_0.Args[0] - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.reset(OpAMD64LEAQ8) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(x, y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) - // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB - // result: (LEAQ1 [c+d] {s} x y) - for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64ADDQconst { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETA { continue } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - y := v_1 - if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v.reset(OpAMD64LEAQ1) - v.AuxInt = int32ToAuxInt(c + d) - v.Aux = symToAux(s) - v.AddArg2(x, y) + v.reset(OpAMD64CMOVQHI) + v.AddArg3(yes, no, flags) return true } break } - // match: (LEAQ1 [c] {s} x z:(ADDQ y y)) - // cond: x != z - // result: (LEAQ2 [c] {s} x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETB flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQCS yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - z := v_1 - if z.Op != OpAMD64ADDQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETB { continue } - y := z.Args[1] - if y != z.Args[0] || !(x != z) { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v.reset(OpAMD64LEAQ2) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + v.reset(OpAMD64CMOVQCS) + v.AddArg3(yes, no, flags) return true } break } - // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) - // result: (LEAQ4 [c] {s} x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETAE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQCC yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETAE { continue } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ4) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQCC) + v.AddArg3(yes, no, flags) return true } break } - // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) - // result: (LEAQ8 [c] {s} x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETBE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQLS yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETBE { continue } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ8) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQLS) + v.AddArg3(yes, no, flags) return true } break } - // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETEQF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQEQF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQF { continue } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - x := v_0.Args[0] - y := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v.reset(OpAMD64LEAQ1) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(x, y) + v.reset(OpAMD64CMOVQEQF) + v.AddArg3(yes, no, flags) return true } break } - // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETNEF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQNEF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64LEAQ1 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNEF { continue } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - y := v_1.Args[1] - if y != v_1.Args[0] || !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v.reset(OpAMD64LEAQ2) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(x, y) + v.reset(OpAMD64CMOVQNEF) + v.AddArg3(yes, no, flags) return true } break } - // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) + // match: (CMOVQNE yes no t:(TESTB s:(SETGF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQGTF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64LEAQ1 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGF { continue } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if x != v_1_0 { - continue - } - y := v_1_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - continue - } - v.reset(OpAMD64LEAQ2) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(y, x) - return true + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue } + v.reset(OpAMD64CMOVQGTF) + v.AddArg3(yes, no, flags) + return true } break } - // match: (LEAQ1 [0] x y) - // cond: v.Aux == nil - // result: (ADDQ x y) + // match: (CMOVQNE yes no t:(TESTB s:(SETGEF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVQGEF yes no flags) for { - if auxIntToInt32(v.AuxInt) != 0 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - x := v_0 - y := v_1 - if !(v.Aux == nil) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVQGEF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64ADDQ) - v.AddArg2(x, y) - return true + break } return false } -func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVWCC(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) - // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB - // result: (LEAQ2 [c+d] {s} x y) + // match: (CMOVWCC x y (InvertFlags cond)) + // result: (CMOVWLS x y cond) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { - break - } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] + x := v_0 y := v_1 - if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { + if v_2.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64LEAQ2) - v.AuxInt = int32ToAuxInt(c + d) - v.Aux = symToAux(s) - v.AddArg2(x, y) + cond := v_2.Args[0] + v.reset(OpAMD64CMOVWLS) + v.AddArg3(x, y, cond) return true } - // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) - // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB - // result: (LEAQ2 [c+2*d] {s} x y) + // match: (CMOVWCC _ x (FlagEQ)) + // result: x for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64ADDQconst { + x := v_1 + if v_2.Op != OpAMD64FlagEQ { break } - d := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ2) - v.AuxInt = int32ToAuxInt(c + 2*d) - v.Aux = symToAux(s) - v.AddArg2(x, y) + v.copyOf(x) return true } - // match: (LEAQ2 [c] {s} x z:(ADDQ y y)) - // cond: x != z - // result: (LEAQ4 [c] {s} x y) + // match: (CMOVWCC _ x (FlagGT_UGT)) + // result: x for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - z := v_1 - if z.Op != OpAMD64ADDQ { - break - } - y := z.Args[1] - if y != z.Args[0] || !(x != z) { + x := v_1 + if v_2.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64LEAQ4) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + v.copyOf(x) return true } - // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) - // result: (LEAQ8 [c] {s} x y) + // match: (CMOVWCC y _ (FlagGT_ULT)) + // result: y for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { + y := v_0 + if v_2.Op != OpAMD64FlagGT_ULT { break } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ8) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + v.copyOf(y) return true } - // match: (LEAQ2 [0] {s} (ADDQ x x) x) - // cond: s == nil - // result: (SHLQconst [2] x) + // match: (CMOVWCC y _ (FlagLT_ULT)) + // result: y for { - if auxIntToInt32(v.AuxInt) != 0 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQ { - break - } - x := v_0.Args[1] - if x != v_0.Args[0] || x != v_1 || !(s == nil) { + y := v_0 + if v_2.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64SHLQconst) - v.AuxInt = int8ToAuxInt(2) - v.AddArg(x) + v.copyOf(y) return true } - // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) + // match: (CMOVWCC _ x (FlagLT_UGT)) + // result: x for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { - break - } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - x := v_0.Args[0] - y := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { + x := v_1 + if v_2.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64LEAQ2) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(x, y) + v.copyOf(x) return true } - // match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) - // cond: is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil - // result: (LEAQ4 [off1+2*off2] {sym1} x y) + return false +} +func rewriteValueAMD64_OpAMD64CMOVWCS(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMOVWCS x y (InvertFlags cond)) + // result: (CMOVWHI x y cond) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) x := v_0 - if v_1.Op != OpAMD64LEAQ1 { + y := v_1 + if v_2.Op != OpAMD64InvertFlags { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - y := v_1.Args[1] - if y != v_1.Args[0] || !(is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) { + cond := v_2.Args[0] + v.reset(OpAMD64CMOVWHI) + v.AddArg3(x, y, cond) + return true + } + // match: (CMOVWCS y _ (FlagEQ)) + // result: y + for { + y := v_0 + if v_2.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64LEAQ4) - v.AuxInt = int32ToAuxInt(off1 + 2*off2) - v.Aux = symToAux(sym1) - v.AddArg2(x, y) + v.copyOf(y) return true } - // match: (LEAQ2 [off] {sym} x (MOVQconst [scale])) - // cond: is32Bit(int64(off)+int64(scale)*2) - // result: (LEAQ [off+int32(scale)*2] {sym} x) + // match: (CMOVWCS y _ (FlagGT_UGT)) + // result: y for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + y := v_0 + if v_2.Op != OpAMD64FlagGT_UGT { break } - scale := auxIntToInt64(v_1.AuxInt) - if !(is32Bit(int64(off) + int64(scale)*2)) { + v.copyOf(y) + return true + } + // match: (CMOVWCS _ x (FlagGT_ULT)) + // result: x + for { + x := v_1 + if v_2.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64LEAQ) - v.AuxInt = int32ToAuxInt(off + int32(scale)*2) - v.Aux = symToAux(sym) - v.AddArg(x) + v.copyOf(x) return true } - // match: (LEAQ2 [off] {sym} x (MOVLconst [scale])) - // cond: is32Bit(int64(off)+int64(scale)*2) - // result: (LEAQ [off+int32(scale)*2] {sym} x) + // match: (CMOVWCS _ x (FlagLT_ULT)) + // result: x for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + x := v_1 + if v_2.Op != OpAMD64FlagLT_ULT { break } - scale := auxIntToInt32(v_1.AuxInt) - if !(is32Bit(int64(off) + int64(scale)*2)) { + v.copyOf(x) + return true + } + // match: (CMOVWCS y _ (FlagLT_UGT)) + // result: y + for { + y := v_0 + if v_2.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64LEAQ) - v.AuxInt = int32ToAuxInt(off + int32(scale)*2) - v.Aux = symToAux(sym) - v.AddArg(x) + v.copyOf(y) return true } return false } -func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVWEQ(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) - // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB - // result: (LEAQ4 [c+d] {s} x y) + // match: (CMOVWEQ x y (InvertFlags cond)) + // result: (CMOVWEQ x y cond) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { - break - } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] + x := v_0 y := v_1 - if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { + if v_2.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64LEAQ4) - v.AuxInt = int32ToAuxInt(c + d) - v.Aux = symToAux(s) - v.AddArg2(x, y) + cond := v_2.Args[0] + v.reset(OpAMD64CMOVWEQ) + v.AddArg3(x, y, cond) return true } - // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) - // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB - // result: (LEAQ4 [c+4*d] {s} x y) + // match: (CMOVWEQ _ x (FlagEQ)) + // result: x for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - d := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { + x := v_1 + if v_2.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64LEAQ4) - v.AuxInt = int32ToAuxInt(c + 4*d) - v.Aux = symToAux(s) - v.AddArg2(x, y) + v.copyOf(x) return true } - // match: (LEAQ4 [c] {s} x z:(ADDQ y y)) - // cond: x != z - // result: (LEAQ8 [c] {s} x y) + // match: (CMOVWEQ y _ (FlagGT_UGT)) + // result: y for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - z := v_1 - if z.Op != OpAMD64ADDQ { + y := v_0 + if v_2.Op != OpAMD64FlagGT_UGT { break } - y := z.Args[1] - if y != z.Args[0] || !(x != z) { + v.copyOf(y) + return true + } + // match: (CMOVWEQ y _ (FlagGT_ULT)) + // result: y + for { + y := v_0 + if v_2.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64LEAQ8) - v.AuxInt = int32ToAuxInt(c) - v.Aux = symToAux(s) - v.AddArg2(x, y) + v.copyOf(y) return true } - // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) + // match: (CMOVWEQ y _ (FlagLT_ULT)) + // result: y for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + y := v_0 + if v_2.Op != OpAMD64FlagLT_ULT { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - x := v_0.Args[0] - y := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { + v.copyOf(y) + return true + } + // match: (CMOVWEQ y _ (FlagLT_UGT)) + // result: y + for { + y := v_0 + if v_2.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64LEAQ4) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(x, y) + v.copyOf(y) return true } - // match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) - // cond: is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil - // result: (LEAQ8 [off1+4*off2] {sym1} x y) + // match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWNE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64LEAQ1 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - y := v_1.Args[1] - if y != v_1.Args[0] || !(is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ8) - v.AuxInt = int32ToAuxInt(off1 + 4*off2) - v.Aux = symToAux(sym1) - v.AddArg2(x, y) - return true + break } - // match: (LEAQ4 [off] {sym} x (MOVQconst [scale])) - // cond: is32Bit(int64(off)+int64(scale)*4) - // result: (LEAQ [off+int32(scale)*4] {sym} x) + // match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWEQ yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - scale := auxIntToInt64(v_1.AuxInt) - if !(is32Bit(int64(off) + int64(scale)*4)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQ) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ) - v.AuxInt = int32ToAuxInt(off + int32(scale)*4) - v.Aux = symToAux(sym) - v.AddArg(x) - return true + break } - // match: (LEAQ4 [off] {sym} x (MOVLconst [scale])) - // cond: is32Bit(int64(off)+int64(scale)*4) - // result: (LEAQ [off+int32(scale)*4] {sym} x) + // match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGE yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - scale := auxIntToInt32(v_1.AuxInt) - if !(is32Bit(int64(off) + int64(scale)*4)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ) - v.AuxInt = int32ToAuxInt(off + int32(scale)*4) - v.Aux = symToAux(sym) - v.AddArg(x) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) - // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB - // result: (LEAQ8 [c+d] {s} x y) + // match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLE yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - y := v_1 - if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ8) - v.AuxInt = int32ToAuxInt(c + d) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true + break } - // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) - // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB - // result: (LEAQ8 [c+8*d] {s} x y) + // match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGT yes no flags) for { - c := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - d := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ8) - v.AuxInt = int32ToAuxInt(c + 8*d) - v.Aux = symToAux(s) - v.AddArg2(x, y) - return true + break } - // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) + // match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLT yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - x := v_0.Args[0] - y := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ8) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(x, y) - return true + break } - // match: (LEAQ8 [off] {sym} x (MOVQconst [scale])) - // cond: is32Bit(int64(off)+int64(scale)*8) - // result: (LEAQ [off+int32(scale)*8] {sym} x) + // match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLS yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - scale := auxIntToInt64(v_1.AuxInt) - if !(is32Bit(int64(off) + int64(scale)*8)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ) - v.AuxInt = int32ToAuxInt(off + int32(scale)*8) - v.Aux = symToAux(sym) - v.AddArg(x) - return true + break } - // match: (LEAQ8 [off] {sym} x (MOVLconst [scale])) - // cond: is32Bit(int64(off)+int64(scale)*8) - // result: (LEAQ [off+int32(scale)*8] {sym} x) + // match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCC yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - scale := auxIntToInt32(v_1.AuxInt) - if !(is32Bit(int64(off) + int64(scale)*8)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCC) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64LEAQ) - v.AuxInt = int32ToAuxInt(off + int32(scale)*8) - v.Aux = symToAux(sym) - v.AddArg(x) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64LoweredPanicBoundsCR(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (LoweredPanicBoundsCR [kind] {p} (MOVQconst [c]) mem) - // result: (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:p.C, Cy:c}} mem) + // match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCS yes no flags) for { - kind := auxIntToInt64(v.AuxInt) - p := auxToPanicBoundsC(v.Aux) - if v_0.Op != OpAMD64MOVQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - c := auxIntToInt64(v_0.AuxInt) - mem := v_1 - v.reset(OpAMD64LoweredPanicBoundsCC) - v.AuxInt = int64ToAuxInt(kind) - v.Aux = panicBoundsCCToAux(PanicBoundsCC{Cx: p.C, Cy: c}) - v.AddArg(mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCS) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64LoweredPanicBoundsRC(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (LoweredPanicBoundsRC [kind] {p} (MOVQconst [c]) mem) - // result: (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:c, Cy:p.C}} mem) + // match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWHI yes no flags) for { - kind := auxIntToInt64(v.AuxInt) - p := auxToPanicBoundsC(v.Aux) - if v_0.Op != OpAMD64MOVQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - c := auxIntToInt64(v_0.AuxInt) - mem := v_1 - v.reset(OpAMD64LoweredPanicBoundsCC) - v.AuxInt = int64ToAuxInt(kind) - v.Aux = panicBoundsCCToAux(PanicBoundsCC{Cx: c, Cy: p.C}) - v.AddArg(mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWHI) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64LoweredPanicBoundsRR(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (LoweredPanicBoundsRR [kind] x (MOVQconst [c]) mem) - // result: (LoweredPanicBoundsRC [kind] x {PanicBoundsC{C:c}} mem) + // match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWNE yes no flags) for { - kind := auxIntToInt64(v.AuxInt) - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - c := auxIntToInt64(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64LoweredPanicBoundsRC) - v.AuxInt = int64ToAuxInt(kind) - v.Aux = panicBoundsCToAux(PanicBoundsC{C: c}) - v.AddArg2(x, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (LoweredPanicBoundsRR [kind] (MOVQconst [c]) y mem) - // result: (LoweredPanicBoundsCR [kind] {PanicBoundsC{C:c}} y mem) + // match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWEQ yes no flags) for { - kind := auxIntToInt64(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - c := auxIntToInt64(v_0.AuxInt) - y := v_1 - mem := v_2 - v.reset(OpAMD64LoweredPanicBoundsCR) - v.AuxInt = int64ToAuxInt(kind) - v.Aux = panicBoundsCToAux(PanicBoundsC{C: c}) - v.AddArg2(y, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVBELstore(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVBELstore [i] {s} p x:(BSWAPL w) mem) - // cond: x.Uses == 1 - // result: (MOVLstore [i] {s} p w mem) + // match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGE yes no flags) for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - x := v_1 - if x.Op != OpAMD64BSWAPL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - w := x.Args[0] - mem := v_2 - if !(x.Uses == 1) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVBEQstore(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVBEQstore [i] {s} p x:(BSWAPQ w) mem) - // cond: x.Uses == 1 - // result: (MOVQstore [i] {s} p w mem) + // match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLE yes no flags) for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - x := v_1 - if x.Op != OpAMD64BSWAPQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - w := x.Args[0] - mem := v_2 - if !(x.Uses == 1) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVBEWstore(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) - // cond: x.Uses == 1 - // result: (MOVWstore [i] {s} p w mem) + // match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGT yes no flags) for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - x := v_1 - if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - w := x.Args[0] - mem := v_2 - if !(x.Uses == 1) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) + // match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLT yes no flags) for { - x := v_0 - if x.Op != OpAMD64MOVBload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLT) + v.AddArg3(yes, no, flags) + return true } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + break } - // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) + // match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLS yes no flags) for { - x := v_0 - if x.Op != OpAMD64MOVWload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLS) + v.AddArg3(yes, no, flags) + return true } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + break } - // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) + // match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCC yes no flags) for { - x := v_0 - if x.Op != OpAMD64MOVLload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCC) + v.AddArg3(yes, no, flags) + return true } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + break } - // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) + // match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCS yes no flags) for { - x := v_0 - if x.Op != OpAMD64MOVQload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCS) + v.AddArg3(yes, no, flags) + return true } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + break } - // match: (MOVBQSX (ANDLconst [c] x)) - // cond: c & 0x80 == 0 - // result: (ANDLconst [c & 0x7f] x) + // match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWHI yes no flags) for { - if v_0.Op != OpAMD64ANDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(c&0x80 == 0) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWHI) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64ANDLconst) - v.AuxInt = int32ToAuxInt(c & 0x7f) - v.AddArg(x) - return true + break } - // match: (MOVBQSX (MOVBQSX x)) - // result: (MOVBQSX x) + // match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWNE yes no flags) for { - if v_0.Op != OpAMD64MOVBQSX { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVBQSX) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNE) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) - // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) - // result: (MOVBQSX x) + // match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWEQ yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVBstore { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - x := v_1.Args[1] - ptr2 := v_1.Args[0] - if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQ) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVBQSX) - v.AddArg(x) - return true + break } - // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) + // match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVBQSXload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) - return true + break } - // match: (MOVBQSXload [off] {sym} (SB) _) - // cond: symIsRO(sym) - // result: (MOVQconst [int64(int8(read8(sym, int64(off))))]) + // match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLE yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpSB || !(symIsRO(sym)) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(int8(read8(sym, int64(off))))) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLE) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVBload [off] {sym} ptr mem) + // match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGT yes no flags) for { - x := v_0 - if x.Op != OpAMD64MOVBload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGT) + v.AddArg3(yes, no, flags) + return true } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + break } - // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVBload [off] {sym} ptr mem) + // match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLT yes no flags) for { - x := v_0 - if x.Op != OpAMD64MOVWload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLT) + v.AddArg3(yes, no, flags) + return true } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + break } - // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVBload [off] {sym} ptr mem) + // match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLS yes no flags) for { - x := v_0 - if x.Op != OpAMD64MOVLload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLS) + v.AddArg3(yes, no, flags) + return true } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + break } - // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVBload [off] {sym} ptr mem) + // match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCC yes no flags) for { - x := v_0 - if x.Op != OpAMD64MOVQload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCC) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCS yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVBQZX (ANDLconst [c] x)) - // result: (ANDLconst [c & 0xff] x) + // match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWHI yes no flags) for { - if v_0.Op != OpAMD64ANDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ANDLconst) - v.AuxInt = int32ToAuxInt(c & 0xff) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWHI) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVBQZX (MOVBQZX x)) - // result: (MOVBQZX x) + // match: (CMOVWEQ yes no t:(TESTB s:(SETEQ flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWNE yes no flags) for { - if v_0.Op != OpAMD64MOVBQZX { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVBQZX) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNE) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVBatomicload [off1+off2] {sym} ptr mem) + // match: (CMOVWEQ yes no t:(TESTB s:(SETNE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWEQ yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQ) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVBatomicload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + break } - // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) + // match: (CMOVWEQ yes no t:(TESTB s:(SETL flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWGE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - ptr := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVBatomicload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(ptr, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) - // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) - // result: (MOVBQZX x) + // match: (CMOVWEQ yes no t:(TESTB s:(SETG flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWLE yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVBstore { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - x := v_1.Args[1] - ptr2 := v_1.Args[0] - if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLE) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVWEQ yes no t:(TESTB s:(SETLE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWGT yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.reset(OpAMD64MOVBQZX) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVBload [off1+off2] {sym} ptr mem) + // match: (CMOVWEQ yes no t:(TESTB s:(SETGE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWLT yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1) + int64(off2))) { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLT) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVWEQ yes no t:(TESTB s:(SETA flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWLS yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.reset(OpAMD64MOVBload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) + // match: (CMOVWEQ yes no t:(TESTB s:(SETB flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWCC yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCC) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVWEQ yes no t:(TESTB s:(SETAE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWCS yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.reset(OpAMD64MOVBload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVBload [off] {sym} (SB) _) - // cond: symIsRO(sym) - // result: (MOVLconst [int32(read8(sym, int64(off)))]) + // match: (CMOVWEQ yes no t:(TESTB s:(SETBE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWHI yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpSB || !(symIsRO(sym)) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(int32(read8(sym, int64(off)))) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWHI) + v.AddArg3(yes, no, flags) + return true + } + break } return false } -func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVWGE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) - // cond: y.Uses == 1 - // result: (SETLstore [off] {sym} ptr x mem) + // match: (CMOVWGE x y (InvertFlags cond)) + // result: (CMOVWLE x y cond) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 + x := v_0 y := v_1 - if y.Op != OpAMD64SETL { + if v_2.Op != OpAMD64InvertFlags { break } - x := y.Args[0] - mem := v_2 - if !(y.Uses == 1) { + cond := v_2.Args[0] + v.reset(OpAMD64CMOVWLE) + v.AddArg3(x, y, cond) + return true + } + // match: (CMOVWGE _ x (FlagEQ)) + // result: x + for { + x := v_1 + if v_2.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64SETLstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(x) return true } - // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) - // cond: y.Uses == 1 - // result: (SETLEstore [off] {sym} ptr x mem) + // match: (CMOVWGE _ x (FlagGT_UGT)) + // result: x for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64SETLE { + x := v_1 + if v_2.Op != OpAMD64FlagGT_UGT { break } - x := y.Args[0] - mem := v_2 - if !(y.Uses == 1) { + v.copyOf(x) + return true + } + // match: (CMOVWGE _ x (FlagGT_ULT)) + // result: x + for { + x := v_1 + if v_2.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64SETLEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(x) return true } - // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) - // cond: y.Uses == 1 - // result: (SETGstore [off] {sym} ptr x mem) + // match: (CMOVWGE y _ (FlagLT_ULT)) + // result: y for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64SETG { + y := v_0 + if v_2.Op != OpAMD64FlagLT_ULT { break } - x := y.Args[0] - mem := v_2 - if !(y.Uses == 1) { + v.copyOf(y) + return true + } + // match: (CMOVWGE y _ (FlagLT_UGT)) + // result: y + for { + y := v_0 + if v_2.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64SETGstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(y) return true } - // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) - // cond: y.Uses == 1 - // result: (SETGEstore [off] {sym} ptr x mem) + return false +} +func rewriteValueAMD64_OpAMD64CMOVWGT(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMOVWGT x y (InvertFlags cond)) + // result: (CMOVWLT x y cond) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 + x := v_0 y := v_1 - if y.Op != OpAMD64SETGE { + if v_2.Op != OpAMD64InvertFlags { break } - x := y.Args[0] - mem := v_2 - if !(y.Uses == 1) { + cond := v_2.Args[0] + v.reset(OpAMD64CMOVWLT) + v.AddArg3(x, y, cond) + return true + } + // match: (CMOVWGT y _ (FlagEQ)) + // result: y + for { + y := v_0 + if v_2.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64SETGEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(y) return true } - // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) - // cond: y.Uses == 1 - // result: (SETEQstore [off] {sym} ptr x mem) + // match: (CMOVWGT _ x (FlagGT_UGT)) + // result: x for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64SETEQ { + x := v_1 + if v_2.Op != OpAMD64FlagGT_UGT { break } - x := y.Args[0] - mem := v_2 - if !(y.Uses == 1) { + v.copyOf(x) + return true + } + // match: (CMOVWGT _ x (FlagGT_ULT)) + // result: x + for { + x := v_1 + if v_2.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64SETEQstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(x) return true } - // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) - // cond: y.Uses == 1 - // result: (SETNEstore [off] {sym} ptr x mem) + // match: (CMOVWGT y _ (FlagLT_ULT)) + // result: y for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64SETNE { + y := v_0 + if v_2.Op != OpAMD64FlagLT_ULT { break } - x := y.Args[0] - mem := v_2 - if !(y.Uses == 1) { + v.copyOf(y) + return true + } + // match: (CMOVWGT y _ (FlagLT_UGT)) + // result: y + for { + y := v_0 + if v_2.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64SETNEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(y) return true } - // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) - // cond: y.Uses == 1 - // result: (SETBstore [off] {sym} ptr x mem) + return false +} +func rewriteValueAMD64_OpAMD64CMOVWHI(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMOVWHI x y (InvertFlags cond)) + // result: (CMOVWCS x y cond) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 + x := v_0 y := v_1 - if y.Op != OpAMD64SETB { + if v_2.Op != OpAMD64InvertFlags { break } - x := y.Args[0] - mem := v_2 - if !(y.Uses == 1) { + cond := v_2.Args[0] + v.reset(OpAMD64CMOVWCS) + v.AddArg3(x, y, cond) + return true + } + // match: (CMOVWHI y _ (FlagEQ)) + // result: y + for { + y := v_0 + if v_2.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(y) return true } - // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) - // cond: y.Uses == 1 - // result: (SETBEstore [off] {sym} ptr x mem) + // match: (CMOVWHI _ x (FlagGT_UGT)) + // result: x for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64SETBE { + x := v_1 + if v_2.Op != OpAMD64FlagGT_UGT { break } - x := y.Args[0] - mem := v_2 - if !(y.Uses == 1) { + v.copyOf(x) + return true + } + // match: (CMOVWHI y _ (FlagGT_ULT)) + // result: y + for { + y := v_0 + if v_2.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64SETBEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(y) return true } - // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) - // cond: y.Uses == 1 - // result: (SETAstore [off] {sym} ptr x mem) + // match: (CMOVWHI y _ (FlagLT_ULT)) + // result: y for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64SETA { + y := v_0 + if v_2.Op != OpAMD64FlagLT_ULT { break } - x := y.Args[0] - mem := v_2 - if !(y.Uses == 1) { + v.copyOf(y) + return true + } + // match: (CMOVWHI _ x (FlagLT_UGT)) + // result: x + for { + x := v_1 + if v_2.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64SETAstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(x) return true } - // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) - // cond: y.Uses == 1 - // result: (SETAEstore [off] {sym} ptr x mem) + return false +} +func rewriteValueAMD64_OpAMD64CMOVWLE(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMOVWLE x y (InvertFlags cond)) + // result: (CMOVWGE x y cond) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 + x := v_0 y := v_1 - if y.Op != OpAMD64SETAE { - break - } - x := y.Args[0] - mem := v_2 - if !(y.Uses == 1) { + if v_2.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + cond := v_2.Args[0] + v.reset(OpAMD64CMOVWGE) + v.AddArg3(x, y, cond) return true } - // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) - // result: (MOVBstore [off] {sym} ptr x mem) + // match: (CMOVWLE _ x (FlagEQ)) + // result: x for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVBQSX { + x := v_1 + if v_2.Op != OpAMD64FlagEQ { break } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(x) return true } - // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) - // result: (MOVBstore [off] {sym} ptr x mem) + // match: (CMOVWLE y _ (FlagGT_UGT)) + // result: y for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVBQZX { + y := v_0 + if v_2.Op != OpAMD64FlagGT_UGT { break } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.copyOf(y) return true } - // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVBstore [off1+off2] {sym} ptr val mem) + // match: (CMOVWLE y _ (FlagGT_ULT)) + // result: y for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { - break - } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + y := v_0 + if v_2.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(ptr, val, mem) + v.copyOf(y) return true } - // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) - // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) + // match: (CMOVWLE _ x (FlagLT_ULT)) + // result: x for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLconst { + x := v_1 + if v_2.Op != OpAMD64FlagLT_ULT { break } - c := auxIntToInt32(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64MOVBstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) + v.copyOf(x) return true } - // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) - // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) + // match: (CMOVWLE _ x (FlagLT_UGT)) + // result: x for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVQconst { + x := v_1 + if v_2.Op != OpAMD64FlagLT_UGT { break } - c := auxIntToInt64(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64MOVBstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) + v.copyOf(x) return true } - // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + return false +} +func rewriteValueAMD64_OpAMD64CMOVWLS(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMOVWLS x y (InvertFlags cond)) + // result: (CMOVWCC x y cond) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + x := v_0 + y := v_1 + if v_2.Op != OpAMD64InvertFlags { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + cond := v_2.Args[0] + v.reset(OpAMD64CMOVWCC) + v.AddArg3(x, y, cond) + return true + } + // match: (CMOVWLS _ x (FlagEQ)) + // result: x + for { + x := v_1 + if v_2.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + v.copyOf(x) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) - // cond: ValAndOff(sc).canAdd32(off) - // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) + // match: (CMOVWLS y _ (FlagGT_UGT)) + // result: y for { - sc := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + y := v_0 + if v_2.Op != OpAMD64FlagGT_UGT { break } - off := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(ValAndOff(sc).canAdd32(off)) { + v.copyOf(y) + return true + } + // match: (CMOVWLS _ x (FlagGT_ULT)) + // result: x + for { + x := v_1 + if v_2.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64MOVBstoreconst) - v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(s) - v.AddArg2(ptr, mem) + v.copyOf(x) return true } - // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) - // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) - // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) + // match: (CMOVWLS _ x (FlagLT_ULT)) + // result: x for { - sc := auxIntToValAndOff(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + x := v_1 + if v_2.Op != OpAMD64FlagLT_ULT { break } - off := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - ptr := v_0.Args[0] - mem := v_1 - if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { + v.copyOf(x) + return true + } + // match: (CMOVWLS y _ (FlagLT_UGT)) + // result: y + for { + y := v_0 + if v_2.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64MOVBstoreconst) - v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(ptr, mem) + v.copyOf(y) return true } return false } -func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVWLT(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) + // match: (CMOVWLT x y (InvertFlags cond)) + // result: (CMOVWGT x y cond) for { x := v_0 - if x.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { + y := v_1 + if v_2.Op != OpAMD64InvertFlags { break } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) + cond := v_2.Args[0] + v.reset(OpAMD64CMOVWGT) + v.AddArg3(x, y, cond) return true } - // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) + // match: (CMOVWLT y _ (FlagEQ)) + // result: y for { - x := v_0 - if x.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { + y := v_0 + if v_2.Op != OpAMD64FlagEQ { break } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) + v.copyOf(y) return true } - // match: (MOVLQSX (ANDLconst [c] x)) - // cond: uint32(c) & 0x80000000 == 0 - // result: (ANDLconst [c & 0x7fffffff] x) + // match: (CMOVWLT y _ (FlagGT_UGT)) + // result: y for { - if v_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(uint32(c)&0x80000000 == 0) { + y := v_0 + if v_2.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64ANDLconst) - v.AuxInt = int32ToAuxInt(c & 0x7fffffff) - v.AddArg(x) + v.copyOf(y) return true } - // match: (MOVLQSX (MOVLQSX x)) - // result: (MOVLQSX x) + // match: (CMOVWLT y _ (FlagGT_ULT)) + // result: y for { - if v_0.Op != OpAMD64MOVLQSX { + y := v_0 + if v_2.Op != OpAMD64FlagGT_ULT { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVLQSX) - v.AddArg(x) + v.copyOf(y) return true } - // match: (MOVLQSX (MOVWQSX x)) - // result: (MOVWQSX x) + // match: (CMOVWLT _ x (FlagLT_ULT)) + // result: x for { - if v_0.Op != OpAMD64MOVWQSX { + x := v_1 + if v_2.Op != OpAMD64FlagLT_ULT { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVWQSX) - v.AddArg(x) + v.copyOf(x) return true } - // match: (MOVLQSX (MOVBQSX x)) - // result: (MOVBQSX x) + // match: (CMOVWLT _ x (FlagLT_UGT)) + // result: x for { - if v_0.Op != OpAMD64MOVBQSX { + x := v_1 + if v_2.Op != OpAMD64FlagLT_UGT { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVBQSX) - v.AddArg(x) + v.copyOf(x) return true } return false } -func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMOVWNE(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) - // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) - // result: (MOVLQSX x) + // match: (CMOVWNE x y (InvertFlags cond)) + // result: (CMOVWNE x y cond) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLstore { - break - } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - x := v_1.Args[1] - ptr2 := v_1.Args[0] - if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + x := v_0 + y := v_1 + if v_2.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64MOVLQSX) - v.AddArg(x) + cond := v_2.Args[0] + v.reset(OpAMD64CMOVWNE) + v.AddArg3(x, y, cond) return true } - // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) + // match: (CMOVWNE y _ (FlagEQ)) + // result: y for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + y := v_0 + if v_2.Op != OpAMD64FlagEQ { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + v.copyOf(y) + return true + } + // match: (CMOVWNE _ x (FlagGT_UGT)) + // result: x + for { + x := v_1 + if v_2.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64MOVLQSXload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) + v.copyOf(x) return true } - // match: (MOVLQSXload [off] {sym} (SB) _) - // cond: symIsRO(sym) - // result: (MOVQconst [int64(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder)))]) + // match: (CMOVWNE _ x (FlagGT_ULT)) + // result: x for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpSB || !(symIsRO(sym)) { + x := v_1 + if v_2.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder)))) + v.copyOf(x) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVLload [off] {sym} ptr mem) + // match: (CMOVWNE _ x (FlagLT_ULT)) + // result: x for { - x := v_0 - if x.Op != OpAMD64MOVLload { + x := v_1 + if v_2.Op != OpAMD64FlagLT_ULT { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { + v.copyOf(x) + return true + } + // match: (CMOVWNE _ x (FlagLT_UGT)) + // result: x + for { + x := v_1 + if v_2.Op != OpAMD64FlagLT_UGT { break } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) + v.copyOf(x) return true } - // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVLload [off] {sym} ptr mem) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWEQ yes no flags) for { - x := v_0 - if x.Op != OpAMD64MOVQload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQ) + v.AddArg3(yes, no, flags) + return true } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + break } - // match: (MOVLQZX (ANDLconst [c] x)) - // result: (ANDLconst [c] x) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWNE yes no flags) for { - if v_0.Op != OpAMD64ANDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ANDLconst) - v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVLQZX (MOVLQZX x)) - // result: (MOVLQZX x) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLT yes no flags) for { - if v_0.Op != OpAMD64MOVLQZX { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVLQZX) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVLQZX (MOVWQZX x)) - // result: (MOVWQZX x) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGT yes no flags) for { - if v_0.Op != OpAMD64MOVWQZX { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVWQZX) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVLQZX (MOVBQZX x)) - // result: (MOVBQZX x) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLE yes no flags) for { - if v_0.Op != OpAMD64MOVBQZX { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVBQZX) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLE) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVLatomicload [off1+off2] {sym} ptr mem) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLatomicload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + break } - // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWHI yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - ptr := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWHI) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLatomicload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(ptr, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVLf2i(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (MOVLf2i (Arg [off] {sym})) - // cond: t.Size() == u.Size() - // result: @b.Func.Entry (Arg [off] {sym}) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCS yes no flags) for { - t := v.Type - if v_0.Op != OpArg { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - u := v_0.Type - off := auxIntToInt32(v_0.AuxInt) - sym := auxToSym(v_0.Aux) - if !(t.Size() == u.Size()) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCS) + v.AddArg3(yes, no, flags) + return true } - b = b.Func.Entry - v0 := b.NewValue0(v.Pos, OpArg, t) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVLi2f(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (MOVLi2f (Arg [off] {sym})) - // cond: t.Size() == u.Size() - // result: @b.Func.Entry (Arg [off] {sym}) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCC yes no flags) for { - t := v.Type - if v_0.Op != OpArg { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - u := v_0.Type - off := auxIntToInt32(v_0.AuxInt) - sym := auxToSym(v_0.Aux) - if !(t.Size() == u.Size()) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCC) + v.AddArg3(yes, no, flags) + return true } - b = b.Func.Entry - v0 := b.NewValue0(v.Pos, OpArg, t) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) - // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) - // result: (MOVLQZX x) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLS yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLstore { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - x := v_1.Args[1] - ptr2 := v_1.Args[0] - if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLQZX) - v.AddArg(x) - return true + break } - // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVLload [off1+off2] {sym} ptr mem) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWEQF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + break } - // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWNEF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNEF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) - return true + break } - // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) - // result: (MOVLf2i val) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGTF yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVSSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - val := v_1.Args[1] - if ptr != v_1.Args[0] { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGTF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLf2i) - v.AddArg(val) - return true + break } - // match: (MOVLload [off] {sym} (SB) _) - // cond: symIsRO(sym) - // result: (MOVLconst [int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) + // match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGEF yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpSB || !(symIsRO(sym)) { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) - // result: (MOVLstore [off] {sym} ptr x mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLQSX { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGEF) + v.AddArg3(yes, no, flags) + return true } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + break } - // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) - // result: (MOVLstore [off] {sym} ptr x mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWEQ yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLQZX { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVLstore [off1+off2] {sym} ptr val mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWNE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(ptr, val, mem) - return true + break } - // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) - // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLT yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - c := auxIntToInt32(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true - } - // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) - // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVQconst { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLT) + v.AddArg3(yes, no, flags) + return true } - c := auxIntToInt64(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + break } - // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGT yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) - return true + break } - // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) - // cond: y.Uses==1 && clobber(y) - // result: (ADDLmodify [off] {sym} ptr x mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLE yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ADDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - mem := y.Args[2] - x := y.Args[0] - if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64ADDLmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + break } - // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) - // cond: y.Uses==1 && clobber(y) - // result: (ANDLmodify [off] {sym} ptr x mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGE yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ANDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - mem := y.Args[2] - x := y.Args[0] - if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64ANDLmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + break } - // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) - // cond: y.Uses==1 && clobber(y) - // result: (ORLmodify [off] {sym} ptr x mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWHI yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - mem := y.Args[2] - x := y.Args[0] - if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWHI) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64ORLmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + break } - // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) - // cond: y.Uses==1 && clobber(y) - // result: (XORLmodify [off] {sym} ptr x mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCS yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64XORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - mem := y.Args[2] - x := y.Args[0] - if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64XORLmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + break } - // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) - // result: (ADDLmodify [off] {sym} ptr x mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCC yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ADDL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - _ = y.Args[1] - y_0 := y.Args[0] - y_1 := y.Args[1] - for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { - l := y_0 - if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - mem := l.Args[1] - if ptr != l.Args[0] { + s := x.Args[0] + if s.Op != OpAMD64SETAE { continue } - x := y_1 - if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v.reset(OpAMD64ADDLmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.reset(OpAMD64CMOVWCC) + v.AddArg3(yes, no, flags) return true } break } - // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) - // result: (SUBLmodify [off] {sym} ptr x mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLS yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64SUBL { - break - } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - mem := l.Args[1] - if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64SUBLmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + break } - // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) - // result: (ANDLmodify [off] {sym} ptr x mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWEQF yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ANDL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - _ = y.Args[1] - y_0 := y.Args[0] - y_1 := y.Args[1] - for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { - l := y_0 - if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - mem := l.Args[1] - if ptr != l.Args[0] { + s := x.Args[0] + if s.Op != OpAMD64SETEQF { continue } - x := y_1 - if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v.reset(OpAMD64ANDLmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.reset(OpAMD64CMOVWEQF) + v.AddArg3(yes, no, flags) return true } break } - // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) - // result: (ORLmodify [off] {sym} ptr x mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWNEF yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ORL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - _ = y.Args[1] - y_0 := y.Args[0] - y_1 := y.Args[1] - for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { - l := y_0 - if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - mem := l.Args[1] - if ptr != l.Args[0] { + s := x.Args[0] + if s.Op != OpAMD64SETNEF { continue } - x := y_1 - if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v.reset(OpAMD64ORLmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.reset(OpAMD64CMOVWNEF) + v.AddArg3(yes, no, flags) return true } break } - // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) - // result: (XORLmodify [off] {sym} ptr x mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGTF yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64XORL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - _ = y.Args[1] - y_0 := y.Args[0] - y_1 := y.Args[1] - for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { - l := y_0 - if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - mem := l.Args[1] - if ptr != l.Args[0] { + s := x.Args[0] + if s.Op != OpAMD64SETGF { continue } - x := y_1 - if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v.reset(OpAMD64XORLmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.reset(OpAMD64CMOVWGTF) + v.AddArg3(yes, no, flags) return true } break } - // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) - // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) - // result: (ADDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGEF yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - a := v_1 - if a.Op != OpAMD64ADDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTL { break } - c := auxIntToInt32(a.AuxInt) - l := a.Args[0] - if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGEF) + v.AddArg3(yes, no, flags) + return true } - mem := l.Args[1] - ptr2 := l.Args[0] - if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWEQ yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64ADDLconstmodify) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQ) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) - // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) - // result: (ANDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWNE yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - a := v_1 - if a.Op != OpAMD64ANDLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - c := auxIntToInt32(a.AuxInt) - l := a.Args[0] - if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNE) + v.AddArg3(yes, no, flags) + return true } - mem := l.Args[1] - ptr2 := l.Args[0] - if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLT yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64ANDLconstmodify) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLT) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) - // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) - // result: (ORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGT yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - a := v_1 - if a.Op != OpAMD64ORLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - c := auxIntToInt32(a.AuxInt) - l := a.Args[0] - if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGT) + v.AddArg3(yes, no, flags) + return true } - mem := l.Args[1] - ptr2 := l.Args[0] - if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLE yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64ORLconstmodify) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLE) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) - // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) - // result: (XORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGE yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - a := v_1 - if a.Op != OpAMD64XORLconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - c := auxIntToInt32(a.AuxInt) - l := a.Args[0] - if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGE) + v.AddArg3(yes, no, flags) + return true } - mem := l.Args[1] - ptr2 := l.Args[0] - if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWHI yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64XORLconstmodify) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWHI) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) - // result: (MOVSSstore [off] {sym} ptr val mem) + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCS yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLf2i { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - val := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64MOVSSstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, val, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCS) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVLstore [i] {s} p x:(BSWAPL w) mem) - // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 - // result: (MOVBELstore [i] {s} p w mem) + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWCC yes no flags) for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - x := v_1 - if x.Op != OpAMD64BSWAPL { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - w := x.Args[0] - mem := v_2 - if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCC) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVBELstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) - // cond: ValAndOff(sc).canAdd32(off) - // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWLS yes no flags) for { - sc := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(ValAndOff(sc).canAdd32(off)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLS) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(s) - v.AddArg2(ptr, mem) - return true + break } - // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) - // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) - // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWEQF yes no flags) for { - sc := auxIntToValAndOff(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - ptr := v_0.Args[0] - mem := v_1 - if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(ptr, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVOload [off1+off2] {sym} ptr mem) + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWNEF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNEF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVOload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + break } - // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGTF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGTF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVOload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVOstore [off1+off2] {sym} ptr val mem) + // match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: (CMOVWGEF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTW { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGEF) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVOstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(ptr, val, mem) - return true + break } - // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (CMOVWNE yes no t:(TESTB s:(SETEQ flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWEQ yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQ) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVOstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) - return true + break } - // match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) - // cond: symIsRO(srcSym) - // result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem)) + // match: (CMOVWNE yes no t:(TESTB s:(SETNE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWNE yes no flags) for { - dstOff := auxIntToInt32(v.AuxInt) - dstSym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVOload { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - srcOff := auxIntToInt32(v_1.AuxInt) - srcSym := auxToSym(v_1.Aux) - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpSB { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNE) + v.AddArg3(yes, no, flags) + return true } - mem := v_2 - if !(symIsRO(srcSym)) { + break + } + // match: (CMOVWNE yes no t:(TESTB s:(SETL flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWLT yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(dstOff + 8) - v.Aux = symToAux(dstSym) - v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))) - v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem) - v1.AuxInt = int32ToAuxInt(dstOff) - v1.Aux = symToAux(dstSym) - v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) - v2.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))) - v1.AddArg3(ptr, v2, mem) - v.AddArg3(ptr, v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLT) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVOstoreconst(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem) - // cond: ValAndOff(sc).canAdd32(off) - // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) + // match: (CMOVWNE yes no t:(TESTB s:(SETG flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWGT yes no flags) for { - sc := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(ValAndOff(sc).canAdd32(off)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGT) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVOstoreconst) - v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(s) - v.AddArg2(ptr, mem) - return true + break } - // match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) - // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) - // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) + // match: (CMOVWNE yes no t:(TESTB s:(SETLE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWLE yes no flags) for { - sc := auxIntToValAndOff(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - ptr := v_0.Args[0] - mem := v_1 - if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVOstoreconst) - v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(ptr, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVQatomicload [off1+off2] {sym} ptr mem) + // match: (CMOVWNE yes no t:(TESTB s:(SETGE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWGE yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGE) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVQatomicload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true + break } - // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) + // match: (CMOVWNE yes no t:(TESTB s:(SETA flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWHI yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - ptr := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWHI) + v.AddArg3(yes, no, flags) + return true } - v.reset(OpAMD64MOVQatomicload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(ptr, mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVQf2i(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (MOVQf2i (Arg [off] {sym})) - // cond: t.Size() == u.Size() - // result: @b.Func.Entry (Arg [off] {sym}) + // match: (CMOVWNE yes no t:(TESTB s:(SETB flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWCS yes no flags) for { - t := v.Type - if v_0.Op != OpArg { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - u := v_0.Type - off := auxIntToInt32(v_0.AuxInt) - sym := auxToSym(v_0.Aux) - if !(t.Size() == u.Size()) { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCS) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVWNE yes no t:(TESTB s:(SETAE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWCC yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - b = b.Func.Entry - v0 := b.NewValue0(v.Pos, OpArg, t) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWCC) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVQi2f(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (MOVQi2f (Arg [off] {sym})) - // cond: t.Size() == u.Size() - // result: @b.Func.Entry (Arg [off] {sym}) + // match: (CMOVWNE yes no t:(TESTB s:(SETBE flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWLS yes no flags) for { - t := v.Type - if v_0.Op != OpArg { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - u := v_0.Type - off := auxIntToInt32(v_0.AuxInt) - sym := auxToSym(v_0.Aux) - if !(t.Size() == u.Size()) { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWLS) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVWNE yes no t:(TESTB s:(SETEQF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWEQF yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - b = b.Func.Entry - v0 := b.NewValue0(v.Pos, OpArg, t) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWEQF) + v.AddArg3(yes, no, flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) - // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) - // result: x + // match: (CMOVWNE yes no t:(TESTB s:(SETNEF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWNEF yes no flags) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVQstore { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - x := v_1.Args[1] - ptr2 := v_1.Args[0] - if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWNEF) + v.AddArg3(yes, no, flags) + return true + } + break + } + // match: (CMOVWNE yes no t:(TESTB s:(SETGF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWGTF yes no flags) + for { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - v.copyOf(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGTF) + v.AddArg3(yes, no, flags) + return true + } + break } - // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVQload [off1+off2] {sym} ptr mem) + // match: (CMOVWNE yes no t:(TESTB s:(SETGEF flags) s)) + // cond: t.Block == s.Block + // result: (CMOVWGEF yes no flags) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + yes := v_0 + no := v_1 + t := v_2 + if t.Op != OpAMD64TESTB { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1) + int64(off2))) { + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64CMOVWGEF) + v.AddArg3(yes, no, flags) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64CMPB(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CMPB x (MOVLconst [c])) + // result: (CMPBconst x [int8(c)]) + for { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64MOVQload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64CMPBconst) + v.AuxInt = int8ToAuxInt(int8(c)) + v.AddArg(x) return true } - // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) + // match: (CMPB (MOVLconst [c]) x) + // result: (InvertFlags (CMPBconst x [int8(c)])) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64MOVLconst { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + c := auxIntToInt32(v_0.AuxInt) + x := v_1 + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(c)) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (CMPB x y) + // cond: canonLessThan(x,y) + // result: (InvertFlags (CMPB y x)) + for { + x := v_0 + y := v_1 + if !(canonLessThan(x, y)) { break } - v.reset(OpAMD64MOVQload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) return true } - // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) - // result: (MOVQf2i val) + // match: (CMPB l:(MOVBload {sym} [off] ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (CMPBload {sym} [off] ptr x mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVSDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { + l := v_0 + if l.Op != OpAMD64MOVBload { break } - val := v_1.Args[1] - if ptr != v_1.Args[0] { + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64MOVQf2i) - v.AddArg(val) + v.reset(OpAMD64CMPBload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (MOVQload [off] {sym} (SB) _) - // cond: symIsRO(sym) - // result: (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) + // match: (CMPB x l:(MOVBload {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (InvertFlags (CMPBload {sym} [off] ptr x mem)) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpSB || !(symIsRO(sym)) { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVBload { break } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(l.Pos, OpAMD64CMPBload, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg3(ptr, x, mem) + v.AddArg(v0) return true } return false } -func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64CMPBconst(v *Value) bool { v_0 := v.Args[0] - // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVQstore [off1+off2] {sym} ptr val mem) + b := v.Block + // match: (CMPBconst (MOVLconst [x]) [y]) + // cond: int8(x)==y + // result: (FlagEQ) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + y := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + x := auxIntToInt32(v_0.AuxInt) + if !(int8(x) == y) { break } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(ptr, val, mem) + v.reset(OpAMD64FlagEQ) return true } - // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) - // cond: validVal(c) - // result: (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) + // match: (CMPBconst (MOVLconst [x]) [y]) + // cond: int8(x)uint8(y) + // result: (FlagLT_UGT) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + y := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + x := auxIntToInt32(v_0.AuxInt) + if !(int8(x) < y && uint8(x) > uint8(y)) { break } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + v.reset(OpAMD64FlagLT_UGT) return true } - // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) - // cond: y.Uses==1 && clobber(y) - // result: (ADDQmodify [off] {sym} ptr x mem) + // match: (CMPBconst (MOVLconst [x]) [y]) + // cond: int8(x)>y && uint8(x) y && uint8(x) < uint8(y)) { break } - v.reset(OpAMD64ADDQmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.reset(OpAMD64FlagGT_ULT) return true } - // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) - // cond: y.Uses==1 && clobber(y) - // result: (ANDQmodify [off] {sym} ptr x mem) + // match: (CMPBconst (MOVLconst [x]) [y]) + // cond: int8(x)>y && uint8(x)>uint8(y) + // result: (FlagGT_UGT) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ANDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { + y := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } - mem := y.Args[2] - x := y.Args[0] - if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + x := auxIntToInt32(v_0.AuxInt) + if !(int8(x) > y && uint8(x) > uint8(y)) { break } - v.reset(OpAMD64ANDQmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.reset(OpAMD64FlagGT_UGT) return true } - // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) - // cond: y.Uses==1 && clobber(y) - // result: (ORQmodify [off] {sym} ptr x mem) + // match: (CMPBconst (ANDLconst _ [m]) [n]) + // cond: 0 <= int8(m) && int8(m) < n + // result: (FlagLT_ULT) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { + n := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64ANDLconst { break } - mem := y.Args[2] - x := y.Args[0] - if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + m := auxIntToInt32(v_0.AuxInt) + if !(0 <= int8(m) && int8(m) < n) { break } - v.reset(OpAMD64ORQmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.reset(OpAMD64FlagLT_ULT) return true } - // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) - // cond: y.Uses==1 && clobber(y) - // result: (XORQmodify [off] {sym} ptr x mem) + // match: (CMPBconst a:(ANDL x y) [0]) + // cond: a.Uses == 1 + // result: (TESTB x y) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64XORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { + if auxIntToInt8(v.AuxInt) != 0 { break } - mem := y.Args[2] - x := y.Args[0] - if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + a := v_0 + if a.Op != OpAMD64ANDL { break } - v.reset(OpAMD64XORQmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + y := a.Args[1] + x := a.Args[0] + if !(a.Uses == 1) { + break + } + v.reset(OpAMD64TESTB) + v.AddArg2(x, y) return true } - // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) - // result: (ADDQmodify [off] {sym} ptr x mem) + // match: (CMPBconst a:(ANDLconst [c] x) [0]) + // cond: a.Uses == 1 + // result: (TESTBconst [int8(c)] x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ADDQ { + if auxIntToInt8(v.AuxInt) != 0 { break } - _ = y.Args[1] - y_0 := y.Args[0] - y_1 := y.Args[1] - for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { - l := y_0 - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { - continue - } - mem := l.Args[1] - if ptr != l.Args[0] { - continue - } - x := y_1 - if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { - continue - } - v.reset(OpAMD64ADDQmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + a := v_0 + if a.Op != OpAMD64ANDLconst { + break } - break + c := auxIntToInt32(a.AuxInt) + x := a.Args[0] + if !(a.Uses == 1) { + break + } + v.reset(OpAMD64TESTBconst) + v.AuxInt = int8ToAuxInt(int8(c)) + v.AddArg(x) + return true } - // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) - // result: (SUBQmodify [off] {sym} ptr x mem) + // match: (CMPBconst x [0]) + // result: (TESTB x x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64SUBQ { + if auxIntToInt8(v.AuxInt) != 0 { break } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + x := v_0 + v.reset(OpAMD64TESTB) + v.AddArg2(x, x) + return true + } + // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) + // cond: l.Uses == 1 && clobber(l) + // result: @l.Block (CMPBconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) + for { + c := auxIntToInt8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64MOVBload { break } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) mem := l.Args[1] - if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { + ptr := l.Args[0] + if !(l.Uses == 1 && clobber(l)) { break } - v.reset(OpAMD64SUBQmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) + v.copyOf(v0) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) - // result: (ANDQmodify [off] {sym} ptr x mem) + return false +} +func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) + // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { - off := auxIntToInt32(v.AuxInt) + valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ANDQ { + if v_0.Op != OpAMD64ADDQconst { break } - _ = y.Args[1] - y_0 := y.Args[0] - y_1 := y.Args[1] - for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { - l := y_0 - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { - continue - } - mem := l.Args[1] - if ptr != l.Args[0] { - continue - } - x := y_1 - if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { - continue - } - v.reset(OpAMD64ANDQmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2)) { + break } - break + v.reset(OpAMD64CMPBconstload) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(sym) + v.AddArg2(base, mem) + return true } - // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) - // result: (ORQmodify [off] {sym} ptr x mem) + // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) + // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64ORQ { + valoff1 := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - _ = y.Args[1] - y_0 := y.Args[0] - y_1 := y.Args[1] - for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { - l := y_0 - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { - continue - } - mem := l.Args[1] - if ptr != l.Args[0] { - continue - } - x := y_1 - if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { - continue - } - v.reset(OpAMD64ORQmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { + break } - break + v.reset(OpAMD64CMPBconstload) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) + return true } - // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) - // result: (XORQmodify [off] {sym} ptr x mem) + return false +} +func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (CMPBload [off1+off2] {sym} base val mem) for { - off := auxIntToInt32(v.AuxInt) + off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - y := v_1 - if y.Op != OpAMD64XORQ { + if v_0.Op != OpAMD64ADDQconst { break } - _ = y.Args[1] - y_0 := y.Args[0] - y_1 := y.Args[1] - for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { - l := y_0 - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { - continue - } - mem := l.Args[1] - if ptr != l.Args[0] { - continue - } - x := y_1 - if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { - continue - } - v.reset(OpAMD64XORQmodify) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break } - break + v.reset(OpAMD64CMPBload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) + return true } - // match: (MOVQstore {sym} [off] ptr x:(BTSQconst [c] l:(MOVQload {sym} [off] ptr mem)) mem) - // cond: x.Uses == 1 && l.Uses == 1 && clobber(x, l) - // result: (BTSQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - x := v_1 - if x.Op != OpAMD64BTSQconst { - break - } - c := auxIntToInt8(x.AuxInt) - l := x.Args[0] - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - mem := l.Args[1] - if ptr != l.Args[0] || mem != v_2 || !(x.Uses == 1 && l.Uses == 1 && clobber(x, l)) { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64BTSQconstmodify) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) + v.reset(OpAMD64CMPBload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (MOVQstore {sym} [off] ptr x:(BTRQconst [c] l:(MOVQload {sym} [off] ptr mem)) mem) - // cond: x.Uses == 1 && l.Uses == 1 && clobber(x, l) - // result: (BTRQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) + // result: (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - x := v_1 - if x.Op != OpAMD64BTRQconst { - break - } - c := auxIntToInt8(x.AuxInt) - l := x.Args[0] - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { - break - } - mem := l.Args[1] - if ptr != l.Args[0] || mem != v_2 || !(x.Uses == 1 && l.Uses == 1 && clobber(x, l)) { + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64BTRQconstmodify) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + c := auxIntToInt32(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64CMPBconstload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } - // match: (MOVQstore {sym} [off] ptr x:(BTCQconst [c] l:(MOVQload {sym} [off] ptr mem)) mem) - // cond: x.Uses == 1 && l.Uses == 1 && clobber(x, l) - // result: (BTCQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + return false +} +func rewriteValueAMD64_OpAMD64CMPL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CMPL x (MOVLconst [c])) + // result: (CMPLconst x [c]) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - x := v_1 - if x.Op != OpAMD64BTCQconst { - break - } - c := auxIntToInt8(x.AuxInt) - l := x.Args[0] - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - mem := l.Args[1] - if ptr != l.Args[0] || mem != v_2 || !(x.Uses == 1 && l.Uses == 1 && clobber(x, l)) { + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64CMPLconst) + v.AuxInt = int32ToAuxInt(c) + v.AddArg(x) + return true + } + // match: (CMPL (MOVLconst [c]) x) + // result: (InvertFlags (CMPLconst x [c])) + for { + if v_0.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64BTCQconstmodify) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) + c := auxIntToInt32(v_0.AuxInt) + x := v_1 + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(c) + v0.AddArg(x) + v.AddArg(v0) return true } - // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) - // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) - // result: (ADDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMPL x y) + // cond: canonLessThan(x,y) + // result: (InvertFlags (CMPL y x)) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - a := v_1 - if a.Op != OpAMD64ADDQconst { + x := v_0 + y := v_1 + if !(canonLessThan(x, y)) { break } - c := auxIntToInt32(a.AuxInt) - l := a.Args[0] - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) + return true + } + // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (CMPLload {sym} [off] ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { break } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) mem := l.Args[1] - ptr2 := l.Args[0] - if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64ADDQconstmodify) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.reset(OpAMD64CMPLload) + v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) - // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) - // result: (ANDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - a := v_1 - if a.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(a.AuxInt) - l := a.Args[0] - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVLload { break } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) mem := l.Args[1] - ptr2 := l.Args[0] - if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64ANDQconstmodify) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg3(ptr, x, mem) + v.AddArg(v0) return true } - // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) - // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) - // result: (ORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + return false +} +func rewriteValueAMD64_OpAMD64CMPLconst(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (CMPLconst (MOVLconst [x]) [y]) + // cond: x==y + // result: (FlagEQ) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - a := v_1 - if a.Op != OpAMD64ORQconst { - break - } - c := auxIntToInt32(a.AuxInt) - l := a.Args[0] - if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + y := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } - mem := l.Args[1] - ptr2 := l.Args[0] - if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + x := auxIntToInt32(v_0.AuxInt) + if !(x == y) { break } - v.reset(OpAMD64ORQconstmodify) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) + v.reset(OpAMD64FlagEQ) return true } - // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) - // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) - // result: (XORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + // match: (CMPLconst (MOVLconst [x]) [y]) + // cond: xuint32(y) + // result: (FlagLT_UGT) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVQf2i { + y := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } - val := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64MOVSDstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, val, mem) + x := auxIntToInt32(v_0.AuxInt) + if !(x < y && uint32(x) > uint32(y)) { + break + } + v.reset(OpAMD64FlagLT_UGT) return true } - // match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem) - // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 - // result: (MOVBEQstore [i] {s} p w mem) + // match: (CMPLconst (MOVLconst [x]) [y]) + // cond: x>y && uint32(x)= 3) { + x := auxIntToInt32(v_0.AuxInt) + if !(x > y && uint32(x) < uint32(y)) { break } - v.reset(OpAMD64MOVBEQstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) + v.reset(OpAMD64FlagGT_ULT) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) - // cond: ValAndOff(sc).canAdd32(off) - // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) + // match: (CMPLconst (MOVLconst [x]) [y]) + // cond: x>y && uint32(x)>uint32(y) + // result: (FlagGT_UGT) for { - sc := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + y := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } - off := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(ValAndOff(sc).canAdd32(off)) { + x := auxIntToInt32(v_0.AuxInt) + if !(x > y && uint32(x) > uint32(y)) { break } - v.reset(OpAMD64MOVQstoreconst) - v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(s) - v.AddArg2(ptr, mem) + v.reset(OpAMD64FlagGT_UGT) return true } - // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) - // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) - // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) + // match: (CMPLconst (SHRLconst _ [c]) [n]) + // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) + // result: (FlagLT_UGT) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64MOVQconst { break } - off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + x := auxIntToInt64(v_0.AuxInt) + if v_1.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64MOVSSstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(ptr, val, mem) + y := auxIntToInt64(v_1.AuxInt) + if !(x < y && uint64(x) > uint64(y)) { + break + } + v.reset(OpAMD64FlagLT_UGT) return true } - // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) + // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { + break + } + v.reset(OpAMD64FlagGT_ULT) return true } - // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) - // result: (MOVLstore [off] {sym} ptr val mem) + // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) + // cond: x>y && uint64(x)>uint64(y) + // result: (FlagGT_UGT) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLi2f { + if v_0.Op != OpAMD64MOVQconst { break } - val := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, val, mem) + x := auxIntToInt64(v_0.AuxInt) + if v_1.Op != OpAMD64MOVQconst { + break + } + y := auxIntToInt64(v_1.AuxInt) + if !(x > y && uint64(x) > uint64(y)) { + break + } + v.reset(OpAMD64FlagGT_UGT) return true } - // match: (MOVSSstore [off] {sym} ptr (MOVSSconst [f]) mem) - // cond: f == f - // result: (MOVLstore [off] {sym} ptr (MOVLconst [int32(math.Float32bits(f))]) mem) + // match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (CMPQload {sym} [off] ptr x mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVSSconst { + l := v_0 + if l.Op != OpAMD64MOVQload { break } - f := auxIntToFloat32(v_1.AuxInt) - mem := v_2 - if !(f == f) { + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64MOVLstore) + v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt32) - v0.AuxInt = int32ToAuxInt(int32(math.Float32bits(f))) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) + // match: (CMPQ x l:(MOVQload {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (InvertFlags (CMPQload {sym} [off] ptr x mem)) for { x := v_0 - if x.Op != OpAMD64MOVWload { + l := v_1 + if l.Op != OpAMD64MOVQload { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { break } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) - v.copyOf(v0) + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) + v0.AddArg3(ptr, x, mem) + v.AddArg(v0) return true } - // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) + return false +} +func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (CMPQconst (MOVQconst [x]) [y]) + // cond: x==int64(y) + // result: (FlagEQ) for { - x := v_0 - if x.Op != OpAMD64MOVLload { + y := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { + x := auxIntToInt64(v_0.AuxInt) + if !(x == int64(y)) { break } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) + v.reset(OpAMD64FlagEQ) return true } - // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) + // match: (CMPQconst (MOVQconst [x]) [y]) + // cond: xuint64(int64(y)) + // result: (FlagLT_UGT) for { - if v_0.Op != OpAMD64ANDLconst { + y := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { break } - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(c&0x8000 == 0) { + x := auxIntToInt64(v_0.AuxInt) + if !(x < int64(y) && uint64(x) > uint64(int64(y))) { break } - v.reset(OpAMD64ANDLconst) - v.AuxInt = int32ToAuxInt(c & 0x7fff) - v.AddArg(x) + v.reset(OpAMD64FlagLT_UGT) return true } - // match: (MOVWQSX (MOVWQSX x)) - // result: (MOVWQSX x) + // match: (CMPQconst (MOVQconst [x]) [y]) + // cond: x>int64(y) && uint64(x) int64(y) && uint64(x) < uint64(int64(y))) { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVBQSX) - v.AddArg(x) + v.reset(OpAMD64FlagGT_ULT) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) - // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) - // result: (MOVWQSX x) + // match: (CMPQconst (MOVQconst [x]) [y]) + // cond: x>int64(y) && uint64(x)>uint64(int64(y)) + // result: (FlagGT_UGT) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVWstore { + y := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - x := v_1.Args[1] - ptr2 := v_1.Args[0] - if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + x := auxIntToInt64(v_0.AuxInt) + if !(x > int64(y) && uint64(x) > uint64(int64(y))) { break } - v.reset(OpAMD64MOVWQSX) - v.AddArg(x) + v.reset(OpAMD64FlagGT_UGT) return true } - // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) + // match: (CMPQconst (MOVBQZX _) [c]) + // cond: 0xFF < c + // result: (FlagLT_ULT) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { - break - } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } - v.reset(OpAMD64MOVWQSXload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) + v.reset(OpAMD64FlagLT_ULT) return true } - // match: (MOVWQSXload [off] {sym} (SB) _) - // cond: symIsRO(sym) - // result: (MOVQconst [int64(int16(read16(sym, int64(off), config.ctxt.Arch.ByteOrder)))]) + // match: (CMPQconst (MOVWQZX _) [c]) + // cond: 0xFFFF < c + // result: (FlagLT_ULT) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpSB || !(symIsRO(sym)) { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(int16(read16(sym, int64(off), config.ctxt.Arch.ByteOrder)))) + v.reset(OpAMD64FlagLT_ULT) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVWload [off] {sym} ptr mem) + // match: (CMPQconst (SHRQconst _ [c]) [n]) + // cond: 0 <= n && 0 < c && c <= 64 && (1< [off] {sym} ptr mem) + // match: (CMPQconst (ANDQconst _ [m]) [n]) + // cond: 0 <= m && m < n + // result: (FlagLT_ULT) for { - x := v_0 - if x.Op != OpAMD64MOVLload { + n := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64ANDQconst { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { + m := auxIntToInt32(v_0.AuxInt) + if !(0 <= m && m < n) { break } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) + v.reset(OpAMD64FlagLT_ULT) return true } - // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) - // cond: x.Uses == 1 && clobber(x) - // result: @x.Block (MOVWload [off] {sym} ptr mem) + // match: (CMPQconst (ANDLconst _ [m]) [n]) + // cond: 0 <= m && m < n + // result: (FlagLT_ULT) for { - x := v_0 - if x.Op != OpAMD64MOVQload { + n := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64ANDLconst { break } - off := auxIntToInt32(x.AuxInt) - sym := auxToSym(x.Aux) - mem := x.Args[1] - ptr := x.Args[0] - if !(x.Uses == 1 && clobber(x)) { + m := auxIntToInt32(v_0.AuxInt) + if !(0 <= m && m < n) { break } - b = x.Block - v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) + v.reset(OpAMD64FlagLT_ULT) return true } - // match: (MOVWQZX (ANDLconst [c] x)) - // result: (ANDLconst [c & 0xffff] x) + // match: (CMPQconst a:(ANDQ x y) [0]) + // cond: a.Uses == 1 + // result: (TESTQ x y) for { - if v_0.Op != OpAMD64ANDLconst { + if auxIntToInt32(v.AuxInt) != 0 { break } - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ANDLconst) - v.AuxInt = int32ToAuxInt(c & 0xffff) - v.AddArg(x) + a := v_0 + if a.Op != OpAMD64ANDQ { + break + } + y := a.Args[1] + x := a.Args[0] + if !(a.Uses == 1) { + break + } + v.reset(OpAMD64TESTQ) + v.AddArg2(x, y) return true } - // match: (MOVWQZX (MOVWQZX x)) - // result: (MOVWQZX x) + // match: (CMPQconst a:(ANDQconst [c] x) [0]) + // cond: a.Uses == 1 + // result: (TESTQconst [c] x) for { - if v_0.Op != OpAMD64MOVWQZX { + if auxIntToInt32(v.AuxInt) != 0 { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVWQZX) + a := v_0 + if a.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(a.AuxInt) + x := a.Args[0] + if !(a.Uses == 1) { + break + } + v.reset(OpAMD64TESTQconst) + v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } - // match: (MOVWQZX (MOVBQZX x)) - // result: (MOVBQZX x) + // match: (CMPQconst x [0]) + // result: (TESTQ x x) for { - if v_0.Op != OpAMD64MOVBQZX { + if auxIntToInt32(v.AuxInt) != 0 { break } - x := v_0.Args[0] - v.reset(OpAMD64MOVBQZX) - v.AddArg(x) + x := v_0 + v.reset(OpAMD64TESTQ) + v.AddArg2(x, x) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) - // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) - // result: (MOVWQZX x) + // match: (CMPQconst l:(MOVQload {sym} [off] ptr mem) [c]) + // cond: l.Uses == 1 && clobber(l) + // result: @l.Block (CMPQconstload {sym} [makeValAndOff(c,off)] ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVWstore { + c := auxIntToInt32(v.AuxInt) + l := v_0 + if l.Op != OpAMD64MOVQload { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - x := v_1.Args[1] - ptr2 := v_1.Args[0] - if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(l.Uses == 1 && clobber(l)) { break } - v.reset(OpAMD64MOVWQZX) - v.AddArg(x) + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) + v.copyOf(v0) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(c, off)) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVWload [off1+off2] {sym} ptr mem) + return false +} +func rewriteValueAMD64_OpAMD64CMPQconstload(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMPQconstload [valoff1] {sym} (ADDQconst [off2] base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) + // result: (CMPQconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { - off1 := auxIntToInt32(v.AuxInt) + valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] + base := v_0.Args[0] mem := v_1 - if !(is32Bit(int64(off1) + int64(off2))) { + if !(ValAndOff(valoff1).canAdd32(off2)) { break } - v.reset(OpAMD64MOVWload) - v.AuxInt = int32ToAuxInt(off1 + off2) + v.reset(OpAMD64CMPQconstload) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) + v.AddArg2(base, mem) return true } - // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) + // match: (CMPQconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) + // result: (CMPQconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { - off1 := auxIntToInt32(v.AuxInt) + valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break @@ -13355,71 +22984,24 @@ func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64MOVWload) - v.AuxInt = int32ToAuxInt(off1 + off2) + v.reset(OpAMD64CMPQconstload) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } - // match: (MOVWload [off] {sym} (SB) _) - // cond: symIsRO(sym) - // result: (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpSB || !(symIsRO(sym)) { - break - } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) - return true - } return false } -func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMPQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) - // result: (MOVWstore [off] {sym} ptr x mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVWQSX { - break - } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) - // result: (MOVWstore [off] {sym} ptr x mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVWQZX { - break - } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // match: (CMPQload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MOVWstore [off1+off2] {sym} ptr val mem) + // result: (CMPQload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -13427,55 +23009,21 @@ func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { break } off2 := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] + base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64MOVWstore) + v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v.AddArg3(ptr, val, mem) - return true - } - // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) - // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true - } - // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) - // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) + v.AddArg3(base, val, mem) return true } - // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // match: (CMPQload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // result: (CMPQload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13490,421 +23038,532 @@ func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64MOVWstore) + v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } - // match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) - // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 - // result: (MOVBEWstore [i] {s} p w mem) + // match: (CMPQload {sym} [off] ptr (MOVQconst [c]) mem) + // cond: validVal(c) + // result: (CMPQconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - x := v_1 - if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - w := x.Args[0] + c := auxIntToInt64(v_1.AuxInt) mem := v_2 - if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { + if !(validVal(c)) { break } - v.reset(OpAMD64MOVBEWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) + v.reset(OpAMD64CMPQconstload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } return false } -func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMPW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) - // cond: ValAndOff(sc).canAdd32(off) - // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) + b := v.Block + // match: (CMPW x (MOVLconst [c])) + // result: (CMPWconst x [int16(c)]) for { - sc := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { - break - } - off := auxIntToInt32(v_0.AuxInt) - ptr := v_0.Args[0] - mem := v_1 - if !(ValAndOff(sc).canAdd32(off)) { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(s) - v.AddArg2(ptr, mem) + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64CMPWconst) + v.AuxInt = int16ToAuxInt(int16(c)) + v.AddArg(x) return true } - // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) - // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) - // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) + // match: (CMPW (MOVLconst [c]) x) + // result: (InvertFlags (CMPWconst x [int16(c)])) for { - sc := auxIntToValAndOff(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { - break - } - off := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - ptr := v_0.Args[0] - mem := v_1 - if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { + if v_0.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(ptr, mem) + c := auxIntToInt32(v_0.AuxInt) + x := v_1 + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v0.AuxInt = int16ToAuxInt(int16(c)) + v0.AddArg(x) + v.AddArg(v0) return true } - return false -} -func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (MULL x (MOVLconst [c])) - // result: (MULLconst [c] x) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - continue - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64MULLconst) - v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64MULLconst(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (MULLconst [c] (MULLconst [d] x)) - // result: (MULLconst [c * d] x) + // match: (CMPW x y) + // cond: canonLessThan(x,y) + // result: (InvertFlags (CMPW y x)) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MULLconst { + x := v_0 + y := v_1 + if !(canonLessThan(x, y)) { break } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64MULLconst) - v.AuxInt = int32ToAuxInt(c * d) - v.AddArg(x) + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) return true } - // match: (MULLconst [ 0] _) - // result: (MOVLconst [0]) + // match: (CMPW l:(MOVWload {sym} [off] ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (CMPWload {sym} [off] ptr x mem) for { - if auxIntToInt32(v.AuxInt) != 0 { + l := v_0 + if l.Op != OpAMD64MOVWload { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64CMPWload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (MULLconst [ 1] x) - // result: x + // match: (CMPW x l:(MOVWload {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (InvertFlags (CMPWload {sym} [off] ptr x mem)) for { - if auxIntToInt32(v.AuxInt) != 1 { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVWload { break } - x := v_0 - v.copyOf(x) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(l.Pos, OpAMD64CMPWload, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg3(ptr, x, mem) + v.AddArg(v0) return true } - // match: (MULLconst [c] x) - // cond: v.Type.Size() <= 4 && canMulStrengthReduce32(config, c) - // result: {mulStrengthReduce32(v, x, c)} + return false +} +func rewriteValueAMD64_OpAMD64CMPWconst(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (CMPWconst (MOVLconst [x]) [y]) + // cond: int16(x)==y + // result: (FlagEQ) for { - c := auxIntToInt32(v.AuxInt) - x := v_0 - if !(v.Type.Size() <= 4 && canMulStrengthReduce32(config, c)) { + y := auxIntToInt16(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } - v.copyOf(mulStrengthReduce32(v, x, c)) + x := auxIntToInt32(v_0.AuxInt) + if !(int16(x) == y) { + break + } + v.reset(OpAMD64FlagEQ) return true } - // match: (MULLconst [c] (MOVLconst [d])) - // result: (MOVLconst [c*d]) + // match: (CMPWconst (MOVLconst [x]) [y]) + // cond: int16(x)uint16(y) + // result: (FlagLT_UGT) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - continue - } - c := auxIntToInt64(v_1.AuxInt) - if !(is32Bit(c)) { - continue - } - v.reset(OpAMD64MULQconst) - v.AuxInt = int32ToAuxInt(int32(c)) - v.AddArg(x) - return true + y := auxIntToInt16(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { + break } - break + x := auxIntToInt32(v_0.AuxInt) + if !(int16(x) < y && uint16(x) > uint16(y)) { + break + } + v.reset(OpAMD64FlagLT_UGT) + return true } - return false -} -func rewriteValueAMD64_OpAMD64MULQconst(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (MULQconst [c] (MULQconst [d] x)) - // cond: is32Bit(int64(c)*int64(d)) - // result: (MULQconst [c * d] x) + // match: (CMPWconst (MOVLconst [x]) [y]) + // cond: int16(x)>y && uint16(x) y && uint16(x) < uint16(y)) { break } - v.reset(OpAMD64MULQconst) - v.AuxInt = int32ToAuxInt(c * d) - v.AddArg(x) + v.reset(OpAMD64FlagGT_ULT) return true } - // match: (MULQconst [ 0] _) - // result: (MOVQconst [0]) + // match: (CMPWconst (MOVLconst [x]) [y]) + // cond: int16(x)>y && uint16(x)>uint16(y) + // result: (FlagGT_UGT) for { - if auxIntToInt32(v.AuxInt) != 0 { + y := auxIntToInt16(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(0) + x := auxIntToInt32(v_0.AuxInt) + if !(int16(x) > y && uint16(x) > uint16(y)) { + break + } + v.reset(OpAMD64FlagGT_UGT) return true } - // match: (MULQconst [ 1] x) - // result: x + // match: (CMPWconst (ANDLconst _ [m]) [n]) + // cond: 0 <= int16(m) && int16(m) < n + // result: (FlagLT_ULT) for { - if auxIntToInt32(v.AuxInt) != 1 { + n := auxIntToInt16(v.AuxInt) + if v_0.Op != OpAMD64ANDLconst { break } - x := v_0 - v.copyOf(x) + m := auxIntToInt32(v_0.AuxInt) + if !(0 <= int16(m) && int16(m) < n) { + break + } + v.reset(OpAMD64FlagLT_ULT) return true } - // match: (MULQconst [c] x) - // cond: canMulStrengthReduce(config, int64(c)) - // result: {mulStrengthReduce(v, x, int64(c))} + // match: (CMPWconst a:(ANDL x y) [0]) + // cond: a.Uses == 1 + // result: (TESTW x y) for { - c := auxIntToInt32(v.AuxInt) - x := v_0 - if !(canMulStrengthReduce(config, int64(c))) { + if auxIntToInt16(v.AuxInt) != 0 { break } - v.copyOf(mulStrengthReduce(v, x, int64(c))) + a := v_0 + if a.Op != OpAMD64ANDL { + break + } + y := a.Args[1] + x := a.Args[0] + if !(a.Uses == 1) { + break + } + v.reset(OpAMD64TESTW) + v.AddArg2(x, y) return true } - // match: (MULQconst [c] (MOVQconst [d])) - // result: (MOVQconst [int64(c)*d]) + // match: (CMPWconst a:(ANDLconst [c] x) [0]) + // cond: a.Uses == 1 + // result: (TESTWconst [int16(c)] x) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + if auxIntToInt16(v.AuxInt) != 0 { break } - d := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(c) * d) + a := v_0 + if a.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(a.AuxInt) + x := a.Args[0] + if !(a.Uses == 1) { + break + } + v.reset(OpAMD64TESTWconst) + v.AuxInt = int16ToAuxInt(int16(c)) + v.AddArg(x) return true } - // match: (MULQconst [c] (NEGQ x)) - // cond: c != -(1<<31) - // result: (MULQconst [-c] x) + // match: (CMPWconst x [0]) + // result: (TESTW x x) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64NEGQ { + if auxIntToInt16(v.AuxInt) != 0 { break } - x := v_0.Args[0] - if !(c != -(1 << 31)) { + x := v_0 + v.reset(OpAMD64TESTW) + v.AddArg2(x, x) + return true + } + // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) + // cond: l.Uses == 1 && clobber(l) + // result: @l.Block (CMPWconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) + for { + c := auxIntToInt16(v.AuxInt) + l := v_0 + if l.Op != OpAMD64MOVWload { break } - v.reset(OpAMD64MULQconst) - v.AuxInt = int32ToAuxInt(-c) - v.AddArg(x) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(l.Uses == 1 && clobber(l)) { + break + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) + v.copyOf(v0) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } return false } -func rewriteValueAMD64_OpAMD64MULSD(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (MULSDload x [off] {sym} ptr mem) + // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) + // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVSDload { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - continue - } - v.reset(OpAMD64MULSDload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true + valoff1 := auxIntToValAndOff(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break } - break + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2)) { + break + } + v.reset(OpAMD64CMPWconstload) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(sym) + v.AddArg2(base, mem) + return true + } + // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) + // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) + for { + valoff1 := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64CMPWconstload) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) + return true } return false } -func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) + // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MULSDload [off1+off2] {sym} val base mem) + // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64ADDQconst { break } - off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64MULSDload) + v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) + v.AddArg3(base, val, mem) return true } - // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64LEAQ { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64MULSDload) + v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) + v.AddArg3(base, val, mem) return true } - // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) - // result: (MULSD x (MOVQi2f y)) + // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) + // result: (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - x := v_0 - ptr := v_1 - if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { + ptr := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - y := v_2.Args[1] - if ptr != v_2.Args[0] { + c := auxIntToInt32(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64CMPWconstload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64CMPXCHGLlock(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - v.reset(OpAMD64MULSD) - v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) - v0.AddArg(y) - v.AddArg2(x, v0) + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + old := v_1 + new_ := v_2 + mem := v_3 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64CMPXCHGLlock) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg4(ptr, old, new_, mem) return true } return false } -func rewriteValueAMD64_OpAMD64MULSS(v *Value) bool { +func rewriteValueAMD64_OpAMD64CMPXCHGQlock(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) + // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + old := v_1 + new_ := v_2 + mem := v_3 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64CMPXCHGQlock) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg4(ptr, old, new_, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64CVTSD2SS(v *Value) bool { + v_0 := v.Args[0] + // match: (CVTSD2SS (ROUNDSD [c] (CVTSS2SD x))) + // result: (ROUNDSS [c] x) + for { + if v_0.Op != OpAMD64ROUNDSD { + break + } + c := auxIntToInt8(v_0.AuxInt) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64CVTSS2SD { + break + } + x := v_0_0.Args[0] + v.reset(OpAMD64ROUNDSS) + v.AuxInt = int8ToAuxInt(c) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64DIVSD(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (MULSSload x [off] {sym} ptr mem) + // result: (DIVSDload x [off] {sym} ptr mem) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVSSload { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - continue - } - v.reset(OpAMD64MULSSload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVSDload { + break } - break + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + break + } + v.reset(OpAMD64DIVSDload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true } return false } -func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { +func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) + // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (MULSSload [off1+off2] {sym} val base mem) + // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -13918,15 +23577,15 @@ func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64MULSSload) + v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } - // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -13941,899 +23600,1278 @@ func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64MULSSload) + v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } - // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) - // result: (MULSS x (MOVLi2f y)) + return false +} +func rewriteValueAMD64_OpAMD64DIVSS(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (DIVSSload x [off] {sym} ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) x := v_0 - ptr := v_1 - if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { + l := v_1 + if l.Op != OpAMD64MOVSSload { break } - y := v_2.Args[1] - if ptr != v_2.Args[0] { + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } - v.reset(OpAMD64MULSS) - v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) - v0.AddArg(y) - v.AddArg2(x, v0) + v.reset(OpAMD64DIVSSload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) return true } return false } -func rewriteValueAMD64_OpAMD64NEGL(v *Value) bool { +func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (NEGL (NEGL x)) - // result: x + // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (DIVSSload [off1+off2] {sym} val base mem) for { - if v_0.Op != OpAMD64NEGL { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { break } - x := v_0.Args[0] - v.copyOf(x) + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64DIVSSload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, base, mem) return true } - // match: (NEGL s:(SUBL x y)) - // cond: s.Uses == 1 - // result: (SUBL y x) + // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { - s := v_0 - if s.Op != OpAMD64SUBL { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { break } - y := s.Args[1] - x := s.Args[0] - if !(s.Uses == 1) { + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SUBL) - v.AddArg2(y, x) + v.reset(OpAMD64DIVSSload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, base, mem) return true } - // match: (NEGL (MOVLconst [c])) - // result: (MOVLconst [-c]) + return false +} +func rewriteValueAMD64_OpAMD64HMULL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (HMULL x y) + // cond: !x.rematerializeable() && y.rematerializeable() + // result: (HMULL y x) for { - if v_0.Op != OpAMD64MOVLconst { + x := v_0 + y := v_1 + if !(!x.rematerializeable() && y.rematerializeable()) { break } - c := auxIntToInt32(v_0.AuxInt) - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(-c) + v.reset(OpAMD64HMULL) + v.AddArg2(y, x) return true } return false } -func rewriteValueAMD64_OpAMD64NEGQ(v *Value) bool { +func rewriteValueAMD64_OpAMD64HMULLU(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (NEGQ (NEGQ x)) - // result: x + // match: (HMULLU x y) + // cond: !x.rematerializeable() && y.rematerializeable() + // result: (HMULLU y x) for { - if v_0.Op != OpAMD64NEGQ { + x := v_0 + y := v_1 + if !(!x.rematerializeable() && y.rematerializeable()) { break } - x := v_0.Args[0] - v.copyOf(x) + v.reset(OpAMD64HMULLU) + v.AddArg2(y, x) return true } - // match: (NEGQ s:(SUBQ x y)) - // cond: s.Uses == 1 - // result: (SUBQ y x) + return false +} +func rewriteValueAMD64_OpAMD64HMULQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (HMULQ x y) + // cond: !x.rematerializeable() && y.rematerializeable() + // result: (HMULQ y x) for { - s := v_0 - if s.Op != OpAMD64SUBQ { + x := v_0 + y := v_1 + if !(!x.rematerializeable() && y.rematerializeable()) { break } - y := s.Args[1] - x := s.Args[0] - if !(s.Uses == 1) { + v.reset(OpAMD64HMULQ) + v.AddArg2(y, x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64HMULQU(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (HMULQU x y) + // cond: !x.rematerializeable() && y.rematerializeable() + // result: (HMULQU y x) + for { + x := v_0 + y := v_1 + if !(!x.rematerializeable() && y.rematerializeable()) { break } - v.reset(OpAMD64SUBQ) + v.reset(OpAMD64HMULQU) v.AddArg2(y, x) return true } - // match: (NEGQ (MOVQconst [c])) - // result: (MOVQconst [-c]) + return false +} +func rewriteValueAMD64_OpAMD64KANDB(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (KANDB (VCMPPD512 [3] x x) (VCMPPD512 [3] y y)) + // result: (VCMPPD512 [3] x x) for { - if v_0.Op != OpAMD64MOVQconst { + if v_0.Op != OpAMD64VCMPPD512 || auxIntToUint8(v_0.AuxInt) != 3 { break } - c := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(-c) + x := v_0.Args[1] + if x != v_0.Args[0] || v_1.Op != OpAMD64VCMPPD512 || auxIntToUint8(v_1.AuxInt) != 3 { + break + } + y := v_1.Args[1] + if y != v_1.Args[0] { + break + } + v.reset(OpAMD64VCMPPD512) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg2(x, x) return true } - // match: (NEGQ (ADDQconst [c] (NEGQ x))) - // cond: c != -(1<<31) - // result: (ADDQconst [-c] x) + return false +} +func rewriteValueAMD64_OpAMD64KANDW(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (KANDW (VCMPPS512 [3] x x) (VCMPPS512 [3] y y)) + // result: (VCMPPS512 [3] x y) for { - if v_0.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64VCMPPS512 || auxIntToUint8(v_0.AuxInt) != 3 { break } - c := auxIntToInt32(v_0.AuxInt) - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64NEGQ { + x := v_0.Args[1] + if x != v_0.Args[0] || v_1.Op != OpAMD64VCMPPS512 || auxIntToUint8(v_1.AuxInt) != 3 { break } - x := v_0_0.Args[0] - if !(c != -(1 << 31)) { + y := v_1.Args[1] + if y != v_1.Args[0] { break } - v.reset(OpAMD64ADDQconst) - v.AuxInt = int32ToAuxInt(-c) - v.AddArg(x) + v.reset(OpAMD64VCMPPS512) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg2(x, y) return true } return false } -func rewriteValueAMD64_OpAMD64NOTL(v *Value) bool { +func rewriteValueAMD64_OpAMD64KMOVBk(v *Value) bool { v_0 := v.Args[0] - // match: (NOTL (MOVLconst [c])) - // result: (MOVLconst [^c]) + // match: (KMOVBk l:(MOVBload [off] {sym} ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (KMOVBload [off] {sym} ptr mem) for { - if v_0.Op != OpAMD64MOVLconst { + l := v_0 + if l.Op != OpAMD64MOVBload { break } - c := auxIntToInt32(v_0.AuxInt) - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(^c) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64KMOVBload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } return false } -func rewriteValueAMD64_OpAMD64NOTQ(v *Value) bool { +func rewriteValueAMD64_OpAMD64KMOVDk(v *Value) bool { v_0 := v.Args[0] - // match: (NOTQ (MOVQconst [c])) - // result: (MOVQconst [^c]) + // match: (KMOVDk l:(MOVLload [off] {sym} ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (KMOVDload [off] {sym} ptr mem) for { - if v_0.Op != OpAMD64MOVQconst { + l := v_0 + if l.Op != OpAMD64MOVLload { break } - c := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(^c) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64KMOVDload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } return false } -func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { +func rewriteValueAMD64_OpAMD64KMOVQk(v *Value) bool { + v_0 := v.Args[0] + // match: (KMOVQk l:(MOVQload [off] {sym} ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (KMOVQload [off] {sym} ptr mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64KMOVQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64KMOVWk(v *Value) bool { + v_0 := v.Args[0] + // match: (KMOVWk l:(MOVWload [off] {sym} ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (KMOVWload [off] {sym} ptr mem) + for { + l := v_0 + if l.Op != OpAMD64MOVWload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64KMOVWload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64LEAL(v *Value) bool { + v_0 := v.Args[0] + // match: (LEAL [c] {s} (ADDLconst [d] x)) + // cond: is32Bit(int64(c)+int64(d)) + // result: (LEAL [c+d] {s} x) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDLconst { + break + } + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(is32Bit(int64(c) + int64(d))) { + break + } + v.reset(OpAMD64LEAL) + v.AuxInt = int32ToAuxInt(c + d) + v.Aux = symToAux(s) + v.AddArg(x) + return true + } + // match: (LEAL [c] {s} (ADDL x y)) + // cond: x.Op != OpSB && y.Op != OpSB + // result: (LEAL1 [c] {s} x y) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if !(x.Op != OpSB && y.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAL1) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64LEAL1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ORL (SHLL (MOVLconst [1]) y) x) - // result: (BTSL x y) + // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) + // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB + // result: (LEAL1 [c+d] {s} x y) for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { + if v_0.Op != OpAMD64ADDLconst { continue } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + y := v_1 + if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } - x := v_1 - v.reset(OpAMD64BTSL) + v.reset(OpAMD64LEAL1) + v.AuxInt = int32ToAuxInt(c + d) + v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } - // match: (ORL x (MOVLconst [c])) - // result: (ORLconst [c] x) + // match: (LEAL1 [c] {s} x z:(ADDL y y)) + // cond: x != z + // result: (LEAL2 [c] {s} x y) for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 - if v_1.Op != OpAMD64MOVLconst { + z := v_1 + if z.Op != OpAMD64ADDL { continue } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64ORLconst) + y := z.Args[1] + if y != z.Args[0] || !(x != z) { + continue + } + v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } break } - // match: (ORL x x) - // result: x + // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) + // result: (LEAL4 [c] {s} x y) for { - x := v_0 - if x != v_1 { - break + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL4) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) + return true } - v.copyOf(x) - return true + break } - // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ORLload x [off] {sym} ptr mem) + // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) + // result: (LEAL8 [c] {s} x y) for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 - l := v_1 - if l.Op != OpAMD64MOVLload { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } - v.reset(OpAMD64ORLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) + y := v_1.Args[0] + v.reset(OpAMD64LEAL8) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } break } return false } -func rewriteValueAMD64_OpAMD64ORLconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64LEAL2(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ORLconst [c] (ORLconst [d] x)) - // result: (ORLconst [c | d] x) + // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) + // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB + // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64ORLconst { + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] - v.reset(OpAMD64ORLconst) - v.AuxInt = int32ToAuxInt(c | d) - v.AddArg(x) + y := v_1 + if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAL2) + v.AuxInt = int32ToAuxInt(c + d) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } - // match: (ORLconst [c] x) - // cond: c==0 - // result: x + // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) + // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB + // result: (LEAL2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) x := v_0 - if !(c == 0) { + if v_1.Op != OpAMD64ADDLconst { break } - v.copyOf(x) + d := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAL2) + v.AuxInt = int32ToAuxInt(c + 2*d) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } - // match: (ORLconst [c] _) - // cond: c==-1 - // result: (MOVLconst [-1]) + // match: (LEAL2 [c] {s} x z:(ADDL y y)) + // cond: x != z + // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) - if !(c == -1) { + s := auxToSym(v.Aux) + x := v_0 + z := v_1 + if z.Op != OpAMD64ADDL { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(-1) + y := z.Args[1] + if y != z.Args[0] || !(x != z) { + break + } + v.reset(OpAMD64LEAL4) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } - // match: (ORLconst [c] (MOVLconst [d])) - // result: (MOVLconst [c|d]) + // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) + // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + s := auxToSym(v.Aux) + x := v_0 + if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { break } - d := auxIntToInt32(v_0.AuxInt) - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(c | d) + y := v_1.Args[0] + v.reset(OpAMD64LEAL8) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpAMD64ORLconstmodify(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (ORLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) - // result: (ORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) + // match: (LEAL2 [0] {s} (ADDL x x) x) + // cond: s == nil + // result: (SHLLconst [2] x) for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + if auxIntToInt32(v.AuxInt) != 0 { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2)) { + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDL { break } - v.reset(OpAMD64ORLconstmodify) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(sym) - v.AddArg2(base, mem) - return true - } - // match: (ORLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (ORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) - for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + x := v_0.Args[1] + if x != v_0.Args[0] || x != v_1 || !(s == nil) { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { + v.reset(OpAMD64SHLLconst) + v.AuxInt = int8ToAuxInt(2) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64LEAL4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) + // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB + // result: (LEAL4 [c+d] {s} x y) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDLconst { break } - v.reset(OpAMD64ORLconstmodify) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + y := v_1 + if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAL4) + v.AuxInt = int32ToAuxInt(c + d) + v.Aux = symToAux(s) + v.AddArg2(x, y) + return true + } + // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) + // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB + // result: (LEAL4 [c+4*d] {s} x y) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + x := v_0 + if v_1.Op != OpAMD64ADDLconst { + break + } + d := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAL4) + v.AuxInt = int32ToAuxInt(c + 4*d) + v.Aux = symToAux(s) + v.AddArg2(x, y) + return true + } + // match: (LEAL4 [c] {s} x z:(ADDL y y)) + // cond: x != z + // result: (LEAL8 [c] {s} x y) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + x := v_0 + z := v_1 + if z.Op != OpAMD64ADDL { + break + } + y := z.Args[1] + if y != z.Args[0] || !(x != z) { + break + } + v.reset(OpAMD64LEAL8) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } return false } -func rewriteValueAMD64_OpAMD64ORLload(v *Value) bool { - v_2 := v.Args[2] +func rewriteValueAMD64_OpAMD64LEAL8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (ORLload [off1] {sym} val (ADDQconst [off2] base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (ORLload [off1+off2] {sym} val base mem) + // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) + // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB + // result: (LEAL8 [c+d] {s} x y) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDLconst { + break + } + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + y := v_1 + if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAL8) + v.AuxInt = int32ToAuxInt(c + d) + v.Aux = symToAux(s) + v.AddArg2(x, y) + return true + } + // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) + // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB + // result: (LEAL8 [c+8*d] {s} x y) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + x := v_0 + if v_1.Op != OpAMD64ADDLconst { + break + } + d := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAL8) + v.AuxInt = int32ToAuxInt(c + 8*d) + v.Aux = symToAux(s) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { + v_0 := v.Args[0] + // match: (LEAQ [c] {s} (ADDQconst [d] x)) + // cond: is32Bit(int64(c)+int64(d)) + // result: (LEAQ [c+d] {s} x) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break + } + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(is32Bit(int64(c) + int64(d))) { + break + } + v.reset(OpAMD64LEAQ) + v.AuxInt = int32ToAuxInt(c + d) + v.Aux = symToAux(s) + v.AddArg(x) + return true + } + // match: (LEAQ [c] {s} (ADDQ x y)) + // cond: x.Op != OpSB && y.Op != OpSB + // result: (LEAQ1 [c] {s} x y) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if !(x.Op != OpSB && y.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) + return true + } + break + } + // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + x := v_0.Args[0] + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64ORLload) + v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg(x) return true } - // match: (ORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64LEAQ1 { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] - mem := v_2 + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + y := v_0.Args[1] + x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64ORLload) + v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) + v.AddArg2(x, y) return true } - // match: ( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) - // result: ( ORL x (MOVLf2i y)) + // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - x := v_0 - ptr := v_1 - if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ2 { break } - y := v_2.Args[1] - if ptr != v_2.Args[0] { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + y := v_0.Args[1] + x := v_0.Args[0] + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64ORL) - v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) - v0.AddArg(y) - v.AddArg2(x, v0) + v.reset(OpAMD64LEAQ2) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpAMD64ORLmodify(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (ORLmodify [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (ORLmodify [off1+off2] {sym} base val mem) + // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ4 { break } off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + sym2 := auxToSym(v_0.Aux) + y := v_0.Args[1] + x := v_0.Args[0] + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64ORLmodify) + v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(x, y) return true } - // match: (ORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64LEAQ8 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 + y := v_0.Args[1] + x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64ORLmodify) + v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + v.AddArg2(x, y) return true } return false } -func rewriteValueAMD64_OpAMD64ORQ(v *Value) bool { +func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ORQ (SHLQ (MOVQconst [1]) y) x) - // result: (BTSQ x y) + // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) + // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB + // result: (LEAQ1 [c+d] {s} x y) for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQ { + if v_0.Op != OpAMD64ADDQconst { continue } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + y := v_1 + if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } - x := v_1 - v.reset(OpAMD64BTSQ) + v.reset(OpAMD64LEAQ1) + v.AuxInt = int32ToAuxInt(c + d) + v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } - // match: (ORQ (MOVQconst [c]) x) - // cond: isUnsignedPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31 - // result: (BTSQconst [int8(log64u(uint64(c)))] x) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64MOVQconst { - continue - } - c := auxIntToInt64(v_0.AuxInt) - x := v_1 - if !(isUnsignedPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31) { - continue - } - v.reset(OpAMD64BTSQconst) - v.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) - v.AddArg(x) - return true - } - break - } - // match: (ORQ x (MOVQconst [c])) - // cond: is32Bit(c) - // result: (ORQconst [int32(c)] x) + // match: (LEAQ1 [c] {s} x z:(ADDQ y y)) + // cond: x != z + // result: (LEAQ2 [c] {s} x y) for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 - if v_1.Op != OpAMD64MOVQconst { + z := v_1 + if z.Op != OpAMD64ADDQ { continue } - c := auxIntToInt64(v_1.AuxInt) - if !(is32Bit(c)) { + y := z.Args[1] + if y != z.Args[0] || !(x != z) { continue } - v.reset(OpAMD64ORQconst) - v.AuxInt = int32ToAuxInt(int32(c)) - v.AddArg(x) + v.reset(OpAMD64LEAQ2) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } break } - // match: (ORQ x (MOVLconst [c])) - // result: (ORQconst [c] x) + // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) + // result: (LEAQ4 [c] {s} x y) for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 - if v_1.Op != OpAMD64MOVLconst { + if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64ORQconst) + y := v_1.Args[0] + v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } break } - // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) - // result: (SHRDQ lo hi bits) + // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) + // result: (LEAQ8 [c] {s} x y) for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRQ { - continue - } - bits := v_0.Args[1] - lo := v_0.Args[0] - if v_1.Op != OpAMD64SHLQ { - continue - } - _ = v_1.Args[1] - hi := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { + x := v_0 + if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } - v.reset(OpAMD64SHRDQ) - v.AddArg3(lo, hi, bits) + y := v_1.Args[0] + v.reset(OpAMD64LEAQ8) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } break } - // match: (ORQ (SHLQ lo bits) (SHRQ hi (NEGQ bits))) - // result: (SHLDQ lo hi bits) + // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB + // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQ { - continue - } - bits := v_0.Args[1] - lo := v_0.Args[0] - if v_1.Op != OpAMD64SHRQ { + if v_0.Op != OpAMD64LEAQ { continue } - _ = v_1.Args[1] - hi := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + x := v_0.Args[0] + y := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } - v.reset(OpAMD64SHLDQ) - v.AddArg3(lo, hi, bits) + v.reset(OpAMD64LEAQ1) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(x, y) return true } break } - // match: (ORQ (SHRXQ lo bits) (SHLXQ hi (NEGQ bits))) - // result: (SHRDQ lo hi bits) + // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRXQ { - continue - } - bits := v_0.Args[1] - lo := v_0.Args[0] - if v_1.Op != OpAMD64SHLXQ { + x := v_0 + if v_1.Op != OpAMD64LEAQ1 { continue } - _ = v_1.Args[1] - hi := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + y := v_1.Args[1] + if y != v_1.Args[0] || !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } - v.reset(OpAMD64SHRDQ) - v.AddArg3(lo, hi, bits) + v.reset(OpAMD64LEAQ2) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(x, y) return true } break } - // match: (ORQ (SHLXQ lo bits) (SHRXQ hi (NEGQ bits))) - // result: (SHLDQ lo hi bits) + // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXQ { - continue - } - bits := v_0.Args[1] - lo := v_0.Args[0] - if v_1.Op != OpAMD64SHRXQ { + x := v_0 + if v_1.Op != OpAMD64LEAQ1 { continue } + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) _ = v_1.Args[1] - hi := v_1.Args[0] + v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { - continue + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if x != v_1_0 { + continue + } + y := v_1_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + continue + } + v.reset(OpAMD64LEAQ2) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(y, x) + return true } - v.reset(OpAMD64SHLDQ) - v.AddArg3(lo, hi, bits) - return true } break } - // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) - // result: (MOVQconst [c|d]) + // match: (LEAQ1 [0] x y) + // cond: v.Aux == nil + // result: (ADDQ x y) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64MOVQconst { - continue - } - c := auxIntToInt64(v_0.AuxInt) - if v_1.Op != OpAMD64MOVQconst { - continue - } - d := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(c | d) - return true + if auxIntToInt32(v.AuxInt) != 0 { + break } - break - } - // match: (ORQ x x) - // result: x - for { x := v_0 - if x != v_1 { + y := v_1 + if !(v.Aux == nil) { break } - v.copyOf(x) + v.reset(OpAMD64ADDQ) + v.AddArg2(x, y) return true } - // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ORQload x [off] {sym} ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVQload { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - continue - } - v.reset(OpAMD64ORQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } return false } -func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ORQconst [c] (ORQconst [d] x)) - // result: (ORQconst [c | d] x) - for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64ORQconst { + // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) + // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB + // result: (LEAQ2 [c+d] {s} x y) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] - v.reset(OpAMD64ORQconst) - v.AuxInt = int32ToAuxInt(c | d) - v.AddArg(x) + y := v_1 + if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ2) + v.AuxInt = int32ToAuxInt(c + d) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } - // match: (ORQconst [0] x) - // result: x + // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) + // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB + // result: (LEAQ2 [c+2*d] {s} x y) for { - if auxIntToInt32(v.AuxInt) != 0 { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + x := v_0 + if v_1.Op != OpAMD64ADDQconst { break } - x := v_0 - v.copyOf(x) + d := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ2) + v.AuxInt = int32ToAuxInt(c + 2*d) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } - // match: (ORQconst [-1] _) - // result: (MOVQconst [-1]) + // match: (LEAQ2 [c] {s} x z:(ADDQ y y)) + // cond: x != z + // result: (LEAQ4 [c] {s} x y) for { - if auxIntToInt32(v.AuxInt) != -1 { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + x := v_0 + z := v_1 + if z.Op != OpAMD64ADDQ { break } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(-1) + y := z.Args[1] + if y != z.Args[0] || !(x != z) { + break + } + v.reset(OpAMD64LEAQ4) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } - // match: (ORQconst [c] (MOVQconst [d])) - // result: (MOVQconst [int64(c)|d]) + // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) + // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + s := auxToSym(v.Aux) + x := v_0 + if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { break } - d := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(c) | d) + y := v_1.Args[0] + v.reset(OpAMD64LEAQ8) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpAMD64ORQconstmodify(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (ORQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) - // result: (ORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) + // match: (LEAQ2 [0] {s} (ADDQ x x) x) + // cond: s == nil + // result: (SHLQconst [2] x) for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + if auxIntToInt32(v.AuxInt) != 0 { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2)) { + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQ { break } - v.reset(OpAMD64ORQconstmodify) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(sym) - v.AddArg2(base, mem) + x := v_0.Args[1] + if x != v_0.Args[0] || x != v_1 || !(s == nil) { + break + } + v.reset(OpAMD64SHLQconst) + v.AuxInt = int8ToAuxInt(2) + v.AddArg(x) return true } - // match: (ORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (ORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) + // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB + // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { - valoff1 := auxIntToValAndOff(v.AuxInt) + off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { + x := v_0.Args[0] + y := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } - v.reset(OpAMD64ORQconstmodify) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.reset(OpAMD64LEAQ2) + v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) + v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpAMD64ORQload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQload [off1] {sym} val (ADDQconst [off2] base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (ORQload [off1+off2] {sym} val base mem) + // match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) + // cond: is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil + // result: (LEAQ4 [off1+2*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + sym1 := auxToSym(v.Aux) + x := v_0 + if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + sym2 := auxToSym(v_1.Aux) + y := v_1.Args[1] + if y != v_1.Args[0] || !(is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) { break } - v.reset(OpAMD64ORQload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) + v.reset(OpAMD64LEAQ4) + v.AuxInt = int32ToAuxInt(off1 + 2*off2) + v.Aux = symToAux(sym1) + v.AddArg2(x, y) return true } - // match: (ORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ORQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // match: (LEAQ2 [off] {sym} x (MOVQconst [scale])) + // cond: is32Bit(int64(off)+int64(scale)*2) + // result: (LEAQ [off+int32(scale)*2] {sym} x) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + scale := auxIntToInt64(v_1.AuxInt) + if !(is32Bit(int64(off) + int64(scale)*2)) { break } - v.reset(OpAMD64ORQload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) + v.reset(OpAMD64LEAQ) + v.AuxInt = int32ToAuxInt(off + int32(scale)*2) + v.Aux = symToAux(sym) + v.AddArg(x) return true } - // match: ( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) - // result: ( ORQ x (MOVQf2i y)) + // match: (LEAQ2 [off] {sym} x (MOVLconst [scale])) + // cond: is32Bit(int64(off)+int64(scale)*2) + // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 - ptr := v_1 - if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { + if v_1.Op != OpAMD64MOVLconst { break } - y := v_2.Args[1] - if ptr != v_2.Args[0] { + scale := auxIntToInt32(v_1.AuxInt) + if !(is32Bit(int64(off) + int64(scale)*2)) { break } - v.reset(OpAMD64ORQ) - v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) - v0.AddArg(y) - v.AddArg2(x, v0) + v.reset(OpAMD64LEAQ) + v.AuxInt = int32ToAuxInt(off + int32(scale)*2) + v.Aux = symToAux(sym) + v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64ORQmodify(v *Value) bool { - v_2 := v.Args[2] +func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ORQmodify [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (ORQmodify [off1+off2] {sym} base val mem) + // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) + // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB + // result: (LEAQ4 [c+d] {s} x y) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + y := v_1 + if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } - v.reset(OpAMD64ORQmodify) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.reset(OpAMD64LEAQ4) + v.AuxInt = int32ToAuxInt(c + d) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } - // match: (ORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (ORQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) + // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB + // result: (LEAQ4 [c+4*d] {s} x y) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + x := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + d := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ4) + v.AuxInt = int32ToAuxInt(c + 4*d) + v.Aux = symToAux(s) + v.AddArg2(x, y) + return true + } + // match: (LEAQ4 [c] {s} x z:(ADDQ y y)) + // cond: x != z + // result: (LEAQ8 [c] {s} x y) + for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + x := v_0 + z := v_1 + if z.Op != OpAMD64ADDQ { + break + } + y := z.Args[1] + if y != z.Args[0] || !(x != z) { + break + } + v.reset(OpAMD64LEAQ8) + v.AuxInt = int32ToAuxInt(c) + v.Aux = symToAux(s) + v.AddArg2(x, y) + return true + } + // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB + // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -14842,1638 +24880,1713 @@ func rewriteValueAMD64_OpAMD64ORQmodify(v *Value) bool { } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + x := v_0.Args[0] + y := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } - v.reset(OpAMD64ORQmodify) + v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpAMD64ROLB(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (ROLB x (NEGQ y)) - // result: (RORB x y) + // match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) + // cond: is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil + // result: (LEAQ8 [off1+4*off2] {sym1} x y) for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) x := v_0 - if v_1.Op != OpAMD64NEGQ { + if v_1.Op != OpAMD64LEAQ1 { break } - y := v_1.Args[0] - v.reset(OpAMD64RORB) - v.AddArg2(x, y) - return true - } - // match: (ROLB x (NEGL y)) - // result: (RORB x y) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + y := v_1.Args[1] + if y != v_1.Args[0] || !(is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) { break } - y := v_1.Args[0] - v.reset(OpAMD64RORB) + v.reset(OpAMD64LEAQ8) + v.AuxInt = int32ToAuxInt(off1 + 4*off2) + v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } - // match: (ROLB x (MOVQconst [c])) - // result: (ROLBconst [int8(c&7) ] x) + // match: (LEAQ4 [off] {sym} x (MOVQconst [scale])) + // cond: is32Bit(int64(off)+int64(scale)*4) + // result: (LEAQ [off+int32(scale)*4] {sym} x) for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt(int8(c & 7)) + scale := auxIntToInt64(v_1.AuxInt) + if !(is32Bit(int64(off) + int64(scale)*4)) { + break + } + v.reset(OpAMD64LEAQ) + v.AuxInt = int32ToAuxInt(off + int32(scale)*4) + v.Aux = symToAux(sym) v.AddArg(x) return true } - // match: (ROLB x (MOVLconst [c])) - // result: (ROLBconst [int8(c&7) ] x) + // match: (LEAQ4 [off] {sym} x (MOVLconst [scale])) + // cond: is32Bit(int64(off)+int64(scale)*4) + // result: (LEAQ [off+int32(scale)*4] {sym} x) for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt(int8(c & 7)) + scale := auxIntToInt32(v_1.AuxInt) + if !(is32Bit(int64(off) + int64(scale)*4)) { + break + } + v.reset(OpAMD64LEAQ) + v.AuxInt = int32ToAuxInt(off + int32(scale)*4) + v.Aux = symToAux(sym) v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64ROLBconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ROLBconst x [0]) - // result: x + // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) + // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB + // result: (LEAQ8 [c+d] {s} x y) for { - if auxIntToInt8(v.AuxInt) != 0 { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - x := v_0 - v.copyOf(x) + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + y := v_1 + if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ8) + v.AuxInt = int32ToAuxInt(c + d) + v.Aux = symToAux(s) + v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpAMD64ROLL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (ROLL x (NEGQ y)) - // result: (RORL x y) + // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) + // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB + // result: (LEAQ8 [c+8*d] {s} x y) for { + c := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) x := v_0 - if v_1.Op != OpAMD64NEGQ { + if v_1.Op != OpAMD64ADDQconst { break } + d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] - v.reset(OpAMD64RORL) + if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ8) + v.AuxInt = int32ToAuxInt(c + 8*d) + v.Aux = symToAux(s) v.AddArg2(x, y) return true } - // match: (ROLL x (NEGL y)) - // result: (RORL x y) + // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB + // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { - x := v_0 - if v_1.Op != OpAMD64NEGL { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - y := v_1.Args[0] - v.reset(OpAMD64RORL) + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + x := v_0.Args[0] + y := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ8) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } - // match: (ROLL x (MOVQconst [c])) - // result: (ROLLconst [int8(c&31)] x) + // match: (LEAQ8 [off] {sym} x (MOVQconst [scale])) + // cond: is32Bit(int64(off)+int64(scale)*8) + // result: (LEAQ [off+int32(scale)*8] {sym} x) for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) + scale := auxIntToInt64(v_1.AuxInt) + if !(is32Bit(int64(off) + int64(scale)*8)) { + break + } + v.reset(OpAMD64LEAQ) + v.AuxInt = int32ToAuxInt(off + int32(scale)*8) + v.Aux = symToAux(sym) v.AddArg(x) return true } - // match: (ROLL x (MOVLconst [c])) - // result: (ROLLconst [int8(c&31)] x) + // match: (LEAQ8 [off] {sym} x (MOVLconst [scale])) + // cond: is32Bit(int64(off)+int64(scale)*8) + // result: (LEAQ [off+int32(scale)*8] {sym} x) for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) + scale := auxIntToInt32(v_1.AuxInt) + if !(is32Bit(int64(off) + int64(scale)*8)) { + break + } + v.reset(OpAMD64LEAQ) + v.AuxInt = int32ToAuxInt(off + int32(scale)*8) + v.Aux = symToAux(sym) v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64ROLLconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64LoweredPanicBoundsCR(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ROLLconst x [0]) - // result: x + // match: (LoweredPanicBoundsCR [kind] {p} (MOVQconst [c]) mem) + // result: (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:p.C, Cy:c}} mem) for { - if auxIntToInt8(v.AuxInt) != 0 { + kind := auxIntToInt64(v.AuxInt) + p := auxToPanicBoundsC(v.Aux) + if v_0.Op != OpAMD64MOVQconst { break } - x := v_0 - v.copyOf(x) + c := auxIntToInt64(v_0.AuxInt) + mem := v_1 + v.reset(OpAMD64LoweredPanicBoundsCC) + v.AuxInt = int64ToAuxInt(kind) + v.Aux = panicBoundsCCToAux(PanicBoundsCC{Cx: p.C, Cy: c}) + v.AddArg(mem) return true } return false } -func rewriteValueAMD64_OpAMD64ROLQ(v *Value) bool { +func rewriteValueAMD64_OpAMD64LoweredPanicBoundsRC(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ROLQ x (NEGQ y)) - // result: (RORQ x y) + // match: (LoweredPanicBoundsRC [kind] {p} (MOVQconst [c]) mem) + // result: (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:c, Cy:p.C}} mem) for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { + kind := auxIntToInt64(v.AuxInt) + p := auxToPanicBoundsC(v.Aux) + if v_0.Op != OpAMD64MOVQconst { break } - y := v_1.Args[0] - v.reset(OpAMD64RORQ) - v.AddArg2(x, y) + c := auxIntToInt64(v_0.AuxInt) + mem := v_1 + v.reset(OpAMD64LoweredPanicBoundsCC) + v.AuxInt = int64ToAuxInt(kind) + v.Aux = panicBoundsCCToAux(PanicBoundsCC{Cx: c, Cy: p.C}) + v.AddArg(mem) return true } - // match: (ROLQ x (NEGL y)) - // result: (RORQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - y := v_1.Args[0] - v.reset(OpAMD64RORQ) - v.AddArg2(x, y) - return true - } - // match: (ROLQ x (MOVQconst [c])) - // result: (ROLQconst [int8(c&63)] x) + return false +} +func rewriteValueAMD64_OpAMD64LoweredPanicBoundsRR(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LoweredPanicBoundsRR [kind] x (MOVQconst [c]) mem) + // result: (LoweredPanicBoundsRC [kind] x {PanicBoundsC{C:c}} mem) for { + kind := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64LoweredPanicBoundsRC) + v.AuxInt = int64ToAuxInt(kind) + v.Aux = panicBoundsCToAux(PanicBoundsC{C: c}) + v.AddArg2(x, mem) return true } - // match: (ROLQ x (MOVLconst [c])) - // result: (ROLQconst [int8(c&63)] x) + // match: (LoweredPanicBoundsRR [kind] (MOVQconst [c]) y mem) + // result: (LoweredPanicBoundsCR [kind] {PanicBoundsC{C:c}} y mem) for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + kind := auxIntToInt64(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) + c := auxIntToInt64(v_0.AuxInt) + y := v_1 + mem := v_2 + v.reset(OpAMD64LoweredPanicBoundsCR) + v.AuxInt = int64ToAuxInt(kind) + v.Aux = panicBoundsCToAux(PanicBoundsC{C: c}) + v.AddArg2(y, mem) return true } return false } -func rewriteValueAMD64_OpAMD64ROLQconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVBELstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ROLQconst x [0]) - // result: x + // match: (MOVBELstore [i] {s} p x:(BSWAPL w) mem) + // cond: x.Uses == 1 + // result: (MOVLstore [i] {s} p w mem) for { - if auxIntToInt8(v.AuxInt) != 0 { + i := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + p := v_0 + x := v_1 + if x.Op != OpAMD64BSWAPL { break } - x := v_0 - v.copyOf(x) + w := x.Args[0] + mem := v_2 + if !(x.Uses == 1) { + break + } + v.reset(OpAMD64MOVLstore) + v.AuxInt = int32ToAuxInt(i) + v.Aux = symToAux(s) + v.AddArg3(p, w, mem) return true } return false } -func rewriteValueAMD64_OpAMD64ROLW(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVBEQstore(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ROLW x (NEGQ y)) - // result: (RORW x y) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - y := v_1.Args[0] - v.reset(OpAMD64RORW) - v.AddArg2(x, y) - return true - } - // match: (ROLW x (NEGL y)) - // result: (RORW x y) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - y := v_1.Args[0] - v.reset(OpAMD64RORW) - v.AddArg2(x, y) - return true - } - // match: (ROLW x (MOVQconst [c])) - // result: (ROLWconst [int8(c&15)] x) + // match: (MOVBEQstore [i] {s} p x:(BSWAPQ w) mem) + // cond: x.Uses == 1 + // result: (MOVQstore [i] {s} p w mem) for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + i := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + p := v_0 + x := v_1 + if x.Op != OpAMD64BSWAPQ { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(int8(c & 15)) - v.AddArg(x) - return true - } - // match: (ROLW x (MOVLconst [c])) - // result: (ROLWconst [int8(c&15)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + w := x.Args[0] + mem := v_2 + if !(x.Uses == 1) { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(int8(c & 15)) - v.AddArg(x) + v.reset(OpAMD64MOVQstore) + v.AuxInt = int32ToAuxInt(i) + v.Aux = symToAux(s) + v.AddArg3(p, w, mem) return true } return false } -func rewriteValueAMD64_OpAMD64ROLWconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVBEWstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ROLWconst x [0]) - // result: x + // match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) + // cond: x.Uses == 1 + // result: (MOVWstore [i] {s} p w mem) for { - if auxIntToInt8(v.AuxInt) != 0 { + i := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + p := v_0 + x := v_1 + if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } - x := v_0 - v.copyOf(x) + w := x.Args[0] + mem := v_2 + if !(x.Uses == 1) { + break + } + v.reset(OpAMD64MOVWstore) + v.AuxInt = int32ToAuxInt(i) + v.Aux = symToAux(s) + v.AddArg3(p, w, mem) return true } return false } -func rewriteValueAMD64_OpAMD64RORB(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value) bool { v_0 := v.Args[0] - // match: (RORB x (NEGQ y)) - // result: (ROLB x y) + b := v.Block + // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 - if v_1.Op != OpAMD64NEGQ { + if x.Op != OpAMD64MOVBload { break } - y := v_1.Args[0] - v.reset(OpAMD64ROLB) - v.AddArg2(x, y) - return true - } - // match: (RORB x (NEGL y)) - // result: (ROLB x y) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { break } - y := v_1.Args[0] - v.reset(OpAMD64ROLB) - v.AddArg2(x, y) + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (RORB x (MOVQconst [c])) - // result: (ROLBconst [int8((-c)&7) ] x) + // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 - if v_1.Op != OpAMD64MOVQconst { + if x.Op != OpAMD64MOVWload { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt(int8((-c) & 7)) - v.AddArg(x) - return true - } - // match: (RORB x (MOVLconst [c])) - // result: (ROLBconst [int8((-c)&7) ] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt(int8((-c) & 7)) - v.AddArg(x) + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64RORL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (RORL x (NEGQ y)) - // result: (ROLL x y) + // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 - if v_1.Op != OpAMD64NEGQ { + if x.Op != OpAMD64MOVLload { break } - y := v_1.Args[0] - v.reset(OpAMD64ROLL) - v.AddArg2(x, y) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (RORL x (NEGL y)) - // result: (ROLL x y) + // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 - if v_1.Op != OpAMD64NEGL { + if x.Op != OpAMD64MOVQload { break } - y := v_1.Args[0] - v.reset(OpAMD64ROLL) - v.AddArg2(x, y) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (RORL x (MOVQconst [c])) - // result: (ROLLconst [int8((-c)&31)] x) + // match: (MOVBQSX (ANDLconst [c] x)) + // cond: c & 0x80 == 0 + // result: (ANDLconst [c & 0x7f] x) for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + if v_0.Op != OpAMD64ANDLconst { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt(int8((-c) & 31)) + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(c&0x80 == 0) { + break + } + v.reset(OpAMD64ANDLconst) + v.AuxInt = int32ToAuxInt(c & 0x7f) v.AddArg(x) return true } - // match: (RORL x (MOVLconst [c])) - // result: (ROLLconst [int8((-c)&31)] x) + // match: (MOVBQSX (MOVBQSX x)) + // result: (MOVBQSX x) for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + if v_0.Op != OpAMD64MOVBQSX { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt(int8((-c) & 31)) + x := v_0.Args[0] + v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64RORQ(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (RORQ x (NEGQ y)) - // result: (ROLQ x y) + // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: (MOVBQSX x) for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVBstore { break } - y := v_1.Args[0] - v.reset(OpAMD64ROLQ) - v.AddArg2(x, y) - return true - } - // match: (RORQ x (NEGL y)) - // result: (ROLQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + x := v_1.Args[1] + ptr2 := v_1.Args[0] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } - y := v_1.Args[0] - v.reset(OpAMD64ROLQ) - v.AddArg2(x, y) + v.reset(OpAMD64MOVBQSX) + v.AddArg(x) return true } - // match: (RORQ x (MOVQconst [c])) - // result: (ROLQconst [int8((-c)&63)] x) + // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt(int8((-c) & 63)) - v.AddArg(x) + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVBQSXload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) return true } - // match: (RORQ x (MOVLconst [c])) - // result: (ROLQconst [int8((-c)&63)] x) + // match: (MOVBQSXload [off] {sym} (SB) _) + // cond: symIsRO(sym) + // result: (MOVQconst [int64(int8(read8(sym, int64(off))))]) for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpSB || !(symIsRO(sym)) { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt(int8((-c) & 63)) - v.AddArg(x) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(int8(read8(sym, int64(off))))) return true } return false } -func rewriteValueAMD64_OpAMD64RORW(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value) bool { v_0 := v.Args[0] - // match: (RORW x (NEGQ y)) - // result: (ROLW x y) + b := v.Block + // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 - if v_1.Op != OpAMD64NEGQ { + if x.Op != OpAMD64MOVBload { break } - y := v_1.Args[0] - v.reset(OpAMD64ROLW) - v.AddArg2(x, y) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (RORW x (NEGL y)) - // result: (ROLW x y) + // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 - if v_1.Op != OpAMD64NEGL { + if x.Op != OpAMD64MOVWload { break } - y := v_1.Args[0] - v.reset(OpAMD64ROLW) - v.AddArg2(x, y) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (RORW x (MOVQconst [c])) - // result: (ROLWconst [int8((-c)&15)] x) + // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 - if v_1.Op != OpAMD64MOVQconst { + if x.Op != OpAMD64MOVLload { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(int8((-c) & 15)) - v.AddArg(x) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (RORW x (MOVLconst [c])) - // result: (ROLWconst [int8((-c)&15)] x) + // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 - if v_1.Op != OpAMD64MOVLconst { + if x.Op != OpAMD64MOVQload { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(int8((-c) & 15)) - v.AddArg(x) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SARB(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (SARB x (MOVQconst [c])) - // result: (SARBconst [int8(min(int64(c)&31,7))] x) + // match: (MOVBQZX (ANDLconst [c] x)) + // result: (ANDLconst [c & 0xff] x) for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + if v_0.Op != OpAMD64ANDLconst { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SARBconst) - v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 7))) + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + v.reset(OpAMD64ANDLconst) + v.AuxInt = int32ToAuxInt(c & 0xff) v.AddArg(x) return true } - // match: (SARB x (MOVLconst [c])) - // result: (SARBconst [int8(min(int64(c)&31,7))] x) + // match: (MOVBQZX (MOVBQZX x)) + // result: (MOVBQZX x) for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + if v_0.Op != OpAMD64MOVBQZX { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SARBconst) - v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 7))) + x := v_0.Args[0] + v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64SARBconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (SARBconst x [0]) - // result: x + // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { - if auxIntToInt8(v.AuxInt) != 0 { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - x := v_0 - v.copyOf(x) + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64MOVBatomicload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SARBconst [c] (MOVQconst [d])) - // result: (MOVQconst [int64(int8(d))>>uint64(c)]) + // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - d := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(int8(d)) >> uint64(c)) + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVBatomicload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(ptr, mem) return true } return false } -func rewriteValueAMD64_OpAMD64SARL(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (SARL x (MOVQconst [c])) - // result: (SARLconst [int8(c&31)] x) + // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: (MOVBQZX x) for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVBstore { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SARLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + x := v_1.Args[1] + ptr2 := v_1.Args[0] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + break + } + v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } - // match: (SARL x (MOVLconst [c])) - // result: (SARLconst [int8(c&31)] x) + // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVBload [off1+off2] {sym} ptr mem) for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SARLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64MOVBload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SARL x (ADDQconst [c] y)) - // cond: c & 31 == 0 - // result: (SARL x y) + // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SARL) - v.AddArg2(x, y) + v.reset(OpAMD64MOVBload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) return true } - // match: (SARL x (NEGQ (ADDQconst [c] y))) - // cond: c & 31 == 0 - // result: (SARL x (NEGQ y)) + // match: (MOVBload [off] {sym} (SB) _) + // cond: symIsRO(sym) + // result: (MOVLconst [int32(read8(sym, int64(off)))]) for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpSB || !(symIsRO(sym)) { break } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(int32(read8(sym, int64(off)))) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) + // cond: y.Uses == 1 + // result: (SETLstore [off] {sym} ptr x mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SETL { break } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { + x := y.Args[0] + mem := v_2 + if !(y.Uses == 1) { break } - v.reset(OpAMD64SARL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) + v.reset(OpAMD64SETLstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (SARL x (ANDQconst [c] y)) - // cond: c & 31 == 31 - // result: (SARL x y) + // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) + // cond: y.Uses == 1 + // result: (SETLEstore [off] {sym} ptr x mem) for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SETLE { break } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { + x := y.Args[0] + mem := v_2 + if !(y.Uses == 1) { break } - v.reset(OpAMD64SARL) - v.AddArg2(x, y) + v.reset(OpAMD64SETLEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (SARL x (NEGQ (ANDQconst [c] y))) - // cond: c & 31 == 31 - // result: (SARL x (NEGQ y)) + // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) + // cond: y.Uses == 1 + // result: (SETGstore [off] {sym} ptr x mem) for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SETG { break } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { + x := y.Args[0] + mem := v_2 + if !(y.Uses == 1) { break } - v.reset(OpAMD64SARL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) + v.reset(OpAMD64SETGstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (SARL x (ADDLconst [c] y)) - // cond: c & 31 == 0 - // result: (SARL x y) + // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) + // cond: y.Uses == 1 + // result: (SETGEstore [off] {sym} ptr x mem) for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SETGE { break } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { + x := y.Args[0] + mem := v_2 + if !(y.Uses == 1) { break } - v.reset(OpAMD64SARL) - v.AddArg2(x, y) + v.reset(OpAMD64SETGEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (SARL x (NEGL (ADDLconst [c] y))) - // cond: c & 31 == 0 - // result: (SARL x (NEGL y)) + // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) + // cond: y.Uses == 1 + // result: (SETEQstore [off] {sym} ptr x mem) for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SETEQ { break } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { + x := y.Args[0] + mem := v_2 + if !(y.Uses == 1) { break } - v.reset(OpAMD64SARL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) + v.reset(OpAMD64SETEQstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (SARL x (ANDLconst [c] y)) - // cond: c & 31 == 31 - // result: (SARL x y) + // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) + // cond: y.Uses == 1 + // result: (SETNEstore [off] {sym} ptr x mem) for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SETNE { break } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { + x := y.Args[0] + mem := v_2 + if !(y.Uses == 1) { break } - v.reset(OpAMD64SARL) - v.AddArg2(x, y) + v.reset(OpAMD64SETNEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (SARL x (NEGL (ANDLconst [c] y))) - // cond: c & 31 == 31 - // result: (SARL x (NEGL y)) + // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) + // cond: y.Uses == 1 + // result: (SETBstore [off] {sym} ptr x mem) for { - x := v_0 - if v_1.Op != OpAMD64NEGL { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SETB { break } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { + x := y.Args[0] + mem := v_2 + if !(y.Uses == 1) { break } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) + // cond: y.Uses == 1 + // result: (SETBEstore [off] {sym} ptr x mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SETBE { break } - v.reset(OpAMD64SARL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) + x := y.Args[0] + mem := v_2 + if !(y.Uses == 1) { + break + } + v.reset(OpAMD64SETBEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (SARL l:(MOVLload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SARXLload [off] {sym} ptr x mem) + // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) + // cond: y.Uses == 1 + // result: (SETAstore [off] {sym} ptr x mem) for { - l := v_0 - if l.Op != OpAMD64MOVLload { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SETA { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + x := y.Args[0] + mem := v_2 + if !(y.Uses == 1) { break } - v.reset(OpAMD64SARXLload) + v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { - v_0 := v.Args[0] - // match: (SARLconst x [0]) - // result: x + // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) + // cond: y.Uses == 1 + // result: (SETAEstore [off] {sym} ptr x mem) for { - if auxIntToInt8(v.AuxInt) != 0 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SETAE { break } - x := v_0 - v.copyOf(x) + x := y.Args[0] + mem := v_2 + if !(y.Uses == 1) { + break + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (SARLconst [c] (MOVQconst [d])) - // result: (MOVQconst [int64(int32(d))>>uint64(c)]) + // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) + // result: (MOVBstore [off] {sym} ptr x mem) for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVBQSX { break } - d := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(int32(d)) >> uint64(c)) + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SARQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SARQ x (MOVQconst [c])) - // result: (SARQconst [int8(c&63)] x) + // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) + // result: (MOVBstore [off] {sym} ptr x mem) for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVBQZX { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SARQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (SARQ x (MOVLconst [c])) - // result: (SARQconst [int8(c&63)] x) + // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SARQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(ptr, val, mem) return true } - // match: (SARQ x (ADDQconst [c] y)) - // cond: c & 63 == 0 - // result: (SARQ x y) + // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) + // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SARQ) - v.AddArg2(x, y) + mem := v_2 + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SARQ x (NEGQ (ADDQconst [c] y))) - // cond: c & 63 == 0 - // result: (SARQ x (NEGQ y)) + // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) + // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SARQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) + c := auxIntToInt64(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SARQ x (ANDQconst [c] y)) - // cond: c & 63 == 63 - // result: (SARQ x y) + // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SARQ) - v.AddArg2(x, y) + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (SARQ x (NEGQ (ANDQconst [c] y))) - // cond: c & 63 == 63 - // result: (SARQ x (NEGQ y)) + // match: (MOVBstore [off] {sym} ptr (KMOVBi mask) mem) + // result: (KMOVBstore [off] {sym} ptr mask mem) for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64KMOVBi { break } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { + mask := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64KMOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) + // cond: ValAndOff(sc).canAdd32(off) + // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) + for { + sc := auxIntToValAndOff(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { + off := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(ValAndOff(sc).canAdd32(off)) { break } - v.reset(OpAMD64SARQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) + v.Aux = symToAux(s) + v.AddArg2(ptr, mem) return true } - // match: (SARQ x (ADDLconst [c] y)) - // cond: c & 63 == 0 - // result: (SARQ x y) + // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) + // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) + // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { + sc := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { + off := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + mem := v_1 + if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } - v.reset(OpAMD64SARQ) - v.AddArg2(x, y) + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(ptr, mem) return true } - // match: (SARQ x (NEGL (ADDLconst [c] y))) - // cond: c & 63 == 0 - // result: (SARQ x (NEGL y)) + return false +} +func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { + if x.Op != OpAMD64MOVLload { break } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { break } - v.reset(OpAMD64SARQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (SARQ x (ANDLconst [c] y)) - // cond: c & 63 == 63 - // result: (SARQ x y) + // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 - if v_1.Op != OpAMD64ANDLconst { + if x.Op != OpAMD64MOVQload { break } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { break } - v.reset(OpAMD64SARQ) - v.AddArg2(x, y) + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (SARQ x (NEGL (ANDLconst [c] y))) - // cond: c & 63 == 63 - // result: (SARQ x (NEGL y)) + // match: (MOVLQSX (ANDLconst [c] x)) + // cond: uint32(c) & 0x80000000 == 0 + // result: (ANDLconst [c & 0x7fffffff] x) for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { + if v_0.Op != OpAMD64ANDLconst { break } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(uint32(c)&0x80000000 == 0) { break } - v.reset(OpAMD64SARQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) + v.reset(OpAMD64ANDLconst) + v.AuxInt = int32ToAuxInt(c & 0x7fffffff) + v.AddArg(x) return true } - // match: (SARQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SARXQload [off] {sym} ptr x mem) + // match: (MOVLQSX (MOVLQSX x)) + // result: (MOVLQSX x) for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + if v_0.Op != OpAMD64MOVLQSX { break } - v.reset(OpAMD64SARXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + x := v_0.Args[0] + v.reset(OpAMD64MOVLQSX) + v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { - v_0 := v.Args[0] - // match: (SARQconst x [0]) - // result: x + // match: (MOVLQSX (MOVWQSX x)) + // result: (MOVWQSX x) for { - if auxIntToInt8(v.AuxInt) != 0 { + if v_0.Op != OpAMD64MOVWQSX { break } - x := v_0 - v.copyOf(x) + x := v_0.Args[0] + v.reset(OpAMD64MOVWQSX) + v.AddArg(x) return true } - // match: (SARQconst [c] (MOVQconst [d])) - // result: (MOVQconst [d>>uint64(c)]) + // match: (MOVLQSX (MOVBQSX x)) + // result: (MOVBQSX x) for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + if v_0.Op != OpAMD64MOVBQSX { break } - d := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(d >> uint64(c)) + x := v_0.Args[0] + v.reset(OpAMD64MOVBQSX) + v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64SARW(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (SARW x (MOVQconst [c])) - // result: (SARWconst [int8(min(int64(c)&31,15))] x) + b := v.Block + config := b.Func.Config + // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: (MOVLQSX x) for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVLstore { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SARWconst) - v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) - v.AddArg(x) - return true - } - // match: (SARW x (MOVLconst [c])) - // result: (SARWconst [int8(min(int64(c)&31,15))] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + x := v_1.Args[1] + ptr2 := v_1.Args[0] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SARWconst) - v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) + v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpAMD64SARWconst(v *Value) bool { - v_0 := v.Args[0] - // match: (SARWconst x [0]) - // result: x + // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { - if auxIntToInt8(v.AuxInt) != 0 { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - x := v_0 - v.copyOf(x) - return true - } - // match: (SARWconst [c] (MOVQconst [d])) - // result: (MOVQconst [int64(int16(d))>>uint64(c)]) - for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - d := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(int16(d)) >> uint64(c)) + v.reset(OpAMD64MOVLQSXload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SARXLload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SARXLload [off] {sym} ptr (MOVLconst [c]) mem) - // result: (SARLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) + // match: (MOVLQSXload [off] {sym} (SB) _) + // cond: symIsRO(sym) + // result: (MOVQconst [int64(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLconst { + if v_0.Op != OpSB || !(symIsRO(sym)) { break } - c := auxIntToInt32(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64SARLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - v.AddArg(v0) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder)))) return true } return false } -func rewriteValueAMD64_OpAMD64SARXQload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (SARXQload [off] {sym} ptr (MOVQconst [c]) mem) - // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) + // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVLload [off] {sym} ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVQconst { + x := v_0 + if x.Op != OpAMD64MOVLload { break } - c := auxIntToInt64(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64SARQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) + v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) - v.AddArg(v0) return true } - // match: (SARXQload [off] {sym} ptr (MOVLconst [c]) mem) - // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) + // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVLload [off] {sym} ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLconst { + x := v_0 + if x.Op != OpAMD64MOVQload { break } - c := auxIntToInt32(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64SARQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) + v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) - v.AddArg(v0) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value) bool { - v_0 := v.Args[0] - // match: (SBBLcarrymask (FlagEQ)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagEQ { - break - } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) return true } - // match: (SBBLcarrymask (FlagLT_ULT)) - // result: (MOVLconst [-1]) + // match: (MOVLQZX (ANDLconst [c] x)) + // result: (ANDLconst [c] x) for { - if v_0.Op != OpAMD64FlagLT_ULT { + if v_0.Op != OpAMD64ANDLconst { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(-1) + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + v.reset(OpAMD64ANDLconst) + v.AuxInt = int32ToAuxInt(c) + v.AddArg(x) return true } - // match: (SBBLcarrymask (FlagLT_UGT)) - // result: (MOVLconst [0]) + // match: (MOVLQZX (MOVLQZX x)) + // result: (MOVLQZX x) for { - if v_0.Op != OpAMD64FlagLT_UGT { + if v_0.Op != OpAMD64MOVLQZX { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + x := v_0.Args[0] + v.reset(OpAMD64MOVLQZX) + v.AddArg(x) return true } - // match: (SBBLcarrymask (FlagGT_ULT)) - // result: (MOVLconst [-1]) + // match: (MOVLQZX (MOVWQZX x)) + // result: (MOVWQZX x) for { - if v_0.Op != OpAMD64FlagGT_ULT { + if v_0.Op != OpAMD64MOVWQZX { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(-1) + x := v_0.Args[0] + v.reset(OpAMD64MOVWQZX) + v.AddArg(x) return true } - // match: (SBBLcarrymask (FlagGT_UGT)) - // result: (MOVLconst [0]) + // match: (MOVLQZX (MOVBQZX x)) + // result: (MOVBQZX x) for { - if v_0.Op != OpAMD64FlagGT_UGT { + if v_0.Op != OpAMD64MOVBQZX { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + x := v_0.Args[0] + v.reset(OpAMD64MOVBQZX) + v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64SBBQ(v *Value) bool { - v_2 := v.Args[2] +func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (SBBQ x (MOVQconst [c]) borrow) - // cond: is32Bit(c) - // result: (SBBQconst x [int32(c)] borrow) + // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - c := auxIntToInt64(v_1.AuxInt) - borrow := v_2 - if !(is32Bit(c)) { + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64SBBQconst) - v.AuxInt = int32ToAuxInt(int32(c)) - v.AddArg2(x, borrow) + v.reset(OpAMD64MOVLatomicload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SBBQ x y (FlagEQ)) - // result: (SUBQborrow x y) + // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { - x := v_0 - y := v_1 - if v_2.Op != OpAMD64FlagEQ { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - v.reset(OpAMD64SUBQborrow) - v.AddArg2(x, y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value) bool { - v_0 := v.Args[0] - // match: (SBBQcarrymask (FlagEQ)) - // result: (MOVQconst [0]) - for { - if v_0.Op != OpAMD64FlagEQ { - break - } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(0) - return true - } - // match: (SBBQcarrymask (FlagLT_ULT)) - // result: (MOVQconst [-1]) - for { - if v_0.Op != OpAMD64FlagLT_ULT { - break - } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(-1) - return true - } - // match: (SBBQcarrymask (FlagLT_UGT)) - // result: (MOVQconst [0]) - for { - if v_0.Op != OpAMD64FlagLT_UGT { - break - } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(0) - return true - } - // match: (SBBQcarrymask (FlagGT_ULT)) - // result: (MOVQconst [-1]) - for { - if v_0.Op != OpAMD64FlagGT_ULT { - break - } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(-1) - return true - } - // match: (SBBQcarrymask (FlagGT_UGT)) - // result: (MOVQconst [0]) - for { - if v_0.Op != OpAMD64FlagGT_UGT { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(0) + v.reset(OpAMD64MOVLatomicload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(ptr, mem) return true } return false } -func rewriteValueAMD64_OpAMD64SBBQconst(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64MOVLf2i(v *Value) bool { v_0 := v.Args[0] - // match: (SBBQconst x [c] (FlagEQ)) - // result: (SUBQconstborrow x [c]) + b := v.Block + // match: (MOVLf2i (Arg [off] {sym})) + // cond: t.Size() == u.Size() + // result: @b.Func.Entry (Arg [off] {sym}) for { - c := auxIntToInt32(v.AuxInt) - x := v_0 - if v_1.Op != OpAMD64FlagEQ { + t := v.Type + if v_0.Op != OpArg { break } - v.reset(OpAMD64SUBQconstborrow) - v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) + u := v_0.Type + off := auxIntToInt32(v_0.AuxInt) + sym := auxToSym(v_0.Aux) + if !(t.Size() == u.Size()) { + break + } + b = b.Func.Entry + v0 := b.NewValue0(v.Pos, OpArg, t) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) return true } return false } -func rewriteValueAMD64_OpAMD64SETA(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVLi2f(v *Value) bool { v_0 := v.Args[0] - // match: (SETA (InvertFlags x)) - // result: (SETB x) - for { - if v_0.Op != OpAMD64InvertFlags { - break - } - x := v_0.Args[0] - v.reset(OpAMD64SETB) - v.AddArg(x) - return true - } - // match: (SETA (FlagEQ)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagEQ { - break - } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } - // match: (SETA (FlagLT_ULT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagLT_ULT { - break - } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } - // match: (SETA (FlagLT_UGT)) - // result: (MOVLconst [1]) - for { - if v_0.Op != OpAMD64FlagLT_UGT { - break - } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) - return true - } - // match: (SETA (FlagGT_ULT)) - // result: (MOVLconst [0]) + b := v.Block + // match: (MOVLi2f (Arg [off] {sym})) + // cond: t.Size() == u.Size() + // result: @b.Func.Entry (Arg [off] {sym}) for { - if v_0.Op != OpAMD64FlagGT_ULT { + t := v.Type + if v_0.Op != OpArg { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } - // match: (SETA (FlagGT_UGT)) - // result: (MOVLconst [1]) - for { - if v_0.Op != OpAMD64FlagGT_UGT { + u := v_0.Type + off := auxIntToInt32(v_0.AuxInt) + sym := auxToSym(v_0.Aux) + if !(t.Size() == u.Size()) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + b = b.Func.Entry + v0 := b.NewValue0(v.Pos, OpArg, t) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) return true } return false } -func rewriteValueAMD64_OpAMD64SETAE(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (SETAE (TESTQ x x)) - // result: (ConstBool [true]) - for { - if v_0.Op != OpAMD64TESTQ { - break - } - x := v_0.Args[1] - if x != v_0.Args[0] { - break - } - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(true) - return true - } - // match: (SETAE (TESTL x x)) - // result: (ConstBool [true]) - for { - if v_0.Op != OpAMD64TESTL { - break - } - x := v_0.Args[1] - if x != v_0.Args[0] { - break - } - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(true) - return true - } - // match: (SETAE (TESTW x x)) - // result: (ConstBool [true]) - for { - if v_0.Op != OpAMD64TESTW { - break - } - x := v_0.Args[1] - if x != v_0.Args[0] { - break - } - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(true) - return true - } - // match: (SETAE (TESTB x x)) - // result: (ConstBool [true]) - for { - if v_0.Op != OpAMD64TESTB { - break - } - x := v_0.Args[1] - if x != v_0.Args[0] { - break - } - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(true) - return true - } - // match: (SETAE (BTLconst [0] x)) - // result: (XORLconst [1] (ANDLconst [1] x)) - for { - if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { - break - } - x := v_0.Args[0] - v.reset(OpAMD64XORLconst) - v.AuxInt = int32ToAuxInt(1) - v0 := b.NewValue0(v.Pos, OpAMD64ANDLconst, typ.Bool) - v0.AuxInt = int32ToAuxInt(1) - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETAE (BTQconst [0] x)) - // result: (XORLconst [1] (ANDLconst [1] x)) - for { - if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { - break - } - x := v_0.Args[0] - v.reset(OpAMD64XORLconst) - v.AuxInt = int32ToAuxInt(1) - v0 := b.NewValue0(v.Pos, OpAMD64ANDLconst, typ.Bool) - v0.AuxInt = int32ToAuxInt(1) - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETAE c:(CMPQconst [128] x)) - // cond: c.Uses == 1 - // result: (SETA (CMPQconst [127] x)) + config := b.Func.Config + // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: (MOVLQZX x) for { - c := v_0 - if c.Op != OpAMD64CMPQconst || auxIntToInt32(c.AuxInt) != 128 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVLstore { break } - x := c.Args[0] - if !(c.Uses == 1) { + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + x := v_1.Args[1] + ptr2 := v_1.Args[0] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } - v.reset(OpAMD64SETA) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64MOVLQZX) + v.AddArg(x) return true } - // match: (SETAE c:(CMPLconst [128] x)) - // cond: c.Uses == 1 - // result: (SETA (CMPLconst [127] x)) + // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVLload [off1+off2] {sym} ptr mem) for { - c := v_0 - if c.Op != OpAMD64CMPLconst || auxIntToInt32(c.AuxInt) != 128 { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - x := c.Args[0] - if !(c.Uses == 1) { + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64SETA) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64MOVLload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SETAE (InvertFlags x)) - // result: (SETBE x) + // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { - if v_0.Op != OpAMD64InvertFlags { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - x := v_0.Args[0] - v.reset(OpAMD64SETBE) - v.AddArg(x) - return true - } - // match: (SETAE (FlagEQ)) - // result: (MOVLconst [1]) - for { - if v_0.Op != OpAMD64FlagEQ { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + v.reset(OpAMD64MOVLload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) return true } - // match: (SETAE (FlagLT_ULT)) - // result: (MOVLconst [0]) + // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) + // result: (MOVLf2i val) for { - if v_0.Op != OpAMD64FlagLT_ULT { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVSSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } - // match: (SETAE (FlagLT_UGT)) - // result: (MOVLconst [1]) - for { - if v_0.Op != OpAMD64FlagLT_UGT { + val := v_1.Args[1] + if ptr != v_1.Args[0] { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + v.reset(OpAMD64MOVLf2i) + v.AddArg(val) return true } - // match: (SETAE (FlagGT_ULT)) - // result: (MOVLconst [0]) + // match: (MOVLload [off] {sym} (SB) _) + // cond: symIsRO(sym) && is32BitInt(t) + // result: (MOVLconst [int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { - if v_0.Op != OpAMD64FlagGT_ULT { + t := v.Type + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpSB || !(symIsRO(sym) && is32BitInt(t)) { break } v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.AuxInt = int32ToAuxInt(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } - // match: (SETAE (FlagGT_UGT)) - // result: (MOVLconst [1]) + // match: (MOVLload [off] {sym} (SB) _) + // cond: symIsRO(sym) && is64BitInt(t) + // result: (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { - if v_0.Op != OpAMD64FlagGT_UGT { + t := v.Type + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpSB || !(symIsRO(sym) && is64BitInt(t)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } -func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) - // result: (SETBEstore [off] {sym} ptr x mem) + // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) + // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64InvertFlags { + if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] mem := v_2 - v.reset(OpAMD64SETBEstore) + v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } - // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) + // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) + // result: (MOVLstore [off] {sym} ptr x mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVLQZX { + break + } + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64MOVLstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SETAEstore [off1+off2] {sym} base val mem) + // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -16481,21 +26594,55 @@ func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { break } off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] + ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64SETAEstore) + v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.AddArg3(ptr, val, mem) return true } - // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) + // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) + // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -16510,539 +26657,792 @@ func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SETAEstore) + v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } - // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) + // cond: y.Uses==1 && clobber(y) + // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagEQ { + y := v_1 + if y.Op != OpAMD64ADDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) + mem := y.Args[2] + x := y.Args[0] + if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + break + } + v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) + // cond: y.Uses==1 && clobber(y) + // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagLT_ULT { + y := v_1 + if y.Op != OpAMD64ANDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) + mem := y.Args[2] + x := y.Args[0] + if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + break + } + v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) + // cond: y.Uses==1 && clobber(y) + // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagLT_UGT { + y := v_1 + if y.Op != OpAMD64ORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) + mem := y.Args[2] + x := y.Args[0] + if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + break + } + v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) + // cond: y.Uses==1 && clobber(y) + // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagGT_ULT { + y := v_1 + if y.Op != OpAMD64XORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) + mem := y.Args[2] + x := y.Args[0] + if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + break + } + v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) + // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) + // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagGT_UGT { + y := v_1 + if y.Op != OpAMD64ADDL { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) - return true + _ = y.Args[1] + y_0 := y.Args[0] + y_1 := y.Args[1] + for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { + l := y_0 + if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + continue + } + mem := l.Args[1] + if ptr != l.Args[0] { + continue + } + x := y_1 + if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { + continue + } + v.reset(OpAMD64ADDLmodify) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) - // result: (SETBstore [off] {sym} ptr x mem) + // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) + // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) + // result: (SUBLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64InvertFlags { + y := v_1 + if y.Op != OpAMD64SUBL { break } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64SETBstore) + x := y.Args[1] + l := y.Args[0] + if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + break + } + mem := l.Args[1] + if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { + break + } + v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } - // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SETAstore [off1+off2] {sym} base val mem) + // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) + // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) + // result: (ANDLmodify [off] {sym} ptr x mem) for { - off1 := auxIntToInt32(v.AuxInt) + off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + ptr := v_0 + y := v_1 + if y.Op != OpAMD64ANDL { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + _ = y.Args[1] + y_0 := y.Args[0] + y_1 := y.Args[1] + for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { + l := y_0 + if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + continue + } + mem := l.Args[1] + if ptr != l.Args[0] { + continue + } + x := y_1 + if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { + continue + } + v.reset(OpAMD64ANDLmodify) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + break + } + // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) + // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) + // result: (ORLmodify [off] {sym} ptr x mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64ORL { break } - v.reset(OpAMD64SETAstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) - return true + _ = y.Args[1] + y_0 := y.Args[0] + y_1 := y.Args[1] + for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { + l := y_0 + if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + continue + } + mem := l.Args[1] + if ptr != l.Args[0] { + continue + } + x := y_1 + if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { + continue + } + v.reset(OpAMD64ORLmodify) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + break } - // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) + // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) + // result: (XORLmodify [off] {sym} ptr x mem) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64XORL { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + _ = y.Args[1] + y_0 := y.Args[0] + y_1 := y.Args[1] + for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { + l := y_0 + if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + continue + } + mem := l.Args[1] + if ptr != l.Args[0] { + continue + } + x := y_1 + if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { + continue + } + v.reset(OpAMD64XORLmodify) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + break + } + // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) + // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) + // result: (ADDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + a := v_1 + if a.Op != OpAMD64ADDLconst { break } - v.reset(OpAMD64SETAstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + c := auxIntToInt32(a.AuxInt) + l := a.Args[0] + if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + break + } + mem := l.Args[1] + ptr2 := l.Args[0] + if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + v.reset(OpAMD64ADDLconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) + // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) + // result: (ANDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagEQ { + a := v_1 + if a.Op != OpAMD64ANDLconst { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) + c := auxIntToInt32(a.AuxInt) + l := a.Args[0] + if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + break + } + mem := l.Args[1] + ptr2 := l.Args[0] + if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + v.reset(OpAMD64ANDLconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg2(ptr, mem) return true } - // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) + // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) + // result: (ORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagLT_ULT { + a := v_1 + if a.Op != OpAMD64ORLconst { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) + c := auxIntToInt32(a.AuxInt) + l := a.Args[0] + if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + break + } + mem := l.Args[1] + ptr2 := l.Args[0] + if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + v.reset(OpAMD64ORLconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg2(ptr, mem) return true } - // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) + // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) + // result: (XORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagLT_UGT { + a := v_1 + if a.Op != OpAMD64XORLconst { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) + c := auxIntToInt32(a.AuxInt) + l := a.Args[0] + if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + break + } + mem := l.Args[1] + ptr2 := l.Args[0] + if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + v.reset(OpAMD64XORLconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg2(ptr, mem) return true } - // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) + // result: (MOVSSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagGT_ULT { + if v_1.Op != OpAMD64MOVLf2i { break } + val := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVBstore) + v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, val, mem) return true } - // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVLstore [i] {s} p x:(BSWAPL w) mem) + // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 + // result: (MOVBELstore [i] {s} p w mem) + for { + i := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + p := v_0 + x := v_1 + if x.Op != OpAMD64BSWAPL { + break + } + w := x.Args[0] + mem := v_2 + if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64MOVBELstore) + v.AuxInt = int32ToAuxInt(i) + v.Aux = symToAux(s) + v.AddArg3(p, w, mem) + return true + } + // match: (MOVLstore [off] {sym} ptr (KMOVDi mask) mem) + // result: (KMOVDstore [off] {sym} ptr mask mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagGT_UGT { + if v_1.Op != OpAMD64KMOVDi { break } + mask := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVBstore) + v.reset(OpAMD64KMOVDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, mask, mem) return true } return false } -func rewriteValueAMD64_OpAMD64SETB(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (SETB (TESTQ x x)) - // result: (ConstBool [false]) + // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) + // cond: ValAndOff(sc).canAdd32(off) + // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { - if v_0.Op != OpAMD64TESTQ { + sc := auxIntToValAndOff(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - x := v_0.Args[1] - if x != v_0.Args[0] { + off := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(ValAndOff(sc).canAdd32(off)) { break } - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(false) + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) + v.Aux = symToAux(s) + v.AddArg2(ptr, mem) return true } - // match: (SETB (TESTL x x)) - // result: (ConstBool [false]) + // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) + // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) + // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { - if v_0.Op != OpAMD64TESTL { + sc := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - x := v_0.Args[1] - if x != v_0.Args[0] { + off := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + mem := v_1 + if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(false) + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(ptr, mem) return true } - // match: (SETB (TESTW x x)) - // result: (ConstBool [false]) + return false +} +func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVOload [off1+off2] {sym} ptr mem) for { - if v_0.Op != OpAMD64TESTW { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - x := v_0.Args[1] - if x != v_0.Args[0] { + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(false) + v.reset(OpAMD64MOVOload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SETB (TESTB x x)) - // result: (ConstBool [false]) + // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { - if v_0.Op != OpAMD64TESTB { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - x := v_0.Args[1] - if x != v_0.Args[0] { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(false) + v.reset(OpAMD64MOVOload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) return true } - // match: (SETB (BTLconst [0] x)) - // result: (ANDLconst [1] x) + return false +} +func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + typ := &b.Func.Config.Types + // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { - if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - x := v_0.Args[0] - v.reset(OpAMD64ANDLconst) - v.AuxInt = int32ToAuxInt(1) - v.AddArg(x) - return true - } - // match: (SETB (BTQconst [0] x)) - // result: (ANDQconst [1] x) - for { - if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { break } - x := v_0.Args[0] - v.reset(OpAMD64ANDQconst) - v.AuxInt = int32ToAuxInt(1) - v.AddArg(x) + v.reset(OpAMD64MOVOstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(ptr, val, mem) return true } - // match: (SETB c:(CMPQconst [128] x)) - // cond: c.Uses == 1 - // result: (SETBE (CMPQconst [127] x)) + // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - c := v_0 - if c.Op != OpAMD64CMPQconst || auxIntToInt32(c.AuxInt) != 128 { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - x := c.Args[0] - if !(c.Uses == 1) { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64MOVOstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (SETB c:(CMPLconst [128] x)) - // cond: c.Uses == 1 - // result: (SETBE (CMPLconst [127] x)) + // match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) + // cond: symIsRO(srcSym) + // result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem)) for { - c := v_0 - if c.Op != OpAMD64CMPLconst || auxIntToInt32(c.AuxInt) != 128 { - break - } - x := c.Args[0] - if !(c.Uses == 1) { + dstOff := auxIntToInt32(v.AuxInt) + dstSym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVOload { break } - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETB (InvertFlags x)) - // result: (SETA x) - for { - if v_0.Op != OpAMD64InvertFlags { + srcOff := auxIntToInt32(v_1.AuxInt) + srcSym := auxToSym(v_1.Aux) + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSB { break } - x := v_0.Args[0] - v.reset(OpAMD64SETA) - v.AddArg(x) - return true - } - // match: (SETB (FlagEQ)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagEQ { + mem := v_2 + if !(symIsRO(srcSym)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64MOVQstore) + v.AuxInt = int32ToAuxInt(dstOff + 8) + v.Aux = symToAux(dstSym) + v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))) + v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem) + v1.AuxInt = int32ToAuxInt(dstOff) + v1.Aux = symToAux(dstSym) + v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) + v2.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))) + v1.AddArg3(ptr, v2, mem) + v.AddArg3(ptr, v0, v1) return true } - // match: (SETB (FlagLT_ULT)) - // result: (MOVLconst [1]) + return false +} +func rewriteValueAMD64_OpAMD64MOVOstoreconst(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem) + // cond: ValAndOff(sc).canAdd32(off) + // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { - if v_0.Op != OpAMD64FlagLT_ULT { + sc := auxIntToValAndOff(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) - return true - } - // match: (SETB (FlagLT_UGT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagLT_UGT { + off := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(ValAndOff(sc).canAdd32(off)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64MOVOstoreconst) + v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) + v.Aux = symToAux(s) + v.AddArg2(ptr, mem) return true } - // match: (SETB (FlagGT_ULT)) - // result: (MOVLconst [1]) + // match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) + // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) + // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { - if v_0.Op != OpAMD64FlagGT_ULT { + sc := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) - return true - } - // match: (SETB (FlagGT_UGT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagGT_UGT { + off := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + mem := v_1 + if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64MOVOstoreconst) + v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(ptr, mem) return true } return false } -func rewriteValueAMD64_OpAMD64SETBE(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (SETBE (InvertFlags x)) - // result: (SETAE x) + // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { - if v_0.Op != OpAMD64InvertFlags { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - x := v_0.Args[0] - v.reset(OpAMD64SETAE) - v.AddArg(x) - return true - } - // match: (SETBE (FlagEQ)) - // result: (MOVLconst [1]) - for { - if v_0.Op != OpAMD64FlagEQ { + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + v.reset(OpAMD64MOVQatomicload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SETBE (FlagLT_ULT)) - // result: (MOVLconst [1]) + // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { - if v_0.Op != OpAMD64FlagLT_ULT { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) - return true - } - // match: (SETBE (FlagLT_UGT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagLT_UGT { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64MOVQatomicload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(ptr, mem) return true } - // match: (SETBE (FlagGT_ULT)) - // result: (MOVLconst [1]) + return false +} +func rewriteValueAMD64_OpAMD64MOVQf2i(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (MOVQf2i (Arg [off] {sym})) + // cond: t.Size() == u.Size() + // result: @b.Func.Entry (Arg [off] {sym}) for { - if v_0.Op != OpAMD64FlagGT_ULT { + t := v.Type + if v_0.Op != OpArg { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + u := v_0.Type + off := auxIntToInt32(v_0.AuxInt) + sym := auxToSym(v_0.Aux) + if !(t.Size() == u.Size()) { + break + } + b = b.Func.Entry + v0 := b.NewValue0(v.Pos, OpArg, t) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) return true } - // match: (SETBE (FlagGT_UGT)) - // result: (MOVLconst [0]) + return false +} +func rewriteValueAMD64_OpAMD64MOVQi2f(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (MOVQi2f (Arg [off] {sym})) + // cond: t.Size() == u.Size() + // result: @b.Func.Entry (Arg [off] {sym}) for { - if v_0.Op != OpAMD64FlagGT_UGT { + t := v.Type + if v_0.Op != OpArg { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + u := v_0.Type + off := auxIntToInt32(v_0.AuxInt) + sym := auxToSym(v_0.Aux) + if !(t.Size() == u.Size()) { + break + } + b = b.Func.Entry + v0 := b.NewValue0(v.Pos, OpArg, t) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) return true } return false } -func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { - v_2 := v.Args[2] +func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) - // result: (SETAEstore [off] {sym} ptr x mem) + config := b.Func.Config + // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: x for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64InvertFlags { + if v_1.Op != OpAMD64MOVQstore { break } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + x := v_1.Args[1] + ptr2 := v_1.Args[0] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + break + } + v.copyOf(x) return true } - // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) + // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SETBEstore [off1+off2] {sym} base val mem) + // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -17050,21 +27450,20 @@ func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { break } off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 + ptr := v_0.Args[0] + mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64SETBEstore) + v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.AddArg2(ptr, mem) return true } - // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -17074,157 +27473,98 @@ func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] - val := v_1 - mem := v_2 + mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SETBEstore) + v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) - return true - } - // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagEQ { - break - } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_ULT { - break - } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg2(base, mem) return true } - // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) + // result: (MOVQf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagLT_UGT { + if v_1.Op != OpAMD64MOVSDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_ULT { + val := v_1.Args[1] + if ptr != v_1.Args[0] { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64MOVQf2i) + v.AddArg(val) return true } - // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVQload [off] {sym} (SB) _) + // cond: symIsRO(sym) + // result: (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_UGT { + if v_0.Op != OpSB || !(symIsRO(sym)) { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } -func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) - // result: (SETAstore [off] {sym} ptr x mem) + // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { - off := auxIntToInt32(v.AuxInt) + off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64InvertFlags { + if v_0.Op != OpAMD64ADDQconst { break } - x := v_1.Args[0] + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + val := v_1 mem := v_2 - v.reset(OpAMD64SETAstore) - v.AuxInt = int32ToAuxInt(off) + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64MOVQstore) + v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.AddArg3(ptr, val, mem) return true } - // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SETBstore [off1+off2] {sym} base val mem) + // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) + // cond: validVal(c) + // result: (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { - off1 := auxIntToInt32(v.AuxInt) + off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + ptr := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 + c := auxIntToInt64(v_1.AuxInt) mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + if !(validVal(c)) { break } - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off1 + off2) + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.AddArg2(ptr, mem) return true } - // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -17239,1014 +27579,684 @@ func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SETBstore) + v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } - // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) + // cond: y.Uses==1 && clobber(y) + // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagEQ { + y := v_1 + if y.Op != OpAMD64ADDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) + mem := y.Args[2] + x := y.Args[0] + if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + break + } + v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) + // cond: y.Uses==1 && clobber(y) + // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagLT_ULT { + y := v_1 + if y.Op != OpAMD64ANDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) + mem := y.Args[2] + x := y.Args[0] + if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + break + } + v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) + // cond: y.Uses==1 && clobber(y) + // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagLT_UGT { + y := v_1 + if y.Op != OpAMD64ORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) + mem := y.Args[2] + x := y.Args[0] + if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + break + } + v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) + // cond: y.Uses==1 && clobber(y) + // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagGT_ULT { + y := v_1 + if y.Op != OpAMD64XORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) + mem := y.Args[2] + x := y.Args[0] + if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { + break + } + v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) + // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) + // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagGT_UGT { - break - } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64SETEQ(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) - // result: (SETAE (BTL x y)) - for { - if v_0.Op != OpAMD64TESTL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } - // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) - // result: (SETAE (BTQ x y)) - for { - if v_0.Op != OpAMD64TESTQ { + y := v_1 + if y.Op != OpAMD64ADDQ { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + _ = y.Args[1] + y_0 := y.Args[0] + y_1 := y.Args[1] + for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { + l := y_0 + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } - y := v_0_1 - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } - // match: (SETEQ (TESTLconst [c] x)) - // cond: isUnsignedPowerOfTwo(uint32(c)) - // result: (SETAE (BTLconst [int8(log32u(uint32(c)))] x)) - for { - if v_0.Op != OpAMD64TESTLconst { - break - } - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(isUnsignedPowerOfTwo(uint32(c))) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQconst [c] x)) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (SETAE (BTQconst [int8(log32u(uint32(c)))] x)) - for { - if v_0.Op != OpAMD64TESTQconst { - break - } - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(isUnsignedPowerOfTwo(uint64(c))) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ (MOVQconst [c]) x)) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (SETAE (BTQconst [int8(log64u(uint64(c)))] x)) - for { - if v_0.Op != OpAMD64TESTQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64MOVQconst { + mem := l.Args[1] + if ptr != l.Args[0] { continue } - c := auxIntToInt64(v_0_0.AuxInt) - x := v_0_1 - if !(isUnsignedPowerOfTwo(uint64(c))) { + x := y_1 + if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64ADDQmodify) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } break } - // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) - // result: (SETNE (CMPLconst [0] s)) + // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) + // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) + // result: (SUBQmodify [off] {sym} ptr x mem) for { - if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { - break - } - s := v_0.Args[0] - if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64SUBQ { break } - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(s) - v.AddArg(v0) - return true - } - // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) - // result: (SETNE (CMPQconst [0] s)) - for { - if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { + x := y.Args[1] + l := y.Args[0] + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } - s := v_0.Args[0] - if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { + mem := l.Args[1] + if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(s) - v.AddArg(v0) + v.reset(OpAMD64SUBQmodify) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) - // cond: z1==z2 - // result: (SETAE (BTQconst [63] x)) + // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) + // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) + // result: (ANDQmodify [off] {sym} ptr x mem) for { - if v_0.Op != OpAMD64TESTQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64ANDQ { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { + _ = y.Args[1] + y_0 := y.Args[0] + y_1 := y.Args[1] + for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { + l := y_0 + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + mem := l.Args[1] + if ptr != l.Args[0] { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + x := y_1 + if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64ANDQmodify) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } break } - // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) - // cond: z1==z2 - // result: (SETAE (BTQconst [31] x)) + // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) + // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) + // result: (ORQmodify [off] {sym} ptr x mem) for { - if v_0.Op != OpAMD64TESTL { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64ORQ { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { + _ = y.Args[1] + y_0 := y.Args[0] + y_1 := y.Args[1] + for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { + l := y_0 + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { + mem := l.Args[1] + if ptr != l.Args[0] { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + x := y_1 + if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64ORQmodify) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } break } - // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) - // cond: z1==z2 - // result: (SETAE (BTQconst [0] x)) + // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) + // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) + // result: (XORQmodify [off] {sym} ptr x mem) for { - if v_0.Op != OpAMD64TESTQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + y := v_1 + if y.Op != OpAMD64XORQ { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + _ = y.Args[1] + y_0 := y.Args[0] + y_1 := y.Args[1] + for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { + l := y_0 + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + mem := l.Args[1] + if ptr != l.Args[0] { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + x := y_1 + if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64XORQmodify) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } break } - // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) - // cond: z1==z2 - // result: (SETAE (BTLconst [0] x)) + // match: (MOVQstore {sym} [off] ptr x:(BTSQconst [c] l:(MOVQload {sym} [off] ptr mem)) mem) + // cond: x.Uses == 1 && l.Uses == 1 && clobber(x, l) + // result: (BTSQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { - if v_0.Op != OpAMD64TESTL { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + x := v_1 + if x.Op != OpAMD64BTSQconst { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { - continue - } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - v.AddArg(v0) - return true - } - break - } - // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) - // cond: z1==z2 - // result: (SETAE (BTQconst [63] x)) - for { - if v_0.Op != OpAMD64TESTQ { + c := auxIntToInt8(x.AuxInt) + l := x.Args[0] + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { - continue - } - x := z1.Args[0] - z2 := v_0_1 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - v.AddArg(v0) - return true + mem := l.Args[1] + if ptr != l.Args[0] || mem != v_2 || !(x.Uses == 1 && l.Uses == 1 && clobber(x, l)) { + break } - break + v.reset(OpAMD64BTSQconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true } - // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) - // cond: z1==z2 - // result: (SETAE (BTLconst [31] x)) + // match: (MOVQstore {sym} [off] ptr x:(BTRQconst [c] l:(MOVQload {sym} [off] ptr mem)) mem) + // cond: x.Uses == 1 && l.Uses == 1 && clobber(x, l) + // result: (BTRQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { - if v_0.Op != OpAMD64TESTL { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + x := v_1 + if x.Op != OpAMD64BTRQconst { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { - continue - } - x := z1.Args[0] - z2 := v_0_1 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - v.AddArg(v0) - return true + c := auxIntToInt8(x.AuxInt) + l := x.Args[0] + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + break } - break - } - // match: (SETEQ (InvertFlags x)) - // result: (SETEQ x) - for { - if v_0.Op != OpAMD64InvertFlags { + mem := l.Args[1] + if ptr != l.Args[0] || mem != v_2 || !(x.Uses == 1 && l.Uses == 1 && clobber(x, l)) { break } - x := v_0.Args[0] - v.reset(OpAMD64SETEQ) - v.AddArg(x) + v.reset(OpAMD64BTRQconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SETEQ (FlagEQ)) - // result: (MOVLconst [1]) + // match: (MOVQstore {sym} [off] ptr x:(BTCQconst [c] l:(MOVQload {sym} [off] ptr mem)) mem) + // cond: x.Uses == 1 && l.Uses == 1 && clobber(x, l) + // result: (BTCQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { - if v_0.Op != OpAMD64FlagEQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + x := v_1 + if x.Op != OpAMD64BTCQconst { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) - return true - } - // match: (SETEQ (FlagLT_ULT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagLT_ULT { + c := auxIntToInt8(x.AuxInt) + l := x.Args[0] + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } - // match: (SETEQ (FlagLT_UGT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagLT_UGT { + mem := l.Args[1] + if ptr != l.Args[0] || mem != v_2 || !(x.Uses == 1 && l.Uses == 1 && clobber(x, l)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64BTCQconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SETEQ (FlagGT_ULT)) - // result: (MOVLconst [0]) + // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) + // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) + // result: (ADDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { - if v_0.Op != OpAMD64FlagGT_ULT { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + a := v_1 + if a.Op != OpAMD64ADDQconst { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } - // match: (SETEQ (FlagGT_UGT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagGT_UGT { + c := auxIntToInt32(a.AuxInt) + l := a.Args[0] + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + mem := l.Args[1] + ptr2 := l.Args[0] + if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + v.reset(OpAMD64ADDQconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) return true } - // match: (SETEQ (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) - // result: (SETEQ (Select1 blsr)) + // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) + // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) + // result: (ANDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { - if v_0.Op != OpAMD64TESTQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + a := v_1 + if a.Op != OpAMD64ANDQconst { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - s := v_0_0 - if s.Op != OpSelect0 { - continue - } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { - continue - } - v.reset(OpAMD64SETEQ) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - v.AddArg(v0) - return true - } - break - } - // match: (SETEQ (TESTL s:(Select0 blsr:(BLSRL _)) s)) - // result: (SETEQ (Select1 blsr)) - for { - if v_0.Op != OpAMD64TESTL { + c := auxIntToInt32(a.AuxInt) + l := a.Args[0] + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - s := v_0_0 - if s.Op != OpSelect0 { - continue - } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRL || s != v_0_1 { - continue - } - v.reset(OpAMD64SETEQ) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - v.AddArg(v0) - return true + mem := l.Args[1] + ptr2 := l.Args[0] + if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break } - break + v.reset(OpAMD64ANDQconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true } - return false -} -func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) - // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) + // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) + // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) + // result: (ORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64TESTL { + a := v_1 + if a.Op != OpAMD64ORQconst { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLL { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true + c := auxIntToInt32(a.AuxInt) + l := a.Args[0] + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + break } - break + mem := l.Args[1] + ptr2 := l.Args[0] + if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + v.reset(OpAMD64ORQconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true } - // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) - // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) + // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) + // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) + // result: (XORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64TESTQ { + a := v_1 + if a.Op != OpAMD64XORQconst { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLQ { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true + c := auxIntToInt32(a.AuxInt) + l := a.Args[0] + if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { + break } - break + mem := l.Args[1] + ptr2 := l.Args[0] + if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { + break + } + v.reset(OpAMD64XORQconstmodify) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true } - // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) - // cond: isUnsignedPowerOfTwo(uint32(c)) - // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32u(uint32(c)))] x) mem) + // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) + // result: (MOVSDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64TESTLconst { + if v_1.Op != OpAMD64MOVQf2i { break } - c := auxIntToInt32(v_1.AuxInt) - x := v_1.Args[0] + val := v_1.Args[0] mem := v_2 - if !(isUnsignedPowerOfTwo(uint32(c))) { - break - } - v.reset(OpAMD64SETAEstore) + v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, val, mem) return true } - // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log32u(uint32(c)))] x) mem) + // match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem) + // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 + // result: (MOVBEQstore [i] {s} p w mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQconst { + i := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + p := v_0 + x := v_1 + if x.Op != OpAMD64BSWAPQ { break } - c := auxIntToInt32(v_1.AuxInt) - x := v_1.Args[0] + w := x.Args[0] mem := v_2 - if !(isUnsignedPowerOfTwo(uint64(c))) { + if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64MOVBEQstore) + v.AuxInt = int32ToAuxInt(i) + v.Aux = symToAux(s) + v.AddArg3(p, w, mem) return true } - // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log64u(uint64(c)))] x) mem) + // match: (MOVQstore [off] {sym} ptr (KMOVQi mask) mem) + // result: (KMOVQstore [off] {sym} ptr mask mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64TESTQ { + if v_1.Op != OpAMD64KMOVQi { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64MOVQconst { - continue - } - c := auxIntToInt64(v_1_0.AuxInt) - x := v_1_1 - mem := v_2 - if !(isUnsignedPowerOfTwo(uint64(c))) { - continue - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) - return true - } - break + mask := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64KMOVQstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true } - // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) - // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) + return false +} +func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) + // cond: ValAndOff(sc).canAdd32(off) + // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { + sc := auxIntToValAndOff(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - s := v_1.Args[0] - if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { + off := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(ValAndOff(sc).canAdd32(off)) { break } - mem := v_2 - v.reset(OpAMD64SETNEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(s) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) + v.Aux = symToAux(s) + v.AddArg2(ptr, mem) return true } - // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) - // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) + // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) + // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) + // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { + sc := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - s := v_1.Args[0] - if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { + off := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + mem := v_1 + if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } - mem := v_2 - v.reset(OpAMD64SETNEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(s) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(ptr, mem) return true } - // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) + // match: (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem)) + // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && setPos(v, x.Pos) && clobber(x) + // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { + c := auxIntToValAndOff(v.AuxInt) + s := auxToSym(v.Aux) + p1 := v_0 + x := v_1 + if x.Op != OpAMD64MOVQstoreconst { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { - continue - } - x := z1_0.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) - return true + a := auxIntToValAndOff(x.AuxInt) + if auxToSym(x.Aux) != s { + break } - break + mem := x.Args[1] + p0 := x.Args[0] + if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && setPos(v, x.Pos) && clobber(x)) { + break + } + v.reset(OpAMD64MOVOstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) + v.Aux = symToAux(s) + v.AddArg2(p0, mem) + return true } - // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) + // match: (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem)) + // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && setPos(v, x.Pos) && clobber(x) + // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { + a := auxIntToValAndOff(v.AuxInt) + s := auxToSym(v.Aux) + p0 := v_0 + x := v_1 + if x.Op != OpAMD64MOVQstoreconst { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { - continue - } - x := z1_0.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) - return true + c := auxIntToValAndOff(x.AuxInt) + if auxToSym(x.Aux) != s { + break } - break + mem := x.Args[1] + p1 := x.Args[0] + if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && setPos(v, x.Pos) && clobber(x)) { + break + } + v.reset(OpAMD64MOVOstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) + v.Aux = symToAux(s) + v.AddArg2(p0, mem) + return true } - // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) + return false +} +func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVSDload [off1+off2] {sym} ptr mem) for { - off := auxIntToInt32(v.AuxInt) + off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { + if v_0.Op != OpAMD64ADDQconst { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { - continue - } - x := z1_0.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) - return true + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { + break } - break + v.reset(OpAMD64MOVSDload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true } - // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) + // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { - continue - } - x := z1_0.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) - return true + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break } - break + v.reset(OpAMD64MOVSDload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) + return true } - // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) + // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) + // result: (MOVQi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64TESTQ { + if v_1.Op != OpAMD64MOVQstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { - continue - } - x := z1.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) - return true - } - break - } - // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { - continue - } - x := z1.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) - return true - } - break - } - // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) - // result: (SETEQstore [off] {sym} ptr x mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64InvertFlags { + val := v_1.Args[1] + if ptr != v_1.Args[0] { break } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64SETEQstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + v.reset(OpAMD64MOVQi2f) + v.AddArg(val) return true } - // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) + return false +} +func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SETEQstore [off1+off2] {sym} base val mem) + // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -18254,21 +28264,21 @@ func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { break } off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] + ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64SETEQstore) + v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.AddArg3(ptr, val, mem) return true } - // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -18283,321 +28293,354 @@ func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SETEQstore) + v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } - // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) + // result: (MOVQstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagEQ { + if v_1.Op != OpAMD64MOVQi2f { break } + val := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVBstore) + v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, val, mem) return true } - // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVSDstore [off] {sym} ptr (MOVSDconst [f]) mem) + // cond: f == f + // result: (MOVQstore [off] {sym} ptr (MOVQconst [int64(math.Float64bits(f))]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagLT_ULT { + if v_1.Op != OpAMD64MOVSDconst { break } + f := auxIntToFloat64(v_1.AuxInt) mem := v_2 - v.reset(OpAMD64MOVBstore) + if !(f == f) { + break + } + v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(int64(math.Float64bits(f))) v.AddArg3(ptr, v0, mem) return true } - // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + return false +} +func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVSSload [off1+off2] {sym} ptr mem) for { - off := auxIntToInt32(v.AuxInt) + off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_UGT { + if v_0.Op != OpAMD64ADDQconst { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64MOVSSload) + v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg2(ptr, mem) return true } - // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_ULT { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVSSload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) return true } - // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) + // result: (MOVLi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagGT_UGT { + if v_1.Op != OpAMD64MOVLstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + val := v_1.Args[1] + if ptr != v_1.Args[0] { + break + } + v.reset(OpAMD64MOVLi2f) + v.AddArg(val) return true } return false } -func rewriteValueAMD64_OpAMD64SETG(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (SETG (InvertFlags x)) - // result: (SETL x) + b := v.Block + typ := &b.Func.Config.Types + // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { - if v_0.Op != OpAMD64InvertFlags { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - x := v_0.Args[0] - v.reset(OpAMD64SETL) - v.AddArg(x) - return true - } - // match: (SETG (FlagEQ)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagEQ { + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64MOVSSstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(ptr, val, mem) return true } - // match: (SETG (FlagLT_ULT)) - // result: (MOVLconst [0]) + // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - if v_0.Op != OpAMD64FlagLT_ULT { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } - // match: (SETG (FlagLT_UGT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagLT_UGT { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64MOVSSstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (SETG (FlagGT_ULT)) - // result: (MOVLconst [1]) + // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) + // result: (MOVLstore [off] {sym} ptr val mem) for { - if v_0.Op != OpAMD64FlagGT_ULT { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVLi2f { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + val := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64MOVLstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, val, mem) return true } - // match: (SETG (FlagGT_UGT)) - // result: (MOVLconst [1]) + // match: (MOVSSstore [off] {sym} ptr (MOVSSconst [f]) mem) + // cond: f == f + // result: (MOVLstore [off] {sym} ptr (MOVLconst [int32(math.Float32bits(f))]) mem) for { - if v_0.Op != OpAMD64FlagGT_UGT { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVSSconst { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + f := auxIntToFloat32(v_1.AuxInt) + mem := v_2 + if !(f == f) { + break + } + v.reset(OpAMD64MOVLstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt32) + v0.AuxInt = int32ToAuxInt(int32(math.Float32bits(f))) + v.AddArg3(ptr, v0, mem) return true } return false } -func rewriteValueAMD64_OpAMD64SETGE(v *Value) bool { +func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block - // match: (SETGE c:(CMPQconst [128] x)) - // cond: c.Uses == 1 - // result: (SETG (CMPQconst [127] x)) + // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { - c := v_0 - if c.Op != OpAMD64CMPQconst || auxIntToInt32(c.AuxInt) != 128 { + x := v_0 + if x.Op != OpAMD64MOVWload { break } - x := c.Args[0] - if !(c.Uses == 1) { + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { break } - v.reset(OpAMD64SETG) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(x) - v.AddArg(v0) + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (SETGE c:(CMPLconst [128] x)) - // cond: c.Uses == 1 - // result: (SETG (CMPLconst [127] x)) + // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { - c := v_0 - if c.Op != OpAMD64CMPLconst || auxIntToInt32(c.AuxInt) != 128 { + x := v_0 + if x.Op != OpAMD64MOVLload { break } - x := c.Args[0] - if !(c.Uses == 1) { + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { break } - v.reset(OpAMD64SETG) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(x) - v.AddArg(v0) + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (SETGE (InvertFlags x)) - // result: (SETLE x) + // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { - if v_0.Op != OpAMD64InvertFlags { + x := v_0 + if x.Op != OpAMD64MOVQload { break } - x := v_0.Args[0] - v.reset(OpAMD64SETLE) - v.AddArg(x) - return true - } - // match: (SETGE (FlagEQ)) - // result: (MOVLconst [1]) - for { - if v_0.Op != OpAMD64FlagEQ { + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (SETGE (FlagLT_ULT)) - // result: (MOVLconst [0]) + // match: (MOVWQSX (ANDLconst [c] x)) + // cond: c & 0x8000 == 0 + // result: (ANDLconst [c & 0x7fff] x) for { - if v_0.Op != OpAMD64FlagLT_ULT { + if v_0.Op != OpAMD64ANDLconst { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } - // match: (SETGE (FlagLT_UGT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagLT_UGT { + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(c&0x8000 == 0) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64ANDLconst) + v.AuxInt = int32ToAuxInt(c & 0x7fff) + v.AddArg(x) return true } - // match: (SETGE (FlagGT_ULT)) - // result: (MOVLconst [1]) + // match: (MOVWQSX (MOVWQSX x)) + // result: (MOVWQSX x) for { - if v_0.Op != OpAMD64FlagGT_ULT { + if v_0.Op != OpAMD64MOVWQSX { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + x := v_0.Args[0] + v.reset(OpAMD64MOVWQSX) + v.AddArg(x) return true } - // match: (SETGE (FlagGT_UGT)) - // result: (MOVLconst [1]) + // match: (MOVWQSX (MOVBQSX x)) + // result: (MOVBQSX x) for { - if v_0.Op != OpAMD64FlagGT_UGT { + if v_0.Op != OpAMD64MOVBQSX { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + x := v_0.Args[0] + v.reset(OpAMD64MOVBQSX) + v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { - v_2 := v.Args[2] +func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) - // result: (SETLEstore [off] {sym} ptr x mem) + config := b.Func.Config + // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: (MOVWQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64InvertFlags { - break - } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64SETLEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SETGEstore [off1+off2] {sym} base val mem) - for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + if v_1.Op != OpAMD64MOVWstore { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + x := v_1.Args[1] + ptr2 := v_1.Args[0] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } - v.reset(OpAMD64SETGEstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.reset(OpAMD64MOVWQSX) + v.AddArg(x) return true } - // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -18607,135 +28650,169 @@ func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] - val := v_1 - mem := v_2 + mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SETGEstore) + v.reset(OpAMD64MOVWQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + v.AddArg2(base, mem) return true } - // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVWQSXload [off] {sym} (SB) _) + // cond: symIsRO(sym) + // result: (MOVQconst [int64(int16(read16(sym, int64(off), config.ctxt.Arch.ByteOrder)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagEQ { + if v_0.Op != OpSB || !(symIsRO(sym)) { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(int16(read16(sym, int64(off), config.ctxt.Arch.ByteOrder)))) return true } - // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + return false +} +func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVWload [off] {sym} ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_ULT { + x := v_0 + if x.Op != OpAMD64MOVWload { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVWload [off] {sym} ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_UGT { + x := v_0 + if x.Op != OpAMD64MOVLload { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (MOVWload [off] {sym} ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_ULT { + x := v_0 + if x.Op != OpAMD64MOVQload { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVWQZX (ANDLconst [c] x)) + // result: (ANDLconst [c & 0xffff] x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_UGT { + if v_0.Op != OpAMD64ANDLconst { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + v.reset(OpAMD64ANDLconst) + v.AuxInt = int32ToAuxInt(c & 0xffff) + v.AddArg(x) + return true + } + // match: (MOVWQZX (MOVWQZX x)) + // result: (MOVWQZX x) + for { + if v_0.Op != OpAMD64MOVWQZX { + break + } + x := v_0.Args[0] + v.reset(OpAMD64MOVWQZX) + v.AddArg(x) + return true + } + // match: (MOVWQZX (MOVBQZX x)) + // result: (MOVBQZX x) + for { + if v_0.Op != OpAMD64MOVBQZX { + break + } + x := v_0.Args[0] + v.reset(OpAMD64MOVBQZX) + v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { - v_2 := v.Args[2] +func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) - // result: (SETLstore [off] {sym} ptr x mem) + config := b.Func.Config + // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: (MOVWQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64InvertFlags { + if v_1.Op != OpAMD64MOVWstore { break } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64SETLstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + x := v_1.Args[1] + ptr2 := v_1.Args[0] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + break + } + v.reset(OpAMD64MOVWQZX) + v.AddArg(x) return true } - // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) + // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SETGstore [off1+off2] {sym} base val mem) + // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -18743,21 +28820,20 @@ func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { break } off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 + ptr := v_0.Args[0] + mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64SETGstore) + v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.AddArg2(ptr, mem) return true } - // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -18767,1887 +28843,1552 @@ func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] - val := v_1 - mem := v_2 + mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SETGstore) + v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + v.AddArg2(base, mem) return true } - // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVWload [off] {sym} (SB) _) + // cond: symIsRO(sym) + // result: (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpSB || !(symIsRO(sym)) { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) + // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagEQ { + if v_1.Op != OpAMD64MOVWQSX { break } + x := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVBstore) + v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) + // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagLT_ULT { + if v_1.Op != OpAMD64MOVWQZX { break } + x := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVBstore) + v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, x, mem) return true } - // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { - off := auxIntToInt32(v.AuxInt) + off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_UGT { + if v_0.Op != OpAMD64ADDQconst { break } + off2 := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + val := v_1 mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64MOVWstore) + v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg3(ptr, val, mem) return true } - // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) + // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagGT_ULT { + if v_1.Op != OpAMD64MOVLconst { break } + c := auxIntToInt32(v_1.AuxInt) mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg2(ptr, mem) return true } - // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) + // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 - if v_1.Op != OpAMD64FlagGT_UGT { + if v_1.Op != OpAMD64MOVQconst { break } + c := auxIntToInt64(v_1.AuxInt) mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg2(ptr, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SETL(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (SETL c:(CMPQconst [128] x)) - // cond: c.Uses == 1 - // result: (SETLE (CMPQconst [127] x)) + // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - c := v_0 - if c.Op != OpAMD64CMPQconst || auxIntToInt32(c.AuxInt) != 128 { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - x := c.Args[0] - if !(c.Uses == 1) { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SETLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64MOVWstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (SETL c:(CMPLconst [128] x)) - // cond: c.Uses == 1 - // result: (SETLE (CMPLconst [127] x)) + // match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) + // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 + // result: (MOVBEWstore [i] {s} p w mem) for { - c := v_0 - if c.Op != OpAMD64CMPLconst || auxIntToInt32(c.AuxInt) != 128 { + i := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + p := v_0 + x := v_1 + if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } - x := c.Args[0] - if !(c.Uses == 1) { + w := x.Args[0] + mem := v_2 + if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } - v.reset(OpAMD64SETLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64MOVBEWstore) + v.AuxInt = int32ToAuxInt(i) + v.Aux = symToAux(s) + v.AddArg3(p, w, mem) return true } - // match: (SETL (InvertFlags x)) - // result: (SETG x) + // match: (MOVWstore [off] {sym} ptr (KMOVWi mask) mem) + // result: (KMOVWstore [off] {sym} ptr mask mem) for { - if v_0.Op != OpAMD64InvertFlags { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64KMOVWi { break } - x := v_0.Args[0] - v.reset(OpAMD64SETG) - v.AddArg(x) + mask := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64KMOVWstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) return true } - // match: (SETL (FlagEQ)) - // result: (MOVLconst [0]) + return false +} +func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) + // cond: ValAndOff(sc).canAdd32(off) + // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { - if v_0.Op != OpAMD64FlagEQ { + sc := auxIntToValAndOff(v.AuxInt) + s := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } - // match: (SETL (FlagLT_ULT)) - // result: (MOVLconst [1]) - for { - if v_0.Op != OpAMD64FlagLT_ULT { + off := auxIntToInt32(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(ValAndOff(sc).canAdd32(off)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) + v.Aux = symToAux(s) + v.AddArg2(ptr, mem) return true } - // match: (SETL (FlagLT_UGT)) - // result: (MOVLconst [1]) + // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) + // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) + // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { - if v_0.Op != OpAMD64FlagLT_UGT { + sc := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) - return true - } - // match: (SETL (FlagGT_ULT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagGT_ULT { + off := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + mem := v_1 + if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(ptr, mem) return true } - // match: (SETL (FlagGT_UGT)) - // result: (MOVLconst [0]) + return false +} +func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MULL x (MOVLconst [c])) + // result: (MULLconst [c] x) for { - if v_0.Op != OpAMD64FlagGT_UGT { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64MULLconst) + v.AuxInt = int32ToAuxInt(c) + v.AddArg(x) + return true } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true + break } return false } -func rewriteValueAMD64_OpAMD64SETLE(v *Value) bool { +func rewriteValueAMD64_OpAMD64MULLconst(v *Value) bool { v_0 := v.Args[0] - // match: (SETLE (InvertFlags x)) - // result: (SETGE x) + b := v.Block + config := b.Func.Config + // match: (MULLconst [c] (MULLconst [d] x)) + // result: (MULLconst [c * d] x) for { - if v_0.Op != OpAMD64InvertFlags { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MULLconst { break } + d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] - v.reset(OpAMD64SETGE) + v.reset(OpAMD64MULLconst) + v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } - // match: (SETLE (FlagEQ)) - // result: (MOVLconst [1]) + // match: (MULLconst [ 0] _) + // result: (MOVLconst [0]) for { - if v_0.Op != OpAMD64FlagEQ { + if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (SETLE (FlagLT_ULT)) - // result: (MOVLconst [1]) + // match: (MULLconst [ 1] x) + // result: x for { - if v_0.Op != OpAMD64FlagLT_ULT { + if auxIntToInt32(v.AuxInt) != 1 { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + x := v_0 + v.copyOf(x) return true } - // match: (SETLE (FlagLT_UGT)) - // result: (MOVLconst [1]) + // match: (MULLconst [c] x) + // cond: v.Type.Size() <= 4 && canMulStrengthReduce32(config, c) + // result: {mulStrengthReduce32(v, x, c)} for { - if v_0.Op != OpAMD64FlagLT_UGT { + c := auxIntToInt32(v.AuxInt) + x := v_0 + if !(v.Type.Size() <= 4 && canMulStrengthReduce32(config, c)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + v.copyOf(mulStrengthReduce32(v, x, c)) return true } - // match: (SETLE (FlagGT_ULT)) - // result: (MOVLconst [0]) + // match: (MULLconst [c] (MOVLconst [d])) + // result: (MOVLconst [c*d]) for { - if v_0.Op != OpAMD64FlagGT_ULT { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } + d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.AuxInt = int32ToAuxInt(c * d) return true } - // match: (SETLE (FlagGT_UGT)) - // result: (MOVLconst [0]) - for { - if v_0.Op != OpAMD64FlagGT_UGT { - break + return false +} +func rewriteValueAMD64_OpAMD64MULQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MULQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (MULQconst [int32(c)] x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := auxIntToInt64(v_1.AuxInt) + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64MULQconst) + v.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg(x) + return true } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true + break } return false } -func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64MULQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) - // result: (SETGEstore [off] {sym} ptr x mem) + config := b.Func.Config + // match: (MULQconst [c] (MULQconst [d] x)) + // cond: is32Bit(int64(c)*int64(d)) + // result: (MULQconst [c * d] x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64InvertFlags { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MULQconst { break } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64SETGEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(is32Bit(int64(c) * int64(d))) { + break + } + v.reset(OpAMD64MULQconst) + v.AuxInt = int32ToAuxInt(c * d) + v.AddArg(x) return true } - // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SETLEstore [off1+off2] {sym} base val mem) + // match: (MULQconst [ 0] _) + // result: (MOVQconst [0]) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { - break - } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + if auxIntToInt32(v.AuxInt) != 0 { break } - v.reset(OpAMD64SETLEstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(0) return true } - // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (MULQconst [ 1] x) + // result: x for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + if auxIntToInt32(v.AuxInt) != 1 { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + x := v_0 + v.copyOf(x) + return true + } + // match: (MULQconst [c] x) + // cond: canMulStrengthReduce(config, int64(c)) + // result: {mulStrengthReduce(v, x, int64(c))} + for { + c := auxIntToInt32(v.AuxInt) + x := v_0 + if !(canMulStrengthReduce(config, int64(c))) { break } - v.reset(OpAMD64SETLEstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + v.copyOf(mulStrengthReduce(v, x, int64(c))) return true } - // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MULQconst [c] (MOVQconst [d])) + // result: (MOVQconst [int64(c)*d]) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagEQ { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + d := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(c) * d) return true } - // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (MULQconst [c] (NEGQ x)) + // cond: c != -(1<<31) + // result: (MULQconst [-c] x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_ULT { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64NEGQ { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + x := v_0.Args[0] + if !(c != -(1 << 31)) { + break + } + v.reset(OpAMD64MULQconst) + v.AuxInt = int32ToAuxInt(-c) + v.AddArg(x) return true } - // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + return false +} +func rewriteValueAMD64_OpAMD64MULSD(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (MULSDload x [off] {sym} ptr mem) for { - off := auxIntToInt32(v.AuxInt) + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVSDload { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64MULSDload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (MULSDload [off1+off2] {sym} val base mem) + for { + off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_UGT { + val := v_0 + if v_1.Op != OpAMD64ADDQconst { break } + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64MULSDload) + v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg3(val, base, mem) return true } - // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_ULT { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { break } + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MULSDload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, base, mem) return true } - // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) + // result: (MULSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_UGT { + x := v_0 + ptr := v_1 + if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + y := v_2.Args[1] + if ptr != v_2.Args[0] { + break + } + v.reset(OpAMD64MULSD) + v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) + v0.AddArg(y) + v.AddArg2(x, v0) return true } return false } -func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { - v_2 := v.Args[2] +func rewriteValueAMD64_OpAMD64MULSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) - // result: (SETGstore [off] {sym} ptr x mem) + // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (MULSSload x [off] {sym} ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64InvertFlags { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVSSload { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64MULSSload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64SETGstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true + break } - // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) + return false +} +func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SETLstore [off1+off2] {sym} base val mem) + // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + val := v_0 + if v_1.Op != OpAMD64ADDQconst { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64SETLstore) + v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.AddArg3(val, base, mem) return true } - // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + val := v_0 + if v_1.Op != OpAMD64LEAQ { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SETLstore) + v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + v.AddArg3(val, base, mem) return true } - // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) + // result: (MULSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagEQ { + x := v_0 + ptr := v_1 + if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_ULT { + y := v_2.Args[1] + if ptr != v_2.Args[0] { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64MULSS) + v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + return false +} +func rewriteValueAMD64_OpAMD64NEGL(v *Value) bool { + v_0 := v.Args[0] + // match: (NEGL (NEGL x)) + // result: x for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_UGT { + if v_0.Op != OpAMD64NEGL { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + x := v_0.Args[0] + v.copyOf(x) return true } - // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (NEGL s:(SUBL x y)) + // cond: s.Uses == 1 + // result: (SUBL y x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_ULT { + s := v_0 + if s.Op != OpAMD64SUBL { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + y := s.Args[1] + x := s.Args[0] + if !(s.Uses == 1) { + break + } + v.reset(OpAMD64SUBL) + v.AddArg2(y, x) return true } - // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + // match: (NEGL (MOVLconst [c])) + // result: (MOVLconst [-c]) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_UGT { + if v_0.Op != OpAMD64MOVLconst { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + c := auxIntToInt32(v_0.AuxInt) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(-c) return true } return false } -func rewriteValueAMD64_OpAMD64SETNE(v *Value) bool { +func rewriteValueAMD64_OpAMD64NEGQ(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (SETNE (TESTBconst [1] x)) - // result: (ANDLconst [1] x) + // match: (NEGQ (NEGQ x)) + // result: x for { - if v_0.Op != OpAMD64TESTBconst || auxIntToInt8(v_0.AuxInt) != 1 { + if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] - v.reset(OpAMD64ANDLconst) - v.AuxInt = int32ToAuxInt(1) - v.AddArg(x) + v.copyOf(x) return true } - // match: (SETNE (TESTWconst [1] x)) - // result: (ANDLconst [1] x) + // match: (NEGQ s:(SUBQ x y)) + // cond: s.Uses == 1 + // result: (SUBQ y x) for { - if v_0.Op != OpAMD64TESTWconst || auxIntToInt16(v_0.AuxInt) != 1 { + s := v_0 + if s.Op != OpAMD64SUBQ { break } - x := v_0.Args[0] - v.reset(OpAMD64ANDLconst) - v.AuxInt = int32ToAuxInt(1) - v.AddArg(x) + y := s.Args[1] + x := s.Args[0] + if !(s.Uses == 1) { + break + } + v.reset(OpAMD64SUBQ) + v.AddArg2(y, x) return true } - // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) - // result: (SETB (BTL x y)) + // match: (NEGQ (MOVQconst [c])) + // result: (MOVQconst [-c]) for { - if v_0.Op != OpAMD64TESTL { + if v_0.Op != OpAMD64MOVQconst { break } - _ = v_0.Args[1] + c := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(-c) + return true + } + // match: (NEGQ (ADDQconst [c] (NEGQ x))) + // cond: c != -(1<<31) + // result: (ADDQconst [-c] x) + for { + if v_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_0.AuxInt) v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } - // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) - // result: (SETB (BTQ x y)) - for { - if v_0.Op != OpAMD64TESTQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } - // match: (SETNE (TESTLconst [c] x)) - // cond: isUnsignedPowerOfTwo(uint32(c)) - // result: (SETB (BTLconst [int8(log32u(uint32(c)))] x)) - for { - if v_0.Op != OpAMD64TESTLconst { + if v_0_0.Op != OpAMD64NEGQ { break } - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(isUnsignedPowerOfTwo(uint32(c))) { + x := v_0_0.Args[0] + if !(c != -(1 << 31)) { break } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64ADDQconst) + v.AuxInt = int32ToAuxInt(-c) + v.AddArg(x) return true } - // match: (SETNE (TESTQconst [c] x)) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (SETB (BTQconst [int8(log32u(uint32(c)))] x)) + return false +} +func rewriteValueAMD64_OpAMD64NOTL(v *Value) bool { + v_0 := v.Args[0] + // match: (NOTL (MOVLconst [c])) + // result: (MOVLconst [^c]) for { - if v_0.Op != OpAMD64TESTQconst { + if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(isUnsignedPowerOfTwo(uint64(c))) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ (MOVQconst [c]) x)) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (SETB (BTQconst [int8(log64u(uint64(c)))] x)) - for { - if v_0.Op != OpAMD64TESTQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64MOVQconst { - continue - } - c := auxIntToInt64(v_0_0.AuxInt) - x := v_0_1 - if !(isUnsignedPowerOfTwo(uint64(c))) { - continue - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) - v0.AddArg(x) - v.AddArg(v0) - return true - } - break - } - // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) - // result: (SETEQ (CMPLconst [0] s)) - for { - if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { - break - } - s := v_0.Args[0] - if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { - break - } - v.reset(OpAMD64SETEQ) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(s) - v.AddArg(v0) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(^c) return true } - // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) - // result: (SETEQ (CMPQconst [0] s)) + return false +} +func rewriteValueAMD64_OpAMD64NOTQ(v *Value) bool { + v_0 := v.Args[0] + // match: (NOTQ (MOVQconst [c])) + // result: (MOVQconst [^c]) for { - if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { - break - } - s := v_0.Args[0] - if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { + if v_0.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64SETEQ) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(s) - v.AddArg(v0) + c := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(^c) return true } - // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) - // cond: z1==z2 - // result: (SETB (BTQconst [63] x)) - for { - if v_0.Op != OpAMD64TESTQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { - continue - } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - v.AddArg(v0) - return true - } - break - } - // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) - // cond: z1==z2 - // result: (SETB (BTQconst [31] x)) - for { - if v_0.Op != OpAMD64TESTL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { - continue - } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - v.AddArg(v0) - return true - } - break - } - // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) - // cond: z1==z2 - // result: (SETB (BTQconst [0] x)) + return false +} +func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ORL (SHLL (MOVLconst [1]) y) x) + // result: (BTSL x y) for { - if v_0.Op != OpAMD64TESTQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLL { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - v.AddArg(v0) + x := v_1 + v.reset(OpAMD64BTSL) + v.AddArg2(x, y) return true } break } - // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) - // cond: z1==z2 - // result: (SETB (BTLconst [0] x)) + // match: (ORL x (MOVLconst [c])) + // result: (ORLconst [c] x) for { - if v_0.Op != OpAMD64TESTL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { - continue - } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { continue } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - v.AddArg(v0) + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64ORLconst) + v.AuxInt = int32ToAuxInt(c) + v.AddArg(x) return true } break } - // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) - // cond: z1==z2 - // result: (SETB (BTQconst [63] x)) + // match: (ORL x x) + // result: x for { - if v_0.Op != OpAMD64TESTQ { + x := v_0 + if x != v_1 { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { - continue - } - x := z1.Args[0] - z2 := v_0_1 - if !(z1 == z2) { - continue - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - v.AddArg(v0) - return true - } - break + v.copyOf(x) + return true } - // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) - // cond: z1==z2 - // result: (SETB (BTLconst [31] x)) + // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (ORLload x [off] {sym} ptr mem) for { - if v_0.Op != OpAMD64TESTL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVLload { continue } - x := z1.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64ORLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) return true } break } - // match: (SETNE (InvertFlags x)) - // result: (SETNE x) + return false +} +func rewriteValueAMD64_OpAMD64ORLconst(v *Value) bool { + v_0 := v.Args[0] + // match: (ORLconst [c] (ORLconst [d] x)) + // result: (ORLconst [c | d] x) for { - if v_0.Op != OpAMD64InvertFlags { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64ORLconst { break } + d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] - v.reset(OpAMD64SETNE) + v.reset(OpAMD64ORLconst) + v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } - // match: (SETNE (FlagEQ)) - // result: (MOVLconst [0]) + // match: (ORLconst [0] x) + // result: x for { - if v_0.Op != OpAMD64FlagEQ { + if auxIntToInt32(v.AuxInt) != 0 { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + x := v_0 + v.copyOf(x) return true } - // match: (SETNE (FlagLT_ULT)) - // result: (MOVLconst [1]) + // match: (ORLconst [-1] _) + // result: (MOVLconst [-1]) for { - if v_0.Op != OpAMD64FlagLT_ULT { + if auxIntToInt32(v.AuxInt) != -1 { break } v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + v.AuxInt = int32ToAuxInt(-1) return true } - // match: (SETNE (FlagLT_UGT)) - // result: (MOVLconst [1]) + // match: (ORLconst [c] (MOVLconst [d])) + // result: (MOVLconst [c|d]) for { - if v_0.Op != OpAMD64FlagLT_UGT { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } + d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + v.AuxInt = int32ToAuxInt(c | d) return true } - // match: (SETNE (FlagGT_ULT)) - // result: (MOVLconst [1]) + return false +} +func rewriteValueAMD64_OpAMD64ORLconstmodify(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ORLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) + // result: (ORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { - if v_0.Op != OpAMD64FlagGT_ULT { + valoff1 := auxIntToValAndOff(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) - return true - } - // match: (SETNE (FlagGT_UGT)) - // result: (MOVLconst [1]) - for { - if v_0.Op != OpAMD64FlagGT_UGT { + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2)) { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(1) + v.reset(OpAMD64ORLconstmodify) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(sym) + v.AddArg2(base, mem) return true } - // match: (SETNE (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) - // result: (SETNE (Select1 blsr)) + // match: (ORLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) + // result: (ORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { - if v_0.Op != OpAMD64TESTQ { + valoff1 := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - s := v_0_0 - if s.Op != OpSelect0 { - continue - } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { - continue - } - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - v.AddArg(v0) - return true - } - break - } - // match: (SETNE (TESTL s:(Select0 blsr:(BLSRL _)) s)) - // result: (SETNE (Select1 blsr)) - for { - if v_0.Op != OpAMD64TESTL { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - s := v_0_0 - if s.Op != OpSelect0 { - continue - } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRL || s != v_0_1 { - continue - } - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - v.AddArg(v0) - return true - } - break + v.reset(OpAMD64ORLconstmodify) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) + return true } return false } -func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { +func rewriteValueAMD64_OpAMD64ORLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) - // result: (SETBstore [off] {sym} ptr (BTL x y) mem) + // match: (ORLload [off1] {sym} val (ADDQconst [off2] base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (ORLload [off1+off2] {sym} val base mem) for { - off := auxIntToInt32(v.AuxInt) + off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { + val := v_0 + if v_1.Op != OpAMD64ADDQconst { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLL { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true - } - break - } - // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) - // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLQ { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true - } - break - } - // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) - // cond: isUnsignedPowerOfTwo(uint32(c)) - // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32u(uint32(c)))] x) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - x := v_1.Args[0] + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] mem := v_2 - if !(isUnsignedPowerOfTwo(uint32(c))) { + if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) + v.reset(OpAMD64ORLload) + v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) + v.AddArg3(val, base, mem) return true } - // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log32u(uint32(c)))] x) mem) + // match: (ORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (ORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQconst { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { break } - c := auxIntToInt32(v_1.AuxInt) - x := v_1.Args[0] + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] mem := v_2 - if !(isUnsignedPowerOfTwo(uint64(c))) { + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64ORLload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, base, mem) return true } - // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log64u(uint64(c)))] x) mem) + // match: ( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) + // result: ( ORL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { + x := v_0 + ptr := v_1 + if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64MOVQconst { - continue - } - c := auxIntToInt64(v_1_0.AuxInt) - x := v_1_1 - mem := v_2 - if !(isUnsignedPowerOfTwo(uint64(c))) { - continue - } - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) - return true + y := v_2.Args[1] + if ptr != v_2.Args[0] { + break } - break + v.reset(OpAMD64ORL) + v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) + v0.AddArg(y) + v.AddArg2(x, v0) + return true } - // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) - // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) + return false +} +func rewriteValueAMD64_OpAMD64ORLmodify(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ORLmodify [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (ORLmodify [off1+off2] {sym} base val mem) for { - off := auxIntToInt32(v.AuxInt) + off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { + if v_0.Op != OpAMD64ADDQconst { break } - s := v_1.Args[0] - if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { break } - mem := v_2 - v.reset(OpAMD64SETEQstore) - v.AuxInt = int32ToAuxInt(off) + v.reset(OpAMD64ORLmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(s) - v.AddArg3(ptr, v0, mem) + v.AddArg3(base, val, mem) return true } - // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) - // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) + // match: (ORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (ORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - s := v_1.Args[0] - if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - mem := v_2 - v.reset(OpAMD64SETEQstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(s) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64ORLmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) + return false +} +func rewriteValueAMD64_OpAMD64ORQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ORQ (SHLQ (MOVQconst [1]) y) x) + // result: (BTSQ x y) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLQ { continue } - x := z1_0.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { continue } - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) + x := v_1 + v.reset(OpAMD64BTSQ) + v.AddArg2(x, y) return true } break } - // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) + // match: (ORQ (MOVQconst [c]) x) + // cond: isPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31 + // result: (BTSQconst [int8(log64u(uint64(c)))] x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64MOVQconst { continue } - x := z1_0.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { + c := auxIntToInt64(v_0.AuxInt) + x := v_1 + if !(isPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31) { continue } - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64BTSQconst) + v.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) + v.AddArg(x) return true } break } - // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) + // match: (ORQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (ORQconst [int32(c)] x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { continue } - x := z1_0.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { + c := auxIntToInt64(v_1.AuxInt) + if !(is32Bit(c)) { continue } - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) + v.reset(OpAMD64ORQconst) + v.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg(x) return true } break } - // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) + // match: (ORQ x (MOVLconst [c])) + // result: (ORQconst [c] x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { - continue - } - x := z1_0.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { continue } - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64ORQconst) + v.AuxInt = int32ToAuxInt(c) + v.AddArg(x) return true } break } - // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) + // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) + // result: (MOVQconst [c|d]) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64MOVQconst { continue } - x := z1.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { + c := auxIntToInt64(v_0.AuxInt) + if v_1.Op != OpAMD64MOVQconst { continue } - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) + d := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(c | d) return true } break } - // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) + // match: (ORQ x x) + // result: x for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { + x := v_0 + if x != v_1 { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - z1 := v_1_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + v.copyOf(x) + return true + } + // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (ORQload x [off] {sym} ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVQload { continue } - x := z1.Args[0] - z2 := v_1_1 - mem := v_2 - if !(z1 == z2) { + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } - v.reset(OpAMD64SETBstore) + v.reset(OpAMD64ORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - v.AddArg3(ptr, v0, mem) + v.AddArg3(x, ptr, mem) return true } break } - // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) - // result: (SETNEstore [off] {sym} ptr x mem) + return false +} +func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { + v_0 := v.Args[0] + // match: (ORQconst [c] (ORQconst [d] x)) + // result: (ORQconst [c | d] x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64InvertFlags { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64ORQconst { break } - x := v_1.Args[0] - mem := v_2 - v.reset(OpAMD64SETNEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + v.reset(OpAMD64ORQconst) + v.AuxInt = int32ToAuxInt(c | d) + v.AddArg(x) return true } - // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SETNEstore [off1+off2] {sym} base val mem) + // match: (ORQconst [0] x) + // result: x for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + if auxIntToInt32(v.AuxInt) != 0 { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + x := v_0 + v.copyOf(x) + return true + } + // match: (ORQconst [-1] _) + // result: (MOVQconst [-1]) + for { + if auxIntToInt32(v.AuxInt) != -1 { break } - v.reset(OpAMD64SETNEstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(-1) return true } - // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (ORQconst [c] (MOVQconst [d])) + // result: (MOVQconst [int64(c)|d]) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break - } - v.reset(OpAMD64SETNEstore) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + d := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(c) | d) return true } - // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + return false +} +func rewriteValueAMD64_OpAMD64ORQconstmodify(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ORQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) + // result: (ORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { - off := auxIntToInt32(v.AuxInt) + valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagEQ { + if v_0.Op != OpAMD64ADDQconst { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2)) { + break + } + v.reset(OpAMD64ORQconstmodify) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(0) - v.AddArg3(ptr, v0, mem) + v.AddArg2(base, mem) return true } - // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (ORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) + // result: (ORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_ULT { + valoff1 := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64ORQconstmodify) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) return true } - // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + return false +} +func rewriteValueAMD64_OpAMD64ORQload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ORQload [off1] {sym} val (ADDQconst [off2] base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (ORQload [off1+off2] {sym} val base mem) for { - off := auxIntToInt32(v.AuxInt) + off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagLT_UGT { + val := v_0 + if v_1.Op != OpAMD64ADDQconst { break } + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64ORQload) + v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + v.AddArg3(val, base, mem) return true } - // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: (ORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (ORQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_ULT { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { break } + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64ORQload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, base, mem) return true } - // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) - // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + // match: ( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) + // result: ( ORQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64FlagGT_UGT { + x := v_0 + ptr := v_1 + if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) - v0.AuxInt = int32ToAuxInt(1) - v.AddArg3(ptr, v0, mem) + y := v_2.Args[1] + if ptr != v_2.Args[0] { + break + } + v.reset(OpAMD64ORQ) + v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) + v0.AddArg(y) + v.AddArg2(x, v0) return true } return false } -func rewriteValueAMD64_OpAMD64SHLL(v *Value) bool { +func rewriteValueAMD64_OpAMD64ORQmodify(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (SHLL x (MOVQconst [c])) - // result: (SHLLconst [int8(c&31)] x) + // match: (ORQmodify [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (ORQmodify [off1+off2] {sym} base val mem) for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHLLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SHLL x (MOVLconst [c])) - // result: (SHLLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHLLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) + v.reset(OpAMD64ORQmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) return true } - // match: (SHLL x (ADDQconst [c] y)) - // cond: c & 31 == 0 - // result: (SHLL x y) + // match: (ORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (ORQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64ORQmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (SHLL x (NEGQ (ADDQconst [c] y))) - // cond: c & 31 == 0 - // result: (SHLL x (NEGQ y)) + return false +} +func rewriteValueAMD64_OpAMD64ROLB(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ROLB x (NEGQ y)) + // result: (RORB x y) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHLL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) + y := v_1.Args[0] + v.reset(OpAMD64RORB) + v.AddArg2(x, y) return true } - // match: (SHLL x (ANDQconst [c] y)) - // cond: c & 31 == 31 - // result: (SHLL x y) + // match: (ROLB x (NEGL y)) + // result: (RORB x y) for { x := v_0 - if v_1.Op != OpAMD64ANDQconst { + if v_1.Op != OpAMD64NEGL { break } - c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLL) + v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } - // match: (SHLL x (NEGQ (ANDQconst [c] y))) - // cond: c & 31 == 31 - // result: (SHLL x (NEGQ y)) + // match: (ROLB x (MOVQconst [c])) + // result: (ROLBconst [int8(c&7) ] x) for { x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { + if v_1.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64SHLL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64ROLBconst) + v.AuxInt = int8ToAuxInt(int8(c & 7)) + v.AddArg(x) return true } - // match: (SHLL x (ADDLconst [c] y)) - // cond: c & 31 == 0 - // result: (SHLL x y) + // match: (ROLB x (MOVLconst [c])) + // result: (ROLBconst [int8(c&7) ] x) for { x := v_0 - if v_1.Op != OpAMD64ADDLconst { + if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64ROLBconst) + v.AuxInt = int8ToAuxInt(int8(c & 7)) + v.AddArg(x) return true } - // match: (SHLL x (NEGL (ADDLconst [c] y))) - // cond: c & 31 == 0 - // result: (SHLL x (NEGL y)) + return false +} +func rewriteValueAMD64_OpAMD64ROLBconst(v *Value) bool { + v_0 := v.Args[0] + // match: (ROLBconst x [0]) + // result: x for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { + if auxIntToInt8(v.AuxInt) != 0 { break } - v.reset(OpAMD64SHLL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) + x := v_0 + v.copyOf(x) return true } - // match: (SHLL x (ANDLconst [c] y)) - // cond: c & 31 == 31 - // result: (SHLL x y) + return false +} +func rewriteValueAMD64_OpAMD64ROLL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ROLL x (NEGQ y)) + // result: (RORL x y) for { x := v_0 - if v_1.Op != OpAMD64ANDLconst { + if v_1.Op != OpAMD64NEGQ { break } - c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLL) + v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } - // match: (SHLL x (NEGL (ANDLconst [c] y))) - // cond: c & 31 == 31 - // result: (SHLL x (NEGL y)) + // match: (ROLL x (NEGL y)) + // result: (RORL x y) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) + y := v_1.Args[0] + v.reset(OpAMD64RORL) + v.AddArg2(x, y) return true } - // match: (SHLL l:(MOVLload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHLXLload [off] {sym} ptr x mem) + // match: (ROLL x (MOVQconst [c])) + // result: (ROLLconst [int8(c&31)] x) for { - l := v_0 - if l.Op != OpAMD64MOVLload { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64ROLLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) + return true + } + // match: (ROLL x (MOVLconst [c])) + // result: (ROLLconst [int8(c&31)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64SHLXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64ROLLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64ROLLconst(v *Value) bool { v_0 := v.Args[0] - // match: (SHLLconst x [0]) + // match: (ROLLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { @@ -20657,478 +30398,400 @@ func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { v.copyOf(x) return true } - // match: (SHLLconst [1] x) - // result: (ADDL x x) + return false +} +func rewriteValueAMD64_OpAMD64ROLQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ROLQ x (NEGQ y)) + // result: (RORQ x y) for { - if auxIntToInt8(v.AuxInt) != 1 { - break - } x := v_0 - v.reset(OpAMD64ADDL) - v.AddArg2(x, x) - return true - } - // match: (SHLLconst [c] (ADDL x x)) - // result: (SHLLconst [c+1] x) - for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ADDL { - break - } - x := v_0.Args[1] - if x != v_0.Args[0] { + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64SHLLconst) - v.AuxInt = int8ToAuxInt(c + 1) - v.AddArg(x) + y := v_1.Args[0] + v.reset(OpAMD64RORQ) + v.AddArg2(x, y) return true } - // match: (SHLLconst [d] (MOVLconst [c])) - // result: (MOVLconst [c << uint64(d)]) + // match: (ROLQ x (NEGL y)) + // result: (RORQ x y) for { - d := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + x := v_0 + if v_1.Op != OpAMD64NEGL { break } - c := auxIntToInt32(v_0.AuxInt) - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(c << uint64(d)) + y := v_1.Args[0] + v.reset(OpAMD64RORQ) + v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SHLQ x (MOVQconst [c])) - // result: (SHLQconst [int8(c&63)] x) + // match: (ROLQ x (MOVQconst [c])) + // result: (ROLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHLQconst) + v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } - // match: (SHLQ x (MOVLconst [c])) - // result: (SHLQconst [int8(c&63)] x) + // match: (ROLQ x (MOVLconst [c])) + // result: (ROLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHLQconst) + v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } - // match: (SHLQ x (ADDQconst [c] y)) - // cond: c & 63 == 0 - // result: (SHLQ x y) + return false +} +func rewriteValueAMD64_OpAMD64ROLQconst(v *Value) bool { + v_0 := v.Args[0] + // match: (ROLQconst x [0]) + // result: x for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { + if auxIntToInt8(v.AuxInt) != 0 { break } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { + x := v_0 + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ROLW(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ROLW x (NEGQ y)) + // result: (RORW x y) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64SHLQ) + y := v_1.Args[0] + v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } - // match: (SHLQ x (NEGQ (ADDQconst [c] y))) - // cond: c & 63 == 0 - // result: (SHLQ x (NEGQ y)) + // match: (ROLW x (NEGL y)) + // result: (RORW x y) for { x := v_0 - if v_1.Op != OpAMD64NEGQ { + if v_1.Op != OpAMD64NEGL { break } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { + y := v_1.Args[0] + v.reset(OpAMD64RORW) + v.AddArg2(x, y) + return true + } + // match: (ROLW x (MOVQconst [c])) + // result: (ROLWconst [int8(c&15)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64SHLQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64ROLWconst) + v.AuxInt = int8ToAuxInt(int8(c & 15)) + v.AddArg(x) return true } - // match: (SHLQ x (ANDQconst [c] y)) - // cond: c & 63 == 63 - // result: (SHLQ x y) + // match: (ROLW x (MOVLconst [c])) + // result: (ROLWconst [int8(c&15)] x) for { x := v_0 - if v_1.Op != OpAMD64ANDQconst { + if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { + v.reset(OpAMD64ROLWconst) + v.AuxInt = int8ToAuxInt(int8(c & 15)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ROLWconst(v *Value) bool { + v_0 := v.Args[0] + // match: (ROLWconst x [0]) + // result: x + for { + if auxIntToInt8(v.AuxInt) != 0 { break } - v.reset(OpAMD64SHLQ) - v.AddArg2(x, y) + x := v_0 + v.copyOf(x) return true } - // match: (SHLQ x (NEGQ (ANDQconst [c] y))) - // cond: c & 63 == 63 - // result: (SHLQ x (NEGQ y)) + return false +} +func rewriteValueAMD64_OpAMD64RORB(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (RORB x (NEGQ y)) + // result: (ROLB x y) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHLQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) + y := v_1.Args[0] + v.reset(OpAMD64ROLB) + v.AddArg2(x, y) return true } - // match: (SHLQ x (ADDLconst [c] y)) - // cond: c & 63 == 0 - // result: (SHLQ x y) + // match: (RORB x (NEGL y)) + // result: (ROLB x y) for { x := v_0 - if v_1.Op != OpAMD64ADDLconst { + if v_1.Op != OpAMD64NEGL { break } - c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHLQ) + v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } - // match: (SHLQ x (NEGL (ADDLconst [c] y))) - // cond: c & 63 == 0 - // result: (SHLQ x (NEGL y)) + // match: (RORB x (MOVQconst [c])) + // result: (ROLBconst [int8((-c)&7) ] x) for { x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { + if v_1.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64SHLQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64ROLBconst) + v.AuxInt = int8ToAuxInt(int8((-c) & 7)) + v.AddArg(x) return true } - // match: (SHLQ x (ANDLconst [c] y)) - // cond: c & 63 == 63 - // result: (SHLQ x y) + // match: (RORB x (MOVLconst [c])) + // result: (ROLBconst [int8((-c)&7) ] x) for { x := v_0 - if v_1.Op != OpAMD64ANDLconst { + if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHLQ) - v.AddArg2(x, y) + v.reset(OpAMD64ROLBconst) + v.AuxInt = int8ToAuxInt(int8((-c) & 7)) + v.AddArg(x) return true } - // match: (SHLQ x (NEGL (ANDLconst [c] y))) - // cond: c & 63 == 63 - // result: (SHLQ x (NEGL y)) + return false +} +func rewriteValueAMD64_OpAMD64RORL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (RORL x (NEGQ y)) + // result: (ROLL x y) for { x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64SHLQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) + y := v_1.Args[0] + v.reset(OpAMD64ROLL) + v.AddArg2(x, y) return true } - // match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHLXQload [off] {sym} ptr x mem) + // match: (RORL x (NEGL y)) + // result: (ROLL x y) for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + x := v_0 + if v_1.Op != OpAMD64NEGL { break } - v.reset(OpAMD64SHLXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) + y := v_1.Args[0] + v.reset(OpAMD64ROLL) + v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { - v_0 := v.Args[0] - // match: (SHLQconst x [0]) - // result: x + // match: (RORL x (MOVQconst [c])) + // result: (ROLLconst [int8((-c)&31)] x) for { - if auxIntToInt8(v.AuxInt) != 0 { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - x := v_0 - v.copyOf(x) + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64ROLLconst) + v.AuxInt = int8ToAuxInt(int8((-c) & 31)) + v.AddArg(x) return true } - // match: (SHLQconst [1] x) - // result: (ADDQ x x) + // match: (RORL x (MOVLconst [c])) + // result: (ROLLconst [int8((-c)&31)] x) for { - if auxIntToInt8(v.AuxInt) != 1 { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - x := v_0 - v.reset(OpAMD64ADDQ) - v.AddArg2(x, x) + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64ROLLconst) + v.AuxInt = int8ToAuxInt(int8((-c) & 31)) + v.AddArg(x) return true } - // match: (SHLQconst [c] (ADDQ x x)) - // result: (SHLQconst [c+1] x) + return false +} +func rewriteValueAMD64_OpAMD64RORQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (RORQ x (NEGQ y)) + // result: (ROLQ x y) for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ADDQ { - break - } - x := v_0.Args[1] - if x != v_0.Args[0] { + x := v_0 + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64SHLQconst) - v.AuxInt = int8ToAuxInt(c + 1) - v.AddArg(x) + y := v_1.Args[0] + v.reset(OpAMD64ROLQ) + v.AddArg2(x, y) return true } - // match: (SHLQconst [d] (MOVQconst [c])) - // result: (MOVQconst [c << uint64(d)]) + // match: (RORQ x (NEGL y)) + // result: (ROLQ x y) for { - d := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + x := v_0 + if v_1.Op != OpAMD64NEGL { break } - c := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(c << uint64(d)) + y := v_1.Args[0] + v.reset(OpAMD64ROLQ) + v.AddArg2(x, y) return true } - // match: (SHLQconst [d] (MOVLconst [c])) - // result: (MOVQconst [int64(c) << uint64(d)]) + // match: (RORQ x (MOVQconst [c])) + // result: (ROLQconst [int8((-c)&63)] x) for { - d := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - c := auxIntToInt32(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(c) << uint64(d)) + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64ROLQconst) + v.AuxInt = int8ToAuxInt(int8((-c) & 63)) + v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpAMD64SHLXLload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SHLXLload [off] {sym} ptr (MOVLconst [c]) mem) - // result: (SHLLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) + // match: (RORQ x (MOVLconst [c])) + // result: (ROLQconst [int8((-c)&63)] x) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 + x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64SHLLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - v.AddArg(v0) + v.reset(OpAMD64ROLQconst) + v.AuxInt = int8ToAuxInt(int8((-c) & 63)) + v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64SHLXQload(v *Value) bool { - v_2 := v.Args[2] +func rewriteValueAMD64_OpAMD64RORW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SHLXQload [off] {sym} ptr (MOVQconst [c]) mem) - // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) + // match: (RORW x (NEGQ y)) + // result: (ROLW x y) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVQconst { + x := v_0 + if v_1.Op != OpAMD64NEGQ { break } - c := auxIntToInt64(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64SHLQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - v.AddArg(v0) + y := v_1.Args[0] + v.reset(OpAMD64ROLW) + v.AddArg2(x, y) return true } - // match: (SHLXQload [off] {sym} ptr (MOVLconst [c]) mem) - // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) + // match: (RORW x (NEGL y)) + // result: (ROLW x y) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64MOVLconst { + x := v_0 + if v_1.Op != OpAMD64NEGL { break } - c := auxIntToInt32(v_1.AuxInt) - mem := v_2 - v.reset(OpAMD64SHLQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - v.AddArg(v0) + y := v_1.Args[0] + v.reset(OpAMD64ROLW) + v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (SHRB x (MOVQconst [c])) - // cond: c&31 < 8 - // result: (SHRBconst [int8(c&31)] x) + // match: (RORW x (MOVQconst [c])) + // result: (ROLWconst [int8((-c)&15)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) - if !(c&31 < 8) { - break - } - v.reset(OpAMD64SHRBconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.reset(OpAMD64ROLWconst) + v.AuxInt = int8ToAuxInt(int8((-c) & 15)) v.AddArg(x) return true } - // match: (SHRB x (MOVLconst [c])) - // cond: c&31 < 8 - // result: (SHRBconst [int8(c&31)] x) + // match: (RORW x (MOVLconst [c])) + // result: (ROLWconst [int8((-c)&15)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - if !(c&31 < 8) { - break - } - v.reset(OpAMD64SHRBconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.reset(OpAMD64ROLWconst) + v.AuxInt = int8ToAuxInt(int8((-c) & 15)) v.AddArg(x) return true } - // match: (SHRB _ (MOVQconst [c])) - // cond: c&31 >= 8 - // result: (MOVLconst [0]) + return false +} +func rewriteValueAMD64_OpAMD64SARB(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SARB x (MOVQconst [c])) + // result: (SARBconst [int8(min(int64(c)&31,7))] x) for { + x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) - if !(c&31 >= 8) { - break - } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64SARBconst) + v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 7))) + v.AddArg(x) return true } - // match: (SHRB _ (MOVLconst [c])) - // cond: c&31 >= 8 - // result: (MOVLconst [0]) + // match: (SARB x (MOVLconst [c])) + // result: (SARBconst [int8(min(int64(c)&31,7))] x) for { + x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - if !(c&31 >= 8) { - break - } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + v.reset(OpAMD64SARBconst) + v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 7))) + v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64SARBconst(v *Value) bool { v_0 := v.Args[0] - // match: (SHRBconst x [0]) + // match: (SARBconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { @@ -21138,41 +30801,53 @@ func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { v.copyOf(x) return true } + // match: (SARBconst [c] (MOVQconst [d])) + // result: (MOVQconst [int64(int8(d))>>uint64(c)]) + for { + c := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { + break + } + d := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(int8(d)) >> uint64(c)) + return true + } return false } -func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { +func rewriteValueAMD64_OpAMD64SARL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SHRL x (MOVQconst [c])) - // result: (SHRLconst [int8(c&31)] x) + // match: (SARL x (MOVQconst [c])) + // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHRLconst) + v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } - // match: (SHRL x (MOVLconst [c])) - // result: (SHRLconst [int8(c&31)] x) + // match: (SARL x (MOVLconst [c])) + // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHRLconst) + v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } - // match: (SHRL x (ADDQconst [c] y)) + // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 - // result: (SHRL x y) + // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { @@ -21183,13 +30858,13 @@ func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { if !(c&31 == 0) { break } - v.reset(OpAMD64SHRL) + v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } - // match: (SHRL x (NEGQ (ADDQconst [c] y))) + // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 - // result: (SHRL x (NEGQ y)) + // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { @@ -21205,15 +30880,15 @@ func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { if !(c&31 == 0) { break } - v.reset(OpAMD64SHRL) + v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (SHRL x (ANDQconst [c] y)) + // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 - // result: (SHRL x y) + // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { @@ -21224,13 +30899,13 @@ func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { if !(c&31 == 31) { break } - v.reset(OpAMD64SHRL) + v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } - // match: (SHRL x (NEGQ (ANDQconst [c] y))) + // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 - // result: (SHRL x (NEGQ y)) + // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { @@ -21246,15 +30921,15 @@ func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { if !(c&31 == 31) { break } - v.reset(OpAMD64SHRL) + v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (SHRL x (ADDLconst [c] y)) + // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 - // result: (SHRL x y) + // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { @@ -21265,13 +30940,13 @@ func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { if !(c&31 == 0) { break } - v.reset(OpAMD64SHRL) + v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } - // match: (SHRL x (NEGL (ADDLconst [c] y))) + // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 - // result: (SHRL x (NEGL y)) + // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { @@ -21287,15 +30962,15 @@ func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { if !(c&31 == 0) { break } - v.reset(OpAMD64SHRL) + v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (SHRL x (ANDLconst [c] y)) + // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 - // result: (SHRL x y) + // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { @@ -21306,13 +30981,13 @@ func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { if !(c&31 == 31) { break } - v.reset(OpAMD64SHRL) + v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } - // match: (SHRL x (NEGL (ANDLconst [c] y))) + // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 - // result: (SHRL x (NEGL y)) + // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { @@ -21328,15 +31003,15 @@ func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { if !(c&31 == 31) { break } - v.reset(OpAMD64SHRL) + v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (SHRL l:(MOVLload [off] {sym} ptr mem) x) + // match: (SARL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHRXLload [off] {sym} ptr x mem) + // result: (SARXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { @@ -21350,7 +31025,7 @@ func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64SHRXLload) + v.reset(OpAMD64SARXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) @@ -21358,24 +31033,9 @@ func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { v_0 := v.Args[0] - // match: (SHRLconst [1] (ADDL x x)) - // result: (ANDLconst [0x7fffffff] x) - for { - if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64ADDL { - break - } - x := v_0.Args[1] - if x != v_0.Args[0] { - break - } - v.reset(OpAMD64ANDLconst) - v.AuxInt = int32ToAuxInt(0x7fffffff) - v.AddArg(x) - return true - } - // match: (SHRLconst x [0]) + // match: (SARLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { @@ -21385,41 +31045,53 @@ func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { v.copyOf(x) return true } - return false -} -func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { + // match: (SARLconst [c] (MOVQconst [d])) + // result: (MOVQconst [int64(int32(d))>>uint64(c)]) + for { + c := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { + break + } + d := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(int32(d)) >> uint64(c)) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SARQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SHRQ x (MOVQconst [c])) - // result: (SHRQconst [int8(c&63)] x) + // match: (SARQ x (MOVQconst [c])) + // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHRQconst) + v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } - // match: (SHRQ x (MOVLconst [c])) - // result: (SHRQconst [int8(c&63)] x) + // match: (SARQ x (MOVLconst [c])) + // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHRQconst) + v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } - // match: (SHRQ x (ADDQconst [c] y)) + // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 - // result: (SHRQ x y) + // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { @@ -21430,13 +31102,13 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { if !(c&63 == 0) { break } - v.reset(OpAMD64SHRQ) + v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } - // match: (SHRQ x (NEGQ (ADDQconst [c] y))) + // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 - // result: (SHRQ x (NEGQ y)) + // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { @@ -21452,15 +31124,15 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { if !(c&63 == 0) { break } - v.reset(OpAMD64SHRQ) + v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (SHRQ x (ANDQconst [c] y)) + // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 - // result: (SHRQ x y) + // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { @@ -21471,13 +31143,13 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { if !(c&63 == 63) { break } - v.reset(OpAMD64SHRQ) + v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } - // match: (SHRQ x (NEGQ (ANDQconst [c] y))) + // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 - // result: (SHRQ x (NEGQ y)) + // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { @@ -21493,15 +31165,15 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { if !(c&63 == 63) { break } - v.reset(OpAMD64SHRQ) + v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (SHRQ x (ADDLconst [c] y)) + // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 - // result: (SHRQ x y) + // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { @@ -21512,13 +31184,13 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { if !(c&63 == 0) { break } - v.reset(OpAMD64SHRQ) + v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } - // match: (SHRQ x (NEGL (ADDLconst [c] y))) + // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 - // result: (SHRQ x (NEGL y)) + // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { @@ -21534,15 +31206,15 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { if !(c&63 == 0) { break } - v.reset(OpAMD64SHRQ) + v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (SHRQ x (ANDLconst [c] y)) + // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 - // result: (SHRQ x y) + // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { @@ -21553,13 +31225,13 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { if !(c&63 == 63) { break } - v.reset(OpAMD64SHRQ) + v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } - // match: (SHRQ x (NEGL (ANDLconst [c] y))) + // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 - // result: (SHRQ x (NEGL y)) + // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { @@ -21575,15 +31247,15 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { if !(c&63 == 63) { break } - v.reset(OpAMD64SHRQ) + v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x) + // match: (SARQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHRXQload [off] {sym} ptr x mem) + // result: (SARXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { @@ -21597,7 +31269,7 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64SHRXQload) + v.reset(OpAMD64SARXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) @@ -21605,107 +31277,66 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { v_0 := v.Args[0] - // match: (SHRQconst [1] (ADDQ x x)) - // result: (BTRQconst [63] x) + // match: (SARQconst x [0]) + // result: x for { - if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64ADDQ { - break - } - x := v_0.Args[1] - if x != v_0.Args[0] { + if auxIntToInt8(v.AuxInt) != 0 { break } - v.reset(OpAMD64BTRQconst) - v.AuxInt = int8ToAuxInt(63) - v.AddArg(x) + x := v_0 + v.copyOf(x) return true } - // match: (SHRQconst x [0]) - // result: x + // match: (SARQconst [c] (MOVQconst [d])) + // result: (MOVQconst [d>>uint64(c)]) for { - if auxIntToInt8(v.AuxInt) != 0 { + c := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { break } - x := v_0 - v.copyOf(x) + d := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } return false } -func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool { +func rewriteValueAMD64_OpAMD64SARW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (SHRW x (MOVQconst [c])) - // cond: c&31 < 16 - // result: (SHRWconst [int8(c&31)] x) + // match: (SARW x (MOVQconst [c])) + // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) - if !(c&31 < 16) { - break - } - v.reset(OpAMD64SHRWconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.reset(OpAMD64SARWconst) + v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } - // match: (SHRW x (MOVLconst [c])) - // cond: c&31 < 16 - // result: (SHRWconst [int8(c&31)] x) + // match: (SARW x (MOVLconst [c])) + // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) - if !(c&31 < 16) { - break - } - v.reset(OpAMD64SHRWconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.reset(OpAMD64SARWconst) + v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } - // match: (SHRW _ (MOVQconst [c])) - // cond: c&31 >= 16 - // result: (MOVLconst [0]) - for { - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(c&31 >= 16) { - break - } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } - // match: (SHRW _ (MOVLconst [c])) - // cond: c&31 >= 16 - // result: (MOVLconst [0]) - for { - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(c&31 >= 16) { - break - } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) - return true - } return false } -func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64SARWconst(v *Value) bool { v_0 := v.Args[0] - // match: (SHRWconst x [0]) + // match: (SARWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { @@ -21715,16 +31346,28 @@ func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { v.copyOf(x) return true } + // match: (SARWconst [c] (MOVQconst [d])) + // result: (MOVQconst [int64(int16(d))>>uint64(c)]) + for { + c := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { + break + } + d := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(int16(d)) >> uint64(c)) + return true + } return false } -func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { +func rewriteValueAMD64_OpAMD64SARXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (SHRXLload [off] {sym} ptr (MOVLconst [c]) mem) - // result: (SHRLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) + // match: (SARXLload [off] {sym} ptr (MOVLconst [c]) mem) + // result: (SARLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -21734,7 +31377,7 @@ func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { } c := auxIntToInt32(v_1.AuxInt) mem := v_2 - v.reset(OpAMD64SHRLconst) + v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) @@ -21745,14 +31388,14 @@ func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { +func rewriteValueAMD64_OpAMD64SARXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (SHRXQload [off] {sym} ptr (MOVQconst [c]) mem) - // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) + // match: (SARXQload [off] {sym} ptr (MOVQconst [c]) mem) + // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -21762,7 +31405,7 @@ func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { } c := auxIntToInt64(v_1.AuxInt) mem := v_2 - v.reset(OpAMD64SHRQconst) + v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) @@ -21771,8 +31414,8 @@ func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { v.AddArg(v0) return true } - // match: (SHRXQload [off] {sym} ptr (MOVLconst [c]) mem) - // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) + // match: (SARXQload [off] {sym} ptr (MOVLconst [c]) mem) + // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -21782,7 +31425,7 @@ func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { } c := auxIntToInt32(v_1.AuxInt) mem := v_2 - v.reset(OpAMD64SHRQconst) + v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) @@ -21793,457 +31436,497 @@ func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (SUBL x (MOVLconst [c])) - // result: (SUBLconst x [c]) + // match: (SBBLcarrymask (FlagEQ)) + // result: (MOVLconst [0]) for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { + if v_0.Op != OpAMD64FlagEQ { break } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SUBLconst) - v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (SUBL (MOVLconst [c]) x) - // result: (NEGL (SUBLconst x [c])) + // match: (SBBLcarrymask (FlagLT_ULT)) + // result: (MOVLconst [-1]) for { - if v_0.Op != OpAMD64MOVLconst { + if v_0.Op != OpAMD64FlagLT_ULT { break } - c := auxIntToInt32(v_0.AuxInt) - x := v_1 - v.reset(OpAMD64NEGL) - v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) - v0.AuxInt = int32ToAuxInt(c) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(-1) return true } - // match: (SUBL x x) + // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { - x := v_0 - if x != v_1 { + if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } - // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (SUBLload x [off] {sym} ptr mem) + // match: (SBBLcarrymask (FlagGT_ULT)) + // result: (MOVLconst [-1]) for { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + if v_0.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64SUBLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(-1) return true } - return false -} -func rewriteValueAMD64_OpAMD64SUBLconst(v *Value) bool { - v_0 := v.Args[0] - // match: (SUBLconst [c] x) - // cond: c==0 - // result: x + // match: (SBBLcarrymask (FlagGT_UGT)) + // result: (MOVLconst [0]) for { - c := auxIntToInt32(v.AuxInt) - x := v_0 - if !(c == 0) { + if v_0.Op != OpAMD64FlagGT_UGT { break } - v.copyOf(x) - return true - } - // match: (SUBLconst [c] x) - // result: (ADDLconst [-c] x) - for { - c := auxIntToInt32(v.AuxInt) - x := v_0 - v.reset(OpAMD64ADDLconst) - v.AuxInt = int32ToAuxInt(-c) - v.AddArg(x) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } + return false } -func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { +func rewriteValueAMD64_OpAMD64SBBQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SUBLload [off1+off2] {sym} val base mem) + // match: (SBBQ x (MOVQconst [c]) borrow) + // cond: is32Bit(c) + // result: (SBBQconst x [int32(c)] borrow) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + c := auxIntToInt64(v_1.AuxInt) + borrow := v_2 + if !(is32Bit(c)) { break } - v.reset(OpAMD64SUBLload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) + v.reset(OpAMD64SBBQconst) + v.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg2(x, borrow) return true } - // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // match: (SBBQ x y (FlagEQ)) + // result: (SUBQborrow x y) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { - break - } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + x := v_0 + y := v_1 + if v_2.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64SUBLload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) + v.reset(OpAMD64SUBQborrow) + v.AddArg2(x, y) return true } - // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) - // result: (SUBL x (MOVLf2i y)) + // match: (SBBQ x y (InvertFlags f)) + // result: (SBBQ x y (Select1 (NEGLflags (MOVBQZX (SETA f))))) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) x := v_0 - ptr := v_1 - if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { - break - } - y := v_2.Args[1] - if ptr != v_2.Args[0] { + y := v_1 + if v_2.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64SUBL) - v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) - v0.AddArg(y) - v.AddArg2(x, v0) + f := v_2.Args[0] + v.reset(OpAMD64SBBQ) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, types.Types[types.TUINT32]) + v3 := b.NewValue0(v.Pos, OpAMD64SETA, types.Types[types.TUINT8]) + v3.AddArg(f) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } return false } -func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value) bool { v_0 := v.Args[0] - // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SUBLmodify [off1+off2] {sym} base val mem) + // match: (SBBQcarrymask (FlagEQ)) + // result: (MOVQconst [0]) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { - break - } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + if v_0.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64SUBLmodify) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(0) return true } - // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (SBBQcarrymask (FlagLT_ULT)) + // result: (MOVQconst [-1]) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { - break - } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + if v_0.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64SUBLmodify) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(-1) return true } - return false -} -func rewriteValueAMD64_OpAMD64SUBQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SUBQ x (MOVQconst [c])) - // cond: is32Bit(c) - // result: (SUBQconst x [int32(c)]) + // match: (SBBQcarrymask (FlagLT_UGT)) + // result: (MOVQconst [0]) for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(is32Bit(c)) { + if v_0.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64SUBQconst) - v.AuxInt = int32ToAuxInt(int32(c)) - v.AddArg(x) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(0) return true } - // match: (SUBQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (NEGQ (SUBQconst x [int32(c)])) + // match: (SBBQcarrymask (FlagGT_ULT)) + // result: (MOVQconst [-1]) for { - if v_0.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_0.AuxInt) - x := v_1 - if !(is32Bit(c)) { + if v_0.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64NEGQ) - v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) - v0.AuxInt = int32ToAuxInt(int32(c)) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(-1) return true } - // match: (SUBQ x x) + // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { - x := v_0 - if x != v_1 { + if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } - // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (SUBQload x [off] {sym} ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64SUBQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } return false } -func rewriteValueAMD64_OpAMD64SUBQborrow(v *Value) bool { +func rewriteValueAMD64_OpAMD64SBBQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (SUBQborrow x (MOVQconst [c])) - // cond: is32Bit(c) - // result: (SUBQconstborrow x [int32(c)]) + b := v.Block + typ := &b.Func.Config.Types + // match: (SBBQconst x [c] (FlagEQ)) + // result: (SUBQconstborrow x [c]) for { + c := auxIntToInt32(v.AuxInt) x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(is32Bit(c)) { + if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) - v.AuxInt = int32ToAuxInt(int32(c)) + v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpAMD64SUBQconst(v *Value) bool { - v_0 := v.Args[0] - // match: (SUBQconst [0] x) - // result: x + // match: (SBBQconst x [c] (InvertFlags f)) + // result: (SBBQconst x [c] (Select1 (NEGLflags (MOVBQZX (SETA f))))) for { - if auxIntToInt32(v.AuxInt) != 0 { + c := auxIntToInt32(v.AuxInt) + x := v_0 + if v_1.Op != OpAMD64InvertFlags { break } - x := v_0 - v.copyOf(x) - return true + f := v_1.Args[0] + v.reset(OpAMD64SBBQconst) + v.AuxInt = int32ToAuxInt(c) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, types.Types[types.TUINT32]) + v3 := b.NewValue0(v.Pos, OpAMD64SETA, types.Types[types.TUINT8]) + v3.AddArg(f) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true } - // match: (SUBQconst [c] x) - // cond: c != -(1<<31) - // result: (ADDQconst [-c] x) + return false +} +func rewriteValueAMD64_OpAMD64SETA(v *Value) bool { + v_0 := v.Args[0] + // match: (SETA (InvertFlags x)) + // result: (SETB x) for { - c := auxIntToInt32(v.AuxInt) - x := v_0 - if !(c != -(1 << 31)) { + if v_0.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64ADDQconst) - v.AuxInt = int32ToAuxInt(-c) + x := v_0.Args[0] + v.reset(OpAMD64SETB) v.AddArg(x) return true } - // match: (SUBQconst (MOVQconst [d]) [c]) - // result: (MOVQconst [d-int64(c)]) + // match: (SETA (FlagEQ)) + // result: (MOVLconst [0]) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + if v_0.Op != OpAMD64FlagEQ { break } - d := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(d - int64(c)) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (SUBQconst (SUBQconst x [d]) [c]) - // cond: is32Bit(int64(-c)-int64(d)) - // result: (ADDQconst [-c-d] x) + // match: (SETA (FlagLT_ULT)) + // result: (MOVLconst [0]) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64SUBQconst { + if v_0.Op != OpAMD64FlagLT_ULT { break } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(is32Bit(int64(-c) - int64(d))) { + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) + return true + } + // match: (SETA (FlagLT_UGT)) + // result: (MOVLconst [1]) + for { + if v_0.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64ADDQconst) - v.AuxInt = int32ToAuxInt(-c - d) - v.AddArg(x) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) + return true + } + // match: (SETA (FlagGT_ULT)) + // result: (MOVLconst [0]) + for { + if v_0.Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) + return true + } + // match: (SETA (FlagGT_UGT)) + // result: (MOVLconst [1]) + for { + if v_0.Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } return false } -func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64SETAE(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SUBQload [off1+off2] {sym} val base mem) + // match: (SETAE (TESTQ x x)) + // result: (ConstBool [true]) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + x := v_0.Args[1] + if x != v_0.Args[0] { break } - v.reset(OpAMD64SUBQload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(true) return true } - // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // match: (SETAE (TESTL x x)) + // result: (ConstBool [true]) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + x := v_0.Args[1] + if x != v_0.Args[0] { break } - v.reset(OpAMD64SUBQload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(true) return true } - // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) - // result: (SUBQ x (MOVQf2i y)) + // match: (SETAE (TESTW x x)) + // result: (ConstBool [true]) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - x := v_0 - ptr := v_1 - if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { + if v_0.Op != OpAMD64TESTW { break } - y := v_2.Args[1] - if ptr != v_2.Args[0] { + x := v_0.Args[1] + if x != v_0.Args[0] { break } - v.reset(OpAMD64SUBQ) - v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) - v0.AddArg(y) - v.AddArg2(x, v0) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(true) + return true + } + // match: (SETAE (TESTB x x)) + // result: (ConstBool [true]) + for { + if v_0.Op != OpAMD64TESTB { + break + } + x := v_0.Args[1] + if x != v_0.Args[0] { + break + } + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(true) + return true + } + // match: (SETAE (BTLconst [0] x)) + // result: (XORLconst [1] (ANDLconst [1] x)) + for { + if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { + break + } + x := v_0.Args[0] + v.reset(OpAMD64XORLconst) + v.AuxInt = int32ToAuxInt(1) + v0 := b.NewValue0(v.Pos, OpAMD64ANDLconst, typ.Bool) + v0.AuxInt = int32ToAuxInt(1) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (SETAE (BTQconst [0] x)) + // result: (XORLconst [1] (ANDLconst [1] x)) + for { + if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { + break + } + x := v_0.Args[0] + v.reset(OpAMD64XORLconst) + v.AuxInt = int32ToAuxInt(1) + v0 := b.NewValue0(v.Pos, OpAMD64ANDLconst, typ.Bool) + v0.AuxInt = int32ToAuxInt(1) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (SETAE c:(CMPQconst [128] x)) + // cond: c.Uses == 1 + // result: (SETA (CMPQconst [127] x)) + for { + c := v_0 + if c.Op != OpAMD64CMPQconst || auxIntToInt32(c.AuxInt) != 128 { + break + } + x := c.Args[0] + if !(c.Uses == 1) { + break + } + v.reset(OpAMD64SETA) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(127) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (SETAE c:(CMPLconst [128] x)) + // cond: c.Uses == 1 + // result: (SETA (CMPLconst [127] x)) + for { + c := v_0 + if c.Op != OpAMD64CMPLconst || auxIntToInt32(c.AuxInt) != 128 { + break + } + x := c.Args[0] + if !(c.Uses == 1) { + break + } + v.reset(OpAMD64SETA) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(127) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (SETAE (InvertFlags x)) + // result: (SETBE x) + for { + if v_0.Op != OpAMD64InvertFlags { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETBE) + v.AddArg(x) + return true + } + // match: (SETAE (FlagEQ)) + // result: (MOVLconst [1]) + for { + if v_0.Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) + return true + } + // match: (SETAE (FlagLT_ULT)) + // result: (MOVLconst [0]) + for { + if v_0.Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) + return true + } + // match: (SETAE (FlagLT_UGT)) + // result: (MOVLconst [1]) + for { + if v_0.Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) + return true + } + // match: (SETAE (FlagGT_ULT)) + // result: (MOVLconst [0]) + for { + if v_0.Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) + return true + } + // match: (SETAE (FlagGT_UGT)) + // result: (MOVLconst [1]) + for { + if v_0.Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } return false } -func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { +func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) + b := v.Block + typ := &b.Func.Config.Types + // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) + // result: (SETBEstore [off] {sym} ptr x mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64InvertFlags { + break + } + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64SETBEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SUBQmodify [off1+off2] {sym} base val mem) + // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -22257,15 +31940,15 @@ func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64SUBQmodify) + v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } - // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) @@ -22280,8342 +31963,75718 @@ func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SUBQmodify) + v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SUBSD(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (SUBSDload x [off] {sym} ptr mem) + // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVSDload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64SUBSDload) + mem := v_2 + v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SUBSDload [off1+off2] {sym} val base mem) + // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - off1 := auxIntToInt32(v.AuxInt) + off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_ULT { break } - off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break - } - v.reset(OpAMD64SUBSDload) - v.AuxInt = int32ToAuxInt(off1 + off2) + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_UGT { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { - break - } - v.reset(OpAMD64SUBSDload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } - // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) - // result: (SUBSD x (MOVQi2f y)) + // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - x := v_0 - ptr := v_1 - if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { - break - } - y := v_2.Args[1] - if ptr != v_2.Args[0] { + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64SUBSD) - v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) - v0.AddArg(y) - v.AddArg2(x, v0) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SUBSS(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (SUBSSload x [off] {sym} ptr mem) + // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVSSload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64SUBSSload) + mem := v_2 + v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } return false } -func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { +func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) + // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) + // result: (SETBstore [off] {sym} ptr x mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64InvertFlags { + break + } + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (SUBSSload [off1+off2] {sym} val base mem) + // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64ADDQconst { break } - off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64SUBSSload) + v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) + v.AddArg3(base, val, mem) return true } - // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64LEAQ { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64SUBSSload) + v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) + v.AddArg3(base, val, mem) return true } - // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) - // result: (SUBSS x (MOVLi2f y)) + // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - x := v_0 - ptr := v_1 - if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { - break - } - y := v_2.Args[1] - if ptr != v_2.Args[0] { + ptr := v_0 + if v_1.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64SUBSS) - v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) - v0.AddArg(y) - v.AddArg2(x, v0) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64TESTB(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (TESTB (MOVLconst [c]) x) - // result: (TESTBconst [int8(c)] x) + // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64MOVLconst { - continue - } - c := auxIntToInt32(v_0.AuxInt) - x := v_1 - v.reset(OpAMD64TESTBconst) - v.AuxInt = int8ToAuxInt(int8(c)) - v.AddArg(x) - return true + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_ULT { + break } - break + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) + return true } - // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) - // cond: l == l2 && l.Uses == 2 && clobber(l) - // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0, off)] ptr mem) + // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - l := v_0 - if l.Op != OpAMD64MOVBload { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - l2 := v_1 - if !(l == l2 && l.Uses == 2 && clobber(l)) { - continue - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) - v.copyOf(v0) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_UGT { + break } - break + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) + return true } - return false -} -func rewriteValueAMD64_OpAMD64TESTBconst(v *Value) bool { - v_0 := v.Args[0] - // match: (TESTBconst [-1] x) - // cond: x.Op != OpAMD64MOVLconst - // result: (TESTB x x) + // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - if auxIntToInt8(v.AuxInt) != -1 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_ULT { break } - x := v_0 - if !(x.Op != OpAMD64MOVLconst) { + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) + return true + } + // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64TESTB) - v.AddArg2(x, x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } return false } -func rewriteValueAMD64_OpAMD64TESTL(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64SETB(v *Value) bool { v_0 := v.Args[0] b := v.Block - // match: (TESTL (MOVLconst [c]) x) - // result: (TESTLconst [c] x) + // match: (SETB (TESTQ x x)) + // result: (ConstBool [false]) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64MOVLconst { - continue - } - c := auxIntToInt32(v_0.AuxInt) - x := v_1 - v.reset(OpAMD64TESTLconst) - v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) - return true + if v_0.Op != OpAMD64TESTQ { + break } - break - } - // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) - // cond: l == l2 && l.Uses == 2 && clobber(l) - // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0, off)] ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - l := v_0 - if l.Op != OpAMD64MOVLload { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - l2 := v_1 - if !(l == l2 && l.Uses == 2 && clobber(l)) { - continue - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) - v.copyOf(v0) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + x := v_0.Args[1] + if x != v_0.Args[0] { + break } - break + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(false) + return true } - // match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a) - // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) - // result: (TESTL (MOVLload [off] {sym} ptr mem) x) + // match: (SETB (TESTL x x)) + // result: (ConstBool [false]) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - a := v_0 - if a.Op != OpAMD64ANDLload { - continue - } - off := auxIntToInt32(a.AuxInt) - sym := auxToSym(a.Aux) - mem := a.Args[2] - x := a.Args[0] - ptr := a.Args[1] - if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { - continue - } - v.reset(OpAMD64TESTL) - v0 := b.NewValue0(a.Pos, OpAMD64MOVLload, a.Type) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - v.AddArg2(v0, x) - return true + if v_0.Op != OpAMD64TESTL { + break } - break - } - return false -} -func rewriteValueAMD64_OpAMD64TESTLconst(v *Value) bool { - v_0 := v.Args[0] - // match: (TESTLconst [c] (MOVLconst [c])) - // cond: c == 0 - // result: (FlagEQ) - for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c == 0) { + x := v_0.Args[1] + if x != v_0.Args[0] { break } - v.reset(OpAMD64FlagEQ) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(false) return true } - // match: (TESTLconst [c] (MOVLconst [c])) - // cond: c < 0 - // result: (FlagLT_UGT) + // match: (SETB (TESTW x x)) + // result: (ConstBool [false]) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c < 0) { + if v_0.Op != OpAMD64TESTW { break } - v.reset(OpAMD64FlagLT_UGT) - return true - } - // match: (TESTLconst [c] (MOVLconst [c])) - // cond: c > 0 - // result: (FlagGT_UGT) - for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c > 0) { + x := v_0.Args[1] + if x != v_0.Args[0] { break } - v.reset(OpAMD64FlagGT_UGT) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(false) return true } - // match: (TESTLconst [-1] x) - // cond: x.Op != OpAMD64MOVLconst - // result: (TESTL x x) + // match: (SETB (TESTB x x)) + // result: (ConstBool [false]) for { - if auxIntToInt32(v.AuxInt) != -1 { + if v_0.Op != OpAMD64TESTB { break } - x := v_0 - if !(x.Op != OpAMD64MOVLconst) { + x := v_0.Args[1] + if x != v_0.Args[0] { break } - v.reset(OpAMD64TESTL) - v.AddArg2(x, x) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(false) return true } - return false -} -func rewriteValueAMD64_OpAMD64TESTQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (TESTQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (TESTQconst [int32(c)] x) + // match: (SETB (BTLconst [0] x)) + // result: (ANDLconst [1] x) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64MOVQconst { - continue - } - c := auxIntToInt64(v_0.AuxInt) - x := v_1 - if !(is32Bit(c)) { - continue - } - v.reset(OpAMD64TESTQconst) - v.AuxInt = int32ToAuxInt(int32(c)) - v.AddArg(x) - return true + if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { + break } - break + x := v_0.Args[0] + v.reset(OpAMD64ANDLconst) + v.AuxInt = int32ToAuxInt(1) + v.AddArg(x) + return true } - // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) - // cond: l == l2 && l.Uses == 2 && clobber(l) - // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0, off)] ptr mem) + // match: (SETB (BTQconst [0] x)) + // result: (ANDQconst [1] x) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - l := v_0 - if l.Op != OpAMD64MOVQload { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - l2 := v_1 - if !(l == l2 && l.Uses == 2 && clobber(l)) { - continue - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) - v.copyOf(v0) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { + break } - break + x := v_0.Args[0] + v.reset(OpAMD64ANDQconst) + v.AuxInt = int32ToAuxInt(1) + v.AddArg(x) + return true } - // match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a) - // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) - // result: (TESTQ (MOVQload [off] {sym} ptr mem) x) + // match: (SETB c:(CMPQconst [128] x)) + // cond: c.Uses == 1 + // result: (SETBE (CMPQconst [127] x)) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - a := v_0 - if a.Op != OpAMD64ANDQload { - continue - } - off := auxIntToInt32(a.AuxInt) - sym := auxToSym(a.Aux) - mem := a.Args[2] - x := a.Args[0] - ptr := a.Args[1] - if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { - continue - } - v.reset(OpAMD64TESTQ) - v0 := b.NewValue0(a.Pos, OpAMD64MOVQload, a.Type) - v0.AuxInt = int32ToAuxInt(off) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - v.AddArg2(v0, x) - return true + c := v_0 + if c.Op != OpAMD64CMPQconst || auxIntToInt32(c.AuxInt) != 128 { + break } - break + x := c.Args[0] + if !(c.Uses == 1) { + break + } + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(127) + v0.AddArg(x) + v.AddArg(v0) + return true } - return false -} -func rewriteValueAMD64_OpAMD64TESTQconst(v *Value) bool { - v_0 := v.Args[0] - // match: (TESTQconst [c] (MOVQconst [d])) - // cond: int64(c) == d && c == 0 - // result: (FlagEQ) + // match: (SETB c:(CMPLconst [128] x)) + // cond: c.Uses == 1 + // result: (SETBE (CMPLconst [127] x)) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + c := v_0 + if c.Op != OpAMD64CMPLconst || auxIntToInt32(c.AuxInt) != 128 { break } - d := auxIntToInt64(v_0.AuxInt) - if !(int64(c) == d && c == 0) { + x := c.Args[0] + if !(c.Uses == 1) { break } - v.reset(OpAMD64FlagEQ) + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(127) + v0.AddArg(x) + v.AddArg(v0) return true } - // match: (TESTQconst [c] (MOVQconst [d])) - // cond: int64(c) == d && c < 0 - // result: (FlagLT_UGT) + // match: (SETB (InvertFlags x)) + // result: (SETA x) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + if v_0.Op != OpAMD64InvertFlags { break } - d := auxIntToInt64(v_0.AuxInt) - if !(int64(c) == d && c < 0) { + x := v_0.Args[0] + v.reset(OpAMD64SETA) + v.AddArg(x) + return true + } + // match: (SETB (FlagEQ)) + // result: (MOVLconst [0]) + for { + if v_0.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64FlagLT_UGT) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (TESTQconst [c] (MOVQconst [d])) - // cond: int64(c) == d && c > 0 - // result: (FlagGT_UGT) + // match: (SETB (FlagLT_ULT)) + // result: (MOVLconst [1]) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + if v_0.Op != OpAMD64FlagLT_ULT { break } - d := auxIntToInt64(v_0.AuxInt) - if !(int64(c) == d && c > 0) { + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) + return true + } + // match: (SETB (FlagLT_UGT)) + // result: (MOVLconst [0]) + for { + if v_0.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64FlagGT_UGT) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (TESTQconst [-1] x) - // cond: x.Op != OpAMD64MOVQconst - // result: (TESTQ x x) + // match: (SETB (FlagGT_ULT)) + // result: (MOVLconst [1]) for { - if auxIntToInt32(v.AuxInt) != -1 { + if v_0.Op != OpAMD64FlagGT_ULT { break } - x := v_0 - if !(x.Op != OpAMD64MOVQconst) { + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) + return true + } + // match: (SETB (FlagGT_UGT)) + // result: (MOVLconst [0]) + for { + if v_0.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64TESTQ) - v.AddArg2(x, x) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } return false } -func rewriteValueAMD64_OpAMD64TESTW(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64SETBE(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (TESTW (MOVLconst [c]) x) - // result: (TESTWconst [int16(c)] x) + // match: (SETBE (InvertFlags x)) + // result: (SETAE x) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64MOVLconst { - continue - } - c := auxIntToInt32(v_0.AuxInt) - x := v_1 - v.reset(OpAMD64TESTWconst) - v.AuxInt = int16ToAuxInt(int16(c)) - v.AddArg(x) - return true + if v_0.Op != OpAMD64InvertFlags { + break } - break + x := v_0.Args[0] + v.reset(OpAMD64SETAE) + v.AddArg(x) + return true } - // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) - // cond: l == l2 && l.Uses == 2 && clobber(l) - // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0, off)] ptr mem) + // match: (SETBE (FlagEQ)) + // result: (MOVLconst [1]) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - l := v_0 - if l.Op != OpAMD64MOVWload { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - l2 := v_1 - if !(l == l2 && l.Uses == 2 && clobber(l)) { - continue - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) - v.copyOf(v0) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) - v0.Aux = symToAux(sym) - v0.AddArg2(ptr, mem) - return true + if v_0.Op != OpAMD64FlagEQ { + break } - break + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) + return true } - return false -} -func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { - v_0 := v.Args[0] - // match: (TESTWconst [-1] x) - // cond: x.Op != OpAMD64MOVLconst - // result: (TESTW x x) + // match: (SETBE (FlagLT_ULT)) + // result: (MOVLconst [1]) for { - if auxIntToInt16(v.AuxInt) != -1 { + if v_0.Op != OpAMD64FlagLT_ULT { break } - x := v_0 - if !(x.Op != OpAMD64MOVLconst) { + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) + return true + } + // match: (SETBE (FlagLT_UGT)) + // result: (MOVLconst [0]) + for { + if v_0.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64TESTW) - v.AddArg2(x, x) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - return false -} -func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (XADDLlock [off1+off2] {sym} val ptr mem) + // match: (SETBE (FlagGT_ULT)) + // result: (MOVLconst [1]) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64FlagGT_ULT { break } - off2 := auxIntToInt32(v_1.AuxInt) - ptr := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) + return true + } + // match: (SETBE (FlagGT_UGT)) + // result: (MOVLconst [0]) + for { + if v_0.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64XADDLlock) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(val, ptr, mem) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } return false } -func rewriteValueAMD64_OpAMD64XADDQlock(v *Value) bool { +func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (XADDQlock [off1+off2] {sym} val ptr mem) + b := v.Block + typ := &b.Func.Config.Types + // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) + // result: (SETAEstore [off] {sym} ptr x mem) for { - off1 := auxIntToInt32(v.AuxInt) + off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + ptr := v_0 + if v_1.Op != OpAMD64InvertFlags { break } - off2 := auxIntToInt32(v_1.AuxInt) - ptr := v_1.Args[0] + x := v_1.Args[0] mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break - } - v.reset(OpAMD64XADDQlock) - v.AuxInt = int32ToAuxInt(off1 + off2) + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v.AddArg3(val, ptr, mem) + v.AddArg3(ptr, x, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) + // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) - // result: (XCHGL [off1+off2] {sym} val ptr mem) + // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64ADDQconst { break } - off2 := auxIntToInt32(v_1.AuxInt) - ptr := v_1.Args[0] + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64XCHGL) + v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) - v.AddArg3(val, ptr, mem) + v.AddArg3(base, val, mem) return true } - // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB - // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) + // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64LEAQ { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - ptr := v_1.Args[0] + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64XCHGL) + v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, ptr, mem) + v.AddArg3(base, val, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (XCHGQ [off1+off2] {sym} val ptr mem) + // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - off1 := auxIntToInt32(v.AuxInt) + off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + ptr := v_0 + if v_1.Op != OpAMD64FlagEQ { break } - off2 := auxIntToInt32(v_1.AuxInt) - ptr := v_1.Args[0] mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break - } - v.reset(OpAMD64XCHGQ) - v.AuxInt = int32ToAuxInt(off1 + off2) + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) - v.AddArg3(val, ptr, mem) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } - // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB - // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) + // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_ULT { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - ptr := v_1.Args[0] mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { - break - } - v.reset(OpAMD64XCHGQ) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, ptr, mem) + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64XORL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (XORL (SHLL (MOVLconst [1]) y) x) - // result: (BTCL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTCL) - v.AddArg2(x, y) - return true - } - break - } - // match: (XORL x (MOVLconst [c])) - // result: (XORLconst [c] x) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - continue - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64XORLconst) - v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (XORL x x) - // result: (MOVLconst [0]) + // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - x := v_0 - if x != v_1 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(0) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (XORLload x [off] {sym} ptr mem) + // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVLload { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - continue - } - v.reset(OpAMD64XORLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_ULT { + break } - break + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) + return true } - // match: (XORL x (ADDLconst [-1] x)) - // cond: buildcfg.GOAMD64 >= 3 - // result: (BLSMSKL x) + // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { - continue - } - v.reset(OpAMD64BLSMSKL) - v.AddArg(x) - return true + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_UGT { + break } - break + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) + return true } return false } -func rewriteValueAMD64_OpAMD64XORLconst(v *Value) bool { +func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (XORLconst [1] (SETNE x)) - // result: (SETEQ x) + b := v.Block + typ := &b.Func.Config.Types + // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) + // result: (SETAstore [off] {sym} ptr x mem) for { - if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETNE { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64InvertFlags { break } - x := v_0.Args[0] - v.reset(OpAMD64SETEQ) - v.AddArg(x) + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64SETAstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (XORLconst [1] (SETEQ x)) - // result: (SETNE x) + // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SETBstore [off1+off2] {sym} base val mem) for { - if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETEQ { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - x := v_0.Args[0] - v.reset(OpAMD64SETNE) - v.AddArg(x) + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) return true } - // match: (XORLconst [1] (SETL x)) - // result: (SETGE x) + // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETL { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - x := v_0.Args[0] - v.reset(OpAMD64SETGE) - v.AddArg(x) + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (XORLconst [1] (SETGE x)) - // result: (SETL x) + // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETGE { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagEQ { break } - x := v_0.Args[0] - v.reset(OpAMD64SETL) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - // match: (XORLconst [1] (SETLE x)) - // result: (SETG x) + // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETLE { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_ULT { break } - x := v_0.Args[0] - v.reset(OpAMD64SETG) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } - // match: (XORLconst [1] (SETG x)) - // result: (SETLE x) + // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETG { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_UGT { break } - x := v_0.Args[0] - v.reset(OpAMD64SETLE) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - // match: (XORLconst [1] (SETB x)) - // result: (SETAE x) + // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETB { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_ULT { break } - x := v_0.Args[0] - v.reset(OpAMD64SETAE) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } - // match: (XORLconst [1] (SETAE x)) - // result: (SETB x) + // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETAE { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_UGT { break } - x := v_0.Args[0] - v.reset(OpAMD64SETB) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - // match: (XORLconst [1] (SETBE x)) - // result: (SETA x) + return false +} +func rewriteValueAMD64_OpAMD64SETEQ(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) + // result: (SETAE (BTL x y)) for { - if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETBE { + if v_0.Op != OpAMD64TESTL { break } - x := v_0.Args[0] - v.reset(OpAMD64SETA) - v.AddArg(x) - return true - } - // match: (XORLconst [1] (SETA x)) - // result: (SETBE x) - for { - if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETA { - break - } - x := v_0.Args[0] - v.reset(OpAMD64SETBE) - v.AddArg(x) - return true - } - // match: (XORLconst [c] (XORLconst [d] x)) - // result: (XORLconst [c ^ d] x) - for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64XORLconst { - break + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true } - d := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64XORLconst) - v.AuxInt = int32ToAuxInt(c ^ d) - v.AddArg(x) - return true + break } - // match: (XORLconst [c] x) - // cond: c==0 - // result: x + // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) + // result: (SETAE (BTQ x y)) for { - c := auxIntToInt32(v.AuxInt) - x := v_0 - if !(c == 0) { + if v_0.Op != OpAMD64TESTQ { break } - v.copyOf(x) - return true - } - // match: (XORLconst [c] (MOVLconst [d])) - // result: (MOVLconst [c^d]) - for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVLconst { - break + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true } - d := auxIntToInt32(v_0.AuxInt) - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(c ^ d) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64XORLconstmodify(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (XORLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) - // result: (XORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) + // match: (SETEQ (TESTLconst [c] x)) + // cond: isPowerOfTwo(uint32(c)) + // result: (SETAE (BTLconst [int8(log32u(uint32(c)))] x)) for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64TESTLconst { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2)) { + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(isPowerOfTwo(uint32(c))) { break } - v.reset(OpAMD64XORLconstmodify) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(sym) - v.AddArg2(base, mem) + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) + v.AddArg(v0) return true } - // match: (XORLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (XORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) + // match: (SETEQ (TESTQconst [c] x)) + // cond: isPowerOfTwo(uint64(c)) + // result: (SETAE (BTQconst [int8(log32u(uint32(c)))] x)) for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64TESTQconst { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(isPowerOfTwo(uint64(c))) { break } - v.reset(OpAMD64XORLconstmodify) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) + v.AddArg(v0) return true } - return false -} -func rewriteValueAMD64_OpAMD64XORLload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (XORLload [off1] {sym} val (ADDQconst [off2] base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (XORLload [off1+off2] {sym} val base mem) + // match: (SETEQ (TESTQ (MOVQconst [c]) x)) + // cond: isPowerOfTwo(uint64(c)) + // result: (SETAE (BTQconst [int8(log64u(uint64(c)))] x)) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := auxIntToInt64(v_0_0.AuxInt) + x := v_0_1 + if !(isPowerOfTwo(uint64(c))) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64XORLload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) - return true + break } - // match: (XORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (XORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) + // result: (SETNE (CMPLconst [0] s)) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + s := v_0.Args[0] + if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } - v.reset(OpAMD64XORLload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(s) + v.AddArg(v0) return true } - // match: (XORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) - // result: (XORL x (MOVLf2i y)) + // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) + // result: (SETNE (CMPQconst [0] s)) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - x := v_0 - ptr := v_1 - if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { + if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } - y := v_2.Args[1] - if ptr != v_2.Args[0] { + s := v_0.Args[0] + if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } - v.reset(OpAMD64XORL) - v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) - v0.AddArg(y) - v.AddArg2(x, v0) + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(s) + v.AddArg(v0) return true } - return false -} -func rewriteValueAMD64_OpAMD64XORLmodify(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (XORLmodify [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (XORLmodify [off1+off2] {sym} base val mem) + // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) + // cond: z1==z2 + // result: (SETAE (BTQconst [63] x)) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64TESTQ { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { - break + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64XORLmodify) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) - return true + break } - // match: (XORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (XORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) + // cond: z1==z2 + // result: (SETAE (BTQconst [31] x)) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { - break - } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + if v_0.Op != OpAMD64TESTL { break } - v.reset(OpAMD64XORLmodify) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64XORQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (XORQ (SHLQ (MOVQconst [1]) y) x) - // result: (BTCQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQ { + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } - x := v_1 - v.reset(OpAMD64BTCQ) - v.AddArg2(x, y) + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + v.AddArg(v0) return true } break } - // match: (XORQ (MOVQconst [c]) x) - // cond: isUnsignedPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31 - // result: (BTCQconst [int8(log64u(uint64(c)))] x) + // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) + // cond: z1==z2 + // result: (SETAE (BTQconst [0] x)) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64MOVQconst { + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } - c := auxIntToInt64(v_0.AuxInt) - x := v_1 - if !(isUnsignedPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31) { + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } - v.reset(OpAMD64BTCQconst) - v.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) - v.AddArg(x) + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + v.AddArg(v0) return true } break } - // match: (XORQ x (MOVQconst [c])) - // cond: is32Bit(c) - // result: (XORQconst [int32(c)] x) + // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) + // cond: z1==z2 + // result: (SETAE (BTLconst [0] x)) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { + if v_0.Op != OpAMD64TESTL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } - c := auxIntToInt64(v_1.AuxInt) - if !(is32Bit(c)) { + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } - v.reset(OpAMD64XORQconst) - v.AuxInt = int32ToAuxInt(int32(c)) - v.AddArg(x) + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + v.AddArg(v0) return true } break } - // match: (XORQ x x) - // result: (MOVQconst [0]) + // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) + // cond: z1==z2 + // result: (SETAE (BTQconst [63] x)) for { - x := v_0 - if x != v_1 { + if v_0.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(0) - return true - } - // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (XORQload x [off] {sym} ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64MOVQload { + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + x := z1.Args[0] + z2 := v_0_1 + if !(z1 == z2) { continue } - v.reset(OpAMD64XORQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + v.AddArg(v0) return true } break } - // match: (XORQ x (ADDQconst [-1] x)) - // cond: buildcfg.GOAMD64 >= 3 - // result: (BLSMSKQ x) + // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) + // cond: z1==z2 + // result: (SETAE (BTLconst [31] x)) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { + if v_0.Op != OpAMD64TESTL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } - v.reset(OpAMD64BLSMSKQ) - v.AddArg(x) + x := z1.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + v.AddArg(v0) return true } break } - return false -} -func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool { - v_0 := v.Args[0] - // match: (XORQconst [c] (XORQconst [d] x)) - // result: (XORQconst [c ^ d] x) + // match: (SETEQ (InvertFlags x)) + // result: (SETEQ x) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64XORQconst { + if v_0.Op != OpAMD64InvertFlags { break } - d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] - v.reset(OpAMD64XORQconst) - v.AuxInt = int32ToAuxInt(c ^ d) + v.reset(OpAMD64SETEQ) v.AddArg(x) return true } - // match: (XORQconst [0] x) - // result: x + // match: (SETEQ (FlagEQ)) + // result: (MOVLconst [1]) for { - if auxIntToInt32(v.AuxInt) != 0 { + if v_0.Op != OpAMD64FlagEQ { break } - x := v_0 - v.copyOf(x) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } - // match: (XORQconst [c] (MOVQconst [d])) - // result: (MOVQconst [int64(c)^d]) + // match: (SETEQ (FlagLT_ULT)) + // result: (MOVLconst [0]) for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpAMD64MOVQconst { + if v_0.Op != OpAMD64FlagLT_ULT { break } - d := auxIntToInt64(v_0.AuxInt) - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(int64(c) ^ d) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - return false -} -func rewriteValueAMD64_OpAMD64XORQconstmodify(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (XORQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) - // result: (XORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) + // match: (SETEQ (FlagLT_UGT)) + // result: (MOVLconst [0]) for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64FlagLT_UGT { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2)) { + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) + return true + } + // match: (SETEQ (FlagGT_ULT)) + // result: (MOVLconst [0]) + for { + if v_0.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64XORQconstmodify) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(sym) - v.AddArg2(base, mem) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (XORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) - // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) - // result: (XORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) + // match: (SETEQ (FlagGT_UGT)) + // result: (MOVLconst [0]) for { - valoff1 := auxIntToValAndOff(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64FlagGT_UGT { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - mem := v_1 - if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) + return true + } + // match: (SETEQ (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) + // result: (SETEQ (Select1 blsr)) + for { + if v_0.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64XORQconstmodify) - v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg2(base, mem) - return true + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + s := v_0_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { + continue + } + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + v.AddArg(v0) + return true + } + break } - return false -} -func rewriteValueAMD64_OpAMD64XORQload(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (XORQload [off1] {sym} val (ADDQconst [off2] base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (XORQload [off1+off2] {sym} val base mem) + // match: (SETEQ (TESTL s:(Select0 blsr:(BLSRL _)) s)) + // result: (SETEQ (Select1 blsr)) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64TESTL { break } - off2 := auxIntToInt32(v_1.AuxInt) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + s := v_0_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRL || s != v_0_1 { + continue + } + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + v.AddArg(v0) + return true + } + break + } + // match: (SETEQ (VPTEST x:(VPAND128 j k) y)) + // cond: x == y && x.Uses == 2 + // result: (SETEQ (VPTEST j k)) + for { + if v_0.Op != OpAMD64VPTEST { break } - v.reset(OpAMD64XORQload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(val, base, mem) + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPAND128 { + break + } + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(j, k) + v.AddArg(v0) return true } - // match: (XORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (XORQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + // match: (SETEQ (VPTEST x:(VPAND256 j k) y)) + // cond: x == y && x.Uses == 2 + // result: (SETEQ (VPTEST j k)) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - val := v_0 - if v_1.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64VPTEST { break } - off2 := auxIntToInt32(v_1.AuxInt) - sym2 := auxToSym(v_1.Aux) - base := v_1.Args[0] - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPAND256 { break } - v.reset(OpAMD64XORQload) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(val, base, mem) + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(j, k) + v.AddArg(v0) return true } - // match: (XORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) - // result: (XORQ x (MOVQf2i y)) + // match: (SETEQ (VPTEST x:(VPANDD512 j k) y)) + // cond: x == y && x.Uses == 2 + // result: (SETEQ (VPTEST j k)) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - x := v_0 - ptr := v_1 - if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { + if v_0.Op != OpAMD64VPTEST { break } - y := v_2.Args[1] - if ptr != v_2.Args[0] { + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDD512 { break } - v.reset(OpAMD64XORQ) - v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) - v0.AddArg(y) - v.AddArg2(x, v0) + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(j, k) + v.AddArg(v0) return true } - return false -} -func rewriteValueAMD64_OpAMD64XORQmodify(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (XORQmodify [off1] {sym} (ADDQconst [off2] base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) - // result: (XORQmodify [off1+off2] {sym} base val mem) + // match: (SETEQ (VPTEST x:(VPANDQ512 j k) y)) + // cond: x == y && x.Uses == 2 + // result: (SETEQ (VPTEST j k)) for { - off1 := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpAMD64ADDQconst { + if v_0.Op != OpAMD64VPTEST { break } - off2 := auxIntToInt32(v_0.AuxInt) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1) + int64(off2))) { + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDQ512 { break } - v.reset(OpAMD64XORQmodify) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(sym) - v.AddArg3(base, val, mem) + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(j, k) + v.AddArg(v0) return true } - // match: (XORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) - // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) - // result: (XORQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) + // match: (SETEQ (VPTEST x:(VPANDN128 j k) y)) + // cond: x == y && x.Uses == 2 + // result: (SETB (VPTEST k j)) for { - off1 := auxIntToInt32(v.AuxInt) - sym1 := auxToSym(v.Aux) - if v_0.Op != OpAMD64LEAQ { + if v_0.Op != OpAMD64VPTEST { break } - off2 := auxIntToInt32(v_0.AuxInt) - sym2 := auxToSym(v_0.Aux) - base := v_0.Args[0] - val := v_1 - mem := v_2 - if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDN128 { break } - v.reset(OpAMD64XORQmodify) - v.AuxInt = int32ToAuxInt(off1 + off2) - v.Aux = symToAux(mergeSym(sym1, sym2)) - v.AddArg3(base, val, mem) + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(k, j) + v.AddArg(v0) return true } - return false -} -func rewriteValueAMD64_OpAddr(v *Value) bool { - v_0 := v.Args[0] - // match: (Addr {sym} base) - // result: (LEAQ {sym} base) + // match: (SETEQ (VPTEST x:(VPANDN256 j k) y)) + // cond: x == y && x.Uses == 2 + // result: (SETB (VPTEST k j)) for { - sym := auxToSym(v.Aux) - base := v_0 - v.reset(OpAMD64LEAQ) - v.Aux = symToAux(sym) - v.AddArg(base) + if v_0.Op != OpAMD64VPTEST { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDN256 { + break + } + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(k, j) + v.AddArg(v0) return true } -} -func rewriteValueAMD64_OpAtomicAdd32(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (AtomicAdd32 ptr val mem) - // result: (AddTupleFirst32 val (XADDLlock val ptr mem)) + // match: (SETEQ (VPTEST x:(VPANDND512 j k) y)) + // cond: x == y && x.Uses == 2 + // result: (SETB (VPTEST k j)) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64AddTupleFirst32) - v0 := b.NewValue0(v.Pos, OpAMD64XADDLlock, types.NewTuple(typ.UInt32, types.TypeMem)) - v0.AddArg3(val, ptr, mem) - v.AddArg2(val, v0) + if v_0.Op != OpAMD64VPTEST { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDND512 { + break + } + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(k, j) + v.AddArg(v0) return true } -} -func rewriteValueAMD64_OpAtomicAdd64(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (AtomicAdd64 ptr val mem) - // result: (AddTupleFirst64 val (XADDQlock val ptr mem)) + // match: (SETEQ (VPTEST x:(VPANDNQ512 j k) y)) + // cond: x == y && x.Uses == 2 + // result: (SETB (VPTEST k j)) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64AddTupleFirst64) - v0 := b.NewValue0(v.Pos, OpAMD64XADDQlock, types.NewTuple(typ.UInt64, types.TypeMem)) - v0.AddArg3(val, ptr, mem) - v.AddArg2(val, v0) + if v_0.Op != OpAMD64VPTEST { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDNQ512 { + break + } + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(k, j) + v.AddArg(v0) return true } -} -func rewriteValueAMD64_OpAtomicAnd32(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicAnd32 ptr val mem) - // result: (ANDLlock ptr val mem) + // match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (SETNE flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64ANDLlock) - v.AddArg3(ptr, val, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTQ { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETNE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicAnd32value(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicAnd32value ptr val mem) - // result: (LoweredAtomicAnd32 ptr val mem) + // match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (SETEQ flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64LoweredAtomicAnd32) - v.AddArg3(ptr, val, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTQ { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETEQ) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicAnd64value(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicAnd64value ptr val mem) - // result: (LoweredAtomicAnd64 ptr val mem) + // match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (SETGE flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64LoweredAtomicAnd64) - v.AddArg3(ptr, val, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTQ { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETGE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicAnd8(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicAnd8 ptr val mem) - // result: (ANDBlock ptr val mem) + // match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (SETLE flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64ANDBlock) - v.AddArg3(ptr, val, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTQ { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETLE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicCompareAndSwap32(v *Value) bool { - v_3 := v.Args[3] - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicCompareAndSwap32 ptr old new_ mem) - // result: (CMPXCHGLlock ptr old new_ mem) + // match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (SETG flags) for { - ptr := v_0 - old := v_1 - new_ := v_2 - mem := v_3 - v.reset(OpAMD64CMPXCHGLlock) - v.AddArg4(ptr, old, new_, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTQ { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETG) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicCompareAndSwap64(v *Value) bool { - v_3 := v.Args[3] - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicCompareAndSwap64 ptr old new_ mem) - // result: (CMPXCHGQlock ptr old new_ mem) + // match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (SETL flags) for { - ptr := v_0 - old := v_1 - new_ := v_2 - mem := v_3 - v.reset(OpAMD64CMPXCHGQlock) - v.AddArg4(ptr, old, new_, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTQ { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETL) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicExchange32(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicExchange32 ptr val mem) - // result: (XCHGL val ptr mem) + // match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (SETBE flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64XCHGL) - v.AddArg3(val, ptr, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTQ { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETBE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicExchange64(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicExchange64 ptr val mem) - // result: (XCHGQ val ptr mem) + // match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (SETAE flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64XCHGQ) - v.AddArg3(val, ptr, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTQ { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETAE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicExchange8(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicExchange8 ptr val mem) - // result: (XCHGB val ptr mem) + // match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (SETB flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64XCHGB) - v.AddArg3(val, ptr, mem) - return true - } -} -func rewriteValueAMD64_OpAtomicLoad32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicLoad32 ptr mem) - // result: (MOVLatomicload ptr mem) - for { - ptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVLatomicload) - v.AddArg2(ptr, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTQ { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETB) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicLoad64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicLoad64 ptr mem) - // result: (MOVQatomicload ptr mem) + // match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (SETA flags) for { - ptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVQatomicload) - v.AddArg2(ptr, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTQ { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETA) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicLoad8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicLoad8 ptr mem) - // result: (MOVBatomicload ptr mem) + // match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (SETNE flags) for { - ptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVBatomicload) - v.AddArg2(ptr, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTL { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETNE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicLoadPtr(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicLoadPtr ptr mem) - // result: (MOVQatomicload ptr mem) + // match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (SETEQ flags) for { - ptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVQatomicload) - v.AddArg2(ptr, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTL { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETEQ) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicOr32(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicOr32 ptr val mem) - // result: (ORLlock ptr val mem) + // match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (SETGE flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64ORLlock) - v.AddArg3(ptr, val, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTL { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETGE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicOr32value(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicOr32value ptr val mem) - // result: (LoweredAtomicOr32 ptr val mem) + // match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (SETLE flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64LoweredAtomicOr32) - v.AddArg3(ptr, val, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTL { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETLE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicOr64value(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicOr64value ptr val mem) - // result: (LoweredAtomicOr64 ptr val mem) + // match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (SETG flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64LoweredAtomicOr64) - v.AddArg3(ptr, val, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTL { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETG) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicOr8(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (AtomicOr8 ptr val mem) - // result: (ORBlock ptr val mem) + // match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (SETL flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpAMD64ORBlock) - v.AddArg3(ptr, val, mem) - return true + t := v_0 + if t.Op != OpAMD64TESTL { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETL) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicStore32(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (AtomicStore32 ptr val mem) - // result: (Select1 (XCHGL val ptr mem)) + // match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (SETBE flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) - v0.AddArg3(val, ptr, mem) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTL { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETBE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicStore64(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (AtomicStore64 ptr val mem) - // result: (Select1 (XCHGQ val ptr mem)) + // match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (SETAE flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) - v0.AddArg3(val, ptr, mem) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTL { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETAE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicStore8(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (AtomicStore8 ptr val mem) - // result: (Select1 (XCHGB val ptr mem)) + // match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (SETB flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) - v0.AddArg3(val, ptr, mem) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTL { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETB) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (AtomicStorePtrNoWB ptr val mem) - // result: (Select1 (XCHGQ val ptr mem)) + // match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (SETA flags) for { - ptr := v_0 - val := v_1 - mem := v_2 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) - v0.AddArg3(val, ptr, mem) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTL { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETA) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpBitLen16(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (BitLen16 x) - // cond: buildcfg.GOAMD64 < 3 - // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) + // match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: (SETNE flags) for { - x := v_0 - if !(buildcfg.GOAMD64 < 3) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64BSRL) - v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) - v0.AuxInt = int32ToAuxInt(1) - v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) - v1.AddArg(x) - v0.AddArg2(v1, v1) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETNE) + v.AddArg(flags) + return true + } + break } - // match: (BitLen16 x) - // cond: buildcfg.GOAMD64 >= 3 - // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVWQZX x)))) + // match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: (SETEQ flags) for { - t := v.Type - x := v_0 - if !(buildcfg.GOAMD64 >= 3) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64NEGQ) - v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) - v0.AuxInt = int32ToAuxInt(-32) - v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, x.Type) - v2.AddArg(x) - v1.AddArg(v2) - v0.AddArg(v1) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETEQ) + v.AddArg(flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpBitLen32(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (BitLen32 x) - // cond: buildcfg.GOAMD64 < 3 - // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) + // match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: (SETGE flags) for { - x := v_0 - if !(buildcfg.GOAMD64 < 3) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) - v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) - v1.AuxInt = int32ToAuxInt(1) - v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) - v2.AddArg(x) - v1.AddArg2(v2, v2) - v0.AddArg(v1) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETGE) + v.AddArg(flags) + return true + } + break } - // match: (BitLen32 x) - // cond: buildcfg.GOAMD64 >= 3 - // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) + // match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: (SETLE flags) for { - t := v.Type - x := v_0 - if !(buildcfg.GOAMD64 >= 3) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64NEGQ) - v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) - v0.AuxInt = int32ToAuxInt(-32) - v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) - v1.AddArg(x) - v0.AddArg(v1) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETLE) + v.AddArg(flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpBitLen64(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (BitLen64 x) - // cond: buildcfg.GOAMD64 < 3 - // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) + // match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: (SETG flags) for { - t := v.Type - x := v_0 - if !(buildcfg.GOAMD64 < 3) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64ADDQconst) - v.AuxInt = int32ToAuxInt(1) - v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) - v1 := b.NewValue0(v.Pos, OpSelect0, t) - v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) - v2.AddArg(x) - v1.AddArg(v2) - v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) - v3.AuxInt = int64ToAuxInt(-1) - v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v4.AddArg(v2) - v0.AddArg3(v1, v3, v4) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETG) + v.AddArg(flags) + return true + } + break } - // match: (BitLen64 x) - // cond: buildcfg.GOAMD64 >= 3 - // result: (NEGQ (ADDQconst [-64] (LZCNTQ x))) + // match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: (SETL flags) for { - t := v.Type - x := v_0 - if !(buildcfg.GOAMD64 >= 3) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64NEGQ) - v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) - v0.AuxInt = int32ToAuxInt(-64) - v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64) - v1.AddArg(x) - v0.AddArg(v1) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETL) + v.AddArg(flags) + return true + } + break } - return false -} -func rewriteValueAMD64_OpBitLen8(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (BitLen8 x) - // cond: buildcfg.GOAMD64 < 3 - // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) + // match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: (SETBE flags) for { - x := v_0 - if !(buildcfg.GOAMD64 < 3) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64BSRL) - v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) - v0.AuxInt = int32ToAuxInt(1) - v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) - v1.AddArg(x) - v0.AddArg2(v1, v1) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETBE) + v.AddArg(flags) + return true + } + break } - // match: (BitLen8 x) - // cond: buildcfg.GOAMD64 >= 3 - // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVBQZX x)))) + // match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: (SETAE flags) for { - t := v.Type - x := v_0 - if !(buildcfg.GOAMD64 >= 3) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64NEGQ) - v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) - v0.AuxInt = int32ToAuxInt(-32) - v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, x.Type) - v2.AddArg(x) - v1.AddArg(v2) - v0.AddArg(v1) - v.AddArg(v0) - return true - } - return false -} -func rewriteValueAMD64_OpBswap16(v *Value) bool { - v_0 := v.Args[0] - // match: (Bswap16 x) - // result: (ROLWconst [8] x) - for { - x := v_0 - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(8) - v.AddArg(x) - return true - } -} -func rewriteValueAMD64_OpCeil(v *Value) bool { - v_0 := v.Args[0] - // match: (Ceil x) - // result: (ROUNDSD [2] x) - for { - x := v_0 - v.reset(OpAMD64ROUNDSD) - v.AuxInt = int8ToAuxInt(2) - v.AddArg(x) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETAE) + v.AddArg(flags) + return true + } + break } -} -func rewriteValueAMD64_OpCondSelect(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (CondSelect x y (SETEQ cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQEQ y x cond) + // match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: (SETB flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETEQ { + t := v_0 + if t.Op != OpAMD64TESTW { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETB) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQEQ) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETNE cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQNE y x cond) + // match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: (SETA flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETNE { + t := v_0 + if t.Op != OpAMD64TESTW { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETA) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQNE) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETL cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQLT y x cond) + // match: (SETEQ t:(TESTB s:(SETEQ flags) s)) + // cond: t.Block == s.Block + // result: (SETNE flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETL { + t := v_0 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETNE) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQLT) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETG cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQGT y x cond) + // match: (SETEQ t:(TESTB s:(SETNE flags) s)) + // cond: t.Block == s.Block + // result: (SETEQ flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETG { + t := v_0 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETEQ) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQGT) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETLE cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQLE y x cond) + // match: (SETEQ t:(TESTB s:(SETL flags) s)) + // cond: t.Block == s.Block + // result: (SETGE flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETLE { + t := v_0 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETGE) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQLE) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETGE cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQGE y x cond) + // match: (SETEQ t:(TESTB s:(SETG flags) s)) + // cond: t.Block == s.Block + // result: (SETLE flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETGE { + t := v_0 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETLE) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQGE) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETA cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQHI y x cond) + // match: (SETEQ t:(TESTB s:(SETLE flags) s)) + // cond: t.Block == s.Block + // result: (SETG flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETA { + t := v_0 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETG) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQHI) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETB cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQCS y x cond) + // match: (SETEQ t:(TESTB s:(SETGE flags) s)) + // cond: t.Block == s.Block + // result: (SETL flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETB { + t := v_0 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETL) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQCS) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETAE cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQCC y x cond) + // match: (SETEQ t:(TESTB s:(SETA flags) s)) + // cond: t.Block == s.Block + // result: (SETBE flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETAE { + t := v_0 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETBE) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQCC) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETBE cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQLS y x cond) + // match: (SETEQ t:(TESTB s:(SETB flags) s)) + // cond: t.Block == s.Block + // result: (SETAE flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETBE { + t := v_0 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETAE) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQLS) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETEQF cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQEQF y x cond) + // match: (SETEQ t:(TESTB s:(SETAE flags) s)) + // cond: t.Block == s.Block + // result: (SETB flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETEQF { + t := v_0 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETB) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQEQF) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETNEF cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQNEF y x cond) + // match: (SETEQ t:(TESTB s:(SETBE flags) s)) + // cond: t.Block == s.Block + // result: (SETA flags) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETNEF { + t := v_0 + if t.Op != OpAMD64TESTB { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.reset(OpAMD64SETA) + v.AddArg(flags) + return true } - v.reset(OpAMD64CMOVQNEF) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETGF cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQGTF y x cond) + return false +} +func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) + // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETGF { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLL { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true } - v.reset(OpAMD64CMOVQGTF) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETGEF cond)) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (CMOVQGEF y x cond) + // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) + // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETGEF { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - if !(is64BitInt(t) || isPtr(t)) { - break + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLQ { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true } - v.reset(OpAMD64CMOVQGEF) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETEQ cond)) - // cond: is32BitInt(t) - // result: (CMOVLEQ y x cond) + // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) + // cond: isPowerOfTwo(uint32(c)) + // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32u(uint32(c)))] x) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETEQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTLconst { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { + c := auxIntToInt32(v_1.AuxInt) + x := v_1.Args[0] + mem := v_2 + if !(isPowerOfTwo(uint32(c))) { break } - v.reset(OpAMD64CMOVLEQ) - v.AddArg3(y, x, cond) + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) return true } - // match: (CondSelect x y (SETNE cond)) - // cond: is32BitInt(t) - // result: (CMOVLNE y x cond) + // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) + // cond: isPowerOfTwo(uint64(c)) + // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log32u(uint32(c)))] x) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETNE { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQconst { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { + c := auxIntToInt32(v_1.AuxInt) + x := v_1.Args[0] + mem := v_2 + if !(isPowerOfTwo(uint64(c))) { break } - v.reset(OpAMD64CMOVLNE) - v.AddArg3(y, x, cond) + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) return true } - // match: (CondSelect x y (SETL cond)) - // cond: is32BitInt(t) - // result: (CMOVLLT y x cond) + // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) + // cond: isPowerOfTwo(uint64(c)) + // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log64u(uint64(c)))] x) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETL { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { - break + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64MOVQconst { + continue + } + c := auxIntToInt64(v_1_0.AuxInt) + x := v_1_1 + mem := v_2 + if !(isPowerOfTwo(uint64(c))) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true } - v.reset(OpAMD64CMOVLLT) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETG cond)) - // cond: is32BitInt(t) - // result: (CMOVLGT y x cond) + // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) + // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETG { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { + s := v_1.Args[0] + if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } - v.reset(OpAMD64CMOVLGT) - v.AddArg3(y, x, cond) + mem := v_2 + v.reset(OpAMD64SETNEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(s) + v.AddArg3(ptr, v0, mem) return true } - // match: (CondSelect x y (SETLE cond)) - // cond: is32BitInt(t) - // result: (CMOVLLE y x cond) + // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) + // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETLE { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { + s := v_1.Args[0] + if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } - v.reset(OpAMD64CMOVLLE) - v.AddArg3(y, x, cond) + mem := v_2 + v.reset(OpAMD64SETNEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(s) + v.AddArg3(ptr, v0, mem) return true } - // match: (CondSelect x y (SETGE cond)) - // cond: is32BitInt(t) - // result: (CMOVLGE y x cond) + // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) + // cond: z1==z2 + // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETGE { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { - break + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true } - v.reset(OpAMD64CMOVLGE) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETA cond)) - // cond: is32BitInt(t) - // result: (CMOVLHI y x cond) + // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) + // cond: z1==z2 + // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETA { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { - break + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true } - v.reset(OpAMD64CMOVLHI) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETB cond)) - // cond: is32BitInt(t) - // result: (CMOVLCS y x cond) + // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) + // cond: z1==z2 + // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETB { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { - break + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true } - v.reset(OpAMD64CMOVLCS) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETAE cond)) - // cond: is32BitInt(t) - // result: (CMOVLCC y x cond) + // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) + // cond: z1==z2 + // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETAE { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { - break + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true } - v.reset(OpAMD64CMOVLCC) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETBE cond)) - // cond: is32BitInt(t) - // result: (CMOVLLS y x cond) + // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) + // cond: z1==z2 + // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETBE { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { - break + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + x := z1.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true } - v.reset(OpAMD64CMOVLLS) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETEQF cond)) - // cond: is32BitInt(t) - // result: (CMOVLEQF y x cond) + // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) + // cond: z1==z2 + // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETEQF { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { - break + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + x := z1.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true } - v.reset(OpAMD64CMOVLEQF) - v.AddArg3(y, x, cond) - return true + break } - // match: (CondSelect x y (SETNEF cond)) - // cond: is32BitInt(t) - // result: (CMOVLNEF y x cond) + // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) + // result: (SETEQstore [off] {sym} ptr x mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETNEF { - break - } - cond := v_2.Args[0] - if !(is32BitInt(t)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64CMOVLNEF) - v.AddArg3(y, x, cond) + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64SETEQstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (CondSelect x y (SETGF cond)) - // cond: is32BitInt(t) - // result: (CMOVLGTF y x cond) + // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SETEQstore [off1+off2] {sym} base val mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETGF { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64CMOVLGTF) - v.AddArg3(y, x, cond) + v.reset(OpAMD64SETEQstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) return true } - // match: (CondSelect x y (SETGEF cond)) - // cond: is32BitInt(t) - // result: (CMOVLGEF y x cond) + // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETGEF { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - cond := v_2.Args[0] - if !(is32BitInt(t)) { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64CMOVLGEF) - v.AddArg3(y, x, cond) + v.reset(OpAMD64SETEQstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (CondSelect x y (SETEQ cond)) - // cond: is16BitInt(t) - // result: (CMOVWEQ y x cond) + // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETEQ { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagEQ { break } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) + return true + } + // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64CMOVWEQ) - v.AddArg3(y, x, cond) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - // match: (CondSelect x y (SETNE cond)) - // cond: is16BitInt(t) - // result: (CMOVWNE y x cond) + // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETNE { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_UGT { break } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) + return true + } + // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64CMOVWNE) - v.AddArg3(y, x, cond) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - // match: (CondSelect x y (SETL cond)) - // cond: is16BitInt(t) - // result: (CMOVWLT y x cond) + // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETL { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_UGT { break } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETG(v *Value) bool { + v_0 := v.Args[0] + // match: (SETG (InvertFlags x)) + // result: (SETL x) + for { + if v_0.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64CMOVWLT) - v.AddArg3(y, x, cond) + x := v_0.Args[0] + v.reset(OpAMD64SETL) + v.AddArg(x) return true } - // match: (CondSelect x y (SETG cond)) - // cond: is16BitInt(t) - // result: (CMOVWGT y x cond) + // match: (SETG (FlagEQ)) + // result: (MOVLconst [0]) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETG { + if v_0.Op != OpAMD64FlagEQ { break } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) + return true + } + // match: (SETG (FlagLT_ULT)) + // result: (MOVLconst [0]) + for { + if v_0.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64CMOVWGT) - v.AddArg3(y, x, cond) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (CondSelect x y (SETLE cond)) - // cond: is16BitInt(t) - // result: (CMOVWLE y x cond) + // match: (SETG (FlagLT_UGT)) + // result: (MOVLconst [0]) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETLE { + if v_0.Op != OpAMD64FlagLT_UGT { break } - cond := v_2.Args[0] - if !(is16BitInt(t)) { - break - } - v.reset(OpAMD64CMOVWLE) - v.AddArg3(y, x, cond) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (CondSelect x y (SETGE cond)) - // cond: is16BitInt(t) - // result: (CMOVWGE y x cond) + // match: (SETG (FlagGT_ULT)) + // result: (MOVLconst [1]) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETGE { - break - } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + if v_0.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64CMOVWGE) - v.AddArg3(y, x, cond) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } - // match: (CondSelect x y (SETA cond)) - // cond: is16BitInt(t) - // result: (CMOVWHI y x cond) + // match: (SETG (FlagGT_UGT)) + // result: (MOVLconst [1]) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETA { - break - } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + if v_0.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64CMOVWHI) - v.AddArg3(y, x, cond) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } - // match: (CondSelect x y (SETB cond)) - // cond: is16BitInt(t) - // result: (CMOVWCS y x cond) + return false +} +func rewriteValueAMD64_OpAMD64SETGE(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (SETGE c:(CMPQconst [128] x)) + // cond: c.Uses == 1 + // result: (SETG (CMPQconst [127] x)) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETB { + c := v_0 + if c.Op != OpAMD64CMPQconst || auxIntToInt32(c.AuxInt) != 128 { break } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + x := c.Args[0] + if !(c.Uses == 1) { break } - v.reset(OpAMD64CMOVWCS) - v.AddArg3(y, x, cond) + v.reset(OpAMD64SETG) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(127) + v0.AddArg(x) + v.AddArg(v0) return true } - // match: (CondSelect x y (SETAE cond)) - // cond: is16BitInt(t) - // result: (CMOVWCC y x cond) + // match: (SETGE c:(CMPLconst [128] x)) + // cond: c.Uses == 1 + // result: (SETG (CMPLconst [127] x)) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETAE { + c := v_0 + if c.Op != OpAMD64CMPLconst || auxIntToInt32(c.AuxInt) != 128 { break } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + x := c.Args[0] + if !(c.Uses == 1) { break } - v.reset(OpAMD64CMOVWCC) - v.AddArg3(y, x, cond) + v.reset(OpAMD64SETG) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(127) + v0.AddArg(x) + v.AddArg(v0) return true } - // match: (CondSelect x y (SETBE cond)) - // cond: is16BitInt(t) - // result: (CMOVWLS y x cond) + // match: (SETGE (InvertFlags x)) + // result: (SETLE x) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETBE { - break - } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + if v_0.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64CMOVWLS) - v.AddArg3(y, x, cond) + x := v_0.Args[0] + v.reset(OpAMD64SETLE) + v.AddArg(x) return true } - // match: (CondSelect x y (SETEQF cond)) - // cond: is16BitInt(t) - // result: (CMOVWEQF y x cond) + // match: (SETGE (FlagEQ)) + // result: (MOVLconst [1]) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETEQF { - break - } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + if v_0.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64CMOVWEQF) - v.AddArg3(y, x, cond) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } - // match: (CondSelect x y (SETNEF cond)) - // cond: is16BitInt(t) - // result: (CMOVWNEF y x cond) + // match: (SETGE (FlagLT_ULT)) + // result: (MOVLconst [0]) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETNEF { - break - } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + if v_0.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64CMOVWNEF) - v.AddArg3(y, x, cond) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (CondSelect x y (SETGF cond)) - // cond: is16BitInt(t) - // result: (CMOVWGTF y x cond) + // match: (SETGE (FlagLT_UGT)) + // result: (MOVLconst [0]) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETGF { - break - } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + if v_0.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64CMOVWGTF) - v.AddArg3(y, x, cond) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (CondSelect x y (SETGEF cond)) - // cond: is16BitInt(t) - // result: (CMOVWGEF y x cond) + // match: (SETGE (FlagGT_ULT)) + // result: (MOVLconst [1]) for { - t := v.Type - x := v_0 - y := v_1 - if v_2.Op != OpAMD64SETGEF { - break - } - cond := v_2.Args[0] - if !(is16BitInt(t)) { + if v_0.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64CMOVWGEF) - v.AddArg3(y, x, cond) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } - // match: (CondSelect x y check) - // cond: !check.Type.IsFlags() && check.Type.Size() == 1 - // result: (CondSelect x y (MOVBQZX check)) + // match: (SETGE (FlagGT_UGT)) + // result: (MOVLconst [1]) for { - t := v.Type - x := v_0 - y := v_1 - check := v_2 - if !(!check.Type.IsFlags() && check.Type.Size() == 1) { + if v_0.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpCondSelect) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) - v0.AddArg(check) - v.AddArg3(x, y, v0) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } - // match: (CondSelect x y check) - // cond: !check.Type.IsFlags() && check.Type.Size() == 2 - // result: (CondSelect x y (MOVWQZX check)) + return false +} +func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) + // result: (SETLEstore [off] {sym} ptr x mem) for { - t := v.Type - x := v_0 - y := v_1 - check := v_2 - if !(!check.Type.IsFlags() && check.Type.Size() == 2) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64InvertFlags { break } - v.reset(OpCondSelect) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) - v0.AddArg(check) - v.AddArg3(x, y, v0) + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64SETLEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (CondSelect x y check) - // cond: !check.Type.IsFlags() && check.Type.Size() == 4 - // result: (CondSelect x y (MOVLQZX check)) + // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SETGEstore [off1+off2] {sym} base val mem) for { - t := v.Type - x := v_0 - y := v_1 - check := v_2 - if !(!check.Type.IsFlags() && check.Type.Size() == 4) { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - v.reset(OpCondSelect) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) - v0.AddArg(check) - v.AddArg3(x, y, v0) + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64SETGEstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) return true } - // match: (CondSelect x y check) - // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) - // result: (CMOVQNE y x (CMPQconst [0] check)) + // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - t := v.Type - x := v_0 - y := v_1 - check := v_2 - if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - v.reset(OpAMD64CMOVQNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(check) - v.AddArg3(y, x, v0) + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64SETGEstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (CondSelect x y check) - // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) - // result: (CMOVLNE y x (CMPQconst [0] check)) + // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - t := v.Type - x := v_0 - y := v_1 - check := v_2 - if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64CMOVLNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(check) - v.AddArg3(y, x, v0) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } - // match: (CondSelect x y check) - // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) - // result: (CMOVWNE y x (CMPQconst [0] check)) + // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - t := v.Type - x := v_0 - y := v_1 - check := v_2 - if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64CMOVWNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) - v0.AddArg(check) - v.AddArg3(y, x, v0) - return true - } - return false -} -func rewriteValueAMD64_OpConst16(v *Value) bool { - // match: (Const16 [c]) - // result: (MOVLconst [int32(c)]) - for { - c := auxIntToInt16(v.AuxInt) - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(int32(c)) - return true - } -} -func rewriteValueAMD64_OpConst8(v *Value) bool { - // match: (Const8 [c]) - // result: (MOVLconst [int32(c)]) - for { - c := auxIntToInt8(v.AuxInt) - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(int32(c)) - return true - } -} -func rewriteValueAMD64_OpConstBool(v *Value) bool { - // match: (ConstBool [c]) - // result: (MOVLconst [b2i32(c)]) - for { - c := auxIntToBool(v.AuxInt) - v.reset(OpAMD64MOVLconst) - v.AuxInt = int32ToAuxInt(b2i32(c)) - return true - } -} -func rewriteValueAMD64_OpConstNil(v *Value) bool { - // match: (ConstNil ) - // result: (MOVQconst [0]) - for { - v.reset(OpAMD64MOVQconst) - v.AuxInt = int64ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpCtz16(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Ctz16 x) - // result: (BSFL (ORLconst [1<<16] x)) + // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - x := v_0 - v.reset(OpAMD64BSFL) - v0 := b.NewValue0(v.Pos, OpAMD64ORLconst, typ.UInt32) - v0.AuxInt = int32ToAuxInt(1 << 16) - v0.AddArg(x) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_UGT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool { - v_0 := v.Args[0] - // match: (Ctz16NonZero x) - // cond: buildcfg.GOAMD64 >= 3 - // result: (TZCNTL x) + // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - if !(buildcfg.GOAMD64 >= 3) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64TZCNTL) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } - // match: (Ctz16NonZero x) - // cond: buildcfg.GOAMD64 < 3 - // result: (BSFL x) + // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - if !(buildcfg.GOAMD64 < 3) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64BSFL) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } return false } -func rewriteValueAMD64_OpCtz32(v *Value) bool { +func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Ctz32 x) - // cond: buildcfg.GOAMD64 >= 3 - // result: (TZCNTL x) + // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) + // result: (SETLstore [off] {sym} ptr x mem) for { - x := v_0 - if !(buildcfg.GOAMD64 >= 3) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64TZCNTL) - v.AddArg(x) + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64SETLstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } - // match: (Ctz32 x) - // cond: buildcfg.GOAMD64 < 3 - // result: (Select0 (BSFQ (BTSQconst [32] x))) + // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SETGstore [off1+off2] {sym} base val mem) for { - x := v_0 - if !(buildcfg.GOAMD64 < 3) { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) - v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) - v1.AuxInt = int8ToAuxInt(32) - v1.AddArg(x) - v0.AddArg(v1) - v.AddArg(v0) + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64SETGstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) return true } - return false -} -func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool { - v_0 := v.Args[0] - // match: (Ctz32NonZero x) - // cond: buildcfg.GOAMD64 >= 3 - // result: (TZCNTL x) + // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - x := v_0 - if !(buildcfg.GOAMD64 >= 3) { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - v.reset(OpAMD64TZCNTL) - v.AddArg(x) + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64SETGstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } - // match: (Ctz32NonZero x) - // cond: buildcfg.GOAMD64 < 3 - // result: (BSFL x) + // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - x := v_0 - if !(buildcfg.GOAMD64 < 3) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64BSFL) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - return false -} -func rewriteValueAMD64_OpCtz64(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Ctz64 x) - // cond: buildcfg.GOAMD64 >= 3 - // result: (TZCNTQ x) + // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - x := v_0 - if !(buildcfg.GOAMD64 >= 3) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64TZCNTQ) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - // match: (Ctz64 x) - // cond: buildcfg.GOAMD64 < 3 - // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) + // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - t := v.Type - x := v_0 - if !(buildcfg.GOAMD64 < 3) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64CMOVQEQ) - v0 := b.NewValue0(v.Pos, OpSelect0, t) - v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v3.AddArg(v1) - v.AddArg3(v0, v2, v3) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - return false -} -func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Ctz64NonZero x) - // cond: buildcfg.GOAMD64 >= 3 - // result: (TZCNTQ x) + // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - if !(buildcfg.GOAMD64 >= 3) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64TZCNTQ) - v.AddArg(x) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } - // match: (Ctz64NonZero x) - // cond: buildcfg.GOAMD64 < 3 - // result: (Select0 (BSFQ x)) + // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - if !(buildcfg.GOAMD64 < 3) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) - v0.AddArg(x) - v.AddArg(v0) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } return false } -func rewriteValueAMD64_OpCtz8(v *Value) bool { +func rewriteValueAMD64_OpAMD64SETL(v *Value) bool { v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (Ctz8 x) - // result: (BSFL (ORLconst [1<<8 ] x)) + // match: (SETL c:(CMPQconst [128] x)) + // cond: c.Uses == 1 + // result: (SETLE (CMPQconst [127] x)) for { - x := v_0 - v.reset(OpAMD64BSFL) - v0 := b.NewValue0(v.Pos, OpAMD64ORLconst, typ.UInt32) - v0.AuxInt = int32ToAuxInt(1 << 8) + c := v_0 + if c.Op != OpAMD64CMPQconst || auxIntToInt32(c.AuxInt) != 128 { + break + } + x := c.Args[0] + if !(c.Uses == 1) { + break + } + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(127) v0.AddArg(x) v.AddArg(v0) return true } -} -func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { - v_0 := v.Args[0] - // match: (Ctz8NonZero x) - // cond: buildcfg.GOAMD64 >= 3 - // result: (TZCNTL x) + // match: (SETL c:(CMPLconst [128] x)) + // cond: c.Uses == 1 + // result: (SETLE (CMPLconst [127] x)) for { - x := v_0 - if !(buildcfg.GOAMD64 >= 3) { + c := v_0 + if c.Op != OpAMD64CMPLconst || auxIntToInt32(c.AuxInt) != 128 { break } - v.reset(OpAMD64TZCNTL) - v.AddArg(x) + x := c.Args[0] + if !(c.Uses == 1) { + break + } + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(127) + v0.AddArg(x) + v.AddArg(v0) return true } - // match: (Ctz8NonZero x) - // cond: buildcfg.GOAMD64 < 3 - // result: (BSFL x) + // match: (SETL (InvertFlags x)) + // result: (SETG x) for { - x := v_0 - if !(buildcfg.GOAMD64 < 3) { + if v_0.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64BSFL) + x := v_0.Args[0] + v.reset(OpAMD64SETG) v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpCvt32Fto32(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Cvt32Fto32 x) - // cond: base.ConvertHash.MatchPos(v.Pos, nil) - // result: (XORL y (SARLconst [31] (ANDL y:(CVTTSS2SL x) (NOTL (MOVLf2i x))))) + // match: (SETL (FlagEQ)) + // result: (MOVLconst [0]) for { - t := v.Type - x := v_0 - if !(base.ConvertHash.MatchPos(v.Pos, nil)) { + if v_0.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64XORL) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64SARLconst, t) - v0.AuxInt = int8ToAuxInt(31) - v1 := b.NewValue0(v.Pos, OpAMD64ANDL, t) - y := b.NewValue0(v.Pos, OpAMD64CVTTSS2SL, t) - y.AddArg(x) - v3 := b.NewValue0(v.Pos, OpAMD64NOTL, typ.Int32) - v4 := b.NewValue0(v.Pos, OpAMD64MOVLf2i, typ.UInt32) - v4.AddArg(x) - v3.AddArg(v4) - v1.AddArg2(y, v3) - v0.AddArg(v1) - v.AddArg2(y, v0) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (Cvt32Fto32 x) - // cond: !base.ConvertHash.MatchPos(v.Pos, nil) - // result: (CVTTSS2SL x) + // match: (SETL (FlagLT_ULT)) + // result: (MOVLconst [1]) for { - t := v.Type - x := v_0 - if !(!base.ConvertHash.MatchPos(v.Pos, nil)) { + if v_0.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64CVTTSS2SL) - v.Type = t - v.AddArg(x) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } - return false -} -func rewriteValueAMD64_OpCvt32Fto64(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Cvt32Fto64 x) - // cond: base.ConvertHash.MatchPos(v.Pos, nil) - // result: (XORQ y (SARQconst [63] (ANDQ y:(CVTTSS2SQ x) (NOTQ (MOVQf2i (CVTSS2SD x))) ))) + // match: (SETL (FlagLT_UGT)) + // result: (MOVLconst [1]) for { - t := v.Type - x := v_0 - if !(base.ConvertHash.MatchPos(v.Pos, nil)) { + if v_0.Op != OpAMD64FlagLT_UGT { break } - v.reset(OpAMD64XORQ) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64SARQconst, t) - v0.AuxInt = int8ToAuxInt(63) - v1 := b.NewValue0(v.Pos, OpAMD64ANDQ, t) - y := b.NewValue0(v.Pos, OpAMD64CVTTSS2SQ, t) - y.AddArg(x) - v3 := b.NewValue0(v.Pos, OpAMD64NOTQ, typ.Int64) - v4 := b.NewValue0(v.Pos, OpAMD64MOVQf2i, typ.UInt64) - v5 := b.NewValue0(v.Pos, OpAMD64CVTSS2SD, typ.Float64) - v5.AddArg(x) - v4.AddArg(v5) - v3.AddArg(v4) - v1.AddArg2(y, v3) - v0.AddArg(v1) - v.AddArg2(y, v0) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } - // match: (Cvt32Fto64 x) - // cond: !base.ConvertHash.MatchPos(v.Pos, nil) - // result: (CVTTSS2SQ x) + // match: (SETL (FlagGT_ULT)) + // result: (MOVLconst [0]) for { - t := v.Type - x := v_0 - if !(!base.ConvertHash.MatchPos(v.Pos, nil)) { + if v_0.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64CVTTSS2SQ) - v.Type = t - v.AddArg(x) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - return false -} -func rewriteValueAMD64_OpCvt64Fto32(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Cvt64Fto32 x) - // cond: base.ConvertHash.MatchPos(v.Pos, nil) - // result: (XORL y (SARLconst [31] (ANDL y:(CVTTSD2SL x) (NOTL (MOVLf2i (CVTSD2SS x)))))) + // match: (SETL (FlagGT_UGT)) + // result: (MOVLconst [0]) for { - t := v.Type - x := v_0 - if !(base.ConvertHash.MatchPos(v.Pos, nil)) { + if v_0.Op != OpAMD64FlagGT_UGT { break } - v.reset(OpAMD64XORL) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64SARLconst, t) - v0.AuxInt = int8ToAuxInt(31) - v1 := b.NewValue0(v.Pos, OpAMD64ANDL, t) - y := b.NewValue0(v.Pos, OpAMD64CVTTSD2SL, t) - y.AddArg(x) - v3 := b.NewValue0(v.Pos, OpAMD64NOTL, typ.Int32) - v4 := b.NewValue0(v.Pos, OpAMD64MOVLf2i, typ.UInt32) - v5 := b.NewValue0(v.Pos, OpAMD64CVTSD2SS, typ.Float32) - v5.AddArg(x) - v4.AddArg(v5) - v3.AddArg(v4) - v1.AddArg2(y, v3) - v0.AddArg(v1) - v.AddArg2(y, v0) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (Cvt64Fto32 x) - // cond: !base.ConvertHash.MatchPos(v.Pos, nil) - // result: (CVTTSD2SL x) + return false +} +func rewriteValueAMD64_OpAMD64SETLE(v *Value) bool { + v_0 := v.Args[0] + // match: (SETLE (InvertFlags x)) + // result: (SETGE x) for { - t := v.Type - x := v_0 - if !(!base.ConvertHash.MatchPos(v.Pos, nil)) { + if v_0.Op != OpAMD64InvertFlags { break } - v.reset(OpAMD64CVTTSD2SL) - v.Type = t + x := v_0.Args[0] + v.reset(OpAMD64SETGE) v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpCvt64Fto64(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Cvt64Fto64 x) - // cond: base.ConvertHash.MatchPos(v.Pos, nil) - // result: (XORQ y (SARQconst [63] (ANDQ y:(CVTTSD2SQ x) (NOTQ (MOVQf2i x))))) + // match: (SETLE (FlagEQ)) + // result: (MOVLconst [1]) for { - t := v.Type - x := v_0 - if !(base.ConvertHash.MatchPos(v.Pos, nil)) { + if v_0.Op != OpAMD64FlagEQ { break } - v.reset(OpAMD64XORQ) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64SARQconst, t) - v0.AuxInt = int8ToAuxInt(63) - v1 := b.NewValue0(v.Pos, OpAMD64ANDQ, t) - y := b.NewValue0(v.Pos, OpAMD64CVTTSD2SQ, t) - y.AddArg(x) - v3 := b.NewValue0(v.Pos, OpAMD64NOTQ, typ.Int64) - v4 := b.NewValue0(v.Pos, OpAMD64MOVQf2i, typ.UInt64) - v4.AddArg(x) - v3.AddArg(v4) - v1.AddArg2(y, v3) - v0.AddArg(v1) - v.AddArg2(y, v0) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } - // match: (Cvt64Fto64 x) - // cond: !base.ConvertHash.MatchPos(v.Pos, nil) - // result: (CVTTSD2SQ x) + // match: (SETLE (FlagLT_ULT)) + // result: (MOVLconst [1]) for { - t := v.Type - x := v_0 - if !(!base.ConvertHash.MatchPos(v.Pos, nil)) { + if v_0.Op != OpAMD64FlagLT_ULT { break } - v.reset(OpAMD64CVTTSD2SQ) - v.Type = t - v.AddArg(x) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } - return false -} -func rewriteValueAMD64_OpDiv16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div16 [a] x y) - // result: (Select0 (DIVW [a] x y)) + // match: (SETLE (FlagLT_UGT)) + // result: (MOVLconst [1]) for { - a := auxIntToBool(v.AuxInt) - x := v_0 - y := v_1 - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) - v0.AuxInt = boolToAuxInt(a) - v0.AddArg2(x, y) - v.AddArg(v0) + if v_0.Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } -} -func rewriteValueAMD64_OpDiv16u(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div16u x y) - // result: (Select0 (DIVWU x y)) + // match: (SETLE (FlagGT_ULT)) + // result: (MOVLconst [0]) for { - x := v_0 - y := v_1 - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) - v0.AddArg2(x, y) - v.AddArg(v0) + if v_0.Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } -} -func rewriteValueAMD64_OpDiv32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div32 [a] x y) - // result: (Select0 (DIVL [a] x y)) + // match: (SETLE (FlagGT_UGT)) + // result: (MOVLconst [0]) for { - a := auxIntToBool(v.AuxInt) - x := v_0 - y := v_1 - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) - v0.AuxInt = boolToAuxInt(a) - v0.AddArg2(x, y) - v.AddArg(v0) + if v_0.Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } + return false } -func rewriteValueAMD64_OpDiv32u(v *Value) bool { +func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Div32u x y) - // result: (Select0 (DIVLU x y)) + // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) + // result: (SETGEstore [off] {sym} ptr x mem) for { - x := v_0 - y := v_1 - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) - v0.AddArg2(x, y) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64InvertFlags { + break + } + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64SETGEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } -} -func rewriteValueAMD64_OpDiv64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div64 [a] x y) - // result: (Select0 (DIVQ [a] x y)) + // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SETLEstore [off1+off2] {sym} base val mem) for { - a := auxIntToBool(v.AuxInt) - x := v_0 - y := v_1 - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) - v0.AuxInt = boolToAuxInt(a) - v0.AddArg2(x, y) - v.AddArg(v0) + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64SETLEstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) return true } -} -func rewriteValueAMD64_OpDiv64u(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div64u x y) - // result: (Select0 (DIVQU x y)) - for { - x := v_0 - y := v_1 - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } -} -func rewriteValueAMD64_OpDiv8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div8 x y) - // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) + // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - x := v_0 - y := v_1 - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) - v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64SETLEstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } -} -func rewriteValueAMD64_OpDiv8u(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div8u x y) - // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) + // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - y := v_1 - v.reset(OpSelect0) - v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) - v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagEQ { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpEq16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Eq16 x y) - // result: (SETEQ (CMPW x y)) + // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETEQ) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_ULT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpEq32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Eq32 x y) - // result: (SETEQ (CMPL x y)) + // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETEQ) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_UGT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpEq32F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Eq32F x y) - // result: (SETEQF (UCOMISS x y)) + // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETEQF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_ULT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpEq64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Eq64 x y) - // result: (SETEQ (CMPQ x y)) + // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETEQ) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_UGT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } + return false } -func rewriteValueAMD64_OpEq64F(v *Value) bool { +func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Eq64F x y) - // result: (SETEQF (UCOMISD x y)) + typ := &b.Func.Config.Types + // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) + // result: (SETGstore [off] {sym} ptr x mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETEQF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64InvertFlags { + break + } + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64SETGstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } -} -func rewriteValueAMD64_OpEq8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Eq8 x y) - // result: (SETEQ (CMPB x y)) + // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SETLstore [off1+off2] {sym} base val mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETEQ) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64SETLstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) return true } -} -func rewriteValueAMD64_OpEqB(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (EqB x y) - // result: (SETEQ (CMPB x y)) + // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETEQ) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64SETLstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } -} -func rewriteValueAMD64_OpEqPtr(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (EqPtr x y) - // result: (SETEQ (CMPQ x y)) + // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETEQ) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagEQ { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpFMA(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (FMA x y z) - // result: (VFMADD231SD z x y) + // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - y := v_1 - z := v_2 - v.reset(OpAMD64VFMADD231SD) - v.AddArg3(z, x, y) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_ULT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpFloor(v *Value) bool { - v_0 := v.Args[0] - // match: (Floor x) - // result: (ROUNDSD [1] x) + // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - v.reset(OpAMD64ROUNDSD) - v.AuxInt = int8ToAuxInt(1) - v.AddArg(x) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_UGT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpGetG(v *Value) bool { - v_0 := v.Args[0] - // match: (GetG mem) - // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal - // result: (LoweredGetG mem) + // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - mem := v_0 - if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64LoweredGetG) - v.AddArg(mem) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } - return false -} -func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (HasCPUFeature {s}) - // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) + // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - s := auxToSym(v.Aux) - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagGT_UGT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) - v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) - v1.Aux = symToAux(s) - v0.AddArg(v1) - v.AddArg(v0) + v.AddArg3(ptr, v0, mem) return true } + return false } -func rewriteValueAMD64_OpIsInBounds(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64SETNE(v *Value) bool { v_0 := v.Args[0] b := v.Block - // match: (IsInBounds idx len) - // result: (SETB (CMPQ idx len)) + // match: (SETNE (TESTBconst [1] x)) + // result: (ANDLconst [1] x) for { - idx := v_0 - len := v_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(idx, len) - v.AddArg(v0) + if v_0.Op != OpAMD64TESTBconst || auxIntToInt8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpAMD64ANDLconst) + v.AuxInt = int32ToAuxInt(1) + v.AddArg(x) return true } -} -func rewriteValueAMD64_OpIsNonNil(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (IsNonNil p) - // result: (SETNE (TESTQ p p)) + // match: (SETNE (TESTWconst [1] x)) + // result: (ANDLconst [1] x) for { - p := v_0 - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) - v0.AddArg2(p, p) - v.AddArg(v0) + if v_0.Op != OpAMD64TESTWconst || auxIntToInt16(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpAMD64ANDLconst) + v.AuxInt = int32ToAuxInt(1) + v.AddArg(x) return true } -} -func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (IsSliceInBounds idx len) - // result: (SETBE (CMPQ idx len)) + // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) + // result: (SETB (BTL x y)) for { - idx := v_0 - len := v_1 - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(idx, len) - v.AddArg(v0) - return true + if v_0.Op != OpAMD64TESTL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break } -} -func rewriteValueAMD64_OpLeq16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Leq16 x y) - // result: (SETLE (CMPW x y)) + // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) + // result: (SETB (BTQ x y)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break } -} -func rewriteValueAMD64_OpLeq16U(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Leq16U x y) - // result: (SETBE (CMPW x y)) + // match: (SETNE (TESTLconst [c] x)) + // cond: isPowerOfTwo(uint32(c)) + // result: (SETB (BTLconst [int8(log32u(uint32(c)))] x)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) - v0.AddArg2(x, y) + if v_0.Op != OpAMD64TESTLconst { + break + } + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(isPowerOfTwo(uint32(c))) { + break + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) v.AddArg(v0) return true } -} -func rewriteValueAMD64_OpLeq32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Leq32 x y) - // result: (SETLE (CMPL x y)) + // match: (SETNE (TESTQconst [c] x)) + // cond: isPowerOfTwo(uint64(c)) + // result: (SETB (BTQconst [int8(log32u(uint32(c)))] x)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) - v0.AddArg2(x, y) + if v_0.Op != OpAMD64TESTQconst { + break + } + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(isPowerOfTwo(uint64(c))) { + break + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) v.AddArg(v0) return true } -} -func rewriteValueAMD64_OpLeq32F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Leq32F x y) - // result: (SETGEF (UCOMISS y x)) + // match: (SETNE (TESTQ (MOVQconst [c]) x)) + // cond: isPowerOfTwo(uint64(c)) + // result: (SETB (BTQconst [int8(log64u(uint64(c)))] x)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETGEF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) - v0.AddArg2(y, x) - v.AddArg(v0) - return true + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := auxIntToInt64(v_0_0.AuxInt) + x := v_0_1 + if !(isPowerOfTwo(uint64(c))) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) + v0.AddArg(x) + v.AddArg(v0) + return true + } + break } -} -func rewriteValueAMD64_OpLeq32U(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Leq32U x y) - // result: (SETBE (CMPL x y)) + // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) + // result: (SETEQ (CMPLconst [0] s)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) - v0.AddArg2(x, y) + if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { + break + } + s := v_0.Args[0] + if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { + break + } + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(s) v.AddArg(v0) return true } -} -func rewriteValueAMD64_OpLeq64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Leq64 x y) - // result: (SETLE (CMPQ x y)) + // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) + // result: (SETEQ (CMPQconst [0] s)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(x, y) + if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { + break + } + s := v_0.Args[0] + if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { + break + } + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(s) v.AddArg(v0) return true } -} -func rewriteValueAMD64_OpLeq64F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Leq64F x y) - // result: (SETGEF (UCOMISD y x)) + // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) + // cond: z1==z2 + // result: (SETB (BTQconst [63] x)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETGEF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) - v0.AddArg2(y, x) - v.AddArg(v0) - return true + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + v.AddArg(v0) + return true + } + break } -} -func rewriteValueAMD64_OpLeq64U(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Leq64U x y) - // result: (SETBE (CMPQ x y)) + // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) + // cond: z1==z2 + // result: (SETB (BTQconst [31] x)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + if v_0.Op != OpAMD64TESTL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + v.AddArg(v0) + return true + } + break } -} -func rewriteValueAMD64_OpLeq8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Leq8 x y) - // result: (SETLE (CMPB x y)) + // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) + // cond: z1==z2 + // result: (SETB (BTQconst [0] x)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + v.AddArg(v0) + return true + } + break } -} -func rewriteValueAMD64_OpLeq8U(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Leq8U x y) - // result: (SETBE (CMPB x y)) + // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) + // cond: z1==z2 + // result: (SETB (BTLconst [0] x)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + if v_0.Op != OpAMD64TESTL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + v.AddArg(v0) + return true + } + break } -} -func rewriteValueAMD64_OpLess16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Less16 x y) - // result: (SETL (CMPW x y)) + // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) + // cond: z1==z2 + // result: (SETB (BTQconst [63] x)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETL) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + x := z1.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + v.AddArg(v0) + return true + } + break } -} -func rewriteValueAMD64_OpLess16U(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Less16U x y) - // result: (SETB (CMPW x y)) + // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) + // cond: z1==z2 + // result: (SETB (BTLconst [31] x)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + if v_0.Op != OpAMD64TESTL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + x := z1.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + v.AddArg(v0) + return true + } + break } -} -func rewriteValueAMD64_OpLess32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Less32 x y) - // result: (SETL (CMPL x y)) + // match: (SETNE (InvertFlags x)) + // result: (SETNE x) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETL) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + if v_0.Op != OpAMD64InvertFlags { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETNE) + v.AddArg(x) return true } -} -func rewriteValueAMD64_OpLess32F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Less32F x y) - // result: (SETGF (UCOMISS y x)) + // match: (SETNE (FlagEQ)) + // result: (MOVLconst [0]) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETGF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) - v0.AddArg2(y, x) - v.AddArg(v0) + if v_0.Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } -} -func rewriteValueAMD64_OpLess32U(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Less32U x y) - // result: (SETB (CMPL x y)) + // match: (SETNE (FlagLT_ULT)) + // result: (MOVLconst [1]) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + if v_0.Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } -} -func rewriteValueAMD64_OpLess64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Less64 x y) - // result: (SETL (CMPQ x y)) + // match: (SETNE (FlagLT_UGT)) + // result: (MOVLconst [1]) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETL) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + if v_0.Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } -} -func rewriteValueAMD64_OpLess64F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Less64F x y) - // result: (SETGF (UCOMISD y x)) - for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETGF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) - v0.AddArg2(y, x) - v.AddArg(v0) - return true - } -} -func rewriteValueAMD64_OpLess64U(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Less64U x y) - // result: (SETB (CMPQ x y)) + // match: (SETNE (FlagGT_ULT)) + // result: (MOVLconst [1]) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + if v_0.Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } -} -func rewriteValueAMD64_OpLess8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Less8 x y) - // result: (SETL (CMPB x y)) + // match: (SETNE (FlagGT_UGT)) + // result: (MOVLconst [1]) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETL) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + if v_0.Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(1) return true } -} -func rewriteValueAMD64_OpLess8U(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Less8U x y) - // result: (SETB (CMPB x y)) + // match: (SETNE (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) + // result: (SETNE (Select1 blsr)) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + s := v_0_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { + continue + } + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + v.AddArg(v0) + return true + } + break } -} -func rewriteValueAMD64_OpLoad(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (Load ptr mem) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (MOVQload ptr mem) + // match: (SETNE (TESTL s:(Select0 blsr:(BLSRL _)) s)) + // result: (SETNE (Select1 blsr)) for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is64BitInt(t) || isPtr(t)) { + if v_0.Op != OpAMD64TESTL { break } - v.reset(OpAMD64MOVQload) - v.AddArg2(ptr, mem) - return true + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + s := v_0_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRL || s != v_0_1 { + continue + } + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + v.AddArg(v0) + return true + } + break } - // match: (Load ptr mem) - // cond: is32BitInt(t) - // result: (MOVLload ptr mem) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is32BitInt(t)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64MOVLload) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Load ptr mem) - // cond: is16BitInt(t) - // result: (MOVWload ptr mem) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is16BitInt(t)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64MOVWload) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Load ptr mem) - // cond: (t.IsBoolean() || is8BitInt(t)) - // result: (MOVBload ptr mem) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(t.IsBoolean() || is8BitInt(t)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64MOVBload) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Load ptr mem) - // cond: is32BitFloat(t) - // result: (MOVSSload ptr mem) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is32BitFloat(t)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64MOVSSload) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Load ptr mem) - // cond: is64BitFloat(t) - // result: (MOVSDload ptr mem) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is64BitFloat(t)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64MOVSDload) - v.AddArg2(ptr, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLocalAddr(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (LocalAddr {sym} base mem) - // cond: t.Elem().HasPointers() - // result: (LEAQ {sym} (SPanchored base mem)) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - sym := auxToSym(v.Aux) - base := v_0 - mem := v_1 - if !(t.Elem().HasPointers()) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64LEAQ) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) - v0.AddArg2(base, mem) - v.AddArg(v0) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (LocalAddr {sym} base _) - // cond: !t.Elem().HasPointers() - // result: (LEAQ {sym} base) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - sym := auxToSym(v.Aux) - base := v_0 - if !(!t.Elem().HasPointers()) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64LEAQ) - v.Aux = symToAux(sym) - v.AddArg(base) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh16x16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh16x16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh16x16 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh16x32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh16x32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh16x32 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh16x64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh16x64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh16x64 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh16x8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh16x8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + // match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh16x8 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh32x16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh32x16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh32x16 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh32x32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh32x32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh32x32 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh32x64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh32x64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh32x64 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh32x8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh32x8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh32x8 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh64x16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh64x16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh64x16 x y) - // cond: shiftIsBounded(v) - // result: (SHLQ x y) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64SHLQ) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh64x32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh64x32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh64x32 x y) - // cond: shiftIsBounded(v) - // result: (SHLQ x y) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64SHLQ) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh64x64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh64x64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) + // match: (SETNE t:(TESTL x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTL { break } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh64x64 x y) - // cond: shiftIsBounded(v) - // result: (SHLQ x y) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64SHLQ) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh64x8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh64x8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETNE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh64x8 x y) - // cond: shiftIsBounded(v) - // result: (SHLQ x y) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETL flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64SHLQ) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh8x16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh8x16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETG flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh8x16 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETLE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh8x32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh8x32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETGE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh8x32 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETA flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh8x64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh8x64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETB flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh8x64 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETAE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - return false -} -func rewriteValueAMD64_OpLsh8x8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh8x8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETBE flags)) x)) + // cond: t.Block == s.Block + // result: s for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Lsh8x8 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETEQF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + t := v_0 + if t.Op != OpAMD64TESTW { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) - return true - } - return false -} -func rewriteValueAMD64_OpMax32F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Max32F x y) - // result: (Neg32F (Min32F (Neg32F x) (Neg32F y))) - for { - t := v.Type - x := v_0 - y := v_1 - v.reset(OpNeg32F) - v.Type = t - v0 := b.NewValue0(v.Pos, OpMin32F, t) - v1 := b.NewValue0(v.Pos, OpNeg32F, t) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpNeg32F, t) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) - return true - } -} -func rewriteValueAMD64_OpMax64F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Max64F x y) - // result: (Neg64F (Min64F (Neg64F x) (Neg64F y))) - for { - t := v.Type - x := v_0 - y := v_1 - v.reset(OpNeg64F) - v.Type = t - v0 := b.NewValue0(v.Pos, OpMin64F, t) - v1 := b.NewValue0(v.Pos, OpNeg64F, t) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpNeg64F, t) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) - return true - } -} -func rewriteValueAMD64_OpMin32F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Min32F x y) - // result: (POR (MINSS (MINSS x y) x) (MINSS x y)) - for { - t := v.Type - x := v_0 - y := v_1 - v.reset(OpAMD64POR) - v0 := b.NewValue0(v.Pos, OpAMD64MINSS, t) - v1 := b.NewValue0(v.Pos, OpAMD64MINSS, t) - v1.AddArg2(x, y) - v0.AddArg2(v1, x) - v.AddArg2(v0, v1) - return true - } -} -func rewriteValueAMD64_OpMin64F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Min64F x y) - // result: (POR (MINSD (MINSD x y) x) (MINSD x y)) - for { - t := v.Type - x := v_0 - y := v_1 - v.reset(OpAMD64POR) - v0 := b.NewValue0(v.Pos, OpAMD64MINSD, t) - v1 := b.NewValue0(v.Pos, OpAMD64MINSD, t) - v1.AddArg2(x, y) - v0.AddArg2(v1, x) - v.AddArg2(v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } -} -func rewriteValueAMD64_OpMod16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Mod16 [a] x y) - // result: (Select1 (DIVW [a] x y)) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETNEF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - a := auxIntToBool(v.AuxInt) - x := v_0 - y := v_1 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) - v0.AuxInt = boolToAuxInt(a) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTW { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } -} -func rewriteValueAMD64_OpMod16u(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Mod16u x y) - // result: (Select1 (DIVWU x y)) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETGF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTW { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } -} -func rewriteValueAMD64_OpMod32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Mod32 [a] x y) - // result: (Select1 (DIVL [a] x y)) + // match: (SETNE t:(TESTW x:(MOVBQZX s:(SETGEF flags)) x)) + // cond: t.Block == s.Block + // result: s for { - a := auxIntToBool(v.AuxInt) - x := v_0 - y := v_1 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) - v0.AuxInt = boolToAuxInt(a) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTW { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + if x != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } -} -func rewriteValueAMD64_OpMod32u(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Mod32u x y) - // result: (Select1 (DIVLU x y)) + // match: (SETNE t:(TESTB s:(SETEQ flags) s)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQ { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } -} -func rewriteValueAMD64_OpMod64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Mod64 [a] x y) - // result: (Select1 (DIVQ [a] x y)) + // match: (SETNE t:(TESTB s:(SETNE flags) s)) + // cond: t.Block == s.Block + // result: s for { - a := auxIntToBool(v.AuxInt) - x := v_0 - y := v_1 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) - v0.AuxInt = boolToAuxInt(a) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNE { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } -} -func rewriteValueAMD64_OpMod64u(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Mod64u x y) - // result: (Select1 (DIVQU x y)) + // match: (SETNE t:(TESTB s:(SETL flags) s)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETL { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } -} -func rewriteValueAMD64_OpMod8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Mod8 x y) - // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) + // match: (SETNE t:(TESTB s:(SETG flags) s)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) - v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETG { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } -} -func rewriteValueAMD64_OpMod8u(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Mod8u x y) - // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) + // match: (SETNE t:(TESTB s:(SETLE flags) s)) + // cond: t.Block == s.Block + // result: s for { - x := v_0 - y := v_1 - v.reset(OpSelect1) - v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) - v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) - return true + t := v_0 + if t.Op != OpAMD64TESTB { + break + } + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETLE { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } -} -func rewriteValueAMD64_OpMove(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Move [0] _ _ mem) - // result: mem + // match: (SETNE t:(TESTB s:(SETGE flags) s)) + // cond: t.Block == s.Block + // result: s for { - if auxIntToInt64(v.AuxInt) != 0 { + t := v_0 + if t.Op != OpAMD64TESTB { break } - mem := v_2 - v.copyOf(mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGE { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Move [1] dst src mem) - // result: (MOVBstore dst (MOVBload src mem) mem) + // match: (SETNE t:(TESTB s:(SETA flags) s)) + // cond: t.Block == s.Block + // result: s for { - if auxIntToInt64(v.AuxInt) != 1 { + t := v_0 + if t.Op != OpAMD64TESTB { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVBstore) - v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) - v0.AddArg2(src, mem) - v.AddArg3(dst, v0, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETA { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Move [2] dst src mem) - // result: (MOVWstore dst (MOVWload src mem) mem) + // match: (SETNE t:(TESTB s:(SETB flags) s)) + // cond: t.Block == s.Block + // result: s for { - if auxIntToInt64(v.AuxInt) != 2 { + t := v_0 + if t.Op != OpAMD64TESTB { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVWstore) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) - v0.AddArg2(src, mem) - v.AddArg3(dst, v0, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETB { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Move [4] dst src mem) - // result: (MOVLstore dst (MOVLload src mem) mem) + // match: (SETNE t:(TESTB s:(SETAE flags) s)) + // cond: t.Block == s.Block + // result: s for { - if auxIntToInt64(v.AuxInt) != 4 { + t := v_0 + if t.Op != OpAMD64TESTB { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVLstore) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) - v0.AddArg2(src, mem) - v.AddArg3(dst, v0, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETAE { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Move [8] dst src mem) - // result: (MOVQstore dst (MOVQload src mem) mem) + // match: (SETNE t:(TESTB s:(SETBE flags) s)) + // cond: t.Block == s.Block + // result: s for { - if auxIntToInt64(v.AuxInt) != 8 { + t := v_0 + if t.Op != OpAMD64TESTB { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVQstore) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) - v0.AddArg2(src, mem) - v.AddArg3(dst, v0, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETBE { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Move [16] dst src mem) - // result: (MOVOstore dst (MOVOload src mem) mem) + // match: (SETNE t:(TESTB s:(SETEQF flags) s)) + // cond: t.Block == s.Block + // result: s for { - if auxIntToInt64(v.AuxInt) != 16 { + t := v_0 + if t.Op != OpAMD64TESTB { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVOstore) - v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) - v0.AddArg2(src, mem) - v.AddArg3(dst, v0, mem) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQF { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Move [3] dst src mem) - // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) + // match: (SETNE t:(TESTB s:(SETNEF flags) s)) + // cond: t.Block == s.Block + // result: s for { - if auxIntToInt64(v.AuxInt) != 3 { + t := v_0 + if t.Op != OpAMD64TESTB { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(2) - v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) - v0.AuxInt = int32ToAuxInt(2) - v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) - v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AddArg2(src, mem) - v1.AddArg3(dst, v2, mem) - v.AddArg3(dst, v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNEF { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Move [5] dst src mem) - // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) + // match: (SETNE t:(TESTB s:(SETGF flags) s)) + // cond: t.Block == s.Block + // result: s for { - if auxIntToInt64(v.AuxInt) != 5 { + t := v_0 + if t.Op != OpAMD64TESTB { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(4) - v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) - v0.AuxInt = int32ToAuxInt(4) - v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) - v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AddArg2(src, mem) - v1.AddArg3(dst, v2, mem) - v.AddArg3(dst, v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGF { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Move [6] dst src mem) - // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) + // match: (SETNE t:(TESTB s:(SETGEF flags) s)) + // cond: t.Block == s.Block + // result: s for { - if auxIntToInt64(v.AuxInt) != 6 { + t := v_0 + if t.Op != OpAMD64TESTB { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(4) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) - v0.AuxInt = int32ToAuxInt(4) - v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) - v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AddArg2(src, mem) - v1.AddArg3(dst, v2, mem) - v.AddArg3(dst, v0, v1) - return true + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGEF { + continue + } + if s != t_1 || !(t.Block == s.Block) { + continue + } + v.copyOf(s) + return true + } + break } - // match: (Move [7] dst src mem) - // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) + return false +} +func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) + // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { - if auxIntToInt64(v.AuxInt) != 7 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(3) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) - v0.AuxInt = int32ToAuxInt(3) - v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) - v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AddArg2(src, mem) - v1.AddArg3(dst, v2, mem) - v.AddArg3(dst, v0, v1) - return true + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLL { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true + } + break } - // match: (Move [9] dst src mem) - // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) + // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) + // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { - if auxIntToInt64(v.AuxInt) != 9 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVBstore) - v.AuxInt = int32ToAuxInt(8) - v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) - v0.AuxInt = int32ToAuxInt(8) - v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) - v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) - v2.AddArg2(src, mem) - v1.AddArg3(dst, v2, mem) - v.AddArg3(dst, v0, v1) - return true + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLQ { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true + } + break } - // match: (Move [10] dst src mem) - // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) + // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) + // cond: isPowerOfTwo(uint32(c)) + // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32u(uint32(c)))] x) mem) for { - if auxIntToInt64(v.AuxInt) != 10 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTLconst { break } - dst := v_0 - src := v_1 + c := auxIntToInt32(v_1.AuxInt) + x := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(8) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) - v0.AuxInt = int32ToAuxInt(8) - v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) - v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) - v2.AddArg2(src, mem) - v1.AddArg3(dst, v2, mem) - v.AddArg3(dst, v0, v1) + if !(isPowerOfTwo(uint32(c))) { + break + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) return true } - // match: (Move [11] dst src mem) - // result: (MOVLstore [7] dst (MOVLload [7] src mem) (MOVQstore dst (MOVQload src mem) mem)) + // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) + // cond: isPowerOfTwo(uint64(c)) + // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log32u(uint32(c)))] x) mem) for { - if auxIntToInt64(v.AuxInt) != 11 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQconst { break } - dst := v_0 - src := v_1 + c := auxIntToInt32(v_1.AuxInt) + x := v_1.Args[0] mem := v_2 - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(7) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) - v0.AuxInt = int32ToAuxInt(7) - v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) - v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) - v2.AddArg2(src, mem) - v1.AddArg3(dst, v2, mem) - v.AddArg3(dst, v0, v1) + if !(isPowerOfTwo(uint64(c))) { + break + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) return true } - // match: (Move [12] dst src mem) - // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) + // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) + // cond: isPowerOfTwo(uint64(c)) + // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log64u(uint64(c)))] x) mem) for { - if auxIntToInt64(v.AuxInt) != 12 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { break } - dst := v_0 - src := v_1 - mem := v_2 - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(8) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) - v0.AuxInt = int32ToAuxInt(8) - v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) - v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) - v2.AddArg2(src, mem) - v1.AddArg3(dst, v2, mem) - v.AddArg3(dst, v0, v1) - return true + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64MOVQconst { + continue + } + c := auxIntToInt64(v_1_0.AuxInt) + x := v_1_1 + mem := v_2 + if !(isPowerOfTwo(uint64(c))) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true + } + break } - // match: (Move [s] dst src mem) - // cond: s >= 13 && s <= 15 - // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem)) + // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) + // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { - s := auxIntToInt64(v.AuxInt) - dst := v_0 - src := v_1 - mem := v_2 - if !(s >= 13 && s <= 15) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(int32(s - 8)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) - v0.AuxInt = int32ToAuxInt(int32(s - 8)) - v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) - v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) - v2.AddArg2(src, mem) - v1.AddArg3(dst, v2, mem) - v.AddArg3(dst, v0, v1) + s := v_1.Args[0] + if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { + break + } + mem := v_2 + v.reset(OpAMD64SETEQstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(s) + v.AddArg3(ptr, v0, mem) return true } - // match: (Move [s] dst src mem) - // cond: s > 16 && s < 192 && logLargeCopy(v, s) - // result: (LoweredMove [s] dst src mem) + // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) + // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { - s := auxIntToInt64(v.AuxInt) - dst := v_0 - src := v_1 - mem := v_2 - if !(s > 16 && s < 192 && logLargeCopy(v, s)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } - v.reset(OpAMD64LoweredMove) - v.AuxInt = int64ToAuxInt(s) - v.AddArg3(dst, src, mem) + s := v_1.Args[0] + if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { + break + } + mem := v_2 + v.reset(OpAMD64SETEQstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(s) + v.AddArg3(ptr, v0, mem) return true } - // match: (Move [s] dst src mem) - // cond: s >= 192 && s <= repMoveThreshold && logLargeCopy(v, s) - // result: (LoweredMoveLoop [s] dst src mem) + // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) + // cond: z1==z2 + // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { - s := auxIntToInt64(v.AuxInt) - dst := v_0 - src := v_1 - mem := v_2 - if !(s >= 192 && s <= repMoveThreshold && logLargeCopy(v, s)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64LoweredMoveLoop) - v.AuxInt = int64ToAuxInt(s) - v.AddArg3(dst, src, mem) - return true + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true + } + break } - // match: (Move [s] dst src mem) - // cond: s > repMoveThreshold && s%8 != 0 - // result: (Move [s-s%8] (OffPtr dst [s%8]) (OffPtr src [s%8]) (MOVQstore dst (MOVQload src mem) mem)) + // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) + // cond: z1==z2 + // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { - s := auxIntToInt64(v.AuxInt) - dst := v_0 - src := v_1 - mem := v_2 - if !(s > repMoveThreshold && s%8 != 0) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { break } - v.reset(OpMove) - v.AuxInt = int64ToAuxInt(s - s%8) - v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) - v0.AuxInt = int64ToAuxInt(s % 8) - v0.AddArg(dst) - v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) - v1.AuxInt = int64ToAuxInt(s % 8) - v1.AddArg(src) - v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) - v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) - v3.AddArg2(src, mem) - v2.AddArg3(dst, v3, mem) - v.AddArg3(v0, v1, v2) - return true + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true + } + break } - // match: (Move [s] dst src mem) - // cond: s > repMoveThreshold && s%8 == 0 && logLargeCopy(v, s) - // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) + // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) + // cond: z1==z2 + // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { - s := auxIntToInt64(v.AuxInt) - dst := v_0 - src := v_1 - mem := v_2 - if !(s > repMoveThreshold && s%8 == 0 && logLargeCopy(v, s)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { break } - v.reset(OpAMD64REPMOVSQ) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(s / 8) - v.AddArg4(dst, src, v0, mem) - return true + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true + } + break } - return false -} -func rewriteValueAMD64_OpNeg32F(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Neg32F x) - // result: (PXOR x (MOVSSconst [float32(math.Copysign(0, -1))])) + // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) + // cond: z1==z2 + // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { - x := v_0 - v.reset(OpAMD64PXOR) - v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) - v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1))) - v.AddArg2(x, v0) - return true + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true + } + break } -} -func rewriteValueAMD64_OpNeg64F(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Neg64F x) - // result: (PXOR x (MOVSDconst [math.Copysign(0, -1)])) + // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) + // cond: z1==z2 + // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { - x := v_0 - v.reset(OpAMD64PXOR) - v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) - v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1)) - v.AddArg2(x, v0) - return true - } -} -func rewriteValueAMD64_OpNeq16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Neq16 x y) - // result: (SETNE (CMPW x y)) - for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } -} -func rewriteValueAMD64_OpNeq32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Neq32 x y) - // result: (SETNE (CMPL x y)) - for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + x := z1.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true + } + break } -} -func rewriteValueAMD64_OpNeq32F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Neq32F x y) - // result: (SETNEF (UCOMISS x y)) + // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) + // cond: z1==z2 + // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETNEF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + z1 := v_1_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + x := z1.Args[0] + z2 := v_1_1 + mem := v_2 + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + v.AddArg3(ptr, v0, mem) + return true + } + break } -} -func rewriteValueAMD64_OpNeq64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Neq64 x y) - // result: (SETNE (CMPQ x y)) + // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) + // result: (SETNEstore [off] {sym} ptr x mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64InvertFlags { + break + } + x := v_1.Args[0] + mem := v_2 + v.reset(OpAMD64SETNEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } -} -func rewriteValueAMD64_OpNeq64F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Neq64F x y) - // result: (SETNEF (UCOMISD x y)) + // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SETNEstore [off1+off2] {sym} base val mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETNEF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64SETNEstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) return true } -} -func rewriteValueAMD64_OpNeq8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Neq8 x y) - // result: (SETNE (CMPB x y)) + // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64SETNEstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } -} -func rewriteValueAMD64_OpNeqB(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (NeqB x y) - // result: (SETNE (CMPB x y)) + // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagEQ { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpNeqPtr(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (NeqPtr x y) - // result: (SETNE (CMPQ x y)) + // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - y := v_1 - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_ULT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpNot(v *Value) bool { - v_0 := v.Args[0] - // match: (Not x) - // result: (XORLconst [1] x) + // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - x := v_0 - v.reset(OpAMD64XORLconst) - v.AuxInt = int32ToAuxInt(1) - v.AddArg(x) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64FlagLT_UGT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } -} -func rewriteValueAMD64_OpOffPtr(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (OffPtr [off] ptr) - // cond: is32Bit(off) - // result: (ADDQconst [int32(off)] ptr) + // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - off := auxIntToInt64(v.AuxInt) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) ptr := v_0 - if !(is32Bit(off)) { + if v_1.Op != OpAMD64FlagGT_ULT { break } - v.reset(OpAMD64ADDQconst) - v.AuxInt = int32ToAuxInt(int32(off)) - v.AddArg(ptr) + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } - // match: (OffPtr [off] ptr) - // result: (ADDQ (MOVQconst [off]) ptr) + // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) + // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { - off := auxIntToInt64(v.AuxInt) + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) ptr := v_0 - v.reset(OpAMD64ADDQ) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(off) - v.AddArg2(v0, ptr) + if v_1.Op != OpAMD64FlagGT_UGT { + break + } + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg3(ptr, v0, mem) return true } + return false } -func rewriteValueAMD64_OpPopCount16(v *Value) bool { +func rewriteValueAMD64_OpAMD64SHLL(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (PopCount16 x) - // result: (POPCNTL (MOVWQZX x)) + // match: (SHLL x (MOVQconst [c])) + // result: (SHLLconst [int8(c&31)] x) for { x := v_0 - v.reset(OpAMD64POPCNTL) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) - v0.AddArg(x) - v.AddArg(v0) + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHLLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) return true } -} -func rewriteValueAMD64_OpPopCount8(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (PopCount8 x) - // result: (POPCNTL (MOVBQZX x)) + // match: (SHLL x (MOVLconst [c])) + // result: (SHLLconst [int8(c&31)] x) for { x := v_0 - v.reset(OpAMD64POPCNTL) - v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) - v0.AddArg(x) - v.AddArg(v0) + if v_1.Op != OpAMD64MOVLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHLLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) return true } -} -func rewriteValueAMD64_OpRoundToEven(v *Value) bool { - v_0 := v.Args[0] - // match: (RoundToEven x) - // result: (ROUNDSD [0] x) + // match: (SHLL x (ADDQconst [c] y)) + // cond: c & 31 == 0 + // result: (SHLL x y) for { x := v_0 - v.reset(OpAMD64ROUNDSD) - v.AuxInt = int8ToAuxInt(0) - v.AddArg(x) + if v_1.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) return true } -} -func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh16Ux16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) + // match: (SHLL x (NEGQ (ADDQconst [c] y))) + // cond: c & 31 == 0 + // result: (SHLL x (NEGQ y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(16) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Rsh16Ux16 x y) - // cond: shiftIsBounded(v) - // result: (SHRW x y) + // match: (SHLL x (ANDQconst [c] y)) + // cond: c & 31 == 31 + // result: (SHLL x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ANDQconst { break } - v.reset(OpAMD64SHRW) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh16Ux32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) + // match: (SHLL x (NEGQ (ANDQconst [c] y))) + // cond: c & 31 == 31 + // result: (SHLL x (NEGQ y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(16) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Rsh16Ux32 x y) - // cond: shiftIsBounded(v) - // result: (SHRW x y) + // match: (SHLL x (ADDLconst [c] y)) + // cond: c & 31 == 0 + // result: (SHLL x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ADDLconst { break } - v.reset(OpAMD64SHRW) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh16Ux64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) + // match: (SHLL x (NEGL (ADDLconst [c] y))) + // cond: c & 31 == 0 + // result: (SHLL x (NEGL y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGL { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(16) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Rsh16Ux64 x y) - // cond: shiftIsBounded(v) - // result: (SHRW x y) + // match: (SHLL x (ANDLconst [c] y)) + // cond: c & 31 == 31 + // result: (SHLL x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ANDLconst { break } - v.reset(OpAMD64SHRW) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh16Ux8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) + // match: (SHLL x (NEGL (ANDLconst [c] y))) + // cond: c & 31 == 31 + // result: (SHLL x (NEGL y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGL { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(16) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Rsh16Ux8 x y) - // cond: shiftIsBounded(v) - // result: (SHRW x y) + // match: (SHLL l:(MOVLload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHLXLload [off] {sym} ptr x mem) for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + l := v_0 + if l.Op != OpAMD64MOVLload { break } - v.reset(OpAMD64SHRW) - v.AddArg2(x, y) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHLXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } return false } -func rewriteValueAMD64_OpRsh16x16(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Rsh16x16 x y) - // cond: !shiftIsBounded(v) - // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) + // match: (SHLLconst x [0]) + // result: x for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if auxIntToInt8(v.AuxInt) != 0 { break } - v.reset(OpAMD64SARW) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v3.AuxInt = int16ToAuxInt(16) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) - v.AddArg2(x, v0) + x := v_0 + v.copyOf(x) return true } - // match: (Rsh16x16 x y) - // cond: shiftIsBounded(v) - // result: (SARW x y) + // match: (SHLLconst [1] x) + // result: (ADDL x x) for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if auxIntToInt8(v.AuxInt) != 1 { break } - v.reset(OpAMD64SARW) - v.AddArg2(x, y) + x := v_0 + v.reset(OpAMD64ADDL) + v.AddArg2(x, x) return true } - return false -} -func rewriteValueAMD64_OpRsh16x32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh16x32 x y) - // cond: !shiftIsBounded(v) - // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) + // match: (SHLLconst [c] (ADDL x x)) + // cond: c < 31 + // result: (SHLLconst [c+1] x) for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + c := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64ADDL { break } - v.reset(OpAMD64SARW) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v3.AuxInt = int32ToAuxInt(16) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) - v.AddArg2(x, v0) + x := v_0.Args[1] + if x != v_0.Args[0] || !(c < 31) { + break + } + v.reset(OpAMD64SHLLconst) + v.AuxInt = int8ToAuxInt(c + 1) + v.AddArg(x) return true } - // match: (Rsh16x32 x y) - // cond: shiftIsBounded(v) - // result: (SARW x y) + // match: (SHLLconst [d] (MOVLconst [c])) + // result: (MOVLconst [c << uint64(d)]) for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + d := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64SARW) - v.AddArg2(x, y) + c := auxIntToInt32(v_0.AuxInt) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } return false } -func rewriteValueAMD64_OpRsh16x64(v *Value) bool { +func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh16x64 x y) - // cond: !shiftIsBounded(v) - // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) + // match: (SHLQ x (MOVQconst [c])) + // result: (SHLQconst [int8(c&63)] x) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64SARW) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v3.AuxInt = int32ToAuxInt(16) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) - v.AddArg2(x, v0) + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHLQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) return true } - // match: (Rsh16x64 x y) - // cond: shiftIsBounded(v) - // result: (SARW x y) + // match: (SHLQ x (MOVLconst [c])) + // result: (SHLQconst [int8(c&63)] x) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64SARW) - v.AddArg2(x, y) + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHLQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpRsh16x8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh16x8 x y) - // cond: !shiftIsBounded(v) - // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) + // match: (SHLQ x (ADDQconst [c] y)) + // cond: c & 63 == 0 + // result: (SHLQ x y) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64ADDQconst { break } - v.reset(OpAMD64SARW) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v3.AuxInt = int8ToAuxInt(16) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) - v.AddArg2(x, v0) - return true - } - // match: (Rsh16x8 x y) - // cond: shiftIsBounded(v) - // result: (SARW x y) - for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { break } - v.reset(OpAMD64SARW) + v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh32Ux16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) + // match: (SHLQ x (NEGQ (ADDQconst [c] y))) + // cond: c & 63 == 0 + // result: (SHLQ x (NEGQ y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Rsh32Ux16 x y) - // cond: shiftIsBounded(v) - // result: (SHRL x y) + // match: (SHLQ x (ANDQconst [c] y)) + // cond: c & 63 == 63 + // result: (SHLQ x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ANDQconst { break } - v.reset(OpAMD64SHRL) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh32Ux32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) + // match: (SHLQ x (NEGQ (ANDQconst [c] y))) + // cond: c & 63 == 63 + // result: (SHLQ x (NEGQ y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Rsh32Ux32 x y) - // cond: shiftIsBounded(v) - // result: (SHRL x y) + // match: (SHLQ x (ADDLconst [c] y)) + // cond: c & 63 == 0 + // result: (SHLQ x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ADDLconst { break } - v.reset(OpAMD64SHRL) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh32Ux64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) + // match: (SHLQ x (NEGL (ADDLconst [c] y))) + // cond: c & 63 == 0 + // result: (SHLQ x (NEGL y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGL { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Rsh32Ux64 x y) - // cond: shiftIsBounded(v) - // result: (SHRL x y) + // match: (SHLQ x (ANDLconst [c] y)) + // cond: c & 63 == 63 + // result: (SHLQ x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ANDLconst { break } - v.reset(OpAMD64SHRL) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh32Ux8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) + // match: (SHLQ x (NEGL (ANDLconst [c] y))) + // cond: c & 63 == 63 + // result: (SHLQ x (NEGL y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGL { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Rsh32Ux8 x y) - // cond: shiftIsBounded(v) - // result: (SHRL x y) + // match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHLXQload [off] {sym} ptr x mem) for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + l := v_0 + if l.Op != OpAMD64MOVQload { break } - v.reset(OpAMD64SHRL) - v.AddArg2(x, y) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHLXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } return false } -func rewriteValueAMD64_OpRsh32x16(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Rsh32x16 x y) - // cond: !shiftIsBounded(v) - // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) + // match: (SHLQconst x [0]) + // result: x for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if auxIntToInt8(v.AuxInt) != 0 { break } - v.reset(OpAMD64SARL) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v3.AuxInt = int16ToAuxInt(32) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) - v.AddArg2(x, v0) + x := v_0 + v.copyOf(x) return true } - // match: (Rsh32x16 x y) - // cond: shiftIsBounded(v) - // result: (SARL x y) + // match: (SHLQconst [1] x) + // result: (ADDQ x x) for { + if auxIntToInt8(v.AuxInt) != 1 { + break + } x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + v.reset(OpAMD64ADDQ) + v.AddArg2(x, x) + return true + } + // match: (SHLQconst [c] (ADDQ x x)) + // cond: c < 63 + // result: (SHLQconst [c+1] x) + for { + c := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64ADDQ { break } - v.reset(OpAMD64SARL) - v.AddArg2(x, y) + x := v_0.Args[1] + if x != v_0.Args[0] || !(c < 63) { + break + } + v.reset(OpAMD64SHLQconst) + v.AuxInt = int8ToAuxInt(c + 1) + v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpRsh32x32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh32x32 x y) - // cond: !shiftIsBounded(v) - // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) + // match: (SHLQconst [d] (MOVQconst [c])) + // result: (MOVQconst [c << uint64(d)]) for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + d := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64SARL) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v3.AuxInt = int32ToAuxInt(32) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) - v.AddArg2(x, v0) + c := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } - // match: (Rsh32x32 x y) - // cond: shiftIsBounded(v) - // result: (SARL x y) + // match: (SHLQconst [d] (MOVLconst [c])) + // result: (MOVQconst [int64(c) << uint64(d)]) for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + d := auxIntToInt8(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64SARL) - v.AddArg2(x, y) + c := auxIntToInt32(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(c) << uint64(d)) return true } return false } -func rewriteValueAMD64_OpRsh32x64(v *Value) bool { +func rewriteValueAMD64_OpAMD64SHLXLload(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh32x64 x y) - // cond: !shiftIsBounded(v) - // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SARL) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v3.AuxInt = int32ToAuxInt(32) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) - v.AddArg2(x, v0) - return true - } - // match: (Rsh32x64 x y) - // cond: shiftIsBounded(v) - // result: (SARL x y) + typ := &b.Func.Config.Types + // match: (SHLXLload [off] {sym} ptr (MOVLconst [c]) mem) + // result: (SHLLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64SARL) - v.AddArg2(x, y) + c := auxIntToInt32(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64SHLLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + v.AddArg(v0) return true } return false } -func rewriteValueAMD64_OpRsh32x8(v *Value) bool { +func rewriteValueAMD64_OpAMD64SHLXQload(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh32x8 x y) - // cond: !shiftIsBounded(v) - // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) + typ := &b.Func.Config.Types + // match: (SHLXQload [off] {sym} ptr (MOVQconst [c]) mem) + // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64SARL) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v3.AuxInt = int8ToAuxInt(32) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) - v.AddArg2(x, v0) + c := auxIntToInt64(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64SHLQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + v.AddArg(v0) return true } - // match: (Rsh32x8 x y) - // cond: shiftIsBounded(v) - // result: (SARL x y) + // match: (SHLXQload [off] {sym} ptr (MOVLconst [c]) mem) + // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64SARL) - v.AddArg2(x, y) + c := auxIntToInt32(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64SHLQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + v.AddArg(v0) return true } return false } -func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool { +func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (Rsh64Ux16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) + // match: (SHRB x (MOVQconst [c])) + // cond: c&31 < 8 + // result: (SHRBconst [int8(c&31)] x) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + c := auxIntToInt64(v_1.AuxInt) + if !(c&31 < 8) { + break + } + v.reset(OpAMD64SHRBconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) return true } - // match: (Rsh64Ux16 x y) - // cond: shiftIsBounded(v) - // result: (SHRQ x y) + // match: (SHRB x (MOVLconst [c])) + // cond: c&31 < 8 + // result: (SHRBconst [int8(c&31)] x) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64SHRQ) - v.AddArg2(x, y) + c := auxIntToInt32(v_1.AuxInt) + if !(c&31 < 8) { + break + } + v.reset(OpAMD64SHRBconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh64Ux32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) + // match: (SHRB _ (MOVQconst [c])) + // cond: c&31 >= 8 + // result: (MOVLconst [0]) for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + c := auxIntToInt64(v_1.AuxInt) + if !(c&31 >= 8) { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (Rsh64Ux32 x y) - // cond: shiftIsBounded(v) - // result: (SHRQ x y) + // match: (SHRB _ (MOVLconst [c])) + // cond: c&31 >= 8 + // result: (MOVLconst [0]) for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64SHRQ) - v.AddArg2(x, y) + c := auxIntToInt32(v_1.AuxInt) + if !(c&31 >= 8) { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } return false } -func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Rsh64Ux64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) + // match: (SHRBconst x [0]) + // result: x for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if auxIntToInt8(v.AuxInt) != 0 { break } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true - } - // match: (Rsh64Ux64 x y) - // cond: shiftIsBounded(v) - // result: (SHRQ x y) - for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHRQ) - v.AddArg2(x, y) + v.copyOf(x) return true } return false } -func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool { +func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh64Ux8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) + // match: (SHRL x (MOVQconst [c])) + // result: (SHRLconst [int8(c&31)] x) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHRLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) return true } - // match: (Rsh64Ux8 x y) - // cond: shiftIsBounded(v) - // result: (SHRQ x y) + // match: (SHRL x (MOVLconst [c])) + // result: (SHRLconst [int8(c&31)] x) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64SHRQ) - v.AddArg2(x, y) + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHRLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpRsh64x16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh64x16 x y) - // cond: !shiftIsBounded(v) - // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) + // match: (SHRL x (ADDQconst [c] y)) + // cond: c & 31 == 0 + // result: (SHRL x y) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64ADDQconst { break } - v.reset(OpAMD64SARQ) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v3.AuxInt = int16ToAuxInt(64) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) - v.AddArg2(x, v0) - return true - } - // match: (Rsh64x16 x y) - // cond: shiftIsBounded(v) - // result: (SARQ x y) - for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { break } - v.reset(OpAMD64SARQ) + v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh64x32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh64x32 x y) - // cond: !shiftIsBounded(v) - // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) + // match: (SHRL x (NEGQ (ADDQconst [c] y))) + // cond: c & 31 == 0 + // result: (SHRL x (NEGQ y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64SARQ) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v3.AuxInt = int32ToAuxInt(64) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (Rsh64x32 x y) - // cond: shiftIsBounded(v) - // result: (SARQ x y) + // match: (SHRL x (ANDQconst [c] y)) + // cond: c & 31 == 31 + // result: (SHRL x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ANDQconst { break } - v.reset(OpAMD64SARQ) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh64x64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh64x64 x y) - // cond: !shiftIsBounded(v) - // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) + // match: (SHRL x (NEGQ (ANDQconst [c] y))) + // cond: c & 31 == 31 + // result: (SHRL x (NEGQ y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64SARQ) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v3.AuxInt = int32ToAuxInt(64) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (Rsh64x64 x y) - // cond: shiftIsBounded(v) - // result: (SARQ x y) + // match: (SHRL x (ADDLconst [c] y)) + // cond: c & 31 == 0 + // result: (SHRL x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ADDLconst { break } - v.reset(OpAMD64SARQ) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh64x8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh64x8 x y) - // cond: !shiftIsBounded(v) - // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) + // match: (SHRL x (NEGL (ADDLconst [c] y))) + // cond: c & 31 == 0 + // result: (SHRL x (NEGL y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGL { break } - v.reset(OpAMD64SARQ) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v3.AuxInt = int8ToAuxInt(64) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (Rsh64x8 x y) - // cond: shiftIsBounded(v) - // result: (SARQ x y) + // match: (SHRL x (ANDLconst [c] y)) + // cond: c & 31 == 31 + // result: (SHRL x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ANDLconst { break } - v.reset(OpAMD64SARQ) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh8Ux16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) + // match: (SHRL x (NEGL (ANDLconst [c] y))) + // cond: c & 31 == 31 + // result: (SHRL x (NEGL y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGL { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(8) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Rsh8Ux16 x y) - // cond: shiftIsBounded(v) - // result: (SHRB x y) + // match: (SHRL l:(MOVLload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHRXLload [off] {sym} ptr x mem) for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + l := v_0 + if l.Op != OpAMD64MOVLload { break } - v.reset(OpAMD64SHRB) - v.AddArg2(x, y) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHRXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } return false } -func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Rsh8Ux32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) + // match: (SHRLconst [1] (ADDL x x)) + // result: (ANDLconst [0x7fffffff] x) for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64ADDL { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(8) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + x := v_0.Args[1] + if x != v_0.Args[0] { + break + } + v.reset(OpAMD64ANDLconst) + v.AuxInt = int32ToAuxInt(0x7fffffff) + v.AddArg(x) return true } - // match: (Rsh8Ux32 x y) - // cond: shiftIsBounded(v) - // result: (SHRB x y) + // match: (SHRLconst x [0]) + // result: x for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if auxIntToInt8(v.AuxInt) != 0 { break } - v.reset(OpAMD64SHRB) - v.AddArg2(x, y) + x := v_0 + v.copyOf(x) return true } return false } -func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool { +func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh8Ux64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) + // match: (SHRQ x (MOVQconst [c])) + // result: (SHRQconst [int8(c&63)] x) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64MOVQconst { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(8) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHRQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) return true } - // match: (Rsh8Ux64 x y) - // cond: shiftIsBounded(v) - // result: (SHRB x y) + // match: (SHRQ x (MOVLconst [c])) + // result: (SHRQconst [int8(c&63)] x) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64MOVLconst { break } - v.reset(OpAMD64SHRB) - v.AddArg2(x, y) + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHRQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) return true } - return false -} -func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh8Ux8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) + // match: (SHRQ x (ADDQconst [c] y)) + // cond: c & 63 == 0 + // result: (SHRQ x y) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64ADDQconst { break } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(8) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) - return true - } - // match: (Rsh8Ux8 x y) - // cond: shiftIsBounded(v) - // result: (SHRB x y) - for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { break } - v.reset(OpAMD64SHRB) + v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh8x16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh8x16 x y) - // cond: !shiftIsBounded(v) - // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) + // match: (SHRQ x (NEGQ (ADDQconst [c] y))) + // cond: c & 63 == 0 + // result: (SHRQ x (NEGQ y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64SARB) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v3.AuxInt = int16ToAuxInt(8) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (Rsh8x16 x y) - // cond: shiftIsBounded(v) - // result: (SARB x y) + // match: (SHRQ x (ANDQconst [c] y)) + // cond: c & 63 == 63 + // result: (SHRQ x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ANDQconst { break } - v.reset(OpAMD64SARB) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh8x32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh8x32 x y) - // cond: !shiftIsBounded(v) - // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) + // match: (SHRQ x (NEGQ (ANDQconst [c] y))) + // cond: c & 63 == 63 + // result: (SHRQ x (NEGQ y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGQ { break } - v.reset(OpAMD64SARB) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v3.AuxInt = int32ToAuxInt(8) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (Rsh8x32 x y) - // cond: shiftIsBounded(v) - // result: (SARB x y) + // match: (SHRQ x (ADDLconst [c] y)) + // cond: c & 63 == 0 + // result: (SHRQ x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ADDLconst { break } - v.reset(OpAMD64SARB) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh8x64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh8x64 x y) - // cond: !shiftIsBounded(v) - // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) + // match: (SHRQ x (NEGL (ADDLconst [c] y))) + // cond: c & 63 == 0 + // result: (SHRQ x (NEGL y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGL { break } - v.reset(OpAMD64SARB) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v3.AuxInt = int32ToAuxInt(8) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (Rsh8x64 x y) - // cond: shiftIsBounded(v) - // result: (SARB x y) + // match: (SHRQ x (ANDLconst [c] y)) + // cond: c & 63 == 63 + // result: (SHRQ x y) for { x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + if v_1.Op != OpAMD64ANDLconst { break } - v.reset(OpAMD64SARB) + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } - return false -} -func rewriteValueAMD64_OpRsh8x8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Rsh8x8 x y) - // cond: !shiftIsBounded(v) - // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) + // match: (SHRQ x (NEGL (ANDLconst [c] y))) + // cond: c & 63 == 63 + // result: (SHRQ x (NEGL y)) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpAMD64NEGL { break } - v.reset(OpAMD64SARB) - v.Type = t - v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) - v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) - v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) - v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v3.AuxInt = int8ToAuxInt(8) - v3.AddArg(y) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(y, v1) + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) v.AddArg2(x, v0) return true } - // match: (Rsh8x8 x y) - // cond: shiftIsBounded(v) - // result: (SARB x y) + // match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHRXQload [off] {sym} ptr x mem) for { - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + l := v_0 + if l.Op != OpAMD64MOVQload { break } - v.reset(OpAMD64SARB) - v.AddArg2(x, y) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHRXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) return true } return false } -func rewriteValueAMD64_OpSelect0(v *Value) bool { +func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Select0 (Mul64uover x y)) - // result: (Select0 (MULQU x y)) + // match: (SHRQconst [1] (ADDQ x x)) + // result: (BTRQconst [63] x) for { - if v_0.Op != OpMul64uover { + if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64ADDQ { break } - y := v_0.Args[1] - x := v_0.Args[0] - v.reset(OpSelect0) - v.Type = typ.UInt64 - v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - // match: (Select0 (Mul32uover x y)) - // result: (Select0 (MULLU x y)) - for { - if v_0.Op != OpMul32uover { + x := v_0.Args[1] + if x != v_0.Args[0] { break } - y := v_0.Args[1] - x := v_0.Args[0] - v.reset(OpSelect0) - v.Type = typ.UInt32 - v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) - v0.AddArg2(x, y) - v.AddArg(v0) + v.reset(OpAMD64BTRQconst) + v.AuxInt = int8ToAuxInt(63) + v.AddArg(x) return true } - // match: (Select0 (Add64carry x y c)) - // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) + // match: (SHRQconst x [0]) + // result: x for { - if v_0.Op != OpAdd64carry { + if auxIntToInt8(v.AuxInt) != 0 { break } - c := v_0.Args[2] - x := v_0.Args[0] - y := v_0.Args[1] - v.reset(OpSelect0) - v.Type = typ.UInt64 - v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) - v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) - v2.AddArg(c) - v1.AddArg(v2) - v0.AddArg3(x, y, v1) - v.AddArg(v0) + x := v_0 + v.copyOf(x) return true } - // match: (Select0 (Sub64borrow x y c)) - // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) + return false +} +func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SHRW x (MOVQconst [c])) + // cond: c&31 < 16 + // result: (SHRWconst [int8(c&31)] x) for { - if v_0.Op != OpSub64borrow { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - c := v_0.Args[2] - x := v_0.Args[0] - y := v_0.Args[1] - v.reset(OpSelect0) - v.Type = typ.UInt64 - v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) - v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) - v2.AddArg(c) - v1.AddArg(v2) - v0.AddArg3(x, y, v1) - v.AddArg(v0) + c := auxIntToInt64(v_1.AuxInt) + if !(c&31 < 16) { + break + } + v.reset(OpAMD64SHRWconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) return true } - // match: (Select0 (AddTupleFirst32 val tuple)) - // result: (ADDL val (Select0 tuple)) + // match: (SHRW x (MOVLconst [c])) + // cond: c&31 < 16 + // result: (SHRWconst [int8(c&31)] x) for { - t := v.Type - if v_0.Op != OpAMD64AddTupleFirst32 { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - tuple := v_0.Args[1] - val := v_0.Args[0] - v.reset(OpAMD64ADDL) - v0 := b.NewValue0(v.Pos, OpSelect0, t) - v0.AddArg(tuple) - v.AddArg2(val, v0) + c := auxIntToInt32(v_1.AuxInt) + if !(c&31 < 16) { + break + } + v.reset(OpAMD64SHRWconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) return true } - // match: (Select0 (AddTupleFirst64 val tuple)) - // result: (ADDQ val (Select0 tuple)) + // match: (SHRW _ (MOVQconst [c])) + // cond: c&31 >= 16 + // result: (MOVLconst [0]) for { - t := v.Type - if v_0.Op != OpAMD64AddTupleFirst64 { + if v_1.Op != OpAMD64MOVQconst { break } - tuple := v_0.Args[1] - val := v_0.Args[0] - v.reset(OpAMD64ADDQ) - v0 := b.NewValue0(v.Pos, OpSelect0, t) - v0.AddArg(tuple) - v.AddArg2(val, v0) + c := auxIntToInt64(v_1.AuxInt) + if !(c&31 >= 16) { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (Select0 a:(ADDQconstflags [c] x)) - // cond: a.Uses == 1 - // result: (ADDQconst [c] x) + // match: (SHRW _ (MOVLconst [c])) + // cond: c&31 >= 16 + // result: (MOVLconst [0]) for { - a := v_0 - if a.Op != OpAMD64ADDQconstflags { + if v_1.Op != OpAMD64MOVLconst { break } - c := auxIntToInt32(a.AuxInt) - x := a.Args[0] - if !(a.Uses == 1) { + c := auxIntToInt32(v_1.AuxInt) + if !(c&31 >= 16) { break } - v.reset(OpAMD64ADDQconst) - v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (Select0 a:(ADDLconstflags [c] x)) - // cond: a.Uses == 1 - // result: (ADDLconst [c] x) + return false +} +func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { + v_0 := v.Args[0] + // match: (SHRWconst x [0]) + // result: x for { - a := v_0 - if a.Op != OpAMD64ADDLconstflags { - break - } - c := auxIntToInt32(a.AuxInt) - x := a.Args[0] - if !(a.Uses == 1) { + if auxIntToInt8(v.AuxInt) != 0 { break } - v.reset(OpAMD64ADDLconst) - v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) + x := v_0 + v.copyOf(x) return true } return false } -func rewriteValueAMD64_OpSelect1(v *Value) bool { +func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Select1 (Mul64uover x y)) - // result: (SETO (Select1 (MULQU x y))) + // match: (SHRXLload [off] {sym} ptr (MOVLconst [c]) mem) + // result: (SHRLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { - if v_0.Op != OpMul64uover { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - y := v_0.Args[1] - x := v_0.Args[0] - v.reset(OpAMD64SETO) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) - v1.AddArg2(x, y) - v0.AddArg(v1) + c := auxIntToInt32(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64SHRLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) v.AddArg(v0) return true } - // match: (Select1 (Mul32uover x y)) - // result: (SETO (Select1 (MULLU x y))) + return false +} +func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (SHRXQload [off] {sym} ptr (MOVQconst [c]) mem) + // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { - if v_0.Op != OpMul32uover { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - y := v_0.Args[1] - x := v_0.Args[0] - v.reset(OpAMD64SETO) - v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) - v1.AddArg2(x, y) - v0.AddArg(v1) + c := auxIntToInt64(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64SHRQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) v.AddArg(v0) return true } - // match: (Select1 (Add64carry x y c)) - // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) + // match: (SHRXQload [off] {sym} ptr (MOVLconst [c]) mem) + // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { - if v_0.Op != OpAdd64carry { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - c := v_0.Args[2] - x := v_0.Args[0] - y := v_0.Args[1] - v.reset(OpAMD64NEGQ) - v.Type = typ.UInt64 - v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) - v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) - v4.AddArg(c) - v3.AddArg(v4) - v2.AddArg3(x, y, v3) - v1.AddArg(v2) - v0.AddArg(v1) + c := auxIntToInt32(v_1.AuxInt) + mem := v_2 + v.reset(OpAMD64SHRQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) v.AddArg(v0) return true } - // match: (Select1 (Sub64borrow x y c)) - // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) + return false +} +func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (SUBL x (MOVLconst [c])) + // result: (SUBLconst x [c]) for { - if v_0.Op != OpSub64borrow { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { break } - c := v_0.Args[2] - x := v_0.Args[0] - y := v_0.Args[1] - v.reset(OpAMD64NEGQ) - v.Type = typ.UInt64 - v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) - v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) - v4.AddArg(c) - v3.AddArg(v4) - v2.AddArg3(x, y, v3) - v1.AddArg(v2) - v0.AddArg(v1) - v.AddArg(v0) + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SUBLconst) + v.AuxInt = int32ToAuxInt(c) + v.AddArg(x) return true } - // match: (Select1 (NEGLflags (MOVQconst [0]))) - // result: (FlagEQ) + // match: (SUBL (MOVLconst [c]) x) + // result: (NEGL (SUBLconst x [c])) for { - if v_0.Op != OpAMD64NEGLflags { + if v_0.Op != OpAMD64MOVLconst { break } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 { + c := auxIntToInt32(v_0.AuxInt) + x := v_1 + v.reset(OpAMD64NEGL) + v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) + v0.AuxInt = int32ToAuxInt(c) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (SUBL x x) + // result: (MOVLconst [0]) + for { + x := v_0 + if x != v_1 { break } - v.reset(OpAMD64FlagEQ) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) - // result: x + // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (SUBLload x [off] {sym} ptr mem) for { - if v_0.Op != OpAMD64NEGLflags { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVLload { break } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64NEGQ { + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64SBBQcarrymask { + v.reset(OpAMD64SUBLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SUBLconst(v *Value) bool { + v_0 := v.Args[0] + // match: (SUBLconst [0] x) + // result: x + for { + if auxIntToInt32(v.AuxInt) != 0 { break } - x := v_0_0_0.Args[0] + x := v_0 v.copyOf(x) return true } - // match: (Select1 (AddTupleFirst32 _ tuple)) - // result: (Select1 tuple) + // match: (SUBLconst [c] x) + // result: (ADDLconst [-c] x) for { - if v_0.Op != OpAMD64AddTupleFirst32 { - break - } - tuple := v_0.Args[1] - v.reset(OpSelect1) - v.AddArg(tuple) + c := auxIntToInt32(v.AuxInt) + x := v_0 + v.reset(OpAMD64ADDLconst) + v.AuxInt = int32ToAuxInt(-c) + v.AddArg(x) return true } - // match: (Select1 (AddTupleFirst64 _ tuple)) - // result: (Select1 tuple) +} +func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SUBLload [off1+off2] {sym} val base mem) for { - if v_0.Op != OpAMD64AddTupleFirst64 { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { break } - tuple := v_0.Args[1] - v.reset(OpSelect1) - v.AddArg(tuple) + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64SUBLload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, base, mem) return true } - // match: (Select1 a:(LoweredAtomicAnd64 ptr val mem)) - // cond: a.Uses == 1 && clobber(a) - // result: (ANDQlock ptr val mem) + // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { - a := v_0 - if a.Op != OpAMD64LoweredAtomicAnd64 { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { break } - mem := a.Args[2] - ptr := a.Args[0] - val := a.Args[1] - if !(a.Uses == 1 && clobber(a)) { + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64ANDQlock) - v.AddArg3(ptr, val, mem) + v.reset(OpAMD64SUBLload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, base, mem) return true } - // match: (Select1 a:(LoweredAtomicAnd32 ptr val mem)) - // cond: a.Uses == 1 && clobber(a) - // result: (ANDLlock ptr val mem) + // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) + // result: (SUBL x (MOVLf2i y)) for { - a := v_0 - if a.Op != OpAMD64LoweredAtomicAnd32 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + ptr := v_1 + if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } - mem := a.Args[2] - ptr := a.Args[0] - val := a.Args[1] - if !(a.Uses == 1 && clobber(a)) { + y := v_2.Args[1] + if ptr != v_2.Args[0] { break } - v.reset(OpAMD64ANDLlock) - v.AddArg3(ptr, val, mem) + v.reset(OpAMD64SUBL) + v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Select1 a:(LoweredAtomicOr64 ptr val mem)) - // cond: a.Uses == 1 && clobber(a) - // result: (ORQlock ptr val mem) + return false +} +func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SUBLmodify [off1+off2] {sym} base val mem) for { - a := v_0 - if a.Op != OpAMD64LoweredAtomicOr64 { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { break } - mem := a.Args[2] - ptr := a.Args[0] - val := a.Args[1] - if !(a.Uses == 1 && clobber(a)) { + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64ORQlock) - v.AddArg3(ptr, val, mem) + v.reset(OpAMD64SUBLmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) return true } - // match: (Select1 a:(LoweredAtomicOr32 ptr val mem)) - // cond: a.Uses == 1 && clobber(a) - // result: (ORLlock ptr val mem) + // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - a := v_0 - if a.Op != OpAMD64LoweredAtomicOr32 { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { break } - mem := a.Args[2] - ptr := a.Args[0] - val := a.Args[1] - if !(a.Uses == 1 && clobber(a)) { + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64ORLlock) - v.AddArg3(ptr, val, mem) + v.reset(OpAMD64SUBLmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } return false } -func rewriteValueAMD64_OpSelectN(v *Value) bool { +func rewriteValueAMD64_OpAMD64SUBQ(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - config := b.Func.Config - // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem))))) - // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call) - // result: (Move [sc.Val64()] dst src mem) + // match: (SUBQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (SUBQconst x [int32(c)]) for { - if auxIntToInt64(v.AuxInt) != 0 { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - call := v_0 - if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 { + c := auxIntToInt64(v_1.AuxInt) + if !(is32Bit(c)) { break } - sym := auxToCall(call.Aux) - s1 := call.Args[0] - if s1.Op != OpAMD64MOVQstoreconst { + v.reset(OpAMD64SUBQconst) + v.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg(x) + return true + } + // match: (SUBQ (MOVQconst [c]) x) + // cond: is32Bit(c) + // result: (NEGQ (SUBQconst x [int32(c)])) + for { + if v_0.Op != OpAMD64MOVQconst { break } - sc := auxIntToValAndOff(s1.AuxInt) - _ = s1.Args[1] - s2 := s1.Args[1] - if s2.Op != OpAMD64MOVQstore { - break - } - _ = s2.Args[2] - src := s2.Args[1] - s3 := s2.Args[2] - if s3.Op != OpAMD64MOVQstore { + c := auxIntToInt64(v_0.AuxInt) + x := v_1 + if !(is32Bit(c)) { break } - mem := s3.Args[2] - dst := s3.Args[1] - if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) { + v.reset(OpAMD64NEGQ) + v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) + v0.AuxInt = int32ToAuxInt(int32(c)) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (SUBQ x x) + // result: (MOVLconst [0]) + for { + x := v_0 + if x != v_1 { break } - v.reset(OpMove) - v.AuxInt = int64ToAuxInt(sc.Val64()) - v.AddArg3(dst, src, mem) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) return true } - // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem)) - // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) - // result: (Move [sz] dst src mem) + // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (SUBQload x [off] {sym} ptr mem) for { - if auxIntToInt64(v.AuxInt) != 0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVQload { break } - call := v_0 - if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 { + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } - sym := auxToCall(call.Aux) - mem := call.Args[3] - dst := call.Args[0] - src := call.Args[1] - call_2 := call.Args[2] - if call_2.Op != OpAMD64MOVQconst { + v.reset(OpAMD64SUBQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SUBQborrow(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SUBQborrow x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (SUBQconstborrow x [int32(c)]) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { break } - sz := auxIntToInt64(call_2.AuxInt) - if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { + c := auxIntToInt64(v_1.AuxInt) + if !(is32Bit(c)) { break } - v.reset(OpMove) - v.AuxInt = int64ToAuxInt(sz) - v.AddArg3(dst, src, mem) + v.reset(OpAMD64SUBQconstborrow) + v.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg(x) return true } return false } -func rewriteValueAMD64_OpSlicemask(v *Value) bool { +func rewriteValueAMD64_OpAMD64SUBQconst(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Slicemask x) - // result: (SARQconst (NEGQ x) [63]) + // match: (SUBQconst [0] x) + // result: x for { - t := v.Type + if auxIntToInt32(v.AuxInt) != 0 { + break + } x := v_0 - v.reset(OpAMD64SARQconst) - v.AuxInt = int8ToAuxInt(63) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(x) - v.AddArg(v0) + v.copyOf(x) return true } -} -func rewriteValueAMD64_OpSpectreIndex(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SpectreIndex x y) - // result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y)) + // match: (SUBQconst [c] x) + // cond: c != -(1<<31) + // result: (ADDQconst [-c] x) for { + c := auxIntToInt32(v.AuxInt) x := v_0 - y := v_1 - v.reset(OpAMD64CMOVQCC) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(0) - v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v1.AddArg2(x, y) - v.AddArg3(x, v0, v1) + if !(c != -(1 << 31)) { + break + } + v.reset(OpAMD64ADDQconst) + v.AuxInt = int32ToAuxInt(-c) + v.AddArg(x) return true } -} -func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (SpectreSliceIndex x y) - // result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y)) + // match: (SUBQconst (MOVQconst [d]) [c]) + // result: (MOVQconst [d-int64(c)]) for { - x := v_0 - y := v_1 - v.reset(OpAMD64CMOVQHI) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(0) - v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v1.AddArg2(x, y) - v.AddArg3(x, v0, v1) + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { + break + } + d := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(d - int64(c)) + return true + } + // match: (SUBQconst (SUBQconst x [d]) [c]) + // cond: is32Bit(int64(-c)-int64(d)) + // result: (ADDQconst [-c-d] x) + for { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64SUBQconst { + break + } + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(is32Bit(int64(-c) - int64(d))) { + break + } + v.reset(OpAMD64ADDQconst) + v.AuxInt = int32ToAuxInt(-c - d) + v.AddArg(x) return true } + return false } -func rewriteValueAMD64_OpStore(v *Value) bool { +func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (Store {t} ptr val mem) - // cond: t.Size() == 8 && t.IsFloat() - // result: (MOVSDstore ptr val mem) + b := v.Block + typ := &b.Func.Config.Types + // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SUBQload [off1+off2] {sym} val base mem) for { - t := auxToType(v.Aux) - ptr := v_0 - val := v_1 - mem := v_2 - if !(t.Size() == 8 && t.IsFloat()) { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { break } - v.reset(OpAMD64MOVSDstore) - v.AddArg3(ptr, val, mem) - return true - } - // match: (Store {t} ptr val mem) - // cond: t.Size() == 4 && t.IsFloat() - // result: (MOVSSstore ptr val mem) - for { - t := auxToType(v.Aux) - ptr := v_0 - val := v_1 + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] mem := v_2 - if !(t.Size() == 4 && t.IsFloat()) { + if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64MOVSSstore) - v.AddArg3(ptr, val, mem) + v.reset(OpAMD64SUBQload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, base, mem) return true } - // match: (Store {t} ptr val mem) - // cond: t.Size() == 8 && !t.IsFloat() - // result: (MOVQstore ptr val mem) + // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { - t := auxToType(v.Aux) - ptr := v_0 - val := v_1 + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] mem := v_2 - if !(t.Size() == 8 && !t.IsFloat()) { + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64MOVQstore) - v.AddArg3(ptr, val, mem) + v.reset(OpAMD64SUBQload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, base, mem) return true } - // match: (Store {t} ptr val mem) - // cond: t.Size() == 4 && !t.IsFloat() - // result: (MOVLstore ptr val mem) + // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) + // result: (SUBQ x (MOVQf2i y)) for { - t := auxToType(v.Aux) - ptr := v_0 - val := v_1 - mem := v_2 - if !(t.Size() == 4 && !t.IsFloat()) { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + ptr := v_1 + if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } - v.reset(OpAMD64MOVLstore) - v.AddArg3(ptr, val, mem) + y := v_2.Args[1] + if ptr != v_2.Args[0] { + break + } + v.reset(OpAMD64SUBQ) + v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Store {t} ptr val mem) - // cond: t.Size() == 2 - // result: (MOVWstore ptr val mem) + return false +} +func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SUBQmodify [off1+off2] {sym} base val mem) for { - t := auxToType(v.Aux) - ptr := v_0 + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] val := v_1 mem := v_2 - if !(t.Size() == 2) { + if !(is32Bit(int64(off1) + int64(off2))) { break } - v.reset(OpAMD64MOVWstore) - v.AddArg3(ptr, val, mem) + v.reset(OpAMD64SUBQmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) return true } - // match: (Store {t} ptr val mem) - // cond: t.Size() == 1 - // result: (MOVBstore ptr val mem) + // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { - t := auxToType(v.Aux) - ptr := v_0 + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] val := v_1 mem := v_2 - if !(t.Size() == 1) { + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } - v.reset(OpAMD64MOVBstore) - v.AddArg3(ptr, val, mem) + v.reset(OpAMD64SUBQmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) return true } return false } -func rewriteValueAMD64_OpTrunc(v *Value) bool { +func rewriteValueAMD64_OpAMD64SUBSD(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (Trunc x) - // result: (ROUNDSD [3] x) + // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (SUBSDload x [off] {sym} ptr mem) for { x := v_0 - v.reset(OpAMD64ROUNDSD) - v.AuxInt = int8ToAuxInt(3) - v.AddArg(x) + l := v_1 + if l.Op != OpAMD64MOVSDload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + break + } + v.reset(OpAMD64SUBSDload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) return true } + return false } -func rewriteValueAMD64_OpZero(v *Value) bool { +func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Zero [0] _ mem) - // result: mem + // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SUBSDload [off1+off2] {sym} val base mem) for { - if auxIntToInt64(v.AuxInt) != 0 { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { break } - mem := v_1 - v.copyOf(mem) + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64SUBSDload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, base, mem) return true } - // match: (Zero [1] destptr mem) - // result: (MOVBstoreconst [makeValAndOff(0,0)] destptr mem) + // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { - if auxIntToInt64(v.AuxInt) != 1 { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { break } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVBstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v.AddArg2(destptr, mem) + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64SUBSDload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, base, mem) return true } - // match: (Zero [2] destptr mem) - // result: (MOVWstoreconst [makeValAndOff(0,0)] destptr mem) + // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) + // result: (SUBSD x (MOVQi2f y)) for { - if auxIntToInt64(v.AuxInt) != 2 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + ptr := v_1 + if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v.AddArg2(destptr, mem) + y := v_2.Args[1] + if ptr != v_2.Args[0] { + break + } + v.reset(OpAMD64SUBSD) + v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Zero [4] destptr mem) - // result: (MOVLstoreconst [makeValAndOff(0,0)] destptr mem) + return false +} +func rewriteValueAMD64_OpAMD64SUBSS(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (SUBSSload x [off] {sym} ptr mem) for { - if auxIntToInt64(v.AuxInt) != 4 { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVSSload { break } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v.AddArg2(destptr, mem) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + break + } + v.reset(OpAMD64SUBSSload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) return true } - // match: (Zero [8] destptr mem) - // result: (MOVQstoreconst [makeValAndOff(0,0)] destptr mem) + return false +} +func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (SUBSSload [off1+off2] {sym} val base mem) for { - if auxIntToInt64(v.AuxInt) != 8 { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { break } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVQstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v.AddArg2(destptr, mem) + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64SUBSSload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, base, mem) return true } - // match: (Zero [3] destptr mem) - // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) + // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { - if auxIntToInt64(v.AuxInt) != 3 { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { break } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVBstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 2)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v0.AddArg2(destptr, mem) - v.AddArg2(destptr, v0) + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64SUBSSload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, base, mem) return true } - // match: (Zero [5] destptr mem) - // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) + // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) + // result: (SUBSS x (MOVLi2f y)) for { - if auxIntToInt64(v.AuxInt) != 5 { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + ptr := v_1 + if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVBstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v0.AddArg2(destptr, mem) - v.AddArg2(destptr, v0) - return true - } - // match: (Zero [6] destptr mem) - // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) - for { - if auxIntToInt64(v.AuxInt) != 6 { + y := v_2.Args[1] + if ptr != v_2.Args[0] { break } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v0.AddArg2(destptr, mem) - v.AddArg2(destptr, v0) + v.reset(OpAMD64SUBSS) + v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) + v0.AddArg(y) + v.AddArg2(x, v0) return true } - // match: (Zero [7] destptr mem) - // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) + return false +} +func rewriteValueAMD64_OpAMD64TESTB(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (TESTB (MOVLconst [c]) x) + // result: (TESTBconst [int8(c)] x) for { - if auxIntToInt64(v.AuxInt) != 7 { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := auxIntToInt32(v_0.AuxInt) + x := v_1 + v.reset(OpAMD64TESTBconst) + v.AuxInt = int8ToAuxInt(int8(c)) + v.AddArg(x) + return true } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 3)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v0.AddArg2(destptr, mem) - v.AddArg2(destptr, v0) - return true + break } - // match: (Zero [9] destptr mem) - // result: (MOVBstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) + // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) + // cond: l == l2 && l.Uses == 2 && clobber(l) + // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0, off)] ptr mem) for { - if auxIntToInt64(v.AuxInt) != 9 { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + l := v_0 + if l.Op != OpAMD64MOVBload { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + l2 := v_1 + if !(l == l2 && l.Uses == 2 && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) + v.copyOf(v0) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + return true } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVBstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v0.AddArg2(destptr, mem) - v.AddArg2(destptr, v0) - return true + break } - // match: (Zero [10] destptr mem) - // result: (MOVWstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) + return false +} +func rewriteValueAMD64_OpAMD64TESTBconst(v *Value) bool { + v_0 := v.Args[0] + // match: (TESTBconst [-1] x) + // cond: x.Op != OpAMD64MOVLconst + // result: (TESTB x x) for { - if auxIntToInt64(v.AuxInt) != 10 { + if auxIntToInt8(v.AuxInt) != -1 { break } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v0.AddArg2(destptr, mem) - v.AddArg2(destptr, v0) + x := v_0 + if !(x.Op != OpAMD64MOVLconst) { + break + } + v.reset(OpAMD64TESTB) + v.AddArg2(x, x) return true } - // match: (Zero [11] destptr mem) - // result: (MOVLstoreconst [makeValAndOff(0,7)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) + return false +} +func rewriteValueAMD64_OpAMD64TESTL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (TESTL (MOVLconst [c]) x) + // result: (TESTLconst [c] x) for { - if auxIntToInt64(v.AuxInt) != 11 { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := auxIntToInt32(v_0.AuxInt) + x := v_1 + v.reset(OpAMD64TESTLconst) + v.AuxInt = int32ToAuxInt(c) + v.AddArg(x) + return true } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 7)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v0.AddArg2(destptr, mem) - v.AddArg2(destptr, v0) - return true + break } - // match: (Zero [12] destptr mem) - // result: (MOVLstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) + // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) + // cond: l == l2 && l.Uses == 2 && clobber(l) + // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0, off)] ptr mem) for { - if auxIntToInt64(v.AuxInt) != 12 { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + l := v_0 + if l.Op != OpAMD64MOVLload { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + l2 := v_1 + if !(l == l2 && l.Uses == 2 && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) + v.copyOf(v0) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + return true } - destptr := v_0 - mem := v_1 - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v0.AddArg2(destptr, mem) - v.AddArg2(destptr, v0) - return true + break } - // match: (Zero [s] destptr mem) - // cond: s > 12 && s < 16 - // result: (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) + // match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a) + // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) + // result: (TESTL (MOVLload [off] {sym} ptr mem) x) for { - s := auxIntToInt64(v.AuxInt) - destptr := v_0 - mem := v_1 - if !(s > 12 && s < 16) { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + a := v_0 + if a.Op != OpAMD64ANDLload { + continue + } + off := auxIntToInt32(a.AuxInt) + sym := auxToSym(a.Aux) + mem := a.Args[2] + x := a.Args[0] + ptr := a.Args[1] + if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { + continue + } + v.reset(OpAMD64TESTL) + v0 := b.NewValue0(a.Pos, OpAMD64MOVLload, a.Type) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + v.AddArg2(v0, x) + return true } - v.reset(OpAMD64MOVQstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, int32(s-8))) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) - v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v0.AddArg2(destptr, mem) - v.AddArg2(destptr, v0) - return true + break } - // match: (Zero [s] destptr mem) - // cond: s >= 16 && s < 192 - // result: (LoweredZero [s] destptr mem) + return false +} +func rewriteValueAMD64_OpAMD64TESTLconst(v *Value) bool { + v_0 := v.Args[0] + // match: (TESTLconst [c] (MOVLconst [c])) + // cond: c == 0 + // result: (FlagEQ) for { - s := auxIntToInt64(v.AuxInt) - destptr := v_0 - mem := v_1 - if !(s >= 16 && s < 192) { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c == 0) { break } - v.reset(OpAMD64LoweredZero) - v.AuxInt = int64ToAuxInt(s) - v.AddArg2(destptr, mem) + v.reset(OpAMD64FlagEQ) return true } - // match: (Zero [s] destptr mem) - // cond: s >= 192 && s <= repZeroThreshold - // result: (LoweredZeroLoop [s] destptr mem) + // match: (TESTLconst [c] (MOVLconst [c])) + // cond: c < 0 + // result: (FlagLT_UGT) for { - s := auxIntToInt64(v.AuxInt) - destptr := v_0 - mem := v_1 - if !(s >= 192 && s <= repZeroThreshold) { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c < 0) { break } - v.reset(OpAMD64LoweredZeroLoop) - v.AuxInt = int64ToAuxInt(s) - v.AddArg2(destptr, mem) + v.reset(OpAMD64FlagLT_UGT) return true } - // match: (Zero [s] destptr mem) - // cond: s > repZeroThreshold && s%8 != 0 - // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) + // match: (TESTLconst [c] (MOVLconst [c])) + // cond: c > 0 + // result: (FlagGT_UGT) for { - s := auxIntToInt64(v.AuxInt) - destptr := v_0 - mem := v_1 - if !(s > repZeroThreshold && s%8 != 0) { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c > 0) { break } - v.reset(OpZero) - v.AuxInt = int64ToAuxInt(s - s%8) - v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) - v0.AuxInt = int64ToAuxInt(s % 8) - v0.AddArg(destptr) - v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) - v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) - v1.AddArg2(destptr, mem) - v.AddArg2(v0, v1) + v.reset(OpAMD64FlagGT_UGT) return true } - // match: (Zero [s] destptr mem) - // cond: s > repZeroThreshold && s%8 == 0 - // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) + // match: (TESTLconst [-1] x) + // cond: x.Op != OpAMD64MOVLconst + // result: (TESTL x x) for { - s := auxIntToInt64(v.AuxInt) - destptr := v_0 - mem := v_1 - if !(s > repZeroThreshold && s%8 == 0) { + if auxIntToInt32(v.AuxInt) != -1 { break } - v.reset(OpAMD64REPSTOSQ) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(s / 8) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) - v1.AuxInt = int64ToAuxInt(0) - v.AddArg4(destptr, v0, v1, mem) + x := v_0 + if !(x.Op != OpAMD64MOVLconst) { + break + } + v.reset(OpAMD64TESTL) + v.AddArg2(x, x) return true } return false } -func rewriteBlockAMD64(b *Block) bool { - typ := &b.Func.Config.Types - switch b.Kind { - case BlockAMD64EQ: - // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) - // result: (UGE (BTL x y)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64UGE, v0) - return true +func rewriteValueAMD64_OpAMD64TESTQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (TESTQ (MOVQconst [c]) x) + // cond: is32Bit(c) + // result: (TESTQconst [int32(c)] x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64MOVQconst { + continue } - break - } - // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) - // result: (UGE (BTQ x y)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64UGE, v0) - return true + c := auxIntToInt64(v_0.AuxInt) + x := v_1 + if !(is32Bit(c)) { + continue } - break + v.reset(OpAMD64TESTQconst) + v.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg(x) + return true } - // match: (EQ (TESTLconst [c] x)) - // cond: isUnsignedPowerOfTwo(uint32(c)) - // result: (UGE (BTLconst [int8(log32u(uint32(c)))] x)) - for b.Controls[0].Op == OpAMD64TESTLconst { - v_0 := b.Controls[0] - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(isUnsignedPowerOfTwo(uint32(c))) { - break + break + } + // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) + // cond: l == l2 && l.Uses == 2 && clobber(l) + // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0, off)] ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + l := v_0 + if l.Op != OpAMD64MOVQload { + continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - b.resetWithControl(BlockAMD64UGE, v0) + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + l2 := v_1 + if !(l == l2 && l.Uses == 2 && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) + v.copyOf(v0) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) return true } - // match: (EQ (TESTQconst [c] x)) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (UGE (BTQconst [int8(log32u(uint32(c)))] x)) - for b.Controls[0].Op == OpAMD64TESTQconst { - v_0 := b.Controls[0] - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(isUnsignedPowerOfTwo(uint64(c))) { - break + break + } + // match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a) + // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) + // result: (TESTQ (MOVQload [off] {sym} ptr mem) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + a := v_0 + if a.Op != OpAMD64ANDQload { + continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - b.resetWithControl(BlockAMD64UGE, v0) + off := auxIntToInt32(a.AuxInt) + sym := auxToSym(a.Aux) + mem := a.Args[2] + x := a.Args[0] + ptr := a.Args[1] + if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { + continue + } + v.reset(OpAMD64TESTQ) + v0 := b.NewValue0(a.Pos, OpAMD64MOVQload, a.Type) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + v.AddArg2(v0, x) return true } - // match: (EQ (TESTQ (MOVQconst [c]) x)) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (UGE (BTQconst [int8(log64u(uint64(c)))] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64MOVQconst { - continue - } - c := auxIntToInt64(v_0_0.AuxInt) - x := v_0_1 - if !(isUnsignedPowerOfTwo(uint64(c))) { - continue - } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) - v0.AddArg(x) - b.resetWithControl(BlockAMD64UGE, v0) - return true - } + break + } + return false +} +func rewriteValueAMD64_OpAMD64TESTQconst(v *Value) bool { + v_0 := v.Args[0] + // match: (TESTQconst [c] (MOVQconst [d])) + // cond: int64(c) == d && c == 0 + // result: (FlagEQ) + for { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { break } - // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) - // cond: z1==z2 - // result: (UGE (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { - continue - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { - continue - } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { - continue - } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - b.resetWithControl(BlockAMD64UGE, v0) - return true - } + d := auxIntToInt64(v_0.AuxInt) + if !(int64(c) == d && c == 0) { break } - // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) + v.reset(OpAMD64FlagEQ) + return true + } + // match: (TESTQconst [c] (MOVQconst [d])) + // cond: int64(c) == d && c < 0 + // result: (FlagLT_UGT) + for { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { + break + } + d := auxIntToInt64(v_0.AuxInt) + if !(int64(c) == d && c < 0) { + break + } + v.reset(OpAMD64FlagLT_UGT) + return true + } + // match: (TESTQconst [c] (MOVQconst [d])) + // cond: int64(c) == d && c > 0 + // result: (FlagGT_UGT) + for { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { + break + } + d := auxIntToInt64(v_0.AuxInt) + if !(int64(c) == d && c > 0) { + break + } + v.reset(OpAMD64FlagGT_UGT) + return true + } + // match: (TESTQconst [-1] x) + // cond: x.Op != OpAMD64MOVQconst + // result: (TESTQ x x) + for { + if auxIntToInt32(v.AuxInt) != -1 { + break + } + x := v_0 + if !(x.Op != OpAMD64MOVQconst) { + break + } + v.reset(OpAMD64TESTQ) + v.AddArg2(x, x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64TESTW(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (TESTW (MOVLconst [c]) x) + // result: (TESTWconst [int16(c)] x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := auxIntToInt32(v_0.AuxInt) + x := v_1 + v.reset(OpAMD64TESTWconst) + v.AuxInt = int16ToAuxInt(int16(c)) + v.AddArg(x) + return true + } + break + } + // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) + // cond: l == l2 && l.Uses == 2 && clobber(l) + // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0, off)] ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + l := v_0 + if l.Op != OpAMD64MOVWload { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + l2 := v_1 + if !(l == l2 && l.Uses == 2 && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) + v.copyOf(v0) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { + v_0 := v.Args[0] + // match: (TESTWconst [-1] x) + // cond: x.Op != OpAMD64MOVLconst + // result: (TESTW x x) + for { + if auxIntToInt16(v.AuxInt) != -1 { + break + } + x := v_0 + if !(x.Op != OpAMD64MOVLconst) { + break + } + v.reset(OpAMD64TESTW) + v.AddArg2(x, x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPS128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPS256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPS512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPS512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPSMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPSMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPSMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPSMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDPSMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDPSMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VADDPSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VADDSUBPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDSUBPD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VADDSUBPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VADDSUBPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDSUBPD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VADDSUBPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VADDSUBPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDSUBPS128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VADDSUBPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VADDSUBPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VADDSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VADDSUBPS256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VADDSUBPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VAESDEC128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VAESDEC128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VAESDEC128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VAESDEC128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VAESDEC256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VAESDEC256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VAESDEC256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VAESDEC256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VAESDECLAST128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VAESDECLAST128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VAESDECLAST128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VAESDECLAST128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VAESDECLAST256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VAESDECLAST256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VAESDECLAST256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VAESDECLAST256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VAESENC128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VAESENC128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VAESENC128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VAESENC128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VAESENC256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VAESENC256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VAESENC256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VAESENC256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VAESENCLAST128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VAESENCLAST128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VAESENCLAST128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VAESENCLAST128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VAESENCLAST256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VAESENCLAST256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VAESENCLAST256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VAESENCLAST256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VAESIMC128(v *Value) bool { + v_0 := v.Args[0] + // match: (VAESIMC128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VAESIMC128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VAESIMC128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VAESKEYGENASSIST128(v *Value) bool { + v_0 := v.Args[0] + // match: (VAESKEYGENASSIST128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VAESKEYGENASSIST128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VAESKEYGENASSIST128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VBROADCASTSD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VBROADCASTSD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx) && canMergeLoad(v, l) && clobber(l) + // result: (VBROADCASTSD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx) && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VBROADCASTSD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VBROADCASTSD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VBROADCASTSD512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VBROADCASTSD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VBROADCASTSD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VBROADCASTSDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VBROADCASTSDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VBROADCASTSDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VBROADCASTSDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VBROADCASTSDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VBROADCASTSDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VBROADCASTSDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VBROADCASTSDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VBROADCASTSS128(v *Value) bool { + v_0 := v.Args[0] + // match: (VBROADCASTSS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx) && canMergeLoad(v, l) && clobber(l) + // result: (VBROADCASTSS128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx) && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VBROADCASTSS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VBROADCASTSS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VBROADCASTSS256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx) && canMergeLoad(v, l) && clobber(l) + // result: (VBROADCASTSS256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx) && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VBROADCASTSS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VBROADCASTSS512(v *Value) bool { + v_0 := v.Args[0] + // match: (VBROADCASTSS512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VBROADCASTSS512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VBROADCASTSS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VBROADCASTSSMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VBROADCASTSSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VBROADCASTSSMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VBROADCASTSSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VBROADCASTSSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VBROADCASTSSMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VBROADCASTSSMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VBROADCASTSSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VBROADCASTSSMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VBROADCASTSSMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VBROADCASTSSMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VBROADCASTSSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPD128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPD256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPDMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPDMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPDMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPS128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPS128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPS128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPS256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPS256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPS256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPS512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPS512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPS512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPS512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPSMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPSMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPSMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPSMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPSMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPSMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPSMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPSMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCMPPSMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCMPPSMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCMPPSMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCMPPSMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTDQ2PD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTDQ2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTDQ2PD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTDQ2PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTDQ2PD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTDQ2PD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTDQ2PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTDQ2PDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTDQ2PDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTDQ2PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTDQ2PDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTDQ2PDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTDQ2PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTDQ2PS128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTDQ2PS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTDQ2PS128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTDQ2PS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTDQ2PS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTDQ2PS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTDQ2PS256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTDQ2PS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTDQ2PS512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTDQ2PS512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTDQ2PS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTDQ2PSMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTDQ2PSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTDQ2PSMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTDQ2PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTDQ2PSMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTDQ2PSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTPD2PS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTPD2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTPD2PS256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTPD2PS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTPD2PSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTPD2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTPD2PSMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTPD2PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTPD2PSX128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTPD2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTPD2PSX128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTPD2PSX128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTPD2PSXMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTPD2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTPD2PSXMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTPD2PSXMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTPD2PSY128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTPD2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTPD2PSY128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTPD2PSY128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTPD2PSYMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTPD2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTPD2PSYMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTPD2PSYMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTPS2PD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTPS2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTPS2PD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTPS2PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTPS2PD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTPS2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTPS2PD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTPS2PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTPS2PDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTPS2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTPS2PDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTPS2PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTPS2PDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTPS2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTPS2PDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTPS2PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PS256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PSMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PSX128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PSX128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PSX128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PSXMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PSXMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PSXMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PSY128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PSY128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PSY128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTQQ2PSYMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTQQ2PSYMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTQQ2PSYMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2DQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2DQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2DQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2DQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2DQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2DQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2DQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2DQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2DQX128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2DQX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2DQX128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2DQX128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2DQXMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2DQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2DQXMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2DQXMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2DQY128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2DQY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2DQY128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2DQY128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2DQYMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2DQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2DQYMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2DQYMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2QQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2QQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2QQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2QQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2QQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2QQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2UDQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2UDQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQX128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2UDQX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQX128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQX128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQXMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2UDQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQXMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQXMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQY128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2UDQY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQY128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQY128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQYMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2UDQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQYMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQYMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2UQQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UQQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UQQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2UQQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UQQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UQQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2UQQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UQQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UQQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2UQQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UQQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UQQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2UQQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UQQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UQQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2UQQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UQQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UQQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2DQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2DQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2DQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2DQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2DQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2DQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2DQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2DQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2DQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2DQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2DQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2DQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2DQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2DQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2DQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2DQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2DQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2DQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2DQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2DQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2QQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2QQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2QQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2QQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2QQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2QQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2QQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2QQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2QQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2QQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2QQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2QQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2QQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2QQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2QQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2QQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UQQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2UQQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UQQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UQQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2UQQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UQQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UQQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2UQQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UQQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UQQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2UQQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UQQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUDQ2PD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUDQ2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUDQ2PD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUDQ2PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUDQ2PD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUDQ2PD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUDQ2PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUDQ2PDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUDQ2PDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUDQ2PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUDQ2PDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUDQ2PDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUDQ2PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUDQ2PS128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUDQ2PS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUDQ2PS128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUDQ2PS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUDQ2PS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUDQ2PS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUDQ2PS256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUDQ2PS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUDQ2PS512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUDQ2PS512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUDQ2PS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUDQ2PSMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUDQ2PSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUDQ2PSMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUDQ2PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUDQ2PSMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUDQ2PSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PS256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PSMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PSX128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PSX128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PSX128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PSXMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PSXMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PSXMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PSY128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTUQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PSY128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PSY128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTUQQ2PSYMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTUQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTUQQ2PSYMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTUQQ2PSYMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPS128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPS256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPS512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPS512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPSMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPSMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPSMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPSMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VDIVPSMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VDIVPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VDIVPSMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VDIVPSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VEXPANDPDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VEXPANDPDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VEXPANDPDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VEXPANDPDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VEXPANDPDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VEXPANDPDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VEXPANDPDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VEXPANDPDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VEXPANDPSMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VEXPANDPSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VEXPANDPSMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VEXPANDPSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VEXPANDPSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VEXPANDPSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VEXPANDPSMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VEXPANDPSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PD128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PD128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PD256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PD256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PD512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PD512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PDMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PDMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PDMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PDMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PDMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PDMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PS128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PS128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PS256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PS256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PS512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PS512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PSMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PSMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PSMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PSMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADD213PSMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADD213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADD213PSMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADD213PSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PD128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PD128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PD256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PD256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PD512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PD512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PDMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PDMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PDMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PDMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PDMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PDMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PS128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PS128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PS256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PS256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PS512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PS512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PSMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PSMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PSMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PSMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMADDSUB213PSMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMADDSUB213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMADDSUB213PSMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMADDSUB213PSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PD128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PD128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PD256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PD256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PD512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PD512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PDMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PDMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PDMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PDMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PDMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PDMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PS128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PS128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PS256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PS256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PS512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PS512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PSMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PSMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PSMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PSMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VFMSUBADD213PSMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VFMSUBADD213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VFMSUBADD213PSMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VFMSUBADD213PSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEINVQB128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEINVQB128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEINVQB128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEINVQB256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEINVQB256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEINVQB256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQB512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEINVQB512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEINVQB512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEINVQB512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEINVQBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEINVQBMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEINVQBMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEINVQBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEINVQBMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEINVQBMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEINVQBMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEINVQBMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEINVQBMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEINVQBMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEQB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEQB128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEQB128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEQB128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEQB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEQB256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEQB256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEQB256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEQB512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEQB512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEQB512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEQB512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEQBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEQBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEQBMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEQBMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEQBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEQBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEQBMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEQBMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8AFFINEQBMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8AFFINEQBMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8AFFINEQBMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8AFFINEQBMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8MULB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8MULB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8MULB128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8MULB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8MULB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8MULB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8MULB256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8MULB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8MULBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8MULBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8MULBMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8MULBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VGF2P8MULBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VGF2P8MULBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VGF2P8MULBMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VGF2P8MULBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VHADDPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VHADDPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VHADDPD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VHADDPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VHADDPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VHADDPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VHADDPD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VHADDPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VHADDPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VHADDPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VHADDPS128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VHADDPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VHADDPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VHADDPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VHADDPS256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VHADDPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VHSUBPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VHSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VHSUBPD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VHSUBPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VHSUBPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VHSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VHSUBPD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VHSUBPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VHSUBPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VHSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VHSUBPS128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VHSUBPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VHSUBPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VHSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VHSUBPS256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VHSUBPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VINSERTF128256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VINSERTF128256 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VINSERTF128256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VINSERTF128256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VINSERTF64X4512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VINSERTF64X4512 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VINSERTF64X4512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VINSERTF64X4512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VINSERTI128256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VINSERTI128256 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VINSERTI128256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VINSERTI128256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VINSERTI64X4512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VINSERTI64X4512 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VINSERTI64X4512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VINSERTI64X4512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPS128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPS256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPS512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPS512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPSMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPSMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPSMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPSMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMAXPSMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMAXPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMAXPSMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMAXPSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPS128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPS256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPS512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPS512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPSMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPSMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPSMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPSMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMINPSMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMINPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMINPSMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMINPSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVD(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (VMOVD x:(MOVLload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (VMOVDload [off] {sym} ptr mem) + for { + x := v_0 + if x.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64VMOVDload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU16Masked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU16Masked128 (VPABSW128 x) mask) + // result: (VPABSWMasked128 x mask) + for { + if v_0.Op != OpAMD64VPABSW128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSWMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPADDW128 x y) mask) + // result: (VPADDWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPADDW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPADDSW128 x y) mask) + // result: (VPADDSWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPADDSW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDSWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPADDUSW128 x y) mask) + // result: (VPADDUSWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPADDUSW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDUSWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPAVGW128 x y) mask) + // result: (VPAVGWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPAVGW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPAVGWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPERMI2W128 x y z) mask) + // result: (VPERMI2WMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2W128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2WMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMADDWD128 x y) mask) + // result: (VPMADDWDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMADDWD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMADDWDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMADDUBSW128 x y) mask) + // result: (VPMADDUBSWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMADDUBSW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMADDUBSWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMOVSXWQ128 x) mask) + // result: (VPMOVSXWQMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXWQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXWQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMOVZXWQ128 x) mask) + // result: (VPMOVZXWQMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXWQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXWQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMOVSXWD128 x) mask) + // result: (VPMOVSXWDMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXWD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXWDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMOVZXWD128 x) mask) + // result: (VPMOVZXWDMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXWD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXWDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMAXSW128 x y) mask) + // result: (VPMAXSWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMAXUW128 x y) mask) + // result: (VPMAXUWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMINSW128 x y) mask) + // result: (VPMINSWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMINSW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMINUW128 x y) mask) + // result: (VPMINUWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMINUW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMULHW128 x y) mask) + // result: (VPMULHWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMULHW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULHWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMULHUW128 x y) mask) + // result: (VPMULHUWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMULHUW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULHUWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMULLW128 x y) mask) + // result: (VPMULLWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMULLW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULLWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPOPCNTW128 x) mask) + // result: (VPOPCNTWMasked128 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTW128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTWMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPERMW128 x y) mask) + // result: (VPERMWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPERMW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMOVSWB128_128 x) mask) + // result: (VPMOVSWBMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSWB128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSWBMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMOVUSWB128_128 x) mask) + // result: (VPMOVUSWBMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSWB128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSWBMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSHLDW128 [a] x y) mask) + // result: (VPSHLDWMasked128 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHLDW128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHLDWMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSLLW128 x y) mask) + // result: (VPSLLWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSLLW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSHRDW128 [a] x y) mask) + // result: (VPSHRDWMasked128 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHRDW128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHRDWMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSRAW128 x y) mask) + // result: (VPSRAWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRAW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSRLW128 x y) mask) + // result: (VPSRLWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRLW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSHLDVW128 x y z) mask) + // result: (VPSHLDVWMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPSHLDVW128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHLDVWMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSLLVW128 x y) mask) + // result: (VPSLLVWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSLLVW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLVWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSHRDVW128 x y z) mask) + // result: (VPSHRDVWMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPSHRDVW128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHRDVWMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSRAVW128 x y) mask) + // result: (VPSRAVWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRAVW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAVWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSRLVW128 x y) mask) + // result: (VPSRLVWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRLVW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLVWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSUBW128 x y) mask) + // result: (VPSUBWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSUBW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSUBSW128 x y) mask) + // result: (VPSUBSWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSUBSW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBSWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSUBUSW128 x y) mask) + // result: (VPSUBUSWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSUBUSW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBUSWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPMOVWB128_128 x) mask) + // result: (VPMOVWBMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVWB128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVWBMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSHUFHW128 [a] x) mask) + // result: (VPSHUFHWMasked128 [a] x mask) + for { + if v_0.Op != OpAMD64VPSHUFHW128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFHWMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSHUFLW128 [a] x) mask) + // result: (VPSHUFLWMasked128 [a] x mask) + for { + if v_0.Op != OpAMD64VPSHUFLW128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFLWMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSLLW128const [a] x) mask) + // result: (VPSLLWMasked128const [a] x mask) + for { + if v_0.Op != OpAMD64VPSLLW128const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLWMasked128const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSRAW128const [a] x) mask) + // result: (VPSRAWMasked128const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRAW128const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAWMasked128const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked128 (VPSRLW128const [a] x) mask) + // result: (VPSRLWMasked128const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRLW128const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLWMasked128const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU16Masked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU16Masked256 (VPABSW256 x) mask) + // result: (VPABSWMasked256 x mask) + for { + if v_0.Op != OpAMD64VPABSW256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSWMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPADDW256 x y) mask) + // result: (VPADDWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPADDW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPADDSW256 x y) mask) + // result: (VPADDSWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPADDSW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDSWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPADDUSW256 x y) mask) + // result: (VPADDUSWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPADDUSW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDUSWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPAVGW256 x y) mask) + // result: (VPAVGWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPAVGW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPAVGWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPERMI2W256 x y z) mask) + // result: (VPERMI2WMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2W256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2WMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMADDWD256 x y) mask) + // result: (VPMADDWDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMADDWD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMADDWDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMADDUBSW256 x y) mask) + // result: (VPMADDUBSWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMADDUBSW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMADDUBSWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMOVSXWQ256 x) mask) + // result: (VPMOVSXWQMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXWQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXWQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMOVZXWQ256 x) mask) + // result: (VPMOVZXWQMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXWQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXWQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMOVSXWD256 x) mask) + // result: (VPMOVSXWDMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXWD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXWDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMOVZXWD256 x) mask) + // result: (VPMOVZXWDMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXWD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXWDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMAXSW256 x y) mask) + // result: (VPMAXSWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMAXUW256 x y) mask) + // result: (VPMAXUWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMINSW256 x y) mask) + // result: (VPMINSWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMINSW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMINUW256 x y) mask) + // result: (VPMINUWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMINUW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMULHW256 x y) mask) + // result: (VPMULHWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMULHW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULHWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMULHUW256 x y) mask) + // result: (VPMULHUWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMULHUW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULHUWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMULLW256 x y) mask) + // result: (VPMULLWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMULLW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULLWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPOPCNTW256 x) mask) + // result: (VPOPCNTWMasked256 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTW256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTWMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPERMW256 x y) mask) + // result: (VPERMWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPERMW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMOVSWB128_256 x) mask) + // result: (VPMOVSWBMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSWB128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSWBMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMOVSWB256 x) mask) + // result: (VPMOVSWBMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSWB256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSWBMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMOVUSWB128_256 x) mask) + // result: (VPMOVUSWBMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSWB128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSWBMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMOVUSWB256 x) mask) + // result: (VPMOVUSWBMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSWB256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSWBMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSHLDW256 [a] x y) mask) + // result: (VPSHLDWMasked256 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHLDW256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHLDWMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSLLW256 x y) mask) + // result: (VPSLLWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSLLW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSHRDW256 [a] x y) mask) + // result: (VPSHRDWMasked256 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHRDW256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHRDWMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSRAW256 x y) mask) + // result: (VPSRAWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRAW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSRLW256 x y) mask) + // result: (VPSRLWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRLW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSHLDVW256 x y z) mask) + // result: (VPSHLDVWMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPSHLDVW256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHLDVWMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSLLVW256 x y) mask) + // result: (VPSLLVWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSLLVW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLVWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSHRDVW256 x y z) mask) + // result: (VPSHRDVWMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPSHRDVW256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHRDVWMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSRAVW256 x y) mask) + // result: (VPSRAVWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRAVW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAVWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSRLVW256 x y) mask) + // result: (VPSRLVWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRLVW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLVWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSUBW256 x y) mask) + // result: (VPSUBWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSUBW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSUBSW256 x y) mask) + // result: (VPSUBSWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSUBSW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBSWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSUBUSW256 x y) mask) + // result: (VPSUBUSWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSUBUSW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBUSWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMOVWB128_256 x) mask) + // result: (VPMOVWBMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVWB128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVWBMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPMOVWB256 x) mask) + // result: (VPMOVWBMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVWB256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVWBMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSHUFHW256 [a] x) mask) + // result: (VPSHUFHWMasked256 [a] x mask) + for { + if v_0.Op != OpAMD64VPSHUFHW256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFHWMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSHUFLW256 [a] x) mask) + // result: (VPSHUFLWMasked256 [a] x mask) + for { + if v_0.Op != OpAMD64VPSHUFLW256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFLWMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSLLW256const [a] x) mask) + // result: (VPSLLWMasked256const [a] x mask) + for { + if v_0.Op != OpAMD64VPSLLW256const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLWMasked256const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSRAW256const [a] x) mask) + // result: (VPSRAWMasked256const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRAW256const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAWMasked256const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked256 (VPSRLW256const [a] x) mask) + // result: (VPSRLWMasked256const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRLW256const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLWMasked256const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU16Masked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU16Masked512 (VPABSW512 x) mask) + // result: (VPABSWMasked512 x mask) + for { + if v_0.Op != OpAMD64VPABSW512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSWMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPADDW512 x y) mask) + // result: (VPADDWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPADDW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPADDSW512 x y) mask) + // result: (VPADDSWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPADDSW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDSWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPADDUSW512 x y) mask) + // result: (VPADDUSWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPADDUSW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDUSWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPAVGW512 x y) mask) + // result: (VPAVGWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPAVGW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPAVGWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPERMI2W512 x y z) mask) + // result: (VPERMI2WMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2W512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2WMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMADDWD512 x y) mask) + // result: (VPMADDWDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMADDWD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMADDWDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMADDUBSW512 x y) mask) + // result: (VPMADDUBSWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMADDUBSW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMADDUBSWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMOVSXWD512 x) mask) + // result: (VPMOVSXWDMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXWD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXWDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMOVSXWQ512 x) mask) + // result: (VPMOVSXWQMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXWQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXWQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMOVZXWD512 x) mask) + // result: (VPMOVZXWDMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXWD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXWDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMOVZXWQ512 x) mask) + // result: (VPMOVZXWQMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXWQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXWQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMAXSW512 x y) mask) + // result: (VPMAXSWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMAXUW512 x y) mask) + // result: (VPMAXUWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMINSW512 x y) mask) + // result: (VPMINSWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMINSW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMINUW512 x y) mask) + // result: (VPMINUWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMINUW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMULHW512 x y) mask) + // result: (VPMULHWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMULHW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULHWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMULHUW512 x y) mask) + // result: (VPMULHUWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMULHUW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULHUWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPMULLW512 x y) mask) + // result: (VPMULLWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMULLW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULLWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPOPCNTW512 x) mask) + // result: (VPOPCNTWMasked512 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTW512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTWMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPERMW512 x y) mask) + // result: (VPERMWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPERMW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSHLDW512 [a] x y) mask) + // result: (VPSHLDWMasked512 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHLDW512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHLDWMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSLLW512 x y) mask) + // result: (VPSLLWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSLLW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSHRDW512 [a] x y) mask) + // result: (VPSHRDWMasked512 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHRDW512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHRDWMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSRAW512 x y) mask) + // result: (VPSRAWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRAW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSRLW512 x y) mask) + // result: (VPSRLWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRLW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSHLDVW512 x y z) mask) + // result: (VPSHLDVWMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPSHLDVW512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHLDVWMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSLLVW512 x y) mask) + // result: (VPSLLVWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSLLVW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLVWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSHRDVW512 x y z) mask) + // result: (VPSHRDVWMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPSHRDVW512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHRDVWMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSRAVW512 x y) mask) + // result: (VPSRAVWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRAVW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAVWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSRLVW512 x y) mask) + // result: (VPSRLVWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRLVW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLVWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSUBW512 x y) mask) + // result: (VPSUBWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSUBW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSUBSW512 x y) mask) + // result: (VPSUBSWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSUBSW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBSWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSUBUSW512 x y) mask) + // result: (VPSUBUSWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSUBUSW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBUSWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSHUFHW512 [a] x) mask) + // result: (VPSHUFHWMasked512 [a] x mask) + for { + if v_0.Op != OpAMD64VPSHUFHW512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFHWMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSHUFLW512 [a] x) mask) + // result: (VPSHUFLWMasked512 [a] x mask) + for { + if v_0.Op != OpAMD64VPSHUFLW512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFLWMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSLLW512const [a] x) mask) + // result: (VPSLLWMasked512const [a] x mask) + for { + if v_0.Op != OpAMD64VPSLLW512const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLWMasked512const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSRAW512const [a] x) mask) + // result: (VPSRAWMasked512const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRAW512const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAWMasked512const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU16Masked512 (VPSRLW512const [a] x) mask) + // result: (VPSRLWMasked512const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRLW512const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLWMasked512const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU32Masked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU32Masked128 (VPABSD128 x) mask) + // result: (VPABSDMasked128 x mask) + for { + if v_0.Op != OpAMD64VPABSD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VADDPS128 x y) mask) + // result: (VADDPSMasked128 x y mask) + for { + if v_0.Op != OpAMD64VADDPS128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VADDPSMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPADDD128 x y) mask) + // result: (VPADDDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPADDD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VRNDSCALEPS128 [a] x) mask) + // result: (VRNDSCALEPSMasked128 [a] x mask) + for { + if v_0.Op != OpAMD64VRNDSCALEPS128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VREDUCEPS128 [a] x) mask) + // result: (VREDUCEPSMasked128 [a] x mask) + for { + if v_0.Op != OpAMD64VREDUCEPS128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPERMI2PS128 x y z) mask) + // result: (VPERMI2PSMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2PS128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2PSMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPERMI2D128 x y z) mask) + // result: (VPERMI2DMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2D128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2DMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked128 (VCVTDQ2PS128 x) mask) + // result: (VCVTDQ2PSMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTDQ2PS128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTDQ2PSMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VCVTUDQ2PS128 x) mask) + // result: (VCVTUDQ2PSMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTUDQ2PS128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUDQ2PSMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VCVTTPS2DQ128 x) mask) + // result: (VCVTTPS2DQMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2DQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2DQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VCVTTPS2UDQ128 x) mask) + // result: (VCVTTPS2UDQMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2UDQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2UDQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VDIVPS128 x y) mask) + // result: (VDIVPSMasked128 x y mask) + for { + if v_0.Op != OpAMD64VDIVPS128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VDIVPSMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMOVSXDQ128 x) mask) + // result: (VPMOVSXDQMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXDQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXDQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMOVZXDQ128 x) mask) + // result: (VPMOVZXDQMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXDQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXDQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPLZCNTD128 x) mask) + // result: (VPLZCNTDMasked128 x mask) + for { + if v_0.Op != OpAMD64VPLZCNTD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPLZCNTDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VMAXPS128 x y) mask) + // result: (VMAXPSMasked128 x y mask) + for { + if v_0.Op != OpAMD64VMAXPS128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMAXPSMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMAXSD128 x y) mask) + // result: (VPMAXSDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMAXUD128 x y) mask) + // result: (VPMAXUDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VMINPS128 x y) mask) + // result: (VMINPSMasked128 x y mask) + for { + if v_0.Op != OpAMD64VMINPS128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMINPSMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMINSD128 x y) mask) + // result: (VPMINSDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMINSD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMINUD128 x y) mask) + // result: (VPMINUDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMINUD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VFMADDSUB213PS128 x y z) mask) + // result: (VFMADDSUB213PSMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VFMADDSUB213PS128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADDSUB213PSMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked128 (VFMADD213PS128 x y z) mask) + // result: (VFMADD213PSMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VFMADD213PS128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADD213PSMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked128 (VFMSUBADD213PS128 x y z) mask) + // result: (VFMSUBADD213PSMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VFMSUBADD213PS128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMSUBADD213PSMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked128 (VMULPS128 x y) mask) + // result: (VMULPSMasked128 x y mask) + for { + if v_0.Op != OpAMD64VMULPS128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMULPSMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMULLD128 x y) mask) + // result: (VPMULLDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMULLD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULLDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPOPCNTD128 x) mask) + // result: (VPOPCNTDMasked128 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPROLVD128 x y) mask) + // result: (VPROLVDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPROLVD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPROLVDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPRORVD128 x y) mask) + // result: (VPRORVDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPRORVD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPRORVDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMOVSDB128_128 x) mask) + // result: (VPMOVSDBMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSDB128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSDBMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPACKSSDW128 x y) mask) + // result: (VPACKSSDWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPACKSSDW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPACKSSDWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMOVSDW128_128 x) mask) + // result: (VPMOVSDWMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSDW128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSDWMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMOVUSDB128_128 x) mask) + // result: (VPMOVUSDBMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSDB128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSDBMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPACKUSDW128 x y) mask) + // result: (VPACKUSDWMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPACKUSDW128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPACKUSDWMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMOVUSDW128_128 x) mask) + // result: (VPMOVUSDWMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSDW128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSDWMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VSCALEFPS128 x y) mask) + // result: (VSCALEFPSMasked128 x y mask) + for { + if v_0.Op != OpAMD64VSCALEFPS128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSCALEFPSMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSHLDD128 [a] x y) mask) + // result: (VPSHLDDMasked128 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHLDD128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHLDDMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSLLD128 x y) mask) + // result: (VPSLLDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSLLD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSHRDD128 [a] x y) mask) + // result: (VPSHRDDMasked128 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHRDD128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHRDDMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSRAD128 x y) mask) + // result: (VPSRADMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRAD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRADMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSRLD128 x y) mask) + // result: (VPSRLDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRLD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSHLDVD128 x y z) mask) + // result: (VPSHLDVDMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPSHLDVD128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHLDVDMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSLLVD128 x y) mask) + // result: (VPSLLVDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSLLVD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLVDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSHRDVD128 x y z) mask) + // result: (VPSHRDVDMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPSHRDVD128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHRDVDMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSRAVD128 x y) mask) + // result: (VPSRAVDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRAVD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAVDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSRLVD128 x y) mask) + // result: (VPSRLVDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRLVD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLVDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VSQRTPS128 x) mask) + // result: (VSQRTPSMasked128 x mask) + for { + if v_0.Op != OpAMD64VSQRTPS128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSQRTPSMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VSUBPS128 x y) mask) + // result: (VSUBPSMasked128 x y mask) + for { + if v_0.Op != OpAMD64VSUBPS128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSUBPSMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSUBD128 x y) mask) + // result: (VPSUBDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSUBD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMOVDB128_128 x) mask) + // result: (VPMOVDBMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVDB128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVDBMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPMOVDW128_128 x) mask) + // result: (VPMOVDWMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVDW128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVDWMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSHUFD128 [a] x) mask) + // result: (VPSHUFDMasked128 [a] x mask) + for { + if v_0.Op != OpAMD64VPSHUFD128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFDMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSLLD128const [a] x) mask) + // result: (VPSLLDMasked128const [a] x mask) + for { + if v_0.Op != OpAMD64VPSLLD128const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLDMasked128const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSRAD128const [a] x) mask) + // result: (VPSRADMasked128const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRAD128const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRADMasked128const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked128 (VPSRLD128const [a] x) mask) + // result: (VPSRLDMasked128const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRLD128const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLDMasked128const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU32Masked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU32Masked256 (VPABSD256 x) mask) + // result: (VPABSDMasked256 x mask) + for { + if v_0.Op != OpAMD64VPABSD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VADDPS256 x y) mask) + // result: (VADDPSMasked256 x y mask) + for { + if v_0.Op != OpAMD64VADDPS256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VADDPSMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPADDD256 x y) mask) + // result: (VPADDDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPADDD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VRNDSCALEPS256 [a] x) mask) + // result: (VRNDSCALEPSMasked256 [a] x mask) + for { + if v_0.Op != OpAMD64VRNDSCALEPS256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VREDUCEPS256 [a] x) mask) + // result: (VREDUCEPSMasked256 [a] x mask) + for { + if v_0.Op != OpAMD64VREDUCEPS256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPERMI2PS256 x y z) mask) + // result: (VPERMI2PSMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2PS256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2PSMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPERMI2D256 x y z) mask) + // result: (VPERMI2DMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2D256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2DMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTDQ2PS256 x) mask) + // result: (VCVTDQ2PSMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTDQ2PS256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTDQ2PSMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTUDQ2PS256 x) mask) + // result: (VCVTUDQ2PSMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTUDQ2PS256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUDQ2PSMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTPS2PD256 x) mask) + // result: (VCVTPS2PDMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTPS2PD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTPS2PDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTDQ2PD256 x) mask) + // result: (VCVTDQ2PDMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTDQ2PD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTDQ2PDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTUDQ2PD256 x) mask) + // result: (VCVTUDQ2PDMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTUDQ2PD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUDQ2PDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTTPS2DQ256 x) mask) + // result: (VCVTTPS2DQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2DQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2DQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTTPS2QQ256 x) mask) + // result: (VCVTTPS2QQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2QQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2QQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTTPS2UDQ256 x) mask) + // result: (VCVTTPS2UDQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2UDQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2UDQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTTPS2UQQ256 x) mask) + // result: (VCVTTPS2UQQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2UQQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2UQQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VDIVPS256 x y) mask) + // result: (VDIVPSMasked256 x y mask) + for { + if v_0.Op != OpAMD64VDIVPS256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VDIVPSMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVSXDQ256 x) mask) + // result: (VPMOVSXDQMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXDQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXDQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVZXDQ256 x) mask) + // result: (VPMOVZXDQMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXDQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXDQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPLZCNTD256 x) mask) + // result: (VPLZCNTDMasked256 x mask) + for { + if v_0.Op != OpAMD64VPLZCNTD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPLZCNTDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VMAXPS256 x y) mask) + // result: (VMAXPSMasked256 x y mask) + for { + if v_0.Op != OpAMD64VMAXPS256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMAXPSMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMAXSD256 x y) mask) + // result: (VPMAXSDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMAXUD256 x y) mask) + // result: (VPMAXUDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VMINPS256 x y) mask) + // result: (VMINPSMasked256 x y mask) + for { + if v_0.Op != OpAMD64VMINPS256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMINPSMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMINSD256 x y) mask) + // result: (VPMINSDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMINSD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMINUD256 x y) mask) + // result: (VPMINUDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMINUD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VFMADDSUB213PS256 x y z) mask) + // result: (VFMADDSUB213PSMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VFMADDSUB213PS256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADDSUB213PSMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked256 (VFMADD213PS256 x y z) mask) + // result: (VFMADD213PSMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VFMADD213PS256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADD213PSMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked256 (VFMSUBADD213PS256 x y z) mask) + // result: (VFMSUBADD213PSMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VFMSUBADD213PS256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMSUBADD213PSMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked256 (VMULPS256 x y) mask) + // result: (VMULPSMasked256 x y mask) + for { + if v_0.Op != OpAMD64VMULPS256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMULPSMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMULLD256 x y) mask) + // result: (VPMULLDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMULLD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULLDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPOPCNTD256 x) mask) + // result: (VPOPCNTDMasked256 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPERMPS256 x y) mask) + // result: (VPERMPSMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPERMPS256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMPSMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPERMD256 x y) mask) + // result: (VPERMDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPERMD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPROLVD256 x y) mask) + // result: (VPROLVDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPROLVD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPROLVDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPRORVD256 x y) mask) + // result: (VPRORVDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPRORVD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPRORVDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVSDB128_256 x) mask) + // result: (VPMOVSDBMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSDB128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSDBMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPACKSSDW256 x y) mask) + // result: (VPACKSSDWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPACKSSDW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPACKSSDWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVSDW128_256 x) mask) + // result: (VPMOVSDWMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSDW128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSDWMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVSDW256 x) mask) + // result: (VPMOVSDWMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSDW256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSDWMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVUSDB128_256 x) mask) + // result: (VPMOVUSDBMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSDB128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSDBMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPACKUSDW256 x y) mask) + // result: (VPACKUSDWMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPACKUSDW256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPACKUSDWMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVUSDW128_256 x) mask) + // result: (VPMOVUSDWMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSDW128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSDWMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVUSDW256 x) mask) + // result: (VPMOVUSDWMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSDW256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSDWMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VSCALEFPS256 x y) mask) + // result: (VSCALEFPSMasked256 x y mask) + for { + if v_0.Op != OpAMD64VSCALEFPS256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSCALEFPSMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSHLDD256 [a] x y) mask) + // result: (VPSHLDDMasked256 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHLDD256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHLDDMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSLLD256 x y) mask) + // result: (VPSLLDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSLLD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSHRDD256 [a] x y) mask) + // result: (VPSHRDDMasked256 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHRDD256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHRDDMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSRAD256 x y) mask) + // result: (VPSRADMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRAD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRADMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSRLD256 x y) mask) + // result: (VPSRLDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRLD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSHLDVD256 x y z) mask) + // result: (VPSHLDVDMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPSHLDVD256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHLDVDMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSLLVD256 x y) mask) + // result: (VPSLLVDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSLLVD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLVDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSHRDVD256 x y z) mask) + // result: (VPSHRDVDMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPSHRDVD256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHRDVDMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSRAVD256 x y) mask) + // result: (VPSRAVDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRAVD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAVDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSRLVD256 x y) mask) + // result: (VPSRLVDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRLVD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLVDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VSQRTPS256 x) mask) + // result: (VSQRTPSMasked256 x mask) + for { + if v_0.Op != OpAMD64VSQRTPS256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSQRTPSMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VSUBPS256 x y) mask) + // result: (VSUBPSMasked256 x y mask) + for { + if v_0.Op != OpAMD64VSUBPS256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSUBPSMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSUBD256 x y) mask) + // result: (VPSUBDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSUBD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVDB128_256 x) mask) + // result: (VPMOVDBMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVDB128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVDBMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVDW128_256 x) mask) + // result: (VPMOVDWMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVDW128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVDWMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPMOVDW256 x) mask) + // result: (VPMOVDWMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVDW256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVDWMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSHUFD256 [a] x) mask) + // result: (VPSHUFDMasked256 [a] x mask) + for { + if v_0.Op != OpAMD64VPSHUFD256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFDMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSLLD256const [a] x) mask) + // result: (VPSLLDMasked256const [a] x mask) + for { + if v_0.Op != OpAMD64VPSLLD256const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLDMasked256const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSRAD256const [a] x) mask) + // result: (VPSRADMasked256const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRAD256const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRADMasked256const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VPSRLD256const [a] x) mask) + // result: (VPSRLDMasked256const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRLD256const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLDMasked256const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU32Masked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU32Masked512 (VPABSD512 x) mask) + // result: (VPABSDMasked512 x mask) + for { + if v_0.Op != OpAMD64VPABSD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VADDPS512 x y) mask) + // result: (VADDPSMasked512 x y mask) + for { + if v_0.Op != OpAMD64VADDPS512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VADDPSMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPADDD512 x y) mask) + // result: (VPADDDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPADDD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPANDD512 x y) mask) + // result: (VPANDDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPANDD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPANDDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPANDND512 x y) mask) + // result: (VPANDNDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPANDND512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPANDNDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VRNDSCALEPS512 [a] x) mask) + // result: (VRNDSCALEPSMasked512 [a] x mask) + for { + if v_0.Op != OpAMD64VRNDSCALEPS512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VREDUCEPS512 [a] x) mask) + // result: (VREDUCEPSMasked512 [a] x mask) + for { + if v_0.Op != OpAMD64VREDUCEPS512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPERMI2PS512 x y z) mask) + // result: (VPERMI2PSMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2PS512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2PSMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPERMI2D512 x y z) mask) + // result: (VPERMI2DMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2D512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2DMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTDQ2PS512 x) mask) + // result: (VCVTDQ2PSMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTDQ2PS512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTDQ2PSMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTUDQ2PS512 x) mask) + // result: (VCVTUDQ2PSMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTUDQ2PS512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUDQ2PSMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTPS2PD512 x) mask) + // result: (VCVTPS2PDMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTPS2PD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTPS2PDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTDQ2PD512 x) mask) + // result: (VCVTDQ2PDMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTDQ2PD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTDQ2PDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTUDQ2PD512 x) mask) + // result: (VCVTUDQ2PDMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTUDQ2PD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUDQ2PDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTTPS2DQ512 x) mask) + // result: (VCVTTPS2DQMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2DQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2DQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTTPS2QQ512 x) mask) + // result: (VCVTTPS2QQMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2QQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2QQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTTPS2UDQ512 x) mask) + // result: (VCVTTPS2UDQMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2UDQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2UDQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTTPS2UQQ512 x) mask) + // result: (VCVTTPS2UQQMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2UQQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2UQQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VDIVPS512 x y) mask) + // result: (VDIVPSMasked512 x y mask) + for { + if v_0.Op != OpAMD64VDIVPS512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VDIVPSMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPMOVSXDQ512 x) mask) + // result: (VPMOVSXDQMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXDQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXDQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPMOVZXDQ512 x) mask) + // result: (VPMOVZXDQMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXDQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXDQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPLZCNTD512 x) mask) + // result: (VPLZCNTDMasked512 x mask) + for { + if v_0.Op != OpAMD64VPLZCNTD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPLZCNTDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VMAXPS512 x y) mask) + // result: (VMAXPSMasked512 x y mask) + for { + if v_0.Op != OpAMD64VMAXPS512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMAXPSMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPMAXSD512 x y) mask) + // result: (VPMAXSDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPMAXUD512 x y) mask) + // result: (VPMAXUDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VMINPS512 x y) mask) + // result: (VMINPSMasked512 x y mask) + for { + if v_0.Op != OpAMD64VMINPS512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMINPSMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPMINSD512 x y) mask) + // result: (VPMINSDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMINSD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPMINUD512 x y) mask) + // result: (VPMINUDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMINUD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VFMADDSUB213PS512 x y z) mask) + // result: (VFMADDSUB213PSMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VFMADDSUB213PS512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADDSUB213PSMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked512 (VFMADD213PS512 x y z) mask) + // result: (VFMADD213PSMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VFMADD213PS512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADD213PSMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked512 (VFMSUBADD213PS512 x y z) mask) + // result: (VFMSUBADD213PSMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VFMSUBADD213PS512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMSUBADD213PSMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked512 (VMULPS512 x y) mask) + // result: (VMULPSMasked512 x y mask) + for { + if v_0.Op != OpAMD64VMULPS512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMULPSMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPMULLD512 x y) mask) + // result: (VPMULLDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMULLD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULLDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPOPCNTD512 x) mask) + // result: (VPOPCNTDMasked512 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPORD512 x y) mask) + // result: (VPORDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPORD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPORDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPERMPS512 x y) mask) + // result: (VPERMPSMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPERMPS512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMPSMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPERMD512 x y) mask) + // result: (VPERMDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPERMD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VRCP14PS512 x) mask) + // result: (VRCP14PSMasked512 x mask) + for { + if v_0.Op != OpAMD64VRCP14PS512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRCP14PSMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VRSQRT14PS512 x) mask) + // result: (VRSQRT14PSMasked512 x mask) + for { + if v_0.Op != OpAMD64VRSQRT14PS512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRSQRT14PSMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPROLVD512 x y) mask) + // result: (VPROLVDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPROLVD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPROLVDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPRORVD512 x y) mask) + // result: (VPRORVDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPRORVD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPRORVDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPMOVSDB128_512 x) mask) + // result: (VPMOVSDBMasked128_512 x mask) + for { + if v_0.Op != OpAMD64VPMOVSDB128_512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSDBMasked128_512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPACKSSDW512 x y) mask) + // result: (VPACKSSDWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPACKSSDW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPACKSSDWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPMOVUSDB128_512 x) mask) + // result: (VPMOVUSDBMasked128_512 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSDB128_512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSDBMasked128_512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPACKUSDW512 x y) mask) + // result: (VPACKUSDWMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPACKUSDW512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPACKUSDWMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VSCALEFPS512 x y) mask) + // result: (VSCALEFPSMasked512 x y mask) + for { + if v_0.Op != OpAMD64VSCALEFPS512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSCALEFPSMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSHLDD512 [a] x y) mask) + // result: (VPSHLDDMasked512 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHLDD512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHLDDMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSLLD512 x y) mask) + // result: (VPSLLDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSLLD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSHRDD512 [a] x y) mask) + // result: (VPSHRDDMasked512 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHRDD512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHRDDMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSRAD512 x y) mask) + // result: (VPSRADMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRAD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRADMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSRLD512 x y) mask) + // result: (VPSRLDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRLD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSHLDVD512 x y z) mask) + // result: (VPSHLDVDMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPSHLDVD512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHLDVDMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSLLVD512 x y) mask) + // result: (VPSLLVDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSLLVD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLVDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSHRDVD512 x y z) mask) + // result: (VPSHRDVDMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPSHRDVD512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHRDVDMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSRAVD512 x y) mask) + // result: (VPSRAVDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRAVD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAVDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSRLVD512 x y) mask) + // result: (VPSRLVDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRLVD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLVDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VSQRTPS512 x) mask) + // result: (VSQRTPSMasked512 x mask) + for { + if v_0.Op != OpAMD64VSQRTPS512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSQRTPSMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VSUBPS512 x y) mask) + // result: (VSUBPSMasked512 x y mask) + for { + if v_0.Op != OpAMD64VSUBPS512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSUBPSMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSUBD512 x y) mask) + // result: (VPSUBDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSUBD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPMOVDB128_512 x) mask) + // result: (VPMOVDBMasked128_512 x mask) + for { + if v_0.Op != OpAMD64VPMOVDB128_512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVDBMasked128_512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPXORD512 x y) mask) + // result: (VPXORDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPXORD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPXORDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSHUFD512 [a] x) mask) + // result: (VPSHUFDMasked512 [a] x mask) + for { + if v_0.Op != OpAMD64VPSHUFD512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFDMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSLLD512const [a] x) mask) + // result: (VPSLLDMasked512const [a] x mask) + for { + if v_0.Op != OpAMD64VPSLLD512const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLDMasked512const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSRAD512const [a] x) mask) + // result: (VPSRADMasked512const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRAD512const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRADMasked512const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VPSRLD512const [a] x) mask) + // result: (VPSRLDMasked512const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRLD512const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLDMasked512const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU64Masked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU64Masked128 (VPABSQ128 x) mask) + // result: (VPABSQMasked128 x mask) + for { + if v_0.Op != OpAMD64VPABSQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VADDPD128 x y) mask) + // result: (VADDPDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VADDPD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VADDPDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPADDQ128 x y) mask) + // result: (VPADDQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPADDQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VRNDSCALEPD128 [a] x) mask) + // result: (VRNDSCALEPDMasked128 [a] x mask) + for { + if v_0.Op != OpAMD64VRNDSCALEPD128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VREDUCEPD128 [a] x) mask) + // result: (VREDUCEPDMasked128 [a] x mask) + for { + if v_0.Op != OpAMD64VREDUCEPD128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPERMI2PD128 x y z) mask) + // result: (VPERMI2PDMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2PD128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2PDMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPERMI2Q128 x y z) mask) + // result: (VPERMI2QMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2Q128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2QMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTPD2PSX128 x) mask) + // result: (VCVTPD2PSXMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTPD2PSX128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTPD2PSXMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTPD2PSY128 x) mask) + // result: (VCVTPD2PSYMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTPD2PSY128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTPD2PSYMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTQQ2PSX128 x) mask) + // result: (VCVTQQ2PSXMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTQQ2PSX128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTQQ2PSXMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTQQ2PSY128 x) mask) + // result: (VCVTQQ2PSYMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTQQ2PSY128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTQQ2PSYMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTUQQ2PSX128 x) mask) + // result: (VCVTUQQ2PSXMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTUQQ2PSX128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUQQ2PSXMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTUQQ2PSY128 x) mask) + // result: (VCVTUQQ2PSYMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTUQQ2PSY128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUQQ2PSYMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTQQ2PD128 x) mask) + // result: (VCVTQQ2PDMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTQQ2PD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTQQ2PDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTUQQ2PD128 x) mask) + // result: (VCVTUQQ2PDMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTUQQ2PD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUQQ2PDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2DQX128 x) mask) + // result: (VCVTTPD2DQXMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2DQX128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2DQXMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2DQY128 x) mask) + // result: (VCVTTPD2DQYMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2DQY128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2DQYMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2QQ128 x) mask) + // result: (VCVTTPD2QQMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2QQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2QQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2UDQX128 x) mask) + // result: (VCVTTPD2UDQXMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UDQX128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UDQXMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2UDQY128 x) mask) + // result: (VCVTTPD2UDQYMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UDQY128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UDQYMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2UQQ128 x) mask) + // result: (VCVTTPD2UQQMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UQQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UQQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VDIVPD128 x y) mask) + // result: (VDIVPDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VDIVPD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VDIVPDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPLZCNTQ128 x) mask) + // result: (VPLZCNTQMasked128 x mask) + for { + if v_0.Op != OpAMD64VPLZCNTQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPLZCNTQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VMAXPD128 x y) mask) + // result: (VMAXPDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VMAXPD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMAXPDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMAXSQ128 x y) mask) + // result: (VPMAXSQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMAXUQ128 x y) mask) + // result: (VPMAXUQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VMINPD128 x y) mask) + // result: (VMINPDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VMINPD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMINPDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMINSQ128 x y) mask) + // result: (VPMINSQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMINSQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMINUQ128 x y) mask) + // result: (VPMINUQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMINUQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VFMADDSUB213PD128 x y z) mask) + // result: (VFMADDSUB213PDMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VFMADDSUB213PD128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADDSUB213PDMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked128 (VFMADD213PD128 x y z) mask) + // result: (VFMADD213PDMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VFMADD213PD128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADD213PDMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked128 (VFMSUBADD213PD128 x y z) mask) + // result: (VFMSUBADD213PDMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VFMSUBADD213PD128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMSUBADD213PDMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked128 (VMULPD128 x y) mask) + // result: (VMULPDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VMULPD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMULPDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMULLQ128 x y) mask) + // result: (VPMULLQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMULLQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULLQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPOPCNTQ128 x) mask) + // result: (VPOPCNTQMasked128 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VRCP14PD128 x) mask) + // result: (VRCP14PDMasked128 x mask) + for { + if v_0.Op != OpAMD64VRCP14PD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRCP14PDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VRSQRT14PD128 x) mask) + // result: (VRSQRT14PDMasked128 x mask) + for { + if v_0.Op != OpAMD64VRSQRT14PD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRSQRT14PDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPROLVQ128 x y) mask) + // result: (VPROLVQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPROLVQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPROLVQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPRORVQ128 x y) mask) + // result: (VPRORVQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPRORVQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPRORVQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMOVSQB128_128 x) mask) + // result: (VPMOVSQBMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSQB128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSQBMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMOVSQW128_128 x) mask) + // result: (VPMOVSQWMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSQW128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSQWMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMOVSQD128_128 x) mask) + // result: (VPMOVSQDMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSQD128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSQDMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMOVUSQB128_128 x) mask) + // result: (VPMOVUSQBMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSQB128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSQBMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMOVUSQW128_128 x) mask) + // result: (VPMOVUSQWMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSQW128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSQWMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMOVUSQD128_128 x) mask) + // result: (VPMOVUSQDMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSQD128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSQDMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VSCALEFPD128 x y) mask) + // result: (VSCALEFPDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VSCALEFPD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSCALEFPDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSHLDQ128 [a] x y) mask) + // result: (VPSHLDQMasked128 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHLDQ128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHLDQMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSLLQ128 x y) mask) + // result: (VPSLLQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSLLQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSHRDQ128 [a] x y) mask) + // result: (VPSHRDQMasked128 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHRDQ128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHRDQMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSRAQ128 x y) mask) + // result: (VPSRAQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRAQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSRLQ128 x y) mask) + // result: (VPSRLQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRLQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSHLDVQ128 x y z) mask) + // result: (VPSHLDVQMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPSHLDVQ128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHLDVQMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSLLVQ128 x y) mask) + // result: (VPSLLVQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSLLVQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLVQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSHRDVQ128 x y z) mask) + // result: (VPSHRDVQMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPSHRDVQ128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHRDVQMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSRAVQ128 x y) mask) + // result: (VPSRAVQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRAVQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAVQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSRLVQ128 x y) mask) + // result: (VPSRLVQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSRLVQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLVQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VSQRTPD128 x) mask) + // result: (VSQRTPDMasked128 x mask) + for { + if v_0.Op != OpAMD64VSQRTPD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSQRTPDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VSUBPD128 x y) mask) + // result: (VSUBPDMasked128 x y mask) + for { + if v_0.Op != OpAMD64VSUBPD128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSUBPDMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSUBQ128 x y) mask) + // result: (VPSUBQMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSUBQ128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBQMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMOVQB128_128 x) mask) + // result: (VPMOVQBMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVQB128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVQBMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMOVQW128_128 x) mask) + // result: (VPMOVQWMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVQW128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVQWMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPMOVQD128_128 x) mask) + // result: (VPMOVQDMasked128_128 x mask) + for { + if v_0.Op != OpAMD64VPMOVQD128_128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVQDMasked128_128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSLLQ128const [a] x) mask) + // result: (VPSLLQMasked128const [a] x mask) + for { + if v_0.Op != OpAMD64VPSLLQ128const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLQMasked128const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSRAQ128const [a] x) mask) + // result: (VPSRAQMasked128const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRAQ128const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAQMasked128const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VPSRLQ128const [a] x) mask) + // result: (VPSRLQMasked128const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRLQ128const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLQMasked128const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU64Masked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU64Masked256 (VPABSQ256 x) mask) + // result: (VPABSQMasked256 x mask) + for { + if v_0.Op != OpAMD64VPABSQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VADDPD256 x y) mask) + // result: (VADDPDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VADDPD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VADDPDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPADDQ256 x y) mask) + // result: (VPADDQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPADDQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VRNDSCALEPD256 [a] x) mask) + // result: (VRNDSCALEPDMasked256 [a] x mask) + for { + if v_0.Op != OpAMD64VRNDSCALEPD256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VREDUCEPD256 [a] x) mask) + // result: (VREDUCEPDMasked256 [a] x mask) + for { + if v_0.Op != OpAMD64VREDUCEPD256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPERMI2PD256 x y z) mask) + // result: (VPERMI2PDMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2PD256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2PDMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPERMI2Q256 x y z) mask) + // result: (VPERMI2QMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2Q256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2QMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTPD2PS256 x) mask) + // result: (VCVTPD2PSMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTPD2PS256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTPD2PSMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTQQ2PS256 x) mask) + // result: (VCVTQQ2PSMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTQQ2PS256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTQQ2PSMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTUQQ2PS256 x) mask) + // result: (VCVTUQQ2PSMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTUQQ2PS256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUQQ2PSMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTQQ2PD256 x) mask) + // result: (VCVTQQ2PDMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTQQ2PD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTQQ2PDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTUQQ2PD256 x) mask) + // result: (VCVTUQQ2PDMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTUQQ2PD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUQQ2PDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTTPD2DQ256 x) mask) + // result: (VCVTTPD2DQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2DQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2DQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTTPD2QQ256 x) mask) + // result: (VCVTTPD2QQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2QQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2QQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTTPD2UDQ256 x) mask) + // result: (VCVTTPD2UDQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UDQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UDQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTTPD2UQQ256 x) mask) + // result: (VCVTTPD2UQQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UQQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UQQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VDIVPD256 x y) mask) + // result: (VDIVPDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VDIVPD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VDIVPDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPLZCNTQ256 x) mask) + // result: (VPLZCNTQMasked256 x mask) + for { + if v_0.Op != OpAMD64VPLZCNTQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPLZCNTQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VMAXPD256 x y) mask) + // result: (VMAXPDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VMAXPD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMAXPDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMAXSQ256 x y) mask) + // result: (VPMAXSQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMAXUQ256 x y) mask) + // result: (VPMAXUQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VMINPD256 x y) mask) + // result: (VMINPDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VMINPD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMINPDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMINSQ256 x y) mask) + // result: (VPMINSQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMINSQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMINUQ256 x y) mask) + // result: (VPMINUQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMINUQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VFMADDSUB213PD256 x y z) mask) + // result: (VFMADDSUB213PDMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VFMADDSUB213PD256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADDSUB213PDMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked256 (VFMADD213PD256 x y z) mask) + // result: (VFMADD213PDMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VFMADD213PD256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADD213PDMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked256 (VFMSUBADD213PD256 x y z) mask) + // result: (VFMSUBADD213PDMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VFMSUBADD213PD256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMSUBADD213PDMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked256 (VMULPD256 x y) mask) + // result: (VMULPDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VMULPD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMULPDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMULLQ256 x y) mask) + // result: (VPMULLQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMULLQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULLQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPOPCNTQ256 x) mask) + // result: (VPOPCNTQMasked256 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPERMPD256 x y) mask) + // result: (VPERMPDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPERMPD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMPDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPERMQ256 x y) mask) + // result: (VPERMQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPERMQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VRCP14PD256 x) mask) + // result: (VRCP14PDMasked256 x mask) + for { + if v_0.Op != OpAMD64VRCP14PD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRCP14PDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VRSQRT14PD256 x) mask) + // result: (VRSQRT14PDMasked256 x mask) + for { + if v_0.Op != OpAMD64VRSQRT14PD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRSQRT14PDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPROLVQ256 x y) mask) + // result: (VPROLVQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPROLVQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPROLVQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPRORVQ256 x y) mask) + // result: (VPRORVQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPRORVQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPRORVQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVSQB128_256 x) mask) + // result: (VPMOVSQBMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSQB128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSQBMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVSQW128_256 x) mask) + // result: (VPMOVSQWMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSQW128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSQWMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVSQD128_256 x) mask) + // result: (VPMOVSQDMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSQD128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSQDMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVSQD256 x) mask) + // result: (VPMOVSQDMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSQD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSQDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVUSQB128_256 x) mask) + // result: (VPMOVUSQBMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSQB128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSQBMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVUSQW128_256 x) mask) + // result: (VPMOVUSQWMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSQW128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSQWMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVUSQD128_256 x) mask) + // result: (VPMOVUSQDMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSQD128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSQDMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVUSQD256 x) mask) + // result: (VPMOVUSQDMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSQD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSQDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VSCALEFPD256 x y) mask) + // result: (VSCALEFPDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VSCALEFPD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSCALEFPDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSHLDQ256 [a] x y) mask) + // result: (VPSHLDQMasked256 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHLDQ256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHLDQMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSLLQ256 x y) mask) + // result: (VPSLLQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSLLQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSHRDQ256 [a] x y) mask) + // result: (VPSHRDQMasked256 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHRDQ256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHRDQMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSRAQ256 x y) mask) + // result: (VPSRAQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRAQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSRLQ256 x y) mask) + // result: (VPSRLQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRLQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSHLDVQ256 x y z) mask) + // result: (VPSHLDVQMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPSHLDVQ256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHLDVQMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSLLVQ256 x y) mask) + // result: (VPSLLVQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSLLVQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLVQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSHRDVQ256 x y z) mask) + // result: (VPSHRDVQMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPSHRDVQ256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHRDVQMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSRAVQ256 x y) mask) + // result: (VPSRAVQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRAVQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAVQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSRLVQ256 x y) mask) + // result: (VPSRLVQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSRLVQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLVQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VSQRTPD256 x) mask) + // result: (VSQRTPDMasked256 x mask) + for { + if v_0.Op != OpAMD64VSQRTPD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSQRTPDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VSUBPD256 x y) mask) + // result: (VSUBPDMasked256 x y mask) + for { + if v_0.Op != OpAMD64VSUBPD256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSUBPDMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSUBQ256 x y) mask) + // result: (VPSUBQMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSUBQ256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBQMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVQB128_256 x) mask) + // result: (VPMOVQBMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVQB128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVQBMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVQW128_256 x) mask) + // result: (VPMOVQWMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVQW128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVQWMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVQD128_256 x) mask) + // result: (VPMOVQDMasked128_256 x mask) + for { + if v_0.Op != OpAMD64VPMOVQD128_256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVQDMasked128_256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPMOVQD256 x) mask) + // result: (VPMOVQDMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVQD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVQDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSLLQ256const [a] x) mask) + // result: (VPSLLQMasked256const [a] x mask) + for { + if v_0.Op != OpAMD64VPSLLQ256const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLQMasked256const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSRAQ256const [a] x) mask) + // result: (VPSRAQMasked256const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRAQ256const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAQMasked256const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VPSRLQ256const [a] x) mask) + // result: (VPSRLQMasked256const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRLQ256const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLQMasked256const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU64Masked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU64Masked512 (VPABSQ512 x) mask) + // result: (VPABSQMasked512 x mask) + for { + if v_0.Op != OpAMD64VPABSQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VADDPD512 x y) mask) + // result: (VADDPDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VADDPD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VADDPDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPADDQ512 x y) mask) + // result: (VPADDQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPADDQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPANDQ512 x y) mask) + // result: (VPANDQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPANDQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPANDQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPANDNQ512 x y) mask) + // result: (VPANDNQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPANDNQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPANDNQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VRNDSCALEPD512 [a] x) mask) + // result: (VRNDSCALEPDMasked512 [a] x mask) + for { + if v_0.Op != OpAMD64VRNDSCALEPD512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VREDUCEPD512 [a] x) mask) + // result: (VREDUCEPDMasked512 [a] x mask) + for { + if v_0.Op != OpAMD64VREDUCEPD512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPERMI2PD512 x y z) mask) + // result: (VPERMI2PDMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2PD512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2PDMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPERMI2Q512 x y z) mask) + // result: (VPERMI2QMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2Q512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2QMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked512 (VCVTQQ2PD512 x) mask) + // result: (VCVTQQ2PDMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTQQ2PD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTQQ2PDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VCVTUQQ2PD512 x) mask) + // result: (VCVTUQQ2PDMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTUQQ2PD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTUQQ2PDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VCVTTPD2QQ512 x) mask) + // result: (VCVTTPD2QQMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2QQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2QQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VCVTTPD2UQQ512 x) mask) + // result: (VCVTTPD2UQQMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UQQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UQQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VDIVPD512 x y) mask) + // result: (VDIVPDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VDIVPD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VDIVPDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPLZCNTQ512 x) mask) + // result: (VPLZCNTQMasked512 x mask) + for { + if v_0.Op != OpAMD64VPLZCNTQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPLZCNTQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VMAXPD512 x y) mask) + // result: (VMAXPDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VMAXPD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMAXPDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMAXSQ512 x y) mask) + // result: (VPMAXSQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMAXUQ512 x y) mask) + // result: (VPMAXUQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VMINPD512 x y) mask) + // result: (VMINPDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VMINPD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMINPDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMINSQ512 x y) mask) + // result: (VPMINSQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMINSQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMINUQ512 x y) mask) + // result: (VPMINUQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMINUQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VFMADDSUB213PD512 x y z) mask) + // result: (VFMADDSUB213PDMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VFMADDSUB213PD512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADDSUB213PDMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked512 (VFMADD213PD512 x y z) mask) + // result: (VFMADD213PDMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VFMADD213PD512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMADD213PDMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked512 (VFMSUBADD213PD512 x y z) mask) + // result: (VFMSUBADD213PDMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VFMSUBADD213PD512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VFMSUBADD213PDMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked512 (VMULPD512 x y) mask) + // result: (VMULPDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VMULPD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VMULPDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMULLQ512 x y) mask) + // result: (VPMULLQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMULLQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMULLQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPOPCNTQ512 x) mask) + // result: (VPOPCNTQMasked512 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPORQ512 x y) mask) + // result: (VPORQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPORQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPORQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPERMPD512 x y) mask) + // result: (VPERMPDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPERMPD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMPDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPERMQ512 x y) mask) + // result: (VPERMQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPERMQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VRCP14PD512 x) mask) + // result: (VRCP14PDMasked512 x mask) + for { + if v_0.Op != OpAMD64VRCP14PD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRCP14PDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VRSQRT14PD512 x) mask) + // result: (VRSQRT14PDMasked512 x mask) + for { + if v_0.Op != OpAMD64VRSQRT14PD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VRSQRT14PDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPROLVQ512 x y) mask) + // result: (VPROLVQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPROLVQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPROLVQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPRORVQ512 x y) mask) + // result: (VPRORVQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPRORVQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPRORVQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMOVSQB128_512 x) mask) + // result: (VPMOVSQBMasked128_512 x mask) + for { + if v_0.Op != OpAMD64VPMOVSQB128_512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSQBMasked128_512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMOVSQW128_512 x) mask) + // result: (VPMOVSQWMasked128_512 x mask) + for { + if v_0.Op != OpAMD64VPMOVSQW128_512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSQWMasked128_512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMOVUSQB128_512 x) mask) + // result: (VPMOVUSQBMasked128_512 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSQB128_512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSQBMasked128_512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMOVUSQW128_512 x) mask) + // result: (VPMOVUSQWMasked128_512 x mask) + for { + if v_0.Op != OpAMD64VPMOVUSQW128_512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVUSQWMasked128_512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VSCALEFPD512 x y) mask) + // result: (VSCALEFPDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VSCALEFPD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSCALEFPDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSHLDQ512 [a] x y) mask) + // result: (VPSHLDQMasked512 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHLDQ512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHLDQMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSLLQ512 x y) mask) + // result: (VPSLLQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSLLQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSHRDQ512 [a] x y) mask) + // result: (VPSHRDQMasked512 [a] x y mask) + for { + if v_0.Op != OpAMD64VPSHRDQ512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHRDQMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSRAQ512 x y) mask) + // result: (VPSRAQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRAQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSRLQ512 x y) mask) + // result: (VPSRLQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRLQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSHLDVQ512 x y z) mask) + // result: (VPSHLDVQMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPSHLDVQ512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHLDVQMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSLLVQ512 x y) mask) + // result: (VPSLLVQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSLLVQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLVQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSHRDVQ512 x y z) mask) + // result: (VPSHRDVQMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPSHRDVQ512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPSHRDVQMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSRAVQ512 x y) mask) + // result: (VPSRAVQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRAVQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAVQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSRLVQ512 x y) mask) + // result: (VPSRLVQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSRLVQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLVQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VSQRTPD512 x) mask) + // result: (VSQRTPDMasked512 x mask) + for { + if v_0.Op != OpAMD64VSQRTPD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSQRTPDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VSUBPD512 x y) mask) + // result: (VSUBPDMasked512 x y mask) + for { + if v_0.Op != OpAMD64VSUBPD512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VSUBPDMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSUBQ512 x y) mask) + // result: (VPSUBQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSUBQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMOVQB128_512 x) mask) + // result: (VPMOVQBMasked128_512 x mask) + for { + if v_0.Op != OpAMD64VPMOVQB128_512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVQBMasked128_512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPMOVQW128_512 x) mask) + // result: (VPMOVQWMasked128_512 x mask) + for { + if v_0.Op != OpAMD64VPMOVQW128_512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVQWMasked128_512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPXORQ512 x y) mask) + // result: (VPXORQMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPXORQ512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPXORQMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSLLQ512const [a] x) mask) + // result: (VPSLLQMasked512const [a] x mask) + for { + if v_0.Op != OpAMD64VPSLLQ512const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSLLQMasked512const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSRAQ512const [a] x) mask) + // result: (VPSRAQMasked512const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRAQ512const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRAQMasked512const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VPSRLQ512const [a] x) mask) + // result: (VPSRLQMasked512const [a] x mask) + for { + if v_0.Op != OpAMD64VPSRLQ512const { + break + } + a := auxIntToUint8(v_0.AuxInt) + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSRLQMasked512const) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU8Masked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU8Masked128 (VPABSB128 x) mask) + // result: (VPABSBMasked128 x mask) + for { + if v_0.Op != OpAMD64VPABSB128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSBMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPADDB128 x y) mask) + // result: (VPADDBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPADDB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPADDSB128 x y) mask) + // result: (VPADDSBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPADDSB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDSBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPADDUSB128 x y) mask) + // result: (VPADDUSBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPADDUSB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDUSBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPAVGB128 x y) mask) + // result: (VPAVGBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPAVGB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPAVGBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPERMI2B128 x y z) mask) + // result: (VPERMI2BMasked128 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2B128 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2BMasked128) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPALIGNR128 [a] x y) mask) + // result: (VPALIGNRMasked128 [a] x y mask) + for { + if v_0.Op != OpAMD64VPALIGNR128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPALIGNRMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPMOVSXBQ128 x) mask) + // result: (VPMOVSXBQMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXBQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXBQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPMOVZXBQ128 x) mask) + // result: (VPMOVZXBQMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXBQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXBQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPMOVSXBD128 x) mask) + // result: (VPMOVSXBDMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXBD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXBDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPMOVZXBD128 x) mask) + // result: (VPMOVZXBDMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXBD128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXBDMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPMOVSXBW128 x) mask) + // result: (VPMOVSXBWMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXBW128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXBWMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPMOVZXBW128 x) mask) + // result: (VPMOVZXBWMasked128 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXBW128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXBWMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked128 (VGF2P8AFFINEINVQB128 [a] x y) mask) + // result: (VGF2P8AFFINEINVQBMasked128 [a] x y mask) + for { + if v_0.Op != OpAMD64VGF2P8AFFINEINVQB128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VGF2P8AFFINEINVQBMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VGF2P8AFFINEQB128 [a] x y) mask) + // result: (VGF2P8AFFINEQBMasked128 [a] x y mask) + for { + if v_0.Op != OpAMD64VGF2P8AFFINEQB128 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VGF2P8AFFINEQBMasked128) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VGF2P8MULB128 x y) mask) + // result: (VGF2P8MULBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VGF2P8MULB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VGF2P8MULBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPMAXSB128 x y) mask) + // result: (VPMAXSBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPMAXUB128 x y) mask) + // result: (VPMAXUBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPMINSB128 x y) mask) + // result: (VPMINSBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMINSB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPMINUB128 x y) mask) + // result: (VPMINUBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPMINUB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPOPCNTB128 x) mask) + // result: (VPOPCNTBMasked128 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTB128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTBMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPERMB128 x y) mask) + // result: (VPERMBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPERMB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPSHUFB128 x y) mask) + // result: (VPSHUFBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSHUFB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPSUBB128 x y) mask) + // result: (VPSUBBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSUBB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPSUBSB128 x y) mask) + // result: (VPSUBSBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSUBSB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBSBMasked128) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked128 (VPSUBUSB128 x y) mask) + // result: (VPSUBUSBMasked128 x y mask) + for { + if v_0.Op != OpAMD64VPSUBUSB128 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBUSBMasked128) + v.AddArg3(x, y, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU8Masked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU8Masked256 (VPABSB256 x) mask) + // result: (VPABSBMasked256 x mask) + for { + if v_0.Op != OpAMD64VPABSB256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSBMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPADDB256 x y) mask) + // result: (VPADDBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPADDB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPADDSB256 x y) mask) + // result: (VPADDSBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPADDSB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDSBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPADDUSB256 x y) mask) + // result: (VPADDUSBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPADDUSB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDUSBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPAVGB256 x y) mask) + // result: (VPAVGBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPAVGB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPAVGBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPERMI2B256 x y z) mask) + // result: (VPERMI2BMasked256 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2B256 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2BMasked256) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPALIGNR256 [a] x y) mask) + // result: (VPALIGNRMasked256 [a] x y mask) + for { + if v_0.Op != OpAMD64VPALIGNR256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPALIGNRMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPMOVSXBQ256 x) mask) + // result: (VPMOVSXBQMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXBQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXBQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPMOVZXBQ256 x) mask) + // result: (VPMOVZXBQMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXBQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXBQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPMOVSXBD256 x) mask) + // result: (VPMOVSXBDMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXBD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXBDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPMOVZXBD256 x) mask) + // result: (VPMOVZXBDMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXBD256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXBDMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPMOVSXBW256 x) mask) + // result: (VPMOVSXBWMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXBW256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXBWMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPMOVZXBW256 x) mask) + // result: (VPMOVZXBWMasked256 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXBW256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXBWMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked256 (VGF2P8AFFINEINVQB256 [a] x y) mask) + // result: (VGF2P8AFFINEINVQBMasked256 [a] x y mask) + for { + if v_0.Op != OpAMD64VGF2P8AFFINEINVQB256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VGF2P8AFFINEINVQBMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VGF2P8AFFINEQB256 [a] x y) mask) + // result: (VGF2P8AFFINEQBMasked256 [a] x y mask) + for { + if v_0.Op != OpAMD64VGF2P8AFFINEQB256 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VGF2P8AFFINEQBMasked256) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VGF2P8MULB256 x y) mask) + // result: (VGF2P8MULBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VGF2P8MULB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VGF2P8MULBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPMAXSB256 x y) mask) + // result: (VPMAXSBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPMAXUB256 x y) mask) + // result: (VPMAXUBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPMINSB256 x y) mask) + // result: (VPMINSBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMINSB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPMINUB256 x y) mask) + // result: (VPMINUBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPMINUB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPOPCNTB256 x) mask) + // result: (VPOPCNTBMasked256 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTB256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTBMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPERMB256 x y) mask) + // result: (VPERMBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPERMB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPSHUFB256 x y) mask) + // result: (VPSHUFBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSHUFB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPSUBB256 x y) mask) + // result: (VPSUBBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSUBB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPSUBSB256 x y) mask) + // result: (VPSUBSBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSUBSB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBSBMasked256) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked256 (VPSUBUSB256 x y) mask) + // result: (VPSUBUSBMasked256 x y mask) + for { + if v_0.Op != OpAMD64VPSUBUSB256 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBUSBMasked256) + v.AddArg3(x, y, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQU8Masked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQU8Masked512 (VPABSB512 x) mask) + // result: (VPABSBMasked512 x mask) + for { + if v_0.Op != OpAMD64VPABSB512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPABSBMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPADDB512 x y) mask) + // result: (VPADDBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPADDB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPADDSB512 x y) mask) + // result: (VPADDSBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPADDSB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDSBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPADDUSB512 x y) mask) + // result: (VPADDUSBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPADDUSB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPADDUSBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPAVGB512 x y) mask) + // result: (VPAVGBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPAVGB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPAVGBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPERMI2B512 x y z) mask) + // result: (VPERMI2BMasked512 x y z mask) + for { + if v_0.Op != OpAMD64VPERMI2B512 { + break + } + z := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + mask := v_1 + v.reset(OpAMD64VPERMI2BMasked512) + v.AddArg4(x, y, z, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPALIGNR512 [a] x y) mask) + // result: (VPALIGNRMasked512 [a] x y mask) + for { + if v_0.Op != OpAMD64VPALIGNR512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPALIGNRMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPMOVSXBQ512 x) mask) + // result: (VPMOVSXBQMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXBQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXBQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPMOVZXBQ512 x) mask) + // result: (VPMOVZXBQMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXBQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXBQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPMOVSXBW512 x) mask) + // result: (VPMOVSXBWMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXBW512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXBWMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPMOVSXBD512 x) mask) + // result: (VPMOVSXBDMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVSXBD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVSXBDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPMOVZXBW512 x) mask) + // result: (VPMOVZXBWMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXBW512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXBWMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPMOVZXBD512 x) mask) + // result: (VPMOVZXBDMasked512 x mask) + for { + if v_0.Op != OpAMD64VPMOVZXBD512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMOVZXBDMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked512 (VGF2P8AFFINEINVQB512 [a] x y) mask) + // result: (VGF2P8AFFINEINVQBMasked512 [a] x y mask) + for { + if v_0.Op != OpAMD64VGF2P8AFFINEINVQB512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VGF2P8AFFINEINVQBMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VGF2P8AFFINEQB512 [a] x y) mask) + // result: (VGF2P8AFFINEQBMasked512 [a] x y mask) + for { + if v_0.Op != OpAMD64VGF2P8AFFINEQB512 { + break + } + a := auxIntToUint8(v_0.AuxInt) + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VGF2P8AFFINEQBMasked512) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VGF2P8MULB512 x y) mask) + // result: (VGF2P8MULBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VGF2P8MULB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VGF2P8MULBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPMAXSB512 x y) mask) + // result: (VPMAXSBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMAXSB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXSBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPMAXUB512 x y) mask) + // result: (VPMAXUBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMAXUB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMAXUBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPMINSB512 x y) mask) + // result: (VPMINSBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMINSB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINSBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPMINUB512 x y) mask) + // result: (VPMINUBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPMINUB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPMINUBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPOPCNTB512 x) mask) + // result: (VPOPCNTBMasked512 x mask) + for { + if v_0.Op != OpAMD64VPOPCNTB512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPOPCNTBMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPERMB512 x y) mask) + // result: (VPERMBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPERMB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPERMBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPSHUFB512 x y) mask) + // result: (VPSHUFBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSHUFB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSHUFBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPSUBB512 x y) mask) + // result: (VPSUBBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSUBB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPSUBSB512 x y) mask) + // result: (VPSUBSBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSUBSB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBSBMasked512) + v.AddArg3(x, y, mask) + return true + } + // match: (VMOVDQU8Masked512 (VPSUBUSB512 x y) mask) + // result: (VPSUBUSBMasked512 x y mask) + for { + if v_0.Op != OpAMD64VPSUBUSB512 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VPSUBUSBMasked512) + v.AddArg3(x, y, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQUload128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQUload128 [off1] {sym} x:(ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (VMOVDQUload128 [off1+off2] {sym} ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(x.AuxInt) + ptr := x.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64VMOVDQUload128) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + // match: (VMOVDQUload128 [off1] {sym1} x:(LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (VMOVDQUload128 [off1+off2] {mergeSym(sym1, sym2)} base mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(x.AuxInt) + sym2 := auxToSym(x.Aux) + base := x.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64VMOVDQUload128) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQUload256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQUload256 [off1] {sym} x:(ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (VMOVDQUload256 [off1+off2] {sym} ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(x.AuxInt) + ptr := x.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64VMOVDQUload256) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + // match: (VMOVDQUload256 [off1] {sym1} x:(LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (VMOVDQUload256 [off1+off2] {mergeSym(sym1, sym2)} base mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(x.AuxInt) + sym2 := auxToSym(x.Aux) + base := x.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64VMOVDQUload256) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQUload512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQUload512 [off1] {sym} x:(ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (VMOVDQUload512 [off1+off2] {sym} ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(x.AuxInt) + ptr := x.Args[0] + mem := v_1 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64VMOVDQUload512) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + // match: (VMOVDQUload512 [off1] {sym1} x:(LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (VMOVDQUload512 [off1+off2] {mergeSym(sym1, sym2)} base mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(x.AuxInt) + sym2 := auxToSym(x.Aux) + base := x.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64VMOVDQUload512) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQUstore128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQUstore128 [off1] {sym} x:(ADDQconst [off2] ptr) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (VMOVDQUstore128 [off1+off2] {sym} ptr val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(x.AuxInt) + ptr := x.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64VMOVDQUstore128) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(ptr, val, mem) + return true + } + // match: (VMOVDQUstore128 [off1] {sym1} x:(LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (VMOVDQUstore128 [off1+off2] {mergeSym(sym1, sym2)} base val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(x.AuxInt) + sym2 := auxToSym(x.Aux) + base := x.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64VMOVDQUstore128) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQUstore256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQUstore256 [off1] {sym} x:(ADDQconst [off2] ptr) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (VMOVDQUstore256 [off1+off2] {sym} ptr val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(x.AuxInt) + ptr := x.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64VMOVDQUstore256) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(ptr, val, mem) + return true + } + // match: (VMOVDQUstore256 [off1] {sym1} x:(LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (VMOVDQUstore256 [off1+off2] {mergeSym(sym1, sym2)} base val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(x.AuxInt) + sym2 := auxToSym(x.Aux) + base := x.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64VMOVDQUstore256) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVDQUstore512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVDQUstore512 [off1] {sym} x:(ADDQconst [off2] ptr) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (VMOVDQUstore512 [off1+off2] {sym} ptr val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(x.AuxInt) + ptr := x.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64VMOVDQUstore512) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(ptr, val, mem) + return true + } + // match: (VMOVDQUstore512 [off1] {sym1} x:(LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (VMOVDQUstore512 [off1+off2] {mergeSym(sym1, sym2)} base val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + x := v_0 + if x.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(x.AuxInt) + sym2 := auxToSym(x.Aux) + base := x.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64VMOVDQUstore512) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVQ(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (VMOVQ x:(MOVQload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (VMOVQload [off] {sym} ptr mem) + for { + x := v_0 + if x.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64VMOVQload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVSDf2v(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (VMOVSDf2v x:(MOVSDload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (VMOVSDload [off] {sym} ptr mem) + for { + x := v_0 + if x.Op != OpAMD64MOVSDload { + break + } + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64VMOVSDload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + return true + } + // match: (VMOVSDf2v x:(MOVSDconst [c] )) + // result: (VMOVSDconst [c] ) + for { + x := v_0 + if x.Op != OpAMD64MOVSDconst { + break + } + c := auxIntToFloat64(x.AuxInt) + v.reset(OpAMD64VMOVSDconst) + v.AuxInt = float64ToAuxInt(c) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMOVSSf2v(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (VMOVSSf2v x:(MOVSSload [off] {sym} ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: @x.Block (VMOVSSload [off] {sym} ptr mem) + for { + x := v_0 + if x.Op != OpAMD64MOVSSload { + break + } + off := auxIntToInt32(x.AuxInt) + sym := auxToSym(x.Aux) + mem := x.Args[1] + ptr := x.Args[0] + if !(x.Uses == 1 && clobber(x)) { + break + } + b = x.Block + v0 := b.NewValue0(x.Pos, OpAMD64VMOVSSload, v.Type) + v.copyOf(v0) + v0.AuxInt = int32ToAuxInt(off) + v0.Aux = symToAux(sym) + v0.AddArg2(ptr, mem) + return true + } + // match: (VMOVSSf2v x:(MOVSSconst [c] )) + // result: (VMOVSSconst [c] ) + for { + x := v_0 + if x.Op != OpAMD64MOVSSconst { + break + } + c := auxIntToFloat32(x.AuxInt) + v.reset(OpAMD64VMOVSSconst) + v.AuxInt = float32ToAuxInt(c) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPS128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPS256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPS512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPS512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPSMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPSMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPSMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPSMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VMULPSMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMULPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VMULPSMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VMULPSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSB128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPABSB128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSB128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSB256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPABSB256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSB256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSBMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPABSBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSBMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSBMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPABSBMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSBMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPABSD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPABSD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPABSD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPABSDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPABSDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPABSDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPABSQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPABSQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPABSQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPABSQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPABSQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPABSQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSW128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPABSW128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSW128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSW256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPABSW256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSW256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSWMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPABSWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSWMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPABSWMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPABSWMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPABSWMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPABSWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKSSDW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKSSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKSSDW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKSSDW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKSSDW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKSSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKSSDW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKSSDW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKSSDW512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKSSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKSSDW512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKSSDW512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKSSDWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKSSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKSSDWMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKSSDWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKSSDWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKSSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKSSDWMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKSSDWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKSSDWMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKSSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKSSDWMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKSSDWMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKUSDW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKUSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKUSDW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKUSDW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKUSDW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKUSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKUSDW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKUSDW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKUSDW512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKUSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKUSDW512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKUSDW512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKUSDWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKUSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKUSDWMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKUSDWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKUSDWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKUSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKUSDWMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKUSDWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPACKUSDWMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPACKUSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPACKUSDWMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPACKUSDWMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDB128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDB256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDBMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDBMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDQ128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDQ256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDQ512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDQMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDQMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDQMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDSB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDSB128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDSB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDSB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDSB256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDSB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDSBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDSBMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDSBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDSBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDSBMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDSBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDSW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDSW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDSW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDSW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDSW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDSW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDSWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDSWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDSWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDSWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDSWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDSWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDUSB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDUSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDUSB128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDUSB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDUSB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDUSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDUSB256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDUSB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDUSBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDUSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDUSBMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDUSBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDUSBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDUSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDUSBMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDUSBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDUSW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDUSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDUSW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDUSW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDUSW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDUSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDUSW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDUSW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDUSWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDUSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDUSWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDUSWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDUSWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDUSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDUSWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDUSWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPADDWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPADDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPADDWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPADDWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPALIGNR128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPALIGNR128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPALIGNR128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPALIGNR128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPALIGNR256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPALIGNR256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPALIGNR256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPALIGNR256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPALIGNRMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPALIGNRMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPALIGNRMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPALIGNRMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPALIGNRMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPALIGNRMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPALIGNRMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPALIGNRMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPAND128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (VPAND128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec8x16 (KANDW x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec8x16 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec8x16 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64KANDW, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPAND128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec16x8 (KANDB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec16x8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec16x8 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64KANDB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPAND128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec32x4 (KANDB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec32x4 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec32x4 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64KANDB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPAND128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec64x2 (KANDB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec64x2 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec64x2 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64KANDB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPAND128 x (VPMOVMToVec8x16 k)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMOVDQU8Masked128 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec8x16 { + continue + } + k := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VMOVDQU8Masked128) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPAND128 x (VPMOVMToVec16x8 k)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMOVDQU16Masked128 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec16x8 { + continue + } + k := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VMOVDQU16Masked128) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPAND128 x (VPMOVMToVec32x4 k)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMOVDQU32Masked128 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec32x4 { + continue + } + k := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VMOVDQU32Masked128) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPAND128 x (VPMOVMToVec64x2 k)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMOVDQU64Masked128 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec64x2 { + continue + } + k := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VMOVDQU64Masked128) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPAND128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPAND128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPAND128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPAND256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (VPAND256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec8x32 (KANDD x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec8x32 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec8x32 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64KANDD, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPAND256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec16x16 (KANDW x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec16x16 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec16x16 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64KANDW, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPAND256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec32x8 (KANDB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec32x8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec32x8 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64KANDB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPAND256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec64x4 (KANDB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec64x4 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec64x4 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64KANDB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPAND256 x (VPMOVMToVec8x32 k)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMOVDQU8Masked256 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec8x32 { + continue + } + k := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VMOVDQU8Masked256) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPAND256 x (VPMOVMToVec16x16 k)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMOVDQU16Masked256 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec16x16 { + continue + } + k := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VMOVDQU16Masked256) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPAND256 x (VPMOVMToVec32x8 k)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMOVDQU32Masked256 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec32x8 { + continue + } + k := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VMOVDQU32Masked256) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPAND256 x (VPMOVMToVec64x4 k)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMOVDQU64Masked256 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec64x4 { + continue + } + k := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VMOVDQU64Masked256) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPAND256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPAND256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPAND256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (VPANDD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec8x64 (KANDQ x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec8x64 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec8x64 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64KANDQ, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPANDD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec16x32 (KANDD x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec16x32 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec16x32 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64KANDD, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPANDD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec32x16 (KANDW x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec32x16 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec32x16 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64KANDW, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPANDD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec64x8 (KANDB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec64x8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec64x8 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64KANDB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPANDD512 x (VPMOVMToVec64x8 k)) + // result: (VMOVDQU64Masked512 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec64x8 { + continue + } + k := v_1.Args[0] + v.reset(OpAMD64VMOVDQU64Masked512) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPANDD512 x (VPMOVMToVec32x16 k)) + // result: (VMOVDQU32Masked512 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec32x16 { + continue + } + k := v_1.Args[0] + v.reset(OpAMD64VMOVDQU32Masked512) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPANDD512 x (VPMOVMToVec16x32 k)) + // result: (VMOVDQU16Masked512 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec16x32 { + continue + } + k := v_1.Args[0] + v.reset(OpAMD64VMOVDQU16Masked512) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPANDD512 x (VPMOVMToVec8x64 k)) + // result: (VMOVDQU8Masked512 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec8x64 { + continue + } + k := v_1.Args[0] + v.reset(OpAMD64VMOVDQU8Masked512) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPANDD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPANDD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPANDDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPANDDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPANDDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDN128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDN128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDN128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPANDN128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDN256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDN256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDN256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPANDN256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDND512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDND512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDND512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPANDND512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDNDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDNDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDNDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPANDNDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDNDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDNDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDNDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPANDNDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDNDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDNDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDNDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPANDNDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDNQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDNQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDNQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPANDNQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDNQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDNQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDNQMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPANDNQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDNQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDNQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDNQMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPANDNQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDNQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDNQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDNQMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPANDNQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDQ512 x (VPMOVMToVec64x8 k)) + // result: (VMOVDQU64Masked512 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec64x8 { + continue + } + k := v_1.Args[0] + v.reset(OpAMD64VMOVDQU64Masked512) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPANDQ512 x (VPMOVMToVec32x16 k)) + // result: (VMOVDQU32Masked512 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec32x16 { + continue + } + k := v_1.Args[0] + v.reset(OpAMD64VMOVDQU32Masked512) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPANDQ512 x (VPMOVMToVec16x32 k)) + // result: (VMOVDQU16Masked512 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec16x32 { + continue + } + k := v_1.Args[0] + v.reset(OpAMD64VMOVDQU16Masked512) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPANDQ512 x (VPMOVMToVec8x64 k)) + // result: (VMOVDQU8Masked512 x k) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64VPMOVMToVec8x64 { + continue + } + k := v_1.Args[0] + v.reset(OpAMD64VMOVDQU8Masked512) + v.AddArg2(x, k) + return true + } + break + } + // match: (VPANDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDQ512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPANDQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDQMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPANDQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDQMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPANDQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPANDQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPANDQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPANDQMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPANDQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPAVGB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPAVGB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPAVGB128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPAVGB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPAVGB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPAVGB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPAVGB256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPAVGB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPAVGBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPAVGBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPAVGBMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPAVGBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPAVGBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPAVGBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPAVGBMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPAVGBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPAVGW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPAVGW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPAVGW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPAVGW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPAVGW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPAVGW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPAVGW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPAVGW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPAVGWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPAVGWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPAVGWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPAVGWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPAVGWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPAVGWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPAVGWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPAVGWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPBLENDMBMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBLENDMBMasked512 dst (VGF2P8MULB512 x y) mask) + // result: (VGF2P8MULBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VGF2P8MULB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VGF2P8MULBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPABSB512 x) mask) + // result: (VPABSBMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSB512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPABSBMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPADDB512 x y) mask) + // result: (VPADDBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPADDBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPADDSB512 x y) mask) + // result: (VPADDSBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDSB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPADDSBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPADDUSB512 x y) mask) + // result: (VPADDUSBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDUSB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPADDUSBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPAVGB512 x y) mask) + // result: (VPAVGBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPAVGB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPAVGBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPMAXSB512 x y) mask) + // result: (VPMAXSBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMAXSBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPMAXUB512 x y) mask) + // result: (VPMAXUBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMAXUBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPMINSB512 x y) mask) + // result: (VPMINSBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMINSBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPMINUB512 x y) mask) + // result: (VPMINUBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMINUBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPOPCNTB512 x) mask) + // result: (VPOPCNTBMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTB512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPOPCNTBMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPSHUFB512 x y) mask) + // result: (VPSHUFBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSHUFBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPSUBB512 x y) mask) + // result: (VPSUBBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSUBBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPSUBSB512 x y) mask) + // result: (VPSUBSBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBSB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSUBSBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMBMasked512 dst (VPSUBUSB512 x y) mask) + // result: (VPSUBUSBMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBUSB512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSUBUSBMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBLENDMDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBLENDMDMasked512 dst (VADDPS512 x y) mask) + // result: (VADDPSMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VADDPS512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VADDPSMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VCVTDQ2PS512 x) mask) + // result: (VCVTDQ2PSMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTDQ2PS512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTDQ2PSMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask) + // result: (VCVTTPS2DQMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2DQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTTPS2DQMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VCVTTPS2UDQ512 x) mask) + // result: (VCVTTPS2UDQMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2UDQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTTPS2UDQMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VCVTUDQ2PS512 x) mask) + // result: (VCVTUDQ2PSMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUDQ2PS512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTUDQ2PSMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VDIVPS512 x y) mask) + // result: (VDIVPSMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VDIVPS512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VDIVPSMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VMAXPS512 x y) mask) + // result: (VMAXPSMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VMAXPS512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VMAXPSMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VMINPS512 x y) mask) + // result: (VMINPSMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VMINPS512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VMINPSMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VMULPS512 x y) mask) + // result: (VMULPSMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VMULPS512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VMULPSMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPABSD512 x) mask) + // result: (VPABSDMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSD512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPABSDMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPACKSSDW512 x y) mask) + // result: (VPACKSSDWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPACKSSDW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPACKSSDWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPACKUSDW512 x y) mask) + // result: (VPACKUSDWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPACKUSDW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPACKUSDWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPADDD512 x y) mask) + // result: (VPADDDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPADDDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPANDD512 x y) mask) + // result: (VPANDDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPANDD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPANDDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPLZCNTD512 x) mask) + // result: (VPLZCNTDMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPLZCNTD512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPLZCNTDMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMAXSD512 x y) mask) + // result: (VPMAXSDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMAXSDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMAXUD512 x y) mask) + // result: (VPMAXUDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMAXUDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMINSD512 x y) mask) + // result: (VPMINSDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMINSDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMINUD512 x y) mask) + // result: (VPMINUDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMINUDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMOVDB128_512 x) mask) + // result: (VPMOVDBMasked128_512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVDB128_512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVDBMasked128_512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMOVDW256 x) mask) + // result: (VPMOVDWMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVDW256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVDWMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMOVSDB128_512 x) mask) + // result: (VPMOVSDBMasked128_512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSDB128_512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVSDBMasked128_512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMOVSDW256 x) mask) + // result: (VPMOVSDWMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSDW256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVSDWMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMOVUSDB128_512 x) mask) + // result: (VPMOVUSDBMasked128_512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSDB128_512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVUSDBMasked128_512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMOVUSDW256 x) mask) + // result: (VPMOVUSDWMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSDW256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVUSDWMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPMULLD512 x y) mask) + // result: (VPMULLDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULLD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMULLDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPOPCNTD512 x) mask) + // result: (VPOPCNTDMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTD512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPOPCNTDMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPORD512 x y) mask) + // result: (VPORDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPORD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPORDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPROLVD512 x y) mask) + // result: (VPROLVDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPROLVD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPROLVDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPRORVD512 x y) mask) + // result: (VPRORVDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPRORVD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPRORVDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPSHUFD512 [a] x) mask) + // result: (VPSHUFDMasked512Merging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFD512 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSHUFDMasked512Merging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPSLLD512const [a] x) mask) + // result: (VPSLLDMasked512constMerging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLD512const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSLLDMasked512constMerging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPSLLVD512 x y) mask) + // result: (VPSLLVDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLVD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSLLVDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPSRAD512const [a] x) mask) + // result: (VPSRADMasked512constMerging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAD512const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRADMasked512constMerging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPSRAVD512 x y) mask) + // result: (VPSRAVDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAVD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRAVDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPSRLD512const [a] x) mask) + // result: (VPSRLDMasked512constMerging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLD512const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRLDMasked512constMerging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPSRLVD512 x y) mask) + // result: (VPSRLVDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLVD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRLVDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPSUBD512 x y) mask) + // result: (VPSUBDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSUBDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VPXORD512 x y) mask) + // result: (VPXORDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPXORD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPXORDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VRCP14PS512 x) mask) + // result: (VRCP14PSMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VRCP14PS512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VRCP14PSMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VREDUCEPS512 [a] x) mask) + // result: (VREDUCEPSMasked512Merging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VREDUCEPS512 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VREDUCEPSMasked512Merging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VRNDSCALEPS512 [a] x) mask) + // result: (VRNDSCALEPSMasked512Merging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VRNDSCALEPS512 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VRNDSCALEPSMasked512Merging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VRSQRT14PS512 x) mask) + // result: (VRSQRT14PSMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VRSQRT14PS512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VRSQRT14PSMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VSCALEFPS512 x y) mask) + // result: (VSCALEFPSMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VSCALEFPS512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VSCALEFPSMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VSQRTPS512 x) mask) + // result: (VSQRTPSMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VSQRTPS512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VSQRTPSMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMDMasked512 dst (VSUBPS512 x y) mask) + // result: (VSUBPSMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VSUBPS512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VSUBPSMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBLENDMDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBLENDMDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBLENDMQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBLENDMQMasked512 dst (VADDPD512 x y) mask) + // result: (VADDPDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VADDPD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VADDPDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTPD2PS256 x) mask) + // result: (VCVTPD2PSMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTPD2PS256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTPD2PSMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTQQ2PD512 x) mask) + // result: (VCVTQQ2PDMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTQQ2PD512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTQQ2PDMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTQQ2PS256 x) mask) + // result: (VCVTQQ2PSMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTQQ2PS256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTQQ2PSMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTTPD2DQ256 x) mask) + // result: (VCVTTPD2DQMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2DQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTTPD2DQMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTTPD2QQ512 x) mask) + // result: (VCVTTPD2QQMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2QQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTTPD2QQMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTTPD2UDQ256 x) mask) + // result: (VCVTTPD2UDQMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UDQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTTPD2UDQMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTTPD2UQQ512 x) mask) + // result: (VCVTTPD2UQQMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UQQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTTPD2UQQMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTUQQ2PD512 x) mask) + // result: (VCVTUQQ2PDMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUQQ2PD512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTUQQ2PDMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTUQQ2PS256 x) mask) + // result: (VCVTUQQ2PSMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUQQ2PS256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTUQQ2PSMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VDIVPD512 x y) mask) + // result: (VDIVPDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VDIVPD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VDIVPDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VMAXPD512 x y) mask) + // result: (VMAXPDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VMAXPD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VMAXPDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VMINPD512 x y) mask) + // result: (VMINPDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VMINPD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VMINPDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VMULPD512 x y) mask) + // result: (VMULPDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VMULPD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VMULPDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPABSQ512 x) mask) + // result: (VPABSQMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPABSQMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPADDQ512 x y) mask) + // result: (VPADDQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPADDQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPANDQ512 x y) mask) + // result: (VPANDQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPANDQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPANDQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPLZCNTQ512 x) mask) + // result: (VPLZCNTQMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPLZCNTQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPLZCNTQMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMAXSQ512 x y) mask) + // result: (VPMAXSQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMAXSQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMAXUQ512 x y) mask) + // result: (VPMAXUQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMAXUQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMINSQ512 x y) mask) + // result: (VPMINSQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMINSQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMINUQ512 x y) mask) + // result: (VPMINUQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMINUQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMOVQB128_512 x) mask) + // result: (VPMOVQBMasked128_512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVQB128_512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVQBMasked128_512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMOVQD256 x) mask) + // result: (VPMOVQDMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVQD256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVQDMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMOVQW128_512 x) mask) + // result: (VPMOVQWMasked128_512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVQW128_512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVQWMasked128_512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMOVSQB128_512 x) mask) + // result: (VPMOVSQBMasked128_512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSQB128_512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVSQBMasked128_512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMOVSQD256 x) mask) + // result: (VPMOVSQDMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSQD256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVSQDMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMOVSQW128_512 x) mask) + // result: (VPMOVSQWMasked128_512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSQW128_512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVSQWMasked128_512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMOVUSQB128_512 x) mask) + // result: (VPMOVUSQBMasked128_512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSQB128_512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVUSQBMasked128_512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMOVUSQD256 x) mask) + // result: (VPMOVUSQDMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSQD256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVUSQDMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMOVUSQW128_512 x) mask) + // result: (VPMOVUSQWMasked128_512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSQW128_512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVUSQWMasked128_512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPMULLQ512 x y) mask) + // result: (VPMULLQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULLQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMULLQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPOPCNTQ512 x) mask) + // result: (VPOPCNTQMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPOPCNTQMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPORQ512 x y) mask) + // result: (VPORQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPORQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPORQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPROLVQ512 x y) mask) + // result: (VPROLVQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPROLVQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPROLVQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPRORVQ512 x y) mask) + // result: (VPRORVQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPRORVQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPRORVQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPSLLQ512const [a] x) mask) + // result: (VPSLLQMasked512constMerging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLQ512const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSLLQMasked512constMerging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPSLLVQ512 x y) mask) + // result: (VPSLLVQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLVQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSLLVQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPSRAQ512const [a] x) mask) + // result: (VPSRAQMasked512constMerging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAQ512const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRAQMasked512constMerging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPSRAVQ512 x y) mask) + // result: (VPSRAVQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAVQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRAVQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPSRLQ512const [a] x) mask) + // result: (VPSRLQMasked512constMerging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLQ512const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRLQMasked512constMerging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPSRLVQ512 x y) mask) + // result: (VPSRLVQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLVQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRLVQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPSUBQ512 x y) mask) + // result: (VPSUBQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSUBQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VPXORQ512 x y) mask) + // result: (VPXORQMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPXORQ512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPXORQMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VRCP14PD512 x) mask) + // result: (VRCP14PDMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VRCP14PD512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VRCP14PDMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VREDUCEPD512 [a] x) mask) + // result: (VREDUCEPDMasked512Merging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VREDUCEPD512 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VREDUCEPDMasked512Merging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VRNDSCALEPD512 [a] x) mask) + // result: (VRNDSCALEPDMasked512Merging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VRNDSCALEPD512 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VRNDSCALEPDMasked512Merging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VRSQRT14PD512 x) mask) + // result: (VRSQRT14PDMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VRSQRT14PD512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VRSQRT14PDMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VSCALEFPD512 x y) mask) + // result: (VSCALEFPDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VSCALEFPD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VSCALEFPDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VSQRTPD512 x) mask) + // result: (VSQRTPDMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VSQRTPD512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VSQRTPDMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VSUBPD512 x y) mask) + // result: (VSUBPDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VSUBPD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VSUBPDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBLENDMQMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBLENDMQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBLENDMWMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBLENDMWMasked512 dst (VPABSW512 x) mask) + // result: (VPABSWMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSW512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPABSWMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPADDSW512 x y) mask) + // result: (VPADDSWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDSW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPADDSWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPADDUSW512 x y) mask) + // result: (VPADDUSWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDUSW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPADDUSWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPADDW512 x y) mask) + // result: (VPADDWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPADDWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPAVGW512 x y) mask) + // result: (VPAVGWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPAVGW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPAVGWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMADDUBSW512 x y) mask) + // result: (VPMADDUBSWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMADDUBSW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMADDUBSWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMADDWD512 x y) mask) + // result: (VPMADDWDMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMADDWD512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMADDWDMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMAXSW512 x y) mask) + // result: (VPMAXSWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMAXSWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMAXUW512 x y) mask) + // result: (VPMAXUWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMAXUWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMINSW512 x y) mask) + // result: (VPMINSWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMINSWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMINUW512 x y) mask) + // result: (VPMINUWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMINUWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMOVSWB256 x) mask) + // result: (VPMOVSWBMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSWB256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVSWBMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMOVUSWB256 x) mask) + // result: (VPMOVUSWBMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSWB256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVUSWBMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMOVWB256 x) mask) + // result: (VPMOVWBMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVWB256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMOVWBMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMULHUW512 x y) mask) + // result: (VPMULHUWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULHUW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMULHUWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMULHW512 x y) mask) + // result: (VPMULHWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULHW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMULHWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPMULLW512 x y) mask) + // result: (VPMULLWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULLW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPMULLWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPOPCNTW512 x) mask) + // result: (VPOPCNTWMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTW512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPOPCNTWMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSHUFHW512 [a] x) mask) + // result: (VPSHUFHWMasked512Merging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFHW512 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSHUFHWMasked512Merging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSHUFLW512 [a] x) mask) + // result: (VPSHUFLWMasked512Merging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFLW512 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSHUFLWMasked512Merging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSLLVW512 x y) mask) + // result: (VPSLLVWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLVW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSLLVWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSLLW512const [a] x) mask) + // result: (VPSLLWMasked512constMerging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLW512const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSLLWMasked512constMerging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSRAVW512 x y) mask) + // result: (VPSRAVWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAVW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRAVWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSRAW512const [a] x) mask) + // result: (VPSRAWMasked512constMerging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAW512const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRAWMasked512constMerging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSRLVW512 x y) mask) + // result: (VPSRLVWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLVW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRLVWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSRLW512const [a] x) mask) + // result: (VPSRLWMasked512constMerging dst [a] x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLW512const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSRLWMasked512constMerging) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSUBSW512 x y) mask) + // result: (VPSUBSWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBSW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSUBSWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSUBUSW512 x y) mask) + // result: (VPSUBUSWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBUSW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSUBUSWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + // match: (VPBLENDMWMasked512 dst (VPSUBW512 x y) mask) + // result: (VPSUBWMasked512Merging dst x y mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBW512 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VPSUBWMasked512Merging) + v.AddArg4(dst, x, y, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBLENDVB128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (VPBLENDVB128 dst (VADDPD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VADDPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VADDPD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VADDPDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VADDPS128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VADDPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VADDPS128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VADDPSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VBROADCASTSD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VBROADCASTSDMasked256Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VBROADCASTSD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VBROADCASTSDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VBROADCASTSD512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VBROADCASTSDMasked512Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VBROADCASTSD512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VBROADCASTSDMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VBROADCASTSS128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VBROADCASTSSMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VBROADCASTSS128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VBROADCASTSSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VBROADCASTSS256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VBROADCASTSSMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VBROADCASTSS256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VBROADCASTSSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VBROADCASTSS512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VBROADCASTSSMasked512Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VBROADCASTSS512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VBROADCASTSSMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTDQ2PD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTDQ2PD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTDQ2PDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTDQ2PS128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTDQ2PS128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTDQ2PSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTPD2PSX128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTPD2PSXMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTPD2PSX128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTPD2PSXMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTPS2PD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTPS2PDMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTPS2PD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTPS2PDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTQQ2PD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTQQ2PD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTQQ2PDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTQQ2PSX128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTQQ2PSX128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTQQ2PSXMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPD2DQX128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2DQXMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2DQX128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2DQXMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPD2QQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2QQMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2QQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2QQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPD2UDQX128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2UDQXMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UDQX128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQXMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPD2UQQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2UQQMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UQQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2UQQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPS2DQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2DQMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2DQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2DQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPS2QQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2QQMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2QQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2QQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPS2UDQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2UDQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPS2UQQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2UQQMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2UQQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTUDQ2PD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTUDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUDQ2PD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTUDQ2PDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTUDQ2PS128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTUDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUDQ2PS128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTUDQ2PSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTUQQ2PD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTUQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUQQ2PD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTUQQ2PDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTUQQ2PSX128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTUQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUQQ2PSX128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTUQQ2PSXMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VDIVPD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VDIVPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VDIVPD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VDIVPDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VDIVPS128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VDIVPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VDIVPS128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VDIVPSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VGF2P8MULB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VGF2P8MULBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VGF2P8MULB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VGF2P8MULBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VMAXPD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMAXPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMAXPD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMAXPDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VMAXPS128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMAXPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMAXPS128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMAXPSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VMINPD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMINPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMINPD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMINPDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VMINPS128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMINPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMINPS128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMINPSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VMULPD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMULPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMULPD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMULPDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VMULPS128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMULPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMULPS128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMULPSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPABSB128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPABSBMasked128Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSB128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPABSBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPABSD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPABSDMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPABSDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPABSQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPABSQMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPABSQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPABSW128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPABSWMasked128Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSW128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPABSWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPACKSSDW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPACKSSDWMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPACKSSDW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPACKSSDWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPACKUSDW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPACKUSDWMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPACKUSDW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPACKUSDWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPADDB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPADDD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPADDQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPADDSB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDSB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDSBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPADDSW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDSW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDSWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPADDUSB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDUSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDUSB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDUSBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPADDUSW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDUSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDUSW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDUSWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPADDW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPAVGB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPAVGBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPAVGB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPAVGBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPAVGW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPAVGWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPAVGW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPAVGWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTB128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTBMasked128Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTB128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTB256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTBMasked256Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTB256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTB512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTBMasked512Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTB512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTBMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTDMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTDMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTD512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTDMasked512Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTD512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTDMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTQMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTQMasked256Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTQMasked512Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTW128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTWMasked128Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTW128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTW256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTWMasked256Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTW256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPBROADCASTW512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPBROADCASTWMasked512Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPBROADCASTW512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPBROADCASTWMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPLZCNTD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPLZCNTDMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPLZCNTD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPLZCNTDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPLZCNTQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPLZCNTQMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPLZCNTQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPLZCNTQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMADDUBSW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMADDUBSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMADDUBSW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMADDUBSWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMADDWD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMADDWDMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMADDWD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMADDWDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMAXSB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXSBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMAXSD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXSDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXSDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMAXSQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXSQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXSQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMAXSW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXSWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMAXUB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXUBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXUBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMAXUD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXUDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXUDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMAXUQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXUQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXUQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMAXUW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXUWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXUWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMINSB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINSBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMINSD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINSDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINSDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMINSQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINSQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINSQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMINSW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINSWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMINUB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINUBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINUBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMINUD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINUDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINUDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMINUQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINUQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINUQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMINUW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINUWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINUWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVDB128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVDBMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVDB128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVDBMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVDW128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVDWMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVDW128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVDWMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVQB128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVQBMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVQB128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVQBMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVQD128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVQDMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVQD128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVQDMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVQW128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVQWMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVQW128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVQWMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSDB128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSDBMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSDB128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSDBMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSDW128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSDWMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSDW128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSDWMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSQB128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSQBMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSQB128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSQBMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSQD128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSQDMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSQD128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSQDMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSQW128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSQWMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSQW128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSQWMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSWB128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSWBMasked128_128Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSWB128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSWBMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXBD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXBDMasked128Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXBD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXBDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXBD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXBDMasked256Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXBD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXBDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXBD512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXBDMasked512Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXBD512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXBDMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXBQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXBQMasked128Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXBQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXBQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXBQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXBQMasked256Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXBQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXBQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXBQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXBQMasked512Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXBQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXBQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXBW128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXBWMasked128Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXBW128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXBWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXBW256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXBWMasked256Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXBW256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXBWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXDQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXDQMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXDQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXDQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXDQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXDQMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXDQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXDQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXWD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXWDMasked128Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXWD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXWDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXWD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXWDMasked256Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXWD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXWDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXWQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXWQMasked128Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXWQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXWQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXWQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXWQMasked256Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXWQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXWQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVSXWQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXWQMasked512Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXWQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXWQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVUSDB128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSDBMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSDB128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSDBMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVUSDW128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSDWMasked128_128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSDW128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSDWMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVUSQB128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSQBMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSQB128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSQBMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVUSQD128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSQDMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSQD128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSQDMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVUSQW128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSQWMasked128_128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSQW128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSQWMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVUSWB128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSWBMasked128_128Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSWB128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSWBMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVWB128_128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVWBMasked128_128Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVWB128_128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVWBMasked128_128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXBD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXBDMasked128Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXBD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXBDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXBD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXBDMasked256Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXBD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXBDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXBD512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXBDMasked512Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXBD512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXBDMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXBQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXBQMasked128Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXBQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXBQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXBQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXBQMasked256Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXBQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXBQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXBQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXBQMasked512Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXBQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXBQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXBW128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXBWMasked128Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXBW128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXBWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXBW256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXBWMasked256Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXBW256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXBWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXDQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXDQMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXDQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXDQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXDQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXDQMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXDQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXDQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXWD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXWDMasked128Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXWD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXWDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXWD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXWDMasked256Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXWD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXWDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXWQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXWQMasked128Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXWQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXWQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXWQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXWQMasked256Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXWQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXWQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMOVZXWQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXWQMasked512Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXWQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXWQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMULHUW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMULHUWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULHUW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMULHUWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMULHW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMULHWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULHW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMULHWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMULLD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMULLDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULLD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMULLDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMULLQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMULLQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULLQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMULLQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPMULLW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMULLWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULLW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMULLWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPOPCNTB128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPOPCNTBMasked128Merging dst x (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTB128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPOPCNTBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPOPCNTD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPOPCNTDMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPOPCNTDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPOPCNTQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPOPCNTQMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPOPCNTQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPOPCNTW128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPOPCNTWMasked128Merging dst x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTW128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPOPCNTWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPROLVD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPROLVDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPROLVD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPROLVDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPROLVQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPROLVQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPROLVQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPROLVQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPRORVD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPRORVDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPRORVD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPRORVDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPRORVQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPRORVQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPRORVQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPRORVQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSHUFB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSHUFBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSHUFBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSHUFD128 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSHUFDMasked128Merging dst [a] x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFD128 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSHUFDMasked128Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSHUFHW128 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSHUFHWMasked128Merging dst [a] x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFHW128 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSHUFHWMasked128Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSHUFLW128 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSHUFLWMasked128Merging dst [a] x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFLW128 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSHUFLWMasked128Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSLLD128const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLDMasked128constMerging dst [a] x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLD128const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLDMasked128constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSLLQ128const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLQMasked128constMerging dst [a] x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLQ128const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLQMasked128constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSLLVD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLVDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLVD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLVDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSLLVQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLVQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLVQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLVQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSLLVW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLVWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLVW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLVWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSLLW128const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLWMasked128constMerging dst [a] x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLW128const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLWMasked128constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRAD128const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRADMasked128constMerging dst [a] x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAD128const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRADMasked128constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRAQ128const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRAQMasked128constMerging dst [a] x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAQ128const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRAQMasked128constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRAVD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRAVDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAVD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRAVDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRAVQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRAVQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAVQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRAVQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRAVW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRAVWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAVW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRAVWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRAW128const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRAWMasked128constMerging dst [a] x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAW128const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRAWMasked128constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRLD128const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLDMasked128constMerging dst [a] x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLD128const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLDMasked128constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRLQ128const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLQMasked128constMerging dst [a] x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLQ128const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLQMasked128constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRLVD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLVDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLVD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLVDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRLVQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLVQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLVQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLVQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRLVW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLVWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLVW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLVWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSRLW128const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLWMasked128constMerging dst [a] x (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLW128const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLWMasked128constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSUBB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSUBD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBDMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSUBQ128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBQMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBQ128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSUBSB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBSB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBSBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSUBSW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBSW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBSWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSUBUSB128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBUSBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBUSB128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBUSBMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSUBUSW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBUSWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBUSW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBUSWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VPSUBW128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBWMasked128Merging dst x y (VPMOVVec16x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBW128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBWMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VRCP14PD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VRCP14PDMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VRCP14PD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VRCP14PDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VREDUCEPD128 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VREDUCEPDMasked128Merging dst [a] x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VREDUCEPD128 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VREDUCEPDMasked128Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VREDUCEPS128 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VREDUCEPSMasked128Merging dst [a] x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VREDUCEPS128 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VREDUCEPSMasked128Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VRNDSCALEPD128 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VRNDSCALEPDMasked128Merging dst [a] x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VRNDSCALEPD128 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VRNDSCALEPDMasked128Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VRNDSCALEPS128 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VRNDSCALEPSMasked128Merging dst [a] x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VRNDSCALEPS128 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VRNDSCALEPSMasked128Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VRSQRT14PD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VRSQRT14PDMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VRSQRT14PD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VRSQRT14PDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VSCALEFPD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSCALEFPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSCALEFPD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSCALEFPDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VSCALEFPS128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSCALEFPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSCALEFPS128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSCALEFPSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VSQRTPD128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSQRTPDMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSQRTPD128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSQRTPDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VSQRTPS128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSQRTPSMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSQRTPS128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSQRTPSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VSUBPD128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSUBPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSUBPD128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSUBPDMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB128 dst (VSUBPS128 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSUBPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSUBPS128 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSUBPSMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBLENDVB256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (VPBLENDVB256 dst (VADDPD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VADDPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VADDPD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VADDPDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VADDPS256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VADDPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VADDPS256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VADDPSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTDQ2PD512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTDQ2PD512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTDQ2PDMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTDQ2PS256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTDQ2PS256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTDQ2PSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTPD2PSY128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTPD2PSYMasked128Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTPD2PSY128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTPD2PSYMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTPS2PD512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTPS2PDMasked512Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTPS2PD512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTPS2PDMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTQQ2PD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTQQ2PD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTQQ2PDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTQQ2PSY128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTQQ2PSY128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTQQ2PSYMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPD2DQY128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2DQYMasked128Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2DQY128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2DQYMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPD2QQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2QQMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2QQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2QQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPD2UDQY128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2UDQYMasked128Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UDQY128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQYMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPD2UQQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2UQQMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UQQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2UQQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPS2DQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2DQMasked256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2DQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2DQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPS2QQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2QQMasked512Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2QQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2QQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPS2UDQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2UDQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPS2UQQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2UQQMasked512Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2UQQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTUDQ2PD512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTUDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUDQ2PD512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTUDQ2PDMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTUDQ2PS256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTUDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUDQ2PS256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTUDQ2PSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTUQQ2PD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTUQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUQQ2PD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTUQQ2PDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTUQQ2PSY128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTUQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTUQQ2PSY128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTUQQ2PSYMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VDIVPD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VDIVPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VDIVPD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VDIVPDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VDIVPS256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VDIVPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VDIVPS256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VDIVPSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VGF2P8MULB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VGF2P8MULBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VGF2P8MULB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VGF2P8MULBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VMAXPD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMAXPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMAXPD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMAXPDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VMAXPS256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMAXPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMAXPS256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMAXPSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VMINPD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMINPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMINPD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMINPDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VMINPS256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMINPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMINPS256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMINPSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VMULPD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMULPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMULPD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMULPDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VMULPS256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VMULPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VMULPS256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VMULPSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPABSB256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPABSBMasked256Merging dst x (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSB256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPABSBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPABSD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPABSDMasked256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPABSDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPABSQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPABSQMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPABSQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPABSW256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPABSWMasked256Merging dst x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPABSW256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPABSWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPACKSSDW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPACKSSDWMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPACKSSDW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPACKSSDWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPACKUSDW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPACKUSDWMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPACKUSDW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPACKUSDWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPADDB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPADDD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPADDQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPADDSB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDSB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDSBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPADDSW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDSW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDSWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPADDUSB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDUSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDUSB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDUSBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPADDUSW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDUSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDUSW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDUSWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPADDW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPADDWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPADDW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPADDWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPAVGB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPAVGBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPAVGB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPAVGBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPAVGW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPAVGWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPAVGW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPAVGWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPLZCNTD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPLZCNTDMasked256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPLZCNTD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPLZCNTDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPLZCNTQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPLZCNTQMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPLZCNTQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPLZCNTQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMADDUBSW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMADDUBSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMADDUBSW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMADDUBSWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMADDWD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMADDWDMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMADDWD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMADDWDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMAXSB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXSBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMAXSD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXSDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXSDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMAXSQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXSQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXSQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMAXSW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXSW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXSWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMAXUB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXUBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXUBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMAXUD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXUDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXUDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMAXUQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXUQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXUQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMAXUW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMAXUWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMAXUW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMAXUWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMINSB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINSBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMINSD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINSDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINSDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMINSQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINSQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINSQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMINSW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINSW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINSWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMINUB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINUBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINUBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMINUD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINUDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINUDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMINUQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINUQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINUQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMINUW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMINUWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMINUW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMINUWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVDB128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVDBMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVDB128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVDBMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVDW128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVDWMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVDW128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVDWMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVQB128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVQBMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVQB128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVQBMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVQD128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVQDMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVQD128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVQDMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVQW128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVQWMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVQW128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVQWMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVSDB128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSDBMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSDB128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSDBMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVSDW128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSDWMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSDW128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSDWMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVSQB128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSQBMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSQB128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSQBMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVSQD128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSQDMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSQD128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSQDMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVSQW128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSQWMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSQW128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSQWMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVSWB128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSWBMasked128_256Merging dst x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSWB128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSWBMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVSXBW512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXBWMasked512Merging dst x (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXBW512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXBWMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVSXDQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXDQMasked512Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXDQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXDQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVSXWD512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVSXWDMasked512Merging dst x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVSXWD512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVSXWDMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVUSDB128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSDBMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSDB128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSDBMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVUSDW128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSDWMasked128_256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSDW128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSDWMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVUSQB128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSQBMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSQB128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSQBMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVUSQD128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSQDMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSQD128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSQDMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVUSQW128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSQWMasked128_256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSQW128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSQWMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVUSWB128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVUSWBMasked128_256Merging dst x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVUSWB128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVUSWBMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVWB128_256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVWBMasked128_256Merging dst x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVWB128_256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVWBMasked128_256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVZXBW512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXBWMasked512Merging dst x (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXBW512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXBWMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVZXDQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXDQMasked512Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXDQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXDQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMOVZXWD512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVZXWDMasked512Merging dst x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMOVZXWD512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMOVZXWDMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMULHUW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMULHUWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULHUW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMULHUWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMULHW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMULHWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULHW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMULHWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMULLD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMULLDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULLD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMULLDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMULLQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMULLQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULLQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMULLQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPMULLW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMULLWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPMULLW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPMULLWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPOPCNTB256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPOPCNTBMasked256Merging dst x (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTB256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPOPCNTBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPOPCNTD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPOPCNTDMasked256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPOPCNTDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPOPCNTQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPOPCNTQMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPOPCNTQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPOPCNTW256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPOPCNTWMasked256Merging dst x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPOPCNTW256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPOPCNTWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPROLVD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPROLVDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPROLVD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPROLVDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPROLVQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPROLVQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPROLVQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPROLVQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPRORVD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPRORVDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPRORVD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPRORVDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPRORVQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPRORVQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPRORVQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPRORVQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSHUFB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSHUFBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSHUFBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSHUFD256 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSHUFDMasked256Merging dst [a] x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFD256 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSHUFDMasked256Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSHUFHW256 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSHUFHWMasked256Merging dst [a] x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFHW256 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSHUFHWMasked256Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSHUFLW256 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSHUFLWMasked256Merging dst [a] x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSHUFLW256 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSHUFLWMasked256Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSLLD256const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLDMasked256constMerging dst [a] x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLD256const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLDMasked256constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSLLQ256const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLQMasked256constMerging dst [a] x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLQ256const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLQMasked256constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSLLVD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLVDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLVD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLVDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSLLVQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLVQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLVQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLVQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSLLVW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLVWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLVW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLVWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSLLW256const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSLLWMasked256constMerging dst [a] x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSLLW256const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSLLWMasked256constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRAD256const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRADMasked256constMerging dst [a] x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAD256const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRADMasked256constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRAQ256const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRAQMasked256constMerging dst [a] x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAQ256const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRAQMasked256constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRAVD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRAVDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAVD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRAVDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRAVQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRAVQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAVQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRAVQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRAVW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRAVWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAVW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRAVWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRAW256const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRAWMasked256constMerging dst [a] x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRAW256const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRAWMasked256constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRLD256const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLDMasked256constMerging dst [a] x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLD256const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLDMasked256constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRLQ256const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLQMasked256constMerging dst [a] x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLQ256const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLQMasked256constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRLVD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLVDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLVD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLVDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRLVQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLVQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLVQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLVQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRLVW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLVWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLVW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLVWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSRLW256const [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSRLWMasked256constMerging dst [a] x (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSRLW256const { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSRLWMasked256constMerging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSUBB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSUBD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBDMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSUBQ256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBQMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBQ256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSUBSB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBSB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBSBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSUBSW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBSW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBSWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSUBUSB256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBUSBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBUSB256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBUSBMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSUBUSW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBUSWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBUSW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBUSWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VPSUBW256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPSUBWMasked256Merging dst x y (VPMOVVec16x16ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VPSUBW256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VPSUBWMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VRCP14PD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VRCP14PDMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VRCP14PD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VRCP14PDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VREDUCEPD256 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VREDUCEPDMasked256Merging dst [a] x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VREDUCEPD256 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VREDUCEPDMasked256Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VREDUCEPS256 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VREDUCEPSMasked256Merging dst [a] x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VREDUCEPS256 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VREDUCEPSMasked256Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VRNDSCALEPD256 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VRNDSCALEPDMasked256Merging dst [a] x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VRNDSCALEPD256 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VRNDSCALEPDMasked256Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VRNDSCALEPS256 [a] x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VRNDSCALEPSMasked256Merging dst [a] x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VRNDSCALEPS256 { + break + } + a := auxIntToUint8(v_1.AuxInt) + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VRNDSCALEPSMasked256Merging) + v.AuxInt = uint8ToAuxInt(a) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VRSQRT14PD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VRSQRT14PDMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VRSQRT14PD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VRSQRT14PDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VSCALEFPD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSCALEFPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSCALEFPD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSCALEFPDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VSCALEFPS256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSCALEFPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSCALEFPS256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSCALEFPSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VSQRTPD256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSQRTPDMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSQRTPD256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSQRTPDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VSQRTPS256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSQRTPSMasked256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSQRTPS256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSQRTPSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VSUBPD256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSUBPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSUBPD256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSUBPDMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + // match: (VPBLENDVB256 dst (VSUBPS256 x y) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VSUBPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VSUBPS256 { + break + } + y := v_1.Args[1] + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VSUBPSMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(dst, x, y, v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTB128(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (VPBROADCASTB128 x:(VPINSRB128 [0] (Zero128 ) y)) + // cond: x.Uses == 1 + // result: (VPBROADCASTB128 (VMOVQ y)) + for { + x := v_0 + if x.Op != OpAMD64VPINSRB128 || auxIntToUint8(x.AuxInt) != 0 { + break + } + y := x.Args[1] + x_0 := x.Args[0] + if x_0.Op != OpAMD64Zero128 { + break + } + if !(x.Uses == 1) { + break + } + v.reset(OpAMD64VPBROADCASTB128) + v0 := b.NewValue0(v.Pos, OpAMD64VMOVQ, types.TypeVec128) + v0.AddArg(y) + v.AddArg(v0) + return true + } + // match: (VPBROADCASTB128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTB128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTB256(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (VPBROADCASTB256 x:(VPINSRB128 [0] (Zero128 ) y)) + // cond: x.Uses == 1 + // result: (VPBROADCASTB256 (VMOVQ y)) + for { + x := v_0 + if x.Op != OpAMD64VPINSRB128 || auxIntToUint8(x.AuxInt) != 0 { + break + } + y := x.Args[1] + x_0 := x.Args[0] + if x_0.Op != OpAMD64Zero128 { + break + } + if !(x.Uses == 1) { + break + } + v.reset(OpAMD64VPBROADCASTB256) + v0 := b.NewValue0(v.Pos, OpAMD64VMOVQ, types.TypeVec128) + v0.AddArg(y) + v.AddArg(v0) + return true + } + // match: (VPBROADCASTB256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTB256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTB512(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (VPBROADCASTB512 x:(VPINSRB128 [0] (Zero128 ) y)) + // cond: x.Uses == 1 + // result: (VPBROADCASTB512 (VMOVQ y)) + for { + x := v_0 + if x.Op != OpAMD64VPINSRB128 || auxIntToUint8(x.AuxInt) != 0 { + break + } + y := x.Args[1] + x_0 := x.Args[0] + if x_0.Op != OpAMD64Zero128 { + break + } + if !(x.Uses == 1) { + break + } + v.reset(OpAMD64VPBROADCASTB512) + v0 := b.NewValue0(v.Pos, OpAMD64VMOVQ, types.TypeVec128) + v0.AddArg(y) + v.AddArg(v0) + return true + } + // match: (VPBROADCASTB512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTB512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTB512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTBMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBROADCASTBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTBMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTBMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBROADCASTBMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTBMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTBMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBROADCASTBMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTBMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTBMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPBROADCASTD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPBROADCASTD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPBROADCASTD512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBROADCASTDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBROADCASTDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBROADCASTDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPBROADCASTQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPBROADCASTQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPBROADCASTQ512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBROADCASTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBROADCASTQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPBROADCASTQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTW128(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (VPBROADCASTW128 x:(VPINSRW128 [0] (Zero128 ) y)) + // cond: x.Uses == 1 + // result: (VPBROADCASTW128 (VMOVQ y)) + for { + x := v_0 + if x.Op != OpAMD64VPINSRW128 || auxIntToUint8(x.AuxInt) != 0 { + break + } + y := x.Args[1] + x_0 := x.Args[0] + if x_0.Op != OpAMD64Zero128 { + break + } + if !(x.Uses == 1) { + break + } + v.reset(OpAMD64VPBROADCASTW128) + v0 := b.NewValue0(v.Pos, OpAMD64VMOVQ, types.TypeVec128) + v0.AddArg(y) + v.AddArg(v0) + return true + } + // match: (VPBROADCASTW128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTW128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTW256(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (VPBROADCASTW256 x:(VPINSRW128 [0] (Zero128 ) y)) + // cond: x.Uses == 1 + // result: (VPBROADCASTW256 (VMOVQ y)) + for { + x := v_0 + if x.Op != OpAMD64VPINSRW128 || auxIntToUint8(x.AuxInt) != 0 { + break + } + y := x.Args[1] + x_0 := x.Args[0] + if x_0.Op != OpAMD64Zero128 { + break + } + if !(x.Uses == 1) { + break + } + v.reset(OpAMD64VPBROADCASTW256) + v0 := b.NewValue0(v.Pos, OpAMD64VMOVQ, types.TypeVec128) + v0.AddArg(y) + v.AddArg(v0) + return true + } + // match: (VPBROADCASTW256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPBROADCASTW256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPBROADCASTW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPBROADCASTW512(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (VPBROADCASTW512 x:(VPINSRW128 [0] (Zero128 ) y)) + // cond: x.Uses == 1 + // result: (VPBROADCASTW512 (VMOVQ y)) + for { + x := v_0 + if x.Op != OpAMD64VPINSRW128 || auxIntToUint8(x.AuxInt) != 0 { + break + } + y := x.Args[1] + x_0 := x.Args[0] + if x_0.Op != OpAMD64Zero128 { + break + } + if !(x.Uses == 1) { + break + } + v.reset(OpAMD64VPBROADCASTW512) + v0 := b.NewValue0(v.Pos, OpAMD64VMOVQ, types.TypeVec128) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCLMULQDQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCLMULQDQ128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCLMULQDQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCLMULQDQ128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCLMULQDQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCLMULQDQ256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCLMULQDQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCLMULQDQ256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPBMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPBMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPBMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPBMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPDMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPDMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPDMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPEQB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPEQB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPEQB128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPCMPEQB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPEQB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPEQB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPEQB256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPCMPEQB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPEQD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPEQD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPEQD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPCMPEQD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPEQD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPEQD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPEQD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPCMPEQD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPEQD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPEQD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPEQD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPCMPEQD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPEQQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPEQQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPEQQ128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPCMPEQQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPEQQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPEQQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPEQQ256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPCMPEQQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPEQQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPEQQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPEQQ512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPCMPEQQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPEQW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPEQW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPEQW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPCMPEQW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPEQW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPEQW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPEQW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPCMPEQW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPGTB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPGTB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPGTB128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPGTB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPGTB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPGTB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPGTB256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPGTB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPGTD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPGTD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPGTD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPGTD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPGTD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPGTD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPGTD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPGTD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPGTD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPGTD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPGTD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPGTD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPGTQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPGTQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPGTQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPGTQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPGTQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPGTQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPGTQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPGTQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPGTQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPGTQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPGTQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPGTQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPGTW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPGTW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPGTW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPGTW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPGTW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPGTW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPGTW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPGTW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPQ512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPQMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPQMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPQMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUBMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUBMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUBMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUBMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUDMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUDMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUDMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUQ512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUQMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUQMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUQMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUWMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPUWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPUWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPUWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPUWMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPWMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPCMPWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPCMPWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPCMPWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPCMPWMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPDPWSSD128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPDPWSSD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPDPWSSD128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPDPWSSD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPDPWSSD256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPDPWSSD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPDPWSSD256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPDPWSSD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPDPWSSD512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPDPWSSD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPDPWSSD512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPDPWSSD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPDPWSSDMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPDPWSSDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPDPWSSDMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPDPWSSDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPDPWSSDMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPDPWSSDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPDPWSSDMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPDPWSSDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPDPWSSDMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPDPWSSDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPDPWSSDMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPDPWSSDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERM2F128256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERM2F128256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERM2F128256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERM2F128256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERM2I128256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERM2I128256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERM2I128256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERM2I128256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMB128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMB256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMBMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMBMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2B128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2B128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2B128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2B128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2B256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2B256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2B256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2B256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2BMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2BMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2BMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2BMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2BMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2BMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2BMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2BMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2D128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2D128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2D128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2D128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2D256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2D256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2D256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2D256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2D512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2D512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2D512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2D512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2DMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2DMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2DMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2DMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2DMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2DMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2DMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2DMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2DMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2DMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2DMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2DMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PD128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PD128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PD256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PD256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PD512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PD512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PDMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PDMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PDMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PDMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PDMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PDMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PS128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PS128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PS256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PS256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PS512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PS512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PSMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PSMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PSMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PSMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2PSMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2PSMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2PSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2Q128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2Q128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2Q128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2Q128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2Q256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2Q256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2Q256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2Q256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2Q512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2Q512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2Q512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2Q512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2QMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2QMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2QMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2QMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2QMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2QMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2QMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2QMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2QMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2QMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2QMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2QMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2W128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2W128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2W128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2W128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2W256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2W256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2W256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2W256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2WMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2WMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2WMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2WMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMI2WMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMI2WMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMI2WMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMI2WMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMPD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMPD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMPD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMPDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMPDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMPDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMPDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMPDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMPDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMPS256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMPS512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMPS512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMPS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMPSMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMPSMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMPSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMPSMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMPSMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMPSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMQMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMQMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMWMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPERMWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPERMWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPERMWMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPERMWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPEXPANDBMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPEXPANDBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPEXPANDBMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPEXPANDBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPEXPANDBMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPEXPANDBMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPEXPANDBMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPEXPANDBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPEXPANDDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPEXPANDDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPEXPANDDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPEXPANDDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPEXPANDDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPEXPANDDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPEXPANDDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPEXPANDDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPEXPANDQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPEXPANDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPEXPANDQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPEXPANDQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPEXPANDQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPEXPANDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPEXPANDQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPEXPANDQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPEXPANDWMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPEXPANDWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPEXPANDWMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPEXPANDWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPEXPANDWMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPEXPANDWMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPEXPANDWMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPEXPANDWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHADDD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHADDD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHADDD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHADDD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHADDD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHADDD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHADDD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHADDD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHADDSW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHADDSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHADDSW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHADDSW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHADDSW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHADDSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHADDSW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHADDSW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHADDW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHADDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHADDW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHADDW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHADDW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHADDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHADDW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHADDW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHSUBD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHSUBD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHSUBD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHSUBD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHSUBD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHSUBD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHSUBD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHSUBD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHSUBSW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHSUBSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHSUBSW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHSUBSW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHSUBSW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHSUBSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHSUBSW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHSUBSW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHSUBW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHSUBW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHSUBW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHSUBW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPHSUBW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPHSUBW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPHSUBW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPHSUBW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPINSRD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPINSRD128 [0] (Zero128 ) y) + // cond: y.Type.IsFloat() + // result: (VMOVSSf2v y) + for { + if auxIntToUint8(v.AuxInt) != 0 || v_0.Op != OpAMD64Zero128 { + break + } + y := v_1 + if !(y.Type.IsFloat()) { + break + } + v.reset(OpAMD64VMOVSSf2v) + v.Type = types.TypeVec128 + v.AddArg(y) + return true + } + // match: (VPINSRD128 [0] (Zero128 ) y) + // cond: !y.Type.IsFloat() + // result: (VMOVD y) + for { + if auxIntToUint8(v.AuxInt) != 0 || v_0.Op != OpAMD64Zero128 { + break + } + y := v_1 + if !(!y.Type.IsFloat()) { + break + } + v.reset(OpAMD64VMOVD) + v.Type = types.TypeVec128 + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPINSRQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPINSRQ128 [0] (Zero128 ) y) + // cond: y.Type.IsFloat() + // result: (VMOVSDf2v y) + for { + if auxIntToUint8(v.AuxInt) != 0 || v_0.Op != OpAMD64Zero128 { + break + } + y := v_1 + if !(y.Type.IsFloat()) { + break + } + v.reset(OpAMD64VMOVSDf2v) + v.Type = types.TypeVec128 + v.AddArg(y) + return true + } + // match: (VPINSRQ128 [0] (Zero128 ) y) + // cond: !y.Type.IsFloat() + // result: (VMOVQ y) + for { + if auxIntToUint8(v.AuxInt) != 0 || v_0.Op != OpAMD64Zero128 { + break + } + y := v_1 + if !(!y.Type.IsFloat()) { + break + } + v.reset(OpAMD64VMOVQ) + v.Type = types.TypeVec128 + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPLZCNTD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPLZCNTD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPLZCNTD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPLZCNTDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPLZCNTDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPLZCNTDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPLZCNTQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPLZCNTQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPLZCNTQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPLZCNTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPLZCNTQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPLZCNTQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPLZCNTQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPLZCNTQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPLZCNTQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMADDUBSW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMADDUBSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMADDUBSW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMADDUBSW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMADDUBSW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMADDUBSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMADDUBSW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMADDUBSW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMADDUBSWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMADDUBSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMADDUBSWMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMADDUBSWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMADDUBSWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMADDUBSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMADDUBSWMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMADDUBSWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMADDWD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMADDWD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMADDWD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMADDWD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMADDWD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMADDWD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMADDWD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMADDWD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMADDWDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMADDWDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMADDWDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMADDWDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMADDWDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMADDWDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMADDWDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMADDWDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSB128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSB256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSBMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSBMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSQ128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSQ256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSQ512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSQMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSQMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSQMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXSWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXSWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXSWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUB128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUB256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUBMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUBMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUQ128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUQ256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUQ512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUQMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUQMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUQMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMAXUWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMAXUWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMAXUWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMAXUWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSB128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSB256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSBMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSBMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSQ128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSQ256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSQ512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSQMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSQMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSQMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINSWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINSWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINSWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUB128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUB256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUBMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUBMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUQ128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUQ256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUQ512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUQMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUQMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUQMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMINUWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMINUWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMINUWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMINUWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXBD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXBD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXBD512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXBDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXBDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXBDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXBQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXBQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXBQ512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXBQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXBQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBW128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXBW128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBW128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBW256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXBW256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBW256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBW512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXBW512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBW512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBW512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBWMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXBWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBWMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBWMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXBWMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBWMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXBWMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXBWMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXBWMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXBWMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXDQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXDQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXDQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXDQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXDQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXDQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXDQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXDQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXDQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXDQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXDQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXDQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXDQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXDQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXDQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXDQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXDQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXDQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXDQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXDQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXWD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXWD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXWD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXWDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXWDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXWDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXWQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXWQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVSXWQ512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXWQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXWQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVSXWQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVSXWQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVSXWQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVSXWQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec16x16ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec16x16ToM (VPMOVMToVec16x16 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec16x16 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec16x32ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec16x32ToM (VPMOVMToVec16x32 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec16x32 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec16x8ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec16x8ToM (VPMOVMToVec16x8 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec16x8 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec32x16ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec32x16ToM (VPMOVMToVec32x16 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec32x16 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec32x4ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec32x4ToM (VPMOVMToVec32x4 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec32x4 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec32x8ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec32x8ToM (VPMOVMToVec32x8 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec32x8 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec64x2ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec64x2ToM (VPMOVMToVec64x2 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec64x2 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec64x4ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec64x4ToM (VPMOVMToVec64x4 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec64x4 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec64x8ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec64x8ToM (VPMOVMToVec64x8 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec64x8 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec8x16ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec8x16ToM (VPMOVMToVec8x16 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec8x16 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec8x32ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec8x32ToM (VPMOVMToVec8x32 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec8x32 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec8x64ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec8x64ToM (VPMOVMToVec8x64 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec8x64 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXBD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXBD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXBD512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXBDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXBDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXBDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXBQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXBQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXBQ512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXBQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXBQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBW128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXBW128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBW128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBW256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXBW256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBW256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBW512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXBW512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBW512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBW512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBWMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXBWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBWMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBWMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXBWMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBWMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXBWMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXBWMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXBWMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXBWMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXDQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXDQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXDQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXDQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXDQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXDQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXDQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXDQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXDQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXDQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXDQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXDQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXDQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXDQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXDQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXDQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXDQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXDQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXDQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXDQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXWD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXWD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXWD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXWDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXWDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXWDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXWQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXWQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVZXWQ512 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXWQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXWQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVZXWQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMOVZXWQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMOVZXWQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPMOVZXWQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULDQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULDQ128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULDQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULDQ256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULHUW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULHUW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULHUW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULHUW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULHUW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULHUW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULHUW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULHUW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULHUWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULHUWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULHUWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULHUWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULHUWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULHUWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULHUWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULHUWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULHW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULHW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULHW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULHW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULHW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULHW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULHW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULHW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULHWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULHWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULHWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULHWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULHWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULHWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULHWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULHWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLD128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLD256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLQ128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLQ256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLQ512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLQMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLQMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLQMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLW128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLW256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLWMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULLWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULLWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULLWMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULLWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULUDQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULUDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULUDQ128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULUDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPMULUDQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPMULUDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPMULUDQ256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPMULUDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTB128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPOPCNTB128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTB128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTB256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPOPCNTB256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTB256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTBMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPOPCNTBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTBMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTBMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPOPCNTBMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTBMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPOPCNTD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPOPCNTD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPOPCNTD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPOPCNTDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPOPCNTDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPOPCNTDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPOPCNTQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPOPCNTQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPOPCNTQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPOPCNTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPOPCNTQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPOPCNTQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTW128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPOPCNTW128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTW128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTW256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPOPCNTW256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTW256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTWMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPOPCNTWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTWMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOPCNTWMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPOPCNTWMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOPCNTWMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPOPCNTWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPOR128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (VPOR128 (VCMPPS128 [3] x x) (VCMPPS128 [3] y y)) + // result: (VCMPPS128 [3] x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VCMPPS128 || auxIntToUint8(v_0.AuxInt) != 3 { + continue + } + x := v_0.Args[1] + if x != v_0.Args[0] || v_1.Op != OpAMD64VCMPPS128 || auxIntToUint8(v_1.AuxInt) != 3 { + continue + } + y := v_1.Args[1] + if y != v_1.Args[0] { + continue + } + v.reset(OpAMD64VCMPPS128) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg2(x, y) + return true + } + break + } + // match: (VPOR128 (VCMPPD128 [3] x x) (VCMPPD128 [3] y y)) + // result: (VCMPPD128 [3] x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VCMPPD128 || auxIntToUint8(v_0.AuxInt) != 3 { + continue + } + x := v_0.Args[1] + if x != v_0.Args[0] || v_1.Op != OpAMD64VCMPPD128 || auxIntToUint8(v_1.AuxInt) != 3 { + continue + } + y := v_1.Args[1] + if y != v_1.Args[0] { + continue + } + v.reset(OpAMD64VCMPPD128) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg2(x, y) + return true + } + break + } + // match: (VPOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec8x16 (KORW x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec8x16 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec8x16 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64KORW, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec16x8 (KORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec16x8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec16x8 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64KORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec32x4 (KORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec32x4 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec32x4 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64KORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec64x2 (KORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec64x2 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec64x2 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64KORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPOR128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOR128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPOR128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPOR256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (VPOR256 (VCMPPS256 [3] x x) (VCMPPS256 [3] y y)) + // result: (VCMPPS256 [3] x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VCMPPS256 || auxIntToUint8(v_0.AuxInt) != 3 { + continue + } + x := v_0.Args[1] + if x != v_0.Args[0] || v_1.Op != OpAMD64VCMPPS256 || auxIntToUint8(v_1.AuxInt) != 3 { + continue + } + y := v_1.Args[1] + if y != v_1.Args[0] { + continue + } + v.reset(OpAMD64VCMPPS256) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg2(x, y) + return true + } + break + } + // match: (VPOR256 (VCMPPD256 [3] x x) (VCMPPD256 [3] y y)) + // result: (VCMPPD256 [3] x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VCMPPD256 || auxIntToUint8(v_0.AuxInt) != 3 { + continue + } + x := v_0.Args[1] + if x != v_0.Args[0] || v_1.Op != OpAMD64VCMPPD256 || auxIntToUint8(v_1.AuxInt) != 3 { + continue + } + y := v_1.Args[1] + if y != v_1.Args[0] { + continue + } + v.reset(OpAMD64VCMPPD256) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg2(x, y) + return true + } + break + } + // match: (VPOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec8x32 (KORD x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec8x32 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec8x32 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64KORD, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec16x16 (KORW x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec16x16 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec16x16 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64KORW, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec32x8 (KORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec32x8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec32x8 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64KORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec64x4 (KORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec64x4 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec64x4 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64KORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPOR256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPOR256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPOR256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPORD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (VPORD512 (VPMOVMToVec32x16 (VCMPPS512 [3] x x)) (VPMOVMToVec32x16 (VCMPPS512 [3] y y))) + // result: (VPMOVMToVec32x16 (VCMPPS512 [3] x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec32x16 { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64VCMPPS512 || auxIntToUint8(v_0_0.AuxInt) != 3 { + continue + } + x := v_0_0.Args[1] + if x != v_0_0.Args[0] || v_1.Op != OpAMD64VPMOVMToVec32x16 { + continue + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64VCMPPS512 || auxIntToUint8(v_1_0.AuxInt) != 3 { + continue + } + y := v_1_0.Args[1] + if y != v_1_0.Args[0] { + continue + } + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(3) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPORD512 (VPMOVMToVec64x8 (VCMPPD512 [3] x x)) (VPMOVMToVec64x8 (VCMPPD512 [3] y y))) + // result: (VPMOVMToVec64x8 (VCMPPD512 [3] x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec64x8 { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64VCMPPD512 || auxIntToUint8(v_0_0.AuxInt) != 3 { + continue + } + x := v_0_0.Args[1] + if x != v_0_0.Args[0] || v_1.Op != OpAMD64VPMOVMToVec64x8 { + continue + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64VCMPPD512 || auxIntToUint8(v_1_0.AuxInt) != 3 { + continue + } + y := v_1_0.Args[1] + if y != v_1_0.Args[0] { + continue + } + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(3) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec8x64 (KORQ x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec8x64 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec8x64 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64KORQ, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec16x32 (KORD x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec16x32 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec16x32 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64KORD, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec32x16 (KORW x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec32x16 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec32x16 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64KORW, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec64x8 (KORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec64x8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec64x8 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64KORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPORD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPORD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPORD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPORDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPORDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPORDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPORDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPORDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPORDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPORDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPORDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPORDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPORDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPORDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPORDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPORQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPORQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPORQ512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPORQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPORQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPORQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPORQMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPORQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPORQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPORQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPORQMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPORQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPORQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPORQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPORQMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPORQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPROLD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPROLD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPROLD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLD512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLDMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLDMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLDMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPROLQ128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLQ128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPROLQ256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLQ256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPROLQ512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLQ512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLQMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLQMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLQMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLQMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLQMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLQMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVQMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVQMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPROLVQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPROLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPROLVQMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPROLVQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPRORD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPRORD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPRORD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORD512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORDMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORDMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORDMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPRORQ128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORQ128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPRORQ256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORQ256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPRORQ512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORQ512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORQMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORQMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORQMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORQMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORQMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORQMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVQMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVQMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPRORVQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPRORVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPRORVQMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPRORVQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSADBW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSADBW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSADBW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSADBW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSADBW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSADBW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSADBW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSADBW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDD128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDD256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDDMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDDMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDDMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDQ128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDQ128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDQ256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDQ256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDQ512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDQMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDQMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDQMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVD128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVD128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVD256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVD256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVD512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVD512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVDMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVDMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVDMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVDMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVDMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVDMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVQ128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVQ128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVQ128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVQ256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVQ256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVQ256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVQ512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVQ512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVQ512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVQMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVQMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVQMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVQMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVQMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVQMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVQMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVQMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVQMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVW128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVW128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVW128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVW256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVW256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVW256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVWMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVWMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVWMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDVWMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDVWMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDVWMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDVWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDW128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDW128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDW128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDW256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDW256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDW256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDWMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHLDWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHLDWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHLDWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHLDWMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDD128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDD256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDDMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDDMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDDMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDQ128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDQ128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDQ256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDQ256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDQ512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDQMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDQMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDQMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDQMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDQMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDQMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVD128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVD128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVD256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVD256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVD512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVD512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVDMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVDMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVDMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVDMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVDMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVDMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVQ128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVQ128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVQ128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVQ256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVQ256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVQ256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVQ512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVQ512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVQ512load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVQMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVQMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVQMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVQMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVQMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVQMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVQMasked512(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVQMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVQMasked512load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVW128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVW128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVW128load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVW256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVW256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVW256load {sym} [off] x y ptr mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVWMasked128(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVWMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVWMasked128load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDVWMasked256(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDVWMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDVWMasked256load {sym} [off] x y ptr mask mem) + for { + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_3 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDVWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg5(x, y, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDW128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDW128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDW128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDW256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDW256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDW256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDWMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHRDWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHRDWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHRDWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHRDWMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFB128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFB256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFBMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFBMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSHUFD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSHUFD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSHUFD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFD512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFDMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFDMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFDMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFHW128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSHUFHW128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFHW128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFHW128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFHW256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSHUFHW256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFHW256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFHW256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFHWMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFHWMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFHWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFHWMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFHWMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFHWMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFHWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFHWMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFLW128(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSHUFLW128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFLW128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFLW128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFLW256(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSHUFLW256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFLW256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFLW256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFLWMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFLWMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFLWMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFLWMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSHUFLWMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSHUFLWMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSHUFLWMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSHUFLWMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSIGNB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSIGNB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSIGNB128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSIGNB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSIGNB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSIGNB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSIGNB256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSIGNB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSIGND128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSIGND128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSIGND128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSIGND128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSIGND256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSIGND256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSIGND256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSIGND256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSIGNW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSIGNW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSIGNW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSIGNW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSIGNW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSIGNW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSIGNW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSIGNW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLD128 x (MOVQconst [c])) + // result: (VPSLLD128const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSLLD128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLD128const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSLLD128const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLD256 x (MOVQconst [c])) + // result: (VPSLLD256const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSLLD256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLD256const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSLLD256const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLD512 x (MOVQconst [c])) + // result: (VPSLLD512const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSLLD512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLD512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSLLD512const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSLLD512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLD512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLD512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLDMasked128 x (MOVQconst [c]) mask) + // result: (VPSLLDMasked128const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSLLDMasked128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLDMasked128const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLDMasked128const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSLLDMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLDMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLDMasked128constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLDMasked256 x (MOVQconst [c]) mask) + // result: (VPSLLDMasked256const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSLLDMasked256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLDMasked256const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLDMasked256const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSLLDMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLDMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLDMasked256constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLDMasked512 x (MOVQconst [c]) mask) + // result: (VPSLLDMasked512const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSLLDMasked512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLDMasked512const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLDMasked512const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSLLDMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLDMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLDMasked512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLQ128 x (MOVQconst [c])) + // result: (VPSLLQ128const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSLLQ128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQ128const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSLLQ128const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLQ256 x (MOVQconst [c])) + // result: (VPSLLQ256const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSLLQ256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQ256const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSLLQ256const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLQ512 x (MOVQconst [c])) + // result: (VPSLLQ512const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSLLQ512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQ512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSLLQ512const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSLLQ512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLQ512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLQ512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLQMasked128 x (MOVQconst [c]) mask) + // result: (VPSLLQMasked128const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSLLQMasked128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQMasked128const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLQMasked128const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSLLQMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLQMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLQMasked128constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLQMasked256 x (MOVQconst [c]) mask) + // result: (VPSLLQMasked256const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSLLQMasked256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQMasked256const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLQMasked256const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSLLQMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLQMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLQMasked256constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLQMasked512 x (MOVQconst [c]) mask) + // result: (VPSLLQMasked512const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSLLQMasked512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLQMasked512const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLQMasked512const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSLLQMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLQMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLQMasked512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVQMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVQMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVQMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVWMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLVWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLVWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLVWMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLVWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLW128 x (MOVQconst [c])) + // result: (VPSLLW128const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSLLW128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLW128const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSLLW128const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLW256 x (MOVQconst [c])) + // result: (VPSLLW256const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSLLW256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLW256const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSLLW256const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLW512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLW512 x (MOVQconst [c])) + // result: (VPSLLW512const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSLLW512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLW512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSLLW512const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLWMasked128 x (MOVQconst [c]) mask) + // result: (VPSLLWMasked128const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSLLWMasked128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLWMasked128const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLWMasked128const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSLLWMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLWMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLWMasked128constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLWMasked256 x (MOVQconst [c]) mask) + // result: (VPSLLWMasked256const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSLLWMasked256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLWMasked256const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLWMasked256const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSLLWMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSLLWMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSLLWMasked256constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLWMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSLLWMasked512 x (MOVQconst [c]) mask) + // result: (VPSLLWMasked512const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSLLWMasked512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSLLWMasked512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSLLWMasked512const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAD128 x (MOVQconst [c])) + // result: (VPSRAD128const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRAD128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAD128const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRAD128const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAD256 x (MOVQconst [c])) + // result: (VPSRAD256const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRAD256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAD256const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRAD256const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAD512 x (MOVQconst [c])) + // result: (VPSRAD512const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRAD512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAD512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRAD512const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRAD512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAD512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAD512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRADMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRADMasked128 x (MOVQconst [c]) mask) + // result: (VPSRADMasked128const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRADMasked128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRADMasked128const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRADMasked128const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRADMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRADMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRADMasked128constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRADMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRADMasked256 x (MOVQconst [c]) mask) + // result: (VPSRADMasked256const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRADMasked256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRADMasked256const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRADMasked256const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRADMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRADMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRADMasked256constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRADMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRADMasked512 x (MOVQconst [c]) mask) + // result: (VPSRADMasked512const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRADMasked512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRADMasked512const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRADMasked512const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRADMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRADMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRADMasked512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAQ128 x (MOVQconst [c])) + // result: (VPSRAQ128const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRAQ128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQ128const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRAQ128const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRAQ128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAQ128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAQ128constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAQ256 x (MOVQconst [c])) + // result: (VPSRAQ256const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRAQ256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQ256const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRAQ256const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRAQ256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAQ256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAQ256constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAQ512 x (MOVQconst [c])) + // result: (VPSRAQ512const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRAQ512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQ512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRAQ512const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRAQ512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAQ512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAQ512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAQMasked128 x (MOVQconst [c]) mask) + // result: (VPSRAQMasked128const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRAQMasked128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQMasked128const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAQMasked128const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRAQMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAQMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAQMasked128constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAQMasked256 x (MOVQconst [c]) mask) + // result: (VPSRAQMasked256const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRAQMasked256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQMasked256const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAQMasked256const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRAQMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAQMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAQMasked256constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAQMasked512 x (MOVQconst [c]) mask) + // result: (VPSRAQMasked512const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRAQMasked512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAQMasked512const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAQMasked512const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRAQMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAQMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAQMasked512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVQMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVQMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVQMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVWMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAVWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAVWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAVWMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAVWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAW128 x (MOVQconst [c])) + // result: (VPSRAW128const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRAW128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAW128const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRAW128const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAW256 x (MOVQconst [c])) + // result: (VPSRAW256const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRAW256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAW256const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRAW256const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAW512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAW512 x (MOVQconst [c])) + // result: (VPSRAW512const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRAW512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAW512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRAW512const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAWMasked128 x (MOVQconst [c]) mask) + // result: (VPSRAWMasked128const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRAWMasked128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAWMasked128const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAWMasked128const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRAWMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAWMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAWMasked128constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAWMasked256 x (MOVQconst [c]) mask) + // result: (VPSRAWMasked256const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRAWMasked256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAWMasked256const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAWMasked256const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRAWMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRAWMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRAWMasked256constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAWMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRAWMasked512 x (MOVQconst [c]) mask) + // result: (VPSRAWMasked512const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRAWMasked512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRAWMasked512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRAWMasked512const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLD128 x (MOVQconst [c])) + // result: (VPSRLD128const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRLD128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLD128const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRLD128const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLD256 x (MOVQconst [c])) + // result: (VPSRLD256const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRLD256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLD256const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRLD256const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLD512 x (MOVQconst [c])) + // result: (VPSRLD512const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRLD512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLD512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRLD512const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRLD512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLD512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLD512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLDMasked128 x (MOVQconst [c]) mask) + // result: (VPSRLDMasked128const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRLDMasked128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLDMasked128const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLDMasked128const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRLDMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLDMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLDMasked128constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLDMasked256 x (MOVQconst [c]) mask) + // result: (VPSRLDMasked256const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRLDMasked256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLDMasked256const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLDMasked256const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRLDMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLDMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLDMasked256constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLDMasked512 x (MOVQconst [c]) mask) + // result: (VPSRLDMasked512const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRLDMasked512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLDMasked512const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLDMasked512const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRLDMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLDMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLDMasked512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLQ128 x (MOVQconst [c])) + // result: (VPSRLQ128const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRLQ128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQ128const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRLQ128const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLQ256 x (MOVQconst [c])) + // result: (VPSRLQ256const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRLQ256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQ256const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRLQ256const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLQ512 x (MOVQconst [c])) + // result: (VPSRLQ512const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRLQ512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQ512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRLQ512const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRLQ512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLQ512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLQ512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLQMasked128 x (MOVQconst [c]) mask) + // result: (VPSRLQMasked128const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRLQMasked128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQMasked128const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLQMasked128const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRLQMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLQMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLQMasked128constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLQMasked256 x (MOVQconst [c]) mask) + // result: (VPSRLQMasked256const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRLQMasked256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQMasked256const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLQMasked256const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRLQMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLQMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLQMasked256constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLQMasked512 x (MOVQconst [c]) mask) + // result: (VPSRLQMasked512const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRLQMasked512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLQMasked512const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLQMasked512const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRLQMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLQMasked512constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLQMasked512constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVQMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVQMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVQMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVWMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLVWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLVWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLVWMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLVWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLW128 x (MOVQconst [c])) + // result: (VPSRLW128const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRLW128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLW128const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRLW128const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLW256 x (MOVQconst [c])) + // result: (VPSRLW256const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRLW256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLW256const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRLW256const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLW512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLW512 x (MOVQconst [c])) + // result: (VPSRLW512const [amd64CapAVXShift(c)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64VPSRLW512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLW512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRLW512const [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLWMasked128 x (MOVQconst [c]) mask) + // result: (VPSRLWMasked128const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRLWMasked128const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLWMasked128const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLWMasked128const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRLWMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLWMasked128constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLWMasked128constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLWMasked256 x (MOVQconst [c]) mask) + // result: (VPSRLWMasked256const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRLWMasked256const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLWMasked256const(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLWMasked256const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + // match: (VPSRLWMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSRLWMasked256constload {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSRLWMasked256constload) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLWMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSRLWMasked512 x (MOVQconst [c]) mask) + // result: (VPSRLWMasked512const [amd64CapAVXShift(c)] x mask) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + mask := v_2 + v.reset(OpAMD64VPSRLWMasked512const) + v.AuxInt = uint8ToAuxInt(amd64CapAVXShift(c)) + v.AddArg2(x, mask) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSRLWMasked512const(v *Value) bool { + v_0 := v.Args[0] + // match: (VPSRLWMasked512const [a] x mask) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBB128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBB256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBBMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBBMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBQMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBQMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBQMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBSB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBSB128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBSB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBSB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBSB256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBSB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBSBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBSBMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBSBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBSBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBSBMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBSBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBSW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBSW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBSW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBSW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBSW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBSW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBSWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBSWMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBSWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBSWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBSWMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBSWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBUSB128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBUSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBUSB128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBUSB128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBUSB256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBUSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBUSB256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBUSB256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBUSBMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBUSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBUSBMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBUSBMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBUSBMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBUSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBUSBMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBUSBMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBUSW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBUSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBUSW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBUSW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBUSW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBUSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBUSW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBUSW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBUSWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBUSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBUSWMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBUSWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBUSWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBUSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBUSWMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBUSWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBW128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBW128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBW128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBW256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBW256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBW256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBWMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBWMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBWMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPSUBWMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPSUBWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPSUBWMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPSUBWMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPTERNLOGD128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPTERNLOGD128 [c] x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPTERNLOGD128load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPTERNLOGD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPTERNLOGD256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPTERNLOGD256 [c] x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPTERNLOGD256load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPTERNLOGD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPTERNLOGD512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPTERNLOGD512 [c] x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPTERNLOGD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPTERNLOGD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPTERNLOGQ128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPTERNLOGQ128 [c] x y l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPTERNLOGQ128load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPTERNLOGQ128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPTERNLOGQ256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPTERNLOGQ256 [c] x y l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPTERNLOGQ256load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPTERNLOGQ256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPTERNLOGQ512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPTERNLOGQ512 [c] x y l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPTERNLOGQ512load {sym} [makeValAndOff(int32(uint8(c)),off)] x y ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + y := v_1 + l := v_2 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPTERNLOGQ512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg4(x, y, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKHDQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKHDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKHDQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKHDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKHDQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKHDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKHDQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKHDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKHDQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKHDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKHDQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKHDQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKHQDQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKHQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKHQDQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKHQDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKHQDQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKHQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKHQDQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKHQDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKHQDQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKHQDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKHQDQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKHQDQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKHWD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKHWD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKHWD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKHWD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKHWD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKHWD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKHWD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKHWD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKLDQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKLDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKLDQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKLDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKLDQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKLDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKLDQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKLDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKLDQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKLDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKLDQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKLDQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKLQDQ128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKLQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKLQDQ128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKLQDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKLQDQ256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKLQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKLQDQ256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKLQDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKLQDQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKLQDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKLQDQ512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKLQDQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKLWD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKLWD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKLWD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKLWD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPUNPCKLWD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPUNPCKLWD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPUNPCKLWD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VPUNPCKLWD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPXOR128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (VPXOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec8x16 (KXORW x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec8x16 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec8x16 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64KXORW, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec16x8 (KXORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec16x8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec16x8 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64KXORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec32x4 (KXORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec32x4 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec32x4 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64KXORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec64x2 (KXORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec64x2 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec64x2 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64KXORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXOR128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPXOR128load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPXOR128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPXOR256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (VPXOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec8x32 (KXORD x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec8x32 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec8x32 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64KXORD, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec16x16 (KXORW x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec16x16 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec16x16 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64KXORW, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec32x8 (KXORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec32x8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec32x8 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64KXORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec64x4 (KXORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec64x4 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec64x4 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64KXORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXOR256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPXOR256load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPXOR256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPXORD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (VPXORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec8x64 (KXORQ x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec8x64 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec8x64 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64KXORQ, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec16x32 (KXORD x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec16x32 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec16x32 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64KXORD, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec32x16 (KXORW x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec32x16 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec32x16 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64KXORW, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VPMOVMToVec64x8 (KXORB x y)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64VPMOVMToVec64x8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpAMD64VPMOVMToVec64x8 { + continue + } + y := v_1.Args[0] + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + continue + } + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64KXORB, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (VPXORD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPXORD512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPXORD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPXORDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPXORDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPXORDMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPXORDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPXORDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPXORDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPXORDMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPXORDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPXORDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPXORDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPXORDMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPXORDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPXORQ512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPXORQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPXORQ512load {sym} [off] x ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPXORQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPXORQMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPXORQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPXORQMasked128load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPXORQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPXORQMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPXORQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPXORQMasked256load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPXORQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VPXORQMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VPXORQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VPXORQMasked512load {sym} [off] x ptr mask mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + continue + } + v.reset(OpAMD64VPXORQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64VRCP14PD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VRCP14PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCP14PD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCP14PD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCP14PD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VRCP14PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCP14PD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCP14PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCP14PD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VRCP14PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCP14PD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCP14PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCP14PDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRCP14PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCP14PDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCP14PDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCP14PDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRCP14PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCP14PDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCP14PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCP14PDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRCP14PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCP14PDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCP14PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCP14PS512(v *Value) bool { + v_0 := v.Args[0] + // match: (VRCP14PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCP14PS512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCP14PS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCP14PSMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRCP14PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCP14PSMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCP14PSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCP14PSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRCP14PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCP14PSMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCP14PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCP14PSMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRCP14PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCP14PSMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCP14PSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCPPS128(v *Value) bool { + v_0 := v.Args[0] + // match: (VRCPPS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCPPS128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCPPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRCPPS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VRCPPS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRCPPS256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRCPPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VREDUCEPD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VREDUCEPD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VREDUCEPD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPD512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VREDUCEPDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPDMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VREDUCEPDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPDMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VREDUCEPDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPDMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPS128(v *Value) bool { + v_0 := v.Args[0] + // match: (VREDUCEPS128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPS128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPS128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VREDUCEPS256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPS256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPS256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPS512(v *Value) bool { + v_0 := v.Args[0] + // match: (VREDUCEPS512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPS512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPS512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPSMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VREDUCEPSMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPSMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPSMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VREDUCEPSMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPSMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPSMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VREDUCEPSMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VREDUCEPSMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VREDUCEPSMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VREDUCEPSMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VRNDSCALEPD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VRNDSCALEPD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VRNDSCALEPD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPD512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRNDSCALEPDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPDMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPDMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRNDSCALEPDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPDMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPDMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRNDSCALEPDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPDMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPDMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPS128(v *Value) bool { + v_0 := v.Args[0] + // match: (VRNDSCALEPS128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPS128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPS128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VRNDSCALEPS256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPS256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPS256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPS512(v *Value) bool { + v_0 := v.Args[0] + // match: (VRNDSCALEPS512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPS512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPS512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPSMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRNDSCALEPSMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPSMasked128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPSMasked128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRNDSCALEPSMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPSMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPSMasked256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRNDSCALEPSMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRNDSCALEPSMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRNDSCALEPSMasked512load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mask mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRNDSCALEPSMasked512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VROUNDPD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VROUNDPD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VROUNDPD128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VROUNDPD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VROUNDPD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VROUNDPD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VROUNDPD256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VROUNDPD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VROUNDPS128(v *Value) bool { + v_0 := v.Args[0] + // match: (VROUNDPS128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VROUNDPS128load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VROUNDPS128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VROUNDPS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VROUNDPS256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VROUNDPS256load {sym} [makeValAndOff(int32(uint8(c)),off)] ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VROUNDPS256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRT14PD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VRSQRT14PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRT14PD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRT14PD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRT14PD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VRSQRT14PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRT14PD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRT14PD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRT14PD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VRSQRT14PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRT14PD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRT14PD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRT14PDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRSQRT14PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRT14PDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRT14PDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRT14PDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRSQRT14PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRT14PDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRT14PDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRT14PDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRSQRT14PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRT14PDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRT14PDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRT14PS512(v *Value) bool { + v_0 := v.Args[0] + // match: (VRSQRT14PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRT14PS512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRT14PS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRT14PSMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRSQRT14PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRT14PSMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRT14PSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRT14PSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRSQRT14PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRT14PSMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRT14PSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRT14PSMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VRSQRT14PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRT14PSMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRT14PSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRTPS128(v *Value) bool { + v_0 := v.Args[0] + // match: (VRSQRTPS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRTPS128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRTPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VRSQRTPS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VRSQRTPS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VRSQRTPS256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VRSQRTPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPS128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPS256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPS512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPS512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPSMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPSMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPSMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPSMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSCALEFPSMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSCALEFPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSCALEFPSMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSCALEFPSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSHUFPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSHUFPD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSHUFPD128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSHUFPD128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSHUFPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSHUFPD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSHUFPD256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSHUFPD256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSHUFPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSHUFPD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSHUFPD512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSHUFPD512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSHUFPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSHUFPS128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSHUFPS128load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSHUFPS128load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSHUFPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSHUFPS256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSHUFPS256load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSHUFPS256load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSHUFPS512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSHUFPS512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSHUFPS512load {sym} [makeValAndOff(int32(uint8(c)),off)] x ptr mem) + for { + c := auxIntToUint8(v.AuxInt) + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSHUFPS512load) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(uint8(c)), off)) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPD128(v *Value) bool { + v_0 := v.Args[0] + // match: (VSQRTPD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPD128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPD256(v *Value) bool { + v_0 := v.Args[0] + // match: (VSQRTPD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPD256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPD512(v *Value) bool { + v_0 := v.Args[0] + // match: (VSQRTPD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPD512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPDMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSQRTPDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPDMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPDMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSQRTPDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPDMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPDMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSQRTPDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPDMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPS128(v *Value) bool { + v_0 := v.Args[0] + // match: (VSQRTPS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPS128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPS256(v *Value) bool { + v_0 := v.Args[0] + // match: (VSQRTPS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPS256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPS512(v *Value) bool { + v_0 := v.Args[0] + // match: (VSQRTPS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPS512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPSMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSQRTPSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPSMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPSMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSQRTPSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPSMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSQRTPSMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSQRTPSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSQRTPSMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSQRTPSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPD128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPD128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPD128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPD256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPD256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPD256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPD512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPD512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPD512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPDMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPDMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPDMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPDMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPDMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPDMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPDMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPDMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPDMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPS128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPS128load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPS128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPS256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPS256load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPS256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPS512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPS512load {sym} [off] x ptr mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPS512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPSMasked128(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPSMasked128load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPSMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPSMasked256(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPSMasked256load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPSMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VSUBPSMasked512(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VSUBPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VSUBPSMasked512load {sym} [off] x ptr mask mem) + for { + x := v_0 + l := v_1 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_2 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VSUBPSMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg4(x, ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (XADDLlock [off1+off2] {sym} val ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + ptr := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64XADDLlock) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XADDQlock(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (XADDQlock [off1+off2] {sym} val ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + ptr := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64XADDQlock) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (XCHGL [off1+off2] {sym} val ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + ptr := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64XCHGL) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, ptr, mem) + return true + } + // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB + // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + ptr := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { + break + } + v.reset(OpAMD64XCHGL) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (XCHGQ [off1+off2] {sym} val ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + ptr := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64XCHGQ) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, ptr, mem) + return true + } + // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB + // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + ptr := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { + break + } + v.reset(OpAMD64XCHGQ) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XORL (SHLL (MOVLconst [1]) y) x) + // result: (BTCL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLL { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTCL) + v.AddArg2(x, y) + return true + } + break + } + // match: (XORL x (MOVLconst [c])) + // result: (XORLconst [c] x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64XORLconst) + v.AuxInt = int32ToAuxInt(c) + v.AddArg(x) + return true + } + break + } + // match: (XORL x x) + // result: (MOVLconst [0]) + for { + x := v_0 + if x != v_1 { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) + return true + } + // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (XORLload x [off] {sym} ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVLload { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64XORLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + // match: (XORL x (ADDLconst [-1] x)) + // cond: buildcfg.GOAMD64 >= 3 + // result: (BLSMSKL x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { + continue + } + v.reset(OpAMD64BLSMSKL) + v.AddArg(x) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64XORLconst(v *Value) bool { + v_0 := v.Args[0] + // match: (XORLconst [1] (SETNE x)) + // result: (SETEQ x) + for { + if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETNE { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETEQ) + v.AddArg(x) + return true + } + // match: (XORLconst [1] (SETEQ x)) + // result: (SETNE x) + for { + if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETEQ { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETNE) + v.AddArg(x) + return true + } + // match: (XORLconst [1] (SETL x)) + // result: (SETGE x) + for { + if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETL { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETGE) + v.AddArg(x) + return true + } + // match: (XORLconst [1] (SETGE x)) + // result: (SETL x) + for { + if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETGE { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETL) + v.AddArg(x) + return true + } + // match: (XORLconst [1] (SETLE x)) + // result: (SETG x) + for { + if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETLE { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETG) + v.AddArg(x) + return true + } + // match: (XORLconst [1] (SETG x)) + // result: (SETLE x) + for { + if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETG { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETLE) + v.AddArg(x) + return true + } + // match: (XORLconst [1] (SETB x)) + // result: (SETAE x) + for { + if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETB { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETAE) + v.AddArg(x) + return true + } + // match: (XORLconst [1] (SETAE x)) + // result: (SETB x) + for { + if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETAE { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETB) + v.AddArg(x) + return true + } + // match: (XORLconst [1] (SETBE x)) + // result: (SETA x) + for { + if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETBE { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETA) + v.AddArg(x) + return true + } + // match: (XORLconst [1] (SETA x)) + // result: (SETBE x) + for { + if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETA { + break + } + x := v_0.Args[0] + v.reset(OpAMD64SETBE) + v.AddArg(x) + return true + } + // match: (XORLconst [c] (XORLconst [d] x)) + // result: (XORLconst [c ^ d] x) + for { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64XORLconst { + break + } + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + v.reset(OpAMD64XORLconst) + v.AuxInt = int32ToAuxInt(c ^ d) + v.AddArg(x) + return true + } + // match: (XORLconst [0] x) + // result: x + for { + if auxIntToInt32(v.AuxInt) != 0 { + break + } + x := v_0 + v.copyOf(x) + return true + } + // match: (XORLconst [c] (MOVLconst [d])) + // result: (MOVLconst [c^d]) + for { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVLconst { + break + } + d := auxIntToInt32(v_0.AuxInt) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(c ^ d) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORLconstmodify(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XORLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) + // result: (XORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) + for { + valoff1 := auxIntToValAndOff(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2)) { + break + } + v.reset(OpAMD64XORLconstmodify) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(sym) + v.AddArg2(base, mem) + return true + } + // match: (XORLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) + // result: (XORLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) + for { + valoff1 := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64XORLconstmodify) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORLload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (XORLload [off1] {sym} val (ADDQconst [off2] base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (XORLload [off1+off2] {sym} val base mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64XORLload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, base, mem) + return true + } + // match: (XORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (XORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64XORLload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, base, mem) + return true + } + // match: (XORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) + // result: (XORL x (MOVLf2i y)) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + ptr := v_1 + if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { + break + } + y := v_2.Args[1] + if ptr != v_2.Args[0] { + break + } + v.reset(OpAMD64XORL) + v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORLmodify(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XORLmodify [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (XORLmodify [off1+off2] {sym} base val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64XORLmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) + return true + } + // match: (XORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (XORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64XORLmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XORQ (SHLQ (MOVQconst [1]) y) x) + // result: (BTCQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLQ { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTCQ) + v.AddArg2(x, y) + return true + } + break + } + // match: (XORQ (MOVQconst [c]) x) + // cond: isPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31 + // result: (BTCQconst [int8(log64u(uint64(c)))] x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64MOVQconst { + continue + } + c := auxIntToInt64(v_0.AuxInt) + x := v_1 + if !(isPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31) { + continue + } + v.reset(OpAMD64BTCQconst) + v.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) + v.AddArg(x) + return true + } + break + } + // match: (XORQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (XORQconst [int32(c)] x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := auxIntToInt64(v_1.AuxInt) + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64XORQconst) + v.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg(x) + return true + } + break + } + // match: (XORQ x x) + // result: (MOVLconst [0]) + for { + x := v_0 + if x != v_1 { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(0) + return true + } + // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) + // cond: canMergeLoadClobber(v, l, x) && clobber(l) + // result: (XORQload x [off] {sym} ptr mem) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + l := v_1 + if l.Op != OpAMD64MOVQload { + continue + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64XORQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(x, ptr, mem) + return true + } + break + } + // match: (XORQ x (ADDQconst [-1] x)) + // cond: buildcfg.GOAMD64 >= 3 + // result: (BLSMSKQ x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { + continue + } + v.reset(OpAMD64BLSMSKQ) + v.AddArg(x) + return true + } + break + } + return false +} +func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool { + v_0 := v.Args[0] + // match: (XORQconst [c] (XORQconst [d] x)) + // result: (XORQconst [c ^ d] x) + for { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64XORQconst { + break + } + d := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + v.reset(OpAMD64XORQconst) + v.AuxInt = int32ToAuxInt(c ^ d) + v.AddArg(x) + return true + } + // match: (XORQconst [0] x) + // result: x + for { + if auxIntToInt32(v.AuxInt) != 0 { + break + } + x := v_0 + v.copyOf(x) + return true + } + // match: (XORQconst [c] (MOVQconst [d])) + // result: (MOVQconst [int64(c)^d]) + for { + c := auxIntToInt32(v.AuxInt) + if v_0.Op != OpAMD64MOVQconst { + break + } + d := auxIntToInt64(v_0.AuxInt) + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(int64(c) ^ d) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORQconstmodify(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XORQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) + // result: (XORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) + for { + valoff1 := auxIntToValAndOff(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2)) { + break + } + v.reset(OpAMD64XORQconstmodify) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(sym) + v.AddArg2(base, mem) + return true + } + // match: (XORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) + // result: (XORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) + for { + valoff1 := auxIntToValAndOff(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + mem := v_1 + if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64XORQconstmodify) + v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(base, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORQload(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (XORQload [off1] {sym} val (ADDQconst [off2] base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (XORQload [off1+off2] {sym} val base mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64XORQload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(val, base, mem) + return true + } + // match: (XORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (XORQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + val := v_0 + if v_1.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_1.AuxInt) + sym2 := auxToSym(v_1.Aux) + base := v_1.Args[0] + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64XORQload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(val, base, mem) + return true + } + // match: (XORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) + // result: (XORQ x (MOVQf2i y)) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + x := v_0 + ptr := v_1 + if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { + break + } + y := v_2.Args[1] + if ptr != v_2.Args[0] { + break + } + v.reset(OpAMD64XORQ) + v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORQmodify(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XORQmodify [off1] {sym} (ADDQconst [off2] base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) + // result: (XORQmodify [off1+off2] {sym} base val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpAMD64ADDQconst { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1) + int64(off2))) { + break + } + v.reset(OpAMD64XORQmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(sym) + v.AddArg3(base, val, mem) + return true + } + // match: (XORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) + // result: (XORQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpAMD64LEAQ { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + base := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64XORQmodify) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(base, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAddr(v *Value) bool { + v_0 := v.Args[0] + // match: (Addr {sym} base) + // result: (LEAQ {sym} base) + for { + sym := auxToSym(v.Aux) + base := v_0 + v.reset(OpAMD64LEAQ) + v.Aux = symToAux(sym) + v.AddArg(base) + return true + } +} +func rewriteValueAMD64_OpAtomicAdd32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AtomicAdd32 ptr val mem) + // result: (AddTupleFirst32 val (XADDLlock val ptr mem)) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64AddTupleFirst32) + v0 := b.NewValue0(v.Pos, OpAMD64XADDLlock, types.NewTuple(typ.UInt32, types.TypeMem)) + v0.AddArg3(val, ptr, mem) + v.AddArg2(val, v0) + return true + } +} +func rewriteValueAMD64_OpAtomicAdd64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AtomicAdd64 ptr val mem) + // result: (AddTupleFirst64 val (XADDQlock val ptr mem)) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64AddTupleFirst64) + v0 := b.NewValue0(v.Pos, OpAMD64XADDQlock, types.NewTuple(typ.UInt64, types.TypeMem)) + v0.AddArg3(val, ptr, mem) + v.AddArg2(val, v0) + return true + } +} +func rewriteValueAMD64_OpAtomicAnd32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicAnd32 ptr val mem) + // result: (ANDLlock ptr val mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64ANDLlock) + v.AddArg3(ptr, val, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicAnd32value(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicAnd32value ptr val mem) + // result: (LoweredAtomicAnd32 ptr val mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64LoweredAtomicAnd32) + v.AddArg3(ptr, val, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicAnd64value(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicAnd64value ptr val mem) + // result: (LoweredAtomicAnd64 ptr val mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64LoweredAtomicAnd64) + v.AddArg3(ptr, val, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicAnd8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicAnd8 ptr val mem) + // result: (ANDBlock ptr val mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64ANDBlock) + v.AddArg3(ptr, val, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicCompareAndSwap32(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicCompareAndSwap32 ptr old new_ mem) + // result: (CMPXCHGLlock ptr old new_ mem) + for { + ptr := v_0 + old := v_1 + new_ := v_2 + mem := v_3 + v.reset(OpAMD64CMPXCHGLlock) + v.AddArg4(ptr, old, new_, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicCompareAndSwap64(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicCompareAndSwap64 ptr old new_ mem) + // result: (CMPXCHGQlock ptr old new_ mem) + for { + ptr := v_0 + old := v_1 + new_ := v_2 + mem := v_3 + v.reset(OpAMD64CMPXCHGQlock) + v.AddArg4(ptr, old, new_, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicExchange32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicExchange32 ptr val mem) + // result: (XCHGL val ptr mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64XCHGL) + v.AddArg3(val, ptr, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicExchange64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicExchange64 ptr val mem) + // result: (XCHGQ val ptr mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64XCHGQ) + v.AddArg3(val, ptr, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicExchange8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicExchange8 ptr val mem) + // result: (XCHGB val ptr mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64XCHGB) + v.AddArg3(val, ptr, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicLoad32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicLoad32 ptr mem) + // result: (MOVLatomicload ptr mem) + for { + ptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVLatomicload) + v.AddArg2(ptr, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicLoad64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicLoad64 ptr mem) + // result: (MOVQatomicload ptr mem) + for { + ptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVQatomicload) + v.AddArg2(ptr, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicLoad8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicLoad8 ptr mem) + // result: (MOVBatomicload ptr mem) + for { + ptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVBatomicload) + v.AddArg2(ptr, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicLoadPtr(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicLoadPtr ptr mem) + // result: (MOVQatomicload ptr mem) + for { + ptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVQatomicload) + v.AddArg2(ptr, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicOr32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicOr32 ptr val mem) + // result: (ORLlock ptr val mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64ORLlock) + v.AddArg3(ptr, val, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicOr32value(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicOr32value ptr val mem) + // result: (LoweredAtomicOr32 ptr val mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64LoweredAtomicOr32) + v.AddArg3(ptr, val, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicOr64value(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicOr64value ptr val mem) + // result: (LoweredAtomicOr64 ptr val mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64LoweredAtomicOr64) + v.AddArg3(ptr, val, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicOr8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (AtomicOr8 ptr val mem) + // result: (ORBlock ptr val mem) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpAMD64ORBlock) + v.AddArg3(ptr, val, mem) + return true + } +} +func rewriteValueAMD64_OpAtomicStore32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AtomicStore32 ptr val mem) + // result: (Select1 (XCHGL val ptr mem)) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) + v0.AddArg3(val, ptr, mem) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpAtomicStore64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AtomicStore64 ptr val mem) + // result: (Select1 (XCHGQ val ptr mem)) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) + v0.AddArg3(val, ptr, mem) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpAtomicStore8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AtomicStore8 ptr val mem) + // result: (Select1 (XCHGB val ptr mem)) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) + v0.AddArg3(val, ptr, mem) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AtomicStorePtrNoWB ptr val mem) + // result: (Select1 (XCHGQ val ptr mem)) + for { + ptr := v_0 + val := v_1 + mem := v_2 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) + v0.AddArg3(val, ptr, mem) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpBitLen16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen16 x) + // cond: buildcfg.GOAMD64 < 3 + // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) + for { + x := v_0 + if !(buildcfg.GOAMD64 < 3) { + break + } + v.reset(OpAMD64BSRL) + v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) + v0.AuxInt = int32ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) + v1.AddArg(x) + v0.AddArg2(v1, v1) + v.AddArg(v0) + return true + } + // match: (BitLen16 x) + // cond: buildcfg.GOAMD64 >= 3 + // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVWQZX x)))) + for { + t := v.Type + x := v_0 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64NEGQ) + v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) + v0.AuxInt = int32ToAuxInt(-32) + v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, x.Type) + v2.AddArg(x) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpBitLen32(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen32 x) + // cond: buildcfg.GOAMD64 < 3 + // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) + for { + x := v_0 + if !(buildcfg.GOAMD64 < 3) { + break + } + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) + v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) + v1.AuxInt = int32ToAuxInt(1) + v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) + v2.AddArg(x) + v1.AddArg2(v2, v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (BitLen32 x) + // cond: buildcfg.GOAMD64 >= 3 + // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) + for { + t := v.Type + x := v_0 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64NEGQ) + v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) + v0.AuxInt = int32ToAuxInt(-32) + v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpBitLen64(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen64 x) + // cond: buildcfg.GOAMD64 < 3 + // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) + for { + t := v.Type + x := v_0 + if !(buildcfg.GOAMD64 < 3) { + break + } + v.reset(OpAMD64ADDQconst) + v.AuxInt = int32ToAuxInt(1) + v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) + v1 := b.NewValue0(v.Pos, OpSelect0, t) + v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) + v2.AddArg(x) + v1.AddArg(v2) + v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) + v3.AuxInt = int64ToAuxInt(-1) + v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v4.AddArg(v2) + v0.AddArg3(v1, v3, v4) + v.AddArg(v0) + return true + } + // match: (BitLen64 x) + // cond: buildcfg.GOAMD64 >= 3 + // result: (NEGQ (ADDQconst [-64] (LZCNTQ x))) + for { + t := v.Type + x := v_0 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64NEGQ) + v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) + v0.AuxInt = int32ToAuxInt(-64) + v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpBitLen8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen8 x) + // cond: buildcfg.GOAMD64 < 3 + // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) + for { + x := v_0 + if !(buildcfg.GOAMD64 < 3) { + break + } + v.reset(OpAMD64BSRL) + v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) + v0.AuxInt = int32ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) + v1.AddArg(x) + v0.AddArg2(v1, v1) + v.AddArg(v0) + return true + } + // match: (BitLen8 x) + // cond: buildcfg.GOAMD64 >= 3 + // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVBQZX x)))) + for { + t := v.Type + x := v_0 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64NEGQ) + v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) + v0.AuxInt = int32ToAuxInt(-32) + v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, x.Type) + v2.AddArg(x) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpBswap16(v *Value) bool { + v_0 := v.Args[0] + // match: (Bswap16 x) + // result: (ROLWconst [8] x) + for { + x := v_0 + v.reset(OpAMD64ROLWconst) + v.AuxInt = int8ToAuxInt(8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeil(v *Value) bool { + v_0 := v.Args[0] + // match: (Ceil x) + // result: (ROUNDSD [2] x) + for { + x := v_0 + v.reset(OpAMD64ROUNDSD) + v.AuxInt = int8ToAuxInt(2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilFloat32x4 x) + // result: (VROUNDPS128 [2] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS128) + v.AuxInt = uint8ToAuxInt(2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilFloat32x8 x) + // result: (VROUNDPS256 [2] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS256) + v.AuxInt = uint8ToAuxInt(2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilFloat64x2 x) + // result: (VROUNDPD128 [2] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD128) + v.AuxInt = uint8ToAuxInt(2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilFloat64x4 x) + // result: (VROUNDPD256 [2] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD256) + v.AuxInt = uint8ToAuxInt(2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledResidueFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledResidueFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledResidueFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledResidueFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledResidueFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledResidueFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledResidueFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledResidueFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledResidueFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledResidueFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilScaledResidueFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilScaledResidueFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+2] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = uint8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCompressFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressFloat32x16 x mask) + // result: (VCOMPRESSPSMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VCOMPRESSPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressFloat32x4 x mask) + // result: (VCOMPRESSPSMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VCOMPRESSPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressFloat32x8 x mask) + // result: (VCOMPRESSPSMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VCOMPRESSPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressFloat64x2 x mask) + // result: (VCOMPRESSPDMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VCOMPRESSPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressFloat64x4 x mask) + // result: (VCOMPRESSPDMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VCOMPRESSPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressFloat64x8 x mask) + // result: (VCOMPRESSPDMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VCOMPRESSPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt16x16 x mask) + // result: (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt16x32 x mask) + // result: (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt16x8 x mask) + // result: (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt32x16 x mask) + // result: (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt32x4 x mask) + // result: (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt32x8 x mask) + // result: (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt64x2 x mask) + // result: (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt64x4 x mask) + // result: (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt64x8 x mask) + // result: (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt8x16 x mask) + // result: (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt8x32 x mask) + // result: (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressInt8x64 x mask) + // result: (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint16x16 x mask) + // result: (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint16x32 x mask) + // result: (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint16x8 x mask) + // result: (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint32x16 x mask) + // result: (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint32x4 x mask) + // result: (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint32x8 x mask) + // result: (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint64x2 x mask) + // result: (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint64x4 x mask) + // result: (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint64x8 x mask) + // result: (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint8x16 x mask) + // result: (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint8x32 x mask) + // result: (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCompressUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CompressUint8x64 x mask) + // result: (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPCOMPRESSBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpCondSelect(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CondSelect x y (SETEQ cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQEQ y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETEQ { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQEQ) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETNE cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQNE y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETNE { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQNE) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETL cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQLT y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETL { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQLT) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETG cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQGT y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETG { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQGT) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETLE cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQLE y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETLE { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQLE) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETGE cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQGE y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETGE { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQGE) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETA cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQHI y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETA { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQHI) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETB cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQCS y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETB { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQCS) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETAE cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQCC y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETAE { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQCC) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETBE cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQLS y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETBE { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQLS) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETEQF cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQEQF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETEQF { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQEQF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETNEF cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQNEF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETNEF { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQNEF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETGF cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQGTF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETGF { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQGTF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETGEF cond)) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (CMOVQGEF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETGEF { + break + } + cond := v_2.Args[0] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64CMOVQGEF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETEQ cond)) + // cond: is32BitInt(t) + // result: (CMOVLEQ y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETEQ { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLEQ) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETNE cond)) + // cond: is32BitInt(t) + // result: (CMOVLNE y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETNE { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLNE) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETL cond)) + // cond: is32BitInt(t) + // result: (CMOVLLT y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETL { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLLT) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETG cond)) + // cond: is32BitInt(t) + // result: (CMOVLGT y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETG { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLGT) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETLE cond)) + // cond: is32BitInt(t) + // result: (CMOVLLE y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETLE { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLLE) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETGE cond)) + // cond: is32BitInt(t) + // result: (CMOVLGE y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETGE { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLGE) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETA cond)) + // cond: is32BitInt(t) + // result: (CMOVLHI y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETA { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLHI) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETB cond)) + // cond: is32BitInt(t) + // result: (CMOVLCS y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETB { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLCS) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETAE cond)) + // cond: is32BitInt(t) + // result: (CMOVLCC y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETAE { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLCC) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETBE cond)) + // cond: is32BitInt(t) + // result: (CMOVLLS y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETBE { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLLS) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETEQF cond)) + // cond: is32BitInt(t) + // result: (CMOVLEQF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETEQF { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLEQF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETNEF cond)) + // cond: is32BitInt(t) + // result: (CMOVLNEF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETNEF { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLNEF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETGF cond)) + // cond: is32BitInt(t) + // result: (CMOVLGTF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETGF { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLGTF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETGEF cond)) + // cond: is32BitInt(t) + // result: (CMOVLGEF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETGEF { + break + } + cond := v_2.Args[0] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLGEF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETEQ cond)) + // cond: is16BitInt(t) + // result: (CMOVWEQ y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETEQ { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWEQ) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETNE cond)) + // cond: is16BitInt(t) + // result: (CMOVWNE y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETNE { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWNE) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETL cond)) + // cond: is16BitInt(t) + // result: (CMOVWLT y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETL { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWLT) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETG cond)) + // cond: is16BitInt(t) + // result: (CMOVWGT y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETG { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWGT) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETLE cond)) + // cond: is16BitInt(t) + // result: (CMOVWLE y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETLE { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWLE) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETGE cond)) + // cond: is16BitInt(t) + // result: (CMOVWGE y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETGE { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWGE) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETA cond)) + // cond: is16BitInt(t) + // result: (CMOVWHI y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETA { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWHI) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETB cond)) + // cond: is16BitInt(t) + // result: (CMOVWCS y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETB { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWCS) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETAE cond)) + // cond: is16BitInt(t) + // result: (CMOVWCC y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETAE { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWCC) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETBE cond)) + // cond: is16BitInt(t) + // result: (CMOVWLS y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETBE { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWLS) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETEQF cond)) + // cond: is16BitInt(t) + // result: (CMOVWEQF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETEQF { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWEQF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETNEF cond)) + // cond: is16BitInt(t) + // result: (CMOVWNEF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETNEF { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWNEF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETGF cond)) + // cond: is16BitInt(t) + // result: (CMOVWGTF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETGF { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWGTF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y (SETGEF cond)) + // cond: is16BitInt(t) + // result: (CMOVWGEF y x cond) + for { + t := v.Type + x := v_0 + y := v_1 + if v_2.Op != OpAMD64SETGEF { + break + } + cond := v_2.Args[0] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWGEF) + v.AddArg3(y, x, cond) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) + // result: (CMOVQNE y x (CMPQconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { + break + } + v.reset(OpAMD64CMOVQNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) + // result: (CMOVLNE y x (CMPQconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) + // result: (CMOVWNE y x (CMPQconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 4 && (is64BitInt(t) || isPtr(t)) + // result: (CMOVQNE y x (CMPLconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 4 && (is64BitInt(t) || isPtr(t))) { + break + } + v.reset(OpAMD64CMOVQNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 4 && is32BitInt(t) + // result: (CMOVLNE y x (CMPLconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 4 && is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 4 && is16BitInt(t) + // result: (CMOVWNE y x (CMPLconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 4 && is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 2 && (is64BitInt(t) || isPtr(t)) + // result: (CMOVQNE y x (CMPWconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 2 && (is64BitInt(t) || isPtr(t))) { + break + } + v.reset(OpAMD64CMOVQNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v0.AuxInt = int16ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 2 && is32BitInt(t) + // result: (CMOVLNE y x (CMPWconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 2 && is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v0.AuxInt = int16ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 2 && is16BitInt(t) + // result: (CMOVWNE y x (CMPWconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 2 && is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v0.AuxInt = int16ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 1 && (is64BitInt(t) || isPtr(t)) + // result: (CMOVQNE y x (CMPBconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 1 && (is64BitInt(t) || isPtr(t))) { + break + } + v.reset(OpAMD64CMOVQNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 1 && is32BitInt(t) + // result: (CMOVLNE y x (CMPBconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 1 && is32BitInt(t)) { + break + } + v.reset(OpAMD64CMOVLNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + // match: (CondSelect x y check) + // cond: !check.Type.IsFlags() && check.Type.Size() == 1 && is16BitInt(t) + // result: (CMOVWNE y x (CMPBconst [0] check)) + for { + t := v.Type + x := v_0 + y := v_1 + check := v_2 + if !(!check.Type.IsFlags() && check.Type.Size() == 1 && is16BitInt(t)) { + break + } + v.reset(OpAMD64CMOVWNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(check) + v.AddArg3(y, x, v0) + return true + } + return false +} +func rewriteValueAMD64_OpConst16(v *Value) bool { + // match: (Const16 [c]) + // result: (MOVLconst [int32(c)]) + for { + c := auxIntToInt16(v.AuxInt) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(int32(c)) + return true + } +} +func rewriteValueAMD64_OpConst8(v *Value) bool { + // match: (Const8 [c]) + // result: (MOVLconst [int32(c)]) + for { + c := auxIntToInt8(v.AuxInt) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(int32(c)) + return true + } +} +func rewriteValueAMD64_OpConstBool(v *Value) bool { + // match: (ConstBool [c]) + // result: (MOVLconst [b2i32(c)]) + for { + c := auxIntToBool(v.AuxInt) + v.reset(OpAMD64MOVLconst) + v.AuxInt = int32ToAuxInt(b2i32(c)) + return true + } +} +func rewriteValueAMD64_OpConstNil(v *Value) bool { + // match: (ConstNil ) + // result: (MOVQconst [0]) + for { + v.reset(OpAMD64MOVQconst) + v.AuxInt = int64ToAuxInt(0) + return true + } +} +func rewriteValueAMD64_OpCtz16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Ctz16 x) + // result: (BSFL (ORLconst [1<<16] x)) + for { + x := v_0 + v.reset(OpAMD64BSFL) + v0 := b.NewValue0(v.Pos, OpAMD64ORLconst, typ.UInt32) + v0.AuxInt = int32ToAuxInt(1 << 16) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool { + v_0 := v.Args[0] + // match: (Ctz16NonZero x) + // cond: buildcfg.GOAMD64 >= 3 + // result: (TZCNTL x) + for { + x := v_0 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64TZCNTL) + v.AddArg(x) + return true + } + // match: (Ctz16NonZero x) + // cond: buildcfg.GOAMD64 < 3 + // result: (BSFL x) + for { + x := v_0 + if !(buildcfg.GOAMD64 < 3) { + break + } + v.reset(OpAMD64BSFL) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCtz32(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Ctz32 x) + // cond: buildcfg.GOAMD64 >= 3 + // result: (TZCNTL x) + for { + x := v_0 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64TZCNTL) + v.AddArg(x) + return true + } + // match: (Ctz32 x) + // cond: buildcfg.GOAMD64 < 3 + // result: (Select0 (BSFQ (BTSQconst [32] x))) + for { + x := v_0 + if !(buildcfg.GOAMD64 < 3) { + break + } + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) + v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) + v1.AuxInt = int8ToAuxInt(32) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool { + v_0 := v.Args[0] + // match: (Ctz32NonZero x) + // cond: buildcfg.GOAMD64 >= 3 + // result: (TZCNTL x) + for { + x := v_0 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64TZCNTL) + v.AddArg(x) + return true + } + // match: (Ctz32NonZero x) + // cond: buildcfg.GOAMD64 < 3 + // result: (BSFL x) + for { + x := v_0 + if !(buildcfg.GOAMD64 < 3) { + break + } + v.reset(OpAMD64BSFL) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCtz64(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Ctz64 x) + // cond: buildcfg.GOAMD64 >= 3 + // result: (TZCNTQ x) + for { + x := v_0 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64TZCNTQ) + v.AddArg(x) + return true + } + // match: (Ctz64 x) + // cond: buildcfg.GOAMD64 < 3 + // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) + for { + t := v.Type + x := v_0 + if !(buildcfg.GOAMD64 < 3) { + break + } + v.reset(OpAMD64CMOVQEQ) + v0 := b.NewValue0(v.Pos, OpSelect0, t) + v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) + v2.AuxInt = int64ToAuxInt(64) + v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v3.AddArg(v1) + v.AddArg3(v0, v2, v3) + return true + } + return false +} +func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Ctz64NonZero x) + // cond: buildcfg.GOAMD64 >= 3 + // result: (TZCNTQ x) + for { + x := v_0 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64TZCNTQ) + v.AddArg(x) + return true + } + // match: (Ctz64NonZero x) + // cond: buildcfg.GOAMD64 < 3 + // result: (Select0 (BSFQ x)) + for { + x := v_0 + if !(buildcfg.GOAMD64 < 3) { + break + } + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) + v0.AddArg(x) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpCtz8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Ctz8 x) + // result: (BSFL (ORLconst [1<<8 ] x)) + for { + x := v_0 + v.reset(OpAMD64BSFL) + v0 := b.NewValue0(v.Pos, OpAMD64ORLconst, typ.UInt32) + v0.AuxInt = int32ToAuxInt(1 << 8) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { + v_0 := v.Args[0] + // match: (Ctz8NonZero x) + // cond: buildcfg.GOAMD64 >= 3 + // result: (TZCNTL x) + for { + x := v_0 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64TZCNTL) + v.AddArg(x) + return true + } + // match: (Ctz8NonZero x) + // cond: buildcfg.GOAMD64 < 3 + // result: (BSFL x) + for { + x := v_0 + if !(buildcfg.GOAMD64 < 3) { + break + } + v.reset(OpAMD64BSFL) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt16toMask16x16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt16toMask16x16 x) + // result: (VPMOVMToVec16x16 (KMOVWk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec16x16) + v.Type = types.TypeVec256 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVWk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt16toMask32x16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt16toMask32x16 x) + // result: (VPMOVMToVec32x16 (KMOVWk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec32x16) + v.Type = types.TypeVec512 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVWk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt16toMask8x16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt16toMask8x16 x) + // result: (VPMOVMToVec8x16 (KMOVWk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec8x16) + v.Type = types.TypeVec128 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVWk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt32Fto32(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Cvt32Fto32 x) + // cond: base.ConvertHash.MatchPos(v.Pos, nil) + // result: (XORL y (SARLconst [31] (ANDL y:(CVTTSS2SL x) (NOTL (MOVLf2i x))))) + for { + t := v.Type + x := v_0 + if !(base.ConvertHash.MatchPos(v.Pos, nil)) { + break + } + v.reset(OpAMD64XORL) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64SARLconst, t) + v0.AuxInt = int8ToAuxInt(31) + v1 := b.NewValue0(v.Pos, OpAMD64ANDL, t) + y := b.NewValue0(v.Pos, OpAMD64CVTTSS2SL, t) + y.AddArg(x) + v3 := b.NewValue0(v.Pos, OpAMD64NOTL, typ.Int32) + v4 := b.NewValue0(v.Pos, OpAMD64MOVLf2i, typ.UInt32) + v4.AddArg(x) + v3.AddArg(v4) + v1.AddArg2(y, v3) + v0.AddArg(v1) + v.AddArg2(y, v0) + return true + } + // match: (Cvt32Fto32 x) + // cond: !base.ConvertHash.MatchPos(v.Pos, nil) + // result: (CVTTSS2SL x) + for { + t := v.Type + x := v_0 + if !(!base.ConvertHash.MatchPos(v.Pos, nil)) { + break + } + v.reset(OpAMD64CVTTSS2SL) + v.Type = t + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt32Fto64(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Cvt32Fto64 x) + // cond: base.ConvertHash.MatchPos(v.Pos, nil) + // result: (XORQ y (SARQconst [63] (ANDQ y:(CVTTSS2SQ x) (NOTQ (MOVQf2i (CVTSS2SD x))) ))) + for { + t := v.Type + x := v_0 + if !(base.ConvertHash.MatchPos(v.Pos, nil)) { + break + } + v.reset(OpAMD64XORQ) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64SARQconst, t) + v0.AuxInt = int8ToAuxInt(63) + v1 := b.NewValue0(v.Pos, OpAMD64ANDQ, t) + y := b.NewValue0(v.Pos, OpAMD64CVTTSS2SQ, t) + y.AddArg(x) + v3 := b.NewValue0(v.Pos, OpAMD64NOTQ, typ.Int64) + v4 := b.NewValue0(v.Pos, OpAMD64MOVQf2i, typ.UInt64) + v5 := b.NewValue0(v.Pos, OpAMD64CVTSS2SD, typ.Float64) + v5.AddArg(x) + v4.AddArg(v5) + v3.AddArg(v4) + v1.AddArg2(y, v3) + v0.AddArg(v1) + v.AddArg2(y, v0) + return true + } + // match: (Cvt32Fto64 x) + // cond: !base.ConvertHash.MatchPos(v.Pos, nil) + // result: (CVTTSS2SQ x) + for { + t := v.Type + x := v_0 + if !(!base.ConvertHash.MatchPos(v.Pos, nil)) { + break + } + v.reset(OpAMD64CVTTSS2SQ) + v.Type = t + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt32toMask16x32(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt32toMask16x32 x) + // result: (VPMOVMToVec16x32 (KMOVDk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec16x32) + v.Type = types.TypeVec512 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVDk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt32toMask8x32(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt32toMask8x32 x) + // result: (VPMOVMToVec8x32 (KMOVDk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec8x32) + v.Type = types.TypeVec256 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVDk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt64Fto32(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Cvt64Fto32 x) + // cond: base.ConvertHash.MatchPos(v.Pos, nil) + // result: (XORL y (SARLconst [31] (ANDL y:(CVTTSD2SL x) (NOTL (MOVLf2i (CVTSD2SS x)))))) + for { + t := v.Type + x := v_0 + if !(base.ConvertHash.MatchPos(v.Pos, nil)) { + break + } + v.reset(OpAMD64XORL) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64SARLconst, t) + v0.AuxInt = int8ToAuxInt(31) + v1 := b.NewValue0(v.Pos, OpAMD64ANDL, t) + y := b.NewValue0(v.Pos, OpAMD64CVTTSD2SL, t) + y.AddArg(x) + v3 := b.NewValue0(v.Pos, OpAMD64NOTL, typ.Int32) + v4 := b.NewValue0(v.Pos, OpAMD64MOVLf2i, typ.UInt32) + v5 := b.NewValue0(v.Pos, OpAMD64CVTSD2SS, typ.Float32) + v5.AddArg(x) + v4.AddArg(v5) + v3.AddArg(v4) + v1.AddArg2(y, v3) + v0.AddArg(v1) + v.AddArg2(y, v0) + return true + } + // match: (Cvt64Fto32 x) + // cond: !base.ConvertHash.MatchPos(v.Pos, nil) + // result: (CVTTSD2SL x) + for { + t := v.Type + x := v_0 + if !(!base.ConvertHash.MatchPos(v.Pos, nil)) { + break + } + v.reset(OpAMD64CVTTSD2SL) + v.Type = t + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt64Fto64(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Cvt64Fto64 x) + // cond: base.ConvertHash.MatchPos(v.Pos, nil) + // result: (XORQ y (SARQconst [63] (ANDQ y:(CVTTSD2SQ x) (NOTQ (MOVQf2i x))))) + for { + t := v.Type + x := v_0 + if !(base.ConvertHash.MatchPos(v.Pos, nil)) { + break + } + v.reset(OpAMD64XORQ) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64SARQconst, t) + v0.AuxInt = int8ToAuxInt(63) + v1 := b.NewValue0(v.Pos, OpAMD64ANDQ, t) + y := b.NewValue0(v.Pos, OpAMD64CVTTSD2SQ, t) + y.AddArg(x) + v3 := b.NewValue0(v.Pos, OpAMD64NOTQ, typ.Int64) + v4 := b.NewValue0(v.Pos, OpAMD64MOVQf2i, typ.UInt64) + v4.AddArg(x) + v3.AddArg(v4) + v1.AddArg2(y, v3) + v0.AddArg(v1) + v.AddArg2(y, v0) + return true + } + // match: (Cvt64Fto64 x) + // cond: !base.ConvertHash.MatchPos(v.Pos, nil) + // result: (CVTTSD2SQ x) + for { + t := v.Type + x := v_0 + if !(!base.ConvertHash.MatchPos(v.Pos, nil)) { + break + } + v.reset(OpAMD64CVTTSD2SQ) + v.Type = t + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt64toMask8x64(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt64toMask8x64 x) + // result: (VPMOVMToVec8x64 (KMOVQk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec8x64) + v.Type = types.TypeVec512 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVQk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt8toMask16x8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt8toMask16x8 x) + // result: (VPMOVMToVec16x8 (KMOVBk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec16x8) + v.Type = types.TypeVec128 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt8toMask32x4(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt8toMask32x4 x) + // result: (VPMOVMToVec32x4 (KMOVBk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec32x4) + v.Type = types.TypeVec128 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt8toMask32x8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt8toMask32x8 x) + // result: (VPMOVMToVec32x8 (KMOVBk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec32x8) + v.Type = types.TypeVec256 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt8toMask64x2(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt8toMask64x2 x) + // result: (VPMOVMToVec64x2 (KMOVBk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec64x2) + v.Type = types.TypeVec128 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt8toMask64x4(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt8toMask64x4 x) + // result: (VPMOVMToVec64x4 (KMOVBk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec64x4) + v.Type = types.TypeVec256 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvt8toMask64x8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Cvt8toMask64x8 x) + // result: (VPMOVMToVec64x8 (KMOVBk x)) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64VPMOVMToVec64x8) + v.Type = types.TypeVec512 + v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvtMask16x16to16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (CvtMask16x16to16 x) + // result: (KMOVWi (VPMOVVec16x16ToM x)) + for { + x := v_0 + v.reset(OpAMD64KMOVWi) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvtMask16x32to32(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (CvtMask16x32to32 x) + // result: (KMOVDi (VPMOVVec16x32ToM x)) + for { + x := v_0 + v.reset(OpAMD64KMOVDi) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvtMask16x8to8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (CvtMask16x8to8 x) + // result: (KMOVBi (VPMOVVec16x8ToM x)) + for { + x := v_0 + v.reset(OpAMD64KMOVBi) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvtMask32x16to16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (CvtMask32x16to16 x) + // result: (KMOVWi (VPMOVVec32x16ToM x)) + for { + x := v_0 + v.reset(OpAMD64KMOVWi) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvtMask64x8to8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (CvtMask64x8to8 x) + // result: (KMOVBi (VPMOVVec64x8ToM x)) + for { + x := v_0 + v.reset(OpAMD64KMOVBi) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpCvtMask8x64to64(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (CvtMask8x64to64 x) + // result: (KMOVQi (VPMOVVec8x64ToM x)) + for { + x := v_0 + v.reset(OpAMD64KMOVQi) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpDiv16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div16 [a] x y) + // result: (Select0 (DIVW [a] x y)) + for { + a := auxIntToBool(v.AuxInt) + x := v_0 + y := v_1 + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) + v0.AuxInt = boolToAuxInt(a) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpDiv16u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div16u x y) + // result: (Select0 (DIVWU x y)) + for { + x := v_0 + y := v_1 + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpDiv32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div32 [a] x y) + // result: (Select0 (DIVL [a] x y)) + for { + a := auxIntToBool(v.AuxInt) + x := v_0 + y := v_1 + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) + v0.AuxInt = boolToAuxInt(a) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpDiv32u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div32u x y) + // result: (Select0 (DIVLU x y)) + for { + x := v_0 + y := v_1 + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpDiv64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div64 [a] x y) + // result: (Select0 (DIVQ [a] x y)) + for { + a := auxIntToBool(v.AuxInt) + x := v_0 + y := v_1 + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) + v0.AuxInt = boolToAuxInt(a) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpDiv64u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div64u x y) + // result: (Select0 (DIVQU x y)) + for { + x := v_0 + y := v_1 + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpDiv8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div8 x y) + // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) + for { + x := v_0 + y := v_1 + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) + v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpDiv8u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div8u x y) + // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) + for { + x := v_0 + y := v_1 + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) + v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEq16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq16 x y) + // result: (SETEQ (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEq32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq32 x y) + // result: (SETEQ (CMPL x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEq32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq32F x y) + // result: (SETEQF (UCOMISS x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETEQF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEq64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq64 x y) + // result: (SETEQ (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEq64F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq64F x y) + // result: (SETEQF (UCOMISD x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETEQF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEq8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq8 x y) + // result: (SETEQ (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqB(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (EqB x y) + // result: (SETEQ (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqPtr(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (EqPtr x y) + // result: (SETEQ (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqualFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [0] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(0) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqualFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (EqualFloat32x4 x y) + // result: (VCMPPS128 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpEqualFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (EqualFloat32x8 x y) + // result: (VCMPPS256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpEqualFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (EqualFloat64x2 x y) + // result: (VCMPPD128 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpEqualFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (EqualFloat64x4 x y) + // result: (VCMPPD256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpEqualFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [0] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(0) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqualInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPEQW512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQW512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqualInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPEQD512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQD512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqualInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPEQQ512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQQ512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqualInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPEQB512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQB512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqualUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPEQW512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQW512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqualUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPEQD512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQD512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqualUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPEQQ512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQQ512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpEqualUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPEQB512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQB512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpExpandFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandFloat32x16 x mask) + // result: (VEXPANDPSMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VEXPANDPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandFloat32x4 x mask) + // result: (VEXPANDPSMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VEXPANDPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandFloat32x8 x mask) + // result: (VEXPANDPSMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VEXPANDPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandFloat64x2 x mask) + // result: (VEXPANDPDMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VEXPANDPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandFloat64x4 x mask) + // result: (VEXPANDPDMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VEXPANDPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandFloat64x8 x mask) + // result: (VEXPANDPDMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VEXPANDPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt16x16 x mask) + // result: (VPEXPANDWMasked256 x (VPMOVVec16x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt16x32 x mask) + // result: (VPEXPANDWMasked512 x (VPMOVVec16x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt16x8 x mask) + // result: (VPEXPANDWMasked128 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt32x16 x mask) + // result: (VPEXPANDDMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt32x4 x mask) + // result: (VPEXPANDDMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt32x8 x mask) + // result: (VPEXPANDDMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt64x2 x mask) + // result: (VPEXPANDQMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt64x4 x mask) + // result: (VPEXPANDQMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt64x8 x mask) + // result: (VPEXPANDQMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt8x16 x mask) + // result: (VPEXPANDBMasked128 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt8x32 x mask) + // result: (VPEXPANDBMasked256 x (VPMOVVec8x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandInt8x64 x mask) + // result: (VPEXPANDBMasked512 x (VPMOVVec8x64ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint16x16 x mask) + // result: (VPEXPANDWMasked256 x (VPMOVVec16x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint16x32 x mask) + // result: (VPEXPANDWMasked512 x (VPMOVVec16x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint16x8 x mask) + // result: (VPEXPANDWMasked128 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint32x16 x mask) + // result: (VPEXPANDDMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint32x4 x mask) + // result: (VPEXPANDDMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint32x8 x mask) + // result: (VPEXPANDDMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint64x2 x mask) + // result: (VPEXPANDQMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint64x4 x mask) + // result: (VPEXPANDQMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint64x8 x mask) + // result: (VPEXPANDQMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint8x16 x mask) + // result: (VPEXPANDBMasked128 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint8x32 x mask) + // result: (VPEXPANDBMasked256 x (VPMOVVec8x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpExpandUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (ExpandUint8x64 x mask) + // result: (VPEXPANDBMasked512 x (VPMOVVec8x64ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPEXPANDBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpFMA(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (FMA x y z) + // result: (VFMADD231SD z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.reset(OpAMD64VFMADD231SD) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValueAMD64_OpFloor(v *Value) bool { + v_0 := v.Args[0] + // match: (Floor x) + // result: (ROUNDSD [1] x) + for { + x := v_0 + v.reset(OpAMD64ROUNDSD) + v.AuxInt = int8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorFloat32x4 x) + // result: (VROUNDPS128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorFloat32x8 x) + // result: (VROUNDPS256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorFloat64x2 x) + // result: (VROUNDPD128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorFloat64x4 x) + // result: (VROUNDPD256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledResidueFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledResidueFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledResidueFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledResidueFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledResidueFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledResidueFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledResidueFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledResidueFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledResidueFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledResidueFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorScaledResidueFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorScaledResidueFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+1] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = uint8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetG(v *Value) bool { + v_0 := v.Args[0] + // match: (GetG mem) + // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal + // result: (LoweredGetG mem) + for { + mem := v_0 + if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { + break + } + v.reset(OpAMD64LoweredGetG) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpGetHiFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiFloat32x16 x) + // result: (VEXTRACTF64X4256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTF64X4256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiFloat32x8 x) + // result: (VEXTRACTF128128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTF128128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiFloat64x4 x) + // result: (VEXTRACTF128128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTF128128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiFloat64x8 x) + // result: (VEXTRACTF64X4256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTF64X4256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiInt16x16(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiInt16x16 x) + // result: (VEXTRACTI128128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiInt16x32(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiInt16x32 x) + // result: (VEXTRACTI64X4256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiInt32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiInt32x16 x) + // result: (VEXTRACTI64X4256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiInt32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiInt32x8 x) + // result: (VEXTRACTI128128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiInt64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiInt64x4 x) + // result: (VEXTRACTI128128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiInt64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiInt64x8 x) + // result: (VEXTRACTI64X4256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiInt8x32(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiInt8x32 x) + // result: (VEXTRACTI128128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiInt8x64(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiInt8x64 x) + // result: (VEXTRACTI64X4256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiUint16x16(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiUint16x16 x) + // result: (VEXTRACTI128128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiUint16x32(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiUint16x32 x) + // result: (VEXTRACTI64X4256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiUint32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiUint32x16 x) + // result: (VEXTRACTI64X4256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiUint32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiUint32x8 x) + // result: (VEXTRACTI128128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiUint64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiUint64x4 x) + // result: (VEXTRACTI128128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiUint64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiUint64x8 x) + // result: (VEXTRACTI64X4256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiUint8x32(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiUint8x32 x) + // result: (VEXTRACTI128128 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetHiUint8x64(v *Value) bool { + v_0 := v.Args[0] + // match: (GetHiUint8x64 x) + // result: (VEXTRACTI64X4256 [1] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoFloat32x16 x) + // result: (VEXTRACTF64X4256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTF64X4256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoFloat32x8 x) + // result: (VEXTRACTF128128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTF128128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoFloat64x4 x) + // result: (VEXTRACTF128128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTF128128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoFloat64x8 x) + // result: (VEXTRACTF64X4256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTF64X4256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoInt16x16(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoInt16x16 x) + // result: (VEXTRACTI128128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoInt16x32(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoInt16x32 x) + // result: (VEXTRACTI64X4256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoInt32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoInt32x16 x) + // result: (VEXTRACTI64X4256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoInt32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoInt32x8 x) + // result: (VEXTRACTI128128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoInt64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoInt64x4 x) + // result: (VEXTRACTI128128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoInt64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoInt64x8 x) + // result: (VEXTRACTI64X4256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoInt8x32(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoInt8x32 x) + // result: (VEXTRACTI128128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoInt8x64(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoInt8x64 x) + // result: (VEXTRACTI64X4256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoUint16x16(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoUint16x16 x) + // result: (VEXTRACTI128128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoUint16x32(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoUint16x32 x) + // result: (VEXTRACTI64X4256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoUint32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoUint32x16 x) + // result: (VEXTRACTI64X4256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoUint32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoUint32x8 x) + // result: (VEXTRACTI128128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoUint64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoUint64x4 x) + // result: (VEXTRACTI128128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoUint64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoUint64x8 x) + // result: (VEXTRACTI64X4256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoUint8x32(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoUint8x32 x) + // result: (VEXTRACTI128128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI128128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetLoUint8x64(v *Value) bool { + v_0 := v.Args[0] + // match: (GetLoUint8x64 x) + // result: (VEXTRACTI64X4256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VEXTRACTI64X4256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [13] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(13) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterEqualFloat32x4 x y) + // result: (VCMPPS128 [13] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = uint8ToAuxInt(13) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterEqualFloat32x8 x y) + // result: (VCMPPS256 [13] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = uint8ToAuxInt(13) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterEqualFloat64x2 x y) + // result: (VCMPPD128 [13] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = uint8ToAuxInt(13) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterEqualFloat64x4 x y) + // result: (VCMPPD256 [13] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = uint8ToAuxInt(13) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [13] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(13) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPW512 [13] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(13) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPD512 [13] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(13) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPQ512 [13] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(13) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPB512 [13] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(13) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [13] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(13) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [13] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(13) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [13] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(13) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [13] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(13) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [14] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(14) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterFloat32x4 x y) + // result: (VCMPPS128 [14] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = uint8ToAuxInt(14) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterFloat32x8 x y) + // result: (VCMPPS256 [14] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = uint8ToAuxInt(14) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterFloat64x2 x y) + // result: (VCMPPD128 [14] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = uint8ToAuxInt(14) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterFloat64x4 x y) + // result: (VCMPPD256 [14] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = uint8ToAuxInt(14) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [14] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(14) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPGTW512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTW512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPGTD512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTD512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPGTQ512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTQ512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPGTB512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTB512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [14] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(14) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [14] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(14) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [14] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(14) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [14] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(14) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (HasCPUFeature {s}) + // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) + for { + s := auxToSym(v.Aux) + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) + v1.Aux = symToAux(s) + v0.AddArg(v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsInBounds(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (IsInBounds idx len) + // result: (SETB (CMPQ idx len)) + for { + idx := v_0 + len := v_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(idx, len) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsNaNFloat32x16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (IsNaNFloat32x16 x) + // result: (VPMOVMToVec32x16 (VCMPPS512 [3] x x)) + for { + x := v_0 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(3) + v0.AddArg2(x, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsNaNFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (IsNaNFloat32x4 x) + // result: (VCMPPS128 [3] x x) + for { + x := v_0 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg2(x, x) + return true + } +} +func rewriteValueAMD64_OpIsNaNFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (IsNaNFloat32x8 x) + // result: (VCMPPS256 [3] x x) + for { + x := v_0 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg2(x, x) + return true + } +} +func rewriteValueAMD64_OpIsNaNFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (IsNaNFloat64x2 x) + // result: (VCMPPD128 [3] x x) + for { + x := v_0 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg2(x, x) + return true + } +} +func rewriteValueAMD64_OpIsNaNFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (IsNaNFloat64x4 x) + // result: (VCMPPD256 [3] x x) + for { + x := v_0 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg2(x, x) + return true + } +} +func rewriteValueAMD64_OpIsNaNFloat64x8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (IsNaNFloat64x8 x) + // result: (VPMOVMToVec64x8 (VCMPPD512 [3] x x)) + for { + x := v_0 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(3) + v0.AddArg2(x, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsNonNil(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (IsNonNil p) + // result: (SETNE (TESTQ p p)) + for { + p := v_0 + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) + v0.AddArg2(p, p) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (IsSliceInBounds idx len) + // result: (SETBE (CMPQ idx len)) + for { + idx := v_0 + len := v_1 + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(idx, len) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsZeroVec(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (IsZeroVec x) + // result: (SETEQ (VPTEST x x)) + for { + x := v_0 + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(x, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq16 x y) + // result: (SETLE (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq16U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq16U x y) + // result: (SETBE (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq32 x y) + // result: (SETLE (CMPL x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq32F x y) + // result: (SETGEF (UCOMISS y x)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETGEF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq32U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq32U x y) + // result: (SETBE (CMPL x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq64 x y) + // result: (SETLE (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq64F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq64F x y) + // result: (SETGEF (UCOMISD y x)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETGEF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq64U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq64U x y) + // result: (SETBE (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq8 x y) + // result: (SETLE (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq8U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq8U x y) + // result: (SETBE (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less16 x y) + // result: (SETL (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess16U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less16U x y) + // result: (SETB (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less32 x y) + // result: (SETL (CMPL x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less32F x y) + // result: (SETGF (UCOMISS y x)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETGF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess32U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less32U x y) + // result: (SETB (CMPL x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less64 x y) + // result: (SETL (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess64F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less64F x y) + // result: (SETGF (UCOMISD y x)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETGF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess64U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less64U x y) + // result: (SETB (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less8 x y) + // result: (SETL (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess8U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less8U x y) + // result: (SETB (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessEqualFloat32x4 x y) + // result: (VCMPPS128 [2] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = uint8ToAuxInt(2) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessEqualFloat32x8 x y) + // result: (VCMPPS256 [2] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = uint8ToAuxInt(2) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessEqualFloat64x2 x y) + // result: (VCMPPD128 [2] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = uint8ToAuxInt(2) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessEqualFloat64x4 x y) + // result: (VCMPPD256 [2] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = uint8ToAuxInt(2) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPW512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPD512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPQ512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPB512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessFloat32x4 x y) + // result: (VCMPPS128 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessFloat32x8 x y) + // result: (VCMPPS256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessFloat64x2 x y) + // result: (VCMPPD128 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessFloat64x4 x y) + // result: (VCMPPD256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPW512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPD512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPQ512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPB512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLoad(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (Load ptr mem) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (MOVQload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64MOVQload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: is32BitInt(t) + // result: (MOVLload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64MOVLload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: is16BitInt(t) + // result: (MOVWload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64MOVWload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: (t.IsBoolean() || is8BitInt(t)) + // result: (MOVBload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(t.IsBoolean() || is8BitInt(t)) { + break + } + v.reset(OpAMD64MOVBload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: is32BitFloat(t) + // result: (MOVSSload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is32BitFloat(t)) { + break + } + v.reset(OpAMD64MOVSSload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: is64BitFloat(t) + // result: (MOVSDload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is64BitFloat(t)) { + break + } + v.reset(OpAMD64MOVSDload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: t.Size() == 16 + // result: (VMOVDQUload128 ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(t.Size() == 16) { + break + } + v.reset(OpAMD64VMOVDQUload128) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: t.Size() == 32 + // result: (VMOVDQUload256 ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(t.Size() == 32) { + break + } + v.reset(OpAMD64VMOVDQUload256) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: t.Size() == 64 + // result: (VMOVDQUload512 ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VMOVDQUload512) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpLoadMasked16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (LoadMasked16 ptr mask mem) + // cond: t.Size() == 64 + // result: (VPMASK16load512 ptr (VPMOVVec16x32ToM mask) mem) + for { + t := v.Type + ptr := v_0 + mask := v_1 + mem := v_2 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VPMASK16load512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(ptr, v0, mem) + return true + } + return false +} +func rewriteValueAMD64_OpLoadMasked32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (LoadMasked32 ptr mask mem) + // cond: t.Size() == 16 + // result: (VPMASK32load128 ptr mask mem) + for { + t := v.Type + ptr := v_0 + mask := v_1 + mem := v_2 + if !(t.Size() == 16) { + break + } + v.reset(OpAMD64VPMASK32load128) + v.AddArg3(ptr, mask, mem) + return true + } + // match: (LoadMasked32 ptr mask mem) + // cond: t.Size() == 32 + // result: (VPMASK32load256 ptr mask mem) + for { + t := v.Type + ptr := v_0 + mask := v_1 + mem := v_2 + if !(t.Size() == 32) { + break + } + v.reset(OpAMD64VPMASK32load256) + v.AddArg3(ptr, mask, mem) + return true + } + // match: (LoadMasked32 ptr mask mem) + // cond: t.Size() == 64 + // result: (VPMASK32load512 ptr (VPMOVVec32x16ToM mask) mem) + for { + t := v.Type + ptr := v_0 + mask := v_1 + mem := v_2 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VPMASK32load512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(ptr, v0, mem) + return true + } + return false +} +func rewriteValueAMD64_OpLoadMasked64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (LoadMasked64 ptr mask mem) + // cond: t.Size() == 16 + // result: (VPMASK64load128 ptr mask mem) + for { + t := v.Type + ptr := v_0 + mask := v_1 + mem := v_2 + if !(t.Size() == 16) { + break + } + v.reset(OpAMD64VPMASK64load128) + v.AddArg3(ptr, mask, mem) + return true + } + // match: (LoadMasked64 ptr mask mem) + // cond: t.Size() == 32 + // result: (VPMASK64load256 ptr mask mem) + for { + t := v.Type + ptr := v_0 + mask := v_1 + mem := v_2 + if !(t.Size() == 32) { + break + } + v.reset(OpAMD64VPMASK64load256) + v.AddArg3(ptr, mask, mem) + return true + } + // match: (LoadMasked64 ptr mask mem) + // cond: t.Size() == 64 + // result: (VPMASK64load512 ptr (VPMOVVec64x8ToM mask) mem) + for { + t := v.Type + ptr := v_0 + mask := v_1 + mem := v_2 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VPMASK64load512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(ptr, v0, mem) + return true + } + return false +} +func rewriteValueAMD64_OpLoadMasked8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (LoadMasked8 ptr mask mem) + // cond: t.Size() == 64 + // result: (VPMASK8load512 ptr (VPMOVVec8x64ToM mask) mem) + for { + t := v.Type + ptr := v_0 + mask := v_1 + mem := v_2 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VPMASK8load512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(ptr, v0, mem) + return true + } + return false +} +func rewriteValueAMD64_OpLocalAddr(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LocalAddr {sym} base mem) + // cond: t.Elem().HasPointers() + // result: (LEAQ {sym} (SPanchored base mem)) + for { + t := v.Type + sym := auxToSym(v.Aux) + base := v_0 + mem := v_1 + if !(t.Elem().HasPointers()) { + break + } + v.reset(OpAMD64LEAQ) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) + v0.AddArg2(base, mem) + v.AddArg(v0) + return true + } + // match: (LocalAddr {sym} base _) + // cond: !t.Elem().HasPointers() + // result: (LEAQ {sym} base) + for { + t := v.Type + sym := auxToSym(v.Aux) + base := v_0 + if !(!t.Elem().HasPointers()) { + break + } + v.reset(OpAMD64LEAQ) + v.Aux = symToAux(sym) + v.AddArg(base) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh16x16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh16x16 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh16x32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh16x32 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh16x64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh16x64 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh16x8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh16x8 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh32x16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh32x16 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh32x32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh32x32 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh32x64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh32x64 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh32x8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh32x8 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh64x16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh64x16 x y) + // cond: shiftIsBounded(v) + // result: (SHLQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh64x32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh64x32 x y) + // cond: shiftIsBounded(v) + // result: (SHLQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh64x64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh64x64 x y) + // cond: shiftIsBounded(v) + // result: (SHLQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh64x8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh64x8 x y) + // cond: shiftIsBounded(v) + // result: (SHLQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh8x16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh8x16 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh8x32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh8x32 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh8x64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh8x64 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh8x8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh8x8 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpMax32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Max32F x y) + // result: (Neg32F (Min32F (Neg32F x) (Neg32F y))) + for { + t := v.Type + x := v_0 + y := v_1 + v.reset(OpNeg32F) + v.Type = t + v0 := b.NewValue0(v.Pos, OpMin32F, t) + v1 := b.NewValue0(v.Pos, OpNeg32F, t) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpNeg32F, t) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMax64F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Max64F x y) + // result: (Neg64F (Min64F (Neg64F x) (Neg64F y))) + for { + t := v.Type + x := v_0 + y := v_1 + v.reset(OpNeg64F) + v.Type = t + v0 := b.NewValue0(v.Pos, OpMin64F, t) + v1 := b.NewValue0(v.Pos, OpNeg64F, t) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpNeg64F, t) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMin32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Min32F x y) + // result: (POR (MINSS (MINSS x y) x) (MINSS x y)) + for { + t := v.Type + x := v_0 + y := v_1 + v.reset(OpAMD64POR) + v0 := b.NewValue0(v.Pos, OpAMD64MINSS, t) + v1 := b.NewValue0(v.Pos, OpAMD64MINSS, t) + v1.AddArg2(x, y) + v0.AddArg2(v1, x) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueAMD64_OpMin64F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Min64F x y) + // result: (POR (MINSD (MINSD x y) x) (MINSD x y)) + for { + t := v.Type + x := v_0 + y := v_1 + v.reset(OpAMD64POR) + v0 := b.NewValue0(v.Pos, OpAMD64MINSD, t) + v1 := b.NewValue0(v.Pos, OpAMD64MINSD, t) + v1.AddArg2(x, y) + v0.AddArg2(v1, x) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueAMD64_OpMod16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Mod16 [a] x y) + // result: (Select1 (DIVW [a] x y)) + for { + a := auxIntToBool(v.AuxInt) + x := v_0 + y := v_1 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) + v0.AuxInt = boolToAuxInt(a) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMod16u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Mod16u x y) + // result: (Select1 (DIVWU x y)) + for { + x := v_0 + y := v_1 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMod32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Mod32 [a] x y) + // result: (Select1 (DIVL [a] x y)) + for { + a := auxIntToBool(v.AuxInt) + x := v_0 + y := v_1 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) + v0.AuxInt = boolToAuxInt(a) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMod32u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Mod32u x y) + // result: (Select1 (DIVLU x y)) + for { + x := v_0 + y := v_1 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMod64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Mod64 [a] x y) + // result: (Select1 (DIVQ [a] x y)) + for { + a := auxIntToBool(v.AuxInt) + x := v_0 + y := v_1 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) + v0.AuxInt = boolToAuxInt(a) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMod64u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Mod64u x y) + // result: (Select1 (DIVQU x y)) + for { + x := v_0 + y := v_1 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMod8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Mod8 x y) + // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) + for { + x := v_0 + y := v_1 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) + v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMod8u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Mod8u x y) + // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) + for { + x := v_0 + y := v_1 + v.reset(OpSelect1) + v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) + v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMove(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Move [0] _ _ mem) + // result: mem + for { + if auxIntToInt64(v.AuxInt) != 0 { + break + } + mem := v_2 + v.copyOf(mem) + return true + } + // match: (Move [1] dst src mem) + // result: (MOVBstore dst (MOVBload src mem) mem) + for { + if auxIntToInt64(v.AuxInt) != 1 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVBstore) + v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) + v0.AddArg2(src, mem) + v.AddArg3(dst, v0, mem) + return true + } + // match: (Move [2] dst src mem) + // result: (MOVWstore dst (MOVWload src mem) mem) + for { + if auxIntToInt64(v.AuxInt) != 2 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVWstore) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) + v0.AddArg2(src, mem) + v.AddArg3(dst, v0, mem) + return true + } + // match: (Move [4] dst src mem) + // result: (MOVLstore dst (MOVLload src mem) mem) + for { + if auxIntToInt64(v.AuxInt) != 4 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVLstore) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) + v0.AddArg2(src, mem) + v.AddArg3(dst, v0, mem) + return true + } + // match: (Move [8] dst src mem) + // result: (MOVQstore dst (MOVQload src mem) mem) + for { + if auxIntToInt64(v.AuxInt) != 8 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVQstore) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v0.AddArg2(src, mem) + v.AddArg3(dst, v0, mem) + return true + } + // match: (Move [16] dst src mem) + // result: (MOVOstore dst (MOVOload src mem) mem) + for { + if auxIntToInt64(v.AuxInt) != 16 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVOstore) + v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) + v0.AddArg2(src, mem) + v.AddArg3(dst, v0, mem) + return true + } + // match: (Move [3] dst src mem) + // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) + for { + if auxIntToInt64(v.AuxInt) != 3 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(2) + v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) + v0.AuxInt = int32ToAuxInt(2) + v0.AddArg2(src, mem) + v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) + v.AddArg3(dst, v0, v1) + return true + } + // match: (Move [5] dst src mem) + // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) + for { + if auxIntToInt64(v.AuxInt) != 5 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(4) + v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) + v0.AuxInt = int32ToAuxInt(4) + v0.AddArg2(src, mem) + v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) + v.AddArg3(dst, v0, v1) + return true + } + // match: (Move [6] dst src mem) + // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) + for { + if auxIntToInt64(v.AuxInt) != 6 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVWstore) + v.AuxInt = int32ToAuxInt(4) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) + v0.AuxInt = int32ToAuxInt(4) + v0.AddArg2(src, mem) + v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) + v.AddArg3(dst, v0, v1) + return true + } + // match: (Move [7] dst src mem) + // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) + for { + if auxIntToInt64(v.AuxInt) != 7 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVLstore) + v.AuxInt = int32ToAuxInt(3) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) + v0.AuxInt = int32ToAuxInt(3) + v0.AddArg2(src, mem) + v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) + v.AddArg3(dst, v0, v1) + return true + } + // match: (Move [9] dst src mem) + // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) + for { + if auxIntToInt64(v.AuxInt) != 9 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVBstore) + v.AuxInt = int32ToAuxInt(8) + v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) + v0.AuxInt = int32ToAuxInt(8) + v0.AddArg2(src, mem) + v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) + v.AddArg3(dst, v0, v1) + return true + } + // match: (Move [10] dst src mem) + // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) + for { + if auxIntToInt64(v.AuxInt) != 10 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVWstore) + v.AuxInt = int32ToAuxInt(8) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) + v0.AuxInt = int32ToAuxInt(8) + v0.AddArg2(src, mem) + v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) + v.AddArg3(dst, v0, v1) + return true + } + // match: (Move [11] dst src mem) + // result: (MOVLstore [7] dst (MOVLload [7] src mem) (MOVQstore dst (MOVQload src mem) mem)) + for { + if auxIntToInt64(v.AuxInt) != 11 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVLstore) + v.AuxInt = int32ToAuxInt(7) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) + v0.AuxInt = int32ToAuxInt(7) + v0.AddArg2(src, mem) + v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) + v.AddArg3(dst, v0, v1) + return true + } + // match: (Move [12] dst src mem) + // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) + for { + if auxIntToInt64(v.AuxInt) != 12 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpAMD64MOVLstore) + v.AuxInt = int32ToAuxInt(8) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) + v0.AuxInt = int32ToAuxInt(8) + v0.AddArg2(src, mem) + v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) + v.AddArg3(dst, v0, v1) + return true + } + // match: (Move [s] dst src mem) + // cond: s >= 13 && s <= 15 + // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem)) + for { + s := auxIntToInt64(v.AuxInt) + dst := v_0 + src := v_1 + mem := v_2 + if !(s >= 13 && s <= 15) { + break + } + v.reset(OpAMD64MOVQstore) + v.AuxInt = int32ToAuxInt(int32(s - 8)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v0.AuxInt = int32ToAuxInt(int32(s - 8)) + v0.AddArg2(src, mem) + v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) + v.AddArg3(dst, v0, v1) + return true + } + // match: (Move [s] dst src mem) + // cond: s > 16 && s < 192 && logLargeCopy(v, s) + // result: (LoweredMove [s] dst src mem) + for { + s := auxIntToInt64(v.AuxInt) + dst := v_0 + src := v_1 + mem := v_2 + if !(s > 16 && s < 192 && logLargeCopy(v, s)) { + break + } + v.reset(OpAMD64LoweredMove) + v.AuxInt = int64ToAuxInt(s) + v.AddArg3(dst, src, mem) + return true + } + // match: (Move [s] dst src mem) + // cond: s >= 192 && s <= repMoveThreshold && logLargeCopy(v, s) + // result: (LoweredMoveLoop [s] dst src mem) + for { + s := auxIntToInt64(v.AuxInt) + dst := v_0 + src := v_1 + mem := v_2 + if !(s >= 192 && s <= repMoveThreshold && logLargeCopy(v, s)) { + break + } + v.reset(OpAMD64LoweredMoveLoop) + v.AuxInt = int64ToAuxInt(s) + v.AddArg3(dst, src, mem) + return true + } + // match: (Move [s] dst src mem) + // cond: s > repMoveThreshold && s%8 != 0 + // result: (Move [s-s%8] (OffPtr dst [s%8]) (OffPtr src [s%8]) (MOVQstore dst (MOVQload src mem) mem)) + for { + s := auxIntToInt64(v.AuxInt) + dst := v_0 + src := v_1 + mem := v_2 + if !(s > repMoveThreshold && s%8 != 0) { + break + } + v.reset(OpMove) + v.AuxInt = int64ToAuxInt(s - s%8) + v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) + v0.AuxInt = int64ToAuxInt(s % 8) + v0.AddArg(dst) + v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) + v1.AuxInt = int64ToAuxInt(s % 8) + v1.AddArg(src) + v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) + v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v3.AddArg2(src, mem) + v2.AddArg3(dst, v3, mem) + v.AddArg3(v0, v1, v2) + return true + } + // match: (Move [s] dst src mem) + // cond: s > repMoveThreshold && s%8 == 0 && logLargeCopy(v, s) + // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) + for { + s := auxIntToInt64(v.AuxInt) + dst := v_0 + src := v_1 + mem := v_2 + if !(s > repMoveThreshold && s%8 == 0 && logLargeCopy(v, s)) { + break + } + v.reset(OpAMD64REPMOVSQ) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(s / 8) + v.AddArg4(dst, src, v0, mem) + return true + } + return false +} +func rewriteValueAMD64_OpNeg32F(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Neg32F x) + // result: (PXOR x (MOVSSconst [float32(math.Copysign(0, -1))])) + for { + x := v_0 + v.reset(OpAMD64PXOR) + v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) + v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1))) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpNeg64F(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Neg64F x) + // result: (PXOR x (MOVSDconst [math.Copysign(0, -1)])) + for { + x := v_0 + v.reset(OpAMD64PXOR) + v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) + v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1)) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpNeq16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Neq16 x y) + // result: (SETNE (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNeq32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Neq32 x y) + // result: (SETNE (CMPL x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNeq32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Neq32F x y) + // result: (SETNEF (UCOMISS x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETNEF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNeq64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Neq64 x y) + // result: (SETNE (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNeq64F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Neq64F x y) + // result: (SETNEF (UCOMISD x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETNEF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNeq8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Neq8 x y) + // result: (SETNE (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNeqB(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (NeqB x y) + // result: (SETNE (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNeqPtr(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (NeqPtr x y) + // result: (SETNE (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNot(v *Value) bool { + v_0 := v.Args[0] + // match: (Not x) + // result: (XORLconst [1] x) + for { + x := v_0 + v.reset(OpAMD64XORLconst) + v.AuxInt = int32ToAuxInt(1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (NotEqualFloat32x4 x y) + // result: (VCMPPS128 [4] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = uint8ToAuxInt(4) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (NotEqualFloat32x8 x y) + // result: (VCMPPS256 [4] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = uint8ToAuxInt(4) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (NotEqualFloat64x2 x y) + // result: (VCMPPD128 [4] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = uint8ToAuxInt(4) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (NotEqualFloat64x4 x y) + // result: (VCMPPD256 [4] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = uint8ToAuxInt(4) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPW512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPD512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPQ512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPB512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = uint8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpOffPtr(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (OffPtr [off] ptr) + // cond: is32Bit(off) + // result: (ADDQconst [int32(off)] ptr) + for { + off := auxIntToInt64(v.AuxInt) + ptr := v_0 + if !(is32Bit(off)) { + break + } + v.reset(OpAMD64ADDQconst) + v.AuxInt = int32ToAuxInt(int32(off)) + v.AddArg(ptr) + return true + } + // match: (OffPtr [off] ptr) + // result: (ADDQ (MOVQconst [off]) ptr) + for { + off := auxIntToInt64(v.AuxInt) + ptr := v_0 + v.reset(OpAMD64ADDQ) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(off) + v.AddArg2(v0, ptr) + return true + } +} +func rewriteValueAMD64_OpPopCount16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (PopCount16 x) + // result: (POPCNTL (MOVWQZX x)) + for { + x := v_0 + v.reset(OpAMD64POPCNTL) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpPopCount8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (PopCount8 x) + // result: (POPCNTL (MOVBQZX x)) + for { + x := v_0 + v.reset(OpAMD64POPCNTL) + v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpRoundFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundFloat32x4 x) + // result: (VROUNDPS128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundFloat32x8 x) + // result: (VROUNDPS256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundFloat64x2 x) + // result: (VROUNDPD128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD128) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundFloat64x4 x) + // result: (VROUNDPD256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledResidueFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledResidueFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledResidueFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledResidueFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledResidueFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledResidueFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledResidueFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledResidueFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledResidueFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledResidueFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundScaledResidueFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundScaledResidueFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+0] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = uint8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundToEven(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundToEven x) + // result: (ROUNDSD [0] x) + for { + x := v_0 + v.reset(OpAMD64ROUNDSD) + v.AuxInt = int8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh16Ux16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(16) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh16Ux16 x y) + // cond: shiftIsBounded(v) + // result: (SHRW x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRW) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh16Ux32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(16) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh16Ux32 x y) + // cond: shiftIsBounded(v) + // result: (SHRW x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRW) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh16Ux64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(16) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh16Ux64 x y) + // cond: shiftIsBounded(v) + // result: (SHRW x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRW) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh16Ux8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(16) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh16Ux8 x y) + // cond: shiftIsBounded(v) + // result: (SHRW x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRW) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh16x16 x y) + // cond: !shiftIsBounded(v) + // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARW) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v3.AuxInt = int16ToAuxInt(16) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh16x16 x y) + // cond: shiftIsBounded(v) + // result: (SARW x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARW) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh16x32 x y) + // cond: !shiftIsBounded(v) + // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARW) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v3.AuxInt = int32ToAuxInt(16) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh16x32 x y) + // cond: shiftIsBounded(v) + // result: (SARW x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARW) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh16x64 x y) + // cond: !shiftIsBounded(v) + // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARW) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v3.AuxInt = int32ToAuxInt(16) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh16x64 x y) + // cond: shiftIsBounded(v) + // result: (SARW x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARW) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh16x8 x y) + // cond: !shiftIsBounded(v) + // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARW) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v3.AuxInt = int8ToAuxInt(16) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh16x8 x y) + // cond: shiftIsBounded(v) + // result: (SARW x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARW) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh32Ux16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh32Ux16 x y) + // cond: shiftIsBounded(v) + // result: (SHRL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh32Ux32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh32Ux32 x y) + // cond: shiftIsBounded(v) + // result: (SHRL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh32Ux64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh32Ux64 x y) + // cond: shiftIsBounded(v) + // result: (SHRL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh32Ux8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh32Ux8 x y) + // cond: shiftIsBounded(v) + // result: (SHRL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh32x16 x y) + // cond: !shiftIsBounded(v) + // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARL) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v3.AuxInt = int16ToAuxInt(32) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh32x16 x y) + // cond: shiftIsBounded(v) + // result: (SARL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh32x32 x y) + // cond: !shiftIsBounded(v) + // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARL) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v3.AuxInt = int32ToAuxInt(32) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh32x32 x y) + // cond: shiftIsBounded(v) + // result: (SARL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh32x64 x y) + // cond: !shiftIsBounded(v) + // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARL) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v3.AuxInt = int32ToAuxInt(32) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh32x64 x y) + // cond: shiftIsBounded(v) + // result: (SARL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh32x8 x y) + // cond: !shiftIsBounded(v) + // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARL) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v3.AuxInt = int8ToAuxInt(32) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh32x8 x y) + // cond: shiftIsBounded(v) + // result: (SARL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh64Ux16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh64Ux16 x y) + // cond: shiftIsBounded(v) + // result: (SHRQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh64Ux32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh64Ux32 x y) + // cond: shiftIsBounded(v) + // result: (SHRQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh64Ux64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh64Ux64 x y) + // cond: shiftIsBounded(v) + // result: (SHRQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh64Ux8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh64Ux8 x y) + // cond: shiftIsBounded(v) + // result: (SHRQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh64x16 x y) + // cond: !shiftIsBounded(v) + // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARQ) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v3.AuxInt = int16ToAuxInt(64) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh64x16 x y) + // cond: shiftIsBounded(v) + // result: (SARQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh64x32 x y) + // cond: !shiftIsBounded(v) + // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARQ) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v3.AuxInt = int32ToAuxInt(64) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh64x32 x y) + // cond: shiftIsBounded(v) + // result: (SARQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh64x64 x y) + // cond: !shiftIsBounded(v) + // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARQ) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v3.AuxInt = int32ToAuxInt(64) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh64x64 x y) + // cond: shiftIsBounded(v) + // result: (SARQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh64x8 x y) + // cond: !shiftIsBounded(v) + // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARQ) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v3.AuxInt = int8ToAuxInt(64) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh64x8 x y) + // cond: shiftIsBounded(v) + // result: (SARQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh8Ux16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(8) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh8Ux16 x y) + // cond: shiftIsBounded(v) + // result: (SHRB x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRB) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh8Ux32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(8) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh8Ux32 x y) + // cond: shiftIsBounded(v) + // result: (SHRB x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRB) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh8Ux64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(8) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh8Ux64 x y) + // cond: shiftIsBounded(v) + // result: (SHRB x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRB) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh8Ux8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(8) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Rsh8Ux8 x y) + // cond: shiftIsBounded(v) + // result: (SHRB x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHRB) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh8x16 x y) + // cond: !shiftIsBounded(v) + // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARB) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v3.AuxInt = int16ToAuxInt(8) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh8x16 x y) + // cond: shiftIsBounded(v) + // result: (SARB x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARB) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh8x32 x y) + // cond: !shiftIsBounded(v) + // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARB) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v3.AuxInt = int32ToAuxInt(8) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh8x32 x y) + // cond: shiftIsBounded(v) + // result: (SARB x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARB) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh8x64 x y) + // cond: !shiftIsBounded(v) + // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARB) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v3.AuxInt = int32ToAuxInt(8) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh8x64 x y) + // cond: shiftIsBounded(v) + // result: (SARB x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARB) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Rsh8x8 x y) + // cond: !shiftIsBounded(v) + // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARB) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) + v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v3.AuxInt = int8ToAuxInt(8) + v3.AddArg(y) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(y, v1) + v.AddArg2(x, v0) + return true + } + // match: (Rsh8x8 x y) + // cond: shiftIsBounded(v) + // result: (SARB x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SARB) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpSelect0(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Select0 (Mul64uover x y)) + // result: (Select0 (MULQU x y)) + for { + if v_0.Op != OpMul64uover { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + v.reset(OpSelect0) + v.Type = typ.UInt64 + v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + // match: (Select0 (Mul32uover x y)) + // result: (Select0 (MULLU x y)) + for { + if v_0.Op != OpMul32uover { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + v.reset(OpSelect0) + v.Type = typ.UInt32 + v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + // match: (Select0 (Add64carry x y c)) + // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) + for { + if v_0.Op != OpAdd64carry { + break + } + c := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) + v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) + v2.AddArg(c) + v1.AddArg(v2) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } + // match: (Select0 (Sub64borrow x y c)) + // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) + for { + if v_0.Op != OpSub64borrow { + break + } + c := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) + v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) + v2.AddArg(c) + v1.AddArg(v2) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } + // match: (Select0 (AddTupleFirst32 val tuple)) + // result: (ADDL val (Select0 tuple)) + for { + t := v.Type + if v_0.Op != OpAMD64AddTupleFirst32 { + break + } + tuple := v_0.Args[1] + val := v_0.Args[0] + v.reset(OpAMD64ADDL) + v0 := b.NewValue0(v.Pos, OpSelect0, t) + v0.AddArg(tuple) + v.AddArg2(val, v0) + return true + } + // match: (Select0 (AddTupleFirst64 val tuple)) + // result: (ADDQ val (Select0 tuple)) + for { + t := v.Type + if v_0.Op != OpAMD64AddTupleFirst64 { + break + } + tuple := v_0.Args[1] + val := v_0.Args[0] + v.reset(OpAMD64ADDQ) + v0 := b.NewValue0(v.Pos, OpSelect0, t) + v0.AddArg(tuple) + v.AddArg2(val, v0) + return true + } + // match: (Select0 a:(ADDQconstflags [c] x)) + // cond: a.Uses == 1 + // result: (ADDQconst [c] x) + for { + a := v_0 + if a.Op != OpAMD64ADDQconstflags { + break + } + c := auxIntToInt32(a.AuxInt) + x := a.Args[0] + if !(a.Uses == 1) { + break + } + v.reset(OpAMD64ADDQconst) + v.AuxInt = int32ToAuxInt(c) + v.AddArg(x) + return true + } + // match: (Select0 a:(ADDLconstflags [c] x)) + // cond: a.Uses == 1 + // result: (ADDLconst [c] x) + for { + a := v_0 + if a.Op != OpAMD64ADDLconstflags { + break + } + c := auxIntToInt32(a.AuxInt) + x := a.Args[0] + if !(a.Uses == 1) { + break + } + v.reset(OpAMD64ADDLconst) + v.AuxInt = int32ToAuxInt(c) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpSelect1(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Select1 (Mul64uover x y)) + // result: (SETO (Select1 (MULQU x y))) + for { + if v_0.Op != OpMul64uover { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + v.reset(OpAMD64SETO) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) + v1.AddArg2(x, y) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (Select1 (Mul32uover x y)) + // result: (SETO (Select1 (MULLU x y))) + for { + if v_0.Op != OpMul32uover { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + v.reset(OpAMD64SETO) + v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) + v1.AddArg2(x, y) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (Select1 (Add64carry x y c)) + // result: (MOVBQZX (SETB (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) + for { + if v_0.Op != OpAdd64carry { + break + } + c := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + v.reset(OpAMD64MOVBQZX) + v0 := b.NewValue0(v.Pos, OpAMD64SETB, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) + v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) + v4.AddArg(c) + v3.AddArg(v4) + v2.AddArg3(x, y, v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (Select1 (Sub64borrow x y c)) + // result: (MOVBQZX (SETB (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) + for { + if v_0.Op != OpSub64borrow { + break + } + c := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + v.reset(OpAMD64MOVBQZX) + v0 := b.NewValue0(v.Pos, OpAMD64SETB, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) + v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) + v4.AddArg(c) + v3.AddArg(v4) + v2.AddArg3(x, y, v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (Select1 (NEGLflags (MOVQconst [0]))) + // result: (FlagEQ) + for { + if v_0.Op != OpAMD64NEGLflags { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 { + break + } + v.reset(OpAMD64FlagEQ) + return true + } + // match: (Select1 (NEGLflags (MOVBQZX (SETB x)))) + // result: x + for { + if v_0.Op != OpAMD64NEGLflags { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVBQZX { + break + } + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64SETB { + break + } + x := v_0_0_0.Args[0] + v.copyOf(x) + return true + } + // match: (Select1 (AddTupleFirst32 _ tuple)) + // result: (Select1 tuple) + for { + if v_0.Op != OpAMD64AddTupleFirst32 { + break + } + tuple := v_0.Args[1] + v.reset(OpSelect1) + v.AddArg(tuple) + return true + } + // match: (Select1 (AddTupleFirst64 _ tuple)) + // result: (Select1 tuple) + for { + if v_0.Op != OpAMD64AddTupleFirst64 { + break + } + tuple := v_0.Args[1] + v.reset(OpSelect1) + v.AddArg(tuple) + return true + } + // match: (Select1 a:(LoweredAtomicAnd64 ptr val mem)) + // cond: a.Uses == 1 && clobber(a) + // result: (ANDQlock ptr val mem) + for { + a := v_0 + if a.Op != OpAMD64LoweredAtomicAnd64 { + break + } + mem := a.Args[2] + ptr := a.Args[0] + val := a.Args[1] + if !(a.Uses == 1 && clobber(a)) { + break + } + v.reset(OpAMD64ANDQlock) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Select1 a:(LoweredAtomicAnd32 ptr val mem)) + // cond: a.Uses == 1 && clobber(a) + // result: (ANDLlock ptr val mem) + for { + a := v_0 + if a.Op != OpAMD64LoweredAtomicAnd32 { + break + } + mem := a.Args[2] + ptr := a.Args[0] + val := a.Args[1] + if !(a.Uses == 1 && clobber(a)) { + break + } + v.reset(OpAMD64ANDLlock) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Select1 a:(LoweredAtomicOr64 ptr val mem)) + // cond: a.Uses == 1 && clobber(a) + // result: (ORQlock ptr val mem) + for { + a := v_0 + if a.Op != OpAMD64LoweredAtomicOr64 { + break + } + mem := a.Args[2] + ptr := a.Args[0] + val := a.Args[1] + if !(a.Uses == 1 && clobber(a)) { + break + } + v.reset(OpAMD64ORQlock) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Select1 a:(LoweredAtomicOr32 ptr val mem)) + // cond: a.Uses == 1 && clobber(a) + // result: (ORLlock ptr val mem) + for { + a := v_0 + if a.Op != OpAMD64LoweredAtomicOr32 { + break + } + mem := a.Args[2] + ptr := a.Args[0] + val := a.Args[1] + if !(a.Uses == 1 && clobber(a)) { + break + } + v.reset(OpAMD64ORLlock) + v.AddArg3(ptr, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpSelectN(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem))))) + // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call) + // result: (Move [sc.Val64()] dst src mem) + for { + if auxIntToInt64(v.AuxInt) != 0 { + break + } + call := v_0 + if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 { + break + } + sym := auxToCall(call.Aux) + s1 := call.Args[0] + if s1.Op != OpAMD64MOVQstoreconst { + break + } + sc := auxIntToValAndOff(s1.AuxInt) + _ = s1.Args[1] + s2 := s1.Args[1] + if s2.Op != OpAMD64MOVQstore { + break + } + _ = s2.Args[2] + src := s2.Args[1] + s3 := s2.Args[2] + if s3.Op != OpAMD64MOVQstore { + break + } + mem := s3.Args[2] + dst := s3.Args[1] + if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) { + break + } + v.reset(OpMove) + v.AuxInt = int64ToAuxInt(sc.Val64()) + v.AddArg3(dst, src, mem) + return true + } + // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem)) + // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) + // result: (Move [sz] dst src mem) + for { + if auxIntToInt64(v.AuxInt) != 0 { + break + } + call := v_0 + if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 { + break + } + sym := auxToCall(call.Aux) + mem := call.Args[3] + dst := call.Args[0] + src := call.Args[1] + call_2 := call.Args[2] + if call_2.Op != OpAMD64MOVQconst { + break + } + sz := auxIntToInt64(call_2.AuxInt) + if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { + break + } + v.reset(OpMove) + v.AuxInt = int64ToAuxInt(sz) + v.AddArg3(dst, src, mem) + return true + } + return false +} +func rewriteValueAMD64_OpSetHiFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiFloat32x16 x y) + // result: (VINSERTF64X4512 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTF64X4512) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiFloat32x8 x y) + // result: (VINSERTF128256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTF128256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiFloat64x4 x y) + // result: (VINSERTF128256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTF128256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiFloat64x8 x y) + // result: (VINSERTF64X4512 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTF64X4512) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiInt16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiInt16x16 x y) + // result: (VINSERTI128256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiInt16x32 x y) + // result: (VINSERTI64X4512 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiInt32x16 x y) + // result: (VINSERTI64X4512 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiInt32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiInt32x8 x y) + // result: (VINSERTI128256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiInt64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiInt64x4 x y) + // result: (VINSERTI128256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiInt64x8 x y) + // result: (VINSERTI64X4512 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiInt8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiInt8x32 x y) + // result: (VINSERTI128256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiInt8x64 x y) + // result: (VINSERTI64X4512 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiUint16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiUint16x16 x y) + // result: (VINSERTI128256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiUint16x32 x y) + // result: (VINSERTI64X4512 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiUint32x16 x y) + // result: (VINSERTI64X4512 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiUint32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiUint32x8 x y) + // result: (VINSERTI128256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiUint64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiUint64x4 x y) + // result: (VINSERTI128256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiUint64x8 x y) + // result: (VINSERTI64X4512 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiUint8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiUint8x32 x y) + // result: (VINSERTI128256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetHiUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetHiUint8x64 x y) + // result: (VINSERTI64X4512 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoFloat32x16 x y) + // result: (VINSERTF64X4512 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTF64X4512) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoFloat32x8 x y) + // result: (VINSERTF128256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTF128256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoFloat64x4 x y) + // result: (VINSERTF128256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTF128256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoFloat64x8 x y) + // result: (VINSERTF64X4512 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTF64X4512) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoInt16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoInt16x16 x y) + // result: (VINSERTI128256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoInt16x32 x y) + // result: (VINSERTI64X4512 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoInt32x16 x y) + // result: (VINSERTI64X4512 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoInt32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoInt32x8 x y) + // result: (VINSERTI128256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoInt64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoInt64x4 x y) + // result: (VINSERTI128256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoInt64x8 x y) + // result: (VINSERTI64X4512 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoInt8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoInt8x32 x y) + // result: (VINSERTI128256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoInt8x64 x y) + // result: (VINSERTI64X4512 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoUint16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoUint16x16 x y) + // result: (VINSERTI128256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoUint16x32 x y) + // result: (VINSERTI64X4512 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoUint32x16 x y) + // result: (VINSERTI64X4512 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoUint32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoUint32x8 x y) + // result: (VINSERTI128256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoUint64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoUint64x4 x y) + // result: (VINSERTI128256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoUint64x8 x y) + // result: (VINSERTI64X4512 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoUint8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoUint8x32 x y) + // result: (VINSERTI128256 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI128256) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSetLoUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (SetLoUint8x64 x y) + // result: (VINSERTI64X4512 [0] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VINSERTI64X4512) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpSlicemask(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Slicemask x) + // result: (SARQconst (NEGQ x) [63]) + for { + t := v.Type + x := v_0 + v.reset(OpAMD64SARQconst) + v.AuxInt = int8ToAuxInt(63) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpSpectreIndex(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (SpectreIndex x y) + // result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64CMOVQCC) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v1.AddArg2(x, y) + v.AddArg3(x, v0, v1) + return true + } +} +func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (SpectreSliceIndex x y) + // result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64CMOVQHI) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v1.AddArg2(x, y) + v.AddArg3(x, v0, v1) + return true + } +} +func rewriteValueAMD64_OpStore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (Store {t} ptr val mem) + // cond: t.Size() == 8 && t.IsFloat() + // result: (MOVSDstore ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 8 && t.IsFloat()) { + break + } + v.reset(OpAMD64MOVSDstore) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 4 && t.IsFloat() + // result: (MOVSSstore ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 4 && t.IsFloat()) { + break + } + v.reset(OpAMD64MOVSSstore) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 8 && !t.IsFloat() + // result: (MOVQstore ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 8 && !t.IsFloat()) { + break + } + v.reset(OpAMD64MOVQstore) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 4 && !t.IsFloat() + // result: (MOVLstore ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 4 && !t.IsFloat()) { + break + } + v.reset(OpAMD64MOVLstore) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 2 + // result: (MOVWstore ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 2) { + break + } + v.reset(OpAMD64MOVWstore) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 1 + // result: (MOVBstore ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 1) { + break + } + v.reset(OpAMD64MOVBstore) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 16 + // result: (VMOVDQUstore128 ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 16) { + break + } + v.reset(OpAMD64VMOVDQUstore128) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 32 + // result: (VMOVDQUstore256 ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 32) { + break + } + v.reset(OpAMD64VMOVDQUstore256) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 64 + // result: (VMOVDQUstore512 ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VMOVDQUstore512) + v.AddArg3(ptr, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpStoreMasked16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (StoreMasked16 {t} ptr mask val mem) + // cond: t.Size() == 64 + // result: (VPMASK16store512 ptr (VPMOVVec16x32ToM mask) val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + mask := v_1 + val := v_2 + mem := v_3 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VPMASK16store512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(ptr, v0, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpStoreMasked32(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (StoreMasked32 {t} ptr mask val mem) + // cond: t.Size() == 16 + // result: (VPMASK32store128 ptr mask val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + mask := v_1 + val := v_2 + mem := v_3 + if !(t.Size() == 16) { + break + } + v.reset(OpAMD64VPMASK32store128) + v.AddArg4(ptr, mask, val, mem) + return true + } + // match: (StoreMasked32 {t} ptr mask val mem) + // cond: t.Size() == 32 + // result: (VPMASK32store256 ptr mask val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + mask := v_1 + val := v_2 + mem := v_3 + if !(t.Size() == 32) { + break + } + v.reset(OpAMD64VPMASK32store256) + v.AddArg4(ptr, mask, val, mem) + return true + } + // match: (StoreMasked32 {t} ptr mask val mem) + // cond: t.Size() == 64 + // result: (VPMASK32store512 ptr (VPMOVVec32x16ToM mask) val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + mask := v_1 + val := v_2 + mem := v_3 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VPMASK32store512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(ptr, v0, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpStoreMasked64(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (StoreMasked64 {t} ptr mask val mem) + // cond: t.Size() == 16 + // result: (VPMASK64store128 ptr mask val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + mask := v_1 + val := v_2 + mem := v_3 + if !(t.Size() == 16) { + break + } + v.reset(OpAMD64VPMASK64store128) + v.AddArg4(ptr, mask, val, mem) + return true + } + // match: (StoreMasked64 {t} ptr mask val mem) + // cond: t.Size() == 32 + // result: (VPMASK64store256 ptr mask val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + mask := v_1 + val := v_2 + mem := v_3 + if !(t.Size() == 32) { + break + } + v.reset(OpAMD64VPMASK64store256) + v.AddArg4(ptr, mask, val, mem) + return true + } + // match: (StoreMasked64 {t} ptr mask val mem) + // cond: t.Size() == 64 + // result: (VPMASK64store512 ptr (VPMOVVec64x8ToM mask) val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + mask := v_1 + val := v_2 + mem := v_3 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VPMASK64store512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(ptr, v0, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpStoreMasked8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (StoreMasked8 {t} ptr mask val mem) + // cond: t.Size() == 64 + // result: (VPMASK8store512 ptr (VPMOVVec8x64ToM mask) val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + mask := v_1 + val := v_2 + mem := v_3 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VPMASK8store512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(ptr, v0, val, mem) + return true + } + return false +} +func rewriteValueAMD64_OpTrunc(v *Value) bool { + v_0 := v.Args[0] + // match: (Trunc x) + // result: (ROUNDSD [3] x) + for { + x := v_0 + v.reset(OpAMD64ROUNDSD) + v.AuxInt = int8ToAuxInt(3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncFloat32x4 x) + // result: (VROUNDPS128 [3] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS128) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncFloat32x8 x) + // result: (VROUNDPS256 [3] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS256) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncFloat64x2 x) + // result: (VROUNDPD128 [3] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD128) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncFloat64x4 x) + // result: (VROUNDPD256 [3] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD256) + v.AuxInt = uint8ToAuxInt(3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledResidueFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledResidueFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledResidueFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledResidueFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledResidueFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledResidueFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledResidueFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledResidueFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledResidueFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledResidueFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncScaledResidueFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncScaledResidueFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+3] x) + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = uint8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpZero(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Zero [0] _ mem) + // result: mem + for { + if auxIntToInt64(v.AuxInt) != 0 { + break + } + mem := v_1 + v.copyOf(mem) + return true + } + // match: (Zero [1] destptr mem) + // result: (MOVBstoreconst [makeValAndOff(0,0)] destptr mem) + for { + if auxIntToInt64(v.AuxInt) != 1 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v.AddArg2(destptr, mem) + return true + } + // match: (Zero [2] destptr mem) + // result: (MOVWstoreconst [makeValAndOff(0,0)] destptr mem) + for { + if auxIntToInt64(v.AuxInt) != 2 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v.AddArg2(destptr, mem) + return true + } + // match: (Zero [4] destptr mem) + // result: (MOVLstoreconst [makeValAndOff(0,0)] destptr mem) + for { + if auxIntToInt64(v.AuxInt) != 4 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v.AddArg2(destptr, mem) + return true + } + // match: (Zero [8] destptr mem) + // result: (MOVQstoreconst [makeValAndOff(0,0)] destptr mem) + for { + if auxIntToInt64(v.AuxInt) != 8 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v.AddArg2(destptr, mem) + return true + } + // match: (Zero [3] destptr mem) + // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) + for { + if auxIntToInt64(v.AuxInt) != 3 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 2)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v0.AddArg2(destptr, mem) + v.AddArg2(destptr, v0) + return true + } + // match: (Zero [5] destptr mem) + // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) + for { + if auxIntToInt64(v.AuxInt) != 5 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v0.AddArg2(destptr, mem) + v.AddArg2(destptr, v0) + return true + } + // match: (Zero [6] destptr mem) + // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) + for { + if auxIntToInt64(v.AuxInt) != 6 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v0.AddArg2(destptr, mem) + v.AddArg2(destptr, v0) + return true + } + // match: (Zero [7] destptr mem) + // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) + for { + if auxIntToInt64(v.AuxInt) != 7 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 3)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v0.AddArg2(destptr, mem) + v.AddArg2(destptr, v0) + return true + } + // match: (Zero [9] destptr mem) + // result: (MOVBstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) + for { + if auxIntToInt64(v.AuxInt) != 9 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v0.AddArg2(destptr, mem) + v.AddArg2(destptr, v0) + return true + } + // match: (Zero [10] destptr mem) + // result: (MOVWstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) + for { + if auxIntToInt64(v.AuxInt) != 10 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v0.AddArg2(destptr, mem) + v.AddArg2(destptr, v0) + return true + } + // match: (Zero [11] destptr mem) + // result: (MOVLstoreconst [makeValAndOff(0,7)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) + for { + if auxIntToInt64(v.AuxInt) != 11 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 7)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v0.AddArg2(destptr, mem) + v.AddArg2(destptr, v0) + return true + } + // match: (Zero [12] destptr mem) + // result: (MOVLstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) + for { + if auxIntToInt64(v.AuxInt) != 12 { + break + } + destptr := v_0 + mem := v_1 + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v0.AddArg2(destptr, mem) + v.AddArg2(destptr, v0) + return true + } + // match: (Zero [s] destptr mem) + // cond: s > 12 && s < 16 + // result: (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) + for { + s := auxIntToInt64(v.AuxInt) + destptr := v_0 + mem := v_1 + if !(s > 12 && s < 16) { + break + } + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, int32(s-8))) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) + v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v0.AddArg2(destptr, mem) + v.AddArg2(destptr, v0) + return true + } + // match: (Zero [s] destptr mem) + // cond: s >= 16 && s < 192 + // result: (LoweredZero [s] destptr mem) + for { + s := auxIntToInt64(v.AuxInt) + destptr := v_0 + mem := v_1 + if !(s >= 16 && s < 192) { + break + } + v.reset(OpAMD64LoweredZero) + v.AuxInt = int64ToAuxInt(s) + v.AddArg2(destptr, mem) + return true + } + // match: (Zero [s] destptr mem) + // cond: s >= 192 && s <= repZeroThreshold + // result: (LoweredZeroLoop [s] destptr mem) + for { + s := auxIntToInt64(v.AuxInt) + destptr := v_0 + mem := v_1 + if !(s >= 192 && s <= repZeroThreshold) { + break + } + v.reset(OpAMD64LoweredZeroLoop) + v.AuxInt = int64ToAuxInt(s) + v.AddArg2(destptr, mem) + return true + } + // match: (Zero [s] destptr mem) + // cond: s > repZeroThreshold && s%8 != 0 + // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) + for { + s := auxIntToInt64(v.AuxInt) + destptr := v_0 + mem := v_1 + if !(s > repZeroThreshold && s%8 != 0) { + break + } + v.reset(OpZero) + v.AuxInt = int64ToAuxInt(s - s%8) + v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) + v0.AuxInt = int64ToAuxInt(s % 8) + v0.AddArg(destptr) + v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) + v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) + v1.AddArg2(destptr, mem) + v.AddArg2(v0, v1) + return true + } + // match: (Zero [s] destptr mem) + // cond: s > repZeroThreshold && s%8 == 0 + // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) + for { + s := auxIntToInt64(v.AuxInt) + destptr := v_0 + mem := v_1 + if !(s > repZeroThreshold && s%8 == 0) { + break + } + v.reset(OpAMD64REPSTOSQ) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(s / 8) + v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) + v1.AuxInt = int64ToAuxInt(0) + v.AddArg4(destptr, v0, v1, mem) + return true + } + return false +} +func rewriteValueAMD64_OpZeroSIMD(v *Value) bool { + // match: (ZeroSIMD ) + // cond: t.Size() == 16 + // result: (Zero128 ) + for { + t := v.Type + if !(t.Size() == 16) { + break + } + v.reset(OpAMD64Zero128) + v.Type = t + return true + } + // match: (ZeroSIMD ) + // cond: t.Size() == 32 + // result: (Zero256 ) + for { + t := v.Type + if !(t.Size() == 32) { + break + } + v.reset(OpAMD64Zero256) + v.Type = t + return true + } + // match: (ZeroSIMD ) + // cond: t.Size() == 64 + // result: (Zero512 ) + for { + t := v.Type + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64Zero512) + v.Type = t + return true + } + return false +} +func rewriteValueAMD64_OpblendMaskedInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (blendMaskedInt16x32 x y mask) + // result: (VPBLENDMWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPBLENDMWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpblendMaskedInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (blendMaskedInt32x16 x y mask) + // result: (VPBLENDMDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPBLENDMDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpblendMaskedInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (blendMaskedInt64x8 x y mask) + // result: (VPBLENDMQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPBLENDMQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpblendMaskedInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (blendMaskedInt8x64 x y mask) + // result: (VPBLENDMBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPBLENDMBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To16MaskedFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To16MaskedFloat32x4 x mask) + // result: (VBROADCASTSSMasked512 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VBROADCASTSSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To16MaskedInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To16MaskedInt16x8 x mask) + // result: (VPBROADCASTWMasked256 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To16MaskedInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To16MaskedInt32x4 x mask) + // result: (VPBROADCASTDMasked512 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To16MaskedInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To16MaskedInt8x16 x mask) + // result: (VPBROADCASTBMasked128 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To16MaskedUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To16MaskedUint16x8 x mask) + // result: (VPBROADCASTWMasked256 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To16MaskedUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To16MaskedUint32x4 x mask) + // result: (VPBROADCASTDMasked512 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To16MaskedUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To16MaskedUint8x16 x mask) + // result: (VPBROADCASTBMasked128 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To2MaskedFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To2MaskedFloat64x2 x mask) + // result: (VPBROADCASTQMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To2MaskedInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To2MaskedInt64x2 x mask) + // result: (VPBROADCASTQMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To2MaskedUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To2MaskedUint64x2 x mask) + // result: (VPBROADCASTQMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To32MaskedInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To32MaskedInt16x8 x mask) + // result: (VPBROADCASTWMasked512 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To32MaskedInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To32MaskedInt8x16 x mask) + // result: (VPBROADCASTBMasked256 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To32MaskedUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To32MaskedUint16x8 x mask) + // result: (VPBROADCASTWMasked512 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To32MaskedUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To32MaskedUint8x16 x mask) + // result: (VPBROADCASTBMasked256 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To4MaskedFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To4MaskedFloat32x4 x mask) + // result: (VBROADCASTSSMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VBROADCASTSSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To4MaskedFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To4MaskedFloat64x2 x mask) + // result: (VBROADCASTSDMasked256 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VBROADCASTSDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To4MaskedInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To4MaskedInt32x4 x mask) + // result: (VPBROADCASTDMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To4MaskedInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To4MaskedInt64x2 x mask) + // result: (VPBROADCASTQMasked256 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To4MaskedUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To4MaskedUint32x4 x mask) + // result: (VPBROADCASTDMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To4MaskedUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To4MaskedUint64x2 x mask) + // result: (VPBROADCASTQMasked256 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To64MaskedInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To64MaskedInt8x16 x mask) + // result: (VPBROADCASTBMasked512 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To64MaskedUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To64MaskedUint8x16 x mask) + // result: (VPBROADCASTBMasked512 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To8MaskedFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To8MaskedFloat32x4 x mask) + // result: (VBROADCASTSSMasked256 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VBROADCASTSSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To8MaskedFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To8MaskedFloat64x2 x mask) + // result: (VBROADCASTSDMasked512 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VBROADCASTSDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To8MaskedInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To8MaskedInt16x8 x mask) + // result: (VPBROADCASTWMasked128 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To8MaskedInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To8MaskedInt32x4 x mask) + // result: (VPBROADCASTDMasked256 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To8MaskedInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To8MaskedInt64x2 x mask) + // result: (VPBROADCASTQMasked512 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To8MaskedUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To8MaskedUint16x8 x mask) + // result: (VPBROADCASTWMasked128 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To8MaskedUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To8MaskedUint32x4 x mask) + // result: (VPBROADCASTDMasked256 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_Opbroadcast1To8MaskedUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (broadcast1To8MaskedUint64x2 x mask) + // result: (VPBROADCASTQMasked512 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPBROADCASTQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteBlockAMD64(b *Block) bool { + typ := &b.Func.Config.Types + switch b.Kind { + case BlockAMD64EQ: + // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) + // result: (UGE (BTL x y)) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) + // result: (UGE (BTQ x y)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (TESTLconst [c] x)) + // cond: isPowerOfTwo(uint32(c)) + // result: (UGE (BTLconst [int8(log32u(uint32(c)))] x)) + for b.Controls[0].Op == OpAMD64TESTLconst { + v_0 := b.Controls[0] + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(isPowerOfTwo(uint32(c))) { + break + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + // match: (EQ (TESTQconst [c] x)) + // cond: isPowerOfTwo(uint64(c)) + // result: (UGE (BTQconst [int8(log32u(uint32(c)))] x)) + for b.Controls[0].Op == OpAMD64TESTQconst { + v_0 := b.Controls[0] + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(isPowerOfTwo(uint64(c))) { + break + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + // match: (EQ (TESTQ (MOVQconst [c]) x)) + // cond: isPowerOfTwo(uint64(c)) + // result: (UGE (BTQconst [int8(log64u(uint64(c)))] x)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := auxIntToInt64(v_0_0.AuxInt) + x := v_0_1 + if !(isPowerOfTwo(uint64(c))) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) + v0.AddArg(x) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) + // cond: z1==z2 + // result: (UGE (BTQconst [63] x)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) + // cond: z1==z2 + // result: (UGE (BTQconst [0] x)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) + // cond: z1==z2 + // result: (UGE (BTLconst [0] x)) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) + // cond: z1==z2 + // result: (UGE (BTQconst [63] x)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + x := z1.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) + // cond: z1==z2 + // result: (UGE (BTLconst [31] x)) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + x := z1.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (InvertFlags cmp) yes no) + // result: (EQ cmp yes no) + for b.Controls[0].Op == OpAMD64InvertFlags { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64EQ, cmp) + return true + } + // match: (EQ (FlagEQ) yes no) + // result: (First yes no) + for b.Controls[0].Op == OpAMD64FlagEQ { + b.Reset(BlockFirst) + return true + } + // match: (EQ (FlagLT_ULT) yes no) + // result: (First no yes) + for b.Controls[0].Op == OpAMD64FlagLT_ULT { + b.Reset(BlockFirst) + b.swapSuccessors() + return true + } + // match: (EQ (FlagLT_UGT) yes no) + // result: (First no yes) + for b.Controls[0].Op == OpAMD64FlagLT_UGT { + b.Reset(BlockFirst) + b.swapSuccessors() + return true + } + // match: (EQ (FlagGT_ULT) yes no) + // result: (First no yes) + for b.Controls[0].Op == OpAMD64FlagGT_ULT { + b.Reset(BlockFirst) + b.swapSuccessors() + return true + } + // match: (EQ (FlagGT_UGT) yes no) + // result: (First no yes) + for b.Controls[0].Op == OpAMD64FlagGT_UGT { + b.Reset(BlockFirst) + b.swapSuccessors() + return true + } + // match: (EQ (TESTQ s:(Select0 blsr:(BLSRQ _)) s) yes no) + // result: (EQ (Select1 blsr) yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + s := v_0_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { + continue + } + v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + b.resetWithControl(BlockAMD64EQ, v0) + return true + } + break + } + // match: (EQ (TESTL s:(Select0 blsr:(BLSRL _)) s) yes no) + // result: (EQ (Select1 blsr) yes no) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + s := v_0_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRL || s != v_0_1 { + continue + } + v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + b.resetWithControl(BlockAMD64EQ, v0) + return true + } + break + } + // match: (EQ t:(TESTQ a:(ADDQconst [c] x) a)) + // cond: t.Uses == 1 && flagify(a) + // result: (EQ (Select1 a.Args[0])) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + a := t_0 + if a.Op != OpAMD64ADDQconst { + continue + } + if a != t_1 || !(t.Uses == 1 && flagify(a)) { + continue + } + v0 := b.NewValue0(t.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(a.Args[0]) + b.resetWithControl(BlockAMD64EQ, v0) + return true + } + break + } + // match: (EQ t:(TESTL a:(ADDLconst [c] x) a)) + // cond: t.Uses == 1 && flagify(a) + // result: (EQ (Select1 a.Args[0])) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + a := t_0 + if a.Op != OpAMD64ADDLconst { + continue + } + if a != t_1 || !(t.Uses == 1 && flagify(a)) { + continue + } + v0 := b.NewValue0(t.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(a.Args[0]) + b.resetWithControl(BlockAMD64EQ, v0) + return true + } + break + } + // match: (EQ (VPTEST x:(VPAND128 j k) y) yes no) + // cond: x == y && x.Uses == 2 + // result: (EQ (VPTEST j k) yes no) + for b.Controls[0].Op == OpAMD64VPTEST { + v_0 := b.Controls[0] + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPAND128 { + break + } + _ = x.Args[1] + x_0 := x.Args[0] + x_1 := x.Args[1] + for _i0 := 0; _i0 <= 1; _i0, x_0, x_1 = _i0+1, x_1, x_0 { + j := x_0 + k := x_1 + if !(x == y && x.Uses == 2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(j, k) + b.resetWithControl(BlockAMD64EQ, v0) + return true + } + break + } + // match: (EQ (VPTEST x:(VPAND256 j k) y) yes no) + // cond: x == y && x.Uses == 2 + // result: (EQ (VPTEST j k) yes no) + for b.Controls[0].Op == OpAMD64VPTEST { + v_0 := b.Controls[0] + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPAND256 { + break + } + _ = x.Args[1] + x_0 := x.Args[0] + x_1 := x.Args[1] + for _i0 := 0; _i0 <= 1; _i0, x_0, x_1 = _i0+1, x_1, x_0 { + j := x_0 + k := x_1 + if !(x == y && x.Uses == 2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(j, k) + b.resetWithControl(BlockAMD64EQ, v0) + return true + } + break + } + // match: (EQ (VPTEST x:(VPANDD512 j k) y) yes no) + // cond: x == y && x.Uses == 2 + // result: (EQ (VPTEST j k) yes no) + for b.Controls[0].Op == OpAMD64VPTEST { + v_0 := b.Controls[0] + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDD512 { + break + } + _ = x.Args[1] + x_0 := x.Args[0] + x_1 := x.Args[1] + for _i0 := 0; _i0 <= 1; _i0, x_0, x_1 = _i0+1, x_1, x_0 { + j := x_0 + k := x_1 + if !(x == y && x.Uses == 2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(j, k) + b.resetWithControl(BlockAMD64EQ, v0) + return true + } + break + } + // match: (EQ (VPTEST x:(VPANDQ512 j k) y) yes no) + // cond: x == y && x.Uses == 2 + // result: (EQ (VPTEST j k) yes no) + for b.Controls[0].Op == OpAMD64VPTEST { + v_0 := b.Controls[0] + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDQ512 { + break + } + _ = x.Args[1] + x_0 := x.Args[0] + x_1 := x.Args[1] + for _i0 := 0; _i0 <= 1; _i0, x_0, x_1 = _i0+1, x_1, x_0 { + j := x_0 + k := x_1 + if !(x == y && x.Uses == 2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(j, k) + b.resetWithControl(BlockAMD64EQ, v0) + return true + } + break + } + // match: (EQ (VPTEST x:(VPANDN128 j k) y) yes no) + // cond: x == y && x.Uses == 2 + // result: (ULT (VPTEST k j) yes no) + for b.Controls[0].Op == OpAMD64VPTEST { + v_0 := b.Controls[0] + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDN128 { + break + } + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v0 := b.NewValue0(v_0.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(k, j) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + // match: (EQ (VPTEST x:(VPANDN256 j k) y) yes no) + // cond: x == y && x.Uses == 2 + // result: (ULT (VPTEST k j) yes no) + for b.Controls[0].Op == OpAMD64VPTEST { + v_0 := b.Controls[0] + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDN256 { + break + } + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v0 := b.NewValue0(v_0.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(k, j) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + // match: (EQ (VPTEST x:(VPANDND512 j k) y) yes no) + // cond: x == y && x.Uses == 2 + // result: (ULT (VPTEST k j) yes no) + for b.Controls[0].Op == OpAMD64VPTEST { + v_0 := b.Controls[0] + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDND512 { + break + } + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v0 := b.NewValue0(v_0.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(k, j) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + // match: (EQ (VPTEST x:(VPANDNQ512 j k) y) yes no) + // cond: x == y && x.Uses == 2 + // result: (ULT (VPTEST k j) yes no) + for b.Controls[0].Op == OpAMD64VPTEST { + v_0 := b.Controls[0] + y := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpAMD64VPANDNQ512 { + break + } + k := x.Args[1] + j := x.Args[0] + if !(x == y && x.Uses == 2) { + break + } + v0 := b.NewValue0(v_0.Pos, OpAMD64VPTEST, types.TypeFlags) + v0.AddArg2(k, j) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + // match: (EQ t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x) yes no) + // cond: t.Block == s.Block + // result: (NE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64NE, flags) + return true + } + break + } + // match: (EQ t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (EQ flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64EQ, flags) + return true + } + break + } + // match: (EQ t:(TESTQ x:(MOVBQZX s:(SETL flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GE, flags) + return true + } + break + } + // match: (EQ t:(TESTQ x:(MOVBQZX s:(SETG flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LE, flags) + return true + } + break + } + // match: (EQ t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GT flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GT, flags) + return true + } + break + } + // match: (EQ t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LT flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LT, flags) + return true + } + break + } + // match: (EQ t:(TESTQ x:(MOVBQZX s:(SETA flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULE, flags) + return true + } + break + } + // match: (EQ t:(TESTQ x:(MOVBQZX s:(SETB flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGE, flags) + return true + } + break + } + // match: (EQ t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULT flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULT, flags) + return true + } + break + } + // match: (EQ t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGT, flags) + return true + } + break + } + // match: (EQ t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x) yes no) + // cond: t.Block == s.Block + // result: (NE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64NE, flags) + return true + } + break + } + // match: (EQ t:(TESTL x:(MOVBQZX s:(SETNE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (EQ flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64EQ, flags) + return true + } + break + } + // match: (EQ t:(TESTL x:(MOVBQZX s:(SETL flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GE, flags) + return true + } + break + } + // match: (EQ t:(TESTL x:(MOVBQZX s:(SETG flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LE, flags) + return true + } + break + } + // match: (EQ t:(TESTL x:(MOVBQZX s:(SETLE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GT flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GT, flags) + return true + } + break + } + // match: (EQ t:(TESTL x:(MOVBQZX s:(SETGE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LT flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LT, flags) + return true + } + break + } + // match: (EQ t:(TESTL x:(MOVBQZX s:(SETA flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULE, flags) + return true + } + break + } + // match: (EQ t:(TESTL x:(MOVBQZX s:(SETB flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGE, flags) + return true + } + break + } + // match: (EQ t:(TESTL x:(MOVBQZX s:(SETAE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULT flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULT, flags) + return true + } + break + } + // match: (EQ t:(TESTL x:(MOVBQZX s:(SETBE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGT, flags) + return true + } + break + } + // match: (EQ t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x) yes no) + // cond: t.Block == s.Block + // result: (NE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64NE, flags) + return true + } + break + } + // match: (EQ t:(TESTW x:(MOVBQZX s:(SETNE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (EQ flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64EQ, flags) + return true + } + break + } + // match: (EQ t:(TESTW x:(MOVBQZX s:(SETL flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GE, flags) + return true + } + break + } + // match: (EQ t:(TESTW x:(MOVBQZX s:(SETG flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LE, flags) + return true + } + break + } + // match: (EQ t:(TESTW x:(MOVBQZX s:(SETLE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GT flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GT, flags) + return true + } + break + } + // match: (EQ t:(TESTW x:(MOVBQZX s:(SETGE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LT flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LT, flags) + return true + } + break + } + // match: (EQ t:(TESTW x:(MOVBQZX s:(SETA flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULE, flags) + return true + } + break + } + // match: (EQ t:(TESTW x:(MOVBQZX s:(SETB flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { + s := x.Args[0] + if s.Op != OpAMD64SETB { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - b.resetWithControl(BlockAMD64UGE, v0) + b.resetWithControl(BlockAMD64UGE, flags) return true } break } - // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) - // cond: z1==z2 - // result: (UGE (BTQconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + // match: (EQ t:(TESTW x:(MOVBQZX s:(SETAE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULT flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + s := x.Args[0] + if s.Op != OpAMD64SETAE { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - b.resetWithControl(BlockAMD64UGE, v0) + b.resetWithControl(BlockAMD64ULT, flags) return true } break } - // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) - // cond: z1==z2 - // result: (UGE (BTLconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + // match: (EQ t:(TESTW x:(MOVBQZX s:(SETBE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { + s := x.Args[0] + if s.Op != OpAMD64SETBE { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - b.resetWithControl(BlockAMD64UGE, v0) + b.resetWithControl(BlockAMD64UGT, flags) return true } break } - // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) - // cond: z1==z2 - // result: (UGE (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + // match: (EQ t:(TESTB s:(SETEQ flags) s) yes no) + // cond: t.Block == s.Block + // result: (NE flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQ { continue } - x := z1.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - b.resetWithControl(BlockAMD64UGE, v0) + b.resetWithControl(BlockAMD64NE, flags) return true } break } - // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) - // cond: z1==z2 - // result: (UGE (BTLconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + // match: (EQ t:(TESTB s:(SETNE flags) s) yes no) + // cond: t.Block == s.Block + // result: (EQ flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNE { continue } - x := z1.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - b.resetWithControl(BlockAMD64UGE, v0) + b.resetWithControl(BlockAMD64EQ, flags) return true } break } - // match: (EQ (InvertFlags cmp) yes no) - // result: (EQ cmp yes no) + // match: (EQ t:(TESTB s:(SETL flags) s) yes no) + // cond: t.Block == s.Block + // result: (GE flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GE, flags) + return true + } + break + } + // match: (EQ t:(TESTB s:(SETG flags) s) yes no) + // cond: t.Block == s.Block + // result: (LE flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LE, flags) + return true + } + break + } + // match: (EQ t:(TESTB s:(SETLE flags) s) yes no) + // cond: t.Block == s.Block + // result: (GT flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GT, flags) + return true + } + break + } + // match: (EQ t:(TESTB s:(SETGE flags) s) yes no) + // cond: t.Block == s.Block + // result: (LT flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LT, flags) + return true + } + break + } + // match: (EQ t:(TESTB s:(SETA flags) s) yes no) + // cond: t.Block == s.Block + // result: (ULE flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULE, flags) + return true + } + break + } + // match: (EQ t:(TESTB s:(SETB flags) s) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGE, flags) + return true + } + break + } + // match: (EQ t:(TESTB s:(SETAE flags) s) yes no) + // cond: t.Block == s.Block + // result: (ULT flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULT, flags) + return true + } + break + } + // match: (EQ t:(TESTB s:(SETBE flags) s) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGT, flags) + return true + } + break + } + case BlockAMD64GE: + // match: (GE c:(CMPQconst [128] z) yes no) + // cond: c.Uses == 1 + // result: (GT (CMPQconst [127] z) yes no) + for b.Controls[0].Op == OpAMD64CMPQconst { + c := b.Controls[0] + if auxIntToInt32(c.AuxInt) != 128 { + break + } + z := c.Args[0] + if !(c.Uses == 1) { + break + } + v0 := b.NewValue0(c.Pos, OpAMD64CMPQconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(127) + v0.AddArg(z) + b.resetWithControl(BlockAMD64GT, v0) + return true + } + // match: (GE c:(CMPLconst [128] z) yes no) + // cond: c.Uses == 1 + // result: (GT (CMPLconst [127] z) yes no) + for b.Controls[0].Op == OpAMD64CMPLconst { + c := b.Controls[0] + if auxIntToInt32(c.AuxInt) != 128 { + break + } + z := c.Args[0] + if !(c.Uses == 1) { + break + } + v0 := b.NewValue0(c.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(127) + v0.AddArg(z) + b.resetWithControl(BlockAMD64GT, v0) + return true + } + // match: (GE (InvertFlags cmp) yes no) + // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] - b.resetWithControl(BlockAMD64EQ, cmp) + b.resetWithControl(BlockAMD64LE, cmp) return true } - // match: (EQ (FlagEQ) yes no) + // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } - // match: (EQ (FlagLT_ULT) yes no) + // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } - // match: (EQ (FlagLT_UGT) yes no) + // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } - // match: (EQ (FlagGT_ULT) yes no) - // result: (First no yes) + // match: (GE (FlagGT_ULT) yes no) + // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { + b.Reset(BlockFirst) + return true + } + // match: (GE (FlagGT_UGT) yes no) + // result: (First yes no) + for b.Controls[0].Op == OpAMD64FlagGT_UGT { + b.Reset(BlockFirst) + return true + } + case BlockAMD64GT: + // match: (GT (InvertFlags cmp) yes no) + // result: (LT cmp yes no) + for b.Controls[0].Op == OpAMD64InvertFlags { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64LT, cmp) + return true + } + // match: (GT (FlagEQ) yes no) + // result: (First no yes) + for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } - // match: (EQ (FlagGT_UGT) yes no) + // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) - for b.Controls[0].Op == OpAMD64FlagGT_UGT { + for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } - // match: (EQ (TESTQ s:(Select0 blsr:(BLSRQ _)) s) yes no) - // result: (EQ (Select1 blsr) yes no) - for b.Controls[0].Op == OpAMD64TESTQ { + // match: (GT (FlagLT_UGT) yes no) + // result: (First no yes) + for b.Controls[0].Op == OpAMD64FlagLT_UGT { + b.Reset(BlockFirst) + b.swapSuccessors() + return true + } + // match: (GT (FlagGT_ULT) yes no) + // result: (First yes no) + for b.Controls[0].Op == OpAMD64FlagGT_ULT { + b.Reset(BlockFirst) + return true + } + // match: (GT (FlagGT_UGT) yes no) + // result: (First yes no) + for b.Controls[0].Op == OpAMD64FlagGT_UGT { + b.Reset(BlockFirst) + return true + } + case BlockIf: + // match: (If (SETL cmp) yes no) + // result: (LT cmp yes no) + for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - s := v_0_0 - if s.Op != OpSelect0 { - continue - } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { - continue - } - v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - b.resetWithControl(BlockAMD64EQ, v0) - return true - } - break + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64LT, cmp) + return true } - // match: (EQ (TESTL s:(Select0 blsr:(BLSRL _)) s) yes no) - // result: (EQ (Select1 blsr) yes no) - for b.Controls[0].Op == OpAMD64TESTL { + // match: (If (SETLE cmp) yes no) + // result: (LE cmp yes no) + for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - s := v_0_0 - if s.Op != OpSelect0 { - continue - } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRL || s != v_0_1 { - continue - } - v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - b.resetWithControl(BlockAMD64EQ, v0) - return true - } - break + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64LE, cmp) + return true + } + // match: (If (SETG cmp) yes no) + // result: (GT cmp yes no) + for b.Controls[0].Op == OpAMD64SETG { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64GT, cmp) + return true + } + // match: (If (SETGE cmp) yes no) + // result: (GE cmp yes no) + for b.Controls[0].Op == OpAMD64SETGE { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64GE, cmp) + return true + } + // match: (If (SETEQ cmp) yes no) + // result: (EQ cmp yes no) + for b.Controls[0].Op == OpAMD64SETEQ { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64EQ, cmp) + return true + } + // match: (If (SETNE cmp) yes no) + // result: (NE cmp yes no) + for b.Controls[0].Op == OpAMD64SETNE { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64NE, cmp) + return true + } + // match: (If (SETB cmp) yes no) + // result: (ULT cmp yes no) + for b.Controls[0].Op == OpAMD64SETB { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64ULT, cmp) + return true + } + // match: (If (SETBE cmp) yes no) + // result: (ULE cmp yes no) + for b.Controls[0].Op == OpAMD64SETBE { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64ULE, cmp) + return true + } + // match: (If (SETA cmp) yes no) + // result: (UGT cmp yes no) + for b.Controls[0].Op == OpAMD64SETA { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64UGT, cmp) + return true + } + // match: (If (SETAE cmp) yes no) + // result: (UGE cmp yes no) + for b.Controls[0].Op == OpAMD64SETAE { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64UGE, cmp) + return true + } + // match: (If (SETO cmp) yes no) + // result: (OS cmp yes no) + for b.Controls[0].Op == OpAMD64SETO { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64OS, cmp) + return true + } + // match: (If (SETGF cmp) yes no) + // result: (UGT cmp yes no) + for b.Controls[0].Op == OpAMD64SETGF { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64UGT, cmp) + return true + } + // match: (If (SETGEF cmp) yes no) + // result: (UGE cmp yes no) + for b.Controls[0].Op == OpAMD64SETGEF { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64UGE, cmp) + return true + } + // match: (If (SETEQF cmp) yes no) + // result: (EQF cmp yes no) + for b.Controls[0].Op == OpAMD64SETEQF { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64EQF, cmp) + return true + } + // match: (If (SETNEF cmp) yes no) + // result: (NEF cmp yes no) + for b.Controls[0].Op == OpAMD64SETNEF { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64NEF, cmp) + return true + } + // match: (If cond yes no) + // result: (NE (TESTB cond cond) yes no) + for { + cond := b.Controls[0] + v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) + v0.AddArg2(cond, cond) + b.resetWithControl(BlockAMD64NE, v0) + return true + } + case BlockJumpTable: + // match: (JumpTable idx) + // result: (JUMPTABLE {makeJumpTableSym(b)} idx (LEAQ {makeJumpTableSym(b)} (SB))) + for { + idx := b.Controls[0] + v0 := b.NewValue0(b.Pos, OpAMD64LEAQ, typ.Uintptr) + v0.Aux = symToAux(makeJumpTableSym(b)) + v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) + v0.AddArg(v1) + b.resetWithControl2(BlockAMD64JUMPTABLE, idx, v0) + b.Aux = symToAux(makeJumpTableSym(b)) + return true + } + case BlockAMD64LE: + // match: (LE (InvertFlags cmp) yes no) + // result: (GE cmp yes no) + for b.Controls[0].Op == OpAMD64InvertFlags { + v_0 := b.Controls[0] + cmp := v_0.Args[0] + b.resetWithControl(BlockAMD64GE, cmp) + return true } - // match: (EQ t:(TESTQ a:(ADDQconst [c] x) a)) - // cond: t.Uses == 1 && flagify(a) - // result: (EQ (Select1 a.Args[0])) - for b.Controls[0].Op == OpAMD64TESTQ { - t := b.Controls[0] - _ = t.Args[1] - t_0 := t.Args[0] - t_1 := t.Args[1] - for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { - a := t_0 - if a.Op != OpAMD64ADDQconst { - continue - } - if a != t_1 || !(t.Uses == 1 && flagify(a)) { - continue - } - v0 := b.NewValue0(t.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(a.Args[0]) - b.resetWithControl(BlockAMD64EQ, v0) - return true - } - break + // match: (LE (FlagEQ) yes no) + // result: (First yes no) + for b.Controls[0].Op == OpAMD64FlagEQ { + b.Reset(BlockFirst) + return true } - // match: (EQ t:(TESTL a:(ADDLconst [c] x) a)) - // cond: t.Uses == 1 && flagify(a) - // result: (EQ (Select1 a.Args[0])) - for b.Controls[0].Op == OpAMD64TESTL { - t := b.Controls[0] - _ = t.Args[1] - t_0 := t.Args[0] - t_1 := t.Args[1] - for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { - a := t_0 - if a.Op != OpAMD64ADDLconst { - continue - } - if a != t_1 || !(t.Uses == 1 && flagify(a)) { - continue - } - v0 := b.NewValue0(t.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(a.Args[0]) - b.resetWithControl(BlockAMD64EQ, v0) - return true - } - break + // match: (LE (FlagLT_ULT) yes no) + // result: (First yes no) + for b.Controls[0].Op == OpAMD64FlagLT_ULT { + b.Reset(BlockFirst) + return true } - case BlockAMD64GE: - // match: (GE c:(CMPQconst [128] z) yes no) + // match: (LE (FlagLT_UGT) yes no) + // result: (First yes no) + for b.Controls[0].Op == OpAMD64FlagLT_UGT { + b.Reset(BlockFirst) + return true + } + // match: (LE (FlagGT_ULT) yes no) + // result: (First no yes) + for b.Controls[0].Op == OpAMD64FlagGT_ULT { + b.Reset(BlockFirst) + b.swapSuccessors() + return true + } + // match: (LE (FlagGT_UGT) yes no) + // result: (First no yes) + for b.Controls[0].Op == OpAMD64FlagGT_UGT { + b.Reset(BlockFirst) + b.swapSuccessors() + return true + } + case BlockAMD64LT: + // match: (LT c:(CMPQconst [128] z) yes no) // cond: c.Uses == 1 - // result: (GT (CMPQconst [127] z) yes no) + // result: (LE (CMPQconst [127] z) yes no) for b.Controls[0].Op == OpAMD64CMPQconst { c := b.Controls[0] if auxIntToInt32(c.AuxInt) != 128 { @@ -30628,12 +107687,12 @@ func rewriteBlockAMD64(b *Block) bool { v0 := b.NewValue0(c.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(127) v0.AddArg(z) - b.resetWithControl(BlockAMD64GT, v0) + b.resetWithControl(BlockAMD64LE, v0) return true } - // match: (GE c:(CMPLconst [128] z) yes no) + // match: (LT c:(CMPLconst [128] z) yes no) // cond: c.Uses == 1 - // result: (GT (CMPLconst [127] z) yes no) + // result: (LE (CMPLconst [127] z) yes no) for b.Controls[0].Op == OpAMD64CMPLconst { c := b.Controls[0] if auxIntToInt32(c.AuxInt) != 128 { @@ -30646,1013 +107705,2110 @@ func rewriteBlockAMD64(b *Block) bool { v0 := b.NewValue0(c.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(127) v0.AddArg(z) - b.resetWithControl(BlockAMD64GT, v0) + b.resetWithControl(BlockAMD64LE, v0) return true } - // match: (GE (InvertFlags cmp) yes no) - // result: (LE cmp yes no) + // match: (LT (InvertFlags cmp) yes no) + // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] - b.resetWithControl(BlockAMD64LE, cmp) - return true - } - // match: (GE (FlagEQ) yes no) - // result: (First yes no) - for b.Controls[0].Op == OpAMD64FlagEQ { - b.Reset(BlockFirst) - return true - } - // match: (GE (FlagLT_ULT) yes no) - // result: (First no yes) - for b.Controls[0].Op == OpAMD64FlagLT_ULT { - b.Reset(BlockFirst) - b.swapSuccessors() + b.resetWithControl(BlockAMD64GT, cmp) return true } - // match: (GE (FlagLT_UGT) yes no) + // match: (LT (FlagEQ) yes no) // result: (First no yes) - for b.Controls[0].Op == OpAMD64FlagLT_UGT { + for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } - // match: (GE (FlagGT_ULT) yes no) + // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) - for b.Controls[0].Op == OpAMD64FlagGT_ULT { + for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } - // match: (GE (FlagGT_UGT) yes no) + // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) - for b.Controls[0].Op == OpAMD64FlagGT_UGT { - b.Reset(BlockFirst) - return true - } - case BlockAMD64GT: - // match: (GT (InvertFlags cmp) yes no) - // result: (LT cmp yes no) - for b.Controls[0].Op == OpAMD64InvertFlags { - v_0 := b.Controls[0] - cmp := v_0.Args[0] - b.resetWithControl(BlockAMD64LT, cmp) - return true - } - // match: (GT (FlagEQ) yes no) - // result: (First no yes) - for b.Controls[0].Op == OpAMD64FlagEQ { + for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) - b.swapSuccessors() return true } - // match: (GT (FlagLT_ULT) yes no) + // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) - for b.Controls[0].Op == OpAMD64FlagLT_ULT { + for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } - // match: (GT (FlagLT_UGT) yes no) + // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) - for b.Controls[0].Op == OpAMD64FlagLT_UGT { - b.Reset(BlockFirst) - b.swapSuccessors() - return true - } - // match: (GT (FlagGT_ULT) yes no) - // result: (First yes no) - for b.Controls[0].Op == OpAMD64FlagGT_ULT { - b.Reset(BlockFirst) - return true - } - // match: (GT (FlagGT_UGT) yes no) - // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) + b.swapSuccessors() return true } - case BlockIf: - // match: (If (SETL cmp) yes no) + case BlockAMD64NE: + // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) - for b.Controls[0].Op == OpAMD64SETL { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETL { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64LT, cmp) return true } - // match: (If (SETLE cmp) yes no) + // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) - for b.Controls[0].Op == OpAMD64SETLE { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETLE { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64LE, cmp) return true } - // match: (If (SETG cmp) yes no) + // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) - for b.Controls[0].Op == OpAMD64SETG { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETG { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64GT, cmp) return true } - // match: (If (SETGE cmp) yes no) + // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) - for b.Controls[0].Op == OpAMD64SETGE { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETGE { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64GE, cmp) return true } - // match: (If (SETEQ cmp) yes no) + // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) - for b.Controls[0].Op == OpAMD64SETEQ { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETEQ { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64EQ, cmp) return true } - // match: (If (SETNE cmp) yes no) + // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) - for b.Controls[0].Op == OpAMD64SETNE { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETNE { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64NE, cmp) return true } - // match: (If (SETB cmp) yes no) + // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) - for b.Controls[0].Op == OpAMD64SETB { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETB { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64ULT, cmp) return true } - // match: (If (SETBE cmp) yes no) + // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) - for b.Controls[0].Op == OpAMD64SETBE { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETBE { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64ULE, cmp) return true } - // match: (If (SETA cmp) yes no) - // result: (UGT cmp yes no) - for b.Controls[0].Op == OpAMD64SETA { + // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) + // result: (UGT cmp yes no) + for b.Controls[0].Op == OpAMD64TESTB { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETA { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { + break + } + b.resetWithControl(BlockAMD64UGT, cmp) + return true + } + // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) + // result: (UGE cmp yes no) + for b.Controls[0].Op == OpAMD64TESTB { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETAE { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { + break + } + b.resetWithControl(BlockAMD64UGE, cmp) + return true + } + // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) + // result: (OS cmp yes no) + for b.Controls[0].Op == OpAMD64TESTB { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETO { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { + break + } + b.resetWithControl(BlockAMD64OS, cmp) + return true + } + // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) + // result: (ULT (BTL x y)) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break + } + // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) + // result: (ULT (BTQ x y)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break + } + // match: (NE (TESTLconst [c] x)) + // cond: isPowerOfTwo(uint32(c)) + // result: (ULT (BTLconst [int8(log32u(uint32(c)))] x)) + for b.Controls[0].Op == OpAMD64TESTLconst { + v_0 := b.Controls[0] + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(isPowerOfTwo(uint32(c))) { + break + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + // match: (NE (TESTQconst [c] x)) + // cond: isPowerOfTwo(uint64(c)) + // result: (ULT (BTQconst [int8(log32u(uint32(c)))] x)) + for b.Controls[0].Op == OpAMD64TESTQconst { + v_0 := b.Controls[0] + c := auxIntToInt32(v_0.AuxInt) + x := v_0.Args[0] + if !(isPowerOfTwo(uint64(c))) { + break + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) + v0.AddArg(x) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + // match: (NE (TESTQ (MOVQconst [c]) x)) + // cond: isPowerOfTwo(uint64(c)) + // result: (ULT (BTQconst [int8(log64u(uint64(c)))] x)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := auxIntToInt64(v_0_0.AuxInt) + x := v_0_1 + if !(isPowerOfTwo(uint64(c))) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) + v0.AddArg(x) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break + } + // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) + // cond: z1==z2 + // result: (ULT (BTQconst [63] x)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break + } + // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) + // cond: z1==z2 + // result: (ULT (BTQconst [31] x)) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break + } + // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) + // cond: z1==z2 + // result: (ULT (BTQconst [0] x)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break + } + // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) + // cond: z1==z2 + // result: (ULT (BTLconst [0] x)) + for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - cmp := v_0.Args[0] - b.resetWithControl(BlockAMD64UGT, cmp) - return true + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg(x) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break } - // match: (If (SETAE cmp) yes no) - // result: (UGE cmp yes no) - for b.Controls[0].Op == OpAMD64SETAE { + // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) + // cond: z1==z2 + // result: (ULT (BTQconst [63] x)) + for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - cmp := v_0.Args[0] - b.resetWithControl(BlockAMD64UGE, cmp) - return true + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + continue + } + x := z1.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(63) + v0.AddArg(x) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break } - // match: (If (SETO cmp) yes no) - // result: (OS cmp yes no) - for b.Controls[0].Op == OpAMD64SETO { + // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) + // cond: z1==z2 + // result: (ULT (BTLconst [31] x)) + for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - cmp := v_0.Args[0] - b.resetWithControl(BlockAMD64OS, cmp) - return true + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + z1 := v_0_0 + if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + continue + } + x := z1.Args[0] + z2 := v_0_1 + if !(z1 == z2) { + continue + } + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = int8ToAuxInt(31) + v0.AddArg(x) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break } - // match: (If (SETGF cmp) yes no) + // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) - for b.Controls[0].Op == OpAMD64SETGF { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETGF { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64UGT, cmp) return true } - // match: (If (SETGEF cmp) yes no) + // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) - for b.Controls[0].Op == OpAMD64SETGEF { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETGEF { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64UGE, cmp) return true } - // match: (If (SETEQF cmp) yes no) + // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) - for b.Controls[0].Op == OpAMD64SETEQF { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETEQF { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64EQF, cmp) return true } - // match: (If (SETNEF cmp) yes no) + // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) - for b.Controls[0].Op == OpAMD64SETNEF { + for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] - cmp := v_0.Args[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SETNEF { + break + } + cmp := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { + break + } b.resetWithControl(BlockAMD64NEF, cmp) return true } - // match: (If cond yes no) - // result: (NE (TESTB cond cond) yes no) - for { - cond := b.Controls[0] - v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) - v0.AddArg2(cond, cond) - b.resetWithControl(BlockAMD64NE, v0) - return true - } - case BlockJumpTable: - // match: (JumpTable idx) - // result: (JUMPTABLE {makeJumpTableSym(b)} idx (LEAQ {makeJumpTableSym(b)} (SB))) - for { - idx := b.Controls[0] - v0 := b.NewValue0(b.Pos, OpAMD64LEAQ, typ.Uintptr) - v0.Aux = symToAux(makeJumpTableSym(b)) - v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) - v0.AddArg(v1) - b.resetWithControl2(BlockAMD64JUMPTABLE, idx, v0) - b.Aux = symToAux(makeJumpTableSym(b)) - return true - } - case BlockAMD64LE: - // match: (LE (InvertFlags cmp) yes no) - // result: (GE cmp yes no) + // match: (NE (InvertFlags cmp) yes no) + // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] - b.resetWithControl(BlockAMD64GE, cmp) + b.resetWithControl(BlockAMD64NE, cmp) return true } - // match: (LE (FlagEQ) yes no) - // result: (First yes no) + // match: (NE (FlagEQ) yes no) + // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) + b.swapSuccessors() return true } - // match: (LE (FlagLT_ULT) yes no) + // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } - // match: (LE (FlagLT_UGT) yes no) + // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } - // match: (LE (FlagGT_ULT) yes no) - // result: (First no yes) + // match: (NE (FlagGT_ULT) yes no) + // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) - b.swapSuccessors() return true } - // match: (LE (FlagGT_UGT) yes no) - // result: (First no yes) + // match: (NE (FlagGT_UGT) yes no) + // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) - b.swapSuccessors() return true } - case BlockAMD64LT: - // match: (LT c:(CMPQconst [128] z) yes no) - // cond: c.Uses == 1 - // result: (LE (CMPQconst [127] z) yes no) - for b.Controls[0].Op == OpAMD64CMPQconst { - c := b.Controls[0] - if auxIntToInt32(c.AuxInt) != 128 { - break + // match: (NE (TESTQ s:(Select0 blsr:(BLSRQ _)) s) yes no) + // result: (NE (Select1 blsr) yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + s := v_0_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { + continue + } + v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + b.resetWithControl(BlockAMD64NE, v0) + return true } - z := c.Args[0] - if !(c.Uses == 1) { - break + break + } + // match: (NE (TESTL s:(Select0 blsr:(BLSRL _)) s) yes no) + // result: (NE (Select1 blsr) yes no) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + s := v_0_0 + if s.Op != OpSelect0 { + continue + } + blsr := s.Args[0] + if blsr.Op != OpAMD64BLSRL || s != v_0_1 { + continue + } + v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(blsr) + b.resetWithControl(BlockAMD64NE, v0) + return true } - v0 := b.NewValue0(c.Pos, OpAMD64CMPQconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(z) - b.resetWithControl(BlockAMD64LE, v0) - return true + break } - // match: (LT c:(CMPLconst [128] z) yes no) - // cond: c.Uses == 1 - // result: (LE (CMPLconst [127] z) yes no) - for b.Controls[0].Op == OpAMD64CMPLconst { - c := b.Controls[0] - if auxIntToInt32(c.AuxInt) != 128 { - break + // match: (NE t:(TESTQ a:(ADDQconst [c] x) a)) + // cond: t.Uses == 1 && flagify(a) + // result: (NE (Select1 a.Args[0])) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + a := t_0 + if a.Op != OpAMD64ADDQconst { + continue + } + if a != t_1 || !(t.Uses == 1 && flagify(a)) { + continue + } + v0 := b.NewValue0(t.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(a.Args[0]) + b.resetWithControl(BlockAMD64NE, v0) + return true } - z := c.Args[0] - if !(c.Uses == 1) { - break + break + } + // match: (NE t:(TESTL a:(ADDLconst [c] x) a)) + // cond: t.Uses == 1 && flagify(a) + // result: (NE (Select1 a.Args[0])) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + a := t_0 + if a.Op != OpAMD64ADDLconst { + continue + } + if a != t_1 || !(t.Uses == 1 && flagify(a)) { + continue + } + v0 := b.NewValue0(t.Pos, OpSelect1, types.TypeFlags) + v0.AddArg(a.Args[0]) + b.resetWithControl(BlockAMD64NE, v0) + return true } - v0 := b.NewValue0(c.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(127) - v0.AddArg(z) - b.resetWithControl(BlockAMD64LE, v0) - return true + break } - // match: (LT (InvertFlags cmp) yes no) - // result: (GT cmp yes no) - for b.Controls[0].Op == OpAMD64InvertFlags { - v_0 := b.Controls[0] - cmp := v_0.Args[0] - b.resetWithControl(BlockAMD64GT, cmp) - return true + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x) yes no) + // cond: t.Block == s.Block + // result: (EQ flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64EQ, flags) + return true + } + break } - // match: (LT (FlagEQ) yes no) - // result: (First no yes) - for b.Controls[0].Op == OpAMD64FlagEQ { - b.Reset(BlockFirst) - b.swapSuccessors() - return true + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (NE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64NE, flags) + return true + } + break } - // match: (LT (FlagLT_ULT) yes no) - // result: (First yes no) - for b.Controls[0].Op == OpAMD64FlagLT_ULT { - b.Reset(BlockFirst) - return true + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETL flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LT flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LT, flags) + return true + } + break } - // match: (LT (FlagLT_UGT) yes no) - // result: (First yes no) - for b.Controls[0].Op == OpAMD64FlagLT_UGT { - b.Reset(BlockFirst) - return true + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETG flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GT flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GT, flags) + return true + } + break } - // match: (LT (FlagGT_ULT) yes no) - // result: (First no yes) - for b.Controls[0].Op == OpAMD64FlagGT_ULT { - b.Reset(BlockFirst) - b.swapSuccessors() - return true + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LE, flags) + return true + } + break + } + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GE, flags) + return true + } + break + } + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETA flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGT, flags) + return true + } + break + } + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETB flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULT flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULT, flags) + return true + } + break + } + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGE, flags) + return true + } + break + } + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULE, flags) + return true + } + break } - // match: (LT (FlagGT_UGT) yes no) - // result: (First no yes) - for b.Controls[0].Op == OpAMD64FlagGT_UGT { - b.Reset(BlockFirst) - b.swapSuccessors() - return true + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETEQF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (EQF flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64EQF, flags) + return true + } + break } - case BlockAMD64NE: - // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) - // result: (LT cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETL { - break + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETNEF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (NEF flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64NEF, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETGF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGT, flags) + return true } - b.resetWithControl(BlockAMD64LT, cmp) - return true + break } - // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) - // result: (LE cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETLE { - break + // match: (NE t:(TESTQ x:(MOVBQZX s:(SETGEF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTQ { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGE, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x) yes no) + // cond: t.Block == s.Block + // result: (EQ flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64EQ, flags) + return true } - b.resetWithControl(BlockAMD64LE, cmp) - return true + break } - // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) - // result: (GT cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETG { - break + // match: (NE t:(TESTL x:(MOVBQZX s:(SETNE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (NE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64NE, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTL x:(MOVBQZX s:(SETL flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LT flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LT, flags) + return true } - b.resetWithControl(BlockAMD64GT, cmp) - return true + break } - // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) - // result: (GE cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETGE { - break + // match: (NE t:(TESTL x:(MOVBQZX s:(SETG flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GT flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GT, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTL x:(MOVBQZX s:(SETLE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LE, flags) + return true } - b.resetWithControl(BlockAMD64GE, cmp) - return true + break } - // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) - // result: (EQ cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETEQ { - break + // match: (NE t:(TESTL x:(MOVBQZX s:(SETGE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GE, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTL x:(MOVBQZX s:(SETA flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGT, flags) + return true } - b.resetWithControl(BlockAMD64EQ, cmp) - return true + break } - // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) - // result: (NE cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETNE { - break + // match: (NE t:(TESTL x:(MOVBQZX s:(SETB flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULT flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULT, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTL x:(MOVBQZX s:(SETAE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGE, flags) + return true } - b.resetWithControl(BlockAMD64NE, cmp) - return true + break } - // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) - // result: (ULT cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETB { - break + // match: (NE t:(TESTL x:(MOVBQZX s:(SETBE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULE, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTL x:(MOVBQZX s:(SETEQF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (EQF flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64EQF, flags) + return true } - b.resetWithControl(BlockAMD64ULT, cmp) - return true + break } - // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) - // result: (ULE cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETBE { - break + // match: (NE t:(TESTL x:(MOVBQZX s:(SETNEF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (NEF flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64NEF, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTL x:(MOVBQZX s:(SETGF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGT, flags) + return true } - b.resetWithControl(BlockAMD64ULE, cmp) - return true + break } - // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) - // result: (UGT cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETA { - break + // match: (NE t:(TESTL x:(MOVBQZX s:(SETGEF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTL { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETGEF { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGE, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x) yes no) + // cond: t.Block == s.Block + // result: (EQ flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETEQ { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64EQ, flags) + return true } - b.resetWithControl(BlockAMD64UGT, cmp) - return true + break } - // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) - // result: (UGE cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETAE { - break + // match: (NE t:(TESTW x:(MOVBQZX s:(SETNE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (NE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETNE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64NE, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTW x:(MOVBQZX s:(SETL flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LT flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LT, flags) + return true } - b.resetWithControl(BlockAMD64UGE, cmp) - return true + break } - // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) - // result: (OS cmp yes no) - for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETO { - break + // match: (NE t:(TESTW x:(MOVBQZX s:(SETG flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GT flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GT, flags) + return true } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { - break + break + } + // match: (NE t:(TESTW x:(MOVBQZX s:(SETLE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (LE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LE, flags) + return true } - b.resetWithControl(BlockAMD64OS, cmp) - return true + break } - // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) - // result: (ULT (BTL x y)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLL { + // match: (NE t:(TESTW x:(MOVBQZX s:(SETGE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (GE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + s := x.Args[0] + if s.Op != OpAMD64SETGE { continue } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64ULT, v0) + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GE, flags) return true } break } - // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) - // result: (ULT (BTQ x y)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLQ { + // match: (NE t:(TESTW x:(MOVBQZX s:(SETA flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + s := x.Args[0] + if s.Op != OpAMD64SETA { continue } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64ULT, v0) + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGT, flags) return true } break } - // match: (NE (TESTLconst [c] x)) - // cond: isUnsignedPowerOfTwo(uint32(c)) - // result: (ULT (BTLconst [int8(log32u(uint32(c)))] x)) - for b.Controls[0].Op == OpAMD64TESTLconst { - v_0 := b.Controls[0] - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(isUnsignedPowerOfTwo(uint32(c))) { - break + // match: (NE t:(TESTW x:(MOVBQZX s:(SETB flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULT flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULT, flags) + return true } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - b.resetWithControl(BlockAMD64ULT, v0) - return true + break } - // match: (NE (TESTQconst [c] x)) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (ULT (BTQconst [int8(log32u(uint32(c)))] x)) - for b.Controls[0].Op == OpAMD64TESTQconst { - v_0 := b.Controls[0] - c := auxIntToInt32(v_0.AuxInt) - x := v_0.Args[0] - if !(isUnsignedPowerOfTwo(uint64(c))) { - break + // match: (NE t:(TESTW x:(MOVBQZX s:(SETAE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { + continue + } + s := x.Args[0] + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGE, flags) + return true } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log32u(uint32(c)))) - v0.AddArg(x) - b.resetWithControl(BlockAMD64ULT, v0) - return true + break } - // match: (NE (TESTQ (MOVQconst [c]) x)) - // cond: isUnsignedPowerOfTwo(uint64(c)) - // result: (ULT (BTQconst [int8(log64u(uint64(c)))] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64MOVQconst { + // match: (NE t:(TESTW x:(MOVBQZX s:(SETBE flags)) x) yes no) + // cond: t.Block == s.Block + // result: (ULE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - c := auxIntToInt64(v_0_0.AuxInt) - x := v_0_1 - if !(isUnsignedPowerOfTwo(uint64(c))) { + s := x.Args[0] + if s.Op != OpAMD64SETBE { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(int8(log64u(uint64(c)))) - v0.AddArg(x) - b.resetWithControl(BlockAMD64ULT, v0) + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULE, flags) return true } break } - // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) - // cond: z1==z2 - // result: (ULT (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { + // match: (NE t:(TESTW x:(MOVBQZX s:(SETEQF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (EQF flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + s := x.Args[0] + if s.Op != OpAMD64SETEQF { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - b.resetWithControl(BlockAMD64ULT, v0) + b.resetWithControl(BlockAMD64EQF, flags) return true } break } - // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) - // cond: z1==z2 - // result: (ULT (BTQconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { + // match: (NE t:(TESTW x:(MOVBQZX s:(SETNEF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (NEF flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { + s := x.Args[0] + if s.Op != OpAMD64SETNEF { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - b.resetWithControl(BlockAMD64ULT, v0) + b.resetWithControl(BlockAMD64NEF, flags) return true } break } - // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) - // cond: z1==z2 - // result: (ULT (BTQconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + // match: (NE t:(TESTW x:(MOVBQZX s:(SETGF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { + s := x.Args[0] + if s.Op != OpAMD64SETGF { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - b.resetWithControl(BlockAMD64ULT, v0) + b.resetWithControl(BlockAMD64UGT, flags) return true } break } - // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) - // cond: z1==z2 - // result: (ULT (BTLconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + // match: (NE t:(TESTW x:(MOVBQZX s:(SETGEF flags)) x) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTW { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + x := t_0 + if x.Op != OpAMD64MOVBQZX { continue } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { + s := x.Args[0] + if s.Op != OpAMD64SETGEF { continue } - x := z1_0.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if x != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(0) - v0.AddArg(x) - b.resetWithControl(BlockAMD64ULT, v0) + b.resetWithControl(BlockAMD64UGE, flags) return true } break } - // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) - // cond: z1==z2 - // result: (ULT (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { + // match: (NE t:(TESTB s:(SETEQ flags) s) yes no) + // cond: t.Block == s.Block + // result: (EQ flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQ { continue } - x := z1.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(63) - v0.AddArg(x) - b.resetWithControl(BlockAMD64ULT, v0) + b.resetWithControl(BlockAMD64EQ, flags) return true } break } - // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) - // cond: z1==z2 - // result: (ULT (BTLconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - z1 := v_0_0 - if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { + // match: (NE t:(TESTB s:(SETNE flags) s) yes no) + // cond: t.Block == s.Block + // result: (NE flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNE { continue } - x := z1.Args[0] - z2 := v_0_1 - if !(z1 == z2) { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = int8ToAuxInt(31) - v0.AddArg(x) - b.resetWithControl(BlockAMD64ULT, v0) + b.resetWithControl(BlockAMD64NE, flags) return true } break } - // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) - // result: (UGT cmp yes no) + // match: (NE t:(TESTB s:(SETL flags) s) yes no) + // cond: t.Block == s.Block + // result: (LT flags yes no) for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETGF { - break - } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { - break + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETL { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LT, flags) + return true } - b.resetWithControl(BlockAMD64UGT, cmp) - return true + break } - // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) - // result: (UGE cmp yes no) + // match: (NE t:(TESTB s:(SETG flags) s) yes no) + // cond: t.Block == s.Block + // result: (GT flags yes no) for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETGEF { - break - } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { - break + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETG { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GT, flags) + return true } - b.resetWithControl(BlockAMD64UGE, cmp) - return true + break } - // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) - // result: (EQF cmp yes no) + // match: (NE t:(TESTB s:(SETLE flags) s) yes no) + // cond: t.Block == s.Block + // result: (LE flags yes no) for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETEQF { - break - } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { - break + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETLE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64LE, flags) + return true } - b.resetWithControl(BlockAMD64EQF, cmp) - return true + break } - // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) - // result: (NEF cmp yes no) + // match: (NE t:(TESTB s:(SETGE flags) s) yes no) + // cond: t.Block == s.Block + // result: (GE flags yes no) for b.Controls[0].Op == OpAMD64TESTB { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SETNEF { - break - } - cmp := v_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { - break + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETGE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64GE, flags) + return true } - b.resetWithControl(BlockAMD64NEF, cmp) - return true - } - // match: (NE (InvertFlags cmp) yes no) - // result: (NE cmp yes no) - for b.Controls[0].Op == OpAMD64InvertFlags { - v_0 := b.Controls[0] - cmp := v_0.Args[0] - b.resetWithControl(BlockAMD64NE, cmp) - return true - } - // match: (NE (FlagEQ) yes no) - // result: (First no yes) - for b.Controls[0].Op == OpAMD64FlagEQ { - b.Reset(BlockFirst) - b.swapSuccessors() - return true + break } - // match: (NE (FlagLT_ULT) yes no) - // result: (First yes no) - for b.Controls[0].Op == OpAMD64FlagLT_ULT { - b.Reset(BlockFirst) - return true + // match: (NE t:(TESTB s:(SETA flags) s) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETA { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGT, flags) + return true + } + break } - // match: (NE (FlagLT_UGT) yes no) - // result: (First yes no) - for b.Controls[0].Op == OpAMD64FlagLT_UGT { - b.Reset(BlockFirst) - return true + // match: (NE t:(TESTB s:(SETB flags) s) yes no) + // cond: t.Block == s.Block + // result: (ULT flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETB { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULT, flags) + return true + } + break } - // match: (NE (FlagGT_ULT) yes no) - // result: (First yes no) - for b.Controls[0].Op == OpAMD64FlagGT_ULT { - b.Reset(BlockFirst) - return true + // match: (NE t:(TESTB s:(SETAE flags) s) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETAE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64UGE, flags) + return true + } + break } - // match: (NE (FlagGT_UGT) yes no) - // result: (First yes no) - for b.Controls[0].Op == OpAMD64FlagGT_UGT { - b.Reset(BlockFirst) - return true + // match: (NE t:(TESTB s:(SETBE flags) s) yes no) + // cond: t.Block == s.Block + // result: (ULE flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETBE { + continue + } + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { + continue + } + b.resetWithControl(BlockAMD64ULE, flags) + return true + } + break } - // match: (NE (TESTQ s:(Select0 blsr:(BLSRQ _)) s) yes no) - // result: (NE (Select1 blsr) yes no) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - s := v_0_0 - if s.Op != OpSelect0 { + // match: (NE t:(TESTB s:(SETEQF flags) s) yes no) + // cond: t.Block == s.Block + // result: (EQF flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETEQF { continue } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - b.resetWithControl(BlockAMD64NE, v0) + b.resetWithControl(BlockAMD64EQF, flags) return true } break } - // match: (NE (TESTL s:(Select0 blsr:(BLSRL _)) s) yes no) - // result: (NE (Select1 blsr) yes no) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - s := v_0_0 - if s.Op != OpSelect0 { + // match: (NE t:(TESTB s:(SETNEF flags) s) yes no) + // cond: t.Block == s.Block + // result: (NEF flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { + t := b.Controls[0] + _ = t.Args[1] + t_0 := t.Args[0] + t_1 := t.Args[1] + for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { + s := t_0 + if s.Op != OpAMD64SETNEF { continue } - blsr := s.Args[0] - if blsr.Op != OpAMD64BLSRL || s != v_0_1 { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(blsr) - b.resetWithControl(BlockAMD64NE, v0) + b.resetWithControl(BlockAMD64NEF, flags) return true } break } - // match: (NE t:(TESTQ a:(ADDQconst [c] x) a)) - // cond: t.Uses == 1 && flagify(a) - // result: (NE (Select1 a.Args[0])) - for b.Controls[0].Op == OpAMD64TESTQ { + // match: (NE t:(TESTB s:(SETGF flags) s) yes no) + // cond: t.Block == s.Block + // result: (UGT flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { t := b.Controls[0] _ = t.Args[1] t_0 := t.Args[0] t_1 := t.Args[1] for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { - a := t_0 - if a.Op != OpAMD64ADDQconst { + s := t_0 + if s.Op != OpAMD64SETGF { continue } - if a != t_1 || !(t.Uses == 1 && flagify(a)) { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(t.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(a.Args[0]) - b.resetWithControl(BlockAMD64NE, v0) + b.resetWithControl(BlockAMD64UGT, flags) return true } break } - // match: (NE t:(TESTL a:(ADDLconst [c] x) a)) - // cond: t.Uses == 1 && flagify(a) - // result: (NE (Select1 a.Args[0])) - for b.Controls[0].Op == OpAMD64TESTL { + // match: (NE t:(TESTB s:(SETGEF flags) s) yes no) + // cond: t.Block == s.Block + // result: (UGE flags yes no) + for b.Controls[0].Op == OpAMD64TESTB { t := b.Controls[0] _ = t.Args[1] t_0 := t.Args[0] t_1 := t.Args[1] for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 { - a := t_0 - if a.Op != OpAMD64ADDLconst { + s := t_0 + if s.Op != OpAMD64SETGEF { continue } - if a != t_1 || !(t.Uses == 1 && flagify(a)) { + flags := s.Args[0] + if s != t_1 || !(t.Block == s.Block) { continue } - v0 := b.NewValue0(t.Pos, OpSelect1, types.TypeFlags) - v0.AddArg(a.Args[0]) - b.resetWithControl(BlockAMD64NE, v0) + b.resetWithControl(BlockAMD64UGE, flags) return true } break diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64latelower.go b/src/cmd/compile/internal/ssa/rewriteAMD64latelower.go index 11ecb0b285a22c..531fbe1dd0117f 100644 --- a/src/cmd/compile/internal/ssa/rewriteAMD64latelower.go +++ b/src/cmd/compile/internal/ssa/rewriteAMD64latelower.go @@ -30,11 +30,11 @@ func rewriteValueAMD64latelower(v *Value) bool { func rewriteValueAMD64latelower_OpAMD64MOVBQZX(v *Value) bool { v_0 := v.Args[0] // match: (MOVBQZX x) - // cond: zeroUpper56Bits(x,3) + // cond: ZeroUpper56Bits(x,3) // result: x for { x := v_0 - if !(zeroUpper56Bits(x, 3)) { + if !(ZeroUpper56Bits(x, 3)) { break } v.copyOf(x) @@ -45,11 +45,11 @@ func rewriteValueAMD64latelower_OpAMD64MOVBQZX(v *Value) bool { func rewriteValueAMD64latelower_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] // match: (MOVLQZX x) - // cond: zeroUpper32Bits(x,3) + // cond: ZeroUpper32Bits(x,3) // result: x for { x := v_0 - if !(zeroUpper32Bits(x, 3)) { + if !(ZeroUpper32Bits(x, 3)) { break } v.copyOf(x) @@ -60,11 +60,11 @@ func rewriteValueAMD64latelower_OpAMD64MOVLQZX(v *Value) bool { func rewriteValueAMD64latelower_OpAMD64MOVWQZX(v *Value) bool { v_0 := v.Args[0] // match: (MOVWQZX x) - // cond: zeroUpper48Bits(x,3) + // cond: ZeroUpper48Bits(x,3) // result: x for { x := v_0 - if !(zeroUpper48Bits(x, 3)) { + if !(ZeroUpper48Bits(x, 3)) { break } v.copyOf(x) diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64splitload.go b/src/cmd/compile/internal/ssa/rewriteAMD64splitload.go index 0dcb1b460f9627..83aeff926e1975 100644 --- a/src/cmd/compile/internal/ssa/rewriteAMD64splitload.go +++ b/src/cmd/compile/internal/ssa/rewriteAMD64splitload.go @@ -151,9 +151,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPBload {sym} [off] ptr x mem) - // result: (CMPB (MOVBload {sym} [off] ptr mem) x) + // result: (CMPB (MOVBload {sym} [off] ptr mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -161,7 +160,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPBload(v *Value) bool { x := v_1 mem := v_2 v.reset(OpAMD64CMPB) - v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) + v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) @@ -175,9 +174,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPBloadidx1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPBloadidx1 {sym} [off] ptr idx x mem) - // result: (CMPB (MOVBloadidx1 {sym} [off] ptr idx mem) x) + // result: (CMPB (MOVBloadidx1 {sym} [off] ptr idx mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -186,7 +184,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPBloadidx1(v *Value) bool { x := v_2 mem := v_3 v.reset(OpAMD64CMPB) - v0 := b.NewValue0(v.Pos, OpAMD64MOVBloadidx1, typ.UInt8) + v0 := b.NewValue0(v.Pos, OpAMD64MOVBloadidx1, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, idx, mem) @@ -343,9 +341,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPLload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPLload {sym} [off] ptr x mem) - // result: (CMPL (MOVLload {sym} [off] ptr mem) x) + // result: (CMPL (MOVLload {sym} [off] ptr mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -353,7 +350,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPLload(v *Value) bool { x := v_1 mem := v_2 v.reset(OpAMD64CMPL) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) @@ -367,9 +364,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPLloadidx1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPLloadidx1 {sym} [off] ptr idx x mem) - // result: (CMPL (MOVLloadidx1 {sym} [off] ptr idx mem) x) + // result: (CMPL (MOVLloadidx1 {sym} [off] ptr idx mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -378,7 +374,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPLloadidx1(v *Value) bool { x := v_2 mem := v_3 v.reset(OpAMD64CMPL) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, idx, mem) @@ -392,9 +388,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPLloadidx4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPLloadidx4 {sym} [off] ptr idx x mem) - // result: (CMPL (MOVLloadidx4 {sym} [off] ptr idx mem) x) + // result: (CMPL (MOVLloadidx4 {sym} [off] ptr idx mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -403,7 +398,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPLloadidx4(v *Value) bool { x := v_2 mem := v_3 v.reset(OpAMD64CMPL) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx4, typ.UInt32) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx4, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, idx, mem) @@ -560,9 +555,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPQload {sym} [off] ptr x mem) - // result: (CMPQ (MOVQload {sym} [off] ptr mem) x) + // result: (CMPQ (MOVQload {sym} [off] ptr mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -570,7 +564,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPQload(v *Value) bool { x := v_1 mem := v_2 v.reset(OpAMD64CMPQ) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) @@ -584,9 +578,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPQloadidx1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPQloadidx1 {sym} [off] ptr idx x mem) - // result: (CMPQ (MOVQloadidx1 {sym} [off] ptr idx mem) x) + // result: (CMPQ (MOVQloadidx1 {sym} [off] ptr idx mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -595,7 +588,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPQloadidx1(v *Value) bool { x := v_2 mem := v_3 v.reset(OpAMD64CMPQ) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, idx, mem) @@ -609,9 +602,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPQloadidx8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPQloadidx8 {sym} [off] ptr idx x mem) - // result: (CMPQ (MOVQloadidx8 {sym} [off] ptr idx mem) x) + // result: (CMPQ (MOVQloadidx8 {sym} [off] ptr idx mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -620,7 +612,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPQloadidx8(v *Value) bool { x := v_2 mem := v_3 v.reset(OpAMD64CMPQ) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx8, typ.UInt64) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx8, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, idx, mem) @@ -777,9 +769,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPWload {sym} [off] ptr x mem) - // result: (CMPW (MOVWload {sym} [off] ptr mem) x) + // result: (CMPW (MOVWload {sym} [off] ptr mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -787,7 +778,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPWload(v *Value) bool { x := v_1 mem := v_2 v.reset(OpAMD64CMPW) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) @@ -801,9 +792,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPWloadidx1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPWloadidx1 {sym} [off] ptr idx x mem) - // result: (CMPW (MOVWloadidx1 {sym} [off] ptr idx mem) x) + // result: (CMPW (MOVWloadidx1 {sym} [off] ptr idx mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -812,7 +802,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPWloadidx1(v *Value) bool { x := v_2 mem := v_3 v.reset(OpAMD64CMPW) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, idx, mem) @@ -826,9 +816,8 @@ func rewriteValueAMD64splitload_OpAMD64CMPWloadidx2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (CMPWloadidx2 {sym} [off] ptr idx x mem) - // result: (CMPW (MOVWloadidx2 {sym} [off] ptr idx mem) x) + // result: (CMPW (MOVWloadidx2 {sym} [off] ptr idx mem) x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -837,7 +826,7 @@ func rewriteValueAMD64splitload_OpAMD64CMPWloadidx2(v *Value) bool { x := v_2 mem := v_3 v.reset(OpAMD64CMPW) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx2, typ.UInt16) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx2, x.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, idx, mem) diff --git a/src/cmd/compile/internal/ssa/rewriteARM.go b/src/cmd/compile/internal/ssa/rewriteARM.go index 44380cf8f57d85..da7dc28f97b42e 100644 --- a/src/cmd/compile/internal/ssa/rewriteARM.go +++ b/src/cmd/compile/internal/ssa/rewriteARM.go @@ -446,6 +446,9 @@ func rewriteValueARM(v *Value) bool { case OpAdd32carry: v.Op = OpARMADDS return true + case OpAdd32carrywithcarry: + v.Op = OpARMADCS + return true case OpAdd32withcarry: v.Op = OpARMADC return true @@ -873,6 +876,9 @@ func rewriteValueARM(v *Value) bool { case OpTailCall: v.Op = OpARMCALLtail return true + case OpTailCallInter: + v.Op = OpARMCALLtailinter + return true case OpTrunc16to8: v.Op = OpCopy return true diff --git a/src/cmd/compile/internal/ssa/rewriteARM64.go b/src/cmd/compile/internal/ssa/rewriteARM64.go index 6af15588338873..26d94b9ebf83fd 100644 --- a/src/cmd/compile/internal/ssa/rewriteARM64.go +++ b/src/cmd/compile/internal/ssa/rewriteARM64.go @@ -106,6 +106,10 @@ func rewriteValueARM64(v *Value) bool { return rewriteValueARM64_OpARM64FCMPD(v) case OpARM64FCMPS: return rewriteValueARM64_OpARM64FCMPS(v) + case OpARM64FCVTDS: + return rewriteValueARM64_OpARM64FCVTDS(v) + case OpARM64FLDPQ: + return rewriteValueARM64_OpARM64FLDPQ(v) case OpARM64FMOVDfpgp: return rewriteValueARM64_OpARM64FMOVDfpgp(v) case OpARM64FMOVDgpfp: @@ -122,6 +126,10 @@ func rewriteValueARM64(v *Value) bool { return rewriteValueARM64_OpARM64FMOVDstoreidx(v) case OpARM64FMOVDstoreidx8: return rewriteValueARM64_OpARM64FMOVDstoreidx8(v) + case OpARM64FMOVQload: + return rewriteValueARM64_OpARM64FMOVQload(v) + case OpARM64FMOVQstore: + return rewriteValueARM64_OpARM64FMOVQstore(v) case OpARM64FMOVSload: return rewriteValueARM64_OpARM64FMOVSload(v) case OpARM64FMOVSloadidx: @@ -146,6 +154,8 @@ func rewriteValueARM64(v *Value) bool { return rewriteValueARM64_OpARM64FNMULD(v) case OpARM64FNMULS: return rewriteValueARM64_OpARM64FNMULS(v) + case OpARM64FSTPQ: + return rewriteValueARM64_OpARM64FSTPQ(v) case OpARM64FSUBD: return rewriteValueARM64_OpARM64FSUBD(v) case OpARM64FSUBS: @@ -326,6 +336,8 @@ func rewriteValueARM64(v *Value) bool { return rewriteValueARM64_OpARM64ORshiftRO(v) case OpARM64REV: return rewriteValueARM64_OpARM64REV(v) + case OpARM64REV16: + return rewriteValueARM64_OpARM64REV16(v) case OpARM64REVW: return rewriteValueARM64_OpARM64REVW(v) case OpARM64ROR: @@ -388,6 +400,102 @@ func rewriteValueARM64(v *Value) bool { return rewriteValueARM64_OpARM64UMOD(v) case OpARM64UMODW: return rewriteValueARM64_OpARM64UMODW(v) + case OpARM64VBIF16B: + return rewriteValueARM64_OpARM64VBIF16B(v) + case OpARM64VBIT16B: + return rewriteValueARM64_OpARM64VBIT16B(v) + case OpARM64VDUPBbcast: + return rewriteValueARM64_OpARM64VDUPBbcast(v) + case OpARM64VFCVTL4S: + return rewriteValueARM64_OpARM64VFCVTL4S(v) + case OpARM64VMOVDins0: + return rewriteValueARM64_OpARM64VMOVDins0(v) + case OpARM64VMOVSins0: + return rewriteValueARM64_OpARM64VMOVSins0(v) + case OpARM64VPMULL2D: + return rewriteValueARM64_OpARM64VPMULL2D(v) + case OpARM64VSHL16B: + return rewriteValueARM64_OpARM64VSHL16B(v) + case OpARM64VSHL2D: + return rewriteValueARM64_OpARM64VSHL2D(v) + case OpARM64VSHL4S: + return rewriteValueARM64_OpARM64VSHL4S(v) + case OpARM64VSHL8H: + return rewriteValueARM64_OpARM64VSHL8H(v) + case OpARM64VSHRN2D: + return rewriteValueARM64_OpARM64VSHRN2D(v) + case OpARM64VSHRN4S: + return rewriteValueARM64_OpARM64VSHRN4S(v) + case OpARM64VSHRN8H: + return rewriteValueARM64_OpARM64VSHRN8H(v) + case OpARM64VSMULL16B: + return rewriteValueARM64_OpARM64VSMULL16B(v) + case OpARM64VSMULL4S: + return rewriteValueARM64_OpARM64VSMULL4S(v) + case OpARM64VSMULL8H: + return rewriteValueARM64_OpARM64VSMULL8H(v) + case OpARM64VSQSHL16Bconst: + return rewriteValueARM64_OpARM64VSQSHL16Bconst(v) + case OpARM64VSQSHL2Dconst: + return rewriteValueARM64_OpARM64VSQSHL2Dconst(v) + case OpARM64VSQSHL4Sconst: + return rewriteValueARM64_OpARM64VSQSHL4Sconst(v) + case OpARM64VSQSHL8Hconst: + return rewriteValueARM64_OpARM64VSQSHL8Hconst(v) + case OpARM64VSSHLL16B: + return rewriteValueARM64_OpARM64VSSHLL16B(v) + case OpARM64VSSHLL4S: + return rewriteValueARM64_OpARM64VSSHLL4S(v) + case OpARM64VSSHLL8H: + return rewriteValueARM64_OpARM64VSSHLL8H(v) + case OpARM64VSSHR16B: + return rewriteValueARM64_OpARM64VSSHR16B(v) + case OpARM64VSSHR2D: + return rewriteValueARM64_OpARM64VSSHR2D(v) + case OpARM64VSSHR4S: + return rewriteValueARM64_OpARM64VSSHR4S(v) + case OpARM64VSSHR8H: + return rewriteValueARM64_OpARM64VSSHR8H(v) + case OpARM64VSXTL16B: + return rewriteValueARM64_OpARM64VSXTL16B(v) + case OpARM64VSXTL4S: + return rewriteValueARM64_OpARM64VSXTL4S(v) + case OpARM64VSXTL8H: + return rewriteValueARM64_OpARM64VSXTL8H(v) + case OpARM64VUMULL16B: + return rewriteValueARM64_OpARM64VUMULL16B(v) + case OpARM64VUMULL4S: + return rewriteValueARM64_OpARM64VUMULL4S(v) + case OpARM64VUMULL8H: + return rewriteValueARM64_OpARM64VUMULL8H(v) + case OpARM64VUQSHL16Bconst: + return rewriteValueARM64_OpARM64VUQSHL16Bconst(v) + case OpARM64VUQSHL2Dconst: + return rewriteValueARM64_OpARM64VUQSHL2Dconst(v) + case OpARM64VUQSHL4Sconst: + return rewriteValueARM64_OpARM64VUQSHL4Sconst(v) + case OpARM64VUQSHL8Hconst: + return rewriteValueARM64_OpARM64VUQSHL8Hconst(v) + case OpARM64VUSHLL16B: + return rewriteValueARM64_OpARM64VUSHLL16B(v) + case OpARM64VUSHLL4S: + return rewriteValueARM64_OpARM64VUSHLL4S(v) + case OpARM64VUSHLL8H: + return rewriteValueARM64_OpARM64VUSHLL8H(v) + case OpARM64VUSHR16B: + return rewriteValueARM64_OpARM64VUSHR16B(v) + case OpARM64VUSHR2D: + return rewriteValueARM64_OpARM64VUSHR2D(v) + case OpARM64VUSHR4S: + return rewriteValueARM64_OpARM64VUSHR4S(v) + case OpARM64VUSHR8H: + return rewriteValueARM64_OpARM64VUSHR8H(v) + case OpARM64VUXTL16B: + return rewriteValueARM64_OpARM64VUXTL16B(v) + case OpARM64VUXTL4S: + return rewriteValueARM64_OpARM64VUXTL4S(v) + case OpARM64VUXTL8H: + return rewriteValueARM64_OpARM64VUXTL8H(v) case OpARM64XOR: return rewriteValueARM64_OpARM64XOR(v) case OpARM64XORconst: @@ -403,6 +511,24 @@ func rewriteValueARM64(v *Value) bool { case OpAbs: v.Op = OpARM64FABSD return true + case OpAbsFloat32x4: + v.Op = OpARM64VFABS4S + return true + case OpAbsFloat64x2: + v.Op = OpARM64VFABS2D + return true + case OpAbsInt16x8: + v.Op = OpARM64VABS8H + return true + case OpAbsInt32x4: + v.Op = OpARM64VABS4S + return true + case OpAbsInt64x2: + v.Op = OpARM64VABS2D + return true + case OpAbsInt8x16: + v.Op = OpARM64VABS16B + return true case OpAdd16: v.Op = OpARM64ADD return true @@ -421,9 +547,63 @@ func rewriteValueARM64(v *Value) bool { case OpAdd8: v.Op = OpARM64ADD return true + case OpAddFloat32x4: + v.Op = OpARM64VFADD4S + return true + case OpAddFloat64x2: + v.Op = OpARM64VFADD2D + return true + case OpAddInt16x8: + v.Op = OpARM64VADD8H + return true + case OpAddInt32x4: + v.Op = OpARM64VADD4S + return true + case OpAddInt64x2: + v.Op = OpARM64VADD2D + return true + case OpAddInt8x16: + v.Op = OpARM64VADD16B + return true case OpAddPtr: v.Op = OpARM64ADD return true + case OpAddSaturatedInt16x8: + v.Op = OpARM64VSQADD8H + return true + case OpAddSaturatedInt32x4: + v.Op = OpARM64VSQADD4S + return true + case OpAddSaturatedInt64x2: + v.Op = OpARM64VSQADD2D + return true + case OpAddSaturatedInt8x16: + v.Op = OpARM64VSQADD16B + return true + case OpAddSaturatedUint16x8: + v.Op = OpARM64VUQADD8H + return true + case OpAddSaturatedUint32x4: + v.Op = OpARM64VUQADD4S + return true + case OpAddSaturatedUint64x2: + v.Op = OpARM64VUQADD2D + return true + case OpAddSaturatedUint8x16: + v.Op = OpARM64VUQADD16B + return true + case OpAddUint16x8: + v.Op = OpARM64VADD8H + return true + case OpAddUint32x4: + v.Op = OpARM64VADD4S + return true + case OpAddUint64x2: + v.Op = OpARM64VADD2D + return true + case OpAddUint8x16: + v.Op = OpARM64VADD16B + return true case OpAddr: return rewriteValueARM64_OpAddr(v) case OpAnd16: @@ -441,6 +621,54 @@ func rewriteValueARM64(v *Value) bool { case OpAndB: v.Op = OpARM64AND return true + case OpAndInt16x8: + v.Op = OpARM64VAND16B + return true + case OpAndInt32x4: + v.Op = OpARM64VAND16B + return true + case OpAndInt64x2: + v.Op = OpARM64VAND16B + return true + case OpAndInt8x16: + v.Op = OpARM64VAND16B + return true + case OpAndNotInt16x8: + v.Op = OpARM64VBIC16B + return true + case OpAndNotInt32x4: + v.Op = OpARM64VBIC16B + return true + case OpAndNotInt64x2: + v.Op = OpARM64VBIC16B + return true + case OpAndNotInt8x16: + v.Op = OpARM64VBIC16B + return true + case OpAndNotUint16x8: + v.Op = OpARM64VBIC16B + return true + case OpAndNotUint32x4: + v.Op = OpARM64VBIC16B + return true + case OpAndNotUint64x2: + v.Op = OpARM64VBIC16B + return true + case OpAndNotUint8x16: + v.Op = OpARM64VBIC16B + return true + case OpAndUint16x8: + v.Op = OpARM64VAND16B + return true + case OpAndUint32x4: + v.Op = OpARM64VAND16B + return true + case OpAndUint64x2: + v.Op = OpARM64VAND16B + return true + case OpAndUint8x16: + v.Op = OpARM64VAND16B + return true case OpAtomicAdd32: v.Op = OpARM64LoweredAtomicAdd32 return true @@ -543,6 +771,24 @@ func rewriteValueARM64(v *Value) bool { case OpAtomicStorePtrNoWB: v.Op = OpARM64STLR return true + case OpAverageInt16x8: + v.Op = OpARM64VSRHADD8H + return true + case OpAverageInt32x4: + v.Op = OpARM64VSRHADD4S + return true + case OpAverageInt8x16: + v.Op = OpARM64VSRHADD16B + return true + case OpAverageUint16x8: + v.Op = OpARM64VURHADD8H + return true + case OpAverageUint32x4: + v.Op = OpARM64VURHADD4S + return true + case OpAverageUint8x16: + v.Op = OpARM64VURHADD16B + return true case OpAvg64u: return rewriteValueARM64_OpAvg64u(v) case OpBitLen16: @@ -575,6 +821,12 @@ func rewriteValueARM64(v *Value) bool { case OpCeil: v.Op = OpARM64FRINTPD return true + case OpCeilFloat32x4: + v.Op = OpARM64VFRINTP4S + return true + case OpCeilFloat64x2: + v.Op = OpARM64VFRINTP2D + return true case OpClosureCall: v.Op = OpARM64CALLclosure return true @@ -590,6 +842,81 @@ func rewriteValueARM64(v *Value) bool { case OpCom8: v.Op = OpARM64MVN return true + case OpConcatAddPairsFloat32x4: + v.Op = OpARM64VFADDP4S + return true + case OpConcatAddPairsFloat64x2: + v.Op = OpARM64VFADDP2D + return true + case OpConcatAddPairsInt16x8: + v.Op = OpARM64VADDP8H + return true + case OpConcatAddPairsInt32x4: + v.Op = OpARM64VADDP4S + return true + case OpConcatAddPairsInt64x2: + v.Op = OpARM64VADDP2D + return true + case OpConcatAddPairsUint16x8: + v.Op = OpARM64VADDP8H + return true + case OpConcatAddPairsUint32x4: + v.Op = OpARM64VADDP4S + return true + case OpConcatAddPairsUint64x2: + v.Op = OpARM64VADDP2D + return true + case OpConcatEvenInt16x8: + v.Op = OpARM64VUZP18H + return true + case OpConcatEvenInt32x4: + v.Op = OpARM64VUZP14S + return true + case OpConcatEvenInt64x2: + v.Op = OpARM64VUZP12D + return true + case OpConcatEvenInt8x16: + v.Op = OpARM64VUZP116B + return true + case OpConcatEvenUint16x8: + v.Op = OpARM64VUZP18H + return true + case OpConcatEvenUint32x4: + v.Op = OpARM64VUZP14S + return true + case OpConcatEvenUint64x2: + v.Op = OpARM64VUZP12D + return true + case OpConcatEvenUint8x16: + v.Op = OpARM64VUZP116B + return true + case OpConcatOddInt16x8: + v.Op = OpARM64VUZP28H + return true + case OpConcatOddInt32x4: + v.Op = OpARM64VUZP24S + return true + case OpConcatOddInt64x2: + v.Op = OpARM64VUZP22D + return true + case OpConcatOddInt8x16: + v.Op = OpARM64VUZP216B + return true + case OpConcatOddUint16x8: + v.Op = OpARM64VUZP28H + return true + case OpConcatOddUint32x4: + v.Op = OpARM64VUZP24S + return true + case OpConcatOddUint64x2: + v.Op = OpARM64VUZP22D + return true + case OpConcatOddUint8x16: + v.Op = OpARM64VUZP216B + return true + case OpConcatShiftBytesRightUint8x16: + v.Op = OpARM64VEXT16B + return true case OpCondSelect: return rewriteValueARM64_OpCondSelect(v) case OpConst16: @@ -608,6 +935,36 @@ func rewriteValueARM64(v *Value) bool { return rewriteValueARM64_OpConstBool(v) case OpConstNil: return rewriteValueARM64_OpConstNil(v) + case OpConvertLo2ToFloat64Float32x4: + v.Op = OpARM64VFCVTL4S + return true + case OpConvertToFloat32Float64x2: + v.Op = OpARM64VFCVTN2D + return true + case OpConvertToFloat32Int32x4: + v.Op = OpARM64VSCVTF4S + return true + case OpConvertToFloat32Uint32x4: + v.Op = OpARM64VUCVTF4S + return true + case OpConvertToFloat64Int64x2: + v.Op = OpARM64VSCVTF2D + return true + case OpConvertToFloat64Uint64x2: + v.Op = OpARM64VUCVTF2D + return true + case OpConvertToInt32Float32x4: + v.Op = OpARM64VFCVTZS4S + return true + case OpConvertToInt64Float64x2: + v.Op = OpARM64VFCVTZS2D + return true + case OpConvertToUint32Float32x4: + v.Op = OpARM64VFCVTZU4S + return true + case OpConvertToUint64Float64x2: + v.Op = OpARM64VFCVTZU2D + return true case OpCtz16: return rewriteValueARM64_OpCtz16(v) case OpCtz16NonZero: @@ -709,6 +1066,12 @@ func rewriteValueARM64(v *Value) bool { return rewriteValueARM64_OpDiv8(v) case OpDiv8u: return rewriteValueARM64_OpDiv8u(v) + case OpDivFloat32x4: + v.Op = OpARM64VFDIV4S + return true + case OpDivFloat64x2: + v.Op = OpARM64VFDIV2D + return true case OpEq16: return rewriteValueARM64_OpEq16(v) case OpEq32: @@ -725,11 +1088,65 @@ func rewriteValueARM64(v *Value) bool { return rewriteValueARM64_OpEqB(v) case OpEqPtr: return rewriteValueARM64_OpEqPtr(v) + case OpEqualFloat32x4: + v.Op = OpARM64VFCMEQ4S + return true + case OpEqualFloat64x2: + v.Op = OpARM64VFCMEQ2D + return true + case OpEqualInt16x8: + v.Op = OpARM64VCMEQ8H + return true + case OpEqualInt32x4: + v.Op = OpARM64VCMEQ4S + return true + case OpEqualInt64x2: + v.Op = OpARM64VCMEQ2D + return true + case OpEqualInt8x16: + v.Op = OpARM64VCMEQ16B + return true + case OpEqualUint16x8: + v.Op = OpARM64VCMEQ8H + return true + case OpEqualUint32x4: + v.Op = OpARM64VCMEQ4S + return true + case OpEqualUint64x2: + v.Op = OpARM64VCMEQ2D + return true + case OpEqualUint8x16: + v.Op = OpARM64VCMEQ16B + return true + case OpExtendLo2ToInt64Int32x4: + v.Op = OpARM64VSXTL4S + return true + case OpExtendLo2ToUint64Uint32x4: + v.Op = OpARM64VUXTL4S + return true + case OpExtendLo4ToInt32Int16x8: + v.Op = OpARM64VSXTL8H + return true + case OpExtendLo4ToUint32Uint16x8: + v.Op = OpARM64VUXTL8H + return true + case OpExtendLo8ToInt16Int8x16: + v.Op = OpARM64VSXTL16B + return true + case OpExtendLo8ToUint16Uint8x16: + v.Op = OpARM64VUXTL16B + return true case OpFMA: return rewriteValueARM64_OpFMA(v) case OpFloor: v.Op = OpARM64FRINTMD return true + case OpFloorFloat32x4: + v.Op = OpARM64VFRINTM4S + return true + case OpFloorFloat64x2: + v.Op = OpARM64VFRINTM2D + return true case OpGetCallerPC: v.Op = OpARM64LoweredGetCallerPC return true @@ -739,6 +1156,96 @@ func rewriteValueARM64(v *Value) bool { case OpGetClosurePtr: v.Op = OpARM64LoweredGetClosurePtr return true + case OpGetElemFloat32x4: + v.Op = OpARM64VDUPSextr + return true + case OpGetElemFloat64x2: + v.Op = OpARM64VDUPDextr + return true + case OpGetElemInt16x8: + v.Op = OpARM64VMOVHextr + return true + case OpGetElemInt32x4: + v.Op = OpARM64VMOVSextr + return true + case OpGetElemInt64x2: + v.Op = OpARM64VMOVDextr + return true + case OpGetElemInt8x16: + v.Op = OpARM64VMOVBextr + return true + case OpGetElemUint16x8: + v.Op = OpARM64VMOVHextr + return true + case OpGetElemUint32x4: + v.Op = OpARM64VMOVSextr + return true + case OpGetElemUint64x2: + v.Op = OpARM64VMOVDextr + return true + case OpGetElemUint8x16: + v.Op = OpARM64VMOVBextr + return true + case OpGreaterEqualFloat32x4: + v.Op = OpARM64VFCMGE4S + return true + case OpGreaterEqualFloat64x2: + v.Op = OpARM64VFCMGE2D + return true + case OpGreaterEqualInt16x8: + v.Op = OpARM64VCMGE8H + return true + case OpGreaterEqualInt32x4: + v.Op = OpARM64VCMGE4S + return true + case OpGreaterEqualInt64x2: + v.Op = OpARM64VCMGE2D + return true + case OpGreaterEqualInt8x16: + v.Op = OpARM64VCMGE16B + return true + case OpGreaterEqualUint16x8: + v.Op = OpARM64VCMHS8H + return true + case OpGreaterEqualUint32x4: + v.Op = OpARM64VCMHS4S + return true + case OpGreaterEqualUint64x2: + v.Op = OpARM64VCMHS2D + return true + case OpGreaterEqualUint8x16: + v.Op = OpARM64VCMHS16B + return true + case OpGreaterFloat32x4: + v.Op = OpARM64VFCMGT4S + return true + case OpGreaterFloat64x2: + v.Op = OpARM64VFCMGT2D + return true + case OpGreaterInt16x8: + v.Op = OpARM64VCMGT8H + return true + case OpGreaterInt32x4: + v.Op = OpARM64VCMGT4S + return true + case OpGreaterInt64x2: + v.Op = OpARM64VCMGT2D + return true + case OpGreaterInt8x16: + v.Op = OpARM64VCMGT16B + return true + case OpGreaterUint16x8: + v.Op = OpARM64VCMHI8H + return true + case OpGreaterUint32x4: + v.Op = OpARM64VCMHI4S + return true + case OpGreaterUint64x2: + v.Op = OpARM64VCMHI2D + return true + case OpGreaterUint8x16: + v.Op = OpARM64VCMHI16B + return true case OpHmul32: return rewriteValueARM64_OpHmul32(v) case OpHmul32u: @@ -752,12 +1259,144 @@ func rewriteValueARM64(v *Value) bool { case OpInterCall: v.Op = OpARM64CALLinter return true + case OpInterleaveEvenInt16x8: + v.Op = OpARM64VTRN18H + return true + case OpInterleaveEvenInt32x4: + v.Op = OpARM64VTRN14S + return true + case OpInterleaveEvenInt64x2: + v.Op = OpARM64VTRN12D + return true + case OpInterleaveEvenInt8x16: + v.Op = OpARM64VTRN116B + return true + case OpInterleaveEvenUint16x8: + v.Op = OpARM64VTRN18H + return true + case OpInterleaveEvenUint32x4: + v.Op = OpARM64VTRN14S + return true + case OpInterleaveEvenUint64x2: + v.Op = OpARM64VTRN12D + return true + case OpInterleaveEvenUint8x16: + v.Op = OpARM64VTRN116B + return true + case OpInterleaveHiInt16x8: + v.Op = OpARM64VZIP28H + return true + case OpInterleaveHiInt32x4: + v.Op = OpARM64VZIP24S + return true + case OpInterleaveHiInt64x2: + v.Op = OpARM64VZIP22D + return true + case OpInterleaveHiInt8x16: + v.Op = OpARM64VZIP216B + return true + case OpInterleaveHiUint16x8: + v.Op = OpARM64VZIP28H + return true + case OpInterleaveHiUint32x4: + v.Op = OpARM64VZIP24S + return true + case OpInterleaveHiUint64x2: + v.Op = OpARM64VZIP22D + return true + case OpInterleaveHiUint8x16: + v.Op = OpARM64VZIP216B + return true + case OpInterleaveLoInt16x8: + v.Op = OpARM64VZIP18H + return true + case OpInterleaveLoInt32x4: + v.Op = OpARM64VZIP14S + return true + case OpInterleaveLoInt64x2: + v.Op = OpARM64VZIP12D + return true + case OpInterleaveLoInt8x16: + v.Op = OpARM64VZIP116B + return true + case OpInterleaveLoUint16x8: + v.Op = OpARM64VZIP18H + return true + case OpInterleaveLoUint32x4: + v.Op = OpARM64VZIP14S + return true + case OpInterleaveLoUint64x2: + v.Op = OpARM64VZIP12D + return true + case OpInterleaveLoUint8x16: + v.Op = OpARM64VZIP116B + return true + case OpInterleaveOddInt16x8: + v.Op = OpARM64VTRN28H + return true + case OpInterleaveOddInt32x4: + v.Op = OpARM64VTRN24S + return true + case OpInterleaveOddInt64x2: + v.Op = OpARM64VTRN22D + return true + case OpInterleaveOddInt8x16: + v.Op = OpARM64VTRN216B + return true + case OpInterleaveOddUint16x8: + v.Op = OpARM64VTRN28H + return true + case OpInterleaveOddUint32x4: + v.Op = OpARM64VTRN24S + return true + case OpInterleaveOddUint64x2: + v.Op = OpARM64VTRN22D + return true + case OpInterleaveOddUint8x16: + v.Op = OpARM64VTRN216B + return true case OpIsInBounds: return rewriteValueARM64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueARM64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueARM64_OpIsSliceInBounds(v) + case OpLeadingSignBitsInt16x8: + v.Op = OpARM64VCLS8H + return true + case OpLeadingSignBitsInt32x4: + v.Op = OpARM64VCLS4S + return true + case OpLeadingSignBitsInt8x16: + v.Op = OpARM64VCLS16B + return true + case OpLeadingSignBitsUint16x8: + v.Op = OpARM64VCLS8H + return true + case OpLeadingSignBitsUint32x4: + v.Op = OpARM64VCLS4S + return true + case OpLeadingSignBitsUint8x16: + v.Op = OpARM64VCLS16B + return true + case OpLeadingZerosInt16x8: + v.Op = OpARM64VCLZ8H + return true + case OpLeadingZerosInt32x4: + v.Op = OpARM64VCLZ4S + return true + case OpLeadingZerosInt8x16: + v.Op = OpARM64VCLZ16B + return true + case OpLeadingZerosUint16x8: + v.Op = OpARM64VCLZ8H + return true + case OpLeadingZerosUint32x4: + v.Op = OpARM64VCLZ4S + return true + case OpLeadingZerosUint8x16: + v.Op = OpARM64VCLZ16B + return true case OpLeq16: return rewriteValueARM64_OpLeq16(v) case OpLeq16U: @@ -802,22 +1441,36 @@ func rewriteValueARM64(v *Value) bool { return rewriteValueARM64_OpLoad(v) case OpLocalAddr: return rewriteValueARM64_OpLocalAddr(v) + case OpLookupOrZeroInt8x16: + v.Op = OpARM64VTBL16B + return true + case OpLookupOrZeroUint8x16: + v.Op = OpARM64VTBL16B + return true case OpLsh16x16: - return rewriteValueARM64_OpLsh16x16(v) + v.Op = OpLsh64x16 + return true case OpLsh16x32: - return rewriteValueARM64_OpLsh16x32(v) + v.Op = OpLsh64x32 + return true case OpLsh16x64: - return rewriteValueARM64_OpLsh16x64(v) + v.Op = OpLsh64x64 + return true case OpLsh16x8: - return rewriteValueARM64_OpLsh16x8(v) + v.Op = OpLsh64x8 + return true case OpLsh32x16: - return rewriteValueARM64_OpLsh32x16(v) + v.Op = OpLsh64x16 + return true case OpLsh32x32: - return rewriteValueARM64_OpLsh32x32(v) + v.Op = OpLsh64x32 + return true case OpLsh32x64: - return rewriteValueARM64_OpLsh32x64(v) + v.Op = OpLsh64x64 + return true case OpLsh32x8: - return rewriteValueARM64_OpLsh32x8(v) + v.Op = OpLsh64x8 + return true case OpLsh64x16: return rewriteValueARM64_OpLsh64x16(v) case OpLsh64x32: @@ -827,25 +1480,80 @@ func rewriteValueARM64(v *Value) bool { case OpLsh64x8: return rewriteValueARM64_OpLsh64x8(v) case OpLsh8x16: - return rewriteValueARM64_OpLsh8x16(v) + v.Op = OpLsh64x16 + return true case OpLsh8x32: - return rewriteValueARM64_OpLsh8x32(v) + v.Op = OpLsh64x32 + return true case OpLsh8x64: - return rewriteValueARM64_OpLsh8x64(v) + v.Op = OpLsh64x64 + return true case OpLsh8x8: - return rewriteValueARM64_OpLsh8x8(v) + v.Op = OpLsh64x8 + return true case OpMax32F: v.Op = OpARM64FMAXS return true case OpMax64F: v.Op = OpARM64FMAXD return true + case OpMaxFloat32x4: + v.Op = OpARM64VFMAX4S + return true + case OpMaxFloat64x2: + v.Op = OpARM64VFMAX2D + return true + case OpMaxInt16x8: + v.Op = OpARM64VSMAX8H + return true + case OpMaxInt32x4: + v.Op = OpARM64VSMAX4S + return true + case OpMaxInt8x16: + v.Op = OpARM64VSMAX16B + return true + case OpMaxUint16x8: + v.Op = OpARM64VUMAX8H + return true + case OpMaxUint32x4: + v.Op = OpARM64VUMAX4S + return true + case OpMaxUint8x16: + v.Op = OpARM64VUMAX16B + return true + case OpMemEq: + v.Op = OpARM64LoweredMemEq + return true case OpMin32F: v.Op = OpARM64FMINS return true case OpMin64F: v.Op = OpARM64FMIND return true + case OpMinFloat32x4: + v.Op = OpARM64VFMIN4S + return true + case OpMinFloat64x2: + v.Op = OpARM64VFMIN2D + return true + case OpMinInt16x8: + v.Op = OpARM64VSMIN8H + return true + case OpMinInt32x4: + v.Op = OpARM64VSMIN4S + return true + case OpMinInt8x16: + v.Op = OpARM64VSMIN16B + return true + case OpMinUint16x8: + v.Op = OpARM64VUMIN8H + return true + case OpMinUint32x4: + v.Op = OpARM64VUMIN4S + return true + case OpMinUint8x16: + v.Op = OpARM64VUMIN16B + return true case OpMod16: return rewriteValueARM64_OpMod16(v) case OpMod16u: @@ -884,6 +1592,64 @@ func rewriteValueARM64(v *Value) bool { case OpMul8: v.Op = OpARM64MULW return true + case OpMulAddFloat32x4: + return rewriteValueARM64_OpMulAddFloat32x4(v) + case OpMulAddFloat64x2: + return rewriteValueARM64_OpMulAddFloat64x2(v) + case OpMulAddInt16x8: + return rewriteValueARM64_OpMulAddInt16x8(v) + case OpMulAddInt32x4: + return rewriteValueARM64_OpMulAddInt32x4(v) + case OpMulAddInt8x16: + return rewriteValueARM64_OpMulAddInt8x16(v) + case OpMulAddUint16x8: + return rewriteValueARM64_OpMulAddUint16x8(v) + case OpMulAddUint32x4: + return rewriteValueARM64_OpMulAddUint32x4(v) + case OpMulAddUint8x16: + return rewriteValueARM64_OpMulAddUint8x16(v) + case OpMulFloat32x4: + v.Op = OpARM64VFMUL4S + return true + case OpMulFloat64x2: + v.Op = OpARM64VFMUL2D + return true + case OpMulInt16x8: + v.Op = OpARM64VMUL8H + return true + case OpMulInt32x4: + v.Op = OpARM64VMUL4S + return true + case OpMulInt8x16: + v.Op = OpARM64VMUL16B + return true + case OpMulUint16x8: + v.Op = OpARM64VMUL8H + return true + case OpMulUint32x4: + v.Op = OpARM64VMUL4S + return true + case OpMulUint8x16: + v.Op = OpARM64VMUL16B + return true + case OpMulWidenLoInt16x8: + v.Op = OpARM64VSMULL8H + return true + case OpMulWidenLoInt32x4: + v.Op = OpARM64VSMULL4S + return true + case OpMulWidenLoInt8x16: + v.Op = OpARM64VSMULL16B + return true + case OpMulWidenLoUint16x8: + v.Op = OpARM64VUMULL8H + return true + case OpMulWidenLoUint32x4: + v.Op = OpARM64VUMULL4S + return true + case OpMulWidenLoUint8x16: + v.Op = OpARM64VUMULL16B + return true case OpNeg16: v.Op = OpARM64NEG return true @@ -902,6 +1668,24 @@ func rewriteValueARM64(v *Value) bool { case OpNeg8: v.Op = OpARM64NEG return true + case OpNegFloat32x4: + v.Op = OpARM64VFNEG4S + return true + case OpNegFloat64x2: + v.Op = OpARM64VFNEG2D + return true + case OpNegInt16x8: + v.Op = OpARM64VNEG8H + return true + case OpNegInt32x4: + v.Op = OpARM64VNEG4S + return true + case OpNegInt64x2: + v.Op = OpARM64VNEG2D + return true + case OpNegInt8x16: + v.Op = OpARM64VNEG16B + return true case OpNeq16: return rewriteValueARM64_OpNeq16(v) case OpNeq32: @@ -924,8 +1708,38 @@ func rewriteValueARM64(v *Value) bool { return true case OpNot: return rewriteValueARM64_OpNot(v) + case OpNotInt16x8: + v.Op = OpARM64VNOT16B + return true + case OpNotInt32x4: + v.Op = OpARM64VNOT16B + return true + case OpNotInt64x2: + v.Op = OpARM64VNOT16B + return true + case OpNotInt8x16: + v.Op = OpARM64VNOT16B + return true + case OpNotUint16x8: + v.Op = OpARM64VNOT16B + return true + case OpNotUint32x4: + v.Op = OpARM64VNOT16B + return true + case OpNotUint64x2: + v.Op = OpARM64VNOT16B + return true + case OpNotUint8x16: + v.Op = OpARM64VNOT16B + return true case OpOffPtr: return rewriteValueARM64_OpOffPtr(v) + case OpOnesCountInt8x16: + v.Op = OpARM64VCNT16B + return true + case OpOnesCountUint8x16: + v.Op = OpARM64VCNT16B + return true case OpOr16: v.Op = OpARM64OR return true @@ -941,6 +1755,54 @@ func rewriteValueARM64(v *Value) bool { case OpOrB: v.Op = OpARM64OR return true + case OpOrInt16x8: + v.Op = OpARM64VORR16B + return true + case OpOrInt32x4: + v.Op = OpARM64VORR16B + return true + case OpOrInt64x2: + v.Op = OpARM64VORR16B + return true + case OpOrInt8x16: + v.Op = OpARM64VORR16B + return true + case OpOrNotInt16x8: + v.Op = OpARM64VORN16B + return true + case OpOrNotInt32x4: + v.Op = OpARM64VORN16B + return true + case OpOrNotInt64x2: + v.Op = OpARM64VORN16B + return true + case OpOrNotInt8x16: + v.Op = OpARM64VORN16B + return true + case OpOrNotUint16x8: + v.Op = OpARM64VORN16B + return true + case OpOrNotUint32x4: + v.Op = OpARM64VORN16B + return true + case OpOrNotUint64x2: + v.Op = OpARM64VORN16B + return true + case OpOrNotUint8x16: + v.Op = OpARM64VORN16B + return true + case OpOrUint16x8: + v.Op = OpARM64VORR16B + return true + case OpOrUint32x4: + v.Op = OpARM64VORR16B + return true + case OpOrUint64x2: + v.Op = OpARM64VORR16B + return true + case OpOrUint8x16: + v.Op = OpARM64VORR16B + return true case OpPanicBounds: v.Op = OpARM64LoweredPanicBoundsRR return true @@ -973,6 +1835,12 @@ func rewriteValueARM64(v *Value) bool { case OpRound64F: v.Op = OpARM64LoweredRound64F return true + case OpRoundFloat32x4: + v.Op = OpARM64VFRINTN4S + return true + case OpRoundFloat64x2: + v.Op = OpARM64VFRINTN2D + return true case OpRoundToEven: v.Op = OpARM64FRINTND return true @@ -1040,12 +1908,149 @@ func rewriteValueARM64(v *Value) bool { return rewriteValueARM64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueARM64_OpRsh8x8(v) + case OpSaturateToInt16Int32x4: + v.Op = OpARM64VSQXTN4S + return true + case OpSaturateToInt32Int64x2: + v.Op = OpARM64VSQXTN2D + return true + case OpSaturateToInt8Int16x8: + v.Op = OpARM64VSQXTN8H + return true + case OpSaturateToUint16Int32x4: + v.Op = OpARM64VSQXTUN4S + return true + case OpSaturateToUint16Uint32x4: + v.Op = OpARM64VUQXTN4S + return true + case OpSaturateToUint32Int64x2: + v.Op = OpARM64VSQXTUN2D + return true + case OpSaturateToUint32Uint64x2: + v.Op = OpARM64VUQXTN2D + return true + case OpSaturateToUint8Int16x8: + v.Op = OpARM64VSQXTUN8H + return true + case OpSaturateToUint8Uint16x8: + v.Op = OpARM64VUQXTN8H + return true case OpSelect0: return rewriteValueARM64_OpSelect0(v) case OpSelect1: return rewriteValueARM64_OpSelect1(v) case OpSelectN: return rewriteValueARM64_OpSelectN(v) + case OpSetElemFloat32x4: + v.Op = OpARM64VMOVSins0 + return true + case OpSetElemFloat64x2: + v.Op = OpARM64VMOVDins0 + return true + case OpSetElemInt16x8: + v.Op = OpARM64VMOVHins + return true + case OpSetElemInt32x4: + v.Op = OpARM64VMOVSins + return true + case OpSetElemInt64x2: + v.Op = OpARM64VMOVDins + return true + case OpSetElemInt8x16: + v.Op = OpARM64VMOVBins + return true + case OpSetElemUint16x8: + v.Op = OpARM64VMOVHins + return true + case OpSetElemUint32x4: + v.Op = OpARM64VMOVSins + return true + case OpSetElemUint64x2: + v.Op = OpARM64VMOVDins + return true + case OpSetElemUint8x16: + v.Op = OpARM64VMOVBins + return true + case OpShiftAllLeftInt16x8: + return rewriteValueARM64_OpShiftAllLeftInt16x8(v) + case OpShiftAllLeftInt32x4: + return rewriteValueARM64_OpShiftAllLeftInt32x4(v) + case OpShiftAllLeftInt64x2: + return rewriteValueARM64_OpShiftAllLeftInt64x2(v) + case OpShiftAllLeftInt8x16: + return rewriteValueARM64_OpShiftAllLeftInt8x16(v) + case OpShiftAllLeftUint16x8: + return rewriteValueARM64_OpShiftAllLeftUint16x8(v) + case OpShiftAllLeftUint32x4: + return rewriteValueARM64_OpShiftAllLeftUint32x4(v) + case OpShiftAllLeftUint64x2: + return rewriteValueARM64_OpShiftAllLeftUint64x2(v) + case OpShiftAllLeftUint8x16: + return rewriteValueARM64_OpShiftAllLeftUint8x16(v) + case OpShiftAllRightInt16x8: + return rewriteValueARM64_OpShiftAllRightInt16x8(v) + case OpShiftAllRightInt32x4: + return rewriteValueARM64_OpShiftAllRightInt32x4(v) + case OpShiftAllRightInt64x2: + return rewriteValueARM64_OpShiftAllRightInt64x2(v) + case OpShiftAllRightInt8x16: + return rewriteValueARM64_OpShiftAllRightInt8x16(v) + case OpShiftAllRightUint16x8: + return rewriteValueARM64_OpShiftAllRightUint16x8(v) + case OpShiftAllRightUint32x4: + return rewriteValueARM64_OpShiftAllRightUint32x4(v) + case OpShiftAllRightUint64x2: + return rewriteValueARM64_OpShiftAllRightUint64x2(v) + case OpShiftAllRightUint8x16: + return rewriteValueARM64_OpShiftAllRightUint8x16(v) + case OpShiftInt16x8: + v.Op = OpARM64VSSHL8H + return true + case OpShiftInt32x4: + v.Op = OpARM64VSSHL4S + return true + case OpShiftInt64x2: + v.Op = OpARM64VSSHL2D + return true + case OpShiftInt8x16: + v.Op = OpARM64VSSHL16B + return true + case OpShiftSaturatedInt16x8: + v.Op = OpARM64VSQSHL8H + return true + case OpShiftSaturatedInt32x4: + v.Op = OpARM64VSQSHL4S + return true + case OpShiftSaturatedInt64x2: + v.Op = OpARM64VSQSHL2D + return true + case OpShiftSaturatedInt8x16: + v.Op = OpARM64VSQSHL16B + return true + case OpShiftSaturatedUint16x8: + v.Op = OpARM64VUQSHL8H + return true + case OpShiftSaturatedUint32x4: + v.Op = OpARM64VUQSHL4S + return true + case OpShiftSaturatedUint64x2: + v.Op = OpARM64VUQSHL2D + return true + case OpShiftSaturatedUint8x16: + v.Op = OpARM64VUQSHL16B + return true + case OpShiftUint16x8: + v.Op = OpARM64VUSHL8H + return true + case OpShiftUint32x4: + v.Op = OpARM64VUSHL4S + return true + case OpShiftUint64x2: + v.Op = OpARM64VUSHL2D + return true + case OpShiftUint8x16: + v.Op = OpARM64VUSHL16B + return true case OpSignExt16to32: v.Op = OpARM64MOVHreg return true @@ -1072,6 +2077,12 @@ func rewriteValueARM64(v *Value) bool { case OpSqrt32: v.Op = OpARM64FSQRTS return true + case OpSqrtFloat32x4: + v.Op = OpARM64VFSQRT4S + return true + case OpSqrtFloat64x2: + v.Op = OpARM64VFSQRT2D + return true case OpStaticCall: v.Op = OpARM64CALLstatic return true @@ -1095,12 +2106,69 @@ func rewriteValueARM64(v *Value) bool { case OpSub8: v.Op = OpARM64SUB return true + case OpSubFloat32x4: + v.Op = OpARM64VFSUB4S + return true + case OpSubFloat64x2: + v.Op = OpARM64VFSUB2D + return true + case OpSubInt16x8: + v.Op = OpARM64VSUB8H + return true + case OpSubInt32x4: + v.Op = OpARM64VSUB4S + return true + case OpSubInt64x2: + v.Op = OpARM64VSUB2D + return true + case OpSubInt8x16: + v.Op = OpARM64VSUB16B + return true case OpSubPtr: v.Op = OpARM64SUB return true + case OpSubSaturatedInt16x8: + v.Op = OpARM64VSQSUB8H + return true + case OpSubSaturatedInt32x4: + v.Op = OpARM64VSQSUB4S + return true + case OpSubSaturatedInt64x2: + v.Op = OpARM64VSQSUB2D + return true + case OpSubSaturatedInt8x16: + v.Op = OpARM64VSQSUB16B + return true + case OpSubSaturatedUint16x8: + v.Op = OpARM64VUQSUB8H + return true + case OpSubSaturatedUint32x4: + v.Op = OpARM64VUQSUB4S + return true + case OpSubSaturatedUint64x2: + v.Op = OpARM64VUQSUB2D + return true + case OpSubSaturatedUint8x16: + v.Op = OpARM64VUQSUB16B + return true + case OpSubUint16x8: + v.Op = OpARM64VSUB8H + return true + case OpSubUint32x4: + v.Op = OpARM64VSUB4S + return true + case OpSubUint64x2: + v.Op = OpARM64VSUB2D + return true + case OpSubUint8x16: + v.Op = OpARM64VSUB16B + return true case OpTailCall: v.Op = OpARM64CALLtail return true + case OpTailCallInter: + v.Op = OpARM64CALLtailinter + return true case OpTrunc: v.Op = OpARM64FRINTZD return true @@ -1122,6 +2190,30 @@ func rewriteValueARM64(v *Value) bool { case OpTrunc64to8: v.Op = OpCopy return true + case OpTruncFloat32x4: + v.Op = OpARM64VFRINTZ4S + return true + case OpTruncFloat64x2: + v.Op = OpARM64VFRINTZ2D + return true + case OpTruncToInt16Int32x4: + v.Op = OpARM64VXTN4S + return true + case OpTruncToInt32Int64x2: + v.Op = OpARM64VXTN2D + return true + case OpTruncToInt8Int16x8: + v.Op = OpARM64VXTN8H + return true + case OpTruncToUint16Uint32x4: + v.Op = OpARM64VXTN4S + return true + case OpTruncToUint32Uint64x2: + v.Op = OpARM64VXTN2D + return true + case OpTruncToUint8Uint16x8: + v.Op = OpARM64VXTN8H + return true case OpWB: v.Op = OpARM64LoweredWB return true @@ -1137,6 +2229,30 @@ func rewriteValueARM64(v *Value) bool { case OpXor8: v.Op = OpARM64XOR return true + case OpXorInt16x8: + v.Op = OpARM64VEOR16B + return true + case OpXorInt32x4: + v.Op = OpARM64VEOR16B + return true + case OpXorInt64x2: + v.Op = OpARM64VEOR16B + return true + case OpXorInt8x16: + v.Op = OpARM64VEOR16B + return true + case OpXorUint16x8: + v.Op = OpARM64VEOR16B + return true + case OpXorUint32x4: + v.Op = OpARM64VEOR16B + return true + case OpXorUint64x2: + v.Op = OpARM64VEOR16B + return true + case OpXorUint8x16: + v.Op = OpARM64VEOR16B + return true case OpZero: return rewriteValueARM64_OpZero(v) case OpZeroExt16to32: @@ -1157,6 +2273,97 @@ func rewriteValueARM64(v *Value) bool { case OpZeroExt8to64: v.Op = OpARM64MOVBUreg return true + case OpZeroSIMD: + return rewriteValueARM64_OpZeroSIMD(v) + case OpbitSelectInt8x16: + v.Op = OpARM64VBIF16B + return true + case OpbitSelectNotInt8x16: + v.Op = OpARM64VBIT16B + return true + case Opbroadcast1To16Int8x16: + return rewriteValueARM64_Opbroadcast1To16Int8x16(v) + case Opbroadcast1To16Uint8x16: + return rewriteValueARM64_Opbroadcast1To16Uint8x16(v) + case Opbroadcast1To2Float64x2: + return rewriteValueARM64_Opbroadcast1To2Float64x2(v) + case Opbroadcast1To2Int64x2: + return rewriteValueARM64_Opbroadcast1To2Int64x2(v) + case Opbroadcast1To2Uint64x2: + return rewriteValueARM64_Opbroadcast1To2Uint64x2(v) + case Opbroadcast1To4Float32x4: + return rewriteValueARM64_Opbroadcast1To4Float32x4(v) + case Opbroadcast1To4Int32x4: + return rewriteValueARM64_Opbroadcast1To4Int32x4(v) + case Opbroadcast1To4Uint32x4: + return rewriteValueARM64_Opbroadcast1To4Uint32x4(v) + case Opbroadcast1To8Int16x8: + return rewriteValueARM64_Opbroadcast1To8Int16x8(v) + case Opbroadcast1To8Uint16x8: + return rewriteValueARM64_Opbroadcast1To8Uint16x8(v) + case OpcarrylessMultiplyWidenLoUint64x2: + v.Op = OpARM64VPMULL2D + return true + case OpreduceMaxFloat32x4: + v.Op = OpARM64VFMAXV4S + return true + case OpreduceMaxInt16x8: + v.Op = OpARM64VSMAXV8H + return true + case OpreduceMaxInt32x4: + v.Op = OpARM64VSMAXV4S + return true + case OpreduceMaxInt8x16: + v.Op = OpARM64VSMAXV16B + return true + case OpreduceMaxUint16x8: + v.Op = OpARM64VUMAXV8H + return true + case OpreduceMaxUint32x4: + v.Op = OpARM64VUMAXV4S + return true + case OpreduceMaxUint8x16: + v.Op = OpARM64VUMAXV16B + return true + case OpreduceMinFloat32x4: + v.Op = OpARM64VFMINV4S + return true + case OpreduceMinInt16x8: + v.Op = OpARM64VSMINV8H + return true + case OpreduceMinInt32x4: + v.Op = OpARM64VSMINV4S + return true + case OpreduceMinInt8x16: + v.Op = OpARM64VSMINV16B + return true + case OpreduceMinUint16x8: + v.Op = OpARM64VUMINV8H + return true + case OpreduceMinUint32x4: + v.Op = OpARM64VUMINV4S + return true + case OpreduceMinUint8x16: + v.Op = OpARM64VUMINV16B + return true + case OpreduceSumInt16x8: + v.Op = OpARM64VADDV8H + return true + case OpreduceSumInt32x4: + v.Op = OpARM64VADDV4S + return true + case OpreduceSumInt8x16: + v.Op = OpARM64VADDV16B + return true + case OpreduceSumUint16x8: + v.Op = OpARM64VADDV8H + return true + case OpreduceSumUint32x4: + v.Op = OpARM64VADDV4S + return true + case OpreduceSumUint8x16: + v.Op = OpARM64VADDV16B + return true } return false } @@ -2280,6 +3487,39 @@ func rewriteValueARM64_OpARM64ANDconst(v *Value) bool { v.AddArg(x) return true } + // match: (ANDconst [0xffffffff] x) + // result: (MOVWUreg x) + for { + if auxIntToInt64(v.AuxInt) != 0xffffffff { + break + } + x := v_0 + v.reset(OpARM64MOVWUreg) + v.AddArg(x) + return true + } + // match: (ANDconst [0xffff ] x) + // result: (MOVHUreg x) + for { + if auxIntToInt64(v.AuxInt) != 0xffff { + break + } + x := v_0 + v.reset(OpARM64MOVHUreg) + v.AddArg(x) + return true + } + // match: (ANDconst [0xff ] x) + // result: (MOVBUreg x) + for { + if auxIntToInt64(v.AuxInt) != 0xff { + break + } + x := v_0 + v.reset(OpARM64MOVBUreg) + v.AddArg(x) + return true + } return false } func rewriteValueARM64_OpARM64ANDshiftLL(v *Value) bool { @@ -4787,6 +6027,165 @@ func rewriteValueARM64_OpARM64FCMPS(v *Value) bool { } return false } +func rewriteValueARM64_OpARM64FCVTDS(v *Value) bool { + v_0 := v.Args[0] + // match: (FCVTDS (FABSD (FCVTSD x))) + // result: (FABSS x) + for { + if v_0.Op != OpARM64FABSD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpARM64FCVTSD { + break + } + x := v_0_0.Args[0] + v.reset(OpARM64FABSS) + v.AddArg(x) + return true + } + // match: (FCVTDS (FSQRTD (FCVTSD x))) + // result: (FSQRTS x) + for { + if v_0.Op != OpARM64FSQRTD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpARM64FCVTSD { + break + } + x := v_0_0.Args[0] + v.reset(OpARM64FSQRTS) + v.AddArg(x) + return true + } + // match: (FCVTDS (FRINTPD (FCVTSD x))) + // result: (FRINTPS x) + for { + if v_0.Op != OpARM64FRINTPD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpARM64FCVTSD { + break + } + x := v_0_0.Args[0] + v.reset(OpARM64FRINTPS) + v.AddArg(x) + return true + } + // match: (FCVTDS (FRINTMD (FCVTSD x))) + // result: (FRINTMS x) + for { + if v_0.Op != OpARM64FRINTMD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpARM64FCVTSD { + break + } + x := v_0_0.Args[0] + v.reset(OpARM64FRINTMS) + v.AddArg(x) + return true + } + // match: (FCVTDS (FRINTAD (FCVTSD x))) + // result: (FRINTAS x) + for { + if v_0.Op != OpARM64FRINTAD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpARM64FCVTSD { + break + } + x := v_0_0.Args[0] + v.reset(OpARM64FRINTAS) + v.AddArg(x) + return true + } + // match: (FCVTDS (FRINTND (FCVTSD x))) + // result: (FRINTNS x) + for { + if v_0.Op != OpARM64FRINTND { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpARM64FCVTSD { + break + } + x := v_0_0.Args[0] + v.reset(OpARM64FRINTNS) + v.AddArg(x) + return true + } + // match: (FCVTDS (FRINTZD (FCVTSD x))) + // result: (FRINTZS x) + for { + if v_0.Op != OpARM64FRINTZD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpARM64FCVTSD { + break + } + x := v_0_0.Args[0] + v.reset(OpARM64FRINTZS) + v.AddArg(x) + return true + } + return false +} +func rewriteValueARM64_OpARM64FLDPQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + // match: (FLDPQ [off1] {sym} (ADDconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) + // result: (FLDPQ [off1+int32(off2)] {sym} ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpARM64ADDconst { + break + } + off2 := auxIntToInt64(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { + break + } + v.reset(OpARM64FLDPQ) + v.AuxInt = int32ToAuxInt(off1 + int32(off2)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + // match: (FLDPQ [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) + // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) + // result: (FLDPQ [off1+off2] {mergeSym(sym1,sym2)} ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpARM64MOVDaddr { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + mem := v_1 + if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { + break + } + v.reset(OpARM64FLDPQ) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(ptr, mem) + return true + } + return false +} func rewriteValueARM64_OpARM64FMOVDfpgp(v *Value) bool { v_0 := v.Args[0] b := v.Block @@ -5235,31 +6634,14 @@ func rewriteValueARM64_OpARM64FMOVDstoreidx8(v *Value) bool { } return false } -func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool { +func rewriteValueARM64_OpARM64FMOVQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config - // match: (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) - // result: (FMOVSgpfp val) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpARM64MOVWstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { - break - } - val := v_1.Args[1] - if ptr != v_1.Args[0] { - break - } - v.reset(OpARM64FMOVSgpfp) - v.AddArg(val) - return true - } - // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) + // match: (FMOVQload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) - // result: (FMOVSload [off1+int32(off2)] {sym} ptr mem) + // result: (FMOVQload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) @@ -5272,37 +6654,157 @@ func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool { if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } - v.reset(OpARM64FMOVSload) + v.reset(OpARM64FMOVQload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } - // match: (FMOVSload [off] {sym} (ADD ptr idx) mem) - // cond: off == 0 && sym == nil - // result: (FMOVSloadidx ptr idx mem) + // match: (FMOVQload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) + // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) + // result: (FMOVQload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpARM64MOVDaddr { break } - idx := v_0.Args[1] + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 - if !(off == 0 && sym == nil) { + if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } - v.reset(OpARM64FMOVSloadidx) - v.AddArg3(ptr, idx, mem) + v.reset(OpARM64FMOVQload) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg2(ptr, mem) return true } - // match: (FMOVSload [off] {sym} (ADDshiftLL [2] ptr idx) mem) - // cond: off == 0 && sym == nil - // result: (FMOVSloadidx4 ptr idx mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) + return false +} +func rewriteValueARM64_OpARM64FMOVQstore(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + // match: (FMOVQstore [off1] {sym} (ADDconst [off2] ptr) val mem) + // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) + // result: (FMOVQstore [off1+int32(off2)] {sym} ptr val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpARM64ADDconst { + break + } + off2 := auxIntToInt64(v_0.AuxInt) + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { + break + } + v.reset(OpARM64FMOVQstore) + v.AuxInt = int32ToAuxInt(off1 + int32(off2)) + v.Aux = symToAux(sym) + v.AddArg3(ptr, val, mem) + return true + } + // match: (FMOVQstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) + // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) + // result: (FMOVQstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpARM64MOVDaddr { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { + break + } + v.reset(OpARM64FMOVQstore) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg3(ptr, val, mem) + return true + } + return false +} +func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + // match: (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) + // result: (FMOVSgpfp val) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpARM64MOVWstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { + break + } + val := v_1.Args[1] + if ptr != v_1.Args[0] { + break + } + v.reset(OpARM64FMOVSgpfp) + v.AddArg(val) + return true + } + // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) + // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) + // result: (FMOVSload [off1+int32(off2)] {sym} ptr mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpARM64ADDconst { + break + } + off2 := auxIntToInt64(v_0.AuxInt) + ptr := v_0.Args[0] + mem := v_1 + if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { + break + } + v.reset(OpARM64FMOVSload) + v.AuxInt = int32ToAuxInt(off1 + int32(off2)) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + // match: (FMOVSload [off] {sym} (ADD ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (FMOVSloadidx ptr idx mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpARM64ADD { + break + } + idx := v_0.Args[1] + ptr := v_0.Args[0] + mem := v_1 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpARM64FMOVSloadidx) + v.AddArg3(ptr, idx, mem) + return true + } + // match: (FMOVSload [off] {sym} (ADDshiftLL [2] ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (FMOVSloadidx4 ptr idx mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } @@ -5777,6 +7279,62 @@ func rewriteValueARM64_OpARM64FNMULS(v *Value) bool { } return false } +func rewriteValueARM64_OpARM64FSTPQ(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + // match: (FSTPQ [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) + // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) + // result: (FSTPQ [off1+int32(off2)] {sym} ptr val1 val2 mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpARM64ADDconst { + break + } + off2 := auxIntToInt64(v_0.AuxInt) + ptr := v_0.Args[0] + val1 := v_1 + val2 := v_2 + mem := v_3 + if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { + break + } + v.reset(OpARM64FSTPQ) + v.AuxInt = int32ToAuxInt(off1 + int32(off2)) + v.Aux = symToAux(sym) + v.AddArg4(ptr, val1, val2, mem) + return true + } + // match: (FSTPQ [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) + // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) + // result: (FSTPQ [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) + for { + off1 := auxIntToInt32(v.AuxInt) + sym1 := auxToSym(v.Aux) + if v_0.Op != OpARM64MOVDaddr { + break + } + off2 := auxIntToInt32(v_0.AuxInt) + sym2 := auxToSym(v_0.Aux) + ptr := v_0.Args[0] + val1 := v_1 + val2 := v_2 + mem := v_3 + if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { + break + } + v.reset(OpARM64FSTPQ) + v.AuxInt = int32ToAuxInt(off1 + off2) + v.Aux = symToAux(mergeSym(sym1, sym2)) + v.AddArg4(ptr, val1, val2, mem) + return true + } + return false +} func rewriteValueARM64_OpARM64FSUBD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -12556,6 +14114,54 @@ func rewriteValueARM64_OpARM64MUL(v *Value) bool { } break } + // match: (MUL r:(MOVWUreg x) s:(MOVWUreg y)) + // cond: r.Uses == 1 && s.Uses == 1 + // result: (UMULL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + r := v_0 + if r.Op != OpARM64MOVWUreg { + continue + } + x := r.Args[0] + s := v_1 + if s.Op != OpARM64MOVWUreg { + continue + } + y := s.Args[0] + if !(r.Uses == 1 && s.Uses == 1) { + continue + } + v.reset(OpARM64UMULL) + v.AddArg2(x, y) + return true + } + break + } + // match: (MUL r:(MOVWreg x) s:(MOVWreg y)) + // cond: r.Uses == 1 && s.Uses == 1 + // result: (MULL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + r := v_0 + if r.Op != OpARM64MOVWreg { + continue + } + x := r.Args[0] + s := v_1 + if s.Op != OpARM64MOVWreg { + continue + } + y := s.Args[0] + if !(r.Uses == 1 && s.Uses == 1) { + continue + } + v.reset(OpARM64MULL) + v.AddArg2(x, y) + return true + } + break + } return false } func rewriteValueARM64_OpARM64MULW(v *Value) bool { @@ -14266,6 +15872,21 @@ func rewriteValueARM64_OpARM64REV(v *Value) bool { } return false } +func rewriteValueARM64_OpARM64REV16(v *Value) bool { + v_0 := v.Args[0] + // match: (REV16 (MOVWUreg x)) + // result: (REV16W x) + for { + if v_0.Op != OpARM64MOVWUreg { + break + } + x := v_0.Args[0] + v.reset(OpARM64REV16W) + v.AddArg(x) + return true + } + return false +} func rewriteValueARM64_OpARM64REVW(v *Value) bool { v_0 := v.Args[0] // match: (REVW (REVW p)) @@ -14391,7 +16012,7 @@ func rewriteValueARM64_OpARM64SBFX(v *Value) bool { return true } // match: (SBFX [bfc] s:(SLLconst [sc] x)) - // cond: s.Uses == 1 && sc > bfc.lsb() + // cond: s.Uses == 1 && sc > bfc.lsb() && sc < bfc.lsb()+bfc.width() // result: (SBFIZ [armBFAuxInt(sc - bfc.lsb(), bfc.width() - (sc-bfc.lsb()))] x) for { bfc := auxIntToArm64BitField(v.AuxInt) @@ -14401,7 +16022,7 @@ func rewriteValueARM64_OpARM64SBFX(v *Value) bool { } sc := auxIntToInt64(s.AuxInt) x := s.Args[0] - if !(s.Uses == 1 && sc > bfc.lsb()) { + if !(s.Uses == 1 && sc > bfc.lsb() && sc < bfc.lsb()+bfc.width()) { break } v.reset(OpARM64SBFIZ) @@ -16363,1488 +17984,2349 @@ func rewriteValueARM64_OpARM64UMODW(v *Value) bool { } return false } -func rewriteValueARM64_OpARM64XOR(v *Value) bool { +func rewriteValueARM64_OpARM64VBIF16B(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (XOR x (MOVDconst [c])) - // result: (XORconst [c] x) + // match: (VBIF16B x y (VNOT16B mask)) + // result: (VBIT16B x y mask) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpARM64MOVDconst { - continue - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpARM64XORconst) - v.AuxInt = int64ToAuxInt(c) - v.AddArg(x) - return true + x := v_0 + y := v_1 + if v_2.Op != OpARM64VNOT16B { + break } - break + mask := v_2.Args[0] + v.reset(OpARM64VBIT16B) + v.AddArg3(x, y, mask) + return true } - // match: (XOR x x) - // result: (MOVDconst [0]) + return false +} +func rewriteValueARM64_OpARM64VBIT16B(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VBIT16B x y (VNOT16B mask)) + // result: (VBIF16B x y mask) for { x := v_0 - if x != v_1 { + y := v_1 + if v_2.Op != OpARM64VNOT16B { break } - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(0) + mask := v_2.Args[0] + v.reset(OpARM64VBIF16B) + v.AddArg3(x, y, mask) return true } - // match: (XOR x (MVN y)) - // result: (EON x y) + return false +} +func rewriteValueARM64_OpARM64VDUPBbcast(v *Value) bool { + v_0 := v.Args[0] + // match: (VDUPBbcast [i] (VMOVBins [j] _ (MOVDconst [c]))) + // cond: i == j && c>=-128 && c<=255 + // result: (VMOVI16B [uint8(c)]) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpARM64MVN { - continue - } - y := v_1.Args[0] - v.reset(OpARM64EON) - v.AddArg2(x, y) - return true + i := auxIntToUint8(v.AuxInt) + if v_0.Op != OpARM64VMOVBins { + break } - break + j := auxIntToUint8(v_0.AuxInt) + _ = v_0.Args[1] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpARM64MOVDconst { + break + } + c := auxIntToInt64(v_0_1.AuxInt) + if !(i == j && c >= -128 && c <= 255) { + break + } + v.reset(OpARM64VMOVI16B) + v.AuxInt = uint8ToAuxInt(uint8(c)) + return true } - // match: (XOR x0 x1:(SLLconst [c] y)) - // cond: clobberIfDead(x1) - // result: (XORshiftLL x0 y [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - x1 := v_1 - if x1.Op != OpARM64SLLconst { - continue - } - c := auxIntToInt64(x1.AuxInt) - y := x1.Args[0] - if !(clobberIfDead(x1)) { - continue - } - v.reset(OpARM64XORshiftLL) - v.AuxInt = int64ToAuxInt(c) - v.AddArg2(x0, y) - return true - } - break - } - // match: (XOR x0 x1:(SRLconst [c] y)) - // cond: clobberIfDead(x1) - // result: (XORshiftRL x0 y [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - x1 := v_1 - if x1.Op != OpARM64SRLconst { - continue - } - c := auxIntToInt64(x1.AuxInt) - y := x1.Args[0] - if !(clobberIfDead(x1)) { - continue - } - v.reset(OpARM64XORshiftRL) - v.AuxInt = int64ToAuxInt(c) - v.AddArg2(x0, y) - return true - } - break - } - // match: (XOR x0 x1:(SRAconst [c] y)) - // cond: clobberIfDead(x1) - // result: (XORshiftRA x0 y [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - x1 := v_1 - if x1.Op != OpARM64SRAconst { - continue - } - c := auxIntToInt64(x1.AuxInt) - y := x1.Args[0] - if !(clobberIfDead(x1)) { - continue - } - v.reset(OpARM64XORshiftRA) - v.AuxInt = int64ToAuxInt(c) - v.AddArg2(x0, y) - return true - } - break - } - // match: (XOR x0 x1:(RORconst [c] y)) - // cond: clobberIfDead(x1) - // result: (XORshiftRO x0 y [c]) + return false +} +func rewriteValueARM64_OpARM64VFCVTL4S(v *Value) bool { + v_0 := v.Args[0] + // match: (VFCVTL4S (VDUPDextr [1] x)) + // result: (VFCVTL2_4S x) for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - x1 := v_1 - if x1.Op != OpARM64RORconst { - continue - } - c := auxIntToInt64(x1.AuxInt) - y := x1.Args[0] - if !(clobberIfDead(x1)) { - continue - } - v.reset(OpARM64XORshiftRO) - v.AuxInt = int64ToAuxInt(c) - v.AddArg2(x0, y) - return true + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break } - break + x := v_0.Args[0] + v.reset(OpARM64VFCVTL2_4S) + v.AddArg(x) + return true } return false } -func rewriteValueARM64_OpARM64XORconst(v *Value) bool { +func rewriteValueARM64_OpARM64VMOVDins0(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (XORconst [0] x) - // result: x + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VFCVTN2D y))) + // result: (VFCVTN2_2D dst y) for { - if auxIntToInt64(v.AuxInt) != 0 { + if auxIntToUint8(v.AuxInt) != 1 { break } - x := v_0 - v.copyOf(x) + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VFCVTN2D { + break + } + y := v_1_0.Args[0] + v.reset(OpARM64VFCVTN2_2D) + v.AddArg2(dst, y) return true } - // match: (XORconst [-1] x) - // result: (MVN x) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VSHRN2D [c] y))) + // result: (VSHRN2_2D dst [c] y) for { - if auxIntToInt64(v.AuxInt) != -1 { + if auxIntToUint8(v.AuxInt) != 1 { break } - x := v_0 - v.reset(OpARM64MVN) - v.AddArg(x) + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VSHRN2D { + break + } + c := auxIntToUint8(v_1_0.AuxInt) + y := v_1_0.Args[0] + v.reset(OpARM64VSHRN2_2D) + v.AuxInt = uint8ToAuxInt(c) + v.AddArg2(dst, y) return true } - // match: (XORconst [c] (MOVDconst [d])) - // result: (MOVDconst [c^d]) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VSHRN4S [c] y))) + // result: (VSHRN2_4S dst [c] y) for { - c := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64MOVDconst { + if auxIntToUint8(v.AuxInt) != 1 { break } - d := auxIntToInt64(v_0.AuxInt) - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(c ^ d) + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VSHRN4S { + break + } + c := auxIntToUint8(v_1_0.AuxInt) + y := v_1_0.Args[0] + v.reset(OpARM64VSHRN2_4S) + v.AuxInt = uint8ToAuxInt(c) + v.AddArg2(dst, y) return true } - // match: (XORconst [c] (XORconst [d] x)) - // result: (XORconst [c^d] x) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VSHRN8H [c] y))) + // result: (VSHRN2_8H dst [c] y) for { - c := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64XORconst { + if auxIntToUint8(v.AuxInt) != 1 { break } - d := auxIntToInt64(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpARM64XORconst) - v.AuxInt = int64ToAuxInt(c ^ d) - v.AddArg(x) + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VSHRN8H { + break + } + c := auxIntToUint8(v_1_0.AuxInt) + y := v_1_0.Args[0] + v.reset(OpARM64VSHRN2_8H) + v.AuxInt = uint8ToAuxInt(c) + v.AddArg2(dst, y) return true } - return false -} -func rewriteValueARM64_OpARM64XORshiftLL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (XORshiftLL (MOVDconst [c]) x [d]) - // result: (XORconst [c] (SLLconst x [d])) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTN2D y))) + // result: (VSQXTN2_2D dst y) for { - d := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64MOVDconst { + if auxIntToUint8(v.AuxInt) != 1 { break } - c := auxIntToInt64(v_0.AuxInt) - x := v_1 - v.reset(OpARM64XORconst) - v.AuxInt = int64ToAuxInt(c) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) - v0.AuxInt = int64ToAuxInt(d) - v0.AddArg(x) - v.AddArg(v0) + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VSQXTN2D { + break + } + y := v_1_0.Args[0] + v.reset(OpARM64VSQXTN2_2D) + v.AddArg2(dst, y) return true } - // match: (XORshiftLL x (MOVDconst [c]) [d]) - // result: (XORconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) - // result: (REV16W x) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTUN2D y))) + // result: (VSQXTUN2_2D dst y) for { - if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { + if auxIntToUint8(v.AuxInt) != 1 { break } - x := v_0.Args[0] - if x != v_1 { + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { break } - v.reset(OpARM64REV16W) - v.AddArg(x) + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VSQXTUN2D { + break + } + y := v_1_0.Args[0] + v.reset(OpARM64VSQXTUN2_2D) + v.AddArg2(dst, y) return true } - // match: (XORshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) - // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff - // result: (REV16W x) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTUN4S y))) + // result: (VSQXTUN2_4S dst y) for { - if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpARM64ANDconst { + if auxIntToUint8(v.AuxInt) != 1 { break } - c1 := auxIntToInt64(v_0_0.AuxInt) - x := v_0_0.Args[0] - if v_1.Op != OpARM64ANDconst { + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { break } - c2 := auxIntToInt64(v_1.AuxInt) - if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VSQXTUN4S { break } - v.reset(OpARM64REV16W) - v.AddArg(x) + y := v_1_0.Args[0] + v.reset(OpARM64VSQXTUN2_4S) + v.AddArg2(dst, y) return true } - // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) - // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) - // result: (REV16 x) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTUN8H y))) + // result: (VSQXTUN2_8H dst y) for { - if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpARM64ANDconst { + if auxIntToUint8(v.AuxInt) != 1 { break } - c1 := auxIntToInt64(v_0_0.AuxInt) - x := v_0_0.Args[0] - if v_1.Op != OpARM64ANDconst { + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { break } - c2 := auxIntToInt64(v_1.AuxInt) - if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VSQXTUN8H { break } - v.reset(OpARM64REV16) - v.AddArg(x) + y := v_1_0.Args[0] + v.reset(OpARM64VSQXTUN2_8H) + v.AddArg2(dst, y) return true } - // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) - // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) - // result: (REV16 (ANDconst [0xffffffff] x)) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VUQXTN2D y))) + // result: (VUQXTN2_2D dst y) for { - if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpARM64ANDconst { + if auxIntToUint8(v.AuxInt) != 1 { break } - c1 := auxIntToInt64(v_0_0.AuxInt) - x := v_0_0.Args[0] - if v_1.Op != OpARM64ANDconst { + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { break } - c2 := auxIntToInt64(v_1.AuxInt) - if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VUQXTN2D { break } - v.reset(OpARM64REV16) - v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) - v0.AuxInt = int64ToAuxInt(0xffffffff) - v0.AddArg(x) - v.AddArg(v0) + y := v_1_0.Args[0] + v.reset(OpARM64VUQXTN2_2D) + v.AddArg2(dst, y) return true } - // match: (XORshiftLL [c] (SRLconst x [64-c]) x2) - // result: (EXTRconst [64-c] x2 x) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VUQXTN4S y))) + // result: (VUQXTN2_4S dst y) for { - c := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { + if auxIntToUint8(v.AuxInt) != 1 { break } - x := v_0.Args[0] - x2 := v_1 - v.reset(OpARM64EXTRconst) - v.AuxInt = int64ToAuxInt(64 - c) - v.AddArg2(x2, x) - return true - } - // match: (XORshiftLL [c] (UBFX [bfc] x) x2) - // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) - // result: (EXTRWconst [32-c] x2 x) - for { - t := v.Type - c := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64UBFX { + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { break } - bfc := auxIntToArm64BitField(v_0.AuxInt) - x := v_0.Args[0] - x2 := v_1 - if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VUQXTN4S { break } - v.reset(OpARM64EXTRWconst) - v.AuxInt = int64ToAuxInt(32 - c) - v.AddArg2(x2, x) + y := v_1_0.Args[0] + v.reset(OpARM64VUQXTN2_4S) + v.AddArg2(dst, y) return true } - return false -} -func rewriteValueARM64_OpARM64XORshiftRA(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (XORshiftRA (MOVDconst [c]) x [d]) - // result: (XORconst [c] (SRAconst x [d])) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VUQXTN8H y))) + // result: (VUQXTN2_8H dst y) for { - d := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64MOVDconst { + if auxIntToUint8(v.AuxInt) != 1 { break } - c := auxIntToInt64(v_0.AuxInt) - x := v_1 - v.reset(OpARM64XORconst) - v.AuxInt = int64ToAuxInt(c) - v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) - v0.AuxInt = int64ToAuxInt(d) - v0.AddArg(x) - v.AddArg(v0) + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VUQXTN8H { + break + } + y := v_1_0.Args[0] + v.reset(OpARM64VUQXTN2_8H) + v.AddArg2(dst, y) return true } - // match: (XORshiftRA x (MOVDconst [c]) [d]) - // result: (XORconst x [c>>uint64(d)]) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VXTN2D y))) + // result: (VXTN2_2D dst y) for { - d := auxIntToInt64(v.AuxInt) - x := v_0 - if v_1.Op != OpARM64MOVDconst { + if auxIntToUint8(v.AuxInt) != 1 { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpARM64XORconst) - v.AuxInt = int64ToAuxInt(c >> uint64(d)) - v.AddArg(x) + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VXTN2D { + break + } + y := v_1_0.Args[0] + v.reset(OpARM64VXTN2_2D) + v.AddArg2(dst, y) return true } - // match: (XORshiftRA (SRAconst x [c]) x [c]) - // result: (MOVDconst [0]) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VXTN4S y))) + // result: (VXTN2_4S dst y) for { - c := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { + if auxIntToUint8(v.AuxInt) != 1 { break } - x := v_0.Args[0] - if x != v_1 { + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { break } - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(0) + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VXTN4S { + break + } + y := v_1_0.Args[0] + v.reset(OpARM64VXTN2_4S) + v.AddArg2(dst, y) return true } - return false -} -func rewriteValueARM64_OpARM64XORshiftRL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (XORshiftRL (MOVDconst [c]) x [d]) - // result: (XORconst [c] (SRLconst x [d])) + // match: (VMOVDins0 [1] dst (VDUPDextr [0] (VXTN8H y))) + // result: (VXTN2_8H dst y) for { - d := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64MOVDconst { + if auxIntToUint8(v.AuxInt) != 1 { break } - c := auxIntToInt64(v_0.AuxInt) - x := v_1 - v.reset(OpARM64XORconst) - v.AuxInt = int64ToAuxInt(c) - v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) - v0.AuxInt = int64ToAuxInt(d) - v0.AddArg(x) - v.AddArg(v0) + dst := v_0 + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 0 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpARM64VXTN8H { + break + } + y := v_1_0.Args[0] + v.reset(OpARM64VXTN2_8H) + v.AddArg2(dst, y) return true } - // match: (XORshiftRL x (MOVDconst [c]) [d]) - // result: (XORconst x [int64(uint64(c)>>uint64(d))]) + // match: (VMOVDins0 [0] (VMOVI16B [0]) y:(VDUPDextr [i] _)) + // result: y for { - d := auxIntToInt64(v.AuxInt) - x := v_0 - if v_1.Op != OpARM64MOVDconst { + if auxIntToUint8(v.AuxInt) != 0 || v_0.Op != OpARM64VMOVI16B || auxIntToUint8(v_0.AuxInt) != 0 { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpARM64XORconst) - v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) - v.AddArg(x) + y := v_1 + if y.Op != OpARM64VDUPDextr { + break + } + v.copyOf(y) return true } - // match: (XORshiftRL (SRLconst x [c]) x [c]) - // result: (MOVDconst [0]) + return false +} +func rewriteValueARM64_OpARM64VMOVSins0(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VMOVSins0 [0] (VMOVI16B [0]) y:(VDUPSextr [i] _)) + // result: y for { - c := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { + if auxIntToUint8(v.AuxInt) != 0 || v_0.Op != OpARM64VMOVI16B || auxIntToUint8(v_0.AuxInt) != 0 { break } - x := v_0.Args[0] - if x != v_1 { + y := v_1 + if y.Op != OpARM64VDUPSextr { break } - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(0) + v.copyOf(y) return true } return false } -func rewriteValueARM64_OpARM64XORshiftRO(v *Value) bool { +func rewriteValueARM64_OpARM64VPMULL2D(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (XORshiftRO (MOVDconst [c]) x [d]) - // result: (XORconst [c] (RORconst x [d])) + // match: (VPMULL2D (VDUPDextr [1] x) (VDUPDextr [1] y)) + // result: (VPMULL2_2D x y) for { - d := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpARM64VPMULL2_2D) + v.AddArg2(x, y) + return true } - c := auxIntToInt64(v_0.AuxInt) - x := v_1 - v.reset(OpARM64XORconst) - v.AuxInt = int64ToAuxInt(c) - v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) - v0.AuxInt = int64ToAuxInt(d) - v0.AddArg(x) - v.AddArg(v0) - return true + break } - // match: (XORshiftRO x (MOVDconst [c]) [d]) - // result: (XORconst x [rotateRight64(c, d)]) + return false +} +func rewriteValueARM64_OpARM64VSHL16B(v *Value) bool { + v_0 := v.Args[0] + // match: (VSHL16B [a] x) + // cond: a==0 + // result: x for { - d := auxIntToInt64(v.AuxInt) + a := auxIntToUint8(v.AuxInt) x := v_0 - if v_1.Op != OpARM64MOVDconst { + if !(a == 0) { break } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpARM64XORconst) - v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) - v.AddArg(x) + v.copyOf(x) return true } - // match: (XORshiftRO (RORconst x [c]) x [c]) - // result: (MOVDconst [0]) + return false +} +func rewriteValueARM64_OpARM64VSHL2D(v *Value) bool { + v_0 := v.Args[0] + // match: (VSHL2D [a] x) + // cond: a==0 + // result: x for { - c := auxIntToInt64(v.AuxInt) - if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { - break - } - x := v_0.Args[0] - if x != v_1 { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { break } - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(0) + v.copyOf(x) return true } return false } -func rewriteValueARM64_OpAddr(v *Value) bool { +func rewriteValueARM64_OpARM64VSHL4S(v *Value) bool { v_0 := v.Args[0] - // match: (Addr {sym} base) - // result: (MOVDaddr {sym} base) + // match: (VSHL4S [a] x) + // cond: a==0 + // result: x for { - sym := auxToSym(v.Aux) - base := v_0 - v.reset(OpARM64MOVDaddr) - v.Aux = symToAux(sym) - v.AddArg(base) + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpAvg64u(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VSHL8H(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Avg64u x y) - // result: (ADD (SRLconst (SUB x y) [1]) y) + // match: (VSHL8H [a] x) + // cond: a==0 + // result: x for { - t := v.Type + a := auxIntToUint8(v.AuxInt) x := v_0 - y := v_1 - v.reset(OpARM64ADD) - v0 := b.NewValue0(v.Pos, OpARM64SRLconst, t) - v0.AuxInt = int64ToAuxInt(1) - v1 := b.NewValue0(v.Pos, OpARM64SUB, t) - v1.AddArg2(x, y) - v0.AddArg(v1) - v.AddArg2(v0, y) + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpBitLen16(v *Value) bool { +func rewriteValueARM64_OpARM64VSHRN2D(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (BitLen16 x) - // result: (BitLen64 (ZeroExt16to64 x)) + // match: (VSHRN2D [0] x) + // result: (VXTN2D x) for { + if auxIntToUint8(v.AuxInt) != 0 { + break + } x := v_0 - v.reset(OpBitLen64) - v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v0.AddArg(x) - v.AddArg(v0) + v.reset(OpARM64VXTN2D) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpBitLen32(v *Value) bool { +func rewriteValueARM64_OpARM64VSHRN4S(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (BitLen32 x) - // result: (SUB (MOVDconst [32]) (CLZW x)) + // match: (VSHRN4S [0] x) + // result: (VXTN4S x) for { + if auxIntToUint8(v.AuxInt) != 0 { + break + } x := v_0 - v.reset(OpARM64SUB) - v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(32) - v1 := b.NewValue0(v.Pos, OpARM64CLZW, typ.Int) - v1.AddArg(x) - v.AddArg2(v0, v1) + v.reset(OpARM64VXTN4S) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpBitLen64(v *Value) bool { +func rewriteValueARM64_OpARM64VSHRN8H(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (BitLen64 x) - // result: (SUB (MOVDconst [64]) (CLZ x)) + // match: (VSHRN8H [0] x) + // result: (VXTN8H x) for { + if auxIntToUint8(v.AuxInt) != 0 { + break + } x := v_0 - v.reset(OpARM64SUB) - v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(64) - v1 := b.NewValue0(v.Pos, OpARM64CLZ, typ.Int) - v1.AddArg(x) - v.AddArg2(v0, v1) + v.reset(OpARM64VXTN8H) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpBitLen8(v *Value) bool { +func rewriteValueARM64_OpARM64VSMULL16B(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (BitLen8 x) - // result: (BitLen64 (ZeroExt8to64 x)) + // match: (VSMULL16B (VDUPDextr [1] x) (VDUPDextr [1] y)) + // result: (VSMULL2_16B x y) for { - x := v_0 - v.reset(OpBitLen64) - v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v0.AddArg(x) - v.AddArg(v0) - return true + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpARM64VSMULL2_16B) + v.AddArg2(x, y) + return true + } + break } + return false } -func rewriteValueARM64_OpBitRev16(v *Value) bool { +func rewriteValueARM64_OpARM64VSMULL4S(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (BitRev16 x) - // result: (SRLconst [48] (RBIT x)) + // match: (VSMULL4S (VDUPDextr [1] x) (VDUPDextr [1] y)) + // result: (VSMULL2_4S x y) for { - x := v_0 - v.reset(OpARM64SRLconst) - v.AuxInt = int64ToAuxInt(48) - v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) - v0.AddArg(x) - v.AddArg(v0) - return true + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpARM64VSMULL2_4S) + v.AddArg2(x, y) + return true + } + break } + return false } -func rewriteValueARM64_OpBitRev8(v *Value) bool { +func rewriteValueARM64_OpARM64VSMULL8H(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (BitRev8 x) - // result: (SRLconst [56] (RBIT x)) + // match: (VSMULL8H (VDUPDextr [1] x) (VDUPDextr [1] y)) + // result: (VSMULL2_8H x y) for { - x := v_0 - v.reset(OpARM64SRLconst) - v.AuxInt = int64ToAuxInt(56) - v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) - v0.AddArg(x) - v.AddArg(v0) - return true + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpARM64VSMULL2_8H) + v.AddArg2(x, y) + return true + } + break } + return false } -func rewriteValueARM64_OpCondSelect(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VSQSHL16Bconst(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (CondSelect x y boolval) - // cond: flagArg(boolval) != nil - // result: (CSEL [boolval.Op] x y flagArg(boolval)) + // match: (VSQSHL16Bconst [a] x) + // cond: a==0 + // result: x for { + a := auxIntToUint8(v.AuxInt) x := v_0 - y := v_1 - boolval := v_2 - if !(flagArg(boolval) != nil) { + if !(a == 0) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(boolval.Op) - v.AddArg3(x, y, flagArg(boolval)) + v.copyOf(x) return true } - // match: (CondSelect x y boolval) - // cond: flagArg(boolval) == nil - // result: (CSEL [OpARM64NotEqual] x y (TSTWconst [1] boolval)) + return false +} +func rewriteValueARM64_OpARM64VSQSHL2Dconst(v *Value) bool { + v_0 := v.Args[0] + // match: (VSQSHL2Dconst [a] x) + // cond: a==0 + // result: x for { + a := auxIntToUint8(v.AuxInt) x := v_0 - y := v_1 - boolval := v_2 - if !(flagArg(boolval) == nil) { + if !(a == 0) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64NotEqual) - v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(1) - v0.AddArg(boolval) - v.AddArg3(x, y, v0) + v.copyOf(x) return true } return false } -func rewriteValueARM64_OpConst16(v *Value) bool { - // match: (Const16 [val]) - // result: (MOVDconst [int64(val)]) +func rewriteValueARM64_OpARM64VSQSHL4Sconst(v *Value) bool { + v_0 := v.Args[0] + // match: (VSQSHL4Sconst [a] x) + // cond: a==0 + // result: x for { - val := auxIntToInt16(v.AuxInt) - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(int64(val)) + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpConst32(v *Value) bool { - // match: (Const32 [val]) - // result: (MOVDconst [int64(val)]) +func rewriteValueARM64_OpARM64VSQSHL8Hconst(v *Value) bool { + v_0 := v.Args[0] + // match: (VSQSHL8Hconst [a] x) + // cond: a==0 + // result: x for { - val := auxIntToInt32(v.AuxInt) - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(int64(val)) + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpConst32F(v *Value) bool { - // match: (Const32F [val]) - // result: (FMOVSconst [float64(val)]) +func rewriteValueARM64_OpARM64VSSHLL16B(v *Value) bool { + v_0 := v.Args[0] + // match: (VSSHLL16B [a] (VDUPDextr [1] x)) + // result: (VSSHLL2_16B [a] x) for { - val := auxIntToFloat32(v.AuxInt) - v.reset(OpARM64FMOVSconst) - v.AuxInt = float64ToAuxInt(float64(val)) + a := auxIntToUint8(v.AuxInt) + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VSSHLL2_16B) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpConst64(v *Value) bool { - // match: (Const64 [val]) - // result: (MOVDconst [int64(val)]) +func rewriteValueARM64_OpARM64VSSHLL4S(v *Value) bool { + v_0 := v.Args[0] + // match: (VSSHLL4S [a] (VDUPDextr [1] x)) + // result: (VSSHLL2_4S [a] x) for { - val := auxIntToInt64(v.AuxInt) - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(int64(val)) + a := auxIntToUint8(v.AuxInt) + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VSSHLL2_4S) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpConst64F(v *Value) bool { - // match: (Const64F [val]) - // result: (FMOVDconst [float64(val)]) +func rewriteValueARM64_OpARM64VSSHLL8H(v *Value) bool { + v_0 := v.Args[0] + // match: (VSSHLL8H [a] (VDUPDextr [1] x)) + // result: (VSSHLL2_8H [a] x) for { - val := auxIntToFloat64(v.AuxInt) - v.reset(OpARM64FMOVDconst) - v.AuxInt = float64ToAuxInt(float64(val)) + a := auxIntToUint8(v.AuxInt) + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VSSHLL2_8H) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpConst8(v *Value) bool { - // match: (Const8 [val]) - // result: (MOVDconst [int64(val)]) +func rewriteValueARM64_OpARM64VSSHR16B(v *Value) bool { + v_0 := v.Args[0] + // match: (VSSHR16B [a] x) + // cond: a==0 + // result: x for { - val := auxIntToInt8(v.AuxInt) - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(int64(val)) + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpConstBool(v *Value) bool { - // match: (ConstBool [t]) - // result: (MOVDconst [b2i(t)]) +func rewriteValueARM64_OpARM64VSSHR2D(v *Value) bool { + v_0 := v.Args[0] + // match: (VSSHR2D [a] x) + // cond: a==0 + // result: x for { - t := auxIntToBool(v.AuxInt) - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(b2i(t)) + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpConstNil(v *Value) bool { - // match: (ConstNil) - // result: (MOVDconst [0]) +func rewriteValueARM64_OpARM64VSSHR4S(v *Value) bool { + v_0 := v.Args[0] + // match: (VSSHR4S [a] x) + // cond: a==0 + // result: x for { - v.reset(OpARM64MOVDconst) - v.AuxInt = int64ToAuxInt(0) + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpCtz16(v *Value) bool { +func rewriteValueARM64_OpARM64VSSHR8H(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Ctz16 x) - // result: (CLZW (RBITW (ORconst [0x10000] x))) + // match: (VSSHR8H [a] x) + // cond: a==0 + // result: x for { - t := v.Type + a := auxIntToUint8(v.AuxInt) x := v_0 - v.reset(OpARM64CLZW) - v.Type = t - v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) - v1.AuxInt = int64ToAuxInt(0x10000) - v1.AddArg(x) - v0.AddArg(v1) - v.AddArg(v0) + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpCtz32(v *Value) bool { +func rewriteValueARM64_OpARM64VSXTL16B(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Ctz32 x) - // result: (CLZW (RBITW x)) + // match: (VSXTL16B (VDUPDextr [1] x)) + // result: (VSXTL2_16B x) for { - t := v.Type - x := v_0 - v.reset(OpARM64CLZW) - v0 := b.NewValue0(v.Pos, OpARM64RBITW, t) - v0.AddArg(x) - v.AddArg(v0) + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VSXTL2_16B) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpCtz64(v *Value) bool { +func rewriteValueARM64_OpARM64VSXTL4S(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Ctz64 x) - // result: (CLZ (RBIT x)) + // match: (VSXTL4S (VDUPDextr [1] x)) + // result: (VSXTL2_4S x) for { - t := v.Type - x := v_0 - v.reset(OpARM64CLZ) - v0 := b.NewValue0(v.Pos, OpARM64RBIT, t) - v0.AddArg(x) - v.AddArg(v0) + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VSXTL2_4S) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpCtz8(v *Value) bool { +func rewriteValueARM64_OpARM64VSXTL8H(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Ctz8 x) - // result: (CLZW (RBITW (ORconst [0x100] x))) + // match: (VSXTL8H (VDUPDextr [1] x)) + // result: (VSXTL2_8H x) for { - t := v.Type - x := v_0 - v.reset(OpARM64CLZW) - v.Type = t - v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) - v1.AuxInt = int64ToAuxInt(0x100) - v1.AddArg(x) - v0.AddArg(v1) - v.AddArg(v0) + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VSXTL2_8H) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpDiv16(v *Value) bool { +func rewriteValueARM64_OpARM64VUMULL16B(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div16 [false] x y) - // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) + // match: (VUMULL16B (VDUPDextr [1] x) (VDUPDextr [1] y)) + // result: (VUMULL2_16B x y) for { - if auxIntToBool(v.AuxInt) != false { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpARM64VUMULL2_16B) + v.AddArg2(x, y) + return true } - x := v_0 - y := v_1 - v.reset(OpARM64DIVW) - v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(y) - v.AddArg2(v0, v1) - return true + break } return false } -func rewriteValueARM64_OpDiv16u(v *Value) bool { +func rewriteValueARM64_OpARM64VUMULL4S(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div16u x y) - // result: (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y)) + // match: (VUMULL4S (VDUPDextr [1] x) (VDUPDextr [1] y)) + // result: (VUMULL2_4S x y) for { - x := v_0 - y := v_1 - v.reset(OpARM64UDIVW) - v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) - v1.AddArg(y) - v.AddArg2(v0, v1) - return true + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpARM64VUMULL2_4S) + v.AddArg2(x, y) + return true + } + break } + return false } -func rewriteValueARM64_OpDiv32(v *Value) bool { +func rewriteValueARM64_OpARM64VUMULL8H(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (Div32 [false] x y) - // result: (DIVW x y) + // match: (VUMULL8H (VDUPDextr [1] x) (VDUPDextr [1] y)) + // result: (VUMULL2_8H x y) for { - if auxIntToBool(v.AuxInt) != false { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpARM64VDUPDextr || auxIntToUint8(v_1.AuxInt) != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpARM64VUMULL2_8H) + v.AddArg2(x, y) + return true } - x := v_0 - y := v_1 - v.reset(OpARM64DIVW) - v.AddArg2(x, y) - return true + break } return false } -func rewriteValueARM64_OpDiv64(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VUQSHL16Bconst(v *Value) bool { v_0 := v.Args[0] - // match: (Div64 [false] x y) - // result: (DIV x y) + // match: (VUQSHL16Bconst [a] x) + // cond: a==0 + // result: x for { - if auxIntToBool(v.AuxInt) != false { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { break } - x := v_0 - y := v_1 - v.reset(OpARM64DIV) - v.AddArg2(x, y) + v.copyOf(x) return true } return false } -func rewriteValueARM64_OpDiv8(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VUQSHL2Dconst(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div8 x y) - // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) + // match: (VUQSHL2Dconst [a] x) + // cond: a==0 + // result: x for { + a := auxIntToUint8(v.AuxInt) x := v_0 - y := v_1 - v.reset(OpARM64DIVW) - v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(y) - v.AddArg2(v0, v1) + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpDiv8u(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VUQSHL4Sconst(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Div8u x y) - // result: (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y)) + // match: (VUQSHL4Sconst [a] x) + // cond: a==0 + // result: x for { + a := auxIntToUint8(v.AuxInt) x := v_0 - y := v_1 - v.reset(OpARM64UDIVW) - v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) - v1.AddArg(y) - v.AddArg2(v0, v1) + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpEq16(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VUQSHL8Hconst(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Eq16 x y) - // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) + // match: (VUQSHL8Hconst [a] x) + // cond: a==0 + // result: x for { + a := auxIntToUint8(v.AuxInt) x := v_0 - y := v_1 - v.reset(OpARM64Equal) - v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpEq32(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VUSHLL16B(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Eq32 x y) - // result: (Equal (CMPW x y)) + // match: (VUSHLL16B [a] (VDUPDextr [1] x)) + // result: (VUSHLL2_16B [a] x) for { - x := v_0 - y := v_1 - v.reset(OpARM64Equal) - v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + a := auxIntToUint8(v.AuxInt) + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VUSHLL2_16B) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpEq32F(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VUSHLL4S(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Eq32F x y) - // result: (Equal (FCMPS x y)) + // match: (VUSHLL4S [a] (VDUPDextr [1] x)) + // result: (VUSHLL2_4S [a] x) for { - x := v_0 - y := v_1 - v.reset(OpARM64Equal) - v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + a := auxIntToUint8(v.AuxInt) + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VUSHLL2_4S) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpEq64(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VUSHLL8H(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Eq64 x y) - // result: (Equal (CMP x y)) + // match: (VUSHLL8H [a] (VDUPDextr [1] x)) + // result: (VUSHLL2_8H [a] x) for { - x := v_0 - y := v_1 - v.reset(OpARM64Equal) - v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + a := auxIntToUint8(v.AuxInt) + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VUSHLL2_8H) + v.AuxInt = uint8ToAuxInt(a) + v.AddArg(x) return true } + return false } -func rewriteValueARM64_OpEq64F(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VUSHR16B(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Eq64F x y) - // result: (Equal (FCMPD x y)) + // match: (VUSHR16B [a] x) + // cond: a==0 + // result: x for { + a := auxIntToUint8(v.AuxInt) x := v_0 - y := v_1 - v.reset(OpARM64Equal) - v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpEq8(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VUSHR2D(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Eq8 x y) - // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) + // match: (VUSHR2D [a] x) + // cond: a==0 + // result: x for { + a := auxIntToUint8(v.AuxInt) x := v_0 - y := v_1 - v.reset(OpARM64Equal) - v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpEqB(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpARM64VUSHR4S(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (EqB x y) - // result: (XOR (MOVDconst [1]) (XOR x y)) + // match: (VUSHR4S [a] x) + // cond: a==0 + // result: x for { + a := auxIntToUint8(v.AuxInt) x := v_0 - y := v_1 - v.reset(OpARM64XOR) - v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(1) - v1 := b.NewValue0(v.Pos, OpARM64XOR, typ.Bool) - v1.AddArg2(x, y) - v.AddArg2(v0, v1) + if !(a == 0) { + break + } + v.copyOf(x) return true } + return false } -func rewriteValueARM64_OpEqPtr(v *Value) bool { +func rewriteValueARM64_OpARM64VUSHR8H(v *Value) bool { + v_0 := v.Args[0] + // match: (VUSHR8H [a] x) + // cond: a==0 + // result: x + for { + a := auxIntToUint8(v.AuxInt) + x := v_0 + if !(a == 0) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueARM64_OpARM64VUXTL16B(v *Value) bool { + v_0 := v.Args[0] + // match: (VUXTL16B (VDUPDextr [1] x)) + // result: (VUXTL2_16B x) + for { + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VUXTL2_16B) + v.AddArg(x) + return true + } + return false +} +func rewriteValueARM64_OpARM64VUXTL4S(v *Value) bool { + v_0 := v.Args[0] + // match: (VUXTL4S (VDUPDextr [1] x)) + // result: (VUXTL2_4S x) + for { + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VUXTL2_4S) + v.AddArg(x) + return true + } + return false +} +func rewriteValueARM64_OpARM64VUXTL8H(v *Value) bool { + v_0 := v.Args[0] + // match: (VUXTL8H (VDUPDextr [1] x)) + // result: (VUXTL2_8H x) + for { + if v_0.Op != OpARM64VDUPDextr || auxIntToUint8(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + v.reset(OpARM64VUXTL2_8H) + v.AddArg(x) + return true + } + return false +} +func rewriteValueARM64_OpARM64XOR(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (XOR x (MOVDconst [c])) + // result: (XORconst [c] x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpARM64MOVDconst { + continue + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpARM64XORconst) + v.AuxInt = int64ToAuxInt(c) + v.AddArg(x) + return true + } + break + } + // match: (XOR x x) + // result: (MOVDconst [0]) + for { + x := v_0 + if x != v_1 { + break + } + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(0) + return true + } + // match: (XOR x (MVN y)) + // result: (EON x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpARM64MVN { + continue + } + y := v_1.Args[0] + v.reset(OpARM64EON) + v.AddArg2(x, y) + return true + } + break + } + // match: (XOR x0 x1:(SLLconst [c] y)) + // cond: clobberIfDead(x1) + // result: (XORshiftLL x0 y [c]) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x0 := v_0 + x1 := v_1 + if x1.Op != OpARM64SLLconst { + continue + } + c := auxIntToInt64(x1.AuxInt) + y := x1.Args[0] + if !(clobberIfDead(x1)) { + continue + } + v.reset(OpARM64XORshiftLL) + v.AuxInt = int64ToAuxInt(c) + v.AddArg2(x0, y) + return true + } + break + } + // match: (XOR x0 x1:(SRLconst [c] y)) + // cond: clobberIfDead(x1) + // result: (XORshiftRL x0 y [c]) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x0 := v_0 + x1 := v_1 + if x1.Op != OpARM64SRLconst { + continue + } + c := auxIntToInt64(x1.AuxInt) + y := x1.Args[0] + if !(clobberIfDead(x1)) { + continue + } + v.reset(OpARM64XORshiftRL) + v.AuxInt = int64ToAuxInt(c) + v.AddArg2(x0, y) + return true + } + break + } + // match: (XOR x0 x1:(SRAconst [c] y)) + // cond: clobberIfDead(x1) + // result: (XORshiftRA x0 y [c]) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x0 := v_0 + x1 := v_1 + if x1.Op != OpARM64SRAconst { + continue + } + c := auxIntToInt64(x1.AuxInt) + y := x1.Args[0] + if !(clobberIfDead(x1)) { + continue + } + v.reset(OpARM64XORshiftRA) + v.AuxInt = int64ToAuxInt(c) + v.AddArg2(x0, y) + return true + } + break + } + // match: (XOR x0 x1:(RORconst [c] y)) + // cond: clobberIfDead(x1) + // result: (XORshiftRO x0 y [c]) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x0 := v_0 + x1 := v_1 + if x1.Op != OpARM64RORconst { + continue + } + c := auxIntToInt64(x1.AuxInt) + y := x1.Args[0] + if !(clobberIfDead(x1)) { + continue + } + v.reset(OpARM64XORshiftRO) + v.AuxInt = int64ToAuxInt(c) + v.AddArg2(x0, y) + return true + } + break + } + return false +} +func rewriteValueARM64_OpARM64XORconst(v *Value) bool { + v_0 := v.Args[0] + // match: (XORconst [0] x) + // result: x + for { + if auxIntToInt64(v.AuxInt) != 0 { + break + } + x := v_0 + v.copyOf(x) + return true + } + // match: (XORconst [-1] x) + // result: (MVN x) + for { + if auxIntToInt64(v.AuxInt) != -1 { + break + } + x := v_0 + v.reset(OpARM64MVN) + v.AddArg(x) + return true + } + // match: (XORconst [c] (MOVDconst [d])) + // result: (MOVDconst [c^d]) + for { + c := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64MOVDconst { + break + } + d := auxIntToInt64(v_0.AuxInt) + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(c ^ d) + return true + } + // match: (XORconst [c] (XORconst [d] x)) + // result: (XORconst [c^d] x) + for { + c := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64XORconst { + break + } + d := auxIntToInt64(v_0.AuxInt) + x := v_0.Args[0] + v.reset(OpARM64XORconst) + v.AuxInt = int64ToAuxInt(c ^ d) + v.AddArg(x) + return true + } + return false +} +func rewriteValueARM64_OpARM64XORshiftLL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (XORshiftLL (MOVDconst [c]) x [d]) + // result: (XORconst [c] (SLLconst x [d])) + for { + d := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64MOVDconst { + break + } + c := auxIntToInt64(v_0.AuxInt) + x := v_1 + v.reset(OpARM64XORconst) + v.AuxInt = int64ToAuxInt(c) + v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) + v0.AuxInt = int64ToAuxInt(d) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (XORshiftLL x (MOVDconst [c]) [d]) + // result: (XORconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) + // result: (REV16W x) + for { + if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { + break + } + x := v_0.Args[0] + if x != v_1 { + break + } + v.reset(OpARM64REV16W) + v.AddArg(x) + return true + } + // match: (XORshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) + // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff + // result: (REV16W x) + for { + if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpARM64ANDconst { + break + } + c1 := auxIntToInt64(v_0_0.AuxInt) + x := v_0_0.Args[0] + if v_1.Op != OpARM64ANDconst { + break + } + c2 := auxIntToInt64(v_1.AuxInt) + if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { + break + } + v.reset(OpARM64REV16W) + v.AddArg(x) + return true + } + // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) + // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) + // result: (REV16 x) + for { + if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpARM64ANDconst { + break + } + c1 := auxIntToInt64(v_0_0.AuxInt) + x := v_0_0.Args[0] + if v_1.Op != OpARM64ANDconst { + break + } + c2 := auxIntToInt64(v_1.AuxInt) + if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { + break + } + v.reset(OpARM64REV16) + v.AddArg(x) + return true + } + // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) + // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) + // result: (REV16 (ANDconst [0xffffffff] x)) + for { + if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpARM64ANDconst { + break + } + c1 := auxIntToInt64(v_0_0.AuxInt) + x := v_0_0.Args[0] + if v_1.Op != OpARM64ANDconst { + break + } + c2 := auxIntToInt64(v_1.AuxInt) + if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { + break + } + v.reset(OpARM64REV16) + v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) + v0.AuxInt = int64ToAuxInt(0xffffffff) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (XORshiftLL [c] (SRLconst x [64-c]) x2) + // result: (EXTRconst [64-c] x2 x) + for { + c := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { + break + } + x := v_0.Args[0] + x2 := v_1 + v.reset(OpARM64EXTRconst) + v.AuxInt = int64ToAuxInt(64 - c) + v.AddArg2(x2, x) + return true + } + // match: (XORshiftLL [c] (UBFX [bfc] x) x2) + // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) + // result: (EXTRWconst [32-c] x2 x) + for { + t := v.Type + c := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64UBFX { + break + } + bfc := auxIntToArm64BitField(v_0.AuxInt) + x := v_0.Args[0] + x2 := v_1 + if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { + break + } + v.reset(OpARM64EXTRWconst) + v.AuxInt = int64ToAuxInt(32 - c) + v.AddArg2(x2, x) + return true + } + return false +} +func rewriteValueARM64_OpARM64XORshiftRA(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (XORshiftRA (MOVDconst [c]) x [d]) + // result: (XORconst [c] (SRAconst x [d])) + for { + d := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64MOVDconst { + break + } + c := auxIntToInt64(v_0.AuxInt) + x := v_1 + v.reset(OpARM64XORconst) + v.AuxInt = int64ToAuxInt(c) + v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) + v0.AuxInt = int64ToAuxInt(d) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (XORshiftRA x (MOVDconst [c]) [d]) + // result: (XORconst x [c>>uint64(d)]) + for { + d := auxIntToInt64(v.AuxInt) + x := v_0 + if v_1.Op != OpARM64MOVDconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpARM64XORconst) + v.AuxInt = int64ToAuxInt(c >> uint64(d)) + v.AddArg(x) + return true + } + // match: (XORshiftRA (SRAconst x [c]) x [c]) + // result: (MOVDconst [0]) + for { + c := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { + break + } + x := v_0.Args[0] + if x != v_1 { + break + } + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(0) + return true + } + return false +} +func rewriteValueARM64_OpARM64XORshiftRL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (XORshiftRL (MOVDconst [c]) x [d]) + // result: (XORconst [c] (SRLconst x [d])) + for { + d := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64MOVDconst { + break + } + c := auxIntToInt64(v_0.AuxInt) + x := v_1 + v.reset(OpARM64XORconst) + v.AuxInt = int64ToAuxInt(c) + v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) + v0.AuxInt = int64ToAuxInt(d) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (XORshiftRL x (MOVDconst [c]) [d]) + // result: (XORconst x [int64(uint64(c)>>uint64(d))]) + for { + d := auxIntToInt64(v.AuxInt) + x := v_0 + if v_1.Op != OpARM64MOVDconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpARM64XORconst) + v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) + v.AddArg(x) + return true + } + // match: (XORshiftRL (SRLconst x [c]) x [c]) + // result: (MOVDconst [0]) + for { + c := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { + break + } + x := v_0.Args[0] + if x != v_1 { + break + } + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(0) + return true + } + return false +} +func rewriteValueARM64_OpARM64XORshiftRO(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (XORshiftRO (MOVDconst [c]) x [d]) + // result: (XORconst [c] (RORconst x [d])) + for { + d := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64MOVDconst { + break + } + c := auxIntToInt64(v_0.AuxInt) + x := v_1 + v.reset(OpARM64XORconst) + v.AuxInt = int64ToAuxInt(c) + v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) + v0.AuxInt = int64ToAuxInt(d) + v0.AddArg(x) + v.AddArg(v0) + return true + } + // match: (XORshiftRO x (MOVDconst [c]) [d]) + // result: (XORconst x [rotateRight64(c, d)]) + for { + d := auxIntToInt64(v.AuxInt) + x := v_0 + if v_1.Op != OpARM64MOVDconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpARM64XORconst) + v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) + v.AddArg(x) + return true + } + // match: (XORshiftRO (RORconst x [c]) x [c]) + // result: (MOVDconst [0]) + for { + c := auxIntToInt64(v.AuxInt) + if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { + break + } + x := v_0.Args[0] + if x != v_1 { + break + } + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(0) + return true + } + return false +} +func rewriteValueARM64_OpAddr(v *Value) bool { + v_0 := v.Args[0] + // match: (Addr {sym} base) + // result: (MOVDaddr {sym} base) + for { + sym := auxToSym(v.Aux) + base := v_0 + v.reset(OpARM64MOVDaddr) + v.Aux = symToAux(sym) + v.AddArg(base) + return true + } +} +func rewriteValueARM64_OpAvg64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (EqPtr x y) - // result: (Equal (CMP x y)) + // match: (Avg64u x y) + // result: (ADD (SRLconst (SUB x y) [1]) y) for { + t := v.Type x := v_0 y := v_1 - v.reset(OpARM64Equal) - v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) - v0.AddArg2(x, y) + v.reset(OpARM64ADD) + v0 := b.NewValue0(v.Pos, OpARM64SRLconst, t) + v0.AuxInt = int64ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpARM64SUB, t) + v1.AddArg2(x, y) + v0.AddArg(v1) + v.AddArg2(v0, y) + return true + } +} +func rewriteValueARM64_OpBitLen16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen16 x) + // result: (BitLen64 (ZeroExt16to64 x)) + for { + x := v_0 + v.reset(OpBitLen64) + v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) + v0.AddArg(x) v.AddArg(v0) return true } } -func rewriteValueARM64_OpFMA(v *Value) bool { +func rewriteValueARM64_OpBitLen32(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen32 x) + // result: (SUB (MOVDconst [32]) (CLZW x)) + for { + x := v_0 + v.reset(OpARM64SUB) + v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(32) + v1 := b.NewValue0(v.Pos, OpARM64CLZW, typ.Int) + v1.AddArg(x) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueARM64_OpBitLen64(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen64 x) + // result: (SUB (MOVDconst [64]) (CLZ x)) + for { + x := v_0 + v.reset(OpARM64SUB) + v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(64) + v1 := b.NewValue0(v.Pos, OpARM64CLZ, typ.Int) + v1.AddArg(x) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueARM64_OpBitLen8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen8 x) + // result: (BitLen64 (ZeroExt8to64 x)) + for { + x := v_0 + v.reset(OpBitLen64) + v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpBitRev16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitRev16 x) + // result: (SRLconst [48] (RBIT x)) + for { + x := v_0 + v.reset(OpARM64SRLconst) + v.AuxInt = int64ToAuxInt(48) + v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpBitRev8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitRev8 x) + // result: (SRLconst [56] (RBIT x)) + for { + x := v_0 + v.reset(OpARM64SRLconst) + v.AuxInt = int64ToAuxInt(56) + v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - // match: (FMA x y z) - // result: (FMADDD z x y) + b := v.Block + // match: (CondSelect x y boolval) + // cond: flagArg(boolval) != nil + // result: (CSEL [boolval.Op] x y flagArg(boolval)) for { x := v_0 y := v_1 - z := v_2 - v.reset(OpARM64FMADDD) - v.AddArg3(z, x, y) + boolval := v_2 + if !(flagArg(boolval) != nil) { + break + } + v.reset(OpARM64CSEL) + v.AuxInt = opToAuxInt(boolval.Op) + v.AddArg3(x, y, flagArg(boolval)) + return true + } + // match: (CondSelect x y boolval) + // cond: flagArg(boolval) == nil + // result: (CSEL [OpARM64NotEqual] x y (TSTWconst [1] boolval)) + for { + x := v_0 + y := v_1 + boolval := v_2 + if !(flagArg(boolval) == nil) { + break + } + v.reset(OpARM64CSEL) + v.AuxInt = opToAuxInt(OpARM64NotEqual) + v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(1) + v0.AddArg(boolval) + v.AddArg3(x, y, v0) + return true + } + return false +} +func rewriteValueARM64_OpConst16(v *Value) bool { + // match: (Const16 [val]) + // result: (MOVDconst [int64(val)]) + for { + val := auxIntToInt16(v.AuxInt) + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(int64(val)) + return true + } +} +func rewriteValueARM64_OpConst32(v *Value) bool { + // match: (Const32 [val]) + // result: (MOVDconst [int64(val)]) + for { + val := auxIntToInt32(v.AuxInt) + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(int64(val)) + return true + } +} +func rewriteValueARM64_OpConst32F(v *Value) bool { + // match: (Const32F [val]) + // result: (FMOVSconst [float64(val)]) + for { + val := auxIntToFloat32(v.AuxInt) + v.reset(OpARM64FMOVSconst) + v.AuxInt = float64ToAuxInt(float64(val)) + return true + } +} +func rewriteValueARM64_OpConst64(v *Value) bool { + // match: (Const64 [val]) + // result: (MOVDconst [int64(val)]) + for { + val := auxIntToInt64(v.AuxInt) + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(int64(val)) + return true + } +} +func rewriteValueARM64_OpConst64F(v *Value) bool { + // match: (Const64F [val]) + // result: (FMOVDconst [float64(val)]) + for { + val := auxIntToFloat64(v.AuxInt) + v.reset(OpARM64FMOVDconst) + v.AuxInt = float64ToAuxInt(float64(val)) + return true + } +} +func rewriteValueARM64_OpConst8(v *Value) bool { + // match: (Const8 [val]) + // result: (MOVDconst [int64(val)]) + for { + val := auxIntToInt8(v.AuxInt) + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(int64(val)) + return true + } +} +func rewriteValueARM64_OpConstBool(v *Value) bool { + // match: (ConstBool [t]) + // result: (MOVDconst [b2i(t)]) + for { + t := auxIntToBool(v.AuxInt) + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(b2i(t)) + return true + } +} +func rewriteValueARM64_OpConstNil(v *Value) bool { + // match: (ConstNil) + // result: (MOVDconst [0]) + for { + v.reset(OpARM64MOVDconst) + v.AuxInt = int64ToAuxInt(0) return true } } -func rewriteValueARM64_OpHmul32(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Hmul32 x y) - // result: (SRAconst (MULL x y) [32]) + // match: (Ctz16 x) + // result: (CLZW (RBITW (ORconst [0x10000] x))) for { + t := v.Type x := v_0 - y := v_1 - v.reset(OpARM64SRAconst) - v.AuxInt = int64ToAuxInt(32) - v0 := b.NewValue0(v.Pos, OpARM64MULL, typ.Int64) - v0.AddArg2(x, y) + v.reset(OpARM64CLZW) + v.Type = t + v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) + v1.AuxInt = int64ToAuxInt(0x10000) + v1.AddArg(x) + v0.AddArg(v1) v.AddArg(v0) return true } } -func rewriteValueARM64_OpHmul32u(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (Hmul32u x y) - // result: (SRAconst (UMULL x y) [32]) + // match: (Ctz32 x) + // result: (CLZW (RBITW x)) for { + t := v.Type x := v_0 - y := v_1 - v.reset(OpARM64SRAconst) - v.AuxInt = int64ToAuxInt(32) - v0 := b.NewValue0(v.Pos, OpARM64UMULL, typ.UInt64) - v0.AddArg2(x, y) + v.reset(OpARM64CLZW) + v0 := b.NewValue0(v.Pos, OpARM64RBITW, t) + v0.AddArg(x) v.AddArg(v0) return true } } -func rewriteValueARM64_OpIsInBounds(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueARM64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block - // match: (IsInBounds idx len) - // result: (LessThanU (CMP idx len)) + // match: (Ctz64 x) + // result: (CLZ (RBIT x)) for { - idx := v_0 - len := v_1 - v.reset(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) - v0.AddArg2(idx, len) + t := v.Type + x := v_0 + v.reset(OpARM64CLZ) + v0 := b.NewValue0(v.Pos, OpARM64RBIT, t) + v0.AddArg(x) v.AddArg(v0) return true } } -func rewriteValueARM64_OpIsNonNil(v *Value) bool { +func rewriteValueARM64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block - // match: (IsNonNil ptr) - // result: (NotEqual (CMPconst [0] ptr)) + typ := &b.Func.Config.Types + // match: (Ctz8 x) + // result: (CLZW (RBITW (ORconst [0x100] x))) for { - ptr := v_0 - v.reset(OpARM64NotEqual) - v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v0.AuxInt = int64ToAuxInt(0) - v0.AddArg(ptr) + t := v.Type + x := v_0 + v.reset(OpARM64CLZW) + v.Type = t + v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) + v1.AuxInt = int64ToAuxInt(0x100) + v1.AddArg(x) + v0.AddArg(v1) v.AddArg(v0) return true } } -func rewriteValueARM64_OpIsSliceInBounds(v *Value) bool { +func rewriteValueARM64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (IsSliceInBounds idx len) - // result: (LessEqualU (CMP idx len)) + typ := &b.Func.Config.Types + // match: (Div16 [false] x y) + // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) for { - idx := v_0 - len := v_1 - v.reset(OpARM64LessEqualU) - v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) - v0.AddArg2(idx, len) - v.AddArg(v0) + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + y := v_1 + v.reset(OpARM64DIVW) + v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v1.AddArg(y) + v.AddArg2(v0, v1) return true } + return false } -func rewriteValueARM64_OpLeq16(v *Value) bool { +func rewriteValueARM64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Leq16 x y) - // result: (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) + // match: (Div16u x y) + // result: (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessEqual) - v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) + v.reset(OpARM64UDIVW) + v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v1.AddArg(y) + v.AddArg2(v0, v1) return true } } -func rewriteValueARM64_OpLeq16U(v *Value) bool { +func rewriteValueARM64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Leq16U x zero:(MOVDconst [0])) - // result: (Eq16 x zero) + // match: (Div32 [false] x y) + // result: (DIVW x y) for { - x := v_0 - zero := v_1 - if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { + if auxIntToBool(v.AuxInt) != false { break } - v.reset(OpEq16) - v.AddArg2(x, zero) + x := v_0 + y := v_1 + v.reset(OpARM64DIVW) + v.AddArg2(x, y) return true } - // match: (Leq16U (MOVDconst [1]) x) - // result: (Neq16 (MOVDconst [0]) x) + return false +} +func rewriteValueARM64_OpDiv64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (Div64 [false] x y) + // result: (DIV x y) for { - if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { + if auxIntToBool(v.AuxInt) != false { break } - x := v_1 - v.reset(OpNeq16) - v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(0) - v.AddArg2(v0, x) - return true - } - // match: (Leq16U x y) - // result: (LessEqualU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) - for { x := v_0 y := v_1 - v.reset(OpARM64LessEqualU) - v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) + v.reset(OpARM64DIV) + v.AddArg2(x, y) return true } + return false } -func rewriteValueARM64_OpLeq32(v *Value) bool { +func rewriteValueARM64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq32 x y) - // result: (LessEqual (CMPW x y)) + typ := &b.Func.Config.Types + // match: (Div8 x y) + // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessEqual) - v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.reset(OpARM64DIVW) + v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v1.AddArg(y) + v.AddArg2(v0, v1) return true } } -func rewriteValueARM64_OpLeq32F(v *Value) bool { +func rewriteValueARM64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq32F x y) - // result: (LessEqualF (FCMPS x y)) + typ := &b.Func.Config.Types + // match: (Div8u x y) + // result: (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessEqualF) - v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.reset(OpARM64UDIVW) + v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v1.AddArg(y) + v.AddArg2(v0, v1) return true } } -func rewriteValueARM64_OpLeq32U(v *Value) bool { +func rewriteValueARM64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Leq32U x zero:(MOVDconst [0])) - // result: (Eq32 x zero) + // match: (Eq16 x y) + // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 - zero := v_1 - if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { - break - } - v.reset(OpEq32) - v.AddArg2(x, zero) + y := v_1 + v.reset(OpARM64Equal) + v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) return true } - // match: (Leq32U (MOVDconst [1]) x) - // result: (Neq32 (MOVDconst [0]) x) +} +func rewriteValueARM64_OpEq32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq32 x y) + // result: (Equal (CMPW x y)) for { - if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - x := v_1 - v.reset(OpNeq32) - v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(0) - v.AddArg2(v0, x) + x := v_0 + y := v_1 + v.reset(OpARM64Equal) + v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - // match: (Leq32U x y) - // result: (LessEqualU (CMPW x y)) +} +func rewriteValueARM64_OpEq32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq32F x y) + // result: (Equal (FCMPS x y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessEqualU) - v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) + v.reset(OpARM64Equal) + v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLeq64(v *Value) bool { +func rewriteValueARM64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq64 x y) - // result: (LessEqual (CMP x y)) + // match: (Eq64 x y) + // result: (Equal (CMP x y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessEqual) + v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLeq64F(v *Value) bool { +func rewriteValueARM64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq64F x y) - // result: (LessEqualF (FCMPD x y)) + // match: (Eq64F x y) + // result: (Equal (FCMPD x y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessEqualF) + v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLeq64U(v *Value) bool { +func rewriteValueARM64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Leq64U x zero:(MOVDconst [0])) - // result: (Eq64 x zero) + // match: (Eq8 x y) + // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 - zero := v_1 - if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { - break - } - v.reset(OpEq64) - v.AddArg2(x, zero) + y := v_1 + v.reset(OpARM64Equal) + v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) return true } - // match: (Leq64U (MOVDconst [1]) x) - // result: (Neq64 (MOVDconst [0]) x) +} +func rewriteValueARM64_OpEqB(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqB x y) + // result: (XOR (MOVDconst [1]) (XOR x y)) for { - if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - x := v_1 - v.reset(OpNeq64) + x := v_0 + y := v_1 + v.reset(OpARM64XOR) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(0) - v.AddArg2(v0, x) + v0.AuxInt = int64ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpARM64XOR, typ.Bool) + v1.AddArg2(x, y) + v.AddArg2(v0, v1) return true } - // match: (Leq64U x y) - // result: (LessEqualU (CMP x y)) +} +func rewriteValueARM64_OpEqPtr(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (EqPtr x y) + // result: (Equal (CMP x y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessEqualU) + v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLeq8(v *Value) bool { +func rewriteValueARM64_OpFMA(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (FMA x y z) + // result: (FMADDD z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.reset(OpARM64FMADDD) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValueARM64_OpHmul32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Leq8 x y) - // result: (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) + // match: (Hmul32 x y) + // result: (SRAconst (MULL x y) [32]) for { x := v_0 y := v_1 - v.reset(OpARM64LessEqual) - v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v2.AddArg(y) - v0.AddArg2(v1, v2) + v.reset(OpARM64SRAconst) + v.AuxInt = int64ToAuxInt(32) + v0 := b.NewValue0(v.Pos, OpARM64MULL, typ.Int64) + v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLeq8U(v *Value) bool { +func rewriteValueARM64_OpHmul32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Leq8U x zero:(MOVDconst [0])) - // result: (Eq8 x zero) + // match: (Hmul32u x y) + // result: (SRAconst (UMULL x y) [32]) for { x := v_0 - zero := v_1 - if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { - break - } - v.reset(OpEq8) - v.AddArg2(x, zero) + y := v_1 + v.reset(OpARM64SRAconst) + v.AuxInt = int64ToAuxInt(32) + v0 := b.NewValue0(v.Pos, OpARM64UMULL, typ.UInt64) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - // match: (Leq8U (MOVDconst [1]) x) - // result: (Neq8 (MOVDconst [0]) x) +} +func rewriteValueARM64_OpIsInBounds(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (IsInBounds idx len) + // result: (LessThanU (CMP idx len)) for { - if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - x := v_1 - v.reset(OpNeq8) - v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + idx := v_0 + len := v_1 + v.reset(OpARM64LessThanU) + v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) + v0.AddArg2(idx, len) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpIsNonNil(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (IsNonNil ptr) + // result: (NotEqual (CMPconst [0] ptr)) + for { + ptr := v_0 + v.reset(OpARM64NotEqual) + v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(0) - v.AddArg2(v0, x) + v0.AddArg(ptr) + v.AddArg(v0) return true } - // match: (Leq8U x y) - // result: (LessEqualU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) +} +func rewriteValueARM64_OpIsSliceInBounds(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (IsSliceInBounds idx len) + // result: (LessEqualU (CMP idx len)) for { - x := v_0 - y := v_1 + idx := v_0 + len := v_1 v.reset(OpARM64LessEqualU) - v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) - v2.AddArg(y) - v0.AddArg2(v1, v2) + v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) + v0.AddArg2(idx, len) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLess16(v *Value) bool { +func rewriteValueARM64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Less16 x y) - // result: (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) + // match: (Leq16 x y) + // result: (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v_0 y := v_1 - v.reset(OpARM64LessThan) + v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) @@ -17855,42 +20337,42 @@ func rewriteValueARM64_OpLess16(v *Value) bool { return true } } -func rewriteValueARM64_OpLess16U(v *Value) bool { +func rewriteValueARM64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Less16U zero:(MOVDconst [0]) x) - // result: (Neq16 zero x) + // match: (Leq16U x zero:(MOVDconst [0])) + // result: (Eq16 x zero) for { - zero := v_0 + x := v_0 + zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } - x := v_1 - v.reset(OpNeq16) - v.AddArg2(zero, x) + v.reset(OpEq16) + v.AddArg2(x, zero) return true } - // match: (Less16U x (MOVDconst [1])) - // result: (Eq16 x (MOVDconst [0])) + // match: (Leq16U (MOVDconst [1]) x) + // result: (Neq16 (MOVDconst [0]) x) for { - x := v_0 - if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { + if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } - v.reset(OpEq16) + x := v_1 + v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) - v.AddArg2(x, v0) + v.AddArg2(v0, x) return true } - // match: (Less16U x y) - // result: (LessThanU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) + // match: (Leq16U x y) + // result: (LessEqualU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 - v.reset(OpARM64LessThanU) + v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) @@ -17901,165 +20383,165 @@ func rewriteValueARM64_OpLess16U(v *Value) bool { return true } } -func rewriteValueARM64_OpLess32(v *Value) bool { +func rewriteValueARM64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Less32 x y) - // result: (LessThan (CMPW x y)) + // match: (Leq32 x y) + // result: (LessEqual (CMPW x y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessThan) + v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLess32F(v *Value) bool { +func rewriteValueARM64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Less32F x y) - // result: (LessThanF (FCMPS x y)) + // match: (Leq32F x y) + // result: (LessEqualF (FCMPS x y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessThanF) + v.reset(OpARM64LessEqualF) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLess32U(v *Value) bool { +func rewriteValueARM64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Less32U zero:(MOVDconst [0]) x) - // result: (Neq32 zero x) + // match: (Leq32U x zero:(MOVDconst [0])) + // result: (Eq32 x zero) for { - zero := v_0 + x := v_0 + zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } - x := v_1 - v.reset(OpNeq32) - v.AddArg2(zero, x) + v.reset(OpEq32) + v.AddArg2(x, zero) return true } - // match: (Less32U x (MOVDconst [1])) - // result: (Eq32 x (MOVDconst [0])) + // match: (Leq32U (MOVDconst [1]) x) + // result: (Neq32 (MOVDconst [0]) x) for { - x := v_0 - if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { + if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } - v.reset(OpEq32) + x := v_1 + v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) - v.AddArg2(x, v0) + v.AddArg2(v0, x) return true } - // match: (Less32U x y) - // result: (LessThanU (CMPW x y)) + // match: (Leq32U x y) + // result: (LessEqualU (CMPW x y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessThanU) + v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLess64(v *Value) bool { +func rewriteValueARM64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Less64 x y) - // result: (LessThan (CMP x y)) + // match: (Leq64 x y) + // result: (LessEqual (CMP x y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessThan) + v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLess64F(v *Value) bool { +func rewriteValueARM64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Less64F x y) - // result: (LessThanF (FCMPD x y)) + // match: (Leq64F x y) + // result: (LessEqualF (FCMPD x y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessThanF) + v.reset(OpARM64LessEqualF) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLess64U(v *Value) bool { +func rewriteValueARM64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Less64U zero:(MOVDconst [0]) x) - // result: (Neq64 zero x) + // match: (Leq64U x zero:(MOVDconst [0])) + // result: (Eq64 x zero) for { - zero := v_0 + x := v_0 + zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } - x := v_1 - v.reset(OpNeq64) - v.AddArg2(zero, x) + v.reset(OpEq64) + v.AddArg2(x, zero) return true } - // match: (Less64U x (MOVDconst [1])) - // result: (Eq64 x (MOVDconst [0])) + // match: (Leq64U (MOVDconst [1]) x) + // result: (Neq64 (MOVDconst [0]) x) for { - x := v_0 - if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { + if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } - v.reset(OpEq64) + x := v_1 + v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) - v.AddArg2(x, v0) + v.AddArg2(v0, x) return true } - // match: (Less64U x y) - // result: (LessThanU (CMP x y)) + // match: (Leq64U x y) + // result: (LessEqualU (CMP x y)) for { x := v_0 y := v_1 - v.reset(OpARM64LessThanU) + v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueARM64_OpLess8(v *Value) bool { +func rewriteValueARM64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Less8 x y) - // result: (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) + // match: (Leq8 x y) + // result: (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v_0 y := v_1 - v.reset(OpARM64LessThan) + v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) @@ -18070,786 +20552,539 @@ func rewriteValueARM64_OpLess8(v *Value) bool { return true } } -func rewriteValueARM64_OpLess8U(v *Value) bool { +func rewriteValueARM64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Less8U zero:(MOVDconst [0]) x) - // result: (Neq8 zero x) - for { - zero := v_0 - if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { - break - } - x := v_1 - v.reset(OpNeq8) - v.AddArg2(zero, x) - return true - } - // match: (Less8U x (MOVDconst [1])) - // result: (Eq8 x (MOVDconst [0])) + // match: (Leq8U x zero:(MOVDconst [0])) + // result: (Eq8 x zero) for { x := v_0 - if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { + zero := v_1 + if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq8) - v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(0) - v.AddArg2(x, v0) - return true - } - // match: (Less8U x y) - // result: (LessThanU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) - for { - x := v_0 - y := v_1 - v.reset(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) - return true - } -} -func rewriteValueARM64_OpLoad(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (Load ptr mem) - // cond: t.IsBoolean() - // result: (MOVBUload ptr mem) - for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(t.IsBoolean()) { - break - } - v.reset(OpARM64MOVBUload) - v.AddArg2(ptr, mem) - return true - } - // match: (Load ptr mem) - // cond: (is8BitInt(t) && t.IsSigned()) - // result: (MOVBload ptr mem) - for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is8BitInt(t) && t.IsSigned()) { - break - } - v.reset(OpARM64MOVBload) - v.AddArg2(ptr, mem) - return true - } - // match: (Load ptr mem) - // cond: (is8BitInt(t) && !t.IsSigned()) - // result: (MOVBUload ptr mem) - for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is8BitInt(t) && !t.IsSigned()) { - break - } - v.reset(OpARM64MOVBUload) - v.AddArg2(ptr, mem) - return true - } - // match: (Load ptr mem) - // cond: (is16BitInt(t) && t.IsSigned()) - // result: (MOVHload ptr mem) - for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is16BitInt(t) && t.IsSigned()) { - break - } - v.reset(OpARM64MOVHload) - v.AddArg2(ptr, mem) - return true - } - // match: (Load ptr mem) - // cond: (is16BitInt(t) && !t.IsSigned()) - // result: (MOVHUload ptr mem) - for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is16BitInt(t) && !t.IsSigned()) { - break - } - v.reset(OpARM64MOVHUload) - v.AddArg2(ptr, mem) - return true - } - // match: (Load ptr mem) - // cond: (is32BitInt(t) && t.IsSigned()) - // result: (MOVWload ptr mem) - for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is32BitInt(t) && t.IsSigned()) { - break - } - v.reset(OpARM64MOVWload) - v.AddArg2(ptr, mem) - return true - } - // match: (Load ptr mem) - // cond: (is32BitInt(t) && !t.IsSigned()) - // result: (MOVWUload ptr mem) - for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is32BitInt(t) && !t.IsSigned()) { - break - } - v.reset(OpARM64MOVWUload) - v.AddArg2(ptr, mem) - return true - } - // match: (Load ptr mem) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (MOVDload ptr mem) - for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is64BitInt(t) || isPtr(t)) { - break - } - v.reset(OpARM64MOVDload) - v.AddArg2(ptr, mem) - return true - } - // match: (Load ptr mem) - // cond: is32BitFloat(t) - // result: (FMOVSload ptr mem) - for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is32BitFloat(t)) { - break - } - v.reset(OpARM64FMOVSload) - v.AddArg2(ptr, mem) + v.AddArg2(x, zero) return true } - // match: (Load ptr mem) - // cond: is64BitFloat(t) - // result: (FMOVDload ptr mem) + // match: (Leq8U (MOVDconst [1]) x) + // result: (Neq8 (MOVDconst [0]) x) for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is64BitFloat(t)) { + if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } - v.reset(OpARM64FMOVDload) - v.AddArg2(ptr, mem) + x := v_1 + v.reset(OpNeq8) + v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(0) + v.AddArg2(v0, x) + return true + } + // match: (Leq8U x y) + // result: (LessEqualU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64LessEqualU) + v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) return true } - return false } -func rewriteValueARM64_OpLocalAddr(v *Value) bool { +func rewriteValueARM64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (LocalAddr {sym} base mem) - // cond: t.Elem().HasPointers() - // result: (MOVDaddr {sym} (SPanchored base mem)) + // match: (Less16 x y) + // result: (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { - t := v.Type - sym := auxToSym(v.Aux) - base := v_0 - mem := v_1 - if !(t.Elem().HasPointers()) { - break - } - v.reset(OpARM64MOVDaddr) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) - v0.AddArg2(base, mem) + x := v_0 + y := v_1 + v.reset(OpARM64LessThan) + v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v2.AddArg(y) + v0.AddArg2(v1, v2) v.AddArg(v0) return true } - // match: (LocalAddr {sym} base _) - // cond: !t.Elem().HasPointers() - // result: (MOVDaddr {sym} base) - for { - t := v.Type - sym := auxToSym(v.Aux) - base := v_0 - if !(!t.Elem().HasPointers()) { - break - } - v.reset(OpARM64MOVDaddr) - v.Aux = symToAux(sym) - v.AddArg(base) - return true - } - return false } -func rewriteValueARM64_OpLsh16x16(v *Value) bool { +func rewriteValueARM64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Lsh16x16 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (Less16U zero:(MOVDconst [0]) x) + // result: (Neq16 zero x) for { - t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + zero := v_0 + if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + x := v_1 + v.reset(OpNeq16) + v.AddArg2(zero, x) return true } - // match: (Lsh16x16 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) + // match: (Less16U x (MOVDconst [1])) + // result: (Eq16 x (MOVDconst [0])) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(0) + v.AddArg2(x, v0) + return true + } + // match: (Less16U x y) + // result: (LessThanU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64LessThanU) + v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) return true } - return false } -func rewriteValueARM64_OpLsh16x32(v *Value) bool { +func rewriteValueARM64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (Lsh16x32 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (Less32 x y) + // result: (LessThan (CMPW x y)) for { - t := v.Type x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + v.reset(OpARM64LessThan) + v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - // match: (Lsh16x32 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) +} +func rewriteValueARM64_OpLess32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less32F x y) + // result: (LessThanF (FCMPS x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) + v.reset(OpARM64LessThanF) + v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.AddArg(v0) return true } - return false } -func rewriteValueARM64_OpLsh16x64(v *Value) bool { +func rewriteValueARM64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh16x64 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + typ := &b.Func.Config.Types + // match: (Less32U zero:(MOVDconst [0]) x) + // result: (Neq32 zero x) for { - t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + zero := v_0 + if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + x := v_1 + v.reset(OpNeq32) + v.AddArg2(zero, x) return true } - // match: (Lsh16x64 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) + // match: (Less32U x (MOVDconst [1])) + // result: (Eq32 x (MOVDconst [0])) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(0) + v.AddArg2(x, v0) + return true + } + // match: (Less32U x y) + // result: (LessThanU (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpARM64LessThanU) + v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v2.AddArg(y) - v.AddArg3(v0, v1, v2) + v.AddArg(v0) return true } - return false } -func rewriteValueARM64_OpLsh16x8(v *Value) bool { +func rewriteValueARM64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (Lsh16x8 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (Less64 x y) + // result: (LessThan (CMP x y)) for { - t := v.Type x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + v.reset(OpARM64LessThan) + v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - // match: (Lsh16x8 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) +} +func rewriteValueARM64_OpLess64F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less64F x y) + // result: (LessThanF (FCMPD x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) + v.reset(OpARM64LessThanF) + v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.AddArg(v0) return true } - return false } -func rewriteValueARM64_OpLsh32x16(v *Value) bool { +func rewriteValueARM64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Lsh32x16 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (Less64U zero:(MOVDconst [0]) x) + // result: (Neq64 zero x) for { - t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + zero := v_0 + if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + x := v_1 + v.reset(OpNeq64) + v.AddArg2(zero, x) return true } - // match: (Lsh32x16 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) + // match: (Less64U x (MOVDconst [1])) + // result: (Eq64 x (MOVDconst [0])) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) + v.reset(OpEq64) + v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(0) + v.AddArg2(x, v0) + return true + } + // match: (Less64U x y) + // result: (LessThanU (CMP x y)) + for { + x := v_0 + y := v_1 + v.reset(OpARM64LessThanU) + v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.AddArg(v0) return true } - return false } -func rewriteValueARM64_OpLsh32x32(v *Value) bool { +func rewriteValueARM64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Lsh32x32 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (Less8 x y) + // result: (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { - t := v.Type x := v_0 y := v_1 - if !(shiftIsBounded(v)) { + v.reset(OpARM64LessThan) + v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpLess8U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Less8U zero:(MOVDconst [0]) x) + // result: (Neq8 zero x) + for { + zero := v_0 + if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + x := v_1 + v.reset(OpNeq8) + v.AddArg2(zero, x) return true } - // match: (Lsh32x32 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) + // match: (Less8U x (MOVDconst [1])) + // result: (Eq8 x (MOVDconst [0])) for { - t := v.Type x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(0) + v.AddArg2(x, v0) + return true + } + // match: (Less8U x y) + // result: (LessThanU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64LessThanU) + v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) return true } - return false } -func rewriteValueARM64_OpLsh32x64(v *Value) bool { +func rewriteValueARM64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (Lsh32x64 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (Load ptr mem) + // cond: t.IsBoolean() + // result: (MOVBUload ptr mem) for { t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + ptr := v_0 + mem := v_1 + if !(t.IsBoolean()) { break } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + v.reset(OpARM64MOVBUload) + v.AddArg2(ptr, mem) return true } - // match: (Lsh32x64 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) + // match: (Load ptr mem) + // cond: (is8BitInt(t) && t.IsSigned()) + // result: (MOVBload ptr mem) for { t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + ptr := v_0 + mem := v_1 + if !(is8BitInt(t) && t.IsSigned()) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v2.AddArg(y) - v.AddArg3(v0, v1, v2) + v.reset(OpARM64MOVBload) + v.AddArg2(ptr, mem) return true } - return false -} -func rewriteValueARM64_OpLsh32x8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Lsh32x8 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (Load ptr mem) + // cond: (is8BitInt(t) && !t.IsSigned()) + // result: (MOVBUload ptr mem) for { t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + ptr := v_0 + mem := v_1 + if !(is8BitInt(t) && !t.IsSigned()) { break } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + v.reset(OpARM64MOVBUload) + v.AddArg2(ptr, mem) return true } - // match: (Lsh32x8 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + // match: (Load ptr mem) + // cond: (is16BitInt(t) && t.IsSigned()) + // result: (MOVHload ptr mem) for { t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + ptr := v_0 + mem := v_1 + if !(is16BitInt(t) && t.IsSigned()) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.reset(OpARM64MOVHload) + v.AddArg2(ptr, mem) return true } - return false -} -func rewriteValueARM64_OpLsh64x16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Lsh64x16 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (Load ptr mem) + // cond: (is16BitInt(t) && !t.IsSigned()) + // result: (MOVHUload ptr mem) for { t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + ptr := v_0 + mem := v_1 + if !(is16BitInt(t) && !t.IsSigned()) { break } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + v.reset(OpARM64MOVHUload) + v.AddArg2(ptr, mem) return true } - // match: (Lsh64x16 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) + // match: (Load ptr mem) + // cond: (is32BitInt(t) && t.IsSigned()) + // result: (MOVWload ptr mem) for { t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + ptr := v_0 + mem := v_1 + if !(is32BitInt(t) && t.IsSigned()) { + break + } + v.reset(OpARM64MOVWload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: (is32BitInt(t) && !t.IsSigned()) + // result: (MOVWUload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is32BitInt(t) && !t.IsSigned()) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.reset(OpARM64MOVWUload) + v.AddArg2(ptr, mem) return true } - return false -} -func rewriteValueARM64_OpLsh64x32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Lsh64x32 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (Load ptr mem) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (MOVDload ptr mem) for { t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + ptr := v_0 + mem := v_1 + if !(is64BitInt(t) || isPtr(t)) { break } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + v.reset(OpARM64MOVDload) + v.AddArg2(ptr, mem) return true } - // match: (Lsh64x32 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) + // match: (Load ptr mem) + // cond: is32BitFloat(t) + // result: (FMOVSload ptr mem) for { t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + ptr := v_0 + mem := v_1 + if !(is32BitFloat(t)) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.reset(OpARM64FMOVSload) + v.AddArg2(ptr, mem) return true } - return false -} -func rewriteValueARM64_OpLsh64x64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh64x64 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (Load ptr mem) + // cond: is64BitFloat(t) + // result: (FMOVDload ptr mem) for { t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + ptr := v_0 + mem := v_1 + if !(is64BitFloat(t)) { break } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + v.reset(OpARM64FMOVDload) + v.AddArg2(ptr, mem) return true } - // match: (Lsh64x64 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) + // match: (Load ptr mem) + // cond: t.Size() == 16 + // result: (FMOVQload ptr mem) for { t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + ptr := v_0 + mem := v_1 + if !(t.Size() == 16) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v2.AddArg(y) - v.AddArg3(v0, v1, v2) + v.reset(OpARM64FMOVQload) + v.AddArg2(ptr, mem) return true } return false } -func rewriteValueARM64_OpLsh64x8(v *Value) bool { +func rewriteValueARM64_OpLocalAddr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Lsh64x8 x y) - // cond: shiftIsBounded(v) - // result: (SLL x y) + // match: (LocalAddr {sym} base mem) + // cond: t.Elem().HasPointers() + // result: (MOVDaddr {sym} (SPanchored base mem)) for { t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + sym := auxToSym(v.Aux) + base := v_0 + mem := v_1 + if !(t.Elem().HasPointers()) { break } - v.reset(OpARM64SLL) - v.Type = t - v.AddArg2(x, y) + v.reset(OpARM64MOVDaddr) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) + v0.AddArg2(base, mem) + v.AddArg(v0) return true } - // match: (Lsh64x8 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + // match: (LocalAddr {sym} base _) + // cond: !t.Elem().HasPointers() + // result: (MOVDaddr {sym} base) for { t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { + sym := auxToSym(v.Aux) + base := v_0 + if !(!t.Elem().HasPointers()) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.reset(OpARM64MOVDaddr) + v.Aux = symToAux(sym) + v.AddArg(base) return true } return false } -func rewriteValueARM64_OpLsh8x16(v *Value) bool { +func rewriteValueARM64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Lsh8x16 x y) + // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { @@ -18864,38 +21099,32 @@ func rewriteValueARM64_OpLsh8x16(v *Value) bool { v.AddArg2(x, y) return true } - // match: (Lsh8x16 x y) + // match: (Lsh64x16 [bounded] x y) // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) + // result: (Lsh64x32 [bounded] x (ZeroExt16to32 y)) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.reset(OpLsh64x32) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) + v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v0.AddArg(y) + v.AddArg2(x, v0) return true } return false } -func rewriteValueARM64_OpLsh8x32(v *Value) bool { +func rewriteValueARM64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (Lsh8x32 x y) + // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { @@ -18910,9 +21139,9 @@ func rewriteValueARM64_OpLsh8x32(v *Value) bool { v.AddArg2(x, y) return true } - // match: (Lsh8x32 x y) + // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) + // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPWconst [64] y)) for { t := v.Type x := v_0 @@ -18926,21 +21155,19 @@ func rewriteValueARM64_OpLsh8x32(v *Value) bool { v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) + v2 := b.NewValue0(v.Pos, OpARM64CMPWconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(64) + v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } -func rewriteValueARM64_OpLsh8x64(v *Value) bool { +func rewriteValueARM64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh8x64 x y) + // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { @@ -18955,7 +21182,7 @@ func rewriteValueARM64_OpLsh8x64(v *Value) bool { v.AddArg2(x, y) return true } - // match: (Lsh8x64 x y) + // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { @@ -18979,12 +21206,12 @@ func rewriteValueARM64_OpLsh8x64(v *Value) bool { } return false } -func rewriteValueARM64_OpLsh8x8(v *Value) bool { +func rewriteValueARM64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Lsh8x8 x y) + // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { @@ -18999,28 +21226,23 @@ func rewriteValueARM64_OpLsh8x8(v *Value) bool { v.AddArg2(x, y) return true } - // match: (Lsh8x8 x y) + // match: (Lsh64x8 [bounded] x y) // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + // result: (Lsh64x32 [bounded] x (ZeroExt8to32 y)) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.reset(OpLsh64x32) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) + v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v0.AddArg(y) + v.AddArg2(x, v0) return true } return false @@ -19435,7 +21657,7 @@ func rewriteValueARM64_OpMove(v *Value) bool { return true } // match: (Move [16] dst src mem) - // result: (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem) + // result: (FMOVQstore dst (FMOVQload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break @@ -19443,19 +21665,15 @@ func rewriteValueARM64_OpMove(v *Value) bool { dst := v_0 src := v_1 mem := v_2 - v.reset(OpARM64STP) - v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v1.AddArg2(src, mem) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v2.AddArg(v1) - v.AddArg4(dst, v0, v2, mem) + v.reset(OpARM64FMOVQstore) + v0 := b.NewValue0(v.Pos, OpARM64FMOVQload, typ.Vec128) + v0.AddArg2(src, mem) + v.AddArg3(dst, v0, mem) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s <= 24 - // result: (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)) + // result: (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem) (FMOVQstore dst (FMOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 @@ -19469,51 +21687,58 @@ func rewriteValueARM64_OpMove(v *Value) bool { v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(int32(s - 8)) v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v2 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v3 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v3.AddArg2(src, mem) - v2.AddArg(v3) - v4 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v4.AddArg(v3) - v1.AddArg4(dst, v2, v4, mem) + v1 := b.NewValue0(v.Pos, OpARM64FMOVQstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpARM64FMOVQload, typ.Vec128) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) - // cond: s > 24 && s <= 32 - // result: (STP [int32(s-16)] dst (Select0 (LDP [int32(s-16)] src mem)) (Select1 (LDP [int32(s-16)] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)) + // cond: s > 24 && s < 32 + // result: (FMOVQstore [int32(s-16)] dst (FMOVQload [int32(s-16)] src mem) (FMOVQstore dst (FMOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 - if !(s > 24 && s <= 32) { + if !(s > 24 && s < 32) { break } - v.reset(OpARM64STP) + v.reset(OpARM64FMOVQstore) v.AuxInt = int32ToAuxInt(int32(s - 16)) - v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v1.AuxInt = int32ToAuxInt(int32(s - 16)) + v0 := b.NewValue0(v.Pos, OpARM64FMOVQload, typ.Vec128) + v0.AuxInt = int32ToAuxInt(int32(s - 16)) + v0.AddArg2(src, mem) + v1 := b.NewValue0(v.Pos, OpARM64FMOVQstore, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpARM64FMOVQload, typ.Vec128) + v2.AddArg2(src, mem) + v1.AddArg3(dst, v2, mem) + v.AddArg3(dst, v0, v1) + return true + } + // match: (Move [32] dst src mem) + // result: (FSTPQ dst (Select0 (FLDPQ src mem)) (Select1 (FLDPQ src mem)) mem) + for { + if auxIntToInt64(v.AuxInt) != 32 { + break + } + dst := v_0 + src := v_1 + mem := v_2 + v.reset(OpARM64FSTPQ) + v0 := b.NewValue0(v.Pos, OpSelect0, typ.Vec128) + v1 := b.NewValue0(v.Pos, OpARM64FLDPQ, types.NewTuple(typ.Vec128, typ.Vec128)) v1.AddArg2(src, mem) v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpSelect1, typ.Vec128) v2.AddArg(v1) - v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v5.AddArg2(src, mem) - v4.AddArg(v5) - v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v6.AddArg(v5) - v3.AddArg4(dst, v4, v6, mem) - v.AddArg4(dst, v0, v2, v3) + v.AddArg4(dst, v0, v2, mem) return true } // match: (Move [s] dst src mem) // cond: s > 32 && s <= 40 - // result: (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem))) + // result: (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem) (FSTPQ dst (Select0 (FLDPQ src mem)) (Select1 (FLDPQ src mem)) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 @@ -19527,163 +21752,72 @@ func rewriteValueARM64_OpMove(v *Value) bool { v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(int32(s - 8)) v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v1.AuxInt = int32ToAuxInt(16) - v2 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v3 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v3.AuxInt = int32ToAuxInt(16) - v3.AddArg2(src, mem) - v2.AddArg(v3) - v4 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v4.AddArg(v3) - v5 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v6 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v7 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v7.AddArg2(src, mem) - v6.AddArg(v7) - v8 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v8.AddArg(v7) - v5.AddArg4(dst, v6, v8, mem) - v1.AddArg4(dst, v2, v4, v5) - v.AddArg3(dst, v0, v1) - return true - } - // match: (Move [s] dst src mem) - // cond: s > 40 && s <= 48 - // result: (STP [int32(s-16)] dst (Select0 (LDP [int32(s-16)] src mem)) (Select1 (LDP [int32(s-16)] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem))) - for { - s := auxIntToInt64(v.AuxInt) - dst := v_0 - src := v_1 - mem := v_2 - if !(s > 40 && s <= 48) { - break - } - v.reset(OpARM64STP) - v.AuxInt = int32ToAuxInt(int32(s - 16)) - v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v1.AuxInt = int32ToAuxInt(int32(s - 16)) - v1.AddArg2(src, mem) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v2.AddArg(v1) - v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v3.AuxInt = int32ToAuxInt(16) - v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v5.AuxInt = int32ToAuxInt(16) - v5.AddArg2(src, mem) - v4.AddArg(v5) - v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v6.AddArg(v5) - v7 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v9 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v9.AddArg2(src, mem) - v8.AddArg(v9) - v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v10.AddArg(v9) - v7.AddArg4(dst, v8, v10, mem) - v3.AddArg4(dst, v4, v6, v7) - v.AddArg4(dst, v0, v2, v3) + v1 := b.NewValue0(v.Pos, OpARM64FSTPQ, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpSelect0, typ.Vec128) + v3 := b.NewValue0(v.Pos, OpARM64FLDPQ, types.NewTuple(typ.Vec128, typ.Vec128)) + v3.AddArg2(src, mem) + v2.AddArg(v3) + v4 := b.NewValue0(v.Pos, OpSelect1, typ.Vec128) + v4.AddArg(v3) + v1.AddArg4(dst, v2, v4, mem) + v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) - // cond: s > 48 && s <= 56 - // result: (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem) (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)))) + // cond: s > 40 && s <= 48 + // result: (FMOVQstore [int32(s-16)] dst (FMOVQload [int32(s-16)] src mem) (FSTPQ dst (Select0 (FLDPQ src mem)) (Select1 (FLDPQ src mem)) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 - if !(s > 48 && s <= 56) { + if !(s > 40 && s <= 48) { break } - v.reset(OpARM64MOVDstore) - v.AuxInt = int32ToAuxInt(int32(s - 8)) - v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) - v0.AuxInt = int32ToAuxInt(int32(s - 8)) + v.reset(OpARM64FMOVQstore) + v.AuxInt = int32ToAuxInt(int32(s - 16)) + v0 := b.NewValue0(v.Pos, OpARM64FMOVQload, typ.Vec128) + v0.AuxInt = int32ToAuxInt(int32(s - 16)) v0.AddArg2(src, mem) - v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v1.AuxInt = int32ToAuxInt(32) - v2 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v3 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v3.AuxInt = int32ToAuxInt(32) + v1 := b.NewValue0(v.Pos, OpARM64FSTPQ, types.TypeMem) + v2 := b.NewValue0(v.Pos, OpSelect0, typ.Vec128) + v3 := b.NewValue0(v.Pos, OpARM64FLDPQ, types.NewTuple(typ.Vec128, typ.Vec128)) v3.AddArg2(src, mem) v2.AddArg(v3) - v4 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) + v4 := b.NewValue0(v.Pos, OpSelect1, typ.Vec128) v4.AddArg(v3) - v5 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v5.AuxInt = int32ToAuxInt(16) - v6 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v7 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v7.AuxInt = int32ToAuxInt(16) - v7.AddArg2(src, mem) - v6.AddArg(v7) - v8 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v8.AddArg(v7) - v9 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v10 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v11 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v11.AddArg2(src, mem) - v10.AddArg(v11) - v12 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v12.AddArg(v11) - v9.AddArg4(dst, v10, v12, mem) - v5.AddArg4(dst, v6, v8, v9) - v1.AddArg4(dst, v2, v4, v5) + v1.AddArg4(dst, v2, v4, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) - // cond: s > 56 && s <= 64 - // result: (STP [int32(s-16)] dst (Select0 (LDP [int32(s-16)] src mem)) (Select1 (LDP [int32(s-16)] src mem)) (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)))) + // cond: s > 48 && s <= 64 + // result: (FSTPQ [int32(s-32)] dst (Select0 (FLDPQ [int32(s-32)] src mem)) (Select1 (FLDPQ [int32(s-32)] src mem)) (FSTPQ dst (Select0 (FLDPQ src mem)) (Select1 (FLDPQ src mem)) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 - if !(s > 56 && s <= 64) { + if !(s > 48 && s <= 64) { break } - v.reset(OpARM64STP) - v.AuxInt = int32ToAuxInt(int32(s - 16)) - v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v1.AuxInt = int32ToAuxInt(int32(s - 16)) + v.reset(OpARM64FSTPQ) + v.AuxInt = int32ToAuxInt(int32(s - 32)) + v0 := b.NewValue0(v.Pos, OpSelect0, typ.Vec128) + v1 := b.NewValue0(v.Pos, OpARM64FLDPQ, types.NewTuple(typ.Vec128, typ.Vec128)) + v1.AuxInt = int32ToAuxInt(int32(s - 32)) v1.AddArg2(src, mem) v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpSelect1, typ.Vec128) v2.AddArg(v1) - v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v3.AuxInt = int32ToAuxInt(32) - v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v5.AuxInt = int32ToAuxInt(32) + v3 := b.NewValue0(v.Pos, OpARM64FSTPQ, types.TypeMem) + v4 := b.NewValue0(v.Pos, OpSelect0, typ.Vec128) + v5 := b.NewValue0(v.Pos, OpARM64FLDPQ, types.NewTuple(typ.Vec128, typ.Vec128)) v5.AddArg2(src, mem) v4.AddArg(v5) - v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) + v6 := b.NewValue0(v.Pos, OpSelect1, typ.Vec128) v6.AddArg(v5) - v7 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v7.AuxInt = int32ToAuxInt(16) - v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v9 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v9.AuxInt = int32ToAuxInt(16) - v9.AddArg2(src, mem) - v8.AddArg(v9) - v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v10.AddArg(v9) - v11 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) - v12 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) - v13 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) - v13.AddArg2(src, mem) - v12.AddArg(v13) - v14 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) - v14.AddArg(v13) - v11.AddArg4(dst, v12, v14, mem) - v7.AddArg4(dst, v8, v10, v11) - v3.AddArg4(dst, v4, v6, v7) + v3.AddArg4(dst, v4, v6, mem) v.AddArg4(dst, v0, v2, v3) return true } @@ -19721,6 +21855,126 @@ func rewriteValueARM64_OpMove(v *Value) bool { } return false } +func rewriteValueARM64_OpMulAddFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddFloat32x4 x y z) + // result: (VFMLA4S z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.reset(OpARM64VFMLA4S) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValueARM64_OpMulAddFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddFloat64x2 x y z) + // result: (VFMLA2D z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.reset(OpARM64VFMLA2D) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValueARM64_OpMulAddInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddInt16x8 x y z) + // result: (VMLA8H z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.reset(OpARM64VMLA8H) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValueARM64_OpMulAddInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddInt32x4 x y z) + // result: (VMLA4S z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.reset(OpARM64VMLA4S) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValueARM64_OpMulAddInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddInt8x16 x y z) + // result: (VMLA16B z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.reset(OpARM64VMLA16B) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValueARM64_OpMulAddUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddUint16x8 x y z) + // result: (VMLA8H z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.reset(OpARM64VMLA8H) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValueARM64_OpMulAddUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddUint32x4 x y z) + // result: (VMLA4S z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.reset(OpARM64VMLA4S) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValueARM64_OpMulAddUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddUint8x16 x y z) + // result: (VMLA16B z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.reset(OpARM64VMLA16B) + v.AddArg3(z, x, y) + return true + } +} func rewriteValueARM64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -20115,795 +22369,347 @@ func rewriteValueARM64_OpRotateLeft8(v *Value) bool { v4.AuxInt = int64ToAuxInt(7) v5 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) v5.AddArg(y) - v4.AddArg(v5) - v2.AddArg2(v3, v4) - v.AddArg2(v0, v2) - return true - } -} -func rewriteValueARM64_OpRsh16Ux16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Rsh16Ux16 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt16to64 x) y) - for { - t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) - v.Type = t - v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v0.AddArg(x) - v.AddArg2(v0, y) - return true - } - // match: (Rsh16Ux16 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v.AddArg3(v0, v2, v3) - return true - } - return false -} -func rewriteValueARM64_OpRsh16Ux32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Rsh16Ux32 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt16to64 x) y) - for { - t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) - v.Type = t - v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v0.AddArg(x) - v.AddArg2(v0, y) - return true - } - // match: (Rsh16Ux32 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v.AddArg3(v0, v2, v3) - return true - } - return false -} -func rewriteValueARM64_OpRsh16Ux64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Rsh16Ux64 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt16to64 x) y) - for { - t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) - v.Type = t - v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v0.AddArg(x) - v.AddArg2(v0, y) - return true - } - // match: (Rsh16Ux64 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] y)) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v3.AddArg(y) - v.AddArg3(v0, v2, v3) - return true - } - return false -} -func rewriteValueARM64_OpRsh16Ux8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Rsh16Ux8 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt16to64 x) y) - for { - t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) - v.Type = t - v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v0.AddArg(x) - v.AddArg2(v0, y) - return true - } - // match: (Rsh16Ux8 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v.AddArg3(v0, v2, v3) + v4.AddArg(v5) + v2.AddArg2(v3, v4) + v.AddArg2(v0, v2) return true } - return false } -func rewriteValueARM64_OpRsh16x16(v *Value) bool { +func rewriteValueARM64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh16x16 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt16to64 x) y) + // match: (Rsh16Ux16 [bounded] x y) + // result: (Rsh64Ux16 [bounded] (ZeroExt16to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64Ux16) v.Type = t - v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) + v.AuxInt = boolToAuxInt(bounded) + v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh16x16 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) +} +func rewriteValueARM64_OpRsh16Ux32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Rsh16Ux32 [bounded] x y) + // result: (Rsh64Ux32 [bounded] (ZeroExt16to64 x) y) for { + t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) - v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) + v.reset(OpRsh64Ux32) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) + v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) + v.AddArg2(v0, y) return true } - return false } -func rewriteValueARM64_OpRsh16x32(v *Value) bool { +func rewriteValueARM64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh16x32 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt16to64 x) y) + // match: (Rsh16Ux64 [bounded] x y) + // result: (Rsh64Ux64 [bounded] (ZeroExt16to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64Ux64) v.Type = t - v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) + v.AuxInt = boolToAuxInt(bounded) + v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh16x32 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) +} +func rewriteValueARM64_OpRsh16Ux8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Rsh16Ux8 [bounded] x y) + // result: (Rsh64Ux8 [bounded] (ZeroExt16to64 x) y) for { + t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) - v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) + v.reset(OpRsh64Ux8) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) + v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) + v.AddArg2(v0, y) return true } - return false } -func rewriteValueARM64_OpRsh16x64(v *Value) bool { +func rewriteValueARM64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh16x64 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt16to64 x) y) + // match: (Rsh16x16 [bounded] x y) + // result: (Rsh64x16 [bounded] (SignExt16to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x16) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh16x64 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) +} +func rewriteValueARM64_OpRsh16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Rsh16x32 [bounded] x y) + // result: (Rsh64x32 [bounded] (SignExt16to64 x) y) for { + t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x32) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v3.AddArg(y) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) + v.AddArg2(v0, y) return true } - return false } -func rewriteValueARM64_OpRsh16x8(v *Value) bool { +func rewriteValueARM64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh16x8 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt16to64 x) y) + // match: (Rsh16x64 [bounded] x y) + // result: (Rsh64x64 [bounded] (SignExt16to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x64) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh16x8 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) +} +func rewriteValueARM64_OpRsh16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Rsh16x8 [bounded] x y) + // result: (Rsh64x8 [bounded] (SignExt16to64 x) y) for { + t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x8) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) + v.AddArg2(v0, y) return true } - return false } func rewriteValueARM64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh32Ux16 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt32to64 x) y) + // match: (Rsh32Ux16 [bounded] x y) + // result: (Rsh64Ux16 [bounded] (ZeroExt32to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) + v.reset(OpRsh64Ux16) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh32Ux16 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v.AddArg3(v0, v2, v3) - return true - } - return false } func rewriteValueARM64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh32Ux32 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt32to64 x) y) + // match: (Rsh32Ux32 [bounded] x y) + // result: (Rsh64Ux32 [bounded] (ZeroExt32to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) + v.reset(OpRsh64Ux32) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh32Ux32 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v.AddArg3(v0, v2, v3) - return true - } - return false } func rewriteValueARM64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh32Ux64 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt32to64 x) y) + // match: (Rsh32Ux64 [bounded] x y) + // result: (Rsh64Ux64 [bounded] (ZeroExt32to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) + v.reset(OpRsh64Ux64) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh32Ux64 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] y)) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v3.AddArg(y) - v.AddArg3(v0, v2, v3) - return true - } - return false } func rewriteValueARM64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh32Ux8 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt32to64 x) y) + // match: (Rsh32Ux8 [bounded] x y) + // result: (Rsh64Ux8 [bounded] (ZeroExt32to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) + v.reset(OpRsh64Ux8) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh32Ux8 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v.AddArg3(v0, v2, v3) - return true - } - return false } func rewriteValueARM64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh32x16 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt32to64 x) y) + // match: (Rsh32x16 [bounded] x y) + // result: (Rsh64x16 [bounded] (SignExt32to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x16) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh32x16 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) - for { - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) - v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) - return true - } - return false } func rewriteValueARM64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh32x32 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt32to64 x) y) + // match: (Rsh32x32 [bounded] x y) + // result: (Rsh64x32 [bounded] (SignExt32to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x32) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh32x32 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) - for { - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) - v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) - return true - } - return false } func rewriteValueARM64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh32x64 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt32to64 x) y) + // match: (Rsh32x64 [bounded] x y) + // result: (Rsh64x64 [bounded] (SignExt32to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x64) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh32x64 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) - for { - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) - v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v3.AddArg(y) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) - return true - } - return false } func rewriteValueARM64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh32x8 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt32to64 x) y) + // match: (Rsh32x8 [bounded] x y) + // result: (Rsh64x8 [bounded] (SignExt32to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x8) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh32x8 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) - for { - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) - v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) - return true - } - return false } func rewriteValueARM64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] @@ -20925,28 +22731,23 @@ func rewriteValueARM64_OpRsh64Ux16(v *Value) bool { v.AddArg2(x, y) return true } - // match: (Rsh64Ux16 x y) + // match: (Rsh64Ux16 [bounded] x y) // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) + // result: (Rsh64Ux32 [bounded] x (ZeroExt16to32 y)) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.reset(OpRsh64Ux32) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) + v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v0.AddArg(y) + v.AddArg2(x, v0) return true } return false @@ -20955,7 +22756,6 @@ func rewriteValueARM64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL x y) @@ -20973,7 +22773,7 @@ func rewriteValueARM64_OpRsh64Ux32(v *Value) bool { } // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) + // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPWconst [64] y)) for { t := v.Type x := v_0 @@ -20987,11 +22787,9 @@ func rewriteValueARM64_OpRsh64Ux32(v *Value) bool { v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) + v2 := b.NewValue0(v.Pos, OpARM64CMPWconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(64) + v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } @@ -21060,28 +22858,23 @@ func rewriteValueARM64_OpRsh64Ux8(v *Value) bool { v.AddArg2(x, y) return true } - // match: (Rsh64Ux8 x y) + // match: (Rsh64Ux8 [bounded] x y) // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + // result: (Rsh64Ux32 [bounded] x (ZeroExt8to32 y)) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(0) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v.AddArg3(v0, v1, v2) + v.reset(OpRsh64Ux32) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) + v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v0.AddArg(y) + v.AddArg2(x, v0) return true } return false @@ -21106,26 +22899,22 @@ func rewriteValueARM64_OpRsh64x16(v *Value) bool { v.AddArg2(x, y) return true } - // match: (Rsh64x16 x y) + // match: (Rsh64x16 [bounded] x y) // cond: !shiftIsBounded(v) - // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) + // result: (Rsh64x32 [bounded] x (ZeroExt16to32 y)) for { + t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } - v.reset(OpARM64SRA) - v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v0.AuxInt = opToAuxInt(OpARM64LessThanU) - v1 := b.NewValue0(v.Pos, OpConst64, y.Type) - v1.AuxInt = int64ToAuxInt(63) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v0.AddArg3(y, v1, v2) + v.reset(OpRsh64x32) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) + v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v0.AddArg(y) v.AddArg2(x, v0) return true } @@ -21135,7 +22924,6 @@ func rewriteValueARM64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SRA x y) @@ -21151,9 +22939,9 @@ func rewriteValueARM64_OpRsh64x32(v *Value) bool { v.AddArg2(x, y) return true } - // match: (Rsh64x32 x y) + // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) - // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) + // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPWconst [64] y))) for { x := v_0 y := v_1 @@ -21165,11 +22953,9 @@ func rewriteValueARM64_OpRsh64x32(v *Value) bool { v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) + v2 := b.NewValue0(v.Pos, OpARM64CMPWconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(64) + v2.AddArg(y) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true @@ -21195,7 +22981,7 @@ func rewriteValueARM64_OpRsh64x64(v *Value) bool { v.AddArg2(x, y) return true } - // match: (Rsh64x64 x y) + // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { @@ -21238,26 +23024,22 @@ func rewriteValueARM64_OpRsh64x8(v *Value) bool { v.AddArg2(x, y) return true } - // match: (Rsh64x8 x y) + // match: (Rsh64x8 [bounded] x y) // cond: !shiftIsBounded(v) - // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) + // result: (Rsh64x32 [bounded] x (ZeroExt8to32 y)) for { + t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } - v.reset(OpARM64SRA) - v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v0.AuxInt = opToAuxInt(OpARM64LessThanU) - v1 := b.NewValue0(v.Pos, OpConst64, y.Type) - v1.AuxInt = int64ToAuxInt(63) - v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v2.AuxInt = int64ToAuxInt(64) - v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v3.AddArg(y) - v2.AddArg(v3) - v0.AddArg3(y, v1, v2) + v.reset(OpRsh64x32) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) + v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v0.AddArg(y) v.AddArg2(x, v0) return true } @@ -21268,392 +23050,168 @@ func rewriteValueARM64_OpRsh8Ux16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh8Ux16 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt8to64 x) y) + // match: (Rsh8Ux16 [bounded] x y) + // result: (Rsh64Ux16 [bounded] (ZeroExt8to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) + v.reset(OpRsh64Ux16) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh8Ux16 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v.AddArg3(v0, v2, v3) - return true - } - return false } func rewriteValueARM64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh8Ux32 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt8to64 x) y) + // match: (Rsh8Ux32 [bounded] x y) + // result: (Rsh64Ux32 [bounded] (ZeroExt8to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) + v.reset(OpRsh64Ux32) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh8Ux32 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v.AddArg3(v0, v2, v3) - return true - } - return false } func rewriteValueARM64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh8Ux64 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt8to64 x) y) + // match: (Rsh8Ux64 [bounded] x y) + // result: (Rsh64Ux64 [bounded] (ZeroExt8to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) + v.reset(OpRsh64Ux64) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh8Ux64 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] y)) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v3.AddArg(y) - v.AddArg3(v0, v2, v3) - return true - } - return false } func rewriteValueARM64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh8Ux8 x y) - // cond: shiftIsBounded(v) - // result: (SRL (ZeroExt8to64 x) y) + // match: (Rsh8Ux8 [bounded] x y) + // result: (Rsh64Ux8 [bounded] (ZeroExt8to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRL) + v.reset(OpRsh64Ux8) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) - v.AddArg2(v0, y) - return true - } - // match: (Rsh8Ux8 x y) - // cond: !shiftIsBounded(v) - // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) - for { - t := v.Type - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64CSEL) - v.AuxInt = opToAuxInt(OpARM64LessThanU) - v0 := b.NewValue0(v.Pos, OpARM64SRL, t) - v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v1.AddArg(x) - v0.AddArg2(v1, y) - v2 := b.NewValue0(v.Pos, OpConst64, t) - v2.AuxInt = int64ToAuxInt(0) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v.AddArg3(v0, v2, v3) - return true - } - return false -} -func rewriteValueARM64_OpRsh8x16(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Rsh8x16 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt8to64 x) y) - for { - t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) - v.Type = t - v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) - v0.AddArg(x) - v.AddArg2(v0, y) - return true - } - // match: (Rsh8x16 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) - for { - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) - v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) - return true - } - return false -} -func rewriteValueARM64_OpRsh8x32(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Rsh8x32 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt8to64 x) y) - for { - t := v.Type - x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) - v.Type = t - v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) - v0.AddArg(x) - v.AddArg2(v0, y) - return true - } - // match: (Rsh8x32 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) - for { - x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) - v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) + v.AddArg2(v0, y) return true } - return false } -func rewriteValueARM64_OpRsh8x64(v *Value) bool { +func rewriteValueARM64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh8x64 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt8to64 x) y) + // match: (Rsh8x16 [bounded] x y) + // result: (Rsh64x16 [bounded] (SignExt8to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x16) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh8x64 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) +} +func rewriteValueARM64_OpRsh8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Rsh8x32 [bounded] x y) + // result: (Rsh64x32 [bounded] (SignExt8to64 x) y) for { + t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x32) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v3.AddArg(y) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) + v.AddArg2(v0, y) return true } - return false } -func rewriteValueARM64_OpRsh8x8(v *Value) bool { +func rewriteValueARM64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Rsh8x8 x y) - // cond: shiftIsBounded(v) - // result: (SRA (SignExt8to64 x) y) + // match: (Rsh8x64 [bounded] x y) + // result: (Rsh64x64 [bounded] (SignExt8to64 x) y) for { t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x64) v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } - // match: (Rsh8x8 x y) - // cond: !shiftIsBounded(v) - // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) +} +func rewriteValueARM64_OpRsh8x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Rsh8x8 [bounded] x y) + // result: (Rsh64x8 [bounded] (SignExt8to64 x) y) for { + t := v.Type + bounded := auxIntToBool(v.AuxInt) x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpARM64SRA) + v.reset(OpRsh64x8) + v.Type = t + v.AuxInt = boolToAuxInt(bounded) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) - v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) - v1.AuxInt = opToAuxInt(OpARM64LessThanU) - v2 := b.NewValue0(v.Pos, OpConst64, y.Type) - v2.AuxInt = int64ToAuxInt(63) - v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) - v3.AuxInt = int64ToAuxInt(64) - v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) - v4.AddArg(y) - v3.AddArg(v4) - v1.AddArg3(y, v2, v3) - v.AddArg2(v0, v1) + v.AddArg2(v0, y) return true } - return false } func rewriteValueARM64_OpSelect0(v *Value) bool { v_0 := v.Args[0] @@ -21882,7 +23440,487 @@ func rewriteValueARM64_OpSelectN(v *Value) bool { v.AddArg3(dst, src, mem) return true } - return false + return false +} +func rewriteValueARM64_OpShiftAllLeftInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftInt16x8 x y) + // result: (VSSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VSSHL8H) + v0 := b.NewValue0(v.Pos, OpARM64VDUPHbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVHins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v2.AuxInt = opToAuxInt(OpARM64LessThanU) + v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = int64ToAuxInt(127) + v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v4.AuxInt = int64ToAuxInt(127) + v4.AddArg(y) + v2.AddArg3(y, v3, v4) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllLeftInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftInt32x4 x y) + // result: (VSSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VSSHL4S) + v0 := b.NewValue0(v.Pos, OpARM64VDUPSbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVSins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v2.AuxInt = opToAuxInt(OpARM64LessThanU) + v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = int64ToAuxInt(127) + v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v4.AuxInt = int64ToAuxInt(127) + v4.AddArg(y) + v2.AddArg3(y, v3, v4) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllLeftInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftInt64x2 x y) + // result: (VSSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VSSHL2D) + v0 := b.NewValue0(v.Pos, OpARM64VDUPDbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVDins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v2.AuxInt = opToAuxInt(OpARM64LessThanU) + v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = int64ToAuxInt(127) + v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v4.AuxInt = int64ToAuxInt(127) + v4.AddArg(y) + v2.AddArg3(y, v3, v4) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllLeftInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftInt8x16 x y) + // result: (VSSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VSSHL16B) + v0 := b.NewValue0(v.Pos, OpARM64VDUPBbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVBins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v2.AuxInt = opToAuxInt(OpARM64LessThanU) + v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = int64ToAuxInt(127) + v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v4.AuxInt = int64ToAuxInt(127) + v4.AddArg(y) + v2.AddArg3(y, v3, v4) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllLeftUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftUint16x8 x y) + // result: (VUSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VUSHL8H) + v0 := b.NewValue0(v.Pos, OpARM64VDUPHbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVHins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v2.AuxInt = opToAuxInt(OpARM64LessThanU) + v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = int64ToAuxInt(127) + v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v4.AuxInt = int64ToAuxInt(127) + v4.AddArg(y) + v2.AddArg3(y, v3, v4) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllLeftUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftUint32x4 x y) + // result: (VUSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VUSHL4S) + v0 := b.NewValue0(v.Pos, OpARM64VDUPSbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVSins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v2.AuxInt = opToAuxInt(OpARM64LessThanU) + v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = int64ToAuxInt(127) + v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v4.AuxInt = int64ToAuxInt(127) + v4.AddArg(y) + v2.AddArg3(y, v3, v4) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllLeftUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftUint64x2 x y) + // result: (VUSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VUSHL2D) + v0 := b.NewValue0(v.Pos, OpARM64VDUPDbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVDins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v2.AuxInt = opToAuxInt(OpARM64LessThanU) + v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = int64ToAuxInt(127) + v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v4.AuxInt = int64ToAuxInt(127) + v4.AddArg(y) + v2.AddArg3(y, v3, v4) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllLeftUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftUint8x16 x y) + // result: (VUSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VUSHL16B) + v0 := b.NewValue0(v.Pos, OpARM64VDUPBbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVBins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v2.AuxInt = opToAuxInt(OpARM64LessThanU) + v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = int64ToAuxInt(127) + v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v4.AuxInt = int64ToAuxInt(127) + v4.AddArg(y) + v2.AddArg3(y, v3, v4) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllRightInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightInt16x8 x y) + // result: (VSSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VSSHL8H) + v0 := b.NewValue0(v.Pos, OpARM64VDUPHbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVHins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) + v3 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v3.AuxInt = opToAuxInt(OpARM64LessThanU) + v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v4.AuxInt = int64ToAuxInt(127) + v5 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v5.AuxInt = int64ToAuxInt(127) + v5.AddArg(y) + v3.AddArg3(y, v4, v5) + v2.AddArg(v3) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllRightInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightInt32x4 x y) + // result: (VSSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VSSHL4S) + v0 := b.NewValue0(v.Pos, OpARM64VDUPSbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVSins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) + v3 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v3.AuxInt = opToAuxInt(OpARM64LessThanU) + v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v4.AuxInt = int64ToAuxInt(127) + v5 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v5.AuxInt = int64ToAuxInt(127) + v5.AddArg(y) + v3.AddArg3(y, v4, v5) + v2.AddArg(v3) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllRightInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightInt64x2 x y) + // result: (VSSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VSSHL2D) + v0 := b.NewValue0(v.Pos, OpARM64VDUPDbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVDins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) + v3 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v3.AuxInt = opToAuxInt(OpARM64LessThanU) + v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v4.AuxInt = int64ToAuxInt(127) + v5 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v5.AuxInt = int64ToAuxInt(127) + v5.AddArg(y) + v3.AddArg3(y, v4, v5) + v2.AddArg(v3) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllRightInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightInt8x16 x y) + // result: (VSSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VSSHL16B) + v0 := b.NewValue0(v.Pos, OpARM64VDUPBbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVBins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) + v3 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v3.AuxInt = opToAuxInt(OpARM64LessThanU) + v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v4.AuxInt = int64ToAuxInt(127) + v5 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v5.AuxInt = int64ToAuxInt(127) + v5.AddArg(y) + v3.AddArg3(y, v4, v5) + v2.AddArg(v3) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllRightUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightUint16x8 x y) + // result: (VUSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VUSHL8H) + v0 := b.NewValue0(v.Pos, OpARM64VDUPHbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVHins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) + v3 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v3.AuxInt = opToAuxInt(OpARM64LessThanU) + v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v4.AuxInt = int64ToAuxInt(127) + v5 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v5.AuxInt = int64ToAuxInt(127) + v5.AddArg(y) + v3.AddArg3(y, v4, v5) + v2.AddArg(v3) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllRightUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightUint32x4 x y) + // result: (VUSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VUSHL4S) + v0 := b.NewValue0(v.Pos, OpARM64VDUPSbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVSins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) + v3 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v3.AuxInt = opToAuxInt(OpARM64LessThanU) + v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v4.AuxInt = int64ToAuxInt(127) + v5 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v5.AuxInt = int64ToAuxInt(127) + v5.AddArg(y) + v3.AddArg3(y, v4, v5) + v2.AddArg(v3) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllRightUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightUint64x2 x y) + // result: (VUSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VUSHL2D) + v0 := b.NewValue0(v.Pos, OpARM64VDUPDbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVDins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) + v3 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v3.AuxInt = opToAuxInt(OpARM64LessThanU) + v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v4.AuxInt = int64ToAuxInt(127) + v5 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v5.AuxInt = int64ToAuxInt(127) + v5.AddArg(y) + v3.AddArg3(y, v4, v5) + v2.AddArg(v3) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueARM64_OpShiftAllRightUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightUint8x16 x y) + // result: (VUSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (NEG (CSEL [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) + for { + x := v_0 + y := v_1 + v.reset(OpARM64VUSHL16B) + v0 := b.NewValue0(v.Pos, OpARM64VDUPBbcast, typ.Vec128) + v0.AuxInt = uint8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpARM64VMOVBins, typ.Vec128) + v1.AuxInt = uint8ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) + v3 := b.NewValue0(v.Pos, OpARM64CSEL, typ.UInt64) + v3.AuxInt = opToAuxInt(OpARM64LessThanU) + v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) + v4.AuxInt = int64ToAuxInt(127) + v5 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) + v5.AuxInt = int64ToAuxInt(127) + v5.AddArg(y) + v3.AddArg3(y, v4, v5) + v2.AddArg(v3) + v1.AddArg2(x, v2) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } } func rewriteValueARM64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] @@ -21994,6 +24032,21 @@ func rewriteValueARM64_OpStore(v *Value) bool { v.AddArg3(ptr, val, mem) return true } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 16 + // result: (FMOVQstore ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 16) { + break + } + v.reset(OpARM64FMOVQstore) + v.AddArg3(ptr, val, mem) + return true + } return false } func rewriteValueARM64_OpZero(v *Value) bool { @@ -22301,6 +24354,142 @@ func rewriteValueARM64_OpZero(v *Value) bool { } return false } +func rewriteValueARM64_OpZeroSIMD(v *Value) bool { + // match: (ZeroSIMD ) + // cond: t.Size() == 16 + // result: (VMOVI16B [0] ) + for { + t := v.Type + if !(t.Size() == 16) { + break + } + v.reset(OpARM64VMOVI16B) + v.Type = t + v.AuxInt = uint8ToAuxInt(0) + return true + } + return false +} +func rewriteValueARM64_Opbroadcast1To16Int8x16(v *Value) bool { + v_0 := v.Args[0] + // match: (broadcast1To16Int8x16 x) + // result: (VDUPBbcast [0] x) + for { + x := v_0 + v.reset(OpARM64VDUPBbcast) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_Opbroadcast1To16Uint8x16(v *Value) bool { + v_0 := v.Args[0] + // match: (broadcast1To16Uint8x16 x) + // result: (VDUPBbcast [0] x) + for { + x := v_0 + v.reset(OpARM64VDUPBbcast) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_Opbroadcast1To2Float64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (broadcast1To2Float64x2 x) + // result: (VDUPDbcast [0] x) + for { + x := v_0 + v.reset(OpARM64VDUPDbcast) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_Opbroadcast1To2Int64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (broadcast1To2Int64x2 x) + // result: (VDUPDbcast [0] x) + for { + x := v_0 + v.reset(OpARM64VDUPDbcast) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_Opbroadcast1To2Uint64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (broadcast1To2Uint64x2 x) + // result: (VDUPDbcast [0] x) + for { + x := v_0 + v.reset(OpARM64VDUPDbcast) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_Opbroadcast1To4Float32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (broadcast1To4Float32x4 x) + // result: (VDUPSbcast [0] x) + for { + x := v_0 + v.reset(OpARM64VDUPSbcast) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_Opbroadcast1To4Int32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (broadcast1To4Int32x4 x) + // result: (VDUPSbcast [0] x) + for { + x := v_0 + v.reset(OpARM64VDUPSbcast) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_Opbroadcast1To4Uint32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (broadcast1To4Uint32x4 x) + // result: (VDUPSbcast [0] x) + for { + x := v_0 + v.reset(OpARM64VDUPSbcast) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_Opbroadcast1To8Int16x8(v *Value) bool { + v_0 := v.Args[0] + // match: (broadcast1To8Int16x8 x) + // result: (VDUPHbcast [0] x) + for { + x := v_0 + v.reset(OpARM64VDUPHbcast) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_Opbroadcast1To8Uint16x8(v *Value) bool { + v_0 := v.Args[0] + // match: (broadcast1To8Uint16x8 x) + // result: (VDUPHbcast [0] x) + for { + x := v_0 + v.reset(OpARM64VDUPHbcast) + v.AuxInt = uint8ToAuxInt(0) + v.AddArg(x) + return true + } +} func rewriteBlockARM64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { @@ -25024,6 +27213,38 @@ func rewriteBlockARM64(b *Block) bool { b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } + // match: (NZ s:(SRLconst [63] x) yes no) + // cond: s.Uses == 1 + // result: (TBNZ [63] x yes no) + for b.Controls[0].Op == OpARM64SRLconst { + s := b.Controls[0] + if auxIntToInt64(s.AuxInt) != 63 { + break + } + x := s.Args[0] + if !(s.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBNZ, x) + b.AuxInt = int64ToAuxInt(63) + return true + } + // match: (NZ s:(SRAconst [63] x) yes no) + // cond: s.Uses == 1 + // result: (TBNZ [63] x yes no) + for b.Controls[0].Op == OpARM64SRAconst { + s := b.Controls[0] + if auxIntToInt64(s.AuxInt) != 63 { + break + } + x := s.Args[0] + if !(s.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBNZ, x) + b.AuxInt = int64ToAuxInt(63) + return true + } // match: (NZ (MOVDconst [0]) yes no) // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { @@ -25273,6 +27494,241 @@ func rewriteBlockARM64(b *Block) bool { b.resetWithControl(BlockARM64FGE, cc) return true } + // match: (TBNZ [0] (XORconst [1] x) yes no) + // result: (TBZ [0] x yes no) + for b.Controls[0].Op == OpARM64XORconst { + v_0 := b.Controls[0] + if auxIntToInt64(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + if auxIntToInt64(b.AuxInt) != 0 { + break + } + b.resetWithControl(BlockARM64TBZ, x) + b.AuxInt = int64ToAuxInt(0) + return true + } + // match: (TBNZ [t] sv:(SRLconst [s] x) yes no) + // cond: t+s < 64 && sv.Uses == 1 + // result: (TBNZ [t+s] x yes no ) + for b.Controls[0].Op == OpARM64SRLconst { + sv := b.Controls[0] + s := auxIntToInt64(sv.AuxInt) + x := sv.Args[0] + t := auxIntToInt64(b.AuxInt) + if !(t+s < 64 && sv.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBNZ, x) + b.AuxInt = int64ToAuxInt(t + s) + return true + } + // match: (TBNZ [t] (SRLconst [s] x) yes no) + // cond: t+s >= 64 + // result: (First no yes) + for b.Controls[0].Op == OpARM64SRLconst { + v_0 := b.Controls[0] + s := auxIntToInt64(v_0.AuxInt) + t := auxIntToInt64(b.AuxInt) + if !(t+s >= 64) { + break + } + b.Reset(BlockFirst) + b.swapSuccessors() + return true + } + // match: (TBNZ [t] sv:(SLLconst [s] x) yes no) + // cond: t-s >= 0 && sv.Uses == 1 + // result: (TBNZ [t-s] x yes no ) + for b.Controls[0].Op == OpARM64SLLconst { + sv := b.Controls[0] + s := auxIntToInt64(sv.AuxInt) + x := sv.Args[0] + t := auxIntToInt64(b.AuxInt) + if !(t-s >= 0 && sv.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBNZ, x) + b.AuxInt = int64ToAuxInt(t - s) + return true + } + // match: (TBNZ [t] (SLLconst [s] x) yes no) + // cond: t-s < 0 + // result: (First no yes) + for b.Controls[0].Op == OpARM64SLLconst { + v_0 := b.Controls[0] + s := auxIntToInt64(v_0.AuxInt) + t := auxIntToInt64(b.AuxInt) + if !(t-s < 0) { + break + } + b.Reset(BlockFirst) + b.swapSuccessors() + return true + } + // match: (TBNZ [t] rv:(RORconst [r] x) yes no) + // cond: rv.Uses == 1 + // result: (TBNZ [int64(uint64(t+r)%64)] x yes no) + for b.Controls[0].Op == OpARM64RORconst { + rv := b.Controls[0] + r := auxIntToInt64(rv.AuxInt) + x := rv.Args[0] + t := auxIntToInt64(b.AuxInt) + if !(rv.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBNZ, x) + b.AuxInt = int64ToAuxInt(int64(uint64(t+r) % 64)) + return true + } + // match: (TBNZ [t] sv:(SRAconst [s] x) yes no) + // cond: t+s < 64 && sv.Uses == 1 + // result: (TBNZ [t+s] x yes no) + for b.Controls[0].Op == OpARM64SRAconst { + sv := b.Controls[0] + s := auxIntToInt64(sv.AuxInt) + x := sv.Args[0] + t := auxIntToInt64(b.AuxInt) + if !(t+s < 64 && sv.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBNZ, x) + b.AuxInt = int64ToAuxInt(t + s) + return true + } + // match: (TBNZ [t] sv:(SRAconst [s] x) yes no) + // cond: t+s >= 64 && sv.Uses == 1 + // result: (TBNZ [63 ] x yes no) + for b.Controls[0].Op == OpARM64SRAconst { + sv := b.Controls[0] + s := auxIntToInt64(sv.AuxInt) + x := sv.Args[0] + t := auxIntToInt64(b.AuxInt) + if !(t+s >= 64 && sv.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBNZ, x) + b.AuxInt = int64ToAuxInt(63) + return true + } + case BlockARM64TBZ: + // match: (TBZ [0] (XORconst [1] x) yes no) + // result: (TBNZ [0] x yes no) + for b.Controls[0].Op == OpARM64XORconst { + v_0 := b.Controls[0] + if auxIntToInt64(v_0.AuxInt) != 1 { + break + } + x := v_0.Args[0] + if auxIntToInt64(b.AuxInt) != 0 { + break + } + b.resetWithControl(BlockARM64TBNZ, x) + b.AuxInt = int64ToAuxInt(0) + return true + } + // match: (TBZ [t] sv:(SRLconst [s] x) yes no) + // cond: t+s < 64 && sv.Uses == 1 + // result: (TBZ [t+s] x yes no ) + for b.Controls[0].Op == OpARM64SRLconst { + sv := b.Controls[0] + s := auxIntToInt64(sv.AuxInt) + x := sv.Args[0] + t := auxIntToInt64(b.AuxInt) + if !(t+s < 64 && sv.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBZ, x) + b.AuxInt = int64ToAuxInt(t + s) + return true + } + // match: (TBZ [t] (SRLconst [s] x) yes no) + // cond: t+s >= 64 + // result: (First yes no ) + for b.Controls[0].Op == OpARM64SRLconst { + v_0 := b.Controls[0] + s := auxIntToInt64(v_0.AuxInt) + t := auxIntToInt64(b.AuxInt) + if !(t+s >= 64) { + break + } + b.Reset(BlockFirst) + return true + } + // match: (TBZ [t] sv:(SLLconst [s] x) yes no) + // cond: t-s >= 0 && sv.Uses == 1 + // result: (TBZ [t-s] x yes no ) + for b.Controls[0].Op == OpARM64SLLconst { + sv := b.Controls[0] + s := auxIntToInt64(sv.AuxInt) + x := sv.Args[0] + t := auxIntToInt64(b.AuxInt) + if !(t-s >= 0 && sv.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBZ, x) + b.AuxInt = int64ToAuxInt(t - s) + return true + } + // match: (TBZ [t] (SLLconst [s] x) yes no) + // cond: t-s < 0 + // result: (First yes no ) + for b.Controls[0].Op == OpARM64SLLconst { + v_0 := b.Controls[0] + s := auxIntToInt64(v_0.AuxInt) + t := auxIntToInt64(b.AuxInt) + if !(t-s < 0) { + break + } + b.Reset(BlockFirst) + return true + } + // match: (TBZ [t] rv:(RORconst [r] x) yes no) + // cond: rv.Uses == 1 + // result: (TBZ [int64(uint64(t+r)%64)] x yes no) + for b.Controls[0].Op == OpARM64RORconst { + rv := b.Controls[0] + r := auxIntToInt64(rv.AuxInt) + x := rv.Args[0] + t := auxIntToInt64(b.AuxInt) + if !(rv.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBZ, x) + b.AuxInt = int64ToAuxInt(int64(uint64(t+r) % 64)) + return true + } + // match: (TBZ [t] sv:(SRAconst [s] x) yes no) + // cond: t+s < 64 && sv.Uses == 1 + // result: (TBZ [t+s] x yes no) + for b.Controls[0].Op == OpARM64SRAconst { + sv := b.Controls[0] + s := auxIntToInt64(sv.AuxInt) + x := sv.Args[0] + t := auxIntToInt64(b.AuxInt) + if !(t+s < 64 && sv.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBZ, x) + b.AuxInt = int64ToAuxInt(t + s) + return true + } + // match: (TBZ [t] sv:(SRAconst [s] x) yes no) + // cond: t+s >= 64 && sv.Uses == 1 + // result: (TBZ [63 ] x yes no) + for b.Controls[0].Op == OpARM64SRAconst { + sv := b.Controls[0] + s := auxIntToInt64(sv.AuxInt) + x := sv.Args[0] + t := auxIntToInt64(b.AuxInt) + if !(t+s >= 64 && sv.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBZ, x) + b.AuxInt = int64ToAuxInt(63) + return true + } case BlockARM64UGE: // match: (UGE (FlagConstant [fc]) yes no) // cond: fc.uge() @@ -25511,6 +27967,38 @@ func rewriteBlockARM64(b *Block) bool { b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } + // match: (Z s:(SRLconst [63] x) yes no) + // cond: s.Uses == 1 + // result: (TBZ [63] x yes no) + for b.Controls[0].Op == OpARM64SRLconst { + s := b.Controls[0] + if auxIntToInt64(s.AuxInt) != 63 { + break + } + x := s.Args[0] + if !(s.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBZ, x) + b.AuxInt = int64ToAuxInt(63) + return true + } + // match: (Z s:(SRAconst [63] x) yes no) + // cond: s.Uses == 1 + // result: (TBZ [63] x yes no) + for b.Controls[0].Op == OpARM64SRAconst { + s := b.Controls[0] + if auxIntToInt64(s.AuxInt) != 63 { + break + } + x := s.Args[0] + if !(s.Uses == 1) { + break + } + b.resetWithControl(BlockARM64TBZ, x) + b.AuxInt = int64ToAuxInt(63) + return true + } // match: (Z (MOVDconst [0]) yes no) // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { diff --git a/src/cmd/compile/internal/ssa/rewriteARM64latelower.go b/src/cmd/compile/internal/ssa/rewriteARM64latelower.go index 0fa5e26e93d0f9..43ddb34b30dcb2 100644 --- a/src/cmd/compile/internal/ssa/rewriteARM64latelower.go +++ b/src/cmd/compile/internal/ssa/rewriteARM64latelower.go @@ -653,11 +653,11 @@ func rewriteValueARM64latelower_OpARM64MOVHreg(v *Value) bool { func rewriteValueARM64latelower_OpARM64MOVWUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVWUreg x) - // cond: zeroUpper32Bits(x, 3) + // cond: ZeroUpper32Bits(x, 3) // result: x for { x := v_0 - if !(zeroUpper32Bits(x, 3)) { + if !(ZeroUpper32Bits(x, 3)) { break } v.copyOf(x) diff --git a/src/cmd/compile/internal/ssa/rewriteLOONG64.go b/src/cmd/compile/internal/ssa/rewriteLOONG64.go index 3fc57e9f497eca..7f5099654302f6 100644 --- a/src/cmd/compile/internal/ssa/rewriteLOONG64.go +++ b/src/cmd/compile/internal/ssa/rewriteLOONG64.go @@ -157,6 +157,9 @@ func rewriteValueLOONG64(v *Value) bool { case OpBswap64: v.Op = OpLOONG64REVBV return true + case OpCeil: + v.Op = OpLOONG64FRINTPD + return true case OpClosureCall: v.Op = OpLOONG64CALLclosure return true @@ -286,6 +289,9 @@ func rewriteValueLOONG64(v *Value) bool { case OpFMA: v.Op = OpLOONG64FMADDD return true + case OpFloor: + v.Op = OpLOONG64FRINTMD + return true case OpGetCallerPC: v.Op = OpLOONG64LoweredGetCallerPC return true @@ -360,6 +366,8 @@ func rewriteValueLOONG64(v *Value) bool { return rewriteValueLOONG64_OpLOONG64MOVBstore(v) case OpLOONG64MOVBstoreidx: return rewriteValueLOONG64_OpLOONG64MOVBstoreidx(v) + case OpLOONG64MOVDF: + return rewriteValueLOONG64_OpLOONG64MOVDF(v) case OpLOONG64MOVDload: return rewriteValueLOONG64_OpLOONG64MOVDload(v) case OpLOONG64MOVDloadidx: @@ -694,6 +702,9 @@ func rewriteValueLOONG64(v *Value) bool { case OpRound64F: v.Op = OpLOONG64LoweredRound64F return true + case OpRoundToEven: + v.Op = OpLOONG64FRINTND + return true case OpRsh16Ux16: return rewriteValueLOONG64_OpRsh16Ux16(v) case OpRsh16Ux32: @@ -819,6 +830,12 @@ func rewriteValueLOONG64(v *Value) bool { case OpTailCall: v.Op = OpLOONG64CALLtail return true + case OpTailCallInter: + v.Op = OpLOONG64CALLtailinter + return true + case OpTrunc: + v.Op = OpLOONG64FRINTZD + return true case OpTrunc16to8: v.Op = OpCopy return true @@ -2368,6 +2385,7 @@ func rewriteValueLOONG64_OpLOONG64MOVBUload(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVBUload [off] {sym} ptr (MOVBstore [off] {sym} ptr x _)) // result: (MOVBUreg x) for { @@ -2447,6 +2465,29 @@ func rewriteValueLOONG64_OpLOONG64MOVBUload(v *Value) bool { v.AddArg3(ptr, idx, mem) return true } + // match: (MOVBUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (MOVBUloadidx ptr (SLLVconst [shift] idx) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + mem := v_1 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVBUloadidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg3(ptr, v0, mem) + return true + } // match: (MOVBUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVVconst [int64(read8(sym, int64(off)))]) @@ -2653,6 +2694,21 @@ func rewriteValueLOONG64_OpLOONG64MOVBUreg(v *Value) bool { v.AddArg(x) return true } + // match: (MOVBUreg x:(SRLconst [c] y)) + // cond: c >= 24 + // result: x + for { + x := v_0 + if x.Op != OpLOONG64SRLconst { + break + } + c := auxIntToInt64(x.AuxInt) + if !(c >= 24) { + break + } + v.copyOf(x) + return true + } // match: (MOVBUreg x:(ANDconst [c] y)) // cond: c >= 0 && int64(uint8(c)) == c // result: x @@ -2675,6 +2731,7 @@ func rewriteValueLOONG64_OpLOONG64MOVBload(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVBload [off] {sym} ptr (MOVBstore [off] {sym} ptr x _)) // result: (MOVBreg x) for { @@ -2754,6 +2811,29 @@ func rewriteValueLOONG64_OpLOONG64MOVBload(v *Value) bool { v.AddArg3(ptr, idx, mem) return true } + // match: (MOVBload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (MOVBloadidx ptr (SLLVconst [shift] idx) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + mem := v_1 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVBloadidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg3(ptr, v0, mem) + return true + } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVVconst [int64(int8(read8(sym, int64(off))))]) @@ -2880,6 +2960,7 @@ func rewriteValueLOONG64_OpLOONG64MOVBstore(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+int32(off2)] {sym} ptr val mem) @@ -3047,6 +3128,30 @@ func rewriteValueLOONG64_OpLOONG64MOVBstore(v *Value) bool { v.AddArg4(ptr, idx, val, mem) return true } + // match: (MOVBstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) + // cond: off == 0 && sym == nil + // result: (MOVBstoreidx ptr (SLLVconst [shift] idx) val mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVBstoreidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg4(ptr, v0, val, mem) + return true + } return false } func rewriteValueLOONG64_OpLOONG64MOVBstoreidx(v *Value) bool { @@ -3094,11 +3199,46 @@ func rewriteValueLOONG64_OpLOONG64MOVBstoreidx(v *Value) bool { } return false } +func rewriteValueLOONG64_OpLOONG64MOVDF(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVDF (ABSD (MOVFD x))) + // result: (ABSF x) + for { + if v_0.Op != OpLOONG64ABSD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpLOONG64MOVFD { + break + } + x := v_0_0.Args[0] + v.reset(OpLOONG64ABSF) + v.AddArg(x) + return true + } + // match: (MOVDF (SQRTD (MOVFD x))) + // result: (SQRTF x) + for { + if v_0.Op != OpLOONG64SQRTD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpLOONG64MOVFD { + break + } + x := v_0_0.Args[0] + v.reset(OpLOONG64SQRTF) + v.AddArg(x) + return true + } + return false +} func rewriteValueLOONG64_OpLOONG64MOVDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVDload [off] {sym} ptr (MOVVstore [off] {sym} ptr val _)) // result: (MOVVgpfp val) for { @@ -3178,6 +3318,29 @@ func rewriteValueLOONG64_OpLOONG64MOVDload(v *Value) bool { v.AddArg3(ptr, idx, mem) return true } + // match: (MOVDload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (MOVDloadidx ptr (SLLVconst [shift] idx) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + mem := v_1 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVDloadidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg3(ptr, v0, mem) + return true + } return false } func rewriteValueLOONG64_OpLOONG64MOVDloadidx(v *Value) bool { @@ -3228,6 +3391,7 @@ func rewriteValueLOONG64_OpLOONG64MOVDstore(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVDstore [off] {sym} ptr (MOVVgpfp val) mem) // result: (MOVVstore [off] {sym} ptr val mem) for { @@ -3310,6 +3474,30 @@ func rewriteValueLOONG64_OpLOONG64MOVDstore(v *Value) bool { v.AddArg4(ptr, idx, val, mem) return true } + // match: (MOVDstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) + // cond: off == 0 && sym == nil + // result: (MOVDstoreidx ptr (SLLVconst [shift] idx) val mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVDstoreidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg4(ptr, v0, val, mem) + return true + } return false } func rewriteValueLOONG64_OpLOONG64MOVDstoreidx(v *Value) bool { @@ -3362,6 +3550,7 @@ func rewriteValueLOONG64_OpLOONG64MOVFload(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVFload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) // result: (MOVWgpfp val) for { @@ -3441,6 +3630,29 @@ func rewriteValueLOONG64_OpLOONG64MOVFload(v *Value) bool { v.AddArg3(ptr, idx, mem) return true } + // match: (MOVFload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (MOVFloadidx ptr (SLLVconst [shift] idx) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + mem := v_1 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVFloadidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg3(ptr, v0, mem) + return true + } return false } func rewriteValueLOONG64_OpLOONG64MOVFloadidx(v *Value) bool { @@ -3491,6 +3703,7 @@ func rewriteValueLOONG64_OpLOONG64MOVFstore(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVFstore [off] {sym} ptr (MOVWgpfp val) mem) // result: (MOVWstore [off] {sym} ptr val mem) for { @@ -3573,6 +3786,30 @@ func rewriteValueLOONG64_OpLOONG64MOVFstore(v *Value) bool { v.AddArg4(ptr, idx, val, mem) return true } + // match: (MOVFstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) + // cond: off == 0 && sym == nil + // result: (MOVFstoreidx ptr (SLLVconst [shift] idx) val mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVFstoreidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg4(ptr, v0, val, mem) + return true + } return false } func rewriteValueLOONG64_OpLOONG64MOVFstoreidx(v *Value) bool { @@ -3625,6 +3862,7 @@ func rewriteValueLOONG64_OpLOONG64MOVHUload(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVHUload [off] {sym} ptr (MOVHstore [off] {sym} ptr x _)) // result: (MOVHUreg x) for { @@ -3704,6 +3942,29 @@ func rewriteValueLOONG64_OpLOONG64MOVHUload(v *Value) bool { v.AddArg3(ptr, idx, mem) return true } + // match: (MOVHUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (MOVHUloadidx ptr (SLLVconst [shift] idx) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + mem := v_1 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVHUloadidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg3(ptr, v0, mem) + return true + } // match: (MOVHUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVVconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) @@ -3872,6 +4133,21 @@ func rewriteValueLOONG64_OpLOONG64MOVHUreg(v *Value) bool { v.AuxInt = int64ToAuxInt(int64(uint16(c))) return true } + // match: (MOVHUreg x:(SRLconst [c] y)) + // cond: c >= 16 + // result: x + for { + x := v_0 + if x.Op != OpLOONG64SRLconst { + break + } + c := auxIntToInt64(x.AuxInt) + if !(c >= 16) { + break + } + v.copyOf(x) + return true + } // match: (MOVHUreg x:(ANDconst [c] y)) // cond: c >= 0 && int64(uint16(c)) == c // result: x @@ -3894,6 +4170,7 @@ func rewriteValueLOONG64_OpLOONG64MOVHload(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVHload [off] {sym} ptr (MOVHstore [off] {sym} ptr x _)) // result: (MOVHreg x) for { @@ -3973,6 +4250,29 @@ func rewriteValueLOONG64_OpLOONG64MOVHload(v *Value) bool { v.AddArg3(ptr, idx, mem) return true } + // match: (MOVHload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (MOVHloadidx ptr (SLLVconst [shift] idx) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + mem := v_1 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVHloadidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg3(ptr, v0, mem) + return true + } // match: (MOVHload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVVconst [int64(int16(read16(sym, int64(off), config.ctxt.Arch.ByteOrder)))]) @@ -4165,6 +4465,7 @@ func rewriteValueLOONG64_OpLOONG64MOVHstore(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstore [off1+int32(off2)] {sym} ptr val mem) @@ -4298,6 +4599,30 @@ func rewriteValueLOONG64_OpLOONG64MOVHstore(v *Value) bool { v.AddArg4(ptr, idx, val, mem) return true } + // match: (MOVHstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) + // cond: off == 0 && sym == nil + // result: (MOVHstoreidx ptr (SLLVconst [shift] idx) val mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVHstoreidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg4(ptr, v0, val, mem) + return true + } return false } func rewriteValueLOONG64_OpLOONG64MOVHstoreidx(v *Value) bool { @@ -4350,6 +4675,7 @@ func rewriteValueLOONG64_OpLOONG64MOVVload(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVVload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) // result: (MOVVfpgp val) for { @@ -4446,6 +4772,29 @@ func rewriteValueLOONG64_OpLOONG64MOVVload(v *Value) bool { v.AddArg3(ptr, idx, mem) return true } + // match: (MOVVload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (MOVVloadidx ptr (SLLVconst [shift] idx) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + mem := v_1 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVVloadidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg3(ptr, v0, mem) + return true + } // match: (MOVVload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVVconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) @@ -4551,6 +4900,7 @@ func rewriteValueLOONG64_OpLOONG64MOVVstore(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVVstore [off] {sym} ptr (MOVVfpgp val) mem) // result: (MOVDstore [off] {sym} ptr val mem) for { @@ -4633,6 +4983,30 @@ func rewriteValueLOONG64_OpLOONG64MOVVstore(v *Value) bool { v.AddArg4(ptr, idx, val, mem) return true } + // match: (MOVVstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) + // cond: off == 0 && sym == nil + // result: (MOVVstoreidx ptr (SLLVconst [shift] idx) val mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVVstoreidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg4(ptr, v0, val, mem) + return true + } return false } func rewriteValueLOONG64_OpLOONG64MOVVstoreidx(v *Value) bool { @@ -4784,6 +5158,29 @@ func rewriteValueLOONG64_OpLOONG64MOVWUload(v *Value) bool { v.AddArg3(ptr, idx, mem) return true } + // match: (MOVWUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (MOVWUloadidx ptr (SLLVconst [shift] idx) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + mem := v_1 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVWUloadidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg3(ptr, v0, mem) + return true + } // match: (MOVWUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVVconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) @@ -4985,6 +5382,16 @@ func rewriteValueLOONG64_OpLOONG64MOVWUreg(v *Value) bool { v.AuxInt = int64ToAuxInt(int64(uint32(c))) return true } + // match: (MOVWUreg x:(SRLconst [c] y)) + // result: x + for { + x := v_0 + if x.Op != OpLOONG64SRLconst { + break + } + v.copyOf(x) + return true + } // match: (MOVWUreg x:(ANDconst [c] y)) // cond: c >= 0 && int64(uint32(c)) == c // result: x @@ -5007,6 +5414,7 @@ func rewriteValueLOONG64_OpLOONG64MOVWload(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVWload [off] {sym} ptr (MOVWstore [off] {sym} ptr x _)) // result: (MOVWreg x) for { @@ -5086,6 +5494,29 @@ func rewriteValueLOONG64_OpLOONG64MOVWload(v *Value) bool { v.AddArg3(ptr, idx, mem) return true } + // match: (MOVWload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) + // cond: off == 0 && sym == nil + // result: (MOVWloadidx ptr (SLLVconst [shift] idx) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + mem := v_1 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVWloadidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg3(ptr, v0, mem) + return true + } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVVconst [int64(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder)))]) @@ -5333,6 +5764,7 @@ func rewriteValueLOONG64_OpLOONG64MOVWstore(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (MOVWstore [off] {sym} ptr (MOVWfpgp val) mem) // result: (MOVFstore [off] {sym} ptr val mem) for { @@ -5449,6 +5881,30 @@ func rewriteValueLOONG64_OpLOONG64MOVWstore(v *Value) bool { v.AddArg4(ptr, idx, val, mem) return true } + // match: (MOVWstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) + // cond: off == 0 && sym == nil + // result: (MOVWstoreidx ptr (SLLVconst [shift] idx) val mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + if v_0.Op != OpLOONG64ADDshiftLLV { + break + } + shift := auxIntToInt64(v_0.AuxInt) + idx := v_0.Args[1] + ptr := v_0.Args[0] + val := v_1 + mem := v_2 + if !(off == 0 && sym == nil) { + break + } + v.reset(OpLOONG64MOVWstoreidx) + v0 := b.NewValue0(v.Pos, OpLOONG64SLLVconst, typ.Int64) + v0.AuxInt = int64ToAuxInt(shift) + v0.AddArg(idx) + v.AddArg4(ptr, v0, val, mem) + return true + } return false } func rewriteValueLOONG64_OpLOONG64MOVWstoreidx(v *Value) bool { @@ -5501,7 +5957,54 @@ func rewriteValueLOONG64_OpLOONG64MULV(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config - typ := &b.Func.Config.Types + // match: (MULV r:(MOVWUreg x) s:(MOVWUreg y)) + // cond: r.Uses == 1 && s.Uses == 1 + // result: (MULWVWU x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + r := v_0 + if r.Op != OpLOONG64MOVWUreg { + continue + } + x := r.Args[0] + s := v_1 + if s.Op != OpLOONG64MOVWUreg { + continue + } + y := s.Args[0] + if !(r.Uses == 1 && s.Uses == 1) { + continue + } + v.reset(OpLOONG64MULWVWU) + v.AddArg2(x, y) + return true + } + break + } + // match: (MULV r:(MOVWreg x) s:(MOVWreg y)) + // cond: r.Uses == 1 && s.Uses == 1 + // result: (MULWVW x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + r := v_0 + if r.Op != OpLOONG64MOVWreg { + continue + } + x := r.Args[0] + s := v_1 + if s.Op != OpLOONG64MOVWreg { + continue + } + y := s.Args[0] + if !(r.Uses == 1 && s.Uses == 1) { + continue + } + v.reset(OpLOONG64MULWVW) + v.AddArg2(x, y) + return true + } + break + } // match: (MULV _ (MOVVconst [0])) // result: (MOVVconst [0]) for { @@ -5546,44 +6049,6 @@ func rewriteValueLOONG64_OpLOONG64MULV(v *Value) bool { } break } - // match: (MULV (NEGV x) (MOVVconst [c])) - // result: (MULV x (MOVVconst [-c])) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpLOONG64NEGV { - continue - } - x := v_0.Args[0] - if v_1.Op != OpLOONG64MOVVconst { - continue - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpLOONG64MULV) - v0 := b.NewValue0(v.Pos, OpLOONG64MOVVconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(-c) - v.AddArg2(x, v0) - return true - } - break - } - // match: (MULV (NEGV x) (NEGV y)) - // result: (MULV x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpLOONG64NEGV { - continue - } - x := v_0.Args[0] - if v_1.Op != OpLOONG64NEGV { - continue - } - y := v_1.Args[0] - v.reset(OpLOONG64MULV) - v.AddArg2(x, y) - return true - } - break - } // match: (MULV (MOVVconst [c]) (MOVVconst [d])) // result: (MOVVconst [c*d]) for { diff --git a/src/cmd/compile/internal/ssa/rewriteMIPS.go b/src/cmd/compile/internal/ssa/rewriteMIPS.go index fda02e64d19d70..a3534c2614f2e2 100644 --- a/src/cmd/compile/internal/ssa/rewriteMIPS.go +++ b/src/cmd/compile/internal/ssa/rewriteMIPS.go @@ -333,10 +333,6 @@ func rewriteValueMIPS(v *Value) bool { return rewriteValueMIPS_OpMIPSMUL(v) case OpMIPSNEG: return rewriteValueMIPS_OpMIPSNEG(v) - case OpMIPSNOR: - return rewriteValueMIPS_OpMIPSNOR(v) - case OpMIPSNORconst: - return rewriteValueMIPS_OpMIPSNORconst(v) case OpMIPSOR: return rewriteValueMIPS_OpMIPSOR(v) case OpMIPSORconst: @@ -576,6 +572,9 @@ func rewriteValueMIPS(v *Value) bool { case OpTailCall: v.Op = OpMIPSCALLtail return true + case OpTailCallInter: + v.Op = OpMIPSCALLtailinter + return true case OpTrunc16to8: v.Op = OpCopy return true @@ -654,7 +653,7 @@ func rewriteValueMIPS_OpAtomicAnd8(v *Value) bool { typ := &b.Func.Config.Types // match: (AtomicAnd8 ptr val mem) // cond: !config.BigEndian - // result: (LoweredAtomicAnd (AND (MOVWconst [^3]) ptr) (OR (SLL (ZeroExt8to32 val) (SLLconst [3] (ANDconst [3] ptr))) (NORconst [0] (SLL (MOVWconst [0xff]) (SLLconst [3] (ANDconst [3] ptr))))) mem) + // result: (LoweredAtomicAnd (AND (MOVWconst [^3]) ptr) (OR (SLL (ZeroExt8to32 val) (SLLconst [3] (ANDconst [3] ptr))) (NOR (MOVWconst [0]) (SLL (MOVWconst [0xff]) (SLLconst [3] (ANDconst [3] ptr))))) mem) for { ptr := v_0 val := v_1 @@ -678,20 +677,21 @@ func rewriteValueMIPS_OpAtomicAnd8(v *Value) bool { v6.AddArg(ptr) v5.AddArg(v6) v3.AddArg2(v4, v5) - v7 := b.NewValue0(v.Pos, OpMIPSNORconst, typ.UInt32) - v7.AuxInt = int32ToAuxInt(0) - v8 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32) - v9 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32) - v9.AuxInt = int32ToAuxInt(0xff) - v8.AddArg2(v9, v5) - v7.AddArg(v8) + v7 := b.NewValue0(v.Pos, OpMIPSNOR, typ.UInt32) + v8 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32) + v8.AuxInt = int32ToAuxInt(0) + v9 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32) + v10 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32) + v10.AuxInt = int32ToAuxInt(0xff) + v9.AddArg2(v10, v5) + v7.AddArg2(v8, v9) v2.AddArg2(v3, v7) v.AddArg3(v0, v2, mem) return true } // match: (AtomicAnd8 ptr val mem) // cond: config.BigEndian - // result: (LoweredAtomicAnd (AND (MOVWconst [^3]) ptr) (OR (SLL (ZeroExt8to32 val) (SLLconst [3] (ANDconst [3] (XORconst [3] ptr)))) (NORconst [0] (SLL (MOVWconst [0xff]) (SLLconst [3] (ANDconst [3] (XORconst [3] ptr)))))) mem) + // result: (LoweredAtomicAnd (AND (MOVWconst [^3]) ptr) (OR (SLL (ZeroExt8to32 val) (SLLconst [3] (ANDconst [3] (XORconst [3] ptr)))) (NOR (MOVWconst [0]) (SLL (MOVWconst [0xff]) (SLLconst [3] (ANDconst [3] (XORconst [3] ptr)))))) mem) for { ptr := v_0 val := v_1 @@ -718,13 +718,14 @@ func rewriteValueMIPS_OpAtomicAnd8(v *Value) bool { v6.AddArg(v7) v5.AddArg(v6) v3.AddArg2(v4, v5) - v8 := b.NewValue0(v.Pos, OpMIPSNORconst, typ.UInt32) - v8.AuxInt = int32ToAuxInt(0) - v9 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32) - v10 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32) - v10.AuxInt = int32ToAuxInt(0xff) - v9.AddArg2(v10, v5) - v8.AddArg(v9) + v8 := b.NewValue0(v.Pos, OpMIPSNOR, typ.UInt32) + v9 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32) + v9.AuxInt = int32ToAuxInt(0) + v10 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32) + v11 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32) + v11.AuxInt = int32ToAuxInt(0xff) + v10.AddArg2(v11, v5) + v8.AddArg2(v9, v10) v2.AddArg2(v3, v8) v.AddArg3(v0, v2, mem) return true @@ -869,37 +870,46 @@ func rewriteValueMIPS_OpBitLen8(v *Value) bool { } func rewriteValueMIPS_OpCom16(v *Value) bool { v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types // match: (Com16 x) - // result: (NORconst [0] x) + // result: (NOR (MOVWconst [0]) x) for { x := v_0 - v.reset(OpMIPSNORconst) - v.AuxInt = int32ToAuxInt(0) - v.AddArg(x) + v.reset(OpMIPSNOR) + v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg2(v0, x) return true } } func rewriteValueMIPS_OpCom32(v *Value) bool { v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types // match: (Com32 x) - // result: (NORconst [0] x) + // result: (NOR (MOVWconst [0]) x) for { x := v_0 - v.reset(OpMIPSNORconst) - v.AuxInt = int32ToAuxInt(0) - v.AddArg(x) + v.reset(OpMIPSNOR) + v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg2(v0, x) return true } } func rewriteValueMIPS_OpCom8(v *Value) bool { v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types // match: (Com8 x) - // result: (NORconst [0] x) + // result: (NOR (MOVWconst [0]) x) for { x := v_0 - v.reset(OpMIPSNORconst) - v.AuxInt = int32ToAuxInt(0) - v.AddArg(x) + v.reset(OpMIPSNOR) + v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32) + v0.AuxInt = int32ToAuxInt(0) + v.AddArg2(v0, x) return true } } @@ -4197,7 +4207,7 @@ func rewriteValueMIPS_OpMIPSMUL(v *Value) bool { break } // match: (MUL (MOVWconst [c]) x ) - // cond: isUnsignedPowerOfTwo(uint32(c)) + // cond: isPowerOfTwo(uint32(c)) // result: (SLLconst [int32(log32u(uint32(c)))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { @@ -4206,7 +4216,7 @@ func rewriteValueMIPS_OpMIPSMUL(v *Value) bool { } c := auxIntToInt32(v_0.AuxInt) x := v_1 - if !(isUnsignedPowerOfTwo(uint32(c))) { + if !(isPowerOfTwo(uint32(c))) { continue } v.reset(OpMIPSSLLconst) @@ -4273,43 +4283,6 @@ func rewriteValueMIPS_OpMIPSNEG(v *Value) bool { } return false } -func rewriteValueMIPS_OpMIPSNOR(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (NOR x (MOVWconst [c])) - // result: (NORconst [c] x) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMIPSMOVWconst { - continue - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpMIPSNORconst) - v.AuxInt = int32ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - return false -} -func rewriteValueMIPS_OpMIPSNORconst(v *Value) bool { - v_0 := v.Args[0] - // match: (NORconst [c] (MOVWconst [d])) - // result: (MOVWconst [^(c|d)]) - for { - c := auxIntToInt32(v.AuxInt) - if v_0.Op != OpMIPSMOVWconst { - break - } - d := auxIntToInt32(v_0.AuxInt) - v.reset(OpMIPSMOVWconst) - v.AuxInt = int32ToAuxInt(^(c | d)) - return true - } - return false -} func rewriteValueMIPS_OpMIPSOR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -5046,18 +5019,6 @@ func rewriteValueMIPS_OpMIPSXORconst(v *Value) bool { v.copyOf(x) return true } - // match: (XORconst [-1] x) - // result: (NORconst [0] x) - for { - if auxIntToInt32(v.AuxInt) != -1 { - break - } - x := v_0 - v.reset(OpMIPSNORconst) - v.AuxInt = int32ToAuxInt(0) - v.AddArg(x) - return true - } // match: (XORconst [c] (MOVWconst [d])) // result: (MOVWconst [c^d]) for { @@ -6562,6 +6523,23 @@ func rewriteValueMIPS_OpSelect0(v *Value) bool { v.AddArg2(x, y) return true } + // match: (Select0 (Add32carrywithcarry x y c)) + // result: (ADD c (ADD x y)) + for { + if v_0.Op != OpAdd32carrywithcarry { + break + } + t := v_0.Type + c := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + v.reset(OpMIPSADD) + v.Type = t.FieldType(0) + v0 := b.NewValue0(v.Pos, OpMIPSADD, t.FieldType(0)) + v0.AddArg2(x, y) + v.AddArg2(c, v0) + return true + } // match: (Select0 (Sub32carry x y)) // result: (SUB x y) for { @@ -6638,7 +6616,7 @@ func rewriteValueMIPS_OpSelect0(v *Value) bool { break } // match: (Select0 (MULTU (MOVWconst [c]) x )) - // cond: isUnsignedPowerOfTwo(uint32(c)) + // cond: isPowerOfTwo(uint32(c)) // result: (SRLconst [int32(32-log32u(uint32(c)))] x) for { if v_0.Op != OpMIPSMULTU { @@ -6653,7 +6631,7 @@ func rewriteValueMIPS_OpSelect0(v *Value) bool { } c := auxIntToInt32(v_0_0.AuxInt) x := v_0_1 - if !(isUnsignedPowerOfTwo(uint32(c))) { + if !(isPowerOfTwo(uint32(c))) { continue } v.reset(OpMIPSSRLconst) @@ -6759,6 +6737,29 @@ func rewriteValueMIPS_OpSelect1(v *Value) bool { v.AddArg2(x, v0) return true } + // match: (Select1 (Add32carrywithcarry x y c)) + // result: (OR (SGTU x xy:(ADD x y)) (SGTU xy (ADD c xy))) + for { + if v_0.Op != OpAdd32carrywithcarry { + break + } + t := v_0.Type + c := v_0.Args[2] + x := v_0.Args[0] + y := v_0.Args[1] + v.reset(OpMIPSOR) + v.Type = typ.Bool + v0 := b.NewValue0(v.Pos, OpMIPSSGTU, typ.Bool) + xy := b.NewValue0(v.Pos, OpMIPSADD, t.FieldType(0)) + xy.AddArg2(x, y) + v0.AddArg2(x, xy) + v2 := b.NewValue0(v.Pos, OpMIPSSGTU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpMIPSADD, t.FieldType(0)) + v3.AddArg2(c, xy) + v2.AddArg2(xy, v3) + v.AddArg2(v0, v2) + return true + } // match: (Select1 (Sub32carry x y)) // result: (SGTU (SUB x y) x) for { @@ -6834,7 +6835,7 @@ func rewriteValueMIPS_OpSelect1(v *Value) bool { break } // match: (Select1 (MULTU (MOVWconst [c]) x )) - // cond: isUnsignedPowerOfTwo(uint32(c)) + // cond: isPowerOfTwo(uint32(c)) // result: (SLLconst [int32(log32u(uint32(c)))] x) for { if v_0.Op != OpMIPSMULTU { @@ -6849,7 +6850,7 @@ func rewriteValueMIPS_OpSelect1(v *Value) bool { } c := auxIntToInt32(v_0_0.AuxInt) x := v_0_1 - if !(isUnsignedPowerOfTwo(uint32(c))) { + if !(isPowerOfTwo(uint32(c))) { continue } v.reset(OpMIPSSLLconst) diff --git a/src/cmd/compile/internal/ssa/rewriteMIPS64.go b/src/cmd/compile/internal/ssa/rewriteMIPS64.go index eae67a2afe10ca..60a22646d6a885 100644 --- a/src/cmd/compile/internal/ssa/rewriteMIPS64.go +++ b/src/cmd/compile/internal/ssa/rewriteMIPS64.go @@ -332,6 +332,8 @@ func rewriteValueMIPS64(v *Value) bool { return rewriteValueMIPS64_OpMIPS64MOVBreg(v) case OpMIPS64MOVBstore: return rewriteValueMIPS64_OpMIPS64MOVBstore(v) + case OpMIPS64MOVDF: + return rewriteValueMIPS64_OpMIPS64MOVDF(v) case OpMIPS64MOVDload: return rewriteValueMIPS64_OpMIPS64MOVDload(v) case OpMIPS64MOVDstore: @@ -370,10 +372,6 @@ func rewriteValueMIPS64(v *Value) bool { return rewriteValueMIPS64_OpMIPS64MOVWstore(v) case OpMIPS64NEGV: return rewriteValueMIPS64_OpMIPS64NEGV(v) - case OpMIPS64NOR: - return rewriteValueMIPS64_OpMIPS64NOR(v) - case OpMIPS64NORconst: - return rewriteValueMIPS64_OpMIPS64NORconst(v) case OpMIPS64OR: return rewriteValueMIPS64_OpMIPS64OR(v) case OpMIPS64ORconst: @@ -641,6 +639,9 @@ func rewriteValueMIPS64(v *Value) bool { case OpTailCall: v.Op = OpMIPS64CALLtail return true + case OpTailCallInter: + v.Op = OpMIPS64CALLtailinter + return true case OpTrunc16to8: v.Op = OpCopy return true @@ -719,7 +720,7 @@ func rewriteValueMIPS64_OpAtomicAnd8(v *Value) bool { typ := &b.Func.Config.Types // match: (AtomicAnd8 ptr val mem) // cond: !config.BigEndian - // result: (LoweredAtomicAnd32 (AND (MOVVconst [^3]) ptr) (OR (SLLV (ZeroExt8to32 val) (SLLVconst [3] (ANDconst [3] ptr))) (NORconst [0] (SLLV (MOVVconst [0xff]) (SLLVconst [3] (ANDconst [3] ptr))))) mem) + // result: (LoweredAtomicAnd32 (AND (MOVVconst [^3]) ptr) (OR (SLLV (ZeroExt8to32 val) (SLLVconst [3] (ANDconst [3] ptr))) (NOR (MOVVconst [0]) (SLLV (MOVVconst [0xff]) (SLLVconst [3] (ANDconst [3] ptr))))) mem) for { ptr := v_0 val := v_1 @@ -743,20 +744,21 @@ func rewriteValueMIPS64_OpAtomicAnd8(v *Value) bool { v6.AddArg(ptr) v5.AddArg(v6) v3.AddArg2(v4, v5) - v7 := b.NewValue0(v.Pos, OpMIPS64NORconst, typ.UInt64) - v7.AuxInt = int64ToAuxInt(0) - v8 := b.NewValue0(v.Pos, OpMIPS64SLLV, typ.UInt64) - v9 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64) - v9.AuxInt = int64ToAuxInt(0xff) - v8.AddArg2(v9, v5) - v7.AddArg(v8) + v7 := b.NewValue0(v.Pos, OpMIPS64NOR, typ.UInt64) + v8 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64) + v8.AuxInt = int64ToAuxInt(0) + v9 := b.NewValue0(v.Pos, OpMIPS64SLLV, typ.UInt64) + v10 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64) + v10.AuxInt = int64ToAuxInt(0xff) + v9.AddArg2(v10, v5) + v7.AddArg2(v8, v9) v2.AddArg2(v3, v7) v.AddArg3(v0, v2, mem) return true } // match: (AtomicAnd8 ptr val mem) // cond: config.BigEndian - // result: (LoweredAtomicAnd32 (AND (MOVVconst [^3]) ptr) (OR (SLLV (ZeroExt8to32 val) (SLLVconst [3] (ANDconst [3] (XORconst [3] ptr)))) (NORconst [0] (SLLV (MOVVconst [0xff]) (SLLVconst [3] (ANDconst [3] (XORconst [3] ptr)))))) mem) + // result: (LoweredAtomicAnd32 (AND (MOVVconst [^3]) ptr) (OR (SLLV (ZeroExt8to32 val) (SLLVconst [3] (ANDconst [3] (XORconst [3] ptr)))) (NOR (MOVVconst [0]) (SLLV (MOVVconst [0xff]) (SLLVconst [3] (ANDconst [3] (XORconst [3] ptr)))))) mem) for { ptr := v_0 val := v_1 @@ -783,13 +785,14 @@ func rewriteValueMIPS64_OpAtomicAnd8(v *Value) bool { v6.AddArg(v7) v5.AddArg(v6) v3.AddArg2(v4, v5) - v8 := b.NewValue0(v.Pos, OpMIPS64NORconst, typ.UInt64) - v8.AuxInt = int64ToAuxInt(0) - v9 := b.NewValue0(v.Pos, OpMIPS64SLLV, typ.UInt64) - v10 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64) - v10.AuxInt = int64ToAuxInt(0xff) - v9.AddArg2(v10, v5) - v8.AddArg(v9) + v8 := b.NewValue0(v.Pos, OpMIPS64NOR, typ.UInt64) + v9 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64) + v9.AuxInt = int64ToAuxInt(0) + v10 := b.NewValue0(v.Pos, OpMIPS64SLLV, typ.UInt64) + v11 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64) + v11.AuxInt = int64ToAuxInt(0xff) + v10.AddArg2(v11, v5) + v8.AddArg2(v9, v10) v2.AddArg2(v3, v8) v.AddArg3(v0, v2, mem) return true @@ -3191,6 +3194,40 @@ func rewriteValueMIPS64_OpMIPS64MOVBstore(v *Value) bool { } return false } +func rewriteValueMIPS64_OpMIPS64MOVDF(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVDF (ABSD (MOVFD x))) + // result: (ABSF x) + for { + if v_0.Op != OpMIPS64ABSD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpMIPS64MOVFD { + break + } + x := v_0_0.Args[0] + v.reset(OpMIPS64ABSF) + v.AddArg(x) + return true + } + // match: (MOVDF (SQRTD (MOVFD x))) + // result: (SQRTF x) + for { + if v_0.Op != OpMIPS64SQRTD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpMIPS64MOVFD { + break + } + x := v_0_0.Args[0] + v.reset(OpMIPS64SQRTF) + v.AddArg(x) + return true + } + return false +} func rewriteValueMIPS64_OpMIPS64MOVDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -4526,47 +4563,6 @@ func rewriteValueMIPS64_OpMIPS64NEGV(v *Value) bool { } return false } -func rewriteValueMIPS64_OpMIPS64NOR(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (NOR x (MOVVconst [c])) - // cond: is32Bit(c) - // result: (NORconst [c] x) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMIPS64MOVVconst { - continue - } - c := auxIntToInt64(v_1.AuxInt) - if !(is32Bit(c)) { - continue - } - v.reset(OpMIPS64NORconst) - v.AuxInt = int64ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - return false -} -func rewriteValueMIPS64_OpMIPS64NORconst(v *Value) bool { - v_0 := v.Args[0] - // match: (NORconst [c] (MOVVconst [d])) - // result: (MOVVconst [^(c|d)]) - for { - c := auxIntToInt64(v.AuxInt) - if v_0.Op != OpMIPS64MOVVconst { - break - } - d := auxIntToInt64(v_0.AuxInt) - v.reset(OpMIPS64MOVVconst) - v.AuxInt = int64ToAuxInt(^(c | d)) - return true - } - return false -} func rewriteValueMIPS64_OpMIPS64OR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -5305,18 +5301,6 @@ func rewriteValueMIPS64_OpMIPS64XORconst(v *Value) bool { v.copyOf(x) return true } - // match: (XORconst [-1] x) - // result: (NORconst [0] x) - for { - if auxIntToInt64(v.AuxInt) != -1 { - break - } - x := v_0 - v.reset(OpMIPS64NORconst) - v.AuxInt = int64ToAuxInt(0) - v.AddArg(x) - return true - } // match: (XORconst [c] (MOVVconst [d])) // result: (MOVVconst [c^d]) for { @@ -6154,6 +6138,8 @@ func rewriteValueMIPS64_OpNot(v *Value) bool { } func rewriteValueMIPS64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types // match: (OffPtr [off] ptr:(SP)) // cond: is32Bit(off) // result: (MOVVaddr [int32(off)] ptr) @@ -6169,15 +6155,35 @@ func rewriteValueMIPS64_OpOffPtr(v *Value) bool { return true } // match: (OffPtr [off] ptr) + // cond: is32Bit(off) // result: (ADDVconst [off] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 + if !(is32Bit(off)) { + break + } v.reset(OpMIPS64ADDVconst) v.AuxInt = int64ToAuxInt(off) v.AddArg(ptr) return true } + // match: (OffPtr [off] ptr) + // cond: !is32Bit(off) + // result: (ADDV ptr (MOVVconst [off])) + for { + off := auxIntToInt64(v.AuxInt) + ptr := v_0 + if !(!is32Bit(off)) { + break + } + v.reset(OpMIPS64ADDV) + v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64) + v0.AuxInt = int64ToAuxInt(off) + v.AddArg2(ptr, v0) + return true + } + return false } func rewriteValueMIPS64_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] diff --git a/src/cmd/compile/internal/ssa/rewritePPC64.go b/src/cmd/compile/internal/ssa/rewritePPC64.go index 050ace83dea2d7..181494e669df00 100644 --- a/src/cmd/compile/internal/ssa/rewritePPC64.go +++ b/src/cmd/compile/internal/ssa/rewritePPC64.go @@ -835,6 +835,9 @@ func rewriteValuePPC64(v *Value) bool { case OpTailCall: v.Op = OpPPC64CALLtail return true + case OpTailCallInter: + v.Op = OpPPC64CALLtailinter + return true case OpTrunc: v.Op = OpPPC64FTRUNC return true @@ -4125,18 +4128,19 @@ func rewriteValuePPC64_OpOffPtr(v *Value) bool { func rewriteValuePPC64_OpPPC64ADD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (ADD l:(MULLD x y) z) + b := v.Block + // match: (ADD z l:(MULLD x y)) // cond: buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) - // result: (MADDLD x y z) + // result: (MADDLD x y z ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - l := v_0 + z := v_0 + l := v_1 if l.Op != OpPPC64MULLD { continue } y := l.Args[1] x := l.Args[0] - z := v_1 if !(buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l)) { continue } @@ -4146,6 +4150,30 @@ func rewriteValuePPC64_OpPPC64ADD(v *Value) bool { } break } + // match: (ADD z l:(MULLDconst [x] y)) + // cond: buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) + // result: (MADDLD (MOVDconst [int64(x)]) y z ) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + z := v_0 + l := v_1 + if l.Op != OpPPC64MULLDconst { + continue + } + mt := l.Type + x := auxIntToInt32(l.AuxInt) + y := l.Args[0] + if !(buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l)) { + continue + } + v.reset(OpPPC64MADDLD) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, mt) + v0.AuxInt = int64ToAuxInt(int64(x)) + v.AddArg3(v0, y, z) + return true + } + break + } // match: (ADD x (MOVDconst [c])) // cond: is32Bit(c) && !t.IsPtr() // result: (ADDconst [c] x) @@ -4239,6 +4267,52 @@ func rewriteValuePPC64_OpPPC64ADDE(v *Value) bool { } func rewriteValuePPC64_OpPPC64ADDconst(v *Value) bool { v_0 := v.Args[0] + b := v.Block + // match: (ADDconst [z] l:(MULLD x y)) + // cond: buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) + // result: (MADDLD x y (MOVDconst [int64(z)])) + for { + at := v.Type + z := auxIntToInt64(v.AuxInt) + l := v_0 + if l.Op != OpPPC64MULLD { + break + } + y := l.Args[1] + x := l.Args[0] + if !(buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l)) { + break + } + v.reset(OpPPC64MADDLD) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, at) + v0.AuxInt = int64ToAuxInt(int64(z)) + v.AddArg3(x, y, v0) + return true + } + // match: (ADDconst [z] l:(MULLDconst [x] y)) + // cond: buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) + // result: (MADDLD (MOVDconst [int64(x)]) y (MOVDconst [int64(z)])) + for { + at := v.Type + z := auxIntToInt64(v.AuxInt) + l := v_0 + if l.Op != OpPPC64MULLDconst { + break + } + mt := l.Type + x := auxIntToInt32(l.AuxInt) + y := l.Args[0] + if !(buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l)) { + break + } + v.reset(OpPPC64MADDLD) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, mt) + v0.AuxInt = int64ToAuxInt(int64(x)) + v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, at) + v1.AuxInt = int64ToAuxInt(int64(z)) + v.AddArg3(v0, y, v1) + return true + } // match: (ADDconst [c] (ADDconst [d] x)) // cond: is32Bit(c+d) // result: (ADDconst [c+d] x) @@ -4324,6 +4398,48 @@ func rewriteValuePPC64_OpPPC64ADDconst(v *Value) bool { func rewriteValuePPC64_OpPPC64AND(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + // match: (AND x (MOVDconst [m])) + // cond: t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m)) + // result: (ANDconst [int64(uint8(m))] x) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpPPC64MOVDconst { + continue + } + m := auxIntToInt64(v_1.AuxInt) + if !(t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m))) { + continue + } + v.reset(OpPPC64ANDconst) + v.AuxInt = int64ToAuxInt(int64(uint8(m))) + v.AddArg(x) + return true + } + break + } + // match: (AND x (MOVDconst [m])) + // cond: t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m)) + // result: (ANDconst [int64(uint16(m))] x) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpPPC64MOVDconst { + continue + } + m := auxIntToInt64(v_1.AuxInt) + if !(t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m))) { + continue + } + v.reset(OpPPC64ANDconst) + v.AuxInt = int64ToAuxInt(int64(uint16(m))) + v.AddArg(x) + return true + } + break + } // match: (AND (MOVDconst [m]) (ROTLWconst [r] x)) // cond: isPPC64WordRotateMask(m) // result: (RLWINM [encodePPC64RotateMask(r,m,32)] x) @@ -11665,6 +11781,48 @@ func rewriteValuePPC64_OpPPC64NotEqual(v *Value) bool { func rewriteValuePPC64_OpPPC64OR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + // match: (OR x (MOVDconst [m])) + // cond: t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m)) + // result: (ORconst [int64(uint8(m))] x) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpPPC64MOVDconst { + continue + } + m := auxIntToInt64(v_1.AuxInt) + if !(t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m))) { + continue + } + v.reset(OpPPC64ORconst) + v.AuxInt = int64ToAuxInt(int64(uint8(m))) + v.AddArg(x) + return true + } + break + } + // match: (OR x (MOVDconst [m])) + // cond: t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m)) + // result: (ORconst [int64(uint16(m))] x) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpPPC64MOVDconst { + continue + } + m := auxIntToInt64(v_1.AuxInt) + if !(t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m))) { + continue + } + v.reset(OpPPC64ORconst) + v.AuxInt = int64ToAuxInt(int64(uint16(m))) + v.AddArg(x) + return true + } + break + } // match: (OR x (NOR y y)) // result: (ORN x y) for { @@ -12540,6 +12698,23 @@ func rewriteValuePPC64_OpPPC64SLDconst(v *Value) bool { } break } + // match: (SLDconst [c] (ADD x x)) + // cond: c < 63 + // result: (SLDconst [c+1] x) + for { + c := auxIntToInt64(v.AuxInt) + if v_0.Op != OpPPC64ADD { + break + } + x := v_0.Args[1] + if x != v_0.Args[0] || !(c < 63) { + break + } + v.reset(OpPPC64SLDconst) + v.AuxInt = int64ToAuxInt(c + 1) + v.AddArg(x) + return true + } // match: (SLDconst [c] z:(MOVWreg x)) // cond: c < 32 && buildcfg.GOPPC64 >= 9 // result: (EXTSWSLconst [c] x) @@ -12676,6 +12851,23 @@ func rewriteValuePPC64_OpPPC64SLWconst(v *Value) bool { } break } + // match: (SLWconst [c] (ADD x x)) + // cond: c < 31 + // result: (SLWconst [c+1] x) + for { + c := auxIntToInt64(v.AuxInt) + if v_0.Op != OpPPC64ADD { + break + } + x := v_0.Args[1] + if x != v_0.Args[0] || !(c < 31) { + break + } + v.reset(OpPPC64SLWconst) + v.AuxInt = int64ToAuxInt(c + 1) + v.AddArg(x) + return true + } // match: (SLWconst [c] z:(MOVWreg x)) // cond: c < 32 && buildcfg.GOPPC64 >= 9 // result: (EXTSWSLconst [c] x) @@ -12974,6 +13166,48 @@ func rewriteValuePPC64_OpPPC64SUBFCconst(v *Value) bool { func rewriteValuePPC64_OpPPC64XOR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + // match: (XOR x (MOVDconst [m])) + // cond: t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m)) + // result: (XORconst [int64(uint8(m))] x) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpPPC64MOVDconst { + continue + } + m := auxIntToInt64(v_1.AuxInt) + if !(t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m))) { + continue + } + v.reset(OpPPC64XORconst) + v.AuxInt = int64ToAuxInt(int64(uint8(m))) + v.AddArg(x) + return true + } + break + } + // match: (XOR x (MOVDconst [m])) + // cond: t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m)) + // result: (XORconst [int64(uint16(m))] x) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpPPC64MOVDconst { + continue + } + m := auxIntToInt64(v_1.AuxInt) + if !(t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m))) { + continue + } + v.reset(OpPPC64XORconst) + v.AuxInt = int64ToAuxInt(int64(uint16(m))) + v.AddArg(x) + return true + } + break + } // match: (XOR (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c^d]) for { diff --git a/src/cmd/compile/internal/ssa/rewritePPC64latelower.go b/src/cmd/compile/internal/ssa/rewritePPC64latelower.go index 18c05280c04bf0..011f66c769f5f6 100644 --- a/src/cmd/compile/internal/ssa/rewritePPC64latelower.go +++ b/src/cmd/compile/internal/ssa/rewritePPC64latelower.go @@ -55,28 +55,6 @@ func rewriteValuePPC64latelower_OpPPC64ADD(v *Value) bool { func rewriteValuePPC64latelower_OpPPC64AND(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (AND x:(MOVDconst [m]) n) - // cond: t.Size() <= 2 - // result: (ANDconst [int64(int16(m))] n) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if x.Op != OpPPC64MOVDconst { - continue - } - m := auxIntToInt64(x.AuxInt) - n := v_1 - if !(t.Size() <= 2) { - continue - } - v.reset(OpPPC64ANDconst) - v.AuxInt = int64ToAuxInt(int64(int16(m))) - v.AddArg(n) - return true - } - break - } // match: (AND x:(MOVDconst [m]) n) // cond: isPPC64ValidShiftMask(m) // result: (RLDICL [encodePPC64RotateMask(0,m,64)] n) diff --git a/src/cmd/compile/internal/ssa/rewriteRISCV64.go b/src/cmd/compile/internal/ssa/rewriteRISCV64.go index a7b4cf1bc402d1..de8a2dcd41ab4e 100644 --- a/src/cmd/compile/internal/ssa/rewriteRISCV64.go +++ b/src/cmd/compile/internal/ssa/rewriteRISCV64.go @@ -4,6 +4,7 @@ package ssa import "internal/buildcfg" import "math" +import "math/bits" import "cmd/compile/internal/types" func rewriteValueRISCV64(v *Value) bool { @@ -132,16 +133,20 @@ func rewriteValueRISCV64(v *Value) bool { case OpCom8: v.Op = OpRISCV64NOT return true + case OpCondSelect: + return rewriteValueRISCV64_OpCondSelect(v) case OpConst16: return rewriteValueRISCV64_OpConst16(v) case OpConst32: return rewriteValueRISCV64_OpConst32(v) case OpConst32F: - return rewriteValueRISCV64_OpConst32F(v) + v.Op = OpRISCV64FMOVFconst + return true case OpConst64: return rewriteValueRISCV64_OpConst64(v) case OpConst64F: - return rewriteValueRISCV64_OpConst64F(v) + v.Op = OpRISCV64FMOVDconst + return true case OpConst8: return rewriteValueRISCV64_OpConst8(v) case OpConstBool: @@ -511,10 +516,16 @@ func rewriteValueRISCV64(v *Value) bool { return rewriteValueRISCV64_OpRISCV64AND(v) case OpRISCV64ANDI: return rewriteValueRISCV64_OpRISCV64ANDI(v) + case OpRISCV64CZEROEQZ: + return rewriteValueRISCV64_OpRISCV64CZEROEQZ(v) + case OpRISCV64CZERONEZ: + return rewriteValueRISCV64_OpRISCV64CZERONEZ(v) case OpRISCV64FADDD: return rewriteValueRISCV64_OpRISCV64FADDD(v) case OpRISCV64FADDS: return rewriteValueRISCV64_OpRISCV64FADDS(v) + case OpRISCV64FCVTSD: + return rewriteValueRISCV64_OpRISCV64FCVTSD(v) case OpRISCV64FEQD: return rewriteValueRISCV64_OpRISCV64FEQD(v) case OpRISCV64FLED: @@ -796,6 +807,9 @@ func rewriteValueRISCV64(v *Value) bool { case OpTailCall: v.Op = OpRISCV64CALLtail return true + case OpTailCallInter: + v.Op = OpRISCV64CALLtailinter + return true case OpTrunc16to8: v.Op = OpCopy return true @@ -1078,6 +1092,30 @@ func rewriteValueRISCV64_OpBswap32(v *Value) bool { return true } } +func rewriteValueRISCV64_OpCondSelect(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (CondSelect x y cond) + // result: (OR (CZEROEQZ x (MOVBUreg cond)) (CZERONEZ y (MOVBUreg cond))) + for { + t := v.Type + x := v_0 + y := v_1 + cond := v_2 + v.reset(OpRISCV64OR) + v0 := b.NewValue0(v.Pos, OpRISCV64CZEROEQZ, t) + v1 := b.NewValue0(v.Pos, OpRISCV64MOVBUreg, typ.UInt64) + v1.AddArg(cond) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpRISCV64CZERONEZ, t) + v2.AddArg2(y, v1) + v.AddArg2(v0, v2) + return true + } +} func rewriteValueRISCV64_OpConst16(v *Value) bool { // match: (Const16 [val]) // result: (MOVDconst [int64(val)]) @@ -1098,20 +1136,6 @@ func rewriteValueRISCV64_OpConst32(v *Value) bool { return true } } -func rewriteValueRISCV64_OpConst32F(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (Const32F [val]) - // result: (FMVSX (MOVDconst [int64(math.Float32bits(val))])) - for { - val := auxIntToFloat32(v.AuxInt) - v.reset(OpRISCV64FMVSX) - v0 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(int64(math.Float32bits(val))) - v.AddArg(v0) - return true - } -} func rewriteValueRISCV64_OpConst64(v *Value) bool { // match: (Const64 [val]) // result: (MOVDconst [int64(val)]) @@ -1122,20 +1146,6 @@ func rewriteValueRISCV64_OpConst64(v *Value) bool { return true } } -func rewriteValueRISCV64_OpConst64F(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (Const64F [val]) - // result: (FMVDX (MOVDconst [int64(math.Float64bits(val))])) - for { - val := auxIntToFloat64(v.AuxInt) - v.reset(OpRISCV64FMVDX) - v0 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(int64(math.Float64bits(val))) - v.AddArg(v0) - return true - } -} func rewriteValueRISCV64_OpConst8(v *Value) bool { // match: (Const8 [val]) // result: (MOVDconst [int64(val)]) @@ -3092,7 +3102,7 @@ func rewriteValueRISCV64_OpMove(v *Value) bool { } // match: (Move [s] {t} dst src mem) // cond: s > 0 && s <= 3*8*moveSize(t.Alignment(), config) && logLargeCopy(v, s) - // result: (LoweredMove [makeValAndOff(int32(s),int32(t.Alignment()))] dst src mem) + // result: (LoweredMove [s] {t.Alignment()} dst src mem) for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) @@ -3103,13 +3113,14 @@ func rewriteValueRISCV64_OpMove(v *Value) bool { break } v.reset(OpRISCV64LoweredMove) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(s), int32(t.Alignment()))) + v.AuxInt = int64ToAuxInt(s) + v.Aux = int64ToAux(t.Alignment()) v.AddArg3(dst, src, mem) return true } // match: (Move [s] {t} dst src mem) // cond: s > 3*8*moveSize(t.Alignment(), config) && logLargeCopy(v, s) - // result: (LoweredMoveLoop [makeValAndOff(int32(s),int32(t.Alignment()))] dst src mem) + // result: (LoweredMoveLoop [s] {t.Alignment()} dst src mem) for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) @@ -3120,7 +3131,8 @@ func rewriteValueRISCV64_OpMove(v *Value) bool { break } v.reset(OpRISCV64LoweredMoveLoop) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(s), int32(t.Alignment()))) + v.AuxInt = int64ToAuxInt(s) + v.Aux = int64ToAux(t.Alignment()) v.AddArg3(dst, src, mem) return true } @@ -3553,6 +3565,129 @@ func rewriteValueRISCV64_OpRISCV64ANDI(v *Value) bool { } return false } +func rewriteValueRISCV64_OpRISCV64CZEROEQZ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CZEROEQZ x (SNEZ y)) + // result: (CZEROEQZ x y) + for { + x := v_0 + if v_1.Op != OpRISCV64SNEZ { + break + } + y := v_1.Args[0] + v.reset(OpRISCV64CZEROEQZ) + v.AddArg2(x, y) + return true + } + // match: (CZEROEQZ x (SEQZ y)) + // result: (CZERONEZ x y) + for { + x := v_0 + if v_1.Op != OpRISCV64SEQZ { + break + } + y := v_1.Args[0] + v.reset(OpRISCV64CZERONEZ) + v.AddArg2(x, y) + return true + } + // match: (CZEROEQZ x (NEG y)) + // result: (CZEROEQZ x y) + for { + x := v_0 + if v_1.Op != OpRISCV64NEG { + break + } + y := v_1.Args[0] + v.reset(OpRISCV64CZEROEQZ) + v.AddArg2(x, y) + return true + } + // match: (CZEROEQZ x x) + // result: x + for { + x := v_0 + if x != v_1 { + break + } + v.copyOf(x) + return true + } + // match: (CZEROEQZ (MOVDconst [0]) _) + // result: (MOVDconst [0]) + for { + if v_0.Op != OpRISCV64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 { + break + } + v.reset(OpRISCV64MOVDconst) + v.AuxInt = int64ToAuxInt(0) + return true + } + return false +} +func rewriteValueRISCV64_OpRISCV64CZERONEZ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (CZERONEZ x (SNEZ y)) + // result: (CZERONEZ x y) + for { + x := v_0 + if v_1.Op != OpRISCV64SNEZ { + break + } + y := v_1.Args[0] + v.reset(OpRISCV64CZERONEZ) + v.AddArg2(x, y) + return true + } + // match: (CZERONEZ x (SEQZ y)) + // result: (CZEROEQZ x y) + for { + x := v_0 + if v_1.Op != OpRISCV64SEQZ { + break + } + y := v_1.Args[0] + v.reset(OpRISCV64CZEROEQZ) + v.AddArg2(x, y) + return true + } + // match: (CZERONEZ x (NEG y)) + // result: (CZERONEZ x y) + for { + x := v_0 + if v_1.Op != OpRISCV64NEG { + break + } + y := v_1.Args[0] + v.reset(OpRISCV64CZERONEZ) + v.AddArg2(x, y) + return true + } + // match: (CZERONEZ x x) + // result: (MOVDconst [0]) + for { + x := v_0 + if x != v_1 { + break + } + v.reset(OpRISCV64MOVDconst) + v.AuxInt = int64ToAuxInt(0) + return true + } + // match: (CZERONEZ (MOVDconst [0]) _) + // result: (MOVDconst [0]) + for { + if v_0.Op != OpRISCV64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 { + break + } + v.reset(OpRISCV64MOVDconst) + v.AuxInt = int64ToAuxInt(0) + return true + } + return false +} func rewriteValueRISCV64_OpRISCV64FADDD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -3603,25 +3738,55 @@ func rewriteValueRISCV64_OpRISCV64FADDS(v *Value) bool { } return false } +func rewriteValueRISCV64_OpRISCV64FCVTSD(v *Value) bool { + v_0 := v.Args[0] + // match: (FCVTSD (FABSD (FCVTDS X))) + // result: (FABSS X) + for { + if v_0.Op != OpRISCV64FABSD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64FCVTDS { + break + } + X := v_0_0.Args[0] + v.reset(OpRISCV64FABSS) + v.AddArg(X) + return true + } + // match: (FCVTSD (FSQRTD (FCVTDS X))) + // result: (FSQRTS X) + for { + if v_0.Op != OpRISCV64FSQRTD { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64FCVTDS { + break + } + X := v_0_0.Args[0] + v.reset(OpRISCV64FSQRTS) + v.AddArg(X) + return true + } + return false +} func rewriteValueRISCV64_OpRISCV64FEQD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (FEQD x (FMVDX (MOVDconst [int64(math.Float64bits(math.Inf(-1)))]))) - // result: (ANDI [1] (FCLASSD x)) + // match: (FEQD x (FMOVDconst [math.Inf(-1)])) + // result: (ANDI [0b00_0000_0001] (FCLASSD x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 - if v_1.Op != OpRISCV64FMVDX { - continue - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRISCV64MOVDconst || auxIntToInt64(v_1_0.AuxInt) != int64(math.Float64bits(math.Inf(-1))) { + if v_1.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != math.Inf(-1) { continue } v.reset(OpRISCV64ANDI) - v.AuxInt = int64ToAuxInt(1) + v.AuxInt = int64ToAuxInt(0b00_0000_0001) v0 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) v0.AddArg(x) v.AddArg(v0) @@ -3629,21 +3794,17 @@ func rewriteValueRISCV64_OpRISCV64FEQD(v *Value) bool { } break } - // match: (FEQD x (FMVDX (MOVDconst [int64(math.Float64bits(math.Inf(1)))]))) - // result: (SNEZ (ANDI [1<<7] (FCLASSD x))) + // match: (FEQD x (FMOVDconst [math.Inf(1)])) + // result: (SNEZ (ANDI [0b00_1000_0000] (FCLASSD x))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 - if v_1.Op != OpRISCV64FMVDX { - continue - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRISCV64MOVDconst || auxIntToInt64(v_1_0.AuxInt) != int64(math.Float64bits(math.Inf(1))) { + if v_1.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != math.Inf(1) { continue } v.reset(OpRISCV64SNEZ) v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) - v0.AuxInt = int64ToAuxInt(1 << 7) + v0.AuxInt = int64ToAuxInt(0b00_1000_0000) v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) v1.AddArg(x) v0.AddArg(v1) @@ -3659,40 +3820,64 @@ func rewriteValueRISCV64_OpRISCV64FLED(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (FLED (FMVDX (MOVDconst [int64(math.Float64bits(-math.MaxFloat64))])) x) - // result: (SNEZ (ANDI [0xff &^ 1] (FCLASSD x))) + // match: (FLED (FMOVDconst [-math.MaxFloat64]) x) + // result: (SNEZ (ANDI [0b00_1111_1110] (FCLASSD x))) for { - if v_0.Op != OpRISCV64FMVDX { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpRISCV64MOVDconst || auxIntToInt64(v_0_0.AuxInt) != int64(math.Float64bits(-math.MaxFloat64)) { + if v_0.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_0.AuxInt) != -math.MaxFloat64 { break } x := v_1 v.reset(OpRISCV64SNEZ) v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) - v0.AuxInt = int64ToAuxInt(0xff &^ 1) + v0.AuxInt = int64ToAuxInt(0b00_1111_1110) v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } - // match: (FLED x (FMVDX (MOVDconst [int64(math.Float64bits(math.MaxFloat64))]))) - // result: (SNEZ (ANDI [0xff &^ (1<<7)] (FCLASSD x))) + // match: (FLED x (FMOVDconst [math.MaxFloat64])) + // result: (SNEZ (ANDI [0b00_0111_1111] (FCLASSD x))) for { x := v_0 - if v_1.Op != OpRISCV64FMVDX { + if v_1.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != math.MaxFloat64 { + break + } + v.reset(OpRISCV64SNEZ) + v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt(0b00_0111_1111) + v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (FLED (FMOVDconst [+0x1p-1022]) x) + // result: (SNEZ (ANDI [0b00_1100_0000] (FCLASSD x))) + for { + if v_0.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_0.AuxInt) != +0x1p-1022 { break } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRISCV64MOVDconst || auxIntToInt64(v_1_0.AuxInt) != int64(math.Float64bits(math.MaxFloat64)) { + x := v_1 + v.reset(OpRISCV64SNEZ) + v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt(0b00_1100_0000) + v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (FLED x (FMOVDconst [-0x1p-1022])) + // result: (SNEZ (ANDI [0b00_0000_0011] (FCLASSD x))) + for { + x := v_0 + if v_1.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != -0x1p-1022 { break } v.reset(OpRISCV64SNEZ) v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) - v0.AuxInt = int64ToAuxInt(0xff &^ (1 << 7)) + v0.AuxInt = int64ToAuxInt(0b00_0000_0011) v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) v1.AddArg(x) v0.AddArg(v1) @@ -3706,38 +3891,62 @@ func rewriteValueRISCV64_OpRISCV64FLTD(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (FLTD x (FMVDX (MOVDconst [int64(math.Float64bits(-math.MaxFloat64))]))) - // result: (ANDI [1] (FCLASSD x)) + // match: (FLTD x (FMOVDconst [-math.MaxFloat64])) + // result: (ANDI [0b00_0000_0001] (FCLASSD x)) for { x := v_0 - if v_1.Op != OpRISCV64FMVDX { - break - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRISCV64MOVDconst || auxIntToInt64(v_1_0.AuxInt) != int64(math.Float64bits(-math.MaxFloat64)) { + if v_1.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != -math.MaxFloat64 { break } v.reset(OpRISCV64ANDI) - v.AuxInt = int64ToAuxInt(1) + v.AuxInt = int64ToAuxInt(0b00_0000_0001) v0 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } - // match: (FLTD (FMVDX (MOVDconst [int64(math.Float64bits(math.MaxFloat64))])) x) - // result: (SNEZ (ANDI [1<<7] (FCLASSD x))) + // match: (FLTD (FMOVDconst [math.MaxFloat64]) x) + // result: (SNEZ (ANDI [0b00_1000_0000] (FCLASSD x))) for { - if v_0.Op != OpRISCV64FMVDX { + if v_0.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_0.AuxInt) != math.MaxFloat64 { break } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpRISCV64MOVDconst || auxIntToInt64(v_0_0.AuxInt) != int64(math.Float64bits(math.MaxFloat64)) { + x := v_1 + v.reset(OpRISCV64SNEZ) + v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt(0b00_1000_0000) + v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (FLTD x (FMOVDconst [+0x1p-1022])) + // result: (SNEZ (ANDI [0b00_0011_1111] (FCLASSD x))) + for { + x := v_0 + if v_1.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != +0x1p-1022 { + break + } + v.reset(OpRISCV64SNEZ) + v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt(0b00_0011_1111) + v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (FLTD (FMOVDconst [-0x1p-1022]) x) + // result: (SNEZ (ANDI [0b00_1111_1100] (FCLASSD x))) + for { + if v_0.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_0.AuxInt) != -0x1p-1022 { break } x := v_1 v.reset(OpRISCV64SNEZ) v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) - v0.AuxInt = int64ToAuxInt(1 << 7) + v0.AuxInt = int64ToAuxInt(0b00_1111_1100) v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) v1.AddArg(x) v0.AddArg(v1) @@ -4175,21 +4384,17 @@ func rewriteValueRISCV64_OpRISCV64FNED(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (FNED x (FMVDX (MOVDconst [int64(math.Float64bits(math.Inf(-1)))]))) - // result: (SEQZ (ANDI [1] (FCLASSD x))) + // match: (FNED x (FMOVDconst [math.Inf(-1)])) + // result: (SEQZ (ANDI [0b00_0000_0001] (FCLASSD x))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 - if v_1.Op != OpRISCV64FMVDX { - continue - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRISCV64MOVDconst || auxIntToInt64(v_1_0.AuxInt) != int64(math.Float64bits(math.Inf(-1))) { + if v_1.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != math.Inf(-1) { continue } v.reset(OpRISCV64SEQZ) v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) - v0.AuxInt = int64ToAuxInt(1) + v0.AuxInt = int64ToAuxInt(0b00_0000_0001) v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) v1.AddArg(x) v0.AddArg(v1) @@ -4198,21 +4403,17 @@ func rewriteValueRISCV64_OpRISCV64FNED(v *Value) bool { } break } - // match: (FNED x (FMVDX (MOVDconst [int64(math.Float64bits(math.Inf(1)))]))) - // result: (SEQZ (ANDI [1<<7] (FCLASSD x))) + // match: (FNED x (FMOVDconst [math.Inf(1)])) + // result: (SEQZ (ANDI [0b00_1000_0000] (FCLASSD x))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 - if v_1.Op != OpRISCV64FMVDX { - continue - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRISCV64MOVDconst || auxIntToInt64(v_1_0.AuxInt) != int64(math.Float64bits(math.Inf(1))) { + if v_1.Op != OpRISCV64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != math.Inf(1) { continue } v.reset(OpRISCV64SEQZ) v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) - v0.AuxInt = int64ToAuxInt(1 << 7) + v0.AuxInt = int64ToAuxInt(0b00_1000_0000) v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) v1.AddArg(x) v0.AddArg(v1) @@ -6471,10 +6672,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(ADDIW _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64ADDIW { + if x.Op != OpRISCV64ADDIW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6482,10 +6684,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(SUBW _ _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64SUBW { + if x.Op != OpRISCV64SUBW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6493,10 +6696,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(NEGW _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64NEGW { + if x.Op != OpRISCV64NEGW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6504,10 +6708,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(MULW _ _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64MULW { + if x.Op != OpRISCV64MULW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6515,10 +6720,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(DIVW _ _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64DIVW { + if x.Op != OpRISCV64DIVW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6526,10 +6732,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(DIVUW _ _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64DIVUW { + if x.Op != OpRISCV64DIVUW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6537,10 +6744,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(REMW _ _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64REMW { + if x.Op != OpRISCV64REMW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6548,10 +6756,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(REMUW _ _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64REMUW { + if x.Op != OpRISCV64REMUW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6559,10 +6768,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(ROLW _ _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64ROLW { + if x.Op != OpRISCV64ROLW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6570,10 +6780,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(RORW _ _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64RORW { + if x.Op != OpRISCV64RORW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6581,10 +6792,11 @@ func rewriteValueRISCV64_OpRISCV64MOVWreg(v *Value) bool { return true } // match: (MOVWreg x:(RORIW _)) + // cond: (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) // result: (MOVDreg x) for { x := v_0 - if x.Op != OpRISCV64RORIW { + if x.Op != OpRISCV64RORIW || !(x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) { break } v.reset(OpRISCV64MOVDreg) @@ -6918,6 +7130,8 @@ func rewriteValueRISCV64_OpRISCV64NEGW(v *Value) bool { func rewriteValueRISCV64_OpRISCV64OR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types // match: (OR (MOVDconst [val]) x) // cond: is32Bit(val) // result: (ORI [val] x) @@ -6948,38 +7162,685 @@ func rewriteValueRISCV64_OpRISCV64OR(v *Value) bool { v.copyOf(x) return true } - return false -} -func rewriteValueRISCV64_OpRISCV64ORI(v *Value) bool { - v_0 := v.Args[0] - // match: (ORI [0] x) - // result: x - for { - if auxIntToInt64(v.AuxInt) != 0 { - break - } - x := v_0 - v.copyOf(x) - return true - } - // match: (ORI [-1] x) - // result: (MOVDconst [-1]) + // match: (OR (CZEROEQZ x cond) (CZERONEZ (ADD x y) cond)) + // result: (ADD x (CZERONEZ y cond)) for { - if auxIntToInt64(v.AuxInt) != -1 { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpRISCV64ADD { + continue + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0_0, v_1_0_1 = _i1+1, v_1_0_1, v_1_0_0 { + if x != v_1_0_0 { + continue + } + y := v_1_0_1 + if cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64ADD) + v0 := b.NewValue0(v.Pos, OpRISCV64CZERONEZ, t) + v0.AddArg2(y, cond) + v.AddArg2(x, v0) + return true + } } - v.reset(OpRISCV64MOVDconst) - v.AuxInt = int64ToAuxInt(-1) - return true + break } - // match: (ORI [x] (MOVDconst [y])) - // result: (MOVDconst [x | y]) + // match: (OR (CZEROEQZ x cond) (CZERONEZ (SUB x y) cond)) + // result: (SUB x (CZERONEZ y cond)) for { - x := auxIntToInt64(v.AuxInt) - if v_0.Op != OpRISCV64MOVDconst { - break - } - y := auxIntToInt64(v_0.AuxInt) + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpRISCV64SUB { + continue + } + y := v_1_0.Args[1] + if x != v_1_0.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64SUB) + v0 := b.NewValue0(v.Pos, OpRISCV64CZERONEZ, t) + v0.AddArg2(y, cond) + v.AddArg2(x, v0) + return true + } + break + } + // match: (OR (CZEROEQZ x cond) (CZERONEZ (OR x y) cond)) + // result: (OR x (CZERONEZ y cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpRISCV64OR { + continue + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0_0, v_1_0_1 = _i1+1, v_1_0_1, v_1_0_0 { + if x != v_1_0_0 { + continue + } + y := v_1_0_1 + if cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64OR) + v0 := b.NewValue0(v.Pos, OpRISCV64CZERONEZ, t) + v0.AddArg2(y, cond) + v.AddArg2(x, v0) + return true + } + } + break + } + // match: (OR (CZEROEQZ x cond) (CZERONEZ (XOR x y) cond)) + // result: (XOR x (CZERONEZ y cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpRISCV64XOR { + continue + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0_0, v_1_0_1 = _i1+1, v_1_0_1, v_1_0_0 { + if x != v_1_0_0 { + continue + } + y := v_1_0_1 + if cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64XOR) + v0 := b.NewValue0(v.Pos, OpRISCV64CZERONEZ, t) + v0.AddArg2(y, cond) + v.AddArg2(x, v0) + return true + } + } + break + } + // match: (OR (CZEROEQZ x cond) (CZERONEZ (SUBW x y) cond)) + // result: (SUBW x (CZERONEZ y cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpRISCV64SUBW { + continue + } + y := v_1_0.Args[1] + if x != v_1_0.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64SUBW) + v0 := b.NewValue0(v.Pos, OpRISCV64CZERONEZ, t) + v0.AddArg2(y, cond) + v.AddArg2(x, v0) + return true + } + break + } + // match: (OR (CZEROEQZ (ADD x y) cond) (CZERONEZ x cond)) + // result: (ADD x (CZEROEQZ y cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64ADD { + continue + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + v_0_0_1 := v_0_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0_0, v_0_0_1 = _i1+1, v_0_0_1, v_0_0_0 { + x := v_0_0_0 + y := v_0_0_1 + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64ADD) + v0 := b.NewValue0(v.Pos, OpRISCV64CZEROEQZ, t) + v0.AddArg2(y, cond) + v.AddArg2(x, v0) + return true + } + } + break + } + // match: (OR (CZEROEQZ (SUB x y) cond) (CZERONEZ x cond)) + // result: (SUB x (CZEROEQZ y cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64SUB { + continue + } + y := v_0_0.Args[1] + x := v_0_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64SUB) + v0 := b.NewValue0(v.Pos, OpRISCV64CZEROEQZ, t) + v0.AddArg2(y, cond) + v.AddArg2(x, v0) + return true + } + break + } + // match: (OR (CZEROEQZ (OR x y) cond) (CZERONEZ x cond)) + // result: (OR x (CZEROEQZ y cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64OR { + continue + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + v_0_0_1 := v_0_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0_0, v_0_0_1 = _i1+1, v_0_0_1, v_0_0_0 { + x := v_0_0_0 + y := v_0_0_1 + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64OR) + v0 := b.NewValue0(v.Pos, OpRISCV64CZEROEQZ, t) + v0.AddArg2(y, cond) + v.AddArg2(x, v0) + return true + } + } + break + } + // match: (OR (CZEROEQZ (XOR x y) cond) (CZERONEZ x cond)) + // result: (XOR x (CZEROEQZ y cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64XOR { + continue + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + v_0_0_1 := v_0_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0_0, v_0_0_1 = _i1+1, v_0_0_1, v_0_0_0 { + x := v_0_0_0 + y := v_0_0_1 + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64XOR) + v0 := b.NewValue0(v.Pos, OpRISCV64CZEROEQZ, t) + v0.AddArg2(y, cond) + v.AddArg2(x, v0) + return true + } + } + break + } + // match: (OR (CZEROEQZ (SUBW x y) cond) (CZERONEZ x cond)) + // result: (SUBW x (CZEROEQZ y cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64SUBW { + continue + } + y := v_0_0.Args[1] + x := v_0_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64SUBW) + v0 := b.NewValue0(v.Pos, OpRISCV64CZEROEQZ, t) + v0.AddArg2(y, cond) + v.AddArg2(x, v0) + return true + } + break + } + // match: (OR x:(CZEROEQZ z cond) (CZERONEZ y:(AND z _) cond)) + // result: (OR y x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if x.Op != OpRISCV64CZEROEQZ { + continue + } + cond := x.Args[1] + z := x.Args[0] + if v_1.Op != OpRISCV64CZERONEZ { + continue + } + _ = v_1.Args[1] + y := v_1.Args[0] + if y.Op != OpRISCV64AND { + continue + } + y_0 := y.Args[0] + y_1 := y.Args[1] + for _i1 := 0; _i1 <= 1; _i1, y_0, y_1 = _i1+1, y_1, y_0 { + if z != y_0 || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64OR) + v.AddArg2(y, x) + return true + } + } + break + } + // match: (OR (CZEROEQZ x:(AND z _) cond) y:(CZERONEZ z cond)) + // result: (OR x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + cond := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpRISCV64AND { + continue + } + x_0 := x.Args[0] + x_1 := x.Args[1] + for _i1 := 0; _i1 <= 1; _i1, x_0, x_1 = _i1+1, x_1, x_0 { + z := x_0 + y := v_1 + if y.Op != OpRISCV64CZERONEZ { + continue + } + _ = y.Args[1] + if z != y.Args[0] || cond != y.Args[1] { + continue + } + v.reset(OpRISCV64OR) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (OR x:(CZEROEQZ z cond) (CZERONEZ y:(ANDI [c] z) cond)) + // result: (OR y x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if x.Op != OpRISCV64CZEROEQZ { + continue + } + cond := x.Args[1] + z := x.Args[0] + if v_1.Op != OpRISCV64CZERONEZ { + continue + } + _ = v_1.Args[1] + y := v_1.Args[0] + if y.Op != OpRISCV64ANDI { + continue + } + if z != y.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64OR) + v.AddArg2(y, x) + return true + } + break + } + // match: (OR (CZEROEQZ x:(ANDI [c] z) cond) y:(CZERONEZ z cond)) + // result: (OR x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + cond := v_0.Args[1] + x := v_0.Args[0] + if x.Op != OpRISCV64ANDI { + continue + } + z := x.Args[0] + y := v_1 + if y.Op != OpRISCV64CZERONEZ { + continue + } + _ = y.Args[1] + if z != y.Args[0] || cond != y.Args[1] { + continue + } + v.reset(OpRISCV64OR) + v.AddArg2(x, y) + return true + } + break + } + // match: (OR (CZEROEQZ x cond) (CZERONEZ (ADDI [c] x) cond)) + // result: (ADD x (CZERONEZ (MOVDconst [c]) cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpRISCV64ADDI { + continue + } + c := auxIntToInt64(v_1_0.AuxInt) + if x != v_1_0.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64ADD) + v0 := b.NewValue0(v.Pos, OpRISCV64CZERONEZ, t) + v1 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64) + v1.AuxInt = int64ToAuxInt(c) + v0.AddArg2(v1, cond) + v.AddArg2(x, v0) + return true + } + break + } + // match: (OR (CZEROEQZ x cond) (CZERONEZ (ORI [c] x) cond)) + // result: (OR x (CZERONEZ (MOVDconst [c]) cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpRISCV64ORI { + continue + } + c := auxIntToInt64(v_1_0.AuxInt) + if x != v_1_0.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64OR) + v0 := b.NewValue0(v.Pos, OpRISCV64CZERONEZ, t) + v1 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64) + v1.AuxInt = int64ToAuxInt(c) + v0.AddArg2(v1, cond) + v.AddArg2(x, v0) + return true + } + break + } + // match: (OR (CZEROEQZ x cond) (CZERONEZ (XORI [c] x) cond)) + // result: (XOR x (CZERONEZ (MOVDconst [c]) cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpRISCV64XORI { + continue + } + c := auxIntToInt64(v_1_0.AuxInt) + if x != v_1_0.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64XOR) + v0 := b.NewValue0(v.Pos, OpRISCV64CZERONEZ, t) + v1 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64) + v1.AuxInt = int64ToAuxInt(c) + v0.AddArg2(v1, cond) + v.AddArg2(x, v0) + return true + } + break + } + // match: (OR (CZEROEQZ (ADDI [c] x) cond) (CZERONEZ x cond)) + // result: (ADD x (CZEROEQZ (MOVDconst [c]) cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64ADDI { + continue + } + c := auxIntToInt64(v_0_0.AuxInt) + x := v_0_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64ADD) + v0 := b.NewValue0(v.Pos, OpRISCV64CZEROEQZ, t) + v1 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64) + v1.AuxInt = int64ToAuxInt(c) + v0.AddArg2(v1, cond) + v.AddArg2(x, v0) + return true + } + break + } + // match: (OR (CZEROEQZ (ORI [c] x) cond) (CZERONEZ x cond)) + // result: (OR x (CZEROEQZ (MOVDconst [c]) cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64ORI { + continue + } + c := auxIntToInt64(v_0_0.AuxInt) + x := v_0_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64OR) + v0 := b.NewValue0(v.Pos, OpRISCV64CZEROEQZ, t) + v1 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64) + v1.AuxInt = int64ToAuxInt(c) + v0.AddArg2(v1, cond) + v.AddArg2(x, v0) + return true + } + break + } + // match: (OR (CZEROEQZ (XORI [c] x) cond) (CZERONEZ x cond)) + // result: (XOR x (CZEROEQZ (MOVDconst [c]) cond)) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpRISCV64CZEROEQZ { + continue + } + t := v_0.Type + cond := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64XORI { + continue + } + c := auxIntToInt64(v_0_0.AuxInt) + x := v_0_0.Args[0] + if v_1.Op != OpRISCV64CZERONEZ || v_1.Type != t { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] || cond != v_1.Args[1] { + continue + } + v.reset(OpRISCV64XOR) + v0 := b.NewValue0(v.Pos, OpRISCV64CZEROEQZ, t) + v1 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64) + v1.AuxInt = int64ToAuxInt(c) + v0.AddArg2(v1, cond) + v.AddArg2(x, v0) + return true + } + break + } + return false +} +func rewriteValueRISCV64_OpRISCV64ORI(v *Value) bool { + v_0 := v.Args[0] + // match: (ORI [0] x) + // result: x + for { + if auxIntToInt64(v.AuxInt) != 0 { + break + } + x := v_0 + v.copyOf(x) + return true + } + // match: (ORI [-1] x) + // result: (MOVDconst [-1]) + for { + if auxIntToInt64(v.AuxInt) != -1 { + break + } + v.reset(OpRISCV64MOVDconst) + v.AuxInt = int64ToAuxInt(-1) + return true + } + // match: (ORI [x] (MOVDconst [y])) + // result: (MOVDconst [x | y]) + for { + x := auxIntToInt64(v.AuxInt) + if v_0.Op != OpRISCV64MOVDconst { + break + } + y := auxIntToInt64(v_0.AuxInt) v.reset(OpRISCV64MOVDconst) v.AuxInt = int64ToAuxInt(x | y) return true @@ -7020,7 +7881,7 @@ func rewriteValueRISCV64_OpRISCV64ROL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ROL x (MOVDconst [val])) - // result: (RORI [int64(int8(-val)&63)] x) + // result: (RORI [-val&63] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { @@ -7028,7 +7889,7 @@ func rewriteValueRISCV64_OpRISCV64ROL(v *Value) bool { } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64RORI) - v.AuxInt = int64ToAuxInt(int64(int8(-val) & 63)) + v.AuxInt = int64ToAuxInt(-val & 63) v.AddArg(x) return true } @@ -7050,7 +7911,7 @@ func rewriteValueRISCV64_OpRISCV64ROLW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ROLW x (MOVDconst [val])) - // result: (RORIW [int64(int8(-val)&31)] x) + // result: (RORIW [-val&31] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { @@ -7058,7 +7919,7 @@ func rewriteValueRISCV64_OpRISCV64ROLW(v *Value) bool { } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64RORIW) - v.AuxInt = int64ToAuxInt(int64(int8(-val) & 31)) + v.AuxInt = int64ToAuxInt(-val & 31) v.AddArg(x) return true } @@ -7080,7 +7941,7 @@ func rewriteValueRISCV64_OpRISCV64ROR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ROR x (MOVDconst [val])) - // result: (RORI [int64(val&63)] x) + // result: (RORI [val&63] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { @@ -7088,7 +7949,7 @@ func rewriteValueRISCV64_OpRISCV64ROR(v *Value) bool { } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64RORI) - v.AuxInt = int64ToAuxInt(int64(val & 63)) + v.AuxInt = int64ToAuxInt(val & 63) v.AddArg(x) return true } @@ -7098,7 +7959,7 @@ func rewriteValueRISCV64_OpRISCV64RORW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RORW x (MOVDconst [val])) - // result: (RORIW [int64(val&31)] x) + // result: (RORIW [val&31] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { @@ -7106,7 +7967,7 @@ func rewriteValueRISCV64_OpRISCV64RORW(v *Value) bool { } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64RORIW) - v.AuxInt = int64ToAuxInt(int64(val & 31)) + v.AuxInt = int64ToAuxInt(val & 31) v.AddArg(x) return true } @@ -7114,6 +7975,8 @@ func rewriteValueRISCV64_OpRISCV64RORW(v *Value) bool { } func rewriteValueRISCV64_OpRISCV64SEQZ(v *Value) bool { v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types // match: (SEQZ (NEG x)) // result: (SEQZ x) for { @@ -7147,13 +8010,63 @@ func rewriteValueRISCV64_OpRISCV64SEQZ(v *Value) bool { v.AddArg(x) return true } + // match: (SEQZ (ANDI [c] (FCLASSD (FNEGD x)))) + // result: (SEQZ (ANDI [(c&0b11_0000_0000)|int64(bits.Reverse8(uint8(c))&0b1111_1111)] (FCLASSD x))) + for { + if v_0.Op != OpRISCV64ANDI { + break + } + c := auxIntToInt64(v_0.AuxInt) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64FCLASSD { + break + } + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRISCV64FNEGD { + break + } + x := v_0_0_0.Args[0] + v.reset(OpRISCV64SEQZ) + v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt((c & 0b11_0000_0000) | int64(bits.Reverse8(uint8(c))&0b1111_1111)) + v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (SEQZ (ANDI [c] (FCLASSD (FABSD x)))) + // result: (SEQZ (ANDI [(c&0b11_1111_0000)|int64(bits.Reverse8(uint8(c))&0b0000_1111)] (FCLASSD x))) + for { + if v_0.Op != OpRISCV64ANDI { + break + } + c := auxIntToInt64(v_0.AuxInt) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64FCLASSD { + break + } + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRISCV64FABSD { + break + } + x := v_0_0_0.Args[0] + v.reset(OpRISCV64SEQZ) + v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt((c & 0b11_1111_0000) | int64(bits.Reverse8(uint8(c))&0b0000_1111)) + v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } return false } func rewriteValueRISCV64_OpRISCV64SLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SLL x (MOVDconst [val])) - // result: (SLLI [int64(val&63)] x) + // result: (SLLI [val&63] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { @@ -7161,7 +8074,7 @@ func rewriteValueRISCV64_OpRISCV64SLL(v *Value) bool { } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64SLLI) - v.AuxInt = int64ToAuxInt(int64(val & 63)) + v.AuxInt = int64ToAuxInt(val & 63) v.AddArg(x) return true } @@ -7187,7 +8100,7 @@ func rewriteValueRISCV64_OpRISCV64SLLI(v *Value) bool { } // match: (SLLI [c] (ADD x x)) // cond: c < t.Size() * 8 - 1 - // result: (SLLI [c+1] x) + // result: (SLLI [c+1] x) for { t := v.Type c := auxIntToInt64(v.AuxInt) @@ -7199,7 +8112,6 @@ func rewriteValueRISCV64_OpRISCV64SLLI(v *Value) bool { break } v.reset(OpRISCV64SLLI) - v.Type = t v.AuxInt = int64ToAuxInt(c + 1) v.AddArg(x) return true @@ -7227,7 +8139,7 @@ func rewriteValueRISCV64_OpRISCV64SLLW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SLLW x (MOVDconst [val])) - // result: (SLLIW [int64(val&31)] x) + // result: (SLLIW [val&31] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { @@ -7235,7 +8147,7 @@ func rewriteValueRISCV64_OpRISCV64SLLW(v *Value) bool { } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64SLLIW) - v.AuxInt = int64ToAuxInt(int64(val & 31)) + v.AuxInt = int64ToAuxInt(val & 31) v.AddArg(x) return true } @@ -7245,7 +8157,7 @@ func rewriteValueRISCV64_OpRISCV64SLT(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SLT x (MOVDconst [val])) - // cond: val >= -2048 && val <= 2047 + // cond: is12Bit(val) // result: (SLTI [val] x) for { x := v_0 @@ -7253,7 +8165,7 @@ func rewriteValueRISCV64_OpRISCV64SLT(v *Value) bool { break } val := auxIntToInt64(v_1.AuxInt) - if !(val >= -2048 && val <= 2047) { + if !(is12Bit(val)) { break } v.reset(OpRISCV64SLTI) @@ -7304,22 +8216,6 @@ func rewriteValueRISCV64_OpRISCV64SLTI(v *Value) bool { v.AuxInt = int64ToAuxInt(1) return true } - // match: (SLTI [x] (ORI [y] _)) - // cond: y >= 0 && int64(y) >= int64(x) - // result: (MOVDconst [0]) - for { - x := auxIntToInt64(v.AuxInt) - if v_0.Op != OpRISCV64ORI { - break - } - y := auxIntToInt64(v_0.AuxInt) - if !(y >= 0 && int64(y) >= int64(x)) { - break - } - v.reset(OpRISCV64MOVDconst) - v.AuxInt = int64ToAuxInt(0) - return true - } return false } func rewriteValueRISCV64_OpRISCV64SLTIU(v *Value) bool { @@ -7374,7 +8270,7 @@ func rewriteValueRISCV64_OpRISCV64SLTU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SLTU x (MOVDconst [val])) - // cond: val >= -2048 && val <= 2047 + // cond: is12Bit(val) // result: (SLTIU [val] x) for { x := v_0 @@ -7382,7 +8278,7 @@ func rewriteValueRISCV64_OpRISCV64SLTU(v *Value) bool { break } val := auxIntToInt64(v_1.AuxInt) - if !(val >= -2048 && val <= 2047) { + if !(is12Bit(val)) { break } v.reset(OpRISCV64SLTIU) @@ -7405,6 +8301,8 @@ func rewriteValueRISCV64_OpRISCV64SLTU(v *Value) bool { } func rewriteValueRISCV64_OpRISCV64SNEZ(v *Value) bool { v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types // match: (SNEZ (NEG x)) // result: (SNEZ x) for { @@ -7438,13 +8336,63 @@ func rewriteValueRISCV64_OpRISCV64SNEZ(v *Value) bool { v.AddArg(x) return true } + // match: (SNEZ (ANDI [c] (FCLASSD (FNEGD x)))) + // result: (SNEZ (ANDI [(c&0b11_0000_0000)|int64(bits.Reverse8(uint8(c))&0b1111_1111)] (FCLASSD x))) + for { + if v_0.Op != OpRISCV64ANDI { + break + } + c := auxIntToInt64(v_0.AuxInt) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64FCLASSD { + break + } + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRISCV64FNEGD { + break + } + x := v_0_0_0.Args[0] + v.reset(OpRISCV64SNEZ) + v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt((c & 0b11_0000_0000) | int64(bits.Reverse8(uint8(c))&0b1111_1111)) + v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (SNEZ (ANDI [c] (FCLASSD (FABSD x)))) + // result: (SNEZ (ANDI [(c&0b11_1111_0000)|int64(bits.Reverse8(uint8(c))&0b0000_1111)] (FCLASSD x))) + for { + if v_0.Op != OpRISCV64ANDI { + break + } + c := auxIntToInt64(v_0.AuxInt) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64FCLASSD { + break + } + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRISCV64FABSD { + break + } + x := v_0_0_0.Args[0] + v.reset(OpRISCV64SNEZ) + v0 := b.NewValue0(v.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt((c & 0b11_1111_0000) | int64(bits.Reverse8(uint8(c))&0b0000_1111)) + v1 := b.NewValue0(v.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } return false } func rewriteValueRISCV64_OpRISCV64SRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SRA x (MOVDconst [val])) - // result: (SRAI [int64(val&63)] x) + // result: (SRAI [val&63] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { @@ -7452,7 +8400,7 @@ func rewriteValueRISCV64_OpRISCV64SRA(v *Value) bool { } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64SRAI) - v.AuxInt = int64ToAuxInt(int64(val & 63)) + v.AuxInt = int64ToAuxInt(val & 63) v.AddArg(x) return true } @@ -7461,11 +8409,10 @@ func rewriteValueRISCV64_OpRISCV64SRA(v *Value) bool { func rewriteValueRISCV64_OpRISCV64SRAI(v *Value) bool { v_0 := v.Args[0] b := v.Block - // match: (SRAI [x] (MOVWreg y)) + // match: (SRAI [x] (MOVWreg y)) // cond: x >= 0 && x <= 31 - // result: (SRAIW [int64(x)] y) + // result: (SRAIW [x] y) for { - t := v.Type x := auxIntToInt64(v.AuxInt) if v_0.Op != OpRISCV64MOVWreg { break @@ -7475,8 +8422,7 @@ func rewriteValueRISCV64_OpRISCV64SRAI(v *Value) bool { break } v.reset(OpRISCV64SRAIW) - v.Type = t - v.AuxInt = int64ToAuxInt(int64(x)) + v.AuxInt = int64ToAuxInt(x) v.AddArg(y) return true } @@ -7522,7 +8468,7 @@ func rewriteValueRISCV64_OpRISCV64SRAI(v *Value) bool { v.AddArg(v0) return true } - // match: (SRAI [x] (MOVWreg y)) + // match: (SRAI [x] (MOVWreg y)) // cond: x >= 32 // result: (SRAIW [31] y) for { @@ -7557,7 +8503,7 @@ func rewriteValueRISCV64_OpRISCV64SRAW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SRAW x (MOVDconst [val])) - // result: (SRAIW [int64(val&31)] x) + // result: (SRAIW [val&31] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { @@ -7565,7 +8511,7 @@ func rewriteValueRISCV64_OpRISCV64SRAW(v *Value) bool { } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64SRAIW) - v.AuxInt = int64ToAuxInt(int64(val & 31)) + v.AuxInt = int64ToAuxInt(val & 31) v.AddArg(x) return true } @@ -7575,7 +8521,7 @@ func rewriteValueRISCV64_OpRISCV64SRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SRL x (MOVDconst [val])) - // result: (SRLI [int64(val&63)] x) + // result: (SRLI [val&63] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { @@ -7583,7 +8529,7 @@ func rewriteValueRISCV64_OpRISCV64SRL(v *Value) bool { } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64SRLI) - v.AuxInt = int64ToAuxInt(int64(val & 63)) + v.AuxInt = int64ToAuxInt(val & 63) v.AddArg(x) return true } @@ -7591,11 +8537,10 @@ func rewriteValueRISCV64_OpRISCV64SRL(v *Value) bool { } func rewriteValueRISCV64_OpRISCV64SRLI(v *Value) bool { v_0 := v.Args[0] - // match: (SRLI [x] (MOVWUreg y)) + // match: (SRLI [x] (MOVWUreg y)) // cond: x >= 0 && x <= 31 - // result: (SRLIW [int64(x)] y) + // result: (SRLIW [x] y) for { - t := v.Type x := auxIntToInt64(v.AuxInt) if v_0.Op != OpRISCV64MOVWUreg { break @@ -7605,16 +8550,14 @@ func rewriteValueRISCV64_OpRISCV64SRLI(v *Value) bool { break } v.reset(OpRISCV64SRLIW) - v.Type = t - v.AuxInt = int64ToAuxInt(int64(x)) + v.AuxInt = int64ToAuxInt(x) v.AddArg(y) return true } - // match: (SRLI [x] (MOVBUreg y)) + // match: (SRLI [x] (MOVBUreg y)) // cond: x >= 8 - // result: (MOVDconst [0]) + // result: (MOVDconst [0]) for { - t := v.Type x := auxIntToInt64(v.AuxInt) if v_0.Op != OpRISCV64MOVBUreg { break @@ -7623,15 +8566,13 @@ func rewriteValueRISCV64_OpRISCV64SRLI(v *Value) bool { break } v.reset(OpRISCV64MOVDconst) - v.Type = t v.AuxInt = int64ToAuxInt(0) return true } - // match: (SRLI [x] (MOVHUreg y)) + // match: (SRLI [x] (MOVHUreg y)) // cond: x >= 16 - // result: (MOVDconst [0]) + // result: (MOVDconst [0]) for { - t := v.Type x := auxIntToInt64(v.AuxInt) if v_0.Op != OpRISCV64MOVHUreg { break @@ -7640,15 +8581,13 @@ func rewriteValueRISCV64_OpRISCV64SRLI(v *Value) bool { break } v.reset(OpRISCV64MOVDconst) - v.Type = t v.AuxInt = int64ToAuxInt(0) return true } - // match: (SRLI [x] (MOVWUreg y)) + // match: (SRLI [x] (MOVWUreg y)) // cond: x >= 32 - // result: (MOVDconst [0]) + // result: (MOVDconst [0]) for { - t := v.Type x := auxIntToInt64(v.AuxInt) if v_0.Op != OpRISCV64MOVWUreg { break @@ -7657,7 +8596,6 @@ func rewriteValueRISCV64_OpRISCV64SRLI(v *Value) bool { break } v.reset(OpRISCV64MOVDconst) - v.Type = t v.AuxInt = int64ToAuxInt(0) return true } @@ -7679,7 +8617,7 @@ func rewriteValueRISCV64_OpRISCV64SRLW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SRLW x (MOVDconst [val])) - // result: (SRLIW [int64(val&31)] x) + // result: (SRLIW [val&31] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { @@ -7687,7 +8625,7 @@ func rewriteValueRISCV64_OpRISCV64SRLW(v *Value) bool { } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64SRLIW) - v.AuxInt = int64ToAuxInt(int64(val & 31)) + v.AuxInt = int64ToAuxInt(val & 31) v.AddArg(x) return true } @@ -9832,7 +10770,7 @@ func rewriteValueRISCV64_OpZero(v *Value) bool { } // match: (Zero [s] {t} ptr mem) // cond: s <= 24*moveSize(t.Alignment(), config) - // result: (LoweredZero [makeValAndOff(int32(s),int32(t.Alignment()))] ptr mem) + // result: (LoweredZero [s] {t.Alignment()} ptr mem) for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) @@ -9842,13 +10780,14 @@ func rewriteValueRISCV64_OpZero(v *Value) bool { break } v.reset(OpRISCV64LoweredZero) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(s), int32(t.Alignment()))) + v.AuxInt = int64ToAuxInt(s) + v.Aux = int64ToAux(t.Alignment()) v.AddArg2(ptr, mem) return true } // match: (Zero [s] {t} ptr mem) // cond: s > 24*moveSize(t.Alignment(), config) - // result: (LoweredZeroLoop [makeValAndOff(int32(s),int32(t.Alignment()))] ptr mem) + // result: (LoweredZeroLoop [s] {t.Alignment()} ptr mem) for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) @@ -9858,7 +10797,8 @@ func rewriteValueRISCV64_OpZero(v *Value) bool { break } v.reset(OpRISCV64LoweredZeroLoop) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(s), int32(t.Alignment()))) + v.AuxInt = int64ToAuxInt(s) + v.Aux = int64ToAux(t.Alignment()) v.AddArg2(ptr, mem) return true } @@ -9998,6 +10938,50 @@ func rewriteBlockRISCV64(b *Block) bool { b.resetWithControl2(BlockRISCV64BGEU, y, v0) return true } + // match: (BEQZ (ANDI [c] (FCLASSD (FNEGD x))) yes no) + // result: (BEQZ (ANDI [(c&0b11_0000_0000)|int64(bits.Reverse8(uint8(c))&0b1111_1111)] (FCLASSD x)) yes no) + for b.Controls[0].Op == OpRISCV64ANDI { + v_0 := b.Controls[0] + c := auxIntToInt64(v_0.AuxInt) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64FCLASSD { + break + } + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRISCV64FNEGD { + break + } + x := v_0_0_0.Args[0] + v0 := b.NewValue0(v_0.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt((c & 0b11_0000_0000) | int64(bits.Reverse8(uint8(c))&0b1111_1111)) + v1 := b.NewValue0(v_0.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + b.resetWithControl(BlockRISCV64BEQZ, v0) + return true + } + // match: (BEQZ (ANDI [c] (FCLASSD (FABSD x))) yes no) + // result: (BEQZ (ANDI [(c&0b11_1111_0000)|int64(bits.Reverse8(uint8(c))&0b0000_1111)] (FCLASSD x)) yes no) + for b.Controls[0].Op == OpRISCV64ANDI { + v_0 := b.Controls[0] + c := auxIntToInt64(v_0.AuxInt) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64FCLASSD { + break + } + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRISCV64FABSD { + break + } + x := v_0_0_0.Args[0] + v0 := b.NewValue0(v_0.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt((c & 0b11_1111_0000) | int64(bits.Reverse8(uint8(c))&0b0000_1111)) + v1 := b.NewValue0(v_0.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + b.resetWithControl(BlockRISCV64BEQZ, v0) + return true + } case BlockRISCV64BGE: // match: (BGE (MOVDconst [0]) cond yes no) // result: (BLEZ cond yes no) @@ -10199,6 +11183,50 @@ func rewriteBlockRISCV64(b *Block) bool { b.resetWithControl2(BlockRISCV64BLTU, y, v0) return true } + // match: (BNEZ (ANDI [c] (FCLASSD (FNEGD x))) yes no) + // result: (BNEZ (ANDI [(c&0b11_0000_0000)|int64(bits.Reverse8(uint8(c))&0b1111_1111)] (FCLASSD x)) yes no) + for b.Controls[0].Op == OpRISCV64ANDI { + v_0 := b.Controls[0] + c := auxIntToInt64(v_0.AuxInt) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64FCLASSD { + break + } + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRISCV64FNEGD { + break + } + x := v_0_0_0.Args[0] + v0 := b.NewValue0(v_0.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt((c & 0b11_0000_0000) | int64(bits.Reverse8(uint8(c))&0b1111_1111)) + v1 := b.NewValue0(v_0.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + b.resetWithControl(BlockRISCV64BNEZ, v0) + return true + } + // match: (BNEZ (ANDI [c] (FCLASSD (FABSD x))) yes no) + // result: (BNEZ (ANDI [(c&0b11_1111_0000)|int64(bits.Reverse8(uint8(c))&0b0000_1111)] (FCLASSD x)) yes no) + for b.Controls[0].Op == OpRISCV64ANDI { + v_0 := b.Controls[0] + c := auxIntToInt64(v_0.AuxInt) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpRISCV64FCLASSD { + break + } + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRISCV64FABSD { + break + } + x := v_0_0_0.Args[0] + v0 := b.NewValue0(v_0.Pos, OpRISCV64ANDI, typ.Int64) + v0.AuxInt = int64ToAuxInt((c & 0b11_1111_0000) | int64(bits.Reverse8(uint8(c))&0b0000_1111)) + v1 := b.NewValue0(v_0.Pos, OpRISCV64FCLASSD, typ.Int64) + v1.AddArg(x) + v0.AddArg(v1) + b.resetWithControl(BlockRISCV64BNEZ, v0) + return true + } case BlockIf: // match: (If cond yes no) // result: (BNEZ (MOVBUreg cond) yes no) diff --git a/src/cmd/compile/internal/ssa/rewriteS390X.go b/src/cmd/compile/internal/ssa/rewriteS390X.go index 07dbe7bf7a697c..541cb70b12d767 100644 --- a/src/cmd/compile/internal/ssa/rewriteS390X.go +++ b/src/cmd/compile/internal/ssa/rewriteS390X.go @@ -864,6 +864,9 @@ func rewriteValueS390X(v *Value) bool { case OpTailCall: v.Op = OpS390XCALLtail return true + case OpTailCallInter: + v.Op = OpS390XCALLtailinter + return true case OpTrunc: return rewriteValueS390X_OpTrunc(v) case OpTrunc16to8: diff --git a/src/cmd/compile/internal/ssa/rewriteWasm.go b/src/cmd/compile/internal/ssa/rewriteWasm.go index a164a6eee555b9..eb46c55011f88c 100644 --- a/src/cmd/compile/internal/ssa/rewriteWasm.go +++ b/src/cmd/compile/internal/ssa/rewriteWasm.go @@ -10,6 +10,24 @@ func rewriteValueWasm(v *Value) bool { case OpAbs: v.Op = OpWasmF64Abs return true + case OpAbsFloat32x4: + v.Op = OpWasmF32x4Abs + return true + case OpAbsFloat64x2: + v.Op = OpWasmF64x2Abs + return true + case OpAbsInt16x8: + v.Op = OpWasmI16x8Abs + return true + case OpAbsInt32x4: + v.Op = OpWasmI32x4Abs + return true + case OpAbsInt64x2: + v.Op = OpWasmI64x2Abs + return true + case OpAbsInt8x16: + v.Op = OpWasmI8x16Abs + return true case OpAdd16: v.Op = OpWasmI64Add return true @@ -28,9 +46,39 @@ func rewriteValueWasm(v *Value) bool { case OpAdd8: v.Op = OpWasmI64Add return true + case OpAddFloat32x4: + v.Op = OpWasmF32x4Add + return true + case OpAddFloat64x2: + v.Op = OpWasmF64x2Add + return true + case OpAddInt16x8: + v.Op = OpWasmI16x8Add + return true + case OpAddInt32x4: + v.Op = OpWasmI32x4Add + return true + case OpAddInt64x2: + v.Op = OpWasmI64x2Add + return true + case OpAddInt8x16: + v.Op = OpWasmI8x16Add + return true case OpAddPtr: v.Op = OpWasmI64Add return true + case OpAddSaturatedInt16x8: + v.Op = OpWasmI16x8AddSatS + return true + case OpAddSaturatedInt8x16: + v.Op = OpWasmI8x16AddSatS + return true + case OpAddSaturatedUint16x8: + v.Op = OpWasmI16x8AddSatU + return true + case OpAddSaturatedUint8x16: + v.Op = OpWasmI8x16AddSatU + return true case OpAddr: return rewriteValueWasm_OpAddr(v) case OpAnd16: @@ -48,6 +96,62 @@ func rewriteValueWasm(v *Value) bool { case OpAndB: v.Op = OpWasmI64And return true + case OpAndInt16x8: + v.Op = OpWasmV128And + return true + case OpAndInt32x4: + v.Op = OpWasmV128And + return true + case OpAndInt64x2: + v.Op = OpWasmV128And + return true + case OpAndInt8x16: + v.Op = OpWasmV128And + return true + case OpAndNotInt16x8: + v.Op = OpWasmV128Andnot + return true + case OpAndNotInt32x4: + v.Op = OpWasmV128Andnot + return true + case OpAndNotInt64x2: + v.Op = OpWasmV128Andnot + return true + case OpAndNotInt8x16: + v.Op = OpWasmV128Andnot + return true + case OpAndNotUint16x8: + v.Op = OpWasmV128Andnot + return true + case OpAndNotUint32x4: + v.Op = OpWasmV128Andnot + return true + case OpAndNotUint64x2: + v.Op = OpWasmV128Andnot + return true + case OpAndNotUint8x16: + v.Op = OpWasmV128Andnot + return true + case OpAndUint16x8: + v.Op = OpWasmV128And + return true + case OpAndUint32x4: + v.Op = OpWasmV128And + return true + case OpAndUint64x2: + v.Op = OpWasmV128And + return true + case OpAndUint8x16: + v.Op = OpWasmV128And + return true + case OpAverageUint16x8: + v.Op = OpWasmI16x8AvgrU + return true + case OpAverageUint8x16: + v.Op = OpWasmI8x16AvgrU + return true + case OpAvg64u: + return rewriteValueWasm_OpAvg64u(v) case OpBitLen16: return rewriteValueWasm_OpBitLen16(v) case OpBitLen32: @@ -56,9 +160,57 @@ func rewriteValueWasm(v *Value) bool { return rewriteValueWasm_OpBitLen64(v) case OpBitLen8: return rewriteValueWasm_OpBitLen8(v) + case OpBitSelectInt16x8: + v.Op = OpWasmV128Bitselect + return true + case OpBitSelectInt32x4: + v.Op = OpWasmV128Bitselect + return true + case OpBitSelectInt64x2: + v.Op = OpWasmV128Bitselect + return true + case OpBitSelectInt8x16: + v.Op = OpWasmV128Bitselect + return true + case OpBitSelectUint16x8: + v.Op = OpWasmV128Bitselect + return true + case OpBitSelectUint32x4: + v.Op = OpWasmV128Bitselect + return true + case OpBitSelectUint64x2: + v.Op = OpWasmV128Bitselect + return true + case OpBitSelectUint8x16: + v.Op = OpWasmV128Bitselect + return true + case OpBroadcastFloat32x4: + v.Op = OpWasmF32x4Splat + return true + case OpBroadcastFloat64x2: + v.Op = OpWasmF64x2Splat + return true + case OpBroadcastInt16x8: + v.Op = OpWasmI16x8Splat + return true + case OpBroadcastInt32x4: + v.Op = OpWasmI32x4Splat + return true + case OpBroadcastInt64x2: + v.Op = OpWasmI64x2Splat + return true + case OpBroadcastInt8x16: + v.Op = OpWasmI8x16Splat + return true case OpCeil: v.Op = OpWasmF64Ceil return true + case OpCeilFloat32x4: + v.Op = OpWasmF32x4Ceil + return true + case OpCeilFloat64x2: + v.Op = OpWasmF64x2Ceil + return true case OpClosureCall: v.Op = OpWasmLoweredClosureCall return true @@ -95,6 +247,24 @@ func rewriteValueWasm(v *Value) bool { case OpConvert: v.Op = OpWasmLoweredConvert return true + case OpConvertLo2ToFloat64Int32x4: + v.Op = OpWasmF64x2ConvertLowI32x4S + return true + case OpConvertLo2ToFloat64Uint32x4: + v.Op = OpWasmF64x2ConvertLowI32x4U + return true + case OpConvertToFloat32Int32x4: + v.Op = OpWasmF32x4ConvertI32x4S + return true + case OpConvertToFloat32Uint32x4: + v.Op = OpWasmF32x4ConvertI32x4U + return true + case OpConvertToInt32Float32x4: + v.Op = OpWasmI32x4TruncSatF32x4S + return true + case OpConvertToUint32Float32x4: + v.Op = OpWasmI32x4TruncSatF32x4U + return true case OpCopysign: v.Op = OpWasmF64Copysign return true @@ -195,6 +365,12 @@ func rewriteValueWasm(v *Value) bool { return rewriteValueWasm_OpDiv8(v) case OpDiv8u: return rewriteValueWasm_OpDiv8u(v) + case OpDivFloat32x4: + v.Op = OpWasmF32x4Div + return true + case OpDivFloat64x2: + v.Op = OpWasmF64x2Div + return true case OpEq16: return rewriteValueWasm_OpEq16(v) case OpEq32: @@ -216,9 +392,81 @@ func rewriteValueWasm(v *Value) bool { case OpEqPtr: v.Op = OpWasmI64Eq return true + case OpEqualFloat32x4: + v.Op = OpWasmF32x4Eq + return true + case OpEqualFloat64x2: + v.Op = OpWasmF64x2Eq + return true + case OpEqualInt16x8: + v.Op = OpWasmI16x8Eq + return true + case OpEqualInt32x4: + v.Op = OpWasmI32x4Eq + return true + case OpEqualInt64x2: + v.Op = OpWasmI64x2Eq + return true + case OpEqualInt8x16: + v.Op = OpWasmI8x16Eq + return true + case OpEqualUint16x8: + v.Op = OpWasmI16x8Eq + return true + case OpEqualUint32x4: + v.Op = OpWasmI32x4Eq + return true + case OpEqualUint64x2: + v.Op = OpWasmI64x2Eq + return true + case OpEqualUint8x16: + v.Op = OpWasmI8x16Eq + return true + case OpExtendHi2ToInt64Int32x4: + v.Op = OpWasmI64x2ExtendHighI32x4S + return true + case OpExtendHi2ToUint64Uint32x4: + v.Op = OpWasmI64x2ExtendHighI32x4U + return true + case OpExtendHi4ToInt32Int16x8: + v.Op = OpWasmI32x4ExtendHighI16x8S + return true + case OpExtendHi4ToUint32Uint16x8: + v.Op = OpWasmI32x4ExtendHighI16x8U + return true + case OpExtendHi8ToInt16Int8x16: + v.Op = OpWasmI16x8ExtendHighI8x16S + return true + case OpExtendHi8ToUint16Uint8x16: + v.Op = OpWasmI16x8ExtendHighI8x16U + return true + case OpExtendLo2ToInt64Int32x4: + v.Op = OpWasmI64x2ExtendLowI32x4S + return true + case OpExtendLo2ToUint64Uint32x4: + v.Op = OpWasmI64x2ExtendLowI32x4U + return true + case OpExtendLo4ToInt32Int16x8: + v.Op = OpWasmI32x4ExtendLowI16x8S + return true + case OpExtendLo4ToUint32Uint16x8: + v.Op = OpWasmI32x4ExtendLowI16x8U + return true + case OpExtendLo8ToInt16Int8x16: + v.Op = OpWasmI16x8ExtendLowI8x16S + return true + case OpExtendLo8ToUint16Uint8x16: + v.Op = OpWasmI16x8ExtendLowI8x16U + return true case OpFloor: v.Op = OpWasmF64Floor return true + case OpFloorFloat32x4: + v.Op = OpWasmF32x4Floor + return true + case OpFloorFloat64x2: + v.Op = OpWasmF64x2Floor + return true case OpGetCallerPC: v.Op = OpWasmLoweredGetCallerPC return true @@ -228,6 +476,94 @@ func rewriteValueWasm(v *Value) bool { case OpGetClosurePtr: v.Op = OpWasmLoweredGetClosurePtr return true + case OpGetElemFloat32x4: + v.Op = OpWasmF32x4ExtractLane + return true + case OpGetElemFloat64x2: + v.Op = OpWasmF64x2ExtractLane + return true + case OpGetElemInt16x8: + v.Op = OpWasmI16x8ExtractLaneS + return true + case OpGetElemInt32x4: + v.Op = OpWasmI32x4ExtractLane + return true + case OpGetElemInt64x2: + v.Op = OpWasmI64x2ExtractLane + return true + case OpGetElemInt8x16: + v.Op = OpWasmI8x16ExtractLaneS + return true + case OpGetElemUint16x8: + v.Op = OpWasmI16x8ExtractLaneU + return true + case OpGetElemUint32x4: + v.Op = OpWasmI32x4ExtractLane + return true + case OpGetElemUint64x2: + v.Op = OpWasmI64x2ExtractLane + return true + case OpGetElemUint8x16: + v.Op = OpWasmI8x16ExtractLaneU + return true + case OpGreaterEqualFloat32x4: + v.Op = OpWasmF32x4Ge + return true + case OpGreaterEqualFloat64x2: + v.Op = OpWasmF64x2Ge + return true + case OpGreaterEqualInt16x8: + v.Op = OpWasmI16x8GeS + return true + case OpGreaterEqualInt32x4: + v.Op = OpWasmI32x4GeS + return true + case OpGreaterEqualInt64x2: + v.Op = OpWasmI64x2GeS + return true + case OpGreaterEqualInt8x16: + v.Op = OpWasmI8x16GeS + return true + case OpGreaterEqualUint16x8: + v.Op = OpWasmI16x8GeU + return true + case OpGreaterEqualUint32x4: + v.Op = OpWasmI32x4GeU + return true + case OpGreaterEqualUint8x16: + v.Op = OpWasmI8x16GeU + return true + case OpGreaterFloat32x4: + v.Op = OpWasmF32x4Gt + return true + case OpGreaterFloat64x2: + v.Op = OpWasmF64x2Gt + return true + case OpGreaterInt16x8: + v.Op = OpWasmI16x8GtS + return true + case OpGreaterInt32x4: + v.Op = OpWasmI32x4GtS + return true + case OpGreaterInt64x2: + v.Op = OpWasmI64x2GtS + return true + case OpGreaterInt8x16: + v.Op = OpWasmI8x16GtS + return true + case OpGreaterUint16x8: + v.Op = OpWasmI16x8GtU + return true + case OpGreaterUint32x4: + v.Op = OpWasmI32x4GtU + return true + case OpGreaterUint8x16: + v.Op = OpWasmI8x16GtU + return true + case OpHmul64: + return rewriteValueWasm_OpHmul64(v) + case OpHmul64u: + return rewriteValueWasm_OpHmul64u(v) case OpInterCall: v.Op = OpWasmLoweredInterCall return true @@ -239,6 +575,8 @@ func rewriteValueWasm(v *Value) bool { case OpIsSliceInBounds: v.Op = OpWasmI64LeU return true + case OpLast: + return rewriteValueWasm_OpLast(v) case OpLeq16: return rewriteValueWasm_OpLeq16(v) case OpLeq16U: @@ -287,10 +625,67 @@ func rewriteValueWasm(v *Value) bool { return rewriteValueWasm_OpLess8(v) case OpLess8U: return rewriteValueWasm_OpLess8U(v) + case OpLessEqualFloat32x4: + v.Op = OpWasmF32x4Le + return true + case OpLessEqualFloat64x2: + v.Op = OpWasmF64x2Le + return true + case OpLessEqualInt16x8: + v.Op = OpWasmI16x8LeS + return true + case OpLessEqualInt32x4: + v.Op = OpWasmI32x4LeS + return true + case OpLessEqualInt64x2: + v.Op = OpWasmI64x2LeS + return true + case OpLessEqualInt8x16: + v.Op = OpWasmI8x16LeS + return true + case OpLessEqualUint16x8: + v.Op = OpWasmI16x8LeU + return true + case OpLessEqualUint32x4: + v.Op = OpWasmI32x4LeU + return true + case OpLessEqualUint8x16: + v.Op = OpWasmI8x16LeU + return true + case OpLessFloat32x4: + v.Op = OpWasmF32x4Lt + return true + case OpLessFloat64x2: + v.Op = OpWasmF64x2Lt + return true + case OpLessInt16x8: + v.Op = OpWasmI16x8LtS + return true + case OpLessInt32x4: + v.Op = OpWasmI32x4LtS + return true + case OpLessInt64x2: + v.Op = OpWasmI64x2LtS + return true + case OpLessInt8x16: + v.Op = OpWasmI8x16LtS + return true + case OpLessUint16x8: + v.Op = OpWasmI16x8LtU + return true + case OpLessUint32x4: + v.Op = OpWasmI32x4LtU + return true + case OpLessUint8x16: + v.Op = OpWasmI8x16LtU + return true case OpLoad: return rewriteValueWasm_OpLoad(v) case OpLocalAddr: return rewriteValueWasm_OpLocalAddr(v) + case OpLookupOrZeroInt8x16: + v.Op = OpWasmI8x16Swizzle + return true case OpLsh16x16: return rewriteValueWasm_OpLsh16x16(v) case OpLsh16x32: @@ -326,6 +721,54 @@ func rewriteValueWasm(v *Value) bool { return true case OpLsh8x8: return rewriteValueWasm_OpLsh8x8(v) + case OpMaxFloat32x4: + v.Op = OpWasmF32x4Max + return true + case OpMaxFloat64x2: + v.Op = OpWasmF64x2Max + return true + case OpMaxInt16x8: + v.Op = OpWasmI16x8MaxS + return true + case OpMaxInt32x4: + v.Op = OpWasmI32x4MaxS + return true + case OpMaxInt8x16: + v.Op = OpWasmI8x16MaxS + return true + case OpMaxUint16x8: + v.Op = OpWasmI16x8MaxU + return true + case OpMaxUint32x4: + v.Op = OpWasmI32x4MaxU + return true + case OpMaxUint8x16: + v.Op = OpWasmI8x16MaxU + return true + case OpMinFloat32x4: + v.Op = OpWasmF32x4Min + return true + case OpMinFloat64x2: + v.Op = OpWasmF64x2Min + return true + case OpMinInt16x8: + v.Op = OpWasmI16x8MinS + return true + case OpMinInt32x4: + v.Op = OpWasmI32x4MinS + return true + case OpMinInt8x16: + v.Op = OpWasmI8x16MinS + return true + case OpMinUint16x8: + v.Op = OpWasmI16x8MinU + return true + case OpMinUint32x4: + v.Op = OpWasmI32x4MinU + return true + case OpMinUint8x16: + v.Op = OpWasmI8x16MinU + return true case OpMod16: return rewriteValueWasm_OpMod16(v) case OpMod16u: @@ -363,6 +806,66 @@ func rewriteValueWasm(v *Value) bool { case OpMul8: v.Op = OpWasmI64Mul return true + case OpMulFloat32x4: + v.Op = OpWasmF32x4Mul + return true + case OpMulFloat64x2: + v.Op = OpWasmF64x2Mul + return true + case OpMulInt16x8: + v.Op = OpWasmI16x8Mul + return true + case OpMulInt32x4: + v.Op = OpWasmI32x4Mul + return true + case OpMulInt64x2: + v.Op = OpWasmI64x2Mul + return true + case OpMulUint16x8: + v.Op = OpWasmI16x8Mul + return true + case OpMulUint32x4: + v.Op = OpWasmI32x4Mul + return true + case OpMulUint64x2: + v.Op = OpWasmI64x2Mul + return true + case OpMulWidenHiInt16x8: + v.Op = OpWasmI32x4ExtmulHighI16x8S + return true + case OpMulWidenHiInt32x4: + v.Op = OpWasmI64x2ExtmulHighI32x4S + return true + case OpMulWidenHiInt8x16: + v.Op = OpWasmI16x8ExtmulHighI8x16S + return true + case OpMulWidenHiUint16x8: + v.Op = OpWasmI32x4ExtmulHighI16x8U + return true + case OpMulWidenHiUint32x4: + v.Op = OpWasmI64x2ExtmulHighI32x4U + return true + case OpMulWidenHiUint8x16: + v.Op = OpWasmI16x8ExtmulHighI8x16U + return true + case OpMulWidenLoInt16x8: + v.Op = OpWasmI32x4ExtmulLowI16x8S + return true + case OpMulWidenLoInt32x4: + v.Op = OpWasmI64x2ExtmulLowI32x4S + return true + case OpMulWidenLoInt8x16: + v.Op = OpWasmI16x8ExtmulLowI8x16S + return true + case OpMulWidenLoUint16x8: + v.Op = OpWasmI32x4ExtmulLowI16x8U + return true + case OpMulWidenLoUint32x4: + v.Op = OpWasmI64x2ExtmulLowI32x4U + return true + case OpMulWidenLoUint8x16: + v.Op = OpWasmI16x8ExtmulLowI8x16U + return true case OpNeg16: return rewriteValueWasm_OpNeg16(v) case OpNeg32: @@ -377,6 +880,24 @@ func rewriteValueWasm(v *Value) bool { return true case OpNeg8: return rewriteValueWasm_OpNeg8(v) + case OpNegFloat32x4: + v.Op = OpWasmF32x4Neg + return true + case OpNegFloat64x2: + v.Op = OpWasmF64x2Neg + return true + case OpNegInt16x8: + v.Op = OpWasmI16x8Neg + return true + case OpNegInt32x4: + v.Op = OpWasmI32x4Neg + return true + case OpNegInt64x2: + v.Op = OpWasmI64x2Neg + return true + case OpNegInt8x16: + v.Op = OpWasmI8x16Neg + return true case OpNeq16: return rewriteValueWasm_OpNeq16(v) case OpNeq32: @@ -404,9 +925,66 @@ func rewriteValueWasm(v *Value) bool { case OpNot: v.Op = OpWasmI64Eqz return true + case OpNotEqualFloat32x4: + v.Op = OpWasmF32x4Ne + return true + case OpNotEqualFloat64x2: + v.Op = OpWasmF64x2Ne + return true + case OpNotEqualInt16x8: + v.Op = OpWasmI16x8Ne + return true + case OpNotEqualInt32x4: + v.Op = OpWasmI32x4Ne + return true + case OpNotEqualInt64x2: + v.Op = OpWasmI64x2Ne + return true + case OpNotEqualInt8x16: + v.Op = OpWasmI8x16Ne + return true + case OpNotEqualUint16x8: + v.Op = OpWasmI16x8Ne + return true + case OpNotEqualUint32x4: + v.Op = OpWasmI32x4Ne + return true + case OpNotEqualUint64x2: + v.Op = OpWasmI64x2Ne + return true + case OpNotEqualUint8x16: + v.Op = OpWasmI8x16Ne + return true + case OpNotInt16x8: + v.Op = OpWasmV128Not + return true + case OpNotInt32x4: + v.Op = OpWasmV128Not + return true + case OpNotInt64x2: + v.Op = OpWasmV128Not + return true + case OpNotInt8x16: + v.Op = OpWasmV128Not + return true + case OpNotUint16x8: + v.Op = OpWasmV128Not + return true + case OpNotUint32x4: + v.Op = OpWasmV128Not + return true + case OpNotUint64x2: + v.Op = OpWasmV128Not + return true + case OpNotUint8x16: + v.Op = OpWasmV128Not + return true case OpOffPtr: v.Op = OpWasmI64AddConst return true + case OpOnesCountInt8x16: + v.Op = OpWasmI8x16Popcnt + return true case OpOr16: v.Op = OpWasmI64Or return true @@ -422,6 +1000,30 @@ func rewriteValueWasm(v *Value) bool { case OpOrB: v.Op = OpWasmI64Or return true + case OpOrInt16x8: + v.Op = OpWasmV128Or + return true + case OpOrInt32x4: + v.Op = OpWasmV128Or + return true + case OpOrInt64x2: + v.Op = OpWasmV128Or + return true + case OpOrInt8x16: + v.Op = OpWasmV128Or + return true + case OpOrUint16x8: + v.Op = OpWasmV128Or + return true + case OpOrUint32x4: + v.Op = OpWasmV128Or + return true + case OpOrUint64x2: + v.Op = OpWasmV128Or + return true + case OpOrUint8x16: + v.Op = OpWasmV128Or + return true case OpPopCount16: return rewriteValueWasm_OpPopCount16(v) case OpPopCount32: @@ -431,6 +1033,38 @@ func rewriteValueWasm(v *Value) bool { return true case OpPopCount8: return rewriteValueWasm_OpPopCount8(v) + case OpRotateAllLeftVarInt16x8: + return rewriteValueWasm_OpRotateAllLeftVarInt16x8(v) + case OpRotateAllLeftVarInt32x4: + return rewriteValueWasm_OpRotateAllLeftVarInt32x4(v) + case OpRotateAllLeftVarInt64x2: + return rewriteValueWasm_OpRotateAllLeftVarInt64x2(v) + case OpRotateAllLeftVarInt8x16: + return rewriteValueWasm_OpRotateAllLeftVarInt8x16(v) + case OpRotateAllLeftVarUint16x8: + return rewriteValueWasm_OpRotateAllLeftVarUint16x8(v) + case OpRotateAllLeftVarUint32x4: + return rewriteValueWasm_OpRotateAllLeftVarUint32x4(v) + case OpRotateAllLeftVarUint64x2: + return rewriteValueWasm_OpRotateAllLeftVarUint64x2(v) + case OpRotateAllLeftVarUint8x16: + return rewriteValueWasm_OpRotateAllLeftVarUint8x16(v) + case OpRotateAllRightVarInt16x8: + return rewriteValueWasm_OpRotateAllRightVarInt16x8(v) + case OpRotateAllRightVarInt32x4: + return rewriteValueWasm_OpRotateAllRightVarInt32x4(v) + case OpRotateAllRightVarInt64x2: + return rewriteValueWasm_OpRotateAllRightVarInt64x2(v) + case OpRotateAllRightVarInt8x16: + return rewriteValueWasm_OpRotateAllRightVarInt8x16(v) + case OpRotateAllRightVarUint16x8: + return rewriteValueWasm_OpRotateAllRightVarUint16x8(v) + case OpRotateAllRightVarUint32x4: + return rewriteValueWasm_OpRotateAllRightVarUint32x4(v) + case OpRotateAllRightVarUint64x2: + return rewriteValueWasm_OpRotateAllRightVarUint64x2(v) + case OpRotateAllRightVarUint8x16: + return rewriteValueWasm_OpRotateAllRightVarUint8x16(v) case OpRotateLeft16: return rewriteValueWasm_OpRotateLeft16(v) case OpRotateLeft32: @@ -447,6 +1081,12 @@ func rewriteValueWasm(v *Value) bool { case OpRound64F: v.Op = OpCopy return true + case OpRoundFloat32x4: + v.Op = OpWasmF32x4Nearest + return true + case OpRoundFloat64x2: + v.Op = OpWasmF64x2Nearest + return true case OpRoundToEven: v.Op = OpWasmF64Nearest return true @@ -514,6 +1154,72 @@ func rewriteValueWasm(v *Value) bool { return rewriteValueWasm_OpRsh8x64(v) case OpRsh8x8: return rewriteValueWasm_OpRsh8x8(v) + case OpSelect0: + return rewriteValueWasm_OpSelect0(v) + case OpSelect1: + return rewriteValueWasm_OpSelect1(v) + case OpSetElemFloat32x4: + v.Op = OpWasmF32x4ReplaceLane + return true + case OpSetElemFloat64x2: + v.Op = OpWasmF64x2ReplaceLane + return true + case OpSetElemInt16x8: + v.Op = OpWasmI16x8ReplaceLane + return true + case OpSetElemInt32x4: + v.Op = OpWasmI32x4ReplaceLane + return true + case OpSetElemInt64x2: + v.Op = OpWasmI64x2ReplaceLane + return true + case OpSetElemInt8x16: + v.Op = OpWasmI8x16ReplaceLane + return true + case OpSetElemUint16x8: + v.Op = OpWasmI16x8ReplaceLane + return true + case OpSetElemUint32x4: + v.Op = OpWasmI32x4ReplaceLane + return true + case OpSetElemUint64x2: + v.Op = OpWasmI64x2ReplaceLane + return true + case OpSetElemUint8x16: + v.Op = OpWasmI8x16ReplaceLane + return true + case OpShiftAllLeftInt16x8: + return rewriteValueWasm_OpShiftAllLeftInt16x8(v) + case OpShiftAllLeftInt32x4: + return rewriteValueWasm_OpShiftAllLeftInt32x4(v) + case OpShiftAllLeftInt64x2: + return rewriteValueWasm_OpShiftAllLeftInt64x2(v) + case OpShiftAllLeftInt8x16: + return rewriteValueWasm_OpShiftAllLeftInt8x16(v) + case OpShiftAllLeftUint16x8: + return rewriteValueWasm_OpShiftAllLeftUint16x8(v) + case OpShiftAllLeftUint32x4: + return rewriteValueWasm_OpShiftAllLeftUint32x4(v) + case OpShiftAllLeftUint64x2: + return rewriteValueWasm_OpShiftAllLeftUint64x2(v) + case OpShiftAllLeftUint8x16: + return rewriteValueWasm_OpShiftAllLeftUint8x16(v) + case OpShiftAllRightInt16x8: + return rewriteValueWasm_OpShiftAllRightInt16x8(v) + case OpShiftAllRightInt32x4: + return rewriteValueWasm_OpShiftAllRightInt32x4(v) + case OpShiftAllRightInt64x2: + return rewriteValueWasm_OpShiftAllRightInt64x2(v) + case OpShiftAllRightInt8x16: + return rewriteValueWasm_OpShiftAllRightInt8x16(v) + case OpShiftAllRightUint16x8: + return rewriteValueWasm_OpShiftAllRightUint16x8(v) + case OpShiftAllRightUint32x4: + return rewriteValueWasm_OpShiftAllRightUint32x4(v) + case OpShiftAllRightUint64x2: + return rewriteValueWasm_OpShiftAllRightUint64x2(v) + case OpShiftAllRightUint8x16: + return rewriteValueWasm_OpShiftAllRightUint8x16(v) case OpSignExt16to32: return rewriteValueWasm_OpSignExt16to32(v) case OpSignExt16to64: @@ -534,6 +1240,12 @@ func rewriteValueWasm(v *Value) bool { case OpSqrt32: v.Op = OpWasmF32Sqrt return true + case OpSqrtFloat32x4: + v.Op = OpWasmF32x4Sqrt + return true + case OpSqrtFloat64x2: + v.Op = OpWasmF64x2Sqrt + return true case OpStaticCall: v.Op = OpWasmLoweredStaticCall return true @@ -557,12 +1269,45 @@ func rewriteValueWasm(v *Value) bool { case OpSub8: v.Op = OpWasmI64Sub return true + case OpSubFloat32x4: + v.Op = OpWasmF32x4Sub + return true + case OpSubFloat64x2: + v.Op = OpWasmF64x2Sub + return true + case OpSubInt16x8: + v.Op = OpWasmI16x8Sub + return true + case OpSubInt32x4: + v.Op = OpWasmI32x4Sub + return true + case OpSubInt64x2: + v.Op = OpWasmI64x2Sub + return true + case OpSubInt8x16: + v.Op = OpWasmI8x16Sub + return true case OpSubPtr: v.Op = OpWasmI64Sub return true + case OpSubSaturatedInt16x8: + v.Op = OpWasmI16x8SubSatS + return true + case OpSubSaturatedInt8x16: + v.Op = OpWasmI8x16SubSatS + return true + case OpSubSaturatedUint16x8: + v.Op = OpWasmI16x8SubSatU + return true + case OpSubSaturatedUint8x16: + v.Op = OpWasmI8x16SubSatU + return true case OpTailCall: v.Op = OpWasmLoweredTailCall return true + case OpTailCallInter: + v.Op = OpWasmLoweredTailCallInter + return true case OpTrunc: v.Op = OpWasmF64Trunc return true @@ -584,9 +1329,17 @@ func rewriteValueWasm(v *Value) bool { case OpTrunc64to8: v.Op = OpCopy return true + case OpTruncFloat32x4: + v.Op = OpWasmF32x4Trunc + return true + case OpTruncFloat64x2: + v.Op = OpWasmF64x2Trunc + return true case OpWB: v.Op = OpWasmLoweredWB return true + case OpWasmF32DemoteF64: + return rewriteValueWasm_OpWasmF32DemoteF64(v) case OpWasmF64Add: return rewriteValueWasm_OpWasmF64Add(v) case OpWasmF64Mul: @@ -601,6 +1354,12 @@ func rewriteValueWasm(v *Value) bool { return rewriteValueWasm_OpWasmI64Eq(v) case OpWasmI64Eqz: return rewriteValueWasm_OpWasmI64Eqz(v) + case OpWasmI64Extend16S: + return rewriteValueWasm_OpWasmI64Extend16S(v) + case OpWasmI64Extend32S: + return rewriteValueWasm_OpWasmI64Extend32S(v) + case OpWasmI64Extend8S: + return rewriteValueWasm_OpWasmI64Extend8S(v) case OpWasmI64LeU: return rewriteValueWasm_OpWasmI64LeU(v) case OpWasmI64Load: @@ -639,6 +1398,8 @@ func rewriteValueWasm(v *Value) bool { return rewriteValueWasm_OpWasmI64Store32(v) case OpWasmI64Store8: return rewriteValueWasm_OpWasmI64Store8(v) + case OpWasmI64Sub: + return rewriteValueWasm_OpWasmI64Sub(v) case OpWasmI64Xor: return rewriteValueWasm_OpWasmI64Xor(v) case OpXor16: @@ -653,6 +1414,30 @@ func rewriteValueWasm(v *Value) bool { case OpXor8: v.Op = OpWasmI64Xor return true + case OpXorInt16x8: + v.Op = OpWasmV128Xor + return true + case OpXorInt32x4: + v.Op = OpWasmV128Xor + return true + case OpXorInt64x2: + v.Op = OpWasmV128Xor + return true + case OpXorInt8x16: + v.Op = OpWasmV128Xor + return true + case OpXorUint16x8: + v.Op = OpWasmV128Xor + return true + case OpXorUint32x4: + v.Op = OpWasmV128Xor + return true + case OpXorUint64x2: + v.Op = OpWasmV128Xor + return true + case OpXorUint8x16: + v.Op = OpWasmV128Xor + return true case OpZero: return rewriteValueWasm_OpZero(v) case OpZeroExt16to32: @@ -667,6 +1452,8 @@ func rewriteValueWasm(v *Value) bool { return rewriteValueWasm_OpZeroExt8to32(v) case OpZeroExt8to64: return rewriteValueWasm_OpZeroExt8to64(v) + case OpZeroSIMD: + return rewriteValueWasm_OpZeroSIMD(v) } return false } @@ -684,6 +1471,27 @@ func rewriteValueWasm_OpAddr(v *Value) bool { return true } } +func rewriteValueWasm_OpAvg64u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Avg64u x y) + // result: (I64Add (I64ShrU (I64Sub x y) (I64Const [1])) y) + for { + x := v_0 + y := v_1 + v.reset(OpWasmI64Add) + v0 := b.NewValue0(v.Pos, OpWasmI64ShrU, typ.Int64) + v1 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v1.AddArg2(x, y) + v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v2.AuxInt = int64ToAuxInt(1) + v0.AddArg2(v1, v2) + v.AddArg2(v0, y) + return true + } +} func rewriteValueWasm_OpBitLen16(v *Value) bool { v_0 := v.Args[0] b := v.Block @@ -1162,28 +1970,138 @@ func rewriteValueWasm_OpEq8(v *Value) bool { return true } } -func rewriteValueWasm_OpIsNonNil(v *Value) bool { +func rewriteValueWasm_OpHmul64(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (IsNonNil p) - // result: (I64Eqz (I64Eqz p)) + // match: (Hmul64 x y) + // result: (Last x0: (ZeroExt32to64 x) x1: (I64ShrS x (I64Const [32])) y0: (ZeroExt32to64 y) y1: (I64ShrS y (I64Const [32])) x0y0: (I64Mul x0 y0) tt: (I64Add (I64Mul x1 y0) (I64ShrU x0y0 (I64Const [32]))) w1: (I64Add (I64Mul x0 y1) (ZeroExt32to64 tt)) w2: (I64ShrS tt (I64Const [32])) (I64Add (I64Add (I64Mul x1 y1) w2) (I64ShrS w1 (I64Const [32])))) for { - p := v_0 - v.reset(OpWasmI64Eqz) - v0 := b.NewValue0(v.Pos, OpWasmI64Eqz, typ.Bool) - v0.AddArg(p) - v.AddArg(v0) - return true - } -} -func rewriteValueWasm_OpLeq16(v *Value) bool { + t := v.Type + x := v_0 + y := v_1 + v.reset(OpLast) + v.Type = t + x0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) + x0.AddArg(x) + x1 := b.NewValue0(v.Pos, OpWasmI64ShrS, typ.Int64) + v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v2.AuxInt = int64ToAuxInt(32) + x1.AddArg2(x, v2) + y0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) + y0.AddArg(y) + y1 := b.NewValue0(v.Pos, OpWasmI64ShrS, typ.Int64) + y1.AddArg2(y, v2) + x0y0 := b.NewValue0(v.Pos, OpWasmI64Mul, typ.Int64) + x0y0.AddArg2(x0, y0) + tt := b.NewValue0(v.Pos, OpWasmI64Add, typ.Int64) + v7 := b.NewValue0(v.Pos, OpWasmI64Mul, typ.Int64) + v7.AddArg2(x1, y0) + v8 := b.NewValue0(v.Pos, OpWasmI64ShrU, typ.Int64) + v8.AddArg2(x0y0, v2) + tt.AddArg2(v7, v8) + w1 := b.NewValue0(v.Pos, OpWasmI64Add, typ.Int64) + v10 := b.NewValue0(v.Pos, OpWasmI64Mul, typ.Int64) + v10.AddArg2(x0, y1) + v11 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) + v11.AddArg(tt) + w1.AddArg2(v10, v11) + w2 := b.NewValue0(v.Pos, OpWasmI64ShrS, typ.Int64) + w2.AddArg2(tt, v2) + v13 := b.NewValue0(v.Pos, OpWasmI64Add, typ.Int64) + v14 := b.NewValue0(v.Pos, OpWasmI64Add, typ.Int64) + v15 := b.NewValue0(v.Pos, OpWasmI64Mul, typ.Int64) + v15.AddArg2(x1, y1) + v14.AddArg2(v15, w2) + v16 := b.NewValue0(v.Pos, OpWasmI64ShrS, typ.Int64) + v16.AddArg2(w1, v2) + v13.AddArg2(v14, v16) + v.AddArgs(x0, x1, y0, y1, x0y0, tt, w1, w2, v13) + return true + } +} +func rewriteValueWasm_OpHmul64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Leq16 x y) - // result: (I64LeS (SignExt16to64 x) (SignExt16to64 y)) + // match: (Hmul64u x y) + // result: (Last x0: (ZeroExt32to64 x) x1: (I64ShrU x (I64Const [32])) y0: (ZeroExt32to64 y) y1: (I64ShrU y (I64Const [32])) w0: (I64Mul x0 y0) tt: (I64Add (I64Mul x1 y0) (I64ShrU w0 (I64Const [32]))) w1: (I64Add (I64Mul x0 y1) (ZeroExt32to64 tt)) w2: (I64ShrU tt (I64Const [32])) hi: (I64Add (I64Add (I64Mul x1 y1) w2) (I64ShrU w1 (I64Const [32])))) + for { + t := v.Type + x := v_0 + y := v_1 + v.reset(OpLast) + v.Type = t + x0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) + x0.AddArg(x) + x1 := b.NewValue0(v.Pos, OpWasmI64ShrU, typ.Int64) + v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v2.AuxInt = int64ToAuxInt(32) + x1.AddArg2(x, v2) + y0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) + y0.AddArg(y) + y1 := b.NewValue0(v.Pos, OpWasmI64ShrU, typ.Int64) + y1.AddArg2(y, v2) + w0 := b.NewValue0(v.Pos, OpWasmI64Mul, typ.Int64) + w0.AddArg2(x0, y0) + tt := b.NewValue0(v.Pos, OpWasmI64Add, typ.Int64) + v7 := b.NewValue0(v.Pos, OpWasmI64Mul, typ.Int64) + v7.AddArg2(x1, y0) + v8 := b.NewValue0(v.Pos, OpWasmI64ShrU, typ.Int64) + v8.AddArg2(w0, v2) + tt.AddArg2(v7, v8) + w1 := b.NewValue0(v.Pos, OpWasmI64Add, typ.Int64) + v10 := b.NewValue0(v.Pos, OpWasmI64Mul, typ.Int64) + v10.AddArg2(x0, y1) + v11 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) + v11.AddArg(tt) + w1.AddArg2(v10, v11) + w2 := b.NewValue0(v.Pos, OpWasmI64ShrU, typ.Int64) + w2.AddArg2(tt, v2) + hi := b.NewValue0(v.Pos, OpWasmI64Add, typ.Int64) + v14 := b.NewValue0(v.Pos, OpWasmI64Add, typ.Int64) + v15 := b.NewValue0(v.Pos, OpWasmI64Mul, typ.Int64) + v15.AddArg2(x1, y1) + v14.AddArg2(v15, w2) + v16 := b.NewValue0(v.Pos, OpWasmI64ShrU, typ.Int64) + v16.AddArg2(w1, v2) + hi.AddArg2(v14, v16) + v.AddArgs(x0, x1, y0, y1, w0, tt, w1, w2, hi) + return true + } +} +func rewriteValueWasm_OpIsNonNil(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (IsNonNil p) + // result: (I64Eqz (I64Eqz p)) + for { + p := v_0 + v.reset(OpWasmI64Eqz) + v0 := b.NewValue0(v.Pos, OpWasmI64Eqz, typ.Bool) + v0.AddArg(p) + v.AddArg(v0) + return true + } +} +func rewriteValueWasm_OpLast(v *Value) bool { + // match: (Last ___) + // result: v.Args[len(v.Args)-1] + for { + v.copyOf(v.Args[len(v.Args)-1]) + return true + } +} +func rewriteValueWasm_OpLeq16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Leq16 x y) + // result: (I64LeS (SignExt16to64 x) (SignExt16to64 y)) for { x := v_0 y := v_1 @@ -1437,6 +2355,20 @@ func rewriteValueWasm_OpLoad(v *Value) bool { return true } // match: (Load ptr mem) + // cond: t.Size() == 16 + // result: (V128Load ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(t.Size() == 16) { + break + } + v.reset(OpWasmV128Load) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) // cond: t.Size() == 8 // result: (I64Load ptr mem) for { @@ -2396,6 +3328,374 @@ func rewriteValueWasm_OpPopCount8(v *Value) bool { return true } } +func rewriteValueWasm_OpRotateAllLeftVarInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllLeftVarInt16x8 x y) + // result: (V128Or (I16x8Shl x y) (I16x8ShrU x (I64Sub (I64Const [16]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI16x8Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI16x8ShrU, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(16) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllLeftVarInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllLeftVarInt32x4 x y) + // result: (V128Or (I32x4Shl x y) (I32x4ShrU x (I64Sub (I64Const [32]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI32x4Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI32x4ShrU, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(32) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllLeftVarInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllLeftVarInt64x2 x y) + // result: (V128Or (I64x2Shl x y) (I64x2ShrU x (I64Sub (I64Const [64]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI64x2Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI64x2ShrU, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(64) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllLeftVarInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllLeftVarInt8x16 x y) + // result: (V128Or (I8x16Shl x y) (I8x16ShrU x (I64Sub (I64Const [8]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI8x16Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI8x16ShrU, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(8) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllLeftVarUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllLeftVarUint16x8 x y) + // result: (V128Or (I16x8Shl x y) (I16x8ShrU x (I64Sub (I64Const [16]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI16x8Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI16x8ShrU, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(16) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllLeftVarUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllLeftVarUint32x4 x y) + // result: (V128Or (I32x4Shl x y) (I32x4ShrU x (I64Sub (I64Const [32]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI32x4Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI32x4ShrU, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(32) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllLeftVarUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllLeftVarUint64x2 x y) + // result: (V128Or (I64x2Shl x y) (I64x2ShrU x (I64Sub (I64Const [64]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI64x2Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI64x2ShrU, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(64) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllLeftVarUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllLeftVarUint8x16 x y) + // result: (V128Or (I8x16Shl x y) (I8x16ShrU x (I64Sub (I64Const [8]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI8x16Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI8x16ShrU, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(8) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllRightVarInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllRightVarInt16x8 x y) + // result: (V128Or (I16x8ShrU x y) (I16x8Shl x (I64Sub (I64Const [16]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI16x8ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI16x8Shl, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(16) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllRightVarInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllRightVarInt32x4 x y) + // result: (V128Or (I32x4ShrU x y) (I32x4Shl x (I64Sub (I64Const [32]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI32x4ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI32x4Shl, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(32) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllRightVarInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllRightVarInt64x2 x y) + // result: (V128Or (I64x2ShrU x y) (I64x2Shl x (I64Sub (I64Const [64]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI64x2ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI64x2Shl, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(64) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllRightVarInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllRightVarInt8x16 x y) + // result: (V128Or (I8x16ShrU x y) (I8x16Shl x (I64Sub (I64Const [8]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI8x16ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI8x16Shl, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(8) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllRightVarUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllRightVarUint16x8 x y) + // result: (V128Or (I16x8ShrU x y) (I16x8Shl x (I64Sub (I64Const [16]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI16x8ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI16x8Shl, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(16) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllRightVarUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllRightVarUint32x4 x y) + // result: (V128Or (I32x4ShrU x y) (I32x4Shl x (I64Sub (I64Const [32]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI32x4ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI32x4Shl, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(32) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllRightVarUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllRightVarUint64x2 x y) + // result: (V128Or (I64x2ShrU x y) (I64x2Shl x (I64Sub (I64Const [64]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI64x2ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI64x2Shl, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(64) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValueWasm_OpRotateAllRightVarUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RotateAllRightVarUint8x16 x y) + // result: (V128Or (I8x16ShrU x y) (I8x16Shl x (I64Sub (I64Const [8]) y))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmV128Or) + v0 := b.NewValue0(v.Pos, OpWasmI8x16ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI8x16Shl, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(8) + v2.AddArg2(v3, y) + v1.AddArg2(x, v2) + v.AddArg2(v0, v1) + return true + } +} func rewriteValueWasm_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -3199,6 +4499,992 @@ func rewriteValueWasm_OpRsh8x8(v *Value) bool { return true } } +func rewriteValueWasm_OpSelect0(v *Value) bool { + v_0 := v.Args[0] + // match: (Select0 (Mul64uhilo x y)) + // result: (Hmul64u x y) + for { + t := v.Type + if v_0.Op != OpMul64uhilo { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + v.reset(OpHmul64u) + v.Type = t + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueWasm_OpSelect1(v *Value) bool { + v_0 := v.Args[0] + // match: (Select1 (Mul64uhilo x y)) + // result: (I64Mul x y) + for { + if v_0.Op != OpMul64uhilo { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + v.reset(OpWasmI64Mul) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueWasm_OpShiftAllLeftInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftInt16x8 x d:(Const64 [c])) + // cond: uint64(c) < 16 + // result: (I16x8Shl x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 16) { + break + } + v.reset(OpWasmI16x8Shl) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllLeftInt16x8 x d:(I64Const [c])) + // cond: uint64(c) < 16 + // result: (I16x8Shl x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 16) { + break + } + v.reset(OpWasmI16x8Shl) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllLeftInt16x8 x y) + // result: (SelectV (I16x8Shl x y) (V128Xor x x) (I64LtU y (I64Const [16]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI16x8Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(16) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllLeftInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftInt32x4 x d:(Const64 [c])) + // cond: uint64(c) < 32 + // result: (I32x4Shl x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 32) { + break + } + v.reset(OpWasmI32x4Shl) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllLeftInt32x4 x d:(I64Const [c])) + // cond: uint64(c) < 32 + // result: (I32x4Shl x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 32) { + break + } + v.reset(OpWasmI32x4Shl) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllLeftInt32x4 x y) + // result: (SelectV (I32x4Shl x y) (V128Xor x x) (I64LtU y (I64Const [32]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI32x4Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(32) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllLeftInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftInt64x2 x d:(Const64 [c])) + // cond: uint64(c) < 64 + // result: (I64x2Shl x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 64) { + break + } + v.reset(OpWasmI64x2Shl) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllLeftInt64x2 x d:(I64Const [c])) + // cond: uint64(c) < 64 + // result: (I64x2Shl x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 64) { + break + } + v.reset(OpWasmI64x2Shl) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllLeftInt64x2 x y) + // result: (SelectV (I64x2Shl x y) (V128Xor x x) (I64LtU y (I64Const [64]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI64x2Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(64) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllLeftInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftInt8x16 x d:(Const64 [c])) + // cond: uint64(c) < 8 + // result: (I8x16Shl x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 8) { + break + } + v.reset(OpWasmI8x16Shl) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllLeftInt8x16 x d:(I64Const [c])) + // cond: uint64(c) < 8 + // result: (I8x16Shl x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 8) { + break + } + v.reset(OpWasmI8x16Shl) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllLeftInt8x16 x y) + // result: (SelectV (I8x16Shl x y) (V128Xor x x) (I64LtU y (I64Const [8]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI8x16Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(8) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllLeftUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftUint16x8 x d:(Const64 [c])) + // cond: uint64(c) < 16 + // result: (I16x8Shl x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 16) { + break + } + v.reset(OpWasmI16x8Shl) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllLeftUint16x8 x d:(I64Const [c])) + // cond: uint64(c) < 16 + // result: (I16x8Shl x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 16) { + break + } + v.reset(OpWasmI16x8Shl) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllLeftUint16x8 x y) + // result: (SelectV (I16x8Shl x y) (V128Xor x x) (I64LtU y (I64Const [16]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI16x8Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(16) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllLeftUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftUint32x4 x d:(Const64 [c])) + // cond: uint64(c) < 32 + // result: (I32x4Shl x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 32) { + break + } + v.reset(OpWasmI32x4Shl) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllLeftUint32x4 x d:(I64Const [c])) + // cond: uint64(c) < 32 + // result: (I32x4Shl x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 32) { + break + } + v.reset(OpWasmI32x4Shl) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllLeftUint32x4 x y) + // result: (SelectV (I32x4Shl x y) (V128Xor x x) (I64LtU y (I64Const [32]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI32x4Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(32) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllLeftUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftUint64x2 x d:(Const64 [c])) + // cond: uint64(c) < 64 + // result: (I64x2Shl x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 64) { + break + } + v.reset(OpWasmI64x2Shl) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllLeftUint64x2 x d:(I64Const [c])) + // cond: uint64(c) < 64 + // result: (I64x2Shl x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 64) { + break + } + v.reset(OpWasmI64x2Shl) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllLeftUint64x2 x y) + // result: (SelectV (I64x2Shl x y) (V128Xor x x) (I64LtU y (I64Const [64]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI64x2Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(64) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllLeftUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllLeftUint8x16 x d:(Const64 [c])) + // cond: uint64(c) < 8 + // result: (I8x16Shl x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 8) { + break + } + v.reset(OpWasmI8x16Shl) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllLeftUint8x16 x d:(I64Const [c])) + // cond: uint64(c) < 8 + // result: (I8x16Shl x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 8) { + break + } + v.reset(OpWasmI8x16Shl) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllLeftUint8x16 x y) + // result: (SelectV (I8x16Shl x y) (V128Xor x x) (I64LtU y (I64Const [8]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI8x16Shl, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(8) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllRightInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightInt16x8 x d:(Const64 [c])) + // cond: uint64(c) < 16 + // result: (I16x8ShrS x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 16) { + break + } + v.reset(OpWasmI16x8ShrS) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllRightInt16x8 x d:(I64Const [c])) + // cond: uint64(c) < 16 + // result: (I16x8ShrS x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 16) { + break + } + v.reset(OpWasmI16x8ShrS) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllRightInt16x8 x y) + // result: (SelectV (I16x8ShrS x y) (I16x8ShrS x (I64Const [15])) (I64LtU y (I64Const [16]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI16x8ShrS, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI16x8ShrS, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v2.AuxInt = int64ToAuxInt(15) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v4 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v4.AuxInt = int64ToAuxInt(16) + v3.AddArg2(y, v4) + v.AddArg3(v0, v1, v3) + return true + } +} +func rewriteValueWasm_OpShiftAllRightInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightInt32x4 x d:(Const64 [c])) + // cond: uint64(c) < 32 + // result: (I32x4ShrS x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 32) { + break + } + v.reset(OpWasmI32x4ShrS) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllRightInt32x4 x d:(I64Const [c])) + // cond: uint64(c) < 32 + // result: (I32x4ShrS x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 32) { + break + } + v.reset(OpWasmI32x4ShrS) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllRightInt32x4 x y) + // result: (SelectV (I32x4ShrS x y) (I32x4ShrS x (I64Const [31])) (I64LtU y (I64Const [32]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI32x4ShrS, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI32x4ShrS, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v2.AuxInt = int64ToAuxInt(31) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v4 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v4.AuxInt = int64ToAuxInt(32) + v3.AddArg2(y, v4) + v.AddArg3(v0, v1, v3) + return true + } +} +func rewriteValueWasm_OpShiftAllRightInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightInt64x2 x d:(Const64 [c])) + // cond: uint64(c) < 64 + // result: (I64x2ShrS x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 64) { + break + } + v.reset(OpWasmI64x2ShrS) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllRightInt64x2 x d:(I64Const [c])) + // cond: uint64(c) < 64 + // result: (I64x2ShrS x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 64) { + break + } + v.reset(OpWasmI64x2ShrS) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllRightInt64x2 x y) + // result: (SelectV (I64x2ShrS x y) (I64x2ShrS x (I64Const [63])) (I64LtU y (I64Const [64]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI64x2ShrS, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI64x2ShrS, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v2.AuxInt = int64ToAuxInt(63) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v4 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v4.AuxInt = int64ToAuxInt(64) + v3.AddArg2(y, v4) + v.AddArg3(v0, v1, v3) + return true + } +} +func rewriteValueWasm_OpShiftAllRightInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightInt8x16 x d:(Const64 [c])) + // cond: uint64(c) < 8 + // result: (I8x16ShrS x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 8) { + break + } + v.reset(OpWasmI8x16ShrS) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllRightInt8x16 x d:(I64Const [c])) + // cond: uint64(c) < 8 + // result: (I8x16ShrS x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 8) { + break + } + v.reset(OpWasmI8x16ShrS) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllRightInt8x16 x y) + // result: (SelectV (I8x16ShrS x y) (I8x16ShrS x (I64Const [7])) (I64LtU y (I64Const [8]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI8x16ShrS, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmI8x16ShrS, typ.Vec128) + v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v2.AuxInt = int64ToAuxInt(7) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v4 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v4.AuxInt = int64ToAuxInt(8) + v3.AddArg2(y, v4) + v.AddArg3(v0, v1, v3) + return true + } +} +func rewriteValueWasm_OpShiftAllRightUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightUint16x8 x d:(Const64 [c])) + // cond: uint64(c) < 16 + // result: (I16x8ShrU x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 16) { + break + } + v.reset(OpWasmI16x8ShrU) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllRightUint16x8 x d:(I64Const [c])) + // cond: uint64(c) < 16 + // result: (I16x8ShrU x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 16) { + break + } + v.reset(OpWasmI16x8ShrU) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllRightUint16x8 x y) + // result: (SelectV (I16x8ShrU x y) (V128Xor x x) (I64LtU y (I64Const [16]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI16x8ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(16) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllRightUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightUint32x4 x d:(Const64 [c])) + // cond: uint64(c) < 32 + // result: (I32x4ShrU x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 32) { + break + } + v.reset(OpWasmI32x4ShrU) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllRightUint32x4 x d:(I64Const [c])) + // cond: uint64(c) < 32 + // result: (I32x4ShrU x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 32) { + break + } + v.reset(OpWasmI32x4ShrU) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllRightUint32x4 x y) + // result: (SelectV (I32x4ShrU x y) (V128Xor x x) (I64LtU y (I64Const [32]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI32x4ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(32) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllRightUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightUint64x2 x d:(Const64 [c])) + // cond: uint64(c) < 64 + // result: (I64x2ShrU x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 64) { + break + } + v.reset(OpWasmI64x2ShrU) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllRightUint64x2 x d:(I64Const [c])) + // cond: uint64(c) < 64 + // result: (I64x2ShrU x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 64) { + break + } + v.reset(OpWasmI64x2ShrU) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllRightUint64x2 x y) + // result: (SelectV (I64x2ShrU x y) (V128Xor x x) (I64LtU y (I64Const [64]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI64x2ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(64) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} +func rewriteValueWasm_OpShiftAllRightUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (ShiftAllRightUint8x16 x d:(Const64 [c])) + // cond: uint64(c) < 8 + // result: (I8x16ShrU x (I64Const [c])) + for { + x := v_0 + d := v_1 + if d.Op != OpConst64 { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 8) { + break + } + v.reset(OpWasmI8x16ShrU) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c) + v.AddArg2(x, v0) + return true + } + // match: (ShiftAllRightUint8x16 x d:(I64Const [c])) + // cond: uint64(c) < 8 + // result: (I8x16ShrU x d) + for { + x := v_0 + d := v_1 + if d.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(d.AuxInt) + if !(uint64(c) < 8) { + break + } + v.reset(OpWasmI8x16ShrU) + v.AddArg2(x, d) + return true + } + // match: (ShiftAllRightUint8x16 x y) + // result: (SelectV (I8x16ShrU x y) (V128Xor x x) (I64LtU y (I64Const [8]))) + for { + x := v_0 + y := v_1 + v.reset(OpWasmSelectV) + v0 := b.NewValue0(v.Pos, OpWasmI8x16ShrU, typ.Vec128) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpWasmV128Xor, typ.Vec128) + v1.AddArg2(x, x) + v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool) + v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v3.AuxInt = int64ToAuxInt(8) + v2.AddArg2(y, v3) + v.AddArg3(v0, v1, v2) + return true + } +} func rewriteValueWasm_OpSignExt16to32(v *Value) bool { v_0 := v.Args[0] // match: (SignExt16to32 x:(I64Load16S _ _)) @@ -3374,68 +5660,198 @@ func rewriteValueWasm_OpStore(v *Value) bool { if !(is32BitFloat(t)) { break } - v.reset(OpWasmF32Store) - v.AddArg3(ptr, val, mem) + v.reset(OpWasmF32Store) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 16 + // result: (V128Store ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 16) { + break + } + v.reset(OpWasmV128Store) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 8 + // result: (I64Store ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 8) { + break + } + v.reset(OpWasmI64Store) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 4 + // result: (I64Store32 ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 4) { + break + } + v.reset(OpWasmI64Store32) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 2 + // result: (I64Store16 ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 2) { + break + } + v.reset(OpWasmI64Store16) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 1 + // result: (I64Store8 ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 1) { + break + } + v.reset(OpWasmI64Store8) + v.AddArg3(ptr, val, mem) + return true + } + return false +} +func rewriteValueWasm_OpWasmF32DemoteF64(v *Value) bool { + v_0 := v.Args[0] + // match: (F32DemoteF64 (F64Sqrt (F64PromoteF32 x))) + // result: (F32Sqrt x) + for { + if v_0.Op != OpWasmF64Sqrt { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpWasmF64PromoteF32 { + break + } + x := v_0_0.Args[0] + v.reset(OpWasmF32Sqrt) + v.AddArg(x) + return true + } + // match: (F32DemoteF64 (F64Trunc (F64PromoteF32 x))) + // result: (F32Trunc x) + for { + if v_0.Op != OpWasmF64Trunc { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpWasmF64PromoteF32 { + break + } + x := v_0_0.Args[0] + v.reset(OpWasmF32Trunc) + v.AddArg(x) + return true + } + // match: (F32DemoteF64 (F64Ceil (F64PromoteF32 x))) + // result: (F32Ceil x) + for { + if v_0.Op != OpWasmF64Ceil { + break + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpWasmF64PromoteF32 { + break + } + x := v_0_0.Args[0] + v.reset(OpWasmF32Ceil) + v.AddArg(x) return true } - // match: (Store {t} ptr val mem) - // cond: t.Size() == 8 - // result: (I64Store ptr val mem) + // match: (F32DemoteF64 (F64Floor (F64PromoteF32 x))) + // result: (F32Floor x) for { - t := auxToType(v.Aux) - ptr := v_0 - val := v_1 - mem := v_2 - if !(t.Size() == 8) { + if v_0.Op != OpWasmF64Floor { break } - v.reset(OpWasmI64Store) - v.AddArg3(ptr, val, mem) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpWasmF64PromoteF32 { + break + } + x := v_0_0.Args[0] + v.reset(OpWasmF32Floor) + v.AddArg(x) return true } - // match: (Store {t} ptr val mem) - // cond: t.Size() == 4 - // result: (I64Store32 ptr val mem) + // match: (F32DemoteF64 (F64Nearest (F64PromoteF32 x))) + // result: (F32Nearest x) for { - t := auxToType(v.Aux) - ptr := v_0 - val := v_1 - mem := v_2 - if !(t.Size() == 4) { + if v_0.Op != OpWasmF64Nearest { break } - v.reset(OpWasmI64Store32) - v.AddArg3(ptr, val, mem) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpWasmF64PromoteF32 { + break + } + x := v_0_0.Args[0] + v.reset(OpWasmF32Nearest) + v.AddArg(x) return true } - // match: (Store {t} ptr val mem) - // cond: t.Size() == 2 - // result: (I64Store16 ptr val mem) + // match: (F32DemoteF64 (F64Abs (F64PromoteF32 x))) + // result: (F32Abs x) for { - t := auxToType(v.Aux) - ptr := v_0 - val := v_1 - mem := v_2 - if !(t.Size() == 2) { + if v_0.Op != OpWasmF64Abs { break } - v.reset(OpWasmI64Store16) - v.AddArg3(ptr, val, mem) + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpWasmF64PromoteF32 { + break + } + x := v_0_0.Args[0] + v.reset(OpWasmF32Abs) + v.AddArg(x) return true } - // match: (Store {t} ptr val mem) - // cond: t.Size() == 1 - // result: (I64Store8 ptr val mem) + // match: (F32DemoteF64 (F64Copysign (F64PromoteF32 x) (F64PromoteF32 y))) + // result: (F32Copysign x y) for { - t := auxToType(v.Aux) - ptr := v_0 - val := v_1 - mem := v_2 - if !(t.Size() == 1) { + if v_0.Op != OpWasmF64Copysign { break } - v.reset(OpWasmI64Store8) - v.AddArg3(ptr, val, mem) + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpWasmF64PromoteF32 { + break + } + x := v_0_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpWasmF64PromoteF32 { + break + } + y := v_0_1.Args[0] + v.reset(OpWasmF32Copysign) + v.AddArg2(x, y) return true } return false @@ -3650,6 +6066,49 @@ func rewriteValueWasm_OpWasmI64And(v *Value) bool { v.AuxInt = int64ToAuxInt(x & y) return true } + // match: (I64And x (I64Const [-1])) + // result: x + for { + x := v_0 + if v_1.Op != OpWasmI64Const || auxIntToInt64(v_1.AuxInt) != -1 { + break + } + v.copyOf(x) + return true + } + // match: (I64And x (I64Const [0])) + // result: (I64Const [0]) + for { + if v_1.Op != OpWasmI64Const || auxIntToInt64(v_1.AuxInt) != 0 { + break + } + v.reset(OpWasmI64Const) + v.AuxInt = int64ToAuxInt(0) + return true + } + // match: (I64And (I64And x (I64Const [c1])) (I64Const [c2])) + // result: (I64And x (I64Const [c1 & c2])) + for { + if v_0.Op != OpWasmI64And { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpWasmI64Const { + break + } + c1 := auxIntToInt64(v_0_1.AuxInt) + if v_1.Op != OpWasmI64Const { + break + } + c2 := auxIntToInt64(v_1.AuxInt) + v.reset(OpWasmI64And) + v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64) + v0.AuxInt = int64ToAuxInt(c1 & c2) + v.AddArg2(x, v0) + return true + } // match: (I64And (I64Const [x]) y) // cond: y.Op != OpWasmI64Const // result: (I64And y (I64Const [x])) @@ -3763,6 +6222,144 @@ func rewriteValueWasm_OpWasmI64Eqz(v *Value) bool { } return false } +func rewriteValueWasm_OpWasmI64Extend16S(v *Value) bool { + v_0 := v.Args[0] + // match: (I64Extend16S (I64Extend16S x)) + // result: (I64Extend16S x) + for { + if v_0.Op != OpWasmI64Extend16S { + break + } + x := v_0.Args[0] + v.reset(OpWasmI64Extend16S) + v.AddArg(x) + return true + } + // match: (I64Extend16S (I64Extend8S x)) + // result: (I64Extend8S x) + for { + if v_0.Op != OpWasmI64Extend8S { + break + } + x := v_0.Args[0] + v.reset(OpWasmI64Extend8S) + v.AddArg(x) + return true + } + // match: (I64Extend16S x:(I64And _ (I64Const [c]))) + // cond: c >= 0 && int64(int16(c)) == c + // result: x + for { + x := v_0 + if x.Op != OpWasmI64And { + break + } + _ = x.Args[1] + x_1 := x.Args[1] + if x_1.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(x_1.AuxInt) + if !(c >= 0 && int64(int16(c)) == c) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueWasm_OpWasmI64Extend32S(v *Value) bool { + v_0 := v.Args[0] + // match: (I64Extend32S (I64Extend32S x)) + // result: (I64Extend32S x) + for { + if v_0.Op != OpWasmI64Extend32S { + break + } + x := v_0.Args[0] + v.reset(OpWasmI64Extend32S) + v.AddArg(x) + return true + } + // match: (I64Extend32S (I64Extend16S x)) + // result: (I64Extend16S x) + for { + if v_0.Op != OpWasmI64Extend16S { + break + } + x := v_0.Args[0] + v.reset(OpWasmI64Extend16S) + v.AddArg(x) + return true + } + // match: (I64Extend32S (I64Extend8S x)) + // result: (I64Extend8S x) + for { + if v_0.Op != OpWasmI64Extend8S { + break + } + x := v_0.Args[0] + v.reset(OpWasmI64Extend8S) + v.AddArg(x) + return true + } + // match: (I64Extend32S x:(I64And _ (I64Const [c]))) + // cond: c >= 0 && int64(int32(c)) == c + // result: x + for { + x := v_0 + if x.Op != OpWasmI64And { + break + } + _ = x.Args[1] + x_1 := x.Args[1] + if x_1.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(x_1.AuxInt) + if !(c >= 0 && int64(int32(c)) == c) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueWasm_OpWasmI64Extend8S(v *Value) bool { + v_0 := v.Args[0] + // match: (I64Extend8S (I64Extend8S x)) + // result: (I64Extend8S x) + for { + if v_0.Op != OpWasmI64Extend8S { + break + } + x := v_0.Args[0] + v.reset(OpWasmI64Extend8S) + v.AddArg(x) + return true + } + // match: (I64Extend8S x:(I64And _ (I64Const [c]))) + // cond: c >= 0 && int64(int8(c)) == c + // result: x + for { + x := v_0 + if x.Op != OpWasmI64And { + break + } + _ = x.Args[1] + x_1 := x.Args[1] + if x_1.Op != OpWasmI64Const { + break + } + c := auxIntToInt64(x_1.AuxInt) + if !(c >= 0 && int64(int8(c)) == c) { + break + } + v.copyOf(x) + return true + } + return false +} func rewriteValueWasm_OpWasmI64LeU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -4149,6 +6746,26 @@ func rewriteValueWasm_OpWasmI64Mul(v *Value) bool { v.AuxInt = int64ToAuxInt(x * y) return true } + // match: (I64Mul x (I64Const [0])) + // result: (I64Const [0]) + for { + if v_1.Op != OpWasmI64Const || auxIntToInt64(v_1.AuxInt) != 0 { + break + } + v.reset(OpWasmI64Const) + v.AuxInt = int64ToAuxInt(0) + return true + } + // match: (I64Mul x (I64Const [1])) + // result: x + for { + x := v_0 + if v_1.Op != OpWasmI64Const || auxIntToInt64(v_1.AuxInt) != 1 { + break + } + v.copyOf(x) + return true + } // match: (I64Mul (I64Const [x]) y) // cond: y.Op != OpWasmI64Const // result: (I64Mul y (I64Const [x])) @@ -4265,6 +6882,26 @@ func rewriteValueWasm_OpWasmI64Or(v *Value) bool { v.AuxInt = int64ToAuxInt(x | y) return true } + // match: (I64Or x (I64Const [0])) + // result: x + for { + x := v_0 + if v_1.Op != OpWasmI64Const || auxIntToInt64(v_1.AuxInt) != 0 { + break + } + v.copyOf(x) + return true + } + // match: (I64Or x (I64Const [-1])) + // result: (I64Const [-1]) + for { + if v_1.Op != OpWasmI64Const || auxIntToInt64(v_1.AuxInt) != -1 { + break + } + v.reset(OpWasmI64Const) + v.AuxInt = int64ToAuxInt(-1) + return true + } // match: (I64Or (I64Const [x]) y) // cond: y.Op != OpWasmI64Const // result: (I64Or y (I64Const [x])) @@ -4449,6 +7086,26 @@ func rewriteValueWasm_OpWasmI64Store8(v *Value) bool { } return false } +func rewriteValueWasm_OpWasmI64Sub(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (I64Sub (I64Const [x]) (I64Const [y])) + // result: (I64Const [x - y]) + for { + if v_0.Op != OpWasmI64Const { + break + } + x := auxIntToInt64(v_0.AuxInt) + if v_1.Op != OpWasmI64Const { + break + } + y := auxIntToInt64(v_1.AuxInt) + v.reset(OpWasmI64Const) + v.AuxInt = int64ToAuxInt(x - y) + return true + } + return false +} func rewriteValueWasm_OpWasmI64Xor(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -4469,6 +7126,16 @@ func rewriteValueWasm_OpWasmI64Xor(v *Value) bool { v.AuxInt = int64ToAuxInt(x ^ y) return true } + // match: (I64Xor x (I64Const [0])) + // result: x + for { + x := v_0 + if v_1.Op != OpWasmI64Const || auxIntToInt64(v_1.AuxInt) != 0 { + break + } + v.copyOf(x) + return true + } // match: (I64Xor (I64Const [x]) y) // cond: y.Op != OpWasmI64Const // result: (I64Xor y (I64Const [x])) @@ -4872,6 +7539,16 @@ func rewriteValueWasm_OpZeroExt8to64(v *Value) bool { return true } } +func rewriteValueWasm_OpZeroSIMD(v *Value) bool { + // match: (ZeroSIMD ) + // result: (V128Zero ) + for { + t := v.Type + v.reset(OpWasmV128Zero) + v.Type = t + return true + } +} func rewriteBlockWasm(b *Block) bool { return false } diff --git a/src/cmd/compile/internal/ssa/rewrite_test.go b/src/cmd/compile/internal/ssa/rewrite_test.go index 92e9d3fd5b9ca5..02c0cd2780e0f0 100644 --- a/src/cmd/compile/internal/ssa/rewrite_test.go +++ b/src/cmd/compile/internal/ssa/rewrite_test.go @@ -6,6 +6,8 @@ package ssa import ( "cmd/compile/internal/rttype" + "math" + "math/rand" "reflect" "testing" "unsafe" @@ -42,6 +44,78 @@ func TestSubFlags(t *testing.T) { } } +//go:noinline +func unopt(f func(float64) float64, x float32) float32 { + return float32(f(float64(x))) +} + +func differ(x, y float32) bool { + if x != x && y != y { + // if both are NaN, exact bit pattern of the NaN is uninteresting + return false + } + return math.Float32bits(x) != math.Float32bits(y) +} + +func test32bitUnary(t *testing.T, x float32) { + if want, got := unopt(math.Round, x), float32(math.Round(float64(x))); differ(want, got) { + t.Errorf("Optimized 32-bit Round did not match, x=%f, want=%f, got=%f", x, want, got) + } + if want, got := unopt(math.RoundToEven, x), float32(math.RoundToEven(float64(x))); differ(want, got) { + t.Errorf("Optimized 32-bit RoundToEven did not match, x=%f, want=%f, got=%f", x, want, got) + } + if want, got := unopt(math.Trunc, x), float32(math.Trunc(float64(x))); differ(want, got) { + t.Errorf("Optimized 32-bit Trunc did not match, x=%f, want=%f, got=%f", x, want, got) + } + if want, got := unopt(math.Ceil, x), float32(math.Ceil(float64(x))); differ(want, got) { + t.Errorf("Optimized 32-bit Ceil did not match, x=%f, want=%f, got=%f", x, want, got) + } + if want, got := unopt(math.Floor, x), float32(math.Floor(float64(x))); differ(want, got) { + t.Errorf("Optimized 32-bit Floor did not match, x=%f, want=%f, got=%f", x, want, got) + } + if x >= 0 { + if want, got := unopt(math.Sqrt, x), float32(math.Sqrt(float64(x))); differ(want, got) { + t.Errorf("Optimized 32-bit Sqrt did not match, x=%f, want=%f, got=%f", x, want, got) + } + } + if want, got := unopt(math.Abs, x), float32(math.Abs(float64(x))); differ(want, got) { + t.Errorf("Optimized 32-bit Abs did not match, x=%f, want=%f, got=%f", x, want, got) + } + +} + +var zero float32 + +func Test32bitUnary(t *testing.T) { + // this is mostly for testing rounding. + test32bitUnary(t, -1.5) + test32bitUnary(t, -0.5) + test32bitUnary(t, 0.5) + test32bitUnary(t, 1.5) + + test32bitUnary(t, -1.4) + test32bitUnary(t, -0.4) + test32bitUnary(t, 0.4) + test32bitUnary(t, 1.4) + + test32bitUnary(t, -1.6) + test32bitUnary(t, -0.6) + test32bitUnary(t, 0.6) + test32bitUnary(t, 1.6) + + // negative zero + test32bitUnary(t, 1/(-1/zero)) + + var rnd = rand.New(rand.NewSource(0)) + + for i := uint32(0); i <= 1<<20; i++ { + test32bitUnary(t, math.Float32frombits(math.Float32bits(math.MaxFloat32)-i)) + test32bitUnary(t, float32(i)+1.5) + test32bitUnary(t, math.Float32frombits(rnd.Uint32())) + } + +} + func TestIsPPC64WordRotateMask(t *testing.T) { tests := []struct { input int64 @@ -285,3 +359,20 @@ func TestDisjointTypesRun(t *testing.T) { t.Errorf("disjointTypes gives an incorrect answer that leads to an incorrect optimization.") } } + +func TestModularMultiplicativeInverse(t *testing.T) { + t.Parallel() + + // We've got 63 bits of phase space for the Multiplier + // Needless to say this is too much to bruteforce here. + // I've randomly picked a range of 1<<24 because it runs in 0.03s on my machine which isn't too slow. + // We test both sides of the wrapping point (0 and math.MaxUint64) since we need to test something and it's a usual place to have bugs. + const halfRange = 1 << 23 + for i := -int64(halfRange) - 1; i < halfRange; i += 2 { // odd only, a bit after to a bit before the wrapping point + mmi := modularMultiplicativeInverse(uint64(i)) + + if uint64(i)*mmi != 1 { + t.Errorf("%d * modularMultiplicativeInverse(%d) != 1; modularMultiplicativeInverse(%d) == %d", i, i, i, mmi) + } + } +} diff --git a/src/cmd/compile/internal/ssa/rewritedec.go b/src/cmd/compile/internal/ssa/rewritedec.go index 16d02692105b55..1141d322bf0a59 100644 --- a/src/cmd/compile/internal/ssa/rewritedec.go +++ b/src/cmd/compile/internal/ssa/rewritedec.go @@ -242,12 +242,16 @@ func rewriteValuedec_OpIData(v *Value) bool { config := b.Func.Config typ := &b.Func.Config.Types // match: (IData (IMake _ data)) + // cond: data.Op != OpStructMake && data.Op != OpArrayMake1 // result: data for { if v_0.Op != OpIMake { break } data := v_0.Args[1] + if !(data.Op != OpStructMake && data.Op != OpArrayMake1) { + break + } v.copyOf(data) return true } @@ -279,11 +283,20 @@ func rewriteValuedec_OpIData(v *Value) bool { func rewriteValuedec_OpIMake(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (IMake _typ (StructMake val)) + // match: (IMake _typ (StructMake ___)) + // result: imakeOfStructMake(v) + for { + if v_1.Op != OpStructMake { + break + } + v.copyOf(imakeOfStructMake(v)) + return true + } + // match: (IMake _typ (ArrayMake1 val)) // result: (IMake _typ val) for { _typ := v_0 - if v_1.Op != OpStructMake || len(v_1.Args) != 1 { + if v_1.Op != OpArrayMake1 { break } val := v_1.Args[0] @@ -839,17 +852,34 @@ func rewriteValuedec_OpStructMake(v *Value) bool { func rewriteValuedec_OpStructSelect(v *Value) bool { v_0 := v.Args[0] b := v.Block - // match: (StructSelect [0] (IData x)) + // match: (StructSelect (IData x)) + // cond: v.Type.Size() > 0 // result: (IData x) for { - if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpIData { + if v_0.Op != OpIData { break } x := v_0.Args[0] + if !(v.Type.Size() > 0) { + break + } v.reset(OpIData) v.AddArg(x) return true } + // match: (StructSelect (IData x)) + // cond: v.Type.Size() == 0 + // result: (Empty) + for { + if v_0.Op != OpIData { + break + } + if !(v.Type.Size() == 0) { + break + } + v.reset(OpEmpty) + return true + } // match: (StructSelect [i] x:(StructMake ___)) // result: x.Args[i] for { @@ -861,13 +891,10 @@ func rewriteValuedec_OpStructSelect(v *Value) bool { v.copyOf(x.Args[i]) return true } - // match: (StructSelect [0] x) + // match: (StructSelect x) // cond: x.Type.IsPtrShaped() // result: x for { - if auxIntToInt64(v.AuxInt) != 0 { - break - } x := v_0 if !(x.Type.IsPtrShaped()) { break diff --git a/src/cmd/compile/internal/ssa/rewritedec64.go b/src/cmd/compile/internal/ssa/rewritedec64.go index 901dc758c30cd3..a0388551b53015 100644 --- a/src/cmd/compile/internal/ssa/rewritedec64.go +++ b/src/cmd/compile/internal/ssa/rewritedec64.go @@ -12,6 +12,8 @@ func rewriteValuedec64(v *Value) bool { return rewriteValuedec64_OpAnd64(v) case OpArg: return rewriteValuedec64_OpArg(v) + case OpAvg64u: + return rewriteValuedec64_OpAvg64u(v) case OpBitLen64: return rewriteValuedec64_OpBitLen64(v) case OpBswap64: @@ -27,10 +29,16 @@ func rewriteValuedec64(v *Value) bool { return true case OpEq64: return rewriteValuedec64_OpEq64(v) + case OpHmul64: + return rewriteValuedec64_OpHmul64(v) + case OpHmul64u: + return rewriteValuedec64_OpHmul64u(v) case OpInt64Hi: return rewriteValuedec64_OpInt64Hi(v) case OpInt64Lo: return rewriteValuedec64_OpInt64Lo(v) + case OpLast: + return rewriteValuedec64_OpLast(v) case OpLeq64: return rewriteValuedec64_OpLeq64(v) case OpLeq64U: @@ -57,6 +65,8 @@ func rewriteValuedec64(v *Value) bool { return rewriteValuedec64_OpLsh8x64(v) case OpMul64: return rewriteValuedec64_OpMul64(v) + case OpMul64uhilo: + return rewriteValuedec64_OpMul64uhilo(v) case OpNeg64: return rewriteValuedec64_OpNeg64(v) case OpNeq64: @@ -101,6 +111,10 @@ func rewriteValuedec64(v *Value) bool { return rewriteValuedec64_OpRsh8Ux64(v) case OpRsh8x64: return rewriteValuedec64_OpRsh8x64(v) + case OpSelect0: + return rewriteValuedec64_OpSelect0(v) + case OpSelect1: + return rewriteValuedec64_OpSelect1(v) case OpSignExt16to64: return rewriteValuedec64_OpSignExt16to64(v) case OpSignExt32to64: @@ -133,29 +147,33 @@ func rewriteValuedec64_OpAdd64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Add64 x y) - // result: (Int64Make (Add32withcarry (Int64Hi x) (Int64Hi y) (Select1 (Add32carry (Int64Lo x) (Int64Lo y)))) (Select0 (Add32carry (Int64Lo x) (Int64Lo y)))) + // match: (Add64 x y) + // result: (Last x0: (Int64Lo x) x1: (Int64Hi x) y0: (Int64Lo y) y1: (Int64Hi y) add: (Add32carry x0 y0) (Int64Make (Add32withcarry x1 y1 (Select1 add)) (Select0 add))) for { + t := v.Type x := v_0 y := v_1 - v.reset(OpInt64Make) - v0 := b.NewValue0(v.Pos, OpAdd32withcarry, typ.Int32) - v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) - v2.AddArg(y) - v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v4 := b.NewValue0(v.Pos, OpAdd32carry, types.NewTuple(typ.UInt32, types.TypeFlags)) - v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) - v5.AddArg(x) - v6 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) - v6.AddArg(y) - v4.AddArg2(v5, v6) - v3.AddArg(v4) - v0.AddArg3(v1, v2, v3) - v7 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) - v7.AddArg(v4) - v.AddArg2(v0, v7) + v.reset(OpLast) + v.Type = t + x0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + x0.AddArg(x) + x1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + x1.AddArg(x) + y0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + y0.AddArg(y) + y1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + y1.AddArg(y) + add := b.NewValue0(v.Pos, OpAdd32carry, types.NewTuple(typ.UInt32, types.TypeFlags)) + add.AddArg2(x0, y0) + v5 := b.NewValue0(v.Pos, OpInt64Make, typ.UInt64) + v6 := b.NewValue0(v.Pos, OpAdd32withcarry, typ.UInt32) + v7 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v7.AddArg(add) + v6.AddArg3(x1, y1, v7) + v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + v8.AddArg(add) + v5.AddArg2(v6, v8) + v.AddArg6(x0, x1, y0, y1, add, v5) return true } } @@ -268,6 +286,28 @@ func rewriteValuedec64_OpArg(v *Value) bool { } return false } +func rewriteValuedec64_OpAvg64u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Avg64u x y) + // result: (Add64 (Rsh64Ux32 (Sub64 x y) (Const32 [1])) y) + for { + t := v.Type + x := v_0 + y := v_1 + v.reset(OpAdd64) + v0 := b.NewValue0(v.Pos, OpRsh64Ux32, t) + v1 := b.NewValue0(v.Pos, OpSub64, t) + v1.AddArg2(x, y) + v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v2.AuxInt = int32ToAuxInt(1) + v0.AddArg2(v1, v2) + v.AddArg2(v0, y) + return true + } +} func rewriteValuedec64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block @@ -430,6 +470,62 @@ func rewriteValuedec64_OpEq64(v *Value) bool { return true } } +func rewriteValuedec64_OpHmul64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Hmul64 x y) + // result: (Last p: (Hmul64u x y) xSign: (Int64Make xs:(Rsh32x32 (Int64Hi x) (Const32 [31])) xs) ySign: (Int64Make ys:(Rsh32x32 (Int64Hi y) (Const32 [31])) ys) (Sub64 (Sub64 p (And64 xSign y)) (And64 ySign x))) + for { + x := v_0 + y := v_1 + v.reset(OpLast) + p := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) + p.AddArg2(x, y) + xSign := b.NewValue0(v.Pos, OpInt64Make, typ.UInt64) + xs := b.NewValue0(v.Pos, OpRsh32x32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v3.AddArg(x) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int32ToAuxInt(31) + xs.AddArg2(v3, v4) + xSign.AddArg2(xs, xs) + ySign := b.NewValue0(v.Pos, OpInt64Make, typ.UInt64) + ys := b.NewValue0(v.Pos, OpRsh32x32, typ.UInt32) + v7 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v7.AddArg(y) + ys.AddArg2(v7, v4) + ySign.AddArg2(ys, ys) + v8 := b.NewValue0(v.Pos, OpSub64, typ.Int64) + v9 := b.NewValue0(v.Pos, OpSub64, typ.Int64) + v10 := b.NewValue0(v.Pos, OpAnd64, typ.Int64) + v10.AddArg2(xSign, y) + v9.AddArg2(p, v10) + v11 := b.NewValue0(v.Pos, OpAnd64, typ.Int64) + v11.AddArg2(ySign, x) + v8.AddArg2(v9, v11) + v.AddArg4(p, xSign, ySign, v8) + return true + } +} +func rewriteValuedec64_OpHmul64u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Hmul64u x y) + // result: (Select0 (Mul64uhilo x y)) + for { + x := v_0 + y := v_1 + v.reset(OpSelect0) + v0 := b.NewValue0(v.Pos, OpMul64uhilo, types.NewTuple(typ.UInt64, typ.UInt64)) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} func rewriteValuedec64_OpInt64Hi(v *Value) bool { v_0 := v.Args[0] // match: (Int64Hi (Int64Make hi _)) @@ -458,6 +554,14 @@ func rewriteValuedec64_OpInt64Lo(v *Value) bool { } return false } +func rewriteValuedec64_OpLast(v *Value) bool { + // match: (Last ___) + // result: v.Args[len(v.Args)-1] + for { + v.copyOf(v.Args[len(v.Args)-1]) + return true + } +} func rewriteValuedec64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -1114,35 +1218,124 @@ func rewriteValuedec64_OpMul64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Mul64 x y) - // result: (Int64Make (Add32 (Mul32 (Int64Lo x) (Int64Hi y)) (Add32 (Mul32 (Int64Hi x) (Int64Lo y)) (Select0 (Mul32uhilo (Int64Lo x) (Int64Lo y))))) (Select1 (Mul32uhilo (Int64Lo x) (Int64Lo y)))) + // match: (Mul64 x y) + // result: (Last x0: (Int64Lo x) x1: (Int64Hi x) y0: (Int64Lo y) y1: (Int64Hi y) x0y0: (Mul32uhilo x0 y0) x0y0Hi: (Select0 x0y0) x0y0Lo: (Select1 x0y0) (Int64Make (Add32 x0y0Hi (Add32 (Mul32 x0 y1) (Mul32 x1 y0))) x0y0Lo)) for { + t := v.Type x := v_0 y := v_1 - v.reset(OpInt64Make) - v0 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) - v2.AddArg(x) - v3 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) - v3.AddArg(y) - v1.AddArg2(v2, v3) - v4 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) - v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v6 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) - v6.AddArg(x) - v7 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) - v7.AddArg(y) - v5.AddArg2(v6, v7) - v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) - v9 := b.NewValue0(v.Pos, OpMul32uhilo, types.NewTuple(typ.UInt32, typ.UInt32)) - v9.AddArg2(v2, v7) - v8.AddArg(v9) - v4.AddArg2(v5, v8) - v0.AddArg2(v1, v4) - v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt32) - v10.AddArg(v9) - v.AddArg2(v0, v10) + v.reset(OpLast) + v.Type = t + x0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + x0.AddArg(x) + x1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + x1.AddArg(x) + y0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + y0.AddArg(y) + y1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + y1.AddArg(y) + x0y0 := b.NewValue0(v.Pos, OpMul32uhilo, types.NewTuple(typ.UInt32, typ.UInt32)) + x0y0.AddArg2(x0, y0) + x0y0Hi := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + x0y0Hi.AddArg(x0y0) + x0y0Lo := b.NewValue0(v.Pos, OpSelect1, typ.UInt32) + x0y0Lo.AddArg(x0y0) + v7 := b.NewValue0(v.Pos, OpInt64Make, typ.UInt64) + v8 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v9 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v10 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v10.AddArg2(x0, y1) + v11 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v11.AddArg2(x1, y0) + v9.AddArg2(v10, v11) + v8.AddArg2(x0y0Hi, v9) + v7.AddArg2(v8, x0y0Lo) + v.AddArgs(x0, x1, y0, y1, x0y0, x0y0Hi, x0y0Lo, v7) + return true + } +} +func rewriteValuedec64_OpMul64uhilo(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Mul64uhilo x y) + // result: (Last x0: (Int64Lo x) x1: (Int64Hi x) y0: (Int64Lo y) y1: (Int64Hi y) x0y0: (Mul32uhilo x0 y0) x0y1: (Mul32uhilo x0 y1) x1y0: (Mul32uhilo x1 y0) x1y1: (Mul32uhilo x1 y1) x0y0Hi: (Select0 x0y0) x0y0Lo: (Select1 x0y0) x0y1Hi: (Select0 x0y1) x0y1Lo: (Select1 x0y1) x1y0Hi: (Select0 x1y0) x1y0Lo: (Select1 x1y0) x1y1Hi: (Select0 x1y1) x1y1Lo: (Select1 x1y1) w1a: (Add32carry x0y0Hi x0y1Lo) w2a: (Add32carrywithcarry x0y1Hi x1y0Hi (Select1 w1a)) w3a: (Add32withcarry x1y1Hi (Const32 [0]) (Select1 w2a)) w1b: (Add32carry x1y0Lo (Select0 w1a)) w2b: (Add32carrywithcarry x1y1Lo (Select0 w2a) (Select1 w1b)) w3b: (Add32withcarry w3a (Const32 [0]) (Select1 w2b)) (MakeTuple (Int64Make w3b (Select0 w2b)) (Int64Make (Select0 w1b) x0y0Lo))) + for { + t := v.Type + x := v_0 + y := v_1 + v.reset(OpLast) + v.Type = t + x0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + x0.AddArg(x) + x1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + x1.AddArg(x) + y0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + y0.AddArg(y) + y1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + y1.AddArg(y) + x0y0 := b.NewValue0(v.Pos, OpMul32uhilo, types.NewTuple(typ.UInt32, typ.UInt32)) + x0y0.AddArg2(x0, y0) + x0y1 := b.NewValue0(v.Pos, OpMul32uhilo, types.NewTuple(typ.UInt32, typ.UInt32)) + x0y1.AddArg2(x0, y1) + x1y0 := b.NewValue0(v.Pos, OpMul32uhilo, types.NewTuple(typ.UInt32, typ.UInt32)) + x1y0.AddArg2(x1, y0) + x1y1 := b.NewValue0(v.Pos, OpMul32uhilo, types.NewTuple(typ.UInt32, typ.UInt32)) + x1y1.AddArg2(x1, y1) + x0y0Hi := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + x0y0Hi.AddArg(x0y0) + x0y0Lo := b.NewValue0(v.Pos, OpSelect1, typ.UInt32) + x0y0Lo.AddArg(x0y0) + x0y1Hi := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + x0y1Hi.AddArg(x0y1) + x0y1Lo := b.NewValue0(v.Pos, OpSelect1, typ.UInt32) + x0y1Lo.AddArg(x0y1) + x1y0Hi := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + x1y0Hi.AddArg(x1y0) + x1y0Lo := b.NewValue0(v.Pos, OpSelect1, typ.UInt32) + x1y0Lo.AddArg(x1y0) + x1y1Hi := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + x1y1Hi.AddArg(x1y1) + x1y1Lo := b.NewValue0(v.Pos, OpSelect1, typ.UInt32) + x1y1Lo.AddArg(x1y1) + w1a := b.NewValue0(v.Pos, OpAdd32carry, types.NewTuple(typ.UInt32, types.TypeFlags)) + w1a.AddArg2(x0y0Hi, x0y1Lo) + w2a := b.NewValue0(v.Pos, OpAdd32carrywithcarry, types.NewTuple(typ.UInt32, types.TypeFlags)) + v18 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v18.AddArg(w1a) + w2a.AddArg3(x0y1Hi, x1y0Hi, v18) + w3a := b.NewValue0(v.Pos, OpAdd32withcarry, typ.UInt32) + v20 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v20.AuxInt = int32ToAuxInt(0) + v21 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v21.AddArg(w2a) + w3a.AddArg3(x1y1Hi, v20, v21) + w1b := b.NewValue0(v.Pos, OpAdd32carry, types.NewTuple(typ.UInt32, types.TypeFlags)) + v23 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + v23.AddArg(w1a) + w1b.AddArg2(x1y0Lo, v23) + w2b := b.NewValue0(v.Pos, OpAdd32carrywithcarry, types.NewTuple(typ.UInt32, types.TypeFlags)) + v25 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + v25.AddArg(w2a) + v26 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v26.AddArg(w1b) + w2b.AddArg3(x1y1Lo, v25, v26) + w3b := b.NewValue0(v.Pos, OpAdd32withcarry, typ.UInt32) + v28 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v28.AddArg(w2b) + w3b.AddArg3(w3a, v20, v28) + v29 := b.NewValue0(v.Pos, OpMakeTuple, types.NewTuple(typ.UInt64, typ.UInt64)) + v30 := b.NewValue0(v.Pos, OpInt64Make, typ.UInt64) + v31 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + v31.AddArg(w2b) + v30.AddArg2(w3b, v31) + v32 := b.NewValue0(v.Pos, OpInt64Make, typ.UInt64) + v33 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + v33.AddArg(w1b) + v32.AddArg2(v33, x0y0Lo) + v29.AddArg2(v30, v32) + v.AddArgs(x0, x1, y0, y1, x0y0, x0y1, x1y0, x1y1, x0y0Hi, x0y0Lo, x0y1Hi, x0y1Lo, x1y0Hi, x1y0Lo, x1y1Hi, x1y1Lo, w1a, w2a, w3a, w1b, w2b, w3b, v29) return true } } @@ -1310,6 +1503,8 @@ func rewriteValuedec64_OpRotateLeft32(v *Value) bool { func rewriteValuedec64_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types // match: (RotateLeft64 x (Int64Make hi lo)) // result: (RotateLeft64 x lo) for { @@ -1322,6 +1517,458 @@ func rewriteValuedec64_OpRotateLeft64(v *Value) bool { v.AddArg2(x, lo) return true } + // match: (RotateLeft64 x (Const64 [c])) + // cond: c&63 == 0 + // result: x + for { + x := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(c&63 == 0) { + break + } + v.copyOf(x) + return true + } + // match: (RotateLeft64 x (Const32 [c])) + // cond: c&63 == 0 + // result: x + for { + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(c&63 == 0) { + break + } + v.copyOf(x) + return true + } + // match: (RotateLeft64 x (Const16 [c])) + // cond: c&63 == 0 + // result: x + for { + x := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(c&63 == 0) { + break + } + v.copyOf(x) + return true + } + // match: (RotateLeft64 x (Const8 [c])) + // cond: c&63 == 0 + // result: x + for { + x := v_0 + if v_1.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1.AuxInt) + if !(c&63 == 0) { + break + } + v.copyOf(x) + return true + } + // match: (RotateLeft64 x (Const64 [c])) + // cond: c&63 == 32 + // result: (Int64Make (Int64Lo x) (Int64Hi x)) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(c&63 == 32) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v1.AddArg(x) + v.AddArg2(v0, v1) + return true + } + // match: (RotateLeft64 x (Const32 [c])) + // cond: c&63 == 32 + // result: (Int64Make (Int64Lo x) (Int64Hi x)) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(c&63 == 32) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v1.AddArg(x) + v.AddArg2(v0, v1) + return true + } + // match: (RotateLeft64 x (Const16 [c])) + // cond: c&63 == 32 + // result: (Int64Make (Int64Lo x) (Int64Hi x)) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(c&63 == 32) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v1.AddArg(x) + v.AddArg2(v0, v1) + return true + } + // match: (RotateLeft64 x (Const8 [c])) + // cond: c&63 == 32 + // result: (Int64Make (Int64Lo x) (Int64Hi x)) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1.AuxInt) + if !(c&63 == 32) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v1.AddArg(x) + v.AddArg2(v0, v1) + return true + } + // match: (RotateLeft64 x (Const64 [c])) + // cond: 0 < c&63 && c&63 < 32 + // result: (Int64Make (Or32 (Lsh32x32 (Int64Hi x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Lo x) (Const32 [int32(32-c&31)]))) (Or32 (Lsh32x32 (Int64Lo x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Hi x) (Const32 [int32(32-c&31)])))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(0 < c&63 && c&63 < 32) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(c & 31)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v5.AddArg(x) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int32ToAuxInt(int32(32 - c&31)) + v4.AddArg2(v5, v6) + v0.AddArg2(v1, v4) + v7 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v8 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v8.AddArg2(v5, v3) + v9 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v9.AddArg2(v2, v6) + v7.AddArg2(v8, v9) + v.AddArg2(v0, v7) + return true + } + // match: (RotateLeft64 x (Const32 [c])) + // cond: 0 < c&63 && c&63 < 32 + // result: (Int64Make (Or32 (Lsh32x32 (Int64Hi x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Lo x) (Const32 [int32(32-c&31)]))) (Or32 (Lsh32x32 (Int64Lo x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Hi x) (Const32 [int32(32-c&31)])))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(0 < c&63 && c&63 < 32) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(c & 31)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v5.AddArg(x) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int32ToAuxInt(int32(32 - c&31)) + v4.AddArg2(v5, v6) + v0.AddArg2(v1, v4) + v7 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v8 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v8.AddArg2(v5, v3) + v9 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v9.AddArg2(v2, v6) + v7.AddArg2(v8, v9) + v.AddArg2(v0, v7) + return true + } + // match: (RotateLeft64 x (Const16 [c])) + // cond: 0 < c&63 && c&63 < 32 + // result: (Int64Make (Or32 (Lsh32x32 (Int64Hi x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Lo x) (Const32 [int32(32-c&31)]))) (Or32 (Lsh32x32 (Int64Lo x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Hi x) (Const32 [int32(32-c&31)])))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(0 < c&63 && c&63 < 32) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(c & 31)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v5.AddArg(x) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int32ToAuxInt(int32(32 - c&31)) + v4.AddArg2(v5, v6) + v0.AddArg2(v1, v4) + v7 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v8 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v8.AddArg2(v5, v3) + v9 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v9.AddArg2(v2, v6) + v7.AddArg2(v8, v9) + v.AddArg2(v0, v7) + return true + } + // match: (RotateLeft64 x (Const8 [c])) + // cond: 0 < c&63 && c&63 < 32 + // result: (Int64Make (Or32 (Lsh32x32 (Int64Hi x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Lo x) (Const32 [int32(32-c&31)]))) (Or32 (Lsh32x32 (Int64Lo x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Hi x) (Const32 [int32(32-c&31)])))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1.AuxInt) + if !(0 < c&63 && c&63 < 32) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(c & 31)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v5.AddArg(x) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int32ToAuxInt(int32(32 - c&31)) + v4.AddArg2(v5, v6) + v0.AddArg2(v1, v4) + v7 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v8 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v8.AddArg2(v5, v3) + v9 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v9.AddArg2(v2, v6) + v7.AddArg2(v8, v9) + v.AddArg2(v0, v7) + return true + } + // match: (RotateLeft64 x (Const64 [c])) + // cond: 32 < c&63 && c&63 < 64 + // result: (Int64Make (Or32 (Lsh32x32 (Int64Lo x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Hi x) (Const32 [int32(32-c&31)]))) (Or32 (Lsh32x32 (Int64Hi x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Lo x) (Const32 [int32(32-c&31)])))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(32 < c&63 && c&63 < 64) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(c & 31)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v5 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v5.AddArg(x) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int32ToAuxInt(int32(32 - c&31)) + v4.AddArg2(v5, v6) + v0.AddArg2(v1, v4) + v7 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v8 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v8.AddArg2(v5, v3) + v9 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v9.AddArg2(v2, v6) + v7.AddArg2(v8, v9) + v.AddArg2(v0, v7) + return true + } + // match: (RotateLeft64 x (Const32 [c])) + // cond: 32 < c&63 && c&63 < 64 + // result: (Int64Make (Or32 (Lsh32x32 (Int64Lo x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Hi x) (Const32 [int32(32-c&31)]))) (Or32 (Lsh32x32 (Int64Hi x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Lo x) (Const32 [int32(32-c&31)])))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(32 < c&63 && c&63 < 64) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(c & 31)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v5 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v5.AddArg(x) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int32ToAuxInt(int32(32 - c&31)) + v4.AddArg2(v5, v6) + v0.AddArg2(v1, v4) + v7 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v8 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v8.AddArg2(v5, v3) + v9 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v9.AddArg2(v2, v6) + v7.AddArg2(v8, v9) + v.AddArg2(v0, v7) + return true + } + // match: (RotateLeft64 x (Const16 [c])) + // cond: 32 < c&63 && c&63 < 64 + // result: (Int64Make (Or32 (Lsh32x32 (Int64Lo x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Hi x) (Const32 [int32(32-c&31)]))) (Or32 (Lsh32x32 (Int64Hi x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Lo x) (Const32 [int32(32-c&31)])))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(32 < c&63 && c&63 < 64) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(c & 31)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v5 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v5.AddArg(x) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int32ToAuxInt(int32(32 - c&31)) + v4.AddArg2(v5, v6) + v0.AddArg2(v1, v4) + v7 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v8 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v8.AddArg2(v5, v3) + v9 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v9.AddArg2(v2, v6) + v7.AddArg2(v8, v9) + v.AddArg2(v0, v7) + return true + } + // match: (RotateLeft64 x (Const8 [c])) + // cond: 32 < c&63 && c&63 < 64 + // result: (Int64Make (Or32 (Lsh32x32 (Int64Lo x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Hi x) (Const32 [int32(32-c&31)]))) (Or32 (Lsh32x32 (Int64Hi x) (Const32 [int32(c&31)])) (Rsh32Ux32 (Int64Lo x) (Const32 [int32(32-c&31)])))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1.AuxInt) + if !(32 < c&63 && c&63 < 64) { + break + } + v.reset(OpInt64Make) + v.Type = t + v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(c & 31)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v5 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + v5.AddArg(x) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int32ToAuxInt(int32(32 - c&31)) + v4.AddArg2(v5, v6) + v0.AddArg2(v1, v4) + v7 := b.NewValue0(v.Pos, OpOr32, typ.UInt32) + v8 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32) + v8.AddArg2(v5, v3) + v9 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32) + v9.AddArg2(v2, v6) + v7.AddArg2(v8, v9) + v.AddArg2(v0, v7) + return true + } return false } func rewriteValuedec64_OpRotateLeft8(v *Value) bool { @@ -2251,6 +2898,34 @@ func rewriteValuedec64_OpRsh8x64(v *Value) bool { return true } } +func rewriteValuedec64_OpSelect0(v *Value) bool { + v_0 := v.Args[0] + // match: (Select0 (MakeTuple x y)) + // result: x + for { + if v_0.Op != OpMakeTuple { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValuedec64_OpSelect1(v *Value) bool { + v_0 := v.Args[0] + // match: (Select1 (MakeTuple x y)) + // result: y + for { + if v_0.Op != OpMakeTuple { + break + } + y := v_0.Args[1] + v.copyOf(y) + return true + } + return false +} func rewriteValuedec64_OpSignExt16to64(v *Value) bool { v_0 := v.Args[0] b := v.Block @@ -2361,29 +3036,33 @@ func rewriteValuedec64_OpSub64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Sub64 x y) - // result: (Int64Make (Sub32withcarry (Int64Hi x) (Int64Hi y) (Select1 (Sub32carry (Int64Lo x) (Int64Lo y)))) (Select0 (Sub32carry (Int64Lo x) (Int64Lo y)))) + // match: (Sub64 x y) + // result: (Last x0: (Int64Lo x) x1: (Int64Hi x) y0: (Int64Lo y) y1: (Int64Hi y) sub: (Sub32carry x0 y0) (Int64Make (Sub32withcarry x1 y1 (Select1 sub)) (Select0 sub))) for { + t := v.Type x := v_0 y := v_1 - v.reset(OpInt64Make) - v0 := b.NewValue0(v.Pos, OpSub32withcarry, typ.Int32) - v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) - v2.AddArg(y) - v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) - v4 := b.NewValue0(v.Pos, OpSub32carry, types.NewTuple(typ.UInt32, types.TypeFlags)) - v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) - v5.AddArg(x) - v6 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) - v6.AddArg(y) - v4.AddArg2(v5, v6) - v3.AddArg(v4) - v0.AddArg3(v1, v2, v3) - v7 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) - v7.AddArg(v4) - v.AddArg2(v0, v7) + v.reset(OpLast) + v.Type = t + x0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + x0.AddArg(x) + x1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + x1.AddArg(x) + y0 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32) + y0.AddArg(y) + y1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32) + y1.AddArg(y) + sub := b.NewValue0(v.Pos, OpSub32carry, types.NewTuple(typ.UInt32, types.TypeFlags)) + sub.AddArg2(x0, y0) + v5 := b.NewValue0(v.Pos, OpInt64Make, typ.UInt64) + v6 := b.NewValue0(v.Pos, OpSub32withcarry, typ.UInt32) + v7 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) + v7.AddArg(sub) + v6.AddArg3(x1, y1, v7) + v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32) + v8.AddArg(sub) + v5.AddArg2(v6, v8) + v.AddArg6(x0, x1, y0, y1, sub, v5) return true } } diff --git a/src/cmd/compile/internal/ssa/rewritedivisible.go b/src/cmd/compile/internal/ssa/rewritedivisible.go new file mode 100644 index 00000000000000..b9c077af0f474b --- /dev/null +++ b/src/cmd/compile/internal/ssa/rewritedivisible.go @@ -0,0 +1,1532 @@ +// Code generated from _gen/divisible.rules using 'go generate'; DO NOT EDIT. + +package ssa + +func rewriteValuedivisible(v *Value) bool { + switch v.Op { + case OpEq16: + return rewriteValuedivisible_OpEq16(v) + case OpEq32: + return rewriteValuedivisible_OpEq32(v) + case OpEq64: + return rewriteValuedivisible_OpEq64(v) + case OpEq8: + return rewriteValuedivisible_OpEq8(v) + case OpNeq16: + return rewriteValuedivisible_OpNeq16(v) + case OpNeq32: + return rewriteValuedivisible_OpNeq32(v) + case OpNeq64: + return rewriteValuedivisible_OpNeq64(v) + case OpNeq8: + return rewriteValuedivisible_OpNeq8(v) + } + return false +} +func rewriteValuedivisible_OpEq16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq16 x (Mul16 (Div16u x (Const16 [c])) (Const16 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Eq16 (And16 x (Const16 [c-1])) (Const16 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul16 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv16u { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst16 || auxIntToInt16(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpAnd16, t) + v1 := b.NewValue0(v.Pos, OpConst16, t) + v1.AuxInt = int16ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst16, t) + v2.AuxInt = int16ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Eq16 x (Mul16 (Div16 x (Const16 [c])) (Const16 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Eq16 (And16 x (Const16 [c-1])) (Const16 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul16 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv16 { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst16 || auxIntToInt16(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpAnd16, t) + v1 := b.NewValue0(v.Pos, OpConst16, t) + v1.AuxInt = int16ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst16, t) + v2.AuxInt = int16ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Eq16 x (Mul16 div:(Div16u x (Const16 [c])) (Const16 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst16 && udivisibleOK16(c) + // result: (Leq16U (RotateLeft16 (Mul16 x (Const16 [int16(udivisible16(c).m)])) (Const16 [int16(16 - udivisible16(c).k)])) (Const16 [int16(udivisible16(c).max)])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul16 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv16u { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(div_1.AuxInt) + if v_1_1.Op != OpConst16 || auxIntToInt16(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst16 && udivisibleOK16(c)) { + continue + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, t) + v1 := b.NewValue0(v.Pos, OpMul16, t) + v2 := b.NewValue0(v.Pos, OpConst16, t) + v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpConst16, t) + v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) + v0.AddArg2(v1, v3) + v4 := b.NewValue0(v.Pos, OpConst16, t) + v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) + v.AddArg2(v0, v4) + return true + } + } + break + } + // match: (Eq16 x (Mul16 div:(Div16 x (Const16 [c])) (Const16 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst16 && sdivisibleOK16(c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 x (Const16 [int16(sdivisible16(c).m)])) (Const16 [int16(sdivisible16(c).a)])) (Const16 [int16(16 - sdivisible16(c).k)])) (Const16 [int16(sdivisible16(c).max)])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul16 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv16 { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(div_1.AuxInt) + if v_1_1.Op != OpConst16 || auxIntToInt16(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst16 && sdivisibleOK16(c)) { + continue + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, t) + v1 := b.NewValue0(v.Pos, OpAdd16, t) + v2 := b.NewValue0(v.Pos, OpMul16, t) + v3 := b.NewValue0(v.Pos, OpConst16, t) + v3.AuxInt = int16ToAuxInt(int16(sdivisible16(c).m)) + v2.AddArg2(x, v3) + v4 := b.NewValue0(v.Pos, OpConst16, t) + v4.AuxInt = int16ToAuxInt(int16(sdivisible16(c).a)) + v1.AddArg2(v2, v4) + v5 := b.NewValue0(v.Pos, OpConst16, t) + v5.AuxInt = int16ToAuxInt(int16(16 - sdivisible16(c).k)) + v0.AddArg2(v1, v5) + v6 := b.NewValue0(v.Pos, OpConst16, t) + v6.AuxInt = int16ToAuxInt(int16(sdivisible16(c).max)) + v.AddArg2(v0, v6) + return true + } + } + break + } + return false +} +func rewriteValuedivisible_OpEq32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq32 x (Mul32 (Div32u x (Const32 [c])) (Const32 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Eq32 (And32 x (Const32 [c-1])) (Const32 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul32 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv32u { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst32 || auxIntToInt32(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpAnd32, t) + v1 := b.NewValue0(v.Pos, OpConst32, t) + v1.AuxInt = int32ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst32, t) + v2.AuxInt = int32ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Eq32 x (Mul32 (Div32 x (Const32 [c])) (Const32 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Eq32 (And32 x (Const32 [c-1])) (Const32 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul32 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv32 { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst32 || auxIntToInt32(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpAnd32, t) + v1 := b.NewValue0(v.Pos, OpConst32, t) + v1.AuxInt = int32ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst32, t) + v2.AuxInt = int32ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Eq32 x (Mul32 div:(Div32u x (Const32 [c])) (Const32 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst32 && udivisibleOK32(c) + // result: (Leq32U (RotateLeft32 (Mul32 x (Const32 [int32(udivisible32(c).m)])) (Const32 [int32(32 - udivisible32(c).k)])) (Const32 [int32(udivisible32(c).max)])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul32 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv32u { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(div_1.AuxInt) + if v_1_1.Op != OpConst32 || auxIntToInt32(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst32 && udivisibleOK32(c)) { + continue + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, t) + v1 := b.NewValue0(v.Pos, OpMul32, t) + v2 := b.NewValue0(v.Pos, OpConst32, t) + v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpConst32, t) + v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) + v0.AddArg2(v1, v3) + v4 := b.NewValue0(v.Pos, OpConst32, t) + v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) + v.AddArg2(v0, v4) + return true + } + } + break + } + // match: (Eq32 x (Mul32 div:(Div32 x (Const32 [c])) (Const32 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst32 && sdivisibleOK32(c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 x (Const32 [int32(sdivisible32(c).m)])) (Const32 [int32(sdivisible32(c).a)])) (Const32 [int32(32 - sdivisible32(c).k)])) (Const32 [int32(sdivisible32(c).max)])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul32 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv32 { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(div_1.AuxInt) + if v_1_1.Op != OpConst32 || auxIntToInt32(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst32 && sdivisibleOK32(c)) { + continue + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, t) + v1 := b.NewValue0(v.Pos, OpAdd32, t) + v2 := b.NewValue0(v.Pos, OpMul32, t) + v3 := b.NewValue0(v.Pos, OpConst32, t) + v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) + v2.AddArg2(x, v3) + v4 := b.NewValue0(v.Pos, OpConst32, t) + v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) + v1.AddArg2(v2, v4) + v5 := b.NewValue0(v.Pos, OpConst32, t) + v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) + v0.AddArg2(v1, v5) + v6 := b.NewValue0(v.Pos, OpConst32, t) + v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) + v.AddArg2(v0, v6) + return true + } + } + break + } + return false +} +func rewriteValuedivisible_OpEq64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq64 x (Mul64 (Div64u x (Const64 [c])) (Const64 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Eq64 (And64 x (Const64 [c-1])) (Const64 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul64 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv64u { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpEq64) + v0 := b.NewValue0(v.Pos, OpAnd64, t) + v1 := b.NewValue0(v.Pos, OpConst64, t) + v1.AuxInt = int64ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst64, t) + v2.AuxInt = int64ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Eq64 x (Mul64 (Div64 x (Const64 [c])) (Const64 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Eq64 (And64 x (Const64 [c-1])) (Const64 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul64 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv64 { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpEq64) + v0 := b.NewValue0(v.Pos, OpAnd64, t) + v1 := b.NewValue0(v.Pos, OpConst64, t) + v1.AuxInt = int64ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst64, t) + v2.AuxInt = int64ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Eq64 x (Mul64 div:(Div64u x (Const64 [c])) (Const64 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst64 && udivisibleOK64(c) + // result: (Leq64U (RotateLeft64 (Mul64 x (Const64 [int64(udivisible64(c).m)])) (Const64 [int64(64 - udivisible64(c).k)])) (Const64 [int64(udivisible64(c).max)])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul64 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv64u { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(div_1.AuxInt) + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst64 && udivisibleOK64(c)) { + continue + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, t) + v1 := b.NewValue0(v.Pos, OpMul64, t) + v2 := b.NewValue0(v.Pos, OpConst64, t) + v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpConst64, t) + v3.AuxInt = int64ToAuxInt(int64(64 - udivisible64(c).k)) + v0.AddArg2(v1, v3) + v4 := b.NewValue0(v.Pos, OpConst64, t) + v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) + v.AddArg2(v0, v4) + return true + } + } + break + } + // match: (Eq64 x (Mul64 div:(Div64 x (Const64 [c])) (Const64 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst64 && sdivisibleOK64(c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 x (Const64 [int64(sdivisible64(c).m)])) (Const64 [int64(sdivisible64(c).a)])) (Const64 [int64(64 - sdivisible64(c).k)])) (Const64 [int64(sdivisible64(c).max)])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul64 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv64 { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(div_1.AuxInt) + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst64 && sdivisibleOK64(c)) { + continue + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, t) + v1 := b.NewValue0(v.Pos, OpAdd64, t) + v2 := b.NewValue0(v.Pos, OpMul64, t) + v3 := b.NewValue0(v.Pos, OpConst64, t) + v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) + v2.AddArg2(x, v3) + v4 := b.NewValue0(v.Pos, OpConst64, t) + v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) + v1.AddArg2(v2, v4) + v5 := b.NewValue0(v.Pos, OpConst64, t) + v5.AuxInt = int64ToAuxInt(int64(64 - sdivisible64(c).k)) + v0.AddArg2(v1, v5) + v6 := b.NewValue0(v.Pos, OpConst64, t) + v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) + v.AddArg2(v0, v6) + return true + } + } + break + } + return false +} +func rewriteValuedivisible_OpEq8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Eq8 (And8 x (Const8 [c-1])) (Const8 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul8 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv8u { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst8 || auxIntToInt8(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpAnd8, t) + v1 := b.NewValue0(v.Pos, OpConst8, t) + v1.AuxInt = int8ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst8, t) + v2.AuxInt = int8ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Eq8 x (Mul8 (Div8 x (Const8 [c])) (Const8 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Eq8 (And8 x (Const8 [c-1])) (Const8 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul8 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv8 { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst8 || auxIntToInt8(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpAnd8, t) + v1 := b.NewValue0(v.Pos, OpConst8, t) + v1.AuxInt = int8ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst8, t) + v2.AuxInt = int8ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Eq8 x (Mul8 div:(Div8u x (Const8 [c])) (Const8 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst8 && udivisibleOK8(c) + // result: (Leq8U (RotateLeft8 (Mul8 x (Const8 [int8(udivisible8(c).m)])) (Const8 [int8(8 - udivisible8(c).k)])) (Const8 [int8(udivisible8(c).max)])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul8 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv8u { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(div_1.AuxInt) + if v_1_1.Op != OpConst8 || auxIntToInt8(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst8 && udivisibleOK8(c)) { + continue + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, t) + v1 := b.NewValue0(v.Pos, OpMul8, t) + v2 := b.NewValue0(v.Pos, OpConst8, t) + v2.AuxInt = int8ToAuxInt(int8(udivisible8(c).m)) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpConst8, t) + v3.AuxInt = int8ToAuxInt(int8(8 - udivisible8(c).k)) + v0.AddArg2(v1, v3) + v4 := b.NewValue0(v.Pos, OpConst8, t) + v4.AuxInt = int8ToAuxInt(int8(udivisible8(c).max)) + v.AddArg2(v0, v4) + return true + } + } + break + } + // match: (Eq8 x (Mul8 div:(Div8 x (Const8 [c])) (Const8 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst8 && sdivisibleOK8(c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 x (Const8 [int8(sdivisible8(c).m)])) (Const8 [int8(sdivisible8(c).a)])) (Const8 [int8(8 - sdivisible8(c).k)])) (Const8 [int8(sdivisible8(c).max)])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul8 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv8 { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(div_1.AuxInt) + if v_1_1.Op != OpConst8 || auxIntToInt8(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst8 && sdivisibleOK8(c)) { + continue + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, t) + v1 := b.NewValue0(v.Pos, OpAdd8, t) + v2 := b.NewValue0(v.Pos, OpMul8, t) + v3 := b.NewValue0(v.Pos, OpConst8, t) + v3.AuxInt = int8ToAuxInt(int8(sdivisible8(c).m)) + v2.AddArg2(x, v3) + v4 := b.NewValue0(v.Pos, OpConst8, t) + v4.AuxInt = int8ToAuxInt(int8(sdivisible8(c).a)) + v1.AddArg2(v2, v4) + v5 := b.NewValue0(v.Pos, OpConst8, t) + v5.AuxInt = int8ToAuxInt(int8(8 - sdivisible8(c).k)) + v0.AddArg2(v1, v5) + v6 := b.NewValue0(v.Pos, OpConst8, t) + v6.AuxInt = int8ToAuxInt(int8(sdivisible8(c).max)) + v.AddArg2(v0, v6) + return true + } + } + break + } + return false +} +func rewriteValuedivisible_OpNeq16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Neq16 x (Mul16 (Div16u x (Const16 [c])) (Const16 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Neq16 (And16 x (Const16 [c-1])) (Const16 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul16 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv16u { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst16 || auxIntToInt16(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Pos, OpAnd16, t) + v1 := b.NewValue0(v.Pos, OpConst16, t) + v1.AuxInt = int16ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst16, t) + v2.AuxInt = int16ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Neq16 x (Mul16 (Div16 x (Const16 [c])) (Const16 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Neq16 (And16 x (Const16 [c-1])) (Const16 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul16 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv16 { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst16 || auxIntToInt16(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Pos, OpAnd16, t) + v1 := b.NewValue0(v.Pos, OpConst16, t) + v1.AuxInt = int16ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst16, t) + v2.AuxInt = int16ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Neq16 x (Mul16 div:(Div16u x (Const16 [c])) (Const16 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst16 && udivisibleOK16(c) + // result: (Less16U (Const16 [int16(udivisible16(c).max)]) (RotateLeft16 (Mul16 x (Const16 [int16(udivisible16(c).m)])) (Const16 [int16(16 - udivisible16(c).k)]))) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul16 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv16u { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(div_1.AuxInt) + if v_1_1.Op != OpConst16 || auxIntToInt16(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst16 && udivisibleOK16(c)) { + continue + } + v.reset(OpLess16U) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) + v1 := b.NewValue0(v.Pos, OpRotateLeft16, t) + v2 := b.NewValue0(v.Pos, OpMul16, t) + v3 := b.NewValue0(v.Pos, OpConst16, t) + v3.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) + v2.AddArg2(x, v3) + v4 := b.NewValue0(v.Pos, OpConst16, t) + v4.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) + v1.AddArg2(v2, v4) + v.AddArg2(v0, v1) + return true + } + } + break + } + // match: (Neq16 x (Mul16 div:(Div16 x (Const16 [c])) (Const16 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst16 && sdivisibleOK16(c) + // result: (Less16U (Const16 [int16(sdivisible16(c).max)]) (RotateLeft16 (Add16 (Mul16 x (Const16 [int16(sdivisible16(c).m)])) (Const16 [int16(sdivisible16(c).a)])) (Const16 [int16(16 - sdivisible16(c).k)]))) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul16 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv16 { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(div_1.AuxInt) + if v_1_1.Op != OpConst16 || auxIntToInt16(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst16 && sdivisibleOK16(c)) { + continue + } + v.reset(OpLess16U) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(int16(sdivisible16(c).max)) + v1 := b.NewValue0(v.Pos, OpRotateLeft16, t) + v2 := b.NewValue0(v.Pos, OpAdd16, t) + v3 := b.NewValue0(v.Pos, OpMul16, t) + v4 := b.NewValue0(v.Pos, OpConst16, t) + v4.AuxInt = int16ToAuxInt(int16(sdivisible16(c).m)) + v3.AddArg2(x, v4) + v5 := b.NewValue0(v.Pos, OpConst16, t) + v5.AuxInt = int16ToAuxInt(int16(sdivisible16(c).a)) + v2.AddArg2(v3, v5) + v6 := b.NewValue0(v.Pos, OpConst16, t) + v6.AuxInt = int16ToAuxInt(int16(16 - sdivisible16(c).k)) + v1.AddArg2(v2, v6) + v.AddArg2(v0, v1) + return true + } + } + break + } + return false +} +func rewriteValuedivisible_OpNeq32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Neq32 x (Mul32 (Div32u x (Const32 [c])) (Const32 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Neq32 (And32 x (Const32 [c-1])) (Const32 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul32 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv32u { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst32 || auxIntToInt32(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpNeq32) + v0 := b.NewValue0(v.Pos, OpAnd32, t) + v1 := b.NewValue0(v.Pos, OpConst32, t) + v1.AuxInt = int32ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst32, t) + v2.AuxInt = int32ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Neq32 x (Mul32 (Div32 x (Const32 [c])) (Const32 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Neq32 (And32 x (Const32 [c-1])) (Const32 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul32 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv32 { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst32 || auxIntToInt32(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpNeq32) + v0 := b.NewValue0(v.Pos, OpAnd32, t) + v1 := b.NewValue0(v.Pos, OpConst32, t) + v1.AuxInt = int32ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst32, t) + v2.AuxInt = int32ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Neq32 x (Mul32 div:(Div32u x (Const32 [c])) (Const32 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst32 && udivisibleOK32(c) + // result: (Less32U (Const32 [int32(udivisible32(c).max)]) (RotateLeft32 (Mul32 x (Const32 [int32(udivisible32(c).m)])) (Const32 [int32(32 - udivisible32(c).k)]))) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul32 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv32u { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(div_1.AuxInt) + if v_1_1.Op != OpConst32 || auxIntToInt32(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst32 && udivisibleOK32(c)) { + continue + } + v.reset(OpLess32U) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) + v1 := b.NewValue0(v.Pos, OpRotateLeft32, t) + v2 := b.NewValue0(v.Pos, OpMul32, t) + v3 := b.NewValue0(v.Pos, OpConst32, t) + v3.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) + v2.AddArg2(x, v3) + v4 := b.NewValue0(v.Pos, OpConst32, t) + v4.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) + v1.AddArg2(v2, v4) + v.AddArg2(v0, v1) + return true + } + } + break + } + // match: (Neq32 x (Mul32 div:(Div32 x (Const32 [c])) (Const32 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst32 && sdivisibleOK32(c) + // result: (Less32U (Const32 [int32(sdivisible32(c).max)]) (RotateLeft32 (Add32 (Mul32 x (Const32 [int32(sdivisible32(c).m)])) (Const32 [int32(sdivisible32(c).a)])) (Const32 [int32(32 - sdivisible32(c).k)]))) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul32 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv32 { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(div_1.AuxInt) + if v_1_1.Op != OpConst32 || auxIntToInt32(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst32 && sdivisibleOK32(c)) { + continue + } + v.reset(OpLess32U) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) + v1 := b.NewValue0(v.Pos, OpRotateLeft32, t) + v2 := b.NewValue0(v.Pos, OpAdd32, t) + v3 := b.NewValue0(v.Pos, OpMul32, t) + v4 := b.NewValue0(v.Pos, OpConst32, t) + v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) + v3.AddArg2(x, v4) + v5 := b.NewValue0(v.Pos, OpConst32, t) + v5.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) + v2.AddArg2(v3, v5) + v6 := b.NewValue0(v.Pos, OpConst32, t) + v6.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) + v1.AddArg2(v2, v6) + v.AddArg2(v0, v1) + return true + } + } + break + } + return false +} +func rewriteValuedivisible_OpNeq64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Neq64 x (Mul64 (Div64u x (Const64 [c])) (Const64 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Neq64 (And64 x (Const64 [c-1])) (Const64 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul64 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv64u { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpNeq64) + v0 := b.NewValue0(v.Pos, OpAnd64, t) + v1 := b.NewValue0(v.Pos, OpConst64, t) + v1.AuxInt = int64ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst64, t) + v2.AuxInt = int64ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Neq64 x (Mul64 (Div64 x (Const64 [c])) (Const64 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Neq64 (And64 x (Const64 [c-1])) (Const64 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul64 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv64 { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpNeq64) + v0 := b.NewValue0(v.Pos, OpAnd64, t) + v1 := b.NewValue0(v.Pos, OpConst64, t) + v1.AuxInt = int64ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst64, t) + v2.AuxInt = int64ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Neq64 x (Mul64 div:(Div64u x (Const64 [c])) (Const64 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst64 && udivisibleOK64(c) + // result: (Less64U (Const64 [int64(udivisible64(c).max)]) (RotateLeft64 (Mul64 x (Const64 [int64(udivisible64(c).m)])) (Const64 [int64(64 - udivisible64(c).k)]))) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul64 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv64u { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(div_1.AuxInt) + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst64 && udivisibleOK64(c)) { + continue + } + v.reset(OpLess64U) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) + v1 := b.NewValue0(v.Pos, OpRotateLeft64, t) + v2 := b.NewValue0(v.Pos, OpMul64, t) + v3 := b.NewValue0(v.Pos, OpConst64, t) + v3.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) + v2.AddArg2(x, v3) + v4 := b.NewValue0(v.Pos, OpConst64, t) + v4.AuxInt = int64ToAuxInt(int64(64 - udivisible64(c).k)) + v1.AddArg2(v2, v4) + v.AddArg2(v0, v1) + return true + } + } + break + } + // match: (Neq64 x (Mul64 div:(Div64 x (Const64 [c])) (Const64 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst64 && sdivisibleOK64(c) + // result: (Less64U (Const64 [int64(sdivisible64(c).max)]) (RotateLeft64 (Add64 (Mul64 x (Const64 [int64(sdivisible64(c).m)])) (Const64 [int64(sdivisible64(c).a)])) (Const64 [int64(64 - sdivisible64(c).k)]))) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul64 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv64 { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(div_1.AuxInt) + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst64 && sdivisibleOK64(c)) { + continue + } + v.reset(OpLess64U) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) + v1 := b.NewValue0(v.Pos, OpRotateLeft64, t) + v2 := b.NewValue0(v.Pos, OpAdd64, t) + v3 := b.NewValue0(v.Pos, OpMul64, t) + v4 := b.NewValue0(v.Pos, OpConst64, t) + v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) + v3.AddArg2(x, v4) + v5 := b.NewValue0(v.Pos, OpConst64, t) + v5.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) + v2.AddArg2(v3, v5) + v6 := b.NewValue0(v.Pos, OpConst64, t) + v6.AuxInt = int64ToAuxInt(int64(64 - sdivisible64(c).k)) + v1.AddArg2(v2, v6) + v.AddArg2(v0, v1) + return true + } + } + break + } + return false +} +func rewriteValuedivisible_OpNeq8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Neq8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Neq8 (And8 x (Const8 [c-1])) (Const8 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul8 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv8u { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst8 || auxIntToInt8(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpNeq8) + v0 := b.NewValue0(v.Pos, OpAnd8, t) + v1 := b.NewValue0(v.Pos, OpConst8, t) + v1.AuxInt = int8ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst8, t) + v2.AuxInt = int8ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Neq8 x (Mul8 (Div8 x (Const8 [c])) (Const8 [c]))) + // cond: x.Op != OpConst64 && isPowerOfTwo(c) + // result: (Neq8 (And8 x (Const8 [c-1])) (Const8 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul8 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpDiv8 { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if v_1_1.Op != OpConst8 || auxIntToInt8(v_1_1.AuxInt) != c || !(x.Op != OpConst64 && isPowerOfTwo(c)) { + continue + } + v.reset(OpNeq8) + v0 := b.NewValue0(v.Pos, OpAnd8, t) + v1 := b.NewValue0(v.Pos, OpConst8, t) + v1.AuxInt = int8ToAuxInt(c - 1) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst8, t) + v2.AuxInt = int8ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } + } + break + } + // match: (Neq8 x (Mul8 div:(Div8u x (Const8 [c])) (Const8 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst8 && udivisibleOK8(c) + // result: (Less8U (Const8 [int8(udivisible8(c).max)]) (RotateLeft8 (Mul8 x (Const8 [int8(udivisible8(c).m)])) (Const8 [int8(8 - udivisible8(c).k)]))) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul8 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv8u { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(div_1.AuxInt) + if v_1_1.Op != OpConst8 || auxIntToInt8(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst8 && udivisibleOK8(c)) { + continue + } + v.reset(OpLess8U) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(int8(udivisible8(c).max)) + v1 := b.NewValue0(v.Pos, OpRotateLeft8, t) + v2 := b.NewValue0(v.Pos, OpMul8, t) + v3 := b.NewValue0(v.Pos, OpConst8, t) + v3.AuxInt = int8ToAuxInt(int8(udivisible8(c).m)) + v2.AddArg2(x, v3) + v4 := b.NewValue0(v.Pos, OpConst8, t) + v4.AuxInt = int8ToAuxInt(int8(8 - udivisible8(c).k)) + v1.AddArg2(v2, v4) + v.AddArg2(v0, v1) + return true + } + } + break + } + // match: (Neq8 x (Mul8 div:(Div8 x (Const8 [c])) (Const8 [c]))) + // cond: div.Uses == 1 && x.Op != OpConst8 && sdivisibleOK8(c) + // result: (Less8U (Const8 [int8(sdivisible8(c).max)]) (RotateLeft8 (Add8 (Mul8 x (Const8 [int8(sdivisible8(c).m)])) (Const8 [int8(sdivisible8(c).a)])) (Const8 [int8(8 - sdivisible8(c).k)]))) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpMul8 { + continue + } + t := v_1.Type + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + div := v_1_0 + if div.Op != OpDiv8 { + continue + } + _ = div.Args[1] + if x != div.Args[0] { + continue + } + div_1 := div.Args[1] + if div_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(div_1.AuxInt) + if v_1_1.Op != OpConst8 || auxIntToInt8(v_1_1.AuxInt) != c || !(div.Uses == 1 && x.Op != OpConst8 && sdivisibleOK8(c)) { + continue + } + v.reset(OpLess8U) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(int8(sdivisible8(c).max)) + v1 := b.NewValue0(v.Pos, OpRotateLeft8, t) + v2 := b.NewValue0(v.Pos, OpAdd8, t) + v3 := b.NewValue0(v.Pos, OpMul8, t) + v4 := b.NewValue0(v.Pos, OpConst8, t) + v4.AuxInt = int8ToAuxInt(int8(sdivisible8(c).m)) + v3.AddArg2(x, v4) + v5 := b.NewValue0(v.Pos, OpConst8, t) + v5.AuxInt = int8ToAuxInt(int8(sdivisible8(c).a)) + v2.AddArg2(v3, v5) + v6 := b.NewValue0(v.Pos, OpConst8, t) + v6.AuxInt = int8ToAuxInt(int8(8 - sdivisible8(c).k)) + v1.AddArg2(v2, v6) + v.AddArg2(v0, v1) + return true + } + } + break + } + return false +} +func rewriteBlockdivisible(b *Block) bool { + return false +} diff --git a/src/cmd/compile/internal/ssa/rewritedivmod.go b/src/cmd/compile/internal/ssa/rewritedivmod.go new file mode 100644 index 00000000000000..1ee39b34f6347e --- /dev/null +++ b/src/cmd/compile/internal/ssa/rewritedivmod.go @@ -0,0 +1,923 @@ +// Code generated from _gen/divmod.rules using 'go generate'; DO NOT EDIT. + +package ssa + +func rewriteValuedivmod(v *Value) bool { + switch v.Op { + case OpDiv16: + return rewriteValuedivmod_OpDiv16(v) + case OpDiv16u: + return rewriteValuedivmod_OpDiv16u(v) + case OpDiv32: + return rewriteValuedivmod_OpDiv32(v) + case OpDiv32u: + return rewriteValuedivmod_OpDiv32u(v) + case OpDiv64: + return rewriteValuedivmod_OpDiv64(v) + case OpDiv64u: + return rewriteValuedivmod_OpDiv64u(v) + case OpDiv8: + return rewriteValuedivmod_OpDiv8(v) + case OpDiv8u: + return rewriteValuedivmod_OpDiv8u(v) + } + return false +} +func rewriteValuedivmod_OpDiv16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div16 n (Const16 [c])) + // cond: isPowerOfTwo(c) + // result: (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [int64(16-log16(c))]))) (Const64 [int64(log16(c))])) + for { + t := v.Type + n := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(isPowerOfTwo(c)) { + break + } + v.reset(OpRsh16x64) + v0 := b.NewValue0(v.Pos, OpAdd16, t) + v1 := b.NewValue0(v.Pos, OpRsh16Ux64, t) + v2 := b.NewValue0(v.Pos, OpRsh16x64, t) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(15) + v2.AddArg2(n, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(int64(16 - log16(c))) + v1.AddArg2(v2, v4) + v0.AddArg2(n, v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64ToAuxInt(int64(log16(c))) + v.AddArg2(v0, v5) + return true + } + // match: (Div16 x (Const16 [c])) + // cond: smagicOK16(c) + // result: (Sub16 (Rsh32x64 (Mul32 (SignExt16to32 x) (Const32 [int32(smagic16(c).m)])) (Const64 [16 + smagic16(c).s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(smagicOK16(c)) { + break + } + v.reset(OpSub16) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh32x64, t) + v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(smagic16(c).m)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(16 + smagic16(c).s) + v0.AddArg2(v1, v4) + v5 := b.NewValue0(v.Pos, OpRsh32x64, t) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64ToAuxInt(31) + v5.AddArg2(v2, v6) + v.AddArg2(v0, v5) + return true + } + return false +} +func rewriteValuedivmod_OpDiv16u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + typ := &b.Func.Config.Types + // match: (Div16u x (Const16 [c])) + // cond: t.IsSigned() && smagicOK16(c) + // result: (Rsh32Ux64 (Mul32 (SignExt16to32 x) (Const32 [int32(smagic16(c).m)])) (Const64 [16 + smagic16(c).s])) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(t.IsSigned() && smagicOK16(c)) { + break + } + v.reset(OpRsh32Ux64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v2.AuxInt = int32ToAuxInt(int32(smagic16(c).m)) + v0.AddArg2(v1, v2) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(16 + smagic16(c).s) + v.AddArg2(v0, v3) + return true + } + // match: (Div16u x (Const16 [c])) + // cond: umagicOK16(c) && config.RegSize == 8 + // result: (Trunc64to16 (Rsh64Ux64 (Mul64 (ZeroExt16to64 x) (Const64 [int64(1<<16 + umagic16(c).m)])) (Const64 [16 + umagic16(c).s]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(umagicOK16(c) && config.RegSize == 8) { + break + } + v.reset(OpTrunc64to16) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(int64(1<<16 + umagic16(c).m)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s) + v0.AddArg2(v1, v4) + v.AddArg(v0) + return true + } + // match: (Div16u x (Const16 [c])) + // cond: umagicOK16(c) && umagic16(c).m&1 == 0 + // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (ZeroExt16to32 x) (Const32 [int32(1<<15 + umagic16(c).m/2)])) (Const64 [16 + umagic16(c).s - 1]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(umagicOK16(c) && umagic16(c).m&1 == 0) { + break + } + v.reset(OpTrunc32to16) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(1<<15 + umagic16(c).m/2)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) + v0.AddArg2(v1, v4) + v.AddArg(v0) + return true + } + // match: (Div16u x (Const16 [c])) + // cond: umagicOK16(c) && config.RegSize == 4 && c&1 == 0 + // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [int32(1<<15 + (umagic16(c).m+1)/2)])) (Const64 [16 + umagic16(c).s - 2]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(umagicOK16(c) && config.RegSize == 4 && c&1 == 0) { + break + } + v.reset(OpTrunc32to16) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v3.AddArg(x) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(1) + v2.AddArg2(v3, v4) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int32ToAuxInt(int32(1<<15 + (umagic16(c).m+1)/2)) + v1.AddArg2(v2, v5) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 2) + v0.AddArg2(v1, v6) + v.AddArg(v0) + return true + } + // match: (Div16u x (Const16 [c])) + // cond: umagicOK16(c) && config.RegSize == 4 + // result: (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) (Mul32 (ZeroExt16to32 x) (Const32 [int32(umagic16(c).m)]))) (Const64 [16 + umagic16(c).s - 1]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1.AuxInt) + if !(umagicOK16(c) && config.RegSize == 4) { + break + } + v.reset(OpTrunc32to16) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpLsh32x64, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v3.AddArg(x) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(16) + v2.AddArg2(v3, v4) + v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int32ToAuxInt(int32(umagic16(c).m)) + v5.AddArg2(v3, v6) + v1.AddArg2(v2, v5) + v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v7.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) + v0.AddArg2(v1, v7) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuedivmod_OpDiv32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + typ := &b.Func.Config.Types + // match: (Div32 n (Const32 [c])) + // cond: isPowerOfTwo(c) + // result: (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [int64(32-log32(c))]))) (Const64 [int64(log32(c))])) + for { + t := v.Type + n := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(isPowerOfTwo(c)) { + break + } + v.reset(OpRsh32x64) + v0 := b.NewValue0(v.Pos, OpAdd32, t) + v1 := b.NewValue0(v.Pos, OpRsh32Ux64, t) + v2 := b.NewValue0(v.Pos, OpRsh32x64, t) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(31) + v2.AddArg2(n, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(int64(32 - log32(c))) + v1.AddArg2(v2, v4) + v0.AddArg2(n, v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64ToAuxInt(int64(log32(c))) + v.AddArg2(v0, v5) + return true + } + // match: (Div32 x (Const32 [c])) + // cond: smagicOK32(c) && config.RegSize == 8 + // result: (Sub32 (Rsh64x64 (Mul64 (SignExt32to64 x) (Const64 [int64(smagic32(c).m)])) (Const64 [32 + smagic32(c).s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(smagicOK32(c) && config.RegSize == 8) { + break + } + v.reset(OpSub32) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh64x64, t) + v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(int64(smagic32(c).m)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(32 + smagic32(c).s) + v0.AddArg2(v1, v4) + v5 := b.NewValue0(v.Pos, OpRsh64x64, t) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64ToAuxInt(63) + v5.AddArg2(v2, v6) + v.AddArg2(v0, v5) + return true + } + // match: (Div32 x (Const32 [c])) + // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 + // result: (Sub32 (Rsh32x64 (Hmul32 x (Const32 [int32(smagic32(c).m/2)])) (Const64 [smagic32(c).s - 1])) (Rsh32x64 x (Const64 [31]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0) { + break + } + v.reset(OpSub32) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh32x64, t) + v1 := b.NewValue0(v.Pos, OpHmul32, t) + v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v2.AuxInt = int32ToAuxInt(int32(smagic32(c).m / 2)) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(smagic32(c).s - 1) + v0.AddArg2(v1, v3) + v4 := b.NewValue0(v.Pos, OpRsh32x64, t) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64ToAuxInt(31) + v4.AddArg2(x, v5) + v.AddArg2(v0, v4) + return true + } + // match: (Div32 x (Const32 [c])) + // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 + // result: (Sub32 (Rsh32x64 (Add32 x (Hmul32 x (Const32 [int32(smagic32(c).m)]))) (Const64 [smagic32(c).s])) (Rsh32x64 x (Const64 [31]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0) { + break + } + v.reset(OpSub32) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh32x64, t) + v1 := b.NewValue0(v.Pos, OpAdd32, t) + v2 := b.NewValue0(v.Pos, OpHmul32, t) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(smagic32(c).m)) + v2.AddArg2(x, v3) + v1.AddArg2(x, v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(smagic32(c).s) + v0.AddArg2(v1, v4) + v5 := b.NewValue0(v.Pos, OpRsh32x64, t) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64ToAuxInt(31) + v5.AddArg2(x, v6) + v.AddArg2(v0, v5) + return true + } + return false +} +func rewriteValuedivmod_OpDiv32u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + typ := &b.Func.Config.Types + // match: (Div32u x (Const32 [c])) + // cond: t.IsSigned() && smagicOK32(c) && config.RegSize == 8 + // result: (Rsh64Ux64 (Mul64 (SignExt32to64 x) (Const64 [int64(smagic32(c).m)])) (Const64 [32 + smagic32(c).s])) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(t.IsSigned() && smagicOK32(c) && config.RegSize == 8) { + break + } + v.reset(OpRsh64Ux64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(int64(smagic32(c).m)) + v0.AddArg2(v1, v2) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(32 + smagic32(c).s) + v.AddArg2(v0, v3) + return true + } + // match: (Div32u x (Const32 [c])) + // cond: t.IsSigned() && smagicOK32(c) && config.RegSize == 4 + // result: (Rsh32Ux64 (Hmul32u x (Const32 [int32(smagic32(c).m)])) (Const64 [smagic32(c).s])) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(t.IsSigned() && smagicOK32(c) && config.RegSize == 4) { + break + } + v.reset(OpRsh32Ux64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v1.AuxInt = int32ToAuxInt(int32(smagic32(c).m)) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(smagic32(c).s) + v.AddArg2(v0, v2) + return true + } + // match: (Div32u x (Const32 [c])) + // cond: umagicOK32(c) && umagic32(c).m&1 == 0 && config.RegSize == 8 + // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (ZeroExt32to64 x) (Const64 [int64(1<<31 + umagic32(c).m/2)])) (Const64 [32 + umagic32(c).s - 1]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(umagicOK32(c) && umagic32(c).m&1 == 0 && config.RegSize == 8) { + break + } + v.reset(OpTrunc64to32) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(int64(1<<31 + umagic32(c).m/2)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) + v0.AddArg2(v1, v4) + v.AddArg(v0) + return true + } + // match: (Div32u x (Const32 [c])) + // cond: umagicOK32(c) && umagic32(c).m&1 == 0 && config.RegSize == 4 + // result: (Rsh32Ux64 (Hmul32u x (Const32 [int32(1<<31 + umagic32(c).m/2)])) (Const64 [umagic32(c).s - 1])) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(umagicOK32(c) && umagic32(c).m&1 == 0 && config.RegSize == 4) { + break + } + v.reset(OpRsh32Ux64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v1.AuxInt = int32ToAuxInt(int32(1<<31 + umagic32(c).m/2)) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(umagic32(c).s - 1) + v.AddArg2(v0, v2) + return true + } + // match: (Div32u x (Const32 [c])) + // cond: umagicOK32(c) && config.RegSize == 8 && c&1 == 0 + // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1])) (Const64 [int64(1<<31 + (umagic32(c).m+1)/2)])) (Const64 [32 + umagic32(c).s - 2]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(umagicOK32(c) && config.RegSize == 8 && c&1 == 0) { + break + } + v.reset(OpTrunc64to32) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) + v3.AddArg(x) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(1) + v2.AddArg2(v3, v4) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64ToAuxInt(int64(1<<31 + (umagic32(c).m+1)/2)) + v1.AddArg2(v2, v5) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 2) + v0.AddArg2(v1, v6) + v.AddArg(v0) + return true + } + // match: (Div32u x (Const32 [c])) + // cond: umagicOK32(c) && config.RegSize == 4 && c&1 == 0 + // result: (Rsh32Ux64 (Hmul32u (Rsh32Ux64 x (Const64 [1])) (Const32 [int32(1<<31 + (umagic32(c).m+1)/2)])) (Const64 [umagic32(c).s - 2])) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(umagicOK32(c) && config.RegSize == 4 && c&1 == 0) { + break + } + v.reset(OpRsh32Ux64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(1) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(1<<31 + (umagic32(c).m+1)/2)) + v0.AddArg2(v1, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(umagic32(c).s - 2) + v.AddArg2(v0, v4) + return true + } + // match: (Div32u x (Const32 [c])) + // cond: umagicOK32(c) && config.RegSize == 8 + // result: (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) (Mul64 (ZeroExt32to64 x) (Const64 [int64(umagic32(c).m)]))) (Const64 [32 + umagic32(c).s - 1]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(umagicOK32(c) && config.RegSize == 8) { + break + } + v.reset(OpTrunc64to32) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) + v3.AddArg(x) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(32) + v2.AddArg2(v3, v4) + v5 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64ToAuxInt(int64(umagic32(c).m)) + v5.AddArg2(v3, v6) + v1.AddArg2(v2, v5) + v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v7.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) + v0.AddArg2(v1, v7) + v.AddArg(v0) + return true + } + // match: (Div32u x (Const32 [c])) + // cond: umagicOK32(c) && config.RegSize == 4 + // result: (Rsh32Ux64 (Avg32u x (Hmul32u x (Const32 [int32(umagic32(c).m)]))) (Const64 [umagic32(c).s - 1])) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1.AuxInt) + if !(umagicOK32(c) && config.RegSize == 4) { + break + } + v.reset(OpRsh32Ux64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v2.AuxInt = int32ToAuxInt(int32(umagic32(c).m)) + v1.AddArg2(x, v2) + v0.AddArg2(x, v1) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(umagic32(c).s - 1) + v.AddArg2(v0, v3) + return true + } + return false +} +func rewriteValuedivmod_OpDiv64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div64 n (Const64 [c])) + // cond: isPowerOfTwo(c) + // result: (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [int64(64-log64(c))]))) (Const64 [int64(log64(c))])) + for { + t := v.Type + n := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(isPowerOfTwo(c)) { + break + } + v.reset(OpRsh64x64) + v0 := b.NewValue0(v.Pos, OpAdd64, t) + v1 := b.NewValue0(v.Pos, OpRsh64Ux64, t) + v2 := b.NewValue0(v.Pos, OpRsh64x64, t) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(63) + v2.AddArg2(n, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(int64(64 - log64(c))) + v1.AddArg2(v2, v4) + v0.AddArg2(n, v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64ToAuxInt(int64(log64(c))) + v.AddArg2(v0, v5) + return true + } + // match: (Div64 x (Const64 [c])) + // cond: smagicOK64(c) && smagic64(c).m&1 == 0 + // result: (Sub64 (Rsh64x64 (Hmul64 x (Const64 [int64(smagic64(c).m/2)])) (Const64 [smagic64(c).s - 1])) (Rsh64x64 x (Const64 [63]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(smagicOK64(c) && smagic64(c).m&1 == 0) { + break + } + v.reset(OpSub64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh64x64, t) + v1 := b.NewValue0(v.Pos, OpHmul64, t) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(int64(smagic64(c).m / 2)) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(smagic64(c).s - 1) + v0.AddArg2(v1, v3) + v4 := b.NewValue0(v.Pos, OpRsh64x64, t) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64ToAuxInt(63) + v4.AddArg2(x, v5) + v.AddArg2(v0, v4) + return true + } + // match: (Div64 x (Const64 [c])) + // cond: smagicOK64(c) && smagic64(c).m&1 != 0 + // result: (Sub64 (Rsh64x64 (Add64 x (Hmul64 x (Const64 [int64(smagic64(c).m)]))) (Const64 [smagic64(c).s])) (Rsh64x64 x (Const64 [63]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(smagicOK64(c) && smagic64(c).m&1 != 0) { + break + } + v.reset(OpSub64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh64x64, t) + v1 := b.NewValue0(v.Pos, OpAdd64, t) + v2 := b.NewValue0(v.Pos, OpHmul64, t) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(int64(smagic64(c).m)) + v2.AddArg2(x, v3) + v1.AddArg2(x, v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(smagic64(c).s) + v0.AddArg2(v1, v4) + v5 := b.NewValue0(v.Pos, OpRsh64x64, t) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64ToAuxInt(63) + v5.AddArg2(x, v6) + v.AddArg2(v0, v5) + return true + } + return false +} +func rewriteValuedivmod_OpDiv64u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div64u x (Const64 [c])) + // cond: t.IsSigned() && smagicOK64(c) + // result: (Rsh64Ux64 (Hmul64u x (Const64 [int64(smagic64(c).m)])) (Const64 [smagic64(c).s])) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(t.IsSigned() && smagicOK64(c)) { + break + } + v.reset(OpRsh64Ux64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v1.AuxInt = int64ToAuxInt(int64(smagic64(c).m)) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(smagic64(c).s) + v.AddArg2(v0, v2) + return true + } + // match: (Div64u x (Const64 [c])) + // cond: umagicOK64(c) && umagic64(c).m&1 == 0 + // result: (Rsh64Ux64 (Hmul64u x (Const64 [int64(1<<63 + umagic64(c).m/2)])) (Const64 [umagic64(c).s - 1])) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(umagicOK64(c) && umagic64(c).m&1 == 0) { + break + } + v.reset(OpRsh64Ux64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v1.AuxInt = int64ToAuxInt(int64(1<<63 + umagic64(c).m/2)) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(umagic64(c).s - 1) + v.AddArg2(v0, v2) + return true + } + // match: (Div64u x (Const64 [c])) + // cond: umagicOK64(c) && c&1 == 0 + // result: (Rsh64Ux64 (Hmul64u (Rsh64Ux64 x (Const64 [1])) (Const64 [int64(1<<63 + (umagic64(c).m+1)/2)])) (Const64 [umagic64(c).s - 2])) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(umagicOK64(c) && c&1 == 0) { + break + } + v.reset(OpRsh64Ux64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(1) + v1.AddArg2(x, v2) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(int64(1<<63 + (umagic64(c).m+1)/2)) + v0.AddArg2(v1, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(umagic64(c).s - 2) + v.AddArg2(v0, v4) + return true + } + // match: (Div64u x (Const64 [c])) + // cond: umagicOK64(c) + // result: (Rsh64Ux64 (Avg64u x (Hmul64u x (Const64 [int64(umagic64(c).m)]))) (Const64 [umagic64(c).s - 1])) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1.AuxInt) + if !(umagicOK64(c)) { + break + } + v.reset(OpRsh64Ux64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(int64(umagic64(c).m)) + v1.AddArg2(x, v2) + v0.AddArg2(x, v1) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(umagic64(c).s - 1) + v.AddArg2(v0, v3) + return true + } + return false +} +func rewriteValuedivmod_OpDiv8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div8 n (Const8 [c])) + // cond: isPowerOfTwo(c) + // result: (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [int64( 8-log8(c))]))) (Const64 [int64(log8(c))])) + for { + t := v.Type + n := v_0 + if v_1.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1.AuxInt) + if !(isPowerOfTwo(c)) { + break + } + v.reset(OpRsh8x64) + v0 := b.NewValue0(v.Pos, OpAdd8, t) + v1 := b.NewValue0(v.Pos, OpRsh8Ux64, t) + v2 := b.NewValue0(v.Pos, OpRsh8x64, t) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64ToAuxInt(7) + v2.AddArg2(n, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(int64(8 - log8(c))) + v1.AddArg2(v2, v4) + v0.AddArg2(n, v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64ToAuxInt(int64(log8(c))) + v.AddArg2(v0, v5) + return true + } + // match: (Div8 x (Const8 [c])) + // cond: smagicOK8(c) + // result: (Sub8 (Rsh32x64 (Mul32 (SignExt8to32 x) (Const32 [int32(smagic8(c).m)])) (Const64 [8 + smagic8(c).s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1.AuxInt) + if !(smagicOK8(c)) { + break + } + v.reset(OpSub8) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh32x64, t) + v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(smagic8(c).m)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(8 + smagic8(c).s) + v0.AddArg2(v1, v4) + v5 := b.NewValue0(v.Pos, OpRsh32x64, t) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64ToAuxInt(31) + v5.AddArg2(v2, v6) + v.AddArg2(v0, v5) + return true + } + return false +} +func rewriteValuedivmod_OpDiv8u(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div8u x (Const8 [c])) + // cond: umagicOK8(c) + // result: (Trunc32to8 (Rsh32Ux64 (Mul32 (ZeroExt8to32 x) (Const32 [int32(1<<8 + umagic8(c).m)])) (Const64 [8 + umagic8(c).s]))) + for { + t := v.Type + x := v_0 + if v_1.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1.AuxInt) + if !(umagicOK8(c)) { + break + } + v.reset(OpTrunc32to8) + v.Type = t + v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) + v2.AddArg(x) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(int32(1<<8 + umagic8(c).m)) + v1.AddArg2(v2, v3) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64ToAuxInt(8 + umagic8(c).s) + v0.AddArg2(v1, v4) + v.AddArg(v0) + return true + } + return false +} +func rewriteBlockdivmod(b *Block) bool { + return false +} diff --git a/src/cmd/compile/internal/ssa/rewritegeneric.go b/src/cmd/compile/internal/ssa/rewritegeneric.go index 79c444a86b29df..83adb5397f8437 100644 --- a/src/cmd/compile/internal/ssa/rewritegeneric.go +++ b/src/cmd/compile/internal/ssa/rewritegeneric.go @@ -224,6 +224,8 @@ func rewriteValuegeneric(v *Value) bool { return rewriteValuegeneric_OpLsh8x64(v) case OpLsh8x8: return rewriteValuegeneric_OpLsh8x8(v) + case OpMemEq: + return rewriteValuegeneric_OpMemEq(v) case OpMod16: return rewriteValuegeneric_OpMod16(v) case OpMod16u: @@ -551,6 +553,19 @@ func rewriteValuegeneric_OpAdd16(v *Value) bool { } break } + // match: (Add16 x x) + // result: (Lsh16x64 x (Const64 [1])) + for { + x := v_0 + if x != v_1 { + break + } + v.reset(OpLsh16x64) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) + v0.AuxInt = int64ToAuxInt(1) + v.AddArg2(x, v0) + return true + } // match: (Add16 (Const16 [0]) x) // result: x for { @@ -1164,6 +1179,19 @@ func rewriteValuegeneric_OpAdd32(v *Value) bool { } break } + // match: (Add32 x x) + // result: (Lsh32x64 x (Const64 [1])) + for { + x := v_0 + if x != v_1 { + break + } + v.reset(OpLsh32x64) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) + v0.AuxInt = int64ToAuxInt(1) + v.AddArg2(x, v0) + return true + } // match: (Add32 (Const32 [0]) x) // result: x for { @@ -1804,6 +1832,19 @@ func rewriteValuegeneric_OpAdd64(v *Value) bool { } break } + // match: (Add64 x x) + // result: (Lsh64x64 x (Const64 [1])) + for { + x := v_0 + if x != v_1 { + break + } + v.reset(OpLsh64x64) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) + v0.AuxInt = int64ToAuxInt(1) + v.AddArg2(x, v0) + return true + } // match: (Add64 (Const64 [0]) x) // result: x for { @@ -2482,6 +2523,19 @@ func rewriteValuegeneric_OpAdd8(v *Value) bool { } break } + // match: (Add8 x x) + // result: (Lsh8x64 x (Const64 [1])) + for { + x := v_0 + if x != v_1 { + break + } + v.reset(OpLsh8x64) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) + v0.AuxInt = int64ToAuxInt(1) + v.AddArg2(x, v0) + return true + } // match: (Add8 (Const8 [0]) x) // result: x for { @@ -3115,6 +3169,27 @@ func rewriteValuegeneric_OpAnd16(v *Value) bool { } break } + // match: (And16 x (Or16 x y)) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpOr16 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if x != v_1_0 { + continue + } + v.copyOf(x) + return true + } + } + break + } // match: (And16 (Const16 [m]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c >= int64(16-ntz16(m)) // result: (Const16 [0]) @@ -3351,6 +3426,27 @@ func rewriteValuegeneric_OpAnd32(v *Value) bool { } break } + // match: (And32 x (Or32 x y)) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpOr32 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if x != v_1_0 { + continue + } + v.copyOf(x) + return true + } + } + break + } // match: (And32 (Const32 [m]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c >= int64(32-ntz32(m)) // result: (Const32 [0]) @@ -3587,6 +3683,27 @@ func rewriteValuegeneric_OpAnd64(v *Value) bool { } break } + // match: (And64 x (Or64 x y)) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpOr64 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if x != v_1_0 { + continue + } + v.copyOf(x) + return true + } + } + break + } // match: (And64 (Const64 [m]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c >= int64(64-ntz64(m)) // result: (Const64 [0]) @@ -3823,6 +3940,27 @@ func rewriteValuegeneric_OpAnd8(v *Value) bool { } break } + // match: (And8 x (Or8 x y)) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpOr8 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if x != v_1_0 { + continue + } + v.copyOf(x) + return true + } + } + break + } // match: (And8 (Const8 [m]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c >= int64(8-ntz8(m)) // result: (Const8 [0]) @@ -5332,6 +5470,182 @@ func rewriteValuegeneric_OpAndB(v *Value) bool { } break } + // match: (AndB (Neq64 x cv:(Const64 [c])) (Neq64 x (Const64 [d]))) + // cond: c|d == c && oneBit(c^d) + // result: (Neq64 (Or64 x (Const64 [c^d])) cv) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpNeq64 { + continue + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { + x := v_0_0 + cv := v_0_1 + if cv.Op != OpConst64 { + continue + } + c := auxIntToInt64(cv.AuxInt) + if v_1.Op != OpNeq64 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { + if x != v_1_0 || v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c|d == c && oneBit(c^d)) { + continue + } + v.reset(OpNeq64) + v0 := b.NewValue0(v.Pos, OpOr64, x.Type) + v1 := b.NewValue0(v.Pos, OpConst64, x.Type) + v1.AuxInt = int64ToAuxInt(c ^ d) + v0.AddArg2(x, v1) + v.AddArg2(v0, cv) + return true + } + } + } + break + } + // match: (AndB (Neq32 x cv:(Const32 [c])) (Neq32 x (Const32 [d]))) + // cond: c|d == c && oneBit(c^d) + // result: (Neq32 (Or32 x (Const32 [c^d])) cv) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpNeq32 { + continue + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { + x := v_0_0 + cv := v_0_1 + if cv.Op != OpConst32 { + continue + } + c := auxIntToInt32(cv.AuxInt) + if v_1.Op != OpNeq32 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { + if x != v_1_0 || v_1_1.Op != OpConst32 { + continue + } + d := auxIntToInt32(v_1_1.AuxInt) + if !(c|d == c && oneBit(c^d)) { + continue + } + v.reset(OpNeq32) + v0 := b.NewValue0(v.Pos, OpOr32, x.Type) + v1 := b.NewValue0(v.Pos, OpConst32, x.Type) + v1.AuxInt = int32ToAuxInt(c ^ d) + v0.AddArg2(x, v1) + v.AddArg2(v0, cv) + return true + } + } + } + break + } + // match: (AndB (Neq16 x cv:(Const16 [c])) (Neq16 x (Const16 [d]))) + // cond: c|d == c && oneBit(c^d) + // result: (Neq16 (Or16 x (Const16 [c^d])) cv) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpNeq16 { + continue + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { + x := v_0_0 + cv := v_0_1 + if cv.Op != OpConst16 { + continue + } + c := auxIntToInt16(cv.AuxInt) + if v_1.Op != OpNeq16 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { + if x != v_1_0 || v_1_1.Op != OpConst16 { + continue + } + d := auxIntToInt16(v_1_1.AuxInt) + if !(c|d == c && oneBit(c^d)) { + continue + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Pos, OpOr16, x.Type) + v1 := b.NewValue0(v.Pos, OpConst16, x.Type) + v1.AuxInt = int16ToAuxInt(c ^ d) + v0.AddArg2(x, v1) + v.AddArg2(v0, cv) + return true + } + } + } + break + } + // match: (AndB (Neq8 x cv:(Const8 [c])) (Neq8 x (Const8 [d]))) + // cond: c|d == c && oneBit(c^d) + // result: (Neq8 (Or8 x (Const8 [c^d])) cv) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpNeq8 { + continue + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { + x := v_0_0 + cv := v_0_1 + if cv.Op != OpConst8 { + continue + } + c := auxIntToInt8(cv.AuxInt) + if v_1.Op != OpNeq8 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { + if x != v_1_0 || v_1_1.Op != OpConst8 { + continue + } + d := auxIntToInt8(v_1_1.AuxInt) + if !(c|d == c && oneBit(c^d)) { + continue + } + v.reset(OpNeq8) + v0 := b.NewValue0(v.Pos, OpOr8, x.Type) + v1 := b.NewValue0(v.Pos, OpConst8, x.Type) + v1.AuxInt = int8ToAuxInt(c ^ d) + v0.AddArg2(x, v1) + v.AddArg2(v0, cv) + return true + } + } + } + break + } return false } func rewriteValuegeneric_OpArraySelect(v *Value) bool { @@ -5734,221 +6048,613 @@ func rewriteValuegeneric_OpCondSelect(v *Value) bool { v.copyOf(x) return true } - // match: (CondSelect (Add8 x (Const8 [1])) x bool) - // cond: config.arch != "arm64" - // result: (Add8 x (CvtBoolToUint8 bool)) + // match: (CondSelect op:(Add8 x c:(Const8)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Add8 x (Mul8 c (CvtBoolToUint8 bool))) for { - if v_0.Op != OpAdd8 { + op := v_0 + if op.Op != OpAdd8 { break } - t := v_0.Type - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - if v_0_1.Op != OpConst8 || auxIntToInt8(v_0_1.AuxInt) != 1 || x != v_1 { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst8 || x != v_1 { continue } bool := v_2 - if !(config.arch != "arm64") { + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { continue } v.reset(OpAdd8) - v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, t) - v0.AddArg(bool) + v0 := b.NewValue0(v.Pos, OpMul8, t) + v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, t) + v1.AddArg(bool) + v0.AddArg2(c, v1) v.AddArg2(x, v0) return true } break } - // match: (CondSelect (Add64 x (Const64 [1])) x bool) - // cond: config.arch != "arm64" - // result: (Add64 x (ZeroExt8to64 (CvtBoolToUint8 bool))) + // match: (CondSelect op:(Add64 x c:(Const64)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Add64 x (Mul64 c (ZeroExt8to64 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpAdd64 { + op := v_0 + if op.Op != OpAdd64 { break } - t := v_0.Type - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 1 || x != v_1 { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst64 || x != v_1 { continue } bool := v_2 - if !(config.arch != "arm64") { + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { continue } v.reset(OpAdd64) - v0 := b.NewValue0(v.Pos, OpZeroExt8to64, t) - v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) - v1.AddArg(bool) - v0.AddArg(v1) + v0 := b.NewValue0(v.Pos, OpMul64, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to64, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) v.AddArg2(x, v0) return true } break } - // match: (CondSelect (Add32 x (Const32 [1])) x bool) - // cond: config.arch != "arm64" - // result: (Add32 x (ZeroExt8to32 (CvtBoolToUint8 bool))) + // match: (CondSelect op:(Add32 x c:(Const32)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Add32 x (Mul32 c (ZeroExt8to32 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpAdd32 { + op := v_0 + if op.Op != OpAdd32 { break } - t := v_0.Type - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - if v_0_1.Op != OpConst32 || auxIntToInt32(v_0_1.AuxInt) != 1 || x != v_1 { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst32 || x != v_1 { continue } bool := v_2 - if !(config.arch != "arm64") { + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { continue } v.reset(OpAdd32) - v0 := b.NewValue0(v.Pos, OpZeroExt8to32, t) - v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) - v1.AddArg(bool) - v0.AddArg(v1) + v0 := b.NewValue0(v.Pos, OpMul32, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to32, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) v.AddArg2(x, v0) return true } break } - // match: (CondSelect (Add16 x (Const16 [1])) x bool) - // cond: config.arch != "arm64" - // result: (Add16 x (ZeroExt8to16 (CvtBoolToUint8 bool))) + // match: (CondSelect op:(Add16 x c:(Const16)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Add16 x (Mul16 c (ZeroExt8to16 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpAdd16 { + op := v_0 + if op.Op != OpAdd16 { break } - t := v_0.Type - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - if v_0_1.Op != OpConst16 || auxIntToInt16(v_0_1.AuxInt) != 1 || x != v_1 { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst16 || x != v_1 { continue } bool := v_2 - if !(config.arch != "arm64") { + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { continue } v.reset(OpAdd16) - v0 := b.NewValue0(v.Pos, OpZeroExt8to16, t) - v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) - v1.AddArg(bool) - v0.AddArg(v1) + v0 := b.NewValue0(v.Pos, OpMul16, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to16, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) v.AddArg2(x, v0) return true } break } - // match: (CondSelect (Add8 x (Const8 [-1])) x bool) - // result: (Sub8 x (CvtBoolToUint8 bool)) + // match: (CondSelect x op:(Add8 x c:(Const8)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Add8 x (Mul8 c (CvtBoolToUint8 (Not bool)))) for { - if v_0.Op != OpAdd8 { + x := v_0 + op := v_1 + if op.Op != OpAdd8 { break } - t := v_0.Type - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - if v_0_1.Op != OpConst8 || auxIntToInt8(v_0_1.AuxInt) != -1 || x != v_1 { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst8 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpAdd8) + v0 := b.NewValue0(v.Pos, OpMul8, t) + v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, t) + v2 := b.NewValue0(v.Pos, OpNot, bool.Type) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true + } + break + } + // match: (CondSelect x op:(Add64 x c:(Const64)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Add64 x (Mul64 c (ZeroExt8to64 (CvtBoolToUint8 (Not bool))))) + for { + x := v_0 + op := v_1 + if op.Op != OpAdd64 { + break + } + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst64 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpAdd64) + v0 := b.NewValue0(v.Pos, OpMul64, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to64, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3 := b.NewValue0(v.Pos, OpNot, bool.Type) + v3.AddArg(bool) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true + } + break + } + // match: (CondSelect x op:(Add32 x c:(Const32)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Add32 x (Mul32 c (ZeroExt8to32 (CvtBoolToUint8 (Not bool))))) + for { + x := v_0 + op := v_1 + if op.Op != OpAdd32 { + break + } + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst32 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpAdd32) + v0 := b.NewValue0(v.Pos, OpMul32, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to32, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3 := b.NewValue0(v.Pos, OpNot, bool.Type) + v3.AddArg(bool) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true + } + break + } + // match: (CondSelect x op:(Add16 x c:(Const16)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Add16 x (Mul16 c (ZeroExt8to16 (CvtBoolToUint8 (Not bool))))) + for { + x := v_0 + op := v_1 + if op.Op != OpAdd16 { + break + } + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst16 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpAdd16) + v0 := b.NewValue0(v.Pos, OpMul16, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to16, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3 := b.NewValue0(v.Pos, OpNot, bool.Type) + v3.AddArg(bool) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true + } + break + } + // match: (CondSelect op:(Add8 x c:(Const8 [consT])) x bool) + // cond: !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) + // result: (Sub8 x (Mul8 (Const8 [-consT]) (CvtBoolToUint8 bool))) + for { + op := v_0 + if op.Op != OpAdd8 { + break + } + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst8 { + continue + } + consT := auxIntToInt8(c.AuxInt) + if x != v_1 { continue } bool := v_2 + if !(!rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt)) { + continue + } v.reset(OpSub8) - v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, t) - v0.AddArg(bool) + v0 := b.NewValue0(v.Pos, OpMul8, t) + v1 := b.NewValue0(v.Pos, OpConst8, t) + v1.AuxInt = int8ToAuxInt(-consT) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, t) + v2.AddArg(bool) + v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } break } - // match: (CondSelect (Add64 x (Const64 [-1])) x bool) - // result: (Sub64 x (ZeroExt8to64 (CvtBoolToUint8 bool))) + // match: (CondSelect op:(Add64 x c:(Const64 [consT])) x bool) + // cond: !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) + // result: (Sub64 x (Mul64 (Const64 [-consT]) (ZeroExt8to64 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpAdd64 { + op := v_0 + if op.Op != OpAdd64 { break } - t := v_0.Type - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != -1 || x != v_1 { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst64 { + continue + } + consT := auxIntToInt64(c.AuxInt) + if x != v_1 { continue } bool := v_2 + if !(!rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt)) { + continue + } v.reset(OpSub64) - v0 := b.NewValue0(v.Pos, OpZeroExt8to64, t) - v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) - v1.AddArg(bool) - v0.AddArg(v1) + v0 := b.NewValue0(v.Pos, OpMul64, t) + v1 := b.NewValue0(v.Pos, OpConst64, t) + v1.AuxInt = int64ToAuxInt(-consT) + v2 := b.NewValue0(v.Pos, OpZeroExt8to64, t) + v3 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3.AddArg(bool) + v2.AddArg(v3) + v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } break } - // match: (CondSelect (Add32 x (Const32 [-1])) x bool) - // result: (Sub32 x (ZeroExt8to32 (CvtBoolToUint8 bool))) + // match: (CondSelect op:(Add32 x c:(Const32 [consT])) x bool) + // cond: !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) + // result: (Sub32 x (Mul32 (Const32 [-consT]) (ZeroExt8to32 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpAdd32 { + op := v_0 + if op.Op != OpAdd32 { break } - t := v_0.Type - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - if v_0_1.Op != OpConst32 || auxIntToInt32(v_0_1.AuxInt) != -1 || x != v_1 { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst32 { + continue + } + consT := auxIntToInt32(c.AuxInt) + if x != v_1 { continue } bool := v_2 + if !(!rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt)) { + continue + } v.reset(OpSub32) - v0 := b.NewValue0(v.Pos, OpZeroExt8to32, t) - v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) - v1.AddArg(bool) - v0.AddArg(v1) + v0 := b.NewValue0(v.Pos, OpMul32, t) + v1 := b.NewValue0(v.Pos, OpConst32, t) + v1.AuxInt = int32ToAuxInt(-consT) + v2 := b.NewValue0(v.Pos, OpZeroExt8to32, t) + v3 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3.AddArg(bool) + v2.AddArg(v3) + v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } break } - // match: (CondSelect (Add16 x (Const16 [-1])) x bool) - // result: (Sub16 x (ZeroExt8to16 (CvtBoolToUint8 bool))) + // match: (CondSelect op:(Add16 x c:(Const16 [consT])) x bool) + // cond: !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) + // result: (Sub16 x (Mul16 (Const16 [-consT]) (ZeroExt8to16 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpAdd16 { + op := v_0 + if op.Op != OpAdd16 { break } - t := v_0.Type - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - if v_0_1.Op != OpConst16 || auxIntToInt16(v_0_1.AuxInt) != -1 || x != v_1 { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst16 { + continue + } + consT := auxIntToInt16(c.AuxInt) + if x != v_1 { continue } bool := v_2 + if !(!rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt)) { + continue + } v.reset(OpSub16) - v0 := b.NewValue0(v.Pos, OpZeroExt8to16, t) - v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) - v1.AddArg(bool) - v0.AddArg(v1) + v0 := b.NewValue0(v.Pos, OpMul16, t) + v1 := b.NewValue0(v.Pos, OpConst16, t) + v1.AuxInt = int16ToAuxInt(-consT) + v2 := b.NewValue0(v.Pos, OpZeroExt8to16, t) + v3 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3.AddArg(bool) + v2.AddArg(v3) + v0.AddArg2(v1, v2) + v.AddArg2(x, v0) + return true + } + break + } + // match: (CondSelect x op:(Add8 x c:(Const8 [consT])) bool) + // cond: !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) + // result: (Sub8 x (Mul8 (Const8 [-consT]) (CvtBoolToUint8 (Not bool)))) + for { + x := v_0 + op := v_1 + if op.Op != OpAdd8 { + break + } + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst8 { + continue + } + consT := auxIntToInt8(c.AuxInt) + bool := v_2 + if !(!rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt)) { + continue + } + v.reset(OpSub8) + v0 := b.NewValue0(v.Pos, OpMul8, t) + v1 := b.NewValue0(v.Pos, OpConst8, t) + v1.AuxInt = int8ToAuxInt(-consT) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, t) + v3 := b.NewValue0(v.Pos, OpNot, bool.Type) + v3.AddArg(bool) + v2.AddArg(v3) + v0.AddArg2(v1, v2) + v.AddArg2(x, v0) + return true + } + break + } + // match: (CondSelect x op:(Add64 x c:(Const64 [consT])) bool) + // cond: !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) + // result: (Sub64 x (Mul64 (Const64 [-consT]) (ZeroExt8to64 (CvtBoolToUint8 (Not bool))))) + for { + x := v_0 + op := v_1 + if op.Op != OpAdd64 { + break + } + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst64 { + continue + } + consT := auxIntToInt64(c.AuxInt) + bool := v_2 + if !(!rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt)) { + continue + } + v.reset(OpSub64) + v0 := b.NewValue0(v.Pos, OpMul64, t) + v1 := b.NewValue0(v.Pos, OpConst64, t) + v1.AuxInt = int64ToAuxInt(-consT) + v2 := b.NewValue0(v.Pos, OpZeroExt8to64, t) + v3 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v4 := b.NewValue0(v.Pos, OpNot, bool.Type) + v4.AddArg(bool) + v3.AddArg(v4) + v2.AddArg(v3) + v0.AddArg2(v1, v2) + v.AddArg2(x, v0) + return true + } + break + } + // match: (CondSelect x op:(Add32 x c:(Const32 [consT])) bool) + // cond: !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) + // result: (Sub32 x (Mul32 (Const32 [-consT]) (ZeroExt8to32 (CvtBoolToUint8 (Not bool))))) + for { + x := v_0 + op := v_1 + if op.Op != OpAdd32 { + break + } + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst32 { + continue + } + consT := auxIntToInt32(c.AuxInt) + bool := v_2 + if !(!rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt)) { + continue + } + v.reset(OpSub32) + v0 := b.NewValue0(v.Pos, OpMul32, t) + v1 := b.NewValue0(v.Pos, OpConst32, t) + v1.AuxInt = int32ToAuxInt(-consT) + v2 := b.NewValue0(v.Pos, OpZeroExt8to32, t) + v3 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v4 := b.NewValue0(v.Pos, OpNot, bool.Type) + v4.AddArg(bool) + v3.AddArg(v4) + v2.AddArg(v3) + v0.AddArg2(v1, v2) + v.AddArg2(x, v0) + return true + } + break + } + // match: (CondSelect x op:(Add16 x c:(Const16 [consT])) bool) + // cond: !rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt) + // result: (Sub16 x (Mul16 (Const16 [-consT]) (ZeroExt8to16 (CvtBoolToUint8 (Not bool))))) + for { + x := v_0 + op := v_1 + if op.Op != OpAdd16 { + break + } + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst16 { + continue + } + consT := auxIntToInt16(c.AuxInt) + bool := v_2 + if !(!rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) && rewriteCondSelectIntoMath(config, addToSub(op.Op), -c.AuxInt)) { + continue + } + v.reset(OpSub16) + v0 := b.NewValue0(v.Pos, OpMul16, t) + v1 := b.NewValue0(v.Pos, OpConst16, t) + v1.AuxInt = int16ToAuxInt(-consT) + v2 := b.NewValue0(v.Pos, OpZeroExt8to16, t) + v3 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v4 := b.NewValue0(v.Pos, OpNot, bool.Type) + v4.AddArg(bool) + v3.AddArg(v4) + v2.AddArg(v3) + v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } @@ -6034,70 +6740,170 @@ func rewriteValuegeneric_OpCondSelect(v *Value) bool { v.AddArg2(x, v0) return true } - // match: (CondSelect (Rsh64x64 x (Const64 [1])) x bool) - // result: (Rsh64x8 [true] x (CvtBoolToUint8 bool)) + // match: (CondSelect x (Lsh64x64 x (Const64 [1])) bool) + // result: (Lsh64x8 [true] x (CvtBoolToUint8 (Not bool))) for { - if v_0.Op != OpRsh64x64 { + x := v_0 + if v_1.Op != OpLsh64x64 { break } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 1 || x != v_1 { + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { break } bool := v_2 - v.reset(OpRsh64x8) + v.reset(OpLsh64x8) v.AuxInt = boolToAuxInt(true) v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) - v0.AddArg(bool) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) + v0.AddArg(v1) v.AddArg2(x, v0) return true } - // match: (CondSelect (Rsh32x64 x (Const64 [1])) x bool) - // result: (Rsh32x8 [true] x (CvtBoolToUint8 bool)) + // match: (CondSelect x (Lsh32x64 x (Const64 [1])) bool) + // result: (Lsh32x8 [true] x (CvtBoolToUint8 (Not bool))) for { - if v_0.Op != OpRsh32x64 { + x := v_0 + if v_1.Op != OpLsh32x64 { break } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 1 || x != v_1 { + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { break } bool := v_2 - v.reset(OpRsh32x8) + v.reset(OpLsh32x8) v.AuxInt = boolToAuxInt(true) v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) - v0.AddArg(bool) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) + v0.AddArg(v1) v.AddArg2(x, v0) return true } - // match: (CondSelect (Rsh16x64 x (Const64 [1])) x bool) - // result: (Rsh16x8 [true] x (CvtBoolToUint8 bool)) + // match: (CondSelect x (Lsh16x64 x (Const64 [1])) bool) + // result: (Lsh16x8 [true] x (CvtBoolToUint8 (Not bool))) for { - if v_0.Op != OpRsh16x64 { + x := v_0 + if v_1.Op != OpLsh16x64 { break } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 1 || x != v_1 { + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { break } bool := v_2 - v.reset(OpRsh16x8) + v.reset(OpLsh16x8) v.AuxInt = boolToAuxInt(true) v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) - v0.AddArg(bool) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) + v0.AddArg(v1) v.AddArg2(x, v0) return true } - // match: (CondSelect (Rsh8x64 x (Const64 [1])) x bool) - // result: (Rsh8x8 [true] x (CvtBoolToUint8 bool)) + // match: (CondSelect x (Lsh8x64 x (Const64 [1])) bool) + // result: (Lsh8x8 [true] x (CvtBoolToUint8 (Not bool))) for { - if v_0.Op != OpRsh8x64 { + x := v_0 + if v_1.Op != OpLsh8x64 { + break + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { + break + } + bool := v_2 + v.reset(OpLsh8x8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } + // match: (CondSelect (Rsh64x64 x (Const64 [1])) x bool) + // result: (Rsh64x8 [true] x (CvtBoolToUint8 bool)) + for { + if v_0.Op != OpRsh64x64 { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 1 || x != v_1 { + break + } + bool := v_2 + v.reset(OpRsh64x8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v0.AddArg(bool) + v.AddArg2(x, v0) + return true + } + // match: (CondSelect (Rsh32x64 x (Const64 [1])) x bool) + // result: (Rsh32x8 [true] x (CvtBoolToUint8 bool)) + for { + if v_0.Op != OpRsh32x64 { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 1 || x != v_1 { + break + } + bool := v_2 + v.reset(OpRsh32x8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v0.AddArg(bool) + v.AddArg2(x, v0) + return true + } + // match: (CondSelect (Rsh16x64 x (Const64 [1])) x bool) + // result: (Rsh16x8 [true] x (CvtBoolToUint8 bool)) + for { + if v_0.Op != OpRsh16x64 { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 1 || x != v_1 { + break + } + bool := v_2 + v.reset(OpRsh16x8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v0.AddArg(bool) + v.AddArg2(x, v0) + return true + } + // match: (CondSelect (Rsh8x64 x (Const64 [1])) x bool) + // result: (Rsh8x8 [true] x (CvtBoolToUint8 bool)) + for { + if v_0.Op != OpRsh8x64 { break } _ = v_0.Args[1] @@ -6194,549 +7000,1325 @@ func rewriteValuegeneric_OpCondSelect(v *Value) bool { v.AddArg2(x, v0) return true } - return false -} -func rewriteValuegeneric_OpConstInterface(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ConstInterface) - // result: (IMake (ConstNil ) (ConstNil )) - for { - v.reset(OpIMake) - v0 := b.NewValue0(v.Pos, OpConstNil, typ.Uintptr) - v1 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) - v.AddArg2(v0, v1) - return true - } -} -func rewriteValuegeneric_OpConstSlice(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (ConstSlice) - // cond: config.PtrSize == 4 - // result: (SliceMake (ConstNil ) (Const32 [0]) (Const32 [0])) + // match: (CondSelect x (Rsh64x64 x (Const64 [1])) bool) + // result: (Rsh64x8 [true] x (CvtBoolToUint8 (Not bool))) for { - if !(config.PtrSize == 4) { + x := v_0 + if v_1.Op != OpRsh64x64 { break } - v.reset(OpSliceMake) - v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) - v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) - v1.AuxInt = int32ToAuxInt(0) - v.AddArg3(v0, v1, v1) + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { + break + } + bool := v_2 + v.reset(OpRsh64x8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) + v0.AddArg(v1) + v.AddArg2(x, v0) return true } - // match: (ConstSlice) - // cond: config.PtrSize == 8 - // result: (SliceMake (ConstNil ) (Const64 [0]) (Const64 [0])) + // match: (CondSelect x (Rsh32x64 x (Const64 [1])) bool) + // result: (Rsh32x8 [true] x (CvtBoolToUint8 (Not bool))) for { - if !(config.PtrSize == 8) { + x := v_0 + if v_1.Op != OpRsh32x64 { break } - v.reset(OpSliceMake) - v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) - v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) - v1.AuxInt = int64ToAuxInt(0) - v.AddArg3(v0, v1, v1) + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { + break + } + bool := v_2 + v.reset(OpRsh32x8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) + v0.AddArg(v1) + v.AddArg2(x, v0) return true } - return false -} -func rewriteValuegeneric_OpConstString(v *Value) bool { - b := v.Block - config := b.Func.Config - fe := b.Func.fe - typ := &b.Func.Config.Types - // match: (ConstString {str}) - // cond: config.PtrSize == 4 && str == "" - // result: (StringMake (ConstNil) (Const32 [0])) + // match: (CondSelect x (Rsh16x64 x (Const64 [1])) bool) + // result: (Rsh16x8 [true] x (CvtBoolToUint8 (Not bool))) for { - str := auxToString(v.Aux) - if !(config.PtrSize == 4 && str == "") { + x := v_0 + if v_1.Op != OpRsh16x64 { break } - v.reset(OpStringMake) - v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) - v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) - v1.AuxInt = int32ToAuxInt(0) - v.AddArg2(v0, v1) + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { + break + } + bool := v_2 + v.reset(OpRsh16x8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) + v0.AddArg(v1) + v.AddArg2(x, v0) return true } - // match: (ConstString {str}) - // cond: config.PtrSize == 8 && str == "" - // result: (StringMake (ConstNil) (Const64 [0])) + // match: (CondSelect x (Rsh8x64 x (Const64 [1])) bool) + // result: (Rsh8x8 [true] x (CvtBoolToUint8 (Not bool))) for { - str := auxToString(v.Aux) - if !(config.PtrSize == 8 && str == "") { + x := v_0 + if v_1.Op != OpRsh8x64 { break } - v.reset(OpStringMake) - v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) - v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) - v1.AuxInt = int64ToAuxInt(0) - v.AddArg2(v0, v1) + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { + break + } + bool := v_2 + v.reset(OpRsh8x8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) + v0.AddArg(v1) + v.AddArg2(x, v0) return true } - // match: (ConstString {str}) - // cond: config.PtrSize == 4 && str != "" - // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const32 [int32(len(str))])) + // match: (CondSelect x (Rsh64Ux64 x (Const64 [1])) bool) + // result: (Rsh64Ux8 [true] x (CvtBoolToUint8 (Not bool))) for { - str := auxToString(v.Aux) - if !(config.PtrSize == 4 && str != "") { + x := v_0 + if v_1.Op != OpRsh64Ux64 { break } - v.reset(OpStringMake) - v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) - v0.Aux = symToAux(fe.StringData(str)) - v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { + break + } + bool := v_2 + v.reset(OpRsh64Ux8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpConst32, typ.Int) - v2.AuxInt = int32ToAuxInt(int32(len(str))) - v.AddArg2(v0, v2) + v.AddArg2(x, v0) return true } - // match: (ConstString {str}) - // cond: config.PtrSize == 8 && str != "" - // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const64 [int64(len(str))])) + // match: (CondSelect x (Rsh32Ux64 x (Const64 [1])) bool) + // result: (Rsh32Ux8 [true] x (CvtBoolToUint8 (Not bool))) for { - str := auxToString(v.Aux) - if !(config.PtrSize == 8 && str != "") { + x := v_0 + if v_1.Op != OpRsh32Ux64 { break } - v.reset(OpStringMake) - v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) - v0.Aux = symToAux(fe.StringData(str)) - v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { + break + } + bool := v_2 + v.reset(OpRsh32Ux8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpConst64, typ.Int) - v2.AuxInt = int64ToAuxInt(int64(len(str))) - v.AddArg2(v0, v2) + v.AddArg2(x, v0) return true } - return false -} -func rewriteValuegeneric_OpConvert(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Convert (Add64 (Convert ptr mem) off) mem) - // result: (AddPtr ptr off) + // match: (CondSelect x (Rsh16Ux64 x (Const64 [1])) bool) + // result: (Rsh16Ux8 [true] x (CvtBoolToUint8 (Not bool))) for { - if v_0.Op != OpAdd64 { + x := v_0 + if v_1.Op != OpRsh16Ux64 { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpConvert { + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { + break + } + bool := v_2 + v.reset(OpRsh16Ux8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } + // match: (CondSelect x (Rsh8Ux64 x (Const64 [1])) bool) + // result: (Rsh8Ux8 [true] x (CvtBoolToUint8 (Not bool))) + for { + x := v_0 + if v_1.Op != OpRsh8Ux64 { + break + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 || auxIntToInt64(v_1_1.AuxInt) != 1 { + break + } + bool := v_2 + v.reset(OpRsh8Ux8) + v.AuxInt = boolToAuxInt(true) + v0 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v1 := b.NewValue0(v.Pos, OpNot, bool.Type) + v1.AddArg(bool) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } + // match: (CondSelect op:(Or8 x c:(Const8)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Or8 x (Mul8 c (CvtBoolToUint8 bool))) + for { + op := v_0 + if op.Op != OpOr8 { + break + } + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst8 || x != v_1 { continue } - mem := v_0_0.Args[1] - ptr := v_0_0.Args[0] - off := v_0_1 - if mem != v_1 { + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { continue } - v.reset(OpAddPtr) - v.AddArg2(ptr, off) + v.reset(OpOr8) + v0 := b.NewValue0(v.Pos, OpMul8, t) + v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, t) + v1.AddArg(bool) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) return true } break } - // match: (Convert (Add32 (Convert ptr mem) off) mem) - // result: (AddPtr ptr off) + // match: (CondSelect op:(Or64 x c:(Const64)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Or64 x (Mul64 c (ZeroExt8to64 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpAdd32 { + op := v_0 + if op.Op != OpOr64 { break } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpConvert { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst64 || x != v_1 { continue } - mem := v_0_0.Args[1] - ptr := v_0_0.Args[0] - off := v_0_1 - if mem != v_1 { + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { continue } - v.reset(OpAddPtr) - v.AddArg2(ptr, off) + v.reset(OpOr64) + v0 := b.NewValue0(v.Pos, OpMul64, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to64, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) return true } break } - // match: (Convert (Convert ptr mem) mem) - // result: ptr + // match: (CondSelect op:(Or32 x c:(Const32)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Or32 x (Mul32 c (ZeroExt8to32 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpConvert { + op := v_0 + if op.Op != OpOr32 { break } - mem := v_0.Args[1] - ptr := v_0.Args[0] - if mem != v_1 { - break + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst32 || x != v_1 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpOr32) + v0 := b.NewValue0(v.Pos, OpMul32, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to32, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } - v.copyOf(ptr) - return true + break } - // match: (Convert a:(Add64 (Add64 (Convert ptr mem) off1) off2) mem) - // result: (AddPtr ptr (Add64 off1 off2)) + // match: (CondSelect op:(Or16 x c:(Const16)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Or16 x (Mul16 c (ZeroExt8to16 (CvtBoolToUint8 bool)))) for { - a := v_0 - if a.Op != OpAdd64 { + op := v_0 + if op.Op != OpOr16 { break } - _ = a.Args[1] - a_0 := a.Args[0] - a_1 := a.Args[1] - for _i0 := 0; _i0 <= 1; _i0, a_0, a_1 = _i0+1, a_1, a_0 { - if a_0.Op != OpAdd64 { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst16 || x != v_1 { continue } - _ = a_0.Args[1] - a_0_0 := a_0.Args[0] - a_0_1 := a_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, a_0_0, a_0_1 = _i1+1, a_0_1, a_0_0 { - if a_0_0.Op != OpConvert { - continue - } - mem := a_0_0.Args[1] - ptr := a_0_0.Args[0] - off1 := a_0_1 - off2 := a_1 - if mem != v_1 { - continue - } - v.reset(OpAddPtr) - v0 := b.NewValue0(v.Pos, OpAdd64, a.Type) - v0.AddArg2(off1, off2) - v.AddArg2(ptr, v0) - return true + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue } + v.reset(OpOr16) + v0 := b.NewValue0(v.Pos, OpMul16, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to16, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } break } - // match: (Convert a:(Add32 (Add32 (Convert ptr mem) off1) off2) mem) - // result: (AddPtr ptr (Add32 off1 off2)) + // match: (CondSelect x op:(Or8 x c:(Const8)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Or8 x (Mul8 c (CvtBoolToUint8 (Not bool)))) for { - a := v_0 - if a.Op != OpAdd32 { + x := v_0 + op := v_1 + if op.Op != OpOr8 { break } - _ = a.Args[1] - a_0 := a.Args[0] - a_1 := a.Args[1] - for _i0 := 0; _i0 <= 1; _i0, a_0, a_1 = _i0+1, a_1, a_0 { - if a_0.Op != OpAdd32 { + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { continue } - _ = a_0.Args[1] - a_0_0 := a_0.Args[0] - a_0_1 := a_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, a_0_0, a_0_1 = _i1+1, a_0_1, a_0_0 { - if a_0_0.Op != OpConvert { - continue - } - mem := a_0_0.Args[1] - ptr := a_0_0.Args[0] - off1 := a_0_1 - off2 := a_1 - if mem != v_1 { - continue - } - v.reset(OpAddPtr) - v0 := b.NewValue0(v.Pos, OpAdd32, a.Type) - v0.AddArg2(off1, off2) - v.AddArg2(ptr, v0) - return true + c := op_1 + if c.Op != OpConst8 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue } + v.reset(OpOr8) + v0 := b.NewValue0(v.Pos, OpMul8, t) + v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, t) + v2 := b.NewValue0(v.Pos, OpNot, bool.Type) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } break } - return false -} -func rewriteValuegeneric_OpCtz16(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (Ctz16 (Const16 [c])) - // cond: config.PtrSize == 4 - // result: (Const32 [int32(ntz16(c))]) + // match: (CondSelect x op:(Or64 x c:(Const64)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Or64 x (Mul64 c (ZeroExt8to64 (CvtBoolToUint8 (Not bool))))) for { - if v_0.Op != OpConst16 { + x := v_0 + op := v_1 + if op.Op != OpOr64 { break } - c := auxIntToInt16(v_0.AuxInt) - if !(config.PtrSize == 4) { - break + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst64 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpOr64) + v0 := b.NewValue0(v.Pos, OpMul64, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to64, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3 := b.NewValue0(v.Pos, OpNot, bool.Type) + v3.AddArg(bool) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } - v.reset(OpConst32) - v.AuxInt = int32ToAuxInt(int32(ntz16(c))) - return true + break } - // match: (Ctz16 (Const16 [c])) - // cond: config.PtrSize == 8 - // result: (Const64 [int64(ntz16(c))]) + // match: (CondSelect x op:(Or32 x c:(Const32)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Or32 x (Mul32 c (ZeroExt8to32 (CvtBoolToUint8 (Not bool))))) for { - if v_0.Op != OpConst16 { + x := v_0 + op := v_1 + if op.Op != OpOr32 { break } - c := auxIntToInt16(v_0.AuxInt) - if !(config.PtrSize == 8) { - break + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst32 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpOr32) + v0 := b.NewValue0(v.Pos, OpMul32, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to32, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3 := b.NewValue0(v.Pos, OpNot, bool.Type) + v3.AddArg(bool) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } - v.reset(OpConst64) - v.AuxInt = int64ToAuxInt(int64(ntz16(c))) - return true + break } - return false -} -func rewriteValuegeneric_OpCtz32(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (Ctz32 (Const32 [c])) - // cond: config.PtrSize == 4 - // result: (Const32 [int32(ntz32(c))]) + // match: (CondSelect x op:(Or16 x c:(Const16)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Or16 x (Mul16 c (ZeroExt8to16 (CvtBoolToUint8 (Not bool))))) for { - if v_0.Op != OpConst32 { + x := v_0 + op := v_1 + if op.Op != OpOr16 { break } - c := auxIntToInt32(v_0.AuxInt) - if !(config.PtrSize == 4) { - break + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst16 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpOr16) + v0 := b.NewValue0(v.Pos, OpMul16, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to16, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3 := b.NewValue0(v.Pos, OpNot, bool.Type) + v3.AddArg(bool) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } - v.reset(OpConst32) - v.AuxInt = int32ToAuxInt(int32(ntz32(c))) - return true + break } - // match: (Ctz32 (Const32 [c])) - // cond: config.PtrSize == 8 - // result: (Const64 [int64(ntz32(c))]) + // match: (CondSelect op:(Xor8 x c:(Const8)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Xor8 x (Mul8 c (CvtBoolToUint8 bool))) for { - if v_0.Op != OpConst32 { + op := v_0 + if op.Op != OpXor8 { break } - c := auxIntToInt32(v_0.AuxInt) - if !(config.PtrSize == 8) { - break + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst8 || x != v_1 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpXor8) + v0 := b.NewValue0(v.Pos, OpMul8, t) + v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, t) + v1.AddArg(bool) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } - v.reset(OpConst64) - v.AuxInt = int64ToAuxInt(int64(ntz32(c))) - return true + break } - return false -} -func rewriteValuegeneric_OpCtz64(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (Ctz64 (Const64 [c])) - // cond: config.PtrSize == 4 - // result: (Const32 [int32(ntz64(c))]) + // match: (CondSelect op:(Xor64 x c:(Const64)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Xor64 x (Mul64 c (ZeroExt8to64 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpConst64 { - break - } - c := auxIntToInt64(v_0.AuxInt) - if !(config.PtrSize == 4) { + op := v_0 + if op.Op != OpXor64 { break } - v.reset(OpConst32) - v.AuxInt = int32ToAuxInt(int32(ntz64(c))) - return true + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst64 || x != v_1 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpXor64) + v0 := b.NewValue0(v.Pos, OpMul64, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to64, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true + } + break } - // match: (Ctz64 (Const64 [c])) - // cond: config.PtrSize == 8 - // result: (Const64 [int64(ntz64(c))]) + // match: (CondSelect op:(Xor32 x c:(Const32)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Xor32 x (Mul32 c (ZeroExt8to32 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpConst64 { + op := v_0 + if op.Op != OpXor32 { break } - c := auxIntToInt64(v_0.AuxInt) - if !(config.PtrSize == 8) { - break + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst32 || x != v_1 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpXor32) + v0 := b.NewValue0(v.Pos, OpMul32, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to32, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } - v.reset(OpConst64) - v.AuxInt = int64ToAuxInt(int64(ntz64(c))) - return true + break } - return false -} -func rewriteValuegeneric_OpCtz8(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - config := b.Func.Config - // match: (Ctz8 (Const8 [c])) - // cond: config.PtrSize == 4 - // result: (Const32 [int32(ntz8(c))]) + // match: (CondSelect op:(Xor16 x c:(Const16)) x bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Xor16 x (Mul16 c (ZeroExt8to16 (CvtBoolToUint8 bool)))) for { - if v_0.Op != OpConst8 { + op := v_0 + if op.Op != OpXor16 { break } - c := auxIntToInt8(v_0.AuxInt) - if !(config.PtrSize == 4) { - break + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + x := op_0 + c := op_1 + if c.Op != OpConst16 || x != v_1 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpXor16) + v0 := b.NewValue0(v.Pos, OpMul16, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to16, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } - v.reset(OpConst32) - v.AuxInt = int32ToAuxInt(int32(ntz8(c))) - return true + break } - // match: (Ctz8 (Const8 [c])) - // cond: config.PtrSize == 8 - // result: (Const64 [int64(ntz8(c))]) + // match: (CondSelect x op:(Xor8 x c:(Const8)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Xor8 x (Mul8 c (CvtBoolToUint8 (Not bool)))) for { - if v_0.Op != OpConst8 { + x := v_0 + op := v_1 + if op.Op != OpXor8 { break } - c := auxIntToInt8(v_0.AuxInt) - if !(config.PtrSize == 8) { - break + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst8 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpXor8) + v0 := b.NewValue0(v.Pos, OpMul8, t) + v1 := b.NewValue0(v.Pos, OpCvtBoolToUint8, t) + v2 := b.NewValue0(v.Pos, OpNot, bool.Type) + v2.AddArg(bool) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } - v.reset(OpConst64) - v.AuxInt = int64ToAuxInt(int64(ntz8(c))) - return true + break } - return false -} -func rewriteValuegeneric_OpCvt32Fto32(v *Value) bool { - v_0 := v.Args[0] - // match: (Cvt32Fto32 (Const32F [c])) - // cond: c >= -1<<31 && c < 1<<31 - // result: (Const32 [int32(c)]) + // match: (CondSelect x op:(Xor64 x c:(Const64)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Xor64 x (Mul64 c (ZeroExt8to64 (CvtBoolToUint8 (Not bool))))) for { - if v_0.Op != OpConst32F { + x := v_0 + op := v_1 + if op.Op != OpXor64 { break } - c := auxIntToFloat32(v_0.AuxInt) - if !(c >= -1<<31 && c < 1<<31) { - break + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst64 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpXor64) + v0 := b.NewValue0(v.Pos, OpMul64, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to64, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3 := b.NewValue0(v.Pos, OpNot, bool.Type) + v3.AddArg(bool) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } - v.reset(OpConst32) - v.AuxInt = int32ToAuxInt(int32(c)) - return true + break } - return false -} -func rewriteValuegeneric_OpCvt32Fto64(v *Value) bool { - v_0 := v.Args[0] - // match: (Cvt32Fto64 (Const32F [c])) - // cond: c >= -1<<63 && c < 1<<63 - // result: (Const64 [int64(c)]) + // match: (CondSelect x op:(Xor32 x c:(Const32)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Xor32 x (Mul32 c (ZeroExt8to32 (CvtBoolToUint8 (Not bool))))) for { - if v_0.Op != OpConst32F { + x := v_0 + op := v_1 + if op.Op != OpXor32 { break } - c := auxIntToFloat32(v_0.AuxInt) - if !(c >= -1<<63 && c < 1<<63) { - break + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst32 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpXor32) + v0 := b.NewValue0(v.Pos, OpMul32, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to32, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3 := b.NewValue0(v.Pos, OpNot, bool.Type) + v3.AddArg(bool) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true } - v.reset(OpConst64) - v.AuxInt = int64ToAuxInt(int64(c)) - return true + break } - return false -} -func rewriteValuegeneric_OpCvt32Fto64F(v *Value) bool { - v_0 := v.Args[0] - // match: (Cvt32Fto64F (Const32F [c])) - // result: (Const64F [float64(c)]) + // match: (CondSelect x op:(Xor16 x c:(Const16)) bool) + // cond: rewriteCondSelectIntoMath(config, op.Op, c.AuxInt) + // result: (Xor16 x (Mul16 c (ZeroExt8to16 (CvtBoolToUint8 (Not bool))))) for { - if v_0.Op != OpConst32F { + x := v_0 + op := v_1 + if op.Op != OpXor16 { break } - c := auxIntToFloat32(v_0.AuxInt) - v.reset(OpConst64F) - v.AuxInt = float64ToAuxInt(float64(c)) - return true + t := op.Type + _ = op.Args[1] + op_0 := op.Args[0] + op_1 := op.Args[1] + for _i0 := 0; _i0 <= 1; _i0, op_0, op_1 = _i0+1, op_1, op_0 { + if x != op_0 { + continue + } + c := op_1 + if c.Op != OpConst16 { + continue + } + bool := v_2 + if !(rewriteCondSelectIntoMath(config, op.Op, c.AuxInt)) { + continue + } + v.reset(OpXor16) + v0 := b.NewValue0(v.Pos, OpMul16, t) + v1 := b.NewValue0(v.Pos, OpZeroExt8to16, t) + v2 := b.NewValue0(v.Pos, OpCvtBoolToUint8, types.Types[types.TUINT8]) + v3 := b.NewValue0(v.Pos, OpNot, bool.Type) + v3.AddArg(bool) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg2(c, v1) + v.AddArg2(x, v0) + return true + } + break } return false } -func rewriteValuegeneric_OpCvt32to32F(v *Value) bool { - v_0 := v.Args[0] - // match: (Cvt32to32F (Const32 [c])) - // result: (Const32F [float32(c)]) +func rewriteValuegeneric_OpConstInterface(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (ConstInterface) + // result: (IMake (ConstNil ) (ConstNil )) for { - if v_0.Op != OpConst32 { - break - } - c := auxIntToInt32(v_0.AuxInt) - v.reset(OpConst32F) - v.AuxInt = float32ToAuxInt(float32(c)) + v.reset(OpIMake) + v0 := b.NewValue0(v.Pos, OpConstNil, typ.Uintptr) + v1 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) + v.AddArg2(v0, v1) return true } - return false } -func rewriteValuegeneric_OpCvt32to64F(v *Value) bool { - v_0 := v.Args[0] - // match: (Cvt32to64F (Const32 [c])) - // result: (Const64F [float64(c)]) +func rewriteValuegeneric_OpConstSlice(v *Value) bool { + b := v.Block + config := b.Func.Config + typ := &b.Func.Config.Types + // match: (ConstSlice) + // cond: config.PtrSize == 4 + // result: (SliceMake (ConstNil ) (Const32 [0]) (Const32 [0])) for { - if v_0.Op != OpConst32 { + if !(config.PtrSize == 4) { break } - c := auxIntToInt32(v_0.AuxInt) - v.reset(OpConst64F) - v.AuxInt = float64ToAuxInt(float64(c)) + v.reset(OpSliceMake) + v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) + v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) + v1.AuxInt = int32ToAuxInt(0) + v.AddArg3(v0, v1, v1) return true } - return false -} -func rewriteValuegeneric_OpCvt64Fto32(v *Value) bool { - v_0 := v.Args[0] - // match: (Cvt64Fto32 (Const64F [c])) - // cond: c >= -1<<31 && c < 1<<31 - // result: (Const32 [int32(c)]) + // match: (ConstSlice) + // cond: config.PtrSize == 8 + // result: (SliceMake (ConstNil ) (Const64 [0]) (Const64 [0])) for { - if v_0.Op != OpConst64F { - break - } - c := auxIntToFloat64(v_0.AuxInt) - if !(c >= -1<<31 && c < 1<<31) { + if !(config.PtrSize == 8) { break } - v.reset(OpConst32) - v.AuxInt = int32ToAuxInt(int32(c)) + v.reset(OpSliceMake) + v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) + v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) + v1.AuxInt = int64ToAuxInt(0) + v.AddArg3(v0, v1, v1) return true } return false } -func rewriteValuegeneric_OpCvt64Fto32F(v *Value) bool { - v_0 := v.Args[0] - // match: (Cvt64Fto32F (Const64F [c])) - // result: (Const32F [float32(c)]) +func rewriteValuegeneric_OpConstString(v *Value) bool { + b := v.Block + config := b.Func.Config + fe := b.Func.fe + typ := &b.Func.Config.Types + // match: (ConstString {str}) + // cond: config.PtrSize == 4 && str == "" + // result: (StringMake (ConstNil) (Const32 [0])) for { - if v_0.Op != OpConst64F { + str := auxToString(v.Aux) + if !(config.PtrSize == 4 && str == "") { break } - c := auxIntToFloat64(v_0.AuxInt) - v.reset(OpConst32F) - v.AuxInt = float32ToAuxInt(float32(c)) + v.reset(OpStringMake) + v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) + v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) + v1.AuxInt = int32ToAuxInt(0) + v.AddArg2(v0, v1) return true } - // match: (Cvt64Fto32F sqrt0:(Sqrt (Cvt32Fto64F x))) - // cond: sqrt0.Uses==1 - // result: (Sqrt32 x) + // match: (ConstString {str}) + // cond: config.PtrSize == 8 && str == "" + // result: (StringMake (ConstNil) (Const64 [0])) for { - sqrt0 := v_0 - if sqrt0.Op != OpSqrt { - break - } - sqrt0_0 := sqrt0.Args[0] - if sqrt0_0.Op != OpCvt32Fto64F { - break - } - x := sqrt0_0.Args[0] - if !(sqrt0.Uses == 1) { + str := auxToString(v.Aux) + if !(config.PtrSize == 8 && str == "") { break } - v.reset(OpSqrt32) - v.AddArg(x) + v.reset(OpStringMake) + v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) + v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) + v1.AuxInt = int64ToAuxInt(0) + v.AddArg2(v0, v1) + return true + } + // match: (ConstString {str}) + // cond: config.PtrSize == 4 && str != "" + // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const32 [int32(len(str))])) + for { + str := auxToString(v.Aux) + if !(config.PtrSize == 4 && str != "") { + break + } + v.reset(OpStringMake) + v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) + v0.Aux = symToAux(fe.StringData(str)) + v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpConst32, typ.Int) + v2.AuxInt = int32ToAuxInt(int32(len(str))) + v.AddArg2(v0, v2) + return true + } + // match: (ConstString {str}) + // cond: config.PtrSize == 8 && str != "" + // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const64 [int64(len(str))])) + for { + str := auxToString(v.Aux) + if !(config.PtrSize == 8 && str != "") { + break + } + v.reset(OpStringMake) + v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) + v0.Aux = symToAux(fe.StringData(str)) + v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpConst64, typ.Int) + v2.AuxInt = int64ToAuxInt(int64(len(str))) + v.AddArg2(v0, v2) + return true + } + return false +} +func rewriteValuegeneric_OpConvert(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Convert (Add64 (Convert ptr mem) off) mem) + // result: (AddPtr ptr off) + for { + if v_0.Op != OpAdd64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpConvert { + continue + } + mem := v_0_0.Args[1] + ptr := v_0_0.Args[0] + off := v_0_1 + if mem != v_1 { + continue + } + v.reset(OpAddPtr) + v.AddArg2(ptr, off) + return true + } + break + } + // match: (Convert (Add32 (Convert ptr mem) off) mem) + // result: (AddPtr ptr off) + for { + if v_0.Op != OpAdd32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpConvert { + continue + } + mem := v_0_0.Args[1] + ptr := v_0_0.Args[0] + off := v_0_1 + if mem != v_1 { + continue + } + v.reset(OpAddPtr) + v.AddArg2(ptr, off) + return true + } + break + } + // match: (Convert (Convert ptr mem) mem) + // result: ptr + for { + if v_0.Op != OpConvert { + break + } + mem := v_0.Args[1] + ptr := v_0.Args[0] + if mem != v_1 { + break + } + v.copyOf(ptr) + return true + } + // match: (Convert a:(Add64 (Add64 (Convert ptr mem) off1) off2) mem) + // result: (AddPtr ptr (Add64 off1 off2)) + for { + a := v_0 + if a.Op != OpAdd64 { + break + } + _ = a.Args[1] + a_0 := a.Args[0] + a_1 := a.Args[1] + for _i0 := 0; _i0 <= 1; _i0, a_0, a_1 = _i0+1, a_1, a_0 { + if a_0.Op != OpAdd64 { + continue + } + _ = a_0.Args[1] + a_0_0 := a_0.Args[0] + a_0_1 := a_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, a_0_0, a_0_1 = _i1+1, a_0_1, a_0_0 { + if a_0_0.Op != OpConvert { + continue + } + mem := a_0_0.Args[1] + ptr := a_0_0.Args[0] + off1 := a_0_1 + off2 := a_1 + if mem != v_1 { + continue + } + v.reset(OpAddPtr) + v0 := b.NewValue0(v.Pos, OpAdd64, a.Type) + v0.AddArg2(off1, off2) + v.AddArg2(ptr, v0) + return true + } + } + break + } + // match: (Convert a:(Add32 (Add32 (Convert ptr mem) off1) off2) mem) + // result: (AddPtr ptr (Add32 off1 off2)) + for { + a := v_0 + if a.Op != OpAdd32 { + break + } + _ = a.Args[1] + a_0 := a.Args[0] + a_1 := a.Args[1] + for _i0 := 0; _i0 <= 1; _i0, a_0, a_1 = _i0+1, a_1, a_0 { + if a_0.Op != OpAdd32 { + continue + } + _ = a_0.Args[1] + a_0_0 := a_0.Args[0] + a_0_1 := a_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, a_0_0, a_0_1 = _i1+1, a_0_1, a_0_0 { + if a_0_0.Op != OpConvert { + continue + } + mem := a_0_0.Args[1] + ptr := a_0_0.Args[0] + off1 := a_0_1 + off2 := a_1 + if mem != v_1 { + continue + } + v.reset(OpAddPtr) + v0 := b.NewValue0(v.Pos, OpAdd32, a.Type) + v0.AddArg2(off1, off2) + v.AddArg2(ptr, v0) + return true + } + } + break + } + return false +} +func rewriteValuegeneric_OpCtz16(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + // match: (Ctz16 (Const16 [c])) + // cond: config.PtrSize == 4 + // result: (Const32 [int32(ntz16(c))]) + for { + if v_0.Op != OpConst16 { + break + } + c := auxIntToInt16(v_0.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpConst32) + v.AuxInt = int32ToAuxInt(int32(ntz16(c))) + return true + } + // match: (Ctz16 (Const16 [c])) + // cond: config.PtrSize == 8 + // result: (Const64 [int64(ntz16(c))]) + for { + if v_0.Op != OpConst16 { + break + } + c := auxIntToInt16(v_0.AuxInt) + if !(config.PtrSize == 8) { + break + } + v.reset(OpConst64) + v.AuxInt = int64ToAuxInt(int64(ntz16(c))) + return true + } + return false +} +func rewriteValuegeneric_OpCtz32(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + // match: (Ctz32 (Const32 [c])) + // cond: config.PtrSize == 4 + // result: (Const32 [int32(ntz32(c))]) + for { + if v_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_0.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpConst32) + v.AuxInt = int32ToAuxInt(int32(ntz32(c))) + return true + } + // match: (Ctz32 (Const32 [c])) + // cond: config.PtrSize == 8 + // result: (Const64 [int64(ntz32(c))]) + for { + if v_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_0.AuxInt) + if !(config.PtrSize == 8) { + break + } + v.reset(OpConst64) + v.AuxInt = int64ToAuxInt(int64(ntz32(c))) + return true + } + return false +} +func rewriteValuegeneric_OpCtz64(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + // match: (Ctz64 (Const64 [c])) + // cond: config.PtrSize == 4 + // result: (Const32 [int32(ntz64(c))]) + for { + if v_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_0.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpConst32) + v.AuxInt = int32ToAuxInt(int32(ntz64(c))) + return true + } + // match: (Ctz64 (Const64 [c])) + // cond: config.PtrSize == 8 + // result: (Const64 [int64(ntz64(c))]) + for { + if v_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_0.AuxInt) + if !(config.PtrSize == 8) { + break + } + v.reset(OpConst64) + v.AuxInt = int64ToAuxInt(int64(ntz64(c))) + return true + } + return false +} +func rewriteValuegeneric_OpCtz8(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + // match: (Ctz8 (Const8 [c])) + // cond: config.PtrSize == 4 + // result: (Const32 [int32(ntz8(c))]) + for { + if v_0.Op != OpConst8 { + break + } + c := auxIntToInt8(v_0.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpConst32) + v.AuxInt = int32ToAuxInt(int32(ntz8(c))) + return true + } + // match: (Ctz8 (Const8 [c])) + // cond: config.PtrSize == 8 + // result: (Const64 [int64(ntz8(c))]) + for { + if v_0.Op != OpConst8 { + break + } + c := auxIntToInt8(v_0.AuxInt) + if !(config.PtrSize == 8) { + break + } + v.reset(OpConst64) + v.AuxInt = int64ToAuxInt(int64(ntz8(c))) + return true + } + return false +} +func rewriteValuegeneric_OpCvt32Fto32(v *Value) bool { + v_0 := v.Args[0] + // match: (Cvt32Fto32 (Const32F [c])) + // cond: c >= -1<<31 && c < 1<<31 + // result: (Const32 [int32(c)]) + for { + if v_0.Op != OpConst32F { + break + } + c := auxIntToFloat32(v_0.AuxInt) + if !(c >= -1<<31 && c < 1<<31) { + break + } + v.reset(OpConst32) + v.AuxInt = int32ToAuxInt(int32(c)) + return true + } + return false +} +func rewriteValuegeneric_OpCvt32Fto64(v *Value) bool { + v_0 := v.Args[0] + // match: (Cvt32Fto64 (Const32F [c])) + // cond: c >= -1<<63 && c < 1<<63 + // result: (Const64 [int64(c)]) + for { + if v_0.Op != OpConst32F { + break + } + c := auxIntToFloat32(v_0.AuxInt) + if !(c >= -1<<63 && c < 1<<63) { + break + } + v.reset(OpConst64) + v.AuxInt = int64ToAuxInt(int64(c)) + return true + } + return false +} +func rewriteValuegeneric_OpCvt32Fto64F(v *Value) bool { + v_0 := v.Args[0] + // match: (Cvt32Fto64F (Const32F [c])) + // result: (Const64F [float64(c)]) + for { + if v_0.Op != OpConst32F { + break + } + c := auxIntToFloat32(v_0.AuxInt) + v.reset(OpConst64F) + v.AuxInt = float64ToAuxInt(float64(c)) + return true + } + return false +} +func rewriteValuegeneric_OpCvt32to32F(v *Value) bool { + v_0 := v.Args[0] + // match: (Cvt32to32F (Const32 [c])) + // result: (Const32F [float32(c)]) + for { + if v_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_0.AuxInt) + v.reset(OpConst32F) + v.AuxInt = float32ToAuxInt(float32(c)) + return true + } + return false +} +func rewriteValuegeneric_OpCvt32to64F(v *Value) bool { + v_0 := v.Args[0] + // match: (Cvt32to64F (Const32 [c])) + // result: (Const64F [float64(c)]) + for { + if v_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_0.AuxInt) + v.reset(OpConst64F) + v.AuxInt = float64ToAuxInt(float64(c)) + return true + } + return false +} +func rewriteValuegeneric_OpCvt64Fto32(v *Value) bool { + v_0 := v.Args[0] + // match: (Cvt64Fto32 (Const64F [c])) + // cond: c >= -1<<31 && c < 1<<31 + // result: (Const32 [int32(c)]) + for { + if v_0.Op != OpConst64F { + break + } + c := auxIntToFloat64(v_0.AuxInt) + if !(c >= -1<<31 && c < 1<<31) { + break + } + v.reset(OpConst32) + v.AuxInt = int32ToAuxInt(int32(c)) + return true + } + return false +} +func rewriteValuegeneric_OpCvt64Fto32F(v *Value) bool { + v_0 := v.Args[0] + // match: (Cvt64Fto32F (Const64F [c])) + // result: (Const32F [float32(c)]) + for { + if v_0.Op != OpConst64F { + break + } + c := auxIntToFloat64(v_0.AuxInt) + v.reset(OpConst32F) + v.AuxInt = float32ToAuxInt(float32(c)) + return true + } + // match: (Cvt64Fto32F sqrt0:(Sqrt (Cvt32Fto64F x))) + // cond: sqrt0.Uses==1 + // result: (Sqrt32 x) + for { + sqrt0 := v_0 + if sqrt0.Op != OpSqrt { + break + } + sqrt0_0 := sqrt0.Args[0] + if sqrt0_0.Op != OpCvt32Fto64F { + break + } + x := sqrt0_0.Args[0] + if !(sqrt0.Uses == 1) { + break + } + v.reset(OpSqrt32) + v.AddArg(x) return true } return false @@ -6862,24 +8444,6 @@ func rewriteValuegeneric_OpDiv16(v *Value) bool { v.AuxInt = int16ToAuxInt(c / d) return true } - // match: (Div16 n (Const16 [c])) - // cond: isNonNegative(n) && isPowerOfTwo(c) - // result: (Rsh16Ux64 n (Const64 [log16(c)])) - for { - n := v_0 - if v_1.Op != OpConst16 { - break - } - c := auxIntToInt16(v_1.AuxInt) - if !(isNonNegative(n) && isPowerOfTwo(c)) { - break - } - v.reset(OpRsh16Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v0.AuxInt = int64ToAuxInt(log16(c)) - v.AddArg2(n, v0) - return true - } // match: (Div16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Neg16 (Div16 n (Const16 [-c]))) @@ -6919,74 +8483,12 @@ func rewriteValuegeneric_OpDiv16(v *Value) bool { v.AddArg2(v0, v2) return true } - // match: (Div16 n (Const16 [c])) - // cond: isPowerOfTwo(c) - // result: (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [int64(16-log16(c))]))) (Const64 [int64(log16(c))])) - for { - t := v.Type - n := v_0 - if v_1.Op != OpConst16 { - break - } - c := auxIntToInt16(v_1.AuxInt) - if !(isPowerOfTwo(c)) { - break - } - v.reset(OpRsh16x64) - v0 := b.NewValue0(v.Pos, OpAdd16, t) - v1 := b.NewValue0(v.Pos, OpRsh16Ux64, t) - v2 := b.NewValue0(v.Pos, OpRsh16x64, t) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(15) - v2.AddArg2(n, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(int64(16 - log16(c))) - v1.AddArg2(v2, v4) - v0.AddArg2(n, v1) - v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v5.AuxInt = int64ToAuxInt(int64(log16(c))) - v.AddArg2(v0, v5) - return true - } - // match: (Div16 x (Const16 [c])) - // cond: smagicOK16(c) - // result: (Sub16 (Rsh32x64 (Mul32 (Const32 [int32(smagic16(c).m)]) (SignExt16to32 x)) (Const64 [16+smagic16(c).s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) - for { - t := v.Type - x := v_0 - if v_1.Op != OpConst16 { - break - } - c := auxIntToInt16(v_1.AuxInt) - if !(smagicOK16(c)) { - break - } - v.reset(OpSub16) - v.Type = t - v0 := b.NewValue0(v.Pos, OpRsh32x64, t) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(smagic16(c).m)) - v3 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v3.AddArg(x) - v1.AddArg2(v2, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(16 + smagic16(c).s) - v0.AddArg2(v1, v4) - v5 := b.NewValue0(v.Pos, OpRsh32x64, t) - v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v6.AuxInt = int64ToAuxInt(31) - v5.AddArg2(v3, v6) - v.AddArg2(v0, v5) - return true - } return false } func rewriteValuegeneric_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - config := b.Func.Config typ := &b.Func.Config.Types // match: (Div16u (Const16 [c]) (Const16 [d])) // cond: d != 0 @@ -7008,7 +8510,7 @@ func rewriteValuegeneric_OpDiv16u(v *Value) bool { return true } // match: (Div16u n (Const16 [c])) - // cond: isUnsignedPowerOfTwo(uint16(c)) + // cond: isPowerOfTwo(uint16(c)) // result: (Rsh16Ux64 n (Const64 [log16u(uint16(c))])) for { n := v_0 @@ -7016,7 +8518,7 @@ func rewriteValuegeneric_OpDiv16u(v *Value) bool { break } c := auxIntToInt16(v_1.AuxInt) - if !(isUnsignedPowerOfTwo(uint16(c))) { + if !(isPowerOfTwo(uint16(c))) { break } v.reset(OpRsh16Ux64) @@ -7025,127 +8527,12 @@ func rewriteValuegeneric_OpDiv16u(v *Value) bool { v.AddArg2(n, v0) return true } - // match: (Div16u x (Const16 [c])) - // cond: umagicOK16(c) && config.RegSize == 8 - // result: (Trunc64to16 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<16+umagic16(c).m)]) (ZeroExt16to64 x)) (Const64 [16+umagic16(c).s]))) - for { - x := v_0 - if v_1.Op != OpConst16 { - break - } - c := auxIntToInt16(v_1.AuxInt) - if !(umagicOK16(c) && config.RegSize == 8) { - break - } - v.reset(OpTrunc64to16) - v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(int64(1<<16 + umagic16(c).m)) - v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) - v3.AddArg(x) - v1.AddArg2(v2, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s) - v0.AddArg2(v1, v4) - v.AddArg(v0) - return true - } - // match: (Div16u x (Const16 [c])) - // cond: umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0 - // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<15+umagic16(c).m/2)]) (ZeroExt16to32 x)) (Const64 [16+umagic16(c).s-1]))) - for { - x := v_0 - if v_1.Op != OpConst16 { - break - } - c := auxIntToInt16(v_1.AuxInt) - if !(umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0) { - break - } - v.reset(OpTrunc32to16) - v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(1<<15 + umagic16(c).m/2)) - v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) - v3.AddArg(x) - v1.AddArg2(v2, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) - v0.AddArg2(v1, v4) - v.AddArg(v0) - return true - } - // match: (Div16u x (Const16 [c])) - // cond: umagicOK16(c) && config.RegSize == 4 && c&1 == 0 - // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<15+(umagic16(c).m+1)/2)]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [16+umagic16(c).s-2]))) - for { - x := v_0 - if v_1.Op != OpConst16 { - break - } - c := auxIntToInt16(v_1.AuxInt) - if !(umagicOK16(c) && config.RegSize == 4 && c&1 == 0) { - break - } - v.reset(OpTrunc32to16) - v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(1<<15 + (umagic16(c).m+1)/2)) - v3 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) - v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) - v4.AddArg(x) - v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v5.AuxInt = int64ToAuxInt(1) - v3.AddArg2(v4, v5) - v1.AddArg2(v2, v3) - v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v6.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 2) - v0.AddArg2(v1, v6) - v.AddArg(v0) - return true - } - // match: (Div16u x (Const16 [c])) - // cond: umagicOK16(c) && config.RegSize == 4 && config.useAvg - // result: (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) (Mul32 (Const32 [int32(umagic16(c).m)]) (ZeroExt16to32 x))) (Const64 [16+umagic16(c).s-1]))) - for { - x := v_0 - if v_1.Op != OpConst16 { - break - } - c := auxIntToInt16(v_1.AuxInt) - if !(umagicOK16(c) && config.RegSize == 4 && config.useAvg) { - break - } - v.reset(OpTrunc32to16) - v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpLsh32x64, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) - v3.AddArg(x) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(16) - v2.AddArg2(v3, v4) - v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v6.AuxInt = int32ToAuxInt(int32(umagic16(c).m)) - v5.AddArg2(v6, v3) - v1.AddArg2(v2, v5) - v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v7.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) - v0.AddArg2(v1, v7) - v.AddArg(v0) - return true - } return false } func rewriteValuegeneric_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32 (Const32 [c]) (Const32 [d])) // cond: d != 0 @@ -7166,24 +8553,6 @@ func rewriteValuegeneric_OpDiv32(v *Value) bool { v.AuxInt = int32ToAuxInt(c / d) return true } - // match: (Div32 n (Const32 [c])) - // cond: isNonNegative(n) && isPowerOfTwo(c) - // result: (Rsh32Ux64 n (Const64 [log32(c)])) - for { - n := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(isNonNegative(n) && isPowerOfTwo(c)) { - break - } - v.reset(OpRsh32Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v0.AuxInt = int64ToAuxInt(log32(c)) - v.AddArg2(n, v0) - return true - } // match: (Div32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Neg32 (Div32 n (Const32 [-c]))) @@ -7217,133 +8586,10 @@ func rewriteValuegeneric_OpDiv32(v *Value) bool { v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpNeg32, t) v1.AddArg(x) - v0.AddArg2(x, v1) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(31) - v.AddArg2(v0, v2) - return true - } - // match: (Div32 n (Const32 [c])) - // cond: isPowerOfTwo(c) - // result: (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [int64(32-log32(c))]))) (Const64 [int64(log32(c))])) - for { - t := v.Type - n := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(isPowerOfTwo(c)) { - break - } - v.reset(OpRsh32x64) - v0 := b.NewValue0(v.Pos, OpAdd32, t) - v1 := b.NewValue0(v.Pos, OpRsh32Ux64, t) - v2 := b.NewValue0(v.Pos, OpRsh32x64, t) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(31) - v2.AddArg2(n, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(int64(32 - log32(c))) - v1.AddArg2(v2, v4) - v0.AddArg2(n, v1) - v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v5.AuxInt = int64ToAuxInt(int64(log32(c))) - v.AddArg2(v0, v5) - return true - } - // match: (Div32 x (Const32 [c])) - // cond: smagicOK32(c) && config.RegSize == 8 - // result: (Sub32 (Rsh64x64 (Mul64 (Const64 [int64(smagic32(c).m)]) (SignExt32to64 x)) (Const64 [32+smagic32(c).s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) - for { - t := v.Type - x := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(smagicOK32(c) && config.RegSize == 8) { - break - } - v.reset(OpSub32) - v.Type = t - v0 := b.NewValue0(v.Pos, OpRsh64x64, t) - v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(int64(smagic32(c).m)) - v3 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) - v3.AddArg(x) - v1.AddArg2(v2, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(32 + smagic32(c).s) - v0.AddArg2(v1, v4) - v5 := b.NewValue0(v.Pos, OpRsh64x64, t) - v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v6.AuxInt = int64ToAuxInt(63) - v5.AddArg2(v3, v6) - v.AddArg2(v0, v5) - return true - } - // match: (Div32 x (Const32 [c])) - // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul - // result: (Sub32 (Rsh32x64 (Hmul32 (Const32 [int32(smagic32(c).m/2)]) x) (Const64 [smagic32(c).s-1])) (Rsh32x64 x (Const64 [31]))) - for { - t := v.Type - x := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul) { - break - } - v.reset(OpSub32) - v.Type = t - v0 := b.NewValue0(v.Pos, OpRsh32x64, t) - v1 := b.NewValue0(v.Pos, OpHmul32, t) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(smagic32(c).m / 2)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(smagic32(c).s - 1) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpRsh32x64, t) - v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v5.AuxInt = int64ToAuxInt(31) - v4.AddArg2(x, v5) - v.AddArg2(v0, v4) - return true - } - // match: (Div32 x (Const32 [c])) - // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul - // result: (Sub32 (Rsh32x64 (Add32 (Hmul32 (Const32 [int32(smagic32(c).m)]) x) x) (Const64 [smagic32(c).s])) (Rsh32x64 x (Const64 [31]))) - for { - t := v.Type - x := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul) { - break - } - v.reset(OpSub32) - v.Type = t - v0 := b.NewValue0(v.Pos, OpRsh32x64, t) - v1 := b.NewValue0(v.Pos, OpAdd32, t) - v2 := b.NewValue0(v.Pos, OpHmul32, t) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(int32(smagic32(c).m)) - v2.AddArg2(v3, x) - v1.AddArg2(v2, x) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(smagic32(c).s) - v0.AddArg2(v1, v4) - v5 := b.NewValue0(v.Pos, OpRsh32x64, t) - v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v6.AuxInt = int64ToAuxInt(31) - v5.AddArg2(x, v6) - v.AddArg2(v0, v5) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(31) + v.AddArg2(v0, v2) return true } return false @@ -7396,7 +8642,6 @@ func rewriteValuegeneric_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32u (Const32 [c]) (Const32 [d])) // cond: d != 0 @@ -7418,7 +8663,7 @@ func rewriteValuegeneric_OpDiv32u(v *Value) bool { return true } // match: (Div32u n (Const32 [c])) - // cond: isUnsignedPowerOfTwo(uint32(c)) + // cond: isPowerOfTwo(uint32(c)) // result: (Rsh32Ux64 n (Const64 [log32u(uint32(c))])) for { n := v_0 @@ -7426,7 +8671,7 @@ func rewriteValuegeneric_OpDiv32u(v *Value) bool { break } c := auxIntToInt32(v_1.AuxInt) - if !(isUnsignedPowerOfTwo(uint32(c))) { + if !(isPowerOfTwo(uint32(c))) { break } v.reset(OpRsh32Ux64) @@ -7435,176 +8680,12 @@ func rewriteValuegeneric_OpDiv32u(v *Value) bool { v.AddArg2(n, v0) return true } - // match: (Div32u x (Const32 [c])) - // cond: umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul - // result: (Rsh32Ux64 (Hmul32u (Const32 [int32(1<<31+umagic32(c).m/2)]) x) (Const64 [umagic32(c).s-1])) - for { - x := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul) { - break - } - v.reset(OpRsh32Ux64) - v.Type = typ.UInt32 - v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v1.AuxInt = int32ToAuxInt(int32(1<<31 + umagic32(c).m/2)) - v0.AddArg2(v1, x) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(umagic32(c).s - 1) - v.AddArg2(v0, v2) - return true - } - // match: (Div32u x (Const32 [c])) - // cond: umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul - // result: (Rsh32Ux64 (Hmul32u (Const32 [int32(1<<31+(umagic32(c).m+1)/2)]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [umagic32(c).s-2])) - for { - x := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul) { - break - } - v.reset(OpRsh32Ux64) - v.Type = typ.UInt32 - v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v1.AuxInt = int32ToAuxInt(int32(1<<31 + (umagic32(c).m+1)/2)) - v2 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(1) - v2.AddArg2(x, v3) - v0.AddArg2(v1, v2) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(umagic32(c).s - 2) - v.AddArg2(v0, v4) - return true - } - // match: (Div32u x (Const32 [c])) - // cond: umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul - // result: (Rsh32Ux64 (Avg32u x (Hmul32u (Const32 [int32(umagic32(c).m)]) x)) (Const64 [umagic32(c).s-1])) - for { - x := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul) { - break - } - v.reset(OpRsh32Ux64) - v.Type = typ.UInt32 - v0 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(umagic32(c).m)) - v1.AddArg2(v2, x) - v0.AddArg2(x, v1) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(umagic32(c).s - 1) - v.AddArg2(v0, v3) - return true - } - // match: (Div32u x (Const32 [c])) - // cond: umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0 - // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+umagic32(c).m/2)]) (ZeroExt32to64 x)) (Const64 [32+umagic32(c).s-1]))) - for { - x := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0) { - break - } - v.reset(OpTrunc64to32) - v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(int64(1<<31 + umagic32(c).m/2)) - v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v3.AddArg(x) - v1.AddArg2(v2, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) - v0.AddArg2(v1, v4) - v.AddArg(v0) - return true - } - // match: (Div32u x (Const32 [c])) - // cond: umagicOK32(c) && config.RegSize == 8 && c&1 == 0 - // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+(umagic32(c).m+1)/2)]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [32+umagic32(c).s-2]))) - for { - x := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(umagicOK32(c) && config.RegSize == 8 && c&1 == 0) { - break - } - v.reset(OpTrunc64to32) - v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(int64(1<<31 + (umagic32(c).m+1)/2)) - v3 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) - v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v4.AddArg(x) - v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v5.AuxInt = int64ToAuxInt(1) - v3.AddArg2(v4, v5) - v1.AddArg2(v2, v3) - v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v6.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 2) - v0.AddArg2(v1, v6) - v.AddArg(v0) - return true - } - // match: (Div32u x (Const32 [c])) - // cond: umagicOK32(c) && config.RegSize == 8 && config.useAvg - // result: (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) (Mul64 (Const64 [int64(umagic32(c).m)]) (ZeroExt32to64 x))) (Const64 [32+umagic32(c).s-1]))) - for { - x := v_0 - if v_1.Op != OpConst32 { - break - } - c := auxIntToInt32(v_1.AuxInt) - if !(umagicOK32(c) && config.RegSize == 8 && config.useAvg) { - break - } - v.reset(OpTrunc64to32) - v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) - v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v3.AddArg(x) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(32) - v2.AddArg2(v3, v4) - v5 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt32) - v6.AuxInt = int64ToAuxInt(int64(umagic32(c).m)) - v5.AddArg2(v6, v3) - v1.AddArg2(v2, v5) - v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v7.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) - v0.AddArg2(v1, v7) - v.AddArg(v0) - return true - } return false } func rewriteValuegeneric_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64 (Const64 [c]) (Const64 [d])) // cond: d != 0 @@ -7625,36 +8706,6 @@ func rewriteValuegeneric_OpDiv64(v *Value) bool { v.AuxInt = int64ToAuxInt(c / d) return true } - // match: (Div64 n (Const64 [c])) - // cond: isNonNegative(n) && isPowerOfTwo(c) - // result: (Rsh64Ux64 n (Const64 [log64(c)])) - for { - n := v_0 - if v_1.Op != OpConst64 { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(isNonNegative(n) && isPowerOfTwo(c)) { - break - } - v.reset(OpRsh64Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v0.AuxInt = int64ToAuxInt(log64(c)) - v.AddArg2(n, v0) - return true - } - // match: (Div64 n (Const64 [-1<<63])) - // cond: isNonNegative(n) - // result: (Const64 [0]) - for { - n := v_0 - if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 || !(isNonNegative(n)) { - break - } - v.reset(OpConst64) - v.AuxInt = int64ToAuxInt(0) - return true - } // match: (Div64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Neg64 (Div64 n (Const64 [-c]))) @@ -7676,6 +8727,18 @@ func rewriteValuegeneric_OpDiv64(v *Value) bool { v.AddArg(v0) return true } + // match: (Div64 x (Const64 [-1<<63])) + // cond: isNonNegative(x) + // result: (Const64 [0]) + for { + x := v_0 + if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 || !(isNonNegative(x)) { + break + } + v.reset(OpConst64) + v.AuxInt = int64ToAuxInt(0) + return true + } // match: (Div64 x (Const64 [-1<<63])) // result: (Rsh64Ux64 (And64 x (Neg64 x)) (Const64 [63])) for { @@ -7694,97 +8757,6 @@ func rewriteValuegeneric_OpDiv64(v *Value) bool { v.AddArg2(v0, v2) return true } - // match: (Div64 n (Const64 [c])) - // cond: isPowerOfTwo(c) - // result: (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [int64(64-log64(c))]))) (Const64 [int64(log64(c))])) - for { - t := v.Type - n := v_0 - if v_1.Op != OpConst64 { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(isPowerOfTwo(c)) { - break - } - v.reset(OpRsh64x64) - v0 := b.NewValue0(v.Pos, OpAdd64, t) - v1 := b.NewValue0(v.Pos, OpRsh64Ux64, t) - v2 := b.NewValue0(v.Pos, OpRsh64x64, t) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(63) - v2.AddArg2(n, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(int64(64 - log64(c))) - v1.AddArg2(v2, v4) - v0.AddArg2(n, v1) - v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v5.AuxInt = int64ToAuxInt(int64(log64(c))) - v.AddArg2(v0, v5) - return true - } - // match: (Div64 x (Const64 [c])) - // cond: smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul - // result: (Sub64 (Rsh64x64 (Hmul64 (Const64 [int64(smagic64(c).m/2)]) x) (Const64 [smagic64(c).s-1])) (Rsh64x64 x (Const64 [63]))) - for { - t := v.Type - x := v_0 - if v_1.Op != OpConst64 { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul) { - break - } - v.reset(OpSub64) - v.Type = t - v0 := b.NewValue0(v.Pos, OpRsh64x64, t) - v1 := b.NewValue0(v.Pos, OpHmul64, t) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(int64(smagic64(c).m / 2)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(smagic64(c).s - 1) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpRsh64x64, t) - v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v5.AuxInt = int64ToAuxInt(63) - v4.AddArg2(x, v5) - v.AddArg2(v0, v4) - return true - } - // match: (Div64 x (Const64 [c])) - // cond: smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul - // result: (Sub64 (Rsh64x64 (Add64 (Hmul64 (Const64 [int64(smagic64(c).m)]) x) x) (Const64 [smagic64(c).s])) (Rsh64x64 x (Const64 [63]))) - for { - t := v.Type - x := v_0 - if v_1.Op != OpConst64 { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul) { - break - } - v.reset(OpSub64) - v.Type = t - v0 := b.NewValue0(v.Pos, OpRsh64x64, t) - v1 := b.NewValue0(v.Pos, OpAdd64, t) - v2 := b.NewValue0(v.Pos, OpHmul64, t) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(int64(smagic64(c).m)) - v2.AddArg2(v3, x) - v1.AddArg2(v2, x) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(smagic64(c).s) - v0.AddArg2(v1, v4) - v5 := b.NewValue0(v.Pos, OpRsh64x64, t) - v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v6.AuxInt = int64ToAuxInt(63) - v5.AddArg2(x, v6) - v.AddArg2(v0, v5) - return true - } return false } func rewriteValuegeneric_OpDiv64F(v *Value) bool { @@ -7835,7 +8807,6 @@ func rewriteValuegeneric_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64u (Const64 [c]) (Const64 [d])) // cond: d != 0 @@ -7857,7 +8828,7 @@ func rewriteValuegeneric_OpDiv64u(v *Value) bool { return true } // match: (Div64u n (Const64 [c])) - // cond: isUnsignedPowerOfTwo(uint64(c)) + // cond: isPowerOfTwo(uint64(c)) // result: (Rsh64Ux64 n (Const64 [log64u(uint64(c))])) for { n := v_0 @@ -7865,7 +8836,7 @@ func rewriteValuegeneric_OpDiv64u(v *Value) bool { break } c := auxIntToInt64(v_1.AuxInt) - if !(isUnsignedPowerOfTwo(uint64(c))) { + if !(isPowerOfTwo(uint64(c))) { break } v.reset(OpRsh64Ux64) @@ -7874,141 +8845,6 @@ func rewriteValuegeneric_OpDiv64u(v *Value) bool { v.AddArg2(n, v0) return true } - // match: (Div64u x (Const64 [c])) - // cond: c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul - // result: (Add64 (Add64 (Add64 (Lsh64x64 (ZeroExt32to64 (Div32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)]))) (Const64 [32])) (ZeroExt32to64 (Div32u (Trunc64to32 x) (Const32 [int32(c)])))) (Mul64 (ZeroExt32to64 (Mod32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)]))) (Const64 [int64((1<<32)/c)]))) (ZeroExt32to64 (Div32u (Add32 (Mod32u (Trunc64to32 x) (Const32 [int32(c)])) (Mul32 (Mod32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)])) (Const32 [int32((1<<32)%c)]))) (Const32 [int32(c)])))) - for { - x := v_0 - if v_1.Op != OpConst64 { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul) { - break - } - v.reset(OpAdd64) - v0 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) - v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v4 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) - v5 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) - v6 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) - v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v7.AuxInt = int64ToAuxInt(32) - v6.AddArg2(x, v7) - v5.AddArg(v6) - v8 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v8.AuxInt = int32ToAuxInt(int32(c)) - v4.AddArg2(v5, v8) - v3.AddArg(v4) - v2.AddArg2(v3, v7) - v9 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v10 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) - v11 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) - v11.AddArg(x) - v10.AddArg2(v11, v8) - v9.AddArg(v10) - v1.AddArg2(v2, v9) - v12 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v13 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v14 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) - v14.AddArg2(v5, v8) - v13.AddArg(v14) - v15 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v15.AuxInt = int64ToAuxInt(int64((1 << 32) / c)) - v12.AddArg2(v13, v15) - v0.AddArg2(v1, v12) - v16 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) - v17 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) - v18 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) - v19 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) - v19.AddArg2(v11, v8) - v20 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v21 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v21.AuxInt = int32ToAuxInt(int32((1 << 32) % c)) - v20.AddArg2(v14, v21) - v18.AddArg2(v19, v20) - v17.AddArg2(v18, v8) - v16.AddArg(v17) - v.AddArg2(v0, v16) - return true - } - // match: (Div64u x (Const64 [c])) - // cond: umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul - // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+umagic64(c).m/2)]) x) (Const64 [umagic64(c).s-1])) - for { - x := v_0 - if v_1.Op != OpConst64 { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul) { - break - } - v.reset(OpRsh64Ux64) - v.Type = typ.UInt64 - v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v1.AuxInt = int64ToAuxInt(int64(1<<63 + umagic64(c).m/2)) - v0.AddArg2(v1, x) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(umagic64(c).s - 1) - v.AddArg2(v0, v2) - return true - } - // match: (Div64u x (Const64 [c])) - // cond: umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul - // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+(umagic64(c).m+1)/2)]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [umagic64(c).s-2])) - for { - x := v_0 - if v_1.Op != OpConst64 { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul) { - break - } - v.reset(OpRsh64Ux64) - v.Type = typ.UInt64 - v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v1.AuxInt = int64ToAuxInt(int64(1<<63 + (umagic64(c).m+1)/2)) - v2 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(1) - v2.AddArg2(x, v3) - v0.AddArg2(v1, v2) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(umagic64(c).s - 2) - v.AddArg2(v0, v4) - return true - } - // match: (Div64u x (Const64 [c])) - // cond: umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul - // result: (Rsh64Ux64 (Avg64u x (Hmul64u (Const64 [int64(umagic64(c).m)]) x)) (Const64 [umagic64(c).s-1])) - for { - x := v_0 - if v_1.Op != OpConst64 { - break - } - c := auxIntToInt64(v_1.AuxInt) - if !(umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul) { - break - } - v.reset(OpRsh64Ux64) - v.Type = typ.UInt64 - v0 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(int64(umagic64(c).m)) - v1.AddArg2(v2, x) - v0.AddArg2(x, v1) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(umagic64(c).s - 1) - v.AddArg2(v0, v3) - return true - } return false } func rewriteValuegeneric_OpDiv8(v *Value) bool { @@ -8035,24 +8871,6 @@ func rewriteValuegeneric_OpDiv8(v *Value) bool { v.AuxInt = int8ToAuxInt(c / d) return true } - // match: (Div8 n (Const8 [c])) - // cond: isNonNegative(n) && isPowerOfTwo(c) - // result: (Rsh8Ux64 n (Const64 [log8(c)])) - for { - n := v_0 - if v_1.Op != OpConst8 { - break - } - c := auxIntToInt8(v_1.AuxInt) - if !(isNonNegative(n) && isPowerOfTwo(c)) { - break - } - v.reset(OpRsh8Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v0.AuxInt = int64ToAuxInt(log8(c)) - v.AddArg2(n, v0) - return true - } // match: (Div8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Neg8 (Div8 n (Const8 [-c]))) @@ -8067,90 +8885,29 @@ func rewriteValuegeneric_OpDiv8(v *Value) bool { break } v.reset(OpNeg8) - v0 := b.NewValue0(v.Pos, OpDiv8, t) - v1 := b.NewValue0(v.Pos, OpConst8, t) - v1.AuxInt = int8ToAuxInt(-c) - v0.AddArg2(n, v1) - v.AddArg(v0) - return true - } - // match: (Div8 x (Const8 [-1<<7 ])) - // result: (Rsh8Ux64 (And8 x (Neg8 x)) (Const64 [7 ])) - for { - t := v.Type - x := v_0 - if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != -1<<7 { - break - } - v.reset(OpRsh8Ux64) - v0 := b.NewValue0(v.Pos, OpAnd8, t) - v1 := b.NewValue0(v.Pos, OpNeg8, t) - v1.AddArg(x) - v0.AddArg2(x, v1) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(7) - v.AddArg2(v0, v2) - return true - } - // match: (Div8 n (Const8 [c])) - // cond: isPowerOfTwo(c) - // result: (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [int64( 8-log8(c))]))) (Const64 [int64(log8(c))])) - for { - t := v.Type - n := v_0 - if v_1.Op != OpConst8 { - break - } - c := auxIntToInt8(v_1.AuxInt) - if !(isPowerOfTwo(c)) { - break - } - v.reset(OpRsh8x64) - v0 := b.NewValue0(v.Pos, OpAdd8, t) - v1 := b.NewValue0(v.Pos, OpRsh8Ux64, t) - v2 := b.NewValue0(v.Pos, OpRsh8x64, t) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(7) - v2.AddArg2(n, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(int64(8 - log8(c))) - v1.AddArg2(v2, v4) + v0 := b.NewValue0(v.Pos, OpDiv8, t) + v1 := b.NewValue0(v.Pos, OpConst8, t) + v1.AuxInt = int8ToAuxInt(-c) v0.AddArg2(n, v1) - v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v5.AuxInt = int64ToAuxInt(int64(log8(c))) - v.AddArg2(v0, v5) + v.AddArg(v0) return true } - // match: (Div8 x (Const8 [c])) - // cond: smagicOK8(c) - // result: (Sub8 (Rsh32x64 (Mul32 (Const32 [int32(smagic8(c).m)]) (SignExt8to32 x)) (Const64 [8+smagic8(c).s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) + // match: (Div8 x (Const8 [-1<<7 ])) + // result: (Rsh8Ux64 (And8 x (Neg8 x)) (Const64 [7 ])) for { t := v.Type x := v_0 - if v_1.Op != OpConst8 { - break - } - c := auxIntToInt8(v_1.AuxInt) - if !(smagicOK8(c)) { + if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != -1<<7 { break } - v.reset(OpSub8) - v.Type = t - v0 := b.NewValue0(v.Pos, OpRsh32x64, t) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(smagic8(c).m)) - v3 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v3.AddArg(x) - v1.AddArg2(v2, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(8 + smagic8(c).s) - v0.AddArg2(v1, v4) - v5 := b.NewValue0(v.Pos, OpRsh32x64, t) - v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v6.AuxInt = int64ToAuxInt(31) - v5.AddArg2(v3, v6) - v.AddArg2(v0, v5) + v.reset(OpRsh8Ux64) + v0 := b.NewValue0(v.Pos, OpAnd8, t) + v1 := b.NewValue0(v.Pos, OpNeg8, t) + v1.AddArg(x) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v2.AuxInt = int64ToAuxInt(7) + v.AddArg2(v0, v2) return true } return false @@ -8180,7 +8937,7 @@ func rewriteValuegeneric_OpDiv8u(v *Value) bool { return true } // match: (Div8u n (Const8 [c])) - // cond: isUnsignedPowerOfTwo(uint8(c)) + // cond: isPowerOfTwo(uint8(c)) // result: (Rsh8Ux64 n (Const64 [log8u(uint8(c))])) for { n := v_0 @@ -8188,7 +8945,7 @@ func rewriteValuegeneric_OpDiv8u(v *Value) bool { break } c := auxIntToInt8(v_1.AuxInt) - if !(isUnsignedPowerOfTwo(uint8(c))) { + if !(isPowerOfTwo(uint8(c))) { break } v.reset(OpRsh8Ux64) @@ -8197,32 +8954,6 @@ func rewriteValuegeneric_OpDiv8u(v *Value) bool { v.AddArg2(n, v0) return true } - // match: (Div8u x (Const8 [c])) - // cond: umagicOK8(c) - // result: (Trunc32to8 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<8+umagic8(c).m)]) (ZeroExt8to32 x)) (Const64 [8+umagic8(c).s]))) - for { - x := v_0 - if v_1.Op != OpConst8 { - break - } - c := auxIntToInt8(v_1.AuxInt) - if !(umagicOK8(c)) { - break - } - v.reset(OpTrunc32to8) - v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(1<<8 + umagic8(c).m)) - v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) - v3.AddArg(x) - v1.AddArg2(v2, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(8 + umagic8(c).s) - v0.AddArg2(v1, v4) - v.AddArg(v0) - return true - } return false } func rewriteValuegeneric_OpEq16(v *Value) bool { @@ -8242,7 +8973,8 @@ func rewriteValuegeneric_OpEq16(v *Value) bool { v.AuxInt = boolToAuxInt(true) return true } - // match: (Eq16 (Const16 [c]) (Add16 (Const16 [d]) x)) + // match: (Eq16 (Const16 [c]) o:(Add16 (Const16 [d]) x)) + // cond: o.Uses == 1 // result: (Eq16 (Const16 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { @@ -8251,18 +8983,22 @@ func rewriteValuegeneric_OpEq16(v *Value) bool { } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) - if v_1.Op != OpAdd16 { + o := v_1 + if o.Op != OpAdd16 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst16 || v_1_0.Type != t { + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst16 { + continue + } + d := auxIntToInt16(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { continue } - d := auxIntToInt16(v_1_0.AuxInt) - x := v_1_1 v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) @@ -8272,524 +9008,270 @@ func rewriteValuegeneric_OpEq16(v *Value) bool { } break } - // match: (Eq16 (Const16 [c]) (Const16 [d])) - // result: (ConstBool [c == d]) + // match: (Eq16 (Const16 [c]) o:(Sub16 x (Const16 [d]))) + // cond: o.Uses == 1 + // result: (Eq16 (Const16 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } + t := v_0.Type c := auxIntToInt16(v_0.AuxInt) - if v_1.Op != OpConst16 { + o := v_1 + if o.Op != OpSub16 { continue } - d := auxIntToInt16(v_1.AuxInt) - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(c == d) + _ = o.Args[1] + x := o.Args[0] + o_1 := o.Args[1] + if o_1.Op != OpConst16 { + continue + } + d := auxIntToInt16(o_1.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(c + d) + v.AddArg2(v0, x) return true } break } - // match: (Eq16 (Mod16u x (Const16 [c])) (Const16 [0])) - // cond: x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config) - // result: (Eq32 (Mod32u (ZeroExt16to32 x) (Const32 [int32(uint16(c))])) (Const32 [0])) + // match: (Eq16 (Const16 [c]) o:(Sub16 (Const16 [d]) x)) + // cond: o.Uses == 1 + // result: (Eq16 (Const16 [d-c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpMod16u { + if v_0.Op != OpConst16 { continue } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpConst16 { + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpSub16 { continue } - c := auxIntToInt16(v_0_1.AuxInt) - if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config)) { + x := o.Args[1] + o_0 := o.Args[0] + if o_0.Op != OpConst16 { continue } - v.reset(OpEq32) - v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(uint16(c))) - v0.AddArg2(v1, v2) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(0) - v.AddArg2(v0, v3) + d := auxIntToInt16(o_0.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(d - c) + v.AddArg2(v0, x) return true } break } - // match: (Eq16 (Mod16 x (Const16 [c])) (Const16 [0])) - // cond: x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config) - // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [int32(c)])) (Const32 [0])) + // match: (Eq16 (Const16 [c]) o:(Xor16 (Const16 [d]) x)) + // cond: o.Uses == 1 + // result: (Eq16 (Const16 [d^c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpMod16 { + if v_0.Op != OpConst16 { continue } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpConst16 { + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpXor16 { continue } - c := auxIntToInt16(v_0_1.AuxInt) - if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config)) { - continue + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst16 { + continue + } + d := auxIntToInt16(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { + continue + } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(d ^ c) + v.AddArg2(v0, x) + return true } - v.reset(OpEq32) - v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) - v2.AuxInt = int32ToAuxInt(int32(c)) - v0.AddArg2(v1, v2) - v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) - v3.AuxInt = int32ToAuxInt(0) - v.AddArg2(v0, v3) - return true } break } - // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s && x.Op != OpConst16 && udivisibleOK16(c) - // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) + // match: (Eq16 (Const16 [c]) o:(Com16 x)) + // cond: o.Uses == 1 + // result: (Eq16 (Const16 [^c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul16 { + if v_0.Op != OpConst16 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst16 { - continue - } - c := auxIntToInt16(v_1_0.AuxInt) - if v_1_1.Op != OpTrunc64to16 { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh64Ux64 { - continue - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul64 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst64 { - continue - } - m := auxIntToInt64(mul_0.AuxInt) - if mul_1.Op != OpZeroExt16to64 || x != mul_1.Args[0] { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s && x.Op != OpConst16 && udivisibleOK16(c)) { - continue - } - v.reset(OpLeq16U) - v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) - v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) - v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) - v.AddArg2(v0, v4) - return true - } + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpCom16 { + continue } + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(^c) + v.AddArg2(v0, x) + return true } break } - // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c) - // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) + // match: (Eq16 (Const16 [c]) o:(Neg16 x)) + // cond: o.Uses == 1 + // result: (Eq16 (Const16 [-c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul16 { + if v_0.Op != OpConst16 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst16 { - continue - } - c := auxIntToInt16(v_1_0.AuxInt) - if v_1_1.Op != OpTrunc32to16 { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh32Ux64 { - continue - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul32 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if mul_1.Op != OpZeroExt16to32 || x != mul_1.Args[0] { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c)) { - continue - } - v.reset(OpLeq16U) - v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) - v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) - v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) - v.AddArg2(v0, v4) - return true - } + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpNeg16 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(-c) + v.AddArg2(v0, x) + return true } break } - // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 && x.Op != OpConst16 && udivisibleOK16(c) - // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) + // match: (Eq16 (Const16 [c]) o:(Mul16 (Const16 [d]) x)) + // cond: uint16(d)%2 == 1 && o.Uses == 1 + // result: (Eq16 (Const16 [int16(uint16(c) * uint16(modularMultiplicativeInverse(uint64(d))))]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul16 { + if v_0.Op != OpConst16 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst16 { - continue - } - c := auxIntToInt16(v_1_0.AuxInt) - if v_1_1.Op != OpTrunc32to16 { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh32Ux64 { + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpMul16 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst16 { continue } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul32 { + d := auxIntToInt16(o_0.AuxInt) + x := o_1 + if !(uint16(d)%2 == 1 && o.Uses == 1) { continue } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if mul_1.Op != OpRsh32Ux64 { - continue - } - _ = mul_1.Args[1] - mul_1_0 := mul_1.Args[0] - if mul_1_0.Op != OpZeroExt16to32 || x != mul_1_0.Args[0] { - continue - } - mul_1_1 := mul_1.Args[1] - if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 && x.Op != OpConst16 && udivisibleOK16(c)) { - continue - } - v.reset(OpLeq16U) - v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) - v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) - v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) - v.AddArg2(v0, v4) - return true - } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(int16(uint16(c) * uint16(modularMultiplicativeInverse(uint64(d))))) + v.AddArg2(v0, x) + return true } } break } - // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c) - // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) + // match: (Eq16 (Const16 [c]) (Const16 [d])) + // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul16 { + if v_0.Op != OpConst16 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst16 { - continue - } - c := auxIntToInt16(v_1_0.AuxInt) - if v_1_1.Op != OpTrunc32to16 { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh32Ux64 { - continue - } - _ = v_1_1_0.Args[1] - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAvg32u { - continue - } - _ = v_1_1_0_0.Args[1] - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpLsh32x64 { - continue - } - _ = v_1_1_0_0_0.Args[1] - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpZeroExt16to32 || x != v_1_1_0_0_0_0.Args[0] { - continue - } - v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] - if v_1_1_0_0_0_1.Op != OpConst64 || auxIntToInt64(v_1_1_0_0_0_1.AuxInt) != 16 { - continue - } - mul := v_1_1_0_0.Args[1] - if mul.Op != OpMul32 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if mul_1.Op != OpZeroExt16to32 || x != mul_1.Args[0] { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c)) { - continue - } - v.reset(OpLeq16U) - v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) - v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) - v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) - v.AddArg2(v0, v4) - return true - } + c := auxIntToInt16(v_0.AuxInt) + if v_1.Op != OpConst16 { + continue } + d := auxIntToInt16(v_1.AuxInt) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(c == d) + return true } break } - // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic16(c).m) && s == 16+smagic16(c).s && x.Op != OpConst16 && sdivisibleOK16(c) - // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int16(sdivisible16(c).m)]) x) (Const16 [int16(sdivisible16(c).a)]) ) (Const16 [int16(16-sdivisible16(c).k)]) ) (Const16 [int16(sdivisible16(c).max)]) ) + // match: (Eq16 (Mod16u x (Const16 [c])) (Const16 [0])) + // cond: x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32u (ZeroExt16to32 x) (Const32 [int32(uint16(c))])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul16 { + if v_0.Op != OpMod16u { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst16 { - continue - } - c := auxIntToInt16(v_1_0.AuxInt) - if v_1_1.Op != OpSub16 { - continue - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh32x64 { - continue - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul32 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if mul_1.Op != OpSignExt16to32 || x != mul_1.Args[0] { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpRsh32x64 { - continue - } - _ = v_1_1_1.Args[1] - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpSignExt16to32 || x != v_1_1_1_0.Args[0] { - continue - } - v_1_1_1_1 := v_1_1_1.Args[1] - if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic16(c).m) && s == 16+smagic16(c).s && x.Op != OpConst16 && sdivisibleOK16(c)) { - continue - } - v.reset(OpLeq16U) - v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) - v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) - v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) - v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v3.AuxInt = int16ToAuxInt(int16(sdivisible16(c).m)) - v2.AddArg2(v3, x) - v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v4.AuxInt = int16ToAuxInt(int16(sdivisible16(c).a)) - v1.AddArg2(v2, v4) - v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v5.AuxInt = int16ToAuxInt(int16(16 - sdivisible16(c).k)) - v0.AddArg2(v1, v5) - v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v6.AuxInt = int16ToAuxInt(int16(sdivisible16(c).max)) - v.AddArg2(v0, v6) - return true - } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_0_1.AuxInt) + if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config)) { + continue } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v2.AuxInt = int32ToAuxInt(int32(uint16(c))) + v0.AddArg2(v1, v2) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int32ToAuxInt(0) + v.AddArg2(v0, v3) + return true } break } - // match: (Eq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) - // cond: k > 0 && k < 15 && kbar == 16 - k - // result: (Eq16 (And16 n (Const16 [1< [0])) + // match: (Eq16 (Mod16 x (Const16 [c])) (Const16 [0])) + // cond: x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [int32(c)])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpLsh16x64 { + if v_0.Op != OpMod16 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRsh16x64 { + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst16 { continue } - _ = v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAdd16 { + c := auxIntToInt16(v_0_1.AuxInt) + if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config)) { continue } - t := v_1_0_0.Type - _ = v_1_0_0.Args[1] - v_1_0_0_0 := v_1_0_0.Args[0] - v_1_0_0_1 := v_1_0_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { - if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh16Ux64 || v_1_0_0_1.Type != t { - continue - } - _ = v_1_0_0_1.Args[1] - v_1_0_0_1_0 := v_1_0_0_1.Args[0] - if v_1_0_0_1_0.Op != OpRsh16x64 || v_1_0_0_1_0.Type != t { - continue - } - _ = v_1_0_0_1_0.Args[1] - if n != v_1_0_0_1_0.Args[0] { - continue - } - v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] - if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 15 { - continue - } - v_1_0_0_1_1 := v_1_0_0_1.Args[1] - if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { - continue - } - kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { - continue - } - k := auxIntToInt64(v_1_0_1.AuxInt) - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 15 && kbar == 16-k) { - continue - } - v.reset(OpEq16) - v0 := b.NewValue0(v.Pos, OpAnd16, t) - v1 := b.NewValue0(v.Pos, OpConst16, t) - v1.AuxInt = int16ToAuxInt(1< [c]) (Add32 (Const32 [d]) x)) - // result: (Eq32 (Const32 [c-d]) x) + // match: (Eq16 (ZeroExt8to16 (CvtBoolToUint8 x)) (Const16 [1])) + // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpConst32 { - continue - } - t := v_0.Type - c := auxIntToInt32(v_0.AuxInt) - if v_1.Op != OpAdd32 { + if v_0.Op != OpZeroExt8to16 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 || v_1_0.Type != t { - continue - } - d := auxIntToInt32(v_1_0.AuxInt) - x := v_1_1 - v.reset(OpEq32) - v0 := b.NewValue0(v.Pos, OpConst32, t) - v0.AuxInt = int32ToAuxInt(c - d) - v.AddArg2(v0, x) - return true - } - } - break - } - // match: (Eq32 (Const32 [c]) (Const32 [d])) - // result: (ConstBool [c == d]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpConst32 { + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpCvtBoolToUint8 { continue } - c := auxIntToInt32(v_0.AuxInt) - if v_1.Op != OpConst32 { + x := v_0_0.Args[0] + if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 1 { continue } - d := auxIntToInt32(v_1.AuxInt) - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(c == d) + v.copyOf(x) return true } break } - // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) - // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) + // match: (Eq16 (ZeroExt8to16 (CvtBoolToUint8 x)) (Const16 [0])) + // result: (Not x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul32 { + if v_0.Op != OpZeroExt8to16 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 { - continue - } - c := auxIntToInt32(v_1_0.AuxInt) - if v_1_1.Op != OpRsh32Ux64 { - continue - } - _ = v_1_1.Args[1] - mul := v_1_1.Args[0] - if mul.Op != OpHmul32u { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if x != mul_1 { - continue - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { - continue - } - v.reset(OpLeq32U) - v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) - v.AddArg2(v0, v4) - return true - } - } - } - break - } - // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c) - // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul32 { + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpCvtBoolToUint8 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 { - continue - } - c := auxIntToInt32(v_1_0.AuxInt) - if v_1_1.Op != OpRsh32Ux64 { - continue - } - _ = v_1_1.Args[1] - mul := v_1_1.Args[0] - if mul.Op != OpHmul32u { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 || mul_0.Type != typ.UInt32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if mul_1.Op != OpRsh32Ux64 { - continue - } - _ = mul_1.Args[1] - if x != mul_1.Args[0] { - continue - } - mul_1_1 := mul_1.Args[1] - if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { - continue - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c)) { - continue - } - v.reset(OpLeq32U) - v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) - v.AddArg2(v0, v4) - return true - } + x := v_0_0.Args[0] + if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 { + continue } + v.reset(OpNot) + v.AddArg(x) + return true } break } - // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic32(c).m) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) - // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul32 { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 { - continue - } - c := auxIntToInt32(v_1_0.AuxInt) - if v_1_1.Op != OpRsh32Ux64 { - continue - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAvg32u { - continue - } - _ = v_1_1_0.Args[1] - if x != v_1_1_0.Args[0] { - continue - } - mul := v_1_1_0.Args[1] - if mul.Op != OpHmul32u { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if x != mul_1 { - continue - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic32(c).m) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { - continue - } - v.reset(OpLeq32U) - v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) - v.AddArg2(v0, v4) - return true - } - } + return false +} +func rewriteValuegeneric_OpEq32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq32 x x) + // result: (ConstBool [true]) + for { + x := v_0 + if x != v_1 { + break } - break + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(true) + return true } - // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) - // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) + // match: (Eq32 (Const32 [c]) o:(Add32 (Const32 [d]) x)) + // cond: o.Uses == 1 + // result: (Eq32 (Const32 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul32 { + if v_0.Op != OpConst32 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 { - continue - } - c := auxIntToInt32(v_1_0.AuxInt) - if v_1_1.Op != OpTrunc64to32 { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh64Ux64 { + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpAdd32 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst32 { continue } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul64 { + d := auxIntToInt32(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { continue } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst64 { - continue - } - m := auxIntToInt64(mul_0.AuxInt) - if mul_1.Op != OpZeroExt32to64 || x != mul_1.Args[0] { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { - continue - } - v.reset(OpLeq32U) - v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) - v.AddArg2(v0, v4) - return true - } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(c - d) + v.AddArg2(v0, x) + return true } } break } - // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c) - // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) + // match: (Eq32 (Const32 [c]) o:(Sub32 x (Const32 [d]))) + // cond: o.Uses == 1 + // result: (Eq32 (Const32 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul32 { + if v_0.Op != OpConst32 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 { - continue - } - c := auxIntToInt32(v_1_0.AuxInt) - if v_1_1.Op != OpTrunc64to32 { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh64Ux64 { - continue - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul64 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst64 { - continue - } - m := auxIntToInt64(mul_0.AuxInt) - if mul_1.Op != OpRsh64Ux64 { - continue - } - _ = mul_1.Args[1] - mul_1_0 := mul_1.Args[0] - if mul_1_0.Op != OpZeroExt32to64 || x != mul_1_0.Args[0] { - continue - } - mul_1_1 := mul_1.Args[1] - if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c)) { - continue - } - v.reset(OpLeq32U) - v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) - v.AddArg2(v0, v4) - return true - } + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpSub32 { + continue } - } - break - } - // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) - // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul32 { + _ = o.Args[1] + x := o.Args[0] + o_1 := o.Args[1] + if o_1.Op != OpConst32 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 { - continue - } - c := auxIntToInt32(v_1_0.AuxInt) - if v_1_1.Op != OpTrunc64to32 { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh64Ux64 { - continue - } - _ = v_1_1_0.Args[1] - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAvg64u { - continue - } - _ = v_1_1_0_0.Args[1] - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpLsh64x64 { - continue - } - _ = v_1_1_0_0_0.Args[1] - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpZeroExt32to64 || x != v_1_1_0_0_0_0.Args[0] { - continue - } - v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] - if v_1_1_0_0_0_1.Op != OpConst64 || auxIntToInt64(v_1_1_0_0_0_1.AuxInt) != 32 { - continue - } - mul := v_1_1_0_0.Args[1] - if mul.Op != OpMul64 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst64 { - continue - } - m := auxIntToInt64(mul_0.AuxInt) - if mul_1.Op != OpZeroExt32to64 || x != mul_1.Args[0] { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { - continue - } - v.reset(OpLeq32U) - v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) - v.AddArg2(v0, v4) - return true - } + d := auxIntToInt32(o_1.AuxInt) + if !(o.Uses == 1) { + continue } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(c + d) + v.AddArg2(v0, x) + return true } break } - // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic32(c).m) && s == 32+smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c) - // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) + // match: (Eq32 (Const32 [c]) o:(Sub32 (Const32 [d]) x)) + // cond: o.Uses == 1 + // result: (Eq32 (Const32 [d-c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul32 { + if v_0.Op != OpConst32 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 { - continue - } - c := auxIntToInt32(v_1_0.AuxInt) - if v_1_1.Op != OpSub32 { - continue - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh64x64 { - continue - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul64 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst64 { - continue - } - m := auxIntToInt64(mul_0.AuxInt) - if mul_1.Op != OpSignExt32to64 || x != mul_1.Args[0] { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpRsh64x64 { - continue - } - _ = v_1_1_1.Args[1] - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpSignExt32to64 || x != v_1_1_1_0.Args[0] { - continue - } - v_1_1_1_1 := v_1_1_1.Args[1] - if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic32(c).m) && s == 32+smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c)) { - continue - } - v.reset(OpLeq32U) - v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) - v2.AddArg2(v3, x) - v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) - v1.AddArg2(v2, v4) - v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) - v0.AddArg2(v1, v5) - v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) - v.AddArg2(v0, v6) - return true - } + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpSub32 { + continue + } + x := o.Args[1] + o_0 := o.Args[0] + if o_0.Op != OpConst32 { + continue + } + d := auxIntToInt32(o_0.AuxInt) + if !(o.Uses == 1) { + continue } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(d - c) + v.AddArg2(v0, x) + return true } break } - // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 && x.Op != OpConst32 && sdivisibleOK32(c) - // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) + // match: (Eq32 (Const32 [c]) o:(Xor32 (Const32 [d]) x)) + // cond: o.Uses == 1 + // result: (Eq32 (Const32 [d^c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul32 { + if v_0.Op != OpConst32 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 { - continue - } - c := auxIntToInt32(v_1_0.AuxInt) - if v_1_1.Op != OpSub32 { - continue - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh32x64 { + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpXor32 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst32 { continue } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpHmul32 { + d := auxIntToInt32(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { continue } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if x != mul_1 { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpRsh32x64 { - continue - } - _ = v_1_1_1.Args[1] - if x != v_1_1_1.Args[0] { - continue - } - v_1_1_1_1 := v_1_1_1.Args[1] - if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 && x.Op != OpConst32 && sdivisibleOK32(c)) { - continue - } - v.reset(OpLeq32U) - v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) - v2.AddArg2(v3, x) - v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) - v1.AddArg2(v2, v4) - v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) - v0.AddArg2(v1, v5) - v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) - v.AddArg2(v0, v6) - return true - } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(d ^ c) + v.AddArg2(v0, x) + return true } } break } - // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m) && s == smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c) - // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) + // match: (Eq32 (Const32 [c]) o:(Com32 x)) + // cond: o.Uses == 1 + // result: (Eq32 (Const32 [^c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul32 { + if v_0.Op != OpConst32 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 { - continue - } - c := auxIntToInt32(v_1_0.AuxInt) - if v_1_1.Op != OpSub32 { - continue - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh32x64 { - continue - } - _ = v_1_1_0.Args[1] - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAdd32 { - continue - } - _ = v_1_1_0_0.Args[1] - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - v_1_1_0_0_1 := v_1_1_0_0.Args[1] - for _i2 := 0; _i2 <= 1; _i2, v_1_1_0_0_0, v_1_1_0_0_1 = _i2+1, v_1_1_0_0_1, v_1_1_0_0_0 { - mul := v_1_1_0_0_0 - if mul.Op != OpHmul32 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i3 := 0; _i3 <= 1; _i3, mul_0, mul_1 = _i3+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if x != mul_1 || x != v_1_1_0_0_1 { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpRsh32x64 { - continue - } - _ = v_1_1_1.Args[1] - if x != v_1_1_1.Args[0] { - continue - } - v_1_1_1_1 := v_1_1_1.Args[1] - if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m) && s == smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c)) { - continue - } - v.reset(OpLeq32U) - v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) - v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) - v2.AddArg2(v3, x) - v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) - v1.AddArg2(v2, v4) - v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) - v0.AddArg2(v1, v5) - v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) - v.AddArg2(v0, v6) - return true - } - } + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpCom32 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(^c) + v.AddArg2(v0, x) + return true } break } - // match: (Eq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) - // cond: k > 0 && k < 31 && kbar == 32 - k - // result: (Eq32 (And32 n (Const32 [1< [0])) + // match: (Eq32 (Const32 [c]) o:(Neg32 x)) + // cond: o.Uses == 1 + // result: (Eq32 (Const32 [-c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpLsh32x64 { + if v_0.Op != OpConst32 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRsh32x64 { + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpNeg32 { continue } - _ = v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAdd32 { + x := o.Args[0] + if !(o.Uses == 1) { continue } - t := v_1_0_0.Type - _ = v_1_0_0.Args[1] - v_1_0_0_0 := v_1_0_0.Args[0] - v_1_0_0_1 := v_1_0_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { - if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh32Ux64 || v_1_0_0_1.Type != t { - continue - } - _ = v_1_0_0_1.Args[1] - v_1_0_0_1_0 := v_1_0_0_1.Args[0] - if v_1_0_0_1_0.Op != OpRsh32x64 || v_1_0_0_1_0.Type != t { - continue - } - _ = v_1_0_0_1_0.Args[1] - if n != v_1_0_0_1_0.Args[0] { - continue - } - v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] - if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 31 { - continue - } - v_1_0_0_1_1 := v_1_0_0_1.Args[1] - if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { - continue - } - kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(-c) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Eq32 (Const32 [c]) o:(Mul32 (Const32 [d]) x)) + // cond: uint32(d)%2 == 1 && o.Uses == 1 + // result: (Eq32 (Const32 [int32(uint32(c) * uint32(modularMultiplicativeInverse(uint64(d))))]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst32 { + continue + } + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpMul32 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst32 { continue } - k := auxIntToInt64(v_1_0_1.AuxInt) - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 31 && kbar == 32-k) { + d := auxIntToInt32(o_0.AuxInt) + x := o_1 + if !(uint32(d)%2 == 1 && o.Uses == 1) { continue } v.reset(OpEq32) - v0 := b.NewValue0(v.Pos, OpAnd32, t) - v1 := b.NewValue0(v.Pos, OpConst32, t) - v1.AuxInt = int32ToAuxInt(1< [c]) (Add64 (Const64 [d]) x)) + // match: (Eq64 (Const64 [c]) o:(Add64 (Const64 [d]) x)) + // cond: o.Uses == 1 // result: (Eq64 (Const64 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { @@ -9761,18 +9770,22 @@ func rewriteValuegeneric_OpEq64(v *Value) bool { } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) - if v_1.Op != OpAdd64 { + o := v_1 + if o.Op != OpAdd64 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst64 || v_1_0.Type != t { + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst64 { + continue + } + d := auxIntToInt64(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { continue } - d := auxIntToInt64(v_1_0.AuxInt) - x := v_1_1 v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) @@ -9782,462 +9795,209 @@ func rewriteValuegeneric_OpEq64(v *Value) bool { } break } - // match: (Eq64 (Const64 [c]) (Const64 [d])) - // result: (ConstBool [c == d]) + // match: (Eq64 (Const64 [c]) o:(Sub64 x (Const64 [d]))) + // cond: o.Uses == 1 + // result: (Eq64 (Const64 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } + t := v_0.Type c := auxIntToInt64(v_0.AuxInt) - if v_1.Op != OpConst64 { + o := v_1 + if o.Op != OpSub64 { continue } - d := auxIntToInt64(v_1.AuxInt) - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(c == d) + _ = o.Args[1] + x := o.Args[0] + o_1 := o.Args[1] + if o_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(o_1.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpEq64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(c + d) + v.AddArg2(v0, x) return true } break } - // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c) - // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) + // match: (Eq64 (Const64 [c]) o:(Sub64 (Const64 [d]) x)) + // cond: o.Uses == 1 + // result: (Eq64 (Const64 [d-c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul64 { + if v_0.Op != OpConst64 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst64 { - continue - } - c := auxIntToInt64(v_1_0.AuxInt) - if v_1_1.Op != OpRsh64Ux64 { - continue - } - _ = v_1_1.Args[1] - mul := v_1_1.Args[0] - if mul.Op != OpHmul64u { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst64 { - continue - } - m := auxIntToInt64(mul_0.AuxInt) - if x != mul_1 { - continue - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c)) { - continue - } - v.reset(OpLeq64U) - v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) - v.AddArg2(v0, v4) - return true - } + t := v_0.Type + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpSub64 { + continue } - } - break - } - // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 && x.Op != OpConst64 && udivisibleOK64(c) - // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul64 { + x := o.Args[1] + o_0 := o.Args[0] + if o_0.Op != OpConst64 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst64 { - continue - } - c := auxIntToInt64(v_1_0.AuxInt) - if v_1_1.Op != OpRsh64Ux64 { - continue - } - _ = v_1_1.Args[1] - mul := v_1_1.Args[0] - if mul.Op != OpHmul64u { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst64 { - continue - } - m := auxIntToInt64(mul_0.AuxInt) - if mul_1.Op != OpRsh64Ux64 { - continue - } - _ = mul_1.Args[1] - if x != mul_1.Args[0] { - continue - } - mul_1_1 := mul_1.Args[1] - if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { - continue - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 && x.Op != OpConst64 && udivisibleOK64(c)) { - continue - } - v.reset(OpLeq64U) - v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) - v.AddArg2(v0, v4) - return true - } + d := auxIntToInt64(o_0.AuxInt) + if !(o.Uses == 1) { + continue } + v.reset(OpEq64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(d - c) + v.AddArg2(v0, x) + return true } break } - // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic64(c).m) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c) - // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) + // match: (Eq64 (Const64 [c]) o:(Xor64 (Const64 [d]) x)) + // cond: o.Uses == 1 + // result: (Eq64 (Const64 [d^c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul64 { + if v_0.Op != OpConst64 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst64 { - continue - } - c := auxIntToInt64(v_1_0.AuxInt) - if v_1_1.Op != OpRsh64Ux64 { - continue - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAvg64u { - continue - } - _ = v_1_1_0.Args[1] - if x != v_1_1_0.Args[0] { + t := v_0.Type + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpXor64 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst64 { continue } - mul := v_1_1_0.Args[1] - if mul.Op != OpHmul64u { + d := auxIntToInt64(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { continue } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst64 { - continue - } - m := auxIntToInt64(mul_0.AuxInt) - if x != mul_1 { - continue - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic64(c).m) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c)) { - continue - } - v.reset(OpLeq64U) - v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) - v.AddArg2(v0, v4) - return true - } + v.reset(OpEq64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(d ^ c) + v.AddArg2(v0, x) + return true } } break } - // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 && x.Op != OpConst64 && sdivisibleOK64(c) - // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible64(c).m)]) x) (Const64 [int64(sdivisible64(c).a)]) ) (Const64 [64-sdivisible64(c).k]) ) (Const64 [int64(sdivisible64(c).max)]) ) + // match: (Eq64 (Const64 [c]) o:(Com64 x)) + // cond: o.Uses == 1 + // result: (Eq64 (Const64 [^c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul64 { + if v_0.Op != OpConst64 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst64 { - continue - } - c := auxIntToInt64(v_1_0.AuxInt) - if v_1_1.Op != OpSub64 { - continue - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh64x64 { - continue - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpHmul64 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst64 { - continue - } - m := auxIntToInt64(mul_0.AuxInt) - if x != mul_1 { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpRsh64x64 { - continue - } - _ = v_1_1_1.Args[1] - if x != v_1_1_1.Args[0] { - continue - } - v_1_1_1_1 := v_1_1_1.Args[1] - if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 && x.Op != OpConst64 && sdivisibleOK64(c)) { - continue - } - v.reset(OpLeq64U) - v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) - v2.AddArg2(v3, x) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) - v1.AddArg2(v2, v4) - v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v5.AuxInt = int64ToAuxInt(64 - sdivisible64(c).k) - v0.AddArg2(v1, v5) - v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) - v.AddArg2(v0, v6) - return true - } + t := v_0.Type + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpCom64 { + continue } + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpEq64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(^c) + v.AddArg2(v0, x) + return true } break } - // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m) && s == smagic64(c).s && x.Op != OpConst64 && sdivisibleOK64(c) - // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible64(c).m)]) x) (Const64 [int64(sdivisible64(c).a)]) ) (Const64 [64-sdivisible64(c).k]) ) (Const64 [int64(sdivisible64(c).max)]) ) + // match: (Eq64 (Const64 [c]) o:(Neg64 x)) + // cond: o.Uses == 1 + // result: (Eq64 (Const64 [-c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul64 { + if v_0.Op != OpConst64 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst64 { - continue - } - c := auxIntToInt64(v_1_0.AuxInt) - if v_1_1.Op != OpSub64 { - continue - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh64x64 { - continue - } - _ = v_1_1_0.Args[1] - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAdd64 { - continue - } - _ = v_1_1_0_0.Args[1] - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - v_1_1_0_0_1 := v_1_1_0_0.Args[1] - for _i2 := 0; _i2 <= 1; _i2, v_1_1_0_0_0, v_1_1_0_0_1 = _i2+1, v_1_1_0_0_1, v_1_1_0_0_0 { - mul := v_1_1_0_0_0 - if mul.Op != OpHmul64 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i3 := 0; _i3 <= 1; _i3, mul_0, mul_1 = _i3+1, mul_1, mul_0 { - if mul_0.Op != OpConst64 { - continue - } - m := auxIntToInt64(mul_0.AuxInt) - if x != mul_1 || x != v_1_1_0_0_1 { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpRsh64x64 { - continue - } - _ = v_1_1_1.Args[1] - if x != v_1_1_1.Args[0] { - continue - } - v_1_1_1_1 := v_1_1_1.Args[1] - if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m) && s == smagic64(c).s && x.Op != OpConst64 && sdivisibleOK64(c)) { - continue - } - v.reset(OpLeq64U) - v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) - v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) - v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) - v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) - v2.AddArg2(v3, x) - v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) - v1.AddArg2(v2, v4) - v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v5.AuxInt = int64ToAuxInt(64 - sdivisible64(c).k) - v0.AddArg2(v1, v5) - v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) - v.AddArg2(v0, v6) - return true - } - } + t := v_0.Type + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpNeg64 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue } + v.reset(OpEq64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(-c) + v.AddArg2(v0, x) + return true } break } - // match: (Eq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) - // cond: k > 0 && k < 63 && kbar == 64 - k - // result: (Eq64 (And64 n (Const64 [1< [0])) + // match: (Eq64 (Const64 [c]) o:(Mul64 (Const64 [d]) x)) + // cond: uint64(d)%2 == 1 && o.Uses == 1 + // result: (Eq64 (Const64 [int64(uint64(c) * modularMultiplicativeInverse(uint64(d))) ]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpLsh64x64 { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRsh64x64 { + if v_0.Op != OpConst64 { continue } - _ = v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAdd64 { + t := v_0.Type + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpMul64 { continue } - t := v_1_0_0.Type - _ = v_1_0_0.Args[1] - v_1_0_0_0 := v_1_0_0.Args[0] - v_1_0_0_1 := v_1_0_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { - if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh64Ux64 || v_1_0_0_1.Type != t { - continue - } - _ = v_1_0_0_1.Args[1] - v_1_0_0_1_0 := v_1_0_0_1.Args[0] - if v_1_0_0_1_0.Op != OpRsh64x64 || v_1_0_0_1_0.Type != t { - continue - } - _ = v_1_0_0_1_0.Args[1] - if n != v_1_0_0_1_0.Args[0] { - continue - } - v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] - if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 63 { - continue - } - v_1_0_0_1_1 := v_1_0_0_1.Args[1] - if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst64 { continue } - kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { - continue - } - k := auxIntToInt64(v_1_0_1.AuxInt) - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 63 && kbar == 64-k) { + d := auxIntToInt64(o_0.AuxInt) + x := o_1 + if !(uint64(d)%2 == 1 && o.Uses == 1) { continue } v.reset(OpEq64) - v0 := b.NewValue0(v.Pos, OpAnd64, t) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(1< [c]) (Add8 (Const8 [d]) x)) + // match: (Eq8 (Const8 [c]) o:(Add8 (Const8 [d]) x)) + // cond: o.Uses == 1 // result: (Eq8 (Const8 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { @@ -10343,18 +10145,22 @@ func rewriteValuegeneric_OpEq8(v *Value) bool { } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) - if v_1.Op != OpAdd8 { + o := v_1 + if o.Op != OpAdd8 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst8 || v_1_0.Type != t { + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst8 { + continue + } + d := auxIntToInt8(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { continue } - d := auxIntToInt8(v_1_0.AuxInt) - x := v_1_1 v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) @@ -10364,299 +10170,270 @@ func rewriteValuegeneric_OpEq8(v *Value) bool { } break } - // match: (Eq8 (Const8 [c]) (Const8 [d])) - // result: (ConstBool [c == d]) + // match: (Eq8 (Const8 [c]) o:(Sub8 x (Const8 [d]))) + // cond: o.Uses == 1 + // result: (Eq8 (Const8 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } + t := v_0.Type c := auxIntToInt8(v_0.AuxInt) - if v_1.Op != OpConst8 { + o := v_1 + if o.Op != OpSub8 { continue } - d := auxIntToInt8(v_1.AuxInt) - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(c == d) + _ = o.Args[1] + x := o.Args[0] + o_1 := o.Args[1] + if o_1.Op != OpConst8 { + continue + } + d := auxIntToInt8(o_1.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(c + d) + v.AddArg2(v0, x) return true } break } - // match: (Eq8 (Mod8u x (Const8 [c])) (Const8 [0])) - // cond: x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config) - // result: (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [int32(uint8(c))])) (Const32 [0])) + // match: (Eq8 (Const8 [c]) o:(Sub8 (Const8 [d]) x)) + // cond: o.Uses == 1 + // result: (Eq8 (Const8 [d-c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpMod8u { + if v_0.Op != OpConst8 { continue } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpConst8 { + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + o := v_1 + if o.Op != OpSub8 { continue } - c := auxIntToInt8(v_0_1.AuxInt) - if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config)) { + x := o.Args[1] + o_0 := o.Args[0] + if o_0.Op != OpConst8 { continue } - v.reset(OpEq32) - v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) - v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v2.AuxInt = int32ToAuxInt(int32(uint8(c))) - v0.AddArg2(v1, v2) - v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) - v3.AuxInt = int32ToAuxInt(0) - v.AddArg2(v0, v3) + d := auxIntToInt8(o_0.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(d - c) + v.AddArg2(v0, x) return true } break } - // match: (Eq8 (Mod8 x (Const8 [c])) (Const8 [0])) - // cond: x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config) - // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [int32(c)])) (Const32 [0])) + // match: (Eq8 (Const8 [c]) o:(Xor8 (Const8 [d]) x)) + // cond: o.Uses == 1 + // result: (Eq8 (Const8 [d^c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpMod8 { + if v_0.Op != OpConst8 { continue } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpConst8 { + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + o := v_1 + if o.Op != OpXor8 { continue } - c := auxIntToInt8(v_0_1.AuxInt) - if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config)) { + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst8 { + continue + } + d := auxIntToInt8(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { + continue + } + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(d ^ c) + v.AddArg2(v0, x) + return true + } + } + break + } + // match: (Eq8 (Const8 [c]) o:(Com8 x)) + // cond: o.Uses == 1 + // result: (Eq8 (Const8 [^c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst8 { continue } - v.reset(OpEq32) - v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) - v2.AuxInt = int32ToAuxInt(int32(c)) - v0.AddArg2(v1, v2) - v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) - v3.AuxInt = int32ToAuxInt(0) - v.AddArg2(v0, v3) + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + o := v_1 + if o.Op != OpCom8 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(^c) + v.AddArg2(v0, x) return true } break } - // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s && x.Op != OpConst8 && udivisibleOK8(c) - // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int8(udivisible8(c).m)]) x) (Const8 [int8(8-udivisible8(c).k)]) ) (Const8 [int8(udivisible8(c).max)]) ) + // match: (Eq8 (Const8 [c]) o:(Neg8 x)) + // cond: o.Uses == 1 + // result: (Eq8 (Const8 [-c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul8 { + if v_0.Op != OpConst8 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst8 { - continue - } - c := auxIntToInt8(v_1_0.AuxInt) - if v_1_1.Op != OpTrunc32to8 { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh32Ux64 { - continue - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul32 { - continue - } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if mul_1.Op != OpZeroExt8to32 || x != mul_1.Args[0] { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s && x.Op != OpConst8 && udivisibleOK8(c)) { - continue - } - v.reset(OpLeq8U) - v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) - v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) - v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v2.AuxInt = int8ToAuxInt(int8(udivisible8(c).m)) - v1.AddArg2(v2, x) - v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v3.AuxInt = int8ToAuxInt(int8(8 - udivisible8(c).k)) - v0.AddArg2(v1, v3) - v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v4.AuxInt = int8ToAuxInt(int8(udivisible8(c).max)) - v.AddArg2(v0, v4) - return true - } + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + o := v_1 + if o.Op != OpNeg8 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue } + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(-c) + v.AddArg2(v0, x) + return true } break } - // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) ) ) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic8(c).m) && s == 8+smagic8(c).s && x.Op != OpConst8 && sdivisibleOK8(c) - // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int8(sdivisible8(c).m)]) x) (Const8 [int8(sdivisible8(c).a)]) ) (Const8 [int8(8-sdivisible8(c).k)]) ) (Const8 [int8(sdivisible8(c).max)]) ) + // match: (Eq8 (Const8 [c]) o:(Mul8 (Const8 [d]) x)) + // cond: uint8( d)%2 == 1 && o.Uses == 1 + // result: (Eq8 (Const8 [int8( uint8( c) * uint8( modularMultiplicativeInverse(uint64(d))))]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - if v_1.Op != OpMul8 { + if v_0.Op != OpConst8 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst8 { - continue - } - c := auxIntToInt8(v_1_0.AuxInt) - if v_1_1.Op != OpSub8 { - continue - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh32x64 { + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + o := v_1 + if o.Op != OpMul8 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst8 { continue } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul32 { + d := auxIntToInt8(o_0.AuxInt) + x := o_1 + if !(uint8(d)%2 == 1 && o.Uses == 1) { continue } - _ = mul.Args[1] - mul_0 := mul.Args[0] - mul_1 := mul.Args[1] - for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { - if mul_0.Op != OpConst32 { - continue - } - m := auxIntToInt32(mul_0.AuxInt) - if mul_1.Op != OpSignExt8to32 || x != mul_1.Args[0] { - continue - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - continue - } - s := auxIntToInt64(v_1_1_0_1.AuxInt) - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpRsh32x64 { - continue - } - _ = v_1_1_1.Args[1] - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpSignExt8to32 || x != v_1_1_1_0.Args[0] { - continue - } - v_1_1_1_1 := v_1_1_1.Args[1] - if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic8(c).m) && s == 8+smagic8(c).s && x.Op != OpConst8 && sdivisibleOK8(c)) { - continue - } - v.reset(OpLeq8U) - v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) - v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) - v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) - v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v3.AuxInt = int8ToAuxInt(int8(sdivisible8(c).m)) - v2.AddArg2(v3, x) - v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v4.AuxInt = int8ToAuxInt(int8(sdivisible8(c).a)) - v1.AddArg2(v2, v4) - v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v5.AuxInt = int8ToAuxInt(int8(8 - sdivisible8(c).k)) - v0.AddArg2(v1, v5) - v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v6.AuxInt = int8ToAuxInt(int8(sdivisible8(c).max)) - v.AddArg2(v0, v6) - return true - } + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(int8(uint8(c) * uint8(modularMultiplicativeInverse(uint64(d))))) + v.AddArg2(v0, x) + return true + } + } + break + } + // match: (Eq8 (Const8 [c]) (Const8 [d])) + // result: (ConstBool [c == d]) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst8 { + continue } + c := auxIntToInt8(v_0.AuxInt) + if v_1.Op != OpConst8 { + continue + } + d := auxIntToInt8(v_1.AuxInt) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(c == d) + return true } break } - // match: (Eq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) - // cond: k > 0 && k < 7 && kbar == 8 - k - // result: (Eq8 (And8 n (Const8 [1< [0])) + // match: (Eq8 (Mod8u x (Const8 [c])) (Const8 [0])) + // cond: x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [int32(uint8(c))])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpLsh8x64 { + if v_0.Op != OpMod8u { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRsh8x64 { + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst8 { continue } - _ = v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAdd8 { + c := auxIntToInt8(v_0_1.AuxInt) + if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config)) { continue } - t := v_1_0_0.Type - _ = v_1_0_0.Args[1] - v_1_0_0_0 := v_1_0_0.Args[0] - v_1_0_0_1 := v_1_0_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { - if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh8Ux64 || v_1_0_0_1.Type != t { - continue - } - _ = v_1_0_0_1.Args[1] - v_1_0_0_1_0 := v_1_0_0_1.Args[0] - if v_1_0_0_1_0.Op != OpRsh8x64 || v_1_0_0_1_0.Type != t { - continue - } - _ = v_1_0_0_1_0.Args[1] - if n != v_1_0_0_1_0.Args[0] { - continue - } - v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] - if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 7 { - continue - } - v_1_0_0_1_1 := v_1_0_0_1.Args[1] - if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { - continue - } - kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { - continue - } - k := auxIntToInt64(v_1_0_1.AuxInt) - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 7 && kbar == 8-k) { - continue - } - v.reset(OpEq8) - v0 := b.NewValue0(v.Pos, OpAnd8, t) - v1 := b.NewValue0(v.Pos, OpConst8, t) - v1.AuxInt = int8ToAuxInt(1< (SignExt8to32 x) (Const32 [int32(c)])) (Const32 [0])) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpMod8 { + continue } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_0_1.AuxInt) + if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config)) { + continue + } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v2.AuxInt = int32ToAuxInt(int32(c)) + v0.AddArg2(v1, v2) + v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v3.AuxInt = int32ToAuxInt(0) + v.AddArg2(v0, v3) + return true } break } @@ -10714,11 +10491,55 @@ func rewriteValuegeneric_OpEq8(v *Value) bool { } break } + // match: (Eq8 (CvtBoolToUint8 x) (Const8 [1])) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpCvtBoolToUint8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 1 { + continue + } + v.copyOf(x) + return true + } + break + } + // match: (Eq8 (CvtBoolToUint8 x) (Const8 [0])) + // result: (Not x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpCvtBoolToUint8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 { + continue + } + v.reset(OpNot) + v.AddArg(x) + return true + } + break + } return false } func rewriteValuegeneric_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + // match: (EqB x x) + // result: (ConstBool [true]) + for { + x := v_0 + if x != v_1 { + break + } + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(true) + return true + } // match: (EqB (ConstBool [c]) (ConstBool [d])) // result: (ConstBool [c == d]) for { @@ -10764,6 +10585,21 @@ func rewriteValuegeneric_OpEqB(v *Value) bool { } break } + // match: (EqB (Not x) y) + // result: (NeqB x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpNot { + continue + } + x := v_0.Args[0] + y := v_1 + v.reset(OpNeqB) + v.AddArg2(x, y) + return true + } + break + } return false } func rewriteValuegeneric_OpEqInter(v *Value) bool { @@ -11218,16 +11054,13 @@ func rewriteValuegeneric_OpFloor(v *Value) bool { func rewriteValuegeneric_OpIMake(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (IMake _typ (StructMake val)) - // result: (IMake _typ val) + // match: (IMake _typ (StructMake ___)) + // result: imakeOfStructMake(v) for { - _typ := v_0 - if v_1.Op != OpStructMake || len(v_1.Args) != 1 { + if v_1.Op != OpStructMake { break } - val := v_1.Args[0] - v.reset(OpIMake) - v.AddArg2(_typ, val) + v.copyOf(imakeOfStructMake(v)) return true } // match: (IMake _typ (ArrayMake1 val)) @@ -14105,6 +13938,8 @@ func rewriteValuegeneric_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config + typ := &b.Func.Config.Types // match: (Load p1 (Store {t2} p2 x _)) // cond: isSamePtr(p1, p2) && copyCompatibleType(t1, x.Type) && t1.Size() == t2.Size() // result: x @@ -14219,6 +14054,37 @@ func rewriteValuegeneric_OpLoad(v *Value) bool { v.copyOf(x) return true } + // match: (Load op:(OffPtr [o1] p1) move:(Move [n] p2 src mem)) + // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p2) && !isVolatile(src) + // result: @move.Block (Load (OffPtr [o1] src) mem) + for { + t1 := v.Type + op := v_0 + if op.Op != OpOffPtr { + break + } + o1 := auxIntToInt64(op.AuxInt) + p1 := op.Args[0] + move := v_1 + if move.Op != OpMove { + break + } + n := auxIntToInt64(move.AuxInt) + mem := move.Args[2] + p2 := move.Args[0] + src := move.Args[1] + if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p2) && !isVolatile(src)) { + break + } + b = move.Block + v0 := b.NewValue0(v.Pos, OpLoad, t1) + v.copyOf(v0) + v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) + v1.AuxInt = int64ToAuxInt(o1) + v1.AddArg(src) + v0.AddArg2(v1, mem) + return true + } // match: (Load p1 (Store {t2} p2 (Const64 [x]) _)) // cond: isSamePtr(p1,p2) && t2.Size() == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x))) // result: (Const64F [math.Float64frombits(uint64(x))]) @@ -14652,27 +14518,16 @@ func rewriteValuegeneric_OpLoad(v *Value) bool { return true } // match: (Load _ _) - // cond: t.IsStruct() && CanSSA(t) + // cond: t.IsStruct() && t.Size() > 0 && CanSSA(t) && !t.IsSIMD() // result: rewriteStructLoad(v) for { t := v.Type - if !(t.IsStruct() && CanSSA(t)) { + if !(t.IsStruct() && t.Size() > 0 && CanSSA(t) && !t.IsSIMD()) { break } v.copyOf(rewriteStructLoad(v)) return true } - // match: (Load _ _) - // cond: t.IsArray() && t.NumElem() == 0 - // result: (ArrayMake0) - for { - t := v.Type - if !(t.IsArray() && t.NumElem() == 0) { - break - } - v.reset(OpArrayMake0) - return true - } // match: (Load ptr mem) // cond: t.IsArray() && t.NumElem() == 1 && CanSSA(t) // result: (ArrayMake1 (Load ptr mem)) @@ -14689,6 +14544,113 @@ func rewriteValuegeneric_OpLoad(v *Value) bool { v.AddArg(v0) return true } + // match: (Load _ _) + // cond: t.Size() == 0 + // result: (Empty) + for { + t := v.Type + if !(t.Size() == 0) { + break + } + v.reset(OpEmpty) + return true + } + // match: (Load sptr:(Addr {scon} (SB)) mem) + // cond: symIsRO(scon) + // result: (Const8 [int8(read8(scon,0))]) + for { + if v.Type != typ.Int8 { + break + } + sptr := v_0 + if sptr.Op != OpAddr { + break + } + scon := auxToSym(sptr.Aux) + sptr_0 := sptr.Args[0] + if sptr_0.Op != OpSB { + break + } + if !(symIsRO(scon)) { + break + } + v.reset(OpConst8) + v.Type = typ.Int8 + v.AuxInt = int8ToAuxInt(int8(read8(scon, 0))) + return true + } + // match: (Load sptr:(Addr {scon} (SB)) mem) + // cond: symIsRO(scon) + // result: (Const16 [int16(read16(scon,0,config.ctxt.Arch.ByteOrder))]) + for { + if v.Type != typ.Int16 { + break + } + sptr := v_0 + if sptr.Op != OpAddr { + break + } + scon := auxToSym(sptr.Aux) + sptr_0 := sptr.Args[0] + if sptr_0.Op != OpSB { + break + } + if !(symIsRO(scon)) { + break + } + v.reset(OpConst16) + v.Type = typ.Int16 + v.AuxInt = int16ToAuxInt(int16(read16(scon, 0, config.ctxt.Arch.ByteOrder))) + return true + } + // match: (Load sptr:(Addr {scon} (SB)) mem) + // cond: symIsRO(scon) + // result: (Const32 [int32(read32(scon,0,config.ctxt.Arch.ByteOrder))]) + for { + if v.Type != typ.Int32 { + break + } + sptr := v_0 + if sptr.Op != OpAddr { + break + } + scon := auxToSym(sptr.Aux) + sptr_0 := sptr.Args[0] + if sptr_0.Op != OpSB { + break + } + if !(symIsRO(scon)) { + break + } + v.reset(OpConst32) + v.Type = typ.Int32 + v.AuxInt = int32ToAuxInt(int32(read32(scon, 0, config.ctxt.Arch.ByteOrder))) + return true + } + // match: (Load sptr:(Addr {scon} (SB)) mem) + // cond: symIsRO(scon) + // result: (Const64 [int64(read64(scon,0,config.ctxt.Arch.ByteOrder))]) + for { + if v.Type != typ.Int64 { + break + } + sptr := v_0 + if sptr.Op != OpAddr { + break + } + scon := auxToSym(sptr.Aux) + sptr_0 := sptr.Args[0] + if sptr_0.Op != OpSB { + break + } + if !(symIsRO(scon)) { + break + } + v.reset(OpConst64) + v.Type = typ.Int64 + v.AuxInt = int64ToAuxInt(int64(read64(scon, 0, config.ctxt.Arch.ByteOrder))) + return true + } // match: (Load (Addr {s} sb) _) // cond: isFixedLoad(v, s, 0) // result: rewriteFixedLoad(v, s, sb, 0) @@ -14883,17 +14845,16 @@ func rewriteValuegeneric_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh16x16 x (Const16 [c])) - // result: (Lsh16x64 x (Const64 [int64(uint16(c))])) + // match: (Lsh16x16 x (Const16 [c])) + // result: (Lsh16x64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh16x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -14908,23 +14869,43 @@ func rewriteValuegeneric_OpLsh16x16(v *Value) bool { v.AuxInt = int16ToAuxInt(0) return true } + // match: (Lsh16x16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 16 + // result: (Lsh16x16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpLsh16x16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh16x32 x (Const32 [c])) - // result: (Lsh16x64 x (Const64 [int64(uint32(c))])) + // match: (Lsh16x32 x (Const32 [c])) + // result: (Lsh16x64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh16x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -14939,6 +14920,27 @@ func rewriteValuegeneric_OpLsh16x32(v *Value) bool { v.AuxInt = int16ToAuxInt(0) return true } + // match: (Lsh16x32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 16 + // result: (Lsh16x32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpLsh16x32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh16x64(v *Value) bool { @@ -15291,7 +15293,28 @@ func rewriteValuegeneric_OpLsh16x64(v *Value) bool { v.AddArg2(v0, v2) return true } - break + break + } + // match: (Lsh16x64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 16 + // result: (Lsh16x64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpLsh16x64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true } return false } @@ -15299,17 +15322,16 @@ func rewriteValuegeneric_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh16x8 x (Const8 [c])) - // result: (Lsh16x64 x (Const64 [int64(uint8(c))])) + // match: (Lsh16x8 x (Const8 [c])) + // result: (Lsh16x64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh16x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -15324,23 +15346,43 @@ func rewriteValuegeneric_OpLsh16x8(v *Value) bool { v.AuxInt = int16ToAuxInt(0) return true } + // match: (Lsh16x8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 16 + // result: (Lsh16x8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpLsh16x8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh32x16 x (Const16 [c])) - // result: (Lsh32x64 x (Const64 [int64(uint16(c))])) + // match: (Lsh32x16 x (Const16 [c])) + // result: (Lsh32x64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh32x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -15355,23 +15397,43 @@ func rewriteValuegeneric_OpLsh32x16(v *Value) bool { v.AuxInt = int32ToAuxInt(0) return true } + // match: (Lsh32x16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 32 + // result: (Lsh32x16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpLsh32x16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh32x32 x (Const32 [c])) - // result: (Lsh32x64 x (Const64 [int64(uint32(c))])) + // match: (Lsh32x32 x (Const32 [c])) + // result: (Lsh32x64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh32x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -15386,6 +15448,27 @@ func rewriteValuegeneric_OpLsh32x32(v *Value) bool { v.AuxInt = int32ToAuxInt(0) return true } + // match: (Lsh32x32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 32 + // result: (Lsh32x32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpLsh32x32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh32x64(v *Value) bool { @@ -15740,23 +15823,43 @@ func rewriteValuegeneric_OpLsh32x64(v *Value) bool { } break } + // match: (Lsh32x64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 32 + // result: (Lsh32x64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpLsh32x64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh32x8 x (Const8 [c])) - // result: (Lsh32x64 x (Const64 [int64(uint8(c))])) + // match: (Lsh32x8 x (Const8 [c])) + // result: (Lsh32x64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh32x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -15771,23 +15874,43 @@ func rewriteValuegeneric_OpLsh32x8(v *Value) bool { v.AuxInt = int32ToAuxInt(0) return true } + // match: (Lsh32x8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 32 + // result: (Lsh32x8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpLsh32x8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh64x16 x (Const16 [c])) - // result: (Lsh64x64 x (Const64 [int64(uint16(c))])) + // match: (Lsh64x16 x (Const16 [c])) + // result: (Lsh64x64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh64x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -15802,23 +15925,43 @@ func rewriteValuegeneric_OpLsh64x16(v *Value) bool { v.AuxInt = int64ToAuxInt(0) return true } + // match: (Lsh64x16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 64 + // result: (Lsh64x16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpLsh64x16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh64x32 x (Const32 [c])) - // result: (Lsh64x64 x (Const64 [int64(uint32(c))])) + // match: (Lsh64x32 x (Const32 [c])) + // result: (Lsh64x64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh64x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -15833,6 +15976,27 @@ func rewriteValuegeneric_OpLsh64x32(v *Value) bool { v.AuxInt = int64ToAuxInt(0) return true } + // match: (Lsh64x32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 64 + // result: (Lsh64x32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpLsh64x32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh64x64(v *Value) bool { @@ -16187,23 +16351,43 @@ func rewriteValuegeneric_OpLsh64x64(v *Value) bool { } break } + // match: (Lsh64x64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 64 + // result: (Lsh64x64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpLsh64x64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh64x8 x (Const8 [c])) - // result: (Lsh64x64 x (Const64 [int64(uint8(c))])) + // match: (Lsh64x8 x (Const8 [c])) + // result: (Lsh64x64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh64x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -16218,23 +16402,43 @@ func rewriteValuegeneric_OpLsh64x8(v *Value) bool { v.AuxInt = int64ToAuxInt(0) return true } + // match: (Lsh64x8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 64 + // result: (Lsh64x8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpLsh64x8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh8x16 x (Const16 [c])) - // result: (Lsh8x64 x (Const64 [int64(uint16(c))])) + // match: (Lsh8x16 x (Const16 [c])) + // result: (Lsh8x64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh8x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -16249,23 +16453,43 @@ func rewriteValuegeneric_OpLsh8x16(v *Value) bool { v.AuxInt = int8ToAuxInt(0) return true } + // match: (Lsh8x16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 8 + // result: (Lsh8x16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpLsh8x16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh8x32 x (Const32 [c])) - // result: (Lsh8x64 x (Const64 [int64(uint32(c))])) + // match: (Lsh8x32 x (Const32 [c])) + // result: (Lsh8x64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh8x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -16280,6 +16504,27 @@ func rewriteValuegeneric_OpLsh8x32(v *Value) bool { v.AuxInt = int8ToAuxInt(0) return true } + // match: (Lsh8x32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 8 + // result: (Lsh8x32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpLsh8x32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpLsh8x64(v *Value) bool { @@ -16622,47 +16867,374 @@ func rewriteValuegeneric_OpLsh8x64(v *Value) bool { if !(c < e) { continue } - v.reset(OpAnd8) - v0 := b.NewValue0(v.Pos, OpLsh8x64, t) - v1 := b.NewValue0(v.Pos, OpConst64, t2) - v1.AuxInt = int64ToAuxInt(e - c) - v0.AddArg2(x, v1) - v2 := b.NewValue0(v.Pos, OpConst8, t) - v2.AuxInt = int8ToAuxInt(d << e) - v.AddArg2(v0, v2) + v.reset(OpAnd8) + v0 := b.NewValue0(v.Pos, OpLsh8x64, t) + v1 := b.NewValue0(v.Pos, OpConst64, t2) + v1.AuxInt = int64ToAuxInt(e - c) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst8, t) + v2.AuxInt = int8ToAuxInt(d << e) + v.AddArg2(v0, v2) + return true + } + break + } + // match: (Lsh8x64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 8 + // result: (Lsh8x64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpLsh8x64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } + return false +} +func rewriteValuegeneric_OpLsh8x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh8x8 x (Const8 [c])) + // result: (Lsh8x64 x (Const64 [int64(uint8(c))])) + for { + x := v_0 + if v_1.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1.AuxInt) + v.reset(OpLsh8x64) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) + v0.AuxInt = int64ToAuxInt(int64(uint8(c))) + v.AddArg2(x, v0) + return true + } + // match: (Lsh8x8 (Const8 [0]) _) + // result: (Const8 [0]) + for { + if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { + break + } + v.reset(OpConst8) + v.AuxInt = int8ToAuxInt(0) + return true + } + // match: (Lsh8x8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 8 + // result: (Lsh8x8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpLsh8x8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } + return false +} +func rewriteValuegeneric_OpMemEq(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + config := b.Func.Config + typ := &b.Func.Config.Types + // match: (MemEq sptr tptr (Const64 [1]) mem) + // result: (Eq8 (Load sptr mem) (Load tptr mem)) + for { + sptr := v_0 + tptr := v_1 + if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 1 { + break + } + mem := v_3 + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpLoad, typ.Int8) + v0.AddArg2(sptr, mem) + v1 := b.NewValue0(v.Pos, OpLoad, typ.Int8) + v1.AddArg2(tptr, mem) + v.AddArg2(v0, v1) + return true + } + // match: (MemEq sptr tptr (Const64 [2]) mem) + // cond: canLoadUnaligned(config) + // result: (Eq16 (Load sptr mem) (Load tptr mem)) + for { + sptr := v_0 + tptr := v_1 + if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 2 { + break + } + mem := v_3 + if !(canLoadUnaligned(config)) { + break + } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpLoad, typ.Int16) + v0.AddArg2(sptr, mem) + v1 := b.NewValue0(v.Pos, OpLoad, typ.Int16) + v1.AddArg2(tptr, mem) + v.AddArg2(v0, v1) + return true + } + // match: (MemEq sptr tptr (Const64 [4]) mem) + // cond: canLoadUnaligned(config) + // result: (Eq32 (Load sptr mem) (Load tptr mem)) + for { + sptr := v_0 + tptr := v_1 + if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 4 { + break + } + mem := v_3 + if !(canLoadUnaligned(config)) { + break + } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpLoad, typ.Int32) + v0.AddArg2(sptr, mem) + v1 := b.NewValue0(v.Pos, OpLoad, typ.Int32) + v1.AddArg2(tptr, mem) + v.AddArg2(v0, v1) + return true + } + // match: (MemEq sptr tptr (Const64 [8]) mem) + // cond: canLoadUnaligned(config) && config.PtrSize == 8 + // result: (Eq64 (Load sptr mem) (Load tptr mem)) + for { + sptr := v_0 + tptr := v_1 + if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 8 { + break + } + mem := v_3 + if !(canLoadUnaligned(config) && config.PtrSize == 8) { + break + } + v.reset(OpEq64) + v0 := b.NewValue0(v.Pos, OpLoad, typ.Int64) + v0.AddArg2(sptr, mem) + v1 := b.NewValue0(v.Pos, OpLoad, typ.Int64) + v1.AddArg2(tptr, mem) + v.AddArg2(v0, v1) + return true + } + // match: (MemEq _ _ (Const64 [0]) _) + // result: (ConstBool [true]) + for { + if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 0 { + break + } + v.reset(OpConstBool) + v.Type = typ.Bool + v.AuxInt = boolToAuxInt(true) + return true + } + // match: (MemEq p q _ _) + // cond: isSamePtr(p, q) + // result: (ConstBool [true]) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + p := v_0 + q := v_1 + if !(isSamePtr(p, q)) { + continue + } + v.reset(OpConstBool) + v.Type = typ.Bool + v.AuxInt = boolToAuxInt(true) return true } break } - return false -} -func rewriteValuegeneric_OpLsh8x8(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (Lsh8x8 x (Const8 [c])) - // result: (Lsh8x64 x (Const64 [int64(uint8(c))])) + // match: (MemEq p q (Const64 [c]) mem) + // cond: (c == 3 || c == 5 || c == 9 || c == 17) && canLoadUnaligned(config) && config.RegSize == 8 + // result: (AndB (MemEq p q (Const64 [c-1]) mem) (Eq8 (Load (OffPtr p [c-1]) mem) (Load (OffPtr q [c-1]) mem))) for { - t := v.Type - x := v_0 - if v_1.Op != OpConst8 { + p := v_0 + q := v_1 + if v_2.Op != OpConst64 { + break + } + c := auxIntToInt64(v_2.AuxInt) + mem := v_3 + if !((c == 3 || c == 5 || c == 9 || c == 17) && canLoadUnaligned(config) && config.RegSize == 8) { + break + } + v.reset(OpAndB) + v0 := b.NewValue0(v.Pos, OpMemEq, typ.Bool) + v1 := b.NewValue0(v.Pos, OpConst64, typ.Int64) + v1.AuxInt = int64ToAuxInt(c - 1) + v0.AddArg4(p, q, v1, mem) + v2 := b.NewValue0(v.Pos, OpEq8, typ.Bool) + v3 := b.NewValue0(v.Pos, OpLoad, typ.Int8) + v4 := b.NewValue0(v.Pos, OpOffPtr, p.Type) + v4.AuxInt = int64ToAuxInt(c - 1) + v4.AddArg(p) + v3.AddArg2(v4, mem) + v5 := b.NewValue0(v.Pos, OpLoad, typ.Int8) + v6 := b.NewValue0(v.Pos, OpOffPtr, q.Type) + v6.AuxInt = int64ToAuxInt(c - 1) + v6.AddArg(q) + v5.AddArg2(v6, mem) + v2.AddArg2(v3, v5) + v.AddArg2(v0, v2) + return true + } + // match: (MemEq p q (Const64 [c]) mem) + // cond: (c == 6 || c == 10 || c == 18) && canLoadUnaligned(config) && config.RegSize == 8 + // result: (AndB (MemEq p q (Const64 [c-2]) mem) (Eq16 (Load (OffPtr p [c-2]) mem) (Load (OffPtr q [c-2]) mem))) + for { + p := v_0 + q := v_1 + if v_2.Op != OpConst64 { break } - c := auxIntToInt8(v_1.AuxInt) - v.reset(OpLsh8x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) - v0.AuxInt = int64ToAuxInt(int64(uint8(c))) - v.AddArg2(x, v0) + c := auxIntToInt64(v_2.AuxInt) + mem := v_3 + if !((c == 6 || c == 10 || c == 18) && canLoadUnaligned(config) && config.RegSize == 8) { + break + } + v.reset(OpAndB) + v0 := b.NewValue0(v.Pos, OpMemEq, typ.Bool) + v1 := b.NewValue0(v.Pos, OpConst64, typ.Int64) + v1.AuxInt = int64ToAuxInt(c - 2) + v0.AddArg4(p, q, v1, mem) + v2 := b.NewValue0(v.Pos, OpEq16, typ.Bool) + v3 := b.NewValue0(v.Pos, OpLoad, typ.Int16) + v4 := b.NewValue0(v.Pos, OpOffPtr, p.Type) + v4.AuxInt = int64ToAuxInt(c - 2) + v4.AddArg(p) + v3.AddArg2(v4, mem) + v5 := b.NewValue0(v.Pos, OpLoad, typ.Int16) + v6 := b.NewValue0(v.Pos, OpOffPtr, q.Type) + v6.AuxInt = int64ToAuxInt(c - 2) + v6.AddArg(q) + v5.AddArg2(v6, mem) + v2.AddArg2(v3, v5) + v.AddArg2(v0, v2) return true } - // match: (Lsh8x8 (Const8 [0]) _) - // result: (Const8 [0]) + // match: (MemEq p q (Const64 [c]) mem) + // cond: (c == 7 || c == 11 || c == 19 || c == 20) && canLoadUnaligned(config) && config.RegSize == 8 + // result: (AndB (MemEq p q (Const64 [min(c-3,16)]) mem) (Eq32 (Load (OffPtr p [c-4]) mem) (Load (OffPtr q [c-4]) mem))) for { - if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { + p := v_0 + q := v_1 + if v_2.Op != OpConst64 { break } - v.reset(OpConst8) - v.AuxInt = int8ToAuxInt(0) + c := auxIntToInt64(v_2.AuxInt) + mem := v_3 + if !((c == 7 || c == 11 || c == 19 || c == 20) && canLoadUnaligned(config) && config.RegSize == 8) { + break + } + v.reset(OpAndB) + v0 := b.NewValue0(v.Pos, OpMemEq, typ.Bool) + v1 := b.NewValue0(v.Pos, OpConst64, typ.Int64) + v1.AuxInt = int64ToAuxInt(min(c-3, 16)) + v0.AddArg4(p, q, v1, mem) + v2 := b.NewValue0(v.Pos, OpEq32, typ.Bool) + v3 := b.NewValue0(v.Pos, OpLoad, typ.Int32) + v4 := b.NewValue0(v.Pos, OpOffPtr, p.Type) + v4.AuxInt = int64ToAuxInt(c - 4) + v4.AddArg(p) + v3.AddArg2(v4, mem) + v5 := b.NewValue0(v.Pos, OpLoad, typ.Int32) + v6 := b.NewValue0(v.Pos, OpOffPtr, q.Type) + v6.AuxInt = int64ToAuxInt(c - 4) + v6.AddArg(q) + v5.AddArg2(v6, mem) + v2.AddArg2(v3, v5) + v.AddArg2(v0, v2) + return true + } + // match: (MemEq p q (Const64 [c]) mem) + // cond: ((c >= 12 && c <= 16) || (c >= 21 && c <= 24)) && canLoadUnaligned(config) && config.RegSize == 8 + // result: (AndB (MemEq p q (Const64 [8 + int64(bool2int(c>16))*8]) mem) (Eq64 (Load (OffPtr p [c-8]) mem) (Load (OffPtr q [c-8]) mem))) + for { + p := v_0 + q := v_1 + if v_2.Op != OpConst64 { + break + } + c := auxIntToInt64(v_2.AuxInt) + mem := v_3 + if !(((c >= 12 && c <= 16) || (c >= 21 && c <= 24)) && canLoadUnaligned(config) && config.RegSize == 8) { + break + } + v.reset(OpAndB) + v0 := b.NewValue0(v.Pos, OpMemEq, typ.Bool) + v1 := b.NewValue0(v.Pos, OpConst64, typ.Int64) + v1.AuxInt = int64ToAuxInt(8 + int64(bool2int(c > 16))*8) + v0.AddArg4(p, q, v1, mem) + v2 := b.NewValue0(v.Pos, OpEq64, typ.Bool) + v3 := b.NewValue0(v.Pos, OpLoad, typ.Int64) + v4 := b.NewValue0(v.Pos, OpOffPtr, p.Type) + v4.AuxInt = int64ToAuxInt(c - 8) + v4.AddArg(p) + v3.AddArg2(v4, mem) + v5 := b.NewValue0(v.Pos, OpLoad, typ.Int64) + v6 := b.NewValue0(v.Pos, OpOffPtr, q.Type) + v6.AuxInt = int64ToAuxInt(c - 8) + v6.AddArg(q) + v5.AddArg2(v6, mem) + v2.AddArg2(v3, v5) + v.AddArg2(v0, v2) + return true + } + // match: (MemEq p q (Const64 [c]) mem) + // cond: c >= 25 && c <= 32 && canLoadUnaligned(config) && config.RegSize == 8 + // result: (AndB (MemEq p q (Const64 [16]) mem) (MemEq (OffPtr p [16]) (OffPtr q [16]) (Const64 [c-16]) mem)) + for { + p := v_0 + q := v_1 + if v_2.Op != OpConst64 { + break + } + c := auxIntToInt64(v_2.AuxInt) + mem := v_3 + if !(c >= 25 && c <= 32 && canLoadUnaligned(config) && config.RegSize == 8) { + break + } + v.reset(OpAndB) + v0 := b.NewValue0(v.Pos, OpMemEq, typ.Bool) + v1 := b.NewValue0(v.Pos, OpConst64, typ.Int64) + v1.AuxInt = int64ToAuxInt(16) + v0.AddArg4(p, q, v1, mem) + v2 := b.NewValue0(v.Pos, OpMemEq, typ.Bool) + v3 := b.NewValue0(v.Pos, OpOffPtr, p.Type) + v3.AuxInt = int64ToAuxInt(16) + v3.AddArg(p) + v4 := b.NewValue0(v.Pos, OpOffPtr, q.Type) + v4.AuxInt = int64ToAuxInt(16) + v4.AddArg(q) + v5 := b.NewValue0(v.Pos, OpConst64, typ.Int64) + v5.AuxInt = int64ToAuxInt(c - 16) + v2.AddArg4(v3, v4, v5, mem) + v.AddArg2(v0, v2) return true } return false @@ -16778,7 +17350,7 @@ func rewriteValuegeneric_OpMod16u(v *Value) bool { return true } // match: (Mod16u n (Const16 [c])) - // cond: isUnsignedPowerOfTwo(uint16(c)) + // cond: isPowerOfTwo(uint16(c)) // result: (And16 n (Const16 [c-1])) for { t := v.Type @@ -16787,7 +17359,7 @@ func rewriteValuegeneric_OpMod16u(v *Value) bool { break } c := auxIntToInt16(v_1.AuxInt) - if !(isUnsignedPowerOfTwo(uint16(c))) { + if !(isPowerOfTwo(uint16(c))) { break } v.reset(OpAnd16) @@ -16797,7 +17369,7 @@ func rewriteValuegeneric_OpMod16u(v *Value) bool { return true } // match: (Mod16u x (Const16 [c])) - // cond: x.Op != OpConst16 && c > 0 && umagicOK16(c) + // cond: x.Op != OpConst16 && c != 0 // result: (Sub16 x (Mul16 (Div16u x (Const16 [c])) (Const16 [c]))) for { t := v.Type @@ -16806,7 +17378,7 @@ func rewriteValuegeneric_OpMod16u(v *Value) bool { break } c := auxIntToInt16(v_1.AuxInt) - if !(x.Op != OpConst16 && c > 0 && umagicOK16(c)) { + if !(x.Op != OpConst16 && c != 0) { break } v.reset(OpSub16) @@ -16932,7 +17504,7 @@ func rewriteValuegeneric_OpMod32u(v *Value) bool { return true } // match: (Mod32u n (Const32 [c])) - // cond: isUnsignedPowerOfTwo(uint32(c)) + // cond: isPowerOfTwo(uint32(c)) // result: (And32 n (Const32 [c-1])) for { t := v.Type @@ -16941,7 +17513,7 @@ func rewriteValuegeneric_OpMod32u(v *Value) bool { break } c := auxIntToInt32(v_1.AuxInt) - if !(isUnsignedPowerOfTwo(uint32(c))) { + if !(isPowerOfTwo(uint32(c))) { break } v.reset(OpAnd32) @@ -16951,7 +17523,7 @@ func rewriteValuegeneric_OpMod32u(v *Value) bool { return true } // match: (Mod32u x (Const32 [c])) - // cond: x.Op != OpConst32 && c > 0 && umagicOK32(c) + // cond: x.Op != OpConst32 && c != 0 // result: (Sub32 x (Mul32 (Div32u x (Const32 [c])) (Const32 [c]))) for { t := v.Type @@ -16960,7 +17532,7 @@ func rewriteValuegeneric_OpMod32u(v *Value) bool { break } c := auxIntToInt32(v_1.AuxInt) - if !(x.Op != OpConst32 && c > 0 && umagicOK32(c)) { + if !(x.Op != OpConst32 && c != 0) { break } v.reset(OpSub32) @@ -17097,7 +17669,7 @@ func rewriteValuegeneric_OpMod64u(v *Value) bool { return true } // match: (Mod64u n (Const64 [c])) - // cond: isUnsignedPowerOfTwo(uint64(c)) + // cond: isPowerOfTwo(uint64(c)) // result: (And64 n (Const64 [c-1])) for { t := v.Type @@ -17106,7 +17678,7 @@ func rewriteValuegeneric_OpMod64u(v *Value) bool { break } c := auxIntToInt64(v_1.AuxInt) - if !(isUnsignedPowerOfTwo(uint64(c))) { + if !(isPowerOfTwo(uint64(c))) { break } v.reset(OpAnd64) @@ -17116,7 +17688,7 @@ func rewriteValuegeneric_OpMod64u(v *Value) bool { return true } // match: (Mod64u x (Const64 [c])) - // cond: x.Op != OpConst64 && c > 0 && umagicOK64(c) + // cond: x.Op != OpConst64 && c != 0 // result: (Sub64 x (Mul64 (Div64u x (Const64 [c])) (Const64 [c]))) for { t := v.Type @@ -17125,7 +17697,7 @@ func rewriteValuegeneric_OpMod64u(v *Value) bool { break } c := auxIntToInt64(v_1.AuxInt) - if !(x.Op != OpConst64 && c > 0 && umagicOK64(c)) { + if !(x.Op != OpConst64 && c != 0) { break } v.reset(OpSub64) @@ -17251,7 +17823,7 @@ func rewriteValuegeneric_OpMod8u(v *Value) bool { return true } // match: (Mod8u n (Const8 [c])) - // cond: isUnsignedPowerOfTwo(uint8(c)) + // cond: isPowerOfTwo(uint8(c)) // result: (And8 n (Const8 [c-1])) for { t := v.Type @@ -17260,7 +17832,7 @@ func rewriteValuegeneric_OpMod8u(v *Value) bool { break } c := auxIntToInt8(v_1.AuxInt) - if !(isUnsignedPowerOfTwo(uint8(c))) { + if !(isPowerOfTwo(uint8(c))) { break } v.reset(OpAnd8) @@ -17270,7 +17842,7 @@ func rewriteValuegeneric_OpMod8u(v *Value) bool { return true } // match: (Mod8u x (Const8 [c])) - // cond: x.Op != OpConst8 && c > 0 && umagicOK8( c) + // cond: x.Op != OpConst8 && c != 0 // result: (Sub8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) for { t := v.Type @@ -17279,7 +17851,7 @@ func rewriteValuegeneric_OpMod8u(v *Value) bool { break } c := auxIntToInt8(v_1.AuxInt) - if !(x.Op != OpConst8 && c > 0 && umagicOK8(c)) { + if !(x.Op != OpConst8 && c != 0) { break } v.reset(OpSub8) @@ -18683,54 +19255,47 @@ func rewriteValuegeneric_OpMul16(v *Value) bool { } break } - // match: (Mul16 n (Const16 [c])) - // cond: isPowerOfTwo(c) - // result: (Lsh16x64 n (Const64 [log16(c)])) + // match: (Mul16 (Const16 [c]) (Neg16 x)) + // result: (Mul16 x (Const16 [-c])) for { - t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpConst16 { + if v_0.Op != OpConst16 { continue } - c := auxIntToInt16(v_1.AuxInt) - if !(isPowerOfTwo(c)) { + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + if v_1.Op != OpNeg16 { continue } - v.reset(OpLsh16x64) - v.Type = t - v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v0.AuxInt = int64ToAuxInt(log16(c)) - v.AddArg2(n, v0) + x := v_1.Args[0] + v.reset(OpMul16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(-c) + v.AddArg2(x, v0) return true } break } - // match: (Mul16 n (Const16 [c])) - // cond: t.IsSigned() && isPowerOfTwo(-c) - // result: (Neg16 (Lsh16x64 n (Const64 [log16(-c)]))) + // match: (Mul16 (Neg16 x) (Neg16 y)) + // result: (Mul16 x y) for { - t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpConst16 { + if v_0.Op != OpNeg16 { continue } - c := auxIntToInt16(v_1.AuxInt) - if !(t.IsSigned() && isPowerOfTwo(-c)) { + x := v_0.Args[0] + if v_1.Op != OpNeg16 { continue } - v.reset(OpNeg16) - v0 := b.NewValue0(v.Pos, OpLsh16x64, t) - v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v1.AuxInt = int64ToAuxInt(log16(-c)) - v0.AddArg2(n, v1) - v.AddArg(v0) + y := v_1.Args[0] + v.reset(OpMul16) + v.AddArg2(x, y) return true } break } // match: (Mul16 (Const16 [c]) (Add16 (Const16 [d]) x)) + // cond: !isPowerOfTwo(c) // result: (Add16 (Const16 [c*d]) (Mul16 (Const16 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { @@ -18751,6 +19316,9 @@ func rewriteValuegeneric_OpMul16(v *Value) bool { } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 + if !(!isPowerOfTwo(c)) { + continue + } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c * d) @@ -18777,6 +19345,53 @@ func rewriteValuegeneric_OpMul16(v *Value) bool { } break } + // match: (Mul16 x (Const16 [c])) + // cond: isPowerOfTwo(uint16(c)) && v.Block.Func.pass.name != "opt" + // result: (Lsh16x64 x (Const64 [log16u(uint16(c))])) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1.AuxInt) + if !(isPowerOfTwo(uint16(c)) && v.Block.Func.pass.name != "opt") { + continue + } + v.reset(OpLsh16x64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v0.AuxInt = int64ToAuxInt(log16u(uint16(c))) + v.AddArg2(x, v0) + return true + } + break + } + // match: (Mul16 x (Const16 [c])) + // cond: isPowerOfTwo(uint16(-c)) && v.Block.Func.pass.name != "opt" + // result: (Neg16 (Lsh16x64 x (Const64 [log16u(uint16(-c))]))) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1.AuxInt) + if !(isPowerOfTwo(uint16(-c)) && v.Block.Func.pass.name != "opt") { + continue + } + v.reset(OpNeg16) + v0 := b.NewValue0(v.Pos, OpLsh16x64, t) + v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v1.AuxInt = int64ToAuxInt(log16u(uint16(-c))) + v0.AddArg2(x, v1) + v.AddArg(v0) + return true + } + break + } // match: (Mul16 (Mul16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Mul16 i (Mul16 x z)) @@ -18890,54 +19505,47 @@ func rewriteValuegeneric_OpMul32(v *Value) bool { } break } - // match: (Mul32 n (Const32 [c])) - // cond: isPowerOfTwo(c) - // result: (Lsh32x64 n (Const64 [log32(c)])) + // match: (Mul32 (Const32 [c]) (Neg32 x)) + // result: (Mul32 x (Const32 [-c])) for { - t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpConst32 { + if v_0.Op != OpConst32 { continue } - c := auxIntToInt32(v_1.AuxInt) - if !(isPowerOfTwo(c)) { + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + if v_1.Op != OpNeg32 { continue } - v.reset(OpLsh32x64) - v.Type = t - v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v0.AuxInt = int64ToAuxInt(log32(c)) - v.AddArg2(n, v0) + x := v_1.Args[0] + v.reset(OpMul32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(-c) + v.AddArg2(x, v0) return true } break } - // match: (Mul32 n (Const32 [c])) - // cond: t.IsSigned() && isPowerOfTwo(-c) - // result: (Neg32 (Lsh32x64 n (Const64 [log32(-c)]))) + // match: (Mul32 (Neg32 x) (Neg32 y)) + // result: (Mul32 x y) for { - t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpConst32 { + if v_0.Op != OpNeg32 { continue } - c := auxIntToInt32(v_1.AuxInt) - if !(t.IsSigned() && isPowerOfTwo(-c)) { + x := v_0.Args[0] + if v_1.Op != OpNeg32 { continue } - v.reset(OpNeg32) - v0 := b.NewValue0(v.Pos, OpLsh32x64, t) - v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v1.AuxInt = int64ToAuxInt(log32(-c)) - v0.AddArg2(n, v1) - v.AddArg(v0) + y := v_1.Args[0] + v.reset(OpMul32) + v.AddArg2(x, y) return true } break } // match: (Mul32 (Const32 [c]) (Add32 (Const32 [d]) x)) + // cond: !isPowerOfTwo(c) // result: (Add32 (Const32 [c*d]) (Mul32 (Const32 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { @@ -18958,6 +19566,9 @@ func rewriteValuegeneric_OpMul32(v *Value) bool { } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 + if !(!isPowerOfTwo(c)) { + continue + } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c * d) @@ -18984,6 +19595,53 @@ func rewriteValuegeneric_OpMul32(v *Value) bool { } break } + // match: (Mul32 x (Const32 [c])) + // cond: isPowerOfTwo(uint32(c)) && v.Block.Func.pass.name != "opt" + // result: (Lsh32x64 x (Const64 [log32u(uint32(c))])) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1.AuxInt) + if !(isPowerOfTwo(uint32(c)) && v.Block.Func.pass.name != "opt") { + continue + } + v.reset(OpLsh32x64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v0.AuxInt = int64ToAuxInt(log32u(uint32(c))) + v.AddArg2(x, v0) + return true + } + break + } + // match: (Mul32 x (Const32 [c])) + // cond: isPowerOfTwo(uint32(-c)) && v.Block.Func.pass.name != "opt" + // result: (Neg32 (Lsh32x64 x (Const64 [log32u(uint32(-c))]))) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1.AuxInt) + if !(isPowerOfTwo(uint32(-c)) && v.Block.Func.pass.name != "opt") { + continue + } + v.reset(OpNeg32) + v0 := b.NewValue0(v.Pos, OpLsh32x64, t) + v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v1.AuxInt = int64ToAuxInt(log32u(uint32(-c))) + v0.AddArg2(x, v1) + v.AddArg(v0) + return true + } + break + } // match: (Mul32 (Mul32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Mul32 i (Mul32 x z)) @@ -19258,54 +19916,47 @@ func rewriteValuegeneric_OpMul64(v *Value) bool { } break } - // match: (Mul64 n (Const64 [c])) - // cond: isPowerOfTwo(c) - // result: (Lsh64x64 n (Const64 [log64(c)])) + // match: (Mul64 (Const64 [c]) (Neg64 x)) + // result: (Mul64 x (Const64 [-c])) for { - t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpConst64 { + if v_0.Op != OpConst64 { continue } - c := auxIntToInt64(v_1.AuxInt) - if !(isPowerOfTwo(c)) { + t := v_0.Type + c := auxIntToInt64(v_0.AuxInt) + if v_1.Op != OpNeg64 { continue } - v.reset(OpLsh64x64) - v.Type = t - v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v0.AuxInt = int64ToAuxInt(log64(c)) - v.AddArg2(n, v0) + x := v_1.Args[0] + v.reset(OpMul64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(-c) + v.AddArg2(x, v0) return true } break } - // match: (Mul64 n (Const64 [c])) - // cond: t.IsSigned() && isPowerOfTwo(-c) - // result: (Neg64 (Lsh64x64 n (Const64 [log64(-c)]))) + // match: (Mul64 (Neg64 x) (Neg64 y)) + // result: (Mul64 x y) for { - t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpConst64 { + if v_0.Op != OpNeg64 { continue } - c := auxIntToInt64(v_1.AuxInt) - if !(t.IsSigned() && isPowerOfTwo(-c)) { + x := v_0.Args[0] + if v_1.Op != OpNeg64 { continue } - v.reset(OpNeg64) - v0 := b.NewValue0(v.Pos, OpLsh64x64, t) - v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v1.AuxInt = int64ToAuxInt(log64(-c)) - v0.AddArg2(n, v1) - v.AddArg(v0) + y := v_1.Args[0] + v.reset(OpMul64) + v.AddArg2(x, y) return true } break } // match: (Mul64 (Const64 [c]) (Add64 (Const64 [d]) x)) + // cond: !isPowerOfTwo(c) // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { @@ -19326,6 +19977,9 @@ func rewriteValuegeneric_OpMul64(v *Value) bool { } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 + if !(!isPowerOfTwo(c)) { + continue + } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c * d) @@ -19339,15 +19993,62 @@ func rewriteValuegeneric_OpMul64(v *Value) bool { } break } - // match: (Mul64 (Const64 [0]) _) - // result: (Const64 [0]) + // match: (Mul64 (Const64 [0]) _) + // result: (Const64 [0]) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { + continue + } + v.reset(OpConst64) + v.AuxInt = int64ToAuxInt(0) + return true + } + break + } + // match: (Mul64 x (Const64 [c])) + // cond: isPowerOfTwo(uint64(c)) && v.Block.Func.pass.name != "opt" + // result: (Lsh64x64 x (Const64 [log64u(uint64(c))])) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1.AuxInt) + if !(isPowerOfTwo(uint64(c)) && v.Block.Func.pass.name != "opt") { + continue + } + v.reset(OpLsh64x64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v0.AuxInt = int64ToAuxInt(log64u(uint64(c))) + v.AddArg2(x, v0) + return true + } + break + } + // match: (Mul64 x (Const64 [c])) + // cond: isPowerOfTwo(uint64(-c)) && v.Block.Func.pass.name != "opt" + // result: (Neg64 (Lsh64x64 x (Const64 [log64u(uint64(-c))]))) for { + t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { + x := v_0 + if v_1.Op != OpConst64 { continue } - v.reset(OpConst64) - v.AuxInt = int64ToAuxInt(0) + c := auxIntToInt64(v_1.AuxInt) + if !(isPowerOfTwo(uint64(-c)) && v.Block.Func.pass.name != "opt") { + continue + } + v.reset(OpNeg64) + v0 := b.NewValue0(v.Pos, OpLsh64x64, t) + v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v1.AuxInt = int64ToAuxInt(log64u(uint64(-c))) + v0.AddArg2(x, v1) + v.AddArg(v0) return true } break @@ -19626,54 +20327,47 @@ func rewriteValuegeneric_OpMul8(v *Value) bool { } break } - // match: (Mul8 n (Const8 [c])) - // cond: isPowerOfTwo(c) - // result: (Lsh8x64 n (Const64 [log8(c)])) + // match: (Mul8 (Const8 [c]) (Neg8 x)) + // result: (Mul8 x (Const8 [-c])) for { - t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpConst8 { + if v_0.Op != OpConst8 { continue } - c := auxIntToInt8(v_1.AuxInt) - if !(isPowerOfTwo(c)) { + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + if v_1.Op != OpNeg8 { continue } - v.reset(OpLsh8x64) - v.Type = t - v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v0.AuxInt = int64ToAuxInt(log8(c)) - v.AddArg2(n, v0) + x := v_1.Args[0] + v.reset(OpMul8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(-c) + v.AddArg2(x, v0) return true } break } - // match: (Mul8 n (Const8 [c])) - // cond: t.IsSigned() && isPowerOfTwo(-c) - // result: (Neg8 (Lsh8x64 n (Const64 [log8(-c)]))) + // match: (Mul8 (Neg8 x) (Neg8 y)) + // result: (Mul8 x y) for { - t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpConst8 { + if v_0.Op != OpNeg8 { continue } - c := auxIntToInt8(v_1.AuxInt) - if !(t.IsSigned() && isPowerOfTwo(-c)) { + x := v_0.Args[0] + if v_1.Op != OpNeg8 { continue } - v.reset(OpNeg8) - v0 := b.NewValue0(v.Pos, OpLsh8x64, t) - v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) - v1.AuxInt = int64ToAuxInt(log8(-c)) - v0.AddArg2(n, v1) - v.AddArg(v0) + y := v_1.Args[0] + v.reset(OpMul8) + v.AddArg2(x, y) return true } break } // match: (Mul8 (Const8 [c]) (Add8 (Const8 [d]) x)) + // cond: !isPowerOfTwo(c) // result: (Add8 (Const8 [c*d]) (Mul8 (Const8 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { @@ -19694,6 +20388,9 @@ func rewriteValuegeneric_OpMul8(v *Value) bool { } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 + if !(!isPowerOfTwo(c)) { + continue + } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c * d) @@ -19720,6 +20417,53 @@ func rewriteValuegeneric_OpMul8(v *Value) bool { } break } + // match: (Mul8 x (Const8 [c])) + // cond: isPowerOfTwo(uint8(c)) && v.Block.Func.pass.name != "opt" + // result: (Lsh8x64 x (Const64 [log8u(uint8(c))])) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1.AuxInt) + if !(isPowerOfTwo(uint8(c)) && v.Block.Func.pass.name != "opt") { + continue + } + v.reset(OpLsh8x64) + v.Type = t + v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v0.AuxInt = int64ToAuxInt(log8u(uint8(c))) + v.AddArg2(x, v0) + return true + } + break + } + // match: (Mul8 x (Const8 [c])) + // cond: isPowerOfTwo(uint8(-c)) && v.Block.Func.pass.name != "opt" + // result: (Neg8 (Lsh8x64 x (Const64 [log8u(uint8(-c))]))) + for { + t := v.Type + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1.AuxInt) + if !(isPowerOfTwo(uint8(-c)) && v.Block.Func.pass.name != "opt") { + continue + } + v.reset(OpNeg8) + v0 := b.NewValue0(v.Pos, OpLsh8x64, t) + v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v1.AuxInt = int64ToAuxInt(log8u(uint8(-c))) + v0.AddArg2(x, v1) + v.AddArg(v0) + return true + } + break + } // match: (Mul8 (Mul8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Mul8 i (Mul8 x z)) @@ -19797,6 +20541,51 @@ func rewriteValuegeneric_OpNeg16(v *Value) bool { v.AuxInt = int16ToAuxInt(-c) return true } + // match: (Neg16 (Mul16 x (Const16 [c]))) + // result: (Mul16 x (Const16 [-c])) + for { + if v_0.Op != OpMul16 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + if v_0_1.Op != OpConst16 { + continue + } + t := v_0_1.Type + c := auxIntToInt16(v_0_1.AuxInt) + v.reset(OpMul16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(-c) + v.AddArg2(x, v0) + return true + } + break + } + // match: (Neg16 (Mul16 x (Neg16 y))) + // result: (Mul16 x y) + for { + if v_0.Op != OpMul16 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + if v_0_1.Op != OpNeg16 { + continue + } + y := v_0_1.Args[0] + v.reset(OpMul16) + v.AddArg2(x, y) + return true + } + break + } // match: (Neg16 (Sub16 x y)) // result: (Sub16 y x) for { @@ -19849,6 +20638,51 @@ func rewriteValuegeneric_OpNeg32(v *Value) bool { v.AuxInt = int32ToAuxInt(-c) return true } + // match: (Neg32 (Mul32 x (Const32 [c]))) + // result: (Mul32 x (Const32 [-c])) + for { + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + if v_0_1.Op != OpConst32 { + continue + } + t := v_0_1.Type + c := auxIntToInt32(v_0_1.AuxInt) + v.reset(OpMul32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(-c) + v.AddArg2(x, v0) + return true + } + break + } + // match: (Neg32 (Mul32 x (Neg32 y))) + // result: (Mul32 x y) + for { + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + if v_0_1.Op != OpNeg32 { + continue + } + y := v_0_1.Args[0] + v.reset(OpMul32) + v.AddArg2(x, y) + return true + } + break + } // match: (Neg32 (Sub32 x y)) // result: (Sub32 y x) for { @@ -19875,166 +20709,605 @@ func rewriteValuegeneric_OpNeg32(v *Value) bool { // result: (Add32 (Const32 [1]) x) for { t := v.Type - if v_0.Op != OpCom32 { + if v_0.Op != OpCom32 { + break + } + x := v_0.Args[0] + v.reset(OpAdd32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(1) + v.AddArg2(v0, x) + return true + } + return false +} +func rewriteValuegeneric_OpNeg32F(v *Value) bool { + v_0 := v.Args[0] + // match: (Neg32F (Const32F [c])) + // cond: c != 0 + // result: (Const32F [-c]) + for { + if v_0.Op != OpConst32F { + break + } + c := auxIntToFloat32(v_0.AuxInt) + if !(c != 0) { + break + } + v.reset(OpConst32F) + v.AuxInt = float32ToAuxInt(-c) + return true + } + return false +} +func rewriteValuegeneric_OpNeg64(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Neg64 (Const64 [c])) + // result: (Const64 [-c]) + for { + if v_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_0.AuxInt) + v.reset(OpConst64) + v.AuxInt = int64ToAuxInt(-c) + return true + } + // match: (Neg64 (Mul64 x (Const64 [c]))) + // result: (Mul64 x (Const64 [-c])) + for { + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + if v_0_1.Op != OpConst64 { + continue + } + t := v_0_1.Type + c := auxIntToInt64(v_0_1.AuxInt) + v.reset(OpMul64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(-c) + v.AddArg2(x, v0) + return true + } + break + } + // match: (Neg64 (Mul64 x (Neg64 y))) + // result: (Mul64 x y) + for { + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + if v_0_1.Op != OpNeg64 { + continue + } + y := v_0_1.Args[0] + v.reset(OpMul64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Neg64 (Sub64 x y)) + // result: (Sub64 y x) + for { + if v_0.Op != OpSub64 { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + v.reset(OpSub64) + v.AddArg2(y, x) + return true + } + // match: (Neg64 (Neg64 x)) + // result: x + for { + if v_0.Op != OpNeg64 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + // match: (Neg64 (Com64 x)) + // result: (Add64 (Const64 [1]) x) + for { + t := v.Type + if v_0.Op != OpCom64 { break } x := v_0.Args[0] - v.reset(OpAdd32) - v0 := b.NewValue0(v.Pos, OpConst32, t) - v0.AuxInt = int32ToAuxInt(1) + v.reset(OpAdd64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(1) v.AddArg2(v0, x) return true } return false } -func rewriteValuegeneric_OpNeg32F(v *Value) bool { +func rewriteValuegeneric_OpNeg64F(v *Value) bool { v_0 := v.Args[0] - // match: (Neg32F (Const32F [c])) + // match: (Neg64F (Const64F [c])) // cond: c != 0 - // result: (Const32F [-c]) + // result: (Const64F [-c]) for { - if v_0.Op != OpConst32F { + if v_0.Op != OpConst64F { break } - c := auxIntToFloat32(v_0.AuxInt) + c := auxIntToFloat64(v_0.AuxInt) if !(c != 0) { break } - v.reset(OpConst32F) - v.AuxInt = float32ToAuxInt(-c) + v.reset(OpConst64F) + v.AuxInt = float64ToAuxInt(-c) return true } return false } -func rewriteValuegeneric_OpNeg64(v *Value) bool { +func rewriteValuegeneric_OpNeg8(v *Value) bool { v_0 := v.Args[0] b := v.Block - // match: (Neg64 (Const64 [c])) - // result: (Const64 [-c]) + // match: (Neg8 (Const8 [c])) + // result: (Const8 [-c]) for { - if v_0.Op != OpConst64 { + if v_0.Op != OpConst8 { break } - c := auxIntToInt64(v_0.AuxInt) - v.reset(OpConst64) - v.AuxInt = int64ToAuxInt(-c) + c := auxIntToInt8(v_0.AuxInt) + v.reset(OpConst8) + v.AuxInt = int8ToAuxInt(-c) return true } - // match: (Neg64 (Sub64 x y)) - // result: (Sub64 y x) + // match: (Neg8 (Mul8 x (Const8 [c]))) + // result: (Mul8 x (Const8 [-c])) for { - if v_0.Op != OpSub64 { + if v_0.Op != OpMul8 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + if v_0_1.Op != OpConst8 { + continue + } + t := v_0_1.Type + c := auxIntToInt8(v_0_1.AuxInt) + v.reset(OpMul8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(-c) + v.AddArg2(x, v0) + return true + } + break + } + // match: (Neg8 (Mul8 x (Neg8 y))) + // result: (Mul8 x y) + for { + if v_0.Op != OpMul8 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + if v_0_1.Op != OpNeg8 { + continue + } + y := v_0_1.Args[0] + v.reset(OpMul8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Neg8 (Sub8 x y)) + // result: (Sub8 y x) + for { + if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] - v.reset(OpSub64) + v.reset(OpSub8) v.AddArg2(y, x) return true } - // match: (Neg64 (Neg64 x)) + // match: (Neg8 (Neg8 x)) // result: x for { - if v_0.Op != OpNeg64 { + if v_0.Op != OpNeg8 { break } x := v_0.Args[0] v.copyOf(x) return true } - // match: (Neg64 (Com64 x)) - // result: (Add64 (Const64 [1]) x) + // match: (Neg8 (Com8 x)) + // result: (Add8 (Const8 [1]) x) for { t := v.Type - if v_0.Op != OpCom64 { + if v_0.Op != OpCom8 { break } x := v_0.Args[0] - v.reset(OpAdd64) - v0 := b.NewValue0(v.Pos, OpConst64, t) - v0.AuxInt = int64ToAuxInt(1) + v.reset(OpAdd8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(1) v.AddArg2(v0, x) return true } return false } -func rewriteValuegeneric_OpNeg64F(v *Value) bool { +func rewriteValuegeneric_OpNeq16(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (Neg64F (Const64F [c])) - // cond: c != 0 - // result: (Const64F [-c]) + b := v.Block + // match: (Neq16 x x) + // result: (ConstBool [false]) for { - if v_0.Op != OpConst64F { + x := v_0 + if x != v_1 { break } - c := auxIntToFloat64(v_0.AuxInt) - if !(c != 0) { - break + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(false) + return true + } + // match: (Neq16 (Const16 [c]) o:(Add16 (Const16 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq16 (Const16 [c-d]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst16 { + continue + } + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpAdd16 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst16 { + continue + } + d := auxIntToInt16(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(c - d) + v.AddArg2(v0, x) + return true + } + } + break + } + // match: (Neq16 (Const16 [c]) o:(Sub16 x (Const16 [d]))) + // cond: o.Uses == 1 + // result: (Neq16 (Const16 [c+d]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst16 { + continue + } + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpSub16 { + continue + } + _ = o.Args[1] + x := o.Args[0] + o_1 := o.Args[1] + if o_1.Op != OpConst16 { + continue + } + d := auxIntToInt16(o_1.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(c + d) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Neq16 (Const16 [c]) o:(Sub16 (Const16 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq16 (Const16 [d-c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst16 { + continue + } + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpSub16 { + continue + } + x := o.Args[1] + o_0 := o.Args[0] + if o_0.Op != OpConst16 { + continue + } + d := auxIntToInt16(o_0.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(d - c) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Neq16 (Const16 [c]) o:(Xor16 (Const16 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq16 (Const16 [d^c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst16 { + continue + } + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpXor16 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst16 { + continue + } + d := auxIntToInt16(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(d ^ c) + v.AddArg2(v0, x) + return true + } + } + break + } + // match: (Neq16 (Const16 [c]) o:(Com16 x)) + // cond: o.Uses == 1 + // result: (Neq16 (Const16 [^c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst16 { + continue + } + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpCom16 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(^c) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Neq16 (Const16 [c]) o:(Neg16 x)) + // cond: o.Uses == 1 + // result: (Neq16 (Const16 [-c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst16 { + continue + } + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpNeg16 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(-c) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Neq16 (Const16 [c]) o:(Mul16 (Const16 [d]) x)) + // cond: uint16(d)%2 == 1 && o.Uses == 1 + // result: (Neq16 (Const16 [int16(uint16(c) * uint16(modularMultiplicativeInverse(uint64(d))))]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst16 { + continue + } + t := v_0.Type + c := auxIntToInt16(v_0.AuxInt) + o := v_1 + if o.Op != OpMul16 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst16 { + continue + } + d := auxIntToInt16(o_0.AuxInt) + x := o_1 + if !(uint16(d)%2 == 1 && o.Uses == 1) { + continue + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Pos, OpConst16, t) + v0.AuxInt = int16ToAuxInt(int16(uint16(c) * uint16(modularMultiplicativeInverse(uint64(d))))) + v.AddArg2(v0, x) + return true + } + } + break + } + // match: (Neq16 (Const16 [c]) (Const16 [d])) + // result: (ConstBool [c != d]) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_0.AuxInt) + if v_1.Op != OpConst16 { + continue + } + d := auxIntToInt16(v_1.AuxInt) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(c != d) + return true } - v.reset(OpConst64F) - v.AuxInt = float64ToAuxInt(-c) - return true + break } - return false -} -func rewriteValuegeneric_OpNeg8(v *Value) bool { - v_0 := v.Args[0] - b := v.Block - // match: (Neg8 (Const8 [c])) - // result: (Const8 [-c]) + // match: (Neq16 s:(Sub16 x y) (Const16 [0])) + // cond: s.Uses == 1 + // result: (Neq16 x y) for { - if v_0.Op != OpConst8 { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + s := v_0 + if s.Op != OpSub16 { + continue + } + y := s.Args[1] + x := s.Args[0] + if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(s.Uses == 1) { + continue + } + v.reset(OpNeq16) + v.AddArg2(x, y) + return true } - c := auxIntToInt8(v_0.AuxInt) - v.reset(OpConst8) - v.AuxInt = int8ToAuxInt(-c) - return true + break } - // match: (Neg8 (Sub8 x y)) - // result: (Sub8 y x) + // match: (Neq16 (And16 x (Const16 [y])) (Const16 [y])) + // cond: oneBit(y) + // result: (Eq16 (And16 x (Const16 [y])) (Const16 [0])) for { - if v_0.Op != OpSub8 { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAnd16 { + continue + } + t := v_0.Type + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { + x := v_0_0 + if v_0_1.Op != OpConst16 || v_0_1.Type != t { + continue + } + y := auxIntToInt16(v_0_1.AuxInt) + if v_1.Op != OpConst16 || v_1.Type != t || auxIntToInt16(v_1.AuxInt) != y || !(oneBit(y)) { + continue + } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpAnd16, t) + v1 := b.NewValue0(v.Pos, OpConst16, t) + v1.AuxInt = int16ToAuxInt(y) + v0.AddArg2(x, v1) + v2 := b.NewValue0(v.Pos, OpConst16, t) + v2.AuxInt = int16ToAuxInt(0) + v.AddArg2(v0, v2) + return true + } } - y := v_0.Args[1] - x := v_0.Args[0] - v.reset(OpSub8) - v.AddArg2(y, x) - return true + break } - // match: (Neg8 (Neg8 x)) + // match: (Neq16 (ZeroExt8to16 (CvtBoolToUint8 x)) (Const16 [0])) // result: x for { - if v_0.Op != OpNeg8 { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpZeroExt8to16 { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpCvtBoolToUint8 { + continue + } + x := v_0_0.Args[0] + if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 { + continue + } + v.copyOf(x) + return true } - x := v_0.Args[0] - v.copyOf(x) - return true + break } - // match: (Neg8 (Com8 x)) - // result: (Add8 (Const8 [1]) x) + // match: (Neq16 (ZeroExt8to16 (CvtBoolToUint8 x)) (Const16 [1])) + // result: (Not x) for { - t := v.Type - if v_0.Op != OpCom8 { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpZeroExt8to16 { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpCvtBoolToUint8 { + continue + } + x := v_0_0.Args[0] + if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 1 { + continue + } + v.reset(OpNot) + v.AddArg(x) + return true } - x := v_0.Args[0] - v.reset(OpAdd8) - v0 := b.NewValue0(v.Pos, OpConst8, t) - v0.AuxInt = int8ToAuxInt(1) - v.AddArg2(v0, x) - return true + break } return false } -func rewriteValuegeneric_OpNeq16(v *Value) bool { +func rewriteValuegeneric_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (Neq16 x x) + // match: (Neq32 x x) // result: (ConstBool [false]) for { x := v_0 @@ -20045,147 +21318,270 @@ func rewriteValuegeneric_OpNeq16(v *Value) bool { v.AuxInt = boolToAuxInt(false) return true } - // match: (Neq16 (Const16 [c]) (Add16 (Const16 [d]) x)) - // result: (Neq16 (Const16 [c-d]) x) + // match: (Neq32 (Const32 [c]) o:(Add32 (Const32 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq32 (Const32 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpConst16 { + if v_0.Op != OpConst32 { continue } t := v_0.Type - c := auxIntToInt16(v_0.AuxInt) - if v_1.Op != OpAdd16 { + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpAdd32 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst16 || v_1_0.Type != t { + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst32 { continue } - d := auxIntToInt16(v_1_0.AuxInt) - x := v_1_1 - v.reset(OpNeq16) - v0 := b.NewValue0(v.Pos, OpConst16, t) - v0.AuxInt = int16ToAuxInt(c - d) + d := auxIntToInt32(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } - // match: (Neq16 (Const16 [c]) (Const16 [d])) - // result: (ConstBool [c != d]) + // match: (Neq32 (Const32 [c]) o:(Sub32 x (Const32 [d]))) + // cond: o.Uses == 1 + // result: (Neq32 (Const32 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpConst16 { + if v_0.Op != OpConst32 { continue } - c := auxIntToInt16(v_0.AuxInt) - if v_1.Op != OpConst16 { + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpSub32 { continue } - d := auxIntToInt16(v_1.AuxInt) - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(c != d) + _ = o.Args[1] + x := o.Args[0] + o_1 := o.Args[1] + if o_1.Op != OpConst32 { + continue + } + d := auxIntToInt32(o_1.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(c + d) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Neq32 (Const32 [c]) o:(Sub32 (Const32 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq32 (Const32 [d-c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst32 { + continue + } + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpSub32 { + continue + } + x := o.Args[1] + o_0 := o.Args[0] + if o_0.Op != OpConst32 { + continue + } + d := auxIntToInt32(o_0.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(d - c) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Neq32 (Const32 [c]) o:(Xor32 (Const32 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq32 (Const32 [d^c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst32 { + continue + } + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpXor32 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst32 { + continue + } + d := auxIntToInt32(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(d ^ c) + v.AddArg2(v0, x) + return true + } + } + break + } + // match: (Neq32 (Const32 [c]) o:(Com32 x)) + // cond: o.Uses == 1 + // result: (Neq32 (Const32 [^c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst32 { + continue + } + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpCom32 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(^c) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Neq32 (Const32 [c]) o:(Neg32 x)) + // cond: o.Uses == 1 + // result: (Neq32 (Const32 [-c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst32 { + continue + } + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpNeg32 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(-c) + v.AddArg2(v0, x) return true } break } - // match: (Neq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) - // cond: k > 0 && k < 15 && kbar == 16 - k - // result: (Neq16 (And16 n (Const16 [1< [0])) + // match: (Neq32 (Const32 [c]) o:(Mul32 (Const32 [d]) x)) + // cond: uint32(d)%2 == 1 && o.Uses == 1 + // result: (Neq32 (Const32 [int32(uint32(c) * uint32(modularMultiplicativeInverse(uint64(d))))]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpLsh16x64 { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRsh16x64 { + if v_0.Op != OpConst32 { continue } - _ = v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAdd16 { + t := v_0.Type + c := auxIntToInt32(v_0.AuxInt) + o := v_1 + if o.Op != OpMul32 { continue } - t := v_1_0_0.Type - _ = v_1_0_0.Args[1] - v_1_0_0_0 := v_1_0_0.Args[0] - v_1_0_0_1 := v_1_0_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { - if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh16Ux64 || v_1_0_0_1.Type != t { - continue - } - _ = v_1_0_0_1.Args[1] - v_1_0_0_1_0 := v_1_0_0_1.Args[0] - if v_1_0_0_1_0.Op != OpRsh16x64 || v_1_0_0_1_0.Type != t { - continue - } - _ = v_1_0_0_1_0.Args[1] - if n != v_1_0_0_1_0.Args[0] { - continue - } - v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] - if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 15 { - continue - } - v_1_0_0_1_1 := v_1_0_0_1.Args[1] - if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst32 { continue } - kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { + d := auxIntToInt32(o_0.AuxInt) + x := o_1 + if !(uint32(d)%2 == 1 && o.Uses == 1) { continue } - k := auxIntToInt64(v_1_0_1.AuxInt) - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 15 && kbar == 16-k) { - continue - } - v.reset(OpNeq16) - v0 := b.NewValue0(v.Pos, OpAnd16, t) - v1 := b.NewValue0(v.Pos, OpConst16, t) - v1.AuxInt = int16ToAuxInt(1< x (Const16 [y])) (Const16 [y])) + // match: (Neq32 (And32 x (Const32 [y])) (Const32 [y])) // cond: oneBit(y) - // result: (Eq16 (And16 x (Const16 [y])) (Const16 [0])) + // result: (Eq32 (And32 x (Const32 [y])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAnd16 { + if v_0.Op != OpAnd32 { continue } t := v_0.Type @@ -20194,34 +21590,97 @@ func rewriteValuegeneric_OpNeq16(v *Value) bool { v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 - if v_0_1.Op != OpConst16 || v_0_1.Type != t { + if v_0_1.Op != OpConst32 || v_0_1.Type != t { continue } - y := auxIntToInt16(v_0_1.AuxInt) - if v_1.Op != OpConst16 || v_1.Type != t || auxIntToInt16(v_1.AuxInt) != y || !(oneBit(y)) { + y := auxIntToInt32(v_0_1.AuxInt) + if v_1.Op != OpConst32 || v_1.Type != t || auxIntToInt32(v_1.AuxInt) != y || !(oneBit(y)) { continue } - v.reset(OpEq16) - v0 := b.NewValue0(v.Pos, OpAnd16, t) - v1 := b.NewValue0(v.Pos, OpConst16, t) - v1.AuxInt = int16ToAuxInt(y) + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpAnd32, t) + v1 := b.NewValue0(v.Pos, OpConst32, t) + v1.AuxInt = int32ToAuxInt(y) v0.AddArg2(x, v1) - v2 := b.NewValue0(v.Pos, OpConst16, t) - v2.AuxInt = int16ToAuxInt(0) + v2 := b.NewValue0(v.Pos, OpConst32, t) + v2.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } + // match: (Neq32 (ZeroExt8to32 (CvtBoolToUint8 x)) (Const32 [0])) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpZeroExt8to32 { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpCvtBoolToUint8 { + continue + } + x := v_0_0.Args[0] + if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != 0 { + continue + } + v.copyOf(x) + return true + } + break + } + // match: (Neq32 (ZeroExt8to32 (CvtBoolToUint8 x)) (Const32 [1])) + // result: (Not x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpZeroExt8to32 { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpCvtBoolToUint8 { + continue + } + x := v_0_0.Args[0] + if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != 1 { + continue + } + v.reset(OpNot) + v.AddArg(x) + return true + } + break + } return false } -func rewriteValuegeneric_OpNeq32(v *Value) bool { +func rewriteValuegeneric_OpNeq32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (Neq32F (Const32F [c]) (Const32F [d])) + // result: (ConstBool [c != d]) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst32F { + continue + } + c := auxIntToFloat32(v_0.AuxInt) + if v_1.Op != OpConst32F { + continue + } + d := auxIntToFloat32(v_1.AuxInt) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(c != d) + return true + } + break + } + return false +} +func rewriteValuegeneric_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (Neq32 x x) + // match: (Neq64 x x) // result: (ConstBool [false]) for { x := v_0 @@ -20232,218 +21691,194 @@ func rewriteValuegeneric_OpNeq32(v *Value) bool { v.AuxInt = boolToAuxInt(false) return true } - // match: (Neq32 (Const32 [c]) (Add32 (Const32 [d]) x)) - // result: (Neq32 (Const32 [c-d]) x) + // match: (Neq64 (Const64 [c]) o:(Add64 (Const64 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq64 (Const64 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpConst32 { + if v_0.Op != OpConst64 { continue } t := v_0.Type - c := auxIntToInt32(v_0.AuxInt) - if v_1.Op != OpAdd32 { + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpAdd64 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst32 || v_1_0.Type != t { + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst64 { continue } - d := auxIntToInt32(v_1_0.AuxInt) - x := v_1_1 - v.reset(OpNeq32) - v0 := b.NewValue0(v.Pos, OpConst32, t) - v0.AuxInt = int32ToAuxInt(c - d) + d := auxIntToInt64(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } - // match: (Neq32 (Const32 [c]) (Const32 [d])) - // result: (ConstBool [c != d]) + // match: (Neq64 (Const64 [c]) o:(Sub64 x (Const64 [d]))) + // cond: o.Uses == 1 + // result: (Neq64 (Const64 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpConst32 { + if v_0.Op != OpConst64 { continue } - c := auxIntToInt32(v_0.AuxInt) - if v_1.Op != OpConst32 { + t := v_0.Type + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpSub64 { continue } - d := auxIntToInt32(v_1.AuxInt) - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(c != d) + _ = o.Args[1] + x := o.Args[0] + o_1 := o.Args[1] + if o_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(o_1.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(c + d) + v.AddArg2(v0, x) return true } break } - // match: (Neq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) - // cond: k > 0 && k < 31 && kbar == 32 - k - // result: (Neq32 (And32 n (Const32 [1< [0])) + // match: (Neq64 (Const64 [c]) o:(Sub64 (Const64 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq64 (Const64 [d-c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpLsh32x64 { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRsh32x64 { + if v_0.Op != OpConst64 { continue } - _ = v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAdd32 { + t := v_0.Type + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpSub64 { continue } - t := v_1_0_0.Type - _ = v_1_0_0.Args[1] - v_1_0_0_0 := v_1_0_0.Args[0] - v_1_0_0_1 := v_1_0_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { - if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh32Ux64 || v_1_0_0_1.Type != t { - continue - } - _ = v_1_0_0_1.Args[1] - v_1_0_0_1_0 := v_1_0_0_1.Args[0] - if v_1_0_0_1_0.Op != OpRsh32x64 || v_1_0_0_1_0.Type != t { - continue - } - _ = v_1_0_0_1_0.Args[1] - if n != v_1_0_0_1_0.Args[0] { - continue - } - v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] - if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 31 { - continue - } - v_1_0_0_1_1 := v_1_0_0_1.Args[1] - if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { - continue - } - kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { - continue - } - k := auxIntToInt64(v_1_0_1.AuxInt) - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 31 && kbar == 32-k) { - continue - } - v.reset(OpNeq32) - v0 := b.NewValue0(v.Pos, OpAnd32, t) - v1 := b.NewValue0(v.Pos, OpConst32, t) - v1.AuxInt = int32ToAuxInt(1< x (Const32 [y])) (Const32 [y])) - // cond: oneBit(y) - // result: (Eq32 (And32 x (Const32 [y])) (Const32 [0])) + // match: (Neq64 (Const64 [c]) o:(Xor64 (Const64 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq64 (Const64 [d^c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAnd32 { + if v_0.Op != OpConst64 { continue } t := v_0.Type - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { - x := v_0_0 - if v_0_1.Op != OpConst32 || v_0_1.Type != t { + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpXor64 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst64 { continue } - y := auxIntToInt32(v_0_1.AuxInt) - if v_1.Op != OpConst32 || v_1.Type != t || auxIntToInt32(v_1.AuxInt) != y || !(oneBit(y)) { + d := auxIntToInt64(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { continue - } - v.reset(OpEq32) - v0 := b.NewValue0(v.Pos, OpAnd32, t) - v1 := b.NewValue0(v.Pos, OpConst32, t) - v1.AuxInt = int32ToAuxInt(y) - v0.AddArg2(x, v1) - v2 := b.NewValue0(v.Pos, OpConst32, t) - v2.AuxInt = int32ToAuxInt(0) - v.AddArg2(v0, v2) + } + v.reset(OpNeq64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(d ^ c) + v.AddArg2(v0, x) return true } } break } - return false -} -func rewriteValuegeneric_OpNeq32F(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (Neq32F (Const32F [c]) (Const32F [d])) - // result: (ConstBool [c != d]) + // match: (Neq64 (Const64 [c]) o:(Com64 x)) + // cond: o.Uses == 1 + // result: (Neq64 (Const64 [^c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpConst32F { + if v_0.Op != OpConst64 { continue } - c := auxIntToFloat32(v_0.AuxInt) - if v_1.Op != OpConst32F { + t := v_0.Type + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpCom64 { continue } - d := auxIntToFloat32(v_1.AuxInt) - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(c != d) + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(^c) + v.AddArg2(v0, x) return true } break } - return false -} -func rewriteValuegeneric_OpNeq64(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (Neq64 x x) - // result: (ConstBool [false]) + // match: (Neq64 (Const64 [c]) o:(Neg64 x)) + // cond: o.Uses == 1 + // result: (Neq64 (Const64 [-c]) x) for { - x := v_0 - if x != v_1 { - break + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst64 { + continue + } + t := v_0.Type + c := auxIntToInt64(v_0.AuxInt) + o := v_1 + if o.Op != OpNeg64 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq64) + v0 := b.NewValue0(v.Pos, OpConst64, t) + v0.AuxInt = int64ToAuxInt(-c) + v.AddArg2(v0, x) + return true } - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(false) - return true + break } - // match: (Neq64 (Const64 [c]) (Add64 (Const64 [d]) x)) - // result: (Neq64 (Const64 [c-d]) x) + // match: (Neq64 (Const64 [c]) o:(Mul64 (Const64 [d]) x)) + // cond: uint64(d)%2 == 1 && o.Uses == 1 + // result: (Neq64 (Const64 [int64(uint64(c) * modularMultiplicativeInverse(uint64(d))) ]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { @@ -20451,21 +21886,25 @@ func rewriteValuegeneric_OpNeq64(v *Value) bool { } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) - if v_1.Op != OpAdd64 { + o := v_1 + if o.Op != OpMul64 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst64 || v_1_0.Type != t { + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst64 { + continue + } + d := auxIntToInt64(o_0.AuxInt) + x := o_1 + if !(uint64(d)%2 == 1 && o.Uses == 1) { continue } - d := auxIntToInt64(v_1_0.AuxInt) - x := v_1_1 v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) - v0.AuxInt = int64ToAuxInt(c - d) + v0.AuxInt = int64ToAuxInt(int64(uint64(c) * modularMultiplicativeInverse(uint64(d)))) v.AddArg2(v0, x) return true } @@ -20490,73 +21929,6 @@ func rewriteValuegeneric_OpNeq64(v *Value) bool { } break } - // match: (Neq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) - // cond: k > 0 && k < 63 && kbar == 64 - k - // result: (Neq64 (And64 n (Const64 [1< [0])) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpLsh64x64 { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRsh64x64 { - continue - } - _ = v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAdd64 { - continue - } - t := v_1_0_0.Type - _ = v_1_0_0.Args[1] - v_1_0_0_0 := v_1_0_0.Args[0] - v_1_0_0_1 := v_1_0_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { - if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh64Ux64 || v_1_0_0_1.Type != t { - continue - } - _ = v_1_0_0_1.Args[1] - v_1_0_0_1_0 := v_1_0_0_1.Args[0] - if v_1_0_0_1_0.Op != OpRsh64x64 || v_1_0_0_1_0.Type != t { - continue - } - _ = v_1_0_0_1_0.Args[1] - if n != v_1_0_0_1_0.Args[0] { - continue - } - v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] - if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 63 { - continue - } - v_1_0_0_1_1 := v_1_0_0_1.Args[1] - if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { - continue - } - kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { - continue - } - k := auxIntToInt64(v_1_0_1.AuxInt) - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 63 && kbar == 64-k) { - continue - } - v.reset(OpNeq64) - v0 := b.NewValue0(v.Pos, OpAnd64, t) - v1 := b.NewValue0(v.Pos, OpConst64, t) - v1.AuxInt = int64ToAuxInt(1< [c]) (Add8 (Const8 [d]) x)) + // match: (Neq8 (Const8 [c]) o:(Add8 (Const8 [d]) x)) + // cond: o.Uses == 1 // result: (Neq8 (Const8 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { @@ -20661,18 +22074,22 @@ func rewriteValuegeneric_OpNeq8(v *Value) bool { } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) - if v_1.Op != OpAdd8 { + o := v_1 + if o.Op != OpAdd8 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpConst8 || v_1_0.Type != t { + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst8 { + continue + } + d := auxIntToInt8(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { continue } - d := auxIntToInt8(v_1_0.AuxInt) - x := v_1_1 v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) @@ -20682,91 +22099,209 @@ func rewriteValuegeneric_OpNeq8(v *Value) bool { } break } - // match: (Neq8 (Const8 [c]) (Const8 [d])) - // result: (ConstBool [c != d]) + // match: (Neq8 (Const8 [c]) o:(Sub8 x (Const8 [d]))) + // cond: o.Uses == 1 + // result: (Neq8 (Const8 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } + t := v_0.Type c := auxIntToInt8(v_0.AuxInt) - if v_1.Op != OpConst8 { + o := v_1 + if o.Op != OpSub8 { continue } - d := auxIntToInt8(v_1.AuxInt) - v.reset(OpConstBool) - v.AuxInt = boolToAuxInt(c != d) + _ = o.Args[1] + x := o.Args[0] + o_1 := o.Args[1] + if o_1.Op != OpConst8 { + continue + } + d := auxIntToInt8(o_1.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(c + d) + v.AddArg2(v0, x) return true } break } - // match: (Neq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) - // cond: k > 0 && k < 7 && kbar == 8 - k - // result: (Neq8 (And8 n (Const8 [1< [0])) + // match: (Neq8 (Const8 [c]) o:(Sub8 (Const8 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq8 (Const8 [d-c]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - n := v_0 - if v_1.Op != OpLsh8x64 { + if v_0.Op != OpConst8 { continue } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpRsh8x64 { + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + o := v_1 + if o.Op != OpSub8 { continue } - _ = v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAdd8 { + x := o.Args[1] + o_0 := o.Args[0] + if o_0.Op != OpConst8 { continue } - t := v_1_0_0.Type - _ = v_1_0_0.Args[1] - v_1_0_0_0 := v_1_0_0.Args[0] - v_1_0_0_1 := v_1_0_0.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { - if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh8Ux64 || v_1_0_0_1.Type != t { - continue - } - _ = v_1_0_0_1.Args[1] - v_1_0_0_1_0 := v_1_0_0_1.Args[0] - if v_1_0_0_1_0.Op != OpRsh8x64 || v_1_0_0_1_0.Type != t { - continue - } - _ = v_1_0_0_1_0.Args[1] - if n != v_1_0_0_1_0.Args[0] { - continue - } - v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] - if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 7 { - continue - } - v_1_0_0_1_1 := v_1_0_0_1.Args[1] - if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { - continue - } - kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { + d := auxIntToInt8(o_0.AuxInt) + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(d - c) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Neq8 (Const8 [c]) o:(Xor8 (Const8 [d]) x)) + // cond: o.Uses == 1 + // result: (Neq8 (Const8 [d^c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst8 { + continue + } + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + o := v_1 + if o.Op != OpXor8 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst8 { continue } - k := auxIntToInt64(v_1_0_1.AuxInt) - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 7 && kbar == 8-k) { + d := auxIntToInt8(o_0.AuxInt) + x := o_1 + if !(o.Uses == 1) { continue } v.reset(OpNeq8) - v0 := b.NewValue0(v.Pos, OpAnd8, t) - v1 := b.NewValue0(v.Pos, OpConst8, t) - v1.AuxInt = int8ToAuxInt(1< [c]) o:(Com8 x)) + // cond: o.Uses == 1 + // result: (Neq8 (Const8 [^c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst8 { + continue + } + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + o := v_1 + if o.Op != OpCom8 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(^c) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Neq8 (Const8 [c]) o:(Neg8 x)) + // cond: o.Uses == 1 + // result: (Neq8 (Const8 [-c]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst8 { + continue + } + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + o := v_1 + if o.Op != OpNeg8 { + continue + } + x := o.Args[0] + if !(o.Uses == 1) { + continue + } + v.reset(OpNeq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(-c) + v.AddArg2(v0, x) + return true + } + break + } + // match: (Neq8 (Const8 [c]) o:(Mul8 (Const8 [d]) x)) + // cond: uint8( d)%2 == 1 && o.Uses == 1 + // result: (Neq8 (Const8 [int8( uint8( c) * uint8( modularMultiplicativeInverse(uint64(d))))]) x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst8 { + continue + } + t := v_0.Type + c := auxIntToInt8(v_0.AuxInt) + o := v_1 + if o.Op != OpMul8 { + continue + } + _ = o.Args[1] + o_0 := o.Args[0] + o_1 := o.Args[1] + for _i1 := 0; _i1 <= 1; _i1, o_0, o_1 = _i1+1, o_1, o_0 { + if o_0.Op != OpConst8 { + continue + } + d := auxIntToInt8(o_0.AuxInt) + x := o_1 + if !(uint8(d)%2 == 1 && o.Uses == 1) { + continue + } + v.reset(OpNeq8) + v0 := b.NewValue0(v.Pos, OpConst8, t) + v0.AuxInt = int8ToAuxInt(int8(uint8(c) * uint8(modularMultiplicativeInverse(uint64(d))))) + v.AddArg2(v0, x) return true } } break } + // match: (Neq8 (Const8 [c]) (Const8 [d])) + // result: (ConstBool [c != d]) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_0.AuxInt) + if v_1.Op != OpConst8 { + continue + } + d := auxIntToInt8(v_1.AuxInt) + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(c != d) + return true + } + break + } // match: (Neq8 s:(Sub8 x y) (Const8 [0])) // cond: s.Uses == 1 // result: (Neq8 x y) @@ -20821,11 +22356,55 @@ func rewriteValuegeneric_OpNeq8(v *Value) bool { } break } + // match: (Neq8 (CvtBoolToUint8 x) (Const8 [0])) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpCvtBoolToUint8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 { + continue + } + v.copyOf(x) + return true + } + break + } + // match: (Neq8 (CvtBoolToUint8 x) (Const8 [1])) + // result: (Not x) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpCvtBoolToUint8 { + continue + } + x := v_0.Args[0] + if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 1 { + continue + } + v.reset(OpNot) + v.AddArg(x) + return true + } + break + } return false } func rewriteValuegeneric_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + // match: (NeqB x x) + // result: (ConstBool [false]) + for { + x := v_0 + if x != v_1 { + break + } + v.reset(OpConstBool) + v.AuxInt = boolToAuxInt(false) + return true + } // match: (NeqB (ConstBool [c]) (ConstBool [d])) // result: (ConstBool [c != d]) for { @@ -20871,19 +22450,16 @@ func rewriteValuegeneric_OpNeqB(v *Value) bool { } break } - // match: (NeqB (Not x) (Not y)) - // result: (NeqB x y) + // match: (NeqB (Not x) y) + // result: (EqB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpNot { continue } x := v_0.Args[0] - if v_1.Op != OpNot { - continue - } - y := v_1.Args[0] - v.reset(OpNeqB) + y := v_1 + v.reset(OpEqB) v.AddArg2(x, y) return true } @@ -21919,6 +23495,27 @@ func rewriteValuegeneric_OpOr16(v *Value) bool { } break } + // match: (Or16 x (And16 x y)) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAnd16 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if x != v_1_0 { + continue + } + v.copyOf(x) + return true + } + } + break + } // match: (Or16 x x) // result: x for { @@ -22444,6 +24041,27 @@ func rewriteValuegeneric_OpOr32(v *Value) bool { } break } + // match: (Or32 x (And32 x y)) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAnd32 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if x != v_1_0 { + continue + } + v.copyOf(x) + return true + } + } + break + } // match: (Or32 x x) // result: x for { @@ -22969,6 +24587,27 @@ func rewriteValuegeneric_OpOr64(v *Value) bool { } break } + // match: (Or64 x (And64 x y)) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAnd64 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if x != v_1_0 { + continue + } + v.copyOf(x) + return true + } + } + break + } // match: (Or64 x x) // result: x for { @@ -23494,6 +25133,27 @@ func rewriteValuegeneric_OpOr8(v *Value) bool { } break } + // match: (Or8 x (And8 x y)) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpAnd8 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if x != v_1_0 { + continue + } + v.copyOf(x) + return true + } + } + break + } // match: (Or8 x x) // result: x for { @@ -25292,6 +26952,182 @@ func rewriteValuegeneric_OpOrB(v *Value) bool { } break } + // match: (OrB (Eq64 x cv:(Const64 [c])) (Eq64 x (Const64 [d]))) + // cond: c|d == c && oneBit(c^d) + // result: (Eq64 (Or64 x (Const64 [c^d])) cv) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpEq64 { + continue + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { + x := v_0_0 + cv := v_0_1 + if cv.Op != OpConst64 { + continue + } + c := auxIntToInt64(cv.AuxInt) + if v_1.Op != OpEq64 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { + if x != v_1_0 || v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c|d == c && oneBit(c^d)) { + continue + } + v.reset(OpEq64) + v0 := b.NewValue0(v.Pos, OpOr64, x.Type) + v1 := b.NewValue0(v.Pos, OpConst64, x.Type) + v1.AuxInt = int64ToAuxInt(c ^ d) + v0.AddArg2(x, v1) + v.AddArg2(v0, cv) + return true + } + } + } + break + } + // match: (OrB (Eq32 x cv:(Const32 [c])) (Eq32 x (Const32 [d]))) + // cond: c|d == c && oneBit(c^d) + // result: (Eq32 (Or32 x (Const32 [c^d])) cv) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpEq32 { + continue + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { + x := v_0_0 + cv := v_0_1 + if cv.Op != OpConst32 { + continue + } + c := auxIntToInt32(cv.AuxInt) + if v_1.Op != OpEq32 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { + if x != v_1_0 || v_1_1.Op != OpConst32 { + continue + } + d := auxIntToInt32(v_1_1.AuxInt) + if !(c|d == c && oneBit(c^d)) { + continue + } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpOr32, x.Type) + v1 := b.NewValue0(v.Pos, OpConst32, x.Type) + v1.AuxInt = int32ToAuxInt(c ^ d) + v0.AddArg2(x, v1) + v.AddArg2(v0, cv) + return true + } + } + } + break + } + // match: (OrB (Eq16 x cv:(Const16 [c])) (Eq16 x (Const16 [d]))) + // cond: c|d == c && oneBit(c^d) + // result: (Eq16 (Or16 x (Const16 [c^d])) cv) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpEq16 { + continue + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { + x := v_0_0 + cv := v_0_1 + if cv.Op != OpConst16 { + continue + } + c := auxIntToInt16(cv.AuxInt) + if v_1.Op != OpEq16 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { + if x != v_1_0 || v_1_1.Op != OpConst16 { + continue + } + d := auxIntToInt16(v_1_1.AuxInt) + if !(c|d == c && oneBit(c^d)) { + continue + } + v.reset(OpEq16) + v0 := b.NewValue0(v.Pos, OpOr16, x.Type) + v1 := b.NewValue0(v.Pos, OpConst16, x.Type) + v1.AuxInt = int16ToAuxInt(c ^ d) + v0.AddArg2(x, v1) + v.AddArg2(v0, cv) + return true + } + } + } + break + } + // match: (OrB (Eq8 x cv:(Const8 [c])) (Eq8 x (Const8 [d]))) + // cond: c|d == c && oneBit(c^d) + // result: (Eq8 (Or8 x (Const8 [c^d])) cv) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpEq8 { + continue + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { + x := v_0_0 + cv := v_0_1 + if cv.Op != OpConst8 { + continue + } + c := auxIntToInt8(cv.AuxInt) + if v_1.Op != OpEq8 { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { + if x != v_1_0 || v_1_1.Op != OpConst8 { + continue + } + d := auxIntToInt8(v_1_1.AuxInt) + if !(c|d == c && oneBit(c^d)) { + continue + } + v.reset(OpEq8) + v0 := b.NewValue0(v.Pos, OpOr8, x.Type) + v1 := b.NewValue0(v.Pos, OpConst8, x.Type) + v1.AuxInt = int8ToAuxInt(c ^ d) + v0.AddArg2(x, v1) + v.AddArg2(v0, cv) + return true + } + } + } + break + } // match: (OrB (Neq64F x x) (Less64F x y:(Const64F [c]))) // result: (Not (Leq64F y x)) for { @@ -26151,6 +27987,7 @@ func rewriteValuegeneric_OpRotateLeft16(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (RotateLeft16 x (Const16 [c])) // cond: c%16 == 0 // result: x @@ -26594,21 +28431,20 @@ func rewriteValuegeneric_OpRotateLeft16(v *Value) bool { v.AddArg2(x, v0) return true } - // match: (RotateLeft16 x (Const64 [c])) + // match: (RotateLeft16 x (Const64 [c])) // cond: config.PtrSize == 4 - // result: (RotateLeft16 x (Const32 [int32(c)])) + // result: (RotateLeft16 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } - t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft16) - v0 := b.NewValue0(v.Pos, OpConst32, t) + v0 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true @@ -26696,6 +28532,7 @@ func rewriteValuegeneric_OpRotateLeft32(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (RotateLeft32 x (Const32 [c])) // cond: c%32 == 0 // result: x @@ -27139,21 +28976,20 @@ func rewriteValuegeneric_OpRotateLeft32(v *Value) bool { v.AddArg2(x, v0) return true } - // match: (RotateLeft32 x (Const64 [c])) + // match: (RotateLeft32 x (Const64 [c])) // cond: config.PtrSize == 4 - // result: (RotateLeft32 x (Const32 [int32(c)])) + // result: (RotateLeft32 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } - t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft32) - v0 := b.NewValue0(v.Pos, OpConst32, t) + v0 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true @@ -27241,6 +29077,7 @@ func rewriteValuegeneric_OpRotateLeft64(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (RotateLeft64 x (Const64 [c])) // cond: c%64 == 0 // result: x @@ -27684,21 +29521,20 @@ func rewriteValuegeneric_OpRotateLeft64(v *Value) bool { v.AddArg2(x, v0) return true } - // match: (RotateLeft64 x (Const64 [c])) + // match: (RotateLeft64 x (Const64 [c])) // cond: config.PtrSize == 4 - // result: (RotateLeft64 x (Const32 [int32(c)])) + // result: (RotateLeft64 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } - t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft64) - v0 := b.NewValue0(v.Pos, OpConst32, t) + v0 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true @@ -27786,6 +29622,7 @@ func rewriteValuegeneric_OpRotateLeft8(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config + typ := &b.Func.Config.Types // match: (RotateLeft8 x (Const8 [c])) // cond: c%8 == 0 // result: x @@ -28229,21 +30066,20 @@ func rewriteValuegeneric_OpRotateLeft8(v *Value) bool { v.AddArg2(x, v0) return true } - // match: (RotateLeft8 x (Const64 [c])) + // match: (RotateLeft8 x (Const64 [c])) // cond: config.PtrSize == 4 - // result: (RotateLeft8 x (Const32 [int32(c)])) + // result: (RotateLeft8 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } - t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft8) - v0 := b.NewValue0(v.Pos, OpConst32, t) + v0 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true @@ -28373,17 +30209,16 @@ func rewriteValuegeneric_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh16Ux16 x (Const16 [c])) - // result: (Rsh16Ux64 x (Const64 [int64(uint16(c))])) + // match: (Rsh16Ux16 x (Const16 [c])) + // result: (Rsh16Ux64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh16Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -28398,23 +30233,43 @@ func rewriteValuegeneric_OpRsh16Ux16(v *Value) bool { v.AuxInt = int16ToAuxInt(0) return true } + // match: (Rsh16Ux16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 16 + // result: (Rsh16Ux16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpRsh16Ux16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh16Ux32 x (Const32 [c])) - // result: (Rsh16Ux64 x (Const64 [int64(uint32(c))])) + // match: (Rsh16Ux32 x (Const32 [c])) + // result: (Rsh16Ux64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh16Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -28429,6 +30284,27 @@ func rewriteValuegeneric_OpRsh16Ux32(v *Value) bool { v.AuxInt = int16ToAuxInt(0) return true } + // match: (Rsh16Ux32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 16 + // result: (Rsh16Ux32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpRsh16Ux32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh16Ux64(v *Value) bool { @@ -28613,23 +30489,43 @@ func rewriteValuegeneric_OpRsh16Ux64(v *Value) bool { v.AddArg(v0) return true } + // match: (Rsh16Ux64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 16 + // result: (Rsh16Ux64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpRsh16Ux64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh16Ux8 x (Const8 [c])) - // result: (Rsh16Ux64 x (Const64 [int64(uint8(c))])) + // match: (Rsh16Ux8 x (Const8 [c])) + // result: (Rsh16Ux64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh16Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -28644,23 +30540,43 @@ func rewriteValuegeneric_OpRsh16Ux8(v *Value) bool { v.AuxInt = int16ToAuxInt(0) return true } + // match: (Rsh16Ux8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 16 + // result: (Rsh16Ux8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpRsh16Ux8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh16x16 x (Const16 [c])) - // result: (Rsh16x64 x (Const64 [int64(uint16(c))])) + // match: (Rsh16x16 x (Const16 [c])) + // result: (Rsh16x64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh16x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -28675,23 +30591,43 @@ func rewriteValuegeneric_OpRsh16x16(v *Value) bool { v.AuxInt = int16ToAuxInt(0) return true } + // match: (Rsh16x16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 16 + // result: (Rsh16x16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpRsh16x16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh16x32 x (Const32 [c])) - // result: (Rsh16x64 x (Const64 [int64(uint32(c))])) + // match: (Rsh16x32 x (Const32 [c])) + // result: (Rsh16x64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh16x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -28706,6 +30642,27 @@ func rewriteValuegeneric_OpRsh16x32(v *Value) bool { v.AuxInt = int16ToAuxInt(0) return true } + // match: (Rsh16x32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 16 + // result: (Rsh16x32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpRsh16x32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh16x64(v *Value) bool { @@ -28794,23 +30751,43 @@ func rewriteValuegeneric_OpRsh16x64(v *Value) bool { v.AddArg(v0) return true } + // match: (Rsh16x64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 16 + // result: (Rsh16x64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpRsh16x64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh16x8 x (Const8 [c])) - // result: (Rsh16x64 x (Const64 [int64(uint8(c))])) + // match: (Rsh16x8 x (Const8 [c])) + // result: (Rsh16x64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh16x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -28825,23 +30802,43 @@ func rewriteValuegeneric_OpRsh16x8(v *Value) bool { v.AuxInt = int16ToAuxInt(0) return true } + // match: (Rsh16x8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 16 + // result: (Rsh16x8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 16) { + break + } + v.reset(OpRsh16x8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh32Ux16 x (Const16 [c])) - // result: (Rsh32Ux64 x (Const64 [int64(uint16(c))])) + // match: (Rsh32Ux16 x (Const16 [c])) + // result: (Rsh32Ux64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh32Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -28856,23 +30853,43 @@ func rewriteValuegeneric_OpRsh32Ux16(v *Value) bool { v.AuxInt = int32ToAuxInt(0) return true } + // match: (Rsh32Ux16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 32 + // result: (Rsh32Ux16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpRsh32Ux16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh32Ux32 x (Const32 [c])) - // result: (Rsh32Ux64 x (Const64 [int64(uint32(c))])) + // match: (Rsh32Ux32 x (Const32 [c])) + // result: (Rsh32Ux64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh32Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -28887,6 +30904,27 @@ func rewriteValuegeneric_OpRsh32Ux32(v *Value) bool { v.AuxInt = int32ToAuxInt(0) return true } + // match: (Rsh32Ux32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 32 + // result: (Rsh32Ux32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpRsh32Ux32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh32Ux64(v *Value) bool { @@ -29089,23 +31127,43 @@ func rewriteValuegeneric_OpRsh32Ux64(v *Value) bool { v.AddArg(v0) return true } + // match: (Rsh32Ux64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 32 + // result: (Rsh32Ux64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpRsh32Ux64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh32Ux8 x (Const8 [c])) - // result: (Rsh32Ux64 x (Const64 [int64(uint8(c))])) + // match: (Rsh32Ux8 x (Const8 [c])) + // result: (Rsh32Ux64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh32Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -29120,23 +31178,43 @@ func rewriteValuegeneric_OpRsh32Ux8(v *Value) bool { v.AuxInt = int32ToAuxInt(0) return true } + // match: (Rsh32Ux8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 32 + // result: (Rsh32Ux8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpRsh32Ux8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh32x16 x (Const16 [c])) - // result: (Rsh32x64 x (Const64 [int64(uint16(c))])) + // match: (Rsh32x16 x (Const16 [c])) + // result: (Rsh32x64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh32x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -29151,23 +31229,43 @@ func rewriteValuegeneric_OpRsh32x16(v *Value) bool { v.AuxInt = int32ToAuxInt(0) return true } + // match: (Rsh32x16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 32 + // result: (Rsh32x16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpRsh32x16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh32x32 x (Const32 [c])) - // result: (Rsh32x64 x (Const64 [int64(uint32(c))])) + // match: (Rsh32x32 x (Const32 [c])) + // result: (Rsh32x64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh32x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -29182,6 +31280,27 @@ func rewriteValuegeneric_OpRsh32x32(v *Value) bool { v.AuxInt = int32ToAuxInt(0) return true } + // match: (Rsh32x32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 32 + // result: (Rsh32x32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpRsh32x32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh32x64(v *Value) bool { @@ -29288,23 +31407,43 @@ func rewriteValuegeneric_OpRsh32x64(v *Value) bool { v.AddArg(v0) return true } + // match: (Rsh32x64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 32 + // result: (Rsh32x64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpRsh32x64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh32x8 x (Const8 [c])) - // result: (Rsh32x64 x (Const64 [int64(uint8(c))])) + // match: (Rsh32x8 x (Const8 [c])) + // result: (Rsh32x64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh32x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -29319,23 +31458,43 @@ func rewriteValuegeneric_OpRsh32x8(v *Value) bool { v.AuxInt = int32ToAuxInt(0) return true } + // match: (Rsh32x8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 32 + // result: (Rsh32x8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 32) { + break + } + v.reset(OpRsh32x8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh64Ux16 x (Const16 [c])) - // result: (Rsh64Ux64 x (Const64 [int64(uint16(c))])) + // match: (Rsh64Ux16 x (Const16 [c])) + // result: (Rsh64Ux64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh64Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -29350,23 +31509,43 @@ func rewriteValuegeneric_OpRsh64Ux16(v *Value) bool { v.AuxInt = int64ToAuxInt(0) return true } + // match: (Rsh64Ux16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 64 + // result: (Rsh64Ux16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpRsh64Ux16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh64Ux32 x (Const32 [c])) - // result: (Rsh64Ux64 x (Const64 [int64(uint32(c))])) + // match: (Rsh64Ux32 x (Const32 [c])) + // result: (Rsh64Ux64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh64Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -29381,6 +31560,27 @@ func rewriteValuegeneric_OpRsh64Ux32(v *Value) bool { v.AuxInt = int64ToAuxInt(0) return true } + // match: (Rsh64Ux32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 64 + // result: (Rsh64Ux32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpRsh64Ux32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh64Ux64(v *Value) bool { @@ -29601,23 +31801,43 @@ func rewriteValuegeneric_OpRsh64Ux64(v *Value) bool { v.AddArg(v0) return true } + // match: (Rsh64Ux64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 64 + // result: (Rsh64Ux64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpRsh64Ux64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh64Ux8 x (Const8 [c])) - // result: (Rsh64Ux64 x (Const64 [int64(uint8(c))])) + // match: (Rsh64Ux8 x (Const8 [c])) + // result: (Rsh64Ux64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh64Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -29632,23 +31852,43 @@ func rewriteValuegeneric_OpRsh64Ux8(v *Value) bool { v.AuxInt = int64ToAuxInt(0) return true } + // match: (Rsh64Ux8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 64 + // result: (Rsh64Ux8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpRsh64Ux8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh64x16 x (Const16 [c])) - // result: (Rsh64x64 x (Const64 [int64(uint16(c))])) + // match: (Rsh64x16 x (Const16 [c])) + // result: (Rsh64x64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh64x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -29663,23 +31903,43 @@ func rewriteValuegeneric_OpRsh64x16(v *Value) bool { v.AuxInt = int64ToAuxInt(0) return true } + // match: (Rsh64x16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 64 + // result: (Rsh64x16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpRsh64x16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh64x32 x (Const32 [c])) - // result: (Rsh64x64 x (Const64 [int64(uint32(c))])) + // match: (Rsh64x32 x (Const32 [c])) + // result: (Rsh64x64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh64x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -29694,6 +31954,27 @@ func rewriteValuegeneric_OpRsh64x32(v *Value) bool { v.AuxInt = int64ToAuxInt(0) return true } + // match: (Rsh64x32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 64 + // result: (Rsh64x32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpRsh64x32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh64x64(v *Value) bool { @@ -29818,23 +32099,43 @@ func rewriteValuegeneric_OpRsh64x64(v *Value) bool { v.AddArg(v0) return true } + // match: (Rsh64x64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 64 + // result: (Rsh64x64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpRsh64x64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh64x8 x (Const8 [c])) - // result: (Rsh64x64 x (Const64 [int64(uint8(c))])) + // match: (Rsh64x8 x (Const8 [c])) + // result: (Rsh64x64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh64x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -29849,23 +32150,43 @@ func rewriteValuegeneric_OpRsh64x8(v *Value) bool { v.AuxInt = int64ToAuxInt(0) return true } + // match: (Rsh64x8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 64 + // result: (Rsh64x8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 64) { + break + } + v.reset(OpRsh64x8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh8Ux16 x (Const16 [c])) - // result: (Rsh8Ux64 x (Const64 [int64(uint16(c))])) + // match: (Rsh8Ux16 x (Const16 [c])) + // result: (Rsh8Ux64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh8Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -29880,23 +32201,43 @@ func rewriteValuegeneric_OpRsh8Ux16(v *Value) bool { v.AuxInt = int8ToAuxInt(0) return true } + // match: (Rsh8Ux16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 8 + // result: (Rsh8Ux16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpRsh8Ux16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh8Ux32 x (Const32 [c])) - // result: (Rsh8Ux64 x (Const64 [int64(uint32(c))])) + // match: (Rsh8Ux32 x (Const32 [c])) + // result: (Rsh8Ux64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh8Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -29911,6 +32252,27 @@ func rewriteValuegeneric_OpRsh8Ux32(v *Value) bool { v.AuxInt = int8ToAuxInt(0) return true } + // match: (Rsh8Ux32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 8 + // result: (Rsh8Ux32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpRsh8Ux32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh8Ux64(v *Value) bool { @@ -30077,23 +32439,43 @@ func rewriteValuegeneric_OpRsh8Ux64(v *Value) bool { v.AddArg2(x, v0) return true } + // match: (Rsh8Ux64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 8 + // result: (Rsh8Ux64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpRsh8Ux64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh8Ux8 x (Const8 [c])) - // result: (Rsh8Ux64 x (Const64 [int64(uint8(c))])) + // match: (Rsh8Ux8 x (Const8 [c])) + // result: (Rsh8Ux64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh8Ux64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -30108,23 +32490,43 @@ func rewriteValuegeneric_OpRsh8Ux8(v *Value) bool { v.AuxInt = int8ToAuxInt(0) return true } + // match: (Rsh8Ux8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 8 + // result: (Rsh8Ux8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpRsh8Ux8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh8x16 x (Const16 [c])) - // result: (Rsh8x64 x (Const64 [int64(uint16(c))])) + // match: (Rsh8x16 x (Const16 [c])) + // result: (Rsh8x64 x (Const64 [int64(uint16(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh8x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true @@ -30139,23 +32541,43 @@ func rewriteValuegeneric_OpRsh8x16(v *Value) bool { v.AuxInt = int8ToAuxInt(0) return true } + // match: (Rsh8x16 [false] x con:(Const16 [c])) + // cond: 0 < c && c < 8 + // result: (Rsh8x16 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst16 { + break + } + c := auxIntToInt16(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpRsh8x16) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh8x32 x (Const32 [c])) - // result: (Rsh8x64 x (Const64 [int64(uint32(c))])) + // match: (Rsh8x32 x (Const32 [c])) + // result: (Rsh8x64 x (Const64 [int64(uint32(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh8x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true @@ -30170,6 +32592,27 @@ func rewriteValuegeneric_OpRsh8x32(v *Value) bool { v.AuxInt = int8ToAuxInt(0) return true } + // match: (Rsh8x32 [false] x con:(Const32 [c])) + // cond: 0 < c && c < 8 + // result: (Rsh8x32 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst32 { + break + } + c := auxIntToInt32(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpRsh8x32) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh8x64(v *Value) bool { @@ -30239,23 +32682,43 @@ func rewriteValuegeneric_OpRsh8x64(v *Value) bool { v.AddArg2(x, v0) return true } + // match: (Rsh8x64 [false] x con:(Const64 [c])) + // cond: 0 < c && c < 8 + // result: (Rsh8x64 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst64 { + break + } + c := auxIntToInt64(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpRsh8x64) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Rsh8x8 x (Const8 [c])) - // result: (Rsh8x64 x (Const64 [int64(uint8(c))])) + // match: (Rsh8x8 x (Const8 [c])) + // result: (Rsh8x64 x (Const64 [int64(uint8(c))])) for { - t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh8x64) - v0 := b.NewValue0(v.Pos, OpConst64, t) + v0 := b.NewValue0(v.Pos, OpConst64, types.Types[types.TUINT64]) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true @@ -30270,10 +32733,50 @@ func rewriteValuegeneric_OpRsh8x8(v *Value) bool { v.AuxInt = int8ToAuxInt(0) return true } + // match: (Rsh8x8 [false] x con:(Const8 [c])) + // cond: 0 < c && c < 8 + // result: (Rsh8x8 [true] x con) + for { + if auxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + con := v_1 + if con.Op != OpConst8 { + break + } + c := auxIntToInt8(con.AuxInt) + if !(0 < c && c < 8) { + break + } + v.reset(OpRsh8x8) + v.AuxInt = boolToAuxInt(true) + v.AddArg2(x, con) + return true + } return false } func rewriteValuegeneric_OpSelect0(v *Value) bool { v_0 := v.Args[0] + // match: (Select0 a:(Add64carry x y (Const64 [0]))) + // cond: a.Uses == 1 + // result: (Add64 x y) + for { + a := v_0 + if a.Op != OpAdd64carry { + break + } + _ = a.Args[2] + x := a.Args[0] + y := a.Args[1] + a_2 := a.Args[2] + if a_2.Op != OpConst64 || auxIntToInt64(a_2.AuxInt) != 0 || !(a.Uses == 1) { + break + } + v.reset(OpAdd64) + v.AddArg2(x, y) + return true + } // match: (Select0 (MakeTuple x y)) // result: x for { @@ -30613,7 +33116,7 @@ func rewriteValuegeneric_OpSelectN(v *Value) bool { return true } // match: (SelectN [1] (StaticCall {sym} _ newLen:(Const64) _ _ _ _)) - // cond: v.Type.IsInteger() && isSameCall(sym, "runtime.growslice") + // cond: v.Type.IsInteger() && (isSameCall(sym, "runtime.growslice") || isSameCall(sym, "runtime.growsliceNoAlias")) // result: newLen for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStaticCall || len(v_0.Args) != 6 { @@ -30622,14 +33125,14 @@ func rewriteValuegeneric_OpSelectN(v *Value) bool { sym := auxToCall(v_0.Aux) _ = v_0.Args[1] newLen := v_0.Args[1] - if newLen.Op != OpConst64 || !(v.Type.IsInteger() && isSameCall(sym, "runtime.growslice")) { + if newLen.Op != OpConst64 || !(v.Type.IsInteger() && (isSameCall(sym, "runtime.growslice") || isSameCall(sym, "runtime.growsliceNoAlias"))) { break } v.copyOf(newLen) return true } // match: (SelectN [1] (StaticCall {sym} _ newLen:(Const32) _ _ _ _)) - // cond: v.Type.IsInteger() && isSameCall(sym, "runtime.growslice") + // cond: v.Type.IsInteger() && (isSameCall(sym, "runtime.growslice") || isSameCall(sym, "runtime.growsliceNoAlias")) // result: newLen for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStaticCall || len(v_0.Args) != 6 { @@ -30638,7 +33141,7 @@ func rewriteValuegeneric_OpSelectN(v *Value) bool { sym := auxToCall(v_0.Aux) _ = v_0.Args[1] newLen := v_0.Args[1] - if newLen.Op != OpConst32 || !(v.Type.IsInteger() && isSameCall(sym, "runtime.growslice")) { + if newLen.Op != OpConst32 || !(v.Type.IsInteger() && (isSameCall(sym, "runtime.growslice") || isSameCall(sym, "runtime.growsliceNoAlias"))) { break } v.copyOf(newLen) @@ -30845,6 +33348,17 @@ func rewriteValuegeneric_OpSignExt8to16(v *Value) bool { v.copyOf(x) return true } + // match: (SignExt8to16 cvt:(CvtBoolToUint8 bool)) + // result: (ZeroExt8to16 cvt) + for { + cvt := v_0 + if cvt.Op != OpCvtBoolToUint8 { + break + } + v.reset(OpZeroExt8to16) + v.AddArg(cvt) + return true + } return false } func rewriteValuegeneric_OpSignExt8to32(v *Value) bool { @@ -30883,6 +33397,17 @@ func rewriteValuegeneric_OpSignExt8to32(v *Value) bool { v.copyOf(x) return true } + // match: (SignExt8to32 cvt:(CvtBoolToUint8 bool)) + // result: (ZeroExt8to32 cvt) + for { + cvt := v_0 + if cvt.Op != OpCvtBoolToUint8 { + break + } + v.reset(OpZeroExt8to32) + v.AddArg(cvt) + return true + } return false } func rewriteValuegeneric_OpSignExt8to64(v *Value) bool { @@ -30921,6 +33446,17 @@ func rewriteValuegeneric_OpSignExt8to64(v *Value) bool { v.copyOf(x) return true } + // match: (SignExt8to64 cvt:(CvtBoolToUint8 bool)) + // result: (ZeroExt8to64 cvt) + for { + cvt := v_0 + if cvt.Op != OpCvtBoolToUint8 { + break + } + v.reset(OpZeroExt8to64) + v.AddArg(cvt) + return true + } return false } func rewriteValuegeneric_OpSliceCap(v *Value) bool { @@ -30993,6 +33529,29 @@ func rewriteValuegeneric_OpSliceCap(v *Value) bool { v.AddArg(x) return true } + // match: (SliceCap (Phi (SliceMake _ _ x) (SliceMake _ _ x))) + // result: x + for { + if v_0.Op != OpPhi || len(v_0.Args) != 2 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSliceMake { + break + } + x := v_0_0.Args[2] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSliceMake { + break + } + _ = v_0_1.Args[2] + if x != v_0_1.Args[2] { + break + } + v.copyOf(x) + return true + } return false } func rewriteValuegeneric_OpSliceLen(v *Value) bool { @@ -31049,8 +33608,31 @@ func rewriteValuegeneric_OpSliceLen(v *Value) bool { v.AddArg(x) return true } + // match: (SliceLen (Phi (SliceMake _ x _) (SliceMake _ x _))) + // result: x + for { + if v_0.Op != OpPhi || len(v_0.Args) != 2 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSliceMake { + break + } + x := v_0_0.Args[1] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSliceMake { + break + } + _ = v_0_1.Args[1] + if x != v_0_1.Args[1] { + break + } + v.copyOf(x) + return true + } // match: (SliceLen (SelectN [0] (StaticLECall {sym} _ newLen:(Const64) _ _ _ _))) - // cond: isSameCall(sym, "runtime.growslice") + // cond: (isSameCall(sym, "runtime.growslice") || isSameCall(sym, "runtime.growsliceNoAlias")) // result: newLen for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { @@ -31063,14 +33645,14 @@ func rewriteValuegeneric_OpSliceLen(v *Value) bool { sym := auxToCall(v_0_0.Aux) _ = v_0_0.Args[1] newLen := v_0_0.Args[1] - if newLen.Op != OpConst64 || !(isSameCall(sym, "runtime.growslice")) { + if newLen.Op != OpConst64 || !(isSameCall(sym, "runtime.growslice") || isSameCall(sym, "runtime.growsliceNoAlias")) { break } v.copyOf(newLen) return true } // match: (SliceLen (SelectN [0] (StaticLECall {sym} _ newLen:(Const32) _ _ _ _))) - // cond: isSameCall(sym, "runtime.growslice") + // cond: (isSameCall(sym, "runtime.growslice") || isSameCall(sym, "runtime.growsliceNoAlias")) // result: newLen for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { @@ -31083,7 +33665,7 @@ func rewriteValuegeneric_OpSliceLen(v *Value) bool { sym := auxToCall(v_0_0.Aux) _ = v_0_0.Args[1] newLen := v_0_0.Args[1] - if newLen.Op != OpConst32 || !(isSameCall(sym, "runtime.growslice")) { + if newLen.Op != OpConst32 || !(isSameCall(sym, "runtime.growslice") || isSameCall(sym, "runtime.growsliceNoAlias")) { break } v.copyOf(newLen) @@ -32035,7 +34617,7 @@ func rewriteValuegeneric_OpStaticLECall(v *Value) bool { return true } // match: (StaticLECall {f} typ_ x y mem) - // cond: isSameCall(f, "runtime.efaceeq") && isDirectType(typ_) && clobber(v) + // cond: isSameCall(f, "runtime.efaceeq") && isDirectAndComparableType(typ_) && clobber(v) // result: (MakeResult (EqPtr x y) mem) for { if len(v.Args) != 4 { @@ -32046,7 +34628,7 @@ func rewriteValuegeneric_OpStaticLECall(v *Value) bool { typ_ := v.Args[0] x := v.Args[1] y := v.Args[2] - if !(isSameCall(f, "runtime.efaceeq") && isDirectType(typ_) && clobber(v)) { + if !(isSameCall(f, "runtime.efaceeq") && isDirectAndComparableType(typ_) && clobber(v)) { break } v.reset(OpMakeResult) @@ -32056,7 +34638,7 @@ func rewriteValuegeneric_OpStaticLECall(v *Value) bool { return true } // match: (StaticLECall {f} itab x y mem) - // cond: isSameCall(f, "runtime.ifaceeq") && isDirectIface(itab) && clobber(v) + // cond: isSameCall(f, "runtime.ifaceeq") && isDirectAndComparableIface(itab) && clobber(v) // result: (MakeResult (EqPtr x y) mem) for { if len(v.Args) != 4 { @@ -32067,7 +34649,7 @@ func rewriteValuegeneric_OpStaticLECall(v *Value) bool { itab := v.Args[0] x := v.Args[1] y := v.Args[2] - if !(isSameCall(f, "runtime.ifaceeq") && isDirectIface(itab) && clobber(v)) { + if !(isSameCall(f, "runtime.ifaceeq") && isDirectAndComparableIface(itab) && clobber(v)) { break } v.reset(OpMakeResult) @@ -32461,16 +35043,6 @@ func rewriteValuegeneric_OpStore(v *Value) bool { v.AddArg3(dst, src, v0) return true } - // match: (Store _ (ArrayMake0) mem) - // result: mem - for { - if v_1.Op != OpArrayMake0 { - break - } - mem := v_2 - v.copyOf(mem) - return true - } // match: (Store dst (ArrayMake1 e) mem) // result: (Store {e.Type} dst e mem) for { @@ -32485,6 +35057,16 @@ func rewriteValuegeneric_OpStore(v *Value) bool { v.AddArg3(dst, e, mem) return true } + // match: (Store _ (Empty) mem) + // result: mem + for { + if v_1.Op != OpEmpty { + break + } + mem := v_2 + v.copyOf(mem) + return true + } // match: (Store (SelectN [0] call:(StaticLECall ___)) x mem:(SelectN [1] call)) // cond: isConstZero(x) && isMalloc(call.Aux) // result: mem @@ -32960,17 +35542,34 @@ func rewriteValuegeneric_OpStructSelect(v *Value) bool { v0.AddArg2(v1, mem) return true } - // match: (StructSelect [0] (IData x)) + // match: (StructSelect (IData x)) + // cond: v.Type.Size() > 0 // result: (IData x) for { - if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpIData { + if v_0.Op != OpIData { break } x := v_0.Args[0] + if !(v.Type.Size() > 0) { + break + } v.reset(OpIData) v.AddArg(x) return true } + // match: (StructSelect (IData x)) + // cond: v.Type.Size() == 0 + // result: (Empty) + for { + if v_0.Op != OpIData { + break + } + if !(v.Type.Size() == 0) { + break + } + v.reset(OpEmpty) + return true + } return false } func rewriteValuegeneric_OpSub16(v *Value) bool { diff --git a/src/cmd/compile/internal/ssa/rewritetern.go b/src/cmd/compile/internal/ssa/rewritetern.go new file mode 100644 index 00000000000000..766b3f898c0765 --- /dev/null +++ b/src/cmd/compile/internal/ssa/rewritetern.go @@ -0,0 +1,294 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "internal/goarch" + "slices" +) + +var truthTableValues [3]uint8 = [3]uint8{0b1111_0000, 0b1100_1100, 0b1010_1010} + +func (slop SIMDLogicalOP) String() string { + if slop == sloInterior { + return "leaf" + } + interior := "" + if slop&sloInterior != 0 { + interior = "+interior" + } + switch slop &^ sloInterior { + case sloAnd: + return "and" + interior + case sloXor: + return "xor" + interior + case sloOr: + return "or" + interior + case sloAndNot: + return "andNot" + interior + case sloNot: + return "not" + interior + } + return "wrong" +} + +func rewriteTern(f *Func) { + if f.maxCPUFeatures == CPUNone { + return + } + + arch := f.Config.Ctxt().Arch.Family + // TODO there are other SIMD architectures + if arch != goarch.AMD64 { + return + } + + boolExprTrees := make(map[*Value]SIMDLogicalOP) + + // Find logical-expr expression trees, including leaves. + // interior nodes will be marked sloInterior, + // root nodes will not be marked sloInterior, + // leaf nodes are only marked sloInterior. + for _, b := range f.Blocks { + for _, v := range b.Values { + slo := classifyBooleanSIMD(v) + switch slo { + case sloOr, + sloAndNot, + sloXor, + sloAnd: + boolExprTrees[v.Args[1]] |= sloInterior + fallthrough + case sloNot: + boolExprTrees[v.Args[0]] |= sloInterior + boolExprTrees[v] |= slo + } + } + } + + // get a canonical sorted set of roots + var roots []*Value + for v, slo := range boolExprTrees { + if f.pass.debug > 1 { + f.Warnl(v.Pos, "%s has SLO %v", v.LongString(), slo) + } + + if slo&sloInterior == 0 && v.Block.CPUfeatures.hasFeature(CPUavx512) { + roots = append(roots, v) + } + } + slices.SortFunc(roots, func(u, v *Value) int { return int(u.ID - v.ID) }) // IDs are small enough to not care about overflow. + + // This rewrite works by iterating over the root set. + // For each boolean expression, it walks the expression + // bottom up accumulating sets of variables mentioned in + // subexpressions, lazy-greedily finding the largest subexpressions + // of 3 inputs that can be rewritten to use ternary-truth-table instructions. + + // rewrite recursively attempts to replace v and v's subexpressions with + // ternary-logic truth-table operations, returning a set of not more than 3 + // subexpressions within v that may be combined into a parent's replacement. + // V need not have the CPU features that allow a ternary-logic operation; + // in that case, v will not be rewritten. Replacements also require + // exactly 3 different variable inputs to a boolean expression. + // + // Given the CPU feature and 3 inputs, v is replaced in the following + // cases: + // + // 1) v is a root + // 2) u = NOT(v) and u lacks the CPU feature + // 3) u = OP(v, w) and u lacks the CPU feature + // 4) u = OP(v, w) and u has more than 3 variable inputs. var rewrite func(v *Value) [3]*Value + var rewrite func(v *Value) [3]*Value + + // computeTT returns the truth table for a boolean expression + // over the variables in vars, where vars[0] varies slowest in + // the truth table and vars[2] varies fastest. + // e.g. computeTT( "and(x, or(y, not(z)))", {x,y,z} ) returns + // (bit 0 first) 0 0 0 0 1 0 1 1 = (reversed) 1101_0000 = 0xD0 + // x: 0 0 0 0 1 1 1 1 + // y: 0 0 1 1 0 0 1 1 + // z: 0 1 0 1 0 1 0 1 + var computeTT func(v *Value, vars [3]*Value) uint8 + + // combine two sets of variables into one, returning ok/not + // if the two sets contained 3 or fewer elements. Combine + // ensures that the sets of Values never contain duplicates. + // (Duplicates would create less-efficient code, not incorrect code.) + combine := func(a, b [3]*Value) ([3]*Value, bool) { + var c [3]*Value + i := 0 + for _, v := range a { + if v == nil { + break + } + c[i] = v + i++ + } + bloop: + for _, v := range b { + if v == nil { + break + } + for _, u := range a { + if v == u { + continue bloop + } + } + if i == 3 { + return [3]*Value{}, false + } + c[i] = v + i++ + } + return c, true + } + + computeTT = func(v *Value, vars [3]*Value) uint8 { + i := 0 + for ; i < len(vars); i++ { + if vars[i] == v { + return truthTableValues[i] + } + } + slo := boolExprTrees[v] &^ sloInterior + a := computeTT(v.Args[0], vars) + switch slo { + case sloNot: + return ^a + case sloAnd: + return a & computeTT(v.Args[1], vars) + case sloXor: + return a ^ computeTT(v.Args[1], vars) + case sloOr: + return a | computeTT(v.Args[1], vars) + case sloAndNot: + return a & ^computeTT(v.Args[1], vars) + } + panic("switch should have covered all cases, or unknown var in logical expression") + } + + replace := func(a0 *Value, vars0 [3]*Value) { + imm := computeTT(a0, vars0) + op := ternOpForLogical(a0.Op) + if op == a0.Op { + if f.pass.debug > 0 { + f.Warnl(a0.Pos, "Skipping rewrite for %s, op=%v", a0.LongString(), op) + } + return + } + if f.pass.debug > 0 { + f.Warnl(a0.Pos, "Rewriting %s into %v of 0b%b %v %v %v", a0.LongString(), op, imm, + vars0[0], vars0[1], vars0[2]) + } + a0.reset(op) + a0.SetArgs3(vars0[0], vars0[1], vars0[2]) + a0.AuxInt = int64(int8(imm)) + } + + // addOne ensures the no-duplicates addition of a single value + // to a set that is not full. It seems possible that a shared + // subexpression in tricky combination with blocks lacking the + // AVX512 feature might permit this. + addOne := func(vars [3]*Value, v *Value) [3]*Value { + if vars[2] != nil { + panic("rewriteTern.addOne, vars[2] should be nil") + } + if v == vars[0] || v == vars[1] { + return vars + } + if vars[1] == nil { + vars[1] = v + } else { + vars[2] = v + } + return vars + } + + rewrite = func(v *Value) [3]*Value { + slo := boolExprTrees[v] + if slo == sloInterior { // leaf node, i.e., a "variable" + return [3]*Value{v, nil, nil} + } + var vars [3]*Value + hasFeature := v.Block.CPUfeatures.hasFeature(CPUavx512) + if slo&sloNot == sloNot { + vars = rewrite(v.Args[0]) + if !hasFeature { + if vars[2] != nil { + replace(v.Args[0], vars) + return [3]*Value{v, nil, nil} + } + return vars + } + } else { + var ok bool + a0, a1 := v.Args[0], v.Args[1] + vars0 := rewrite(a0) + vars1 := rewrite(a1) + vars, ok = combine(vars0, vars1) + + if f.pass.debug > 1 { + f.Warnl(a0.Pos, "combine(%v, %v) -> %v, %v", vars0, vars1, vars, ok) + } + + if !(ok && v.Block.CPUfeatures.hasFeature(CPUavx512)) { + // too many variables, or cannot rewrite current values. + // rewrite one or both subtrees if possible + if vars0[2] != nil && a0.Block.CPUfeatures.hasFeature(CPUavx512) { + replace(a0, vars0) + } + if vars1[2] != nil && a1.Block.CPUfeatures.hasFeature(CPUavx512) { + replace(a1, vars1) + } + + // 3-element var arrays are either rewritten, or unable to be rewritten + // because of the features in effect in their block. Either way, they + // are treated as a "new var" if 3 elements are present. + + if vars0[2] == nil { + if vars1[2] == nil { + // both subtrees are 2-element and were not rewritten. + // + // TODO a clever person would look at subtrees of inputs, + // e.g. rewrite + // ((a AND b) XOR b) XOR (d XOR (c AND d)) + // to (((a AND b) XOR b) XOR d) XOR (c AND d) + // to v = TERNLOG(truthtable, a, b, d) XOR (c AND d) + // and return the variable set {v, c, d} + // + // But for now, just restart with a0 and a1. + return [3]*Value{a0, a1, nil} + } else { + // a1 (maybe) rewrote, a0 has room for another var + vars = addOne(vars0, a1) + } + } else if vars1[2] == nil { + // a0 (maybe) rewrote, a1 has room for another var + vars = addOne(vars1, a0) + } else if !ok { + // both (maybe) rewrote + // a0 and a1 are different because otherwise their variable + // sets would have combined "ok". + return [3]*Value{a0, a1, nil} + } + // continue with either the vars from "ok" or the updated set of vars. + } + } + // if root and 3 vars and hasFeature, rewrite. + if slo&sloInterior == 0 && vars[2] != nil && hasFeature { + replace(v, vars) + return [3]*Value{v, nil, nil} + } + return vars + } + + for _, v := range roots { + if f.pass.debug > 1 { + f.Warnl(v.Pos, "SLO root %s", v.LongString()) + } + rewrite(v) + } +} diff --git a/src/cmd/compile/internal/ssa/sccp.go b/src/cmd/compile/internal/ssa/sccp.go index 107db23ed4af08..3793e9f86a5be9 100644 --- a/src/cmd/compile/internal/ssa/sccp.go +++ b/src/cmd/compile/internal/ssa/sccp.go @@ -4,10 +4,6 @@ package ssa -import ( - "fmt" -) - // ---------------------------------------------------------------------------- // Sparse Conditional Constant Propagation // @@ -54,6 +50,7 @@ type lattice struct { type worklist struct { f *Func // the target function to be optimized out edges []Edge // propagate constant facts through edges + inUses *sparseSet // IDs already in uses, for duplicate check uses []*Value // re-visiting set visited map[Edge]bool // visited edges latticeCells map[*Value]lattice // constant lattices @@ -75,6 +72,8 @@ func sccp(f *Func) { t.defBlock = make(map[*Value][]*Block) t.latticeCells = make(map[*Value]lattice) t.visitedBlock = f.Cache.allocBoolSlice(f.NumBlocks()) + t.inUses = f.newSparseSet(f.NumValues()) + defer f.retSparseSet(t.inUses) defer f.Cache.freeBoolSlice(t.visitedBlock) // build it early since we rely heavily on the def-use chain later @@ -108,6 +107,7 @@ func sccp(f *Func) { if len(t.uses) > 0 { use := t.uses[0] t.uses = t.uses[1:] + t.inUses.remove(use.ID) t.visitValue(use) continue } @@ -118,7 +118,7 @@ func sccp(f *Func) { constCnt, rewireCnt := t.replaceConst() if f.pass.debug > 0 { if constCnt > 0 || rewireCnt > 0 { - fmt.Printf("Phase SCCP for %v : %v constants, %v dce\n", f.Name, constCnt, rewireCnt) + f.Warnl(f.Entry.Pos, "Phase SCCP for %v : %v constants, %v dce", f.Name, constCnt, rewireCnt) } } } @@ -255,6 +255,10 @@ func (t *worklist) buildDefUses() { for _, arg := range val.Args { // find its uses, only uses that can become constants take into account if possibleConst(arg) && possibleConst(val) { + // Phi may refer to itself as uses, avoid duplicate visits + if arg == val { + continue + } if _, exist := t.defUse[arg]; !exist { t.defUse[arg] = make([]*Value, 0, arg.Uses) } @@ -274,12 +278,16 @@ func (t *worklist) buildDefUses() { // addUses finds all uses of value and appends them into work list for further process func (t *worklist) addUses(val *Value) { for _, use := range t.defUse[val] { - if val == use { - // Phi may refer to itself as uses, ignore them to avoid re-visiting phi - // for performance reason + // Provenly not a constant, ignore + useLt := t.getLatticeCell(use) + if useLt.tag == bottom { continue } - t.uses = append(t.uses, use) + // Avoid duplicate visits + if !t.inUses.contains(use.ID) { + t.inUses.add(use.ID) + t.uses = append(t.uses, use) + } } for _, block := range t.defBlock[val] { if t.visitedBlock[block.ID] { @@ -366,15 +374,19 @@ func computeLattice(f *Func, val *Value, args ...*Value) lattice { } func (t *worklist) visitValue(val *Value) { + // Impossible to be a constant, fast fail if !possibleConst(val) { - // fast fail for always worst Values, i.e. there is no lowering happen - // on them, their lattices must be initially worse Bottom. return } + // Provenly not a constant, fast fail oldLt := t.getLatticeCell(val) + if oldLt.tag == bottom { + return + } + + // Re-visit all uses of value if its lattice is changed defer func() { - // re-visit all uses of value if its lattice is changed newLt := t.getLatticeCell(val) if !equals(newLt, oldLt) { if oldLt.tag > newLt.tag { @@ -511,6 +523,10 @@ func (t *worklist) propagate(block *Block) { branchIdx = 1 - condLattice.val.AuxInt } else { branchIdx = condLattice.val.AuxInt + if branchIdx < 0 || branchIdx >= int64(len(block.Succs)) { + // unreachable code, do nothing then + break + } } t.edges = append(t.edges, block.Succs[branchIdx]) } else { @@ -563,7 +579,7 @@ func (t *worklist) replaceConst() (int, int) { if lt.tag == constant { if !isConst(val) { if t.f.pass.debug > 0 { - fmt.Printf("Replace %v with %v\n", val.LongString(), lt.val.LongString()) + t.f.Warnl(val.Pos, "Replace %v with %v", val.LongString(), lt.val.LongString()) } val.reset(lt.val.Op) val.AuxInt = lt.val.AuxInt @@ -575,7 +591,7 @@ func (t *worklist) replaceConst() (int, int) { if rewireSuccessor(block, lt.val) { rewireCnt++ if t.f.pass.debug > 0 { - fmt.Printf("Rewire %v %v successors\n", block.Kind, block) + t.f.Warnl(block.Pos, "Rewire %v %v successors", block.Kind, block) } } } diff --git a/src/cmd/compile/internal/ssa/schedule.go b/src/cmd/compile/internal/ssa/schedule.go index 325118a1827b04..9f64c065a78f8f 100644 --- a/src/cmd/compile/internal/ssa/schedule.go +++ b/src/cmd/compile/internal/ssa/schedule.go @@ -22,8 +22,8 @@ const ( ScoreMemory ScoreReadFlags ScoreDefault - ScoreInductionInc // an increment of an induction variable ScoreFlags + ScoreInductionInc // an increment of an induction variable ScoreControl // towards bottom of block ) @@ -36,13 +36,13 @@ type ValHeap struct { func (h ValHeap) Len() int { return len(h.a) } func (h ValHeap) Swap(i, j int) { a := h.a; a[i], a[j] = a[j], a[i] } -func (h *ValHeap) Push(x interface{}) { +func (h *ValHeap) Push(x any) { // Push and Pop use pointer receivers because they modify the slice's length, // not just its contents. v := x.(*Value) h.a = append(h.a, v) } -func (h *ValHeap) Pop() interface{} { +func (h *ValHeap) Pop() any { old := h.a n := len(old) x := old[n-1] diff --git a/src/cmd/compile/internal/ssa/sizeof_test.go b/src/cmd/compile/internal/ssa/sizeof_test.go index a27002ee3ac3b2..9533a560f42742 100644 --- a/src/cmd/compile/internal/ssa/sizeof_test.go +++ b/src/cmd/compile/internal/ssa/sizeof_test.go @@ -16,14 +16,14 @@ func TestSizeof(t *testing.T) { const _64bit = unsafe.Sizeof(uintptr(0)) == 8 var tests = []struct { - val interface{} // type as a value - _32bit uintptr // size on 32bit platforms - _64bit uintptr // size on 64bit platforms + val any // type as a value + _32bit uintptr // size on 32bit platforms + _64bit uintptr // size on 64bit platforms }{ {Value{}, 72, 112}, - {Block{}, 164, 304}, + {Block{}, 168, 312}, {LocalSlot{}, 28, 40}, - {valState{}, 28, 40}, + {valState{}, 36, 48}, } for _, tt := range tests { diff --git a/src/cmd/compile/internal/ssa/softfloat.go b/src/cmd/compile/internal/ssa/softfloat.go index 351f824a9f579a..cd6df5fe8b0361 100644 --- a/src/cmd/compile/internal/ssa/softfloat.go +++ b/src/cmd/compile/internal/ssa/softfloat.go @@ -73,7 +73,7 @@ func softfloat(f *Func) { if newInt64 && f.Config.RegSize == 4 { // On 32bit arch, decompose Uint64 introduced in the switch above. - decomposeBuiltIn(f) + decomposeBuiltin(f) applyRewrite(f, rewriteBlockdec64, rewriteValuedec64, removeDeadValues) } diff --git a/src/cmd/compile/internal/ssa/sparsetree.go b/src/cmd/compile/internal/ssa/sparsetree.go index 6f2bd040375a83..1e0f4601346a35 100644 --- a/src/cmd/compile/internal/ssa/sparsetree.go +++ b/src/cmd/compile/internal/ssa/sparsetree.go @@ -56,27 +56,13 @@ const ( type SparseTree []SparseTreeNode // newSparseTree creates a SparseTree from a block-to-parent map (array indexed by Block.ID). +// The children of a given node are in reverse postorder. +// This has the nice property that for a given tree walk, the source block of all +// non-retreating edges are visited before their destination block. func newSparseTree(f *Func, parentOf []*Block) SparseTree { + po := f.postorder() t := make(SparseTree, f.NumBlocks()) - for _, b := range f.Blocks { - n := &t[b.ID] - if p := parentOf[b.ID]; p != nil { - n.parent = p - n.sibling = t[p.ID].child - t[p.ID].child = b - } - } - t.numberBlock(f.Entry, 1) - return t -} - -// newSparseOrderedTree creates a SparseTree from a block-to-parent map (array indexed by Block.ID) -// children will appear in the reverse of their order in reverseOrder -// in particular, if reverseOrder is a dfs-reversePostOrder, then the root-to-children -// walk of the tree will yield a pre-order. -func newSparseOrderedTree(f *Func, parentOf, reverseOrder []*Block) SparseTree { - t := make(SparseTree, f.NumBlocks()) - for _, b := range reverseOrder { + for _, b := range po { n := &t[b.ID] if p := parentOf[b.ID]; p != nil { n.parent = p diff --git a/src/cmd/compile/internal/ssa/stackalloc.go b/src/cmd/compile/internal/ssa/stackalloc.go index 11ffe5b55ea65f..06097e95da0bc1 100644 --- a/src/cmd/compile/internal/ssa/stackalloc.go +++ b/src/cmd/compile/internal/ssa/stackalloc.go @@ -56,10 +56,35 @@ func putStackAllocState(s *stackAllocState) { } type stackValState struct { - typ *types.Type - spill *Value - needSlot bool - isArg bool + typ *types.Type + spill *Value + needSlot bool + isArg bool + defBlock ID + useBlocks []stackUseBlock +} + +// addUseBlock adds a block to the set of blocks that uses this value. +// Note that we only loosely enforce the set property by checking the last +// block that was appended to the list and duplicates may occur. +// Because we add values block by block (barring phi-nodes), the number of duplicates is +// small and we deduplicate as part of the liveness algorithm later anyway. +func (sv *stackValState) addUseBlock(b *Block, liveout bool) { + entry := stackUseBlock{ + b: b, + liveout: liveout, + } + if sv.useBlocks == nil || sv.useBlocks[len(sv.useBlocks)-1] != entry { + sv.useBlocks = append(sv.useBlocks, stackUseBlock{ + b: b, + liveout: liveout, + }) + } +} + +type stackUseBlock struct { + b *Block + liveout bool } // stackalloc allocates storage in the stack frame for @@ -99,6 +124,7 @@ func (s *stackAllocState) init(f *Func, spillLive [][]ID) { s.values[v.ID].typ = v.Type s.values[v.ID].needSlot = !v.Type.IsMemory() && !v.Type.IsVoid() && !v.Type.IsFlags() && f.getHome(v.ID) == nil && !v.rematerializeable() && !v.OnWasmStack s.values[v.ID].isArg = hasAnyArgOp(v) + s.values[v.ID].defBlock = b.ID if f.pass.debug > stackDebug && s.values[v.ID].needSlot { fmt.Printf("%s needs a stack slot\n", v) } @@ -291,80 +317,89 @@ func (s *stackAllocState) stackalloc() { // computeLive computes a map from block ID to a list of // stack-slot-needing value IDs live at the end of that block. -// TODO: this could be quadratic if lots of variables are live across lots of -// basic blocks. Figure out a way to make this function (or, more precisely, the user -// of this function) require only linear size & time. func (s *stackAllocState) computeLive(spillLive [][]ID) { - s.live = make([][]ID, s.f.NumBlocks()) - var phis []*Value - live := s.f.newSparseSet(s.f.NumValues()) - defer s.f.retSparseSet(live) - t := s.f.newSparseSet(s.f.NumValues()) - defer s.f.retSparseSet(t) - - // Instead of iterating over f.Blocks, iterate over their postordering. - // Liveness information flows backward, so starting at the end - // increases the probability that we will stabilize quickly. - po := s.f.postorder() - for { - changed := false - for _, b := range po { - // Start with known live values at the end of the block - live.clear() - live.addAll(s.live[b.ID]) - - // Propagate backwards to the start of the block - phis = phis[:0] - for i := len(b.Values) - 1; i >= 0; i-- { - v := b.Values[i] - live.remove(v.ID) - if v.Op == OpPhi { - // Save phi for later. - // Note: its args might need a stack slot even though - // the phi itself doesn't. So don't use needSlot. - if !v.Type.IsMemory() && !v.Type.IsVoid() { - phis = append(phis, v) - } - continue - } - for _, a := range v.Args { - if s.values[a.ID].needSlot { - live.add(a.ID) - } - } - } - // for each predecessor of b, expand its list of live-at-end values - // invariant: s contains the values live at the start of b (excluding phi inputs) - for i, e := range b.Preds { - p := e.b - t.clear() - t.addAll(s.live[p.ID]) - t.addAll(live.contents()) - t.addAll(spillLive[p.ID]) - for _, v := range phis { - a := v.Args[i] - if s.values[a.ID].needSlot { - t.add(a.ID) - } - if spill := s.values[a.ID].spill; spill != nil { + // Because values using stack slots are few and far inbetween + // (compared to the set of all values), we use a path exploration + // algorithm to calculate liveness here. + f := s.f + for _, b := range f.Blocks { + for _, spillvid := range spillLive[b.ID] { + val := &s.values[spillvid] + val.addUseBlock(b, true) + } + for _, v := range b.Values { + for i, a := range v.Args { + val := &s.values[a.ID] + useBlock := b + forceLiveout := false + if v.Op == OpPhi { + useBlock = b.Preds[i].b + forceLiveout = true + if spill := val.spill; spill != nil { //TODO: remove? Subsumed by SpillUse? - t.add(spill.ID) + s.values[spill.ID].addUseBlock(useBlock, true) } } - if t.size() == len(s.live[p.ID]) { + if !val.needSlot { continue } - // grow p's live set - s.live[p.ID] = append(s.live[p.ID][:0], t.contents()...) - changed = true + val.addUseBlock(useBlock, forceLiveout) } } + } - if !changed { - break + s.live = make([][]ID, f.NumBlocks()) + push := func(bid, vid ID) { + l := s.live[bid] + if l == nil || l[len(l)-1] != vid { + l = append(l, vid) + s.live[bid] = l } } + // TODO: If we can help along the interference graph by calculating livein sets, + // we can do so trivially by turning this sparse set into an array of arrays + // and checking the top for the current value instead of inclusion in the sparse set. + seen := f.newSparseSet(f.NumBlocks()) + defer f.retSparseSet(seen) + // instead of pruning out duplicate blocks when we build the useblocks slices + // or when we add them to the queue, rely on the seen set to stop considering + // them. This is slightly faster than building the workqueues as sets + // + // However, this means that the queue can grow larger than the number of blocks, + // usually in very short functions. Returning a slice with values appended beyond the + // original allocation can corrupt the allocator state, so cap the queue and return + // the originally allocated slice regardless. + allocedBqueue := f.Cache.allocBlockSlice(f.NumBlocks()) + defer f.Cache.freeBlockSlice(allocedBqueue) + bqueue := allocedBqueue[:0:f.NumBlocks()] + + for vid, v := range s.values { + if !v.needSlot { + continue + } + seen.clear() + bqueue = bqueue[:0] + for _, b := range v.useBlocks { + if b.liveout { + push(b.b.ID, ID(vid)) + } + bqueue = append(bqueue, b.b) + } + for len(bqueue) > 0 { + work := bqueue[len(bqueue)-1] + bqueue = bqueue[:len(bqueue)-1] + if seen.contains(work.ID) || work.ID == v.defBlock { + continue + } + seen.add(work.ID) + for _, e := range work.Preds { + push(e.b.ID, ID(vid)) + bqueue = append(bqueue, e.b) + } + } + } + if s.f.pass.debug > stackDebug { for _, b := range s.f.Blocks { fmt.Printf("stacklive %s %v\n", b, s.live[b.ID]) diff --git a/src/cmd/compile/internal/ssa/stmtlines_test.go b/src/cmd/compile/internal/ssa/stmtlines_test.go index d0f09da86ffce2..acab3c9cb114d0 100644 --- a/src/cmd/compile/internal/ssa/stmtlines_test.go +++ b/src/cmd/compile/internal/ssa/stmtlines_test.go @@ -103,7 +103,8 @@ func TestStmtLines(t *testing.T) { if pkgname == "runtime" { continue } - if pkgname == "crypto/internal/fips140/nistec/fiat" { + if pkgname == "crypto/internal/fips140/nistec/fiat" || + pkgname == "crypto/internal/fips140/nistec" { continue // golang.org/issue/49372 } if e.Val(dwarf.AttrStmtList) == nil { @@ -138,11 +139,12 @@ func TestStmtLines(t *testing.T) { } var m float64 - if runtime.GOARCH == "amd64" { - m = 0.011 // > 98.9% obtained on amd64, no backsliding - } else if runtime.GOARCH == "riscv64" { + switch runtime.GOARCH { + case "amd64": + m = 0.015 // > 98.5% obtained on amd64, there has been minor backsliding + case "riscv64": m = 0.03 // XXX temporary update threshold to 97% for regabi - } else { + default: m = 0.02 // expect 98% elsewhere. } diff --git a/src/cmd/compile/internal/ssa/tern_helpers.go b/src/cmd/compile/internal/ssa/tern_helpers.go new file mode 100644 index 00000000000000..923a9f505e5fd3 --- /dev/null +++ b/src/cmd/compile/internal/ssa/tern_helpers.go @@ -0,0 +1,160 @@ +// Code generated by 'tmplgen'; DO NOT EDIT. + +package ssa + +type SIMDLogicalOP uint8 + +const ( + // boolean simd operations, for reducing expression to VPTERNLOG* instructions + // sloInterior is set for non-root nodes in logical-op expression trees. + // the operations are even-numbered. + sloInterior SIMDLogicalOP = 1 + sloNone SIMDLogicalOP = 2 * iota + sloAnd + sloOr + sloAndNot + sloXor + sloNot +) + +func classifyBooleanSIMD(v *Value) SIMDLogicalOP { + switch v.Op { + case OpAndInt8x16, OpAndInt16x8, OpAndInt32x4, OpAndInt64x2, OpAndInt8x32, OpAndInt16x16, OpAndInt32x8, OpAndInt64x4, OpAndInt8x64, OpAndInt16x32, OpAndInt32x16, OpAndInt64x8: + return sloAnd + + case OpOrInt8x16, OpOrInt16x8, OpOrInt32x4, OpOrInt64x2, OpOrInt8x32, OpOrInt16x16, OpOrInt32x8, OpOrInt64x4, OpOrInt8x64, OpOrInt16x32, OpOrInt32x16, OpOrInt64x8: + return sloOr + + case OpAndNotInt8x16, OpAndNotInt16x8, OpAndNotInt32x4, OpAndNotInt64x2, OpAndNotInt8x32, OpAndNotInt16x16, OpAndNotInt32x8, OpAndNotInt64x4, OpAndNotInt8x64, OpAndNotInt16x32, OpAndNotInt32x16, OpAndNotInt64x8: + return sloAndNot + case OpXorInt8x16: + if y := v.Args[1]; y.Op == OpEqualInt8x16 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt16x8: + if y := v.Args[1]; y.Op == OpEqualInt16x8 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt32x4: + if y := v.Args[1]; y.Op == OpEqualInt32x4 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt64x2: + if y := v.Args[1]; y.Op == OpEqualInt64x2 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt8x32: + if y := v.Args[1]; y.Op == OpEqualInt8x32 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt16x16: + if y := v.Args[1]; y.Op == OpEqualInt16x16 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt32x8: + if y := v.Args[1]; y.Op == OpEqualInt32x8 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt64x4: + if y := v.Args[1]; y.Op == OpEqualInt64x4 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt8x64: + if y := v.Args[1]; y.Op == OpEqualInt8x64 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt16x32: + if y := v.Args[1]; y.Op == OpEqualInt16x32 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt32x16: + if y := v.Args[1]; y.Op == OpEqualInt32x16 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + case OpXorInt64x8: + if y := v.Args[1]; y.Op == OpEqualInt64x8 && + y.Args[0] == y.Args[1] { + return sloNot + } + return sloXor + + } + return sloNone +} + +func ternOpForLogical(op Op) Op { + switch op { + case OpAndInt8x16, OpOrInt8x16, OpXorInt8x16, OpAndNotInt8x16: + return OpternInt32x4 + case OpAndUint8x16, OpOrUint8x16, OpXorUint8x16, OpAndNotUint8x16: + return OpternUint32x4 + case OpAndInt16x8, OpOrInt16x8, OpXorInt16x8, OpAndNotInt16x8: + return OpternInt32x4 + case OpAndUint16x8, OpOrUint16x8, OpXorUint16x8, OpAndNotUint16x8: + return OpternUint32x4 + case OpAndInt32x4, OpOrInt32x4, OpXorInt32x4, OpAndNotInt32x4: + return OpternInt32x4 + case OpAndUint32x4, OpOrUint32x4, OpXorUint32x4, OpAndNotUint32x4: + return OpternUint32x4 + case OpAndInt64x2, OpOrInt64x2, OpXorInt64x2, OpAndNotInt64x2: + return OpternInt64x2 + case OpAndUint64x2, OpOrUint64x2, OpXorUint64x2, OpAndNotUint64x2: + return OpternUint64x2 + case OpAndInt8x32, OpOrInt8x32, OpXorInt8x32, OpAndNotInt8x32: + return OpternInt32x8 + case OpAndUint8x32, OpOrUint8x32, OpXorUint8x32, OpAndNotUint8x32: + return OpternUint32x8 + case OpAndInt16x16, OpOrInt16x16, OpXorInt16x16, OpAndNotInt16x16: + return OpternInt32x8 + case OpAndUint16x16, OpOrUint16x16, OpXorUint16x16, OpAndNotUint16x16: + return OpternUint32x8 + case OpAndInt32x8, OpOrInt32x8, OpXorInt32x8, OpAndNotInt32x8: + return OpternInt32x8 + case OpAndUint32x8, OpOrUint32x8, OpXorUint32x8, OpAndNotUint32x8: + return OpternUint32x8 + case OpAndInt64x4, OpOrInt64x4, OpXorInt64x4, OpAndNotInt64x4: + return OpternInt64x4 + case OpAndUint64x4, OpOrUint64x4, OpXorUint64x4, OpAndNotUint64x4: + return OpternUint64x4 + case OpAndInt8x64, OpOrInt8x64, OpXorInt8x64, OpAndNotInt8x64: + return OpternInt32x16 + case OpAndUint8x64, OpOrUint8x64, OpXorUint8x64, OpAndNotUint8x64: + return OpternUint32x16 + case OpAndInt16x32, OpOrInt16x32, OpXorInt16x32, OpAndNotInt16x32: + return OpternInt32x16 + case OpAndUint16x32, OpOrUint16x32, OpXorUint16x32, OpAndNotUint16x32: + return OpternUint32x16 + case OpAndInt32x16, OpOrInt32x16, OpXorInt32x16, OpAndNotInt32x16: + return OpternInt32x16 + case OpAndUint32x16, OpOrUint32x16, OpXorUint32x16, OpAndNotUint32x16: + return OpternUint32x16 + case OpAndInt64x8, OpOrInt64x8, OpXorInt64x8, OpAndNotInt64x8: + return OpternInt64x8 + case OpAndUint64x8, OpOrUint64x8, OpXorUint64x8, OpAndNotUint64x8: + return OpternUint64x8 + + } + return op +} diff --git a/src/cmd/compile/internal/ssa/uses.go b/src/cmd/compile/internal/ssa/uses.go new file mode 100644 index 00000000000000..9dd4194d07ad36 --- /dev/null +++ b/src/cmd/compile/internal/ssa/uses.go @@ -0,0 +1,109 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// useInfo provides a map from a value to the users of that value. +// We do not keep track of this data in the IR directly, as it is +// expensive to keep updated. But sometimes we need to compute it +// temporarily. +// +// A useInfo is only valid until the next modification of the IR. +// +// Note that block control uses are not reported. (TODO: add +// if needed.) +// Also, index of use is not reported. (TODO: add if needed.) +// +// We keep track of all uses in a single array, and use a +// starts array to tell us where to find the sub-array for +// each value. +// +// For a function with 10 values, we would have: +// +// starts[0] starts[1] starts[2] starts[9] len(uses) +// | | | | | +// v v v v v +// +------------+------------+-...-+------------+ +// | uses of v0 | uses of v1 | ... | uses of v9 | +// +------------+------------+-...-+------------+ +// +// We can find all the uses of v by listing all entries +// of uses between starts[v.ID] and starts[v.ID+1]. +type useInfo struct { + starts []int32 + uses []*Value +} + +// build useInfo for a function. Result only valid until +// the next modification of f. +func uses(f *Func) useInfo { + // Write down number of uses of each value. + idx := f.Cache.allocInt32Slice(f.NumValues()) + for _, b := range f.Blocks { + for _, v := range b.Values { + idx[v.ID] = v.Uses + } + } + + // Compute cumulative sum of uses up to and + // including each value ID. + var cum int32 + for vid, uses := range idx { + cum += uses + idx[vid] = cum + } + + // Compute uses. + uses := f.Cache.allocValueSlice(int(cum)) + for _, b := range f.Blocks { + for _, v := range b.Values { + for _, a := range v.Args { + idx[a.ID]-- + uses[idx[a.ID]] = v + } + } + } + for _, b := range f.Blocks { + for _, c := range b.ControlValues() { + // We don't track block control uses, but + // we have to decrement idx values here + // so that the accounting comes out right. + // Each value will have, at the start of its + // use list, a bunch of nils that represent + // the number of Block.Control uses. + idx[c.ID]-- + } + } + + // The loop above decremented each idx entry + // by the number of uses. It now contains + // the sum of uses up to, but not including, + // each value ID. + return useInfo{starts: idx, uses: uses} +} + +// get returns a list of uses of v. +// Every use in an argument slot is listed (e.g. for +// w=(Add v v), w is listed twice in the uses of v). +// Uses by Block.Controls are not reported. +func (u useInfo) get(v *Value) []*Value { + i := u.starts[v.ID] + var j int32 + if int(v.ID) < len(u.starts)-1 { + j = u.starts[v.ID+1] + } else { + j = int32(len(u.uses)) + } + r := u.uses[i:j] + // skip nil entries from block control uses + for len(r) > 0 && r[0] == nil { + r = r[1:] + } + return r +} + +func (u useInfo) free(f *Func) { + f.Cache.freeInt32Slice(u.starts) + f.Cache.freeValueSlice(u.uses) +} diff --git a/src/cmd/compile/internal/ssa/value.go b/src/cmd/compile/internal/ssa/value.go index 51a70c7fd4fdcd..bd11e526fea6df 100644 --- a/src/cmd/compile/internal/ssa/value.go +++ b/src/cmd/compile/internal/ssa/value.go @@ -9,6 +9,7 @@ import ( "cmd/compile/internal/types" "cmd/internal/src" "fmt" + "internal/buildcfg" "math" "sort" "strings" @@ -151,6 +152,10 @@ func (v *Value) AuxArm64ConditionalParams() arm64ConditionalParams { return auxIntToArm64ConditionalParams(v.AuxInt) } +func (v *Value) AuxSizeAndAlign() (int64, int64) { + return v.AuxInt, int64(v.Aux.(int64Aux)) +} + // long form print. v# = opcode [aux] args [: reg] (names) func (v *Value) LongString() string { if v == nil { @@ -249,6 +254,8 @@ func (v *Value) auxString() string { return fmt.Sprintf(" {%v}", v.Aux) case auxFlagConstant: return fmt.Sprintf("[%s]", flagConstant(v.AuxInt)) + case auxSizeAndAlign: + return fmt.Sprintf(" [size=%d] {align=%d}", v.AuxInt, v.Aux) case auxNone: return "" default: @@ -471,9 +478,9 @@ func (v *Value) copyIntoWithXPos(b *Block, pos src.XPos) *Value { return c } -func (v *Value) Logf(msg string, args ...interface{}) { v.Block.Logf(msg, args...) } -func (v *Value) Log() bool { return v.Block.Log() } -func (v *Value) Fatalf(msg string, args ...interface{}) { +func (v *Value) Logf(msg string, args ...any) { v.Block.Logf(msg, args...) } +func (v *Value) Log() bool { return v.Block.Log() } +func (v *Value) Fatalf(msg string, args ...any) { v.Block.Func.fe.Fatalf(v.Pos, msg, args...) } @@ -612,11 +619,20 @@ func AutoVar(v *Value) (*ir.Name, int64) { // CanSSA reports whether values of type t can be represented as a Value. func CanSSA(t *types.Type) bool { types.CalcSize(t) - if t.Size() > int64(4*types.PtrSize) { + if t.IsSIMD() { + return true + } + if t.Size() == 0 { + return true + } + sizeLimit := int64(MaxStruct * types.PtrSize) + if t.Size() > sizeLimit { // 4*Widthptr is an arbitrary constant. We want it // to be at least 3*Widthptr so slices can be registerized. // Too big and we'll introduce too much register pressure. - return false + if !buildcfg.Experiment.SIMD { + return false + } } switch t.Kind() { case types.TARRAY: @@ -628,6 +644,10 @@ func CanSSA(t *types.Type) bool { } return false case types.TSTRUCT: + if types.IsDirectIface(t) { + // Note: even if t.NumFields()>MaxStruct! See issue 77534. + return true + } if t.NumFields() > MaxStruct { return false } @@ -636,8 +656,30 @@ func CanSSA(t *types.Type) bool { return false } } - return true + // Special check for SIMD. If the composite type + // contains SIMD vectors we can return true + // if it pass the checks below. + if !buildcfg.Experiment.SIMD { + return true + } + if t.Size() <= sizeLimit { + return true + } + i, f := t.Registers() + return i+f <= MaxStruct default: return true } } + +// AddrSinkArg reports whether the idx'th argument is known +// to not propagate to the output value. +func (v *Value) AddrSinkArg(idx int) bool { + if idx == 0 { + return opcodeTable[v.Op].addrSinkArg0 + } + if idx == 1 { + return opcodeTable[v.Op].addrSinkArg1 + } + return false +} diff --git a/src/cmd/compile/internal/ssagen/abi.go b/src/cmd/compile/internal/ssagen/abi.go index 3d50155cf36d10..ba1aba047a04cb 100644 --- a/src/cmd/compile/internal/ssagen/abi.go +++ b/src/cmd/compile/internal/ssagen/abi.go @@ -99,6 +99,18 @@ func (s *SymABIs) ReadSymABIs(file string) { } } +// HasDef returns whether the given symbol has an assembly definition. +func (s *SymABIs) HasDef(sym *types.Sym) bool { + symName := sym.Linkname + if symName == "" { + symName = sym.Pkg.Prefix + "." + sym.Name + } + symName = s.canonicalize(symName) + + _, hasDefABI := s.defs[symName] + return hasDefABI +} + // GenABIWrappers applies ABI information to Funcs and generates ABI // wrapper functions where necessary. func (s *SymABIs) GenABIWrappers() { @@ -156,6 +168,9 @@ func (s *SymABIs) GenABIWrappers() { if sym.Linksym().IsLinkname() { sym.LinksymABI(fn.ABI).Set(obj.AttrLinkname, true) } + if sym.Linksym().IsLinknameStd() { + sym.LinksymABI(fn.ABI).Set(obj.AttrLinknameStd, true) + } } // If cgo-exported, add the definition ABI to the cgo @@ -265,6 +280,10 @@ func makeABIWrapper(f *ir.Func, wrapperABI obj.ABI) { fn.SetABIWrapper(true) fn.SetDupok(true) + // Propagate linkname attribute. + fn.LinksymABI(fn.ABI).Set(obj.AttrLinkname, f.Linksym().IsLinkname()) + fn.LinksymABI(fn.ABI).Set(obj.AttrLinknameStd, f.Linksym().IsLinknameStd()) + // ABI0-to-ABIInternal wrappers will be mainly loading params from // stack into registers (and/or storing stack locations back to // registers after the wrapped call); in most cases they won't @@ -302,7 +321,7 @@ func makeABIWrapper(f *ir.Func, wrapperABI obj.ABI) { // extra work in typecheck/walk/ssa, might want to add a new node // OTAILCALL or something to this effect. tailcall := fn.Type().NumResults() == 0 && fn.Type().NumParams() == 0 && fn.Type().NumRecvs() == 0 - if base.Ctxt.Arch.Name == "ppc64le" && base.Ctxt.Flag_dynlink { + if (base.Ctxt.Arch.Name == "ppc64le" || base.Ctxt.Arch.Name == "ppc64") && base.Ctxt.Flag_dynlink { // cannot tailcall on PPC64 with dynamic linking, as we need // to restore R2 after call. tailcall = false @@ -417,33 +436,37 @@ func paramsToWasmFields(f *ir.Func, pragma string, result *abi.ABIParamResultInf for _, p := range abiParams { t := p.Type var wt obj.WasmFieldType - switch t.Kind() { - case types.TINT32, types.TUINT32: - wt = obj.WasmI32 - case types.TINT64, types.TUINT64: - wt = obj.WasmI64 - case types.TFLOAT32: - wt = obj.WasmF32 - case types.TFLOAT64: - wt = obj.WasmF64 - case types.TUNSAFEPTR, types.TUINTPTR: - wt = obj.WasmPtr - case types.TBOOL: - wt = obj.WasmBool - case types.TSTRING: - // Two parts, (ptr, len) - wt = obj.WasmPtr - wfs = append(wfs, obj.WasmField{Type: wt, Offset: p.FrameOffset(result)}) - wfs = append(wfs, obj.WasmField{Type: wt, Offset: p.FrameOffset(result) + int64(types.PtrSize)}) - continue - case types.TPTR: - if wasmElemTypeAllowed(t.Elem()) { + if t.IsSIMD() { + wt = obj.WasmV128 + } else { + switch t.Kind() { + case types.TINT32, types.TUINT32: + wt = obj.WasmI32 + case types.TINT64, types.TUINT64: + wt = obj.WasmI64 + case types.TFLOAT32: + wt = obj.WasmF32 + case types.TFLOAT64: + wt = obj.WasmF64 + case types.TUNSAFEPTR, types.TUINTPTR: + wt = obj.WasmPtr + case types.TBOOL: + wt = obj.WasmBool + case types.TSTRING: + // Two parts, (ptr, len) wt = obj.WasmPtr - break + wfs = append(wfs, obj.WasmField{Type: wt, Offset: p.FrameOffset(result)}) + wfs = append(wfs, obj.WasmField{Type: wt, Offset: p.FrameOffset(result) + int64(types.PtrSize)}) + continue + case types.TPTR: + if wasmElemTypeAllowed(t.Elem()) { + wt = obj.WasmPtr + break + } + fallthrough + default: + base.ErrorfAt(f.Pos(), 0, "%s: unsupported parameter type %s", pragma, t.String()) } - fallthrough - default: - base.ErrorfAt(f.Pos(), 0, "%s: unsupported parameter type %s", pragma, t.String()) } wfs = append(wfs, obj.WasmField{Type: wt, Offset: p.FrameOffset(result)}) } @@ -458,27 +481,31 @@ func resultsToWasmFields(f *ir.Func, pragma string, result *abi.ABIParamResultIn wfs := make([]obj.WasmField, len(abiParams)) for i, p := range abiParams { t := p.Type - switch t.Kind() { - case types.TINT32, types.TUINT32: - wfs[i].Type = obj.WasmI32 - case types.TINT64, types.TUINT64: - wfs[i].Type = obj.WasmI64 - case types.TFLOAT32: - wfs[i].Type = obj.WasmF32 - case types.TFLOAT64: - wfs[i].Type = obj.WasmF64 - case types.TUNSAFEPTR, types.TUINTPTR: - wfs[i].Type = obj.WasmPtr - case types.TBOOL: - wfs[i].Type = obj.WasmBool - case types.TPTR: - if wasmElemTypeAllowed(t.Elem()) { + if t.IsSIMD() { + wfs[i].Type = obj.WasmV128 + } else { + switch t.Kind() { + case types.TINT32, types.TUINT32: + wfs[i].Type = obj.WasmI32 + case types.TINT64, types.TUINT64: + wfs[i].Type = obj.WasmI64 + case types.TFLOAT32: + wfs[i].Type = obj.WasmF32 + case types.TFLOAT64: + wfs[i].Type = obj.WasmF64 + case types.TUNSAFEPTR, types.TUINTPTR: wfs[i].Type = obj.WasmPtr - break + case types.TBOOL: + wfs[i].Type = obj.WasmBool + case types.TPTR: + if wasmElemTypeAllowed(t.Elem()) { + wfs[i].Type = obj.WasmPtr + break + } + fallthrough + default: + base.ErrorfAt(f.Pos(), 0, "%s: unsupported result type %s", pragma, t.String()) } - fallthrough - default: - base.ErrorfAt(f.Pos(), 0, "%s: unsupported result type %s", pragma, t.String()) } wfs[i].Offset = p.FrameOffset(result) } diff --git a/src/cmd/compile/internal/ssagen/intrinsics.go b/src/cmd/compile/internal/ssagen/intrinsics.go index e14db7b0a0c3e6..6044efdb4f7bbe 100644 --- a/src/cmd/compile/internal/ssagen/intrinsics.go +++ b/src/cmd/compile/internal/ssagen/intrinsics.go @@ -12,6 +12,7 @@ import ( "cmd/compile/internal/base" "cmd/compile/internal/ir" "cmd/compile/internal/ssa" + "cmd/compile/internal/typecheck" "cmd/compile/internal/types" "cmd/internal/sys" ) @@ -195,6 +196,12 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { }, sys.AMD64, sys.I386, sys.ARM64, sys.ARM, sys.Loong64, sys.S390X) + addF("runtime", "memequal", + func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue4(ssa.OpMemEq, s.f.Config.Types.Bool, args[0], args[1], args[2], s.mem()) + }, + sys.ARM64) + if cfg.goppc64 >= 10 { // Use only on Power10 as the new byte reverse instructions that Power10 provide // make it worthwhile as an intrinsic @@ -295,7 +302,7 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { s.vars[memVar] = s.newValue3(ssa.OpAtomicStore8, types.TypeMem, args[0], args[1], s.mem()) return nil }, - sys.AMD64, sys.ARM64, sys.MIPS, sys.MIPS64, sys.PPC64, sys.RISCV64, sys.S390X) + sys.AMD64, sys.ARM64, sys.Loong64, sys.MIPS, sys.MIPS64, sys.PPC64, sys.RISCV64, sys.S390X) addF("internal/runtime/atomic", "Store64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { s.vars[memVar] = s.newValue3(ssa.OpAtomicStore64, types.TypeMem, args[0], args[1], s.mem()) @@ -324,7 +331,7 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { makeAtomicStoreGuardedIntrinsicLoong64 := func(op0, op1 ssa.Op, typ types.Kind, emit atomicOpEmitter) intrinsicBuilder { return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { // Target Atomic feature is identified by dynamic detection - addr := s.entryNewValue1A(ssa.OpAddr, types.Types[types.TBOOL].PtrTo(), ir.Syms.Loong64HasLAM_BH, s.sb) + addr := s.entryNewValue1A(ssa.OpAddr, types.Types[types.TBOOL].PtrTo(), ir.Syms.Loong64HasDBAR_HINTS, s.sb) v := s.load(types.Types[types.TBOOL], addr) b := s.endBlock() b.Kind = ssa.BlockIf @@ -336,14 +343,14 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { b.AddEdgeTo(bFalse) b.Likely = ssa.BranchLikely - // We have atomic instructions - use it directly. + // most loong64 machines support the finer-grained DBAR hints s.startBlock(bTrue) - emit(s, n, args, op1, typ, false) + emit(s, n, args, op0, typ, false) s.endBlock().AddEdgeTo(bEnd) // Use original instruction sequence. s.startBlock(bFalse) - emit(s, n, args, op0, typ, false) + emit(s, n, args, op1, typ, false) s.endBlock().AddEdgeTo(bEnd) // Merge results. @@ -361,20 +368,11 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { } } - addF("internal/runtime/atomic", "Store8", - makeAtomicStoreGuardedIntrinsicLoong64(ssa.OpAtomicStore8, ssa.OpAtomicStore8Variant, types.TUINT8, atomicStoreEmitterLoong64), - sys.Loong64) addF("internal/runtime/atomic", "Store", - func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { - s.vars[memVar] = s.newValue3(ssa.OpAtomicStore32Variant, types.TypeMem, args[0], args[1], s.mem()) - return nil - }, + makeAtomicStoreGuardedIntrinsicLoong64(ssa.OpAtomicStore32, ssa.OpAtomicStore32Variant, types.TUINT8, atomicStoreEmitterLoong64), sys.Loong64) addF("internal/runtime/atomic", "Store64", - func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { - s.vars[memVar] = s.newValue3(ssa.OpAtomicStore64Variant, types.TypeMem, args[0], args[1], s.mem()) - return nil - }, + makeAtomicStoreGuardedIntrinsicLoong64(ssa.OpAtomicStore64, ssa.OpAtomicStore64Variant, types.TUINT8, atomicStoreEmitterLoong64), sys.Loong64) addF("internal/runtime/atomic", "Xchg8", @@ -700,9 +698,7 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { alias("internal/runtime/atomic", "LoadAcq", "internal/runtime/atomic", "Load", lwatomics...) alias("internal/runtime/atomic", "LoadAcq64", "internal/runtime/atomic", "Load64", lwatomics...) alias("internal/runtime/atomic", "LoadAcquintptr", "internal/runtime/atomic", "LoadAcq", p4...) - alias("sync", "runtime_LoadAcquintptr", "internal/runtime/atomic", "LoadAcq", p4...) // linknamed alias("internal/runtime/atomic", "LoadAcquintptr", "internal/runtime/atomic", "LoadAcq64", p8...) - alias("sync", "runtime_LoadAcquintptr", "internal/runtime/atomic", "LoadAcq64", p8...) // linknamed // Aliases for atomic store operations alias("internal/runtime/atomic", "Storeint32", "internal/runtime/atomic", "Store", all...) @@ -712,9 +708,7 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { alias("internal/runtime/atomic", "StoreRel", "internal/runtime/atomic", "Store", lwatomics...) alias("internal/runtime/atomic", "StoreRel64", "internal/runtime/atomic", "Store64", lwatomics...) alias("internal/runtime/atomic", "StoreReluintptr", "internal/runtime/atomic", "StoreRel", p4...) - alias("sync", "runtime_StoreReluintptr", "internal/runtime/atomic", "StoreRel", p4...) // linknamed alias("internal/runtime/atomic", "StoreReluintptr", "internal/runtime/atomic", "StoreRel64", p8...) - alias("sync", "runtime_StoreReluintptr", "internal/runtime/atomic", "StoreRel64", p8...) // linknamed // Aliases for atomic swap operations alias("internal/runtime/atomic", "Xchgint32", "internal/runtime/atomic", "Xchg", all...) @@ -894,6 +888,48 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { makeRoundAMD64(ssa.OpTrunc), sys.AMD64) + makeRoundLoong64 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + addr := s.entryNewValue1A(ssa.OpAddr, types.Types[types.TBOOL].PtrTo(), ir.Syms.Loong64HasLSX, s.sb) + v := s.load(types.Types[types.TBOOL], addr) + b := s.endBlock() + b.Kind = ssa.BlockIf + b.SetControl(v) + bTrue := s.f.NewBlock(ssa.BlockPlain) + bFalse := s.f.NewBlock(ssa.BlockPlain) + bEnd := s.f.NewBlock(ssa.BlockPlain) + b.AddEdgeTo(bTrue) + b.AddEdgeTo(bFalse) + b.Likely = ssa.BranchLikely // most loong64 machines support the LSX + + // We have the intrinsic - use it directly. + s.startBlock(bTrue) + s.vars[n] = s.newValue1(op, types.Types[types.TFLOAT64], args[0]) + s.endBlock().AddEdgeTo(bEnd) + + // Call the pure Go version. + s.startBlock(bFalse) + s.vars[n] = s.callResult(n, callNormal) // types.Types[TFLOAT64] + s.endBlock().AddEdgeTo(bEnd) + + // Merge results. + s.startBlock(bEnd) + return s.variable(n, types.Types[types.TFLOAT64]) + } + } + addF("math", "RoundToEven", + makeRoundLoong64(ssa.OpRoundToEven), + sys.Loong64) + addF("math", "Floor", + makeRoundLoong64(ssa.OpFloor), + sys.Loong64) + addF("math", "Ceil", + makeRoundLoong64(ssa.OpCeil), + sys.Loong64) + addF("math", "Trunc", + makeRoundLoong64(ssa.OpTrunc), + sys.Loong64) + /******** math/bits ********/ addF("math/bits", "TrailingZeros64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { @@ -1021,27 +1057,27 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { // LeadingZeros is handled because it trivially calls Len. addF("math/bits", "Reverse64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { - return s.newValue1(ssa.OpBitRev64, types.Types[types.TINT], args[0]) + return s.newValue1(ssa.OpBitRev64, types.Types[types.TUINT64], args[0]) }, sys.ARM64, sys.Loong64) addF("math/bits", "Reverse32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { - return s.newValue1(ssa.OpBitRev32, types.Types[types.TINT], args[0]) + return s.newValue1(ssa.OpBitRev32, types.Types[types.TUINT32], args[0]) }, sys.ARM64, sys.Loong64) addF("math/bits", "Reverse16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { - return s.newValue1(ssa.OpBitRev16, types.Types[types.TINT], args[0]) + return s.newValue1(ssa.OpBitRev16, types.Types[types.TUINT16], args[0]) }, sys.ARM64, sys.Loong64) addF("math/bits", "Reverse8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { - return s.newValue1(ssa.OpBitRev8, types.Types[types.TINT], args[0]) + return s.newValue1(ssa.OpBitRev8, types.Types[types.TUINT8], args[0]) }, sys.ARM64, sys.Loong64) addF("math/bits", "Reverse", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { - return s.newValue1(ssa.OpBitRev64, types.Types[types.TINT], args[0]) + return s.newValue1(ssa.OpBitRev64, types.Types[types.TUINT], args[0]) }, sys.ARM64, sys.Loong64) addF("math/bits", "RotateLeft8", @@ -1219,13 +1255,12 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { alias("math/bits", "OnesCount", "math/bits", "OnesCount64", p8...) - addF("math/bits", "Mul64", + add("math/bits", "Mul64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return s.newValue2(ssa.OpMul64uhilo, types.NewTuple(types.Types[types.TUINT64], types.Types[types.TUINT64]), args[0], args[1]) }, - sys.AMD64, sys.ARM64, sys.PPC64, sys.S390X, sys.MIPS64, sys.RISCV64, sys.Loong64) + all...) alias("math/bits", "Mul", "math/bits", "Mul64", p8...) - alias("internal/runtime/math", "Mul64", "math/bits", "Mul64", p8...) addF("math/bits", "Add64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return s.newValue3(ssa.OpAdd64carry, types.NewTuple(types.Types[types.TUINT64], types.Types[types.TUINT64]), args[0], args[1], args[2]) @@ -1435,7 +1470,7 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { // byte N matched). // // NOTE: See comment above on bitsetFirst. - out := s.newValue1(ssa.OpAMD64PMOVMSKB, types.Types[types.TUINT16], eq) + out := s.newValue1(ssa.OpAMD64PMOVMSKB, types.Types[types.TUINT8], eq) // g is only 64-bits so the upper 64-bits of the // 128-bit register will be zero. If h2 is also zero, @@ -1495,7 +1530,7 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { // means byte N matched). // // NOTE: See comment above on bitsetFirst. - ret := s.newValue1(ssa.OpAMD64PMOVMSKB, types.Types[types.TUINT16], sign) + ret := s.newValue1(ssa.OpAMD64PMOVMSKB, types.Types[types.TUINT64], sign) // g is only 64-bits so the upper 64-bits of // the 128-bit register will be zero. PSIGNB @@ -1525,7 +1560,7 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { // byte N matched). // // NOTE: See comment above on bitsetFirst. - out := s.newValue1(ssa.OpAMD64PMOVMSKB, types.Types[types.TUINT16], eq) + out := s.newValue1(ssa.OpAMD64PMOVMSKB, types.Types[types.TUINT8], eq) // g is only 64-bits so the upper 64-bits of the // 128-bit register will be zero. The upper 64-bits of @@ -1559,7 +1594,7 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { // byte N matched). // // NOTE: See comment above on bitsetFirst. - ret := s.newValue1(ssa.OpAMD64PMOVMSKB, types.Types[types.TUINT16], gfp) + ret := s.newValue1(ssa.OpAMD64PMOVMSKB, types.Types[types.TUINT64], gfp) // g is only 64-bits so the upper 64-bits of the // 128-bit register will be zero. Zero will never match @@ -1591,10 +1626,10 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { // byte N matched). // // NOTE: See comment above on bitsetFirst. - mask := s.newValue1(ssa.OpAMD64PMOVMSKB, types.Types[types.TUINT16], gfp) + mask := s.newValue1(ssa.OpAMD64PMOVMSKB, types.Types[types.TUINT8], gfp) // Invert the mask to set the bits for the full slots. - out := s.newValue1(ssa.OpCom16, types.Types[types.TUINT16], mask) + out := s.newValue1(ssa.OpCom8, types.Types[types.TUINT8], mask) // g is only 64-bits so the upper 64-bits of the // 128-bit register will be zero, with bit 7 unset. @@ -1602,6 +1637,750 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { return s.newValue1(ssa.OpZeroExt8to64, types.Types[types.TUINT64], out) }, sys.AMD64) + + /******** crypto/internal/constanttime ********/ + // We implement a superset of the Select promise: + // Select returns x if v != 0 and y if v == 0. + hasCMOV := []*sys.Arch{sys.ArchAMD64, sys.ArchARM64, sys.ArchLoong64, sys.ArchPPC64, sys.ArchPPC64LE, sys.ArchWasm} + if cfg.goriscv64 >= 23 { + hasCMOV = append(hasCMOV, sys.ArchRISCV64) + } + add("crypto/internal/constanttime", "Select", + func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + v, x, y := args[0], args[1], args[2] + + var checkOp ssa.Op + var zero *ssa.Value + switch s.config.PtrSize { + case 8: + checkOp = ssa.OpNeq64 + zero = s.constInt64(types.Types[types.TINT], 0) + case 4: + checkOp = ssa.OpNeq32 + zero = s.constInt32(types.Types[types.TINT], 0) + default: + panic("unreachable") + } + check := s.newValue2(checkOp, types.Types[types.TBOOL], zero, v) + + return s.newValue3(ssa.OpCondSelect, types.Types[types.TINT], x, y, check) + }, hasCMOV...) // all with CMOV support. + add("crypto/internal/constanttime", "boolToUint8", + func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue1(ssa.OpCvtBoolToUint8, types.Types[types.TUINT8], args[0]) + }, + all...) + + if buildcfg.Experiment.SIMD { + // Only enable intrinsics, if SIMD experiment. + simdAMD64Intrinsics(addF) + simdARM64Intrinsics(addF) + initWasmSIMD() + + addF(simdPackage, "ClearAVXUpperBits", + func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + s.vars[memVar] = s.newValue1(ssa.OpAMD64VZEROUPPER, types.TypeMem, s.mem()) + return nil + }, + sys.AMD64) + + addF(simdPackage, "Int8x16.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Int16x8.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Int32x4.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Int64x2.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Uint8x16.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Uint16x8.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Uint32x4.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Uint64x2.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Int8x32.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Int16x16.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Int32x8.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Int64x4.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Uint8x32.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Uint16x16.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Uint32x8.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Uint64x4.IsZero", opLen1(ssa.OpIsZeroVec, types.Types[types.TBOOL]), sys.AMD64) + addF(simdPackage, "Float32x4.IsNaN", opLen1(ssa.OpIsNaNFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.IsNaN", opLen1(ssa.OpIsNaNFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.IsNaN", opLen1(ssa.OpIsNaNFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.IsNaN", opLen1(ssa.OpIsNaNFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.IsNaN", opLen1(ssa.OpIsNaNFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.IsNaN", opLen1(ssa.OpIsNaNFloat64x8, types.TypeVec512), sys.AMD64) + + // sfp4 is intrinsic-if-constant, but otherwise it's complicated enough to just implement in Go. + sfp4 := func(method string, hwop ssa.Op, vectype *types.Type) { + addF(simdPackage, method, + func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + x, a, b, c, d, y := args[0], args[1], args[2], args[3], args[4], args[5] + if a.Op == ssa.OpConst8 && b.Op == ssa.OpConst8 && c.Op == ssa.OpConst8 && d.Op == ssa.OpConst8 { + z := select4FromPair(x, a, b, c, d, y, s, hwop, vectype) + if z != nil { + return z + } + } + return s.callResult(n, callNormal) + }, + sys.AMD64) + } + + sfp4("Int32x4.ConcatPermuteScalars", ssa.OpconcatSelectedConstantInt32x4, types.TypeVec128) + sfp4("Uint32x4.ConcatPermuteScalars", ssa.OpconcatSelectedConstantUint32x4, types.TypeVec128) + sfp4("Float32x4.ConcatPermuteScalars", ssa.OpconcatSelectedConstantFloat32x4, types.TypeVec128) + + sfp4("Int32x8.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedInt32x8, types.TypeVec256) + sfp4("Uint32x8.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedUint32x8, types.TypeVec256) + sfp4("Float32x8.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedFloat32x8, types.TypeVec256) + + sfp4("Int32x16.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedInt32x16, types.TypeVec512) + sfp4("Uint32x16.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedUint32x16, types.TypeVec512) + sfp4("Float32x16.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedFloat32x16, types.TypeVec512) + + // sfp2 is intrinsic-if-constant, but otherwise it's complicated enough to just implement in Go. + sfp2 := func(method string, hwop ssa.Op, vectype *types.Type, cscimm func(i, j uint8) int64) { + addF(simdPackage, method, + func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + x, a, b, y := args[0], args[1], args[2], args[3] + if a.Op == ssa.OpConst8 && b.Op == ssa.OpConst8 { + z := select2FromPair(x, a, b, y, s, hwop, vectype, cscimm) + if z != nil { + return z + } + } + return s.callResult(n, callNormal) + }, + sys.AMD64) + } + + sfp2("Uint64x2.ConcatPermuteScalars", ssa.OpconcatSelectedConstantUint64x2, types.TypeVec128, cscimm2) + sfp2("Int64x2.ConcatPermuteScalars", ssa.OpconcatSelectedConstantInt64x2, types.TypeVec128, cscimm2) + sfp2("Float64x2.ConcatPermuteScalars", ssa.OpconcatSelectedConstantFloat64x2, types.TypeVec128, cscimm2) + + sfp2("Uint64x4.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedUint64x4, types.TypeVec256, cscimm2g2) + sfp2("Int64x4.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedInt64x4, types.TypeVec256, cscimm2g2) + sfp2("Float64x4.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedFloat64x4, types.TypeVec256, cscimm2g2) + + sfp2("Uint64x8.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedUint64x8, types.TypeVec512, cscimm2g4) + sfp2("Int64x8.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedInt64x8, types.TypeVec512, cscimm2g4) + sfp2("Float64x8.ConcatPermuteScalarsGrouped", ssa.OpconcatSelectedConstantGroupedFloat64x8, types.TypeVec512, cscimm2g4) + + } +} + +const simdPackage = "simd/archsimd" + +func cscimm4(a, b, c, d uint8) int64 { + return se(a + b<<2 + c<<4 + d<<6) +} + +func cscimm2(a, b uint8) int64 { + return se(a + b<<1) +} + +func cscimm2g2(a, b uint8) int64 { + g := cscimm2(a, b) + return int64(int8(g + g<<2)) +} + +func cscimm2g4(a, b uint8) int64 { + g := cscimm2g2(a, b) + return int64(int8(g + g<<4)) +} + +const ( + _LLLL = iota + _HLLL + _LHLL + _HHLL + _LLHL + _HLHL + _LHHL + _HHHL + _LLLH + _HLLH + _LHLH + _HHLH + _LLHH + _HLHH + _LHHH + _HHHH +) + +const ( + _LL = iota + _HL + _LH + _HH +) + +func select2FromPair(x, _a, _b, y *ssa.Value, s *state, op ssa.Op, t *types.Type, csc func(a, b uint8) int64) *ssa.Value { + a, b := uint8(_a.AuxInt8()), uint8(_b.AuxInt8()) + if a > 3 || b > 3 { + return nil + } + pattern := (a&2)>>1 + (b & 2) + a, b = a&1, b&1 + + switch pattern { + case _LL: + return s.newValue2I(op, t, csc(a, b), x, x) + case _HH: + return s.newValue2I(op, t, csc(a, b), y, y) + case _LH: + return s.newValue2I(op, t, csc(a, b), x, y) + case _HL: + return s.newValue2I(op, t, csc(a, b), y, x) + } + panic("The preceding switch should have been exhaustive") +} + +func select4FromPair(x, _a, _b, _c, _d, y *ssa.Value, s *state, op ssa.Op, t *types.Type) *ssa.Value { + a, b, c, d := uint8(_a.AuxInt8()), uint8(_b.AuxInt8()), uint8(_c.AuxInt8()), uint8(_d.AuxInt8()) + if a > 7 || b > 7 || c > 7 || d > 7 { + return nil + } + pattern := a>>2 + (b&4)>>1 + (c & 4) + (d&4)<<1 + + a, b, c, d = a&3, b&3, c&3, d&3 + + switch pattern { + case _LLLL: + // TODO DETECT 0,1,2,3, 0,0,0,0 + return s.newValue2I(op, t, cscimm4(a, b, c, d), x, x) + case _HHHH: + // TODO DETECT 0,1,2,3, 0,0,0,0 + return s.newValue2I(op, t, cscimm4(a, b, c, d), y, y) + case _LLHH: + return s.newValue2I(op, t, cscimm4(a, b, c, d), x, y) + case _HHLL: + return s.newValue2I(op, t, cscimm4(a, b, c, d), y, x) + + case _HLLL: + z := s.newValue2I(op, t, cscimm4(a, a, b, b), y, x) + return s.newValue2I(op, t, cscimm4(0, 2, c, d), z, x) + case _LHLL: + z := s.newValue2I(op, t, cscimm4(a, a, b, b), x, y) + return s.newValue2I(op, t, cscimm4(0, 2, c, d), z, x) + case _HLHH: + z := s.newValue2I(op, t, cscimm4(a, a, b, b), y, x) + return s.newValue2I(op, t, cscimm4(0, 2, c, d), z, y) + case _LHHH: + z := s.newValue2I(op, t, cscimm4(a, a, b, b), x, y) + return s.newValue2I(op, t, cscimm4(0, 2, c, d), z, y) + + case _LLLH: + z := s.newValue2I(op, t, cscimm4(c, c, d, d), x, y) + return s.newValue2I(op, t, cscimm4(a, b, 0, 2), x, z) + case _LLHL: + z := s.newValue2I(op, t, cscimm4(c, c, d, d), y, x) + return s.newValue2I(op, t, cscimm4(a, b, 0, 2), x, z) + + case _HHLH: + z := s.newValue2I(op, t, cscimm4(c, c, d, d), x, y) + return s.newValue2I(op, t, cscimm4(a, b, 0, 2), y, z) + + case _HHHL: + z := s.newValue2I(op, t, cscimm4(c, c, d, d), y, x) + return s.newValue2I(op, t, cscimm4(a, b, 0, 2), y, z) + + case _LHLH: + z := s.newValue2I(op, t, cscimm4(a, c, b, d), x, y) + return s.newValue2I(op, t, se(0b11_01_10_00), z, z) + case _HLHL: + z := s.newValue2I(op, t, cscimm4(b, d, a, c), x, y) + return s.newValue2I(op, t, se(0b01_11_00_10), z, z) + case _HLLH: + z := s.newValue2I(op, t, cscimm4(b, c, a, d), x, y) + return s.newValue2I(op, t, se(0b11_01_00_10), z, z) + case _LHHL: + z := s.newValue2I(op, t, cscimm4(a, d, b, c), x, y) + return s.newValue2I(op, t, se(0b01_11_10_00), z, z) + } + panic("The preceding switch should have been exhaustive") +} + +// se smears the not-really-a-sign bit of a uint8 to conform to the conventions +// for representing AuxInt in ssa. +func se(x uint8) int64 { + return int64(int8(x)) +} + +func opLen1(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue1(op, t, args[0]) + } +} + +func opLen2(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue2(op, t, args[0], args[1]) + } +} + +func opLen2_21(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue2(op, t, args[1], args[0]) + } +} + +func opLen3(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue3(op, t, args[0], args[1], args[2]) + } +} + +var ssaVecBySize = map[int64]*types.Type{ + 16: types.TypeVec128, + 32: types.TypeVec256, + 64: types.TypeVec512, +} + +func opLen3_31Zero3(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + if t, ok := ssaVecBySize[args[1].Type.Size()]; !ok { + panic("unknown simd vector size") + } else { + return s.newValue3(op, t, s.newValue0(ssa.OpZeroSIMD, t), args[1], args[0]) + } + } +} + +func opLen3_21(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue3(op, t, args[1], args[0], args[2]) + } +} + +func opLen3_231(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue3(op, t, args[2], args[0], args[1]) + } +} + +func opLen4(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue4(op, t, args[0], args[1], args[2], args[3]) + } +} + +func opLen4_231(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue4(op, t, args[2], args[0], args[1], args[3]) + } +} + +func opLen4_31(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue4(op, t, args[2], args[1], args[0], args[3]) + } +} + +func immJumpTable(s *state, idx *ssa.Value, intrinsicCall *ir.CallExpr, genOp func(*state, int)) *ssa.Value { + if !idx.Type.IsKind(types.TUINT8) && !idx.Type.IsKind(types.TUINT64) { + panic("immJumpTable expects uint8 or uint64 value") + } + if idx.Type.IsKind(types.TUINT64) { + // Match the constant path and keep the jump table index in range. + idx = s.conv(nil, idx, idx.Type, types.Types[types.TUINT8]) + } + + if base.Ctxt.Retpoline { + // Note spectre=all implies retpoline which requires binary search instead of table switch. + return branchTableImm8(s, idx, intrinsicCall, genOp) + } + + // Make blocks we'll need. + bEnd := s.f.NewBlock(ssa.BlockPlain) + + // We will exhaust 0-255, so no need to check the bounds. + t := types.Types[types.TUINTPTR] + idx = s.conv(nil, idx, idx.Type, t) + + b := s.curBlock + b.Kind = ssa.BlockJumpTable + b.Pos = intrinsicCall.Pos() + + b.SetControl(idx) + targets := [256]*ssa.Block{} + for i := range 256 { + t := s.f.NewBlock(ssa.BlockPlain) + targets[i] = t + b.AddEdgeTo(t) + } + s.endBlock() + + for i, t := range targets { + s.startBlock(t) + genOp(s, i) + if t.Kind != ssa.BlockExit { + t.AddEdgeTo(bEnd) + } + s.endBlock() + } + + s.startBlock(bEnd) + ret := s.variable(intrinsicCall, intrinsicCall.Type()) + return ret +} + +func branchTableImm8(s *state, idx *ssa.Value, intrinsicCall *ir.CallExpr, genOp func(*state, int)) *ssa.Value { + return branchTableN(s, idx, intrinsicCall, genOp, 256, true) +} + +func branchTableN(s *state, idx *ssa.Value, intrinsicCall *ir.CallExpr, genOp func(*state, int), immLimit uint64, preChecked bool) *ssa.Value { + // Make blocks we'll need. + bEnd := s.f.NewBlock(ssa.BlockPlain) + bPanic := s.f.NewBlock(ssa.BlockPlain) + + jt := s.f.NewBlock(ssa.BlockPlain) + + t := types.Types[types.TUINTPTR] + idx = s.conv(nil, idx, idx.Type, t) + + if !preChecked { + // Begin with a bounds check + width := s.uintptrConstant(immLimit) + cmp := s.newValue2(s.ssaOp(ir.OLT, t), types.Types[types.TBOOL], idx, width) + bb := s.endBlock() + bb.Kind = ssa.BlockIf + bb.SetControl(cmp) + bb.AddEdgeTo(jt) // in range - use jump table + bb.AddEdgeTo(bPanic) // out of range - panic + bb.Likely = ssa.BranchLikely // panic is unlikely + + s.startBlock(bPanic) + s.rtcall(ir.Syms.PanicSimdImm, false, nil) + } + if s.curBlock != nil { + bb := s.endBlock() + bb.AddEdgeTo(jt) + } + + s.startBlock(jt) + jt.Kind = ssa.BlockPlain + jt.Pos = intrinsicCall.Pos() + + branchTableNInner(s, idx, 0, immLimit, genOp, bEnd) + + s.startBlock(bEnd) + ret := s.variable(intrinsicCall, intrinsicCall.Type()) + return ret +} + +func branchTableNInner(s *state, idx *ssa.Value, lowInclusive, len uint64, genOp func(*state, int), bEnd *ssa.Block) { + t := types.Types[types.TUINTPTR] + if len == 0 { + panic("empty branch table") + } + if len == 1 { + genOp(s, int(lowInclusive+len-1)) + if s.curBlock != nil { // if genOp was "panic" then curBlock is already ended and nil + if s.curBlock.Kind != ssa.BlockExit { + s.curBlock.AddEdgeTo(bEnd) + } + s.endBlock() + } + return + } + + s.curBlock.Kind = ssa.BlockIf + cmp := s.newValue2(s.ssaOp(ir.OLT, t), types.Types[types.TBOOL], idx, s.uintptrConstant(lowInclusive+len/2)) + bb := s.endBlock() + bb.Kind = ssa.BlockIf + bb.SetControl(cmp) + bMatch := s.f.NewBlock(ssa.BlockPlain) + bNext := s.f.NewBlock(ssa.BlockPlain) + bb.AddEdgeTo(bMatch) + bb.AddEdgeTo(bNext) + s.startBlock(bMatch) + branchTableNInner(s, idx, lowInclusive, len/2, genOp, bEnd) + s.startBlock(bNext) + branchTableNInner(s, idx, lowInclusive+len/2, len-len/2, genOp, bEnd) +} + +// immJumpTableN emits a jump table to one of a number of indexed cases, from zero to n-1. +// an index of n or larger will panic +func immJumpTableN(s *state, idx *ssa.Value, intrinsicCall *ir.CallExpr, immLimit uint64, genOp func(*state, int)) *ssa.Value { + + if !idx.Type.IsKind(types.TUINT8) && !idx.Type.IsKind(types.TUINT64) { + s.Fatalf("immJumpTable expects uint8 or uint64 value, saw %v instead, val=%s", idx.Type.String(), idx.LongString()) + } + + if base.Flag.N != 0 || !Arch.LinkArch.CanJumpTable || base.Ctxt.Retpoline { + return branchTableN(s, idx, intrinsicCall, genOp, immLimit, false) + } + + // Make blocks we'll need. + bEnd := s.f.NewBlock(ssa.BlockPlain) + bPanic := s.f.NewBlock(ssa.BlockPlain) + + jt := s.f.NewBlock(ssa.BlockJumpTable) + + t := types.Types[types.TUINTPTR] + idx = s.conv(nil, idx, idx.Type, t) + width := s.uintptrConstant(immLimit) + + // Begin with a bounds check + cmp := s.newValue2(s.ssaOp(ir.OLT, t), types.Types[types.TBOOL], idx, width) + bb := s.endBlock() + bb.Kind = ssa.BlockIf + bb.SetControl(cmp) + bb.AddEdgeTo(jt) // in range - use jump table + bb.AddEdgeTo(bPanic) // out of range - panic + bb.Likely = ssa.BranchLikely // panic is unlikely + + s.startBlock(bPanic) + s.rtcall(ir.Syms.PanicSimdImm, false, nil) + s.endBlock() + + s.startBlock(jt) + jt.Kind = ssa.BlockJumpTable + jt.Pos = intrinsicCall.Pos() + if base.Flag.Cfg.SpectreIndex { + // Potential Spectre vulnerability hardening? + idx = s.newValue2(ssa.OpSpectreSliceIndex, t, idx, s.uintptrConstant(immLimit-1)) + } + jt.SetControl(idx) + targets := make([]*ssa.Block, immLimit, immLimit) + for i := range immLimit { + t := s.f.NewBlock(ssa.BlockPlain) + targets[i] = t + jt.AddEdgeTo(t) + } + s.endBlock() + + for i, t := range targets { + s.startBlock(t) + genOp(s, i) + if t.Kind != ssa.BlockExit { + t.AddEdgeTo(bEnd) + } + s.endBlock() + } + + s.startBlock(bEnd) + ret := s.variable(intrinsicCall, intrinsicCall.Type()) + return ret +} + +func opLen1Imm8(op ssa.Op, t *types.Type, offset int) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + if args[1].Op == ssa.OpConst8 || args[1].Op == ssa.OpConst64 { + return s.newValue1I(op, t, int64(int8(args[1].AuxInt< 0 { + if ft.NumResults() == 1 { + call.SetType(ft.Result(0).Type) + } else { + call.SetType(ft.ResultsTuple()) + } + n := ir.NewReturnStmt(base.Pos, nil) + n.Results = []ir.Node{call} + ret = n + } + fn.Body.Append(ret) + + if base.Flag.LowerR != 0 { + ir.DumpList("generate intrinsic body", fn.Body) + } + + ir.CurFunc = fn + typecheck.Stmts(fn.Body) + ir.CurFunc = nil // we know CurFunc is nil at entry } diff --git a/src/cmd/compile/internal/ssagen/intrinsics_test.go b/src/cmd/compile/internal/ssagen/intrinsics_test.go index 0623c5f2098c4e..0fe0525ce1a3fc 100644 --- a/src/cmd/compile/internal/ssagen/intrinsics_test.go +++ b/src/cmd/compile/internal/ssagen/intrinsics_test.go @@ -16,6 +16,9 @@ import ( var updateIntrinsics = flag.Bool("update", false, "Print an updated intrinsics table") +// TODO turn on after SIMD is stable. The time burned keeping this test happy during SIMD development has already well exceeded any plausible benefit. +var simd = flag.Bool("simd", false, "Also check SIMD intrinsics; for now, it is noisy and not helpful") + type testIntrinsicKey struct { archName string pkg string @@ -33,6 +36,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"386", "internal/runtime/sys", "TrailingZeros64"}: struct{}{}, {"386", "internal/runtime/sys", "TrailingZeros8"}: struct{}{}, {"386", "math", "sqrt"}: struct{}{}, + {"386", "math/bits", "Mul64"}: struct{}{}, {"386", "math/bits", "ReverseBytes32"}: struct{}{}, {"386", "math/bits", "ReverseBytes64"}: struct{}{}, {"386", "math/bits", "TrailingZeros16"}: struct{}{}, @@ -41,6 +45,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"386", "math/bits", "TrailingZeros8"}: struct{}{}, {"386", "runtime", "KeepAlive"}: struct{}{}, {"386", "runtime", "slicebytetostringtmp"}: struct{}{}, + {"386", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"amd64", "internal/runtime/atomic", "And"}: struct{}{}, {"amd64", "internal/runtime/atomic", "And32"}: struct{}{}, {"amd64", "internal/runtime/atomic", "And64"}: struct{}{}, @@ -97,7 +102,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"amd64", "internal/runtime/maps", "ctrlGroupMatchEmptyOrDeleted"}: struct{}{}, {"amd64", "internal/runtime/maps", "ctrlGroupMatchFull"}: struct{}{}, {"amd64", "internal/runtime/math", "Add64"}: struct{}{}, - {"amd64", "internal/runtime/math", "Mul64"}: struct{}{}, {"amd64", "internal/runtime/math", "MulUintptr"}: struct{}{}, {"amd64", "internal/runtime/sys", "Bswap32"}: struct{}{}, {"amd64", "internal/runtime/sys", "Bswap64"}: struct{}{}, @@ -149,8 +153,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"amd64", "math/bits", "TrailingZeros8"}: struct{}{}, {"amd64", "runtime", "KeepAlive"}: struct{}{}, {"amd64", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"amd64", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"amd64", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"amd64", "sync/atomic", "AddInt32"}: struct{}{}, {"amd64", "sync/atomic", "AddInt64"}: struct{}{}, {"amd64", "sync/atomic", "AddUint32"}: struct{}{}, @@ -187,6 +189,8 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"amd64", "sync/atomic", "SwapUint32"}: struct{}{}, {"amd64", "sync/atomic", "SwapUint64"}: struct{}{}, {"amd64", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"amd64", "crypto/internal/constanttime", "Select"}: struct{}{}, + {"amd64", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"arm", "internal/runtime/sys", "Bswap32"}: struct{}{}, {"arm", "internal/runtime/sys", "Bswap64"}: struct{}{}, {"arm", "internal/runtime/sys", "GetCallerPC"}: struct{}{}, @@ -205,6 +209,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"arm", "math/bits", "Len32"}: struct{}{}, {"arm", "math/bits", "Len64"}: struct{}{}, {"arm", "math/bits", "Len8"}: struct{}{}, + {"arm", "math/bits", "Mul64"}: struct{}{}, {"arm", "math/bits", "ReverseBytes32"}: struct{}{}, {"arm", "math/bits", "ReverseBytes64"}: struct{}{}, {"arm", "math/bits", "RotateLeft32"}: struct{}{}, @@ -214,6 +219,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"arm", "math/bits", "TrailingZeros8"}: struct{}{}, {"arm", "runtime", "KeepAlive"}: struct{}{}, {"arm", "runtime", "slicebytetostringtmp"}: struct{}{}, + {"arm", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"arm64", "internal/runtime/atomic", "And"}: struct{}{}, {"arm64", "internal/runtime/atomic", "And32"}: struct{}{}, {"arm64", "internal/runtime/atomic", "And64"}: struct{}{}, @@ -264,7 +270,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"arm64", "internal/runtime/atomic", "Xchgint64"}: struct{}{}, {"arm64", "internal/runtime/atomic", "Xchguintptr"}: struct{}{}, {"arm64", "internal/runtime/math", "Add64"}: struct{}{}, - {"arm64", "internal/runtime/math", "Mul64"}: struct{}{}, {"arm64", "internal/runtime/math", "MulUintptr"}: struct{}{}, {"arm64", "internal/runtime/sys", "Bswap32"}: struct{}{}, {"arm64", "internal/runtime/sys", "Bswap64"}: struct{}{}, @@ -318,10 +323,9 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"arm64", "math/bits", "TrailingZeros64"}: struct{}{}, {"arm64", "math/bits", "TrailingZeros8"}: struct{}{}, {"arm64", "runtime", "KeepAlive"}: struct{}{}, + {"arm64", "runtime", "memequal"}: struct{}{}, {"arm64", "runtime", "publicationBarrier"}: struct{}{}, {"arm64", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"arm64", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"arm64", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"arm64", "sync/atomic", "AddInt32"}: struct{}{}, {"arm64", "sync/atomic", "AddInt64"}: struct{}{}, {"arm64", "sync/atomic", "AddUint32"}: struct{}{}, @@ -358,6 +362,8 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"arm64", "sync/atomic", "SwapUint32"}: struct{}{}, {"arm64", "sync/atomic", "SwapUint64"}: struct{}{}, {"arm64", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"arm64", "crypto/internal/constanttime", "Select"}: struct{}{}, + {"arm64", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"loong64", "internal/runtime/atomic", "And"}: struct{}{}, {"loong64", "internal/runtime/atomic", "And32"}: struct{}{}, {"loong64", "internal/runtime/atomic", "And64"}: struct{}{}, @@ -408,7 +414,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"loong64", "internal/runtime/atomic", "Xchgint64"}: struct{}{}, {"loong64", "internal/runtime/atomic", "Xchguintptr"}: struct{}{}, {"loong64", "internal/runtime/math", "Add64"}: struct{}{}, - {"loong64", "internal/runtime/math", "Mul64"}: struct{}{}, {"loong64", "internal/runtime/math", "MulUintptr"}: struct{}{}, {"loong64", "internal/runtime/sys", "Bswap32"}: struct{}{}, {"loong64", "internal/runtime/sys", "Bswap64"}: struct{}{}, @@ -427,6 +432,10 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"loong64", "math", "Copysign"}: struct{}{}, {"loong64", "math", "FMA"}: struct{}{}, {"loong64", "math", "sqrt"}: struct{}{}, + {"loong64", "math", "Ceil"}: struct{}{}, + {"loong64", "math", "Floor"}: struct{}{}, + {"loong64", "math", "RoundToEven"}: struct{}{}, + {"loong64", "math", "Trunc"}: struct{}{}, {"loong64", "math/big", "mulWW"}: struct{}{}, {"loong64", "math/bits", "Add"}: struct{}{}, {"loong64", "math/bits", "Add64"}: struct{}{}, @@ -461,8 +470,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"loong64", "runtime", "KeepAlive"}: struct{}{}, {"loong64", "runtime", "publicationBarrier"}: struct{}{}, {"loong64", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"loong64", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"loong64", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"loong64", "sync/atomic", "AddInt32"}: struct{}{}, {"loong64", "sync/atomic", "AddInt64"}: struct{}{}, {"loong64", "sync/atomic", "AddUint32"}: struct{}{}, @@ -504,6 +511,8 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"loong64", "sync/atomic", "SwapUint32"}: struct{}{}, {"loong64", "sync/atomic", "SwapUint64"}: struct{}{}, {"loong64", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"loong64", "crypto/internal/constanttime", "Select"}: struct{}{}, + {"loong64", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"mips", "internal/runtime/atomic", "And"}: struct{}{}, {"mips", "internal/runtime/atomic", "And8"}: struct{}{}, {"mips", "internal/runtime/atomic", "Cas"}: struct{}{}, @@ -549,6 +558,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mips", "math/bits", "Len32"}: struct{}{}, {"mips", "math/bits", "Len64"}: struct{}{}, {"mips", "math/bits", "Len8"}: struct{}{}, + {"mips", "math/bits", "Mul64"}: struct{}{}, {"mips", "math/bits", "TrailingZeros16"}: struct{}{}, {"mips", "math/bits", "TrailingZeros32"}: struct{}{}, {"mips", "math/bits", "TrailingZeros64"}: struct{}{}, @@ -556,8 +566,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mips", "runtime", "KeepAlive"}: struct{}{}, {"mips", "runtime", "publicationBarrier"}: struct{}{}, {"mips", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"mips", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"mips", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"mips", "sync/atomic", "AddInt32"}: struct{}{}, {"mips", "sync/atomic", "AddUint32"}: struct{}{}, {"mips", "sync/atomic", "AddUintptr"}: struct{}{}, @@ -574,6 +582,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mips", "sync/atomic", "SwapInt32"}: struct{}{}, {"mips", "sync/atomic", "SwapUint32"}: struct{}{}, {"mips", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"mips", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"mips64", "internal/runtime/atomic", "And"}: struct{}{}, {"mips64", "internal/runtime/atomic", "And8"}: struct{}{}, {"mips64", "internal/runtime/atomic", "Cas"}: struct{}{}, @@ -617,7 +626,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mips64", "internal/runtime/atomic", "Xchgint64"}: struct{}{}, {"mips64", "internal/runtime/atomic", "Xchguintptr"}: struct{}{}, {"mips64", "internal/runtime/math", "Add64"}: struct{}{}, - {"mips64", "internal/runtime/math", "Mul64"}: struct{}{}, {"mips64", "internal/runtime/math", "MulUintptr"}: struct{}{}, {"mips64", "internal/runtime/sys", "GetCallerPC"}: struct{}{}, {"mips64", "internal/runtime/sys", "GetCallerSP"}: struct{}{}, @@ -634,8 +642,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mips64", "runtime", "KeepAlive"}: struct{}{}, {"mips64", "runtime", "publicationBarrier"}: struct{}{}, {"mips64", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"mips64", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"mips64", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"mips64", "sync/atomic", "AddInt32"}: struct{}{}, {"mips64", "sync/atomic", "AddInt64"}: struct{}{}, {"mips64", "sync/atomic", "AddUint32"}: struct{}{}, @@ -662,6 +668,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mips64", "sync/atomic", "SwapUint32"}: struct{}{}, {"mips64", "sync/atomic", "SwapUint64"}: struct{}{}, {"mips64", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"mips64", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"mips64le", "internal/runtime/atomic", "And"}: struct{}{}, {"mips64le", "internal/runtime/atomic", "And8"}: struct{}{}, {"mips64le", "internal/runtime/atomic", "Cas"}: struct{}{}, @@ -705,7 +712,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mips64le", "internal/runtime/atomic", "Xchgint64"}: struct{}{}, {"mips64le", "internal/runtime/atomic", "Xchguintptr"}: struct{}{}, {"mips64le", "internal/runtime/math", "Add64"}: struct{}{}, - {"mips64le", "internal/runtime/math", "Mul64"}: struct{}{}, {"mips64le", "internal/runtime/math", "MulUintptr"}: struct{}{}, {"mips64le", "internal/runtime/sys", "GetCallerPC"}: struct{}{}, {"mips64le", "internal/runtime/sys", "GetCallerSP"}: struct{}{}, @@ -722,8 +728,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mips64le", "runtime", "KeepAlive"}: struct{}{}, {"mips64le", "runtime", "publicationBarrier"}: struct{}{}, {"mips64le", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"mips64le", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"mips64le", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"mips64le", "sync/atomic", "AddInt32"}: struct{}{}, {"mips64le", "sync/atomic", "AddInt64"}: struct{}{}, {"mips64le", "sync/atomic", "AddUint32"}: struct{}{}, @@ -750,6 +754,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mips64le", "sync/atomic", "SwapUint32"}: struct{}{}, {"mips64le", "sync/atomic", "SwapUint64"}: struct{}{}, {"mips64le", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"mips64le", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"mipsle", "internal/runtime/atomic", "And"}: struct{}{}, {"mipsle", "internal/runtime/atomic", "And8"}: struct{}{}, {"mipsle", "internal/runtime/atomic", "Cas"}: struct{}{}, @@ -795,6 +800,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mipsle", "math/bits", "Len32"}: struct{}{}, {"mipsle", "math/bits", "Len64"}: struct{}{}, {"mipsle", "math/bits", "Len8"}: struct{}{}, + {"mipsle", "math/bits", "Mul64"}: struct{}{}, {"mipsle", "math/bits", "TrailingZeros16"}: struct{}{}, {"mipsle", "math/bits", "TrailingZeros32"}: struct{}{}, {"mipsle", "math/bits", "TrailingZeros64"}: struct{}{}, @@ -802,8 +808,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mipsle", "runtime", "KeepAlive"}: struct{}{}, {"mipsle", "runtime", "publicationBarrier"}: struct{}{}, {"mipsle", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"mipsle", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"mipsle", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"mipsle", "sync/atomic", "AddInt32"}: struct{}{}, {"mipsle", "sync/atomic", "AddUint32"}: struct{}{}, {"mipsle", "sync/atomic", "AddUintptr"}: struct{}{}, @@ -820,6 +824,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"mipsle", "sync/atomic", "SwapInt32"}: struct{}{}, {"mipsle", "sync/atomic", "SwapUint32"}: struct{}{}, {"mipsle", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"mipsle", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"ppc64", "internal/runtime/atomic", "And"}: struct{}{}, {"ppc64", "internal/runtime/atomic", "And8"}: struct{}{}, {"ppc64", "internal/runtime/atomic", "Cas"}: struct{}{}, @@ -863,7 +868,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"ppc64", "internal/runtime/atomic", "Xchgint64"}: struct{}{}, {"ppc64", "internal/runtime/atomic", "Xchguintptr"}: struct{}{}, {"ppc64", "internal/runtime/math", "Add64"}: struct{}{}, - {"ppc64", "internal/runtime/math", "Mul64"}: struct{}{}, {"ppc64", "internal/runtime/math", "MulUintptr"}: struct{}{}, {"ppc64", "internal/runtime/sys", "Bswap32"}: struct{}{}, {"ppc64", "internal/runtime/sys", "Bswap64"}: struct{}{}, @@ -916,8 +920,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"ppc64", "runtime", "KeepAlive"}: struct{}{}, {"ppc64", "runtime", "publicationBarrier"}: struct{}{}, {"ppc64", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"ppc64", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"ppc64", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"ppc64", "sync/atomic", "AddInt32"}: struct{}{}, {"ppc64", "sync/atomic", "AddInt64"}: struct{}{}, {"ppc64", "sync/atomic", "AddUint32"}: struct{}{}, @@ -944,6 +946,8 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"ppc64", "sync/atomic", "SwapUint32"}: struct{}{}, {"ppc64", "sync/atomic", "SwapUint64"}: struct{}{}, {"ppc64", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"ppc64", "crypto/internal/constanttime", "Select"}: struct{}{}, + {"ppc64", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"ppc64le", "internal/runtime/atomic", "And"}: struct{}{}, {"ppc64le", "internal/runtime/atomic", "And8"}: struct{}{}, {"ppc64le", "internal/runtime/atomic", "Cas"}: struct{}{}, @@ -987,7 +991,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"ppc64le", "internal/runtime/atomic", "Xchgint64"}: struct{}{}, {"ppc64le", "internal/runtime/atomic", "Xchguintptr"}: struct{}{}, {"ppc64le", "internal/runtime/math", "Add64"}: struct{}{}, - {"ppc64le", "internal/runtime/math", "Mul64"}: struct{}{}, {"ppc64le", "internal/runtime/math", "MulUintptr"}: struct{}{}, {"ppc64le", "internal/runtime/sys", "Bswap32"}: struct{}{}, {"ppc64le", "internal/runtime/sys", "Bswap64"}: struct{}{}, @@ -1040,8 +1043,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"ppc64le", "runtime", "KeepAlive"}: struct{}{}, {"ppc64le", "runtime", "publicationBarrier"}: struct{}{}, {"ppc64le", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"ppc64le", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"ppc64le", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"ppc64le", "sync/atomic", "AddInt32"}: struct{}{}, {"ppc64le", "sync/atomic", "AddInt64"}: struct{}{}, {"ppc64le", "sync/atomic", "AddUint32"}: struct{}{}, @@ -1068,6 +1069,8 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"ppc64le", "sync/atomic", "SwapUint32"}: struct{}{}, {"ppc64le", "sync/atomic", "SwapUint64"}: struct{}{}, {"ppc64le", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"ppc64le", "crypto/internal/constanttime", "Select"}: struct{}{}, + {"ppc64le", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"riscv64", "internal/runtime/atomic", "And"}: struct{}{}, {"riscv64", "internal/runtime/atomic", "And8"}: struct{}{}, {"riscv64", "internal/runtime/atomic", "Cas"}: struct{}{}, @@ -1111,7 +1114,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"riscv64", "internal/runtime/atomic", "Xchgint64"}: struct{}{}, {"riscv64", "internal/runtime/atomic", "Xchguintptr"}: struct{}{}, {"riscv64", "internal/runtime/math", "Add64"}: struct{}{}, - {"riscv64", "internal/runtime/math", "Mul64"}: struct{}{}, {"riscv64", "internal/runtime/math", "MulUintptr"}: struct{}{}, {"riscv64", "internal/runtime/sys", "Bswap32"}: struct{}{}, {"riscv64", "internal/runtime/sys", "Bswap64"}: struct{}{}, @@ -1160,8 +1162,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"riscv64", "runtime", "KeepAlive"}: struct{}{}, {"riscv64", "runtime", "publicationBarrier"}: struct{}{}, {"riscv64", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"riscv64", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"riscv64", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"riscv64", "sync/atomic", "AddInt32"}: struct{}{}, {"riscv64", "sync/atomic", "AddInt64"}: struct{}{}, {"riscv64", "sync/atomic", "AddUint32"}: struct{}{}, @@ -1188,6 +1188,8 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"riscv64", "sync/atomic", "SwapUint32"}: struct{}{}, {"riscv64", "sync/atomic", "SwapUint64"}: struct{}{}, {"riscv64", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"riscv64", "crypto/internal/constanttime", "Select"}: struct{}{}, + {"riscv64", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"s390x", "internal/runtime/atomic", "And"}: struct{}{}, {"s390x", "internal/runtime/atomic", "And8"}: struct{}{}, {"s390x", "internal/runtime/atomic", "Cas"}: struct{}{}, @@ -1231,7 +1233,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"s390x", "internal/runtime/atomic", "Xchgint64"}: struct{}{}, {"s390x", "internal/runtime/atomic", "Xchguintptr"}: struct{}{}, {"s390x", "internal/runtime/math", "Add64"}: struct{}{}, - {"s390x", "internal/runtime/math", "Mul64"}: struct{}{}, {"s390x", "internal/runtime/sys", "Bswap32"}: struct{}{}, {"s390x", "internal/runtime/sys", "Bswap64"}: struct{}{}, {"s390x", "internal/runtime/sys", "GetCallerPC"}: struct{}{}, @@ -1278,8 +1279,6 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"s390x", "math/bits", "TrailingZeros8"}: struct{}{}, {"s390x", "runtime", "KeepAlive"}: struct{}{}, {"s390x", "runtime", "slicebytetostringtmp"}: struct{}{}, - {"s390x", "sync", "runtime_LoadAcquintptr"}: struct{}{}, - {"s390x", "sync", "runtime_StoreReluintptr"}: struct{}{}, {"s390x", "sync/atomic", "AddInt32"}: struct{}{}, {"s390x", "sync/atomic", "AddInt64"}: struct{}{}, {"s390x", "sync/atomic", "AddUint32"}: struct{}{}, @@ -1306,6 +1305,7 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"s390x", "sync/atomic", "SwapUint32"}: struct{}{}, {"s390x", "sync/atomic", "SwapUint64"}: struct{}{}, {"s390x", "sync/atomic", "SwapUintptr"}: struct{}{}, + {"s390x", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, {"wasm", "internal/runtime/sys", "GetCallerPC"}: struct{}{}, {"wasm", "internal/runtime/sys", "GetCallerSP"}: struct{}{}, {"wasm", "internal/runtime/sys", "GetClosurePtr"}: struct{}{}, @@ -1322,11 +1322,14 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"wasm", "math", "RoundToEven"}: struct{}{}, {"wasm", "math", "Trunc"}: struct{}{}, {"wasm", "math", "sqrt"}: struct{}{}, + {"wasm", "math/big", "mulWW"}: struct{}{}, {"wasm", "math/bits", "Len"}: struct{}{}, {"wasm", "math/bits", "Len16"}: struct{}{}, {"wasm", "math/bits", "Len32"}: struct{}{}, {"wasm", "math/bits", "Len64"}: struct{}{}, {"wasm", "math/bits", "Len8"}: struct{}{}, + {"wasm", "math/bits", "Mul"}: struct{}{}, + {"wasm", "math/bits", "Mul64"}: struct{}{}, {"wasm", "math/bits", "OnesCount"}: struct{}{}, {"wasm", "math/bits", "OnesCount16"}: struct{}{}, {"wasm", "math/bits", "OnesCount32"}: struct{}{}, @@ -1341,6 +1344,8 @@ var wantIntrinsics = map[testIntrinsicKey]struct{}{ {"wasm", "math/bits", "TrailingZeros8"}: struct{}{}, {"wasm", "runtime", "KeepAlive"}: struct{}{}, {"wasm", "runtime", "slicebytetostringtmp"}: struct{}{}, + {"wasm", "crypto/internal/constanttime", "Select"}: struct{}{}, + {"wasm", "crypto/internal/constanttime", "boolToUint8"}: struct{}{}, } func TestIntrinsics(t *testing.T) { @@ -1375,13 +1380,13 @@ func TestIntrinsics(t *testing.T) { gotIntrinsics[testIntrinsicKey{ik.arch.Name, ik.pkg, ik.fn}] = struct{}{} } for ik, _ := range gotIntrinsics { - if _, found := wantIntrinsics[ik]; !found { + if _, found := wantIntrinsics[ik]; !found && (ik.pkg != "simd/archsimd" || *simd) { t.Errorf("Got unwanted intrinsic %v %v.%v", ik.archName, ik.pkg, ik.fn) } } for ik, _ := range wantIntrinsics { - if _, found := gotIntrinsics[ik]; !found { + if _, found := gotIntrinsics[ik]; !found && (ik.pkg != "simd/archsimd" || *simd) { t.Errorf("Want missing intrinsic %v %v.%v", ik.archName, ik.pkg, ik.fn) } } diff --git a/src/cmd/compile/internal/ssagen/phi.go b/src/cmd/compile/internal/ssagen/phi.go index 0dcf353bf43089..4043ac457648e1 100644 --- a/src/cmd/compile/internal/ssagen/phi.go +++ b/src/cmd/compile/internal/ssagen/phi.go @@ -396,11 +396,11 @@ type blockHeap struct { func (h *blockHeap) Len() int { return len(h.a) } func (h *blockHeap) Swap(i, j int) { a := h.a; a[i], a[j] = a[j], a[i] } -func (h *blockHeap) Push(x interface{}) { +func (h *blockHeap) Push(x any) { v := x.(*ssa.Block) h.a = append(h.a, v) } -func (h *blockHeap) Pop() interface{} { +func (h *blockHeap) Pop() any { old := h.a n := len(old) x := old[n-1] diff --git a/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go b/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go new file mode 100644 index 00000000000000..c133f2dea7d38d --- /dev/null +++ b/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go @@ -0,0 +1,1879 @@ +// Code generated by 'simdgen -o godefs -goroot $GOROOT -arch amd64 -xedPath $XED_PATH go_amd64.yaml types.yaml categories.yaml'; DO NOT EDIT. +package ssagen + +import ( + "cmd/compile/internal/ir" + "cmd/compile/internal/ssa" + "cmd/compile/internal/types" + "cmd/internal/sys" +) + +func simdAMD64Intrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies ...sys.ArchFamily)) { + + addF(simdPackage, "Uint8x16.AESDecryptLastRound", opLen2(ssa.OpAESDecryptLastRoundUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.AESDecryptLastRound", opLen2(ssa.OpAESDecryptLastRoundUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.AESDecryptLastRound", opLen2(ssa.OpAESDecryptLastRoundUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.AESDecryptOneRound", opLen2(ssa.OpAESDecryptOneRoundUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.AESDecryptOneRound", opLen2(ssa.OpAESDecryptOneRoundUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.AESDecryptOneRound", opLen2(ssa.OpAESDecryptOneRoundUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.AESEncryptLastRound", opLen2(ssa.OpAESEncryptLastRoundUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.AESEncryptLastRound", opLen2(ssa.OpAESEncryptLastRoundUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.AESEncryptLastRound", opLen2(ssa.OpAESEncryptLastRoundUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.AESEncryptOneRound", opLen2(ssa.OpAESEncryptOneRoundUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.AESEncryptOneRound", opLen2(ssa.OpAESEncryptOneRoundUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.AESEncryptOneRound", opLen2(ssa.OpAESEncryptOneRoundUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.AESInvMixColumns", opLen1(ssa.OpAESInvMixColumnsUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.AESRoundKeyGenAssist", opLen1Imm8(ssa.OpAESRoundKeyGenAssistUint32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int8x16.Abs", opLen1(ssa.OpAbsInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Abs", opLen1(ssa.OpAbsInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Abs", opLen1(ssa.OpAbsInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Abs", opLen1(ssa.OpAbsInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Abs", opLen1(ssa.OpAbsInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Abs", opLen1(ssa.OpAbsInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Abs", opLen1(ssa.OpAbsInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Abs", opLen1(ssa.OpAbsInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Abs", opLen1(ssa.OpAbsInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Abs", opLen1(ssa.OpAbsInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Abs", opLen1(ssa.OpAbsInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Abs", opLen1(ssa.OpAbsInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Add", opLen2(ssa.OpAddFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Add", opLen2(ssa.OpAddFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Add", opLen2(ssa.OpAddFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Add", opLen2(ssa.OpAddFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Add", opLen2(ssa.OpAddFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Add", opLen2(ssa.OpAddFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.Add", opLen2(ssa.OpAddInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Add", opLen2(ssa.OpAddInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Add", opLen2(ssa.OpAddInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Add", opLen2(ssa.OpAddInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Add", opLen2(ssa.OpAddInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Add", opLen2(ssa.OpAddInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Add", opLen2(ssa.OpAddInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Add", opLen2(ssa.OpAddInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Add", opLen2(ssa.OpAddInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Add", opLen2(ssa.OpAddInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Add", opLen2(ssa.OpAddInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Add", opLen2(ssa.OpAddInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.Add", opLen2(ssa.OpAddUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.Add", opLen2(ssa.OpAddUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.Add", opLen2(ssa.OpAddUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Add", opLen2(ssa.OpAddUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Add", opLen2(ssa.OpAddUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Add", opLen2(ssa.OpAddUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.Add", opLen2(ssa.OpAddUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.Add", opLen2(ssa.OpAddUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.Add", opLen2(ssa.OpAddUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.Add", opLen2(ssa.OpAddUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.Add", opLen2(ssa.OpAddUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.Add", opLen2(ssa.OpAddUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.AddOddSubEven", opLen2(ssa.OpAddOddSubEvenFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.AddOddSubEven", opLen2(ssa.OpAddOddSubEvenFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x2.AddOddSubEven", opLen2(ssa.OpAddOddSubEvenFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.AddOddSubEven", opLen2(ssa.OpAddOddSubEvenFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x16.AddSaturated", opLen2(ssa.OpAddSaturatedInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.AddSaturated", opLen2(ssa.OpAddSaturatedInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.AddSaturated", opLen2(ssa.OpAddSaturatedInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.AddSaturated", opLen2(ssa.OpAddSaturatedInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.AddSaturated", opLen2(ssa.OpAddSaturatedInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.AddSaturated", opLen2(ssa.OpAddSaturatedInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.AddSaturated", opLen2(ssa.OpAddSaturatedUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.AddSaturated", opLen2(ssa.OpAddSaturatedUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.AddSaturated", opLen2(ssa.OpAddSaturatedUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.AddSaturated", opLen2(ssa.OpAddSaturatedUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.AddSaturated", opLen2(ssa.OpAddSaturatedUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.AddSaturated", opLen2(ssa.OpAddSaturatedUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.And", opLen2(ssa.OpAndInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.And", opLen2(ssa.OpAndInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.And", opLen2(ssa.OpAndInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.And", opLen2(ssa.OpAndInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.And", opLen2(ssa.OpAndInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.And", opLen2(ssa.OpAndInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.And", opLen2(ssa.OpAndInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.And", opLen2(ssa.OpAndInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.And", opLen2(ssa.OpAndInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.And", opLen2(ssa.OpAndInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.And", opLen2(ssa.OpAndInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.And", opLen2(ssa.OpAndUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.And", opLen2(ssa.OpAndUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.And", opLen2(ssa.OpAndUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.And", opLen2(ssa.OpAndUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.And", opLen2(ssa.OpAndUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.And", opLen2(ssa.OpAndUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.And", opLen2(ssa.OpAndUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.And", opLen2(ssa.OpAndUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.And", opLen2(ssa.OpAndUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x4.And", opLen2(ssa.OpAndUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.And", opLen2(ssa.OpAndUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.And", opLen2(ssa.OpAndUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x16.AndNot", opLen2_21(ssa.OpAndNotInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.AndNot", opLen2_21(ssa.OpAndNotInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.AndNot", opLen2_21(ssa.OpAndNotInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.AndNot", opLen2_21(ssa.OpAndNotInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.AndNot", opLen2_21(ssa.OpAndNotInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.AndNot", opLen2_21(ssa.OpAndNotInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.AndNot", opLen2_21(ssa.OpAndNotInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.AndNot", opLen2_21(ssa.OpAndNotInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.AndNot", opLen2_21(ssa.OpAndNotInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.AndNot", opLen2_21(ssa.OpAndNotInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.AndNot", opLen2_21(ssa.OpAndNotInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.AndNot", opLen2_21(ssa.OpAndNotInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.AndNot", opLen2_21(ssa.OpAndNotUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.AndNot", opLen2_21(ssa.OpAndNotUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.AndNot", opLen2_21(ssa.OpAndNotUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.AndNot", opLen2_21(ssa.OpAndNotUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.AndNot", opLen2_21(ssa.OpAndNotUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.AndNot", opLen2_21(ssa.OpAndNotUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.AndNot", opLen2_21(ssa.OpAndNotUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.AndNot", opLen2_21(ssa.OpAndNotUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.AndNot", opLen2_21(ssa.OpAndNotUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x4.AndNot", opLen2_21(ssa.OpAndNotUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.AndNot", opLen2_21(ssa.OpAndNotUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.AndNot", opLen2_21(ssa.OpAndNotUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x16.Average", opLen2(ssa.OpAverageUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.Average", opLen2(ssa.OpAverageUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.Average", opLen2(ssa.OpAverageUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Average", opLen2(ssa.OpAverageUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Average", opLen2(ssa.OpAverageUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Average", opLen2(ssa.OpAverageUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Ceil", opLen1(ssa.OpCeilFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Ceil", opLen1(ssa.OpCeilFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x2.Ceil", opLen1(ssa.OpCeilFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Ceil", opLen1(ssa.OpCeilFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.CeilScaled", opLen1Imm8(ssa.OpCeilScaledFloat32x4, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float32x8.CeilScaled", opLen1Imm8(ssa.OpCeilScaledFloat32x8, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float32x16.CeilScaled", opLen1Imm8(ssa.OpCeilScaledFloat32x16, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float64x2.CeilScaled", opLen1Imm8(ssa.OpCeilScaledFloat64x2, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float64x4.CeilScaled", opLen1Imm8(ssa.OpCeilScaledFloat64x4, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float64x8.CeilScaled", opLen1Imm8(ssa.OpCeilScaledFloat64x8, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float32x4.CeilScaledResidue", opLen1Imm8(ssa.OpCeilScaledResidueFloat32x4, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float32x8.CeilScaledResidue", opLen1Imm8(ssa.OpCeilScaledResidueFloat32x8, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float32x16.CeilScaledResidue", opLen1Imm8(ssa.OpCeilScaledResidueFloat32x16, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float64x2.CeilScaledResidue", opLen1Imm8(ssa.OpCeilScaledResidueFloat64x2, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float64x4.CeilScaledResidue", opLen1Imm8(ssa.OpCeilScaledResidueFloat64x4, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float64x8.CeilScaledResidue", opLen1Imm8(ssa.OpCeilScaledResidueFloat64x8, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float32x4.Compress", opLen2(ssa.OpCompressFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Compress", opLen2(ssa.OpCompressFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Compress", opLen2(ssa.OpCompressFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Compress", opLen2(ssa.OpCompressFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Compress", opLen2(ssa.OpCompressFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Compress", opLen2(ssa.OpCompressFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.Compress", opLen2(ssa.OpCompressInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Compress", opLen2(ssa.OpCompressInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Compress", opLen2(ssa.OpCompressInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Compress", opLen2(ssa.OpCompressInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Compress", opLen2(ssa.OpCompressInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Compress", opLen2(ssa.OpCompressInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Compress", opLen2(ssa.OpCompressInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Compress", opLen2(ssa.OpCompressInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Compress", opLen2(ssa.OpCompressInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Compress", opLen2(ssa.OpCompressInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Compress", opLen2(ssa.OpCompressInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Compress", opLen2(ssa.OpCompressInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.Compress", opLen2(ssa.OpCompressUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.Compress", opLen2(ssa.OpCompressUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.Compress", opLen2(ssa.OpCompressUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Compress", opLen2(ssa.OpCompressUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Compress", opLen2(ssa.OpCompressUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Compress", opLen2(ssa.OpCompressUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.Compress", opLen2(ssa.OpCompressUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.Compress", opLen2(ssa.OpCompressUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.Compress", opLen2(ssa.OpCompressUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.Compress", opLen2(ssa.OpCompressUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.Compress", opLen2(ssa.OpCompressUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.Compress", opLen2(ssa.OpCompressUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x2.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x8.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x8.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.ConcatAddPairsGrouped", opLen2(ssa.OpConcatAddPairsGroupedFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x4.ConcatAddPairsGrouped", opLen2(ssa.OpConcatAddPairsGroupedFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x16.ConcatAddPairsGrouped", opLen2(ssa.OpConcatAddPairsGroupedInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x8.ConcatAddPairsGrouped", opLen2(ssa.OpConcatAddPairsGroupedInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x16.ConcatAddPairsGrouped", opLen2(ssa.OpConcatAddPairsGroupedUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x8.ConcatAddPairsGrouped", opLen2(ssa.OpConcatAddPairsGroupedUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x8.ConcatAddPairsSaturated", opLen2(ssa.OpConcatAddPairsSaturatedInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.ConcatAddPairsSaturatedGrouped", opLen2(ssa.OpConcatAddPairsSaturatedGroupedInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x16.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x16.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x32.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x64.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x8.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x16.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x32.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.ConcatPermute", opLen3_231(ssa.OpConcatPermuteFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.ConcatPermute", opLen3_231(ssa.OpConcatPermuteFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x8.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x8.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.ConcatPermute", opLen3_231(ssa.OpConcatPermuteFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x16.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x16.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.ConcatPermute", opLen3_231(ssa.OpConcatPermuteFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x2.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x2.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ConcatPermute", opLen3_231(ssa.OpConcatPermuteFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x4.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x4.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.ConcatPermute", opLen3_231(ssa.OpConcatPermuteFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x8.ConcatPermute", opLen3_231(ssa.OpConcatPermuteInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x8.ConcatPermute", opLen3_231(ssa.OpConcatPermuteUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x8.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsFloat32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Float64x4.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsFloat64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int8x32.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsInt8x32, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int16x16.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsInt16x16, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int32x8.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsInt32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int64x4.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsInt64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint8x32.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsUint8x32, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint16x16.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsUint16x16, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint32x8.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsUint32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint64x4.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsUint64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint8x16.ConcatShiftBytesRight", opLen2Imm8_2I(ssa.OpConcatShiftBytesRightUint8x16, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint8x32.ConcatShiftBytesRightGrouped", opLen2Imm8_2I(ssa.OpConcatShiftBytesRightGroupedUint8x32, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint8x64.ConcatShiftBytesRightGrouped", opLen2Imm8_2I(ssa.OpConcatShiftBytesRightGroupedUint8x64, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Float32x4.ConcatSubPairs", opLen2(ssa.OpConcatSubPairsFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x2.ConcatSubPairs", opLen2(ssa.OpConcatSubPairsFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x8.ConcatSubPairs", opLen2(ssa.OpConcatSubPairsInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.ConcatSubPairs", opLen2(ssa.OpConcatSubPairsInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x8.ConcatSubPairs", opLen2(ssa.OpConcatSubPairsUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.ConcatSubPairs", opLen2(ssa.OpConcatSubPairsUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.ConcatSubPairsGrouped", opLen2(ssa.OpConcatSubPairsGroupedFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x4.ConcatSubPairsGrouped", opLen2(ssa.OpConcatSubPairsGroupedFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x16.ConcatSubPairsGrouped", opLen2(ssa.OpConcatSubPairsGroupedInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x8.ConcatSubPairsGrouped", opLen2(ssa.OpConcatSubPairsGroupedInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x16.ConcatSubPairsGrouped", opLen2(ssa.OpConcatSubPairsGroupedUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x8.ConcatSubPairsGrouped", opLen2(ssa.OpConcatSubPairsGroupedUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x8.ConcatSubPairsSaturated", opLen2(ssa.OpConcatSubPairsSaturatedInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.ConcatSubPairsSaturatedGrouped", opLen2(ssa.OpConcatSubPairsSaturatedGroupedInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Float64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Float64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Float64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Float32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Float32x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int32x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint32x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x8.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x8.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float32x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x8.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x8.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float32x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Div", opLen2(ssa.OpDivFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Div", opLen2(ssa.OpDivFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Div", opLen2(ssa.OpDivFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Div", opLen2(ssa.OpDivFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Div", opLen2(ssa.OpDivFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Div", opLen2(ssa.OpDivFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.DotProductPairs", opLen2(ssa.OpDotProductPairsInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.DotProductPairs", opLen2(ssa.OpDotProductPairsInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.DotProductPairs", opLen2(ssa.OpDotProductPairsInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.DotProductPairsSaturated", opLen2(ssa.OpDotProductPairsSaturatedUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.DotProductPairsSaturated", opLen2(ssa.OpDotProductPairsSaturatedUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.DotProductPairsSaturated", opLen2(ssa.OpDotProductPairsSaturatedUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.Equal", opLen2(ssa.OpEqualInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Equal", opLen2(ssa.OpEqualInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Equal", opLen2(ssa.OpEqualInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Equal", opLen2(ssa.OpEqualInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Equal", opLen2(ssa.OpEqualInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Equal", opLen2(ssa.OpEqualInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Equal", opLen2(ssa.OpEqualInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Equal", opLen2(ssa.OpEqualInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Equal", opLen2(ssa.OpEqualInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Equal", opLen2(ssa.OpEqualInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Equal", opLen2(ssa.OpEqualInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Equal", opLen2(ssa.OpEqualInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.Equal", opLen2(ssa.OpEqualUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.Equal", opLen2(ssa.OpEqualUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.Equal", opLen2(ssa.OpEqualUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Equal", opLen2(ssa.OpEqualUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Equal", opLen2(ssa.OpEqualUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Equal", opLen2(ssa.OpEqualUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.Equal", opLen2(ssa.OpEqualUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.Equal", opLen2(ssa.OpEqualUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.Equal", opLen2(ssa.OpEqualUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.Equal", opLen2(ssa.OpEqualUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.Equal", opLen2(ssa.OpEqualUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.Equal", opLen2(ssa.OpEqualUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Equal", opLen2(ssa.OpEqualFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Equal", opLen2(ssa.OpEqualFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Equal", opLen2(ssa.OpEqualFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Equal", opLen2(ssa.OpEqualFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Equal", opLen2(ssa.OpEqualFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Equal", opLen2(ssa.OpEqualFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Expand", opLen2(ssa.OpExpandFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Expand", opLen2(ssa.OpExpandFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Expand", opLen2(ssa.OpExpandFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Expand", opLen2(ssa.OpExpandFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Expand", opLen2(ssa.OpExpandFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Expand", opLen2(ssa.OpExpandFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.Expand", opLen2(ssa.OpExpandInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Expand", opLen2(ssa.OpExpandInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Expand", opLen2(ssa.OpExpandInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Expand", opLen2(ssa.OpExpandInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Expand", opLen2(ssa.OpExpandInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Expand", opLen2(ssa.OpExpandInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Expand", opLen2(ssa.OpExpandInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Expand", opLen2(ssa.OpExpandInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Expand", opLen2(ssa.OpExpandInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Expand", opLen2(ssa.OpExpandInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Expand", opLen2(ssa.OpExpandInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Expand", opLen2(ssa.OpExpandInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.Expand", opLen2(ssa.OpExpandUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.Expand", opLen2(ssa.OpExpandUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.Expand", opLen2(ssa.OpExpandUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Expand", opLen2(ssa.OpExpandUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Expand", opLen2(ssa.OpExpandUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Expand", opLen2(ssa.OpExpandUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.Expand", opLen2(ssa.OpExpandUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.Expand", opLen2(ssa.OpExpandUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.Expand", opLen2(ssa.OpExpandUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.Expand", opLen2(ssa.OpExpandUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.Expand", opLen2(ssa.OpExpandUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.Expand", opLen2(ssa.OpExpandUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.ExtendLo2ToInt64", opLen1(ssa.OpExtendLo2ToInt64Int8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x8.ExtendLo2ToInt64", opLen1(ssa.OpExtendLo2ToInt64Int16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.ExtendLo2ToInt64", opLen1(ssa.OpExtendLo2ToInt64Int32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x16.ExtendLo2ToUint64", opLen1(ssa.OpExtendLo2ToUint64Uint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x8.ExtendLo2ToUint64", opLen1(ssa.OpExtendLo2ToUint64Uint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.ExtendLo2ToUint64", opLen1(ssa.OpExtendLo2ToUint64Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x16.ExtendLo4ToInt32", opLen1(ssa.OpExtendLo4ToInt32Int8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x8.ExtendLo4ToInt32", opLen1(ssa.OpExtendLo4ToInt32Int16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x16.ExtendLo4ToInt64", opLen1(ssa.OpExtendLo4ToInt64Int8x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x8.ExtendLo4ToInt64", opLen1(ssa.OpExtendLo4ToInt64Int16x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x16.ExtendLo4ToUint32", opLen1(ssa.OpExtendLo4ToUint32Uint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x8.ExtendLo4ToUint32", opLen1(ssa.OpExtendLo4ToUint32Uint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x16.ExtendLo4ToUint64", opLen1(ssa.OpExtendLo4ToUint64Uint8x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x8.ExtendLo4ToUint64", opLen1(ssa.OpExtendLo4ToUint64Uint16x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x16.ExtendLo8ToInt16", opLen1(ssa.OpExtendLo8ToInt16Int8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x16.ExtendLo8ToInt32", opLen1(ssa.OpExtendLo8ToInt32Int8x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x16.ExtendLo8ToInt64", opLen1(ssa.OpExtendLo8ToInt64Int8x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.ExtendLo8ToUint16", opLen1(ssa.OpExtendLo8ToUint16Uint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x16.ExtendLo8ToUint32", opLen1(ssa.OpExtendLo8ToUint32Uint8x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x16.ExtendLo8ToUint64", opLen1(ssa.OpExtendLo8ToUint64Uint8x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.ExtendToInt16", opLen1(ssa.OpExtendToInt16Int8x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x32.ExtendToInt16", opLen1(ssa.OpExtendToInt16Int8x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.ExtendToInt32", opLen1(ssa.OpExtendToInt32Int8x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.ExtendToInt32", opLen1(ssa.OpExtendToInt32Int16x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x16.ExtendToInt32", opLen1(ssa.OpExtendToInt32Int16x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.ExtendToInt64", opLen1(ssa.OpExtendToInt64Int16x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.ExtendToInt64", opLen1(ssa.OpExtendToInt64Int32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x8.ExtendToInt64", opLen1(ssa.OpExtendToInt64Int32x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.ExtendToUint16", opLen1(ssa.OpExtendToUint16Uint8x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x32.ExtendToUint16", opLen1(ssa.OpExtendToUint16Uint8x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.ExtendToUint32", opLen1(ssa.OpExtendToUint32Uint8x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.ExtendToUint32", opLen1(ssa.OpExtendToUint32Uint16x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x16.ExtendToUint32", opLen1(ssa.OpExtendToUint32Uint16x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.ExtendToUint64", opLen1(ssa.OpExtendToUint64Uint16x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.ExtendToUint64", opLen1(ssa.OpExtendToUint64Uint32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x8.ExtendToUint64", opLen1(ssa.OpExtendToUint64Uint32x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Floor", opLen1(ssa.OpFloorFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Floor", opLen1(ssa.OpFloorFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x2.Floor", opLen1(ssa.OpFloorFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Floor", opLen1(ssa.OpFloorFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.FloorScaled", opLen1Imm8(ssa.OpFloorScaledFloat32x4, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float32x8.FloorScaled", opLen1Imm8(ssa.OpFloorScaledFloat32x8, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float32x16.FloorScaled", opLen1Imm8(ssa.OpFloorScaledFloat32x16, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float64x2.FloorScaled", opLen1Imm8(ssa.OpFloorScaledFloat64x2, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float64x4.FloorScaled", opLen1Imm8(ssa.OpFloorScaledFloat64x4, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float64x8.FloorScaled", opLen1Imm8(ssa.OpFloorScaledFloat64x8, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float32x4.FloorScaledResidue", opLen1Imm8(ssa.OpFloorScaledResidueFloat32x4, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float32x8.FloorScaledResidue", opLen1Imm8(ssa.OpFloorScaledResidueFloat32x8, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float32x16.FloorScaledResidue", opLen1Imm8(ssa.OpFloorScaledResidueFloat32x16, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float64x2.FloorScaledResidue", opLen1Imm8(ssa.OpFloorScaledResidueFloat64x2, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float64x4.FloorScaledResidue", opLen1Imm8(ssa.OpFloorScaledResidueFloat64x4, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float64x8.FloorScaledResidue", opLen1Imm8(ssa.OpFloorScaledResidueFloat64x8, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Uint8x16.GaloisFieldAffineTransform", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformUint8x16, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint8x32.GaloisFieldAffineTransform", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformUint8x32, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint8x64.GaloisFieldAffineTransform", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformUint8x64, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint8x16.GaloisFieldAffineTransformInverse", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformInverseUint8x16, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint8x32.GaloisFieldAffineTransformInverse", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformInverseUint8x32, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint8x64.GaloisFieldAffineTransformInverse", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformInverseUint8x64, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint8x16.GaloisFieldMul", opLen2(ssa.OpGaloisFieldMulUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.GaloisFieldMul", opLen2(ssa.OpGaloisFieldMulUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.GaloisFieldMul", opLen2(ssa.OpGaloisFieldMulUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.GetElem", opLen1Imm(ssa.OpGetElemFloat32x4, types.Types[types.TFLOAT32], 0, 3), sys.AMD64) + addF(simdPackage, "Float64x2.GetElem", opLen1Imm(ssa.OpGetElemFloat64x2, types.Types[types.TFLOAT64], 0, 1), sys.AMD64) + addF(simdPackage, "Int8x16.GetElem", opLen1Imm(ssa.OpGetElemInt8x16, types.Types[types.TINT8], 0, 15), sys.AMD64) + addF(simdPackage, "Int16x8.GetElem", opLen1Imm(ssa.OpGetElemInt16x8, types.Types[types.TINT16], 0, 7), sys.AMD64) + addF(simdPackage, "Int32x4.GetElem", opLen1Imm(ssa.OpGetElemInt32x4, types.Types[types.TINT32], 0, 3), sys.AMD64) + addF(simdPackage, "Int64x2.GetElem", opLen1Imm(ssa.OpGetElemInt64x2, types.Types[types.TINT64], 0, 1), sys.AMD64) + addF(simdPackage, "Uint8x16.GetElem", opLen1Imm(ssa.OpGetElemUint8x16, types.Types[types.TUINT8], 0, 15), sys.AMD64) + addF(simdPackage, "Uint16x8.GetElem", opLen1Imm(ssa.OpGetElemUint16x8, types.Types[types.TUINT16], 0, 7), sys.AMD64) + addF(simdPackage, "Uint32x4.GetElem", opLen1Imm(ssa.OpGetElemUint32x4, types.Types[types.TUINT32], 0, 3), sys.AMD64) + addF(simdPackage, "Uint64x2.GetElem", opLen1Imm(ssa.OpGetElemUint64x2, types.Types[types.TUINT64], 0, 1), sys.AMD64) + addF(simdPackage, "Float32x8.GetHi", opLen1(ssa.OpGetHiFloat32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x16.GetHi", opLen1(ssa.OpGetHiFloat32x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x4.GetHi", opLen1(ssa.OpGetHiFloat64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x8.GetHi", opLen1(ssa.OpGetHiFloat64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x32.GetHi", opLen1(ssa.OpGetHiInt8x32, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x64.GetHi", opLen1(ssa.OpGetHiInt8x64, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x16.GetHi", opLen1(ssa.OpGetHiInt16x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x32.GetHi", opLen1(ssa.OpGetHiInt16x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x8.GetHi", opLen1(ssa.OpGetHiInt32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x16.GetHi", opLen1(ssa.OpGetHiInt32x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x4.GetHi", opLen1(ssa.OpGetHiInt64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x8.GetHi", opLen1(ssa.OpGetHiInt64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x32.GetHi", opLen1(ssa.OpGetHiUint8x32, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x64.GetHi", opLen1(ssa.OpGetHiUint8x64, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x16.GetHi", opLen1(ssa.OpGetHiUint16x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x32.GetHi", opLen1(ssa.OpGetHiUint16x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x8.GetHi", opLen1(ssa.OpGetHiUint32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x16.GetHi", opLen1(ssa.OpGetHiUint32x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x4.GetHi", opLen1(ssa.OpGetHiUint64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x8.GetHi", opLen1(ssa.OpGetHiUint64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x8.GetLo", opLen1(ssa.OpGetLoFloat32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x16.GetLo", opLen1(ssa.OpGetLoFloat32x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x4.GetLo", opLen1(ssa.OpGetLoFloat64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x8.GetLo", opLen1(ssa.OpGetLoFloat64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x32.GetLo", opLen1(ssa.OpGetLoInt8x32, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x64.GetLo", opLen1(ssa.OpGetLoInt8x64, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x16.GetLo", opLen1(ssa.OpGetLoInt16x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x32.GetLo", opLen1(ssa.OpGetLoInt16x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x8.GetLo", opLen1(ssa.OpGetLoInt32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x16.GetLo", opLen1(ssa.OpGetLoInt32x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x4.GetLo", opLen1(ssa.OpGetLoInt64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x8.GetLo", opLen1(ssa.OpGetLoInt64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x32.GetLo", opLen1(ssa.OpGetLoUint8x32, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x64.GetLo", opLen1(ssa.OpGetLoUint8x64, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x16.GetLo", opLen1(ssa.OpGetLoUint16x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x32.GetLo", opLen1(ssa.OpGetLoUint16x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x8.GetLo", opLen1(ssa.OpGetLoUint32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x16.GetLo", opLen1(ssa.OpGetLoUint32x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x4.GetLo", opLen1(ssa.OpGetLoUint64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x8.GetLo", opLen1(ssa.OpGetLoUint64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x16.Greater", opLen2(ssa.OpGreaterInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Greater", opLen2(ssa.OpGreaterInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Greater", opLen2(ssa.OpGreaterInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Greater", opLen2(ssa.OpGreaterInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Greater", opLen2(ssa.OpGreaterInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Greater", opLen2(ssa.OpGreaterInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Greater", opLen2(ssa.OpGreaterInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Greater", opLen2(ssa.OpGreaterInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Greater", opLen2(ssa.OpGreaterInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Greater", opLen2(ssa.OpGreaterInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Greater", opLen2(ssa.OpGreaterInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Greater", opLen2(ssa.OpGreaterInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Greater", opLen2(ssa.OpGreaterFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Greater", opLen2(ssa.OpGreaterFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Greater", opLen2(ssa.OpGreaterFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Greater", opLen2(ssa.OpGreaterFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Greater", opLen2(ssa.OpGreaterFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Greater", opLen2(ssa.OpGreaterFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x64.Greater", opLen2(ssa.OpGreaterUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x32.Greater", opLen2(ssa.OpGreaterUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x16.Greater", opLen2(ssa.OpGreaterUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x8.Greater", opLen2(ssa.OpGreaterUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x64.GreaterEqual", opLen2(ssa.OpGreaterEqualInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x32.GreaterEqual", opLen2(ssa.OpGreaterEqualInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x16.GreaterEqual", opLen2(ssa.OpGreaterEqualInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x8.GreaterEqual", opLen2(ssa.OpGreaterEqualInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x64.GreaterEqual", opLen2(ssa.OpGreaterEqualUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x32.GreaterEqual", opLen2(ssa.OpGreaterEqualUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x16.GreaterEqual", opLen2(ssa.OpGreaterEqualUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x8.GreaterEqual", opLen2(ssa.OpGreaterEqualUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.InterleaveHi", opLen2(ssa.OpInterleaveHiInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.InterleaveHi", opLen2(ssa.OpInterleaveHiInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x2.InterleaveHi", opLen2(ssa.OpInterleaveHiInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x8.InterleaveHi", opLen2(ssa.OpInterleaveHiUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.InterleaveHi", opLen2(ssa.OpInterleaveHiUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x2.InterleaveHi", opLen2(ssa.OpInterleaveHiUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x8.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x4.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x16.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x8.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x4.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.InterleaveHiGrouped", opLen2(ssa.OpInterleaveHiGroupedUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.InterleaveLo", opLen2(ssa.OpInterleaveLoInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.InterleaveLo", opLen2(ssa.OpInterleaveLoInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x2.InterleaveLo", opLen2(ssa.OpInterleaveLoInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x8.InterleaveLo", opLen2(ssa.OpInterleaveLoUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.InterleaveLo", opLen2(ssa.OpInterleaveLoUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x2.InterleaveLo", opLen2(ssa.OpInterleaveLoUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x8.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x4.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x16.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x8.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x4.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.InterleaveLoGrouped", opLen2(ssa.OpInterleaveLoGroupedUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.LeadingZeros", opLen1(ssa.OpLeadingZerosInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.LeadingZeros", opLen1(ssa.OpLeadingZerosInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.LeadingZeros", opLen1(ssa.OpLeadingZerosInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.LeadingZeros", opLen1(ssa.OpLeadingZerosInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.LeadingZeros", opLen1(ssa.OpLeadingZerosInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.LeadingZeros", opLen1(ssa.OpLeadingZerosInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.LeadingZeros", opLen1(ssa.OpLeadingZerosUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.LeadingZeros", opLen1(ssa.OpLeadingZerosUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.LeadingZeros", opLen1(ssa.OpLeadingZerosUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.LeadingZeros", opLen1(ssa.OpLeadingZerosUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.LeadingZeros", opLen1(ssa.OpLeadingZerosUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.LeadingZeros", opLen1(ssa.OpLeadingZerosUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Less", opLen2(ssa.OpLessFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Less", opLen2(ssa.OpLessFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Less", opLen2(ssa.OpLessFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Less", opLen2(ssa.OpLessFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Less", opLen2(ssa.OpLessFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Less", opLen2(ssa.OpLessFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x64.Less", opLen2(ssa.OpLessInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x32.Less", opLen2(ssa.OpLessInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x16.Less", opLen2(ssa.OpLessInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x8.Less", opLen2(ssa.OpLessInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x64.Less", opLen2(ssa.OpLessUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x32.Less", opLen2(ssa.OpLessUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x16.Less", opLen2(ssa.OpLessUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x8.Less", opLen2(ssa.OpLessUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.LessEqual", opLen2(ssa.OpLessEqualFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.LessEqual", opLen2(ssa.OpLessEqualFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.LessEqual", opLen2(ssa.OpLessEqualFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.LessEqual", opLen2(ssa.OpLessEqualFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.LessEqual", opLen2(ssa.OpLessEqualFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.LessEqual", opLen2(ssa.OpLessEqualFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x64.LessEqual", opLen2(ssa.OpLessEqualInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x32.LessEqual", opLen2(ssa.OpLessEqualInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x16.LessEqual", opLen2(ssa.OpLessEqualInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x8.LessEqual", opLen2(ssa.OpLessEqualInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x64.LessEqual", opLen2(ssa.OpLessEqualUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x32.LessEqual", opLen2(ssa.OpLessEqualUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x16.LessEqual", opLen2(ssa.OpLessEqualUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x8.LessEqual", opLen2(ssa.OpLessEqualUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Max", opLen2(ssa.OpMaxFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Max", opLen2(ssa.OpMaxFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Max", opLen2(ssa.OpMaxFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Max", opLen2(ssa.OpMaxFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Max", opLen2(ssa.OpMaxFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Max", opLen2(ssa.OpMaxFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.Max", opLen2(ssa.OpMaxInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Max", opLen2(ssa.OpMaxInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Max", opLen2(ssa.OpMaxInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Max", opLen2(ssa.OpMaxInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Max", opLen2(ssa.OpMaxInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Max", opLen2(ssa.OpMaxInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Max", opLen2(ssa.OpMaxInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Max", opLen2(ssa.OpMaxInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Max", opLen2(ssa.OpMaxInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Max", opLen2(ssa.OpMaxInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Max", opLen2(ssa.OpMaxInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Max", opLen2(ssa.OpMaxInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.Max", opLen2(ssa.OpMaxUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.Max", opLen2(ssa.OpMaxUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.Max", opLen2(ssa.OpMaxUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Max", opLen2(ssa.OpMaxUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Max", opLen2(ssa.OpMaxUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Max", opLen2(ssa.OpMaxUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.Max", opLen2(ssa.OpMaxUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.Max", opLen2(ssa.OpMaxUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.Max", opLen2(ssa.OpMaxUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.Max", opLen2(ssa.OpMaxUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.Max", opLen2(ssa.OpMaxUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.Max", opLen2(ssa.OpMaxUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Min", opLen2(ssa.OpMinFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Min", opLen2(ssa.OpMinFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Min", opLen2(ssa.OpMinFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Min", opLen2(ssa.OpMinFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Min", opLen2(ssa.OpMinFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Min", opLen2(ssa.OpMinFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.Min", opLen2(ssa.OpMinInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Min", opLen2(ssa.OpMinInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Min", opLen2(ssa.OpMinInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Min", opLen2(ssa.OpMinInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Min", opLen2(ssa.OpMinInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Min", opLen2(ssa.OpMinInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Min", opLen2(ssa.OpMinInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Min", opLen2(ssa.OpMinInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Min", opLen2(ssa.OpMinInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Min", opLen2(ssa.OpMinInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Min", opLen2(ssa.OpMinInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Min", opLen2(ssa.OpMinInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.Min", opLen2(ssa.OpMinUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.Min", opLen2(ssa.OpMinUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.Min", opLen2(ssa.OpMinUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Min", opLen2(ssa.OpMinUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Min", opLen2(ssa.OpMinUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Min", opLen2(ssa.OpMinUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.Min", opLen2(ssa.OpMinUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.Min", opLen2(ssa.OpMinUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.Min", opLen2(ssa.OpMinUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.Min", opLen2(ssa.OpMinUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.Min", opLen2(ssa.OpMinUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.Min", opLen2(ssa.OpMinUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Mul", opLen2(ssa.OpMulFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Mul", opLen2(ssa.OpMulFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Mul", opLen2(ssa.OpMulFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Mul", opLen2(ssa.OpMulFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Mul", opLen2(ssa.OpMulFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Mul", opLen2(ssa.OpMulFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Mul", opLen2(ssa.OpMulInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Mul", opLen2(ssa.OpMulInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Mul", opLen2(ssa.OpMulInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Mul", opLen2(ssa.OpMulInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Mul", opLen2(ssa.OpMulInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Mul", opLen2(ssa.OpMulInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Mul", opLen2(ssa.OpMulInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Mul", opLen2(ssa.OpMulInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Mul", opLen2(ssa.OpMulInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Mul", opLen2(ssa.OpMulUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Mul", opLen2(ssa.OpMulUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Mul", opLen2(ssa.OpMulUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.Mul", opLen2(ssa.OpMulUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.Mul", opLen2(ssa.OpMulUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.Mul", opLen2(ssa.OpMulUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.Mul", opLen2(ssa.OpMulUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.Mul", opLen2(ssa.OpMulUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.Mul", opLen2(ssa.OpMulUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.MulAdd", opLen3(ssa.OpMulAddFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.MulAdd", opLen3(ssa.OpMulAddFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.MulAdd", opLen3(ssa.OpMulAddFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.MulAdd", opLen3(ssa.OpMulAddFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.MulAdd", opLen3(ssa.OpMulAddFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.MulAdd", opLen3(ssa.OpMulAddFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.MulAddEvenSubOdd", opLen3(ssa.OpMulAddEvenSubOddFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.MulAddEvenSubOdd", opLen3(ssa.OpMulAddEvenSubOddFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.MulAddEvenSubOdd", opLen3(ssa.OpMulAddEvenSubOddFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.MulAddEvenSubOdd", opLen3(ssa.OpMulAddEvenSubOddFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.MulAddEvenSubOdd", opLen3(ssa.OpMulAddEvenSubOddFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.MulAddEvenSubOdd", opLen3(ssa.OpMulAddEvenSubOddFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.MulAddOddSubEven", opLen3(ssa.OpMulAddOddSubEvenFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.MulAddOddSubEven", opLen3(ssa.OpMulAddOddSubEvenFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.MulAddOddSubEven", opLen3(ssa.OpMulAddOddSubEvenFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.MulAddOddSubEven", opLen3(ssa.OpMulAddOddSubEvenFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.MulAddOddSubEven", opLen3(ssa.OpMulAddOddSubEvenFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.MulAddOddSubEven", opLen3(ssa.OpMulAddOddSubEvenFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.MulHigh", opLen2(ssa.OpMulHighInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.MulHigh", opLen2(ssa.OpMulHighInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.MulHigh", opLen2(ssa.OpMulHighInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.MulHigh", opLen2(ssa.OpMulHighUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.MulHigh", opLen2(ssa.OpMulHighUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.MulHigh", opLen2(ssa.OpMulHighUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.MulSign", opLen2(ssa.OpMulSignInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.MulSign", opLen2(ssa.OpMulSignInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x8.MulSign", opLen2(ssa.OpMulSignInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.MulSign", opLen2(ssa.OpMulSignInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x4.MulSign", opLen2(ssa.OpMulSignInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.MulSign", opLen2(ssa.OpMulSignInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x4.MulWidenEven", opLen2(ssa.OpMulWidenEvenInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.MulWidenEven", opLen2(ssa.OpMulWidenEvenInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x4.MulWidenEven", opLen2(ssa.OpMulWidenEvenUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.MulWidenEven", opLen2(ssa.OpMulWidenEvenUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.NotEqual", opLen2(ssa.OpNotEqualFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.NotEqual", opLen2(ssa.OpNotEqualFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.NotEqual", opLen2(ssa.OpNotEqualFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.NotEqual", opLen2(ssa.OpNotEqualFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.NotEqual", opLen2(ssa.OpNotEqualFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.NotEqual", opLen2(ssa.OpNotEqualFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x64.NotEqual", opLen2(ssa.OpNotEqualInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x32.NotEqual", opLen2(ssa.OpNotEqualInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x16.NotEqual", opLen2(ssa.OpNotEqualInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x8.NotEqual", opLen2(ssa.OpNotEqualInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x64.NotEqual", opLen2(ssa.OpNotEqualUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x32.NotEqual", opLen2(ssa.OpNotEqualUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x16.NotEqual", opLen2(ssa.OpNotEqualUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x8.NotEqual", opLen2(ssa.OpNotEqualUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.OnesCount", opLen1(ssa.OpOnesCountInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.OnesCount", opLen1(ssa.OpOnesCountInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.OnesCount", opLen1(ssa.OpOnesCountInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.OnesCount", opLen1(ssa.OpOnesCountInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.OnesCount", opLen1(ssa.OpOnesCountInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.OnesCount", opLen1(ssa.OpOnesCountInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.OnesCount", opLen1(ssa.OpOnesCountInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.OnesCount", opLen1(ssa.OpOnesCountInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.OnesCount", opLen1(ssa.OpOnesCountInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.OnesCount", opLen1(ssa.OpOnesCountInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.OnesCount", opLen1(ssa.OpOnesCountInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.OnesCount", opLen1(ssa.OpOnesCountInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.OnesCount", opLen1(ssa.OpOnesCountUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.OnesCount", opLen1(ssa.OpOnesCountUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.OnesCount", opLen1(ssa.OpOnesCountUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.OnesCount", opLen1(ssa.OpOnesCountUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.OnesCount", opLen1(ssa.OpOnesCountUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.OnesCount", opLen1(ssa.OpOnesCountUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.OnesCount", opLen1(ssa.OpOnesCountUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.OnesCount", opLen1(ssa.OpOnesCountUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.OnesCount", opLen1(ssa.OpOnesCountUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.OnesCount", opLen1(ssa.OpOnesCountUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.OnesCount", opLen1(ssa.OpOnesCountUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.OnesCount", opLen1(ssa.OpOnesCountUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.Or", opLen2(ssa.OpOrInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Or", opLen2(ssa.OpOrInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Or", opLen2(ssa.OpOrInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Or", opLen2(ssa.OpOrInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Or", opLen2(ssa.OpOrInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Or", opLen2(ssa.OpOrInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Or", opLen2(ssa.OpOrInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Or", opLen2(ssa.OpOrInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Or", opLen2(ssa.OpOrInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Or", opLen2(ssa.OpOrInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Or", opLen2(ssa.OpOrInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.Or", opLen2(ssa.OpOrUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.Or", opLen2(ssa.OpOrUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.Or", opLen2(ssa.OpOrUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Or", opLen2(ssa.OpOrUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Or", opLen2(ssa.OpOrUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Or", opLen2(ssa.OpOrUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.Or", opLen2(ssa.OpOrUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.Or", opLen2(ssa.OpOrUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.Or", opLen2(ssa.OpOrUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x4.Or", opLen2(ssa.OpOrUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.Or", opLen2(ssa.OpOrUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.Or", opLen2(ssa.OpOrUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x16.Permute", opLen2_21(ssa.OpPermuteInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x16.Permute", opLen2_21(ssa.OpPermuteUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Permute", opLen2_21(ssa.OpPermuteInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x32.Permute", opLen2_21(ssa.OpPermuteUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Permute", opLen2_21(ssa.OpPermuteInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x64.Permute", opLen2_21(ssa.OpPermuteUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Permute", opLen2_21(ssa.OpPermuteInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x8.Permute", opLen2_21(ssa.OpPermuteUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Permute", opLen2_21(ssa.OpPermuteInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x16.Permute", opLen2_21(ssa.OpPermuteUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Permute", opLen2_21(ssa.OpPermuteInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x32.Permute", opLen2_21(ssa.OpPermuteUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x8.Permute", opLen2_21(ssa.OpPermuteFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x8.Permute", opLen2_21(ssa.OpPermuteInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x8.Permute", opLen2_21(ssa.OpPermuteUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Permute", opLen2_21(ssa.OpPermuteFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x16.Permute", opLen2_21(ssa.OpPermuteInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x16.Permute", opLen2_21(ssa.OpPermuteUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x4.Permute", opLen2_21(ssa.OpPermuteFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x4.Permute", opLen2_21(ssa.OpPermuteInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x4.Permute", opLen2_21(ssa.OpPermuteUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Permute", opLen2_21(ssa.OpPermuteFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x8.Permute", opLen2_21(ssa.OpPermuteInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x8.Permute", opLen2_21(ssa.OpPermuteUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.PermuteOrZero", opLen2(ssa.OpPermuteOrZeroInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x16.PermuteOrZero", opLen2(ssa.OpPermuteOrZeroUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.PermuteOrZeroGrouped", opLen2(ssa.OpPermuteOrZeroGroupedInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.PermuteOrZeroGrouped", opLen2(ssa.OpPermuteOrZeroGroupedInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x32.PermuteOrZeroGrouped", opLen2(ssa.OpPermuteOrZeroGroupedUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.PermuteOrZeroGrouped", opLen2(ssa.OpPermuteOrZeroGroupedUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Reciprocal", opLen1(ssa.OpReciprocalFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Reciprocal", opLen1(ssa.OpReciprocalFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Reciprocal", opLen1(ssa.OpReciprocalFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Reciprocal", opLen1(ssa.OpReciprocalFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Reciprocal", opLen1(ssa.OpReciprocalFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Reciprocal", opLen1(ssa.OpReciprocalFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.ReciprocalSqrt", opLen1(ssa.OpReciprocalSqrtFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.ReciprocalSqrt", opLen1(ssa.OpReciprocalSqrtFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.ReciprocalSqrt", opLen1(ssa.OpReciprocalSqrtFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.ReciprocalSqrt", opLen1(ssa.OpReciprocalSqrtFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ReciprocalSqrt", opLen1(ssa.OpReciprocalSqrtFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.ReciprocalSqrt", opLen1(ssa.OpReciprocalSqrtFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.RotateLeft", opLen2(ssa.OpRotateLeftInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.RotateLeft", opLen2(ssa.OpRotateLeftInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.RotateLeft", opLen2(ssa.OpRotateLeftInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.RotateLeft", opLen2(ssa.OpRotateLeftInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.RotateLeft", opLen2(ssa.OpRotateLeftInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.RotateLeft", opLen2(ssa.OpRotateLeftInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.RotateLeft", opLen2(ssa.OpRotateLeftUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.RotateLeft", opLen2(ssa.OpRotateLeftUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.RotateLeft", opLen2(ssa.OpRotateLeftUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.RotateLeft", opLen2(ssa.OpRotateLeftUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.RotateLeft", opLen2(ssa.OpRotateLeftUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.RotateLeft", opLen2(ssa.OpRotateLeftUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.RotateRight", opLen2(ssa.OpRotateRightInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.RotateRight", opLen2(ssa.OpRotateRightInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.RotateRight", opLen2(ssa.OpRotateRightInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.RotateRight", opLen2(ssa.OpRotateRightInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.RotateRight", opLen2(ssa.OpRotateRightInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.RotateRight", opLen2(ssa.OpRotateRightInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.RotateRight", opLen2(ssa.OpRotateRightUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.RotateRight", opLen2(ssa.OpRotateRightUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.RotateRight", opLen2(ssa.OpRotateRightUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.RotateRight", opLen2(ssa.OpRotateRightUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.RotateRight", opLen2(ssa.OpRotateRightUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.RotateRight", opLen2(ssa.OpRotateRightUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Round", opLen1(ssa.OpRoundFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Round", opLen1(ssa.OpRoundFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x2.Round", opLen1(ssa.OpRoundFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Round", opLen1(ssa.OpRoundFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat32x4, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float32x8.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat32x8, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float32x16.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat32x16, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float64x2.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat64x2, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float64x4.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat64x4, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float64x8.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat64x8, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float32x4.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat32x4, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float32x8.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat32x8, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float32x16.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat32x16, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float64x2.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat64x2, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float64x4.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat64x4, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float64x8.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat64x8, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Uint32x4.SHA1FourRounds", opLen2Imm8_SHA1RNDS4(ssa.OpSHA1FourRoundsUint32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint32x4.SHA1Message1", opLen2(ssa.OpSHA1Message1Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.SHA1Message2", opLen2(ssa.OpSHA1Message2Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.SHA1NextE", opLen2(ssa.OpSHA1NextEUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.SHA256Message1", opLen2(ssa.OpSHA256Message1Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.SHA256Message2", opLen2(ssa.OpSHA256Message2Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.SHA256TwoRounds", opLen3(ssa.OpSHA256TwoRoundsUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x8.SaturateToInt8", opLen1(ssa.OpSaturateToInt8Int16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.SaturateToInt8", opLen1(ssa.OpSaturateToInt8Int16x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x32.SaturateToInt8", opLen1(ssa.OpSaturateToInt8Int16x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x4.SaturateToInt8", opLen1(ssa.OpSaturateToInt8Int32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.SaturateToInt8", opLen1(ssa.OpSaturateToInt8Int32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x16.SaturateToInt8", opLen1(ssa.OpSaturateToInt8Int32x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x2.SaturateToInt8", opLen1(ssa.OpSaturateToInt8Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.SaturateToInt8", opLen1(ssa.OpSaturateToInt8Int64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x8.SaturateToInt8", opLen1(ssa.OpSaturateToInt8Int64x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.SaturateToInt16", opLen1(ssa.OpSaturateToInt16Int32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.SaturateToInt16", opLen1(ssa.OpSaturateToInt16Int32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x16.SaturateToInt16", opLen1(ssa.OpSaturateToInt16Int32x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x2.SaturateToInt16", opLen1(ssa.OpSaturateToInt16Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.SaturateToInt16", opLen1(ssa.OpSaturateToInt16Int64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x8.SaturateToInt16", opLen1(ssa.OpSaturateToInt16Int64x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.SaturateToInt16Concat", opLen2(ssa.OpSaturateToInt16ConcatInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.SaturateToInt16ConcatGrouped", opLen2(ssa.OpSaturateToInt16ConcatGroupedInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.SaturateToInt16ConcatGrouped", opLen2(ssa.OpSaturateToInt16ConcatGroupedInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.SaturateToInt32", opLen1(ssa.OpSaturateToInt32Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.SaturateToInt32", opLen1(ssa.OpSaturateToInt32Int64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x8.SaturateToInt32", opLen1(ssa.OpSaturateToInt32Int64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x8.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Uint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Uint16x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x32.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Uint16x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x4.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Uint32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x16.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Uint32x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x2.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Uint64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x8.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Uint64x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Uint32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x16.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Uint32x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x2.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Uint64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x8.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Uint64x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.SaturateToUint16Concat", opLen2(ssa.OpSaturateToUint16ConcatInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.SaturateToUint16ConcatGrouped", opLen2(ssa.OpSaturateToUint16ConcatGroupedInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.SaturateToUint16ConcatGrouped", opLen2(ssa.OpSaturateToUint16ConcatGroupedInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.SaturateToUint32", opLen1(ssa.OpSaturateToUint32Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.SaturateToUint32", opLen1(ssa.OpSaturateToUint32Uint64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x8.SaturateToUint32", opLen1(ssa.OpSaturateToUint32Uint64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.Scale", opLen2(ssa.OpScaleFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Scale", opLen2(ssa.OpScaleFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Scale", opLen2(ssa.OpScaleFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Scale", opLen2(ssa.OpScaleFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Scale", opLen2(ssa.OpScaleFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Scale", opLen2(ssa.OpScaleFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.SetElem", opLen2Imm(ssa.OpSetElemFloat32x4, types.TypeVec128, 0, 3), sys.AMD64) + addF(simdPackage, "Float64x2.SetElem", opLen2Imm(ssa.OpSetElemFloat64x2, types.TypeVec128, 0, 1), sys.AMD64) + addF(simdPackage, "Int8x16.SetElem", opLen2Imm(ssa.OpSetElemInt8x16, types.TypeVec128, 0, 15), sys.AMD64) + addF(simdPackage, "Int16x8.SetElem", opLen2Imm(ssa.OpSetElemInt16x8, types.TypeVec128, 0, 7), sys.AMD64) + addF(simdPackage, "Int32x4.SetElem", opLen2Imm(ssa.OpSetElemInt32x4, types.TypeVec128, 0, 3), sys.AMD64) + addF(simdPackage, "Int64x2.SetElem", opLen2Imm(ssa.OpSetElemInt64x2, types.TypeVec128, 0, 1), sys.AMD64) + addF(simdPackage, "Uint8x16.SetElem", opLen2Imm(ssa.OpSetElemUint8x16, types.TypeVec128, 0, 15), sys.AMD64) + addF(simdPackage, "Uint16x8.SetElem", opLen2Imm(ssa.OpSetElemUint16x8, types.TypeVec128, 0, 7), sys.AMD64) + addF(simdPackage, "Uint32x4.SetElem", opLen2Imm(ssa.OpSetElemUint32x4, types.TypeVec128, 0, 3), sys.AMD64) + addF(simdPackage, "Uint64x2.SetElem", opLen2Imm(ssa.OpSetElemUint64x2, types.TypeVec128, 0, 1), sys.AMD64) + addF(simdPackage, "Float32x8.SetHi", opLen2(ssa.OpSetHiFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.SetHi", opLen2(ssa.OpSetHiFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x4.SetHi", opLen2(ssa.OpSetHiFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.SetHi", opLen2(ssa.OpSetHiFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x32.SetHi", opLen2(ssa.OpSetHiInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.SetHi", opLen2(ssa.OpSetHiInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x16.SetHi", opLen2(ssa.OpSetHiInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.SetHi", opLen2(ssa.OpSetHiInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x8.SetHi", opLen2(ssa.OpSetHiInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.SetHi", opLen2(ssa.OpSetHiInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x4.SetHi", opLen2(ssa.OpSetHiInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.SetHi", opLen2(ssa.OpSetHiInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x32.SetHi", opLen2(ssa.OpSetHiUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.SetHi", opLen2(ssa.OpSetHiUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x16.SetHi", opLen2(ssa.OpSetHiUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.SetHi", opLen2(ssa.OpSetHiUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x8.SetHi", opLen2(ssa.OpSetHiUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.SetHi", opLen2(ssa.OpSetHiUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x4.SetHi", opLen2(ssa.OpSetHiUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.SetHi", opLen2(ssa.OpSetHiUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x8.SetLo", opLen2(ssa.OpSetLoFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.SetLo", opLen2(ssa.OpSetLoFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x4.SetLo", opLen2(ssa.OpSetLoFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.SetLo", opLen2(ssa.OpSetLoFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x32.SetLo", opLen2(ssa.OpSetLoInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.SetLo", opLen2(ssa.OpSetLoInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x16.SetLo", opLen2(ssa.OpSetLoInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.SetLo", opLen2(ssa.OpSetLoInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x8.SetLo", opLen2(ssa.OpSetLoInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.SetLo", opLen2(ssa.OpSetLoInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x4.SetLo", opLen2(ssa.OpSetLoInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.SetLo", opLen2(ssa.OpSetLoInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x32.SetLo", opLen2(ssa.OpSetLoUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.SetLo", opLen2(ssa.OpSetLoUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x16.SetLo", opLen2(ssa.OpSetLoUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.SetLo", opLen2(ssa.OpSetLoUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x8.SetLo", opLen2(ssa.OpSetLoUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.SetLo", opLen2(ssa.OpSetLoUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x4.SetLo", opLen2(ssa.OpSetLoUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.SetLo", opLen2(ssa.OpSetLoUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.ShiftAllLeftConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod16Int16x8, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int16x16.ShiftAllLeftConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod16Int16x16, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int16x32.ShiftAllLeftConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod16Int16x32, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint16x8.ShiftAllLeftConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod16Uint16x8, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint16x16.ShiftAllLeftConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod16Uint16x16, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint16x32.ShiftAllLeftConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod16Uint16x32, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int32x4.ShiftAllLeftConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod32Int32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int32x8.ShiftAllLeftConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod32Int32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int32x16.ShiftAllLeftConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod32Int32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint32x4.ShiftAllLeftConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod32Uint32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint32x8.ShiftAllLeftConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod32Uint32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint32x16.ShiftAllLeftConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod32Uint32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int64x2.ShiftAllLeftConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod64Int64x2, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int64x4.ShiftAllLeftConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod64Int64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int64x8.ShiftAllLeftConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod64Int64x8, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint64x2.ShiftAllLeftConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod64Uint64x2, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint64x4.ShiftAllLeftConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod64Uint64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint64x8.ShiftAllLeftConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllLeftConcatMod64Uint64x8, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int16x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.ShiftAllRightConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod16Int16x8, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int16x16.ShiftAllRightConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod16Int16x16, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int16x32.ShiftAllRightConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod16Int16x32, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint16x8.ShiftAllRightConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod16Uint16x8, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint16x16.ShiftAllRightConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod16Uint16x16, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint16x32.ShiftAllRightConcatMod16", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod16Uint16x32, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int32x4.ShiftAllRightConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod32Int32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int32x8.ShiftAllRightConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod32Int32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int32x16.ShiftAllRightConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod32Int32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint32x4.ShiftAllRightConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod32Uint32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint32x8.ShiftAllRightConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod32Uint32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint32x16.ShiftAllRightConcatMod32", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod32Uint32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int64x2.ShiftAllRightConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod64Int64x2, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int64x4.ShiftAllRightConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod64Int64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int64x8.ShiftAllRightConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod64Int64x8, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint64x2.ShiftAllRightConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod64Uint64x2, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint64x4.ShiftAllRightConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod64Uint64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint64x8.ShiftAllRightConcatMod64", opLen2Imm8_2I(ssa.OpShiftAllRightConcatMod64Uint64x8, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int16x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.ShiftLeftConcatMod16", opLen3(ssa.OpShiftLeftConcatMod16Int16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.ShiftLeftConcatMod16", opLen3(ssa.OpShiftLeftConcatMod16Int16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.ShiftLeftConcatMod16", opLen3(ssa.OpShiftLeftConcatMod16Int16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.ShiftLeftConcatMod16", opLen3(ssa.OpShiftLeftConcatMod16Uint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.ShiftLeftConcatMod16", opLen3(ssa.OpShiftLeftConcatMod16Uint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.ShiftLeftConcatMod16", opLen3(ssa.OpShiftLeftConcatMod16Uint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.ShiftLeftConcatMod32", opLen3(ssa.OpShiftLeftConcatMod32Int32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.ShiftLeftConcatMod32", opLen3(ssa.OpShiftLeftConcatMod32Int32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.ShiftLeftConcatMod32", opLen3(ssa.OpShiftLeftConcatMod32Int32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.ShiftLeftConcatMod32", opLen3(ssa.OpShiftLeftConcatMod32Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.ShiftLeftConcatMod32", opLen3(ssa.OpShiftLeftConcatMod32Uint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.ShiftLeftConcatMod32", opLen3(ssa.OpShiftLeftConcatMod32Uint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.ShiftLeftConcatMod64", opLen3(ssa.OpShiftLeftConcatMod64Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.ShiftLeftConcatMod64", opLen3(ssa.OpShiftLeftConcatMod64Int64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.ShiftLeftConcatMod64", opLen3(ssa.OpShiftLeftConcatMod64Int64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.ShiftLeftConcatMod64", opLen3(ssa.OpShiftLeftConcatMod64Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.ShiftLeftConcatMod64", opLen3(ssa.OpShiftLeftConcatMod64Uint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.ShiftLeftConcatMod64", opLen3(ssa.OpShiftLeftConcatMod64Uint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.ShiftRight", opLen2(ssa.OpShiftRightInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.ShiftRight", opLen2(ssa.OpShiftRightInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.ShiftRight", opLen2(ssa.OpShiftRightInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.ShiftRight", opLen2(ssa.OpShiftRightInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.ShiftRight", opLen2(ssa.OpShiftRightInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.ShiftRight", opLen2(ssa.OpShiftRightInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.ShiftRight", opLen2(ssa.OpShiftRightInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.ShiftRight", opLen2(ssa.OpShiftRightInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.ShiftRight", opLen2(ssa.OpShiftRightInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.ShiftRight", opLen2(ssa.OpShiftRightUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.ShiftRight", opLen2(ssa.OpShiftRightUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.ShiftRight", opLen2(ssa.OpShiftRightUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.ShiftRight", opLen2(ssa.OpShiftRightUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.ShiftRight", opLen2(ssa.OpShiftRightUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.ShiftRight", opLen2(ssa.OpShiftRightUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.ShiftRight", opLen2(ssa.OpShiftRightUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.ShiftRight", opLen2(ssa.OpShiftRightUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.ShiftRight", opLen2(ssa.OpShiftRightUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.ShiftRightConcatMod16", opLen3(ssa.OpShiftRightConcatMod16Int16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.ShiftRightConcatMod16", opLen3(ssa.OpShiftRightConcatMod16Int16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.ShiftRightConcatMod16", opLen3(ssa.OpShiftRightConcatMod16Int16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.ShiftRightConcatMod16", opLen3(ssa.OpShiftRightConcatMod16Uint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.ShiftRightConcatMod16", opLen3(ssa.OpShiftRightConcatMod16Uint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.ShiftRightConcatMod16", opLen3(ssa.OpShiftRightConcatMod16Uint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.ShiftRightConcatMod32", opLen3(ssa.OpShiftRightConcatMod32Int32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.ShiftRightConcatMod32", opLen3(ssa.OpShiftRightConcatMod32Int32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.ShiftRightConcatMod32", opLen3(ssa.OpShiftRightConcatMod32Int32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.ShiftRightConcatMod32", opLen3(ssa.OpShiftRightConcatMod32Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.ShiftRightConcatMod32", opLen3(ssa.OpShiftRightConcatMod32Uint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.ShiftRightConcatMod32", opLen3(ssa.OpShiftRightConcatMod32Uint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.ShiftRightConcatMod64", opLen3(ssa.OpShiftRightConcatMod64Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.ShiftRightConcatMod64", opLen3(ssa.OpShiftRightConcatMod64Int64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.ShiftRightConcatMod64", opLen3(ssa.OpShiftRightConcatMod64Int64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.ShiftRightConcatMod64", opLen3(ssa.OpShiftRightConcatMod64Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.ShiftRightConcatMod64", opLen3(ssa.OpShiftRightConcatMod64Uint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.ShiftRightConcatMod64", opLen3(ssa.OpShiftRightConcatMod64Uint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Sqrt", opLen1(ssa.OpSqrtFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Sqrt", opLen1(ssa.OpSqrtFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Sqrt", opLen1(ssa.OpSqrtFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Sqrt", opLen1(ssa.OpSqrtFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Sqrt", opLen1(ssa.OpSqrtFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Sqrt", opLen1(ssa.OpSqrtFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Sub", opLen2(ssa.OpSubFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Sub", opLen2(ssa.OpSubFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x16.Sub", opLen2(ssa.OpSubFloat32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.Sub", opLen2(ssa.OpSubFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Sub", opLen2(ssa.OpSubFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.Sub", opLen2(ssa.OpSubFloat64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.Sub", opLen2(ssa.OpSubInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Sub", opLen2(ssa.OpSubInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Sub", opLen2(ssa.OpSubInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Sub", opLen2(ssa.OpSubInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Sub", opLen2(ssa.OpSubInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Sub", opLen2(ssa.OpSubInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Sub", opLen2(ssa.OpSubInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Sub", opLen2(ssa.OpSubInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Sub", opLen2(ssa.OpSubInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Sub", opLen2(ssa.OpSubInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Sub", opLen2(ssa.OpSubInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Sub", opLen2(ssa.OpSubInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.Sub", opLen2(ssa.OpSubUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.Sub", opLen2(ssa.OpSubUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.Sub", opLen2(ssa.OpSubUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Sub", opLen2(ssa.OpSubUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Sub", opLen2(ssa.OpSubUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Sub", opLen2(ssa.OpSubUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.Sub", opLen2(ssa.OpSubUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.Sub", opLen2(ssa.OpSubUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.Sub", opLen2(ssa.OpSubUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.Sub", opLen2(ssa.OpSubUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.Sub", opLen2(ssa.OpSubUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.Sub", opLen2(ssa.OpSubUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.SubSaturated", opLen2(ssa.OpSubSaturatedInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.SubSaturated", opLen2(ssa.OpSubSaturatedInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.SubSaturated", opLen2(ssa.OpSubSaturatedInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.SubSaturated", opLen2(ssa.OpSubSaturatedInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.SubSaturated", opLen2(ssa.OpSubSaturatedInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.SubSaturated", opLen2(ssa.OpSubSaturatedInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.SubSaturated", opLen2(ssa.OpSubSaturatedUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.SubSaturated", opLen2(ssa.OpSubSaturatedUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.SubSaturated", opLen2(ssa.OpSubSaturatedUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.SubSaturated", opLen2(ssa.OpSubSaturatedUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.SubSaturated", opLen2(ssa.OpSubSaturatedUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.SubSaturated", opLen2(ssa.OpSubSaturatedUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.SumOf8AbsDiff", opLen2(ssa.OpSumOf8AbsDiffUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.SumOf8AbsDiff", opLen2(ssa.OpSumOf8AbsDiffUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.SumOf8AbsDiff", opLen2(ssa.OpSumOf8AbsDiffUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.Trunc", opLen1(ssa.OpTruncFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x8.Trunc", opLen1(ssa.OpTruncFloat32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x2.Trunc", opLen1(ssa.OpTruncFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.Trunc", opLen1(ssa.OpTruncFloat64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.TruncScaled", opLen1Imm8(ssa.OpTruncScaledFloat32x4, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float32x8.TruncScaled", opLen1Imm8(ssa.OpTruncScaledFloat32x8, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float32x16.TruncScaled", opLen1Imm8(ssa.OpTruncScaledFloat32x16, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float64x2.TruncScaled", opLen1Imm8(ssa.OpTruncScaledFloat64x2, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float64x4.TruncScaled", opLen1Imm8(ssa.OpTruncScaledFloat64x4, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float64x8.TruncScaled", opLen1Imm8(ssa.OpTruncScaledFloat64x8, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float32x4.TruncScaledResidue", opLen1Imm8(ssa.OpTruncScaledResidueFloat32x4, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float32x8.TruncScaledResidue", opLen1Imm8(ssa.OpTruncScaledResidueFloat32x8, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float32x16.TruncScaledResidue", opLen1Imm8(ssa.OpTruncScaledResidueFloat32x16, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Float64x2.TruncScaledResidue", opLen1Imm8(ssa.OpTruncScaledResidueFloat64x2, types.TypeVec128, 4), sys.AMD64) + addF(simdPackage, "Float64x4.TruncScaledResidue", opLen1Imm8(ssa.OpTruncScaledResidueFloat64x4, types.TypeVec256, 4), sys.AMD64) + addF(simdPackage, "Float64x8.TruncScaledResidue", opLen1Imm8(ssa.OpTruncScaledResidueFloat64x8, types.TypeVec512, 4), sys.AMD64) + addF(simdPackage, "Int16x8.TruncToInt8", opLen1(ssa.OpTruncToInt8Int16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.TruncToInt8", opLen1(ssa.OpTruncToInt8Int16x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x32.TruncToInt8", opLen1(ssa.OpTruncToInt8Int16x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x4.TruncToInt8", opLen1(ssa.OpTruncToInt8Int32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.TruncToInt8", opLen1(ssa.OpTruncToInt8Int32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x16.TruncToInt8", opLen1(ssa.OpTruncToInt8Int32x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x2.TruncToInt8", opLen1(ssa.OpTruncToInt8Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.TruncToInt8", opLen1(ssa.OpTruncToInt8Int64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x8.TruncToInt8", opLen1(ssa.OpTruncToInt8Int64x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.TruncToInt16", opLen1(ssa.OpTruncToInt16Int32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.TruncToInt16", opLen1(ssa.OpTruncToInt16Int32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x16.TruncToInt16", opLen1(ssa.OpTruncToInt16Int32x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x2.TruncToInt16", opLen1(ssa.OpTruncToInt16Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.TruncToInt16", opLen1(ssa.OpTruncToInt16Int64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x8.TruncToInt16", opLen1(ssa.OpTruncToInt16Int64x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x2.TruncToInt32", opLen1(ssa.OpTruncToInt32Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.TruncToInt32", opLen1(ssa.OpTruncToInt32Int64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x8.TruncToInt32", opLen1(ssa.OpTruncToInt32Int64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x8.TruncToUint8", opLen1(ssa.OpTruncToUint8Uint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.TruncToUint8", opLen1(ssa.OpTruncToUint8Uint16x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x32.TruncToUint8", opLen1(ssa.OpTruncToUint8Uint16x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x4.TruncToUint8", opLen1(ssa.OpTruncToUint8Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.TruncToUint8", opLen1(ssa.OpTruncToUint8Uint32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x16.TruncToUint8", opLen1(ssa.OpTruncToUint8Uint32x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x2.TruncToUint8", opLen1(ssa.OpTruncToUint8Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.TruncToUint8", opLen1(ssa.OpTruncToUint8Uint64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x8.TruncToUint8", opLen1(ssa.OpTruncToUint8Uint64x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.TruncToUint16", opLen1(ssa.OpTruncToUint16Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.TruncToUint16", opLen1(ssa.OpTruncToUint16Uint32x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x16.TruncToUint16", opLen1(ssa.OpTruncToUint16Uint32x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x2.TruncToUint16", opLen1(ssa.OpTruncToUint16Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.TruncToUint16", opLen1(ssa.OpTruncToUint16Uint64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x8.TruncToUint16", opLen1(ssa.OpTruncToUint16Uint64x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x2.TruncToUint32", opLen1(ssa.OpTruncToUint32Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x4.TruncToUint32", opLen1(ssa.OpTruncToUint32Uint64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x8.TruncToUint32", opLen1(ssa.OpTruncToUint32Uint64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x16.Xor", opLen2(ssa.OpXorInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.Xor", opLen2(ssa.OpXorInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.Xor", opLen2(ssa.OpXorInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.Xor", opLen2(ssa.OpXorInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x16.Xor", opLen2(ssa.OpXorInt16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x32.Xor", opLen2(ssa.OpXorInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x4.Xor", opLen2(ssa.OpXorInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x8.Xor", opLen2(ssa.OpXorInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x16.Xor", opLen2(ssa.OpXorInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x2.Xor", opLen2(ssa.OpXorInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x4.Xor", opLen2(ssa.OpXorInt64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x8.Xor", opLen2(ssa.OpXorInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.Xor", opLen2(ssa.OpXorUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint8x32.Xor", opLen2(ssa.OpXorUint8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint8x64.Xor", opLen2(ssa.OpXorUint8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.Xor", opLen2(ssa.OpXorUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x16.Xor", opLen2(ssa.OpXorUint16x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x32.Xor", opLen2(ssa.OpXorUint16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint32x4.Xor", opLen2(ssa.OpXorUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x8.Xor", opLen2(ssa.OpXorUint32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x16.Xor", opLen2(ssa.OpXorUint32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x4.Xor", opLen2(ssa.OpXorUint64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x8.Xor", opLen2(ssa.OpXorUint64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.Xor", opLen2(ssa.OpXorUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x16.blend", opLen3(ssa.OpblendInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int8x32.blend", opLen3(ssa.OpblendInt8x32, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int8x64.blendMasked", opLen3(ssa.OpblendMaskedInt8x64, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x32.blendMasked", opLen3(ssa.OpblendMaskedInt16x32, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int32x16.blendMasked", opLen3(ssa.OpblendMaskedInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int64x8.blendMasked", opLen3(ssa.OpblendMaskedInt64x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.broadcast1To2", opLen1(ssa.Opbroadcast1To2Float64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x2.broadcast1To2", opLen1(ssa.Opbroadcast1To2Int64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x2.broadcast1To2", opLen1(ssa.Opbroadcast1To2Uint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x2.broadcast1To2Masked", opLen2(ssa.Opbroadcast1To2MaskedFloat64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x2.broadcast1To2Masked", opLen2(ssa.Opbroadcast1To2MaskedInt64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x2.broadcast1To2Masked", opLen2(ssa.Opbroadcast1To2MaskedUint64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float32x4.broadcast1To4", opLen1(ssa.Opbroadcast1To4Float32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x2.broadcast1To4", opLen1(ssa.Opbroadcast1To4Float64x2, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x4.broadcast1To4", opLen1(ssa.Opbroadcast1To4Int32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x2.broadcast1To4", opLen1(ssa.Opbroadcast1To4Int64x2, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x4.broadcast1To4", opLen1(ssa.Opbroadcast1To4Uint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x2.broadcast1To4", opLen1(ssa.Opbroadcast1To4Uint64x2, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.broadcast1To4Masked", opLen2(ssa.Opbroadcast1To4MaskedFloat32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x2.broadcast1To4Masked", opLen2(ssa.Opbroadcast1To4MaskedFloat64x2, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x4.broadcast1To4Masked", opLen2(ssa.Opbroadcast1To4MaskedInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int64x2.broadcast1To4Masked", opLen2(ssa.Opbroadcast1To4MaskedInt64x2, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x4.broadcast1To4Masked", opLen2(ssa.Opbroadcast1To4MaskedUint32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint64x2.broadcast1To4Masked", opLen2(ssa.Opbroadcast1To4MaskedUint64x2, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.broadcast1To8", opLen1(ssa.Opbroadcast1To8Float32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x2.broadcast1To8", opLen1(ssa.Opbroadcast1To8Float64x2, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.broadcast1To8", opLen1(ssa.Opbroadcast1To8Int16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.broadcast1To8", opLen1(ssa.Opbroadcast1To8Int32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x2.broadcast1To8", opLen1(ssa.Opbroadcast1To8Int64x2, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.broadcast1To8", opLen1(ssa.Opbroadcast1To8Uint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.broadcast1To8", opLen1(ssa.Opbroadcast1To8Uint32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x2.broadcast1To8", opLen1(ssa.Opbroadcast1To8Uint64x2, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.broadcast1To8Masked", opLen2(ssa.Opbroadcast1To8MaskedFloat32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x2.broadcast1To8Masked", opLen2(ssa.Opbroadcast1To8MaskedFloat64x2, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int16x8.broadcast1To8Masked", opLen2(ssa.Opbroadcast1To8MaskedInt16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int32x4.broadcast1To8Masked", opLen2(ssa.Opbroadcast1To8MaskedInt32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int64x2.broadcast1To8Masked", opLen2(ssa.Opbroadcast1To8MaskedInt64x2, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint16x8.broadcast1To8Masked", opLen2(ssa.Opbroadcast1To8MaskedUint16x8, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint32x4.broadcast1To8Masked", opLen2(ssa.Opbroadcast1To8MaskedUint32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint64x2.broadcast1To8Masked", opLen2(ssa.Opbroadcast1To8MaskedUint64x2, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.broadcast1To16", opLen1(ssa.Opbroadcast1To16Float32x4, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.broadcast1To16", opLen1(ssa.Opbroadcast1To16Int8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x8.broadcast1To16", opLen1(ssa.Opbroadcast1To16Int16x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x4.broadcast1To16", opLen1(ssa.Opbroadcast1To16Int32x4, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.broadcast1To16", opLen1(ssa.Opbroadcast1To16Uint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x8.broadcast1To16", opLen1(ssa.Opbroadcast1To16Uint16x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x4.broadcast1To16", opLen1(ssa.Opbroadcast1To16Uint32x4, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float32x4.broadcast1To16Masked", opLen2(ssa.Opbroadcast1To16MaskedFloat32x4, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.broadcast1To16Masked", opLen2(ssa.Opbroadcast1To16MaskedInt8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Int16x8.broadcast1To16Masked", opLen2(ssa.Opbroadcast1To16MaskedInt16x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int32x4.broadcast1To16Masked", opLen2(ssa.Opbroadcast1To16MaskedInt32x4, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.broadcast1To16Masked", opLen2(ssa.Opbroadcast1To16MaskedUint8x16, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Uint16x8.broadcast1To16Masked", opLen2(ssa.Opbroadcast1To16MaskedUint16x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint32x4.broadcast1To16Masked", opLen2(ssa.Opbroadcast1To16MaskedUint32x4, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.broadcast1To32", opLen1(ssa.Opbroadcast1To32Int8x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x8.broadcast1To32", opLen1(ssa.Opbroadcast1To32Int16x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.broadcast1To32", opLen1(ssa.Opbroadcast1To32Uint8x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x8.broadcast1To32", opLen1(ssa.Opbroadcast1To32Uint16x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.broadcast1To32Masked", opLen2(ssa.Opbroadcast1To32MaskedInt8x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Int16x8.broadcast1To32Masked", opLen2(ssa.Opbroadcast1To32MaskedInt16x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.broadcast1To32Masked", opLen2(ssa.Opbroadcast1To32MaskedUint8x16, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Uint16x8.broadcast1To32Masked", opLen2(ssa.Opbroadcast1To32MaskedUint16x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.broadcast1To64", opLen1(ssa.Opbroadcast1To64Int8x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.broadcast1To64", opLen1(ssa.Opbroadcast1To64Uint8x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Int8x16.broadcast1To64Masked", opLen2(ssa.Opbroadcast1To64MaskedInt8x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint8x16.broadcast1To64Masked", opLen2(ssa.Opbroadcast1To64MaskedUint8x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Uint64x2.carrylessMultiply", opLen2Imm8(ssa.OpcarrylessMultiplyUint64x2, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint64x4.carrylessMultiply", opLen2Imm8(ssa.OpcarrylessMultiplyUint64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint64x8.carrylessMultiply", opLen2Imm8(ssa.OpcarrylessMultiplyUint64x8, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Float32x4.concatSelectedConstant", opLen2Imm8(ssa.OpconcatSelectedConstantFloat32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Float64x2.concatSelectedConstant", opLen2Imm8(ssa.OpconcatSelectedConstantFloat64x2, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int32x4.concatSelectedConstant", opLen2Imm8(ssa.OpconcatSelectedConstantInt32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int64x2.concatSelectedConstant", opLen2Imm8(ssa.OpconcatSelectedConstantInt64x2, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint32x4.concatSelectedConstant", opLen2Imm8(ssa.OpconcatSelectedConstantUint32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint64x2.concatSelectedConstant", opLen2Imm8(ssa.OpconcatSelectedConstantUint64x2, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Float32x8.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedFloat32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Float32x16.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedFloat32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Float64x4.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedFloat64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Float64x8.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedFloat64x8, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int32x8.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedInt32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int32x16.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedInt32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int64x4.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedInt64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int64x8.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedInt64x8, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint32x8.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedUint32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint32x16.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedUint32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint64x4.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedUint64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint64x8.concatSelectedConstantGrouped", opLen2Imm8(ssa.OpconcatSelectedConstantGroupedUint64x8, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int32x4.permuteScalars", opLen1Imm8(ssa.OppermuteScalarsInt32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint32x4.permuteScalars", opLen1Imm8(ssa.OppermuteScalarsUint32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int32x8.permuteScalarsGrouped", opLen1Imm8(ssa.OppermuteScalarsGroupedInt32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int32x16.permuteScalarsGrouped", opLen1Imm8(ssa.OppermuteScalarsGroupedInt32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint32x8.permuteScalarsGrouped", opLen1Imm8(ssa.OppermuteScalarsGroupedUint32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint32x16.permuteScalarsGrouped", opLen1Imm8(ssa.OppermuteScalarsGroupedUint32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int16x8.permuteScalarsHi", opLen1Imm8(ssa.OppermuteScalarsHiInt16x8, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint16x8.permuteScalarsHi", opLen1Imm8(ssa.OppermuteScalarsHiUint16x8, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int16x16.permuteScalarsHiGrouped", opLen1Imm8(ssa.OppermuteScalarsHiGroupedInt16x16, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int16x32.permuteScalarsHiGrouped", opLen1Imm8(ssa.OppermuteScalarsHiGroupedInt16x32, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint16x16.permuteScalarsHiGrouped", opLen1Imm8(ssa.OppermuteScalarsHiGroupedUint16x16, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint16x32.permuteScalarsHiGrouped", opLen1Imm8(ssa.OppermuteScalarsHiGroupedUint16x32, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int16x8.permuteScalarsLo", opLen1Imm8(ssa.OppermuteScalarsLoInt16x8, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint16x8.permuteScalarsLo", opLen1Imm8(ssa.OppermuteScalarsLoUint16x8, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int16x16.permuteScalarsLoGrouped", opLen1Imm8(ssa.OppermuteScalarsLoGroupedInt16x16, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int16x32.permuteScalarsLoGrouped", opLen1Imm8(ssa.OppermuteScalarsLoGroupedInt16x32, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint16x16.permuteScalarsLoGrouped", opLen1Imm8(ssa.OppermuteScalarsLoGroupedUint16x16, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint16x32.permuteScalarsLoGrouped", opLen1Imm8(ssa.OppermuteScalarsLoGroupedUint16x32, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int32x4.tern", opLen3Imm8(ssa.OpternInt32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int32x8.tern", opLen3Imm8(ssa.OpternInt32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int32x16.tern", opLen3Imm8(ssa.OpternInt32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Int64x2.tern", opLen3Imm8(ssa.OpternInt64x2, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Int64x4.tern", opLen3Imm8(ssa.OpternInt64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Int64x8.tern", opLen3Imm8(ssa.OpternInt64x8, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint32x4.tern", opLen3Imm8(ssa.OpternUint32x4, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint32x8.tern", opLen3Imm8(ssa.OpternUint32x8, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint32x16.tern", opLen3Imm8(ssa.OpternUint32x16, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Uint64x2.tern", opLen3Imm8(ssa.OpternUint64x2, types.TypeVec128, 0), sys.AMD64) + addF(simdPackage, "Uint64x4.tern", opLen3Imm8(ssa.OpternUint64x4, types.TypeVec256, 0), sys.AMD64) + addF(simdPackage, "Uint64x8.tern", opLen3Imm8(ssa.OpternUint64x8, types.TypeVec512, 0), sys.AMD64) + addF(simdPackage, "Float32x4.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x4.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x4.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x4.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x4.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x4.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x4.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x4.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x4.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x8.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x8.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x8.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x8.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x8.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x8.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x8.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x8.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x8.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x16.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x16.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x16.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x16.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x16.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x16.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x16.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x16.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x16.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x2.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x2.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x2.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x2.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x2.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x2.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x2.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x2.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x2.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x4.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x4.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x4.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x4.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x4.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x4.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x4.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x4.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x4.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x8.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x8.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x8.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x8.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x8.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x8.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x8.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x8.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x8.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.BitsToInt8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.ConvertToInt8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.ConvertToUint8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x16.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.BitsToInt8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.ConvertToInt8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.ConvertToUint8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x32.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.BitsToInt8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.ConvertToInt8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.ConvertToUint8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint8x64.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.BitsToInt16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.ConvertToInt16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.ConvertToUint16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x8.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.BitsToInt16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.ConvertToInt16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.ConvertToUint16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x16.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.BitsToInt16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.ConvertToInt16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.ConvertToUint16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint16x32.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.BitsToFloat32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x4.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.BitsToInt32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.ConvertToInt32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.ConvertToUint32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x4.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.BitsToFloat32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x8.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.BitsToInt32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.ConvertToInt32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.ConvertToUint32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x8.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.BitsToFloat32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float32x16.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.BitsToInt32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.ConvertToInt32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.ConvertToUint32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint32x16.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.BitsToFloat64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x2.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.BitsToInt64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.ConvertToInt64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.ConvertToUint64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x2.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.BitsToFloat64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x4.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.BitsToInt64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.ConvertToInt64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.ConvertToUint64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x4.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.BitsToFloat64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Float64x8.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.BitsToInt64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.ConvertToInt64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.ConvertToUint64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Uint64x8.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "LoadFloat32x4Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Float32x4.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadFloat32x8Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Float32x8.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadFloat32x16Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Float32x16.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadFloat64x2Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Float64x2.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadFloat64x4Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Float64x4.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadFloat64x8Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Float64x8.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt8x16Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int8x16.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt8x32Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int8x32.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt8x64Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int8x64.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt16x8Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int16x8.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt16x16Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int16x16.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt16x32Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int16x32.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt32x4Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int32x4.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt32x8Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int32x8.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt32x16Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int32x16.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt64x2Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int64x2.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt64x4Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int64x4.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadInt64x8Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Int64x8.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint8x16Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint8x16.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint8x32Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint8x32.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint8x64Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint8x64.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint16x8Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint16x8.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint16x16Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint16x16.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint16x32Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint16x32.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint32x4Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint32x4.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint32x8Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint32x8.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint32x16Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint32x16.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint64x2Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint64x2.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint64x4Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint64x4.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "LoadUint64x8Array", simdLoad(), sys.AMD64) + addF(simdPackage, "Uint64x8.StoreArray", simdStore(), sys.AMD64) + addF(simdPackage, "Float32x4.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked32), sys.AMD64) + addF(simdPackage, "Float32x8.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked32), sys.AMD64) + addF(simdPackage, "Float32x16.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked32), sys.AMD64) + addF(simdPackage, "Float64x2.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked64), sys.AMD64) + addF(simdPackage, "Float64x4.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked64), sys.AMD64) + addF(simdPackage, "Float64x8.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked64), sys.AMD64) + addF(simdPackage, "Int8x64.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked8), sys.AMD64) + addF(simdPackage, "Int16x32.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked16), sys.AMD64) + addF(simdPackage, "Int32x4.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked32), sys.AMD64) + addF(simdPackage, "Int32x8.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked32), sys.AMD64) + addF(simdPackage, "Int32x16.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked32), sys.AMD64) + addF(simdPackage, "Int64x2.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked64), sys.AMD64) + addF(simdPackage, "Int64x4.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked64), sys.AMD64) + addF(simdPackage, "Int64x8.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked64), sys.AMD64) + addF(simdPackage, "Uint8x64.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked8), sys.AMD64) + addF(simdPackage, "Uint16x32.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked16), sys.AMD64) + addF(simdPackage, "Uint32x4.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked32), sys.AMD64) + addF(simdPackage, "Uint32x8.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked32), sys.AMD64) + addF(simdPackage, "Uint32x16.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked32), sys.AMD64) + addF(simdPackage, "Uint64x2.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked64), sys.AMD64) + addF(simdPackage, "Uint64x4.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked64), sys.AMD64) + addF(simdPackage, "Uint64x8.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked64), sys.AMD64) + addF(simdPackage, "Mask8x64.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked8), sys.AMD64) + addF(simdPackage, "Mask16x32.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked16), sys.AMD64) + addF(simdPackage, "Mask32x16.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked32), sys.AMD64) + addF(simdPackage, "Mask64x8.StoreArrayMasked", simdMaskedStore(ssa.OpStoreMasked64), sys.AMD64) + addF(simdPackage, "Mask8x16.ToInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x16.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask8x16.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Mask8x16.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Mask8x16FromBits", simdCvtVToMask(8, 16), sys.AMD64) + addF(simdPackage, "Mask8x16.ToBits", simdCvtMaskToV(8, 16), sys.AMD64) + addF(simdPackage, "Mask8x32.ToInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x32.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask8x32.And", opLen2(ssa.OpAndInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Mask8x32.Or", opLen2(ssa.OpOrInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Mask8x32FromBits", simdCvtVToMask(8, 32), sys.AMD64) + addF(simdPackage, "Mask8x32.ToBits", simdCvtMaskToV(8, 32), sys.AMD64) + addF(simdPackage, "Mask8x64.ToInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int8x64.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask8x64.And", opLen2(ssa.OpAndInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Mask8x64.Or", opLen2(ssa.OpOrInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Mask8x64FromBits", simdCvtVToMask(8, 64), sys.AMD64) + addF(simdPackage, "Mask8x64.ToBits", simdCvtMaskToV(8, 64), sys.AMD64) + addF(simdPackage, "Mask16x8.ToInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x8.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask16x8.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Mask16x8.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Mask16x8FromBits", simdCvtVToMask(16, 8), sys.AMD64) + addF(simdPackage, "Mask16x8.ToBits", simdCvtMaskToV(16, 8), sys.AMD64) + addF(simdPackage, "Mask16x16.ToInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x16.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask16x16.And", opLen2(ssa.OpAndInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Mask16x16.Or", opLen2(ssa.OpOrInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Mask16x16FromBits", simdCvtVToMask(16, 16), sys.AMD64) + addF(simdPackage, "Mask16x16.ToBits", simdCvtMaskToV(16, 16), sys.AMD64) + addF(simdPackage, "Mask16x32.ToInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int16x32.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask16x32.And", opLen2(ssa.OpAndInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Mask16x32.Or", opLen2(ssa.OpOrInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Mask16x32FromBits", simdCvtVToMask(16, 32), sys.AMD64) + addF(simdPackage, "Mask16x32.ToBits", simdCvtMaskToV(16, 32), sys.AMD64) + addF(simdPackage, "Mask32x4.ToInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x4.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask32x4.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Mask32x4.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Mask32x4FromBits", simdCvtVToMask(32, 4), sys.AMD64) + addF(simdPackage, "Mask32x4.ToBits", simdCvtMaskToV(32, 4), sys.AMD64) + addF(simdPackage, "Mask32x8.ToInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x8.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask32x8.And", opLen2(ssa.OpAndInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Mask32x8.Or", opLen2(ssa.OpOrInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Mask32x8FromBits", simdCvtVToMask(32, 8), sys.AMD64) + addF(simdPackage, "Mask32x8.ToBits", simdCvtMaskToV(32, 8), sys.AMD64) + addF(simdPackage, "Mask32x16.ToInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int32x16.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask32x16.And", opLen2(ssa.OpAndInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Mask32x16.Or", opLen2(ssa.OpOrInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Mask32x16FromBits", simdCvtVToMask(32, 16), sys.AMD64) + addF(simdPackage, "Mask32x16.ToBits", simdCvtMaskToV(32, 16), sys.AMD64) + addF(simdPackage, "Mask64x2.ToInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x2.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask64x2.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Mask64x2.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Mask64x2FromBits", simdCvtVToMask(64, 2), sys.AMD64) + addF(simdPackage, "Mask64x2.ToBits", simdCvtMaskToV(64, 2), sys.AMD64) + addF(simdPackage, "Mask64x4.ToInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x4.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask64x4.And", opLen2(ssa.OpAndInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Mask64x4.Or", opLen2(ssa.OpOrInt32x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Mask64x4FromBits", simdCvtVToMask(64, 4), sys.AMD64) + addF(simdPackage, "Mask64x4.ToBits", simdCvtMaskToV(64, 4), sys.AMD64) + addF(simdPackage, "Mask64x8.ToInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Int64x8.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64) + addF(simdPackage, "Mask64x8.And", opLen2(ssa.OpAndInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Mask64x8.Or", opLen2(ssa.OpOrInt32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Mask64x8FromBits", simdCvtVToMask(64, 8), sys.AMD64) + addF(simdPackage, "Mask64x8.ToBits", simdCvtMaskToV(64, 8), sys.AMD64) +} diff --git a/src/cmd/compile/internal/ssagen/simdARM64intrinsics.go b/src/cmd/compile/internal/ssagen/simdARM64intrinsics.go new file mode 100644 index 00000000000000..74a11a443d0767 --- /dev/null +++ b/src/cmd/compile/internal/ssagen/simdARM64intrinsics.go @@ -0,0 +1,546 @@ +// Code generated by 'simdgen -o godefs -goroot $GOROOT -arch arm64 -arm64Path $ARM64_ISA_PATH go_arm64.yaml types.yaml categories.yaml'; DO NOT EDIT. +package ssagen + +import ( + "cmd/compile/internal/ir" + "cmd/compile/internal/ssa" + "cmd/compile/internal/types" + "cmd/internal/sys" +) + +func simdARM64Intrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies ...sys.ArchFamily)) { + + addF(simdPackage, "Float32x4.Abs", opLen1(ssa.OpAbsFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Abs", opLen1(ssa.OpAbsFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Abs", opLen1(ssa.OpAbsInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Abs", opLen1(ssa.OpAbsInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Abs", opLen1(ssa.OpAbsInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.Abs", opLen1(ssa.OpAbsInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Add", opLen2(ssa.OpAddFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Add", opLen2(ssa.OpAddFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Add", opLen2(ssa.OpAddInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Add", opLen2(ssa.OpAddInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Add", opLen2(ssa.OpAddInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.Add", opLen2(ssa.OpAddInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Add", opLen2(ssa.OpAddUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Add", opLen2(ssa.OpAddUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Add", opLen2(ssa.OpAddUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.Add", opLen2(ssa.OpAddUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.AddSaturated", opLen2(ssa.OpAddSaturatedInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.AddSaturated", opLen2(ssa.OpAddSaturatedInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.AddSaturated", opLen2(ssa.OpAddSaturatedInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.AddSaturated", opLen2(ssa.OpAddSaturatedInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.AddSaturated", opLen2(ssa.OpAddSaturatedUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.AddSaturated", opLen2(ssa.OpAddSaturatedUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.AddSaturated", opLen2(ssa.OpAddSaturatedUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.AddSaturated", opLen2(ssa.OpAddSaturatedUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.And", opLen2(ssa.OpAndInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.And", opLen2(ssa.OpAndInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.And", opLen2(ssa.OpAndInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.And", opLen2(ssa.OpAndUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.And", opLen2(ssa.OpAndUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.And", opLen2(ssa.OpAndUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.And", opLen2(ssa.OpAndUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.AndNot", opLen2(ssa.OpAndNotInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.AndNot", opLen2(ssa.OpAndNotInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.AndNot", opLen2(ssa.OpAndNotInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.AndNot", opLen2(ssa.OpAndNotInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.AndNot", opLen2(ssa.OpAndNotUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.AndNot", opLen2(ssa.OpAndNotUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.AndNot", opLen2(ssa.OpAndNotUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.AndNot", opLen2(ssa.OpAndNotUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Average", opLen2(ssa.OpAverageInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Average", opLen2(ssa.OpAverageInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Average", opLen2(ssa.OpAverageInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Average", opLen2(ssa.OpAverageUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Average", opLen2(ssa.OpAverageUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Average", opLen2(ssa.OpAverageUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Ceil", opLen1(ssa.OpCeilFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Ceil", opLen1(ssa.OpCeilFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.ConcatAddPairs", opLen2(ssa.OpConcatAddPairsUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.ConcatEven", opLen2(ssa.OpConcatEvenInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.ConcatEven", opLen2(ssa.OpConcatEvenInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.ConcatEven", opLen2(ssa.OpConcatEvenInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.ConcatEven", opLen2(ssa.OpConcatEvenInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.ConcatEven", opLen2(ssa.OpConcatEvenUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.ConcatEven", opLen2(ssa.OpConcatEvenUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.ConcatEven", opLen2(ssa.OpConcatEvenUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.ConcatEven", opLen2(ssa.OpConcatEvenUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.ConcatOdd", opLen2(ssa.OpConcatOddInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.ConcatOdd", opLen2(ssa.OpConcatOddInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.ConcatOdd", opLen2(ssa.OpConcatOddInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.ConcatOdd", opLen2(ssa.OpConcatOddInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.ConcatOdd", opLen2(ssa.OpConcatOddUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.ConcatOdd", opLen2(ssa.OpConcatOddUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.ConcatOdd", opLen2(ssa.OpConcatOddUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.ConcatOdd", opLen2(ssa.OpConcatOddUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.ConcatShiftBytesRight", opLen2Imm_2I(ssa.OpConcatShiftBytesRightUint8x16, types.TypeVec128, 0, 15), sys.ARM64) + addF(simdPackage, "Float32x4.ConvertLo2ToFloat64", opLen1(ssa.OpConvertLo2ToFloat64Float32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Float64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Div", opLen2(ssa.OpDivFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Div", opLen2(ssa.OpDivFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Equal", opLen2(ssa.OpEqualFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Equal", opLen2(ssa.OpEqualFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Equal", opLen2(ssa.OpEqualInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Equal", opLen2(ssa.OpEqualInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Equal", opLen2(ssa.OpEqualInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.Equal", opLen2(ssa.OpEqualInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Equal", opLen2(ssa.OpEqualUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Equal", opLen2(ssa.OpEqualUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Equal", opLen2(ssa.OpEqualUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.Equal", opLen2(ssa.OpEqualUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.ExtendLo2ToInt64", opLen1(ssa.OpExtendLo2ToInt64Int32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.ExtendLo2ToUint64", opLen1(ssa.OpExtendLo2ToUint64Uint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.ExtendLo4ToInt32", opLen1(ssa.OpExtendLo4ToInt32Int16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.ExtendLo4ToUint32", opLen1(ssa.OpExtendLo4ToUint32Uint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.ExtendLo8ToInt16", opLen1(ssa.OpExtendLo8ToInt16Int8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.ExtendLo8ToUint16", opLen1(ssa.OpExtendLo8ToUint16Uint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Floor", opLen1(ssa.OpFloorFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Floor", opLen1(ssa.OpFloorFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.GetElem", opLen1Imm(ssa.OpGetElemFloat32x4, types.Types[types.TFLOAT32], 0, 3), sys.ARM64) + addF(simdPackage, "Float64x2.GetElem", opLen1Imm(ssa.OpGetElemFloat64x2, types.Types[types.TFLOAT64], 0, 1), sys.ARM64) + addF(simdPackage, "Int8x16.GetElem", opLen1Imm(ssa.OpGetElemInt8x16, types.Types[types.TINT8], 0, 15), sys.ARM64) + addF(simdPackage, "Int16x8.GetElem", opLen1Imm(ssa.OpGetElemInt16x8, types.Types[types.TINT16], 0, 7), sys.ARM64) + addF(simdPackage, "Int32x4.GetElem", opLen1Imm(ssa.OpGetElemInt32x4, types.Types[types.TINT32], 0, 3), sys.ARM64) + addF(simdPackage, "Int64x2.GetElem", opLen1Imm(ssa.OpGetElemInt64x2, types.Types[types.TINT64], 0, 1), sys.ARM64) + addF(simdPackage, "Uint8x16.GetElem", opLen1Imm(ssa.OpGetElemUint8x16, types.Types[types.TUINT8], 0, 15), sys.ARM64) + addF(simdPackage, "Uint16x8.GetElem", opLen1Imm(ssa.OpGetElemUint16x8, types.Types[types.TUINT16], 0, 7), sys.ARM64) + addF(simdPackage, "Uint32x4.GetElem", opLen1Imm(ssa.OpGetElemUint32x4, types.Types[types.TUINT32], 0, 3), sys.ARM64) + addF(simdPackage, "Uint64x2.GetElem", opLen1Imm(ssa.OpGetElemUint64x2, types.Types[types.TUINT64], 0, 1), sys.ARM64) + addF(simdPackage, "Float32x4.Greater", opLen2(ssa.OpGreaterFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Greater", opLen2(ssa.OpGreaterFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Greater", opLen2(ssa.OpGreaterInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Greater", opLen2(ssa.OpGreaterInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Greater", opLen2(ssa.OpGreaterInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.Greater", opLen2(ssa.OpGreaterInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Greater", opLen2(ssa.OpGreaterUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Greater", opLen2(ssa.OpGreaterUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Greater", opLen2(ssa.OpGreaterUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.Greater", opLen2(ssa.OpGreaterUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.GreaterEqual", opLen2(ssa.OpGreaterEqualInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.GreaterEqual", opLen2(ssa.OpGreaterEqualInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.GreaterEqual", opLen2(ssa.OpGreaterEqualInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.GreaterEqual", opLen2(ssa.OpGreaterEqualInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.GreaterEqual", opLen2(ssa.OpGreaterEqualUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.GreaterEqual", opLen2(ssa.OpGreaterEqualUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.GreaterEqual", opLen2(ssa.OpGreaterEqualUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.GreaterEqual", opLen2(ssa.OpGreaterEqualUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.InterleaveEven", opLen2(ssa.OpInterleaveEvenInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.InterleaveEven", opLen2(ssa.OpInterleaveEvenInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.InterleaveEven", opLen2(ssa.OpInterleaveEvenInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.InterleaveEven", opLen2(ssa.OpInterleaveEvenInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.InterleaveEven", opLen2(ssa.OpInterleaveEvenUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.InterleaveEven", opLen2(ssa.OpInterleaveEvenUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.InterleaveEven", opLen2(ssa.OpInterleaveEvenUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.InterleaveEven", opLen2(ssa.OpInterleaveEvenUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.InterleaveHi", opLen2(ssa.OpInterleaveHiInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.InterleaveHi", opLen2(ssa.OpInterleaveHiInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.InterleaveHi", opLen2(ssa.OpInterleaveHiInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.InterleaveHi", opLen2(ssa.OpInterleaveHiInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.InterleaveHi", opLen2(ssa.OpInterleaveHiUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.InterleaveHi", opLen2(ssa.OpInterleaveHiUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.InterleaveHi", opLen2(ssa.OpInterleaveHiUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.InterleaveHi", opLen2(ssa.OpInterleaveHiUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.InterleaveLo", opLen2(ssa.OpInterleaveLoInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.InterleaveLo", opLen2(ssa.OpInterleaveLoInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.InterleaveLo", opLen2(ssa.OpInterleaveLoInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.InterleaveLo", opLen2(ssa.OpInterleaveLoInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.InterleaveLo", opLen2(ssa.OpInterleaveLoUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.InterleaveLo", opLen2(ssa.OpInterleaveLoUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.InterleaveLo", opLen2(ssa.OpInterleaveLoUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.InterleaveLo", opLen2(ssa.OpInterleaveLoUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.InterleaveOdd", opLen2(ssa.OpInterleaveOddInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.InterleaveOdd", opLen2(ssa.OpInterleaveOddInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.InterleaveOdd", opLen2(ssa.OpInterleaveOddInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.InterleaveOdd", opLen2(ssa.OpInterleaveOddInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.InterleaveOdd", opLen2(ssa.OpInterleaveOddUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.InterleaveOdd", opLen2(ssa.OpInterleaveOddUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.InterleaveOdd", opLen2(ssa.OpInterleaveOddUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.InterleaveOdd", opLen2(ssa.OpInterleaveOddUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.LeadingSignBits", opLen1(ssa.OpLeadingSignBitsInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.LeadingSignBits", opLen1(ssa.OpLeadingSignBitsInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.LeadingSignBits", opLen1(ssa.OpLeadingSignBitsInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.LeadingSignBits", opLen1(ssa.OpLeadingSignBitsUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.LeadingSignBits", opLen1(ssa.OpLeadingSignBitsUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.LeadingSignBits", opLen1(ssa.OpLeadingSignBitsUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.LeadingZeros", opLen1(ssa.OpLeadingZerosInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.LeadingZeros", opLen1(ssa.OpLeadingZerosInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.LeadingZeros", opLen1(ssa.OpLeadingZerosInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.LeadingZeros", opLen1(ssa.OpLeadingZerosUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.LeadingZeros", opLen1(ssa.OpLeadingZerosUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.LeadingZeros", opLen1(ssa.OpLeadingZerosUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.LookupOrZero", opLen2(ssa.OpLookupOrZeroInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.LookupOrZero", opLen2(ssa.OpLookupOrZeroUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Max", opLen2(ssa.OpMaxFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Max", opLen2(ssa.OpMaxFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Max", opLen2(ssa.OpMaxInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Max", opLen2(ssa.OpMaxInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Max", opLen2(ssa.OpMaxInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Max", opLen2(ssa.OpMaxUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Max", opLen2(ssa.OpMaxUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Max", opLen2(ssa.OpMaxUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Min", opLen2(ssa.OpMinFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Min", opLen2(ssa.OpMinFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Min", opLen2(ssa.OpMinInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Min", opLen2(ssa.OpMinInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Min", opLen2(ssa.OpMinInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Min", opLen2(ssa.OpMinUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Min", opLen2(ssa.OpMinUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Min", opLen2(ssa.OpMinUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Mul", opLen2(ssa.OpMulFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Mul", opLen2(ssa.OpMulFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Mul", opLen2(ssa.OpMulInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Mul", opLen2(ssa.OpMulInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Mul", opLen2(ssa.OpMulInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Mul", opLen2(ssa.OpMulUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Mul", opLen2(ssa.OpMulUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Mul", opLen2(ssa.OpMulUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.MulAdd", opLen3(ssa.OpMulAddFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.MulAdd", opLen3(ssa.OpMulAddFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.MulAdd", opLen3(ssa.OpMulAddInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.MulAdd", opLen3(ssa.OpMulAddInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.MulAdd", opLen3(ssa.OpMulAddInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.MulAdd", opLen3(ssa.OpMulAddUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.MulAdd", opLen3(ssa.OpMulAddUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.MulAdd", opLen3(ssa.OpMulAddUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.MulWidenLo", opLen2(ssa.OpMulWidenLoInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.MulWidenLo", opLen2(ssa.OpMulWidenLoInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.MulWidenLo", opLen2(ssa.OpMulWidenLoInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.MulWidenLo", opLen2(ssa.OpMulWidenLoUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.MulWidenLo", opLen2(ssa.OpMulWidenLoUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.MulWidenLo", opLen2(ssa.OpMulWidenLoUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Neg", opLen1(ssa.OpNegFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Neg", opLen1(ssa.OpNegFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Neg", opLen1(ssa.OpNegInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Neg", opLen1(ssa.OpNegInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Neg", opLen1(ssa.OpNegInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.Neg", opLen1(ssa.OpNegInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Not", opLen1(ssa.OpNotInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Not", opLen1(ssa.OpNotInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Not", opLen1(ssa.OpNotInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.Not", opLen1(ssa.OpNotInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Not", opLen1(ssa.OpNotUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Not", opLen1(ssa.OpNotUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Not", opLen1(ssa.OpNotUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.Not", opLen1(ssa.OpNotUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.OnesCount", opLen1(ssa.OpOnesCountInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.OnesCount", opLen1(ssa.OpOnesCountUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Or", opLen2(ssa.OpOrInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Or", opLen2(ssa.OpOrInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.Or", opLen2(ssa.OpOrInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Or", opLen2(ssa.OpOrUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Or", opLen2(ssa.OpOrUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Or", opLen2(ssa.OpOrUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.Or", opLen2(ssa.OpOrUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.OrNot", opLen2(ssa.OpOrNotInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.OrNot", opLen2(ssa.OpOrNotInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.OrNot", opLen2(ssa.OpOrNotInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.OrNot", opLen2(ssa.OpOrNotInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.OrNot", opLen2(ssa.OpOrNotUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.OrNot", opLen2(ssa.OpOrNotUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.OrNot", opLen2(ssa.OpOrNotUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.OrNot", opLen2(ssa.OpOrNotUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Round", opLen1(ssa.OpRoundFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Round", opLen1(ssa.OpRoundFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.SaturateToInt8", opLen1(ssa.OpSaturateToInt8Int16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.SaturateToInt16", opLen1(ssa.OpSaturateToInt16Int32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.SaturateToInt32", opLen1(ssa.OpSaturateToInt32Int64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Int16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.SaturateToUint8", opLen1(ssa.OpSaturateToUint8Uint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Int32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Uint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.SaturateToUint32", opLen1(ssa.OpSaturateToUint32Int64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.SaturateToUint32", opLen1(ssa.OpSaturateToUint32Uint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.SetElem", opLen2Imm(ssa.OpSetElemInt8x16, types.TypeVec128, 0, 15), sys.ARM64) + addF(simdPackage, "Int16x8.SetElem", opLen2Imm(ssa.OpSetElemInt16x8, types.TypeVec128, 0, 7), sys.ARM64) + addF(simdPackage, "Int32x4.SetElem", opLen2Imm(ssa.OpSetElemInt32x4, types.TypeVec128, 0, 3), sys.ARM64) + addF(simdPackage, "Int64x2.SetElem", opLen2Imm(ssa.OpSetElemInt64x2, types.TypeVec128, 0, 1), sys.ARM64) + addF(simdPackage, "Uint8x16.SetElem", opLen2Imm(ssa.OpSetElemUint8x16, types.TypeVec128, 0, 15), sys.ARM64) + addF(simdPackage, "Uint16x8.SetElem", opLen2Imm(ssa.OpSetElemUint16x8, types.TypeVec128, 0, 7), sys.ARM64) + addF(simdPackage, "Uint32x4.SetElem", opLen2Imm(ssa.OpSetElemUint32x4, types.TypeVec128, 0, 3), sys.ARM64) + addF(simdPackage, "Uint64x2.SetElem", opLen2Imm(ssa.OpSetElemUint64x2, types.TypeVec128, 0, 1), sys.ARM64) + addF(simdPackage, "Float32x4.SetElem", opLen2Imm(ssa.OpSetElemFloat32x4, types.TypeVec128, 0, 3), sys.ARM64) + addF(simdPackage, "Float64x2.SetElem", opLen2Imm(ssa.OpSetElemFloat64x2, types.TypeVec128, 0, 1), sys.ARM64) + addF(simdPackage, "Int8x16.Shift", opLen2(ssa.OpShiftInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Shift", opLen2(ssa.OpShiftInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Shift", opLen2(ssa.OpShiftInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.Shift", opLen2(ssa.OpShiftInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Shift", opLen2(ssa.OpShiftUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Shift", opLen2(ssa.OpShiftUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Shift", opLen2(ssa.OpShiftUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.Shift", opLen2(ssa.OpShiftUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.ShiftSaturated", opLen2(ssa.OpShiftSaturatedInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.ShiftSaturated", opLen2(ssa.OpShiftSaturatedInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.ShiftSaturated", opLen2(ssa.OpShiftSaturatedInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.ShiftSaturated", opLen2(ssa.OpShiftSaturatedInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.ShiftSaturated", opLen2(ssa.OpShiftSaturatedUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.ShiftSaturated", opLen2(ssa.OpShiftSaturatedUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.ShiftSaturated", opLen2(ssa.OpShiftSaturatedUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.ShiftSaturated", opLen2(ssa.OpShiftSaturatedUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Sqrt", opLen1(ssa.OpSqrtFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Sqrt", opLen1(ssa.OpSqrtFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Sub", opLen2(ssa.OpSubFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Sub", opLen2(ssa.OpSubFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Sub", opLen2(ssa.OpSubInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Sub", opLen2(ssa.OpSubInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Sub", opLen2(ssa.OpSubInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.Sub", opLen2(ssa.OpSubInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Sub", opLen2(ssa.OpSubUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Sub", opLen2(ssa.OpSubUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Sub", opLen2(ssa.OpSubUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.Sub", opLen2(ssa.OpSubUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.SubSaturated", opLen2(ssa.OpSubSaturatedInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.SubSaturated", opLen2(ssa.OpSubSaturatedInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.SubSaturated", opLen2(ssa.OpSubSaturatedInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.SubSaturated", opLen2(ssa.OpSubSaturatedInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.SubSaturated", opLen2(ssa.OpSubSaturatedUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.SubSaturated", opLen2(ssa.OpSubSaturatedUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.SubSaturated", opLen2(ssa.OpSubSaturatedUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.SubSaturated", opLen2(ssa.OpSubSaturatedUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.Trunc", opLen1(ssa.OpTruncFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.Trunc", opLen1(ssa.OpTruncFloat64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.TruncToInt8", opLen1(ssa.OpTruncToInt8Int16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.TruncToInt16", opLen1(ssa.OpTruncToInt16Int32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.TruncToInt32", opLen1(ssa.OpTruncToInt32Int64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.TruncToUint8", opLen1(ssa.OpTruncToUint8Uint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.TruncToUint16", opLen1(ssa.OpTruncToUint16Uint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.TruncToUint32", opLen1(ssa.OpTruncToUint32Uint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.Xor", opLen2(ssa.OpXorInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.Xor", opLen2(ssa.OpXorInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.Xor", opLen2(ssa.OpXorInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.Xor", opLen2(ssa.OpXorInt64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.Xor", opLen2(ssa.OpXorUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.Xor", opLen2(ssa.OpXorUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.Xor", opLen2(ssa.OpXorUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.Xor", opLen2(ssa.OpXorUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.bitSelect", opLen3(ssa.OpbitSelectInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.bitSelectNot", opLen3(ssa.OpbitSelectNotInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float64x2.broadcast1To2", opLen1(ssa.Opbroadcast1To2Float64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int64x2.broadcast1To2", opLen1(ssa.Opbroadcast1To2Int64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.broadcast1To2", opLen1(ssa.Opbroadcast1To2Uint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.broadcast1To4", opLen1(ssa.Opbroadcast1To4Float32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.broadcast1To4", opLen1(ssa.Opbroadcast1To4Int32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.broadcast1To4", opLen1(ssa.Opbroadcast1To4Uint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.broadcast1To8", opLen1(ssa.Opbroadcast1To8Int16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.broadcast1To8", opLen1(ssa.Opbroadcast1To8Uint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.broadcast1To16", opLen1(ssa.Opbroadcast1To16Int8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.broadcast1To16", opLen1(ssa.Opbroadcast1To16Uint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint64x2.carrylessMultiplyWidenLo", opLen2(ssa.OpcarrylessMultiplyWidenLoUint64x2, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.reduceMax", opLen1(ssa.OpreduceMaxFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.reduceMax", opLen1(ssa.OpreduceMaxInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.reduceMax", opLen1(ssa.OpreduceMaxInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.reduceMax", opLen1(ssa.OpreduceMaxInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.reduceMax", opLen1(ssa.OpreduceMaxUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.reduceMax", opLen1(ssa.OpreduceMaxUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.reduceMax", opLen1(ssa.OpreduceMaxUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.reduceMin", opLen1(ssa.OpreduceMinFloat32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.reduceMin", opLen1(ssa.OpreduceMinInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.reduceMin", opLen1(ssa.OpreduceMinInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.reduceMin", opLen1(ssa.OpreduceMinInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.reduceMin", opLen1(ssa.OpreduceMinUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.reduceMin", opLen1(ssa.OpreduceMinUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.reduceMin", opLen1(ssa.OpreduceMinUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int8x16.reduceSum", opLen1(ssa.OpreduceSumInt8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int16x8.reduceSum", opLen1(ssa.OpreduceSumInt16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Int32x4.reduceSum", opLen1(ssa.OpreduceSumInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint8x16.reduceSum", opLen1(ssa.OpreduceSumUint8x16, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint16x8.reduceSum", opLen1(ssa.OpreduceSumUint16x8, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Uint32x4.reduceSum", opLen1(ssa.OpreduceSumUint32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Float32x4.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float32x4.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float32x4.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float32x4.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float32x4.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float32x4.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float32x4.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float32x4.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float32x4.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float64x2.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float64x2.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float64x2.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float64x2.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float64x2.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float64x2.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float64x2.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float64x2.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float64x2.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.BitsToInt8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.ConvertToInt8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.ConvertToUint8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint8x16.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.BitsToInt16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.ConvertToInt16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.ConvertToUint16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint16x8.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.BitsToFloat32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float32x4.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.BitsToInt32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.ConvertToInt32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.ConvertToUint32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint32x4.ReshapeToUint64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.BitsToFloat64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Float64x2.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.BitsToInt64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.ConvertToInt64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.ConvertToUint64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.ToBits", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.ReshapeToUint8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.ReshapeToUint16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Uint64x2.ReshapeToUint32s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "LoadFloat32x4Array", simdLoad(), sys.ARM64) + addF(simdPackage, "Float32x4.StoreArray", simdStore(), sys.ARM64) + addF(simdPackage, "LoadFloat64x2Array", simdLoad(), sys.ARM64) + addF(simdPackage, "Float64x2.StoreArray", simdStore(), sys.ARM64) + addF(simdPackage, "LoadInt8x16Array", simdLoad(), sys.ARM64) + addF(simdPackage, "Int8x16.StoreArray", simdStore(), sys.ARM64) + addF(simdPackage, "LoadInt16x8Array", simdLoad(), sys.ARM64) + addF(simdPackage, "Int16x8.StoreArray", simdStore(), sys.ARM64) + addF(simdPackage, "LoadInt32x4Array", simdLoad(), sys.ARM64) + addF(simdPackage, "Int32x4.StoreArray", simdStore(), sys.ARM64) + addF(simdPackage, "LoadInt64x2Array", simdLoad(), sys.ARM64) + addF(simdPackage, "Int64x2.StoreArray", simdStore(), sys.ARM64) + addF(simdPackage, "LoadUint8x16Array", simdLoad(), sys.ARM64) + addF(simdPackage, "Uint8x16.StoreArray", simdStore(), sys.ARM64) + addF(simdPackage, "LoadUint16x8Array", simdLoad(), sys.ARM64) + addF(simdPackage, "Uint16x8.StoreArray", simdStore(), sys.ARM64) + addF(simdPackage, "LoadUint32x4Array", simdLoad(), sys.ARM64) + addF(simdPackage, "Uint32x4.StoreArray", simdStore(), sys.ARM64) + addF(simdPackage, "LoadUint64x2Array", simdLoad(), sys.ARM64) + addF(simdPackage, "Uint64x2.StoreArray", simdStore(), sys.ARM64) + addF(simdPackage, "Mask8x16.ToInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int8x16.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Mask8x16.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask8x16.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask8x16.Not", opLen1(ssa.OpNotInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask16x8.ToInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int16x8.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Mask16x8.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask16x8.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask16x8.Not", opLen1(ssa.OpNotInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask32x4.ToInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int32x4.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Mask32x4.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask32x4.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask32x4.Not", opLen1(ssa.OpNotInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask64x2.ToInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Int64x2.asMask", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) + addF(simdPackage, "Mask64x2.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask64x2.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.ARM64) + addF(simdPackage, "Mask64x2.Not", opLen1(ssa.OpNotInt32x4, types.TypeVec128), sys.ARM64) +} diff --git a/src/cmd/compile/internal/ssagen/simdWasmintrinsics.go b/src/cmd/compile/internal/ssagen/simdWasmintrinsics.go new file mode 100644 index 00000000000000..9a92cf8eedbe83 --- /dev/null +++ b/src/cmd/compile/internal/ssagen/simdWasmintrinsics.go @@ -0,0 +1,515 @@ +// Code generated by 'wasmgen'; DO NOT EDIT. + +package ssagen + +import ( + "cmd/compile/internal/ir" + "cmd/compile/internal/ssa" + "cmd/compile/internal/types" + "cmd/internal/sys" +) + +func initWasmSIMD() { + makeSimdOp1 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue1(op, types.TypeVec128, args[0]) + } + } + makeSimdOp2 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue2(op, types.TypeVec128, args[0], args[1]) + } + } + makeSimdOp3 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue3(op, types.TypeVec128, args[0], args[1], args[2]) + } + } + + // "As" is a type pun, just return the bits + makeAsOp := func() func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return args[0] + } + } + + // converting to a mask is an not-equals comparison with zero, zero obtained by x XOR x. + makeToMask := func(op, xor ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue2(op, types.TypeVec128, args[0], s.newValue2(xor, n.Type(), args[0], args[0])) + } + } + + makeSimdOp1Imm8 := func(op ssa.Op, immLimit uint64) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + t := n.Type() + if args[1].Op == ssa.OpConst8 && uint64(args[1].AuxInt) < immLimit { + return s.newValue1I(op, t, args[1].AuxInt, args[0]) + } + return immJumpTableN(s, args[1], n, immLimit, func(sNew *state, idx int) { + // Encode as int8 due to requirement of AuxInt, check its comment for details. + s.vars[n] = sNew.newValue1I(op, t, int64(int8(idx)), args[0]) + }) + } + } + + makeSimdOp2Imm8 := func(op ssa.Op, immLimit uint64) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + t := types.TypeVec128 + if args[1].Op == ssa.OpConst8 && uint64(args[1].AuxInt) < immLimit { + return s.newValue2I(op, t, args[1].AuxInt, args[0], args[2]) + } + return immJumpTableN(s, args[1], n, immLimit, func(sNew *state, idx int) { + // Encode as int8 due to requirement of AuxInt, check its comment for details. + s.vars[n] = sNew.newValue2I(op, t, int64(int8(idx)), args[0], args[2]) + }) + } + } + + addWasmSIMD := func(pkg, fn string, builder func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value) { + intrinsics.add(sys.ArchWasm, pkg, fn, builder) + } + + addWasmSIMD("simd/archsimd", "Int8x16.Abs", makeSimdOp1(ssa.OpAbsInt8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Abs", makeSimdOp1(ssa.OpAbsInt16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Abs", makeSimdOp1(ssa.OpAbsInt32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Abs", makeSimdOp1(ssa.OpAbsFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Abs", makeSimdOp1(ssa.OpAbsInt64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.Abs", makeSimdOp1(ssa.OpAbsFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.Add", makeSimdOp2(ssa.OpAddInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.Add", makeSimdOp2(ssa.OpAddInt8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Add", makeSimdOp2(ssa.OpAddInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Add", makeSimdOp2(ssa.OpAddInt16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Add", makeSimdOp2(ssa.OpAddInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Add", makeSimdOp2(ssa.OpAddInt32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Add", makeSimdOp2(ssa.OpAddFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Add", makeSimdOp2(ssa.OpAddInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.Add", makeSimdOp2(ssa.OpAddInt64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.Add", makeSimdOp2(ssa.OpAddFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedUint16x8)) + addWasmSIMD("simd/archsimd", "Int8x16.And", makeSimdOp2(ssa.OpAndInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.And", makeSimdOp2(ssa.OpAndUint8x16)) + addWasmSIMD("simd/archsimd", "Mask8x16.And", makeSimdOp2(ssa.OpAndInt8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.And", makeSimdOp2(ssa.OpAndInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.And", makeSimdOp2(ssa.OpAndUint16x8)) + addWasmSIMD("simd/archsimd", "Mask16x8.And", makeSimdOp2(ssa.OpAndInt16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.And", makeSimdOp2(ssa.OpAndInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.And", makeSimdOp2(ssa.OpAndUint32x4)) + addWasmSIMD("simd/archsimd", "Mask32x4.And", makeSimdOp2(ssa.OpAndInt32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.And", makeSimdOp2(ssa.OpAndInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.And", makeSimdOp2(ssa.OpAndUint64x2)) + addWasmSIMD("simd/archsimd", "Mask64x2.And", makeSimdOp2(ssa.OpAndInt64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.AndNot", makeSimdOp2(ssa.OpAndNotInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.AndNot", makeSimdOp2(ssa.OpAndNotUint8x16)) + addWasmSIMD("simd/archsimd", "Mask8x16.AndNot", makeSimdOp2(ssa.OpAndNotInt8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.AndNot", makeSimdOp2(ssa.OpAndNotInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.AndNot", makeSimdOp2(ssa.OpAndNotUint16x8)) + addWasmSIMD("simd/archsimd", "Mask16x8.AndNot", makeSimdOp2(ssa.OpAndNotInt16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.AndNot", makeSimdOp2(ssa.OpAndNotInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.AndNot", makeSimdOp2(ssa.OpAndNotUint32x4)) + addWasmSIMD("simd/archsimd", "Mask32x4.AndNot", makeSimdOp2(ssa.OpAndNotInt32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.AndNot", makeSimdOp2(ssa.OpAndNotInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.AndNot", makeSimdOp2(ssa.OpAndNotUint64x2)) + addWasmSIMD("simd/archsimd", "Mask64x2.AndNot", makeSimdOp2(ssa.OpAndNotInt64x2)) + addWasmSIMD("simd/archsimd", "Uint8x16.Average", makeSimdOp2(ssa.OpAverageUint8x16)) + addWasmSIMD("simd/archsimd", "Uint16x8.Average", makeSimdOp2(ssa.OpAverageUint16x8)) + addWasmSIMD("simd/archsimd", "Int8x16.BitSelect", makeSimdOp3(ssa.OpBitSelectInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.BitSelect", makeSimdOp3(ssa.OpBitSelectUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.BitSelect", makeSimdOp3(ssa.OpBitSelectInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.BitSelect", makeSimdOp3(ssa.OpBitSelectUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.BitSelect", makeSimdOp3(ssa.OpBitSelectInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.BitSelect", makeSimdOp3(ssa.OpBitSelectUint32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.BitSelect", makeSimdOp3(ssa.OpBitSelectInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.BitSelect", makeSimdOp3(ssa.OpBitSelectUint64x2)) + addWasmSIMD("simd/archsimd", "Float32x4.Ceil", makeSimdOp1(ssa.OpCeilFloat32x4)) + addWasmSIMD("simd/archsimd", "Float64x2.Ceil", makeSimdOp1(ssa.OpCeilFloat64x2)) + addWasmSIMD("simd/archsimd", "Int32x4.ConvertLo2ToFloat64", makeSimdOp1(ssa.OpConvertLo2ToFloat64Int32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.ConvertLo2ToFloat64", makeSimdOp1(ssa.OpConvertLo2ToFloat64Uint32x4)) + addWasmSIMD("simd/archsimd", "Int32x4.ConvertToFloat32", makeSimdOp1(ssa.OpConvertToFloat32Int32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.ConvertToFloat32", makeSimdOp1(ssa.OpConvertToFloat32Uint32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.ConvertToInt32", makeSimdOp1(ssa.OpConvertToInt32Float32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.ConvertToUint32", makeSimdOp1(ssa.OpConvertToUint32Float32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Div", makeSimdOp2(ssa.OpDivFloat32x4)) + addWasmSIMD("simd/archsimd", "Float64x2.Div", makeSimdOp2(ssa.OpDivFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.Equal", makeSimdOp2(ssa.OpEqualInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.Equal", makeSimdOp2(ssa.OpEqualUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Equal", makeSimdOp2(ssa.OpEqualInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Equal", makeSimdOp2(ssa.OpEqualUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Equal", makeSimdOp2(ssa.OpEqualInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Equal", makeSimdOp2(ssa.OpEqualUint32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Equal", makeSimdOp2(ssa.OpEqualFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Equal", makeSimdOp2(ssa.OpEqualInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.Equal", makeSimdOp2(ssa.OpEqualUint64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.Equal", makeSimdOp2(ssa.OpEqualFloat64x2)) + addWasmSIMD("simd/archsimd", "Int32x4.ExtendHi2ToInt64", makeSimdOp1(ssa.OpExtendHi2ToInt64Int32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.ExtendHi2ToUint64", makeSimdOp1(ssa.OpExtendHi2ToUint64Uint32x4)) + addWasmSIMD("simd/archsimd", "Int16x8.ExtendHi4ToInt32", makeSimdOp1(ssa.OpExtendHi4ToInt32Int16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.ExtendHi4ToUint32", makeSimdOp1(ssa.OpExtendHi4ToUint32Uint16x8)) + addWasmSIMD("simd/archsimd", "Int8x16.ExtendHi8ToInt16", makeSimdOp1(ssa.OpExtendHi8ToInt16Int8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.ExtendHi8ToUint16", makeSimdOp1(ssa.OpExtendHi8ToUint16Uint8x16)) + addWasmSIMD("simd/archsimd", "Int32x4.ExtendLo2ToInt64", makeSimdOp1(ssa.OpExtendLo2ToInt64Int32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.ExtendLo2ToUint64", makeSimdOp1(ssa.OpExtendLo2ToUint64Uint32x4)) + addWasmSIMD("simd/archsimd", "Int16x8.ExtendLo4ToInt32", makeSimdOp1(ssa.OpExtendLo4ToInt32Int16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.ExtendLo4ToUint32", makeSimdOp1(ssa.OpExtendLo4ToUint32Uint16x8)) + addWasmSIMD("simd/archsimd", "Int8x16.ExtendLo8ToInt16", makeSimdOp1(ssa.OpExtendLo8ToInt16Int8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.ExtendLo8ToUint16", makeSimdOp1(ssa.OpExtendLo8ToUint16Uint8x16)) + addWasmSIMD("simd/archsimd", "Float32x4.Floor", makeSimdOp1(ssa.OpFloorFloat32x4)) + addWasmSIMD("simd/archsimd", "Float64x2.Floor", makeSimdOp1(ssa.OpFloorFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt8x16, 16)) + addWasmSIMD("simd/archsimd", "Uint8x16.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint8x16, 16)) + addWasmSIMD("simd/archsimd", "Int16x8.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt16x8, 8)) + addWasmSIMD("simd/archsimd", "Uint16x8.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint16x8, 8)) + addWasmSIMD("simd/archsimd", "Int32x4.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt32x4, 4)) + addWasmSIMD("simd/archsimd", "Uint32x4.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint32x4, 4)) + addWasmSIMD("simd/archsimd", "Float32x4.GetElem", makeSimdOp1Imm8(ssa.OpGetElemFloat32x4, 4)) + addWasmSIMD("simd/archsimd", "Int64x2.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt64x2, 2)) + addWasmSIMD("simd/archsimd", "Uint64x2.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint64x2, 2)) + addWasmSIMD("simd/archsimd", "Float64x2.GetElem", makeSimdOp1Imm8(ssa.OpGetElemFloat64x2, 2)) + addWasmSIMD("simd/archsimd", "Int8x16.Greater", makeSimdOp2(ssa.OpGreaterInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.Greater", makeSimdOp2(ssa.OpGreaterUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Greater", makeSimdOp2(ssa.OpGreaterInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Greater", makeSimdOp2(ssa.OpGreaterUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Greater", makeSimdOp2(ssa.OpGreaterInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Greater", makeSimdOp2(ssa.OpGreaterUint32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Greater", makeSimdOp2(ssa.OpGreaterFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Greater", makeSimdOp2(ssa.OpGreaterInt64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.Greater", makeSimdOp2(ssa.OpGreaterFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualUint32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.Less", makeSimdOp2(ssa.OpLessInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.Less", makeSimdOp2(ssa.OpLessUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Less", makeSimdOp2(ssa.OpLessInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Less", makeSimdOp2(ssa.OpLessUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Less", makeSimdOp2(ssa.OpLessInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Less", makeSimdOp2(ssa.OpLessUint32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Less", makeSimdOp2(ssa.OpLessFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Less", makeSimdOp2(ssa.OpLessInt64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.Less", makeSimdOp2(ssa.OpLessFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.LessEqual", makeSimdOp2(ssa.OpLessEqualInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.LessEqual", makeSimdOp2(ssa.OpLessEqualUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.LessEqual", makeSimdOp2(ssa.OpLessEqualInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.LessEqual", makeSimdOp2(ssa.OpLessEqualUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.LessEqual", makeSimdOp2(ssa.OpLessEqualInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.LessEqual", makeSimdOp2(ssa.OpLessEqualUint32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.LessEqual", makeSimdOp2(ssa.OpLessEqualFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.LessEqual", makeSimdOp2(ssa.OpLessEqualInt64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.LessEqual", makeSimdOp2(ssa.OpLessEqualFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.LookupOrZero", makeSimdOp2(ssa.OpLookupOrZeroInt8x16)) + addWasmSIMD("simd/archsimd", "Int8x16.Max", makeSimdOp2(ssa.OpMaxInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.Max", makeSimdOp2(ssa.OpMaxUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Max", makeSimdOp2(ssa.OpMaxInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Max", makeSimdOp2(ssa.OpMaxUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Max", makeSimdOp2(ssa.OpMaxInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Max", makeSimdOp2(ssa.OpMaxUint32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Max", makeSimdOp2(ssa.OpMaxFloat32x4)) + addWasmSIMD("simd/archsimd", "Float64x2.Max", makeSimdOp2(ssa.OpMaxFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.Min", makeSimdOp2(ssa.OpMinInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.Min", makeSimdOp2(ssa.OpMinUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Min", makeSimdOp2(ssa.OpMinInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Min", makeSimdOp2(ssa.OpMinUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Min", makeSimdOp2(ssa.OpMinInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Min", makeSimdOp2(ssa.OpMinUint32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Min", makeSimdOp2(ssa.OpMinFloat32x4)) + addWasmSIMD("simd/archsimd", "Float64x2.Min", makeSimdOp2(ssa.OpMinFloat64x2)) + addWasmSIMD("simd/archsimd", "Int16x8.Mul", makeSimdOp2(ssa.OpMulInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Mul", makeSimdOp2(ssa.OpMulUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Mul", makeSimdOp2(ssa.OpMulInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Mul", makeSimdOp2(ssa.OpMulUint32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Mul", makeSimdOp2(ssa.OpMulFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Mul", makeSimdOp2(ssa.OpMulInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.Mul", makeSimdOp2(ssa.OpMulUint64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.Mul", makeSimdOp2(ssa.OpMulFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiUint32x4)) + addWasmSIMD("simd/archsimd", "Int8x16.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoUint32x4)) + addWasmSIMD("simd/archsimd", "Int8x16.Neg", makeSimdOp1(ssa.OpNegInt8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Neg", makeSimdOp1(ssa.OpNegInt16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Neg", makeSimdOp1(ssa.OpNegInt32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Neg", makeSimdOp1(ssa.OpNegFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Neg", makeSimdOp1(ssa.OpNegInt64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.Neg", makeSimdOp1(ssa.OpNegFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.Not", makeSimdOp1(ssa.OpNotInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.Not", makeSimdOp1(ssa.OpNotUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Not", makeSimdOp1(ssa.OpNotInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Not", makeSimdOp1(ssa.OpNotUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Not", makeSimdOp1(ssa.OpNotInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Not", makeSimdOp1(ssa.OpNotUint32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Not", makeSimdOp1(ssa.OpNotInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.Not", makeSimdOp1(ssa.OpNotUint64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.NotEqual", makeSimdOp2(ssa.OpNotEqualInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.NotEqual", makeSimdOp2(ssa.OpNotEqualUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.NotEqual", makeSimdOp2(ssa.OpNotEqualInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.NotEqual", makeSimdOp2(ssa.OpNotEqualUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.NotEqual", makeSimdOp2(ssa.OpNotEqualInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.NotEqual", makeSimdOp2(ssa.OpNotEqualUint32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.NotEqual", makeSimdOp2(ssa.OpNotEqualFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.NotEqual", makeSimdOp2(ssa.OpNotEqualInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.NotEqual", makeSimdOp2(ssa.OpNotEqualUint64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.NotEqual", makeSimdOp2(ssa.OpNotEqualFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.OnesCount", makeSimdOp1(ssa.OpOnesCountInt8x16)) + addWasmSIMD("simd/archsimd", "Int8x16.Or", makeSimdOp2(ssa.OpOrInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.Or", makeSimdOp2(ssa.OpOrUint8x16)) + addWasmSIMD("simd/archsimd", "Mask8x16.Or", makeSimdOp2(ssa.OpOrInt8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Or", makeSimdOp2(ssa.OpOrInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Or", makeSimdOp2(ssa.OpOrUint16x8)) + addWasmSIMD("simd/archsimd", "Mask16x8.Or", makeSimdOp2(ssa.OpOrInt16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Or", makeSimdOp2(ssa.OpOrInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Or", makeSimdOp2(ssa.OpOrUint32x4)) + addWasmSIMD("simd/archsimd", "Mask32x4.Or", makeSimdOp2(ssa.OpOrInt32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Or", makeSimdOp2(ssa.OpOrInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.Or", makeSimdOp2(ssa.OpOrUint64x2)) + addWasmSIMD("simd/archsimd", "Mask64x2.Or", makeSimdOp2(ssa.OpOrInt64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint64x2)) + addWasmSIMD("simd/archsimd", "Float32x4.Round", makeSimdOp1(ssa.OpRoundFloat32x4)) + addWasmSIMD("simd/archsimd", "Float64x2.Round", makeSimdOp1(ssa.OpRoundFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt8x16, 16)) + addWasmSIMD("simd/archsimd", "Uint8x16.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint8x16, 16)) + addWasmSIMD("simd/archsimd", "Int16x8.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt16x8, 8)) + addWasmSIMD("simd/archsimd", "Uint16x8.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint16x8, 8)) + addWasmSIMD("simd/archsimd", "Int32x4.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt32x4, 4)) + addWasmSIMD("simd/archsimd", "Uint32x4.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint32x4, 4)) + addWasmSIMD("simd/archsimd", "Float32x4.SetElem", makeSimdOp2Imm8(ssa.OpSetElemFloat32x4, 4)) + addWasmSIMD("simd/archsimd", "Int64x2.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt64x2, 2)) + addWasmSIMD("simd/archsimd", "Uint64x2.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint64x2, 2)) + addWasmSIMD("simd/archsimd", "Float64x2.SetElem", makeSimdOp2Imm8(ssa.OpSetElemFloat64x2, 2)) + addWasmSIMD("simd/archsimd", "Int8x16.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint64x2)) + addWasmSIMD("simd/archsimd", "Float32x4.Sqrt", makeSimdOp1(ssa.OpSqrtFloat32x4)) + addWasmSIMD("simd/archsimd", "Float64x2.Sqrt", makeSimdOp1(ssa.OpSqrtFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.Sub", makeSimdOp2(ssa.OpSubInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.Sub", makeSimdOp2(ssa.OpSubInt8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Sub", makeSimdOp2(ssa.OpSubInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Sub", makeSimdOp2(ssa.OpSubInt16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Sub", makeSimdOp2(ssa.OpSubInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Sub", makeSimdOp2(ssa.OpSubInt32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.Sub", makeSimdOp2(ssa.OpSubFloat32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Sub", makeSimdOp2(ssa.OpSubInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.Sub", makeSimdOp2(ssa.OpSubInt64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.Sub", makeSimdOp2(ssa.OpSubFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedUint8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedUint16x8)) + addWasmSIMD("simd/archsimd", "Float32x4.Trunc", makeSimdOp1(ssa.OpTruncFloat32x4)) + addWasmSIMD("simd/archsimd", "Float64x2.Trunc", makeSimdOp1(ssa.OpTruncFloat64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.Xor", makeSimdOp2(ssa.OpXorInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.Xor", makeSimdOp2(ssa.OpXorUint8x16)) + addWasmSIMD("simd/archsimd", "Mask8x16.Xor", makeSimdOp2(ssa.OpXorInt8x16)) + addWasmSIMD("simd/archsimd", "Int16x8.Xor", makeSimdOp2(ssa.OpXorInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.Xor", makeSimdOp2(ssa.OpXorUint16x8)) + addWasmSIMD("simd/archsimd", "Mask16x8.Xor", makeSimdOp2(ssa.OpXorInt16x8)) + addWasmSIMD("simd/archsimd", "Int32x4.Xor", makeSimdOp2(ssa.OpXorInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.Xor", makeSimdOp2(ssa.OpXorUint32x4)) + addWasmSIMD("simd/archsimd", "Mask32x4.Xor", makeSimdOp2(ssa.OpXorInt32x4)) + addWasmSIMD("simd/archsimd", "Int64x2.Xor", makeSimdOp2(ssa.OpXorInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.Xor", makeSimdOp2(ssa.OpXorUint64x2)) + addWasmSIMD("simd/archsimd", "Mask64x2.Xor", makeSimdOp2(ssa.OpXorInt64x2)) + addWasmSIMD("simd/archsimd", "Int8x16.ToMask", makeToMask(ssa.OpNotEqualInt8x16, ssa.OpXorInt8x16)) + addWasmSIMD("simd/archsimd", "Mask8x16.ToInt8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.ToMask", makeToMask(ssa.OpNotEqualInt16x8, ssa.OpXorInt16x8)) + addWasmSIMD("simd/archsimd", "Mask16x8.ToInt16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.ToMask", makeToMask(ssa.OpNotEqualInt32x4, ssa.OpXorInt32x4)) + addWasmSIMD("simd/archsimd", "Mask32x4.ToInt32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.ToMask", makeToMask(ssa.OpNotEqualInt64x2, ssa.OpXorInt64x2)) + addWasmSIMD("simd/archsimd", "Mask64x2.ToInt64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "LoadInt8x16Array", simdLoad()) + addWasmSIMD("simd/archsimd", "BroadcastInt8x16", simdBroadcast(ssa.OpBroadcastInt8x16)) + addWasmSIMD("simd/archsimd", "Int8x16.StoreArray", simdStore()) + addWasmSIMD("simd/archsimd", "LoadInt16x8Array", simdLoad()) + addWasmSIMD("simd/archsimd", "BroadcastInt16x8", simdBroadcast(ssa.OpBroadcastInt16x8)) + addWasmSIMD("simd/archsimd", "Int16x8.StoreArray", simdStore()) + addWasmSIMD("simd/archsimd", "LoadInt32x4Array", simdLoad()) + addWasmSIMD("simd/archsimd", "BroadcastInt32x4", simdBroadcast(ssa.OpBroadcastInt32x4)) + addWasmSIMD("simd/archsimd", "Int32x4.StoreArray", simdStore()) + addWasmSIMD("simd/archsimd", "LoadInt64x2Array", simdLoad()) + addWasmSIMD("simd/archsimd", "BroadcastInt64x2", simdBroadcast(ssa.OpBroadcastInt64x2)) + addWasmSIMD("simd/archsimd", "Int64x2.StoreArray", simdStore()) + addWasmSIMD("simd/archsimd", "LoadUint8x16Array", simdLoad()) + addWasmSIMD("simd/archsimd", "BroadcastUint8x16", simdBroadcast(ssa.OpBroadcastInt8x16)) + addWasmSIMD("simd/archsimd", "Uint8x16.StoreArray", simdStore()) + addWasmSIMD("simd/archsimd", "LoadUint16x8Array", simdLoad()) + addWasmSIMD("simd/archsimd", "BroadcastUint16x8", simdBroadcast(ssa.OpBroadcastInt16x8)) + addWasmSIMD("simd/archsimd", "Uint16x8.StoreArray", simdStore()) + addWasmSIMD("simd/archsimd", "LoadUint32x4Array", simdLoad()) + addWasmSIMD("simd/archsimd", "BroadcastUint32x4", simdBroadcast(ssa.OpBroadcastInt32x4)) + addWasmSIMD("simd/archsimd", "Uint32x4.StoreArray", simdStore()) + addWasmSIMD("simd/archsimd", "LoadUint64x2Array", simdLoad()) + addWasmSIMD("simd/archsimd", "BroadcastUint64x2", simdBroadcast(ssa.OpBroadcastInt64x2)) + addWasmSIMD("simd/archsimd", "Uint64x2.StoreArray", simdStore()) + addWasmSIMD("simd/archsimd", "LoadFloat32x4Array", simdLoad()) + addWasmSIMD("simd/archsimd", "BroadcastFloat32x4", simdBroadcast(ssa.OpBroadcastFloat32x4)) + addWasmSIMD("simd/archsimd", "Float32x4.StoreArray", simdStore()) + addWasmSIMD("simd/archsimd", "LoadFloat64x2Array", simdLoad()) + addWasmSIMD("simd/archsimd", "BroadcastFloat64x2", simdBroadcast(ssa.OpBroadcastFloat64x2)) + addWasmSIMD("simd/archsimd", "Float64x2.StoreArray", simdStore()) + addWasmSIMD("simd/archsimd", "Int8x16.AsInt16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int8x16.AsInt32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int8x16.AsInt64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int8x16.AsUint8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int8x16.AsUint16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int8x16.AsUint32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int8x16.AsUint64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int8x16.AsFloat32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int8x16.AsFloat64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.AsInt8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.AsInt32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.AsInt64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.AsUint8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.AsUint16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.AsUint32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.AsUint64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.AsFloat32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.AsFloat64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.AsInt8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.AsInt16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.AsInt64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.AsUint8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.AsUint16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.AsUint32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.AsUint64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.AsFloat32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.AsFloat64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.AsInt8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.AsInt16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.AsInt32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.AsUint8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.AsUint16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.AsUint32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.AsUint64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.AsFloat32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.AsFloat64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.AsInt8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.AsInt16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.AsInt32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.AsInt64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.AsUint16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.AsUint32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.AsUint64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.AsFloat32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.AsFloat64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.AsInt8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.AsInt16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.AsInt32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.AsInt64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.AsUint8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.AsUint32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.AsUint64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.AsFloat32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.AsFloat64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.AsInt8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.AsInt16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.AsInt32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.AsInt64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.AsUint8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.AsUint16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.AsUint64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.AsFloat32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.AsFloat64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.AsInt8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.AsInt16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.AsInt32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.AsInt64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.AsUint8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.AsUint16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.AsUint32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.AsFloat32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.AsFloat64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float32x4.AsInt8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float32x4.AsInt16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float32x4.AsInt32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float32x4.AsInt64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float32x4.AsUint8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float32x4.AsUint16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float32x4.AsUint32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float32x4.AsUint64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float32x4.AsFloat64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float64x2.AsInt8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float64x2.AsInt16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float64x2.AsInt32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float64x2.AsInt64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float64x2.AsUint8x16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float64x2.AsUint16x8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float64x2.AsUint32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float64x2.AsUint64x2", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float64x2.AsFloat32x4", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.BitsToFloat32", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float32x4.ToBits", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.BitsToFloat64", makeAsOp()) + addWasmSIMD("simd/archsimd", "Float64x2.ToBits", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.BitsToInt8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.ConvertToInt8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int8x16.ConvertToUint8", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int8x16.ToBits", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.BitsToInt16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.ConvertToInt16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.ConvertToUint16", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int16x8.ToBits", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.BitsToInt32", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.ConvertToInt32", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.ConvertToUint32", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int32x4.ToBits", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.BitsToInt64", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.ConvertToInt64", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.ConvertToUint64", makeAsOp()) + addWasmSIMD("simd/archsimd", "Int64x2.ToBits", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.ReshapeToUint16s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.ReshapeToUint32s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint8x16.ReshapeToUint64s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.ReshapeToUint8s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.ReshapeToUint32s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint16x8.ReshapeToUint64s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.ReshapeToUint8s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.ReshapeToUint16s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint32x4.ReshapeToUint64s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.ReshapeToUint8s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.ReshapeToUint16s", makeAsOp()) + addWasmSIMD("simd/archsimd", "Uint64x2.ReshapeToUint32s", makeAsOp()) +} diff --git a/src/cmd/compile/internal/ssagen/ssa.go b/src/cmd/compile/internal/ssagen/ssa.go index ae7d57566f7e0d..7052dc2dc8b5ce 100644 --- a/src/cmd/compile/internal/ssagen/ssa.go +++ b/src/cmd/compile/internal/ssagen/ssa.go @@ -12,6 +12,7 @@ import ( "go/constant" "html" "internal/buildcfg" + "internal/goexperiment" "internal/runtime/gc" "os" "path/filepath" @@ -124,6 +125,13 @@ func InitConfig() { ir.Syms.GCWriteBarrier[7] = typecheck.LookupRuntimeFunc("gcWriteBarrier8") ir.Syms.Goschedguarded = typecheck.LookupRuntimeFunc("goschedguarded") ir.Syms.Growslice = typecheck.LookupRuntimeFunc("growslice") + ir.Syms.GrowsliceBuf = typecheck.LookupRuntimeFunc("growsliceBuf") + ir.Syms.GrowsliceBufNoAlias = typecheck.LookupRuntimeFunc("growsliceBufNoAlias") + ir.Syms.GrowsliceNoAlias = typecheck.LookupRuntimeFunc("growsliceNoAlias") + ir.Syms.MoveSlice = typecheck.LookupRuntimeFunc("moveSlice") + ir.Syms.MoveSliceNoScan = typecheck.LookupRuntimeFunc("moveSliceNoScan") + ir.Syms.MoveSliceNoCap = typecheck.LookupRuntimeFunc("moveSliceNoCap") + ir.Syms.MoveSliceNoCapNoScan = typecheck.LookupRuntimeFunc("moveSliceNoCapNoScan") ir.Syms.InterfaceSwitch = typecheck.LookupRuntimeFunc("interfaceSwitch") for i := 1; i < len(ir.Syms.MallocGCSmallNoScan); i++ { ir.Syms.MallocGCSmallNoScan[i] = typecheck.LookupRuntimeFunc(fmt.Sprintf("mallocgcSmallNoScanSC%d", i)) @@ -131,11 +139,10 @@ func InitConfig() { for i := 1; i < len(ir.Syms.MallocGCSmallScanNoHeader); i++ { ir.Syms.MallocGCSmallScanNoHeader[i] = typecheck.LookupRuntimeFunc(fmt.Sprintf("mallocgcSmallScanNoHeaderSC%d", i)) } - for i := 1; i < len(ir.Syms.MallocGCTiny); i++ { - ir.Syms.MallocGCTiny[i] = typecheck.LookupRuntimeFunc(fmt.Sprintf("mallocTiny%d", i)) - } + ir.Syms.MallocGCTiny = typecheck.LookupRuntimeFunc("mallocgcTinySC2") ir.Syms.MallocGC = typecheck.LookupRuntimeFunc("mallocgc") ir.Syms.Memmove = typecheck.LookupRuntimeFunc("memmove") + ir.Syms.Memequal = typecheck.LookupRuntimeFunc("memequal") ir.Syms.Msanread = typecheck.LookupRuntimeFunc("msanread") ir.Syms.Msanwrite = typecheck.LookupRuntimeFunc("msanwrite") ir.Syms.Msanmove = typecheck.LookupRuntimeFunc("msanmove") @@ -151,6 +158,7 @@ func InitConfig() { ir.Syms.Panicnildottype = typecheck.LookupRuntimeFunc("panicnildottype") ir.Syms.Panicoverflow = typecheck.LookupRuntimeFunc("panicoverflow") ir.Syms.Panicshift = typecheck.LookupRuntimeFunc("panicshift") + ir.Syms.PanicSimdImm = typecheck.LookupRuntimeFunc("panicSimdImm") ir.Syms.Racefuncenter = typecheck.LookupRuntimeFunc("racefuncenter") ir.Syms.Racefuncexit = typecheck.LookupRuntimeFunc("racefuncexit") ir.Syms.Raceread = typecheck.LookupRuntimeFunc("raceread") @@ -160,15 +168,17 @@ func InitConfig() { ir.Syms.TypeAssert = typecheck.LookupRuntimeFunc("typeAssert") ir.Syms.WBZero = typecheck.LookupRuntimeFunc("wbZero") ir.Syms.WBMove = typecheck.LookupRuntimeFunc("wbMove") - ir.Syms.X86HasPOPCNT = typecheck.LookupRuntimeVar("x86HasPOPCNT") // bool - ir.Syms.X86HasSSE41 = typecheck.LookupRuntimeVar("x86HasSSE41") // bool - ir.Syms.X86HasFMA = typecheck.LookupRuntimeVar("x86HasFMA") // bool - ir.Syms.ARMHasVFPv4 = typecheck.LookupRuntimeVar("armHasVFPv4") // bool - ir.Syms.ARM64HasATOMICS = typecheck.LookupRuntimeVar("arm64HasATOMICS") // bool - ir.Syms.Loong64HasLAMCAS = typecheck.LookupRuntimeVar("loong64HasLAMCAS") // bool - ir.Syms.Loong64HasLAM_BH = typecheck.LookupRuntimeVar("loong64HasLAM_BH") // bool - ir.Syms.Loong64HasLSX = typecheck.LookupRuntimeVar("loong64HasLSX") // bool - ir.Syms.RISCV64HasZbb = typecheck.LookupRuntimeVar("riscv64HasZbb") // bool + ir.Syms.X86HasAVX = typecheck.LookupRuntimeVar("x86HasAVX") // bool + ir.Syms.X86HasFMA = typecheck.LookupRuntimeVar("x86HasFMA") // bool + ir.Syms.X86HasPOPCNT = typecheck.LookupRuntimeVar("x86HasPOPCNT") // bool + ir.Syms.X86HasSSE41 = typecheck.LookupRuntimeVar("x86HasSSE41") // bool + ir.Syms.ARMHasVFPv4 = typecheck.LookupRuntimeVar("armHasVFPv4") // bool + ir.Syms.ARM64HasATOMICS = typecheck.LookupRuntimeVar("arm64HasATOMICS") // bool + ir.Syms.Loong64HasLAMCAS = typecheck.LookupRuntimeVar("loong64HasLAMCAS") // bool + ir.Syms.Loong64HasLAM_BH = typecheck.LookupRuntimeVar("loong64HasLAM_BH") // bool + ir.Syms.Loong64HasDBAR_HINTS = typecheck.LookupRuntimeVar("loong64HasDBAR_HINTS") // bool + ir.Syms.Loong64HasLSX = typecheck.LookupRuntimeVar("loong64HasLSX") // bool + ir.Syms.RISCV64HasZbb = typecheck.LookupRuntimeVar("riscv64HasZbb") // bool ir.Syms.Staticuint64s = typecheck.LookupRuntimeVar("staticuint64s") ir.Syms.Typedmemmove = typecheck.LookupRuntimeFunc("typedmemmove") ir.Syms.Udiv = typecheck.LookupRuntimeVar("udiv") // asm func with special ABI @@ -213,12 +223,11 @@ func InitTables() { // any ABI wrapper that is present is nosplit, hence a precise // stack map is not needed there (the parameters survive only long // enough to call the wrapped assembly function). -// This always returns a freshly copied ABI. func AbiForBodylessFuncStackMap(fn *ir.Func) *abi.ABIConfig { - return ssaConfig.ABI0.Copy() // No idea what races will result, be safe + return ssaConfig.ABI0 } -// abiForFunc implements ABI policy for a function, but does not return a copy of the ABI. +// abiForFunc implements ABI policy for a function. // Passing a nil function returns the default ABI based on experiment configuration. func abiForFunc(fn *ir.Func, abi0, abi1 *abi.ABIConfig) *abi.ABIConfig { if buildcfg.Experiment.RegabiArgs { @@ -272,6 +281,7 @@ func (s *state) emitOpenDeferInfo() { x := base.Ctxt.Lookup(s.curfn.LSym.Name + ".opendefer") x.Set(obj.AttrContentAddressable, true) + x.Align = 1 s.curfn.LSym.Func().OpenCodedDeferInfo = x off := 0 @@ -329,9 +339,9 @@ func buildssa(fn *ir.Func, worker int, isPgoHot bool) *ssa.Func { if base.Flag.Cfg.Instrumenting && fn.Pragma&ir.Norace == 0 && !fn.Linksym().ABIWrapper() { if !base.Flag.Race || !objabi.LookupPkgSpecial(fn.Sym().Pkg.Path).NoRaceFunc { s.instrumentMemory = true - } - if base.Flag.Race { - s.instrumentEnterExit = true + if base.Flag.Race { + s.instrumentEnterExit = true + } } } @@ -595,6 +605,9 @@ func buildssa(fn *ir.Func, worker int, isPgoHot bool) *ssa.Func { // TODO figure out exactly what's unused, don't spill it. Make liveness fine-grained, also. for _, p := range params.InParams() { typs, offs := p.RegisterTypesAndOffsets() + if len(offs) < len(typs) { + s.Fatalf("len(offs)=%d < len(typs)=%d, params=\n%s", len(offs), len(typs), params) + } for i, t := range typs { o := offs[i] // offset within parameter fo := p.FrameOffset(params) // offset of parameter in frame @@ -792,11 +805,8 @@ func (s *state) specializedMallocSym(size int64, hasPointers bool) *obj.LSym { if !s.sizeSpecializedMallocEnabled() { return nil } - ptrSize := s.config.PtrSize - ptrBits := ptrSize * 8 - minSizeForMallocHeader := ptrSize * ptrBits - heapBitsInSpan := size <= minSizeForMallocHeader - if !heapBitsInSpan { + const specializedMallocMax = 80 // This must match the constant in mkmalloc. + if size > specializedMallocMax { return nil } divRoundUp := func(n, a uintptr) uintptr { return (n + a - 1) / a } @@ -805,7 +815,7 @@ func (s *state) specializedMallocSym(size int64, hasPointers bool) *obj.LSym { return ir.Syms.MallocGCSmallScanNoHeader[sizeClass] } if size < gc.TinySize { - return ir.Syms.MallocGCTiny[size] + return ir.Syms.MallocGCTiny } return ir.Syms.MallocGCSmallNoScan[sizeClass] } @@ -1091,6 +1101,23 @@ type state struct { // Block starting position, indexed by block id. blockStarts []src.XPos + + // Information for stack allocation. Indexed by the first argument + // to an append call. Normally a slice-typed variable, but not always. + backingStores map[ir.Node]*backingStoreInfo +} + +type backingStoreInfo struct { + // Size of backing store array (in elements) + K int64 + // Stack-allocated backing store variable. + store *ir.Name + // Dynamic boolean variable marking the fact that we used this backing store. + used *ir.Name + // Have we used this variable statically yet? This is just a hint + // to avoid checking the dynamic variable if the answer is obvious. + // (usedStatic == true implies used == true) + usedStatic bool } type funcLine struct { @@ -1115,13 +1142,13 @@ func (s *state) label(sym *types.Sym) *ssaLabel { return lab } -func (s *state) Logf(msg string, args ...interface{}) { s.f.Logf(msg, args...) } -func (s *state) Log() bool { return s.f.Log() } -func (s *state) Fatalf(msg string, args ...interface{}) { +func (s *state) Logf(msg string, args ...any) { s.f.Logf(msg, args...) } +func (s *state) Log() bool { return s.f.Log() } +func (s *state) Fatalf(msg string, args ...any) { s.f.Frontend().Fatalf(s.peekPos(), msg, args...) } -func (s *state) Warnl(pos src.XPos, msg string, args ...interface{}) { s.f.Warnl(pos, msg, args...) } -func (s *state) Debug_checknil() bool { return s.f.Frontend().Debug_checknil() } +func (s *state) Warnl(pos src.XPos, msg string, args ...any) { s.f.Warnl(pos, msg, args...) } +func (s *state) Debug_checknil() bool { return s.f.Frontend().Debug_checknil() } func ssaMarker(name string) *ir.Name { return ir.NewNameAt(base.Pos, &types.Sym{Name: name}, nil) @@ -1311,6 +1338,11 @@ func (s *state) newValue4(op ssa.Op, t *types.Type, arg0, arg1, arg2, arg3 *ssa. return s.curBlock.NewValue4(s.peekPos(), op, t, arg0, arg1, arg2, arg3) } +// newValue4A adds a new value with four arguments and an aux value to the current block. +func (s *state) newValue4A(op ssa.Op, t *types.Type, aux ssa.Aux, arg0, arg1, arg2, arg3 *ssa.Value) *ssa.Value { + return s.curBlock.NewValue4A(s.peekPos(), op, t, aux, arg0, arg1, arg2, arg3) +} + // newValue4I adds a new value with four arguments and an auxint value to the current block. func (s *state) newValue4I(op ssa.Op, t *types.Type, aux int64, arg0, arg1, arg2, arg3 *ssa.Value) *ssa.Value { return s.curBlock.NewValue4I(s.peekPos(), op, t, aux, arg0, arg1, arg2, arg3) @@ -1440,7 +1472,7 @@ func (s *state) instrument(t *types.Type, addr *ssa.Value, kind instrumentKind) // If it is instrumenting for MSAN or ASAN and t is a struct type, it instruments // operation for each field, instead of for the whole struct. func (s *state) instrumentFields(t *types.Type, addr *ssa.Value, kind instrumentKind) { - if !(base.Flag.MSan || base.Flag.ASan) || !t.IsStruct() { + if !(base.Flag.MSan || base.Flag.ASan) || !isStructNotSIMD(t) { s.instrument(t, addr, kind) return } @@ -1617,6 +1649,16 @@ func (s *state) stmtList(l ir.Nodes) { } } +func peelConvNop(n ir.Node) ir.Node { + if n == nil { + return n + } + for n.Op() == ir.OCONVNOP { + n = n.(*ir.ConvExpr).X + } + return n +} + // stmt converts the statement n to SSA and adds it to s. func (s *state) stmt(n ir.Node) { s.pushLine(n.Pos()) @@ -1792,12 +1834,10 @@ func (s *state) stmt(n ir.Node) { // arrays referenced are strictly smaller parts of the same base array. // If one side of the assignment is a full array, then partial overlap // can't happen. (The arrays are either disjoint or identical.) - mayOverlap := n.X.Op() == ir.ODEREF && (n.Y != nil && n.Y.Op() == ir.ODEREF) - if n.Y != nil && n.Y.Op() == ir.ODEREF { - p := n.Y.(*ir.StarExpr).X - for p.Op() == ir.OCONVNOP { - p = p.(*ir.ConvExpr).X - } + ny := peelConvNop(n.Y) + mayOverlap := n.X.Op() == ir.ODEREF && (n.Y != nil && ny.Op() == ir.ODEREF) + if ny != nil && ny.Op() == ir.ODEREF { + p := peelConvNop(ny.(*ir.StarExpr).X) if p.Op() == ir.OSPTR && p.(*ir.UnaryExpr).X.Type().IsString() { // Pointer fields of strings point to unmodifiable memory. // That memory can't overlap with the memory being written. @@ -3513,16 +3553,14 @@ func (s *state) exprCheckPtr(n ir.Node, checkPtrOK bool) *ssa.Value { bound := n.X.Type().NumElem() a := s.expr(n.X) i := s.expr(n.Index) + len := s.constInt(types.Types[types.TINT], bound) if bound == 0 { - // Bounds check will never succeed. Might as well - // use constants for the bounds check. - z := s.constInt(types.Types[types.TINT], 0) - s.boundsCheck(z, z, ssa.BoundsIndex, false) - // The return value won't be live, return junk. - // But not quite junk, in case bounds checks are turned off. See issue 48092. - return s.zeroVal(n.Type()) + // Bounds check will never succeed. + s.boundsCheck(i, len, ssa.BoundsIndex, false) + // The return value won't be live. In case bounds checks + // are turned off, load from (*T)(nil) to cause a segfault. + return s.load(n.Type(), s.constNil(n.Type().PtrTo())) } - len := s.constInt(types.Types[types.TINT], bound) s.boundsCheck(i, len, ssa.BoundsIndex, n.Bounded()) // checks i == 0 return s.newValue1I(ssa.OpArraySelect, n.Type(), 0, a) } @@ -3673,6 +3711,9 @@ func (s *state) exprCheckPtr(n ir.Node, checkPtrOK bool) *ssa.Value { case ir.OAPPEND: return s.append(n.(*ir.CallExpr), false) + case ir.OMOVE2HEAP: + return s.move2heap(n.(*ir.MoveToHeapExpr)) + case ir.OMIN, ir.OMAX: return s.minMax(n.(*ir.CallExpr)) @@ -3734,6 +3775,68 @@ func (s *state) resultAddrOfCall(c *ssa.Value, which int64, t *types.Type) *ssa. return addr } +// Get backing store information for an append call. +func (s *state) getBackingStoreInfoForAppend(n *ir.CallExpr) *backingStoreInfo { + if n.Esc() != ir.EscNone { + return nil + } + return s.getBackingStoreInfo(n.Args[0]) +} +func (s *state) getBackingStoreInfo(n ir.Node) *backingStoreInfo { + t := n.Type() + et := t.Elem() + maxStackSize := int64(base.Debug.VariableMakeThreshold) + if et.Size() == 0 || et.Size() > maxStackSize { + return nil + } + if base.Flag.N != 0 { + return nil + } + if !base.VariableMakeHash.MatchPos(n.Pos(), nil) { + return nil + } + i := s.backingStores[n] + if i != nil { + return i + } + + // Build type of backing store. + K := maxStackSize / et.Size() // rounds down + KT := types.NewArray(et, K) + KT.SetNoalg(true) + types.CalcArraySize(KT) + // Align more than naturally for the type KT. See issue 73199. + align := types.NewArray(types.Types[types.TUINTPTR], 0) + types.CalcArraySize(align) + storeTyp := types.NewStruct([]*types.Field{ + {Sym: types.BlankSym, Type: align}, + {Sym: types.BlankSym, Type: KT}, + }) + storeTyp.SetNoalg(true) + types.CalcStructSize(storeTyp) + + // Make backing store variable. + backingStore := typecheck.TempAt(n.Pos(), s.curfn, storeTyp) + backingStore.SetAddrtaken(true) + + // Make "used" boolean. + used := typecheck.TempAt(n.Pos(), s.curfn, types.Types[types.TBOOL]) + if s.curBlock == s.f.Entry { + s.vars[used] = s.constBool(false) + } else { + // initialize this variable at end of entry block + s.defvars[s.f.Entry.ID][used] = s.constBool(false) + } + + // Initialize an info structure. + if s.backingStores == nil { + s.backingStores = map[ir.Node]*backingStoreInfo{} + } + i = &backingStoreInfo{K: K, store: backingStore, used: used, usedStatic: false} + s.backingStores[n] = i + return i +} + // append converts an OAPPEND node to SSA. // If inplace is false, it converts the OAPPEND expression n to an ssa.Value, // adds it to s, and returns the Value. @@ -3824,9 +3927,29 @@ func (s *state) append(n *ir.CallExpr, inplace bool) *ssa.Value { // A stack-allocated backing store could be used at every // append that qualifies, but we limit it in some cases to // avoid wasted code and stack space. - // TODO: handle ... append case. - maxStackSize := int64(base.Debug.VariableMakeThreshold) - if !inplace && n.Esc() == ir.EscNone && et.Size() > 0 && et.Size() <= maxStackSize && base.Flag.N == 0 && base.VariableMakeHash.MatchPos(n.Pos(), nil) && !s.appendTargets[sn] { + // + // Note that we have two different strategies. + // 1. The standard strategy is just to allocate the full + // backing store at the first append. + // 2. An alternate strategy is used when + // a. The backing store eventually escapes via move2heap + // and b. The capacity is used somehow + // In this case, we don't want to just allocate + // the full buffer at the first append, because when + // we move2heap the buffer to the heap when it escapes, + // we might end up wasting memory because we can't + // change the capacity. + // So in this case we use growsliceBuf to reuse the buffer + // and walk one step up the size class ladder each time. + // + // TODO: handle ... append case? Currently we handle only + // a fixed number of appended elements. + var info *backingStoreInfo + if !inplace { + info = s.getBackingStoreInfoForAppend(n) + } + + if !inplace && info != nil && !n.UseBuf && !info.usedStatic { // if l <= K { // if !used { // if oldLen == 0 { @@ -3850,43 +3973,19 @@ func (s *state) append(n *ir.CallExpr, inplace bool) *ssa.Value { // It is ok to do it more often, but it is probably helpful only for // the first instance. TODO: this could use more tuning. Using ir.Node // as the key works for *ir.Name instances but probably nothing else. - if s.appendTargets == nil { - s.appendTargets = map[ir.Node]bool{} - } - s.appendTargets[sn] = true - - K := maxStackSize / et.Size() // rounds down - KT := types.NewArray(et, K) - KT.SetNoalg(true) - types.CalcArraySize(KT) - // Align more than naturally for the type KT. See issue 73199. - align := types.NewArray(types.Types[types.TUINTPTR], 0) - types.CalcArraySize(align) - storeTyp := types.NewStruct([]*types.Field{ - {Sym: types.BlankSym, Type: align}, - {Sym: types.BlankSym, Type: KT}, - }) - storeTyp.SetNoalg(true) - types.CalcStructSize(storeTyp) + info.usedStatic = true + // TODO: unset usedStatic somehow? usedTestBlock := s.f.NewBlock(ssa.BlockPlain) oldLenTestBlock := s.f.NewBlock(ssa.BlockPlain) bodyBlock := s.f.NewBlock(ssa.BlockPlain) growSlice := s.f.NewBlock(ssa.BlockPlain) - - // Make "used" boolean. - tBool := types.Types[types.TBOOL] - used := typecheck.TempAt(n.Pos(), s.curfn, tBool) - s.defvars[s.f.Entry.ID][used] = s.constBool(false) // initialize this variable at fn entry - - // Make backing store variable. tInt := types.Types[types.TINT] - backingStore := typecheck.TempAt(n.Pos(), s.curfn, storeTyp) - backingStore.SetAddrtaken(true) + tBool := types.Types[types.TBOOL] // if l <= K s.startBlock(grow) - kTest := s.newValue2(s.ssaOp(ir.OLE, tInt), tBool, l, s.constInt(tInt, K)) + kTest := s.newValue2(s.ssaOp(ir.OLE, tInt), tBool, l, s.constInt(tInt, info.K)) b := s.endBlock() b.Kind = ssa.BlockIf b.SetControl(kTest) @@ -3896,7 +3995,7 @@ func (s *state) append(n *ir.CallExpr, inplace bool) *ssa.Value { // if !used s.startBlock(usedTestBlock) - usedTest := s.newValue1(ssa.OpNot, tBool, s.expr(used)) + usedTest := s.newValue1(ssa.OpNot, tBool, s.expr(info.used)) b = s.endBlock() b.Kind = ssa.BlockIf b.SetControl(usedTest) @@ -3917,18 +4016,18 @@ func (s *state) append(n *ir.CallExpr, inplace bool) *ssa.Value { // var store struct { _ [0]uintptr; arr [K]T } s.startBlock(bodyBlock) if et.HasPointers() { - s.vars[memVar] = s.newValue1A(ssa.OpVarDef, types.TypeMem, backingStore, s.mem()) + s.vars[memVar] = s.newValue1A(ssa.OpVarDef, types.TypeMem, info.store, s.mem()) } - addr := s.addr(backingStore) - s.zero(storeTyp, addr) + addr := s.addr(info.store) + s.zero(info.store.Type(), addr) // s = store.arr[:l:K] s.vars[ptrVar] = addr s.vars[lenVar] = l // nargs would also be ok because of the oldLen==0 test. - s.vars[capVar] = s.constInt(tInt, K) + s.vars[capVar] = s.constInt(tInt, info.K) // used = true - s.assign(used, s.constBool(true), false, 0) + s.assign(info.used, s.constBool(true), false, 0) b = s.endBlock() b.AddEdgeTo(assign) @@ -3939,7 +4038,41 @@ func (s *state) append(n *ir.CallExpr, inplace bool) *ssa.Value { // Call growslice s.startBlock(grow) taddr := s.expr(n.Fun) - r := s.rtcall(ir.Syms.Growslice, true, []*types.Type{n.Type()}, p, l, c, nargs, taddr) + var r []*ssa.Value + if info != nil && n.UseBuf { + // Use stack-allocated buffer as backing store, if we can. + if et.HasPointers() && !info.usedStatic { + // Initialize in the function header. Not the best place, + // but it makes sure we don't scan this area before it is + // initialized. + mem := s.defvars[s.f.Entry.ID][memVar] + mem = s.f.Entry.NewValue1A(n.Pos(), ssa.OpVarDef, types.TypeMem, info.store, mem) + addr := s.f.Entry.NewValue2A(n.Pos(), ssa.OpLocalAddr, types.NewPtr(info.store.Type()), info.store, s.sp, mem) + mem = s.f.Entry.NewValue2I(n.Pos(), ssa.OpZero, types.TypeMem, info.store.Type().Size(), addr, mem) + mem.Aux = info.store.Type() + s.defvars[s.f.Entry.ID][memVar] = mem + info.usedStatic = true + } + fn := ir.Syms.GrowsliceBuf + if goexperiment.RuntimeFreegc && n.AppendNoAlias && !et.HasPointers() { + // The append is for a non-aliased slice where the runtime knows how to free + // the old logically dead backing store after growth. + // TODO(thepudds): for now, we only use the NoAlias version for element types + // without pointers while waiting on additional runtime support (CL 698515). + fn = ir.Syms.GrowsliceBufNoAlias + } + r = s.rtcall(fn, true, []*types.Type{n.Type()}, p, l, c, nargs, taddr, s.addr(info.store), s.constInt(types.Types[types.TINT], info.K)) + } else { + fn := ir.Syms.Growslice + if goexperiment.RuntimeFreegc && n.AppendNoAlias && !et.HasPointers() { + // The append is for a non-aliased slice where the runtime knows how to free + // the old logically dead backing store after growth. + // TODO(thepudds): for now, we only use the NoAlias version for element types + // without pointers while waiting on additional runtime support (CL 698515). + fn = ir.Syms.GrowsliceNoAlias + } + r = s.rtcall(fn, true, []*types.Type{n.Type()}, p, l, c, nargs, taddr) + } // Decompose output slice p = s.newValue1(ssa.OpSlicePtr, pt, r[0]) @@ -4026,6 +4159,95 @@ func (s *state) append(n *ir.CallExpr, inplace bool) *ssa.Value { return s.newValue3(ssa.OpSliceMake, n.Type(), p, l, c) } +func (s *state) move2heap(n *ir.MoveToHeapExpr) *ssa.Value { + // s := n.Slice + // if s.ptr points to current stack frame { + // s2 := make([]T, s.len, s.cap) + // copy(s2[:cap], s[:cap]) + // s = s2 + // } + // return s + + slice := s.expr(n.Slice) + et := slice.Type.Elem() + pt := types.NewPtr(et) + + info := s.getBackingStoreInfo(n) + if info == nil { + // Backing store will never be stack allocated, so + // move2heap is a no-op. + return slice + } + + // Decomposse input slice. + p := s.newValue1(ssa.OpSlicePtr, pt, slice) + l := s.newValue1(ssa.OpSliceLen, types.Types[types.TINT], slice) + c := s.newValue1(ssa.OpSliceCap, types.Types[types.TINT], slice) + + moveBlock := s.f.NewBlock(ssa.BlockPlain) + mergeBlock := s.f.NewBlock(ssa.BlockPlain) + + s.vars[ptrVar] = p + s.vars[lenVar] = l + s.vars[capVar] = c + + // Decide if we need to move the slice backing store. + // It needs to be moved if it is currently on the stack. + sub := ssa.OpSub64 + less := ssa.OpLess64U + if s.config.PtrSize == 4 { + sub = ssa.OpSub32 + less = ssa.OpLess32U + } + callerSP := s.newValue1(ssa.OpGetCallerSP, types.Types[types.TUINTPTR], s.mem()) + frameSize := s.newValue2(sub, types.Types[types.TUINTPTR], callerSP, s.sp) + pInt := s.newValue2(ssa.OpConvert, types.Types[types.TUINTPTR], p, s.mem()) + off := s.newValue2(sub, types.Types[types.TUINTPTR], pInt, s.sp) + cond := s.newValue2(less, types.Types[types.TBOOL], off, frameSize) + + b := s.endBlock() + b.Kind = ssa.BlockIf + b.Likely = ssa.BranchUnlikely // fast path is to not have to call into runtime + b.SetControl(cond) + b.AddEdgeTo(moveBlock) + b.AddEdgeTo(mergeBlock) + + // Move the slice to heap + s.startBlock(moveBlock) + var newSlice *ssa.Value + if et.HasPointers() { + typ := s.expr(n.RType) + if n.PreserveCapacity { + newSlice = s.rtcall(ir.Syms.MoveSlice, true, []*types.Type{slice.Type}, typ, p, l, c)[0] + } else { + newSlice = s.rtcall(ir.Syms.MoveSliceNoCap, true, []*types.Type{slice.Type}, typ, p, l)[0] + } + } else { + elemSize := s.constInt(types.Types[types.TUINTPTR], et.Size()) + if n.PreserveCapacity { + newSlice = s.rtcall(ir.Syms.MoveSliceNoScan, true, []*types.Type{slice.Type}, elemSize, p, l, c)[0] + } else { + newSlice = s.rtcall(ir.Syms.MoveSliceNoCapNoScan, true, []*types.Type{slice.Type}, elemSize, p, l)[0] + } + } + // Decompose output slice + s.vars[ptrVar] = s.newValue1(ssa.OpSlicePtr, pt, newSlice) + s.vars[lenVar] = s.newValue1(ssa.OpSliceLen, types.Types[types.TINT], newSlice) + s.vars[capVar] = s.newValue1(ssa.OpSliceCap, types.Types[types.TINT], newSlice) + b = s.endBlock() + b.AddEdgeTo(mergeBlock) + + // Merge fast path (no moving) and slow path (moved) + s.startBlock(mergeBlock) + p = s.variable(ptrVar, pt) // generates phi for ptr + l = s.variable(lenVar, types.Types[types.TINT]) // generates phi for len + c = s.variable(capVar, types.Types[types.TINT]) // generates phi for cap + delete(s.vars, ptrVar) + delete(s.vars, lenVar) + delete(s.vars, capVar) + return s.newValue3(ssa.OpSliceMake, slice.Type, p, l, c) +} + // minMax converts an OMIN/OMAX builtin call into SSA. func (s *state) minMax(n *ir.CallExpr) *ssa.Value { // The OMIN/OMAX builtin is variadic, but its semantics are @@ -4053,10 +4275,12 @@ func (s *state) minMax(n *ir.CallExpr) *ssa.Value { if typ.IsFloat() { hasIntrinsic := false switch Arch.LinkArch.Family { - case sys.AMD64, sys.ARM64, sys.Loong64, sys.RISCV64, sys.S390X: + case sys.AMD64, sys.ARM64, sys.Loong64, sys.RISCV64: hasIntrinsic = true case sys.PPC64: hasIntrinsic = buildcfg.GOPPC64 >= 9 + case sys.S390X: + // FIXME: add check once GOS390X exists } if hasIntrinsic { @@ -4268,6 +4492,11 @@ func (s *state) assignWhichMayOverlap(left ir.Node, right *ssa.Value, deref bool // Grab old value of structure. old := s.expr(left.X) + if left.Type().Size() == 0 { + // Nothing to do when assigning zero-sized things. + return + } + // Make new structure. new := s.newValue0(ssa.OpStructMake, t) @@ -4296,15 +4525,35 @@ func (s *state) assignWhichMayOverlap(left ir.Node, right *ssa.Value, deref bool i := s.expr(left.Index) // index if n == 0 { + _ = s.expr(left.X) // Evaluating left.X for any side-effects. // The bounds check must fail. Might as well // ignore the actual index and just use zeros. z := s.constInt(types.Types[types.TINT], 0) s.boundsCheck(z, z, ssa.BoundsIndex, false) return } + if t.Size() == 0 { + _ = s.expr(left.X) // Evaluating left.X for any side-effects. + // Generate bounds check for left, since this can happen + // for 0-size assignment case, see issue #79236. + len := s.constInt(types.Types[types.TINT], n) + s.boundsCheck(i, len, ssa.BoundsIndex, false) + return + } if n != 1 { - s.Fatalf("assigning to non-1-length array") + // This can happen in weird, always-panics cases, like: + // var x [0][2]int + // x[i][j] = 5 + // We know it always panics because the LHS is ssa-able, + // and arrays of length > 1 can't be ssa-able unless + // they are somewhere inside an outer [0]. + // We can ignore the actual assignment, it is dynamically + // unreachable. See issue 77635. + // Still, evaluating left.X for any side-effects. + _ = s.expr(left.X) + return } + // Rewrite to a = [1]{v} len := s.constInt(types.Types[types.TINT], 1) s.boundsCheck(i, len, ssa.BoundsIndex, false) // checks i == 0 @@ -4350,6 +4599,9 @@ func (s *state) assignWhichMayOverlap(left ir.Node, right *ssa.Value, deref bool // zeroVal returns the zero value for type t. func (s *state) zeroVal(t *types.Type) *ssa.Value { + if t.Size() == 0 { + return s.entryNewValue0(ssa.OpEmpty, t) + } switch { case t.IsInteger(): switch t.Size() { @@ -4395,20 +4647,17 @@ func (s *state) zeroVal(t *types.Type) *ssa.Value { return s.constInterface(t) case t.IsSlice(): return s.constSlice(t) - case t.IsStruct(): + case isStructNotSIMD(t): n := t.NumFields() v := s.entryNewValue0(ssa.OpStructMake, t) for i := 0; i < n; i++ { v.AddArg(s.zeroVal(t.FieldType(i))) } return v - case t.IsArray(): - switch t.NumElem() { - case 0: - return s.entryNewValue0(ssa.OpArrayMake0, t) - case 1: - return s.entryNewValue1(ssa.OpArrayMake1, t, s.zeroVal(t.Elem())) - } + case t.IsArray() && t.NumElem() == 1: + return s.entryNewValue1(ssa.OpArrayMake1, t, s.zeroVal(t.Elem())) + case t.IsSIMD(): + return s.newValue0(ssa.OpZeroSIMD, t) } s.Fatalf("zero for type %v not implemented", t) return nil @@ -4776,7 +5025,7 @@ func (s *state) call(n *ir.CallExpr, k callKind, returnResultAddr bool, deferExt fn := fn.(*ir.SelectorExpr) var iclosure *ssa.Value iclosure, rcvr = s.getClosureAndRcvr(fn) - if k == callNormal { + if k == callNormal || k == callTail { codeptr = s.load(types.Types[types.TUINTPTR], iclosure) } else { closure = iclosure @@ -4865,6 +5114,16 @@ func (s *state) call(n *ir.CallExpr, k callKind, returnResultAddr bool, deferExt callArgs = append(callArgs, s.putArg(n, t.Param(i).Type)) } + // In -race mode, we need to call racefuncexit before a tail call. + // A tail call reuses our frame and returns directly to our caller, + // so this is the last chance we get to tell the race detector that + // this function is done. Note: this has to happen after the + // arguments are evaluated, otherwise races in the argument + // expressions would be attributed to the caller instead. + if k == callTail && s.instrumentEnterExit { + s.rtcall(ir.Syms.Racefuncexit, true, nil) + } + callArgs = append(callArgs, s.mem()) // call target @@ -4892,6 +5151,10 @@ func (s *state) call(n *ir.CallExpr, k callKind, returnResultAddr bool, deferExt // Note that the "receiver" parameter is nil because the actual receiver is the first input parameter. aux := ssa.InterfaceAuxCall(params) call = s.newValue1A(ssa.OpInterLECall, aux.LateExpansionResultType(), aux, codeptr) + if k == callTail { + call.Op = ssa.OpTailLECallInter + stksize = 0 // Tail call does not use stack. We reuse caller's frame. + } case calleeLSym != nil: aux := ssa.StaticAuxCall(calleeLSym, params) call = s.newValue0A(ssa.OpStaticLECall, aux.LateExpansionResultType(), aux) @@ -4920,6 +5183,22 @@ func (s *state) call(n *ir.CallExpr, k callKind, returnResultAddr bool, deferExt s.vars[memVar] = s.newValue1A(ssa.OpVarLive, types.TypeMem, v, s.mem()) } + // Build result value (before we might end the defer block, below). + var result *ssa.Value + if len(res) == 0 || k != callNormal { + result = nil + } else { + fp := res[0] + if returnResultAddr { + result = s.resultAddrOfCall(call, 0, fp.Type) + } else { + result = s.newValue1I(ssa.OpSelectN, fp.Type, 0, call) + } + if n.Reshape { + result = s.newValue1(ssa.OpCopy, n.Type(), result) + } + } + // Finish block for defers if k == callDefer || k == callDeferStack || isCallDeferRangeFunc { b := s.endBlock() @@ -4939,15 +5218,7 @@ func (s *state) call(n *ir.CallExpr, k callKind, returnResultAddr bool, deferExt s.startBlock(bNext) } - if len(res) == 0 || k != callNormal { - // call has no return value. Continue with the next statement. - return nil - } - fp := res[0] - if returnResultAddr { - return s.resultAddrOfCall(call, 0, fp.Type) - } - return s.newValue1I(ssa.OpSelectN, fp.Type, 0, call) + return result } // maybeNilCheckClosure checks if a nil check of a closure is needed in some @@ -4993,7 +5264,16 @@ func (s *state) addr(n ir.Node) *ssa.Value { } if s.canSSA(n) { - s.Fatalf("addr of canSSA expression: %+v", n) + // This happens in weird, always-panics cases, like: + // var x [0][2]int + // x[i][j] = 5 + // The outer assignment, ...[j] = 5, is a fine + // assignment to do, but requires computing the address + // &x[i], which will always panic when evaluated. + // We just return something reasonable in this case. + // It will be dynamically unreachable. See issue 77635. + s.boundsCheckArrayIndex(n) + return s.newValue1A(ssa.OpAddr, n.Type().PtrTo(), ir.Syms.Zerobase, s.sb) } t := types.NewPtr(n.Type()) @@ -5175,6 +5455,21 @@ func (s *state) nilCheck(ptr *ssa.Value) *ssa.Value { return s.newValue2(ssa.OpNilCheck, ptr.Type, ptr, s.mem()) } +// boundsCheckArrayIndex generates bounds checking code for array indexing operations. +func (s *state) boundsCheckArrayIndex(n ir.Node) { + if n.Op() != ir.OINDEX { + return + } + nn := n.(*ir.IndexExpr) + typ := nn.X.Type() + if typ.IsArray() { + _ = s.expr(nn.X) // for side effects + idx := s.expr(nn.Index) + len := s.constInt(types.Types[types.TINT], typ.NumElem()) + s.boundsCheck(idx, len, ssa.BoundsIndex, nn.Bounded()) + } +} + // boundsCheck generates bounds checking code. Checks if 0 <= idx <[=] len, branches to exit if not. // Starts a new block on return. // On input, len must be converted to full int width and be nonnegative. @@ -5388,7 +5683,7 @@ func (s *state) storeType(t *types.Type, left, right *ssa.Value, skip skipMask, // do *left = right for all scalar (non-pointer) parts of t. func (s *state) storeTypeScalars(t *types.Type, left, right *ssa.Value, skip skipMask) { switch { - case t.IsBoolean() || t.IsInteger() || t.IsFloat() || t.IsComplex(): + case t.IsBoolean() || t.IsInteger() || t.IsFloat() || t.IsComplex() || t.IsSIMD(): s.store(t, left, right) case t.IsPtrShaped(): if t.IsPtr() && t.Elem().NotInHeap() { @@ -5417,7 +5712,7 @@ func (s *state) storeTypeScalars(t *types.Type, left, right *ssa.Value, skip ski // itab field doesn't need a write barrier (even though it is a pointer). itab := s.newValue1(ssa.OpITab, s.f.Config.Types.BytePtr, right) s.store(types.Types[types.TUINTPTR], left, itab) - case t.IsStruct(): + case isStructNotSIMD(t): n := t.NumFields() for i := 0; i < n; i++ { ft := t.FieldType(i) @@ -5425,7 +5720,7 @@ func (s *state) storeTypeScalars(t *types.Type, left, right *ssa.Value, skip ski val := s.newValue1I(ssa.OpStructSelect, ft, int64(i), right) s.storeTypeScalars(ft, addr, val, 0) } - case t.IsArray() && t.NumElem() == 0: + case t.IsArray() && t.Size() == 0: // nothing case t.IsArray() && t.NumElem() == 1: s.storeTypeScalars(t.Elem(), left, s.newValue1I(ssa.OpArraySelect, t.Elem(), 0, right), 0) @@ -5454,7 +5749,7 @@ func (s *state) storeTypePtrs(t *types.Type, left, right *ssa.Value) { idata := s.newValue1(ssa.OpIData, s.f.Config.Types.BytePtr, right) idataAddr := s.newValue1I(ssa.OpOffPtr, s.f.Config.Types.BytePtrPtr, s.config.PtrSize, left) s.store(s.f.Config.Types.BytePtr, idataAddr, idata) - case t.IsStruct(): + case isStructNotSIMD(t): n := t.NumFields() for i := 0; i < n; i++ { ft := t.FieldType(i) @@ -5465,7 +5760,7 @@ func (s *state) storeTypePtrs(t *types.Type, left, right *ssa.Value) { val := s.newValue1I(ssa.OpStructSelect, ft, int64(i), right) s.storeTypePtrs(ft, addr, val) } - case t.IsArray() && t.NumElem() == 0: + case t.IsArray() && t.Size() == 0: // nothing case t.IsArray() && t.NumElem() == 1: s.storeTypePtrs(t.Elem(), left, s.newValue1I(ssa.OpArraySelect, t.Elem(), 0, right)) @@ -5970,8 +6265,8 @@ func (s *state) dottype(n *ir.TypeAssertExpr, commaok bool) (res, resok *ssa.Val base.Fatalf("unexpected *ir.TypeAssertExpr with UseNilPanic == true && commaok == true") } if n.Type().IsInterface() { - // Currently we do not expect the compiler to emit type asserts with UseNilPanic, that assert to an interface type. - // If needed, this can be relaxed in the future, but for now we can assert that. + // Currently we do not expect the compiler to emit type assertions with UseNilPanic, that asserts to an interface type. + // If needed, this can be relaxed in the future, but for now we can't assert that. base.Fatalf("unexpected *ir.TypeAssertExpr with UseNilPanic == true && Type().IsInterface() == true") } typs := s.f.Config.Types @@ -6559,6 +6854,7 @@ func emitArgInfo(e *ssafn, f *ssa.Func, pp *objw.Progs) { // emit argument info (locations on stack) of f for traceback. func EmitArgInfo(f *ir.Func, abiInfo *abi.ABIParamResultInfo) *obj.LSym { x := base.Ctxt.Lookup(fmt.Sprintf("%s.arginfo%d", f.LSym.Name, f.ABI)) + x.Align = 1 // NOTE: do not set ContentAddressable here. This may be referenced from // assembly code by name (in this case f is a declaration). // Instead, set it in emitArgInfo above. @@ -6567,7 +6863,7 @@ func EmitArgInfo(f *ir.Func, abiInfo *abi.ABIParamResultInfo) *obj.LSym { uintptrTyp := types.Types[types.TUINTPTR] isAggregate := func(t *types.Type) bool { - return t.IsStruct() || t.IsArray() || t.IsComplex() || t.IsInterface() || t.IsString() || t.IsSlice() + return isStructNotSIMD(t) || t.IsArray() || t.IsComplex() || t.IsInterface() || t.IsString() || t.IsSlice() } wOff := 0 @@ -6627,7 +6923,7 @@ func EmitArgInfo(f *ir.Func, abiInfo *abi.ABIParamResultInfo) *obj.LSym { } baseOffset += t.Elem().Size() } - case t.IsStruct(): + case isStructNotSIMD(t): if t.NumFields() == 0 { n++ // {} counts as a component break @@ -6678,6 +6974,7 @@ func emitWrappedFuncInfo(e *ssafn, pp *objw.Progs) { x := base.Ctxt.LookupInit(fmt.Sprintf("%s.wrapinfo", wsym.Name), func(x *obj.LSym) { objw.SymPtrOff(x, 0, wsym) x.Set(obj.AttrContentAddressable, true) + x.Align = 4 }) e.curfn.LSym.Func().WrapInfo = x @@ -7573,7 +7870,7 @@ func AddrAuto(a *obj.Addr, v *ssa.Value) { // Call returns a new CALL instruction for the SSA value v. // It uses PrepareCall to prepare the call. func (s *State) Call(v *ssa.Value) *obj.Prog { - pPosIsStmt := s.pp.Pos.IsStmt() // The statement-ness fo the call comes from ssaGenState + pPosIsStmt := s.pp.Pos.IsStmt() // The statement-ness of the call comes from ssaGenState s.PrepareCall(v) p := s.Prog(obj.ACALL) @@ -7647,7 +7944,7 @@ func (s *State) UseArgs(n int64) { // fieldIdx finds the index of the field referred to by the ODOT node n. func fieldIdx(n *ir.SelectorExpr) int { t := n.X.Type() - if !t.IsStruct() { + if !isStructNotSIMD(t) { panic("ODOT's LHS is not a struct") } @@ -7714,7 +8011,7 @@ func (e *ssafn) SplitSlot(parent *ssa.LocalSlot, suffix string, offset int64, t } // Logf logs a message from the compiler. -func (e *ssafn) Logf(msg string, args ...interface{}) { +func (e *ssafn) Logf(msg string, args ...any) { if e.log { fmt.Printf(msg, args...) } @@ -7725,15 +8022,15 @@ func (e *ssafn) Log() bool { } // Fatalf reports a compiler error and exits. -func (e *ssafn) Fatalf(pos src.XPos, msg string, args ...interface{}) { +func (e *ssafn) Fatalf(pos src.XPos, msg string, args ...any) { base.Pos = pos - nargs := append([]interface{}{ir.FuncName(e.curfn)}, args...) + nargs := append([]any{ir.FuncName(e.curfn)}, args...) base.Fatalf("'%s': "+msg, nargs...) } // Warnl reports a "warning", which is usually flag-triggered // logging output for the benefit of tests. -func (e *ssafn) Warnl(pos src.XPos, fmt_ string, args ...interface{}) { +func (e *ssafn) Warnl(pos src.XPos, fmt_ string, args ...any) { base.WarnfAt(pos, fmt_, args...) } @@ -7855,4 +8152,8 @@ func SpillSlotAddr(spill ssa.Spill, baseReg int16, extraOffset int64) obj.Addr { } } +func isStructNotSIMD(t *types.Type) bool { + return t.IsStruct() && !t.IsSIMD() +} + var BoundsCheckFunc [ssa.BoundsKindCount]*obj.LSym diff --git a/src/cmd/compile/internal/staticdata/data.go b/src/cmd/compile/internal/staticdata/data.go index acafe9d3393e85..d742ecbc64f634 100644 --- a/src/cmd/compile/internal/staticdata/data.go +++ b/src/cmd/compile/internal/staticdata/data.go @@ -92,6 +92,7 @@ func StringSym(pos src.XPos, s string) (data *obj.LSym) { off := dstringdata(symdata, 0, s, pos, "string") objw.Global(symdata, int32(off), obj.DUPOK|obj.RODATA|obj.LOCAL) symdata.Set(obj.AttrContentAddressable, true) + symdata.Align = 1 } return symdata @@ -109,7 +110,7 @@ func StringSymNoCommon(s string) (data *obj.LSym) { // maxFileSize is the maximum file size permitted by the linker // (see issue #9862). -const maxFileSize = int64(2e9) +const maxFileSize = obj.MaxSymSize // fileStringSym returns a symbol for the contents and the size of file. // If readonly is true, the symbol shares storage with any literal string @@ -185,6 +186,7 @@ func fileStringSym(pos src.XPos, file string, readonly bool, hashBytes []byte) ( info.Name = file info.Size = size objw.Global(symdata, int32(size), obj.DUPOK|obj.RODATA|obj.LOCAL) + symdata.Align = 1 // Note: AttrContentAddressable cannot be set here, // because the content-addressable-handling code // does not know about file symbols. @@ -211,6 +213,7 @@ func slicedata(pos src.XPos, s string) *obj.LSym { lsym := types.LocalPkg.Lookup(symname).LinksymABI(obj.ABI0) off := dstringdata(lsym, 0, s, pos, "slice") objw.Global(lsym, int32(off), obj.NOPTR|obj.LOCAL) + lsym.Align = 1 return lsym } diff --git a/src/cmd/compile/internal/staticinit/sched.go b/src/cmd/compile/internal/staticinit/sched.go index 5e39bb512f45f4..c9546313bb50aa 100644 --- a/src/cmd/compile/internal/staticinit/sched.go +++ b/src/cmd/compile/internal/staticinit/sched.go @@ -113,7 +113,7 @@ func (s *Schedule) tryStaticInit(n ir.Node) bool { // "var a, b = f()" that needs type conversion, which is not static. n := n.(*ir.AssignListStmt) for _, rhs := range n.Rhs { - for rhs.Op() == ir.OCONVNOP { + for rhs.Op() == ir.OCONVNOP || rhs.Op() == ir.OCONVIFACE { rhs = rhs.(*ir.ConvExpr).X } if name, ok := rhs.(*ir.Name); !ok || !name.AutoTemp() { @@ -228,6 +228,9 @@ func (s *Schedule) staticcopy(l *ir.Name, loff int64, rn *ir.Name, typ *types.Ty case ir.OADDR: r := r.(*ir.AddrExpr) if a, ok := r.X.(*ir.Name); ok && a.Op() == ir.ONAME { + if a.Class != ir.PEXTERN { + return false // e.g. local from new(expr) + } staticdata.InitAddr(l, loff, staticdata.GlobalLinksym(a)) return true } @@ -542,7 +545,7 @@ func (s *Schedule) initplan(n ir.Node) { if a.Sym().IsBlank() { continue } - s.addvalue(p, a.Field.Offset, a.Value) + s.addvalue(p, typecheck.FieldOffset(n.Type(), a.Field), a.Value) } case ir.OMAPLIT: @@ -760,6 +763,8 @@ func StaticName(t *types.Type) *ir.Name { typecheck.Target.Externs = append(typecheck.Target.Externs, n) n.Linksym().Set(obj.AttrStatic, true) + n.Linksym().Align = int16(t.Alignment()) + return n } diff --git a/src/cmd/compile/internal/syntax/branches.go b/src/cmd/compile/internal/syntax/branches.go index 8b360176e86a4c..3a2479bb8a1eab 100644 --- a/src/cmd/compile/internal/syntax/branches.go +++ b/src/cmd/compile/internal/syntax/branches.go @@ -61,7 +61,7 @@ type block struct { lstmt *LabeledStmt // labeled statement associated with this block, or nil } -func (ls *labelScope) errf(pos Pos, format string, args ...interface{}) { +func (ls *labelScope) errf(pos Pos, format string, args ...any) { ls.errh(Error{pos, fmt.Sprintf(format, args...)}) } diff --git a/src/cmd/compile/internal/syntax/dumper.go b/src/cmd/compile/internal/syntax/dumper.go index d5247886dae531..9a021a4582903d 100644 --- a/src/cmd/compile/internal/syntax/dumper.go +++ b/src/cmd/compile/internal/syntax/dumper.go @@ -89,7 +89,7 @@ type writeError struct { } // printf is a convenience wrapper that takes care of print errors. -func (p *dumper) printf(format string, args ...interface{}) { +func (p *dumper) printf(format string, args ...any) { if _, err := fmt.Fprintf(p, format, args...); err != nil { panic(writeError{err}) } diff --git a/src/cmd/compile/internal/syntax/nodes.go b/src/cmd/compile/internal/syntax/nodes.go index de277fc3d8cdab..34017134bd6c71 100644 --- a/src/cmd/compile/internal/syntax/nodes.go +++ b/src/cmd/compile/internal/syntax/nodes.go @@ -4,6 +4,8 @@ package syntax +import "fmt" + // ---------------------------------------------------------------------------- // Nodes @@ -44,6 +46,10 @@ type File struct { node } +func (f *File) String() string { + return fmt.Sprintf("File{PkgName:%v, DeclList:%v}", f.PkgName, f.DeclList) +} + // ---------------------------------------------------------------------------- // Declarations @@ -113,6 +119,18 @@ type ( } ) +func (d *FuncDecl) String() string { + return fmt.Sprintf("FuncDecl{Name:%v}", d.Name) +} + +func (d *TypeDecl) String() string { + return fmt.Sprintf("TypeDecl{Name:%v}", d.Name) +} + +func (d *VarDecl) String() string { + return fmt.Sprintf("FuncDecl{NameList:%v}", d.NameList) +} + type decl struct{ node } func (*decl) aDecl() {} diff --git a/src/cmd/compile/internal/syntax/operator_string.go b/src/cmd/compile/internal/syntax/operator_string.go index f045d8c55243ea..0f427ffa393a25 100644 --- a/src/cmd/compile/internal/syntax/operator_string.go +++ b/src/cmd/compile/internal/syntax/operator_string.go @@ -38,9 +38,9 @@ const _Operator_name = ":!<-~||&&==!=<<=>>=+-|^*/%&&^<<>>" var _Operator_index = [...]uint8{0, 1, 2, 4, 5, 7, 9, 11, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 33} func (i Operator) String() string { - i -= 1 - if i >= Operator(len(_Operator_index)-1) { - return "Operator(" + strconv.FormatInt(int64(i+1), 10) + ")" + idx := int(i) - 1 + if i < 1 || idx >= len(_Operator_index)-1 { + return "Operator(" + strconv.FormatInt(int64(i), 10) + ")" } - return _Operator_name[_Operator_index[i]:_Operator_index[i+1]] + return _Operator_name[_Operator_index[idx]:_Operator_index[idx+1]] } diff --git a/src/cmd/compile/internal/syntax/parser.go b/src/cmd/compile/internal/syntax/parser.go index 82786859435b97..f1f15c60a21070 100644 --- a/src/cmd/compile/internal/syntax/parser.go +++ b/src/cmd/compile/internal/syntax/parser.go @@ -8,6 +8,7 @@ import ( "fmt" "go/build/constraint" "io" + "path/filepath" "strconv" "strings" ) @@ -161,6 +162,13 @@ func (p *parser) updateBase(pos Pos, tline, tcol uint, text string) { if filename == "" && ok2 { filename = p.base.Filename() trimmed = p.base.Trimmed() + } else if filename != "" { + filename = filepath.Clean(filename) + if !filepath.IsAbs(filename) { + if dir := filepath.Dir(p.file.Filename()); dir != "." { + filename = filepath.Join(dir, filename) + } + } } p.base = NewLineBase(pos, filename, trimmed, line, col) @@ -797,9 +805,9 @@ func (p *parser) funcDeclOrNil() *FuncDecl { f.pos = p.pos() f.Pragma = p.takePragma() - var context string + hasRecv := false if p.got(_Lparen) { - context = "method" + hasRecv = true rcvr := p.paramList(nil, nil, _Rparen, false, false) switch len(rcvr) { case 0: @@ -814,13 +822,13 @@ func (p *parser) funcDeclOrNil() *FuncDecl { if p.tok == _Name { f.Name = p.name() - f.TParamList, f.Type = p.funcType(context) + f.TParamList, f.Type = p.funcType("") } else { f.Name = NewName(p.pos(), "_") f.Type = new(FuncType) f.Type.pos = p.pos() msg := "expected name or (" - if context != "" { + if hasRecv { msg = "expected name" } p.syntaxError(msg) diff --git a/src/cmd/compile/internal/syntax/parser_test.go b/src/cmd/compile/internal/syntax/parser_test.go index b6c4b8fd5693d1..1f5d44caa9ded3 100644 --- a/src/cmd/compile/internal/syntax/parser_test.go +++ b/src/cmd/compile/internal/syntax/parser_test.go @@ -232,7 +232,7 @@ func TestParseFile(t *testing.T) { var tooLarge int = PosMax + 1 func TestLineDirectives(t *testing.T) { - // valid line directives lead to a syntax error after them + // valid line directives lead to this syntax error after them const valid = "syntax error: package statement must be first" const filename = "directives.go" @@ -271,11 +271,9 @@ func TestLineDirectives(t *testing.T) { {fmt.Sprintf("//line foo:10:%d\n", tooLarge), fmt.Sprintf("invalid column number: %d", tooLarge), filename, 1, 15}, // effect of valid //line directives on lines - {"//line foo:123\n foo", valid, "foo", 123, 0}, - {"//line foo:123\n foo", valid, " foo", 123, 0}, + {"//line foo:123\n", valid, "foo", 123, 0}, + {"//line foo:123\n", valid, " foo", 123, 0}, {"//line foo:123\n//line bar:345\nfoo", valid, "bar", 345, 0}, - {"//line C:foo:123\n", valid, "C:foo", 123, 0}, - {"//line /src/a/a.go:123\n foo", valid, "/src/a/a.go", 123, 0}, {"//line :x:1\n", valid, ":x", 1, 0}, {"//line foo ::1\n", valid, "foo :", 1, 0}, {"//line foo:123abc:1\n", valid, "foo:123abc", 1, 0}, @@ -324,10 +322,8 @@ func TestLineDirectives(t *testing.T) { {fmt.Sprintf("/*line foo:10:%d*/", tooLarge), fmt.Sprintf("invalid column number: %d", tooLarge), filename, 1, 15}, // effect of valid /*line directives on lines - {"/*line foo:123*/ foo", valid, "foo", 123, 0}, + {"/*line foo:123*/", valid, "foo", 123, 0}, {"/*line foo:123*/\n//line bar:345\nfoo", valid, "bar", 345, 0}, - {"/*line C:foo:123*/", valid, "C:foo", 123, 0}, - {"/*line /src/a/a.go:123*/ foo", valid, "/src/a/a.go", 123, 0}, {"/*line :x:1*/", valid, ":x", 1, 0}, {"/*line foo ::1*/", valid, "foo :", 1, 0}, {"/*line foo:123abc:1*/", valid, "foo:123abc", 1, 0}, @@ -346,6 +342,14 @@ func TestLineDirectives(t *testing.T) { {"/*line :10:20*/", valid, filename, 10, 20}, {"//line bar:1\n/*line :10*/", valid, "", 10, 0}, {"//line bar:1\n/*line :10:20*/", valid, "bar", 10, 20}, + + // effect of cleaning filenames + {"//line C:foo:123\n", valid, filepath.Clean("C:foo"), 123, 0}, + {"//line /src/a/a.go:123\n", valid, filepath.Clean("/src/a/a.go"), 123, 0}, + {"//line foo/../bar:1\n", valid, filepath.Clean("foo/../bar"), 1, 0}, + {"/*line C:foo:123*/", valid, filepath.Clean("C:foo"), 123, 0}, + {"/*line /src/a/a.go:123*/", valid, filepath.Clean("/src/a/a.go"), 123, 0}, + {"/*line foo/../bar:1*/", valid, filepath.Clean("foo/../bar"), 1, 0}, } { base := NewFileBase(filename) _, err := Parse(base, strings.NewReader(test.src), nil, nil, 0) @@ -375,6 +379,44 @@ func TestLineDirectives(t *testing.T) { } } +func TestLineDirectivesWithDir(t *testing.T) { + const dir = "dir" + filename := filepath.Join(dir, "directives.go") + + type test struct{ src, filename string } + relPaths := []test{ + {"//line foo:1\n", filepath.Join(dir, "foo")}, + {"//line ./foo:1\n", filepath.Join(dir, "foo")}, + {"//line ../foo:1\n", "foo"}, + {"//line sub/foo:1\n", filepath.Join(dir, "sub", "foo")}, + {"/*line foo:1*/", filepath.Join(dir, "foo")}, + {"//line bar:1\n//line :2:1\n", filepath.Join(dir, "bar")}, + } + + var absPaths []test + if runtime.GOOS == "windows" { + absPaths = []test{ + {"//line c:\\bar:1\n", "c:\\bar"}, + } + } else { + absPaths = []test{ + {"//line /abs/foo:1\n", "/abs/foo"}, + {"//line /src/a/a.go:1\n", "/src/a/a.go"}, + } + } + + for _, test := range append(relPaths, absPaths...) { + base := NewFileBase(filename) + pkg, err := Parse(base, strings.NewReader(test.src+"package p"), nil, nil, 0) + if err != nil { + t.Error(err) + } + if got := pkg.Pos().RelFilename(); got != test.filename { + t.Errorf("%s: got filename = %q; want %q", test.src, got, test.filename) + } + } +} + // Test that typical uses of UnpackListExpr don't allocate. func TestUnpackListExprAllocs(t *testing.T) { var x Expr = NewName(Pos{}, "x") diff --git a/src/cmd/compile/internal/syntax/printer.go b/src/cmd/compile/internal/syntax/printer.go index d86d77e73f70ec..86d93e8932d2b3 100644 --- a/src/cmd/compile/internal/syntax/printer.go +++ b/src/cmd/compile/internal/syntax/printer.go @@ -247,7 +247,7 @@ func mayCombine(prev token, next byte) (b bool) { // return } -func (p *printer) print(args ...interface{}) { +func (p *printer) print(args ...any) { for i := 0; i < len(args); i++ { switch x := args[i].(type) { case nil: @@ -455,7 +455,7 @@ func (p *printer) printRawNode(n Node) { p.printExprList(n.ElemList) case *ArrayType: - var len interface{} = _DotDotDot + var len any = _DotDotDot if n.Len != nil { len = n.Len } diff --git a/src/cmd/compile/internal/syntax/scanner.go b/src/cmd/compile/internal/syntax/scanner.go index 807d8383866dcb..700908f6bda28a 100644 --- a/src/cmd/compile/internal/syntax/scanner.go +++ b/src/cmd/compile/internal/syntax/scanner.go @@ -50,12 +50,12 @@ func (s *scanner) init(src io.Reader, errh func(line, col uint, msg string), mod } // errorf reports an error at the most recently read character position. -func (s *scanner) errorf(format string, args ...interface{}) { +func (s *scanner) errorf(format string, args ...any) { s.error(fmt.Sprintf(format, args...)) } // errorAtf reports an error at a byte column offset relative to the current token start. -func (s *scanner) errorAtf(offset int, format string, args ...interface{}) { +func (s *scanner) errorAtf(offset int, format string, args ...any) { s.errh(s.line, s.col+uint(offset), fmt.Sprintf(format, args...)) } diff --git a/src/cmd/compile/internal/syntax/syntax.go b/src/cmd/compile/internal/syntax/syntax.go index 83b102da9f564e..dd8f2b82004571 100644 --- a/src/cmd/compile/internal/syntax/syntax.go +++ b/src/cmd/compile/internal/syntax/syntax.go @@ -36,7 +36,7 @@ type ErrorHandler func(err error) // A Pragma value augments a package, import, const, func, type, or var declaration. // Its meaning is entirely up to the PragmaHandler, // except that nil is used to mean “no pragma seen.” -type Pragma interface{} +type Pragma any // A PragmaHandler is used to process //go: directives while scanning. // It is passed the current pragma value, which starts out being nil, diff --git a/src/cmd/compile/internal/syntax/testdata/smoketest.go b/src/cmd/compile/internal/syntax/testdata/smoketest.go index 6b3593ac7ad122..e7c9f7283f6be0 100644 --- a/src/cmd/compile/internal/syntax/testdata/smoketest.go +++ b/src/cmd/compile/internal/syntax/testdata/smoketest.go @@ -71,3 +71,33 @@ type _ interface { T[P] T[P1, P2] } + +// generic method +type List[E any] []E + +func (l List[E]) Map[F any](m func(E) F) (r List[F]) { + for _, x := range l { + r = append(r, m(x)) + } + return +} + +func _() { + l := List[string]{"foo", "foobar", "42"} + r := l.Map(func(s string) int { return len(s)}) + _ = r +} + +func _[E, F any](l List[E]) List[F] { + var f func(List[E], func(E) F) List[F] = List[E].Map // method expression & type inference + return f(l, func(E) F { var f F; return f }) +} + +// disallowed type parameters + +type _ func /* ERROR function type must have no type parameters */ [P any](P) +type _ interface { + m /* ERROR interface method must have no type parameters */ [P any](P) +} + +var _ = func /* ERROR function type must have no type parameters */ [P any](P) {} diff --git a/src/cmd/compile/internal/syntax/token_string.go b/src/cmd/compile/internal/syntax/token_string.go index ef295eb24b2bc9..eaad90c0972431 100644 --- a/src/cmd/compile/internal/syntax/token_string.go +++ b/src/cmd/compile/internal/syntax/token_string.go @@ -62,9 +62,9 @@ const _token_name = "EOFnameliteralopop=opop=:=<-*([{)]},;:....breakcasechancons var _token_index = [...]uint8{0, 3, 7, 14, 16, 19, 23, 24, 26, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 42, 47, 51, 55, 60, 68, 75, 80, 84, 95, 98, 102, 104, 108, 110, 116, 125, 128, 135, 140, 146, 152, 158, 164, 168, 171, 171} func (i token) String() string { - i -= 1 - if i >= token(len(_token_index)-1) { - return "token(" + strconv.FormatInt(int64(i+1), 10) + ")" + idx := int(i) - 1 + if i < 1 || idx >= len(_token_index)-1 { + return "token(" + strconv.FormatInt(int64(i), 10) + ")" } - return _token_name[_token_index[i]:_token_index[i+1]] + return _token_name[_token_index[idx]:_token_index[idx+1]] } diff --git a/src/cmd/compile/internal/test/bench_test.go b/src/cmd/compile/internal/test/bench_test.go index 7303f672fee2a2..1d74d39a49fe78 100644 --- a/src/cmd/compile/internal/test/bench_test.go +++ b/src/cmd/compile/internal/test/bench_test.go @@ -4,7 +4,10 @@ package test -import "testing" +import ( + "fmt" + "testing" +) var globl int64 var globl32 int32 @@ -145,3 +148,82 @@ func BenchmarkMul2Neg(b *testing.B) { globl = s } } + +func BenchmarkSimplifyNegMul(b *testing.B) { + x := make([]int64, 1024) + y := make([]int64, 1024) + b.ResetTimer() + for i := 0; i < b.N; i++ { + var s int64 + for i := range x { + s = -(-x[i] * y[i]) + } + globl = s + } +} + +func BenchmarkSimplifyNegDiv(b *testing.B) { + x := make([]int64, 1024) + y := make([]int64, 1024) + for i := range y { + y[i] = 42 + } + b.ResetTimer() + for i := 0; i < b.N; i++ { + var s int64 + for i := range x { + s = -(-x[i] / y[i]) + } + globl = s + } +} + +var globbool bool + +// containsRight compares strs[i] == str (slice element on left). +// +//go:noinline +func containsRight(strs []string, str string) bool { + for i := range strs { + if strs[i] == str { + return true + } + } + return false +} + +// containsLeft compares str == strs[i] (parameter on left). +// +//go:noinline +func containsLeft(strs []string, str string) bool { + for i := range strs { + if str == strs[i] { + return true + } + } + return false +} + +// BenchmarkStringEqParamOrder tests that the operand order of string +// equality comparisons does not affect performance. See issue #74471. +func BenchmarkStringEqParamOrder(b *testing.B) { + strs := []string{ + "12312312", "abcsdsfw", "abcdefgh", "qereqwre", + "gwertdsg", "hellowod", "iamgroot", "theiswer", + "dg323sdf", "gadsewwe", "g42dg4t3", "4hre2323", + "23eg4325", "13234234", "32dfgsdg", "23fgre34", + "43rerrer", "hh2s2443", "hhwesded", "1swdf23d", + "gwcdrwer", "bfgwertd", "badgwe3g", "lhoejyop", + } + target := fmt.Sprintf("%s", "notfound") + b.Run("ParamRight", func(b *testing.B) { + for b.Loop() { + globbool = containsRight(strs, target) + } + }) + b.Run("ParamLeft", func(b *testing.B) { + for b.Loop() { + globbool = containsLeft(strs, target) + } + }) +} diff --git a/src/cmd/compile/internal/test/conditionalCmpConst_test.go b/src/cmd/compile/internal/test/conditionalCmpConst_test.go new file mode 100644 index 00000000000000..2f384da715999a --- /dev/null +++ b/src/cmd/compile/internal/test/conditionalCmpConst_test.go @@ -0,0 +1,4408 @@ +// Code generated by conditionalCmpConstGen.go; DO NOT EDIT. + +package test + +import "testing" + +type IntegerConstraint interface { + int | uint | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 +} + +type TestCase[T IntegerConstraint] struct { + cmp1, cmp2 func(a, b T) bool + combine func(x, y bool) bool + targetFunc func(a, b, c, d T) bool + cmp1Expr, cmp2Expr, logicalExpr string // String representations for debugging +} + +type BoundaryValues[T IntegerConstraint] struct { + base T + variants [3]T +} + +func generateTestCases[T IntegerConstraint]() []TestCase[T] { + return []TestCase[T]{ + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c == d", + logicalExpr: "(a == b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c == d", + logicalExpr: "(a == b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c == d", + logicalExpr: "!(a == b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c == d", + logicalExpr: "!(a == b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c == d", + logicalExpr: "(a == b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c == d", + logicalExpr: "(a == b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c == d", + logicalExpr: "!(a == b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c == d", + logicalExpr: "!(a == b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c <= d", + logicalExpr: "(a == b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c <= d", + logicalExpr: "(a == b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c <= d", + logicalExpr: "!(a == b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c <= d", + logicalExpr: "!(a == b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c <= d", + logicalExpr: "(a == b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c <= d", + logicalExpr: "(a == b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c <= d", + logicalExpr: "!(a == b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c <= d", + logicalExpr: "!(a == b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c < d", + logicalExpr: "(a == b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c < d", + logicalExpr: "(a == b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c < d", + logicalExpr: "!(a == b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c < d", + logicalExpr: "!(a == b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c < d", + logicalExpr: "(a == b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c < d", + logicalExpr: "(a == b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c < d", + logicalExpr: "!(a == b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c < d", + logicalExpr: "!(a == b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c != d", + logicalExpr: "(a == b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c != d", + logicalExpr: "(a == b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c != d", + logicalExpr: "!(a == b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c != d", + logicalExpr: "!(a == b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c != d", + logicalExpr: "(a == b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c != d", + logicalExpr: "(a == b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c != d", + logicalExpr: "!(a == b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c != d", + logicalExpr: "!(a == b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c >= d", + logicalExpr: "(a == b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c >= d", + logicalExpr: "(a == b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c >= d", + logicalExpr: "!(a == b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c >= d", + logicalExpr: "!(a == b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c >= d", + logicalExpr: "(a == b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c >= d", + logicalExpr: "(a == b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c >= d", + logicalExpr: "!(a == b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c >= d", + logicalExpr: "!(a == b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c > d", + logicalExpr: "(a == b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c > d", + logicalExpr: "(a == b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c > d", + logicalExpr: "!(a == b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c > d", + logicalExpr: "!(a == b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c > d", + logicalExpr: "(a == b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a == b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c > d", + logicalExpr: "(a == b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c > d", + logicalExpr: "!(a == b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a == b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a == b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a == b", + cmp2Expr: "c > d", + logicalExpr: "!(a == b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c == d", + logicalExpr: "(a <= b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c == d", + logicalExpr: "(a <= b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c == d", + logicalExpr: "!(a <= b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c == d", + logicalExpr: "!(a <= b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c == d", + logicalExpr: "(a <= b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c == d", + logicalExpr: "(a <= b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c == d", + logicalExpr: "!(a <= b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c == d", + logicalExpr: "!(a <= b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c <= d", + logicalExpr: "(a <= b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c <= d", + logicalExpr: "(a <= b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c <= d", + logicalExpr: "!(a <= b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c <= d", + logicalExpr: "!(a <= b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c <= d", + logicalExpr: "(a <= b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c <= d", + logicalExpr: "(a <= b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c <= d", + logicalExpr: "!(a <= b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c <= d", + logicalExpr: "!(a <= b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c < d", + logicalExpr: "(a <= b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c < d", + logicalExpr: "(a <= b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c < d", + logicalExpr: "!(a <= b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c < d", + logicalExpr: "!(a <= b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c < d", + logicalExpr: "(a <= b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c < d", + logicalExpr: "(a <= b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c < d", + logicalExpr: "!(a <= b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c < d", + logicalExpr: "!(a <= b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c != d", + logicalExpr: "(a <= b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c != d", + logicalExpr: "(a <= b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c != d", + logicalExpr: "!(a <= b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c != d", + logicalExpr: "!(a <= b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c != d", + logicalExpr: "(a <= b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c != d", + logicalExpr: "(a <= b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c != d", + logicalExpr: "!(a <= b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c != d", + logicalExpr: "!(a <= b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c >= d", + logicalExpr: "(a <= b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c >= d", + logicalExpr: "(a <= b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c >= d", + logicalExpr: "!(a <= b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c >= d", + logicalExpr: "!(a <= b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c >= d", + logicalExpr: "(a <= b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c >= d", + logicalExpr: "(a <= b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c >= d", + logicalExpr: "!(a <= b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c >= d", + logicalExpr: "!(a <= b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c > d", + logicalExpr: "(a <= b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c > d", + logicalExpr: "(a <= b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c > d", + logicalExpr: "!(a <= b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c > d", + logicalExpr: "!(a <= b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c > d", + logicalExpr: "(a <= b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a <= b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c > d", + logicalExpr: "(a <= b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c > d", + logicalExpr: "!(a <= b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a <= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a <= b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a <= b", + cmp2Expr: "c > d", + logicalExpr: "!(a <= b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c == d", + logicalExpr: "(a < b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c == d", + logicalExpr: "(a < b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c == d", + logicalExpr: "!(a < b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c == d", + logicalExpr: "!(a < b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c == d", + logicalExpr: "(a < b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c == d", + logicalExpr: "(a < b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c == d", + logicalExpr: "!(a < b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c == d", + logicalExpr: "!(a < b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c <= d", + logicalExpr: "(a < b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c <= d", + logicalExpr: "(a < b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c <= d", + logicalExpr: "!(a < b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c <= d", + logicalExpr: "!(a < b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c <= d", + logicalExpr: "(a < b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c <= d", + logicalExpr: "(a < b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c <= d", + logicalExpr: "!(a < b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c <= d", + logicalExpr: "!(a < b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c < d", + logicalExpr: "(a < b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c < d", + logicalExpr: "(a < b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c < d", + logicalExpr: "!(a < b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c < d", + logicalExpr: "!(a < b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c < d", + logicalExpr: "(a < b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c < d", + logicalExpr: "(a < b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c < d", + logicalExpr: "!(a < b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c < d", + logicalExpr: "!(a < b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c != d", + logicalExpr: "(a < b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c != d", + logicalExpr: "(a < b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c != d", + logicalExpr: "!(a < b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c != d", + logicalExpr: "!(a < b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c != d", + logicalExpr: "(a < b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c != d", + logicalExpr: "(a < b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c != d", + logicalExpr: "!(a < b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c != d", + logicalExpr: "!(a < b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c >= d", + logicalExpr: "(a < b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c >= d", + logicalExpr: "(a < b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c >= d", + logicalExpr: "!(a < b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c >= d", + logicalExpr: "!(a < b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c >= d", + logicalExpr: "(a < b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c >= d", + logicalExpr: "(a < b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c >= d", + logicalExpr: "!(a < b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c >= d", + logicalExpr: "!(a < b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c > d", + logicalExpr: "(a < b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c > d", + logicalExpr: "(a < b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c > d", + logicalExpr: "!(a < b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c > d", + logicalExpr: "!(a < b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c > d", + logicalExpr: "(a < b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a < b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c > d", + logicalExpr: "(a < b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c > d", + logicalExpr: "!(a < b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a < b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a < b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a < b", + cmp2Expr: "c > d", + logicalExpr: "!(a < b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c == d", + logicalExpr: "(a != b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c == d", + logicalExpr: "(a != b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c == d", + logicalExpr: "!(a != b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c == d", + logicalExpr: "!(a != b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c == d", + logicalExpr: "(a != b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c == d", + logicalExpr: "(a != b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c == d", + logicalExpr: "!(a != b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c == d", + logicalExpr: "!(a != b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c <= d", + logicalExpr: "(a != b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c <= d", + logicalExpr: "(a != b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c <= d", + logicalExpr: "!(a != b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c <= d", + logicalExpr: "!(a != b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c <= d", + logicalExpr: "(a != b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c <= d", + logicalExpr: "(a != b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c <= d", + logicalExpr: "!(a != b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c <= d", + logicalExpr: "!(a != b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c < d", + logicalExpr: "(a != b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c < d", + logicalExpr: "(a != b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c < d", + logicalExpr: "!(a != b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c < d", + logicalExpr: "!(a != b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c < d", + logicalExpr: "(a != b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c < d", + logicalExpr: "(a != b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c < d", + logicalExpr: "!(a != b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c < d", + logicalExpr: "!(a != b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c != d", + logicalExpr: "(a != b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c != d", + logicalExpr: "(a != b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c != d", + logicalExpr: "!(a != b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c != d", + logicalExpr: "!(a != b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c != d", + logicalExpr: "(a != b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c != d", + logicalExpr: "(a != b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c != d", + logicalExpr: "!(a != b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c != d", + logicalExpr: "!(a != b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c >= d", + logicalExpr: "(a != b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c >= d", + logicalExpr: "(a != b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c >= d", + logicalExpr: "!(a != b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c >= d", + logicalExpr: "!(a != b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c >= d", + logicalExpr: "(a != b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c >= d", + logicalExpr: "(a != b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c >= d", + logicalExpr: "!(a != b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c >= d", + logicalExpr: "!(a != b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c > d", + logicalExpr: "(a != b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c > d", + logicalExpr: "(a != b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c > d", + logicalExpr: "!(a != b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c > d", + logicalExpr: "!(a != b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c > d", + logicalExpr: "(a != b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a != b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c > d", + logicalExpr: "(a != b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c > d", + logicalExpr: "!(a != b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a != b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a != b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a != b", + cmp2Expr: "c > d", + logicalExpr: "!(a != b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c == d", + logicalExpr: "(a >= b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c == d", + logicalExpr: "(a >= b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c == d", + logicalExpr: "!(a >= b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c == d", + logicalExpr: "!(a >= b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c == d", + logicalExpr: "(a >= b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c == d", + logicalExpr: "(a >= b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c == d", + logicalExpr: "!(a >= b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c == d", + logicalExpr: "!(a >= b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c <= d", + logicalExpr: "(a >= b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c <= d", + logicalExpr: "(a >= b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c <= d", + logicalExpr: "!(a >= b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c <= d", + logicalExpr: "!(a >= b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c <= d", + logicalExpr: "(a >= b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c <= d", + logicalExpr: "(a >= b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c <= d", + logicalExpr: "!(a >= b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c <= d", + logicalExpr: "!(a >= b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c < d", + logicalExpr: "(a >= b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c < d", + logicalExpr: "(a >= b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c < d", + logicalExpr: "!(a >= b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c < d", + logicalExpr: "!(a >= b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c < d", + logicalExpr: "(a >= b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c < d", + logicalExpr: "(a >= b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c < d", + logicalExpr: "!(a >= b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c < d", + logicalExpr: "!(a >= b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c != d", + logicalExpr: "(a >= b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c != d", + logicalExpr: "(a >= b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c != d", + logicalExpr: "!(a >= b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c != d", + logicalExpr: "!(a >= b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c != d", + logicalExpr: "(a >= b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c != d", + logicalExpr: "(a >= b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c != d", + logicalExpr: "!(a >= b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c != d", + logicalExpr: "!(a >= b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c >= d", + logicalExpr: "(a >= b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c >= d", + logicalExpr: "(a >= b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c >= d", + logicalExpr: "!(a >= b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c >= d", + logicalExpr: "!(a >= b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c >= d", + logicalExpr: "(a >= b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c >= d", + logicalExpr: "(a >= b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c >= d", + logicalExpr: "!(a >= b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c >= d", + logicalExpr: "!(a >= b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c > d", + logicalExpr: "(a >= b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c > d", + logicalExpr: "(a >= b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c > d", + logicalExpr: "!(a >= b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c > d", + logicalExpr: "!(a >= b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c > d", + logicalExpr: "(a >= b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a >= b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c > d", + logicalExpr: "(a >= b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c > d", + logicalExpr: "!(a >= b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a >= b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a >= b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a >= b", + cmp2Expr: "c > d", + logicalExpr: "!(a >= b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c == d", + logicalExpr: "(a > b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c == d", + logicalExpr: "(a > b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && (c == d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c == d", + logicalExpr: "!(a > b) && (c == d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && !(c == d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c == d", + logicalExpr: "!(a > b) && !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c == d", + logicalExpr: "(a > b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c == d", + logicalExpr: "(a > b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || (c == d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c == d", + logicalExpr: "!(a > b) || (c == d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a == b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || !(c == d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c == d", + logicalExpr: "!(a > b) || !(c == d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c <= d", + logicalExpr: "(a > b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c <= d", + logicalExpr: "(a > b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && (c <= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c <= d", + logicalExpr: "!(a > b) && (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c <= d", + logicalExpr: "!(a > b) && !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c <= d", + logicalExpr: "(a > b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c <= d", + logicalExpr: "(a > b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || (c <= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c <= d", + logicalExpr: "!(a > b) || (c <= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a <= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || !(c <= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c <= d", + logicalExpr: "!(a > b) || !(c <= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c < d", + logicalExpr: "(a > b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c < d", + logicalExpr: "(a > b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && (c < d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c < d", + logicalExpr: "!(a > b) && (c < d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && !(c < d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c < d", + logicalExpr: "!(a > b) && !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c < d", + logicalExpr: "(a > b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c < d", + logicalExpr: "(a > b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || (c < d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c < d", + logicalExpr: "!(a > b) || (c < d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a < b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || !(c < d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c < d", + logicalExpr: "!(a > b) || !(c < d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c != d", + logicalExpr: "(a > b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c != d", + logicalExpr: "(a > b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && (c != d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c != d", + logicalExpr: "!(a > b) && (c != d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && !(c != d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c != d", + logicalExpr: "!(a > b) && !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c != d", + logicalExpr: "(a > b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c != d", + logicalExpr: "(a > b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || (c != d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c != d", + logicalExpr: "!(a > b) || (c != d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a != b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || !(c != d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c != d", + logicalExpr: "!(a > b) || !(c != d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c >= d", + logicalExpr: "(a > b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c >= d", + logicalExpr: "(a > b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && (c >= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c >= d", + logicalExpr: "!(a > b) && (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c >= d", + logicalExpr: "!(a > b) && !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c >= d", + logicalExpr: "(a > b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c >= d", + logicalExpr: "(a > b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || (c >= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c >= d", + logicalExpr: "!(a > b) || (c >= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a >= b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || !(c >= d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c >= d", + logicalExpr: "!(a > b) || !(c >= d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c > d", + logicalExpr: "(a > b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c > d", + logicalExpr: "(a > b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && (c > d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c > d", + logicalExpr: "!(a > b) && (c > d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) && !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) && !(c > d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c > d", + logicalExpr: "!(a > b) && !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c > d", + logicalExpr: "(a > b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return (x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if (a > b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c > d", + logicalExpr: "(a > b) || !(c > d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || (y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || (c > d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c > d", + logicalExpr: "!(a > b) || (c > d)", + }, + { + cmp1: func(a, b T) bool { return a > b }, + cmp2: func(a, b T) bool { return a > b }, + combine: func(x, y bool) bool { return !(x) || !(y) }, + targetFunc: func(a, b, c, d T) bool { + if !(a > b) || !(c > d) { + return true + } + return false + }, + cmp1Expr: "a > b", + cmp2Expr: "c > d", + logicalExpr: "!(a > b) || !(c > d)", + }, + } +} + +func TestInt8ConditionalCmpConst(t *testing.T) { + testCases := generateTestCases[int8]() + base := int8(1 << 6) + values := [3]int8{base - 1, base, base + 1} + + for _, tc := range testCases { + a, c := base, base + for _, b := range values { + for _, d := range values { + expected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d)) + actual := tc.targetFunc(a, b, c, d) + if actual != expected { + t.Errorf("conditional comparison failed:\n"+ + " type: %T\n"+ + " condition: %s\n"+ + " values: a=%v, b=%v, c=%v, d=%v\n"+ + " cmp1(a,b)=%v (%s)\n"+ + " cmp2(c,d)=%v (%s)\n"+ + " expected: combine(%v, %v)=%v\n"+ + " actual: %v\n"+ + " logical expression: %s", + a, + tc.logicalExpr, + a, b, c, d, + tc.cmp1(a, b), tc.cmp1Expr, + tc.cmp2(c, d), tc.cmp2Expr, + tc.cmp1(a, b), tc.cmp2(c, d), expected, + actual, + tc.logicalExpr) + } + } + } + } +} + +func TestUint8ConditionalCmpConst(t *testing.T) { + testCases := generateTestCases[uint8]() + base := uint8(1 << 6) + values := [3]uint8{base - 1, base, base + 1} + + for _, tc := range testCases { + a, c := base, base + for _, b := range values { + for _, d := range values { + expected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d)) + actual := tc.targetFunc(a, b, c, d) + if actual != expected { + t.Errorf("conditional comparison failed:\n"+ + " type: %T\n"+ + " condition: %s\n"+ + " values: a=%v, b=%v, c=%v, d=%v\n"+ + " cmp1(a,b)=%v (%s)\n"+ + " cmp2(c,d)=%v (%s)\n"+ + " expected: combine(%v, %v)=%v\n"+ + " actual: %v\n"+ + " logical expression: %s", + a, + tc.logicalExpr, + a, b, c, d, + tc.cmp1(a, b), tc.cmp1Expr, + tc.cmp2(c, d), tc.cmp2Expr, + tc.cmp1(a, b), tc.cmp2(c, d), expected, + actual, + tc.logicalExpr) + } + } + } + } +} + +func TestInt16ConditionalCmpConst(t *testing.T) { + testCases := generateTestCases[int16]() + base := int16(1 << 14) + values := [3]int16{base - 1, base, base + 1} + + for _, tc := range testCases { + a, c := base, base + for _, b := range values { + for _, d := range values { + expected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d)) + actual := tc.targetFunc(a, b, c, d) + if actual != expected { + t.Errorf("conditional comparison failed:\n"+ + " type: %T\n"+ + " condition: %s\n"+ + " values: a=%v, b=%v, c=%v, d=%v\n"+ + " cmp1(a,b)=%v (%s)\n"+ + " cmp2(c,d)=%v (%s)\n"+ + " expected: combine(%v, %v)=%v\n"+ + " actual: %v\n"+ + " logical expression: %s", + a, + tc.logicalExpr, + a, b, c, d, + tc.cmp1(a, b), tc.cmp1Expr, + tc.cmp2(c, d), tc.cmp2Expr, + tc.cmp1(a, b), tc.cmp2(c, d), expected, + actual, + tc.logicalExpr) + } + } + } + } +} + +func TestUint16ConditionalCmpConst(t *testing.T) { + testCases := generateTestCases[uint16]() + base := uint16(1 << 14) + values := [3]uint16{base - 1, base, base + 1} + + for _, tc := range testCases { + a, c := base, base + for _, b := range values { + for _, d := range values { + expected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d)) + actual := tc.targetFunc(a, b, c, d) + if actual != expected { + t.Errorf("conditional comparison failed:\n"+ + " type: %T\n"+ + " condition: %s\n"+ + " values: a=%v, b=%v, c=%v, d=%v\n"+ + " cmp1(a,b)=%v (%s)\n"+ + " cmp2(c,d)=%v (%s)\n"+ + " expected: combine(%v, %v)=%v\n"+ + " actual: %v\n"+ + " logical expression: %s", + a, + tc.logicalExpr, + a, b, c, d, + tc.cmp1(a, b), tc.cmp1Expr, + tc.cmp2(c, d), tc.cmp2Expr, + tc.cmp1(a, b), tc.cmp2(c, d), expected, + actual, + tc.logicalExpr) + } + } + } + } +} + +func TestInt32ConditionalCmpConst(t *testing.T) { + testCases := generateTestCases[int32]() + base := int32(1 << 30) + values := [3]int32{base - 1, base, base + 1} + + for _, tc := range testCases { + a, c := base, base + for _, b := range values { + for _, d := range values { + expected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d)) + actual := tc.targetFunc(a, b, c, d) + if actual != expected { + t.Errorf("conditional comparison failed:\n"+ + " type: %T\n"+ + " condition: %s\n"+ + " values: a=%v, b=%v, c=%v, d=%v\n"+ + " cmp1(a,b)=%v (%s)\n"+ + " cmp2(c,d)=%v (%s)\n"+ + " expected: combine(%v, %v)=%v\n"+ + " actual: %v\n"+ + " logical expression: %s", + a, + tc.logicalExpr, + a, b, c, d, + tc.cmp1(a, b), tc.cmp1Expr, + tc.cmp2(c, d), tc.cmp2Expr, + tc.cmp1(a, b), tc.cmp2(c, d), expected, + actual, + tc.logicalExpr) + } + } + } + } +} + +func TestUint32ConditionalCmpConst(t *testing.T) { + testCases := generateTestCases[uint32]() + base := uint32(1 << 30) + values := [3]uint32{base - 1, base, base + 1} + + for _, tc := range testCases { + a, c := base, base + for _, b := range values { + for _, d := range values { + expected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d)) + actual := tc.targetFunc(a, b, c, d) + if actual != expected { + t.Errorf("conditional comparison failed:\n"+ + " type: %T\n"+ + " condition: %s\n"+ + " values: a=%v, b=%v, c=%v, d=%v\n"+ + " cmp1(a,b)=%v (%s)\n"+ + " cmp2(c,d)=%v (%s)\n"+ + " expected: combine(%v, %v)=%v\n"+ + " actual: %v\n"+ + " logical expression: %s", + a, + tc.logicalExpr, + a, b, c, d, + tc.cmp1(a, b), tc.cmp1Expr, + tc.cmp2(c, d), tc.cmp2Expr, + tc.cmp1(a, b), tc.cmp2(c, d), expected, + actual, + tc.logicalExpr) + } + } + } + } +} + +func TestIntConditionalCmpConst(t *testing.T) { + testCases := generateTestCases[int]() + base := int(1 << 30) + values := [3]int{base - 1, base, base + 1} + + for _, tc := range testCases { + a, c := base, base + for _, b := range values { + for _, d := range values { + expected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d)) + actual := tc.targetFunc(a, b, c, d) + if actual != expected { + t.Errorf("conditional comparison failed:\n"+ + " type: %T\n"+ + " condition: %s\n"+ + " values: a=%v, b=%v, c=%v, d=%v\n"+ + " cmp1(a,b)=%v (%s)\n"+ + " cmp2(c,d)=%v (%s)\n"+ + " expected: combine(%v, %v)=%v\n"+ + " actual: %v\n"+ + " logical expression: %s", + a, + tc.logicalExpr, + a, b, c, d, + tc.cmp1(a, b), tc.cmp1Expr, + tc.cmp2(c, d), tc.cmp2Expr, + tc.cmp1(a, b), tc.cmp2(c, d), expected, + actual, + tc.logicalExpr) + } + } + } + } +} + +func TestUintConditionalCmpConst(t *testing.T) { + testCases := generateTestCases[uint]() + base := uint(1 << 30) + values := [3]uint{base - 1, base, base + 1} + + for _, tc := range testCases { + a, c := base, base + for _, b := range values { + for _, d := range values { + expected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d)) + actual := tc.targetFunc(a, b, c, d) + if actual != expected { + t.Errorf("conditional comparison failed:\n"+ + " type: %T\n"+ + " condition: %s\n"+ + " values: a=%v, b=%v, c=%v, d=%v\n"+ + " cmp1(a,b)=%v (%s)\n"+ + " cmp2(c,d)=%v (%s)\n"+ + " expected: combine(%v, %v)=%v\n"+ + " actual: %v\n"+ + " logical expression: %s", + a, + tc.logicalExpr, + a, b, c, d, + tc.cmp1(a, b), tc.cmp1Expr, + tc.cmp2(c, d), tc.cmp2Expr, + tc.cmp1(a, b), tc.cmp2(c, d), expected, + actual, + tc.logicalExpr) + } + } + } + } +} + +func TestInt64ConditionalCmpConst(t *testing.T) { + testCases := generateTestCases[int64]() + base := int64(1 << 62) + values := [3]int64{base - 1, base, base + 1} + + for _, tc := range testCases { + a, c := base, base + for _, b := range values { + for _, d := range values { + expected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d)) + actual := tc.targetFunc(a, b, c, d) + if actual != expected { + t.Errorf("conditional comparison failed:\n"+ + " type: %T\n"+ + " condition: %s\n"+ + " values: a=%v, b=%v, c=%v, d=%v\n"+ + " cmp1(a,b)=%v (%s)\n"+ + " cmp2(c,d)=%v (%s)\n"+ + " expected: combine(%v, %v)=%v\n"+ + " actual: %v\n"+ + " logical expression: %s", + a, + tc.logicalExpr, + a, b, c, d, + tc.cmp1(a, b), tc.cmp1Expr, + tc.cmp2(c, d), tc.cmp2Expr, + tc.cmp1(a, b), tc.cmp2(c, d), expected, + actual, + tc.logicalExpr) + } + } + } + } +} + +func TestUint64ConditionalCmpConst(t *testing.T) { + testCases := generateTestCases[uint64]() + base := uint64(1 << 62) + values := [3]uint64{base - 1, base, base + 1} + + for _, tc := range testCases { + a, c := base, base + for _, b := range values { + for _, d := range values { + expected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d)) + actual := tc.targetFunc(a, b, c, d) + if actual != expected { + t.Errorf("conditional comparison failed:\n"+ + " type: %T\n"+ + " condition: %s\n"+ + " values: a=%v, b=%v, c=%v, d=%v\n"+ + " cmp1(a,b)=%v (%s)\n"+ + " cmp2(c,d)=%v (%s)\n"+ + " expected: combine(%v, %v)=%v\n"+ + " actual: %v\n"+ + " logical expression: %s", + a, + tc.logicalExpr, + a, b, c, d, + tc.cmp1(a, b), tc.cmp1Expr, + tc.cmp2(c, d), tc.cmp2Expr, + tc.cmp1(a, b), tc.cmp2(c, d), expected, + actual, + tc.logicalExpr) + } + } + } + } +} diff --git a/src/cmd/compile/internal/test/eq_test.go b/src/cmd/compile/internal/test/eq_test.go new file mode 100644 index 00000000000000..336ec01e08e065 --- /dev/null +++ b/src/cmd/compile/internal/test/eq_test.go @@ -0,0 +1,298 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Tests of generated equality functions. + +package test + +import ( + "reflect" + "testing" + "unsafe" +) + +//go:noinline +func checkEq(t *testing.T, x, y any) { + // Make sure we don't inline the equality test. + if x != y { + t.Errorf("%#v != %#v, wanted equal", x, y) + } +} + +//go:noinline +func checkNe(t *testing.T, x, y any) { + // Make sure we don't inline the equality test. + if x == y { + t.Errorf("%#v == %#v, wanted not equal", x, y) + } +} + +//go:noinline +func checkPanic(t *testing.T, x, y any) { + defer func() { + if recover() == nil { + t.Errorf("%#v == %#v didn't panic", x, y) + } + }() + _ = x == y +} + +type fooComparable struct { + x int +} + +func (f fooComparable) foo() { +} + +type fooIncomparable struct { + b func() +} + +func (i fooIncomparable) foo() { +} + +type eqResult int + +const ( + eq eqResult = iota + ne + panic_ +) + +func (x eqResult) String() string { + return []string{eq: "eq", ne: "ne", panic_: "panic"}[x] +} + +// testEq returns eq if x==y, ne if x!=y, or panic_ if the comparison panics. +func testEq(x, y any) (r eqResult) { + defer func() { + if e := recover(); e != nil { + r = panic_ + } + }() + r = ne + if x == y { + r = eq + } + return +} + +// testCompare make two instances of struct type typ, then +// assigns its len(vals) fields one value from each slice in vals. +// Then it checks the results against a "manual" comparison field +// by field. +func testCompare(t *testing.T, typ reflect.Type, vals [][]any) { + if len(vals) != typ.NumField() { + t.Fatalf("bad test, have %d fields in the list, but %d fields in the type", len(vals), typ.NumField()) + } + + x := reflect.New(typ).Elem() + y := reflect.New(typ).Elem() + ps := powerSet(vals) // all possible settings of fields of the test type. + for _, xf := range ps { // Pick fields for x + for _, yf := range ps { // Pick fields for y + // Make x and y from their chosen fields. + for i, f := range xf { + x.Field(i).Set(reflect.ValueOf(f)) + } + for i, f := range yf { + y.Field(i).Set(reflect.ValueOf(f)) + } + // Compute what we want the result to be. + want := eq + for i := range len(vals) { + if c := testEq(xf[i], yf[i]); c != eq { + want = c + break + } + } + // Compute actual result using generated equality function. + got := testEq(x.Interface(), y.Interface()) + if got != want { + t.Errorf("%#v == %#v, got %s want %s\n", x, y, got, want) + } + } + } +} + +// powerset returns all possible sequences of choosing one +// element from each entry in s. +// For instance, if s = {{1,2}, {a,b}}, then +// it returns {{1,a},{1,b},{2,a},{2,b}}. +func powerSet(s [][]any) [][]any { + if len(s) == 0 { + return [][]any{{}} + } + p := powerSet(s[:len(s)-1]) // powerset from first len(s)-1 entries + var r [][]any + for _, head := range p { + // add one more entry. + for _, v := range s[len(s)-1] { + x := make([]any, 0, len(s)) + x = append(x, head...) + x = append(x, v) + r = append(r, x) + } + } + return r +} + +func TestCompareKinds1(t *testing.T) { + type S struct { + X0 int8 + X1 int16 + X2 int32 + X3 int64 + X4 float32 + X5 float64 + } + testCompare(t, reflect.TypeOf(S{}), [][]any{ + {int8(0), int8(1)}, + {int16(0), int16(1), int16(1 << 14)}, + {int32(0), int32(1), int32(1 << 30)}, + {int64(0), int64(1), int64(1 << 62)}, + {float32(0), float32(1.0)}, + {0.0, 1.0}, + }) +} +func TestCompareKinds2(t *testing.T) { + type S struct { + X0 uint8 + X1 uint16 + X2 uint32 + X3 uint64 + X4 uintptr + X5 bool + } + testCompare(t, reflect.TypeOf(S{}), [][]any{ + {uint8(0), uint8(1)}, + {uint16(0), uint16(1), uint16(1 << 15)}, + {uint32(0), uint32(1), uint32(1 << 31)}, + {uint64(0), uint64(1), uint64(1 << 63)}, + {uintptr(0), uintptr(1)}, + {false, true}, + }) +} +func TestCompareKinds3(t *testing.T) { + type S struct { + X0 complex64 + X1 complex128 + X2 *byte + X3 chan int + X4 unsafe.Pointer + } + testCompare(t, reflect.TypeOf(S{}), [][]any{ + {complex64(1 + 1i), complex64(1 + 2i), complex64(2 + 1i)}, + {complex128(1 + 1i), complex128(1 + 2i), complex128(2 + 1i)}, + {new(byte), new(byte)}, + {make(chan int), make(chan int)}, + {unsafe.Pointer(new(byte)), unsafe.Pointer(new(byte))}, + }) +} + +func TestCompareOrdering(t *testing.T) { + type S struct { + A string + E any + B string + } + + testCompare(t, reflect.TypeOf(S{}), [][]any{ + {"a", "b", "cc"}, + {3, []byte{0}, []byte{1}}, + {"a", "b", "cc"}, + }) +} +func TestCompareInterfaces(t *testing.T) { + type S struct { + A any + B fooer + } + testCompare(t, reflect.TypeOf(S{}), [][]any{ + {3, []byte{0}}, + {fooComparable{x: 3}, fooIncomparable{b: nil}}, + }) +} + +func TestCompareSkip(t *testing.T) { + type S struct { + A int8 + B int16 + } + type S2 struct { + A int8 + padding int8 + B int16 + } + x := S{A: 1, B: 3} + y := S{A: 1, B: 3} + (*S2)(unsafe.Pointer(&x)).padding = 88 + (*S2)(unsafe.Pointer(&y)).padding = 99 + + want := eq + if got := testEq(x, y); got != want { + t.Errorf("%#v == %#v, got %s want %s", x, y, got, want) + } +} + +func TestCompareMemequal(t *testing.T) { + type S struct { + s1 string + d [100]byte + s2 string + } + var x, y S + + checkEq(t, x, y) + y.d[0] = 1 + checkNe(t, x, y) + y.d[0] = 0 + y.d[99] = 1 + checkNe(t, x, y) +} + +func TestComparePanic(t *testing.T) { + type S struct { + X0 string + X1 any + X2 string + X3 fooer + X4 string + } + testCompare(t, reflect.TypeOf(S{}), [][]any{ + {"a", "b", "cc"}, // length equal, as well as length unequal + {3, []byte{1}}, // comparable and incomparable + {"a", "b", "cc"}, // length equal, as well as length unequal + {fooComparable{x: 3}, fooIncomparable{b: nil}}, // comparable and incomparable + {"a", "b", "cc"}, // length equal, as well as length unequal + }) +} + +func TestCompareArray(t *testing.T) { + type S struct { + X0 string + X1 [100]string + X2 string + } + x := S{X0: "a", X2: "b"} + y := x + checkEq(t, x, y) + x.X0 = "c" + checkNe(t, x, y) + x.X0 = "a" + x.X2 = "c" + checkNe(t, x, y) + x.X2 = "b" + checkEq(t, x, y) + + for i := 0; i < 100; i++ { + x.X1[i] = "d" + checkNe(t, x, y) + y.X1[i] = "e" + checkNe(t, x, y) + x.X1[i] = "" + y.X1[i] = "" + checkEq(t, x, y) + } +} diff --git a/src/cmd/compile/internal/test/fixedbugs_test.go b/src/cmd/compile/internal/test/fixedbugs_test.go index 8ff7a60aae66dc..49d4fbb4157d8c 100644 --- a/src/cmd/compile/internal/test/fixedbugs_test.go +++ b/src/cmd/compile/internal/test/fixedbugs_test.go @@ -5,9 +5,12 @@ package test import ( + "bytes" + "internal/platform" "internal/testenv" "os" "path/filepath" + "runtime" "strings" "testing" ) @@ -24,7 +27,7 @@ func makeT() T { var g T -var sink interface{} +var sink any func TestIssue15854(t *testing.T) { for i := 0; i < 10000; i++ { @@ -84,3 +87,46 @@ func Mod32(x uint32) uint32 { return x % 3 // frontend rewrites it as HMUL with 2863311531, the LITERAL node has unknown Pos } ` + +// Test that building and running a program with -race -gcflags='all=-N -l' +// does not crash. This is a regression test for #77597 where generic functions +// from NoRaceFunc packages (like internal/runtime/atomic) were incorrectly +// getting racefuncenter/racefuncexit instrumentation when instantiated in +// other packages with optimizations disabled. +func TestIssue77597(t *testing.T) { + if !platform.RaceDetectorSupported(runtime.GOOS, runtime.GOARCH) { + t.Skipf("race detector not supported on %s/%s", runtime.GOOS, runtime.GOARCH) + } + testenv.MustHaveGoBuild(t) + testenv.MustHaveGoRun(t) + testenv.MustHaveCGO(t) + + dir := t.TempDir() + src := filepath.Join(dir, "main.go") + err := os.WriteFile(src, []byte(issue77597src), 0644) + if err != nil { + t.Fatalf("could not write file: %v", err) + } + + cmd := testenv.Command(t, testenv.GoToolPath(t), "run", "-race", "-gcflags=all=-N -l", src) + out, err := cmd.CombinedOutput() + if err != nil { + // For details, please refer to CL 160919. + unsupportedVMA := []byte("unsupported VMA range") + if bytes.Contains(out, unsupportedVMA) { + t.Skipf("skipped due to unsupported VMA on %s/%s", runtime.GOOS, runtime.GOARCH) + } else { + t.Fatalf("program failed: %v\n%s", err, out) + } + } +} + +var issue77597src = ` +package main + +import "fmt" + +func main() { + fmt.Println("OK") +} +` diff --git a/src/cmd/compile/internal/test/float_test.go b/src/cmd/compile/internal/test/float_test.go index 7a5e27870f97f0..00735e3cb11162 100644 --- a/src/cmd/compile/internal/test/float_test.go +++ b/src/cmd/compile/internal/test/float_test.go @@ -727,6 +727,65 @@ func TestFusedNaNChecks32(t *testing.T) { } } +// minNormal64 is the smallest float64 value that is not subnormal. +const minNormal64 = 2.2250738585072014e-308 + +//go:noinline +func isAbsLessThanMinNormal64(x float64) bool { + return math.Abs(x) < minNormal64 +} + +//go:noinline +func isLessThanMinNormal64(x float64) bool { + return x < minNormal64 +} + +//go:noinline +func isGreaterThanNegMinNormal64(x float64) bool { + return x > -minNormal64 +} + +//go:noinline +func isGreaterThanOrEqualToMinNormal64(x float64) bool { + return math.Abs(x) >= minNormal64 +} + +func TestSubnormalComparisons(t *testing.T) { + tests := []struct { + value float64 + isAbsLessThanMinNormal bool + isPositive bool + isNegative bool + isNaN bool + }{ + {value: math.Inf(1), isPositive: true}, + {value: math.MaxFloat64, isPositive: true}, + {value: math.Inf(-1), isNegative: true}, + {value: -math.MaxFloat64, isNegative: true}, + {value: math.NaN(), isNaN: true}, + {value: minNormal64, isPositive: true}, + {value: minNormal64 / 2, isAbsLessThanMinNormal: true, isPositive: true}, + {value: -minNormal64, isNegative: true}, + {value: -minNormal64 / 2, isAbsLessThanMinNormal: true, isNegative: true}, + {value: 0, isAbsLessThanMinNormal: true, isPositive: true}, + {value: math.Copysign(0, -1), isAbsLessThanMinNormal: true, isNegative: true}, + } + + check := func(name string, f func(x float64) bool, value float64, want bool) { + got := f(value) + if got != want { + t.Errorf("%v(%g): want %v, got %v", name, value, want, got) + } + } + + for _, test := range tests { + check("isAbsLessThanMinNormal64", isAbsLessThanMinNormal64, test.value, test.isAbsLessThanMinNormal) + check("isLessThanMinNormal64", isLessThanMinNormal64, test.value, test.isAbsLessThanMinNormal || test.isNegative) + check("isGreaterThanNegMinNormal64", isGreaterThanNegMinNormal64, test.value, test.isAbsLessThanMinNormal || test.isPositive) + check("isGreaterThanOrEqualToMinNormal64", isGreaterThanOrEqualToMinNormal64, test.value, !test.isAbsLessThanMinNormal && !test.isNaN) + } +} + var sinkFloat float64 func BenchmarkMul2(b *testing.B) { diff --git a/src/cmd/compile/internal/test/free_test.go b/src/cmd/compile/internal/test/free_test.go new file mode 100644 index 00000000000000..061cc9a6e4e3ac --- /dev/null +++ b/src/cmd/compile/internal/test/free_test.go @@ -0,0 +1,55 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package test + +import ( + "internal/asan" + "internal/goexperiment" + "internal/msan" + "internal/race" + "testing" +) + +func TestFreeAppendAllocations(t *testing.T) { + t.Run("slice-no-alias", func(t *testing.T) { + if !goexperiment.RuntimeFreegc { + t.Skip("skipping allocation test when runtime.freegc is disabled") + } + if race.Enabled || msan.Enabled || asan.Enabled { + // TODO(thepudds): we get 8 allocs for slice-no-alias instead of 1 with -race. This + // might be expected given some allocation optimizations are already disabled + // under race, but if not, we might need to update walk. + t.Skip("skipping allocation test under race detector and other sanitizers") + } + + allocs := testing.AllocsPerRun(100, func() { + var s []int64 + for i := range 100 { + s = append(s, int64(i)) + } + _ = s + }) + t.Logf("allocs: %v", allocs) + if allocs != 1 { + t.Errorf("allocs: %v, want 1", allocs) + } + }) + + t.Run("slice-aliased", func(t *testing.T) { + allocs := testing.AllocsPerRun(100, func() { + var s []int64 + var alias []int64 + for i := range 100 { + s = append(s, int64(i)) + alias = s + } + _ = alias + }) + t.Logf("allocs: %v", allocs) + if allocs < 2 { + t.Errorf("allocs: %v, want >= 2", allocs) + } + }) +} diff --git a/src/cmd/compile/internal/test/iface_test.go b/src/cmd/compile/internal/test/iface_test.go index db41eb8e55c740..cb7dc70c2ff893 100644 --- a/src/cmd/compile/internal/test/iface_test.go +++ b/src/cmd/compile/internal/test/iface_test.go @@ -13,7 +13,7 @@ var x int func TestEfaceConv1(t *testing.T) { a := 5 - i := interface{}(a) + i := any(a) a += 2 if got := i.(int); got != 5 { t.Errorf("wanted 5, got %d\n", got) @@ -23,7 +23,7 @@ func TestEfaceConv1(t *testing.T) { func TestEfaceConv2(t *testing.T) { a := 5 sink = &a - i := interface{}(a) + i := any(a) a += 2 if got := i.(int); got != 5 { t.Errorf("wanted 5, got %d\n", got) @@ -38,7 +38,7 @@ func TestEfaceConv3(t *testing.T) { } //go:noinline -func e2int3(i interface{}) int { +func e2int3(i any) int { x = 7 return i.(int) } @@ -51,7 +51,7 @@ func TestEfaceConv4(t *testing.T) { } //go:noinline -func e2int4(i interface{}, p *int) int { +func e2int4(i any, p *int) int { *p = 7 return i.(int) } @@ -69,7 +69,7 @@ func (i Int) foo() { func TestIfaceConv1(t *testing.T) { a := Int(5) - i := interface{}(a) + i := any(a) a += 2 if got := i.(Int); got != 5 { t.Errorf("wanted 5, got %d\n", int(got)) @@ -79,7 +79,7 @@ func TestIfaceConv1(t *testing.T) { func TestIfaceConv2(t *testing.T) { a := Int(5) sink = &a - i := interface{}(a) + i := any(a) a += 2 if got := i.(Int); got != 5 { t.Errorf("wanted 5, got %d\n", int(got)) @@ -121,7 +121,7 @@ func BenchmarkEfaceInteger(b *testing.B) { } //go:noinline -func i2int(i interface{}) int { +func i2int(i any) int { return i.(int) } diff --git a/src/cmd/compile/internal/test/inl_test.go b/src/cmd/compile/internal/test/inl_test.go index 3bea11dbb17b12..b0d78749d7ee61 100644 --- a/src/cmd/compile/internal/test/inl_test.go +++ b/src/cmd/compile/internal/test/inl_test.go @@ -51,7 +51,6 @@ func TestIntendedInlining(t *testing.T) { "noescape", "pcvalueCacheKey", "rand32", - "readUnaligned32", "readUnaligned64", "releasem", "roundupsize", @@ -113,11 +112,12 @@ func TestIntendedInlining(t *testing.T) { "internal/runtime/math": { "MulUintptr", }, + "internal/runtime/maps": { + "readUnaligned32", + "readUnaligned64", + }, "internal/runtime/sys": {}, "compress/flate": { - "byLiteral.Len", - "byLiteral.Less", - "byLiteral.Swap", "(*dictDecoder).tryWriteCopy", }, "encoding/base64": { @@ -233,6 +233,9 @@ func TestIntendedInlining(t *testing.T) { "testing": { "(*B).Loop", }, + "time": { + "Duration.String", + }, "path": { "Base", "scanChunk", @@ -240,6 +243,10 @@ func TestIntendedInlining(t *testing.T) { "path/filepath": { "scanChunk", }, + "internal/strconv": { + "prescale", + "uscale", + }, } if runtime.GOARCH != "386" && runtime.GOARCH != "loong64" && runtime.GOARCH != "mips64" && runtime.GOARCH != "mips64le" && runtime.GOARCH != "riscv64" { @@ -262,7 +269,7 @@ func TestIntendedInlining(t *testing.T) { } if bits.UintSize == 64 { // mix is only defined on 64-bit architectures - want["runtime"] = append(want["runtime"], "mix") + want["internal/runtime/maps"] = append(want["internal/runtime/maps"], "mix") // (*Bool).CompareAndSwap is just over budget on 32-bit systems (386, arm). want["sync/atomic"] = append(want["sync/atomic"], "(*Bool).CompareAndSwap") } @@ -303,11 +310,7 @@ func TestIntendedInlining(t *testing.T) { } // Functions that must actually be inlined; they must have actual callers. - must := map[string]bool{ - "compress/flate.byLiteral.Len": true, - "compress/flate.byLiteral.Less": true, - "compress/flate.byLiteral.Swap": true, - } + must := map[string]bool{} notInlinedReason := make(map[string]string) pkgs := make([]string, 0, len(want)) diff --git a/src/cmd/compile/internal/test/issue_81478_test.go b/src/cmd/compile/internal/test/issue_81478_test.go new file mode 100644 index 00000000000000..e3af6eb40bd5e0 --- /dev/null +++ b/src/cmd/compile/internal/test/issue_81478_test.go @@ -0,0 +1,98 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package test + +import ( + "internal/platform" + "internal/testenv" + "os" + "path/filepath" + "runtime" + "strings" + "testing" +) + +// Test that compiler-generated wrappers that end in a tail call still tell the +// race detector that the wrapper has returned. This is a regression test for +// #81478, where the missing racefuncexit call made every wrapper call leak an +// entry in the race detector's shadow stack, which in turn made later +// synchronization operations dramatically slower. +func TestIssue81478(t *testing.T) { + if !platform.RaceDetectorSupported(runtime.GOOS, runtime.GOARCH) { + t.Skipf("race detector not supported on %s/%s", runtime.GOOS, runtime.GOARCH) + } + testenv.MustHaveGoBuild(t) + + dir := t.TempDir() + src := filepath.Join(dir, "x.go") + if err := os.WriteFile(src, []byte(issue81478src), 0644); err != nil { + t.Fatalf("could not write file: %v", err) + } + + cmd := testenv.Command(t, testenv.GoToolPath(t), "tool", "compile", "-race", "-p=main", "-S", "-o", filepath.Join(dir, "x.o"), src) + out, err := cmd.CombinedOutput() + if err != nil { + t.Fatalf("compile failed: %v\n%s", err, out) + } + + // W.F tail calls through an interface, S.G tail calls a static function. + // Whether the tail call is actually emitted is architecture-dependent, but + // either way the enter/exit instrumentation must be balanced. + for _, wrapper := range []string{"main.(*W).F", "main.(*S).G"} { + body, ok := funcBody(string(out), wrapper) + if !ok { + t.Errorf("no assembly found for %s", wrapper) + continue + } + enter := strings.Count(body, "runtime.racefuncenter") + exit := strings.Count(body, "runtime.racefuncexit") + if enter == 0 { + t.Errorf("%s: not instrumented for the race detector\n%s", wrapper, body) + } else if enter != exit { + t.Errorf("%s: unbalanced race instrumentation: %d racefuncenter, %d racefuncexit\n%s", wrapper, enter, exit, body) + } + } +} + +// funcBody returns the part of the -S output that belongs to the symbol fn: +// its header line plus the indented instruction and relocation lines below it. +func funcBody(out, fn string) (string, bool) { + lines := strings.Split(out, "\n") + for i, line := range lines { + if !strings.HasPrefix(line, fn+" STEXT") { + continue + } + end := i + 1 + for end < len(lines) && strings.HasPrefix(lines[end], "\t") { + end++ + } + return strings.Join(lines[i:end], "\n"), true + } + return "", false +} + +var issue81478src = ` +package main + +type I interface{ F() } + +type T struct{ n int } + +func (t *T) F() { t.n++ } + +//go:noinline +func (t *T) G() { t.n++ } + +// W.F is a wrapper around an embedded interface method. +type W struct{ I } + +// S.G is a wrapper around an embedded pointer's method. +type S struct{ *T } + +var _ I = &W{} +var _ = (&S{}).G + +func main() {} +` diff --git a/src/cmd/compile/internal/test/memoverlap_test.go b/src/cmd/compile/internal/test/memoverlap_test.go new file mode 100644 index 00000000000000..c53288e6bb24ac --- /dev/null +++ b/src/cmd/compile/internal/test/memoverlap_test.go @@ -0,0 +1,41 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package test + +import "testing" + +const arrFooSize = 96 + +type arrFoo [arrFooSize]int + +//go:noinline +func badCopy(dst, src []int) { + p := (*[arrFooSize]int)(dst[:arrFooSize]) + q := (*[arrFooSize]int)(src[:arrFooSize]) + *p = arrFoo(*q) +} + +//go:noinline +func goodCopy(dst, src []int) { + p := (*[arrFooSize]int)(dst[:arrFooSize]) + q := (*[arrFooSize]int)(src[:arrFooSize]) + *p = *q +} + +func TestOverlapedMoveWithNoopIConv(t *testing.T) { + h1 := make([]int, arrFooSize+1) + h2 := make([]int, arrFooSize+1) + for i := range arrFooSize + 1 { + h1[i] = i + h2[i] = i + } + badCopy(h1[1:], h1[:arrFooSize]) + goodCopy(h2[1:], h2[:arrFooSize]) + for i := range arrFooSize + 1 { + if h1[i] != h2[i] { + t.Errorf("h1 and h2 differ at index %d, expect them to be the same", i) + } + } +} diff --git a/src/cmd/compile/internal/test/move_test.go b/src/cmd/compile/internal/test/move_test.go new file mode 100644 index 00000000000000..f361a86539142d --- /dev/null +++ b/src/cmd/compile/internal/test/move_test.go @@ -0,0 +1,55 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package test + +import "testing" + +var ( + n = [16]int{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16} + m = [16]int{2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32} +) + +func TestEqual(t *testing.T) { + if r := move2(n, m, 0); r != n { + t.Fatalf("%v != %v", r, n) + } + if r := move2(n, m, 1); r != m { + t.Fatalf("%v != %v", r, m) + } + if r := move2p(n, m, 0); r != n { + t.Fatalf("%v != %v", r, n) + } + if r := move2p(n, m, 1); r != m { + t.Fatalf("%v != %v", r, m) + } +} + +//go:noinline +func move2(a, b [16]int, c int) [16]int { + e := a + f := b + var d [16]int + if c%2 == 0 { + d = e + } else { + d = f + } + r := d + return r +} + +//go:noinline +func move2p(a, b [16]int, c int) [16]int { + e := a + f := b + var p *[16]int + if c%2 == 0 { + p = &e + } else { + p = &f + } + r := *p + return r +} diff --git a/src/cmd/compile/internal/test/moveload_test.go b/src/cmd/compile/internal/test/moveload_test.go new file mode 100644 index 00000000000000..d14c4b8f5804c5 --- /dev/null +++ b/src/cmd/compile/internal/test/moveload_test.go @@ -0,0 +1,62 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package test + +import "testing" + +// From issue #77720. +type moveLoadBenchHandle[T any] struct { + value *T +} + +func (h moveLoadBenchHandle[T]) Value() T { + return *h.value +} + +type moveLoadBenchBig struct { + typ int8 + index int64 + str string + pkgID string + dummyField [1024]byte +} + +type moveLoadBenchS struct { + h moveLoadBenchHandle[moveLoadBenchBig] +} + +var moveLoadBenchSink int8 + +func moveLoadBenchTypViaValue(s moveLoadBenchS) int8 { + return s.h.Value().typ +} + +func moveLoadBenchTypViaPtr(s moveLoadBenchS) int8 { + return (*s.h.value).typ +} + +func benchmarkMoveLoad(b *testing.B, f func(moveLoadBenchS) int8) { + backing := make([]moveLoadBenchBig, 1<<10) + ss := make([]moveLoadBenchS, len(backing)) + for i := range backing { + backing[i].typ = int8(i) + ss[i] = moveLoadBenchS{h: moveLoadBenchHandle[moveLoadBenchBig]{&backing[i]}} + } + + b.ResetTimer() + var x int8 + for i := 0; i < b.N; i++ { + x += f(ss[i&(len(ss)-1)]) + } + moveLoadBenchSink = x +} + +func BenchmarkMoveLoadTypViaValue(b *testing.B) { + benchmarkMoveLoad(b, moveLoadBenchTypViaValue) +} + +func BenchmarkMoveLoadTypViaPtr(b *testing.B) { + benchmarkMoveLoad(b, moveLoadBenchTypViaPtr) +} diff --git a/src/cmd/compile/internal/test/pgo_inl_test.go b/src/cmd/compile/internal/test/pgo_inl_test.go index 0859431b029edf..d9d133c8d97829 100644 --- a/src/cmd/compile/internal/test/pgo_inl_test.go +++ b/src/cmd/compile/internal/test/pgo_inl_test.go @@ -365,3 +365,53 @@ func TestPGOHash(t *testing.T) { t.Errorf("output contains unexpected source line, out:\n%s", out) } } + +// TestPGOZeroValues tests that a profile with all sample values scaled to zero +// is treated as empty, ensuring the build succeeds without error. +func TestPGOZeroValues(t *testing.T) { + wd, err := os.Getwd() + if err != nil { + t.Fatalf("error getting wd: %v", err) + } + srcDir := filepath.Join(wd, "testdata/pgo/inline") + + // Copy the module to a scratch location so we can add a go.mod. + dir := t.TempDir() + + originalPprofFile, err := os.Open(filepath.Join(srcDir, profFile)) + if err != nil { + t.Fatalf("error opening %v: %v", profFile, err) + } + defer originalPprofFile.Close() + + p, err := profile.Parse(originalPprofFile) + if err != nil { + t.Fatalf("error parsing %v: %v", profFile, err) + } + + // Zero out all samples to simulate a profile with all samples scaled away + for _, s := range p.Sample { + for i := range s.Value { + s.Value[i] = 0 + } + } + + emptyProf, err := os.Create(filepath.Join(dir, profFile)) + if err != nil { + t.Fatalf("error creating %v: %v", profFile, err) + } + defer emptyProf.Close() + + if err := p.Write(emptyProf); err != nil { + t.Fatalf("error writing %v: %v", profFile, err) + } + + for _, file := range []string{"inline_hot.go", "inline_hot_test.go"} { + if err := copyFile(filepath.Join(dir, file), filepath.Join(srcDir, file)); err != nil { + t.Fatalf("error copying %s: %v", file, err) + } + } + + gcflag := fmt.Sprintf("-pgoprofile=%s", profFile) + buildPGOInliningTest(t, dir, gcflag) +} diff --git a/src/cmd/compile/internal/test/reproduciblebuilds_test.go b/src/cmd/compile/internal/test/reproduciblebuilds_test.go index 466e0c3a38ae1b..b2ff4068a8a86a 100644 --- a/src/cmd/compile/internal/test/reproduciblebuilds_test.go +++ b/src/cmd/compile/internal/test/reproduciblebuilds_test.go @@ -26,7 +26,6 @@ func TestReproducibleBuilds(t *testing.T) { } t.Parallel() for _, test := range tests { - test := test t.Run(test, func(t *testing.T) { t.Parallel() var want []byte diff --git a/src/cmd/compile/internal/test/shift_test.go b/src/cmd/compile/internal/test/shift_test.go index 492379e188c01a..d540f25c73a217 100644 --- a/src/cmd/compile/internal/test/shift_test.go +++ b/src/cmd/compile/internal/test/shift_test.go @@ -916,7 +916,7 @@ func TestShiftGeneric(t *testing.T) { signed bool shiftWidth int left bool - f interface{} + f any }{ {64, true, 64, true, func(n int64, s uint64) int64 { return n << s }}, {64, true, 64, false, func(n int64, s uint64) int64 { return n >> s }}, diff --git a/src/cmd/compile/internal/test/ssa_test.go b/src/cmd/compile/internal/test/ssa_test.go index 7d213fcecac458..c0a8b6c1c0817c 100644 --- a/src/cmd/compile/internal/test/ssa_test.go +++ b/src/cmd/compile/internal/test/ssa_test.go @@ -95,7 +95,7 @@ func TestCode(t *testing.T) { t.Fatalf("can't read testdata/%s: %v", f.Name(), err) } fset := token.NewFileSet() - code, err := parser.ParseFile(fset, f.Name(), text, 0) + code, err := parser.ParseFile(fset, f.Name(), text, parser.SkipObjectResolution) if err != nil { t.Fatalf("can't parse testdata/%s: %v", f.Name(), err) } @@ -163,7 +163,6 @@ func TestCode(t *testing.T) { // Now we have a test binary. Run it with all the tests as subtests of this one. for _, test := range tests { - test := test if flag == ",softfloat" && !test.usesFloat { // No point in running the soft float version if the test doesn't use floats. continue diff --git a/src/cmd/compile/internal/test/switch_test.go b/src/cmd/compile/internal/test/switch_test.go index 1d12361cbb6954..0442cdc8fc5362 100644 --- a/src/cmd/compile/internal/test/switch_test.go +++ b/src/cmd/compile/internal/test/switch_test.go @@ -294,3 +294,135 @@ func (r rng) next(predictable bool) rng { func (r rng) value() uint64 { return uint64(r) } + +// Benchmarks for switch-to-lookup-table optimization. +// These use functions that return constants, which is the pattern +// the lookup table optimization targets. + +//go:noinline +func switchLookup8(x int) int { + switch x { + case 0: + return 1 + case 1: + return 2 + case 2: + return 3 + case 3: + return 5 + case 4: + return 8 + case 5: + return 13 + case 6: + return 21 + case 7: + return 34 + default: + return 0 + } +} + +//go:noinline +func switchLookup32(x int) int { + switch x { + case 0: + return 10 + case 1: + return 20 + case 2: + return 30 + case 3: + return 40 + case 4: + return 50 + case 5: + return 60 + case 6: + return 70 + case 7: + return 80 + case 8: + return 90 + case 9: + return 100 + case 10: + return 110 + case 11: + return 120 + case 12: + return 130 + case 13: + return 140 + case 14: + return 150 + case 15: + return 160 + case 16: + return 170 + case 17: + return 180 + case 18: + return 190 + case 19: + return 200 + case 20: + return 210 + case 21: + return 220 + case 22: + return 230 + case 23: + return 240 + case 24: + return 250 + case 25: + return 260 + case 26: + return 270 + case 27: + return 280 + case 28: + return 290 + case 29: + return 300 + case 30: + return 310 + case 31: + return 320 + default: + return 0 + } +} + +func BenchmarkSwitchLookup8Predictable(b *testing.B) { + benchmarkSwitchLookup8(b, true) +} +func BenchmarkSwitchLookup8Unpredictable(b *testing.B) { + benchmarkSwitchLookup8(b, false) +} +func benchmarkSwitchLookup8(b *testing.B, predictable bool) { + n := 0 + rng := newRNG() + for i := 0; i < b.N; i++ { + rng = rng.next(predictable) + n += switchLookup8(int(rng.value() & 7)) + } + sink = n +} + +func BenchmarkSwitchLookup32Predictable(b *testing.B) { + benchmarkSwitchLookup32(b, true) +} +func BenchmarkSwitchLookup32Unpredictable(b *testing.B) { + benchmarkSwitchLookup32(b, false) +} +func benchmarkSwitchLookup32(b *testing.B, predictable bool) { + n := 0 + rng := newRNG() + for i := 0; i < b.N; i++ { + rng = rng.next(predictable) + n += switchLookup32(int(rng.value() & 31)) + } + sink = n +} diff --git a/src/cmd/compile/internal/test/testdata/arith_test.go b/src/cmd/compile/internal/test/testdata/arith_test.go index cd7b5bc2c4a985..6f53618b59432d 100644 --- a/src/cmd/compile/internal/test/testdata/arith_test.go +++ b/src/cmd/compile/internal/test/testdata/arith_test.go @@ -223,7 +223,7 @@ func testArithConstShift(t *testing.T) { } } -// overflowConstShift_ssa verifies that constant folding for shift +// overflowConstShift64_ssa verifies that constant folding for shift // doesn't wrap (i.e. x << MAX_INT << 1 doesn't get folded to x << 0). // //go:noinline @@ -444,6 +444,19 @@ func testBitwiseRshU_ssa(a uint32, b, c uint32) uint32 { return a >> b >> c } +//go:noinline +func orLt_ssa(x int) bool { + y := x - x + return (x | 2) < y +} + +// test riscv64 SLTI rules +func testSetIfLessThan(t *testing.T) { + if want, got := true, orLt_ssa(-7); got != want { + t.Errorf("orLt_ssa(-7) = %t want %t", got, want) + } +} + //go:noinline func testShiftCX_ssa() int { v1 := uint8(3) @@ -977,6 +990,7 @@ func TestArithmetic(t *testing.T) { testRegallocCVSpill(t) testSubqToNegq(t) testBitwiseLogic(t) + testSetIfLessThan(t) testOcom(t) testLrot(t) testShiftCX(t) @@ -1390,11 +1404,17 @@ func div19_int64(n int64) bool { return n%19 == 0 } +var ( + // These have to be global to avoid getting constant-folded in the function body: + // as locals, prove can see that they are actually constants. + sixU, nineteenU uint64 = 6, 19 + sixS, nineteenS int64 = 6, 19 +) + // testDivisibility confirms that rewrite rules x%c ==0 for c constant are correct. func testDivisibility(t *testing.T) { // unsigned tests // test an even and an odd divisor - var sixU, nineteenU uint64 = 6, 19 // test all inputs for uint8, uint16 for i := uint64(0); i <= math.MaxUint16; i++ { if i <= math.MaxUint8 { @@ -1402,7 +1422,7 @@ func testDivisibility(t *testing.T) { t.Errorf("div6_uint8(%d) = %v want %v", i, got, want) } if want, got := uint8(i)%uint8(nineteenU) == 0, div19_uint8(uint8(i)); got != want { - t.Errorf("div6_uint19(%d) = %v want %v", i, got, want) + t.Errorf("div19_uint8(%d) = %v want %v", i, got, want) } } if want, got := uint16(i)%uint16(sixU) == 0, div6_uint16(uint16(i)); got != want { @@ -1450,7 +1470,6 @@ func testDivisibility(t *testing.T) { // signed tests // test an even and an odd divisor - var sixS, nineteenS int64 = 6, 19 // test all inputs for int8, int16 for i := int64(math.MinInt16); i <= math.MaxInt16; i++ { if math.MinInt8 <= i && i <= math.MaxInt8 { @@ -1458,7 +1477,7 @@ func testDivisibility(t *testing.T) { t.Errorf("div6_int8(%d) = %v want %v", i, got, want) } if want, got := int8(i)%int8(nineteenS) == 0, div19_int8(int8(i)); got != want { - t.Errorf("div6_int19(%d) = %v want %v", i, got, want) + t.Errorf("div19_int8(%d) = %v want %v", i, got, want) } } if want, got := int16(i)%int16(sixS) == 0, div6_int16(int16(i)); got != want { diff --git a/src/cmd/compile/internal/test/testdata/ctl_test.go b/src/cmd/compile/internal/test/testdata/ctl_test.go index 501f79eee1e2dd..608bdcf6b941fb 100644 --- a/src/cmd/compile/internal/test/testdata/ctl_test.go +++ b/src/cmd/compile/internal/test/testdata/ctl_test.go @@ -72,6 +72,22 @@ func switch_ssa(a int) int { return ret } +func switch_nonconstcase(n, c int) int { + switch n { + case 1: + return 1 + case 2: + return 2 + case c: + return 9 + case 3: + return 3 + case 4: + return 4 + } + return 0 +} + func fallthrough_ssa(a int) int { ret := 0 switch a { @@ -107,6 +123,9 @@ func testSwitch(t *testing.T) { t.Errorf("switch_ssa(i) = %d, wanted %d", got, i) } } + if got := switch_nonconstcase(3, 3); got != 9 { + t.Errorf("switch_nonconstcase(3, 3) = %d, wanted 9", got) + } } type junk struct { diff --git a/src/cmd/compile/internal/test/testdata/gen/conditionalCmpConstGen.go b/src/cmd/compile/internal/test/testdata/gen/conditionalCmpConstGen.go new file mode 100644 index 00000000000000..c3e3d7e81702a0 --- /dev/null +++ b/src/cmd/compile/internal/test/testdata/gen/conditionalCmpConstGen.go @@ -0,0 +1,231 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// This program generates tests to verify that conditional comparisons +// with constants are properly optimized by the compiler through constant folding. +// The generated test should be compiled with a known working version of Go. +// Run with `go run conditionalCmpConstGen.go` to generate a file called +// conditionalCmpConst_test.go in the grandparent directory. + +package main + +import ( + "bytes" + "fmt" + "go/format" + "log" + "os" + "strings" +) + +// IntegerConstraint defines a type constraint for all integer types +func writeIntegerConstraint(w *bytes.Buffer) { + fmt.Fprintf(w, "type IntegerConstraint interface {\n") + fmt.Fprintf(w, "\tint | uint | int8 | uint8 | int16 | ") + fmt.Fprintf(w, "uint16 | int32 | uint32 | int64 | uint64\n") + fmt.Fprintf(w, "}\n\n") +} + +// TestCase describes a parameterized test case with comparison and logical operations +func writeTestCaseStruct(w *bytes.Buffer) { + fmt.Fprintf(w, "type TestCase[T IntegerConstraint] struct {\n") + fmt.Fprintf(w, "\tcmp1, cmp2 func(a, b T) bool\n") + fmt.Fprintf(w, "\tcombine func(x, y bool) bool\n") + fmt.Fprintf(w, "\ttargetFunc func(a, b, c, d T) bool\n") + fmt.Fprintf(w, "\tcmp1Expr, cmp2Expr, logicalExpr string // String representations for debugging\n") + fmt.Fprintf(w, "}\n\n") +} + +// BoundaryValues contains base value and its variations for edge case testing +func writeBoundaryValuesStruct(w *bytes.Buffer) { + fmt.Fprintf(w, "type BoundaryValues[T IntegerConstraint] struct {\n") + fmt.Fprintf(w, "\tbase T\n") + fmt.Fprintf(w, "\tvariants [3]T\n") + fmt.Fprintf(w, "}\n\n") +} + +// writeTypeDefinitions generates all necessary type declarations +func writeTypeDefinitions(w *bytes.Buffer) { + writeIntegerConstraint(w) + writeTestCaseStruct(w) + writeBoundaryValuesStruct(w) +} + +// comparisonOperators contains format strings for comparison operators +var comparisonOperators = []string{ + "%s == %s", "%s <= %s", "%s < %s", + "%s != %s", "%s >= %s", "%s > %s", +} + +// logicalOperators contains format strings for logical combination of boolean expressions +var logicalOperators = []string{ + "(%s) && (%s)", "(%s) && !(%s)", "!(%s) && (%s)", "!(%s) && !(%s)", + "(%s) || (%s)", "(%s) || !(%s)", "!(%s) || (%s)", "!(%s) || !(%s)", +} + +// writeComparator generates a comparator function based on the comparison operator +func writeComparator(w *bytes.Buffer, fieldName, operatorFormat string) { + expression := fmt.Sprintf(operatorFormat, "a", "b") + fmt.Fprintf(w, "\t\t\t%s: func(a, b T) bool { return %s },\n", fieldName, expression) +} + +// writeLogicalCombiner generates a function to combine two boolean values +func writeLogicalCombiner(w *bytes.Buffer, logicalOperator string) { + expression := fmt.Sprintf(logicalOperator, "x", "y") + fmt.Fprintf(w, "\t\t\tcombine: func(x, y bool) bool { return %s },\n", expression) +} + +// writeTargetFunction generates the target function with conditional expression +func writeTargetFunction(w *bytes.Buffer, cmp1, cmp2, logicalOp string) { + leftExpr := fmt.Sprintf(cmp1, "a", "b") + rightExpr := fmt.Sprintf(cmp2, "c", "d") + condition := fmt.Sprintf(logicalOp, leftExpr, rightExpr) + + fmt.Fprintf(w, "\t\t\ttargetFunc: func(a, b, c, d T) bool {\n") + fmt.Fprintf(w, "\t\t\t\tif %s {\n", condition) + fmt.Fprintf(w, "\t\t\t\t\treturn true\n") + fmt.Fprintf(w, "\t\t\t\t}\n") + fmt.Fprintf(w, "\t\t\t\treturn false\n") + fmt.Fprintf(w, "\t\t\t},\n") +} + +// writeTestCase creates a single test case with given comparison and logical operators +func writeTestCase(w *bytes.Buffer, cmp1, cmp2, logicalOp string) { + fmt.Fprintf(w, "\t\t{\n") + writeComparator(w, "cmp1", cmp1) + writeComparator(w, "cmp2", cmp2) + writeLogicalCombiner(w, logicalOp) + writeTargetFunction(w, cmp1, cmp2, logicalOp) + + // Store string representations for debugging + cmp1Expr := fmt.Sprintf(cmp1, "a", "b") + cmp2Expr := fmt.Sprintf(cmp2, "c", "d") + logicalExpr := fmt.Sprintf(logicalOp, cmp1Expr, cmp2Expr) + + fmt.Fprintf(w, "\t\t\tcmp1Expr: %q,\n", cmp1Expr) + fmt.Fprintf(w, "\t\t\tcmp2Expr: %q,\n", cmp2Expr) + fmt.Fprintf(w, "\t\t\tlogicalExpr: %q,\n", logicalExpr) + + fmt.Fprintf(w, "\t\t},\n") +} + +// generateTestCases creates a slice of all possible test cases +func generateTestCases(w *bytes.Buffer) { + fmt.Fprintf(w, "func generateTestCases[T IntegerConstraint]() []TestCase[T] {\n") + fmt.Fprintf(w, "\treturn []TestCase[T]{\n") + + for _, cmp1 := range comparisonOperators { + for _, cmp2 := range comparisonOperators { + for _, logicalOp := range logicalOperators { + writeTestCase(w, cmp1, cmp2, logicalOp) + } + } + } + + fmt.Fprintf(w, "\t}\n") + fmt.Fprintf(w, "}\n\n") +} + +// TypeConfig defines a type and its test base value +type TypeConfig struct { + typeName, baseValue string +} + +// typeConfigs contains all integer types to test with their base values +var typeConfigs = []TypeConfig{ + {typeName: "int8", baseValue: "1 << 6"}, + {typeName: "uint8", baseValue: "1 << 6"}, + {typeName: "int16", baseValue: "1 << 14"}, + {typeName: "uint16", baseValue: "1 << 14"}, + {typeName: "int32", baseValue: "1 << 30"}, + {typeName: "uint32", baseValue: "1 << 30"}, + {typeName: "int", baseValue: "1 << 30"}, + {typeName: "uint", baseValue: "1 << 30"}, + {typeName: "int64", baseValue: "1 << 62"}, + {typeName: "uint64", baseValue: "1 << 62"}, +} + +// writeTypeSpecificTest generates test for a specific integer type +func writeTypeSpecificTest(w *bytes.Buffer, typeName, baseValue string) { + typeTitle := strings.Title(typeName) + + fmt.Fprintf(w, "func Test%sConditionalCmpConst(t *testing.T) {\n", typeTitle) + + fmt.Fprintf(w, "\ttestCases := generateTestCases[%s]()\n", typeName) + fmt.Fprintf(w, "\tbase := %s(%s)\n", typeName, baseValue) + fmt.Fprintf(w, "\tvalues := [3]%s{base - 1, base, base + 1}\n\n", typeName) + + fmt.Fprintf(w, "\tfor _, tc := range testCases {\n") + fmt.Fprintf(w, "\t\ta, c := base, base\n") + fmt.Fprintf(w, "\t\tfor _, b := range values {\n") + fmt.Fprintf(w, "\t\t\tfor _, d := range values {\n") + fmt.Fprintf(w, "\t\t\t\texpected := tc.combine(tc.cmp1(a, b), tc.cmp2(c, d))\n") + fmt.Fprintf(w, "\t\t\t\tactual := tc.targetFunc(a, b, c, d)\n") + fmt.Fprintf(w, "\t\t\t\tif actual != expected {\n") + fmt.Fprintf(w, "\t\t\t\t\tt.Errorf(\"conditional comparison failed:\\n\"+\n") + fmt.Fprintf(w, "\t\t\t\t\t\t\" type: %%T\\n\"+\n") + fmt.Fprintf(w, "\t\t\t\t\t\t\" condition: %%s\\n\"+\n") + fmt.Fprintf(w, "\t\t\t\t\t\t\" values: a=%%v, b=%%v, c=%%v, d=%%v\\n\"+\n") + fmt.Fprintf(w, "\t\t\t\t\t\t\" cmp1(a,b)=%%v (%%s)\\n\"+\n") + fmt.Fprintf(w, "\t\t\t\t\t\t\" cmp2(c,d)=%%v (%%s)\\n\"+\n") + fmt.Fprintf(w, "\t\t\t\t\t\t\" expected: combine(%%v, %%v)=%%v\\n\"+\n") + fmt.Fprintf(w, "\t\t\t\t\t\t\" actual: %%v\\n\"+\n") + fmt.Fprintf(w, "\t\t\t\t\t\t\" logical expression: %%s\",\n") + fmt.Fprintf(w, "\t\t\t\t\t\ta,\n") + fmt.Fprintf(w, "\t\t\t\t\t\ttc.logicalExpr,\n") + fmt.Fprintf(w, "\t\t\t\t\t\ta, b, c, d,\n") + fmt.Fprintf(w, "\t\t\t\t\t\ttc.cmp1(a, b), tc.cmp1Expr,\n") + fmt.Fprintf(w, "\t\t\t\t\t\ttc.cmp2(c, d), tc.cmp2Expr,\n") + fmt.Fprintf(w, "\t\t\t\t\t\ttc.cmp1(a, b), tc.cmp2(c, d), expected,\n") + fmt.Fprintf(w, "\t\t\t\t\t\tactual,\n") + fmt.Fprintf(w, "\t\t\t\t\t\ttc.logicalExpr)\n") + fmt.Fprintf(w, "\t\t\t\t}\n") + fmt.Fprintf(w, "\t\t\t}\n") + fmt.Fprintf(w, "\t\t}\n") + fmt.Fprintf(w, "\t}\n") + + fmt.Fprintf(w, "}\n\n") +} + +// writeAllTests generates tests for all supported integer types +func writeAllTests(w *bytes.Buffer) { + for _, config := range typeConfigs { + writeTypeSpecificTest(w, config.typeName, config.baseValue) + } +} + +func main() { + buffer := new(bytes.Buffer) + + // Header for generated file + fmt.Fprintf(buffer, "// Code generated by conditionalCmpConstGen.go; DO NOT EDIT.\n\n") + fmt.Fprintf(buffer, "package test\n\n") + fmt.Fprintf(buffer, "import \"testing\"\n\n") + + // Generate type definitions + writeTypeDefinitions(buffer) + + // Generate test cases + generateTestCases(buffer) + + // Generate specific tests for each integer type + writeAllTests(buffer) + + // Format generated source code + rawSource := buffer.Bytes() + formattedSource, err := format.Source(rawSource) + if err != nil { + // Output raw source for debugging if formatting fails + fmt.Printf("%s\n", rawSource) + log.Fatal("error formatting generated code: ", err) + } + + // Write to output file + outputPath := "../../conditionalCmpConst_test.go" + if err := os.WriteFile(outputPath, formattedSource, 0666); err != nil { + log.Fatal("failed to write output file: ", err) + } + + log.Printf("Tests successfully generated to %s", outputPath) +} diff --git a/src/cmd/compile/internal/test/value_test.go b/src/cmd/compile/internal/test/value_test.go new file mode 100644 index 00000000000000..bb98f4f22b31b0 --- /dev/null +++ b/src/cmd/compile/internal/test/value_test.go @@ -0,0 +1,41 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package test + +import ( + "cmd/compile/internal/ssa" + "cmd/compile/internal/types" + "internal/buildcfg" + "testing" +) + +// This file contains tests for ssa values, types and their utility functions. + +func TestCanSSA(t *testing.T) { + i64 := types.Types[types.TINT64] + v128 := types.TypeVec128 + s1 := mkstruct(i64, mkstruct(i64, i64, i64, i64)) + if ssa.CanSSA(s1) { + // Test size check for struct. + t.Errorf("CanSSA(%v) returned true, expected false", s1) + } + a1 := types.NewArray(s1, 1) + if ssa.CanSSA(a1) { + // Test size check for array. + t.Errorf("CanSSA(%v) returned true, expected false", a1) + } + if buildcfg.Experiment.SIMD { + s2 := mkstruct(v128, v128, v128, v128) + if !ssa.CanSSA(s2) { + // Test size check for SIMD struct special case. + t.Errorf("CanSSA(%v) returned false, expected true", s2) + } + a2 := types.NewArray(s2, 1) + if !ssa.CanSSA(a2) { + // Test size check for SIMD array special case. + t.Errorf("CanSSA(%v) returned false, expected true", a2) + } + } +} diff --git a/src/cmd/compile/internal/typecheck/_builtin/runtime.go b/src/cmd/compile/internal/typecheck/_builtin/runtime.go index 296bfdc281d4d5..4da2b4cf503f9e 100644 --- a/src/cmd/compile/internal/typecheck/_builtin/runtime.go +++ b/src/cmd/compile/internal/typecheck/_builtin/runtime.go @@ -49,12 +49,15 @@ func goPanicSlice3CU(x uint, y int) func goPanicSliceConvert(x int, y int) func printbool(bool) -func printfloat(float64) +func printfloat64(float64) +func printfloat32(float32) func printint(int64) func printhex(uint64) func printuint(uint64) -func printcomplex(complex128) +func printcomplex128(complex128) +func printcomplex64(complex64) func printstring(string) +func printquoted(string) func printpointer(any) func printuintptr(uintptr) func printiface(any) @@ -193,6 +196,9 @@ func makeslice(typ *byte, len int, cap int) unsafe.Pointer func makeslice64(typ *byte, len int64, cap int64) unsafe.Pointer func makeslicecopy(typ *byte, tolen int, fromlen int, from unsafe.Pointer) unsafe.Pointer func growslice(oldPtr *any, newLen, oldCap, num int, et *byte) (ary []any) +func growsliceBuf(oldPtr *any, newLen, oldCap, num int, et *byte, buf *any, bufLen int) (ary []any) +func growsliceBufNoAlias(oldPtr *any, newLen, oldCap, num int, et *byte, buf *any, bufLen int) (ary []any) +func growsliceNoAlias(oldPtr *any, newLen, oldCap, num int, et *byte) (ary []any) func unsafeslicecheckptr(typ *byte, ptr unsafe.Pointer, len int64) func panicunsafeslicelen() func panicunsafeslicenilptr() @@ -200,17 +206,22 @@ func unsafestringcheckptr(ptr unsafe.Pointer, len int64) func panicunsafestringlen() func panicunsafestringnilptr() +func moveSlice(typ *byte, old *byte, len, cap int) (*byte, int, int) +func moveSliceNoScan(elemSize uintptr, old *byte, len, cap int) (*byte, int, int) +func moveSliceNoCap(typ *byte, old *byte, len int) (*byte, int, int) +func moveSliceNoCapNoScan(elemSize uintptr, old *byte, len int) (*byte, int, int) + func memmove(to *any, frm *any, length uintptr) func memclrNoHeapPointers(ptr unsafe.Pointer, n uintptr) func memclrHasPointers(ptr unsafe.Pointer, n uintptr) -func memequal(x, y *any, size uintptr) bool -func memequal0(x, y *any) bool -func memequal8(x, y *any) bool -func memequal16(x, y *any) bool -func memequal32(x, y *any) bool -func memequal64(x, y *any) bool -func memequal128(x, y *any) bool +func memequal(x, y unsafe.Pointer, size uintptr) bool +func memequal0(x, y unsafe.Pointer) bool +func memequal8(x, y unsafe.Pointer) bool +func memequal16(x, y unsafe.Pointer) bool +func memequal32(x, y unsafe.Pointer) bool +func memequal64(x, y unsafe.Pointer) bool +func memequal128(x, y unsafe.Pointer) bool func f32equal(p, q unsafe.Pointer) bool func f64equal(p, q unsafe.Pointer) bool func c64equal(p, q unsafe.Pointer) bool @@ -219,20 +230,20 @@ func strequal(p, q unsafe.Pointer) bool func interequal(p, q unsafe.Pointer) bool func nilinterequal(p, q unsafe.Pointer) bool -func memhash(x *any, h uintptr, size uintptr) uintptr +func memhash(x unsafe.Pointer, h uintptr, size uintptr) uintptr func memhash0(p unsafe.Pointer, h uintptr) uintptr func memhash8(p unsafe.Pointer, h uintptr) uintptr func memhash16(p unsafe.Pointer, h uintptr) uintptr func memhash32(p unsafe.Pointer, h uintptr) uintptr func memhash64(p unsafe.Pointer, h uintptr) uintptr func memhash128(p unsafe.Pointer, h uintptr) uintptr -func f32hash(p *any, h uintptr) uintptr -func f64hash(p *any, h uintptr) uintptr -func c64hash(p *any, h uintptr) uintptr -func c128hash(p *any, h uintptr) uintptr -func strhash(a *any, h uintptr) uintptr -func interhash(p *any, h uintptr) uintptr -func nilinterhash(p *any, h uintptr) uintptr +func f32hash(p unsafe.Pointer, h uintptr) uintptr +func f64hash(p unsafe.Pointer, h uintptr) uintptr +func c64hash(p unsafe.Pointer, h uintptr) uintptr +func c128hash(p unsafe.Pointer, h uintptr) uintptr +func strhash(a unsafe.Pointer, h uintptr) uintptr +func interhash(p unsafe.Pointer, h uintptr) uintptr +func nilinterhash(p unsafe.Pointer, h uintptr) uintptr // only used on 32-bit func int64div(int64, int64) int64 @@ -284,14 +295,19 @@ func libfuzzerHookEqualFold(string, string, uint) func addCovMeta(p unsafe.Pointer, len uint32, hash [16]byte, pkpath string, pkgId int, cmode uint8, cgran uint8) uint32 // architecture variants +var x86HasAVX bool +var x86HasFMA bool var x86HasPOPCNT bool var x86HasSSE41 bool -var x86HasFMA bool var armHasVFPv4 bool var arm64HasATOMICS bool var loong64HasLAMCAS bool var loong64HasLAM_BH bool +var loong64HasDBAR_HINTS bool var loong64HasLSX bool var riscv64HasZbb bool func asanregisterglobals(unsafe.Pointer, uintptr) + +// used by testing.B.Loop +func KeepAlive(interface{}) diff --git a/src/cmd/compile/internal/typecheck/builtin.go b/src/cmd/compile/internal/typecheck/builtin.go index 535f0fb7e88851..2e469aef60eda1 100644 --- a/src/cmd/compile/internal/typecheck/builtin.go +++ b/src/cmd/compile/internal/typecheck/builtin.go @@ -56,196 +56,209 @@ var runtimeDecls = [...]struct { {"goPanicSlice3CU", funcTag, 16}, {"goPanicSliceConvert", funcTag, 14}, {"printbool", funcTag, 17}, - {"printfloat", funcTag, 19}, - {"printint", funcTag, 21}, - {"printhex", funcTag, 23}, - {"printuint", funcTag, 23}, - {"printcomplex", funcTag, 25}, - {"printstring", funcTag, 27}, - {"printpointer", funcTag, 28}, - {"printuintptr", funcTag, 29}, - {"printiface", funcTag, 28}, - {"printeface", funcTag, 28}, - {"printslice", funcTag, 28}, + {"printfloat64", funcTag, 19}, + {"printfloat32", funcTag, 21}, + {"printint", funcTag, 23}, + {"printhex", funcTag, 25}, + {"printuint", funcTag, 25}, + {"printcomplex128", funcTag, 27}, + {"printcomplex64", funcTag, 29}, + {"printstring", funcTag, 31}, + {"printquoted", funcTag, 31}, + {"printpointer", funcTag, 32}, + {"printuintptr", funcTag, 33}, + {"printiface", funcTag, 32}, + {"printeface", funcTag, 32}, + {"printslice", funcTag, 32}, {"printnl", funcTag, 9}, {"printsp", funcTag, 9}, {"printlock", funcTag, 9}, {"printunlock", funcTag, 9}, - {"concatstring2", funcTag, 32}, - {"concatstring3", funcTag, 33}, - {"concatstring4", funcTag, 34}, - {"concatstring5", funcTag, 35}, - {"concatstrings", funcTag, 37}, - {"concatbyte2", funcTag, 39}, - {"concatbyte3", funcTag, 40}, - {"concatbyte4", funcTag, 41}, - {"concatbyte5", funcTag, 42}, - {"concatbytes", funcTag, 43}, - {"cmpstring", funcTag, 44}, - {"intstring", funcTag, 47}, - {"slicebytetostring", funcTag, 48}, - {"slicebytetostringtmp", funcTag, 49}, - {"slicerunetostring", funcTag, 52}, - {"stringtoslicebyte", funcTag, 53}, - {"stringtoslicerune", funcTag, 56}, - {"slicecopy", funcTag, 57}, - {"decoderune", funcTag, 58}, - {"countrunes", funcTag, 59}, - {"convT", funcTag, 60}, - {"convTnoptr", funcTag, 60}, - {"convT16", funcTag, 62}, - {"convT32", funcTag, 64}, - {"convT64", funcTag, 65}, - {"convTstring", funcTag, 66}, - {"convTslice", funcTag, 69}, - {"assertE2I", funcTag, 70}, - {"assertE2I2", funcTag, 70}, - {"panicdottypeE", funcTag, 71}, - {"panicdottypeI", funcTag, 71}, - {"panicnildottype", funcTag, 72}, - {"typeAssert", funcTag, 70}, - {"interfaceSwitch", funcTag, 73}, - {"ifaceeq", funcTag, 75}, - {"efaceeq", funcTag, 75}, - {"panicrangestate", funcTag, 76}, + {"concatstring2", funcTag, 36}, + {"concatstring3", funcTag, 37}, + {"concatstring4", funcTag, 38}, + {"concatstring5", funcTag, 39}, + {"concatstrings", funcTag, 41}, + {"concatbyte2", funcTag, 43}, + {"concatbyte3", funcTag, 44}, + {"concatbyte4", funcTag, 45}, + {"concatbyte5", funcTag, 46}, + {"concatbytes", funcTag, 47}, + {"cmpstring", funcTag, 48}, + {"intstring", funcTag, 51}, + {"slicebytetostring", funcTag, 52}, + {"slicebytetostringtmp", funcTag, 53}, + {"slicerunetostring", funcTag, 56}, + {"stringtoslicebyte", funcTag, 57}, + {"stringtoslicerune", funcTag, 60}, + {"slicecopy", funcTag, 61}, + {"decoderune", funcTag, 62}, + {"countrunes", funcTag, 63}, + {"convT", funcTag, 64}, + {"convTnoptr", funcTag, 64}, + {"convT16", funcTag, 66}, + {"convT32", funcTag, 68}, + {"convT64", funcTag, 69}, + {"convTstring", funcTag, 70}, + {"convTslice", funcTag, 73}, + {"assertE2I", funcTag, 74}, + {"assertE2I2", funcTag, 74}, + {"panicdottypeE", funcTag, 75}, + {"panicdottypeI", funcTag, 75}, + {"panicnildottype", funcTag, 76}, + {"typeAssert", funcTag, 74}, + {"interfaceSwitch", funcTag, 77}, + {"ifaceeq", funcTag, 79}, + {"efaceeq", funcTag, 79}, + {"panicrangestate", funcTag, 80}, {"deferrangefunc", funcTag, 12}, - {"rand", funcTag, 77}, - {"rand32", funcTag, 78}, - {"makemap64", funcTag, 80}, - {"makemap", funcTag, 81}, - {"makemap_small", funcTag, 82}, - {"mapaccess1", funcTag, 83}, - {"mapaccess1_fast32", funcTag, 84}, - {"mapaccess1_fast64", funcTag, 85}, - {"mapaccess1_faststr", funcTag, 86}, - {"mapaccess1_fat", funcTag, 87}, - {"mapaccess2", funcTag, 88}, - {"mapaccess2_fast32", funcTag, 89}, - {"mapaccess2_fast64", funcTag, 90}, - {"mapaccess2_faststr", funcTag, 91}, - {"mapaccess2_fat", funcTag, 92}, - {"mapassign", funcTag, 83}, - {"mapassign_fast32", funcTag, 84}, - {"mapassign_fast32ptr", funcTag, 93}, - {"mapassign_fast64", funcTag, 85}, - {"mapassign_fast64ptr", funcTag, 93}, - {"mapassign_faststr", funcTag, 86}, - {"mapIterStart", funcTag, 94}, - {"mapdelete", funcTag, 94}, - {"mapdelete_fast32", funcTag, 95}, - {"mapdelete_fast64", funcTag, 96}, - {"mapdelete_faststr", funcTag, 97}, - {"mapIterNext", funcTag, 98}, - {"mapclear", funcTag, 99}, - {"makechan64", funcTag, 101}, - {"makechan", funcTag, 102}, - {"chanrecv1", funcTag, 104}, - {"chanrecv2", funcTag, 105}, - {"chansend1", funcTag, 107}, - {"closechan", funcTag, 108}, - {"chanlen", funcTag, 109}, - {"chancap", funcTag, 109}, - {"writeBarrier", varTag, 111}, - {"typedmemmove", funcTag, 112}, - {"typedmemclr", funcTag, 113}, - {"typedslicecopy", funcTag, 114}, - {"selectnbsend", funcTag, 115}, - {"selectnbrecv", funcTag, 116}, - {"selectsetpc", funcTag, 117}, - {"selectgo", funcTag, 118}, + {"rand", funcTag, 81}, + {"rand32", funcTag, 82}, + {"makemap64", funcTag, 84}, + {"makemap", funcTag, 85}, + {"makemap_small", funcTag, 86}, + {"mapaccess1", funcTag, 87}, + {"mapaccess1_fast32", funcTag, 88}, + {"mapaccess1_fast64", funcTag, 89}, + {"mapaccess1_faststr", funcTag, 90}, + {"mapaccess1_fat", funcTag, 91}, + {"mapaccess2", funcTag, 92}, + {"mapaccess2_fast32", funcTag, 93}, + {"mapaccess2_fast64", funcTag, 94}, + {"mapaccess2_faststr", funcTag, 95}, + {"mapaccess2_fat", funcTag, 96}, + {"mapassign", funcTag, 87}, + {"mapassign_fast32", funcTag, 88}, + {"mapassign_fast32ptr", funcTag, 97}, + {"mapassign_fast64", funcTag, 89}, + {"mapassign_fast64ptr", funcTag, 97}, + {"mapassign_faststr", funcTag, 90}, + {"mapIterStart", funcTag, 98}, + {"mapdelete", funcTag, 98}, + {"mapdelete_fast32", funcTag, 99}, + {"mapdelete_fast64", funcTag, 100}, + {"mapdelete_faststr", funcTag, 101}, + {"mapIterNext", funcTag, 102}, + {"mapclear", funcTag, 103}, + {"makechan64", funcTag, 105}, + {"makechan", funcTag, 106}, + {"chanrecv1", funcTag, 108}, + {"chanrecv2", funcTag, 109}, + {"chansend1", funcTag, 111}, + {"closechan", funcTag, 112}, + {"chanlen", funcTag, 113}, + {"chancap", funcTag, 113}, + {"writeBarrier", varTag, 115}, + {"typedmemmove", funcTag, 116}, + {"typedmemclr", funcTag, 117}, + {"typedslicecopy", funcTag, 118}, + {"selectnbsend", funcTag, 119}, + {"selectnbrecv", funcTag, 120}, + {"selectsetpc", funcTag, 121}, + {"selectgo", funcTag, 122}, {"block", funcTag, 9}, - {"makeslice", funcTag, 119}, - {"makeslice64", funcTag, 120}, - {"makeslicecopy", funcTag, 121}, - {"growslice", funcTag, 123}, - {"unsafeslicecheckptr", funcTag, 124}, + {"makeslice", funcTag, 123}, + {"makeslice64", funcTag, 124}, + {"makeslicecopy", funcTag, 125}, + {"growslice", funcTag, 127}, + {"growsliceBuf", funcTag, 128}, + {"growsliceBufNoAlias", funcTag, 128}, + {"growsliceNoAlias", funcTag, 127}, + {"unsafeslicecheckptr", funcTag, 129}, {"panicunsafeslicelen", funcTag, 9}, {"panicunsafeslicenilptr", funcTag, 9}, - {"unsafestringcheckptr", funcTag, 125}, + {"unsafestringcheckptr", funcTag, 130}, {"panicunsafestringlen", funcTag, 9}, {"panicunsafestringnilptr", funcTag, 9}, - {"memmove", funcTag, 126}, - {"memclrNoHeapPointers", funcTag, 127}, - {"memclrHasPointers", funcTag, 127}, - {"memequal", funcTag, 128}, - {"memequal0", funcTag, 129}, - {"memequal8", funcTag, 129}, - {"memequal16", funcTag, 129}, - {"memequal32", funcTag, 129}, - {"memequal64", funcTag, 129}, - {"memequal128", funcTag, 129}, - {"f32equal", funcTag, 130}, - {"f64equal", funcTag, 130}, - {"c64equal", funcTag, 130}, - {"c128equal", funcTag, 130}, - {"strequal", funcTag, 130}, - {"interequal", funcTag, 130}, - {"nilinterequal", funcTag, 130}, - {"memhash", funcTag, 131}, - {"memhash0", funcTag, 132}, - {"memhash8", funcTag, 132}, - {"memhash16", funcTag, 132}, - {"memhash32", funcTag, 132}, - {"memhash64", funcTag, 132}, - {"memhash128", funcTag, 132}, - {"f32hash", funcTag, 133}, - {"f64hash", funcTag, 133}, - {"c64hash", funcTag, 133}, - {"c128hash", funcTag, 133}, - {"strhash", funcTag, 133}, - {"interhash", funcTag, 133}, - {"nilinterhash", funcTag, 133}, - {"int64div", funcTag, 134}, - {"uint64div", funcTag, 135}, - {"int64mod", funcTag, 134}, - {"uint64mod", funcTag, 135}, - {"float64toint64", funcTag, 136}, - {"float64touint64", funcTag, 137}, - {"float64touint32", funcTag, 138}, - {"int64tofloat64", funcTag, 139}, - {"int64tofloat32", funcTag, 141}, - {"uint64tofloat64", funcTag, 142}, - {"uint64tofloat32", funcTag, 143}, - {"uint32tofloat64", funcTag, 144}, - {"complex128div", funcTag, 145}, - {"racefuncenter", funcTag, 29}, + {"moveSlice", funcTag, 131}, + {"moveSliceNoScan", funcTag, 132}, + {"moveSliceNoCap", funcTag, 133}, + {"moveSliceNoCapNoScan", funcTag, 134}, + {"memmove", funcTag, 135}, + {"memclrNoHeapPointers", funcTag, 136}, + {"memclrHasPointers", funcTag, 136}, + {"memequal", funcTag, 137}, + {"memequal0", funcTag, 138}, + {"memequal8", funcTag, 138}, + {"memequal16", funcTag, 138}, + {"memequal32", funcTag, 138}, + {"memequal64", funcTag, 138}, + {"memequal128", funcTag, 138}, + {"f32equal", funcTag, 138}, + {"f64equal", funcTag, 138}, + {"c64equal", funcTag, 138}, + {"c128equal", funcTag, 138}, + {"strequal", funcTag, 138}, + {"interequal", funcTag, 138}, + {"nilinterequal", funcTag, 138}, + {"memhash", funcTag, 139}, + {"memhash0", funcTag, 140}, + {"memhash8", funcTag, 140}, + {"memhash16", funcTag, 140}, + {"memhash32", funcTag, 140}, + {"memhash64", funcTag, 140}, + {"memhash128", funcTag, 140}, + {"f32hash", funcTag, 140}, + {"f64hash", funcTag, 140}, + {"c64hash", funcTag, 140}, + {"c128hash", funcTag, 140}, + {"strhash", funcTag, 140}, + {"interhash", funcTag, 140}, + {"nilinterhash", funcTag, 140}, + {"int64div", funcTag, 141}, + {"uint64div", funcTag, 142}, + {"int64mod", funcTag, 141}, + {"uint64mod", funcTag, 142}, + {"float64toint64", funcTag, 143}, + {"float64touint64", funcTag, 144}, + {"float64touint32", funcTag, 145}, + {"int64tofloat64", funcTag, 146}, + {"int64tofloat32", funcTag, 147}, + {"uint64tofloat64", funcTag, 148}, + {"uint64tofloat32", funcTag, 149}, + {"uint32tofloat64", funcTag, 150}, + {"complex128div", funcTag, 151}, + {"racefuncenter", funcTag, 33}, {"racefuncexit", funcTag, 9}, - {"raceread", funcTag, 29}, - {"racewrite", funcTag, 29}, - {"racereadrange", funcTag, 146}, - {"racewriterange", funcTag, 146}, - {"msanread", funcTag, 146}, - {"msanwrite", funcTag, 146}, - {"msanmove", funcTag, 147}, - {"asanread", funcTag, 146}, - {"asanwrite", funcTag, 146}, - {"checkptrAlignment", funcTag, 148}, - {"checkptrArithmetic", funcTag, 150}, - {"libfuzzerTraceCmp1", funcTag, 151}, - {"libfuzzerTraceCmp2", funcTag, 152}, - {"libfuzzerTraceCmp4", funcTag, 153}, - {"libfuzzerTraceCmp8", funcTag, 154}, - {"libfuzzerTraceConstCmp1", funcTag, 151}, - {"libfuzzerTraceConstCmp2", funcTag, 152}, - {"libfuzzerTraceConstCmp4", funcTag, 153}, - {"libfuzzerTraceConstCmp8", funcTag, 154}, - {"libfuzzerHookStrCmp", funcTag, 155}, - {"libfuzzerHookEqualFold", funcTag, 155}, - {"addCovMeta", funcTag, 157}, + {"raceread", funcTag, 33}, + {"racewrite", funcTag, 33}, + {"racereadrange", funcTag, 152}, + {"racewriterange", funcTag, 152}, + {"msanread", funcTag, 152}, + {"msanwrite", funcTag, 152}, + {"msanmove", funcTag, 153}, + {"asanread", funcTag, 152}, + {"asanwrite", funcTag, 152}, + {"checkptrAlignment", funcTag, 154}, + {"checkptrArithmetic", funcTag, 156}, + {"libfuzzerTraceCmp1", funcTag, 157}, + {"libfuzzerTraceCmp2", funcTag, 158}, + {"libfuzzerTraceCmp4", funcTag, 159}, + {"libfuzzerTraceCmp8", funcTag, 160}, + {"libfuzzerTraceConstCmp1", funcTag, 157}, + {"libfuzzerTraceConstCmp2", funcTag, 158}, + {"libfuzzerTraceConstCmp4", funcTag, 159}, + {"libfuzzerTraceConstCmp8", funcTag, 160}, + {"libfuzzerHookStrCmp", funcTag, 161}, + {"libfuzzerHookEqualFold", funcTag, 161}, + {"addCovMeta", funcTag, 163}, + {"x86HasAVX", varTag, 6}, + {"x86HasFMA", varTag, 6}, {"x86HasPOPCNT", varTag, 6}, {"x86HasSSE41", varTag, 6}, - {"x86HasFMA", varTag, 6}, {"armHasVFPv4", varTag, 6}, {"arm64HasATOMICS", varTag, 6}, {"loong64HasLAMCAS", varTag, 6}, {"loong64HasLAM_BH", varTag, 6}, + {"loong64HasDBAR_HINTS", varTag, 6}, {"loong64HasLSX", varTag, 6}, {"riscv64HasZbb", varTag, 6}, - {"asanregisterglobals", funcTag, 127}, + {"asanregisterglobals", funcTag, 136}, + {"KeepAlive", funcTag, 11}, } func runtimeTypes() []*types.Type { - var typs [158]*types.Type + var typs [164]*types.Type typs[0] = types.ByteType typs[1] = types.NewPtr(typs[0]) typs[2] = types.Types[types.TANY] @@ -266,144 +279,150 @@ func runtimeTypes() []*types.Type { typs[17] = newSig(params(typs[6]), nil) typs[18] = types.Types[types.TFLOAT64] typs[19] = newSig(params(typs[18]), nil) - typs[20] = types.Types[types.TINT64] + typs[20] = types.Types[types.TFLOAT32] typs[21] = newSig(params(typs[20]), nil) - typs[22] = types.Types[types.TUINT64] + typs[22] = types.Types[types.TINT64] typs[23] = newSig(params(typs[22]), nil) - typs[24] = types.Types[types.TCOMPLEX128] + typs[24] = types.Types[types.TUINT64] typs[25] = newSig(params(typs[24]), nil) - typs[26] = types.Types[types.TSTRING] + typs[26] = types.Types[types.TCOMPLEX128] typs[27] = newSig(params(typs[26]), nil) - typs[28] = newSig(params(typs[2]), nil) - typs[29] = newSig(params(typs[5]), nil) - typs[30] = types.NewArray(typs[0], 32) - typs[31] = types.NewPtr(typs[30]) - typs[32] = newSig(params(typs[31], typs[26], typs[26]), params(typs[26])) - typs[33] = newSig(params(typs[31], typs[26], typs[26], typs[26]), params(typs[26])) - typs[34] = newSig(params(typs[31], typs[26], typs[26], typs[26], typs[26]), params(typs[26])) - typs[35] = newSig(params(typs[31], typs[26], typs[26], typs[26], typs[26], typs[26]), params(typs[26])) - typs[36] = types.NewSlice(typs[26]) - typs[37] = newSig(params(typs[31], typs[36]), params(typs[26])) - typs[38] = types.NewSlice(typs[0]) - typs[39] = newSig(params(typs[31], typs[26], typs[26]), params(typs[38])) - typs[40] = newSig(params(typs[31], typs[26], typs[26], typs[26]), params(typs[38])) - typs[41] = newSig(params(typs[31], typs[26], typs[26], typs[26], typs[26]), params(typs[38])) - typs[42] = newSig(params(typs[31], typs[26], typs[26], typs[26], typs[26], typs[26]), params(typs[38])) - typs[43] = newSig(params(typs[31], typs[36]), params(typs[38])) - typs[44] = newSig(params(typs[26], typs[26]), params(typs[13])) - typs[45] = types.NewArray(typs[0], 4) - typs[46] = types.NewPtr(typs[45]) - typs[47] = newSig(params(typs[46], typs[20]), params(typs[26])) - typs[48] = newSig(params(typs[31], typs[1], typs[13]), params(typs[26])) - typs[49] = newSig(params(typs[1], typs[13]), params(typs[26])) - typs[50] = types.RuneType - typs[51] = types.NewSlice(typs[50]) - typs[52] = newSig(params(typs[31], typs[51]), params(typs[26])) - typs[53] = newSig(params(typs[31], typs[26]), params(typs[38])) - typs[54] = types.NewArray(typs[50], 32) - typs[55] = types.NewPtr(typs[54]) - typs[56] = newSig(params(typs[55], typs[26]), params(typs[51])) - typs[57] = newSig(params(typs[3], typs[13], typs[3], typs[13], typs[5]), params(typs[13])) - typs[58] = newSig(params(typs[26], typs[13]), params(typs[50], typs[13])) - typs[59] = newSig(params(typs[26]), params(typs[13])) - typs[60] = newSig(params(typs[1], typs[3]), params(typs[7])) - typs[61] = types.Types[types.TUINT16] - typs[62] = newSig(params(typs[61]), params(typs[7])) - typs[63] = types.Types[types.TUINT32] - typs[64] = newSig(params(typs[63]), params(typs[7])) - typs[65] = newSig(params(typs[22]), params(typs[7])) - typs[66] = newSig(params(typs[26]), params(typs[7])) - typs[67] = types.Types[types.TUINT8] - typs[68] = types.NewSlice(typs[67]) - typs[69] = newSig(params(typs[68]), params(typs[7])) - typs[70] = newSig(params(typs[1], typs[1]), params(typs[1])) - typs[71] = newSig(params(typs[1], typs[1], typs[1]), nil) - typs[72] = newSig(params(typs[1]), nil) - typs[73] = newSig(params(typs[1], typs[1]), params(typs[13], typs[1])) - typs[74] = types.NewPtr(typs[5]) - typs[75] = newSig(params(typs[74], typs[7], typs[7]), params(typs[6])) - typs[76] = newSig(params(typs[13]), nil) - typs[77] = newSig(nil, params(typs[22])) - typs[78] = newSig(nil, params(typs[63])) - typs[79] = types.NewMap(typs[2], typs[2]) - typs[80] = newSig(params(typs[1], typs[20], typs[3]), params(typs[79])) - typs[81] = newSig(params(typs[1], typs[13], typs[3]), params(typs[79])) - typs[82] = newSig(nil, params(typs[79])) - typs[83] = newSig(params(typs[1], typs[79], typs[3]), params(typs[3])) - typs[84] = newSig(params(typs[1], typs[79], typs[63]), params(typs[3])) - typs[85] = newSig(params(typs[1], typs[79], typs[22]), params(typs[3])) - typs[86] = newSig(params(typs[1], typs[79], typs[26]), params(typs[3])) - typs[87] = newSig(params(typs[1], typs[79], typs[3], typs[1]), params(typs[3])) - typs[88] = newSig(params(typs[1], typs[79], typs[3]), params(typs[3], typs[6])) - typs[89] = newSig(params(typs[1], typs[79], typs[63]), params(typs[3], typs[6])) - typs[90] = newSig(params(typs[1], typs[79], typs[22]), params(typs[3], typs[6])) - typs[91] = newSig(params(typs[1], typs[79], typs[26]), params(typs[3], typs[6])) - typs[92] = newSig(params(typs[1], typs[79], typs[3], typs[1]), params(typs[3], typs[6])) - typs[93] = newSig(params(typs[1], typs[79], typs[7]), params(typs[3])) - typs[94] = newSig(params(typs[1], typs[79], typs[3]), nil) - typs[95] = newSig(params(typs[1], typs[79], typs[63]), nil) - typs[96] = newSig(params(typs[1], typs[79], typs[22]), nil) - typs[97] = newSig(params(typs[1], typs[79], typs[26]), nil) - typs[98] = newSig(params(typs[3]), nil) - typs[99] = newSig(params(typs[1], typs[79]), nil) - typs[100] = types.NewChan(typs[2], types.Cboth) - typs[101] = newSig(params(typs[1], typs[20]), params(typs[100])) - typs[102] = newSig(params(typs[1], typs[13]), params(typs[100])) - typs[103] = types.NewChan(typs[2], types.Crecv) - typs[104] = newSig(params(typs[103], typs[3]), nil) - typs[105] = newSig(params(typs[103], typs[3]), params(typs[6])) - typs[106] = types.NewChan(typs[2], types.Csend) - typs[107] = newSig(params(typs[106], typs[3]), nil) - typs[108] = newSig(params(typs[106]), nil) - typs[109] = newSig(params(typs[2]), params(typs[13])) - typs[110] = types.NewArray(typs[0], 3) - typs[111] = types.NewStruct([]*types.Field{types.NewField(src.NoXPos, Lookup("enabled"), typs[6]), types.NewField(src.NoXPos, Lookup("pad"), typs[110]), types.NewField(src.NoXPos, Lookup("cgo"), typs[6]), types.NewField(src.NoXPos, Lookup("alignme"), typs[22])}) - typs[112] = newSig(params(typs[1], typs[3], typs[3]), nil) - typs[113] = newSig(params(typs[1], typs[3]), nil) - typs[114] = newSig(params(typs[1], typs[3], typs[13], typs[3], typs[13]), params(typs[13])) - typs[115] = newSig(params(typs[106], typs[3]), params(typs[6])) - typs[116] = newSig(params(typs[3], typs[103]), params(typs[6], typs[6])) - typs[117] = newSig(params(typs[74]), nil) - typs[118] = newSig(params(typs[1], typs[1], typs[74], typs[13], typs[13], typs[6]), params(typs[13], typs[6])) - typs[119] = newSig(params(typs[1], typs[13], typs[13]), params(typs[7])) - typs[120] = newSig(params(typs[1], typs[20], typs[20]), params(typs[7])) - typs[121] = newSig(params(typs[1], typs[13], typs[13], typs[7]), params(typs[7])) - typs[122] = types.NewSlice(typs[2]) - typs[123] = newSig(params(typs[3], typs[13], typs[13], typs[13], typs[1]), params(typs[122])) - typs[124] = newSig(params(typs[1], typs[7], typs[20]), nil) - typs[125] = newSig(params(typs[7], typs[20]), nil) - typs[126] = newSig(params(typs[3], typs[3], typs[5]), nil) - typs[127] = newSig(params(typs[7], typs[5]), nil) - typs[128] = newSig(params(typs[3], typs[3], typs[5]), params(typs[6])) - typs[129] = newSig(params(typs[3], typs[3]), params(typs[6])) - typs[130] = newSig(params(typs[7], typs[7]), params(typs[6])) - typs[131] = newSig(params(typs[3], typs[5], typs[5]), params(typs[5])) - typs[132] = newSig(params(typs[7], typs[5]), params(typs[5])) - typs[133] = newSig(params(typs[3], typs[5]), params(typs[5])) - typs[134] = newSig(params(typs[20], typs[20]), params(typs[20])) - typs[135] = newSig(params(typs[22], typs[22]), params(typs[22])) - typs[136] = newSig(params(typs[18]), params(typs[20])) - typs[137] = newSig(params(typs[18]), params(typs[22])) - typs[138] = newSig(params(typs[18]), params(typs[63])) - typs[139] = newSig(params(typs[20]), params(typs[18])) - typs[140] = types.Types[types.TFLOAT32] - typs[141] = newSig(params(typs[20]), params(typs[140])) - typs[142] = newSig(params(typs[22]), params(typs[18])) - typs[143] = newSig(params(typs[22]), params(typs[140])) - typs[144] = newSig(params(typs[63]), params(typs[18])) - typs[145] = newSig(params(typs[24], typs[24]), params(typs[24])) - typs[146] = newSig(params(typs[5], typs[5]), nil) - typs[147] = newSig(params(typs[5], typs[5], typs[5]), nil) - typs[148] = newSig(params(typs[7], typs[1], typs[5]), nil) - typs[149] = types.NewSlice(typs[7]) - typs[150] = newSig(params(typs[7], typs[149]), nil) - typs[151] = newSig(params(typs[67], typs[67], typs[15]), nil) - typs[152] = newSig(params(typs[61], typs[61], typs[15]), nil) - typs[153] = newSig(params(typs[63], typs[63], typs[15]), nil) - typs[154] = newSig(params(typs[22], typs[22], typs[15]), nil) - typs[155] = newSig(params(typs[26], typs[26], typs[15]), nil) - typs[156] = types.NewArray(typs[0], 16) - typs[157] = newSig(params(typs[7], typs[63], typs[156], typs[26], typs[13], typs[67], typs[67]), params(typs[63])) + typs[28] = types.Types[types.TCOMPLEX64] + typs[29] = newSig(params(typs[28]), nil) + typs[30] = types.Types[types.TSTRING] + typs[31] = newSig(params(typs[30]), nil) + typs[32] = newSig(params(typs[2]), nil) + typs[33] = newSig(params(typs[5]), nil) + typs[34] = types.NewArray(typs[0], 32) + typs[35] = types.NewPtr(typs[34]) + typs[36] = newSig(params(typs[35], typs[30], typs[30]), params(typs[30])) + typs[37] = newSig(params(typs[35], typs[30], typs[30], typs[30]), params(typs[30])) + typs[38] = newSig(params(typs[35], typs[30], typs[30], typs[30], typs[30]), params(typs[30])) + typs[39] = newSig(params(typs[35], typs[30], typs[30], typs[30], typs[30], typs[30]), params(typs[30])) + typs[40] = types.NewSlice(typs[30]) + typs[41] = newSig(params(typs[35], typs[40]), params(typs[30])) + typs[42] = types.NewSlice(typs[0]) + typs[43] = newSig(params(typs[35], typs[30], typs[30]), params(typs[42])) + typs[44] = newSig(params(typs[35], typs[30], typs[30], typs[30]), params(typs[42])) + typs[45] = newSig(params(typs[35], typs[30], typs[30], typs[30], typs[30]), params(typs[42])) + typs[46] = newSig(params(typs[35], typs[30], typs[30], typs[30], typs[30], typs[30]), params(typs[42])) + typs[47] = newSig(params(typs[35], typs[40]), params(typs[42])) + typs[48] = newSig(params(typs[30], typs[30]), params(typs[13])) + typs[49] = types.NewArray(typs[0], 4) + typs[50] = types.NewPtr(typs[49]) + typs[51] = newSig(params(typs[50], typs[22]), params(typs[30])) + typs[52] = newSig(params(typs[35], typs[1], typs[13]), params(typs[30])) + typs[53] = newSig(params(typs[1], typs[13]), params(typs[30])) + typs[54] = types.RuneType + typs[55] = types.NewSlice(typs[54]) + typs[56] = newSig(params(typs[35], typs[55]), params(typs[30])) + typs[57] = newSig(params(typs[35], typs[30]), params(typs[42])) + typs[58] = types.NewArray(typs[54], 32) + typs[59] = types.NewPtr(typs[58]) + typs[60] = newSig(params(typs[59], typs[30]), params(typs[55])) + typs[61] = newSig(params(typs[3], typs[13], typs[3], typs[13], typs[5]), params(typs[13])) + typs[62] = newSig(params(typs[30], typs[13]), params(typs[54], typs[13])) + typs[63] = newSig(params(typs[30]), params(typs[13])) + typs[64] = newSig(params(typs[1], typs[3]), params(typs[7])) + typs[65] = types.Types[types.TUINT16] + typs[66] = newSig(params(typs[65]), params(typs[7])) + typs[67] = types.Types[types.TUINT32] + typs[68] = newSig(params(typs[67]), params(typs[7])) + typs[69] = newSig(params(typs[24]), params(typs[7])) + typs[70] = newSig(params(typs[30]), params(typs[7])) + typs[71] = types.Types[types.TUINT8] + typs[72] = types.NewSlice(typs[71]) + typs[73] = newSig(params(typs[72]), params(typs[7])) + typs[74] = newSig(params(typs[1], typs[1]), params(typs[1])) + typs[75] = newSig(params(typs[1], typs[1], typs[1]), nil) + typs[76] = newSig(params(typs[1]), nil) + typs[77] = newSig(params(typs[1], typs[1]), params(typs[13], typs[1])) + typs[78] = types.NewPtr(typs[5]) + typs[79] = newSig(params(typs[78], typs[7], typs[7]), params(typs[6])) + typs[80] = newSig(params(typs[13]), nil) + typs[81] = newSig(nil, params(typs[24])) + typs[82] = newSig(nil, params(typs[67])) + typs[83] = types.NewMap(typs[2], typs[2]) + typs[84] = newSig(params(typs[1], typs[22], typs[3]), params(typs[83])) + typs[85] = newSig(params(typs[1], typs[13], typs[3]), params(typs[83])) + typs[86] = newSig(nil, params(typs[83])) + typs[87] = newSig(params(typs[1], typs[83], typs[3]), params(typs[3])) + typs[88] = newSig(params(typs[1], typs[83], typs[67]), params(typs[3])) + typs[89] = newSig(params(typs[1], typs[83], typs[24]), params(typs[3])) + typs[90] = newSig(params(typs[1], typs[83], typs[30]), params(typs[3])) + typs[91] = newSig(params(typs[1], typs[83], typs[3], typs[1]), params(typs[3])) + typs[92] = newSig(params(typs[1], typs[83], typs[3]), params(typs[3], typs[6])) + typs[93] = newSig(params(typs[1], typs[83], typs[67]), params(typs[3], typs[6])) + typs[94] = newSig(params(typs[1], typs[83], typs[24]), params(typs[3], typs[6])) + typs[95] = newSig(params(typs[1], typs[83], typs[30]), params(typs[3], typs[6])) + typs[96] = newSig(params(typs[1], typs[83], typs[3], typs[1]), params(typs[3], typs[6])) + typs[97] = newSig(params(typs[1], typs[83], typs[7]), params(typs[3])) + typs[98] = newSig(params(typs[1], typs[83], typs[3]), nil) + typs[99] = newSig(params(typs[1], typs[83], typs[67]), nil) + typs[100] = newSig(params(typs[1], typs[83], typs[24]), nil) + typs[101] = newSig(params(typs[1], typs[83], typs[30]), nil) + typs[102] = newSig(params(typs[3]), nil) + typs[103] = newSig(params(typs[1], typs[83]), nil) + typs[104] = types.NewChan(typs[2], types.Cboth) + typs[105] = newSig(params(typs[1], typs[22]), params(typs[104])) + typs[106] = newSig(params(typs[1], typs[13]), params(typs[104])) + typs[107] = types.NewChan(typs[2], types.Crecv) + typs[108] = newSig(params(typs[107], typs[3]), nil) + typs[109] = newSig(params(typs[107], typs[3]), params(typs[6])) + typs[110] = types.NewChan(typs[2], types.Csend) + typs[111] = newSig(params(typs[110], typs[3]), nil) + typs[112] = newSig(params(typs[110]), nil) + typs[113] = newSig(params(typs[2]), params(typs[13])) + typs[114] = types.NewArray(typs[0], 3) + typs[115] = types.NewStruct([]*types.Field{types.NewField(src.NoXPos, Lookup("enabled"), typs[6]), types.NewField(src.NoXPos, Lookup("pad"), typs[114]), types.NewField(src.NoXPos, Lookup("cgo"), typs[6]), types.NewField(src.NoXPos, Lookup("alignme"), typs[24])}) + typs[116] = newSig(params(typs[1], typs[3], typs[3]), nil) + typs[117] = newSig(params(typs[1], typs[3]), nil) + typs[118] = newSig(params(typs[1], typs[3], typs[13], typs[3], typs[13]), params(typs[13])) + typs[119] = newSig(params(typs[110], typs[3]), params(typs[6])) + typs[120] = newSig(params(typs[3], typs[107]), params(typs[6], typs[6])) + typs[121] = newSig(params(typs[78]), nil) + typs[122] = newSig(params(typs[1], typs[1], typs[78], typs[13], typs[13], typs[6]), params(typs[13], typs[6])) + typs[123] = newSig(params(typs[1], typs[13], typs[13]), params(typs[7])) + typs[124] = newSig(params(typs[1], typs[22], typs[22]), params(typs[7])) + typs[125] = newSig(params(typs[1], typs[13], typs[13], typs[7]), params(typs[7])) + typs[126] = types.NewSlice(typs[2]) + typs[127] = newSig(params(typs[3], typs[13], typs[13], typs[13], typs[1]), params(typs[126])) + typs[128] = newSig(params(typs[3], typs[13], typs[13], typs[13], typs[1], typs[3], typs[13]), params(typs[126])) + typs[129] = newSig(params(typs[1], typs[7], typs[22]), nil) + typs[130] = newSig(params(typs[7], typs[22]), nil) + typs[131] = newSig(params(typs[1], typs[1], typs[13], typs[13]), params(typs[1], typs[13], typs[13])) + typs[132] = newSig(params(typs[5], typs[1], typs[13], typs[13]), params(typs[1], typs[13], typs[13])) + typs[133] = newSig(params(typs[1], typs[1], typs[13]), params(typs[1], typs[13], typs[13])) + typs[134] = newSig(params(typs[5], typs[1], typs[13]), params(typs[1], typs[13], typs[13])) + typs[135] = newSig(params(typs[3], typs[3], typs[5]), nil) + typs[136] = newSig(params(typs[7], typs[5]), nil) + typs[137] = newSig(params(typs[7], typs[7], typs[5]), params(typs[6])) + typs[138] = newSig(params(typs[7], typs[7]), params(typs[6])) + typs[139] = newSig(params(typs[7], typs[5], typs[5]), params(typs[5])) + typs[140] = newSig(params(typs[7], typs[5]), params(typs[5])) + typs[141] = newSig(params(typs[22], typs[22]), params(typs[22])) + typs[142] = newSig(params(typs[24], typs[24]), params(typs[24])) + typs[143] = newSig(params(typs[18]), params(typs[22])) + typs[144] = newSig(params(typs[18]), params(typs[24])) + typs[145] = newSig(params(typs[18]), params(typs[67])) + typs[146] = newSig(params(typs[22]), params(typs[18])) + typs[147] = newSig(params(typs[22]), params(typs[20])) + typs[148] = newSig(params(typs[24]), params(typs[18])) + typs[149] = newSig(params(typs[24]), params(typs[20])) + typs[150] = newSig(params(typs[67]), params(typs[18])) + typs[151] = newSig(params(typs[26], typs[26]), params(typs[26])) + typs[152] = newSig(params(typs[5], typs[5]), nil) + typs[153] = newSig(params(typs[5], typs[5], typs[5]), nil) + typs[154] = newSig(params(typs[7], typs[1], typs[5]), nil) + typs[155] = types.NewSlice(typs[7]) + typs[156] = newSig(params(typs[7], typs[155]), nil) + typs[157] = newSig(params(typs[71], typs[71], typs[15]), nil) + typs[158] = newSig(params(typs[65], typs[65], typs[15]), nil) + typs[159] = newSig(params(typs[67], typs[67], typs[15]), nil) + typs[160] = newSig(params(typs[24], typs[24], typs[15]), nil) + typs[161] = newSig(params(typs[30], typs[30], typs[15]), nil) + typs[162] = types.NewArray(typs[0], 16) + typs[163] = newSig(params(typs[7], typs[67], typs[162], typs[30], typs[13], typs[71], typs[71]), params(typs[67])) return typs[:] } diff --git a/src/cmd/compile/internal/typecheck/dcl.go b/src/cmd/compile/internal/typecheck/dcl.go index 4a847e85583f8a..ce3b9b43668452 100644 --- a/src/cmd/compile/internal/typecheck/dcl.go +++ b/src/cmd/compile/internal/typecheck/dcl.go @@ -42,7 +42,12 @@ func CheckFuncStack() { } } -// make a new Node off the books. +// TempAt makes a new Node off the books. +// +// N.B., the new Node is a function-local variable defaulting to function scope. +// It helps in some cases if an ODCL is also created and placed in a narrower scope, +// such as if the variable can be used in a loop body and potentially escape. +// TODO: Consider some mechanism to more conveniently create a block scoped temporary. func TempAt(pos src.XPos, curfn *ir.Func, typ *types.Type) *ir.Name { if curfn == nil { base.FatalfAt(pos, "no curfn for TempAt") diff --git a/src/cmd/compile/internal/typecheck/expr.go b/src/cmd/compile/internal/typecheck/expr.go index 44a69f03320efd..10b7c823534f4f 100644 --- a/src/cmd/compile/internal/typecheck/expr.go +++ b/src/cmd/compile/internal/typecheck/expr.go @@ -6,8 +6,6 @@ package typecheck import ( "fmt" - "go/constant" - "go/token" "internal/types/errors" "strings" @@ -314,6 +312,19 @@ func tcStructLitKey(typ *types.Type, kv *ir.KeyExpr) *ir.StructKeyExpr { return ir.NewStructKeyExpr(kv.Pos(), f, kv.Value) } + var f *types.Field + if p, ambig := dotpath(sym, typ, &f, false); p != nil { + if ambig { + base.Errorf("ambiguous promoted field '%v' in struct literal of type %v", sym, typ) + return nil + } + if f.IsMethod() { + base.Errorf("cannot use method '%v' in struct literal of type %v", sym, typ) + return nil + } + return ir.NewStructKeyExpr(kv.Pos(), f, kv.Value) + } + if ci := Lookdot1(nil, sym, typ, typ.Fields(), 2); ci != nil { // Case-insensitive lookup. if visible(ci.Sym) { base.Errorf("unknown field '%v' in struct literal of type %v (but does have %v)", sym, typ, ci.Sym) @@ -325,7 +336,6 @@ func tcStructLitKey(typ *types.Type, kv *ir.KeyExpr) *ir.StructKeyExpr { return nil } - var f *types.Field p, _ := dotpath(sym, typ, &f, true) if p == nil || f.IsMethod() { base.Errorf("unknown field '%v' in struct literal of type %v", sym, typ) @@ -337,8 +347,8 @@ func tcStructLitKey(typ *types.Type, kv *ir.KeyExpr) *ir.StructKeyExpr { for ei := len(p) - 1; ei >= 0; ei-- { ep = append(ep, p[ei].field.Sym.Name) } - ep = append(ep, sym.Name) - base.Errorf("cannot use promoted field %v in struct literal of type %v", strings.Join(ep, "."), typ) + ep = append(ep, f.Sym.Name) + base.Errorf("unknown field '%v' in struct literal of type %v (but does have %v)", sym, typ, strings.Join(ep, ".")) return nil } @@ -826,18 +836,6 @@ func tcSliceHeader(n *ir.SliceHeaderExpr) ir.Node { n.Len = DefaultLit(Expr(n.Len), types.Types[types.TINT]) n.Cap = DefaultLit(Expr(n.Cap), types.Types[types.TINT]) - if ir.IsConst(n.Len, constant.Int) && ir.Int64Val(n.Len) < 0 { - base.Fatalf("len for OSLICEHEADER must be non-negative") - } - - if ir.IsConst(n.Cap, constant.Int) && ir.Int64Val(n.Cap) < 0 { - base.Fatalf("cap for OSLICEHEADER must be non-negative") - } - - if ir.IsConst(n.Len, constant.Int) && ir.IsConst(n.Cap, constant.Int) && constant.Compare(n.Len.Val(), token.GTR, n.Cap.Val()) { - base.Fatalf("len larger than cap for OSLICEHEADER") - } - return n } @@ -859,10 +857,6 @@ func tcStringHeader(n *ir.StringHeaderExpr) ir.Node { n.Ptr = Expr(n.Ptr) n.Len = DefaultLit(Expr(n.Len), types.Types[types.TINT]) - if ir.IsConst(n.Len, constant.Int) && ir.Int64Val(n.Len) < 0 { - base.Fatalf("len for OSTRINGHEADER must be non-negative") - } - return n } diff --git a/src/cmd/compile/internal/typecheck/func.go b/src/cmd/compile/internal/typecheck/func.go index 57657315467abf..79093e5194b406 100644 --- a/src/cmd/compile/internal/typecheck/func.go +++ b/src/cmd/compile/internal/typecheck/func.go @@ -12,7 +12,6 @@ import ( "fmt" "go/constant" - "go/token" ) // MakeDotArgs package all the arguments that match a ... T parameter into a []T. @@ -564,11 +563,6 @@ func tcMake(n *ir.CallExpr) ir.Node { n.SetType(nil) return n } - if ir.IsConst(l, constant.Int) && r != nil && ir.IsConst(r, constant.Int) && constant.Compare(l.Val(), token.GTR, r.Val()) { - base.Errorf("len larger than cap in make(%v)", t) - n.SetType(nil) - return n - } nn = ir.NewMakeExpr(n.Pos(), ir.OMAKESLICE, l, r) case types.TMAP: @@ -655,14 +649,6 @@ func tcMakeSliceCopy(n *ir.MakeExpr) ir.Node { base.Errorf("non-integer len argument in OMAKESLICECOPY") } - if ir.IsConst(n.Len, constant.Int) { - if ir.ConstOverflow(n.Len.Val(), types.Types[types.TINT]) { - base.Fatalf("len for OMAKESLICECOPY too large") - } - if constant.Sign(n.Len.Val()) < 0 { - base.Fatalf("len for OMAKESLICECOPY must be non-negative") - } - } return n } diff --git a/src/cmd/compile/internal/typecheck/mkbuiltin.go b/src/cmd/compile/internal/typecheck/mkbuiltin.go index 28afac5d7ab190..c3b0848b1eef17 100644 --- a/src/cmd/compile/internal/typecheck/mkbuiltin.go +++ b/src/cmd/compile/internal/typecheck/mkbuiltin.go @@ -79,7 +79,7 @@ func params(tlist ...*types.Type) []*types.Field { func mkbuiltin(w io.Writer, name string) { fset := token.NewFileSet() - f, err := parser.ParseFile(fset, filepath.Join("_builtin", name+".go"), nil, 0) + f, err := parser.ParseFile(fset, filepath.Join("_builtin", name+".go"), nil, parser.SkipObjectResolution) if err != nil { log.Fatal(err) } diff --git a/src/cmd/compile/internal/typecheck/stmt.go b/src/cmd/compile/internal/typecheck/stmt.go index 2ca8e7fb861626..9c3c8e97e1084f 100644 --- a/src/cmd/compile/internal/typecheck/stmt.go +++ b/src/cmd/compile/internal/typecheck/stmt.go @@ -224,7 +224,7 @@ func normalizeGoDeferCall(pos src.XPos, op ir.Op, call ir.Node, init *ir.Nodes) } // Create a new wrapper function without parameters or results. - wrapperFn := ir.NewClosureFunc(pos, pos, op, types.NewSignature(nil, nil, nil), ir.CurFunc, Target) + wrapperFn := ir.NewClosureFunc(pos, pos, op, types.NewSignature(nil, nil, nil), ir.CurFunc, Target, 0) wrapperFn.DeclareParams(true) wrapperFn.SetWrapper(true) diff --git a/src/cmd/compile/internal/typecheck/subr.go b/src/cmd/compile/internal/typecheck/subr.go index 3b22d260bf4faf..27943f2902c85c 100644 --- a/src/cmd/compile/internal/typecheck/subr.go +++ b/src/cmd/compile/internal/typecheck/subr.go @@ -790,3 +790,21 @@ var slist []symlink type symlink struct { field *types.Field } + +// FieldOffset returns the offset of field f in t, +// including any implicit offsets from embedded fields. +func FieldOffset(t *types.Type, f *types.Field) int64 { + if f.Sym == nil { + return f.Offset + } + path, ambig := dotpath(f.Sym, t, nil, false) + if path == nil || ambig { + return f.Offset + } + var offset int64 + for _, d := range path { + offset += d.field.Offset + } + offset += f.Offset + return offset +} diff --git a/src/cmd/compile/internal/typecheck/typecheck.go b/src/cmd/compile/internal/typecheck/typecheck.go index c97220e6c23291..d7aad9c6b96f60 100644 --- a/src/cmd/compile/internal/typecheck/typecheck.go +++ b/src/cmd/compile/internal/typecheck/typecheck.go @@ -713,7 +713,7 @@ func implicitstar(n ir.Node) ir.Node { return Expr(star) } -func needOneArg(n *ir.CallExpr, f string, args ...interface{}) (ir.Node, bool) { +func needOneArg(n *ir.CallExpr, f string, args ...any) (ir.Node, bool) { if len(n.Args) == 0 { p := fmt.Sprintf(f, args...) base.Errorf("missing argument to %s: %v", p, n) diff --git a/src/cmd/compile/internal/types/algkind_string.go b/src/cmd/compile/internal/types/algkind_string.go index ca65a72c29acd4..d48940dfc1ab18 100644 --- a/src/cmd/compile/internal/types/algkind_string.go +++ b/src/cmd/compile/internal/types/algkind_string.go @@ -33,8 +33,9 @@ const _AlgKind_name = "UNKNOEQNOALGMEMMEM0MEM8MEM16MEM32MEM64MEM128STRINGINTERNI var _AlgKind_index = [...]uint8{0, 3, 7, 12, 15, 19, 23, 28, 33, 38, 44, 50, 55, 63, 70, 77, 83, 90, 97} func (i AlgKind) String() string { - if i < 0 || i >= AlgKind(len(_AlgKind_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_AlgKind_index)-1 { return "AlgKind(" + strconv.FormatInt(int64(i), 10) + ")" } - return _AlgKind_name[_AlgKind_index[i]:_AlgKind_index[i+1]] + return _AlgKind_name[_AlgKind_index[idx]:_AlgKind_index[idx+1]] } diff --git a/src/cmd/compile/internal/types/fmt.go b/src/cmd/compile/internal/types/fmt.go index 67e2e99f02f5fd..dd52cd1298fe7e 100644 --- a/src/cmd/compile/internal/types/fmt.go +++ b/src/cmd/compile/internal/types/fmt.go @@ -9,6 +9,7 @@ import ( "encoding/binary" "fmt" "strconv" + "strings" "sync" "cmd/compile/internal/base" @@ -183,7 +184,7 @@ var BasicTypeNames = []string{ } var fmtBufferPool = sync.Pool{ - New: func() interface{} { + New: func() any { return new(bytes.Buffer) }, } @@ -430,10 +431,11 @@ func tconv2(b *bytes.Buffer, t *Type, verb rune, mode fmtMode, visited map[*Type case IsExported(f.Sym.Name): sconv2(b, f.Sym, 'S', mode) default: + smode := mode if mode != fmtTypeIDName { - mode = fmtTypeID + smode = fmtTypeID } - sconv2(b, f.Sym, 'v', mode) + sconv2(b, f.Sym, 'v', smode) } tconv2(b, f.Type, 'S', mode, visited) } @@ -640,6 +642,16 @@ func SplitVargenSuffix(name string) (base, suffix string) { return name, "" } +// SplitMethSuffix returns name split into a defining type name and a .m +// suffix, if any. +func SplitMethSuffix(name string) (tname, suffix string) { + i := strings.LastIndex(name, ".") + if i >= 0 { + return name[:i], name[i:] + } + return name, "" +} + // TypeHash computes a hash value for type t to use in type switch statements. func TypeHash(t *Type) uint32 { p := t.LinkString() diff --git a/src/cmd/compile/internal/types/kind_string.go b/src/cmd/compile/internal/types/kind_string.go index 1e1e84624080b0..7bd78b3919613c 100644 --- a/src/cmd/compile/internal/types/kind_string.go +++ b/src/cmd/compile/internal/types/kind_string.go @@ -53,8 +53,9 @@ const _Kind_name = "xxxINT8UINT8INT16UINT16INT32UINT32INT64UINT64INTUINTUINTPTRC var _Kind_index = [...]uint8{0, 3, 7, 12, 17, 23, 28, 34, 39, 45, 48, 52, 59, 68, 78, 85, 92, 96, 99, 103, 108, 113, 119, 123, 126, 131, 135, 138, 144, 153, 158, 161, 166, 174, 182, 185, 190, 197, 202} func (i Kind) String() string { - if i >= Kind(len(_Kind_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_Kind_index)-1 { return "Kind(" + strconv.FormatInt(int64(i), 10) + ")" } - return _Kind_name[_Kind_index[i]:_Kind_index[i+1]] + return _Kind_name[_Kind_index[idx]:_Kind_index[idx+1]] } diff --git a/src/cmd/compile/internal/types/size.go b/src/cmd/compile/internal/types/size.go index 72ec4052a808e4..4d64c7f8d28cc9 100644 --- a/src/cmd/compile/internal/types/size.go +++ b/src/cmd/compile/internal/types/size.go @@ -10,6 +10,7 @@ import ( "cmd/compile/internal/base" "cmd/internal/src" + "internal/buildcfg" "internal/types/errors" ) @@ -365,6 +366,12 @@ func CalcSize(t *Type) { t.intRegs = 1 CheckSize(t.Elem()) CheckSize(t.Key()) + if t.Elem().width >= 1<<31 { + base.Errorf("map element type too large") + } + if t.Key().width >= 1<<31 { + base.Errorf("map key type too large") + } t.setAlg(ANOEQ) t.ptrBytes = int64(PtrSize) @@ -452,6 +459,26 @@ func CalcSize(t *Type) { ResumeCheckSize() } +// simdify marks as type as "SIMD", either as a tag field, +// or having the SIMD attribute. The tag field is a marker +// type used to identify a struct that is not really a struct. +// A SIMD type is allocated to a vector register (on amd64, +// xmm, ymm, or zmm). The fields of a SIMD type are ignored +// by the compiler except for the space that they reserve. +func simdify(st *Type, isTag bool) { + st.align = 8 + st.alg = ANOALG // not comparable with == + st.intRegs = 0 + st.isSIMD = true + if isTag { + st.width = 0 + st.isSIMDTag = true + st.floatRegs = 0 + } else { + st.floatRegs = 1 + } +} + // CalcStructSize calculates the size of t, // filling in t.width, t.align, t.intRegs, and t.floatRegs, // even if size calculation is otherwise disabled. @@ -464,10 +491,26 @@ func CalcStructSize(t *Type) { switch { case sym.Name == "align64" && isAtomicStdPkg(sym.Pkg): maxAlign = 8 + + case buildcfg.Experiment.SIMD && (sym.Pkg.Path == "simd/archsimd") && len(t.Fields()) >= 1: + // This gates the experiment -- without it, no user-visible types can be "simd". + // The SSA-visible SIMD types remain. + switch sym.Name { + case "v128": + simdify(t, true) + return + case "v256": + simdify(t, true) + return + case "v512": + simdify(t, true) + return + } } } fields := t.Fields() + size := calcStructOffset(t, fields, 0) // For non-zero-sized structs which end in a zero-sized field, we @@ -540,6 +583,11 @@ func CalcStructSize(t *Type) { break } } + + if len(t.Fields()) >= 1 && t.Fields()[0].Type.isSIMDTag { + // this catches `type Foo simd.Whatever` -- Foo is also SIMD. + simdify(t, false) + } } // CalcArraySize calculates the size of t, diff --git a/src/cmd/compile/internal/types/sizeof_test.go b/src/cmd/compile/internal/types/sizeof_test.go index ba033ec499b086..1b80659c8edb0b 100644 --- a/src/cmd/compile/internal/types/sizeof_test.go +++ b/src/cmd/compile/internal/types/sizeof_test.go @@ -16,9 +16,9 @@ func TestSizeof(t *testing.T) { const _64bit = unsafe.Sizeof(uintptr(0)) == 8 var tests = []struct { - val interface{} // type as a value - _32bit uintptr // size on 32bit platforms - _64bit uintptr // size on 64bit platforms + val any // type as a value + _32bit uintptr // size on 32bit platforms + _64bit uintptr // size on 64bit platforms }{ {Sym{}, 32, 64}, {Type{}, 60, 96}, diff --git a/src/cmd/compile/internal/types/type.go b/src/cmd/compile/internal/types/type.go index da859290f7a256..3fa0b90e12938e 100644 --- a/src/cmd/compile/internal/types/type.go +++ b/src/cmd/compile/internal/types/type.go @@ -174,7 +174,7 @@ type Type struct { // TARRAY: *Array // TSLICE: Slice // TSSA: string - extra interface{} + extra any // width is the width of this Type in bytes. width int64 // valid if Align > 0 @@ -200,8 +200,9 @@ type Type struct { intRegs, floatRegs uint8 // registers needed for ABIInternal - flags bitset8 - alg AlgKind // valid if Align > 0 + flags bitset8 + alg AlgKind // valid if Align > 0 + isSIMDTag, isSIMD bool // tag is the marker type, isSIMD means has marker type // size of prefix of object that contains all pointers. valid if Align > 0. // Note that for pointers, this is always PtrSize even if the element type @@ -594,6 +595,12 @@ func newSSA(name string) *Type { return t } +func newSIMD(name string) *Type { + t := newSSA(name) + t.isSIMD = true + return t +} + // NewMap returns a new map Type with key type k and element (aka value) type v. func NewMap(k, v *Type) *Type { t := newType(TMAP) @@ -982,17 +989,16 @@ func (t *Type) ArgWidth() int64 { return t.extra.(*Func).Argwid } +// Size returns the width of t in bytes. func (t *Type) Size() int64 { if t.kind == TSSA { - if t == TypeInt128 { - return 16 - } - return 0 + return t.width } CalcSize(t) return t.width } +// Alignment returns the alignment of t in bytes. func (t *Type) Alignment() int64 { CalcSize(t) return int64(t.align) @@ -1598,12 +1604,26 @@ var ( TypeFlags = newSSA("flags") TypeVoid = newSSA("void") TypeInt128 = newSSA("int128") + TypeVec128 = newSIMD("vec128") + TypeVec256 = newSIMD("vec256") + TypeVec512 = newSIMD("vec512") + TypeMask = newSIMD("mask") // not a vector, not 100% sure what this should be. TypeResultMem = newResults([]*Type{TypeMem}) ) func init() { TypeInt128.width = 16 TypeInt128.align = 8 + + TypeVec128.width = 16 + TypeVec128.align = 8 + TypeVec256.width = 32 + TypeVec256.align = 8 + TypeVec512.width = 64 + TypeVec512.align = 8 + + TypeMask.width = 8 // This will depend on the architecture; spilling will be "interesting". + TypeMask.align = 8 } // NewNamed returns a new named type for the given type name. obj should be an @@ -1663,6 +1683,9 @@ func (t *Type) SetUnderlying(underlying *Type) { if underlying.HasShape() { t.SetHasShape(true) } + if underlying.isSIMD { + simdify(t, underlying.isSIMDTag) + } // spec: "The declared type does not inherit any methods bound // to the existing type, but the method set of an interface @@ -1822,26 +1845,7 @@ func IsReflexive(t *Type) bool { // Can this type be stored directly in an interface word? // Yes, if the representation is a single pointer. func IsDirectIface(t *Type) bool { - switch t.Kind() { - case TPTR: - // Pointers to notinheap types must be stored indirectly. See issue 42076. - return !t.Elem().NotInHeap() - case TCHAN, - TMAP, - TFUNC, - TUNSAFEPTR: - return true - - case TARRAY: - // Array of 1 direct iface type can be direct. - return t.NumElem() == 1 && IsDirectIface(t.Elem()) - - case TSTRUCT: - // Struct with 1 field of direct iface type can be direct. - return t.NumFields() == 1 && IsDirectIface(t.Field(0).Type) - } - - return false + return t.Size() == int64(PtrSize) && PtrDataSize(t) == int64(PtrSize) } // IsInterfaceMethod reports whether (field) m is @@ -1982,3 +1986,7 @@ var SimType [NTYPE]Kind // Fake package for shape types (see typecheck.Shapify()). var ShapePkg = NewPkg("go.shape", "go.shape") + +func (t *Type) IsSIMD() bool { + return t.isSIMD +} diff --git a/src/cmd/compile/internal/types/type_test.go b/src/cmd/compile/internal/types/type_test.go index 1fd05b3f5e8c76..ddb7e4f3365b27 100644 --- a/src/cmd/compile/internal/types/type_test.go +++ b/src/cmd/compile/internal/types/type_test.go @@ -5,9 +5,62 @@ package types import ( + "bytes" + "fmt" + "strings" "testing" + + "cmd/internal/src" ) +// testTypeName is a minimal types.Object for NewNamed in tests. +type testTypeName struct { + sym *Sym +} + +func (o *testTypeName) Sym() *Sym { return o.sym } +func (o *testTypeName) Pos() src.XPos { return src.NoXPos } +func (o *testTypeName) Type() *Type { return nil } + +// If the printer mistakenly switches to fmtTypeID while formatting an +// unexported interface method name, the method's signature is then +// printed in fmtTypeID as well, so package-local names use Pkg.Prefix +// (import path) instead of Pkg.Name. Regression test for that mistake. +func TestFormatInterfaceUnexportedMethodUsesGoModeForSignature(t *testing.T) { + oldLocal := LocalPkg + oldPtr, oldReg, oldMax := PtrSize, RegSize, MaxWidth + t.Cleanup(func() { + LocalPkg = oldLocal + PtrSize, RegSize, MaxWidth = oldPtr, oldReg, oldMax + }) + LocalPkg = NewPkg("main", "main") + PtrSize = 8 + RegSize = 8 + MaxWidth = 1 << 50 + + lib := NewPkg("example.com/lib", "lib") + namedT := NewNamed(&testTypeName{sym: lib.Lookup("T")}) + // Underlying must not rely on Types[…]; InitTypes is not run in this package's tests. + namedT.SetUnderlying(NewStruct(nil)) + + sig := NewSignature(nil, nil, []*Field{NewField(src.NoXPos, nil, namedT)}) + iface := NewInterface([]*Field{NewField(src.NoXPos, LocalPkg.Lookup("unexported"), sig)}) + CalcSize(iface) // populate interface method set for printing (expandiface) + + var buf bytes.Buffer + fmt.Fprintf(&buf, "%v", iface) + got := buf.String() + // Go syntax should qualify T with the package name, not the linker prefix / path. + const want = "lib.T" + if !strings.Contains(got, want) { + t.Fatalf("formatted type missing %q:\n%s", want, got) + } + // Stale fmtTypeID mode used Prefix ("example.com/lib") instead of Name ("lib"). + if strings.Contains(got, "example.com/lib.T") { + t.Fatalf("formatted type should not use import path to qualify T (found example.com/lib.T):\n%s", got) + } +} + func TestSSACompare(t *testing.T) { a := []*Type{ TypeInvalid, diff --git a/src/cmd/compile/internal/types2/alias.go b/src/cmd/compile/internal/types2/alias.go index d306600ebd2710..11581bd5a7b2f2 100644 --- a/src/cmd/compile/internal/types2/alias.go +++ b/src/cmd/compile/internal/types2/alias.go @@ -21,24 +21,6 @@ import ( // // Like a defined ([Named]) type, an alias type has a name. // Use the [Alias.Obj] method to access its [TypeName] object. -// -// Historically, Alias types were not materialized so that, in the example -// above, A's type was represented by a Basic (int), not an Alias -// whose [Alias.Rhs] is int. But Go 1.24 allows you to declare an -// alias type with type parameters or arguments: -// -// type Set[K comparable] = map[K]bool -// s := make(Set[String]) -// -// and this requires that Alias types be materialized. Use the -// [Alias.TypeParams] and [Alias.TypeArgs] methods to access them. -// -// To ease the transition, the Alias type was introduced in go1.22, -// but the type-checker would not construct values of this type unless -// the GODEBUG=gotypesalias=1 environment variable was provided. -// Starting in go1.23, this variable is enabled by default. -// This setting also causes the predeclared type "any" to be -// represented as an Alias, not a bare [Interface]. type Alias struct { obj *TypeName // corresponding declared alias object orig *Alias // original, uninstantiated alias diff --git a/src/cmd/compile/internal/types2/alias_test.go b/src/cmd/compile/internal/types2/alias_test.go new file mode 100644 index 00000000000000..7e108e179c325c --- /dev/null +++ b/src/cmd/compile/internal/types2/alias_test.go @@ -0,0 +1,61 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package types2_test + +import ( + "cmd/compile/internal/types2" + "testing" +) + +func TestIssue74181(t *testing.T) { + src := `package p + +type AB = A[B] + +type _ struct { + _ AB +} + +type B struct { + f *AB +} + +type A[T any] struct{} +` + + pkg := mustTypecheck(src, nil, nil) + b := pkg.Scope().Lookup("B").Type() + if n, ok := b.(*types2.Named); ok { + if s, ok := n.Underlying().(*types2.Struct); ok { + got := s.Field(0).Type() + want := types2.NewPointer(pkg.Scope().Lookup("AB").Type()) + if !types2.Identical(got, want) { + t.Errorf("wrong type for f: got %v, want %v", got, want) + } + return + } + } + t.Errorf("unexpected type for B: %v", b) +} + +func TestPartialTypeCheckUndeclaredAliasPanic(t *testing.T) { + src := `package p + +type A = B // undeclared +` + + pkg, _ := typecheck(src, nil, nil) // don't panic on error + a := pkg.Scope().Lookup("A").Type() + if alias, ok := a.(*types2.Alias); ok { + got := alias.Rhs() + want := types2.Typ[types2.Invalid] + + if !types2.Identical(got, want) { + t.Errorf("wrong type for B: got %v, want %v", got, want) + } + return + } + t.Errorf("unexpected type for A: %v", a) +} diff --git a/src/cmd/compile/internal/types2/api.go b/src/cmd/compile/internal/types2/api.go index 8752eff99212e6..e6caf676b3a4c6 100644 --- a/src/cmd/compile/internal/types2/api.go +++ b/src/cmd/compile/internal/types2/api.go @@ -175,16 +175,6 @@ type Config struct { // of an error message. ErrorURL must be a format string containing // exactly one "%s" format, e.g. "[go.dev/e/%s]". ErrorURL string - - // If EnableAlias is set, alias declarations produce an Alias type. Otherwise - // the alias information is only in the type name, which points directly to - // the actual (aliased) type. - // - // This setting must not differ among concurrent type-checking operations, - // since it affects the behavior of Universe.Lookup("any"). - // - // This flag will eventually be removed (with Go 1.24 at the earliest). - EnableAlias bool } // Info holds result type information for a type-checked package. @@ -447,6 +437,10 @@ type Instance struct { Type Type } +func (inst Instance) String() string { + return fmt.Sprintf("%s%s", inst.TypeArgs, inst.Type) +} + // An Initializer describes a package-level variable, or a list of variables in case // of a multi-valued initialization expression, and the corresponding initialization // expression. diff --git a/src/cmd/compile/internal/types2/api_predicates.go b/src/cmd/compile/internal/types2/api_predicates.go index d2473804c067a6..f41890d66cc9a1 100644 --- a/src/cmd/compile/internal/types2/api_predicates.go +++ b/src/cmd/compile/internal/types2/api_predicates.go @@ -28,7 +28,7 @@ func AssertableTo(V *Interface, T Type) bool { // The behavior of AssignableTo is unspecified if V or T is Typ[Invalid] or an // uninstantiated generic type. func AssignableTo(V, T Type) bool { - x := operand{mode: value, typ: V} + x := operand{mode_: value, typ_: V} ok, _ := x.assignableTo(nil, T, nil) // check not needed for non-constant x return ok } @@ -39,7 +39,7 @@ func AssignableTo(V, T Type) bool { // The behavior of ConvertibleTo is unspecified if V or T is Typ[Invalid] or an // uninstantiated generic type. func ConvertibleTo(V, T Type) bool { - x := operand{mode: value, typ: V} + x := operand{mode_: value, typ_: V} return x.convertibleTo(nil, T, nil) // check not needed for non-constant x } diff --git a/src/cmd/compile/internal/types2/api_test.go b/src/cmd/compile/internal/types2/api_test.go index 4b7012e6c45e9f..832d7cdcd33331 100644 --- a/src/cmd/compile/internal/types2/api_test.go +++ b/src/cmd/compile/internal/types2/api_test.go @@ -1015,13 +1015,13 @@ func (r *N[C]) n() { } t.Errorf(`N.Method(...) returns %v for "m", but Info.Defs has %v`, gm, dm) } if gn != dn { - t.Errorf(`N.Method(...) returns %v for "m", but Info.Defs has %v`, gm, dm) + t.Errorf(`N.Method(...) returns %v for "n", but Info.Defs has %v`, gn, dn) } - if dmm != dm { - t.Errorf(`Inside "m", r.m uses %v, want the defined func %v`, dmm, dm) + if dmm == dm { + t.Errorf(`Inside "m", r.m uses %v, want a func distinct from %v`, dmm, dm) } if dmn == dn { - t.Errorf(`Inside "m", r.n uses %v, want a func distinct from %v`, dmm, dm) + t.Errorf(`Inside "m", r.n uses %v, want a func distinct from %v`, dmn, dn) } } @@ -1225,9 +1225,9 @@ func TestPredicatesInfo(t *testing.T) { {`package v0; var (a, b int; _ = a + b)`, `a + b`, `value`}, {`package v1; var _ = &[]int{1}`, `[]int{…}`, `value`}, {`package v2; var _ = func(){}`, `func() {}`, `value`}, - {`package v4; func f() { _ = f }`, `f`, `value`}, - {`package v3; var _ *int = nil`, `nil`, `value, nil`}, - {`package v3; var _ *int = (nil)`, `(nil)`, `value, nil`}, + {`package v3; func f() { _ = f }`, `f`, `value`}, + {`package v4; var _ *int = nil`, `nil`, `value, nil`}, + {`package v5; var _ *int = (nil)`, `(nil)`, `value, nil`}, // addressable (and thus assignable) operands {`package a0; var (x int; _ = x)`, `x`, `value, addressable, assignable`}, @@ -1258,8 +1258,8 @@ func TestPredicatesInfo(t *testing.T) { {`package m4; var v int`, `v`, ``}, {`package m5; func f() {}`, `f`, ``}, {`package m6; func _(x int) {}`, `x`, ``}, - {`package m6; func _()(x int) { return }`, `x`, ``}, - {`package m6; type T int; func (x T) _() {}`, `x`, ``}, + {`package m7; func _()(x int) { return }`, `x`, ``}, + {`package m8; type T int; func (x T) _() {}`, `x`, ``}, } for _, test := range tests { @@ -2404,6 +2404,12 @@ type J = I[int] type Nested[P any] *interface{b(P)} type K = Nested[string] + +type G[T any] struct{} + +func (G[T]) M[P interface{ ~*T }](P) {} + +type GI = G[int] ` pkg := mustTypecheck(src, nil, nil) @@ -2419,8 +2425,7 @@ type K = Nested[string] methods [2][]string // method strings ) var wg sync.WaitGroup - for i := 0; i < 2; i++ { - i := i + for i := range counts { wg.Add(1) go func() { defer wg.Done() @@ -2443,6 +2448,23 @@ type K = Nested[string] } } } + + // Expand a generic method on a Named instance concurrently. + named := Unalias(pkg.Scope().Lookup("GI").Type()).(*Named) + var bounds [2]string + var wg sync.WaitGroup + for i := range bounds { + wg.Add(1) + go func() { + defer wg.Done() + sig := named.Method(0).Type().(*Signature) + bounds[i] = sig.TypeParams().At(0).Underlying().String() + }() + } + wg.Wait() + if bounds[0] != bounds[1] || bounds[0] != "interface{~*int}" { + t.Errorf("mismatching bounds for GI.M: %s vs %s", bounds[0], bounds[1]) + } } func TestInstantiateErrors(t *testing.T) { @@ -2599,7 +2621,6 @@ func fn() { }) for _, test := range tests { - test := test t.Run(test.name, func(t *testing.T) { if got := len(idents[test.name]); got != 1 { t.Fatalf("found %d identifiers named %s, want 1", got, test.name) @@ -2979,7 +3000,6 @@ func TestTooNew(t *testing.T) { // This is a regression test for #66704. func TestUnaliasTooSoonInCycle(t *testing.T) { - t.Setenv("GODEBUG", "gotypesalias=1") const src = `package a var x T[B] // this appears to cause Unalias to be called on B while still Invalid @@ -3005,7 +3025,7 @@ type B = C type C = int ` - pkg := mustTypecheck(src, &Config{EnableAlias: true}, nil) + pkg := mustTypecheck(src, nil, nil) A := pkg.Scope().Lookup("A") got, want := A.Type().(*Alias).Rhs().String(), "p.B" @@ -3014,28 +3034,6 @@ type C = int } } -// Test the hijacking described of "any" described in golang/go#66921, for -// (concurrent) type checking. -func TestAnyHijacking_Check(t *testing.T) { - for _, enableAlias := range []bool{false, true} { - t.Run(fmt.Sprintf("EnableAlias=%t", enableAlias), func(t *testing.T) { - var wg sync.WaitGroup - for i := 0; i < 10; i++ { - wg.Add(1) - go func() { - defer wg.Done() - pkg := mustTypecheck("package p; var x any", &Config{EnableAlias: enableAlias}, nil) - x := pkg.Scope().Lookup("x") - if _, gotAlias := x.Type().(*Alias); gotAlias != enableAlias { - t.Errorf(`Lookup("x").Type() is %T: got Alias: %t, want %t`, x.Type(), gotAlias, enableAlias) - } - }() - } - wg.Wait() - }) - } -} - // This test function only exists for go/types. // func TestVersionIssue69477(t *testing.T) @@ -3112,3 +3110,56 @@ func (recv T) f(param int) (result int) { t.Errorf("got:\n%s\nwant:\n%s", got, want) } } + +func TestIssue79657(t *testing.T) { + src := `package p + +type T[P any] struct{} +func (T[P]) M() {} +func (T[P]) N[Q any]() {} +func (*T[P]) L[Q any]() {} + +var ( + x = T[int]{} + _ = x.M + _ = T[int].M + _ = x.N[bool] + _ = T[int].N[bool] + _ = x.L[bool] + _ = (*T[int]).L[bool] +) +` + + info := &Info{Instances: make(map[*syntax.Name]Instance)} + mustTypecheck(src, nil, info) + + test := func(inst Instance, want string) { + if recv := inst.Type.(*Signature).Recv(); recv != nil { + if got := recv.Type().String(); got != want { + t.Errorf("instance %v has receiver type %s, want %s", inst, got, want) + } + } else { + t.Errorf("instance %v has no receiver", inst) + } + } + + n, l := 0, 0 + for id, inst := range info.Instances { + switch id.Value { + case "M": + t.Errorf("unexpected instance %v", inst) + case "N": + n++ + test(inst, "p.T[int]") + case "L": + l++ + test(inst, "*p.T[int]") + } + } + if n != 2 { + t.Errorf("found %d instances of N, want 2", n) + } + if l != 2 { + t.Errorf("found %d instances of L, want 2", l) + } +} diff --git a/src/cmd/compile/internal/types2/assignments.go b/src/cmd/compile/internal/types2/assignments.go index 87f5c8beeafcaf..ac565fd6ab191b 100644 --- a/src/cmd/compile/internal/types2/assignments.go +++ b/src/cmd/compile/internal/types2/assignments.go @@ -21,7 +21,7 @@ import ( func (check *Checker) assignment(x *operand, T Type, context string) { check.singleValue(x) - switch x.mode { + switch x.mode() { case invalid: return // error reported before case nilvalue: @@ -33,11 +33,11 @@ func (check *Checker) assignment(x *operand, T Type, context string) { // we may get here because of other problems (go.dev/issue/39634, crash 12) // TODO(gri) do we need a new "generic" error code here? check.errorf(x, IncompatibleAssign, "cannot assign %s to %s in %s", x, T, context) - x.mode = invalid + x.invalidate() return } - if isUntyped(x.typ) { + if isUntyped(x.typ()) { target := T // spec: "If an untyped constant is assigned to a variable of interface // type or the blank identifier, the constant is first converted to type @@ -48,20 +48,20 @@ func (check *Checker) assignment(x *operand, T Type, context string) { if x.isNil() { if T == nil { check.errorf(x, UntypedNilUse, "use of untyped nil in %s", context) - x.mode = invalid + x.invalidate() return } } else if T == nil || isNonTypeParamInterface(T) { - target = Default(x.typ) + target = Default(x.typ()) } } else { // go/types if T == nil || isNonTypeParamInterface(T) { - if T == nil && x.typ == Typ[UntypedNil] { + if T == nil && x.typ() == Typ[UntypedNil] { check.errorf(x, UntypedNilUse, "use of untyped nil in %s", context) - x.mode = invalid + x.invalidate() return } - target = Default(x.typ) + target = Default(x.typ()) } } newType, val, code := check.implicitTypeAndValue(x, target) @@ -76,24 +76,23 @@ func (check *Checker) assignment(x *operand, T Type, context string) { code = IncompatibleAssign } check.error(x, code, msg) - x.mode = invalid + x.invalidate() return } if val != nil { x.val = val check.updateExprVal(x.expr, val) } - if newType != x.typ { - x.typ = newType + if newType != x.typ() { + x.typ_ = newType check.updateExprType(x.expr, newType, false) } } // x.typ is typed // A generic (non-instantiated) function value cannot be assigned to a variable. - if sig, _ := x.typ.Underlying().(*Signature); sig != nil && sig.TypeParams().Len() > 0 { - check.errorf(x, WrongTypeArgCount, "cannot use generic function %s without instantiation in %s", x, context) - x.mode = invalid + check.nonGeneric(newTarget(T, context), x) + if !x.isValid() { return } @@ -111,12 +110,12 @@ func (check *Checker) assignment(x *operand, T Type, context string) { } else { check.errorf(x, code, "cannot use %s as %s value in %s", x, T, context) } - x.mode = invalid + x.invalidate() } } func (check *Checker) initConst(lhs *Const, x *operand) { - if x.mode == invalid || !isValid(x.typ) || !isValid(lhs.typ) { + if !x.isValid() || !isValid(x.typ()) || !isValid(lhs.typ) { if lhs.typ == nil { lhs.typ = Typ[Invalid] } @@ -124,22 +123,22 @@ func (check *Checker) initConst(lhs *Const, x *operand) { } // rhs must be a constant - if x.mode != constant_ { + if x.mode() != constant_ { check.errorf(x, InvalidConstInit, "%s is not constant", x) if lhs.typ == nil { lhs.typ = Typ[Invalid] } return } - assert(isConstType(x.typ)) + assert(isConstType(x.typ())) // If the lhs doesn't have a type yet, use the type of x. if lhs.typ == nil { - lhs.typ = x.typ + lhs.typ = x.typ() } check.assignment(x, lhs.typ, "constant declaration") - if x.mode == invalid { + if !x.isValid() { return } @@ -151,23 +150,23 @@ func (check *Checker) initConst(lhs *Const, x *operand) { // or Typ[Invalid] in case of an error. // If the initialization check fails, x.mode is set to invalid. func (check *Checker) initVar(lhs *Var, x *operand, context string) { - if x.mode == invalid || !isValid(x.typ) || !isValid(lhs.typ) { + if !x.isValid() || !isValid(x.typ()) || !isValid(lhs.typ) { if lhs.typ == nil { lhs.typ = Typ[Invalid] } - x.mode = invalid + x.invalidate() return } // If lhs doesn't have a type yet, use the type of x. if lhs.typ == nil { - typ := x.typ + typ := x.typ() if isUntyped(typ) { // convert untyped types to default types if typ == Typ[UntypedNil] { check.errorf(x, UntypedNilUse, "use of untyped nil in %s", context) lhs.typ = Typ[Invalid] - x.mode = invalid + x.invalidate() return } typ = Default(typ) @@ -216,13 +215,13 @@ func (check *Checker) lhsVar(lhs syntax.Expr) Type { check.usedVars[v] = v_used // restore v.used } - if x.mode == invalid || !isValid(x.typ) { + if !x.isValid() || !isValid(x.typ()) { return Typ[Invalid] } // spec: "Each left-hand side operand must be addressable, a map index // expression, or the blank identifier. Operands may be parenthesized." - switch x.mode { + switch x.mode() { case invalid: return Typ[Invalid] case variable, mapindex: @@ -231,7 +230,7 @@ func (check *Checker) lhsVar(lhs syntax.Expr) Type { if sel, ok := x.expr.(*syntax.SelectorExpr); ok { var op operand check.expr(nil, &op, sel.X) - if op.mode == mapindex { + if op.mode() == mapindex { check.errorf(&x, UnaddressableFieldAssign, "cannot assign to struct field %s in map", ExprString(x.expr)) return Typ[Invalid] } @@ -240,7 +239,7 @@ func (check *Checker) lhsVar(lhs syntax.Expr) Type { return Typ[Invalid] } - return x.typ + return x.typ() } // assignVar checks the assignment lhs = rhs (if x == nil), or lhs = x (if x != nil). @@ -250,7 +249,7 @@ func (check *Checker) assignVar(lhs, rhs syntax.Expr, x *operand, context string T := check.lhsVar(lhs) // nil if lhs is _ if !isValid(T) { if x != nil { - x.mode = invalid + x.invalidate() } else { check.use(rhs) } @@ -278,7 +277,7 @@ func (check *Checker) assignVar(lhs, rhs syntax.Expr, x *operand, context string // operandTypes returns the list of types for the given operands. func operandTypes(list []*operand) (res []Type) { for _, x := range list { - res = append(res, x.typ) + res = append(res, x.typ()) } return res } @@ -383,13 +382,15 @@ func (check *Checker) returnError(at poser, lhs []*Var, rhs []*operand) { // If returnStmt is non-nil, initVars type-checks the implicit assignment // of result expressions orig_rhs to function result parameters lhs. func (check *Checker) initVars(lhs []*Var, orig_rhs []syntax.Expr, returnStmt syntax.Stmt) { + l, r := len(lhs), len(orig_rhs) + context := "assignment" if returnStmt != nil { context = "return statement" + } else if l > 1 { + context = "multiple assignment" } - l, r := len(lhs), len(orig_rhs) - // If l == 1 and the rhs is a single call, for a better // error message don't handle it as n:n mapping below. isCall := false @@ -441,7 +442,7 @@ func (check *Checker) initVars(lhs []*Var, orig_rhs []syntax.Expr, returnStmt sy } // Only record comma-ok expression if both initializations succeeded // (go.dev/issue/59371). - if commaOk && rhs[0].mode != invalid && rhs[1].mode != invalid { + if commaOk && rhs[0].mode() != invalid && rhs[1].mode() != invalid { check.recordCommaOkTypes(orig_rhs[0], rhs) } return @@ -449,7 +450,7 @@ func (check *Checker) initVars(lhs []*Var, orig_rhs []syntax.Expr, returnStmt sy // In all other cases we have an assignment mismatch. // Only report a mismatch error if there are no other errors on the rhs. - if rhs[0].mode != invalid { + if rhs[0].mode() != invalid { if returnStmt != nil { check.returnError(returnStmt, lhs, rhs) } else { @@ -469,6 +470,11 @@ func (check *Checker) initVars(lhs []*Var, orig_rhs []syntax.Expr, returnStmt sy func (check *Checker) assignVars(lhs, orig_rhs []syntax.Expr) { l, r := len(lhs), len(orig_rhs) + context := "assignment" + if l > 1 { + context = "multiple assignment" + } + // If l == 1 and the rhs is a single call, for a better // error message don't handle it as n:n mapping below. isCall := false @@ -480,7 +486,7 @@ func (check *Checker) assignVars(lhs, orig_rhs []syntax.Expr) { // each value can be assigned to its corresponding variable. if l == r && !isCall { for i, lhs := range lhs { - check.assignVar(lhs, orig_rhs[i], nil, "assignment") + check.assignVar(lhs, orig_rhs[i], nil, context) } return } @@ -501,11 +507,11 @@ func (check *Checker) assignVars(lhs, orig_rhs []syntax.Expr) { r = len(rhs) if l == r { for i, lhs := range lhs { - check.assignVar(lhs, nil, rhs[i], "assignment") + check.assignVar(lhs, nil, rhs[i], context) } // Only record comma-ok expression if both assignments succeeded // (go.dev/issue/59371). - if commaOk && rhs[0].mode != invalid && rhs[1].mode != invalid { + if commaOk && rhs[0].mode() != invalid && rhs[1].mode() != invalid { check.recordCommaOkTypes(orig_rhs[0], rhs) } return @@ -513,7 +519,7 @@ func (check *Checker) assignVars(lhs, orig_rhs []syntax.Expr) { // In all other cases we have an assignment mismatch. // Only report a mismatch error if there are no other errors on the rhs. - if rhs[0].mode != invalid { + if rhs[0].mode() != invalid { check.assignError(orig_rhs, l, r) } check.useLHS(lhs...) diff --git a/src/cmd/compile/internal/types2/builtins.go b/src/cmd/compile/internal/types2/builtins.go index d4463bc4b09a5f..e9cfcf541d76fe 100644 --- a/src/cmd/compile/internal/types2/builtins.go +++ b/src/cmd/compile/internal/types2/builtins.go @@ -53,7 +53,7 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( args = check.exprList(argList) nargs = len(args) for _, a := range args { - if a.mode == invalid { + if !a.isValid() { return } } @@ -91,6 +91,17 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // to type []byte with a second argument of string type followed by ... . // This form appends the bytes of the string." + // In either case, the first argument must be a slice; in particular it + // cannot be the predeclared nil value. Note that nil is not excluded by + // the assignability requirement alone for the special case (go.dev/issue/76220). + // spec: "If S is a type parameter, all types in its type set + // must have the same underlying slice type []E." + E, err := sliceElem(x) + if err != nil { + check.errorf(x, InvalidAppend, "invalid append: %s", err.format(check)) + return + } + // Handle append(bytes, y...) special case, where // the type set of y is {string} or {string, []byte}. var sig *Signature @@ -98,10 +109,10 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( if ok, _ := x.assignableTo(check, NewSlice(universeByte), nil); ok { y := args[1] hasString := false - for _, u := range typeset(y.typ) { + for _, u := range typeset(y.typ()) { if s, _ := u.(*Slice); s != nil && Identical(s.elem, universeByte) { // typeset ⊇ {[]byte} - } else if isString(u) { + } else if u != nil && isString(u) { // typeset ⊇ {string} hasString = true } else { @@ -111,7 +122,7 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( } if y != nil && hasString { // setting the signature also signals that we're done - sig = makeSig(x.typ, x.typ, y.typ) + sig = makeSig(x.typ(), x.typ(), y.typ()) sig.variadic = true } } @@ -119,15 +130,8 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // general case if sig == nil { - // spec: "If S is a type parameter, all types in its type set - // must have the same underlying slice type []E." - E, err := sliceElem(x) - if err != nil { - check.errorf(x, InvalidAppend, "invalid append: %s", err.format(check)) - return - } // check arguments by creating custom signature - sig = makeSig(x.typ, x.typ, NewSlice(E)) // []E required for variadic signature + sig = makeSig(x.typ(), x.typ(), NewSlice(E)) // []E required for variadic signature sig.variadic = true check.arguments(call, sig, nil, nil, args, nil) // discard result (we know the result type) // ok to continue even if check.arguments reported errors @@ -136,7 +140,7 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( if check.recordTypes() { check.recordBuiltinType(call.Fun, sig) } - x.mode = value + x.mode_ = value // x.typ is unchanged case _Cap, _Len: @@ -144,12 +148,12 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // len(x) mode := invalid var val constant.Value - switch t := arrayPtrDeref(x.typ.Underlying()).(type) { + switch t := arrayPtrDeref(x.typ().Underlying()).(type) { case *Basic: if isString(t) && id == _Len { - if x.mode == constant_ { + if x.mode() == constant_ { mode = constant_ - val = constant.MakeInt64(int64(len(constant.StringVal(x.val)))) + val = constant.MakeInt64(constant.StringLen(x.val)) } else { mode = value } @@ -179,10 +183,10 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( } case *Interface: - if !isTypeParam(x.typ) { + if !isTypeParam(x.typ()) { break } - if underIs(x.typ, func(u Type) bool { + if underIs(x.typ(), func(u Type) bool { switch t := arrayPtrDeref(u).(type) { case *Basic: if isString(t) && id == _Len { @@ -203,7 +207,7 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( if mode == invalid { // avoid error if underlying type is invalid - if isValid(x.typ.Underlying()) { + if isValid(x.typ().Underlying()) { code := InvalidCap if id == _Len { code = InvalidLen @@ -215,18 +219,18 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // record the signature before changing x.typ if check.recordTypes() && mode != constant_ { - check.recordBuiltinType(call.Fun, makeSig(Typ[Int], x.typ)) + check.recordBuiltinType(call.Fun, makeSig(Typ[Int], x.typ())) } - x.mode = mode - x.typ = Typ[Int] + x.mode_ = mode + x.typ_ = Typ[Int] x.val = val case _Clear: // clear(m) check.verifyVersionf(call.Fun, go1_21, "clear") - if !underIs(x.typ, func(u Type) bool { + if !underIs(x.typ(), func(u Type) bool { switch u.(type) { case *Map, *Slice: return true @@ -237,14 +241,14 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( return } - x.mode = novalue + x.mode_ = novalue if check.recordTypes() { - check.recordBuiltinType(call.Fun, makeSig(nil, x.typ)) + check.recordBuiltinType(call.Fun, makeSig(nil, x.typ())) } case _Close: // close(c) - if !underIs(x.typ, func(u Type) bool { + if !underIs(x.typ(), func(u Type) bool { uch, _ := u.(*Chan) if uch == nil { check.errorf(x, InvalidClose, invalidOp+"cannot close non-channel %s", x) @@ -258,9 +262,9 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( }) { return } - x.mode = novalue + x.mode_ = novalue if check.recordTypes() { - check.recordBuiltinType(call.Fun, makeSig(nil, x.typ)) + check.recordBuiltinType(call.Fun, makeSig(nil, x.typ())) } case _Complex: @@ -269,10 +273,10 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // convert or check untyped arguments d := 0 - if isUntyped(x.typ) { + if isUntyped(x.typ()) { d |= 1 } - if isUntyped(y.typ) { + if isUntyped(y.typ()) { d |= 2 } switch d { @@ -280,10 +284,10 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // x and y are typed => nothing to do case 1: // only x is untyped => convert to type of y - check.convertUntyped(x, y.typ) + check.convertUntyped(x, y.typ()) case 2: // only y is untyped => convert to type of x - check.convertUntyped(y, x.typ) + check.convertUntyped(y, x.typ()) case 3: // x and y are untyped => // 1) if both are constants, convert them to untyped @@ -293,10 +297,10 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // both of them to float64 since they must have the // same type to succeed (this will result in an error // because shifts of floats are not permitted) - if x.mode == constant_ && y.mode == constant_ { + if x.mode() == constant_ && y.mode() == constant_ { toFloat := func(x *operand) { - if isNumeric(x.typ) && constant.Sign(constant.Imag(x.val)) == 0 { - x.typ = Typ[UntypedFloat] + if isNumeric(x.typ()) && constant.Sign(constant.Imag(x.val)) == 0 { + x.typ_ = Typ[UntypedFloat] } } toFloat(x) @@ -308,13 +312,13 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // and check below } } - if x.mode == invalid || y.mode == invalid { + if !x.isValid() || !y.isValid() { return } // both argument types must be identical - if !Identical(x.typ, y.typ) { - check.errorf(x, InvalidComplex, invalidOp+"%v (mismatched types %s and %s)", call, x.typ, y.typ) + if !Identical(x.typ(), y.typ()) { + check.errorf(x, InvalidComplex, invalidOp+"%v (mismatched types %s and %s)", call, x.typ(), y.typ()) return } @@ -336,22 +340,22 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( } resTyp := check.applyTypeFunc(f, x, id) if resTyp == nil { - check.errorf(x, InvalidComplex, invalidArg+"arguments have type %s, expected floating-point", x.typ) + check.errorf(x, InvalidComplex, invalidArg+"arguments have type %s, expected floating-point", x.typ()) return } // if both arguments are constants, the result is a constant - if x.mode == constant_ && y.mode == constant_ { + if x.mode() == constant_ && y.mode() == constant_ { x.val = constant.BinaryOp(constant.ToFloat(x.val), token.ADD, constant.MakeImag(constant.ToFloat(y.val))) } else { - x.mode = value + x.mode_ = value } - if check.recordTypes() && x.mode != constant_ { - check.recordBuiltinType(call.Fun, makeSig(resTyp, x.typ, x.typ)) + if check.recordTypes() && x.mode() != constant_ { + check.recordBuiltinType(call.Fun, makeSig(resTyp, x.typ(), x.typ())) } - x.typ = resTyp + x.typ_ = resTyp case _Copy: // copy(x, y []E) int @@ -363,15 +367,26 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // []byte with a source argument of a string type. // This form copies the bytes from the string into the byte slice." + // In either case, the first argument must be a slice; in particular it + // cannot be the predeclared nil value. Note that nil is not excluded by + // the assignability requirement alone for the special case (go.dev/issue/79687). + // spec: "If the type of one or both arguments is a type parameter, all types + // in their respective type sets must have the same underlying slice type []E." + dstE, err := sliceElem(x) + if err != nil { + check.errorf(x, InvalidCopy, "invalid copy: %s", err.format(check)) + return + } + // get special case out of the way y := args[1] var special bool if ok, _ := x.assignableTo(check, NewSlice(universeByte), nil); ok { special = true - for _, u := range typeset(y.typ) { + for _, u := range typeset(y.typ()) { if s, _ := u.(*Slice); s != nil && Identical(s.elem, universeByte) { // typeset ⊇ {[]byte} - } else if isString(u) { + } else if u != nil && isString(u) { // typeset ⊇ {string} } else { special = false @@ -382,17 +397,10 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // general case if !special { - // spec: "If the type of one or both arguments is a type parameter, all types - // in their respective type sets must have the same underlying slice type []E." - dstE, err := sliceElem(x) - if err != nil { - check.errorf(x, InvalidCopy, "invalid copy: %s", err.format(check)) - return - } srcE, err := sliceElem(y) if err != nil { // If we have a string, for a better error message proceed with byte element type. - if !allString(y.typ) { + if !allString(y.typ()) { check.errorf(y, InvalidCopy, "invalid copy: %s", err.format(check)) return } @@ -405,16 +413,16 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( } if check.recordTypes() { - check.recordBuiltinType(call.Fun, makeSig(Typ[Int], x.typ, y.typ)) + check.recordBuiltinType(call.Fun, makeSig(Typ[Int], x.typ(), y.typ())) } - x.mode = value - x.typ = Typ[Int] + x.mode_ = value + x.typ_ = Typ[Int] case _Delete: // delete(map_, key) // map_ must be a map type or a type parameter describing map types. // The key cannot be a type parameter for now. - map_ := x.typ + map_ := x.typ() var key Type if !underIs(map_, func(u Type) bool { map_, _ := u.(*Map) @@ -434,11 +442,11 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( *x = *args[1] // key check.assignment(x, key, "argument to delete") - if x.mode == invalid { + if !x.isValid() { return } - x.mode = novalue + x.mode_ = novalue if check.recordTypes() { check.recordBuiltinType(call.Fun, makeSig(nil, map_, key)) } @@ -448,12 +456,12 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // real(complexT) floatT // convert or check untyped argument - if isUntyped(x.typ) { - if x.mode == constant_ { + if isUntyped(x.typ()) { + if x.mode() == constant_ { // an untyped constant number can always be considered // as a complex constant - if isNumeric(x.typ) { - x.typ = Typ[UntypedComplex] + if isNumeric(x.typ()) { + x.typ_ = Typ[UntypedComplex] } } else { // an untyped non-constant argument may appear if @@ -462,7 +470,7 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // result in an error (shift of complex value) check.convertUntyped(x, Typ[Complex128]) // x should be invalid now, but be conservative and check - if x.mode == invalid { + if !x.isValid() { return } } @@ -490,26 +498,26 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( if id == _Real { code = InvalidReal } - check.errorf(x, code, invalidArg+"argument has type %s, expected complex type", x.typ) + check.errorf(x, code, invalidArg+"argument has type %s, expected complex type", x.typ()) return } // if the argument is a constant, the result is a constant - if x.mode == constant_ { + if x.mode() == constant_ { if id == _Real { x.val = constant.Real(x.val) } else { x.val = constant.Imag(x.val) } } else { - x.mode = value + x.mode_ = value } - if check.recordTypes() && x.mode != constant_ { - check.recordBuiltinType(call.Fun, makeSig(resTyp, x.typ)) + if check.recordTypes() && x.mode() != constant_ { + check.recordBuiltinType(call.Fun, makeSig(resTyp, x.typ())) } - x.typ = resTyp + x.typ_ = resTyp case _Make: // make(T, n) @@ -564,10 +572,10 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( check.error(argList[1], SwappedMakeArgs, invalidArg+"length and capacity swapped") // safe to continue } - x.mode = value - x.typ = T + x.mode_ = value + x.typ_ = T if check.recordTypes() { - check.recordBuiltinType(call.Fun, makeSig(x.typ, types...)) + check.recordBuiltinType(call.Fun, makeSig(x.typ(), types...)) } case _Max, _Min: @@ -581,11 +589,11 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( } for i, a := range args { - if a.mode == invalid { + if !a.isValid() { return } - if !allOrdered(a.typ) { + if !allOrdered(a.typ()) { check.errorf(a, InvalidMinMaxOperand, invalidArg+"%s cannot be ordered", a) return } @@ -593,46 +601,46 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( // The first argument is already in x and there's nothing left to do. if i > 0 { check.matchTypes(x, a) - if x.mode == invalid { + if !x.isValid() { return } - if !Identical(x.typ, a.typ) { - check.errorf(a, MismatchedTypes, invalidArg+"mismatched types %s (previous argument) and %s (type of %s)", x.typ, a.typ, a.expr) + if !Identical(x.typ(), a.typ()) { + check.errorf(a, MismatchedTypes, invalidArg+"mismatched types %s (previous argument) and %s (type of %s)", x.typ(), a.typ(), a.expr) return } - if x.mode == constant_ && a.mode == constant_ { + if x.mode() == constant_ && a.mode() == constant_ { if constant.Compare(a.val, op, x.val) { *x = *a } } else { - x.mode = value + x.mode_ = value } } } // If nargs == 1, make sure x.mode is either a value or a constant. - if x.mode != constant_ { - x.mode = value + if x.mode() != constant_ { + x.mode_ = value // A value must not be untyped. check.assignment(x, &emptyInterface, "argument to built-in "+bin.name) - if x.mode == invalid { + if !x.isValid() { return } } // Use the final type computed above for all arguments. for _, a := range args { - check.updateExprType(a.expr, x.typ, true) + check.updateExprType(a.expr, x.typ(), true) } - if check.recordTypes() && x.mode != constant_ { + if check.recordTypes() && x.mode() != constant_ { types := make([]Type, nargs) for i := range types { - types[i] = x.typ + types[i] = x.typ() } - check.recordBuiltinType(call.Fun, makeSig(x.typ, types...)) + check.recordBuiltinType(call.Fun, makeSig(x.typ(), types...)) } case _New: @@ -641,31 +649,31 @@ func (check *Checker) builtin(x *operand, call *syntax.CallExpr, id builtinId) ( arg := argList[0] check.exprOrType(x, arg, false) check.exclude(x, 1< want { // Providing too many type arguments is always an error. check.errorf(xlist[got-1], WrongTypeArgCount, "got %d type arguments but want %d", got, want) - x.mode = invalid + x.invalidate() return nil } @@ -99,7 +99,7 @@ func (check *Checker) funcInst(T *target, pos syntax.Pos, x *operand, inst *synt // or the result type in a return statement. Create a pseudo-expression for that operand // that makes sense when reported in error messages from infer, below. expr := syntax.NewName(x.Pos(), T.desc) - args = []*operand{{mode: value, expr: expr, typ: T.sig}} + args = []*operand{{mode_: value, expr: expr, typ_: T.sig}} reverse = true } @@ -113,7 +113,7 @@ func (check *Checker) funcInst(T *target, pos syntax.Pos, x *operand, inst *synt if !err.empty() { err.report() } - x.mode = invalid + x.invalidate() return nil } got = len(targs) @@ -123,8 +123,8 @@ func (check *Checker) funcInst(T *target, pos syntax.Pos, x *operand, inst *synt // instantiate function signature sig = check.instantiateSignature(x.Pos(), x.expr, sig, targs, xlist) - x.typ = sig - x.mode = value + x.typ_ = sig + x.mode_ = value return nil } @@ -175,7 +175,7 @@ func (check *Checker) callExpr(x *operand, call *syntax.CallExpr) exprKind { // Delay function instantiation to argument checking, // where we combine type and value arguments for type // inference. - assert(x.mode == value) + assert(x.mode() == value) inst = iexpr } x.expr = iexpr @@ -185,7 +185,7 @@ func (check *Checker) callExpr(x *operand, call *syntax.CallExpr) exprKind { } // x.typ may be generic - switch x.mode { + switch x.mode() { case invalid: check.use(call.ArgList...) x.expr = call @@ -194,17 +194,22 @@ func (check *Checker) callExpr(x *operand, call *syntax.CallExpr) exprKind { case typexpr: // conversion check.nonGeneric(nil, x) - if x.mode == invalid { + if !x.isValid() { + return conversion + } + T := x.typ() + x.invalidate() + // We cannot convert a value to an incomplete type; make sure it's complete. + if !check.isComplete(T) { + x.expr = call return conversion } - T := x.typ - x.mode = invalid switch n := len(call.ArgList); n { case 0: check.errorf(call, WrongArgCount, "missing argument in conversion to %s", T) case 1: - check.expr(nil, x, call.ArgList[0]) - if x.mode != invalid { + check.expr(newTarget(T, "conversion"), x, call.ArgList[0]) + if x.isValid() { if t, _ := T.Underlying().(*Interface); t != nil && !isTypeParam(T) { if !t.IsMethodSet() { check.errorf(call, MisplacedConstraintIface, "cannot use interface %s in conversion (contains specific type constraints or is comparable)", T) @@ -228,11 +233,11 @@ func (check *Checker) callExpr(x *operand, call *syntax.CallExpr) exprKind { // no need to check for non-genericity here id := x.id if !check.builtin(x, call, id) { - x.mode = invalid + x.invalidate() } x.expr = call // a non-constant result implies a function call - if x.mode != invalid && x.mode != constant_ { + if x.isValid() && x.mode() != constant_ { check.hasCallOrRecv = true } return predeclaredFuncs[id].kind @@ -240,11 +245,11 @@ func (check *Checker) callExpr(x *operand, call *syntax.CallExpr) exprKind { // ordinary function/method call // signature may be generic - cgocall := x.mode == cgofunc + cgocall := x.mode() == cgofunc // If the operand type is a type parameter, all types in its type set // must have a common underlying type, which must be a signature. - u, err := commonUnder(x.typ, func(t, u Type) *typeError { + u, err := commonUnder(x.typ(), func(t, u Type) *typeError { if _, ok := u.(*Signature); u != nil && !ok { return typeErrorf("%s is not a function", t) } @@ -252,7 +257,7 @@ func (check *Checker) callExpr(x *operand, call *syntax.CallExpr) exprKind { }) if err != nil { check.errorf(x, InvalidCall, invalidOp+"cannot call %s: %s", x, err.format(check)) - x.mode = invalid + x.invalidate() x.expr = call return statement } @@ -269,7 +274,7 @@ func (check *Checker) callExpr(x *operand, call *syntax.CallExpr) exprKind { targs = check.typeList(xlist) if targs == nil { check.use(call.ArgList...) - x.mode = invalid + x.invalidate() x.expr = call return statement } @@ -280,7 +285,7 @@ func (check *Checker) callExpr(x *operand, call *syntax.CallExpr) exprKind { if got > want { check.errorf(xlist[want], WrongTypeArgCount, "got %d type arguments but want %d", got, want) check.use(call.ArgList...) - x.mode = invalid + x.invalidate() x.expr = call return statement } @@ -312,25 +317,32 @@ func (check *Checker) callExpr(x *operand, call *syntax.CallExpr) exprKind { // determine result switch sig.results.Len() { case 0: - x.mode = novalue + x.mode_ = novalue case 1: if cgocall { - x.mode = commaerr + x.mode_ = commaerr } else { - x.mode = value + x.mode_ = value + } + typ := sig.results.vars[0].typ // unpack tuple + // We cannot return a value of an incomplete type; make sure it's complete. + if !check.isComplete(typ) { + x.invalidate() + x.expr = call + return statement } - x.typ = sig.results.vars[0].typ // unpack tuple + x.typ_ = typ default: - x.mode = value - x.typ = sig.results + x.mode_ = value + x.typ_ = sig.results } x.expr = call check.hasCallOrRecv = true // if type inference failed, a parameterized result must be invalidated // (operands cannot have a parameterized type) - if x.mode == value && sig.TypeParams().Len() > 0 && isParameterized(sig.TypeParams().list(), x.typ) { - x.mode = invalid + if x.mode() == value && sig.TypeParams().Len() > 0 && isParameterized(sig.TypeParams().list(), x.typ()) { + x.invalidate() } return statement @@ -368,7 +380,7 @@ func (check *Checker) genericExprList(elist []syntax.Expr) (resList []*operand, if i < len(targsList) { if n := len(targsList[i]); n > 0 { // x must be a partially instantiated function - assert(n < x.typ.(*Signature).TypeParams().Len()) + assert(n < x.typ().(*Signature).TypeParams().Len()) } } } @@ -376,7 +388,7 @@ func (check *Checker) genericExprList(elist []syntax.Expr) (resList []*operand, } // Before Go 1.21, uninstantiated or partially instantiated argument functions are - // nor permitted. Checker.funcInst must infer missing type arguments in that case. + // not permitted. Checker.funcInst must infer missing type arguments in that case. infer := true // for -lang < go1.21 n := len(elist) if n > 0 && check.allowVersion(go1_21) { @@ -405,11 +417,11 @@ func (check *Checker) genericExprList(elist []syntax.Expr) (resList []*operand, // x is not a function instantiation (it may still be a generic function). check.rawExpr(nil, &x, e, nil, true) check.exclude(&x, 1< 0 { + if asig, _ := arg.typ().(*Signature); asig != nil && asig.TypeParams().Len() > 0 { // The argument type is a generic function signature. This type is // pointer-identical with (it's copied from) the type of the generic // function argument and thus the function object. @@ -583,7 +595,7 @@ func (check *Checker) arguments(call *syntax.CallExpr, sig *Signature, targs []T atparams, tmp := check.renameTParams(call.Pos(), asig.TypeParams().list(), asig) asig = tmp.(*Signature) asig.tparams = &TypeParamList{atparams} // renameTParams doesn't touch associated type parameters - arg.typ = asig // new type identity for the function argument + arg.typ_ = asig // new type identity for the function argument tparams = append(tparams, atparams...) // add partial list of type arguments, if any if i < len(atargs) { @@ -638,11 +650,11 @@ func (check *Checker) arguments(call *syntax.CallExpr, sig *Signature, targs []T j := n for _, i := range genericArgs { arg := args[i] - asig := arg.typ.(*Signature) + asig := arg.typ().(*Signature) k := j + asig.TypeParams().Len() // targs[j:k] are the inferred type arguments for asig - arg.typ = check.instantiateSignature(call.Pos(), arg.expr, asig, targs[j:k], nil) // TODO(gri) provide xlist if possible (partial instantiations) - check.record(arg) // record here because we didn't use the usual expr evaluators + arg.typ_ = check.instantiateSignature(call.Pos(), arg.expr, asig, targs[j:k], nil) // TODO(gri) provide xlist if possible (partial instantiations) + check.record(arg) // record here because we didn't use the usual expr evaluators j = k } } @@ -669,7 +681,7 @@ var cgoPrefixes = [...]string{ "_Cmacro_", // function to evaluate the expanded expression } -func (check *Checker) selector(x *operand, e *syntax.SelectorExpr, def *TypeName, wantType bool) { +func (check *Checker) selector(x *operand, e *syntax.SelectorExpr, wantType bool) { // these must be declared before the "goto Error" statements var ( obj Object @@ -715,7 +727,7 @@ func (check *Checker) selector(x *operand, e *syntax.SelectorExpr, def *TypeName } goto Error } - check.objDecl(exp, nil) + check.objDecl(exp) } else { exp = pkg.scope.Lookup(sel) if exp == nil { @@ -743,28 +755,28 @@ func (check *Checker) selector(x *operand, e *syntax.SelectorExpr, def *TypeName switch exp := exp.(type) { case *Const: assert(exp.Val() != nil) - x.mode = constant_ - x.typ = exp.typ + x.mode_ = constant_ + x.typ_ = exp.typ x.val = exp.val case *TypeName: - x.mode = typexpr - x.typ = exp.typ + x.mode_ = typexpr + x.typ_ = exp.typ case *Var: - x.mode = variable - x.typ = exp.typ + x.mode_ = variable + x.typ_ = exp.typ if pkg.cgo && strings.HasPrefix(exp.name, "_Cvar_") { - x.typ = x.typ.(*Pointer).base + x.typ_ = x.typ().(*Pointer).base } case *Func: - x.mode = funcMode - x.typ = exp.typ + x.mode_ = funcMode + x.typ_ = exp.typ if pkg.cgo && strings.HasPrefix(exp.name, "_Cmacro_") { - x.mode = value - x.typ = x.typ.(*Signature).results.vars[0].typ + x.mode_ = value + x.typ_ = x.typ().(*Signature).results.vars[0].typ } case *Builtin: - x.mode = builtin - x.typ = exp.typ + x.mode_ = builtin + x.typ_ = exp.typ x.id = exp.id default: check.dump("%v: unexpected object %v", atPos(e.Sel), exp) @@ -776,13 +788,7 @@ func (check *Checker) selector(x *operand, e *syntax.SelectorExpr, def *TypeName } check.exprOrType(x, e.X, false) - switch x.mode { - case typexpr: - // don't crash for "type T T.x" (was go.dev/issue/51509) - if def != nil && def.typ == x.typ { - check.cycleError([]Object{def}, 0) - goto Error - } + switch x.mode() { case builtin: check.errorf(e.Pos(), UncalledBuiltin, "invalid use of %s in selector expression", x) goto Error @@ -790,8 +796,12 @@ func (check *Checker) selector(x *operand, e *syntax.SelectorExpr, def *TypeName goto Error } - // Avoid crashing when checking an invalid selector in a method declaration - // (i.e., where def is not set): + // We cannot select on an incomplete type; make sure it's complete. + if !check.isComplete(x.typ()) { + goto Error + } + + // Avoid crashing when checking an invalid selector in a method declaration. // // type S[T any] struct{} // type V = S[any] @@ -801,18 +811,21 @@ func (check *Checker) selector(x *operand, e *syntax.SelectorExpr, def *TypeName // expecting a type expression, it is an error. // // See go.dev/issue/57522 for more details. - // - // TODO(rfindley): We should do better by refusing to check selectors in all cases where - // x.typ is incomplete. if wantType { check.errorf(e.Sel, NotAType, "%s is not a type", syntax.Expr(e)) goto Error } - obj, index, indirect = lookupFieldOrMethod(x.typ, x.mode == variable, check.pkg, sel, false) + // Additionally, if x.typ is a pointer type, selecting implicitly dereferences the value, meaning + // its base type must also be complete. + if p, ok := x.typ().Underlying().(*Pointer); ok && !check.isComplete(p.base) { + goto Error + } + + obj, index, indirect = lookupFieldOrMethod(x.typ(), x.mode() == variable, check.pkg, sel, false) if obj == nil { // Don't report another error if the underlying type was invalid (go.dev/issue/49541). - if !isValid(x.typ.Underlying()) { + if !isValid(x.typ().Underlying()) { goto Error } @@ -823,106 +836,104 @@ func (check *Checker) selector(x *operand, e *syntax.SelectorExpr, def *TypeName } if indirect { - if x.mode == typexpr { - check.errorf(e.Sel, InvalidMethodExpr, "invalid method expression %s.%s (needs pointer receiver (*%s).%s)", x.typ, sel, x.typ, sel) + if x.mode() == typexpr { + check.errorf(e.Sel, InvalidMethodExpr, "invalid method expression %s.%s (needs pointer receiver (*%s).%s)", x.typ(), sel, x.typ(), sel) } else { - check.errorf(e.Sel, InvalidMethodExpr, "cannot call pointer method %s on %s", sel, x.typ) + check.errorf(e.Sel, InvalidMethodExpr, "cannot call pointer method %s on %s", sel, x.typ()) } goto Error } var why string - if isInterfacePtr(x.typ) { - why = check.interfacePtrError(x.typ) + if isInterfacePtr(x.typ()) { + why = check.interfacePtrError(x.typ()) } else { - alt, _, _ := lookupFieldOrMethod(x.typ, x.mode == variable, check.pkg, sel, true) - why = check.lookupError(x.typ, sel, alt, false) + alt, _, _ := lookupFieldOrMethod(x.typ(), x.mode() == variable, check.pkg, sel, true) + why = check.lookupError(x.typ(), sel, alt, false) } check.errorf(e.Sel, MissingFieldOrMethod, "%s.%s undefined (%s)", x.expr, sel, why) goto Error } + // obj != nil - // methods may not have a fully set up signature yet - if m, _ := obj.(*Func); m != nil { - check.objDecl(m, nil) - } - - if x.mode == typexpr { - // method expression - m, _ := obj.(*Func) - if m == nil { - check.errorf(e.Sel, MissingFieldOrMethod, "%s.%s undefined (type %s has no method %s)", x.expr, sel, x.typ, sel) + switch obj := obj.(type) { + case *Var: + if x.mode() == typexpr { + check.errorf(e.X, MissingFieldOrMethod, "operand for field selector %s must be value of type %s", sel, x.typ()) goto Error } - check.recordSelection(e, MethodExpr, x.typ, m, index, indirect) - - sig := m.typ.(*Signature) - if sig.recv == nil { - check.error(e, InvalidDeclCycle, "illegal cycle in method declaration") - goto Error + // field value + check.recordSelection(e, FieldVal, x.typ(), obj, index, indirect) + if x.mode() == variable || indirect { + x.mode_ = variable + } else { + x.mode_ = value } + x.typ_ = obj.typ - // The receiver type becomes the type of the first function - // argument of the method expression's function type. - var params []*Var - if sig.params != nil { - params = sig.params.vars - } - // Be consistent about named/unnamed parameters. This is not needed - // for type-checking, but the newly constructed signature may appear - // in an error message and then have mixed named/unnamed parameters. - // (An alternative would be to not print parameter names in errors, - // but it's useful to see them; this is cheap and method expressions - // are rare.) - name := "" - if len(params) > 0 && params[0].name != "" { - // name needed - name = sig.recv.name - if name == "" { - name = "_" - } - } - params = append([]*Var{NewParam(sig.recv.pos, sig.recv.pkg, name, x.typ)}, params...) - x.mode = value - x.typ = &Signature{ - tparams: sig.tparams, - params: NewTuple(params...), - results: sig.results, - variadic: sig.variadic, - } + case *Func: + check.objDecl(obj) // ensure fully set-up signature + check.addDeclDep(obj) + // TODO(mark): Assert that sig.rparams is nil here? - check.addDeclDep(m) + if x.mode() == typexpr { + // method expression + check.recordSelection(e, MethodExpr, x.typ(), obj, index, indirect) - } else { - // regular selector - switch obj := obj.(type) { - case *Var: - check.recordSelection(e, FieldVal, x.typ, obj, index, indirect) - if x.mode == variable || indirect { - x.mode = variable - } else { - x.mode = value + sig := obj.typ.(*Signature) + if sig.recv == nil { + check.error(e, InvalidDeclCycle, "illegal cycle in method declaration") + goto Error + } + + // The receiver type becomes the type of the first function + // argument of the method expression's function type. + var params []*Var + if sig.params != nil { + params = sig.params.vars + } + // Be consistent about named/unnamed parameters. This is not needed + // for type-checking, but the newly constructed signature may appear + // in an error message and then have mixed named/unnamed parameters. + // (An alternative would be to not print parameter names in errors, + // but it's useful to see them; this is cheap and method expressions + // are rare.) + name := "" + if len(params) > 0 && params[0].name != "" { + // name needed + name = sig.recv.name + if name == "" { + name = "_" + } } - x.typ = obj.typ + params = append([]*Var{NewParam(sig.recv.pos, sig.recv.pkg, name, x.typ())}, params...) + x.mode_ = value + x.typ_ = &Signature{ + tparams: sig.tparams, + recvold: methodExprSentinel, + params: NewTuple(params...), + results: sig.results, + variadic: sig.variadic, + } + } else { + // method value - case *Func: // TODO(gri) If we needed to take into account the receiver's // addressability, should we report the type &(x.typ) instead? - check.recordSelection(e, MethodVal, x.typ, obj, index, indirect) + check.recordSelection(e, MethodVal, x.typ(), obj, index, indirect) - x.mode = value + x.mode_ = value - // remove receiver + // remove/stash receiver sig := *obj.typ.(*Signature) + sig.recvold = sig.recv sig.recv = nil - x.typ = &sig - - check.addDeclDep(obj) - - default: - panic("unreachable") + x.typ_ = &sig } + + default: + panic("unreachable") } // everything went well @@ -930,7 +941,8 @@ func (check *Checker) selector(x *operand, e *syntax.SelectorExpr, def *TypeName return Error: - x.mode = invalid + x.invalidate() + x.typ_ = Typ[Invalid] x.expr = e } @@ -958,7 +970,7 @@ func (check *Checker) useN(args []syntax.Expr, lhs bool) bool { func (check *Checker) use1(e syntax.Expr, lhs bool) bool { var x operand - x.mode = value // anything but invalid + x.mode_ = value // anything but invalid switch n := syntax.Unparen(e).(type) { case nil: // nothing to do @@ -992,5 +1004,5 @@ func (check *Checker) use1(e syntax.Expr, lhs bool) bool { default: check.rawExpr(nil, &x, e, nil, true) } - return x.mode != invalid + return x.isValid() } diff --git a/src/cmd/compile/internal/types2/check.go b/src/cmd/compile/internal/types2/check.go index 411a1719ce4bb5..d714976f74781c 100644 --- a/src/cmd/compile/internal/types2/check.go +++ b/src/cmd/compile/internal/types2/check.go @@ -12,7 +12,6 @@ import ( "go/constant" . "internal/types/errors" "os" - "sync/atomic" ) // nopos indicates an unknown position @@ -24,29 +23,6 @@ const debug = false // leave on during development // position tracing for panics during type checking const tracePos = true -// _aliasAny changes the behavior of [Scope.Lookup] for "any" in the -// [Universe] scope. -// -// This is necessary because while Alias creation is controlled by -// [Config.EnableAlias], the representation of "any" is a global. In -// [Scope.Lookup], we select this global representation based on the result of -// [aliasAny], but as a result need to guard against this behavior changing -// during the type checking pass. Therefore we implement the following rule: -// any number of goroutines can type check concurrently with the same -// EnableAlias value, but if any goroutine tries to type check concurrently -// with a different EnableAlias value, we panic. -// -// To achieve this, _aliasAny is a state machine: -// -// 0: no type checking is occurring -// negative: type checking is occurring without EnableAlias set -// positive: type checking is occurring with EnableAlias set -var _aliasAny int32 - -func aliasAny() bool { - return atomic.LoadInt32(&_aliasAny) >= 0 // default true -} - // exprInfo stores information about an untyped expression. type exprInfo struct { isLhs bool // expression is lhs operand of a shift with delayed type-check @@ -118,7 +94,7 @@ type action struct { // If debug is set, describef sets a printf-formatted description for action a. // Otherwise, it is a no-op. -func (a *action) describef(pos poser, format string, args ...interface{}) { +func (a *action) describef(pos poser, format string, args ...any) { if debug { a.desc = &actionDesc{pos, format, args} } @@ -129,7 +105,7 @@ func (a *action) describef(pos poser, format string, args ...interface{}) { type actionDesc struct { pos poser format string - args []interface{} + args []any } // A Checker maintains the state of the type checker. @@ -141,9 +117,10 @@ type Checker struct { ctxt *Context // context for de-duplicating instances pkg *Package *Info - nextID uint64 // unique Id for type parameters (first valid Id is 1) - objMap map[Object]*declInfo // maps package-level objects and (non-interface) methods to declaration info - impMap map[importKey]*Package // maps (import path, source directory) to (complete or fake) package + nextID uint64 // unique Id for type parameters (first valid Id is 1) + objMap map[Object]*declInfo // maps package-level objects and (non-interface) methods to declaration info + objList []Object // source-ordered keys of objMap + impMap map[importKey]*Package // maps (import path, source directory) to (complete or fake) package // see TODO in validtype.go // valids instanceLookup // valid *Named (incl. instantiated) types per the validType check @@ -170,12 +147,13 @@ type Checker struct { usedPkgNames map[*PkgName]bool // set of used package names mono monoGraph // graph for detecting non-monomorphizable instantiation loops - firstErr error // first error encountered - methods map[*TypeName][]*Func // maps package scope type names to associated non-blank (non-interface) methods - untyped map[syntax.Expr]exprInfo // map of expressions without final type - delayed []action // stack of delayed action segments; segments are processed in FIFO order - objPath []Object // path of object dependencies during type inference (for cycle reporting) - cleaners []cleaner // list of types that may need a final cleanup at the end of type-checking + firstErr error // first error encountered + methods map[*TypeName][]*Func // maps package scope type names to associated non-blank (non-interface) methods + untyped map[syntax.Expr]exprInfo // map of expressions without final type + delayed []action // stack of delayed action segments; segments are processed in FIFO order + objPath []Object // path of object dependencies during type-checking (for cycle reporting) + objPathIdx map[Object]int // map of object to object path index during type-checking (for cycle reporting) + cleaners []cleaner // list of types that may need a final cleanup at the end of type-checking // environment within which the current object is type-checked (valid only // for the duration of type-checking a specific object) @@ -198,34 +176,6 @@ func (check *Checker) addDeclDep(to Object) { from.addDep(to) } -// Note: The following three alias-related functions are only used -// when Alias types are not enabled. - -// brokenAlias records that alias doesn't have a determined type yet. -// It also sets alias.typ to Typ[Invalid]. -// Not used if check.conf.EnableAlias is set. -func (check *Checker) brokenAlias(alias *TypeName) { - assert(!check.conf.EnableAlias) - if check.brokenAliases == nil { - check.brokenAliases = make(map[*TypeName]bool) - } - check.brokenAliases[alias] = true - alias.typ = Typ[Invalid] -} - -// validAlias records that alias has the valid type typ (possibly Typ[Invalid]). -func (check *Checker) validAlias(alias *TypeName, typ Type) { - assert(!check.conf.EnableAlias) - delete(check.brokenAliases, alias) - alias.typ = typ -} - -// isBrokenAlias reports whether alias doesn't have a determined type yet. -func (check *Checker) isBrokenAlias(alias *TypeName) bool { - assert(!check.conf.EnableAlias) - return check.brokenAliases[alias] -} - func (check *Checker) rememberUntyped(e syntax.Expr, lhs bool, mode operandMode, typ *Basic, val constant.Value) { m := check.untyped if m == nil { @@ -247,19 +197,22 @@ func (check *Checker) later(f func()) *action { return &check.delayed[i] } -// push pushes obj onto the object path and returns its index in the path. -func (check *Checker) push(obj Object) int { +// push pushes obj onto the object path and records its index in the path index map. +func (check *Checker) push(obj Object) { + if check.objPathIdx == nil { + check.objPathIdx = make(map[Object]int) + } + check.objPathIdx[obj] = len(check.objPath) check.objPath = append(check.objPath, obj) - return len(check.objPath) - 1 } -// pop pops and returns the topmost object from the object path. -func (check *Checker) pop() Object { +// pop pops an object from the object path and removes it from the path index map. +func (check *Checker) pop() { i := len(check.objPath) - 1 obj := check.objPath[i] - check.objPath[i] = nil + check.objPath[i] = nil // help the garbage collector check.objPath = check.objPath[:i] - return obj + delete(check.objPathIdx, obj) } type cleaner interface { @@ -318,6 +271,7 @@ func (check *Checker) initFiles(files []*syntax.File) { check.untyped = nil check.delayed = nil check.objPath = nil + check.objPathIdx = nil check.cleaners = nil // We must initialize usedVars and usedPkgNames both here and in NewChecker, @@ -466,20 +420,6 @@ func (check *Checker) Files(files []*syntax.File) (err error) { // syntax is properly type annotated even in a package containing // errors. func (check *Checker) checkFiles(files []*syntax.File) { - // Ensure that EnableAlias is consistent among concurrent type checking - // operations. See the documentation of [_aliasAny] for details. - if check.conf.EnableAlias { - if atomic.AddInt32(&_aliasAny, 1) <= 0 { - panic("EnableAlias set while !EnableAlias type checking is ongoing") - } - defer atomic.AddInt32(&_aliasAny, -1) - } else { - if atomic.AddInt32(&_aliasAny, -1) >= 0 { - panic("!EnableAlias set while EnableAlias type checking is ongoing") - } - defer atomic.AddInt32(&_aliasAny, 1) - } - print := func(msg string) { if check.conf.Trace { fmt.Println() @@ -493,6 +433,12 @@ func (check *Checker) checkFiles(files []*syntax.File) { print("== collectObjects ==") check.collectObjects() + print("== sortObjects ==") + check.sortObjects() + + print("== directCycles ==") + check.directCycles() + print("== packageObjects ==") check.packageObjects() diff --git a/src/cmd/compile/internal/types2/check_test.go b/src/cmd/compile/internal/types2/check_test.go index 8b97a9f676e073..69e22f7e16627e 100644 --- a/src/cmd/compile/internal/types2/check_test.go +++ b/src/cmd/compile/internal/types2/check_test.go @@ -34,6 +34,8 @@ import ( "cmd/compile/internal/syntax" "flag" "fmt" + "go/build" + "go/build/constraint" "internal/buildcfg" "internal/testenv" "os" @@ -41,6 +43,7 @@ import ( "reflect" "regexp" "runtime" + "slices" "strconv" "strings" "testing" @@ -112,8 +115,6 @@ func parseFlags(src []byte, flags *flag.FlagSet) error { // testFiles type-checks the package consisting of the given files, and // compares the resulting errors with the ERROR annotations in the source. -// Except for manual tests, each package is type-checked twice, once without -// use of Alias types, and once with Alias types. // // The srcs slice contains the file content for the files named in the // filenames slice. The colDelta parameter specifies the tolerance for position @@ -122,16 +123,6 @@ func parseFlags(src []byte, flags *flag.FlagSet) error { // // If provided, opts may be used to mutate the Config before type-checking. func testFiles(t *testing.T, filenames []string, srcs [][]byte, colDelta uint, manual bool, opts ...func(*Config)) { - enableAlias := true - opts = append(opts, func(conf *Config) { conf.EnableAlias = enableAlias }) - testFilesImpl(t, filenames, srcs, colDelta, manual, opts...) - if !manual { - enableAlias = false - testFilesImpl(t, filenames, srcs, colDelta, manual, opts...) - } -} - -func testFilesImpl(t *testing.T, filenames []string, srcs [][]byte, colDelta uint, manual bool, opts ...func(*Config)) { if len(filenames) == 0 { t.Fatal("no source files") } @@ -171,12 +162,11 @@ func testFilesImpl(t *testing.T, filenames []string, srcs [][]byte, colDelta uin } // apply flag setting (overrides custom configuration) - var goexperiment, gotypesalias string + var goexperiment string flags := flag.NewFlagSet("", flag.PanicOnError) flags.StringVar(&conf.GoVersion, "lang", "", "") flags.StringVar(&goexperiment, "goexperiment", "", "") flags.BoolVar(&conf.FakeImportC, "fakeImportC", false, "") - flags.StringVar(&gotypesalias, "gotypesalias", "", "") if err := parseFlags(srcs[0], flags); err != nil { t.Fatal(err) } @@ -186,11 +176,6 @@ func testFilesImpl(t *testing.T, filenames []string, srcs [][]byte, colDelta uin defer revert() } - // By default, gotypesalias is not set. - if gotypesalias != "" { - conf.EnableAlias = gotypesalias != "0" - } - // Provide Config.Info with all maps so that info recording is tested. info := Info{ Types: make(map[syntax.Expr]TypeAndValue), @@ -453,13 +438,42 @@ func testDir(t *testing.T, dir string, colDelta uint, manual bool) { } func testPkg(t *testing.T, filenames []string, colDelta uint, manual bool) { - srcs := make([][]byte, len(filenames)) - for i, filename := range filenames { + fs := filenames[:0] + srcs := make([][]byte, 0, len(filenames)) + for _, filename := range filenames { src, err := os.ReadFile(filename) if err != nil { t.Fatalf("could not read %s: %v", filename, err) } - srcs[i] = src + if !shouldTest(src) { + continue + } + fs = append(fs, filename) + srcs = append(srcs, src) + } + if len(fs) == 0 { + t.Skip("all files skipped by build tags") + } + testFiles(t, fs, srcs, colDelta, manual) +} + +// shouldTest checks build tags in src and returns whether the file +// should be tested according to the tags. +func shouldTest(src []byte) bool { + match := func(tag string) bool { + // We only care GOOS, GOARCH, and go version tags. + if slices.Contains(build.Default.ReleaseTags, tag) { + return true + } + return tag == runtime.GOOS || tag == runtime.GOARCH + } + for line := range strings.SplitSeq(string(src), "\n") { + if strings.HasPrefix(line, "package ") { + break + } + if expr, err := constraint.Parse(line); err == nil { + return expr.Eval(match) + } } - testFiles(t, filenames, srcs, colDelta, manual) + return true } diff --git a/src/cmd/compile/internal/types2/compiler_internal.go b/src/cmd/compile/internal/types2/compiler_internal.go index 7b976625ef8cef..f27923ff8eb19c 100644 --- a/src/cmd/compile/internal/types2/compiler_internal.go +++ b/src/cmd/compile/internal/types2/compiler_internal.go @@ -48,3 +48,6 @@ func (s *Signature) RenameResult(results []*syntax.Field, i int) (*Var, *syntax. return obj, n } + +// Comment returns the scope comment, for debugging purposes. +func (s *Scope) Comment() string { return s.comment } diff --git a/src/cmd/compile/internal/types2/const.go b/src/cmd/compile/internal/types2/const.go index b68d72de4d27f4..dc459798c8b0c1 100644 --- a/src/cmd/compile/internal/types2/const.go +++ b/src/cmd/compile/internal/types2/const.go @@ -18,7 +18,7 @@ import ( // For untyped constants, it checks that the value doesn't become // arbitrarily large. func (check *Checker) overflow(x *operand, opPos syntax.Pos) { - assert(x.mode == constant_) + assert(x.mode() == constant_) if x.val.Kind() == constant.Unknown { // TODO(gri) We should report exactly what went wrong. At the @@ -32,8 +32,8 @@ func (check *Checker) overflow(x *operand, opPos syntax.Pos) { // their type after each constant operation. // x.typ cannot be a type parameter (type // parameters cannot be constant types). - if isTyped(x.typ) { - check.representable(x, x.typ.Underlying().(*Basic)) + if isTyped(x.typ()) { + check.representable(x, x.typ().Underlying().(*Basic)) return } @@ -46,6 +46,18 @@ func (check *Checker) overflow(x *operand, opPos syntax.Pos) { } check.errorf(atPos(opPos), InvalidConstVal, "constant %soverflow", op) x.val = constant.MakeUnknown() + return + } + + // String values must not become arbitrarily long (go.dev/issue/78346). + const maxLen = int64(2e9) // cmd/internal/obj.MaxSymSize + if x.val.Kind() == constant.String { + len := constant.StringLen(x.val) + if len > maxLen { + check.errorf(atPos(opPos), InvalidConstVal, "constant string too long (%d bytes > %d bytes)", len, maxLen) + x.val = constant.MakeUnknown() + return + } } } @@ -238,7 +250,7 @@ func (check *Checker) representable(x *operand, typ *Basic) { v, code := check.representation(x, typ) if code != 0 { check.invalidConversion(code, x, typ) - x.mode = invalid + x.invalidate() return } assert(v != nil) @@ -250,10 +262,10 @@ func (check *Checker) representable(x *operand, typ *Basic) { // // If no such representation is possible, it returns a non-zero error code. func (check *Checker) representation(x *operand, typ *Basic) (constant.Value, Code) { - assert(x.mode == constant_) + assert(x.mode() == constant_) v := x.val if !representableConst(x.val, check, typ, &v) { - if isNumeric(x.typ) && isNumeric(typ) { + if isNumeric(x.typ()) && isNumeric(typ) { // numeric conversion : error msg // // integer -> integer : overflows @@ -261,7 +273,7 @@ func (check *Checker) representation(x *operand, typ *Basic) (constant.Value, Co // float -> integer : truncated // float -> float : overflows // - if !isInteger(x.typ) && isInteger(typ) { + if !isInteger(x.typ()) && isInteger(typ) { return nil, TruncatedFloat } else { return nil, NumericOverflow @@ -292,15 +304,15 @@ func (check *Checker) convertUntyped(x *operand, target Type) { t = safeUnderlying(target) } check.invalidConversion(code, x, t) - x.mode = invalid + x.invalidate() return } if val != nil { x.val = val check.updateExprVal(x.expr, val) } - if newType != x.typ { - x.typ = newType + if newType != x.typ() { + x.typ_ = newType check.updateExprType(x.expr, newType, false) } } diff --git a/src/cmd/compile/internal/types2/conversions.go b/src/cmd/compile/internal/types2/conversions.go index d0920d7ef1006d..693ccd4b609454 100644 --- a/src/cmd/compile/internal/types2/conversions.go +++ b/src/cmd/compile/internal/types2/conversions.go @@ -15,7 +15,7 @@ import ( // conversion type-checks the conversion T(x). // The result is in x. func (check *Checker) conversion(x *operand, T Type) { - constArg := x.mode == constant_ + constArg := x.mode() == constant_ constConvertibleTo := func(T Type, val *constant.Value) bool { switch t, _ := T.Underlying().(*Basic); { @@ -23,7 +23,7 @@ func (check *Checker) conversion(x *operand, T Type) { // nothing to do case representableConst(x.val, check, t, val): return true - case isInteger(x.typ) && isString(t): + case isInteger(x.typ()) && isString(t): codepoint := unicode.ReplacementChar if i, ok := constant.Uint64Val(x.val); ok && i <= unicode.MaxRune { codepoint = rune(i) @@ -45,9 +45,9 @@ func (check *Checker) conversion(x *operand, T Type) { // A conversion from an integer constant to an integer type // can only fail if there's overflow. Give a concise error. // (go.dev/issue/63563) - if !ok && isInteger(x.typ) && isInteger(T) { + if !ok && isInteger(x.typ()) && isInteger(T) { check.errorf(x, InvalidConversion, "constant %s overflows %s", x.val, T) - x.mode = invalid + x.invalidate() return } case constArg && isTypeParam(T): @@ -62,11 +62,11 @@ func (check *Checker) conversion(x *operand, T Type) { cause = check.sprintf("%s does not contain specific types", T) return false } - if isString(x.typ) && isBytesOrRunes(u) { + if isString(x.typ()) && isBytesOrRunes(u) { return true } if !constConvertibleTo(u, nil) { - if isInteger(x.typ) && isInteger(u) { + if isInteger(x.typ()) && isInteger(u) { // see comment above on constant conversion cause = check.sprintf("constant %s overflows %s (in %s)", x.val, u, T) } else { @@ -76,11 +76,11 @@ func (check *Checker) conversion(x *operand, T Type) { } return true }) - x.mode = value // type parameters are not constants + x.mode_ = value // type parameters are not constants case x.convertibleTo(check, T, &cause): // non-constant conversion ok = true - x.mode = value + x.mode_ = value } if !ok { @@ -89,14 +89,14 @@ func (check *Checker) conversion(x *operand, T Type) { } else { check.errorf(x, InvalidConversion, "cannot convert %s to type %s", x, T) } - x.mode = invalid + x.invalidate() return } // The conversion argument types are final. For untyped values the // conversion provides the type, per the spec: "A constant may be // given a type explicitly by a constant declaration or conversion,...". - if isUntyped(x.typ) { + if isUntyped(x.typ()) { final := T // - For conversions to interfaces, except for untyped nil arguments // and isTypes2, use the argument's default type. @@ -106,17 +106,17 @@ func (check *Checker) conversion(x *operand, T Type) { // - If !isTypes2, keep untyped nil for untyped nil arguments. // - For constant integer to string conversions, keep the argument type. // (See also the TODO below.) - if isTypes2 && x.typ == Typ[UntypedNil] { + if isTypes2 && x.typ() == Typ[UntypedNil] { // ok } else if isNonTypeParamInterface(T) || constArg && !isConstType(T) || !isTypes2 && x.isNil() { - final = Default(x.typ) // default type of untyped nil is untyped nil - } else if x.mode == constant_ && isInteger(x.typ) && allString(T) { - final = x.typ + final = Default(x.typ()) // default type of untyped nil is untyped nil + } else if x.mode() == constant_ && isInteger(x.typ()) && allString(T) { + final = x.typ() } check.updateExprType(x.expr, final, true) } - x.typ = T + x.typ_ = T } // TODO(gri) convertibleTo checks if T(x) is valid. It assumes that the type @@ -140,7 +140,7 @@ func (x *operand) convertibleTo(check *Checker, T Type, cause *string) bool { } origT := T - V := Unalias(x.typ) + V := Unalias(x.typ()) T = Unalias(T) Vu := V.Underlying() Tu := T.Underlying() @@ -250,7 +250,7 @@ func (x *operand) convertibleTo(check *Checker, T Type, cause *string) bool { if V == nil { return false // no specific types } - x.typ = V.typ + x.typ_ = V.typ return Tp.is(func(T *term) bool { if T == nil { return false // no specific types @@ -268,7 +268,7 @@ func (x *operand) convertibleTo(check *Checker, T Type, cause *string) bool { if V == nil { return false // no specific types } - x.typ = V.typ + x.typ_ = V.typ if !x.convertibleTo(check, T, cause) { errorf("cannot convert %s (in %s) to type %s", V.typ, Vp, origT) return false @@ -281,7 +281,7 @@ func (x *operand) convertibleTo(check *Checker, T Type, cause *string) bool { return false // no specific types } if !x.convertibleTo(check, T.typ, cause) { - errorf("cannot convert %s to type %s (in %s)", x.typ, T.typ, Tp) + errorf("cannot convert %s to type %s (in %s)", x.typ(), T.typ, Tp) return false } return true diff --git a/src/cmd/compile/internal/types2/cycles.go b/src/cmd/compile/internal/types2/cycles.go new file mode 100644 index 00000000000000..c0541be52d9a50 --- /dev/null +++ b/src/cmd/compile/internal/types2/cycles.go @@ -0,0 +1,139 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package types2 + +import "cmd/compile/internal/syntax" + +// directCycles searches for direct cycles among package level type declarations. +// See directCycle for details. +func (check *Checker) directCycles() { + pathIdx := make(map[*TypeName]int) + for _, obj := range check.objList { + if tname, ok := obj.(*TypeName); ok { + check.directCycle(tname, pathIdx) + } + } +} + +// directCycle checks if the declaration of the type given by tname contains a direct cycle. +// A direct cycle exists if the path from tname's declaration's RHS leads from type name to +// type name and eventually ends up on that path again, via regular or alias declarations; +// in other words if there are no type literals (or basic types) on the path, and the path +// doesn't end in an undeclared object. +// If a cycle is detected, a cycle error is reported and the type at the start of the cycle +// is marked as invalid. +// +// The pathIdx map tracks which type names have been processed. An entry can be +// in 1 of 3 states as used in a typical 3-state (white/grey/black) graph marking +// algorithm for cycle detection: +// +// - entry not found: tname has not been seen before (white) +// - value is >= 0 : tname has been seen but is not done (grey); the value is the path index +// - value is < 0 : tname has been seen and is done (black) +// +// When directCycle returns, the pathIdx entries for all type names on the path +// that starts at tname are marked black, regardless of whether there was a cycle. +// This ensures that a type name is traversed only once. +func (check *Checker) directCycle(tname *TypeName, pathIdx map[*TypeName]int) { + if debug && check.conf.Trace { + check.trace(tname.Pos(), "-- check direct cycle for %s", tname) + } + + var path []*TypeName + for { + start, found := pathIdx[tname] + if start < 0 { + // tname is marked black - do not traverse it again. + // (start can only be < 0 if it was found in the first place) + break + } + + if found { + // tname is marked grey - we have a cycle on the path beginning at start. + // Mark tname as invalid. + tname.setType(Typ[Invalid]) + + // collect type names on cycle + var cycle []Object + for _, tname := range path[start:] { + cycle = append(cycle, tname) + } + + check.cycleError(cycle, firstInSrc(cycle)) + break + } + + // tname is marked white - mark it grey and add it to the path. + pathIdx[tname] = len(path) + path = append(path, tname) + + // For direct cycle detection, we don't care about whether we have an alias or not. + // If the associated type is not a name, we're at the end of the path and we're done. + rhs, ok := check.objMap[tname].tdecl.Type.(*syntax.Name) + if !ok { + break + } + + // Determine the RHS type. If it is not found in the package scope, we either + // have an error (which will be reported later), or the type exists elsewhere + // (universe scope, file scope via dot-import) and a cycle is not possible in + // the first place. If it is not a type name, we cannot have a direct cycle + // either. In all these cases we can stop. + tname1, ok := check.pkg.scope.Lookup(rhs.Value).(*TypeName) + if !ok { + break + } + + // Otherwise, continue with the RHS. + tname = tname1 + } + + // Mark all traversed type names black. + // (ensure that pathIdx doesn't contain any grey entries upon returning) + for _, tname := range path { + pathIdx[tname] = -1 + } + + if debug { + for _, i := range pathIdx { + assert(i < 0) + } + } +} + +// isComplete returns whether a type is complete (i.e. up to having an underlying type). +// Incomplete types will panic if [Type.Underlying] is called on them. +func (check *Checker) isComplete(t Type) bool { + var ( + obj Object + rhs Type + ) + switch t := t.(type) { + case *Alias: + obj = t.obj + rhs = t.fromRHS + case *Named: + obj = t.obj + rhs = t.fromRHS + default: + return true + } + + if i, found := check.objPathIdx[obj]; found { + cycle := check.objPath[i:] + check.cycleError(cycle, firstInSrc(cycle)) + return false + } + + // We must walk through names because we permit certain cycles of names. + // Consider: + // + // type A B + // type B [unsafe.Sizeof(A{})]int + // + // starting at B. At the site of A{}, A has no underlying type, and so a + // cycle must be reported. + return check.isComplete(rhs) +} diff --git a/src/cmd/compile/internal/types2/decl.go b/src/cmd/compile/internal/types2/decl.go index 91d2492a532ebe..2028edff0d988d 100644 --- a/src/cmd/compile/internal/types2/decl.go +++ b/src/cmd/compile/internal/types2/decl.go @@ -45,8 +45,7 @@ func pathString(path []Object) string { } // objDecl type-checks the declaration of obj in its respective (file) environment. -// For the meaning of def, see Checker.definedType, in typexpr.go. -func (check *Checker) objDecl(obj Object, def *TypeName) { +func (check *Checker) objDecl(obj Object) { if tracePos { check.pushPos(obj.Pos()) defer func() { @@ -62,120 +61,80 @@ func (check *Checker) objDecl(obj Object, def *TypeName) { if check.indent == 0 { fmt.Println() // empty line between top-level objects for readability } - check.trace(obj.Pos(), "-- checking %s (%s, objPath = %s)", obj, obj.color(), pathString(check.objPath)) + check.trace(obj.Pos(), "-- checking %s (objPath = %s)", obj, pathString(check.objPath)) check.indent++ defer func() { check.indent-- - check.trace(obj.Pos(), "=> %s (%s)", obj, obj.color()) + check.trace(obj.Pos(), "=> %s", obj) }() } - // Checking the declaration of obj means inferring its type - // (and possibly its value, for constants). - // An object's type (and thus the object) may be in one of - // three states which are expressed by colors: + // Checking the declaration of an object means determining its type + // (and also its value for constants). An object (and thus its type) + // may be in 1 of 3 states: // - // - an object whose type is not yet known is painted white (initial color) - // - an object whose type is in the process of being inferred is painted grey - // - an object whose type is fully inferred is painted black + // - not in Checker.objPathIdx and type == nil : type is not yet known (white) + // - in Checker.objPathIdx : type is pending (grey) + // - not in Checker.objPathIdx and type != nil : type is known (black) // - // During type inference, an object's color changes from white to grey - // to black (pre-declared objects are painted black from the start). - // A black object (i.e., its type) can only depend on (refer to) other black - // ones. White and grey objects may depend on white and black objects. - // A dependency on a grey object indicates a cycle which may or may not be - // valid. + // During type-checking, an object changes from white to grey to black. + // Predeclared objects start as black (their type is known without checking). // - // When objects turn grey, they are pushed on the object path (a stack); - // they are popped again when they turn black. Thus, if a grey object (a - // cycle) is encountered, it is on the object path, and all the objects - // it depends on are the remaining objects on that path. Color encoding - // is such that the color value of a grey object indicates the index of - // that object in the object path. - - // During type-checking, white objects may be assigned a type without - // traversing through objDecl; e.g., when initializing constants and - // variables. Update the colors of those objects here (rather than - // everywhere where we set the type) to satisfy the color invariants. - if obj.color() == white && obj.Type() != nil { - obj.setColor(black) - return - } - - switch obj.color() { - case white: - assert(obj.Type() == nil) - // All color values other than white and black are considered grey. - // Because black and white are < grey, all values >= grey are grey. - // Use those values to encode the object's index into the object path. - obj.setColor(grey + color(check.push(obj))) - defer func() { - check.pop().setColor(black) - }() - - case black: - assert(obj.Type() != nil) - return - - default: - // Color values other than white or black are considered grey. - fallthrough - - case grey: - // We have a (possibly invalid) cycle. - // In the existing code, this is marked by a non-nil type - // for the object except for constants and variables whose - // type may be non-nil (known), or nil if it depends on the - // not-yet known initialization value. - // In the former case, set the type to Typ[Invalid] because - // we have an initialization cycle. The cycle error will be - // reported later, when determining initialization order. - // TODO(gri) Report cycle here and simplify initialization - // order code. + // A black object may only depend on (refer to) to other black objects. White + // and grey objects may depend on white or black objects. A dependency on a + // grey object indicates a (possibly invalid) cycle. + // + // When an object is marked grey, it is pushed onto the object path (a stack) + // and its index in the path is recorded in the path index map. It is popped + // and removed from the map when its type is determined (and marked black). + + // If this object is grey, we have a (possibly invalid) cycle. This is signaled + // by a non-nil type for the object, except for constants and variables whose + // type may be non-nil (known), or nil if it depends on a not-yet known + // initialization value. + // + // In the former case, set the type to Typ[Invalid] because we have an + // initialization cycle. The cycle error will be reported later, when + // determining initialization order. + // + // TODO(gri) Report cycle here and simplify initialization order code. + if _, ok := check.objPathIdx[obj]; ok { switch obj := obj.(type) { - case *Const: - if !check.validCycle(obj) || obj.typ == nil { - obj.typ = Typ[Invalid] - } - - case *Var: - if !check.validCycle(obj) || obj.typ == nil { - obj.typ = Typ[Invalid] + case *Const, *Var: + if !check.validCycle(obj) || obj.Type() == nil { + obj.setType(Typ[Invalid]) } - case *TypeName: if !check.validCycle(obj) { - // break cycle - // (without this, calling underlying() - // below may lead to an endless loop - // if we have a cycle for a defined - // (*Named) type) - obj.typ = Typ[Invalid] + obj.setType(Typ[Invalid]) } - case *Func: if !check.validCycle(obj) { - // Don't set obj.typ to Typ[Invalid] here - // because plenty of code type-asserts that - // functions have a *Signature type. Grey - // functions have their type set to an empty - // signature which makes it impossible to + // Don't set type to Typ[Invalid]; plenty of code asserts that + // functions have a *Signature type. Instead, leave the type + // as an empty signature, which makes it impossible to // initialize a variable with the function. } - default: panic("unreachable") } + assert(obj.Type() != nil) return } - d := check.objMap[obj] - if d == nil { - check.dump("%v: %s should have been declared", obj.Pos(), obj) - panic("unreachable") + if obj.Type() != nil { // black, meaning it's already type-checked + return } + // white, meaning it must be type-checked + + check.push(obj) + defer check.pop() + + d, ok := check.objMap[obj] + assert(ok) + // save/restore current environment and set up object environment defer func(env environment) { check.environment = env @@ -196,7 +155,7 @@ func (check *Checker) objDecl(obj Object, def *TypeName) { check.varDecl(obj, d.lhs, d.vtyp, d.init) case *TypeName: // invalid recursive types are detected via path - check.typeDecl(obj, d.tdecl, def) + check.typeDecl(obj, d.tdecl) check.collectMethods(obj) // methods can only be added to top-level types case *Func: // functions may be recursive - no need to track dependencies @@ -221,8 +180,8 @@ func (check *Checker) validCycle(obj Object) (valid bool) { } // Count cycle objects. - assert(obj.color() >= grey) - start := obj.color() - grey // index of obj in objPath + start, found := check.objPathIdx[obj] + assert(found) cycle := check.objPath[start:] tparCycle := false // if set, the cycle is through a type parameter list nval := 0 // number of (constant or variable) values in the cycle @@ -240,27 +199,7 @@ loop: tparCycle = true break loop } - - // Determine if the type name is an alias or not. For - // package-level objects, use the object map which - // provides syntactic information (which doesn't rely - // on the order in which the objects are set up). For - // local objects, we can rely on the order, so use - // the object's predicate. - // TODO(gri) It would be less fragile to always access - // the syntactic information. We should consider storing - // this information explicitly in the object. - var alias bool - if check.conf.EnableAlias { - alias = obj.IsAlias() - } else { - if d := check.objMap[obj]; d != nil { - alias = d.tdecl.Alias // package-level object - } else { - alias = obj.IsAlias() // function local object - } - } - if !alias { + if !obj.IsAlias() { ndef++ } case *Func: @@ -316,6 +255,10 @@ func (check *Checker) cycleError(cycle []Object, start int) { // may refer to imported types. See go.dev/issue/50788. // TODO(gri) This functionality is used elsewhere. Factor it out. name := func(obj Object) string { + // include any type arguments in the reported error message + if n := asNamed(obj.Type()); n != nil && n.inst != nil { + return TypeString(n, check.qualifier) + } return packagePrefix(obj.Pkg(), check.qualifier) + obj.Name() } @@ -323,14 +266,8 @@ func (check *Checker) cycleError(cycle []Object, start int) { obj := cycle[start] tname, _ := obj.(*TypeName) if tname != nil { - if check.conf.EnableAlias { - if a, ok := tname.Type().(*Alias); ok { - a.fromRHS = Typ[Invalid] - } - } else { - if tname.IsAlias() { - check.validAlias(tname, Typ[Invalid]) - } + if a, ok := tname.Type().(*Alias); ok { + a.fromRHS = Typ[Invalid] } } @@ -480,7 +417,7 @@ func (check *Checker) isImportedConstraint(typ Type) bool { return u != nil && !u.IsMethodSet() } -func (check *Checker) typeDecl(obj *TypeName, tdecl *syntax.TypeDecl, def *TypeName) { +func (check *Checker) typeDecl(obj *TypeName, tdecl *syntax.TypeDecl) { assert(obj.typ == nil) // Only report a version error if we have not reported one already. @@ -512,41 +449,35 @@ func (check *Checker) typeDecl(obj *TypeName, tdecl *syntax.TypeDecl, def *TypeN versionErr = true } - if check.conf.EnableAlias { - alias := check.newAlias(obj, nil) - setDefType(def, alias) + alias := check.newAlias(obj, nil) - // If we could not type the RHS, set it to invalid. This should - // only ever happen if we panic before setting. - defer func() { - if alias.fromRHS == nil { - alias.fromRHS = Typ[Invalid] - unalias(alias) - } - }() - - // handle type parameters even if not allowed (Alias type is supported) - if tparam0 != nil { - check.openScope(tdecl, "type parameters") - defer check.closeScope() - check.collectTypeParams(&alias.tparams, tdecl.TParamList) + // If we could not type the RHS, set it to invalid. This should + // only ever happen if we panic before setting. + defer func() { + if alias.fromRHS == nil { + alias.fromRHS = Typ[Invalid] + unalias(alias) } + }() - rhs = check.definedType(tdecl.Type, obj) - assert(rhs != nil) + // handle type parameters even if not allowed (Alias type is supported) + if tparam0 != nil { + check.openScope(tdecl, "type parameters") + defer check.closeScope() + check.collectTypeParams(&alias.tparams, tdecl.TParamList) + } - alias.fromRHS = rhs - unalias(alias) // populate alias.actual - } else { - if !versionErr && tparam0 != nil { - check.error(tdecl, UnsupportedFeature, "generic type alias requires GODEBUG=gotypesalias=1 or unset") - versionErr = true - } + rhs = check.declaredType(tdecl.Type, obj) + assert(rhs != nil) + alias.fromRHS = rhs - check.brokenAlias(obj) - rhs = check.typ(tdecl.Type) - check.validAlias(obj, rhs) + // spec: In an alias declaration the given type cannot be a type parameter declared in the same declaration." + // (see also go.dev/issue/75884, go.dev/issue/#75885) + if tpar, ok := rhs.(*TypeParam); ok && alias.tparams != nil && slices.Index(alias.tparams.list(), tpar) >= 0 { + check.error(tdecl.Type, MisplacedTypeParam, "cannot use type parameter declared in alias declaration as RHS") + alias.fromRHS = Typ[Invalid] } + return } @@ -556,27 +487,13 @@ func (check *Checker) typeDecl(obj *TypeName, tdecl *syntax.TypeDecl, def *TypeN } named := check.newNamed(obj, nil, nil) - setDefType(def, named) - - // The RHS of a named N can be nil if, for example, N is defined as a cycle of aliases with - // gotypesalias=0. Consider: - // - // type D N // N.unpack() will panic - // type N A - // type A = N // N.fromRHS is not set before N.unpack(), since A does not call setDefType - // - // There is likely a better way to detect such cases, but it may not be worth the effort. - // Instead, we briefly permit a nil N.fromRHS while type-checking D. - named.allowNilRHS = true - defer (func() { named.allowNilRHS = false })() - if tdecl.TParamList != nil { check.openScope(tdecl, "type parameters") defer check.closeScope() check.collectTypeParams(&named.tparams, tdecl.TParamList) } - rhs = check.definedType(tdecl.Type, obj) + rhs = check.declaredType(tdecl.Type, obj) assert(rhs != nil) named.fromRHS = rhs @@ -764,17 +681,14 @@ func (check *Checker) funcDecl(obj *Func, decl *declInfo) { sig := new(Signature) obj.typ = sig // guard against cycles - // Avoid cycle error when referring to method while type-checking the signature. - // This avoids a nuisance in the best case (non-parameterized receiver type) and - // since the method is not a type, we get an error. If we have a parameterized - // receiver type, instantiating the receiver type leads to the instantiation of - // its methods, and we don't want a cycle error in that case. - // TODO(gri) review if this is correct and/or whether we still need this? - saved := obj.color_ - obj.color_ = black fdecl := decl.fdecl check.funcType(sig, fdecl.Recv, fdecl.TParamList, fdecl.Type) - obj.color_ = saved + + if fdecl.Pragma != nil { + if p, ok := fdecl.Pragma.(interface{ Nointerface() bool }); ok && p.Nointerface() { + obj.nointerface = true + } + } // Set the scope's extent to the complete "func (...) { ... }" // so that Scope.Innermost works correctly. @@ -921,10 +835,9 @@ func (check *Checker) declStmt(list []syntax.Decl) { // the innermost containing block." scopePos := s.Name.Pos() check.declare(check.scope, s.Name, obj, scopePos) - // mark and unmark type before calling typeDecl; its type is still nil (see Checker.objDecl) - obj.setColor(grey + color(check.push(obj))) - check.typeDecl(obj, s, nil) - check.pop().setColor(black) + check.push(obj) // mark as grey + check.typeDecl(obj, s) + check.pop() default: check.errorf(s, InvalidSyntaxTree, "unknown syntax.Decl node %T", s) diff --git a/src/cmd/compile/internal/types2/errors.go b/src/cmd/compile/internal/types2/errors.go index 44f2adc7b79f09..e2f5508a1a430c 100644 --- a/src/cmd/compile/internal/types2/errors.go +++ b/src/cmd/compile/internal/types2/errors.go @@ -56,7 +56,7 @@ func (check *Checker) newError(code Code) *error_ { // Subsequent calls to addf provide additional information in the form of additional lines // in the error message (types2) or continuation errors identified by a tab-indented error // message (go/types). -func (err *error_) addf(at poser, format string, args ...interface{}) { +func (err *error_) addf(at poser, format string, args ...any) { err.desc = append(err.desc, errorDesc{atPos(at), err.check.sprintf(format, args...)}) } diff --git a/src/cmd/compile/internal/types2/expr.go b/src/cmd/compile/internal/types2/expr.go index d62b0247578d6e..317453c257308f 100644 --- a/src/cmd/compile/internal/types2/expr.go +++ b/src/cmd/compile/internal/types2/expr.go @@ -23,7 +23,7 @@ are generally of the form: func f(x *operand, e *syntax.Expr, ...) where e is the expression to be checked, and x is the result of the check. -The check performed by f may fail in which case x.mode == invalid, and +The check performed by f may fail in which case x.mode_ == invalid, and related error messages will have been issued by f. If a hint argument is present, it is the composite literal element type @@ -72,7 +72,7 @@ func init() { func (check *Checker) op(m opPredicates, x *operand, op syntax.Operator) bool { if pred := m[op]; pred != nil { - if !pred(x.typ) { + if !pred(x.typ()) { check.errorf(x, UndefinedOp, invalidOp+"operator %s not defined on %s", op, x) return false } @@ -129,7 +129,7 @@ var op2str2 = [...]string{ func (check *Checker) unary(x *operand, e *syntax.Operation) { check.expr(nil, x, e.X) - if x.mode == invalid { + if !x.isValid() { return } @@ -138,30 +138,31 @@ func (check *Checker) unary(x *operand, e *syntax.Operation) { case syntax.And: // spec: "As an exception to the addressability // requirement x may also be a composite literal." - if _, ok := syntax.Unparen(e.X).(*syntax.CompositeLit); !ok && x.mode != variable { + if _, ok := syntax.Unparen(e.X).(*syntax.CompositeLit); !ok && x.mode() != variable { check.errorf(x, UnaddressableOperand, invalidOp+"cannot take address of %s", x) - x.mode = invalid + x.invalidate() return } - x.mode = value - x.typ = &Pointer{base: x.typ} + x.mode_ = value + x.typ_ = &Pointer{base: x.typ()} return case syntax.Recv: - if elem := check.chanElem(x, x, true); elem != nil { - x.mode = commaok - x.typ = elem + // We cannot receive a value with an incomplete type; make sure it's complete. + if elem := check.chanElem(x, x, true); elem != nil && check.isComplete(elem) { + x.mode_ = commaok + x.typ_ = elem check.hasCallOrRecv = true return } - x.mode = invalid + x.invalidate() return case syntax.Tilde: // Provide a better error position and message than what check.op below would do. - if !allInteger(x.typ) { + if !allInteger(x.typ()) { check.error(e, UndefinedOp, "cannot use ~ outside of interface or type constraint") - x.mode = invalid + x.invalidate() return } check.error(e, UndefinedOp, "cannot use ~ outside of interface or type constraint (use ^ for bitwise complement)") @@ -169,18 +170,18 @@ func (check *Checker) unary(x *operand, e *syntax.Operation) { } if !check.op(unaryOpPredicates, x, op) { - x.mode = invalid + x.invalidate() return } - if x.mode == constant_ { + if x.mode() == constant_ { if x.val.Kind() == constant.Unknown { // nothing to do (and don't cause an error below in the overflow check) return } var prec uint - if isUnsigned(x.typ) { - prec = uint(check.conf.sizeof(x.typ) * 8) + if isUnsigned(x.typ()) { + prec = uint(check.conf.sizeof(x.typ()) * 8) } x.val = constant.UnaryOp(op2tok[op], x.val, prec) x.expr = e @@ -188,7 +189,7 @@ func (check *Checker) unary(x *operand, e *syntax.Operation) { return } - x.mode = value + x.mode_ = value // x.typ remains unchanged } @@ -196,7 +197,7 @@ func (check *Checker) unary(x *operand, e *syntax.Operation) { // or send to x (recv == false) operation. If the operation is not valid, chanElem // reports an error and returns nil. func (check *Checker) chanElem(pos poser, x *operand, recv bool) Type { - u, err := commonUnder(x.typ, func(t, u Type) *typeError { + u, err := commonUnder(x.typ(), func(t, u Type) *typeError { if u == nil { return typeErrorf("no specific channel type") } @@ -219,14 +220,14 @@ func (check *Checker) chanElem(pos poser, x *operand, recv bool) Type { cause := err.format(check) if recv { - if isTypeParam(x.typ) { + if isTypeParam(x.typ()) { check.errorf(pos, InvalidReceive, invalidOp+"cannot receive from %s: %s", x, cause) } else { // In this case, only the non-channel and send-only channel error are possible. check.errorf(pos, InvalidReceive, invalidOp+"cannot receive from %s %s", cause, x) } } else { - if isTypeParam(x.typ) { + if isTypeParam(x.typ()) { check.errorf(pos, InvalidSend, invalidOp+"cannot send to %s: %s", x, cause) } else { // In this case, only the non-channel and receive-only channel error are possible. @@ -386,7 +387,7 @@ func (check *Checker) updateExprType(x syntax.Expr, typ Type, final bool) { // If x is a constant, it must be representable as a value of typ. c := operand{old.mode, x, old.typ, old.val, 0} check.convertUntyped(&c, typ) - if c.mode == invalid { + if !c.isValid() { return } } @@ -410,21 +411,21 @@ func (check *Checker) updateExprVal(x syntax.Expr, val constant.Value) { // If x is a constant operand, the returned constant.Value will be the // representation of x in this context. func (check *Checker) implicitTypeAndValue(x *operand, target Type) (Type, constant.Value, Code) { - if x.mode == invalid || isTyped(x.typ) || !isValid(target) { - return x.typ, nil, 0 + if !x.isValid() || isTyped(x.typ()) || !isValid(target) { + return x.typ(), nil, 0 } // x is untyped if isUntyped(target) { // both x and target are untyped - if m := maxType(x.typ, target); m != nil { + if m := maxType(x.typ(), target); m != nil { return m, nil, 0 } return nil, nil, InvalidUntypedConversion } if x.isNil() { - assert(isUntyped(x.typ)) + assert(isUntyped(x.typ())) if hasNil(target) { return target, nil, 0 } @@ -433,7 +434,7 @@ func (check *Checker) implicitTypeAndValue(x *operand, target Type) (Type, const switch u := target.Underlying().(type) { case *Basic: - if x.mode == constant_ { + if x.mode() == constant_ { v, code := check.representation(x, u) if code != 0 { return nil, nil, code @@ -444,7 +445,7 @@ func (check *Checker) implicitTypeAndValue(x *operand, target Type) (Type, const // result of comparisons (untyped bool), intermediate // (delayed-checked) rhs operands of shifts, and as // the value nil. - switch x.typ.(*Basic).kind { + switch x.typ().(*Basic).kind { case UntypedBool: if !isBoolean(target) { return nil, nil, InvalidUntypedConversion @@ -482,7 +483,7 @@ func (check *Checker) implicitTypeAndValue(x *operand, target Type) (Type, const if !u.Empty() { return nil, nil, InvalidUntypedConversion // cannot assign untyped values to non-empty interfaces } - return Default(x.typ), nil, 0 // default type for nil is nil + return Default(x.typ()), nil, 0 // default type for nil is nil default: return nil, nil, InvalidUntypedConversion } @@ -492,8 +493,8 @@ func (check *Checker) implicitTypeAndValue(x *operand, target Type) (Type, const // If switchCase is true, the operator op is ignored. func (check *Checker) comparison(x, y *operand, op syntax.Operator, switchCase bool) { // Avoid spurious errors if any of the operands has an invalid type (go.dev/issue/54405). - if !isValid(x.typ) || !isValid(y.typ) { - x.mode = invalid + if !isValid(x.typ()) || !isValid(y.typ()) { + x.invalidate() return } @@ -507,16 +508,16 @@ func (check *Checker) comparison(x, y *operand, op syntax.Operator, switchCase b // spec: "In any comparison, the first operand must be assignable // to the type of the second operand, or vice versa." code := MismatchedTypes - ok, _ := x.assignableTo(check, y.typ, nil) + ok, _ := x.assignableTo(check, y.typ(), nil) if !ok { - ok, _ = y.assignableTo(check, x.typ, nil) + ok, _ = y.assignableTo(check, x.typ(), nil) } if !ok { // Report the error on the 2nd operand since we only // know after seeing the 2nd operand whether we have // a type mismatch. errOp = y - cause = check.sprintf("mismatched types %s and %s", x.typ, y.typ) + cause = check.sprintf("mismatched types %s and %s", x.typ(), y.typ()) goto Error } @@ -528,9 +529,9 @@ func (check *Checker) comparison(x, y *operand, op syntax.Operator, switchCase b switch { case x.isNil() || y.isNil(): // Comparison against nil requires that the other operand type has nil. - typ := x.typ + typ := x.typ() if x.isNil() { - typ = y.typ + typ = y.typ() } if !hasNil(typ) { // This case should only be possible for "nil == nil". @@ -541,24 +542,24 @@ func (check *Checker) comparison(x, y *operand, op syntax.Operator, switchCase b goto Error } - case !Comparable(x.typ): + case !Comparable(x.typ()): errOp = x - cause = check.incomparableCause(x.typ) + cause = check.incomparableCause(x.typ()) goto Error - case !Comparable(y.typ): + case !Comparable(y.typ()): errOp = y - cause = check.incomparableCause(y.typ) + cause = check.incomparableCause(y.typ()) goto Error } case syntax.Lss, syntax.Leq, syntax.Gtr, syntax.Geq: // spec: The ordering operators <, <=, >, and >= apply to operands that are ordered." switch { - case !allOrdered(x.typ): + case !allOrdered(x.typ()): errOp = x goto Error - case !allOrdered(y.typ): + case !allOrdered(y.typ()): errOp = y goto Error } @@ -568,39 +569,39 @@ func (check *Checker) comparison(x, y *operand, op syntax.Operator, switchCase b } // comparison is ok - if x.mode == constant_ && y.mode == constant_ { + if x.mode() == constant_ && y.mode() == constant_ { x.val = constant.MakeBool(constant.Compare(x.val, op2tok[op], y.val)) // The operands are never materialized; no need to update // their types. } else { - x.mode = value + x.mode_ = value // The operands have now their final types, which at run- // time will be materialized. Update the expression trees. // If the current types are untyped, the materialized type // is the respective default type. - check.updateExprType(x.expr, Default(x.typ), true) - check.updateExprType(y.expr, Default(y.typ), true) + check.updateExprType(x.expr, Default(x.typ()), true) + check.updateExprType(y.expr, Default(y.typ()), true) } // spec: "Comparison operators compare two operands and yield // an untyped boolean value." - x.typ = Typ[UntypedBool] + x.typ_ = Typ[UntypedBool] return Error: // We have an offending operand errOp and possibly an error cause. if cause == "" { - if isTypeParam(x.typ) || isTypeParam(y.typ) { + if isTypeParam(x.typ()) || isTypeParam(y.typ()) { // TODO(gri) should report the specific type causing the problem, if any - if !isTypeParam(x.typ) { + if !isTypeParam(x.typ()) { errOp = y } - cause = check.sprintf("type parameter %s cannot use operator %s", errOp.typ, op) + cause = check.sprintf("type parameter %s cannot use operator %s", errOp.typ(), op) } else { // catch-all: neither x nor y is a type parameter - what := compositeKind(errOp.typ) + what := compositeKind(errOp.typ()) if what == "" { - what = check.sprintf("%s", errOp.typ) + what = check.sprintf("%s", errOp.typ()) } cause = check.sprintf("operator %s not defined on %s", op, what) } @@ -610,7 +611,7 @@ Error: } else { check.errorf(errOp, code, invalidOp+"%s %s %s (%s)", x.expr, op, y.expr, cause) } - x.mode = invalid + x.invalidate() } // incomparableCause returns a more specific cause why typ is not comparable. @@ -629,17 +630,17 @@ func (check *Checker) shift(x, y *operand, e syntax.Expr, op syntax.Operator) { // TODO(gri) This function seems overly complex. Revisit. var xval constant.Value - if x.mode == constant_ { + if x.mode() == constant_ { xval = constant.ToInt(x.val) } - if allInteger(x.typ) || isUntyped(x.typ) && xval != nil && xval.Kind() == constant.Int { + if allInteger(x.typ()) || isUntyped(x.typ()) && xval != nil && xval.Kind() == constant.Int { // The lhs is of integer type or an untyped constant representable // as an integer. Nothing to do. } else { // shift has no chance check.errorf(x, InvalidShiftOperand, invalidOp+"shifted operand %s must be integer", x) - x.mode = invalid + x.invalidate() return } @@ -649,55 +650,55 @@ func (check *Checker) shift(x, y *operand, e syntax.Expr, op syntax.Operator) { // Check that constants are representable by uint, but do not convert them // (see also go.dev/issue/47243). var yval constant.Value - if y.mode == constant_ { + if y.mode() == constant_ { // Provide a good error message for negative shift counts. yval = constant.ToInt(y.val) // consider -1, 1.0, but not -1.1 if yval.Kind() == constant.Int && constant.Sign(yval) < 0 { check.errorf(y, InvalidShiftCount, invalidOp+"negative shift count %s", y) - x.mode = invalid + x.invalidate() return } - if isUntyped(y.typ) { + if isUntyped(y.typ()) { // Caution: Check for representability here, rather than in the switch // below, because isInteger includes untyped integers (was bug go.dev/issue/43697). check.representable(y, Typ[Uint]) - if y.mode == invalid { - x.mode = invalid + if !y.isValid() { + x.invalidate() return } } } else { // Check that RHS is otherwise at least of integer type. switch { - case allInteger(y.typ): - if !allUnsigned(y.typ) && !check.verifyVersionf(y, go1_13, invalidOp+"signed shift count %s", y) { - x.mode = invalid + case allInteger(y.typ()): + if !allUnsigned(y.typ()) && !check.verifyVersionf(y, go1_13, invalidOp+"signed shift count %s", y) { + x.invalidate() return } - case isUntyped(y.typ): + case isUntyped(y.typ()): // This is incorrect, but preserves pre-existing behavior. // See also go.dev/issue/47410. check.convertUntyped(y, Typ[Uint]) - if y.mode == invalid { - x.mode = invalid + if !y.isValid() { + x.invalidate() return } default: check.errorf(y, InvalidShiftCount, invalidOp+"shift count %s must be integer", y) - x.mode = invalid + x.invalidate() return } } - if x.mode == constant_ { - if y.mode == constant_ { + if x.mode() == constant_ { + if y.mode() == constant_ { // if either x or y has an unknown value, the result is unknown if x.val.Kind() == constant.Unknown || y.val.Kind() == constant.Unknown { x.val = constant.MakeUnknown() // ensure the correct type - see comment below - if !isInteger(x.typ) { - x.typ = Typ[UntypedInt] + if !isInteger(x.typ()) { + x.typ_ = Typ[UntypedInt] } return } @@ -706,15 +707,15 @@ func (check *Checker) shift(x, y *operand, e syntax.Expr, op syntax.Operator) { s, ok := constant.Uint64Val(yval) if !ok || s > shiftBound { check.errorf(y, InvalidShiftCount, invalidOp+"invalid shift count %s", y) - x.mode = invalid + x.invalidate() return } // The lhs is representable as an integer but may not be an integer // (e.g., 2.0, an untyped float) - this can only happen for untyped // non-integer numeric constants. Correct the type so that the shift // result is of integer type. - if !isInteger(x.typ) { - x.typ = Typ[UntypedInt] + if !isInteger(x.typ()) { + x.typ_ = Typ[UntypedInt] } // x is a constant so xval != nil and it must be of Int kind. x.val = constant.Shift(xval, op2tok[op], uint(s)) @@ -724,7 +725,7 @@ func (check *Checker) shift(x, y *operand, e syntax.Expr, op syntax.Operator) { } // non-constant shift with constant lhs - if isUntyped(x.typ) { + if isUntyped(x.typ()) { // spec: "If the left operand of a non-constant shift // expression is an untyped constant, the type of the // constant is what it would be if the shift expression @@ -749,19 +750,19 @@ func (check *Checker) shift(x, y *operand, e syntax.Expr, op syntax.Operator) { check.untyped[x.expr] = info } // keep x's type - x.mode = value + x.mode_ = value return } } // non-constant shift - lhs must be an integer - if !allInteger(x.typ) { + if !allInteger(x.typ()) { check.errorf(x, InvalidShiftOperand, invalidOp+"shifted operand %s must be integer", x) - x.mode = invalid + x.invalidate() return } - x.mode = value + x.mode_ = value } var binaryOpPredicates opPredicates @@ -793,11 +794,11 @@ func (check *Checker) binary(x *operand, e syntax.Expr, lhs, rhs syntax.Expr, op check.expr(nil, x, lhs) check.expr(nil, &y, rhs) - if x.mode == invalid { + if !x.isValid() { return } - if y.mode == invalid { - x.mode = invalid + if !y.isValid() { + x.invalidate() x.expr = y.expr return } @@ -808,7 +809,7 @@ func (check *Checker) binary(x *operand, e syntax.Expr, lhs, rhs syntax.Expr, op } check.matchTypes(x, &y) - if x.mode == invalid { + if !x.isValid() { return } @@ -817,46 +818,46 @@ func (check *Checker) binary(x *operand, e syntax.Expr, lhs, rhs syntax.Expr, op return } - if !Identical(x.typ, y.typ) { + if !Identical(x.typ(), y.typ()) { // only report an error if we have valid types // (otherwise we had an error reported elsewhere already) - if isValid(x.typ) && isValid(y.typ) { + if isValid(x.typ()) && isValid(y.typ()) { if e != nil { - check.errorf(x, MismatchedTypes, invalidOp+"%s (mismatched types %s and %s)", e, x.typ, y.typ) + check.errorf(x, MismatchedTypes, invalidOp+"%s (mismatched types %s and %s)", e, x.typ(), y.typ()) } else { - check.errorf(x, MismatchedTypes, invalidOp+"%s %s= %s (mismatched types %s and %s)", lhs, op, rhs, x.typ, y.typ) + check.errorf(x, MismatchedTypes, invalidOp+"%s %s= %s (mismatched types %s and %s)", lhs, op, rhs, x.typ(), y.typ()) } } - x.mode = invalid + x.invalidate() return } if !check.op(binaryOpPredicates, x, op) { - x.mode = invalid + x.invalidate() return } if op == syntax.Div || op == syntax.Rem { // check for zero divisor - if (x.mode == constant_ || allInteger(x.typ)) && y.mode == constant_ && constant.Sign(y.val) == 0 { + if (x.mode() == constant_ || allInteger(x.typ())) && y.mode() == constant_ && constant.Sign(y.val) == 0 { check.error(&y, DivByZero, invalidOp+"division by zero") - x.mode = invalid + x.invalidate() return } // check for divisor underflow in complex division (see go.dev/issue/20227) - if x.mode == constant_ && y.mode == constant_ && isComplex(x.typ) { + if x.mode() == constant_ && y.mode() == constant_ && isComplex(x.typ()) { re, im := constant.Real(y.val), constant.Imag(y.val) re2, im2 := constant.BinaryOp(re, token.MUL, re), constant.BinaryOp(im, token.MUL, im) if constant.Sign(re2) == 0 && constant.Sign(im2) == 0 { check.error(&y, DivByZero, invalidOp+"division by zero") - x.mode = invalid + x.invalidate() return } } } - if x.mode == constant_ && y.mode == constant_ { + if x.mode() == constant_ && y.mode() == constant_ { // if either x or y has an unknown value, the result is unknown if x.val.Kind() == constant.Unknown || y.val.Kind() == constant.Unknown { x.val = constant.MakeUnknown() @@ -865,7 +866,7 @@ func (check *Checker) binary(x *operand, e syntax.Expr, lhs, rhs syntax.Expr, op } // force integer division for integer operands tok := op2tok[op] - if op == syntax.Div && isInteger(x.typ) { + if op == syntax.Div && isInteger(x.typ()) { tok = token.QUO_ASSIGN } x.val = constant.BinaryOp(x.val, tok, y.val) @@ -874,7 +875,7 @@ func (check *Checker) binary(x *operand, e syntax.Expr, lhs, rhs syntax.Expr, op return } - x.mode = value + x.mode_ = value // x.typ is unchanged } @@ -892,51 +893,51 @@ func (check *Checker) matchTypes(x, y *operand) { // not compatible, we report a type mismatch error. mayConvert := func(x, y *operand) bool { // If both operands are typed, there's no need for an implicit conversion. - if isTyped(x.typ) && isTyped(y.typ) { + if isTyped(x.typ()) && isTyped(y.typ()) { return false } // A numeric type can only convert to another numeric type. - if allNumeric(x.typ) != allNumeric(y.typ) { + if allNumeric(x.typ()) != allNumeric(y.typ()) { return false } // An untyped operand may convert to its default type when paired with an empty interface // TODO(gri) This should only matter for comparisons (the only binary operation that is // valid with interfaces), but in that case the assignability check should take // care of the conversion. Verify and possibly eliminate this extra test. - if isNonTypeParamInterface(x.typ) || isNonTypeParamInterface(y.typ) { + if isNonTypeParamInterface(x.typ()) || isNonTypeParamInterface(y.typ()) { return true } // A boolean type can only convert to another boolean type. - if allBoolean(x.typ) != allBoolean(y.typ) { + if allBoolean(x.typ()) != allBoolean(y.typ()) { return false } // A string type can only convert to another string type. - if allString(x.typ) != allString(y.typ) { + if allString(x.typ()) != allString(y.typ()) { return false } // Untyped nil can only convert to a type that has a nil. if x.isNil() { - return hasNil(y.typ) + return hasNil(y.typ()) } if y.isNil() { - return hasNil(x.typ) + return hasNil(x.typ()) } // An untyped operand cannot convert to a pointer. // TODO(gri) generalize to type parameters - if isPointer(x.typ) || isPointer(y.typ) { + if isPointer(x.typ()) || isPointer(y.typ()) { return false } return true } if mayConvert(x, y) { - check.convertUntyped(x, y.typ) - if x.mode == invalid { + check.convertUntyped(x, y.typ()) + if !x.isValid() { return } - check.convertUntyped(y, x.typ) - if y.mode == invalid { - x.mode = invalid + check.convertUntyped(y, x.typ()) + if !y.isValid() { + x.invalidate() return } } @@ -963,8 +964,10 @@ type target struct { // The result is nil if typ is not a signature. func newTarget(typ Type, desc string) *target { if typ != nil { - if sig, _ := typ.Underlying().(*Signature); sig != nil { - return &target{sig, desc} + if u, _ := commonUnder(typ, nil); u != nil { + if sig, _ := u.(*Signature); sig != nil { + return &target{sig, desc} + } } } return nil @@ -1002,11 +1005,11 @@ func (check *Checker) rawExpr(T *target, x *operand, e syntax.Expr, hint Type, a // from a non-nil target T, nonGeneric reports an error and invalidates x.mode and x.typ. // Otherwise it leaves x alone. func (check *Checker) nonGeneric(T *target, x *operand) { - if x.mode == invalid || x.mode == novalue { + if !x.isValid() || x.mode() == novalue { return } var what string - switch t := x.typ.(type) { + switch t := x.typ().(type) { case *Alias, *Named: if isGeneric(t) { what = "type" @@ -1022,8 +1025,8 @@ func (check *Checker) nonGeneric(T *target, x *operand) { } if what != "" { check.errorf(x.expr, WrongTypeArgCount, "cannot use generic %s %s without instantiation", what, x.expr) - x.mode = invalid - x.typ = Typ[Invalid] + x.invalidate() + x.typ_ = Typ[Invalid] } } @@ -1033,8 +1036,8 @@ func (check *Checker) nonGeneric(T *target, x *operand) { func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Type) exprKind { // make sure x has a valid state in case of bailout // (was go.dev/issue/5770) - x.mode = invalid - x.typ = Typ[Invalid] + x.invalidate() + x.typ_ = Typ[Invalid] switch e := e.(type) { case nil: @@ -1044,7 +1047,7 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty goto Error // error was reported before case *syntax.Name: - check.ident(x, e, nil, false) + check.ident(x, e, false) case *syntax.DotsType: // dots are handled explicitly where they are valid @@ -1056,19 +1059,19 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty goto Error // error reported during parsing } check.basicLit(x, e) - if x.mode == invalid { + if !x.isValid() { goto Error } case *syntax.FuncLit: check.funcLit(x, e) - if x.mode == invalid { + if !x.isValid() { goto Error } case *syntax.CompositeLit: check.compositeLit(x, e, hint) - if x.mode == invalid { + if !x.isValid() { goto Error } @@ -1079,7 +1082,7 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty return kind case *syntax.SelectorExpr: - check.selector(x, e, nil, false) + check.selector(x, e, false) case *syntax.IndexExpr: if check.indexExpr(x, e) { @@ -1088,19 +1091,19 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty } check.funcInst(T, e.Pos(), x, e, true) } - if x.mode == invalid { + if !x.isValid() { goto Error } case *syntax.SliceExpr: check.sliceExpr(x, e) - if x.mode == invalid { + if !x.isValid() { goto Error } case *syntax.AssertExpr: check.expr(nil, x, e.X) - if x.mode == invalid { + if !x.isValid() { goto Error } // x.(type) expressions are encoded via TypeSwitchGuards @@ -1108,11 +1111,11 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty check.error(e, InvalidSyntaxTree, "invalid use of AssertExpr") goto Error } - if isTypeParam(x.typ) { + if isTypeParam(x.typ()) { check.errorf(x, InvalidAssert, invalidOp+"cannot use type assertion on type parameter value %s", x) goto Error } - if _, ok := x.typ.Underlying().(*Interface); !ok { + if _, ok := x.typ().Underlying().(*Interface); !ok { check.errorf(x, InvalidAssert, invalidOp+"%s is not an interface", x) goto Error } @@ -1120,9 +1123,13 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty if !isValid(T) { goto Error } + // We cannot assert to an incomplete type; make sure it's complete. + if !check.isComplete(T) { + goto Error + } check.typeAssertion(e, x, T, false) - x.mode = commaok - x.typ = T + x.mode_ = commaok + x.typ_ = T case *syntax.TypeSwitchGuard: // x.(type) expressions are handled explicitly in type switches @@ -1164,15 +1171,15 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty if e.Op == syntax.Mul { // pointer indirection check.exprOrType(x, e.X, false) - switch x.mode { + switch x.mode() { case invalid: goto Error case typexpr: - check.validVarType(e.X, x.typ) - x.typ = &Pointer{base: x.typ} + check.validVarType(e.X, x.typ()) + x.typ_ = &Pointer{base: x.typ()} default: var base Type - if !underIs(x.typ, func(u Type) bool { + if !underIs(x.typ(), func(u Type) bool { p, _ := u.(*Pointer) if p == nil { check.errorf(x, InvalidIndirection, invalidOp+"cannot indirect %s", x) @@ -1187,14 +1194,18 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty }) { goto Error } - x.mode = variable - x.typ = base + // We cannot dereference a pointer with an incomplete base type; make sure it's complete. + if !check.isComplete(base) { + goto Error + } + x.mode_ = variable + x.typ_ = base } break } check.unary(x, e) - if x.mode == invalid { + if !x.isValid() { goto Error } if e.Op == syntax.Recv { @@ -1206,7 +1217,7 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty // binary expression check.binary(x, e, e.X, e.Y, e.Op) - if x.mode == invalid { + if !x.isValid() { goto Error } @@ -1217,8 +1228,8 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty case *syntax.ArrayType, *syntax.SliceType, *syntax.StructType, *syntax.FuncType, *syntax.InterfaceType, *syntax.MapType, *syntax.ChanType: - x.mode = typexpr - x.typ = check.typ(e) + x.mode_ = typexpr + x.typ_ = check.typ(e) // Note: rawExpr (caller of exprInternal) will call check.recordTypeAndValue // even though check.typ has already called it. This is fine as both // times the same expression and type are recorded. It is also not a @@ -1234,7 +1245,7 @@ func (check *Checker) exprInternal(T *target, x *operand, e syntax.Expr, hint Ty return expression Error: - x.mode = invalid + x.invalidate() x.expr = e return statement // avoid follow-up errors } @@ -1247,7 +1258,7 @@ Error: // represented as an integer (such as 1.0) it is returned as an integer value. // This ensures that constants of different kind but equal value (such as // 1.0 + 0i, 1.0, 1) result in the same value. -func keyVal(x constant.Value) interface{} { +func keyVal(x constant.Value) any { switch x.Kind() { case constant.Complex: f := constant.ToFloat(x) @@ -1284,7 +1295,7 @@ func keyVal(x constant.Value) interface{} { // typeAssertion checks x.(T). The type of x must be an interface. func (check *Checker) typeAssertion(e syntax.Expr, x *operand, T Type, typeSwitch bool) { var cause string - if check.assertableTo(x.typ, T, &cause) { + if check.assertableTo(x.typ(), T, &cause) { return // success } @@ -1293,7 +1304,7 @@ func (check *Checker) typeAssertion(e syntax.Expr, x *operand, T Type, typeSwitc return } - check.errorf(e, ImpossibleAssert, "impossible type assertion: %s\n\t%s does not implement %s %s", e, T, x.typ, cause) + check.errorf(e, ImpossibleAssert, "impossible type assertion: %s\n\t%s does not implement %s %s", e, T, x.typ(), cause) } // expr typechecks expression e and initializes x with the expression value. @@ -1308,8 +1319,8 @@ func (check *Checker) expr(T *target, x *operand, e syntax.Expr) { } // genericExpr is like expr but the result may also be generic. -func (check *Checker) genericExpr(x *operand, e syntax.Expr) { - check.rawExpr(nil, x, e, nil, true) +func (check *Checker) genericExpr(x *operand, e syntax.Expr, hint Type) { + check.rawExpr(nil, x, e, hint, true) check.exclude(x, 1< 0 { + buf.WriteString(", ") + } + buf.WriteString(operandString(x, qf)) + } + buf.WriteByte(']') + arg = buf.String() case syntax.Pos: arg = a.String() case syntax.Expr: diff --git a/src/cmd/compile/internal/types2/hilbert_test.go b/src/cmd/compile/internal/types2/hilbert_test.go index df8a3e7d78af57..6cc0974c3344be 100644 --- a/src/cmd/compile/internal/types2/hilbert_test.go +++ b/src/cmd/compile/internal/types2/hilbert_test.go @@ -68,7 +68,7 @@ type gen struct { bytes.Buffer } -func (g *gen) p(format string, args ...interface{}) { +func (g *gen) p(format string, args ...any) { fmt.Fprintf(&g.Buffer, format, args...) } diff --git a/src/cmd/compile/internal/types2/index.go b/src/cmd/compile/internal/types2/index.go index ca84184d35afed..7be7ca61f884ca 100644 --- a/src/cmd/compile/internal/types2/index.go +++ b/src/cmd/compile/internal/types2/index.go @@ -19,23 +19,23 @@ func (check *Checker) indexExpr(x *operand, e *syntax.IndexExpr) (isFuncInst boo check.exprOrType(x, e.X, true) // x may be generic - switch x.mode { + switch x.mode() { case invalid: check.use(e.Index) return false case typexpr: // type instantiation - x.mode = invalid + x.invalidate() // TODO(gri) here we re-evaluate e.X - try to avoid this - x.typ = check.varType(e) - if isValid(x.typ) { - x.mode = typexpr + x.typ_ = check.varType(e) + if isValid(x.typ()) { + x.mode_ = typexpr } return false case value: - if sig, _ := x.typ.Underlying().(*Signature); sig != nil && sig.TypeParams().Len() > 0 { + if sig, _ := x.typ().Underlying().(*Signature); sig != nil && sig.TypeParams().Len() > 0 { // function instantiation return true } @@ -43,72 +43,94 @@ func (check *Checker) indexExpr(x *operand, e *syntax.IndexExpr) (isFuncInst boo // x should not be generic at this point, but be safe and check check.nonGeneric(nil, x) - if x.mode == invalid { + if !x.isValid() { return false } + // We cannot index on an incomplete type; make sure it's complete. + if !check.isComplete(x.typ()) { + x.invalidate() + return false + } + switch typ := x.typ().Underlying().(type) { + case *Pointer: + // Additionally, if x.typ is a pointer to an array type, indexing implicitly dereferences the value, meaning + // its base type must also be complete. + if !check.isComplete(typ.base) { + x.invalidate() + return false + } + case *Map: + // Lastly, if x.typ is a map type, indexing must produce a value of a complete type, meaning + // its element type must also be complete. + if !check.isComplete(typ.elem) { + x.invalidate() + return false + } + } + // ordinary index expression valid := false length := int64(-1) // valid if >= 0 - switch typ := x.typ.Underlying().(type) { + switch typ := x.typ().Underlying().(type) { case *Basic: if isString(typ) { valid = true - if x.mode == constant_ { - length = int64(len(constant.StringVal(x.val))) + if x.mode() == constant_ { + length = constant.StringLen(x.val) } // an indexed string always yields a byte value // (not a constant) even if the string and the // index are constant - x.mode = value - x.typ = universeByte // use 'byte' name + x.mode_ = value + x.typ_ = universeByte // use 'byte' name } case *Array: valid = true length = typ.len - if x.mode != variable { - x.mode = value + if x.mode() != variable { + x.mode_ = value } - x.typ = typ.elem + x.typ_ = typ.elem case *Pointer: if typ, _ := typ.base.Underlying().(*Array); typ != nil { valid = true length = typ.len - x.mode = variable - x.typ = typ.elem + x.mode_ = variable + x.typ_ = typ.elem } case *Slice: valid = true - x.mode = variable - x.typ = typ.elem + x.mode_ = variable + x.typ_ = typ.elem case *Map: index := check.singleIndex(e) if index == nil { - x.mode = invalid + x.invalidate() return false } var key operand - check.expr(nil, &key, index) + check.genericExpr(&key, index, nil) check.assignment(&key, typ.key, "map index") // ok to continue even if indexing failed - map element type is known - x.mode = mapindex - x.typ = typ.elem + x.mode_ = mapindex + x.typ_ = typ.elem x.expr = e return false case *Interface: - if !isTypeParam(x.typ) { + if !isTypeParam(x.typ()) { break } // TODO(gri) report detailed failure cause for better error messages var key, elem Type // key != nil: we must have all maps mode := variable // non-maps result mode // TODO(gri) factor out closure and use it for non-typeparam cases as well - if underIs(x.typ, func(u Type) bool { + if underIs(x.typ(), func(u Type) bool { l := int64(-1) // valid if >= 0 var k, e Type // k is only set for maps switch t := u.(type) { @@ -120,7 +142,7 @@ func (check *Checker) indexExpr(x *operand, e *syntax.IndexExpr) (isFuncInst boo case *Array: l = t.len e = t.elem - if x.mode != variable { + if x.mode() != variable { mode = value } case *Pointer: @@ -162,44 +184,44 @@ func (check *Checker) indexExpr(x *operand, e *syntax.IndexExpr) (isFuncInst boo if key != nil { index := check.singleIndex(e) if index == nil { - x.mode = invalid + x.invalidate() return false } var k operand - check.expr(nil, &k, index) + check.genericExpr(&k, index, nil) check.assignment(&k, key, "map index") // ok to continue even if indexing failed - map element type is known - x.mode = mapindex - x.typ = elem + x.mode_ = mapindex + x.typ_ = elem x.expr = e return false } // no maps valid = true - x.mode = mode - x.typ = elem + x.mode_ = mode + x.typ_ = elem } } if !valid { check.errorf(e.Pos(), NonSliceableOperand, "cannot index %s", x) check.use(e.Index) - x.mode = invalid + x.invalidate() return false } index := check.singleIndex(e) if index == nil { - x.mode = invalid + x.invalidate() return false } // In pathological (invalid) cases (e.g.: type T1 [][[]T1{}[0][0]]T0) // the element type may be accessed before it's set. Make sure we have // a valid type. - if x.typ == nil { - x.typ = Typ[Invalid] + if x.typ() == nil { + x.typ_ = Typ[Invalid] } check.index(index, length) @@ -208,7 +230,7 @@ func (check *Checker) indexExpr(x *operand, e *syntax.IndexExpr) (isFuncInst boo func (check *Checker) sliceExpr(x *operand, e *syntax.SliceExpr) { check.expr(nil, x, e.X) - if x.mode == invalid { + if !x.isValid() { check.use(e.Index[:]...) return } @@ -216,9 +238,9 @@ func (check *Checker) sliceExpr(x *operand, e *syntax.SliceExpr) { // determine common underlying type cu var ct, cu Type // type and respective common underlying type var hasString bool - for t, u := range typeset(x.typ) { + for t, u := range typeset(x.typ()) { if u == nil { - check.errorf(x, NonSliceableOperand, "cannot slice %s: no specific type in %s", x, x.typ) + check.errorf(x, NonSliceableOperand, "cannot slice %s: no specific type in %s", x, x.typ()) cu = nil break } @@ -246,17 +268,25 @@ func (check *Checker) sliceExpr(x *operand, e *syntax.SliceExpr) { // If we saw a string, proceed with string type, // but don't go from untyped string to string. cu = Typ[String] - if !isTypeParam(x.typ) { - cu = x.typ.Underlying() // untyped string remains untyped + if !isTypeParam(x.typ()) { + cu = x.typ().Underlying() // untyped string remains untyped } } + // Note that we don't permit slice expressions where x is a type expression, so we don't check for that here. + // However, if x.typ is a pointer to an array type, slicing implicitly dereferences the value, meaning + // its base type must also be complete. + if p, ok := x.typ().Underlying().(*Pointer); ok && !check.isComplete(p.base) { + x.invalidate() + return + } + valid := false length := int64(-1) // valid if >= 0 switch u := cu.(type) { case nil: // error reported above - x.mode = invalid + x.invalidate() return case *Basic: @@ -267,35 +297,35 @@ func (check *Checker) sliceExpr(x *operand, e *syntax.SliceExpr) { at = e // e.Index[2] should be present but be careful } check.error(at, InvalidSliceExpr, invalidOp+"3-index slice of string") - x.mode = invalid + x.invalidate() return } valid = true - if x.mode == constant_ { - length = int64(len(constant.StringVal(x.val))) + if x.mode() == constant_ { + length = constant.StringLen(x.val) } // spec: "For untyped string operands the result // is a non-constant value of type string." - if isUntyped(x.typ) { - x.typ = Typ[String] + if isUntyped(x.typ()) { + x.typ_ = Typ[String] } } case *Array: valid = true length = u.len - if x.mode != variable { + if x.mode() != variable { check.errorf(x, NonSliceableOperand, "cannot slice unaddressable value %s", x) - x.mode = invalid + x.invalidate() return } - x.typ = &Slice{elem: u.elem} + x.typ_ = &Slice{elem: u.elem} case *Pointer: if u, _ := u.base.Underlying().(*Array); u != nil { valid = true length = u.len - x.typ = &Slice{elem: u.elem} + x.typ_ = &Slice{elem: u.elem} } case *Slice: @@ -305,16 +335,16 @@ func (check *Checker) sliceExpr(x *operand, e *syntax.SliceExpr) { if !valid { check.errorf(x, NonSliceableOperand, "cannot slice %s", x) - x.mode = invalid + x.invalidate() return } - x.mode = value + x.mode_ = value // spec: "Only the first index may be omitted; it defaults to 0." if e.Full && (e.Index[1] == nil || e.Index[2] == nil) { check.error(e, InvalidSyntaxTree, "2nd and 3rd index required in 3-index slice") - x.mode = invalid + x.invalidate() return } @@ -397,8 +427,8 @@ func (check *Checker) index(index syntax.Expr, max int64) (typ Type, val int64) return } - if x.mode != constant_ { - return x.typ, -1 + if x.mode() != constant_ { + return x.typ(), -1 } if x.val.Kind() == constant.Unknown { @@ -413,7 +443,7 @@ func (check *Checker) index(index syntax.Expr, max int64) (typ Type, val int64) } // 0 <= v [ && v < max ] - return x.typ, v + return x.typ(), v } // isValidIndex checks whether operand x satisfies the criteria for integer @@ -421,23 +451,23 @@ func (check *Checker) index(index syntax.Expr, max int64) (typ Type, val int64) // If the operand is not valid, an error is reported (using what as context) // and the result is false. func (check *Checker) isValidIndex(x *operand, code Code, what string, allowNegative bool) bool { - if x.mode == invalid { + if !x.isValid() { return false } // spec: "a constant index that is untyped is given type int" check.convertUntyped(x, Typ[Int]) - if x.mode == invalid { + if !x.isValid() { return false } // spec: "the index x must be of integer type or an untyped constant" - if !allInteger(x.typ) { + if !allInteger(x.typ()) { check.errorf(x, code, invalidArg+"%s %s must be integer", what, x) return false } - if x.mode == constant_ { + if x.mode() == constant_ { // spec: "a constant index must be non-negative ..." if !allowNegative && constant.Sign(x.val) < 0 { check.errorf(x, code, invalidArg+"%s %s must not be negative", what, x) diff --git a/src/cmd/compile/internal/types2/infer.go b/src/cmd/compile/internal/types2/infer.go index 996f6a51090585..1529d111714f7d 100644 --- a/src/cmd/compile/internal/types2/infer.go +++ b/src/cmd/compile/internal/types2/infer.go @@ -62,7 +62,7 @@ func (check *Checker) infer(pos syntax.Pos, tparams []*TypeParam, targs []Type, // If we have invalid (ordinary) arguments, an error was reported before. // Avoid additional inference errors and exit early (go.dev/issue/60434). for _, arg := range args { - if arg.mode == invalid { + if !arg.isValid() { return nil } } @@ -111,7 +111,7 @@ func (check *Checker) infer(pos syntax.Pos, tparams []*TypeParam, targs []Type, // Unify parameter and argument types for generic parameters with typed arguments // and collect the indices of generic parameters with untyped arguments. // Terminology: generic parameter = function parameter with a type-parameterized type - u := newUnifier(tparams, targs, check.allowVersion(go1_21)) + u := newUnifier(check, tparams, targs, check.allowVersion(go1_21)) errorf := func(tpar, targ Type, arg *operand) { // provide a better error message if we can @@ -162,7 +162,7 @@ func (check *Checker) infer(pos syntax.Pos, tparams []*TypeParam, targs []Type, } for i, arg := range args { - if arg.mode == invalid { + if !arg.isValid() { // An error was reported earlier. Ignore this arg // and continue, we may still be able to infer all // targs resulting in fewer follow-on errors. @@ -170,12 +170,12 @@ func (check *Checker) infer(pos syntax.Pos, tparams []*TypeParam, targs []Type, continue } par := params.At(i) - if isParameterized(tparams, par.typ) || isParameterized(tparams, arg.typ) { + if isParameterized(tparams, par.typ) || isParameterized(tparams, arg.typ()) { // Function parameters are always typed. Arguments may be untyped. // Collect the indices of untyped arguments and handle them later. - if isTyped(arg.typ) { - if !u.unify(par.typ, arg.typ, assign) { - errorf(par.typ, arg.typ, arg) + if isTyped(arg.typ()) { + if !u.unify(par.typ, arg.typ(), assign) { + errorf(par.typ, arg.typ(), arg) return nil } } else if _, ok := par.typ.(*TypeParam); ok && !arg.isNil() { @@ -337,11 +337,11 @@ func (check *Checker) infer(pos syntax.Pos, tparams []*TypeParam, targs []Type, } max := maxUntyped[tpar] if max == nil { - max = arg.typ + max = arg.typ() } else { - m := maxType(max, arg.typ) + m := maxType(max, arg.typ()) if m == nil { - err.addf(arg, "mismatched types %s and %s (cannot infer %s)", max, arg.typ, tpar) + err.addf(arg, "mismatched types %s and %s (cannot infer %s)", max, arg.typ(), tpar) return nil } max = m @@ -431,7 +431,7 @@ func (check *Checker) infer(pos syntax.Pos, tparams []*TypeParam, targs []Type, // TODO(gri) Consider doing this in Checker.subst. // Then this would fall out automatically here and also // in instantiation (where we also explicitly nil out - // type parameters). See the *Signature TODO in subst. + // type parameters). if sig, _ := t1.(*Signature); sig != nil && sig.TypeParams().Len() > 0 && !isParameterized(tparams, sig) { sig.tparams = nil } diff --git a/src/cmd/compile/internal/types2/instantiate.go b/src/cmd/compile/internal/types2/instantiate.go index 3c4044ed3c9f2c..4dbd4729993613 100644 --- a/src/cmd/compile/internal/types2/instantiate.go +++ b/src/cmd/compile/internal/types2/instantiate.go @@ -21,7 +21,7 @@ type genericType interface { } // Instantiate instantiates the type orig with the given type arguments targs. -// orig must be an *Alias, *Named, or *Signature type. If there is no error, +// orig must be a generic *Alias, *Named, or *Signature type. If there is no error, // the resulting Type is an instantiated type of the same kind (*Alias, *Named // or *Signature, respectively). // @@ -36,30 +36,37 @@ type genericType interface { // signatures will yield different instances. The use of a shared context does // not guarantee that identical instances are deduplicated in all cases. // -// If validate is set, Instantiate verifies that the number of type arguments -// and parameters match, and that the type arguments satisfy their respective -// type constraints. If verification fails, the resulting error may wrap an -// *ArgumentError indicating which type argument did not satisfy its type parameter -// constraint, and why. +// If validate is set, Instantiate verifies that the type orig is in fact generic, +// that the number of type arguments and parameters match, and that the type arguments +// satisfy their respective type constraints. +// If verification fails, the resulting error may wrap an *ArgumentError indicating +// which type argument did not satisfy its type parameter constraint, and why. // -// If validate is not set, Instantiate does not verify the type argument count -// or whether the type arguments satisfy their constraints. Instantiate is -// guaranteed to not return an error, but may panic. Specifically, for -// *Signature types, Instantiate will panic immediately if the type argument +// If validate is not set, Instantiate does not check if orig is generic, verify the +// type argument count, or check whether the type arguments satisfy their constraints. +// Instantiate is guaranteed to not return an error, but may panic. Specifically, +// for *Signature types, Instantiate will panic immediately if the type argument // count is incorrect; for *Named types, a panic may occur later inside the // *Named API. func Instantiate(ctxt *Context, orig Type, targs []Type, validate bool) (Type, error) { - assert(len(targs) > 0) if ctxt == nil { ctxt = NewContext() } - orig_ := orig.(genericType) // signature of Instantiate must not change for backward-compatibility + orig_, ok := orig.(genericType) // signature of Instantiate must not change for backward-compatibility + if !ok { + panic(sprintf(nil, false, "cannot instantiate non-generic %s: expected *Named, *Alias, or *Signature", orig)) + } + if len(targs) == 0 { + panic(sprintf(nil, false, "cannot instantiate %s: empty type argument list", orig)) + } if validate { tparams := orig_.TypeParams().list() - assert(len(tparams) > 0) + if len(tparams) == 0 { + return nil, fmt.Errorf("cannot instantiate non-generic %s: has no type parameters", orig) + } if len(targs) != len(tparams) { - return nil, fmt.Errorf("got %d type arguments but %s has %d type parameters", len(targs), orig, len(tparams)) + return nil, fmt.Errorf("cannot instantiate %s: got %d type arguments but have %d type parameters", orig, len(targs), len(tparams)) } if i, err := (*Checker)(nil).verify(nopos, tparams, targs, ctxt); err != nil { return nil, &ArgumentError{i, err} @@ -146,6 +153,11 @@ func (check *Checker) instance(pos syntax.Pos, orig genericType, targs []Type, e case *Signature: assert(expanding == nil) // function instances cannot be reached from Named types + // Note that orig may be a generic method on a generic type. In that case, orig + // is an instantiated type. It will not have receiver type parameters, but will + // still have ordinary type parameters. + assert(orig.RecvTypeParams() == nil) + assert(orig.TypeParams() != nil) tparams := orig.TypeParams() // TODO(gri) investigate if this is needed (type argument and parameter count seem to be correct here) @@ -245,7 +257,7 @@ func (check *Checker) implements(V, T Type, constraint bool, cause *string) bool if cause != nil { var detail string if isInterfacePtr(Tu) { - detail = check.sprintf("type %s is pointer to interface, not interface", T) + detail = check.interfacePtrError(T) } else { detail = check.sprintf("%s is not an interface", T) } diff --git a/src/cmd/compile/internal/types2/issues_test.go b/src/cmd/compile/internal/types2/issues_test.go index 8ddb39987a5db0..c51543b40df870 100644 --- a/src/cmd/compile/internal/types2/issues_test.go +++ b/src/cmd/compile/internal/types2/issues_test.go @@ -631,9 +631,13 @@ func TestIssue55030(t *testing.T) { makeSig := func(typ Type, valid bool) { if !valid { defer func() { - if recover() == nil { + r := recover() + if r == nil { panic("NewSignatureType panic expected") } + if _, ok := r.(string); !ok { + panic("NewSignatureType string panic expected") + } }() } par := NewParam(nopos, nil, "", typ) @@ -863,8 +867,7 @@ func TestIssue59944(t *testing.T) { testenv.MustHaveCGO(t) // Methods declared on aliases of cgo types are not permitted. - const src = `// -gotypesalias=1 - + const src = ` package p /* @@ -1011,8 +1014,7 @@ type A = []int type S struct{ A } ` - conf := Config{EnableAlias: true} - pkg := mustTypecheck(src, &conf, nil) + pkg := mustTypecheck(src, nil, nil) S := pkg.Scope().Lookup("S") if S == nil { @@ -1155,8 +1157,7 @@ type ( T A )` - conf := Config{EnableAlias: true} - pkg := mustTypecheck(src, &conf, nil) + pkg := mustTypecheck(src, nil, nil) T := pkg.Scope().Lookup("T").(*TypeName) got := T.String() // this must not panic (was issue) const want = "type p.T struct{}" @@ -1190,3 +1191,34 @@ var _ = T{{x}} t.Fatalf("unexpected type for {x}: %s", tv.Type) } } + +func TestIssue72978(t *testing.T) { + const src = ` +package p + +type ( + genericG[T, U any] struct { x T; y U } + G1 genericG[int, string] + G2 = G1 +) + +func genericF[T, U any]() {} +var f = genericF[string, float64] +` + + pkg := mustTypecheck(src, nil, nil) + for _, name := range []string{"G1", "G2", "f"} { + func() { + typ := pkg.Scope().Lookup(name).Type() + _, err := Instantiate(nil, typ, []Type{Typ[Bool], Typ[Int]}, true) + if err == nil { + t.Errorf("%s[bool, int]: got no error", name) + return + } + want := fmt.Sprintf("cannot instantiate non-generic %s: has no type parameters", typ) + if err.Error() != want { + t.Errorf("%s[bool, int]: got %q, want %q", name, err.Error(), want) + } + }() + } +} diff --git a/src/cmd/compile/internal/types2/literals.go b/src/cmd/compile/internal/types2/literals.go index 5b2dae9b13a726..3cef0362695954 100644 --- a/src/cmd/compile/internal/types2/literals.go +++ b/src/cmd/compile/internal/types2/literals.go @@ -57,18 +57,18 @@ func (check *Checker) basicLit(x *operand, e *syntax.BasicLit) { const limit = 10000 if len(e.Value) > limit { check.errorf(e, InvalidConstVal, "excessively long constant: %s... (%d chars)", e.Value[:10], len(e.Value)) - x.mode = invalid + x.invalidate() return } } x.setConst(e.Kind, e.Value) - if x.mode == invalid { + if !x.isValid() { // The parser already establishes syntactic correctness. // If we reach here it's because of number under-/overflow. // TODO(gri) setConst (and in turn the go/constant package) // should return an error describing the issue. check.errorf(e, InvalidConstVal, "malformed constant: %s", e.Value) - x.mode = invalid + x.invalidate() return } // Ensure that integer values don't overflow (go.dev/issue/54280). @@ -96,11 +96,11 @@ func (check *Checker) funcLit(x *operand, e *syntax.FuncLit) { check.funcBody(decl, "", sig, e.Body, iota) }).describef(e, "func literal") } - x.mode = value - x.typ = sig + x.mode_ = value + x.typ_ = sig } else { check.errorf(e, InvalidSyntaxTree, "invalid function literal %v", e) - x.mode = invalid + x.invalidate() } } @@ -143,15 +143,14 @@ func (check *Checker) compositeLit(x *operand, e *syntax.CompositeLit, hint Type base = typ } + // We cannot create a literal of an incomplete type; make sure it's complete. + if !check.isComplete(base) { + x.invalidate() + return + } + switch u, _ := commonUnder(base, nil); utyp := u.(type) { case *Struct: - // Prevent crash if the struct referred to is not yet set up. - // See analogous comment for *Array. - if utyp.fields == nil { - check.error(e, InvalidTypeCycle, "invalid recursive type") - x.mode = invalid - return - } if len(e.ElemList) == 0 { break } @@ -161,7 +160,7 @@ func (check *Checker) compositeLit(x *operand, e *syntax.CompositeLit, hint Type fields := utyp.fields if _, ok := e.ElemList[0].(*syntax.KeyValueExpr); ok { // all elements must have keys - visited := make([]bool, len(fields)) + visited := make(trie[*Var]) for _, e := range e.ElemList { kv, _ := e.(*syntax.KeyValueExpr) if kv == nil { @@ -171,31 +170,42 @@ func (check *Checker) compositeLit(x *operand, e *syntax.CompositeLit, hint Type key, _ := kv.Key.(*syntax.Name) // do all possible checks early (before exiting due to errors) // so we don't drop information on the floor - check.expr(nil, x, kv.Value) + check.genericExpr(x, kv.Value, nil) if key == nil { check.errorf(kv, InvalidLitField, "invalid field name %s in struct literal", kv.Key) continue } - i := fieldIndex(fields, check.pkg, key.Value, false) - if i < 0 { - var alt Object - if j := fieldIndex(fields, check.pkg, key.Value, true); j >= 0 { - alt = fields[j] - } + obj, index, indirect := lookupFieldOrMethod(utyp, false, check.pkg, key.Value, false) + if obj == nil { + alt, _, _ := lookupFieldOrMethod(utyp, false, check.pkg, key.Value, true) msg := check.lookupError(base, key.Value, alt, true) check.error(kv.Key, MissingLitField, msg) continue } - fld := fields[i] + fld, _ := obj.(*Var) + if fld == nil { + check.errorf(kv.Key, MissingLitField, "%s is not a field", kv.Key) + continue + } + if len(index) > 1 && !check.verifyVersionf(kv.Key, go1_27, "use of promoted field %s in struct literal of type %s", fieldPath(utyp, index), base) { + continue + } + if indirect { + check.errorf(kv.Key, InvalidLitField, "invalid implicit pointer indirection to reach %s", kv.Key) + continue + } check.recordUse(key, fld) etyp := fld.typ check.assignment(x, etyp, "struct literal") - // 0 <= i < len(fields) - if visited[i] { - check.errorf(kv, DuplicateLitField, "duplicate field name %s in struct literal", key.Value) - continue + if alt, n := visited.insert(index, fld); n != 0 { + if fld == alt { + check.errorf(kv, DuplicateLitField, "duplicate field name %s in struct literal", fld.name) + } else if n < len(index) { + check.errorf(kv, DuplicateLitField, "cannot specify promoted field %s and enclosing embedded field %s", fld.name, alt.name) + } else { // n > len(index) + check.errorf(kv, DuplicateLitField, "cannot specify embedded field %s and enclosed promoted field %s", fld.name, alt.name) + } } - visited[i] = true } } else { // no element must have a key @@ -204,7 +214,7 @@ func (check *Checker) compositeLit(x *operand, e *syntax.CompositeLit, hint Type check.error(kv, MixedStructLit, "mixture of field:value and value elements in struct literal") continue } - check.expr(nil, x, e) + check.genericExpr(x, e, nil) if i >= len(fields) { check.errorf(x, InvalidStructLit, "too many values in struct literal of type %s", base) break // cannot continue @@ -219,20 +229,19 @@ func (check *Checker) compositeLit(x *operand, e *syntax.CompositeLit, hint Type check.assignment(x, etyp, "struct literal") } if len(e.ElemList) < len(fields) { - check.errorf(inNode(e, e.Rbrace), InvalidStructLit, "too few values in struct literal of type %s", base) + var hint string + for _, fld := range fields { + if !fld.Exported() && fld.pkg != check.pkg { + hint = " (type has unexported fields - use key:value pairs)" + break + } + } + check.errorf(inNode(e, e.Rbrace), InvalidStructLit, "too few values in struct literal of type %s%s", base, hint) // ok to continue } } case *Array: - // Prevent crash if the array referred to is not yet set up. Was go.dev/issue/18643. - // This is a stop-gap solution. Should use Checker.objPath to report entire - // path starting with earliest declaration in the source. TODO(gri) fix this. - if utyp.elem == nil { - check.error(e, InvalidTypeCycle, "invalid recursive type") - x.mode = invalid - return - } n := check.indexedElts(e.ElemList, utyp.elem, utyp.len) // If we have an array of unknown length (usually [...]T arrays, but also // arrays [n]T where n is invalid) set the length now that we know it and @@ -254,23 +263,9 @@ func (check *Checker) compositeLit(x *operand, e *syntax.CompositeLit, hint Type } case *Slice: - // Prevent crash if the slice referred to is not yet set up. - // See analogous comment for *Array. - if utyp.elem == nil { - check.error(e, InvalidTypeCycle, "invalid recursive type") - x.mode = invalid - return - } check.indexedElts(e.ElemList, utyp.elem, -1) case *Map: - // Prevent crash if the map referred to is not yet set up. - // See analogous comment for *Array. - if utyp.key == nil || utyp.elem == nil { - check.error(e, InvalidTypeCycle, "invalid recursive type") - x.mode = invalid - return - } // If the map key type is an interface (but not a type parameter), // the type of a constant key must be considered when checking for // duplicates. @@ -282,22 +277,22 @@ func (check *Checker) compositeLit(x *operand, e *syntax.CompositeLit, hint Type check.error(e, MissingLitKey, "missing key in map literal") continue } - check.exprWithHint(x, kv.Key, utyp.key) + check.genericExpr(x, kv.Key, utyp.key) check.assignment(x, utyp.key, "map literal") - if x.mode == invalid { + if !x.isValid() { continue } - if x.mode == constant_ { + if x.mode() == constant_ { duplicate := false xkey := keyVal(x.val) if keyIsInterface { for _, vtyp := range visited[xkey] { - if Identical(vtyp, x.typ) { + if Identical(vtyp, x.typ()) { duplicate = true break } } - visited[xkey] = append(visited[xkey], x.typ) + visited[xkey] = append(visited[xkey], x.typ()) } else { _, duplicate = visited[xkey] visited[xkey] = nil @@ -307,7 +302,7 @@ func (check *Checker) compositeLit(x *operand, e *syntax.CompositeLit, hint Type continue } } - check.exprWithHint(x, kv.Value, utyp.elem) + check.genericExpr(x, kv.Value, utyp.elem) check.assignment(x, utyp.elem, "map literal") } @@ -334,13 +329,13 @@ func (check *Checker) compositeLit(x *operand, e *syntax.CompositeLit, hint Type cause = " (no common underlying type)" } check.errorf(e, InvalidLit, "invalid composite literal%s type %s%s", qualifier, typ, cause) - x.mode = invalid + x.invalidate() return } } - x.mode = value - x.typ = typ + x.mode_ = value + x.typ_ = typ } // indexedElts checks the elements (elts) of an array or slice composite literal @@ -384,7 +379,7 @@ func (check *Checker) indexedElts(elts []syntax.Expr, typ Type, length int64) in // check element against composite literal element type var x operand - check.exprWithHint(&x, eval, typ) + check.genericExpr(&x, eval, typ) check.assignment(&x, typ, "array or slice literal") } return max diff --git a/src/cmd/compile/internal/types2/lookup.go b/src/cmd/compile/internal/types2/lookup.go index 3e18db09f5c498..107101fe1ca038 100644 --- a/src/cmd/compile/internal/types2/lookup.go +++ b/src/cmd/compile/internal/types2/lookup.go @@ -6,7 +6,10 @@ package types2 -import "bytes" +import ( + "bytes" + "strings" +) // LookupSelection selects the field or method whose ID is Id(pkg, // name), on a value of type T. If addressable is set, T is the type @@ -387,6 +390,7 @@ func (check *Checker) missingMethod(V, T Type, static bool, equivalent func(x, y ambigSel ptrRecv field + nointerface ) state := ok @@ -447,7 +451,12 @@ func (check *Checker) missingMethod(V, T Type, static bool, equivalent func(x, y // methods may not have a fully set up signature yet if check != nil { - check.objDecl(f, nil) + check.objDecl(f) + } + + if f.nointerface { + state = nointerface + break } if !equivalent(f.typ, m.typ) { @@ -466,7 +475,7 @@ func (check *Checker) missingMethod(V, T Type, static bool, equivalent func(x, y // This method may be formatted in funcString below, so must have a fully // set up signature. if check != nil { - check.objDecl(f, nil) + check.objDecl(f) } } switch state { @@ -509,6 +518,8 @@ func (check *Checker) missingMethod(V, T Type, static bool, equivalent func(x, y *cause = check.sprintf("(method %s has pointer receiver)", m.Name()) case field: *cause = check.sprintf("(%s.%s is a field, not a method)", V, m.Name()) + case nointerface: + *cause = check.sprintf("(%s method is marked 'nointerface')", m.Name()) default: panic("unreachable") } @@ -645,19 +656,6 @@ func concat(list []int, i int) []int { return append(t, i) } -// fieldIndex returns the index for the field with matching package and name, or a value < 0. -// See Object.sameId for the meaning of foldCase. -func fieldIndex(fields []*Var, pkg *Package, name string, foldCase bool) int { - if name != "_" { - for i, f := range fields { - if f.sameId(pkg, name, foldCase) { - return i - } - } - } - return -1 -} - // methodIndex returns the index of and method with matching package and name, or (-1, nil). // See Object.sameId for the meaning of foldCase. func methodIndex(methods []*Func, pkg *Package, name string, foldCase bool) (int, *Func) { @@ -670,3 +668,22 @@ func methodIndex(methods []*Func, pkg *Package, name string, foldCase bool) (int } return -1, nil } + +// Given a (possibly pointer to a) struct type and field index sequence, +// fieldPath returns the dot-separated concatenated field names for the +// given index sequence (e.g. "a.b.c"). +// Use for error reporting etc. where speed is not important. +func fieldPath(typ Type, index []int) string { + var names []string + for _, i := range index { + u, ok := derefStructPtr(typ).Underlying().(*Struct) + if !ok { + // should not happen if index is valid for typ + break + } + fld := u.Field(i) + names = append(names, fld.name) + typ = fld.typ + } + return strings.Join(names, ".") +} diff --git a/src/cmd/compile/internal/types2/mono_test.go b/src/cmd/compile/internal/types2/mono_test.go index c2955a282818b4..989005d18b03b8 100644 --- a/src/cmd/compile/internal/types2/mono_test.go +++ b/src/cmd/compile/internal/types2/mono_test.go @@ -79,4 +79,8 @@ var bads = []string{ "type U[_ any] int; const X = unsafe.Sizeof(func() { type A[T any] U[A[*T]] })", "func F[T any]() { type A = *T; F[A]() }", "type A[T any] struct { _ A[*T] }", + "type T struct{}; func (t T) M[P any]() { t.M[*P]() }", + "type T struct{}; func (t T) A[P any]() { t.B[*P]() }; func (t T) B[Q any]() { t.A[*Q]() }", + "type G[T any] int; func (g G[T]) M[P any]() { g.M[*P]() }", + "type G[T any] int; func (g G[T]) A[P any]() { g.B[*P]() }; func (g G[T]) B[Q any]() { g.A[*Q]() }", } diff --git a/src/cmd/compile/internal/types2/named.go b/src/cmd/compile/internal/types2/named.go index 9f99c568d74dd7..94da87f0d6b3b0 100644 --- a/src/cmd/compile/internal/types2/named.go +++ b/src/cmd/compile/internal/types2/named.go @@ -106,9 +106,7 @@ type Named struct { check *Checker // non-nil during type-checking; nil otherwise obj *TypeName // corresponding declared object for declared types; see above for instantiated types - // flags indicating temporary violations of the invariants for fromRHS and underlying - allowNilRHS bool // same as below, as well as briefly during checking of a type declaration - allowNilUnderlying bool // may be true from creation via [NewNamed] until [Named.SetUnderlying] + allowNilRHS bool // may be true from creation via [NewNamed] until [Named.SetUnderlying] inst *instance // information for instantiated types; nil otherwise @@ -117,6 +115,7 @@ type Named struct { fromRHS Type // the declaration RHS this type is derived from tparams *TypeParamList // type parameters, or nil underlying Type // underlying type, or nil + varSize bool // whether the type has variable size // methods declared for this type (not the method set of this type) // Signatures are type-checked lazily. @@ -148,10 +147,11 @@ type instance struct { // unpacked // └── hasMethods // └── hasUnder +// └── hasVarSize // // That is, descent down the tree is mostly linear (initial through unpacked), except upon -// reaching the leaves (hasMethods and hasUnder). A type may occupy any combination of the -// leaf states at once (they are independent states). +// reaching the leaves (hasMethods, hasUnder, and hasVarSize). A type may occupy any +// combination of the leaf states at once (they are independent states). // // To represent this independence, the set of active states is represented with a bit set. State // transitions are monotonic. Once a state bit is set, it remains set. @@ -159,12 +159,14 @@ type instance struct { // The above constraints significantly narrow the possible bit sets for a named type. With bits // set left-to-right, they are: // -// 0000 | initial -// 1000 | lazyLoaded -// 1100 | unpacked, which implies lazyLoaded -// 1110 | hasMethods, which implies unpacked (which in turn implies lazyLoaded) -// 1101 | hasUnder, which implies unpacked ... -// 1111 | both hasMethods and hasUnder which implies unpacked ... +// 00000 | initial +// 10000 | lazyLoaded +// 11000 | unpacked, which implies lazyLoaded +// 11100 | hasMethods, which implies unpacked (which in turn implies lazyLoaded) +// 11010 | hasUnder, which implies unpacked ... +// 11001 | hasVarSize, which implies unpacked ... +// 11110 | both hasMethods and hasUnder which implies unpacked ... +// ... | (other combinations of leaf states) // // To read the state of a named type, use [Named.stateHas]; to write, use [Named.setState]. type stateMask uint32 @@ -175,6 +177,7 @@ const ( unpacked // methods might be unexpanded (for instances) hasMethods // methods are all expanded (for instances) hasUnder // underlying type is available + hasVarSize // varSize is available ) // NewNamed returns a new named type for the given type name, underlying type, and associated methods. @@ -187,7 +190,6 @@ func NewNamed(obj *TypeName, underlying Type, methods []*Func) *Named { n := (*Checker)(nil).newNamed(obj, underlying, methods) if underlying == nil { n.allowNilRHS = true - n.allowNilUnderlying = true } else { n.SetUnderlying(underlying) } @@ -215,7 +217,7 @@ func NewNamed(obj *TypeName, underlying Type, methods []*Func) *Named { // All others: // Effectively, nothing happens. func (n *Named) unpack() *Named { - if n.stateHas(unpacked | lazyLoaded) { // avoid locking below + if n.stateHas(lazyLoaded | unpacked) { // avoid locking below return n } @@ -225,13 +227,10 @@ func (n *Named) unpack() *Named { defer n.mu.Unlock() // only atomic for consistency; we are holding the mutex - if n.stateHas(unpacked | lazyLoaded) { + if n.stateHas(lazyLoaded | unpacked) { return n } - // underlying comes after unpacking, do not set it - defer (func() { assert(!n.stateHas(hasUnder)) })() - if n.inst != nil { assert(n.fromRHS == nil) // instantiated types are not declared types assert(n.loader == nil) // cannot import an instantiation @@ -243,11 +242,13 @@ func (n *Named) unpack() *Named { n.tparams = orig.tparams if len(orig.methods) == 0 { - n.setState(unpacked | hasMethods) // nothing further to do + n.setState(lazyLoaded | unpacked | hasMethods) // nothing further to do n.inst.ctxt = nil } else { - n.setState(unpacked) + n.setState(lazyLoaded | unpacked) } + // underlying comes after unpacking, do not set it + assert(!n.stateHas(hasUnder)) return n } @@ -266,28 +267,56 @@ func (n *Named) unpack() *Named { n.loader = nil n.tparams = bindTParams(tparams) + n.underlying = underlying n.fromRHS = underlying // for cycle detection n.methods = methods - n.setState(lazyLoaded) // avoid deadlock calling delayed functions + // Careful: A delayed function could need the underlying type of + // the type we are loading, so we must advance to hasUnder to + // avoid a deadlock (see go.dev/issue/80258). + n.setState(lazyLoaded | unpacked | hasMethods | hasUnder) for _, f := range delayed { f() } + return n } - n.setState(unpacked | hasMethods) + // underlying comes after unpacking, do not set it + n.setState(lazyLoaded | unpacked | hasMethods) + assert(!n.stateHas(hasUnder)) return n } // stateHas atomically determines whether the current state includes any active bit in sm. -func (n *Named) stateHas(sm stateMask) bool { - return atomic.LoadUint32(&n.state_)&uint32(sm) != 0 +func (n *Named) stateHas(m stateMask) bool { + return stateMask(atomic.LoadUint32(&n.state_))&m != 0 } // setState atomically sets the current state to include each active bit in sm. // Must only be called while holding n.mu. -func (n *Named) setState(sm stateMask) { - atomic.OrUint32(&n.state_, uint32(sm)) +func (n *Named) setState(m stateMask) { + atomic.OrUint32(&n.state_, uint32(m)) + // verify state transitions + if debug { + m := stateMask(atomic.LoadUint32(&n.state_)) + u := m&unpacked != 0 + // unpacked => lazyLoaded + if u { + assert(m&lazyLoaded != 0) + } + // hasMethods => unpacked + if m&hasMethods != 0 { + assert(u) + } + // hasUnder => unpacked + if m&hasUnder != 0 { + assert(u) + } + // hasVarSize => unpacked + if m&hasVarSize != 0 { + assert(u) + } + } } // newNamed is like NewNamed but with a *Checker receiver. @@ -385,9 +414,13 @@ func (t *Named) NumMethods() int { // Method returns the i'th method of named type t for 0 <= i < t.NumMethods(). // -// For an ordinary or instantiated type t, the receiver base type of this -// method is the named type t. For an uninstantiated generic type t, each -// method receiver is instantiated with its receiver type parameters. +// For an ordinary or instantiated type t, the receiver base type of this method +// is the named type t. The returned Func's Signature will not have receiver +// type parameters. +// +// For an uninstantiated generic type t, each method receiver is instantiated with +// its receiver type parameters. The returned Func's Signature will have the +// receiver type parameters used to instantiate the receiver. // // Methods are numbered deterministically: given the same list of source files // presented to the type checker, or the same sequence of NewMethod and AddMethod @@ -429,62 +462,65 @@ func (t *Named) Method(i int) *Func { } // expandMethod substitutes type arguments in the i'th method for an -// instantiated receiver. +// instantiated receiver. A returned Func's Signature never has +// receiver type parameters. func (t *Named) expandMethod(i int) *Func { - // t.orig.methods is not lazy. origm is the method instantiated with its - // receiver type parameters (the "origin" method). - origm := t.inst.orig.Method(i) - assert(origm != nil) + // t.orig.methods is not lazy. orig is the declared function on t, which + // must have receiver type parameters (since t is generic). + orig := t.inst.orig.Method(i) + assert(orig != nil) check := t.check // Ensure that the original method is type-checked. if check != nil { - check.objDecl(origm, nil) + check.objDecl(orig) } - origSig := origm.typ.(*Signature) - rbase, _ := deref(origSig.Recv().Type()) + oldSig := orig.typ.(*Signature) + rtpars := oldSig.rparams.list() + rtargs := t.inst.targs.list() - // If rbase is t, then origm is already the instantiated method we're looking - // for. In this case, we return origm to preserve the invariant that - // traversing Method->Receiver Type->Method should get back to the same - // method. + // Consider: // - // This occurs if t is instantiated with the receiver type parameters, as in - // the use of m in func (r T[_]) m() { r.m() }. - if rbase == t { - return origm - } + // type T[P any] struct{} + // func (t T[P]) m() { t.m() } + // + // At t.m, m is expanded for T[P] to get a new Func, which must be different from + // the declared Func for the origin method T.m; notably, the Func for t.m lacks + // receiver type parameters, since it is instantiated (as opposed to declared) + // and thus no longer generic. One must not return the origin method here. - sig := origSig // We can only substitute if we have a correspondence between type arguments // and type parameters. This check is necessary in the presence of invalid // code. - if origSig.RecvTypeParams().Len() == t.inst.targs.Len() { - smap := makeSubstMap(origSig.RecvTypeParams().list(), t.inst.targs.list()) + newSig := oldSig + if len(rtpars) == len(rtargs) { + smap := makeSubstMap(rtpars, rtargs) var ctxt *Context if check != nil { ctxt = check.context() } - sig = check.subst(origm.pos, origSig, smap, t, ctxt).(*Signature) + newSig = check.subst(orig.pos, oldSig, smap, t, ctxt).(*Signature) } - if sig == origSig { + if newSig == oldSig { // No substitution occurred, but we still need to create a new signature to // hold the instantiated receiver. - copy := *origSig - sig = © + copy := *oldSig + newSig = © } var rtyp Type - if origm.hasPtrRecv() { + if orig.hasPtrRecv() { rtyp = NewPointer(t) } else { rtyp = t } - sig.recv = cloneVar(origSig.recv, rtyp) - return cloneFunc(origm, sig) + newSig.recv = cloneVar(oldSig.recv, rtyp) + newSig.rparams = nil + + return cloneFunc(orig, newSig) } // SetUnderlying sets the underlying type and marks t as complete. @@ -503,10 +539,9 @@ func (t *Named) SetUnderlying(u Type) { t.fromRHS = u t.allowNilRHS = false - t.setState(unpacked | hasMethods) // TODO(markfreeman): Why hasMethods? + t.setState(lazyLoaded | unpacked | hasMethods) // TODO(markfreeman): Why hasMethods? t.underlying = u - t.allowNilUnderlying = false t.setState(hasUnder) } @@ -545,6 +580,16 @@ func (t *Named) methodIndex(name string, foldCase bool) int { return -1 } +// rhs returns [Named.fromRHS]. +// +// In debug mode, it also asserts that n is in an appropriate state. +func (n *Named) rhs() Type { + if debug { + assert(n.stateHas(lazyLoaded | unpacked)) + } + return n.fromRHS +} + // Underlying returns the [underlying type] of the named type t, resolving all // forwarding declarations. Underlying types are never Named, TypeParam, or // Alias types. @@ -556,14 +601,12 @@ func (n *Named) Underlying() Type { // The gccimporter depends on writing a nil underlying via NewNamed and // immediately reading it back. Rather than putting that in Named.under // and complicating things there, we just check for that special case here. - if n.fromRHS == nil { + if n.rhs() == nil { assert(n.allowNilRHS) - if n.allowNilUnderlying { - return nil - } + return nil } - if !n.stateHas(hasUnder) { + if !n.stateHas(hasUnder) { // minor performance optimization n.resolveUnderlying() } @@ -578,78 +621,70 @@ func (t *Named) String() string { return TypeString(t, nil) } // TODO(rfindley): reorganize the loading and expansion methods under this // heading. -// resolveUnderlying computes the underlying type of n. +// resolveUnderlying computes the underlying type of n. If n already has an +// underlying type, nothing happens. // -// It does so by following RHS type chains. If a type literal is found, each -// named type in the chain has its underlying set to that type. Aliases are -// skipped because their underlying type is not memoized. +// It does so by following RHS type chains for alias and named types. If any +// other type T is found, each named type in the chain has its underlying +// type set to T. Aliases are skipped because their underlying type is +// not memoized. // -// This function also checks for instantiated layout cycles, which are -// reachable only in the case where unpack() expanded an instantiated -// type which became self-referencing without indirection. -// If such a cycle is found, the underlying type is set to Typ[Invalid] -// and a cycle is reported. +// resolveUnderlying assumes that there are no direct cycles; if there were +// any, they were broken (by setting the respective types to invalid) during +// the directCycles check phase. func (n *Named) resolveUnderlying() { - assert(n.stateHas(unpacked)) + assert(n.stateHas(lazyLoaded | unpacked)) + + var seen map[*Named]bool // for debugging only + if debug { + seen = make(map[*Named]bool) + } - var seen map[*Named]int // allocated lazily + var path []*Named var u Type for rhs := Type(n); u == nil; { switch t := rhs.(type) { - case nil: - u = Typ[Invalid] - case *Alias: rhs = unalias(t) case *Named: - if i, ok := seen[t]; ok { - // compute cycle path - path := make([]Object, len(seen)) - for t, j := range seen { - path[j] = t.obj - } - path = path[i:] - // Note: This code may only be called during type checking, - // hence n.check != nil. - n.check.cycleError(path, firstInSrc(path)) - u = Typ[Invalid] - break + if debug { + assert(!seen[t]) + seen[t] = true } - // avoid acquiring the lock if we can + // don't recalculate the underlying if t.stateHas(hasUnder) { u = t.underlying break } - if seen == nil { - seen = make(map[*Named]int) + if debug { + seen[t] = true } - seen[t] = len(seen) + path = append(path, t) t.unpack() - t.mu.Lock() - defer t.mu.Unlock() - - assert(t.fromRHS != nil || t.allowNilRHS) - rhs = t.fromRHS + rhs = t.rhs() + assert(rhs != nil) default: - u = rhs // any type literal works + u = rhs // any type literal or predeclared type works } } - // set underlying for all Named types in the chain - for t := range seen { - // Careful, t.underlying has lock-free readers. Since we might be racing - // another call to resolveUnderlying, we have to avoid overwriting - // t.underlying. Otherwise, the race detector will be tripped. - if t.stateHas(hasUnder) { - continue - } - t.underlying = u - t.setState(hasUnder) + for _, t := range path { + func() { + t.mu.Lock() + defer t.mu.Unlock() + // Careful, t.underlying has lock-free readers. Since we might be racing + // another call to resolveUnderlying, we have to avoid overwriting + // t.underlying. Otherwise, the race detector will be tripped. + if !t.stateHas(hasUnder) { + t.underlying = u + t.setState(hasUnder) + } + }() } } @@ -718,7 +753,7 @@ func (n *Named) expandRHS() (rhs Type) { } assert(!n.stateHas(unpacked)) - assert(n.inst.orig.stateHas(unpacked | lazyLoaded)) + assert(n.inst.orig.stateHas(lazyLoaded | unpacked)) if n.inst.ctxt == nil { n.inst.ctxt = NewContext() @@ -743,7 +778,7 @@ func (n *Named) expandRHS() (rhs Type) { ctxt = check.context() } - rhs = check.subst(n.obj.pos, orig.fromRHS, m, n, ctxt) + rhs = check.subst(n.obj.pos, orig.rhs(), m, n, ctxt) // TODO(markfreeman): Can we handle this in substitution? // If the RHS is an interface, we must set the receiver of interface methods @@ -752,7 +787,7 @@ func (n *Named) expandRHS() (rhs Type) { if methods, copied := replaceRecvType(iface.methods, orig, n); copied { // If the RHS doesn't use type parameters, it may not have been // substituted; we need to craft a new interface first. - if iface == orig.fromRHS { + if iface == orig.rhs() { assert(iface.complete) // otherwise we are copying incomplete data crafted := check.newInterface() diff --git a/src/cmd/compile/internal/types2/named_test.go b/src/cmd/compile/internal/types2/named_test.go index 76093060994807..e241c83b9de2bf 100644 --- a/src/cmd/compile/internal/types2/named_test.go +++ b/src/cmd/compile/internal/types2/named_test.go @@ -123,7 +123,7 @@ package p type T struct{} func (T) a() {} -func (T) c() {} +func (T) c[X any](x X) {} func (T) b() {} ` // should get the same method order each time diff --git a/src/cmd/compile/internal/types2/object.go b/src/cmd/compile/internal/types2/object.go index ce129dbf590f81..a3ab50f7cad406 100644 --- a/src/cmd/compile/internal/types2/object.go +++ b/src/cmd/compile/internal/types2/object.go @@ -42,18 +42,12 @@ type Object interface { // 0 for all other objects (including objects in file scopes). order() uint32 - // color returns the object's color. - color() color - // setType sets the type of the object. setType(Type) // setOrder sets the order number of the object. It must be > 0. setOrder(uint32) - // setColor sets the object's color. It must not be white. - setColor(color color) - // setParent sets the parent scope of the object. setParent(*Scope) @@ -102,41 +96,9 @@ type object struct { name string typ Type order_ uint32 - color_ color scopePos_ syntax.Pos } -// color encodes the color of an object (see Checker.objDecl for details). -type color uint32 - -// An object may be painted in one of three colors. -// Color values other than white or black are considered grey. -const ( - white color = iota - black - grey // must be > white and black -) - -func (c color) String() string { - switch c { - case white: - return "white" - case black: - return "black" - default: - return "grey" - } -} - -// colorFor returns the (initial) color for an object depending on -// whether its type t is known or not. -func colorFor(t Type) color { - if t != nil { - return black - } - return white -} - // Parent returns the scope in which the object is declared. // The result is nil for methods and struct fields. func (obj *object) Parent() *Scope { return obj.parent } @@ -164,13 +126,11 @@ func (obj *object) Id() string { return Id(obj.pkg, obj.name) } func (obj *object) String() string { panic("abstract") } func (obj *object) order() uint32 { return obj.order_ } -func (obj *object) color() color { return obj.color_ } func (obj *object) scopePos() syntax.Pos { return obj.scopePos_ } func (obj *object) setParent(parent *Scope) { obj.parent = parent } func (obj *object) setType(typ Type) { obj.typ = typ } func (obj *object) setOrder(order uint32) { assert(order > 0); obj.order_ = order } -func (obj *object) setColor(color color) { assert(color != white); obj.color_ = color } func (obj *object) setScopePos(pos syntax.Pos) { obj.scopePos_ = pos } func (obj *object) sameId(pkg *Package, name string, foldCase bool) bool { @@ -247,7 +207,7 @@ type PkgName struct { // NewPkgName returns a new PkgName object representing an imported package. // The remaining arguments set the attributes found with all Objects. func NewPkgName(pos syntax.Pos, pkg *Package, name string, imported *Package) *PkgName { - return &PkgName{object{nil, pos, pkg, name, Typ[Invalid], 0, black, nopos}, imported} + return &PkgName{object{nil, pos, pkg, name, Typ[Invalid], 0, nopos}, imported} } // Imported returns the package that was imported. @@ -263,7 +223,7 @@ type Const struct { // NewConst returns a new constant with value val. // The remaining arguments set the attributes found with all Objects. func NewConst(pos syntax.Pos, pkg *Package, name string, typ Type, val constant.Value) *Const { - return &Const{object{nil, pos, pkg, name, typ, 0, colorFor(typ), nopos}, val} + return &Const{object{nil, pos, pkg, name, typ, 0, nopos}, val} } // Val returns the constant's value. @@ -288,7 +248,7 @@ type TypeName struct { // argument for NewNamed, which will set the TypeName's type as a side- // effect. func NewTypeName(pos syntax.Pos, pkg *Package, name string, typ Type) *TypeName { - return &TypeName{object{nil, pos, pkg, name, typ, 0, colorFor(typ), nopos}} + return &TypeName{object{nil, pos, pkg, name, typ, 0, nopos}} } // NewTypeNameLazy returns a new defined type like NewTypeName, but it @@ -402,7 +362,7 @@ func NewField(pos syntax.Pos, pkg *Package, name string, typ Type, embedded bool // newVar returns a new variable. // The arguments set the attributes found with all Objects. func newVar(kind VarKind, pos syntax.Pos, pkg *Package, name string, typ Type) *Var { - return &Var{object: object{nil, pos, pkg, name, typ, 0, colorFor(typ), nopos}, kind: kind} + return &Var{object: object{nil, pos, pkg, name, typ, 0, nopos}, kind: kind} } // Anonymous reports whether the variable is an embedded field. @@ -436,8 +396,9 @@ func (*Var) isDependency() {} // a variable may be a dependency of an initializa // An abstract method may belong to many interfaces due to embedding. type Func struct { object - hasPtrRecv_ bool // only valid for methods that don't have a type yet; use hasPtrRecv() to read origin *Func // if non-nil, the Func from which this one was instantiated + hasPtrRecv_ bool // only valid for methods that don't have a type yet; use hasPtrRecv() to read + nointerface bool } // NewFunc returns a new function with the given signature, representing @@ -452,7 +413,7 @@ func NewFunc(pos syntax.Pos, pkg *Package, name string, sig *Signature) *Func { // as this would violate object.{Type,color} invariants. // TODO(adonovan): propose to disallow NewFunc with nil *Signature. } - return &Func{object{nil, pos, pkg, name, typ, 0, colorFor(typ), nopos}, false, nil} + return &Func{object{nil, pos, pkg, name, typ, 0, nopos}, nil, false, false} } // Signature returns the signature (type) of the function or method. @@ -534,7 +495,7 @@ type Label struct { // NewLabel returns a new label. func NewLabel(pos syntax.Pos, pkg *Package, name string) *Label { - return &Label{object{pos: pos, pkg: pkg, name: name, typ: Typ[Invalid], color_: black}, false} + return &Label{object{pos: pos, pkg: pkg, name: name, typ: Typ[Invalid]}, false} } // A Builtin represents a built-in function. @@ -545,7 +506,7 @@ type Builtin struct { } func newBuiltin(id builtinId) *Builtin { - return &Builtin{object{name: predeclaredFuncs[id].name, typ: Typ[Invalid], color_: black}, id} + return &Builtin{object{name: predeclaredFuncs[id].name, typ: Typ[Invalid]}, id} } // Nil represents the predeclared value nil. @@ -631,7 +592,7 @@ func writeObject(buf *bytes.Buffer, obj Object, qf Qualifier) { } if tname.IsAlias() { buf.WriteString(" =") - if alias, ok := typ.(*Alias); ok { // materialized? (gotypesalias=1) + if alias, ok := typ.(*Alias); ok { // materialized? TODO(gri) Do we still need this (e.g. for byte, rune)? typ = alias.fromRHS } } else if t, _ := typ.(*TypeParam); t != nil { @@ -711,3 +672,52 @@ func writeFuncName(buf *bytes.Buffer, f *Func, qf Qualifier) { } buf.WriteString(f.name) } + +// objectKind returns a description of the object's kind. +func objectKind(obj Object) string { + switch obj := obj.(type) { + case *PkgName: + return "package name" + case *Const: + return "constant" + case *TypeName: + if obj.IsAlias() { + return "type alias" + } else if _, ok := obj.Type().(*TypeParam); ok { + return "type parameter" + } else { + return "defined type" + } + case *Var: + switch obj.Kind() { + case PackageVar: + return "package-level variable" + case LocalVar: + return "local variable" + case RecvVar: + return "receiver" + case ParamVar: + return "parameter" + case ResultVar: + return "result variable" + case FieldVar: + return "struct field" + } + case *Func: + if obj.Signature().Recv() != nil { + return "method" + } else { + return "function" + } + case *Label: + return "label" + case *Builtin: + return "built-in function" + case *Nil: + return "untyped nil" + } + if debug { + panic(fmt.Sprintf("unknown symbol (%T)", obj)) + } + return "unknown symbol" +} diff --git a/src/cmd/compile/internal/types2/object_test.go b/src/cmd/compile/internal/types2/object_test.go index 4f1a653ff3be27..58dfc547dc0e8c 100644 --- a/src/cmd/compile/internal/types2/object_test.go +++ b/src/cmd/compile/internal/types2/object_test.go @@ -80,32 +80,31 @@ func TestEmbeddedMethod(t *testing.T) { } var testObjects = []struct { - src string - obj string - want string - alias bool // needs materialized (and possibly generic) aliases + src string + obj string + want string }{ - {"import \"io\"; var r io.Reader", "r", "var p.r io.Reader", false}, - - {"const c = 1.2", "c", "const p.c untyped float", false}, - {"const c float64 = 3.14", "c", "const p.c float64", false}, - - {"type t struct{f int}", "t", "type p.t struct{f int}", false}, - {"type t func(int)", "t", "type p.t func(int)", false}, - {"type t[P any] struct{f P}", "t", "type p.t[P any] struct{f P}", false}, - {"type t[P any] struct{f P}", "t.P", "type parameter P any", false}, - {"type C interface{m()}; type t[P C] struct{}", "t.P", "type parameter P p.C", false}, - - {"type t = struct{f int}", "t", "type p.t = struct{f int}", false}, - {"type t = func(int)", "t", "type p.t = func(int)", false}, - {"type A = B; type B = int", "A", "type p.A = p.B", true}, - {"type A[P ~int] = struct{}", "A", "type p.A[P ~int] = struct{}", true}, - {"var v int", "v", "var p.v int", false}, - - {"func f(int) string", "f", "func p.f(int) string", false}, - {"func g[P any](x P){}", "g", "func p.g[P any](x P)", false}, - {"func g[P interface{~int}](x P){}", "g.P", "type parameter P interface{~int}", false}, - {"", "any", "type any = interface{}", false}, + {"import \"io\"; var r io.Reader", "r", "var p.r io.Reader"}, + + {"const c = 1.2", "c", "const p.c untyped float"}, + {"const c float64 = 3.14", "c", "const p.c float64"}, + + {"type t struct{f int}", "t", "type p.t struct{f int}"}, + {"type t func(int)", "t", "type p.t func(int)"}, + {"type t[P any] struct{f P}", "t", "type p.t[P any] struct{f P}"}, + {"type t[P any] struct{f P}", "t.P", "type parameter P any"}, + {"type C interface{m()}; type t[P C] struct{}", "t.P", "type parameter P p.C"}, + + {"type t = struct{f int}", "t", "type p.t = struct{f int}"}, + {"type t = func(int)", "t", "type p.t = func(int)"}, + {"type A = B; type B = int", "A", "type p.A = p.B"}, + {"type A[P ~int] = struct{}", "A", "type p.A[P ~int] = struct{}"}, + {"var v int", "v", "var p.v int"}, + + {"func f(int) string", "f", "func p.f(int) string"}, + {"func g[P any](x P){}", "g", "func p.g[P any](x P)"}, + {"func g[P interface{~int}](x P){}", "g.P", "type parameter P interface{~int}"}, + {"", "any", "type any = interface{}"}, } func TestObjectString(t *testing.T) { @@ -114,8 +113,7 @@ func TestObjectString(t *testing.T) { for i, test := range testObjects { t.Run(fmt.Sprint(i), func(t *testing.T) { src := "package p; " + test.src - conf := Config{Error: func(error) {}, Importer: defaultImporter(), EnableAlias: test.alias} - pkg, err := typecheck(src, &conf, nil) + pkg, err := typecheck(src, nil, nil) if err != nil { t.Fatalf("%s: %s", src, err) } diff --git a/src/cmd/compile/internal/types2/operand.go b/src/cmd/compile/internal/types2/operand.go index cd9e9f3575f71a..0e8aa24163cbab 100644 --- a/src/cmd/compile/internal/types2/operand.go +++ b/src/cmd/compile/internal/types2/operand.go @@ -53,11 +53,27 @@ var operandModeString = [...]string{ // for built-in functions. // The zero value of operand is a ready to use invalid operand. type operand struct { - mode operandMode - expr syntax.Expr - typ Type - val constant.Value - id builtinId + mode_ operandMode + expr syntax.Expr + typ_ Type + val constant.Value + id builtinId +} + +func (x *operand) mode() operandMode { + return x.mode_ +} + +func (x *operand) typ() Type { + return x.typ_ +} + +func (x *operand) isValid() bool { + return x.mode() != invalid +} + +func (x *operand) invalidate() { + x.mode_ = invalid } // Pos returns the position of the expression corresponding to x. @@ -109,18 +125,18 @@ func (x *operand) Pos() syntax.Pos { func operandString(x *operand, qf Qualifier) string { // special-case nil if isTypes2 { - if x.mode == nilvalue { - switch x.typ { + if x.mode() == nilvalue { + switch x.typ() { case nil, Typ[Invalid]: return "nil (with invalid type)" case Typ[UntypedNil]: return "nil" default: - return fmt.Sprintf("nil (of type %s)", TypeString(x.typ, qf)) + return fmt.Sprintf("nil (of type %s)", TypeString(x.typ(), qf)) } } } else { // go/types - if x.mode == value && x.typ == Typ[UntypedNil] { + if x.mode() == value && x.typ() == Typ[UntypedNil] { return "nil" } } @@ -131,11 +147,11 @@ func operandString(x *operand, qf Qualifier) string { if x.expr != nil { expr = ExprString(x.expr) } else { - switch x.mode { + switch x.mode() { case builtin: expr = predeclaredFuncs[x.id].name case typexpr: - expr = TypeString(x.typ, qf) + expr = TypeString(x.typ(), qf) case constant_: expr = x.val.String() } @@ -149,14 +165,14 @@ func operandString(x *operand, qf Qualifier) string { // hasType := false - switch x.mode { + switch x.mode() { case invalid, novalue, builtin, typexpr: // no type default: // should have a type, but be cautious (don't crash during printing) - if x.typ != nil { - if isUntyped(x.typ) { - buf.WriteString(x.typ.(*Basic).name) + if x.typ() != nil { + if isUntyped(x.typ()) { + buf.WriteString(x.typ().(*Basic).name) buf.WriteByte(' ') break } @@ -165,10 +181,10 @@ func operandString(x *operand, qf Qualifier) string { } // - buf.WriteString(operandModeString[x.mode]) + buf.WriteString(operandModeString[x.mode()]) // - if x.mode == constant_ { + if x.mode() == constant_ { if s := x.val.String(); s != expr { buf.WriteByte(' ') buf.WriteString(s) @@ -177,9 +193,9 @@ func operandString(x *operand, qf Qualifier) string { // if hasType { - if isValid(x.typ) { + if isValid(x.typ()) { var desc string - if isGeneric(x.typ) { + if isGeneric(x.typ()) { desc = "generic " } @@ -187,14 +203,14 @@ func operandString(x *operand, qf Qualifier) string { // If the type is a renamed basic type, describe the basic type, // as in "int32 type MyInt" for a *Named type MyInt. // If it is a type parameter, describe the constraint instead. - tpar, _ := Unalias(x.typ).(*TypeParam) + tpar, _ := Unalias(x.typ()).(*TypeParam) if tpar == nil { - switch x.typ.(type) { + switch x.typ().(type) { case *Alias, *Named: - what := compositeKind(x.typ) + what := compositeKind(x.typ()) if what == "" { // x.typ must be basic type - what = x.typ.Underlying().(*Basic).name + what = x.typ().Underlying().(*Basic).name } desc += what + " " } @@ -202,7 +218,7 @@ func operandString(x *operand, qf Qualifier) string { // desc is "" or has a trailing space at the end buf.WriteString(" of " + desc + "type ") - WriteType(&buf, x.typ, qf) + WriteType(&buf, x.typ(), qf) if tpar != nil { buf.WriteString(" constrained by ") @@ -281,21 +297,21 @@ func (x *operand) setConst(k syntax.LitKind, lit string) { val := makeFromLiteral(lit, k) if val.Kind() == constant.Unknown { - x.mode = invalid - x.typ = Typ[Invalid] + x.invalidate() + x.typ_ = Typ[Invalid] return } - x.mode = constant_ - x.typ = Typ[kind] + x.mode_ = constant_ + x.typ_ = Typ[kind] x.val = val } // isNil reports whether x is the (untyped) nil value. func (x *operand) isNil() bool { if isTypes2 { - return x.mode == nilvalue + return x.mode() == nilvalue } else { // go/types - return x.mode == value && x.typ == Typ[UntypedNil] + return x.mode() == value && x.typ() == Typ[UntypedNil] } } @@ -306,12 +322,12 @@ func (x *operand) isNil() bool { // if assignableTo is invoked through an exported API call, i.e., when all // methods have been type-checked. func (x *operand) assignableTo(check *Checker, T Type, cause *string) (bool, Code) { - if x.mode == invalid || !isValid(T) { + if !x.isValid() || !isValid(T) { return true, 0 // avoid spurious errors } origT := T - V := Unalias(x.typ) + V := Unalias(x.typ()) T = Unalias(T) // x's type is identical to T @@ -416,7 +432,7 @@ func (x *operand) assignableTo(check *Checker, T Type, cause *string) (bool, Cod } ok, code = x.assignableTo(check, T.typ, cause) if !ok { - errorf("cannot assign %s to %s (in %s)", x.typ, T.typ, Tp) + errorf("cannot assign %s to %s (in %s)", x.typ(), T.typ, Tp) return false } return true @@ -435,7 +451,7 @@ func (x *operand) assignableTo(check *Checker, T Type, cause *string) (bool, Cod if V == nil { return false // no specific types } - x.typ = V.typ + x.typ_ = V.typ ok, code = x.assignableTo(check, T, cause) if !ok { errorf("cannot assign %s (in %s) to %s", V.typ, Vp, origT) diff --git a/src/cmd/compile/internal/types2/range.go b/src/cmd/compile/internal/types2/range.go index 899f5c09911a5e..f7ecbb4c760766 100644 --- a/src/cmd/compile/internal/types2/range.go +++ b/src/cmd/compile/internal/types2/range.go @@ -34,8 +34,8 @@ func (check *Checker) rangeStmt(inner stmtContext, rangeStmt *syntax.ForStmt, no check.hasCallOrRecv = false check.expr(nil, &x, rangeVar) - if isTypes2 && x.mode != invalid && sValue == nil && !check.hasCallOrRecv { - if t, ok := arrayPtrDeref(x.typ.Underlying()).(*Array); ok { + if isTypes2 && x.isValid() && sValue == nil && !check.hasCallOrRecv { + if t, ok := arrayPtrDeref(x.typ().Underlying()).(*Array); ok { for { // Put constant info on the thing inside parentheses. // That's where (*../noder/writer).expr expects it. @@ -50,19 +50,19 @@ func (check *Checker) rangeStmt(inner stmtContext, rangeStmt *syntax.ForStmt, no // (and thus side-effects will not be computed // by the backend). check.record(&operand{ - mode: constant_, - expr: rangeVar, - typ: Typ[Int], - val: constant.MakeInt64(t.len), - id: x.id, + mode_: constant_, + expr: rangeVar, + typ_: Typ[Int], + val: constant.MakeInt64(t.len), + id: x.id, }) } } // determine key/value types var key, val Type - if x.mode != invalid { - k, v, cause, ok := rangeKeyVal(check, x.typ, func(v goVersion) bool { + if x.isValid() { + k, v, cause, ok := rangeKeyVal(check, x.typ(), func(v goVersion) bool { return check.allowVersion(v) }) switch { @@ -92,7 +92,7 @@ func (check *Checker) rangeStmt(inner stmtContext, rangeStmt *syntax.ForStmt, no lhs := [2]syntax.Expr{sKey, sValue} // sKey, sValue may be nil rhs := [2]Type{key, val} // key, val may be nil - rangeOverInt := isInteger(x.typ) + rangeOverInt := isInteger(x.typ()) if isDef { // short variable declaration @@ -133,9 +133,9 @@ func (check *Checker) rangeStmt(inner stmtContext, rangeStmt *syntax.ForStmt, no check.initVar(obj, &x, "range clause") } else { var y operand - y.mode = value + y.mode_ = value y.expr = lhs // we don't have a better rhs expression to use here - y.typ = typ + y.typ_ = typ check.initVar(obj, &y, "assignment") // error is on variable, use "assignment" not "range clause" } assert(obj.typ != nil) @@ -169,14 +169,14 @@ func (check *Checker) rangeStmt(inner stmtContext, rangeStmt *syntax.ForStmt, no // If the assignment succeeded, if x was untyped before, it now // has a type inferred via the assignment. It must be an integer. // (go.dev/issues/67027) - if x.mode != invalid && !isInteger(x.typ) { - check.softErrorf(lhs, InvalidRangeExpr, "cannot use iteration variable of type %s", x.typ) + if x.isValid() && !isInteger(x.typ()) { + check.softErrorf(lhs, InvalidRangeExpr, "cannot use iteration variable of type %s", x.typ()) } } else { var y operand - y.mode = value + y.mode_ = value y.expr = lhs // we don't have a better rhs expression to use here - y.typ = typ + y.typ_ = typ check.assignVar(lhs, nil, &y, "assignment") // error is on variable, use "assignment" not "range clause" } } @@ -240,6 +240,7 @@ func rangeKeyVal(check *Checker, orig Type, allowVersion func(goVersion) bool) ( return bad("requires go1.23 or later") } // check iterator arity + // TODO(gri) error messages could be less verbose (consider rangeStmt error and cause returned here) switch { case typ.Params().Len() != 1: return bad("func must be func(yield func(...) bool): wrong argument count") @@ -266,6 +267,8 @@ func rangeKeyVal(check *Checker, orig Type, allowVersion func(goVersion) bool) ( } else { return bad("func must be func(yield func(...) bool): yield func does not return bool") } + case cb.Variadic(): + return bad(check.sprintf("yield func of type %s cannot be variadic", cb)) } assert(cb.Recv() == nil) // determine key and value types, if any diff --git a/src/cmd/compile/internal/types2/recording.go b/src/cmd/compile/internal/types2/recording.go index 2c83dd2db9df13..53be6a18149ef0 100644 --- a/src/cmd/compile/internal/types2/recording.go +++ b/src/cmd/compile/internal/types2/recording.go @@ -17,25 +17,25 @@ func (check *Checker) record(x *operand) { // TODO(gri) this code can be simplified var typ Type var val constant.Value - switch x.mode { + switch x.mode() { case invalid: typ = Typ[Invalid] case novalue: typ = (*Tuple)(nil) case constant_: - typ = x.typ + typ = x.typ() val = x.val default: - typ = x.typ + typ = x.typ() } assert(x.expr != nil && typ != nil) if isUntyped(typ) { // delay type and value recording until we know the type // or until the end of type checking - check.rememberUntyped(x.expr, false, x.mode, typ.(*Basic), val) + check.rememberUntyped(x.expr, false, x.mode(), typ.(*Basic), val) } else { - check.recordTypeAndValue(x.expr, x.mode, typ, val) + check.recordTypeAndValue(x.expr, x.mode(), typ, val) } } @@ -94,10 +94,10 @@ func (check *Checker) recordBuiltinType(f syntax.Expr, sig *Signature) { func (check *Checker) recordCommaOkTypes(x syntax.Expr, a []*operand) { assert(x != nil) assert(len(a) == 2) - if a[0].mode == invalid { + if a[0].mode() == invalid { return } - t0, t1 := a[0].typ, a[1].typ + t0, t1 := a[0].typ(), a[1].typ() assert(isTyped(t0) && isTyped(t1) && (allBoolean(t1) || t1 == universeError)) if m := check.Types; m != nil { for { @@ -131,6 +131,23 @@ func (check *Checker) recordInstance(expr syntax.Expr, targs []Type, typ Type) { assert(ident != nil) assert(typ != nil) if m := check.Instances; m != nil { + // If this is an instance of a method value/expression, replace the + // receiver for the Signature stored in Instances (go.dev/issue/79657). + if sig, _ := typ.(*Signature); sig != nil && sig.recvold != nil { + copy := *sig + copy.recvold = nil // not strictly necessary + if sig.recvold == methodExprSentinel { + pars := *copy.params + copy.recv = pars.vars[0] + pars.vars = pars.vars[1:] + copy.params = &pars + m[ident] = Instance{newTypeList(targs), ©} + return + } + copy.recv = sig.recvold + m[ident] = Instance{newTypeList(targs), ©} + return + } m[ident] = Instance{newTypeList(targs), typ} } } diff --git a/src/cmd/compile/internal/types2/resolver.go b/src/cmd/compile/internal/types2/resolver.go index 9d8769b96f7c1d..ef9d0ed4ec3ac1 100644 --- a/src/cmd/compile/internal/types2/resolver.go +++ b/src/cmd/compile/internal/types2/resolver.go @@ -415,22 +415,27 @@ func (check *Checker) collectObjects() { case *syntax.FuncDecl: name := s.Name.Value - obj := NewFunc(s.Name.Pos(), pkg, name, nil) - hasTParamError := false // avoid duplicate type parameter errors + obj := NewFunc(s.Name.Pos(), pkg, name, nil) // signature set later + var tparam0 *syntax.Field + if len(s.TParamList) > 0 { + tparam0 = s.TParamList[0] + } if s.Recv == nil { // regular function if name == "init" || name == "main" && pkg.name == "main" { + // init and main functions must not declare type and ordinary parameters or results code := InvalidInitDecl if name == "main" { code = InvalidMainDecl } - if len(s.TParamList) != 0 { - check.softErrorf(s.TParamList[0], code, "func %s must have no type parameters", name) - hasTParamError = true + if tparam0 != nil { + check.softErrorf(tparam0, code, "func %s must have no type parameters", name) } if t := s.Type; len(t.ParamList) != 0 || len(t.ResultList) != 0 { check.softErrorf(s.Name, code, "func %s must have no arguments and no return values", name) } + } else { + _ = tparam0 != nil && check.verifyVersionf(tparam0, go1_18, "type parameter") } // don't declare init functions in the package scope - they are invisible if name == "init" { @@ -452,9 +457,9 @@ func (check *Checker) collectObjects() { if recv, _ := base.(*syntax.Name); recv != nil && name != "_" { methods = append(methods, methodInfo{obj, ptr, recv}) } + _ = tparam0 != nil && check.verifyVersionf(tparam0, go1_27, "generic method") check.recordDef(s.Name, obj) } - _ = len(s.TParamList) != 0 && !hasTParamError && check.verifyVersionf(s.TParamList[0], go1_18, "type parameter") info := &declInfo{file: fileScope, version: check.version, fdecl: s} // Methods are not package-level objects but we still track them in the // object map so that we can handle them like regular functions (if the @@ -508,6 +513,19 @@ func (check *Checker) collectObjects() { } } +// sortObjects sorts package-level objects by source-order for reproducible processing +func (check *Checker) sortObjects() { + check.objList = make([]Object, len(check.objMap)) + i := 0 + for obj := range check.objMap { + check.objList[i] = obj + i++ + } + slices.SortFunc(check.objList, func(a, b Object) int { + return cmp.Compare(a.order(), b.order()) + }) +} + // unpackRecv unpacks a receiver type expression and returns its components: ptr indicates // whether rtyp is a pointer receiver, base is the receiver base type expression stripped // of its type parameters (if any), and tparams are its type parameter names, if any. The @@ -626,31 +644,19 @@ func (check *Checker) resolveBaseTypeName(ptr bool, name *syntax.Name) (ptr_ boo // packageObjects typechecks all package objects, but not function bodies. func (check *Checker) packageObjects() { - // process package objects in source order for reproducible results - objList := make([]Object, len(check.objMap)) - i := 0 - for obj := range check.objMap { - objList[i] = obj - i++ - } - slices.SortFunc(objList, func(a, b Object) int { - return cmp.Compare(a.order(), b.order()) - }) - // add new methods to already type-checked types (from a prior Checker.Files call) - for _, obj := range objList { + for _, obj := range check.objList { if obj, _ := obj.(*TypeName); obj != nil && obj.typ != nil { check.collectMethods(obj) } } - if false && check.conf.EnableAlias { - // With Alias nodes we can process declarations in any order. + if false { + // TODO: determine if we can enable this code now or + // if there are still problems with cycles and + // aliases. // - // TODO(adonovan): unfortunately, Alias nodes - // (GODEBUG=gotypesalias=1) don't entirely resolve - // problems with cycles. For example, in - // GOROOT/test/typeparam/issue50259.go, + // For example, in GOROOT/test/typeparam/issue50259.go, // // type T[_ any] struct{} // type A T[B] @@ -661,11 +667,11 @@ func (check *Checker) packageObjects() { // its Type is Invalid. // // Investigate and reenable this branch. - for _, obj := range objList { - check.objDecl(obj, nil) + for _, obj := range check.objList { + check.objDecl(obj) } } else { - // Without Alias nodes, we process non-alias type declarations first, followed by + // To avoid problems with cycles, process non-alias type declarations first, followed by // alias declarations, and then everything else. This appears to avoid most situations // where the type of an alias is needed before it is available. // There may still be cases where this is not good enough (see also go.dev/issue/25838). @@ -673,12 +679,12 @@ func (check *Checker) packageObjects() { var aliasList []*TypeName var othersList []Object // everything that's not a type // phase 1: non-alias type declarations - for _, obj := range objList { + for _, obj := range check.objList { if tname, _ := obj.(*TypeName); tname != nil { if check.objMap[tname].tdecl.Alias { aliasList = append(aliasList, tname) } else { - check.objDecl(obj, nil) + check.objDecl(obj) } } else { othersList = append(othersList, obj) @@ -686,11 +692,11 @@ func (check *Checker) packageObjects() { } // phase 2: alias type declarations for _, obj := range aliasList { - check.objDecl(obj, nil) + check.objDecl(obj) } // phase 3: all other declarations for _, obj := range othersList { - check.objDecl(obj, nil) + check.objDecl(obj) } } diff --git a/src/cmd/compile/internal/types2/scope.go b/src/cmd/compile/internal/types2/scope.go index 566184df739137..90f52a77376da6 100644 --- a/src/cmd/compile/internal/types2/scope.go +++ b/src/cmd/compile/internal/types2/scope.go @@ -67,21 +67,7 @@ func (s *Scope) Child(i int) *Scope { return s.children[i] } // Lookup returns the object in scope s with the given name if such an // object exists; otherwise the result is nil. -func (s *Scope) Lookup(name string) Object { - obj := resolve(name, s.elems[name]) - // Hijack Lookup for "any": with gotypesalias=1, we want the Universe to - // return an Alias for "any", and with gotypesalias=0 we want to return - // the legacy representation of aliases. - // - // This is rather tricky, but works out after auditing of the usage of - // s.elems. The only external API to access scope elements is Lookup. - // - // TODO: remove this once gotypesalias=0 is no longer supported. - if obj == universeAnyAlias && !aliasAny() { - return universeAnyNoAlias - } - return obj -} +func (s *Scope) Lookup(name string) Object { return resolve(name, s.elems[name]) } // lookupIgnoringCase returns the objects in scope s whose names match // the given name ignoring case. If exported is set, only exported names @@ -217,10 +203,8 @@ func (*lazyObject) Exported() bool { panic("unreachable") } func (*lazyObject) Id() string { panic("unreachable") } func (*lazyObject) String() string { panic("unreachable") } func (*lazyObject) order() uint32 { panic("unreachable") } -func (*lazyObject) color() color { panic("unreachable") } func (*lazyObject) setType(Type) { panic("unreachable") } func (*lazyObject) setOrder(uint32) { panic("unreachable") } -func (*lazyObject) setColor(color color) { panic("unreachable") } func (*lazyObject) setParent(*Scope) { panic("unreachable") } func (*lazyObject) sameId(*Package, string, bool) bool { panic("unreachable") } func (*lazyObject) scopePos() syntax.Pos { panic("unreachable") } diff --git a/src/cmd/compile/internal/types2/selection.go b/src/cmd/compile/internal/types2/selection.go index 2d882b2ee4470a..4e546a8f752198 100644 --- a/src/cmd/compile/internal/types2/selection.go +++ b/src/cmd/compile/internal/types2/selection.go @@ -92,6 +92,7 @@ func (s *Selection) Obj() Object { return s.obj } func (s *Selection) Type() Type { switch s.kind { case MethodVal: + // TODO(mark) Align this with call.go if possible. // The type of x.f is a method with its receiver type set // to the type of x. sig := *s.obj.(*Func).typ.(*Signature) @@ -107,6 +108,7 @@ func (s *Selection) Type() Type { // TODO(gri) Compute this eagerly to avoid allocations. sig := *s.obj.(*Func).typ.(*Signature) arg0 := *sig.recv + sig.recvold = sig.recv // stash receiver (for consistency with call.go) sig.recv = nil arg0.typ = s.recv var params []*Var @@ -117,7 +119,7 @@ func (s *Selection) Type() Type { return &sig } - // In all other cases, the type of x.f is the type of x. + // In all other cases, the type of x.f is the type of f. return s.obj.Type() } diff --git a/src/cmd/compile/internal/types2/signature.go b/src/cmd/compile/internal/types2/signature.go index ea60254fa6832e..7ce640107bb1aa 100644 --- a/src/cmd/compile/internal/types2/signature.go +++ b/src/cmd/compile/internal/types2/signature.go @@ -26,21 +26,40 @@ type Signature struct { tparams *TypeParamList // type parameters from left to right, or nil scope *Scope // function scope for package-local and non-instantiated signatures; nil otherwise recv *Var // nil if not a method + recvold *Var // receiver dropped via method selection; or nil params *Tuple // (incoming) parameters from left to right; or nil results *Tuple // (outgoing) results from left to right; or nil - variadic bool // true if the last parameter's type is of the form ...T (or string, for append built-in only) + variadic bool // true if the last parameter's type is of the form ...T + + // If recvold is the sentinel value [methExpr], then recvold should + // instead be sourced from params[0]. Otherwise, recvold points to + // the receiver of the original method signature from which this + // function signature was cloned via a selector expression. + + // If variadic, the last element of params ordinarily has an + // unnamed Slice type. As a special case, in a call to append, + // it may be string, or a TypeParam T whose typeset ⊇ {string, []byte}. + // It may even be a named []byte type if a client instantiates + // T at such a type. } +// sentinel value for detecting method expressions +var methodExprSentinel = &Var{} + // NewSignatureType creates a new function type for the given receiver, // receiver type parameters, type parameters, parameters, and results. +// // If variadic is set, params must hold at least one parameter and the // last parameter must be an unnamed slice or a type parameter whose // type set has an unnamed slice as common underlying type. -// As a special case, for variadic signatures the last parameter may -// also be a string type, or a type parameter containing a mix of byte -// slices and string types in its type set. -// If recv is non-nil, typeParams must be empty. If recvTypeParams is -// non-empty, recv must be non-nil. +// +// As a special case, to support append([]byte, str...), for variadic +// signatures the last parameter may also be a string type, or a type +// parameter containing a mix of byte slices and string types in its +// type set. It may even be a named []byte slice type resulting from +// substitution of such a type parameter. +// +// If recvTypeParams is non-empty, recv must be non-nil. func NewSignatureType(recv *Var, recvTypeParams, typeParams []*TypeParam, params, results *Tuple, variadic bool) *Signature { if variadic { n := params.Len() @@ -50,21 +69,36 @@ func NewSignatureType(recv *Var, recvTypeParams, typeParams []*TypeParam, params last := params.At(n - 1).typ var S *Slice for t := range typeset(last) { + if t == nil { + break + } var s *Slice if isString(t) { s = NewSlice(universeByte) } else { - s, _ = Unalias(t).(*Slice) // don't accept a named slice type + // Variadic Go functions have a last parameter of type []T, + // suggesting we should reject a named slice type B here. + // + // However, a call to built-in append(slice, x...) + // where x has a TypeParam type [T ~string | ~[]byte], + // has the type func([]byte, T). Since a client may + // instantiate this type at T=B, we must permit + // named slice types, even when this results in a + // signature func([]byte, B) where type B []byte. + // + // (The caller of NewSignatureType may have no way to + // know that it is dealing with the append special case.) + s, _ = t.Underlying().(*Slice) } if S == nil { S = s - } else if !Identical(S, s) { + } else if s == nil || !Identical(S, s) { S = nil break } } if S == nil { - panic(fmt.Sprintf("got %s, want variadic parameter of unnamed slice or string type", last)) + panic(fmt.Sprintf("got %s, want variadic parameter of slice or string type", last)) } } sig := &Signature{recv: recv, params: params, results: results, variadic: variadic} @@ -75,9 +109,6 @@ func NewSignatureType(recv *Var, recvTypeParams, typeParams []*TypeParam, params sig.rparams = bindTParams(recvTypeParams) } if len(typeParams) != 0 { - if recv != nil { - panic("function with type parameters cannot have a receiver") - } sig.tparams = bindTParams(typeParams) } return sig @@ -98,6 +129,7 @@ func (s *Signature) TypeParams() *TypeParamList { return s.tparams } func (s *Signature) RecvTypeParams() *TypeParamList { return s.rparams } // Params returns the parameters of signature s, or nil. +// See [NewSignatureType] for details of variadic functions. func (s *Signature) Params() *Tuple { return s.params } // Results returns the results of signature s, or nil. @@ -131,7 +163,6 @@ func (check *Checker) funcType(sig *Signature, recvPar *syntax.Field, tparams [] // collect and declare function type parameters if tparams != nil { - // The parser will complain about invalid type parameters for methods. check.collectTypeParams(&sig.tparams, tparams) } diff --git a/src/cmd/compile/internal/types2/sizeof_test.go b/src/cmd/compile/internal/types2/sizeof_test.go index 13b96209114de1..68959aa87d73fa 100644 --- a/src/cmd/compile/internal/types2/sizeof_test.go +++ b/src/cmd/compile/internal/types2/sizeof_test.go @@ -15,9 +15,9 @@ func TestSizeof(t *testing.T) { const _64bit = ^uint(0)>>32 != 0 var tests = []struct { - val interface{} // type as a value - _32bit uintptr // size on 32bit platforms - _64bit uintptr // size on 64bit platforms + val any // type as a value + _32bit uintptr // size on 32bit platforms + _64bit uintptr // size on 64bit platforms }{ // Types {Basic{}, 16, 32}, @@ -26,24 +26,24 @@ func TestSizeof(t *testing.T) { {Struct{}, 24, 48}, {Pointer{}, 8, 16}, {Tuple{}, 12, 24}, - {Signature{}, 28, 56}, + {Signature{}, 32, 64}, {Union{}, 12, 24}, {Interface{}, 40, 80}, {Map{}, 16, 32}, {Chan{}, 12, 24}, - {Named{}, 64, 120}, + {Named{}, 68, 128}, {TypeParam{}, 28, 48}, {term{}, 12, 24}, // Objects - {PkgName{}, 60, 96}, - {Const{}, 64, 104}, - {TypeName{}, 56, 88}, - {Var{}, 64, 104}, - {Func{}, 64, 104}, - {Label{}, 60, 96}, - {Builtin{}, 60, 96}, - {Nil{}, 56, 88}, + {PkgName{}, 56, 96}, + {Const{}, 60, 104}, + {TypeName{}, 52, 88}, + {Var{}, 60, 104}, + {Func{}, 60, 104}, + {Label{}, 56, 96}, + {Builtin{}, 56, 96}, + {Nil{}, 52, 88}, // Misc {Scope{}, 60, 104}, diff --git a/src/cmd/compile/internal/types2/sizes_test.go b/src/cmd/compile/internal/types2/sizes_test.go index 9a772f4b1523fe..9597db58cb983d 100644 --- a/src/cmd/compile/internal/types2/sizes_test.go +++ b/src/cmd/compile/internal/types2/sizes_test.go @@ -184,7 +184,6 @@ func main() { func TestGCSizes(t *testing.T) { types2.DefPredeclaredTestFuncs() for _, tc := range gcSizesTests { - tc := tc t.Run(tc.name, func(t *testing.T) { t.Parallel() conf := types2.Config{Importer: defaultImporter(), Sizes: types2.SizesFor("gc", "amd64")} diff --git a/src/cmd/compile/internal/types2/stdlib_test.go b/src/cmd/compile/internal/types2/stdlib_test.go index a579c8184e3e14..94d31ba4ee3dd5 100644 --- a/src/cmd/compile/internal/types2/stdlib_test.go +++ b/src/cmd/compile/internal/types2/stdlib_test.go @@ -59,8 +59,6 @@ func TestStdlib(t *testing.T) { var wg sync.WaitGroup for dir := range dirFiles { - dir := dir - cpulimit <- struct{}{} wg.Add(1) go func() { @@ -330,12 +328,9 @@ func TestStdFixed(t *testing.T) { "issue48230.go", // go/types doesn't check validity of //go:xxx directives "issue49767.go", // go/types does not have constraints on channel element size "issue49814.go", // go/types does not have constraints on array size + "issue78355.go", // types2 does not have constraints on map element size "issue56103.go", // anonymous interface cycles; will be a type checker error in 1.22 "issue52697.go", // types2 does not have constraints on stack size - "issue68054.go", // this test requires GODEBUG=gotypesalias=1 - "issue68580.go", // this test requires GODEBUG=gotypesalias=1 - "issue73309.go", // this test requires GODEBUG=gotypesalias=1 - "issue73309b.go", // this test requires GODEBUG=gotypesalias=1 // These tests requires runtime/cgo.Incomplete, which is only available on some platforms. // However, types2 does not know about build constraints. @@ -360,7 +355,16 @@ func TestStdKen(t *testing.T) { var excluded = map[string]bool{ "builtin": true, "cmd/compile/internal/ssa/_gen": true, - "runtime/_mkmalloc": true, + "crypto/internal/cryptotest/wycheproof/_schema": true, + "crypto/internal/cryptotest/x509limbo/_schema": true, + "runtime/_mkmalloc": true, + "simd/archsimd/_gen/midway": true, + "simd/archsimd/_gen/sgutil": true, + "simd/archsimd/_gen/simdgen": true, + "simd/archsimd/_gen/simdgen/arm64": true, + "simd/archsimd/_gen/tmplgen": true, + "simd/archsimd/_gen/unify": true, + "simd/archsimd/_gen/wasmgen": true, } // printPackageMu synchronizes the printing of type-checked package files in @@ -400,8 +404,7 @@ func typecheckFiles(path string, filenames []string, importer Importer) (*Packag Error: func(err error) { errs = append(errs, err) }, - Importer: importer, - EnableAlias: true, + Importer: importer, } info := Info{Uses: make(map[*syntax.Name]Object)} pkg, _ := conf.Check(path, files, &info) @@ -460,7 +463,7 @@ func pkgFilenames(dir string, includeTest bool) ([]string, error) { return filenames, nil } -func walkPkgDirs(dir string, pkgh func(dir string, filenames []string), errh func(args ...interface{})) { +func walkPkgDirs(dir string, pkgh func(dir string, filenames []string), errh func(args ...any)) { w := walker{pkgh, errh} w.walk(dir) } diff --git a/src/cmd/compile/internal/types2/stmt.go b/src/cmd/compile/internal/types2/stmt.go index efe9c99d87625f..7bd5d8712b3889 100644 --- a/src/cmd/compile/internal/types2/stmt.go +++ b/src/cmd/compile/internal/types2/stmt.go @@ -192,7 +192,7 @@ func (check *Checker) suspendedCall(keyword string, call syntax.Expr) { } // goVal returns the Go value for val, or nil. -func goVal(val constant.Value) interface{} { +func goVal(val constant.Value) any { // val should exist, but be conservative and check if val == nil { return nil @@ -226,7 +226,7 @@ func goVal(val constant.Value) interface{} { // types we need to also check the value's types (e.g., byte(1) vs myByte(1)) // when the switch expression is of interface type. type ( - valueMap map[interface{}][]valueType // underlying Go value -> valueType + valueMap map[any][]valueType // underlying Go value -> valueType valueType struct { pos syntax.Pos typ Type @@ -238,20 +238,20 @@ L: for _, e := range values { var v operand check.expr(nil, &v, e) - if x.mode == invalid || v.mode == invalid { + if !x.isValid() || !v.isValid() { continue L } - check.convertUntyped(&v, x.typ) - if v.mode == invalid { + check.convertUntyped(&v, x.typ()) + if !v.isValid() { continue L } // Order matters: By comparing v against x, error positions are at the case values. res := v // keep original v unchanged check.comparison(&res, x, syntax.Eql, true) - if res.mode == invalid { + if !res.isValid() { continue L } - if v.mode != constant_ { + if v.mode() != constant_ { continue L // we're done } // look for duplicate values @@ -259,7 +259,7 @@ L: // look for duplicate types for a given value // (quadratic algorithm, but these lists tend to be very short) for _, vt := range seen[val] { - if Identical(v.typ, vt.typ) { + if Identical(v.typ(), vt.typ) { err := check.newError(DuplicateCase) err.addf(&v, "duplicate case %s in expression switch", &v) err.addf(vt.pos, "previous case") @@ -267,7 +267,7 @@ L: continue L } } - seen[val] = append(seen[val], valueType{v.Pos(), v.typ}) + seen[val] = append(seen[val], valueType{v.Pos(), v.typ()}) } } } @@ -345,7 +345,7 @@ L: if len(types) != 1 || T == nil { T = Typ[Invalid] if x != nil { - T = x.typ + T = x.typ() } } @@ -398,7 +398,7 @@ L: if len(types) != 1 || T == nil { T = Typ[Invalid] if x != nil { - T = x.typ + T = x.typ() } } @@ -444,7 +444,7 @@ func (check *Checker) stmt(ctxt stmtContext, s syntax.Stmt) { kind := check.rawExpr(nil, &x, s.X, nil, false) var msg string var code Code - switch x.mode { + switch x.mode() { default: if kind == statement { return @@ -463,8 +463,8 @@ func (check *Checker) stmt(ctxt stmtContext, s syntax.Stmt) { case *syntax.SendStmt: var ch, val operand check.expr(nil, &ch, s.Chan) - check.expr(nil, &val, s.Value) - if ch.mode == invalid || val.mode == invalid { + check.genericExpr(&val, s.Value, nil) + if !ch.isValid() || !val.isValid() { return } if elem := check.chanElem(s, &ch, false); elem != nil { @@ -477,11 +477,11 @@ func (check *Checker) stmt(ctxt stmtContext, s syntax.Stmt) { // (no need to call unpackExpr as s.Lhs must be single-valued) var x operand check.expr(nil, &x, s.Lhs) - if x.mode == invalid { + if !x.isValid() { return } - if !allNumeric(x.typ) { - check.errorf(s.Lhs, NonNumericIncDec, invalidOp+"%s%s%s (non-numeric type %s)", s.Lhs, s.Op, s.Op, x.typ) + if !allNumeric(x.typ()) { + check.errorf(s.Lhs, NonNumericIncDec, invalidOp+"%s%s%s (non-numeric type %s)", s.Lhs, s.Op, s.Op, x.typ()) return } check.assignVar(s.Lhs, nil, &x, "assignment") @@ -592,7 +592,7 @@ func (check *Checker) stmt(ctxt stmtContext, s syntax.Stmt) { check.simpleStmt(s.Init) var x operand check.expr(nil, &x, s.Cond) - if x.mode != invalid && !allBoolean(x.typ) { + if x.isValid() && !allBoolean(x.typ()) { check.error(s.Cond, InvalidCond, "non-boolean condition in if statement") } check.stmt(inner, s.Then) @@ -694,7 +694,7 @@ func (check *Checker) stmt(ctxt stmtContext, s syntax.Stmt) { if s.Cond != nil { var x operand check.expr(nil, &x, s.Cond) - if x.mode != invalid && !allBoolean(x.typ) { + if x.isValid() && !allBoolean(x.typ()) { check.error(s.Cond, InvalidCond, "non-boolean condition in for statement") } } @@ -721,15 +721,15 @@ func (check *Checker) switchStmt(inner stmtContext, s *syntax.SwitchStmt) { // By checking assignment of x to an invisible temporary // (as a compiler would), we get all the relevant checks. check.assignment(&x, nil, "switch expression") - if x.mode != invalid && !Comparable(x.typ) && !hasNil(x.typ) { - check.errorf(&x, InvalidExprSwitch, "cannot switch on %s (%s is not comparable)", &x, x.typ) - x.mode = invalid + if x.isValid() && !Comparable(x.typ()) && !hasNil(x.typ()) { + check.errorf(&x, InvalidExprSwitch, "cannot switch on %s (%s is not comparable)", &x, x.typ()) + x.invalidate() } } else { // spec: "A missing switch expression is // equivalent to the boolean value true." - x.mode = constant_ - x.typ = Typ[Bool] + x.mode_ = constant_ + x.typ_ = Typ[Bool] x.val = constant.MakeBool(true) // TODO(gri) should have a better position here pos := s.Rbrace @@ -785,10 +785,10 @@ func (check *Checker) typeSwitchStmt(inner stmtContext, s *syntax.SwitchStmt, gu { var x operand check.expr(nil, &x, guard.X) - if x.mode != invalid { - if isTypeParam(x.typ) { + if x.isValid() { + if isTypeParam(x.typ()) { check.errorf(&x, InvalidTypeSwitch, "cannot use type switch on type parameter value %s", &x) - } else if IsInterface(x.typ) { + } else if IsInterface(x.typ()) { sx = &x } else { check.errorf(&x, InvalidTypeSwitch, "%s is not an interface", &x) diff --git a/src/cmd/compile/internal/types2/subst.go b/src/cmd/compile/internal/types2/subst.go index 70fb232aa1feac..c79c821b0123d7 100644 --- a/src/cmd/compile/internal/types2/subst.go +++ b/src/cmd/compile/internal/types2/subst.go @@ -161,15 +161,92 @@ func (subst *subster) typ(typ Type) Type { // recv->interface->recv->interface->... recv := t.recv - params := subst.tuple(t.params) - results := subst.tuple(t.results) - if params != t.params || results != t.results { + // If t is a generic method signature whose own type parameters are not + // themselves the subject of this substitution, we are substituting the + // receiver type parameters (via Named.expandMethod). Because a method + // type parameter's bound may refer to a receiver type parameter + // (e.g. func (G[T]) M[P interface{ ~*T }]), we must create fresh type + // parameters with substituted bounds, and rename occurrences in params + // and results so they refer to the fresh parameters. Otherwise the + // resulting signature would retain a free reference to the original + // receiver type parameter. + // + // Fresh type parameters are always created, even when the bounds are + // unaffected by the substitution, so that the methods of distinct + // instances of the receiver type have distinct (method-specific) type + // parameters. + // + // When t's type parameters are the variables being substituted, we are + // instantiating t itself; the caller (Checker.instance for *Signature) + // sets tparams to nil afterward, so we leave them in place here. + tparams := t.tparams + s := subst + if n := tparams.Len(); n > 0 { + // If (any) one of the signature's type parameters is in the + // substitution map, this subst call is an instantiation of the + // signature. + _, instantiating := subst.smap[tparams.At(0)] + if debug { + // When calling subst on a signature, the substitution either + // applies to all of the type parameters (all are in the map) + // or none of them (none are in the map). + for _, tp := range tparams.list() { + _, ok := subst.smap[tp] + assert(ok == instantiating) + } + } + if !instantiating { + fresh := make([]*TypeParam, n) + // We're introducing a fresh set of method type parameters + // which appear elsewhere in the signature (parameter or + // result types, or the bounds of other type parameters). + // Create an updated substitution map containing the + // existing entries plus an entry for each fresh type + // parameter so that they are substituted simultaneously + // when we proceed with the outer substitution. + smap := make(substMap, len(subst.smap)+n) + for k, v := range subst.smap { + smap[k] = v + } + for i, tp := range tparams.list() { + tname := NewTypeName(tp.Obj().Pos(), tp.Obj().Pkg(), tp.Obj().Name(), nil) + ftp := subst.check.newTypeParam(tname, nil) + ftp.index = tp.index + fresh[i] = ftp + smap[tp] = ftp + // The fresh parameter stands in for tp in the mono graph, + // so that instantiations of (e.g.) G[int].M and G[A].M + // are tracked against the same vertex as the origin's tp. + if subst.check != nil { + subst.check.mono.recordCanon(ftp, tp) + } + } + // Now that we have the updated substitution map, use it to + // compute the constraints for the fresh type parameters. + for i, tp := range tparams.list() { + fresh[i].bound = subst.check.subst(subst.pos, tp.bound, smap, subst.expanding, subst.ctxt) + } + // Continue with the fresh type parameters and updated map. + tparams = &TypeParamList{tparams: fresh} + s = &subster{ + pos: subst.pos, + smap: smap, + check: subst.check, + expanding: subst.expanding, + ctxt: subst.ctxt, + } + } + } + + params := s.tuple(t.params) + results := s.tuple(t.results) + if params != t.params || results != t.results || tparams != t.tparams { return &Signature{ rparams: t.rparams, - // TODO(gri) why can't we nil out tparams here, rather than in instantiate? - tparams: t.tparams, + tparams: tparams, // instantiated signatures have a nil scope recv: recv, + recvold: t.recvold, params: params, results: results, variadic: t.variadic, diff --git a/src/cmd/compile/internal/types2/testdata/manual.go b/src/cmd/compile/internal/types2/testdata/manual.go index 825ab50f92de49..13829ded953c50 100644 --- a/src/cmd/compile/internal/types2/testdata/manual.go +++ b/src/cmd/compile/internal/types2/testdata/manual.go @@ -1,4 +1,4 @@ -// Copyright 2025 The Go Authors. All rights reserved. +// Copyright 2026 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. diff --git a/src/cmd/compile/internal/types2/trie.go b/src/cmd/compile/internal/types2/trie.go new file mode 100644 index 00000000000000..d369b931b1f60a --- /dev/null +++ b/src/cmd/compile/internal/types2/trie.go @@ -0,0 +1,90 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package types2 + +import "sort" + +// A trie[V] maps keys to values V, similar to a map. +// A key is a list of integers; two keys collide if one of them is a prefix of the other. +// For instance, [1, 2] and [1, 2, 3] collide, but [1, 2, 3] and [1, 2, 4] do not. +// If all keys have length 1, a trie degenerates into an ordinary map[int]V. +type trie[V any] map[int]any // map value is either trie[V] (non-leaf node), or V (leaf node) + +// insert inserts a value with a key into the trie; key must not be empty. +// If key doesn't collide with any other key in the trie, insert succeeds +// and returns (val, 0). Otherwise, insert fails and returns (alt, n) where +// alt is an unspecified but deterministically chosen value with a colliding +// key and n is the length > 0 of the common key prefix. The trie is not +// changed in this case. +func (tr trie[V]) insert(key []int, val V) (V, int) { + // A key serves as the path from the trie root to its corresponding value. + for l, index := range key { + if v, exists := tr[index]; exists { + // An entry already exists for this index; check its type to determine collision. + switch v := v.(type) { + case trie[V]: + // Path continues. + // Must check this case first in case V is any which would act as catch-all. + tr = v + case V: + // Collision: An existing key ends here. + // This means the existing key is a prefix of (or exactly equal to) key. + return v, l + 1 + case nil: + // Handle esoteric case where V is any and val is nil. + var zero V + return zero, l + 1 + default: + panic("trie.insert: invalid entry") + } + } else { + // Path doesn't exist yet, we need to build it. + if l == len(key)-1 { + // No prefix collision detected; insert val as a new leaf node. + tr[index] = val + return val, 0 + } + node := make(trie[V]) + tr[index] = node + tr = node + } + } + + if len(key) == 0 { + panic("trie.insert: key must not be empty") + } + + // Collision: path ends here, but the trie continues. + // This means key is a prefix of an existing key. + // Return a value from the subtrie. + for len(tr) != 0 { + // see switch above + switch v := tr.pickValue().(type) { + case trie[V]: + tr = v + case V: + return v, len(key) + case nil: + var zero V + return zero, len(key) + default: + panic("trie.insert: invalid entry") + } + } + + panic("trie.insert: unreachable") +} + +// pickValue deterministically picks a value of the trie and returns it. +// Only called in case of a collision. +// The trie must not be empty. +func (tr trie[V]) pickValue() any { + var keys []int + for k := range tr { + keys = append(keys, k) + } + sort.Ints(keys) // guarantee deterministic element pick + return tr[keys[0]] +} diff --git a/src/cmd/compile/internal/types2/trie_test.go b/src/cmd/compile/internal/types2/trie_test.go new file mode 100644 index 00000000000000..86813d1f462632 --- /dev/null +++ b/src/cmd/compile/internal/types2/trie_test.go @@ -0,0 +1,79 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package types2 + +import ( + "fmt" + "testing" +) + +func TestTrie(t *testing.T) { + strie := make(trie[string]) + + okay := func(index ...int) { + s := fmt.Sprintf("%x", index) + if p, n := strie.insert(index, s); n != 0 { + t.Errorf("%s collided with %s (n = %d)", s, p, n) + } + } + + fail := func(collision string, index ...int) { + s := fmt.Sprintf("%x", index) + if p, n := strie.insert(index, s); n == 0 { + t.Errorf("%s did not collide", s) + } else if p != collision { + t.Errorf("%s collided with %s (n == %d), want %s", s, p, n, collision) + } + } + + clear(strie) + okay(0) + fail("[0]", 0) + + clear(strie) + okay(0) + fail("[0]", 0, 1, 2, 3, 4, 5) + + clear(strie) + okay(1, 2) + okay(1, 3) + okay(1, 4, 5) + okay(1, 4, 2) + fail("[1 4 2]", 1, 4) + fail("[1 4 5]", 1, 4, 5) + okay(1, 4, 3) + okay(2, 1) + okay(2, 2) + fail("[2 2]", 2, 2, 3) + + clear(strie) + okay(0, 1, 2, 3, 4, 5) + okay(0, 1, 2, 3, 4, 6) + okay(0, 1, 2, 3, 4, 7) + okay(0, 1, 2, 3, 4, 8, 1) + okay(0, 1, 2, 3, 4, 4) + fail("[0 1 2 3 4 4]", 0, 1, 2, 3) +} + +func TestAnyValue(t *testing.T) { + atrie := make(trie[any]) // allow values of any type + + val := new(42) + alt, n := atrie.insert([]int{0}, val) + if n != 0 { + t.Errorf("unexpected collision (n = %d)", n) + } + if alt != val { + t.Errorf("unexpected result (alt = %#x, val = %#x)", alt, val) + } + + alt, n = atrie.insert([]int{0}, val) // nil is a valid value + if n == 0 { + t.Errorf("expected collision") + } + if alt != val { + t.Errorf("unexpected result (alt = %#x, val = %#x)", alt, val) + } +} diff --git a/src/cmd/compile/internal/types2/typelists.go b/src/cmd/compile/internal/types2/typelists.go index a2aba4a9a553c9..b0633022ae2015 100644 --- a/src/cmd/compile/internal/types2/typelists.go +++ b/src/cmd/compile/internal/types2/typelists.go @@ -4,6 +4,8 @@ package types2 +import "bytes" + // TypeParamList holds a list of type parameters. type TypeParamList struct{ tparams []*TypeParam } @@ -24,6 +26,19 @@ func (l *TypeParamList) list() []*TypeParam { return l.tparams } +func (l *TypeParamList) String() string { + var buf bytes.Buffer + buf.WriteByte('[') + for i, tparam := range l.tparams { + if i > 0 { + buf.WriteString(", ") + } + WriteType(&buf, tparam, nil) + } + buf.WriteByte(']') + return buf.String() +} + // TypeList holds a list of types. type TypeList struct{ types []Type } @@ -52,6 +67,19 @@ func (l *TypeList) list() []Type { return l.types } +func (l *TypeList) String() string { + var buf bytes.Buffer + buf.WriteByte('[') + for i, t := range l.types { + if i > 0 { + buf.WriteString(", ") + } + WriteType(&buf, t, nil) + } + buf.WriteByte(']') + return buf.String() +} + // ---------------------------------------------------------------------------- // Implementation diff --git a/src/cmd/compile/internal/types2/typestring.go b/src/cmd/compile/internal/types2/typestring.go index b1f0d0929bae33..fa220fc277ea18 100644 --- a/src/cmd/compile/internal/types2/typestring.go +++ b/src/cmd/compile/internal/types2/typestring.go @@ -211,14 +211,6 @@ func (w *typeWriter) typ(typ Type) { case *Interface: if w.ctxt == nil { - if t == universeAnyAlias.Type().Underlying() { - // When not hashing, we can try to improve type strings by writing "any" - // for a type that is pointer-identical to universeAny. - // TODO(rfindley): this logic should not be necessary with - // gotypesalias=1. Remove once that is always the case. - w.string("any") - break - } if t == asNamed(universeComparable.Type()).underlying { w.string("interface{comparable}") break @@ -344,7 +336,11 @@ func (w *typeWriter) typ(typ Type) { } if w.ctxt != nil { // TODO(gri) do we need to print the alias type name, too? - w.typ(Unalias(t.obj.typ)) + typ := Unalias(t.obj.typ) + if typ == nil { + panic("known implementation limitation: encountered an incomplete alias (see go.dev/issue/78296)") + } + w.typ(typ) } default: @@ -449,22 +445,25 @@ func (w *typeWriter) tuple(tup *Tuple, variadic bool) { } typ := v.typ if variadic && i == len(tup.vars)-1 { - if s, ok := typ.(*Slice); ok { + if slice, ok := typ.(*Slice); ok { w.string("...") - typ = s.elem + w.typ(slice.elem) } else { - // special case: - // append(s, "foo"...) leads to signature func([]byte, string...) - if t, _ := typ.Underlying().(*Basic); t == nil || t.kind != String { - w.error("expected string type") - continue - } + // append(slice, str...) entails various special + // cases, especially in conjunction with generics. + // str may be: + // - a string, + // - a TypeParam whose typeset includes string, or + // - a named []byte slice type B resulting from + // a client instantiating append([]byte, T) at T=B. + // For such cases we use the irregular notation + // func([]byte, T...), with the dots after the type. w.typ(typ) w.string("...") - continue } + } else { + w.typ(typ) } - w.typ(typ) } } w.byte(')') diff --git a/src/cmd/compile/internal/types2/typestring_test.go b/src/cmd/compile/internal/types2/typestring_test.go index c2be40da291d9d..fe787771e3f5b6 100644 --- a/src/cmd/compile/internal/types2/typestring_test.go +++ b/src/cmd/compile/internal/types2/typestring_test.go @@ -82,10 +82,10 @@ var independentTestTypes = []testEntry{ dup(`interface{String() string; m(int) float32}`), dup("interface{int | float32 | complex128}"), dup("interface{int | ~float32 | ~complex128}"), - dup("any"), dup("interface{comparable}"), - {"comparable", "interface{comparable}"}, {"error", "interface{Error() string}"}, + {"any", "interface{}"}, + {"comparable", "interface{comparable}"}, // maps dup("map[string]int"), diff --git a/src/cmd/compile/internal/types2/typexpr.go b/src/cmd/compile/internal/types2/typexpr.go index 8601ce627768e4..bffc9ba684eb45 100644 --- a/src/cmd/compile/internal/types2/typexpr.go +++ b/src/cmd/compile/internal/types2/typexpr.go @@ -16,10 +16,9 @@ import ( // ident type-checks identifier e and initializes x with the value or type of e. // If an error occurred, x.mode is set to invalid. -// For the meaning of def, see Checker.definedType, below. // If wantType is set, the identifier e is expected to denote a type. -func (check *Checker) ident(x *operand, e *syntax.Name, def *TypeName, wantType bool) { - x.mode = invalid +func (check *Checker) ident(x *operand, e *syntax.Name, wantType bool) { + x.invalidate() x.expr = e scope, obj := check.lookupScope(e.Value) @@ -31,14 +30,7 @@ func (check *Checker) ident(x *operand, e *syntax.Name, def *TypeName, wantType check.errorf(e, UndeclaredName, "undefined: %s", e.Value) } return - case universeComparable: - if !check.verifyVersionf(e, go1_18, "predeclared %s", e.Value) { - return // avoid follow-on errors - } - } - // Because the representation of any depends on gotypesalias, we don't check - // pointer identity here. - if obj.Name() == "any" && obj.Parent() == Universe { + case universeAny, universeComparable: if !check.verifyVersionf(e, go1_18, "predeclared %s", e.Value) { return // avoid follow-on errors } @@ -51,7 +43,8 @@ func (check *Checker) ident(x *operand, e *syntax.Name, def *TypeName, wantType // (see go.dev/issue/65344). _, gotType := obj.(*TypeName) if !gotType && wantType { - check.errorf(e, NotAType, "%s is not a type", obj.Name()) + check.errorf(e, NotAType, "%s (%s) is not a type", obj.Name(), objectKind(obj)) + // avoid "declared but not used" errors // (don't use Checker.use - we don't want to evaluate too much) if v, _ := obj.(*Var); v != nil && v.pkg == check.pkg /* see Checker.use1 */ { @@ -73,7 +66,7 @@ func (check *Checker) ident(x *operand, e *syntax.Name, def *TypeName, wantType // packages, to avoid races: see issue #69912. typ := obj.Type() if typ == nil || (gotType && wantType && obj.Pkg() == check.pkg) { - check.objDecl(obj, def) + check.objDecl(obj) typ = obj.Type() // type must have been assigned by Checker.objDecl } assert(typ != nil) @@ -106,14 +99,10 @@ func (check *Checker) ident(x *operand, e *syntax.Name, def *TypeName, wantType x.val = obj.val } assert(x.val != nil) - x.mode = constant_ + x.mode_ = constant_ case *TypeName: - if !check.conf.EnableAlias && check.isBrokenAlias(obj) { - check.errorf(e, InvalidDeclCycle, "invalid use of type alias %s in recursive type (see go.dev/issue/50729)", obj.name) - return - } - x.mode = typexpr + x.mode_ = typexpr case *Var: // It's ok to mark non-local variables, but ignore variables @@ -126,37 +115,37 @@ func (check *Checker) ident(x *operand, e *syntax.Name, def *TypeName, wantType if !isValid(typ) { return } - x.mode = variable + x.mode_ = variable case *Func: check.addDeclDep(obj) - x.mode = value + x.mode_ = value case *Builtin: x.id = obj.id - x.mode = builtin + x.mode_ = builtin case *Nil: - x.mode = nilvalue + x.mode_ = nilvalue default: panic("unreachable") } - x.typ = typ + x.typ_ = typ } // typ type-checks the type expression e and returns its type, or Typ[Invalid]. // The type must not be an (uninstantiated) generic type. func (check *Checker) typ(e syntax.Expr) Type { - return check.definedType(e, nil) + return check.declaredType(e, nil) } // varType type-checks the type expression e and returns its type, or Typ[Invalid]. // The type must not be an (uninstantiated) generic type and it must not be a // constraint interface. func (check *Checker) varType(e syntax.Expr) Type { - typ := check.definedType(e, nil) + typ := check.declaredType(e, nil) check.validVarType(e, typ) return typ } @@ -187,11 +176,11 @@ func (check *Checker) validVarType(e syntax.Expr, typ Type) { }).describef(e, "check var type %s", typ) } -// definedType is like typ but also accepts a type name def. -// If def != nil, e is the type specification for the type named def, declared -// in a type declaration, and def.typ.underlying will be set to the type of e -// before any components of e are type-checked. -func (check *Checker) definedType(e syntax.Expr, def *TypeName) Type { +// declaredType is like typ but also accepts a type name def. +// If def != nil, e is the type specification for the [Alias] or [Named] type +// named def, and def.typ.fromRHS will be set to the [Type] of e immediately +// after its creation. +func (check *Checker) declaredType(e syntax.Expr, def *TypeName) Type { typ := check.typInternal(e, def) assert(isTyped(typ)) if isGeneric(typ) { @@ -230,7 +219,7 @@ func goTypeName(typ Type) string { } // typInternal drives type checking of types. -// Must only be called by definedType or genericType. +// Must only be called by declaredType or genericType. func (check *Checker) typInternal(e0 syntax.Expr, def *TypeName) (T Type) { if check.conf.Trace { check.trace(e0.Pos(), "-- type %s", e0) @@ -257,13 +246,11 @@ func (check *Checker) typInternal(e0 syntax.Expr, def *TypeName) (T Type) { case *syntax.Name: var x operand - check.ident(&x, e, def, true) + check.ident(&x, e, true) - switch x.mode { + switch x.mode() { case typexpr: - typ := x.typ - setDefType(def, typ) - return typ + return x.typ() case invalid: // ignore - error reported before case novalue: @@ -274,13 +261,11 @@ func (check *Checker) typInternal(e0 syntax.Expr, def *TypeName) (T Type) { case *syntax.SelectorExpr: var x operand - check.selector(&x, e, def, true) + check.selector(&x, e, true) - switch x.mode { + switch x.mode() { case typexpr: - typ := x.typ - setDefType(def, typ) - return typ + return x.typ() case invalid: // ignore - error reported before case novalue: @@ -291,16 +276,15 @@ func (check *Checker) typInternal(e0 syntax.Expr, def *TypeName) (T Type) { case *syntax.IndexExpr: check.verifyVersionf(e, go1_18, "type instantiation") - return check.instantiatedType(e.X, syntax.UnpackListExpr(e.Index), def) + return check.instantiatedType(e.X, syntax.UnpackListExpr(e.Index)) case *syntax.ParenExpr: // Generic types must be instantiated before they can be used in any form. // Consequently, generic types cannot be parenthesized. - return check.definedType(e.X, def) + return check.declaredType(e.X, def) case *syntax.ArrayType: typ := new(Array) - setDefType(def, typ) if e.Len != nil { typ.len = check.arrayLength(e.Len) } else { @@ -316,7 +300,6 @@ func (check *Checker) typInternal(e0 syntax.Expr, def *TypeName) (T Type) { case *syntax.SliceType: typ := new(Slice) - setDefType(def, typ) typ.elem = check.varType(e.Elem) return typ @@ -326,7 +309,6 @@ func (check *Checker) typInternal(e0 syntax.Expr, def *TypeName) (T Type) { case *syntax.StructType: typ := new(Struct) - setDefType(def, typ) check.structType(typ, e) return typ @@ -334,7 +316,6 @@ func (check *Checker) typInternal(e0 syntax.Expr, def *TypeName) (T Type) { if e.Op == syntax.Mul && e.Y == nil { typ := new(Pointer) typ.base = Typ[Invalid] // avoid nil base in invalid recursive type declaration - setDefType(def, typ) typ.base = check.varType(e.X) // If typ.base is invalid, it's unlikely that *base is particularly // useful - even a valid dereferenciation will lead to an invalid @@ -351,20 +332,16 @@ func (check *Checker) typInternal(e0 syntax.Expr, def *TypeName) (T Type) { case *syntax.FuncType: typ := new(Signature) - setDefType(def, typ) check.funcType(typ, nil, nil, e) return typ case *syntax.InterfaceType: typ := check.newInterface() - setDefType(def, typ) check.interfaceType(typ, e, def) return typ case *syntax.MapType: typ := new(Map) - setDefType(def, typ) - typ.key = check.varType(e.Key) typ.elem = check.varType(e.Value) @@ -388,7 +365,6 @@ func (check *Checker) typInternal(e0 syntax.Expr, def *TypeName) (T Type) { case *syntax.ChanType: typ := new(Chan) - setDefType(def, typ) dir := SendRecv switch e.Dir { @@ -413,26 +389,10 @@ func (check *Checker) typInternal(e0 syntax.Expr, def *TypeName) (T Type) { } typ := Typ[Invalid] - setDefType(def, typ) return typ } -func setDefType(def *TypeName, typ Type) { - if def != nil { - switch t := def.typ.(type) { - case *Alias: - t.fromRHS = typ - case *Basic: - assert(t == Typ[Invalid]) - case *Named: - t.fromRHS = typ - default: - panic(fmt.Sprintf("unexpected type %T", t)) - } - } -} - -func (check *Checker) instantiatedType(x syntax.Expr, xlist []syntax.Expr, def *TypeName) (res Type) { +func (check *Checker) instantiatedType(x syntax.Expr, xlist []syntax.Expr) (res Type) { if check.conf.Trace { check.trace(x.Pos(), "-- instantiating type %s with %s", x, xlist) check.indent++ @@ -443,10 +403,6 @@ func (check *Checker) instantiatedType(x syntax.Expr, xlist []syntax.Expr, def * }() } - defer func() { - setDefType(def, res) - }() - var cause string typ := check.genericType(x, &cause) if cause != "" { @@ -526,14 +482,14 @@ func (check *Checker) arrayLength(e syntax.Expr) int64 { var x operand check.expr(nil, &x, e) - if x.mode != constant_ { - if x.mode != invalid { + if x.mode() != constant_ { + if x.isValid() { check.errorf(&x, InvalidArrayLen, "array length %s must be constant", &x) } return -1 } - if isUntyped(x.typ) || isInteger(x.typ) { + if isUntyped(x.typ()) || isInteger(x.typ()) { if val := constant.ToInt(x.val); val.Kind() == constant.Int { if representableConst(val, check, Typ[Int], nil) { if n, ok := constant.Int64Val(val); ok && n >= 0 { @@ -544,7 +500,7 @@ func (check *Checker) arrayLength(e syntax.Expr) int64 { } var msg string - if isInteger(x.typ) { + if isInteger(x.typ()) { msg = "invalid array length %s" } else { msg = "array length %s must be integer" diff --git a/src/cmd/compile/internal/types2/under.go b/src/cmd/compile/internal/types2/under.go index 98c62733c7cd99..15fca73522278a 100644 --- a/src/cmd/compile/internal/types2/under.go +++ b/src/cmd/compile/internal/types2/under.go @@ -26,12 +26,12 @@ func all(t Type, f func(t, u Type) bool) bool { // typeset is an iterator over the (type/underlying type) pairs of the // specific type terms of the type set implied by t. // If t is a type parameter, the implied type set is the type set of t's constraint. -// In that case, if there are no specific terms, typeset calls yield with (nil, nil). +// In this case, if there are no specific terms, the iterator produces (nil, nil). // If t is not a type parameter, the implied type set consists of just t. -// In any case, typeset is guaranteed to call yield at least once. +// In any case, typeset is guaranteed to produce at least one set of results. func typeset(t Type) iter.Seq2[Type, Type] { return func(yield func(t, u Type) bool) { - _ = all(t, yield) + all(t, yield) } } diff --git a/src/cmd/compile/internal/types2/unify.go b/src/cmd/compile/internal/types2/unify.go index f4f24f4d1b7ec0..e554e77a5dfad7 100644 --- a/src/cmd/compile/internal/types2/unify.go +++ b/src/cmd/compile/internal/types2/unify.go @@ -67,6 +67,7 @@ const ( // corresponding types inferred for each type parameter. // A unifier is created by calling newUnifier. type unifier struct { + check *Checker // handles maps each type parameter to its inferred type through // an indirection *Type called (inferred type) "handle". // Initially, each type parameter has its own, separate handle, @@ -85,7 +86,7 @@ type unifier struct { // and corresponding type argument lists. The type argument list may be shorter // than the type parameter list, and it may contain nil types. Matching type // parameters and arguments must have the same index. -func newUnifier(tparams []*TypeParam, targs []Type, enableInterfaceInference bool) *unifier { +func newUnifier(check *Checker, tparams []*TypeParam, targs []Type, enableInterfaceInference bool) *unifier { assert(len(tparams) >= len(targs)) handles := make(map[*TypeParam]*Type, len(tparams)) // Allocate all handles up-front: in a correct program, all type parameters @@ -99,7 +100,7 @@ func newUnifier(tparams []*TypeParam, targs []Type, enableInterfaceInference boo } handles[x] = &t } - return &unifier{handles, 0, enableInterfaceInference} + return &unifier{check, handles, 0, enableInterfaceInference} } // unifyMode controls the behavior of the unifier. @@ -141,7 +142,8 @@ func (u *unifier) unify(x, y Type, mode unifyMode) bool { return u.nify(x, y, mode, nil) } -func (u *unifier) tracef(format string, args ...interface{}) { +func (u *unifier) tracef(format string, args ...any) { + // TODO(gri) consider adjusting this to use Checker.trace fmt.Println(strings.Repeat(". ", u.depth) + sprintf(nil, true, format, args...)) } @@ -534,10 +536,17 @@ func (u *unifier) nify(x, y Type, mode unifyMode, p *ifacePair) (result bool) { // the non-interface type, otherwise unification fails. if xi != nil { // All xi methods must exist in y and corresponding signatures must unify. + // A generic method never satisfies an interface method, so fail rather + // than unify ym's own type parameter into an inference variable. xmethods := xi.typeSet().methods for _, xm := range xmethods { obj, _, _ := LookupFieldOrMethod(y, false, xm.pkg, xm.name) - if ym, _ := obj.(*Func); ym == nil || !u.nify(xm.typ, ym.typ, exact, p) { + ym, _ := obj.(*Func) + if ym == nil { + return false + } + u.check.objDecl(ym) // ensure fully set-up signature + if ym.Signature().TypeParams() != nil || !u.nify(xm.typ, ym.typ, exact, p) { return false } } diff --git a/src/cmd/compile/internal/types2/universe.go b/src/cmd/compile/internal/types2/universe.go index 332cd174f97466..6a649843d17d72 100644 --- a/src/cmd/compile/internal/types2/universe.go +++ b/src/cmd/compile/internal/types2/universe.go @@ -24,9 +24,8 @@ var ( universeBool Type universeByte Type // uint8 alias, but has name "byte" universeRune Type // int32 alias, but has name "rune" - universeAnyNoAlias *TypeName - universeAnyAlias *TypeName universeError Type + universeAny Object universeComparable Object ) @@ -76,47 +75,15 @@ func defPredeclaredTypes() { for _, t := range Typ { def(NewTypeName(nopos, nil, t.name, t)) } + for _, t := range basicAliases { def(NewTypeName(nopos, nil, t.name, t)) } - // type any = interface{} - // - // Implement two representations of any: one for the legacy gotypesalias=0, - // and one for gotypesalias=1. This is necessary for consistent - // representation of interface aliases during type checking, and is - // implemented via hijacking [Scope.Lookup] for the [Universe] scope. - // - // Both representations use the same distinguished pointer for their RHS - // interface type, allowing us to detect any (even with the legacy - // representation), and format it as "any" rather than interface{}, which - // clarifies user-facing error messages significantly. - // - // TODO(rfindley): once the gotypesalias GODEBUG variable is obsolete (and we - // consistently use the Alias node), we should be able to clarify user facing - // error messages without using a distinguished pointer for the any - // interface. - { - universeAnyNoAlias = NewTypeName(nopos, nil, "any", &Interface{complete: true, tset: &topTypeSet}) - universeAnyNoAlias.setColor(black) - // ensure that the any TypeName reports a consistent Parent, after - // hijacking Universe.Lookup with gotypesalias=0. - universeAnyNoAlias.setParent(Universe) - - // It shouldn't matter which representation of any is actually inserted - // into the Universe, but we lean toward the future and insert the Alias - // representation. - universeAnyAlias = NewTypeName(nopos, nil, "any", nil) - universeAnyAlias.setColor(black) - _ = NewAlias(universeAnyAlias, universeAnyNoAlias.Type().Underlying()) // Link TypeName and Alias - def(universeAnyAlias) - } - // type error interface{ Error() string } { obj := NewTypeName(nopos, nil, "error", nil) - obj.setColor(black) - typ := (*Checker)(nil).newNamed(obj, nil, nil) + typ := NewNamed(obj, nil, nil) // error.Error() string recv := newVar(RecvVar, nopos, nil, "", typ) @@ -133,17 +100,17 @@ func defPredeclaredTypes() { def(obj) } + // type any = interface{} + { + obj := NewTypeName(nopos, nil, "any", nil) + NewAlias(obj, &emptyInterface) + def(obj) + } + // type comparable interface{} // marked as comparable { obj := NewTypeName(nopos, nil, "comparable", nil) - obj.setColor(black) - typ := (*Checker)(nil).newNamed(obj, nil, nil) - - // interface{} // marked as comparable - ityp := &Interface{complete: true, tset: &_TypeSet{nil, allTermlist, true}} - - typ.fromRHS = ityp - typ.Underlying() + NewNamed(obj, &Interface{complete: true, tset: &_TypeSet{nil, allTermlist, true}}, nil) def(obj) } } @@ -165,7 +132,7 @@ func defPredeclaredConsts() { } func defPredeclaredNil() { - def(&Nil{object{name: "nil", typ: Typ[UntypedNil], color_: black}}) + def(&Nil{object{name: "nil", typ: Typ[UntypedNil]}}) } // A builtinId is the id of a builtin function. @@ -282,6 +249,7 @@ func init() { universeByte = Universe.Lookup("byte").Type() universeRune = Universe.Lookup("rune").Type() universeError = Universe.Lookup("error").Type() + universeAny = Universe.Lookup("any") universeComparable = Universe.Lookup("comparable") } @@ -289,7 +257,7 @@ func init() { // a scope. Objects with exported names are inserted in the unsafe package // scope; other objects are inserted in the universe scope. func def(obj Object) { - assert(obj.color() == black) + assert(obj.Type() != nil) name := obj.Name() if strings.Contains(name, " ") { return // nothing to do diff --git a/src/cmd/compile/internal/types2/validtype.go b/src/cmd/compile/internal/types2/validtype.go index c21c36d6f6fd1a..bec6412f86153a 100644 --- a/src/cmd/compile/internal/types2/validtype.go +++ b/src/cmd/compile/internal/types2/validtype.go @@ -141,7 +141,8 @@ func (check *Checker) validType0(pos syntax.Pos, typ Type, nest, path []*Named) // Every type added to nest is also added to path; thus every type that is in nest // must also be in path (invariant). But not every type in path is in nest, since // nest may be pruned (see below, *TypeParam case). - if !check.validType0(pos, t.Origin().fromRHS, append(nest, t), append(path, t)) { + t.Origin().unpack() + if !check.validType0(pos, t.Origin().rhs(), append(nest, t), append(path, t)) { return false } diff --git a/src/cmd/compile/internal/types2/version.go b/src/cmd/compile/internal/types2/version.go index 765b0f7e9aba44..05cb9391b957da 100644 --- a/src/cmd/compile/internal/types2/version.go +++ b/src/cmd/compile/internal/types2/version.go @@ -44,6 +44,7 @@ var ( go1_22 = asGoVersion("go1.22") go1_23 = asGoVersion("go1.23") go1_26 = asGoVersion("go1.26") + go1_27 = asGoVersion("go1.27") // current (deployed) Go version go_current = asGoVersion(fmt.Sprintf("go1.%d", goversion.Version)) @@ -58,7 +59,7 @@ func (check *Checker) allowVersion(want goVersion) bool { // verifyVersionf is like allowVersion but also accepts a format string and arguments // which are used to report a version error if allowVersion returns false. -func (check *Checker) verifyVersionf(at poser, v goVersion, format string, args ...interface{}) bool { +func (check *Checker) verifyVersionf(at poser, v goVersion, format string, args ...any) bool { if !check.allowVersion(v) { check.versionErrorf(at, v, format, args...) return false diff --git a/src/cmd/compile/internal/walk/assign.go b/src/cmd/compile/internal/walk/assign.go index 63b6a1d2c14163..6c4c13ef824b82 100644 --- a/src/cmd/compile/internal/walk/assign.go +++ b/src/cmd/compile/internal/walk/assign.go @@ -120,6 +120,16 @@ func walkAssign(init *ir.Nodes, n ir.Node) ir.Node { // walkAssignDotType walks an OAS2DOTTYPE node. func walkAssignDotType(n *ir.AssignListStmt, init *ir.Nodes) ir.Node { walkExprListSafe(n.Lhs, init) + + if r, ok := n.Rhs[0].(*ir.TypeAssertExpr); ok && r.Op() == ir.ODOTTYPE2 && !r.Type().IsInterface() { + if shapeTypeAssertImpossible(r.X, r.Type()) { + init.Append(typecheck.Stmt(ir.NewAssignStmt(base.Pos, ir.BlankNode, walkExpr(r.X, init)))) + init.Append(typecheck.Stmt(ir.NewAssignStmt(base.Pos, n.Lhs[0], ir.NewZero(base.Pos, r.Type())))) + init.Append(typecheck.Stmt(ir.NewAssignStmt(base.Pos, n.Lhs[1], ir.NewBool(base.Pos, false)))) + return ir.NewBlockStmt(base.Pos, nil) + } + } + n.Rhs[0] = walkExpr(n.Rhs[0], init) return n } @@ -154,10 +164,10 @@ func walkAssignMapRead(init *ir.Nodes, n *ir.AssignListStmt) ir.Node { r := n.Rhs[0].(*ir.IndexExpr) walkExprListSafe(n.Lhs, init) + r.X = walkExpr(r.X, init) r.Index = walkExpr(r.Index, init) t := r.X.Type() - fast := mapfast(t) key := mapKeyArg(fast, r, r.Index, false) @@ -219,7 +229,7 @@ func walkAssignRecv(init *ir.Nodes, n *ir.AssignListStmt) ir.Node { fn := chanfn("chanrecv2", 2, r.X.Type()) ok := n.Lhs[1] call := mkcall1(fn, types.Types[types.TBOOL], init, r.X, n1) - return typecheck.Stmt(ir.NewAssignStmt(base.Pos, ok, call)) + return walkAssign(init, typecheck.Stmt(ir.NewAssignStmt(base.Pos, ok, call))) } // walkReturn walks an ORETURN node. diff --git a/src/cmd/compile/internal/walk/builtin.go b/src/cmd/compile/internal/walk/builtin.go index 974eb06886f855..e4db9f0186a2ad 100644 --- a/src/cmd/compile/internal/walk/builtin.go +++ b/src/cmd/compile/internal/walk/builtin.go @@ -136,17 +136,18 @@ func walkGrowslice(slice *ir.Name, init *ir.Nodes, oldPtr, newLen, oldCap, num i } // walkClear walks an OCLEAR node. -func walkClear(n *ir.UnaryExpr) ir.Node { +func walkClear(n *ir.UnaryExpr, init *ir.Nodes) ir.Node { + x := walkExpr(n.X, init) typ := n.X.Type() switch { case typ.IsSlice(): - if n := arrayClear(n.X.Pos(), n.X, nil); n != nil { + if n := arrayClear(x.Pos(), x, nil); n != nil { return n } // If n == nil, we are clearing an array which takes zero memory, do nothing. return ir.NewBlockStmt(n.Pos(), nil) case typ.IsMap(): - return mapClear(n.X, reflectdata.TypePtrAt(n.X.Pos(), n.X.Type())) + return mapClear(x, reflectdata.TypePtrAt(x.Pos(), typ)) } panic("unreachable") } @@ -455,7 +456,7 @@ func walkMakeSlice(n *ir.MakeExpr, init *ir.Nodes) ir.Node { niflen := ir.NewIfStmt(base.Pos, ir.NewBinaryExpr(base.Pos, ir.OLT, len, ir.NewInt(base.Pos, 0)), nil, nil) niflen.Body = []ir.Node{mkcall("panicmakeslicelen", nil, init)} nif.Body.Append(niflen, mkcall("panicmakeslicecap", nil, init)) - init.Append(typecheck.Stmt(nif)) + appendWalkStmt(init, nif) // var arr [cap]E // s = arr[:len] @@ -714,10 +715,14 @@ func walkPrint(nn *ir.CallExpr, init *ir.Nodes) ir.Node { } case types.TINT, types.TINT8, types.TINT16, types.TINT32, types.TINT64: on = typecheck.LookupRuntime("printint") - case types.TFLOAT32, types.TFLOAT64: - on = typecheck.LookupRuntime("printfloat") - case types.TCOMPLEX64, types.TCOMPLEX128: - on = typecheck.LookupRuntime("printcomplex") + case types.TFLOAT32: + on = typecheck.LookupRuntime("printfloat32") + case types.TFLOAT64: + on = typecheck.LookupRuntime("printfloat64") + case types.TCOMPLEX64: + on = typecheck.LookupRuntime("printcomplex64") + case types.TCOMPLEX128: + on = typecheck.LookupRuntime("printcomplex128") case types.TBOOL: on = typecheck.LookupRuntime("printbool") case types.TSTRING: @@ -725,16 +730,21 @@ func walkPrint(nn *ir.CallExpr, init *ir.Nodes) ir.Node { if ir.IsConst(n, constant.String) { cs = ir.StringVal(n) } - switch cs { - case " ": - on = typecheck.LookupRuntime("printsp") - case "\n": - on = typecheck.LookupRuntime("printnl") - default: - on = typecheck.LookupRuntime("printstring") + // Print values of the named type `quoted` using printquoted. + if types.RuntimeSymName(n.Type().Sym()) == "quoted" { + on = typecheck.LookupRuntime("printquoted") + } else { + switch cs { + case " ": + on = typecheck.LookupRuntime("printsp") + case "\n": + on = typecheck.LookupRuntime("printnl") + default: + on = typecheck.LookupRuntime("printstring") + } } default: - badtype(ir.OPRINT, n.Type(), nil) + badtype(nn.Op(), n.Type(), nil) continue } diff --git a/src/cmd/compile/internal/walk/compare.go b/src/cmd/compile/internal/walk/compare.go index d3a91f30b9e8d4..445fbb0889b184 100644 --- a/src/cmd/compile/internal/walk/compare.go +++ b/src/cmd/compile/internal/walk/compare.go @@ -192,18 +192,18 @@ func walkCompare(n *ir.BinaryExpr, init *ir.Nodes) ir.Node { // is handled by walkCompare. fn, needsLength := reflectdata.EqFor(t) call := ir.NewCallExpr(base.Pos, ir.OCALL, fn, nil) - addrCmpl := typecheck.NodAddr(cmpl) + addrCmpL := typecheck.NodAddr(cmpl) addrCmpR := typecheck.NodAddr(cmpr) if !types.IsNoRacePkg(types.LocalPkg) && base.Flag.Race { - ptrL := typecheck.Conv(typecheck.Conv(addrCmpl, types.Types[types.TUNSAFEPTR]), types.Types[types.TUINTPTR]) + ptrL := typecheck.Conv(typecheck.Conv(addrCmpL, types.Types[types.TUNSAFEPTR]), types.Types[types.TUINTPTR]) ptrR := typecheck.Conv(typecheck.Conv(addrCmpR, types.Types[types.TUNSAFEPTR]), types.Types[types.TUINTPTR]) raceFn := typecheck.LookupRuntime("racereadrange") size := ir.NewInt(base.Pos, t.Size()) call.PtrInit().Append(mkcall1(raceFn, nil, init, ptrL, size)) call.PtrInit().Append(mkcall1(raceFn, nil, init, ptrR, size)) } - call.Args.Append(addrCmpl) - call.Args.Append(addrCmpR) + call.Args.Append(typecheck.Conv(addrCmpL, types.Types[types.TUNSAFEPTR])) + call.Args.Append(typecheck.Conv(addrCmpR, types.Types[types.TUNSAFEPTR])) if needsLength { call.Args.Append(ir.NewInt(base.Pos, t.Size())) } diff --git a/src/cmd/compile/internal/walk/complit.go b/src/cmd/compile/internal/walk/complit.go index 6452618f6cead7..4a72cc27e689ef 100644 --- a/src/cmd/compile/internal/walk/complit.go +++ b/src/cmd/compile/internal/walk/complit.go @@ -23,7 +23,7 @@ func walkCompLit(n ir.Node, init *ir.Nodes) ir.Node { // n can be directly represented in the read-only data section. // Make direct reference to the static data. See issue 12841. vstat := readonlystaticname(n.Type()) - fixedlit(inInitFunction, initKindStatic, n, vstat, init) + fixedlit(initKindStatic, n, vstat, init) return typecheck.Expr(vstat) } var_ := typecheck.TempAt(base.Pos, ir.CurFunc, n.Type()) @@ -31,30 +31,6 @@ func walkCompLit(n ir.Node, init *ir.Nodes) ir.Node { return var_ } -// initContext is the context in which static data is populated. -// It is either in an init function or in any other function. -// Static data populated in an init function will be written either -// zero times (as a readonly, static data symbol) or -// one time (during init function execution). -// Either way, there is no opportunity for races or further modification, -// so the data can be written to a (possibly readonly) data symbol. -// Static data populated in any other function needs to be local to -// that function to allow multiple instances of that function -// to execute concurrently without clobbering each others' data. -type initContext uint8 - -const ( - inInitFunction initContext = iota - inNonInitFunction -) - -func (c initContext) String() string { - if c == inInitFunction { - return "inInitFunction" - } - return "inNonInitFunction" -} - // readonlystaticname returns a name backed by a read-only static data symbol. func readonlystaticname(t *types.Type) *ir.Name { n := staticinit.StaticName(t) @@ -85,9 +61,7 @@ const ( func getdyn(n ir.Node, top bool) initGenType { switch n.Op() { default: - // Handle constants in linker, except that linker cannot do - // the relocations necessary for string constants in FIPS packages. - if ir.IsConstNode(n) && (!n.Type().IsString() || !base.Ctxt.IsFIPS()) { + if isStaticLiteral(n) { return initConst } return initDynamic @@ -127,7 +101,17 @@ func getdyn(n ir.Node, top bool) initGenType { return mode } -// isStaticCompositeLiteral reports whether n is a compile-time constant. +// isStaticLiteral reports whether n is a compile-time (non-composite) +// constant, which can be represented in the read-only data section. +func isStaticLiteral(n ir.Node) bool { + // A string reference requires a relocation, not allowed + // in static data in FIPS mode. + return ir.IsConstNode(n) && !(base.Ctxt.IsFIPS() && n.Type().IsString()) +} + +// isStaticCompositeLiteral reports whether a composite literal n +// is a compile-time constant, which can be represented in the +// read-only data section. func isStaticCompositeLiteral(n ir.Node) bool { switch n.Op() { case ir.OSLICELIT: @@ -152,8 +136,10 @@ func isStaticCompositeLiteral(n ir.Node) bool { } } return true - case ir.OLITERAL, ir.ONIL: + case ir.ONIL: return true + case ir.OLITERAL: + return isStaticLiteral(n) case ir.OCONVIFACE: // See staticinit.Schedule.StaticAssign's OCONVIFACE case for comments. if base.Ctxt.IsFIPS() && base.Ctxt.Flag_shared { @@ -194,7 +180,7 @@ const ( // fixedlit handles struct, array, and slice literals. // TODO: expand documentation. -func fixedlit(ctxt initContext, kind initKind, n *ir.CompLitExpr, var_ ir.Node, init *ir.Nodes) { +func fixedlit(kind initKind, n *ir.CompLitExpr, var_ ir.Node, init *ir.Nodes) { isBlank := var_ == ir.BlankNode var splitnode func(ir.Node) (a ir.Node, value ir.Node) switch n.Op() { @@ -220,7 +206,7 @@ func fixedlit(ctxt initContext, kind initKind, n *ir.CompLitExpr, var_ ir.Node, return ir.BlankNode, r.Value } ir.SetPos(r) - return ir.NewSelectorExpr(base.Pos, ir.ODOT, var_, r.Sym()), r.Value + return ir.NewSelectorExpr(base.Pos, ir.OXDOT, var_, r.Sym()), r.Value } default: base.Fatalf("fixedlit bad op: %v", n.Op()) @@ -236,29 +222,18 @@ func fixedlit(ctxt initContext, kind initKind, n *ir.CompLitExpr, var_ ir.Node, switch value.Op() { case ir.OSLICELIT: value := value.(*ir.CompLitExpr) - if (kind == initKindStatic && ctxt == inNonInitFunction) || (kind == initKindDynamic && ctxt == inInitFunction) { - var sinit ir.Nodes - slicelit(ctxt, value, a, &sinit) - if kind == initKindStatic { - // When doing static initialization, init statements may contain dynamic - // expression, which will be initialized later, causing liveness analysis - // confuses about variables lifetime. So making sure those expressions - // are ordered correctly here. See issue #52673. - orderBlock(&sinit, map[string][]*ir.Name{}) - typecheck.Stmts(sinit) - walkStmtList(sinit) - } - init.Append(sinit...) + if kind == initKindDynamic { + slicelit(value, a, init) continue } case ir.OARRAYLIT, ir.OSTRUCTLIT: value := value.(*ir.CompLitExpr) - fixedlit(ctxt, kind, value, a, init) + fixedlit(kind, value, a, init) continue } - islit := ir.IsConstNode(value) + islit := isStaticLiteral(value) if (kind == initKindStatic && !islit) || (kind == initKindDynamic && islit) { continue } @@ -287,28 +262,11 @@ func isSmallSliceLit(n *ir.CompLitExpr) bool { return n.Type().Elem().Size() == 0 || n.Len <= ir.MaxSmallArraySize/n.Type().Elem().Size() } -func slicelit(ctxt initContext, n *ir.CompLitExpr, var_ ir.Node, init *ir.Nodes) { +func slicelit(n *ir.CompLitExpr, var_ ir.Node, init *ir.Nodes) { // make an array type corresponding the number of elements we have t := types.NewArray(n.Type().Elem(), n.Len) types.CalcSize(t) - if ctxt == inNonInitFunction { - // put everything into static array - vstat := staticinit.StaticName(t) - - fixedlit(ctxt, initKindStatic, n, vstat, init) - fixedlit(ctxt, initKindDynamic, n, vstat, init) - - // copy static to slice - var_ = typecheck.AssignExpr(var_) - name, offset, ok := staticinit.StaticLoc(var_) - if !ok || name.Class != ir.PEXTERN { - base.Fatalf("slicelit: %v", var_) - } - staticdata.InitSlice(name, offset, vstat.Linksym(), t.NumElem()) - return - } - // recipe for var = []t{...} // 1. make a static array // var vstat [...]t @@ -334,12 +292,8 @@ func slicelit(ctxt initContext, n *ir.CompLitExpr, var_ ir.Node, init *ir.Nodes) mode := getdyn(n, true) if mode&initConst != 0 && !isSmallSliceLit(n) { - if ctxt == inInitFunction { - vstat = readonlystaticname(t) - } else { - vstat = staticinit.StaticName(t) - } - fixedlit(ctxt, initKindStatic, n, vstat, init) + vstat = readonlystaticname(t) + fixedlit(initKindStatic, n, vstat, init) } // make new auto *array (3 declare) @@ -394,11 +348,11 @@ func slicelit(ctxt initContext, n *ir.CompLitExpr, var_ ir.Node, init *ir.Nodes) // See issue #31987. k = initKindLocalCode } - fixedlit(ctxt, k, value, a, init) + fixedlit(k, value, a, init) continue } - if vstat != nil && ir.IsConstNode(value) { // already set by copy from static value + if vstat != nil && isStaticLiteral(value) { // already set by copy from static value continue } @@ -456,8 +410,8 @@ func maplit(n *ir.CompLitExpr, m ir.Node, init *ir.Nodes) { datak.List.Append(r.Key) datae.List.Append(r.Value) } - fixedlit(inInitFunction, initKindStatic, datak, vstatk, init) - fixedlit(inInitFunction, initKindStatic, datae, vstate, init) + fixedlit(initKindStatic, datak, vstatk, init) + fixedlit(initKindStatic, datae, vstate, init) // loop adding structure elements to map // for i = 0; i < len(vstatk); i++ { @@ -567,17 +521,13 @@ func anylit(n ir.Node, var_ ir.Node, init *ir.Nodes) { // lay out static data vstat := readonlystaticname(t) - ctxt := inInitFunction - if n.Op() == ir.OARRAYLIT { - ctxt = inNonInitFunction - } - fixedlit(ctxt, initKindStatic, n, vstat, init) + fixedlit(initKindStatic, n, vstat, init) // copy static to var appendWalkStmt(init, ir.NewAssignStmt(base.Pos, var_, vstat)) // add expressions to automatic - fixedlit(inInitFunction, initKindDynamic, n, var_, init) + fixedlit(initKindDynamic, n, var_, init) break } @@ -592,11 +542,11 @@ func anylit(n ir.Node, var_ ir.Node, init *ir.Nodes) { appendWalkStmt(init, ir.NewAssignStmt(base.Pos, var_, nil)) } - fixedlit(inInitFunction, initKindLocalCode, n, var_, init) + fixedlit(initKindLocalCode, n, var_, init) case ir.OSLICELIT: n := n.(*ir.CompLitExpr) - slicelit(inInitFunction, n, var_, init) + slicelit(n, var_, init) case ir.OMAPLIT: n := n.(*ir.CompLitExpr) diff --git a/src/cmd/compile/internal/walk/expr.go b/src/cmd/compile/internal/walk/expr.go index b9e226b20741fc..296d43f1d92da4 100644 --- a/src/cmd/compile/internal/walk/expr.go +++ b/src/cmd/compile/internal/walk/expr.go @@ -13,6 +13,7 @@ import ( "cmd/compile/internal/base" "cmd/compile/internal/ir" + "cmd/compile/internal/noder" "cmd/compile/internal/objw" "cmd/compile/internal/reflectdata" "cmd/compile/internal/rttype" @@ -293,7 +294,7 @@ func walkExpr1(n ir.Node, init *ir.Nodes) ir.Node { case ir.OCLEAR: n := n.(*ir.UnaryExpr) - return walkClear(n) + return walkClear(n, init) case ir.OCLOSE: n := n.(*ir.UnaryExpr) @@ -351,6 +352,11 @@ func walkExpr1(n ir.Node, init *ir.Nodes) ir.Node { case ir.OMETHVALUE: return walkMethodValue(n.(*ir.SelectorExpr), init) + + case ir.OMOVE2HEAP: + n := n.(*ir.MoveToHeapExpr) + n.Slice = walkExpr(n.Slice, init) + return n } // No return! Each case must return (or panic), @@ -704,27 +710,21 @@ func walkDivMod(n *ir.BinaryExpr, init *ir.Nodes) ir.Node { // runtime calls late in SSA processing. if types.RegSize < 8 && (et == types.TINT64 || et == types.TUINT64) { if n.Y.Op() == ir.OLITERAL { - // Leave div/mod by constant powers of 2 or small 16-bit constants. + // Leave div/mod by non-zero uint64 constants. // The SSA backend will handle those. + // (Zero constants should have been rejected already, but we check just in case.) switch et { case types.TINT64: - c := ir.Int64Val(n.Y) - if c < 0 { - c = -c - } - if c != 0 && c&(c-1) == 0 { + if ir.Int64Val(n.Y) != 0 { return n } case types.TUINT64: - c := ir.Uint64Val(n.Y) - if c < 1<<16 { - return n - } - if c != 0 && c&(c-1) == 0 { + if ir.Uint64Val(n.Y) != 0 { return n } } } + // Build call to uint64div, uint64mod, int64div, or int64mod. var fn string if et == types.TINT64 { fn = "int64" @@ -763,6 +763,51 @@ func walkDotType(n *ir.TypeAssertExpr, init *ir.Nodes) ir.Node { return n } +// shapeTypeAssertImpossible reports whether a type assertion from src +// to concrete type dst can never succeed because they have +// incompatible shape types. +func shapeTypeAssertImpossible(src ir.Node, dst *types.Type) bool { + if dst.IsInterface() { + return false + } + srcShape := convIfaceShapeType(src) + if srcShape == nil { + return false + } + return !types.Identical(srcShape, noder.Shapify(dst, false)) && + !types.Identical(srcShape, noder.Shapify(dst, true)) +} + +// convIfaceShapeType returns the shape type from which src was +// created via OCONVIFACE, or nil. +func convIfaceShapeType(src ir.Node) *types.Type { + for { + switch s := src.(type) { + case *ir.ParenExpr: + src = s.X + continue + case *ir.ConvExpr: + if s.Op() == ir.OCONVNOP { + src = s.X + continue + } + if s.Op() == ir.OCONVIFACE { + srcType := s.X.Type() + if srcType != nil && !srcType.IsInterface() && srcType.IsShape() { + return srcType + } + return nil + } + } + break + } + + if name, ok := src.(*ir.Name); ok && shapeConvSources != nil { + return shapeConvSources[name.Canonical()] + } + return nil +} + func makeTypeAssertDescriptor(target *types.Type, canFail bool) *obj.LSym { // When converting from an interface to a non-empty interface. Needs a runtime call. // Allocate an internal/abi.TypeAssert descriptor for that call. @@ -947,7 +992,7 @@ func walkStringHeader(n *ir.StringHeaderExpr, init *ir.Nodes) ir.Node { return n } -// return 1 if integer n must be in range [0, max), 0 otherwise. +// bounded reports whether integer n must be in range [0, max). func bounded(n ir.Node, max int64) bool { if n.Type() == nil || !n.Type().IsInteger() { return false @@ -1005,7 +1050,7 @@ func bounded(n ir.Node, max int64) bool { if !sign && ir.IsSmallIntConst(n.Y) { v := ir.Int64Val(n.Y) if v > int64(bits) { - return true + return max > 0 } bits -= int32(v) } diff --git a/src/cmd/compile/internal/walk/order.go b/src/cmd/compile/internal/walk/order.go index 4b0e36da859275..e22bb7317a9510 100644 --- a/src/cmd/compile/internal/walk/order.go +++ b/src/cmd/compile/internal/walk/order.go @@ -260,7 +260,7 @@ func (o *orderState) addrTemp(n ir.Node) ir.Node { // v can be directly represented in the read-only data section. lit := v.(*ir.CompLitExpr) vstat := readonlystaticname(n.Type()) - fixedlit(inInitFunction, initKindStatic, lit, vstat, nil) // nil init + fixedlit(initKindStatic, lit, vstat, nil) // nil init vstat = typecheck.Expr(vstat).(*ir.Name) return vstat } diff --git a/src/cmd/compile/internal/walk/range.go b/src/cmd/compile/internal/walk/range.go index 139343a8ede2a3..5034b91833854c 100644 --- a/src/cmd/compile/internal/walk/range.go +++ b/src/cmd/compile/internal/walk/range.go @@ -23,7 +23,7 @@ func cheapComputableIndex(width int64) bool { // MIPS does not have R+R addressing // Arm64 may lack ability to generate this code in our assembler, // but the architecture supports it. - case sys.PPC64, sys.S390X: + case sys.Loong64, sys.PPC64, sys.S390X: return width == 1 case sys.AMD64, sys.I386, sys.ARM64, sys.ARM: switch width { @@ -348,6 +348,8 @@ func walkRange(nrange *ir.RangeStmt) ir.Node { // } else { // hv2, hv1 = decoderune(ha, hv1) fn := typecheck.LookupRuntime("decoderune") + // decoderune expects a uint, but hv1 is an int. + // This is safe because hv1 is always >= 0. call := mkcall1(fn, fn.Type().ResultsTuple(), &nif.Else, ha, hv1) a := ir.NewAssignListStmt(base.Pos, ir.OAS2, []ir.Node{hv2, hv1}, []ir.Node{call}) nif.Else.Append(a) @@ -477,7 +479,7 @@ func mapClear(m, rtyp ir.Node) ir.Node { // instantiate mapclear(typ *type, hmap map[any]any) fn := typecheck.LookupRuntime("mapclear", t.Key(), t.Elem()) n := mkcallstmt1(fn, rtyp, m) - return walkStmt(typecheck.Stmt(n)) + return typecheck.Stmt(n) } // Lower n into runtime·memclr if possible, for @@ -559,14 +561,17 @@ func arrayClear(wbPos src.XPos, a ir.Node, nrange *ir.RangeStmt) ir.Node { } // Convert to - // if len(a) != 0 { + // if ln := len(a); ln != 0 { // hp = &a[0] // hn = len(a)*sizeof(elem(a)) // memclr{NoHeap,Has}Pointers(hp, hn) - // i = len(a) - 1 + // i = ln - 1 // } n := ir.NewIfStmt(base.Pos, nil, nil, nil) - n.Cond = ir.NewBinaryExpr(base.Pos, ir.ONE, ir.NewUnaryExpr(base.Pos, ir.OLEN, a), ir.NewInt(base.Pos, 0)) + ln := typecheck.TempAt(base.Pos, ir.CurFunc, types.Types[types.TINT]) + as := ir.NewAssignStmt(base.Pos, ln, ir.NewUnaryExpr(base.Pos, ir.OLEN, a)) + n.PtrInit().Append(typecheck.Stmt(as)) + n.Cond = ir.NewBinaryExpr(base.Pos, ir.ONE, ln, ir.NewInt(base.Pos, 0)) // hp = &a[0] hp := typecheck.TempAt(base.Pos, ir.CurFunc, types.Types[types.TUNSAFEPTR]) @@ -578,7 +583,7 @@ func arrayClear(wbPos src.XPos, a ir.Node, nrange *ir.RangeStmt) ir.Node { // hn = len(a) * sizeof(elem(a)) hn := typecheck.TempAt(base.Pos, ir.CurFunc, types.Types[types.TUINTPTR]) - mul := typecheck.Conv(ir.NewBinaryExpr(base.Pos, ir.OMUL, ir.NewUnaryExpr(base.Pos, ir.OLEN, a), ir.NewInt(base.Pos, elemsize)), types.Types[types.TUINTPTR]) + mul := typecheck.Conv(ir.NewBinaryExpr(base.Pos, ir.OMUL, ln, ir.NewInt(base.Pos, elemsize)), types.Types[types.TUINTPTR]) n.Body.Append(ir.NewAssignStmt(base.Pos, hn, mul)) var fn ir.Node @@ -595,7 +600,7 @@ func arrayClear(wbPos src.XPos, a ir.Node, nrange *ir.RangeStmt) ir.Node { // For array range clear, also set "i = len(a) - 1" if nrange != nil { - idx := ir.NewAssignStmt(base.Pos, nrange.Key, typecheck.Conv(ir.NewBinaryExpr(base.Pos, ir.OSUB, ir.NewUnaryExpr(base.Pos, ir.OLEN, a), ir.NewInt(base.Pos, 1)), nrange.Key.Type())) + idx := ir.NewAssignStmt(base.Pos, nrange.Key, typecheck.Conv(ir.NewBinaryExpr(base.Pos, ir.OSUB, ln, ir.NewInt(base.Pos, 1)), nrange.Key.Type())) n.Body.Append(idx) } diff --git a/src/cmd/compile/internal/walk/stmt.go b/src/cmd/compile/internal/walk/stmt.go index 2c01fd10f124e5..b9999cd9ea4732 100644 --- a/src/cmd/compile/internal/walk/stmt.go +++ b/src/cmd/compile/internal/walk/stmt.go @@ -7,6 +7,7 @@ package walk import ( "cmd/compile/internal/base" "cmd/compile/internal/ir" + "cmd/compile/internal/reflectdata" ) // The result of walkStmt MUST be assigned back to n, e.g. @@ -138,6 +139,16 @@ func walkStmt(n ir.Node) ir.Node { case ir.OTAILCALL: n := n.(*ir.TailCallStmt) + // Since go.dev/cl/751465, the compiler emits tail calls for wrappers + // for embedded interfaces. But a tail call never reaches walkCall, so + // the interface calls are not marked as used, causing the linker to + // drop the callee. See issues #81089 and #81340. + // TODO: Should we just call walkCall here? + if n.Call.Op() == ir.OCALLINTER { + usemethod(n.Call) + reflectdata.MarkUsedIfaceMethod(n.Call) + } + var init ir.Nodes n.Call.Fun = walkExpr(n.Call.Fun, &init) diff --git a/src/cmd/compile/internal/walk/switch.go b/src/cmd/compile/internal/walk/switch.go index cbe38b54bcd038..e5373150f9c89c 100644 --- a/src/cmd/compile/internal/walk/switch.go +++ b/src/cmd/compile/internal/walk/switch.go @@ -9,6 +9,7 @@ import ( "fmt" "go/constant" "go/token" + "math" "math/bits" "slices" "sort" @@ -20,6 +21,7 @@ import ( "cmd/compile/internal/reflectdata" "cmd/compile/internal/rttype" "cmd/compile/internal/ssagen" + "cmd/compile/internal/staticdata" "cmd/compile/internal/typecheck" "cmd/compile/internal/types" "cmd/internal/obj" @@ -75,6 +77,8 @@ func walkSwitchExpr(sw *ir.SwitchStmt) { base.Pos = lno + tryLookupTable(sw, cond) + s := exprSwitch{ pos: lno, exprname: cond, @@ -334,6 +338,318 @@ func (s *exprSwitch) tryJumpTable(cc []exprClause, out *ir.Nodes) bool { return true } +// tryLookupTable attempts to replace constant-returning cases of an integer +// switch with a static lookup table. Cases whose bodies are a single "return +// " are served from a read-only array, eliminating branching. +// Remaining cases (non-constant bodies, default) are left in sw.Cases for +// normal switch compilation. +// +// For example: +// +// switch x { +// case 0: return 10 +// case 1: return 20 +// case 2, 3: return 30 +// default: return -1 +// } +// +// Becomes: +// +// var table = [4]int{10, 20, 30, 30} +// if uint(x) < 4 { return table[x] } +// // remaining switch for default +// +// Partial optimization also works when some cases have non-constant bodies: +// +// switch x { +// case 1: return 1 +// case 2: return 4 +// case 3: sideEffect(); return 9 +// ... +// default: return x * x +// } +// +// Becomes: +// +// var table = [8]int{1, 4, 0, ...} +// var mask = [8]uint8{1, 1, 0, ...} +// if uint(x-1) <= 7 && mask[x-1] != 0 { return table[x-1] } +// // remaining switch for case 3 + default +func tryLookupTable(sw *ir.SwitchStmt, cond ir.Node) { + const minCases = 4 // need enough cases to justify a table + + if base.Flag.N != 0 { + return // optimizations disabled + } + if !cond.Type().IsInteger() { + return + } + if cond.Type().Size() > int64(types.PtrSize) { + return // 64-bit switches on 32-bit archs + } + + fn := ir.CurFunc + if fn == nil || fn.Type().NumResults() != 1 { + return // only handle single return value + } + resultType := fn.Type().Results()[0].Type + + // Classify each case as const-returning or not. + // TODO: support more complex bodies, like local variable assignments. + // For example: + // + // var n int + // switch x { + // case 1: n = 1 + // case 2: n = 4 + // case 3: n = 9 + // case 4: n = 16 + // } + // return n + // + // Could be optimized to: + // + // var table = [4]int{1, 4, 9, 16} + // var n int + // if uint(x-1) < 4 { n = table[x-1] } + // return n + constSet := make(map[int64]ir.Node) // case value → return constant literal + constCaseSet := make(map[int]bool) // indices of const-returning non-default cases + excludeSet := make(map[int64]bool) // case values with non-const bodies + var defaultVal ir.Node // non-nil if default returns a constant + minVal, maxVal := int64(math.MaxInt64), int64(math.MinInt64) + var excludeNextCase bool // true if the previous case ends in fallthrough + + for i, ncase := range sw.Cases { + // A case that is the target of a fallthrough must be excluded, + // since removing it would break the fallthrough chain. + isFallthroughTarget := excludeNextCase + excludeNextCase, _ = endsInFallthrough(ncase.Body) + + if len(ncase.List) == 0 { + // Default case: check if it returns a constant (for gap filling). + if isConstReturn(ncase) && !isFallthroughTarget { + defaultVal = ncase.Body[0].(*ir.ReturnStmt).Results[0] + } + continue + } + + vals, ok := constIntCaseVals(ncase) + if !ok { + // Case has a non-constant case expression (e.g. a variable). + // Bail out: we can't determine overlap with the table range. + // For example: + // case 1: return 1 // const → would go to table + // case c: return 9 // c is a variable, not a constant + // case 3: return 3 // const → would go to table + // At runtime, if c==3 then Go evaluates case c before case 3, + // returning 9. But if we put cases 1 and 3 in a table, n==3 + // would return 3 from the table, skipping the case c check. + return + } + + if !isConstReturn(ncase) || isFallthroughTarget || excludeNextCase { + // Non-const body, fallthrough source, or fallthrough target: + // exclude these values from the table so the mask redirects + // them to the normal switch, preserving Go's top-to-bottom + // case evaluation order. + for _, v := range vals { + excludeSet[v] = true + } + continue // will be handled by normal switch + } + + retVal := ncase.Body[0].(*ir.ReturnStmt).Results[0] + for _, v := range vals { + constSet[v] = retVal + minVal = min(minVal, v) + maxVal = max(maxVal, v) + } + constCaseSet[i] = true + } + + if len(constSet) < minCases { + return + } + + tableSize := maxVal - minVal + 1 + if tableSize <= 0 || !isSwitchDense(int64(len(constSet)), tableSize) { + return // too sparse + } + + // Build static lookup table and determine which slots are valid. + // Also build the bitmask inline if the table is small enough. + tabType := types.NewArray(resultType, tableSize) + tabName := readonlystaticname(tabType) + elemSize := int(resultType.Size()) + maxBitmaskSize := int64(types.PtrSize * 8) // 32 or 64 + + var needMask bool + var bitmask uint64 + validSlots := make([]bool, tableSize) + // Pre-size the symbol to cover the full table. + tabName.Linksym().WriteInt(base.Ctxt, tableSize*int64(elemSize)-1, 1, 0) + for i := range tableSize { + caseVal := minVal + i + if excludeSet[caseVal] { + // Non-const case in range: must fall through to normal switch. + needMask = true + } else { + val := constSet[caseVal] + if val == nil { + if defaultVal == nil { + // Gap with no const default: must fall through to normal switch. + needMask = true + continue + } + val = defaultVal // gap filled with default constant value + } + staticdata.InitConst(tabName, i*int64(elemSize), val, elemSize) + validSlots[i] = true + bitmask |= 1 << uint(i) + } + } + + // Build mask if some slots must fall through to normal switch. + // When the table fits in a register-width bitmask (≤32 entries on 32-bit, + // ≤64 on 64-bit), use the bitmask computed above. For larger tables, + // fall back to a byte array. + var maskName *ir.Name + useBitmask := needMask && tableSize <= maxBitmaskSize + if needMask && !useBitmask { + maskType := types.NewArray(types.Types[types.TUINT8], tableSize) + maskName = readonlystaticname(maskType) + maskSym := maskName.Linksym() + for i := range tableSize { + var v uint8 + if validSlots[i] { + v = 1 + } + maskSym.WriteInt(base.Ctxt, i, 1, int64(v)) + } + } + + // Generate code: + // idx := uint(int(cond) - minVal) + // if idx <= uint(maxVal-minVal) [&& bitmask>>idx&1 != 0] { return table[idx] } + pos := sw.Pos() + + // Widen cond to int to avoid overflow in small integer types. + intType := types.Types[types.TINT] + wideCond := typecheck.Conv(cond, intType) + + // Compute idx = int(cond) - minVal. + var idx ir.Node + if minVal != 0 { + minLit := ir.NewBasicLit(pos, intType, constant.MakeInt64(minVal)) + idx = typecheck.Expr(ir.NewBinaryExpr(pos, ir.OSUB, wideCond, minLit)) + } else { + idx = wideCond + } + + // Convert to uint for the one-sided bounds check and store in a temp + // so the index can be shared across the bounds check, table, and mask. + uintType := types.Types[types.TUINT] + uidx := typecheck.Conv(idx, uintType) + uidx = copyExpr(uidx, uintType, &sw.Compiled) + + // Bounds check: uint(idx) <= uint(maxVal - minVal). + rangeLit := ir.NewBasicLit(pos, uintType, constant.MakeUint64(uint64(maxVal-minVal))) + boundsCheck := typecheck.Expr(ir.NewBinaryExpr(pos, ir.OLE, uidx, rangeLit)) + boundsCheck = typecheck.DefaultLit(boundsCheck, nil) + + // Table lookup: table[idx] with bounds elided (already checked). + lookup := ir.NewIndexExpr(pos, tabName, uidx) + lookup.SetBounded(true) + lookup = typecheck.Expr(lookup).(*ir.IndexExpr) + + retStmt := ir.NewReturnStmt(pos, []ir.Node{lookup}) + + var ifBody []ir.Node + if needMask { + var maskCheck ir.Node + if useBitmask { + // Bitmask check: (bitmask >> idx) & 1 != 0. + // Use uintptr so the operation is register-width on all architectures. + bitmaskType := types.Types[types.TUINTPTR] + bitmaskLit := ir.NewBasicLit(pos, bitmaskType, constant.MakeUint64(bitmask)) + shifted := typecheck.Expr(ir.NewBinaryExpr(pos, ir.ORSH, bitmaskLit, uidx)) + one := ir.NewBasicLit(pos, bitmaskType, constant.MakeUint64(1)) + masked := typecheck.Expr(ir.NewBinaryExpr(pos, ir.OAND, shifted, one)) + zero := ir.NewBasicLit(pos, bitmaskType, constant.MakeUint64(0)) + maskCheck = typecheck.Expr(ir.NewBinaryExpr(pos, ir.ONE, masked, zero)) + } else { + // Mask array check: mask[idx] != 0. + maskLookup := ir.NewIndexExpr(pos, maskName, uidx) + maskLookup.SetBounded(true) + maskLookup = typecheck.Expr(maskLookup).(*ir.IndexExpr) + zero := ir.NewBasicLit(pos, types.Types[types.TUINT8], constant.MakeInt64(0)) + maskCheck = typecheck.Expr(ir.NewBinaryExpr(pos, ir.ONE, maskLookup, zero)) + } + maskCheck = typecheck.DefaultLit(maskCheck, nil) + + innerIf := ir.NewIfStmt(pos, maskCheck, []ir.Node{retStmt}, nil) + ifBody = []ir.Node{innerIf} + } else { + ifBody = []ir.Node{retStmt} + } + + outerIf := ir.NewIfStmt(pos, boundsCheck, ifBody, nil) + sw.Compiled.Append(outerIf) + + // Remove handled const cases from sw.Cases. + // Keep default and non-const cases for normal switch processing. + newCases := make([]*ir.CaseClause, 0, len(sw.Cases)-len(constCaseSet)) + for i, ncase := range sw.Cases { + if !constCaseSet[i] { + newCases = append(newCases, ncase) + } + } + sw.Cases = newCases +} + +// isSwitchDense reports whether a lookup table with tableSize entries +// for numCases cases is dense enough to be worth building. +// It requires at least 40% of table slots to be used, matching the +// density threshold used by LLVM's SimplifyCFG. +func isSwitchDense(numCases, tableSize int64) bool { + const minDensity = 40 + if tableSize >= math.MaxInt64/100 { + return false // avoid multiplication overflow below + } + return numCases*100 >= tableSize*minDensity +} + +// isConstReturn reports whether ncase has a body that is a single +// return statement returning one constant. +func isConstReturn(ncase *ir.CaseClause) bool { + if len(ncase.Body) != 1 { + return false + } + ret, ok := ncase.Body[0].(*ir.ReturnStmt) + if !ok || len(ret.Results) != 1 { + return false + } + return ret.Results[0].Op() == ir.OLITERAL +} + +// constIntCaseVals returns the int64 values of all case expressions in +// ncase, if they are all integer constants. Returns ok=false if any +// case expression is not a constant integer. +func constIntCaseVals(ncase *ir.CaseClause) (vals []int64, ok bool) { + for _, n1 := range ncase.List { + if n1.Op() != ir.OLITERAL || n1.Val().Kind() != constant.Int { + return nil, false + } + v, fit := constant.Int64Val(n1.Val()) + if !fit { + return nil, false + } + vals = append(vals, v) + } + return vals, true +} + func (c *exprClause) test(exprname ir.Node) ir.Node { // Integer range. if c.hi != c.lo { @@ -387,7 +703,8 @@ func endsInFallthrough(stmts []ir.Node) (bool, src.XPos) { // type switch. func walkSwitchType(sw *ir.SwitchStmt) { var s typeSwitch - s.srcName = sw.Tag.(*ir.TypeSwitchGuard).X + origSrc := sw.Tag.(*ir.TypeSwitchGuard).X + s.srcName = origSrc s.srcName = walkExpr(s.srcName, sw.PtrInit()) s.srcName = copyExpr(s.srcName, s.srcName.Type(), &sw.Compiled) s.okName = typecheck.TempAt(base.Pos, ir.CurFunc, types.Types[types.TBOOL]) @@ -617,6 +934,10 @@ caseLoop: // the dynamic type cases separately, as we do above. } + if shapeTypeAssertImpossible(origSrc, c.typ.Type()) { + continue + } + if c.typ.Type().IsInterface() { interfaceCases = append(interfaceCases, c) } else { diff --git a/src/cmd/compile/internal/walk/walk.go b/src/cmd/compile/internal/walk/walk.go index 25add3d8043905..259649019a414b 100644 --- a/src/cmd/compile/internal/walk/walk.go +++ b/src/cmd/compile/internal/walk/walk.go @@ -10,7 +10,6 @@ import ( "cmd/compile/internal/base" "cmd/compile/internal/ir" - "cmd/compile/internal/reflectdata" "cmd/compile/internal/rttype" "cmd/compile/internal/ssagen" "cmd/compile/internal/typecheck" @@ -24,11 +23,11 @@ const tmpstringbufsize = 32 func Walk(fn *ir.Func) { ir.CurFunc = fn - // Set and then clear a package-level cache of static values for this fn. + // Build pre-walk analysis caches with a single AST traversal. // (At some point, it might be worthwhile to have a walkState structure // that gets passed everywhere where things like this can go.) - staticValues = findStaticValues(fn) - defer func() { staticValues = nil }() + analyzePreWalk(fn) + defer func() { staticValues = nil; shapeConvSources = nil }() errorsBefore := base.Errors() order(fn) @@ -194,7 +193,7 @@ func mapfast(t *types.Type) int { if t.Elem().Size() > abi.MapMaxElemBytes { return mapslow } - switch reflectdata.AlgType(t.Key()) { + switch algType(t.Key()) { case types.AMEM32: if !t.Key().HasPointers() { return mapfast32 @@ -218,6 +217,35 @@ func mapfast(t *types.Type) int { return mapslow } +// algType returns the fixed-width AMEMxx variants instead of the general +// AMEM kind when possible. +func algType(t *types.Type) types.AlgKind { + a := types.AlgType(t) + if a == types.AMEM { + if t.Alignment() < int64(base.Ctxt.Arch.Alignment) && t.Alignment() < t.Size() { + // For example, we can't treat [2]int16 as an int32 if int32s require + // 4-byte alignment. See issue 46283. + return a + } + switch t.Size() { + case 0: + return types.AMEM0 + case 1: + return types.AMEM8 + case 2: + return types.AMEM16 + case 4: + return types.AMEM32 + case 8: + return types.AMEM64 + case 16: + return types.AMEM128 + } + } + + return a +} + func walkAppendArgs(n *ir.CallExpr, init *ir.Nodes) { walkExprListSafe(n.Args, init) @@ -422,23 +450,44 @@ func staticValue(n ir.Node) ir.Node { // staticValues is a cache of static values for use by staticValue. var staticValues map[ir.Node]ir.Node -// findStaticValues returns a map of static values for fn. -func findStaticValues(fn *ir.Func) map[ir.Node]ir.Node { - // We can't use an ir.ReassignOracle or ir.StaticValue in the - // middle of walk because they don't currently handle - // transformed assignments (e.g., will complain about 'RHS == nil'). - // So we instead build this map to use in walk. +// shapeConvSources maps an *ir.Name (a PAUTO interface variable) to +// the shape type of the OCONVIFACE expression that is its single +// static value, if any. +var shapeConvSources map[*ir.Name]*types.Type + +// analyzePreWalk populates staticValues and shapeConvSources using a +// single AST traversal. We can't use an ir.ReassignOracle or +// ir.StaticValue in the middle of walk because they don't currently +// handle transformed assignments (e.g., will complain about +// 'RHS == nil'). So we build these maps before walk begins. +func analyzePreWalk(fn *ir.Func) { ro := &ir.ReassignOracle{} ro.Init(fn) - m := make(map[ir.Node]ir.Node) + sv := make(map[ir.Node]ir.Node) + scs := make(map[*ir.Name]*types.Type) ir.Visit(fn, func(n ir.Node) { - if n.Op() == ir.OCONVIFACE { + switch n.Op() { + case ir.OCONVIFACE: x := n.(*ir.ConvExpr).X v := ro.StaticValue(x) if v != nil && v != x { - m[x] = v + sv[x] = v + } + case ir.ONAME: + name := n.(*ir.Name).Canonical() + if name.Class != ir.PAUTO || name.Type() == nil || !name.Type().IsInterface() { + return + } + val := ro.StaticValue(name) + if val == nil || val.Op() != ir.OCONVIFACE { + return + } + srcType := val.(*ir.ConvExpr).X.Type() + if srcType != nil && !srcType.IsInterface() && srcType.IsShape() { + scs[name] = srcType } } }) - return m + staticValues = sv + shapeConvSources = scs } diff --git a/src/cmd/compile/internal/wasm/simdssa.go b/src/cmd/compile/internal/wasm/simdssa.go new file mode 100644 index 00000000000000..2d28657df13537 --- /dev/null +++ b/src/cmd/compile/internal/wasm/simdssa.go @@ -0,0 +1,132 @@ +// Code generated by 'wasmgen'; DO NOT EDIT. + +package wasm + +import ( + "cmd/compile/internal/ssa" + "cmd/compile/internal/ssagen" + "cmd/internal/obj" + "cmd/internal/obj/wasm" +) + +func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value, extend bool) bool { + switch v.Op { + case ssa.OpWasmF32x4ExtractLane, ssa.OpWasmI64x2ExtractLane, ssa.OpWasmF64x2ExtractLane: + getValue128(s, v.Args[0]) + p := s.Prog(v.Op.Asm()) + p.To = obj.Addr{Type: obj.TYPE_CONST, Offset: v.AuxInt} + case ssa.OpWasmI8x16ExtractLaneU, ssa.OpWasmI16x8ExtractLaneU: + getValue128(s, v.Args[0]) + p := s.Prog(v.Op.Asm()) + p.To = obj.Addr{Type: obj.TYPE_CONST, Offset: v.AuxInt} + if extend { + s.Prog(wasm.AI64ExtendI32U) + } + case ssa.OpWasmI8x16ExtractLaneS, ssa.OpWasmI16x8ExtractLaneS, ssa.OpWasmI32x4ExtractLane: + getValue128(s, v.Args[0]) + p := s.Prog(v.Op.Asm()) + p.To = obj.Addr{Type: obj.TYPE_CONST, Offset: v.AuxInt} + if extend { + s.Prog(wasm.AI64ExtendI32S) + } + case ssa.OpWasmI8x16ReplaceLane, ssa.OpWasmI16x8ReplaceLane, ssa.OpWasmI32x4ReplaceLane: + getValue128(s, v.Args[0]) + getValue32(s, v.Args[1]) + p := s.Prog(v.Op.Asm()) + p.To = obj.Addr{Type: obj.TYPE_CONST, Offset: v.AuxInt} + case ssa.OpWasmF32x4ReplaceLane, ssa.OpWasmI64x2ReplaceLane, ssa.OpWasmF64x2ReplaceLane: + getValue128(s, v.Args[0]) + getValue64(s, v.Args[1]) + p := s.Prog(v.Op.Asm()) + p.To = obj.Addr{Type: obj.TYPE_CONST, Offset: v.AuxInt} + case ssa.OpWasmI8x16Splat, ssa.OpWasmI16x8Splat, ssa.OpWasmI32x4Splat: + getValue32(s, v.Args[0]) + s.Prog(v.Op.Asm()) + case ssa.OpWasmI64x2Splat: + getValue64(s, v.Args[0]) + s.Prog(v.Op.Asm()) + case ssa.OpWasmF32x4Splat: + getValueFxx(s, v.Args[0]) + s.Prog(v.Op.Asm()) + case ssa.OpWasmF64x2Splat: + getValueFxx(s, v.Args[0]) + s.Prog(v.Op.Asm()) + case ssa.OpWasmI8x16AllTrue, ssa.OpWasmV128AnyTrue, ssa.OpWasmI16x8AllTrue, + ssa.OpWasmI32x4AllTrue, ssa.OpWasmI64x2AllTrue, ssa.OpWasmI8x16Abs, + ssa.OpWasmI16x8Abs, ssa.OpWasmI32x4Abs, ssa.OpWasmF32x4Abs, + ssa.OpWasmI64x2Abs, ssa.OpWasmF64x2Abs, ssa.OpWasmF32x4Ceil, + ssa.OpWasmF64x2Ceil, ssa.OpWasmF64x2ConvertLowI32x4S, ssa.OpWasmF64x2ConvertLowI32x4U, + ssa.OpWasmF32x4ConvertI32x4S, ssa.OpWasmF32x4ConvertI32x4U, ssa.OpWasmI32x4TruncSatF32x4S, + ssa.OpWasmI32x4TruncSatF32x4U, ssa.OpWasmI64x2ExtendHighI32x4S, ssa.OpWasmI64x2ExtendHighI32x4U, + ssa.OpWasmI32x4ExtendHighI16x8S, ssa.OpWasmI32x4ExtendHighI16x8U, ssa.OpWasmI16x8ExtendHighI8x16S, + ssa.OpWasmI16x8ExtendHighI8x16U, ssa.OpWasmI64x2ExtendLowI32x4S, ssa.OpWasmI64x2ExtendLowI32x4U, + ssa.OpWasmI32x4ExtendLowI16x8S, ssa.OpWasmI32x4ExtendLowI16x8U, ssa.OpWasmI16x8ExtendLowI8x16S, + ssa.OpWasmI16x8ExtendLowI8x16U, ssa.OpWasmF32x4Floor, ssa.OpWasmF64x2Floor, + ssa.OpWasmI8x16Neg, ssa.OpWasmI16x8Neg, ssa.OpWasmI32x4Neg, + ssa.OpWasmF32x4Neg, ssa.OpWasmI64x2Neg, ssa.OpWasmF64x2Neg, + ssa.OpWasmV128Not, ssa.OpWasmI8x16Popcnt, ssa.OpWasmF32x4Nearest, + ssa.OpWasmF64x2Nearest, ssa.OpWasmF32x4Sqrt, ssa.OpWasmF64x2Sqrt, + ssa.OpWasmF32x4Trunc, ssa.OpWasmF64x2Trunc: + getValue128(s, v.Args[0]) + s.Prog(v.Op.Asm()) + case ssa.OpWasmI16x8Q15MulrSatS, ssa.OpWasmI16x8RelaxedQ15MulrS, ssa.OpWasmF32x4Pmax, + ssa.OpWasmF32x4Pmin, ssa.OpWasmF32x4RelaxedMax, ssa.OpWasmF32x4RelaxedMin, + ssa.OpWasmF64x2Pmax, ssa.OpWasmF64x2Pmin, ssa.OpWasmF64x2RelaxedMax, + ssa.OpWasmF64x2RelaxedMin, ssa.OpWasmI8x16Add, ssa.OpWasmI16x8Add, + ssa.OpWasmI32x4Add, ssa.OpWasmF32x4Add, ssa.OpWasmI64x2Add, + ssa.OpWasmF64x2Add, ssa.OpWasmI8x16AddSatS, ssa.OpWasmI8x16AddSatU, + ssa.OpWasmI16x8AddSatS, ssa.OpWasmI16x8AddSatU, ssa.OpWasmV128And, + ssa.OpWasmV128Andnot, ssa.OpWasmI8x16AvgrU, ssa.OpWasmI16x8AvgrU, + ssa.OpWasmF32x4Div, ssa.OpWasmF64x2Div, ssa.OpWasmI8x16Eq, + ssa.OpWasmI16x8Eq, ssa.OpWasmI32x4Eq, ssa.OpWasmF32x4Eq, + ssa.OpWasmI64x2Eq, ssa.OpWasmF64x2Eq, ssa.OpWasmI8x16GtS, + ssa.OpWasmI8x16GtU, ssa.OpWasmI16x8GtS, ssa.OpWasmI16x8GtU, + ssa.OpWasmI32x4GtS, ssa.OpWasmI32x4GtU, ssa.OpWasmF32x4Gt, + ssa.OpWasmI64x2GtS, ssa.OpWasmF64x2Gt, ssa.OpWasmI8x16GeS, + ssa.OpWasmI8x16GeU, ssa.OpWasmI16x8GeS, ssa.OpWasmI16x8GeU, + ssa.OpWasmI32x4GeS, ssa.OpWasmI32x4GeU, ssa.OpWasmF32x4Ge, + ssa.OpWasmI64x2GeS, ssa.OpWasmF64x2Ge, ssa.OpWasmI8x16LtS, + ssa.OpWasmI8x16LtU, ssa.OpWasmI16x8LtS, ssa.OpWasmI16x8LtU, + ssa.OpWasmI32x4LtS, ssa.OpWasmI32x4LtU, ssa.OpWasmF32x4Lt, + ssa.OpWasmI64x2LtS, ssa.OpWasmF64x2Lt, ssa.OpWasmI8x16LeS, + ssa.OpWasmI8x16LeU, ssa.OpWasmI16x8LeS, ssa.OpWasmI16x8LeU, + ssa.OpWasmI32x4LeS, ssa.OpWasmI32x4LeU, ssa.OpWasmF32x4Le, + ssa.OpWasmI64x2LeS, ssa.OpWasmF64x2Le, ssa.OpWasmI8x16Swizzle, + ssa.OpWasmI8x16MaxS, ssa.OpWasmI8x16MaxU, ssa.OpWasmI16x8MaxS, + ssa.OpWasmI16x8MaxU, ssa.OpWasmI32x4MaxS, ssa.OpWasmI32x4MaxU, + ssa.OpWasmF32x4Max, ssa.OpWasmF64x2Max, ssa.OpWasmI8x16MinS, + ssa.OpWasmI8x16MinU, ssa.OpWasmI16x8MinS, ssa.OpWasmI16x8MinU, + ssa.OpWasmI32x4MinS, ssa.OpWasmI32x4MinU, ssa.OpWasmF32x4Min, + ssa.OpWasmF64x2Min, ssa.OpWasmI16x8Mul, ssa.OpWasmI32x4Mul, + ssa.OpWasmF32x4Mul, ssa.OpWasmI64x2Mul, ssa.OpWasmF64x2Mul, + ssa.OpWasmI16x8ExtmulHighI8x16S, ssa.OpWasmI16x8ExtmulHighI8x16U, ssa.OpWasmI32x4ExtmulHighI16x8S, + ssa.OpWasmI32x4ExtmulHighI16x8U, ssa.OpWasmI64x2ExtmulHighI32x4S, ssa.OpWasmI64x2ExtmulHighI32x4U, + ssa.OpWasmI16x8ExtmulLowI8x16S, ssa.OpWasmI16x8ExtmulLowI8x16U, ssa.OpWasmI32x4ExtmulLowI16x8S, + ssa.OpWasmI32x4ExtmulLowI16x8U, ssa.OpWasmI64x2ExtmulLowI32x4S, ssa.OpWasmI64x2ExtmulLowI32x4U, + ssa.OpWasmI8x16Ne, ssa.OpWasmI16x8Ne, ssa.OpWasmI32x4Ne, + ssa.OpWasmF32x4Ne, ssa.OpWasmI64x2Ne, ssa.OpWasmF64x2Ne, + ssa.OpWasmV128Or, ssa.OpWasmI8x16Sub, ssa.OpWasmI16x8Sub, + ssa.OpWasmI32x4Sub, ssa.OpWasmF32x4Sub, ssa.OpWasmI64x2Sub, + ssa.OpWasmF64x2Sub, ssa.OpWasmI8x16SubSatS, ssa.OpWasmI8x16SubSatU, + ssa.OpWasmI16x8SubSatS, ssa.OpWasmI16x8SubSatU, ssa.OpWasmV128Xor: + getValue128(s, v.Args[0]) + getValue128(s, v.Args[1]) + s.Prog(v.Op.Asm()) + case ssa.OpWasmI8x16Shl, ssa.OpWasmI16x8Shl, ssa.OpWasmI32x4Shl, + ssa.OpWasmI64x2Shl, ssa.OpWasmI8x16ShrS, ssa.OpWasmI8x16ShrU, + ssa.OpWasmI16x8ShrS, ssa.OpWasmI16x8ShrU, ssa.OpWasmI32x4ShrS, + ssa.OpWasmI32x4ShrU, ssa.OpWasmI64x2ShrS, ssa.OpWasmI64x2ShrU: + getValue128(s, v.Args[0]) + getValue32(s, v.Args[1]) + s.Prog(v.Op.Asm()) + case ssa.OpWasmV128Bitselect: + getValue128(s, v.Args[0]) + getValue128(s, v.Args[1]) + getValue128(s, v.Args[2]) + s.Prog(v.Op.Asm()) + + default: + return false + } + return true +} diff --git a/src/cmd/compile/internal/wasm/ssa.go b/src/cmd/compile/internal/wasm/ssa.go index 1e3b318e8c9fe0..4aa0a2018e0b31 100644 --- a/src/cmd/compile/internal/wasm/ssa.go +++ b/src/cmd/compile/internal/wasm/ssa.go @@ -203,7 +203,7 @@ func ssaGenBlock(s *ssagen.State, b, next *ssa.Block) { case ssa.BlockExit, ssa.BlockRetJmp: default: - panic("unexpected block") + base.FatalfAt(b.Pos, "unexpected block b%d, kind=%v", b.ID, b.Kind) } // Entry point for the next block. Used by the JMP in goToBlock. @@ -216,7 +216,7 @@ func ssaGenBlock(s *ssagen.State, b, next *ssa.Block) { func ssaGenValue(s *ssagen.State, v *ssa.Value) { switch v.Op { - case ssa.OpWasmLoweredStaticCall, ssa.OpWasmLoweredClosureCall, ssa.OpWasmLoweredInterCall, ssa.OpWasmLoweredTailCall: + case ssa.OpWasmLoweredStaticCall, ssa.OpWasmLoweredClosureCall, ssa.OpWasmLoweredInterCall, ssa.OpWasmLoweredTailCall, ssa.OpWasmLoweredTailCallInter: s.PrepareCall(v) if call, ok := v.Aux.(*ssa.AuxCall); ok && call.Fn == ir.Syms.Deferreturn { // The runtime needs to inject jumps to @@ -243,6 +243,9 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p := s.Prog(obj.ACALL) p.To = obj.Addr{Type: obj.TYPE_NONE} p.Pos = v.Pos + if v.Op == ssa.OpWasmLoweredTailCallInter { + p.As = obj.ARET + } } case ssa.OpWasmLoweredMove: @@ -283,9 +286,19 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p := s.Prog(v.Op.Asm()) p.To = obj.Addr{Type: obj.TYPE_CONST, Offset: v.AuxInt} + case ssa.OpWasmV128Store: + getValue32(s, v.Args[0]) + getValue128(s, v.Args[1]) + p := s.Prog(v.Op.Asm()) + p.To = obj.Addr{Type: obj.TYPE_CONST, Offset: v.AuxInt} + case ssa.OpStoreReg: getReg(s, wasm.REG_SP) - getValue64(s, v.Args[0]) + if v.Type.Size() == 16 { + getValue128(s, v.Args[0]) + } else { + getValue64(s, v.Args[0]) + } p := s.Prog(storeOp(v.Type)) ssagen.AddrAuto(&p.To, v) @@ -362,6 +375,12 @@ func ssaGenValueOnStack(s *ssagen.State, v *ssa.Value, extend bool) { getValue32(s, v.Args[2]) s.Prog(v.Op.Asm()) + case ssa.OpWasmSelectV: + getValue128(s, v.Args[0]) + getValue128(s, v.Args[1]) + getValue32(s, v.Args[2]) + s.Prog(v.Op.Asm()) + case ssa.OpWasmI64AddConst: getValue64(s, v.Args[0]) i64Const(s, v.AuxInt) @@ -376,7 +395,8 @@ func ssaGenValueOnStack(s *ssagen.State, v *ssa.Value, extend bool) { case ssa.OpWasmF64Const: f64Const(s, v.AuxFloat()) - case ssa.OpWasmI64Load8U, ssa.OpWasmI64Load8S, ssa.OpWasmI64Load16U, ssa.OpWasmI64Load16S, ssa.OpWasmI64Load32U, ssa.OpWasmI64Load32S, ssa.OpWasmI64Load, ssa.OpWasmF32Load, ssa.OpWasmF64Load: + case ssa.OpWasmI64Load8U, ssa.OpWasmI64Load8S, ssa.OpWasmI64Load16U, ssa.OpWasmI64Load16S, + ssa.OpWasmI64Load32U, ssa.OpWasmI64Load32S, ssa.OpWasmI64Load, ssa.OpWasmF32Load, ssa.OpWasmF64Load, ssa.OpWasmV128Load: getValue32(s, v.Args[0]) p := s.Prog(v.Op.Asm()) p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: v.AuxInt} @@ -447,24 +467,37 @@ func ssaGenValueOnStack(s *ssagen.State, v *ssa.Value, extend bool) { getValue64(s, v.Args[0]) s.Prog(v.Op.Asm()) + case ssa.OpWasmV128Zero: + p := s.Prog(wasm.AV128Const) + p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: 0} + p.To = obj.Addr{Type: obj.TYPE_CONST, Offset: 0} + case ssa.OpLoadReg: p := s.Prog(loadOp(v.Type)) ssagen.AddrAuto(&p.From, v.Args[0]) case ssa.OpCopy: - getValue64(s, v.Args[0]) + if v.Type.Size() == 16 { + getValue128(s, v.Args[0]) + } else { + getValue64(s, v.Args[0]) + } default: - v.Fatalf("unexpected op: %s", v.Op) + if !ssaGenSIMDValue(s, v, extend) { + v.Fatalf("unexpected op: %s", v.Op) + } } } -func isCmp(v *ssa.Value) bool { +func isAlready32(v *ssa.Value) bool { switch v.Op { case ssa.OpWasmI64Eqz, ssa.OpWasmI64Eq, ssa.OpWasmI64Ne, ssa.OpWasmI64LtS, ssa.OpWasmI64LtU, ssa.OpWasmI64GtS, ssa.OpWasmI64GtU, ssa.OpWasmI64LeS, ssa.OpWasmI64LeU, ssa.OpWasmI64GeS, ssa.OpWasmI64GeU, ssa.OpWasmF32Eq, ssa.OpWasmF32Ne, ssa.OpWasmF32Lt, ssa.OpWasmF32Gt, ssa.OpWasmF32Le, ssa.OpWasmF32Ge, - ssa.OpWasmF64Eq, ssa.OpWasmF64Ne, ssa.OpWasmF64Lt, ssa.OpWasmF64Gt, ssa.OpWasmF64Le, ssa.OpWasmF64Ge: + ssa.OpWasmF64Eq, ssa.OpWasmF64Ne, ssa.OpWasmF64Lt, ssa.OpWasmF64Gt, ssa.OpWasmF64Le, ssa.OpWasmF64Ge, + ssa.OpWasmI8x16ExtractLaneS, ssa.OpWasmI16x8ExtractLaneS, ssa.OpWasmI32x4ExtractLane, + ssa.OpWasmI8x16ExtractLaneU, ssa.OpWasmI16x8ExtractLaneU: return true default: return false @@ -475,7 +508,7 @@ func getValue32(s *ssagen.State, v *ssa.Value) { if v.OnWasmStack { s.OnWasmStackSkipped-- ssaGenValueOnStack(s, v, false) - if !isCmp(v) { + if !isAlready32(v) { s.Prog(wasm.AI32WrapI64) } return @@ -502,6 +535,28 @@ func getValue64(s *ssagen.State, v *ssa.Value) { } } +func getValue128(s *ssagen.State, v *ssa.Value) { + if v.OnWasmStack { + s.OnWasmStackSkipped-- + ssaGenValueOnStack(s, v, true) + return + } + + reg := v.Reg() + getReg(s, reg) +} + +func getValueFxx(s *ssagen.State, v *ssa.Value) { + if v.OnWasmStack { + s.OnWasmStackSkipped-- + ssaGenValueOnStack(s, v, true) + return + } + + reg := v.Reg() + getReg(s, reg) +} + func i32Const(s *ssagen.State, val int32) { p := s.Prog(wasm.AI32Const) p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: int64(val)} @@ -562,6 +617,8 @@ func loadOp(t *types.Type) obj.As { return wasm.AI64Load32U case 8: return wasm.AI64Load + case 16: + return wasm.AV128Load default: panic("bad load type") } @@ -588,6 +645,8 @@ func storeOp(t *types.Type) obj.As { return wasm.AI64Store32 case 8: return wasm.AI64Store + case 16: + return wasm.AV128Store default: panic("bad store type") } diff --git a/src/cmd/compile/internal/x86/ssa.go b/src/cmd/compile/internal/x86/ssa.go index d0aad088496351..4ca2a12349217e 100644 --- a/src/cmd/compile/internal/x86/ssa.go +++ b/src/cmd/compile/internal/x86/ssa.go @@ -167,7 +167,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { ssa.Op386SBBL: opregreg(s, v.Op.Asm(), v.Reg(), v.Args[1].Reg()) - case ssa.Op386ADDLcarry, ssa.Op386SUBLcarry: + case ssa.Op386ADDLcarry, ssa.Op386ADCLcarry, ssa.Op386SUBLcarry: // output 0 is carry/borrow, output 1 is the low 32 bits. opregreg(s, v.Op.Asm(), v.Reg0(), v.Args[1].Reg()) @@ -903,7 +903,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { case ssa.Op386CALLstatic, ssa.Op386CALLclosure, ssa.Op386CALLinter: s.Call(v) - case ssa.Op386CALLtail: + case ssa.Op386CALLtail, ssa.Op386CALLtailinter: s.TailCall(v) case ssa.Op386NEGL, ssa.Op386BSWAPL, diff --git a/src/cmd/compile/testdata/script/closure_name.txt b/src/cmd/compile/testdata/script/closure_name.txt new file mode 100644 index 00000000000000..0ec1c8d9dece27 --- /dev/null +++ b/src/cmd/compile/testdata/script/closure_name.txt @@ -0,0 +1,80 @@ +# Test closure naming with inlining. + +go build -gcflags=-S -o x.exe x.go +# original closure name should appear +stderr 'adder\.func1' +# inlining should not cause the closure to have longer names +! stderr 'F1\.adder\.func1' +! stderr 'F2\.adder\.func1' +# the counter should match the original one, regardless of +# how many closures are in the inlined caller +! stderr 'adder\.func2' +! stderr 'adder\.func3' +! stderr 'adder\.func4' +# user closure counter and range func counter should not +# interfere +stderr 'ranger\.func1' +stderr 'ranger-range1' +stderr 'ranger\.func2' + +go tool nm x.exe +# same applies to the nm output +stdout 'adder\.func1' +! stdout 'F1\.adder\.func1' +! stdout 'F2\.adder\.func1' +! stdout 'adder\.func2' +! stdout 'adder\.func3' +! stdout 'adder\.func4' +stdout 'ranger\.func1' +stdout 'ranger-range1' +stdout 'ranger\.func2' +# the inline hash should not make into the final binary +! stdout 'adder\.func1#' + +-- x.go -- +package main + +// keep prevents closures being optimized out +// +//go:noinline +func keep(x func()) func() { return x } + +func adder(n int) func(int) int { + return func(x int) int { return x + n } +} + +//go:noinline +func F1() func(int) int { + // adder is inlined into F1, along with its closure. + // The closure should still be named addr.func1. + return adder(1) +} + +//go:noinline +func F2() func(int) int { + keep(func() {}) + keep(func() {}) + keep(func() {}) + // Closures in the outer function should not change + // the counter. It should still be addr.func1. + return adder(2) +} + +//go:noinline +func iter(yield func(int) bool) { + _ = yield(1) && yield(2) && yield(3) +} + +func ranger() func(int) int { + keep(func() {}) // func1 + s := 0 + for x := range iter { // range1 + s += x + } + return func(x int) int { return s + x } // func2 +} + +func main() { + x := 1 + F1()(F2()(ranger()(x))) +} diff --git a/src/cmd/compile/testdata/script/issue77033.txt b/src/cmd/compile/testdata/script/issue77033.txt new file mode 100644 index 00000000000000..40d4a95405cd8a --- /dev/null +++ b/src/cmd/compile/testdata/script/issue77033.txt @@ -0,0 +1,40 @@ +go test -bench=Foo -cpuprofile=default.pgo -timeout=30s +go test -bench=Foo -pgo=default.pgo -timeout=30s +! stdout 'FAIL' + +-- main_test.go -- +package main + +import ( + "testing" +) + +var a int + +func save(x int) { + a = x +} + +func foo() { + for i := range yield1 { + defer save(i) + } +} + +func yield1(yield func(int) bool) { + yield(1) +} + +func BenchmarkFoo(b *testing.B) { + for i := 0; i < b.N; i++ { + foo() + } + if a != 1 { + b.Fatalf("a = %d; want 1", a) + } +} + +-- go.mod -- +module demo + +go 1.24 diff --git a/src/cmd/compile/testdata/script/issue80258.txt b/src/cmd/compile/testdata/script/issue80258.txt new file mode 100644 index 00000000000000..d33c882ff19e74 --- /dev/null +++ b/src/cmd/compile/testdata/script/issue80258.txt @@ -0,0 +1,25 @@ +go build main.go +! stdout . +! stderr . + +-- main.go -- +package main + +import "m/p" + +func main() { + var _ p.T +} + +-- go.mod -- +module m + +go 1.27 + +-- p/p.go -- + +package p + +type T int + +func (T) M[P T]() {} diff --git a/src/cmd/covdata/covdata.go b/src/cmd/covdata/covdata.go index 122ad28b5cafce..b88b81799e6cda 100644 --- a/src/cmd/covdata/covdata.go +++ b/src/cmd/covdata/covdata.go @@ -42,14 +42,14 @@ func Exit(code int) { os.Exit(code) } -func dbgtrace(vlevel int, s string, a ...interface{}) { +func dbgtrace(vlevel int, s string, a ...any) { if *verbflag >= vlevel { fmt.Printf(s, a...) fmt.Printf("\n") } } -func warn(s string, a ...interface{}) { +func warn(s string, a ...any) { fmt.Fprintf(os.Stderr, "warning: ") fmt.Fprintf(os.Stderr, s, a...) fmt.Fprintf(os.Stderr, "\n") @@ -58,7 +58,7 @@ func warn(s string, a ...interface{}) { } } -func fatal(s string, a ...interface{}) { +func fatal(s string, a ...any) { fmt.Fprintf(os.Stderr, "error: ") fmt.Fprintf(os.Stderr, s, a...) fmt.Fprintf(os.Stderr, "\n") diff --git a/src/cmd/covdata/tool_test.go b/src/cmd/covdata/tool_test.go index 730adf4c8e62e0..ee54de623eff08 100644 --- a/src/cmd/covdata/tool_test.go +++ b/src/cmd/covdata/tool_test.go @@ -50,7 +50,7 @@ func TestMain(m *testing.M) { fmt.Fprintf(os.Stderr, "debug: preserving tmpdir %s\n", topTmpdir) } os.Setenv("CMDCOVDATA_TEST_RUN_MAIN", "true") - os.Exit(m.Run()) + m.Run() } var tdmu sync.Mutex @@ -414,7 +414,7 @@ func testTextfmt(t *testing.T, s state) { dumplines(lines[0:10]) t.Errorf("textfmt: want %s got %s", want0, lines[0]) } - want1 := mainPkgPath + "/prog1.go:13.14,15.2 1 1" + want1 := mainPkgPath + "/prog1.go:14.2,15.1 1 1" if lines[1] != want1 { dumplines(lines[0:10]) t.Errorf("textfmt: want %s got %s", want1, lines[1]) @@ -545,7 +545,7 @@ func testMergeSimple(t *testing.T, s state, indir1, indir2, tag string) { }, { tag: "third function unit 0", - re: regexp.MustCompile(`^0: L23:C23 -- L24:C12 NS=1 = (\d+)$`), + re: regexp.MustCompile(`^0: L24:C2 -- L24:C12 NS=1 = (\d+)$`), nonzero: true, }, { @@ -555,7 +555,7 @@ func testMergeSimple(t *testing.T, s state, indir1, indir2, tag string) { }, { tag: "third function unit 2", - re: regexp.MustCompile(`^2: L24:C12 -- L26:C3 NS=1 = (\d+)$`), + re: regexp.MustCompile(`^2: L25:C3 -- L26:C1 NS=1 = (\d+)$`), nonzero: true, }, } @@ -727,7 +727,7 @@ func testSubtract(t *testing.T, s state) { }, { tag: "third function unit 0", - re: regexp.MustCompile(`^0: L23:C23 -- L24:C12 NS=1 = (\d+)$`), + re: regexp.MustCompile(`^0: L24:C2 -- L24:C12 NS=1 = (\d+)$`), zero: true, }, { @@ -737,7 +737,7 @@ func testSubtract(t *testing.T, s state) { }, { tag: "third function unit 2", - re: regexp.MustCompile(`^2: L24:C12 -- L26:C3 NS=1 = (\d+)$`), + re: regexp.MustCompile(`^2: L25:C3 -- L26:C1 NS=1 = (\d+)$`), zero: true, }, } diff --git a/src/cmd/cover/cover.go b/src/cmd/cover/cover.go index 9207fa0e8b0987..82c419483d0f69 100644 --- a/src/cmd/cover/cover.go +++ b/src/cmd/cover/cover.go @@ -13,6 +13,7 @@ import ( "fmt" "go/ast" "go/parser" + "go/scanner" "go/token" "internal/coverage" "internal/coverage/encodemeta" @@ -266,6 +267,156 @@ type File struct { pkg *Package } +// Range represents a contiguous range of executable code within a basic block. +type Range struct { + pos token.Pos + end token.Pos +} + +// codeRanges analyzes a block range and returns the sub-ranges that contain +// executable code, excluding comment-only and blank lines. +// If no executable code is found, it returns a single zero-width range at +// start, so that callers always get at least one range (required by pkgcfg +// mode, which needs a counter unit for every function body). +func (f *File) codeRanges(start, end token.Pos) []Range { + var ( + startOffset = f.offset(start) + endOffset = f.offset(end) + src = f.content[startOffset:endOffset] + origFile = f.fset.File(start) + ) + + // Create a temporary File for scanning this block. + // We use a separate file because we're scanning a slice of the + // original source, so positions in scanFile are relative to the + // block start, not the original file. + scanFile := token.NewFileSet().AddFile("", -1, len(src)) + + var s scanner.Scanner + s.Init(scanFile, src, nil, 0) + + // Build ranges in a single pass through the token stream. + // We track the last line known to contain code (prevEndLine). + // When the next token appears on a line beyond prevEndLine+1, + // a gap (comment or blank lines) has been detected: close the + // current range and start a new one. Using the token's position + // directly (rather than the line start) ensures counter insertion + // lands after any closing "*/" on that line. + var ranges []Range + var codeStart token.Pos // start of current code range (in origFile) + prevEndLine := 0 // last line with code; 0 means no code yet + + for { + pos, tok, lit := s.Scan() + if tok == token.EOF { + break + } + + // Skip braces and automatic semicolons: braces are block + // delimiters, not executable code. The Go spec + // (https://go.dev/ref/spec#Semicolons) requires the scanner + // to insert semicolons (with lit == "\n") after }, ), ], etc. + // These are always on lines already marked by real tokens, + // except for lone "}" lines. Skipping both prevents a lone + // "}" from being treated as a separate code range, which + // would cause counter insertion after return statements. + if tok == token.LBRACE || tok == token.RBRACE { + continue + } + if tok == token.SEMICOLON && lit == "\n" { + continue + } + + // Use PositionFor with adjusted=false to ignore //line directives. + startLine := scanFile.PositionFor(pos, false).Line + endLine := startLine + if tok == token.STRING { + // Only string literals can span multiple lines. + // TODO(adonovan): simplify when https://go.dev/issue/74958 is resolved. + endLine = scanFile.PositionFor(pos+token.Pos(len(lit)), false).Line + } + + if prevEndLine == 0 { + // First code token — start the first range. + codeStart = origFile.Pos(startOffset + scanFile.Offset(pos)) + } else if startLine > prevEndLine+1 { + // Gap detected — close previous range, start new one. + codeEnd := origFile.Pos(startOffset + scanFile.Offset(scanFile.LineStart(prevEndLine+1))) + ranges = append(ranges, Range{pos: codeStart, end: codeEnd}) + codeStart = origFile.Pos(startOffset + scanFile.Offset(pos)) + } + + if endLine > prevEndLine { + prevEndLine = endLine + } + } + + // Close any open code range at the end. + if prevEndLine > 0 { + if prevEndLine < scanFile.LineCount() { + // There are non-code lines after the last code line + // (e.g., a lone "}"). Close at the next line's start. + codeEnd := origFile.Pos(startOffset + scanFile.Offset(scanFile.LineStart(prevEndLine+1))) + ranges = append(ranges, Range{pos: codeStart, end: codeEnd}) + } else { + ranges = append(ranges, Range{pos: codeStart, end: end}) + } + } + + // If no code was found, return a zero-width range so that callers + // still get a counter (needed for pkgcfg function registration) + // but the range doesn't visually cover any source lines. + if len(ranges) == 0 { + return []Range{{pos: start, end: start}} + } + + return ranges +} + +// insideStatement reports whether pos falls strictly inside +// (not at the start of) any statement in stmts. +func insideStatement(pos token.Pos, stmts []ast.Stmt) bool { + // Binary search for the first statement starting at or after pos. + i, _ := slices.BinarySearchFunc(stmts, pos, func(s ast.Stmt, p token.Pos) int { + return cmp.Compare(s.Pos(), p) + }) + // Check if pos falls inside the preceding statement. + return i > 0 && pos < stmts[i-1].End() +} + +// mergeRangesWithinStatements merges consecutive ranges when a later range's +// start position falls strictly inside a statement. This prevents counter +// insertion inside multi-line statements such as const (...) blocks. +type rangeWithStatements struct { + Range + numStmt int +} + +func mergeRangesWithinStatements(ranges []Range, stmts []ast.Stmt) []rangeWithStatements { + merged := make([]rangeWithStatements, 0, len(ranges)) + for _, r := range ranges { + // Statements are sorted by source position, so use binary search to + // find the statements whose positions fall within this range. + first, _ := slices.BinarySearchFunc(stmts, r.pos, func(s ast.Stmt, p token.Pos) int { + return cmp.Compare(s.Pos(), p) + }) + last, _ := slices.BinarySearchFunc(stmts, r.end, func(s ast.Stmt, p token.Pos) int { + return cmp.Compare(s.Pos(), p) + }) + numStmt := last - first + + if len(merged) > 0 && insideStatement(r.pos, stmts) { + // Extend the previous range to cover this one. + last := &merged[len(merged)-1] + last.end = r.end + last.numStmt += numStmt + } else { + merged = append(merged, rangeWithStatements{Range: r, numStmt: numStmt}) + } + } + return merged +} + // findText finds text in the original source, starting at pos. // It correctly skips over comments and assumes it need not // handle quoted strings. @@ -636,7 +787,7 @@ func (p *Package) annotateFile(name string, fd io.Writer) { if err != nil { log.Fatalf("cover: %s: %s", name, err) } - parsedFile, err := parser.ParseFile(fset, name, content, parser.ParseComments) + parsedFile, err := parser.ParseFile(fset, name, content, parser.ParseComments|parser.SkipObjectResolution) if err != nil { log.Fatalf("cover: %s: %s", name, err) } @@ -720,8 +871,9 @@ func (f *File) newCounter(start, end token.Pos, numStmt int) string { panic("internal error: counter var unset") } stmt = counterStmt(f, fmt.Sprintf("%s[%d]", f.fn.counterVar, slot)) - stpos := f.fset.Position(start) - enpos := f.fset.Position(end) + // Physical positions, ignoring //line directives. + stpos := f.position(start) + enpos := f.position(end) stpos, enpos = dedup(stpos, enpos) unit := coverage.CoverableUnit{ StLine: uint32(stpos.Line), @@ -755,7 +907,8 @@ func (f *File) addCounters(pos, insertPos, blockEnd token.Pos, list []ast.Stmt, // Special case: make sure we add a counter to an empty block. Can't do this below // or we will add a counter to an empty statement list after, say, a return statement. if len(list) == 0 { - f.edit.Insert(f.offset(insertPos), f.newCounter(insertPos, blockEnd, 0)+";") + r := f.codeRanges(insertPos, blockEnd)[0] + f.edit.Insert(f.offset(r.pos), f.newCounter(r.pos, r.end, 0)+";") return } // Make a copy of the list, as we may mutate it and should leave the @@ -805,7 +958,16 @@ func (f *File) addCounters(pos, insertPos, blockEnd token.Pos, list []ast.Stmt, end = blockEnd } if pos != end { // Can have no source to cover if e.g. blocks abut. - f.edit.Insert(f.offset(insertPos), f.newCounter(pos, end, last)+";") + // Create counters only for executable code ranges. + // Merge back ranges that fall inside a statement to avoid + // inserting counters inside multi-line constructs (e.g. const blocks). + for i, r := range mergeRangesWithinStatements(f.codeRanges(pos, end), list[:last]) { + insertOffset := f.offset(r.pos) + if i == 0 { + insertOffset = f.offset(insertPos) + } + f.edit.Insert(insertOffset, f.newCounter(r.pos, r.end, r.numStmt)+";") + } } list = list[last:] if len(list) == 0 { @@ -976,9 +1138,14 @@ type block1 struct { index int } +// position returns the Position for pos, ignoring //line directives. +func (f *File) position(pos token.Pos) token.Position { + return f.fset.PositionFor(pos, false) +} + // offset translates a token position into a 0-indexed byte offset. func (f *File) offset(pos token.Pos) int { - return f.fset.Position(pos).Offset + return f.position(pos).Offset } // addVariables adds to the end of the file the declarations to set up the counter and position variables. @@ -1020,8 +1187,9 @@ func (f *File) addVariables(w io.Writer) { // - 32-bit ending line number // - (16 bit ending column number << 16) | (16-bit starting column number). for i, block := range f.blocks { - start := f.fset.Position(block.startByte) - end := f.fset.Position(block.endByte) + // Physical positions, ignoring //line directives. + start := f.position(block.startByte) + end := f.position(block.endByte) start, end = dedup(start, end) diff --git a/src/cmd/cover/cover_test.go b/src/cmd/cover/cover_test.go index 431c0560f6eb23..1991f140c79957 100644 --- a/src/cmd/cover/cover_test.go +++ b/src/cmd/cover/cover_test.go @@ -8,6 +8,7 @@ import ( "bufio" "bytes" cmdcover "cmd/cover" + "cmp" "flag" "fmt" "go/ast" @@ -19,6 +20,8 @@ import ( "os/exec" "path/filepath" "regexp" + "slices" + "strconv" "strings" "sync" "testing" @@ -87,7 +90,7 @@ func TestMain(m *testing.M) { fmt.Fprintf(os.Stderr, "debug: preserving tmpdir %s\n", topTmpdir) } os.Setenv("CMDCOVER_TEST_RUN_MAIN", "normal") - os.Exit(m.Run()) + m.Run() } var tdmu sync.Mutex @@ -256,7 +259,7 @@ func TestDirectives(t *testing.T) { // come before the beginning of the named declaration and after the end // of the previous declaration. fset := token.NewFileSet() - astFile, err := parser.ParseFile(fset, testDirectives, output, 0) + astFile, err := parser.ParseFile(fset, testDirectives, output, parser.SkipObjectResolution) if err != nil { t.Fatal(err) } @@ -638,3 +641,276 @@ func main() { t.Errorf("unexpected success; want failure due to newline in file path") } } + +func TestAlignment(t *testing.T) { + // Test that cover data structures are aligned appropriately. See issue 58936. + testenv.MustHaveGoRun(t) + t.Parallel() + + cmd := testenv.Command(t, testenv.GoToolPath(t), "test", "-cover", filepath.Join(testdata, "align.go"), filepath.Join(testdata, "align_test.go")) + run(cmd, t) +} + +// lineRange represents a coverage range as a pair of line numbers (1-indexed, inclusive). +type lineRange struct { + start, end int +} + +// parseBrackets strips bracket markers (U+00AB «, U+00BB ») from src, +// returning the cleaned Go source and a list of expected coverage ranges +// as line number pairs (1-indexed, inclusive). +func parseBrackets(src []byte) ([]byte, []lineRange) { + const ( + open = "\u00ab" // « + close = "\u00bb" // » + ) + var ( + cleaned []byte + ranges []lineRange + stack []int // stack of open marker byte positions in cleaned + ) + i := 0 + for i < len(src) { + if bytes.HasPrefix(src[i:], []byte(open)) { + stack = append(stack, len(cleaned)) + i += len(open) + } else if bytes.HasPrefix(src[i:], []byte(close)) { + if len(stack) == 0 { + panic("unmatched close bracket at offset " + strconv.Itoa(i)) + } + startPos := stack[len(stack)-1] + stack = stack[:len(stack)-1] + endPos := len(cleaned) + // Convert byte positions to line numbers. + startLine := 1 + bytes.Count(cleaned[:startPos], []byte{'\n'}) + endLine := 1 + bytes.Count(cleaned[:endPos], []byte{'\n'}) + // If endPos is at the start of a line (after \n), the range + // actually ended on the previous line. + if endPos > 0 && cleaned[endPos-1] == '\n' { + endLine-- + } + if endLine < startLine { + endLine = startLine + } + ranges = append(ranges, lineRange{startLine, endLine}) + i += len(close) + } else { + cleaned = append(cleaned, src[i]) + i++ + } + } + if len(stack) != 0 { + panic("unmatched open bracket(s)") + } + return cleaned, ranges +} + +// coverRanges runs the cover tool on src and returns the coverage ranges +// as line number pairs (1-indexed, inclusive). +func coverRanges(t *testing.T, src []byte) []lineRange { + t.Helper() + tmpdir := t.TempDir() + srcPath := filepath.Join(tmpdir, "test.go") + if err := os.WriteFile(srcPath, src, 0666); err != nil { + t.Fatalf("writing test file: %v", err) + } + + cmd := testenv.Command(t, testcover(t), "-mode=set", srcPath) + out, err := cmd.Output() + if err != nil { + t.Fatalf("cover failed: %v\nOutput: %s", err, out) + } + + outStr := string(out) + // Skip the //line directive that cover adds at the top. + if _, after, ok := strings.Cut(outStr, "\n"); ok { + outStr = after + } + + // Parse the coverage struct's Pos array to extract ranges. + // Format: startLine, endLine, (endCol<<16)|startCol, // [index] + re := regexp.MustCompile(`(\d+), (\d+), (0x[0-9a-f]+), // \[\d+\]`) + matches := re.FindAllStringSubmatch(outStr, -1) + + var result []lineRange + for _, m := range matches { + startLine, _ := strconv.Atoi(m[1]) + endLine, _ := strconv.Atoi(m[2]) + var packed int + fmt.Sscanf(m[3], "0x%x", &packed) + endCol := (packed >> 16) & 0xFFFF + startCol := packed & 0xFFFF + // Skip zero-width ranges (comment-only or empty blocks). + if startLine == endLine && startCol == endCol { + continue + } + // The range [start, end) is half-open. When endCol==1, the + // range reaches the beginning of endLine but includes no + // content on it, so the last covered line is endLine-1. + if endCol == 1 && endLine > startLine { + endLine-- + } + result = append(result, lineRange{startLine, endLine}) + } + return result +} + +// compareRanges is a test helper that compares got and want line ranges. +// Both slices are sorted before comparison since the cover tool's output +// order (AST walk order) may differ from source order (marker order). +func compareRanges(t *testing.T, src []byte, got, want []lineRange) { + t.Helper() + lines := strings.Split(string(src), "\n") + snippet := func(r lineRange) string { + start, end := r.start-1, r.end + if start < 0 { + start = 0 + } + if end > len(lines) { + end = len(lines) + } + s := strings.Join(lines[start:end], "\n") + if len(s) > 120 { + s = s[:117] + "..." + } + return s + } + + sortRanges := func(rs []lineRange) []lineRange { + s := append([]lineRange(nil), rs...) + slices.SortFunc(s, func(a, b lineRange) int { + if c := cmp.Compare(a.start, b.start); c != 0 { + return c + } + return cmp.Compare(a.end, b.end) + }) + return s + } + + gotSorted := sortRanges(got) + wantSorted := sortRanges(want) + + if len(gotSorted) != len(wantSorted) { + t.Errorf("got %d ranges, want %d", len(gotSorted), len(wantSorted)) + for i, r := range gotSorted { + t.Logf(" got[%d]: lines %d-%d %q", i, r.start, r.end, snippet(r)) + } + for i, r := range wantSorted { + t.Logf(" want[%d]: lines %d-%d %q", i, r.start, r.end, snippet(r)) + } + return + } + for i := range wantSorted { + if gotSorted[i] != wantSorted[i] { + t.Errorf("range %d: got lines %d-%d %q, want lines %d-%d %q", + i, gotSorted[i].start, gotSorted[i].end, snippet(gotSorted[i]), + wantSorted[i].start, wantSorted[i].end, snippet(wantSorted[i])) + } + } +} + +// TestCommentedOutCodeExclusion tests that comment-only and blank lines +// are excluded from coverage ranges using a bracket-marker testdata file. +func TestCommentedOutCodeExclusion(t *testing.T) { + testenv.MustHaveGoBuild(t) + + markedSrc, err := os.ReadFile(filepath.Join(testdata, "ranges", "ranges.go")) + if err != nil { + t.Fatal(err) + } + src, want := parseBrackets(markedSrc) + got := coverRanges(t, src) + compareRanges(t, src, got, want) +} + +// TestLineDirective verifies that //line directives don't affect coverage +// line number calculations (we use physical lines, not remapped ones). +func TestLineDirective(t *testing.T) { + testenv.MustHaveGoBuild(t) + + // Source with //line directive that would remap lines if not handled correctly. + testSrc := `package main + +import "fmt" + +func main() { + //line other.go:100 +« x := 1 +» // comment that should be excluded +« y := 2 +» //line other.go:200 +« fmt.Println(x, y) +»}` + + src, want := parseBrackets([]byte(testSrc)) + got := coverRanges(t, src) + compareRanges(t, src, got, want) +} + +// TestCommentExclusionBasic is a simple test verifying that a comment splits +// a single block into two separate coverage ranges. +func TestCommentExclusionBasic(t *testing.T) { + testenv.MustHaveGoBuild(t) + + testSrc := `package main + +func main() { +« x := 1 +» // this comment should split the block +« y := 2 +»}` + + src, want := parseBrackets([]byte(testSrc)) + got := coverRanges(t, src) + compareRanges(t, src, got, want) +} + +// TestStatementCountsAfterCommentSplit verifies that splitting a basic block +// at blank or comment-only lines preserves the statement count of the block. +func TestStatementCountsAfterCommentSplit(t *testing.T) { + testenv.MustHaveGoBuild(t) + + src := []byte(`package main + +func main() { + a := 1 + b := 2 + + c := 3 + d := 4 + + if a == 0 { + return + } + + println(a + b + c + d) +}`) + tmpdir := t.TempDir() + srcPath := filepath.Join(tmpdir, "test.go") + if err := os.WriteFile(srcPath, src, 0666); err != nil { + t.Fatal(err) + } + cmd := testenv.Command(t, testcover(t), "-mode=set", srcPath) + out, err := cmd.Output() + if err != nil { + t.Fatalf("cover failed: %v\nOutput: %s", err, out) + } + + re := regexp.MustCompile(`(?s)NumStmt: \[\d+\]uint16\{(.*?)\n\t\}`) + m := re.FindSubmatch(out) + if m == nil { + t.Fatalf("NumStmt array not found in output:\n%s", out) + } + var got []int + for _, entry := range regexp.MustCompile(`(?m)^\s*(\d+),`).FindAllSubmatch(m[1], -1) { + n, err := strconv.Atoi(string(entry[1])) + if err != nil { + t.Fatal(err) + } + got = append(got, n) + } + want := []int{2, 2, 1, 1, 1} + if !slices.Equal(got, want) { + t.Errorf("NumStmt = %v, want %v", got, want) + } +} diff --git a/src/cmd/cover/func.go b/src/cmd/cover/func.go index dffd3c1a0553ac..82e9d0c7ac9af1 100644 --- a/src/cmd/cover/func.go +++ b/src/cmd/cover/func.go @@ -93,7 +93,7 @@ func funcOutput(profile, outputFile string) error { // findFuncs parses the file and returns a slice of FuncExtent descriptors. func findFuncs(name string) ([]*FuncExtent, error) { fset := token.NewFileSet() - parsedFile, err := parser.ParseFile(fset, name, nil, 0) + parsedFile, err := parser.ParseFile(fset, name, nil, parser.SkipObjectResolution) if err != nil { return nil, err } diff --git a/src/cmd/cover/testdata/align.go b/src/cmd/cover/testdata/align.go new file mode 100644 index 00000000000000..2e8a45345de33c --- /dev/null +++ b/src/cmd/cover/testdata/align.go @@ -0,0 +1,11 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package p + +var badSlice [8265]byte + +func init() { + badSlice[0] = 4 +} diff --git a/src/cmd/cover/testdata/align_test.go b/src/cmd/cover/testdata/align_test.go new file mode 100644 index 00000000000000..e908c5a1cb3fa5 --- /dev/null +++ b/src/cmd/cover/testdata/align_test.go @@ -0,0 +1,10 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package p + +import "testing" + +func TestFoo(t *testing.T) { +} diff --git a/src/cmd/cover/testdata/html/html.golden b/src/cmd/cover/testdata/html/html.golden index 84377d1e2035a9..8cacf6ade1bdd0 100644 --- a/src/cmd/cover/testdata/html/html.golden +++ b/src/cmd/cover/testdata/html/html.golden @@ -1,6 +1,6 @@ // START f -func f() { - ch := make(chan int) +func f() { + ch := make(chan int) select { case <-ch: default: @@ -9,10 +9,10 @@ func f() { // END f // START g -func g() { - if false { - fmt.Printf("Hello") - } +func g() { + if false { + fmt.Printf("Hello") + } } // END g diff --git a/src/cmd/cover/testdata/main.go b/src/cmd/cover/testdata/main.go index be74b4aa655942..009de789f05185 100644 --- a/src/cmd/cover/testdata/main.go +++ b/src/cmd/cover/testdata/main.go @@ -94,12 +94,16 @@ func count(line uint32) (uint32, int) { // and we don't want that brace to steal the count for the condition on the "if". // Therefore we test for a perfect (lo==line && hi==line) match, but if we can't // find that we take the first imperfect match. + // When multiple perfect matches exist (e.g., an outer block counter and an inner + // function literal counter on the same line), prefer the last one: it corresponds + // to the innermost scope, which is the most specific counter for that line. index := -1 indexLo := uint32(1e9) + perfectIndex := -1 for i := range coverTest.Count { lo, hi := coverTest.Pos[3*i], coverTest.Pos[3*i+1] if lo == line && line == hi { - return coverTest.Count[i], i + perfectIndex = i } // Choose the earliest match (the counters are in unpredictable order). if lo <= line && line <= hi && indexLo > lo { @@ -107,6 +111,9 @@ func count(line uint32) (uint32, int) { indexLo = lo } } + if perfectIndex >= 0 { + return coverTest.Count[perfectIndex], perfectIndex + } if index == -1 { fmt.Fprintln(os.Stderr, "cover_test: no counter for line", line) PASS = false diff --git a/src/cmd/cover/testdata/ranges/ranges.go b/src/cmd/cover/testdata/ranges/ranges.go new file mode 100644 index 00000000000000..17b42e6423e87a --- /dev/null +++ b/src/cmd/cover/testdata/ranges/ranges.go @@ -0,0 +1,114 @@ +package main + +import "fmt" + +func main() { +« fmt.Println("Start") + x := 42 +» + // This is a regular comment +« y := 0 + fmt.Println("After comment") +» + // Multiple comment lines + // fmt.Println("commented code") + // TODO: implement this later + +« fmt.Println("After multiple comments") +» + /* block comment */ + +« fmt.Println("After block comment") + z := 0 +» + «if x > 0 {» +« y = x * 2 +» } else { +« y = x - 2 +» } + +« z = 5 +» + /* Multiline block + comment spanning + several lines */ + +« z1 := 0 +» +« z1 = 1 /* inline comment +» spanning lines +« end */ z1 = 2 +» +« z1 = 3; /* // */ z1 = 4 +» +« z1 = 5 /* // +» // +« // */ z1 = 6 +» + /* +« */ z1 = 7 /* +» */ + +« z1 = 8/* +» */ /* comment +« */z1 = 9 +» +« /* before */ z1 = 10 + /* before */ z1 = 10 /* after */ + z1 = 10 /* after */ +» +« fmt.Printf("Result: %d\n", z) + fmt.Printf("Result: %d\n", z1) +» +« s := `This is a multi-line raw string + // fake comment on line 2 + /* and fake comment on line 3 */ + and other` +» +« s = `another multiline string + ` // another trap +» +« fmt.Printf("%s", s) +» + // More comments to exclude + // for i := 0; i < 10; i++ { + // fmt.Printf("Loop %d", i) + // } + +« fmt.Printf("Result: %d\n", y)» + // end comment +} + +func empty() { + +} + +func singleBlock() { +« fmt.Printf("ResultSomething") +»} + +func justComment() { + // comment +} + +func justMultilineComment() { + /* comment + again + until here */ +} + +func constBlock() { +« const ( + A = 1 + + B = 2 + ) + fmt.Printf("A=%d B=%d", A, B) +»} + +func compositeLit() { +« m := map[string]int{ + "a": 1, +» } +« fmt.Println(m) +»} diff --git a/src/cmd/dist/build.go b/src/cmd/dist/build.go index 2fcdb2d3915b9b..78d55bec559987 100644 --- a/src/cmd/dist/build.go +++ b/src/cmd/dist/build.go @@ -9,6 +9,7 @@ import ( "encoding/json" "flag" "fmt" + "go/build/constraint" "io" "io/fs" "log" @@ -418,12 +419,7 @@ func findgoversion() string { return chomp(readfile(path)) } - // Show a nicer error message if this isn't a Git repo. - if !isGitRepo() { - fatalf("FAILED: not a Git repo; must put a VERSION file in $GOROOT") - } - - // Otherwise, use Git. + // Otherwise, use Git or jj. // // Include 1.x base version, hash, and date in the version. // Make sure it includes the substring "devel", but otherwise @@ -442,7 +438,16 @@ func findgoversion() string { fatalf("internal/goversion/goversion.go does not contain 'const Version = ...'") } version := fmt.Sprintf("go1.%s-devel_", m[1]) - version += chomp(run(goroot, CheckExit, "git", "log", "-n", "1", "--format=format:%h %cd", "HEAD")) + switch { + case isGitRepo(): + version += chomp(run(goroot, CheckExit, "git", "log", "-n", "1", "--format=format:%h %cd", "HEAD")) + case isJJRepo(): + const jjTemplate = `commit_id.short(10) ++ " " ++ committer.timestamp().format("%c %z")` + version += chomp(run(goroot, CheckExit, "jj", "--no-pager", "--color=never", "log", "--no-graph", "-r", "@", "-T", jjTemplate)) + default: + // Show a nicer error message if this isn't a Git or jj repo. + fatalf("FAILED: not a Git or jj repo; must put a VERSION file in $GOROOT") + } // Cache version. writefile(version, path, 0) @@ -489,6 +494,16 @@ func isGitRepo() bool { return isdir(gitDir) } +// isJJRepo reports whether the working directory is inside a jj repository. +func isJJRepo() bool { + // Don't check the error from jj, similarly to what we do in isGitRepo. + jjDir := chomp(run(goroot, 0, "jj", "--no-pager", "--color=never", "root")) + if !filepath.IsAbs(jjDir) { + jjDir = filepath.Join(goroot, jjDir) + } + return isdir(jjDir) +} + /* * Initial tree setup. */ @@ -624,14 +639,9 @@ func mustLinkExternal(goos, goarch string, cgoEnabled bool) bool { // Internally linking cgo is incomplete on some architectures. // https://golang.org/issue/14449 return true - case "arm64": - if goos == "windows" { - // windows/arm64 internal linking is not implemented. - return true - } case "ppc64": - // Big Endian PPC64 cgo internal linking is not implemented for aix or linux. - if goos == "aix" || goos == "linux" { + // Big Endian PPC64 cgo internal linking is not implemented for aix. + if goos == "aix" { return true } } @@ -914,6 +924,7 @@ func runInstall(pkg string, ch chan struct{}) { "-D", "GOARCH_" + goarch, "-D", "GOOS_GOARCH_" + goos + "_" + goarch, "-p", pkg, + "-std", } if goarch == "mips" || goarch == "mipsle" { // Define GOMIPS_value from gomips. @@ -1157,11 +1168,12 @@ func shouldbuild(file, pkg string) bool { break } if strings.HasPrefix(p, "//go:build ") { - matched, err := matchexpr(p[len("//go:build "):]) + c, err := constraint.Parse(p) if err != nil { - errprintf("%s: %v", file, err) + errprintf("%s: parsing //go:build line: %v", file, err) + return false } - return matched + return c.Eval(matchtag) } } @@ -1785,7 +1797,7 @@ var cgoEnabled = map[string]bool{ "linux/arm": true, "linux/arm64": true, "linux/loong64": true, - "linux/ppc64": false, + "linux/ppc64": true, "linux/ppc64le": true, "linux/mips": true, "linux/mipsle": true, @@ -1810,7 +1822,6 @@ var cgoEnabled = map[string]bool{ "openbsd/amd64": true, "openbsd/arm": true, "openbsd/arm64": true, - "openbsd/mips64": true, "openbsd/ppc64": false, "openbsd/riscv64": true, "plan9/386": false, @@ -1827,9 +1838,8 @@ var cgoEnabled = map[string]bool{ // get filtered out of cgoEnabled for 'dist list'. // See go.dev/issue/56679. var broken = map[string]bool{ - "freebsd/riscv64": true, // Broken: go.dev/issue/73568. + "freebsd/riscv64": true, // Broken: go.dev/issue/76475. "linux/sparc64": true, // An incomplete port. See CL 132155. - "openbsd/mips64": true, // Broken: go.dev/issue/58110. } // List of platforms which are first class ports. See go.dev/issue/38874. diff --git a/src/cmd/dist/buildtag.go b/src/cmd/dist/buildtag.go deleted file mode 100644 index 24776a0aaf735f..00000000000000 --- a/src/cmd/dist/buildtag.go +++ /dev/null @@ -1,133 +0,0 @@ -// Copyright 2021 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -package main - -import ( - "fmt" - "strings" -) - -// exprParser is a //go:build expression parser and evaluator. -// The parser is a trivial precedence-based parser which is still -// almost overkill for these very simple expressions. -type exprParser struct { - x string - t exprToken // upcoming token -} - -// val is the value type result of parsing. -// We don't keep a parse tree, just the value of the expression. -type val bool - -// exprToken describes a single token in the input. -// Prefix operators define a prefix func that parses the -// upcoming value. Binary operators define an infix func -// that combines two values according to the operator. -// In that case, the parsing loop parses the two values. -type exprToken struct { - tok string - prec int - prefix func(*exprParser) val - infix func(val, val) val -} - -var exprTokens []exprToken - -func init() { // init to break init cycle - exprTokens = []exprToken{ - {tok: "&&", prec: 1, infix: func(x, y val) val { return x && y }}, - {tok: "||", prec: 2, infix: func(x, y val) val { return x || y }}, - {tok: "!", prec: 3, prefix: (*exprParser).not}, - {tok: "(", prec: 3, prefix: (*exprParser).paren}, - {tok: ")"}, - } -} - -// matchexpr parses and evaluates the //go:build expression x. -func matchexpr(x string) (matched bool, err error) { - defer func() { - if e := recover(); e != nil { - matched = false - err = fmt.Errorf("parsing //go:build line: %v", e) - } - }() - - p := &exprParser{x: x} - p.next() - v := p.parse(0) - if p.t.tok != "end of expression" { - panic("unexpected " + p.t.tok) - } - return bool(v), nil -} - -// parse parses an expression, including binary operators at precedence >= prec. -func (p *exprParser) parse(prec int) val { - if p.t.prefix == nil { - panic("unexpected " + p.t.tok) - } - v := p.t.prefix(p) - for p.t.prec >= prec && p.t.infix != nil { - t := p.t - p.next() - v = t.infix(v, p.parse(t.prec+1)) - } - return v -} - -// not is the prefix parser for a ! token. -func (p *exprParser) not() val { - p.next() - return !p.parse(100) -} - -// paren is the prefix parser for a ( token. -func (p *exprParser) paren() val { - p.next() - v := p.parse(0) - if p.t.tok != ")" { - panic("missing )") - } - p.next() - return v -} - -// next advances the parser to the next token, -// leaving the token in p.t. -func (p *exprParser) next() { - p.x = strings.TrimSpace(p.x) - if p.x == "" { - p.t = exprToken{tok: "end of expression"} - return - } - for _, t := range exprTokens { - if strings.HasPrefix(p.x, t.tok) { - p.x = p.x[len(t.tok):] - p.t = t - return - } - } - - i := 0 - for i < len(p.x) && validtag(p.x[i]) { - i++ - } - if i == 0 { - panic(fmt.Sprintf("syntax error near %#q", rune(p.x[i]))) - } - tag := p.x[:i] - p.x = p.x[i:] - p.t = exprToken{ - tok: "tag", - prefix: func(p *exprParser) val { - p.next() - return val(matchtag(tag)) - }, - } -} - -func validtag(c byte) bool { - return 'A' <= c && c <= 'Z' || 'a' <= c && c <= 'z' || '0' <= c && c <= '9' || c == '.' || c == '_' -} diff --git a/src/cmd/dist/buildtag_test.go b/src/cmd/dist/buildtag_test.go deleted file mode 100644 index f64abfd1f18c25..00000000000000 --- a/src/cmd/dist/buildtag_test.go +++ /dev/null @@ -1,43 +0,0 @@ -// Copyright 2021 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -package main - -import ( - "fmt" - "reflect" - "testing" -) - -var buildParserTests = []struct { - x string - matched bool - err error -}{ - {"gc", true, nil}, - {"gccgo", false, nil}, - {"!gc", false, nil}, - {"gc && gccgo", false, nil}, - {"gc || gccgo", true, nil}, - {"gc || (gccgo && !gccgo)", true, nil}, - {"gc && (gccgo || !gccgo)", true, nil}, - {"!(gc && (gccgo || !gccgo))", false, nil}, - {"gccgo || gc", true, nil}, - {"!(!(!(gccgo || gc)))", false, nil}, - {"compiler_bootstrap", false, nil}, - {"cmd_go_bootstrap", true, nil}, - {"syntax(error", false, fmt.Errorf("parsing //go:build line: unexpected (")}, - {"(gc", false, fmt.Errorf("parsing //go:build line: missing )")}, - {"gc gc", false, fmt.Errorf("parsing //go:build line: unexpected tag")}, - {"(gc))", false, fmt.Errorf("parsing //go:build line: unexpected )")}, -} - -func TestBuildParser(t *testing.T) { - for _, tt := range buildParserTests { - matched, err := matchexpr(tt.x) - if matched != tt.matched || !reflect.DeepEqual(err, tt.err) { - t.Errorf("matchexpr(%q) = %v, %v; want %v, %v", tt.x, matched, err, tt.matched, tt.err) - } - } -} diff --git a/src/cmd/dist/buildtool.go b/src/cmd/dist/buildtool.go index 62cd9376927e0d..2da9a17636aae6 100644 --- a/src/cmd/dist/buildtool.go +++ b/src/cmd/dist/buildtool.go @@ -92,6 +92,7 @@ var bootstrapDirs = []string{ "internal/race", "internal/runtime/gc", "internal/saferio", + "internal/strconv", "internal/syscall/unix", "internal/types/errors", "internal/unsafeheader", diff --git a/src/cmd/dist/imports.go b/src/cmd/dist/imports.go index 0ec2b06c4f6e7a..c00369a6ba1e09 100644 --- a/src/cmd/dist/imports.go +++ b/src/cmd/dist/imports.go @@ -259,6 +259,6 @@ func resolveVendor(imp, srcDir string) string { } else if strings.HasPrefix(srcDir, filepath.Join(goroot, "src")) { return path.Join("vendor", imp) } else { - panic(fmt.Sprintf("srcDir %q not in GOOROT/src", srcDir)) + panic(fmt.Sprintf("srcDir %q not in GOROOT/src", srcDir)) } } diff --git a/src/cmd/dist/main.go b/src/cmd/dist/main.go index f3425a9dd8578e..8d316e1d1cdd15 100644 --- a/src/cmd/dist/main.go +++ b/src/cmd/dist/main.go @@ -140,10 +140,6 @@ func main() { } case gohostos == "openbsd" && strings.Contains(out, "powerpc64"): gohostarch = "ppc64" - case gohostos == "openbsd": - if strings.Contains(run("", CheckExit, "uname", "-p"), "mips64") { - gohostarch = "mips64" - } default: fatalf("unknown architecture: %s", out) } diff --git a/src/cmd/dist/test.go b/src/cmd/dist/test.go index 1e74438f48db39..43ac003c7907c7 100644 --- a/src/cmd/dist/test.go +++ b/src/cmd/dist/test.go @@ -30,6 +30,8 @@ func cmdtest() { var t tester + t.asmflags = os.Getenv("GO_TEST_ASMFLAGS") + var noRebuild bool flag.BoolVar(&t.listMode, "list", false, "list available tests") flag.BoolVar(&t.rebuild, "rebuild", false, "rebuild everything first") @@ -63,6 +65,10 @@ type tester struct { failed bool keepGoing bool compileOnly bool // just try to compile all tests, but no need to run + short bool + cgoEnabled bool + asmflags string + json bool runRxStr string runRx *regexp.Regexp runRxWant bool // want runRx to match (true) or not match (false) @@ -70,13 +76,9 @@ type tester struct { banner string // prefix, or "" for none lastHeading string // last dir heading printed - short bool - cgoEnabled bool - json bool - tests []distTest // use addTest to extend testNames map[string]bool - timeoutScale int + timeoutScale int // a non-negative integer factor to scale test timeout by; defaults to 1 worklist []*work } @@ -435,9 +437,6 @@ func (opts *goTest) buildArgs(t *tester) (build, run, pkgs, testFlags []string, run = append(run, "-short") } var tags []string - if t.iOS() { - tags = append(tags, "lldb") - } if noOpt { tags = append(tags, "noopt") } @@ -478,6 +477,9 @@ func (opts *goTest) buildArgs(t *tester) (build, run, pkgs, testFlags []string, if opts.ldflags != "" { build = append(build, "-ldflags="+opts.ldflags) } + if t.asmflags != "" { + build = append(build, "-asmflags="+t.asmflags) + } if opts.buildmode != "" { build = append(build, "-buildmode="+opts.buildmode) } @@ -571,9 +573,20 @@ func (t *tester) registerStdTest(pkg string) { timeoutSec := 180 * time.Second for _, pkg := range stdMatches { - if pkg == "cmd/go" { + switch pkg { + case "cmd/go": timeoutSec *= 3 - break + case "cmd/cgo/internal/testshared": + // This package can take 2-3 minutes to test, so 3 min timeout causes + // flaky failures, like https://ci.chromium.org/b/8679277370961616529. + // Use the default timeout for it rather than the custom 3 minute one. + timeoutSec = 0 + case "internal/godebugs": + // This package can take 5-6 minutes to test when the asan mode is on. + // The asan modifier scales the timeout by 2, but even 3*2 minutes is + // sometimes not enough. See go.dev/issue/78392. + // Use the default timeout for it rather than the custom 3 minute one. + timeoutSec = 0 } } return (&goTest{ @@ -699,16 +712,16 @@ func (t *tester) registerTests() { tags: []string{"osusergo"}, pkg: "os/user", }) - t.registerTest("hash/maphash purego implementation", - &goTest{ - variant: "purego", - timeout: 300 * time.Second, - tags: []string{"purego"}, - pkg: "hash/maphash", - env: []string{"GODEBUG=fips140=off"}, // FIPS 140-3 mode is incompatible with purego - }) } + // Tests that the nethttpomithttp2 build tag doesn't rot too much, + // even if there's not a regular builder on it. + t.registerTest("net/http with tag nethttpomithttp2", &goTest{ + variant: "nethttpomithttp2", + tags: []string{"nethttpomithttp2"}, + pkg: "net/http", + }) + // Check that all crypto packages compile with the purego build tag. t.registerTest("crypto with tag purego (build and vet only)", &goTest{ variant: "purego", @@ -728,7 +741,7 @@ func (t *tester) registerTests() { // Test that earlier FIPS snapshots build. // In long mode, test that they work too. - for _, version := range fipsVersions(t.short) { + for _, version := range fipsVersions() { suffix := " # (build and vet only)" run := "^$" // only ensure they compile if !t.short { @@ -744,15 +757,43 @@ func (t *tester) registerTests() { } } - // Test GOEXPERIMENT=jsonv2. - if !strings.Contains(goexperiment, "jsonv2") { - t.registerTest("GOEXPERIMENT=jsonv2 go test encoding/json/...", &goTest{ - variant: "jsonv2", - env: []string{"GOEXPERIMENT=jsonv2"}, + // Test GOEXPERIMENT=nojsonv2. + if !strings.Contains(goexperiment, "nojsonv2") { + t.registerTest("GOEXPERIMENT=nojsonv2 go test encoding/json/...", &goTest{ + variant: "nojsonv2", + env: []string{"GOEXPERIMENT=" + goexperiments("nojsonv2")}, pkg: "encoding/json/...", }) } + // Test GOEXPERIMENT=runtimesecret. + if !strings.Contains(goexperiment, "runtimesecret") { + t.registerTest("GOEXPERIMENT=runtimesecret go test runtime/secret/...", &goTest{ + variant: "runtimesecret", + env: []string{"GOEXPERIMENT=" + goexperiments("runtimesecret")}, + pkg: "runtime/secret/...", + }) + } + + // Test GOEXPERIMENT=simd. + if !strings.Contains(goexperiment, "simd") { + // simd package is portable. + t.registerTest("GOEXPERIMENT=simd go test simd", &goTest{ + variant: "simd", + env: []string{"GOEXPERIMENT=" + goexperiments("simd")}, + pkg: "simd", + }) + // simd/archsimd supports amd64, arm64, and wasm. + archsimdSupported := goarch == "amd64" || goarch == "arm64" || goarch == "wasm" + if archsimdSupported { + t.registerTest("GOEXPERIMENT=simd go test simd/archsimd/...", &goTest{ + variant: "simd", + env: []string{"GOEXPERIMENT=" + goexperiments("simd")}, + pkg: "simd/archsimd/...", + }) + } + } + // Test ios/amd64 for the iOS simulator. if goos == "darwin" && goarch == "amd64" && t.cgoEnabled { t.registerTest("GOOS=ios on darwin/amd64", @@ -771,7 +812,7 @@ func (t *tester) registerTests() { if !t.compileOnly && !t.short { t.registerTest("GODEBUG=gcstoptheworld=2 archive/zip", &goTest{ - variant: "runtime:gcstoptheworld2", + variant: "gcstoptheworld2", timeout: 300 * time.Second, short: true, env: []string{"GODEBUG=gcstoptheworld=2"}, @@ -779,7 +820,7 @@ func (t *tester) registerTests() { }) t.registerTest("GODEBUG=gccheckmark=1 runtime", &goTest{ - variant: "runtime:gccheckmark", + variant: "gccheckmark", timeout: 300 * time.Second, short: true, env: []string{"GODEBUG=gccheckmark=1"}, @@ -787,6 +828,22 @@ func (t *tester) registerTests() { }) } + // Spectre mitigation smoke test. + if goos == "linux" && goarch == "amd64" && !(gogcflags == "-spectre=all" && t.asmflags == "all=-spectre=all") { + // Pick a bunch of packages known to have some assembly. + pkgs := []string{"internal/runtime/...", "reflect", "crypto/..."} + if !t.short { + pkgs = append(pkgs, "runtime") + } + t.registerTest("spectre", + &goTest{ + variant: "spectre", + short: true, + env: []string{"GOFLAGS=-gcflags=all=-spectre=all -asmflags=all=-spectre=all"}, + pkgs: pkgs, + }) + } + // morestack tests. We only run these in long-test mode // (with GO_TEST_SHORT=0) because the runtime test is // already quite long and mayMoreStackMove makes it about @@ -956,7 +1013,9 @@ func (t *tester) registerTests() { // which is darwin,linux,windows/amd64 and darwin/arm64. // // The same logic applies to the release notes that correspond to each api/next file. - if goos == "darwin" || ((goos == "linux" || goos == "windows") && goarch == "amd64") { + // + // TODO: remove the exclusion of goexperiment simd right before dev.simd branch is merged to master. + if goos == "darwin" || ((goos == "linux" || goos == "windows") && (goarch == "amd64" && !strings.Contains(goexperiment, "simd"))) { t.registerTest("API release note check", &goTest{variant: "check", pkg: "cmd/relnote", testFlags: []string{"-check"}}) t.registerTest("API check", &goTest{variant: "check", pkg: "cmd/api", timeout: 5 * time.Minute, testFlags: []string{"-check"}}) } @@ -1108,7 +1167,7 @@ func (t *tester) registerTest(heading string, test *goTest, opts ...registerTest // dirCmd constructs a Cmd intended to be run in the foreground. // The command will be run in dir, and Stdout and Stderr will go to os.Stdout // and os.Stderr. -func (t *tester) dirCmd(dir string, cmdline ...interface{}) *exec.Cmd { +func (t *tester) dirCmd(dir string, cmdline ...any) *exec.Cmd { bin, args := flattenCmdline(cmdline) cmd := exec.Command(bin, args...) if filepath.IsAbs(dir) { @@ -1126,7 +1185,7 @@ func (t *tester) dirCmd(dir string, cmdline ...interface{}) *exec.Cmd { // flattenCmdline flattens a mixture of string and []string as single list // and then interprets it as a command line: first element is binary, then args. -func flattenCmdline(cmdline []interface{}) (bin string, args []string) { +func flattenCmdline(cmdline []any) (bin string, args []string) { var list []string for _, x := range cmdline { switch x := x.(type) { @@ -1166,7 +1225,7 @@ func (t *tester) extLink() bool { if !cgoEnabled[goos+"/"+goarch] { return false } - if goarch == "ppc64" && goos != "aix" { + if goarch == "ppc64" && goos != "aix" && goos != "linux" { return false } return true @@ -1183,9 +1242,6 @@ func (t *tester) internalLink() bool { if goos == "ios" { return false } - if goos == "windows" && goarch == "arm64" { - return false - } // Internally linking cgo is incomplete on some architectures. // https://golang.org/issue/10373 // https://golang.org/issue/14449 @@ -1210,9 +1266,9 @@ func (t *tester) internalLinkPIE() bool { } switch goos + "-" + goarch { case "darwin-amd64", "darwin-arm64", - "linux-amd64", "linux-arm64", "linux-loong64", "linux-ppc64le", + "linux-amd64", "linux-arm64", "linux-loong64", "linux-ppc64", "linux-ppc64le", "linux-s390x", "android-arm64", - "windows-amd64", "windows-386": + "windows-amd64", "windows-386", "windows-arm64": return true } return false @@ -1220,15 +1276,10 @@ func (t *tester) internalLinkPIE() bool { func (t *tester) externalLinkPIE() bool { // General rule is if -buildmode=pie and -linkmode=external both work, then they work together. - // Handle exceptions and then fall back to the general rule. - switch goos + "-" + goarch { - case "linux-s390x": - return true - } return t.internalLinkPIE() && t.extLink() } -// supportedBuildMode reports whether the given build mode is supported. +// supportedBuildmode reports whether the given build mode is supported. func (t *tester) supportedBuildmode(mode string) bool { switch mode { case "c-archive", "c-shared", "shared", "plugin", "pie": @@ -1263,11 +1314,12 @@ func (t *tester) registerCgoTests(heading string) { // This isn't actually a Go buildmode, just a convenient way to tell // cgoTest we want static linking. gt.buildmode = "" - if linkmode == "external" { + switch linkmode { + case "external": ldflags = append(ldflags, `-extldflags "-static -pthread"`) - } else if linkmode == "auto" { + case "auto": gt.env = append(gt.env, "CGO_LDFLAGS=-static -pthread") - } else { + default: panic("unknown linkmode with static build: " + linkmode) } gt.tags = append(gt.tags, "static") @@ -1292,8 +1344,8 @@ func (t *tester) registerCgoTests(heading string) { os := gohostos p := gohostos + "/" + goarch - switch { - case os == "darwin", os == "windows": + switch os { + case "darwin", "windows": if !t.extLink() { break } @@ -1310,7 +1362,7 @@ func (t *tester) registerCgoTests(heading string) { } } - case os == "aix", os == "android", os == "dragonfly", os == "freebsd", os == "linux", os == "netbsd", os == "openbsd": + case "aix", "android", "dragonfly", "freebsd", "linux", "netbsd", "openbsd": gt := cgoTest("external-g0", "test", "external", "") gt.env = append(gt.env, "CGO_CFLAGS=-g0 -fdiagnostics-color") @@ -1498,14 +1550,6 @@ func (t *tester) runPending(nextTest *distTest) { } } -func (t *tester) hasBash() bool { - switch gohostos { - case "windows", "plan9": - return false - } - return true -} - // hasParallelism is a copy of the function // internal/testenv.HasParallelism, which can't be used here // because cmd/dist can not import internal packages during bootstrap. @@ -1729,9 +1773,7 @@ func buildModeSupported(compiler, buildmode, goos, goarch string) bool { return true case "linux": switch goarch { - case "386", "amd64", "arm", "armbe", "arm64", "arm64be", "loong64", "ppc64le", "riscv64", "s390x": - // linux/ppc64 not supported because it does - // not support external linking mode yet. + case "386", "amd64", "arm", "armbe", "arm64", "arm64be", "loong64", "ppc64", "ppc64le", "riscv64", "s390x": return true default: // Other targets do not support -shared, @@ -1749,7 +1791,7 @@ func buildModeSupported(compiler, buildmode, goos, goarch string) bool { case "c-shared": switch platform { - case "linux/amd64", "linux/arm", "linux/arm64", "linux/loong64", "linux/386", "linux/ppc64le", "linux/riscv64", "linux/s390x", + case "linux/amd64", "linux/arm", "linux/arm64", "linux/loong64", "linux/386", "linux/ppc64", "linux/ppc64le", "linux/riscv64", "linux/s390x", "android/amd64", "android/arm", "android/arm64", "android/386", "freebsd/amd64", "darwin/amd64", "darwin/arm64", @@ -1767,7 +1809,7 @@ func buildModeSupported(compiler, buildmode, goos, goarch string) bool { case "pie": switch platform { - case "linux/386", "linux/amd64", "linux/arm", "linux/arm64", "linux/loong64", "linux/ppc64le", "linux/riscv64", "linux/s390x", + case "linux/386", "linux/amd64", "linux/arm", "linux/arm64", "linux/loong64", "linux/ppc64", "linux/ppc64le", "linux/riscv64", "linux/s390x", "android/amd64", "android/arm", "android/arm64", "android/386", "freebsd/amd64", "darwin/amd64", "darwin/arm64", @@ -1781,14 +1823,14 @@ func buildModeSupported(compiler, buildmode, goos, goarch string) bool { case "shared": switch platform { - case "linux/386", "linux/amd64", "linux/arm", "linux/arm64", "linux/ppc64le", "linux/s390x": + case "linux/386", "linux/amd64", "linux/arm", "linux/arm64", "linux/ppc64", "linux/ppc64le", "linux/s390x": return true } return false case "plugin": switch platform { - case "linux/amd64", "linux/arm", "linux/arm64", "linux/386", "linux/loong64", "linux/riscv64", "linux/s390x", "linux/ppc64le", + case "linux/amd64", "linux/arm", "linux/arm64", "linux/386", "linux/loong64", "linux/riscv64", "linux/s390x", "linux/ppc64", "linux/ppc64le", "android/amd64", "android/386", "darwin/amd64", "darwin/arm64", "freebsd/amd64": @@ -1853,7 +1895,7 @@ func (t *tester) fipsSupported() bool { } // fipsVersions returns the list of versions available in lib/fips140. -func fipsVersions(short bool) []string { +func fipsVersions() []string { var versions []string zips, err := filepath.Glob(filepath.Join(goroot, "lib/fips140/*.zip")) if err != nil { @@ -1871,3 +1913,19 @@ func fipsVersions(short bool) []string { } return versions } + +// goexperiments returns the GOEXPERIMENT value to use +// when running a test with the given experiments enabled. +// +// It preserves any existing GOEXPERIMENTs. +func goexperiments(exps ...string) string { + if len(exps) == 0 { + return goexperiment + } + existing := goexperiment + if existing != "" { + existing += "," + } + return existing + strings.Join(exps, ",") + +} diff --git a/src/cmd/dist/testjson.go b/src/cmd/dist/testjson.go index c190c665ebf779..8ae6e8905d578c 100644 --- a/src/cmd/dist/testjson.go +++ b/src/cmd/dist/testjson.go @@ -80,7 +80,8 @@ func (f *testJSONFilter) process(line []byte) { // struct, or other additions outside of it. If humans are ever looking // at the output, it's really nice to keep field order because it // preserves a lot of regularity in the output. - dec := json.NewDecoder(bytes.NewBuffer(line)) + lineBuf := bytes.NewBuffer(line) + dec := json.NewDecoder(lineBuf) dec.UseNumber() val, err := decodeJSONValue(dec) if err == nil && val.atom == json.Delim('{') { @@ -105,6 +106,7 @@ func (f *testJSONFilter) process(line []byte) { // Copy any trailing text. We expect at most a "\n" here, but // there could be other text and we want to feed that through. io.Copy(f.w, dec.Buffered()) + io.Copy(f.w, lineBuf) return } } diff --git a/src/cmd/dist/util.go b/src/cmd/dist/util.go index 121c2dc62cf7a4..1109bf0efd7a1e 100644 --- a/src/cmd/dist/util.go +++ b/src/cmd/dist/util.go @@ -21,7 +21,7 @@ import ( // pathf is fmt.Sprintf for generating paths // (on windows it turns / into \ after the printf). -func pathf(format string, args ...interface{}) string { +func pathf(format string, args ...any) string { return filepath.Clean(fmt.Sprintf(format, args...)) } @@ -324,7 +324,7 @@ func xworkdir() string { } // fatalf prints an error message to standard error and exits. -func fatalf(format string, args ...interface{}) { +func fatalf(format string, args ...any) { fmt.Fprintf(os.Stderr, "go tool dist: %s\n", fmt.Sprintf(format, args...)) dieOnce.Do(func() { close(dying) }) @@ -353,12 +353,12 @@ func xatexit(f func()) { } // xprintf prints a message to standard output. -func xprintf(format string, args ...interface{}) { +func xprintf(format string, args ...any) { fmt.Printf(format, args...) } // errprintf prints a message to standard output. -func errprintf(format string, args ...interface{}) { +func errprintf(format string, args ...any) { fmt.Fprintf(os.Stderr, format, args...) } diff --git a/src/cmd/distpack/pack.go b/src/cmd/distpack/pack.go index 09c3a331195f58..53e9dbd73b64ca 100644 --- a/src/cmd/distpack/pack.go +++ b/src/cmd/distpack/pack.go @@ -113,6 +113,7 @@ func main() { ".gitattributes", ".github/**", ".gitignore", + ".jj/**", "VERSION.cache", "misc/cgo/*/_obj/**", "**/.DS_Store", diff --git a/src/cmd/distpack/test.go b/src/cmd/distpack/test.go index 7479bd77f55951..7fd2dad57be7f1 100644 --- a/src/cmd/distpack/test.go +++ b/src/cmd/distpack/test.go @@ -30,6 +30,7 @@ var srcRules = []testRule{ {name: "go/.git", exclude: true}, {name: "go/.gitattributes", exclude: true}, {name: "go/.github", exclude: true}, + {name: "go/.jj", exclude: true}, {name: "go/VERSION.cache", exclude: true}, {name: "go/bin/**", exclude: true}, {name: "go/pkg/**", exclude: true}, @@ -48,6 +49,7 @@ var zipRules = []testRule{ {name: "go/.git", exclude: true}, {name: "go/.gitattributes", exclude: true}, {name: "go/.github", exclude: true}, + {name: "go/.jj", exclude: true}, {name: "go/VERSION.cache", exclude: true}, {name: "go/bin", exclude: true}, {name: "go/pkg", exclude: true}, @@ -84,6 +86,7 @@ var modRules = []testRule{ {name: "golang.org/toolchain@*/.git", exclude: true}, {name: "golang.org/toolchain@*/.gitattributes", exclude: true}, {name: "golang.org/toolchain@*/.github", exclude: true}, + {name: "golang.org/toolchain@*/.jj", exclude: true}, {name: "golang.org/toolchain@*/VERSION.cache", exclude: true}, {name: "golang.org/toolchain@*/bin", exclude: true}, {name: "golang.org/toolchain@*/pkg", exclude: true}, diff --git a/src/cmd/fix/main.go b/src/cmd/fix/main.go index 8fc412fe29e02c..32a4ce0d1e7415 100644 --- a/src/cmd/fix/main.go +++ b/src/cmd/fix/main.go @@ -22,13 +22,8 @@ package main import ( "cmd/internal/objabi" "cmd/internal/telemetry/counter" - "slices" - "golang.org/x/tools/go/analysis" - "golang.org/x/tools/go/analysis/passes/buildtag" - "golang.org/x/tools/go/analysis/passes/hostport" - "golang.org/x/tools/go/analysis/passes/inline" - "golang.org/x/tools/go/analysis/passes/modernize" + "golang.org/x/tools/go/analysis/suite/fix" "golang.org/x/tools/go/analysis/unitchecker" ) @@ -38,26 +33,5 @@ func main() { objabi.AddVersionFlag() counter.Inc("fix/invocations") - unitchecker.Main(suite...) // (never returns) + unitchecker.Main(fix.Suite...) // (never returns) } - -// The fix suite analyzers produce fixes are unambiguously safe to apply, -// even if the diagnostics might not describe actual problems. -var suite = slices.Concat( - []*analysis.Analyzer{ - buildtag.Analyzer, - hostport.Analyzer, - inline.Analyzer, - }, - modernize.Suite, - // TODO(adonovan): add any other vet analyzers whose fixes are always safe. - // Candidates to audit: sigchanyzer, printf, assign, unreachable. - // Many of staticcheck's analyzers would make good candidates - // (e.g. rewriting WriteString(fmt.Sprintf()) to Fprintf.) - // Rejected: - // - composites: some types (e.g. PointXY{1,2}) don't want field names. - // - timeformat: flipping MM/DD is a behavior change, but the code - // could potentially be a workaround for another bug. - // - stringintconv: offers two fixes, user input required to choose. - // - fieldalignment: poor signal/noise; fix could be a regression. -) diff --git a/src/cmd/go.mod b/src/cmd/go.mod index 42d510c34fe6b4..068d8d22476f1a 100644 --- a/src/cmd/go.mod +++ b/src/cmd/go.mod @@ -1,21 +1,21 @@ module cmd -go 1.26 +go 1.27 require ( - github.com/google/pprof v0.0.0-20250630185457-6e76a2b096b5 - golang.org/x/arch v0.22.1-0.20251016010524-fea4a9ec4938 - golang.org/x/build v0.0.0-20250806225920-b7c66c047964 - golang.org/x/mod v0.29.0 - golang.org/x/sync v0.17.0 - golang.org/x/sys v0.37.0 - golang.org/x/telemetry v0.0.0-20251008203120-078029d740a8 - golang.org/x/term v0.34.0 - golang.org/x/tools v0.38.1-0.20251015192825-7d9453ccc0f5 + github.com/google/pprof v0.0.0-20260507013755-92041b743c96 + golang.org/x/arch v0.27.1-0.20260521044007-9c1a596a2c97 + golang.org/x/build v0.0.0-20260522210304-d55d0041b921 + golang.org/x/mod v0.36.1-0.20260813213634-8569e2639ca1 + golang.org/x/sync v0.20.0 + golang.org/x/sys v0.45.0 + golang.org/x/telemetry v0.0.0-20260519152614-eab6ae52b5e2 + golang.org/x/term v0.43.0 + golang.org/x/tools v0.45.1-0.20260917185718-3dd9077b8066 ) require ( github.com/ianlancetaylor/demangle v0.0.0-20250417193237-f615e6bd150b // indirect - golang.org/x/text v0.30.0 // indirect + golang.org/x/text v0.37.0 // indirect rsc.io/markdown v0.0.0-20240306144322-0bf8f97ee8ef // indirect ) diff --git a/src/cmd/go.sum b/src/cmd/go.sum index 0a09e6e401a926..a5248cabd280a0 100644 --- a/src/cmd/go.sum +++ b/src/cmd/go.sum @@ -1,28 +1,28 @@ -github.com/google/go-cmp v0.6.0 h1:ofyhxvXcZhMsU5ulbFiLKl/XBFqE1GSq7atu8tAmTRI= -github.com/google/go-cmp v0.6.0/go.mod h1:17dUlkBOakJ0+DkrSSNjCkIjxS6bF9zb3elmeNGIjoY= -github.com/google/pprof v0.0.0-20250630185457-6e76a2b096b5 h1:xhMrHhTJ6zxu3gA4enFM9MLn9AY7613teCdFnlUVbSQ= -github.com/google/pprof v0.0.0-20250630185457-6e76a2b096b5/go.mod h1:5hDyRhoBCxViHszMt12TnOpEI4VVi+U8Gm9iphldiMA= +github.com/google/go-cmp v0.7.0 h1:wk8382ETsv4JYUZwIsn6YpYiWiBsYLSJiTsyBybVuN8= +github.com/google/go-cmp v0.7.0/go.mod h1:pXiqmnSA92OHEEa9HXL2W4E7lf9JzCmGVUdgjX3N/iU= +github.com/google/pprof v0.0.0-20260507013755-92041b743c96 h1:YDDnaZ9afWajDboPMt9Vikqca/yWAX7KAxVzb4lJU1M= +github.com/google/pprof v0.0.0-20260507013755-92041b743c96/go.mod h1:MxpfABSjhmINe3F1It9d+8exIHFvUqtLIRCdOGNXqiI= github.com/ianlancetaylor/demangle v0.0.0-20250417193237-f615e6bd150b h1:ogbOPx86mIhFy764gGkqnkFC8m5PJA7sPzlk9ppLVQA= github.com/ianlancetaylor/demangle v0.0.0-20250417193237-f615e6bd150b/go.mod h1:gx7rwoVhcfuVKG5uya9Hs3Sxj7EIvldVofAWIUtGouw= github.com/yuin/goldmark v1.6.0 h1:boZcn2GTjpsynOsC0iJHnBWa4Bi0qzfJjthwauItG68= github.com/yuin/goldmark v1.6.0/go.mod h1:6yULJ656Px+3vBD8DxQVa3kxgyrAnzto9xy5taEt/CY= -golang.org/x/arch v0.22.1-0.20251016010524-fea4a9ec4938 h1:VJ182b/ajNehMFRltVfCh/FR0jAH+QX6hs9zqYod/mU= -golang.org/x/arch v0.22.1-0.20251016010524-fea4a9ec4938/go.mod h1:dNHoOeKiyja7GTvF9NJS1l3Z2yntpQNzgrjh1cU103A= -golang.org/x/build v0.0.0-20250806225920-b7c66c047964 h1:yRs1K51GKq7hsIO+YHJ8LsslrvwFceNPIv0tYjpcBd0= -golang.org/x/build v0.0.0-20250806225920-b7c66c047964/go.mod h1:i9Vx7+aOQUpYJRxSO+OpRStVBCVL/9ccI51xblWm5WY= -golang.org/x/mod v0.29.0 h1:HV8lRxZC4l2cr3Zq1LvtOsi/ThTgWnUk/y64QSs8GwA= -golang.org/x/mod v0.29.0/go.mod h1:NyhrlYXJ2H4eJiRy/WDBO6HMqZQ6q9nk4JzS3NuCK+w= -golang.org/x/sync v0.17.0 h1:l60nONMj9l5drqw6jlhIELNv9I0A4OFgRsG9k2oT9Ug= -golang.org/x/sync v0.17.0/go.mod h1:9KTHXmSnoGruLpwFjVSX0lNNA75CykiMECbovNTZqGI= -golang.org/x/sys v0.37.0 h1:fdNQudmxPjkdUTPnLn5mdQv7Zwvbvpaxqs831goi9kQ= -golang.org/x/sys v0.37.0/go.mod h1:OgkHotnGiDImocRcuBABYBEXf8A9a87e/uXjp9XT3ks= -golang.org/x/telemetry v0.0.0-20251008203120-078029d740a8 h1:LvzTn0GQhWuvKH/kVRS3R3bVAsdQWI7hvfLHGgh9+lU= -golang.org/x/telemetry v0.0.0-20251008203120-078029d740a8/go.mod h1:Pi4ztBfryZoJEkyFTI5/Ocsu2jXyDr6iSdgJiYE/uwE= -golang.org/x/term v0.34.0 h1:O/2T7POpk0ZZ7MAzMeWFSg6S5IpWd/RXDlM9hgM3DR4= -golang.org/x/term v0.34.0/go.mod h1:5jC53AEywhIVebHgPVeg0mj8OD3VO9OzclacVrqpaAw= -golang.org/x/text v0.30.0 h1:yznKA/E9zq54KzlzBEAWn1NXSQ8DIp/NYMy88xJjl4k= -golang.org/x/text v0.30.0/go.mod h1:yDdHFIX9t+tORqspjENWgzaCVXgk0yYnYuSZ8UzzBVM= -golang.org/x/tools v0.38.1-0.20251015192825-7d9453ccc0f5 h1:cz7f45KGWAtyIrz6bm45Gc+lw8beIxBSW3EQh4Bwbg4= -golang.org/x/tools v0.38.1-0.20251015192825-7d9453ccc0f5/go.mod h1:yEsQ/d/YK8cjh0L6rZlY8tgtlKiBNTL14pGDJPJpYQs= +golang.org/x/arch v0.27.1-0.20260521044007-9c1a596a2c97 h1:OEbDVxixMxnrAI3whhcFkCb0rPrEHwxeSSUMdN0V414= +golang.org/x/arch v0.27.1-0.20260521044007-9c1a596a2c97/go.mod h1:0X+GdSIP+kL5wPmpK7sdkEVTt2XoYP0cSjQSbZBwOi8= +golang.org/x/build v0.0.0-20260522210304-d55d0041b921 h1:94de7eCg8UQyP1wZw1ap2Y6rUGCmlKFSmffASSuprtk= +golang.org/x/build v0.0.0-20260522210304-d55d0041b921/go.mod h1:fBHxr1BrGapBTKSXEIQF99Z70AVWGYjAYKtf4FahAkA= +golang.org/x/mod v0.36.1-0.20260813213634-8569e2639ca1 h1:mvVf5vNWIEd2A6cnWTrK9hv194u/9lVqhYdiQzRvBZo= +golang.org/x/mod v0.36.1-0.20260813213634-8569e2639ca1/go.mod h1:moc6ELqsWcOw5Ef3xVprK5ul/MvtVvkIXLziUOICjUQ= +golang.org/x/sync v0.20.0 h1:e0PTpb7pjO8GAtTs2dQ6jYa5BWYlMuX047Dco/pItO4= +golang.org/x/sync v0.20.0/go.mod h1:9xrNwdLfx4jkKbNva9FpL6vEN7evnE43NNNJQ2LF3+0= +golang.org/x/sys v0.45.0 h1:dO4czNzziLiiXplLQgBCEpCvXQ3dnkn0SdaZSYdQ+FY= +golang.org/x/sys v0.45.0/go.mod h1:4GL1E5IUh+htKOUEOaiffhrAeqysfVGipDYzABqnCmw= +golang.org/x/telemetry v0.0.0-20260519152614-eab6ae52b5e2 h1:2EucmYlcIsc8Y6aLj+kX90Y00hmjqLNlw935kc13R2k= +golang.org/x/telemetry v0.0.0-20260519152614-eab6ae52b5e2/go.mod h1:Eqhaxk/wZsWEH8CRxLwj6xzEJbz7k1EFGqx7nyCoabE= +golang.org/x/term v0.43.0 h1:S4RLU2sB31O/NCl+zFN9Aru9A/Cq2aqKpTZJ6B+DwT4= +golang.org/x/term v0.43.0/go.mod h1:lrhlHNdQJHO+1qVYiHfFKVuVioJIheAc3fBSMFYEIsk= +golang.org/x/text v0.37.0 h1:Cqjiwd9eSg8e0QAkyCaQTNHFIIzWtidPahFWR83rTrc= +golang.org/x/text v0.37.0/go.mod h1:a5sjxXGs9hsn/AJVwuElvCAo9v8QYLzvavO5z2PiM38= +golang.org/x/tools v0.45.1-0.20260917185718-3dd9077b8066 h1:xPYC80nKQHF/E3LNhvTNYVga54nQm+ziyokKY2lud1c= +golang.org/x/tools v0.45.1-0.20260917185718-3dd9077b8066/go.mod h1:LuUGqqaXcXMEFEruIVJVm5mgDD8vww/z/SR1gQ4uE/0= rsc.io/markdown v0.0.0-20240306144322-0bf8f97ee8ef h1:mqLYrXCXYEZOop9/Dbo6RPX11539nwiCNBb1icVPmw8= rsc.io/markdown v0.0.0-20240306144322-0bf8f97ee8ef/go.mod h1:8xcPgWmwlZONN1D9bjxtHEjrUtSEa3fakVF8iaewYKQ= diff --git a/src/cmd/go/alldocs.go b/src/cmd/go/alldocs.go index 46bca7480b70a4..44cec1ae79e710 100644 --- a/src/cmd/go/alldocs.go +++ b/src/cmd/go/alldocs.go @@ -25,13 +25,13 @@ // install compile and install packages and dependencies // list list packages or modules // mod module maintenance -// work workspace maintenance // run compile and run Go program // telemetry manage telemetry data and settings // test test packages // tool run specified go tool // version print Go version // vet report likely mistakes in packages +// work workspace maintenance // // Use "go help " for more information about a command. // @@ -199,7 +199,7 @@ // By default, if a vendor directory is present and the go version in go.mod // is 1.14 or higher, the go command acts as if -mod=vendor were set. // Otherwise, the go command acts as if -mod=readonly were set. -// See https://golang.org/ref/mod#build-commands for details. +// See https://go.dev/ref/mod#build-commands for details. // -modcacherw // leave newly-created directories in the module cache read-write // instead of making them read-only. @@ -267,12 +267,14 @@ // prints the disassembly for fmt and all its dependencies. // // For more about specifying packages, see 'go help packages'. -// For more about where packages and binaries are installed, -// run 'go help gopath'. +// For more about where binaries are installed, run 'go help gopath'. // For more about calling between Go and C/C++, run 'go help c'. +// For more about project organization, run 'go help modules'. // -// Note: Build adheres to certain conventions such as those described -// by 'go help gopath'. Not all projects can follow these conventions, +// Note: go build adheres to certain conventions for organizing projects: +// it primarily supports go modules (see 'go help modules') while +// also supporting an alternative GOPATH mode (see 'go help gopath'). +// Not all projects can follow these conventions, // however. Installations that have their own conventions or that use // a separate software build system may choose to use lower-level // invocations such as 'go tool compile' and 'go tool link' to avoid @@ -450,10 +452,13 @@ // Treat a command (package main) like a regular package. // Otherwise package main's exported symbols are hidden // when showing the package's top-level documentation. +// -ex +// Include executable examples. // -http // Serve HTML docs over HTTP. // -short -// One-line representation for each symbol. +// One-line representation for each symbol. Cannot be +// combined with -all. // -src // Show the full source code for the symbol. This will // display the full Go source of its declaration and @@ -507,7 +512,8 @@ // It supports these flags: // // -diff -// instead of applying each fix, print the patch as a unified diff +// instead of applying each fix, print the patch as a unified diff; +// exit with a non-zero status if the diff is not empty // // The -fixtool=prog flag selects a different analysis tool with // alternative or additional fixers; see the documentation for go vet's @@ -712,7 +718,7 @@ // // go get toolchain@patch // -// See https://golang.org/ref/mod#go-get for details. +// See https://go.dev/ref/mod#go-get for details. // // In earlier versions of Go, 'go get' was used to build and install packages. // Now, 'go get' is dedicated to adjusting dependencies in go.mod. 'go install' @@ -723,7 +729,7 @@ // go install example.com/pkg@v1.2.3 // go install example.com/pkg@latest // -// See 'go help install' or https://golang.org/ref/mod#go-install for details. +// See 'go help install' or https://go.dev/ref/mod#go-install for details. // // 'go get' accepts the following flags. // @@ -742,6 +748,7 @@ // // The -tool flag instructs go to add a matching tool line to go.mod for each // listed package. If -tool is used with @none, the line will be removed. +// See 'go help tool' for more information. // // The -x flag prints commands as they are executed. This is useful for // debugging version control commands when a module is downloaded directly @@ -749,7 +756,7 @@ // // For more about build flags, see 'go help build'. // -// For more about modules, see https://golang.org/ref/mod. +// For more about modules, see https://go.dev/ref/mod. // // For more about using 'go get' to update the minimum Go version and // suggested Go toolchain, see https://go.dev/doc/toolchain. @@ -1128,7 +1135,7 @@ // // For more about specifying packages, see 'go help packages'. // -// For more about modules, see https://golang.org/ref/mod. +// For more about modules, see https://go.dev/ref/mod. // // # Module maintenance // @@ -1206,9 +1213,9 @@ // // The -x flag causes download to print the commands download executes. // -// See https://golang.org/ref/mod#go-mod-download for more about 'go mod download'. +// See https://go.dev/ref/mod#go-mod-download for more about 'go mod download'. // -// See https://golang.org/ref/mod#version-queries for more about version queries. +// See https://go.dev/ref/mod#version-queries for more about version queries. // // # Edit go.mod from tools or scripts // @@ -1247,10 +1254,14 @@ // // The -go=version flag sets the expected Go language version. // This flag is mainly for tools that understand Go version dependencies. +// It takes a version like "1.26" or "1.26.2". +// Using the version "none" removes the go directive. // Users should prefer 'go get go@version'. // -// The -toolchain=version flag sets the Go toolchain to use. +// The -toolchain=name flag sets the Go toolchain to use. // This flag is mainly for tools that understand Go version dependencies. +// It takes a toolchain name like "go1.26" or "go1.26.2". +// Using the name "none" removes the toolchain directive. // Users should prefer 'go get toolchain@version'. // // The -exclude=path@version and -dropexclude=path@version flags @@ -1353,7 +1364,7 @@ // // Edit also provides the -C, -n, and -x build flags. // -// See https://golang.org/ref/mod#go-mod-edit for more about 'go mod edit'. +// See https://go.dev/ref/mod#go-mod-edit for more about 'go mod edit'. // // # Print module requirement graph // @@ -1372,7 +1383,7 @@ // // The -x flag causes graph to print the commands graph executes. // -// See https://golang.org/ref/mod#go-mod-graph for more about 'go mod graph'. +// See https://go.dev/ref/mod#go-mod-graph for more about 'go mod graph'. // // # Initialize new module in current directory // @@ -1388,7 +1399,7 @@ // module path argument is omitted, init will attempt to infer the module path // using import comments in .go files and the current directory (if in GOPATH). // -// See https://golang.org/ref/mod#go-mod-init for more about 'go mod init'. +// See https://go.dev/ref/mod#go-mod-init for more about 'go mod init'. // // # Add missing and remove unused modules // @@ -1428,7 +1439,7 @@ // // The -x flag causes tidy to print the commands download executes. // -// See https://golang.org/ref/mod#go-mod-tidy for more about 'go mod tidy'. +// See https://go.dev/ref/mod#go-mod-tidy for more about 'go mod tidy'. // // # Make vendored copy of dependencies // @@ -1451,7 +1462,7 @@ // named "vendor" within the module root directory, so this flag is // primarily useful for other tools. // -// See https://golang.org/ref/mod#go-mod-vendor for more about 'go mod vendor'. +// See https://go.dev/ref/mod#go-mod-vendor for more about 'go mod vendor'. // // # Verify dependencies have expected content // @@ -1466,7 +1477,7 @@ // modules have been changed and causes 'go mod' to exit with a // non-zero status. // -// See https://golang.org/ref/mod#go-mod-verify for more about 'go mod verify'. +// See https://go.dev/ref/mod#go-mod-verify for more about 'go mod verify'. // // # Explain why packages or modules are needed // @@ -1503,256 +1514,7 @@ // (main module does not need package golang.org/x/text/encoding) // $ // -// See https://golang.org/ref/mod#go-mod-why for more about 'go mod why'. -// -// # Workspace maintenance -// -// Work provides access to operations on workspaces. -// -// Note that support for workspaces is built into many other commands, not -// just 'go work'. -// -// See 'go help modules' for information about Go's module system of which -// workspaces are a part. -// -// See https://go.dev/ref/mod#workspaces for an in-depth reference on -// workspaces. -// -// See https://go.dev/doc/tutorial/workspaces for an introductory -// tutorial on workspaces. -// -// A workspace is specified by a go.work file that specifies a set of -// module directories with the "use" directive. These modules are used as -// root modules by the go command for builds and related operations. A -// workspace that does not specify modules to be used cannot be used to do -// builds from local modules. -// -// go.work files are line-oriented. Each line holds a single directive, -// made up of a keyword followed by arguments. For example: -// -// go 1.18 -// -// use ../foo/bar -// use ./baz -// -// replace example.com/foo v1.2.3 => example.com/bar v1.4.5 -// -// The leading keyword can be factored out of adjacent lines to create a block, -// like in Go imports. -// -// use ( -// ../foo/bar -// ./baz -// ) -// -// The use directive specifies a module to be included in the workspace's -// set of main modules. The argument to the use directive is the directory -// containing the module's go.mod file. -// -// The go directive specifies the version of Go the file was written at. It -// is possible there may be future changes in the semantics of workspaces -// that could be controlled by this version, but for now the version -// specified has no effect. -// -// The replace directive has the same syntax as the replace directive in a -// go.mod file and takes precedence over replaces in go.mod files. It is -// primarily intended to override conflicting replaces in different workspace -// modules. -// -// To determine whether the go command is operating in workspace mode, use -// the "go env GOWORK" command. This will specify the workspace file being -// used. -// -// Usage: -// -// go work [arguments] -// -// The commands are: -// -// edit edit go.work from tools or scripts -// init initialize workspace file -// sync sync workspace build list to modules -// use add modules to workspace file -// vendor make vendored copy of dependencies -// -// Use "go help work " for more information about a command. -// -// # Edit go.work from tools or scripts -// -// Usage: -// -// go work edit [editing flags] [go.work] -// -// Edit provides a command-line interface for editing go.work, -// for use primarily by tools or scripts. It only reads go.work; -// it does not look up information about the modules involved. -// If no file is specified, Edit looks for a go.work file in the current -// directory and its parent directories -// -// The editing flags specify a sequence of editing operations. -// -// The -fmt flag reformats the go.work file without making other changes. -// This reformatting is also implied by any other modifications that use or -// rewrite the go.mod file. The only time this flag is needed is if no other -// flags are specified, as in 'go work edit -fmt'. -// -// The -godebug=key=value flag adds a godebug key=value line, -// replacing any existing godebug lines with the given key. -// -// The -dropgodebug=key flag drops any existing godebug lines -// with the given key. -// -// The -use=path and -dropuse=path flags -// add and drop a use directive from the go.work file's set of module directories. -// -// The -replace=old[@v]=new[@v] flag adds a replacement of the given -// module path and version pair. If the @v in old@v is omitted, a -// replacement without a version on the left side is added, which applies -// to all versions of the old module path. If the @v in new@v is omitted, -// the new path should be a local module root directory, not a module -// path. Note that -replace overrides any redundant replacements for old[@v], -// so omitting @v will drop existing replacements for specific versions. -// -// The -dropreplace=old[@v] flag drops a replacement of the given -// module path and version pair. If the @v is omitted, a replacement without -// a version on the left side is dropped. -// -// The -use, -dropuse, -replace, and -dropreplace, -// editing flags may be repeated, and the changes are applied in the order given. -// -// The -go=version flag sets the expected Go language version. -// -// The -toolchain=name flag sets the Go toolchain to use. -// -// The -print flag prints the final go.work in its text format instead of -// writing it back to go.mod. -// -// The -json flag prints the final go.work file in JSON format instead of -// writing it back to go.mod. The JSON output corresponds to these Go types: -// -// type GoWork struct { -// Go string -// Toolchain string -// Godebug []Godebug -// Use []Use -// Replace []Replace -// } -// -// type Godebug struct { -// Key string -// Value string -// } -// -// type Use struct { -// DiskPath string -// ModulePath string -// } -// -// type Replace struct { -// Old Module -// New Module -// } -// -// type Module struct { -// Path string -// Version string -// } -// -// See the workspaces reference at https://go.dev/ref/mod#workspaces -// for more information. -// -// # Initialize workspace file -// -// Usage: -// -// go work init [moddirs] -// -// Init initializes and writes a new go.work file in the -// current directory, in effect creating a new workspace at the current -// directory. -// -// go work init optionally accepts paths to the workspace modules as -// arguments. If the argument is omitted, an empty workspace with no -// modules will be created. -// -// Each argument path is added to a use directive in the go.work file. The -// current go version will also be listed in the go.work file. -// -// See the workspaces reference at https://go.dev/ref/mod#workspaces -// for more information. -// -// # Sync workspace build list to modules -// -// Usage: -// -// go work sync -// -// Sync syncs the workspace's build list back to the -// workspace's modules -// -// The workspace's build list is the set of versions of all the -// (transitive) dependency modules used to do builds in the workspace. go -// work sync generates that build list using the Minimal Version Selection -// algorithm, and then syncs those versions back to each of modules -// specified in the workspace (with use directives). -// -// The syncing is done by sequentially upgrading each of the dependency -// modules specified in a workspace module to the version in the build list -// if the dependency module's version is not already the same as the build -// list's version. Note that Minimal Version Selection guarantees that the -// build list's version of each module is always the same or higher than -// that in each workspace module. -// -// See the workspaces reference at https://go.dev/ref/mod#workspaces -// for more information. -// -// # Add modules to workspace file -// -// Usage: -// -// go work use [-r] [moddirs] -// -// Use provides a command-line interface for adding -// directories, optionally recursively, to a go.work file. -// -// A use directive will be added to the go.work file for each argument -// directory listed on the command line go.work file, if it exists, -// or removed from the go.work file if it does not exist. -// Use fails if any remaining use directives refer to modules that -// do not exist. -// -// Use updates the go line in go.work to specify a version at least as -// new as all the go lines in the used modules, both preexisting ones -// and newly added ones. With no arguments, this update is the only -// thing that go work use does. -// -// The -r flag searches recursively for modules in the argument -// directories, and the use command operates as if each of the directories -// were specified as arguments. -// -// See the workspaces reference at https://go.dev/ref/mod#workspaces -// for more information. -// -// # Make vendored copy of dependencies -// -// Usage: -// -// go work vendor [-e] [-v] [-o outdir] -// -// Vendor resets the workspace's vendor directory to include all packages -// needed to build and test all the workspace's packages. -// It does not include test code for vendored packages. -// -// The -v flag causes vendor to print the names of vendored -// modules and packages to standard error. -// -// The -e flag causes vendor to attempt to proceed despite errors -// encountered while loading packages. -// -// The -o flag causes vendor to create the vendor directory at the given -// path instead of "vendor". The go command can only use a vendor directory -// named "vendor" within the module root directory, so this flag is -// primarily useful for other tools. +// See https://go.dev/ref/mod#go-mod-why for more about 'go mod why'. // // # Compile and run Go program // @@ -1792,6 +1554,10 @@ // used by debuggers, to reduce build time. To include debugger information in // the binary, use 'go build'. // +// The go command places $GOROOT/bin at the beginning of $PATH in the +// subprocess environment, so that subprocesses that execute 'go' commands +// use the same 'go' as their parent. +// // The exit status of Run is not the exit status of the compiled binary. // // For more about build flags, see 'go help build'. @@ -1869,11 +1635,11 @@ // and its test source files to identify significant problems. If go vet // finds any problems, go test reports those and does not run the test // binary. Only a high-confidence subset of the default go vet checks are -// used. That subset is: atomic, bool, buildtags, directive, errorsas, -// ifaceassert, nilfunc, printf, stringintconv, and tests. You can see -// the documentation for these and other vet tests via "go doc cmd/vet". -// To disable the running of go vet, use the -vet=off flag. To run all -// checks, use the -vet=all flag. +// used. That subset is: atomic, bools, buildtag, directive, errorsas, +// ifaceassert, nilfunc, printf, stdversion, stringintconv, and tests. +// You can see the documentation for these and other vet tests via +// "go doc cmd/vet". To disable the running of go vet, use the -vet=off flag. +// To run all checks, use the -vet=all flag. // // All test output and summary lines are printed to the go command's // standard output, even if the test printed them to its own standard @@ -1953,8 +1719,8 @@ // Also emits build output in JSON. See 'go help buildjson'. // // -o file -// Compile the test binary to the named file. -// The test still runs (unless -c or -i is specified). +// Save a copy of the test binary to the named file. +// The test still runs (unless -c is specified). // If file ends in a slash or names an existing directory, // the test is written to pkg.test in that directory. // @@ -1975,7 +1741,14 @@ // Tool runs the go tool command identified by the arguments. // // Go ships with a number of builtin tools, and additional tools -// may be defined in the go.mod of the current module. +// may be defined in the go.mod of the current module. 'go get -tool' +// can be used to define additional tools in the current module's +// go.mod file. See 'go help get' for more information. +// +// The command can be specified using the full package path to the tool declared with +// a tool directive. The default binary name of the tool, which is the last component of +// the package path, excluding the major version suffix, can also be used if it is unique +// among declared tools. // // With no arguments it prints the list of known tools. // @@ -1987,6 +1760,10 @@ // // Tool also provides the -C, -overlay, and -modcacherw build flags. // +// The go command places $GOROOT/bin at the beginning of $PATH in the +// environment of commands run via tool directives, so that they use the +// same 'go' as the parent 'go tool'. +// // For more about build flags, see 'go help build'. // // For more about each builtin tool command, see 'go doc cmd/'. @@ -2037,7 +1814,8 @@ // -fix // instead of printing each diagnostic, apply its first fix (if any) // -diff -// instead of applying each fix, print the patch as a unified diff +// instead of applying each fix, print the patch as a unified diff; +// exit with a non-zero status if the diff is not empty // // The -vettool=prog flag selects a different analysis tool with // alternative or additional checks. For example, the 'shadow' analyzer @@ -2061,9 +1839,269 @@ // // See also: go fmt, go fix. // -// # Build constraints +// # Workspace maintenance // -// A build constraint, also known as a build tag, is a condition under which a +// Work provides access to operations on workspaces. +// +// Note that support for workspaces is built into many other commands, not +// just 'go work'. +// +// See 'go help modules' for information about Go's module system of which +// workspaces are a part. +// +// See https://go.dev/ref/mod#workspaces for an in-depth reference on +// workspaces. +// +// See https://go.dev/doc/tutorial/workspaces for an introductory +// tutorial on workspaces. +// +// A workspace is specified by a go.work file that specifies a set of +// module directories with the "use" directive. These modules are used as +// root modules by the go command for builds and related operations. A +// workspace that does not specify modules to be used cannot be used to do +// builds from local modules. +// +// go.work files are line-oriented. Each line holds a single directive, +// made up of a keyword followed by arguments. For example: +// +// go 1.18 +// +// use ../foo/bar +// use ./baz +// +// replace example.com/foo v1.2.3 => example.com/bar v1.4.5 +// +// The leading keyword can be factored out of adjacent lines to create a block, +// like in Go imports. +// +// use ( +// ../foo/bar +// ./baz +// ) +// +// The use directive specifies a module to be included in the workspace's +// set of main modules. The argument to the use directive is the directory +// containing the module's go.mod file. The go command does not resolve +// symbolic links when matching use paths to module directories, so a +// symlink to a directory is not interchangeable with its target. +// +// The go directive specifies the version of Go the file was written at. It +// is possible there may be future changes in the semantics of workspaces +// that could be controlled by this version, but for now the version +// specified has no effect. +// +// The replace directive has the same syntax as the replace directive in a +// go.mod file and takes precedence over replaces in go.mod files. It is +// primarily intended to override conflicting replaces in different workspace +// modules. +// +// To determine whether the go command is operating in workspace mode, use +// the "go env GOWORK" command. This will specify the workspace file being +// used. +// +// Usage: +// +// go work [arguments] +// +// The commands are: +// +// edit edit go.work from tools or scripts +// init initialize workspace file +// sync sync workspace build list to modules +// use add modules to workspace file +// vendor make vendored copy of dependencies +// +// Use "go help work " for more information about a command. +// +// # Edit go.work from tools or scripts +// +// Usage: +// +// go work edit [editing flags] [go.work] +// +// Edit provides a command-line interface for editing go.work, +// for use primarily by tools or scripts. It only reads go.work; +// it does not look up information about the modules involved. +// If no file is specified, Edit looks for a go.work file in the current +// directory and its parent directories +// +// The editing flags specify a sequence of editing operations. +// +// The -fmt flag reformats the go.work file without making other changes. +// This reformatting is also implied by any other modifications that use or +// rewrite the go.work file. The only time this flag is needed is if no other +// flags are specified, as in 'go work edit -fmt'. +// +// The -godebug=key=value flag adds a godebug key=value line, +// replacing any existing godebug lines with the given key. +// +// The -dropgodebug=key flag drops any existing godebug lines +// with the given key. +// +// The -use=path and -dropuse=path flags +// add and drop a use directive from the go.work file's set of module directories. +// +// The -replace=old[@v]=new[@v] flag adds a replacement of the given +// module path and version pair. If the @v in old@v is omitted, a +// replacement without a version on the left side is added, which applies +// to all versions of the old module path. If the @v in new@v is omitted, +// the new path should be a local module root directory, not a module +// path. Note that -replace overrides any redundant replacements for old[@v], +// so omitting @v will drop existing replacements for specific versions. +// +// The -dropreplace=old[@v] flag drops a replacement of the given +// module path and version pair. If the @v is omitted, a replacement without +// a version on the left side is dropped. +// +// The -use, -dropuse, -replace, and -dropreplace, +// editing flags may be repeated, and the changes are applied in the order given. +// +// The -go=version flag sets the expected Go language version. +// It takes a version like "1.26" or "1.26.2". +// Using "none" as the version removes the go directive. +// +// The -toolchain=name flag sets the Go toolchain to use. +// It takes a toolchain name like "go1.26" or "go1.26.2". +// Using "none" as the name removes the toolchain directive. +// +// The -print flag prints the final go.work in its text format instead of +// writing it back to go.work. +// +// The -json flag prints the final go.work file in JSON format instead of +// writing it back to go.work. The JSON output corresponds to these Go types: +// +// type GoWork struct { +// Go string +// Toolchain string +// Godebug []Godebug +// Use []Use +// Replace []Replace +// } +// +// type Godebug struct { +// Key string +// Value string +// } +// +// type Use struct { +// DiskPath string +// ModulePath string +// } +// +// type Replace struct { +// Old Module +// New Module +// } +// +// type Module struct { +// Path string +// Version string +// } +// +// See the workspaces reference at https://go.dev/ref/mod#workspaces +// for more information. +// +// # Initialize workspace file +// +// Usage: +// +// go work init [moddirs] +// +// Init initializes and writes a new go.work file in the +// current directory, in effect creating a new workspace at the current +// directory. +// +// go work init optionally accepts paths to the workspace modules as +// arguments. If the argument is omitted, an empty workspace with no +// modules will be created. +// +// Each argument path is added to a use directive in the go.work file. The +// current go version will also be listed in the go.work file. +// +// See the workspaces reference at https://go.dev/ref/mod#workspaces +// for more information. +// +// # Sync workspace build list to modules +// +// Usage: +// +// go work sync +// +// Sync syncs the workspace's build list back to the +// workspace's modules +// +// The workspace's build list is the set of versions of all the +// (transitive) dependency modules used to do builds in the workspace. go +// work sync generates that build list using the Minimal Version Selection +// algorithm, and then syncs those versions back to each of modules +// specified in the workspace (with use directives). +// +// The syncing is done by sequentially upgrading each of the dependency +// modules specified in a workspace module to the version in the build list +// if the dependency module's version is not already the same as the build +// list's version. Note that Minimal Version Selection guarantees that the +// build list's version of each module is always the same or higher than +// that in each workspace module. +// +// See the workspaces reference at https://go.dev/ref/mod#workspaces +// for more information. +// +// # Add modules to workspace file +// +// Usage: +// +// go work use [-r] [moddirs] +// +// Use provides a command-line interface for adding +// directories, optionally recursively, to a go.work file. +// +// A use directive will be added to the go.work file for each argument +// directory listed on the command line go.work file, if it exists, +// or removed from the go.work file if it does not exist. +// Use fails if any remaining use directives refer to modules that +// do not exist. +// +// Use updates the go line in go.work to specify a version at least as +// new as all the go lines in the used modules, both preexisting ones +// and newly added ones. With no arguments, this update is the only +// thing that go work use does. +// +// The -r flag searches recursively for modules in the argument +// directories, and the use command operates as if each of the directories +// were specified as arguments. When -r is used, symlinks to directories +// within the argument tree are ignored. +// +// The go command matches use paths to module directories without resolving +// symbolic links. A use directive that names a symlink to a directory is +// not interchangeable with one that names the symlink's target. +// +// See the workspaces reference at https://go.dev/ref/mod#workspaces +// for more information. +// +// # Make vendored copy of dependencies +// +// Usage: +// +// go work vendor [-e] [-v] [-o outdir] +// +// Vendor resets the workspace's vendor directory to include all packages +// needed to build and test all the workspace's packages. +// It does not include test code for vendored packages. +// +// The -v flag causes vendor to print the names of vendored +// modules and packages to standard error. +// +// The -e flag causes vendor to attempt to proceed despite errors +// encountered while loading packages. +// +// The -o flag causes vendor to create the vendor directory at the given +// path instead of "vendor". The go command can only use a vendor directory +// named "vendor" within the module root directory, so this flag is +// primarily useful for other tools. +// +// # Build constraints +// +// A build constraint, also known as a build tag, is a condition under which a // file should be included in the package. Build constraints are given by a // line comment that begins // @@ -2190,6 +2228,12 @@ // building the package for Windows; similarly, math_386.s will be included // only when building the package for 32-bit x86. // +// By convention, packages with assembly implementations may provide a go-only +// version under the "purego" build constraint. This does not limit the use of +// cgo (use the "cgo" build constraint) or unsafe. For example: +// +// //go:build purego +// // Go versions 1.16 and earlier used a different syntax for build constraints, // with a "// +build" prefix. The gofmt command will add an equivalent //go:build // constraint when encountering the older syntax. @@ -2357,6 +2401,10 @@ // GODEBUG=gocachetest=1 causes the go command to print details of its // decisions about whether to reuse a cached test result. // +// The GOCACHEPROG environment variable can be used to provide an +// externally managed build cache. For details see: +// "go doc cmd/go/internal/cacheprog". +// // # Environment variables // // The go command and the tools it invokes consult environment variables @@ -2378,7 +2426,7 @@ // GO111MODULE // Controls whether the go command runs in module-aware mode or GOPATH mode. // May be "off", "on", or "auto". -// See https://golang.org/ref/mod#mod-commands. +// See https://go.dev/ref/mod#mod-commands. // GOARCH // The architecture, or processor, for which to compile code. // Examples are amd64, 386, arm, ppc64. @@ -2427,15 +2475,15 @@ // Comma-separated list of glob patterns (in the syntax of Go's path.Match) // of module path prefixes that should always be fetched directly // or that should not be compared against the checksum database. -// See https://golang.org/ref/mod#private-modules. +// See https://go.dev/ref/mod#private-modules. // GOPROXY -// URL of Go module proxy. See https://golang.org/ref/mod#environment-variables -// and https://golang.org/ref/mod#module-proxy for details. +// URL of Go module proxy. See https://go.dev/ref/mod#environment-variables +// and https://go.dev/ref/mod#module-proxy for details. // GOROOT // The root of the go tree. // GOSUMDB // The name of checksum database to use and optionally its public key and -// URL. See https://golang.org/ref/mod#authenticating. +// URL. See https://go.dev/ref/mod#authenticating. // GOTMPDIR // Temporary directory used by the go command and testing package. // Overrides the platform-specific temporary directory such as "/tmp". @@ -2503,7 +2551,7 @@ // GOAMD64 // For GOARCH=amd64, the microarchitecture level for which to compile. // Valid values are v1 (default), v2, v3, v4. -// See https://golang.org/wiki/MinimumRequirements#amd64 +// See https://go.dev/wiki/MinimumRequirements#amd64 // GOARM // For GOARCH=arm, the ARM architecture for which to compile. // Valid values are 5, 6, 7. @@ -2709,40 +2757,62 @@ // marking the root of the main (current) module. // // The go.mod file format is described in detail at -// https://golang.org/ref/mod#go-mod-file. +// https://go.dev/ref/mod#go-mod-file. // // To create a new go.mod file, use 'go mod init'. For details see -// 'go help mod init' or https://golang.org/ref/mod#go-mod-init. +// 'go help mod init' or https://go.dev/ref/mod#go-mod-init. // // To add missing module requirements or remove unneeded requirements, // use 'go mod tidy'. For details, see 'go help mod tidy' or -// https://golang.org/ref/mod#go-mod-tidy. +// https://go.dev/ref/mod#go-mod-tidy. // // To add, upgrade, downgrade, or remove a specific module requirement, use // 'go get'. For details, see 'go help module-get' or -// https://golang.org/ref/mod#go-get. +// https://go.dev/ref/mod#go-get. // // To make other changes or to parse go.mod as JSON for use by other tools, // use 'go mod edit'. See 'go help mod edit' or -// https://golang.org/ref/mod#go-mod-edit. +// https://go.dev/ref/mod#go-mod-edit. // // # GOPATH environment variable // -// The Go path is used to resolve import statements. -// It is implemented by and documented in the go/build package. -// -// The GOPATH environment variable lists places to look for Go code. -// On Unix, the value is a colon-separated string. -// On Windows, the value is a semicolon-separated string. -// On Plan 9, the value is a list. +// The GOPATH environment variable is used to change the default +// location to store the module cache and installed binaries, if +// not overridden by GOMODCACHE and GOBIN respectively. // +// Most users don't need to explicitly set GOPATH. // If the environment variable is unset, GOPATH defaults // to a subdirectory named "go" in the user's home directory // ($HOME/go on Unix, %USERPROFILE%\go on Windows), // unless that directory holds a Go distribution. // Run "go env GOPATH" to see the current GOPATH. // -// See https://golang.org/wiki/SettingGOPATH to set a custom GOPATH. +// The module cache is stored in the directory specified by +// GOPATH/pkg/mod. If GOMODCACHE is set, it will be used +// as the directory to store the module cache instead. +// +// Executables installed using 'go install' are placed in the +// directory specified by GOPATH/bin or, if GOBIN is set, by GOBIN. +// +// # GOPATH mode +// +// The GOPATH environment variable is also used by a legacy behavior of the +// toolchain called GOPATH mode that allows some older projects, created before +// modules were introduced in Go 1.11 and never updated to use modules, +// to continue to build. +// +// GOPATH mode is enabled when modules are disabled, either when GO111MODULE=off, +// or when GO111MODULE=auto, and the working directory is not in a module or workspace. +// +// In GOPATH mode, packages are located using the GOPATH environment variable, +// which specifies a list of paths to search: +// On Unix, the value is a colon-separated string. +// On Windows, the value is a semicolon-separated string. +// On Plan 9, the value is a list. +// The first element of this list is used to set the default module cache and +// binary install directory locations as described above. +// +// See https://go.dev/wiki/SettingGOPATH to set a custom GOPATH. // // Each directory listed in GOPATH must have a prescribed structure: // @@ -2790,49 +2860,11 @@ // but new packages are always downloaded into the first directory // in the list. // -// See https://golang.org/doc/code.html for an example. -// -// # GOPATH and Modules -// -// When using modules, GOPATH is no longer used for resolving imports. -// However, it is still used to store downloaded source code (in GOPATH/pkg/mod) -// and compiled commands (in GOPATH/bin). -// -// # Internal Directories +// See https://go.dev/doc/code.html for an example. // -// Code in or below a directory named "internal" is importable only -// by code in the directory tree rooted at the parent of "internal". -// Here's an extended version of the directory layout above: -// -// /home/user/go/ -// src/ -// crash/ -// bang/ (go code in package bang) -// b.go -// foo/ (go code in package foo) -// f.go -// bar/ (go code in package bar) -// x.go -// internal/ -// baz/ (go code in package baz) -// z.go -// quux/ (go code in package main) -// y.go -// -// The code in z.go is imported as "foo/internal/baz", but that -// import statement can only appear in source files in the subtree -// rooted at foo. The source files foo/f.go, foo/bar/x.go, and -// foo/quux/y.go can all import "foo/internal/baz", but the source file -// crash/bang/b.go cannot. +// # GOPATH mode vendor directories // -// See https://golang.org/s/go14internal for details. -// -// # Vendor Directories -// -// Go 1.6 includes support for using local copies of external dependencies -// to satisfy imports of those dependencies, often referred to as vendoring. -// -// Code below a directory named "vendor" is importable only +// In GOPATH mode, code below a directory named "vendor" is importable only // by code in the directory tree rooted at the parent of "vendor", // and only using an import path that omits the prefix up to and // including the vendor element. @@ -2862,22 +2894,25 @@ // The same visibility rules apply as for internal, but the code // in z.go is imported as "baz", not as "foo/vendor/baz". // -// Code in vendor directories deeper in the source tree shadows +// Code in GOPATH mode vendor directories deeper in the source tree shadows // code in higher directories. Within the subtree rooted at foo, an import // of "crash/bang" resolves to "foo/vendor/crash/bang", not the // top-level "crash/bang". // -// Code in vendor directories is not subject to import path -// checking (see 'go help importpath'). +// Code in GOPATH mode vendor directories is not subject to +// GOPATH mode import path checking (see 'go help importpath'). // -// When 'go get' checks out or updates a git repository, it now also -// updates submodules. +// In GOPATH mode, the default GODEBUG values built into a binary +// will be the same GODEBUG values as when a module specifies +// "godebug default=go1.20". To use different GODEBUG settings, the +// GODEBUG environment variable must be set to override those values. +// This also means that the standard library tests will not run +// properly with GO111MODULE=off. // -// Vendor directories do not affect the placement of new repositories -// being checked out for the first time by 'go get': those are always -// placed in the main GOPATH, never in a vendor subtree. +// See https://go.dev/s/go15vendor for details. // -// See https://golang.org/s/go15vendor for details. +// See https://go.dev/ref/mod#vendoring for details about vendoring in +// module mode. // // # Module proxy protocol // @@ -2887,46 +2922,80 @@ // can be a module proxy. // // For details on the GOPROXY protocol, see -// https://golang.org/ref/mod#goproxy-protocol. +// https://go.dev/ref/mod#goproxy-protocol. // // # Import path syntax // -// An import path (see 'go help packages') denotes a package stored in the local -// file system. In general, an import path denotes either a standard package (such -// as "unicode/utf8") or a package found in one of the work spaces (For more -// details see: 'go help gopath'). +// An import path is used to uniquely identify and locate a package. +// In general, an import path denotes either a standard library package +// (such as "unicode/utf8") or a package found in a module (for more +// details see: 'go help modules'). // -// # Relative import paths +// The standard library reserves all import paths without a dot in the +// first element for its packages. See "Fully-qualified import paths" +// below for choosing an import path for your module. +// The following names are reserved to be used as short module names +// when working locally, and in tutorials, examples, and test code. // -// An import path beginning with ./ or ../ is called a relative path. -// The toolchain supports relative import paths as a shortcut in two ways. +// - "test" +// - "example" // -// First, a relative path can be used as a shorthand on the command line. -// If you are working in the directory containing the code imported as -// "unicode" and want to run the tests for "unicode/utf8", you can type -// "go test ./utf8" instead of needing to specify the full path. -// Similarly, in the reverse situation, "go test .." will test "unicode" from -// the "unicode/utf8" directory. Relative patterns are also allowed, like -// "go test ./..." to test all subdirectories. See 'go help packages' for details -// on the pattern syntax. +// # Internal packages +// +// Code in or below a directory named "internal" is importable only +// by code that shares the same import path above the internal directory. +// Here's an example directory layout of a module example.com/m: +// +// /home/user/modules/m/ +// go.mod (declares module example.com/m) +// crash/ +// bang/ (go code in package bang) +// b.go +// foo/ (go code in package foo) +// f.go +// bar/ (go code in package bar) +// x.go +// internal/ +// baz/ (go code in package baz) +// z.go +// quux/ (go code in package quux) +// y.go +// +// The code in z.go is imported as "example.com/m/foo/internal/baz", but that +// import statement can only appear in packages with the import path prefix +// "example.com/m/foo". The packages "example.com/m/foo", "example.com/m/foo/bar", and +// "example.com/m/foo/quux" can all import "foo/internal/baz", but the package +// "example.com/m/crash/bang" cannot. // -// Second, if you are compiling a Go program not in a work space, -// you can use a relative path in an import statement in that program -// to refer to nearby code also not in a work space. -// This makes it easy to experiment with small multipackage programs -// outside of the usual work spaces, but such programs cannot be -// installed with "go install" (there is no work space in which to install them), -// so they are rebuilt from scratch each time they are built. -// To avoid ambiguity, Go programs cannot use relative import paths -// within a work space. +// See https://go.dev/s/go14internal for details. // -// # Remote import paths +// # Fully-qualified import paths +// +// A fully-qualified import path for a package not belonging to the standard library +// starts with the path of the module the package to which the package belongs. +// The module's path specifies where to obtain the source code for the module. +// The complete import path is formed by joining the module path with the +// relative directory path of a package within the module. Example: +// +// /home/user/modules/m/ +// go.mod (declares "module example.com/m") +// crash/ +// bang/ (importable as "example.com/m/crash/bang") +// b.go +// foo/ (importable as "example.com/m/foo") +// f.go +// bar/ (importable as "example.com/m/foo/bar") +// x.go // -// Certain import paths also -// describe how to obtain the source code for the package using -// a revision control system. +// As import paths without a dot in the first element are reserved by the standard library, +// module paths (which form the prefix of all import paths) should start with an element +// containing a dot, e.g. "github.com/user/repo", or "example.com/project". +// A module path may point directly to a code hosting service, +// or to a custom address that points to the code hosting service in a html meta tags. +// Modules may also use the reserved names "example" for documentation +// and "test" for testing. These modules cannot be fetched by the go command. // -// A few common code hosting sites have special syntax: +// Import paths belonging to modules hosted on common code hosting sites have special syntax: // // Bitbucket (Git, Mercurial) // @@ -2952,7 +3021,7 @@ // import "hub.jazz.net/git/user/project" // import "hub.jazz.net/git/user/project/sub/directory" // -// For code hosted on other servers, import paths may either be qualified +// For modules hosted on other servers, import paths may either be qualified // with the version control type, or the go tool can dynamically fetch // the import path over https/http and discover where the code resides // from a tag in the HTML. @@ -2965,7 +3034,6 @@ // using the named version control system, and then the path inside // that repository. The supported version control systems are: // -// Bazaar .bzr // Fossil .fossil // Git .git // Mercurial .hg @@ -3015,7 +3083,7 @@ // In particular, it should appear before any raw JavaScript or CSS, // to avoid confusing the go command's restricted parser. // -// The vcs is one of "bzr", "fossil", "git", "hg", "svn". +// The vcs is one of "fossil", "git", "hg", "svn". // // The repo-root is the root of the version control system // containing a scheme and not containing a .vcs qualifier. @@ -3050,10 +3118,10 @@ // tag and then download the code from the "foo/subdir" subdirectory within the Git repository // at https://code.org/r/p/exproj // -// Downloaded packages are stored in the module cache. -// See https://golang.org/ref/mod#module-cache. +// Downloaded modules are stored in the module cache. +// See https://go.dev/ref/mod#module-cache. // -// When using modules, an additional variant of the go-import meta tag is +// An additional variant of the go-import meta tag is // recognized and is preferred over those listing version control systems. // That variant uses "mod" as the vcs in the content value, as in: // @@ -3061,35 +3129,9 @@ // // This tag means to fetch modules with paths beginning with example.org // from the module proxy available at the URL https://code.org/moduleproxy. -// See https://golang.org/ref/mod#goproxy-protocol for details about the +// See https://go.dev/ref/mod#goproxy-protocol for details about the // proxy protocol. // -// # Import path checking -// -// When the custom import path feature described above redirects to a -// known code hosting site, each of the resulting packages has two possible -// import paths, using the custom domain or the known hosting site. -// -// A package statement is said to have an "import comment" if it is immediately -// followed (before the next newline) by a comment of one of these two forms: -// -// package math // import "path" -// package math /* import "path" */ -// -// The go command will refuse to install a package with an import comment -// unless it is being referred to by that import path. In this way, import comments -// let package authors make sure the custom import path is used and not a -// direct path to the underlying code hosting site. -// -// Import path checking is disabled for code found within vendor trees. -// This makes it possible to copy code into alternate locations in vendor trees -// without needing to update import comments. -// -// Import path checking is also disabled when using modules. -// Import path comments are obsoleted by the go.mod file's module statement. -// -// See https://golang.org/s/go14customimport for details. -// // # Modules, module versions, and more // // Modules are how Go manages dependencies. @@ -3099,9 +3141,9 @@ // repositories or from module proxy servers. // // For a series of tutorials on modules, see -// https://golang.org/doc/tutorial/create-module. +// https://go.dev/doc/tutorial/create-module. // -// For a detailed reference on modules, see https://golang.org/ref/mod. +// For a detailed reference on modules, see https://go.dev/ref/mod. // // By default, the go command may download modules from https://proxy.golang.org. // It may authenticate modules using the checksum database at @@ -3112,7 +3154,7 @@ // // The go command's download behavior may be configured using GOPROXY, GOSUMDB, // GOPRIVATE, and other environment variables. See 'go help environment' -// and https://golang.org/ref/mod#private-module-privacy for more information. +// and https://go.dev/ref/mod#private-module-privacy for more information. // // # Module authentication using go.sum // @@ -3123,7 +3165,7 @@ // may also be downloaded from the checksum database depending on the values of // GOSUMDB, GOPRIVATE, and GONOSUMDB. // -// For details, see https://golang.org/ref/mod#authenticating. +// For details, see https://go.dev/ref/mod#authenticating. // // # Package lists and patterns // @@ -3131,91 +3173,145 @@ // // go [packages] // -// Usually, [packages] is a list of import paths. +// Usually, [packages] is a list of package patterns, +// which can take several forms: // -// An import path that is a rooted path or that begins with -// a . or .. element is interpreted as a file system path and -// denotes the package in that directory. -// -// Otherwise, the import path P denotes the package found in -// the directory DIR/src/P for some DIR listed in the GOPATH -// environment variable (For more details see: 'go help gopath'). +// - A relative or absolute path to a file system directory, +// which can contain "..." wildcard elements. +// - An import path, which can also contain "..." wildcard elements. +// - A reserved name that expands to a set of packages +// - A list of files // // If no import paths are given, the action applies to the // package in the current directory. // -// There are five reserved names for paths that should not be used -// for packages to be built with the go tool: +// "..." elements in filesystem or import paths expand +// to match 0 or more path elements. +// Specific rules are described below. // -// - "main" denotes the top-level package in a stand-alone executable. +// # File system patterns +// +// Patterns beginning with a file system root like / on Unixes, +// or a volume name like C: on Windows are interpreted as absolute file system paths. +// Patterns beginning with a "." or ".." element are interpreted as relative file system paths. +// File system paths denote the package contained within the given directory. +// +// Relative paths can be used as a shorthand on the command line. +// If you are working in the directory containing the code imported as +// "unicode" and want to run the tests for "unicode/utf8", you can type +// "go test ./utf8" instead of needing to specify the full path. +// Similarly, in the reverse situation, "go test .." will test "unicode" from +// the "unicode/utf8" directory. Relative patterns are also allowed, such as +// "go test ./..." to test all subdirectories. +// +// File system patterns expanded with the "..." wildcard exclude the following: +// +// - Directories named "vendor" +// - Directories named "testdata" +// - Files and directories with names beginning with "_" or "." +// - Directories that contain a go.mod file +// - Directories matching an ignore directive in a module's go.mod file +// +// These can be included by either using them in the prefix, +// or changing into the directories. For example, "./..." won't +// match a "./testdata/foo" package, but "./testdata/..." will. +// +// Directories containing other go modules, +// which are denoted by the presence of a go.mod file, +// can only be matched by changing the working directory into module. +// +// # Import path patterns +// +// Patterns may be import paths as described in "go help importpath". +// Import path patterns natch the packages from modules in the build list. +// The "build list" is the list of module versions used for a build. +// See https://go.dev/ref/mod#glos-build-list for more details. +// +// Some commands accept versioned package patterns, +// such as: "example.com/my/module@v1.2.3" +// These describe the matching package at the given version, +// independent of the versions used by the current module. +// +// Import path patterns may also use a "..." wildcard, +// such as: "example.com/my/module/...". +// This can be combined with the version specifier +// such as: "example.com/my/module/...@latest". +// +// Import path pattern expansion with "..." depends on context: +// +// - "prefix/..." matches all packages in modules in the build list +// that share the prefix, even if they belong to different modules. +// - patterns that include a version specifier such as in "prefix/...@latest" +// only match packages from the module that "prefix" belongs to. +// +// # Reserved names +// +// The following reserved names expand to a set of packages: +// +// - "work" expands to all packages in the main module (or workspace modules). +// +// - "tool" expands to the tools defined in the current module's go.mod file. // // - "all" expands to all packages in the main module (or workspace modules) and // their dependencies, including dependencies needed by tests of any of those. In -// GOPATH mode, "all" expands to all packages found in all the GOPATH trees. +// the legacy GOPATH mode, "all" expands to all packages found in all the GOPATH trees. // -// - "std" is like all but expands to just the packages in the standard -// Go library. +// - "std" expands to all the packages in the standard library +// and their internal libraries. // // - "cmd" expands to the Go repository's commands and their // internal libraries. // -// - "tool" expands to the tools defined in the current module's go.mod file. +// # List of .go files +// +// If the pattern is a list of Go files rather than a complete package, +// the go command synthesizes a virtual package named "command-line-arguments" +// containing just the given files. In most cases, it is an error +// to do so (e.g. "go build main.go" or "go build *.go"). +// Instead prefer to operate on complete packages (directories), +// such as: "go build ." +// +// # Package names +// +// Packages are identified by their import path. +// Import paths for packages in the standard library use their +// relative path under "$GOROOT/src". +// Import paths for all other packages are a combination of their module name +// and their relative directory path within the module. +// Within a program, all packages must be identified by a unique import path. +// +// Packages also have names, declared with the "package" keyword +// in a .go file, and used as the identifier when imported +// by another package. By convention, the names of importable packages +// match the last element of their import path, generally the name +// of the directory containing the package. +// +// Package names do not have to be unique within a module, +// but packages that share the same name can't be imported +// together without one of them being aliased to a different name. +// +// As the go command primarily operates on directories, +// all non test .go files within a directory (excluding subdirectories) +// should share the same package declaration. +// Test files may suffix their package declaration with "_test", +// tests in these files are compiled as a separate package +// and don't have access to unexported identifiers of their corresponding +// package. See "go help test" and "go help testflag" for details. +// +// There following package names have special meanings: +// +// - "main" denotes the top-level package in a stand-alone executable. +// "main" packages cannot be imported. +// +// - "documentation" indicates documentation for a non-Go program +// in the directory. Files in package documentation are ignored +// by the go command. +// +// - "_test" suffix in "*_test.go" files. These form a separate test +// package that only has access to the colocated package's exported +// identifiers. See "go doc testing" for details. // -// Package names match against fully-qualified import paths or patterns that -// match against any number of import paths. For instance, "fmt" refers to the -// standard library's package fmt, but "http" alone for package http would not -// match the import path "net/http" from the standard library. Instead, the -// complete import path "net/http" must be used. -// -// Import paths beginning with "cmd/" only match source code in -// the Go repository. -// -// An import path is a pattern if it includes one or more "..." wildcards, -// each of which can match any string, including the empty string and -// strings containing slashes. Such a pattern expands to all package -// directories found in the GOPATH trees with names matching the -// patterns. -// -// To make common patterns more convenient, there are two special cases. -// First, /... at the end of the pattern can match an empty string, -// so that net/... matches both net and packages in its subdirectories, like net/http. -// Second, any slash-separated pattern element containing a wildcard never -// participates in a match of the "vendor" element in the path of a vendored -// package, so that ./... does not match packages in subdirectories of -// ./vendor or ./mycode/vendor, but ./vendor/... and ./mycode/vendor/... do. -// Note, however, that a directory named vendor that itself contains code -// is not a vendored package: cmd/vendor would be a command named vendor, -// and the pattern cmd/... matches it. -// See golang.org/s/go15vendor for more about vendoring. -// -// An import path can also name a package to be downloaded from -// a remote repository. Run 'go help importpath' for details. -// -// Every package in a program must have a unique import path. -// By convention, this is arranged by starting each path with a -// unique prefix that belongs to you. For example, paths used -// internally at Google all begin with 'google', and paths -// denoting remote repositories begin with the path to the code, -// such as 'github.com/user/repo'. Package patterns should include this prefix. -// For instance, a package called 'http' residing under 'github.com/user/repo', -// would be addressed with the fully-qualified pattern: -// 'github.com/user/repo/http'. -// -// Packages in a program need not have unique package names, -// but there are two reserved package names with special meaning. -// The name main indicates a command, not a library. -// Commands are built into binaries and cannot be imported. -// The name documentation indicates documentation for -// a non-Go program in the directory. Files in package documentation -// are ignored by the go command. -// -// As a special case, if the package list is a list of .go files from a -// single directory, the command is applied to a single synthesized -// package made up of exactly those files, ignoring any build constraints -// in those files and ignoring any other files in the directory. -// -// Directory and file names that begin with "." or "_" are ignored -// by the go tool, as are directories named "testdata". +// For more information about import paths, see "go help importpath". // // # Configuration for downloading non-public code // @@ -3256,7 +3352,7 @@ // The 'go env -w' command (see 'go help env') can be used to set these variables // for future go command invocations. // -// For more details, see https://golang.org/ref/mod#private-modules. +// For more details, see https://go.dev/ref/mod#private-modules. // // # Testing flags // @@ -3618,15 +3714,15 @@ // // # Controlling version control with GOVCS // -// The 'go get' command can run version control commands like git +// The go command can run version control commands like git // to download imported code. This functionality is critical to the decentralized // Go package ecosystem, in which code can be imported from any server, // but it is also a potential security problem, if a malicious server finds a // way to cause the invoked version control command to run unintended code. // -// To balance the functionality and security concerns, the 'go get' command +// To balance the functionality and security concerns, the go command // by default will only use git and hg to download code from public servers. -// But it will use any known version control system (bzr, fossil, git, hg, svn) +// But it will use any known version control system (fossil, git, hg, svn) // to download code from private servers, defined as those hosting packages // matching the GOPRIVATE variable (see 'go help private'). The rationale behind // allowing only Git and Mercurial is that these two systems have had the most @@ -3636,8 +3732,8 @@ // // The version control command restrictions only apply when using direct version // control access to download code. When downloading modules from a proxy, -// 'go get' uses the proxy protocol instead, which is always permitted. -// By default, the 'go get' command uses the Go module mirror (proxy.golang.org) +// the go command uses the proxy protocol instead, which is always permitted. +// By default, the go command uses the Go module mirror (proxy.golang.org) // for public packages and only falls back to version control for private // packages or when the mirror refuses to serve a public package (typically for // legal reasons). Therefore, clients can still access public code served from diff --git a/src/cmd/go/chdir_test.go b/src/cmd/go/chdir_test.go index 44cbb9c3f7339c..dd0eecd023355f 100644 --- a/src/cmd/go/chdir_test.go +++ b/src/cmd/go/chdir_test.go @@ -12,6 +12,8 @@ import ( ) func TestChdir(t *testing.T) { + t.Parallel() + // We want -C to apply to every go subcommand. // Test that every command either has a -C flag registered // or has CustomFlags set. In the latter case, the command diff --git a/src/cmd/go/go_test.go b/src/cmd/go/go_test.go index e4ee9bd1e8d2ec..47839e0229b951 100644 --- a/src/cmd/go/go_test.go +++ b/src/cmd/go/go_test.go @@ -487,11 +487,12 @@ func (tg *testgoData) goTool() string { // returning exit status. func (tg *testgoData) doRun(args []string) error { tg.t.Helper() - if tg.inParallel { - for _, arg := range args { - if strings.HasPrefix(arg, "testdata") || strings.HasPrefix(arg, "./testdata") { - tg.t.Fatal("internal testsuite error: parallel run using testdata") - } + if !tg.inParallel { + tg.t.Fatal("all tests using testgoData must run in parallel") + } + for _, arg := range args { + if strings.HasPrefix(arg, "testdata") || strings.HasPrefix(arg, "./testdata") { + tg.t.Fatal("internal testsuite error: parallel run using testdata") } } @@ -972,19 +973,6 @@ func TestNewReleaseRebuildsStalePackagesInGOPATH(t *testing.T) { tg.wantNotStale("p1", "", "./testgo list claims p1 is stale after building with old release") } -func TestPackageMainTestCompilerFlags(t *testing.T) { - tg := testgo(t) - defer tg.cleanup() - tg.parallel() - tg.makeTempdir() - tg.setenv("GOPATH", tg.path(".")) - tg.tempFile("src/p1/p1.go", "package main\n") - tg.tempFile("src/p1/p1_test.go", "package main\nimport \"testing\"\nfunc Test(t *testing.T){}\n") - tg.run("test", "-c", "-n", "p1") - tg.grepBothNot(`([\\/]compile|gccgo).* (-p main|-fgo-pkgpath=main).*p1\.go`, "should not have run compile -p main p1.go") - tg.grepStderr(`([\\/]compile|gccgo).* (-p p1|-fgo-pkgpath=p1).*p1\.go`, "should have run compile -p p1 p1.go") -} - // Issue 4104. func TestGoTestWithPackageListedMultipleTimes(t *testing.T) { tooSlow(t, "links and runs a test") @@ -1070,43 +1058,6 @@ func TestGoListDeps(t *testing.T) { } } -func TestGoListTest(t *testing.T) { - skipIfGccgo(t, "gccgo does not have standard packages") - tg := testgo(t) - defer tg.cleanup() - tg.parallel() - tg.makeTempdir() - tg.setenv("GOCACHE", tg.tempdir) - - tg.run("list", "-test", "-deps", "bytes") - tg.grepStdout(`^bytes.test$`, "missing test main") - tg.grepStdout(`^bytes$`, "missing real bytes") - tg.grepStdout(`^bytes \[bytes.test\]$`, "missing test copy of bytes") - tg.grepStdout(`^testing \[bytes.test\]$`, "missing test copy of testing") - tg.grepStdoutNot(`^testing$`, "unexpected real copy of testing") - - tg.run("list", "-test", "bytes") - tg.grepStdout(`^bytes.test$`, "missing test main") - tg.grepStdout(`^bytes$`, "missing real bytes") - tg.grepStdout(`^bytes \[bytes.test\]$`, "unexpected test copy of bytes") - tg.grepStdoutNot(`^testing \[bytes.test\]$`, "unexpected test copy of testing") - tg.grepStdoutNot(`^testing$`, "unexpected real copy of testing") - - tg.run("list", "-test", "cmd/buildid", "cmd/gofmt") - tg.grepStdout(`^cmd/buildid$`, "missing cmd/buildid") - tg.grepStdout(`^cmd/gofmt$`, "missing cmd/gofmt") - tg.grepStdout(`^cmd/gofmt\.test$`, "missing cmd/gofmt test") - tg.grepStdoutNot(`^cmd/buildid\.test$`, "unexpected cmd/buildid test") - tg.grepStdoutNot(`^testing`, "unexpected testing") - - tg.run("list", "-test", "runtime/cgo") - tg.grepStdout(`^runtime/cgo$`, "missing runtime/cgo") - - tg.run("list", "-deps", "-f", "{{if .DepOnly}}{{.ImportPath}}{{end}}", "sort") - tg.grepStdout(`^internal/reflectlite$`, "missing internal/reflectlite") - tg.grepStdoutNot(`^sort`, "unexpected sort") -} - func TestGoListCompiledCgo(t *testing.T) { tooSlow(t, "compiles cgo files") @@ -1506,15 +1457,17 @@ func main() { tg.setenv("PKG_CONFIG_PATH", tg.path(".")) tg.run("run", tg.path("foo.go")) - if runtime.GOOS != "darwin" { // darwin doesn't like these ldflags - // test for ldflags - tg.tempFile("bar.pc", ` + libs := `Libs: -Wl,-rpath=/path\ with\ spaces/bin` + if runtime.GOOS == "darwin" { + libs = "" // darwin linker doesn't have -rpath + } + // test for ldflags + tg.tempFile("bar.pc", ` Name: bar Description: The bar library Version: 1.0.0 -Libs: -Wl,-rpath=/path\ with\ spaces/bin +`+libs+` `) - } tg.tempFile("bar.go", `package main /* @@ -1526,40 +1479,6 @@ func main() {} tg.run("run", tg.path("bar.go")) } -func TestListTemplateContextFunction(t *testing.T) { - t.Parallel() - for _, tt := range []struct { - v string - want string - }{ - {"GOARCH", runtime.GOARCH}, - {"GOOS", runtime.GOOS}, - {"GOROOT", testGOROOT}, - {"GOPATH", os.Getenv("GOPATH")}, - {"CgoEnabled", ""}, - {"UseAllFiles", ""}, - {"Compiler", ""}, - {"BuildTags", ""}, - {"ReleaseTags", ""}, - {"InstallSuffix", ""}, - } { - tt := tt - t.Run(tt.v, func(t *testing.T) { - tg := testgo(t) - tg.parallel() - defer tg.cleanup() - tmpl := "{{context." + tt.v + "}}" - tg.run("list", "-f", tmpl) - if tt.want == "" { - return - } - if got := strings.TrimSpace(tg.getStdout()); got != tt.want { - t.Errorf("go list -f %q: got %q; want %q", tmpl, got, tt.want) - } - }) - } -} - // Test that you cannot use a local import in a package // accessed by a non-local import (found in a GOPATH/GOROOT). // See golang.org/issue/17475. @@ -2030,6 +1949,7 @@ func TestNeedVersion(t *testing.T) { func TestBuildmodePIE(t *testing.T) { tooSlow(t, "links binaries") + t.Parallel() if !platform.BuildModeSupported(runtime.Compiler, "pie", runtime.GOOS, runtime.GOARCH) { t.Skipf("skipping test because buildmode=pie is not supported on %s/%s", runtime.GOOS, runtime.GOARCH) @@ -2052,6 +1972,7 @@ func TestWindowsDefaultBuildmodIsPIE(t *testing.T) { t.Skip("skipping windows only test") } tooSlow(t, "links binaries") + t.Parallel() t.Run("non-cgo", func(t *testing.T) { testBuildmodePIE(t, false, false) @@ -2245,23 +2166,6 @@ func TestCacheCoverage(t *testing.T) { tg.run("test", "-cover", "-short", "math", "strings") } -func TestIssue22588(t *testing.T) { - // Don't get confused by stderr coming from tools. - tg := testgo(t) - defer tg.cleanup() - tg.parallel() - - tg.wantNotStale("runtime", "", "must be non-stale to compare staleness under -toolexec") - - if _, err := os.Stat("/usr/bin/time"); err != nil { - t.Skip(err) - } - - tg.run("list", "-f={{.Stale}}", "runtime") - tg.run("list", "-toolexec=/usr/bin/time", "-f={{.Stale}}", "runtime") - tg.grepStdout("false", "incorrectly reported runtime as stale") -} - func TestIssue22531(t *testing.T) { tooSlow(t, "links binaries") if gocacheverify.Value() == "1" { @@ -2750,24 +2654,3 @@ func TestCoverpkgTestOnly(t *testing.T) { tg.grepStderrNot("no packages being tested depend on matches", "bad match message") tg.grepStdout("coverage: 100", "no coverage") } - -// Regression test for golang.org/issue/34499: version command should not crash -// when executed in a deleted directory on Linux. -func TestExecInDeletedDir(t *testing.T) { - switch runtime.GOOS { - case "windows", "plan9", - "aix", // Fails with "device busy". - "solaris", "illumos": // Fails with "invalid argument". - t.Skipf("%v does not support removing the current working directory", runtime.GOOS) - } - tg := testgo(t) - defer tg.cleanup() - - tg.makeTempdir() - t.Chdir(tg.tempdir) - - tg.check(os.Remove(tg.tempdir)) - - // `go version` should not fail - tg.run("version") -} diff --git a/src/cmd/go/internal/auth/userauth.go b/src/cmd/go/internal/auth/userauth.go index 2649a9c271dce3..44c0b3cff0993d 100644 --- a/src/cmd/go/internal/auth/userauth.go +++ b/src/cmd/go/internal/auth/userauth.go @@ -48,7 +48,7 @@ func runAuthCommand(command string, url string, res *http.Response) (map[string] // parseUserAuth parses the output from a GOAUTH command and // returns a mapping of prefix → http.Header without the leading "https://" // or an error if the data does not follow the expected format. -// Returns an nil error and an empty map if the data is empty. +// Returns a nil error and an empty map if the data is empty. // See the expected format in 'go help goauth'. func parseUserAuth(data string) (map[string]http.Header, error) { credentials := make(map[string]http.Header) diff --git a/src/cmd/go/internal/base/base.go b/src/cmd/go/internal/base/base.go index d5d5f8d36e1133..236d18e420cbf9 100644 --- a/src/cmd/go/internal/base/base.go +++ b/src/cmd/go/internal/base/base.go @@ -175,6 +175,8 @@ func Fatal(err error) { var exitStatus = 0 var exitMu sync.Mutex +// SetExitStatus sets exit status to n if +// n is higher than the current exit status. func SetExitStatus(n int) { exitMu.Lock() if exitStatus < n { @@ -183,6 +185,7 @@ func SetExitStatus(n int) { exitMu.Unlock() } +// GetExitStatus reports the current exit status. func GetExitStatus() int { return exitStatus } diff --git a/src/cmd/go/internal/base/limit.go b/src/cmd/go/internal/base/limit.go index 4317432527a433..a90b700a031e3a 100644 --- a/src/cmd/go/internal/base/limit.go +++ b/src/cmd/go/internal/base/limit.go @@ -63,6 +63,12 @@ func AcquireNet() (release func(), err error) { <-netLimitSem } cleanup.Stop() + + // checker may be dead at the moment after we last access + // it in this function, so the cleanup can fire before Stop + // completes. Keep checker alive while we call Stop. See + // the documentation for runtime.Cleanup.Stop. + runtime.KeepAlive(checker) }, nil } diff --git a/src/cmd/go/internal/base/tool.go b/src/cmd/go/internal/base/tool.go index f2fc0ff7435f86..dc35ca26951b44 100644 --- a/src/cmd/go/internal/base/tool.go +++ b/src/cmd/go/internal/base/tool.go @@ -42,6 +42,9 @@ func ToolPath(toolName string) (string, error) { } func ValidToolName(toolName string) bool { + if toolName == "" { + return false + } for _, c := range toolName { switch { case 'a' <= c && c <= 'z', '0' <= c && c <= '9', c == '_': diff --git a/src/cmd/go/internal/bug/bug.go b/src/cmd/go/internal/bug/bug.go index 749edc51cf1d03..1e43e115510838 100644 --- a/src/cmd/go/internal/bug/bug.go +++ b/src/cmd/go/internal/bug/bug.go @@ -42,17 +42,17 @@ func init() { } func runBug(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() if len(args) > 0 { base.Fatalf("go: bug takes no arguments") } - work.BuildInit(moduleLoaderState) + work.BuildInit(moduleLoader) var buf strings.Builder buf.WriteString(bugHeader) printGoVersion(&buf) buf.WriteString("### Does this issue reproduce with the latest release?\n\n\n") - printEnvDetails(moduleLoaderState, &buf) + printEnvDetails(moduleLoader, &buf) buf.WriteString(bugFooter) body := buf.String() @@ -76,11 +76,11 @@ A link on go.dev/play is best. -### What did you expect to see? +### What did you see happen? -### What did you see instead? +### What did you expect to see? ` @@ -93,21 +93,21 @@ func printGoVersion(w io.Writer) { fmt.Fprintf(w, "\n") } -func printEnvDetails(loaderstate *modload.State, w io.Writer) { +func printEnvDetails(ld *modload.Loader, w io.Writer) { fmt.Fprintf(w, "### What operating system and processor architecture are you using (`go env`)?\n\n") fmt.Fprintf(w, "
    go env Output
    \n")
     	fmt.Fprintf(w, "$ go env\n")
    -	printGoEnv(loaderstate, w)
    +	printGoEnv(ld, w)
     	printGoDetails(w)
     	printOSDetails(w)
     	printCDetails(w)
     	fmt.Fprintf(w, "
    \n\n") } -func printGoEnv(loaderstate *modload.State, w io.Writer) { +func printGoEnv(ld *modload.Loader, w io.Writer) { env := envcmd.MkEnv() - env = append(env, envcmd.ExtraEnvVars(loaderstate)...) - env = append(env, envcmd.ExtraEnvVarsCostly(loaderstate)...) + env = append(env, envcmd.ExtraEnvVars(ld)...) + env = append(env, envcmd.ExtraEnvVarsCostly(ld)...) envcmd.PrintEnv(w, env, false) } @@ -184,14 +184,14 @@ func firstLine(buf []byte) []byte { // printGlibcVersion prints information about the glibc version. // It ignores failures. func printGlibcVersion(w io.Writer) { - tempdir := os.TempDir() - if tempdir == "" { + tempdir, err := os.MkdirTemp("", "") + if err != nil { return } src := []byte(`int main() {}`) srcfile := filepath.Join(tempdir, "go-bug.c") outfile := filepath.Join(tempdir, "go-bug") - err := os.WriteFile(srcfile, src, 0644) + err = os.WriteFile(srcfile, src, 0644) if err != nil { return } diff --git a/src/cmd/go/internal/cache/cache.go b/src/cmd/go/internal/cache/cache.go index 23cc531e697453..67f8202c06a55c 100644 --- a/src/cmd/go/internal/cache/cache.go +++ b/src/cmd/go/internal/cache/cache.go @@ -385,13 +385,42 @@ func (c *DiskCache) Trim() error { // trim time is too far in the future, attempt the trim anyway. It's possible that // the cache was full when the corruption happened. Attempting a trim on // an empty cache is cheap, so there wouldn't be a big performance hit in that case. - if data, err := lockedfile.Read(filepath.Join(c.dir, "trim.txt")); err == nil { + skipTrim := func(data []byte) bool { if t, err := strconv.ParseInt(strings.TrimSpace(string(data)), 10, 64); err == nil { lastTrim := time.Unix(t, 0) if d := now.Sub(lastTrim); d < trimInterval && d > -mtimeInterval { - return nil + return true } } + return false + } + // Check to see if we need a trim. Do this check separately from the lockedfile.Transform + // so that we can skip getting an exclusive lock in the common case. + if data, err := lockedfile.Read(filepath.Join(c.dir, "trim.txt")); err == nil { + if skipTrim(data) { + return nil + } + } + + errFileChanged := errors.New("file changed") + + // Write the new timestamp before we start trimming to reduce the chance that multiple invocations + // try to trim at the same time, causing contention in CI (#76314). + err := lockedfile.Transform(filepath.Join(c.dir, "trim.txt"), func(data []byte) ([]byte, error) { + if skipTrim(data) { + // The timestamp in the file no longer meets the criteria for us to + // do a trim. It must have been updated by another go command invocation + // since we last read it. Skip the trim. + return nil, errFileChanged + } + return fmt.Appendf(nil, "%d", now.Unix()), nil + }) + if errors.Is(err, errors.ErrUnsupported) { + return err + } + if errors.Is(err, errFileChanged) { + // Skip the trim because we don't need it anymore. + return nil } // Trim each of the 256 subdirectories. @@ -403,14 +432,6 @@ func (c *DiskCache) Trim() error { c.trimSubdir(subdir, cutoff) } - // Ignore errors from here: if we don't write the complete timestamp, the - // cache will appear older than it is, and we'll trim it again next time. - var b bytes.Buffer - fmt.Fprintf(&b, "%d", now.Unix()) - if err := lockedfile.Write(filepath.Join(c.dir, "trim.txt"), &b, 0o666); err != nil { - return err - } - return nil } diff --git a/src/cmd/go/internal/cache/hash.go b/src/cmd/go/internal/cache/hash.go index 4f79c315002449..27d275644a4bd0 100644 --- a/src/cmd/go/internal/cache/hash.go +++ b/src/cmd/go/internal/cache/hash.go @@ -51,6 +51,9 @@ func stripExperiment(version string) string { if i := strings.Index(version, " X:"); i >= 0 { return version[:i] } + if i := strings.Index(version, "-X:"); i >= 0 { + return version[:i] + } return version } diff --git a/src/cmd/go/internal/cache/prog.go b/src/cmd/go/internal/cache/prog.go index 74e9dc9de534e1..cbd495642cb9c5 100644 --- a/src/cmd/go/internal/cache/prog.go +++ b/src/cmd/go/internal/cache/prog.go @@ -204,6 +204,7 @@ func (c *ProgCache) send(ctx context.Context, req *cacheprog.Request) (*cachepro func (c *ProgCache) writeToChild(req *cacheprog.Request, resc chan<- *cacheprog.Response) (err error) { c.mu.Lock() if c.inFlight == nil { + c.mu.Unlock() return errCacheprogClosed } c.nextID++ @@ -240,7 +241,7 @@ func (c *ProgCache) writeToChild(req *cacheprog.Request, resc chan<- *cacheprog. return err } if err := e.Close(); err != nil { - return nil + return err } if wrote != req.BodySize { return fmt.Errorf("short write writing body to GOCACHEPROG for action %x, output %x: wrote %v; expected %v", diff --git a/src/cmd/go/internal/cacheprog/cacheprog.go b/src/cmd/go/internal/cacheprog/cacheprog.go index 9379636e5ab662..168df83b9d3f08 100644 --- a/src/cmd/go/internal/cacheprog/cacheprog.go +++ b/src/cmd/go/internal/cacheprog/cacheprog.go @@ -122,5 +122,7 @@ type Response struct { // DiskPath is the absolute path on disk of the body corresponding to a // "get" (on cache hit) or "put" request's ActionID. + // By convention, cached files are stored without any filename extensions. + // Some tools may filter out files with extensions. DiskPath string `json:",omitempty"` } diff --git a/src/cmd/go/internal/cfg/cfg.go b/src/cmd/go/internal/cfg/cfg.go index a4edd854f1d35a..78cbbb949e7c27 100644 --- a/src/cmd/go/internal/cfg/cfg.go +++ b/src/cmd/go/internal/cfg/cfg.go @@ -460,7 +460,7 @@ var ( GOROOTpkg string GOROOTsrc string - GOBIN = Getenv("GOBIN") + GOBIN, GOBINChanged = EnvOrAndChanged("GOBIN", "") GOCACHEPROG, GOCACHEPROGChanged = EnvOrAndChanged("GOCACHEPROG", "") GOMODCACHE, GOMODCACHEChanged = EnvOrAndChanged("GOMODCACHE", gopathDir("pkg/mod")) diff --git a/src/cmd/go/internal/clean/clean.go b/src/cmd/go/internal/clean/clean.go index ae744e13bc79b5..c2e3775c306e69 100644 --- a/src/cmd/go/internal/clean/clean.go +++ b/src/cmd/go/internal/clean/clean.go @@ -120,8 +120,8 @@ func init() { } func runClean(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() if len(args) > 0 { cacheFlag := "" switch { @@ -143,13 +143,13 @@ func runClean(ctx context.Context, cmd *base.Command, args []string) { // either the flags and arguments explicitly imply a package, // or no other target (such as a cache) was requested to be cleaned. cleanPkg := len(args) > 0 || cleanI || cleanR - if (!modload.Enabled(moduleLoaderState) || modload.HasModRoot(moduleLoaderState)) && + if (!moduleLoader.Enabled() || moduleLoader.HasModRoot()) && !cleanCache && !cleanModcache && !cleanTestcache && !cleanFuzzcache { cleanPkg = true } if cleanPkg { - for _, pkg := range load.PackagesAndErrors(moduleLoaderState, ctx, load.PackageOpts{}, args) { + for _, pkg := range load.PackagesAndErrors(moduleLoader, ctx, load.PackageOpts{}, args) { clean(pkg) } } @@ -272,13 +272,6 @@ func logFilesInGOMODCACHE() { var cleaned = map[*load.Package]bool{} -// TODO: These are dregs left by Makefile-based builds. -// Eventually, can stop deleting these. -var cleanDir = map[string]bool{ - "_test": true, - "_obj": true, -} - var cleanFile = map[string]bool{ "_testmain.go": true, "test.out": true, @@ -329,25 +322,21 @@ func clean(p *load.Package) { } _, elem := filepath.Split(p.Dir) - var allRemove []string + toRemove := map[string]bool{} // Remove dir-named executable only if this is package main. if p.Name == "main" { - allRemove = append(allRemove, - elem, - elem+".exe", - p.DefaultExecName(), - p.DefaultExecName()+".exe", - ) + toRemove[elem] = true + toRemove[elem+".exe"] = true + toRemove[p.DefaultExecName()] = true + toRemove[p.DefaultExecName()+".exe"] = true } // Remove package test executables. - allRemove = append(allRemove, - elem+".test", - elem+".test.exe", - p.DefaultExecName()+".test", - p.DefaultExecName()+".test.exe", - ) + toRemove[elem+".test"] = true + toRemove[elem+".test.exe"] = true + toRemove[p.DefaultExecName()+".test"] = true + toRemove[p.DefaultExecName()+".test.exe"] = true // Remove a potential executable, test executable for each .go file in the directory that // is not part of the directory's package. @@ -362,53 +351,31 @@ func clean(p *load.Package) { } if base, found := strings.CutSuffix(name, "_test.go"); found { - allRemove = append(allRemove, base+".test", base+".test.exe") + toRemove[base+".test"] = true + toRemove[base+".test.exe"] = true } if base, found := strings.CutSuffix(name, ".go"); found { // TODO(adg,rsc): check that this .go file is actually // in "package main", and therefore capable of building // to an executable file. - allRemove = append(allRemove, base, base+".exe") + toRemove[base] = true + toRemove[base+".exe"] = true } } - if cfg.BuildN || cfg.BuildX { - sh.ShowCmd(p.Dir, "rm -f %s", strings.Join(allRemove, " ")) - } - - toRemove := map[string]bool{} - for _, name := range allRemove { - toRemove[name] = true - } for _, dir := range dirs { name := dir.Name() if dir.IsDir() { - // TODO: Remove once Makefiles are forgotten. - if cleanDir[name] { - if err := sh.RemoveAll(filepath.Join(p.Dir, name)); err != nil { - base.Error(err) - } - } continue } - - if cfg.BuildN { - continue - } - if cleanFile[name] || cleanExt[filepath.Ext(name)] || toRemove[name] { - removeFile(filepath.Join(p.Dir, name)) + removeFile(sh, filepath.Join(p.Dir, name)) } } if cleanI && p.Target != "" { - if cfg.BuildN || cfg.BuildX { - sh.ShowCmd("", "rm -f %s", p.Target) - } - if !cfg.BuildN { - removeFile(p.Target) - } + removeFile(sh, p.Target) } if cleanR { @@ -420,7 +387,13 @@ func clean(p *load.Package) { // removeFile tries to remove file f, if error other than file doesn't exist // occurs, it will report the error. -func removeFile(f string) { +func removeFile(sh *work.Shell, f string) { + if cfg.BuildN || cfg.BuildX { + sh.ShowCmd("", "rm -f %s", f) + } + if cfg.BuildN { + return + } err := os.Remove(f) if err == nil || os.IsNotExist(err) { return diff --git a/src/cmd/go/internal/doc/dirs.go b/src/cmd/go/internal/doc/dirs.go index 5efd40b1d5a48b..3d0bf52f69c061 100644 --- a/src/cmd/go/internal/doc/dirs.go +++ b/src/cmd/go/internal/doc/dirs.go @@ -15,6 +15,9 @@ import ( "strings" "sync" + "cmd/go/internal/cfg" + "cmd/go/internal/modload" + "golang.org/x/mod/semver" ) @@ -41,29 +44,18 @@ var dirs Dirs // dirsInit starts the scanning of package directories in GOROOT and GOPATH. Any // extra paths passed to it are included in the channel. func dirsInit(extra ...Dir) { - if buildCtx.GOROOT == "" { - stdout, err := exec.Command("go", "env", "GOROOT").Output() - if err != nil { - if ee, ok := err.(*exec.ExitError); ok && len(ee.Stderr) > 0 { - log.Fatalf("failed to determine GOROOT: $GOROOT is not set and 'go env GOROOT' failed:\n%s", ee.Stderr) - } - log.Fatalf("failed to determine GOROOT: $GOROOT is not set and could not run 'go env GOROOT':\n\t%s", err) - } - buildCtx.GOROOT = string(bytes.TrimSpace(stdout)) - } - dirs.hist = make([]Dir, 0, 1000) dirs.hist = append(dirs.hist, extra...) dirs.scan = make(chan Dir) go dirs.walk(codeRoots()) } -// goCmd returns the "go" command path corresponding to buildCtx.GOROOT. +// goCmd returns the "go" command path corresponding to cfg.GOROOT. func goCmd() string { - if buildCtx.GOROOT == "" { + if cfg.GOROOT == "" { return "go" } - return filepath.Join(buildCtx.GOROOT, "bin", "go") + return filepath.Join(cfg.GOROOT, "bin", "go") } // Reset puts the scan back at the beginning. @@ -187,30 +179,32 @@ var usingModules bool func findCodeRoots() []Dir { var list []Dir if !testGOPATH { - // Check for use of modules by 'go env GOMOD', - // which reports a go.mod file path if modules are enabled. - stdout, _ := exec.Command(goCmd(), "env", "GOMOD").Output() - gomod := string(bytes.TrimSpace(stdout)) - - usingModules = len(gomod) > 0 - if usingModules && buildCtx.GOROOT != "" { - list = append(list, - Dir{dir: filepath.Join(buildCtx.GOROOT, "src"), inModule: true}, - Dir{importPath: "cmd", dir: filepath.Join(buildCtx.GOROOT, "src", "cmd"), inModule: true}) - } + // TODO: use the same state used to load the package. + // For now it's okay to use a new state because we're just + // using it to determine whether we're in module mode. But + // it would be good to avoid an extra run of modload.Init. + if state := modload.NewLoader(); state.WillBeEnabled() { + usingModules = state.HasModRoot() + + if cfg.GOROOT != "" { + list = append(list, + Dir{dir: filepath.Join(cfg.GOROOT, "src"), inModule: usingModules}, + Dir{importPath: "cmd", dir: filepath.Join(cfg.GOROOT, "src", "cmd"), inModule: usingModules}) + } - if gomod == os.DevNull { - // Modules are enabled, but the working directory is outside any module. - // We can still access std, cmd, and packages specified as source files - // on the command line, but there are no module roots. - // Avoid 'go list -m all' below, since it will not work. - return list + if !usingModules { + // Modules are enabled, but the working directory is outside any module. + // We can still access std, cmd, and packages specified as source files + // on the command line, but there are no module roots. + // Avoid 'go list -m all' below, since it will not work. + return list + } } } if !usingModules { - if buildCtx.GOROOT != "" { - list = append(list, Dir{dir: filepath.Join(buildCtx.GOROOT, "src")}) + if cfg.GOROOT != "" { + list = append(list, Dir{dir: filepath.Join(cfg.GOROOT, "src")}) } for _, root := range splitGopath() { list = append(list, Dir{dir: filepath.Join(root, "src")}) diff --git a/src/cmd/go/internal/doc/doc.go b/src/cmd/go/internal/doc/doc.go index fceeaf101efd62..68306867a6dd6f 100644 --- a/src/cmd/go/internal/doc/doc.go +++ b/src/cmd/go/internal/doc/doc.go @@ -21,6 +21,10 @@ import ( "strings" "cmd/go/internal/base" + "cmd/go/internal/cfg" + "cmd/go/internal/load" + "cmd/go/internal/modload" + "cmd/go/internal/search" "cmd/internal/telemetry/counter" ) @@ -129,10 +133,13 @@ Flags: Treat a command (package main) like a regular package. Otherwise package main's exported symbols are hidden when showing the package's top-level documentation. + -ex + Include executable examples. -http Serve HTML docs over HTTP. -short - One-line representation for each symbol. + One-line representation for each symbol. Cannot be + combined with -all. -src Show the full source code for the symbol. This will display the full Go source of its declaration and @@ -151,7 +158,7 @@ func runDoc(ctx context.Context, cmd *base.Command, args []string) { log.SetPrefix("doc: ") dirsInit() var flagSet flag.FlagSet - err := do(os.Stdout, &flagSet, args) + err := do(ctx, os.Stdout, &flagSet, args) if err != nil { log.Fatal(err) } @@ -163,6 +170,7 @@ var ( chdir string // -C flag showAll bool // -all flag showCmd bool // -cmd flag + showEx bool // -ex flag showSrc bool // -src flag short bool // -short flag serveHTTP bool // -http flag @@ -179,13 +187,11 @@ func usage(flagSet *flag.FlagSet) { fmt.Fprintf(os.Stderr, "\tgo doc [.]\n") fmt.Fprintf(os.Stderr, "For more information run\n") fmt.Fprintf(os.Stderr, "\tgo help doc\n\n") - fmt.Fprintf(os.Stderr, "Flags:\n") - flagSet.PrintDefaults() os.Exit(2) } // do is the workhorse, broken out of runDoc to make testing easier. -func do(writer io.Writer, flagSet *flag.FlagSet, args []string) (err error) { +func do(ctx context.Context, writer io.Writer, flagSet *flag.FlagSet, args []string) (err error) { flagSet.Usage = func() { usage(flagSet) } unexported = false matchCase = false @@ -193,17 +199,21 @@ func do(writer io.Writer, flagSet *flag.FlagSet, args []string) (err error) { flagSet.BoolVar(&unexported, "u", false, "show unexported symbols as well as exported") flagSet.BoolVar(&matchCase, "c", false, "symbol matching honors case (paths not affected)") flagSet.BoolVar(&showAll, "all", false, "show all documentation for package") + flagSet.BoolVar(&showEx, "ex", false, "show executable examples for symbol or package") flagSet.BoolVar(&showCmd, "cmd", false, "show symbols with package docs even if package is a command") flagSet.BoolVar(&showSrc, "src", false, "show source code for symbol") flagSet.BoolVar(&short, "short", false, "one-line representation for each symbol") flagSet.BoolVar(&serveHTTP, "http", false, "serve HTML docs over HTTP") flagSet.Parse(args) - counter.CountFlags("doc/flag:", *flag.CommandLine) + counter.CountFlags("doc/flag:", *flagSet) if chdir != "" { if err := os.Chdir(chdir); err != nil { return err } } + if showAll && short { + return fmt.Errorf("cannot combine -all and -short") + } if serveHTTP { // Special case: if there are no arguments, try to go to an appropriate page // depending on whether we're in a module or workspace. The pkgsite homepage @@ -212,16 +222,16 @@ func do(writer io.Writer, flagSet *flag.FlagSet, args []string) (err error) { mod, err := runCmd(append(os.Environ(), "GOWORK=off"), "go", "list", "-m") if err == nil && mod != "" && mod != "command-line-arguments" { // If there's a module, go to the module's doc page. - return doPkgsite(mod, "") + return doPkgsite(ctx, mod, "") } gowork, err := runCmd(nil, "go", "env", "GOWORK") if err == nil && gowork != "" { // Outside a module, but in a workspace, go to the home page // with links to each of the modules' pages. - return doPkgsite("", "") + return doPkgsite(ctx, "", "") } // Outside a module or workspace, go to the documentation for the standard library. - return doPkgsite("std", "") + return doPkgsite(ctx, "std", "") } // If args are provided, we need to figure out which page to open on the pkgsite @@ -234,7 +244,7 @@ func do(writer io.Writer, flagSet *flag.FlagSet, args []string) (err error) { // Loop until something is printed. dirs.Reset() for i := 0; ; i++ { - buildPackage, userPath, sym, more := parseArgs(flagSet, flagSet.Args()) + buildPackage, userPath, sym, more := parseArgs(ctx, flagSet, flagSet.Args()) if i > 0 && !more { // Ignore the "more" bit on the first iteration. return failMessage(paths, symbol, method) } @@ -286,7 +296,7 @@ func do(writer io.Writer, flagSet *flag.FlagSet, args []string) (err error) { if err != nil { return err } - return doPkgsite(path, fragment) + return doPkgsite(ctx, path, fragment) } return nil } @@ -356,22 +366,54 @@ func failMessage(paths []string, symbol, method string) error { // and there may be more matches. For example, if the argument // is rand.Float64, we must scan both crypto/rand and math/rand // to find the symbol, and the first call will return crypto/rand, true. -func parseArgs(flagSet *flag.FlagSet, args []string) (pkg *build.Package, path, symbol string, more bool) { +func parseArgs(ctx context.Context, flagSet *flag.FlagSet, args []string) (pkg *load.Package, path, symbol string, more bool) { wd, err := os.Getwd() if err != nil { log.Fatal(err) } + loader := modload.NewLoader() + if testGOPATH { + loader = modload.NewDisabledState() + } + if len(args) > 0 && strings.Index(args[0], "@") >= 0 { + // Version query: force no root + loader.ForceUseModules = true + loader.RootMode = modload.NoRoot + modload.Init(loader) + } else if loader.WillBeEnabled() { + loader.InitWorkfile() + modload.Init(loader) + modload.LoadModFile(loader, context.TODO()) + } + if len(args) == 0 { // Easy: current directory. - return importDir(wd), "", "", false + return mustLoadPackage(ctx, loader, wd), "", "", false } arg := args[0] + + var version string + if i := strings.Index(arg, "@"); i >= 0 { + arg, version = arg[:i], arg[i+1:] + } + // We have an argument. If it is a directory name beginning with . or .., // use the absolute path name. This discriminates "./errors" from "errors" // if the current directory contains a non-standard errors package. if isDotSlash(arg) { arg = filepath.Join(wd, arg) } + if version != "" && (build.IsLocalImport(filepath.ToSlash(arg)) || filepath.IsAbs(arg)) { + log.Fatal("cannot use @version with local or absolute paths") + } + + importPkg := func(p string) (*load.Package, error) { + if version != "" { + return loadVersioned(ctx, loader, p, version) + } + return loadPackage(ctx, loader, p) + } + switch len(args) { default: usage(flagSet) @@ -379,20 +421,20 @@ func parseArgs(flagSet *flag.FlagSet, args []string) (pkg *build.Package, path, // Done below. case 2: // Package must be findable and importable. - pkg, err := build.Import(args[0], wd, build.ImportComment) + pkg, err := importPkg(arg) if err == nil { - return pkg, args[0], args[1], false + return pkg, arg, args[1], false } - for { - packagePath, ok := findNextPackage(arg) - if !ok { - break - } - if pkg, err := build.ImportDir(packagePath, build.ImportComment); err == nil { - return pkg, arg, args[1], true - } + if p, findErr, ok := findPackage(arg, importPkg); ok { + pkg = p + return pkg, arg, args[1], true + } else if findErr != nil { + err = findErr + } + if version != "" { + log.Fatal(err) } - return nil, args[0], args[1], false + return nil, arg, args[1], false } // Usual case: one argument. // If it contains slashes, it begins with either a package path @@ -402,12 +444,12 @@ func parseArgs(flagSet *flag.FlagSet, args []string) (pkg *build.Package, path, // package paths as their prefix. var importErr error if filepath.IsAbs(arg) { - pkg, importErr = build.ImportDir(arg, build.ImportComment) + pkg, importErr = loadPackage(ctx, loader, arg) if importErr == nil { return pkg, arg, "", false } } else { - pkg, importErr = build.Import(arg, wd, build.ImportComment) + pkg, importErr = importPkg(arg) if importErr == nil { return pkg, arg, "", false } @@ -417,7 +459,7 @@ func parseArgs(flagSet *flag.FlagSet, args []string) (pkg *build.Package, path, // Kills the problem caused by case-insensitive file systems // matching an upper case name as a package name. if !strings.ContainsAny(arg, `/\`) && token.IsExported(arg) { - pkg, err := build.ImportDir(".", build.ImportComment) + pkg, err := loadPackage(ctx, loader, ".") if err == nil { return pkg, "", arg, false } @@ -443,24 +485,39 @@ func parseArgs(flagSet *flag.FlagSet, args []string) (pkg *build.Package, path, symbol = arg[period+1:] } // Have we identified a package already? - pkg, err := build.Import(arg[0:period], wd, build.ImportComment) + pkg, err := loadPackage(ctx, loader, arg[0:period]) if err == nil { return pkg, arg[0:period], symbol, false } // See if we have the basename or tail of a package, as in json for encoding/json // or ivy/value for robpike.io/ivy/value. pkgName := arg[:period] - for { - path, ok := findNextPackage(pkgName) - if !ok { - break + if pkg, _, ok := findPackage(pkgName, importPkg); ok { + return pkg, arg[0:period], symbol, true + } + dirs.Reset() // Next iteration of for loop must scan all the directories again. + } + + // Try inference from $PATH before giving up. + if slash < 0 && !isDotSlash(arg) && !filepath.IsAbs(arg) { + if pkgPath, v, ok := inferVersion(arg); ok { + if version == "" { + version = v } - if pkg, err = build.ImportDir(path, build.ImportComment); err == nil { - return pkg, arg[0:period], symbol, true + pkg, err := loadVersioned(ctx, loader, pkgPath, version) + if err == nil { + return pkg, pkgPath, "", false } } - dirs.Reset() // Next iteration of for loop must scan all the directories again. } + + if version != "" { + if importErr != nil { + log.Fatal(importErr) + } + log.Fatalf("no such package %q at version %q", arg, version) + } + // If it has a slash, we've failed. if slash >= 0 { // build.Import should always include the path in its error message, @@ -477,7 +534,114 @@ func parseArgs(flagSet *flag.FlagSet, args []string) (pkg *build.Package, path, } } // Guess it's a symbol in the current directory. - return importDir(wd), "", arg, false + return mustLoadPackage(ctx, loader, wd), "", arg, false +} + +// findPackage returns the first successfully imported package matching the query pkg. +// It updates dirs.offset to the candidate's nextOffset so that subsequent searches +// work across retry loops. +// +// (pkg, nil, true) => imported a package +// (nil, err, false) => all imports failed (along with last error) +// (nil, nil, false) => no matching packages +func findPackage(pkg string, importPkg func(string) (*load.Package, error)) (*load.Package, error, bool) { + var lastErr error + for _, m := range matchingPackages(pkg) { + p, err := importPkg(m.importPath) + if err == nil { + dirs.offset = m.nextOffset + return p, nil, true + } + lastErr = err + } + return nil, lastErr, false +} + +type packageMatch struct { + importPath string + nextOffset int +} + +func matchingPackages(pkg string) []packageMatch { + // TODO(adonovan): once go1.28 tree opens, refactor matchingPackages to use + // iter.Seq[string] to encapsulate iteration state and avoid global vars. + if filepath.IsAbs(pkg) { + if dirs.offset == 0 { + dirs.offset = -1 + return []packageMatch{{importPath: pkg, nextOffset: -1}} + } + return nil + } + if pkg == "" || token.IsExported(pkg) { // Upper case symbol cannot be a package name. + return nil + } + pkg = path.Clean(pkg) + pkgSuffix := "/" + pkg + deferInternal := !hasPathElement(pkg, "internal") + // Prefer non-internal packages unless pkg is itself internal. + // Scanning directories is cheap compared to loading packages, so + // collect all matches and sort internal matches to the end. + var matches []packageMatch + var nonInternal []packageMatch + var internal []packageMatch + for { + d, ok := dirs.Next() + if !ok { + break + } + if d.importPath != pkg && !strings.HasSuffix(d.importPath, pkgSuffix) { + continue + } + m := packageMatch{importPath: d.importPath, nextOffset: dirs.offset} + if !deferInternal { + matches = append(matches, m) + } else if hasPathElement(d.importPath, "internal") { + internal = append(internal, m) + } else { + nonInternal = append(nonInternal, m) + } + } + if !deferInternal { + return matches + } + if len(nonInternal) == 0 { + return internal + } + // If the last non-internal match is returned, later retries should + // not fall through to internal-only matches for the same package path. + nonInternal[len(nonInternal)-1].nextOffset = dirs.offset + return append(nonInternal, internal...) +} + +func loadPackage(ctx context.Context, loader *modload.Loader, pattern string) (*load.Package, error) { + if !search.NewMatch(pattern).IsLiteral() { + return nil, fmt.Errorf("pattern %q does not specify a single package", pattern) + } + + pkgOpts := load.PackageOpts{ + IgnoreImports: true, + SuppressBuildInfo: true, + SuppressEmbedFiles: true, + } + pkgs := load.PackagesAndErrors(loader, ctx, pkgOpts, []string{pattern}) + + if len(pkgs) != 1 { + return nil, fmt.Errorf("path %q matched multiple packages", pattern) + } + + p := pkgs[0] + if p.Error != nil { + return nil, p.Error + } + return p, nil +} + +func mustLoadPackage(ctx context.Context, loader *modload.Loader, dir string) *load.Package { + pkg, err := loadPackage(ctx, loader, dir) + if err != nil { + log.Fatal(err) + } + return pkg } // dotPaths lists all the dotted paths legal on Unix-like and @@ -505,15 +669,6 @@ func isDotSlash(arg string) bool { return false } -// importDir is just an error-catching wrapper for build.ImportDir. -func importDir(dir string) *build.Package { - pkg, err := build.ImportDir(dir, build.ImportComment) - if err != nil { - log.Fatal(err) - } - return pkg -} - // parseSymbol breaks str apart into a symbol and method. // Both may be missing or the method may be missing. // If present, each must be a valid Go identifier. @@ -541,35 +696,16 @@ func isExported(name string) bool { return unexported || token.IsExported(name) } -// findNextPackage returns the next full file name path that matches the -// (perhaps partial) package path pkg. The boolean reports if any match was found. -func findNextPackage(pkg string) (string, bool) { - if filepath.IsAbs(pkg) { - if dirs.offset == 0 { - dirs.offset = -1 - return pkg, true - } - return "", false - } - if pkg == "" || token.IsExported(pkg) { // Upper case symbol cannot be a package name. - return "", false - } - pkg = path.Clean(pkg) - pkgSuffix := "/" + pkg - for { - d, ok := dirs.Next() - if !ok { - return "", false - } - if d.importPath == pkg || strings.HasSuffix(d.importPath, pkgSuffix) { - return d.dir, true +func hasPathElement(p, elem string) bool { + for part := range strings.SplitSeq(path.Clean(p), "/") { + if part == elem { + return true } } + return false } -var buildCtx = build.Default - // splitGopath splits $GOPATH into a list of roots. func splitGopath() []string { - return filepath.SplitList(buildCtx.GOPATH) + return filepath.SplitList(cfg.BuildContext.GOPATH) } diff --git a/src/cmd/go/internal/doc/doc_test.go b/src/cmd/go/internal/doc/doc_test.go index f91dcd658f247b..2feac69080a87c 100644 --- a/src/cmd/go/internal/doc/doc_test.go +++ b/src/cmd/go/internal/doc/doc_test.go @@ -7,7 +7,6 @@ package doc import ( "bytes" "flag" - "go/build" "internal/testenv" "log" "os" @@ -16,18 +15,19 @@ import ( "runtime" "strings" "testing" + + "cmd/go/internal/cfg" ) func TestMain(m *testing.M) { // Clear GOPATH so we don't access the user's own packages in the test. - buildCtx.GOPATH = "" + cfg.BuildContext.GOPATH = "" testGOPATH = true // force GOPATH mode; module test is in cmd/go/testdata/script/mod_doc.txt // Set GOROOT in case runtime.GOROOT is wrong (for example, if the test was // built with -trimpath). dirsInit would identify it using 'go env GOROOT', // but we can't be sure that the 'go' in $PATH is the right one either. - buildCtx.GOROOT = testenv.GOROOT(nil) - build.Default.GOROOT = testenv.GOROOT(nil) + cfg.GOROOT = testenv.GOROOT(nil) // Add $GOROOT/src/cmd/go/internal/doc/testdata explicitly so we can access its contents in the test. // Normally testdata directories are ignored, but sending it to dirs.scan directly is @@ -37,9 +37,9 @@ func TestMain(m *testing.M) { panic(err) } dirsInit( - Dir{importPath: "testdata", dir: testdataDir}, - Dir{importPath: "testdata/nested", dir: filepath.Join(testdataDir, "nested")}, - Dir{importPath: "testdata/nested/nested", dir: filepath.Join(testdataDir, "nested", "nested")}) + Dir{importPath: "cmd/go/internal/doc/testdata", dir: testdataDir}, + Dir{importPath: "cmd/go/internal/doc/testdata/nested", dir: filepath.Join(testdataDir, "nested")}, + Dir{importPath: "cmd/go/internal/doc/testdata/nested/nested", dir: filepath.Join(testdataDir, "nested", "nested")}) os.Exit(m.Run()) } @@ -629,6 +629,35 @@ var tests = []test{ `Has unexported methods`, }, }, + // Interface with comparable constraint. + { + "interface type with comparable", + []string{p, `ExportedComparableInterface`}, + []string{ + `Comment about exported interface with comparable`, // Include comment. + `type ExportedComparableInterface interface`, // Interface definition. + `comparable.*Comment on line with comparable`, // Comparable should be shown. + `ExportedMethod\(\).*Comment on line with exported method`, + `Has unexported methods`, + }, + []string{ + `unexportedMethod`, // No unexported method. + }, + }, + // Interface with only comparable (no unexported methods). + { + "interface type with comparable only", + []string{p, `ExportedComparableOnlyInterface`}, + []string{ + `ExportedComparableOnlyInterface has only comparable`, // Include comment. + `type ExportedComparableOnlyInterface interface`, // Interface definition. + `comparable.*Comment on line with comparable`, // Comparable should be shown. + `ExportedMethod\(\).*Comment on line with exported method`, + }, + []string{ + `Has unexported methods`, // Should NOT appear - no unexported methods. + }, + }, // Interface method. { @@ -721,6 +750,143 @@ var tests = []test{ []string{`other fields elided`}, }, + // Package with -ex. + { + "package with -ex", + []string{`-ex`, p}, + []string{ + `func ExampleExportedFunc\(\)`, + `func ExampleExportedType\(\)`, + `func Example\(\)`, + `func Example_multiline\(\)`, + `func Example_playable\(\)`, + }, + nil, + }, + + // Type with -ex. + { + "type with -ex", + []string{`-ex`, p, `ExportedType`}, + []string{ + `func ExampleExportedType\(\)`, + `func ExampleExportedType_ExportedMethod\(\)`, + }, + nil, + }, + + // Function with -ex. + { + "function with -ex", + []string{`-ex`, p, `ExportedFunc`}, + []string{ + `func ExampleExportedFunc\(\)`, + `Function example.`, + `func ExampleExportedFunc_two\(\)`, + `Function example two.`, + }, + nil, + }, + + // Method with -ex. + { + "method with -ex", + []string{`-ex`, p, `ExportedType.ExportedMethod`}, + []string{ + `func ExampleExportedType_ExportedMethod\(\)`, + `Method example.`, + }, + nil, + }, + + // Package example. + { + "package example", + []string{p, `Example`}, + []string{ + `fmt.Println\("Package example output"\)`, + `Output: Package example output`, + }, + []string{`func Example\(\)`}, + }, + + // Multiline output example. + { + "multiline output example", + []string{p, `Example_multiline`}, + []string{ + `fmt.Println\("Multiline\\nexample\\noutput"\)`, + "Output: \nMultiline\nexample\noutput", + }, + []string{`Output: Multiline example output`}, + }, + + // Type example. + { + "type example", + []string{p, `ExampleExportedType`}, + []string{ + `fmt.Println\("Type example output"\)`, + `Output: Type example output`, + }, + []string{`func ExampleExportedType\(\)`}, + }, + + // Function example. + { + "function example", + []string{p, `ExampleExportedFunc`}, + []string{ + `fmt.Println\("Function example output"\)`, + `Output: Function example output`, + }, + []string{ + `func ExampleExportedFunc\(\)`, + `fmt.Println\("Function example two output"\)`, + `Output: Function example two output`, + }, + }, + + // Function example two. + { + "function example", + []string{p, `ExampleExportedFunc_two`}, + []string{ + `fmt.Println\("Function example two output"\)`, + `Output: Function example two output`, + }, + []string{ + `func ExampleExportedFunc_two\(\)`, + `fmt.Println\("Function example output"\)`, + `Output: Function example output`, + }, + }, + + // Method example. + { + "method example", + []string{p, `ExampleExportedType_ExportedMethod`}, + []string{ + `fmt.Println\("Method example output"\)`, + `Output: Method example output`, + }, + []string{`func ExampleExportedType_ExportedMethod\(\)`}, + }, + + // Playable example. + { + "playable example", + []string{p, `Example_playable`}, + []string{ + `package main`, + `func main\(\) {`, + `fmt.Println\("Playable example output"\)`, + `}`, + `Output: Playable example output`, + }, + []string{`func Example_playable\(\)`}, + }, + // Case matching off. { "case matching off", @@ -881,7 +1047,7 @@ func TestDoc(t *testing.T) { var flagSet flag.FlagSet var logbuf bytes.Buffer log.SetOutput(&logbuf) - err := do(&b, &flagSet, test.args) + err := do(t.Context(), &b, &flagSet, test.args) if err != nil { t.Fatalf("%s %v: %s\n", test.name, test.args, err) } @@ -934,7 +1100,7 @@ func TestMultiplePackages(t *testing.T) { // Make sure crypto/rand does not have the symbol. { var flagSet flag.FlagSet - err := do(&b, &flagSet, []string{"crypto/rand.float64"}) + err := do(t.Context(), &b, &flagSet, []string{"crypto/rand.float64"}) if err == nil { t.Errorf("expected error from crypto/rand.float64") } else if !strings.Contains(err.Error(), "no symbol float64") { @@ -944,7 +1110,7 @@ func TestMultiplePackages(t *testing.T) { // Make sure math/rand does have the symbol. { var flagSet flag.FlagSet - err := do(&b, &flagSet, []string{"math/rand.float64"}) + err := do(t.Context(), &b, &flagSet, []string{"math/rand.float64"}) if err != nil { t.Errorf("unexpected error %q from math/rand.float64", err) } @@ -952,7 +1118,7 @@ func TestMultiplePackages(t *testing.T) { // Try the shorthand. { var flagSet flag.FlagSet - err := do(&b, &flagSet, []string{"rand.float64"}) + err := do(t.Context(), &b, &flagSet, []string{"rand.float64"}) if err != nil { t.Errorf("unexpected error %q from rand.float64", err) } @@ -960,7 +1126,7 @@ func TestMultiplePackages(t *testing.T) { // Now try a missing symbol. We should see both packages in the error. { var flagSet flag.FlagSet - err := do(&b, &flagSet, []string{"rand.doesnotexit"}) + err := do(t.Context(), &b, &flagSet, []string{"rand.doesnotexit"}) if err == nil { t.Errorf("expected error from rand.doesnotexit") } else { @@ -978,6 +1144,40 @@ func TestMultiplePackages(t *testing.T) { } } +func TestInternalPackagesArePreferredLast(t *testing.T) { + if testing.Short() { + t.Skip("scanning file system takes too long") + } + maybeSkip(t) + var b bytes.Buffer + var flagSet flag.FlagSet + err := do(t.Context(), &b, &flagSet, []string{"synctest.Wait"}) + if err != nil { + t.Fatalf("unexpected error from synctest.Wait: %v", err) + } + out := b.String() + if !strings.Contains(out, `package synctest // import "testing/synctest"`) { + t.Fatalf("synctest.Wait resolved to wrong package:\n%s", out) + } + if strings.Contains(out, `internal/synctest`) { + t.Fatalf("synctest.Wait resolved to internal package:\n%s", out) + } + + b.Reset() + flagSet = flag.FlagSet{} + err = do(t.Context(), &b, &flagSet, []string{"synctest.DoesNotExist"}) + if err == nil { + t.Fatal("expected error from synctest.DoesNotExist") + } + errStr := err.Error() + if !strings.Contains(errStr, "testing/synctest") { + t.Fatalf("error %q should contain testing/synctest", errStr) + } + if strings.Contains(errStr, "internal/synctest") { + t.Fatalf("error %q should not contain internal/synctest", errStr) + } +} + // Test the code to look up packages when given two args. First test case is // // go doc binary BigEndian @@ -998,21 +1198,21 @@ func TestTwoArgLookup(t *testing.T) { var b bytes.Buffer // We don't care about the output. { var flagSet flag.FlagSet - err := do(&b, &flagSet, []string{"binary", "BigEndian"}) + err := do(t.Context(), &b, &flagSet, []string{"binary", "BigEndian"}) if err != nil { t.Errorf("unexpected error %q from binary BigEndian", err) } } { var flagSet flag.FlagSet - err := do(&b, &flagSet, []string{"rand", "Float64"}) + err := do(t.Context(), &b, &flagSet, []string{"rand", "Float64"}) if err != nil { t.Errorf("unexpected error %q from rand Float64", err) } } { var flagSet flag.FlagSet - err := do(&b, &flagSet, []string{"bytes", "Foo"}) + err := do(t.Context(), &b, &flagSet, []string{"bytes", "Foo"}) if err == nil { t.Errorf("expected error from bytes Foo") } else if !strings.Contains(err.Error(), "no symbol Foo") { @@ -1021,7 +1221,7 @@ func TestTwoArgLookup(t *testing.T) { } { var flagSet flag.FlagSet - err := do(&b, &flagSet, []string{"nosuchpackage", "Foo"}) + err := do(t.Context(), &b, &flagSet, []string{"nosuchpackage", "Foo"}) if err == nil { // actually present in the user's filesystem } else if !strings.Contains(err.Error(), "no such package") { @@ -1038,11 +1238,11 @@ func TestDotSlashLookup(t *testing.T) { t.Skip("scanning file system takes too long") } maybeSkip(t) - t.Chdir(filepath.Join(buildCtx.GOROOT, "src", "text")) + t.Chdir(filepath.Join(cfg.GOROOT, "src", "text")) var b strings.Builder var flagSet flag.FlagSet - err := do(&b, &flagSet, []string{"./template"}) + err := do(t.Context(), &b, &flagSet, []string{"./template"}) if err != nil { t.Errorf("unexpected error %q from ./template", err) } @@ -1060,7 +1260,7 @@ func TestNoPackageClauseWhenNoMatch(t *testing.T) { maybeSkip(t) var b strings.Builder var flagSet flag.FlagSet - err := do(&b, &flagSet, []string{"template.ZZZ"}) + err := do(t.Context(), &b, &flagSet, []string{"template.ZZZ"}) // Expect an error. if err == nil { t.Error("expect an error for template.zzz") diff --git a/src/cmd/go/internal/doc/mod.go b/src/cmd/go/internal/doc/mod.go new file mode 100644 index 00000000000000..adf6e6048548b0 --- /dev/null +++ b/src/cmd/go/internal/doc/mod.go @@ -0,0 +1,48 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package doc + +import ( + "context" + "debug/buildinfo" + "fmt" + "os/exec" + + "cmd/go/internal/load" + "cmd/go/internal/modload" +) + +// loadVersioned loads a package at a specific version. +func loadVersioned(ctx context.Context, loader *modload.Loader, pkgPath, version string) (*load.Package, error) { + var opts load.PackageOpts + args := []string{ + fmt.Sprintf("%s@%s", pkgPath, version), + } + pkgs, err := load.PackagesAndErrorsOutsideModule(loader, ctx, opts, args) + if err != nil { + return nil, err + } + if len(pkgs) != 1 { + return nil, fmt.Errorf("incorrect number of packages: want 1, got %d", len(pkgs)) + } + return pkgs[0], nil +} + +// inferVersion checks if the argument matches a command on $PATH and returns its module path and version. +func inferVersion(arg string) (pkgPath, version string, ok bool) { + path, err := exec.LookPath(arg) + if err != nil { + return "", "", false + } + bi, err := buildinfo.ReadFile(path) + if err != nil { + return "", "", false + } + if bi.Main.Path == "" || bi.Main.Version == "" { + return "", "", false + } + // bi.Path is the package path for the main package. + return bi.Path, bi.Main.Version, true +} diff --git a/src/cmd/go/internal/doc/pkg.go b/src/cmd/go/internal/doc/pkg.go index 7b5e00365d04a1..e35ad38ebc6d38 100644 --- a/src/cmd/go/internal/doc/pkg.go +++ b/src/cmd/go/internal/doc/pkg.go @@ -9,7 +9,6 @@ import ( "bytes" "fmt" "go/ast" - "go/build" "go/doc" "go/format" "go/parser" @@ -22,6 +21,9 @@ import ( "strings" "unicode" "unicode/utf8" + + "cmd/go/internal/cfg" + "cmd/go/internal/load" ) const ( @@ -36,7 +38,7 @@ type Package struct { pkg *ast.Package // Parsed package. file *ast.File // Merged from all files in the package doc *doc.Package - build *build.Package + build *load.Package typedValue map[*doc.Value]bool // Consts and vars related to types. constructor map[*doc.Func]bool // Constructors. fs *token.FileSet // Needed for printing. @@ -96,8 +98,8 @@ func (pkg *Package) prettyPath() string { // Also convert everything to slash-separated paths for uniform handling. path = filepath.Clean(filepath.ToSlash(pkg.build.Dir)) // Can we find a decent prefix? - if buildCtx.GOROOT != "" { - goroot := filepath.Join(buildCtx.GOROOT, "src") + if cfg.GOROOT != "" { + goroot := filepath.Join(cfg.GOROOT, "src") if p, ok := trim(path, filepath.ToSlash(goroot)); ok { return p } @@ -137,19 +139,18 @@ func (pkg *Package) Fatalf(format string, args ...any) { // parsePackage turns the build package we found into a parsed package // we can then use to generate documentation. -func parsePackage(writer io.Writer, pkg *build.Package, userPath string) *Package { +func parsePackage(writer io.Writer, pkg *load.Package, userPath string) *Package { // include tells parser.ParseDir which files to include. - // That means the file must be in the build package's GoFiles or CgoFiles - // list only (no tag-ignored files, tests, swig or other non-Go files). + // That means the file must be in the build package's GoFiles, CgoFiles, + // TestGoFiles or XTestGoFiles list only (no tag-ignored files, swig or + // other non-Go files). include := func(info fs.FileInfo) bool { - for _, name := range pkg.GoFiles { - if name == info.Name() { - return true - } - } - for _, name := range pkg.CgoFiles { - if name == info.Name() { - return true + files := [][]string{pkg.GoFiles, pkg.CgoFiles, pkg.TestGoFiles, pkg.XTestGoFiles} + for _, f := range files { + for _, name := range f { + if name == info.Name() { + return true + } } } return false @@ -159,13 +160,9 @@ func parsePackage(writer io.Writer, pkg *build.Package, userPath string) *Packag if err != nil { log.Fatal(err) } - // Make sure they are all in one package. if len(pkgs) == 0 { log.Fatalf("no source-code package in directory %s", pkg.Dir) } - if len(pkgs) > 1 { - log.Fatalf("multiple packages in directory %s", pkg.Dir) - } astPkg := pkgs[pkg.Name] // TODO: go/doc does not include typed constants in the constants @@ -180,7 +177,16 @@ func parsePackage(writer io.Writer, pkg *build.Package, userPath string) *Packag if showSrc { mode |= doc.PreserveAST // See comment for Package.emit. } - docPkg := doc.New(astPkg, pkg.ImportPath, mode) + var allGoFiles []*ast.File + for _, p := range pkgs { + for _, f := range p.Files { + allGoFiles = append(allGoFiles, f) + } + } + docPkg, err := doc.NewFromFiles(fset, allGoFiles, pkg.ImportPath, mode) + if err != nil { + log.Fatal(err) + } typedValue := make(map[*doc.Value]bool) constructor := make(map[*doc.Func]bool) for _, typ := range docPkg.Types { @@ -526,7 +532,7 @@ func (pkg *Package) funcsDoc() { } } -// funcsDoc prints all type documentation, if any, including a header. +// typesDoc prints all type documentation, if any, including a header. func (pkg *Package) typesDoc() { var header bool for _, typ := range pkg.doc.Types { @@ -568,6 +574,7 @@ func (pkg *Package) packageDoc() { pkg.valueSummary(pkg.doc.Vars, false) pkg.funcSummary(pkg.doc.Funcs, false) pkg.typeSummary() + pkg.exampleSummary(pkg.doc.Examples, false) } if !short { @@ -650,11 +657,27 @@ func (pkg *Package) funcSummary(funcs []*doc.Func, showConstructors bool) { if isExported(fun.Name) { if showConstructors || !pkg.constructor[fun] { pkg.Printf("%s\n", pkg.oneLineNode(fun.Decl)) + if showEx { + pkg.exampleSummary(fun.Examples, false) + } } } } } +// exampleSummary prints a one-line summary for each example. +func (pkg *Package) exampleSummary(exs []*doc.Example, showDoc bool) { + if !showEx { + return + } + for _, ex := range exs { + pkg.Printf(indent+"func Example%s()\n", ex.Name) + if showDoc && ex.Doc != "" { + pkg.ToText(&pkg.buf, ex.Doc, indent+indent, indent+indent) + } + } +} + // typeSummary prints a one-line summary for each type, followed by its constructors. func (pkg *Package) typeSummary() { for _, typ := range pkg.doc.Types { @@ -676,8 +699,10 @@ func (pkg *Package) typeSummary() { for _, constructor := range typ.Funcs { if isExported(constructor.Name) { pkg.Printf(indent+"%s\n", pkg.oneLineNode(constructor.Decl)) + pkg.exampleSummary(constructor.Examples, false) } } + pkg.exampleSummary(typ.Examples, false) } } } @@ -728,6 +753,40 @@ func (pkg *Package) findTypes(symbol string) (types []*doc.Type) { return } +// findExamples finds any examples that describe the symbol. +func (pkg *Package) findExamples(symbol string) (examples []*doc.Example) { + if !strings.HasPrefix(symbol, "Example") { + return + } + symbol = strings.TrimPrefix(symbol, "Example") + var all []*doc.Example + all = append(all, pkg.doc.Examples...) + for _, typ := range pkg.doc.Types { + all = append(all, typ.Examples...) + for _, fun := range typ.Funcs { + all = append(all, fun.Examples...) + } + for _, fun := range typ.Methods { + all = append(all, fun.Examples...) + } + } + for _, fun := range pkg.doc.Funcs { + all = append(all, fun.Examples...) + } + + // always include unexported in below match(), so Example_one + // is still matched despite trimming the Example_ part. + u := unexported + unexported = true + for _, ex := range all { + if match(symbol, ex.Name) { + examples = append(examples, ex) + } + } + unexported = u + return +} + // findTypeSpec returns the ast.TypeSpec within the declaration that defines the symbol. // The name must match exactly. func (pkg *Package) findTypeSpec(decl *ast.GenDecl, symbol string) *ast.TypeSpec { @@ -749,7 +808,17 @@ func (pkg *Package) symbolDoc(symbol string) bool { for _, fun := range pkg.findFuncs(symbol) { // Symbol is a function. decl := fun.Decl + found = true + if short { + pkg.Printf("%s\n", pkg.oneLineNode(decl)) + pkg.exampleSummary(fun.Examples, false) + continue + } pkg.emit(fun.Doc, decl) + pkg.exampleSummary(fun.Examples, true) + } + for _, ex := range pkg.findExamples(symbol) { + pkg.emitExample(ex) found = true } // Constants and variables behave the same. @@ -822,8 +891,12 @@ func (pkg *Package) valueDoc(value *doc.Value, printed map[*ast.GenDecl]bool) { return } value.Decl.Specs = specs - pkg.emit(value.Doc, value.Decl) printed[value.Decl] = true + if short { + pkg.Printf("%s\n", pkg.oneLineNode(value.Decl)) + return + } + pkg.emit(value.Doc, value.Decl) } // typeDoc prints the docs for a type, including constructors and other items @@ -836,6 +909,10 @@ func (pkg *Package) typeDoc(typ *doc.Type) { if len(decl.Specs) > 1 { decl.Specs = []ast.Spec{spec} } + if short { + pkg.Printf("%s\n", pkg.oneLineNode(spec)) + return + } pkg.emit(typ.Doc, decl) pkg.newlines(2) // Show associated methods, constants, etc. @@ -866,6 +943,7 @@ func (pkg *Package) typeDoc(typ *doc.Type) { pkg.valueSummary(typ.Consts, true) pkg.valueSummary(typ.Vars, true) pkg.funcSummary(typ.Funcs, true) + pkg.exampleSummary(typ.Examples, false) pkg.funcSummary(typ.Methods, true) } } @@ -947,10 +1025,11 @@ func trimUnexportedFields(fields *ast.FieldList, isInterface bool) *ast.FieldLis constraint := false switch ident := ty.(type) { case *ast.Ident: - if isInterface && ident.Name == "error" && ident.Obj == nil { + if isInterface && ident.Obj == nil && + (ident.Name == "error" || ident.Name == "comparable") { // For documentation purposes, we consider the builtin error - // type special when embedded in an interface, such that it - // always gets shown publicly. + // and comparable types special when embedded in an interface, + // such that they always get shown publicly. list = append(list, field) continue } @@ -1024,6 +1103,7 @@ func (pkg *Package) printMethodDoc(symbol, method string) bool { if match(method, meth.Name) { decl := meth.Decl pkg.emit(meth.Doc, decl) + pkg.exampleSummary(meth.Examples, true) found = true } } @@ -1165,3 +1245,33 @@ func simpleFold(r rune) rune { r = r1 } } + +// emitExample prints an example and its output. +func (pkg *Package) emitExample(ex *doc.Example) { + pkg.buf.printed = true // omit the package clause + var err error + if ex.Play != nil { + err = format.Node(&pkg.buf, pkg.fs, ex.Play) + } else { + // If code is an *ast.BlockStmt, trim the braces and indentation + // by just printing the enclosed List of ast.[]Stmt. + b, ok := ex.Code.(*ast.BlockStmt) + if !ok { + err = format.Node(&pkg.buf, pkg.fs, ex.Code) + } else { + err = format.Node(&pkg.buf, pkg.fs, b.List) + } + } + if err != nil { + log.Fatal(err) + } + if ex.Output != "" { + pkg.newlines(2) + pkg.Printf("Output: ") + if strings.Count(ex.Output, "\n") > 1 { + pkg.newlines(1) + } + pkg.Printf("%s", ex.Output) + } + pkg.newlines(1) +} diff --git a/src/cmd/go/internal/doc/pkgsite.go b/src/cmd/go/internal/doc/pkgsite.go index c173167b6329a4..9ab0843ab25ce1 100644 --- a/src/cmd/go/internal/doc/pkgsite.go +++ b/src/cmd/go/internal/doc/pkgsite.go @@ -7,17 +7,33 @@ package doc import ( + "context" "errors" "fmt" "net" "net/url" "os" "os/exec" - "os/signal" "path/filepath" "strings" + + "cmd/go/internal/base" + "cmd/go/internal/cfg" + "cmd/go/internal/load" + "cmd/go/internal/modload" + "cmd/go/internal/work" ) +// pkgsiteCmdInternalDocVersion controls the version of the golang.org/x/pkgsite/cmd/internal/doc +// module to build in buildPkgsite. +// +// This version is maintained, like other golang.org/x dependencies, via the go.dev/issue/36905 process. +// +// To make that process easier, the exact name and file location of this constant are known +// to the [golang.org/x/build/cmd/updatestd] command. If this constant needs to be renamed +// or moved to another .go file, update that code too. +const pkgsiteCmdInternalDocVersion = "v0.0.0-20260722200430-7c7eca789259" + // pickUnusedPort finds an unused port by trying to listen on port 0 // and letting the OS pick a port, then closing that connection and // returning that port number. @@ -34,7 +50,59 @@ func pickUnusedPort() (int, error) { return port, nil } -func doPkgsite(urlPath, fragment string) error { +// buildPkgsite builds a pkgsite binary whose build may be cached. +func buildPkgsite(ctx context.Context) string { + load.ClearPackageCache() + loader := modload.NewLoader() + + // Set the builder to have no module root so we can build a pkg@version pattern. + loader.ForceUseModules = true + loader.RootMode = modload.NoRoot + loader.AllowMissingModuleImports() + modload.Init(loader) + + work.BuildInit(loader) + b := work.NewBuilder("", loader.VendorDirOrEmpty) + defer func() { + if err := b.Close(); err != nil { + base.Fatal(err) + } + }() + + version := pkgsiteCmdInternalDocVersion + if os.Getenv("TEST_GODOC_BUILD_ONLY") != "" { + version = "v0.1.0" + } + pkgVers := "golang.org/x/pkgsite/cmd/internal/doc@" + version + pkgOpts := load.PackageOpts{MainOnly: true} + pkgs, err := load.PackagesAndErrorsOutsideModule(loader, ctx, pkgOpts, []string{pkgVers}) + if err != nil { + base.Fatal(err) + } + if len(pkgs) == 0 { + base.Fatalf("go: internal error: no packages loaded for %s", pkgVers) + } + if len(pkgs) > 1 { + base.Fatalf("go: internal error: pattern %s matches multiple packages", pkgVers) + } + p := pkgs[0] + p.Internal.OmitDebug = true + p.Internal.ExeName = p.DefaultExecName() + load.CheckPackageErrors([]*load.Package{p}) + + a := b.LinkAction(loader, work.ModeBuild, work.ModeBuild, p) + a.CacheExecutable = true + b.Do(ctx, a) + + // Both paths return an executable in GOCACHE: CachedExecutable is set on + // fresh builds, while BuiltTarget is set on cache hits. + if cached := a.CachedExecutable(); cached != "" { + return cached + } + return a.BuiltTarget() +} + +func doPkgsite(ctx context.Context, urlPath, fragment string) error { port, err := pickUnusedPort() if err != nil { return fmt.Errorf("failed to find port for documentation server: %v", err) @@ -48,10 +116,14 @@ func doPkgsite(urlPath, fragment string) error { path += "#" + fragment } + if file := os.Getenv("TEST_GODOC_URL_FILE"); file != "" { + return os.WriteFile(file, []byte(path+"\n"), 0666) + } + // Turn off the default signal handler for SIGINT (and SIGQUIT on Unix) // and instead wait for the child process to handle the signal and // exit before exiting ourselves. - signal.Ignore(signalsToIgnore...) + base.StartSigHandlers() // Prepend the local download cache to GOPROXY to get around deprecation checks. env := os.Environ() @@ -71,11 +143,14 @@ func doPkgsite(urlPath, fragment string) error { env = append(env, "GOPROXY="+gomodcache+","+goproxy) } - const version = "v0.0.0-20250714212547-01b046e81fe7" - cmd := exec.Command(goCmd(), "run", "golang.org/x/pkgsite/cmd/internal/doc@"+version, - "-gorepo", buildCtx.GOROOT, - "-http", addr, - "-open", path) + pkgsite := buildPkgsite(ctx) + if os.Getenv("TEST_GODOC_BUILD_ONLY") != "" { + if _, err := os.Stat(pkgsite); err != nil { + return fmt.Errorf("built pkgsite binary does not exist: %w", err) + } + return nil + } + cmd := exec.Command(pkgsite, "-gorepo", cfg.GOROOT, "-http", addr, "-open", path) cmd.Env = env cmd.Stdout = os.Stderr cmd.Stderr = os.Stderr diff --git a/src/cmd/go/internal/doc/pkgsite_bootstrap.go b/src/cmd/go/internal/doc/pkgsite_bootstrap.go index 3c9f546957e5a0..cb72492cb5e73a 100644 --- a/src/cmd/go/internal/doc/pkgsite_bootstrap.go +++ b/src/cmd/go/internal/doc/pkgsite_bootstrap.go @@ -8,4 +8,6 @@ package doc -func doPkgsite(string, string) error { return nil } +import "context" + +func doPkgsite(context.Context, string, string) error { return nil } diff --git a/src/cmd/go/internal/doc/testdata/pkg.go b/src/cmd/go/internal/doc/testdata/pkg.go index 4d269ff0a22959..53b018318f3cc7 100644 --- a/src/cmd/go/internal/doc/testdata/pkg.go +++ b/src/cmd/go/internal/doc/testdata/pkg.go @@ -252,3 +252,16 @@ type TildeConstraint interface { type StructConstraint interface { struct { F int } } + +// Comment about exported interface with comparable. +type ExportedComparableInterface interface { + comparable // Comment on line with comparable. + ExportedMethod() // Comment on line with exported method. + unexportedMethod() // Comment on line with unexported method. +} + +// ExportedComparableOnlyInterface has only comparable and exported method (no unexported). +type ExportedComparableOnlyInterface interface { + comparable // Comment on line with comparable. + ExportedMethod() // Comment on line with exported method. +} diff --git a/src/cmd/go/internal/doc/testdata/pkg_test.go b/src/cmd/go/internal/doc/testdata/pkg_test.go new file mode 100644 index 00000000000000..0b4e62e0086b15 --- /dev/null +++ b/src/cmd/go/internal/doc/testdata/pkg_test.go @@ -0,0 +1,47 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package pkg + +import "fmt" + +// Package example. +func Example() { + fmt.Println("Package example output") + // Output: Package example output +} + +// Function example. +func ExampleExportedFunc() { + fmt.Println("Function example output") + // Output: Function example output +} + +// Function example two. +func ExampleExportedFunc_two() { + fmt.Println("Function example two output") + // Output: Function example two output +} + +// Type example. +func ExampleExportedType() { + fmt.Println("Type example output") + // Output: Type example output +} + +// Method example. +func ExampleExportedType_ExportedMethod() { + fmt.Println("Method example output") + // Output: Method example output +} + +// Multiline example. +func Example_multiline() { + fmt.Println("Multiline\nexample\noutput") + // Output: + // Multiline + // example + // output +} + diff --git a/src/cmd/go/internal/doc/testdata/play_test.go b/src/cmd/go/internal/doc/testdata/play_test.go new file mode 100644 index 00000000000000..6b510895031c4f --- /dev/null +++ b/src/cmd/go/internal/doc/testdata/play_test.go @@ -0,0 +1,13 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package pkg_test + +import "fmt" + +// Playable example. +func Example_playable() { + fmt.Println("Playable example output") + // Output: Playable example output +} diff --git a/src/cmd/go/internal/envcmd/env.go b/src/cmd/go/internal/envcmd/env.go index f600a354727ae1..3d72c368b088a2 100644 --- a/src/cmd/go/internal/envcmd/env.go +++ b/src/cmd/go/internal/envcmd/env.go @@ -83,7 +83,6 @@ func MkEnv() []cfg.EnvVar { {Name: "GO111MODULE", Value: cfg.Getenv("GO111MODULE")}, {Name: "GOARCH", Value: cfg.Goarch, Changed: cfg.Goarch != runtime.GOARCH}, {Name: "GOAUTH", Value: cfg.GOAUTH, Changed: cfg.GOAUTHChanged}, - {Name: "GOBIN", Value: cfg.GOBIN}, {Name: "GOCACHE"}, {Name: "GOCACHEPROG", Value: cfg.GOCACHEPROG, Changed: cfg.GOCACHEPROGChanged}, {Name: "GODEBUG", Value: os.Getenv("GODEBUG")}, @@ -106,6 +105,13 @@ func MkEnv() []cfg.EnvVar { {Name: "GONOPROXY", Value: cfg.GONOPROXY, Changed: cfg.GONOPROXYChanged}, {Name: "GONOSUMDB", Value: cfg.GONOSUMDB, Changed: cfg.GONOSUMDBChanged}, {Name: "GOOS", Value: cfg.Goos, Changed: cfg.Goos != runtime.GOOS}, + + // GOPACKAGESDRIVER isn't read or used by cmd/go, so it can only + // be sourced from environment variables. + // We include it for bug reports. + // go.dev/issue/75930 + {Name: "GOPACKAGESDRIVER", Value: os.Getenv("GOPACKAGESDRIVER")}, + {Name: "GOPATH", Value: cfg.BuildContext.GOPATH, Changed: cfg.GOPATHChanged}, {Name: "GOPRIVATE", Value: cfg.GOPRIVATE}, {Name: "GOPROXY", Value: cfg.GOPROXY, Changed: cfg.GOPROXYChanged}, @@ -126,7 +132,7 @@ func MkEnv() []cfg.EnvVar { if env[i].Value != "on" && env[i].Value != "" { env[i].Changed = true } - case "GOBIN", "GOEXPERIMENT", "GOFLAGS", "GOINSECURE", "GOPRIVATE", "GOTMPDIR", "GOVCS": + case "GOEXPERIMENT", "GOFLAGS", "GOINSECURE", "GOPACKAGESDRIVER", "GOPRIVATE", "GOTMPDIR", "GOVCS": if env[i].Value != "" { env[i].Changed = true } @@ -189,30 +195,51 @@ func findEnv(env []cfg.EnvVar, name string) string { } // ExtraEnvVars returns environment variables that should not leak into child processes. -func ExtraEnvVars(loaderstate *modload.State) []cfg.EnvVar { +func ExtraEnvVars(ld *modload.Loader) []cfg.EnvVar { gomod := "" - modload.Init(loaderstate) - if modload.HasModRoot(loaderstate) { - gomod = modload.ModFilePath(loaderstate) - } else if modload.Enabled(loaderstate) { + modload.Init(ld) + if ld.HasModRoot() { + gomod = ld.ModFilePath() + } else if ld.Enabled() { gomod = os.DevNull } - modload.InitWorkfile(loaderstate) - gowork := modload.WorkFilePath(loaderstate) + ld.InitWorkfile() + gowork := modload.WorkFilePath(ld) // As a special case, if a user set off explicitly, report that in GOWORK. if cfg.Getenv("GOWORK") == "off" { gowork = "off" } + gobin := cfg.GOBIN + if gobin == "" && cfg.ModulesEnabled { + gobin = modload.BinDir(ld) + } else if gobin == "" { + // Best effort guess of where the binary will be installed. + // go.dev/issue/23439 + gopaths := filepath.SplitList(cfg.BuildContext.GOPATH) + wd, err := os.Getwd() + if err == nil && len(gopaths) > 0 { + gopath := gopaths[0] + for _, p := range gopaths { + if strings.HasPrefix(wd, p) { + gopath = p + break + } + } + gobin = filepath.Join(gopath, "bin") + } + } + return []cfg.EnvVar{ {Name: "GOMOD", Value: gomod}, {Name: "GOWORK", Value: gowork}, + {Name: "GOBIN", Value: gobin, Changed: cfg.GOBINChanged}, } } // ExtraEnvVarsCostly returns environment variables that should not leak into child processes // but are costly to evaluate. -func ExtraEnvVarsCostly(loaderstate *modload.State) []cfg.EnvVar { - b := work.NewBuilder("", loaderstate.VendorDirOrEmpty) +func ExtraEnvVarsCostly(ld *modload.Loader) []cfg.EnvVar { + b := work.NewBuilder("", ld.VendorDirOrEmpty) defer func() { if err := b.Close(); err != nil { base.Fatal(err) @@ -272,7 +299,7 @@ func argKey(arg string) string { } func runEnv(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() if *envJson && *envU { base.Fatalf("go: cannot use -json with -u") } @@ -307,7 +334,7 @@ func runEnv(ctx context.Context, cmd *base.Command, args []string) { } env := cfg.CmdEnv - env = append(env, ExtraEnvVars(moduleLoaderState)...) + env = append(env, ExtraEnvVars(moduleLoader)...) if err := fsys.Init(); err != nil { base.Fatal(err) @@ -337,8 +364,8 @@ func runEnv(ctx context.Context, cmd *base.Command, args []string) { } } if needCostly { - work.BuildInit(moduleLoaderState) - env = append(env, ExtraEnvVarsCostly(moduleLoaderState)...) + work.BuildInit(moduleLoader) + env = append(env, ExtraEnvVarsCostly(moduleLoader)...) } if len(args) > 0 { @@ -604,7 +631,17 @@ func getOrigEnv(key string) string { func checkEnvWrite(key, val string) error { switch key { - case "GOEXE", "GOGCCFLAGS", "GOHOSTARCH", "GOHOSTOS", "GOMOD", "GOWORK", "GOTOOLDIR", "GOVERSION", "GOTELEMETRY", "GOTELEMETRYDIR": + case "GOEXE", + "GOGCCFLAGS", + "GOHOSTARCH", + "GOHOSTOS", + "GOMOD", + "GOROOT", + "GOTELEMETRY", + "GOTELEMETRYDIR", + "GOTOOLDIR", + "GOVERSION", + "GOWORK": return fmt.Errorf("%s cannot be modified", key) case "GOENV", "GODEBUG": return fmt.Errorf("%s can only be set using the OS environment", key) diff --git a/src/cmd/go/internal/fips140/fips140.go b/src/cmd/go/internal/fips140/fips140.go index 4194f0ff6aa997..f5d3c2c758459e 100644 --- a/src/cmd/go/internal/fips140/fips140.go +++ b/src/cmd/go/internal/fips140/fips140.go @@ -2,7 +2,7 @@ // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. -// Package fips implements support for the GOFIPS140 build setting. +// Package fips140 implements support for the GOFIPS140 build setting. // // The GOFIPS140 build setting controls two aspects of the build: // @@ -85,18 +85,22 @@ package fips140 import ( - "cmd/go/internal/base" - "cmd/go/internal/cfg" - "cmd/go/internal/fsys" - "cmd/go/internal/modfetch" - "cmd/go/internal/str" "context" + "crypto/sha256" + "fmt" + "io" "os" "path" "path/filepath" "slices" "strings" + "cmd/go/internal/base" + "cmd/go/internal/cfg" + "cmd/go/internal/fsys" + "cmd/go/internal/modfetch" + "cmd/go/internal/str" + "golang.org/x/mod/module" "golang.org/x/mod/semver" ) @@ -224,12 +228,78 @@ func initDir() { mod := module.Version{Path: "golang.org/fips140", Version: v} file := filepath.Join(cfg.GOROOT, "lib/fips140", v+".zip") - zdir, err := modfetch.Unzip(context.Background(), mod, file) + ctx := context.Background() + + sumfile := filepath.Join(cfg.GOROOT, "lib/fips140/fips140.sum") + _, ziphash, err := lookupZipSum(sumfile, filepath.Base(file)) + if err != nil { + base.Fatalf("go: verifying GOFIPS140=%v: %v", v, err) + } + + // fips140.sum records both the SHA-256 hash of the zip file and its + // go.sum-style module zip hash. Unzip uses the cached copy in the + // module cache only if the cache records that module zip hash for it, + // and otherwise discards the copy and unpacks the snapshot again. + // + // The FIPS 140-3 Security Policy requires checking the SHA-256 hash + // of the zip file. Unzip calls verify exactly when it is about to + // unpack the zip file, so the hash is checked once per unpacking + // (whatever the reason for it) rather than on every go command. + verify := func() error { return verifyZipSum(file, sumfile) } + zdir, err := modfetch.NewFetcher().Unzip(ctx, mod, file, ziphash, verify) if err != nil { base.Fatalf("go: unpacking GOFIPS140=%v: %v", v, err) } dir = filepath.Join(zdir, "fips140") - return +} + +// lookupZipSum returns the SHA-256 hash and module zip hash recorded for +// name in sumfile, which is expected to be in the format of +// GOROOT/lib/fips140/fips140.sum: "NAME SHA256HEX H1HASH" lines, with "#" +// comments. H1HASH is the module zip hash in the format used by go.sum. +func lookupZipSum(sumfile, name string) (sha256hex, ziphash string, err error) { + sums, err := os.ReadFile(sumfile) + if err != nil { + return "", "", err + } + for line := range strings.SplitSeq(string(sums), "\n") { + line = strings.TrimSpace(line) + if line == "" || strings.HasPrefix(line, "#") { + continue + } + f := strings.Fields(line) + if len(f) != 3 || f[0] != name { + continue + } + if !strings.HasPrefix(f[2], "h1:") { + return "", "", fmt.Errorf("malformed module zip hash %q for %s in %s", f[2], name, sumfile) + } + return f[1], f[2], nil + } + return "", "", fmt.Errorf("no entry for %s in %s", name, sumfile) +} + +// verifyZipSum checks that the SHA-256 hash of zipfile matches the entry +// for its base name in sumfile. +func verifyZipSum(zipfile, sumfile string) error { + name := filepath.Base(zipfile) + want, _, err := lookupZipSum(sumfile, name) + if err != nil { + return err + } + f, err := os.Open(zipfile) + if err != nil { + return err + } + defer f.Close() + h := sha256.New() + if _, err := io.Copy(h, f); err != nil { + return err + } + if got := fmt.Sprintf("%x", h.Sum(nil)); got != want { + return fmt.Errorf("SHA-256 hash of %s is %s, want %s (from %s)", name, got, want, sumfile) + } + return nil } // ResolveImport resolves the import path imp. diff --git a/src/cmd/go/internal/fips140/fips_test.go b/src/cmd/go/internal/fips140/fips_test.go index 53f0c9ab582260..bb9ccb70c6925d 100644 --- a/src/cmd/go/internal/fips140/fips_test.go +++ b/src/cmd/go/internal/fips140/fips_test.go @@ -15,6 +15,8 @@ import ( "slices" "strings" "testing" + + "golang.org/x/mod/sumdb/dirhash" ) var update = flag.Bool("update", false, "update GOROOT/lib/fips140/fips140.sum") @@ -33,8 +35,8 @@ func TestSums(t *testing.T) { t.Fatal(err) } - format := func(name string, sum [32]byte) string { - return fmt.Sprintf("%s %x\n", name, sum[:]) + format := func(name string, sum [32]byte, ziphash string) string { + return fmt.Sprintf("%s %x %s\n", name, sum[:], ziphash) } want := make(map[string]string) @@ -43,8 +45,12 @@ func TestSums(t *testing.T) { if err != nil { t.Fatal(err) } + ziphash, err := dirhash.HashZip(zip, dirhash.DefaultHash) + if err != nil { + t.Fatal(err) + } name := filepath.Base(zip) - want[name] = format(name, sha256.Sum256(data)) + want[name] = format(name, sha256.Sum256(data), ziphash) } // Process diff, deleting or correcting stale lines. @@ -100,3 +106,48 @@ func TestSums(t *testing.T) { t.Errorf("GOROOT/lib/fips140/fips140.sum out of date. changes needed:\n%s", strings.Join(diff, "")) } } + +func TestVerifyZipSum(t *testing.T) { + dir := t.TempDir() + zipfile := filepath.Join(dir, "v1.2.3.zip") + data := []byte("not really a zip, but it does not matter here") + if err := os.WriteFile(zipfile, data, 0666); err != nil { + t.Fatal(err) + } + sum := sha256.Sum256(data) + + sumfile := filepath.Join(dir, "fips140.sum") + write := func(contents string) { + if err := os.WriteFile(sumfile, []byte(contents), 0666); err != nil { + t.Fatal(err) + } + } + + const ( + zeroSum = "0000000000000000000000000000000000000000000000000000000000000000" + ziphash = "h1:AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA=" + ) + + // Matching hash with comments and a second entry passes. + write(fmt.Sprintf("# comment\n\nv1.2.3.zip %x %s\nother.zip %s h1:other=\n", sum[:], ziphash, zeroSum)) + if err := verifyZipSum(zipfile, sumfile); err != nil { + t.Errorf("unexpected error: %v", err) + } + + // Missing entry for this zip fails. + write("# only comments\n") + if err := verifyZipSum(zipfile, sumfile); err == nil { + t.Errorf("expected error when hash entry is missing") + } + + // Wrong hash fails. + write(fmt.Sprintf("v1.2.3.zip %s %s\n", zeroSum, ziphash)) + if err := verifyZipSum(zipfile, sumfile); err == nil { + t.Errorf("expected error when hash does not match") + } + + // Missing sum file fails. + if err := verifyZipSum(zipfile, filepath.Join(dir, "does-not-exist.sum")); err == nil { + t.Errorf("expected error when sum file is missing") + } +} diff --git a/src/cmd/go/internal/fmtcmd/fmt.go b/src/cmd/go/internal/fmtcmd/fmt.go index cd689b510deb19..7f7322b6d7a777 100644 --- a/src/cmd/go/internal/fmtcmd/fmt.go +++ b/src/cmd/go/internal/fmtcmd/fmt.go @@ -50,7 +50,7 @@ See also: go fix, go vet. } func runFmt(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() printed := false gofmt := gofmtPath() @@ -60,8 +60,8 @@ func runFmt(ctx context.Context, cmd *base.Command, args []string) { baseGofmtArgs := len(gofmtArgs) baseGofmtArgLen := gofmtArgLen - for _, pkg := range load.PackagesAndErrors(moduleLoaderState, ctx, load.PackageOpts{}, args) { - if modload.Enabled(moduleLoaderState) && pkg.Module != nil && !pkg.Module.Main { + for _, pkg := range load.PackagesAndErrors(moduleLoader, ctx, load.PackageOpts{}, args) { + if moduleLoader.Enabled() && pkg.Module != nil && !pkg.Module.Main { if !printed { fmt.Fprintf(os.Stderr, "go: not formatting packages in dependency modules\n") printed = true diff --git a/src/cmd/go/internal/generate/generate.go b/src/cmd/go/internal/generate/generate.go index 2a5a5a6764af95..c4ab16cf929dde 100644 --- a/src/cmd/go/internal/generate/generate.go +++ b/src/cmd/go/internal/generate/generate.go @@ -182,8 +182,8 @@ func init() { } func runGenerate(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() if generateRunFlag != "" { var err error @@ -205,8 +205,8 @@ func runGenerate(ctx context.Context, cmd *base.Command, args []string) { // Even if the arguments are .go files, this loop suffices. printed := false pkgOpts := load.PackageOpts{IgnoreImports: true} - for _, pkg := range load.PackagesAndErrors(moduleLoaderState, ctx, pkgOpts, args) { - if modload.Enabled(moduleLoaderState) && pkg.Module != nil && !pkg.Module.Main { + for _, pkg := range load.PackagesAndErrors(moduleLoader, ctx, pkgOpts, args) { + if moduleLoader.Enabled() && pkg.Module != nil && !pkg.Module.Main { if !printed { fmt.Fprintf(os.Stderr, "go: not generating in packages in dependency modules\n") printed = true @@ -244,7 +244,7 @@ func generate(absFile string) bool { } // Parse package clause - filePkg, err := parser.ParseFile(token.NewFileSet(), "", src, parser.PackageClauseOnly) + filePkg, err := parser.ParseFile(token.NewFileSet(), "", src, parser.PackageClauseOnly|parser.SkipObjectResolution) if err != nil { // Invalid package clause - ignore file. return true diff --git a/src/cmd/go/internal/generate/generate_test.go b/src/cmd/go/internal/generate/generate_test.go index 2eef917e7e2758..b11ed505450ba8 100644 --- a/src/cmd/go/internal/generate/generate_test.go +++ b/src/cmd/go/internal/generate/generate_test.go @@ -79,7 +79,7 @@ var defEnvMap = map[string]string{ "_X": "Y", } -// TestGenerateCommandShortHand - similar to TestGenerateCommandParse, +// TestGenerateCommandShorthand - similar to TestGenerateCommandParse, // except: // 1. if the result starts with -command, record that shorthand // before moving on to the next test. diff --git a/src/cmd/go/internal/gover/version.go b/src/cmd/go/internal/gover/version.go index 15c712a4392825..7e27482aa8af2e 100644 --- a/src/cmd/go/internal/gover/version.go +++ b/src/cmd/go/internal/gover/version.go @@ -36,11 +36,16 @@ const ( // the module graph; see https://golang.org/ref/mod#graph-pruning. ExplicitIndirectVersion = "1.17" - // separateIndirectVersion is the Go version at which + // SeparateIndirectVersion is the Go version at which // "// indirect" dependencies are added in a block separate from the direct // ones. See https://golang.org/issue/45965. SeparateIndirectVersion = "1.17" + // SimplifyRequireVersion is the Go version at which + // require blocks are simplified to always have at most two sections + // (one direct, one indirect). See https://go.dev/issue/56471. + SimplifyRequireVersion = "1.27" + // tidyGoModSumVersion is the Go version at which // 'go mod tidy' preserves go.mod checksums needed to build test dependencies // of packages in "all", so that 'go test all' can be run without checksum @@ -57,6 +62,10 @@ const ( // ExplicitModulesTxtImportVersion is the Go version at which vendored packages need to be present // in modules.txt to be imported. ExplicitModulesTxtImportVersion = "1.23" + + // GoModToolVersion is the Go version required for the tool + // directive in go.mod. + GoModToolVersion = "1.24" ) // FromGoMod returns the go version from the go.mod file. diff --git a/src/cmd/go/internal/help/helpdoc.go b/src/cmd/go/internal/help/helpdoc.go index ab04ce001c41db..b305457a23d104 100644 --- a/src/cmd/go/internal/help/helpdoc.go +++ b/src/cmd/go/internal/help/helpdoc.go @@ -38,135 +38,223 @@ Many commands apply to a set of packages: go [packages] -Usually, [packages] is a list of import paths. +Usually, [packages] is a list of package patterns, +which can take several forms: -An import path that is a rooted path or that begins with -a . or .. element is interpreted as a file system path and -denotes the package in that directory. - -Otherwise, the import path P denotes the package found in -the directory DIR/src/P for some DIR listed in the GOPATH -environment variable (For more details see: 'go help gopath'). +- A relative or absolute path to a file system directory, + which can contain "..." wildcard elements. +- An import path, which can also contain "..." wildcard elements. +- A reserved name that expands to a set of packages +- A list of files If no import paths are given, the action applies to the package in the current directory. -There are five reserved names for paths that should not be used -for packages to be built with the go tool: +"..." elements in filesystem or import paths expand +to match 0 or more path elements. +Specific rules are described below. -- "main" denotes the top-level package in a stand-alone executable. +File system patterns + +Patterns beginning with a file system root like / on Unixes, +or a volume name like C: on Windows are interpreted as absolute file system paths. +Patterns beginning with a "." or ".." element are interpreted as relative file system paths. +File system paths denote the package contained within the given directory. + +Relative paths can be used as a shorthand on the command line. +If you are working in the directory containing the code imported as +"unicode" and want to run the tests for "unicode/utf8", you can type +"go test ./utf8" instead of needing to specify the full path. +Similarly, in the reverse situation, "go test .." will test "unicode" from +the "unicode/utf8" directory. Relative patterns are also allowed, such as +"go test ./..." to test all subdirectories. + +File system patterns expanded with the "..." wildcard exclude the following: + +- Directories named "vendor" +- Directories named "testdata" +- Files and directories with names beginning with "_" or "." +- Directories that contain a go.mod file +- Directories matching an ignore directive in a module's go.mod file + +These can be included by either using them in the prefix, +or changing into the directories. For example, "./..." won't +match a "./testdata/foo" package, but "./testdata/..." will. + +Directories containing other go modules, +which are denoted by the presence of a go.mod file, +can only be matched by changing the working directory into module. + +Import path patterns + +Patterns may be import paths as described in "go help importpath". +Import path patterns natch the packages from modules in the build list. +The "build list" is the list of module versions used for a build. +See https://go.dev/ref/mod#glos-build-list for more details. + +Some commands accept versioned package patterns, +such as: "example.com/my/module@v1.2.3" +These describe the matching package at the given version, +independent of the versions used by the current module. + +Import path patterns may also use a "..." wildcard, +such as: "example.com/my/module/...". +This can be combined with the version specifier +such as: "example.com/my/module/...@latest". + +Import path pattern expansion with "..." depends on context: + +- "prefix/..." matches all packages in modules in the build list + that share the prefix, even if they belong to different modules. +- patterns that include a version specifier such as in "prefix/...@latest" + only match packages from the module that "prefix" belongs to. + +Reserved names + +The following reserved names expand to a set of packages: + +- "work" expands to all packages in the main module (or workspace modules). + +- "tool" expands to the tools defined in the current module's go.mod file. - "all" expands to all packages in the main module (or workspace modules) and their dependencies, including dependencies needed by tests of any of those. In -GOPATH mode, "all" expands to all packages found in all the GOPATH trees. +the legacy GOPATH mode, "all" expands to all packages found in all the GOPATH trees. -- "std" is like all but expands to just the packages in the standard -Go library. +- "std" expands to all the packages in the standard library +and their internal libraries. - "cmd" expands to the Go repository's commands and their internal libraries. -- "tool" expands to the tools defined in the current module's go.mod file. +List of .go files -Package names match against fully-qualified import paths or patterns that -match against any number of import paths. For instance, "fmt" refers to the -standard library's package fmt, but "http" alone for package http would not -match the import path "net/http" from the standard library. Instead, the -complete import path "net/http" must be used. - -Import paths beginning with "cmd/" only match source code in -the Go repository. - -An import path is a pattern if it includes one or more "..." wildcards, -each of which can match any string, including the empty string and -strings containing slashes. Such a pattern expands to all package -directories found in the GOPATH trees with names matching the -patterns. - -To make common patterns more convenient, there are two special cases. -First, /... at the end of the pattern can match an empty string, -so that net/... matches both net and packages in its subdirectories, like net/http. -Second, any slash-separated pattern element containing a wildcard never -participates in a match of the "vendor" element in the path of a vendored -package, so that ./... does not match packages in subdirectories of -./vendor or ./mycode/vendor, but ./vendor/... and ./mycode/vendor/... do. -Note, however, that a directory named vendor that itself contains code -is not a vendored package: cmd/vendor would be a command named vendor, -and the pattern cmd/... matches it. -See golang.org/s/go15vendor for more about vendoring. - -An import path can also name a package to be downloaded from -a remote repository. Run 'go help importpath' for details. - -Every package in a program must have a unique import path. -By convention, this is arranged by starting each path with a -unique prefix that belongs to you. For example, paths used -internally at Google all begin with 'google', and paths -denoting remote repositories begin with the path to the code, -such as 'github.com/user/repo'. Package patterns should include this prefix. -For instance, a package called 'http' residing under 'github.com/user/repo', -would be addressed with the fully-qualified pattern: -'github.com/user/repo/http'. - -Packages in a program need not have unique package names, -but there are two reserved package names with special meaning. -The name main indicates a command, not a library. -Commands are built into binaries and cannot be imported. -The name documentation indicates documentation for -a non-Go program in the directory. Files in package documentation -are ignored by the go command. - -As a special case, if the package list is a list of .go files from a -single directory, the command is applied to a single synthesized -package made up of exactly those files, ignoring any build constraints -in those files and ignoring any other files in the directory. - -Directory and file names that begin with "." or "_" are ignored -by the go tool, as are directories named "testdata". - `, +If the pattern is a list of Go files rather than a complete package, +the go command synthesizes a virtual package named "command-line-arguments" +containing just the given files. In most cases, it is an error +to do so (e.g. "go build main.go" or "go build *.go"). +Instead prefer to operate on complete packages (directories), +such as: "go build ." + +Package names + +Packages are identified by their import path. +Import paths for packages in the standard library use their +relative path under "$GOROOT/src". +Import paths for all other packages are a combination of their module name +and their relative directory path within the module. +Within a program, all packages must be identified by a unique import path. + +Packages also have names, declared with the "package" keyword +in a .go file, and used as the identifier when imported +by another package. By convention, the names of importable packages +match the last element of their import path, generally the name +of the directory containing the package. + +Package names do not have to be unique within a module, +but packages that share the same name can't be imported +together without one of them being aliased to a different name. + +As the go command primarily operates on directories, +all non test .go files within a directory (excluding subdirectories) +should share the same package declaration. +Test files may suffix their package declaration with "_test", +tests in these files are compiled as a separate package +and don't have access to unexported identifiers of their corresponding +package. See "go help test" and "go help testflag" for details. + +There following package names have special meanings: + +- "main" denotes the top-level package in a stand-alone executable. +"main" packages cannot be imported. + +- "documentation" indicates documentation for a non-Go program +in the directory. Files in package documentation are ignored +by the go command. + +- "_test" suffix in "*_test.go" files. These form a separate test +package that only has access to the colocated package's exported +identifiers. See "go doc testing" for details. + +For more information about import paths, see "go help importpath". +`, } var HelpImportPath = &base.Command{ UsageLine: "importpath", Short: "import path syntax", Long: ` +An import path is used to uniquely identify and locate a package. +In general, an import path denotes either a standard library package +(such as "unicode/utf8") or a package found in a module (for more +details see: 'go help modules'). -An import path (see 'go help packages') denotes a package stored in the local -file system. In general, an import path denotes either a standard package (such -as "unicode/utf8") or a package found in one of the work spaces (For more -details see: 'go help gopath'). +The standard library reserves all import paths without a dot in the +first element for its packages. See "Fully-qualified import paths" +below for choosing an import path for your module. +The following names are reserved to be used as short module names +when working locally, and in tutorials, examples, and test code. -Relative import paths +- "test" +- "example" -An import path beginning with ./ or ../ is called a relative path. -The toolchain supports relative import paths as a shortcut in two ways. +Internal packages + +Code in or below a directory named "internal" is importable only +by code that shares the same import path above the internal directory. +Here's an example directory layout of a module example.com/m: + + /home/user/modules/m/ + go.mod (declares module example.com/m) + crash/ + bang/ (go code in package bang) + b.go + foo/ (go code in package foo) + f.go + bar/ (go code in package bar) + x.go + internal/ + baz/ (go code in package baz) + z.go + quux/ (go code in package quux) + y.go -First, a relative path can be used as a shorthand on the command line. -If you are working in the directory containing the code imported as -"unicode" and want to run the tests for "unicode/utf8", you can type -"go test ./utf8" instead of needing to specify the full path. -Similarly, in the reverse situation, "go test .." will test "unicode" from -the "unicode/utf8" directory. Relative patterns are also allowed, like -"go test ./..." to test all subdirectories. See 'go help packages' for details -on the pattern syntax. -Second, if you are compiling a Go program not in a work space, -you can use a relative path in an import statement in that program -to refer to nearby code also not in a work space. -This makes it easy to experiment with small multipackage programs -outside of the usual work spaces, but such programs cannot be -installed with "go install" (there is no work space in which to install them), -so they are rebuilt from scratch each time they are built. -To avoid ambiguity, Go programs cannot use relative import paths -within a work space. +The code in z.go is imported as "example.com/m/foo/internal/baz", but that +import statement can only appear in packages with the import path prefix +"example.com/m/foo". The packages "example.com/m/foo", "example.com/m/foo/bar", and +"example.com/m/foo/quux" can all import "foo/internal/baz", but the package +"example.com/m/crash/bang" cannot. -Remote import paths +See https://go.dev/s/go14internal for details. -Certain import paths also -describe how to obtain the source code for the package using -a revision control system. +Fully-qualified import paths -A few common code hosting sites have special syntax: +A fully-qualified import path for a package not belonging to the standard library +starts with the path of the module the package to which the package belongs. +The module's path specifies where to obtain the source code for the module. +The complete import path is formed by joining the module path with the +relative directory path of a package within the module. Example: + + /home/user/modules/m/ + go.mod (declares "module example.com/m") + crash/ + bang/ (importable as "example.com/m/crash/bang") + b.go + foo/ (importable as "example.com/m/foo") + f.go + bar/ (importable as "example.com/m/foo/bar") + x.go + +As import paths without a dot in the first element are reserved by the standard library, +module paths (which form the prefix of all import paths) should start with an element +containing a dot, e.g. "github.com/user/repo", or "example.com/project". +A module path may point directly to a code hosting service, +or to a custom address that points to the code hosting service in a html meta tags. +Modules may also use the reserved names "example" for documentation +and "test" for testing. These modules cannot be fetched by the go command. + +Import paths belonging to modules hosted on common code hosting sites have special syntax: Bitbucket (Git, Mercurial) @@ -192,7 +280,7 @@ A few common code hosting sites have special syntax: import "hub.jazz.net/git/user/project" import "hub.jazz.net/git/user/project/sub/directory" -For code hosted on other servers, import paths may either be qualified +For modules hosted on other servers, import paths may either be qualified with the version control type, or the go tool can dynamically fetch the import path over https/http and discover where the code resides from a tag in the HTML. @@ -205,7 +293,6 @@ specifies the given repository, with or without the .vcs suffix, using the named version control system, and then the path inside that repository. The supported version control systems are: - Bazaar .bzr Fossil .fossil Git .git Mercurial .hg @@ -255,7 +342,7 @@ The meta tag should appear as early in the file as possible. In particular, it should appear before any raw JavaScript or CSS, to avoid confusing the go command's restricted parser. -The vcs is one of "bzr", "fossil", "git", "hg", "svn". +The vcs is one of "fossil", "git", "hg", "svn". The repo-root is the root of the version control system containing a scheme and not containing a .vcs qualifier. @@ -290,10 +377,10 @@ the go tool will verify that https://example.org/?go-get=1 contains the same met tag and then download the code from the "foo/subdir" subdirectory within the Git repository at https://code.org/r/p/exproj -Downloaded packages are stored in the module cache. -See https://golang.org/ref/mod#module-cache. +Downloaded modules are stored in the module cache. +See https://go.dev/ref/mod#module-cache. -When using modules, an additional variant of the go-import meta tag is +An additional variant of the go-import meta tag is recognized and is preferred over those listing version control systems. That variant uses "mod" as the vcs in the content value, as in: @@ -301,34 +388,8 @@ That variant uses "mod" as the vcs in the content value, as in: This tag means to fetch modules with paths beginning with example.org from the module proxy available at the URL https://code.org/moduleproxy. -See https://golang.org/ref/mod#goproxy-protocol for details about the +See https://go.dev/ref/mod#goproxy-protocol for details about the proxy protocol. - -Import path checking - -When the custom import path feature described above redirects to a -known code hosting site, each of the resulting packages has two possible -import paths, using the custom domain or the known hosting site. - -A package statement is said to have an "import comment" if it is immediately -followed (before the next newline) by a comment of one of these two forms: - - package math // import "path" - package math /* import "path" */ - -The go command will refuse to install a package with an import comment -unless it is being referred to by that import path. In this way, import comments -let package authors make sure the custom import path is used and not a -direct path to the underlying code hosting site. - -Import path checking is disabled for code found within vendor trees. -This makes it possible to copy code into alternate locations in vendor trees -without needing to update import comments. - -Import path checking is also disabled when using modules. -Import path comments are obsoleted by the go.mod file's module statement. - -See https://golang.org/s/go14customimport for details. `, } @@ -336,21 +397,43 @@ var HelpGopath = &base.Command{ UsageLine: "gopath", Short: "GOPATH environment variable", Long: ` -The Go path is used to resolve import statements. -It is implemented by and documented in the go/build package. - -The GOPATH environment variable lists places to look for Go code. -On Unix, the value is a colon-separated string. -On Windows, the value is a semicolon-separated string. -On Plan 9, the value is a list. +The GOPATH environment variable is used to change the default +location to store the module cache and installed binaries, if +not overridden by GOMODCACHE and GOBIN respectively. +Most users don't need to explicitly set GOPATH. If the environment variable is unset, GOPATH defaults to a subdirectory named "go" in the user's home directory ($HOME/go on Unix, %USERPROFILE%\go on Windows), unless that directory holds a Go distribution. Run "go env GOPATH" to see the current GOPATH. -See https://golang.org/wiki/SettingGOPATH to set a custom GOPATH. +The module cache is stored in the directory specified by +GOPATH/pkg/mod. If GOMODCACHE is set, it will be used +as the directory to store the module cache instead. + +Executables installed using 'go install' are placed in the +directory specified by GOPATH/bin or, if GOBIN is set, by GOBIN. + +GOPATH mode + +The GOPATH environment variable is also used by a legacy behavior of the +toolchain called GOPATH mode that allows some older projects, created before +modules were introduced in Go 1.11 and never updated to use modules, +to continue to build. + +GOPATH mode is enabled when modules are disabled, either when GO111MODULE=off, +or when GO111MODULE=auto, and the working directory is not in a module or workspace. + +In GOPATH mode, packages are located using the GOPATH environment variable, +which specifies a list of paths to search: +On Unix, the value is a colon-separated string. +On Windows, the value is a semicolon-separated string. +On Plan 9, the value is a list. +The first element of this list is used to set the default module cache and +binary install directory locations as described above. + +See https://go.dev/wiki/SettingGOPATH to set a custom GOPATH. Each directory listed in GOPATH must have a prescribed structure: @@ -398,50 +481,11 @@ Go searches each directory listed in GOPATH to find source code, but new packages are always downloaded into the first directory in the list. -See https://golang.org/doc/code.html for an example. +See https://go.dev/doc/code.html for an example. -GOPATH and Modules +GOPATH mode vendor directories -When using modules, GOPATH is no longer used for resolving imports. -However, it is still used to store downloaded source code (in GOPATH/pkg/mod) -and compiled commands (in GOPATH/bin). - -Internal Directories - -Code in or below a directory named "internal" is importable only -by code in the directory tree rooted at the parent of "internal". -Here's an extended version of the directory layout above: - - /home/user/go/ - src/ - crash/ - bang/ (go code in package bang) - b.go - foo/ (go code in package foo) - f.go - bar/ (go code in package bar) - x.go - internal/ - baz/ (go code in package baz) - z.go - quux/ (go code in package main) - y.go - - -The code in z.go is imported as "foo/internal/baz", but that -import statement can only appear in source files in the subtree -rooted at foo. The source files foo/f.go, foo/bar/x.go, and -foo/quux/y.go can all import "foo/internal/baz", but the source file -crash/bang/b.go cannot. - -See https://golang.org/s/go14internal for details. - -Vendor Directories - -Go 1.6 includes support for using local copies of external dependencies -to satisfy imports of those dependencies, often referred to as vendoring. - -Code below a directory named "vendor" is importable only +In GOPATH mode, code below a directory named "vendor" is importable only by code in the directory tree rooted at the parent of "vendor", and only using an import path that omits the prefix up to and including the vendor element. @@ -471,22 +515,25 @@ and a new foo/vendor/crash/bang directory added: The same visibility rules apply as for internal, but the code in z.go is imported as "baz", not as "foo/vendor/baz". -Code in vendor directories deeper in the source tree shadows +Code in GOPATH mode vendor directories deeper in the source tree shadows code in higher directories. Within the subtree rooted at foo, an import of "crash/bang" resolves to "foo/vendor/crash/bang", not the top-level "crash/bang". -Code in vendor directories is not subject to import path -checking (see 'go help importpath'). +Code in GOPATH mode vendor directories is not subject to +GOPATH mode import path checking (see 'go help importpath'). -When 'go get' checks out or updates a git repository, it now also -updates submodules. +In GOPATH mode, the default GODEBUG values built into a binary +will be the same GODEBUG values as when a module specifies +"godebug default=go1.20". To use different GODEBUG settings, the +GODEBUG environment variable must be set to override those values. +This also means that the standard library tests will not run +properly with GO111MODULE=off. -Vendor directories do not affect the placement of new repositories -being checked out for the first time by 'go get': those are always -placed in the main GOPATH, never in a vendor subtree. +See https://go.dev/s/go15vendor for details. -See https://golang.org/s/go15vendor for details. +See https://go.dev/ref/mod#vendoring for details about vendoring in +module mode. `, } @@ -514,7 +561,7 @@ General-purpose environment variables: GO111MODULE Controls whether the go command runs in module-aware mode or GOPATH mode. May be "off", "on", or "auto". - See https://golang.org/ref/mod#mod-commands. + See https://go.dev/ref/mod#mod-commands. GOARCH The architecture, or processor, for which to compile code. Examples are amd64, 386, arm, ppc64. @@ -563,15 +610,15 @@ General-purpose environment variables: Comma-separated list of glob patterns (in the syntax of Go's path.Match) of module path prefixes that should always be fetched directly or that should not be compared against the checksum database. - See https://golang.org/ref/mod#private-modules. + See https://go.dev/ref/mod#private-modules. GOPROXY - URL of Go module proxy. See https://golang.org/ref/mod#environment-variables - and https://golang.org/ref/mod#module-proxy for details. + URL of Go module proxy. See https://go.dev/ref/mod#environment-variables + and https://go.dev/ref/mod#module-proxy for details. GOROOT The root of the go tree. GOSUMDB The name of checksum database to use and optionally its public key and - URL. See https://golang.org/ref/mod#authenticating. + URL. See https://go.dev/ref/mod#authenticating. GOTMPDIR Temporary directory used by the go command and testing package. Overrides the platform-specific temporary directory such as "/tmp". @@ -639,7 +686,7 @@ Architecture-specific environment variables: GOAMD64 For GOARCH=amd64, the microarchitecture level for which to compile. Valid values are v1 (default), v2, v3, v4. - See https://golang.org/wiki/MinimumRequirements#amd64 + See https://go.dev/wiki/MinimumRequirements#amd64 GOARM For GOARCH=arm, the ARM architecture for which to compile. Valid values are 5, 6, 7. @@ -877,6 +924,10 @@ The output is voluminous but can be useful for debugging the cache. GODEBUG=gocachetest=1 causes the go command to print details of its decisions about whether to reuse a cached test result. + +The GOCACHEPROG environment variable can be used to provide an +externally managed build cache. For details see: +"go doc cmd/go/internal/cacheprog". `, } @@ -1009,6 +1060,12 @@ Naming a file dns_windows.go will cause it to be included only when building the package for Windows; similarly, math_386.s will be included only when building the package for 32-bit x86. +By convention, packages with assembly implementations may provide a go-only +version under the "purego" build constraint. This does not limit the use of +cgo (use the "cgo" build constraint) or unsafe. For example: + + //go:build purego + Go versions 1.16 and earlier used a different syntax for build constraints, with a "// +build" prefix. The gofmt command will add an equivalent //go:build constraint when encountering the older syntax. diff --git a/src/cmd/go/internal/imports/read_test.go b/src/cmd/go/internal/imports/read_test.go index 6a1a6524a116d5..b1247cc490aa51 100644 --- a/src/cmd/go/internal/imports/read_test.go +++ b/src/cmd/go/internal/imports/read_test.go @@ -146,7 +146,7 @@ func testRead(t *testing.T, tests []readTest, read func(io.Reader) ([]byte, erro } continue } - if err == nil && tt.err != "" { + if tt.err != "" { t.Errorf("#%d: success, expected %q", i, tt.err) continue } diff --git a/src/cmd/go/internal/list/list.go b/src/cmd/go/internal/list/list.go index 086a8c2ca390cb..66a51c5e4f4c2c 100644 --- a/src/cmd/go/internal/list/list.go +++ b/src/cmd/go/internal/list/list.go @@ -339,7 +339,7 @@ For more about build flags, see 'go help build'. For more about specifying packages, see 'go help packages'. -For more about modules, see https://golang.org/ref/mod. +For more about modules, see https://go.dev/ref/mod. `, } @@ -419,8 +419,14 @@ func (v *jsonFlag) needAny(fields ...string) bool { var nl = []byte{'\n'} func runList(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) + for _, arg := range args { + if arg == "" { + base.Fatalf("go: invalid package: %q", arg) + } + } + + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() if *listFmt != "" && listJson { base.Fatalf("go list -f cannot be used with -json") @@ -428,11 +434,11 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { if *listReuse != "" && !*listM { base.Fatalf("go list -reuse cannot be used without -m") } - if *listReuse != "" && modload.HasModRoot(moduleLoaderState) { + if *listReuse != "" && moduleLoader.HasModRoot() { base.Fatalf("go list -reuse cannot be used inside a module") } - work.BuildInit(moduleLoaderState) + work.BuildInit(moduleLoader) out := newTrackingWriter(os.Stdout) defer out.w.Flush() @@ -480,7 +486,7 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { fm := template.FuncMap{ "join": strings.Join, "context": context, - "module": func(path string) *modinfo.ModulePublic { return modload.ModuleInfo(moduleLoaderState, ctx, path) }, + "module": func(path string) *modinfo.ModulePublic { return modload.ModuleInfo(moduleLoader, ctx, path) }, } tmpl, err := template.New("main").Funcs(fm).Parse(*listFmt) if err != nil { @@ -497,12 +503,12 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { } } - modload.Init(moduleLoaderState) + modload.Init(moduleLoader) if *listRetracted { if cfg.BuildMod == "vendor" { base.Fatalf("go list -retracted cannot be used when vendoring is enabled") } - if !modload.Enabled(moduleLoaderState) { + if !moduleLoader.Enabled() { base.Fatalf("go list -retracted can only be used in module-aware mode") } } @@ -526,11 +532,11 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { base.Fatalf("go list -test cannot be used with -m") } - if modload.Init(moduleLoaderState); !modload.Enabled(moduleLoaderState) { + if modload.Init(moduleLoader); !moduleLoader.Enabled() { base.Fatalf("go: list -m cannot be used with GO111MODULE=off") } - modload.LoadModFile(moduleLoaderState, ctx) // Sets cfg.BuildMod as a side-effect. + modload.LoadModFile(moduleLoader, ctx) // Sets cfg.BuildMod as a side-effect. if cfg.BuildMod == "vendor" { const actionDisabledFormat = "go: can't %s using the vendor directory\n\t(Use -mod=mod or -mod=readonly to bypass.)" @@ -570,7 +576,7 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { if *listReuse != "" && len(args) == 0 { base.Fatalf("go: list -m -reuse only has an effect with module@version arguments") } - mods, err := modload.ListModules(moduleLoaderState, ctx, args, mode, *listReuse) + mods, err := modload.ListModules(moduleLoader, ctx, args, mode, *listReuse) if !*listE { for _, m := range mods { if m.Error != nil { @@ -614,7 +620,7 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { SuppressBuildInfo: !*listExport && !listJsonFields.needAny("Stale", "StaleReason"), SuppressEmbedFiles: !*listExport && !listJsonFields.needAny("EmbedFiles", "TestEmbedFiles", "XTestEmbedFiles"), } - pkgs := load.PackagesAndErrors(moduleLoaderState, ctx, pkgOpts, args) + pkgs := load.PackagesAndErrors(moduleLoader, ctx, pkgOpts, args) if !*listE { w := 0 for _, pkg := range pkgs { @@ -649,10 +655,10 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { sema.Release(1) wg.Done() } - pmain, ptest, pxtest = load.TestPackagesAndErrors(moduleLoaderState, ctx, done, pkgOpts, p, nil) + pmain, ptest, pxtest = load.TestPackagesAndErrors(moduleLoader, ctx, done, pkgOpts, p, nil) } else { var perr *load.Package - pmain, ptest, pxtest, perr = load.TestPackagesFor(moduleLoaderState, ctx, pkgOpts, p, nil) + pmain, ptest, pxtest, perr = load.TestPackagesFor(moduleLoader, ctx, pkgOpts, p, nil) if perr != nil { base.Fatalf("go: can't load test package: %s", perr.Error) } @@ -714,7 +720,7 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { // Do we need to run a build to gather information? needStale := (listJson && listJsonFields.needAny("Stale", "StaleReason")) || strings.Contains(*listFmt, ".Stale") if needStale || *listExport || *listCompiled { - b := work.NewBuilder("", moduleLoaderState.VendorDirOrEmpty) + b := work.NewBuilder("", moduleLoader.VendorDirOrEmpty) if *listE { b.AllowErrors = true } @@ -728,13 +734,13 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { b.NeedExport = *listExport b.NeedCompiledGoFiles = *listCompiled if cfg.BuildCover { - load.PrepareForCoverageBuild(moduleLoaderState, pkgs) + load.PrepareForCoverageBuild(moduleLoader, pkgs) } a := &work.Action{} // TODO: Use pkgsFilter? for _, p := range pkgs { if len(p.GoFiles)+len(p.CgoFiles) > 0 { - a.Deps = append(a.Deps, b.AutoAction(moduleLoaderState, work.ModeInstall, work.ModeInstall, p)) + a.Deps = append(a.Deps, b.AutoAction(moduleLoader, work.ModeInstall, work.ModeInstall, p)) } } b.Do(ctx, a) @@ -742,8 +748,8 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { for _, p := range pkgs { // Show vendor-expanded paths in listing - p.TestImports = p.Resolve(moduleLoaderState, p.TestImports) - p.XTestImports = p.Resolve(moduleLoaderState, p.XTestImports) + p.TestImports = p.Resolve(moduleLoader, p.TestImports) + p.XTestImports = p.Resolve(moduleLoader, p.XTestImports) p.DepOnly = !cmdline[p] if *listCompiled { @@ -851,7 +857,7 @@ func runList(ctx context.Context, cmd *base.Command, args []string) { if *listRetracted { mode |= modload.ListRetracted } - rmods, err := modload.ListModules(moduleLoaderState, ctx, args, mode, *listReuse) + rmods, err := modload.ListModules(moduleLoader, ctx, args, mode, *listReuse) if err != nil && !*listE { base.Error(err) } diff --git a/src/cmd/go/internal/load/flag.go b/src/cmd/go/internal/load/flag.go index a9188db0fd2828..f0dc99b07af683 100644 --- a/src/cmd/go/internal/load/flag.go +++ b/src/cmd/go/internal/load/flag.go @@ -30,7 +30,7 @@ type PerPackageFlag struct { // A ppfValue is a single = per-package flag value. type ppfValue struct { - match func(*modload.State, *Package) bool // compiled pattern + match func(*modload.Loader, *Package) bool // compiled pattern flags []string } @@ -43,7 +43,7 @@ func (f *PerPackageFlag) Set(v string) error { func (f *PerPackageFlag) set(v, cwd string) error { f.raw = v f.present = true - match := func(_ *modload.State, p *Package) bool { return p.Internal.CmdlinePkg || p.Internal.CmdlineFiles } // default predicate with no pattern + match := func(_ *modload.Loader, p *Package) bool { return p.Internal.CmdlinePkg || p.Internal.CmdlineFiles } // default predicate with no pattern // For backwards compatibility with earlier flag splitting, ignore spaces around flags. v = strings.TrimSpace(v) if v == "" { @@ -89,7 +89,7 @@ func (f *PerPackageFlag) Present() bool { // // The module loader state is used by the matcher to know if certain // patterns match packages within the state's MainModules. -func (f *PerPackageFlag) For(s *modload.State, p *Package) []string { +func (f *PerPackageFlag) For(s *modload.Loader, p *Package) []string { flags := []string{} for _, v := range f.values { if v.match(s, p) { diff --git a/src/cmd/go/internal/load/flag_test.go b/src/cmd/go/internal/load/flag_test.go index 0c2363cb79025f..13d195aa8f7ad9 100644 --- a/src/cmd/go/internal/load/flag_test.go +++ b/src/cmd/go/internal/load/flag_test.go @@ -126,7 +126,7 @@ func TestPerPackageFlag(t *testing.T) { } for _, p := range tt.pkgs { dir := nativeDir(p.dir) - flags := ppFlags.For(modload.NewState(), &Package{PackagePublic: PackagePublic{ImportPath: p.path, Dir: dir}, Internal: PackageInternal{CmdlinePkg: p.cmdline}}) + flags := ppFlags.For(modload.NewLoader(), &Package{PackagePublic: PackagePublic{ImportPath: p.path, Dir: dir}, Internal: PackageInternal{CmdlinePkg: p.cmdline}}) if !reflect.DeepEqual(flags, p.flags) { t.Errorf("For(%v, %v, %v) = %v, want %v", p.path, dir, p.cmdline, flags, p.flags) } diff --git a/src/cmd/go/internal/load/godebug.go b/src/cmd/go/internal/load/godebug.go index 817cc4faebf7b4..9f8182b82aad03 100644 --- a/src/cmd/go/internal/load/godebug.go +++ b/src/cmd/go/internal/load/godebug.go @@ -42,38 +42,44 @@ func ParseGoDebug(text string) (key, value string, err error) { return k, v, nil } +func defaultGODEBUGGoVersion(ld *modload.Loader, p *Package) string { + if !ld.Enabled() { + // GOPATH mode. Use Go 1.20. + return "1.20" + } + if ld.RootMode == modload.NoRoot && p.Module != nil { + // This is go install pkg@version or go run pkg@version. + // Use the Go version from the package. + // If there isn't one, then assume Go 1.20, the last + // version before GODEBUGs were introduced (#56986). + if goVersion := p.Module.GoVersion; goVersion != "" { + return goVersion + } + return "1.20" + } + return ld.MainModules.GoVersion(ld) +} + // defaultGODEBUG returns the default GODEBUG setting for the main package p. // When building a test binary, directives, testDirectives, and xtestDirectives // list additional directives from the package under test. -func defaultGODEBUG(loaderstate *modload.State, p *Package, directives, testDirectives, xtestDirectives []build.Directive) string { +func defaultGODEBUG(ld *modload.Loader, p *Package, directives, testDirectives, xtestDirectives []build.Directive) string { if p.Name != "main" { return "" } - goVersion := loaderstate.MainModules.GoVersion(loaderstate) - if loaderstate.RootMode == modload.NoRoot && p.Module != nil { - // This is go install pkg@version or go run pkg@version. - // Use the Go version from the package. - // If there isn't one, then assume Go 1.20, - // the last version before GODEBUGs were introduced. - goVersion = p.Module.GoVersion - if goVersion == "" { - goVersion = "1.20" - } - } + + goVersion := defaultGODEBUGGoVersion(ld, p) var m map[string]string // If GOFIPS140 is set to anything but "off", // default to GODEBUG=fips140=on. if fips140.Enabled() { - if m == nil { - m = make(map[string]string) - } - m["fips140"] = "on" + m = map[string]string{"fips140": "on"} } // Add directives from main module go.mod. - for _, g := range loaderstate.MainModules.Godebugs(loaderstate) { + for _, g := range ld.MainModules.Godebugs(ld) { if m == nil { m = make(map[string]string) } diff --git a/src/cmd/go/internal/load/pkg.go b/src/cmd/go/internal/load/pkg.go index 3b8bbdc91b8191..9ccbce5f567235 100644 --- a/src/cmd/go/internal/load/pkg.go +++ b/src/cmd/go/internal/load/pkg.go @@ -7,7 +7,6 @@ package load import ( "bytes" - "cmd/internal/objabi" "context" "encoding/json" "errors" @@ -31,6 +30,8 @@ import ( "unicode" "unicode/utf8" + "cmd/internal/objabi" + "cmd/go/internal/base" "cmd/go/internal/cfg" "cmd/go/internal/fips140" @@ -233,6 +234,7 @@ type PackageInternal struct { Cover CoverSetup // coverage mode and other setup info of -cover is being applied to this package OmitDebug bool // tell linker not to write debug information GobinSubdir bool // install target would be subdir of GOBIN + InternalImportOk bool // this package may be imported even though it is internal BuildInfo *debug.BuildInfo // add this info to package main TestmainGo *[]byte // content for _testmain.go Embed map[string][]string // //go:embed comment mapping @@ -355,7 +357,7 @@ func (p *Package) setLoadPackageDataError(err error, path string, stk *ImportSta // can produce better error messages if it starts with the original paths. // The initial load of p loads all the non-test imports and rewrites // the vendored paths, so nothing should ever call p.vendored(p.Imports). -func (p *Package) Resolve(s *modload.State, imports []string) []string { +func (p *Package) Resolve(s *modload.Loader, imports []string) []string { if len(imports) > 0 && len(p.Imports) > 0 && &imports[0] == &p.Imports[0] { panic("internal error: p.Resolve(p.Imports) called") } @@ -632,8 +634,18 @@ func (sp *ImportStack) shorterThan(t []string) bool { // packageCache is a lookup cache for LoadImport, // so that if we look up a package multiple times // we return the same pointer each time. +// +// TODO: associate the packageCache with the module loader state, so that +// different module loaders use different caches. var packageCache = map[string]*Package{} +// ClearPackageCache clears the package cache. +// It cannot be used concurrently with calls to LoadImport or other functions +// that use packageCache without synchronization. +func ClearPackageCache() { + clear(packageCache) +} + // dirToImportPath returns the pseudo-import path we use for a package // outside the Go path. It begins with _/ and then contains the full path // to the directory. If the package lives in c:\home\gopher\my\pkg then @@ -683,11 +695,14 @@ const ( // cmdlinePkgLiteral is for a package mentioned on the command line // without using any wildcards or meta-patterns. cmdlinePkgLiteral + + // allow simd/internal/bridge + allowSimdInternalBridge ) // LoadPackage does Load import, but without a parent package load context -func LoadPackage(loaderstate *modload.State, ctx context.Context, opts PackageOpts, path, srcDir string, stk *ImportStack, importPos []token.Position, mode int) *Package { - p, err := loadImport(loaderstate, ctx, opts, nil, path, srcDir, nil, stk, importPos, mode) +func LoadPackage(ld *modload.Loader, ctx context.Context, opts PackageOpts, path, srcDir string, stk *ImportStack, importPos []token.Position, mode int) *Package { + p, err := loadImport(ld, ctx, opts, nil, path, srcDir, nil, stk, importPos, mode) if err != nil { base.Fatalf("internal error: loadImport of %q with nil parent returned an error", path) } @@ -703,7 +718,7 @@ func LoadPackage(loaderstate *modload.State, ctx context.Context, opts PackageOp // The returned PackageError, if any, describes why parent is not allowed // to import the named package, with the error referring to importPos. // The PackageError can only be non-nil when parent is not nil. -func loadImport(loaderstate *modload.State, ctx context.Context, opts PackageOpts, pre *preload, path, srcDir string, parent *Package, stk *ImportStack, importPos []token.Position, mode int) (*Package, *PackageError) { +func loadImport(ld *modload.Loader, ctx context.Context, opts PackageOpts, pre *preload, path, srcDir string, parent *Package, stk *ImportStack, importPos []token.Position, mode int) (*Package, *PackageError) { ctx, span := trace.StartSpan(ctx, "modload.loadImport "+path) defer span.Done() @@ -718,9 +733,9 @@ func loadImport(loaderstate *modload.State, ctx context.Context, opts PackageOpt parentRoot = parent.Root parentIsStd = parent.Standard } - bp, loaded, err := loadPackageData(loaderstate, ctx, path, parentPath, srcDir, parentRoot, parentIsStd, mode) + bp, loaded, err := loadPackageData(ld, ctx, path, parentPath, srcDir, parentRoot, parentIsStd, mode) if loaded && pre != nil && !opts.IgnoreImports { - pre.preloadImports(loaderstate, ctx, opts, bp.Imports, bp) + pre.preloadImports(ld, ctx, opts, bp.Imports, bp) } if bp == nil { p := &Package{ @@ -741,6 +756,7 @@ func loadImport(loaderstate *modload.State, ctx context.Context, opts PackageOpt defer stk.Pop() } p.setLoadPackageDataError(err, path, stk, nil) + setToolFlags(ld, p) return p, nil } @@ -767,11 +783,12 @@ func loadImport(loaderstate *modload.State, ctx context.Context, opts PackageOpt packageCache[importPath] = p setCmdline(p) + setToolFlags(ld, p) // Load package. // loadPackageData may return bp != nil even if an error occurs, // in order to return partial information. - p.load(loaderstate, ctx, opts, path, stk, importPos, bp, err) + p.load(ld, ctx, opts, path, stk, importPos, bp, err) if !cfg.ModulesEnabled && path != cleanImport(path) { p.Error = &PackageError{ @@ -783,10 +800,12 @@ func loadImport(loaderstate *modload.State, ctx context.Context, opts PackageOpt } } - // Checked on every import because the rules depend on the code doing the importing. - if perr := disallowInternal(loaderstate, ctx, srcDir, parent, parentPath, p, stk); perr != nil { - perr.setPos(importPos) - return p, perr + if mode&allowSimdInternalBridge == 0 || path != SimdBridgePkg { // Special case for just this import. + // Checked on every import because the rules depend on the code doing the importing. + if perr := disallowInternal(ld, ctx, srcDir, parent, parentPath, p, stk); perr != nil { + perr.setPos(importPos) + return p, perr + } } if mode&ResolveImport != 0 { if perr := disallowVendor(srcDir, path, parentPath, p, stk); perr != nil { @@ -838,7 +857,7 @@ func extractFirstImport(importPos []token.Position) *token.Position { // // loadPackageData returns a boolean, loaded, which is true if this is the // first time the package was loaded. Callers may preload imports in this case. -func loadPackageData(loaderstate *modload.State, ctx context.Context, path, parentPath, parentDir, parentRoot string, parentIsStd bool, mode int) (bp *build.Package, loaded bool, err error) { +func loadPackageData(ld *modload.Loader, ctx context.Context, path, parentPath, parentDir, parentRoot string, parentIsStd bool, mode int) (bp *build.Package, loaded bool, err error) { ctx, span := trace.StartSpan(ctx, "load.loadPackageData "+path) defer span.Done() @@ -883,7 +902,7 @@ func loadPackageData(loaderstate *modload.State, ctx context.Context, path, pare r.path = newPath r.dir = dir } else if cfg.ModulesEnabled { - r.dir, r.path, r.err = modload.Lookup(loaderstate, parentPath, parentIsStd, path) + r.dir, r.path, r.err = modload.Lookup(ld, parentPath, parentIsStd, path) } else if build.IsLocalImport(path) { r.dir = filepath.Join(parentDir, path) r.path = dirToImportPath(r.dir) @@ -892,7 +911,7 @@ func loadPackageData(loaderstate *modload.State, ctx context.Context, path, pare // find out the key to use in packageCache without the // overhead of repeated calls to buildContext.Import. // The code is also needed in a few other places anyway. - r.path = resolveImportPath(loaderstate, path, parentPath, parentDir, parentRoot, parentIsStd) + r.path = resolveImportPath(ld, path, parentPath, parentDir, parentRoot, parentIsStd) } else if mode&ResolveModule != 0 { r.path = moduleImportPath(path, parentPath, parentDir, parentRoot) } @@ -921,11 +940,11 @@ func loadPackageData(loaderstate *modload.State, ctx context.Context, path, pare } else { buildContext.GOPATH = "" // Clear GOPATH so packages are imported as pure module packages } - modroot := modload.PackageModRoot(loaderstate, ctx, r.path) - if modroot == "" && str.HasPathPrefix(r.dir, cfg.GOROOTsrc) { + modroot := modload.PackageModRoot(ld, ctx, r.path) + if modroot == "" && str.HasFilePathPrefix(r.dir, cfg.GOROOTsrc) { modroot = cfg.GOROOTsrc gorootSrcCmd := filepath.Join(cfg.GOROOTsrc, "cmd") - if str.HasPathPrefix(r.dir, gorootSrcCmd) { + if str.HasFilePathPrefix(r.dir, gorootSrcCmd) { modroot = gorootSrcCmd } } @@ -942,7 +961,7 @@ func loadPackageData(loaderstate *modload.State, ctx context.Context, path, pare if cfg.ModulesEnabled { // Override data.p.Root, since ImportDir sets it to $GOPATH, if // the module is inside $GOPATH/src. - if info := modload.PackageModuleInfo(loaderstate, ctx, path); info != nil { + if info := modload.PackageModuleInfo(ld, ctx, path); info != nil { data.p.Root = info.Dir } } @@ -989,10 +1008,29 @@ func loadPackageData(loaderstate *modload.State, ctx context.Context, path, pare if cfg.GOBIN != "" { data.p.BinDir = cfg.GOBIN } else if cfg.ModulesEnabled { - data.p.BinDir = modload.BinDir(loaderstate) + data.p.BinDir = modload.BinDir(ld) } } + // For FIPS snapshot packages, set up the proper install paths. + // When fips140.ResolveImport resolved this import, the package + // was loaded via ImportDir which doesn't set PkgTargetRoot/PkgObj + // since the source directory is not under GOROOT. + // We set these here so that FIPS packages can be installed like + // regular standard library packages when GODEBUG=installgoroot=all. + // Note: We don't change Root because it's used elsewhere (e.g., vendor resolution) + // and must point to the actual source directory's root. + if fips140.Snapshot() && r.dir != "" && str.HasFilePathPrefix(r.dir, fips140.Dir()) { + // Compute PkgTargetRoot and PkgObj for proper installation. + suffix := "" + if cfg.BuildContext.InstallSuffix != "" { + suffix = "_" + cfg.BuildContext.InstallSuffix + } + pkgtargetroot := "pkg/" + cfg.BuildContext.GOOS + "_" + cfg.BuildContext.GOARCH + suffix + data.p.PkgTargetRoot = filepath.Join(cfg.GOROOT, pkgtargetroot) + data.p.PkgObj = filepath.Join(cfg.GOROOT, pkgtargetroot, data.p.ImportPath+".a") + } + if !cfg.ModulesEnabled && data.err == nil && data.p.ImportComment != "" && data.p.ImportComment != path && !strings.Contains(path, "/vendor/") && !strings.HasPrefix(path, "vendor/") { @@ -1068,7 +1106,7 @@ func newPreload() *preload { // preloadMatches loads data for package paths matched by patterns. // When preloadMatches returns, some packages may not be loaded yet, but // loadPackageData and loadImport are always safe to call. -func (pre *preload) preloadMatches(loaderstate *modload.State, ctx context.Context, opts PackageOpts, matches []*search.Match) { +func (pre *preload) preloadMatches(ld *modload.Loader, ctx context.Context, opts PackageOpts, matches []*search.Match) { for _, m := range matches { for _, pkg := range m.Pkgs { select { @@ -1077,10 +1115,10 @@ func (pre *preload) preloadMatches(loaderstate *modload.State, ctx context.Conte case pre.sema <- struct{}{}: go func(pkg string) { mode := 0 // don't use vendoring or module import resolution - bp, loaded, err := loadPackageData(loaderstate, ctx, pkg, "", base.Cwd(), "", false, mode) + bp, loaded, err := loadPackageData(ld, ctx, pkg, "", base.Cwd(), "", false, mode) <-pre.sema if bp != nil && loaded && err == nil && !opts.IgnoreImports { - pre.preloadImports(loaderstate, ctx, opts, bp.Imports, bp) + pre.preloadImports(ld, ctx, opts, bp.Imports, bp) } }(pkg) } @@ -1091,7 +1129,7 @@ func (pre *preload) preloadMatches(loaderstate *modload.State, ctx context.Conte // preloadImports queues a list of imports for preloading. // When preloadImports returns, some packages may not be loaded yet, // but loadPackageData and loadImport are always safe to call. -func (pre *preload) preloadImports(loaderstate *modload.State, ctx context.Context, opts PackageOpts, imports []string, parent *build.Package) { +func (pre *preload) preloadImports(ld *modload.Loader, ctx context.Context, opts PackageOpts, imports []string, parent *build.Package) { parentIsStd := parent.Goroot && parent.ImportPath != "" && search.IsStandardImportPath(parent.ImportPath) for _, path := range imports { if path == "C" || path == "unsafe" { @@ -1102,10 +1140,10 @@ func (pre *preload) preloadImports(loaderstate *modload.State, ctx context.Conte return case pre.sema <- struct{}{}: go func(path string) { - bp, loaded, err := loadPackageData(loaderstate, ctx, path, parent.ImportPath, parent.Dir, parent.Root, parentIsStd, ResolveImport) + bp, loaded, err := loadPackageData(ld, ctx, path, parent.ImportPath, parent.Dir, parent.Root, parentIsStd, ResolveImport) <-pre.sema if bp != nil && loaded && err == nil && !opts.IgnoreImports { - pre.preloadImports(loaderstate, ctx, opts, bp.Imports, bp) + pre.preloadImports(ld, ctx, opts, bp.Imports, bp) } }(path) } @@ -1151,7 +1189,7 @@ func isDir(path string) bool { // First, there is Go 1.5 vendoring (golang.org/s/go15vendor). // If vendor expansion doesn't trigger, then the path is also subject to // Go 1.11 module legacy conversion (golang.org/issue/25069). -func ResolveImportPath(s *modload.State, parent *Package, path string) (found string) { +func ResolveImportPath(s *modload.Loader, parent *Package, path string) (found string) { var parentPath, parentDir, parentRoot string parentIsStd := false if parent != nil { @@ -1163,7 +1201,7 @@ func ResolveImportPath(s *modload.State, parent *Package, path string) (found st return resolveImportPath(s, path, parentPath, parentDir, parentRoot, parentIsStd) } -func resolveImportPath(s *modload.State, path, parentPath, parentDir, parentRoot string, parentIsStd bool) (found string) { +func resolveImportPath(s *modload.Loader, path, parentPath, parentDir, parentRoot string, parentIsStd bool) (found string) { if cfg.ModulesEnabled { if _, p, e := modload.Lookup(s, parentPath, parentIsStd, path); e == nil { return p @@ -1463,7 +1501,7 @@ func reusePackage(p *Package, stk *ImportStack) *Package { // is allowed to import p. // If the import is allowed, disallowInternal returns the original package p. // If not, it returns a new package containing just an appropriate error. -func disallowInternal(loaderstate *modload.State, ctx context.Context, srcDir string, importer *Package, importerPath string, p *Package, stk *ImportStack) *PackageError { +func disallowInternal(ld *modload.Loader, ctx context.Context, srcDir string, importer *Package, importerPath string, p *Package, stk *ImportStack) *PackageError { // golang.org/s/go14internal: // An import of a path containing the element “internal” // is disallowed if the importing code is outside the tree @@ -1552,7 +1590,7 @@ func disallowInternal(loaderstate *modload.State, ctx context.Context, srcDir st // directory containing them. // If the directory is outside the main modules, this will resolve to ".", // which is not a prefix of any valid module. - importerPath, _ = loaderstate.MainModules.DirImportPath(loaderstate, ctx, importer.Dir) + importerPath, _ = ld.MainModules.DirImportPath(ld, ctx, importer.Dir) } parentOfInternal := p.ImportPath[:i] if str.HasPathPrefix(importerPath, parentOfInternal) { @@ -1768,10 +1806,29 @@ func (p *Package) DefaultExecName() string { return p.exeFromImportPath() } +// The package used for rewriting "simd" +const SimdBridgePkg = "simd/internal/bridge" + +// hasSimd encodes the conditions under which the presence/absence of +// imports of "simd" is interesting, i.e., if there is intrinsic +// support, and hence some rewriting of AST to use the intrinsics. +// This is used for both build and test (and perhaps in other contexts to +// be discovered later). +func hasSimd(imports []string) (hasSimd bool) { + if cfg.BuildContext.GOARCH == "wasm" || cfg.BuildContext.GOARCH == "amd64" || cfg.BuildContext.GOARCH == "arm64" { + for _, imp := range imports { + if imp == "simd" { + hasSimd = true + } + } + } + return +} + // load populates p using information from bp, err, which should // be the result of calling build.Context.Import. // stk contains the import stack, not including path itself. -func (p *Package) load(loaderstate *modload.State, ctx context.Context, opts PackageOpts, path string, stk *ImportStack, importPos []token.Position, bp *build.Package, err error) { +func (p *Package) load(ld *modload.Loader, ctx context.Context, opts PackageOpts, path string, stk *ImportStack, importPos []token.Position, bp *build.Package, err error) { p.copyBuild(opts, bp) // The localPrefix is the path we interpret ./ imports relative to, @@ -1835,7 +1892,7 @@ func (p *Package) load(loaderstate *modload.State, ctx context.Context, opts Pac elem = full } if p.Internal.Build.BinDir == "" && cfg.ModulesEnabled { - p.Internal.Build.BinDir = modload.BinDir(loaderstate) + p.Internal.Build.BinDir = modload.BinDir(ld) } if p.Internal.Build.BinDir != "" { // Install to GOBIN or bin of GOPATH entry. @@ -1907,6 +1964,12 @@ func (p *Package) load(loaderstate *modload.State, ctx context.Context, opts Pac } } + allowInternalSimdImport := 0 + if hasSimd := hasSimd(p.Imports); hasSimd { + addImport(SimdBridgePkg, true) + allowInternalSimdImport = allowSimdInternalBridge + } + if !opts.IgnoreImports { // Cgo translation adds imports of "unsafe", "runtime/cgo" and "syscall", // except for certain packages, to avoid circular dependencies. @@ -1935,7 +1998,7 @@ func (p *Package) load(loaderstate *modload.State, ctx context.Context, opts Pac // The linker loads implicit dependencies. if p.Name == "main" && !p.Internal.ForceLibrary { - ldDeps, err := LinkerDeps(loaderstate, p) + ldDeps, err := LinkerDeps(ld, p) if err != nil { setError(err) return @@ -1973,9 +2036,9 @@ func (p *Package) load(loaderstate *modload.State, ctx context.Context, opts Pac pkgPath = "command-line-arguments" } if cfg.ModulesEnabled { - p.Module = modload.PackageModuleInfo(loaderstate, ctx, pkgPath) + p.Module = modload.PackageModuleInfo(ld, ctx, pkgPath) } - p.DefaultGODEBUG = defaultGODEBUG(loaderstate, p, nil, nil, nil) + p.DefaultGODEBUG = defaultGODEBUG(ld, p, nil, nil, nil) if !opts.SuppressEmbedFiles { p.EmbedFiles, p.Internal.Embed, err = resolveEmbed(p.Dir, p.EmbedPatterns) @@ -2026,7 +2089,7 @@ func (p *Package) load(loaderstate *modload.State, ctx context.Context, opts Pac if path == "C" { continue } - p1, err := loadImport(loaderstate, ctx, opts, nil, path, p.Dir, p, stk, p.Internal.Build.ImportPos[path], ResolveImport) + p1, err := loadImport(ld, ctx, opts, nil, path, p.Dir, p, stk, p.Internal.Build.ImportPos[path], ResolveImport|allowInternalSimdImport) if err != nil && p.Error == nil { p.Error = err p.Incomplete = true @@ -2049,7 +2112,7 @@ func (p *Package) load(loaderstate *modload.State, ctx context.Context, opts Pac // Consider starting this as a background goroutine and retrieving the result // asynchronously when we're actually ready to build the package, or when we // actually need to evaluate whether the package's metadata is stale. - p.setBuildInfo(ctx, opts.AutoVCS) + p.setBuildInfo(ctx, ld.Fetcher(), opts.AutoVCS) } // If cgo is not enabled, ignore cgo supporting sources @@ -2298,6 +2361,8 @@ func isBadEmbedName(name string) bool { case "": return true // Version control directories won't be present in module. + // TODO(matloob): Keep .bzr for now since we previously disallowed it + // even though bzr is no longer supported. case ".bzr", ".hg", ".git", ".svn": return true } @@ -2322,7 +2387,7 @@ func appendBuildSetting(info *debug.BuildInfo, key, value string) { // // Note that the GoVersion field is not set here to avoid encoding it twice. // It is stored separately in the binary, mostly for historical reasons. -func (p *Package) setBuildInfo(ctx context.Context, autoVCS bool) { +func (p *Package) setBuildInfo(ctx context.Context, f *modfetch.Fetcher, autoVCS bool) { setPkgErrorf := func(format string, args ...any) { if p.Error == nil { p.Error = &PackageError{Err: fmt.Errorf(format, args...)} @@ -2530,7 +2595,7 @@ func (p *Package) setBuildInfo(ctx context.Context, autoVCS bool) { } if cfg.BuildBuildvcs == "auto" && vcsCmd != nil && vcsCmd.Cmd != "" { if _, err := pathcache.LookPath(vcsCmd.Cmd); err != nil { - // We fould a repository, but the required VCS tool is not present. + // We found a repository, but the required VCS tool is not present. // "-buildvcs=auto" means that we should silently drop the VCS metadata. goto omitVCS } @@ -2594,7 +2659,7 @@ func (p *Package) setBuildInfo(ctx context.Context, autoVCS bool) { if !ok { goto omitVCS } - repo := modfetch.LookupLocal(ctx, codeRoot, p.Module.Path, repoDir) + repo := f.LookupLocal(ctx, codeRoot, p.Module.Path, repoDir) revInfo, err := repo.Stat(ctx, st.Revision) if err != nil { goto omitVCS @@ -2635,7 +2700,7 @@ func SafeArg(name string) bool { } // LinkerDeps returns the list of linker-induced dependencies for main package p. -func LinkerDeps(s *modload.State, p *Package) ([]string, error) { +func LinkerDeps(s *modload.Loader, p *Package) ([]string, error) { // Everything links runtime. deps := []string{"runtime"} @@ -2673,7 +2738,7 @@ func LinkerDeps(s *modload.State, p *Package) ([]string, error) { // externalLinkingReason reports the reason external linking is required // even for programs that do not use cgo, or the empty string if external // linking is not required. -func externalLinkingReason(s *modload.State, p *Package) (what string) { +func externalLinkingReason(s *modload.Loader, p *Package) (what string) { // Some targets must use external linking even inside GOROOT. if platform.MustLinkExternal(cfg.Goos, cfg.Goarch, false) { return cfg.Goos + "/" + cfg.Goarch @@ -2797,7 +2862,7 @@ func PackageList(roots []*Package) []*Package { // TestPackageList returns the list of packages in the dag rooted at roots // as visited in a depth-first post-order traversal, including the test // imports of the roots. This ignores errors in test packages. -func TestPackageList(loaderstate *modload.State, ctx context.Context, opts PackageOpts, roots []*Package) []*Package { +func TestPackageList(ld *modload.Loader, ctx context.Context, opts PackageOpts, roots []*Package) []*Package { seen := map[*Package]bool{} all := []*Package{} var walk func(*Package) @@ -2813,7 +2878,7 @@ func TestPackageList(loaderstate *modload.State, ctx context.Context, opts Packa } walkTest := func(root *Package, path string) { var stk ImportStack - p1, err := loadImport(loaderstate, ctx, opts, nil, path, root.Dir, root, &stk, root.Internal.Build.TestImportPos[path], ResolveImport) + p1, err := loadImport(ld, ctx, opts, nil, path, root.Dir, root, &stk, root.Internal.Build.TestImportPos[path], ResolveImport) if err != nil && root.Error == nil { // Assign error importing the package to the importer. root.Error = err @@ -2835,22 +2900,11 @@ func TestPackageList(loaderstate *modload.State, ctx context.Context, opts Packa return all } -// LoadImportWithFlags loads the package with the given import path and -// sets tool flags on that package. This function is useful loading implicit -// dependencies (like sync/atomic for coverage). -// TODO(jayconrod): delete this function and set flags automatically -// in LoadImport instead. -func LoadImportWithFlags(loaderstate *modload.State, path, srcDir string, parent *Package, stk *ImportStack, importPos []token.Position, mode int) (*Package, *PackageError) { - p, err := loadImport(loaderstate, context.TODO(), PackageOpts{}, nil, path, srcDir, parent, stk, importPos, mode) - setToolFlags(loaderstate, p) - return p, err -} - // LoadPackageWithFlags is the same as LoadImportWithFlags but without a parent. // It's then guaranteed to not return an error -func LoadPackageWithFlags(loaderstate *modload.State, path, srcDir string, stk *ImportStack, importPos []token.Position, mode int) *Package { - p := LoadPackage(loaderstate, context.TODO(), PackageOpts{}, path, srcDir, stk, importPos, mode) - setToolFlags(loaderstate, p) +func LoadPackageWithFlags(ld *modload.Loader, path, srcDir string, stk *ImportStack, importPos []token.Position, mode int) *Package { + p := LoadPackage(ld, context.TODO(), PackageOpts{}, path, srcDir, stk, importPos, mode) + setToolFlags(ld, p) return p } @@ -2899,7 +2953,7 @@ type PackageOpts struct { // // To obtain a flat list of packages, use PackageList. // To report errors loading packages, use ReportPackageErrors. -func PackagesAndErrors(loaderstate *modload.State, ctx context.Context, opts PackageOpts, patterns []string) []*Package { +func PackagesAndErrors(ld *modload.Loader, ctx context.Context, opts PackageOpts, patterns []string) []*Package { ctx, span := trace.StartSpan(ctx, "load.PackagesAndErrors") defer span.Done() @@ -2911,7 +2965,7 @@ func PackagesAndErrors(loaderstate *modload.State, ctx context.Context, opts Pac // We need to test whether the path is an actual Go file and not a // package path or pattern ending in '.go' (see golang.org/issue/34653). if fi, err := fsys.Stat(p); err == nil && !fi.IsDir() { - pkgs := []*Package{GoFilesPackage(loaderstate, ctx, opts, patterns)} + pkgs := []*Package{GoFilesPackage(ld, ctx, opts, patterns)} setPGOProfilePath(pkgs) return pkgs } @@ -2919,13 +2973,13 @@ func PackagesAndErrors(loaderstate *modload.State, ctx context.Context, opts Pac } var matches []*search.Match - if modload.Init(loaderstate); cfg.ModulesEnabled { + if modload.Init(ld); cfg.ModulesEnabled { modOpts := modload.PackageOpts{ ResolveMissingImports: true, LoadTests: opts.ModResolveTests, SilencePackageErrors: true, } - matches, _ = modload.LoadPackages(loaderstate, ctx, modOpts, patterns...) + matches, _ = modload.LoadPackages(ld, ctx, modOpts, patterns...) } else { matches = search.ImportPaths(patterns) } @@ -2938,7 +2992,7 @@ func PackagesAndErrors(loaderstate *modload.State, ctx context.Context, opts Pac pre := newPreload() defer pre.flush() - pre.preloadMatches(loaderstate, ctx, opts, matches) + pre.preloadMatches(ld, ctx, opts, matches) for _, m := range matches { for _, pkg := range m.Pkgs { @@ -2952,7 +3006,7 @@ func PackagesAndErrors(loaderstate *modload.State, ctx context.Context, opts Pac // a literal and also a non-literal pattern. mode |= cmdlinePkgLiteral } - p, perr := loadImport(loaderstate, ctx, opts, pre, pkg, base.Cwd(), nil, &stk, nil, mode) + p, perr := loadImport(ld, ctx, opts, pre, pkg, base.Cwd(), nil, &stk, nil, mode) if perr != nil { base.Fatalf("internal error: loadImport of %q with nil parent returned an error", pkg) } @@ -2992,7 +3046,7 @@ func PackagesAndErrors(loaderstate *modload.State, ctx context.Context, opts Pac // compute the effective flags for all loaded packages // (not just the ones matching the patterns but also // their dependencies). - setToolFlags(loaderstate, pkgs...) + setToolFlags(ld, pkgs...) setPGOProfilePath(pkgs) @@ -3231,20 +3285,20 @@ func (e *mainPackageError) ImportPath() string { return e.importPath } -func setToolFlags(loaderstate *modload.State, pkgs ...*Package) { +func setToolFlags(ld *modload.Loader, pkgs ...*Package) { for _, p := range PackageList(pkgs) { - p.Internal.Asmflags = BuildAsmflags.For(loaderstate, p) - p.Internal.Gcflags = BuildGcflags.For(loaderstate, p) - p.Internal.Ldflags = BuildLdflags.For(loaderstate, p) - p.Internal.Gccgoflags = BuildGccgoflags.For(loaderstate, p) + p.Internal.Asmflags = BuildAsmflags.For(ld, p) + p.Internal.Gcflags = BuildGcflags.For(ld, p) + p.Internal.Ldflags = BuildLdflags.For(ld, p) + p.Internal.Gccgoflags = BuildGccgoflags.For(ld, p) } } // GoFilesPackage creates a package for building a collection of Go files // (typically named on the command line). The target is named p.a for // package p or named after the first Go file for package main. -func GoFilesPackage(loaderstate *modload.State, ctx context.Context, opts PackageOpts, gofiles []string) *Package { - modload.Init(loaderstate) +func GoFilesPackage(ld *modload.Loader, ctx context.Context, opts PackageOpts, gofiles []string) *Package { + modload.Init(ld) for _, f := range gofiles { if !strings.HasSuffix(f, ".go") { @@ -3289,7 +3343,7 @@ func GoFilesPackage(loaderstate *modload.State, ctx context.Context, opts Packag ctxt.ReadDir = func(string) ([]fs.FileInfo, error) { return dirent, nil } if cfg.ModulesEnabled { - modload.ImportFromFiles(loaderstate, ctx, gofiles) + modload.ImportFromFiles(ld, ctx, gofiles) } var err error @@ -3305,7 +3359,7 @@ func GoFilesPackage(loaderstate *modload.State, ctx context.Context, opts Packag pkg := new(Package) pkg.Internal.Local = true pkg.Internal.CmdlineFiles = true - pkg.load(loaderstate, ctx, opts, "command-line-arguments", &stk, nil, bp, err) + pkg.load(ld, ctx, opts, "command-line-arguments", &stk, nil, bp, err) if !cfg.ModulesEnabled { pkg.Internal.LocalPrefix = dirToImportPath(dir) } @@ -3319,7 +3373,7 @@ func GoFilesPackage(loaderstate *modload.State, ctx context.Context, opts Packag if cfg.GOBIN != "" { pkg.Target = filepath.Join(cfg.GOBIN, exe) } else if cfg.ModulesEnabled { - pkg.Target = filepath.Join(modload.BinDir(loaderstate), exe) + pkg.Target = filepath.Join(modload.BinDir(ld), exe) } } @@ -3327,7 +3381,7 @@ func GoFilesPackage(loaderstate *modload.State, ctx context.Context, opts Packag pkg.Error = &PackageError{Err: &mainPackageError{importPath: pkg.ImportPath}} pkg.Incomplete = true } - setToolFlags(loaderstate, pkg) + setToolFlags(ld, pkg) return pkg } @@ -3347,11 +3401,11 @@ func GoFilesPackage(loaderstate *modload.State, ctx context.Context, opts Packag // module, but its go.mod file (if it has one) must not contain directives that // would cause it to be interpreted differently if it were the main module // (replace, exclude). -func PackagesAndErrorsOutsideModule(loaderstate *modload.State, ctx context.Context, opts PackageOpts, args []string) ([]*Package, error) { - if !loaderstate.ForceUseModules { +func PackagesAndErrorsOutsideModule(ld *modload.Loader, ctx context.Context, opts PackageOpts, args []string) ([]*Package, error) { + if !ld.ForceUseModules { panic("modload.ForceUseModules must be true") } - if loaderstate.RootMode != modload.NoRoot { + if ld.RootMode != modload.NoRoot { panic("modload.RootMode must be NoRoot") } @@ -3398,25 +3452,25 @@ func PackagesAndErrorsOutsideModule(loaderstate *modload.State, ctx context.Cont // (first result). It's possible this module won't provide packages named by // later arguments, and other modules would. Let's not try to be too // magical though. - allowed := loaderstate.CheckAllowed + allowed := ld.CheckAllowed if modload.IsRevisionQuery(firstPath, version) { // Don't check for retractions if a specific revision is requested. allowed = nil } noneSelected := func(path string) (version string) { return "none" } - qrs, err := modload.QueryPackages(loaderstate, ctx, patterns[0], version, noneSelected, allowed) + qrs, err := modload.QueryPackages(ld, ctx, patterns[0], version, noneSelected, allowed) if err != nil { return nil, fmt.Errorf("%s: %w", args[0], err) } rootMod := qrs[0].Mod - deprecation, err := modload.CheckDeprecation(loaderstate, ctx, rootMod) + deprecation, err := modload.CheckDeprecation(ld, ctx, rootMod) if err != nil { return nil, fmt.Errorf("%s: %w", args[0], err) } if deprecation != "" { fmt.Fprintf(os.Stderr, "go: module %s is deprecated: %s\n", rootMod.Path, modload.ShortMessage(deprecation, "")) } - data, err := modfetch.GoMod(ctx, rootMod.Path, rootMod.Version) + data, err := ld.Fetcher().GoMod(ctx, rootMod.Path, rootMod.Version) if err != nil { return nil, fmt.Errorf("%s: %w", args[0], err) } @@ -3438,12 +3492,12 @@ func PackagesAndErrorsOutsideModule(loaderstate *modload.State, ctx context.Cont // Since we are in NoRoot mode, the build list initially contains only // the dummy command-line-arguments module. Add a requirement on the // module that provides the packages named on the command line. - if _, err := modload.EditBuildList(loaderstate, ctx, nil, []module.Version{rootMod}); err != nil { + if _, err := modload.EditBuildList(ld, ctx, nil, []module.Version{rootMod}); err != nil { return nil, fmt.Errorf("%s: %w", args[0], err) } // Load packages for all arguments. - pkgs := PackagesAndErrors(loaderstate, ctx, opts, patterns) + pkgs := PackagesAndErrors(ld, ctx, opts, patterns) // Check that named packages are all provided by the same module. for _, pkg := range pkgs { @@ -3471,14 +3525,14 @@ func PackagesAndErrorsOutsideModule(loaderstate *modload.State, ctx context.Cont } // EnsureImport ensures that package p imports the named package. -func EnsureImport(s *modload.State, p *Package, pkg string) { +func EnsureImport(s *modload.Loader, p *Package, pkg string) { for _, d := range p.Internal.Imports { if d.Name == pkg { return } } - p1, err := LoadImportWithFlags(s, pkg, p.Dir, p, &ImportStack{}, nil, 0) + p1, err := loadImport(s, context.TODO(), PackageOpts{}, nil, pkg, p.Dir, p, &ImportStack{}, nil, 0) if err != nil { base.Fatalf("load %s: %v", pkg, err) } @@ -3494,10 +3548,10 @@ func EnsureImport(s *modload.State, p *Package, pkg string) { // "go test -cover"). It walks through the packages being built (and // dependencies) and marks them for coverage instrumentation when // appropriate, and possibly adding additional deps where needed. -func PrepareForCoverageBuild(s *modload.State, pkgs []*Package) { - var match []func(*modload.State, *Package) bool +func PrepareForCoverageBuild(s *modload.Loader, pkgs []*Package) { + var match []func(*modload.Loader, *Package) bool - matchMainModAndCommandLine := func(_ *modload.State, p *Package) bool { + matchMainModAndCommandLine := func(_ *modload.Loader, p *Package) bool { // note that p.Standard implies p.Module == nil below. return p.Internal.CmdlineFiles || p.Internal.CmdlinePkg || (p.Module != nil && p.Module.Main) } @@ -3505,7 +3559,7 @@ func PrepareForCoverageBuild(s *modload.State, pkgs []*Package) { if len(cfg.BuildCoverPkg) != 0 { // If -coverpkg has been specified, then we instrument only // the specific packages selected by the user-specified pattern(s). - match = make([]func(*modload.State, *Package) bool, len(cfg.BuildCoverPkg)) + match = make([]func(*modload.Loader, *Package) bool, len(cfg.BuildCoverPkg)) for i := range cfg.BuildCoverPkg { match[i] = MatchPackage(cfg.BuildCoverPkg[i], base.Cwd()) } @@ -3513,7 +3567,7 @@ func PrepareForCoverageBuild(s *modload.State, pkgs []*Package) { // Without -coverpkg, instrument only packages in the main module // (if any), as well as packages/files specifically named on the // command line. - match = []func(*modload.State, *Package) bool{matchMainModAndCommandLine} + match = []func(*modload.Loader, *Package) bool{matchMainModAndCommandLine} } // Visit the packages being built or installed, along with all of @@ -3522,7 +3576,7 @@ func PrepareForCoverageBuild(s *modload.State, pkgs []*Package) { SelectCoverPackages(s, PackageList(pkgs), match, "build") } -func SelectCoverPackages(s *modload.State, roots []*Package, match []func(*modload.State, *Package) bool, op string) []*Package { +func SelectCoverPackages(s *modload.Loader, roots []*Package, match []func(*modload.Loader, *Package) bool, op string) []*Package { var warntag string var includeMain bool switch op { diff --git a/src/cmd/go/internal/load/search.go b/src/cmd/go/internal/load/search.go index 732dc2a5ae4d2f..fe2a5a577070fe 100644 --- a/src/cmd/go/internal/load/search.go +++ b/src/cmd/go/internal/load/search.go @@ -14,7 +14,7 @@ import ( ) // MatchPackage(pattern, cwd)(p) reports whether package p matches pattern in the working directory cwd. -func MatchPackage(pattern, cwd string) func(*modload.State, *Package) bool { +func MatchPackage(pattern, cwd string) func(*modload.Loader, *Package) bool { switch { case search.IsRelativePath(pattern): // Split pattern into leading pattern-free directory path @@ -29,10 +29,10 @@ func MatchPackage(pattern, cwd string) func(*modload.State, *Package) bool { } dir = filepath.Join(cwd, dir) if pattern == "" { - return func(_ *modload.State, p *Package) bool { return p.Dir == dir } + return func(_ *modload.Loader, p *Package) bool { return p.Dir == dir } } matchPath := pkgpattern.MatchPattern(pattern) - return func(_ *modload.State, p *Package) bool { + return func(_ *modload.Loader, p *Package) bool { // Compute relative path to dir and see if it matches the pattern. rel, err := filepath.Rel(dir, p.Dir) if err != nil { @@ -49,17 +49,17 @@ func MatchPackage(pattern, cwd string) func(*modload.State, *Package) bool { // This is slightly inaccurate: it matches every package, which isn't the same // as matching the "all" package pattern. // TODO(matloob): Should we make this more accurate? Does anyone depend on this behavior? - return func(_ *modload.State, p *Package) bool { return true } + return func(_ *modload.Loader, p *Package) bool { return true } case pattern == "std": - return func(_ *modload.State, p *Package) bool { return p.Standard } + return func(_ *modload.Loader, p *Package) bool { return p.Standard } case pattern == "cmd": - return func(_ *modload.State, p *Package) bool { return p.Standard && strings.HasPrefix(p.ImportPath, "cmd/") } + return func(_ *modload.Loader, p *Package) bool { return p.Standard && strings.HasPrefix(p.ImportPath, "cmd/") } default: - return func(s *modload.State, p *Package) bool { + return func(s *modload.Loader, p *Package) bool { switch { - case pattern == "tool" && modload.Enabled(s): + case pattern == "tool" && s.Enabled(): return s.MainModules.Tools()[p.ImportPath] - case pattern == "work" && modload.Enabled(s): + case pattern == "work" && s.Enabled(): return p.Module != nil && s.MainModules.Contains(p.Module.Path) default: matchPath := pkgpattern.MatchPattern(pattern) diff --git a/src/cmd/go/internal/load/test.go b/src/cmd/go/internal/load/test.go index c7c58fd5487765..8453cb2dc020b1 100644 --- a/src/cmd/go/internal/load/test.go +++ b/src/cmd/go/internal/load/test.go @@ -48,8 +48,8 @@ type TestCover struct { // the package containing an error if the test packages or // their dependencies have errors. // Only test packages without errors are returned. -func TestPackagesFor(loaderstate *modload.State, ctx context.Context, opts PackageOpts, p *Package, cover *TestCover) (pmain, ptest, pxtest, perr *Package) { - pmain, ptest, pxtest = TestPackagesAndErrors(loaderstate, ctx, nil, opts, p, cover) +func TestPackagesFor(ld *modload.Loader, ctx context.Context, opts PackageOpts, p *Package, cover *TestCover) (pmain, ptest, pxtest, perr *Package) { + pmain, ptest, pxtest = TestPackagesAndErrors(ld, ctx, nil, opts, p, cover) for _, p1 := range []*Package{ptest, pxtest, pmain} { if p1 == nil { // pxtest may be nil @@ -99,7 +99,7 @@ func TestPackagesFor(loaderstate *modload.State, ctx context.Context, opts Packa // // The caller is expected to have checked that len(p.TestGoFiles)+len(p.XTestGoFiles) > 0, // or else there's no point in any of this. -func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done func(), opts PackageOpts, p *Package, cover *TestCover) (pmain, ptest, pxtest *Package) { +func TestPackagesAndErrors(ld *modload.Loader, ctx context.Context, done func(), opts PackageOpts, p *Package, cover *TestCover) (pmain, ptest, pxtest *Package) { ctx, span := trace.StartSpan(ctx, "load.TestPackagesAndErrors") defer span.Done() @@ -107,7 +107,7 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done defer pre.flush() allImports := append([]string{}, p.TestImports...) allImports = append(allImports, p.XTestImports...) - pre.preloadImports(loaderstate, ctx, opts, allImports, p.Internal.Build) + pre.preloadImports(ld, ctx, opts, allImports, p.Internal.Build) var ptestErr, pxtestErr *PackageError var imports, ximports []*Package @@ -116,8 +116,9 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done var incomplete bool stk.Push(ImportInfo{Pkg: p.ImportPath + " (test)"}) rawTestImports := str.StringList(p.TestImports) + for i, path := range p.TestImports { - p1, err := loadImport(loaderstate, ctx, opts, pre, path, p.Dir, p, &stk, p.Internal.Build.TestImportPos[path], ResolveImport) + p1, err := loadImport(ld, ctx, opts, pre, path, p.Dir, p, &stk, p.Internal.Build.TestImportPos[path], ResolveImport) if err != nil && ptestErr == nil { ptestErr = err incomplete = true @@ -128,6 +129,20 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done p.TestImports[i] = p1.ImportPath imports = append(imports, p1) } + + var ptestCompiledImports []string + if hasSimd := hasSimd(p.TestImports); hasSimd { + p1, err := loadImport(ld, ctx, opts, pre, SimdBridgePkg, p.Dir, p, &stk, nil, ResolveImport|allowSimdInternalBridge) + if err != nil && ptestErr == nil { + ptestErr = err + incomplete = true + } + if p1.Incomplete { + incomplete = true + } + imports = append(imports, p1) + ptestCompiledImports = append(ptestCompiledImports, p1.ImportPath) + } var err error p.TestEmbedFiles, testEmbed, err = resolveEmbed(p.Dir, p.TestEmbedPatterns) if err != nil { @@ -145,8 +160,9 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done pxtestNeedsPtest := false var pxtestIncomplete bool rawXTestImports := str.StringList(p.XTestImports) + for i, path := range p.XTestImports { - p1, err := loadImport(loaderstate, ctx, opts, pre, path, p.Dir, p, &stk, p.Internal.Build.XTestImportPos[path], ResolveImport) + p1, err := loadImport(ld, ctx, opts, pre, path, p.Dir, p, &stk, p.Internal.Build.XTestImportPos[path], ResolveImport) if err != nil && pxtestErr == nil { pxtestErr = err } @@ -160,6 +176,19 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done } p.XTestImports[i] = p1.ImportPath } + + var pxtestCompiledImports []string + if hasSimd := hasSimd(p.XTestImports); hasSimd { + p1, err := loadImport(ld, ctx, opts, pre, SimdBridgePkg, p.Dir, p, &stk, nil, ResolveImport|allowSimdInternalBridge) + if err != nil && pxtestErr == nil { + pxtestErr = err + } + if p1.Incomplete { + pxtestIncomplete = true + } + ximports = append(ximports, p1) + pxtestCompiledImports = append(pxtestCompiledImports, p1.ImportPath) + } p.XTestEmbedFiles, xtestEmbed, err = resolveEmbed(p.Dir, p.XTestEmbedPatterns) if err != nil && pxtestErr == nil { pxtestErr = &PackageError{ @@ -200,6 +229,12 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done ptest.Imports = str.StringList(p.TestImports, p.Imports) ptest.Internal.Imports = append(imports, p.Internal.Imports...) ptest.Internal.RawImports = str.StringList(rawTestImports, p.Internal.RawImports) + ptest.Internal.CompiledImports = slices.Clone(p.Internal.CompiledImports) + for _, path := range ptestCompiledImports { + if !slices.Contains(ptest.Internal.CompiledImports, path) { + ptest.Internal.CompiledImports = append(ptest.Internal.CompiledImports, path) + } + } ptest.Internal.ForceLibrary = true ptest.Internal.BuildInfo = nil ptest.Internal.Build = new(build.Package) @@ -248,8 +283,9 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done ImportPos: p.Internal.Build.XTestImportPos, Directives: p.Internal.Build.XTestDirectives, }, - Imports: ximports, - RawImports: rawXTestImports, + Imports: ximports, + RawImports: rawXTestImports, + CompiledImports: pxtestCompiledImports, Asmflags: p.Internal.Asmflags, Gcflags: p.Internal.Gcflags, @@ -293,16 +329,7 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done } pb := p.Internal.Build - pmain.DefaultGODEBUG = defaultGODEBUG(loaderstate, pmain, pb.Directives, pb.TestDirectives, pb.XTestDirectives) - if pmain.Internal.BuildInfo == nil || pmain.DefaultGODEBUG != p.DefaultGODEBUG { - // Either we didn't generate build info for the package under test (because it wasn't package main), or - // the DefaultGODEBUG used to build the test main package is different from the DefaultGODEBUG - // used to build the package under test. If we didn't set build info for the package under test - // pmain won't have buildinfo set (since we copy it from the package under test). If the default GODEBUG - // used for the package under test is different from that of the test main, the BuildInfo assigned above from the package - // under test incorrect for the test main package. Either set or correct pmain's build info. - pmain.setBuildInfo(ctx, opts.AutoVCS) - } + pmain.DefaultGODEBUG = defaultGODEBUG(ld, pmain, pb.Directives, pb.TestDirectives, pb.XTestDirectives) // The generated main also imports testing, regexp, and os. // Also the linker introduces implicit dependencies reported by LinkerDeps. @@ -311,7 +338,7 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done if cover != nil { deps = append(deps, "internal/coverage/cfile") } - ldDeps, err := LinkerDeps(loaderstate, p) + ldDeps, err := LinkerDeps(ld, p) if err != nil && pmain.Error == nil { pmain.Error = &PackageError{Err: err} } @@ -322,7 +349,7 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done if dep == ptest.ImportPath { pmain.Internal.Imports = append(pmain.Internal.Imports, ptest) } else { - p1, err := loadImport(loaderstate, ctx, opts, pre, dep, "", nil, &stk, nil, 0) + p1, err := loadImport(ld, ctx, opts, pre, dep, "", nil, &stk, nil, 0) if err != nil && pmain.Error == nil { pmain.Error = err pmain.Incomplete = true @@ -333,12 +360,6 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done stk.Pop() parallelizablePart := func() { - allTestImports := make([]*Package, 0, len(pmain.Internal.Imports)+len(imports)+len(ximports)) - allTestImports = append(allTestImports, pmain.Internal.Imports...) - allTestImports = append(allTestImports, imports...) - allTestImports = append(allTestImports, ximports...) - setToolFlags(loaderstate, allTestImports...) - // Do initial scan for metadata needed for writing _testmain.go // Use that metadata to update the list of imports for package main. // The list of imports is used by recompileForTest and by the loop @@ -379,6 +400,15 @@ func TestPackagesAndErrors(loaderstate *modload.State, ctx context.Context, done ptest.Incomplete = true } + if !opts.SuppressBuildInfo { + // Now that pmain.Internal.Imports includes the test dependencies, + // regenerate build info for the test binary. We can't reuse p's + // build info because the test variants of packages can add + // packages from modules that don't already have transitive + // imports from p. + pmain.setBuildInfo(ctx, ld.Fetcher(), opts.AutoVCS) + } + if cover != nil { // Here ptest needs to inherit the proper coverage mode (since // it contains p's Go files), whereas pmain contains only diff --git a/src/cmd/go/internal/lockedfile/lockedfile.go b/src/cmd/go/internal/lockedfile/lockedfile.go index 8bd2ffbe8f7860..f48124ffbc0d3e 100644 --- a/src/cmd/go/internal/lockedfile/lockedfile.go +++ b/src/cmd/go/internal/lockedfile/lockedfile.go @@ -94,6 +94,11 @@ func (f *File) Close() error { err := closeFile(f.osFile.File) f.cleanup.Stop() + // f may be dead at the moment after we access f.cleanup, + // so the cleanup can fire before Stop completes. Keep f + // alive while we call Stop. See the documentation for + // runtime.Cleanup.Stop. + runtime.KeepAlive(f) return err } diff --git a/src/cmd/go/internal/modcmd/download.go b/src/cmd/go/internal/modcmd/download.go index 7544e221d58f81..8f0d827b1ca693 100644 --- a/src/cmd/go/internal/modcmd/download.go +++ b/src/cmd/go/internal/modcmd/download.go @@ -71,9 +71,9 @@ useful on systems that do not preserve the module cache. The -x flag causes download to print the commands download executes. -See https://golang.org/ref/mod#go-mod-download for more about 'go mod download'. +See https://go.dev/ref/mod#go-mod-download for more about 'go mod download'. -See https://golang.org/ref/mod#version-queries for more about version queries. +See https://go.dev/ref/mod#version-queries for more about version queries. `, } @@ -109,19 +109,19 @@ type ModuleJSON struct { } func runDownload(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() // Check whether modules are enabled and whether we're in a module. - moduleLoaderState.ForceUseModules = true + moduleLoader.ForceUseModules = true modload.ExplicitWriteGoMod = true haveExplicitArgs := len(args) > 0 - if modload.HasModRoot(moduleLoaderState) || modload.WorkFilePath(moduleLoaderState) != "" { - modload.LoadModFile(moduleLoaderState, ctx) // to fill MainModules + if moduleLoader.HasModRoot() || modload.WorkFilePath(moduleLoader) != "" { + modload.LoadModFile(moduleLoader, ctx) // to fill MainModules if haveExplicitArgs { - for _, mainModule := range moduleLoaderState.MainModules.Versions() { + for _, mainModule := range moduleLoader.MainModules.Versions() { targetAtUpgrade := mainModule.Path + "@upgrade" targetAtPatch := mainModule.Path + "@patch" for _, arg := range args { @@ -131,14 +131,14 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { } } } - } else if modload.WorkFilePath(moduleLoaderState) != "" { + } else if modload.WorkFilePath(moduleLoader) != "" { // TODO(#44435): Think about what the correct query is to download the // right set of modules. Also see code review comment at // https://go-review.googlesource.com/c/go/+/359794/comments/ce946a80_6cf53992. args = []string{"all"} } else { - mainModule := moduleLoaderState.MainModules.Versions()[0] - modFile := moduleLoaderState.MainModules.ModFile(mainModule) + mainModule := moduleLoader.MainModules.Versions()[0] + modFile := moduleLoader.MainModules.ModFile(mainModule) if modFile.Go == nil || gover.Compare(modFile.Go.Version, gover.ExplicitIndirectVersion) < 0 { if len(modFile.Require) > 0 { args = []string{"all"} @@ -154,12 +154,12 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { // However, we also need to load the full module graph, to ensure that // we have downloaded enough of the module graph to run 'go list all', // 'go mod graph', and similar commands. - _, err := modload.LoadModGraph(moduleLoaderState, ctx, "") + _, err := modload.LoadModGraph(moduleLoader, ctx, "") if err != nil { // TODO(#64008): call base.Fatalf instead of toolchain.SwitchOrFatal // here, since we can only reach this point with an outdated toolchain // if the go.mod file is inconsistent. - toolchain.SwitchOrFatal(moduleLoaderState, ctx, err) + toolchain.SwitchOrFatal(moduleLoader, ctx, err) } for _, m := range modFile.Require { @@ -170,7 +170,7 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { } if len(args) == 0 { - if modload.HasModRoot(moduleLoaderState) { + if moduleLoader.HasModRoot() { os.Stderr.WriteString("go: no module dependencies to download\n") } else { base.Errorf("go: no modules specified (see 'go help mod download')") @@ -178,14 +178,14 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { base.Exit() } - if *downloadReuse != "" && modload.HasModRoot(moduleLoaderState) { + if *downloadReuse != "" && moduleLoader.HasModRoot() { base.Fatalf("go mod download -reuse cannot be used inside a module") } var mods []*ModuleJSON type token struct{} sem := make(chan token, runtime.GOMAXPROCS(0)) - infos, infosErr := modload.ListModules(moduleLoaderState, ctx, args, 0, *downloadReuse) + infos, infosErr := modload.ListModules(moduleLoader, ctx, args, 0, *downloadReuse) // There is a bit of a chicken-and-egg problem here: ideally we need to know // which Go version to switch to download the requested modules, but if we @@ -212,7 +212,7 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { // toolchain version) or only one module (as is used by the Go Module Proxy). if infosErr != nil { - sw := toolchain.NewSwitcher(moduleLoaderState) + sw := toolchain.NewSwitcher(moduleLoader) sw.Error(infosErr) if sw.NeedSwitch() { sw.Switch(ctx) @@ -221,7 +221,7 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { // when we can. } - if !haveExplicitArgs && modload.WorkFilePath(moduleLoaderState) == "" { + if !haveExplicitArgs && modload.WorkFilePath(moduleLoader) == "" { // 'go mod download' is sometimes run without arguments to pre-populate the // module cache. In modules that aren't at go 1.17 or higher, it may fetch // modules that aren't needed to build packages in the main module. This is @@ -232,7 +232,7 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { // TODO(#64008): In the future, report an error if go.mod or go.sum need to // be updated after loading the build list. This may require setting // the mode to "mod" or "readonly" depending on haveExplicitArgs. - if err := modload.WriteGoMod(moduleLoaderState, ctx, modload.WriteOpts{}); err != nil { + if err := modload.WriteGoMod(moduleLoader, ctx, modload.WriteOpts{}); err != nil { base.Fatal(err) } } @@ -264,7 +264,7 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { } sem <- token{} go func() { - err := DownloadModule(ctx, m) + err := DownloadModule(ctx, moduleLoader.Fetcher(), m) if err != nil { downloadErrs.Store(m, err) m.Error = err.Error() @@ -292,8 +292,8 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { // with no arguments we download the module pattern "all", // which may include dependencies that are normally pruned out // of the individual modules in the workspace. - if haveExplicitArgs || modload.WorkFilePath(moduleLoaderState) != "" { - sw := toolchain.NewSwitcher(moduleLoaderState) + if haveExplicitArgs || modload.WorkFilePath(moduleLoader) != "" { + sw := toolchain.NewSwitcher(moduleLoader) // Add errors to the Switcher in deterministic order so that they will be // logged deterministically. for _, m := range mods { @@ -348,8 +348,8 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { // // Don't save sums for 'go mod download' without arguments unless we're in // workspace mode; see comment above. - if haveExplicitArgs || modload.WorkFilePath(moduleLoaderState) != "" { - if err := modload.WriteGoMod(moduleLoaderState, ctx, modload.WriteOpts{}); err != nil { + if haveExplicitArgs || modload.WorkFilePath(moduleLoader) != "" { + if err := modload.WriteGoMod(moduleLoader, ctx, modload.WriteOpts{}); err != nil { base.Error(err) } } @@ -364,27 +364,27 @@ func runDownload(ctx context.Context, cmd *base.Command, args []string) { // DownloadModule runs 'go mod download' for m.Path@m.Version, // leaving the results (including any error) in m itself. -func DownloadModule(ctx context.Context, m *ModuleJSON) error { +func DownloadModule(ctx context.Context, f *modfetch.Fetcher, m *ModuleJSON) error { var err error - _, file, err := modfetch.InfoFile(ctx, m.Path, m.Version) + _, file, err := f.InfoFile(ctx, m.Path, m.Version) if err != nil { return err } m.Info = file - m.GoMod, err = modfetch.GoModFile(ctx, m.Path, m.Version) + m.GoMod, err = f.GoModFile(ctx, m.Path, m.Version) if err != nil { return err } - m.GoModSum, err = modfetch.GoModSum(ctx, m.Path, m.Version) + m.GoModSum, err = f.GoModSum(ctx, m.Path, m.Version) if err != nil { return err } mod := module.Version{Path: m.Path, Version: m.Version} - m.Zip, err = modfetch.DownloadZip(ctx, mod) + m.Zip, err = f.DownloadZip(ctx, mod) if err != nil { return err } m.Sum = modfetch.Sum(ctx, mod) - m.Dir, err = modfetch.Download(ctx, mod) + m.Dir, err = f.Download(ctx, mod) return err } diff --git a/src/cmd/go/internal/modcmd/edit.go b/src/cmd/go/internal/modcmd/edit.go index 2e0d1a6dd8cd02..60468034a08cc7 100644 --- a/src/cmd/go/internal/modcmd/edit.go +++ b/src/cmd/go/internal/modcmd/edit.go @@ -60,10 +60,14 @@ constraints imposed by other modules. The -go=version flag sets the expected Go language version. This flag is mainly for tools that understand Go version dependencies. +It takes a version like "1.26" or "1.26.2". +Using the version "none" removes the go directive. Users should prefer 'go get go@version'. -The -toolchain=version flag sets the Go toolchain to use. +The -toolchain=name flag sets the Go toolchain to use. This flag is mainly for tools that understand Go version dependencies. +It takes a toolchain name like "go1.26" or "go1.26.2". +Using the name "none" removes the toolchain directive. Users should prefer 'go get toolchain@version'. The -exclude=path@version and -dropexclude=path@version flags @@ -166,7 +170,7 @@ use 'go list -m -json all'. Edit also provides the -C, -n, and -x build flags. -See https://golang.org/ref/mod#go-mod-edit for more about 'go mod edit'. +See https://go.dev/ref/mod#go-mod-edit for more about 'go mod edit'. `, } @@ -209,7 +213,7 @@ func init() { } func runEdit(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() anyFlags := *editModule != "" || *editGo != "" || *editToolchain != "" || @@ -233,7 +237,7 @@ func runEdit(ctx context.Context, cmd *base.Command, args []string) { if len(args) == 1 { gomod = args[0] } else { - gomod = modload.ModFilePath(moduleLoaderState) + gomod = moduleLoader.ModFilePath() } if *editModule != "" { @@ -328,7 +332,10 @@ func runEdit(ctx context.Context, cmd *base.Command, args []string) { // parsePathVersion parses -flag=arg expecting arg to be path@version. func parsePathVersion(flag, arg string) (path, version string) { - before, after, found := strings.Cut(arg, "@") + before, after, found, err := modload.ParsePathVersion(arg) + if err != nil { + base.Fatalf("go: -%s=%s: %v", flag, arg, err) + } if !found { base.Fatalf("go: -%s=%s: need path@version", flag, arg) } @@ -362,7 +369,10 @@ func parsePathVersionOptional(adj, arg string, allowDirPath bool) (path, version if allowDirPath && modfile.IsDirectoryPath(arg) { return arg, "", nil } - before, after, found := strings.Cut(arg, "@") + before, after, found, err := modload.ParsePathVersion(arg) + if err != nil { + return "", "", err + } if !found { path = arg } else { @@ -584,14 +594,15 @@ func flagDropIgnore(arg string) { // fileJSON is the -json output data structure. type fileJSON struct { Module editModuleJSON - Go string `json:",omitempty"` - Toolchain string `json:",omitempty"` - Require []requireJSON - Exclude []module.Version - Replace []replaceJSON - Retract []retractJSON - Tool []toolJSON - Ignore []ignoreJSON + Go string `json:",omitempty"` + Toolchain string `json:",omitempty"` + GoDebug []debugJSON `json:",omitempty"` + Require []requireJSON `json:",omitempty"` + Exclude []module.Version `json:",omitempty"` + Replace []replaceJSON `json:",omitempty"` + Retract []retractJSON `json:",omitempty"` + Tool []toolJSON `json:",omitempty"` + Ignore []ignoreJSON `json:",omitempty"` } type editModuleJSON struct { @@ -599,6 +610,11 @@ type editModuleJSON struct { Deprecated string `json:",omitempty"` } +type debugJSON struct { + Key string + Value string +} + type requireJSON struct { Path string Version string `json:",omitempty"` @@ -657,6 +673,9 @@ func editPrintJSON(modFile *modfile.File) { for _, i := range modFile.Ignore { f.Ignore = append(f.Ignore, ignoreJSON{i.Path}) } + for _, d := range modFile.Godebug { + f.GoDebug = append(f.GoDebug, debugJSON{d.Key, d.Value}) + } data, err := json.MarshalIndent(&f, "", "\t") if err != nil { base.Fatalf("go: internal error: %v", err) diff --git a/src/cmd/go/internal/modcmd/graph.go b/src/cmd/go/internal/modcmd/graph.go index 467da99b22961a..1207227ca3a316 100644 --- a/src/cmd/go/internal/modcmd/graph.go +++ b/src/cmd/go/internal/modcmd/graph.go @@ -35,7 +35,7 @@ in the go.mod file. The -x flag causes graph to print the commands graph executes. -See https://golang.org/ref/mod#go-mod-graph for more about 'go mod graph'. +See https://go.dev/ref/mod#go-mod-graph for more about 'go mod graph'. `, Run: runGraph, } @@ -52,24 +52,24 @@ func init() { } func runGraph(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() if len(args) > 0 { base.Fatalf("go: 'go mod graph' accepts no arguments") } - moduleLoaderState.ForceUseModules = true - moduleLoaderState.RootMode = modload.NeedRoot + moduleLoader.ForceUseModules = true + moduleLoader.RootMode = modload.NeedRoot goVersion := graphGo.String() if goVersion != "" && gover.Compare(gover.Local(), goVersion) < 0 { - toolchain.SwitchOrFatal(moduleLoaderState, ctx, &gover.TooNewError{ + toolchain.SwitchOrFatal(moduleLoader, ctx, &gover.TooNewError{ What: "-go flag", GoVersion: goVersion, }) } - mg, err := modload.LoadModGraph(moduleLoaderState, ctx, goVersion) + mg, err := modload.LoadModGraph(moduleLoader, ctx, goVersion) if err != nil { base.Fatal(err) } diff --git a/src/cmd/go/internal/modcmd/init.go b/src/cmd/go/internal/modcmd/init.go index e8db3d005f7c58..c1ff17a66ab73e 100644 --- a/src/cmd/go/internal/modcmd/init.go +++ b/src/cmd/go/internal/modcmd/init.go @@ -24,7 +24,7 @@ Init accepts one optional argument, the module path for the new module. If the module path argument is omitted, init will attempt to infer the module path using import comments in .go files and the current directory (if in GOPATH). -See https://golang.org/ref/mod#go-mod-init for more about 'go mod init'. +See https://go.dev/ref/mod#go-mod-init for more about 'go mod init'. `, Run: runInit, } @@ -35,7 +35,7 @@ func init() { } func runInit(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() if len(args) > 1 { base.Fatalf("go: 'go mod init' accepts at most one argument") } @@ -44,6 +44,6 @@ func runInit(ctx context.Context, cmd *base.Command, args []string) { modPath = args[0] } - moduleLoaderState.ForceUseModules = true - modload.CreateModFile(moduleLoaderState, ctx, modPath) // does all the hard work + moduleLoader.ForceUseModules = true + modload.CreateModFile(moduleLoader, ctx, modPath) // does all the hard work } diff --git a/src/cmd/go/internal/modcmd/tidy.go b/src/cmd/go/internal/modcmd/tidy.go index 3ac0109625e674..532c991861d821 100644 --- a/src/cmd/go/internal/modcmd/tidy.go +++ b/src/cmd/go/internal/modcmd/tidy.go @@ -55,7 +55,7 @@ file. The -x flag causes tidy to print the commands download executes. -See https://golang.org/ref/mod#go-mod-tidy for more about 'go mod tidy'. +See https://go.dev/ref/mod#go-mod-tidy for more about 'go mod tidy'. `, Run: runTidy, } @@ -105,7 +105,7 @@ func (f *goVersionFlag) Set(s string) error { } func runTidy(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() if len(args) > 0 { base.Fatalf("go: 'go mod tidy' accepts no arguments") } @@ -120,18 +120,18 @@ func runTidy(ctx context.Context, cmd *base.Command, args []string) { // those packages. In order to make 'go test' reproducible for the packages // that are in 'all' but outside of the main module, we must explicitly // request that their test dependencies be included. - moduleLoaderState.ForceUseModules = true - moduleLoaderState.RootMode = modload.NeedRoot + moduleLoader.ForceUseModules = true + moduleLoader.RootMode = modload.NeedRoot goVersion := tidyGo.String() if goVersion != "" && gover.Compare(gover.Local(), goVersion) < 0 { - toolchain.SwitchOrFatal(moduleLoaderState, ctx, &gover.TooNewError{ + toolchain.SwitchOrFatal(moduleLoader, ctx, &gover.TooNewError{ What: "-go flag", GoVersion: goVersion, }) } - modload.LoadPackages(moduleLoaderState, ctx, modload.PackageOpts{ + modload.LoadPackages(moduleLoader, ctx, modload.PackageOpts{ TidyGoVersion: tidyGo.String(), Tags: imports.AnyTags(), Tidy: true, @@ -142,6 +142,6 @@ func runTidy(ctx context.Context, cmd *base.Command, args []string) { LoadTests: true, AllowErrors: tidyE, SilenceMissingStdImports: true, - Switcher: toolchain.NewSwitcher(moduleLoaderState), + Switcher: toolchain.NewSwitcher(moduleLoader), }, "all") } diff --git a/src/cmd/go/internal/modcmd/vendor.go b/src/cmd/go/internal/modcmd/vendor.go index ef44ce41c04c7f..1dc7282eb170a8 100644 --- a/src/cmd/go/internal/modcmd/vendor.go +++ b/src/cmd/go/internal/modcmd/vendor.go @@ -49,7 +49,7 @@ path instead of "vendor". The go command can only use a vendor directory named "vendor" within the module root directory, so this flag is primarily useful for other tools. -See https://golang.org/ref/mod#go-mod-vendor for more about 'go mod vendor'. +See https://go.dev/ref/mod#go-mod-vendor for more about 'go mod vendor'. `, Run: runVendor, } @@ -66,20 +66,20 @@ func init() { } func runVendor(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) - if modload.WorkFilePath(moduleLoaderState) != "" { + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() + if modload.WorkFilePath(moduleLoader) != "" { base.Fatalf("go: 'go mod vendor' cannot be run in workspace mode. Run 'go work vendor' to vendor the workspace or set 'GOWORK=off' to exit workspace mode.") } - RunVendor(moduleLoaderState, ctx, vendorE, vendorO, args) + RunVendor(moduleLoader, ctx, vendorE, vendorO, args) } -func RunVendor(loaderstate *modload.State, ctx context.Context, vendorE bool, vendorO string, args []string) { +func RunVendor(ld *modload.Loader, ctx context.Context, vendorE bool, vendorO string, args []string) { if len(args) != 0 { base.Fatalf("go: 'go mod vendor' accepts no arguments") } - loaderstate.ForceUseModules = true - loaderstate.RootMode = modload.NeedRoot + ld.ForceUseModules = true + ld.RootMode = modload.NeedRoot loadOpts := modload.PackageOpts{ Tags: imports.AnyTags(), @@ -89,7 +89,7 @@ func RunVendor(loaderstate *modload.State, ctx context.Context, vendorE bool, ve AllowErrors: vendorE, SilenceMissingStdImports: true, } - _, pkgs := modload.LoadPackages(loaderstate, ctx, loadOpts, "all") + _, pkgs := modload.LoadPackages(ld, ctx, loadOpts, "all") var vdir string switch { @@ -98,7 +98,7 @@ func RunVendor(loaderstate *modload.State, ctx context.Context, vendorE bool, ve case vendorO != "": vdir = filepath.Join(base.Cwd(), vendorO) default: - vdir = filepath.Join(modload.VendorDir(loaderstate)) + vdir = filepath.Join(modload.VendorDir(ld)) } if err := os.RemoveAll(vdir); err != nil { base.Fatal(err) @@ -106,8 +106,8 @@ func RunVendor(loaderstate *modload.State, ctx context.Context, vendorE bool, ve modpkgs := make(map[module.Version][]string) for _, pkg := range pkgs { - m := modload.PackageModule(pkg) - if m.Path == "" || loaderstate.MainModules.Contains(m.Path) { + m := ld.PackageModule(pkg) + if m.Path == "" || ld.MainModules.Contains(m.Path) { continue } modpkgs[m] = append(modpkgs[m], pkg) @@ -117,13 +117,13 @@ func RunVendor(loaderstate *modload.State, ctx context.Context, vendorE bool, ve includeAllReplacements := false includeGoVersions := false isExplicit := map[module.Version]bool{} - gv := loaderstate.MainModules.GoVersion(loaderstate) - if gover.Compare(gv, "1.14") >= 0 && (modload.FindGoWork(loaderstate, base.Cwd()) != "" || modload.ModFile(loaderstate).Go != nil) { + gv := ld.MainModules.GoVersion(ld) + if gover.Compare(gv, "1.14") >= 0 && (ld.FindGoWork(base.Cwd()) != "" || modload.ModFile(ld).Go != nil) { // If the Go version is at least 1.14, annotate all explicit 'require' and // 'replace' targets found in the go.mod file so that we can perform a // stronger consistency check when -mod=vendor is set. - for _, m := range loaderstate.MainModules.Versions() { - if modFile := loaderstate.MainModules.ModFile(m); modFile != nil { + for _, m := range ld.MainModules.Versions() { + if modFile := ld.MainModules.ModFile(m); modFile != nil { for _, r := range modFile.Require { isExplicit[r.Mod] = true } @@ -157,20 +157,20 @@ func RunVendor(loaderstate *modload.State, ctx context.Context, vendorE bool, ve w = io.MultiWriter(&buf, os.Stderr) } - if loaderstate.MainModules.WorkFile() != nil { + if ld.MainModules.WorkFile() != nil { fmt.Fprintf(w, "## workspace\n") } replacementWritten := make(map[module.Version]bool) for _, m := range vendorMods { - replacement := modload.Replacement(loaderstate, m) + replacement := modload.Replacement(ld, m) line := moduleLine(m, replacement) replacementWritten[m] = true io.WriteString(w, line) goVersion := "" if includeGoVersions { - goVersion = modload.ModuleInfo(loaderstate, ctx, m.Path).GoVersion + goVersion = modload.ModuleInfo(ld, ctx, m.Path).GoVersion } switch { case isExplicit[m] && goVersion != "": @@ -185,7 +185,7 @@ func RunVendor(loaderstate *modload.State, ctx context.Context, vendorE bool, ve sort.Strings(pkgs) for _, pkg := range pkgs { fmt.Fprintf(w, "%s\n", pkg) - vendorPkg(loaderstate, vdir, pkg) + vendorPkg(ld, vdir, pkg) } } @@ -193,8 +193,8 @@ func RunVendor(loaderstate *modload.State, ctx context.Context, vendorE bool, ve // Record unused and wildcard replacements at the end of the modules.txt file: // without access to the complete build list, the consumer of the vendor // directory can't otherwise determine that those replacements had no effect. - for _, m := range loaderstate.MainModules.Versions() { - if workFile := loaderstate.MainModules.WorkFile(); workFile != nil { + for _, m := range ld.MainModules.Versions() { + if workFile := ld.MainModules.WorkFile(); workFile != nil { for _, r := range workFile.Replace { if replacementWritten[r.Old] { // We already recorded this replacement. @@ -209,14 +209,14 @@ func RunVendor(loaderstate *modload.State, ctx context.Context, vendorE bool, ve } } } - if modFile := loaderstate.MainModules.ModFile(m); modFile != nil { + if modFile := ld.MainModules.ModFile(m); modFile != nil { for _, r := range modFile.Replace { if replacementWritten[r.Old] { // We already recorded this replacement. continue } replacementWritten[r.Old] = true - rNew := modload.Replacement(loaderstate, r.Old) + rNew := modload.Replacement(ld, r.Old) if rNew == (module.Version{}) { // There is no replacement. Don't try to write it. continue @@ -269,7 +269,7 @@ func moduleLine(m, r module.Version) string { return b.String() } -func vendorPkg(s *modload.State, vdir, pkg string) { +func vendorPkg(s *modload.Loader, vdir, pkg string) { src, realPath, _ := modload.Lookup(s, "", false, pkg) if src == "" { base.Errorf("internal error: no pkg for %s\n", pkg) @@ -294,7 +294,7 @@ func vendorPkg(s *modload.State, vdir, pkg string) { return matchPotentialSourceFile(dir, info, goVersion) } copyDir(dst, src, matcher, copiedFiles) - if m := modload.PackageModule(realPath); m.Path != "" { + if m := s.PackageModule(realPath); m.Path != "" { copyMetadata(m.Path, realPath, dst, src, copiedFiles) } diff --git a/src/cmd/go/internal/modcmd/verify.go b/src/cmd/go/internal/modcmd/verify.go index e40a05ed531648..a4f76427913996 100644 --- a/src/cmd/go/internal/modcmd/verify.go +++ b/src/cmd/go/internal/modcmd/verify.go @@ -33,7 +33,7 @@ verify prints "all modules verified." Otherwise it reports which modules have been changed and causes 'go mod' to exit with a non-zero status. -See https://golang.org/ref/mod#go-mod-verify for more about 'go mod verify'. +See https://go.dev/ref/mod#go-mod-verify for more about 'go mod verify'. `, Run: runVerify, } @@ -44,21 +44,21 @@ func init() { } func runVerify(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() if len(args) != 0 { // NOTE(rsc): Could take a module pattern. base.Fatalf("go: verify takes no arguments") } - moduleLoaderState.ForceUseModules = true - moduleLoaderState.RootMode = modload.NeedRoot + moduleLoader.ForceUseModules = true + moduleLoader.RootMode = modload.NeedRoot // Only verify up to GOMAXPROCS zips at once. type token struct{} sem := make(chan token, runtime.GOMAXPROCS(0)) - mg, err := modload.LoadModGraph(moduleLoaderState, ctx, "") + mg, err := modload.LoadModGraph(moduleLoader, ctx, "") if err != nil { base.Fatal(err) } @@ -72,7 +72,7 @@ func runVerify(ctx context.Context, cmd *base.Command, args []string) { errsChans[i] = errsc mod := mod // use a copy to avoid data races go func() { - errsc <- verifyMod(moduleLoaderState, ctx, mod) + errsc <- verifyMod(moduleLoader, ctx, mod) <-sem }() } @@ -90,12 +90,12 @@ func runVerify(ctx context.Context, cmd *base.Command, args []string) { } } -func verifyMod(loaderstate *modload.State, ctx context.Context, mod module.Version) []error { +func verifyMod(ld *modload.Loader, ctx context.Context, mod module.Version) []error { if gover.IsToolchain(mod.Path) { // "go" and "toolchain" have no disk footprint; nothing to verify. return nil } - if loaderstate.MainModules.Contains(mod.Path) { + if ld.MainModules.Contains(mod.Path) { return nil } var errs []error diff --git a/src/cmd/go/internal/modcmd/why.go b/src/cmd/go/internal/modcmd/why.go index 407a19d5c21040..8a33f5c54df9f9 100644 --- a/src/cmd/go/internal/modcmd/why.go +++ b/src/cmd/go/internal/modcmd/why.go @@ -47,7 +47,7 @@ For example: (main module does not need package golang.org/x/text/encoding) $ -See https://golang.org/ref/mod#go-mod-why for more about 'go mod why'. +See https://go.dev/ref/mod#go-mod-why for more about 'go mod why'. `, } @@ -63,10 +63,10 @@ func init() { } func runWhy(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) - moduleLoaderState.ForceUseModules = true - moduleLoaderState.RootMode = modload.NeedRoot + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() + moduleLoader.ForceUseModules = true + moduleLoader.RootMode = modload.NeedRoot modload.ExplicitWriteGoMod = true // don't write go.mod in ListModules loadOpts := modload.PackageOpts{ @@ -84,15 +84,15 @@ func runWhy(ctx context.Context, cmd *base.Command, args []string) { } } - mods, err := modload.ListModules(moduleLoaderState, ctx, args, 0, "") + mods, err := modload.ListModules(moduleLoader, ctx, args, 0, "") if err != nil { base.Fatal(err) } byModule := make(map[string][]string) - _, pkgs := modload.LoadPackages(moduleLoaderState, ctx, loadOpts, "all") + _, pkgs := modload.LoadPackages(moduleLoader, ctx, loadOpts, "all") for _, path := range pkgs { - m := modload.PackageModule(path) + m := moduleLoader.PackageModule(path) if m.Path != "" { byModule[m.Path] = append(byModule[m.Path], path) } @@ -102,13 +102,13 @@ func runWhy(ctx context.Context, cmd *base.Command, args []string) { best := "" bestDepth := 1000000000 for _, path := range byModule[m.Path] { - d := modload.WhyDepth(path) + d := moduleLoader.WhyDepth(path) if d > 0 && d < bestDepth { best = path bestDepth = d } } - why := modload.Why(best) + why := moduleLoader.Why(best) if why == "" { vendoring := "" if *whyVendor { @@ -121,14 +121,14 @@ func runWhy(ctx context.Context, cmd *base.Command, args []string) { } } else { // Resolve to packages. - matches, _ := modload.LoadPackages(moduleLoaderState, ctx, loadOpts, args...) + matches, _ := modload.LoadPackages(moduleLoader, ctx, loadOpts, args...) - modload.LoadPackages(moduleLoaderState, ctx, loadOpts, "all") // rebuild graph, from main module (not from named packages) + modload.LoadPackages(moduleLoader, ctx, loadOpts, "all") // rebuild graph, from main module (not from named packages) sep := "" for _, m := range matches { for _, path := range m.Pkgs { - why := modload.Why(path) + why := moduleLoader.Why(path) if why == "" { vendoring := "" if *whyVendor { diff --git a/src/cmd/go/internal/modfetch/cache.go b/src/cmd/go/internal/modfetch/cache.go index 9c34581a910a4a..7b728906d34899 100644 --- a/src/cmd/go/internal/modfetch/cache.go +++ b/src/cmd/go/internal/modfetch/cache.go @@ -15,9 +15,11 @@ import ( "math/rand" "os" "path/filepath" + "runtime" "strconv" "strings" "sync" + "syscall" "cmd/go/internal/base" "cmd/go/internal/cfg" @@ -113,15 +115,10 @@ func DownloadDir(ctx context.Context, m module.Version) (string, error) { return dir, err } - // Special case: ziphash is not required for the golang.org/fips140 module, - // because it is unpacked from a file in GOROOT, not downloaded. - // We've already checked that it's not a partial unpacking, so we're happy. - if m.Path == "golang.org/fips140" { - return dir, nil - } - - // Check if a .ziphash file exists. It should be created before the - // zip is extracted, but if it was deleted (by another program?), we need + // Check if a .ziphash file exists. For downloaded modules it is created + // before the zip is extracted; for GOFIPS140 snapshots, which Fetcher.Unzip + // unpacks from GOROOT, it is created only after extraction completes. + // Either way, if it is missing (deleted by another program?), we need // to re-calculate it. Note that checkMod will repopulate the ziphash // file if it doesn't exist, but if the module is excluded by checks // through GONOSUMDB or GOPRIVATE, that check and repopulation won't happen. @@ -156,7 +153,7 @@ func lockVersion(ctx context.Context, mod module.Version) (unlock func(), err er if err != nil { return nil, err } - if err := os.MkdirAll(filepath.Dir(path), 0777); err != nil { + if err := os.MkdirAll(filepath.Dir(path), 0o777); err != nil { return nil, err } return lockedfile.MutexAt(path).Lock() @@ -172,7 +169,7 @@ func SideLock(ctx context.Context) (unlock func(), err error) { } path := filepath.Join(cfg.GOMODCACHE, "cache", "lock") - if err := os.MkdirAll(filepath.Dir(path), 0777); err != nil { + if err := os.MkdirAll(filepath.Dir(path), 0o777); err != nil { return nil, fmt.Errorf("failed to create cache directory: %w", err) } @@ -194,12 +191,14 @@ type cachingRepo struct { once sync.Once initRepo func(context.Context) (Repo, error) r Repo + fetcher *Fetcher } -func newCachingRepo(ctx context.Context, path string, initRepo func(context.Context) (Repo, error)) *cachingRepo { +func newCachingRepo(ctx context.Context, fetcher *Fetcher, path string, initRepo func(context.Context) (Repo, error)) *cachingRepo { return &cachingRepo{ path: path, initRepo: initRepo, + fetcher: fetcher, } } @@ -226,7 +225,6 @@ func (r *cachingRepo) Versions(ctx context.Context, prefix string) (*Versions, e v, err := r.versionsCache.Do(prefix, func() (*Versions, error) { return r.repo(ctx).Versions(ctx, prefix) }) - if err != nil { return nil, err } @@ -263,7 +261,7 @@ func (r *cachingRepo) Stat(ctx context.Context, rev string) (*RevInfo, error) { }) } - if err := writeDiskStat(ctx, file, info); err != nil { + if err := writeDiskStat(ctx, file, info); err != nil && !isErrReadOnlyFS(err) { fmt.Fprintf(os.Stderr, "go: writing stat cache: %v\n", err) } } @@ -309,7 +307,7 @@ func (r *cachingRepo) GoMod(ctx context.Context, version string) ([]byte, error) return r.repo(ctx).GoMod(ctx, version) } text, err := r.gomodCache.Do(version, func() ([]byte, error) { - file, text, err := readDiskGoMod(ctx, r.path, version) + file, text, err := r.fetcher.readDiskGoMod(ctx, r.path, version) if err == nil { // Note: readDiskGoMod already called checkGoMod. return text, nil @@ -317,10 +315,10 @@ func (r *cachingRepo) GoMod(ctx context.Context, version string) ([]byte, error) text, err = r.repo(ctx).GoMod(ctx, version) if err == nil { - if err := checkGoMod(r.path, version, text); err != nil { + if err := checkGoMod(r.fetcher, r.path, version, text); err != nil { return text, err } - if err := writeDiskGoMod(ctx, file, text); err != nil { + if err := writeDiskGoMod(ctx, file, text); err != nil && !isErrReadOnlyFS(err) { fmt.Fprintf(os.Stderr, "go: writing go.mod cache: %v\n", err) } } @@ -341,7 +339,7 @@ func (r *cachingRepo) Zip(ctx context.Context, dst io.Writer, version string) er // InfoFile is like Lookup(ctx, path).Stat(version) but also returns the name of the file // containing the cached information. -func InfoFile(ctx context.Context, path, version string) (*RevInfo, string, error) { +func (f *Fetcher) InfoFile(ctx context.Context, path, version string) (*RevInfo, string, error) { if !gover.ModIsValid(path, version) { return nil, "", fmt.Errorf("invalid version %q", version) } @@ -353,7 +351,7 @@ func InfoFile(ctx context.Context, path, version string) (*RevInfo, string, erro var info *RevInfo var err2info map[error]*RevInfo err := TryProxies(func(proxy string) error { - i, err := Lookup(ctx, proxy, path).Stat(ctx, version) + i, err := f.Lookup(ctx, proxy, path).Stat(ctx, version) if err == nil { info = i } else { @@ -379,7 +377,7 @@ func InfoFile(ctx context.Context, path, version string) (*RevInfo, string, erro // GoMod is like Lookup(ctx, path).GoMod(rev) but avoids the // repository path resolution in Lookup if the result is // already cached on local disk. -func GoMod(ctx context.Context, path, rev string) ([]byte, error) { +func (f *Fetcher) GoMod(ctx context.Context, path, rev string) ([]byte, error) { // Convert commit hash to pseudo-version // to increase cache hit rate. if !gover.ModIsValid(path, rev) { @@ -390,7 +388,7 @@ func GoMod(ctx context.Context, path, rev string) ([]byte, error) { return nil, err } err := TryProxies(func(proxy string) error { - info, err := Lookup(ctx, proxy, path).Stat(ctx, rev) + info, err := f.Lookup(ctx, proxy, path).Stat(ctx, rev) if err == nil { rev = info.Version } @@ -402,13 +400,13 @@ func GoMod(ctx context.Context, path, rev string) ([]byte, error) { } } - _, data, err := readDiskGoMod(ctx, path, rev) + _, data, err := f.readDiskGoMod(ctx, path, rev) if err == nil { return data, nil } err = TryProxies(func(proxy string) (err error) { - data, err = Lookup(ctx, proxy, path).GoMod(ctx, rev) + data, err = f.Lookup(ctx, proxy, path).GoMod(ctx, rev) return err }) return data, err @@ -416,11 +414,11 @@ func GoMod(ctx context.Context, path, rev string) ([]byte, error) { // GoModFile is like GoMod but returns the name of the file containing // the cached information. -func GoModFile(ctx context.Context, path, version string) (string, error) { +func (f *Fetcher) GoModFile(ctx context.Context, path, version string) (string, error) { if !gover.ModIsValid(path, version) { return "", fmt.Errorf("invalid version %q", version) } - if _, err := GoMod(ctx, path, version); err != nil { + if _, err := f.GoMod(ctx, path, version); err != nil { return "", err } // GoMod should have populated the disk cache for us. @@ -433,11 +431,11 @@ func GoModFile(ctx context.Context, path, version string) (string, error) { // GoModSum returns the go.sum entry for the module version's go.mod file. // (That is, it returns the entry listed in go.sum as "path version/go.mod".) -func GoModSum(ctx context.Context, path, version string) (string, error) { +func (f *Fetcher) GoModSum(ctx context.Context, path, version string) (string, error) { if !gover.ModIsValid(path, version) { return "", fmt.Errorf("invalid version %q", version) } - data, err := GoMod(ctx, path, version) + data, err := f.GoMod(ctx, path, version) if err != nil { return "", err } @@ -495,7 +493,7 @@ func readDiskStat(ctx context.Context, path, rev string) (file string, info *Rev // Remarshal and update the cache file if needed. data2, err := json.Marshal(info) if err == nil && !bytes.Equal(data2, data) { - writeDiskCache(ctx, file, data) + writeDiskCache(ctx, file, data2) } return file, info, nil } @@ -565,7 +563,7 @@ var oldVgoPrefix = []byte("//vgo 0.0.") // returning the name of the cache file and the result. // If the read fails, the caller can use // writeDiskGoMod(file, data) to write a new cache entry. -func readDiskGoMod(ctx context.Context, path, rev string) (file string, data []byte, err error) { +func (f *Fetcher) readDiskGoMod(ctx context.Context, path, rev string) (file string, data []byte, err error) { if gover.IsToolchain(path) { return "", nil, errNotCached } @@ -578,7 +576,7 @@ func readDiskGoMod(ctx context.Context, path, rev string) (file string, data []b } if err == nil { - if err := checkGoMod(path, rev, data); err != nil { + if err := checkGoMod(f, path, rev, data); err != nil { return "", nil, err } } @@ -622,10 +620,11 @@ func writeDiskStat(ctx context.Context, file string, info *RevInfo) error { o := *info.Origin info.Origin = &o - // Tags never matter if you are starting with a semver version, + // Tags and RepoSum never matter if you are starting with a semver version, // as we would be when finding this cache entry. o.TagSum = "" o.TagPrefix = "" + o.RepoSum = "" // Ref doesn't matter if you have a pseudoversion. if module.IsPseudoVersion(info.Version) { o.Ref = "" @@ -652,13 +651,13 @@ func writeDiskCache(ctx context.Context, file string, data []byte) error { return nil } // Make sure directory for file exists. - if err := os.MkdirAll(filepath.Dir(file), 0777); err != nil { + if err := os.MkdirAll(filepath.Dir(file), 0o777); err != nil { return err } // Write the file to a temporary location, and then rename it to its final // path to reduce the likelihood of a corrupt file existing at that final path. - f, err := tempFile(ctx, filepath.Dir(file), filepath.Base(file), 0666) + f, err := tempFile(ctx, filepath.Dir(file), filepath.Base(file), 0o666) if err != nil { return err } @@ -688,6 +687,24 @@ func writeDiskCache(ctx context.Context, file string, data []byte) error { return nil } +// isErrReadOnlyFS reports whether err is a read-only filesystem error +// (syscall.EROFS on Unix/wasip1, ERROR_NOT_SUPPORTED on Windows). +func isErrReadOnlyFS(err error) bool { + switch runtime.GOOS { + case "plan9": + return false + case "windows": + const ERROR_NOT_SUPPORTED = 50 + return errors.Is(err, syscall.Errno(ERROR_NOT_SUPPORTED)) + case "wasip1": + const EROFS = 69 + return errors.Is(err, syscall.Errno(EROFS)) + default: // unix and js + const EROFS = 30 + return errors.Is(err, syscall.Errno(EROFS)) + } +} + // tempFile creates a new temporary file with given permission bits. func tempFile(ctx context.Context, dir, prefix string, perm fs.FileMode) (f *os.File, err error) { for i := 0; i < 10000; i++ { @@ -759,7 +776,7 @@ func rewriteVersionList(ctx context.Context, dir string) (err error) { } if fi, err := f.Stat(); err == nil && int(fi.Size()) == buf.Len() { old := make([]byte, buf.Len()+1) - if n, err := f.ReadAt(old, 0); err == io.EOF && n == buf.Len() && bytes.Equal(buf.Bytes(), old) { + if n, err := f.ReadAt(old, 0); err == io.EOF && n == buf.Len() && bytes.Equal(buf.Bytes(), old[:n]) { return nil // No edit needed. } } @@ -811,7 +828,7 @@ func checkCacheDir(ctx context.Context) error { statCacheErr = fmt.Errorf("could not create module cache: %w", err) return } - if err := os.MkdirAll(cfg.GOMODCACHE, 0777); err != nil { + if err := os.MkdirAll(cfg.GOMODCACHE, 0o777); err != nil { statCacheErr = fmt.Errorf("could not create module cache: %w", err) return } diff --git a/src/cmd/go/internal/modfetch/cache_readonly_test.go b/src/cmd/go/internal/modfetch/cache_readonly_test.go new file mode 100644 index 00000000000000..588dd60913d8a3 --- /dev/null +++ b/src/cmd/go/internal/modfetch/cache_readonly_test.go @@ -0,0 +1,31 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build !plan9 && !windows + +package modfetch + +import ( + "fmt" + "syscall" + "testing" +) + +func TestIsErrReadOnlyFS(t *testing.T) { + if isErrReadOnlyFS(nil) { + t.Error("isErrReadOnlyFS(nil) = true, want false") + } + if isErrReadOnlyFS(fmt.Errorf("some error")) { + t.Error("isErrReadOnlyFS(non-EROFS) = true, want false") + } + if !isErrReadOnlyFS(syscall.EROFS) { + t.Error("isErrReadOnlyFS(syscall.EROFS) = false, want true") + } + if !isErrReadOnlyFS(fmt.Errorf("wrapped: %w", syscall.EROFS)) { + t.Error("isErrReadOnlyFS(wrapped EROFS) = false, want true") + } + if isErrReadOnlyFS(syscall.EACCES) { + t.Error("isErrReadOnlyFS(syscall.EACCES) = true, want false") + } +} diff --git a/src/cmd/go/internal/modfetch/codehost/codehost.go b/src/cmd/go/internal/modfetch/codehost/codehost.go index edb87e4089144b..08b1216d6bfa29 100644 --- a/src/cmd/go/internal/modfetch/codehost/codehost.go +++ b/src/cmd/go/internal/modfetch/codehost/codehost.go @@ -116,9 +116,12 @@ type Origin struct { Ref string `json:",omitempty"` // If RepoSum is non-empty, then the resolution of this module version - // failed due to the repo being available but the version not being present. - // This depends on the entire state of the repo, which RepoSum summarizes. - // For Git, this is a hash of all the refs and their hashes. + // depends on the entire state of the repo, which RepoSum summarizes. + // For Git, this is a hash of all the refs and their hashes, and the RepoSum + // is only needed for module versions that don't exist. + // For Mercurial, this is a hash of all the branches and their heads' hashes, + // since the set of available tags is dervied from .hgtags files in those branches, + // and the RepoSum is used for all module versions, available and not, RepoSum string `json:",omitempty"` } diff --git a/src/cmd/go/internal/modfetch/codehost/git.go b/src/cmd/go/internal/modfetch/codehost/git.go index 74c4c646cdc582..13e8799361f29f 100644 --- a/src/cmd/go/internal/modfetch/codehost/git.go +++ b/src/cmd/go/internal/modfetch/codehost/git.go @@ -17,6 +17,7 @@ import ( "os" "os/exec" "path/filepath" + "regexp" "runtime" "slices" "sort" @@ -91,9 +92,21 @@ func newGitRepo(ctx context.Context, remote string, local bool) (Repo, error) { break } } + gitSupportsSHA256, gitVersErr := gitSupportsSHA256() + if gitVersErr != nil { + return nil, fmt.Errorf("unable to resolve git version: %w", gitVersErr) + } objFormatFlag := []string{} + // If git is sufficiently recent to support sha256, + // always initialize with an explicit object-format. if repoSha256Hash { + // We always set --object-format=sha256 if the repo + // we're cloning uses sha256 hashes because if the git + // version is too old, it'll fail either way, so we + // might as well give it one last chance. objFormatFlag = []string{"--object-format=sha256"} + } else if gitSupportsSHA256 { + objFormatFlag = []string{"--object-format=sha1"} } if _, err := Run(ctx, r.dir, "git", "init", "--bare", objFormatFlag); err != nil { os.RemoveAll(r.dir) @@ -248,13 +261,13 @@ func (r *gitRepo) loadRefs(ctx context.Context) (map[string]string, error) { r.refsErr = err return } - out, gitErr := r.runGit(ctx, "git", "ls-remote", "-q", r.remote) + out, gitErr := r.runGit(ctx, "git", "ls-remote", "-q", "--end-of-options", r.remote) release() if gitErr != nil { if rerr, ok := gitErr.(*RunError); ok { if bytes.Contains(rerr.Stderr, []byte("fatal: could not read Username")) { - rerr.HelpText = "Confirm the import path was entered correctly.\nIf this is a private repository, see https://golang.org/doc/faq#git_https for additional information." + rerr.HelpText = "Confirm the import path was entered correctly.\nIf this is a private repository, see https://go.dev/doc/faq#git_https for additional information." } } @@ -389,7 +402,7 @@ func (r *gitRepo) Latest(ctx context.Context) (*RevInfo, error) { func (r *gitRepo) checkConfigSHA256(ctx context.Context) bool { if hashType, sha256CfgErr := r.runGit(ctx, "git", "config", "extensions.objectformat"); sha256CfgErr == nil { - return "sha256" == strings.TrimSpace(string(hashType)) + return strings.TrimSpace(string(hashType)) == "sha256" } return false } @@ -517,7 +530,7 @@ func (r *gitRepo) stat(ctx context.Context, rev string) (info *RevInfo, err erro if fromTag && !slices.Contains(info.Tags, tag) { // The local repo includes the commit hash we want, but it is missing // the corresponding tag. Add that tag and try again. - _, err := r.runGit(ctx, "git", "tag", tag, hash) + _, err := r.runGit(ctx, "git", "tag", "--end-of-options", tag, hash) if err != nil { return nil, err } @@ -566,7 +579,7 @@ func (r *gitRepo) stat(ctx context.Context, rev string) (info *RevInfo, err erro // an apparent Git bug introduced in Git 2.21 (commit 61c771), // which causes the handler for protocol version 1 to sometimes miss // tags that point to the requested commit (see https://go.dev/issue/56881). - _, err = r.runGit(ctx, "git", "-c", "protocol.version=2", "fetch", "-f", "--depth=1", r.remote, refspec) + _, err = r.runGit(ctx, "git", "-c", "protocol.version=2", "fetch", "-f", "--depth=1", "--end-of-options", r.remote, refspec) release() if err == nil { @@ -612,12 +625,12 @@ func (r *gitRepo) fetchRefsLocked(ctx context.Context) error { } defer release() - if _, err := r.runGit(ctx, "git", "fetch", "-f", r.remote, "refs/heads/*:refs/heads/*", "refs/tags/*:refs/tags/*"); err != nil { + if _, err := r.runGit(ctx, "git", "fetch", "-f", "--end-of-options", r.remote, "refs/heads/*:refs/heads/*", "refs/tags/*:refs/tags/*"); err != nil { return err } if _, err := os.Stat(filepath.Join(r.dir, "shallow")); err == nil { - if _, err := r.runGit(ctx, "git", "fetch", "--unshallow", "-f", r.remote); err != nil { + if _, err := r.runGit(ctx, "git", "fetch", "--unshallow", "-f", "--end-of-options", r.remote); err != nil { return err } } @@ -630,7 +643,7 @@ func (r *gitRepo) fetchRefsLocked(ctx context.Context) error { // statLocal returns a new RevInfo describing rev in the local git repository. // It uses version as info.Version. func (r *gitRepo) statLocal(ctx context.Context, version, rev string) (*RevInfo, error) { - out, err := r.runGit(ctx, "git", "-c", "log.showsignature=false", "log", "--no-decorate", "-n1", "--format=format:%H %ct %D", rev, "--") + out, err := r.runGit(ctx, "git", "-c", "log.showsignature=false", "log", "--no-decorate", "-n1", "--format=format:%H %ct %D", "--end-of-options", rev, "--") if err != nil { // Return info with Origin.RepoSum if possible to allow caching of negative lookup. var info *RevInfo @@ -720,7 +733,7 @@ func (r *gitRepo) ReadFile(ctx context.Context, rev, file string, maxSize int64) if err != nil { return nil, err } - out, err := r.runGit(ctx, "git", "cat-file", "blob", info.Name+":"+file) + out, err := r.runGit(ctx, "git", "cat-file", "--end-of-options", "blob", info.Name+":"+file) if err != nil { return nil, fs.ErrNotExist } @@ -738,7 +751,7 @@ func (r *gitRepo) RecentTag(ctx context.Context, rev, prefix string, allowed fun // result is definitive. describe := func() (definitive bool) { var out []byte - out, err = r.runGit(ctx, "git", "for-each-ref", "--format", "%(refname)", "refs/tags", "--merged", rev) + out, err = r.runGit(ctx, "git", "for-each-ref", "--format=%(refname)", "--merged="+rev) if err != nil { return true } @@ -794,15 +807,18 @@ func (r *gitRepo) RecentTag(ctx context.Context, rev, prefix string, allowed fun // There are plausible tags, but we don't know if rev is a descendent of any of them. // Fetch the history to find out. + // Note: do not use defer unlock, because describe calls allowed, + // which uses retracted, which calls ReadFile, which may end up + // back at a method that acquires r.mu. unlock, err := r.mu.Lock() if err != nil { return "", err } - defer unlock() - if err := r.fetchRefsLocked(ctx); err != nil { + unlock() return "", err } + unlock() // If we've reached this point, we have all of the commits that are reachable // from all heads and tags. @@ -887,7 +903,7 @@ func (r *gitRepo) ReadZip(ctx context.Context, rev, subdir string, maxSize int64 // TODO: Use maxSize or drop it. args := []string{} if subdir != "" { - args = append(args, "--", subdir) + args = append(args, subdir) } info, err := r.Stat(ctx, rev) // download rev into local git repo if err != nil { @@ -909,7 +925,7 @@ func (r *gitRepo) ReadZip(ctx context.Context, rev, subdir string, maxSize int64 // text file line endings. Setting -c core.autocrlf=input means only // translate files on the way into the repo, not on the way out (archive). // The -c core.eol=lf should be unnecessary but set it anyway. - archive, err := r.runGit(ctx, "git", "-c", "core.autocrlf=input", "-c", "core.eol=lf", "archive", "--format=zip", "--prefix=prefix/", info.Name, args) + archive, err := r.runGit(ctx, "git", "-c", "core.autocrlf=input", "-c", "core.eol=lf", "archive", "--format=zip", "--prefix=prefix/", "--end-of-options", info.Name, args) if err != nil { if bytes.Contains(err.(*RunError).Stderr, []byte("did not match any files")) { return nil, fs.ErrNotExist @@ -969,3 +985,36 @@ func (r *gitRepo) runGit(ctx context.Context, cmdline ...any) ([]byte, error) { } return RunWithArgs(ctx, args) } + +// Capture the major, minor and (optionally) patch version, but ignore anything later +var gitVersLineExtract = regexp.MustCompile(`git version\s+(\d+\.\d+(?:\.\d+)?)`) + +func gitVersion() (string, error) { + gitOut, runErr := exec.Command("git", "version").CombinedOutput() + if runErr != nil { + return "v0", fmt.Errorf("failed to execute git version: %w", runErr) + } + return extractGitVersion(gitOut) +} + +func extractGitVersion(gitOut []byte) (string, error) { + matches := gitVersLineExtract.FindSubmatch(gitOut) + if len(matches) < 2 { + return "v0", fmt.Errorf("git version extraction regexp did not match version line: %q", gitOut) + } + return "v" + string(matches[1]), nil +} + +func hasAtLeastGitVersion(minVers string) (bool, error) { + gitVers, gitVersErr := gitVersion() + if gitVersErr != nil { + return false, gitVersErr + } + return semver.Compare(minVers, gitVers) <= 0, nil +} + +const minGitSHA256Vers = "v2.29" + +func gitSupportsSHA256() (bool, error) { + return hasAtLeastGitVersion(minGitSHA256Vers) +} diff --git a/src/cmd/go/internal/modfetch/codehost/git_test.go b/src/cmd/go/internal/modfetch/codehost/git_test.go index e8884abdfedb60..8ea3f9157cbb26 100644 --- a/src/cmd/go/internal/modfetch/codehost/git_test.go +++ b/src/cmd/go/internal/modfetch/codehost/git_test.go @@ -24,6 +24,8 @@ import ( "sync" "testing" "time" + + "golang.org/x/mod/semver" ) func TestMain(m *testing.M) { @@ -42,7 +44,7 @@ var altRepos = func() []string { } } -// TODO: Convert gitrepo1 to svn, bzr, fossil and add tests. +// TODO: Convert gitrepo1 to svn and fossil and add tests. // For now, at least the hgrepo1 tests check the general vcs.go logic. // localGitRepo is like gitrepo1 but allows archive access @@ -192,19 +194,56 @@ func testRepo(ctx context.Context, t *testing.T, remote string) (Repo, error) { return NewRepo(ctx, vcsName, remote, false) } -func TestTags(t *testing.T) { +func TestExtractGitVersion(t *testing.T) { t.Parallel() + for _, tbl := range []struct { + in, exp string + }{ + {in: "git version 2.52.0.rc2", exp: "v2.52.0"}, + {in: "git version 2.52.0.38.g5e6e4854e0", exp: "v2.52.0"}, + {in: "git version 2.51.2", exp: "v2.51.2"}, + {in: "git version 1.5.0.5.GIT", exp: "v1.5.0"}, + {in: "git version 1.5.1-rc3.GIT", exp: "v1.5.1"}, + {in: "git version 1.5.2.GIT", exp: "v1.5.2"}, + {in: "git version 2.43.0.rc2.23.gc3cc3e1da7", exp: "v2.43.0"}, + } { + t.Run(tbl.exp, func(t *testing.T) { + out, extrErr := extractGitVersion([]byte(tbl.in)) + if extrErr != nil { + t.Errorf("failed to extract git version from %q: %s", tbl.in, extrErr) + } + if out != tbl.exp { + t.Errorf("unexpected git version extractGitVersion(%q) = %q; want %q", tbl.in, out, tbl.exp) + } + }) + } +} + +func TestTags(t *testing.T) { + + gitVers, gitVersErr := gitVersion() + if gitVersErr != nil { + t.Logf("git version check failed: %s", gitVersErr) + } type tagsTest struct { repo string prefix string tags []Tag + // Override the git default hash for a few cases to make sure + // we handle all 3 reasonable states. + defGitHash string } runTest := func(tt tagsTest) func(*testing.T) { return func(t *testing.T) { - t.Parallel() + if tt.repo == gitsha256repo && semver.Compare(gitVers, minGitSHA256Vers) < 0 { + t.Skipf("git version is too old (%+v); skipping git sha256 test", gitVers) + } ctx := testContext(t) + if tt.defGitHash != "" { + t.Setenv("GIT_DEFAULT_HASH", tt.defGitHash) + } r, err := testRepo(ctx, t, tt.repo) if err != nil { @@ -221,27 +260,37 @@ func TestTags(t *testing.T) { } for _, tt := range []tagsTest{ - {gitrepo1, "xxx", []Tag{}}, + {gitrepo1, "xxx", []Tag{}, ""}, + {gitrepo1, "xxx", []Tag{}, "sha256"}, + {gitrepo1, "xxx", []Tag{}, "sha1"}, {gitrepo1, "", []Tag{ {"v1.2.3", "ede458df7cd0fdca520df19a33158086a8a68e81"}, {"v1.2.4-annotated", "ede458df7cd0fdca520df19a33158086a8a68e81"}, {"v2.0.1", "76a00fb249b7f93091bc2c89a789dab1fc1bc26f"}, {"v2.0.2", "9d02800338b8a55be062c838d1f02e0c5780b9eb"}, {"v2.3", "76a00fb249b7f93091bc2c89a789dab1fc1bc26f"}, - }}, + }, ""}, {gitrepo1, "v", []Tag{ {"v1.2.3", "ede458df7cd0fdca520df19a33158086a8a68e81"}, {"v1.2.4-annotated", "ede458df7cd0fdca520df19a33158086a8a68e81"}, {"v2.0.1", "76a00fb249b7f93091bc2c89a789dab1fc1bc26f"}, {"v2.0.2", "9d02800338b8a55be062c838d1f02e0c5780b9eb"}, {"v2.3", "76a00fb249b7f93091bc2c89a789dab1fc1bc26f"}, - }}, + }, ""}, + {gitrepo1, "v1", []Tag{ + {"v1.2.3", "ede458df7cd0fdca520df19a33158086a8a68e81"}, + {"v1.2.4-annotated", "ede458df7cd0fdca520df19a33158086a8a68e81"}, + }, ""}, {gitrepo1, "v1", []Tag{ {"v1.2.3", "ede458df7cd0fdca520df19a33158086a8a68e81"}, {"v1.2.4-annotated", "ede458df7cd0fdca520df19a33158086a8a68e81"}, - }}, - {gitrepo1, "2", []Tag{}}, - {gitsha256repo, "xxx", []Tag{}}, + }, "sha256"}, + {gitrepo1, "v1", []Tag{ + {"v1.2.3", "ede458df7cd0fdca520df19a33158086a8a68e81"}, + {"v1.2.4-annotated", "ede458df7cd0fdca520df19a33158086a8a68e81"}, + }, "sha1"}, + {gitrepo1, "2", []Tag{}, ""}, + {gitsha256repo, "xxx", []Tag{}, ""}, {gitsha256repo, "", []Tag{ {"v1.2.3", "47b8b51b2a2d9d5caa3d460096c4e01f05700ce3a9390deb54400bd508214c5c"}, {"v1.2.4-annotated", "47b8b51b2a2d9d5caa3d460096c4e01f05700ce3a9390deb54400bd508214c5c"}, @@ -249,7 +298,7 @@ func TestTags(t *testing.T) { {"v2.0.1", "b7550fd9d2129c724c39ae0536e8b2fae4364d8c82bb8b0880c9b71f67295d09"}, {"v2.0.2", "1401e4e1fdb4169b51d44a1ff62af63ccc708bf5c12d15051268b51bbb6cbd82"}, {"v2.3", "b7550fd9d2129c724c39ae0536e8b2fae4364d8c82bb8b0880c9b71f67295d09"}, - }}, + }, ""}, {gitsha256repo, "v", []Tag{ {"v1.2.3", "47b8b51b2a2d9d5caa3d460096c4e01f05700ce3a9390deb54400bd508214c5c"}, {"v1.2.4-annotated", "47b8b51b2a2d9d5caa3d460096c4e01f05700ce3a9390deb54400bd508214c5c"}, @@ -257,13 +306,23 @@ func TestTags(t *testing.T) { {"v2.0.1", "b7550fd9d2129c724c39ae0536e8b2fae4364d8c82bb8b0880c9b71f67295d09"}, {"v2.0.2", "1401e4e1fdb4169b51d44a1ff62af63ccc708bf5c12d15051268b51bbb6cbd82"}, {"v2.3", "b7550fd9d2129c724c39ae0536e8b2fae4364d8c82bb8b0880c9b71f67295d09"}, - }}, + }, ""}, + {gitsha256repo, "v1", []Tag{ + {"v1.2.3", "47b8b51b2a2d9d5caa3d460096c4e01f05700ce3a9390deb54400bd508214c5c"}, + {"v1.2.4-annotated", "47b8b51b2a2d9d5caa3d460096c4e01f05700ce3a9390deb54400bd508214c5c"}, + {"v1.3.0", "a9157cad2aa6dc2f78aa31fced5887f04e758afa8703f04d0178702ebf04ee17"}, + }, ""}, + {gitsha256repo, "v1", []Tag{ + {"v1.2.3", "47b8b51b2a2d9d5caa3d460096c4e01f05700ce3a9390deb54400bd508214c5c"}, + {"v1.2.4-annotated", "47b8b51b2a2d9d5caa3d460096c4e01f05700ce3a9390deb54400bd508214c5c"}, + {"v1.3.0", "a9157cad2aa6dc2f78aa31fced5887f04e758afa8703f04d0178702ebf04ee17"}, + }, "sha1"}, {gitsha256repo, "v1", []Tag{ {"v1.2.3", "47b8b51b2a2d9d5caa3d460096c4e01f05700ce3a9390deb54400bd508214c5c"}, {"v1.2.4-annotated", "47b8b51b2a2d9d5caa3d460096c4e01f05700ce3a9390deb54400bd508214c5c"}, {"v1.3.0", "a9157cad2aa6dc2f78aa31fced5887f04e758afa8703f04d0178702ebf04ee17"}, - }}, - {gitsha256repo, "2", []Tag{}}, + }, "sha256"}, + {gitsha256repo, "2", []Tag{}, ""}, } { t.Run(path.Base(tt.repo)+"/"+tt.prefix, runTest(tt)) if tt.repo == gitrepo1 { @@ -288,6 +347,11 @@ func TestTags(t *testing.T) { func TestLatest(t *testing.T) { t.Parallel() + gitVers, gitVersErr := gitVersion() + if gitVersErr != nil { + t.Logf("git version check failed: %s", gitVersErr) + } + type latestTest struct { repo string info *RevInfo @@ -297,6 +361,10 @@ func TestLatest(t *testing.T) { t.Parallel() ctx := testContext(t) + if tt.repo == gitsha256repo && semver.Compare(gitVers, minGitSHA256Vers) < 0 { + t.Skipf("git version is too old (%+v); skipping git sha256 test", gitVers) + } + r, err := testRepo(ctx, t, tt.repo) if err != nil { t.Fatal(err) @@ -350,12 +418,13 @@ func TestLatest(t *testing.T) { Origin: &Origin{ VCS: "hg", URL: hgrepo1, - Hash: "18518c07eb8ed5c80221e997e518cccaa8c0c287", + Ref: "tip", + Hash: "745aacc8b24decc44ac2b13870f5472b479f4d72", }, - Name: "18518c07eb8ed5c80221e997e518cccaa8c0c287", - Short: "18518c07eb8e", - Version: "18518c07eb8ed5c80221e997e518cccaa8c0c287", - Time: time.Date(2018, 6, 27, 16, 16, 30, 0, time.UTC), + Name: "745aacc8b24decc44ac2b13870f5472b479f4d72", + Short: "745aacc8b24d", + Version: "745aacc8b24decc44ac2b13870f5472b479f4d72", + Time: time.Date(2018, 6, 27, 16, 16, 10, 0, time.UTC), }, }, } { @@ -375,6 +444,11 @@ func TestLatest(t *testing.T) { func TestReadFile(t *testing.T) { t.Parallel() + gitVers, gitVersErr := gitVersion() + if gitVersErr != nil { + t.Logf("git version check failed: %s", gitVersErr) + } + type readFileTest struct { repo string rev string @@ -387,6 +461,10 @@ func TestReadFile(t *testing.T) { t.Parallel() ctx := testContext(t) + if tt.repo == gitsha256repo && semver.Compare(gitVers, minGitSHA256Vers) < 0 { + t.Skipf("git version is too old (%+v); skipping git sha256 test", gitVers) + } + r, err := testRepo(ctx, t, tt.repo) if err != nil { t.Fatal(err) @@ -468,6 +546,11 @@ type zipFile struct { func TestReadZip(t *testing.T) { t.Parallel() + gitVers, gitVersErr := gitVersion() + if gitVersErr != nil { + t.Logf("git version check failed: %s", gitVersErr) + } + type readZipTest struct { repo string rev string @@ -480,6 +563,10 @@ func TestReadZip(t *testing.T) { t.Parallel() ctx := testContext(t) + if tt.repo == gitsha256repo && semver.Compare(gitVers, minGitSHA256Vers) < 0 { + t.Skipf("git version is too old (%+v); skipping git sha256 test", gitVers) + } + r, err := testRepo(ctx, t, tt.repo) if err != nil { t.Fatal(err) @@ -630,7 +717,6 @@ func TestReadZip(t *testing.T) { subdir: "", files: map[string]uint64{ "prefix/.hg_archival.txt": ^uint64(0), - "prefix/.hgtags": 405, "prefix/v3/sub/dir/file.txt": 16, "prefix/README": 0, }, @@ -743,16 +829,21 @@ func TestReadZip(t *testing.T) { } var hgmap = map[string]string{ - "HEAD": "41964ddce1180313bdc01d0a39a2813344d6261d", // not tip due to bad hgrepo1 conversion - "9d02800338b8a55be062c838d1f02e0c5780b9eb": "8f49ee7a6ddcdec6f0112d9dca48d4a2e4c3c09e", - "76a00fb249b7f93091bc2c89a789dab1fc1bc26f": "88fde824ec8b41a76baa16b7e84212cee9f3edd0", - "ede458df7cd0fdca520df19a33158086a8a68e81": "41964ddce1180313bdc01d0a39a2813344d6261d", - "97f6aa59c81c623494825b43d39e445566e429a4": "c0cbbfb24c7c3c50c35c7b88e7db777da4ff625d", + "HEAD": "c0186fb00e50985709b12266419f50bf11860166", + "9d02800338b8a55be062c838d1f02e0c5780b9eb": "b1ed98abc2683d326f89b924875bf14bd584898e", // v2.0.2, v2 + "76a00fb249b7f93091bc2c89a789dab1fc1bc26f": "a546811101e11d6aff2ac72072d2d439b3a88f33", // v2.3, v2.0.1 + "ede458df7cd0fdca520df19a33158086a8a68e81": "c0186fb00e50985709b12266419f50bf11860166", // v1.2.3, v1.2.4-annotated + "97f6aa59c81c623494825b43d39e445566e429a4": "c1638e3673b121d9c83e92166fce2a25dcadd6cb", // foo.txt commit on v2.3.4 branch } func TestStat(t *testing.T) { t.Parallel() + gitVers, gitVersErr := gitVersion() + if gitVersErr != nil { + t.Logf("git version check failed: %s", gitVersErr) + } + type statTest struct { repo string rev string @@ -764,6 +855,10 @@ func TestStat(t *testing.T) { t.Parallel() ctx := testContext(t) + if tt.repo == gitsha256repo && semver.Compare(gitVers, minGitSHA256Vers) < 0 { + t.Skipf("git version is too old (%+v); skipping git sha256 test", gitVers) + } + r, err := testRepo(ctx, t, tt.repo) if err != nil { t.Fatal(err) diff --git a/src/cmd/go/internal/modfetch/codehost/vcs.go b/src/cmd/go/internal/modfetch/codehost/vcs.go index d80397502b422d..0ca1bd1dcbb98d 100644 --- a/src/cmd/go/internal/modfetch/codehost/vcs.go +++ b/src/cmd/go/internal/modfetch/codehost/vcs.go @@ -17,12 +17,16 @@ import ( "strconv" "strings" "sync" + "sync/atomic" "time" "cmd/go/internal/base" + "cmd/go/internal/cfg" "cmd/go/internal/lockedfile" "cmd/go/internal/str" "cmd/internal/par" + + "golang.org/x/mod/semver" ) // A VCSError indicates an error using a version control system. @@ -80,6 +84,13 @@ type vcsRepo struct { fetchOnce sync.Once fetchErr error + fetched atomic.Bool + + repoSumOnce sync.Once + repoSum string + + statCache par.ErrCache[string, *RevInfo] // cache key is revision + readFileCache par.ErrCache[[2]string, []byte] // cache key is revision and file path } func newVCSRepo(ctx context.Context, vcs, remote string, local bool) (Repo, error) { @@ -129,6 +140,9 @@ func newVCSRepo(ctx context.Context, vcs, remote string, local bool) (Repo, erro return nil, err } _, err = Run(ctx, r.dir, cmd.init(r.remote)) + if err == nil && cmd.postInit != nil { + err = cmd.postInit(ctx, r) + } release() if err != nil { @@ -142,20 +156,29 @@ func newVCSRepo(ctx context.Context, vcs, remote string, local bool) (Repo, erro const vcsWorkDirType = "vcs1." type vcsCmd struct { - vcs string // vcs name "hg" - init func(remote string) []string // cmd to init repo to track remote - tags func(remote string) []string // cmd to list local tags - tagRE *lazyregexp.Regexp // regexp to extract tag names from output of tags cmd - branches func(remote string) []string // cmd to list local branches - branchRE *lazyregexp.Regexp // regexp to extract branch names from output of tags cmd - badLocalRevRE *lazyregexp.Regexp // regexp of names that must not be served out of local cache without doing fetch first - statLocal func(rev, remote string) []string // cmd to stat local rev - parseStat func(rev, out string) (*RevInfo, error) // cmd to parse output of statLocal - fetch []string // cmd to fetch everything from remote - latest string // name of latest commit on remote (tip, HEAD, etc) - readFile func(rev, file, remote string) []string // cmd to read rev's file - readZip func(rev, subdir, remote, target string) []string // cmd to read rev's subdir as zip file - doReadZip func(ctx context.Context, dst io.Writer, workDir, rev, subdir, remote string) error // arbitrary function to read rev's subdir as zip file + vcs string // vcs name "hg" + init func(remote string) []string // cmd to init repo to track remote + postInit func(context.Context, *vcsRepo) error // func to init repo after .init runs + repoSum func(remote string) []string // cmd to calculate reposum of remote repo + lookupRef func(remote, ref string) []string // cmd to look up ref in remote repo + tags func(remote string) []string // cmd to list local tags + tagsNeedsFetch bool // run fetch before tags + tagRE *lazyregexp.Regexp // regexp to extract tag names from output of tags cmd + branches func(remote string) []string // cmd to list local branches + branchesNeedsFetch bool // run branches before tags + branchRE *lazyregexp.Regexp // regexp to extract branch names from output of tags cmd + badLocalRevRE *lazyregexp.Regexp // regexp of names that must not be served out of local cache without doing fetch first + statLocal func(rev, remote string) []string // cmd to stat local rev + parseStat func(rev, out string) (*RevInfo, error) // func to parse output of statLocal + fetch []string // cmd to fetch everything from remote + latest string // name of latest commit on remote (tip, HEAD, etc) + descendsFrom func(rev, tag string) []string // cmd to check whether rev descends from tag + recentTags func(rev string) []string // cmd to print tag ancestors of rev + readFile func(rev, file, remote string) []string // cmd to read rev's file + readZip func(rev, subdir, remote, target string) []string // cmd to read rev's subdir as zip file + + // arbitrary function to read rev's subdir as zip file + doReadZip func(ctx context.Context, dst io.Writer, workDir, rev, subdir, remote string) error } var re = lazyregexp.New @@ -163,33 +186,61 @@ var re = lazyregexp.New var vcsCmds = map[string]*vcsCmd{ "hg": { vcs: "hg", + repoSum: func(remote string) []string { + return []string{ + "hg", + "--config=extensions.goreposum=" + filepath.Join(cfg.GOROOT, "lib/hg/goreposum.py"), + "goreposum", + "--", + remote, + } + }, + lookupRef: func(remote, ref string) []string { + return []string{ + "hg", + "--config=extensions.goreposum=" + filepath.Join(cfg.GOROOT, "lib/hg/goreposum.py"), + "golookup", + "--", + remote, + ref, + } + }, init: func(remote string) []string { - return []string{"hg", "clone", "-U", "--", remote, "."} + return []string{"hg", "init", "."} }, + postInit: hgAddRemote, tags: func(remote string) []string { return []string{"hg", "tags", "-q"} }, - tagRE: re(`(?m)^[^\n]+$`), + tagsNeedsFetch: true, + tagRE: re(`(?m)^[^\n]+$`), branches: func(remote string) []string { return []string{"hg", "branches", "-c", "-q"} }, - branchRE: re(`(?m)^[^\n]+$`), - badLocalRevRE: re(`(?m)^(tip)$`), + branchesNeedsFetch: true, + branchRE: re(`(?m)^[^\n]+$`), + badLocalRevRE: re(`(?m)^(tip)$`), statLocal: func(rev, remote string) []string { - return []string{"hg", "log", "-l1", "-r", rev, "--template", "{node} {date|hgdate} {tags}"} + return []string{"hg", "log", "-l1", fmt.Sprintf("--rev=%s", rev), "--template", "{node} {date|hgdate} {tags}"} }, parseStat: hgParseStat, fetch: []string{"hg", "pull", "-f"}, latest: "tip", + descendsFrom: func(rev, tag string) []string { + return []string{"hg", "log", "--rev=ancestors(" + rev + ") and " + tag} + }, + recentTags: func(rev string) []string { + return []string{"hg", "log", "--rev=ancestors(" + rev + ") and tag()", "--template", "{tags}\n"} + }, readFile: func(rev, file, remote string) []string { - return []string{"hg", "cat", "-r", rev, file} + return []string{"hg", "cat", fmt.Sprintf("--rev=%s", rev), "--", file} }, readZip: func(rev, subdir, remote, target string) []string { pattern := []string{} if subdir != "" { - pattern = []string{"-I", subdir + "/**"} + pattern = []string{fmt.Sprintf("--include=%s", subdir+"/**")} } - return str.StringList("hg", "archive", "-t", "zip", "--no-decode", "-r", rev, "--prefix=prefix/", pattern, "--", target) + return str.StringList("hg", "archive", "-t", "zip", "--no-decode", fmt.Sprintf("--rev=%s", rev), "--prefix=prefix/", pattern, "--", target) }, }, @@ -215,36 +266,6 @@ var vcsCmds = map[string]*vcsCmd{ doReadZip: svnReadZip, }, - "bzr": { - vcs: "bzr", - init: func(remote string) []string { - return []string{"bzr", "branch", "--use-existing-dir", "--", remote, "."} - }, - fetch: []string{ - "bzr", "pull", "--overwrite-tags", - }, - tags: func(remote string) []string { - return []string{"bzr", "tags"} - }, - tagRE: re(`(?m)^\S+`), - badLocalRevRE: re(`^revno:-`), - statLocal: func(rev, remote string) []string { - return []string{"bzr", "log", "-l1", "--long", "--show-ids", "-r", rev} - }, - parseStat: bzrParseStat, - latest: "revno:-1", - readFile: func(rev, file, remote string) []string { - return []string{"bzr", "cat", "-r", rev, file} - }, - readZip: func(rev, subdir, remote, target string) []string { - extra := []string{} - if subdir != "" { - extra = []string{"./" + subdir} - } - return str.StringList("bzr", "export", "--format=zip", "-r", rev, "--root=prefix/", "--", target, extra) - }, - }, - "fossil": { vcs: "fossil", init: func(remote string) []string { @@ -256,17 +277,17 @@ var vcsCmds = map[string]*vcsCmd{ }, tagRE: re(`XXXTODO`), statLocal: func(rev, remote string) []string { - return []string{"fossil", "info", "-R", ".fossil", rev} + return []string{"fossil", "info", "-R", ".fossil", "--", rev} }, parseStat: fossilParseStat, latest: "trunk", readFile: func(rev, file, remote string) []string { - return []string{"fossil", "cat", "-R", ".fossil", "-r", rev, file} + return []string{"fossil", "cat", "-R", ".fossil", fmt.Sprintf("-r=%s", rev), "--", file} }, readZip: func(rev, subdir, remote, target string) []string { extra := []string{} if subdir != "" && !strings.ContainsAny(subdir, "*?[],") { - extra = []string{"--include", subdir} + extra = []string{fmt.Sprintf("--include=%s", subdir)} } // Note that vcsRepo.ReadZip below rewrites this command // to run in a different directory, to work around a fossil bug. @@ -276,6 +297,10 @@ var vcsCmds = map[string]*vcsCmd{ } func (r *vcsRepo) loadTags(ctx context.Context) { + if r.cmd.tagsNeedsFetch { + r.fetchOnce.Do(func() { r.fetch(ctx) }) + } + out, err := Run(ctx, r.dir, r.cmd.tags(r.remote)) if err != nil { return @@ -296,6 +321,10 @@ func (r *vcsRepo) loadBranches(ctx context.Context) { return } + if r.cmd.branchesNeedsFetch { + r.fetchOnce.Do(func() { r.fetch(ctx) }) + } + out, err := Run(ctx, r.dir, r.cmd.branches(r.remote)) if err != nil { return @@ -310,7 +339,84 @@ func (r *vcsRepo) loadBranches(ctx context.Context) { } } +func (r *vcsRepo) loadRepoSum(ctx context.Context) { + if r.cmd.repoSum == nil { + return + } + where := r.remote + if r.fetched.Load() { + where = "." // use local repo + } + out, err := Run(ctx, r.dir, r.cmd.repoSum(where)) + if err != nil { + return + } + r.repoSum = strings.TrimSpace(string(out)) +} + +func (r *vcsRepo) lookupRef(ctx context.Context, ref string) (string, error) { + if r.cmd.lookupRef == nil { + return "", fmt.Errorf("no lookupRef") + } + out, err := Run(ctx, r.dir, r.cmd.lookupRef(r.remote, ref)) + if err != nil { + return "", err + } + return strings.TrimSpace(string(out)), nil +} + +// repoSumOrigin returns an Origin containing a RepoSum. +func (r *vcsRepo) repoSumOrigin(ctx context.Context) *Origin { + origin := &Origin{ + VCS: r.cmd.vcs, + URL: r.remote, + RepoSum: r.repoSum, + } + r.repoSumOnce.Do(func() { r.loadRepoSum(ctx) }) + origin.RepoSum = r.repoSum + return origin +} + func (r *vcsRepo) CheckReuse(ctx context.Context, old *Origin, subdir string) error { + if old == nil { + return fmt.Errorf("missing origin") + } + if old.VCS != r.cmd.vcs || old.URL != r.remote { + return fmt.Errorf("origin moved from %v %q to %v %q", old.VCS, old.URL, r.cmd.vcs, r.remote) + } + if old.Subdir != subdir { + return fmt.Errorf("origin moved from %v %q %q to %v %q %q", old.VCS, old.URL, old.Subdir, r.cmd.vcs, r.remote, subdir) + } + + if old.Ref == "" && old.RepoSum == "" && old.Hash != "" { + // Hash has to remain in repo. + hash, err := r.lookupRef(ctx, old.Hash) + if err == nil && hash == old.Hash { + return nil + } + if err != nil { + return fmt.Errorf("looking up hash: %v", err) + } + return fmt.Errorf("hash changed") // weird but maybe they made a tag + } + + if old.Ref != "" && old.RepoSum == "" { + hash, err := r.lookupRef(ctx, old.Ref) + if err == nil && hash != "" && hash == old.Hash { + return nil + } + } + + r.repoSumOnce.Do(func() { r.loadRepoSum(ctx) }) + if r.repoSum != "" { + if old.RepoSum == "" { + return fmt.Errorf("non-specific origin") + } + if old.RepoSum != r.repoSum { + return fmt.Errorf("repo changed") + } + return nil + } return fmt.Errorf("vcs %s: CheckReuse: %w", r.cmd.vcs, errors.ErrUnsupported) } @@ -323,14 +429,8 @@ func (r *vcsRepo) Tags(ctx context.Context, prefix string) (*Tags, error) { r.tagsOnce.Do(func() { r.loadTags(ctx) }) tags := &Tags{ - // None of the other VCS provide a reasonable way to compute TagSum - // without downloading the whole repo, so we only include VCS and URL - // in the Origin. - Origin: &Origin{ - VCS: r.cmd.vcs, - URL: r.remote, - }, - List: []Tag{}, + Origin: r.repoSumOrigin(ctx), + List: []Tag{}, } for tag := range r.tags { if strings.HasPrefix(tag, prefix) { @@ -344,40 +444,42 @@ func (r *vcsRepo) Tags(ctx context.Context, prefix string) (*Tags, error) { } func (r *vcsRepo) Stat(ctx context.Context, rev string) (*RevInfo, error) { - unlock, err := r.mu.Lock() - if err != nil { - return nil, err - } - defer unlock() + return r.statCache.Do(rev, func() (*RevInfo, error) { + unlock, err := r.mu.Lock() + if err != nil { + return nil, err + } + defer unlock() - if rev == "latest" { - rev = r.cmd.latest - } - r.branchesOnce.Do(func() { r.loadBranches(ctx) }) - if r.local { - // Ignore the badLocalRevRE precondition in local only mode. - // We cannot fetch latest upstream changes so only serve what's in the local cache. - return r.statLocal(ctx, rev) - } - revOK := (r.cmd.badLocalRevRE == nil || !r.cmd.badLocalRevRE.MatchString(rev)) && !r.branches[rev] - if revOK { - if info, err := r.statLocal(ctx, rev); err == nil { - return info, nil + if rev == "latest" { + rev = r.cmd.latest + } + r.branchesOnce.Do(func() { r.loadBranches(ctx) }) + if r.local { + // Ignore the badLocalRevRE precondition in local only mode. + // We cannot fetch latest upstream changes so only serve what's in the local cache. + return r.statLocal(ctx, rev) + } + revOK := (r.cmd.badLocalRevRE == nil || !r.cmd.badLocalRevRE.MatchString(rev)) && !r.branches[rev] + if revOK { + if info, err := r.statLocal(ctx, rev); err == nil { + return info, nil + } } - } - r.fetchOnce.Do(func() { r.fetch(ctx) }) - if r.fetchErr != nil { - return nil, r.fetchErr - } - info, err := r.statLocal(ctx, rev) - if err != nil { - return nil, err - } - if !revOK { - info.Version = info.Name - } - return info, nil + r.fetchOnce.Do(func() { r.fetch(ctx) }) + if r.fetchErr != nil { + return nil, r.fetchErr + } + info, err := r.statLocal(ctx, rev) + if err != nil { + return info, err + } + if !revOK { + info.Version = info.Name + } + return info, nil + }) } func (r *vcsRepo) fetch(ctx context.Context) { @@ -389,13 +491,15 @@ func (r *vcsRepo) fetch(ctx context.Context) { } _, r.fetchErr = Run(ctx, r.dir, r.cmd.fetch) release() + r.fetched.Store(true) } } func (r *vcsRepo) statLocal(ctx context.Context, rev string) (*RevInfo, error) { out, err := Run(ctx, r.dir, r.cmd.statLocal(rev, r.remote)) if err != nil { - return nil, &UnknownRevisionError{Rev: rev} + info := &RevInfo{Origin: r.repoSumOrigin(ctx)} + return info, &UnknownRevisionError{Rev: rev} } info, err := r.cmd.parseStat(rev, string(out)) if err != nil { @@ -406,6 +510,10 @@ func (r *vcsRepo) statLocal(ctx context.Context, rev string) (*RevInfo, error) { } info.Origin.VCS = r.cmd.vcs info.Origin.URL = r.remote + info.Origin.Ref = rev + if strings.HasPrefix(info.Name, rev) && len(rev) >= 12 { + info.Origin.Ref = "" // duplicates Hash + } return info, nil } @@ -414,39 +522,62 @@ func (r *vcsRepo) Latest(ctx context.Context) (*RevInfo, error) { } func (r *vcsRepo) ReadFile(ctx context.Context, rev, file string, maxSize int64) ([]byte, error) { - if rev == "latest" { - rev = r.cmd.latest - } - _, err := r.Stat(ctx, rev) // download rev into local repo - if err != nil { - return nil, err - } + return r.readFileCache.Do([2]string{rev, file}, func() ([]byte, error) { + if rev == "latest" { + rev = r.cmd.latest + } + _, err := r.Stat(ctx, rev) // download rev into local repo + if err != nil { + return nil, err + } - // r.Stat acquires r.mu, so lock after that. - unlock, err := r.mu.Lock() - if err != nil { - return nil, err - } - defer unlock() + // r.Stat acquires r.mu, so lock after that. + unlock, err := r.mu.Lock() + if err != nil { + return nil, err + } + defer unlock() - out, err := Run(ctx, r.dir, r.cmd.readFile(rev, file, r.remote)) - if err != nil { - return nil, fs.ErrNotExist - } - return out, nil + out, err := Run(ctx, r.dir, r.cmd.readFile(rev, file, r.remote)) + if err != nil { + return nil, fs.ErrNotExist + } + return out, nil + }) } func (r *vcsRepo) RecentTag(ctx context.Context, rev, prefix string, allowed func(string) bool) (tag string, err error) { - // We don't technically need to lock here since we're returning an error - // unconditionally, but doing so anyway will help to avoid baking in - // lock-inversion bugs. + // Only lock for the subprocess execution, not for the tag scan. + // allowed may call other methods that acquire the lock. unlock, err := r.mu.Lock() if err != nil { return "", err } - defer unlock() - return "", vcsErrorf("vcs %s: RecentTag: %w", r.cmd.vcs, errors.ErrUnsupported) + if r.cmd.recentTags == nil { + unlock() + return "", vcsErrorf("vcs %s: RecentTag: %w", r.cmd.vcs, errors.ErrUnsupported) + } + out, err := Run(ctx, r.dir, r.cmd.recentTags(rev)) + unlock() + if err != nil { + return "", err + } + + highest := "" + for _, tag := range strings.Fields(string(out)) { + if !strings.HasPrefix(tag, prefix) || !allowed(tag) { + continue + } + semtag := tag[len(prefix):] + if semver.Compare(semtag, highest) > 0 { + highest = semtag + } + } + if highest != "" { + return prefix + highest, nil + } + return "", nil } func (r *vcsRepo) DescendsFrom(ctx context.Context, rev, tag string) (bool, error) { @@ -456,7 +587,15 @@ func (r *vcsRepo) DescendsFrom(ctx context.Context, rev, tag string) (bool, erro } defer unlock() - return false, vcsErrorf("vcs %s: DescendsFrom: %w", r.cmd.vcs, errors.ErrUnsupported) + if r.cmd.descendsFrom == nil { + return false, vcsErrorf("vcs %s: DescendsFrom: %w", r.cmd.vcs, errors.ErrUnsupported) + } + + out, err := Run(ctx, r.dir, r.cmd.descendsFrom(rev, tag)) + if err != nil { + return false, err + } + return strings.TrimSpace(string(out)) != "", nil } func (r *vcsRepo) ReadZip(ctx context.Context, rev, subdir string, maxSize int64) (zip io.ReadCloser, err error) { @@ -464,15 +603,20 @@ func (r *vcsRepo) ReadZip(ctx context.Context, rev, subdir string, maxSize int64 return nil, vcsErrorf("vcs %s: ReadZip: %w", r.cmd.vcs, errors.ErrUnsupported) } + if rev == "latest" { + rev = r.cmd.latest + } + _, err = r.Stat(ctx, rev) // download rev into local repo + if err != nil { + return nil, err + } + unlock, err := r.mu.Lock() if err != nil { return nil, err } defer unlock() - if rev == "latest" { - rev = r.cmd.latest - } f, err := os.CreateTemp("", "go-readzip-*.zip") if err != nil { return nil, err @@ -521,6 +665,11 @@ func (d *deleteCloser) Close() error { return d.File.Close() } +func hgAddRemote(ctx context.Context, r *vcsRepo) error { + // Write .hg/hgrc with remote URL in it. + return os.WriteFile(filepath.Join(r.dir, ".hg/hgrc"), []byte(fmt.Sprintf("[paths]\ndefault = %s\n", r.remote)), 0666) +} + func hgParseStat(rev, out string) (*RevInfo, error) { f := strings.Fields(out) if len(f) < 3 { @@ -545,9 +694,7 @@ func hgParseStat(rev, out string) (*RevInfo, error) { sort.Strings(tags) info := &RevInfo{ - Origin: &Origin{ - Hash: hash, - }, + Origin: &Origin{Hash: hash}, Name: hash, Short: ShortenSHA1(hash), Time: time.Unix(t, 0).UTC(), @@ -557,62 +704,6 @@ func hgParseStat(rev, out string) (*RevInfo, error) { return info, nil } -func bzrParseStat(rev, out string) (*RevInfo, error) { - var revno int64 - var tm time.Time - var tags []string - for line := range strings.SplitSeq(out, "\n") { - if line == "" || line[0] == ' ' || line[0] == '\t' { - // End of header, start of commit message. - break - } - if line[0] == '-' { - continue - } - before, after, found := strings.Cut(line, ":") - if !found { - // End of header, start of commit message. - break - } - key, val := before, strings.TrimSpace(after) - switch key { - case "revno": - if j := strings.Index(val, " "); j >= 0 { - val = val[:j] - } - i, err := strconv.ParseInt(val, 10, 64) - if err != nil { - return nil, vcsErrorf("unexpected revno from bzr log: %q", line) - } - revno = i - case "timestamp": - j := strings.Index(val, " ") - if j < 0 { - return nil, vcsErrorf("unexpected timestamp from bzr log: %q", line) - } - t, err := time.Parse("2006-01-02 15:04:05 -0700", val[j+1:]) - if err != nil { - return nil, vcsErrorf("unexpected timestamp from bzr log: %q", line) - } - tm = t.UTC() - case "tags": - tags = strings.Split(val, ", ") - } - } - if revno == 0 || tm.IsZero() { - return nil, vcsErrorf("unexpected response from bzr log: %q", out) - } - - info := &RevInfo{ - Name: strconv.FormatInt(revno, 10), - Short: fmt.Sprintf("%012d", revno), - Time: tm, - Version: rev, - Tags: tags, - } - return info, nil -} - func fossilParseStat(rev, out string) (*RevInfo, error) { for line := range strings.SplitSeq(out, "\n") { if strings.HasPrefix(line, "uuid:") || strings.HasPrefix(line, "hash:") { @@ -630,9 +721,7 @@ func fossilParseStat(rev, out string) (*RevInfo, error) { version = hash // extend to full hash } info := &RevInfo{ - Origin: &Origin{ - Hash: hash, - }, + Origin: &Origin{Hash: hash}, Name: hash, Short: ShortenSHA1(hash), Time: t, diff --git a/src/cmd/go/internal/modfetch/coderepo.go b/src/cmd/go/internal/modfetch/coderepo.go index 3df469d28525fa..7cec96a307012d 100644 --- a/src/cmd/go/internal/modfetch/coderepo.go +++ b/src/cmd/go/internal/modfetch/coderepo.go @@ -384,6 +384,9 @@ func (r *codeRepo) convert(ctx context.Context, info *codehost.RevInfo, statVers } else { origin.TagPrefix = tags.Origin.TagPrefix origin.TagSum = tags.Origin.TagSum + if tags.Origin.RepoSum != "" { + origin.RepoSum = tags.Origin.RepoSum + } } } }() diff --git a/src/cmd/go/internal/modfetch/coderepo_test.go b/src/cmd/go/internal/modfetch/coderepo_test.go index 68594746601a22..04a821df09d1e7 100644 --- a/src/cmd/go/internal/modfetch/coderepo_test.go +++ b/src/cmd/go/internal/modfetch/coderepo_test.go @@ -36,7 +36,6 @@ func TestMain(m *testing.M) { } func testMain(m *testing.M) (err error) { - cfg.GOPROXY = "direct" // The sum database is populated using a released version of the go command, @@ -56,7 +55,7 @@ func testMain(m *testing.M) (err error) { }() cfg.GOMODCACHE = filepath.Join(dir, "modcache") - if err := os.Mkdir(cfg.GOMODCACHE, 0755); err != nil { + if err := os.Mkdir(cfg.GOMODCACHE, 0o755); err != nil { return err } @@ -116,7 +115,7 @@ var codeRepoTests = []codeRepoTest{ "pkg/p.go", }, zipSum: "h1:zVEjciLdlk/TPWCOyZo7k24T+tOKRQC+u8MKq/xS80I=", - zipFileHash: "738a00ddbfe8c329dce6b48e1f23c8e22a92db50f3cfb2653caa0d62676bc09c", + zipFileHash: "f2a1cc87156efcb18e6b2822aba5173da336bf0e9b6b627b764a93a950240e50", }, { vcs: "git", @@ -132,7 +131,7 @@ var codeRepoTests = []codeRepoTest{ "pkg/p.go", }, zipSum: "h1:nOznk2xKsLGkTnXe0q9t1Ewt9jxK+oadtafSUqHM3Ec=", - zipFileHash: "bacb08f391e29d2eaaef8281b5c129ee6d890e608ee65877e0003c0181a766c8", + zipFileHash: "aba60ce70cfc0bb8d58d717f2cfdce227725bc574549b10120b24541c780a8e8", }, { vcs: "git", @@ -154,7 +153,7 @@ var codeRepoTests = []codeRepoTest{ "pkg/p.go", }, zipSum: "h1:e040hOoWGeuJLawDjK9DW6med+cz9FxMFYDMOVG8ctQ=", - zipFileHash: "74caab65cfbea427c341fa815f3bb0378681d8f0e3cf62a7f207014263ec7be3", + zipFileHash: "76fa92777b77fabd24c421ce209f383bca782efbca61c4ebd82564a7acdf502c", }, { vcs: "git", @@ -180,7 +179,7 @@ var codeRepoTests = []codeRepoTest{ "pkg/p.go", }, zipSum: "h1:e040hOoWGeuJLawDjK9DW6med+cz9FxMFYDMOVG8ctQ=", - zipFileHash: "74caab65cfbea427c341fa815f3bb0378681d8f0e3cf62a7f207014263ec7be3", + zipFileHash: "76fa92777b77fabd24c421ce209f383bca782efbca61c4ebd82564a7acdf502c", }, { vcs: "git", @@ -243,7 +242,7 @@ var codeRepoTests = []codeRepoTest{ "LICENSE", }, zipSum: "h1:iMsJ/9uQsk6MnZNnJK311f11QiSlmN92Q2aSjCywuJY=", - zipFileHash: "95801bfa69c5197ae809af512946d22f22850068527cd78100ae3f176bc8043b", + zipFileHash: "f3e031695245e3f5603df37e78e8779387e08235fede90c4a5a5816cb56337dd", }, { vcs: "git", @@ -261,7 +260,7 @@ var codeRepoTests = []codeRepoTest{ "pkg/p.go", }, zipSum: "h1:M69k7q+8bQ+QUpHov45Z/NoR8rj3DsQJUnXLWvf01+Q=", - zipFileHash: "58af45fb248d320ea471f568e006379e2b8d71d6d1663f9b19b2e00fd9ac9265", + zipFileHash: "daedaf1cc4b9d2ec2570accec696dcd6846acd83c18d5b8e70e3b56f9db6d0a2", }, { vcs: "git", @@ -273,7 +272,7 @@ var codeRepoTests = []codeRepoTest{ time: time.Date(2018, 2, 19, 23, 14, 23, 0, time.UTC), gomod: "module \"github.com/rsc/vgotest1/v2\" // root go.mod\n", zipSum: "h1:QmgYy/zt+uoWhDpcsgrSVzYFvKtBEjl5zT/FRz9GTzA=", - zipFileHash: "1aedf1546d322a0121879ddfd6d0e8bfbd916d2cafbeb538ddb440e04b04b9ef", + zipFileHash: "94edcb6035aa5666b1e69896c885ea1615ac33b8dc6dda848a4554db54497e59", }, { vcs: "git", @@ -305,7 +304,7 @@ var codeRepoTests = []codeRepoTest{ time: time.Date(2018, 2, 20, 0, 3, 59, 0, time.UTC), gomod: "module \"github.com/rsc/vgotest1/v2\" // v2/go.mod\n", zipSum: "h1:RIEb9q1SUSEQOzMn0zfl/LQxGFWlhWEAdeEguf1MLGU=", - zipFileHash: "7d92c2c328c5e9b0694101353705d5843746ec1d93a1e986d0da54c8a14dfe6d", + zipFileHash: "1025fed3207f0e276d0c22b683c31127086a318b9b7a988d02eb44a0d9fb37c8", }, { // redirect to github @@ -318,7 +317,7 @@ var codeRepoTests = []codeRepoTest{ time: time.Date(2018, 2, 14, 0, 45, 20, 0, time.UTC), gomod: "module \"rsc.io/quote\"\n", zipSum: "h1:haUSojyo3j2M9g7CEUFG8Na09dtn7QKxvPGaPVQdGwM=", - zipFileHash: "5c08ba2c09a364f93704aaa780e7504346102c6ef4fe1333a11f09904a732078", + zipFileHash: "da4f6166581725af8622e28d77791121f35ce86f8e1f96b4eb4730a9d21280d1", }, { // redirect to static hosting proxy @@ -340,7 +339,7 @@ var codeRepoTests = []codeRepoTest{ short: "4e4a3210bb54", time: time.Date(2018, 2, 8, 4, 12, 48, 0, time.UTC), zipSum: "h1:Yxu6pHX9X2RECiuw/Q5/4uvajuaowck8zOFKXgbfNBk=", - zipFileHash: "ac2c165a5c10aa5a7545dea60a08e019270b982fa6c8bdcb5943931de64922fe", + zipFileHash: "8977f765f19f226ca9d59ebc23dc0710368b05d39eeb8379a634b6d9960a9749", }, { vcs: "git", @@ -351,7 +350,7 @@ var codeRepoTests = []codeRepoTest{ short: "645ef00459ed", time: time.Date(2016, 9, 29, 1, 48, 1, 0, time.UTC), zipSum: "h1:WdK/asTD0HN+q6hsWO3/vpuAkAr+tw6aNJNDFFf0+qw=", - zipFileHash: "e4fa69ba057356614edbc1da881a7d3ebb688505be49f65965686bcb859e2fae", + zipFileHash: "4058869b083e374236200ac34308ed0e19ae25c84f4319e46ccbb15a1d71baa0", }, { // package in subdirectory - custom domain @@ -379,7 +378,7 @@ var codeRepoTests = []codeRepoTest{ time: time.Date(2018, 1, 9, 11, 43, 31, 0, time.UTC), gomod: "module gopkg.in/yaml.v2\n", zipSum: "h1:uUkhRGrsEyx/laRdeS6YIQKIys8pg+lRSRdVMTYjivs=", - zipFileHash: "7b0a141b1b0b49772ab4eecfd11dfd6609a94a5e868cab04a3abb1861ffaa877", + zipFileHash: "c3a03a46ec4ddb2595622e90f867ca61c4c04051cce1973f2aa13523b67e09f7", }, { vcs: "git", @@ -391,7 +390,7 @@ var codeRepoTests = []codeRepoTest{ time: time.Date(2016, 12, 8, 18, 13, 25, 0, time.UTC), gomod: "module gopkg.in/check.v1\n", zipSum: "h1:829vOVxxusYHC+IqBtkX5mbKtsY9fheQiQn0MZRVLfQ=", - zipFileHash: "9e7cb3f4f1e66d722306442b0dbe1f6f43d74d1736d54c510537bdfb1d6f432f", + zipFileHash: "a9476695abf2135504f33e5f76fd46492723cb3dd8f9cbe0270882090df043a5", }, { vcs: "git", @@ -403,7 +402,7 @@ var codeRepoTests = []codeRepoTest{ time: time.Date(2018, 4, 17, 19, 43, 22, 0, time.UTC), gomod: "module vcs-test.golang.org/go/mod/gitrepo1\n", zipSum: "h1:YJYZRsM9BHFTlVr8YADjT0cJH8uFIDtoc5NLiVqZEx8=", - zipFileHash: "c15e49d58b7a4c37966cbe5bc01a0330cd5f2927e990e1839bda1d407766d9c5", + zipFileHash: "1fef2c2388778e6db76820237a91af3d95ef5995e594a4a8967cfc8205261094", }, { vcs: "git", @@ -431,7 +430,7 @@ var codeRepoTests = []codeRepoTest{ time: time.Date(2019, 4, 3, 15, 52, 15, 0, time.UTC), gomod: "module vcs-test.golang.org/go/v2module/v2\n\ngo 1.12\n", zipSum: "h1:JItBZ+gwA5WvtZEGEbuDL4lUttGtLrs53lmdurq3bOg=", - zipFileHash: "9ea9ae1673cffcc44b7fdd3cc89953d68c102449b46c982dbf085e4f2e394da5", + zipFileHash: "5d1a9e8ae8a02f90f044343a485346c155b0b565a11cc27be6e0e304812d2c1f", }, { // Git branch with a semver name, +incompatible version, and no go.mod file. @@ -589,6 +588,7 @@ var codeRepoTests = []codeRepoTest{ func TestCodeRepo(t *testing.T) { testenv.MustHaveExternalNetwork(t) tmpdir := t.TempDir() + fetcher := NewFetcher() for _, tt := range codeRepoTests { f := func(tt codeRepoTest) func(t *testing.T) { @@ -603,7 +603,7 @@ func TestCodeRepo(t *testing.T) { } ctx := context.Background() - repo := Lookup(ctx, "direct", tt.path) + repo := fetcher.Lookup(ctx, "direct", tt.path) if tt.mpath == "" { tt.mpath = tt.path @@ -817,9 +817,8 @@ var codeRepoVersionsTests = []struct { func TestCodeRepoVersions(t *testing.T) { testenv.MustHaveExternalNetwork(t) - + fetcher := NewFetcher() for _, tt := range codeRepoVersionsTests { - tt := tt t.Run(strings.ReplaceAll(tt.path, "/", "_"), func(t *testing.T) { if strings.Contains(tt.path, "gopkg.in") { testenv.SkipFlaky(t, 54503) @@ -831,7 +830,7 @@ func TestCodeRepoVersions(t *testing.T) { } ctx := context.Background() - repo := Lookup(ctx, "direct", tt.path) + repo := fetcher.Lookup(ctx, "direct", tt.path) list, err := repo.Versions(ctx, tt.prefix) if err != nil { t.Fatalf("Versions(%q): %v", tt.prefix, err) @@ -898,7 +897,7 @@ var latestTests = []struct { func TestLatest(t *testing.T) { testenv.MustHaveExternalNetwork(t) - + fetcher := NewFetcher() for _, tt := range latestTests { name := strings.ReplaceAll(tt.path, "/", "_") t.Run(name, func(t *testing.T) { @@ -909,7 +908,7 @@ func TestLatest(t *testing.T) { } ctx := context.Background() - repo := Lookup(ctx, "direct", tt.path) + repo := fetcher.Lookup(ctx, "direct", tt.path) info, err := repo.Latest(ctx) if err != nil { if tt.err != "" { diff --git a/src/cmd/go/internal/modfetch/fetch.go b/src/cmd/go/internal/modfetch/fetch.go index 5d310ccbba90fa..74cbbe06468c8e 100644 --- a/src/cmd/go/internal/modfetch/fetch.go +++ b/src/cmd/go/internal/modfetch/fetch.go @@ -7,6 +7,15 @@ package modfetch import ( "archive/zip" "bytes" + "cmd/go/internal/base" + "cmd/go/internal/cfg" + "cmd/go/internal/fsys" + "cmd/go/internal/gover" + "cmd/go/internal/lockedfile" + "cmd/go/internal/str" + "cmd/go/internal/trace" + "cmd/internal/par" + "cmd/internal/robustio" "context" "crypto/sha256" "encoding/base64" @@ -20,48 +29,37 @@ import ( "strings" "sync" - "cmd/go/internal/base" - "cmd/go/internal/cfg" - "cmd/go/internal/fsys" - "cmd/go/internal/gover" - "cmd/go/internal/lockedfile" - "cmd/go/internal/str" - "cmd/go/internal/trace" - "cmd/internal/par" - "cmd/internal/robustio" - "golang.org/x/mod/module" "golang.org/x/mod/sumdb/dirhash" modzip "golang.org/x/mod/zip" ) -// The downloadCache is used to cache the operation of downloading a module to disk -// (if it's not already downloaded) and getting the directory it was downloaded to. -// It is important that downloadCache must not be accessed by any of the exported -// functions of this package after they return, because it can be modified by the -// non-thread-safe SetState function -var downloadCache = new(par.ErrCache[module.Version, string]) // version → directory; - -var ErrToolchain = errors.New("internal error: invalid operation on toolchain module") +var ( + ErrToolchain = errors.New("internal error: invalid operation on toolchain module") + ErrFIPS140 = errors.New("golang.org/fips140 is bundled with the Go distribution and cannot be downloaded") +) // Download downloads the specific module version to the // local download cache and returns the name of the directory // corresponding to the root of the module's file tree. -func Download(ctx context.Context, mod module.Version) (dir string, err error) { +func (f *Fetcher) Download(ctx context.Context, mod module.Version) (dir string, err error) { if gover.IsToolchain(mod.Path) { return "", ErrToolchain } + if mod.Path == "golang.org/fips140" { + return "", ErrFIPS140 + } if err := checkCacheDir(ctx); err != nil { base.Fatal(err) } // The par.Cache here avoids duplicate work. - return downloadCache.Do(mod, func() (string, error) { - dir, err := download(ctx, mod) + return f.downloadCache.Do(mod, func() (string, error) { + dir, err := f.download(ctx, mod) if err != nil { return "", err } - checkMod(ctx, mod) + f.checkMod(ctx, mod) // If go.mod exists (not an old legacy module), check version is not too new. if data, err := os.ReadFile(filepath.Join(dir, "go.mod")); err == nil { @@ -77,31 +75,82 @@ func Download(ctx context.Context, mod module.Version) (dir string, err error) { }) } -// Unzip is like Download but is given the explicit zip file to use, -// rather than downloading it. This is used for the GOFIPS140 zip files, -// which ship in the Go distribution itself. -func Unzip(ctx context.Context, mod module.Version, zipfile string) (dir string, err error) { +// Unzip is like Download but for GOFIPS140 zip files which ship with +// the Go distribution itself. +// +// Unzip performs a check like the go.sum check for downloaded modules: +// A cached copy of mod is used only if the module cache records ziphash +// as its module zip hash. As with go.sum, this rejects a cached copy +// that was populated from some other source; it does not detect +// modifications made to the module cache directory itself. +// +// Otherwise, any existing copy is discarded, zipfile is unpacked +// again, and ziphash is stamped upon success. +// +// If verify is non-nil, it is called before zipfile is unpacked. +// Unzip does not call verify when it returns a cached copy. +// +// If verify returns an error, the module cache is left untouched and +// Unzip returns that error. +// +// ziphash must be non-empty. +func (f *Fetcher) Unzip(ctx context.Context, mod module.Version, zipfile, ziphash string, verify func() error) (dir string, err error) { + if ziphash == "" { + return "", module.VersionError(mod, errors.New("internal error: Unzip called with empty module zip hash")) + } if err := checkCacheDir(ctx); err != nil { base.Fatal(err) } - return downloadCache.Do(mod, func() (string, error) { + return f.downloadCache.Do(mod, func() (string, error) { ctx, span := trace.StartSpan(ctx, "modfetch.Unzip "+mod.String()) defer span.Done() dir, err = DownloadDir(ctx, mod) if err == nil { // The directory has already been completely extracted (no .partial file exists). - return dir, nil + ok, err := haveZipHash(ctx, mod, ziphash) + if err != nil { + return "", err + } + if ok { + return dir, nil + } } else if dir == "" || !errors.Is(err, fs.ErrNotExist) { return "", err } - return unzip(ctx, mod, zipfile) + return unzip(ctx, mod, zipfile, ziphash, verify) }) } -func download(ctx context.Context, mod module.Version) (dir string, err error) { +func haveZipHash(ctx context.Context, mod module.Version, ziphash string) (bool, error) { + path, err := CachePath(ctx, mod, "ziphash") + if err != nil { + return false, err + } + data, err := lockedfile.Read(path) + if errors.Is(err, fs.ErrNotExist) { + return false, nil + } + if err != nil { + return false, err + } + return strings.TrimSpace(string(data)) == ziphash, nil +} + +func writeZipHash(ctx context.Context, mod module.Version, ziphash string) error { + path, err := CachePath(ctx, mod, "ziphash") + if err != nil { + return err + } + if err := os.MkdirAll(filepath.Dir(path), 0o777); err != nil { + return err + } + return lockedfile.Write(path, strings.NewReader(ziphash), 0o666) +} + +func (f *Fetcher) download(ctx context.Context, mod module.Version) (dir string, err error) { ctx, span := trace.StartSpan(ctx, "modfetch.download "+mod.String()) defer span.Done() @@ -116,15 +165,21 @@ func download(ctx context.Context, mod module.Version) (dir string, err error) { // To avoid cluttering the cache with extraneous files, // DownloadZip uses the same lockfile as Download. // Invoke DownloadZip before locking the file. - zipfile, err := DownloadZip(ctx, mod) + zipfile, err := f.DownloadZip(ctx, mod) if err != nil { return "", err } - return unzip(ctx, mod, zipfile) + return unzip(ctx, mod, zipfile, "", nil) } -func unzip(ctx context.Context, mod module.Version, zipfile string) (dir string, err error) { +// unzip extracts zipfile into the module cache directory for mod, +// unless a complete copy is already there (and, if ziphash is non-empty, +// the module cache records ziphash for it). +// +// If verify is non-nil, it is called once the decision to extract has +// been made, before any existing copy is discarded. +func unzip(ctx context.Context, mod module.Version, zipfile, ziphash string, verify func() error) (dir string, err error) { unlock, err := lockVersion(ctx, mod) if err != nil { return "", err @@ -137,10 +192,29 @@ func unzip(ctx context.Context, mod module.Version, zipfile string) (dir string, // Check whether the directory was populated while we were waiting on the lock. dir, dirErr := DownloadDir(ctx, mod) if dirErr == nil { - return dir, nil + if ziphash == "" { + return dir, nil + } + ok, err := haveZipHash(ctx, mod, ziphash) + if err != nil { + return "", err + } + if ok { + return dir, nil + } + dirErr = &DownloadDirPartialError{dir, errors.New("ziphash file does not match")} } _, dirExists := dirErr.(*DownloadDirPartialError) + // We are going to extract zipfile. Verify it first, while the module + // cache is still untouched, so that a bad zip file never costs us a + // cached copy and a good one is verified at most once per extraction. + if verify != nil { + if err := verify(); err != nil { + return "", err + } + } + // Clean up any remaining temporary directories created by old versions // (before 1.16), as well as partially extracted directories (indicated by // DownloadDirPartialError, usually because of a .partial file). This is only @@ -158,6 +232,19 @@ func unzip(ctx context.Context, mod module.Version, zipfile string) (dir string, return "", err } } + // Remove any recorded module zip hash before extracting, and record the + // new one only after the .partial file is removed (below). That way a + // .ziphash file for the module exists only beside a completely extracted + // directory, no matter where an unpack is interrupted. + if ziphash != "" { + hashPath, err := CachePath(ctx, mod, "ziphash") + if err != nil { + return "", err + } + if err := robustio.RemoveAll(hashPath); err != nil { + return "", err + } + } partialPath, err := CachePath(ctx, mod, "partial") if err != nil { @@ -178,10 +265,10 @@ func unzip(ctx context.Context, mod module.Version, zipfile string) (dir string, // Go 1.14.2 and higher respect .partial files. Older versions may use // partially extracted directories. 'go mod verify' can detect this, // and 'go clean -modcache' can fix it. - if err := os.MkdirAll(parentDir, 0777); err != nil { + if err := os.MkdirAll(parentDir, 0o777); err != nil { return "", err } - if err := os.WriteFile(partialPath, nil, 0666); err != nil { + if err := os.WriteFile(partialPath, nil, 0o666); err != nil { return "", err } if err := modzip.Unzip(dir, mod, zipfile); err != nil { @@ -194,6 +281,13 @@ func unzip(ctx context.Context, mod module.Version, zipfile string) (dir string, if err := os.Remove(partialPath); err != nil { return "", err } + // The directory is complete: record the module zip hash of the zip + // file it was extracted from. See the removal above. + if ziphash != "" { + if err := writeZipHash(ctx, mod, ziphash); err != nil { + return "", err + } + } if !cfg.ModCacheRW { makeDirsReadOnly(dir) @@ -205,7 +299,11 @@ var downloadZipCache par.ErrCache[module.Version, string] // DownloadZip downloads the specific module version to the // local zip cache and returns the name of the zip file. -func DownloadZip(ctx context.Context, mod module.Version) (zipfile string, err error) { +func (f *Fetcher) DownloadZip(ctx context.Context, mod module.Version) (zipfile string, err error) { + if mod.Path == "golang.org/fips140" { + return "", ErrFIPS140 + } + // The par.Cache here avoids duplicate work. return downloadZipCache.Do(mod, func() (string, error) { zipfile, err := CachePath(ctx, mod, "zip") @@ -214,9 +312,12 @@ func DownloadZip(ctx context.Context, mod module.Version) (zipfile string, err e } ziphashfile := zipfile + "hash" - // Return without locking if the zip and ziphash files exist. + // Return early if the zip and ziphash files exist. if _, err := os.Stat(zipfile); err == nil { if _, err := os.Stat(ziphashfile); err == nil { + if !HaveSum(f, mod) { + f.checkMod(ctx, mod) + } return zipfile, nil } } @@ -242,14 +343,14 @@ func DownloadZip(ctx context.Context, mod module.Version) (zipfile string, err e } defer unlock() - if err := downloadZip(ctx, mod, zipfile); err != nil { + if err := f.downloadZip(ctx, mod, zipfile); err != nil { return "", err } return zipfile, nil }) } -func downloadZip(ctx context.Context, mod module.Version, zipfile string) (err error) { +func (f *Fetcher) downloadZip(ctx context.Context, mod module.Version, zipfile string) (err error) { ctx, span := trace.StartSpan(ctx, "modfetch.downloadZip "+zipfile) defer span.Done() @@ -268,7 +369,7 @@ func downloadZip(ctx context.Context, mod module.Version, zipfile string) (err e } // Create parent directories. - if err := os.MkdirAll(filepath.Dir(zipfile), 0777); err != nil { + if err := os.MkdirAll(filepath.Dir(zipfile), 0o777); err != nil { return err } @@ -285,7 +386,7 @@ func downloadZip(ctx context.Context, mod module.Version, zipfile string) (err e // If the zip file exists, the ziphash file must have been deleted // or lost after a file system crash. Re-hash the zip without downloading. if zipExists { - return hashZip(mod, zipfile, ziphashfile) + return hashZip(f, mod, zipfile, ziphashfile) } // From here to the os.Rename call below is functionally almost equivalent to @@ -293,14 +394,14 @@ func downloadZip(ctx context.Context, mod module.Version, zipfile string) (err e // contents of the file (by hashing it) before we commit it. Because the file // is zip-compressed, we need an actual file — or at least an io.ReaderAt — to // validate it: we can't just tee the stream as we write it. - f, err := tempFile(ctx, filepath.Dir(zipfile), filepath.Base(zipfile), 0666) + file, err := tempFile(ctx, filepath.Dir(zipfile), filepath.Base(zipfile), 0o666) if err != nil { return err } defer func() { if err != nil { - f.Close() - os.Remove(f.Name()) + file.Close() + os.Remove(file.Name()) } }() @@ -309,18 +410,18 @@ func downloadZip(ctx context.Context, mod module.Version, zipfile string) (err e if unrecoverableErr != nil { return unrecoverableErr } - repo := Lookup(ctx, proxy, mod.Path) - err := repo.Zip(ctx, f, mod.Version) + repo := f.Lookup(ctx, proxy, mod.Path) + err := repo.Zip(ctx, file, mod.Version) if err != nil { // Zip may have partially written to f before failing. // (Perhaps the server crashed while sending the file?) // Since we allow fallback on error in some cases, we need to fix up the // file to be empty again for the next attempt. - if _, err := f.Seek(0, io.SeekStart); err != nil { + if _, err := file.Seek(0, io.SeekStart); err != nil { unrecoverableErr = err return err } - if err := f.Truncate(0); err != nil { + if err := file.Truncate(0); err != nil { unrecoverableErr = err return err } @@ -334,30 +435,30 @@ func downloadZip(ctx context.Context, mod module.Version, zipfile string) (err e // Double-check that the paths within the zip file are well-formed. // // TODO(bcmills): There is a similar check within the Unzip function. Can we eliminate one? - fi, err := f.Stat() + fi, err := file.Stat() if err != nil { return err } - z, err := zip.NewReader(f, fi.Size()) + z, err := zip.NewReader(file, fi.Size()) if err != nil { return err } prefix := mod.Path + "@" + mod.Version + "/" - for _, f := range z.File { - if !strings.HasPrefix(f.Name, prefix) { - return fmt.Errorf("zip for %s has unexpected file %s", prefix[:len(prefix)-1], f.Name) + for _, zf := range z.File { + if !strings.HasPrefix(zf.Name, prefix) { + return fmt.Errorf("zip for %s has unexpected file %s", prefix[:len(prefix)-1], zf.Name) } } - if err := f.Close(); err != nil { + if err := file.Close(); err != nil { return err } // Hash the zip file and check the sum before renaming to the final location. - if err := hashZip(mod, f.Name(), ziphashfile); err != nil { + if err := hashZip(f, mod, file.Name(), ziphashfile); err != nil { return err } - if err := os.Rename(f.Name(), zipfile); err != nil { + if err := os.Rename(file.Name(), zipfile); err != nil { return err } @@ -371,12 +472,12 @@ func downloadZip(ctx context.Context, mod module.Version, zipfile string) (err e // // If the hash does not match go.sum (or the sumdb if enabled), hashZip returns // an error and does not write ziphashfile. -func hashZip(mod module.Version, zipfile, ziphashfile string) (err error) { +func hashZip(f *Fetcher, mod module.Version, zipfile, ziphashfile string) (err error) { hash, err := dirhash.HashZip(zipfile, dirhash.DefaultHash) if err != nil { return err } - if err := checkModSum(mod, hash); err != nil { + if err := checkModSum(f, mod, hash); err != nil { return err } hf, err := lockedfile.Create(ziphashfile) @@ -408,7 +509,7 @@ func makeDirsReadOnly(dir string) { filepath.WalkDir(dir, func(path string, d fs.DirEntry, err error) error { if err == nil && d.IsDir() { info, err := d.Info() - if err == nil && info.Mode()&0222 != 0 { + if err == nil && info.Mode()&0o222 != 0 { dirs = append(dirs, pathMode{path, info.Mode()}) } } @@ -417,7 +518,7 @@ func makeDirsReadOnly(dir string) { // Run over list backward to chmod children before parents. for i := len(dirs) - 1; i >= 0; i-- { - os.Chmod(dirs[i].path, dirs[i].mode&^0222) + os.Chmod(dirs[i].path, dirs[i].mode&^0o222) } } @@ -430,7 +531,7 @@ func RemoveAll(dir string) error { return nil // ignore errors walking in file system } if info.IsDir() { - os.Chmod(path, 0777) + os.Chmod(path, 0o777) } return nil }) @@ -441,19 +542,11 @@ func RemoveAll(dir string) error { // accessed by any of the exported functions of this package after they return, because // they can be modified by the non-thread-safe SetState function. -var GoSumFile string // path to go.sum; set by package modload -var WorkspaceGoSumFiles []string // path to module go.sums in workspace; set by package modload - type modSum struct { mod module.Version sum string } -var goSum struct { - mu sync.Mutex - sumState -} - type sumState struct { m map[module.Version][]string // content of go.sum file w map[string]map[module.Version][]string // sum file in workspace -> content of that sum file @@ -466,26 +559,57 @@ type modSumStatus struct { used, dirty bool } -// State holds a snapshot of the global state of the modfetch package. -type State struct { - goSumFile string +// Fetcher holds a snapshot of the global state of the modfetch package. +type Fetcher struct { + // path to go.sum; set by package modload + goSumFile string + // path to module go.sums in workspace; set by package modload workspaceGoSumFiles []string - lookupCache *par.Cache[lookupCacheKey, Repo] - downloadCache *par.ErrCache[module.Version, string] - sumState sumState + // The Lookup cache is used cache the work done by Lookup. + // It is important that the global functions of this package that access it do not + // do so after they return. + lookupCache *par.Cache[lookupCacheKey, Repo] + // The downloadCache is used to cache the operation of downloading a module to disk + // (if it's not already downloaded) and getting the directory it was downloaded to. + // It is important that downloadCache must not be accessed by any of the exported + // functions of this package after they return, because it can be modified by the + // non-thread-safe SetState function. + downloadCache *par.ErrCache[module.Version, string] // version → directory; + + mu sync.Mutex + sumState sumState +} + +func NewFetcher() *Fetcher { + f := new(Fetcher) + f.lookupCache = new(par.Cache[lookupCacheKey, Repo]) + f.downloadCache = new(par.ErrCache[module.Version, string]) + return f +} + +func (f *Fetcher) GoSumFile() string { + return f.goSumFile +} + +func (f *Fetcher) SetGoSumFile(str string) { + f.goSumFile = str +} + +func (f *Fetcher) AddWorkspaceGoSumFile(file string) { + f.workspaceGoSumFiles = append(f.workspaceGoSumFiles, file) } // Reset resets globals in the modfetch package, so previous loads don't affect // contents of go.sum files. -func Reset() { - SetState(State{}) +func (f *Fetcher) Reset() { + f.SetState(NewFetcher()) } // SetState sets the global state of the modfetch package to the newState, and returns the previous // global state. newState should have been returned by SetState, or be an empty State. // There should be no concurrent calls to any of the exported functions of this package with // a call to SetState because it will modify the global state in a non-thread-safe way. -func SetState(newState State) (oldState State) { +func (f *Fetcher) SetState(newState *Fetcher) (oldState *Fetcher) { if newState.lookupCache == nil { newState.lookupCache = new(par.Cache[lookupCacheKey, Repo]) } @@ -493,26 +617,26 @@ func SetState(newState State) (oldState State) { newState.downloadCache = new(par.ErrCache[module.Version, string]) } - goSum.mu.Lock() - defer goSum.mu.Unlock() + f.mu.Lock() + defer f.mu.Unlock() - oldState = State{ - goSumFile: GoSumFile, - workspaceGoSumFiles: WorkspaceGoSumFiles, - lookupCache: lookupCache, - downloadCache: downloadCache, - sumState: goSum.sumState, + oldState = &Fetcher{ + goSumFile: f.goSumFile, + workspaceGoSumFiles: f.workspaceGoSumFiles, + lookupCache: f.lookupCache, + downloadCache: f.downloadCache, + sumState: f.sumState, } - GoSumFile = newState.goSumFile - WorkspaceGoSumFiles = newState.workspaceGoSumFiles + f.SetGoSumFile(newState.goSumFile) + f.workspaceGoSumFiles = newState.workspaceGoSumFiles // Uses of lookupCache and downloadCache both can call checkModSum, // which in turn sets the used bit on goSum.status for modules. // Set (or reset) them so used can be computed properly. - lookupCache = newState.lookupCache - downloadCache = newState.downloadCache + f.lookupCache = newState.lookupCache + f.downloadCache = newState.downloadCache // Set, or reset all fields on goSum. If being reset to empty, it will be initialized later. - goSum.sumState = newState.sumState + f.sumState = newState.sumState return oldState } @@ -521,28 +645,28 @@ func SetState(newState State) (oldState State) { // The boolean it returns reports whether the // use of go.sum is now enabled. // The goSum lock must be held. -func initGoSum() (bool, error) { - if GoSumFile == "" { +func (f *Fetcher) initGoSum() (bool, error) { + if f.goSumFile == "" { return false, nil } - if goSum.m != nil { + if f.sumState.m != nil { return true, nil } - goSum.m = make(map[module.Version][]string) - goSum.status = make(map[modSum]modSumStatus) - goSum.w = make(map[string]map[module.Version][]string) + f.sumState.m = make(map[module.Version][]string) + f.sumState.status = make(map[modSum]modSumStatus) + f.sumState.w = make(map[string]map[module.Version][]string) - for _, f := range WorkspaceGoSumFiles { - goSum.w[f] = make(map[module.Version][]string) - _, err := readGoSumFile(goSum.w[f], f) + for _, fn := range f.workspaceGoSumFiles { + f.sumState.w[fn] = make(map[module.Version][]string) + _, err := readGoSumFile(f.sumState.w[fn], fn) if err != nil { return false, err } } - enabled, err := readGoSumFile(goSum.m, GoSumFile) - goSum.enabled = enabled + enabled, err := readGoSumFile(f.sumState.m, f.goSumFile) + f.sumState.enabled = enabled return enabled, err } @@ -611,28 +735,28 @@ func readGoSum(dst map[module.Version][]string, file string, data []byte) { // The entry's hash must be generated with a known hash algorithm. // mod.Version may have a "/go.mod" suffix to distinguish sums for // .mod and .zip files. -func HaveSum(mod module.Version) bool { - goSum.mu.Lock() - defer goSum.mu.Unlock() - inited, err := initGoSum() +func HaveSum(f *Fetcher, mod module.Version) bool { + f.mu.Lock() + defer f.mu.Unlock() + inited, err := f.initGoSum() if err != nil || !inited { return false } - for _, goSums := range goSum.w { + for _, goSums := range f.sumState.w { for _, h := range goSums[mod] { if !strings.HasPrefix(h, "h1:") { continue } - if !goSum.status[modSum{mod, h}].dirty { + if !f.sumState.status[modSum{mod, h}].dirty { return true } } } - for _, h := range goSum.m[mod] { + for _, h := range f.sumState.m[mod] { if !strings.HasPrefix(h, "h1:") { continue } - if !goSum.status[modSum{mod, h}].dirty { + if !f.sumState.status[modSum{mod, h}].dirty { return true } } @@ -645,20 +769,20 @@ func HaveSum(mod module.Version) bool { // The entry's hash must be generated with a known hash algorithm. // mod.Version may have a "/go.mod" suffix to distinguish sums for // .mod and .zip files. -func RecordedSum(mod module.Version) (sum string, ok bool) { - goSum.mu.Lock() - defer goSum.mu.Unlock() - inited, err := initGoSum() +func (f *Fetcher) RecordedSum(mod module.Version) (sum string, ok bool) { + f.mu.Lock() + defer f.mu.Unlock() + inited, err := f.initGoSum() foundSum := "" if err != nil || !inited { return "", false } - for _, goSums := range goSum.w { + for _, goSums := range f.sumState.w { for _, h := range goSums[mod] { if !strings.HasPrefix(h, "h1:") { continue } - if !goSum.status[modSum{mod, h}].dirty { + if !f.sumState.status[modSum{mod, h}].dirty { if foundSum != "" && foundSum != h { // conflicting sums exist return "", false } @@ -666,11 +790,11 @@ func RecordedSum(mod module.Version) (sum string, ok bool) { } } } - for _, h := range goSum.m[mod] { + for _, h := range f.sumState.m[mod] { if !strings.HasPrefix(h, "h1:") { continue } - if !goSum.status[modSum{mod, h}].dirty { + if !f.sumState.status[modSum{mod, h}].dirty { if foundSum != "" && foundSum != h { // conflicting sums exist return "", false } @@ -681,7 +805,7 @@ func RecordedSum(mod module.Version) (sum string, ok bool) { } // checkMod checks the given module's checksum and Go version. -func checkMod(ctx context.Context, mod module.Version) { +func (f *Fetcher) checkMod(ctx context.Context, mod module.Version) { // Do the file I/O before acquiring the go.sum lock. ziphash, err := CachePath(ctx, mod, "ziphash") if err != nil { @@ -698,7 +822,7 @@ func checkMod(ctx context.Context, mod module.Version) { if err != nil { base.Fatalf("verifying %v", module.VersionError(mod, err)) } - err = hashZip(mod, zip, ziphash) + err = hashZip(f, mod, zip, ziphash) if err != nil { base.Fatalf("verifying %v", module.VersionError(mod, err)) } @@ -709,7 +833,7 @@ func checkMod(ctx context.Context, mod module.Version) { base.Fatalf("verifying %v", module.VersionError(mod, fmt.Errorf("unexpected ziphash: %q", h))) } - if err := checkModSum(mod, h); err != nil { + if err := checkModSum(f, mod, h); err != nil { base.Fatalf("%s", err) } } @@ -723,45 +847,44 @@ func goModSum(data []byte) (string, error) { // checkGoMod checks the given module's go.mod checksum; // data is the go.mod content. -func checkGoMod(path, version string, data []byte) error { +func checkGoMod(f *Fetcher, path, version string, data []byte) error { h, err := goModSum(data) if err != nil { return &module.ModuleError{Path: path, Version: version, Err: fmt.Errorf("verifying go.mod: %v", err)} } - return checkModSum(module.Version{Path: path, Version: version + "/go.mod"}, h) + return checkModSum(f, module.Version{Path: path, Version: version + "/go.mod"}, h) } // checkModSum checks that the recorded checksum for mod is h. // // mod.Version may have the additional suffix "/go.mod" to request the checksum // for the module's go.mod file only. -func checkModSum(mod module.Version, h string) error { +func checkModSum(f *Fetcher, mod module.Version, h string) error { // We lock goSum when manipulating it, // but we arrange to release the lock when calling checkSumDB, // so that parallel calls to checkModHash can execute parallel calls // to checkSumDB. // Check whether mod+h is listed in go.sum already. If so, we're done. - goSum.mu.Lock() - inited, err := initGoSum() + f.mu.Lock() + inited, err := f.initGoSum() if err != nil { - goSum.mu.Unlock() + f.mu.Unlock() return err } - done := inited && haveModSumLocked(mod, h) + done := inited && haveModSumLocked(f, mod, h) if inited { - st := goSum.status[modSum{mod, h}] + st := f.sumState.status[modSum{mod, h}] st.used = true - goSum.status[modSum{mod, h}] = st + f.sumState.status[modSum{mod, h}] = st } - goSum.mu.Unlock() + f.mu.Unlock() - if done { + if done && mod.Path != "golang.org/toolchain" { return nil } - // Not listed, so we want to add them. // Consult checksum database if appropriate. if useSumDB(mod) { // Calls base.Fatalf if mismatch detected. @@ -770,14 +893,18 @@ func checkModSum(mod module.Version, h string) error { } } + if done { + return nil + } + // Add mod+h to go.sum, if it hasn't appeared already. if inited { - goSum.mu.Lock() - addModSumLocked(mod, h) - st := goSum.status[modSum{mod, h}] + f.mu.Lock() + addModSumLocked(f, mod, h) + st := f.sumState.status[modSum{mod, h}] st.dirty = true - goSum.status[modSum{mod, h}] = st - goSum.mu.Unlock() + f.sumState.status[modSum{mod, h}] = st + f.mu.Unlock() } return nil } @@ -785,12 +912,12 @@ func checkModSum(mod module.Version, h string) error { // haveModSumLocked reports whether the pair mod,h is already listed in go.sum. // If it finds a conflicting pair instead, it calls base.Fatalf. // goSum.mu must be locked. -func haveModSumLocked(mod module.Version, h string) bool { +func haveModSumLocked(f *Fetcher, mod module.Version, h string) bool { sumFileName := "go.sum" - if strings.HasSuffix(GoSumFile, "go.work.sum") { + if strings.HasSuffix(f.goSumFile, "go.work.sum") { sumFileName = "go.work.sum" } - for _, vh := range goSum.m[mod] { + for _, vh := range f.sumState.m[mod] { if h == vh { return true } @@ -802,7 +929,7 @@ func haveModSumLocked(mod module.Version, h string) bool { foundMatch := false // Check sums from all files in case there are conflicts between // the files. - for goSumFile, goSums := range goSum.w { + for goSumFile, goSums := range f.sumState.w { for _, vh := range goSums[mod] { if h == vh { foundMatch = true @@ -816,14 +943,14 @@ func haveModSumLocked(mod module.Version, h string) bool { // addModSumLocked adds the pair mod,h to go.sum. // goSum.mu must be locked. -func addModSumLocked(mod module.Version, h string) { - if haveModSumLocked(mod, h) { +func addModSumLocked(f *Fetcher, mod module.Version, h string) { + if haveModSumLocked(f, mod, h) { return } - if len(goSum.m[mod]) > 0 { - fmt.Fprintf(os.Stderr, "warning: verifying %s@%s: unknown hashes in go.sum: %v; adding %v"+hashVersionMismatch, mod.Path, mod.Version, strings.Join(goSum.m[mod], ", "), h) + if len(f.sumState.m[mod]) > 0 { + fmt.Fprintf(os.Stderr, "warning: verifying %s@%s: unknown hashes in go.sum: %v; adding %v"+hashVersionMismatch, mod.Path, mod.Version, strings.Join(f.sumState.m[mod], ", "), h) } - goSum.m[mod] = append(goSum.m[mod], h) + f.sumState.m[mod] = append(f.sumState.m[mod], h) } // checkSumDB checks the mod, h pair against the Go checksum database. @@ -851,7 +978,7 @@ func checkSumDB(mod module.Version, h string) error { return module.VersionError(modWithoutSuffix, fmt.Errorf("verifying %s: checksum mismatch\n\tdownloaded: %v\n\t%s: %v"+sumdbMismatch, noun, h, db, line[len(prefix)-len("h1:"):])) } } - return nil + return module.VersionError(modWithoutSuffix, fmt.Errorf("verifying %s: checksum missing from sumdb response"+sumdbAbsent, noun)) } // Sum returns the checksum for the downloaded copy of the given module, @@ -902,12 +1029,12 @@ var ErrGoSumDirty = errors.New("updates to go.sum needed, disabled by -mod=reado // It should have entries for both module content sums and go.mod sums // (version ends with "/go.mod"). Existing sums will be preserved unless they // have been marked for deletion with TrimGoSum. -func WriteGoSum(ctx context.Context, keep map[module.Version]bool, readonly bool) error { - goSum.mu.Lock() - defer goSum.mu.Unlock() +func (f *Fetcher) WriteGoSum(ctx context.Context, keep map[module.Version]bool, readonly bool) error { + f.mu.Lock() + defer f.mu.Unlock() // If we haven't read the go.sum file yet, don't bother writing it. - if !goSum.enabled { + if !f.sumState.enabled { return nil } @@ -916,9 +1043,9 @@ func WriteGoSum(ctx context.Context, keep map[module.Version]bool, readonly bool // just return without opening go.sum. dirty := false Outer: - for m, hs := range goSum.m { + for m, hs := range f.sumState.m { for _, h := range hs { - st := goSum.status[modSum{m, h}] + st := f.sumState.status[modSum{m, h}] if st.dirty && (!st.used || keep[m]) { dirty = true break Outer @@ -931,7 +1058,7 @@ Outer: if readonly { return ErrGoSumDirty } - if fsys.Replaced(GoSumFile) { + if fsys.Replaced(f.goSumFile) { base.Fatalf("go: updates to go.sum needed, but go.sum is part of the overlay specified with -overlay") } @@ -941,64 +1068,63 @@ Outer: defer unlock() } - err := lockedfile.Transform(GoSumFile, func(data []byte) ([]byte, error) { - tidyGoSum := tidyGoSum(data, keep) + err := lockedfile.Transform(f.goSumFile, func(data []byte) ([]byte, error) { + tidyGoSum := tidyGoSum(f, data, keep) return tidyGoSum, nil }) - if err != nil { return fmt.Errorf("updating go.sum: %w", err) } - goSum.status = make(map[modSum]modSumStatus) - goSum.overwrite = false + f.sumState.status = make(map[modSum]modSumStatus) + f.sumState.overwrite = false return nil } // TidyGoSum returns a tidy version of the go.sum file. // A missing go.sum file is treated as if empty. -func TidyGoSum(keep map[module.Version]bool) (before, after []byte) { - goSum.mu.Lock() - defer goSum.mu.Unlock() - before, err := lockedfile.Read(GoSumFile) +func (f *Fetcher) TidyGoSum(keep map[module.Version]bool) (before, after []byte) { + f.mu.Lock() + defer f.mu.Unlock() + before, err := lockedfile.Read(f.goSumFile) if err != nil && !errors.Is(err, fs.ErrNotExist) { base.Fatalf("reading go.sum: %v", err) } - after = tidyGoSum(before, keep) + after = tidyGoSum(f, before, keep) return before, after } // tidyGoSum returns a tidy version of the go.sum file. // The goSum lock must be held. -func tidyGoSum(data []byte, keep map[module.Version]bool) []byte { - if !goSum.overwrite { +func tidyGoSum(f *Fetcher, data []byte, keep map[module.Version]bool) []byte { + if !f.sumState.overwrite { // Incorporate any sums added by other processes in the meantime. // Add only the sums that we actually checked: the user may have edited or // truncated the file to remove erroneous hashes, and we shouldn't restore // them without good reason. - goSum.m = make(map[module.Version][]string, len(goSum.m)) - readGoSum(goSum.m, GoSumFile, data) - for ms, st := range goSum.status { - if st.used && !sumInWorkspaceModulesLocked(ms.mod) { - addModSumLocked(ms.mod, ms.sum) + f.sumState.m = make(map[module.Version][]string, len(f.sumState.m)) + readGoSum(f.sumState.m, f.goSumFile, data) + for ms, st := range f.sumState.status { + if st.used && !sumInWorkspaceModulesLocked(f, ms.mod) { + addModSumLocked(f, ms.mod, ms.sum) } } } - mods := make([]module.Version, 0, len(goSum.m)) - for m := range goSum.m { + mods := make([]module.Version, 0, len(f.sumState.m)) + for m := range f.sumState.m { mods = append(mods, m) } module.Sort(mods) var buf bytes.Buffer for _, m := range mods { - list := goSum.m[m] + list := f.sumState.m[m] sort.Strings(list) str.Uniq(&list) for _, h := range list { - st := goSum.status[modSum{m, h}] - if (!st.dirty || (st.used && keep[m])) && !sumInWorkspaceModulesLocked(m) { + st := f.sumState.status[modSum{m, h}] + if (!st.dirty || (st.used && keep[m])) && !sumInWorkspaceModulesLocked(f, m) { fmt.Fprintf(&buf, "%s %s %s\n", m.Path, m.Version, h) } } @@ -1006,8 +1132,8 @@ func tidyGoSum(data []byte, keep map[module.Version]bool) []byte { return buf.Bytes() } -func sumInWorkspaceModulesLocked(m module.Version) bool { - for _, goSums := range goSum.w { +func sumInWorkspaceModulesLocked(f *Fetcher, m module.Version) bool { + for _, goSums := range f.sumState.w { if _, ok := goSums[m]; ok { return true } @@ -1021,10 +1147,10 @@ func sumInWorkspaceModulesLocked(m module.Version) bool { // keep is used to check whether a sum should be retained in go.mod. It should // have entries for both module content sums and go.mod sums (version ends // with "/go.mod"). -func TrimGoSum(keep map[module.Version]bool) { - goSum.mu.Lock() - defer goSum.mu.Unlock() - inited, err := initGoSum() +func (f *Fetcher) TrimGoSum(keep map[module.Version]bool) { + f.mu.Lock() + defer f.mu.Unlock() + inited, err := f.initGoSum() if err != nil { base.Fatalf("%s", err) } @@ -1032,12 +1158,12 @@ func TrimGoSum(keep map[module.Version]bool) { return } - for m, hs := range goSum.m { + for m, hs := range f.sumState.m { if !keep[m] { for _, h := range hs { - goSum.status[modSum{m, h}] = modSumStatus{used: false, dirty: true} + f.sumState.status[modSum{m, h}] = modSumStatus{used: false, dirty: true} } - goSum.overwrite = true + f.sumState.overwrite = true } } } @@ -1062,6 +1188,19 @@ have intercepted the download attempt. For more information, see 'go help module-auth'. ` +const sumdbAbsent = ` + +SECURITY ERROR +This download does NOT match one reported by the checksum server. +The checksum server has provided checksums, but the checksums do +not contain an entry for the download. +The checksum server may be malfunctioning, or an attacker may have +intercepted the checksum request. +The download cannot be verified. + +For more information, see 'go help module-auth'. +` + const hashVersionMismatch = ` SECURITY WARNING @@ -1083,7 +1222,7 @@ hashes are stored in a file in the module root directory named go.sum. Hashes may also be downloaded from the checksum database depending on the values of GOSUMDB, GOPRIVATE, and GONOSUMDB. -For details, see https://golang.org/ref/mod#authenticating. +For details, see https://go.dev/ref/mod#authenticating. `, } @@ -1128,6 +1267,6 @@ instead of module paths. The 'go env -w' command (see 'go help env') can be used to set these variables for future go command invocations. -For more details, see https://golang.org/ref/mod#private-modules. +For more details, see https://go.dev/ref/mod#private-modules. `, } diff --git a/src/cmd/go/internal/modfetch/fetch_test.go b/src/cmd/go/internal/modfetch/fetch_test.go new file mode 100644 index 00000000000000..4a941510e5b19e --- /dev/null +++ b/src/cmd/go/internal/modfetch/fetch_test.go @@ -0,0 +1,101 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build !js && !wasip1 + +package modfetch + +import ( + "errors" + "io/fs" + "os" + "path/filepath" + "testing" + + "golang.org/x/mod/module" + "golang.org/x/mod/sumdb/dirhash" + modzip "golang.org/x/mod/zip" +) + +func TestUnzipVerify(t *testing.T) { + var ( + ctx = t.Context() + src = t.TempDir() + mod = module.Version{Path: "example.com/unzip", Version: "v1.0.0"} + ) + if err := os.WriteFile(filepath.Join(src, "go.mod"), []byte("module example.com/unzip\n"), 0o666); err != nil { + t.Fatal(err) + } + + zipfile := filepath.Join(t.TempDir(), "v1.0.0.zip") + zf, err := os.Create(zipfile) + if err != nil { + t.Fatal(err) + } + if err := modzip.CreateFromDir(zf, mod, src); err != nil { + t.Fatal(err) + } + if err := zf.Close(); err != nil { + t.Fatal(err) + } + ziphash, err := dirhash.HashZip(zipfile, dirhash.DefaultHash) + if err != nil { + t.Fatal(err) + } + + unzip := func(verify func() error) (string, error) { + dir, err := NewFetcher().Unzip(ctx, mod, zipfile, ziphash, verify) + if dir != "" { + t.Cleanup(func() { RemoveAll(dir) }) + } + return dir, err + } + + var ( + errVerify = errors.New("verify failed") + verifyFnFails = func() error { return errVerify } + verifyFnPasses = func() error { return nil } + ) + if _, err := unzip(verifyFnFails); !errors.Is(err, errVerify) { + t.Fatalf("unzip with empty cache: got %v, want %v", err, errVerify) + } + if _, err := DownloadDir(ctx, mod); !errors.Is(err, fs.ErrNotExist) { + t.Fatalf("DownloadDir after failed verify: got %v, want %v", err, fs.ErrNotExist) + } + + if _, err := unzip(verifyFnPasses); err != nil { + t.Fatal(err) + } + if _, err := DownloadDir(ctx, mod); err != nil { + t.Fatal(err) + } + if ok, err := haveZipHash(ctx, mod, ziphash); err != nil || !ok { + t.Fatalf("haveZipHash = (%v, %v), want (true, nil)", ok, err) + } + + if _, err := unzip(verifyFnFails); err != nil { + t.Fatalf("unzip with cached copy: got %v, want nil", err) + } + + if err := writeZipHash(ctx, mod, "h1:AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA="); err != nil { + t.Fatal(err) + } + if _, err := unzip(verifyFnFails); !errors.Is(err, errVerify) { + t.Fatalf("unzip with mismatched ziphash: got %v, want %v", err, errVerify) + } + if _, err := DownloadDir(ctx, mod); err != nil { + t.Fatal(err) + } + + if _, err := unzip(verifyFnPasses); err != nil { + t.Fatal(err) + } + if _, err := DownloadDir(ctx, mod); err != nil { + t.Fatal(err) + } + + if ok, err := haveZipHash(ctx, mod, ziphash); err != nil || !ok { + t.Errorf("haveZipHash after re-unpack: got (%v, %v), want (true, nil)", ok, err) + } +} diff --git a/src/cmd/go/internal/modfetch/proxy.go b/src/cmd/go/internal/modfetch/proxy.go index 896f310bdf77ca..1934aa3ec3a620 100644 --- a/src/cmd/go/internal/modfetch/proxy.go +++ b/src/cmd/go/internal/modfetch/proxy.go @@ -37,7 +37,7 @@ a site serving from a fixed file system (including a file:/// URL) can be a module proxy. For details on the GOPROXY protocol, see -https://golang.org/ref/mod#goproxy-protocol. +https://go.dev/ref/mod#goproxy-protocol. `, } @@ -238,13 +238,17 @@ func (p *proxyRepo) CheckReuse(ctx context.Context, old *codehost.Origin) error // versionError returns err wrapped in a ModuleError for p.path. func (p *proxyRepo) versionError(version string, err error) error { if version != "" && version != module.CanonicalVersion(version) { - return &module.ModuleError{ - Path: p.path, - Err: &module.InvalidVersionError{ + var iv *module.InvalidVersionError + if !errors.As(err, &iv) { + iv = &module.InvalidVersionError{ Version: version, Pseudo: module.IsPseudoVersion(version), Err: err, - }, + } + } + return &module.ModuleError{ + Path: p.path, + Err: iv, } } diff --git a/src/cmd/go/internal/modfetch/repo.go b/src/cmd/go/internal/modfetch/repo.go index 5d4d679e8327ee..5ed2f259a00dba 100644 --- a/src/cmd/go/internal/modfetch/repo.go +++ b/src/cmd/go/internal/modfetch/repo.go @@ -184,11 +184,6 @@ type RevInfo struct { // To avoid version control access except when absolutely necessary, // Lookup does not attempt to connect to the repository itself. -// The Lookup cache is used cache the work done by Lookup. -// It is important that the global functions of this package that access it do not -// do so after they return. -var lookupCache = new(par.Cache[lookupCacheKey, Repo]) - type lookupCacheKey struct { proxy, path string } @@ -205,14 +200,14 @@ type lookupCacheKey struct { // // A successful return does not guarantee that the module // has any defined versions. -func Lookup(ctx context.Context, proxy, path string) Repo { +func (f *Fetcher) Lookup(ctx context.Context, proxy, path string) Repo { if traceRepo { defer logCall("Lookup(%q, %q)", proxy, path)() } - return lookupCache.Do(lookupCacheKey{proxy, path}, func() Repo { - return newCachingRepo(ctx, path, func(ctx context.Context) (Repo, error) { - r, err := lookup(ctx, proxy, path) + return f.lookupCache.Do(lookupCacheKey{proxy, path}, func() Repo { + return newCachingRepo(ctx, f, path, func(ctx context.Context) (Repo, error) { + r, err := lookup(f, ctx, proxy, path) if err == nil && traceRepo { r = newLoggingRepo(r) } @@ -228,13 +223,13 @@ var lookupLocalCache = new(par.Cache[string, Repo]) // path, Repo // codeRoot is the module path of the root module in the repository. // path is the module path of the module being looked up. // dir is the file system path of the repository containing the module. -func LookupLocal(ctx context.Context, codeRoot string, path string, dir string) Repo { +func (f *Fetcher) LookupLocal(ctx context.Context, codeRoot string, path string, dir string) Repo { if traceRepo { defer logCall("LookupLocal(%q)", path)() } return lookupLocalCache.Do(path, func() Repo { - return newCachingRepo(ctx, path, func(ctx context.Context) (Repo, error) { + return newCachingRepo(ctx, f, path, func(ctx context.Context) (Repo, error) { repoDir, vcsCmd, err := vcs.FromDir(dir, "") if err != nil { return nil, err @@ -253,14 +248,14 @@ func LookupLocal(ctx context.Context, codeRoot string, path string, dir string) } // lookup returns the module with the given module path. -func lookup(ctx context.Context, proxy, path string) (r Repo, err error) { +func lookup(fetcher_ *Fetcher, ctx context.Context, proxy, path string) (r Repo, err error) { if cfg.BuildMod == "vendor" { return nil, errLookupDisabled } switch path { case "go", "toolchain": - return &toolchainRepo{path, Lookup(ctx, proxy, "golang.org/toolchain")}, nil + return &toolchainRepo{path, fetcher_.Lookup(ctx, proxy, "golang.org/toolchain")}, nil } if module.MatchPrefixPatterns(cfg.GONOPROXY, path) { diff --git a/src/cmd/go/internal/modfetch/sumdb.go b/src/cmd/go/internal/modfetch/sumdb.go index ea7d561d7b9e0b..6fb435b010d67c 100644 --- a/src/cmd/go/internal/modfetch/sumdb.go +++ b/src/cmd/go/internal/modfetch/sumdb.go @@ -35,9 +35,8 @@ import ( func useSumDB(mod module.Version) bool { if mod.Path == "golang.org/toolchain" { must := true - // Downloaded toolchains cannot be listed in go.sum, - // so we require checksum database lookups even if - // GOSUMDB=off or GONOSUMDB matches the pattern. + // Toolchain downloads must be verified against the checksum database, + // even if GOSUMDB=off or GONOSUMDB matches the pattern. // If GOSUMDB=off, then the eventual lookup will fail // with a good error message. diff --git a/src/cmd/go/internal/modfetch/zip_sum_test/testdata/zip_sums.csv b/src/cmd/go/internal/modfetch/zip_sum_test/testdata/zip_sums.csv index 0906975f5537e6..adc692e35abadc 100644 --- a/src/cmd/go/internal/modfetch/zip_sum_test/testdata/zip_sums.csv +++ b/src/cmd/go/internal/modfetch/zip_sum_test/testdata/zip_sums.csv @@ -2076,7 +2076,6 @@ k8s.io/node-api,v0.0.0-20191025232816-761e5a80fde0,h1:V3FaBxwSQWPjPScXd5ioFx9+aR k8s.io/sample-apiserver,v0.0.0-20191030110742-cbfc6c263d7e,h1:9bsKcUCncu1Qg3A4pB5ZySTM0JMEZW4qgybjVhmaS4A=,91d701af12da2ff6cde6f07d53547885faafa32c2eadfa8d4614b4d814a854b9 k8s.io/sample-controller,v0.0.0-20191025231305-d7b8b8302943,h1:ZYb6if7+Qa5kXFidUsQRLFDyZjCjRyG1sFf6GpZaA70=,07c3e3a95d0fac07a247a98c38448a8fc4ab0069ad599ec06ac9405df88b470b k8s.io/utils,v0.0.0-20191030222137-2b95a09bc58d,h1:1P0iBJsBzxRmR+dIFnM+Iu4aLxnoa7lBqozW/0uHbT8=,e21be6d971127d4650bd13525a2d2627b2a98dbb8589f168b734a45d50f3ea22 -launchpad.net/gocheck,v0.0.0-20140225173054-000000000087,h1:Izowp2XBH6Ya6rv+hqbceQyw/gSGoXfH/UPoTGduL54=,1a1d9b10f2c69564e69993e4340d5299392a518d895ec06502e842e6c69f4857 layeh.com/radius,v0.0.0-20190322222518-890bc1058917,h1:BDXFaFzUt5EIqe/4wrTc4AcYZWP6iC6Ult+jQWLh5eU=,5eb6b6a05a5f89bc114f37085deda268f895a46621aee2e36649b8d80061357e leb.io/aeshash,v0.0.0-20190627052759-9e6b40329b3b,h1:MG17Tc0pA3XmFTsPwklMMEfcos3pTFnVYM4A0YfVSbU=,a78b48ac18e98ea68dacce16cd94c9074688a0b125f824f047313a33b264ea88 leb.io/hashland,v0.0.0-20171003003232-07375b562dea,h1:s9IkzZTqYqw77voO6taUZHc0C1B096h4T/kQtujGApE=,0698177f24cbde0a7b45495e7fe976fe7623f2b9205995b7d91fd2e7b0f0e243 diff --git a/src/cmd/go/internal/modfetch/zip_sum_test/zip_sum_test.go b/src/cmd/go/internal/modfetch/zip_sum_test/zip_sum_test.go index 9d59d1a8ea8218..9a7d79c1409e66 100644 --- a/src/cmd/go/internal/modfetch/zip_sum_test/zip_sum_test.go +++ b/src/cmd/go/internal/modfetch/zip_sum_test/zip_sum_test.go @@ -31,7 +31,6 @@ import ( "cmd/go/internal/cfg" "cmd/go/internal/modfetch" - "cmd/go/internal/modload" "golang.org/x/mod/module" ) @@ -67,7 +66,6 @@ func TestZipSums(t *testing.T) { testenv.MustHaveGoBuild(t) testenv.MustHaveExternalNetwork(t) - testenv.MustHaveExecPath(t, "bzr") testenv.MustHaveExecPath(t, "git") // TODO(jayconrod): add hg, svn, and fossil modules to testdata. // Could not find any for now. @@ -94,7 +92,6 @@ func TestZipSums(t *testing.T) { cfg.GOPROXY = "direct" cfg.GOSUMDB = "off" - modload.Init(modload.LoaderState) // Shard tests by downloading only every nth module when shard flags are set. // This makes it easier to test small groups of modules quickly. We avoid @@ -114,6 +111,7 @@ func TestZipSums(t *testing.T) { // Download modules with a rate limit. We may run out of file descriptors // or cause timeouts without a limit. needUpdate := false + fetcher := modfetch.NewFetcher() for i := range tests { test := &tests[i] name := fmt.Sprintf("%s@%s", strings.ReplaceAll(test.m.Path, "/", "_"), test.m.Version) @@ -121,7 +119,7 @@ func TestZipSums(t *testing.T) { t.Parallel() ctx := context.Background() - zipPath, err := modfetch.DownloadZip(ctx, test.m) + zipPath, err := fetcher.DownloadZip(ctx, test.m) if err != nil { if *updateTestData { t.Logf("%s: could not download module: %s (will remove from testdata)", test.m, err) diff --git a/src/cmd/go/internal/modget/get.go b/src/cmd/go/internal/modget/get.go index e09fd9c1a45325..682c9016bdf883 100644 --- a/src/cmd/go/internal/modget/get.go +++ b/src/cmd/go/internal/modget/get.go @@ -81,7 +81,7 @@ To upgrade the Go toolchain to the latest patch release of the current Go toolch go get toolchain@patch -See https://golang.org/ref/mod#go-get for details. +See https://go.dev/ref/mod#go-get for details. In earlier versions of Go, 'go get' was used to build and install packages. Now, 'go get' is dedicated to adjusting dependencies in go.mod. 'go install' @@ -92,7 +92,7 @@ current directory. For example: go install example.com/pkg@v1.2.3 go install example.com/pkg@latest -See 'go help install' or https://golang.org/ref/mod#go-install for details. +See 'go help install' or https://go.dev/ref/mod#go-install for details. 'go get' accepts the following flags. @@ -111,6 +111,7 @@ test dependencies as well. The -tool flag instructs go to add a matching tool line to go.mod for each listed package. If -tool is used with @none, the line will be removed. +See 'go help tool' for more information. The -x flag prints commands as they are executed. This is useful for debugging version control commands when a module is downloaded directly @@ -118,7 +119,7 @@ from a repository. For more about build flags, see 'go help build'. -For more about modules, see https://golang.org/ref/mod. +For more about modules, see https://go.dev/ref/mod. For more about using 'go get' to update the minimum Go version and suggested Go toolchain, see https://go.dev/doc/toolchain. @@ -133,15 +134,15 @@ var HelpVCS = &base.Command{ UsageLine: "vcs", Short: "controlling version control with GOVCS", Long: ` -The 'go get' command can run version control commands like git +The go command can run version control commands like git to download imported code. This functionality is critical to the decentralized Go package ecosystem, in which code can be imported from any server, but it is also a potential security problem, if a malicious server finds a way to cause the invoked version control command to run unintended code. -To balance the functionality and security concerns, the 'go get' command +To balance the functionality and security concerns, the go command by default will only use git and hg to download code from public servers. -But it will use any known version control system (bzr, fossil, git, hg, svn) +But it will use any known version control system (fossil, git, hg, svn) to download code from private servers, defined as those hosting packages matching the GOPRIVATE variable (see 'go help private'). The rationale behind allowing only Git and Mercurial is that these two systems have had the most @@ -151,8 +152,8 @@ authenticated environments and are not as well scrutinized as attack surfaces. The version control command restrictions only apply when using direct version control access to download code. When downloading modules from a proxy, -'go get' uses the proxy protocol instead, which is always permitted. -By default, the 'go get' command uses the Go module mirror (proxy.golang.org) +the go command uses the proxy protocol instead, which is always permitted. +By default, the go command uses the Go module mirror (proxy.golang.org) for public packages and only falls back to version control for private packages or when the mirror refuses to serve a public package (typically for legal reasons). Therefore, clients can still access public code served from @@ -273,7 +274,7 @@ func init() { } func runGet(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() switch getU.version { case "", "upgrade", "patch": // ok @@ -299,7 +300,7 @@ func runGet(ctx context.Context, cmd *base.Command, args []string) { base.Fatalf("go: -insecure flag is no longer supported; use GOINSECURE instead") } - moduleLoaderState.ForceUseModules = true + moduleLoader.ForceUseModules = true // Do not allow any updating of go.mod until we've applied // all the requested changes and checked that the result matches @@ -308,23 +309,23 @@ func runGet(ctx context.Context, cmd *base.Command, args []string) { // Allow looking up modules for import paths when outside of a module. // 'go get' is expected to do this, unlike other commands. - modload.AllowMissingModuleImports(moduleLoaderState) + moduleLoader.AllowMissingModuleImports() // 'go get' no longer builds or installs packages, so there's nothing to do // if there's no go.mod file. // TODO(#40775): make modload.Init return ErrNoModRoot instead of exiting. // We could handle that here by printing a different message. - modload.Init(moduleLoaderState) - if !modload.HasModRoot(moduleLoaderState) { + modload.Init(moduleLoader) + if !moduleLoader.HasModRoot() { base.Fatalf("go: go.mod file not found in current directory or any parent directory.\n" + "\t'go get' is no longer supported outside a module.\n" + "\tTo build and install a command, use 'go install' with a version,\n" + "\tlike 'go install example.com/cmd@latest'\n" + - "\tFor more information, see https://golang.org/doc/go-get-install-deprecation\n" + + "\tFor more information, see https://go.dev/doc/go-get-install-deprecation\n" + "\tor run 'go help get' or 'go help install'.") } - dropToolchain, queries := parseArgs(moduleLoaderState, ctx, args) + dropToolchain, queries := parseArgs(moduleLoader, ctx, args) opts := modload.WriteOpts{ DropToolchain: dropToolchain, } @@ -334,17 +335,17 @@ func runGet(ctx context.Context, cmd *base.Command, args []string) { } } - r := newResolver(moduleLoaderState, ctx, queries) - r.performLocalQueries(moduleLoaderState, ctx) - r.performPathQueries(moduleLoaderState, ctx) - r.performToolQueries(moduleLoaderState, ctx) - r.performWorkQueries(moduleLoaderState, ctx) + r := newResolver(moduleLoader, ctx, queries) + r.performLocalQueries(moduleLoader, ctx) + r.performPathQueries(moduleLoader, ctx) + r.performToolQueries(moduleLoader, ctx) + r.performWorkQueries(moduleLoader, ctx) for { - r.performWildcardQueries(moduleLoaderState, ctx) - r.performPatternAllQueries(moduleLoaderState, ctx) + r.performWildcardQueries(moduleLoader, ctx) + r.performPatternAllQueries(moduleLoader, ctx) - if changed := r.resolveQueries(moduleLoaderState, ctx, queries); changed { + if changed := r.resolveQueries(moduleLoader, ctx, queries); changed { // 'go get' arguments can be (and often are) package patterns rather than // (just) modules. A package can be provided by any module with a prefix // of its import path, and a wildcard can even match packages in modules @@ -380,20 +381,20 @@ func runGet(ctx context.Context, cmd *base.Command, args []string) { // // - ambiguous import errors. // TODO(#27899): Try to resolve ambiguous import errors automatically. - upgrades := r.findAndUpgradeImports(moduleLoaderState, ctx, queries) - if changed := r.applyUpgrades(moduleLoaderState, ctx, upgrades); changed { + upgrades := r.findAndUpgradeImports(moduleLoader, ctx, queries) + if changed := r.applyUpgrades(moduleLoader, ctx, upgrades); changed { continue } - r.findMissingWildcards(moduleLoaderState, ctx) - if changed := r.resolveQueries(moduleLoaderState, ctx, r.wildcardQueries); changed { + r.findMissingWildcards(moduleLoader, ctx) + if changed := r.resolveQueries(moduleLoader, ctx, r.wildcardQueries); changed { continue } break } - r.checkWildcardVersions(moduleLoaderState, ctx) + r.checkWildcardVersions(moduleLoader, ctx) var pkgPatterns []string for _, q := range queries { @@ -402,38 +403,38 @@ func runGet(ctx context.Context, cmd *base.Command, args []string) { } } - // If a workspace applies, checkPackageProblems will switch to the workspace - // using modload.EnterWorkspace when doing the final load, and then switch back. - r.checkPackageProblems(moduleLoaderState, ctx, pkgPatterns) - if *getTool { - updateTools(moduleLoaderState, ctx, queries, &opts) + updateTools(moduleLoader, ctx, r, queries, &opts) } + // If a workspace applies, checkPackageProblems will switch to the workspace + // using modload.EnterWorkspace when doing the final load, and then switch back. + r.checkPackageProblems(moduleLoader, ctx, pkgPatterns) + // Everything succeeded. Update go.mod. - oldReqs := reqsFromGoMod(modload.ModFile(moduleLoaderState)) + oldReqs := reqsFromGoMod(modload.ModFile(moduleLoader)) - if err := modload.WriteGoMod(moduleLoaderState, ctx, opts); err != nil { + if err := modload.WriteGoMod(moduleLoader, ctx, opts); err != nil { // A TooNewError can happen for 'go get go@newversion' // when all the required modules are old enough // but the command line is not. // TODO(bcmills): modload.EditBuildList should catch this instead, // and then this can be changed to base.Fatal(err). - toolchain.SwitchOrFatal(moduleLoaderState, ctx, err) + toolchain.SwitchOrFatal(moduleLoader, ctx, err) } - newReqs := reqsFromGoMod(modload.ModFile(moduleLoaderState)) + newReqs := reqsFromGoMod(modload.ModFile(moduleLoader)) r.reportChanges(oldReqs, newReqs) - if gowork := modload.FindGoWork(moduleLoaderState, base.Cwd()); gowork != "" { + if gowork := moduleLoader.FindGoWork(base.Cwd()); gowork != "" { wf, err := modload.ReadWorkFile(gowork) - if err == nil && modload.UpdateWorkGoVersion(wf, moduleLoaderState.MainModules.GoVersion(moduleLoaderState)) { + if err == nil && modload.UpdateWorkGoVersion(wf, moduleLoader.MainModules.GoVersion(moduleLoader)) { modload.WriteWorkFile(gowork, wf) } } } -func updateTools(loaderstate *modload.State, ctx context.Context, queries []*query, opts *modload.WriteOpts) { +func updateTools(ld *modload.Loader, ctx context.Context, r *resolver, queries []*query, opts *modload.WriteOpts) { pkgOpts := modload.PackageOpts{ VendorModulesInGOROOTSrc: true, LoadTests: *getT, @@ -449,7 +450,7 @@ func updateTools(loaderstate *modload.State, ctx context.Context, queries []*que patterns = append(patterns, q.pattern) } - matches, _ := modload.LoadPackages(loaderstate, ctx, pkgOpts, patterns...) + matches, _ := modload.LoadPackages(ld, ctx, pkgOpts, patterns...) for i, m := range matches { if queries[i].version == "none" { opts.DropTools = append(opts.DropTools, m.Pkgs...) @@ -457,17 +458,27 @@ func updateTools(loaderstate *modload.State, ctx context.Context, queries []*que opts.AddTools = append(opts.AddTools, m.Pkgs...) } } + + mg, err := modload.LoadModGraph(ld, ctx, "") + if err != nil { + toolchain.SwitchOrFatal(ld, ctx, err) + } + r.buildList = mg.BuildList() + r.buildListVersion = make(map[string]string, len(r.buildList)) + for _, m := range r.buildList { + r.buildListVersion[m.Path] = m.Version + } } // parseArgs parses command-line arguments and reports errors. // // The command-line arguments are of the form path@version or simply path, with // implicit @upgrade. path@none is "downgrade away". -func parseArgs(loaderstate *modload.State, ctx context.Context, rawArgs []string) (dropToolchain bool, queries []*query) { +func parseArgs(ld *modload.Loader, ctx context.Context, rawArgs []string) (dropToolchain bool, queries []*query) { defer base.ExitIfErrors() for _, arg := range search.CleanPatterns(rawArgs) { - q, err := newQuery(loaderstate, arg) + q, err := newQuery(ld, arg) if err != nil { base.Error(err) continue @@ -554,12 +565,12 @@ type matchInModuleKey struct { m module.Version } -func newResolver(loaderstate *modload.State, ctx context.Context, queries []*query) *resolver { +func newResolver(ld *modload.Loader, ctx context.Context, queries []*query) *resolver { // LoadModGraph also sets modload.Target, which is needed by various resolver // methods. - mg, err := modload.LoadModGraph(loaderstate, ctx, "") + mg, err := modload.LoadModGraph(ld, ctx, "") if err != nil { - toolchain.SwitchOrFatal(loaderstate, ctx, err) + toolchain.SwitchOrFatal(ld, ctx, err) } buildList := mg.BuildList() @@ -575,7 +586,7 @@ func newResolver(loaderstate *modload.State, ctx context.Context, queries []*que buildListVersion: initialVersion, initialVersion: initialVersion, nonesByPath: map[string]*query{}, - workspace: loadWorkspace(modload.FindGoWork(loaderstate, base.Cwd())), + workspace: loadWorkspace(ld.FindGoWork(base.Cwd())), } for _, q := range queries { @@ -644,9 +655,9 @@ func (r *resolver) noneForPath(mPath string) (nq *query, found bool) { // queryModule wraps modload.Query, substituting r.checkAllowedOr to decide // allowed versions. -func (r *resolver) queryModule(loaderstate *modload.State, ctx context.Context, mPath, query string, selected func(string) string) (module.Version, error) { +func (r *resolver) queryModule(ld *modload.Loader, ctx context.Context, mPath, query string, selected func(string) string) (module.Version, error) { current := r.initialSelected(mPath) - rev, err := modload.Query(loaderstate, ctx, mPath, query, current, r.checkAllowedOr(loaderstate, query, selected)) + rev, err := modload.Query(ld, ctx, mPath, query, current, r.checkAllowedOr(ld, query, selected)) if err != nil { return module.Version{}, err } @@ -655,8 +666,8 @@ func (r *resolver) queryModule(loaderstate *modload.State, ctx context.Context, // queryPackages wraps modload.QueryPackage, substituting r.checkAllowedOr to // decide allowed versions. -func (r *resolver) queryPackages(loaderstate *modload.State, ctx context.Context, pattern, query string, selected func(string) string) (pkgMods []module.Version, err error) { - results, err := modload.QueryPackages(loaderstate, ctx, pattern, query, selected, r.checkAllowedOr(loaderstate, query, selected)) +func (r *resolver) queryPackages(ld *modload.Loader, ctx context.Context, pattern, query string, selected func(string) string) (pkgMods []module.Version, err error) { + results, err := modload.QueryPackages(ld, ctx, pattern, query, selected, r.checkAllowedOr(ld, query, selected)) if len(results) > 0 { pkgMods = make([]module.Version, 0, len(results)) for _, qr := range results { @@ -668,8 +679,8 @@ func (r *resolver) queryPackages(loaderstate *modload.State, ctx context.Context // queryPattern wraps modload.QueryPattern, substituting r.checkAllowedOr to // decide allowed versions. -func (r *resolver) queryPattern(loaderstate *modload.State, ctx context.Context, pattern, query string, selected func(string) string) (pkgMods []module.Version, mod module.Version, err error) { - results, modOnly, err := modload.QueryPattern(loaderstate, ctx, pattern, query, selected, r.checkAllowedOr(loaderstate, query, selected)) +func (r *resolver) queryPattern(ld *modload.Loader, ctx context.Context, pattern, query string, selected func(string) string) (pkgMods []module.Version, mod module.Version, err error) { + results, modOnly, err := modload.QueryPattern(ld, ctx, pattern, query, selected, r.checkAllowedOr(ld, query, selected)) if len(results) > 0 { pkgMods = make([]module.Version, 0, len(results)) for _, qr := range results { @@ -684,7 +695,7 @@ func (r *resolver) queryPattern(loaderstate *modload.State, ctx context.Context, // checkAllowedOr is like modload.CheckAllowed, but it always allows the requested // and current versions (even if they are retracted or otherwise excluded). -func (r *resolver) checkAllowedOr(s *modload.State, requested string, selected func(string) string) modload.AllowedFunc { +func (r *resolver) checkAllowedOr(s *modload.Loader, requested string, selected func(string) string) modload.AllowedFunc { return func(ctx context.Context, m module.Version) error { if m.Version == requested { return s.CheckExclusions(ctx, m) @@ -697,9 +708,9 @@ func (r *resolver) checkAllowedOr(s *modload.State, requested string, selected f } // matchInModule is a caching wrapper around modload.MatchInModule. -func (r *resolver) matchInModule(loaderstate *modload.State, ctx context.Context, pattern string, m module.Version) (packages []string, err error) { +func (r *resolver) matchInModule(ld *modload.Loader, ctx context.Context, pattern string, m module.Version) (packages []string, err error) { return r.matchInModuleCache.Do(matchInModuleKey{pattern, m}, func() ([]string, error) { - match := modload.MatchInModule(loaderstate, ctx, pattern, m, imports.AnyTags()) + match := modload.MatchInModule(ld, ctx, pattern, m, imports.AnyTags()) if len(match.Errs) > 0 { return match.Pkgs, match.Errs[0] } @@ -715,15 +726,15 @@ func (r *resolver) matchInModule(loaderstate *modload.State, ctx context.Context // modules second. However, no module exists at version "none", and therefore no // package exists at that version either: we know that the argument cannot match // any packages, and thus it must match modules instead. -func (r *resolver) queryNone(loaderstate *modload.State, ctx context.Context, q *query) { +func (r *resolver) queryNone(ld *modload.Loader, ctx context.Context, q *query) { if search.IsMetaPackage(q.pattern) { panic(fmt.Sprintf("internal error: queryNone called with pattern %q", q.pattern)) } if !q.isWildcard() { q.pathOnce(q.pattern, func() pathSet { - hasModRoot := modload.HasModRoot(loaderstate) - if hasModRoot && loaderstate.MainModules.Contains(q.pattern) { + hasModRoot := ld.HasModRoot() + if hasModRoot && ld.MainModules.Contains(q.pattern) { v := module.Version{Path: q.pattern} // The user has explicitly requested to downgrade their own module to // version "none". This is not an entirely unreasonable request: it @@ -735,7 +746,12 @@ func (r *resolver) queryNone(loaderstate *modload.State, ctx context.Context, q // However, neither of those behaviors would be consistent with the // plain meaning of the query. To try to reduce confusion, reject the // query explicitly. - return errSet(&modload.QueryMatchesMainModulesError{LoaderState: loaderstate, MainModules: []module.Version{v}, Pattern: q.pattern, Query: q.version}) + return errSet(&modload.QueryMatchesMainModulesError{ + MainModules: []module.Version{v}, + Pattern: q.pattern, + Query: q.version, + PatternIsModule: ld.MainModules.Contains(q.pattern), + }) } return pathSet{mod: module.Version{Path: q.pattern, Version: "none"}} @@ -747,15 +763,20 @@ func (r *resolver) queryNone(loaderstate *modload.State, ctx context.Context, q continue } q.pathOnce(curM.Path, func() pathSet { - if modload.HasModRoot(loaderstate) && curM.Version == "" && loaderstate.MainModules.Contains(curM.Path) { - return errSet(&modload.QueryMatchesMainModulesError{LoaderState: loaderstate, MainModules: []module.Version{curM}, Pattern: q.pattern, Query: q.version}) + if ld.HasModRoot() && curM.Version == "" && ld.MainModules.Contains(curM.Path) { + return errSet(&modload.QueryMatchesMainModulesError{ + MainModules: []module.Version{curM}, + Pattern: q.pattern, + Query: q.version, + PatternIsModule: ld.MainModules.Contains(q.pattern), + }) } return pathSet{mod: module.Version{Path: curM.Path, Version: "none"}} }) } } -func (r *resolver) performLocalQueries(loaderstate *modload.State, ctx context.Context) { +func (r *resolver) performLocalQueries(ld *modload.Loader, ctx context.Context) { for _, q := range r.localQueries { q.pathOnce(q.pattern, func() pathSet { absDetail := "" @@ -767,13 +788,13 @@ func (r *resolver) performLocalQueries(loaderstate *modload.State, ctx context.C // Absolute paths like C:\foo and relative paths like ../foo... are // restricted to matching packages in the main module. - pkgPattern, mainModule := loaderstate.MainModules.DirImportPath(loaderstate, ctx, q.pattern) + pkgPattern, mainModule := ld.MainModules.DirImportPath(ld, ctx, q.pattern) if pkgPattern == "." { - modload.MustHaveModRoot(loaderstate) - versions := loaderstate.MainModules.Versions() + ld.MustHaveModRoot() + versions := ld.MainModules.Versions() modRoots := make([]string, 0, len(versions)) for _, m := range versions { - modRoots = append(modRoots, loaderstate.MainModules.ModRoot(m)) + modRoots = append(modRoots, ld.MainModules.ModRoot(m)) } var plural string if len(modRoots) != 1 { @@ -782,7 +803,7 @@ func (r *resolver) performLocalQueries(loaderstate *modload.State, ctx context.C return errSet(fmt.Errorf("%s%s is not within module%s rooted at %s", q.pattern, absDetail, plural, strings.Join(modRoots, ", "))) } - match := modload.MatchInModule(loaderstate, ctx, pkgPattern, mainModule, imports.AnyTags()) + match := modload.MatchInModule(ld, ctx, pkgPattern, mainModule, imports.AnyTags()) if len(match.Errs) > 0 { return pathSet{err: match.Errs[0]} } @@ -792,8 +813,8 @@ func (r *resolver) performLocalQueries(loaderstate *modload.State, ctx context.C return errSet(fmt.Errorf("no package to get in current directory")) } if !q.isWildcard() { - modload.MustHaveModRoot(loaderstate) - return errSet(fmt.Errorf("%s%s is not a package in module rooted at %s", q.pattern, absDetail, loaderstate.MainModules.ModRoot(mainModule))) + ld.MustHaveModRoot() + return errSet(fmt.Errorf("%s%s is not a package in module rooted at %s", q.pattern, absDetail, ld.MainModules.ModRoot(mainModule))) } search.WarnUnmatched([]*search.Match{match}) return pathSet{} @@ -812,14 +833,14 @@ func (r *resolver) performLocalQueries(loaderstate *modload.State, ctx context.C // of modules may be expanded by other queries, so wildcard queries need to be // re-evaluated whenever a potentially-matching module path is added to the // build list. -func (r *resolver) performWildcardQueries(loaderstate *modload.State, ctx context.Context) { +func (r *resolver) performWildcardQueries(ld *modload.Loader, ctx context.Context) { for _, q := range r.wildcardQueries { q := q r.work.Add(func() { if q.version == "none" { - r.queryNone(loaderstate, ctx, q) + r.queryNone(ld, ctx, q) } else { - r.queryWildcard(loaderstate, ctx, q) + r.queryWildcard(ld, ctx, q) } }) } @@ -831,7 +852,7 @@ func (r *resolver) performWildcardQueries(loaderstate *modload.State, ctx contex // - that module exists at some version matching q.version, and // - either the module path itself matches q.pattern, or some package within // the module at q.version matches q.pattern. -func (r *resolver) queryWildcard(loaderstate *modload.State, ctx context.Context, q *query) { +func (r *resolver) queryWildcard(ld *modload.Loader, ctx context.Context, q *query) { // For wildcard patterns, modload.QueryPattern only identifies modules // matching the prefix of the path before the wildcard. However, the build // list may already contain other modules with matching packages, and we @@ -849,17 +870,17 @@ func (r *resolver) queryWildcard(loaderstate *modload.State, ctx context.Context return pathSet{} } - if loaderstate.MainModules.Contains(curM.Path) && !versionOkForMainModule(q.version) { + if ld.MainModules.Contains(curM.Path) && !versionOkForMainModule(q.version) { if q.matchesPath(curM.Path) { return errSet(&modload.QueryMatchesMainModulesError{ - LoaderState: loaderstate, - MainModules: []module.Version{curM}, - Pattern: q.pattern, - Query: q.version, + MainModules: []module.Version{curM}, + Pattern: q.pattern, + Query: q.version, + PatternIsModule: ld.MainModules.Contains(q.pattern), }) } - packages, err := r.matchInModule(loaderstate, ctx, q.pattern, curM) + packages, err := r.matchInModule(ld, ctx, q.pattern, curM) if err != nil { return errSet(err) } @@ -871,10 +892,10 @@ func (r *resolver) queryWildcard(loaderstate *modload.State, ctx context.Context }) } - return r.tryWildcard(loaderstate, ctx, q, curM) + return r.tryWildcard(ld, ctx, q, curM) } - m, err := r.queryModule(loaderstate, ctx, curM.Path, q.version, r.initialSelected) + m, err := r.queryModule(ld, ctx, curM.Path, q.version, r.initialSelected) if err != nil { if !isNoSuchModuleVersion(err) { // We can't tell whether a matching version exists. @@ -896,7 +917,7 @@ func (r *resolver) queryWildcard(loaderstate *modload.State, ctx context.Context return pathSet{} } - return r.tryWildcard(loaderstate, ctx, q, m) + return r.tryWildcard(ld, ctx, q, m) }) } @@ -907,9 +928,9 @@ func (r *resolver) queryWildcard(loaderstate *modload.State, ctx context.Context // tryWildcard returns a pathSet for module m matching query q. // If m does not actually match q, tryWildcard returns an empty pathSet. -func (r *resolver) tryWildcard(loaderstate *modload.State, ctx context.Context, q *query, m module.Version) pathSet { +func (r *resolver) tryWildcard(ld *modload.Loader, ctx context.Context, q *query, m module.Version) pathSet { mMatches := q.matchesPath(m.Path) - packages, err := r.matchInModule(loaderstate, ctx, q.pattern, m) + packages, err := r.matchInModule(ld, ctx, q.pattern, m) if err != nil { return errSet(err) } @@ -924,14 +945,14 @@ func (r *resolver) tryWildcard(loaderstate *modload.State, ctx context.Context, // findMissingWildcards adds a candidate set for each query in r.wildcardQueries // that has not yet resolved to any version containing packages. -func (r *resolver) findMissingWildcards(loaderstate *modload.State, ctx context.Context) { +func (r *resolver) findMissingWildcards(ld *modload.Loader, ctx context.Context) { for _, q := range r.wildcardQueries { if q.version == "none" || q.matchesPackages { continue // q is not “missing” } r.work.Add(func() { q.pathOnce(q.pattern, func() pathSet { - pkgMods, mod, err := r.queryPattern(loaderstate, ctx, q.pattern, q.version, r.initialSelected) + pkgMods, mod, err := r.queryPattern(ld, ctx, q.pattern, q.version, r.initialSelected) if err != nil { if isNoSuchPackageVersion(err) && len(q.resolved) > 0 { // q already resolved one or more modules but matches no packages. @@ -952,7 +973,7 @@ func (r *resolver) findMissingWildcards(loaderstate *modload.State, ctx context. // checkWildcardVersions reports an error if any module in the build list has a // path (or contains a package) matching a query with a wildcard pattern, but // has a selected version that does *not* match the query. -func (r *resolver) checkWildcardVersions(loaderstate *modload.State, ctx context.Context) { +func (r *resolver) checkWildcardVersions(ld *modload.Loader, ctx context.Context) { defer base.ExitIfErrors() for _, q := range r.wildcardQueries { @@ -961,7 +982,7 @@ func (r *resolver) checkWildcardVersions(loaderstate *modload.State, ctx context continue } if !q.matchesPath(curM.Path) { - packages, err := r.matchInModule(loaderstate, ctx, q.pattern, curM) + packages, err := r.matchInModule(ld, ctx, q.pattern, curM) if len(packages) == 0 { if err != nil { reportError(q, err) @@ -970,7 +991,7 @@ func (r *resolver) checkWildcardVersions(loaderstate *modload.State, ctx context } } - rev, err := r.queryModule(loaderstate, ctx, curM.Path, q.version, r.initialSelected) + rev, err := r.queryModule(ld, ctx, curM.Path, q.version, r.initialSelected) if err != nil { reportError(q, err) continue @@ -981,7 +1002,7 @@ func (r *resolver) checkWildcardVersions(loaderstate *modload.State, ctx context if !q.matchesPath(curM.Path) { m := module.Version{Path: curM.Path, Version: rev.Version} - packages, err := r.matchInModule(loaderstate, ctx, q.pattern, m) + packages, err := r.matchInModule(ld, ctx, q.pattern, m) if err != nil { reportError(q, err) continue @@ -1015,14 +1036,14 @@ func (r *resolver) checkWildcardVersions(loaderstate *modload.State, ctx context // The candidate packages and modules for path literals depend only on the // initial build list, not the current build list, so we only need to query path // literals once. -func (r *resolver) performPathQueries(loaderstate *modload.State, ctx context.Context) { +func (r *resolver) performPathQueries(ld *modload.Loader, ctx context.Context) { for _, q := range r.pathQueries { q := q r.work.Add(func() { if q.version == "none" { - r.queryNone(loaderstate, ctx, q) + r.queryNone(ld, ctx, q) } else { - r.queryPath(loaderstate, ctx, q) + r.queryPath(ld, ctx, q) } }) } @@ -1033,7 +1054,7 @@ func (r *resolver) performPathQueries(loaderstate *modload.State, ctx context.Co // The candidate set consists of all modules that could provide q.pattern // and have a version matching q, plus (if it exists) the module whose path // is itself q.pattern (at a matching version). -func (r *resolver) queryPath(loaderstate *modload.State, ctx context.Context, q *query) { +func (r *resolver) queryPath(ld *modload.Loader, ctx context.Context, q *query) { q.pathOnce(q.pattern, func() pathSet { if search.IsMetaPackage(q.pattern) || q.isWildcard() { panic(fmt.Sprintf("internal error: queryPath called with pattern %q", q.pattern)) @@ -1044,7 +1065,7 @@ func (r *resolver) queryPath(loaderstate *modload.State, ctx context.Context, q if search.IsStandardImportPath(q.pattern) { stdOnly := module.Version{} - packages, _ := r.matchInModule(loaderstate, ctx, q.pattern, stdOnly) + packages, _ := r.matchInModule(ld, ctx, q.pattern, stdOnly) if len(packages) > 0 { if q.rawVersion != "" { return errSet(fmt.Errorf("can't request explicit version %q of standard library package %s", q.version, q.pattern)) @@ -1055,7 +1076,7 @@ func (r *resolver) queryPath(loaderstate *modload.State, ctx context.Context, q } } - pkgMods, mod, err := r.queryPattern(loaderstate, ctx, q.pattern, q.version, r.initialSelected) + pkgMods, mod, err := r.queryPattern(ld, ctx, q.pattern, q.version, r.initialSelected) if err != nil { return errSet(err) } @@ -1065,11 +1086,11 @@ func (r *resolver) queryPath(loaderstate *modload.State, ctx context.Context, q // performToolQueries populates the candidates for each query whose // pattern is "tool". -func (r *resolver) performToolQueries(loaderstate *modload.State, ctx context.Context) { +func (r *resolver) performToolQueries(ld *modload.Loader, ctx context.Context) { for _, q := range r.toolQueries { - for tool := range loaderstate.MainModules.Tools() { + for tool := range ld.MainModules.Tools() { q.pathOnce(tool, func() pathSet { - pkgMods, err := r.queryPackages(loaderstate, ctx, tool, q.version, r.initialSelected) + pkgMods, err := r.queryPackages(ld, ctx, tool, q.version, r.initialSelected) return pathSet{pkgMods: pkgMods, err: err} }) } @@ -1078,22 +1099,22 @@ func (r *resolver) performToolQueries(loaderstate *modload.State, ctx context.Co // performWorkQueries populates the candidates for each query whose pattern is "work". // The candidate module to resolve the work pattern is exactly the single main module. -func (r *resolver) performWorkQueries(loaderstate *modload.State, ctx context.Context) { +func (r *resolver) performWorkQueries(ld *modload.Loader, ctx context.Context) { for _, q := range r.workQueries { q.pathOnce(q.pattern, func() pathSet { // TODO(matloob): Maybe export MainModules.mustGetSingleMainModule and call that. // There are a few other places outside the modload package where we expect // a single main module. - if len(loaderstate.MainModules.Versions()) != 1 { + if len(ld.MainModules.Versions()) != 1 { panic("internal error: number of main modules is not exactly one in resolution phase of go get") } - mainModule := loaderstate.MainModules.Versions()[0] + mainModule := ld.MainModules.Versions()[0] // We know what the result is going to be, assuming the main module is not // empty, (it's the main module itself) but first check to see that there // are packages in the main module, so that if there aren't any, we can // return the expected warning that the pattern matched no packages. - match := modload.MatchInModule(loaderstate, ctx, q.pattern, mainModule, imports.AnyTags()) + match := modload.MatchInModule(ld, ctx, q.pattern, mainModule, imports.AnyTags()) if len(match.Errs) > 0 { return pathSet{err: match.Errs[0]} } @@ -1115,7 +1136,7 @@ func (r *resolver) performWorkQueries(loaderstate *modload.State, ctx context.Co // know which candidate is selected — and that selection may depend on the // results of other queries. We need to re-evaluate the "all" queries whenever // the module for one or more packages in "all" are resolved. -func (r *resolver) performPatternAllQueries(loaderstate *modload.State, ctx context.Context) { +func (r *resolver) performPatternAllQueries(ld *modload.Loader, ctx context.Context) { if len(r.patternAllQueries) == 0 { return } @@ -1124,7 +1145,7 @@ func (r *resolver) performPatternAllQueries(loaderstate *modload.State, ctx cont versionOk = true for _, q := range r.patternAllQueries { q.pathOnce(path, func() pathSet { - pkgMods, err := r.queryPackages(loaderstate, ctx, path, q.version, r.initialSelected) + pkgMods, err := r.queryPackages(ld, ctx, path, q.version, r.initialSelected) if len(pkgMods) != 1 || pkgMods[0] != m { // There are candidates other than m for the given path, so we can't // be certain that m will actually be the module selected to provide @@ -1139,7 +1160,7 @@ func (r *resolver) performPatternAllQueries(loaderstate *modload.State, ctx cont return versionOk } - r.loadPackages(loaderstate, ctx, []string{"all"}, findPackage) + r.loadPackages(ld, ctx, []string{"all"}, findPackage) // Since we built up the candidate lists concurrently, they may be in a // nondeterministic order. We want 'go get' to be fully deterministic, @@ -1159,7 +1180,7 @@ func (r *resolver) performPatternAllQueries(loaderstate *modload.State, ctx cont // If the getU flag ("-u") is set, findAndUpgradeImports also returns a // pathSet for each module that is not constrained by any other // command-line argument and has an available matching upgrade. -func (r *resolver) findAndUpgradeImports(loaderstate *modload.State, ctx context.Context, queries []*query) (upgrades []pathSet) { +func (r *resolver) findAndUpgradeImports(ld *modload.Loader, ctx context.Context, queries []*query) (upgrades []pathSet) { patterns := make([]string, 0, len(queries)) for _, q := range queries { if q.matchesPackages { @@ -1200,7 +1221,7 @@ func (r *resolver) findAndUpgradeImports(loaderstate *modload.State, ctx context // - The "-u" flag, unlike other arguments, does not cause version // conflicts with other queries. (The other query always wins.) - pkgMods, err := r.queryPackages(loaderstate, ctx, path, version, r.selected) + pkgMods, err := r.queryPackages(ld, ctx, path, version, r.selected) for _, u := range pkgMods { if u == m { // The selected package version is already upgraded appropriately; there @@ -1231,7 +1252,7 @@ func (r *resolver) findAndUpgradeImports(loaderstate *modload.State, ctx context return false } - r.loadPackages(loaderstate, ctx, patterns, findPackage) + r.loadPackages(ld, ctx, patterns, findPackage) // Since we built up the candidate lists concurrently, they may be in a // nondeterministic order. We want 'go get' to be fully deterministic, @@ -1255,14 +1276,14 @@ func (r *resolver) findAndUpgradeImports(loaderstate *modload.State, ctx context // loadPackages also invokes the findPackage function for each imported package // that is neither present in the standard library nor in any module in the // build list. -func (r *resolver) loadPackages(loaderstate *modload.State, ctx context.Context, patterns []string, findPackage func(ctx context.Context, path string, m module.Version) (versionOk bool)) { +func (r *resolver) loadPackages(ld *modload.Loader, ctx context.Context, patterns []string, findPackage func(ctx context.Context, path string, m module.Version) (versionOk bool)) { opts := modload.PackageOpts{ Tags: imports.AnyTags(), VendorModulesInGOROOTSrc: true, LoadTests: *getT, AssumeRootsImported: true, // After 'go get foo', imports of foo should build. SilencePackageErrors: true, // May be fixed by subsequent upgrades or downgrades. - Switcher: toolchain.NewSwitcher(loaderstate), + Switcher: toolchain.NewSwitcher(ld), } opts.AllowPackage = func(ctx context.Context, path string, m module.Version) error { @@ -1277,13 +1298,13 @@ func (r *resolver) loadPackages(loaderstate *modload.State, ctx context.Context, return nil } - _, pkgs := modload.LoadPackages(loaderstate, ctx, opts, patterns...) + _, pkgs := modload.LoadPackages(ld, ctx, opts, patterns...) for _, pkgPath := range pkgs { const ( parentPath = "" parentIsStd = false ) - _, _, err := modload.Lookup(loaderstate, parentPath, parentIsStd, pkgPath) + _, _, err := modload.Lookup(ld, parentPath, parentIsStd, pkgPath) if err == nil { continue } @@ -1329,7 +1350,7 @@ var errVersionChange = errors.New("version change needed") // // If all pathSets are resolved without any changes to the build list, // resolveQueries returns with changed=false. -func (r *resolver) resolveQueries(loaderstate *modload.State, ctx context.Context, queries []*query) (changed bool) { +func (r *resolver) resolveQueries(ld *modload.Loader, ctx context.Context, queries []*query) (changed bool) { defer base.ExitIfErrors() // Note: this is O(N²) with the number of pathSets in the worst case. @@ -1348,7 +1369,7 @@ func (r *resolver) resolveQueries(loaderstate *modload.State, ctx context.Contex // If we found modules that were too new, find the max of the required versions // and then try to switch to a newer toolchain. - sw := toolchain.NewSwitcher(loaderstate) + sw := toolchain.NewSwitcher(ld) for _, q := range queries { for _, cs := range q.candidates { sw.Error(cs.err) @@ -1373,7 +1394,7 @@ func (r *resolver) resolveQueries(loaderstate *modload.State, ctx context.Contex continue } - filtered, isPackage, m, unique := r.disambiguate(loaderstate, cs) + filtered, isPackage, m, unique := r.disambiguate(ld, cs) if !unique { unresolved = append(unresolved, filtered) continue @@ -1387,7 +1408,7 @@ func (r *resolver) resolveQueries(loaderstate *modload.State, ctx context.Contex if isPackage { q.matchesPackages = true } - r.resolve(loaderstate, q, m) + r.resolve(ld, q, m) resolved++ } @@ -1401,7 +1422,7 @@ func (r *resolver) resolveQueries(loaderstate *modload.State, ctx context.Contex } if resolved > 0 { - if changed = r.updateBuildList(loaderstate, ctx, nil); changed { + if changed = r.updateBuildList(ld, ctx, nil); changed { // The build list has changed, so disregard any remaining ambiguous queries: // they might now be determined by requirements in the build list, which we // would prefer to use instead of arbitrary versions. @@ -1423,12 +1444,12 @@ func (r *resolver) resolveQueries(loaderstate *modload.State, ctx context.Contex if isPackage { q.matchesPackages = true } - r.resolve(loaderstate, q, m) + r.resolve(ld, q, m) resolvedArbitrarily++ } } if resolvedArbitrarily > 0 { - changed = r.updateBuildList(loaderstate, ctx, nil) + changed = r.updateBuildList(ld, ctx, nil) } return changed } @@ -1444,8 +1465,9 @@ func (r *resolver) resolveQueries(loaderstate *modload.State, ctx context.Contex // // If all pathSets are resolved without any changes to the build list, // applyUpgrades returns with changed=false. -func (r *resolver) applyUpgrades(loaderstate *modload.State, ctx context.Context, upgrades []pathSet) (changed bool) { +func (r *resolver) applyUpgrades(ld *modload.Loader, ctx context.Context, upgrades []pathSet) (changed bool) { defer base.ExitIfErrors() + sw := toolchain.NewSwitcher(ld) // Arbitrarily add a "latest" version that provides each missing package, but // do not mark the version as resolved: we still want to allow the explicit @@ -1453,11 +1475,11 @@ func (r *resolver) applyUpgrades(loaderstate *modload.State, ctx context.Context var tentative []module.Version for _, cs := range upgrades { if cs.err != nil { - base.Error(cs.err) + sw.Error(cs.err) continue } - filtered, _, m, unique := r.disambiguate(loaderstate, cs) + filtered, _, m, unique := r.disambiguate(ld, cs) if !unique { _, m = r.chooseArbitrarily(filtered) } @@ -1468,9 +1490,11 @@ func (r *resolver) applyUpgrades(loaderstate *modload.State, ctx context.Context } tentative = append(tentative, m) } + // Switch if necessary. Otherwise, report the errors from sw.Error above. + sw.Switch(ctx) base.ExitIfErrors() - changed = r.updateBuildList(loaderstate, ctx, tentative) + changed = r.updateBuildList(ld, ctx, tentative) return changed } @@ -1484,7 +1508,7 @@ func (r *resolver) applyUpgrades(loaderstate *modload.State, ctx context.Context // In the vast majority of cases, we expect only one module per pathSet, // but we want to give some minimal additional tools so that users can add an // extra argument or two on the command line to resolve simple ambiguities. -func (r *resolver) disambiguate(s *modload.State, cs pathSet) (filtered pathSet, isPackage bool, m module.Version, unique bool) { +func (r *resolver) disambiguate(s *modload.Loader, cs pathSet) (filtered pathSet, isPackage bool, m module.Version, unique bool) { if len(cs.pkgMods) == 0 && cs.mod.Path == "" { panic("internal error: resolveIfUnambiguous called with empty pathSet") } @@ -1601,7 +1625,7 @@ func (r *resolver) chooseArbitrarily(cs pathSet) (isPackage bool, m module.Versi // We skip missing-package errors earlier in the process, since we want to // resolve pathSets ourselves, but at that point, we don't have enough context // to log the package-import chains leading to each error. -func (r *resolver) checkPackageProblems(loaderstate *modload.State, ctx context.Context, pkgPatterns []string) { +func (r *resolver) checkPackageProblems(ld *modload.Loader, ctx context.Context, pkgPatterns []string) { defer base.ExitIfErrors() // Enter workspace mode, if the current main module would belong to it, when @@ -1612,16 +1636,16 @@ func (r *resolver) checkPackageProblems(loaderstate *modload.State, ctx context. // info, but switch back to single module mode when fetching sums so that we update // the single module's go.sum file. var exitWorkspace func() - if r.workspace != nil && r.workspace.hasModule(loaderstate.MainModules.Versions()[0].Path) { + if r.workspace != nil && r.workspace.hasModule(ld.MainModules.Versions()[0].Path) { var err error - exitWorkspace, err = modload.EnterWorkspace(loaderstate, ctx) + exitWorkspace, err = modload.EnterWorkspace(ld, ctx) if err != nil { // A TooNewError can happen for // go get go@newversion when all the required modules // are old enough but the go command itself is not new // enough. See the related comment on the SwitchOrFatal // in runGet when WriteGoMod returns an error. - toolchain.SwitchOrFatal(loaderstate, ctx, err) + toolchain.SwitchOrFatal(ld, ctx, err) } } @@ -1653,7 +1677,7 @@ func (r *resolver) checkPackageProblems(loaderstate *modload.State, ctx context. AllowErrors: true, SilenceNoGoErrors: true, } - matches, pkgs := modload.LoadPackages(loaderstate, ctx, pkgOpts, pkgPatterns...) + matches, pkgs := modload.LoadPackages(ld, ctx, pkgOpts, pkgPatterns...) for _, m := range matches { if len(m.Errs) > 0 { base.SetExitStatus(1) @@ -1661,7 +1685,7 @@ func (r *resolver) checkPackageProblems(loaderstate *modload.State, ctx context. } } for _, pkg := range pkgs { - if dir, _, err := modload.Lookup(loaderstate, "", false, pkg); err != nil { + if dir, _, err := modload.Lookup(ld, "", false, pkg); err != nil { if dir != "" && errors.Is(err, imports.ErrNoGo) { // Since dir is non-empty, we must have located source files // associated with either the package or its test — ErrNoGo must @@ -1680,19 +1704,19 @@ func (r *resolver) checkPackageProblems(loaderstate *modload.State, ctx context. } } } - if m := modload.PackageModule(pkg); m.Path != "" { + if m := ld.PackageModule(pkg); m.Path != "" { relevantMods[m] |= hasPkg } } for _, match := range matches { for _, pkg := range match.Pkgs { - m := modload.PackageModule(pkg) + m := ld.PackageModule(pkg) relevantMods[m] |= named } } } - reqs := modload.LoadModFile(loaderstate, ctx) + reqs := modload.LoadModFile(ld, ctx) for m := range relevantMods { if reqs.IsDirect(m.Path) { relevantMods[m] |= direct @@ -1716,7 +1740,7 @@ func (r *resolver) checkPackageProblems(loaderstate *modload.State, ctx context. for i := range retractions { i := i r.work.Add(func() { - err := loaderstate.CheckRetractions(ctx, retractions[i].m) + err := ld.CheckRetractions(ctx, retractions[i].m) if _, ok := errors.AsType[*modload.ModuleRetractedError](err); ok { retractions[i].message = err.Error() } @@ -1737,7 +1761,7 @@ func (r *resolver) checkPackageProblems(loaderstate *modload.State, ctx context. for i := range deprecations { i := i r.work.Add(func() { - deprecation, err := modload.CheckDeprecation(loaderstate, ctx, deprecations[i].m) + deprecation, err := modload.CheckDeprecation(ld, ctx, deprecations[i].m) if err != nil || deprecation == "" { return } @@ -1767,7 +1791,7 @@ func (r *resolver) checkPackageProblems(loaderstate *modload.State, ctx context. i := i m := r.buildList[i] mActual := m - if mRepl := modload.Replacement(loaderstate, m); mRepl.Path != "" { + if mRepl := modload.Replacement(ld, m); mRepl.Path != "" { mActual = mRepl } old := module.Version{Path: m.Path, Version: r.initialVersion[m.Path]} @@ -1775,14 +1799,14 @@ func (r *resolver) checkPackageProblems(loaderstate *modload.State, ctx context. continue } oldActual := old - if oldRepl := modload.Replacement(loaderstate, old); oldRepl.Path != "" { + if oldRepl := modload.Replacement(ld, old); oldRepl.Path != "" { oldActual = oldRepl } - if mActual == oldActual || mActual.Version == "" || !modfetch.HaveSum(oldActual) { + if mActual == oldActual || mActual.Version == "" || !modfetch.HaveSum(ld.Fetcher(), oldActual) { continue } r.work.Add(func() { - if _, err := modfetch.DownloadZip(ctx, mActual); err != nil { + if _, err := ld.Fetcher().DownloadZip(ctx, mActual); err != nil { verb := "upgraded" if gover.ModCompare(m.Path, m.Version, old.Version) < 0 { verb = "downgraded" @@ -1946,17 +1970,17 @@ func (r *resolver) reportChanges(oldReqs, newReqs []module.Version) { // resolve records that module m must be at its indicated version (which may be // "none") due to query q. If some other query forces module m to be at a // different version, resolve reports a conflict error. -func (r *resolver) resolve(s *modload.State, q *query, m module.Version) { +func (r *resolver) resolve(s *modload.Loader, q *query, m module.Version) { if m.Path == "" { panic("internal error: resolving a module.Version with an empty path") } if s.MainModules.Contains(m.Path) && m.Version != "" { reportError(q, &modload.QueryMatchesMainModulesError{ - LoaderState: s, - MainModules: []module.Version{{Path: m.Path}}, - Pattern: q.pattern, - Query: q.version, + MainModules: []module.Version{{Path: m.Path}}, + Pattern: q.pattern, + Query: q.version, + PatternIsModule: s.MainModules.Contains(q.pattern), }) return } @@ -1979,20 +2003,20 @@ func (r *resolver) resolve(s *modload.State, q *query, m module.Version) { // // If the resulting build list is the same as the one resulting from the last // call to updateBuildList, updateBuildList returns with changed=false. -func (r *resolver) updateBuildList(loaderstate *modload.State, ctx context.Context, additions []module.Version) (changed bool) { +func (r *resolver) updateBuildList(ld *modload.Loader, ctx context.Context, additions []module.Version) (changed bool) { defer base.ExitIfErrors() resolved := make([]module.Version, 0, len(r.resolvedVersion)) for mPath, rv := range r.resolvedVersion { - if !loaderstate.MainModules.Contains(mPath) { + if !ld.MainModules.Contains(mPath) { resolved = append(resolved, module.Version{Path: mPath, Version: rv.version}) } } - changed, err := modload.EditBuildList(loaderstate, ctx, additions, resolved) + changed, err := modload.EditBuildList(ld, ctx, additions, resolved) if err != nil { if errors.Is(err, gover.ErrTooNew) { - toolchain.SwitchOrFatal(loaderstate, ctx, err) + toolchain.SwitchOrFatal(ld, ctx, err) } constraint, ok := errors.AsType[*modload.ConstraintError](err) @@ -2036,9 +2060,9 @@ func (r *resolver) updateBuildList(loaderstate *modload.State, ctx context.Conte return false } - mg, err := modload.LoadModGraph(loaderstate, ctx, "") + mg, err := modload.LoadModGraph(ld, ctx, "") if err != nil { - toolchain.SwitchOrFatal(loaderstate, ctx, err) + toolchain.SwitchOrFatal(ld, ctx, err) } r.buildList = mg.BuildList() diff --git a/src/cmd/go/internal/modget/query.go b/src/cmd/go/internal/modget/query.go index 75d32dc633a420..6919cb53ea34c7 100644 --- a/src/cmd/go/internal/modget/query.go +++ b/src/cmd/go/internal/modget/query.go @@ -139,8 +139,11 @@ func errSet(err error) pathSet { return pathSet{err: err} } // newQuery returns a new query parsed from the raw argument, // which must be either path or path@version. -func newQuery(loaderstate *modload.State, raw string) (*query, error) { - pattern, rawVers, found := strings.Cut(raw, "@") +func newQuery(ld *modload.Loader, raw string) (*query, error) { + pattern, rawVers, found, err := modload.ParsePathVersion(raw) + if err != nil { + return nil, err + } if found && (strings.Contains(rawVers, "@") || rawVers == "") { return nil, fmt.Errorf("invalid module version syntax %q", raw) } @@ -167,14 +170,14 @@ func newQuery(loaderstate *modload.State, raw string) (*query, error) { q.matchWildcard = pkgpattern.MatchPattern(q.pattern) q.canMatchWildcardInModule = pkgpattern.TreeCanMatchPattern(q.pattern) } - if err := q.validate(loaderstate); err != nil { + if err := q.validate(ld); err != nil { return q, err } return q, nil } // validate reports a non-nil error if q is not sensible and well-formed. -func (q *query) validate(loaderstate *modload.State) error { +func (q *query) validate(ld *modload.Loader) error { if q.patternIsLocal { if q.rawVersion != "" { return fmt.Errorf("can't request explicit version %q of path %q in main module", q.rawVersion, q.pattern) @@ -184,15 +187,15 @@ func (q *query) validate(loaderstate *modload.State) error { if q.pattern == "all" { // If there is no main module, "all" is not meaningful. - if !modload.HasModRoot(loaderstate) { - return fmt.Errorf(`cannot match "all": %v`, modload.NewNoMainModulesError(loaderstate)) + if !ld.HasModRoot() { + return fmt.Errorf(`cannot match "all": %v`, modload.NewNoMainModulesError(ld)) } if !versionOkForMainModule(q.version) { // TODO(bcmills): "all@none" seems like a totally reasonable way to // request that we remove all module requirements, leaving only the main // module and standard library. Perhaps we should implement that someday. return &modload.QueryUpgradesAllError{ - MainModules: loaderstate.MainModules.Versions(), + MainModules: ld.MainModules.Versions(), Query: q.version, } } diff --git a/src/cmd/go/internal/modindex/build.go b/src/cmd/go/internal/modindex/build.go index 053e04dfe599e9..c0acb8ff587d7f 100644 --- a/src/cmd/go/internal/modindex/build.go +++ b/src/cmd/go/internal/modindex/build.go @@ -182,9 +182,10 @@ func fileListForExt(p *build.Package, ext string) *[]string { } var ( - slashSlash = []byte("//") - slashStar = []byte("/*") - starSlash = []byte("*/") + bSlashSlash = []byte("//") + bSlashStar = []byte("/*") + bStarSlash = []byte("*/") + bPlusBuild = []byte("+build") ) var dummyPkg build.Package @@ -296,11 +297,6 @@ func cleanDecls(m map[string][]token.Position) ([]string, map[string][]token.Pos } var ( - bSlashSlash = slashSlash - bStarSlash = starSlash - bSlashStar = slashStar - bPlusBuild = []byte("+build") - goBuildComment = []byte("//go:build") errMultipleGoBuild = errors.New("multiple //go:build comments") @@ -382,7 +378,7 @@ Lines: end = len(content) - len(p) continue Lines } - if !bytes.HasPrefix(line, slashSlash) { // Not comment line + if !bytes.HasPrefix(line, bSlashSlash) { // Not comment line ended = true } @@ -399,9 +395,9 @@ Lines: Comments: for len(line) > 0 { if inSlashStar { - if i := bytes.Index(line, starSlash); i >= 0 { + if i := bytes.Index(line, bStarSlash); i >= 0 { inSlashStar = false - line = bytes.TrimSpace(line[i+len(starSlash):]) + line = bytes.TrimSpace(line[i+len(bStarSlash):]) continue Comments } continue Lines diff --git a/src/cmd/go/internal/modindex/build_read.go b/src/cmd/go/internal/modindex/build_read.go index f2e48f36cdff54..0eb28e8b98576f 100644 --- a/src/cmd/go/internal/modindex/build_read.go +++ b/src/cmd/go/internal/modindex/build_read.go @@ -304,7 +304,7 @@ func readGoInfo(f io.Reader, info *fileInfo) error { } // Parse file header & record imports. - info.parsed, info.parseErr = parser.ParseFile(info.fset, info.name, info.header, parser.ImportsOnly|parser.ParseComments) + info.parsed, info.parseErr = parser.ParseFile(info.fset, info.name, info.header, parser.ImportsOnly|parser.ParseComments|parser.SkipObjectResolution) if info.parseErr != nil { return nil } @@ -328,7 +328,7 @@ func readGoInfo(f io.Reader, info *fileInfo) error { if !isValidImport(path) { // The parser used to return a parse error for invalid import paths, but // no longer does, so check for and create the error here instead. - info.parseErr = scanner.Error{Pos: info.fset.Position(spec.Pos()), Msg: "invalid import path: " + path} + info.parseErr = &scanner.Error{Pos: info.fset.Position(spec.Pos()), Msg: "invalid import path: " + path} info.imports = nil return nil } diff --git a/src/cmd/go/internal/modindex/read.go b/src/cmd/go/internal/modindex/read.go index 399e89eca3cf47..529c26ea057019 100644 --- a/src/cmd/go/internal/modindex/read.go +++ b/src/cmd/go/internal/modindex/read.go @@ -138,7 +138,7 @@ func GetPackage(modroot, pkgdir string) (*IndexPackage, error) { if !errors.Is(err, errNotFromModuleCache) { return nil, err } - if cfg.BuildContext.Compiler == "gccgo" && str.HasPathPrefix(modroot, cfg.GOROOTsrc) { + if cfg.BuildContext.Compiler == "gccgo" && str.HasFilePathPrefix(modroot, cfg.GOROOTsrc) { return nil, err // gccgo has no sources for GOROOT packages. } // The pkgdir for fips140 has been replaced in the fsys overlay, @@ -403,6 +403,7 @@ func (rp *IndexPackage) Import(bctxt build.Context, mode build.ImportMode) (p *b // goroot and gopath inTestdata := func(sub string) bool { + sub = filepath.ToSlash(sub) return strings.Contains(sub, "/testdata/") || strings.HasSuffix(sub, "/testdata") || str.HasPathPrefix(sub, "testdata") } var pkga string @@ -680,7 +681,7 @@ func (rp *IndexPackage) Import(bctxt build.Context, mode build.ImportMode) (p *b // and otherwise falling back to internal/goroot.IsStandardPackage func IsStandardPackage(goroot_, compiler, path string) bool { if !enabled || compiler != "gc" { - return goroot.IsStandardPackage(goroot_, compiler, path) + return goroot.IsStandardPackage(fsys.ReadDir, goroot_, compiler, path) } reldir := filepath.FromSlash(path) // relative dir path in module index for package @@ -695,7 +696,7 @@ func IsStandardPackage(goroot_, compiler, path string) bool { } else if errors.Is(err, ErrNotIndexed) { // Fall back because package isn't indexable. (Probably because // a file was modified recently) - return goroot.IsStandardPackage(goroot_, compiler, path) + return goroot.IsStandardPackage(fsys.ReadDir, goroot_, compiler, path) } return false } diff --git a/src/cmd/go/internal/modindex/scan.go b/src/cmd/go/internal/modindex/scan.go index af2c0abe046d72..beded695bfc873 100644 --- a/src/cmd/go/internal/modindex/scan.go +++ b/src/cmd/go/internal/modindex/scan.go @@ -112,10 +112,10 @@ func parseErrorToString(err error) string { return "" } var p parseError - if e, ok := err.(scanner.ErrorList); ok { - p.ErrorList = &e + if errlist, ok := err.(scanner.ErrorList); ok { + p.ErrorList = &errlist } else { - p.ErrorString = e.Error() + p.ErrorString = err.Error() } s, err := json.Marshal(p) if err != nil { diff --git a/src/cmd/go/internal/modload/build.go b/src/cmd/go/internal/modload/build.go index 7299452670c13f..518e544e494ef9 100644 --- a/src/cmd/go/internal/modload/build.go +++ b/src/cmd/go/internal/modload/build.go @@ -12,7 +12,6 @@ import ( "io/fs" "os" "path/filepath" - "strings" "cmd/go/internal/base" "cmd/go/internal/cfg" @@ -51,59 +50,68 @@ func findStandardImportPath(path string) string { // a given package. If modules are not enabled or if the package is in the // standard library or if the package was not successfully loaded with // LoadPackages or ImportFromFiles, nil is returned. -func PackageModuleInfo(loaderstate *State, ctx context.Context, pkgpath string) *modinfo.ModulePublic { - if isStandardImportPath(pkgpath) || !Enabled(loaderstate) { +func PackageModuleInfo(ld *Loader, ctx context.Context, pkgpath string) *modinfo.ModulePublic { + if isStandardImportPath(pkgpath) || !ld.Enabled() { return nil } - m, ok := findModule(loaded, pkgpath) + m, ok := findModule(ld.pkgLoader, pkgpath) if !ok { return nil } - rs := LoadModFile(loaderstate, ctx) - return moduleInfo(loaderstate, ctx, rs, m, 0, nil) + rs := LoadModFile(ld, ctx) + return moduleInfo(ld, ctx, rs, m, 0, nil) } // PackageModRoot returns the module root directory for the module that provides // a given package. If modules are not enabled or if the package is in the // standard library or if the package was not successfully loaded with // LoadPackages or ImportFromFiles, the empty string is returned. -func PackageModRoot(loaderstate *State, ctx context.Context, pkgpath string) string { - if isStandardImportPath(pkgpath) || !Enabled(loaderstate) || cfg.BuildMod == "vendor" { +func PackageModRoot(ld *Loader, ctx context.Context, pkgpath string) string { + if isStandardImportPath(pkgpath) || !ld.Enabled() || cfg.BuildMod == "vendor" { return "" } - m, ok := findModule(loaded, pkgpath) + m, ok := findModule(ld.pkgLoader, pkgpath) if !ok { return "" } - root, _, err := fetch(loaderstate, ctx, m) + root, _, err := fetch(ld, ctx, m) if err != nil { return "" } return root } -func ModuleInfo(loaderstate *State, ctx context.Context, path string) *modinfo.ModulePublic { - if !Enabled(loaderstate) { +func ModuleInfo(ld *Loader, ctx context.Context, path string) *modinfo.ModulePublic { + if !ld.Enabled() { return nil } - if path, vers, found := strings.Cut(path, "@"); found { + path, vers, found, err := ParsePathVersion(path) + if err != nil { + return &modinfo.ModulePublic{ + Path: path, + Error: &modinfo.ModuleError{ + Err: err.Error(), + }, + } + } + if found { m := module.Version{Path: path, Version: vers} - return moduleInfo(loaderstate, ctx, nil, m, 0, nil) + return moduleInfo(ld, ctx, nil, m, 0, nil) } - rs := LoadModFile(loaderstate, ctx) + rs := LoadModFile(ld, ctx) var ( v string ok bool ) if rs.pruning == pruned { - v, ok = rs.rootSelected(loaderstate, path) + v, ok = rs.rootSelected(ld, path) } if !ok { - mg, err := rs.Graph(loaderstate, ctx) + mg, err := rs.Graph(ld, ctx) if err != nil { base.Fatal(err) } @@ -119,16 +127,16 @@ func ModuleInfo(loaderstate *State, ctx context.Context, path string) *modinfo.M } } - return moduleInfo(loaderstate, ctx, rs, module.Version{Path: path, Version: v}, 0, nil) + return moduleInfo(ld, ctx, rs, module.Version{Path: path, Version: v}, 0, nil) } // addUpdate fills in m.Update if an updated version is available. -func addUpdate(loaderstate *State, ctx context.Context, m *modinfo.ModulePublic) { +func addUpdate(ld *Loader, ctx context.Context, m *modinfo.ModulePublic) { if m.Version == "" { return } - info, err := Query(loaderstate, ctx, m.Path, "upgrade", m.Version, loaderstate.CheckAllowed) + info, err := Query(ld, ctx, m.Path, "upgrade", m.Version, ld.CheckAllowed) if _, ok := errors.AsType[*NoMatchingVersionError](err); ok || errors.Is(err, fs.ErrNotExist) || errors.Is(err, ErrDisallowed) { @@ -189,6 +197,12 @@ func mergeOrigin(m1, m2 *codehost.Origin) *codehost.Origin { merged.TagSum = m2.TagSum merged.TagPrefix = m2.TagPrefix } + if m2.RepoSum != "" { + if m1.RepoSum != "" && m1.RepoSum != m2.RepoSum { + return nil + } + merged.RepoSum = m2.RepoSum + } if m2.Ref != "" { if m1.Ref != "" && m1.Ref != m2.Ref { return nil @@ -212,16 +226,16 @@ func mergeOrigin(m1, m2 *codehost.Origin) *codehost.Origin { // addVersions fills in m.Versions with the list of known versions. // Excluded versions will be omitted. If listRetracted is false, retracted // versions will also be omitted. -func addVersions(loaderstate *State, ctx context.Context, m *modinfo.ModulePublic, listRetracted bool) { +func addVersions(ld *Loader, ctx context.Context, m *modinfo.ModulePublic, listRetracted bool) { // TODO(bcmills): Would it make sense to check for reuse here too? // Perhaps that doesn't buy us much, though: we would always have to fetch // all of the version tags to list the available versions anyway. - allowed := loaderstate.CheckAllowed + allowed := ld.CheckAllowed if listRetracted { - allowed = loaderstate.CheckExclusions + allowed = ld.CheckExclusions } - v, origin, err := versions(loaderstate, ctx, m.Path, allowed) + v, origin, err := versions(ld, ctx, m.Path, allowed) if err != nil && m.Error == nil { m.Error = &modinfo.ModuleError{Err: err.Error()} } @@ -231,12 +245,12 @@ func addVersions(loaderstate *State, ctx context.Context, m *modinfo.ModulePubli // addRetraction fills in m.Retracted if the module was retracted by its author. // m.Error is set if there's an error loading retraction information. -func addRetraction(loaderstate *State, ctx context.Context, m *modinfo.ModulePublic) { +func addRetraction(ld *Loader, ctx context.Context, m *modinfo.ModulePublic) { if m.Version == "" { return } - err := loaderstate.CheckRetractions(ctx, module.Version{Path: m.Path, Version: m.Version}) + err := ld.CheckRetractions(ctx, module.Version{Path: m.Path, Version: m.Version}) if err == nil { return } else if _, ok := errors.AsType[*NoMatchingVersionError](err); ok || errors.Is(err, fs.ErrNotExist) { @@ -262,8 +276,8 @@ func addRetraction(loaderstate *State, ctx context.Context, m *modinfo.ModulePub // addDeprecation fills in m.Deprecated if the module was deprecated by its // author. m.Error is set if there's an error loading deprecation information. -func addDeprecation(loaderstate *State, ctx context.Context, m *modinfo.ModulePublic) { - deprecation, err := CheckDeprecation(loaderstate, ctx, module.Version{Path: m.Path, Version: m.Version}) +func addDeprecation(ld *Loader, ctx context.Context, m *modinfo.ModulePublic) { + deprecation, err := CheckDeprecation(ld, ctx, module.Version{Path: m.Path, Version: m.Version}) if _, ok := errors.AsType[*NoMatchingVersionError](err); ok || errors.Is(err, fs.ErrNotExist) { // Ignore "no matching version" and "not found" errors. // This means the proxy has no matching version or no versions at all. @@ -287,8 +301,8 @@ func addDeprecation(loaderstate *State, ctx context.Context, m *modinfo.ModulePu // moduleInfo returns information about module m, loaded from the requirements // in rs (which may be nil to indicate that m was not loaded from a requirement // graph). -func moduleInfo(loaderstate *State, ctx context.Context, rs *Requirements, m module.Version, mode ListMode, reuse map[module.Version]*modinfo.ModulePublic) *modinfo.ModulePublic { - if m.Version == "" && loaderstate.MainModules.Contains(m.Path) { +func moduleInfo(ld *Loader, ctx context.Context, rs *Requirements, m module.Version, mode ListMode, reuse map[module.Version]*modinfo.ModulePublic) *modinfo.ModulePublic { + if m.Version == "" && ld.MainModules.Contains(m.Path) { info := &modinfo.ModulePublic{ Path: m.Path, Version: m.Version, @@ -299,7 +313,7 @@ func moduleInfo(loaderstate *State, ctx context.Context, rs *Requirements, m mod } else { panic("internal error: GoVersion not set for main module") } - if modRoot := loaderstate.MainModules.ModRoot(m); modRoot != "" { + if modRoot := ld.MainModules.ModRoot(m); modRoot != "" { info.Dir = modRoot info.GoMod = modFilePath(modRoot) } @@ -322,15 +336,15 @@ func moduleInfo(loaderstate *State, ctx context.Context, rs *Requirements, m mod } checksumOk := func(suffix string) bool { - return rs == nil || m.Version == "" || !mustHaveSums(loaderstate) || - modfetch.HaveSum(module.Version{Path: m.Path, Version: m.Version + suffix}) + return rs == nil || m.Version == "" || !mustHaveSums(ld) || + modfetch.HaveSum(ld.Fetcher(), module.Version{Path: m.Path, Version: m.Version + suffix}) } mod := module.Version{Path: m.Path, Version: m.Version} if m.Version != "" { if old := reuse[mod]; old != nil { - if err := checkReuse(loaderstate, ctx, mod, old.Origin); err == nil { + if err := checkReuse(ld, ctx, mod, old.Origin); err == nil { *m = *old m.Query = "" m.Dir = "" @@ -338,7 +352,7 @@ func moduleInfo(loaderstate *State, ctx context.Context, rs *Requirements, m mod } } - if q, err := Query(loaderstate, ctx, m.Path, m.Version, "", nil); err != nil { + if q, err := Query(ld, ctx, m.Path, m.Version, "", nil); err != nil { m.Error = &modinfo.ModuleError{Err: err.Error()} } else { m.Version = q.Version @@ -349,7 +363,7 @@ func moduleInfo(loaderstate *State, ctx context.Context, rs *Requirements, m mod if m.GoVersion == "" && checksumOk("/go.mod") { // Load the go.mod file to determine the Go version, since it hasn't // already been populated from rawGoVersion. - if summary, err := rawGoModSummary(loaderstate, mod); err == nil && summary.goVersion != "" { + if summary, err := rawGoModSummary(ld, mod); err == nil && summary.goVersion != "" { m.GoVersion = summary.goVersion } } @@ -362,7 +376,7 @@ func moduleInfo(loaderstate *State, ctx context.Context, rs *Requirements, m mod m.GoMod = gomod } } - if gomodsum, ok := modfetch.RecordedSum(modkey(mod)); ok { + if gomodsum, ok := ld.fetcher.RecordedSum(modkey(mod)); ok { m.GoModSum = gomodsum } } @@ -371,13 +385,13 @@ func moduleInfo(loaderstate *State, ctx context.Context, rs *Requirements, m mod if err == nil { m.Dir = dir } - if sum, ok := modfetch.RecordedSum(mod); ok { + if sum, ok := ld.fetcher.RecordedSum(mod); ok { m.Sum = sum } } if mode&ListRetracted != 0 { - addRetraction(loaderstate, ctx, m) + addRetraction(ld, ctx, m) } } } @@ -389,7 +403,7 @@ func moduleInfo(loaderstate *State, ctx context.Context, rs *Requirements, m mod return info } - r := Replacement(loaderstate, m) + r := Replacement(ld, m) if r.Path == "" { if cfg.BuildMod == "vendor" { // It's tempting to fill in the "Dir" field to point within the vendor @@ -418,7 +432,7 @@ func moduleInfo(loaderstate *State, ctx context.Context, rs *Requirements, m mod if filepath.IsAbs(r.Path) { info.Replace.Dir = r.Path } else { - info.Replace.Dir = filepath.Join(replaceRelativeTo(loaderstate), r.Path) + info.Replace.Dir = filepath.Join(replaceRelativeTo(ld), r.Path) } info.Replace.GoMod = filepath.Join(info.Replace.Dir, "go.mod") } @@ -435,8 +449,8 @@ func moduleInfo(loaderstate *State, ctx context.Context, rs *Requirements, m mod // findModule searches for the module that contains the package at path. // If the package was loaded, its containing module and true are returned. // Otherwise, module.Version{} and false are returned. -func findModule(ld *loader, path string) (module.Version, bool) { - if pkg, ok := ld.pkgCache.Get(path); ok { +func findModule(pld *packageLoader, path string) (module.Version, bool) { + if pkg, ok := pld.pkgCache.Get(path); ok { return pkg.mod, pkg.mod != module.Version{} } return module.Version{}, false diff --git a/src/cmd/go/internal/modload/buildlist.go b/src/cmd/go/internal/modload/buildlist.go index cb64bec9c81d12..73e881ef3cf360 100644 --- a/src/cmd/go/internal/modload/buildlist.go +++ b/src/cmd/go/internal/modload/buildlist.go @@ -104,21 +104,21 @@ func mustHaveGoRoot(roots []module.Version) { // // If vendoring is in effect, the caller must invoke initVendor on the returned // *Requirements before any other method. -func newRequirements(loaderstate *State, pruning modPruning, rootModules []module.Version, direct map[string]bool) *Requirements { +func newRequirements(ld *Loader, pruning modPruning, rootModules []module.Version, direct map[string]bool) *Requirements { mustHaveGoRoot(rootModules) if pruning != workspace { - if loaderstate.workFilePath != "" { + if ld.workFilePath != "" { panic("in workspace mode, but pruning is not workspace in newRequirements") } } if pruning != workspace { - if loaderstate.workFilePath != "" { + if ld.workFilePath != "" { panic("in workspace mode, but pruning is not workspace in newRequirements") } for i, m := range rootModules { - if m.Version == "" && loaderstate.MainModules.Contains(m.Path) { + if m.Version == "" && ld.MainModules.Contains(m.Path) { panic(fmt.Sprintf("newRequirements called with untrimmed build list: rootModules[%v] is a main module", i)) } if m.Path == "" || m.Version == "" { @@ -162,10 +162,10 @@ func (rs *Requirements) String() string { // initVendor initializes rs.graph from the given list of vendored module // dependencies, overriding the graph that would normally be loaded from module // requirements. -func (rs *Requirements) initVendor(loaderstate *State, vendorList []module.Version) { +func (rs *Requirements) initVendor(ld *Loader, vendorList []module.Version) { rs.graphOnce.Do(func() { - roots := loaderstate.MainModules.Versions() - if inWorkspaceMode(loaderstate) { + roots := ld.MainModules.Versions() + if ld.inWorkspaceMode() { // Use rs.rootModules to pull in the go and toolchain roots // from the go.work file and preserve the invariant that all // of rs.rootModules are in mg.g. @@ -176,7 +176,7 @@ func (rs *Requirements) initVendor(loaderstate *State, vendorList []module.Versi } if rs.pruning == pruned { - mainModule := loaderstate.MainModules.mustGetSingleMainModule(loaderstate) + mainModule := ld.MainModules.mustGetSingleMainModule(ld) // The roots of a single pruned module should already include every module in the // vendor list, because the vendored modules are the same as those needed // for graph pruning. @@ -184,7 +184,7 @@ func (rs *Requirements) initVendor(loaderstate *State, vendorList []module.Versi // Just to be sure, we'll double-check that here. inconsistent := false for _, m := range vendorList { - if v, ok := rs.rootSelected(loaderstate, m.Path); !ok || v != m.Version { + if v, ok := rs.rootSelected(ld, m.Path); !ok || v != m.Version { base.Errorf("go: vendored module %v should be required explicitly in go.mod", m) inconsistent = true } @@ -208,15 +208,15 @@ func (rs *Requirements) initVendor(loaderstate *State, vendorList []module.Versi // graph, but still distinguishes between direct and indirect // dependencies. vendorMod := module.Version{Path: "vendor/modules.txt", Version: ""} - if inWorkspaceMode(loaderstate) { - for _, m := range loaderstate.MainModules.Versions() { - reqs, _ := rootsFromModFile(loaderstate, m, loaderstate.MainModules.ModFile(m), omitToolchainRoot) + if ld.inWorkspaceMode() { + for _, m := range ld.MainModules.Versions() { + reqs, _ := rootsFromModFile(ld, m, ld.MainModules.ModFile(m), omitToolchainRoot) mg.g.Require(m, append(reqs, vendorMod)) } mg.g.Require(vendorMod, vendorList) } else { - mainModule := loaderstate.MainModules.mustGetSingleMainModule(loaderstate) + mainModule := ld.MainModules.mustGetSingleMainModule(ld) mg.g.Require(mainModule, append(rs.rootModules, vendorMod)) mg.g.Require(vendorMod, vendorList) } @@ -227,8 +227,8 @@ func (rs *Requirements) initVendor(loaderstate *State, vendorList []module.Versi } // GoVersion returns the Go language version for the Requirements. -func (rs *Requirements) GoVersion(loaderstate *State) string { - v, _ := rs.rootSelected(loaderstate, "go") +func (rs *Requirements) GoVersion(ld *Loader) string { + v, _ := rs.rootSelected(ld, "go") if v == "" { panic("internal error: missing go version in modload.Requirements") } @@ -238,8 +238,8 @@ func (rs *Requirements) GoVersion(loaderstate *State) string { // rootSelected returns the version of the root dependency with the given module // path, or the zero module.Version and ok=false if the module is not a root // dependency. -func (rs *Requirements) rootSelected(loaderstate *State, path string) (version string, ok bool) { - if loaderstate.MainModules.Contains(path) { +func (rs *Requirements) rootSelected(ld *Loader, path string) (version string, ok bool) { + if ld.MainModules.Contains(path) { return "", true } if v, ok := rs.maxRootVersion[path]; ok { @@ -252,9 +252,9 @@ func (rs *Requirements) rootSelected(loaderstate *State, path string) (version s // of the same module or a requirement on any version of the main module. // Redundant requirements should be pruned, but they may influence version // selection. -func (rs *Requirements) hasRedundantRoot(loaderstate *State) bool { +func (rs *Requirements) hasRedundantRoot(ld *Loader) bool { for i, m := range rs.rootModules { - if loaderstate.MainModules.Contains(m.Path) || (i > 0 && m.Path == rs.rootModules[i-1].Path) { + if ld.MainModules.Contains(m.Path) || (i > 0 && m.Path == rs.rootModules[i-1].Path) { return true } } @@ -269,9 +269,9 @@ func (rs *Requirements) hasRedundantRoot(loaderstate *State) bool { // // If the requirements of any relevant module fail to load, Graph also // returns a non-nil error of type *mvs.BuildListError. -func (rs *Requirements) Graph(loaderstate *State, ctx context.Context) (*ModuleGraph, error) { +func (rs *Requirements) Graph(ld *Loader, ctx context.Context) (*ModuleGraph, error) { rs.graphOnce.Do(func() { - mg, mgErr := readModGraph(loaderstate, ctx, rs.pruning, rs.rootModules, nil) + mg, mgErr := readModGraph(ld, ctx, rs.pruning, rs.rootModules, nil) rs.graph.Store(&cachedGraph{mg, mgErr}) }) cached := rs.graph.Load() @@ -295,6 +295,10 @@ type ModuleGraph struct { buildListOnce sync.Once buildList []module.Version + + // checkPathsOnce ensures checkMultiplePaths runs at most once per graph. + // Errors are checked and reported only on the first call. + checkPathsOnce sync.Once } var readModGraphDebugOnce sync.Once @@ -307,7 +311,7 @@ var readModGraphDebugOnce sync.Once // // Unlike LoadModGraph, readModGraph does not attempt to diagnose or update // inconsistent roots. -func readModGraph(loaderstate *State, ctx context.Context, pruning modPruning, roots []module.Version, unprune map[module.Version]bool) (*ModuleGraph, error) { +func readModGraph(ld *Loader, ctx context.Context, pruning modPruning, roots []module.Version, unprune map[module.Version]bool) (*ModuleGraph, error) { mustHaveGoRoot(roots) if pruning == pruned { // Enable diagnostics for lazy module loading @@ -333,10 +337,10 @@ func readModGraph(loaderstate *State, ctx context.Context, pruning modPruning, r } var graphRoots []module.Version - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { graphRoots = roots } else { - graphRoots = loaderstate.MainModules.Versions() + graphRoots = ld.MainModules.Versions() } var ( mu sync.Mutex // guards mg.g and hasError during loading @@ -347,10 +351,10 @@ func readModGraph(loaderstate *State, ctx context.Context, pruning modPruning, r ) if pruning != workspace { - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { panic("pruning is not workspace in workspace mode") } - mg.g.Require(loaderstate.MainModules.mustGetSingleMainModule(loaderstate), roots) + mg.g.Require(ld.MainModules.mustGetSingleMainModule(ld), roots) } type dedupKey struct { @@ -367,7 +371,7 @@ func readModGraph(loaderstate *State, ctx context.Context, pruning modPruning, r // m's go.mod file indicates that it supports graph pruning. loadOne := func(m module.Version) (*modFileSummary, error) { return mg.loadCache.Do(m, func() (*modFileSummary, error) { - summary, err := goModSummary(loaderstate, m) + summary, err := goModSummary(ld, m) mu.Lock() if err == nil { @@ -527,12 +531,12 @@ func (mg *ModuleGraph) findError() error { return nil } -func (mg *ModuleGraph) allRootsSelected(loaderstate *State) bool { +func (mg *ModuleGraph) allRootsSelected(ld *Loader) bool { var roots []module.Version - if inWorkspaceMode(loaderstate) { - roots = loaderstate.MainModules.Versions() + if ld.inWorkspaceMode() { + roots = ld.MainModules.Versions() } else { - roots, _ = mg.g.RequiredBy(loaderstate.MainModules.mustGetSingleMainModule(loaderstate)) + roots, _ = mg.g.RequiredBy(ld.MainModules.mustGetSingleMainModule(ld)) } for _, m := range roots { if mg.Selected(m.Path) != m.Version { @@ -552,14 +556,14 @@ func (mg *ModuleGraph) allRootsSelected(loaderstate *State) bool { // Modules are loaded automatically (and lazily) in LoadPackages: // LoadModGraph need only be called if LoadPackages is not, // typically in commands that care about modules but no particular package. -func LoadModGraph(loaderstate *State, ctx context.Context, goVersion string) (*ModuleGraph, error) { - rs, err := loadModFile(loaderstate, ctx, nil) +func LoadModGraph(ld *Loader, ctx context.Context, goVersion string) (*ModuleGraph, error) { + rs, err := loadModFile(ld, ctx, nil) if err != nil { return nil, err } if goVersion != "" { - v, _ := rs.rootSelected(loaderstate, "go") + v, _ := rs.rootSelected(ld, "go") if gover.Compare(v, gover.GoStrictVersion) >= 0 && gover.Compare(goVersion, v) < 0 { return nil, fmt.Errorf("requested Go version %s cannot load module graph (requires Go >= %s)", goVersion, v) } @@ -569,17 +573,17 @@ func LoadModGraph(loaderstate *State, ctx context.Context, goVersion string) (*M // Use newRequirements instead of convertDepth because convertDepth // also updates roots; here, we want to report the unmodified roots // even though they may seem inconsistent. - rs = newRequirements(loaderstate, unpruned, rs.rootModules, rs.direct) + rs = newRequirements(ld, unpruned, rs.rootModules, rs.direct) } - return rs.Graph(loaderstate, ctx) + return rs.Graph(ld, ctx) } - rs, mg, err := expandGraph(loaderstate, ctx, rs) + rs, mg, err := expandGraph(ld, ctx, rs) if err != nil { return nil, err } - loaderstate.requirements = rs + ld.requirements = rs return mg, nil } @@ -594,22 +598,22 @@ func LoadModGraph(loaderstate *State, ctx context.Context, goVersion string) (*M // from those roots and any error encountered while loading that graph. // expandGraph returns non-nil requirements and a non-nil graph regardless of // errors. On error, the roots might not be updated to be consistent. -func expandGraph(loaderstate *State, ctx context.Context, rs *Requirements) (*Requirements, *ModuleGraph, error) { - mg, mgErr := rs.Graph(loaderstate, ctx) +func expandGraph(ld *Loader, ctx context.Context, rs *Requirements) (*Requirements, *ModuleGraph, error) { + mg, mgErr := rs.Graph(ld, ctx) if mgErr != nil { // Without the graph, we can't update the roots: we don't know which // versions of transitive dependencies would be selected. return rs, mg, mgErr } - if !mg.allRootsSelected(loaderstate) { + if !mg.allRootsSelected(ld) { // The roots of rs are not consistent with the rest of the graph. Update // them. In an unpruned module this is a no-op for the build list as a whole — // it just promotes what were previously transitive requirements to be // roots — but in a pruned module it may pull in previously-irrelevant // transitive dependencies. - newRS, rsErr := updateRoots(loaderstate, ctx, rs.direct, rs, nil, nil, false) + newRS, rsErr := updateRoots(ld, ctx, rs.direct, rs, nil, nil, false) if rsErr != nil { // Failed to update roots, perhaps because of an error in a transitive // dependency needed for the update. Return the original Requirements @@ -617,7 +621,7 @@ func expandGraph(loaderstate *State, ctx context.Context, rs *Requirements) (*Re return rs, mg, rsErr } rs = newRS - mg, mgErr = rs.Graph(loaderstate, ctx) + mg, mgErr = rs.Graph(ld, ctx) } return rs, mg, mgErr @@ -639,16 +643,16 @@ func expandGraph(loaderstate *State, ctx context.Context, rs *Requirements) (*Re // On success, EditBuildList reports whether the selected version of any module // in the build list may have been changed (possibly to or from "none") as a // result. -func EditBuildList(loaderstate *State, ctx context.Context, add, mustSelect []module.Version) (changed bool, err error) { - rs, changed, err := editRequirements(loaderstate, ctx, LoadModFile(loaderstate, ctx), add, mustSelect) +func EditBuildList(ld *Loader, ctx context.Context, add, mustSelect []module.Version) (changed bool, err error) { + rs, changed, err := editRequirements(ld, ctx, LoadModFile(ld, ctx), add, mustSelect) if err != nil { return false, err } - loaderstate.requirements = rs + ld.requirements = rs return changed, nil } -func overrideRoots(loaderstate *State, ctx context.Context, rs *Requirements, replace []module.Version) *Requirements { +func overrideRoots(ld *Loader, ctx context.Context, rs *Requirements, replace []module.Version) *Requirements { drop := make(map[string]bool) for _, m := range replace { drop[m.Path] = true @@ -661,7 +665,7 @@ func overrideRoots(loaderstate *State, ctx context.Context, rs *Requirements, re } roots = append(roots, replace...) gover.ModSort(roots) - return newRequirements(loaderstate, rs.pruning, roots, rs.direct) + return newRequirements(ld, rs.pruning, roots, rs.direct) } // A ConstraintError describes inconsistent constraints in EditBuildList @@ -765,28 +769,28 @@ func (c Conflict) String() string { // tidyRoots trims the root dependencies to the minimal requirements needed to // both retain the same versions of all packages in pkgs and satisfy the // graph-pruning invariants (if applicable). -func tidyRoots(loaderstate *State, ctx context.Context, rs *Requirements, pkgs []*loadPkg) (*Requirements, error) { - mainModule := loaderstate.MainModules.mustGetSingleMainModule(loaderstate) +func tidyRoots(ld *Loader, ctx context.Context, rs *Requirements, pkgs []*loadPkg) (*Requirements, error) { + mainModule := ld.MainModules.mustGetSingleMainModule(ld) if rs.pruning == unpruned { - return tidyUnprunedRoots(loaderstate, ctx, mainModule, rs, pkgs) + return tidyUnprunedRoots(ld, ctx, mainModule, rs, pkgs) } - return tidyPrunedRoots(loaderstate, ctx, mainModule, rs, pkgs) + return tidyPrunedRoots(ld, ctx, mainModule, rs, pkgs) } -func updateRoots(loaderstate *State, ctx context.Context, direct map[string]bool, rs *Requirements, pkgs []*loadPkg, add []module.Version, rootsImported bool) (*Requirements, error) { +func updateRoots(ld *Loader, ctx context.Context, direct map[string]bool, rs *Requirements, pkgs []*loadPkg, add []module.Version, rootsImported bool) (*Requirements, error) { switch rs.pruning { case unpruned: - return updateUnprunedRoots(loaderstate, ctx, direct, rs, add) + return updateUnprunedRoots(ld, ctx, direct, rs, add) case pruned: - return updatePrunedRoots(loaderstate, ctx, direct, rs, pkgs, add, rootsImported) + return updatePrunedRoots(ld, ctx, direct, rs, pkgs, add, rootsImported) case workspace: - return updateWorkspaceRoots(loaderstate, ctx, direct, rs, add) + return updateWorkspaceRoots(ld, ctx, direct, rs, add) default: panic(fmt.Sprintf("unsupported pruning mode: %v", rs.pruning)) } } -func updateWorkspaceRoots(loaderstate *State, ctx context.Context, direct map[string]bool, rs *Requirements, add []module.Version) (*Requirements, error) { +func updateWorkspaceRoots(ld *Loader, ctx context.Context, direct map[string]bool, rs *Requirements, add []module.Version) (*Requirements, error) { if len(add) != 0 { // add should be empty in workspace mode because workspace mode implies // -mod=readonly, which in turn implies no new requirements. The code path @@ -797,7 +801,13 @@ func updateWorkspaceRoots(loaderstate *State, ctx context.Context, direct map[st // return an error. panic("add is not empty") } - return newRequirements(loaderstate, workspace, rs.rootModules, direct), nil + newRS := newRequirements(ld, workspace, rs.rootModules, direct) + // The root modules are unchanged (only the direct imports change), + // so the module graph can be reused to avoid rebuilding it from scratch. + if cached := rs.graph.Load(); cached != nil { + newRS.graphOnce.Do(func() { newRS.graph.Store(cached) }) + } + return newRS, nil } // tidyPrunedRoots returns a minimal set of root requirements that maintains the @@ -816,16 +826,16 @@ func updateWorkspaceRoots(loaderstate *State, ctx context.Context, direct map[st // To ensure that the loading process eventually converges, the caller should // add any needed roots from the tidy root set (without removing existing untidy // roots) until the set of roots has converged. -func tidyPrunedRoots(loaderstate *State, ctx context.Context, mainModule module.Version, old *Requirements, pkgs []*loadPkg) (*Requirements, error) { +func tidyPrunedRoots(ld *Loader, ctx context.Context, mainModule module.Version, old *Requirements, pkgs []*loadPkg) (*Requirements, error) { var ( roots []module.Version pathIsRoot = map[string]bool{mainModule.Path: true} ) - if v, ok := old.rootSelected(loaderstate, "go"); ok { + if v, ok := old.rootSelected(ld, "go"); ok { roots = append(roots, module.Version{Path: "go", Version: v}) pathIsRoot["go"] = true } - if v, ok := old.rootSelected(loaderstate, "toolchain"); ok { + if v, ok := old.rootSelected(ld, "toolchain"); ok { roots = append(roots, module.Version{Path: "toolchain", Version: v}) pathIsRoot["toolchain"] = true } @@ -847,7 +857,7 @@ func tidyPrunedRoots(loaderstate *State, ctx context.Context, mainModule module. if !pkg.flags.has(pkgInAll) { continue } - if pkg.fromExternalModule(loaderstate) && !pathIsRoot[pkg.mod.Path] { + if pkg.fromExternalModule(ld) && !pathIsRoot[pkg.mod.Path] { roots = append(roots, pkg.mod) pathIsRoot[pkg.mod.Path] = true } @@ -855,11 +865,11 @@ func tidyPrunedRoots(loaderstate *State, ctx context.Context, mainModule module. queued[pkg] = true } gover.ModSort(roots) - tidy := newRequirements(loaderstate, pruned, roots, old.direct) + tidy := newRequirements(ld, pruned, roots, old.direct) for len(queue) > 0 { roots = tidy.rootModules - mg, err := tidy.Graph(loaderstate, ctx) + mg, err := tidy.Graph(ld, ctx) if err != nil { return nil, err } @@ -892,12 +902,12 @@ func tidyPrunedRoots(loaderstate *State, ctx context.Context, mainModule module. if len(roots) > len(tidy.rootModules) { gover.ModSort(roots) - tidy = newRequirements(loaderstate, pruned, roots, tidy.direct) + tidy = newRequirements(ld, pruned, roots, tidy.direct) } } roots = tidy.rootModules - _, err := tidy.Graph(loaderstate, ctx) + _, err := tidy.Graph(ld, ctx) if err != nil { return nil, err } @@ -921,7 +931,7 @@ func tidyPrunedRoots(loaderstate *State, ctx context.Context, mainModule module. pkg := pkg q.Add(func() { skipModFile := true - _, _, _, _, err := importFromModules(loaderstate, ctx, pkg.path, tidy, nil, skipModFile) + _, _, _, _, err := importFromModules(ld, ctx, pkg.path, tidy, nil, skipModFile) if _, ok := errors.AsType[*AmbiguousImportError](err); ok { disambiguateRoot.Store(pkg.mod, true) } @@ -938,8 +948,8 @@ func tidyPrunedRoots(loaderstate *State, ctx context.Context, mainModule module. if len(roots) > len(tidy.rootModules) { module.Sort(roots) - tidy = newRequirements(loaderstate, pruned, roots, tidy.direct) - _, err = tidy.Graph(loaderstate, ctx) + tidy = newRequirements(ld, pruned, roots, tidy.direct) + _, err = tidy.Graph(ld, ctx) if err != nil { return nil, err } @@ -999,7 +1009,7 @@ func tidyPrunedRoots(loaderstate *State, ctx context.Context, mainModule module. // // (See https://golang.org/design/36460-lazy-module-loading#invariants for more // detail.) -func updatePrunedRoots(loaderstate *State, ctx context.Context, direct map[string]bool, rs *Requirements, pkgs []*loadPkg, add []module.Version, rootsImported bool) (*Requirements, error) { +func updatePrunedRoots(ld *Loader, ctx context.Context, direct map[string]bool, rs *Requirements, pkgs []*loadPkg, add []module.Version, rootsImported bool) (*Requirements, error) { roots := rs.rootModules rootsUpgraded := false @@ -1009,7 +1019,7 @@ func updatePrunedRoots(loaderstate *State, ctx context.Context, direct map[strin // either pkgInAll or pkgIsRoot is included as a root.” needSort := false for _, pkg := range pkgs { - if !pkg.fromExternalModule(loaderstate) { + if !pkg.fromExternalModule(ld) { // pkg was not loaded from a module dependency, so we don't need // to do anything special to maintain that dependency. continue @@ -1058,7 +1068,7 @@ func updatePrunedRoots(loaderstate *State, ctx context.Context, direct map[strin continue } - if _, ok := rs.rootSelected(loaderstate, pkg.mod.Path); ok { + if _, ok := rs.rootSelected(ld, pkg.mod.Path); ok { // It is possible that the main module's go.mod file is incomplete or // otherwise erroneous — for example, perhaps the author forgot to 'git // add' their updated go.mod file after adding a new package import, or @@ -1094,7 +1104,7 @@ func updatePrunedRoots(loaderstate *State, ctx context.Context, direct map[strin } for _, m := range add { - if v, ok := rs.rootSelected(loaderstate, m.Path); !ok || gover.ModCompare(m.Path, v, m.Version) < 0 { + if v, ok := rs.rootSelected(ld, m.Path); !ok || gover.ModCompare(m.Path, v, m.Version) < 0 { roots = append(roots, m) rootsUpgraded = true needSort = true @@ -1111,7 +1121,7 @@ func updatePrunedRoots(loaderstate *State, ctx context.Context, direct map[strin // We've added or upgraded one or more roots, so load the full module // graph so that we can update those roots to be consistent with other // requirements. - if mustHaveCompleteRequirements(loaderstate) { + if mustHaveCompleteRequirements(ld) { // Our changes to the roots may have moved dependencies into or out of // the graph-pruning horizon, which could in turn change the selected // versions of other modules. (For pruned modules adding or removing an @@ -1119,9 +1129,9 @@ func updatePrunedRoots(loaderstate *State, ctx context.Context, direct map[strin return rs, errGoModDirty } - rs = newRequirements(loaderstate, pruned, roots, direct) + rs = newRequirements(ld, pruned, roots, direct) var err error - mg, err = rs.Graph(loaderstate, ctx) + mg, err = rs.Graph(ld, ctx) if err != nil { return rs, err } @@ -1135,20 +1145,20 @@ func updatePrunedRoots(loaderstate *State, ctx context.Context, direct map[strin // We've already loaded the full module graph, which includes the // requirements of all of the root modules — even the transitive // requirements, if they are unpruned! - mg, _ = rs.Graph(loaderstate, ctx) + mg, _ = rs.Graph(ld, ctx) } else if cfg.BuildMod == "vendor" { // We can't spot-check the requirements of other modules because we // don't in general have their go.mod files available in the vendor // directory. (Fortunately this case is impossible, because mg.graph is // always non-nil in vendor mode!) panic("internal error: rs.graph is unexpectedly nil with -mod=vendor") - } else if !spotCheckRoots(loaderstate, ctx, rs, spotCheckRoot) { + } else if !spotCheckRoots(ld, ctx, rs, spotCheckRoot) { // We spot-checked the explicit requirements of the roots that are // relevant to the packages we've loaded. Unfortunately, they're // inconsistent in some way; we need to load the full module graph // so that we can fix the roots properly. var err error - mg, err = rs.Graph(loaderstate, ctx) + mg, err = rs.Graph(ld, ctx) if err != nil { return rs, err } @@ -1158,7 +1168,7 @@ func updatePrunedRoots(loaderstate *State, ctx context.Context, direct map[strin roots = make([]module.Version, 0, len(rs.rootModules)) rootsUpgraded = false inRootPaths := make(map[string]bool, len(rs.rootModules)+1) - for _, mm := range loaderstate.MainModules.Versions() { + for _, mm := range ld.MainModules.Versions() { inRootPaths[mm.Path] = true } for _, m := range rs.rootModules { @@ -1184,7 +1194,7 @@ func updatePrunedRoots(loaderstate *State, ctx context.Context, direct map[strin var v string if mg == nil { - v, _ = rs.rootSelected(loaderstate, m.Path) + v, _ = rs.rootSelected(ld, m.Path) } else { v = mg.Selected(m.Path) } @@ -1218,12 +1228,12 @@ func updatePrunedRoots(loaderstate *State, ctx context.Context, direct map[strin // preserve its cached ModuleGraph (if any). return rs, nil } - return newRequirements(loaderstate, pruned, roots, direct), nil + return newRequirements(ld, pruned, roots, direct), nil } // spotCheckRoots reports whether the versions of the roots in rs satisfy the // explicit requirements of the modules in mods. -func spotCheckRoots(loaderstate *State, ctx context.Context, rs *Requirements, mods map[module.Version]bool) bool { +func spotCheckRoots(ld *Loader, ctx context.Context, rs *Requirements, mods map[module.Version]bool) bool { ctx, cancel := context.WithCancel(ctx) defer cancel() @@ -1235,14 +1245,14 @@ func spotCheckRoots(loaderstate *State, ctx context.Context, rs *Requirements, m return } - summary, err := goModSummary(loaderstate, m) + summary, err := goModSummary(ld, m) if err != nil { cancel() return } for _, r := range summary.require { - if v, ok := rs.rootSelected(loaderstate, r.Path); ok && gover.ModCompare(r.Path, v, r.Version) < 0 { + if v, ok := rs.rootSelected(ld, r.Path); ok && gover.ModCompare(r.Path, v, r.Version) < 0 { cancel() return } @@ -1264,7 +1274,7 @@ func spotCheckRoots(loaderstate *State, ctx context.Context, rs *Requirements, m // the selected version of every module that provided or lexically could have // provided a package in pkgs, and includes the selected version of every such // module in direct as a root. -func tidyUnprunedRoots(loaderstate *State, ctx context.Context, mainModule module.Version, old *Requirements, pkgs []*loadPkg) (*Requirements, error) { +func tidyUnprunedRoots(ld *Loader, ctx context.Context, mainModule module.Version, old *Requirements, pkgs []*loadPkg) (*Requirements, error) { var ( // keep is a set of modules that provide packages or are needed to // disambiguate imports. @@ -1292,16 +1302,16 @@ func tidyUnprunedRoots(loaderstate *State, ctx context.Context, mainModule modul // without its sum. See #47738. altMods = map[string]string{} ) - if v, ok := old.rootSelected(loaderstate, "go"); ok { + if v, ok := old.rootSelected(ld, "go"); ok { keep = append(keep, module.Version{Path: "go", Version: v}) keptPath["go"] = true } - if v, ok := old.rootSelected(loaderstate, "toolchain"); ok { + if v, ok := old.rootSelected(ld, "toolchain"); ok { keep = append(keep, module.Version{Path: "toolchain", Version: v}) keptPath["toolchain"] = true } for _, pkg := range pkgs { - if !pkg.fromExternalModule(loaderstate) { + if !pkg.fromExternalModule(ld) { continue } if m := pkg.mod; !keptPath[m.Path] { @@ -1319,7 +1329,7 @@ func tidyUnprunedRoots(loaderstate *State, ctx context.Context, mainModule modul // Construct a build list with a minimal set of roots. // This may remove or downgrade modules in altMods. - reqs := &mvsReqs{loaderstate: loaderstate, roots: keep} + reqs := &mvsReqs{ld: ld, roots: keep} min, err := mvs.Req(mainModule, rootPaths, reqs) if err != nil { return nil, err @@ -1350,7 +1360,7 @@ func tidyUnprunedRoots(loaderstate *State, ctx context.Context, mainModule modul } } - return newRequirements(loaderstate, unpruned, min, old.direct), nil + return newRequirements(ld, unpruned, min, old.direct), nil } // updateUnprunedRoots returns a set of root requirements that includes the selected @@ -1367,8 +1377,8 @@ func tidyUnprunedRoots(loaderstate *State, ctx context.Context, mainModule modul // by a dependency in add. // 4. Every version in add is selected at its given version unless upgraded by // (the dependencies of) an existing root or another module in add. -func updateUnprunedRoots(loaderstate *State, ctx context.Context, direct map[string]bool, rs *Requirements, add []module.Version) (*Requirements, error) { - mg, err := rs.Graph(loaderstate, ctx) +func updateUnprunedRoots(ld *Loader, ctx context.Context, direct map[string]bool, rs *Requirements, add []module.Version) (*Requirements, error) { + mg, err := rs.Graph(ld, ctx) if err != nil { // We can't ignore errors in the module graph even if the user passed the -e // flag to try to push past them. If we can't load the complete module @@ -1376,7 +1386,7 @@ func updateUnprunedRoots(loaderstate *State, ctx context.Context, direct map[str return rs, err } - if mustHaveCompleteRequirements(loaderstate) { + if mustHaveCompleteRequirements(ld) { // Instead of actually updating the requirements, just check that no updates // are needed. if rs == nil { @@ -1396,7 +1406,7 @@ func updateUnprunedRoots(loaderstate *State, ctx context.Context, direct map[str } } for mPath := range direct { - if _, ok := rs.rootSelected(loaderstate, mPath); !ok { + if _, ok := rs.rootSelected(ld, mPath); !ok { // Module m is supposed to be listed explicitly, but isn't. // // Note that this condition is also detected (and logged with more @@ -1435,7 +1445,7 @@ func updateUnprunedRoots(loaderstate *State, ctx context.Context, direct map[str // This is only for convenience and clarity for end users: in an unpruned module, // the choice of explicit vs. implicit dependency has no impact on MVS // selection (for itself or any other module). - keep := append(mg.BuildList()[loaderstate.MainModules.Len():], add...) + keep := append(mg.BuildList()[ld.MainModules.Len():], add...) for _, m := range keep { if direct[m.Path] && !inRootPaths[m.Path] { rootPaths = append(rootPaths, m.Path) @@ -1444,14 +1454,14 @@ func updateUnprunedRoots(loaderstate *State, ctx context.Context, direct map[str } var roots []module.Version - for _, mainModule := range loaderstate.MainModules.Versions() { - min, err := mvs.Req(mainModule, rootPaths, &mvsReqs{loaderstate: loaderstate, roots: keep}) + for _, mainModule := range ld.MainModules.Versions() { + min, err := mvs.Req(mainModule, rootPaths, &mvsReqs{ld: ld, roots: keep}) if err != nil { return rs, err } roots = append(roots, min...) } - if loaderstate.MainModules.Len() > 1 { + if ld.MainModules.Len() > 1 { gover.ModSort(roots) } if rs.pruning == unpruned && slices.Equal(roots, rs.rootModules) && maps.Equal(direct, rs.direct) { @@ -1460,12 +1470,12 @@ func updateUnprunedRoots(loaderstate *State, ctx context.Context, direct map[str return rs, nil } - return newRequirements(loaderstate, unpruned, roots, direct), nil + return newRequirements(ld, unpruned, roots, direct), nil } // convertPruning returns a version of rs with the given pruning behavior. // If rs already has the given pruning, convertPruning returns rs unmodified. -func convertPruning(loaderstate *State, ctx context.Context, rs *Requirements, pruning modPruning) (*Requirements, error) { +func convertPruning(ld *Loader, ctx context.Context, rs *Requirements, pruning modPruning) (*Requirements, error) { if rs.pruning == pruning { return rs, nil } else if rs.pruning == workspace || pruning == workspace { @@ -1477,7 +1487,7 @@ func convertPruning(loaderstate *State, ctx context.Context, rs *Requirements, p // pruned module graph are a superset of the roots of an unpruned one, so // we don't need to add any new roots — we just need to drop the ones that // are redundant, which is exactly what updateUnprunedRoots does. - return updateUnprunedRoots(loaderstate, ctx, rs.direct, rs, nil) + return updateUnprunedRoots(ld, ctx, rs.direct, rs, nil) } // We are converting an unpruned module to a pruned one. @@ -1487,9 +1497,9 @@ func convertPruning(loaderstate *State, ctx context.Context, rs *Requirements, p // root set! “Include the transitive dependencies of every module in the build // list” is exactly what happens in a pruned module if we promote every module // in the build list to a root. - mg, err := rs.Graph(loaderstate, ctx) + mg, err := rs.Graph(ld, ctx) if err != nil { return rs, err } - return newRequirements(loaderstate, pruned, mg.BuildList()[loaderstate.MainModules.Len():], rs.direct), nil + return newRequirements(ld, pruned, mg.BuildList()[ld.MainModules.Len():], rs.direct), nil } diff --git a/src/cmd/go/internal/modload/edit.go b/src/cmd/go/internal/modload/edit.go index 1996b7c26b0dc6..a631afc0944f6c 100644 --- a/src/cmd/go/internal/modload/edit.go +++ b/src/cmd/go/internal/modload/edit.go @@ -5,10 +5,6 @@ package modload import ( - "cmd/go/internal/cfg" - "cmd/go/internal/gover" - "cmd/go/internal/mvs" - "cmd/internal/par" "context" "errors" "fmt" @@ -16,6 +12,11 @@ import ( "os" "slices" + "cmd/go/internal/cfg" + "cmd/go/internal/gover" + "cmd/go/internal/mvs" + "cmd/internal/par" + "golang.org/x/mod/module" ) @@ -42,7 +43,7 @@ import ( // If pruning is enabled, the roots of the edited requirements include an // explicit entry for each module path in tryUpgrade, mustSelect, and the roots // of rs, unless the selected version for the module path is "none". -func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, tryUpgrade, mustSelect []module.Version) (edited *Requirements, changed bool, err error) { +func editRequirements(ld *Loader, ctx context.Context, rs *Requirements, tryUpgrade, mustSelect []module.Version) (edited *Requirements, changed bool, err error) { if rs.pruning == workspace { panic("editRequirements cannot edit workspace requirements") } @@ -82,7 +83,7 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, } if rootPruning != rs.pruning { - rs, err = convertPruning(loaderstate, ctx, rs, rootPruning) + rs, err = convertPruning(ld, ctx, rs, rootPruning) if err != nil { return orig, false, err } @@ -100,13 +101,13 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, // dependencies, so we need to treat everything in the build list as // potentially relevant — that is, as what would be a “root” in a module // with graph pruning enabled. - mg, err := rs.Graph(loaderstate, ctx) + mg, err := rs.Graph(ld, ctx) if err != nil { // If we couldn't load the graph, we don't know what its requirements were // to begin with, so we can't edit those requirements in a coherent way. return orig, false, err } - bl := mg.BuildList()[loaderstate.MainModules.Len():] + bl := mg.BuildList()[ld.MainModules.Len():] selectedRoot = make(map[string]string, len(bl)) for _, m := range bl { selectedRoot[m.Path] = m.Version @@ -224,7 +225,7 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, // of every root. The upgraded roots are in addition to the original // roots, so we will have enough information to trace a path to each // conflict we discover from one or more of the original roots. - mg, upgradedRoots, err := extendGraph(loaderstate, ctx, rootPruning, roots, selectedRoot) + mg, upgradedRoots, err := extendGraph(ld, ctx, rootPruning, roots, selectedRoot) if err != nil { if mg == nil { return orig, false, err @@ -391,7 +392,7 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, // the edit. We want to make sure we consider keeping it as-is, // even if it wouldn't normally be included. (For example, it might // be a pseudo-version or pre-release.) - origMG, _ := orig.Graph(loaderstate, ctx) + origMG, _ := orig.Graph(ld, ctx) origV := origMG.Selected(m.Path) if conflict.Err != nil && origV == m.Version { @@ -415,7 +416,7 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, rejectedRoot[m] = true prev := m for { - prev, err = previousVersion(loaderstate, ctx, prev) + prev, err = previousVersion(ld, ctx, prev) if gover.ModCompare(m.Path, m.Version, origV) > 0 && (gover.ModCompare(m.Path, prev.Version, origV) < 0 || err != nil) { // previousVersion skipped over origV. Insert it into the order. prev.Version = origV @@ -515,13 +516,13 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, // The modules in mustSelect are always promoted to be explicit. for _, m := range mustSelect { - if m.Version != "none" && !loaderstate.MainModules.Contains(m.Path) { + if m.Version != "none" && !ld.MainModules.Contains(m.Path) { rootPaths = append(rootPaths, m.Path) } } for _, m := range roots { - if v, ok := rs.rootSelected(loaderstate, m.Path); ok && (v == m.Version || rs.direct[m.Path]) { + if v, ok := rs.rootSelected(ld, m.Path); ok && (v == m.Version || rs.direct[m.Path]) { // m.Path was formerly a root, and either its version hasn't changed or // we believe that it provides a package directly imported by a package // or test in the main module. For now we'll assume that it is still @@ -532,7 +533,7 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, } } - roots, err = mvs.Req(loaderstate.MainModules.mustGetSingleMainModule(loaderstate), rootPaths, &mvsReqs{loaderstate: loaderstate, roots: roots}) + roots, err = mvs.Req(ld.MainModules.mustGetSingleMainModule(ld), rootPaths, &mvsReqs{ld: ld, roots: roots}) if err != nil { return nil, false, err } @@ -563,7 +564,7 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, direct[m.Path] = true } } - edited = newRequirements(loaderstate, rootPruning, roots, direct) + edited = newRequirements(ld, rootPruning, roots, direct) // If we ended up adding a dependency that upgrades our go version far enough // to activate pruning, we must convert the edited Requirements in order to @@ -578,7 +579,7 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, // those two modules will never be downgraded due to a conflict with any other // constraint. if rootPruning == unpruned { - if v, ok := edited.rootSelected(loaderstate, "go"); ok && pruningForGoVersion(v) == pruned { + if v, ok := edited.rootSelected(ld, "go"); ok && pruningForGoVersion(v) == pruned { // Since we computed the edit with the unpruned graph, and the pruned // graph is a strict subset of the unpruned graph, this conversion // preserves the exact (edited) build list that we already computed. @@ -587,7 +588,7 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, // the graph. 'go get' will check for that sort of transition and log a // message reminding the user how to clean up this mess we're about to // make. 😅 - edited, err = convertPruning(loaderstate, ctx, edited, pruned) + edited, err = convertPruning(ld, ctx, edited, pruned) if err != nil { return orig, false, err } @@ -607,9 +608,9 @@ func editRequirements(loaderstate *State, ctx context.Context, rs *Requirements, // The extended graph is useful for diagnosing version conflicts: for each // selected module version, it can provide a complete path of requirements from // some root to that version. -func extendGraph(loaderstate *State, ctx context.Context, rootPruning modPruning, roots []module.Version, selectedRoot map[string]string) (mg *ModuleGraph, upgradedRoot map[module.Version]bool, err error) { +func extendGraph(ld *Loader, ctx context.Context, rootPruning modPruning, roots []module.Version, selectedRoot map[string]string) (mg *ModuleGraph, upgradedRoot map[module.Version]bool, err error) { for { - mg, err = readModGraph(loaderstate, ctx, rootPruning, roots, upgradedRoot) + mg, err = readModGraph(ld, ctx, rootPruning, roots, upgradedRoot) // We keep on going even if err is non-nil until we reach a steady state. // (Note that readModGraph returns a non-nil *ModuleGraph even in case of // errors.) The caller may be able to fix the errors by adjusting versions, diff --git a/src/cmd/go/internal/modload/help.go b/src/cmd/go/internal/modload/help.go index 886ad62bd90cb6..d43a639e2aed99 100644 --- a/src/cmd/go/internal/modload/help.go +++ b/src/cmd/go/internal/modload/help.go @@ -17,9 +17,9 @@ distributed together. Modules may be downloaded directly from version control repositories or from module proxy servers. For a series of tutorials on modules, see -https://golang.org/doc/tutorial/create-module. +https://go.dev/doc/tutorial/create-module. -For a detailed reference on modules, see https://golang.org/ref/mod. +For a detailed reference on modules, see https://go.dev/ref/mod. By default, the go command may download modules from https://proxy.golang.org. It may authenticate modules using the checksum database at @@ -30,7 +30,7 @@ respectively. The go command's download behavior may be configured using GOPROXY, GOSUMDB, GOPRIVATE, and other environment variables. See 'go help environment' -and https://golang.org/ref/mod#private-module-privacy for more information. +and https://go.dev/ref/mod#private-module-privacy for more information. `, } @@ -44,21 +44,21 @@ directory and then successive parent directories to find the go.mod marking the root of the main (current) module. The go.mod file format is described in detail at -https://golang.org/ref/mod#go-mod-file. +https://go.dev/ref/mod#go-mod-file. To create a new go.mod file, use 'go mod init'. For details see -'go help mod init' or https://golang.org/ref/mod#go-mod-init. +'go help mod init' or https://go.dev/ref/mod#go-mod-init. To add missing module requirements or remove unneeded requirements, use 'go mod tidy'. For details, see 'go help mod tidy' or -https://golang.org/ref/mod#go-mod-tidy. +https://go.dev/ref/mod#go-mod-tidy. To add, upgrade, downgrade, or remove a specific module requirement, use 'go get'. For details, see 'go help module-get' or -https://golang.org/ref/mod#go-get. +https://go.dev/ref/mod#go-get. To make other changes or to parse go.mod as JSON for use by other tools, use 'go mod edit'. See 'go help mod edit' or -https://golang.org/ref/mod#go-mod-edit. +https://go.dev/ref/mod#go-mod-edit. `, } diff --git a/src/cmd/go/internal/modload/import.go b/src/cmd/go/internal/modload/import.go index c6b56c35d4b129..98f17ccff15b33 100644 --- a/src/cmd/go/internal/modload/import.go +++ b/src/cmd/go/internal/modload/import.go @@ -29,10 +29,11 @@ import ( ) type ImportMissingError struct { - Path string - Module module.Version - QueryErr error - modContainingCWD module.Version + Path string + Module module.Version + QueryErr error + modContainingCWD module.Version + allowMissingModuleImports bool // modRoot is dependent on the value of ImportingMainModule and should be // kept in sync. @@ -70,7 +71,7 @@ func (e *ImportMissingError) Error() string { if e.QueryErr != nil && !errors.Is(e.QueryErr, ErrNoModRoot) { return fmt.Sprintf("cannot find module providing package %s: %v", e.Path, e.QueryErr) } - if cfg.BuildMod == "mod" || (cfg.BuildMod == "readonly" && allowMissingModuleImports) { + if cfg.BuildMod == "mod" || (cfg.BuildMod == "readonly" && e.allowMissingModuleImports) { return "cannot find module providing package " + e.Path } @@ -266,8 +267,8 @@ func (e *invalidImportError) Unwrap() error { // (https://go.dev/issue/56222) for modules with 'go' versions between 1.17 and // 1.20, preventing unnecessary go.sum churn and network access in those // modules. -func importFromModules(loaderstate *State, ctx context.Context, path string, rs *Requirements, mg *ModuleGraph, skipModFile bool) (m module.Version, modroot, dir string, altMods []module.Version, err error) { - invalidf := func(format string, args ...interface{}) (module.Version, string, string, []module.Version, error) { +func importFromModules(ld *Loader, ctx context.Context, path string, rs *Requirements, mg *ModuleGraph, skipModFile bool) (m module.Version, modroot, dir string, altMods []module.Version, err error) { + invalidf := func(format string, args ...any) (module.Version, string, string, []module.Version, error) { return module.Version{}, "", "", nil, &invalidImportError{ importPath: path, err: fmt.Errorf(format, args...), @@ -303,12 +304,12 @@ func importFromModules(loaderstate *State, ctx context.Context, path string, rs // Is the package in the standard library? pathIsStd := search.IsStandardImportPath(path) if pathIsStd && modindex.IsStandardPackage(cfg.GOROOT, cfg.BuildContext.Compiler, path) { - for _, mainModule := range loaderstate.MainModules.Versions() { - if loaderstate.MainModules.InGorootSrc(mainModule) { - if dir, ok, err := dirInModule(path, loaderstate.MainModules.PathPrefix(mainModule), loaderstate.MainModules.ModRoot(mainModule), true); err != nil { - return module.Version{}, loaderstate.MainModules.ModRoot(mainModule), dir, nil, err + for _, mainModule := range ld.MainModules.Versions() { + if ld.MainModules.InGorootSrc(mainModule) { + if dir, ok, err := dirInModule(path, ld.MainModules.PathPrefix(mainModule), ld.MainModules.ModRoot(mainModule), true); err != nil { + return module.Version{}, ld.MainModules.ModRoot(mainModule), dir, nil, err } else if ok { - return mainModule, loaderstate.MainModules.ModRoot(mainModule), dir, nil, nil + return mainModule, ld.MainModules.ModRoot(mainModule), dir, nil, nil } } } @@ -325,10 +326,10 @@ func importFromModules(loaderstate *State, ctx context.Context, path string, rs // Everything must be in the main modules or the main module's or workspace's vendor directory. if cfg.BuildMod == "vendor" { var mainErr error - for _, mainModule := range loaderstate.MainModules.Versions() { - modRoot := loaderstate.MainModules.ModRoot(mainModule) + for _, mainModule := range ld.MainModules.Versions() { + modRoot := ld.MainModules.ModRoot(mainModule) if modRoot != "" { - dir, mainOK, err := dirInModule(path, loaderstate.MainModules.PathPrefix(mainModule), modRoot, true) + dir, mainOK, err := dirInModule(path, ld.MainModules.PathPrefix(mainModule), modRoot, true) if mainErr == nil { mainErr = err } @@ -340,8 +341,8 @@ func importFromModules(loaderstate *State, ctx context.Context, path string, rs } } - if HasModRoot(loaderstate) { - vendorDir := VendorDir(loaderstate) + if ld.HasModRoot() { + vendorDir := VendorDir(ld) dir, inVendorDir, _ := dirInModule(path, "", vendorDir, false) if inVendorDir { readVendorList(vendorDir) @@ -349,13 +350,13 @@ func importFromModules(loaderstate *State, ctx context.Context, path string, rs // vendor/modules.txt does not exist or the user manually added directories to the vendor directory. // Go 1.23 and later require vendored packages to be present in modules.txt to be imported. _, ok := vendorPkgModule[path] - if ok || (gover.Compare(loaderstate.MainModules.GoVersion(loaderstate), gover.ExplicitModulesTxtImportVersion) < 0) { + if ok || (gover.Compare(ld.MainModules.GoVersion(ld), gover.ExplicitModulesTxtImportVersion) < 0) { mods = append(mods, vendorPkgModule[path]) dirs = append(dirs, dir) roots = append(roots, vendorDir) } else { subCommand := "mod" - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { subCommand = "work" } fmt.Fprintf(os.Stderr, "go: ignoring package %s which exists in the vendor directory but is missing from vendor/modules.txt. To sync the vendor directory run go %s vendor.\n", path, subCommand) @@ -373,8 +374,9 @@ func importFromModules(loaderstate *State, ctx context.Context, path string, rs if len(mods) == 0 { return module.Version{}, "", "", nil, &ImportMissingError{ - Path: path, - modContainingCWD: loaderstate.MainModules.ModContainingCWD(), + Path: path, + modContainingCWD: ld.MainModules.ModContainingCWD(), + allowMissingModuleImports: ld.allowMissingModuleImports, } } @@ -406,7 +408,7 @@ func importFromModules(loaderstate *State, ctx context.Context, path string, rs ok bool ) if mg == nil { - v, ok = rs.rootSelected(loaderstate, prefix) + v, ok = rs.rootSelected(ld, prefix) } else { v, ok = mg.Selected(prefix), true } @@ -415,7 +417,7 @@ func importFromModules(loaderstate *State, ctx context.Context, path string, rs } m := module.Version{Path: prefix, Version: v} - root, isLocal, err := fetch(loaderstate, ctx, m) + root, isLocal, err := fetch(ld, ctx, m) if err != nil { if _, ok := errors.AsType[*sumMissingError](err); ok { // We are missing a sum needed to fetch a module in the build list. @@ -478,8 +480,8 @@ func importFromModules(loaderstate *State, ctx context.Context, path string, rs // If the module graph is pruned and this is a test-only dependency // of a package in "all", we didn't necessarily load that file // when we read the module graph, so do it now to be sure. - if !skipModFile && cfg.BuildMod != "vendor" && mods[0].Path != "" && !loaderstate.MainModules.Contains(mods[0].Path) { - if _, err := goModSummary(loaderstate, mods[0]); err != nil { + if !skipModFile && cfg.BuildMod != "vendor" && mods[0].Path != "" && !ld.MainModules.Contains(mods[0].Path) { + if _, err := goModSummary(ld, mods[0]); err != nil { return module.Version{}, "", "", nil, err } } @@ -490,20 +492,21 @@ func importFromModules(loaderstate *State, ctx context.Context, path string, rs // We checked the full module graph and still didn't find the // requested package. var queryErr error - if !HasModRoot(loaderstate) { - queryErr = NewNoMainModulesError(loaderstate) + if !ld.HasModRoot() { + queryErr = NewNoMainModulesError(ld) } return module.Version{}, "", "", nil, &ImportMissingError{ - Path: path, - QueryErr: queryErr, - isStd: pathIsStd, - modContainingCWD: loaderstate.MainModules.ModContainingCWD(), + Path: path, + QueryErr: queryErr, + isStd: pathIsStd, + modContainingCWD: ld.MainModules.ModContainingCWD(), + allowMissingModuleImports: ld.allowMissingModuleImports, } } // So far we've checked the root dependencies. // Load the full module graph and try again. - mg, err = rs.Graph(loaderstate, ctx) + mg, err = rs.Graph(ld, ctx) if err != nil { // We might be missing one or more transitive (implicit) dependencies from // the module graph, so we can't return an ImportMissingError here — one @@ -519,12 +522,12 @@ func importFromModules(loaderstate *State, ctx context.Context, path string, rs // // Unlike QueryPattern, queryImport prefers to add a replaced version of a // module *before* checking the proxies for a version to add. -func queryImport(loaderstate *State, ctx context.Context, path string, rs *Requirements) (module.Version, error) { +func queryImport(ld *Loader, ctx context.Context, path string, rs *Requirements) (module.Version, error) { // To avoid spurious remote fetches, try the latest replacement for each // module (golang.org/issue/26241). var mods []module.Version - if loaderstate.MainModules != nil { // TODO(#48912): Ensure MainModules exists at this point, and remove the check. - for mp, mv := range loaderstate.MainModules.HighestReplaced() { + if ld.MainModules != nil { // TODO(#48912): Ensure MainModules exists at this point, and remove the check. + for mp, mv := range ld.MainModules.HighestReplaced() { if !maybeInModule(path, mp) { continue } @@ -540,7 +543,7 @@ func queryImport(loaderstate *State, ctx context.Context, path string, rs *Requi mv = module.ZeroPseudoVersion("v0") } } - mg, err := rs.Graph(loaderstate, ctx) + mg, err := rs.Graph(ld, ctx) if err != nil { return module.Version{}, err } @@ -559,7 +562,7 @@ func queryImport(loaderstate *State, ctx context.Context, path string, rs *Requi return len(mods[i].Path) > len(mods[j].Path) }) for _, m := range mods { - root, isLocal, err := fetch(loaderstate, ctx, m) + root, isLocal, err := fetch(ld, ctx, m) if err != nil { if _, ok := errors.AsType[*sumMissingError](err); ok { return module.Version{}, &ImportMissingSumError{importPath: path} @@ -571,9 +574,10 @@ func queryImport(loaderstate *State, ctx context.Context, path string, rs *Requi } else if ok { if cfg.BuildMod == "readonly" { return module.Version{}, &ImportMissingError{ - Path: path, - replaced: m, - modContainingCWD: loaderstate.MainModules.ModContainingCWD(), + Path: path, + replaced: m, + modContainingCWD: ld.MainModules.ModContainingCWD(), + allowMissingModuleImports: ld.allowMissingModuleImports, } } return m, nil @@ -583,7 +587,7 @@ func queryImport(loaderstate *State, ctx context.Context, path string, rs *Requi // The package path is not valid to fetch remotely, // so it can only exist in a replaced module, // and we know from the above loop that it is not. - replacement := Replacement(loaderstate, mods[0]) + replacement := Replacement(ld, mods[0]) return module.Version{}, &PackageNotInModuleError{ Mod: mods[0], Query: "latest", @@ -601,13 +605,14 @@ func queryImport(loaderstate *State, ctx context.Context, path string, rs *Requi // // Instead of trying QueryPattern, report an ImportMissingError immediately. return module.Version{}, &ImportMissingError{ - Path: path, - isStd: true, - modContainingCWD: loaderstate.MainModules.ModContainingCWD(), + Path: path, + isStd: true, + modContainingCWD: ld.MainModules.ModContainingCWD(), + allowMissingModuleImports: ld.allowMissingModuleImports, } } - if (cfg.BuildMod == "readonly" || cfg.BuildMod == "vendor") && !allowMissingModuleImports { + if (cfg.BuildMod == "readonly" || cfg.BuildMod == "vendor") && !ld.allowMissingModuleImports { // In readonly mode, we can't write go.mod, so we shouldn't try to look up // the module. If readonly mode was enabled explicitly, include that in // the error message. @@ -620,9 +625,10 @@ func queryImport(loaderstate *State, ctx context.Context, path string, rs *Requi queryErr = fmt.Errorf("import lookup disabled by -mod=%s\n\t(%s)", cfg.BuildMod, cfg.BuildModReason) } return module.Version{}, &ImportMissingError{ - Path: path, - QueryErr: queryErr, - modContainingCWD: loaderstate.MainModules.ModContainingCWD(), + Path: path, + QueryErr: queryErr, + modContainingCWD: ld.MainModules.ModContainingCWD(), + allowMissingModuleImports: ld.allowMissingModuleImports, } } @@ -631,20 +637,21 @@ func queryImport(loaderstate *State, ctx context.Context, path string, rs *Requi // and return m, dir, ImportMissingError. fmt.Fprintf(os.Stderr, "go: finding module for package %s\n", path) - mg, err := rs.Graph(loaderstate, ctx) + mg, err := rs.Graph(ld, ctx) if err != nil { return module.Version{}, err } - candidates, err := QueryPackages(loaderstate, ctx, path, "latest", mg.Selected, loaderstate.CheckAllowed) + candidates, err := QueryPackages(ld, ctx, path, "latest", mg.Selected, ld.CheckAllowed) if err != nil { if errors.Is(err, fs.ErrNotExist) { // Return "cannot find module providing package […]" instead of whatever // low-level error QueryPattern produced. return module.Version{}, &ImportMissingError{ - Path: path, - QueryErr: err, - modContainingCWD: loaderstate.MainModules.ModContainingCWD(), + Path: path, + QueryErr: err, + modContainingCWD: ld.MainModules.ModContainingCWD(), + allowMissingModuleImports: ld.allowMissingModuleImports, } } else { return module.Version{}, err @@ -670,10 +677,11 @@ func queryImport(loaderstate *State, ctx context.Context, path string, rs *Requi return c.Mod, nil } return module.Version{}, &ImportMissingError{ - Path: path, - Module: candidates[0].Mod, - newMissingVersion: candidate0MissingVersion, - modContainingCWD: loaderstate.MainModules.ModContainingCWD(), + Path: path, + Module: candidates[0].Mod, + newMissingVersion: candidate0MissingVersion, + modContainingCWD: ld.MainModules.ModContainingCWD(), + allowMissingModuleImports: ld.allowMissingModuleImports, } } @@ -776,15 +784,15 @@ func dirInModule(path, mpath, mdir string, isLocal bool) (dir string, haveGoFile // // The isLocal return value reports whether the replacement, // if any, is local to the filesystem. -func fetch(loaderstate *State, ctx context.Context, mod module.Version) (dir string, isLocal bool, err error) { - if modRoot := loaderstate.MainModules.ModRoot(mod); modRoot != "" { +func fetch(ld *Loader, ctx context.Context, mod module.Version) (dir string, isLocal bool, err error) { + if modRoot := ld.MainModules.ModRoot(mod); modRoot != "" { return modRoot, true, nil } - if r := Replacement(loaderstate, mod); r.Path != "" { + if r := Replacement(ld, mod); r.Path != "" { if r.Version == "" { dir = r.Path if !filepath.IsAbs(dir) { - dir = filepath.Join(replaceRelativeTo(loaderstate), dir) + dir = filepath.Join(replaceRelativeTo(ld), dir) } // Ensure that the replacement directory actually exists: // dirInModule does not report errors for missing modules, @@ -809,18 +817,18 @@ func fetch(loaderstate *State, ctx context.Context, mod module.Version) (dir str mod = r } - if mustHaveSums(loaderstate) && !modfetch.HaveSum(mod) { + if mustHaveSums(ld) && !modfetch.HaveSum(ld.Fetcher(), mod) { return "", false, module.VersionError(mod, &sumMissingError{}) } - dir, err = modfetch.Download(ctx, mod) + dir, err = ld.Fetcher().Download(ctx, mod) return dir, false, err } // mustHaveSums reports whether we require that all checksums // needed to load or build packages are already present in the go.sum file. -func mustHaveSums(loaderstate *State) bool { - return HasModRoot(loaderstate) && cfg.BuildMod == "readonly" && !inWorkspaceMode(loaderstate) +func mustHaveSums(ld *Loader) bool { + return ld.HasModRoot() && cfg.BuildMod == "readonly" && !ld.inWorkspaceMode() } type sumMissingError struct { diff --git a/src/cmd/go/internal/modload/import_test.go b/src/cmd/go/internal/modload/import_test.go index a5c4b837a0be12..5dd9890de0a114 100644 --- a/src/cmd/go/internal/modload/import_test.go +++ b/src/cmd/go/internal/modload/import_test.go @@ -56,25 +56,20 @@ var importTests = []struct { } func TestQueryImport(t *testing.T) { + ld := NewLoader() + ld.RootMode = NoRoot + ld.AllowMissingModuleImports() + testenv.MustHaveExternalNetwork(t) testenv.MustHaveExecPath(t, "git") - oldAllowMissingModuleImports := allowMissingModuleImports - oldRootMode := LoaderState.RootMode - defer func() { - allowMissingModuleImports = oldAllowMissingModuleImports - LoaderState.RootMode = oldRootMode - }() - allowMissingModuleImports = true - LoaderState.RootMode = NoRoot - ctx := context.Background() - rs := LoadModFile(LoaderState, ctx) + rs := LoadModFile(ld, ctx) for _, tt := range importTests { t.Run(strings.ReplaceAll(tt.path, "/", "_"), func(t *testing.T) { // Note that there is no build list, so Import should always fail. - m, err := queryImport(LoaderState, ctx, tt.path, rs) + m, err := queryImport(ld, ctx, tt.path, rs) if tt.err == "" { if err != nil { diff --git a/src/cmd/go/internal/modload/init.go b/src/cmd/go/internal/modload/init.go index e2116b728933cf..6e3f9251be9b1e 100644 --- a/src/cmd/go/internal/modload/init.go +++ b/src/cmd/go/internal/modload/init.go @@ -2,6 +2,7 @@ // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. +// Package modload provides module and package loading functionality. package modload import ( @@ -38,8 +39,6 @@ import ( // // TODO(#40775): See if these can be plumbed as explicit parameters. var ( - allowMissingModuleImports bool - // ExplicitWriteGoMod prevents LoadPackages, ListModules, and other functions // from updating go.mod and go.sum or reporting errors when updates are // needed. A package should set this if it would cause go.mod to be written @@ -57,43 +56,43 @@ var ( ) // EnterModule resets MainModules and requirements to refer to just this one module. -func EnterModule(loaderstate *State, ctx context.Context, enterModroot string) { - loaderstate.MainModules = nil // reset MainModules - loaderstate.requirements = nil - loaderstate.workFilePath = "" // Force module mode - modfetch.Reset() +func EnterModule(ld *Loader, ctx context.Context, enterModroot string) { + ld.MainModules = nil // reset MainModules + ld.requirements = nil + ld.workFilePath = "" // Force module mode + ld.Fetcher().Reset() - loaderstate.modRoots = []string{enterModroot} - LoadModFile(loaderstate, ctx) + ld.modRoots = []string{enterModroot} + LoadModFile(ld, ctx) } // EnterWorkspace enters workspace mode from module mode, applying the updated requirements to the main // module to that module in the workspace. There should be no calls to any of the exported // functions of the modload package running concurrently with a call to EnterWorkspace as // EnterWorkspace will modify the global state they depend on in a non-thread-safe way. -func EnterWorkspace(loaderstate *State, ctx context.Context) (exit func(), err error) { +func EnterWorkspace(ld *Loader, ctx context.Context) (exit func(), err error) { // Find the identity of the main module that will be updated before we reset modload state. - mm := loaderstate.MainModules.mustGetSingleMainModule(loaderstate) + mm := ld.MainModules.mustGetSingleMainModule(ld) // Get the updated modfile we will use for that module. - _, _, updatedmodfile, err := UpdateGoModFromReqs(loaderstate, ctx, WriteOpts{}) + _, _, updatedmodfile, err := UpdateGoModFromReqs(ld, ctx, WriteOpts{}) if err != nil { return nil, err } // Reset the state to a clean state. - oldstate := loaderstate.setState(State{}) - loaderstate.ForceUseModules = true + oldstate := ld.setState(NewLoader()) + ld.ForceUseModules = true // Load in workspace mode. - InitWorkfile(loaderstate) - LoadModFile(loaderstate, ctx) + ld.InitWorkfile() + LoadModFile(ld, ctx) // Update the content of the previous main module, and recompute the requirements. - *loaderstate.MainModules.ModFile(mm) = *updatedmodfile - loaderstate.requirements = requirementsFromModFiles(loaderstate, ctx, loaderstate.MainModules.workFile, slices.Collect(maps.Values(loaderstate.MainModules.modFiles)), nil) + *ld.MainModules.ModFile(mm) = *updatedmodfile + ld.requirements = requirementsFromModFiles(ld, ctx, ld.MainModules.workFile, slices.Collect(maps.Values(ld.MainModules.modFiles)), nil) return func() { - loaderstate.setState(oldstate) + ld.setState(oldstate) }, nil } @@ -182,20 +181,20 @@ func (mms *MainModuleSet) InGorootSrc(m module.Version) bool { return mms.inGorootSrc[m] } -func (mms *MainModuleSet) mustGetSingleMainModule(loaderstate *State) module.Version { - mm, err := mms.getSingleMainModule(loaderstate) +func (mms *MainModuleSet) mustGetSingleMainModule(ld *Loader) module.Version { + mm, err := mms.getSingleMainModule(ld) if err != nil { panic(err) } return mm } -func (mms *MainModuleSet) getSingleMainModule(loaderstate *State) (module.Version, error) { +func (mms *MainModuleSet) getSingleMainModule(ld *Loader) (module.Version, error) { if mms == nil || len(mms.versions) == 0 { return module.Version{}, errors.New("internal error: mustGetSingleMainModule called in context with no main modules") } if len(mms.versions) != 1 { - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { return module.Version{}, errors.New("internal error: mustGetSingleMainModule called in workspace mode") } else { return module.Version{}, errors.New("internal error: multiple main modules present outside of workspace mode") @@ -204,14 +203,14 @@ func (mms *MainModuleSet) getSingleMainModule(loaderstate *State) (module.Versio return mms.versions[0], nil } -func (mms *MainModuleSet) GetSingleIndexOrNil(loaderstate *State) *modFileIndex { +func (mms *MainModuleSet) GetSingleIndexOrNil(ld *Loader) *modFileIndex { if mms == nil { return nil } if len(mms.versions) == 0 { return nil } - return mms.indices[mms.mustGetSingleMainModule(loaderstate)] + return mms.indices[mms.mustGetSingleMainModule(ld)] } func (mms *MainModuleSet) Index(m module.Version) *modFileIndex { @@ -254,12 +253,12 @@ func (mms *MainModuleSet) HighestReplaced() map[string]string { // GoVersion returns the go version set on the single module, in module mode, // or the go.work file in workspace mode. -func (mms *MainModuleSet) GoVersion(loaderstate *State) string { - if inWorkspaceMode(loaderstate) { +func (mms *MainModuleSet) GoVersion(ld *Loader) string { + if ld.inWorkspaceMode() { return gover.FromGoWork(mms.workFile) } if mms != nil && len(mms.versions) == 1 { - f := mms.ModFile(mms.mustGetSingleMainModule(loaderstate)) + f := mms.ModFile(mms.mustGetSingleMainModule(ld)) if f == nil { // Special case: we are outside a module, like 'go run x.go'. // Assume the local Go version. @@ -274,15 +273,15 @@ func (mms *MainModuleSet) GoVersion(loaderstate *State) string { // Godebugs returns the godebug lines set on the single module, in module mode, // or on the go.work file in workspace mode. // The caller must not modify the result. -func (mms *MainModuleSet) Godebugs(loaderstate *State) []*modfile.Godebug { - if inWorkspaceMode(loaderstate) { +func (mms *MainModuleSet) Godebugs(ld *Loader) []*modfile.Godebug { + if ld.inWorkspaceMode() { if mms.workFile != nil { return mms.workFile.Godebug } return nil } if mms != nil && len(mms.versions) == 1 { - f := mms.ModFile(mms.mustGetSingleMainModule(loaderstate)) + f := mms.ModFile(mms.mustGetSingleMainModule(ld)) if f == nil { // Special case: we are outside a module, like 'go run x.go'. return nil @@ -322,17 +321,17 @@ const ( // will be lost at the next call to WriteGoMod. // To make permanent changes to the require statements // in go.mod, edit it before loading. -func ModFile(loaderstate *State) *modfile.File { - Init(loaderstate) - modFile := loaderstate.MainModules.ModFile(loaderstate.MainModules.mustGetSingleMainModule(loaderstate)) +func ModFile(ld *Loader) *modfile.File { + Init(ld) + modFile := ld.MainModules.ModFile(ld.MainModules.mustGetSingleMainModule(ld)) if modFile == nil { - die(loaderstate) + die(ld) } return modFile } -func BinDir(loaderstate *State) string { - Init(loaderstate) +func BinDir(ld *Loader) string { + Init(ld) if cfg.GOBIN != "" { return cfg.GOBIN } @@ -345,13 +344,13 @@ func BinDir(loaderstate *State) string { // InitWorkfile initializes the workFilePath variable for commands that // operate in workspace mode. It should not be called by other commands, // for example 'go mod tidy', that don't operate in workspace mode. -func InitWorkfile(loaderstate *State) { +func (ld *Loader) InitWorkfile() { // Initialize fsys early because we need overlay to read go.work file. fips140.Init() if err := fsys.Init(); err != nil { base.Fatal(err) } - loaderstate.workFilePath = FindGoWork(loaderstate, base.Cwd()) + ld.workFilePath = ld.FindGoWork(base.Cwd()) } // FindGoWork returns the name of the go.work file for this command, @@ -359,8 +358,8 @@ func InitWorkfile(loaderstate *State) { // Most code should use Init and Enabled rather than use this directly. // It is exported mainly for Go toolchain switching, which must process // the go.work very early at startup. -func FindGoWork(loaderstate *State, wd string) string { - if loaderstate.RootMode == NoRoot { +func (ld *Loader) FindGoWork(wd string) string { + if ld.RootMode == NoRoot { return "" } @@ -379,43 +378,47 @@ func FindGoWork(loaderstate *State, wd string) string { // WorkFilePath returns the absolute path of the go.work file, or "" if not in // workspace mode. WorkFilePath must be called after InitWorkfile. -func WorkFilePath(loaderstate *State) string { - return loaderstate.workFilePath +func WorkFilePath(ld *Loader) string { + return ld.workFilePath } // Reset clears all the initialized, cached state about the use of modules, // so that we can start over. -func (s *State) Reset() { - s.setState(State{}) +func (ld *Loader) Reset() { + ld.setState(NewLoader()) } -func (s *State) setState(new State) State { - oldState := State{ - initialized: s.initialized, - ForceUseModules: s.ForceUseModules, - RootMode: s.RootMode, - modRoots: s.modRoots, +func (ld *Loader) setState(new *Loader) (old *Loader) { + old = &Loader{ + initialized: ld.initialized, + ForceUseModules: ld.ForceUseModules, + RootMode: ld.RootMode, + modRoots: ld.modRoots, modulesEnabled: cfg.ModulesEnabled, - MainModules: s.MainModules, - requirements: s.requirements, - } - s.initialized = new.initialized - s.ForceUseModules = new.ForceUseModules - s.RootMode = new.RootMode - s.modRoots = new.modRoots + MainModules: ld.MainModules, + requirements: ld.requirements, + workFilePath: ld.workFilePath, + fetcher: ld.fetcher, + } + ld.initialized = new.initialized + ld.ForceUseModules = new.ForceUseModules + ld.RootMode = new.RootMode + ld.modRoots = new.modRoots cfg.ModulesEnabled = new.modulesEnabled - s.MainModules = new.MainModules - s.requirements = new.requirements - s.workFilePath = new.workFilePath + ld.MainModules = new.MainModules + ld.requirements = new.requirements + ld.workFilePath = new.workFilePath // The modfetch package's global state is used to compute // the go.sum file, so save and restore it along with the // modload state. - oldState.modfetchState = modfetch.SetState(new.modfetchState) - return oldState + old.fetcher = ld.fetcher.SetState(new.fetcher) + + return old } -type State struct { - initialized bool +type Loader struct { + initialized bool + allowMissingModuleImports bool // ForceUseModules may be set to force modules to be enabled when // GO111MODULE=auto or to report an error when GO111MODULE=off. @@ -433,6 +436,14 @@ type State struct { modulesEnabled bool MainModules *MainModuleSet + // pkgLoader is the most recently-used package loader. + // It holds details about individual packages. + // + // This variable should only be accessed directly in top-level exported + // functions. All other functions that require or produce a *packageLoader should pass + // or return it as an explicit parameter. + pkgLoader *packageLoader + // requirements is the requirement graph for the main module. // // It is always non-nil if the main module's go.mod file has been @@ -447,23 +458,34 @@ type State struct { // Set to the path to the go.work file, or "" if workspace mode is // disabled - workFilePath string - modfetchState modfetch.State + workFilePath string + fetcher *modfetch.Fetcher } -func NewState() *State { return &State{} } +func NewLoader() *Loader { + s := new(Loader) + s.fetcher = modfetch.NewFetcher() + return s +} -var LoaderState = NewState() +func NewDisabledState() *Loader { + fips140.Init() + return &Loader{initialized: true, modulesEnabled: false} +} + +func (ld *Loader) Fetcher() *modfetch.Fetcher { + return ld.fetcher +} // Init determines whether module mode is enabled, locates the root of the // current module (if any), sets environment variables for Git subprocesses, and // configures the cfg, codehost, load, modfetch, and search packages for use // with modules. -func Init(loaderstate *State) { - if loaderstate.initialized { +func Init(ld *Loader) { + if ld.initialized { return } - loaderstate.initialized = true + ld.initialized = true fips140.Init() @@ -476,11 +498,11 @@ func Init(loaderstate *State) { default: base.Fatalf("go: unknown environment setting GO111MODULE=%s", env) case "auto": - mustUseModules = loaderstate.ForceUseModules + mustUseModules = ld.ForceUseModules case "on", "": mustUseModules = true case "off": - if loaderstate.ForceUseModules { + if ld.ForceUseModules { base.Fatalf("go: modules disabled by GO111MODULE=off; see 'go help modules'") } mustUseModules = false @@ -504,15 +526,15 @@ func Init(loaderstate *State) { if os.Getenv("GCM_INTERACTIVE") == "" { os.Setenv("GCM_INTERACTIVE", "never") } - if loaderstate.modRoots != nil { + if ld.modRoots != nil { // modRoot set before Init was called ("go mod init" does this). // No need to search for go.mod. - } else if loaderstate.RootMode == NoRoot { + } else if ld.RootMode == NoRoot { if cfg.ModFile != "" && !base.InGOFLAGS("-modfile") { base.Fatalf("go: -modfile cannot be used with commands that ignore the current module") } - loaderstate.modRoots = nil - } else if loaderstate.workFilePath != "" { + ld.modRoots = nil + } else if ld.workFilePath != "" { // We're in workspace mode, which implies module mode. if cfg.ModFile != "" { base.Fatalf("go: -modfile cannot be used in workspace mode") @@ -522,8 +544,8 @@ func Init(loaderstate *State) { if cfg.ModFile != "" { base.Fatalf("go: cannot find main module, but -modfile was set.\n\t-modfile cannot be used to set the module root directory.") } - if loaderstate.RootMode == NeedRoot { - base.Fatal(NewNoMainModulesError(loaderstate)) + if ld.RootMode == NeedRoot { + base.Fatal(NewNoMainModulesError(ld)) } if !mustUseModules { // GO111MODULE is 'auto', and we can't find a module root. @@ -537,14 +559,14 @@ func Init(loaderstate *State) { // It's a bit of a peculiar thing to disallow but quite mysterious // when it happens. See golang.org/issue/26708. fmt.Fprintf(os.Stderr, "go: warning: ignoring go.mod in system temp root %v\n", os.TempDir()) - if loaderstate.RootMode == NeedRoot { - base.Fatal(NewNoMainModulesError(loaderstate)) + if ld.RootMode == NeedRoot { + base.Fatal(NewNoMainModulesError(ld)) } if !mustUseModules { return } } else { - loaderstate.modRoots = []string{modRoot} + ld.modRoots = []string{modRoot} } } if cfg.ModFile != "" && !strings.HasSuffix(cfg.ModFile, ".mod") { @@ -553,14 +575,14 @@ func Init(loaderstate *State) { // We're in module mode. Set any global variables that need to be set. cfg.ModulesEnabled = true - setDefaultBuildMod(loaderstate) + setDefaultBuildMod(ld) list := filepath.SplitList(cfg.BuildContext.GOPATH) if len(list) > 0 && list[0] != "" { gopath = list[0] if _, err := fsys.Stat(filepath.Join(gopath, "go.mod")); err == nil { fmt.Fprintf(os.Stderr, "go: warning: ignoring go.mod in $GOPATH %v\n", gopath) - if loaderstate.RootMode == NeedRoot { - base.Fatal(NewNoMainModulesError(loaderstate)) + if ld.RootMode == NeedRoot { + base.Fatal(NewNoMainModulesError(ld)) } if !mustUseModules { return @@ -578,12 +600,12 @@ func Init(loaderstate *State) { // of 'go get', but Init reads the -modfile flag in 'go get', so it shouldn't // be called until the command is installed and flags are parsed. Instead of // calling Init and Enabled, the main package can call this function. -func WillBeEnabled(loaderstate *State) bool { - if loaderstate.modRoots != nil || cfg.ModulesEnabled { +func (ld *Loader) WillBeEnabled() bool { + if ld.modRoots != nil || cfg.ModulesEnabled { // Already enabled. return true } - if loaderstate.initialized { + if ld.initialized { // Initialized, not enabled. return false } @@ -600,7 +622,7 @@ func WillBeEnabled(loaderstate *State) bool { return false } - return FindGoMod(base.Cwd()) != "" + return FindGoMod(base.Cwd()) != "" || ld.FindGoWork(base.Cwd()) != "" } // FindGoMod returns the name of the go.mod file for this command, @@ -630,77 +652,77 @@ func FindGoMod(wd string) string { // If modules are enabled but there is no main module, Enabled returns true // and then the first use of module information will call die // (usually through MustModRoot). -func Enabled(loaderstate *State) bool { - Init(loaderstate) - return loaderstate.modRoots != nil || cfg.ModulesEnabled +func (ld *Loader) Enabled() bool { + Init(ld) + return ld.modRoots != nil || cfg.ModulesEnabled } -func (s *State) vendorDir() (string, error) { - if inWorkspaceMode(s) { - return filepath.Join(filepath.Dir(WorkFilePath(s)), "vendor"), nil +func (ld *Loader) vendorDir() (string, error) { + if ld.inWorkspaceMode() { + return filepath.Join(filepath.Dir(WorkFilePath(ld)), "vendor"), nil } - mainModule, err := s.MainModules.getSingleMainModule(s) + mainModule, err := ld.MainModules.getSingleMainModule(ld) if err != nil { return "", err } // Even if -mod=vendor, we could be operating with no mod root (and thus no // vendor directory). As long as there are no dependencies that is expected // to work. See script/vendor_outside_module.txt. - modRoot := s.MainModules.ModRoot(mainModule) + modRoot := ld.MainModules.ModRoot(mainModule) if modRoot == "" { return "", errors.New("vendor directory does not exist when in single module mode outside of a module") } return filepath.Join(modRoot, "vendor"), nil } -func (s *State) VendorDirOrEmpty() string { - dir, err := s.vendorDir() +func (ld *Loader) VendorDirOrEmpty() string { + dir, err := ld.vendorDir() if err != nil { return "" } return dir } -func VendorDir(loaderstate *State) string { - dir, err := loaderstate.vendorDir() +func VendorDir(ld *Loader) string { + dir, err := ld.vendorDir() if err != nil { panic(err) } return dir } -func inWorkspaceMode(loaderstate *State) bool { - if !loaderstate.initialized { +func (ld *Loader) inWorkspaceMode() bool { + if !ld.initialized { panic("inWorkspaceMode called before modload.Init called") } - if !Enabled(loaderstate) { + if !ld.Enabled() { return false } - return loaderstate.workFilePath != "" + return ld.workFilePath != "" } // HasModRoot reports whether a main module or main modules are present. // HasModRoot may return false even if Enabled returns true: for example, 'get' // does not require a main module. -func HasModRoot(loaderstate *State) bool { - Init(loaderstate) - return loaderstate.modRoots != nil +func (ld *Loader) HasModRoot() bool { + Init(ld) + return ld.modRoots != nil } // MustHaveModRoot checks that a main module or main modules are present, // and calls base.Fatalf if there are no main modules. -func MustHaveModRoot(loaderstate *State) { - Init(loaderstate) - if !HasModRoot(loaderstate) { - die(loaderstate) +func (ld *Loader) MustHaveModRoot() { + Init(ld) + if !ld.HasModRoot() { + die(ld) } } // ModFilePath returns the path that would be used for the go.mod // file, if in module mode. ModFilePath calls base.Fatalf if there is no main // module, even if -modfile is set. -func ModFilePath(loaderstate *State) string { - MustHaveModRoot(loaderstate) +func (ld *Loader) ModFilePath() string { + ld.MustHaveModRoot() return modFilePath(findModuleRoot(base.Cwd())) } @@ -714,11 +736,11 @@ func modFilePath(modRoot string) string { return filepath.Join(modRoot, "go.mod") } -func die(loaderstate *State) { +func die(ld *Loader) { if cfg.Getenv("GO111MODULE") == "off" { base.Fatalf("go: modules disabled by GO111MODULE=off; see 'go help modules'") } - if !inWorkspaceMode(loaderstate) { + if !ld.inWorkspaceMode() { if dir, name := findAltConfig(base.Cwd()); dir != "" { rel, err := filepath.Rel(base.Cwd(), dir) if err != nil { @@ -731,7 +753,7 @@ func die(loaderstate *State) { base.Fatalf("go: cannot find main module, but found %s in %s\n\tto create a module there, run:\n\t%sgo mod init", name, dir, cdCmd) } } - base.Fatal(NewNoMainModulesError(loaderstate)) + base.Fatal(NewNoMainModulesError(ld)) } var ErrNoModRoot = errors.New("no module root") @@ -753,9 +775,9 @@ func (e noMainModulesError) Unwrap() error { return ErrNoModRoot } -func NewNoMainModulesError(s *State) noMainModulesError { +func NewNoMainModulesError(ld *Loader) noMainModulesError { return noMainModulesError{ - inWorkspaceMode: inWorkspaceMode(s), + inWorkspaceMode: ld.inWorkspaceMode(), } } @@ -829,7 +851,7 @@ func WriteWorkFile(path string, wf *modfile.WorkFile) error { wf.Cleanup() out := modfile.Format(wf.Syntax) - return os.WriteFile(path, out, 0666) + return os.WriteFile(path, out, 0o666) } // UpdateWorkGoVersion updates the go line in wf to be at least goVers, @@ -908,33 +930,33 @@ func UpdateWorkFile(wf *modfile.WorkFile) { // other, but unlike LoadModGraph does not load the full module graph or check // it for global consistency. Most callers outside of the modload package should // use LoadModGraph instead. -func LoadModFile(loaderstate *State, ctx context.Context) *Requirements { - rs, err := loadModFile(loaderstate, ctx, nil) +func LoadModFile(ld *Loader, ctx context.Context) *Requirements { + rs, err := loadModFile(ld, ctx, nil) if err != nil { base.Fatal(err) } return rs } -func loadModFile(loaderstate *State, ctx context.Context, opts *PackageOpts) (*Requirements, error) { - if loaderstate.requirements != nil { - return loaderstate.requirements, nil +func loadModFile(ld *Loader, ctx context.Context, opts *PackageOpts) (*Requirements, error) { + if ld.requirements != nil { + return ld.requirements, nil } - Init(loaderstate) + Init(ld) var workFile *modfile.WorkFile - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { var err error - workFile, loaderstate.modRoots, err = LoadWorkFile(loaderstate.workFilePath) + workFile, ld.modRoots, err = LoadWorkFile(ld.workFilePath) if err != nil { return nil, err } - for _, modRoot := range loaderstate.modRoots { + for _, modRoot := range ld.modRoots { sumFile := strings.TrimSuffix(modFilePath(modRoot), ".mod") + ".sum" - modfetch.WorkspaceGoSumFiles = append(modfetch.WorkspaceGoSumFiles, sumFile) + ld.Fetcher().AddWorkspaceGoSumFile(sumFile) } - modfetch.GoSumFile = loaderstate.workFilePath + ".sum" - } else if len(loaderstate.modRoots) == 0 { + ld.Fetcher().SetGoSumFile(ld.workFilePath + ".sum") + } else if len(ld.modRoots) == 0 { // We're in module mode, but not inside a module. // // Commands like 'go build', 'go run', 'go list' have no go.mod file to @@ -953,25 +975,25 @@ func loadModFile(loaderstate *State, ctx context.Context, opts *PackageOpts) (*R // // See golang.org/issue/32027. } else { - modfetch.GoSumFile = strings.TrimSuffix(modFilePath(loaderstate.modRoots[0]), ".mod") + ".sum" + ld.Fetcher().SetGoSumFile(strings.TrimSuffix(modFilePath(ld.modRoots[0]), ".mod") + ".sum") } - if len(loaderstate.modRoots) == 0 { + if len(ld.modRoots) == 0 { // TODO(#49228): Instead of creating a fake module with an empty modroot, // make MainModules.Len() == 0 mean that we're in module mode but not inside // any module. mainModule := module.Version{Path: "command-line-arguments"} - loaderstate.MainModules = makeMainModules(loaderstate, []module.Version{mainModule}, []string{""}, []*modfile.File{nil}, []*modFileIndex{nil}, nil) + ld.MainModules = makeMainModules(ld, []module.Version{mainModule}, []string{""}, []*modfile.File{nil}, []*modFileIndex{nil}, nil) var ( goVersion string pruning modPruning roots []module.Version direct = map[string]bool{"go": true} ) - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { // Since we are in a workspace, the Go version for the synthetic // "command-line-arguments" module must not exceed the Go version // for the workspace. - goVersion = loaderstate.MainModules.GoVersion(loaderstate) + goVersion = ld.MainModules.GoVersion(ld) pruning = workspace roots = []module.Version{ mainModule, @@ -987,26 +1009,26 @@ func loadModFile(loaderstate *State, ctx context.Context, opts *PackageOpts) (*R } } rawGoVersion.Store(mainModule, goVersion) - loaderstate.requirements = newRequirements(loaderstate, pruning, roots, direct) + ld.requirements = newRequirements(ld, pruning, roots, direct) if cfg.BuildMod == "vendor" { // For issue 56536: Some users may have GOFLAGS=-mod=vendor set. // Make sure it behaves as though the fake module is vendored // with no dependencies. - loaderstate.requirements.initVendor(loaderstate, nil) + ld.requirements.initVendor(ld, nil) } - return loaderstate.requirements, nil + return ld.requirements, nil } var modFiles []*modfile.File var mainModules []module.Version var indices []*modFileIndex var errs []error - for _, modroot := range loaderstate.modRoots { + for _, modroot := range ld.modRoots { gomod := modFilePath(modroot) var fixed bool - data, f, err := ReadModFile(gomod, fixVersion(loaderstate, ctx, &fixed)) + data, f, err := ReadModFile(gomod, fixVersion(ld, ctx, &fixed)) if err != nil { - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { if tooNew, ok := err.(*gover.TooNewError); ok && !strings.HasPrefix(cfg.CmdName, "work ") { // Switching to a newer toolchain won't help - the go.work has the wrong version. // Report this more specific error, unless we are a command like 'go work use' @@ -1021,7 +1043,7 @@ func loadModFile(loaderstate *State, ctx context.Context, opts *PackageOpts) (*R errs = append(errs, err) continue } - if inWorkspaceMode(loaderstate) && !strings.HasPrefix(cfg.CmdName, "work ") { + if ld.inWorkspaceMode() && !strings.HasPrefix(cfg.CmdName, "work ") { // Refuse to use workspace if its go version is too old. // Disable this check if we are a workspace command like work use or work sync, // which will fix the problem. @@ -1033,7 +1055,7 @@ func loadModFile(loaderstate *State, ctx context.Context, opts *PackageOpts) (*R } } - if !inWorkspaceMode(loaderstate) { + if !ld.inWorkspaceMode() { ok := true for _, g := range f.Godebug { if err := CheckGodebug("godebug", g.Key, g.Value); err != nil { @@ -1062,45 +1084,45 @@ func loadModFile(loaderstate *State, ctx context.Context, opts *PackageOpts) (*R return nil, errors.Join(errs...) } - loaderstate.MainModules = makeMainModules(loaderstate, mainModules, loaderstate.modRoots, modFiles, indices, workFile) - setDefaultBuildMod(loaderstate) // possibly enable automatic vendoring - rs := requirementsFromModFiles(loaderstate, ctx, workFile, modFiles, opts) + ld.MainModules = makeMainModules(ld, mainModules, ld.modRoots, modFiles, indices, workFile) + setDefaultBuildMod(ld) // possibly enable automatic vendoring + rs := requirementsFromModFiles(ld, ctx, workFile, modFiles, opts) if cfg.BuildMod == "vendor" { - readVendorList(VendorDir(loaderstate)) - versions := loaderstate.MainModules.Versions() + readVendorList(VendorDir(ld)) + versions := ld.MainModules.Versions() indexes := make([]*modFileIndex, 0, len(versions)) modFiles := make([]*modfile.File, 0, len(versions)) modRoots := make([]string, 0, len(versions)) for _, m := range versions { - indexes = append(indexes, loaderstate.MainModules.Index(m)) - modFiles = append(modFiles, loaderstate.MainModules.ModFile(m)) - modRoots = append(modRoots, loaderstate.MainModules.ModRoot(m)) + indexes = append(indexes, ld.MainModules.Index(m)) + modFiles = append(modFiles, ld.MainModules.ModFile(m)) + modRoots = append(modRoots, ld.MainModules.ModRoot(m)) } - checkVendorConsistency(loaderstate, indexes, modFiles, modRoots) - rs.initVendor(loaderstate, vendorList) + checkVendorConsistency(ld, indexes, modFiles, modRoots) + rs.initVendor(ld, vendorList) } - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { // We don't need to update the mod file so return early. - loaderstate.requirements = rs + ld.requirements = rs return rs, nil } - mainModule := loaderstate.MainModules.mustGetSingleMainModule(loaderstate) + mainModule := ld.MainModules.mustGetSingleMainModule(ld) - if rs.hasRedundantRoot(loaderstate) { + if rs.hasRedundantRoot(ld) { // If any module path appears more than once in the roots, we know that the // go.mod file needs to be updated even though we have not yet loaded any // transitive dependencies. var err error - rs, err = updateRoots(loaderstate, ctx, rs.direct, rs, nil, nil, false) + rs, err = updateRoots(ld, ctx, rs.direct, rs, nil, nil, false) if err != nil { return nil, err } } - if loaderstate.MainModules.Index(mainModule).goVersion == "" && rs.pruning != workspace { + if ld.MainModules.Index(mainModule).goVersion == "" && rs.pruning != workspace { // TODO(#45551): Do something more principled instead of checking // cfg.CmdName directly here. if cfg.BuildMod == "mod" && cfg.CmdName != "mod graph" && cfg.CmdName != "mod why" { @@ -1109,8 +1131,8 @@ func loadModFile(loaderstate *State, ctx context.Context, opts *PackageOpts) (*R if opts != nil && opts.TidyGoVersion != "" { v = opts.TidyGoVersion } - addGoStmt(loaderstate.MainModules.ModFile(mainModule), mainModule, v) - rs = overrideRoots(loaderstate, ctx, rs, []module.Version{{Path: "go", Version: v}}) + addGoStmt(ld.MainModules.ModFile(mainModule), mainModule, v) + rs = overrideRoots(ld, ctx, rs, []module.Version{{Path: "go", Version: v}}) // We need to add a 'go' version to the go.mod file, but we must assume // that its existing contents match something between Go 1.11 and 1.16. @@ -1119,7 +1141,7 @@ func loadModFile(loaderstate *State, ctx context.Context, opts *PackageOpts) (*R // requirements to support pruning. if gover.Compare(v, gover.ExplicitIndirectVersion) >= 0 { var err error - rs, err = convertPruning(loaderstate, ctx, rs, pruned) + rs, err = convertPruning(ld, ctx, rs, pruned) if err != nil { return nil, err } @@ -1129,8 +1151,8 @@ func loadModFile(loaderstate *State, ctx context.Context, opts *PackageOpts) (*R } } - loaderstate.requirements = rs - return loaderstate.requirements, nil + ld.requirements = rs + return ld.requirements, nil } func errWorkTooOld(gomod string, wf *modfile.WorkFile, goVers string) error { @@ -1140,8 +1162,8 @@ func errWorkTooOld(gomod string, wf *modfile.WorkFile, goVers string) error { // even when it doesn't list any version. verb = "implicitly requires" } - return fmt.Errorf("module %s listed in go.work file requires go >= %s, but go.work %s go %s; to update it:\n\tgo work use", - base.ShortPath(filepath.Dir(gomod)), goVers, verb, gover.FromGoWork(wf)) + return fmt.Errorf("module %s listed in go.work file requires go >= %s, but go.work %s go %s; to download and use go %s:\n\tgo work use", + base.ShortPath(filepath.Dir(gomod)), goVers, verb, gover.FromGoWork(wf), goVers) } // CheckReservedModulePath checks whether the module path is a reserved module path @@ -1163,10 +1185,10 @@ func CheckReservedModulePath(path string) error { // translate it to go.mod directives. The resulting build list may not be // exactly the same as in the legacy configuration (for example, we can't get // packages at multiple versions from the same module). -func CreateModFile(loaderstate *State, ctx context.Context, modPath string) { +func CreateModFile(ld *Loader, ctx context.Context, modPath string) { modRoot := base.Cwd() - loaderstate.modRoots = []string{modRoot} - Init(loaderstate) + ld.modRoots = []string{modRoot} + Init(ld) modFilePath := modFilePath(modRoot) if _, err := fsys.Stat(modFilePath); err == nil { base.Fatalf("go: %s already exists", modFilePath) @@ -1178,40 +1200,26 @@ func CreateModFile(loaderstate *State, ctx context.Context, modPath string) { if err != nil { base.Fatal(err) } - } else if err := module.CheckImportPath(modPath); err != nil { - if pathErr, ok := err.(*module.InvalidPathError); ok { - pathErr.Kind = "module" - // Same as build.IsLocalPath() - if pathErr.Path == "." || pathErr.Path == ".." || - strings.HasPrefix(pathErr.Path, "./") || strings.HasPrefix(pathErr.Path, "../") { - pathErr.Err = errors.New("is a local import path") - } - } - base.Fatal(err) - } else if err := CheckReservedModulePath(modPath); err != nil { - base.Fatalf(`go: invalid module path %q: `, modPath) - } else if _, _, ok := module.SplitPathVersion(modPath); !ok { - if strings.HasPrefix(modPath, "gopkg.in/") { - invalidMajorVersionMsg := fmt.Errorf("module paths beginning with gopkg.in/ must always have a major version suffix in the form of .vN:\n\tgo mod init %s", suggestGopkgIn(modPath)) - base.Fatalf(`go: invalid module path "%v": %v`, modPath, invalidMajorVersionMsg) - } - invalidMajorVersionMsg := fmt.Errorf("major version suffixes must be in the form of /vN and are only allowed for v2 or later:\n\tgo mod init %s", suggestModulePath(modPath)) - base.Fatalf(`go: invalid module path "%v": %v`, modPath, invalidMajorVersionMsg) } + checkModulePath(modPath) - fmt.Fprintf(os.Stderr, "go: creating new go.mod: module %s\n", modPath) + if cfg.ModFile != "" { + fmt.Fprintf(os.Stderr, "go: creating new go.mod (using -modfile path %s): module %s\n", base.ShortPath(modFilePath), modPath) + } else { + fmt.Fprintf(os.Stderr, "go: creating new go.mod: module %s\n", modPath) + } modFile := new(modfile.File) modFile.AddModuleStmt(modPath) - loaderstate.MainModules = makeMainModules(loaderstate, []module.Version{modFile.Module.Mod}, []string{modRoot}, []*modfile.File{modFile}, []*modFileIndex{nil}, nil) + ld.MainModules = makeMainModules(ld, []module.Version{modFile.Module.Mod}, []string{modRoot}, []*modfile.File{modFile}, []*modFileIndex{nil}, nil) addGoStmt(modFile, modFile.Module.Mod, gover.Local()) // Add the go directive before converted module requirements. - rs := requirementsFromModFiles(loaderstate, ctx, nil, []*modfile.File{modFile}, nil) - rs, err := updateRoots(loaderstate, ctx, rs.direct, rs, nil, nil, false) + rs := requirementsFromModFiles(ld, ctx, nil, []*modfile.File{modFile}, nil) + rs, err := updateRoots(ld, ctx, rs.direct, rs, nil, nil, false) if err != nil { base.Fatal(err) } - loaderstate.requirements = rs - if err := commitRequirements(loaderstate, ctx, WriteOpts{}); err != nil { + ld.requirements = rs + if err := commitRequirements(ld, ctx, WriteOpts{}); err != nil { base.Fatal(err) } @@ -1239,6 +1247,31 @@ func CreateModFile(loaderstate *State, ctx context.Context, modPath string) { } } +func checkModulePath(modPath string) { + if err := module.CheckImportPath(modPath); err != nil { + if pathErr, ok := err.(*module.InvalidPathError); ok { + pathErr.Kind = "module" + // Same as build.IsLocalPath() + if pathErr.Path == "." || pathErr.Path == ".." || + strings.HasPrefix(pathErr.Path, "./") || strings.HasPrefix(pathErr.Path, "../") { + pathErr.Err = errors.New("is a local import path") + } + } + base.Fatal(err) + } + if err := CheckReservedModulePath(modPath); err != nil { + base.Fatalf(`go: invalid module path %q: `, modPath) + } + if _, _, ok := module.SplitPathVersion(modPath); !ok { + if strings.HasPrefix(modPath, "gopkg.in/") { + invalidMajorVersionMsg := fmt.Errorf("module paths beginning with gopkg.in/ must always have a major version suffix in the form of .vN:\n\tgo mod init %s", suggestGopkgIn(modPath)) + base.Fatalf(`go: invalid module path "%v": %v`, modPath, invalidMajorVersionMsg) + } + invalidMajorVersionMsg := fmt.Errorf("major version suffixes must be in the form of /vN and are only allowed for v2 or later:\n\tgo mod init %s", suggestModulePath(modPath)) + base.Fatalf(`go: invalid module path "%v": %v`, modPath, invalidMajorVersionMsg) + } +} + // fixVersion returns a modfile.VersionFixer implemented using the Query function. // // It resolves commit hashes and branch names to versions, @@ -1246,7 +1279,7 @@ func CreateModFile(loaderstate *State, ctx context.Context, modPath string) { // and does nothing for versions that already appear to be canonical. // // The VersionFixer sets 'fixed' if it ever returns a non-canonical version. -func fixVersion(loaderstate *State, ctx context.Context, fixed *bool) modfile.VersionFixer { +func fixVersion(ld *Loader, ctx context.Context, fixed *bool) modfile.VersionFixer { return func(path, vers string) (resolved string, err error) { defer func() { if err == nil && resolved != vers { @@ -1279,7 +1312,7 @@ func fixVersion(loaderstate *State, ctx context.Context, fixed *bool) modfile.Ve return vers, nil } - info, err := Query(loaderstate, ctx, path, vers, "", nil) + info, err := Query(ld, ctx, path, vers, "", nil) if err != nil { return "", err } @@ -1294,16 +1327,16 @@ func fixVersion(loaderstate *State, ctx context.Context, fixed *bool) modfile.Ve // // This function affects the default cfg.BuildMod when outside of a module, // so it can only be called prior to Init. -func AllowMissingModuleImports(loaderstate *State) { - if loaderstate.initialized { +func (ld *Loader) AllowMissingModuleImports() { + if ld.initialized { panic("AllowMissingModuleImports after Init") } - allowMissingModuleImports = true + ld.allowMissingModuleImports = true } // makeMainModules creates a MainModuleSet and associated variables according to // the given main modules. -func makeMainModules(loaderstate *State, ms []module.Version, rootDirs []string, modFiles []*modfile.File, indices []*modFileIndex, workFile *modfile.WorkFile) *MainModuleSet { +func makeMainModules(ld *Loader, ms []module.Version, rootDirs []string, modFiles []*modfile.File, indices []*modFileIndex, workFile *modfile.WorkFile) *MainModuleSet { for _, m := range ms { if m.Version != "" { panic("mainModulesCalled with module.Version with non empty Version field: " + fmt.Sprintf("%#v", m)) @@ -1378,7 +1411,7 @@ func makeMainModules(loaderstate *State, ms []module.Version, rootDirs []string, continue } var newV module.Version = r.New - if WorkFilePath(loaderstate) != "" && newV.Version == "" && !filepath.IsAbs(newV.Path) { + if WorkFilePath(ld) != "" && newV.Version == "" && !filepath.IsAbs(newV.Path) { // Since we are in a workspace, we may be loading replacements from // multiple go.mod files. Relative paths in those replacement are // relative to the go.mod file, not the workspace, so the same string @@ -1420,14 +1453,14 @@ func makeMainModules(loaderstate *State, ms []module.Version, rootDirs []string, // requirementsFromModFiles returns the set of non-excluded requirements from // the global modFile. -func requirementsFromModFiles(loaderstate *State, ctx context.Context, workFile *modfile.WorkFile, modFiles []*modfile.File, opts *PackageOpts) *Requirements { +func requirementsFromModFiles(ld *Loader, ctx context.Context, workFile *modfile.WorkFile, modFiles []*modfile.File, opts *PackageOpts) *Requirements { var roots []module.Version direct := map[string]bool{} var pruning modPruning - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { pruning = workspace - roots = make([]module.Version, len(loaderstate.MainModules.Versions()), 2+len(loaderstate.MainModules.Versions())) - copy(roots, loaderstate.MainModules.Versions()) + roots = make([]module.Version, len(ld.MainModules.Versions()), 2+len(ld.MainModules.Versions())) + copy(roots, ld.MainModules.Versions()) goVersion := gover.FromGoWork(workFile) var toolchain string if workFile.Toolchain != nil { @@ -1436,16 +1469,16 @@ func requirementsFromModFiles(loaderstate *State, ctx context.Context, workFile roots = appendGoAndToolchainRoots(roots, goVersion, toolchain, direct) direct = directRequirements(modFiles) } else { - pruning = pruningForGoVersion(loaderstate.MainModules.GoVersion(loaderstate)) + pruning = pruningForGoVersion(ld.MainModules.GoVersion(ld)) if len(modFiles) != 1 { panic(fmt.Errorf("requirementsFromModFiles called with %v modfiles outside workspace mode", len(modFiles))) } modFile := modFiles[0] - roots, direct = rootsFromModFile(loaderstate, loaderstate.MainModules.mustGetSingleMainModule(loaderstate), modFile, withToolchainRoot) + roots, direct = rootsFromModFile(ld, ld.MainModules.mustGetSingleMainModule(ld), modFile, withToolchainRoot) } gover.ModSort(roots) - rs := newRequirements(loaderstate, pruning, roots, direct) + rs := newRequirements(ld, pruning, roots, direct) return rs } @@ -1468,7 +1501,7 @@ func directRequirements(modFiles []*modfile.File) map[string]bool { return direct } -func rootsFromModFile(loaderstate *State, m module.Version, modFile *modfile.File, addToolchainRoot addToolchainRoot) (roots []module.Version, direct map[string]bool) { +func rootsFromModFile(ld *Loader, m module.Version, modFile *modfile.File, addToolchainRoot addToolchainRoot) (roots []module.Version, direct map[string]bool) { direct = make(map[string]bool) padding := 2 // Add padding for the toolchain and go version, added upon return. if !addToolchainRoot { @@ -1476,7 +1509,7 @@ func rootsFromModFile(loaderstate *State, m module.Version, modFile *modfile.Fil } roots = make([]module.Version, 0, padding+len(modFile.Require)) for _, r := range modFile.Require { - if index := loaderstate.MainModules.Index(m); index != nil && index.exclude[r.Mod] { + if index := ld.MainModules.Index(m); index != nil && index.exclude[r.Mod] { if cfg.BuildMod == "mod" { fmt.Fprintf(os.Stderr, "go: dropping requirement on excluded version %s %s\n", r.Mod.Path, r.Mod.Version) } else { @@ -1517,9 +1550,9 @@ func appendGoAndToolchainRoots(roots []module.Version, goVersion, toolchain stri // setDefaultBuildMod sets a default value for cfg.BuildMod if the -mod flag // wasn't provided. setDefaultBuildMod may be called multiple times. -func setDefaultBuildMod(loaderstate *State) { +func setDefaultBuildMod(ld *Loader) { if cfg.BuildModExplicit { - if inWorkspaceMode(loaderstate) && cfg.BuildMod != "readonly" && cfg.BuildMod != "vendor" { + if ld.inWorkspaceMode() && cfg.BuildMod != "readonly" && cfg.BuildMod != "vendor" { switch cfg.CmdName { case "work sync", "mod graph", "mod verify", "mod why": // These commands run with BuildMod set to mod, but they don't take the @@ -1554,8 +1587,8 @@ func setDefaultBuildMod(loaderstate *State) { cfg.BuildMod = "readonly" return } - if loaderstate.modRoots == nil { - if allowMissingModuleImports { + if ld.modRoots == nil { + if ld.allowMissingModuleImports { cfg.BuildMod = "mod" } else { cfg.BuildMod = "readonly" @@ -1563,29 +1596,29 @@ func setDefaultBuildMod(loaderstate *State) { return } - if len(loaderstate.modRoots) >= 1 { + if len(ld.modRoots) >= 1 { var goVersion string var versionSource string - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { versionSource = "go.work" - if wfg := loaderstate.MainModules.WorkFile().Go; wfg != nil { + if wfg := ld.MainModules.WorkFile().Go; wfg != nil { goVersion = wfg.Version } } else { versionSource = "go.mod" - index := loaderstate.MainModules.GetSingleIndexOrNil(loaderstate) + index := ld.MainModules.GetSingleIndexOrNil(ld) if index != nil { goVersion = index.goVersion } } vendorDir := "" - if loaderstate.workFilePath != "" { - vendorDir = filepath.Join(filepath.Dir(loaderstate.workFilePath), "vendor") + if ld.workFilePath != "" { + vendorDir = filepath.Join(filepath.Dir(ld.workFilePath), "vendor") } else { - if len(loaderstate.modRoots) != 1 { - panic(fmt.Errorf("outside workspace mode, but have %v modRoots", loaderstate.modRoots)) + if len(ld.modRoots) != 1 { + panic(fmt.Errorf("outside workspace mode, but have %v modRoots", ld.modRoots)) } - vendorDir = filepath.Join(loaderstate.modRoots[0], "vendor") + vendorDir = filepath.Join(ld.modRoots[0], "vendor") } if fi, err := fsys.Stat(vendorDir); err == nil && fi.IsDir() { if goVersion != "" { @@ -1653,8 +1686,8 @@ func modulesTextIsForWorkspace(vendorDir string) (bool, error) { return false, nil } -func mustHaveCompleteRequirements(loaderstate *State) bool { - return cfg.BuildMod != "mod" && !inWorkspaceMode(loaderstate) +func mustHaveCompleteRequirements(ld *Loader) bool { + return cfg.BuildMod != "mod" && !ld.inWorkspaceMode() } // addGoStmt adds a go directive to the go.mod file if it does not already @@ -1814,9 +1847,7 @@ Run 'go help mod init' for more information. return "", fmt.Errorf(msg, dir, reason) } -var ( - importCommentRE = lazyregexp.New(`(?m)^package[ \t]+[^ \t\r\n/]+[ \t]+//[ \t]+import[ \t]+(\"[^"]+\")[ \t]*\r?\n`) -) +var importCommentRE = lazyregexp.New(`(?m)^package[ \t]+[^ \t\r\n/]+[ \t]+//[ \t]+import[ \t]+(\"[^"]+\")[ \t]*\r?\n`) func findImportComment(file string) string { data, err := os.ReadFile(file) @@ -1848,22 +1879,22 @@ type WriteOpts struct { } // WriteGoMod writes the current build list back to go.mod. -func WriteGoMod(loaderstate *State, ctx context.Context, opts WriteOpts) error { - loaderstate.requirements = LoadModFile(loaderstate, ctx) - return commitRequirements(loaderstate, ctx, opts) +func WriteGoMod(ld *Loader, ctx context.Context, opts WriteOpts) error { + ld.requirements = LoadModFile(ld, ctx) + return commitRequirements(ld, ctx, opts) } var errNoChange = errors.New("no update needed") // UpdateGoModFromReqs returns a modified go.mod file using the current // requirements. It does not commit these changes to disk. -func UpdateGoModFromReqs(loaderstate *State, ctx context.Context, opts WriteOpts) (before, after []byte, modFile *modfile.File, err error) { - if loaderstate.MainModules.Len() != 1 || loaderstate.MainModules.ModRoot(loaderstate.MainModules.Versions()[0]) == "" { +func UpdateGoModFromReqs(ld *Loader, ctx context.Context, opts WriteOpts) (before, after []byte, modFile *modfile.File, err error) { + if ld.MainModules.Len() != 1 || ld.MainModules.ModRoot(ld.MainModules.Versions()[0]) == "" { // We aren't in a module, so we don't have anywhere to write a go.mod file. return nil, nil, nil, errNoChange } - mainModule := loaderstate.MainModules.mustGetSingleMainModule(loaderstate) - modFile = loaderstate.MainModules.ModFile(mainModule) + mainModule := ld.MainModules.mustGetSingleMainModule(ld) + modFile = ld.MainModules.ModFile(mainModule) if modFile == nil { // command-line-arguments has no .mod file to write. return nil, nil, nil, errNoChange @@ -1876,7 +1907,7 @@ func UpdateGoModFromReqs(loaderstate *State, ctx context.Context, opts WriteOpts var list []*modfile.Require toolchain := "" goVersion := "" - for _, m := range loaderstate.requirements.rootModules { + for _, m := range ld.requirements.rootModules { if m.Path == "go" { goVersion = m.Version continue @@ -1887,7 +1918,7 @@ func UpdateGoModFromReqs(loaderstate *State, ctx context.Context, opts WriteOpts } list = append(list, &modfile.Require{ Mod: m, - Indirect: !loaderstate.requirements.direct[m.Path], + Indirect: !ld.requirements.direct[m.Path], }) } @@ -1913,10 +1944,31 @@ func UpdateGoModFromReqs(loaderstate *State, ctx context.Context, opts WriteOpts forceGoStmt(modFile, mainModule, goVersion) } } + + // Add Go 1.24 requirement if we're running go get and there are tool directives. + tools := map[string]bool{} + for _, t := range modFile.Tool { + tools[t.Path] = true + } + for _, t := range opts.DropTools { + delete(tools, t) + } + for _, t := range opts.AddTools { + tools[t] = true + } + if len(tools) > 0 && gover.Compare(goVersion, gover.GoModToolVersion) < 0 && cfg.CmdName == "get" { + if opts.ExplicitToolchain { + return nil, nil, nil, errors.New(gover.GoModToolVersion + " is required for tool directives in go.mod: go get go@" + gover.GoModToolVersion + ".0") + } + // TODO: If we start enforcing that the go version is > 1.24 on modules + // that have tool directives, add a requirement instead of calling forceGoStmt. + goVersion = gover.GoModToolVersion + forceGoStmt(modFile, mainModule, gover.GoModToolVersion) + } + if toolchain == "" { toolchain = "go" + goVersion } - toolVers := gover.FromToolchain(toolchain) if opts.DropToolchain || toolchain == "go"+goVersion || (gover.Compare(toolVers, gover.GoStrictVersion) < 0 && !opts.ExplicitToolchain) { // go get toolchain@none or toolchain matches go line or isn't valid; drop it. @@ -1937,8 +1989,10 @@ func UpdateGoModFromReqs(loaderstate *State, ctx context.Context, opts WriteOpts // Update require blocks. if gover.Compare(goVersion, gover.SeparateIndirectVersion) < 0 { modFile.SetRequire(list) - } else { + } else if gover.Compare(goVersion, gover.SimplifyRequireVersion) < 0 { modFile.SetRequireSeparateIndirect(list) + } else { + modFile.SetRequireAtMostTwo(list) } modFile.Cleanup() after, err = modFile.Format() @@ -1957,13 +2011,13 @@ func UpdateGoModFromReqs(loaderstate *State, ctx context.Context, opts WriteOpts // go.mod or go.sum are out of date in a semantically significant way. // // In workspace mode, commitRequirements only writes changes to go.work.sum. -func commitRequirements(loaderstate *State, ctx context.Context, opts WriteOpts) (err error) { - if inWorkspaceMode(loaderstate) { +func commitRequirements(ld *Loader, ctx context.Context, opts WriteOpts) (err error) { + if ld.inWorkspaceMode() { // go.mod files aren't updated in workspace mode, but we still want to // update the go.work.sum file. - return modfetch.WriteGoSum(ctx, keepSums(loaderstate, ctx, loaded, loaderstate.requirements, addBuildListZipSums), mustHaveCompleteRequirements(loaderstate)) + return ld.Fetcher().WriteGoSum(ctx, keepSums(ld, ctx, ld.pkgLoader, ld.requirements, addBuildListZipSums), mustHaveCompleteRequirements(ld)) } - _, updatedGoMod, modFile, err := UpdateGoModFromReqs(loaderstate, ctx, opts) + _, updatedGoMod, modFile, err := UpdateGoModFromReqs(ld, ctx, opts) if err != nil { if errors.Is(err, errNoChange) { return nil @@ -1971,7 +2025,7 @@ func commitRequirements(loaderstate *State, ctx context.Context, opts WriteOpts) return err } - index := loaderstate.MainModules.GetSingleIndexOrNil(loaderstate) + index := ld.MainModules.GetSingleIndexOrNil(ld) dirty := index.modFileIsDirty(modFile) || len(opts.DropTools) > 0 || len(opts.AddTools) > 0 if dirty && cfg.BuildMod != "mod" { // If we're about to fail due to -mod=readonly, @@ -1985,15 +2039,15 @@ func commitRequirements(loaderstate *State, ctx context.Context, opts WriteOpts) // Don't write go.mod, but write go.sum in case we added or trimmed sums. // 'go mod init' shouldn't write go.sum, since it will be incomplete. if cfg.CmdName != "mod init" { - if err := modfetch.WriteGoSum(ctx, keepSums(loaderstate, ctx, loaded, loaderstate.requirements, addBuildListZipSums), mustHaveCompleteRequirements(loaderstate)); err != nil { + if err := ld.Fetcher().WriteGoSum(ctx, keepSums(ld, ctx, ld.pkgLoader, ld.requirements, addBuildListZipSums), mustHaveCompleteRequirements(ld)); err != nil { return err } } return nil } - mainModule := loaderstate.MainModules.mustGetSingleMainModule(loaderstate) - modFilePath := modFilePath(loaderstate.MainModules.ModRoot(mainModule)) + mainModule := ld.MainModules.mustGetSingleMainModule(ld) + modFilePath := modFilePath(ld.MainModules.ModRoot(mainModule)) if fsys.Replaced(modFilePath) { if dirty { return errors.New("updates to go.mod needed, but go.mod is part of the overlay specified with -overlay") @@ -2002,13 +2056,13 @@ func commitRequirements(loaderstate *State, ctx context.Context, opts WriteOpts) } defer func() { // At this point we have determined to make the go.mod file on disk equal to new. - loaderstate.MainModules.SetIndex(mainModule, indexModFile(updatedGoMod, modFile, mainModule, false)) + ld.MainModules.SetIndex(mainModule, indexModFile(updatedGoMod, modFile, mainModule, false)) // Update go.sum after releasing the side lock and refreshing the index. // 'go mod init' shouldn't write go.sum, since it will be incomplete. if cfg.CmdName != "mod init" { if err == nil { - err = modfetch.WriteGoSum(ctx, keepSums(loaderstate, ctx, loaded, loaderstate.requirements, addBuildListZipSums), mustHaveCompleteRequirements(loaderstate)) + err = ld.Fetcher().WriteGoSum(ctx, keepSums(ld, ctx, ld.pkgLoader, ld.requirements, addBuildListZipSums), mustHaveCompleteRequirements(ld)) } } }() @@ -2051,7 +2105,7 @@ func commitRequirements(loaderstate *State, ctx context.Context, opts WriteOpts) // including any go.mod files needed to reconstruct the MVS result // or identify go versions, // in addition to the checksums for every module in keepMods. -func keepSums(loaderstate *State, ctx context.Context, ld *loader, rs *Requirements, which whichSums) map[module.Version]bool { +func keepSums(ld *Loader, ctx context.Context, pld *packageLoader, rs *Requirements, which whichSums) map[module.Version]bool { // Every module in the full module graph contributes its requirements, // so in order to ensure that the build list itself is reproducible, // we need sums for every go.mod in the graph (regardless of whether @@ -2063,17 +2117,17 @@ func keepSums(loaderstate *State, ctx context.Context, ld *loader, rs *Requireme // not just the modules containing the actual packages — in order to rule out // ambiguous import errors the next time we load the package. keepModSumsForZipSums := true - if ld == nil { - if gover.Compare(loaderstate.MainModules.GoVersion(loaderstate), gover.TidyGoModSumVersion) < 0 && cfg.BuildMod != "mod" { + if pld == nil { + if gover.Compare(ld.MainModules.GoVersion(ld), gover.TidyGoModSumVersion) < 0 && cfg.BuildMod != "mod" { keepModSumsForZipSums = false } } else { keepPkgGoModSums := true - if gover.Compare(ld.requirements.GoVersion(loaderstate), gover.TidyGoModSumVersion) < 0 && (ld.Tidy || cfg.BuildMod != "mod") { + if gover.Compare(pld.requirements.GoVersion(ld), gover.TidyGoModSumVersion) < 0 && (pld.Tidy || cfg.BuildMod != "mod") { keepPkgGoModSums = false keepModSumsForZipSums = false } - for _, pkg := range ld.pkgs { + for _, pkg := range pld.pkgs { // We check pkg.mod.Path here instead of pkg.inStd because the // pseudo-package "C" is not in std, but not provided by any module (and // shouldn't force loading the whole module graph). @@ -2087,21 +2141,21 @@ func keepSums(loaderstate *State, ctx context.Context, ld *loader, rs *Requireme // minor, so we maintain the previous (buggy) behavior in 'go mod tidy' to // avoid introducing unnecessary churn. if keepPkgGoModSums { - r := resolveReplacement(loaderstate, pkg.mod) + r := resolveReplacement(ld, pkg.mod) keep[modkey(r)] = true } if rs.pruning == pruned && pkg.mod.Path != "" { - if v, ok := rs.rootSelected(loaderstate, pkg.mod.Path); ok && v == pkg.mod.Version { + if v, ok := rs.rootSelected(ld, pkg.mod.Path); ok && v == pkg.mod.Version { // pkg was loaded from a root module, and because the main module has // a pruned module graph we do not check non-root modules for // conflicts for packages that can be found in roots. So we only need // the checksums for the root modules that may contain pkg, not all // possible modules. for prefix := pkg.path; prefix != "."; prefix = path.Dir(prefix) { - if v, ok := rs.rootSelected(loaderstate, prefix); ok && v != "none" { + if v, ok := rs.rootSelected(ld, prefix); ok && v != "none" { m := module.Version{Path: prefix, Version: v} - r := resolveReplacement(loaderstate, m) + r := resolveReplacement(ld, m) keep[r] = true } } @@ -2109,11 +2163,11 @@ func keepSums(loaderstate *State, ctx context.Context, ld *loader, rs *Requireme } } - mg, _ := rs.Graph(loaderstate, ctx) + mg, _ := rs.Graph(ld, ctx) for prefix := pkg.path; prefix != "."; prefix = path.Dir(prefix) { if v := mg.Selected(prefix); v != "none" { m := module.Version{Path: prefix, Version: v} - r := resolveReplacement(loaderstate, m) + r := resolveReplacement(ld, m) keep[r] = true } } @@ -2125,27 +2179,27 @@ func keepSums(loaderstate *State, ctx context.Context, ld *loader, rs *Requireme // Save sums for the root modules (or their replacements), but don't // incur the cost of loading the graph just to find and retain the sums. for _, m := range rs.rootModules { - r := resolveReplacement(loaderstate, m) + r := resolveReplacement(ld, m) keep[modkey(r)] = true if which == addBuildListZipSums { keep[r] = true } } } else { - mg, _ := rs.Graph(loaderstate, ctx) + mg, _ := rs.Graph(ld, ctx) mg.WalkBreadthFirst(func(m module.Version) { if _, ok := mg.RequiredBy(m); ok { // The requirements from m's go.mod file are present in the module graph, // so they are relevant to the MVS result regardless of whether m was // actually selected. - r := resolveReplacement(loaderstate, m) + r := resolveReplacement(ld, m) keep[modkey(r)] = true } }) if which == addBuildListZipSums { for _, m := range mg.BuildList() { - r := resolveReplacement(loaderstate, m) + r := resolveReplacement(ld, m) if keepModSumsForZipSums { keep[modkey(r)] = true // we need the go version from the go.mod file to do anything useful with the zipfile } @@ -2245,8 +2299,15 @@ func CheckGodebug(verb, k, v string) error { } return nil } - for _, info := range godebugs.All { - if k == info.Name { + if godebugs.Lookup(k) != nil { + return nil + } + for _, info := range godebugs.Removed { + if info.Name == k { + if info.Old(v) { + return fmt.Errorf("removed GODEBUG %q set to old value %q (https://go.dev/doc/godebug#go-1%v)", k, v, info.Removed) + } + // Using a removed GODEBUG setting with a non-old value is ok (see go.dev/issue/76163). return nil } } diff --git a/src/cmd/go/internal/modload/list.go b/src/cmd/go/internal/modload/list.go index 6a4d788824caa9..762e760c6874c8 100644 --- a/src/cmd/go/internal/modload/list.go +++ b/src/cmd/go/internal/modload/list.go @@ -41,7 +41,7 @@ const ( // along with any error preventing additional matches from being identified. // // The returned slice can be nonempty even if the error is non-nil. -func ListModules(loaderstate *State, ctx context.Context, args []string, mode ListMode, reuseFile string) ([]*modinfo.ModulePublic, error) { +func ListModules(ld *Loader, ctx context.Context, args []string, mode ListMode, reuseFile string) ([]*modinfo.ModulePublic, error) { var reuse map[module.Version]*modinfo.ModulePublic if reuseFile != "" { data, err := os.ReadFile(reuseFile) @@ -69,7 +69,7 @@ func ListModules(loaderstate *State, ctx context.Context, args []string, mode Li } } - rs, mods, err := listModules(loaderstate, ctx, LoadModFile(loaderstate, ctx), args, mode, reuse) + rs, mods, err := listModules(ld, ctx, LoadModFile(ld, ctx), args, mode, reuse) type token struct{} sem := make(chan token, runtime.GOMAXPROCS(0)) @@ -82,16 +82,16 @@ func ListModules(loaderstate *State, ctx context.Context, args []string, mode Li sem <- token{} go func() { if mode&ListU != 0 { - addUpdate(loaderstate, ctx, m) + addUpdate(ld, ctx, m) } if mode&ListVersions != 0 { - addVersions(loaderstate, ctx, m, mode&ListRetractedVersions != 0) + addVersions(ld, ctx, m, mode&ListRetractedVersions != 0) } if mode&ListRetracted != 0 { - addRetraction(loaderstate, ctx, m) + addRetraction(ld, ctx, m) } if mode&ListDeprecated != 0 { - addDeprecation(loaderstate, ctx, m) + addDeprecation(ld, ctx, m) } <-sem }() @@ -109,7 +109,7 @@ func ListModules(loaderstate *State, ctx context.Context, args []string, mode Li } if err == nil { - loaderstate.requirements = rs + ld.requirements = rs // TODO(#61605): The extra ListU clause fixes a problem with Go 1.21rc3 // where "go mod tidy" and "go list -m -u all" fight over whether the go.sum // should be considered up-to-date. The fix for now is to always treat the @@ -117,20 +117,20 @@ func ListModules(loaderstate *State, ctx context.Context, args []string, mode Li // but in general list -u is looking up other checksums in the checksum database // that won't be necessary later, so it makes sense not to write the go.sum back out. if !ExplicitWriteGoMod && mode&ListU == 0 { - err = commitRequirements(loaderstate, ctx, WriteOpts{}) + err = commitRequirements(ld, ctx, WriteOpts{}) } } return mods, err } -func listModules(loaderstate *State, ctx context.Context, rs *Requirements, args []string, mode ListMode, reuse map[module.Version]*modinfo.ModulePublic) (_ *Requirements, mods []*modinfo.ModulePublic, mgErr error) { +func listModules(ld *Loader, ctx context.Context, rs *Requirements, args []string, mode ListMode, reuse map[module.Version]*modinfo.ModulePublic) (_ *Requirements, mods []*modinfo.ModulePublic, mgErr error) { if len(args) == 0 { var ms []*modinfo.ModulePublic - for _, m := range loaderstate.MainModules.Versions() { + for _, m := range ld.MainModules.Versions() { if gover.IsToolchain(m.Path) { continue } - ms = append(ms, moduleInfo(loaderstate, ctx, rs, m, mode, reuse)) + ms = append(ms, moduleInfo(ld, ctx, rs, m, mode, reuse)) } return rs, ms, nil } @@ -145,41 +145,49 @@ func listModules(loaderstate *State, ctx context.Context, rs *Requirements, args } if arg == "all" || strings.Contains(arg, "...") { needFullGraph = true - if !HasModRoot(loaderstate) { - base.Fatalf("go: cannot match %q: %v", arg, NewNoMainModulesError(loaderstate)) + if !ld.HasModRoot() { + base.Fatalf("go: cannot match %q: %v", arg, NewNoMainModulesError(ld)) } continue } - if path, vers, found := strings.Cut(arg, "@"); found { + path, vers, found, err := ParsePathVersion(arg) + if err != nil { + base.Fatalf("go: %v", err) + } + if found { if vers == "upgrade" || vers == "patch" { - if _, ok := rs.rootSelected(loaderstate, path); !ok || rs.pruning == unpruned { + if _, ok := rs.rootSelected(ld, path); !ok || rs.pruning == unpruned { needFullGraph = true - if !HasModRoot(loaderstate) { - base.Fatalf("go: cannot match %q: %v", arg, NewNoMainModulesError(loaderstate)) + if !ld.HasModRoot() { + base.Fatalf("go: cannot match %q: %v", arg, NewNoMainModulesError(ld)) } } } continue } - if _, ok := rs.rootSelected(loaderstate, arg); !ok || rs.pruning == unpruned { + if _, ok := rs.rootSelected(ld, arg); !ok || rs.pruning == unpruned { needFullGraph = true - if mode&ListVersions == 0 && !HasModRoot(loaderstate) { - base.Fatalf("go: cannot match %q without -versions or an explicit version: %v", arg, NewNoMainModulesError(loaderstate)) + if mode&ListVersions == 0 && !ld.HasModRoot() { + base.Fatalf("go: cannot match %q without -versions or an explicit version: %v", arg, NewNoMainModulesError(ld)) } } } var mg *ModuleGraph if needFullGraph { - rs, mg, mgErr = expandGraph(loaderstate, ctx, rs) + rs, mg, mgErr = expandGraph(ld, ctx, rs) } matchedModule := map[module.Version]bool{} for _, arg := range args { - if path, vers, found := strings.Cut(arg, "@"); found { + path, vers, found, err := ParsePathVersion(arg) + if err != nil { + base.Fatalf("go: %v", err) + } + if found { var current string if mg == nil { - current, _ = rs.rootSelected(loaderstate, path) + current, _ = rs.rootSelected(ld, path) } else { current = mg.Selected(path) } @@ -192,13 +200,13 @@ func listModules(loaderstate *State, ctx context.Context, rs *Requirements, args } } - allowed := loaderstate.CheckAllowed + allowed := ld.CheckAllowed if IsRevisionQuery(path, vers) || mode&ListRetracted != 0 { // Allow excluded and retracted versions if the user asked for a // specific revision or used 'go list -retracted'. allowed = nil } - info, err := queryReuse(loaderstate, ctx, path, vers, current, allowed, reuse) + info, err := queryReuse(ld, ctx, path, vers, current, allowed, reuse) if err != nil { var origin *codehost.Origin if info != nil { @@ -217,7 +225,7 @@ func listModules(loaderstate *State, ctx context.Context, rs *Requirements, args // *Requirements instead. var noRS *Requirements - mod := moduleInfo(loaderstate, ctx, noRS, module.Version{Path: path, Version: info.Version}, mode, reuse) + mod := moduleInfo(ld, ctx, noRS, module.Version{Path: path, Version: info.Version}, mode, reuse) if vers != mod.Version { mod.Query = vers } @@ -237,7 +245,7 @@ func listModules(loaderstate *State, ctx context.Context, rs *Requirements, args var v string if mg == nil { var ok bool - v, ok = rs.rootSelected(loaderstate, arg) + v, ok = rs.rootSelected(ld, arg) if !ok { // We checked rootSelected(arg) in the earlier args loop, so if there // is no such root we should have loaded a non-nil mg. @@ -251,7 +259,7 @@ func listModules(loaderstate *State, ctx context.Context, rs *Requirements, args continue } if v != "none" { - mods = append(mods, moduleInfo(loaderstate, ctx, rs, module.Version{Path: arg, Version: v}, mode, reuse)) + mods = append(mods, moduleInfo(ld, ctx, rs, module.Version{Path: arg, Version: v}, mode, reuse)) } else if cfg.BuildMod == "vendor" { // In vendor mode, we can't determine whether a missing module is “a // known dependency” because the module graph is incomplete. @@ -292,7 +300,7 @@ func listModules(loaderstate *State, ctx context.Context, rs *Requirements, args fetchedMods := make([]*modinfo.ModulePublic, len(matches)) for i, m := range matches { q.Add(func() { - fetchedMods[i] = moduleInfo(loaderstate, ctx, rs, m, mode, reuse) + fetchedMods[i] = moduleInfo(ld, ctx, rs, m, mode, reuse) }) } <-q.Idle() @@ -317,3 +325,21 @@ func modinfoError(path, vers string, err error) *modinfo.ModuleError { return &modinfo.ModuleError{Err: err.Error()} } + +// ParsePathVersion parses arg expecting arg to be path@version. If there is no +// '@' in arg, found is false, vers is "", and path is arg. This mirrors the +// typical usage of strings.Cut. ParsePathVersion is meant to be a general +// replacement for strings.Cut in module version parsing. If the version is +// invalid, an error is returned. The version is considered invalid if it is +// prefixed with '-' or '/', which can cause security problems when constructing +// commands to execute that use the version. +func ParsePathVersion(arg string) (path, vers string, found bool, err error) { + path, vers, found = strings.Cut(arg, "@") + if !found { + return arg, "", false, nil + } + if len(vers) > 0 && (vers[0] == '-' || vers[0] == '/') { + return "", "", false, fmt.Errorf("invalid module version %q", vers) + } + return path, vers, true, nil +} diff --git a/src/cmd/go/internal/modload/load.go b/src/cmd/go/internal/modload/load.go index 065d3a78163a21..4706d05e914330 100644 --- a/src/cmd/go/internal/modload/load.go +++ b/src/cmd/go/internal/modload/load.go @@ -128,14 +128,6 @@ import ( "golang.org/x/mod/module" ) -// loaded is the most recently-used package loader. -// It holds details about individual packages. -// -// This variable should only be accessed directly in top-level exported -// functions. All other functions that require or produce a *loader should pass -// or return it as an explicit parameter. -var loaded *loader - // PackageOpts control the behavior of the LoadPackages function. type PackageOpts struct { // TidyGoVersion is the Go version to which the go.mod file should be updated @@ -250,7 +242,7 @@ type PackageOpts struct { // LoadPackages identifies the set of packages matching the given patterns and // loads the packages in the import graph rooted at that set. -func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, patterns ...string) (matches []*search.Match, loadedPackages []string) { +func LoadPackages(ld *Loader, ctx context.Context, opts PackageOpts, patterns ...string) (matches []*search.Match, loadedPackages []string) { if opts.Tags == nil { opts.Tags = imports.Tags() } @@ -265,17 +257,17 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat } } - updateMatches := func(rs *Requirements, ld *loader) { + updateMatches := func(rs *Requirements, pld *packageLoader) { for _, m := range matches { switch { case m.IsLocal(): // Evaluate list of file system directories on first iteration. if m.Dirs == nil { - matchModRoots := loaderstate.modRoots + matchModRoots := ld.modRoots if opts.MainModule != (module.Version{}) { - matchModRoots = []string{loaderstate.MainModules.ModRoot(opts.MainModule)} + matchModRoots = []string{ld.MainModules.ModRoot(opts.MainModule)} } - matchLocalDirs(loaderstate, ctx, matchModRoots, m, rs) + matchLocalDirs(ld, ctx, matchModRoots, m, rs) } // Make a copy of the directory list and translate to import paths. @@ -286,7 +278,7 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat // the loader iterations. m.Pkgs = m.Pkgs[:0] for _, dir := range m.Dirs { - pkg, err := resolveLocalPackage(loaderstate, ctx, dir, rs) + pkg, err := resolveLocalPackage(ld, ctx, dir, rs) if err != nil { if !m.IsLiteral() && (err == errPkgIsBuiltin || err == errPkgIsGorootSrc) { continue // Don't include "builtin" or GOROOT/src in wildcard patterns. @@ -294,11 +286,11 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat // If we're outside of a module, ensure that the failure mode // indicates that. - if !HasModRoot(loaderstate) { - die(loaderstate) + if !ld.HasModRoot() { + die(ld) } - if ld != nil { + if pld != nil { m.AddError(err) } continue @@ -311,7 +303,7 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat case strings.Contains(m.Pattern(), "..."): m.Errs = m.Errs[:0] - mg, err := rs.Graph(loaderstate, ctx) + mg, err := rs.Graph(ld, ctx) if err != nil { // The module graph is (or may be) incomplete — perhaps we failed to // load the requirements of some module. This is an error in matching @@ -321,32 +313,32 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat // necessarily prevent us from loading the packages we could find. m.Errs = append(m.Errs, err) } - matchPackages(loaderstate, ctx, m, opts.Tags, includeStd, mg.BuildList()) + matchPackages(ld, ctx, m, opts.Tags, includeStd, mg.BuildList()) case m.Pattern() == "work": - matchModules := loaderstate.MainModules.Versions() + matchModules := ld.MainModules.Versions() if opts.MainModule != (module.Version{}) { matchModules = []module.Version{opts.MainModule} } - matchPackages(loaderstate, ctx, m, opts.Tags, omitStd, matchModules) + matchPackages(ld, ctx, m, opts.Tags, omitStd, matchModules) case m.Pattern() == "all": - if ld == nil { + if pld == nil { // The initial roots are the packages and tools in the main module. // loadFromRoots will expand that to "all". m.Errs = m.Errs[:0] - matchModules := loaderstate.MainModules.Versions() + matchModules := ld.MainModules.Versions() if opts.MainModule != (module.Version{}) { matchModules = []module.Version{opts.MainModule} } - matchPackages(loaderstate, ctx, m, opts.Tags, omitStd, matchModules) - for tool := range loaderstate.MainModules.Tools() { + matchPackages(ld, ctx, m, opts.Tags, omitStd, matchModules) + for tool := range ld.MainModules.Tools() { m.Pkgs = append(m.Pkgs, tool) } } else { // Starting with the packages in the main module, // enumerate the full list of "all". - m.Pkgs = ld.computePatternAll() + m.Pkgs = pld.computePatternAll() } case m.Pattern() == "std" || m.Pattern() == "cmd": @@ -355,7 +347,7 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat } case m.Pattern() == "tool": - for tool := range loaderstate.MainModules.Tools() { + for tool := range ld.MainModules.Tools() { m.Pkgs = append(m.Pkgs, tool) } default: @@ -364,12 +356,12 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat } } - initialRS, err := loadModFile(loaderstate, ctx, &opts) + initialRS, err := loadModFile(ld, ctx, &opts) if err != nil { base.Fatal(err) } - ld := loadFromRoots(loaderstate, ctx, loaderParams{ + pld := loadFromRoots(ld, ctx, loaderParams{ PackageOpts: opts, requirements: initialRS, @@ -385,18 +377,18 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat }) // One last pass to finalize wildcards. - updateMatches(ld.requirements, ld) + updateMatches(pld.requirements, pld) // List errors in matching patterns (such as directory permission // errors for wildcard patterns). - if !ld.SilencePackageErrors { + if !pld.SilencePackageErrors { for _, match := range matches { for _, err := range match.Errs { - ld.error(err) + pld.error(err) } } } - ld.exitIfErrors(ctx) + pld.exitIfErrors(ctx) if !opts.SilenceUnmatchedWarnings { search.WarnUnmatched(matches) @@ -404,10 +396,10 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat if opts.Tidy { if cfg.BuildV { - mg, _ := ld.requirements.Graph(loaderstate, ctx) + mg, _ := pld.requirements.Graph(ld, ctx) for _, m := range initialRS.rootModules { var unused bool - if ld.requirements.pruning == unpruned { + if pld.requirements.pruning == unpruned { // m is unused if it was dropped from the module graph entirely. If it // was only demoted from direct to indirect, it may still be in use via // a transitive import. @@ -416,7 +408,7 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat // m is unused if it was dropped from the roots. If it is still present // as a transitive dependency, that transitive dependency is not needed // by any package or test in the main module. - _, ok := ld.requirements.rootSelected(loaderstate, m.Path) + _, ok := pld.requirements.rootSelected(ld, m.Path) unused = !ok } if unused { @@ -425,9 +417,9 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat } } - keep := keepSums(loaderstate, ctx, ld, ld.requirements, loadedZipSumsOnly) - compatVersion := ld.TidyCompatibleVersion - goVersion := ld.requirements.GoVersion(loaderstate) + keep := keepSums(ld, ctx, pld, pld.requirements, loadedZipSumsOnly) + compatVersion := pld.TidyCompatibleVersion + goVersion := pld.requirements.GoVersion(ld) if compatVersion == "" { if gover.Compare(goVersion, gover.GoStrictVersion) < 0 { compatVersion = gover.Prev(goVersion) @@ -443,32 +435,32 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat // version higher than the go.mod version adds nothing. compatVersion = goVersion } - if compatPruning := pruningForGoVersion(compatVersion); compatPruning != ld.requirements.pruning { - compatRS := newRequirements(loaderstate, compatPruning, ld.requirements.rootModules, ld.requirements.direct) - ld.checkTidyCompatibility(loaderstate, ctx, compatRS, compatVersion) + if compatPruning := pruningForGoVersion(compatVersion); compatPruning != pld.requirements.pruning { + compatRS := newRequirements(ld, compatPruning, pld.requirements.rootModules, pld.requirements.direct) + pld.checkTidyCompatibility(ld, ctx, compatRS, compatVersion) - for m := range keepSums(loaderstate, ctx, ld, compatRS, loadedZipSumsOnly) { + for m := range keepSums(ld, ctx, pld, compatRS, loadedZipSumsOnly) { keep[m] = true } } if opts.TidyDiff { cfg.BuildMod = "readonly" - loaded = ld - loaderstate.requirements = loaded.requirements - currentGoMod, updatedGoMod, _, err := UpdateGoModFromReqs(loaderstate, ctx, WriteOpts{}) + ld.pkgLoader = pld + ld.requirements = ld.pkgLoader.requirements + currentGoMod, updatedGoMod, _, err := UpdateGoModFromReqs(ld, ctx, WriteOpts{}) if err != nil { base.Fatal(err) } goModDiff := diff.Diff("current/go.mod", currentGoMod, "tidy/go.mod", updatedGoMod) - modfetch.TrimGoSum(keep) + ld.Fetcher().TrimGoSum(keep) // Dropping compatibility for 1.16 may result in a strictly smaller go.sum. // Update the keep map with only the loaded.requirements. if gover.Compare(compatVersion, "1.16") > 0 { - keep = keepSums(loaderstate, ctx, loaded, loaderstate.requirements, addBuildListZipSums) + keep = keepSums(ld, ctx, ld.pkgLoader, ld.requirements, addBuildListZipSums) } - currentGoSum, tidyGoSum := modfetch.TidyGoSum(keep) + currentGoSum, tidyGoSum := ld.fetcher.TidyGoSum(keep) goSumDiff := diff.Diff("current/go.sum", currentGoSum, "tidy/go.sum", tidyGoSum) if len(goModDiff) > 0 { @@ -483,14 +475,14 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat } if !ExplicitWriteGoMod { - modfetch.TrimGoSum(keep) + ld.Fetcher().TrimGoSum(keep) // commitRequirements below will also call WriteGoSum, but the "keep" map // we have here could be strictly larger: commitRequirements only commits // loaded.requirements, but here we may have also loaded (and want to // preserve checksums for) additional entities from compatRS, which are // only needed for compatibility with ld.TidyCompatibleVersion. - if err := modfetch.WriteGoSum(ctx, keep, mustHaveCompleteRequirements(loaderstate)); err != nil { + if err := ld.Fetcher().WriteGoSum(ctx, keep, mustHaveCompleteRequirements(ld)); err != nil { base.Fatal(err) } } @@ -504,10 +496,10 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat // We'll skip updating if ExplicitWriteGoMod is true (the caller has opted // to call WriteGoMod itself) or if ResolveMissingImports is false (the // command wants to examine the package graph as-is). - loaded = ld - loaderstate.requirements = loaded.requirements + ld.pkgLoader = pld + ld.requirements = ld.pkgLoader.requirements - for _, pkg := range ld.pkgs { + for _, pkg := range pld.pkgs { if !pkg.isTest() { loadedPackages = append(loadedPackages, pkg.path) } @@ -515,7 +507,7 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat sort.Strings(loadedPackages) if !ExplicitWriteGoMod && opts.ResolveMissingImports { - if err := commitRequirements(loaderstate, ctx, WriteOpts{}); err != nil { + if err := commitRequirements(ld, ctx, WriteOpts{}); err != nil { base.Fatal(err) } } @@ -525,7 +517,7 @@ func LoadPackages(loaderstate *State, ctx context.Context, opts PackageOpts, pat // matchLocalDirs is like m.MatchDirs, but tries to avoid scanning directories // outside of the standard library and active modules. -func matchLocalDirs(loaderstate *State, ctx context.Context, modRoots []string, m *search.Match, rs *Requirements) { +func matchLocalDirs(ld *Loader, ctx context.Context, modRoots []string, m *search.Match, rs *Requirements) { if !m.IsLocal() { panic(fmt.Sprintf("internal error: resolveLocalDirs on non-local pattern %s", m.Pattern())) } @@ -543,10 +535,10 @@ func matchLocalDirs(loaderstate *State, ctx context.Context, modRoots []string, } modRoot := findModuleRoot(absDir) - if !slices.Contains(modRoots, modRoot) && search.InDir(absDir, cfg.GOROOTsrc) == "" && pathInModuleCache(loaderstate, ctx, absDir, rs) == "" { + if !slices.Contains(modRoots, modRoot) && search.InDir(absDir, cfg.GOROOTsrc) == "" && pathInModuleCache(ld, ctx, absDir, rs) == "" { m.Dirs = []string{} scope := "main module or its selected dependencies" - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { scope = "modules listed in go.work or their selected dependencies" } m.AddError(fmt.Errorf("directory prefix %s does not contain %s", base.ShortPath(absDir), scope)) @@ -558,7 +550,7 @@ func matchLocalDirs(loaderstate *State, ctx context.Context, modRoots []string, } // resolveLocalPackage resolves a filesystem path to a package path. -func resolveLocalPackage(loaderstate *State, ctx context.Context, dir string, rs *Requirements) (string, error) { +func resolveLocalPackage(ld *Loader, ctx context.Context, dir string, rs *Requirements) (string, error) { var absDir string if filepath.IsAbs(dir) { absDir = filepath.Clean(dir) @@ -596,13 +588,13 @@ func resolveLocalPackage(loaderstate *State, ctx context.Context, dir string, rs } } - for _, mod := range loaderstate.MainModules.Versions() { - modRoot := loaderstate.MainModules.ModRoot(mod) + for _, mod := range ld.MainModules.Versions() { + modRoot := ld.MainModules.ModRoot(mod) if modRoot != "" && absDir == modRoot { if absDir == cfg.GOROOTsrc { return "", errPkgIsGorootSrc } - return loaderstate.MainModules.PathPrefix(mod), nil + return ld.MainModules.PathPrefix(mod), nil } } @@ -611,8 +603,8 @@ func resolveLocalPackage(loaderstate *State, ctx context.Context, dir string, rs // It's not strictly necessary but helpful to keep the checks. var pkgNotFoundErr error pkgNotFoundLongestPrefix := "" - for _, mainModule := range loaderstate.MainModules.Versions() { - modRoot := loaderstate.MainModules.ModRoot(mainModule) + for _, mainModule := range ld.MainModules.Versions() { + modRoot := ld.MainModules.ModRoot(mainModule) if modRoot != "" && str.HasFilePathPrefix(absDir, modRoot) && !strings.Contains(absDir[len(modRoot):], "@") { suffix := filepath.ToSlash(str.TrimFilePathPrefix(absDir, modRoot)) if pkg, found := strings.CutPrefix(suffix, "vendor/"); found { @@ -620,14 +612,14 @@ func resolveLocalPackage(loaderstate *State, ctx context.Context, dir string, rs return "", fmt.Errorf("without -mod=vendor, directory %s has no package path", absDir) } - readVendorList(VendorDir(loaderstate)) + readVendorList(VendorDir(ld)) if _, ok := vendorPkgModule[pkg]; !ok { return "", fmt.Errorf("directory %s is not a package listed in vendor/modules.txt", absDir) } return pkg, nil } - mainModulePrefix := loaderstate.MainModules.PathPrefix(mainModule) + mainModulePrefix := ld.MainModules.PathPrefix(mainModule) if mainModulePrefix == "" { pkg := suffix if pkg == "builtin" { @@ -668,13 +660,13 @@ func resolveLocalPackage(loaderstate *State, ctx context.Context, dir string, rs return pkg, nil } - pkg := pathInModuleCache(loaderstate, ctx, absDir, rs) + pkg := pathInModuleCache(ld, ctx, absDir, rs) if pkg == "" { dirstr := fmt.Sprintf("directory %s", base.ShortPath(absDir)) if dirstr == "directory ." { dirstr = "current directory" } - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { if mr := findModuleRoot(absDir); mr != "" { return "", fmt.Errorf("%s is contained in a module that is not one of the workspace modules listed in go.work. You can add the module to the workspace using:\n\tgo work use %s", dirstr, base.ShortPath(mr)) } @@ -693,17 +685,17 @@ var ( // pathInModuleCache returns the import path of the directory dir, // if dir is in the module cache copy of a module in our build list. -func pathInModuleCache(loaderstate *State, ctx context.Context, dir string, rs *Requirements) string { +func pathInModuleCache(ld *Loader, ctx context.Context, dir string, rs *Requirements) string { tryMod := func(m module.Version) (string, bool) { if gover.IsToolchain(m.Path) { return "", false } var root string var err error - if repl := Replacement(loaderstate, m); repl.Path != "" && repl.Version == "" { + if repl := Replacement(ld, m); repl.Path != "" && repl.Version == "" { root = repl.Path if !filepath.IsAbs(root) { - root = filepath.Join(replaceRelativeTo(loaderstate), root) + root = filepath.Join(replaceRelativeTo(ld), root) } } else if repl.Path != "" { root, err = modfetch.DownloadDir(ctx, repl) @@ -728,7 +720,7 @@ func pathInModuleCache(loaderstate *State, ctx context.Context, dir string, rs * if rs.pruning == pruned { for _, m := range rs.rootModules { - if v, _ := rs.rootSelected(loaderstate, m.Path); v != m.Version { + if v, _ := rs.rootSelected(ld, m.Path); v != m.Version { continue // m is a root, but we have a higher root for the same path. } if importPath, ok := tryMod(m); ok { @@ -747,7 +739,7 @@ func pathInModuleCache(loaderstate *State, ctx context.Context, dir string, rs * // versions of root modules may differ from what we already checked above. // Re-check those paths too. - mg, _ := rs.Graph(loaderstate, ctx) + mg, _ := rs.Graph(ld, ctx) var importPath string for _, m := range mg.BuildList() { var found bool @@ -766,8 +758,8 @@ func pathInModuleCache(loaderstate *State, ctx context.Context, dir string, rs * // // TODO(bcmills): Silencing errors seems off. Take a closer look at this and // figure out what the error-reporting actually ought to be. -func ImportFromFiles(loaderstate *State, ctx context.Context, gofiles []string) { - rs := LoadModFile(loaderstate, ctx) +func ImportFromFiles(ld *Loader, ctx context.Context, gofiles []string) { + rs := LoadModFile(ld, ctx) tags := imports.Tags() imports, testImports, err := imports.ScanFiles(gofiles, tags) @@ -775,7 +767,7 @@ func ImportFromFiles(loaderstate *State, ctx context.Context, gofiles []string) base.Fatal(err) } - loaded = loadFromRoots(loaderstate, ctx, loaderParams{ + ld.pkgLoader = loadFromRoots(ld, ctx, loaderParams{ PackageOpts: PackageOpts{ Tags: tags, ResolveMissingImports: true, @@ -788,10 +780,10 @@ func ImportFromFiles(loaderstate *State, ctx context.Context, gofiles []string) return roots }, }) - loaderstate.requirements = loaded.requirements + ld.requirements = ld.pkgLoader.requirements if !ExplicitWriteGoMod { - if err := commitRequirements(loaderstate, ctx, WriteOpts{}); err != nil { + if err := commitRequirements(ld, ctx, WriteOpts{}); err != nil { base.Fatal(err) } } @@ -799,11 +791,11 @@ func ImportFromFiles(loaderstate *State, ctx context.Context, gofiles []string) // DirImportPath returns the effective import path for dir, // provided it is within a main module, or else returns ".". -func (mms *MainModuleSet) DirImportPath(loaderstate *State, ctx context.Context, dir string) (path string, m module.Version) { - if !HasModRoot(loaderstate) { +func (mms *MainModuleSet) DirImportPath(ld *Loader, ctx context.Context, dir string) (path string, m module.Version) { + if !ld.HasModRoot() { return ".", module.Version{} } - LoadModFile(loaderstate, ctx) // Sets targetPrefix. + LoadModFile(ld, ctx) // Sets targetPrefix. if !filepath.IsAbs(dir) { dir = filepath.Join(base.Cwd(), dir) @@ -820,7 +812,7 @@ func (mms *MainModuleSet) DirImportPath(loaderstate *State, ctx context.Context, return mms.PathPrefix(v), v } if str.HasFilePathPrefix(dir, modRoot) { - pathPrefix := loaderstate.MainModules.PathPrefix(v) + pathPrefix := ld.MainModules.PathPrefix(v) if pathPrefix > longestPrefix { longestPrefix = pathPrefix longestPrefixVersion = v @@ -841,8 +833,8 @@ func (mms *MainModuleSet) DirImportPath(loaderstate *State, ctx context.Context, } // PackageModule returns the module providing the package named by the import path. -func PackageModule(path string) module.Version { - pkg, ok := loaded.pkgCache.Get(path) +func (ld *Loader) PackageModule(path string) module.Version { + pkg, ok := ld.pkgLoader.pkgCache.Get(path) if !ok { return module.Version{} } @@ -853,15 +845,15 @@ func PackageModule(path string) module.Version { // the package at path as imported from the package in parentDir. // Lookup requires that one of the Load functions in this package has already // been called. -func Lookup(loaderstate *State, parentPath string, parentIsStd bool, path string) (dir, realPath string, err error) { +func Lookup(ld *Loader, parentPath string, parentIsStd bool, path string) (dir, realPath string, err error) { if path == "" { panic("Lookup called with empty package path") } if parentIsStd { - path = loaded.stdVendor(loaderstate, parentPath, path) + path = ld.pkgLoader.stdVendor(ld, parentPath, path) } - pkg, ok := loaded.pkgCache.Get(path) + pkg, ok := ld.pkgLoader.pkgCache.Get(path) if !ok { // The loader should have found all the relevant paths. // There are a few exceptions, though: @@ -880,11 +872,11 @@ func Lookup(loaderstate *State, parentPath string, parentIsStd bool, path string return pkg.dir, pkg.path, pkg.err } -// A loader manages the process of loading information about +// A packageLoader manages the process of loading information about // the required packages for a particular build, // checking that the packages are available in the module set, // and updating the module set if needed. -type loader struct { +type packageLoader struct { loaderParams // allClosesOverTests indicates whether the "all" pattern includes @@ -916,52 +908,52 @@ type loaderParams struct { listRoots func(rs *Requirements) []string } -func (ld *loader) reset() { +func (pld *packageLoader) reset() { select { - case <-ld.work.Idle(): + case <-pld.work.Idle(): default: panic("loader.reset when not idle") } - ld.roots = nil - ld.pkgCache = new(par.Cache[string, *loadPkg]) - ld.pkgs = nil + pld.roots = nil + pld.pkgCache = new(par.Cache[string, *loadPkg]) + pld.pkgs = nil } // error reports an error via either os.Stderr or base.Error, // according to whether ld.AllowErrors is set. -func (ld *loader) error(err error) { - if ld.AllowErrors { +func (pld *packageLoader) error(err error) { + if pld.AllowErrors { fmt.Fprintf(os.Stderr, "go: %v\n", err) - } else if ld.Switcher != nil { - ld.Switcher.Error(err) + } else if pld.Switcher != nil { + pld.Switcher.Error(err) } else { base.Error(err) } } // switchIfErrors switches toolchains if a switch is needed. -func (ld *loader) switchIfErrors(ctx context.Context) { - if ld.Switcher != nil { - ld.Switcher.Switch(ctx) +func (pld *packageLoader) switchIfErrors(ctx context.Context) { + if pld.Switcher != nil { + pld.Switcher.Switch(ctx) } } // exitIfErrors switches toolchains if a switch is needed // or else exits if any errors have been reported. -func (ld *loader) exitIfErrors(ctx context.Context) { - ld.switchIfErrors(ctx) +func (pld *packageLoader) exitIfErrors(ctx context.Context) { + pld.switchIfErrors(ctx) base.ExitIfErrors() } // goVersion reports the Go version that should be used for the loader's // requirements: ld.TidyGoVersion if set, or ld.requirements.GoVersion() // otherwise. -func (ld *loader) goVersion(loaderstate *State) string { - if ld.TidyGoVersion != "" { - return ld.TidyGoVersion +func (pld *packageLoader) goVersion(ld *Loader) string { + if pld.TidyGoVersion != "" { + return pld.TidyGoVersion } - return ld.requirements.GoVersion(loaderstate) + return pld.requirements.GoVersion(ld) } // A loadPkg records information about a single loaded package. @@ -970,10 +962,10 @@ type loadPkg struct { path string // import path testOf *loadPkg - // Populated at construction time and updated by (*loader).applyPkgFlags: + // Populated at construction time and updated by (*packageLoader).applyPkgFlags: flags atomicLoadPkgFlags - // Populated by (*loader).load: + // Populated by (*packageLoader).load: mod module.Version // module providing package dir string // directory containing source code err error // error loading package @@ -982,11 +974,11 @@ type loadPkg struct { inStd bool altMods []module.Version // modules that could have contained the package but did not - // Populated by (*loader).pkgTest: + // Populated by (*packageLoader).pkgTest: testOnce sync.Once test *loadPkg - // Populated by postprocessing in (*loader).buildStacks: + // Populated by postprocessing in (*packageLoader).buildStacks: stack *loadPkg // package importing this one in minimal import stack for this pkg } @@ -1064,11 +1056,11 @@ func (pkg *loadPkg) isTest() bool { // fromExternalModule reports whether pkg was loaded from a module other than // the main module. -func (pkg *loadPkg) fromExternalModule(loaderstate *State) bool { +func (pkg *loadPkg) fromExternalModule(ld *Loader) bool { if pkg.mod.Path == "" { return false // loaded from the standard library, not a module } - return !loaderstate.MainModules.Contains(pkg.mod.Path) + return !ld.MainModules.Contains(pkg.mod.Path) } var errMissing = errors.New("cannot find package") @@ -1079,13 +1071,13 @@ var errMissing = errors.New("cannot find package") // The set of root packages is returned by the params.listRoots function, and // expanded to the full set of packages by tracing imports (and possibly tests) // as needed. -func loadFromRoots(loaderstate *State, ctx context.Context, params loaderParams) *loader { - ld := &loader{ +func loadFromRoots(ld *Loader, ctx context.Context, params loaderParams) *packageLoader { + pld := &packageLoader{ loaderParams: params, work: par.NewQueue(runtime.GOMAXPROCS(0)), } - if ld.requirements.pruning == unpruned { + if pld.requirements.pruning == unpruned { // If the module graph does not support pruning, we assume that we will need // the full module graph in order to load package dependencies. // @@ -1095,53 +1087,53 @@ func loadFromRoots(loaderstate *State, ctx context.Context, params loaderParams) // spot-checks in modules that do not maintain the expanded go.mod // requirements needed for graph pruning. var err error - ld.requirements, _, err = expandGraph(loaderstate, ctx, ld.requirements) + pld.requirements, _, err = expandGraph(ld, ctx, pld.requirements) if err != nil { - ld.error(err) + pld.error(err) } } - ld.exitIfErrors(ctx) + pld.exitIfErrors(ctx) updateGoVersion := func() { - goVersion := ld.goVersion(loaderstate) + goVersion := pld.goVersion(ld) - if ld.requirements.pruning != workspace { + if pld.requirements.pruning != workspace { var err error - ld.requirements, err = convertPruning(loaderstate, ctx, ld.requirements, pruningForGoVersion(goVersion)) + pld.requirements, err = convertPruning(ld, ctx, pld.requirements, pruningForGoVersion(goVersion)) if err != nil { - ld.error(err) - ld.exitIfErrors(ctx) + pld.error(err) + pld.exitIfErrors(ctx) } } // If the module's Go version omits go.sum entries for go.mod files for test // dependencies of external packages, avoid loading those files in the first // place. - ld.skipImportModFiles = ld.Tidy && gover.Compare(goVersion, gover.TidyGoModSumVersion) < 0 + pld.skipImportModFiles = pld.Tidy && gover.Compare(goVersion, gover.TidyGoModSumVersion) < 0 // If the module's go version explicitly predates the change in "all" for // graph pruning, continue to use the older interpretation. - ld.allClosesOverTests = gover.Compare(goVersion, gover.NarrowAllVersion) < 0 && !ld.UseVendorAll + pld.allClosesOverTests = gover.Compare(goVersion, gover.NarrowAllVersion) < 0 && !pld.UseVendorAll } for { - ld.reset() + pld.reset() updateGoVersion() // Load the root packages and their imports. // Note: the returned roots can change on each iteration, // since the expansion of package patterns depends on the // build list we're using. - rootPkgs := ld.listRoots(ld.requirements) + rootPkgs := pld.listRoots(pld.requirements) - if ld.requirements.pruning == pruned && cfg.BuildMod == "mod" { + if pld.requirements.pruning == pruned && cfg.BuildMod == "mod" { // Before we start loading transitive imports of packages, locate all of // the root packages and promote their containing modules to root modules // dependencies. If their go.mod files are tidy (the common case) and the // set of root packages does not change then we can select the correct // versions of all transitive imports on the first try and complete // loading in a single iteration. - changedBuildList := ld.preloadRootModules(loaderstate, ctx, rootPkgs) + changedBuildList := pld.preloadRootModules(ld, ctx, rootPkgs) if changedBuildList { // The build list has changed, so the set of root packages may have also // changed. Start over to pick up the changes. (Preloading roots is much @@ -1154,9 +1146,9 @@ func loadFromRoots(loaderstate *State, ctx context.Context, params loaderParams) inRoots := map[*loadPkg]bool{} for _, path := range rootPkgs { - root := ld.pkg(loaderstate, ctx, path, pkgIsRoot) + root := pld.pkg(ld, ctx, path, pkgIsRoot) if !inRoots[root] { - ld.roots = append(ld.roots, root) + pld.roots = append(pld.roots, root) inRoots[root] = true } } @@ -1166,13 +1158,13 @@ func loadFromRoots(loaderstate *State, ctx context.Context, params loaderParams) // // When all of the work in the queue has completed, we'll know that the // transitive closure of dependencies has been loaded. - <-ld.work.Idle() + <-pld.work.Idle() - ld.buildStacks() + pld.buildStacks() - changed, err := ld.updateRequirements(loaderstate, ctx) + changed, err := pld.updateRequirements(ld, ctx) if err != nil { - ld.error(err) + pld.error(err) break } if changed { @@ -1184,14 +1176,14 @@ func loadFromRoots(loaderstate *State, ctx context.Context, params loaderParams) continue } - if !ld.ResolveMissingImports || (!HasModRoot(loaderstate) && !allowMissingModuleImports) { + if !pld.ResolveMissingImports || (!ld.HasModRoot() && !ld.allowMissingModuleImports) { // We've loaded as much as we can without resolving missing imports. break } - modAddedBy, err := ld.resolveMissingImports(loaderstate, ctx) + modAddedBy, err := pld.resolveMissingImports(ld, ctx) if err != nil { - ld.error(err) + pld.error(err) break } if len(modAddedBy) == 0 { @@ -1215,66 +1207,66 @@ func loadFromRoots(loaderstate *State, ctx context.Context, params loaderParams) // We also know that we're going to call updateRequirements again next // iteration so we don't need to also update it here. (That would waste time // computing a "direct" map that we'll have to recompute later anyway.) - direct := ld.requirements.direct - rs, err := updateRoots(loaderstate, ctx, direct, ld.requirements, noPkgs, toAdd, ld.AssumeRootsImported) + direct := pld.requirements.direct + rs, err := updateRoots(ld, ctx, direct, pld.requirements, noPkgs, toAdd, pld.AssumeRootsImported) if err != nil { // If an error was found in a newly added module, report the package // import stack instead of the module requirement stack. Packages // are more descriptive. if err, ok := err.(*mvs.BuildListError); ok { if pkg := modAddedBy[err.Module()]; pkg != nil { - ld.error(fmt.Errorf("%s: %w", pkg.stackText(), err.Err)) + pld.error(fmt.Errorf("%s: %w", pkg.stackText(), err.Err)) break } } - ld.error(err) + pld.error(err) break } - if slices.Equal(rs.rootModules, ld.requirements.rootModules) { + if slices.Equal(rs.rootModules, pld.requirements.rootModules) { // Something is deeply wrong. resolveMissingImports gave us a non-empty // set of modules to add to the graph, but adding those modules had no // effect — either they were already in the graph, or updateRoots did not // add them as requested. panic(fmt.Sprintf("internal error: adding %v to module graph had no effect on root requirements (%v)", toAdd, rs.rootModules)) } - ld.requirements = rs + pld.requirements = rs } - ld.exitIfErrors(ctx) + pld.exitIfErrors(ctx) // Tidy the build list, if applicable, before we report errors. // (The process of tidying may remove errors from irrelevant dependencies.) - if ld.Tidy { - rs, err := tidyRoots(loaderstate, ctx, ld.requirements, ld.pkgs) + if pld.Tidy { + rs, err := tidyRoots(ld, ctx, pld.requirements, pld.pkgs) if err != nil { - ld.error(err) + pld.error(err) } else { - if ld.TidyGoVersion != "" { + if pld.TidyGoVersion != "" { // Attempt to switch to the requested Go version. We have been using its // pruning and semantics all along, but there may have been — and may // still be — requirements on higher versions in the graph. - tidy := overrideRoots(loaderstate, ctx, rs, []module.Version{{Path: "go", Version: ld.TidyGoVersion}}) - mg, err := tidy.Graph(loaderstate, ctx) + tidy := overrideRoots(ld, ctx, rs, []module.Version{{Path: "go", Version: pld.TidyGoVersion}}) + mg, err := tidy.Graph(ld, ctx) if err != nil { - ld.error(err) + pld.error(err) } - if v := mg.Selected("go"); v == ld.TidyGoVersion { + if v := mg.Selected("go"); v == pld.TidyGoVersion { rs = tidy } else { conflict := Conflict{ Path: mg.g.FindPath(func(m module.Version) bool { return m.Path == "go" && m.Version == v })[1:], - Constraint: module.Version{Path: "go", Version: ld.TidyGoVersion}, + Constraint: module.Version{Path: "go", Version: pld.TidyGoVersion}, } msg := conflict.Summary() if cfg.BuildV { msg = conflict.String() } - ld.error(errors.New(msg)) + pld.error(errors.New(msg)) } } - if ld.requirements.pruning == pruned { + if pld.requirements.pruning == pruned { // We continuously add tidy roots to ld.requirements during loading, so // at this point the tidy roots (other than possibly the "go" version // edited above) should be a subset of the roots of ld.requirements, @@ -1282,23 +1274,23 @@ func loadFromRoots(loaderstate *State, ctx context.Context, params loaderParams) // graph-pruning horizon. // If that is not the case, there is a bug in the loading loop above. for _, m := range rs.rootModules { - if m.Path == "go" && ld.TidyGoVersion != "" { + if m.Path == "go" && pld.TidyGoVersion != "" { continue } - if v, ok := ld.requirements.rootSelected(loaderstate, m.Path); !ok || v != m.Version { - ld.error(fmt.Errorf("internal error: a requirement on %v is needed but was not added during package loading (selected %s)", m, v)) + if v, ok := pld.requirements.rootSelected(ld, m.Path); !ok || v != m.Version { + pld.error(fmt.Errorf("internal error: a requirement on %v is needed but was not added during package loading (selected %s)", m, v)) } } } - ld.requirements = rs + pld.requirements = rs } - ld.exitIfErrors(ctx) + pld.exitIfErrors(ctx) } // Report errors, if any. - for _, pkg := range ld.pkgs { + for _, pkg := range pld.pkgs { if pkg.err == nil { continue } @@ -1320,22 +1312,22 @@ func loadFromRoots(loaderstate *State, ctx context.Context, params loaderParams) stdErr.importerGoVersion = v.(string) } } - if ld.SilenceMissingStdImports { + if pld.SilenceMissingStdImports { continue } } - if ld.SilencePackageErrors { + if pld.SilencePackageErrors { continue } - if ld.SilenceNoGoErrors && errors.Is(pkg.err, imports.ErrNoGo) { + if pld.SilenceNoGoErrors && errors.Is(pkg.err, imports.ErrNoGo) { continue } - ld.error(fmt.Errorf("%s: %w", pkg.stackText(), pkg.err)) + pld.error(fmt.Errorf("%s: %w", pkg.stackText(), pkg.err)) } - ld.checkMultiplePaths(loaderstate) - return ld + pld.checkMultiplePaths(ld) + return pld } // updateRequirements ensures that ld.requirements is consistent with the @@ -1357,8 +1349,8 @@ func loadFromRoots(loaderstate *State, ctx context.Context, params loaderParams) // The "changed" return value reports whether the update changed the selected // version of any module that either provided a loaded package or may now // provide a package that was previously unresolved. -func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (changed bool, err error) { - rs := ld.requirements +func (pld *packageLoader) updateRequirements(ld *Loader, ctx context.Context) (changed bool, err error) { + rs := pld.requirements // direct contains the set of modules believed to provide packages directly // imported by the main module. @@ -1368,7 +1360,7 @@ func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (c // imports.AnyTags, then we didn't necessarily load every package that // contributes “direct” imports — so we can't safely mark existing direct // dependencies in ld.requirements as indirect-only. Propagate them as direct. - loadedDirect := ld.allPatternIsRoot && maps.Equal(ld.Tags, imports.AnyTags()) + loadedDirect := pld.allPatternIsRoot && maps.Equal(pld.Tags, imports.AnyTags()) if loadedDirect { direct = make(map[string]bool) } else { @@ -1382,7 +1374,7 @@ func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (c } var maxTooNew *gover.TooNewError - for _, pkg := range ld.pkgs { + for _, pkg := range pld.pkgs { if pkg.err != nil { if tooNew, ok := errors.AsType[*gover.TooNewError](pkg.err); ok { if maxTooNew == nil || gover.Compare(tooNew.GoVersion, maxTooNew.GoVersion) > 0 { @@ -1390,16 +1382,16 @@ func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (c } } } - if pkg.mod.Version != "" || !loaderstate.MainModules.Contains(pkg.mod.Path) { + if pkg.mod.Version != "" || !ld.MainModules.Contains(pkg.mod.Path) { continue } for _, dep := range pkg.imports { - if !dep.fromExternalModule(loaderstate) { + if !dep.fromExternalModule(ld) { continue } - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { // In workspace mode / workspace pruning mode, the roots are the main modules // rather than the main module's direct dependencies. The check below on the selected // roots does not apply. @@ -1412,7 +1404,7 @@ func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (c // of the vendor directory anyway. continue } - if mg, err := rs.Graph(loaderstate, ctx); err != nil { + if mg, err := rs.Graph(ld, ctx); err != nil { return false, err } else if _, ok := mg.RequiredBy(dep.mod); !ok { // dep.mod is not an explicit dependency, but needs to be. @@ -1424,7 +1416,7 @@ func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (c } } } else if pkg.err == nil && cfg.BuildMod != "mod" { - if v, ok := rs.rootSelected(loaderstate, dep.mod.Path); !ok || v != dep.mod.Version { + if v, ok := rs.rootSelected(ld, dep.mod.Path); !ok || v != dep.mod.Version { // dep.mod is not an explicit dependency, but needs to be. // Because we are not in "mod" mode, we will not be able to update it. // Instead, mark the importing package with an error. @@ -1455,7 +1447,7 @@ func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (c } var addRoots []module.Version - if ld.Tidy { + if pld.Tidy { // When we are tidying a module with a pruned dependency graph, we may need // to add roots to preserve the versions of indirect, test-only dependencies // that are upgraded above or otherwise missing from the go.mod files of @@ -1490,37 +1482,37 @@ func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (c // roots can only increase and the set of roots can only expand. The set // of extant root paths is finite and the set of versions of each path is // finite, so the iteration *must* reach a stable fixed-point. - tidy, err := tidyRoots(loaderstate, ctx, rs, ld.pkgs) + tidy, err := tidyRoots(ld, ctx, rs, pld.pkgs) if err != nil { return false, err } addRoots = tidy.rootModules } - rs, err = updateRoots(loaderstate, ctx, direct, rs, ld.pkgs, addRoots, ld.AssumeRootsImported) + rs, err = updateRoots(ld, ctx, direct, rs, pld.pkgs, addRoots, pld.AssumeRootsImported) if err != nil { // We don't actually know what even the root requirements are supposed to be, // so we can't proceed with loading. Return the error to the caller return false, err } - if rs.GoVersion(loaderstate) != ld.requirements.GoVersion(loaderstate) { + if rs.GoVersion(ld) != pld.requirements.GoVersion(ld) { // A change in the selected Go version may or may not affect the set of // loaded packages, but in some cases it can change the meaning of the "all" // pattern, the level of pruning in the module graph, and even the set of // packages present in the standard library. If it has changed, it's best to // reload packages once more to be sure everything is stable. changed = true - } else if rs != ld.requirements && !slices.Equal(rs.rootModules, ld.requirements.rootModules) { + } else if rs != pld.requirements && !slices.Equal(rs.rootModules, pld.requirements.rootModules) { // The roots of the module graph have changed in some way (not just the // "direct" markings). Check whether the changes affected any of the loaded // packages. - mg, err := rs.Graph(loaderstate, ctx) + mg, err := rs.Graph(ld, ctx) if err != nil { return false, err } - for _, pkg := range ld.pkgs { - if pkg.fromExternalModule(loaderstate) && mg.Selected(pkg.mod.Path) != pkg.mod.Version { + for _, pkg := range pld.pkgs { + if pkg.fromExternalModule(ld) && mg.Selected(pkg.mod.Path) != pkg.mod.Version { changed = true break } @@ -1540,7 +1532,7 @@ func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (c // // In some sense, we can think of this as ‘upgraded the module providing // pkg.path from "none" to a version higher than "none"’. - if _, _, _, _, err = importFromModules(loaderstate, ctx, pkg.path, rs, nil, ld.skipImportModFiles); err == nil { + if _, _, _, _, err = importFromModules(ld, ctx, pkg.path, rs, nil, pld.skipImportModFiles); err == nil { changed = true break } @@ -1548,7 +1540,7 @@ func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (c } } - ld.requirements = rs + pld.requirements = rs return changed, nil } @@ -1558,13 +1550,13 @@ func (ld *loader) updateRequirements(loaderstate *State, ctx context.Context) (c // The newly-resolved packages are added to the addedModuleFor map, and // resolveMissingImports returns a map from each new module version to // the first missing package that module would resolve. -func (ld *loader) resolveMissingImports(loaderstate *State, ctx context.Context) (modAddedBy map[module.Version]*loadPkg, err error) { +func (pld *packageLoader) resolveMissingImports(ld *Loader, ctx context.Context) (modAddedBy map[module.Version]*loadPkg, err error) { type pkgMod struct { pkg *loadPkg mod *module.Version } var pkgMods []pkgMod - for _, pkg := range ld.pkgs { + for _, pkg := range pld.pkgs { if pkg.err == nil { continue } @@ -1580,15 +1572,15 @@ func (ld *loader) resolveMissingImports(loaderstate *State, ctx context.Context) pkg := pkg var mod module.Version - ld.work.Add(func() { + pld.work.Add(func() { var err error - mod, err = queryImport(loaderstate, ctx, pkg.path, ld.requirements) + mod, err = queryImport(ld, ctx, pkg.path, pld.requirements) if err != nil { if ime, ok := errors.AsType[*ImportMissingError](err); ok { for curstack := pkg.stack; curstack != nil; curstack = curstack.stack { - if loaderstate.MainModules.Contains(curstack.mod.Path) { + if ld.MainModules.Contains(curstack.mod.Path) { ime.ImportingMainModule = curstack.mod - ime.modRoot = loaderstate.MainModules.ModRoot(ime.ImportingMainModule) + ime.modRoot = ld.MainModules.ModRoot(ime.ImportingMainModule) break } } @@ -1616,7 +1608,7 @@ func (ld *loader) resolveMissingImports(loaderstate *State, ctx context.Context) pkgMods = append(pkgMods, pkgMod{pkg: pkg, mod: &mod}) } - <-ld.work.Idle() + <-pld.work.Idle() modAddedBy = map[module.Version]*loadPkg{} @@ -1659,34 +1651,34 @@ func (ld *loader) resolveMissingImports(loaderstate *State, ctx context.Context) // ld.work queue, and its test (if requested) will also be populated once // imports have been resolved. When ld.work goes idle, all transitive imports of // the requested package (and its test, if requested) will have been loaded. -func (ld *loader) pkg(loaderstate *State, ctx context.Context, path string, flags loadPkgFlags) *loadPkg { +func (pld *packageLoader) pkg(ld *Loader, ctx context.Context, path string, flags loadPkgFlags) *loadPkg { if flags.has(pkgImportsLoaded) { - panic("internal error: (*loader).pkg called with pkgImportsLoaded flag set") + panic("internal error: (*packageLoader).pkg called with pkgImportsLoaded flag set") } - pkg := ld.pkgCache.Do(path, func() *loadPkg { + pkg := pld.pkgCache.Do(path, func() *loadPkg { pkg := &loadPkg{ path: path, } - ld.applyPkgFlags(loaderstate, ctx, pkg, flags) + pld.applyPkgFlags(ld, ctx, pkg, flags) - ld.work.Add(func() { ld.load(loaderstate, ctx, pkg) }) + pld.work.Add(func() { pld.load(ld, ctx, pkg) }) return pkg }) - ld.applyPkgFlags(loaderstate, ctx, pkg, flags) + pld.applyPkgFlags(ld, ctx, pkg, flags) return pkg } // applyPkgFlags updates pkg.flags to set the given flags and propagate the // (transitive) effects of those flags, possibly loading or enqueueing further // packages as a result. -func (ld *loader) applyPkgFlags(loaderstate *State, ctx context.Context, pkg *loadPkg, flags loadPkgFlags) { +func (pld *packageLoader) applyPkgFlags(ld *Loader, ctx context.Context, pkg *loadPkg, flags loadPkgFlags) { if flags == 0 { return } - if flags.has(pkgInAll) && ld.allPatternIsRoot && !pkg.isTest() { + if flags.has(pkgInAll) && pld.allPatternIsRoot && !pkg.isTest() { // This package matches a root pattern by virtue of being in "all". flags |= pkgIsRoot } @@ -1709,7 +1701,7 @@ func (ld *loader) applyPkgFlags(loaderstate *State, ctx context.Context, pkg *lo // so it's ok if we call it more than is strictly necessary. wantTest := false switch { - case ld.allPatternIsRoot && loaderstate.MainModules.Contains(pkg.mod.Path): + case pld.allPatternIsRoot && ld.MainModules.Contains(pkg.mod.Path): // We are loading the "all" pattern, which includes packages imported by // tests in the main module. This package is in the main module, so we // need to identify the imports of its test even if LoadTests is not set. @@ -1717,26 +1709,26 @@ func (ld *loader) applyPkgFlags(loaderstate *State, ctx context.Context, pkg *lo // (We will filter out the extra tests explicitly in computePatternAll.) wantTest = true - case ld.allPatternIsRoot && ld.allClosesOverTests && new.has(pkgInAll): + case pld.allPatternIsRoot && pld.allClosesOverTests && new.has(pkgInAll): // This variant of the "all" pattern includes imports of tests of every // package that is itself in "all", and pkg is in "all", so its test is // also in "all" (as above). wantTest = true - case ld.LoadTests && new.has(pkgIsRoot): + case pld.LoadTests && new.has(pkgIsRoot): // LoadTest explicitly requests tests of “the root packages”. wantTest = true } if wantTest { var testFlags loadPkgFlags - if loaderstate.MainModules.Contains(pkg.mod.Path) || (ld.allClosesOverTests && new.has(pkgInAll)) { + if ld.MainModules.Contains(pkg.mod.Path) || (pld.allClosesOverTests && new.has(pkgInAll)) { // Tests of packages in the main module are in "all", in the sense that // they cause the packages they import to also be in "all". So are tests // of packages in "all" if "all" closes over test dependencies. testFlags |= pkgInAll } - ld.pkgTest(loaderstate, ctx, pkg, testFlags) + pld.pkgTest(ld, ctx, pkg, testFlags) } } @@ -1744,13 +1736,13 @@ func (ld *loader) applyPkgFlags(loaderstate *State, ctx context.Context, pkg *lo // We have just marked pkg with pkgInAll, or we have just loaded its // imports, or both. Now is the time to propagate pkgInAll to the imports. for _, dep := range pkg.imports { - ld.applyPkgFlags(loaderstate, ctx, dep, pkgInAll) + pld.applyPkgFlags(ld, ctx, dep, pkgInAll) } } if new.has(pkgFromRoot) && !old.has(pkgFromRoot|pkgImportsLoaded) { for _, dep := range pkg.imports { - ld.applyPkgFlags(loaderstate, ctx, dep, pkgFromRoot) + pld.applyPkgFlags(ld, ctx, dep, pkgFromRoot) } } } @@ -1758,23 +1750,23 @@ func (ld *loader) applyPkgFlags(loaderstate *State, ctx context.Context, pkg *lo // preloadRootModules loads the module requirements needed to identify the // selected version of each module providing a package in rootPkgs, // adding new root modules to the module graph if needed. -func (ld *loader) preloadRootModules(loaderstate *State, ctx context.Context, rootPkgs []string) (changedBuildList bool) { +func (pld *packageLoader) preloadRootModules(ld *Loader, ctx context.Context, rootPkgs []string) (changedBuildList bool) { needc := make(chan map[module.Version]bool, 1) needc <- map[module.Version]bool{} for _, path := range rootPkgs { path := path - ld.work.Add(func() { + pld.work.Add(func() { // First, try to identify the module containing the package using only roots. // // If the main module is tidy and the package is in "all" — or if we're // lucky — we can identify all of its imports without actually loading the // full module graph. - m, _, _, _, err := importFromModules(loaderstate, ctx, path, ld.requirements, nil, ld.skipImportModFiles) + m, _, _, _, err := importFromModules(ld, ctx, path, pld.requirements, nil, pld.skipImportModFiles) if err != nil { - if _, ok := errors.AsType[*ImportMissingError](err); ok && ld.ResolveMissingImports { + if _, ok := errors.AsType[*ImportMissingError](err); ok && pld.ResolveMissingImports { // This package isn't provided by any selected module. // If we can find it, it will be a new root dependency. - m, err = queryImport(loaderstate, ctx, path, ld.requirements) + m, err = queryImport(ld, ctx, path, pld.requirements) } if err != nil { // We couldn't identify the root module containing this package. @@ -1787,7 +1779,7 @@ func (ld *loader) preloadRootModules(loaderstate *State, ctx context.Context, ro return } - v, ok := ld.requirements.rootSelected(loaderstate, m.Path) + v, ok := pld.requirements.rootSelected(ld, m.Path) if !ok || v != m.Version { // We found the requested package in m, but m is not a root, so // loadModGraph will not load its requirements. We need to promote the @@ -1802,7 +1794,7 @@ func (ld *loader) preloadRootModules(loaderstate *State, ctx context.Context, ro } }) } - <-ld.work.Idle() + <-pld.work.Idle() need := <-needc if len(need) == 0 { @@ -1815,16 +1807,16 @@ func (ld *loader) preloadRootModules(loaderstate *State, ctx context.Context, ro } gover.ModSort(toAdd) - rs, err := updateRoots(loaderstate, ctx, ld.requirements.direct, ld.requirements, nil, toAdd, ld.AssumeRootsImported) + rs, err := updateRoots(ld, ctx, pld.requirements.direct, pld.requirements, nil, toAdd, pld.AssumeRootsImported) if err != nil { // We are missing some root dependency, and for some reason we can't load // enough of the module dependency graph to add the missing root. Package // loading is doomed to fail, so fail quickly. - ld.error(err) - ld.exitIfErrors(ctx) + pld.error(err) + pld.exitIfErrors(ctx) return false } - if slices.Equal(rs.rootModules, ld.requirements.rootModules) { + if slices.Equal(rs.rootModules, pld.requirements.rootModules) { // Something is deeply wrong. resolveMissingImports gave us a non-empty // set of modules to add to the graph, but adding those modules had no // effect — either they were already in the graph, or updateRoots did not @@ -1832,16 +1824,16 @@ func (ld *loader) preloadRootModules(loaderstate *State, ctx context.Context, ro panic(fmt.Sprintf("internal error: adding %v to module graph had no effect on root requirements (%v)", toAdd, rs.rootModules)) } - ld.requirements = rs + pld.requirements = rs return true } // load loads an individual package. -func (ld *loader) load(loaderstate *State, ctx context.Context, pkg *loadPkg) { +func (pld *packageLoader) load(ld *Loader, ctx context.Context, pkg *loadPkg) { var mg *ModuleGraph - if ld.requirements.pruning == unpruned { + if pld.requirements.pruning == unpruned { var err error - mg, err = ld.requirements.Graph(loaderstate, ctx) + mg, err = pld.requirements.Graph(ld, ctx) if err != nil { // We already checked the error from Graph in loadFromRoots and/or // updateRequirements, so we ignored the error on purpose and we should @@ -1856,17 +1848,17 @@ func (ld *loader) load(loaderstate *State, ctx context.Context, pkg *loadPkg) { } var modroot string - pkg.mod, modroot, pkg.dir, pkg.altMods, pkg.err = importFromModules(loaderstate, ctx, pkg.path, ld.requirements, mg, ld.skipImportModFiles) - if loaderstate.MainModules.Tools()[pkg.path] { + pkg.mod, modroot, pkg.dir, pkg.altMods, pkg.err = importFromModules(ld, ctx, pkg.path, pld.requirements, mg, pld.skipImportModFiles) + if ld.MainModules.Tools()[pkg.path] { // Tools declared by main modules are always in "all". // We apply the package flags before returning so that missing // tool dependencies report an error https://go.dev/issue/70582 - ld.applyPkgFlags(loaderstate, ctx, pkg, pkgInAll) + pld.applyPkgFlags(ld, ctx, pkg, pkgInAll) } if pkg.dir == "" { return } - if loaderstate.MainModules.Contains(pkg.mod.Path) { + if ld.MainModules.Contains(pkg.mod.Path) { // Go ahead and mark pkg as in "all". This provides the invariant that a // package that is *only* imported by other packages in "all" is always // marked as such before loading its imports. @@ -1876,10 +1868,10 @@ func (ld *loader) load(loaderstate *State, ctx context.Context, pkg *loadPkg) { // about (by reducing churn on the flag bits of dependencies), and costs // essentially nothing (these atomic flag ops are essentially free compared // to scanning source code for imports). - ld.applyPkgFlags(loaderstate, ctx, pkg, pkgInAll) + pld.applyPkgFlags(ld, ctx, pkg, pkgInAll) } - if ld.AllowPackage != nil { - if err := ld.AllowPackage(ctx, pkg.path, pkg.mod); err != nil { + if pld.AllowPackage != nil { + if err := pld.AllowPackage(ctx, pkg.path, pkg.mod); err != nil { pkg.err = err } } @@ -1892,7 +1884,7 @@ func (ld *loader) load(loaderstate *State, ctx context.Context, pkg *loadPkg) { // We can't scan standard packages for gccgo. } else { var err error - imports, testImports, err = scanDir(modroot, pkg.dir, ld.Tags) + imports, testImports, err = scanDir(modroot, pkg.dir, pld.Tags) if err != nil { pkg.err = err return @@ -1908,13 +1900,13 @@ func (ld *loader) load(loaderstate *State, ctx context.Context, pkg *loadPkg) { if pkg.inStd { // Imports from packages in "std" and "cmd" should resolve using // GOROOT/src/vendor even when "std" is not the main module. - path = ld.stdVendor(loaderstate, pkg.path, path) + path = pld.stdVendor(ld, pkg.path, path) } - pkg.imports = append(pkg.imports, ld.pkg(loaderstate, ctx, path, importFlags)) + pkg.imports = append(pkg.imports, pld.pkg(ld, ctx, path, importFlags)) } pkg.testImports = testImports - ld.applyPkgFlags(loaderstate, ctx, pkg, pkgImportsLoaded) + pld.applyPkgFlags(ld, ctx, pkg, pkgImportsLoaded) } // pkgTest locates the test of pkg, creating it if needed, and updates its state @@ -1922,7 +1914,7 @@ func (ld *loader) load(loaderstate *State, ctx context.Context, pkg *loadPkg) { // // pkgTest requires that the imports of pkg have already been loaded (flagged // with pkgImportsLoaded). -func (ld *loader) pkgTest(loaderstate *State, ctx context.Context, pkg *loadPkg, testFlags loadPkgFlags) *loadPkg { +func (pld *packageLoader) pkgTest(ld *Loader, ctx context.Context, pkg *loadPkg, testFlags loadPkgFlags) *loadPkg { if pkg.isTest() { panic("pkgTest called on a test package") } @@ -1937,7 +1929,7 @@ func (ld *loader) pkgTest(loaderstate *State, ctx context.Context, pkg *loadPkg, err: pkg.err, inStd: pkg.inStd, } - ld.applyPkgFlags(loaderstate, ctx, pkg.test, testFlags) + pld.applyPkgFlags(ld, ctx, pkg.test, testFlags) createdTest = true }) @@ -1950,14 +1942,14 @@ func (ld *loader) pkgTest(loaderstate *State, ctx context.Context, pkg *loadPkg, } for _, path := range pkg.testImports { if pkg.inStd { - path = ld.stdVendor(loaderstate, test.path, path) + path = pld.stdVendor(ld, test.path, path) } - test.imports = append(test.imports, ld.pkg(loaderstate, ctx, path, importFlags)) + test.imports = append(test.imports, pld.pkg(ld, ctx, path, importFlags)) } pkg.testImports = nil - ld.applyPkgFlags(loaderstate, ctx, test, pkgImportsLoaded) + pld.applyPkgFlags(ld, ctx, test, pkgImportsLoaded) } else { - ld.applyPkgFlags(loaderstate, ctx, test, testFlags) + pld.applyPkgFlags(ld, ctx, test, testFlags) } return test @@ -1965,7 +1957,7 @@ func (ld *loader) pkgTest(loaderstate *State, ctx context.Context, pkg *loadPkg, // stdVendor returns the canonical import path for the package with the given // path when imported from the standard-library package at parentPath. -func (ld *loader) stdVendor(loaderstate *State, parentPath, path string) string { +func (pld *packageLoader) stdVendor(ld *Loader, parentPath, path string) string { if p, _, ok := fips140.ResolveImport(path); ok { return p } @@ -1974,14 +1966,14 @@ func (ld *loader) stdVendor(loaderstate *State, parentPath, path string) string } if str.HasPathPrefix(parentPath, "cmd") { - if !ld.VendorModulesInGOROOTSrc || !loaderstate.MainModules.Contains("cmd") { + if !pld.VendorModulesInGOROOTSrc || !ld.MainModules.Contains("cmd") { vendorPath := pathpkg.Join("cmd", "vendor", path) if _, err := os.Stat(filepath.Join(cfg.GOROOTsrc, filepath.FromSlash(vendorPath))); err == nil { return vendorPath } } - } else if !ld.VendorModulesInGOROOTSrc || !loaderstate.MainModules.Contains("std") || str.HasPathPrefix(parentPath, "vendor") { + } else if !pld.VendorModulesInGOROOTSrc || !ld.MainModules.Contains("std") || str.HasPathPrefix(parentPath, "vendor") { // If we are outside of the 'std' module, resolve imports from within 'std' // to the vendor directory. // @@ -2006,8 +1998,8 @@ func (ld *loader) stdVendor(loaderstate *State, parentPath, path string) string // computePatternAll returns the list of packages matching pattern "all", // starting with a list of the import paths for the packages in the main module. -func (ld *loader) computePatternAll() (all []string) { - for _, pkg := range ld.pkgs { +func (pld *packageLoader) computePatternAll() (all []string) { + for _, pkg := range pld.pkgs { if module.CheckImportPath(pkg.path) != nil { // Don't add packages with invalid paths. This means that // we don't try to load invalid imports of the main modules' @@ -2027,33 +2019,41 @@ func (ld *loader) computePatternAll() (all []string) { // or as a replacement for another module, but not both at the same time. // // (See https://golang.org/issue/26607 and https://golang.org/issue/34650.) -func (ld *loader) checkMultiplePaths(loaderstate *State) { - mods := ld.requirements.rootModules - if cached := ld.requirements.graph.Load(); cached != nil { +func (pld *packageLoader) checkMultiplePaths(ld *Loader) { + if cached := pld.requirements.graph.Load(); cached != nil { if mg := cached.mg; mg != nil { - mods = mg.BuildList() + // The check depends only on the build list and workspace replace + // directives, both fixed for the lifetime of mg, so skip it on + // subsequent calls sharing the same graph. + mg.checkPathsOnce.Do(func() { + checkMultiplePathsUncached(ld, pld, mg.BuildList()) + }) + return } } + checkMultiplePathsUncached(ld, pld, pld.requirements.rootModules) +} +func checkMultiplePathsUncached(ld *Loader, pld *packageLoader, mods []module.Version) { firstPath := map[module.Version]string{} for _, mod := range mods { - src := resolveReplacement(loaderstate, mod) + src := resolveReplacement(ld, mod) if prev, ok := firstPath[src]; !ok { firstPath[src] = mod.Path } else if prev != mod.Path { - ld.error(fmt.Errorf("%s@%s used for two different module paths (%s and %s)", src.Path, src.Version, prev, mod.Path)) + pld.error(fmt.Errorf("%s@%s used for two different module paths (%s and %s)", src.Path, src.Version, prev, mod.Path)) } } } // checkTidyCompatibility emits an error if any package would be loaded from a // different module under rs than under ld.requirements. -func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context, rs *Requirements, compatVersion string) { - goVersion := rs.GoVersion(loaderstate) +func (pld *packageLoader) checkTidyCompatibility(ld *Loader, ctx context.Context, rs *Requirements, compatVersion string) { + goVersion := rs.GoVersion(ld) suggestUpgrade := false suggestEFlag := false suggestFixes := func() { - if ld.AllowErrors { + if pld.AllowErrors { // The user is explicitly ignoring these errors, so don't bother them with // other options. return @@ -2066,7 +2066,7 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context fmt.Fprintln(os.Stderr) goFlag := "" - if goVersion != loaderstate.MainModules.GoVersion(loaderstate) { + if goVersion != ld.MainModules.GoVersion(ld) { goFlag = " -go=" + goVersion } @@ -2095,12 +2095,12 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context fmt.Fprintf(os.Stderr, "For information about 'go mod tidy' compatibility, see:\n\thttps://go.dev/ref/mod#graph-pruning\n") } - mg, err := rs.Graph(loaderstate, ctx) + mg, err := rs.Graph(ld, ctx) if err != nil { - ld.error(fmt.Errorf("error loading go %s module graph: %w", compatVersion, err)) - ld.switchIfErrors(ctx) + pld.error(fmt.Errorf("error loading go %s module graph: %w", compatVersion, err)) + pld.switchIfErrors(ctx) suggestFixes() - ld.exitIfErrors(ctx) + pld.exitIfErrors(ctx) return } @@ -2124,7 +2124,7 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context } mismatchMu := make(chan map[*loadPkg]mismatch, 1) mismatchMu <- map[*loadPkg]mismatch{} - for _, pkg := range ld.pkgs { + for _, pkg := range pld.pkgs { if pkg.mod.Path == "" && pkg.err == nil { // This package is from the standard library (which does not vary based on // the module graph). @@ -2132,8 +2132,8 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context } pkg := pkg - ld.work.Add(func() { - mod, _, _, _, err := importFromModules(loaderstate, ctx, pkg.path, rs, mg, ld.skipImportModFiles) + pld.work.Add(func() { + mod, _, _, _, err := importFromModules(ld, ctx, pkg.path, rs, mg, pld.skipImportModFiles) if mod != pkg.mod { mismatches := <-mismatchMu mismatches[pkg] = mismatch{mod: mod, err: err} @@ -2141,7 +2141,7 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context } }) } - <-ld.work.Idle() + <-pld.work.Idle() mismatches := <-mismatchMu if len(mismatches) == 0 { @@ -2156,10 +2156,10 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context // we'll double-check that our reasoning above actually holds — if it // doesn't, we'll emit an internal error and hopefully the user will report // it as a bug. - for _, m := range ld.requirements.rootModules { + for _, m := range pld.requirements.rootModules { if v := mg.Selected(m.Path); v != m.Version { fmt.Fprintln(os.Stderr) - base.Fatalf("go: internal error: failed to diagnose selected-version mismatch for module %s: go %s selects %s, but go %s selects %s\n\tPlease report this at https://golang.org/issue.", m.Path, goVersion, m.Version, compatVersion, v) + base.Fatalf("go: internal error: failed to diagnose selected-version mismatch for module %s: go %s selects %s, but go %s selects %s\n\tPlease report this at https://go.dev/issue.", m.Path, goVersion, m.Version, compatVersion, v) } } return @@ -2167,7 +2167,7 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context // Iterate over the packages (instead of the mismatches map) to emit errors in // deterministic order. - for _, pkg := range ld.pkgs { + for _, pkg := range pld.pkgs { mismatch, ok := mismatches[pkg] if !ok { continue @@ -2200,12 +2200,12 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context Path: pkg.mod.Path, Version: mg.Selected(pkg.mod.Path), } - ld.error(fmt.Errorf("%s loaded from %v,\n\tbut go %s would fail to locate it in %s", pkg.stackText(), pkg.mod, compatVersion, selected)) + pld.error(fmt.Errorf("%s loaded from %v,\n\tbut go %s would fail to locate it in %s", pkg.stackText(), pkg.mod, compatVersion, selected)) } else { if _, ok := errors.AsType[*AmbiguousImportError](mismatch.err); ok { // TODO: Is this check needed? } - ld.error(fmt.Errorf("%s loaded from %v,\n\tbut go %s would fail to locate it:\n\t%v", pkg.stackText(), pkg.mod, compatVersion, mismatch.err)) + pld.error(fmt.Errorf("%s loaded from %v,\n\tbut go %s would fail to locate it:\n\t%v", pkg.stackText(), pkg.mod, compatVersion, mismatch.err)) } suggestEFlag = true @@ -2218,7 +2218,7 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context // We check for that condition here. If all of the roots are consistent // the '-e' flag suffices, but otherwise we need to suggest an upgrade. if !suggestUpgrade { - for _, m := range ld.requirements.rootModules { + for _, m := range pld.requirements.rootModules { if v := mg.Selected(m.Path); v != m.Version { suggestUpgrade = true break @@ -2243,7 +2243,7 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context // pkg.err should have already been logged elsewhere — along with a // stack trace — so log only the import path and non-error info here. suggestUpgrade = true - ld.error(fmt.Errorf("%s failed to load from any module,\n\tbut go %s would load it from %v", pkg.path, compatVersion, mismatch.mod)) + pld.error(fmt.Errorf("%s failed to load from any module,\n\tbut go %s would load it from %v", pkg.path, compatVersion, mismatch.mod)) case pkg.mod != mismatch.mod: // The package is loaded successfully by both Go versions, but from a @@ -2251,16 +2251,16 @@ func (ld *loader) checkTidyCompatibility(loaderstate *State, ctx context.Context // unnoticed!) variations in behavior between builds with different // toolchains. suggestUpgrade = true - ld.error(fmt.Errorf("%s loaded from %v,\n\tbut go %s would select %v\n", pkg.stackText(), pkg.mod, compatVersion, mismatch.mod.Version)) + pld.error(fmt.Errorf("%s loaded from %v,\n\tbut go %s would select %v\n", pkg.stackText(), pkg.mod, compatVersion, mismatch.mod.Version)) default: base.Fatalf("go: internal error: mismatch recorded for package %s, but no differences found", pkg.path) } } - ld.switchIfErrors(ctx) + pld.switchIfErrors(ctx) suggestFixes() - ld.exitIfErrors(ctx) + pld.exitIfErrors(ctx) } // scanDir is like imports.ScanDir but elides known magic imports from the list, @@ -2308,28 +2308,28 @@ Happy: // package up the import stack in their minimal chain. // As a side effect, buildStacks also constructs ld.pkgs, // the list of all packages loaded. -func (ld *loader) buildStacks() { - if len(ld.pkgs) > 0 { +func (pld *packageLoader) buildStacks() { + if len(pld.pkgs) > 0 { panic("buildStacks") } - for _, pkg := range ld.roots { + for _, pkg := range pld.roots { pkg.stack = pkg // sentinel to avoid processing in next loop - ld.pkgs = append(ld.pkgs, pkg) + pld.pkgs = append(pld.pkgs, pkg) } - for i := 0; i < len(ld.pkgs); i++ { // not range: appending to ld.pkgs in loop - pkg := ld.pkgs[i] + for i := 0; i < len(pld.pkgs); i++ { // not range: appending to ld.pkgs in loop + pkg := pld.pkgs[i] for _, next := range pkg.imports { if next.stack == nil { next.stack = pkg - ld.pkgs = append(ld.pkgs, next) + pld.pkgs = append(pld.pkgs, next) } } if next := pkg.test; next != nil && next.stack == nil { next.stack = pkg - ld.pkgs = append(ld.pkgs, next) + pld.pkgs = append(pld.pkgs, next) } } - for _, pkg := range ld.roots { + for _, pkg := range pld.roots { pkg.stack = nil } } @@ -2391,8 +2391,8 @@ func (pkg *loadPkg) why() string { // The package graph must have been loaded already, usually by LoadPackages. // If there is no reason for the package to be in the current build, // Why returns an empty string. -func Why(path string) string { - pkg, ok := loaded.pkgCache.Get(path) +func (ld *Loader) Why(path string) string { + pkg, ok := ld.pkgLoader.pkgCache.Get(path) if !ok { return "" } @@ -2402,9 +2402,9 @@ func Why(path string) string { // WhyDepth returns the number of steps in the Why listing. // If there is no reason for the package to be in the current build, // WhyDepth returns 0. -func WhyDepth(path string) int { +func (ld *Loader) WhyDepth(path string) int { n := 0 - pkg, _ := loaded.pkgCache.Get(path) + pkg, _ := ld.pkgLoader.pkgCache.Get(path) for p := pkg; p != nil; p = p.stack { n++ } diff --git a/src/cmd/go/internal/modload/modfile.go b/src/cmd/go/internal/modload/modfile.go index be0f2a5c1166fc..574ff69c8c22f5 100644 --- a/src/cmd/go/internal/modload/modfile.go +++ b/src/cmd/go/internal/modload/modfile.go @@ -138,11 +138,11 @@ func pruningForGoVersion(goVersion string) modPruning { // CheckAllowed returns an error equivalent to ErrDisallowed if m is excluded by // the main module's go.mod or retracted by its author. Most version queries use // this to filter out versions that should not be used. -func (s *State) CheckAllowed(ctx context.Context, m module.Version) error { - if err := s.CheckExclusions(ctx, m); err != nil { +func (ld *Loader) CheckAllowed(ctx context.Context, m module.Version) error { + if err := ld.CheckExclusions(ctx, m); err != nil { return err } - if err := s.CheckRetractions(ctx, m); err != nil { + if err := ld.CheckRetractions(ctx, m); err != nil { return err } return nil @@ -154,9 +154,9 @@ var ErrDisallowed = errors.New("disallowed module version") // CheckExclusions returns an error equivalent to ErrDisallowed if module m is // excluded by the main module's go.mod file. -func (s *State) CheckExclusions(ctx context.Context, m module.Version) error { - for _, mainModule := range s.MainModules.Versions() { - if index := s.MainModules.Index(mainModule); index != nil && index.exclude[m] { +func (ld *Loader) CheckExclusions(ctx context.Context, m module.Version) error { + for _, mainModule := range ld.MainModules.Versions() { + if index := ld.MainModules.Index(mainModule); index != nil && index.exclude[m] { return module.VersionError(m, errExcluded) } } @@ -172,7 +172,7 @@ func (e *excludedError) Is(err error) bool { return err == ErrDisallowed } // CheckRetractions returns an error if module m has been retracted by // its author. -func (s *State) CheckRetractions(ctx context.Context, m module.Version) (err error) { +func (ld *Loader) CheckRetractions(ctx context.Context, m module.Version) (err error) { defer func() { if err == nil { return @@ -193,7 +193,7 @@ func (s *State) CheckRetractions(ctx context.Context, m module.Version) (err err // Cannot be retracted. return nil } - if repl := Replacement(s, module.Version{Path: m.Path}); repl.Path != "" { + if repl := Replacement(ld, module.Version{Path: m.Path}); repl.Path != "" { // All versions of the module were replaced. // Don't load retractions, since we'd just load the replacement. return nil @@ -210,11 +210,11 @@ func (s *State) CheckRetractions(ctx context.Context, m module.Version) (err err // We load the raw file here: the go.mod file may have a different module // path that we expect if the module or its repository was renamed. // We still want to apply retractions to other aliases of the module. - rm, err := queryLatestVersionIgnoringRetractions(s, ctx, m.Path) + rm, err := queryLatestVersionIgnoringRetractions(ld, ctx, m.Path) if err != nil { return err } - summary, err := rawGoModSummary(s, rm) + summary, err := rawGoModSummary(ld, rm) if err != nil && !errors.Is(err, gover.ErrTooNew) { return err } @@ -300,7 +300,7 @@ func ShortMessage(message, emptyDefault string) string { // // CheckDeprecation returns an error if the message can't be loaded. // CheckDeprecation returns "", nil if there is no deprecation message. -func CheckDeprecation(loaderstate *State, ctx context.Context, m module.Version) (deprecation string, err error) { +func CheckDeprecation(ld *Loader, ctx context.Context, m module.Version) (deprecation string, err error) { defer func() { if err != nil { err = fmt.Errorf("loading deprecation for %s: %w", m.Path, err) @@ -312,17 +312,17 @@ func CheckDeprecation(loaderstate *State, ctx context.Context, m module.Version) // Don't look up deprecation. return "", nil } - if repl := Replacement(loaderstate, module.Version{Path: m.Path}); repl.Path != "" { + if repl := Replacement(ld, module.Version{Path: m.Path}); repl.Path != "" { // All versions of the module were replaced. // We'll look up deprecation separately for the replacement. return "", nil } - latest, err := queryLatestVersionIgnoringRetractions(loaderstate, ctx, m.Path) + latest, err := queryLatestVersionIgnoringRetractions(ld, ctx, m.Path) if err != nil { return "", err } - summary, err := rawGoModSummary(loaderstate, latest) + summary, err := rawGoModSummary(ld, latest) if err != nil && !errors.Is(err, gover.ErrTooNew) { return "", err } @@ -342,28 +342,28 @@ func replacement(mod module.Version, replace map[module.Version]module.Version) // Replacement returns the replacement for mod, if any. If the path in the // module.Version is relative it's relative to the single main module outside // workspace mode, or the workspace's directory in workspace mode. -func Replacement(loaderstate *State, mod module.Version) module.Version { - r, foundModRoot, _ := replacementFrom(loaderstate, mod) - return canonicalizeReplacePath(loaderstate, r, foundModRoot) +func Replacement(ld *Loader, mod module.Version) module.Version { + r, foundModRoot, _ := replacementFrom(ld, mod) + return canonicalizeReplacePath(ld, r, foundModRoot) } // replacementFrom returns the replacement for mod, if any, the modroot of the replacement if it appeared in a go.mod, // and the source of the replacement. The replacement is relative to the go.work or go.mod file it appears in. -func replacementFrom(loaderstate *State, mod module.Version) (r module.Version, modroot string, fromFile string) { +func replacementFrom(ld *Loader, mod module.Version) (r module.Version, modroot string, fromFile string) { foundFrom, found, foundModRoot := "", module.Version{}, "" - if loaderstate.MainModules == nil { + if ld.MainModules == nil { return module.Version{}, "", "" - } else if loaderstate.MainModules.Contains(mod.Path) && mod.Version == "" { + } else if ld.MainModules.Contains(mod.Path) && mod.Version == "" { // Don't replace the workspace version of the main module. return module.Version{}, "", "" } - if _, r, ok := replacement(mod, loaderstate.MainModules.WorkFileReplaceMap()); ok { - return r, "", loaderstate.workFilePath + if _, r, ok := replacement(mod, ld.MainModules.WorkFileReplaceMap()); ok { + return r, "", ld.workFilePath } - for _, v := range loaderstate.MainModules.Versions() { - if index := loaderstate.MainModules.Index(v); index != nil { + for _, v := range ld.MainModules.Versions() { + if index := ld.MainModules.Index(v); index != nil { if from, r, ok := replacement(mod, index.replace); ok { - modRoot := loaderstate.MainModules.ModRoot(v) + modRoot := ld.MainModules.ModRoot(v) if foundModRoot != "" && foundFrom != from && found != r { base.Errorf("conflicting replacements found for %v in workspace modules defined by %v and %v", mod, modFilePath(foundModRoot), modFilePath(modRoot)) @@ -376,21 +376,21 @@ func replacementFrom(loaderstate *State, mod module.Version) (r module.Version, return found, foundModRoot, modFilePath(foundModRoot) } -func replaceRelativeTo(loaderstate *State) string { - if workFilePath := WorkFilePath(loaderstate); workFilePath != "" { +func replaceRelativeTo(ld *Loader) string { + if workFilePath := WorkFilePath(ld); workFilePath != "" { return filepath.Dir(workFilePath) } - return loaderstate.MainModules.ModRoot(loaderstate.MainModules.mustGetSingleMainModule(loaderstate)) + return ld.MainModules.ModRoot(ld.MainModules.mustGetSingleMainModule(ld)) } // canonicalizeReplacePath ensures that relative, on-disk, replaced module paths // are relative to the workspace directory (in workspace mode) or to the module's // directory (in module mode, as they already are). -func canonicalizeReplacePath(loaderstate *State, r module.Version, modRoot string) module.Version { +func canonicalizeReplacePath(ld *Loader, r module.Version, modRoot string) module.Version { if filepath.IsAbs(r.Path) || r.Version != "" || modRoot == "" { return r } - workFilePath := WorkFilePath(loaderstate) + workFilePath := WorkFilePath(ld) if workFilePath == "" { return r } @@ -407,8 +407,8 @@ func canonicalizeReplacePath(loaderstate *State, r module.Version, modRoot strin // for m: either m itself, or the replacement for m (iff m is replaced). // It also returns the modroot of the module providing the replacement if // one was found. -func resolveReplacement(loaderstate *State, m module.Version) module.Version { - if r := Replacement(loaderstate, m); r.Path != "" { +func resolveReplacement(ld *Loader, m module.Version) module.Version { + if r := Replacement(ld, m); r.Path != "" { return r } return m @@ -573,12 +573,12 @@ type retraction struct { // module versions. // // The caller must not modify the returned summary. -func goModSummary(loaderstate *State, m module.Version) (*modFileSummary, error) { - if m.Version == "" && !inWorkspaceMode(loaderstate) && loaderstate.MainModules.Contains(m.Path) { +func goModSummary(ld *Loader, m module.Version) (*modFileSummary, error) { + if m.Version == "" && !ld.inWorkspaceMode() && ld.MainModules.Contains(m.Path) { panic("internal error: goModSummary called on a main module") } if gover.IsToolchain(m.Path) { - return rawGoModSummary(loaderstate, m) + return rawGoModSummary(ld, m) } if cfg.BuildMod == "vendor" { @@ -586,7 +586,7 @@ func goModSummary(loaderstate *State, m module.Version) (*modFileSummary, error) module: module.Version{Path: m.Path}, } - readVendorList(VendorDir(loaderstate)) + readVendorList(VendorDir(ld)) if vendorVersion[m.Path] != m.Version { // This module is not vendored, so packages cannot be loaded from it and // it cannot be relevant to the build. @@ -601,15 +601,15 @@ func goModSummary(loaderstate *State, m module.Version) (*modFileSummary, error) return summary, nil } - actual := resolveReplacement(loaderstate, m) - if mustHaveSums(loaderstate) && actual.Version != "" { + actual := resolveReplacement(ld, m) + if mustHaveSums(ld) && actual.Version != "" { key := module.Version{Path: actual.Path, Version: actual.Version + "/go.mod"} - if !modfetch.HaveSum(key) { + if !modfetch.HaveSum(ld.Fetcher(), key) { suggestion := fmt.Sprintf(" for go.mod file; to add it:\n\tgo mod download %s", m.Path) return nil, module.VersionError(actual, &sumMissingError{suggestion: suggestion}) } } - summary, err := rawGoModSummary(loaderstate, actual) + summary, err := rawGoModSummary(ld, actual) if err != nil { return nil, err } @@ -641,8 +641,8 @@ func goModSummary(loaderstate *State, m module.Version) (*modFileSummary, error) } } - for _, mainModule := range loaderstate.MainModules.Versions() { - if index := loaderstate.MainModules.Index(mainModule); index != nil && len(index.exclude) > 0 { + for _, mainModule := range ld.MainModules.Versions() { + if index := ld.MainModules.Index(mainModule); index != nil && len(index.exclude) > 0 { // Drop any requirements on excluded versions. // Don't modify the cached summary though, since we might need the raw // summary separately. @@ -676,7 +676,7 @@ func goModSummary(loaderstate *State, m module.Version) (*modFileSummary, error) // rawGoModSummary cannot be used on the main module outside of workspace mode. // The modFileSummary can still be used for retractions and deprecations // even if a TooNewError is returned. -func rawGoModSummary(loaderstate *State, m module.Version) (*modFileSummary, error) { +func rawGoModSummary(ld *Loader, m module.Version) (*modFileSummary, error) { if gover.IsToolchain(m.Path) { if m.Path == "go" && gover.Compare(m.Version, gover.GoStrictVersion) >= 0 { // Declare that go 1.21.3 requires toolchain 1.21.3, @@ -686,7 +686,7 @@ func rawGoModSummary(loaderstate *State, m module.Version) (*modFileSummary, err } return &modFileSummary{module: m}, nil } - if m.Version == "" && !inWorkspaceMode(loaderstate) && loaderstate.MainModules.Contains(m.Path) { + if m.Version == "" && !ld.inWorkspaceMode() && ld.MainModules.Contains(m.Path) { // Calling rawGoModSummary implies that we are treating m as a module whose // requirements aren't the roots of the module graph and can't be modified. // @@ -694,22 +694,22 @@ func rawGoModSummary(loaderstate *State, m module.Version) (*modFileSummary, err // are the roots of the module graph and we expect them to be kept consistent. panic("internal error: rawGoModSummary called on a main module") } - if m.Version == "" && inWorkspaceMode(loaderstate) && m.Path == "command-line-arguments" { + if m.Version == "" && ld.inWorkspaceMode() && m.Path == "command-line-arguments" { // "go work sync" calls LoadModGraph to make sure the module graph is valid. // If there are no modules in the workspace, we synthesize an empty // command-line-arguments module, which rawGoModData cannot read a go.mod for. return &modFileSummary{module: m}, nil - } else if m.Version == "" && inWorkspaceMode(loaderstate) && loaderstate.MainModules.Contains(m.Path) { + } else if m.Version == "" && ld.inWorkspaceMode() && ld.MainModules.Contains(m.Path) { // When go get uses EnterWorkspace to check that the workspace loads properly, // it will update the contents of the workspace module's modfile in memory. To use the updated // contents of the modfile when doing the load, don't read from disk and instead // recompute a summary using the updated contents of the modfile. - if mf := loaderstate.MainModules.ModFile(m); mf != nil { - return summaryFromModFile(m, loaderstate.MainModules.modFiles[m]) + if mf := ld.MainModules.ModFile(m); mf != nil { + return summaryFromModFile(m, ld.MainModules.modFiles[m]) } } return rawGoModSummaryCache.Do(m, func() (*modFileSummary, error) { - name, data, err := rawGoModData(loaderstate, m) + name, data, err := rawGoModData(ld, m) if err != nil { return nil, err } @@ -781,15 +781,15 @@ var rawGoModSummaryCache par.ErrCache[module.Version, *modFileSummary] // // Unlike rawGoModSummary, rawGoModData does not cache its results in memory. // Use rawGoModSummary instead unless you specifically need these bytes. -func rawGoModData(loaderstate *State, m module.Version) (name string, data []byte, err error) { +func rawGoModData(ld *Loader, m module.Version) (name string, data []byte, err error) { if m.Version == "" { dir := m.Path if !filepath.IsAbs(dir) { - if inWorkspaceMode(loaderstate) && loaderstate.MainModules.Contains(m.Path) { - dir = loaderstate.MainModules.ModRoot(m) + if ld.inWorkspaceMode() && ld.MainModules.Contains(m.Path) { + dir = ld.MainModules.ModRoot(m) } else { // m is a replacement module with only a file path. - dir = filepath.Join(replaceRelativeTo(loaderstate), dir) + dir = filepath.Join(replaceRelativeTo(ld), dir) } } name = filepath.Join(dir, "go.mod") @@ -810,7 +810,7 @@ func rawGoModData(loaderstate *State, m module.Version) (name string, data []byt base.Fatalf("go: internal error: %s@%s: unexpected invalid semantic version", m.Path, m.Version) } name = "go.mod" - data, err = modfetch.GoMod(context.TODO(), m.Path, m.Version) + data, err = ld.Fetcher().GoMod(context.TODO(), m.Path, m.Version) } return name, data, err } @@ -825,12 +825,12 @@ func rawGoModData(loaderstate *State, m module.Version) (name string, data []byt // // If the queried latest version is replaced, // queryLatestVersionIgnoringRetractions returns the replacement. -func queryLatestVersionIgnoringRetractions(loaderstate *State, ctx context.Context, path string) (latest module.Version, err error) { +func queryLatestVersionIgnoringRetractions(ld *Loader, ctx context.Context, path string) (latest module.Version, err error) { return latestVersionIgnoringRetractionsCache.Do(path, func() (module.Version, error) { ctx, span := trace.StartSpan(ctx, "queryLatestVersionIgnoringRetractions "+path) defer span.Done() - if repl := Replacement(loaderstate, module.Version{Path: path}); repl.Path != "" { + if repl := Replacement(ld, module.Version{Path: path}); repl.Path != "" { // All versions of the module were replaced. // No need to query. return repl, nil @@ -840,12 +840,12 @@ func queryLatestVersionIgnoringRetractions(loaderstate *State, ctx context.Conte // Ignore exclusions from the main module's go.mod. const ignoreSelected = "" var allowAll AllowedFunc - rev, err := Query(loaderstate, ctx, path, "latest", ignoreSelected, allowAll) + rev, err := Query(ld, ctx, path, "latest", ignoreSelected, allowAll) if err != nil { return module.Version{}, err } latest := module.Version{Path: path, Version: rev.Version} - if repl := resolveReplacement(loaderstate, latest); repl.Path != "" { + if repl := resolveReplacement(ld, latest); repl.Path != "" { latest = repl } return latest, nil diff --git a/src/cmd/go/internal/modload/mvs.go b/src/cmd/go/internal/modload/mvs.go index 63fedae0f16212..27796c274ac4c3 100644 --- a/src/cmd/go/internal/modload/mvs.go +++ b/src/cmd/go/internal/modload/mvs.go @@ -39,12 +39,12 @@ func cmpVersion(p string, v1, v2 string) int { // mvsReqs implements mvs.Reqs for module semantic versions, // with any exclusions or replacements applied internally. type mvsReqs struct { - loaderstate *State // TODO(jitsu): Is there a way we can not depend on the entire loader state? - roots []module.Version + ld *Loader // TODO(jitsu): Is there a way we can not depend on the entire loader state? + roots []module.Version } func (r *mvsReqs) Required(mod module.Version) ([]module.Version, error) { - if mod.Version == "" && r.loaderstate.MainModules.Contains(mod.Path) { + if mod.Version == "" && r.ld.MainModules.Contains(mod.Path) { // Use the build list as it existed when r was constructed, not the current // global build list. return r.roots, nil @@ -54,7 +54,7 @@ func (r *mvsReqs) Required(mod module.Version) ([]module.Version, error) { return nil, nil } - summary, err := goModSummary(r.loaderstate, mod) + summary, err := goModSummary(r.ld, mod) if err != nil { return nil, err } @@ -80,11 +80,11 @@ func (*mvsReqs) Upgrade(m module.Version) (module.Version, error) { return m, nil } -func versions(loaderstate *State, ctx context.Context, path string, allowed AllowedFunc) (versions []string, origin *codehost.Origin, err error) { +func versions(ld *Loader, ctx context.Context, path string, allowed AllowedFunc) (versions []string, origin *codehost.Origin, err error) { // Note: modfetch.Lookup and repo.Versions are cached, // so there's no need for us to add extra caching here. err = modfetch.TryProxies(func(proxy string) error { - repo, err := lookupRepo(loaderstate, ctx, proxy, path) + repo, err := lookupRepo(ld, ctx, proxy, path) if err != nil { return err } @@ -112,12 +112,12 @@ func versions(loaderstate *State, ctx context.Context, path string, allowed Allo // // Since the version of a main module is not found in the version list, // it has no previous version. -func previousVersion(loaderstate *State, ctx context.Context, m module.Version) (module.Version, error) { - if m.Version == "" && loaderstate.MainModules.Contains(m.Path) { +func previousVersion(ld *Loader, ctx context.Context, m module.Version) (module.Version, error) { + if m.Version == "" && ld.MainModules.Contains(m.Path) { return module.Version{Path: m.Path, Version: "none"}, nil } - list, _, err := versions(loaderstate, ctx, m.Path, loaderstate.CheckAllowed) + list, _, err := versions(ld, ctx, m.Path, ld.CheckAllowed) if err != nil { if errors.Is(err, os.ErrNotExist) { return module.Version{Path: m.Path, Version: "none"}, nil @@ -133,5 +133,5 @@ func previousVersion(loaderstate *State, ctx context.Context, m module.Version) func (r *mvsReqs) Previous(m module.Version) (module.Version, error) { // TODO(golang.org/issue/38714): thread tracing context through MVS. - return previousVersion(r.loaderstate, context.TODO(), m) + return previousVersion(r.ld, context.TODO(), m) } diff --git a/src/cmd/go/internal/modload/query.go b/src/cmd/go/internal/modload/query.go index 2bf3fcb846633d..e7f30dfaf85c2e 100644 --- a/src/cmd/go/internal/modload/query.go +++ b/src/cmd/go/internal/modload/query.go @@ -80,19 +80,19 @@ import ( // // Query often returns a non-nil *RevInfo with a non-nil error, // to provide an info.Origin that can allow the error to be cached. -func Query(loaderstate *State, ctx context.Context, path, query, current string, allowed AllowedFunc) (*modfetch.RevInfo, error) { +func Query(ld *Loader, ctx context.Context, path, query, current string, allowed AllowedFunc) (*modfetch.RevInfo, error) { ctx, span := trace.StartSpan(ctx, "modload.Query "+path) defer span.Done() - return queryReuse(loaderstate, ctx, path, query, current, allowed, nil) + return queryReuse(ld, ctx, path, query, current, allowed, nil) } // queryReuse is like Query but also takes a map of module info that can be reused // if the validation criteria in Origin are met. -func queryReuse(loaderstate *State, ctx context.Context, path, query, current string, allowed AllowedFunc, reuse map[module.Version]*modinfo.ModulePublic) (*modfetch.RevInfo, error) { +func queryReuse(ld *Loader, ctx context.Context, path, query, current string, allowed AllowedFunc, reuse map[module.Version]*modinfo.ModulePublic) (*modfetch.RevInfo, error) { var info *modfetch.RevInfo err := modfetch.TryProxies(func(proxy string) (err error) { - info, err = queryProxy(loaderstate, ctx, proxy, path, query, current, allowed, reuse) + info, err = queryProxy(ld, ctx, proxy, path, query, current, allowed, reuse) return err }) return info, err @@ -100,9 +100,9 @@ func queryReuse(loaderstate *State, ctx context.Context, path, query, current st // checkReuse checks whether a revision of a given module // for a given module may be reused, according to the information in origin. -func checkReuse(loaderstate *State, ctx context.Context, m module.Version, old *codehost.Origin) error { +func checkReuse(ld *Loader, ctx context.Context, m module.Version, old *codehost.Origin) error { return modfetch.TryProxies(func(proxy string) error { - repo, err := lookupRepo(loaderstate, ctx, proxy, m.Path) + repo, err := lookupRepo(ld, ctx, proxy, m.Path) if err != nil { return err } @@ -197,7 +197,7 @@ func (queryDisabledError) Error() string { return fmt.Sprintf("cannot query module due to -mod=%s\n\t(%s)", cfg.BuildMod, cfg.BuildModReason) } -func queryProxy(loaderstate *State, ctx context.Context, proxy, path, query, current string, allowed AllowedFunc, reuse map[module.Version]*modinfo.ModulePublic) (*modfetch.RevInfo, error) { +func queryProxy(ld *Loader, ctx context.Context, proxy, path, query, current string, allowed AllowedFunc, reuse map[module.Version]*modinfo.ModulePublic) (*modfetch.RevInfo, error) { ctx, span := trace.StartSpan(ctx, "modload.queryProxy "+path+" "+query) defer span.Done() @@ -211,7 +211,7 @@ func queryProxy(loaderstate *State, ctx context.Context, proxy, path, query, cur allowed = func(context.Context, module.Version) error { return nil } } - if loaderstate.MainModules.Contains(path) && (query == "upgrade" || query == "patch") { + if ld.MainModules.Contains(path) && (query == "upgrade" || query == "patch") { m := module.Version{Path: path} if err := allowed(ctx, m); err != nil { return nil, fmt.Errorf("internal error: main module version is not allowed: %w", err) @@ -223,7 +223,7 @@ func queryProxy(loaderstate *State, ctx context.Context, proxy, path, query, cur return nil, fmt.Errorf("can't query specific version (%q) of standard-library module %q", query, path) } - repo, err := lookupRepo(loaderstate, ctx, proxy, path) + repo, err := lookupRepo(ld, ctx, proxy, path) if err != nil { return nil, err } @@ -296,7 +296,7 @@ func queryProxy(loaderstate *State, ctx context.Context, proxy, path, query, cur return &clone } - releases, prereleases, err := qm.filterVersions(loaderstate, ctx, versions.List) + releases, prereleases, err := qm.filterVersions(ld, ctx, versions.List) if err != nil { return revWithOrigin(nil), err } @@ -569,7 +569,7 @@ func (qm *queryMatcher) allowsVersion(ctx context.Context, v string) bool { // // If the allowed predicate returns an error not equivalent to ErrDisallowed, // filterVersions returns that error. -func (qm *queryMatcher) filterVersions(loaderstate *State, ctx context.Context, versions []string) (releases, prereleases []string, err error) { +func (qm *queryMatcher) filterVersions(ld *Loader, ctx context.Context, versions []string) (releases, prereleases []string, err error) { needIncompatible := qm.preferIncompatible var lastCompatible string @@ -602,7 +602,7 @@ func (qm *queryMatcher) filterVersions(loaderstate *State, ctx context.Context, // ignore any version with a higher (+incompatible) major version. (See // https://golang.org/issue/34165.) Note that we even prefer a // compatible pre-release over an incompatible release. - ok, err := versionHasGoMod(loaderstate, ctx, module.Version{Path: qm.path, Version: lastCompatible}) + ok, err := versionHasGoMod(ld, ctx, module.Version{Path: qm.path, Version: lastCompatible}) if err != nil { return nil, nil, err } @@ -639,11 +639,11 @@ type QueryResult struct { // QueryPackages is like QueryPattern, but requires that the pattern match at // least one package and omits the non-package result (if any). -func QueryPackages(loaderstate *State, ctx context.Context, pattern, query string, current func(string) string, allowed AllowedFunc) ([]QueryResult, error) { - pkgMods, modOnly, err := QueryPattern(loaderstate, ctx, pattern, query, current, allowed) +func QueryPackages(ld *Loader, ctx context.Context, pattern, query string, current func(string) string, allowed AllowedFunc) ([]QueryResult, error) { + pkgMods, modOnly, err := QueryPattern(ld, ctx, pattern, query, current, allowed) if len(pkgMods) == 0 && err == nil { - replacement := Replacement(loaderstate, modOnly.Mod) + replacement := Replacement(ld, modOnly.Mod) return nil, &PackageNotInModuleError{ Mod: modOnly.Mod, Replacement: replacement, @@ -670,7 +670,7 @@ func QueryPackages(loaderstate *State, ctx context.Context, pattern, query strin // // QueryPattern always returns at least one QueryResult (which may be only // modOnly) or a non-nil error. -func QueryPattern(loaderstate *State, ctx context.Context, pattern, query string, current func(string) string, allowed AllowedFunc) (pkgMods []QueryResult, modOnly *QueryResult, err error) { +func QueryPattern(ld *Loader, ctx context.Context, pattern, query string, current func(string) string, allowed AllowedFunc) (pkgMods []QueryResult, modOnly *QueryResult, err error) { ctx, span := trace.StartSpan(ctx, "modload.QueryPattern "+pattern+" "+query) defer span.Done() @@ -693,15 +693,15 @@ func QueryPattern(loaderstate *State, ctx context.Context, pattern, query string } match = func(mod module.Version, roots []string, isLocal bool) *search.Match { m := search.NewMatch(pattern) - matchPackages(loaderstate, ctx, m, imports.AnyTags(), omitStd, []module.Version{mod}) + matchPackages(ld, ctx, m, imports.AnyTags(), omitStd, []module.Version{mod}) return m } } else { match = func(mod module.Version, roots []string, isLocal bool) *search.Match { m := search.NewMatch(pattern) prefix := mod.Path - if loaderstate.MainModules.Contains(mod.Path) { - prefix = loaderstate.MainModules.PathPrefix(module.Version{Path: mod.Path}) + if ld.MainModules.Contains(mod.Path) { + prefix = ld.MainModules.PathPrefix(module.Version{Path: mod.Path}) } for _, root := range roots { if _, ok, err := dirInModule(pattern, prefix, root, isLocal); err != nil { @@ -715,8 +715,8 @@ func QueryPattern(loaderstate *State, ctx context.Context, pattern, query string } var mainModuleMatches []module.Version - for _, mainModule := range loaderstate.MainModules.Versions() { - m := match(mainModule, loaderstate.modRoots, true) + for _, mainModule := range ld.MainModules.Versions() { + m := match(mainModule, ld.modRoots, true) if len(m.Pkgs) > 0 { if query != "upgrade" && query != "patch" { return nil, nil, &QueryMatchesPackagesInMainModuleError{ @@ -756,17 +756,17 @@ func QueryPattern(loaderstate *State, ctx context.Context, pattern, query string var ( results []QueryResult - candidateModules = modulePrefixesExcludingTarget(loaderstate, base) + candidateModules = modulePrefixesExcludingTarget(ld, base) ) if len(candidateModules) == 0 { if modOnly != nil { return nil, modOnly, nil } else if len(mainModuleMatches) != 0 { return nil, nil, &QueryMatchesMainModulesError{ - LoaderState: loaderstate, - MainModules: mainModuleMatches, - Pattern: pattern, - Query: query, + MainModules: mainModuleMatches, + Pattern: pattern, + Query: query, + PatternIsModule: ld.MainModules.Contains(pattern), } } else { return nil, nil, &PackageNotInModuleError{ @@ -784,7 +784,7 @@ func QueryPattern(loaderstate *State, ctx context.Context, pattern, query string pathCurrent := current(path) r.Mod.Path = path - r.Rev, err = queryProxy(loaderstate, ctx, proxy, path, query, pathCurrent, allowed, nil) + r.Rev, err = queryProxy(ld, ctx, proxy, path, query, pathCurrent, allowed, nil) if err != nil { return r, err } @@ -792,7 +792,7 @@ func QueryPattern(loaderstate *State, ctx context.Context, pattern, query string if gover.IsToolchain(r.Mod.Path) { return r, nil } - root, isLocal, err := fetch(loaderstate, ctx, r.Mod) + root, isLocal, err := fetch(ld, ctx, r.Mod) if err != nil { return r, err } @@ -802,7 +802,7 @@ func QueryPattern(loaderstate *State, ctx context.Context, pattern, query string if err := firstError(m); err != nil { return r, err } - replacement := Replacement(loaderstate, r.Mod) + replacement := Replacement(ld, r.Mod) return r, &PackageNotInModuleError{ Mod: r.Mod, Replacement: replacement, @@ -813,7 +813,7 @@ func QueryPattern(loaderstate *State, ctx context.Context, pattern, query string return r, nil } - allResults, err := queryPrefixModules(loaderstate, ctx, candidateModules, queryModule) + allResults, err := queryPrefixModules(ld, ctx, candidateModules, queryModule) results = allResults[:0] for _, r := range allResults { if len(r.Packages) == 0 { @@ -827,9 +827,9 @@ func QueryPattern(loaderstate *State, ctx context.Context, pattern, query string if len(mainModuleMatches) > 0 && len(results) == 0 && modOnly == nil && errors.Is(err, fs.ErrNotExist) { return nil, nil, &QueryMatchesMainModulesError{ - LoaderState: loaderstate, - Pattern: pattern, - Query: query, + Pattern: pattern, + Query: query, + PatternIsModule: ld.MainModules.Contains(pattern), } } return slices.Clip(results), modOnly, err @@ -840,11 +840,11 @@ func QueryPattern(loaderstate *State, ctx context.Context, pattern, query string // itself, sorted by descending length. Prefixes that are not valid module paths // but are valid package paths (like "m" or "example.com/.gen") are included, // since they might be replaced. -func modulePrefixesExcludingTarget(loaderstate *State, path string) []string { +func modulePrefixesExcludingTarget(ld *Loader, path string) []string { prefixes := make([]string, 0, strings.Count(path, "/")+1) mainModulePrefixes := make(map[string]bool) - for _, m := range loaderstate.MainModules.Versions() { + for _, m := range ld.MainModules.Versions() { mainModulePrefixes[m.Path] = true } @@ -865,7 +865,7 @@ func modulePrefixesExcludingTarget(loaderstate *State, path string) []string { return prefixes } -func queryPrefixModules(loaderstate *State, ctx context.Context, candidateModules []string, queryModule func(ctx context.Context, path string) (QueryResult, error)) (found []QueryResult, err error) { +func queryPrefixModules(ld *Loader, ctx context.Context, candidateModules []string, queryModule func(ctx context.Context, path string) (QueryResult, error)) (found []QueryResult, err error) { ctx, span := trace.StartSpan(ctx, "modload.queryPrefixModules") defer span.Done() @@ -907,7 +907,7 @@ func queryPrefixModules(loaderstate *State, ctx context.Context, candidateModule case *PackageNotInModuleError: // Given the option, prefer to attribute “package not in module” // to modules other than the main one. - if noPackage == nil || loaderstate.MainModules.Contains(noPackage.Mod.Path) { + if noPackage == nil || ld.MainModules.Contains(noPackage.Mod.Path) { noPackage = rErr } case *NoMatchingVersionError: @@ -1098,8 +1098,8 @@ func (e *PackageNotInModuleError) ImportPath() string { // go.mod with different content. Second, if we don't fetch the .zip, then // we don't need to verify it in go.sum. This makes 'go list -m -u' faster // and simpler. -func versionHasGoMod(loaderstate *State, _ context.Context, m module.Version) (bool, error) { - _, data, err := rawGoModData(loaderstate, m) +func versionHasGoMod(ld *Loader, _ context.Context, m module.Version) (bool, error) { + _, data, err := rawGoModData(ld, m) if err != nil { return false, err } @@ -1119,20 +1119,20 @@ type versionRepo interface { var _ versionRepo = modfetch.Repo(nil) -func lookupRepo(loaderstate *State, ctx context.Context, proxy, path string) (repo versionRepo, err error) { +func lookupRepo(ld *Loader, ctx context.Context, proxy, path string) (repo versionRepo, err error) { if path != "go" && path != "toolchain" { err = module.CheckPath(path) } if err == nil { - repo = modfetch.Lookup(ctx, proxy, path) + repo = ld.Fetcher().Lookup(ctx, proxy, path) } else { repo = emptyRepo{path: path, err: err} } - if loaderstate.MainModules == nil { + if ld.MainModules == nil { return repo, err - } else if _, ok := loaderstate.MainModules.HighestReplaced()[path]; ok { - return &replacementRepo{repo: repo, loaderstate: loaderstate}, nil + } else if _, ok := ld.MainModules.HighestReplaced()[path]; ok { + return &replacementRepo{repo: repo, ld: ld}, nil } return repo, err @@ -1150,9 +1150,11 @@ func (er emptyRepo) ModulePath() string { return er.path } func (er emptyRepo) CheckReuse(ctx context.Context, old *codehost.Origin) error { return fmt.Errorf("empty repo") } + func (er emptyRepo) Versions(ctx context.Context, prefix string) (*modfetch.Versions, error) { return &modfetch.Versions{}, nil } + func (er emptyRepo) Stat(ctx context.Context, rev string) (*modfetch.RevInfo, error) { return nil, er.err } @@ -1165,8 +1167,8 @@ func (er emptyRepo) Latest(ctx context.Context) (*modfetch.RevInfo, error) { ret // modules, so a replacementRepo should only be constructed for a module that // actually has one or more valid replacements. type replacementRepo struct { - repo versionRepo - loaderstate *State + repo versionRepo + ld *Loader } var _ versionRepo = (*replacementRepo)(nil) @@ -1189,8 +1191,8 @@ func (rr *replacementRepo) Versions(ctx context.Context, prefix string) (*modfet } versions := repoVersions.List - for _, mm := range rr.loaderstate.MainModules.Versions() { - if index := rr.loaderstate.MainModules.Index(mm); index != nil && len(index.replace) > 0 { + for _, mm := range rr.ld.MainModules.Versions() { + if index := rr.ld.MainModules.Index(mm); index != nil && len(index.replace) > 0 { path := rr.ModulePath() for m := range index.replace { if m.Path == path && strings.HasPrefix(m.Version, prefix) && m.Version != "" && !module.IsPseudoVersion(m.Version) { @@ -1218,8 +1220,8 @@ func (rr *replacementRepo) Stat(ctx context.Context, rev string) (*modfetch.RevI return info, err } var hasReplacements bool - for _, v := range rr.loaderstate.MainModules.Versions() { - if index := rr.loaderstate.MainModules.Index(v); index != nil && len(index.replace) > 0 { + for _, v := range rr.ld.MainModules.Versions() { + if index := rr.ld.MainModules.Index(v); index != nil && len(index.replace) > 0 { hasReplacements = true } } @@ -1242,7 +1244,7 @@ func (rr *replacementRepo) Stat(ctx context.Context, rev string) (*modfetch.RevI } } - if r := Replacement(rr.loaderstate, module.Version{Path: path, Version: v}); r.Path == "" { + if r := Replacement(rr.ld, module.Version{Path: path, Version: v}); r.Path == "" { return info, err } return rr.replacementStat(v) @@ -1252,7 +1254,7 @@ func (rr *replacementRepo) Latest(ctx context.Context) (*modfetch.RevInfo, error info, err := rr.repo.Latest(ctx) path := rr.ModulePath() - if v, ok := rr.loaderstate.MainModules.HighestReplaced()[path]; ok { + if v, ok := rr.ld.MainModules.HighestReplaced()[path]; ok { if v == "" { // The only replacement is a wildcard that doesn't specify a version, so // synthesize a pseudo-version with an appropriate major version and a @@ -1287,15 +1289,14 @@ func (rr *replacementRepo) replacementStat(v string) (*modfetch.RevInfo, error) // a version of the main module that cannot be satisfied. // (The main module's version cannot be changed.) type QueryMatchesMainModulesError struct { - LoaderState *State - MainModules []module.Version - Pattern string - Query string + MainModules []module.Version + Pattern string + Query string + PatternIsModule bool // true if pattern is one of the main modules } func (e *QueryMatchesMainModulesError) Error() string { - // TODO(jitsu): break dependency on loaderstate - if e.LoaderState.MainModules.Contains(e.Pattern) { + if e.PatternIsModule { return fmt.Sprintf("can't request version %q of the main module (%s)", e.Query, e.Pattern) } diff --git a/src/cmd/go/internal/modload/query_test.go b/src/cmd/go/internal/modload/query_test.go index a465fab5db3933..261240715cc488 100644 --- a/src/cmd/go/internal/modload/query_test.go +++ b/src/cmd/go/internal/modload/query_test.go @@ -168,7 +168,7 @@ func TestQuery(t *testing.T) { ctx := context.Background() for _, tt := range queryTests { - loaderstate := NewState() + ld := NewLoader() allow := tt.allow if allow == "" { allow = "*" @@ -183,7 +183,7 @@ func TestQuery(t *testing.T) { t.Run(strings.ReplaceAll(tt.path, "/", "_")+"/"+tt.query+"/"+tt.current+"/"+allow, func(t *testing.T) { t.Parallel() - info, err := Query(loaderstate, ctx, tt.path, tt.query, tt.current, allowed) + info, err := Query(ld, ctx, tt.path, tt.query, tt.current, allowed) if tt.err != "" { if err == nil { t.Errorf("Query(_, %q, %q, %q, %v) = %v, want error %q", tt.path, tt.query, tt.current, allow, info.Version, tt.err) diff --git a/src/cmd/go/internal/modload/search.go b/src/cmd/go/internal/modload/search.go index 1bb4e3f911e04f..a08c01479f6d83 100644 --- a/src/cmd/go/internal/modload/search.go +++ b/src/cmd/go/internal/modload/search.go @@ -41,7 +41,7 @@ const ( // matchPackages is like m.MatchPackages, but uses a local variable (rather than // a global) for tags, can include or exclude packages in the standard library, // and is restricted to the given list of modules. -func matchPackages(loaderstate *State, ctx context.Context, m *search.Match, tags map[string]bool, filter stdFilter, modules []module.Version) { +func matchPackages(ld *Loader, ctx context.Context, m *search.Match, tags map[string]bool, filter stdFilter, modules []module.Version) { ctx, span := trace.StartSpan(ctx, "modload.matchPackages") defer span.Done() @@ -74,7 +74,7 @@ func matchPackages(loaderstate *State, ctx context.Context, m *search.Match, tag ) q := par.NewQueue(runtime.GOMAXPROCS(0)) - ignorePatternsMap := parseIgnorePatterns(loaderstate, ctx, treeCanMatch, modules) + ignorePatternsMap := parseIgnorePatterns(ld, ctx, treeCanMatch, modules) walkPkgs := func(root, importPathRoot string, prune pruning) { _, span := trace.StartSpan(ctx, "walkPkgs "+root) defer span.Done() @@ -171,13 +171,13 @@ func matchPackages(loaderstate *State, ctx context.Context, m *search.Match, tag } if cfg.BuildMod == "vendor" { - for _, mod := range loaderstate.MainModules.Versions() { - if modRoot := loaderstate.MainModules.ModRoot(mod); modRoot != "" { - walkPkgs(modRoot, loaderstate.MainModules.PathPrefix(mod), pruneGoMod|pruneVendor) + for _, mod := range ld.MainModules.Versions() { + if modRoot := ld.MainModules.ModRoot(mod); modRoot != "" { + walkPkgs(modRoot, ld.MainModules.PathPrefix(mod), pruneGoMod|pruneVendor) } } - if HasModRoot(loaderstate) { - walkPkgs(VendorDir(loaderstate), "", pruneVendor) + if ld.HasModRoot() { + walkPkgs(VendorDir(ld), "", pruneVendor) } return } @@ -191,16 +191,16 @@ func matchPackages(loaderstate *State, ctx context.Context, m *search.Match, tag root, modPrefix string isLocal bool ) - if loaderstate.MainModules.Contains(mod.Path) { - if loaderstate.MainModules.ModRoot(mod) == "" { + if ld.MainModules.Contains(mod.Path) { + if ld.MainModules.ModRoot(mod) == "" { continue // If there is no main module, we can't search in it. } - root = loaderstate.MainModules.ModRoot(mod) - modPrefix = loaderstate.MainModules.PathPrefix(mod) + root = ld.MainModules.ModRoot(mod) + modPrefix = ld.MainModules.PathPrefix(mod) isLocal = true } else { var err error - root, isLocal, err = fetch(loaderstate, ctx, mod) + root, isLocal, err = fetch(ld, ctx, mod) if err != nil { m.AddError(err) continue @@ -283,20 +283,20 @@ func walkFromIndex(index *modindex.Module, importPathRoot string, isMatch, treeC // // If m is the zero module.Version, MatchInModule matches the pattern // against the standard library (std and cmd) in GOROOT/src. -func MatchInModule(loaderstate *State, ctx context.Context, pattern string, m module.Version, tags map[string]bool) *search.Match { +func MatchInModule(ld *Loader, ctx context.Context, pattern string, m module.Version, tags map[string]bool) *search.Match { match := search.NewMatch(pattern) if m == (module.Version{}) { - matchPackages(loaderstate, ctx, match, tags, includeStd, nil) + matchPackages(ld, ctx, match, tags, includeStd, nil) } - LoadModFile(loaderstate, ctx) // Sets Target, needed by fetch and matchPackages. + LoadModFile(ld, ctx) // Sets Target, needed by fetch and matchPackages. if !match.IsLiteral() { - matchPackages(loaderstate, ctx, match, tags, omitStd, []module.Version{m}) + matchPackages(ld, ctx, match, tags, omitStd, []module.Version{m}) return match } - root, isLocal, err := fetch(loaderstate, ctx, m) + root, isLocal, err := fetch(ld, ctx, m) if err != nil { match.Errs = []error{err} return match @@ -322,7 +322,7 @@ func MatchInModule(loaderstate *State, ctx context.Context, pattern string, m mo // parseIgnorePatterns collects all ignore patterns associated with the // provided list of modules. // It returns a map of module root -> *search.IgnorePatterns. -func parseIgnorePatterns(loaderstate *State, ctx context.Context, treeCanMatch func(string) bool, modules []module.Version) map[string]*search.IgnorePatterns { +func parseIgnorePatterns(ld *Loader, ctx context.Context, treeCanMatch func(string) bool, modules []module.Version) map[string]*search.IgnorePatterns { ignorePatternsMap := make(map[string]*search.IgnorePatterns) for _, mod := range modules { if gover.IsToolchain(mod.Path) || !treeCanMatch(mod.Path) { @@ -330,12 +330,12 @@ func parseIgnorePatterns(loaderstate *State, ctx context.Context, treeCanMatch f } var modRoot string var ignorePatterns []string - if loaderstate.MainModules.Contains(mod.Path) { - modRoot = loaderstate.MainModules.ModRoot(mod) + if ld.MainModules.Contains(mod.Path) { + modRoot = ld.MainModules.ModRoot(mod) if modRoot == "" { continue } - modIndex := loaderstate.MainModules.Index(mod) + modIndex := ld.MainModules.Index(mod) if modIndex == nil { continue } @@ -344,11 +344,11 @@ func parseIgnorePatterns(loaderstate *State, ctx context.Context, treeCanMatch f // Skip getting ignore patterns for vendored modules because they // do not have go.mod files. var err error - modRoot, _, err = fetch(loaderstate, ctx, mod) + modRoot, _, err = fetch(ld, ctx, mod) if err != nil { continue } - summary, err := goModSummary(loaderstate, mod) + summary, err := goModSummary(ld, mod) if err != nil { continue } diff --git a/src/cmd/go/internal/modload/stat_openfile.go b/src/cmd/go/internal/modload/stat_openfile.go deleted file mode 100644 index 5773073d903554..00000000000000 --- a/src/cmd/go/internal/modload/stat_openfile.go +++ /dev/null @@ -1,28 +0,0 @@ -// Copyright 2019 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -//go:build (js && wasm) || plan9 - -// On plan9, per http://9p.io/magic/man2html/2/access: “Since file permissions -// are checked by the server and group information is not known to the client, -// access must open the file to check permissions.” -// -// js,wasm is similar, in that it does not define syscall.Access. - -package modload - -import ( - "io/fs" - "os" -) - -// hasWritePerm reports whether the current user has permission to write to the -// file with the given info. -func hasWritePerm(path string, _ fs.FileInfo) bool { - if f, err := os.OpenFile(path, os.O_WRONLY, 0); err == nil { - f.Close() - return true - } - return false -} diff --git a/src/cmd/go/internal/modload/stat_unix.go b/src/cmd/go/internal/modload/stat_unix.go deleted file mode 100644 index a0d5f4d2476ed1..00000000000000 --- a/src/cmd/go/internal/modload/stat_unix.go +++ /dev/null @@ -1,32 +0,0 @@ -// Copyright 2019 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -//go:build unix - -package modload - -import ( - "io/fs" - "os" - "syscall" -) - -// hasWritePerm reports whether the current user has permission to write to the -// file with the given info. -// -// Although the root user on most Unix systems can write to files even without -// permission, hasWritePerm reports false if no appropriate permission bit is -// set even if the current user is root. -func hasWritePerm(path string, fi fs.FileInfo) bool { - if os.Getuid() == 0 { - // The root user can access any file, but we still want to default to - // read-only mode if the go.mod file is marked as globally non-writable. - // (If the user really intends not to be in readonly mode, they can - // pass -mod=mod explicitly.) - return fi.Mode()&0222 != 0 - } - - const W_OK = 0x2 - return syscall.Access(path, W_OK) == nil -} diff --git a/src/cmd/go/internal/modload/stat_windows.go b/src/cmd/go/internal/modload/stat_windows.go deleted file mode 100644 index f29a99165e5300..00000000000000 --- a/src/cmd/go/internal/modload/stat_windows.go +++ /dev/null @@ -1,21 +0,0 @@ -// Copyright 2019 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -//go:build windows - -package modload - -import "io/fs" - -// hasWritePerm reports whether the current user has permission to write to the -// file with the given info. -func hasWritePerm(_ string, fi fs.FileInfo) bool { - // Windows has a read-only attribute independent of ACLs, so use that to - // determine whether the file is intended to be overwritten. - // - // Per https://golang.org/pkg/os/#Chmod: - // “On Windows, only the 0200 bit (owner writable) of mode is used; it - // controls whether the file's read-only attribute is set or cleared.” - return fi.Mode()&0200 != 0 -} diff --git a/src/cmd/go/internal/modload/vendor.go b/src/cmd/go/internal/modload/vendor.go index 1fc20ad398b363..577e8f67769e0e 100644 --- a/src/cmd/go/internal/modload/vendor.go +++ b/src/cmd/go/internal/modload/vendor.go @@ -140,10 +140,10 @@ func readVendorList(vendorDir string) { // checkVendorConsistency verifies that the vendor/modules.txt file matches (if // go 1.14) or at least does not contradict (go 1.13 or earlier) the // requirements and replacements listed in the main module's go.mod file. -func checkVendorConsistency(loaderstate *State, indexes []*modFileIndex, modFiles []*modfile.File, modRoots []string) { +func checkVendorConsistency(ld *Loader, indexes []*modFileIndex, modFiles []*modfile.File, modRoots []string) { // readVendorList only needs the main module to get the directory // the vendor directory is in. - readVendorList(VendorDir(loaderstate)) + readVendorList(VendorDir(ld)) if len(modFiles) < 1 { // We should never get here if there are zero modfiles. Either @@ -154,7 +154,7 @@ func checkVendorConsistency(loaderstate *State, indexes []*modFileIndex, modFile } pre114 := false - if !inWorkspaceMode(loaderstate) { // workspace mode was added after Go 1.14 + if !ld.inWorkspaceMode() { // workspace mode was added after Go 1.14 if len(indexes) != 1 { panic(fmt.Errorf("not in workspace mode but number of indexes is %v, not 1", len(indexes))) } @@ -215,8 +215,8 @@ func checkVendorConsistency(loaderstate *State, indexes []*modFileIndex, modFile continue // Don't print the same error more than once } seenrep[r.Old] = true - rNew, modRoot, replacementSource := replacementFrom(loaderstate, r.Old) - rNewCanonical := canonicalizeReplacePath(loaderstate, rNew, modRoot) + rNew, modRoot, replacementSource := replacementFrom(ld, r.Old) + rNewCanonical := canonicalizeReplacePath(ld, rNew, modRoot) vr := vendorMeta[r.Old].Replacement if vr == (module.Version{}) { if rNewCanonical == (module.Version{}) { @@ -236,8 +236,8 @@ func checkVendorConsistency(loaderstate *State, indexes []*modFileIndex, modFile for _, modFile := range modFiles { checkReplace(modFile.Replace) } - if loaderstate.MainModules.workFile != nil { - checkReplace(loaderstate.MainModules.workFile.Replace) + if ld.MainModules.workFile != nil { + checkReplace(ld.MainModules.workFile.Replace) } for _, mod := range vendorList { @@ -252,7 +252,7 @@ func checkVendorConsistency(loaderstate *State, indexes []*modFileIndex, modFile } if !foundRequire { article := "" - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { article = "a " } vendErrorf(mod, "is marked as explicit in vendor/modules.txt, but not explicitly required in %vgo.mod", article) @@ -262,9 +262,9 @@ func checkVendorConsistency(loaderstate *State, indexes []*modFileIndex, modFile } for _, mod := range vendorReplaced { - r := Replacement(loaderstate, mod) + r := Replacement(ld, mod) replacementSource := "go.mod" - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { replacementSource = "the workspace" } if r == (module.Version{}) { @@ -276,9 +276,9 @@ func checkVendorConsistency(loaderstate *State, indexes []*modFileIndex, modFile if vendErrors.Len() > 0 { subcmd := "mod" - if inWorkspaceMode(loaderstate) { + if ld.inWorkspaceMode() { subcmd = "work" } - base.Fatalf("go: inconsistent vendoring in %s:%s\n\n\tTo ignore the vendor directory, use -mod=readonly or -mod=mod.\n\tTo sync the vendor directory, run:\n\t\tgo %s vendor", filepath.Dir(VendorDir(loaderstate)), vendErrors, subcmd) + base.Fatalf("go: inconsistent vendoring in %s:%s\n\n\tTo ignore the vendor directory, use -mod=readonly or -mod=mod.\n\tTo sync the vendor directory, run:\n\t\tgo %s vendor", filepath.Dir(VendorDir(ld)), vendErrors, subcmd) } } diff --git a/src/cmd/go/internal/rf-cleanup.zsh b/src/cmd/go/internal/rf-cleanup.zsh deleted file mode 100755 index c805db56e3611e..00000000000000 --- a/src/cmd/go/internal/rf-cleanup.zsh +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env zsh - -set -eu -o pipefail - -# This is a large series of sed commands to cleanup after successful use of the -# `rf inject` command. This script will be used to refactor the codebase to -# eliminate global state within the module loader. Once that effort is -# complete, this script will be removed. - -find . -name '*.go' -exec \ - sed -i ' - # - # CompileAction does not use loaderstate. - # - s/CompileAction(loaderstate[^ ]* \*modload.State, /CompileAction(/g - s/CompileAction(modload.LoaderState[^,]*, /CompileAction(/g - s/CompileAction(loaderstate[^,]*, /CompileAction(/g - # - # cgoAction does not use loaderstate. - # - s/cgoAction(loaderstate \*modload\.State, /cgoAction(/g - s/cgoAction(loaderstate, /cgoAction(/g - s/cgoAction(loaderstate_, /cgoAction(/g - # - # Remove redundant mentions of LoaderState from function call sites. - # - s/(modload\.LoaderState_*, loaderstate,/(loaderstate,/g - s/(modload\.LoaderState_*, moduleLoaderState,/(moduleLoaderState,/g - s/(modload\.LoaderState_*, modload\.LoaderState/(modload.LoaderState/g - s/(modload\.LoaderState_*, loaderstate,/(loaderstate,/g - s/(modload\.LoaderState_*, moduleLoaderState,/(moduleLoaderState,/g - s/(modload\.LoaderState_*, modload\.LoaderState,/(modload.LoaderState,/g - s/(loaderstate_* \*modload.State, loaderstate \*modload.State/(loaderstate *modload.State/g - s/(loaderstate_* \*State, loaderstate \*State/(loaderstate *State/g - s/(loaderstate_*, loaderstate,/(loaderstate,/g - s/(LoaderState_*, loaderstate,/(loaderstate,/g - s/(LoaderState_*, loaderState,/(loaderState,/g - s/(LoaderState_*, LoaderState,/(LoaderState,/g - s/(LoaderState_*, LoaderState,/(LoaderState,/g - s/(moduleLoaderState_*, loaderstate,/(loaderstate,/g - s/(moduleLoaderState_*, moduleLoaderState,/(moduleLoaderState,/g - ' {} \; - diff --git a/src/cmd/go/internal/run/run.go b/src/cmd/go/internal/run/run.go index f821b37f292bfd..1725c7d04f9090 100644 --- a/src/cmd/go/internal/run/run.go +++ b/src/cmd/go/internal/run/run.go @@ -53,6 +53,10 @@ By default, 'go run' compiles the binary without generating the information used by debuggers, to reduce build time. To include debugger information in the binary, use 'go build'. +The go command places $GOROOT/bin at the beginning of $PATH in the +subprocess environment, so that subprocesses that execute 'go' commands +use the same 'go' as their parent. + The exit status of Run is not the exit status of the compiled binary. For more about build flags, see 'go help build'. @@ -71,22 +75,22 @@ func init() { } func runRun(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() if shouldUseOutsideModuleMode(args) { // Set global module flags for 'go run cmd@version'. // This must be done before modload.Init, but we need to call work.BuildInit // before loading packages, since it affects package locations, e.g., // for -race and -msan. - moduleLoaderState.ForceUseModules = true - moduleLoaderState.RootMode = modload.NoRoot - modload.AllowMissingModuleImports(moduleLoaderState) - modload.Init(moduleLoaderState) + moduleLoader.ForceUseModules = true + moduleLoader.RootMode = modload.NoRoot + moduleLoader.AllowMissingModuleImports() + modload.Init(moduleLoader) } else { - modload.InitWorkfile(moduleLoaderState) + moduleLoader.InitWorkfile() } - work.BuildInit(moduleLoaderState) - b := work.NewBuilder("", moduleLoaderState.VendorDirOrEmpty) + work.BuildInit(moduleLoader) + b := work.NewBuilder("", moduleLoader.VendorDirOrEmpty) defer func() { if err := b.Close(); err != nil { base.Fatal(err) @@ -108,18 +112,18 @@ func runRun(ctx context.Context, cmd *base.Command, args []string) { base.Fatalf("go: cannot run *_test.go files (%s)", file) } } - p = load.GoFilesPackage(moduleLoaderState, ctx, pkgOpts, files) + p = load.GoFilesPackage(moduleLoader, ctx, pkgOpts, files) } else if len(args) > 0 && !strings.HasPrefix(args[0], "-") { arg := args[0] var pkgs []*load.Package if strings.Contains(arg, "@") && !build.IsLocalImport(arg) && !filepath.IsAbs(arg) { var err error - pkgs, err = load.PackagesAndErrorsOutsideModule(moduleLoaderState, ctx, pkgOpts, args[:1]) + pkgs, err = load.PackagesAndErrorsOutsideModule(moduleLoader, ctx, pkgOpts, args[:1]) if err != nil { base.Fatal(err) } } else { - pkgs = load.PackagesAndErrors(moduleLoaderState, ctx, pkgOpts, args[:1]) + pkgs = load.PackagesAndErrors(moduleLoader, ctx, pkgOpts, args[:1]) } if len(pkgs) == 0 { @@ -141,7 +145,7 @@ func runRun(ctx context.Context, cmd *base.Command, args []string) { load.CheckPackageErrors([]*load.Package{p}) if cfg.BuildCover { - load.PrepareForCoverageBuild(moduleLoaderState, []*load.Package{p}) + load.PrepareForCoverageBuild(moduleLoader, []*load.Package{p}) } p.Internal.OmitDebug = true @@ -167,7 +171,7 @@ func runRun(ctx context.Context, cmd *base.Command, args []string) { p.Internal.ExeName = p.DefaultExecName() } - a1 := b.LinkAction(moduleLoaderState, work.ModeBuild, work.ModeBuild, p) + a1 := b.LinkAction(moduleLoader, work.ModeBuild, work.ModeBuild, p) a1.CacheExecutable = true a := &work.Action{Mode: "go run", Actor: work.ActorFunc(buildRunProgram), Args: cmdArgs, Deps: []*work.Action{a1}} b.Do(ctx, a) diff --git a/src/cmd/go/internal/telemetrystats/telemetrystats.go b/src/cmd/go/internal/telemetrystats/telemetrystats.go index 077c2d817f0e14..c6e58935bb0ee2 100644 --- a/src/cmd/go/internal/telemetrystats/telemetrystats.go +++ b/src/cmd/go/internal/telemetrystats/telemetrystats.go @@ -22,15 +22,26 @@ func Increment() { // incrementConfig increments counters for the configuration // the command is running in. func incrementConfig() { - if !modload.WillBeEnabled(modload.LoaderState) { + // TODO(jitsu): Telemetry for the go/mode counters should eventually be + // moved to modload.Init() + s := modload.NewLoader() + if !s.WillBeEnabled() { counter.Inc("go/mode:gopath") - } else if workfile := modload.FindGoWork(modload.LoaderState, base.Cwd()); workfile != "" { + } else if workfile := s.FindGoWork(base.Cwd()); workfile != "" { counter.Inc("go/mode:workspace") } else { counter.Inc("go/mode:module") } + + if cfg.BuildContext.CgoEnabled { + counter.Inc("go/cgo:enabled") + } else { + counter.Inc("go/cgo:disabled") + } + counter.Inc("go/platform/target/goos:" + cfg.Goos) counter.Inc("go/platform/target/goarch:" + cfg.Goarch) + counter.Inc("go/platform/target/port:" + cfg.Goos + "-" + cfg.Goarch) switch cfg.Goarch { case "386": counter.Inc("go/platform/target/go386:" + cfg.GO386) diff --git a/src/cmd/go/internal/test/test.go b/src/cmd/go/internal/test/test.go index 77fb9488ac03fe..2473c243e31159 100644 --- a/src/cmd/go/internal/test/test.go +++ b/src/cmd/go/internal/test/test.go @@ -78,11 +78,11 @@ As part of building a test binary, go test runs go vet on the package and its test source files to identify significant problems. If go vet finds any problems, go test reports those and does not run the test binary. Only a high-confidence subset of the default go vet checks are -used. That subset is: atomic, bool, buildtags, directive, errorsas, -ifaceassert, nilfunc, printf, stringintconv, and tests. You can see -the documentation for these and other vet tests via "go doc cmd/vet". -To disable the running of go vet, use the -vet=off flag. To run all -checks, use the -vet=all flag. +used. That subset is: atomic, bools, buildtag, directive, errorsas, +ifaceassert, nilfunc, printf, stdversion, stringintconv, and tests. +You can see the documentation for these and other vet tests via +"go doc cmd/vet". To disable the running of go vet, use the -vet=off flag. +To run all checks, use the -vet=all flag. All test output and summary lines are printed to the go command's standard output, even if the test printed them to its own standard @@ -162,8 +162,8 @@ In addition to the build flags, the flags handled by 'go test' itself are: Also emits build output in JSON. See 'go help buildjson'. -o file - Compile the test binary to the named file. - The test still runs (unless -c or -i is specified). + Save a copy of the test binary to the named file. + The test still runs (unless -c is specified). If file ends in a slash or names an existing directory, the test is written to pkg.test in that directory. @@ -654,37 +654,47 @@ func testShowPass() bool { var defaultVetFlags = []string{ // TODO(rsc): Decide which tests are enabled by default. // See golang.org/issue/18085. + // "-appends", // "-asmdecl", // "-assign", "-atomic", - "-bool", - "-buildtags", + "-bools", + "-buildtag", // "-cgocall", // "-composites", // "-copylocks", + // "-defers", "-directive", "-errorsas", + // "-framepointer", + // "-hostport", // "-httpresponse", "-ifaceassert", + // "-loopclosure", // "-lostcancel", - // "-methods", "-nilfunc", "-printf", - // "-rangeloops", // "-shift", + // "-sigchanyzer", "-slog", + // "-stdmethods", + "-stdversion", "-stringintconv", - // "-structtags", + // "-structtag", + // "-testinggoroutine", "-tests", + // "-timeformat", + // "-unmarshal", // "-unreachable", // "-unsafeptr", // "-unusedresult", + // "-waitgroup", } func runTest(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() pkgArgs, testArgs = testFlags(args) - modload.InitWorkfile(moduleLoaderState) // The test command does custom flag processing; initialize workspaces after that. + moduleLoader.InitWorkfile() // The test command does custom flag processing; initialize workspaces after that. if cfg.DebugTrace != "" { var close func() error @@ -705,13 +715,13 @@ func runTest(ctx context.Context, cmd *base.Command, args []string) { work.FindExecCmd() // initialize cached result - work.BuildInit(moduleLoaderState) + work.BuildInit(moduleLoader) work.VetFlags = testVet.flags work.VetExplicit = testVet.explicit work.VetTool = base.Tool("vet") pkgOpts := load.PackageOpts{ModResolveTests: true} - pkgs = load.PackagesAndErrors(moduleLoaderState, ctx, pkgOpts, pkgArgs) + pkgs = load.PackagesAndErrors(moduleLoader, ctx, pkgOpts, pkgArgs) // We *don't* call load.CheckPackageErrors here because we want to report // loading errors as per-package test setup errors later. if len(pkgs) == 0 { @@ -736,13 +746,13 @@ func runTest(ctx context.Context, cmd *base.Command, args []string) { // Otherwise, if fuzzing identifies a failure it could corrupt checksums in // the module cache (or permanently alter the behavior of std tests for all // users) by writing the failing input to the package's testdata directory. - // (See https://golang.org/issue/48495 and test_fuzz_modcache.txt.) - mainMods := moduleLoaderState.MainModules + // (See https://golang.org/issue/48495 and cmd/internal/fuzztest/test_fuzz_modcache.txt.) + mainMods := moduleLoader.MainModules if m := pkgs[0].Module; m != nil && m.Path != "" { if !mainMods.Contains(m.Path) { base.Fatalf("cannot use -fuzz flag on package outside the main module") } - } else if pkgs[0].Standard && modload.Enabled(moduleLoaderState) { + } else if pkgs[0].Standard && moduleLoader.Enabled() { // Because packages in 'std' and 'cmd' are part of the standard library, // they are only treated as part of a module in 'go mod' subcommands and // 'go get'. However, we still don't want to accidentally corrupt their @@ -855,7 +865,7 @@ func runTest(ctx context.Context, cmd *base.Command, args []string) { } } - b := work.NewBuilder("", moduleLoaderState.VendorDirOrEmpty) + b := work.NewBuilder("", moduleLoader.VendorDirOrEmpty) defer func() { if err := b.Close(); err != nil { base.Fatal(err) @@ -866,15 +876,15 @@ func runTest(ctx context.Context, cmd *base.Command, args []string) { var writeCoverMetaAct *work.Action if cfg.BuildCoverPkg != nil { - match := make([]func(*modload.State, *load.Package) bool, len(cfg.BuildCoverPkg)) + match := make([]func(*modload.Loader, *load.Package) bool, len(cfg.BuildCoverPkg)) for i := range cfg.BuildCoverPkg { match[i] = load.MatchPackage(cfg.BuildCoverPkg[i], base.Cwd()) } // Select for coverage all dependencies matching the -coverpkg // patterns. - plist := load.TestPackageList(moduleLoaderState, ctx, pkgOpts, pkgs) - testCoverPkgs = load.SelectCoverPackages(moduleLoaderState, plist, match, "test") + plist := load.TestPackageList(moduleLoader, ctx, pkgOpts, pkgs) + testCoverPkgs = load.SelectCoverPackages(moduleLoader, plist, match, "test") if len(testCoverPkgs) > 0 { // create a new singleton action that will collect up the // meta-data files from all of the packages mentioned in @@ -952,7 +962,7 @@ func runTest(ctx context.Context, cmd *base.Command, args []string) { "testing": true, "time": true, } - for _, p := range load.TestPackageList(moduleLoaderState, ctx, pkgOpts, pkgs) { + for _, p := range load.TestPackageList(moduleLoader, ctx, pkgOpts, pkgs) { if !skipInstrumentation[p.ImportPath] { p.Internal.FuzzInstrument = true } @@ -982,7 +992,7 @@ func runTest(ctx context.Context, cmd *base.Command, args []string) { // happens we'll wind up building the Q compile action // before updating its deps to include sync/atomic). if cfg.BuildCoverMode == "atomic" && p.ImportPath != "sync/atomic" { - load.EnsureImport(moduleLoaderState, p, "sync/atomic") + load.EnsureImport(moduleLoader, p, "sync/atomic") } // Tag the package for static meta-data generation if no // test files (this works only with the new coverage @@ -1049,7 +1059,7 @@ func runTest(ctx context.Context, cmd *base.Command, args []string) { reportSetupFailed(firstErrPkg, firstErrPkg.Error) continue } - buildTest, runTest, printTest, perr, err := builderTest(moduleLoaderState, b, ctx, pkgOpts, p, allImports[p], writeCoverMetaAct) + buildTest, runTest, printTest, perr, err := builderTest(moduleLoader, b, ctx, pkgOpts, p, allImports[p], writeCoverMetaAct) if err != nil { reportErr(perr, err) reportSetupFailed(perr, err) @@ -1130,7 +1140,7 @@ var windowsBadWords = []string{ "update", } -func builderTest(loaderstate *modload.State, b *work.Builder, ctx context.Context, pkgOpts load.PackageOpts, p *load.Package, imported bool, writeCoverMetaAct *work.Action) (buildAction, runAction, printAction *work.Action, perr *load.Package, err error) { +func builderTest(ld *modload.Loader, b *work.Builder, ctx context.Context, pkgOpts load.PackageOpts, p *load.Package, imported bool, writeCoverMetaAct *work.Action) (buildAction, runAction, printAction *work.Action, perr *load.Package, err error) { if len(p.TestGoFiles)+len(p.XTestGoFiles) == 0 { build := b.CompileAction(work.ModeBuild, work.ModeBuild, p) run := &work.Action{ @@ -1158,7 +1168,7 @@ func builderTest(loaderstate *modload.State, b *work.Builder, ctx context.Contex run.Deps = append(run.Deps, writeCoverMetaAct) writeCoverMetaAct.Deps = append(writeCoverMetaAct.Deps, build) } - addTestVet(loaderstate, b, p, run, nil) + addTestVet(ld, b, p, run, nil) print := &work.Action{ Mode: "test print", Actor: work.ActorFunc(builderPrintTest), @@ -1182,7 +1192,7 @@ func builderTest(loaderstate *modload.State, b *work.Builder, ctx context.Contex Paths: cfg.BuildCoverPkg, } } - pmain, ptest, pxtest, perr := load.TestPackagesFor(loaderstate, ctx, pkgOpts, p, cover) + pmain, ptest, pxtest, perr := load.TestPackagesFor(ld, ctx, pkgOpts, p, cover) if perr != nil { return nil, nil, nil, perr, perr.Error } @@ -1222,7 +1232,7 @@ func builderTest(loaderstate *modload.State, b *work.Builder, ctx context.Contex } } - a := b.LinkAction(loaderstate, work.ModeBuild, work.ModeBuild, pmain) + a := b.LinkAction(ld, work.ModeBuild, work.ModeBuild, pmain) a.Target = testDir + testBinary + cfg.ExeSuffix if cfg.Goos == "windows" { // There are many reserved words on Windows that, @@ -1348,10 +1358,10 @@ func builderTest(loaderstate *modload.State, b *work.Builder, ctx context.Contex } if len(ptest.GoFiles)+len(ptest.CgoFiles) > 0 { - addTestVet(loaderstate, b, ptest, vetRunAction, installAction) + addTestVet(ld, b, ptest, vetRunAction, installAction) } if pxtest != nil { - addTestVet(loaderstate, b, pxtest, vetRunAction, installAction) + addTestVet(ld, b, pxtest, vetRunAction, installAction) } if installAction != nil { @@ -1366,12 +1376,12 @@ func builderTest(loaderstate *modload.State, b *work.Builder, ctx context.Contex return buildAction, runAction, printAction, nil, nil } -func addTestVet(loaderstate *modload.State, b *work.Builder, p *load.Package, runAction, installAction *work.Action) { +func addTestVet(ld *modload.Loader, b *work.Builder, p *load.Package, runAction, installAction *work.Action) { if testVet.off { return } - vet := b.VetAction(loaderstate, work.ModeBuild, work.ModeBuild, p) + vet := b.VetAction(ld, work.ModeBuild, work.ModeBuild, false, p) runAction.Deps = append(runAction.Deps, vet) // Install will clean the build directory. // Make sure vet runs first. @@ -1405,9 +1415,10 @@ type runTestActor struct { type runCache struct { disableCache bool // cache should be disabled for this run - buf *bytes.Buffer - id1 cache.ActionID - id2 cache.ActionID + buf *bytes.Buffer + id1 cache.ActionID + id2 cache.ActionID + covMeta cache.ActionID // Hash of writeCoverMetaAct dependencies, for invalidating coverage profiles } func coverProfTempFile(a *work.Action) string { @@ -1800,6 +1811,33 @@ func (c *runCache) tryCacheWithID(b *work.Builder, a *work.Action, id string) bo return false } + // If we are collecting coverage for out-of-band packages (-coverpkg), + // find the writeCoverMetaAct among the run action's dependencies and hash + // its deps to ensure the cache invalidates when covered packages change. + // Note: the run action's original deps may be wrapped inside a "test barrier" + // action, so we search both a.Deps and any barrier's deps. + if len(testCoverPkgs) != 0 { + searchDeps := a.Deps + for _, dep := range a.Deps { + if dep.Mode == "test barrier" { + searchDeps = dep.Deps + break + } + } + for _, dep := range searchDeps { + if dep.Mode == "write coverage meta-data file" { + h := cache.NewHash("covermeta") + for _, metaDep := range dep.Deps { + if aid := metaDep.BuildActionID(); aid != "" { + fmt.Fprintf(h, "dep %s\n", aid) + } + } + c.covMeta = h.Sum() + break + } + } + } + var cacheArgs []string for _, arg := range testArgs { i := strings.Index(arg, "=") @@ -1906,7 +1944,7 @@ func (c *runCache) tryCacheWithID(b *work.Builder, a *work.Action, id string) bo // Merge cached cover profile data to cover profile. if testCoverProfile != "" { // Specifically ignore entry as it will be the same as above. - cpData, _, err := cache.GetFile(cache.Default(), coverProfileAndInputKey(testID, testInputsID)) + cpData, _, err := cache.GetFile(cache.Default(), coverProfileAndInputKey(testID, testInputsID, c.covMeta)) if err != nil { if cache.DebugTest { fmt.Fprintf(os.Stderr, "testcache: %s: cached cover profile missing: %v\n", a.Package.ImportPath, err) @@ -1914,6 +1952,18 @@ func (c *runCache) tryCacheWithID(b *work.Builder, a *work.Action, id string) bo return false } mergeCoverProfile(cpData) + } else if c.covMeta != (cache.ActionID{}) { + // If we have a coverage metadata hash but no testCoverProfile, we're collecting + // coverage for out-of-band packages. Check if the coverage profile cache is still + // valid. If c.covMeta changed (meaning a covered package changed), the coverage + // profile cache will miss and we need to re-run the test. + _, _, err := cache.GetFile(cache.Default(), coverProfileAndInputKey(testID, testInputsID, c.covMeta)) + if err != nil { + if cache.DebugTest { + fmt.Fprintf(os.Stderr, "testcache: %s: coverage metadata changed, re-running test: %v\n", a.Package.ImportPath, err) + } + return false + } } if len(data) == 0 || data[len(data)-1] != '\n' { @@ -2104,9 +2154,15 @@ func testAndInputKey(testID, testInputsID cache.ActionID) cache.ActionID { return cache.Subkey(testID, fmt.Sprintf("inputs:%x", testInputsID)) } -// coverProfileAndInputKey returns the "coverprofile" cache key for the pair (testID, testInputsID). -func coverProfileAndInputKey(testID, testInputsID cache.ActionID) cache.ActionID { - return cache.Subkey(testAndInputKey(testID, testInputsID), "coverprofile") +// coverProfileAndInputKey returns the "coverprofile" cache key. +// If covMetaID is non-zero, it is included in the hash to ensure coverage profiles are invalidated +// when the coverage metadata changes (e.g., when source files in covered packages are modified). +func coverProfileAndInputKey(testID, testInputsID, covMetaID cache.ActionID) cache.ActionID { + key := testAndInputKey(testID, testInputsID) + if covMetaID != (cache.ActionID{}) { + key = cache.Subkey(key, fmt.Sprintf("coverdeps:%x", covMetaID)) + } + return cache.Subkey(key, "coverprofile") } func (c *runCache) saveOutput(a *work.Action) { @@ -2147,7 +2203,11 @@ func (c *runCache) saveOutput(a *work.Action) { cache.PutNoVerify(cache.Default(), c.id1, bytes.NewReader(testlog)) cache.PutNoVerify(cache.Default(), testAndInputKey(c.id1, testInputsID), bytes.NewReader(a.TestOutput.Bytes())) if coverProfile != nil { - cache.PutNoVerify(cache.Default(), coverProfileAndInputKey(c.id1, testInputsID), bytes.NewReader(coverProfile)) + cache.PutNoVerify(cache.Default(), coverProfileAndInputKey(c.id1, testInputsID, c.covMeta), bytes.NewReader(coverProfile)) + } else if c.covMeta != (cache.ActionID{}) { + // Write a sentinel so the else-if branch in tryCacheWithID can verify + // that the covMeta hash has not changed since the last run. + cache.PutNoVerify(cache.Default(), coverProfileAndInputKey(c.id1, testInputsID, c.covMeta), bytes.NewReader(nil)) } } if c.id2 != (cache.ActionID{}) { @@ -2157,7 +2217,10 @@ func (c *runCache) saveOutput(a *work.Action) { cache.PutNoVerify(cache.Default(), c.id2, bytes.NewReader(testlog)) cache.PutNoVerify(cache.Default(), testAndInputKey(c.id2, testInputsID), bytes.NewReader(a.TestOutput.Bytes())) if coverProfile != nil { - cache.PutNoVerify(cache.Default(), coverProfileAndInputKey(c.id2, testInputsID), bytes.NewReader(coverProfile)) + cache.PutNoVerify(cache.Default(), coverProfileAndInputKey(c.id2, testInputsID, c.covMeta), bytes.NewReader(coverProfile)) + } else if c.covMeta != (cache.ActionID{}) { + // Sentinel for covMeta validity; see comment in id1 block above. + cache.PutNoVerify(cache.Default(), coverProfileAndInputKey(c.id2, testInputsID, c.covMeta), bytes.NewReader(nil)) } } } diff --git a/src/cmd/go/internal/test/testflag.go b/src/cmd/go/internal/test/testflag.go index d6891a1d0b955b..ab3c9a16b67ad5 100644 --- a/src/cmd/go/internal/test/testflag.go +++ b/src/cmd/go/internal/test/testflag.go @@ -175,9 +175,6 @@ func (f *vetFlag) Set(value string) error { if len(f.flags) > 1 && single != "" { return fmt.Errorf("-vet does not accept %q in a list with other analyzers", single) } - if len(f.flags) > 1 && single != "" { - return fmt.Errorf("-vet does not accept %q in a list with other analyzers", single) - } return nil } diff --git a/src/cmd/go/internal/tool/signal.go b/src/cmd/go/internal/tool/signal.go new file mode 100644 index 00000000000000..a6525c8d686ceb --- /dev/null +++ b/src/cmd/go/internal/tool/signal.go @@ -0,0 +1,14 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build !plan9 && !js + +package tool + +import ( + "os" + "syscall" +) + +var signalsToForward = []os.Signal{syscall.SIGHUP, os.Interrupt, syscall.SIGQUIT, syscall.SIGTERM} diff --git a/src/cmd/go/internal/tool/signal_js.go b/src/cmd/go/internal/tool/signal_js.go new file mode 100644 index 00000000000000..064f88ffb226c3 --- /dev/null +++ b/src/cmd/go/internal/tool/signal_js.go @@ -0,0 +1,14 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build js + +package tool + +import ( + "os" + "syscall" +) + +var signalsToForward = []os.Signal{os.Interrupt, syscall.SIGQUIT, syscall.SIGTERM} diff --git a/src/cmd/go/internal/tool/signal_plan9.go b/src/cmd/go/internal/tool/signal_plan9.go new file mode 100644 index 00000000000000..45fa878a684bd9 --- /dev/null +++ b/src/cmd/go/internal/tool/signal_plan9.go @@ -0,0 +1,14 @@ +// Copyright 2012 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build plan9 + +package tool + +import ( + "os" + "syscall" +) + +var signalsToForward = []os.Signal{syscall.SIGHUP, os.Interrupt, syscall.SIGTERM} diff --git a/src/cmd/go/internal/tool/tool.go b/src/cmd/go/internal/tool/tool.go index e283c7354f5a34..97c27c8caa44d6 100644 --- a/src/cmd/go/internal/tool/tool.go +++ b/src/cmd/go/internal/tool/tool.go @@ -40,7 +40,14 @@ var CmdTool = &base.Command{ Tool runs the go tool command identified by the arguments. Go ships with a number of builtin tools, and additional tools -may be defined in the go.mod of the current module. +may be defined in the go.mod of the current module. 'go get -tool' +can be used to define additional tools in the current module's +go.mod file. See 'go help get' for more information. + +The command can be specified using the full package path to the tool declared with +a tool directive. The default binary name of the tool, which is the last component of +the package path, excluding the major version suffix, can also be used if it is unique +among declared tools. With no arguments it prints the list of known tools. @@ -52,6 +59,10 @@ instead of the go.mod in the module root directory. Tool also provides the -C, -overlay, and -modcacherw build flags. +The go command places $GOROOT/bin at the beginning of $PATH in the +environment of commands run via tool directives, so that they use the +same 'go' as the parent 'go tool'. + For more about build flags, see 'go help build'. For more about each builtin tool command, see 'go doc cmd/'. @@ -78,10 +89,10 @@ func init() { } func runTool(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() if len(args) == 0 { counter.Inc("go/subcommand:tool") - listTools(moduleLoaderState, ctx) + listTools(moduleLoader, ctx) return } toolName := args[0] @@ -109,14 +120,14 @@ func runTool(ctx context.Context, cmd *base.Command, args []string) { if tool := loadBuiltinTool(toolName); tool != "" { // Increment a counter for the tool subcommand with the tool name. counter.Inc("go/subcommand:tool-" + toolName) - buildAndRunBuiltinTool(moduleLoaderState, ctx, toolName, tool, args[1:]) + buildAndRunBuiltinTool(moduleLoader, ctx, toolName, tool, args[1:]) return } // Try to build and run mod tool. - tool := loadModTool(moduleLoaderState, ctx, toolName) + tool := loadModTool(moduleLoader, ctx, toolName) if tool != "" { - buildAndRunModtool(moduleLoaderState, ctx, toolName, tool, args[1:]) + buildAndRunModtool(moduleLoader, ctx, toolName, tool, args[1:]) return } @@ -133,7 +144,7 @@ func runTool(ctx context.Context, cmd *base.Command, args []string) { } // listTools prints a list of the available tools in the tools directory. -func listTools(loaderstate *modload.State, ctx context.Context) { +func listTools(ld *modload.Loader, ctx context.Context) { f, err := os.Open(build.ToolDir) if err != nil { fmt.Fprintf(os.Stderr, "go: no tool directory: %s\n", err) @@ -148,8 +159,11 @@ func listTools(loaderstate *modload.State, ctx context.Context) { return } + ambiguous := make(map[string]bool) // names that can't be used as aliases because they are ambiguous sort.Strings(names) for _, name := range names { + ambiguous[name] = true + // Unify presentation by going to lower case. // If it's windows, don't show the .exe suffix. name = strings.TrimSuffix(strings.ToLower(name), cfg.ToolExeSuffix()) @@ -162,10 +176,26 @@ func listTools(loaderstate *modload.State, ctx context.Context) { fmt.Println(name) } - modload.InitWorkfile(loaderstate) - modload.LoadModFile(loaderstate, ctx) - modTools := slices.Sorted(maps.Keys(loaderstate.MainModules.Tools())) + ld.InitWorkfile() + modload.LoadModFile(ld, ctx) + modTools := slices.Sorted(maps.Keys(ld.MainModules.Tools())) + seen := make(map[string]bool) // aliases we've seen already + for _, tool := range modTools { + alias := defaultExecName(tool) + switch { + case ambiguous[alias]: + continue + case seen[alias]: + ambiguous[alias] = true + default: + seen[alias] = true + } + } for _, tool := range modTools { + if alias := defaultExecName(tool); !ambiguous[alias] { + fmt.Printf("%s (%s)\n", alias, tool) + continue + } fmt.Println(tool) } } @@ -252,12 +282,12 @@ func loadBuiltinTool(toolName string) string { return cmdTool } -func loadModTool(loaderstate *modload.State, ctx context.Context, name string) string { - modload.InitWorkfile(loaderstate) - modload.LoadModFile(loaderstate, ctx) +func loadModTool(ld *modload.Loader, ctx context.Context, name string) string { + ld.InitWorkfile() + modload.LoadModFile(ld, ctx) matches := []string{} - for tool := range loaderstate.MainModules.Tools() { + for tool := range ld.MainModules.Tools() { if tool == name || defaultExecName(tool) == name { matches = append(matches, tool) } @@ -301,7 +331,7 @@ func builtTool(runAction *work.Action) string { return linkAction.BuiltTarget() } -func buildAndRunBuiltinTool(loaderstate *modload.State, ctx context.Context, toolName, tool string, args []string) { +func buildAndRunBuiltinTool(ld *modload.Loader, ctx context.Context, toolName, tool string, args []string) { // Override GOOS and GOARCH for the build to build the tool using // the same GOOS and GOARCH as this go command. cfg.ForceHost() @@ -309,17 +339,17 @@ func buildAndRunBuiltinTool(loaderstate *modload.State, ctx context.Context, too // Ignore go.mod and go.work: we don't need them, and we want to be able // to run the tool even if there's an issue with the module or workspace the // user happens to be in. - loaderstate.RootMode = modload.NoRoot + ld.RootMode = modload.NoRoot runFunc := func(b *work.Builder, ctx context.Context, a *work.Action) error { cmdline := str.StringList(builtTool(a), a.Args) return runBuiltTool(toolName, nil, cmdline) } - buildAndRunTool(loaderstate, ctx, tool, args, runFunc) + buildAndRunTool(ld, ctx, tool, args, runFunc) } -func buildAndRunModtool(loaderstate *modload.State, ctx context.Context, toolName, tool string, args []string) { +func buildAndRunModtool(ld *modload.Loader, ctx context.Context, toolName, tool string, args []string) { runFunc := func(b *work.Builder, ctx context.Context, a *work.Action) error { // Use the ExecCmd to run the binary, as go run does. ExecCmd allows users // to provide a runner to run the binary, for example a simulator for binaries @@ -333,12 +363,12 @@ func buildAndRunModtool(loaderstate *modload.State, ctx context.Context, toolNam return runBuiltTool(toolName, env, cmdline) } - buildAndRunTool(loaderstate, ctx, tool, args, runFunc) + buildAndRunTool(ld, ctx, tool, args, runFunc) } -func buildAndRunTool(loaderstate *modload.State, ctx context.Context, tool string, args []string, runTool work.ActorFunc) { - work.BuildInit(loaderstate) - b := work.NewBuilder("", loaderstate.VendorDirOrEmpty) +func buildAndRunTool(ld *modload.Loader, ctx context.Context, tool string, args []string, runTool work.ActorFunc) { + work.BuildInit(ld) + b := work.NewBuilder("", ld.VendorDirOrEmpty) defer func() { if err := b.Close(); err != nil { base.Fatal(err) @@ -346,11 +376,11 @@ func buildAndRunTool(loaderstate *modload.State, ctx context.Context, tool strin }() pkgOpts := load.PackageOpts{MainOnly: true} - p := load.PackagesAndErrors(loaderstate, ctx, pkgOpts, []string{tool})[0] + p := load.PackagesAndErrors(ld, ctx, pkgOpts, []string{tool})[0] p.Internal.OmitDebug = true p.Internal.ExeName = p.DefaultExecName() - a1 := b.LinkAction(loaderstate, work.ModeBuild, work.ModeBuild, p) + a1 := b.LinkAction(ld, work.ModeBuild, work.ModeBuild, p) a1.CacheExecutable = true a := &work.Action{Mode: "go tool", Actor: runTool, Args: args, Deps: []*work.Action{a1}} b.Do(ctx, a) @@ -373,7 +403,7 @@ func runBuiltTool(toolName string, env, cmdline []string) error { err := toolCmd.Start() if err == nil { c := make(chan os.Signal, 100) - signal.Notify(c) + signal.Notify(c, signalsToForward...) go func() { for sig := range c { toolCmd.Process.Signal(sig) @@ -394,7 +424,13 @@ func runBuiltTool(toolName string, env, cmdline []string) error { fmt.Fprintf(os.Stderr, "go tool %s: %s\n", toolName, err) } if ok { - base.SetExitStatus(e.ExitCode()) + n := e.ExitCode() + if n == -1 { + // If the tool was terminated by a signal, + // set a non-zero exit status. See go.dev/issue/79540. + n = 1 + } + base.SetExitStatus(n) } else { base.SetExitStatus(1) } diff --git a/src/cmd/go/internal/toolchain/select.go b/src/cmd/go/internal/toolchain/select.go index 86aa89dd7d4a1d..bd2ae4ee2ed030 100644 --- a/src/cmd/go/internal/toolchain/select.go +++ b/src/cmd/go/internal/toolchain/select.go @@ -25,7 +25,6 @@ import ( "cmd/go/internal/base" "cmd/go/internal/cfg" "cmd/go/internal/gover" - "cmd/go/internal/modfetch" "cmd/go/internal/modload" "cmd/go/internal/run" "cmd/go/internal/work" @@ -86,8 +85,10 @@ func FilterEnv(env []string) []string { return out } -var counterErrorsInvalidToolchainInFile = counter.New("go/errors:invalid-toolchain-in-file") -var toolchainTrace = godebug.New("#toolchaintrace").Value() == "1" +var ( + counterErrorsInvalidToolchainInFile = counter.New("go/errors:invalid-toolchain-in-file") + toolchainTrace = godebug.New("#toolchaintrace").Value() == "1" +) // Select invokes a different Go toolchain if directed by // the GOTOOLCHAIN environment variable or the user's configuration @@ -95,11 +96,11 @@ var toolchainTrace = godebug.New("#toolchaintrace").Value() == "1" // It must be called early in startup. // See https://go.dev/doc/toolchain#select. func Select() { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() log.SetPrefix("go: ") defer log.SetPrefix("") - if !modload.WillBeEnabled(moduleLoaderState) { + if !moduleLoader.WillBeEnabled() { return } @@ -172,7 +173,7 @@ func Select() { gotoolchain = minToolchain if mode == "auto" || mode == "path" { // Read go.mod to find new minimum and suggested toolchain. - file, goVers, toolchain := modGoToolchain(moduleLoaderState) + file, goVers, toolchain := modGoToolchain(moduleLoader) gover.Startup.AutoFile = file if toolchain == "default" { // "default" means always use the default toolchain, @@ -232,7 +233,7 @@ func Select() { } } } - maybeSwitchForGoInstallVersion(moduleLoaderState, minVers) + maybeSwitchForGoInstallVersion(moduleLoader, minVers) } // If we are invoked as a target toolchain, confirm that @@ -284,7 +285,8 @@ func Select() { } counterSelectExec.Inc() - Exec(moduleLoaderState, gotoolchain) + Exec(moduleLoader, gotoolchain) + panic("unreachable") } var counterSelectExec = counter.New("go/toolchain/select-exec") @@ -301,7 +303,7 @@ var TestVersionSwitch string // If $GOTOOLCHAIN is set to path or min+path, Exec only considers the PATH // as a source of Go toolchains. Otherwise Exec tries the PATH but then downloads // a toolchain if necessary. -func Exec(s *modload.State, gotoolchain string) { +func Exec(s *modload.Loader, gotoolchain string) { log.SetPrefix("go: ") writeBits = sysWriteBits() @@ -352,12 +354,6 @@ func Exec(s *modload.State, gotoolchain string) { base.Fatalf("cannot find %q in PATH", gotoolchain) } - // Set up modules without an explicit go.mod, to download distribution. - s.Reset() - s.ForceUseModules = true - s.RootMode = modload.NoRoot - modload.Init(s) - // Download and unpack toolchain module into module cache. // Note that multiple go commands might be doing this at the same time, // and that's OK: the module cache handles that case correctly. @@ -365,7 +361,7 @@ func Exec(s *modload.State, gotoolchain string) { Path: gotoolchainModule, Version: gotoolchainVersion + "-" + gotoolchain + "." + runtime.GOOS + "-" + runtime.GOARCH, } - dir, err := modfetch.Download(context.Background(), m) + dir, err := s.Fetcher().Download(context.Background(), m) if err != nil { if errors.Is(err, fs.ErrNotExist) { toolVers := gover.FromToolchain(gotoolchain) @@ -385,7 +381,7 @@ func Exec(s *modload.State, gotoolchain string) { if err != nil { base.Fatalf("download %s: %v", gotoolchain, err) } - if info.Mode()&0111 == 0 { + if info.Mode()&0o111 == 0 { // allowExec sets the exec permission bits on all files found in dir if pattern is the empty string, // or only those files that match the pattern if it's non-empty. allowExec := func(dir, pattern string) { @@ -404,7 +400,7 @@ func Exec(s *modload.State, gotoolchain string) { if err != nil { return err } - if err := os.Chmod(path, info.Mode()&0777|0111); err != nil { + if err := os.Chmod(path, info.Mode()&0o777|0o111); err != nil { return err } } @@ -528,9 +524,9 @@ func raceSafeCopy(old, new string) error { // modGoToolchain finds the enclosing go.work or go.mod file // and returns the go version and toolchain lines from the file. // The toolchain line overrides the version line -func modGoToolchain(loaderstate *modload.State) (file, goVers, toolchain string) { +func modGoToolchain(ld *modload.Loader) (file, goVers, toolchain string) { wd := base.UncachedCwd() - file = modload.FindGoWork(loaderstate, wd) + file = ld.FindGoWork(wd) // $GOWORK can be set to a file that does not yet exist, if we are running 'go work init'. // Do not try to load the file in that case if _, err := os.Stat(file); err != nil { @@ -552,7 +548,7 @@ func modGoToolchain(loaderstate *modload.State) (file, goVers, toolchain string) // maybeSwitchForGoInstallVersion reports whether the command line is go install m@v or go run m@v. // If so, switch to the go version required to build m@v if it's higher than minVers. -func maybeSwitchForGoInstallVersion(loaderstate *modload.State, minVers string) { +func maybeSwitchForGoInstallVersion(ld *modload.Loader, minVers string) { // Note: We assume there are no flags between 'go' and 'install' or 'run'. // During testing there are some debugging flags that are accepted // in that position, but in production go binaries there are not. @@ -630,7 +626,7 @@ func maybeSwitchForGoInstallVersion(loaderstate *modload.State, minVers string) continue } - f := run.CmdRun.Flag.Lookup(a) + f := cmdFlags.Lookup(a) if f == nil { // We don't know whether this flag is a boolean. if os.Args[1] == "run" { @@ -662,6 +658,9 @@ func maybeSwitchForGoInstallVersion(loaderstate *modload.State, minVers string) } if bf, ok := f.Value.(interface{ IsBoolFlag() bool }); !ok || !bf.IsBoolFlag() { + if len(args) == 0 { + return + } // The next arg is the value for this flag. Skip it. args = args[1:] continue @@ -671,7 +670,10 @@ func maybeSwitchForGoInstallVersion(loaderstate *modload.State, minVers string) if !strings.Contains(pkgArg, "@") || build.IsLocalImport(pkgArg) || filepath.IsAbs(pkgArg) { return } - path, version, _ := strings.Cut(pkgArg, "@") + path, version, _, err := modload.ParsePathVersion(pkgArg) + if err != nil { + base.Fatalf("go: %v", err) + } if path == "" || version == "" || gover.IsToolchain(path) { return } @@ -693,27 +695,27 @@ func maybeSwitchForGoInstallVersion(loaderstate *modload.State, minVers string) // command lines if we add new flags in the future. // Set up modules without an explicit go.mod, to download go.mod. - loaderstate.ForceUseModules = true - loaderstate.RootMode = modload.NoRoot - modload.Init(loaderstate) - defer loaderstate.Reset() + ld.ForceUseModules = true + ld.RootMode = modload.NoRoot + modload.Init(ld) + defer ld.Reset() // See internal/load.PackagesAndErrorsOutsideModule ctx := context.Background() - allowed := loaderstate.CheckAllowed + allowed := ld.CheckAllowed if modload.IsRevisionQuery(path, version) { // Don't check for retractions if a specific revision is requested. allowed = nil } noneSelected := func(path string) (version string) { return "none" } - _, err := modload.QueryPackages(loaderstate, ctx, path, version, noneSelected, allowed) + _, err = modload.QueryPackages(ld, ctx, path, version, noneSelected, allowed) if errors.Is(err, gover.ErrTooNew) { // Run early switch, same one go install or go run would eventually do, // if it understood all the command-line flags. - s := NewSwitcher(loaderstate) + s := NewSwitcher(ld) s.Error(err) if s.TooNew != nil && gover.Compare(s.TooNew.GoVersion, minVers) > 0 { - SwitchOrFatal(loaderstate, ctx, err) + SwitchOrFatal(ld, ctx, err) } } } diff --git a/src/cmd/go/internal/toolchain/switch.go b/src/cmd/go/internal/toolchain/switch.go index 76b608fdef4157..b6a8910ff7f896 100644 --- a/src/cmd/go/internal/toolchain/switch.go +++ b/src/cmd/go/internal/toolchain/switch.go @@ -32,14 +32,14 @@ import ( // // See https://go.dev/doc/toolchain#switch. type Switcher struct { - TooNew *gover.TooNewError // max go requirement observed - Errors []error // errors collected so far - loaderstate *modload.State // temporarily here while we eliminate global module loader state + TooNew *gover.TooNewError // max go requirement observed + Errors []error // errors collected so far + ld *modload.Loader // temporarily here while we eliminate global module loader state } -func NewSwitcher(s *modload.State) *Switcher { +func NewSwitcher(s *modload.Loader) *Switcher { sw := new(Switcher) - sw.loaderstate = s + sw.ld = s return sw } @@ -97,7 +97,7 @@ func (s *Switcher) Switch(ctx context.Context) { } // Switch to newer Go toolchain if necessary and possible. - tv, err := NewerToolchain(ctx, s.TooNew.GoVersion) + tv, err := NewerToolchain(ctx, s.ld.Fetcher(), s.TooNew.GoVersion) if err != nil { for _, err := range s.Errors { base.Error(err) @@ -108,7 +108,7 @@ func (s *Switcher) Switch(ctx context.Context) { fmt.Fprintf(os.Stderr, "go: %v requires go >= %v; switching to %v\n", s.TooNew.What, s.TooNew.GoVersion, tv) counterSwitchExec.Inc() - Exec(s.loaderstate, tv) + Exec(s.ld, tv) panic("unreachable") } @@ -116,8 +116,8 @@ var counterSwitchExec = counter.New("go/toolchain/switch-exec") // SwitchOrFatal attempts a toolchain switch based on the information in err // and otherwise falls back to base.Fatal(err). -func SwitchOrFatal(loaderstate *modload.State, ctx context.Context, err error) { - s := NewSwitcher(loaderstate) +func SwitchOrFatal(ld *modload.Loader, ctx context.Context, err error) { + s := NewSwitcher(ld) s.Error(err) s.Switch(ctx) base.Exit() @@ -130,8 +130,11 @@ func SwitchOrFatal(loaderstate *modload.State, ctx context.Context, err error) { // If the latest major release is 1.N.0, we use the latest patch release of 1.(N-1) if that's >= version. // Otherwise we use the latest 1.N if that's allowed. // Otherwise we use the latest release. -func NewerToolchain(ctx context.Context, version string) (string, error) { - fetch := autoToolchains +func NewerToolchain(ctx context.Context, f *modfetch.Fetcher, version string) (string, error) { + fetch := func(ctx context.Context) ([]string, error) { + return autoToolchains(ctx, f) + } + if !HasAuto() { fetch = pathToolchains } @@ -143,10 +146,10 @@ func NewerToolchain(ctx context.Context, version string) (string, error) { } // autoToolchains returns the list of toolchain versions available to GOTOOLCHAIN=auto or =min+auto mode. -func autoToolchains(ctx context.Context) ([]string, error) { +func autoToolchains(ctx context.Context, f *modfetch.Fetcher) ([]string, error) { var versions *modfetch.Versions err := modfetch.TryProxies(func(proxy string) error { - v, err := modfetch.Lookup(ctx, proxy, "go").Versions(ctx, "") + v, err := f.Lookup(ctx, proxy, "go").Versions(ctx, "") if err != nil { return err } diff --git a/src/cmd/go/internal/vcs/vcs.go b/src/cmd/go/internal/vcs/vcs.go index 7c198c5f2b442a..fd6e87803c8e1d 100644 --- a/src/cmd/go/internal/vcs/vcs.go +++ b/src/cmd/go/internal/vcs/vcs.go @@ -11,13 +11,11 @@ import ( "internal/godebug" "internal/lazyregexp" "internal/singleflight" - "io/fs" "log" urlpkg "net/url" "os" "os/exec" "path/filepath" - "regexp" "strconv" "strings" "sync" @@ -29,6 +27,7 @@ import ( "cmd/go/internal/str" "cmd/go/internal/web" "cmd/internal/pathcache" + "cmd/internal/telemetry/counter" "golang.org/x/mod/module" ) @@ -36,25 +35,15 @@ import ( // A Cmd describes how to use a version control system // like Mercurial, Git, or Subversion. type Cmd struct { - Name string - Cmd string // name of binary to invoke command - Env []string // any environment values to set/override - RootNames []rootName // filename and mode indicating the root of a checkout directory - - CreateCmd []string // commands to download a fresh copy of a repository - DownloadCmd []string // commands to download updates into an existing repository - - TagCmd []tagCmd // commands to list tags - TagLookupCmd []tagCmd // commands to lookup tags before running tagSyncCmd - TagSyncCmd []string // commands to sync to specific tag - TagSyncDefault []string // commands to sync to default tag + Name string + Cmd string // name of binary to invoke command + Env []string // any environment values to set/override + Roots []isVCSRoot // filters to identify repository root directories Scheme []string PingCmd string - RemoteRepo func(v *Cmd, rootDir string) (remoteRepo string, err error) - ResolveRepo func(v *Cmd, rootDir, remoteRepo string) (realRepo string, err error) - Status func(v *Cmd, rootDir string) (Status, error) + Status func(v *Cmd, rootDir string) (Status, error) } // Status is the current state of a local repository. @@ -83,7 +72,6 @@ var ( var defaultSecureScheme = map[string]bool{ "https": true, "git+ssh": true, - "bzr+ssh": true, "svn+ssh": true, "ssh": true, } @@ -133,16 +121,15 @@ var vcsList = []*Cmd{ vcsHg, vcsGit, vcsSvn, - vcsBzr, vcsFossil, } // vcsMod is a stub for the "mod" scheme. It's returned by -// repoRootForImportPathDynamic, but is otherwise not treated as a VCS command. +// repoRootForImportDynamic, but is otherwise not treated as a VCS command. var vcsMod = &Cmd{Name: "mod"} // vcsByCmd returns the version control system for the given -// command name (hg, git, svn, bzr). +// command name (hg, git, svn). func vcsByCmd(cmd string) *Cmd { for _, vcs := range vcsList { if vcs.Cmd == cmd { @@ -157,40 +144,16 @@ var vcsHg = &Cmd{ Name: "Mercurial", Cmd: "hg", - // HGPLAIN=1 turns off additional output that a user may have enabled via - // config options or certain extensions. - Env: []string{"HGPLAIN=1"}, - RootNames: []rootName{ - {filename: ".hg", isDir: true}, - }, - - CreateCmd: []string{"clone -U -- {repo} {dir}"}, - DownloadCmd: []string{"pull"}, - - // We allow both tag and branch names as 'tags' - // for selecting a version. This lets people have - // a go.release.r60 branch and a go1 branch - // and make changes in both, without constantly - // editing .hgtags. - TagCmd: []tagCmd{ - {"tags", `^(\S+)`}, - {"branches", `^(\S+)`}, + // HGPLAIN=+strictflags turns off additional output that a user may have + // enabled via config options or certain extensions. + Env: []string{"HGPLAIN=+strictflags"}, + Roots: []isVCSRoot{ + vcsDirRoot(".hg"), }, - TagSyncCmd: []string{"update -r {tag}"}, - TagSyncDefault: []string{"update default"}, - Scheme: []string{"https", "http", "ssh"}, - PingCmd: "identify -- {scheme}://{repo}", - RemoteRepo: hgRemoteRepo, - Status: hgStatus, -} - -func hgRemoteRepo(vcsHg *Cmd, rootDir string) (remoteRepo string, err error) { - out, err := vcsHg.runOutput(rootDir, "paths default") - if err != nil { - return "", err - } - return strings.TrimSpace(string(out)), nil + Scheme: []string{"https", "http", "ssh"}, + PingCmd: "identify -- {scheme}://{repo}", + Status: hgStatus, } func hgStatus(vcsHg *Cmd, rootDir string) (Status, error) { @@ -249,29 +212,10 @@ func parseRevTime(out []byte) (string, time.Time, error) { var vcsGit = &Cmd{ Name: "Git", Cmd: "git", - RootNames: []rootName{ - {filename: ".git", isDir: true}, + Roots: []isVCSRoot{ + vcsGitRoot{}, }, - CreateCmd: []string{"clone -- {repo} {dir}", "-go-internal-cd {dir} submodule update --init --recursive"}, - DownloadCmd: []string{"pull --ff-only", "submodule update --init --recursive"}, - - TagCmd: []tagCmd{ - // tags/xxx matches a git tag named xxx - // origin/xxx matches a git branch named xxx on the default remote repository - {"show-ref", `(?:tags|origin)/(\S+)$`}, - }, - TagLookupCmd: []tagCmd{ - {"show-ref tags/{tag} origin/{tag}", `((?:tags|origin)/\S+)$`}, - }, - TagSyncCmd: []string{"checkout {tag}", "submodule update --init --recursive"}, - // both createCmd and downloadCmd update the working dir. - // No need to do more here. We used to 'checkout master' - // but that doesn't work if the default branch is not named master. - // DO NOT add 'checkout master' here. - // See golang.org/issue/9032. - TagSyncDefault: []string{"submodule update --init --recursive"}, - Scheme: []string{"git", "https", "http", "git+ssh", "ssh"}, // Leave out the '--' separator in the ls-remote command: git 2.7.4 does not @@ -280,54 +224,7 @@ var vcsGit = &Cmd{ // See golang.org/issue/33836. PingCmd: "ls-remote {scheme}://{repo}", - RemoteRepo: gitRemoteRepo, - Status: gitStatus, -} - -// scpSyntaxRe matches the SCP-like addresses used by Git to access -// repositories by SSH. -var scpSyntaxRe = lazyregexp.New(`^(\w+)@([\w.-]+):(.*)$`) - -func gitRemoteRepo(vcsGit *Cmd, rootDir string) (remoteRepo string, err error) { - const cmd = "config remote.origin.url" - outb, err := vcsGit.run1(rootDir, cmd, nil, false) - if err != nil { - // if it doesn't output any message, it means the config argument is correct, - // but the config value itself doesn't exist - if outb != nil && len(outb) == 0 { - return "", errors.New("remote origin not found") - } - return "", err - } - out := strings.TrimSpace(string(outb)) - - var repoURL *urlpkg.URL - if m := scpSyntaxRe.FindStringSubmatch(out); m != nil { - // Match SCP-like syntax and convert it to a URL. - // Eg, "git@github.com:user/repo" becomes - // "ssh://git@github.com/user/repo". - repoURL = &urlpkg.URL{ - Scheme: "ssh", - User: urlpkg.User(m[1]), - Host: m[2], - Path: m[3], - } - } else { - repoURL, err = urlpkg.Parse(out) - if err != nil { - return "", err - } - } - - // Iterate over insecure schemes too, because this function simply - // reports the state of the repo. If we can't see insecure schemes then - // we can't report the actual repo URL. - for _, s := range vcsGit.Scheme { - if repoURL.Scheme == s { - return repoURL.String(), nil - } - } - return "", errors.New("unable to parse output of git " + cmd) + Status: gitStatus, } func gitStatus(vcsGit *Cmd, rootDir string) (Status, error) { @@ -359,177 +256,20 @@ func gitStatus(vcsGit *Cmd, rootDir string) (Status, error) { }, nil } -// vcsBzr describes how to use Bazaar. -var vcsBzr = &Cmd{ - Name: "Bazaar", - Cmd: "bzr", - RootNames: []rootName{ - {filename: ".bzr", isDir: true}, - }, - - CreateCmd: []string{"branch -- {repo} {dir}"}, - - // Without --overwrite bzr will not pull tags that changed. - // Replace by --overwrite-tags after http://pad.lv/681792 goes in. - DownloadCmd: []string{"pull --overwrite"}, - - TagCmd: []tagCmd{{"tags", `^(\S+)`}}, - TagSyncCmd: []string{"update -r {tag}"}, - TagSyncDefault: []string{"update -r revno:-1"}, - - Scheme: []string{"https", "http", "bzr", "bzr+ssh"}, - PingCmd: "info -- {scheme}://{repo}", - RemoteRepo: bzrRemoteRepo, - ResolveRepo: bzrResolveRepo, - Status: bzrStatus, -} - -func bzrRemoteRepo(vcsBzr *Cmd, rootDir string) (remoteRepo string, err error) { - outb, err := vcsBzr.runOutput(rootDir, "config parent_location") - if err != nil { - return "", err - } - return strings.TrimSpace(string(outb)), nil -} - -func bzrResolveRepo(vcsBzr *Cmd, rootDir, remoteRepo string) (realRepo string, err error) { - outb, err := vcsBzr.runOutput(rootDir, "info "+remoteRepo) - if err != nil { - return "", err - } - out := string(outb) - - // Expect: - // ... - // (branch root|repository branch): - // ... - - found := false - for _, prefix := range []string{"\n branch root: ", "\n repository branch: "} { - i := strings.Index(out, prefix) - if i >= 0 { - out = out[i+len(prefix):] - found = true - break - } - } - if !found { - return "", fmt.Errorf("unable to parse output of bzr info") - } - - i := strings.Index(out, "\n") - if i < 0 { - return "", fmt.Errorf("unable to parse output of bzr info") - } - out = out[:i] - return strings.TrimSpace(out), nil -} - -func bzrStatus(vcsBzr *Cmd, rootDir string) (Status, error) { - outb, err := vcsBzr.runOutputVerboseOnly(rootDir, "version-info") - if err != nil { - return Status{}, err - } - out := string(outb) - - // Expect (non-empty repositories only): - // - // revision-id: gopher@gopher.net-20211021072330-qshok76wfypw9lpm - // date: 2021-09-21 12:00:00 +1000 - // ... - var rev string - var commitTime time.Time - - for line := range strings.SplitSeq(out, "\n") { - i := strings.IndexByte(line, ':') - if i < 0 { - continue - } - key := line[:i] - value := strings.TrimSpace(line[i+1:]) - - switch key { - case "revision-id": - rev = value - case "date": - var err error - commitTime, err = time.Parse("2006-01-02 15:04:05 -0700", value) - if err != nil { - return Status{}, errors.New("unable to parse output of bzr version-info") - } - } - } - - outb, err = vcsBzr.runOutputVerboseOnly(rootDir, "status") - if err != nil { - return Status{}, err - } - - // Skip warning when working directory is set to an older revision. - if bytes.HasPrefix(outb, []byte("working tree is out of date")) { - i := bytes.IndexByte(outb, '\n') - if i < 0 { - i = len(outb) - } - outb = outb[:i] - } - uncommitted := len(outb) > 0 - - return Status{ - Revision: rev, - CommitTime: commitTime, - Uncommitted: uncommitted, - }, nil -} - // vcsSvn describes how to use Subversion. var vcsSvn = &Cmd{ Name: "Subversion", Cmd: "svn", - RootNames: []rootName{ - {filename: ".svn", isDir: true}, + Roots: []isVCSRoot{ + vcsDirRoot(".svn"), }, - CreateCmd: []string{"checkout -- {repo} {dir}"}, - DownloadCmd: []string{"update"}, - // There is no tag command in subversion. // The branch information is all in the path names. - Scheme: []string{"https", "http", "svn", "svn+ssh"}, - PingCmd: "info -- {scheme}://{repo}", - RemoteRepo: svnRemoteRepo, - Status: svnStatus, -} - -func svnRemoteRepo(vcsSvn *Cmd, rootDir string) (remoteRepo string, err error) { - outb, err := vcsSvn.runOutput(rootDir, "info") - if err != nil { - return "", err - } - out := string(outb) - - // Expect: - // - // ... - // URL: - // ... - // - // Note that we're not using the Repository Root line, - // because svn allows checking out subtrees. - // The URL will be the URL of the subtree (what we used with 'svn co') - // while the Repository Root may be a much higher parent. - i := strings.Index(out, "\nURL: ") - if i < 0 { - return "", fmt.Errorf("unable to parse output of svn info") - } - out = out[i+len("\nURL: "):] - i = strings.Index(out, "\n") - if i < 0 { - return "", fmt.Errorf("unable to parse output of svn info") - } - out = out[:i] - return strings.TrimSpace(out), nil + Scheme: []string{"https", "http", "svn", "svn+ssh"}, + PingCmd: "info -- {scheme}://{repo}", + Status: svnStatus, } func svnStatus(vcsSvn *Cmd, rootDir string) (Status, error) { @@ -569,29 +309,13 @@ const fossilRepoName = ".fossil" var vcsFossil = &Cmd{ Name: "Fossil", Cmd: "fossil", - RootNames: []rootName{ - {filename: ".fslckout", isDir: false}, - {filename: "_FOSSIL_", isDir: false}, + Roots: []isVCSRoot{ + vcsFileRoot(".fslckout"), + vcsFileRoot("_FOSSIL_"), }, - CreateCmd: []string{"-go-internal-mkdir {dir} clone -- {repo} " + filepath.Join("{dir}", fossilRepoName), "-go-internal-cd {dir} open .fossil"}, - DownloadCmd: []string{"up"}, - - TagCmd: []tagCmd{{"tag ls", `(.*)`}}, - TagSyncCmd: []string{"up tag:{tag}"}, - TagSyncDefault: []string{"up trunk"}, - - Scheme: []string{"https", "http"}, - RemoteRepo: fossilRemoteRepo, - Status: fossilStatus, -} - -func fossilRemoteRepo(vcsFossil *Cmd, rootDir string) (remoteRepo string, err error) { - out, err := vcsFossil.runOutput(rootDir, "remote-url") - if err != nil { - return "", err - } - return strings.TrimSpace(string(out)), nil + Scheme: []string{"https", "http"}, + Status: fossilStatus, } var errFossilInfo = errors.New("unable to parse output of fossil info") @@ -692,32 +416,10 @@ func (v *Cmd) run1(dir string, cmdline string, keyval []string, verbose bool) ([ args[i] = expand(m, arg) } - if len(args) >= 2 && args[0] == "-go-internal-mkdir" { - var err error - if filepath.IsAbs(args[1]) { - err = os.Mkdir(args[1], fs.ModePerm) - } else { - err = os.Mkdir(filepath.Join(dir, args[1]), fs.ModePerm) - } - if err != nil { - return nil, err - } - args = args[2:] - } - - if len(args) >= 2 && args[0] == "-go-internal-cd" { - if filepath.IsAbs(args[1]) { - dir = args[1] - } else { - dir = filepath.Join(dir, args[1]) - } - args = args[2:] - } - _, err := pathcache.LookPath(v.Cmd) if err != nil { fmt.Fprintf(os.Stderr, - "go: missing %s command. See https://golang.org/s/gogetcmd\n", + "go: missing %s command. See https://go.dev/s/gogetcmd\n", v.Name) return nil, err } @@ -755,7 +457,7 @@ func (v *Cmd) Ping(scheme, repo string) error { if !cfg.ModulesEnabled { dir = filepath.Join(cfg.BuildContext.GOPATH, "src") } - os.MkdirAll(dir, 0777) // Ignore errors — if unsuccessful, the command will likely fail. + os.MkdirAll(dir, 0o777) // Ignore errors — if unsuccessful, the command will likely fail. release, err := base.AcquireNet() if err != nil { @@ -766,99 +468,6 @@ func (v *Cmd) Ping(scheme, repo string) error { return v.runVerboseOnly(dir, v.PingCmd, "scheme", scheme, "repo", repo) } -// Create creates a new copy of repo in dir. -// The parent of dir must exist; dir must not. -func (v *Cmd) Create(dir, repo string) error { - release, err := base.AcquireNet() - if err != nil { - return err - } - defer release() - - for _, cmd := range v.CreateCmd { - if err := v.run(filepath.Dir(dir), cmd, "dir", dir, "repo", repo); err != nil { - return err - } - } - return nil -} - -// Download downloads any new changes for the repo in dir. -func (v *Cmd) Download(dir string) error { - release, err := base.AcquireNet() - if err != nil { - return err - } - defer release() - - for _, cmd := range v.DownloadCmd { - if err := v.run(dir, cmd); err != nil { - return err - } - } - return nil -} - -// Tags returns the list of available tags for the repo in dir. -func (v *Cmd) Tags(dir string) ([]string, error) { - var tags []string - for _, tc := range v.TagCmd { - out, err := v.runOutput(dir, tc.cmd) - if err != nil { - return nil, err - } - re := regexp.MustCompile(`(?m-s)` + tc.pattern) - for _, m := range re.FindAllStringSubmatch(string(out), -1) { - tags = append(tags, m[1]) - } - } - return tags, nil -} - -// TagSync syncs the repo in dir to the named tag, -// which either is a tag returned by tags or is v.tagDefault. -func (v *Cmd) TagSync(dir, tag string) error { - if v.TagSyncCmd == nil { - return nil - } - if tag != "" { - for _, tc := range v.TagLookupCmd { - out, err := v.runOutput(dir, tc.cmd, "tag", tag) - if err != nil { - return err - } - re := regexp.MustCompile(`(?m-s)` + tc.pattern) - m := re.FindStringSubmatch(string(out)) - if len(m) > 1 { - tag = m[1] - break - } - } - } - - release, err := base.AcquireNet() - if err != nil { - return err - } - defer release() - - if tag == "" && v.TagSyncDefault != nil { - for _, cmd := range v.TagSyncDefault { - if err := v.run(dir, cmd); err != nil { - return err - } - } - return nil - } - - for _, cmd := range v.TagSyncCmd { - if err := v.run(dir, cmd, "tag", tag); err != nil { - return err - } - } - return nil -} - // A vcsPath describes how to convert an import path into a // version control system and repository name. type vcsPath struct { @@ -889,7 +498,7 @@ func FromDir(dir, srcRoot string) (repoDir string, vcsCmd *Cmd, err error) { origDir := dir for len(dir) > len(srcRoot) { for _, vcs := range vcsList { - if isVCSRoot(dir, vcs.RootNames) { + if isVCSRootDir(dir, vcs.Roots) { if vcsCmd == nil { // Record first VCS we find. vcsCmd = vcs @@ -928,22 +537,71 @@ func FromDir(dir, srcRoot string) (repoDir string, vcsCmd *Cmd, err error) { return repoDir, vcsCmd, nil } -// isVCSRoot identifies a VCS root by checking whether the directory contains -// any of the listed root names. -func isVCSRoot(dir string, rootNames []rootName) bool { - for _, root := range rootNames { - fi, err := os.Stat(filepath.Join(dir, root.filename)) - if err == nil && fi.IsDir() == root.isDir { +// isVCSRootDir reports whether dir is a VCS root according to roots. +func isVCSRootDir(dir string, roots []isVCSRoot) bool { + for _, root := range roots { + if root.isRoot(dir) { return true } } - return false } -type rootName struct { - filename string - isDir bool +type isVCSRoot interface { + isRoot(dir string) bool +} + +// vcsFileRoot identifies a VCS root by the presence of a regular file. +type vcsFileRoot string + +func (vfr vcsFileRoot) isRoot(dir string) bool { + fi, err := os.Stat(filepath.Join(dir, string(vfr))) + return err == nil && fi.Mode().IsRegular() +} + +// vcsDirRoot identifies a VCS root by the presence of a directory. +type vcsDirRoot string + +func (vdr vcsDirRoot) isRoot(dir string) bool { + fi, err := os.Stat(filepath.Join(dir, string(vdr))) + return err == nil && fi.IsDir() +} + +// vcsGitRoot identifies a Git root by the presence of a .git directory or a .git worktree file. +// See https://go.dev/issue/58218. +type vcsGitRoot struct{} + +func (vcsGitRoot) isRoot(dir string) bool { + path := filepath.Join(dir, ".git") + fi, err := os.Stat(path) + if err != nil { + return false + } + if fi.IsDir() { + return true + } + // Is it a git worktree file? + // The format is "gitdir: \n". + if !fi.Mode().IsRegular() || fi.Size() == 0 || fi.Size() > 4096 { + return false + } + raw, err := os.ReadFile(path) + if err != nil { + return false + } + rest, ok := strings.CutPrefix(string(raw), "gitdir:") + if !ok { + return false + } + gitdir := strings.TrimSpace(rest) + if gitdir == "" { + return false + } + if !filepath.IsAbs(gitdir) { + gitdir = filepath.Join(dir, gitdir) + } + fi, err = os.Stat(gitdir) + return err == nil && fi.IsDir() } type vcsNotFoundError struct { @@ -1129,13 +787,6 @@ func RepoRootForImportPath(importPath string, mod ModuleMode, security web.Secur err = importErrorf(importPath, "unrecognized import path %q: %v", importPath, err) } } - if err != nil { - rr1, err1 := repoRootFromVCSPaths(importPath, security, vcsPathsAfterDynamic) - if err1 == nil { - rr = rr1 - err = nil - } - } // Should have been taken care of above, but make sure. if err == nil && strings.Contains(importPath, "...") && strings.Contains(rr.Root, "...") { @@ -1143,6 +794,16 @@ func RepoRootForImportPath(importPath string, mod ModuleMode, security web.Secur rr = nil err = importErrorf(importPath, "cannot expand ... in %q", importPath) } + + // Record telemetry about which VCS was found. + if err == nil { + if rr.VCS == vcsMod { + counter.Inc("go/vcs:mod") + } else { + counter.Inc("go/vcs:" + rr.VCS.Cmd) + } + } + return rr, err } @@ -1385,6 +1046,10 @@ func repoRootForImportDynamic(importPath string, mod ModuleMode, security web.Se } } + if err := validateRepoSubDir(mmi.SubDir); err != nil { + return nil, fmt.Errorf("%s: invalid subdirectory %q: %v", resp.URL, mmi.SubDir, err) + } + if err := validateRepoRoot(mmi.RepoRoot); err != nil { return nil, fmt.Errorf("%s: invalid repo root %q: %v", resp.URL, mmi.RepoRoot, err) } @@ -1416,6 +1081,22 @@ func repoRootForImportDynamic(importPath string, mod ModuleMode, security web.Se return rr, nil } +// validateRepoSubDir returns an error if subdir is not a valid subdirectory path. +// We consider a subdirectory path to be valid as long as it doesn't have a leading +// slash (/) or hyphen (-). +func validateRepoSubDir(subdir string) error { + if subdir == "" { + return nil + } + if subdir[0] == '/' { + return errors.New("leading slash") + } + if subdir[0] == '-' { + return errors.New("leading hyphen") + } + return nil +} + // validateRepoRoot returns an error if repoRoot does not seem to be // a valid URL with scheme. func validateRepoRoot(repoRoot string) error { @@ -1621,26 +1302,11 @@ var vcsPaths = []*vcsPath{ // General syntax for any server. // Must be last. { - regexp: lazyregexp.New(`(?P(?P([a-z0-9.\-]+\.)+[a-z0-9.\-]+(:[0-9]+)?(/~?[\w.\-]+)+?)\.(?Pbzr|fossil|git|hg|svn))(/~?[\w.\-]+)*$`), + regexp: lazyregexp.New(`(?P(?P([a-z0-9.\-]+\.)+[a-z0-9.\-]+(:[0-9]+)?(/~?[\w.\-]+)+?)\.(?Pfossil|git|hg|svn))(/~?[\w.\-]+)*$`), schemelessRepo: true, }, } -// vcsPathsAfterDynamic gives additional vcsPaths entries -// to try after the dynamic HTML check. -// This gives those sites a chance to introduce tags -// as part of a graceful transition away from the hard-coded logic. -var vcsPathsAfterDynamic = []*vcsPath{ - // Launchpad. See golang.org/issue/11436. - { - pathPrefix: "launchpad.net", - regexp: lazyregexp.New(`^(?Plaunchpad\.net/((?P[\w.\-]+)(?P/[\w.\-]+)?|~[\w.\-]+/(\+junk|[\w.\-]+)/[\w.\-]+))(/[\w.\-]+)*$`), - vcs: "bzr", - repo: "https://{root}", - check: launchpadVCS, - }, -} - // noVCSSuffix checks that the repository name does not // end in .foo for any version control system foo. // The usual culprit is ".git". @@ -1654,27 +1320,6 @@ func noVCSSuffix(match map[string]string) error { return nil } -// launchpadVCS solves the ambiguity for "lp.net/project/foo". In this case, -// "foo" could be a series name registered in Launchpad with its own branch, -// and it could also be the name of a directory within the main project -// branch one level up. -func launchpadVCS(match map[string]string) error { - if match["project"] == "" || match["series"] == "" { - return nil - } - url := &urlpkg.URL{ - Scheme: "https", - Host: "code.launchpad.net", - Path: expand(match, "/{project}{series}/.bzr/branch-format"), - } - _, err := web.GetBytes(url) - if err != nil { - match["root"] = expand(match, "launchpad.net/{project}") - match["repo"] = expand(match, "https://{root}") - } - return nil -} - // importError is a copy of load.importError, made to avoid a dependency cycle // on cmd/go/internal/load. It just needs to satisfy load.ImportPathError. type importError struct { diff --git a/src/cmd/go/internal/vcs/vcs_test.go b/src/cmd/go/internal/vcs/vcs_test.go index 361d85bcfb326f..aeef497decaf57 100644 --- a/src/cmd/go/internal/vcs/vcs_test.go +++ b/src/cmd/go/internal/vcs/vcs_test.go @@ -6,14 +6,15 @@ package vcs import ( "errors" - "fmt" - "internal/testenv" + "net/http" + "net/http/httptest" "os" "path/filepath" "strings" "testing" "cmd/go/internal/web" + "cmd/go/internal/web/intercept" ) func init() { @@ -25,9 +26,20 @@ func init() { } // Test that RepoRootForImportPath determines the correct RepoRoot for a given importPath. -// TODO(cmang): Add tests for SVN and BZR. +// TODO(cmang): Add tests for SVN. func TestRepoRootForImportPath(t *testing.T) { - testenv.MustHaveExternalNetwork(t) + // Intercept requests to external servers to avoid making external network connections from the test. + ts := httptest.NewServer(http.NotFoundHandler()) + t.Cleanup(ts.Close) + var interceptors []intercept.Interceptor + for _, d := range []string{"hub.jazz.net", "hubajazz.net", "hub2.jazz.net", "different.example.com"} { + interceptors = append(interceptors, + intercept.Interceptor{Scheme: "https", FromHost: d, ToHost: ts.Listener.Addr().String()}, + intercept.Interceptor{Scheme: "http", FromHost: d, ToHost: ts.Listener.Addr().String()}, + ) + } + intercept.EnableTestHooks(interceptors) + t.Cleanup(intercept.DisableTestHooks) tests := []struct { path string @@ -215,42 +227,62 @@ func TestRepoRootForImportPath(t *testing.T) { // Test that vcs.FromDir correctly inspects a given directory and returns the // right VCS and repo directory. func TestFromDir(t *testing.T) { - tempDir := t.TempDir() + tests := []struct { + name string + vcs string + root string + create func(path string) error + }{ + {"hg", "Mercurial", ".hg", mkdir}, + {"git_dir", "Git", ".git", mkdir}, + {"git_worktree", "Git", ".git", createGitWorktreeFile}, + {"svn", "Subversion", ".svn", mkdir}, + {"fossil_fslckout", "Fossil", ".fslckout", touch}, + {"fossil_FOSSIL_", "Fossil", "_FOSSIL_", touch}, + } - for _, vcs := range vcsList { - for r, root := range vcs.RootNames { - vcsName := fmt.Sprint(vcs.Name, r) - dir := filepath.Join(tempDir, "example.com", vcsName, root.filename) - if root.isDir { - err := os.MkdirAll(dir, 0755) - if err != nil { - t.Fatal(err) - } - } else { - err := os.MkdirAll(filepath.Dir(dir), 0755) - if err != nil { - t.Fatal(err) - } - f, err := os.Create(dir) - if err != nil { - t.Fatal(err) - } - f.Close() + for _, tt := range tests { + t.Run(tt.name, func(t *testing.T) { + tempDir := t.TempDir() + repoDir := filepath.Join(tempDir, "example.com") + if err := mkdir(repoDir); err != nil { + t.Fatal(err) } - - wantRepoDir := filepath.Dir(dir) - gotRepoDir, gotVCS, err := FromDir(dir, tempDir) + rootPath := filepath.Join(repoDir, tt.root) + if err := tt.create(rootPath); err != nil { + t.Fatal(err) + } + gotRepoDir, gotVCS, err := FromDir(repoDir, tempDir) if err != nil { - t.Errorf("FromDir(%q, %q): %v", dir, tempDir, err) - continue + t.Fatal(err) } - if gotRepoDir != wantRepoDir || gotVCS.Name != vcs.Name { - t.Errorf("FromDir(%q, %q) = RepoDir(%s), VCS(%s); want RepoDir(%s), VCS(%s)", dir, tempDir, gotRepoDir, gotVCS.Name, wantRepoDir, vcs.Name) + if gotRepoDir != repoDir { + t.Errorf("RepoDir = %q, want %q", gotRepoDir, repoDir) } - } + if gotVCS.Name != tt.vcs { + t.Errorf("VCS = %q, want %q", gotVCS.Name, tt.vcs) + } + }) } } +func mkdir(path string) error { + return os.Mkdir(path, 0o755) +} + +func touch(path string) error { + return os.WriteFile(path, nil, 0o644) +} + +func createGitWorktreeFile(path string) error { + gitdir := path + ".worktree" + // gitdir must point to a real directory + if err := mkdir(gitdir); err != nil { + return err + } + return os.WriteFile(path, []byte("gitdir: "+gitdir+"\n"), 0o644) +} + func TestIsSecure(t *testing.T) { tests := []struct { vcs *Cmd @@ -259,8 +291,6 @@ func TestIsSecure(t *testing.T) { }{ {vcsGit, "http://example.com/foo.git", false}, {vcsGit, "https://example.com/foo.git", true}, - {vcsBzr, "http://example.com/foo.bzr", false}, - {vcsBzr, "https://example.com/foo.bzr", true}, {vcsSvn, "http://example.com/svn", false}, {vcsSvn, "https://example.com/svn", true}, {vcsHg, "http://example.com/foo.hg", false}, @@ -294,8 +324,6 @@ func TestIsSecureGitAllowProtocol(t *testing.T) { // Same as TestIsSecure to verify same behavior. {vcsGit, "http://example.com/foo.git", false}, {vcsGit, "https://example.com/foo.git", true}, - {vcsBzr, "http://example.com/foo.bzr", false}, - {vcsBzr, "https://example.com/foo.bzr", true}, {vcsSvn, "http://example.com/svn", false}, {vcsSvn, "https://example.com/svn", true}, {vcsHg, "http://example.com/foo.hg", false}, @@ -312,7 +340,6 @@ func TestIsSecureGitAllowProtocol(t *testing.T) { {vcsGit, "foo://example.com/bar.git", true}, {vcsHg, "foo://example.com/bar.hg", false}, {vcsSvn, "foo://example.com/svn", false}, - {vcsBzr, "foo://example.com/bar.bzr", false}, } defer os.Unsetenv("GIT_ALLOW_PROTOCOL") @@ -507,6 +534,42 @@ func TestValidateRepoRoot(t *testing.T) { } } +func TestValidateRepoSubDir(t *testing.T) { + tests := []struct { + subdir string + ok bool + }{ + { + subdir: "", + ok: true, + }, + { + subdir: "sub/dir", + ok: true, + }, + { + subdir: "/leading/slash", + ok: false, + }, + { + subdir: "-leading/hyphen", + ok: false, + }, + } + + for _, test := range tests { + err := validateRepoSubDir(test.subdir) + ok := err == nil + if ok != test.ok { + want := "error" + if test.ok { + want = "nil" + } + t.Errorf("validateRepoSubDir(%q) = %q, want %s", test.subdir, err, want) + } + } +} + var govcsTests = []struct { govcs string path string diff --git a/src/cmd/go/internal/vcweb/bzr.go b/src/cmd/go/internal/vcweb/bzr.go deleted file mode 100644 index a915fb2b93347c..00000000000000 --- a/src/cmd/go/internal/vcweb/bzr.go +++ /dev/null @@ -1,18 +0,0 @@ -// Copyright 2022 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -package vcweb - -import ( - "log" - "net/http" -) - -type bzrHandler struct{} - -func (*bzrHandler) Available() bool { return true } - -func (*bzrHandler) Handler(dir string, env []string, logger *log.Logger) (http.Handler, error) { - return http.FileServer(http.Dir(dir)), nil -} diff --git a/src/cmd/go/internal/vcweb/hg.go b/src/cmd/go/internal/vcweb/hg.go index 4571277c9f1a5a..c94a22524fa51b 100644 --- a/src/cmd/go/internal/vcweb/hg.go +++ b/src/cmd/go/internal/vcweb/hg.go @@ -25,6 +25,13 @@ type hgHandler struct { once sync.Once hgPath string hgPathErr error + + mu sync.Mutex + wg sync.WaitGroup + ctx context.Context + cancel func() + cmds []*exec.Cmd + url map[string]*url.URL } func (h *hgHandler) Available() bool { @@ -34,6 +41,30 @@ func (h *hgHandler) Available() bool { return h.hgPathErr == nil } +func (h *hgHandler) Close() error { + h.mu.Lock() + defer h.mu.Unlock() + + if h.cancel == nil { + return nil + } + + h.cancel() + for _, cmd := range h.cmds { + h.wg.Add(1) + go func() { + cmd.Wait() + h.wg.Done() + }() + } + h.wg.Wait() + h.url = nil + h.cmds = nil + h.ctx = nil + h.cancel = nil + return nil +} + func (h *hgHandler) Handler(dir string, env []string, logger *log.Logger) (http.Handler, error) { if !h.Available() { return nil, ServerNotInstalledError{name: "hg"} @@ -50,10 +81,25 @@ func (h *hgHandler) Handler(dir string, env []string, logger *log.Logger) (http. // if "hg" works at all then "hg serve" works too, and we'll execute that as // a subprocess, using a reverse proxy to forward the request and response. - ctx, cancel := context.WithCancel(req.Context()) - defer cancel() + h.mu.Lock() + + if h.ctx == nil { + h.ctx, h.cancel = context.WithCancel(context.Background()) + } - cmd := exec.CommandContext(ctx, h.hgPath, "serve", "--port", "0", "--address", "localhost", "--accesslog", os.DevNull, "--name", "vcweb", "--print-url") + // Cache the hg server subprocess globally, because hg is too slow + // to start a new one for each request. There are under a dozen different + // repos we serve, so leaving a dozen processes around is not a big deal. + u := h.url[dir] + if u != nil { + logger.Printf("proxying hg request to %s", u) + httputil.NewSingleHostReverseProxy(u).ServeHTTP(w, req) + h.mu.Unlock() + return + } + + logger.Printf("starting hg serve for %s", dir) + cmd := exec.CommandContext(h.ctx, h.hgPath, "serve", "--port", "0", "--address", "localhost", "--accesslog", os.DevNull, "--name", "vcweb", "--print-url") cmd.Dir = dir cmd.Env = append(slices.Clip(env), "PWD="+dir) @@ -74,47 +120,56 @@ func (h *hgHandler) Handler(dir string, env []string, logger *log.Logger) (http. stdout, err := cmd.StdoutPipe() if err != nil { + h.mu.Unlock() http.Error(w, err.Error(), http.StatusInternalServerError) return } if err := cmd.Start(); err != nil { + h.mu.Unlock() http.Error(w, err.Error(), http.StatusInternalServerError) return } - var wg sync.WaitGroup - defer func() { - cancel() - err := cmd.Wait() - if out := strings.TrimSuffix(stderr.String(), "interrupted!\n"); out != "" { - logger.Printf("%v: %v\n%s", cmd, err, out) - } else { - logger.Printf("%v", cmd) - } - wg.Wait() - }() r := bufio.NewReader(stdout) line, err := r.ReadString('\n') if err != nil { + h.mu.Unlock() + http.Error(w, err.Error(), http.StatusInternalServerError) return } // We have read what should be the server URL. 'hg serve' shouldn't need to // write anything else to stdout, but it's not a big deal if it does anyway. // Keep the stdout pipe open so that 'hg serve' won't get a SIGPIPE, but // actively discard its output so that it won't hang on a blocking write. - wg.Add(1) + h.wg.Add(1) go func() { io.Copy(io.Discard, r) - wg.Done() + h.wg.Done() }() - u, err := url.Parse(strings.TrimSpace(line)) + // On some systems, + // hg serve --address=localhost --print-url prints in-addr.arpa hostnames + // even though they cannot be looked up. + // Replace them with IP literals. + line = strings.ReplaceAll(line, "//1.0.0.127.in-addr.arpa", "//127.0.0.1") + line = strings.ReplaceAll(line, "//1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa", "//[::1]") + + u, err = url.Parse(strings.TrimSpace(line)) if err != nil { + h.mu.Unlock() logger.Printf("%v: %v", cmd, err) http.Error(w, err.Error(), http.StatusBadGateway) return } + + if h.url == nil { + h.url = make(map[string]*url.URL) + } + h.url[dir] = u + h.cmds = append(h.cmds, cmd) + defer h.mu.Unlock() + logger.Printf("proxying hg request to %s", u) httputil.NewSingleHostReverseProxy(u).ServeHTTP(w, req) }) diff --git a/src/cmd/go/internal/vcweb/script.go b/src/cmd/go/internal/vcweb/script.go index 3342ab200c6faa..0256f2b856a4b4 100644 --- a/src/cmd/go/internal/vcweb/script.go +++ b/src/cmd/go/internal/vcweb/script.go @@ -18,12 +18,14 @@ import ( "os" "os/exec" "path/filepath" + "regexp" "runtime" "strconv" "strings" "time" "golang.org/x/mod/module" + "golang.org/x/mod/semver" "golang.org/x/mod/zip" ) @@ -38,23 +40,20 @@ func newScriptEngine() *script.Engine { } conds[name] = cond } - lazyBool := func(summary string, f func() bool) script.Cond { - return script.OnceCondition(summary, func() (bool, error) { return f(), nil }) - } - add("bzr", lazyBool("the 'bzr' executable exists and provides the standard CLI", hasWorkingBzr)) + add("git-sha256", script.OnceCondition("the local 'git' version is recent enough to support sha256 object/commit hashes", gitSupportsSHA256)) interrupt := func(cmd *exec.Cmd) error { return cmd.Process.Signal(os.Interrupt) } gracePeriod := 30 * time.Second // arbitrary cmds := script.DefaultCmds() cmds["at"] = scriptAt() - cmds["bzr"] = script.Program("bzr", interrupt, gracePeriod) cmds["fossil"] = script.Program("fossil", interrupt, gracePeriod) cmds["git"] = script.Program("git", interrupt, gracePeriod) cmds["hg"] = script.Program("hg", interrupt, gracePeriod) cmds["handle"] = scriptHandle() cmds["modzip"] = scriptModzip() cmds["skip"] = scriptSkip() + cmds["status"] = scriptStatus() cmds["svnadmin"] = script.Program("svnadmin", interrupt, gracePeriod) cmds["svn"] = script.Program("svn", interrupt, gracePeriod) cmds["unquote"] = scriptUnquote() @@ -263,7 +262,7 @@ func scriptHandle() script.Cmd { Args: "handler [dir]", Detail: []string{ "The handler will be passed the script's current working directory and environment as arguments.", - "Valid handlers include 'dir' (for general http.Dir serving), 'bzr', 'fossil', 'git', and 'hg'", + "Valid handlers include 'dir' (for general http.Dir serving), 'fossil', 'git', and 'hg'", }, }, func(st *script.State, args ...string) (script.WaitFunc, error) { @@ -350,6 +349,50 @@ func scriptSkip() script.Cmd { }) } +type statusWriter struct { + http.ResponseWriter + status int +} + +func (w *statusWriter) WriteHeader(code int) { + w.ResponseWriter.WriteHeader(w.status) +} + +type statusCodeHandler struct { + handler http.Handler + statusCode int +} + +func (h *statusCodeHandler) ServeHTTP(w http.ResponseWriter, r *http.Request) { + h.handler.ServeHTTP(&statusWriter{ResponseWriter: w, status: h.statusCode}, r) +} + +func scriptStatus() script.Cmd { + return script.Command( + script.CmdUsage{ + Summary: "set the HTTP status code for the handler", + Args: "code", + }, + func(st *script.State, args ...string) (script.WaitFunc, error) { + if len(args) != 1 { + return nil, script.ErrUsage + } + sc, err := getScriptCtx(st) + if err != nil { + return nil, err + } + if sc.handler == nil { + return nil, errors.New("status command must be called after handle") + } + code, err := strconv.Atoi(args[0]) + if err != nil { + return nil, err + } + sc.handler = &statusCodeHandler{handler: sc.handler, statusCode: code} + return nil, nil + }) +} + type SkipError struct { Msg string } @@ -384,13 +427,29 @@ func scriptUnquote() script.Cmd { }) } -func hasWorkingBzr() bool { - bzr, err := exec.LookPath("bzr") - if err != nil { - return false +// Capture the major, minor and (optionally) patch version, but ignore anything later +var gitVersLineExtract = regexp.MustCompile(`git version\s+(\d+\.\d+(?:\.\d+)?)`) + +func gitVersion() (string, error) { + gitOut, runErr := exec.Command("git", "version").CombinedOutput() + if runErr != nil { + return "v0", fmt.Errorf("failed to execute git version: %w", runErr) + } + matches := gitVersLineExtract.FindSubmatch(gitOut) + if len(matches) < 2 { + return "v0", fmt.Errorf("git version extraction regexp did not match version line: %q", gitOut) + } + return "v" + string(matches[1]), nil +} + +func hasAtLeastGitVersion(minVers string) (bool, error) { + gitVers, gitVersErr := gitVersion() + if gitVersErr != nil { + return false, gitVersErr } - // Check that 'bzr help' exits with code 0. - // See go.dev/issue/71504 for an example where 'bzr' exists in PATH but doesn't work. - err = exec.Command(bzr, "help").Run() - return err == nil + return semver.Compare(minVers, gitVers) <= 0, nil +} + +func gitSupportsSHA256() (bool, error) { + return hasAtLeastGitVersion("v2.29") } diff --git a/src/cmd/go/internal/vcweb/vcstest/vcstest.go b/src/cmd/go/internal/vcweb/vcstest/vcstest.go index 68278512922825..224cfd791931ca 100644 --- a/src/cmd/go/internal/vcweb/vcstest/vcstest.go +++ b/src/cmd/go/internal/vcweb/vcstest/vcstest.go @@ -7,6 +7,7 @@ package vcstest import ( + "bytes" "cmd/go/internal/vcs" "cmd/go/internal/vcweb" "cmd/go/internal/web/intercept" @@ -70,7 +71,9 @@ func NewServer() (srv *Server, err error) { } }() - srvHTTP := httptest.NewServer(handler) + srvHTTP := httptest.NewUnstartedServer(handler) + srvHTTP.Config.ErrorLog = testLogger() + srvHTTP.Start() httpURL, err := url.Parse(srvHTTP.URL) if err != nil { return nil, err @@ -81,7 +84,9 @@ func NewServer() (srv *Server, err error) { } }() - srvHTTPS := httptest.NewTLSServer(handler) + srvHTTPS := httptest.NewUnstartedServer(handler) + srvHTTPS.Config.ErrorLog = testLogger() + srvHTTPS.StartTLS() httpsURL, err := url.Parse(srvHTTPS.URL) if err != nil { return nil, err @@ -115,6 +120,19 @@ func NewServer() (srv *Server, err error) { return srv, nil } +func testLogger() *log.Logger { + return log.New(httpLogger{}, "vcweb: ", 0) +} + +type httpLogger struct{} + +func (httpLogger) Write(b []byte) (int, error) { + if bytes.Contains(b, []byte("TLS handshake error")) { + return len(b), nil + } + return os.Stdout.Write(b) +} + func (srv *Server) Close() error { if vcs.VCSTestRepoURL != srv.HTTP.URL { panic("vcs URL hooks modified before Close") diff --git a/src/cmd/go/internal/vcweb/vcweb.go b/src/cmd/go/internal/vcweb/vcweb.go index 4b4e127bb042e0..204d4d923535b0 100644 --- a/src/cmd/go/internal/vcweb/vcweb.go +++ b/src/cmd/go/internal/vcweb/vcweb.go @@ -15,7 +15,7 @@ // until the script is modified. // // The script engine includes all of the engine's default commands and -// conditions, as well as commands for each supported VCS binary (bzr, fossil, +// conditions, as well as commands for each supported VCS binary (fossil, // git, hg, and svn), a "handle" command that informs the script which protocol // or handler to use to serve the request, and utilities "at" (which sets // environment variables for Git timestamps) and "unquote" (which unquotes its @@ -129,7 +129,6 @@ func NewServer(scriptDir, workDir string, logger *log.Logger) (*Server, error) { vcsHandlers: map[string]vcsHandler{ "auth": new(authHandler), "dir": new(dirHandler), - "bzr": new(bzrHandler), "fossil": new(fossilHandler), "git": new(gitHandler), "hg": new(hgHandler), @@ -199,8 +198,10 @@ func (s *Server) ServeHTTP(w http.ResponseWriter, req *http.Request) { defer func() { if v := recover(); v != nil { - debug.PrintStack() - s.logger.Fatal(v) + if v == http.ErrAbortHandler { + panic(v) + } + s.logger.Fatalf("panic serving %s: %v\n%s", req.URL, v, debug.Stack()) } }() diff --git a/src/cmd/go/internal/verylongtest/go_test.go b/src/cmd/go/internal/verylongtest/go_test.go new file mode 100644 index 00000000000000..8a2acf36900d76 --- /dev/null +++ b/src/cmd/go/internal/verylongtest/go_test.go @@ -0,0 +1,64 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package verylongtest + +import ( + "bytes" + "flag" + "fmt" + "internal/testenv" + "os" + "os/exec" + "runtime" + "testing" +) + +func TestMain(m *testing.M) { + flag.Parse() + if testing.Short() { + return + } + + tmpdir, err := os.MkdirTemp("", "verylongtest") + if err != nil { + fmt.Fprintf(os.Stderr, "failed to create temp gocache: %v\n", err) + os.Exit(1) + } + os.Setenv("GOCACHE", tmpdir) + + code := m.Run() + + os.RemoveAll(tmpdir) + os.Exit(code) +} + +// Regression test for golang.org/issue/34499: version command should not crash +// when executed in a deleted directory on Linux. +func TestExecInDeletedDir(t *testing.T) { + switch runtime.GOOS { + case "windows", "plan9", + "aix", // Fails with "device busy". + "solaris", "illumos": // Fails with "invalid argument". + t.Skipf("%v does not support removing the current working directory", runtime.GOOS) + } + gotool := testenv.GoToolPath(t) + + tmpdir := t.TempDir() + t.Chdir(tmpdir) + + if err := os.Remove(tmpdir); err != nil { + t.Fatal(err) + } + + // `go version` should not fail + var stdout, stderr bytes.Buffer + cmd := exec.Command(gotool, "version") + cmd.Env = append(os.Environ(), "GO111MODULE=off") // This behavior doesn't apply with GO111MODULE != off because we need to know the module to check the version. + cmd.Stdout = &stdout + cmd.Stderr = &stderr + if err := cmd.Run(); err != nil { + t.Fatalf("running go version: %v\n[stdout]: %s\n[stderr]: %s", err, stdout.Bytes(), stderr.Bytes()) + } +} diff --git a/src/cmd/go/go_unix_test.go b/src/cmd/go/internal/verylongtest/go_unix_test.go similarity index 77% rename from src/cmd/go/go_unix_test.go rename to src/cmd/go/internal/verylongtest/go_unix_test.go index a6b21b86d02099..48463dfd4defe7 100644 --- a/src/cmd/go/go_unix_test.go +++ b/src/cmd/go/internal/verylongtest/go_unix_test.go @@ -4,7 +4,7 @@ //go:build unix -package main_test +package verylongtest import ( "bufio" @@ -13,20 +13,37 @@ import ( "io" "os" "os/exec" - "slices" + "path/filepath" "strings" "syscall" "testing" ) func TestGoBuildUmask(t *testing.T) { + testenv.MustHaveGoBuild(t) + // Do not use tg.parallel; avoid other tests seeing umask manipulation. mask := syscall.Umask(0077) // prohibit low bits defer syscall.Umask(mask) - tg := testgo(t) - defer tg.cleanup() - tg.tempFile("x.go", `package main; func main() {}`) + gotool, err := testenv.GoTool() + if err != nil { + t.Fatal(err) + } + + tmpdir, err := os.MkdirTemp("", "") + if err != nil { + t.Fatal(err) + } + t.Cleanup(func() { + if err := os.RemoveAll(tmpdir); err != nil { + t.Fatal(err) + } + }) + err = os.WriteFile(filepath.Join(tmpdir, "x.go"), []byte(`package main; func main() {}`), 0666) + if err != nil { + t.Fatal(err) + } // We have set a umask, but if the parent directory happens to have a default // ACL, the umask may be ignored. To prevent spurious failures from an ACL, @@ -34,8 +51,7 @@ func TestGoBuildUmask(t *testing.T) { // by os.WriteFile. // // (See https://go.dev/issue/62724, https://go.dev/issue/17909.) - control := tg.path("control") - tg.creatingTemp(control) + control := filepath.Join(tmpdir, "control") if err := os.WriteFile(control, []byte("#!/bin/sh\nexit 0"), 0777); err != nil { t.Fatal(err) } @@ -44,9 +60,10 @@ func TestGoBuildUmask(t *testing.T) { t.Fatal(err) } - exe := tg.path("x") - tg.creatingTemp(exe) - tg.run("build", "-o", exe, tg.path("x.go")) + exe := filepath.Join(tmpdir, "x") + if err := exec.Command(gotool, "build", "-o", exe, filepath.Join(tmpdir, "x.go")).Run(); err != nil { + t.Fatal(err) + } fi, err := os.Stat(exe) if err != nil { t.Fatal(err) @@ -68,20 +85,16 @@ func TestTestInterrupt(t *testing.T) { if testing.Short() { t.Skipf("skipping in short mode: test executes many subprocesses") } + testenv.MustHaveGoBuild(t) // Don't run this test in parallel, for the same reason. - tg := testgo(t) - defer tg.cleanup() - tg.setenv("GOROOT", testGOROOT) + gotool, err := testenv.GoTool() + if err != nil { + t.Fatal(err) + } ctx, cancel := context.WithCancel(context.Background()) - cmd := testenv.CommandContext(t, ctx, tg.goTool(), "test", "std", "-short", "-count=1") - cmd.Dir = tg.execDir - - // Override $TMPDIR when running the tests: since we're terminating the tests - // with a signal they might fail to clean up some temp files, and we don't - // want that to cause an "unexpected files" failure at the end of the run. - cmd.Env = append(slices.Clip(tg.env), tempEnvName()+"="+t.TempDir()) + cmd := testenv.CommandContext(t, ctx, gotool, "test", "std", "-short", "-count=1") cmd.SysProcAttr = &syscall.SysProcAttr{ Setpgid: true, diff --git a/src/cmd/go/internal/verylongtest/script_test.go b/src/cmd/go/internal/verylongtest/script_test.go new file mode 100644 index 00000000000000..5c2feb545151ce --- /dev/null +++ b/src/cmd/go/internal/verylongtest/script_test.go @@ -0,0 +1,80 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package verylongtest + +import ( + "cmd/internal/script" + "cmd/internal/script/scripttest" + "fmt" + "internal/testenv" + "io/fs" + "net" + "net/http" + "os" + "os/exec" + "path/filepath" + "runtime" + "testing" +) + +func TestScript(t *testing.T) { + if testing.Short() { + // Don't bother setting up the script engine. None of these are short tests. + t.Skip() + } + testenv.MustHaveGoBuild(t) + testenv.SkipIfShortAndSlow(t) + + engine, env := scripttest.NewEngine(t, nil) + modcache := filepath.Join(t.TempDir(), "modcache") + env = append(env, "GOMODCACHE="+modcache) + // Remove write only permissions on GOMODCACHE so we can clear its files. + t.Cleanup(func() { + filepath.WalkDir(modcache, func(path string, info fs.DirEntry, err error) error { + os.Chmod(path, 0777) + return nil + }) + }) + env = append(env, "GOROOT="+runtime.GOROOT()) + go404proxyAddr := start404Proxy(t) + env = append(env, "TESTGO_404_PROXY_ADDR="+go404proxyAddr) + engine.Conds["net"] = script.PrefixCondition("can connect to external network host ", hasNet) + engine.Conds["git"] = script.OnceCondition("the 'git' executable exists and provides the standard CLI", hasWorkingGit) + scripttest.RunTests(t, t.Context(), engine, env, "testdata/script/*.txt") +} + +func start404Proxy(t *testing.T) string { + addr := "localhost:0" + l, err := net.Listen("tcp", addr) + if err != nil { + t.Fatal(err) + } + t.Cleanup(func() { + if err := l.Close(); err != nil { + t.Fatal(err) + } + }) + proxyAddr := l.Addr().String() + proxyURL := "http://" + proxyAddr + "/mod" + fmt.Fprintf(os.Stderr, "404 test proxy running at %s\n", proxyURL) + go http.Serve(l, http.HandlerFunc(func(rw http.ResponseWriter, rew *http.Request) { + rw.WriteHeader(http.StatusNotFound) + })) + return proxyURL +} + +func hasNet(*script.State, string) (bool, error) { + return testenv.HasExternalNetwork(), nil +} + +func hasWorkingGit() (bool, error) { + if runtime.GOOS == "plan9" { + // The Git command is usually not the real Git on Plan 9. + // See https://golang.org/issues/29640. + return false, nil + } + _, err := exec.LookPath("git") + return err == nil, nil +} diff --git a/src/cmd/go/internal/verylongtest/testdata/script/gotoolchain_net.txt b/src/cmd/go/internal/verylongtest/testdata/script/gotoolchain_net.txt new file mode 100644 index 00000000000000..44435af8d05b09 --- /dev/null +++ b/src/cmd/go/internal/verylongtest/testdata/script/gotoolchain_net.txt @@ -0,0 +1,26 @@ +# Test downloading a real GOTOOLCHAIN from the network. + +[short] skip +[!net:golang.org] skip +[!net:proxy.golang.org] skip +[!net:sum.golang.org] skip +[!GOOS:darwin] [!GOOS:windows] [!GOOS:linux] skip +[!GOARCH:amd64] [!GOARCH:arm64] skip + +env GOPROXY=proxy.golang.org +env GOSUMDB=sum.golang.org +env GOTOOLCHAIN=go1.20.1 + + # Avoid resolving a "go1.20.1" from the user's real $PATH. + # That would not only cause the "downloading go1.20.1" message + # to be suppressed, but may spuriously fail: + # golang.org/dl/go1.20.1 expects to find its GOROOT in $HOME/sdk, + # but we set HOME=/no-home. +env GOPATH=$WORK/go +env HOME=/no-home +env PATH= +env path= + +go version +stderr '^go: downloading go1.20.1 ' +stdout go1.20.1 diff --git a/src/cmd/go/testdata/script/link_matching_actionid.txt b/src/cmd/go/internal/verylongtest/testdata/script/link_matching_actionid.txt similarity index 89% rename from src/cmd/go/testdata/script/link_matching_actionid.txt rename to src/cmd/go/internal/verylongtest/testdata/script/link_matching_actionid.txt index b8d423d027b693..9f3711dd1d6add 100644 --- a/src/cmd/go/testdata/script/link_matching_actionid.txt +++ b/src/cmd/go/internal/verylongtest/testdata/script/link_matching_actionid.txt @@ -6,8 +6,9 @@ [!symlink] skip # Symlink the compiler to a local path +env TEST_GOROOT=$GOROOT env GOROOT=$WORK/goroot1 -symlink $GOROOT -> $TESTGO_GOROOT +symlink $GOROOT -> $TEST_GOROOT # Set up fresh GOCACHE env GOCACHE=$WORK/gocache1 @@ -18,7 +19,7 @@ go build -o binary1 -trimpath -x main.go # Now repeat the same process with the compiler at a different local path env GOROOT=$WORK/goroot2 -symlink $GOROOT -> $TESTGO_GOROOT +symlink $GOROOT -> $TEST_GOROOT env GOCACHE=$WORK/gocache2 mkdir $GOCACHE diff --git a/src/cmd/go/testdata/script/mod_insecure_issue63845.txt b/src/cmd/go/internal/verylongtest/testdata/script/mod_insecure_issue63845.txt similarity index 100% rename from src/cmd/go/testdata/script/mod_insecure_issue63845.txt rename to src/cmd/go/internal/verylongtest/testdata/script/mod_insecure_issue63845.txt diff --git a/src/cmd/go/testdata/script/mod_proxy_https.txt b/src/cmd/go/internal/verylongtest/testdata/script/mod_proxy_https.txt similarity index 100% rename from src/cmd/go/testdata/script/mod_proxy_https.txt rename to src/cmd/go/internal/verylongtest/testdata/script/mod_proxy_https.txt diff --git a/src/cmd/go/testdata/script/mod_sumdb_golang.txt b/src/cmd/go/internal/verylongtest/testdata/script/mod_sumdb_golang.txt similarity index 90% rename from src/cmd/go/testdata/script/mod_sumdb_golang.txt rename to src/cmd/go/internal/verylongtest/testdata/script/mod_sumdb_golang.txt index 067e2e3b318350..23935f2849c4d4 100644 --- a/src/cmd/go/testdata/script/mod_sumdb_golang.txt +++ b/src/cmd/go/internal/verylongtest/testdata/script/mod_sumdb_golang.txt @@ -14,6 +14,7 @@ [!net:proxy.golang.org] skip [!net:sum.golang.org] skip [!git] skip +env GOMODCACHE=$WORK/modcache # we clean the modcache below env GOSUMDB=sum.golang.org env GOPROXY=direct @@ -64,16 +65,16 @@ cmp go.sum saved.sum # test fallback to direct -env TESTGOPROXY404=1 +env GOPROXY=$TESTGO_404_PROXY_ADDR,direct go clean -modcache rm go.sum go list -mod=mod -x -m all # Download go.mod files -stderr 'proxy.golang.org.*404 testing' +stderr $TESTGO_404_PROXY_ADDR.*'404 Not Found' stderr github.com/rsc go list -mod=mod -x rsc.io/quote # Download module source. -stderr 'proxy.golang.org.*404 testing' +stderr $TESTGO_404_PROXY_ADDR.*'404 Not Found' stderr github.com/rsc cmp go.sum saved.sum diff --git a/src/cmd/go/testdata/script/repro_build.txt b/src/cmd/go/internal/verylongtest/testdata/script/repro_build.txt similarity index 100% rename from src/cmd/go/testdata/script/repro_build.txt rename to src/cmd/go/internal/verylongtest/testdata/script/repro_build.txt diff --git a/src/cmd/go/testdata/script/test_cache_inputs.txt b/src/cmd/go/internal/verylongtest/testdata/script/test_cache_inputs.txt similarity index 96% rename from src/cmd/go/testdata/script/test_cache_inputs.txt rename to src/cmd/go/internal/verylongtest/testdata/script/test_cache_inputs.txt index 29e538c11ece70..05ffcb87e65e4f 100644 --- a/src/cmd/go/testdata/script/test_cache_inputs.txt +++ b/src/cmd/go/internal/verylongtest/testdata/script/test_cache_inputs.txt @@ -1,4 +1,6 @@ env GO111MODULE=off +env GOPATH=$WORK/gopath +cd $WORK/gopath/src # Test that cached test results are invalidated in response to # changes to the external inputs to the test. @@ -103,7 +105,7 @@ go test testcache -run=ExternalFile go test testcache -run=ExternalFile stdout '\(cached\)' -rm $WORK/external.txt +rm external.txt go test testcache -run=ExternalFile stdout '\(cached\)' @@ -191,20 +193,20 @@ go test testcache -run=Exec go test testcache -run=Exec stdout '\(cached\)' --- testcache/file.txt -- +-- gopath/src/testcache/file.txt -- xx --- 4x.txt -- +-- gopath/src/4x.txt -- xxxx --- 6x.txt -- +-- gopath/src/6x.txt -- xxxxxx --- 2y.txt -- +-- gopath/src/2y.txt -- yy --- $WORK/external.txt -- +-- external.txt -- This file is outside of GOPATH. --- testcache/script.sh -- +-- gopath/src/testcache/script.sh -- #!/bin/sh exit 0 --- testcache/hello.go -- +-- gopath/src/testcache/hello.go -- package testcache import "fmt" @@ -216,7 +218,7 @@ func HelloWorld(name string) string { return fmt.Sprintf("Hello, %s!", name) } --- testcache/testcache_test.go -- +-- gopath/src/testcache/testcache_test.go -- // Copyright 2017 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. @@ -331,7 +333,7 @@ func TestCoverageCache(t *testing.T) { } } --- mkold.go -- +-- gopath/src/mkold.go -- package main import ( diff --git a/src/cmd/go/internal/vet/vet.go b/src/cmd/go/internal/vet/vet.go index a429cbff65934e..3f45050159d12b 100644 --- a/src/cmd/go/internal/vet/vet.go +++ b/src/cmd/go/internal/vet/vet.go @@ -6,6 +6,8 @@ package vet import ( + "archive/zip" + "bytes" "context" "encoding/json" "errors" @@ -42,7 +44,8 @@ It supports these flags: -fix instead of printing each diagnostic, apply its first fix (if any) -diff - instead of applying each fix, print the patch as a unified diff + instead of applying each fix, print the patch as a unified diff; + exit with a non-zero status if the diff is not empty The -vettool=prog flag selects a different analysis tool with alternative or additional checks. For example, the 'shadow' analyzer @@ -79,7 +82,8 @@ and applies suggested fixes. It supports these flags: -diff - instead of applying each fix, print the patch as a unified diff + instead of applying each fix, print the patch as a unified diff; + exit with a non-zero status if the diff is not empty The -fixtool=prog flag selects a different analysis tool with alternative or additional fixers; see the documentation for go vet's @@ -120,13 +124,13 @@ var ( // run implements both "go vet" and "go fix". func run(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() // Compute flags for the vet/fix tool (e.g. cmd/{vet,fix}). toolFlags, pkgArgs := toolFlags(cmd, args) // The vet/fix commands do custom flag processing; // initialize workspaces after that. - modload.InitWorkfile(moduleLoaderState) + moduleLoader.InitWorkfile() if cfg.DebugTrace != "" { var close func() error @@ -145,7 +149,7 @@ func run(ctx context.Context, cmd *base.Command, args []string) { ctx, span := trace.StartSpan(ctx, fmt.Sprint("Running ", cmd.Name(), " command")) defer span.Done() - work.BuildInit(moduleLoaderState) + work.BuildInit(moduleLoader) // Flag theory: // @@ -163,8 +167,8 @@ func run(ctx context.Context, cmd *base.Command, args []string) { // command args tool args // go vet => cmd/vet -json Parse stdout, print diagnostics to stderr. // go vet -json => cmd/vet -json Pass stdout through. - // go vet -fix [-diff] => cmd/vet -fix [-diff] Pass stdout through. - // go fix [-diff] => cmd/fix -fix [-diff] Pass stdout through. + // go vet -fix [-diff] => cmd/vet -fix [-diff] Pass stdout through (and exit 1 if diffs). + // go fix [-diff] => cmd/fix -fix [-diff] Pass stdout through (and exit 1 if diffs). // go fix -json => cmd/fix -json Pass stdout through. // // Notes: @@ -176,6 +180,7 @@ func run(ctx context.Context, cmd *base.Command, args []string) { work.VetExplicit = len(toolFlags) > 0 + applyFixes := false if cmd.Name() == "fix" || *vetFixFlag { // fix mode: 'go fix' or 'go vet -fix' if jsonFlag { @@ -186,6 +191,12 @@ func run(ctx context.Context, cmd *base.Command, args []string) { toolFlags = append(toolFlags, "-fix") if diffFlag { toolFlags = append(toolFlags, "-diff") + // In -diff mode, the tool prints unified diffs to stdout. + // Copy stdout through and exit non-zero if diffs were printed, + // consistent with gofmt -d and go mod tidy -diff. + work.VetHandleStdout = copyAndDetectDiff + } else { + applyFixes = true } } if contextFlag != -1 { @@ -209,30 +220,38 @@ func run(ctx context.Context, cmd *base.Command, args []string) { // Implement legacy "go fix -fix=name,..." flag. if *fixFixFlag != "" { - fmt.Fprintf(os.Stderr, "go %s: the -fix=%s flag is obsolete and has no effect", cmd.Name(), *fixFixFlag) + fmt.Fprintf(os.Stderr, "go %s: the -fix=%s flag is obsolete and has no effect\n", cmd.Name(), *fixFixFlag) // The buildtag fixer is now implemented by cmd/fix. if slices.Contains(strings.Split(*fixFixFlag, ","), "buildtag") { - fmt.Fprintf(os.Stderr, "go %s: to enable the buildtag check, use -buildtag", cmd.Name()) + fmt.Fprintf(os.Stderr, "go %s: to enable the buildtag check, use -buildtag\n", cmd.Name()) } } work.VetFlags = toolFlags pkgOpts := load.PackageOpts{ModResolveTests: true} - pkgs := load.PackagesAndErrors(moduleLoaderState, ctx, pkgOpts, pkgArgs) + pkgs := load.PackagesAndErrors(moduleLoader, ctx, pkgOpts, pkgArgs) load.CheckPackageErrors(pkgs) if len(pkgs) == 0 { base.Fatalf("no packages to %s", cmd.Name()) } - b := work.NewBuilder("", moduleLoaderState.VendorDirOrEmpty) + // Build action graph. + b := work.NewBuilder("", moduleLoader.VendorDirOrEmpty) defer func() { if err := b.Close(); err != nil { base.Fatal(err) } }() + root := &work.Action{Mode: "go " + cmd.Name()} + + addVetAction := func(p *load.Package) { + act := b.VetAction(moduleLoader, work.ModeBuild, work.ModeBuild, applyFixes, p) + root.Deps = append(root.Deps, act) + } + // To avoid file corruption from duplicate application of // fixes (in fix mode), and duplicate reporting of diagnostics // (in vet mode), we must run the tool only once for each @@ -248,10 +267,17 @@ func run(ctx context.Context, cmd *base.Command, args []string) { // We needn't worry about intermediate test variants, as they // will only be executed in VetxOnly mode, for facts but not // diagnostics. - - root := &work.Action{Mode: "go " + cmd.Name()} for _, p := range pkgs { - _, ptest, pxtest, perr := load.TestPackagesFor(moduleLoaderState, ctx, pkgOpts, p, nil) + // Don't apply fixes to vendored packages, including + // the GOROOT vendor packages that are part of std, + // or to packages from non-main modules (#76479). + if applyFixes { + if p.Standard && strings.HasPrefix(p.ImportPath, "vendor/") || + p.Module != nil && !p.Module.Main { + continue + } + } + _, ptest, pxtest, perr := load.TestPackagesFor(moduleLoader, ctx, pkgOpts, p, nil) if perr != nil { base.Errorf("%v", perr.Error) continue @@ -262,13 +288,83 @@ func run(ctx context.Context, cmd *base.Command, args []string) { } if len(ptest.GoFiles) > 0 || len(ptest.CgoFiles) > 0 { // The test package includes all the files of primary package. - root.Deps = append(root.Deps, b.VetAction(moduleLoaderState, work.ModeBuild, work.ModeBuild, ptest)) + addVetAction(ptest) } if pxtest != nil { - root.Deps = append(root.Deps, b.VetAction(moduleLoaderState, work.ModeBuild, work.ModeBuild, pxtest)) + addVetAction(pxtest) } } b.Do(ctx, root) + + // Apply fixes. + // + // We do this as a separate phase after the build to avoid + // races between source file updates and reads of those same + // files by concurrent actions of the ongoing build. + // + // If a file is fixed by multiple actions, they must be consistent. + if applyFixes { + contents := make(map[string][]byte) + // Gather the fixes. + for _, act := range root.Deps { + if act.FixArchive != "" { + if err := readZip(act.FixArchive, contents); err != nil { + base.Errorf("reading archive of fixes: %v", err) + return + } + } + } + // Apply them. + for filename, content := range contents { + if err := os.WriteFile(filename, content, 0644); err != nil { + base.Errorf("applying fix: %v", err) + } + } + } +} + +// readZip reads the zipfile entries into the provided map. +// It reports an error if updating the map would change an existing entry. +func readZip(zipfile string, out map[string][]byte) error { + r, err := zip.OpenReader(zipfile) + if err != nil { + return err + } + defer r.Close() // ignore error + for _, f := range r.File { + rc, err := f.Open() + if err != nil { + return err + } + content, err := io.ReadAll(rc) + rc.Close() // ignore error + if err != nil { + return err + } + if prev, ok := out[f.Name]; ok && !bytes.Equal(prev, content) { + return fmt.Errorf("inconsistent fixes to file %v", f.Name) + } + out[f.Name] = content + } + return nil +} + +// copyAndDetectDiff copies the tool's stdout to the go command's stdout +// and sets exit status 1 if any output was produced (meaning diffs exist). +// This is used in -diff mode to implement the convention that "go fix -diff" +// exits non-zero when the diff is not empty, consistent with gofmt -d +// and go mod tidy -diff. +func copyAndDetectDiff(r io.Reader) error { + stdouterrMu.Lock() + defer stdouterrMu.Unlock() + n, err := io.Copy(os.Stdout, r) + if err != nil { + return fmt.Errorf("copying diff output: %w", err) + } + if n > 0 { + base.SetExitStatus(1) + } + return nil } // printJSONDiagnostics parses JSON (from the tool's stdout) and @@ -314,11 +410,11 @@ func printJSONDiagnostics(r io.Reader) error { return nil } -var stderrMu sync.Mutex // serializes concurrent writes to stdout +var stdouterrMu sync.Mutex // serializes concurrent writes to stdout and stderr func printJSONDiagnostic(analyzer string, diag jsonDiagnostic) { - stderrMu.Lock() - defer stderrMu.Unlock() + stdouterrMu.Lock() + defer stdouterrMu.Unlock() type posn struct { file string diff --git a/src/cmd/go/internal/web/http.go b/src/cmd/go/internal/web/http.go index 2ef8169db5c37f..45032bf5f0fb14 100644 --- a/src/cmd/go/internal/web/http.go +++ b/src/cmd/go/internal/web/http.go @@ -31,6 +31,8 @@ import ( "cmd/internal/browser" ) +const userAgent = "GoCommand/1 (+https://go.dev/cmd/go)" + // impatientInsecureHTTPClient is used with GOINSECURE, // when we're connecting to https servers that might not be there // or might be using self-signed certificates. @@ -82,21 +84,6 @@ func get(security SecurityMode, url *urlpkg.URL) (*Response, error) { if intercept.TestHooksEnabled { switch url.Host { - case "proxy.golang.org": - if os.Getenv("TESTGOPROXY404") == "1" { - res := &Response{ - URL: url.Redacted(), - Status: "404 testing", - StatusCode: 404, - Header: make(map[string][]string), - Body: http.NoBody, - } - if cfg.BuildX { - fmt.Fprintf(os.Stderr, "# get %s: %v (%.3fs)\n", url.Redacted(), res.Status, time.Since(start).Seconds()) - } - return res, nil - } - case "localhost.localdev": return nil, fmt.Errorf("no such host localhost.localdev") @@ -146,6 +133,7 @@ func get(security SecurityMode, url *urlpkg.URL) (*Response, error) { req.Host = req.URL.Host req.URL.Host = t.ToHost } + req.Header.Set("User-Agent", userAgent) release, err := base.AcquireNet() if err != nil { diff --git a/src/cmd/go/internal/web/http_test.go b/src/cmd/go/internal/web/http_test.go new file mode 100644 index 00000000000000..b1c0206cb56c61 --- /dev/null +++ b/src/cmd/go/internal/web/http_test.go @@ -0,0 +1,38 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package web + +import ( + "bytes" + "io" + "net/http" + "net/http/httptest" + "net/url" + "testing" +) + +func TestUserAgent(t *testing.T) { + ts := httptest.NewServer(http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { + w.Write([]byte(r.UserAgent())) + })) + defer ts.Close() + + u, err := url.Parse(ts.URL) + if err != nil { + t.Fatal("parse httptest url:", err) + } + res, err := Get(Insecure, u) + if err != nil { + t.Error("http get:", err) + } + b, err := io.ReadAll(res.Body) + if err != nil { + t.Error("read response body:", err) + } + gotUserAgent := string(bytes.TrimSpace(b)) + if gotUserAgent != userAgent { + t.Errorf("User-Agent: %s, want %s", gotUserAgent, userAgent) + } +} diff --git a/src/cmd/go/internal/work/action.go b/src/cmd/go/internal/work/action.go index 698a523c25145f..8b3897e215ed57 100644 --- a/src/cmd/go/internal/work/action.go +++ b/src/cmd/go/internal/work/action.go @@ -109,11 +109,13 @@ type Action struct { actionID cache.ActionID // cache ID of action input buildID string // build ID of action output - VetxOnly bool // Mode=="vet": only being called to supply info about dependencies - needVet bool // Mode=="build": need to fill in vet config - needBuild bool // Mode=="build": need to do actual build (can be false if needVet is true) - vetCfg *vetConfig // vet config - output []byte // output redirect buffer (nil means use b.Print) + VetxOnly bool // Mode=="vet": only being called to supply info about dependencies + needVet bool // Mode=="build": need to fill in vet config + needBuild bool // Mode=="build": need to do actual build (can be false if needVet is true) + needFix bool // Mode=="vet": need secondary target, a .zip file containing fixes + vetCfg *vetConfig // vet config + FixArchive string // the created .zip file containing fixes (if needFix) + output []byte // output redirect buffer (nil means use b.Print) sh *Shell // lazily created per-Action shell; see Builder.Shell @@ -395,7 +397,7 @@ func (b *Builder) NewObjdir() string { // at shlibpath. For the native toolchain this list is stored, newline separated, in // an ELF note with name "Go\x00\x00" and type 1. For GCCGO it is extracted from the // .go_export section. -func readpkglist(s *modload.State, shlibpath string) (pkgs []*load.Package) { +func readpkglist(s *modload.Loader, shlibpath string) (pkgs []*load.Package) { var stk load.ImportStack if cfg.BuildToolchainName == "gccgo" { f, err := elf.Open(shlibpath) @@ -446,7 +448,7 @@ func (b *Builder) cacheAction(mode string, p *load.Package, f func() *Action) *A } // AutoAction returns the "right" action for go build or go install of p. -func (b *Builder) AutoAction(s *modload.State, mode, depMode BuildMode, p *load.Package) *Action { +func (b *Builder) AutoAction(s *modload.Loader, mode, depMode BuildMode, p *load.Package) *Action { if p.Name == "main" { return b.LinkAction(s, mode, depMode, p) } @@ -869,13 +871,14 @@ func (b *Builder) cgoAction(p *load.Package, objdir string, deps []*Action, hasC // It depends on the action for compiling p. // If the caller may be causing p to be installed, it is up to the caller // to make sure that the install depends on (runs after) vet. -func (b *Builder) VetAction(s *modload.State, mode, depMode BuildMode, p *load.Package) *Action { +func (b *Builder) VetAction(s *modload.Loader, mode, depMode BuildMode, needFix bool, p *load.Package) *Action { a := b.vetAction(s, mode, depMode, p) a.VetxOnly = false + a.needFix = needFix return a } -func (b *Builder) vetAction(s *modload.State, mode, depMode BuildMode, p *load.Package) *Action { +func (b *Builder) vetAction(s *modload.Loader, mode, depMode BuildMode, p *load.Package) *Action { // Construct vet action. a := b.cacheAction("vet", p, func() *Action { a1 := b.CompileAction(mode|ModeVetOnly, depMode, p) @@ -916,7 +919,7 @@ func (b *Builder) vetAction(s *modload.State, mode, depMode BuildMode, p *load.P // LinkAction returns the action for linking p into an executable // and possibly installing the result (according to mode). // depMode is the action (build or install) to use when compiling dependencies. -func (b *Builder) LinkAction(s *modload.State, mode, depMode BuildMode, p *load.Package) *Action { +func (b *Builder) LinkAction(s *modload.Loader, mode, depMode BuildMode, p *load.Package) *Action { // Construct link action. a := b.cacheAction("link", p, func() *Action { a := &Action{ @@ -1037,7 +1040,7 @@ func (b *Builder) installAction(a1 *Action, mode BuildMode) *Action { // makes sure those are present in a.Deps. // If shlib is non-empty, then a corresponds to the build and installation of shlib, // so any rebuild of shlib should not be added as a dependency. -func (b *Builder) addTransitiveLinkDeps(s *modload.State, a, a1 *Action, shlib string) { +func (b *Builder) addTransitiveLinkDeps(s *modload.Loader, a, a1 *Action, shlib string) { // Expand Deps to include all built packages, for the linker. // Use breadth-first search to find rebuilt-for-test packages // before the standard ones. @@ -1114,7 +1117,7 @@ func (b *Builder) addInstallHeaderAction(a *Action) { // buildmodeShared takes the "go build" action a1 into the building of a shared library of a1.Deps. // That is, the input a1 represents "go build pkgs" and the result represents "go build -buildmode=shared pkgs". -func (b *Builder) buildmodeShared(s *modload.State, mode, depMode BuildMode, args []string, pkgs []*load.Package, a1 *Action) *Action { +func (b *Builder) buildmodeShared(s *modload.Loader, mode, depMode BuildMode, args []string, pkgs []*load.Package, a1 *Action) *Action { name, err := libname(args, pkgs) if err != nil { base.Fatalf("%v", err) @@ -1126,7 +1129,7 @@ func (b *Builder) buildmodeShared(s *modload.State, mode, depMode BuildMode, arg // and returns an action that links them together into a shared library with the name shlib. // If a1 is nil, shlib should be an absolute path to an existing shared library, // and then linkSharedAction reads that library to find out the package list. -func (b *Builder) linkSharedAction(s *modload.State, mode, depMode BuildMode, shlib string, a1 *Action) *Action { +func (b *Builder) linkSharedAction(s *modload.Loader, mode, depMode BuildMode, shlib string, a1 *Action) *Action { fullShlib := shlib shlib = filepath.Base(shlib) a := b.cacheAction("build-shlib "+shlib, nil, func() *Action { diff --git a/src/cmd/go/internal/work/build.go b/src/cmd/go/internal/work/build.go index 7ca95cbe3f9286..969e0029c3e294 100644 --- a/src/cmd/go/internal/work/build.go +++ b/src/cmd/go/internal/work/build.go @@ -155,7 +155,7 @@ and test commands: By default, if a vendor directory is present and the go version in go.mod is 1.14 or higher, the go command acts as if -mod=vendor were set. Otherwise, the go command acts as if -mod=readonly were set. - See https://golang.org/ref/mod#build-commands for details. + See https://go.dev/ref/mod#build-commands for details. -modcacherw leave newly-created directories in the module cache read-write instead of making them read-only. @@ -223,12 +223,14 @@ only for package fmt, while 'go build -gcflags=all=-S fmt' prints the disassembly for fmt and all its dependencies. For more about specifying packages, see 'go help packages'. -For more about where packages and binaries are installed, -run 'go help gopath'. +For more about where binaries are installed, run 'go help gopath'. For more about calling between Go and C/C++, run 'go help c'. +For more about project organization, run 'go help modules'. -Note: Build adheres to certain conventions such as those described -by 'go help gopath'. Not all projects can follow these conventions, +Note: go build adheres to certain conventions for organizing projects: +it primarily supports go modules (see 'go help modules') while +also supporting an alternative GOPATH mode (see 'go help gopath'). +Not all projects can follow these conventions, however. Installations that have their own conventions or that use a separate software build system may choose to use lower-level invocations such as 'go tool compile' and 'go tool link' to avoid @@ -238,8 +240,6 @@ See also: go install, go get, go clean. `, } -const concurrentGCBackendCompilationEnabledByDefault = true - func init() { // break init cycle CmdBuild.Run = runBuild @@ -459,17 +459,17 @@ func oneMainPkg(pkgs []*load.Package) []*load.Package { var pkgsFilter = func(pkgs []*load.Package) []*load.Package { return pkgs } func runBuild(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) - BuildInit(moduleLoaderState) - b := NewBuilder("", moduleLoaderState.VendorDirOrEmpty) + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() + BuildInit(moduleLoader) + b := NewBuilder("", moduleLoader.VendorDirOrEmpty) defer func() { if err := b.Close(); err != nil { base.Fatal(err) } }() - pkgs := load.PackagesAndErrors(moduleLoaderState, ctx, load.PackageOpts{AutoVCS: true}, args) + pkgs := load.PackagesAndErrors(moduleLoader, ctx, load.PackageOpts{AutoVCS: true}, args) load.CheckPackageErrors(pkgs) explicitO := len(cfg.BuildO) > 0 @@ -504,7 +504,7 @@ func runBuild(ctx context.Context, cmd *base.Command, args []string) { } if cfg.BuildCover { - load.PrepareForCoverageBuild(moduleLoaderState, pkgs) + load.PrepareForCoverageBuild(moduleLoader, pkgs) } if cfg.BuildO != "" { @@ -528,7 +528,7 @@ func runBuild(ctx context.Context, cmd *base.Command, args []string) { p.Target += cfg.ExeSuffix p.Stale = true p.StaleReason = "build -o flag in use" - a.Deps = append(a.Deps, b.AutoAction(moduleLoaderState, ModeInstall, depMode, p)) + a.Deps = append(a.Deps, b.AutoAction(moduleLoader, ModeInstall, depMode, p)) } if len(a.Deps) == 0 { base.Fatalf("go: no main packages to build") @@ -545,17 +545,17 @@ func runBuild(ctx context.Context, cmd *base.Command, args []string) { p.Target = cfg.BuildO p.Stale = true // must build - not up to date p.StaleReason = "build -o flag in use" - a := b.AutoAction(moduleLoaderState, ModeInstall, depMode, p) + a := b.AutoAction(moduleLoader, ModeInstall, depMode, p) b.Do(ctx, a) return } a := &Action{Mode: "go build"} for _, p := range pkgs { - a.Deps = append(a.Deps, b.AutoAction(moduleLoaderState, ModeBuild, depMode, p)) + a.Deps = append(a.Deps, b.AutoAction(moduleLoader, ModeBuild, depMode, p)) } if cfg.BuildBuildmode == "shared" { - a = b.buildmodeShared(moduleLoaderState, ModeBuild, depMode, args, pkgs, a) + a = b.buildmodeShared(moduleLoader, ModeBuild, depMode, args, pkgs, a) } b.Do(ctx, a) } @@ -688,18 +688,18 @@ func libname(args []string, pkgs []*load.Package) (string, error) { } func runInstall(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() for _, arg := range args { if strings.Contains(arg, "@") && !build.IsLocalImport(arg) && !filepath.IsAbs(arg) { - installOutsideModule(moduleLoaderState, ctx, args) + installOutsideModule(moduleLoader, ctx, args) return } } - modload.InitWorkfile(moduleLoaderState) - BuildInit(moduleLoaderState) - pkgs := load.PackagesAndErrors(moduleLoaderState, ctx, load.PackageOpts{AutoVCS: true}, args) - if cfg.ModulesEnabled && !modload.HasModRoot(moduleLoaderState) { + moduleLoader.InitWorkfile() + BuildInit(moduleLoader) + pkgs := load.PackagesAndErrors(moduleLoader, ctx, load.PackageOpts{AutoVCS: true}, args) + if cfg.ModulesEnabled && !moduleLoader.HasModRoot() { haveErrors := false allMissingErrors := true for _, pkg := range pkgs { @@ -724,10 +724,10 @@ func runInstall(ctx context.Context, cmd *base.Command, args []string) { load.CheckPackageErrors(pkgs) if cfg.BuildCover { - load.PrepareForCoverageBuild(moduleLoaderState, pkgs) + load.PrepareForCoverageBuild(moduleLoader, pkgs) } - InstallPackages(moduleLoaderState, ctx, args, pkgs) + InstallPackages(moduleLoader, ctx, args, pkgs) } // omitTestOnly returns pkgs with test-only packages removed. @@ -747,7 +747,7 @@ func omitTestOnly(pkgs []*load.Package) []*load.Package { return list } -func InstallPackages(loaderstate *modload.State, ctx context.Context, patterns []string, pkgs []*load.Package) { +func InstallPackages(ld *modload.Loader, ctx context.Context, patterns []string, pkgs []*load.Package) { ctx, span := trace.StartSpan(ctx, "InstallPackages "+strings.Join(patterns, " ")) defer span.Done() @@ -785,7 +785,7 @@ func InstallPackages(loaderstate *modload.State, ctx context.Context, patterns [ } base.ExitIfErrors() - b := NewBuilder("", loaderstate.VendorDirOrEmpty) + b := NewBuilder("", ld.VendorDirOrEmpty) defer func() { if err := b.Close(); err != nil { base.Fatal(err) @@ -799,7 +799,7 @@ func InstallPackages(loaderstate *modload.State, ctx context.Context, patterns [ // If p is a tool, delay the installation until the end of the build. // This avoids installing assemblers/compilers that are being executed // by other steps in the build. - a1 := b.AutoAction(loaderstate, ModeInstall, depMode, p) + a1 := b.AutoAction(ld, ModeInstall, depMode, p) if load.InstallTargetDir(p) == load.ToTool { a.Deps = append(a.Deps, a1.Deps...) a1.Deps = append(a1.Deps, a) @@ -821,7 +821,7 @@ func InstallPackages(loaderstate *modload.State, ctx context.Context, patterns [ // tools above did not apply, and a is just a simple Action // with a list of Deps, one per package named in pkgs, // the same as in runBuild. - a = b.buildmodeShared(loaderstate, ModeInstall, ModeInstall, patterns, pkgs, a) + a = b.buildmodeShared(ld, ModeInstall, ModeInstall, patterns, pkgs, a) } b.Do(ctx, a) @@ -860,12 +860,12 @@ func InstallPackages(loaderstate *modload.State, ctx context.Context, patterns [ // in the current directory or parent directories. // // See golang.org/issue/40276 for details and rationale. -func installOutsideModule(loaderstate *modload.State, ctx context.Context, args []string) { - loaderstate.ForceUseModules = true - loaderstate.RootMode = modload.NoRoot - modload.AllowMissingModuleImports(loaderstate) - modload.Init(loaderstate) - BuildInit(loaderstate) +func installOutsideModule(ld *modload.Loader, ctx context.Context, args []string) { + ld.ForceUseModules = true + ld.RootMode = modload.NoRoot + ld.AllowMissingModuleImports() + modload.Init(ld) + BuildInit(ld) // Load packages. Ignore non-main packages. // Print a warning if an argument contains "..." and matches no main packages. @@ -874,7 +874,7 @@ func installOutsideModule(loaderstate *modload.State, ctx context.Context, args // TODO(golang.org/issue/40276): don't report errors loading non-main packages // matched by a pattern. pkgOpts := load.PackageOpts{MainOnly: true} - pkgs, err := load.PackagesAndErrorsOutsideModule(loaderstate, ctx, pkgOpts, args) + pkgs, err := load.PackagesAndErrorsOutsideModule(ld, ctx, pkgOpts, args) if err != nil { base.Fatal(err) } @@ -885,7 +885,7 @@ func installOutsideModule(loaderstate *modload.State, ctx context.Context, args } // Build and install the packages. - InstallPackages(loaderstate, ctx, patterns, pkgs) + InstallPackages(ld, ctx, patterns, pkgs) } // ExecCmd is the command to use to run user binaries. diff --git a/src/cmd/go/internal/work/cover.go b/src/cmd/go/internal/work/cover.go index fc96f67d6e8a0b..be090ce4c3b50b 100644 --- a/src/cmd/go/internal/work/cover.go +++ b/src/cmd/go/internal/work/cover.go @@ -24,7 +24,7 @@ import ( func (b *Builder) CovData(a *Action, cmdargs ...any) ([]byte, error) { cmdline := str.StringList(cmdargs...) args := append([]string{}, cfg.BuildToolexec...) - args = append(args, "go", "tool", "covdata") + args = append(args, filepath.Join(cfg.GOROOTbin, "go"), "tool", "covdata") args = append(args, cmdline...) return b.Shell(a).runOut(a.Objdir, nil, args) } diff --git a/src/cmd/go/internal/work/exec.go b/src/cmd/go/internal/work/exec.go index 0c9e96aebbf080..3ed01c0fbd49b8 100644 --- a/src/cmd/go/internal/work/exec.go +++ b/src/cmd/go/internal/work/exec.go @@ -39,12 +39,15 @@ import ( "cmd/go/internal/fsys" "cmd/go/internal/gover" "cmd/go/internal/load" + "cmd/go/internal/modinfo" "cmd/go/internal/modload" "cmd/go/internal/str" "cmd/go/internal/trace" "cmd/internal/buildid" "cmd/internal/quoted" "cmd/internal/sys" + + "golang.org/x/tools/go/analysis" ) const DefaultCFlags = "-O2 -g" @@ -248,6 +251,11 @@ func (b *Builder) Do(ctx context.Context, root *Action) { wg.Wait() + if tokens != totalTokens || concurrentProcesses != 0 { + base.Fatalf("internal error: tokens not restored at end of build: tokens: %d, totalTokens: %d, concurrentProcesses: %d", + tokens, totalTokens, concurrentProcesses) + } + // Write action graph again, this time with timing information. writeActionGraph() } @@ -622,7 +630,7 @@ func (b *Builder) checkCacheForBuild(a, buildAction *Action, covMetaFileName str // If we are going to do a full build anyway, // we're going to regenerate the files in the build action anyway. if need == needVet { - if err := b.loadCachedVet(buildAction); err == nil { + if err := b.loadCachedVet(buildAction, a.Deps); err == nil { need &^= needVet } } @@ -836,7 +844,7 @@ func (b *Builder) build(ctx context.Context, a *Action) (err error) { // Prepare Go vet config if needed. if need&needVet != 0 { - buildVetConfig(a, srcfiles) + buildVetConfig(a, srcfiles, a.Deps) need &^= needVet } if need&needCompiledGoFiles != 0 { @@ -923,6 +931,12 @@ func (b *Builder) build(ctx context.Context, a *Action) (err error) { // Compile Go. objpkg := objdir + "_pkg_.a" ofile, out, err := BuildToolchain.gc(b, a, objpkg, icfg.Bytes(), embedcfg, symabis, len(sfiles) > 0, pgoProfile, gofiles) + if len(out) > 0 && (p.UsesCgo() || p.UsesSwig()) && !cfg.BuildX { + // Fix up output referring to cgo-generated code to be more readable. + // Replace *[100]_Ctype_foo with *[100]C.foo. + // If we're using -x, assume we're debugging and want the full dump, so disable the rewrite. + out = cgoTypeSigRe.ReplaceAll(out, []byte("C.")) + } if err := sh.reportCmd("", "", out, err); err != nil { return err } @@ -1028,6 +1042,8 @@ func (b *Builder) build(ctx context.Context, a *Action) (err error) { return nil } +var cgoTypeSigRe = lazyregexp.New(`\b_C2?(type|func|var|macro)_\B`) + func (b *Builder) checkDirectives(a *Action) error { var msg []byte p := a.Package @@ -1116,7 +1132,7 @@ func (b *Builder) cacheSrcFiles(a *Action, srcfiles []string) { cache.PutBytes(c, cache.Subkey(a.actionID, "srcfiles"), buf.Bytes()) } -func (b *Builder) loadCachedVet(a *Action) error { +func (b *Builder) loadCachedVet(a *Action, vetDeps []*Action) error { c := cache.Default() list, _, err := cache.GetBytes(c, cache.Subkey(a.actionID, "srcfiles")) if err != nil { @@ -1136,7 +1152,7 @@ func (b *Builder) loadCachedVet(a *Action) error { } srcfiles = append(srcfiles, a.Objdir+name) } - buildVetConfig(a, srcfiles) + buildVetConfig(a, srcfiles, vetDeps) return nil } @@ -1177,21 +1193,43 @@ type vetConfig struct { NonGoFiles []string // absolute paths to package non-Go files IgnoredFiles []string // absolute paths to ignored source files - ModulePath string // module path (may be "" on module error) - ModuleVersion string // module version (may be "" on main module or module error) - ImportMap map[string]string // map import path in source code to package path - PackageFile map[string]string // map package path to .a file with export data - Standard map[string]bool // map package path to whether it's in the standard library - PackageVetx map[string]string // map package path to vetx data from earlier vet run - VetxOnly bool // only compute vetx data; don't report detected problems - VetxOutput string // write vetx data to this output file - Stdout string // write stdout (JSON, unified diff) to this output file - GoVersion string // Go version for package + Module *analysis.Module // module information, if any + ImportMap map[string]string // map import path in source code to package path + PackageFile map[string]string // map package path to .a file with export data + Standard map[string]bool // map package path to whether it's in the standard library + PackageVetx map[string]string // map package path to vetx data from earlier vet run + VetxOnly bool // only compute vetx data; don't report detected problems + VetxOutput string // write vetx data to this output file + Stdout string // write stdout (JSON, unified diff) to this output file + GoVersion string // Go version for package + FixArchive string // write fixed files to this zip archive, if non-empty SucceedOnTypecheckFailure bool // awful hack; see #18395 and below } -func buildVetConfig(a *Action, srcfiles []string) { +// analysisModuleFromModulePublic converts a modinfo.ModulePublic to a analysis.Module. +func analysisModuleFromModulePublic(m *modinfo.ModulePublic) *analysis.Module { + if m == nil { + return nil + } + vm := &analysis.Module{ + Path: m.Path, + Version: m.Version, + Replace: analysisModuleFromModulePublic(m.Replace), + Time: m.Time, + Main: m.Main, + Indirect: m.Indirect, + Dir: m.Dir, + GoMod: m.GoMod, + GoVersion: m.GoVersion, + } + if m.Error != nil { + vm.Error = &analysis.ModuleError{Err: m.Error.Err} + } + return vm +} + +func buildVetConfig(a *Action, srcfiles []string, vetDeps []*Action) { // Classify files based on .go extension. // srcfiles does not include raw cgo files. var gofiles, nongofiles []string @@ -1228,11 +1266,7 @@ func buildVetConfig(a *Action, srcfiles []string) { v = gover.DefaultGoModVersion } vcfg.GoVersion = "go" + v - - if a.Package.Module.Error == nil { - vcfg.ModulePath = a.Package.Module.Path - vcfg.ModuleVersion = a.Package.Module.Version - } + vcfg.Module = analysisModuleFromModulePublic(a.Package.Module) } a.vetCfg = vcfg for i, raw := range a.Package.Internal.RawImports { @@ -1247,7 +1281,7 @@ func buildVetConfig(a *Action, srcfiles []string) { vcfgMapped[p] = true } - for _, a1 := range a.Deps { + for _, a1 := range vetDeps { p1 := a1.Package if p1 == nil || p1.ImportPath == "" || p1 == a.Package { continue @@ -1308,10 +1342,14 @@ func (b *Builder) vet(ctx context.Context, a *Action) error { vcfg.VetxOnly = a.VetxOnly vcfg.VetxOutput = a.Objdir + "vet.out" vcfg.Stdout = a.Objdir + "vet.stdout" + if a.needFix { + vcfg.FixArchive = a.Objdir + "vet.fix.zip" + } vcfg.PackageVetx = make(map[string]string) h := cache.NewHash("vet " + a.Package.ImportPath) fmt.Fprintf(h, "vet %q\n", b.toolID("vet")) + fmt.Fprintf(h, "vetxonly %v\n", vcfg.VetxOnly) vetFlags := VetFlags @@ -1331,6 +1369,12 @@ func (b *Builder) vet(ctx context.Context, a *Action) error { // dependency tree turn on *more* analysis, as here. // (The unsafeptr check does not write any facts for use by // later vet runs, nor does unreachable.) + // + // When changing the default analyzer suite, please update + // x/tools/go/analysis/unitchecker/vet_std_test.go too so that + // it functions as a consistent early-warning system for + // changes to analyzers (as opposed to changes in the target + // packages, which is the purpose of this logic). if a.Package.Goroot && !VetExplicit && VetTool == base.Tool("vet") { // Turn off -unsafeptr checks. // There's too much unsafe.Pointer code @@ -1368,31 +1412,60 @@ func (b *Builder) vet(ctx context.Context, a *Action) error { vcfg.PackageVetx[a1.Package.ImportPath] = a1.built } } - vetxKey := cache.ActionID(h.Sum()) // for .vetx file - - fmt.Fprintf(h, "stdout\n") - stdoutKey := cache.ActionID(h.Sum()) // for .stdout file + var ( + id = cache.ActionID(h.Sum()) // for .vetx file + stdoutKey = cache.Subkey(id, "stdout") // for .stdout file + fixArchiveKey = cache.Subkey(id, "fix.zip") // for .fix.zip file + ) // Check the cache; -a forces a rebuild. if !cfg.BuildA { c := cache.Default() - if vcfg.VetxOnly { - if file, _, err := cache.GetFile(c, vetxKey); err == nil { - a.built = file - return nil + + // There may be multiple artifacts in the cache. + // We need to retrieve them all, or none: + // the effect must be transactional. + var ( + vetxFile string // name of cached .vetx file + fixArchive string // name of cached .fix.zip file + stdout io.Reader = bytes.NewReader(nil) // cached stdout stream + ) + + // Obtain location of cached .vetx file. + vetxFile, _, err := cache.GetFile(c, id) + if err != nil { + goto cachemiss + } + + // Obtain location of cached .fix.zip file (if needed). + if a.needFix { + file, _, err := cache.GetFile(c, fixArchiveKey) + if err != nil { + goto cachemiss } - } else { - // Copy cached vet.std files to stdout. - if file, _, err := cache.GetFile(c, stdoutKey); err == nil { - f, err := os.Open(file) - if err != nil { - return err - } - defer f.Close() // ignore error (can't fail) - return VetHandleStdout(f) + fixArchive = file + } + + // Copy cached .stdout file to stdout. + if file, _, err := cache.GetFile(c, stdoutKey); err == nil { + f, err := os.Open(file) + if err != nil { + goto cachemiss } + defer f.Close() // ignore error (can't fail) + stdout = f } + + // Cache hit: commit transaction. + a.built = vetxFile + a.FixArchive = fixArchive + if err := VetHandleStdout(stdout); err != nil { + return err // internal error (don't fall through to cachemiss) + } + + return nil } +cachemiss: js, err := json.MarshalIndent(vcfg, "", "\t") if err != nil { @@ -1419,13 +1492,23 @@ func (b *Builder) vet(ctx context.Context, a *Action) error { return err } - // Vet tool succeeded, possibly with facts and JSON stdout. Save both in cache. + // Vet tool succeeded, possibly with facts, fixes, or JSON stdout. + // Save all in cache. - // Save facts + // Save facts. if f, err := os.Open(vcfg.VetxOutput); err == nil { defer f.Close() // ignore error a.built = vcfg.VetxOutput - cache.Default().Put(vetxKey, f) // ignore error + cache.Default().Put(id, f) // ignore error + } + + // Save fix archive (if any). + if a.needFix { + if f, err := os.Open(vcfg.FixArchive); err == nil { + defer f.Close() // ignore error + a.FixArchive = vcfg.FixArchive + cache.Default().Put(fixArchiveKey, f) // ignore error + } } // Save stdout. @@ -1740,6 +1823,11 @@ func (b *Builder) getPkgConfigFlags(a *Action, p *load.Package) (cflags, ldflags return nil, nil, fmt.Errorf("invalid pkg-config package name: %s", pkg) } } + + if err := checkPkgConfigFlags("", "pkg-config", pcflags); err != nil { + return nil, nil, err + } + var out []byte out, err = sh.runOut(p.Dir, nil, b.PkgconfigCmd(), "--cflags", pcflags, "--", pkgs) if err != nil { @@ -2395,12 +2483,7 @@ func (b *Builder) compilerCmd(compiler []string, incdir, workdir string) []strin // gcc-4.5 and beyond require explicit "-pthread" flag // for multithreading with pthread library. if cfg.BuildContext.CgoEnabled { - switch cfg.Goos { - case "windows": - a = append(a, "-mthreads") - default: - a = append(a, "-pthread") - } + a = append(a, "-pthread") } if cfg.Goos == "aix" { @@ -2724,7 +2807,12 @@ func (b *Builder) gccArchArgs() []string { return append(args, "-msoft-float") } case "loong64": - return []string{"-mabi=lp64d"} + // On loong64, gcc and clang enable relaxation optimization by default, forcing + // Go to handle corresponding relocations. Otherwise, it can lead to unreachable + // jump instructions and an excessive number of temporary symbols in the findfunc + // table. We added the -mno-relax option to disable relaxation optimization in the + // cgo code to ensure that Go doesn't encounter errors without additional processing. + return []string{"-mabi=lp64d", "-mno-relax"} case "ppc64": if cfg.Goos == "aix" { return []string{"-maix64"} @@ -2797,7 +2885,7 @@ func (pr *runCgoProvider) cxxflags() []string { } func (pr *runCgoProvider) fflags() []string { - return pr.CXXFLAGS + return pr.FFLAGS } func (pr *runCgoProvider) ldflags() []string { @@ -2899,6 +2987,11 @@ func (b *Builder) runCgo(ctx context.Context, a *Action) error { flagSources := []string{"CGO_CFLAGS", "CGO_CXXFLAGS", "CGO_FFLAGS"} flagLists := [][]string{cgoCFLAGS, cgoCXXFLAGS, cgoFFLAGS} notCompatibleWithInternalLinking := flagsNotCompatibleWithInternalLinking(flagSources, flagLists) + if !notCompatibleWithInternalLinking { + if err := checkLinkerFlagsForInternalLink("CGO_LDFLAGS", "CGO_LDFLAGS", cgoLDFLAGS); err != nil { + notCompatibleWithInternalLinking = true + } + } if cfg.BuildMSan { cgoCFLAGS = append([]string{"-fsanitize=memory"}, cgoCFLAGS...) @@ -3270,7 +3363,7 @@ func (b *Builder) swig(a *Action, objdir string, pcCFLAGS []string) error { } } for _, f := range p.SwigCXXFiles { - if b.swigOne(a, f, objdir, pcCFLAGS, true, intgosize); err != nil { + if err := b.swigOne(a, f, objdir, pcCFLAGS, true, intgosize); err != nil { return err } } @@ -3383,7 +3476,7 @@ func (b *Builder) swigDoIntSize(objdir string) (intsize string, err error) { } srcs := []string{src} - p := load.GoFilesPackage(modload.NewState(), context.TODO(), load.PackageOpts{}, srcs) + p := load.GoFilesPackage(modload.NewLoader(), context.TODO(), load.PackageOpts{}, srcs) if _, _, e := BuildToolchain.gc(b, &Action{Mode: "swigDoIntSize", Package: p, Objdir: objdir}, "", nil, nil, "", false, "", srcs); e != nil { return "32", nil @@ -3402,6 +3495,10 @@ func (b *Builder) swigIntSize(objdir string) (intsize string, err error) { // Run SWIG on one SWIG input file. func (b *Builder) swigOne(a *Action, file, objdir string, pcCFLAGS []string, cxx bool, intgosize string) error { + if strings.HasPrefix(file, "cgo") { + return errors.New("SWIG file must not use prefix 'cgo'") + } + p := a.Package sh := b.Shell(a) @@ -3588,7 +3685,7 @@ func useResponseFile(path string, argLen int) bool { // TODO: Note that other toolchains like CC are missing here for now. prog := strings.TrimSuffix(filepath.Base(path), ".exe") switch prog { - case "compile", "link", "cgo", "asm", "cover": + case "compile", "link", "cgo", "asm", "cover", "pack": default: return false } @@ -3607,24 +3704,35 @@ func useResponseFile(path string, argLen int) bool { return false } -// encodeArg encodes an argument for response file writing. +// encodeArg encodes an argument for response file writing using GCC-compatible format. +// Arguments containing special characters are wrapped in double quotes with escapes. func encodeArg(arg string) string { - // If there aren't any characters we need to reencode, fastpath out. - if !strings.ContainsAny(arg, "\\\n") { + // Empty string must be quoted to preserve it. + if arg == "" { + return `""` + } + // If no special characters, return as-is. + if !strings.ContainsAny(arg, " \t\n\r'\"\\$`") { return arg } + + // Use double quotes and escape special chars. var b strings.Builder + b.WriteByte('"') for _, r := range arg { switch r { case '\\': - b.WriteByte('\\') - b.WriteByte('\\') - case '\n': - b.WriteByte('\\') - b.WriteByte('n') + b.WriteString(`\\`) + case '"': + b.WriteString(`\"`) + case '$': + b.WriteString(`\$`) + case '`': + b.WriteString("\\`") default: b.WriteRune(r) } } + b.WriteByte('"') return b.String() } diff --git a/src/cmd/go/internal/work/exec_test.go b/src/cmd/go/internal/work/exec_test.go index 8bbf25bb337e8b..e7b550884c6e60 100644 --- a/src/cmd/go/internal/work/exec_test.go +++ b/src/cmd/go/internal/work/exec_test.go @@ -20,12 +20,18 @@ func TestEncodeArgs(t *testing.T) { tests := []struct { arg, want string }{ - {"", ""}, + {"", `""`}, {"hello", "hello"}, - {"hello\n", "hello\\n"}, - {"hello\\", "hello\\\\"}, - {"hello\nthere", "hello\\nthere"}, - {"\\\n", "\\\\\\n"}, + {"hello\n", "\"hello\n\""}, + {"hello\\", `"hello\\"`}, + {"hello\nthere", "\"hello\nthere\""}, + {"\\\n", "\"\\\\\n\""}, + {"hello world", `"hello world"`}, + {"hello\tthere", "\"hello\tthere\""}, + {`hello"there`, `"hello\"there"`}, + {"hello$there", `"hello\$there"`}, + {"hello`there", "\"hello\\`there\""}, + {"simple", "simple"}, } for _, test := range tests { if got := encodeArg(test.arg); got != test.want { @@ -43,10 +49,15 @@ func TestEncodeDecode(t *testing.T) { "hello\nthere", "hello 中国", "hello \n中\\国", + "hello$world", + "hello`world", + `hello"world`, } for _, arg := range tests { - if got := objabi.DecodeArg(encodeArg(arg)); got != arg { - t.Errorf("objabi.DecodeArg(encodeArg(%q)) = %q", arg, got) + encoded := encodeArg(arg) + args := objabi.ParseArgs([]byte(encoded)) + if len(args) != 1 || args[0] != arg { + t.Errorf("ParseArgs(encodeArg(%q)) = %q (encoded: %q)", arg, args, encoded) } } } @@ -80,8 +91,10 @@ func TestEncodeDecodeFuzz(t *testing.T) { } arg := buf.String() - if got := objabi.DecodeArg(encodeArg(arg)); got != arg { - t.Errorf("[%d] objabi.DecodeArg(encodeArg(%q)) = %q [seed: %v]", i, arg, got, seed) + encoded := encodeArg(arg) + args := objabi.ParseArgs([]byte(encoded)) + if len(args) != 1 || args[0] != arg { + t.Errorf("[%d] ParseArgs(encodeArg(%q)) = %q [seed: %v]", i, arg, args, seed) } } } diff --git a/src/cmd/go/internal/work/gc.go b/src/cmd/go/internal/work/gc.go index 71c36e80cbaaab..49b26e15609bb8 100644 --- a/src/cmd/go/internal/work/gc.go +++ b/src/cmd/go/internal/work/gc.go @@ -10,11 +10,11 @@ import ( "internal/buildcfg" "internal/platform" "io" - "log" "os" "path/filepath" "runtime" "strings" + "sync" "cmd/go/internal/base" "cmd/go/internal/cfg" @@ -127,7 +127,9 @@ func (gcToolchain) gc(b *Builder, a *Action, archive string, importcfg, embedcfg gcflags = append(gcflags, fuzzInstrumentFlags()...) } // Add -c=N to use concurrent backend compilation, if possible. - if c := gcBackendConcurrency(gcflags); c > 1 { + c, release := compilerConcurrency() + defer release() + if c > 1 { defaultGcFlags = append(defaultGcFlags, fmt.Sprintf("-c=%d", c)) } @@ -177,31 +179,9 @@ func (gcToolchain) gc(b *Builder, a *Action, archive string, importcfg, embedcfg return ofile, output, err } -// gcBackendConcurrency returns the backend compiler concurrency level for a package compilation. -func gcBackendConcurrency(gcflags []string) int { - // First, check whether we can use -c at all for this compilation. - canDashC := concurrentGCBackendCompilationEnabledByDefault - - switch e := os.Getenv("GO19CONCURRENTCOMPILATION"); e { - case "0": - canDashC = false - case "1": - canDashC = true - case "": - // Not set. Use default. - default: - log.Fatalf("GO19CONCURRENTCOMPILATION must be 0, 1, or unset, got %q", e) - } - - // TODO: Test and delete these conditions. - if cfg.ExperimentErr != nil || cfg.Experiment.FieldTrack || cfg.Experiment.PreemptibleLoops { - canDashC = false - } - - if !canDashC { - return 1 - } - +// compilerConcurrency returns the compiler concurrency level for a package compilation. +// The returned function must be called after the compile finishes. +func compilerConcurrency() (int, func()) { // Decide how many concurrent backend compilations to allow. // // If we allow too many, in theory we might end up with p concurrent processes, @@ -212,29 +192,66 @@ func gcBackendConcurrency(gcflags []string) int { // of the overall compiler execution, so c==1 for much of the build. // So don't worry too much about that interaction for now. // - // However, in practice, setting c above 4 tends not to help very much. - // See the analysis in CL 41192. + // But to keep things reasonable, we maintain a cap on the total number of + // concurrent backend compiles. (If we gave each compile action the full GOMAXPROCS, we could + // potentially have GOMAXPROCS^2 running compile goroutines) In the past, we'd limit + // the number of concurrent backend compiles per process to 4, which would result in a worst-case number + // of backend compiles of 4*cfg.BuildP. Because some compile processes benefit from having + // a larger number of compiles, especially when the compile action is the only + // action running, we'll allow the max value to be larger, but ensure that the + // total number of backend compiles never exceeds that previous worst-case number. + // This is implemented using a pool of tokens that are given out. We'll set aside enough + // tokens to make sure we don't run out, and then give half of the remaining tokens (up to + // GOMAXPROCS) to each compile action that requests it. // - // TODO(josharian): attempt to detect whether this particular compilation - // is likely to be a bottleneck, e.g. when: - // - it has no successor packages to compile (usually package main) - // - all paths through the build graph pass through it - // - critical path scheduling says it is high priority - // and in such a case, set c to runtime.GOMAXPROCS(0). - // By default this is the same as runtime.NumCPU. - // We do this now when p==1. - // To limit parallelism, set GOMAXPROCS below numCPU; this may be useful + // As a user, to limit parallelism, set GOMAXPROCS below numCPU; this may be useful // on a low-memory builder, or if a deterministic build order is required. - c := runtime.GOMAXPROCS(0) if cfg.BuildP == 1 { // No process parallelism, do not cap compiler parallelism. - return c - } - // Some process parallelism. Set c to min(4, maxprocs). - if c > 4 { - c = 4 + return maxCompilerConcurrency, func() {} + } + + // Cap compiler parallelism using the pool. + tokensMu.Lock() + defer tokensMu.Unlock() + concurrentProcesses++ + // Set aside tokens so that we don't run out if we were running cfg.BuildP concurrent compiles. + // We'll set aside one token for each of the action goroutines that aren't currently running a compile. + setAside := (cfg.BuildP - concurrentProcesses) * minTokens + availableTokens := tokens - setAside + // Grab half the remaining tokens: but with a floor of at least minTokens token, and + // a ceiling of the max backend concurrency. + c := max(min(availableTokens/2, maxCompilerConcurrency), minTokens) + tokens -= c + // Successfully grabbed the tokens. + return c, func() { + tokensMu.Lock() + defer tokensMu.Unlock() + concurrentProcesses-- + tokens += c } - return c +} + +var maxCompilerConcurrency = runtime.GOMAXPROCS(0) // max value we will use for -c + +var ( + tokensMu sync.Mutex + totalTokens int // total number of tokens: this is used for checking that we get them all back in the end + tokens int // number of available tokens + concurrentProcesses int // number of currently running compiles + minTokens int // minimum number of tokens to give out +) + +// initCompilerConcurrencyPool sets the number of tokens in the pool. It needs +// to be run after init, so that it can use the value of cfg.BuildP. +func initCompilerConcurrencyPool() { + // Size the pool to allow 2*maxCompilerConcurrency extra tokens to + // be distributed amongst the compile actions in addition to the minimum + // of min(4,GOMAXPROCS) tokens for each of the potentially cfg.BuildP + // concurrently running compile actions. + minTokens = min(4, maxCompilerConcurrency) + tokens = 2*maxCompilerConcurrency + minTokens*cfg.BuildP + totalTokens = tokens } // trimpath returns the -trimpath argument to use @@ -321,6 +338,10 @@ func asmArgs(a *Action, p *load.Package) []any { } } + if p.Standard { + args = append(args, "-std") + } + if cfg.Goarch == "386" { // Define GO386_value from cfg.GO386. args = append(args, "-D", "GO386_"+cfg.GO386) diff --git a/src/cmd/go/internal/work/init.go b/src/cmd/go/internal/work/init.go index a2954ab91ab60a..9226dd3fd631f0 100644 --- a/src/cmd/go/internal/work/init.go +++ b/src/cmd/go/internal/work/init.go @@ -50,16 +50,17 @@ func makeCfgChangedEnv() []string { return slices.Clip(env) } -func BuildInit(loaderstate *modload.State) { +func BuildInit(ld *modload.Loader) { if buildInitStarted { base.Fatalf("go: internal error: work.BuildInit called more than once") } buildInitStarted = true base.AtExit(closeBuilders) - modload.Init(loaderstate) + modload.Init(ld) instrumentInit() buildModeInit() + initCompilerConcurrencyPool() cfgChangedEnv = makeCfgChangedEnv() if err := fsys.Init(); err != nil { diff --git a/src/cmd/go/internal/work/security.go b/src/cmd/go/internal/work/security.go index 3b3eba536cb146..fd54b5c2c021c3 100644 --- a/src/cmd/go/internal/work/security.go +++ b/src/cmd/go/internal/work/security.go @@ -100,7 +100,6 @@ var validCompilerFlags = []*lazyregexp.Regexp{ re(`-m(abi|arch|cpu|fpu|simd|tls-dialect|tune)=([^@\-].*)`), re(`-m(no-)?v?aes`), re(`-marm`), - re(`-m(no-)?avx[0-9a-z]*`), re(`-mcmodel=[0-9a-z-]+`), re(`-mfloat-abi=([^@\-].*)`), re(`-m(soft|single|double)-float`), @@ -130,6 +129,7 @@ var validCompilerFlags = []*lazyregexp.Regexp{ re(`-pedantic(-errors)?`), re(`-pipe`), re(`-pthread`), + re(`--static`), re(`-?-std=([^@\-].*)`), re(`-?-stdlib=([^@\-].*)`), re(`--sysroot=([^@\-].*)`), @@ -253,6 +253,58 @@ var validLinkerFlagsWithNextArg = []string{ "-Wl,-undefined", } +var validPkgConfigFlags = []*lazyregexp.Regexp{ + re(`--atleast-pkgconfig-version=\d+\.\d+\.\d+`), + re(`--atleast-version=\d+\.\d+\.\d+`), + re(`--cflags-only-I`), + re(`--cflags`), + re(`--define-prefix`), + re(`--define-variable=[A-Za-z_][A-Za-z0-9_]*=[^@\-]*`), + re(`--digraph`), + re(`--dont-define-prefix`), + re(`--dont-relocate-paths`), + re(`--dump-personality`), + re(`--env-only`), + re(`--errors-to-stdout`), + re(`--exact-version=\d+\.\d+\.\d+`), + re(`--exists`), + re(`--fragment-filter=[A-Za-z_][a-zA-Z0-9_]*`), + re(`--ignore-conflicts`), + re(`--internal-cflags`), + re(`--keep-system-cflags`), + re(`--keep-system-libs`), + re(`--libs-only-l`), + re(`--libs-only-L`), + re(`--libs`), + re(`--list-all`), + re(`--list-package-names`), + re(`--max-version=\d+\.\d+\.\d+`), + re(`--maximum-traverse-depth=[0-9]+`), + re(`--modversion`), + re(`--msvc-syntax`), + re(`--no-cache`), + re(`--no-provides`), + re(`--no-uninstalled`), + re(`--path`), + re(`--personality=(triplet|filename)`), + re(`--prefix-variable=[A-Za-z_][a-zA-Z0-9_]*`), + re(`--print-errors`), + re(`--print-provides`), + re(`--print-requires-private`), + re(`--print-requires`), + re(`--print-variables`), + re(`--pure`), + re(`--shared`), + re(`--short-errors`), + re(`--silence-errors`), + re(`--simulate`), + re(`--static`), + re(`--uninstalled`), + re(`--validate`), + re(`--variable=[A-Za-z_][a-zA-Z0-9_]*`), + re(`--with-path=[^@\-].*`), +} + func checkCompilerFlags(name, source string, list []string) error { checkOverrides := true return checkFlags(name, source, list, nil, validCompilerFlags, validCompilerFlagsWithNextArg, checkOverrides) @@ -263,6 +315,11 @@ func checkLinkerFlags(name, source string, list []string) error { return checkFlags(name, source, list, invalidLinkerFlags, validLinkerFlags, validLinkerFlagsWithNextArg, checkOverrides) } +func checkPkgConfigFlags(name, source string, list []string) error { + checkOverrides := false + return checkFlags(name, source, list, nil, validPkgConfigFlags, nil, checkOverrides) +} + // checkCompilerFlagsForInternalLink returns an error if 'list' // contains a flag or flags that may not be fully supported by // internal linking (meaning that we should punt the link to the @@ -274,10 +331,34 @@ func checkCompilerFlagsForInternalLink(name, source string, list []string) error } // Currently the only flag on the allow list that causes problems // for the linker is "-flto"; check for it manually here. + // Also check for -static/--static, which some toolchains accept + // as a compiler flag. for _, fl := range list { if strings.HasPrefix(fl, "-flto") { return fmt.Errorf("flag %q triggers external linking", fl) } + if fl == "-static" || fl == "--static" { + return fmt.Errorf("flag %q triggers external linking", fl) + } + } + return nil +} + +// checkLinkerFlagsForInternalLink returns an error if 'list' +// contains linker flags that are not compatible with internal linking. +func checkLinkerFlagsForInternalLink(name, source string, list []string) error { + checkOverrides := false + if err := checkFlags(name, source, list, nil, validLinkerFlags, validLinkerFlagsWithNextArg, checkOverrides); err != nil { + return err + } + // Flags that force static linking require the external linker + // to resolve libc symbols. See #77768. + for _, fl := range list { + if fl == "-static" || fl == "--static" || + fl == "-Wl,-static" || fl == "-Wl,--static" || + fl == "-Wl,-Bstatic" { + return fmt.Errorf("flag %q triggers external linking", fl) + } } return nil } @@ -375,13 +456,13 @@ Args: } if i+1 < len(list) { - return fmt.Errorf("invalid flag in %s: %s %s (see https://golang.org/s/invalidflag)", source, arg, list[i+1]) + return fmt.Errorf("invalid flag in %s: %s %s (see https://go.dev/s/invalidflag)", source, arg, list[i+1]) } - return fmt.Errorf("invalid flag in %s: %s without argument (see https://golang.org/s/invalidflag)", source, arg) + return fmt.Errorf("invalid flag in %s: %s without argument (see https://go.dev/s/invalidflag)", source, arg) } } Bad: - return fmt.Errorf("invalid flag in %s: %s", source, arg) + return fmt.Errorf("invalid flag in %s: %s (see https://go.dev/s/invalidflag)", source, arg) } return nil } diff --git a/src/cmd/go/internal/work/shell.go b/src/cmd/go/internal/work/shell.go index ceff84d81f831f..ffb8f27271d463 100644 --- a/src/cmd/go/internal/work/shell.go +++ b/src/cmd/go/internal/work/shell.go @@ -15,7 +15,6 @@ import ( "cmd/internal/pathcache" "errors" "fmt" - "internal/lazyregexp" "io" "io/fs" "os" @@ -511,15 +510,6 @@ func (sh *Shell) reportCmd(desc, dir string, cmdOut []byte, cmdErr error) error dir = dirP } - // Fix up output referring to cgo-generated code to be more readable. - // Replace x.go:19[/tmp/.../x.cgo1.go:18] with x.go:19. - // Replace *[100]_Ctype_foo with *[100]C.foo. - // If we're using -x, assume we're debugging and want the full dump, so disable the rewrite. - if !cfg.BuildX && cgoLine.MatchString(out) { - out = cgoLine.ReplaceAllString(out, "") - out = cgoTypeSigRe.ReplaceAllString(out, "C.") - } - // Usually desc is already p.Desc(), but if not, signal cmdError.Error to // add a line explicitly mentioning the import path. needsPath := importPath != "" && p != nil && desc != p.Desc() @@ -580,9 +570,6 @@ func (e *cmdError) ImportPath() string { return e.importPath } -var cgoLine = lazyregexp.New(`\[[^\[\]]+\.(cgo1|cover)\.go:[0-9]+(:[0-9]+)?\]`) -var cgoTypeSigRe = lazyregexp.New(`\b_C2?(type|func|var|macro)_\B`) - // run runs the command given by cmdline in the directory dir. // If the command fails, run prints information about the failure // and returns a non-nil error. diff --git a/src/cmd/go/internal/workcmd/edit.go b/src/cmd/go/internal/workcmd/edit.go index 2b9f658f861c85..cde6dcdf94d152 100644 --- a/src/cmd/go/internal/workcmd/edit.go +++ b/src/cmd/go/internal/workcmd/edit.go @@ -35,7 +35,7 @@ The editing flags specify a sequence of editing operations. The -fmt flag reformats the go.work file without making other changes. This reformatting is also implied by any other modifications that use or -rewrite the go.mod file. The only time this flag is needed is if no other +rewrite the go.work file. The only time this flag is needed is if no other flags are specified, as in 'go work edit -fmt'. The -godebug=key=value flag adds a godebug key=value line, @@ -63,14 +63,18 @@ The -use, -dropuse, -replace, and -dropreplace, editing flags may be repeated, and the changes are applied in the order given. The -go=version flag sets the expected Go language version. +It takes a version like "1.26" or "1.26.2". +Using "none" as the version removes the go directive. The -toolchain=name flag sets the Go toolchain to use. +It takes a toolchain name like "go1.26" or "go1.26.2". +Using "none" as the name removes the toolchain directive. The -print flag prints the final go.work in its text format instead of -writing it back to go.mod. +writing it back to go.work. The -json flag prints the final go.work file in JSON format instead of -writing it back to go.mod. The JSON output corresponds to these Go types: +writing it back to go.work. The JSON output corresponds to these Go types: type GoWork struct { Go string @@ -132,7 +136,7 @@ func init() { } func runEditwork(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() + moduleLoader := modload.NewLoader() if *editJSON && *editPrint { base.Fatalf("go: cannot use both -json and -print") } @@ -144,8 +148,8 @@ func runEditwork(ctx context.Context, cmd *base.Command, args []string) { if len(args) == 1 { gowork = args[0] } else { - modload.InitWorkfile(moduleLoaderState) - gowork = modload.WorkFilePath(moduleLoaderState) + moduleLoader.InitWorkfile() + gowork = modload.WorkFilePath(moduleLoader) } if gowork == "" { base.Fatalf("go: no go.work file found\n\t(run 'go work init' first or specify path using GOWORK environment variable)") @@ -262,7 +266,7 @@ func flagEditworkUse(arg string) { func flagEditworkDropUse(arg string) { workedits = append(workedits, func(f *modfile.WorkFile) { if err := f.DropUse(modload.ToDirectoryPath(arg)); err != nil { - base.Fatalf("go: -dropdirectory=%s: %v", arg, err) + base.Fatalf("go: -dropuse=%s: %v", arg, err) } }) } @@ -279,7 +283,10 @@ func allowedVersionArg(arg string) bool { // parsePathVersionOptional parses path[@version], using adj to // describe any errors. func parsePathVersionOptional(adj, arg string, allowDirPath bool) (path, version string, err error) { - before, after, found := strings.Cut(arg, "@") + before, after, found, err := modload.ParsePathVersion(arg) + if err != nil { + return "", "", err + } if !found { path = arg } else { @@ -338,21 +345,21 @@ func flagEditworkDropReplace(arg string) { }) } -type replaceJSON struct { - Old module.Version - New module.Version -} - // editPrintJSON prints the -json output. func editPrintJSON(workFile *modfile.WorkFile) { var f workfileJSON if workFile.Go != nil { f.Go = workFile.Go.Version } + if workFile.Toolchain != nil { + f.Toolchain = workFile.Toolchain.Name + } + for _, d := range workFile.Godebug { + f.Godebug = append(f.Godebug, godebugJSON{Key: d.Key, Value: d.Value}) + } for _, d := range workFile.Use { f.Use = append(f.Use, useJSON{DiskPath: d.Path, ModPath: d.ModulePath}) } - for _, r := range workFile.Replace { f.Replace = append(f.Replace, replaceJSON{r.Old, r.New}) } @@ -366,12 +373,24 @@ func editPrintJSON(workFile *modfile.WorkFile) { // workfileJSON is the -json output data structure. type workfileJSON struct { - Go string `json:",omitempty"` - Use []useJSON - Replace []replaceJSON + Go string `json:",omitempty"` + Toolchain string `json:",omitempty"` + Godebug []godebugJSON `json:",omitempty"` + Use []useJSON `json:",omitempty"` + Replace []replaceJSON `json:",omitempty"` +} + +type godebugJSON struct { + Key string + Value string } type useJSON struct { DiskPath string ModPath string `json:",omitempty"` } + +type replaceJSON struct { + Old module.Version + New module.Version +} diff --git a/src/cmd/go/internal/workcmd/init.go b/src/cmd/go/internal/workcmd/init.go index 0a6db1133fd3ae..c264c3b4beff18 100644 --- a/src/cmd/go/internal/workcmd/init.go +++ b/src/cmd/go/internal/workcmd/init.go @@ -44,12 +44,12 @@ func init() { } func runInit(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() - moduleLoaderState.ForceUseModules = true + moduleLoader.ForceUseModules = true - gowork := modload.WorkFilePath(moduleLoaderState) + gowork := modload.WorkFilePath(moduleLoader) if gowork == "" { gowork = filepath.Join(base.Cwd(), "go.work") } @@ -62,6 +62,6 @@ func runInit(ctx context.Context, cmd *base.Command, args []string) { wf := new(modfile.WorkFile) wf.Syntax = new(modfile.FileSyntax) wf.AddGoStmt(goV) - workUse(moduleLoaderState, ctx, gowork, wf, args) + workUse(ctx, moduleLoader, gowork, wf, args) modload.WriteWorkFile(gowork, wf) } diff --git a/src/cmd/go/internal/workcmd/sync.go b/src/cmd/go/internal/workcmd/sync.go index ae4fd9c5f34ce1..6d0e4cb3160dcf 100644 --- a/src/cmd/go/internal/workcmd/sync.go +++ b/src/cmd/go/internal/workcmd/sync.go @@ -48,20 +48,20 @@ func init() { } func runSync(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - moduleLoaderState.ForceUseModules = true - modload.InitWorkfile(moduleLoaderState) - if modload.WorkFilePath(moduleLoaderState) == "" { + moduleLoader := modload.NewLoader() + moduleLoader.ForceUseModules = true + moduleLoader.InitWorkfile() + if modload.WorkFilePath(moduleLoader) == "" { base.Fatalf("go: no go.work file found\n\t(run 'go work init' first or specify path using GOWORK environment variable)") } - _, err := modload.LoadModGraph(moduleLoaderState, ctx, "") + _, err := modload.LoadModGraph(moduleLoader, ctx, "") if err != nil { - toolchain.SwitchOrFatal(moduleLoaderState, ctx, err) + toolchain.SwitchOrFatal(moduleLoader, ctx, err) } - mustSelectFor := map[module.Version][]module.Version{} + addFor := map[module.Version][]module.Version{} - mms := moduleLoaderState.MainModules + mms := moduleLoader.MainModules opts := modload.PackageOpts{ Tags: imports.AnyTags(), @@ -74,26 +74,27 @@ func runSync(ctx context.Context, cmd *base.Command, args []string) { } for _, m := range mms.Versions() { opts.MainModule = m - _, pkgs := modload.LoadPackages(moduleLoaderState, ctx, opts, "all") + _, pkgs := modload.LoadPackages(moduleLoader, ctx, opts, "all") opts.MainModule = module.Version{} // reset var ( - mustSelect []module.Version - inMustSelect = map[module.Version]bool{} + addReq []module.Version + inAddReq = map[module.Version]bool{} ) for _, pkg := range pkgs { - if r := modload.PackageModule(pkg); r.Version != "" && !inMustSelect[r] { + if r := moduleLoader.PackageModule(pkg); r.Version != "" && !inAddReq[r] { // r has a known version, so force that version. - mustSelect = append(mustSelect, r) - inMustSelect[r] = true + addReq = append(addReq, r) + inAddReq[r] = true } } - gover.ModSort(mustSelect) // ensure determinism - mustSelectFor[m] = mustSelect + gover.ModSort(addReq) // ensure determinism + addFor[m] = addReq } - workFilePath := modload.WorkFilePath(moduleLoaderState) // save go.work path because EnterModule clobbers it. + workFilePath := modload.WorkFilePath(moduleLoader) + var loaders []*modload.Loader var goV string for _, m := range mms.Versions() { if mms.ModRoot(m) == "" && m.Path == "command-line-arguments" { @@ -103,9 +104,9 @@ func runSync(ctx context.Context, cmd *base.Command, args []string) { continue } - // Use EnterModule to reset the global state in modload to be in - // single-module mode using the modroot of m. - modload.EnterModule(moduleLoaderState, ctx, mms.ModRoot(m)) + // Use EnterModule to make a loader with a single work module. + loader := modload.NewLoader() + modload.EnterModule(loader, ctx, mms.ModRoot(m)) // Edit the build list in the same way that 'go get' would if we // requested the relevant module versions explicitly. @@ -115,12 +116,12 @@ func runSync(ctx context.Context, cmd *base.Command, args []string) { // so we don't write some go.mods with the "before" toolchain // and others with the "after" toolchain. If nothing else, that // discrepancy could show up in auto-recorded toolchain lines. - changed, err := modload.EditBuildList(moduleLoaderState, ctx, nil, mustSelectFor[m]) + changed, err := modload.EditBuildList(loader, ctx, addFor[m], nil) if err != nil { - continue + base.Fatal(err) } if changed { - modload.LoadPackages(moduleLoaderState, ctx, modload.PackageOpts{ + modload.LoadPackages(loader, ctx, modload.PackageOpts{ Tags: imports.AnyTags(), Tidy: true, VendorModulesInGOROOTSrc: true, @@ -130,9 +131,17 @@ func runSync(ctx context.Context, cmd *base.Command, args []string) { SilenceMissingStdImports: true, SilencePackageErrors: true, }, "all") - modload.WriteGoMod(moduleLoaderState, ctx, modload.WriteOpts{}) + // Run UpdateGoModFromReqs before we run WriteGoMod so we can catch errors in it early. + if _, _, _, err := modload.UpdateGoModFromReqs(loader, ctx, modload.WriteOpts{}); err != nil { + base.Fatal(err) + } + loaders = append(loaders, loader) } - goV = gover.Max(goV, moduleLoaderState.MainModules.GoVersion(moduleLoaderState)) + goV = gover.Max(goV, loader.MainModules.GoVersion(loader)) + } + base.ExitIfErrors() + for _, loader := range loaders { + modload.WriteGoMod(loader, ctx, modload.WriteOpts{}) } wf, err := modload.ReadWorkFile(workFilePath) diff --git a/src/cmd/go/internal/workcmd/use.go b/src/cmd/go/internal/workcmd/use.go index 425be01f774193..1d833b37ec61f0 100644 --- a/src/cmd/go/internal/workcmd/use.go +++ b/src/cmd/go/internal/workcmd/use.go @@ -42,9 +42,12 @@ thing that go work use does. The -r flag searches recursively for modules in the argument directories, and the use command operates as if each of the directories -were specified as arguments. - +were specified as arguments. When -r is used, symlinks to directories +within the argument tree are ignored. +The go command matches use paths to module directories without resolving +symbolic links. A use directive that names a symlink to a directory is +not interchangeable with one that names the symlink's target. See the workspaces reference at https://go.dev/ref/mod#workspaces for more information. @@ -61,10 +64,10 @@ func init() { } func runUse(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - moduleLoaderState.ForceUseModules = true - modload.InitWorkfile(moduleLoaderState) - gowork := modload.WorkFilePath(moduleLoaderState) + moduleLoader := modload.NewLoader() + moduleLoader.ForceUseModules = true + moduleLoader.InitWorkfile() + gowork := modload.WorkFilePath(moduleLoader) if gowork == "" { base.Fatalf("go: no go.work file found\n\t(run 'go work init' first or specify path using GOWORK environment variable)") } @@ -72,11 +75,11 @@ func runUse(ctx context.Context, cmd *base.Command, args []string) { if err != nil { base.Fatal(err) } - workUse(moduleLoaderState, ctx, gowork, wf, args) + workUse(ctx, moduleLoader, gowork, wf, args) modload.WriteWorkFile(gowork, wf) } -func workUse(loaderstate *modload.State, ctx context.Context, gowork string, wf *modfile.WorkFile, args []string) { +func workUse(ctx context.Context, s *modload.Loader, gowork string, wf *modfile.WorkFile, args []string) { workDir := filepath.Dir(gowork) // absolute, since gowork itself is absolute haveDirs := make(map[string][]string) // absolute → original(s) @@ -95,7 +98,7 @@ func workUse(loaderstate *modload.State, ctx context.Context, gowork string, wf // all entries for the absolute path should be removed. keepDirs := make(map[string]string) - sw := toolchain.NewSwitcher(loaderstate) + sw := toolchain.NewSwitcher(s) // lookDir updates the entry in keepDirs for the directory dir, // which is either absolute or relative to the current working directory @@ -163,6 +166,9 @@ func workUse(loaderstate *modload.State, ctx context.Context, gowork string, wf } return nil } + if d.Name() == "vendor" { + return filepath.SkipDir + } lookDir(path) return nil }) diff --git a/src/cmd/go/internal/workcmd/vendor.go b/src/cmd/go/internal/workcmd/vendor.go index 8852d965fa3b94..fdc7ea312b4131 100644 --- a/src/cmd/go/internal/workcmd/vendor.go +++ b/src/cmd/go/internal/workcmd/vendor.go @@ -46,11 +46,11 @@ func init() { } func runVendor(ctx context.Context, cmd *base.Command, args []string) { - moduleLoaderState := modload.NewState() - modload.InitWorkfile(moduleLoaderState) - if modload.WorkFilePath(moduleLoaderState) == "" { + moduleLoader := modload.NewLoader() + moduleLoader.InitWorkfile() + if modload.WorkFilePath(moduleLoader) == "" { base.Fatalf("go: no go.work file found\n\t(run 'go work init' first or specify path using GOWORK environment variable)") } - modcmd.RunVendor(moduleLoaderState, ctx, vendorE, vendorO, args) + modcmd.RunVendor(moduleLoader, ctx, vendorE, vendorO, args) } diff --git a/src/cmd/go/internal/workcmd/work.go b/src/cmd/go/internal/workcmd/work.go index bfbed83e889cb1..1e4b299bc3f142 100644 --- a/src/cmd/go/internal/workcmd/work.go +++ b/src/cmd/go/internal/workcmd/work.go @@ -52,7 +52,9 @@ like in Go imports. The use directive specifies a module to be included in the workspace's set of main modules. The argument to the use directive is the directory -containing the module's go.mod file. +containing the module's go.mod file. The go command does not resolve +symbolic links when matching use paths to module directories, so a +symlink to a directory is not interchangeable with its target. The go directive specifies the version of Go the file was written at. It is possible there may be future changes in the semantics of workspaces diff --git a/src/cmd/go/main.go b/src/cmd/go/main.go index 8cdfd9196e4cb1..bba11a2fdeaaa6 100644 --- a/src/cmd/go/main.go +++ b/src/cmd/go/main.go @@ -61,13 +61,13 @@ func init() { work.CmdInstall, list.CmdList, modcmd.CmdMod, - workcmd.CmdWork, run.CmdRun, telemetrycmd.CmdTelemetry, test.CmdTest, tool.CmdTool, version.CmdVersion, vet.CmdVet, + workcmd.CmdWork, help.HelpBuildConstraint, help.HelpBuildJSON, diff --git a/src/cmd/go/proxy_test.go b/src/cmd/go/proxy_test.go index 5ff81361c9609a..2a8bacec186819 100644 --- a/src/cmd/go/proxy_test.go +++ b/src/cmd/go/proxy_test.go @@ -172,6 +172,23 @@ func proxyHandler(w http.ResponseWriter, r *http.Request) { return } + // Request for $GOPROXY/sumdb-redirect/module@version:/lookup/... + // performs a lookup for module@version rather than the requested module. + if strings.HasPrefix(path, "sumdb-redirect/") { + redirect, rest, ok := strings.Cut(path[len("sumdb-redirect"):], ":") + if !ok { + w.WriteHeader(500) + return + } + if strings.HasPrefix(rest, "/lookup/") { + r.URL.Path = "/lookup" + redirect + } else { + r.URL.Path = rest + } + sumdbServer.ServeHTTP(w, r) + return + } + // Request for $GOPROXY/redirect//... goes to redirects. if strings.HasPrefix(path, "redirect/") { path = path[len("redirect/"):] diff --git a/src/cmd/go/script_test.go b/src/cmd/go/script_test.go index 390a36723787f4..6033ec420b8452 100644 --- a/src/cmd/go/script_test.go +++ b/src/cmd/go/script_test.go @@ -38,6 +38,8 @@ var testSum = flag.String("testsum", "", `may be tidy, listm, or listall. If set // TestScript runs the tests in testdata/script/*.txt. func TestScript(t *testing.T) { + t.Parallel() + testenv.MustHaveGoBuild(t) testenv.SkipIfShortAndSlow(t) @@ -99,6 +101,7 @@ func TestScript(t *testing.T) { } t.Run("README", func(t *testing.T) { + t.Parallel() checkScriptReadme(t, engine, env) }) @@ -107,7 +110,6 @@ func TestScript(t *testing.T) { t.Fatal(err) } for _, file := range files { - file := file name := strings.TrimSuffix(filepath.Base(file), ".txt") t.Run(name, func(t *testing.T) { t.Parallel() @@ -245,6 +247,7 @@ func scriptEnv(srv *vcstest.Server, srvCertFile string) ([]string, error) { "TESTGO_VCSTEST_CERT=" + srvCertFile, "TESTGONETWORK=panic", // cleared by the [net] condition "GOSUMDB=" + testSumDBVerifierKey, + "TESTGO_SUMDB=" + testSumDBName, "GONOPROXY=", "GONOSUMDB=", "GOVCS=*:all", diff --git a/src/cmd/go/scriptconds_test.go b/src/cmd/go/scriptconds_test.go index af9691ad2a4aca..25053dd1da562b 100644 --- a/src/cmd/go/scriptconds_test.go +++ b/src/cmd/go/scriptconds_test.go @@ -10,14 +10,16 @@ import ( "cmd/internal/script/scripttest" "errors" "fmt" - "internal/testenv" + "internal/buildcfg" "os" "os/exec" "path/filepath" + "regexp" "runtime" "runtime/debug" - "sync" "testing" + + "golang.org/x/mod/semver" ) func scriptConditions(t *testing.T) map[string]script.Cond { @@ -37,12 +39,12 @@ func scriptConditions(t *testing.T) map[string]script.Cond { } add("abscc", script.Condition("default $CC path is absolute and exists", defaultCCIsAbsolute)) - add("bzr", lazyBool("the 'bzr' executable exists and provides the standard CLI", hasWorkingBzr)) add("case-sensitive", script.OnceCondition("$WORK filesystem is case-sensitive", isCaseSensitive)) add("cc", script.PrefixCondition("go env CC = (ignoring the go/env file)", ccIs)) add("git", lazyBool("the 'git' executable exists and provides the standard CLI", hasWorkingGit)) - add("net", script.PrefixCondition("can connect to external network host ", hasNet)) + add("git-sha256", script.OnceCondition("the local 'git' version is recent enough to support sha256 object/commit hashes", gitSupportsSHA256)) add("trimpath", script.OnceCondition("test binary was built with -trimpath", isTrimpath)) + add("default-cgo", lazyBool("when CGO_ENABLED=1|0 was set in make.bash", defaultCgo)) return conds } @@ -69,42 +71,6 @@ func ccIs(s *script.State, want string) (bool, error) { return cfg.DefaultCC(GOOS, GOARCH) == want, nil } -var scriptNetEnabled sync.Map // testing.TB → already enabled - -func hasNet(s *script.State, host string) (bool, error) { - if !testenv.HasExternalNetwork() { - return false, nil - } - - // TODO(bcmills): Add a flag or environment variable to allow skipping tests - // for specific hosts and/or skipping all net tests except for specific hosts. - - t, ok := tbFromContext(s.Context()) - if !ok { - return false, errors.New("script Context unexpectedly missing testing.TB key") - } - - if netTestSem != nil { - // When the number of external network connections is limited, we limit the - // number of net tests that can run concurrently so that the overall number - // of network connections won't exceed the limit. - _, dup := scriptNetEnabled.LoadOrStore(t, true) - if !dup { - // Acquire a net token for this test until the test completes. - netTestSem <- struct{}{} - t.Cleanup(func() { - <-netTestSem - scriptNetEnabled.Delete(t) - }) - } - } - - // Since we have confirmed that the network is available, - // allow cmd/go to use it. - s.Setenv("TESTGONETWORK", "") - return true, nil -} - func isCaseSensitive() (bool, error) { tmpdir, err := os.MkdirTemp(testTmpDir, "case-sensitive") if err != nil { @@ -153,13 +119,33 @@ func hasWorkingGit() bool { return err == nil } -func hasWorkingBzr() bool { - bzr, err := exec.LookPath("bzr") - if err != nil { - return false +// Capture the major, minor and (optionally) patch version, but ignore anything later +var gitVersLineExtract = regexp.MustCompile(`git version\s+(\d+\.\d+(?:\.\d+)?)`) + +func gitVersion() (string, error) { + gitOut, runErr := exec.Command("git", "version").CombinedOutput() + if runErr != nil { + return "v0", fmt.Errorf("failed to execute git version: %w", runErr) } - // Check that 'bzr help' exits with code 0. - // See go.dev/issue/71504 for an example where 'bzr' exists in PATH but doesn't work. - err = exec.Command(bzr, "help").Run() - return err == nil + matches := gitVersLineExtract.FindSubmatch(gitOut) + if len(matches) < 2 { + return "v0", fmt.Errorf("git version extraction regexp did not match version line: %q", gitOut) + } + return "v" + string(matches[1]), nil +} + +func hasAtLeastGitVersion(minVers string) (bool, error) { + gitVers, gitVersErr := gitVersion() + if gitVersErr != nil { + return false, gitVersErr + } + return semver.Compare(minVers, gitVers) <= 0, nil +} + +func gitSupportsSHA256() (bool, error) { + return hasAtLeastGitVersion("v2.29") +} + +func defaultCgo() bool { + return buildcfg.DefaultCGO_ENABLED == "1" || buildcfg.DefaultCGO_ENABLED == "0" } diff --git a/src/cmd/go/terminal_test.go b/src/cmd/go/terminal_test.go index a5ad9191c2a470..c49f119e0de3ee 100644 --- a/src/cmd/go/terminal_test.go +++ b/src/cmd/go/terminal_test.go @@ -16,6 +16,8 @@ import ( ) func TestTerminalPassthrough(t *testing.T) { + t.Parallel() + // Check that if 'go test' is run with a terminal connected to stdin/stdout, // then the go command passes that terminal down to the test binary // invocation (rather than, e.g., putting a pipe in the way). @@ -27,6 +29,7 @@ func TestTerminalPassthrough(t *testing.T) { // terminal, the test can correctly detect that. (cmd/go doesn't guarantee // that it won't add a terminal in the middle, but that would be pretty weird.) t.Run("pipe", func(t *testing.T) { + t.Parallel() r, w, err := os.Pipe() if err != nil { t.Fatalf("pipe failed: %s", err) @@ -44,6 +47,7 @@ func TestTerminalPassthrough(t *testing.T) { // Now test with a read PTY. t.Run("pty", func(t *testing.T) { + t.Parallel() r, processTTY, err := testpty.Open() if errors.Is(err, testpty.ErrNotSupported) { t.Skipf("%s", err) diff --git a/src/cmd/go/testdata/mod/example.com_importcrypto_v1.0.0.txt b/src/cmd/go/testdata/mod/example.com_importcrypto_v1.0.0.txt new file mode 100644 index 00000000000000..0ca0f35bf2ba83 --- /dev/null +++ b/src/cmd/go/testdata/mod/example.com_importcrypto_v1.0.0.txt @@ -0,0 +1,19 @@ +example.com/importcrypto contains a package that imports crypto/sha256 +It's used by the script test case mod_get_fips140_issue73649 + +-- .info -- +{"Version":"v1.0.0"} +-- .mod -- +module example.com/importcrypto + +go 1.27 +-- go.mod -- +module example.com/importcrypto + +go 1.27 +-- importcypto.go -- +package p + +import _ "crypto/sha256" + +func main() {} diff --git a/src/cmd/go/testdata/mod/example.com_increasegoreq_v0.0.1.txt b/src/cmd/go/testdata/mod/example.com_increasegoreq_v0.0.1.txt new file mode 100644 index 00000000000000..30948b759b1268 --- /dev/null +++ b/src/cmd/go/testdata/mod/example.com_increasegoreq_v0.0.1.txt @@ -0,0 +1,7 @@ +-- .info -- +{"Version": "v0.0.1"} +-- .mod -- +module example.com/increasegoreq +go 1.21 +-- increasegoreq.go -- +package increasegoreq diff --git a/src/cmd/go/testdata/mod/example.com_increasegoreq_v0.0.2.txt b/src/cmd/go/testdata/mod/example.com_increasegoreq_v0.0.2.txt new file mode 100644 index 00000000000000..f97a430b3c83d9 --- /dev/null +++ b/src/cmd/go/testdata/mod/example.com_increasegoreq_v0.0.2.txt @@ -0,0 +1,7 @@ +-- .info -- +{"Version": "v0.0.2"} +-- .mod -- +module example.com/increasegoreq +go 1.23 +-- increasegoreq.go -- +package increasegoreq diff --git a/src/cmd/go/testdata/mod/example.com_syncreplace_v1.0.0.txt b/src/cmd/go/testdata/mod/example.com_syncreplace_v1.0.0.txt new file mode 100644 index 00000000000000..3e7c53f64113bd --- /dev/null +++ b/src/cmd/go/testdata/mod/example.com_syncreplace_v1.0.0.txt @@ -0,0 +1,12 @@ +-- .mod -- +module example.com/syncreplace + +go 1.27 + +require rsc.io/quote v1.0.0 +-- syncreplace.go -- +package syncreplace + +import _ "rsc.io/quote" +-- .info -- +{"Version":"v1.0.0"} diff --git a/src/cmd/go/testdata/mod/example.com_syncreplace_v1.1.0.txt b/src/cmd/go/testdata/mod/example.com_syncreplace_v1.1.0.txt new file mode 100644 index 00000000000000..64601d73b1d376 --- /dev/null +++ b/src/cmd/go/testdata/mod/example.com_syncreplace_v1.1.0.txt @@ -0,0 +1,12 @@ +-- .mod -- +module example.com/syncreplace + +go 1.27 + +require rsc.io/quote v1.1.0 +-- syncreplace.go -- +package syncreplace + +import _ "rsc.io/quote" +-- .info -- +{"Version":"v1.1.0"} diff --git a/src/cmd/go/testdata/mod/github.com_go-logr_logr_v1.4.1.txt b/src/cmd/go/testdata/mod/github.com_go-logr_logr_v1.4.1.txt new file mode 100644 index 00000000000000..96550da6a50948 --- /dev/null +++ b/src/cmd/go/testdata/mod/github.com_go-logr_logr_v1.4.1.txt @@ -0,0 +1,16 @@ +module github.com/go-logr/logr@v1.4.1 + +Original import done via `go run addmod.go`. Dependencies have been manually +reduced to the minimum required by the test `get_tool_issue_74691`. +-- .mod -- +module github.com/go-logr/logr + +go 1.18 +-- .info -- +{"Version":"v1.4.1","Time":"2023-12-21T15:57:58Z","Origin":{"VCS":"git","URL":"https://github.com/go-logr/logr","Hash":"dcdc3f2cd12e8a5c4e2a6712d6958c90e2e5bd98","Ref":"refs/tags/v1.4.1"}} +-- go.mod -- +module github.com/go-logr/logr + +go 1.18 +-- logr.go -- +package logr diff --git a/src/cmd/go/testdata/mod/github.com_go-logr_logr_v1.4.3.txt b/src/cmd/go/testdata/mod/github.com_go-logr_logr_v1.4.3.txt new file mode 100644 index 00000000000000..c5cb4f90d1ac12 --- /dev/null +++ b/src/cmd/go/testdata/mod/github.com_go-logr_logr_v1.4.3.txt @@ -0,0 +1,16 @@ +module github.com/go-logr/logr@v1.4.3 + +Original import done via `go run addmod.go`. Dependencies have been manually +reduced to the minimum required by the test `get_tool_issue_74691`. +-- .mod -- +module github.com/go-logr/logr + +go 1.18 +-- .info -- +{"Version":"v1.4.3","Time":"2025-05-19T04:56:57Z","Origin":{"VCS":"git","URL":"https://github.com/go-logr/logr","Hash":"38a1c47ef633fa6b2eee6b8f2e1371ba8626e557","Ref":"refs/tags/v1.4.3"}} +-- go.mod -- +module github.com/go-logr/logr + +go 1.18 +-- logr.go -- +package logr diff --git a/src/cmd/go/testdata/mod/github.com_golangci_golangci-lint_v2_v2.10.1.txt b/src/cmd/go/testdata/mod/github.com_golangci_golangci-lint_v2_v2.10.1.txt new file mode 100644 index 00000000000000..cdef3835b97e69 --- /dev/null +++ b/src/cmd/go/testdata/mod/github.com_golangci_golangci-lint_v2_v2.10.1.txt @@ -0,0 +1,22 @@ +module github.com/golangci/golangci-lint/v2@latest + +Original import done via `go run addmod.go`. Dependencies have been manually +reduced to the minimum required by the test `get_tool_issue_74691`. +-- .mod -- +module github.com/golangci/golangci-lint/v2 + +// The minimum Go version must always be latest-1. +// This version should never be changed outside of the PR to add the support of newer Go version. +// Only golangci-lint maintainers are allowed to change it. +go 1.25.0 + +require github.com/securego/gosec/v2 v2.23.0 +-- .info -- +{"Version":"v2.10.1"} +-- cmd/golangci-lint/main.go -- +package main + +import _ "github.com/securego/gosec/v2/rules" + +func main() + diff --git a/src/cmd/go/testdata/mod/github.com_securego_gosec_v2_v2.23.0.txt b/src/cmd/go/testdata/mod/github.com_securego_gosec_v2_v2.23.0.txt new file mode 100644 index 00000000000000..90e54a51797421 --- /dev/null +++ b/src/cmd/go/testdata/mod/github.com_securego_gosec_v2_v2.23.0.txt @@ -0,0 +1,30 @@ +module github.com/securego/gosec/v2@v2.23.0 + +Original import done via `go run addmod.go`. Dependencies have been manually +reduced to the minimum required by the test `get_tool_issue_74691`. +-- .mod -- +module github.com/securego/gosec/v2 + +require ( + example.com v1.0.0 +) + +require ( + github.com/go-logr/logr v1.4.3 // indirect +) + +go 1.25.0 +-- .info -- +{"Version":"v2.23.0","Time":"2026-02-10T14:47:11Z","Origin":{"VCS":"git","URL":"https://github.com/securego/gosec","Hash":"398ad549bbf1a51dc978fd966169f660c59774de","Ref":"refs/tags/v2.23.0"}} +-- go.mod -- +module github.com/securego/gosec/v2 + +require example.com v1.0.0 + +go 1.25.0 +-- rules/rules_a.go -- +package rules + +import _ "example.com" // pull in a pre-module-pruning module (doesn't declare go version in go.mod) + + diff --git a/src/cmd/go/testdata/mod/golang.org_toolchain_v0.0.1-go1.19rc2.linux-amd64.txt b/src/cmd/go/testdata/mod/golang.org_toolchain_v0.0.1-go1.19rc2.linux-amd64.txt new file mode 100644 index 00000000000000..139b0adf94a0dc --- /dev/null +++ b/src/cmd/go/testdata/mod/golang.org_toolchain_v0.0.1-go1.19rc2.linux-amd64.txt @@ -0,0 +1,7 @@ +golang.org/toolchain v0.0.1-go1.19rc2.linux-amd64 +-- .info -- +{"Version":"v0.0.1-go1.19rc2.linux-amd64"} +-- .mod -- +golang.org/toolchain +-- go.mod -- +golang.org/toolchain diff --git a/src/cmd/go/testdata/mod/golang.org_toolchain_v0.0.1-go1.20.1.linux-amd64.txt b/src/cmd/go/testdata/mod/golang.org_toolchain_v0.0.1-go1.20.1.linux-amd64.txt new file mode 100644 index 00000000000000..3e0eae8e49bda1 --- /dev/null +++ b/src/cmd/go/testdata/mod/golang.org_toolchain_v0.0.1-go1.20.1.linux-amd64.txt @@ -0,0 +1,7 @@ +golang.org/toolchain v0.0.1-go1.20.1.linux-amd64 +-- .info -- +{"Version":"v0.0.1-go1.20.1.linux-amd64"} +-- .mod -- +golang.org/toolchain +-- go.mod -- +golang.org/toolchain diff --git a/src/cmd/go/testdata/mod/golang.org_x_net_v0.1.0.txt b/src/cmd/go/testdata/mod/golang.org_x_net_v0.1.0.txt new file mode 100644 index 00000000000000..66904b6c3f446b --- /dev/null +++ b/src/cmd/go/testdata/mod/golang.org_x_net_v0.1.0.txt @@ -0,0 +1,10 @@ +written by hand - just enough for list_std_vendor.txt + +-- .mod -- +module golang.org/x/net +-- .info -- +{"Version":"v0.1.0","Name":"","Short":"","Time":"2026-03-08T00:00:00Z"} +-- go.mod -- +module golang.org/x/net +-- dns/dnsmessage/dnsmessage.go -- +package dnsmessage diff --git a/src/cmd/go/testdata/mod/golang.org_x_pkgsite_v0.1.0.txt b/src/cmd/go/testdata/mod/golang.org_x_pkgsite_v0.1.0.txt new file mode 100644 index 00000000000000..e452874dcede75 --- /dev/null +++ b/src/cmd/go/testdata/mod/golang.org_x_pkgsite_v0.1.0.txt @@ -0,0 +1,20 @@ +example doc server + +-- .info -- +{"Version":"v0.1.0"} +-- .mod -- +module golang.org/x/pkgsite + +go 1.23 +-- go.mod -- +module golang.org/x/pkgsite + +go 1.23 +-- cmd/internal/doc/main.go -- +package main + +import "fmt" + +func main() { + fmt.Println("fake pkgsite doc server v0.1.0") +} diff --git a/src/cmd/go/testdata/mod/k8s.io_klog_v2_v2.130.1.txt b/src/cmd/go/testdata/mod/k8s.io_klog_v2_v2.130.1.txt new file mode 100644 index 00000000000000..2794d50eb4994b --- /dev/null +++ b/src/cmd/go/testdata/mod/k8s.io_klog_v2_v2.130.1.txt @@ -0,0 +1,22 @@ +Using requirements of .k8s.io/klog/v2 v2.130.1 + +Original import done via `go run addmod.go`. Dependencies have been manually +reduced to the minimum required by the test `get_tool_issue_74691`. +-- .mod -- +module k8s.io/klog/v2 + +go 1.21 + +require github.com/go-logr/logr v1.4.1 +-- .info -- +{"Version":"v2.130.1"} +-- go.mod -- +module k8s.io/klog/v2 + +go 1.21 + +require github.com/go-logr/logr v1.4.1 +-- foo.go -- +package foo + +import _ "github.com/go-logr/logr" diff --git a/src/cmd/go/testdata/mod/vcs-test.golang.org_git_hello.git_v0.0.0-20170922010558-fc3a09f3dc5c.txt b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_hello.git_v0.0.0-20170922010558-fc3a09f3dc5c.txt new file mode 100644 index 00000000000000..80881a0b81f5aa --- /dev/null +++ b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_hello.git_v0.0.0-20170922010558-fc3a09f3dc5c.txt @@ -0,0 +1,13 @@ +written by hand + +-- .mod -- +module vcs-test.golang.org/git/hello.git +-- .info -- +{"Version":"v0.0.0-20170922010558-fc3a09f3dc5c"} +-- testonly.go -- +package main + +func main() { + println("hello, world") +} + diff --git a/src/cmd/go/testdata/mod/vcs-test.golang.org_git_prefercompatible.git_v1.5.1.txt b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_prefercompatible.git_v1.5.1.txt new file mode 100644 index 00000000000000..71db393b446d5c --- /dev/null +++ b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_prefercompatible.git_v1.5.1.txt @@ -0,0 +1,8 @@ +written by hand + +-- .info -- +{"Version":"v1.5.1"} +-- .mod -- +module vcs-test.golang.org/git/prefercompatible.git +-- prefercompatible.go -- +package prefercompatible diff --git a/src/cmd/go/testdata/mod/vcs-test.golang.org_git_prefercompatible.git_v1.5.2.txt b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_prefercompatible.git_v1.5.2.txt new file mode 100644 index 00000000000000..f564ac74864695 --- /dev/null +++ b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_prefercompatible.git_v1.5.2.txt @@ -0,0 +1,10 @@ +written by hand + +-- .info -- +{"Version":"v1.5.2"} +-- .mod -- +module vcs-test.golang.org/git/prefercompatible.git + +go 1.12 +-- prefercompatible.go -- +package prefercompatible diff --git a/src/cmd/go/testdata/mod/vcs-test.golang.org_git_prefercompatible.git_v2.0.0+incompatible.txt b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_prefercompatible.git_v2.0.0+incompatible.txt new file mode 100644 index 00000000000000..1d7792821ef28a --- /dev/null +++ b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_prefercompatible.git_v2.0.0+incompatible.txt @@ -0,0 +1,8 @@ +written by hand + +-- .info -- +{"Version":"v2.0.0+incompatible"} +-- .mod -- +module vcs-test.golang.org/git/prefercompatible.git +-- prefercompatible.go -- +package prefercompatible diff --git a/src/cmd/go/testdata/mod/vcs-test.golang.org_git_proxyonly.git_v0.0.1.txt b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_proxyonly.git_v0.0.1.txt new file mode 100644 index 00000000000000..ce83076183c8d3 --- /dev/null +++ b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_proxyonly.git_v0.0.1.txt @@ -0,0 +1,8 @@ +This is a module that could exist in a vcstest git repo, but that doesn't. + +-- .mod -- +module vcs-test.golang.org/git/proxyonly.git +-- .info -- +{"Version":"v0.0.1"} +-- proxyonly.go -- +package proxyonly diff --git a/src/cmd/go/testdata/mod/vcs-test.golang.org_git_tagtests.git_v0.1.0.txt b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_tagtests.git_v0.1.0.txt new file mode 100644 index 00000000000000..043bad3b822cb8 --- /dev/null +++ b/src/cmd/go/testdata/mod/vcs-test.golang.org_git_tagtests.git_v0.1.0.txt @@ -0,0 +1,9 @@ +There's a tagtests git repo, but add a proxy version, so we +can test that it's not available in mod_gonoproxy. + +-- .mod -- +module vcs-test.golang.org/git/tagtests.git +-- .info -- +{"Version":"v0.1.0"} +-- tagtests.go -- +package tagtests diff --git a/src/cmd/go/testdata/script/README b/src/cmd/go/testdata/script/README index 7724bc10ec46f0..71052159b6e4f5 100644 --- a/src/cmd/go/testdata/script/README +++ b/src/cmd/go/testdata/script/README @@ -377,8 +377,6 @@ The available conditions are: GOOS/GOARCH supports -asan [buildmode:*] go supports -buildmode= -[bzr] - the 'bzr' executable exists and provides the standard CLI [case-sensitive] $WORK filesystem is case-sensitive [cc:*] @@ -391,6 +389,8 @@ The available conditions are: runtime.Compiler == [cross] cmd/go GOOS/GOARCH != GOHOSTOS/GOHOSTARCH +[default-cgo] + when CGO_ENABLED=1|0 was set in make.bash [exec:*] names an executable in the test binary's PATH [fuzz] @@ -399,6 +399,8 @@ The available conditions are: GOOS/GOARCH supports -fuzz with instrumentation [git] the 'git' executable exists and provides the standard CLI +[git-sha256] + the local 'git' version is recent enough to support sha256 object/commit hashes [go-builder] GO_BUILDER_NAME is non-empty [link] @@ -407,8 +409,6 @@ The available conditions are: GOOS/GOARCH supports -msan [mustlinkext] platform always requires external linking -[net:*] - can connect to external network host [pielinkext] platform requires external linking for PIE [race] diff --git a/src/cmd/go/testdata/script/autocgo.txt b/src/cmd/go/testdata/script/autocgo.txt index 586c80251da319..33e72016b4dd29 100644 --- a/src/cmd/go/testdata/script/autocgo.txt +++ b/src/cmd/go/testdata/script/autocgo.txt @@ -1,7 +1,7 @@ # Test automatic setting of CGO_ENABLED based on $CC and what's in $PATH. [!cgo] skip -[cross] skip +[default-cgo] skip # Assume we're on a system that can enable cgo normally. env CGO_ENABLED= diff --git a/src/cmd/go/testdata/script/build_buildvcs_auto.txt b/src/cmd/go/testdata/script/build_buildvcs_auto.txt index cfd5d8243b8e20..cb1207c90f2b28 100644 --- a/src/cmd/go/testdata/script/build_buildvcs_auto.txt +++ b/src/cmd/go/testdata/script/build_buildvcs_auto.txt @@ -57,7 +57,7 @@ cd .. env PATH= env path= ! go build -buildvcs -o example.exe . -stderr 'go: missing Git command\. See https://golang\.org/s/gogetcmd$' +stderr 'go: missing Git command\. See https://go\.dev/s/gogetcmd$' # ...but by default we should omit VCS metadata when the tool is missing. diff --git a/src/cmd/go/testdata/script/build_git_sha256_go_get_branch.txt b/src/cmd/go/testdata/script/build_git_sha256_go_get_branch.txt index fa5557b21e6d7f..1e71e25f11fede 100644 --- a/src/cmd/go/testdata/script/build_git_sha256_go_get_branch.txt +++ b/src/cmd/go/testdata/script/build_git_sha256_go_get_branch.txt @@ -1,5 +1,6 @@ [short] skip [!git] skip +[!git-sha256] skip env GOPRIVATE=vcs-test.golang.org diff --git a/src/cmd/go/testdata/script/build_git_sha256_moddep.txt b/src/cmd/go/testdata/script/build_git_sha256_moddep.txt index e5bf209d895867..7048e8f2e4b860 100644 --- a/src/cmd/go/testdata/script/build_git_sha256_moddep.txt +++ b/src/cmd/go/testdata/script/build_git_sha256_moddep.txt @@ -1,5 +1,6 @@ [short] skip [!git] skip +[!git-sha256] skip env GOPRIVATE=vcs-test.golang.org diff --git a/src/cmd/go/testdata/script/build_line_directive_relative.txt b/src/cmd/go/testdata/script/build_line_directive_relative.txt new file mode 100644 index 00000000000000..d8218755156e08 --- /dev/null +++ b/src/cmd/go/testdata/script/build_line_directive_relative.txt @@ -0,0 +1,32 @@ +# Verify that the compiler resolves a relative filename in a //line directive +# against the directory of the file containing the directive, not against +# the compiler's working directory. +# See go.dev/issue/70478. + +# Build from the module root: the resolved path should include the package dir. +! go build ./sub +stderr 'sub[/\\]README\.md:1: ' + +# Build from a sibling directory (still inside the module): same resolved path. +mkdir other +cd other +! go build ../sub +stderr 'sub[/\\]README\.md:1: ' +cd .. + +# Build from inside the package directory: the resolved path is anchored at +# that directory (which would not be the case under the pre-#70478 behavior, +# where the bare README.md was reported regardless of the build CWD). +cd sub +! go build . +stderr '\.[/\\]README\.md:1: ' + +-- go.mod -- +module example.com/linedirtest + +go 1.21 +-- sub/foo.go -- +package sub + +//line README.md:1 +invalid diff --git a/src/cmd/go/testdata/script/build_overlay.txt b/src/cmd/go/testdata/script/build_overlay.txt index 1111d119ba2841..fe6ddadaaaa112 100644 --- a/src/cmd/go/testdata/script/build_overlay.txt +++ b/src/cmd/go/testdata/script/build_overlay.txt @@ -33,28 +33,10 @@ exec ./print_trimpath_two_files$GOEXE stdout $WORK[/\\]gopath[/\\]src[/\\]m[/\\]printpath[/\\]main.go stdout $WORK[/\\]gopath[/\\]src[/\\]m[/\\]printpath[/\\]other.go -[cgo] go build -overlay overlay.json -o main_cgo_replace$GOEXE ./cgo_hello_replace -[cgo] exec ./main_cgo_replace$GOEXE -[cgo] stdout '^hello cgo\r?\n' - -[cgo] go build -overlay overlay.json -o main_cgo_quote$GOEXE ./cgo_hello_quote -[cgo] exec ./main_cgo_quote$GOEXE -[cgo] stdout '^hello cgo\r?\n' - -[cgo] go build -overlay overlay.json -o main_cgo_angle$GOEXE ./cgo_hello_angle -[cgo] exec ./main_cgo_angle$GOEXE -[cgo] stdout '^hello cgo\r?\n' - go build -overlay overlay.json -o main_call_asm$GOEXE ./call_asm exec ./main_call_asm$GOEXE ! stdout . -[cgo] go list -compiled -overlay overlay.json -f '{{range .CompiledGoFiles}}{{. | printf "%s\n"}}{{end}}' ./cgo_hello_replace -[cgo] cp stdout compiled_cgo_sources.txt -[cgo] go run ../print_line_comments.go compiled_cgo_sources.txt -[cgo] stdout $GOPATH[/\\]src[/\\]m[/\\]cgo_hello_replace[/\\]cgo_hello_replace.go -[cgo] ! stdout $GOPATH[/\\]src[/\\]m[/\\]overlay[/\\]hello.c - # Change the contents of a file in the overlay and ensure that makes the target stale env OLD_GOCACHE=$GOCACHE env GOCACHE=$WORK/cache # use a fresh cache so that multiple runs of the test don't interfere @@ -67,42 +49,6 @@ go build -x -overlay overlay.json ./test_cache stderr '(compile|gccgo)( |\.exe).*test_cache.go' # not cached env CACHE=$OLD_GOCACHE -# Run same tests but with gccgo. -env GO111MODULE=off -[!exec:gccgo] stop -[cross] stop # gccgo can't necessarily cross-compile - -! go build -compiler=gccgo . -go build -compiler=gccgo -overlay overlay.json -o main_gccgo$GOEXE . -exec ./main_gccgo$goexe -stdout '^hello$' - -go build -compiler=gccgo -overlay overlay.json -o print_abspath_gccgo$GOEXE ./printpath -exec ./print_abspath_gccgo$GOEXE -stdout $WORK[/\\]gopath[/\\]src[/\\]m[/\\]printpath[/\\]main.go - -go build -compiler=gccgo -overlay overlay.json -o print_trimpath_gccgo$GOEXE -trimpath ./printpath -exec ./print_trimpath_gccgo$GOEXE -stdout ^\.[/\\]printpath[/\\]main.go - - -go build -compiler=gccgo -overlay overlay.json -o main_cgo_replace_gccgo$GOEXE ./cgo_hello_replace -exec ./main_cgo_replace_gccgo$GOEXE -stdout '^hello cgo\r?\n' - -go build -compiler=gccgo -overlay overlay.json -o main_cgo_quote_gccgo$GOEXE ./cgo_hello_quote -exec ./main_cgo_quote_gccgo$GOEXE -stdout '^hello cgo\r?\n' - -go build -compiler=gccgo -overlay overlay.json -o main_cgo_angle_gccgo$GOEXE ./cgo_hello_angle -exec ./main_cgo_angle_gccgo$GOEXE -stdout '^hello cgo\r?\n' - -go build -compiler=gccgo -overlay overlay.json -o main_call_asm_gccgo$GOEXE ./call_asm -exec ./main_call_asm_gccgo$GOEXE -! stdout . - - -- m/go.mod -- // TODO(matloob): how do overlays work with go.mod (especially if mod=readonly) module m @@ -131,33 +77,9 @@ the actual code is in the overlay "printpath/other.go": "overlay2/printpath2.go", "call_asm/asm_gc.s": "overlay/asm_gc.s", "call_asm/asm_gccgo.s": "overlay/asm_gccgo.s", - "test_cache/main.go": "overlay/test_cache.go", - "cgo_hello_replace/cgo_header.h": "overlay/cgo_head.h", - "cgo_hello_replace/hello.c": "overlay/hello.c", - "cgo_hello_quote/cgo_hello.go": "overlay/cgo_hello_quote.go", - "cgo_hello_quote/cgo_header.h": "overlay/cgo_head.h", - "cgo_hello_angle/cgo_hello.go": "overlay/cgo_hello_angle.go", - "cgo_hello_angle/cgo_header.h": "overlay/cgo_head.h" + "test_cache/main.go": "overlay/test_cache.go" } } --- m/cgo_hello_replace/cgo_hello_replace.go -- -package main - -// #include "cgo_header.h" -import "C" - -func main() { - C.say_hello() -} --- m/cgo_hello_replace/cgo_header.h -- - // Test that this header is replaced with one that has the proper declaration. -void say_goodbye(); - --- m/cgo_hello_replace/hello.c -- -#include - -void say_goodbye() { puts("goodbye cgo\n"); fflush(stdout); } - -- m/overlay/f.go -- package main @@ -220,30 +142,6 @@ import "m/dir" func printMessage() { dir.PrintMessage() } --- m/overlay/cgo_hello_quote.go -- -package main - -// #include "cgo_header.h" -import "C" - -func main() { - C.say_hello() -} --- m/overlay/cgo_hello_angle.go -- -package main - -// #include -import "C" - -func main() { - C.say_hello() -} --- m/overlay/cgo_head.h -- -void say_hello(); --- m/overlay/hello.c -- -#include - -void say_hello() { puts("hello cgo\n"); fflush(stdout); } -- m/overlay/asm_gc.s -- // +build gc @@ -274,42 +172,3 @@ import "fmt" func bar() { fmt.Println("different") } --- m/cgo_hello_quote/hello.c -- -#include - -void say_hello() { puts("hello cgo\n"); fflush(stdout); } --- m/cgo_hello_angle/hello.c -- -#include - -void say_hello() { puts("hello cgo\n"); fflush(stdout); } - --- print_line_comments.go -- -package main - -import ( - "fmt" - "io/ioutil" - "log" - "os" - "strings" -) - -func main() { - compiledGoFilesArg := os.Args[1] - b, err := ioutil.ReadFile(compiledGoFilesArg) - if err != nil { - log.Fatal(err) - } - compiledGoFiles := strings.Split(strings.TrimSpace(string(b)), "\n") - for _, f := range compiledGoFiles { - b, err := ioutil.ReadFile(f) - if err != nil { - log.Fatal(err) - } - for _, line := range strings.Split(string(b), "\n") { - if strings.HasPrefix(line, "#line") || strings.HasPrefix(line, "//line") { - fmt.Println(line) - } - } - } -} diff --git a/src/cmd/go/testdata/script/build_overlay_cgo.txt b/src/cmd/go/testdata/script/build_overlay_cgo.txt new file mode 100644 index 00000000000000..c5b6bf3bbf53ab --- /dev/null +++ b/src/cmd/go/testdata/script/build_overlay_cgo.txt @@ -0,0 +1,128 @@ +[short] skip +[!cgo] skip + +# Test building cgo packages in overlays. + +cd m + +go build -overlay overlay.json -o main_cgo_replace$GOEXE ./cgo_hello_replace +exec ./main_cgo_replace$GOEXE +stdout '^hello cgo\r?\n' + +go build -overlay overlay.json -o main_cgo_quote$GOEXE ./cgo_hello_quote +exec ./main_cgo_quote$GOEXE +stdout '^hello cgo\r?\n' + +go build -overlay overlay.json -o main_cgo_angle$GOEXE ./cgo_hello_angle +exec ./main_cgo_angle$GOEXE +stdout '^hello cgo\r?\n' + +go list -compiled -overlay overlay.json -f '{{range .CompiledGoFiles}}{{. | printf "%s\n"}}{{end}}' ./cgo_hello_replace +cp stdout compiled_cgo_sources.txt +go run ../print_line_comments.go compiled_cgo_sources.txt +stdout $GOPATH[/\\]src[/\\]m[/\\]cgo_hello_replace[/\\]cgo_hello_replace.go +! stdout $GOPATH[/\\]src[/\\]m[/\\]overlay[/\\]hello.c + +-- m/go.mod -- +// TODO(matloob): how do overlays work with go.mod (especially if mod=readonly) +module m + +go 1.16 + +-- m/overlay.json -- +{ + "Replace": { + "printpath/main.go": "overlay/printpath.go", + "printpath/other.go": "overlay2/printpath2.go", + "call_asm/asm_gc.s": "overlay/asm_gc.s", + "call_asm/asm_gccgo.s": "overlay/asm_gccgo.s", + "test_cache/main.go": "overlay/test_cache.go", + "cgo_hello_replace/cgo_header.h": "overlay/cgo_head.h", + "cgo_hello_replace/hello.c": "overlay/hello.c", + "cgo_hello_quote/cgo_hello.go": "overlay/cgo_hello_quote.go", + "cgo_hello_quote/cgo_header.h": "overlay/cgo_head.h", + "cgo_hello_angle/cgo_hello.go": "overlay/cgo_hello_angle.go", + "cgo_hello_angle/cgo_header.h": "overlay/cgo_head.h" + } +} +-- m/cgo_hello_replace/cgo_hello_replace.go -- +package main + +// #include "cgo_header.h" +import "C" + +func main() { + C.say_hello() +} +-- m/cgo_hello_replace/cgo_header.h -- + // Test that this header is replaced with one that has the proper declaration. +void say_goodbye(); + +-- m/cgo_hello_replace/hello.c -- +#include + +void say_goodbye() { puts("goodbye cgo\n"); fflush(stdout); } + +-- m/overlay/cgo_hello_quote.go -- +package main + +// #include "cgo_header.h" +import "C" + +func main() { + C.say_hello() +} +-- m/overlay/cgo_hello_angle.go -- +package main + +// #include +import "C" + +func main() { + C.say_hello() +} +-- m/overlay/cgo_head.h -- +void say_hello(); +-- m/overlay/hello.c -- +#include + +void say_hello() { puts("hello cgo\n"); fflush(stdout); } +-- m/cgo_hello_quote/hello.c -- +#include + +void say_hello() { puts("hello cgo\n"); fflush(stdout); } +-- m/cgo_hello_angle/hello.c -- +#include + +void say_hello() { puts("hello cgo\n"); fflush(stdout); } + +-- print_line_comments.go -- +package main + +import ( + "fmt" + "io/ioutil" + "log" + "os" + "strings" +) + +func main() { + compiledGoFilesArg := os.Args[1] + b, err := ioutil.ReadFile(compiledGoFilesArg) + if err != nil { + log.Fatal(err) + } + compiledGoFiles := strings.Split(strings.TrimSpace(string(b)), "\n") + for _, f := range compiledGoFiles { + b, err := ioutil.ReadFile(f) + if err != nil { + log.Fatal(err) + } + for _, line := range strings.Split(string(b), "\n") { + if strings.HasPrefix(line, "#line") || strings.HasPrefix(line, "//line") { + fmt.Println(line) + } + } + } +} diff --git a/src/cmd/go/testdata/script/build_overlay_gccgo.txt b/src/cmd/go/testdata/script/build_overlay_gccgo.txt new file mode 100644 index 00000000000000..4cc0c49ac547a2 --- /dev/null +++ b/src/cmd/go/testdata/script/build_overlay_gccgo.txt @@ -0,0 +1,209 @@ +[short] skip +[!exec:gccgo] skip +[cross] skip # gccgo can't necessarily cross-compile + +# Test building in overlays with gccgo. +# TODO(#39958): add a test that both gc and gccgo assembly files can include .h +# files. + +# The main package (m) is contained in an overlay. It imports m/dir2 which has one +# file in an overlay and one file outside the overlay, which in turn imports m/dir, +# which only has source files in the overlay. + +env GO111MODULE=off + +cd m + +! go build -compiler=gccgo . +go build -compiler=gccgo -overlay overlay.json -o main_gccgo$GOEXE . +exec ./main_gccgo$goexe +stdout '^hello$' + +go build -compiler=gccgo -overlay overlay.json -o print_abspath_gccgo$GOEXE ./printpath +exec ./print_abspath_gccgo$GOEXE +stdout $WORK[/\\]gopath[/\\]src[/\\]m[/\\]printpath[/\\]main.go + +go build -compiler=gccgo -overlay overlay.json -o print_trimpath_gccgo$GOEXE -trimpath ./printpath +exec ./print_trimpath_gccgo$GOEXE +stdout ^\.[/\\]printpath[/\\]main.go + + +go build -compiler=gccgo -overlay overlay.json -o main_cgo_replace_gccgo$GOEXE ./cgo_hello_replace +exec ./main_cgo_replace_gccgo$GOEXE +stdout '^hello cgo\r?\n' + +go build -compiler=gccgo -overlay overlay.json -o main_cgo_quote_gccgo$GOEXE ./cgo_hello_quote +exec ./main_cgo_quote_gccgo$GOEXE +stdout '^hello cgo\r?\n' + +go build -compiler=gccgo -overlay overlay.json -o main_cgo_angle_gccgo$GOEXE ./cgo_hello_angle +exec ./main_cgo_angle_gccgo$GOEXE +stdout '^hello cgo\r?\n' + +go build -compiler=gccgo -overlay overlay.json -o main_call_asm_gccgo$GOEXE ./call_asm +exec ./main_call_asm_gccgo$GOEXE +! stdout . + +-- m/go.mod -- +// TODO(matloob): how do overlays work with go.mod (especially if mod=readonly) +module m + +go 1.16 + +-- m/dir2/h.go -- +package dir2 + +func PrintMessage() { + printMessage() +} +-- m/dir/foo.txt -- +The build action code currently expects the package directory +to exist, so it can run the compiler in that directory. +TODO(matloob): Remove this requirement. +-- m/printpath/about.txt -- +the actual code is in the overlay +-- m/overlay.json -- +{ + "Replace": { + "f.go": "overlay/f.go", + "dir/g.go": "overlay/dir_g.go", + "dir2/i.go": "overlay/dir2_i.go", + "printpath/main.go": "overlay/printpath.go", + "printpath/other.go": "overlay2/printpath2.go", + "call_asm/asm_gc.s": "overlay/asm_gc.s", + "call_asm/asm_gccgo.s": "overlay/asm_gccgo.s", + "test_cache/main.go": "overlay/test_cache.go", + "cgo_hello_replace/cgo_header.h": "overlay/cgo_head.h", + "cgo_hello_replace/hello.c": "overlay/hello.c", + "cgo_hello_quote/cgo_hello.go": "overlay/cgo_hello_quote.go", + "cgo_hello_quote/cgo_header.h": "overlay/cgo_head.h", + "cgo_hello_angle/cgo_hello.go": "overlay/cgo_hello_angle.go", + "cgo_hello_angle/cgo_header.h": "overlay/cgo_head.h" + } +} +-- m/cgo_hello_replace/cgo_hello_replace.go -- +package main + +// #include "cgo_header.h" +import "C" + +func main() { + C.say_hello() +} +-- m/cgo_hello_replace/cgo_header.h -- + // Test that this header is replaced with one that has the proper declaration. +void say_goodbye(); + +-- m/cgo_hello_replace/hello.c -- +#include + +void say_goodbye() { puts("goodbye cgo\n"); fflush(stdout); } + +-- m/overlay/f.go -- +package main + +import "m/dir2" + +func main() { + dir2.PrintMessage() +} +-- m/call_asm/main.go -- +package main + +func foo() // There will be a "missing function body" error if the assembly file isn't found. + +func main() { + foo() +} +-- m/overlay/dir_g.go -- +package dir + +import "fmt" + +func PrintMessage() { + fmt.Println("hello") +} +-- m/overlay/printpath.go -- +package main + +import ( + "fmt" + "path/filepath" + "runtime" +) + +func main() { + _, file, _, _ := runtime.Caller(0) + + // Since https://golang.org/cl/214286, the runtime's debug paths are + // slash-separated regardless of platform, so normalize them to system file + // paths. + fmt.Println(filepath.FromSlash(file)) +} +-- m/overlay2/printpath2.go -- +package main + +import ( + "fmt" + "path/filepath" + "runtime" +) + +func init() { + _, file, _, _ := runtime.Caller(0) + fmt.Println(filepath.FromSlash(file)) +} +-- m/overlay/dir2_i.go -- +package dir2 + +import "m/dir" + +func printMessage() { + dir.PrintMessage() +} +-- m/overlay/cgo_hello_quote.go -- +package main + +// #include "cgo_header.h" +import "C" + +func main() { + C.say_hello() +} +-- m/overlay/cgo_hello_angle.go -- +package main + +// #include +import "C" + +func main() { + C.say_hello() +} +-- m/overlay/cgo_head.h -- +void say_hello(); +-- m/overlay/hello.c -- +#include + +void say_hello() { puts("hello cgo\n"); fflush(stdout); } +-- m/overlay/asm_gc.s -- +// +build gc + +TEXT ·foo(SB),0,$0 + RET + +-- m/overlay/asm_gccgo.s -- +// +build gccgo + +.globl main.foo +.text +main.foo: + ret + +-- m/cgo_hello_quote/hello.c -- +#include + +void say_hello() { puts("hello cgo\n"); fflush(stdout); } +-- m/cgo_hello_angle/hello.c -- +#include + +void say_hello() { puts("hello cgo\n"); fflush(stdout); } diff --git a/src/cmd/go/testdata/script/cgo_bad_directives.txt b/src/cmd/go/testdata/script/cgo_bad_directives.txt index 7d28171fad47e7..0c64b6d9a40f16 100644 --- a/src/cmd/go/testdata/script/cgo_bad_directives.txt +++ b/src/cmd/go/testdata/script/cgo_bad_directives.txt @@ -45,6 +45,11 @@ cp y_pkgconfig_at_foo.txt y.go ! go build x stderr 'invalid pkg-config package name: @foo' +# Reject #cgo pkg-config: --log-file=/tmp/log +cp y_pkgconfig_log_file.txt y.go +! go build x +stderr 'invalid flag in pkg-config: --log-file=/tmp/log' + # Reject #cgo CFLAGS: @foo cp y_cflags_at_foo.txt y.go ! go build x @@ -108,6 +113,10 @@ import "C" package x // #cgo pkg-config: @foo import "C" +-- y_pkgconfig_log_file.txt -- +package x +// #cgo pkg-config: --log-file=/tmp/log +import "C" -- y_cflags_at_foo.txt -- package x // #cgo CFLAGS: @foo diff --git a/src/cmd/go/testdata/script/cgo_g3.txt b/src/cmd/go/testdata/script/cgo_g3.txt new file mode 100644 index 00000000000000..ada9a8c6914036 --- /dev/null +++ b/src/cmd/go/testdata/script/cgo_g3.txt @@ -0,0 +1,18 @@ +[!cgo] skip + +# Test that -g3 works with cgo. +env CGO_CFLAGS=-g3 +go build + +-- go.mod -- +module cgog3 + +go 1.25 +-- m.go -- +package main + +import "os/user" + +func main() { + user.Current() +} diff --git a/src/cmd/go/testdata/script/cgo_suspect_flag_force_external.txt b/src/cmd/go/testdata/script/cgo_suspect_flag_force_external.txt index b4b2d14b11df33..0d17cbf78af6fd 100644 --- a/src/cmd/go/testdata/script/cgo_suspect_flag_force_external.txt +++ b/src/cmd/go/testdata/script/cgo_suspect_flag_force_external.txt @@ -91,6 +91,36 @@ go build -x -n -o dummy.exe ./usesInternalCgo ! stderr preferlinkext env CGO_CFLAGS= +# CGO_LDFLAGS with -static variants are not compatible with internal linking. +env CGO_LDFLAGS=-static +go build -x -n -o dummy.exe ./usesInternalCgo +stderr preferlinkext +env CGO_LDFLAGS=--static +go build -x -n -o dummy.exe ./usesInternalCgo +stderr preferlinkext +env CGO_LDFLAGS=-Wl,-static +go build -x -n -o dummy.exe ./usesInternalCgo +stderr preferlinkext +env CGO_LDFLAGS=-Wl,--static +go build -x -n -o dummy.exe ./usesInternalCgo +stderr preferlinkext +env CGO_LDFLAGS=-Wl,-Bstatic +go build -x -n -o dummy.exe ./usesInternalCgo +stderr preferlinkext +env CGO_LDFLAGS= + +# CGO_LDFLAGS=-static-libgcc does NOT trigger external linking. +env CGO_LDFLAGS=-static-libgcc +go build -x -n -o dummy.exe ./usesInternalCgo +! stderr preferlinkext +env CGO_LDFLAGS= + +# CGO_CFLAGS=--static triggers external linking (some toolchains accept it). +env CGO_CFLAGS=--static +go build -x -n -o dummy.exe ./usesInternalCgo +stderr preferlinkext +env CGO_CFLAGS= + [short] skip # In the remaining tests below we do actual builds (without -n) to diff --git a/src/cmd/go/testdata/script/cover_switch_toolchain.txt b/src/cmd/go/testdata/script/cover_switch_toolchain.txt new file mode 100644 index 00000000000000..dace804fb6cb27 --- /dev/null +++ b/src/cmd/go/testdata/script/cover_switch_toolchain.txt @@ -0,0 +1,12 @@ +go test -cover -n ./... +[!GOOS:windows] stderr $GOROOT'/bin/go tool covdata' +[GOOS:windows] stderr '\\\\bin\\\\go" tool covdata' + +-- go.mod -- +module example.com/m + +go 1.25.0 +-- m.go -- +package main + +func main() {} diff --git a/src/cmd/go/testdata/script/doc_all_short.txt b/src/cmd/go/testdata/script/doc_all_short.txt new file mode 100644 index 00000000000000..e6a89ec98e23b4 --- /dev/null +++ b/src/cmd/go/testdata/script/doc_all_short.txt @@ -0,0 +1,2 @@ +! go doc -all -short +stderr 'doc: cannot combine -all and -short' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/doc_http_build.txt b/src/cmd/go/testdata/script/doc_http_build.txt new file mode 100644 index 00000000000000..e050ff82cc6814 --- /dev/null +++ b/src/cmd/go/testdata/script/doc_http_build.txt @@ -0,0 +1,4 @@ +# This test builds the pkgsite doc binary using the local script test proxy. +env TEST_GODOC_BUILD_ONLY=1 + +go doc -http fmt diff --git a/src/cmd/go/testdata/script/doc_http_clean_cache.txt b/src/cmd/go/testdata/script/doc_http_clean_cache.txt new file mode 100644 index 00000000000000..0c44326a3f16eb --- /dev/null +++ b/src/cmd/go/testdata/script/doc_http_clean_cache.txt @@ -0,0 +1,11 @@ +[short] skip 'builds pkgsite on clean GOCACHE' + +# Test that go doc -http succeeds on a clean GOCACHE (golang/go#80287). +env TEST_GODOC_BUILD_ONLY=1 +env GOCACHE=$WORK/clean-gocache + +# First run with clean GOCACHE +go doc -http fmt + +# Second run with existing GOCACHE +go doc -http fmt diff --git a/src/cmd/go/testdata/script/doc_http_url.txt b/src/cmd/go/testdata/script/doc_http_url.txt new file mode 100644 index 00000000000000..19947dd7708067 --- /dev/null +++ b/src/cmd/go/testdata/script/doc_http_url.txt @@ -0,0 +1,31 @@ +env TEST_GODOC_URL_FILE=$WORK/url.txt + +# Outside of a module. +go doc -http +grep '/std' $TEST_GODOC_URL_FILE + +# Inside a module with a major version suffix. +# We should use the major version suffix rather than +# the location in the gopath (#75976). +cd example.com/m +go doc -http +grep '/example.com/m/v5' $TEST_GODOC_URL_FILE +go doc -http . +grep '/example.com/m/v5' $TEST_GODOC_URL_FILE + +# In GOPATH mode, we should use the location in the GOPATH. +env GO111MODULE=off +go doc -http +grep '/std' $TEST_GODOC_URL_FILE +# TODO(matloob): This should probably this be the same as 'go doc -http .' +! grep '/example.com/m' $TEST_GODOC_URL_FILE +go doc -http . +grep '/example.com/m' $TEST_GODOC_URL_FILE +! grep '/example.com/m/v5' $TEST_GODOC_URL_FILE + +-- example.com/m/go.mod -- +module example.com/m/v5 + +go 1.27 +-- example.com/m/m.go -- +package m \ No newline at end of file diff --git a/src/cmd/go/testdata/script/doc_internal.txt b/src/cmd/go/testdata/script/doc_internal.txt new file mode 100644 index 00000000000000..a35960662cdec0 --- /dev/null +++ b/src/cmd/go/testdata/script/doc_internal.txt @@ -0,0 +1,32 @@ +# go doc prefers non-internal packages for shorthand package paths. + +env GO111MODULE=off +cd example.com/z/docpick + +go doc docpick.Public +stdout 'package docpick // import "example.com/z/docpick"' +stdout 'func Public' +! stdout 'internal/docpick' + +! go doc docpick.DoesNotExist +stderr 'doc: no symbol DoesNotExist in package example.com/z/docpick' +! stderr 'internal/docpick' + +go doc onlyinternal.Only +stdout 'package onlyinternal // import "example.com/internal/onlyinternal"' +stdout 'func Only' + +-- example.com/internal/docpick/doc.go -- +package docpick + +func Internal() {} + +-- example.com/internal/onlyinternal/doc.go -- +package onlyinternal + +func Only() {} + +-- example.com/z/docpick/doc.go -- +package docpick + +func Public() {} diff --git a/src/cmd/go/testdata/script/env_gobin.txt b/src/cmd/go/testdata/script/env_gobin.txt new file mode 100644 index 00000000000000..3dfec3570e9ab6 --- /dev/null +++ b/src/cmd/go/testdata/script/env_gobin.txt @@ -0,0 +1,44 @@ + +go env GOBIN +stdout $WORK${/}gopath${/}bin +go env -changed GOBIN +! stdout $WORK + +# report explicit settings +env GOBIN=/tmp/gobin +go env GOBIN +stdout /tmp/gobin +go env -changed GOBIN +stdout /tmp/gobin + +# reset +env GOBIN= +go env -changed GOBIN +! stdout $WORK + +# In GOPATH mode +# the default install directory depends on the GOPATH +# technically it also depends on the install target +# but that's not something we can report. +env GO111MODULE=off +env GOPATH=$WORK${/}a${:}$WORK${/}b + +# report GOPATH[0]/bin outside of GOPATH +cd $WORK +go env GOBIN +stdout $WORK${/}a${/}bin + +# report the current GOPATH/bin inside of a GOPATH +cd $WORK/a/src/example1.com +go env GOBIN +stdout $WORK${/}a${/}bin + +cd $WORK/b/src/example2.com +go env GOBIN +stdout $WORK${/}b${/}bin + +-- $WORK/a/src/example1.com/main.go -- +package main + +-- $WORK/b/src/example2.com/main.go -- +package main diff --git a/src/cmd/go/testdata/script/env_write.txt b/src/cmd/go/testdata/script/env_write.txt index bf14a2f0bd8423..2d76ba3c2ef058 100644 --- a/src/cmd/go/testdata/script/env_write.txt +++ b/src/cmd/go/testdata/script/env_write.txt @@ -71,6 +71,8 @@ stderr 'unknown go command variable GOGC' stderr 'GOEXE cannot be modified' ! go env -w GOVERSION=customversion stderr 'GOVERSION cannot be modified' +! go env -w GOROOT=./go +stderr 'GOROOT cannot be modified' ! go env -w GOENV=/env stderr 'GOENV can only be set using the OS environment' ! go env -w GODEBUG=gctrace=1 diff --git a/src/cmd/go/testdata/script/fipssnap.txt b/src/cmd/go/testdata/script/fipssnap.txt index 4d96aedf2a472d..57b938df1064d7 100644 --- a/src/cmd/go/testdata/script/fipssnap.txt +++ b/src/cmd/go/testdata/script/fipssnap.txt @@ -1,4 +1,4 @@ -env snap=v1.0.0-c2097c7c +env snap=v1.26.0 env alias=inprocess env GOFIPS140=$snap @@ -43,6 +43,13 @@ stdout crypto/internal/fips140/$snap/sha256 [short] skip +# FIPS snapshot packages should have install targets with GODEBUG=installgoroot=all +# (issue #76225) +env GODEBUG=installgoroot=all +go list -f '{{.Target}}' crypto/internal/fips140/$snap/sha256 +stdout 'crypto/internal/fips140/'$snap'/sha256\.a$' +env GODEBUG= + # build with GOFIPS140=snap is cached go build -x -o x.exe stderr link.*-fipso diff --git a/src/cmd/go/testdata/script/fipssnap_modcache.txt b/src/cmd/go/testdata/script/fipssnap_modcache.txt new file mode 100644 index 00000000000000..ca43ec9a7d6ce2 --- /dev/null +++ b/src/cmd/go/testdata/script/fipssnap_modcache.txt @@ -0,0 +1,61 @@ +# The module cache copy of a FIPS snapshot is used only if the module +# cache records the module zip hash from GOROOT/lib/fips140/fips140.sum +# for it, the way downloaded modules are checked against go.sum. +# Otherwise it is discarded and the snapshot is unpacked again. +# +# This detects a cache entry that was not unpacked from the bundled +# snapshot (or whose hash record is missing). Like go.sum, it does not +# protect the module cache from being modified in place: the replaced +# source file below stands in for stale contents, not an attacker. + +env snap=v1.26.0 +env GOFIPS140=$snap +env GOMODCACHE=$WORK/modcache +env GOFLAGS=-modcacherw + +# Go+BoringCrypto conflicts with GOFIPS140. +[GOEXPERIMENT:boringcrypto] skip + +env ziphash=$GOMODCACHE/cache/download/golang.org/fips140/@v/$snap.ziphash +env srcfile=$GOMODCACHE/golang.org/fips140@$snap/fips140/$snap/sha256/sha256.go + +# unpacking the snapshot records its module zip hash in the module cache +go list -f '{{.DefaultGODEBUG}}' +stdout fips140=on +exists $ziphash +exists $srcfile +grep '^h1:dtoPX1ALGGp4rMLzyh6oqIkYRXnXxRkpPWu56l5DFpM=$' $ziphash +cp $ziphash good.ziphash + +# a recorded hash that does not match fips140.sum +# discards the cached copy and unpacks the snapshot again +cp bad.ziphash $ziphash +rm $srcfile +cp stale/sha256.go $srcfile +go list -f '{{.DefaultGODEBUG}}' +stdout fips140=on +exists $srcfile +! grep stale $srcfile +cmp $ziphash good.ziphash + +# so does a missing hash +rm $ziphash +rm $srcfile +cp stale/sha256.go $srcfile +go list -f '{{.DefaultGODEBUG}}' +stdout fips140=on +exists $srcfile +! grep stale $srcfile +cmp $ziphash good.ziphash + +-- go.mod -- +module m +-- x.go -- +package main +import _ "crypto/sha256" +func main() { +} +-- bad.ziphash -- +h1:AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA= +-- stale/sha256.go -- +package sha256 // stale diff --git a/src/cmd/go/testdata/script/fix_diff_exitcode.txt b/src/cmd/go/testdata/script/fix_diff_exitcode.txt new file mode 100644 index 00000000000000..2622c0265b6ca4 --- /dev/null +++ b/src/cmd/go/testdata/script/fix_diff_exitcode.txt @@ -0,0 +1,36 @@ +# Test that go fix -diff exits with non-zero status when diffs exist, +# and exits with zero status when no diffs are needed. +# This is consistent with gofmt -d (#46289) and go mod tidy -diff (#27005). + +# When the source needs fixes, go fix -diff should print the diff +# and exit with a non-zero code. +! go fix -diff example.com/needsfix +stdout 'net.JoinHostPort' + +# When the source is already clean, go fix -diff should print nothing +# and exit with a zero code. +go fix -diff example.com/clean +! stdout . + +-- go.mod -- +module example.com +go 1.26 + +-- needsfix/x.go -- +package needsfix + +import ( + "fmt" + "net" +) + +var s string +var _, _ = net.Dial("tcp", fmt.Sprintf("%s:%d", s, 80)) + +-- clean/x.go -- +package clean + +import "net" + +var s string +var _, _ = net.Dial("tcp", net.JoinHostPort(s, "80")) diff --git a/src/cmd/go/testdata/script/fix_suite.txt b/src/cmd/go/testdata/script/fix_suite.txt index 455629dc172f30..28ef96e4d1cacd 100644 --- a/src/cmd/go/testdata/script/fix_suite.txt +++ b/src/cmd/go/testdata/script/fix_suite.txt @@ -5,9 +5,9 @@ # Each assertion matches the expected diff. # # Tip: to see the actual stdout, -# temporarily prefix the go command with "! ". +# temporarily remove the "! " prefix from the go command. -go fix -diff example.com/x +! go fix -diff example.com/x # buildtag stdout '-// \+build go1.26' diff --git a/src/cmd/go/testdata/script/fix_vendor.txt b/src/cmd/go/testdata/script/fix_vendor.txt new file mode 100644 index 00000000000000..b1ee1975dbb9b3 --- /dev/null +++ b/src/cmd/go/testdata/script/fix_vendor.txt @@ -0,0 +1,44 @@ +# Test that go fix skips fixes to non-main and/or vendored packages. +# (It uses the interface{} -> any modernizer.) + +# Create vendor tree programmatically to avoid +# having to hardcode sums in this txtar archive. +go mod vendor + +# Show fixes on two packages, one in the main module +# and one in a vendored dependency. +# Only the main one (a) is shown. Diff => nonzero exit. +! go fix -diff example.com/a example.com/b +stdout 'a[/\\]a.go' +stdout '\-var _ interface\{\}' +stdout '\+var _ any' +! stdout 'b[/\\]b.go' + +# Apply fixes to the same two packages. +# Only the main module was modified. +go fix example.com/a example.com/b +grep 'var _ any' a/a.go +grep 'var _ interface{}' b/b.go +grep 'var _ interface{}' vendor/example.com/b/b.go + +-- go.mod -- +module example.com +go 1.26 + +require "example.com/b" v0.0.0 +replace "example.com/b" => ./b + +-- a/a.go -- +package a + +import _ "example.com/b" + +var _ interface{} + +-- b/go.mod -- +module example.com/b + +-- b/b.go -- +package b + +var _ interface{} diff --git a/src/cmd/go/testdata/script/get_404_meta.txt b/src/cmd/go/testdata/script/get_404_meta.txt index 7665155a4440bb..5f4f41170e1fe2 100644 --- a/src/cmd/go/testdata/script/get_404_meta.txt +++ b/src/cmd/go/testdata/script/get_404_meta.txt @@ -1,15 +1,22 @@ # golang.org/issue/13037: 'go get' was not parsing tags in 404 served over HTTPS. -[!net:bazil.org] skip +[short] skip [!git] skip -env GONOSUMDB=bazil.org,github.com,golang.org +env GONOSUMDB=vcs-test.golang.org env GO111MODULE=on env GOPROXY=direct -go get bazil.org/fuse/fs/fstestutil - +go get -x vcs-test.golang.org/go/get_404_meta +stderr 'get https://vcs-test.golang.org/go/get_404_meta\?go-get=1: 404 Not Found' +cmp go.mod go.mod.want -- go.mod -- module m go 1.18 +-- go.mod.want -- +module m + +go 1.18 + +require vcs-test.golang.org/go/get_404_meta v0.0.0-20170922010558-fc3a09f3dc5c // indirect \ No newline at end of file diff --git a/src/cmd/go/testdata/script/get_insecure.txt b/src/cmd/go/testdata/script/get_insecure.txt index f29ec2daed3587..0a2438038ffcc8 100644 --- a/src/cmd/go/testdata/script/get_insecure.txt +++ b/src/cmd/go/testdata/script/get_insecure.txt @@ -1,4 +1,5 @@ -[!net:insecure.go-get-issue-15410.appspot.com] skip +# Test for #15410 +[short] skip 'builds a go program and a git repo' [!git] skip env PATH=$WORK/tmp/bin${:}$PATH @@ -9,24 +10,23 @@ env GOPATH=$WORK/m/gp mkdir $WORK/m cp module_file $WORK/m/go.mod cd $WORK/m -env GO111MODULE=on -env GOPROXY='' +env GOPROXY=${GOPROXY},direct -# Modules: Try go get -d of HTTP-only repo (should fail). -! go get -d insecure.go-get-issue-15410.appspot.com/pkg/p +# Modules: Try go get of HTTP-only repo (should fail). +! go get -d vcs-test.golang.org/insecure/go/insecure@6fecd21 # Modules: Try again with GOINSECURE (should succeed). -env GOINSECURE=insecure.go-get-issue-15410.appspot.com -env GONOSUMDB=insecure.go-get-issue-15410.appspot.com -go get -d insecure.go-get-issue-15410.appspot.com/pkg/p +env GOINSECURE=vcs-test.golang.org/insecure/go/insecure +env GONOSUMDB=vcs-test.golang.org/insecure +go get -d vcs-test.golang.org/insecure/go/insecure@6fecd21 # Modules: Try updating without GOINSECURE (should fail). env GOINSECURE='' env GONOSUMDB='' -! go get -d -u -f insecure.go-get-issue-15410.appspot.com/pkg/p +! go get -d -u -f vcs-test.golang.org/insecure/go/insecure@6fecd21 go list -m ... -stdout 'insecure.go-get-issue' +stdout 'vcs-test.golang.org/insecure/go/insecure' -- ssh.go -- // stub out uses of ssh by go get diff --git a/src/cmd/go/testdata/script/get_issue53955.txt b/src/cmd/go/testdata/script/get_issue53955.txt index 685c6facaa93b7..afd2c1cccd795c 100644 --- a/src/cmd/go/testdata/script/get_issue53955.txt +++ b/src/cmd/go/testdata/script/get_issue53955.txt @@ -5,7 +5,6 @@ [short] skip 'constructs a local git repo' [!git] skip -[!net:github.com] skip 'does not actually use github.com because of insteadOf, but silence network check just in case' # Redirect git to a test-specific .gitconfig. # GIT_CONFIG_GLOBAL suffices for git 2.32.0 and newer. diff --git a/src/cmd/go/testdata/script/get_panic_issue75251.txt b/src/cmd/go/testdata/script/get_panic_issue75251.txt index 2cc3f3a9c45caa..00d019f8654f93 100644 --- a/src/cmd/go/testdata/script/get_panic_issue75251.txt +++ b/src/cmd/go/testdata/script/get_panic_issue75251.txt @@ -5,7 +5,7 @@ go mod init m ! go get golang.org/x/net/http/httpgutsÿv0.43.0 # contains 0xff byte ! stderr panic -stderr 'malformed module path' +stderr 'module golang.org/x/net@upgrade found.*but does not contain package golang.org/x/net/http/httpguts.v0.43.0' ! go get golang.org/x/net/http/httpgutsÿ@v0.43.0 # contains 0xff byte ! stderr panic diff --git a/src/cmd/go/testdata/script/get_tool_issue74691.txt b/src/cmd/go/testdata/script/get_tool_issue74691.txt new file mode 100644 index 00000000000000..44617ffe34fb16 --- /dev/null +++ b/src/cmd/go/testdata/script/get_tool_issue74691.txt @@ -0,0 +1,13 @@ +# Regression test for https://go.dev/issue/74691. + +go mod init gonzo +go get k8s.io/klog/v2@v2.130.1 +go mod tidy +go build ./... +go get -tool github.com/golangci/golangci-lint/v2/cmd/golangci-lint +go build ./... + +-- main.go -- +package main +import _ "k8s.io/klog/v2" +func main() {} diff --git a/src/cmd/go/testdata/script/get_version_error_44810.txt b/src/cmd/go/testdata/script/get_version_error_44810.txt new file mode 100644 index 00000000000000..37c7b8e4be0b4a --- /dev/null +++ b/src/cmd/go/testdata/script/get_version_error_44810.txt @@ -0,0 +1,10 @@ +# Issue #44810: go get should not produce unnecessarily repetitive +# "invalid version" error messages. + +go mod init m + +# A version string containing a slash should produce a concise error +# without repeating the version information multiple times. +! go get example.com/mod@branch/with/slash +stderr '^go: example.com/mod@branch/with/slash: invalid version: disallowed version string$' +! stderr 'version "branch/with/slash" invalid' diff --git a/src/cmd/go/testdata/script/godebug_default.txt b/src/cmd/go/testdata/script/godebug_default.txt index fecdcdb6b55c39..fdde0c41e91c54 100644 --- a/src/cmd/go/testdata/script/godebug_default.txt +++ b/src/cmd/go/testdata/script/godebug_default.txt @@ -48,27 +48,27 @@ rm go.work # Go 1.21 go.mod with godebug default=go1.20 rm go.work cp go.mod.21 go.mod -go mod edit -godebug default=go1.20 -godebug asynctimerchan=0 +go mod edit -godebug default=go1.20 -godebug randseednop=1 go list -f '{{.Module.GoVersion}} {{.DefaultGODEBUG}}' stdout panicnil=1 -stdout asynctimerchan=0 +stdout randseednop=1 # Go 1.21 go.work with godebug default=go1.20 cp go.work.21 go.work go list -f '{{.Module.GoVersion}} {{.DefaultGODEBUG}}' ! stdout panicnil # go.work wins -stdout asynctimerchan=1 # go.work wins -go work edit -godebug default=go1.20 -godebug asynctimerchan=0 +stdout randseednop=0 # go.work wins +go work edit -godebug default=go1.20 -godebug randseednop=1 go list -f '{{.Module.GoVersion}} {{.DefaultGODEBUG}}' stdout panicnil=1 -stdout asynctimerchan=0 +stdout randseednop=1 rm go.work # Go 1.21 go.mod with //go:debug default=go1.20 in program cp go.mod.21 go.mod go list -tags godebug -f '{{.Module.GoVersion}} {{.DefaultGODEBUG}}' stdout panicnil=1 -stdout asynctimerchan=0 +stdout randseednop=1 # Invalid //go:debug line should be diagnosed at build. ! go build -tags godebugbad @@ -79,10 +79,10 @@ stderr 'invalid //go:debug: value contains space' # Programs in Go 1.21 work module should trigger run-time error. cp go.mod.21 go.mod ! go run . -stderr 'panic: panic called with nil argument' +stderr 'runtime error: panic called with nil argument' ! go run rsc.io/panicnil -stderr 'panic: panic called with nil argument' +stderr 'runtime error: panic called with nil argument' # Programs in Go 1.20 work module use old panic nil behavior. cp go.mod.20 go.mod @@ -99,7 +99,7 @@ stderr 'panic: nil' rm go.mod ! go run rsc.io/panicnil@v1.1.0 -stderr 'panic: panic called with nil argument' +stderr 'runtime error: panic called with nil argument' -- go.work.21 -- go 1.21 @@ -137,13 +137,13 @@ func main() { -- godebug.go -- //go:build godebug //go:debug default=go1.20 -//go:debug asynctimerchan=0 +//go:debug randseednop=1 package main -- godebugbad.go -- //go:build godebugbad -//go:debug default=go1.20 asynctimerchan=0 +//go:debug default=go1.20 randseednop=1 package main diff --git a/src/cmd/go/testdata/script/godebug_default_gopath.txt b/src/cmd/go/testdata/script/godebug_default_gopath.txt new file mode 100644 index 00000000000000..2bdf8369ae8bbd --- /dev/null +++ b/src/cmd/go/testdata/script/godebug_default_gopath.txt @@ -0,0 +1,9 @@ +env GO111MODULE=off + +go list -f '{{.DefaultGODEBUG}}' +! stdout netedns0 + +-- foo.go -- +package main + +func main() {} \ No newline at end of file diff --git a/src/cmd/go/testdata/script/godebug_removed.txt b/src/cmd/go/testdata/script/godebug_removed.txt new file mode 100644 index 00000000000000..71a358b581975f --- /dev/null +++ b/src/cmd/go/testdata/script/godebug_removed.txt @@ -0,0 +1,105 @@ +# The gotypesalias GODEBUG setting was introduced with Go 1.22 and removed +# with Go 1.27 but the GODEBUG behavior of the tool chain is independent of +# the module version; only the tool version matters (go.dev/issue/76163). +cp go.mod.20 go.mod + +# Go 1.20 must accept the removed GODEBUG gotypesalias with default value +go build -n godebugok.go +! stderr 'removed GODEBUG "gotypesalias" set to old value "0"' + +# This also applies to go vet +go vet godebugok.go +! stderr . + +# Go 1.20 must not accept the removed GODEBUG gotypesalias with old value +! go build -n godebugold.go +stderr 'removed GODEBUG "gotypesalias" set to old value "0"' + +! go vet godebugold.go +stderr 'removed GODEBUG "gotypesalias" set to old value "0"' + +# If the GODEBUG setting is valid in the .mod file the build succeeds. +cp go.mod.20.godebugok go.mod +go build -n main.go +! stderr 'removed GODEBUG "gotypesalias" set to old value "0"' + +# In this case, setting an invalid value in the .go file leads to build failure. +! go build -n godebugold.go +stderr 'removed GODEBUG "gotypesalias" set to old value "0"' + +# If the GODEBUG setting is invalid in the .mod file the build fails. +cp go.mod.20.godebugold go.mod +! go build -n main.go +stderr 'removed GODEBUG "gotypesalias" set to old value "0"' + +# In this case, setting a valid value in the .go file does not remedy the failure. +! go build -n godebugok.go +stderr 'removed GODEBUG "gotypesalias" set to old value "0"' + +[short] skip + +# Using a removed GODEBUG with old value in the environment causes panic at startup. +cp go.mod.20 go.mod +env GODEBUG=gotypesalias=0 +! go run printgodebug.go +stderr 'removed GODEBUG "gotypesalias" set to old value "0"' + +# Using a removed GODEBUG with default value in the environment is ok. +env GODEBUG=gotypesalias=1 +go run printgodebug.go +stdout gotypesalias=1 + +# Setting a removed GODEBUG with old value in the environment during runtime is not guarded against. +go run setgodebug.go +stdout gotypesalias=0 + +-- go.mod.20 -- +go 1.20 +module m + +-- go.mod.20.godebugok -- +go 1.20 +module m +godebug gotypesalias=1 + +-- go.mod.20.godebugold -- +go 1.20 +module m +godebug gotypesalias=0 + +-- main.go -- +package main +func main() {} + +-- godebugok.go -- +//go:debug gotypesalias=1 + +package main +func main() {} + +-- godebugold.go -- +//go:debug gotypesalias=0 + +package main +func main() {} + +-- printgodebug.go -- +package main + +import "fmt" +import "os" + +func main() { + fmt.Println(os.Getenv("GODEBUG")) +} + +-- setgodebug.go -- +package main + +import "fmt" +import "os" + +func main() { + os.Setenv("GODEBUG", "gotypesalias=0") + fmt.Println(os.Getenv("GODEBUG")) +} diff --git a/src/cmd/go/testdata/script/gofmt_with_symlink.txt b/src/cmd/go/testdata/script/gofmt_with_symlink.txt new file mode 100644 index 00000000000000..bc51feff164c03 --- /dev/null +++ b/src/cmd/go/testdata/script/gofmt_with_symlink.txt @@ -0,0 +1,31 @@ +# Test that gofmt-ing a symlink works correctly. See #79735. + +# Skip on systems without unix-style symlinks +[GOOS:windows] skip + +cd $WORK/a +cp issue-original.go issue-expected.go +exec go fmt issue-expected.go +! cmp -q issue-expected.go issue-original.go + +# Create that symlink. +exec ln -s issue-original.go issue-symlink.go + +# Now go fmt it. +exec go fmt issue-symlink.go + +# Ensure that the symlinked file is equal to the expected. +cmp issue-expected.go issue-symlink.go + +# Our source code and setup. +-- $WORK/a/go.mod -- +module gofmt_symlink + +-- $WORK/a/issue-original.go -- +package main; + +import "fmt" + +func main() { + fmt.Println( "Hello, world!!!" ) +} diff --git a/src/cmd/go/testdata/script/gotoolchain_get_upgrade.txt b/src/cmd/go/testdata/script/gotoolchain_get_upgrade.txt new file mode 100644 index 00000000000000..b8da7a7dc2ee88 --- /dev/null +++ b/src/cmd/go/testdata/script/gotoolchain_get_upgrade.txt @@ -0,0 +1,39 @@ +env TESTGO_VERSION=go1.21 +env TESTGO_VERSION_SWITCH=switch + +# Control case: get module@version should switch toolchain versions. +cp go.mod.orig go.mod +go get example.com/increasegoreq@v0.0.2 +stderr 'go: module example.com/increasegoreq@v0.0.2 requires go >= 1.23; switching to go1.23.9' +cmp go.mod go.mod.want + +# #79917: get ./... should also switch toolchain versions. +cp go.mod.orig go.mod +go get -u ./... +stderr 'go: module example.com/increasegoreq@v0.0.2 requires go >= 1.23; switching to go1.23.9' +cmp go.mod go.mod.want + +# go get -u without arguments (default to .) should also switch toolchains +cp go.mod.orig go.mod +go get -u +stderr 'go: module example.com/increasegoreq@v0.0.2 requires go >= 1.23; switching to go1.23.9' +cmp go.mod go.mod.want + +-- go.mod.orig -- +module m + +go 1.21 + +require example.com/increasegoreq v0.0.1 +-- go.mod.want -- +module m + +go 1.23 + +require example.com/increasegoreq v0.0.2 +-- main.go -- +package main + +import _ "example.com/increasegoreq" + +func main() {} diff --git a/src/cmd/go/testdata/script/gotoolchain_net.txt b/src/cmd/go/testdata/script/gotoolchain_net.txt index 1d6473c6f945c1..6edabcb9d57600 100644 --- a/src/cmd/go/testdata/script/gotoolchain_net.txt +++ b/src/cmd/go/testdata/script/gotoolchain_net.txt @@ -45,26 +45,3 @@ rm $GOPATH/pkg/mod/cache/download/sumdb stderr 'panic: use of network' # test catches network access env GOSUMDB=$oldsumdb -# Test a real GOTOOLCHAIN -[short] skip -[!net:golang.org] skip -[!net:sum.golang.org] skip -[!GOOS:darwin] [!GOOS:windows] [!GOOS:linux] skip -[!GOARCH:amd64] [!GOARCH:arm64] skip - -env GOPROXY= -[go-builder] env GOSUMDB= -[!go-builder] env GOSUMDB=sum.golang.org # Set explicitly in case GOROOT/go.env is modified. -env GOTOOLCHAIN=go1.20.1 - - # Avoid resolving a "go1.20.1" from the user's real $PATH. - # That would not only cause the "downloading go1.20.1" message - # to be suppressed, but may spuriously fail: - # golang.org/dl/go1.20.1 expects to find its GOROOT in $HOME/sdk, - # but the script environment sets HOME=/no-home. -env PATH= -env path= - -go version -stderr '^go: downloading go1.20.1 ' -stdout go1.20.1 diff --git a/src/cmd/go/testdata/script/gotoolchain_switch_gosum.txt b/src/cmd/go/testdata/script/gotoolchain_switch_gosum.txt new file mode 100644 index 00000000000000..aaac9a9b816f1b --- /dev/null +++ b/src/cmd/go/testdata/script/gotoolchain_switch_gosum.txt @@ -0,0 +1,40 @@ +# A toolchain switch triggered by a dependency must verify the downloaded +# toolchain against the checksum database, even when the main module's go.sum +# already lists a matching entry for golang.org/toolchain. + +[!exec:/bin/sh] skip 'the fake proxy serves shell scripts instead of binaries' +env TESTGO_VERSION=go1.21.0 +env GOTOOLCHAIN=local +env sumdb=$GOSUMDB +env proxy=$GOPROXY +env dbname=localhost.localdev/sumdb + +# Record the toolchain in go.sum, then drop it from go.mod so that only +# the go.sum line remains, as it would in an attacker-supplied repository. +go get golang.org/toolchain@v0.0.1-go1.999testmod.$GOOS-$GOARCH +go mod edit -droprequire golang.org/toolchain +grep '^golang.org/toolchain v0.0.1-go1.999testmod.[a-z0-9\-]* h1:' go.sum +go mod edit -require rsc.io/future@v1.0.0 + +# Point at a checksum database that disagrees with go.sum and the download. +# GONOSUMDB keeps rsc.io/future out of the way; it does not apply to the toolchain. +# Clear cached lookups and the cached tree head so the server is consulted. +go clean -modcache +rm $GOPATH/pkg/sumdb/$dbname/latest +env GOTOOLCHAIN=auto +env GONOSUMDB=rsc.io +env GOSUMDB=$sumdb' '$proxy/sumdb-wrong +! go get . +stderr 'switching to go1.999testmod' +stderr 'golang.org/toolchain@v0.0.1-go1.999testmod.[a-z0-9\-]*: verifying (module|go.mod): checksum mismatch' +stderr 'localhost.localdev/sumdb: h1:wrong' +stderr 'SECURITY ERROR' + +-- go.mod -- +module example + +go 1.21 +-- example.go -- +package example + +import _ "rsc.io/future" diff --git a/src/cmd/go/testdata/script/gotoolchain_version.txt b/src/cmd/go/testdata/script/gotoolchain_version.txt index e0736ff980c5cc..70a1c77635c4ed 100644 --- a/src/cmd/go/testdata/script/gotoolchain_version.txt +++ b/src/cmd/go/testdata/script/gotoolchain_version.txt @@ -1,16 +1,3 @@ -[!net:proxy.golang.org] skip - - # In the Go project's official release GOPROXY defaults to proxy.golang.org, - # but it may be changed in GOROOT/go.env (such as in third-party - # distributions). - # - # Make sure it is in use here, because the server for releases not served - # through the proxy (https://golang.org/toolchain?go-get=1) currently only - # serves the latest patch release for each of the supported stable releases. - -[go-builder] env GOPROXY= -[!go-builder] env GOPROXY=https://proxy.golang.org - go list -m -versions go stdout 1.20.1 # among others stdout 1.19rc2 diff --git a/src/cmd/go/testdata/script/gotoolchain_work_issue76728.txt b/src/cmd/go/testdata/script/gotoolchain_work_issue76728.txt new file mode 100644 index 00000000000000..e1a34c24977c62 --- /dev/null +++ b/src/cmd/go/testdata/script/gotoolchain_work_issue76728.txt @@ -0,0 +1,13 @@ +# #76728: with GO111MODULE=auto, we didn't switch toolchains properly +# in a workspace. + +env GO111MODULE=auto +env TESTGO_VERSION=go1.23.0 +env TESTGO_VERSION_SWITCH=switch + +go version +! stdout 1\.23\.0 +stdout 1\.24\.0 + +-- go.work -- +go 1.24.0 \ No newline at end of file diff --git a/src/cmd/go/testdata/script/govcs.txt b/src/cmd/go/testdata/script/govcs.txt index 876f6065bc54b3..3d3fdd4504f2e4 100644 --- a/src/cmd/go/testdata/script/govcs.txt +++ b/src/cmd/go/testdata/script/govcs.txt @@ -58,16 +58,10 @@ env GOVCS= ! go get rsc.io/nonexist.fossil/hello stderr '^go: rsc.io/nonexist.fossil/hello: GOVCS disallows using fossil for public rsc.io/nonexist.fossil; see ''go help vcs''$' -# bzr is disallowed by default -env GOPRIVATE= -env GOVCS= -! go get rsc.io/nonexist.bzr/hello -stderr '^go: rsc.io/nonexist.bzr/hello: GOVCS disallows using bzr for public rsc.io/nonexist.bzr; see ''go help vcs''$' - # git is OK by default env GOVCS= env GONOSUMDB='*' -[net:rsc.io] [git] [!short] go get rsc.io/sampler +[git] [!short] go get vcs-test.golang.org/git/hello.git # hg is OK by default env GOVCS= diff --git a/src/cmd/go/testdata/script/issue_63696.txt b/src/cmd/go/testdata/script/issue_63696.txt new file mode 100644 index 00000000000000..24de3898f02de8 --- /dev/null +++ b/src/cmd/go/testdata/script/issue_63696.txt @@ -0,0 +1,95 @@ +go mod init m +go get rsc.io/quote@latest +go doc rsc.io/quote +cmp stdout want-latest.txt +go doc rsc.io/quote@latest +cmp stdout want-latest.txt +go doc rsc.io/quote@v1.0.0 +cmp stdout want-1.0.0.txt +go doc rsc.io/quote@v1.1.0 +cmp stdout want-1.1.0.txt +go doc rsc.io/quote@v1.2.0 +cmp stdout want-1.2.0.txt +# Test short format +go doc quote@latest +cmp stdout want-latest.txt +go doc quote@v1.0.0 +cmp stdout want-1.0.0.txt +go doc quote@v1.1.0 +cmp stdout want-1.1.0.txt +go doc quote@v1.2.0 +cmp stdout want-1.2.0.txt +go doc quote +cmp stdout want-latest.txt +go doc quote@v1.0.0 Hello +cmp stdout hello-1.0.0.txt +go doc quote@v1.1.0 Glass +cmp stdout glass-1.1.0.txt +go doc quote@v1.2.0 Go +cmp stdout go-1.2.0.txt +go doc quote@v1.3.0 Opt +cmp stdout opt-1.3.0.txt +-- main.go -- +package main + +import ( + "fmt" + "rsc.io/quote" +) +func main() { + fmt.Println(quote.Hello()) +} +-- want-latest.txt -- +package quote // import "rsc.io/quote" + +Package quote collects pithy sayings. + +func Glass() string +func Go() string +func Hello() string +func Opt() string +-- want-1.0.0.txt -- +package quote // import "rsc.io/quote" + +Package quote collects pithy sayings. + +func Hello() string +-- want-1.1.0.txt -- +package quote // import "rsc.io/quote" + +Package quote collects pithy sayings. + +func Glass() string +func Hello() string +-- want-1.2.0.txt -- +package quote // import "rsc.io/quote" + +Package quote collects pithy sayings. + +func Glass() string +func Go() string +func Hello() string +-- hello-1.0.0.txt -- +package quote // import "rsc.io/quote" + +func Hello() string + Hello returns a greeting. + +-- glass-1.1.0.txt -- +package quote // import "rsc.io/quote" + +func Glass() string + Glass returns a useful phrase for world travelers. + +-- go-1.2.0.txt -- +package quote // import "rsc.io/quote" + +func Go() string + Go returns a Go proverb. + +-- opt-1.3.0.txt -- +package quote // import "rsc.io/quote" + +func Opt() string + Opt returns an optimization truth. + diff --git a/src/cmd/go/testdata/script/list_empty_import.txt b/src/cmd/go/testdata/script/list_empty_import.txt index 4d76f098b97b36..2a18107b67bd38 100644 --- a/src/cmd/go/testdata/script/list_empty_import.txt +++ b/src/cmd/go/testdata/script/list_empty_import.txt @@ -3,6 +3,11 @@ stderr 'invalid import path' ! stderr panic +! go list '' +stderr 'invalid package' +! go list -m '' +stderr 'invalid package' + -- a.go -- package a diff --git a/src/cmd/go/testdata/script/list_empty_importpath.txt b/src/cmd/go/testdata/script/list_empty_importpath.txt index 4ddf6b36d26881..0960a7795d12ea 100644 --- a/src/cmd/go/testdata/script/list_empty_importpath.txt +++ b/src/cmd/go/testdata/script/list_empty_importpath.txt @@ -1,12 +1,6 @@ ! go list all ! stderr 'panic' -[!GOOS:windows] [!GOOS:solaris] stderr 'invalid import path' -# #73976: Allow 'no errors' on Windows and Solaris until issue -# is resolved to prevent flakes. 'no errors' is printed by -# empty scanner.ErrorList errors so that's probably where the -# message is coming from, though we don't know how. -[GOOS:windows] stderr 'invalid import path|no errors' -[GOOS:solaris] stderr 'invalid import path|no errors' +stderr 'invalid import path' # go list produces a package for 'p' but not for '' go list -e all diff --git a/src/cmd/go/testdata/script/list_std_vendor.txt b/src/cmd/go/testdata/script/list_std_vendor.txt index 834babe674d9d9..06674ff41ecab8 100644 --- a/src/cmd/go/testdata/script/list_std_vendor.txt +++ b/src/cmd/go/testdata/script/list_std_vendor.txt @@ -2,6 +2,8 @@ # dependencies regardless of whether they are listed from within or outside # GOROOT/src. +env GOROOT=$WORK/goroot + # Control case: net, viewed from outside the 'std' module, # should depend on vendor/golang.org/… instead of golang.org/…. @@ -25,9 +27,30 @@ cmp stdout $WORK/net-deps.txt # However, 'go mod' and 'go get' subcommands should report the original module # dependencies, not the vendored packages. -[!net:golang.org] stop - -env GOPROXY= env GOWORK=off go mod why -m golang.org/x/net stdout '^# golang.org/x/net\nnet\ngolang.org/x/net' + +-- $WORK/goroot/src/go.mod -- +module std + +go 1.26 + +require golang.org/x/net v0.1.0 +-- $WORK/goroot/src/go.sum -- +golang.org/x/net v0.1.0 h1:iUcD2VNMwNi3BZMUg2qIGo4aAass7E0R4eQNGK3hvc0= +golang.org/x/net v0.1.0/go.mod h1:mL1N/T3taQHkDXs73rZJwtUhF3w3ftmwwsq0BUmARs4= +-- $WORK/goroot/src/vendor/modules.txt -- +# golang.org/x/net v0.1.0 +## explicit +golang.org/x/net/dns/dnsmessage +-- $WORK/goroot/src/vendor/modules.txt -- +# golang.org/x/net v0.1.0 +## explicit +golang.org/x/net/dns/dnsmessage +-- $WORK/goroot/src/vendor/golang.org/x/net/dns/dnsmessage/dnsmessage.go -- +package dnsmessage +-- $WORK/goroot/src/net/net.go -- +package net + +import _ "golang.org/x/net/dns/dnsmessage" diff --git a/src/cmd/go/testdata/script/list_template_context_function.txt b/src/cmd/go/testdata/script/list_template_context_function.txt new file mode 100644 index 00000000000000..70c47c87f8e27c --- /dev/null +++ b/src/cmd/go/testdata/script/list_template_context_function.txt @@ -0,0 +1,15 @@ +# This is a script test conversion of TestListTemplateContextFunction +# originally added in CL 20010, which fixed #14547. +# Test the ability to use the build context in the go list template. + +go list -f '{{context.GOARCH}} {{context.GOOS}} {{context.GOROOT}} {{context.GOPATH}}' +cmpenv stdout want.txt + +go list -f '{{context.CgoEnabled}} {{context.UseAllFiles}} {{context.Compiler}} {{context.BuildTags}} {{context.ReleaseTags}} {{context.InstallSuffix}}' + +-- go.mod -- +module foo +-- foo.go -- +package foo +-- want.txt -- +$GOARCH $GOOS $GOROOT $GOPATH diff --git a/src/cmd/go/testdata/script/list_test.txt b/src/cmd/go/testdata/script/list_test.txt new file mode 100644 index 00000000000000..57104891c86538 --- /dev/null +++ b/src/cmd/go/testdata/script/list_test.txt @@ -0,0 +1,33 @@ +# This is a script test conversion of TestGoListTest which was added in +# CL 107916, which added support for go list -test. +# Test the behavior of go list -test. + +[compiler:gccgo] skip 'gccgo does not have standard packages' + +go list -test -deps strings +stdout '^strings.test$' # test main +stdout '^strings$' # real strings +stdout '^strings \[strings.test\]$' # test copy of strings +stdout 'testing \[strings.test\]$' # test copy of testing +! stdout ^testing$ # should not have real testing + +go list -test strings +stdout '^strings.test$' # test main +stdout '^strings$' # real strings +stdout '^strings \[strings.test\]$' # test copy of strings +! stdout '^testing \[strings.test\]$' # should not have test copy of testing +! stdout '^testing$' # should not have real testing + +go list -test cmd/buildid cmd/gofmt +stdout '^cmd/buildid$' # cmd/buildid +stdout '^cmd/gofmt$' # cmd/gofmt +stdout '^cmd/gofmt\.test$' # cmd/gofmt test +! stdout '^cmd/buildid\.test$' # should not have cmd/buildid test +! stdout '^testing' # should not have real testing + +go list -test runtime/cgo +stdout '^runtime/cgo$' # runtime/cgo + +go list -deps -f '{{if .DepOnly}}{{.ImportPath}}{{end}}' sort +stdout '^internal/reflectlite$' # internal/reflectlite +! stdout '^sort' # should not have sort diff --git a/src/cmd/go/testdata/script/list_toolexec_stderr_issue22588.txt b/src/cmd/go/testdata/script/list_toolexec_stderr_issue22588.txt new file mode 100644 index 00000000000000..dd2eaed2a1f1b2 --- /dev/null +++ b/src/cmd/go/testdata/script/list_toolexec_stderr_issue22588.txt @@ -0,0 +1,11 @@ +# This is a script test conversion of TestIssue22588 which was added in CL 76017. +# Test that the stderr of a tool run under toolexec doesn't affect caching. + +# Don't get confused by stderr coming from tools. +[!exec:/usr/bin/time] skip + +! stale runtime 'must be non-stale to compare staleness under -toolexec' + +go list -f '{{.Stale}}' runtime +go list -toolexec /usr/bin/time -f '{{.Stale}}' runtime +stdout 'false' # runtime should not be reported as stale \ No newline at end of file diff --git a/src/cmd/go/testdata/script/mod_doc.txt b/src/cmd/go/testdata/script/mod_doc.txt index bf0a19d770bfb5..7da8f036eb5f82 100644 --- a/src/cmd/go/testdata/script/mod_doc.txt +++ b/src/cmd/go/testdata/script/mod_doc.txt @@ -8,6 +8,13 @@ env GOFLAGS=-mod=mod go doc y stdout 'Package y is.*alphabet' stdout 'import "x/y"' +go doc -short y.Yell +stdout '^func Yell\(\) string$' +! stdout 'Yell returns the final letter' +go doc -short y.Letter +stdout '^const Letter = "z"$' +go doc -short y.Alphabet +stdout '^type Alphabet struct\{\}$' go doc x/y stdout 'Package y is.*alphabet' ! go doc quote.Hello @@ -38,9 +45,8 @@ go doc rsc.io/quote stdout 'Package quote collects pithy sayings.' # Check that a sensible error message is printed when a package is not found. -env GOPROXY=off ! go doc example.com/hello -stderr '^doc: cannot find module providing package example.com/hello: module lookup disabled by GOPROXY=off$' +stderr 'doc: no required module provides package example.com/hello; to add it:\n\s+go get example.com/hello' # When in a module with a vendor directory, doc should use the vendored copies # of the packages. 'std' and 'cmd' are convenient examples of such modules. @@ -68,6 +74,17 @@ stdout '// import "vendor/golang.org/x/crypto/cryptobyte"' go doc cmd/vendor/golang.org/x/mod/modfile stdout '// import "cmd/vendor/golang.org/x/mod/modfile"' +# Not in a module and not in GOPATH +cd $WORK +go env GOMOD +stdout '(/dev/null|NUL)' + +go doc encoding/json +stdout '// import "encoding/json"' + +go doc json +stdout '// import "encoding/json"' + -- go.mod -- module x require rsc.io/quote v1.5.2 @@ -76,6 +93,13 @@ require rsc.io/quote v1.5.2 // Package y is the next to last package of the alphabet. package y +// Yell returns the final letter of the alphabet. +func Yell() string { return "z" } + +const Letter = "z" + +type Alphabet struct{} + -- x.go -- package x diff --git a/src/cmd/go/testdata/script/mod_download_git_bareRepository_sha256.txt b/src/cmd/go/testdata/script/mod_download_git_bareRepository_sha256.txt index 9e8dc3c0150d7f..2f391e200e77fa 100644 --- a/src/cmd/go/testdata/script/mod_download_git_bareRepository_sha256.txt +++ b/src/cmd/go/testdata/script/mod_download_git_bareRepository_sha256.txt @@ -1,5 +1,6 @@ [short] skip [!git] skip +[!git-sha256] skip # This is a git sha256-mode copy of mod_download_git_bareRepository diff --git a/src/cmd/go/testdata/script/mod_download_hash.txt b/src/cmd/go/testdata/script/mod_download_hash.txt index 5677e69a5d5349..e23cb63606aa84 100644 --- a/src/cmd/go/testdata/script/mod_download_hash.txt +++ b/src/cmd/go/testdata/script/mod_download_hash.txt @@ -1,20 +1,18 @@ -env GO111MODULE=on - # Testing mod download with non semantic versions; turn off proxy. -[!net:rsc.io] skip +[short] skip [!git] skip env GOPROXY=direct env GOSUMDB=off -go mod download rsc.io/quote@a91498bed0a73d4bb9c1fb2597925f7883bc40a7 -exists $GOPATH/pkg/mod/cache/download/rsc.io/quote/@v/v1.5.3-0.20180709162918-a91498bed0a7.info -exists $GOPATH/pkg/mod/cache/download/rsc.io/quote/@v/v1.5.3-0.20180709162918-a91498bed0a7.mod -exists $GOPATH/pkg/mod/cache/download/rsc.io/quote/@v/v1.5.3-0.20180709162918-a91498bed0a7.zip +go mod download vcs-test.golang.org/git/hello.git@fc3a09f +exists $GOPATH/pkg/mod/cache/download/vcs-test.golang.org/git/hello.git/@v/v0.0.0-20170922010558-fc3a09f3dc5c.info +exists $GOPATH/pkg/mod/cache/download/vcs-test.golang.org/git/hello.git/@v/v0.0.0-20170922010558-fc3a09f3dc5c.mod +exists $GOPATH/pkg/mod/cache/download/vcs-test.golang.org/git/hello.git/@v/v0.0.0-20170922010558-fc3a09f3dc5c.zip -go mod download rsc.io/quote@master -exists $GOPATH/pkg/mod/cache/download/rsc.io/quote/@v/v1.5.3-0.20180709162918-a91498bed0a7.info -exists $GOPATH/pkg/mod/cache/download/rsc.io/quote/@v/v1.5.3-0.20180709162918-a91498bed0a7.mod -exists $GOPATH/pkg/mod/cache/download/rsc.io/quote/@v/v1.5.3-0.20180709162918-a91498bed0a7.zip +go mod download vcs-test.golang.org/git/hello.git@master +exists $GOPATH/pkg/mod/cache/download/vcs-test.golang.org/git/hello.git/@v/v0.0.0-20170922010558-fc3a09f3dc5c.info +exists $GOPATH/pkg/mod/cache/download/vcs-test.golang.org/git/hello.git/@v/v0.0.0-20170922010558-fc3a09f3dc5c.mod +exists $GOPATH/pkg/mod/cache/download/vcs-test.golang.org/git/hello.git/@v/v0.0.0-20170922010558-fc3a09f3dc5c.zip -- go.mod -- diff --git a/src/cmd/go/testdata/script/mod_download_issue51114.txt b/src/cmd/go/testdata/script/mod_download_issue51114.txt index a28d467bb8b1ce..d5515463f4bdc7 100644 --- a/src/cmd/go/testdata/script/mod_download_issue51114.txt +++ b/src/cmd/go/testdata/script/mod_download_issue51114.txt @@ -1,29 +1,14 @@ -[!net:github.com] skip +[short] skip [!git] skip -# Redirect git to a test-specific .gitconfig. -# GIT_CONFIG_GLOBAL suffices for git 2.32.0 and newer. -# For older git versions we also set $HOME. -env GIT_CONFIG_GLOBAL=$WORK${/}home${/}gopher${/}.gitconfig -env HOME=$WORK${/}home${/}gopher -exec git config --global --show-origin user.name -stdout 'Go Gopher' - env GOPROXY=direct ! go mod download -stderr '^go: github\.com/golang/notexist/subdir@v0.1.0: reading github\.com/golang/notexist/subdir/go\.mod at revision subdir/v0\.1\.0: ' +stderr '^go: vcs-test.golang.org/notexist.git/subdir@v0.1.0: reading vcs-test\.golang\.org/notexist.git/subdir/go\.mod at revision subdir/v0\.1\.0: ' -- go.mod -- module test go 1.18 -require github.com/golang/notexist/subdir v0.1.0 - --- $WORK/home/gopher/.gitconfig -- -[user] - name = Go Gopher - email = gopher@golang.org -[url "git@github.com:"] - insteadOf = https://github.com/ +require vcs-test.golang.org/notexist.git/subdir v0.1.0 diff --git a/src/cmd/go/testdata/script/mod_download_private_vcs.txt b/src/cmd/go/testdata/script/mod_download_private_vcs.txt index 5c8d93a978d7fe..0e7f5558a0e339 100644 --- a/src/cmd/go/testdata/script/mod_download_private_vcs.txt +++ b/src/cmd/go/testdata/script/mod_download_private_vcs.txt @@ -1,7 +1,5 @@ -env GO111MODULE=on - # Testing stderr for git ls-remote; turn off proxy. -[!net:github.com] skip +[short] skip [!git] skip env GOPROXY=direct @@ -13,20 +11,20 @@ env HOME=$WORK${/}home${/}gopher exec git config --global --show-origin user.name stdout 'Go Gopher' -! go mod download github.com/golang/nonexist@latest +! go mod download vcs-test.golang.org/auth/githttp401.git@latest stderr 'Confirm the import path was entered correctly.' -stderr 'If this is a private repository, see https://golang.org/doc/faq#git_https for additional information.' +stderr 'If this is a private repository, see https://go.dev/doc/faq#git_https for additional information.' ! stdout . # Fetching a nonexistent commit should return an "unknown revision" # error message. -! go mod download github.com/golang/term@86186f3aba07ed0212cfb944f3398997d2d07c6b -stderr '^go: github.com/golang/term@86186f3aba07ed0212cfb944f3398997d2d07c6b: invalid version: unknown revision 86186f3aba07ed0212cfb944f3398997d2d07c6b$' +! go mod download vcs-test.golang.org/git/mainonly.git@86186f3aba07ed0212cfb944f3398997d2d07c6b +stderr '^go: vcs-test.golang.org/git/mainonly.git@86186f3aba07ed0212cfb944f3398997d2d07c6b: invalid version: unknown revision 86186f3aba07ed0212cfb944f3398997d2d07c6b$' ! stdout . -! go mod download github.com/golang/nonexist@master +! go mod download vcs-test.golang.org/auth/githttp401.git@master stderr '^Confirm the import path was entered correctly.$' -stderr '^If this is a private repository, see https://golang.org/doc/faq#git_https for additional information.$' +stderr '^If this is a private repository, see https://go.dev/doc/faq#git_https for additional information.$' ! stderr 'unknown revision' ! stdout . @@ -35,9 +33,9 @@ stderr '^If this is a private repository, see https://golang.org/doc/faq#git_htt # Test that Git clone errors will be shown to the user instead of a generic # "unknown revision" error. To do this we want to force git ls-remote to return # an error we don't already have special handling for. See golang/go#42751. -exec git config --global url.git@github.com.insteadOf https://github.com/ +exec git config --global url.git@vcs-test.golang.org:.insteadOf http://$TESTGO_VCSTEST_HOST/ env GIT_SSH_COMMAND=false -! go install github.com/golang/nonexist@master +! go install vcs-test.golang.org/auth/githttp401.git@master stderr 'fatal: Could not read from remote repository.' ! stderr 'unknown revision' ! stdout . diff --git a/src/cmd/go/testdata/script/mod_download_toolchain_gosum.txt b/src/cmd/go/testdata/script/mod_download_toolchain_gosum.txt new file mode 100644 index 00000000000000..9954fb263f7e7c --- /dev/null +++ b/src/cmd/go/testdata/script/mod_download_toolchain_gosum.txt @@ -0,0 +1,34 @@ +# A matching line in go.sum must not bypass checksum database verification +# for a downloaded toolchain, since useSumDB requires the checksum database +# for golang.org/toolchain even when GOSUMDB=off. + +env GOTOOLCHAIN=local +env sumdb=$GOSUMDB +env proxy=$GOPROXY +env dbname=localhost.localdev/sumdb + +go get golang.org/toolchain@v0.0.1-go1.999testmod.$GOOS-$GOARCH +grep '^golang.org/toolchain v0.0.1-go1.999testmod.[a-z0-9\-]* h1:' go.sum +grep '^golang.org/toolchain v0.0.1-go1.999testmod.[a-z0-9\-]*/go.mod h1:' go.sum + +# With the checksum database disabled, the matching go.sum entry +# must not be accepted on its own. +env GOSUMDB=off +! go mod download golang.org/toolchain +stderr 'checksum database disabled by GOSUMDB=off' + +# With a checksum database that disagrees with go.sum, the download +# must be rejected even though go.sum matches the downloaded bits. +# Clear cached lookups and the cached tree head so the server is consulted. +go clean -modcache +rm $GOPATH/pkg/sumdb/$dbname/latest +env GOSUMDB=$sumdb' '$proxy/sumdb-wrong +! go mod download golang.org/toolchain +stderr 'verifying (module|go.mod): checksum mismatch' +stderr 'localhost.localdev/sumdb: h1:wrong' +stderr 'SECURITY ERROR' + +-- go.mod -- +module example.com/m + +go 1.21 diff --git a/src/cmd/go/testdata/script/mod_edit.txt b/src/cmd/go/testdata/script/mod_edit.txt index 6b7dd2c2c5e21c..a0eac54375cc1f 100644 --- a/src/cmd/go/testdata/script/mod_edit.txt +++ b/src/cmd/go/testdata/script/mod_edit.txt @@ -204,9 +204,7 @@ require x.3 v1.99.0 "Low": "v1.3.0", "High": "v1.4.0" } - ], - "Tool": null, - "Ignore": null + ] } -- $WORK/go.mod.edit3 -- module x.x/y/z @@ -324,9 +322,6 @@ retract ( "Path": "x.x/y/z" }, "Go": "1.15", - "Require": null, - "Exclude": null, - "Replace": null, "Retract": [ { "Low": "v1.0.0", @@ -343,9 +338,7 @@ retract ( "High": "v1.0.2", "Rationale": "c" } - ], - "Tool": null, - "Ignore": null + ] } -- $WORK/go.mod.deprecation -- // Deprecated: and the new one is not ready yet @@ -355,26 +348,14 @@ module m "Module": { "Path": "m", "Deprecated": "and the new one is not ready yet" - }, - "Require": null, - "Exclude": null, - "Replace": null, - "Retract": null, - "Tool": null, - "Ignore": null + } } -- $WORK/go.mod.empty -- -- $WORK/go.mod.empty.json -- { "Module": { "Path": "" - }, - "Require": null, - "Exclude": null, - "Replace": null, - "Retract": null, - "Tool": null, - "Ignore": null + } } -- $WORK/g/go.mod.start -- module g @@ -405,4 +386,4 @@ module g go 1.24 -ignore example.com/ignore \ No newline at end of file +ignore example.com/ignore diff --git a/src/cmd/go/testdata/script/mod_edit_issue75105.txt b/src/cmd/go/testdata/script/mod_edit_issue75105.txt new file mode 100644 index 00000000000000..414d8f700cfe3b --- /dev/null +++ b/src/cmd/go/testdata/script/mod_edit_issue75105.txt @@ -0,0 +1,30 @@ +env GO111MODULE=on + +go mod edit -godebug 'http2debug=2' +cmp go.mod go.mod.edit.want1 + +go mod edit -json +cmp stdout go.mod.edit.want2 +-- go.mod -- +module foo + +go 1.25.0 +-- go.mod.edit.want1 -- +module foo + +go 1.25.0 + +godebug http2debug=2 +-- go.mod.edit.want2 -- +{ + "Module": { + "Path": "foo" + }, + "Go": "1.25.0", + "GoDebug": [ + { + "Key": "http2debug", + "Value": "2" + } + ] +} diff --git a/src/cmd/go/testdata/script/mod_get_direct.txt b/src/cmd/go/testdata/script/mod_get_direct.txt index 02b10ab6fd2a78..2c895764460c10 100644 --- a/src/cmd/go/testdata/script/mod_get_direct.txt +++ b/src/cmd/go/testdata/script/mod_get_direct.txt @@ -2,14 +2,14 @@ # 'GOPROXY=direct go get golang.org/x/tools/gopls@master' did not correctly # resolve the pseudo-version for its dependency on golang.org/x/tools. -[!net:cloud.google.com] skip +[short] skip [!git] skip env GO111MODULE=on env GOPROXY=direct env GOSUMDB=off -go list -m cloud.google.com/go@main +go list -m vcs-test.golang.org/git/tagtests.git@master ! stdout 'v0.0.0-' -- go.mod -- diff --git a/src/cmd/go/testdata/script/mod_get_fallback.txt b/src/cmd/go/testdata/script/mod_get_fallback.txt index a5119b6efe2d2f..794a46e2fa8be3 100644 --- a/src/cmd/go/testdata/script/mod_get_fallback.txt +++ b/src/cmd/go/testdata/script/mod_get_fallback.txt @@ -1,14 +1,11 @@ -env GO111MODULE=on - -[!net:golang.org] skip -[!net:proxy.golang.org] skip - -env GOPROXY=https://proxy.golang.org,direct env GOSUMDB=off -go get -x -v golang.org/x/tools/cmd/goimports -stderr '# get https://proxy.golang.org/golang.org/x/tools/@v/list' -! stderr '# get https://golang.org' +env LOCALMODPROXY=$GOPROXY +env GOPROXY=$LOCALMODPROXY,direct + +go get -x -v vcs-test.golang.org/git/hello.git +stderr '# get '$LOCALMODPROXY'/vcs-test.golang.org/git/hello.git/@v/list' +! stderr '# get https://vcs-test.golang.org' -- go.mod -- module m diff --git a/src/cmd/go/testdata/script/mod_get_fips140_issue73649.txt b/src/cmd/go/testdata/script/mod_get_fips140_issue73649.txt new file mode 100644 index 00000000000000..4ab176cb7a0a4d --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_fips140_issue73649.txt @@ -0,0 +1,10 @@ +[GOEXPERIMENT:boringcrypto] skip + +env GOFIPS140=v1.0.0 +env GOCACHE=$WORK/cache +go get example.com/importcrypto + +-- go.mod -- +module m + +go 1.27 diff --git a/src/cmd/go/testdata/script/mod_get_hash.txt b/src/cmd/go/testdata/script/mod_get_hash.txt index ec5549defe08c7..eb8e7bdfb69135 100644 --- a/src/cmd/go/testdata/script/mod_get_hash.txt +++ b/src/cmd/go/testdata/script/mod_get_hash.txt @@ -1,18 +1,17 @@ -env GO111MODULE=on env GOPROXY=direct env GOSUMDB=off -[!net:golang.org] skip +[short] skip [!git] skip # fetch commit hash reachable from refs/heads/* and refs/tags/* is OK -go list -m golang.org/x/time@8be79e1e0910c292df4e79c241bb7e8f7e725959 # on master branch +go list -m vcs-test.golang.org/git/unreachable-hash.git@6c0e37b1dcaab081b5c413108a46669027fcf02b # on main branch # fetch other commit hash, even with a non-standard ref, is not OK -! go list -m golang.org/x/time@334d83c35137ac2b376c1dc3e4c7733791855a3a # refs/changes/24/41624/3 +! go list -m vcs-test.golang.org/git/unreachable-hash.git@cbd2996c52d20dac558bc3b49c342c7c8320a1fc stderr 'unknown revision' -! go list -m golang.org/x/time@v0.0.0-20170424233410-334d83c35137 +! go list -m vcs-test.golang.org/git/unreachable-hash.git@v0.0.0-20170424233410-cbd2996c52d2 stderr 'unknown revision' -! go list -m golang.org/x/time@334d83c35137 +! go list -m vcs-test.golang.org/git/unreachable-hash.git@cbd2996c52d2 stderr 'unknown revision' -- go.mod -- diff --git a/src/cmd/go/testdata/script/mod_get_pseudo.txt b/src/cmd/go/testdata/script/mod_get_pseudo.txt index 47ad54e352c170..8b3585107fa748 100644 --- a/src/cmd/go/testdata/script/mod_get_pseudo.txt +++ b/src/cmd/go/testdata/script/mod_get_pseudo.txt @@ -1,82 +1,83 @@ env GO111MODULE=on -# Testing git->module converter's generation of +incompatible tags; turn off proxy. -[!net:github.com] skip [!git] skip +[short] skip + +# Testing git->module converter's generation of +incompatible tags; turn off proxy. env GOPROXY=direct env GOSUMDB=off # We can resolve the @master branch without unshallowing the local repository # (even with older gits), so try that before we do anything else. # (This replicates https://golang.org/issue/26713 with git 2.7.4.) -go get github.com/rsc/legacytest@master +go get vcs-test.golang.org/git/legacytest.git@master go list -m all -stdout '^github.com/rsc/legacytest v2\.0\.1-0\.\d{14}-7303f7796364\+incompatible$' +stdout '^vcs-test.golang.org/git/legacytest.git v2\.0\.1-0\.\d{14}-7303f7796364\+incompatible$' # get should include incompatible tags in "latest" calculation. -go mod edit -droprequire github.com/rsc/legacytest -go get github.com/rsc/legacytest@latest +go mod edit -droprequire vcs-test.golang.org/git/legacytest.git +go get vcs-test.golang.org/git/legacytest.git@latest go list go list -m all -stdout '^github.com/rsc/legacytest v2\.0\.0\+incompatible$' +stdout '^vcs-test.golang.org/git/legacytest.git v2\.0\.0\+incompatible$' # v2.0.1-0.pseudo+incompatible -go get ...test@7303f77 +go get ...test.git@7303f77 go list -m all -stdout '^github.com/rsc/legacytest v2\.0\.1-0\.\d{14}-7303f7796364\+incompatible$' +stdout '^vcs-test.golang.org/git/legacytest.git v2\.0\.1-0\.\d{14}-7303f7796364\+incompatible$' # v2.0.0+incompatible by tag+incompatible -go get ...test@v2.0.0+incompatible +go get ...test.git@v2.0.0+incompatible go list -m all -stdout '^github.com/rsc/legacytest v2\.0\.0\+incompatible$' +stdout '^vcs-test.golang.org/git/legacytest.git v2\.0\.0\+incompatible$' # v2.0.0+incompatible by tag -go get ...test@v2.0.0 +go get ...test.git@v2.0.0 go list -m all -stdout '^github.com/rsc/legacytest v2\.0\.0\+incompatible$' +stdout '^vcs-test.golang.org/git/legacytest.git v2\.0\.0\+incompatible$' # v2.0.0+incompatible by hash (back on master) -go get ...test@d7ae1e4 +go get ...test.git@d7ae1e4 go list -m all -stdout '^github.com/rsc/legacytest v2\.0\.0\+incompatible$' +stdout '^vcs-test.golang.org/git/legacytest.git v2\.0\.0\+incompatible$' # v1.2.1-0.pseudo -go get ...test@d2d4c3e +go get ...test.git@d2d4c3e go list -m all -stdout '^github.com/rsc/legacytest v1\.2\.1-0\.\d{14}-d2d4c3ea6623$' +stdout '^vcs-test.golang.org/git/legacytest.git v1\.2\.1-0\.\d{14}-d2d4c3ea6623$' # v1.2.0 -go get ...test@9f6f860 +go get ...test.git@9f6f860 go list -m all -stdout '^github.com/rsc/legacytest v1\.2\.0$' +stdout '^vcs-test.golang.org/git/legacytest.git v1\.2\.0$' # v1.1.0-pre.0.pseudo -go get ...test@fb3c628 +go get ...test.git@fb3c628 go list -m all -stdout '^github.com/rsc/legacytest v1\.1\.0-pre\.0\.\d{14}-fb3c628075e3$' +stdout '^vcs-test.golang.org/git/legacytest.git v1\.1\.0-pre\.0\.\d{14}-fb3c628075e3$' # v1.1.0-pre (no longer on master) -go get ...test@731e3b1 +go get ...test.git@731e3b1 go list -m all -stdout '^github.com/rsc/legacytest v1\.1\.0-pre$' +stdout '^vcs-test.golang.org/git/legacytest.git v1\.1\.0-pre$' # v1.0.1-0.pseudo -go get ...test@fa4f5d6 +go get ...test.git@fa4f5d6 go list -m all -stdout '^github.com/rsc/legacytest v1\.0\.1-0\.\d{14}-fa4f5d6a71c6$' +stdout '^vcs-test.golang.org/git/legacytest.git v1\.0\.1-0\.\d{14}-fa4f5d6a71c6$' # v1.0.0 -go get ...test@7fff7f3 +go get ...test.git@7fff7f3 go list -m all -stdout '^github.com/rsc/legacytest v1\.0\.0$' +stdout '^vcs-test.golang.org/git/legacytest.git v1\.0\.0$' # v0.0.0-pseudo -go get ...test@52853eb +go get ...test.git@52853eb go list -m all -stdout '^github.com/rsc/legacytest v0\.0\.0-\d{14}-52853eb7b552$' +stdout '^vcs-test.golang.org/git/legacytest.git v0\.0\.0-\d{14}-52853eb7b552$' -- go.mod -- module x -- x.go -- package x -import "github.com/rsc/legacytest" +import "vcs-test.golang.org/git/legacytest.git" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_1_0_0.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_1_0_0.txt new file mode 100644 index 00000000000000..59cc894763fb47 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_1_0_0.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v1.0.0 +go get ...test.hg@d6ad17 +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v1\.0\.0$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_1_2_0.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_1_2_0.txt new file mode 100644 index 00000000000000..164ee762b65ede --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_1_2_0.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v1.2.0 +go get ...test.hg@07462d +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v1\.2\.0$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_dash_zero_pseudo.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_dash_zero_pseudo.txt new file mode 100644 index 00000000000000..08662dc649baaf --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_dash_zero_pseudo.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v1.2.1-0.pseudo +go get ...test.hg@ed9a22e +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v1\.2\.1-0\.\d{14}-ed9a22ebb8a1$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" \ No newline at end of file diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_dash_zero_pseudo_2.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_dash_zero_pseudo_2.txt new file mode 100644 index 00000000000000..d22de3cb9465ac --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_dash_zero_pseudo_2.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v1.0.1-0.pseudo +go get ...test.hg@c6260a +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v1\.0\.1-0\.\d{14}-c6260ab8dc3e$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_dash_zero_pseudo_3.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_dash_zero_pseudo_3.txt new file mode 100644 index 00000000000000..2e07c7e3311eee --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_dash_zero_pseudo_3.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v0.0.0-pseudo +go get ...test.hg@ee0106d +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v0\.0\.0-\d{14}-ee0106da3c7c$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_default.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_default.txt new file mode 100644 index 00000000000000..9e81b77fb710cc --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_default.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# get default +go get vcs-test.golang.org/hg/legacytest.hg@default +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v1\.2\.1-0\.20180717164942-2840708d1294$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_incompatible_by_hash.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_incompatible_by_hash.txt new file mode 100644 index 00000000000000..df7c88830ba34c --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_incompatible_by_hash.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v2.0.0+incompatible by hash (back on master) +go get ...test.hg@e64782f +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v2\.0\.0\+incompatible$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" \ No newline at end of file diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_incompatible_by_tag b/src/cmd/go/testdata/script/mod_get_pseudo_hg_incompatible_by_tag new file mode 100644 index 00000000000000..a57be35cb911e7 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_incompatible_by_tag @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v2.0.0+incompatible by tag +go get ...test.hg@v2.0.0 +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v2\.0\.0\+incompatible$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_incompatible_by_tag+incompatible.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_incompatible_by_tag+incompatible.txt new file mode 100644 index 00000000000000..3f4cd7dfeed06c --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_incompatible_by_tag+incompatible.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v2.0.0+incompatible by tag+incompatible +go get ...test.hg@v2.0.0+incompatible +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v2\.0\.0\+incompatible$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_latest_incompatible.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_latest_incompatible.txt new file mode 100644 index 00000000000000..b325a07d5dc862 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_latest_incompatible.txt @@ -0,0 +1,21 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# get should include incompatible tags in "latest" calculation. +go mod edit -droprequire vcs-test.golang.org/hg/legacytest.hg +go get vcs-test.golang.org/hg/legacytest.hg@latest +go list +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v2\.0\.0\+incompatible$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_pre.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_pre.txt new file mode 100644 index 00000000000000..76273e2722ac93 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_pre.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v1.1.0-pre.0.pseudo +go get ...test.hg@accb16 +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v1\.1\.0-pre\.0\.\d{14}-accb169a3696$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_pre_non_master.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_pre_non_master.txt new file mode 100644 index 00000000000000..73e683f0d5a4f8 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_pre_non_master.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v1.1.0-pre (no longer on master) +go get ...test.hg@90da67a9 +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v1\.1\.0-pre$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_hg_pseudo_incompatible.txt b/src/cmd/go/testdata/script/mod_get_pseudo_hg_pseudo_incompatible.txt new file mode 100644 index 00000000000000..0776478f274640 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_pseudo_hg_pseudo_incompatible.txt @@ -0,0 +1,19 @@ +[!exec:hg] skip +[short] skip + +# Testing hg->module converter's generation of +incompatible tags; turn off proxy. +env GOPROXY=direct +env GOSUMDB=off + +# v2.0.1-0.pseudo+incompatible +go get ...test.hg@d6ad6040 +go list -m all +stdout '^vcs-test.golang.org/hg/legacytest.hg v2\.0\.1-0\.\d{14}-d6ad604046f6\+incompatible$' + +-- go.mod -- +module x + +require vcs-test.golang.org/hg/legacytest.hg v1.0.0 +-- x.go -- +package x +import "vcs-test.golang.org/hg/legacytest.hg" diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_other_branch.txt b/src/cmd/go/testdata/script/mod_get_pseudo_other_branch.txt index 6019b45a2c8be4..05e81b4e9a5db7 100644 --- a/src/cmd/go/testdata/script/mod_get_pseudo_other_branch.txt +++ b/src/cmd/go/testdata/script/mod_get_pseudo_other_branch.txt @@ -64,4 +64,4 @@ git checkout master git merge b -m merge zip -r ../tagtests.zip . -gsutil cp ../tagtests.zip gs://vcs-test/git/tagtests.zip +gcloud storage cp ../tagtests.zip gs://vcs-test/git/tagtests.zip diff --git a/src/cmd/go/testdata/script/mod_get_pseudo_prefix.txt b/src/cmd/go/testdata/script/mod_get_pseudo_prefix.txt index ac3233e040656b..1df37b6db55eee 100644 --- a/src/cmd/go/testdata/script/mod_get_pseudo_prefix.txt +++ b/src/cmd/go/testdata/script/mod_get_pseudo_prefix.txt @@ -61,4 +61,4 @@ git add status git commit -m 'after last tag' zip -r ../prefixtagtests.zip . -gsutil cp ../prefixtagtests.zip gs://vcs-test/git/prefixtagtests.zip +gcloud storage cp ../prefixtagtests.zip gs://vcs-test/git/prefixtagtests.zip diff --git a/src/cmd/go/testdata/script/mod_get_tool_upgrade_go.txt b/src/cmd/go/testdata/script/mod_get_tool_upgrade_go.txt new file mode 100644 index 00000000000000..8329010601f858 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_get_tool_upgrade_go.txt @@ -0,0 +1,40 @@ +# Adding a tool upgrades the toolchain to 1.24.0 because older go +# versions fail to parse the tool directive. Issue #74739. +cp go.mod.go1.23.0 go.mod +go get -tool ./mytool +stderr 'go: upgraded go 1.23.0 => 1.24' +cmp go.mod go.mod.go1.24 +go mod tidy +cmp go.mod go.mod.go1.24 + +# No toolchain change if go >= 1.24.0 +cp go.mod.go1.24 go.mod +cmp go.mod go.mod.go1.24 +go get -tool ./mytool +cmp go.mod go.mod.go1.24 +go mod tidy +cmp go.mod go.mod.go1.24 + +# TODO(#78550): If #78550 is approved, go build should reject +# the go.mod file if go < 1.24 but there is a tool directive. +# For now, we will let it through. +cp go.mod.go1.23.0 go.mod +go list ./mytool +go build -n ./mytool + +-- go.mod.go1.23.0 -- +module m + +go 1.23.0 + +tool m/mytool +-- go.mod.go1.24 -- +module m + +go 1.24 + +tool m/mytool +-- mytool/mytool.go -- +package mytool + +func main() {} diff --git a/src/cmd/go/testdata/script/mod_getx.txt b/src/cmd/go/testdata/script/mod_getx.txt index 46bb95bf58fb3a..8a70da1ad2a5ba 100644 --- a/src/cmd/go/testdata/script/mod_getx.txt +++ b/src/cmd/go/testdata/script/mod_getx.txt @@ -1,15 +1,14 @@ -[!net:golang.org] skip +[short] skip [!git] skip -env GO111MODULE=on env GOPROXY=direct env GOSUMDB=off # 'go get -x' should log URLs with an HTTP or HTTPS scheme. # A bug had caused us to log schemeless URLs instead. -go get -x golang.org/x/text@v0.1.0 -stderr '^# get https://golang.org/x/text\?go-get=1$' -stderr '^# get https://golang.org/x/text\?go-get=1: 200 OK \([0-9.]+s\)$' +go get -x vcs-test.golang.org/go/mod/gitrepo1@v1.2.3 +stderr '^# get https://vcs-test.golang.org/go/mod/gitrepo1\?go-get=1$' +stderr '^# get https://vcs-test.golang.org/go/mod/gitrepo1\?go-get=1: 200 OK \([0-9.]+s\)$' ! stderr '^# get //.*' -- go.mod -- diff --git a/src/cmd/go/testdata/script/mod_git_export_subst.txt b/src/cmd/go/testdata/script/mod_git_export_subst.txt index 740ccbdb81e780..c8b598872b7047 100644 --- a/src/cmd/go/testdata/script/mod_git_export_subst.txt +++ b/src/cmd/go/testdata/script/mod_git_export_subst.txt @@ -1,21 +1,21 @@ -env GO111MODULE=on env GOPROXY=direct +env GONOSUMDB=vcs-test.golang.org # Testing that git export-subst is disabled -[!net:github.com] skip +[short] skip 'uses git' [!git] skip go build -- x.go -- package x -import _ "github.com/jasonkeene/export-subst" +import _ "vcs-test.golang.org/git/export-subst.git" -- go.mod -- module x -require github.com/jasonkeene/export-subst v0.0.0-20180927204031-5845945ec626 +require vcs-test.golang.org/git/export-subst.git v0.0.0-20180927204031-98817ac105fc -- go.sum -- -github.com/jasonkeene/export-subst v0.0.0-20180927204031-5845945ec626 h1:AUkXi/xFnm7lH2pgtvVkGb7buRn1ywFHw+xDpZ29Rz0= -github.com/jasonkeene/export-subst v0.0.0-20180927204031-5845945ec626/go.mod h1:DwJXqVtrgrQkv3Giuf2Jh4YyubVe7y41S1eOIaysTJw= +vcs-test.golang.org/git/export-subst.git v0.0.0-20180927204031-98817ac105fc h1:JSFJzPmCTsz2eFs1jjb40Tun7DZZ6TZQUWgsh8VNZYE= +vcs-test.golang.org/git/export-subst.git v0.0.0-20180927204031-98817ac105fc/go.mod h1:UgzsJqCUIrlpaTSm+IYkSmrpeo+9g12tsw/rNKnMfwE= diff --git a/src/cmd/go/testdata/script/mod_goline_too_new.txt b/src/cmd/go/testdata/script/mod_goline_too_new.txt index 6d2667937af3f7..938fedfb544de5 100644 --- a/src/cmd/go/testdata/script/mod_goline_too_new.txt +++ b/src/cmd/go/testdata/script/mod_goline_too_new.txt @@ -8,7 +8,7 @@ stderr '^go: go.mod requires go >= 1.99999 \(running go 1\..+\)$' # go.mod referenced from go.work too new cp go.work.old go.work ! go build . -stderr '^go: module . listed in go.work file requires go >= 1.99999, but go.work lists go 1.10; to update it:\n\tgo work use$' +stderr '^go: module . listed in go.work file requires go >= 1.99999, but go.work lists go 1.10; to download and use go 1.99999:\n\tgo work use$' ! go work sync stderr '^go: cannot load module . listed in go.work file: go.mod requires go >= 1.99999 \(running go 1\..+\)$' diff --git a/src/cmd/go/testdata/script/mod_gonoproxy.txt b/src/cmd/go/testdata/script/mod_gonoproxy.txt index 94d03f22f266b2..d704c54024fb4e 100644 --- a/src/cmd/go/testdata/script/mod_gonoproxy.txt +++ b/src/cmd/go/testdata/script/mod_gonoproxy.txt @@ -35,21 +35,24 @@ env GOPROXY=off ! go get golang.org/x/text stderr '^go: golang.org/x/text: module lookup disabled by GOPROXY=off$' +[short] skip 'the rest of the test uses git' + # GONOPROXY bypasses proxy -[!net:rsc.io] skip [!git] skip +env GOPROXY=$proxy +env GOSUMDB=$sumdb env GOPRIVATE=none -env GONOPROXY='*/fortune' -! go get rsc.io/fortune # does not exist in real world, only on test proxy +env GONOPROXY='*/git/proxyonly.git' +! go get vcs-test.golang.org/git/proxyonly.git # does not exist in vcstest, only on test proxy stderr 'git ls-remote' -[!net:golang.org] skip -env GOSUMDB= +env GOSUMDB=off env GONOPROXY= -env GOPRIVATE='*/x' -go get golang.org/x/text +env GOPRIVATE='*/git/tagtests.git' +go get vcs-test.golang.org/git/tagtests.git go list -m all -! stdout 'text.*v0.0.0-2017' # should not have the version from the proxy +stdout '^vcs-test.golang.org/git/tagtests.git v0.2.2$' +! stdout 'tagtests.git v0.1.0' # should not have the version from the proxy -- go.mod.orig -- module m diff --git a/src/cmd/go/testdata/script/mod_gopkg_unstable.txt b/src/cmd/go/testdata/script/mod_gopkg_unstable.txt index 856f493f30ce91..34e6de381b5053 100644 --- a/src/cmd/go/testdata/script/mod_gopkg_unstable.txt +++ b/src/cmd/go/testdata/script/mod_gopkg_unstable.txt @@ -7,10 +7,9 @@ cp x.go.txt x.go cp go.mod.empty go.mod go list -[!net:gopkg.in] skip +skip # TODO(#54503): redirect gopkg.in requests to a local server and re-enable. [!git] skip -skip # TODO(#54503): redirect gopkg.in requests to a local server and re-enable. env GOPROXY=direct env GOSUMDB=off diff --git a/src/cmd/go/testdata/script/mod_init_invalid_major.txt b/src/cmd/go/testdata/script/mod_init_invalid_major.txt index ae93e70d6307ff..69dfa292510379 100644 --- a/src/cmd/go/testdata/script/mod_init_invalid_major.txt +++ b/src/cmd/go/testdata/script/mod_init_invalid_major.txt @@ -80,3 +80,11 @@ stderr '(?s)^go: malformed module path "foo bar": invalid char '' ''$' ! go mod init 'foo bar baz' stderr '(?s)^go: malformed module path "foo bar baz": invalid char '' ''$' + +# go mod init should not infer an invalid /v1 suffix from GOPATH. +cd $WORK/gopath/src/example.com/user/repo/v1 +! go mod init +stderr '(?s)^go: invalid module path "example.com/user/repo/v1": major version suffixes must be in the form of /vN and are only allowed for v2 or later(.*)go mod init example.com/user/repo/v2$' + +-- example.com/user/repo/v1/empty.go -- +package main diff --git a/src/cmd/go/testdata/script/mod_invalid_version.txt b/src/cmd/go/testdata/script/mod_invalid_version.txt index a0427b39a089e6..5a8c7ee7557310 100644 --- a/src/cmd/go/testdata/script/mod_invalid_version.txt +++ b/src/cmd/go/testdata/script/mod_invalid_version.txt @@ -1,7 +1,6 @@ -[!net:golang.org] skip +[short] skip [!git] skip -env GO111MODULE=on env GOPROXY=direct env GOSUMDB=off env GOFLAGS=-mod=mod @@ -9,222 +8,218 @@ env GOFLAGS=-mod=mod # Regression test for golang.org/issue/27173: if the user (or go.mod file) # requests a pseudo-version that does not match both the module path and commit # metadata, reject it with a helpful error message. -# -# TODO(bcmills): Replace the github.com/pierrec/lz4 examples with something -# equivalent on vcs-test.golang.org. # An incomplete commit hash is not a valid semantic version, # but can appear in the main go.mod file anyway and should be resolved. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@14c0d48ead0c +go mod edit -require vcs-test.golang.org/go/invalid-version@1732873 cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 \(replaced by \./\.\.\): parsing ..[/\\]go.mod: '$WORK'[/\\]gopath[/\\]src[/\\]go.mod:5: require golang.org/x/text: version "14c0d48ead0c" invalid: must be of the form v1.2.3' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 \(replaced by \./\.\.\): parsing ..[/\\]go.mod: '$WORK'[/\\]gopath[/\\]src[/\\]go.mod:5: require vcs-test.golang.org/go/invalid-version: version "1732873" invalid: must be of the form v1.2.3' cd .. -go list -m golang.org/x/text -stdout 'golang.org/x/text v0.1.1-0.20170915032832-14c0d48ead0c' -grep 'golang.org/x/text v0.1.1-0.20170915032832-14c0d48ead0c' go.mod +go list -m vcs-test.golang.org/go/invalid-version +stdout 'vcs-test.golang.org/go/invalid-version v0.1.1-0.20170915032832-1732873102df' +grep 'vcs-test.golang.org/go/invalid-version v0.1.1-0.20170915032832-1732873102df' go.mod # A module path below the repo root that does not contain a go.mod file is invalid. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text/unicode@v0.0.0-20170915032832-14c0d48ead0c +go mod edit -require vcs-test.golang.org/go/invalid-version/unicode@v0.0.0-20170915032832-1732873102df cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text/unicode@v0.0.0-20170915032832-14c0d48ead0c: invalid version: missing golang.org/x/text/unicode/go.mod at revision 14c0d48ead0c' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version/unicode@v0.0.0-20170915032832-1732873102df: invalid version: missing vcs-test.golang.org/go/invalid-version/unicode/go.mod at revision 1732873102df' cd .. -! go list -m golang.org/x/text -stderr 'golang.org/x/text/unicode@v0.0.0-20170915032832-14c0d48ead0c: invalid version: missing golang.org/x/text/unicode/go.mod at revision 14c0d48ead0c' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'vcs-test.golang.org/go/invalid-version/unicode@v0.0.0-20170915032832-1732873102df: invalid version: missing vcs-test.golang.org/go/invalid-version/unicode/go.mod at revision 1732873102df' # However, arguments to 'go get' can name packages above the root. cp go.mod.orig go.mod -go get golang.org/x/text/unicode@v0.0.0-20170915032832-14c0d48ead0c -go list -m golang.org/x/text/... -stdout 'golang.org/x/text v0.0.0-20170915032832-14c0d48ead0c' -! stdout 'golang.org/x/text/unicode' +go get vcs-test.golang.org/go/invalid-version@v0.1.1-0.20170915032832-90ac26bf7f41 +go list -m vcs-test.golang.org/go/invalid-version/... +stdout 'vcs-test.golang.org/go/invalid-version v0.1.1-0.20170915032832-90ac26bf7f41' +! stdout 'vcs-test.golang.org/go/invalid-version/unicode' # A major version that does not match the module path is invalid. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v2.1.1-0.20170915032832-14c0d48ead0c +go mod edit -require vcs-test.golang.org/go/invalid-version@v2.1.1-0.20170915032832-1732873102df cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 \(replaced by \./\.\.\): parsing ..[/\\]go.mod: '$WORK'[/\\]gopath[/\\]src[/\\]go.mod:5: require golang.org/x/text: version "v2.1.1-0.20170915032832-14c0d48ead0c" invalid: should be v0 or v1, not v2' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 \(replaced by \./\.\.\): parsing ..[/\\]go.mod: '$WORK'[/\\]gopath[/\\]src[/\\]go.mod:5: require vcs-test.golang.org/go/invalid-version: version "v2.1.1-0.20170915032832-1732873102df" invalid: should be v0 or v1, not v2' cd .. -! go list -m golang.org/x/text -stderr '^go.mod:5: require golang.org/x/text: version "v2.1.1-0.20170915032832-14c0d48ead0c" invalid: should be v0 or v1, not v2' +! go list -m vcs-test.golang.org/go/invalid-version +stderr '^go.mod:5: require vcs-test.golang.org/go/invalid-version: version "v2.1.1-0.20170915032832-1732873102df" invalid: should be v0 or v1, not v2' # A pseudo-version with fewer than 12 digits of SHA-1 prefix is invalid. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v0.1.1-0.20170915032832-14c0d48ead0 +go mod edit -require vcs-test.golang.org/go/invalid-version@v0.1.1-0.20170915032832-1732873102d cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v0.1.1-0.20170915032832-14c0d48ead0: invalid pseudo-version: revision is shorter than canonical \(expected 14c0d48ead0c\)' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v0.1.1-0.20170915032832-1732873102d: invalid pseudo-version: revision is shorter than canonical \(expected 1732873102df\)' cd .. -! go list -m golang.org/x/text -stderr 'golang.org/x/text@v0.1.1-0.20170915032832-14c0d48ead0: invalid pseudo-version: revision is shorter than canonical \(expected 14c0d48ead0c\)' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'vcs-test.golang.org/go/invalid-version@v0.1.1-0.20170915032832-1732873102d: invalid pseudo-version: revision is shorter than canonical \(expected 1732873102df\)' # A pseudo-version with more than 12 digits of SHA-1 prefix is invalid. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v0.1.1-0.20170915032832-14c0d48ead0cd47e3104ada247d91be04afc7a5a +go mod edit -require vcs-test.golang.org/go/invalid-version@v0.1.1-0.20170915032832-1732873102dfcda2ecfbb94082da3cd4b21bc715 cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v0.1.1-0.20170915032832-14c0d48ead0cd47e3104ada247d91be04afc7a5a: invalid pseudo-version: revision is longer than canonical \(expected 14c0d48ead0c\)' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v0.1.1-0.20170915032832-1732873102dfcda2ecfbb94082da3cd4b21bc715: invalid pseudo-version: revision is longer than canonical \(expected 1732873102df\)' cd .. -! go list -m golang.org/x/text -stderr 'golang.org/x/text@v0.1.1-0.20170915032832-14c0d48ead0cd47e3104ada247d91be04afc7a5a: invalid pseudo-version: revision is longer than canonical \(expected 14c0d48ead0c\)' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'vcs-test.golang.org/go/invalid-version@v0.1.1-0.20170915032832-1732873102dfcda2ecfbb94082da3cd4b21bc715: invalid pseudo-version: revision is longer than canonical \(expected 1732873102df\)' # A pseudo-version that does not match the commit timestamp is invalid. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v0.1.1-0.20190915032832-14c0d48ead0c +go mod edit -require vcs-test.golang.org/go/invalid-version@v0.1.1-0.20190915032832-1732873102df cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v0.1.1-0.20190915032832-14c0d48ead0c: invalid pseudo-version: does not match version-control timestamp \(expected 20170915032832\)' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v0.1.1-0.20190915032832-1732873102df: invalid pseudo-version: does not match version-control timestamp \(expected 20170915032832\)' cd .. -! go list -m golang.org/x/text -stderr 'golang.org/x/text@v0.1.1-0.20190915032832-14c0d48ead0c: invalid pseudo-version: does not match version-control timestamp \(expected 20170915032832\)' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'vcs-test.golang.org/go/invalid-version@v0.1.1-0.20190915032832-1732873102df: invalid pseudo-version: does not match version-control timestamp \(expected 20170915032832\)' # A 'replace' directive in the main module can replace an invalid timestamp # with a valid one. -go mod edit -replace golang.org/x/text@v0.1.1-0.20190915032832-14c0d48ead0c=golang.org/x/text@14c0d48ead0c +go mod edit -replace vcs-test.golang.org/go/invalid-version@v0.1.1-0.20190915032832-1732873102df=vcs-test.golang.org/go/invalid-version@1732873102df cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v0.1.1-0.20190915032832-14c0d48ead0c: invalid pseudo-version: does not match version-control timestamp \(expected 20170915032832\)' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v0.1.1-0.20190915032832-1732873102df: invalid pseudo-version: does not match version-control timestamp \(expected 20170915032832\)' cd .. -go list -m golang.org/x/text -stdout 'golang.org/x/text v0.1.1-0.20190915032832-14c0d48ead0c => golang.org/x/text v0.1.1-0.20170915032832-14c0d48ead0c' +go list -m vcs-test.golang.org/go/invalid-version +stdout 'vcs-test.golang.org/go/invalid-version v0.1.1-0.20190915032832-1732873102df => vcs-test.golang.org/go/invalid-version v0.1.1-0.20170915032832-1732873102df' # A pseudo-version that is not derived from a tag is invalid. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v1.999.999-0.20170915032832-14c0d48ead0c +go mod edit -require vcs-test.golang.org/go/invalid-version@v1.999.999-0.20170915032832-1732873102df cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v1.999.999-0.20170915032832-14c0d48ead0c: invalid pseudo-version: preceding tag \(v1.999.998\) not found' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v1.999.999-0.20170915032832-1732873102df: invalid pseudo-version: preceding tag \(v1.999.998\) not found' cd .. -! go list -m golang.org/x/text -stderr 'golang.org/x/text@v1.999.999-0.20170915032832-14c0d48ead0c: invalid pseudo-version: preceding tag \(v1.999.998\) not found' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'vcs-test.golang.org/go/invalid-version@v1.999.999-0.20170915032832-1732873102df: invalid pseudo-version: preceding tag \(v1.999.998\) not found' # A v1.0.0- pseudo-version that is not derived from a tag is invalid: # v1.0.0- implies no tag, but the correct no-tag prefix for a module path # without a major-version suffix is v0.0.0-. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v1.0.0-20170915032832-14c0d48ead0c +go mod edit -require vcs-test.golang.org/go/invalid-version@v1.0.0-20170915032832-1732873102df cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v1.0.0-20170915032832-14c0d48ead0c: invalid pseudo-version: major version without preceding tag must be v0, not v1' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v1.0.0-20170915032832-1732873102df: invalid pseudo-version: major version without preceding tag must be v0, not v1' cd .. -! go list -m golang.org/x/text -stderr 'golang.org/x/text@v1.0.0-20170915032832-14c0d48ead0c: invalid pseudo-version: major version without preceding tag must be v0, not v1' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'vcs-test.golang.org/go/invalid-version@v1.0.0-20170915032832-1732873102df: invalid pseudo-version: major version without preceding tag must be v0, not v1' # A pseudo-version vX.Y.Z+1 cannot have Z+1 == 0, since that would # imply a base tag with a negative patch field. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v0.0.0-0.20170915032832-14c0d48ead0c +go mod edit -require vcs-test.golang.org/go/invalid-version@v0.0.0-0.20170915032832-1732873102df cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v0.0.0-0.20170915032832-14c0d48ead0c: invalid pseudo-version: version before v0.0.0 would have negative patch number' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v0.0.0-0.20170915032832-1732873102df: invalid pseudo-version: version before v0.0.0 would have negative patch number' cd .. -! go list -m golang.org/x/text -stderr 'golang.org/x/text@v0.0.0-0.20170915032832-14c0d48ead0c: invalid pseudo-version: version before v0.0.0 would have negative patch number' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'vcs-test.golang.org/go/invalid-version@v0.0.0-0.20170915032832-1732873102df: invalid pseudo-version: version before v0.0.0 would have negative patch number' # A 'replace' directive in the main module can replace an # invalid pseudo-version base with a valid one. -go mod edit -replace golang.org/x/text@v0.0.0-0.20170915032832-14c0d48ead0c=golang.org/x/text@v0.0.0-20170915032832-14c0d48ead0c +go mod edit -replace vcs-test.golang.org/go/invalid-version@v0.0.0-0.20170915032832-1732873102df=vcs-test.golang.org/go/invalid-version@v0.0.0-20170915032832-1732873102df cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v0.0.0-0.20170915032832-14c0d48ead0c: invalid pseudo-version: version before v0.0.0 would have negative patch number' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v0.0.0-0.20170915032832-1732873102df: invalid pseudo-version: version before v0.0.0 would have negative patch number' cd .. -go list -m golang.org/x/text -stdout 'golang.org/x/text v0.0.0-0.20170915032832-14c0d48ead0c => golang.org/x/text v0.0.0-20170915032832-14c0d48ead0c' +go list -m vcs-test.golang.org/go/invalid-version +stdout 'vcs-test.golang.org/go/invalid-version v0.0.0-0.20170915032832-1732873102df => vcs-test.golang.org/go/invalid-version v0.0.0-20170915032832-1732873102df' # A 'replace' directive can replace an invalid 'latest' version, and # should suppress errors for that version in 'go get -u' cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v1.999999.0 -go mod edit -replace golang.org/x/text@v1.999999.0=golang.org/x/text@v0.0.0-20170915032832-14c0d48ead0c +go mod edit -require vcs-test.golang.org/go/invalid-version@v1.999999.0 +go mod edit -replace vcs-test.golang.org/go/invalid-version@v1.999999.0=vcs-test.golang.org/go/invalid-version@v0.0.0-20170915032832-1732873102df cd outside -! go get golang.org/x/text@upgrade -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v1.999999.0: reading golang.org/x/text/go.mod at revision v1.999999.0: unknown revision v1.999999.0' +! go get vcs-test.golang.org/go/invalid-version@upgrade +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v1.999999.0: reading vcs-test.golang.org/go/invalid-version/go.mod at revision v1.999999.0: unknown revision v1.999999.0' cd .. -go get golang.org/x/text@upgrade -go list -m golang.org/x/text -stdout 'golang.org/x/text v1.999999.0 => golang.org/x/text v0.0.0-20170915032832-14c0d48ead0c' +go get vcs-test.golang.org/go/invalid-version@upgrade +go list -m vcs-test.golang.org/go/invalid-version +stdout 'vcs-test.golang.org/go/invalid-version v1.999999.0 => vcs-test.golang.org/go/invalid-version v0.0.0-20170915032832-1732873102df' + # A pseudo-version derived from a non-ancestor tag is invalid. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v0.2.1-0.20170915032832-14c0d48ead0c +go mod edit -require vcs-test.golang.org/go/invalid-version@v0.2.1-0.20170915032832-1732873102df cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v0.2.1-0.20170915032832-14c0d48ead0c: invalid pseudo-version: revision 14c0d48ead0c is not a descendent of preceding tag \(v0.2.0\)' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v0.2.1-0.20170915032832-1732873102df: invalid pseudo-version: revision 1732873102df is not a descendent of preceding tag \(v0.2.0\)' cd .. -! go list -m golang.org/x/text -stderr 'golang.org/x/text@v0.2.1-0.20170915032832-14c0d48ead0c: invalid pseudo-version: revision 14c0d48ead0c is not a descendent of preceding tag \(v0.2.0\)' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'vcs-test.golang.org/go/invalid-version@v0.2.1-0.20170915032832-1732873102df: invalid pseudo-version: revision 1732873102df is not a descendent of preceding tag \(v0.2.0\)' # A pseudo-version derived from a canonical tag on the same revision is invalid. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v0.2.1-0.20171213102548-c4d099d611ac +go mod edit -require vcs-test.golang.org/go/invalid-version@v0.2.1-0.20171213102548-a72be5ead5a6 cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v0.2.1-0.20171213102548-c4d099d611ac: invalid pseudo-version: tag \(v0.2.0\) found on revision c4d099d611ac is already canonical, so should not be replaced with a pseudo-version derived from that tag' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v0.2.1-0.20171213102548-a72be5ead5a6: invalid pseudo-version: tag \(v0.2.0\) found on revision a72be5ead5a6 is already canonical, so should not be replaced with a pseudo-version derived from that tag' cd .. -! go list -m golang.org/x/text -stderr 'golang.org/x/text@v0.2.1-0.20171213102548-c4d099d611ac: invalid pseudo-version: tag \(v0.2.0\) found on revision c4d099d611ac is already canonical, so should not be replaced with a pseudo-version derived from that tag' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'vcs-test.golang.org/go/invalid-version@v0.2.1-0.20171213102548-a72be5ead5a6: invalid pseudo-version: tag \(v0.2.0\) found on revision a72be5ead5a6 is already canonical, so should not be replaced with a pseudo-version derived from that tag' # A +incompatible suffix is not allowed on a version that is actually compatible. cp go.mod.orig go.mod -go mod edit -require golang.org/x/text@v0.1.1-0.20170915032832-14c0d48ead0c+incompatible +go mod edit -require vcs-test.golang.org/go/invalid-version@v0.1.1-0.20170915032832-1732873102df+incompatible cd outside -! go list -m golang.org/x/text -stderr 'go: example.com@v0.0.0 requires\n\tgolang.org/x/text@v0.1.1-0.20170915032832-14c0d48ead0c\+incompatible: invalid version: \+incompatible suffix not allowed: major version v0 is compatible' +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v0.1.1-0.20170915032832-1732873102df\+incompatible: invalid version: \+incompatible suffix not allowed: major version v0 is compatible' cd .. -! go list -m golang.org/x/text -stderr 'golang.org/x/text@v0.1.1-0.20170915032832-14c0d48ead0c\+incompatible: invalid version: \+incompatible suffix not allowed: major version v0 is compatible' - -[!net:github.com] stop +! go list -m vcs-test.golang.org/go/invalid-version +stderr 'vcs-test.golang.org/go/invalid-version@v0.1.1-0.20170915032832-1732873102df\+incompatible: invalid version: \+incompatible suffix not allowed: major version v0 is compatible' # The pseudo-version for a commit after a tag with a non-matching major version -# should instead be based on the last matching tag. +# should instead be based on the last matching tag (which is v4.0.0 in this case). cp go.mod.orig go.mod -go mod edit -require github.com/pierrec/lz4@473cd7ce01a1 -go list -m github.com/pierrec/lz4 -stdout 'github.com/pierrec/lz4 v1.0.2-0.20190131084431-473cd7ce01a1' +go mod edit -require vcs-test.golang.org/go/invalid-version@5213b9f8842f +go list -m vcs-test.golang.org/go/invalid-version +stdout 'vcs-test.golang.org/go/invalid-version v0.2.1-0.20171213102548-5213b9f8842f' cd outside -go list -m github.com/pierrec/lz4 -stdout 'github.com/pierrec/lz4 v1.0.2-0.20190131084431-473cd7ce01a1' +go list -m vcs-test.golang.org/go/invalid-version +stdout 'vcs-test.golang.org/go/invalid-version v0.2.1-0.20171213102548-5213b9f8842f' cd .. # A +incompatible pseudo-version for a module that has an explicit go.mod file is invalid. cp go.mod.orig go.mod -go mod edit -require github.com/pierrec/lz4@v2.0.9-0.20190209155647-9a39efadad3d+incompatible +go mod edit -require vcs-test.golang.org/go/invalid-version@v4.0.1-0.20171213102548-5213b9f8842f+incompatible cd outside -! go list -m github.com/pierrec/lz4 -stderr '^go: example.com@v0.0.0 requires\n\tgithub.com/pierrec/lz4@v2.0.9-0.20190209155647-9a39efadad3d\+incompatible: invalid version: module contains a go.mod file, so module path must match major version \("github.com/pierrec/lz4/v2"\)$' +! go list -m vcs-test.golang.org/go/invalid-version +stderr '^go: example.com@v0.0.0 requires\n\tvcs-test.golang.org/go/invalid-version@v4.0.1-0.20171213102548-5213b9f8842f\+incompatible: invalid version: module contains a go.mod file, so module path must match major version \("vcs-test.golang.org/go/invalid-version/v4"\)$' cd .. -! go list -m github.com/pierrec/lz4 -stderr '^go: github.com/pierrec/lz4@v2.0.9-0.20190209155647-9a39efadad3d\+incompatible: invalid version: module contains a go.mod file, so module path must match major version \("github.com/pierrec/lz4/v2"\)$' +! go list -m vcs-test.golang.org/go/invalid-version +stderr '^go: vcs-test.golang.org/go/invalid-version@v4.0.1-0.20171213102548-5213b9f8842f\+incompatible: invalid version: module contains a go.mod file, so module path must match major version \("vcs-test.golang.org/go/invalid-version/v4"\)$' # A +incompatible pseudo-version is valid for a revision of the module # that lacks a go.mod file. cp go.mod.orig go.mod -go mod edit -require github.com/pierrec/lz4@v2.0.4-0.20180826165652-dbe9298ce099+incompatible +go mod edit -require vcs-test.golang.org/go/invalid-version@v4.0.1-0.20171213102548-dbb861dd9ef0+incompatible cd outside -go list -m github.com/pierrec/lz4 -stdout 'github.com/pierrec/lz4 v2.0.4-0.20180826165652-dbe9298ce099\+incompatible' +go list -m vcs-test.golang.org/go/invalid-version +stdout 'vcs-test.golang.org/go/invalid-version v4.0.1-0.20171213102548-dbb861dd9ef0\+incompatible' cd .. -go list -m github.com/pierrec/lz4 -stdout 'github.com/pierrec/lz4 v2.0.4-0.20180826165652-dbe9298ce099\+incompatible' +go list -m vcs-test.golang.org/go/invalid-version +stdout 'vcs-test.golang.org/go/invalid-version v4.0.1-0.20171213102548-dbb861dd9ef0\+incompatible' # 'go get' for a mismatched major version without a go.mod file should resolve # to the equivalent +incompatible version, not a pseudo-version with a different # major version. cp go.mod.orig go.mod -go get github.com/pierrec/lz4@v2.0.5 -go list -m github.com/pierrec/lz4 -stdout 'github.com/pierrec/lz4 v2.0.5\+incompatible' +go get vcs-test.golang.org/go/invalid-version@v5.0.0 +go list -m vcs-test.golang.org/go/invalid-version +stdout 'vcs-test.golang.org/go/invalid-version v5.0.0\+incompatible' # 'go get' for a mismatched major version with a go.mod file should error out, # not resolve to a pseudo-version with a different major version. cp go.mod.orig go.mod -! go get github.com/pierrec/lz4@v2.0.8 -stderr 'go: github.com/pierrec/lz4@v2.0.8: invalid version: module contains a go.mod file, so module path must match major version \("github.com/pierrec/lz4/v2"\)$' +! go get vcs-test.golang.org/go/invalid-version@v4.0.0 +stderr 'go: vcs-test.golang.org/go/invalid-version@v4.0.0: invalid version: module contains a go.mod file, so module path must match major version \("vcs-test.golang.org/go/invalid-version/v4"\)$' # An invalid +incompatible suffix for a canonical version should error out, # not resolve to a pseudo-version. @@ -232,13 +227,13 @@ stderr 'go: github.com/pierrec/lz4@v2.0.8: invalid version: module contains a go # TODO(bcmills): The "outside" view for this failure mode is missing its import stack. # Figure out why and fix it. cp go.mod.orig go.mod -go mod edit -require github.com/pierrec/lz4@v2.0.8+incompatible +go mod edit -require vcs-test.golang.org/go/invalid-version@v4.0.0+incompatible cd outside -! go list -m github.com/pierrec/lz4 -stderr '^go: github.com/pierrec/lz4@v2.0.8\+incompatible: invalid version: module contains a go.mod file, so module path must match major version \("github.com/pierrec/lz4/v2"\)$' +! go list -m vcs-test.golang.org/go/invalid-version +stderr '^go: vcs-test.golang.org/go/invalid-version@v4.0.0\+incompatible: invalid version: module contains a go.mod file, so module path must match major version \("vcs-test.golang.org/go/invalid-version/v4"\)$' cd .. -! go list -m github.com/pierrec/lz4 -stderr '^go: github.com/pierrec/lz4@v2.0.8\+incompatible: invalid version: module contains a go.mod file, so module path must match major version \("github.com/pierrec/lz4/v2"\)$' +! go list -m vcs-test.golang.org/go/invalid-version +stderr '^go: vcs-test.golang.org/go/invalid-version@v4.0.0\+incompatible: invalid version: module contains a go.mod file, so module path must match major version \("vcs-test.golang.org/go/invalid-version/v4"\)$' -- go.mod.orig -- module example.com diff --git a/src/cmd/go/testdata/script/mod_outside.txt b/src/cmd/go/testdata/script/mod_outside.txt index 7a0dc9f22f675e..18cc3d5a27b1fe 100644 --- a/src/cmd/go/testdata/script/mod_outside.txt +++ b/src/cmd/go/testdata/script/mod_outside.txt @@ -173,13 +173,15 @@ go build -n fmt go build ./newgo/newgo.go # 'go doc' without arguments implicitly operates on the current directory, and should fail. -# TODO(golang.org/issue/32027): currently, it succeeds. cd needmod -go doc +! go doc +stderr '^doc: go: go.mod file not found in current directory or any parent directory; see ''go help modules''$' cd .. -# 'go doc' of a non-module directory should also succeed. -go doc ./needmod +# 'go doc' of a non-module directory should also fail. +! go doc ./needmod +stderr '^doc: go: go.mod file not found in current directory or any parent directory; see ''go help modules''$' + # 'go doc' should succeed for standard-library packages. go doc fmt diff --git a/src/cmd/go/testdata/script/mod_prefer_compatible.txt b/src/cmd/go/testdata/script/mod_prefer_compatible.txt index 4d583ff5f7e5a0..d1a985393c6e16 100644 --- a/src/cmd/go/testdata/script/mod_prefer_compatible.txt +++ b/src/cmd/go/testdata/script/mod_prefer_compatible.txt @@ -2,30 +2,26 @@ # @latest, @upgrade, and @patch should prefer compatible versions over # +incompatible ones, even if offered by a proxy. -[!net:github.com] skip -[!net:proxy.golang.org] skip - env GO111MODULE=on -env GOPROXY= -env GOSUMDB= +env GOSUMDB=off -# github.com/russross/blackfriday v2.0.0+incompatible exists, +# vcs-test.golang.org/git/prefercompatible.git v2.0.0+incompatible exists, # and should be resolved if we ask for it explicitly. -go list -m github.com/russross/blackfriday@v2.0.0+incompatible -stdout '^github.com/russross/blackfriday v2\.0\.0\+incompatible$' +go list -m vcs-test.golang.org/git/prefercompatible.git@v2.0.0+incompatible +stdout '^vcs-test.golang.org/git/prefercompatible.git v2\.0\.0\+incompatible$' -# blackfriday v1.5.2 has a go.mod file, so v1.5.2 should be preferred over +# prefercompatible v1.5.2 has a go.mod file, so v1.5.2 should be preferred over # v2.0.0+incompatible when resolving latest, upgrade, and patch. -go list -m github.com/russross/blackfriday@latest -stdout '^github.com/russross/blackfriday v1\.' +go list -m vcs-test.golang.org/git/prefercompatible.git@latest +stdout '^vcs-test.golang.org/git/prefercompatible.git v1\.' -go list -m github.com/russross/blackfriday@upgrade -stdout '^github.com/russross/blackfriday v1\.' +go list -m vcs-test.golang.org/git/prefercompatible.git@upgrade +stdout '^vcs-test.golang.org/git/prefercompatible.git v1\.' -! go list -m github.com/russross/blackfriday@patch -stderr '^go: github.com/russross/blackfriday@patch: can''t query version "patch" of module github.com/russross/blackfriday: no existing version is required$' +! go list -m vcs-test.golang.org/git/prefercompatible.git@patch +stderr '^go: vcs-test.golang.org/git/prefercompatible.git@patch: can''t query version "patch" of module vcs-test.golang.org/git/prefercompatible.git: no existing version is required$' # If we're fetching directly from version control, ignored +incompatible @@ -36,45 +32,46 @@ stderr '^go: github.com/russross/blackfriday@patch: can''t query version "patch" # order to determine whether it contains a go.mod file, and part of the point of # the proxy is to avoid fetching unnecessary data.) +[short] stop [!git] stop env GOPROXY=direct -go list -versions -m github.com/russross/blackfriday -stdout '^github.com/russross/blackfriday v1\.5\.1 v1\.5\.2' # and possibly others +go list -versions -m vcs-test.golang.org/git/prefercompatible.git +stdout '^vcs-test.golang.org/git/prefercompatible.git v1\.5\.1 v1\.5\.2' # and possibly others ! stdout ' v2\.' # For this module, v2.1.0 exists and has a go.mod file. -# 'go list -m github.com/russross/blackfriday@v2.0' will check +# 'go list -m vcs-test.golang.org/git/prefercompatible.git@v2.0' will check # the latest v2.0 tag, discover that it isn't the right module, and stop there # (instead of spending the time to check O(N) previous tags). -! go list -m github.com/russross/blackfriday@v2.0 -stderr '^go: module github.com/russross/blackfriday: no matching versions for query "v2\.0\"' +! go list -m vcs-test.golang.org/git/prefercompatible.git@v2.0 +stderr '^go: module vcs-test.golang.org/git/prefercompatible.git: no matching versions for query "v2\.0\"' # (But asking for exactly v2.0.0+incompatible should still succeed.) -go list -m github.com/russross/blackfriday@v2.0.0+incompatible -stdout '^github.com/russross/blackfriday v2\.0\.0\+incompatible$' +go list -m vcs-test.golang.org/git/prefercompatible.git@v2.0.0+incompatible +stdout '^vcs-test.golang.org/git/prefercompatible.git v2\.0\.0\+incompatible$' # However, if the latest compatible version does not include a go.mod file, # +incompatible versions should still be listed, as they may still reflect the # intent of the module author. -go list -versions -m github.com/rsc/legacytest -stdout '^github.com/rsc/legacytest v1\.0\.0 v1\.1\.0-pre v1\.2\.0 v2\.0\.0\+incompatible' +go list -versions -m vcs-test.golang.org/git/legacytest.git +stdout '^vcs-test.golang.org/git/legacytest.git v1\.0\.0 v1\.1\.0-pre v1\.2\.0 v2\.0\.0\+incompatible' # If we're fetching directly from version control, asking for a commit hash # corresponding to a +incompatible version should continue to produce the # +incompatible version tagged for that commit, even if it is no longer listed. -go list -m github.com/russross/blackfriday@cadec560ec52 -stdout '^github.com/russross/blackfriday v2\.0\.0\+incompatible$' +go list -m vcs-test.golang.org/git/prefercompatible.git@7a6f627326 +stdout '^vcs-test.golang.org/git/prefercompatible.git v2\.0\.0\+incompatible$' # Similarly, requesting an untagged commit should continue to produce a +incompatible # pseudo-version. -go list -m github.com/rsc/legacytest@7303f7796364 -stdout '^github.com/rsc/legacytest v2\.0\.1-0\.20180717164253-7303f7796364\+incompatible$' +go list -m vcs-test.golang.org/git/legacytest.git@7303f7796364 +stdout '^vcs-test.golang.org/git/legacytest.git v2\.0\.1-0\.20180717164253-7303f7796364\+incompatible$' -- go.mod -- module github.com/golang.org/issue/34165 diff --git a/src/cmd/go/testdata/script/mod_pseudo_cache.txt b/src/cmd/go/testdata/script/mod_pseudo_cache.txt index bcaefa2f79f5c7..3f0493ca6856d0 100644 --- a/src/cmd/go/testdata/script/mod_pseudo_cache.txt +++ b/src/cmd/go/testdata/script/mod_pseudo_cache.txt @@ -1,5 +1,5 @@ -[!net:golang.org] skip [!git] skip +[short] skip env GO111MODULE=on env GOPROXY=direct @@ -9,21 +9,21 @@ env GOSUMDB=off # pseudo-version of a commit, future resolution of that commit by hash should # choose the highest appropriate pseudo-version instead of the cached one. -go mod download -json golang.org/x/text@v0.0.0-20171215141712-a1b916ed6726 -stdout '"Version": "v0.0.0-20171215141712-a1b916ed6726",' +go mod download -json vcs-test.golang.org/git/commit-after-tag.git@v0.0.0-20190715211727-b325d8217783 +stdout '"Version": "v0.0.0-20190715211727-b325d8217783",' # If GOPROXY is 'off', lookups should use whatever pseudo-version is available. env GOPROXY=off -go mod download -json golang.org/x/text@a1b916ed6726 -stdout '"Version": "v0.0.0-20171215141712-a1b916ed6726",' +go mod download -json vcs-test.golang.org/git/commit-after-tag.git@b325d8217783 +stdout '"Version": "v0.0.0-20190715211727-b325d8217783",' # If we can re-resolve the commit to a pseudo-version, fetching the commit by # hash should use the highest such pseudo-version appropriate to the commit. env GOPROXY=direct -go mod download -json golang.org/x/text@a1b916ed6726 -stdout '"Version": "v0.3.1-0.20171215141712-a1b916ed6726",' +go mod download -json vcs-test.golang.org/git/commit-after-tag.git@b325d8217783 +stdout '"Version": "v1.0.1-0.20190715211727-b325d8217783",' # If GOPROXY is 'off', lookups should use the highest pseudo-version in the cache. env GOPROXY=off -go mod download -json golang.org/x/text@a1b916ed6726 -stdout '"Version": "v0.3.1-0.20171215141712-a1b916ed6726",' +go mod download -json vcs-test.golang.org/git/commit-after-tag.git@b325d8217783 +stdout '"Version": "v1.0.1-0.20190715211727-b325d8217783",' diff --git a/src/cmd/go/testdata/script/mod_removed_godebug.txt b/src/cmd/go/testdata/script/mod_removed_godebug.txt new file mode 100644 index 00000000000000..cf8f04736bd039 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_removed_godebug.txt @@ -0,0 +1,11 @@ +# Test case that makes sure we print a nice error message +# instead of the generic "unknown godebug" error message +# for removed GODEBUGs. + +! go list +stderr '^go.mod:3: removed GODEBUG "x509sha1" set to old value "1" \(https://go.dev/doc/godebug#go-124\)' + +-- go.mod -- +module example.com/bar + +godebug x509sha1=1 diff --git a/src/cmd/go/testdata/script/mod_replace_gopkgin.txt b/src/cmd/go/testdata/script/mod_replace_gopkgin.txt index 91008f920f31b4..8d7de076f8840f 100644 --- a/src/cmd/go/testdata/script/mod_replace_gopkgin.txt +++ b/src/cmd/go/testdata/script/mod_replace_gopkgin.txt @@ -5,9 +5,7 @@ # gopkg.in path. skip 'skipping test that depends on an unreliable third-party server; see https://go.dev/issue/54503' - # TODO(#54043): Make this test hermetic and re-enable it. - -[!net:gopkg.in] skip +# TODO(#54503): Make this work without needing the external network, and then re-enable. [!git] skip env GO111MODULE=on diff --git a/src/cmd/go/testdata/script/mod_retract_pseudo_base.txt b/src/cmd/go/testdata/script/mod_retract_pseudo_base.txt index 87b440dc7ea793..3d3e03c0377cfc 100644 --- a/src/cmd/go/testdata/script/mod_retract_pseudo_base.txt +++ b/src/cmd/go/testdata/script/mod_retract_pseudo_base.txt @@ -59,4 +59,4 @@ git mv p.go q.go git commit -m 'trivial change' zip -r ../retract-pseudo.zip . -gsutil cp ../retract-pseudo.zip gs://vcs-test/git/retract-pseudo.zip +gcloud storage cp ../retract-pseudo.zip gs://vcs-test/git/retract-pseudo.zip diff --git a/src/cmd/go/testdata/script/mod_run_flags_issue77483.txt b/src/cmd/go/testdata/script/mod_run_flags_issue77483.txt new file mode 100644 index 00000000000000..9a5d3673498dc8 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_run_flags_issue77483.txt @@ -0,0 +1,4 @@ +# Regression test for https://go.dev/issue/77483: 'go run -C' should not panic. + +! go run -C +stderr 'flag needs an argument: -C' diff --git a/src/cmd/go/testdata/script/mod_simplify_require.txt b/src/cmd/go/testdata/script/mod_simplify_require.txt new file mode 100644 index 00000000000000..fe1de470cf1597 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_simplify_require.txt @@ -0,0 +1,155 @@ +# If go.mod has go 1.27 or higher, multiple require blocks should be +# consolidated. Even those with comments. + +cp go.mod.127 go.mod +go mod tidy +cmp go.mod go.mod.127tidy + +# If go.mod has go 1.26, blocks with comments should be preserved. +cp go.mod.126 go.mod +go mod tidy +cmp go.mod go.mod.126tidy + +-- go.mod.127 -- +module example.com/m + +go 1.27 + +require example.com/a v1.0.0 + +// Block comment +require ( + example.com/b v1.0.0 +) + +// Another block comment +require ( + example.com/d v1.0.0 // an inline comment + example.com/c v1.0.0 // indirect +) + +// A third block comment +require ( + example.com/e v1.0.0 // indirect +) + +replace ( + example.com/a v1.0.0 => ./a + example.com/b v1.0.0 => ./b + example.com/c v1.0.0 => ./c + example.com/d v1.0.0 => ./d + example.com/e v1.0.0 => ./e +) +-- go.mod.127tidy -- +module example.com/m + +go 1.27 + +// Block comment +// +// Another block comment +require ( + example.com/a v1.0.0 + example.com/b v1.0.0 + example.com/d v1.0.0 // an inline comment +) + +// A third block comment +require ( + example.com/c v1.0.0 // indirect + example.com/e v1.0.0 // indirect +) + +replace ( + example.com/a v1.0.0 => ./a + example.com/b v1.0.0 => ./b + example.com/c v1.0.0 => ./c + example.com/d v1.0.0 => ./d + example.com/e v1.0.0 => ./e +) +-- go.mod.126 -- +module example.com/m + +go 1.26 + +require example.com/a v1.0.0 + +// Block comment +require ( + example.com/b v1.0.0 + example.com/d v1.0.0 +) + +require example.com/c v1.0.0 // indirect + +replace ( + example.com/a v1.0.0 => ./a + example.com/b v1.0.0 => ./b + example.com/c v1.0.0 => ./c + example.com/d v1.0.0 => ./d + example.com/e v1.0.0 => ./e +) +-- go.mod.126tidy -- +module example.com/m + +go 1.26 + +require example.com/a v1.0.0 + +// Block comment +require ( + example.com/b v1.0.0 + example.com/d v1.0.0 +) + +require ( + example.com/c v1.0.0 // indirect + example.com/e v1.0.0 // indirect +) + +replace ( + example.com/a v1.0.0 => ./a + example.com/b v1.0.0 => ./b + example.com/c v1.0.0 => ./c + example.com/d v1.0.0 => ./d + example.com/e v1.0.0 => ./e +) +-- m.go -- +package m +import _ "example.com/a" +import _ "example.com/b" +import _ "example.com/d" + +-- a/go.mod -- +module example.com/a +go 1.26 +require example.com/c v1.0.0 +require example.com/e v1.0.0 +-- a/a.go -- +package a +import _ "example.com/c" +import _ "example.com/e" + +-- b/go.mod -- +module example.com/b +go 1.26 +-- b/b.go -- +package b + +-- c/go.mod -- +module example.com/c +go 1.26 +-- c/c.go -- +package c + +-- d/go.mod -- +module example.com/d +go 1.26 +-- d/d.go -- +package d + +-- e/go.mod -- +module example.com/e +go 1.26 +-- e/e.go -- +package e diff --git a/src/cmd/go/testdata/script/mod_sum_absent.txt b/src/cmd/go/testdata/script/mod_sum_absent.txt new file mode 100644 index 00000000000000..c2dd814542d671 --- /dev/null +++ b/src/cmd/go/testdata/script/mod_sum_absent.txt @@ -0,0 +1,17 @@ +# When the sumdb returns a response which does not +# include a sum for the requested module, +# we should report an error. +# Verifies CVE-2026-42501. +env sumdb=$GOSUMDB +env proxy=$GOPROXY +env GOPROXY GONOPROXY GOSUMDB GONOSUMDB + +# /sumdb-redirect/ causes the sumdb to return /lookup/ responses +# for rsc.io/quote@v1.0.0, not for the requested module. +env GOSUMDB=$sumdb' '$proxy/sumdb-redirect/rsc.io/quote@v1.0.0: + +! go get rsc.io/fortune@v1.0.0 +stderr 'SECURITY ERROR' +! grep rsc.io go.sum +-- go.mod -- +module m diff --git a/src/cmd/go/testdata/script/mod_sumdb_file_path.txt b/src/cmd/go/testdata/script/mod_sumdb_file_path.txt index 2f42cb54f5a3d1..b34286586162a9 100644 --- a/src/cmd/go/testdata/script/mod_sumdb_file_path.txt +++ b/src/cmd/go/testdata/script/mod_sumdb_file_path.txt @@ -1,49 +1,48 @@ -[!net:proxy.golang.org] skip -[!net:sum.golang.org] skip - env GO111MODULE=on -[go-builder] env GOSUMDB= -[!go-builder] env GOSUMDB=sum.golang.org # Set explicitly in case GOROOT/go.env is modified. +env TESTPROXY=$GOPROXY env GOPATH=$WORK/gopath1 +mkdir $WORK/sumproxy/sumdb/$TESTGO_SUMDB +cp supported $WORK/sumproxy/sumdb/$TESTGO_SUMDB/supported + # With a file-based proxy with an empty checksum directory, # downloading a new module should fail, even if a subsequent # proxy contains a more complete mirror of the sum database. # # TODO(bcmills): The error message here is a bit redundant. # It comes from the sumweb package, which isn't yet producing structured errors. -[GOOS:windows] env GOPROXY=file:///$WORK/sumproxy,https://proxy.golang.org -[!GOOS:windows] env GOPROXY=file://$WORK/sumproxy,https://proxy.golang.org -! go get golang.org/x/text@v0.3.2 -stderr '^go: golang.org/x/text@v0.3.2: verifying module: golang.org/x/text@v0.3.2: reading file://.*/sumdb/sum.golang.org/lookup/golang.org/x/text@v0.3.2: (no such file or directory|.*cannot find the path specified.*)' +[GOOS:windows] env GOPROXY=file:///$WORK/sumproxy,$TESTPROXY +[!GOOS:windows] env GOPROXY=file://$WORK/sumproxy,$TESTPROXY +! go get rsc.io/quote@v1.5.2 +stderr '^go: rsc.io/quote@v1.5.2: verifying module: rsc.io/quote@v1.5.2: reading file://.*/sumdb/.*/lookup/rsc.io/quote@v1.5.2: (no such file or directory|.*cannot find the path specified.*)' # If the proxy does not claim to support the database, # checksum verification should fall through to the next proxy, # and downloading should succeed. -[GOOS:windows] env GOPROXY=file:///$WORK/emptyproxy,https://proxy.golang.org -[!GOOS:windows] env GOPROXY=file://$WORK/emptyproxy,https://proxy.golang.org -go get golang.org/x/text@v0.3.2 +[GOOS:windows] env GOPROXY=file:///$WORK/emptyproxy,$TESTPROXY +[!GOOS:windows] env GOPROXY=file://$WORK/emptyproxy,$TESTPROXY +go get rsc.io/quote@v1.5.2 # After a successful sumdb lookup, the lookup can be repeated # using the download cache as a proxy. -cp supported $GOPATH/pkg/mod/cache/download/sumdb/sum.golang.org/supported +cp supported $GOPATH/pkg/mod/cache/download/sumdb/$TESTGO_SUMDB/supported [GOOS:windows] env GOPROXY=file:///$WORK/gopath1/pkg/mod/cache/download,file:///$WORK/sumproxy [!GOOS:windows] env GOPROXY=file://$WORK/gopath1/pkg/mod/cache/download,file://$WORK/sumproxy env GOPATH=$WORK/gopath2 rm go.sum -go get -x -v golang.org/x/text@v0.3.2 +go get -x -v rsc.io/quote@v1.5.2 # Once the checksum is present in the go.sum file, # an empty file-based sumdb can be used in conjunction with # a fallback module mirror. -grep golang.org/x/text go.sum +grep rsc.io/quote go.sum env GOPATH=$WORK/gopath3 [GOOS:windows] env GOPROXY=file:///$WORK/sumproxy [!GOOS:windows] env GOPROXY=file://$WORK/sumproxy -! go get golang.org/x/text@v0.3.2 -[GOOS:windows] env GOPROXY=file:///$WORK/sumproxy,https://proxy.golang.org -[!GOOS:windows] env GOPROXY=file://$WORK/sumproxy,https://proxy.golang.org -go get golang.org/x/text@v0.3.2 +! go get rsc.io/quote@v1.5.2 +[GOOS:windows] env GOPROXY=file:///$WORK/sumproxy,$TESTPROXY +[!GOOS:windows] env GOPROXY=file://$WORK/sumproxy,$TESTPROXY +go get rsc.io/quote@v1.5.2 -- supported -- @@ -52,7 +51,3 @@ module example.com go 1.13 -- $WORK/emptyproxy/README.md -- This proxy contains no modules. --- $WORK/sumproxy/README.md -- -This proxy contains no modules. --- $WORK/sumproxy/sumdb/sum.golang.org/supported -- -This proxy blocks checksum downloads from sum.golang.org. diff --git a/src/cmd/go/testdata/script/mod_vcs_missing.txt b/src/cmd/go/testdata/script/mod_vcs_missing.txt deleted file mode 100644 index 7f63e9de217f53..00000000000000 --- a/src/cmd/go/testdata/script/mod_vcs_missing.txt +++ /dev/null @@ -1,28 +0,0 @@ -[exec:bzr] skip 'tests NOT having bzr' -[!net:launchpad.net] skip - -env GO111MODULE=on -env GOPROXY=direct - -cd empty -! go get launchpad.net/gocheck -stderr '"bzr": executable file not found' -cd .. - -# 1.11 used to give the cryptic error "cannot find module for path" here, but -# only for a main package. -cd main -! go build -mod=mod -stderr '"bzr": executable file not found' -cd .. - --- empty/go.mod -- -module m --- main/go.mod -- -module m --- main/main.go -- -package main - -import _ "launchpad.net/gocheck" - -func main() {} diff --git a/src/cmd/go/testdata/script/reuse_git.txt b/src/cmd/go/testdata/script/reuse_git.txt index 3c1b38b04de7be..faf2124db56620 100644 --- a/src/cmd/go/testdata/script/reuse_git.txt +++ b/src/cmd/go/testdata/script/reuse_git.txt @@ -5,11 +5,11 @@ env GO111MODULE=on env GOPROXY=direct env GOSUMDB=off -# go mod download with the pseudo-version should invoke git but not have a TagSum or Ref. +# go mod download with the pseudo-version should invoke git but not have a TagSum or Ref or RepoSum. go mod download -x -json vcs-test.golang.org/git/hello.git@v0.0.0-20170922010558-fc3a09f3dc5c stderr 'git( .*)* fetch' cp stdout hellopseudo.json -! stdout '"(Query|TagPrefix|TagSum|Ref)"' +! stdout '"(Query|TagPrefix|TagSum|Ref|RepoSum)"' stdout '"Version": "v0.0.0-20170922010558-fc3a09f3dc5c"' stdout '"VCS": "git"' stdout '"URL": ".*/git/hello"' @@ -28,6 +28,7 @@ stdout '"Query": "latest"' stdout '"TagSum": "t1:47DEQpj8HBSa[+]/TImW[+]5JCeuQeRkm5NMpJWZG3hSuFU="' stdout '"Ref": "HEAD"' stdout '"Hash": "fc3a09f3dc5cfe0d7a743ea18f1f5226e68b3777"' +! stdout '"RepoSum"' # pseudo-version again should not invoke git fetch (it has the version from the @latest query) # but still be careful not to include a TagSum or a Ref, especially not Ref set to HEAD, @@ -47,6 +48,7 @@ stdout '"VCS": "git"' stdout '"URL": ".*/git/hello"' stdout '"TagSum": "t1:47DEQpj8HBSa[+]/TImW[+]5JCeuQeRkm5NMpJWZG3hSuFU="' stdout '"Hash": "fc3a09f3dc5cfe0d7a743ea18f1f5226e68b3777"' +! stdout '"RepoSum"' # go mod download vcstest/hello/v9 should fail, still print origin info ! go mod download -x -json vcs-test.golang.org/git/hello.git/v9@latest @@ -108,6 +110,7 @@ stdout '"URL": ".*/git/tagtests"' stdout '"TagSum": "t1:Dp7yRKDuE8WjG0429PN9hYWjqhy2te7P9Oki/sMEOGo="' stdout '"Ref": "refs/tags/v0.2.2"' stdout '"Hash": "59356c8cd18c5fe9a598167d98a6843e52d57952"' +! stdout '"RepoSum"' # go mod download vcstest/tagtests@v0.2.2 should print origin info, no TagSum needed go mod download -x -json vcs-test.golang.org/git/tagtests.git@v0.2.2 @@ -120,6 +123,7 @@ stdout '"URL": ".*/git/tagtests"' ! stdout '"TagSum"' stdout '"Ref": "refs/tags/v0.2.2"' stdout '"Hash": "59356c8cd18c5fe9a598167d98a6843e52d57952"' +! stdout '"RepoSum"' # go mod download vcstest/tagtests@master needs a TagSum again go mod download -x -json vcs-test.golang.org/git/tagtests.git@master @@ -132,6 +136,7 @@ stdout '"URL": ".*/git/tagtests"' stdout '"TagSum": "t1:Dp7yRKDuE8WjG0429PN9hYWjqhy2te7P9Oki/sMEOGo="' stdout '"Ref": "refs/heads/master"' stdout '"Hash": "c7818c24fa2f3f714c67d0a6d3e411c85a518d1f"' +! stdout '"RepoSum"' # go mod download vcstest/prefixtagtests should invoke git, print origin info go mod download -x -json vcs-test.golang.org/git/prefixtagtests.git/sub@latest @@ -146,6 +151,7 @@ stdout '"TagPrefix": "sub/"' stdout '"TagSum": "t1:YGSbWkJ8dn9ORAr[+]BlKHFK/2ZhXLb9hVuYfTZ9D8C7g="' stdout '"Ref": "refs/tags/sub/v0.0.10"' stdout '"Hash": "2b7c4692e12c109263cab51b416fcc835ddd7eae"' +! stdout '"RepoSum"' # go mod download of a bunch of these should fail (some are invalid) but write good JSON for later ! go mod download -json vcs-test.golang.org/git/hello.git@latest vcs-test.golang.org/git/hello.git/v9@latest vcs-test.golang.org/git/hello.git/sub/v9@latest vcs-test.golang.org/git/tagtests.git@latest vcs-test.golang.org/git/tagtests.git@v0.2.2 vcs-test.golang.org/git/tagtests.git@master @@ -158,6 +164,7 @@ stderr 'git( .*)* fetch' go clean -modcache # reuse go mod download vcstest/hello result +go clean -modcache go mod download -reuse=hello.json -x -json vcs-test.golang.org/git/hello.git@latest ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -168,12 +175,10 @@ stdout '"URL": ".*/git/hello"' stdout '"TagSum": "t1:47DEQpj8HBSa[+]/TImW[+]5JCeuQeRkm5NMpJWZG3hSuFU="' stdout '"Ref": "HEAD"' stdout '"Hash": "fc3a09f3dc5cfe0d7a743ea18f1f5226e68b3777"' -! stdout '"Dir"' -! stdout '"Info"' -! stdout '"GoMod"' -! stdout '"Zip"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' # reuse go mod download vcstest/hello pseudoversion result +go clean -modcache go mod download -reuse=hellopseudo.json -x -json vcs-test.golang.org/git/hello.git@v0.0.0-20170922010558-fc3a09f3dc5c ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -182,9 +187,10 @@ stdout '"VCS": "git"' stdout '"URL": ".*/git/hello"' ! stdout '"(Query|TagPrefix|TagSum|Ref)"' stdout '"Hash": "fc3a09f3dc5cfe0d7a743ea18f1f5226e68b3777"' -! stdout '"(Dir|Info|GoMod|Zip)"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' # reuse go mod download vcstest/hello@hash +go clean -modcache go mod download -reuse=hellohash.json -x -json vcs-test.golang.org/git/hello.git@fc3a09f3dc5c ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -195,9 +201,10 @@ stdout '"URL": ".*/git/hello"' ! stdout '"(TagPrefix|Ref)"' stdout '"TagSum": "t1:47DEQpj8HBSa[+]/TImW[+]5JCeuQeRkm5NMpJWZG3hSuFU="' stdout '"Hash": "fc3a09f3dc5cfe0d7a743ea18f1f5226e68b3777"' -! stdout '"(Dir|Info|GoMod|Zip)"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' # reuse go mod download vcstest/hello/v9 error result +go clean -modcache ! go mod download -reuse=hellov9.json -x -json vcs-test.golang.org/git/hello.git/v9@latest ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -206,9 +213,10 @@ stdout '"Error":.*no matching versions' stdout '"TagSum": "t1:47DEQpj8HBSa[+]/TImW[+]5JCeuQeRkm5NMpJWZG3hSuFU="' stdout '"Ref": "HEAD"' stdout '"Hash": "fc3a09f3dc5cfe0d7a743ea18f1f5226e68b3777"' -! stdout '"(Dir|Info|GoMod|Zip)"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' # reuse go mod download vcstest/hello/sub/v9 error result +go clean -modcache ! go mod download -reuse=hellosubv9.json -x -json vcs-test.golang.org/git/hello.git/sub/v9@latest ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -217,9 +225,10 @@ stdout '"TagPrefix": "sub/"' stdout '"TagSum": "t1:47DEQpj8HBSa[+]/TImW[+]5JCeuQeRkm5NMpJWZG3hSuFU="' stdout '"Ref": "HEAD"' stdout '"Hash": "fc3a09f3dc5cfe0d7a743ea18f1f5226e68b3777"' -! stdout '"(Dir|Info|GoMod|Zip)"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' # reuse go mod download vcstest/hello@nonexist +go clean -modcache ! go mod download -reuse=hellononexist.json -x -json vcs-test.golang.org/git/hello.git@nonexist ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -230,6 +239,7 @@ stdout '"RepoSum": "r1:c0/9JCZ25lxoBiK3[+]3BhACU4giH49flcJmBynJ[+]Jvmc="' ! stdout '"(Dir|Info|GoMod|Zip)"' # reuse go mod download vcstest/hello@1234567890123456789012345678901234567890 +go clean -modcache ! go mod download -reuse=hellononhash.json -x -json vcs-test.golang.org/git/hello.git@1234567890123456789012345678901234567890 ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -240,6 +250,7 @@ stdout '"RepoSum": "r1:c0/9JCZ25lxoBiK3[+]3BhACU4giH49flcJmBynJ[+]Jvmc="' ! stdout '"(Dir|Info|GoMod|Zip)"' # reuse go mod download vcstest/hello@v0.0.0-20220101120101-123456789abc +go clean -modcache ! go mod download -reuse=hellononpseudo.json -x -json vcs-test.golang.org/git/hello.git@v0.0.0-20220101120101-123456789abc ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -250,6 +261,7 @@ stdout '"RepoSum": "r1:c0/9JCZ25lxoBiK3[+]3BhACU4giH49flcJmBynJ[+]Jvmc="' ! stdout '"(Dir|Info|GoMod|Zip)"' # reuse go mod download vcstest/tagtests result +go clean -modcache go mod download -reuse=tagtests.json -x -json vcs-test.golang.org/git/tagtests.git@latest ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -261,9 +273,10 @@ stdout '"URL": ".*/git/tagtests"' stdout '"TagSum": "t1:Dp7yRKDuE8WjG0429PN9hYWjqhy2te7P9Oki/sMEOGo="' stdout '"Ref": "refs/tags/v0.2.2"' stdout '"Hash": "59356c8cd18c5fe9a598167d98a6843e52d57952"' -! stdout '"(Dir|Info|GoMod|Zip)"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' # reuse go mod download vcstest/tagtests@v0.2.2 result +go clean -modcache go mod download -reuse=tagtestsv022.json -x -json vcs-test.golang.org/git/tagtests.git@v0.2.2 ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -275,9 +288,10 @@ stdout '"URL": ".*/git/tagtests"' ! stdout '"TagSum"' stdout '"Ref": "refs/tags/v0.2.2"' stdout '"Hash": "59356c8cd18c5fe9a598167d98a6843e52d57952"' -! stdout '"(Dir|Info|GoMod|Zip)"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' # reuse go mod download vcstest/tagtests@master result +go clean -modcache go mod download -reuse=tagtestsmaster.json -x -json vcs-test.golang.org/git/tagtests.git@master ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -289,9 +303,10 @@ stdout '"URL": ".*/git/tagtests"' stdout '"TagSum": "t1:Dp7yRKDuE8WjG0429PN9hYWjqhy2te7P9Oki/sMEOGo="' stdout '"Ref": "refs/heads/master"' stdout '"Hash": "c7818c24fa2f3f714c67d0a6d3e411c85a518d1f"' -! stdout '"(Dir|Info|GoMod|Zip)"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' # reuse go mod download vcstest/tagtests@master result again with all.json +go clean -modcache go mod download -reuse=all.json -x -json vcs-test.golang.org/git/tagtests.git@master ! stderr 'git( .*)* fetch' stdout '"Reuse": true' @@ -303,9 +318,10 @@ stdout '"URL": ".*/git/tagtests"' stdout '"TagSum": "t1:Dp7yRKDuE8WjG0429PN9hYWjqhy2te7P9Oki/sMEOGo="' stdout '"Ref": "refs/heads/master"' stdout '"Hash": "c7818c24fa2f3f714c67d0a6d3e411c85a518d1f"' -! stdout '"(Dir|Info|GoMod|Zip)"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' # go mod download vcstest/prefixtagtests result with json +go clean -modcache go mod download -reuse=prefixtagtests.json -x -json vcs-test.golang.org/git/prefixtagtests.git/sub@latest ! stderr 'git( .*)* fetch' stdout '"Version": "v0.0.10"' @@ -320,12 +336,14 @@ stdout '"Hash": "2b7c4692e12c109263cab51b416fcc835ddd7eae"' ! stdout '"(Dir|Info|GoMod|Zip)"' # reuse the bulk results with all.json +go clean -modcache ! go mod download -reuse=all.json -json vcs-test.golang.org/git/hello.git@latest vcs-test.golang.org/git/hello.git/v9@latest vcs-test.golang.org/git/hello.git/sub/v9@latest vcs-test.golang.org/git/tagtests.git@latest vcs-test.golang.org/git/tagtests.git@v0.2.2 vcs-test.golang.org/git/tagtests.git@master ! stderr 'git( .*)* fetch' stdout '"Reuse": true' ! stdout '"(Dir|Info|GoMod|Zip)"' # reuse attempt with stale hash should reinvoke git, not report reuse +go clean -modcache cp tagtestsv022.json tagtestsv022badhash.json replace '57952' '56952XXX' tagtestsv022badhash.json go mod download -reuse=tagtestsv022badhash.json -x -json vcs-test.golang.org/git/tagtests.git@v0.2.2 @@ -335,7 +353,7 @@ stdout '"Version": "v0.2.2"' ! stdout '"Query"' stdout '"VCS": "git"' stdout '"URL": ".*/git/tagtests"' -! stdout '"(TagPrefix|TagSum)"' +! stdout '"(TagPrefix|TagSum|RepoSum)"' stdout '"Ref": "refs/tags/v0.2.2"' stdout '"Hash": "59356c8cd18c5fe9a598167d98a6843e52d57952"' stdout '"Dir"' @@ -344,6 +362,7 @@ stdout '"GoMod"' stdout '"Zip"' # reuse with stale repo URL +go clean -modcache cp tagtestsv022.json tagtestsv022badurl.json replace 'git/tagtests\"' 'git/tagtestsXXX\"' tagtestsv022badurl.json go mod download -reuse=tagtestsv022badurl.json -x -json vcs-test.golang.org/git/tagtests.git@v0.2.2 @@ -355,22 +374,107 @@ stdout '"GoMod"' stdout '"Zip"' # reuse with stale VCS +go clean -modcache cp tagtestsv022.json tagtestsv022badvcs.json replace '\"git\"' '\"gitXXX\"' tagtestsv022badvcs.json go mod download -reuse=tagtestsv022badvcs.json -x -json vcs-test.golang.org/git/tagtests.git@v0.2.2 ! stdout '"Reuse": true' stdout '"URL": ".*/git/tagtests"' +! stdout '"RepoSum"' # reuse with stale Dir +go clean -modcache cp tagtestsv022.json tagtestsv022baddir.json replace '\t\t\"Ref\":' '\t\t\"Subdir\": \"subdir\",\n\t\t\"Ref\":' tagtestsv022baddir.json go mod download -reuse=tagtestsv022baddir.json -x -json vcs-test.golang.org/git/tagtests.git@v0.2.2 ! stdout '"Reuse": true' stdout '"URL": ".*/git/tagtests"' +! stdout '"RepoSum"' # reuse with stale TagSum +go clean -modcache cp tagtests.json tagtestsbadtagsum.json replace 'sMEOGo=' 'sMEoGo=XXX' tagtestsbadtagsum.json go mod download -reuse=tagtestsbadtagsum.json -x -json vcs-test.golang.org/git/tagtests.git@latest ! stdout '"Reuse": true' stdout '"TagSum": "t1:Dp7yRKDuE8WjG0429PN9hYWjqhy2te7P9Oki/sMEOGo="' +! stdout '"RepoSum"' + +# go list on repo with no tags +go clean -modcache +go list -x -json -m -retracted -versions vcs-test.golang.org/git/hello.git@latest +stderr 'git( .*)* fetch' +cp stdout hellolist.json +! stdout '"Versions"' +stdout '"Version": "v0.0.0-20170922010558-fc3a09f3dc5c"' +stdout '"VCS": "git"' +stdout '"URL": ".*/git/hello"' +stdout '"Query": "latest"' +! stdout '"TagPrefix"' +stdout '"TagSum": "t1:47DEQpj8HBSa[+]/TImW[+]5JCeuQeRkm5NMpJWZG3hSuFU="' +stdout '"Hash": "fc3a09f3dc5cfe0d7a743ea18f1f5226e68b3777"' +! stdout '"RepoSum"' + +# reuse go list on repo with no tags +go clean -modcache +go list -x -reuse=hellolist.json -json -m -retracted -versions vcs-test.golang.org/git/hello.git@latest +! stderr 'git( .*)* fetch' +stdout '"Reuse": true' +! stdout '"Versions"' +stdout '"Version": "v0.0.0-20170922010558-fc3a09f3dc5c"' +stdout '"VCS": "git"' +stdout '"URL": ".*/git/hello"' +stdout '"Query": "latest"' +! stdout '"TagPrefix"' +stdout '"TagSum": "t1:47DEQpj8HBSa[+]/TImW[+]5JCeuQeRkm5NMpJWZG3hSuFU="' +stdout '"Hash": "fc3a09f3dc5cfe0d7a743ea18f1f5226e68b3777"' +! stdout '"RepoSum"' + +# reuse with stale list +go clean -modcache +cp hellolist.json hellolistbad.json +replace '47DEQ' 'ZZZ' hellolistbad.json +go clean -modcache +go list -x -reuse=hellolistbad.json -json -m -retracted -versions vcs-test.golang.org/git/hello.git@latest +stderr 'git( .*)* fetch' +! stdout '"Reuse": true' +stdout '"TagSum": "t1:47DEQpj8HBSa[+]/TImW[+]5JCeuQeRkm5NMpJWZG3hSuFU="' + +# go list on repo with tags +go clean -modcache +go list -x -json -m -retracted -versions vcs-test.golang.org/git/tagtests.git@latest +cp stdout taglist.json +stderr 'git( .*)* fetch' +stdout '"Versions":' +stdout '"v0.2.1"' +stdout '"v0.2.2"' +stdout '"Version": "v0.2.2"' +stdout '"VCS": "git"' +stdout '"URL": ".*/git/tagtests"' +stdout '"Hash": "59356c8cd18c5fe9a598167d98a6843e52d57952"' +stdout '"TagSum": "t1:Dp7yRKDuE8WjG0429PN9hYWjqhy2te7P9Oki/sMEOGo="' +stdout '"Ref": "refs/tags/v0.2.2"' + +# reuse go list on repo with tags +go clean -modcache +go list -reuse=taglist.json -x -json -m -retracted -versions vcs-test.golang.org/git/tagtests.git@latest +! stderr 'git( .*)* fetch' +stdout '"Reuse": true' +stdout '"Versions":' +stdout '"v0.2.1"' +stdout '"v0.2.2"' +stdout '"Version": "v0.2.2"' +stdout '"VCS": "git"' +stdout '"URL": ".*/git/tagtests"' +stdout '"Hash": "59356c8cd18c5fe9a598167d98a6843e52d57952"' +stdout '"TagSum": "t1:Dp7yRKDuE8WjG0429PN9hYWjqhy2te7P9Oki/sMEOGo="' +stdout '"Ref": "refs/tags/v0.2.2"' + +# reuse with stale list +go clean -modcache +cp taglist.json taglistbad.json +replace 'Dp7yRKDu' 'ZZZ' taglistbad.json +go list -reuse=taglistbad.json -x -json -m -retracted -versions vcs-test.golang.org/git/tagtests.git@latest +stderr 'git( .*)* fetch' +! stdout '"Reuse": true' +stdout '"TagSum": "t1:Dp7yRKDuE8WjG0429PN9hYWjqhy2te7P9Oki/sMEOGo="' diff --git a/src/cmd/go/testdata/script/reuse_hg_all.txt b/src/cmd/go/testdata/script/reuse_hg_all.txt new file mode 100644 index 00000000000000..bfbb9d9b636c82 --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_all.txt @@ -0,0 +1,33 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download of a bunch of these should fail (some are invalid) but write good JSON for later +! go mod download -json vcs-test.golang.org/hg/hello.hg@latest vcs-test.golang.org/hg/hello.hg/v9@latest vcs-test.golang.org/hg/hello.hg/sub/v9@latest vcs-test.golang.org/hg/tagtests.hg@latest vcs-test.golang.org/hg/tagtests.hg@v0.2.2 vcs-test.golang.org/hg/tagtests.hg@default +cp stdout all.json + +# reuse go mod download vcstest/tagtests@default result again with all.json +go clean -modcache +go mod download -reuse=all.json -x -json vcs-test.golang.org/hg/tagtests.hg@default +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Version": "v0.2.3-0.20190509225625-8d0b18b816df"' +stdout '"Query": "default"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/tagtests"' +! stdout '"TagPrefix"' +stdout '"RepoSum": "r1:8dnv906Aq1vb9YpNl9pslfva0VfG9enKb6O6NWs0xF0="' +stdout '"Ref": "default"' +stdout '"Hash": "8d0b18b816df5e9c564761b405b1d7949c24ee6b"' +! stdout '"(Dir|Info|GoMod|Zip)"' + +# reuse the bulk results with all.json +go clean -modcache +! go mod download -reuse=all.json -json vcs-test.golang.org/hg/hello.hg@latest vcs-test.golang.org/hg/hello.hg/v9@latest vcs-test.golang.org/hg/hello.hg/sub/v9@latest vcs-test.golang.org/hg/tagtests.hg@latest vcs-test.golang.org/hg/tagtests.hg@v0.2.2 vcs-test.golang.org/hg/tagtests.hg@default +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +! stdout '"(Dir|Info|GoMod|Zip)"' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_hello.txt b/src/cmd/go/testdata/script/reuse_hg_hello.txt new file mode 100644 index 00000000000000..2745610e5a0721 --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_hello.txt @@ -0,0 +1,74 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download with the pseudo-version should invoke hg but not have a TagSum or Ref or RepoSum. +go mod download -x -json vcs-test.golang.org/hg/hello.hg@v0.0.0-20170922011414-e483a7d9f8c9 +stderr 'hg( .*)* pull' +cp stdout hellopseudo.json +! stdout '"(Query|TagPrefix|TagSum|Ref|RepoSum)"' +stdout '"Version": "v0.0.0-20170922011414-e483a7d9f8c9"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/hello"' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' +! stdout '"RepoSum"' +go clean -modcache + + +# go mod download vcstest/hello should invoke hg, print origin info +go mod download -x -json vcs-test.golang.org/hg/hello.hg@latest +stderr 'hg( .*)* pull' +cp stdout hello.json +stdout '"Version": "v0.0.0-20170922011414-e483a7d9f8c9"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/hello"' +stdout '"Query": "latest"' +! stdout '"TagPrefix"' +! stdout '"TagSum"' +stdout '"Ref": "tip"' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' + +# pseudo-version again should not invoke hg pull (it has the version from the @latest query) +# but still be careful not to include a TagSum or a Ref, especially not Ref set to HEAD, +# which is easy to do when reusing the cached version from the @latest query. +go mod download -x -json vcs-test.golang.org/hg/hello.hg@v0.0.0-20170922011414-e483a7d9f8c9 +! stderr 'hg( .*)* pull' +cp stdout hellopseudo2.json +cmpenv hellopseudo.json hellopseudo2.json + +# reuse go mod download vcstest/hello pseudoversion result +go clean -modcache +go mod download -reuse=hellopseudo.json -x -json vcs-test.golang.org/hg/hello.hg@v0.0.0-20170922011414-e483a7d9f8c9 +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Version": "v0.0.0-20170922011414-e483a7d9f8c9"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/hello"' +! stdout '"(Query|TagPrefix|TagSum|Ref)"' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' + +# reuse go mod download vcstest/hello result +go clean -modcache +go mod download -reuse=hello.json -x -json vcs-test.golang.org/hg/hello.hg@latest +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Version": "v0.0.0-20170922011414-e483a7d9f8c9"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/hello"' +! stdout '"TagPrefix"' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +stdout '"Ref": "tip"' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' +! stdout '"(Dir|Info|GoMod|Zip)"' + +# clean the module cache, make sure that makes go mod download re-run hg pull, clean again +go clean -modcache +go mod download -x -json vcs-test.golang.org/hg/hello.hg@latest +stderr 'hg( .*)* pull' +go clean -modcache \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_hellohash.txt b/src/cmd/go/testdata/script/reuse_hg_hellohash.txt new file mode 100644 index 00000000000000..03544fd9d7b2fc --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_hellohash.txt @@ -0,0 +1,33 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download hg/hello@hash needs to check RepoSum to find pseudoversion base, +# which does a refreshing hg pull. +go mod download -x -json vcs-test.golang.org/hg/hello.hg@e483a7d9f8c9 +stderr 'hg( .*)* pull' +cp stdout hellohash.json +stdout '"Version": "v0.0.0-20170922011414-e483a7d9f8c9"' +stdout '"Query": "e483a7d9f8c9"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/hello"' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' + +# reuse go mod download vcstest/hello@hash +go clean -modcache +go mod download -reuse=hellohash.json -x -json vcs-test.golang.org/hg/hello.hg@e483a7d9f8c9 +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Query": "e483a7d9f8c9"' +stdout '"Version": "v0.0.0-20170922011414-e483a7d9f8c9"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/hello"' +! stdout '"(TagPrefix|Ref)"' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' +! stdout '"(Dir|Info|GoMod|Zip)"' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_hellolist.txt b/src/cmd/go/testdata/script/reuse_hg_hellolist.txt new file mode 100644 index 00000000000000..450f708b0bd0ef --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_hellolist.txt @@ -0,0 +1,43 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go list on repo with no tags +go clean -modcache +go list -x -json -m -retracted -versions vcs-test.golang.org/hg/hello.hg@latest +stderr 'hg( .*)* pull' +cp stdout hellolist.json +! stdout '"Versions"' +stdout '"Version": "v0.0.0-20170922011414-e483a7d9f8c9"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/hello"' +stdout '"Query": "latest"' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' + +# reuse go list on repo with no tags +go clean -modcache +go list -x -reuse=hellolist.json -json -m -retracted -versions vcs-test.golang.org/hg/hello.hg@latest +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +! stdout '"Versions"' +stdout '"Version": "v0.0.0-20170922011414-e483a7d9f8c9"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/hello"' +stdout '"Query": "latest"' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' + +# reuse with stale list +go clean -modcache +cp hellolist.json hellolistbad.json +replace 'blLvkhBri' 'ZZZ' hellolistbad.json +go clean -modcache +go list -x -reuse=hellolistbad.json -json -m -retracted -versions vcs-test.golang.org/hg/hello.hg@latest +stderr 'hg( .*)* pull' +! stdout '"Reuse": true' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_hellononexist.txt b/src/cmd/go/testdata/script/reuse_hg_hellononexist.txt new file mode 100644 index 00000000000000..ae475de5de288c --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_hellononexist.txt @@ -0,0 +1,26 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download vcstest/hello@nonexist should fail, still print origin info +! go mod download -x -json vcs-test.golang.org/hg/hello.hg@nonexist +cp stdout hellononexist.json +stdout '"Version": "nonexist"' +stdout '"Error":.*unknown revision nonexist' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +! stdout '"(TagPrefix|TagSum|Ref|Hash)"' + +# reuse go mod download vcstest/hello@nonexist +go clean -modcache +! go mod download -reuse=hellononexist.json -x -json vcs-test.golang.org/hg/hello.hg@nonexist +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Version": "nonexist"' +stdout '"Error":.*unknown revision nonexist' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +! stdout '"(TagPrefix|TagSum|Ref|Hash)"' +! stdout '"(Dir|Info|GoMod|Zip)"' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_hellononhash.txt b/src/cmd/go/testdata/script/reuse_hg_hellononhash.txt new file mode 100644 index 00000000000000..4073b7871bef71 --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_hellononhash.txt @@ -0,0 +1,27 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download vcstest/hello@1234567890123456789012345678901234567890 should fail, still print origin info +# (40 hex digits is assumed to be a full hash and is a slightly different code path from @nonexist) +! go mod download -x -json vcs-test.golang.org/hg/hello.hg@1234567890123456789012345678901234567890 +cp stdout hellononhash.json +stdout '"Version": "1234567890123456789012345678901234567890"' +stdout '"Error":.*unknown revision 1234567890123456789012345678901234567890' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +! stdout '"(TagPrefix|TagSum|Ref|Hash)"' + +# reuse go mod download vcstest/hello@1234567890123456789012345678901234567890 +go clean -modcache +! go mod download -reuse=hellononhash.json -x -json vcs-test.golang.org/hg/hello.hg@1234567890123456789012345678901234567890 +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Version": "1234567890123456789012345678901234567890"' +stdout '"Error":.*unknown revision 1234567890123456789012345678901234567890' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +! stdout '"(TagPrefix|TagSum|Ref|Hash)"' +! stdout '"(Dir|Info|GoMod|Zip)"' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_hellononpseudo.txt b/src/cmd/go/testdata/script/reuse_hg_hellononpseudo.txt new file mode 100644 index 00000000000000..4e5c15a7d54e51 --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_hellononpseudo.txt @@ -0,0 +1,27 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download vcstest/hello@v0.0.0-20220101120101-123456789abc should fail, still print origin info +# (non-existent pseudoversion) +! go mod download -x -json vcs-test.golang.org/hg/hello.hg@v0.0.0-20220101120101-123456789abc +cp stdout hellononpseudo.json +stdout '"Version": "v0.0.0-20220101120101-123456789abc"' +stdout '"Error":.*unknown revision 123456789abc' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +! stdout '"(TagPrefix|TagSum|Ref|Hash)"' + +# reuse go mod download vcstest/hello@v0.0.0-20220101120101-123456789abc +go clean -modcache +! go mod download -reuse=hellononpseudo.json -x -json vcs-test.golang.org/hg/hello.hg@v0.0.0-20220101120101-123456789abc +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Version": "v0.0.0-20220101120101-123456789abc"' +stdout '"Error":.*unknown revision 123456789abc' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +! stdout '"(TagPrefix|TagSum|Ref|Hash)"' +! stdout '"(Dir|Info|GoMod|Zip)"' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_hellosubv9.txt b/src/cmd/go/testdata/script/reuse_hg_hellosubv9.txt new file mode 100644 index 00000000000000..8e2f88eb67192b --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_hellosubv9.txt @@ -0,0 +1,29 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download vcstest/hello/sub/v9 should also fail, print origin info +# hg uses RepoSum instead of TagSum to describe failure condition. +! go mod download -x -json vcs-test.golang.org/hg/hello.hg/sub/v9@latest +cp stdout hellosubv9.json +stdout '"Version": "latest"' +stdout '"Error":.*no matching versions' +! stdout '"TagPrefix"' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' + +# reuse go mod download vcstest/hello/sub/v9 error result +go clean -modcache +! go mod download -reuse=hellosubv9.json -x -json vcs-test.golang.org/hg/hello.hg/sub/v9@latest +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Error":.*no matching versions' +! stdout '"TagPrefix"' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +stdout '"Ref": "tip"' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' +! stdout '"(Dir|Info|GoMod|Zip)"' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_hellov9.txt b/src/cmd/go/testdata/script/reuse_hg_hellov9.txt new file mode 100644 index 00000000000000..0f6d206e9ab53c --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_hellov9.txt @@ -0,0 +1,29 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download vcstest/hello/v9 should fail, still print origin info +# hg uses RepoSum instead of TagSum to describe failure condition. +! go mod download -x -json vcs-test.golang.org/hg/hello.hg/v9@latest +cp stdout hellov9.json +stdout '"Version": "latest"' +stdout '"Error":.*no matching versions' +! stdout '"TagPrefix"' +! stdout '"TagSum"' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' + +# reuse go mod download vcstest/hello/v9 error result +go clean -modcache +! go mod download -reuse=hellov9.json -x -json vcs-test.golang.org/hg/hello.hg/v9@latest +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Error":.*no matching versions' +! stdout '"TagPrefix"' +stdout '"RepoSum": "r1:blLvkhBriVMV[+]6Il4Ub43wlyWXIe1NpobTelF0peaG0="' +stdout '"Hash": "e483a7d9f8c9b4bc57430bdd8f81f0a65e4011c0"' +! stdout '"(Dir|Info|GoMod|Zip)"' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_prefixtagtests.txt b/src/cmd/go/testdata/script/reuse_hg_prefixtagtests.txt new file mode 100644 index 00000000000000..067e3a8a674464 --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_prefixtagtests.txt @@ -0,0 +1,36 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download vcstest/prefixtagtests should invoke hg, print origin info +go mod download -x -json vcs-test.golang.org/hg/prefixtagtests.hg/sub@latest +stderr 'hg( .*)* pull' +cp stdout prefixtagtests.json +stdout '"Version": "v0.0.10"' +stdout '"Query": "latest"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/prefixtagtests"' +stdout '"Subdir": "sub"' +stdout '"Ref": "sub/v0.0.10"' +! stdout '"TagPrefix"' +! stdout '"TagSum"' +stdout '"RepoSum": "r1:YWOcei109p5Kohsr5xnSYlaQXmpT3iWZHZhRbfMoTkc="' +stdout '"Hash": "1cc0dfcc254cb8901799e7f7ae182c04019b7a88"' + +# go mod download vcstest/prefixtagtests result with json +go clean -modcache +go mod download -reuse=prefixtagtests.json -x -json vcs-test.golang.org/hg/prefixtagtests.hg/sub@latest +! stderr 'hg( .*)* pull' +stdout '"Version": "v0.0.10"' +stdout '"Query": "latest"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/prefixtagtests"' +stdout '"Subdir": "sub"' +stdout '"RepoSum": "r1:YWOcei109p5Kohsr5xnSYlaQXmpT3iWZHZhRbfMoTkc="' +stdout '"Ref": "sub/v0.0.10"' +stdout '"Hash": "1cc0dfcc254cb8901799e7f7ae182c04019b7a88"' +! stdout '"(Dir|Info|GoMod|Zip)"' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_taglist.txt b/src/cmd/go/testdata/script/reuse_hg_taglist.txt new file mode 100644 index 00000000000000..dfd9da2e9b4765 --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_taglist.txt @@ -0,0 +1,46 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go list on repo with tags +go clean -modcache +go list -x -json -m -retracted -versions vcs-test.golang.org/hg/tagtests.hg@latest +cp stdout taglist.json +stderr 'hg( .*)* pull' +stdout '"Versions":' +stdout '"v0.2.1"' +stdout '"v0.2.2"' +stdout '"Version": "v0.2.2"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/tagtests"' +stdout '"Ref": "v0.2.2"' +stdout '"Hash": "1e531550e864b16f25013cfbbf2d8e7cf07a0374"' +stdout '"RepoSum": "r1:8dnv906Aq1vb9YpNl9pslfva0VfG9enKb6O6NWs0xF0="' + +# reuse go list on repo with tags +go clean -modcache +go list -reuse=taglist.json -x -json -m -retracted -versions vcs-test.golang.org/hg/tagtests.hg@latest +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Versions":' +stdout '"v0.2.1"' +stdout '"v0.2.2"' +stdout '"Version": "v0.2.2"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/tagtests"' +stdout '"Ref": "v0.2.2"' +stdout '"Hash": "1e531550e864b16f25013cfbbf2d8e7cf07a0374"' +stdout '"RepoSum": "r1:8dnv906Aq1vb9YpNl9pslfva0VfG9enKb6O6NWs0xF0="' + +# reuse with stale list +go clean -modcache +cp taglist.json taglistbad.json +replace '8dnv906' 'ZZZ' taglistbad.json +go list -reuse=taglistbad.json -x -json -m -retracted -versions vcs-test.golang.org/hg/tagtests.hg@latest +stderr 'hg( .*)* pull' +! stdout '"Reuse": true' +stdout '"RepoSum": "r1:8dnv906Aq1vb9YpNl9pslfva0VfG9enKb6O6NWs0xF0="' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_tagtests.txt b/src/cmd/go/testdata/script/reuse_hg_tagtests.txt new file mode 100644 index 00000000000000..c6306919c41164 --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_tagtests.txt @@ -0,0 +1,43 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download vcstest/tagtests should invoke hg, print origin info +# Need RepoSum to lock in tagged "latest". +go mod download -x -json vcs-test.golang.org/hg/tagtests.hg@latest +stderr 'hg( .*)* pull' +cp stdout tagtests.json +stdout '"Version": "v0.2.2"' +stdout '"Query": "latest"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/tagtests"' +! stdout '"TagPrefix"' +! stdout '"TagSum"' +stdout '"RepoSum": "r1:8dnv906Aq1vb9YpNl9pslfva0VfG9enKb6O6NWs0xF0="' +stdout '"Hash": "1e531550e864b16f25013cfbbf2d8e7cf07a0374"' + +# reuse go mod download vcstest/tagtests result +go clean -modcache +go mod download -reuse=tagtests.json -x -json vcs-test.golang.org/hg/tagtests.hg@latest +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Version": "v0.2.2"' +stdout '"Query": "latest"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/tagtests"' +! stdout '"TagPrefix"' +stdout '"RepoSum": "r1:8dnv906Aq1vb9YpNl9pslfva0VfG9enKb6O6NWs0xF0="' +stdout '"Hash": "1e531550e864b16f25013cfbbf2d8e7cf07a0374"' +! stdout '"(Dir|Info|GoMod|Zip)"' + +# reuse with stale RepoSum +go clean -modcache +cp tagtests.json tagtestsbadreposum.json +replace '8dnv90' '8dnv90XXX' tagtestsbadreposum.json +go mod download -reuse=tagtestsbadreposum.json -x -json vcs-test.golang.org/hg/tagtests.hg@latest +! stdout '"Reuse": true' +stdout '"RepoSum": "r1:8dnv906Aq1vb9YpNl9pslfva0VfG9enKb6O6NWs0xF0="' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_tagtestsdefault.txt b/src/cmd/go/testdata/script/reuse_hg_tagtestsdefault.txt new file mode 100644 index 00000000000000..c77efbee12be86 --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_tagtestsdefault.txt @@ -0,0 +1,34 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download vcstest/tagtests@default needs a RepoSum again +go mod download -x -json vcs-test.golang.org/hg/tagtests.hg@default +cp stdout tagtestsdefault.json +stdout '"Version": "v0.2.3-0.20190509225625-8d0b18b816df"' +stdout '"Query": "default"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/tagtests"' +! stdout '"TagPrefix"' +! stdout '"TagSum"' +stdout '"RepoSum": "r1:8dnv906Aq1vb9YpNl9pslfva0VfG9enKb6O6NWs0xF0="' +stdout '"Hash": "8d0b18b816df5e9c564761b405b1d7949c24ee6b"' + +# reuse go mod download vcstest/tagtests@default result +go clean -modcache +go mod download -reuse=tagtestsdefault.json -x -json vcs-test.golang.org/hg/tagtests.hg@default +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Version": "v0.2.3-0.20190509225625-8d0b18b816df"' +stdout '"Query": "default"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/tagtests"' +! stdout '"TagPrefix"' +stdout '"RepoSum": "r1:8dnv906Aq1vb9YpNl9pslfva0VfG9enKb6O6NWs0xF0="' +stdout '"Ref": "default"' +stdout '"Hash": "8d0b18b816df5e9c564761b405b1d7949c24ee6b"' +! stdout '"(Dir|Info|GoMod|Zip)"' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/reuse_hg_tagtestsv022.txt b/src/cmd/go/testdata/script/reuse_hg_tagtestsv022.txt new file mode 100644 index 00000000000000..aed1dfd78fbbd5 --- /dev/null +++ b/src/cmd/go/testdata/script/reuse_hg_tagtestsv022.txt @@ -0,0 +1,84 @@ +[short] skip +[!exec:hg] skip + +env GO111MODULE=on +env GOPROXY=direct +env GOSUMDB=off +env GOMODCACHE=$WORK/modcache + +# go mod download vcstest/tagtests@v0.2.2 should print origin info, no TagSum or RepoSum needed. +go mod download -x -json vcs-test.golang.org/hg/tagtests.hg@v0.2.2 +cp stdout tagtestsv022.json +stdout '"Version": "v0.2.2"' +! stdout '"Query":' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/tagtests"' +! stdout '"TagPrefix"' +! stdout '"TagSum"' +! stdout '"RepoSum"' +stdout '"Ref": "v0.2.2"' +stdout '"Hash": "1e531550e864b16f25013cfbbf2d8e7cf07a0374"' + +# reuse go mod download vcstest/tagtests@v0.2.2 result +go clean -modcache +go mod download -reuse=tagtestsv022.json -x -json vcs-test.golang.org/hg/tagtests.hg@v0.2.2 +! stderr 'hg( .*)* pull' +stdout '"Reuse": true' +stdout '"Version": "v0.2.2"' +! stdout '"Query":' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/tagtests"' +! stdout '"TagPrefix"' +! stdout '"TagSum"' +stdout '"Ref": "v0.2.2"' +stdout '"Hash": "1e531550e864b16f25013cfbbf2d8e7cf07a0374"' +! stdout '"(Dir|Info|GoMod|Zip|RepoSum)"' + +# reuse attempt with stale hash should reinvoke hg, not report reuse +go clean -modcache +cp tagtestsv022.json tagtestsv022badhash.json +replace '1e5315' '1e5315XXX' tagtestsv022badhash.json +go mod download -reuse=tagtestsv022badhash.json -x -json vcs-test.golang.org/hg/tagtests.hg@v0.2.2 +stderr 'hg( .*)* pull' +! stdout '"Reuse": true' +stdout '"Version": "v0.2.2"' +! stdout '"Query"' +stdout '"VCS": "hg"' +stdout '"URL": ".*/hg/tagtests"' +! stdout '"(TagPrefix|TagSum|RepoSum)"' +stdout '"Ref": "v0.2.2"' +stdout '"Hash": "1e531550e864b16f25013cfbbf2d8e7cf07a0374"' +stdout '"Dir"' +stdout '"Info"' +stdout '"GoMod"' +stdout '"Zip"' + +# reuse with stale repo URL +go clean -modcache +cp tagtestsv022.json tagtestsv022badurl.json +replace 'hg/tagtests\"' 'hg/tagtestsXXX\"' tagtestsv022badurl.json +go mod download -reuse=tagtestsv022badurl.json -x -json vcs-test.golang.org/hg/tagtests.hg@v0.2.2 +! stdout '"Reuse": true' +stdout '"URL": ".*/hg/tagtests"' +stdout '"Dir"' +stdout '"Info"' +stdout '"GoMod"' +stdout '"Zip"' + +# reuse with stale VCS +go clean -modcache +cp tagtestsv022.json tagtestsv022badvcs.json +replace '\"hg\"' '\"hgXXX\"' tagtestsv022badvcs.json +go mod download -reuse=tagtestsv022badvcs.json -x -json vcs-test.golang.org/hg/tagtests.hg@v0.2.2 +! stdout '"Reuse": true' +stdout '"URL": ".*/hg/tagtests"' +! stdout '"RepoSum"' + +# reuse with stale Dir +go clean -modcache +cp tagtestsv022.json tagtestsv022baddir.json +replace '\"VCS\":' '\"Subdir\":\"subdir\", \"VCS\":' tagtestsv022baddir.json +go mod download -reuse=tagtestsv022baddir.json -x -json vcs-test.golang.org/hg/tagtests.hg@v0.2.2 +! stdout '"Reuse": true' +stdout '"URL": ".*/hg/tagtests"' +! stdout '"RepoSum"' \ No newline at end of file diff --git a/src/cmd/go/testdata/script/test_buildinfo.txt b/src/cmd/go/testdata/script/test_buildinfo.txt index fbf097c0a6e6f9..2edc02dc132e97 100644 --- a/src/cmd/go/testdata/script/test_buildinfo.txt +++ b/src/cmd/go/testdata/script/test_buildinfo.txt @@ -4,15 +4,20 @@ [short] skip 'invokes go test' go mod init foo +go get example.com/version@v1.0.0 + go test -v stdout '(devel)' +stdout 'example.com/version v1.0.0' -- foo_test.go -- -package foo_test +package foo import ( "runtime/debug" "testing" + + _ "example.com/version" ) func TestBuildInfo(t *testing.T) { @@ -21,4 +26,8 @@ func TestBuildInfo(t *testing.T) { t.Fatal("no debug info") } t.Log(info.Main.Version) -} \ No newline at end of file + + for _, d := range info.Deps { + t.Log(d.Path, d.Version) + } +} diff --git a/src/cmd/go/testdata/script/test_buildvcs.txt b/src/cmd/go/testdata/script/test_buildvcs.txt index db844f88b35341..1135b899f9e6ab 100644 --- a/src/cmd/go/testdata/script/test_buildvcs.txt +++ b/src/cmd/go/testdata/script/test_buildvcs.txt @@ -31,11 +31,11 @@ go test -c -o $devnull . # When listing a main package, in general we need its VCS metadata to determine # the .Stale and .StaleReason fields. ! go list -buildvcs=true . -stderr '^go: missing Git command\. See https://golang\.org/s/gogetcmd\nerror obtaining VCS status: .*\n\tUse -buildvcs=false to disable VCS stamping.' +stderr '^go: missing Git command\. See https://go\.dev/s/gogetcmd\nerror obtaining VCS status: .*\n\tUse -buildvcs=false to disable VCS stamping.' # Adding the -test flag should be strictly additive — it should not suppress the error. ! go list -buildvcs=true -test . -stderr '^go: missing Git command\. See https://golang\.org/s/gogetcmd\nerror obtaining VCS status: .*\n\tUse -buildvcs=false to disable VCS stamping.' +stderr '^go: missing Git command\. See https://go\.dev/s/gogetcmd\nerror obtaining VCS status: .*\n\tUse -buildvcs=false to disable VCS stamping.' # Adding the suggested flag should suppress the error. go list -test -buildvcs=false . @@ -51,9 +51,9 @@ go list -test ./testonly # Again, setting -buildvcs explicitly should force the use of the VCS tool. ! go list -buildvcs ./testonly -stderr '^go: missing Git command\. See https://golang\.org/s/gogetcmd\nerror obtaining VCS status: .*\n\tUse -buildvcs=false to disable VCS stamping.' +stderr '^go: missing Git command\. See https://go\.dev/s/gogetcmd\nerror obtaining VCS status: .*\n\tUse -buildvcs=false to disable VCS stamping.' ! go list -buildvcs -test ./testonly -stderr '^go: missing Git command\. See https://golang\.org/s/gogetcmd\nerror obtaining VCS status: .*\n\tUse -buildvcs=false to disable VCS stamping.' +stderr '^go: missing Git command\. See https://go\.dev/s/gogetcmd\nerror obtaining VCS status: .*\n\tUse -buildvcs=false to disable VCS stamping.' -- go.mod -- diff --git a/src/cmd/go/testdata/script/test_cache_coverpkg_bug.txt b/src/cmd/go/testdata/script/test_cache_coverpkg_bug.txt new file mode 100644 index 00000000000000..7f85d0a680cfc3 --- /dev/null +++ b/src/cmd/go/testdata/script/test_cache_coverpkg_bug.txt @@ -0,0 +1,134 @@ +# Test for bug where cached coverage profiles with -coverpkg can contain +# outdated line references when source files are modified. +# This reproduces the issue where coverage data from cache may reference +# lines that no longer exist in the updated source files. + +[short] skip +[GODEBUG:gocacheverify=1] skip + +# We're testing cache behavior, so start with a clean GOCACHE. +env GOCACHE=$WORK/cache + +# Create a project structure with multiple packages +# proj/ +# some_func.go +# some_func_test.go +# sub/ +# sub.go +# sub_test.go +# sum/ +# sum.go + +# Switch to the proj directory +cd proj + +# Run tests with -coverpkg to collect coverage for all packages +go test -coverpkg=proj/... -coverprofile=cover1.out ./... +stdout 'coverage:' + +# Verify the first coverage profile exists and has expected content +exists cover1.out +grep -q 'proj/sub/sub.go:' cover1.out + +# Run again to ensure caching works +go test -coverpkg=proj/... -coverprofile=cover1_cached.out ./... +stdout '\(cached\)' +stdout 'coverage:' + +# Note: Due to the bug, cached coverage profiles may have duplicate entries. +# The duplicate entries are the entries for the previous file structure and the new file structure. + +# Now modify sub.go to change line structure - this will invalidate +# the cache for the sub package but not for the proj package. +cp ../sub_modified.go sub/sub.go + +# After modifying sub.go, we should not have both old and new line references. +go test -coverpkg=proj/... -coverprofile=cover2.out ./... +stdout 'coverage:' + +# With the bug present, we would see duplicate entries for the same lines. +# With the bug fixed, there should be no duplicate or stale entries in the coverage profile. +grep 'proj/sub/sub.go:' cover2.out +# The fix should ensure that only the new line format exists, not the old one +grep 'proj/sub/sub.go:4.2,4.35' cover2.out +# This should fail if the stale coverage line exists (the bug is present) +! grep 'proj/sub/sub.go:4.2,4.22' cover2.out + +-- proj/go.mod -- +module proj + +go 1.21 + +-- proj/some_func.go -- +package proj + +import "proj/sum" + +func SomeFunc(a, b int) int { + if a == 0 && b == 0 { + return 0 + } + return sum.Sum(a, b) +} + +-- proj/some_func_test.go -- +package proj + +import ( + "testing" +) + +func Test_SomeFunc(t *testing.T) { + t.Run("test1", func(t *testing.T) { + result := SomeFunc(1, 1) + if result != 2 { + t.Errorf("Expected 2, got %d", result) + } + }) +} + +-- proj/sub/sub.go -- +package sub + +func Sub(a, b int) int { + if a == 0 && b == 0 { + return 0 + } + return a - b +} + +-- proj/sub/sub_test.go -- +package sub + +import ( + "testing" +) + +func Test_Sub(t *testing.T) { + t.Run("test_sub1", func(t *testing.T) { + result := Sub(1, 1) + if result != 0 { + t.Errorf("Expected 0, got %d", result) + } + }) +} + +-- proj/sum/sum.go -- +package sum + +func Sum(a, b int) int { + if a == 0 { + return b + } + return a + b +} + +-- sub_modified.go -- +package sub + +func Sub(a, b int) int { + if a == 0 && b == 0 || a == -100 { + return 0 + } + return a - b +} diff --git a/src/cmd/go/testdata/script/test_cache_coverpkg_no_profile.txt b/src/cmd/go/testdata/script/test_cache_coverpkg_no_profile.txt new file mode 100644 index 00000000000000..263400a9e675ff --- /dev/null +++ b/src/cmd/go/testdata/script/test_cache_coverpkg_no_profile.txt @@ -0,0 +1,80 @@ +# Test that the test cache is invalidated when -coverpkg dependencies change, +# even when -coverprofile is not specified. This exercises the else-if branch +# in tryCacheWithID that checks covMeta without a cover profile file. + +[short] skip +[GODEBUG:gocacheverify=1] skip + +# Start with a clean GOCACHE. +env GOCACHE=$WORK/cache + +cd proj + +# Run tests with -cover and -coverpkg but without -coverprofile. +go test -cover -coverpkg=proj/... ./... +stdout 'coverage:' + +# Run again — should be served from cache. +go test -cover -coverpkg=proj/... ./... +stdout '\(cached\)' +stdout 'coverage:' + +# Modify a covered package that is not directly under test. +cp ../sub_modified.go sub/sub.go + +# Run again — the cache must be invalidated because a covered package changed. +go test -cover -coverpkg=proj/... ./... +! stdout '\(cached\)' +stdout 'coverage:' + +-- proj/go.mod -- +module proj + +go 1.21 + +-- proj/main.go -- +package proj + +import "proj/sub" + +func Add(a, b int) int { + return sub.Sub(a, -b) +} + +-- proj/main_test.go -- +package proj + +import "testing" + +func TestAdd(t *testing.T) { + if Add(1, 2) != 3 { + t.Fatal("expected 3") + } +} + +-- proj/sub/sub.go -- +package sub + +func Sub(a, b int) int { + return a - b +} + +-- proj/sub/sub_test.go -- +package sub + +import "testing" + +func TestSub(t *testing.T) { + if Sub(3, 1) != 2 { + t.Fatal("expected 2") + } +} + +-- sub_modified.go -- +package sub + +// Added a comment to change the source. + +func Sub(a, b int) int { + return a - b +} diff --git a/src/cmd/go/testdata/script/test_chatty_ascii.txt b/src/cmd/go/testdata/script/test_chatty_ascii.txt new file mode 100644 index 00000000000000..6d2570f626443d --- /dev/null +++ b/src/cmd/go/testdata/script/test_chatty_ascii.txt @@ -0,0 +1,24 @@ +# Make sure the ESC character isn't doubled. +! go test -v + +stdout ' x_test.go:11: \x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\n \x0b\x0c\x0d\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f\n' +stdout ' x_test.go:12: \x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\n \x0b\x0c\x0d\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f\n' +! stdout '\x1b\x1b' + +-- go.mod -- +module p + +-- x_test.go -- +package p + +import "testing" + +func Test(t *testing.T) { + var s string + for i := rune(0); i < ' '; i++ { + s += string(i) + } + + t.Log(s) + t.Error(s) +} diff --git a/src/cmd/go/testdata/script/test_fail_fast.txt b/src/cmd/go/testdata/script/test_fail_fast.txt index 1f169d6da8717b..89a304941e2739 100644 --- a/src/cmd/go/testdata/script/test_fail_fast.txt +++ b/src/cmd/go/testdata/script/test_fail_fast.txt @@ -32,6 +32,13 @@ stdout -count=5 'FAIL - ' ! go test ./failfast_test.go -run='TestParallelFailingSubtestsA' -failfast=true stdout -count=1 'FAIL - ' +# a failure in a cleanup of a test with a parallel subtest must stop failfast +# (go.dev/issue/61034) +! go test ./failfast_test.go -run='TestCleanupFailingWithParallelSubtestA|TestFailingB' -failfast=true +stdout -count=1 'FAIL - ' +! go test ./failfast_test.go -run='TestCleanupFailingWithParallelSubtestA|TestFailingB' -failfast=false +stdout -count=2 'FAIL - ' + # only parallels ! go test ./failfast_test.go -run='TestParallelFailing[AB]' -failfast=false stdout -count=2 'FAIL - ' @@ -109,6 +116,18 @@ func TestFailingSubtestsA(t *testing.T) { }) } +func TestCleanupFailingWithParallelSubtestA(t *testing.T) { + // Regression test for go.dev/issue/61034: a failure in a Cleanup + // function must be counted for -failfast even when the test has a + // parallel subtest. + t.Cleanup(func() { + t.Errorf("FAIL - %s", t.Name()) + }) + t.Run("sub", func(t *testing.T) { + t.Parallel() + }) +} + func TestFailingB(t *testing.T) { t.Errorf("FAIL - %s", t.Name()) } diff --git a/src/cmd/go/testdata/script/test_json_ascii.txt b/src/cmd/go/testdata/script/test_json_ascii.txt new file mode 100644 index 00000000000000..8e2f3b6e6fd3ba --- /dev/null +++ b/src/cmd/go/testdata/script/test_json_ascii.txt @@ -0,0 +1,27 @@ +! go test -json + +stdout '"Action":"output","Package":"p","Test":"Test","Output":"=== RUN Test\\n","OutputType":"frame"' +stdout '"Action":"output","Package":"p","Test":"Test","Output":" x_test.go:11: \\u0000\\u0001\\u0002\\u0003\\u0004\\u0005\\u0006\\u0007\\b\\t\\n"}' +stdout '"Action":"output","Package":"p","Test":"Test","Output":" \\u000b\\f\\r\\u000e\\u000f\\u0010\\u0011\\u0012\\u0013\\u0014\\u0015\\u0016\\u0017\\u0018\\u0019\\u001a\\u001b\\u001c\\u001d\\u001e\\u001f\\n"}' +stdout '"Action":"output","Package":"p","Test":"Test","Output":" x_test.go:12: \\u0000\\u0001\\u0002\\u0003\\u0004\\u0005\\u0006\\u0007\\b\\t\\n","OutputType":"error"' +stdout '"Action":"output","Package":"p","Test":"Test","Output":" \\u000b\\f\\r\\u000e\\u000f\\u0010\\u0011\\u0012\\u0013\\u0014\\u0015\\u0016\\u0017\\u0018\\u0019\\u001a\\u001b\\u001c\\u001d\\u001e\\u001f\\n","OutputType":"error-continue"' +stdout '"Action":"output","Package":"p","Test":"Test","Output":"--- FAIL: Test \([\d.]+s\)\\n","OutputType":"frame"' + +-- go.mod -- +module p + +-- x_test.go -- +package p + +import "testing" + +func Test(t *testing.T) { + var s string + for i := rune(0); i < ' '; i++ { + s += string(i) + } + + t.Log(s) + t.Error(s) +} + diff --git a/src/cmd/go/testdata/script/test_json_fails.txt b/src/cmd/go/testdata/script/test_json_fails.txt new file mode 100644 index 00000000000000..b996948d7ab885 --- /dev/null +++ b/src/cmd/go/testdata/script/test_json_fails.txt @@ -0,0 +1,18 @@ +! go test -json + +stdout '"Action":"output","Package":"p","Test":"Test","Output":"=== RUN Test\\n","OutputType":"frame"' +stdout '"Action":"output","Package":"p","Test":"Test","Output":" x_test.go:6: Error1\\n","OutputType":"error"' +stdout '"Action":"output","Package":"p","Test":"Test","Output":" Error2\\n","OutputType":"error-continue"' +stdout '"Action":"output","Package":"p","Test":"Test","Output":"--- FAIL: Test \([\d.]+s\)\\n","OutputType":"frame"' + +-- go.mod -- +module p + +-- x_test.go -- +package p + +import "testing" + +func Test(t *testing.T) { + t.Error("Error1\nError2") +} diff --git a/src/cmd/go/testdata/script/test_json_issue35169.txt b/src/cmd/go/testdata/script/test_json_issue35169.txt index fdb57556bdb8fa..4372d6ca179ffc 100644 --- a/src/cmd/go/testdata/script/test_json_issue35169.txt +++ b/src/cmd/go/testdata/script/test_json_issue35169.txt @@ -12,7 +12,7 @@ ! stdout '\{.*"Action":"pass".*\}' # TODO(#62067): emit this as a build event instead of a test event. -stdout '\{.*"Action":"output","Package":"example","Output":"FAIL\\texample \[build failed\]\\n"\}' +stdout '\{.*"Action":"output","Package":"example","Output":"FAIL\\texample \[build failed\]\\n".*\}' stdout '\{.*"Action":"fail","Package":"example",.*\}' -- go.mod -- diff --git a/src/cmd/go/testdata/script/test_json_prints.txt b/src/cmd/go/testdata/script/test_json_prints.txt index f979998068bcd1..f8bf88cee818f9 100644 --- a/src/cmd/go/testdata/script/test_json_prints.txt +++ b/src/cmd/go/testdata/script/test_json_prints.txt @@ -1,17 +1,17 @@ go test -json stdout '"Action":"output","Package":"p","Output":"M1"}' -stdout '"Action":"output","Package":"p","Test":"Test","Output":"=== RUN Test\\n"}' +stdout '"Action":"output","Package":"p","Test":"Test","Output":"=== RUN Test\\n","OutputType":"frame"}' stdout '"Action":"output","Package":"p","Test":"Test","Output":"T1"}' -stdout '"Action":"output","Package":"p","Test":"Test/Sub1","Output":"=== RUN Test/Sub1\\n"}' +stdout '"Action":"output","Package":"p","Test":"Test/Sub1","Output":"=== RUN Test/Sub1\\n","OutputType":"frame"}' stdout '"Action":"output","Package":"p","Test":"Test/Sub1","Output":"Sub1 x_test.go:19: SubLog1\\n"}' stdout '"Action":"output","Package":"p","Test":"Test/Sub1","Output":"Sub2"}' -stdout '"Action":"output","Package":"p","Test":"Test/Sub1","Output":"--- PASS: Test/Sub1 \([\d.]+s\)\\n"}' +stdout '"Action":"output","Package":"p","Test":"Test/Sub1","Output":"--- PASS: Test/Sub1 \([\d.]+s\)\\n","OutputType":"frame"}' stdout '"Action":"pass","Package":"p","Test":"Test/Sub1","Elapsed"' stdout '"Action":"output","Package":"p","Test":"Test/Sub3","Output":"foo bar"}' stdout '"Action":"output","Package":"p","Test":"Test/Sub3","Output":"baz\\n"}' stdout '"Action":"output","Package":"p","Test":"Test","Output":"T2"}' -stdout '"Action":"output","Package":"p","Test":"Test","Output":"--- PASS: Test \([\d.]+s\)\\n"}' +stdout '"Action":"output","Package":"p","Test":"Test","Output":"--- PASS: Test \([\d.]+s\)\\n","OutputType":"frame"}' stdout '"Action":"pass","Package":"p","Test":"Test","Elapsed"' stdout '"Action":"output","Package":"p","Output":"M2ok \\tp\\t[\d.]+s\\n"}' stdout '"Action":"pass","Package":"p","Elapsed"' diff --git a/src/cmd/go/testdata/script/test_main_compiler_flags.txt b/src/cmd/go/testdata/script/test_main_compiler_flags.txt new file mode 100644 index 00000000000000..e207ecae16ac92 --- /dev/null +++ b/src/cmd/go/testdata/script/test_main_compiler_flags.txt @@ -0,0 +1,22 @@ +# This is a script test conversion of TestPackageMainTestCompilerFlags +# originally added in CL 86265, which fixed #23180. +# Test that we don't pass the package name 'main' to -p when building the +# test package for a main package. + +go test -c -n p1 +# should not have run compile -p main p1.go +! stdout '([\\/]compile|gccgo).* (-p main|-fgo-pkgpath=main).*p1\.go' +! stderr '([\\/]compile|gccgo).* (-p main|-fgo-pkgpath=main).*p1\.go' +# should have run compile -p p1 p1.go +stderr '([\\/]compile|gccgo).* (-p p1|-fgo-pkgpath=p1).*p1\.go' + +-- go.mod -- +module p1 +-- p1.go -- +package main +-- p1_test.go -- +package main + +import "testing" + +func Test(t *testing.T){} diff --git a/src/cmd/go/testdata/script/test_multivcs.txt b/src/cmd/go/testdata/script/test_multivcs.txt deleted file mode 100644 index 538cbf700b4585..00000000000000 --- a/src/cmd/go/testdata/script/test_multivcs.txt +++ /dev/null @@ -1,54 +0,0 @@ -# To avoid VCS injection attacks, we should not accept multiple different VCS metadata -# folders within a single module (either in the same directory, or nested in different -# directories.) -# -# This behavior should be disabled by setting the allowmultiplevcs GODEBUG. - -[short] skip -[!git] skip - -cd samedir - -exec git init . - -# Without explicitly requesting buildvcs, the go command should silently continue -# without determining the correct VCS. -go test -c -o $devnull . - -# If buildvcs is explicitly requested, we expect the go command to fail -! go test -buildvcs -c -o $devnull . -stderr '^error obtaining VCS status: multiple VCS detected:' - -env GODEBUG=allowmultiplevcs=1 -go test -buildvcs -c -o $devnull . - -env GODEBUG= -cd ../nested -exec git init . -# cd a -go test -c -o $devnull ./a -! go test -buildvcs -c -o $devnull ./a -stderr '^error obtaining VCS status: multiple VCS detected:' -# allowmultiplevcs doesn't disable the check that the current directory, package, and -# module are in the same repository. -env GODEBUG=allowmultiplevcs=1 -! go test -buildvcs -c -o $devnull ./a -stderr '^error obtaining VCS status: main package is in repository' - --- samedir/go.mod -- -module example - -go 1.18 --- samedir/example.go -- -package main --- samedir/.bzr/test -- -hello - --- nested/go.mod -- -module example - -go 1.18 --- nested/a/example.go -- -package main --- nested/a/.bzr/test -- -hello diff --git a/src/cmd/go/testdata/script/test_vet.txt b/src/cmd/go/testdata/script/test_vet.txt index 6151f912ae0db1..5af26b54f9141b 100644 --- a/src/cmd/go/testdata/script/test_vet.txt +++ b/src/cmd/go/testdata/script/test_vet.txt @@ -16,22 +16,6 @@ go test -vet=off p1.go ! stderr '[\\/]vet.*-shift' stdout '\[no test files\]' -# ensure all runs non-default vet -! go test -vet=all ./vetall/... -stderr 'using resp before checking for errors' - -# Test issue #47309 -! go test -vet=bools,xyz ./vetall/... -stderr '-vet argument must be a supported analyzer' - -# Test with a single analyzer -! go test -vet=httpresponse ./vetall/... -stderr 'using resp before checking for errors' - -# Test with a list of analyzers -go test -vet=atomic,bools,nilfunc ./vetall/... -stdout 'm/vetall.*\[no tests to run\]' - # Test issue #22890 go test m/vetcycle stdout 'm/vetcycle.*\[no test files\]' @@ -67,21 +51,6 @@ import "fmt" func F() { fmt.Printf("%d") // oops } --- vetall/p.go -- -package p - -import "net/http" - -func F() { - resp, err := http.Head("example.com") - defer resp.Body.Close() - if err != nil { - panic(err) - } - // (defer statement belongs here) -} --- vetall/p_test.go -- -package p -- vetcycle/p.go -- package p diff --git a/src/cmd/go/testdata/script/test_vet_vetall.txt b/src/cmd/go/testdata/script/test_vet_vetall.txt new file mode 100644 index 00000000000000..6f7b6657337968 --- /dev/null +++ b/src/cmd/go/testdata/script/test_vet_vetall.txt @@ -0,0 +1,37 @@ +[short] skip + +# ensure all runs non-default vet +! go test -vet=all ./vetall/... +stderr 'using resp before checking for errors' + +# Test issue #47309 +! go test -vet=bools,xyz ./vetall/... +stderr '-vet argument must be a supported analyzer' + +# Test with a single analyzer +! go test -vet=httpresponse ./vetall/... +stderr 'using resp before checking for errors' + +# Test with a list of analyzers +go test -vet=atomic,bools,nilfunc ./vetall/... +stdout 'm/vetall.*\[no tests to run\]' + +-- go.mod -- +module m + +go 1.16 +-- vetall/p.go -- +package p + +import "net/http" + +func F() { + resp, err := http.Head("example.com") + defer resp.Body.Close() + if err != nil { + panic(err) + } + // (defer statement belongs here) +} +-- vetall/p_test.go -- +package p diff --git a/src/cmd/go/testdata/script/tool_build_as_needed.txt b/src/cmd/go/testdata/script/tool_build_as_needed.txt index 8868ed3085b490..e9bb8d34f356b3 100644 --- a/src/cmd/go/testdata/script/tool_build_as_needed.txt +++ b/src/cmd/go/testdata/script/tool_build_as_needed.txt @@ -40,13 +40,15 @@ rm $TOOLDIR/test2json$GOEXE go tool -n test2json ! stdout $NEWTOOLDIR${/}test2json$GOEXE # Set GOOS/GOARCH to different values than host GOOS/GOARCH. -env GOOS=windows -[GOOS:windows] env GOOS=linux -env GOARCH=arm64 -[GOARCH:arm64] env GOARCH=amd64 +env GOOS=js +env GOARCH=wasm # Control case: go run shouldn't work because it respects # GOOS/GOARCH, and we can't execute non-native binary. -! go run cmd/test2json -exec='' -# But go tool should because it doesn't respect GOOS/GOARCH. +# Don't actually run the binary because maybe we can. +# (Maybe the user has a go_js_wasm_exec installed.) +# Instead just look to see that the right binary got linked. +go run -n cmd/test2json +stderr modinfo.*GOARCH=wasm.*GOOS=js +# go tool should succeed because it doesn't respect GOOS/GOARCH. go tool test2json stdout '{"Action":"start"}' diff --git a/src/cmd/go/testdata/script/tool_exename.txt b/src/cmd/go/testdata/script/tool_exename.txt index a8dba8409f7057..584ee704138cdd 100644 --- a/src/cmd/go/testdata/script/tool_exename.txt +++ b/src/cmd/go/testdata/script/tool_exename.txt @@ -38,6 +38,16 @@ env GOCACHE=$WORK/cache2 go run example.com/foo/v2 stdout 'my name is: foo'$GOEXE +# list aliases for tools +go tool +stdout '^bar \(example.com/foo/bar\)$' +! stdout '^example.com/foo/bar$' +stdout '^foo \(example.com/foo/v2\)$' +! stdout '^example.com/foo/v2$' +stdout '^example.com/foo/noalias$' +! stdout '^noalias \(example.com/foo/noalias\)$' +stdout '^example.com/foo/noalias/noalias$' +! stdout '^noalias \(example.com/foo/noalias\)$' -- go.mod -- module example.com/foo @@ -45,6 +55,8 @@ go 1.24 tool example.com/foo/bar tool example.com/foo/v2 +tool example.com/foo/noalias +tool example.com/foo/noalias/noalias require example.com/foo/v2 v2.0.0 @@ -77,3 +89,11 @@ import ( func main() { fmt.Println("my name is:", filepath.Base(os.Args[0])) } + +-- noalias/noalias.go -- +package main + +func main() {} +-- noalias/noalias/noalias.go -- +pagckage main +func main() {} \ No newline at end of file diff --git a/src/cmd/go/testdata/script/tool_name.txt b/src/cmd/go/testdata/script/tool_name.txt new file mode 100644 index 00000000000000..d3f0f8cf5e20b6 --- /dev/null +++ b/src/cmd/go/testdata/script/tool_name.txt @@ -0,0 +1,22 @@ +[short] skip 'runs go build' + +# Tool name can't be empty. Issue #74757. +! go tool '' +stderr 'go: no such tool ""' + +! go tool -n '' +stderr 'go: no such tool ""' + +# Invalid tool name +! go tool @ +stderr 'go: no such tool "@"' + +! go tool -n @ +stderr 'go: no such tool "@"' + +-- go.mod -- +module example.com/foo + +go 1.24 +-- main.go -- +package main diff --git a/src/cmd/go/testdata/script/tool_signal_exit.txt b/src/cmd/go/testdata/script/tool_signal_exit.txt new file mode 100644 index 00000000000000..86f7f281d26566 --- /dev/null +++ b/src/cmd/go/testdata/script/tool_signal_exit.txt @@ -0,0 +1,29 @@ +[short] skip 'runs go build' +[GOOS:plan9] skip 'signals differ on Plan 9' +[GOOS:windows] skip 'os.Interrupt is not implemented on Windows' + +! go tool interrupter +stderr 'go tool interrupter: signal: interrupt' + +-- go.mod -- +module example.com/interrupter + +go 1.26.0 + +tool example.com/interrupter/cmd/interrupter + +-- cmd/interrupter/main.go -- +package main + +import "os" + +func main() { + p, err := os.FindProcess(os.Getpid()) + if err != nil { + panic(err) + } + if err := p.Signal(os.Interrupt); err != nil { + panic(err) + } + select {} +} diff --git a/src/cmd/go/testdata/script/version_buildvcs_bzr.txt b/src/cmd/go/testdata/script/version_buildvcs_bzr.txt deleted file mode 100644 index fd0b80c40a9eaf..00000000000000 --- a/src/cmd/go/testdata/script/version_buildvcs_bzr.txt +++ /dev/null @@ -1,129 +0,0 @@ -# This test checks that VCS information is stamped into Go binaries by default, -# controlled with -buildvcs. This test focuses on Bazaar specifics. -# The Git test covers common functionality. - -[short] skip -[!bzr] skip 'requires a working bzr client' -env GOBIN=$WORK/gopath/bin -env oldpath=$PATH -env HOME=$WORK -cd repo/a -exec bzr whoami 'J.R. Gopher ' - -# If there's no local repository, there's no VCS info. -go install -go version -m $GOBIN/a$GOEXE -! stdout bzrrevision -stdout '^\tmod\texample.com/a\t\(devel\)' -rm $GOBIN/a$GOEXE - -# If there is a repository, but it can't be used for some reason, -# there should be an error. It should hint about -buildvcs=false. -cd .. -mkdir .bzr -env PATH=$WORK${/}fakebin${:}$oldpath -chmod 0755 $WORK/fakebin/bzr -! exec bzr help -cd a -! go install -stderr '^error obtaining VCS status: exit status 1\n\tUse -buildvcs=false to disable VCS stamping.$' -rm $GOBIN/a$GOEXE -cd .. -env PATH=$oldpath -rm .bzr - -# If there is an empty repository in a parent directory, only "modified" is tagged. -exec bzr init -cd a -go install -go version -m $GOBIN/a$GOEXE -stdout '^\tbuild\tvcs=bzr$' -! stdout vcs.revision -! stdout vcs.time -stdout '^\tbuild\tvcs.modified=true$' -cd .. - -# Revision and commit time are tagged for repositories with commits. -exec bzr add a README go.mod -exec bzr commit -m 'initial commit' -cd a -go install -go version -m $GOBIN/a$GOEXE -stdout '^\tbuild\tvcs=bzr$' -stdout '^\tbuild\tvcs.revision=' -stdout '^\tbuild\tvcs.time=' -stdout '^\tbuild\tvcs.modified=false$' -stdout '^\tmod\texample.com/a\tv0.0.0-\d+-\d+\t+' -rm $GOBIN/a$GOEXE - -# Tag is reflected in the version. -cd .. -cp README README2 -exec bzr add a README2 -exec bzr commit -m 'second commit' -exec bzr tag a/v1.2.3 -cd a -go install -go version -m $GOBIN/a$GOEXE -stdout '^\tbuild\tvcs=bzr$' -stdout '^\tbuild\tvcs.revision=' -stdout '^\tbuild\tvcs.time=' -stdout '^\tbuild\tvcs.modified=false$' -stdout '^\tmod\texample.com/a\tv1.2.3\t+' -rm $GOBIN/a$GOEXE - -# Building an earlier commit should still build clean. -cp ../../outside/empty.txt ../NEWS -exec bzr add ../NEWS -exec bzr commit -m 'add NEWS' -exec bzr update -r1 -go install -go version -m $GOBIN/a$GOEXE -stdout '^\tbuild\tvcs=bzr$' -stdout '^\tbuild\tvcs.revision=' -stdout '^\tbuild\tvcs.time=' -stdout '^\tbuild\tvcs.modified=false$' - -# Building with -buildvcs=false suppresses the info. -go install -buildvcs=false -go version -m $GOBIN/a$GOEXE -! stdout vcs.revision -rm $GOBIN/a$GOEXE - -# An untracked file is shown as modified, even if it isn't part of the build. -cp ../../outside/empty.txt . -go install -go version -m $GOBIN/a$GOEXE -stdout '^\tbuild\tvcs.modified=true$' -rm empty.txt -rm $GOBIN/a$GOEXE - -# An edited file is shown as modified, even if it isn't part of the build. -cp ../../outside/empty.txt ../README -go install -go version -m $GOBIN/a$GOEXE -stdout '^\tbuild\tvcs.modified=true$' -exec bzr revert ../README -rm $GOBIN/a$GOEXE - --- $WORK/fakebin/bzr -- -#!/bin/sh -exit 1 --- $WORK/fakebin/bzr.bat -- -exit 1 --- repo/README -- -Far out in the uncharted backwaters of the unfashionable end of the western -spiral arm of the Galaxy lies a small, unregarded yellow sun. --- repo/go.mod -- -module example.com - -go 1.18 --- repo/a/go.mod -- -module example.com/a - -go 1.18 --- repo/a/a.go -- -package main - -func main() {} --- outside/empty.txt -- diff --git a/src/cmd/go/testdata/script/version_buildvcs_git_worktree.txt b/src/cmd/go/testdata/script/version_buildvcs_git_worktree.txt new file mode 100644 index 00000000000000..651d1699cece62 --- /dev/null +++ b/src/cmd/go/testdata/script/version_buildvcs_git_worktree.txt @@ -0,0 +1,46 @@ +# Test that 'go build' stamps VCS information when building from a git worktree. +# See https://go.dev/issue/58218. + +[!git] skip +[short] skip + +# Create repo with a commit. +cd repo +exec git init +exec git config user.email g.o.p.h.e.r@go.dev +exec git config user.name Gopher +exec git add -A +exec git commit -m 'initial commit' + +# Sanity check: building from main repo includes VCS info. +go build -o main.exe . +go version -m main.exe +stdout '^\tbuild\tvcs=git$' +stdout '^\tbuild\tvcs.modified=false$' + +# Create a worktree and build from it. +exec git worktree add ../worktree HEAD +cd ../worktree +go build -o worktree.exe . +go version -m worktree.exe +stdout '^\tbuild\tvcs=git$' +stdout '^\tbuild\tvcs.modified=false$' + +# Verify that vcs.modified is detected in the worktree. +cp ../changed.go a.go +go build -o modified.exe . +go version -m modified.exe +stdout '^\tbuild\tvcs.modified=true$' + +-- repo/go.mod -- +module example.com/worktree + +go 1.18 +-- repo/a.go -- +package main + +func main() {} +-- changed.go -- +package main + +func main() { _ = 1 } diff --git a/src/cmd/go/testdata/script/version_goexperiment.txt b/src/cmd/go/testdata/script/version_goexperiment.txt index 4b165eb6055447..23fc57d456d52c 100644 --- a/src/cmd/go/testdata/script/version_goexperiment.txt +++ b/src/cmd/go/testdata/script/version_goexperiment.txt @@ -12,5 +12,13 @@ stderr 'X:fieldtrack$' -- version.go -- package main -import "runtime" -func main() { println(runtime.Version()) } +import ( + "go/version" + "runtime" +) +func main() { + if !version.IsValid(runtime.Version()) { + panic("version not valid: "+runtime.Version()) + } + println(runtime.Version()) +} diff --git a/src/cmd/go/testdata/script/vet_asm.txt b/src/cmd/go/testdata/script/vet_asm.txt index c046773a06c0dc..f29e5b7067e1e3 100644 --- a/src/cmd/go/testdata/script/vet_asm.txt +++ b/src/cmd/go/testdata/script/vet_asm.txt @@ -2,6 +2,7 @@ env GO111MODULE=off env GOARCH=amd64 +env GOOS=linux ! go vet -asmdecl a stderr 'f: invalid MOVW of x' diff --git a/src/cmd/go/testdata/script/vet_basic.txt b/src/cmd/go/testdata/script/vet_basic.txt index 5ae66438ea3d81..faff586fcb07b2 100644 --- a/src/cmd/go/testdata/script/vet_basic.txt +++ b/src/cmd/go/testdata/script/vet_basic.txt @@ -28,8 +28,8 @@ stdout '"message": "address format .* does not work with IPv6",' stdout '"suggested_fixes":' stdout '"message": "Replace fmt.Sprintf with net.JoinHostPort",' -# vet -fix -diff displays a diff. -go vet -fix -diff example.com/x +# vet -fix -diff displays a diff. Diff => nonzero exit. +! go vet -fix -diff example.com/x stdout '\-var _ = fmt.Sprintf\(s\)' stdout '\+var _ = fmt.Sprintf\("%s", s\)' stdout '\-var _, _ = net.Dial\("tcp", fmt.Sprintf\("%s:%d", s, 80\)\)' @@ -53,8 +53,8 @@ grep 'net.JoinHostPort' x.go ! stderr . cp x.go.bak x.go -# Show diff of fixes from the fix suite. -go fix -diff example.com/x +# Show diff of fixes from the fix suite. Diff => nonzero exit. +! go fix -diff example.com/x ! stdout '\-var _ = fmt.Sprintf\(s\)' stdout '\-var _, _ = net.Dial\("tcp", fmt.Sprintf\("%s:%d", s, 80\)\)' stdout '\+var _, _ = net.Dial\("tcp", net.JoinHostPort\(s, "80"\)\)' @@ -91,6 +91,7 @@ stderr '-json and -diff cannot be used together' # Legacy way of selecting fixers is a no-op. go fix -fix=old1,old2 example.com/x stderr 'go fix: the -fix=old1,old2 flag is obsolete and has no effect' +cp x.go.bak x.go # -c=n flag shows n lines of context. ! go vet -c=2 -printf example.com/x diff --git a/src/cmd/go/testdata/script/vet_cache.txt b/src/cmd/go/testdata/script/vet_cache.txt index c84844000a43d0..3871352d91b670 100644 --- a/src/cmd/go/testdata/script/vet_cache.txt +++ b/src/cmd/go/testdata/script/vet_cache.txt @@ -1,6 +1,8 @@ # Test that go vet's caching of vet tool actions replays # the recorded stderr output even after a cache hit. +[short] skip 'uses a fresh build cache' + # Set up fresh GOCACHE. env GOCACHE=$WORK/gocache @@ -13,6 +15,14 @@ stderr 'fmt.Sprint call has possible Printf formatting directive' ! go vet example.com/a stderr 'fmt.Sprint call has possible Printf formatting directive' +# Vetting example.com/a only as a dependency of example.com/b +# records facts but reports no diagnostics. A later +# 'go vet example.com/a' must not reuse that result. +env GOCACHE=$WORK/gocache2 +go vet example.com/b +! go vet example.com/a +stderr 'fmt.Sprint call has possible Printf formatting directive' + -- go.mod -- module example.com @@ -22,3 +32,8 @@ package a import "fmt" var _ = fmt.Sprint("%s") // oops! + +-- b/b.go -- +package b + +import _ "example.com/a" diff --git a/src/cmd/go/testdata/script/vet_flags.txt b/src/cmd/go/testdata/script/vet_flags.txt index 21606dc4f1dfc8..e274dbedb39bd8 100644 --- a/src/cmd/go/testdata/script/vet_flags.txt +++ b/src/cmd/go/testdata/script/vet_flags.txt @@ -20,7 +20,8 @@ stderr '-unsafeptr' ! stderr '-unsafeptr=false' # -unreachable is disabled during test but on during plain vet. -go test -n runtime +# The -a makes sure the vet result is not cached, or else we won't print the command line. +go test -a -n runtime stderr '-unreachable=false' # A flag terminator should be allowed before the package list. @@ -63,16 +64,16 @@ go test -n -vet= -run=none . stderr '[/\\]vet'$GOEXE'["]? .* -errorsas .* ["]?\$WORK[/\\][^ ]*[/\\]vet\.cfg' # "go test" on a standard package should by default disable an explicit list. -go test -n -run=none encoding/binary +go test -a -n -run=none encoding/binary stderr '[/\\]vet'$GOEXE'["]? -unsafeptr=false -unreachable=false ["]?\$WORK[/\\][^ ]*[/\\]vet\.cfg' -go test -n -vet= -run=none encoding/binary +go test -a -n -vet= -run=none encoding/binary stderr '[/\\]vet'$GOEXE'["]? -unsafeptr=false -unreachable=false ["]?\$WORK[/\\][^ ]*[/\\]vet\.cfg' # Both should allow users to override via the -vet flag. -go test -n -vet=unreachable -run=none . +go test -a -n -vet=unreachable -run=none . stderr '[/\\]vet'$GOEXE'["]? -unreachable ["]?\$WORK[/\\][^ ]*[/\\]vet\.cfg' -go test -n -vet=unreachable -run=none encoding/binary +go test -a -n -vet=unreachable -run=none encoding/binary stderr '[/\\]vet'$GOEXE'["]? -unreachable ["]?\$WORK[/\\][^ ]*[/\\]vet\.cfg' -- go.mod -- diff --git a/src/cmd/go/testdata/script/work_edit.txt b/src/cmd/go/testdata/script/work_edit.txt index 021346653fb6e3..75a281f0a8ffb6 100644 --- a/src/cmd/go/testdata/script/work_edit.txt +++ b/src/cmd/go/testdata/script/work_edit.txt @@ -31,7 +31,7 @@ cmp go.work go.work.want_dropreplace go work edit -print -go 1.19 -use b -dropuse c -replace 'x.1@v1.4.0 = ../z' -dropreplace x.1 -dropreplace x.1@v1.3.0 cmp stdout go.work.want_print -go work edit -json -go 1.19 -use b -dropuse c -replace 'x.1@v1.4.0 = ../z' -dropreplace x.1 -dropreplace x.1@v1.3.0 +go work edit -json -go 1.19 -use b -dropuse c -replace 'x.1@v1.4.0 = ../z' -dropreplace x.1 -dropreplace x.1@v1.3.0 -toolchain go1.20 -godebug key=value cmp stdout go.work.want_json # go work edit -godebug @@ -131,6 +131,13 @@ replace x.1 v1.4.0 => ../z -- go.work.want_json -- { "Go": "1.19", + "Toolchain": "go1.20", + "Godebug": [ + { + "Key": "key", + "Value": "value" + } + ], "Use": [ { "DiskPath": "../a" diff --git a/src/cmd/go/testdata/script/work_goline_order.txt b/src/cmd/go/testdata/script/work_goline_order.txt index fe1cddbcd4a592..bfba7f462be7d9 100644 --- a/src/cmd/go/testdata/script/work_goline_order.txt +++ b/src/cmd/go/testdata/script/work_goline_order.txt @@ -7,7 +7,7 @@ env TESTGO_VERSION=go1.21.1 env TESTGO_VERSION_SWITCH=switch cp go.work go.work.orig ! go list -stderr '^go: module . listed in go.work file requires go >= 1.21.2, but go.work lists go 1.21.1; to update it:\n\tgo work use$' +stderr '^go: module . listed in go.work file requires go >= 1.21.2, but go.work lists go 1.21.1; to download and use go 1.21.2:\n\tgo work use$' go work use go list @@ -16,7 +16,7 @@ env TESTGO_VERSION=go1.21.2 env TESTGO_VERSION_SWITCH=switch cp go.work.orig go.work ! go list -stderr '^go: module . listed in go.work file requires go >= 1.21.2, but go.work lists go 1.21.1; to update it:\n\tgo work use$' +stderr '^go: module . listed in go.work file requires go >= 1.21.2, but go.work lists go 1.21.1; to download and use go 1.21.2:\n\tgo work use$' # go work use fixes the problem. go work use diff --git a/src/cmd/go/testdata/script/work_implicit_go_requirement.txt b/src/cmd/go/testdata/script/work_implicit_go_requirement.txt index e123a7b01a5c1b..021d95c63d2a03 100644 --- a/src/cmd/go/testdata/script/work_implicit_go_requirement.txt +++ b/src/cmd/go/testdata/script/work_implicit_go_requirement.txt @@ -2,7 +2,7 @@ # go directive in a go.work file so 1.18 is implicitly required. ! go list -stderr 'go: module . listed in go.work file requires go >= 1.21, but go.work implicitly requires go 1.18; to update it:\s+go work use' +stderr 'go: module . listed in go.work file requires go >= 1.21, but go.work implicitly requires go 1.18; to download and use go 1.21:\s+go work use' go work use go list diff --git a/src/cmd/go/testdata/script/work_sync_check_multiple_paths_once.txt b/src/cmd/go/testdata/script/work_sync_check_multiple_paths_once.txt new file mode 100644 index 00000000000000..bc2fd1f1209b59 --- /dev/null +++ b/src/cmd/go/testdata/script/work_sync_check_multiple_paths_once.txt @@ -0,0 +1,56 @@ +# Test that checkMultiplePaths reports errors exactly once in a workspace with +# multiple modules, even though it is called once per workspace module. +# +# example.com/a and example.com/b are both replaced by ../shared (which +# canonicalizes to the same path in workspace mode), triggering a "used for +# two different module paths" error. With three workspace modules the check +# is called three times; the error should appear in stderr exactly once. + +go work sync +stderr -count=1 'used for two different module paths' + +-- go.work -- +go 1.18 + +use ( + ./m + ./n + ./o +) + +-- m/go.mod -- +module example.com/m + +go 1.18 + +require example.com/a v1.0.0 + +replace example.com/a v1.0.0 => ../shared + +-- m/m.go -- +package m + +-- n/go.mod -- +module example.com/n + +go 1.18 + +require example.com/b v1.0.0 + +replace example.com/b v1.0.0 => ../shared + +-- n/n.go -- +package n + +-- o/go.mod -- +module example.com/o + +go 1.18 + +-- o/o.go -- +package o + +-- shared/go.mod -- +module example.com/shared + +go 1.18 diff --git a/src/cmd/go/testdata/script/work_sync_replace.txt b/src/cmd/go/testdata/script/work_sync_replace.txt new file mode 100644 index 00000000000000..79764ddc77bd0c --- /dev/null +++ b/src/cmd/go/testdata/script/work_sync_replace.txt @@ -0,0 +1,65 @@ +go work sync + +cmp a/go.mod a/go.mod.want +cmp b/go.mod b/go.mod.want +-- go.work -- +go 1.27 + +use ( + ./a + ./b +) +-- a/go.mod -- +module example.com/a + +go 1.27 + +replace example.com/syncreplace v1.1.0 => example.com/syncreplace v1.0.0 + +require ( + example.com/syncreplace v1.1.0 + rsc.io/quote v1.0.0 +) +-- a/go.mod.want -- +module example.com/a + +go 1.27 + +replace example.com/syncreplace v1.1.0 => example.com/syncreplace v1.0.0 + +require ( + example.com/syncreplace v1.1.0 + rsc.io/quote v1.0.0 +) +-- a/a.go -- +package a + +import ( + _ "example.com/syncreplace" + _ "rsc.io/quote" +) +-- b/go.mod -- +module example.com/b + +go 1.27 + +require ( + example.com/syncreplace v1.1.0 + rsc.io/quote v1.0.0 +) +-- b/go.mod.want -- +module example.com/b + +go 1.27 + +require ( + example.com/syncreplace v1.1.0 + rsc.io/quote v1.1.0 +) +-- b/b.go -- +package b + +import ( + _ "example.com/syncreplace" + _ "rsc.io/quote" +) \ No newline at end of file diff --git a/src/cmd/go/testdata/script/work_use_vendor.txt b/src/cmd/go/testdata/script/work_use_vendor.txt new file mode 100644 index 00000000000000..9a61db0ddfffd2 --- /dev/null +++ b/src/cmd/go/testdata/script/work_use_vendor.txt @@ -0,0 +1,126 @@ +# Test that 'go work use -r' skips vendor directories. +# See https://go.dev/issue/51710. + +# Scenario 1: Basic recursive use should skip all vendor directories. +# - Top-level vendor/ should be excluded. +# - Nested vendor/ under submodules (sub/vendor/) should be excluded. +# - Deeply nested vendor/a/vendor/ should be excluded (already unreachable via SkipDir). +# - vendor/ under a non-module directory (subdir/vendor/) should also be excluded, +# because d.Name() == "vendor" skips all directories named "vendor" regardless +# of whether the parent is a module. +# - A directory named "notvendor" or "myvendor" should NOT be excluded. +go work use -r . +cmp go.work go.work.want_recursive + +# Scenario 2: Non-recursive 'go work use' on a directory named "vendor" +# should still work — the vendor skip only applies to -r walks. +go work use vendor/example.com/dep +cmp go.work go.work.want_explicit_vendor + +# Scenario 3: Re-running recursive use from clean state should produce +# consistent results. +cp go.work.clean go.work +go work use -r . +cmp go.work go.work.want_recursive + +-- go.work -- +go 1.24 + +-- go.work.clean -- +go 1.24 + +-- go.work.want_recursive -- +go 1.24 + +use ( + . + ./myvendor + ./notvendor + ./sub + ./subdir +) +-- go.work.want_explicit_vendor -- +go 1.24 + +use ( + . + ./myvendor + ./notvendor + ./sub + ./subdir + ./vendor/example.com/dep +) +-- go.mod -- +module example.com/main + +go 1.24 + +-- main.go -- +package main + +-- sub/go.mod -- +module example.com/sub + +go 1.24 + +-- sub/main.go -- +package sub + +-- subdir/go.mod -- +module example.com/subdir + +go 1.24 + +-- subdir/main.go -- +package subdir + +# subdir/vendor/ contains a module, but it is skipped by 'go work use -r' +# because all directories named "vendor" are skipped, not just those at +# the root of a module with an existing vendor directory. +-- subdir/vendor/example.com/vendored/go.mod -- +module example.com/vendored + +go 1.24 + +-- subdir/vendor/example.com/vendored/vendored.go -- +package vendored + +-- vendor/example.com/dep/go.mod -- +module example.com/dep + +go 1.24 + +-- vendor/example.com/dep/dep.go -- +package dep + +-- sub/vendor/example.com/subdep/go.mod -- +module example.com/subdep + +go 1.24 + +-- sub/vendor/example.com/subdep/subdep.go -- +package subdep + +-- vendor/example.com/dep/vendor/example.com/transitive/go.mod -- +module example.com/transitive + +go 1.24 + +-- vendor/example.com/dep/vendor/example.com/transitive/transitive.go -- +package transitive + +-- notvendor/go.mod -- +module example.com/notvendor + +go 1.24 + +-- notvendor/main.go -- +package notvendor + +-- myvendor/go.mod -- +module example.com/myvendor + +go 1.24 + +-- myvendor/main.go -- +package myvendor diff --git a/src/cmd/go/testdata/vcstest/auth/githttp401.txt b/src/cmd/go/testdata/vcstest/auth/githttp401.txt new file mode 100644 index 00000000000000..1b7cc44235149f --- /dev/null +++ b/src/cmd/go/testdata/vcstest/auth/githttp401.txt @@ -0,0 +1,10 @@ +handle auth + +-- .access -- +{ + "Username": "aladdin", + "Password": "opensesame", + "StatusCode": 401, + "Message": "ACCESS DENIED, buddy" +} +-- info/refs -- diff --git a/src/cmd/go/testdata/vcstest/bzr/hello.txt b/src/cmd/go/testdata/vcstest/bzr/hello.txt deleted file mode 100644 index 68465ec553bd55..00000000000000 --- a/src/cmd/go/testdata/vcstest/bzr/hello.txt +++ /dev/null @@ -1,34 +0,0 @@ -[!bzr] skip 'requires a working bzr client' -handle bzr - -env BZR_EMAIL='Russ Cox ' -env EMAIL='Russ Cox ' - -bzr init-repo . - -bzr init b -cd b -cp ../hello.go . -bzr add hello.go -bzr commit --commit-time='2017-09-21 21:20:12 -0400' -m 'hello world' -bzr push .. -cd .. -rm b - -bzr log -cmp stdout .bzr-log - --- .bzr-log -- ------------------------------------------------------------- -revno: 1 -committer: Russ Cox -branch nick: b -timestamp: Thu 2017-09-21 21:20:12 -0400 -message: - hello world --- hello.go -- -package main - -func main() { - println("hello, world") -} diff --git a/src/cmd/go/testdata/vcstest/git/export-subst.txt b/src/cmd/go/testdata/vcstest/git/export-subst.txt new file mode 100644 index 00000000000000..47ecb1df10ba70 --- /dev/null +++ b/src/cmd/go/testdata/vcstest/git/export-subst.txt @@ -0,0 +1,23 @@ +handle git + +env GIT_AUTHOR_NAME='Gopher' +env GIT_AUTHOR_EMAIL='gopher@golang.org' +env GIT_COMMITTER_NAME=$GIT_AUTHOR_NAME +env GIT_COMMITTER_EMAIL=$GIT_AUTHOR_EMAIL + +git init + +at 2018-09-27T20:40:31+00:00 + +git add .gitattributes go.mod export_subst.go +git commit -m 'initial commit' +git branch -m master + +-- .gitattributes -- +export_subst.go export-subst +-- go.mod -- +module vcs-test.golang.org/git/export-subst.git +-- export_subst.go -- +package export_subst + +const CommitHash = "$Format:%H$" diff --git a/src/cmd/go/testdata/vcstest/git/gitrepo-sha256.txt b/src/cmd/go/testdata/vcstest/git/gitrepo-sha256.txt index 81b9a71c12593d..a08e2949d3142a 100644 --- a/src/cmd/go/testdata/vcstest/git/gitrepo-sha256.txt +++ b/src/cmd/go/testdata/vcstest/git/gitrepo-sha256.txt @@ -1,3 +1,5 @@ +[!git-sha256] skip + handle git # This is a sha256 version of gitrepo1.txt (which uses sha1 hashes) diff --git a/src/cmd/go/testdata/vcstest/git/invalid-version.txt b/src/cmd/go/testdata/vcstest/git/invalid-version.txt new file mode 100644 index 00000000000000..60fc30f781766c --- /dev/null +++ b/src/cmd/go/testdata/vcstest/git/invalid-version.txt @@ -0,0 +1,55 @@ +handle git + +env GIT_AUTHOR_NAME='Michael Matloob' +env GIT_AUTHOR_EMAIL='matloob@golang.org' +env GIT_COMMITTER_NAME=$GIT_AUTHOR_NAME +env GIT_COMMITTER_EMAIL=$GIT_AUTHOR_EMAIL + +at 2017-09-15T03:28:32-00:00 + +git init +git commit --allow-empty -m 'initial commit' +git branch -m main +git tag v0.1.0 +git tag v3.1.0 + +git add go.mod +git commit -m 'create module invalid-version' + +git add unicode/unicode.go +git commit -m 'add unicode package' + +at 2017-12-13T10:25:48-00:00 + +git add unicode/unicode2.go +git commit -m 'another commit with tag' +git tag v0.2.0 +git tag v4.0.0 + +git add 3.txt +git commit -m 'yet another commit' + +git rm go.mod +git commit -m 'remove go.mod' + +git tag v5.0.0 + +git log --oneline --decorate=short +cmp stdout .git-log + +-- .git-log -- +dbb861d (HEAD -> main, tag: v5.0.0) remove go.mod +5213b9f yet another commit +a72be5e (tag: v4.0.0, tag: v0.2.0) another commit with tag +90ac26b add unicode package +1732873 create module invalid-version +d047a7b (tag: v3.1.0, tag: v0.1.0) initial commit +-- go.mod -- +module vcs-test.golang.org/go/invalid-version + +go 1.26.0 +-- 3.txt -- +-- unicode/unicode.go -- +package unicode +-- unicode/unicode2.go -- +package unicode \ No newline at end of file diff --git a/src/cmd/go/testdata/vcstest/git/legacytest.txt b/src/cmd/go/testdata/vcstest/git/legacytest.txt new file mode 100644 index 00000000000000..6465242d6211f2 --- /dev/null +++ b/src/cmd/go/testdata/vcstest/git/legacytest.txt @@ -0,0 +1,118 @@ +handle git + +env GIT_AUTHOR_NAME='Russ Cox' +env GIT_AUTHOR_EMAIL='rsc@golang.org' +env GIT_COMMITTER_NAME=$GIT_AUTHOR_NAME +env GIT_COMMITTER_EMAIL=$GIT_AUTHOR_EMAIL + +git init +git checkout -b master + +at 2018-07-17T12:41:39-04:00 +cp x_cf92c7b.go x.go +git add x.go +git commit -m 'initial commit' + +at 2018-07-17T12:41:57-04:00 +cp x_52853eb.go x.go +git commit -m 'add X' x.go + +at 2018-07-17T12:42:07-04:00 +cp x_7fff7f3.go x.go +git commit -m 'gofmt' x.go +git tag v1.0.0 + +at 2018-07-17T12:42:28-04:00 +cp x_fa4f5d6.go x.go +git commit -m 'X->XX' x.go + +at 2018-07-17T12:42:36-04:00 +cp x_d7ae1e4.go x.go +git commit -m 'gofmt' x.go +git tag v2.0.0 + +at 2018-07-17T12:42:53-04:00 +cp x_7303f77.go x.go +git commit -m 'add XXX' x.go + +at 2018-07-17T12:47:59-04:00 +git checkout v1.0.0 +cp x_1abc5ff.go x.go +git commit -m 'comment' x.go + +at 2018-07-17T12:48:22-04:00 +cp x_731e3b1.go x.go +git commit -m 'prerelease' x.go +git tag v1.1.0-pre + +at 2018-07-17T12:48:49-04:00 +cp x_fb3c628.go x.go +git commit -m 'working' x.go + +at 2018-07-17T12:49:05-04:00 +cp x_9f6f860.go x.go +git commit -m 'v1.2.0' x.go +git tag v1.2.0 + +at 2018-07-17T12:49:42-04:00 +cp x_d2d4c3e.go x.go +git commit -m 'more' x.go +git tag morework + +git show-ref --tags --heads +cmp stdout .git-refs + +-- .git-refs -- +7303f77963648d5f1ec5e55eccfad8e14035866c refs/heads/master +d2d4c3ea66230e7ad6fbd8f0ecd8c0f851392364 refs/tags/morework +7fff7f3417faa4a795f9518bc2bef05147a1d6c0 refs/tags/v1.0.0 +731e3b12a0272dcafb560b8fa6a4e9ffb20ef5c9 refs/tags/v1.1.0-pre +9f6f860fe5c92cd835fdde2913aca8db9ce63373 refs/tags/v1.2.0 +d7ae1e4b368320e7a577fc8a9efc1e78aacac52a refs/tags/v2.0.0 +-- x_1abc5ff.go -- +package legacytest + +// add comment +const X = 1 +-- x_52853eb.go -- +package legacytest +const X = 1 +-- x_7303f77.go -- +package legacytest + +const XX = 2 + +const XXX = 3 +-- x_731e3b1.go -- +package legacytest + +// add comment again +const X = 1 +-- x_7fff7f3.go -- +package legacytest + +const X = 1 +-- x_9f6f860.go -- +package legacytest + +// add comment again!!! +const X = 1 +-- x_cf92c7b.go -- +package legacytest +-- x_d2d4c3e.go -- +package legacytest + +// add comment hack hack hack +const X = 1 +-- x_d7ae1e4.go -- +package legacytest + +const XX = 2 +-- x_fa4f5d6.go -- +package legacytest +const XX = 2 +-- x_fb3c628.go -- +package legacytest + +// add comment fixed +const X = 1 diff --git a/src/cmd/go/testdata/vcstest/git/prefercompatible.txt b/src/cmd/go/testdata/vcstest/git/prefercompatible.txt new file mode 100644 index 00000000000000..99e955803f34fe --- /dev/null +++ b/src/cmd/go/testdata/vcstest/git/prefercompatible.txt @@ -0,0 +1,58 @@ +handle git + +env GIT_AUTHOR_NAME='Gopher' +env GIT_AUTHOR_EMAIL='gopher@golang.org' +env GIT_COMMITTER_NAME=$GIT_AUTHOR_NAME +env GIT_COMMITTER_EMAIL=$GIT_AUTHOR_EMAIL + +git init +git checkout -b master + +at 2018-01-01T10:00:00-05:00 +git add prefercompatible.go +git commit -m 'v1.5.1' +git tag v1.5.1 + +at 2018-01-02T10:00:00-05:00 +cp go.mod.v1 go.mod +git add go.mod +git commit -m 'add go.mod' +git tag v1.5.2 + +at 2018-01-03T10:00:00-05:00 +git checkout v1.5.1 +git commit --allow-empty -m 'v2' +git tag v2.0.0 + +at 2018-01-04T10:00:00-05:00 +cp go.mod.v2 go.mod +git add go.mod +git commit -m 'add v2 go.mod' +git tag v2.0.1 + +at 2018-01-05T10:00:00-05:00 +git commit --allow-empty -m 'v2.1' +git tag v2.1.0 + +git checkout master + +git show-ref --tags --heads +cmp stdout .git-refs + +-- .git-refs -- +17354ea3a81eb684eb1aae80a7b52a5034bd34d2 refs/heads/master +e79838949df193e551567d3f245720f7a6520569 refs/tags/v1.5.1 +17354ea3a81eb684eb1aae80a7b52a5034bd34d2 refs/tags/v1.5.2 +7a6f62732689a8e013c3ab4e5e0566ab4969a46e refs/tags/v2.0.0 +45f40e4783d7a9908c85e6dc48603fce3dd6ffad refs/tags/v2.0.1 +70d729681ff71f5dd03dd7142c78fb98f35065fe refs/tags/v2.1.0 +-- prefercompatible.go -- +package prefercompatible +-- go.mod.v1 -- +module vcs-test.golang.org/git/prefercompatible.git + +go 1.12 +-- go.mod.v2 -- +module vcs-test.golang.org/git/prefercompatible.git/v2 + +go 1.12 diff --git a/src/cmd/go/testdata/vcstest/git/unreachable-hash.txt b/src/cmd/go/testdata/vcstest/git/unreachable-hash.txt new file mode 100644 index 00000000000000..6a05be41dfeb9d --- /dev/null +++ b/src/cmd/go/testdata/vcstest/git/unreachable-hash.txt @@ -0,0 +1,31 @@ +handle git + +env GIT_AUTHOR_NAME='Michael Matloob' +env GIT_AUTHOR_EMAIL='matloob@golang.org' +env GIT_COMMITTER_NAME=$GIT_AUTHOR_NAME +env GIT_COMMITTER_EMAIL=$GIT_AUTHOR_EMAIL + +at 2017-04-24T23:34:10-00:00 + +git init +cp go.mod.orig go.mod +git add go.mod +git write-tree +git commit-tree 995c9bbddb810e9fe22d0ba73d661c599eec29e8 -m foo +git checkout cbd2996c52d20dac558bc3b49c342c7c8320a1fc + +git switch --orphan main +mv go.mod.orig go.mod +git add go.mod +git commit -m bar + +git log --oneline --decorate=short main cbd2996c52d20dac558bc3b49c342c7c8320a1fc +cmp stdout .git-log + +-- .git-log -- +6c0e37b (HEAD -> main) bar +cbd2996 foo +-- go.mod.orig -- +module vcs-test.golang.org/git/ureachable-hash.git + +go 1.26 diff --git a/src/cmd/go/testdata/vcstest/go/get_404_meta.txt b/src/cmd/go/testdata/vcstest/go/get_404_meta.txt new file mode 100644 index 00000000000000..3ce811b6a3e76a --- /dev/null +++ b/src/cmd/go/testdata/vcstest/go/get_404_meta.txt @@ -0,0 +1,7 @@ +handle dir +status 404 + +-- index.html -- + + + diff --git a/src/cmd/go/testdata/vcstest/go/invalid-version.txt b/src/cmd/go/testdata/vcstest/go/invalid-version.txt new file mode 100644 index 00000000000000..bae1e17a03d0aa --- /dev/null +++ b/src/cmd/go/testdata/vcstest/go/invalid-version.txt @@ -0,0 +1,10 @@ +handle dir + +-- index.html -- + + + +-- unicode/index.html -- + + + diff --git a/src/cmd/go/testdata/vcstest/hg/hgrepo1.txt b/src/cmd/go/testdata/vcstest/hg/hgrepo1.txt index 1e4b83aae6cda0..42d81e9d39a3ee 100644 --- a/src/cmd/go/testdata/vcstest/hg/hgrepo1.txt +++ b/src/cmd/go/testdata/vcstest/hg/hgrepo1.txt @@ -1,153 +1,97 @@ handle hg -mkdir git -cd git - -env GIT_AUTHOR_NAME='Russ Cox' -env GIT_AUTHOR_EMAIL='rsc@golang.org' -env GIT_COMMITTER_NAME=$GIT_AUTHOR_NAME -env GIT_COMMITTER_EMAIL=$GIT_AUTHOR_EMAIL - -git init +hg init -at 2018-04-17T15:43:22-04:00 +env date=2018-04-17T15:43:22-04:00 unquote '' cp stdout README -git add README -git commit -a -m 'empty README' -git branch -m master -git tag v1.2.3 +hg add README +hg commit --user=rsc --date=$date -m 'empty README' +hg branch tagbranch +hg tag --user=rsc --date=$date v1.2.3 +hg update default -at 2018-04-17T15:45:48-04:00 -git branch v2 -git checkout v2 +env date=2018-04-17T15:45:48-04:00 +hg branch v2 echo 'v2' cp stdout v2 -git add v2 -git commit -a -m 'v2' -git tag v2.3 -git tag v2.0.1 -git branch v2.3.4 -git tag branch-v2.3.4 +hg add v2 +hg commit --user=rsc --date=$date -m 'v2' +hg update tagbranch +hg tag --user=rsc --date=$date -r v2 v2.3 +hg tag --user=rsc --date=$date -r v2 v2.0.1 +hg update v2 +hg branch v2.3.4 -at 2018-04-17T16:00:19-04:00 +env date=2018-04-17T16:00:19-04:00 echo 'intermediate' cp stdout foo.txt -git add foo.txt -git commit -a -m 'intermediate' +hg add foo.txt +hg commit --user=rsc --date=$date -m 'intermediate' -at 2018-04-17T16:00:32-04:00 +env date=2018-04-17T16:00:32-04:00 echo 'another' cp stdout another.txt -git add another.txt -git commit -a -m 'another' -git tag v2.0.2 -git tag branch-v2 +hg add another.txt +hg commit --user=rsc --date=$date -m 'another' +hg update tagbranch +hg tag --user=rsc --date=$date -r v2.3.4 v2.0.2 -at 2018-04-17T16:16:52-04:00 -git checkout master -git branch v3 -git checkout v3 +env date=2018-04-17T16:16:52-04:00 +hg update default +hg branch v3 mkdir v3/sub/dir echo 'v3/sub/dir/file' cp stdout v3/sub/dir/file.txt -git add v3 -git commit -a -m 'add v3/sub/dir/file.txt' -git tag branch-v3 - -at 2018-04-17T22:23:00-04:00 -git checkout master -git tag -a v1.2.4-annotated -m 'v1.2.4-annotated' +hg add v3 +hg commit --user=rsc --date=$date -m 'add v3/sub/dir/file.txt' -cd .. +env date=2018-04-17T22:23:00-04:00 +hg update default +hg tag --user=rsc --date=$date -r v1.2.3 v1.2.4-annotated -hg init -hg convert --datesort ./git . -rm ./git - -hg update -C v2 -hg branch v2 +env date=2018-06-27T12:15:24-04:00 +hg update v2 unquote '' cp stdout dummy hg add dummy -hg commit --user 'Russ Cox ' --date '2018-06-27T12:15:24-04:00' -m 'dummy' - -# 'hg convert' blindly stamps a tag-update commit at the end of whatever branch -# happened to contain the last converted commit — in this case, v3. However, the -# original vcs-test.golang.org copy of this repo had this commit on the v3 -# branch as a descendent of 'add v3/sub/dir/file.txt', so that's where we put it -# here. That leaves the convert-repo 'update tags' commit only reachable as the -# head of the default branch. -hg update -r 4 - -hg branch v3 -unquote '' -cp stdout dummy -hg add dummy -hg commit --user 'Russ Cox ' --date '2018-06-27T12:15:45-04:00' -m 'dummy' +hg commit --user=rsc --date=$date -m 'dummy' +env date=2018-06-27T12:16:10-04:00 hg update v2.3.4 hg branch v2.3.4 unquote '' cp stdout dummy hg add dummy -hg commit --user 'Russ Cox ' --date '2018-06-27T12:16:10-04:00' -m 'dummy' - -hg tag --user 'Russ Cox ' --date '2018-06-27T12:16:30-04:00' -m 'Removed tag branch-v2, branch-v3, branch-v2.3.4' --remove branch-v2 branch-v3 branch-v2.3.4 +hg commit --user=rsc --date=$date -m 'dummy' -# Adding commits to the above branches updates both the branch heads and the -# corresponding bookmarks. -# But apparently at some point it did not do so? The original copy of this repo -# had bookmarks pointing to the base of each branch instead of the tip. 🤔 -# Either way, force the bookmarks we care about to match the original copy of -# the repo. -hg book v2 -r 3 --force -hg book v2.3.4 -r 1 --force -hg book v3 -r 5 --force +hg book v2 -r v2.0.2 --force +hg book v2.3.4 -r v2.0.1 --force hg log -G --debug hg tags cmp stdout .hg-tags - # 'hg convert' leaves an 'update tags' commit on the default branch, and that - # commit always uses the current date (so is not reproducible). Fortunately, - # that commit lands on the 'default' branch and is not tagged as 'tip', so it - # seems to be mostly harmless. However, because it is nondeterministic we - # should avoid listing it here. - # - # Unfortunately, some of our builders are still running Debian 9 “Stretch”, - # which shipped with a version of 'hg' that does not support 'hg branch -r' - # to list branches for specific versions. Although Stretch is past its - # end-of-life date, we need to keep the builders happy until they can be - # turned down (https://go.dev/issue/56414). hg branches -? cmp stdout .hg-branches -stdout 'v2\s+6:9a4f43d231ec' -stdout 'v2.3.4\s+9:18518c07eb8e' -stdout 'v3\s+7:a2cad8a2b1bb' -stdout 'default\s+5:' +cmp stdout .hg-branches -# Likewise, bookmark v3 ends up on the nondeterministic commit. hg bookmarks -? cmp stdout .hg-bookmarks -stdout 'master\s+0:41964ddce118' -stdout 'v2\s+3:8f49ee7a6ddc' -stdout 'v2.3.4\s+1:88fde824ec8b' -stdout 'v3\s+5:.*' +cmp stdout .hg-bookmarks --- .hg-branches -- -v2.3.4 9:18518c07eb8e -v3 7:a2cad8a2b1bb -v2 6:9a4f43d231ec -- .hg-tags -- -tip 9:18518c07eb8e -v2.0.2 3:8f49ee7a6ddc -v2.3 1:88fde824ec8b -v2.0.1 1:88fde824ec8b -v1.2.4-annotated 0:41964ddce118 -v1.2.3 0:41964ddce118 +tip 11:745aacc8b24d +v2.0.2 6:b1ed98abc268 +v2.3 2:a546811101e1 +v2.0.1 2:a546811101e1 +v1.2.4-annotated 0:c0186fb00e50 +v1.2.3 0:c0186fb00e50 +-- .hg-branches -- +v2.3.4 11:745aacc8b24d +v2 10:2b5ca8689628 +default 9:a9a2a32d1392 +v3 8:442174d28f65 +tagbranch 7:1a3473c317b4 -- .hg-bookmarks -- - master 0:41964ddce118 - v2 3:8f49ee7a6ddc - v2.3.4 1:88fde824ec8b + v2 6:b1ed98abc268 + v2.3.4 2:a546811101e1 diff --git a/src/cmd/go/testdata/vcstest/hg/legacytest.txt b/src/cmd/go/testdata/vcstest/hg/legacytest.txt new file mode 100644 index 00000000000000..c3f063e2fa2cca --- /dev/null +++ b/src/cmd/go/testdata/vcstest/hg/legacytest.txt @@ -0,0 +1,124 @@ +handle hg + +env user='Russ Cox ' + +hg init + +env date=2018-07-17T12:41:39-04:00 +cp x_cf92c7b.go x.go +hg add x.go +hg commit --user=$user --date=$date -m 'initial commit' + +env date=2018-07-17T12:41:57-04:00 +cp x_52853eb.go x.go +hg commit --user=$user --date=$date -m 'add X' x.go + +env date=2018-07-17T12:42:07-04:00 +cp x_7fff7f3.go x.go +hg commit --user=$user --date=$date -m 'gofmt' x.go +hg tag --user=$user --date=$date v1.0.0 + +env date=2018-07-17T12:42:28-04:00 +cp x_fa4f5d6.go x.go +hg commit --user=$user --date=$date -m 'X->XX' x.go + +env date=2018-07-17T12:42:36-04:00 +cp x_d7ae1e4.go x.go +hg commit --user=$user --date=$date -m 'gofmt' x.go +hg tag --user=$user --date=$date v2.0.0 + +env date=2018-07-17T12:42:53-04:00 +cp x_7303f77.go x.go +hg commit --user=$user --date=$date -m 'add XXX' x.go + +env date=2018-07-17T12:47:59-04:00 +hg update v1.0.0 +cp x_1abc5ff.go x.go +hg commit --user=$user --date=$date -m 'comment' x.go + +env date=2018-07-17T12:48:22-04:00 +cp x_731e3b1.go x.go +hg commit --user=$user --date=$date -m 'prerelease' x.go +hg tag --user=$user --date=$date v1.1.0-pre + +env date=2018-07-17T12:48:49-04:00 +cp x_fb3c628.go x.go +hg commit --user=$user --date=$date -m 'working' x.go + +env date=2018-07-17T12:49:05-04:00 +cp x_9f6f860.go x.go +hg commit --user=$user --date=$date -m 'v1.2.0' x.go +hg tag --user=$user --date=$date v1.2.0 + +env date=2018-07-17T12:49:42-04:00 +cp x_d2d4c3e.go x.go +hg commit --user=$user --date=$date -m 'more' x.go +hg tag --user=$user --date=$date morework + +hg log -r ':' --template '{node|short} {desc|strip|firstline}\n' +cmp stdout .hg-log + +-- .hg-log -- +9dc9138de2e5 initial commit +ee0106da3c7c add X +d6ad170f61d4 gofmt +90c54d4351ee Added tag v1.0.0 for changeset d6ad170f61d4 +c6260ab8dc3e X->XX +e64782fcadfd gofmt +d6ad604046f6 Added tag v2.0.0 for changeset e64782fcadfd +663753d3ac63 add XXX +4555a6dd66c0 comment +90da67a9bf0c prerelease +d7c15fbd635d Added tag v1.1.0-pre for changeset 90da67a9bf0c +accb169a3696 working +07462d11385f v1.2.0 +ed9a22ebb8a1 Added tag v1.2.0 for changeset 07462d11385f +498b291aa133 more +2840708d1294 Added tag morework for changeset 498b291aa133 +-- x_1abc5ff.go -- +package legacytest + +// add comment +const X = 1 +-- x_52853eb.go -- +package legacytest +const X = 1 +-- x_7303f77.go -- +package legacytest + +const XX = 2 + +const XXX = 3 +-- x_731e3b1.go -- +package legacytest + +// add comment again +const X = 1 +-- x_7fff7f3.go -- +package legacytest + +const X = 1 +-- x_9f6f860.go -- +package legacytest + +// add comment again!!! +const X = 1 +-- x_cf92c7b.go -- +package legacytest +-- x_d2d4c3e.go -- +package legacytest + +// add comment hack hack hack +const X = 1 +-- x_d7ae1e4.go -- +package legacytest + +const XX = 2 +-- x_fa4f5d6.go -- +package legacytest +const XX = 2 +-- x_fb3c628.go -- +package legacytest + +// add comment fixed +const X = 1 diff --git a/src/cmd/go/testdata/vcstest/hg/prefixtagtests.txt b/src/cmd/go/testdata/vcstest/hg/prefixtagtests.txt new file mode 100644 index 00000000000000..c61c9bacae93d0 --- /dev/null +++ b/src/cmd/go/testdata/vcstest/hg/prefixtagtests.txt @@ -0,0 +1,52 @@ +env date=2019-05-09T18:35:00-04:00 + +handle hg + +hg init +hg add sub +hg commit -u rsc -d $date -m 'create module sub' + +echo v0.1.0 +cp stdout status +hg add status +hg commit -u rsc -d $date -m v0.1.0 +hg tag -u rsc -d $date v0.1.0 + +echo sub/v0.0.9 +cp stdout status +hg add status +hg commit -u rsc -d $date -m sub/v0.0.9 +hg tag -u rsc -d $date sub/v0.0.9 + +echo sub/v0.0.10 +cp stdout status +hg commit -u rsc -d $date -m sub/v0.0.10 status +hg tag -u rsc -d $date sub/v0.0.10 + +echo v0.2.0 +cp stdout status +hg commit -u rsc -d $date -m v0.2.0 +hg tag -u rsc -d $date v0.2.0 + +echo 'after last tag' +cp stdout status +hg commit -u rsc -d $date -m 'after last tag' + +hg tags +cmp stdout .hg-tags + +hg branches +cmp stdout .hg-branches + +-- .hg-tags -- +tip 9:840814f739c2 +v0.2.0 7:84e452ea2b0a +sub/v0.0.10 5:1cc0dfcc254c +sub/v0.0.9 3:c5f5e3168705 +v0.1.0 1:d6ba12969a9b +-- .hg-branches -- +default 9:840814f739c2 +-- sub/go.mod -- +module vcs-test.golang.org/git/prefixtagtests.git/sub +-- sub/sub.go -- +package sub diff --git a/src/cmd/go/testdata/vcstest/hg/tagtests.txt b/src/cmd/go/testdata/vcstest/hg/tagtests.txt new file mode 100644 index 00000000000000..38b3e97ef9b359 --- /dev/null +++ b/src/cmd/go/testdata/vcstest/hg/tagtests.txt @@ -0,0 +1,38 @@ +env date=2019-05-09T18:56:25-04:00 + +handle hg + +hg init +hg add go.mod tagtests.go +hg commit --user 'rsc' --date $date -m 'create module tagtests' +hg branch b +hg add v0.2.1 +hg commit --user 'rsc' --date $date -m 'v0.2.1' +hg tag --user 'rsc' --date $date v0.2.1 + +hg update default +hg add v0.2.2 +hg commit --user 'rsc' --date $date -m 'v0.2.2' +hg tag --user 'rsc' --date $date v0.2.2 + +hg tags +cmp stdout .hg-tags + +hg branches +cmp stdout .hg-branches + +-- go.mod -- +module vcs-test.golang.org/git/tagtests.git +-- tagtests.go -- +package tagtests +-- v0.2.1 -- +v0.2.1 +-- v0.2.2 -- +v0.2.2 +-- .hg-tags -- +tip 4:8d0b18b816df +v0.2.2 3:1e531550e864 +v0.2.1 1:010a2d1a2ea7 +-- .hg-branches -- +default 4:8d0b18b816df +b 2:ceae444ffda5 diff --git a/src/cmd/gofmt/gofmt.go b/src/cmd/gofmt/gofmt.go index ad6ad636524479..3178b05f16a9d1 100644 --- a/src/cmd/gofmt/gofmt.go +++ b/src/cmd/gofmt/gofmt.go @@ -79,7 +79,7 @@ func usage() { } func initParserMode() { - parserMode = parser.ParseComments + parserMode = parser.ParseComments | parser.SkipObjectResolution if *allErrors { parserMode |= parser.AllErrors } @@ -280,7 +280,7 @@ func processFile(filename string, info fs.FileInfo, in io.Reader, r *reporter) e } perm := info.Mode().Perm() - if err := writeFile(filename, src, res, perm, info.Size()); err != nil { + if err := writeFile(filename, src, res, perm); err != nil { return err } } @@ -465,7 +465,7 @@ func fileWeight(path string, info fs.FileInfo) int64 { } // writeFile updates a file with the new formatted data. -func writeFile(filename string, orig, formatted []byte, perm fs.FileMode, size int64) error { +func writeFile(filename string, orig, formatted []byte, perm fs.FileMode) error { // Make a temporary backup file before rewriting the original file. bakname, err := backupFile(filename, orig, perm) if err != nil { @@ -489,7 +489,7 @@ func writeFile(filename string, orig, formatted []byte, perm fs.FileMode, size i } n, err := fout.Write(formatted) - if err == nil && int64(n) < size { + if err == nil { err = fout.Truncate(int64(n)) } diff --git a/src/cmd/internal/bootstrap_test/overlaydir_test.go b/src/cmd/internal/bootstrap_test/overlaydir_test.go index 5812c453ac2fec..bee3214b67576f 100644 --- a/src/cmd/internal/bootstrap_test/overlaydir_test.go +++ b/src/cmd/internal/bootstrap_test/overlaydir_test.go @@ -43,6 +43,9 @@ func overlayDir(dstRoot, srcRoot string) error { dstPath := filepath.Join(dstRoot, suffix) info, err := entry.Info() + if err != nil { + return err + } perm := info.Mode() & os.ModePerm if info.Mode()&os.ModeSymlink != 0 { info, err = os.Stat(srcPath) diff --git a/src/cmd/internal/codesign/codesign.go b/src/cmd/internal/codesign/codesign.go index 24496e20003977..33671ce835c394 100644 --- a/src/cmd/internal/codesign/codesign.go +++ b/src/cmd/internal/codesign/codesign.go @@ -11,6 +11,7 @@ package codesign import ( + "bytes" "crypto/sha256" "debug/macho" "encoding/binary" @@ -247,21 +248,35 @@ func Sign(out []byte, data io.Reader, id string, codeSize, textOff, textSize int outp = puts(outp, []byte(id+"\000")) // emit hashes + datab, isBytes := data.(*bytes.Buffer) var buf [pageSize]byte p := 0 for p < int(codeSize) { - n, err := io.ReadFull(data, buf[:]) - if err == io.EOF { - break - } - if err != nil && err != io.ErrUnexpectedEOF { - panic(err) + var chunk []byte + if isBytes { + // If it is already a byte slice, we can read without copying + chunk = datab.Next(pageSize) + if len(chunk) == 0 { + break + } + } else { + n, err := io.ReadFull(data, buf[:]) + if err == io.EOF { + break + } + if err != nil && err != io.ErrUnexpectedEOF { + panic(err) + } + chunk = buf[:n] } + + n := len(chunk) if p+n > int(codeSize) { n = int(codeSize) - p + chunk = chunk[:n] } p += n - b := sha256.Sum256(buf[:n]) + b := sha256.Sum256(chunk) outp = puts(outp, b[:]) } } diff --git a/src/cmd/internal/cov/readcovdata.go b/src/cmd/internal/cov/readcovdata.go index e0e063445957db..f9fd52293071cb 100644 --- a/src/cmd/internal/cov/readcovdata.go +++ b/src/cmd/internal/cov/readcovdata.go @@ -145,14 +145,14 @@ func (r *CovDataReader) Visit() error { return nil } -func (r *CovDataReader) verb(vlevel int, s string, a ...interface{}) { +func (r *CovDataReader) verb(vlevel int, s string, a ...any) { if r.verbosityLevel >= vlevel { fmt.Fprintf(os.Stderr, s, a...) fmt.Fprintf(os.Stderr, "\n") } } -func (r *CovDataReader) warn(s string, a ...interface{}) { +func (r *CovDataReader) warn(s string, a ...any) { fmt.Fprintf(os.Stderr, "warning: ") fmt.Fprintf(os.Stderr, s, a...) fmt.Fprintf(os.Stderr, "\n") @@ -161,7 +161,7 @@ func (r *CovDataReader) warn(s string, a ...interface{}) { } } -func (r *CovDataReader) fatal(s string, a ...interface{}) error { +func (r *CovDataReader) fatal(s string, a ...any) error { if r.err != nil { return nil } diff --git a/src/cmd/internal/dwarf/dwarf.go b/src/cmd/internal/dwarf/dwarf.go index 6e06f139b03d31..b8956b4cffe8d0 100644 --- a/src/cmd/internal/dwarf/dwarf.go +++ b/src/cmd/internal/dwarf/dwarf.go @@ -40,8 +40,7 @@ const AbstractFuncSuffix = "$abstract" var logDwarf bool // Sym represents a symbol. -type Sym interface { -} +type Sym any // A Var represents a local variable or a function parameter. type Var struct { @@ -194,16 +193,16 @@ type Context interface { Size(s Sym) int64 AddInt(s Sym, size int, i int64) AddBytes(s Sym, b []byte) - AddAddress(s Sym, t interface{}, ofs int64) - AddCURelativeAddress(s Sym, t interface{}, ofs int64) - AddSectionOffset(s Sym, size int, t interface{}, ofs int64) - AddDWARFAddrSectionOffset(s Sym, t interface{}, ofs int64) - AddIndirectTextRef(s Sym, t interface{}) + AddAddress(s Sym, t any, ofs int64) + AddCURelativeAddress(s Sym, t any, ofs int64) + AddSectionOffset(s Sym, size int, t any, ofs int64) + AddDWARFAddrSectionOffset(s Sym, t any, ofs int64) + AddIndirectTextRef(s Sym, t any) CurrentOffset(s Sym) int64 RecordDclReference(from Sym, to Sym, dclIdx int, inlIndex int) RecordChildDieOffsets(s Sym, vars []*Var, offsets []int32) AddString(s Sym, v string) - Logf(format string, args ...interface{}) + Logf(format string, args ...any) } // AppendUleb128 appends v to b using DWARF's unsigned LEB128 encoding. @@ -874,7 +873,7 @@ type DWAttr struct { Atr uint16 // DW_AT_ Cls uint8 // DW_CLS_ Value int64 - Data interface{} + Data any } // DWDie represents a DWARF debug info entry. @@ -886,7 +885,7 @@ type DWDie struct { Sym Sym } -func putattr(ctxt Context, s Sym, abbrev int, form int, cls int, value int64, data interface{}) error { +func putattr(ctxt Context, s Sym, abbrev int, form int, cls int, value int64, data any) error { switch form { case DW_FORM_addr: // address // Allow nil addresses for DW_AT_go_runtime_type. diff --git a/src/cmd/internal/dwarf/putvarabbrevgen_test.go b/src/cmd/internal/dwarf/putvarabbrevgen_test.go index 24500a33889d62..ffe400a30a8504 100644 --- a/src/cmd/internal/dwarf/putvarabbrevgen_test.go +++ b/src/cmd/internal/dwarf/putvarabbrevgen_test.go @@ -80,7 +80,7 @@ func TestPutVarAbbrevGenerator(t *testing.T) { func pvagenerate(t *testing.T) string { var fset token.FileSet - f, err := parser.ParseFile(&fset, "./dwarf.go", nil, parser.ParseComments) + f, err := parser.ParseFile(&fset, "./dwarf.go", nil, parser.ParseComments|parser.SkipObjectResolution) if err != nil { t.Fatal(err) } diff --git a/src/cmd/internal/fuzztest/script_test.go b/src/cmd/internal/fuzztest/script_test.go new file mode 100644 index 00000000000000..e8fe701e176394 --- /dev/null +++ b/src/cmd/internal/fuzztest/script_test.go @@ -0,0 +1,22 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package fuzztest + +import ( + "cmd/internal/script/scripttest" + "flag" + "internal/testenv" + "testing" +) + +//go:generate go test cmd/internal/fuzztest -v -run=TestScript/README --fixreadme + +var fixReadme = flag.Bool("fixreadme", false, "if true, update README for script tests") + +func TestScript(t *testing.T) { + testenv.MustHaveGoBuild(t) + testenv.SkipIfShortAndSlow(t) + scripttest.RunToolScriptTest(t, nil, "testdata/script", *fixReadme) +} diff --git a/src/cmd/internal/fuzztest/testdata/script/README b/src/cmd/internal/fuzztest/testdata/script/README new file mode 100644 index 00000000000000..9ec997a138f0f2 --- /dev/null +++ b/src/cmd/internal/fuzztest/testdata/script/README @@ -0,0 +1,286 @@ +This file is generated by 'go generate'. DO NOT EDIT. + +This directory holds test scripts *.txt run during 'go test cmd/'. +To run a specific script foo.txt + + go test cmd/ -run=Script/^foo$ + +In general script files should have short names: a few words, + not whole sentences. +The first word should be the general category of behavior being tested, +often the name of a go subcommand (build, link, compile, ...) or concept (vendor, pattern). + +Each script is a text archive (go doc internal/txtar). +The script begins with an actual command script to run +followed by the content of zero or more supporting files to +create in the script's temporary file system before it starts executing. + +As an example, run_hello.txt says: + + # hello world + go run hello.go + stderr 'hello world' + ! stdout . + + -- hello.go -- + package main + func main() { println("hello world") } + +Each script runs in a fresh temporary work directory tree, available to scripts as $WORK. +Scripts also have access to other environment variables, including: + + GOARCH= + GOOS= + TMPDIR=$WORK/tmp + devnull= + goversion= + +On Plan 9, the variables $path and $home are set instead of $PATH and $HOME. +On Windows, the variables $USERPROFILE and $TMP are set instead of +$HOME and $TMPDIR. + +The lines at the top of the script are a sequence of commands to be executed by +a small script engine configured in .../cmd/internal/script/scripttest/run.go (not the system shell). + +Each line of a script is parsed into a sequence of space-separated command +words, with environment variable expansion within each word and # marking +an end-of-line comment. Additional variables named ':' and '/' are expanded +within script arguments (expanding to the value of os.PathListSeparator and +os.PathSeparator respectively) but are not inherited in subprocess environments. + +Adding single quotes around text keeps spaces in that text from being treated +as word separators and also disables environment variable expansion. Inside a +single-quoted block of text, a repeated single quote indicates a literal single +quote, as in: + + 'Don''t communicate by sharing memory.' + +A line beginning with # is a comment and conventionally explains what is being +done or tested at the start of a new section of the script. + +Commands are executed one at a time, and errors are checked for each command; +if any command fails unexpectedly, no subsequent commands in the script are +executed. The command prefix ! indicates that the command on the rest of the +line (typically go or a matching predicate) must fail instead of succeeding. +The command prefix ? indicates that the command may or may not succeed, but the +script should continue regardless. + +The command prefix [cond] indicates that the command on the rest of the line +should only run when the condition is satisfied. + +A condition can be negated: [!root] means to run the rest of the line only if +the user is not root. Multiple conditions may be given for a single command, +for example, '[linux] [amd64] skip'. The command will run if all conditions are +satisfied. + +When TestScript runs a script and the script fails, by default TestScript shows +the execution of the most recent phase of the script (since the last # comment) +and only shows the # comments for earlier phases. + +Note also that in reported output, the actual name of the per-script temporary directory +has been consistently replaced with the literal string $WORK. + +The available commands are: +cat files... + concatenate files and print to the script's stdout buffer + + +cc args... + run the platform C compiler + + +cd dir + change the working directory + + +chmod perm paths... + change file mode bits + + Changes the permissions of the named files or directories to + be equal to perm. + Only numerical permissions are supported. + +cmp [-q] file1 file2 + compare files for differences + + By convention, file1 is the actual data and file2 is the + expected data. + The command succeeds if the file contents are identical. + File1 can be 'stdout' or 'stderr' to compare the stdout or + stderr buffer from the most recent command. + +cmpenv [-q] file1 file2 + compare files for differences, with environment expansion + + By convention, file1 is the actual data and file2 is the + expected data. + The command succeeds if the file contents are identical + after substituting variables from the script environment. + File1 can be 'stdout' or 'stderr' to compare the script's + stdout or stderr buffer. + +cp src... dst + copy files to a target file or directory + + src can include 'stdout' or 'stderr' to copy from the + script's stdout or stderr buffer. + +echo string... + display a line of text + + +env [key[=value]...] + set or log the values of environment variables + + With no arguments, print the script environment to the log. + Otherwise, add the listed key=value pairs to the environment + or print the listed keys. + +exec program [args...] [&] + run an executable program with arguments + + Note that 'exec' does not terminate the script (unlike Unix + shells). + +exists [-readonly] [-exec] file... + check that files exist + + +go [args...] [&] + run the 'go' program provided by the script host + + +grep [-count=N] [-q] 'pattern' file + find lines in a file that match a pattern + + The command succeeds if at least one match (or the exact + count, if given) is found. + The -q flag suppresses printing of matches. + +help [-v] name... + log help text for commands and conditions + + To display help for a specific condition, enclose it in + brackets: 'help [amd64]'. + To display complete documentation when listing all commands, + pass the -v flag. + +mkdir path... + create directories, if they do not already exist + + Unlike Unix mkdir, parent directories are always created if + needed. + +mv old new + rename a file or directory to a new path + + OS-specific restrictions may apply when old and new are in + different directories. + +replace [old new]... file + replace strings in a file + + The 'old' and 'new' arguments are unquoted as if in quoted + Go strings. + +rm path... + remove a file or directory + + If the path is a directory, its contents are removed + recursively. + +skip [msg] + skip the current test + + +sleep duration [&] + sleep for a specified duration + + The duration must be given as a Go time.Duration string. + +stderr [-count=N] [-q] 'pattern' file + find lines in the stderr buffer that match a pattern + + The command succeeds if at least one match (or the exact + count, if given) is found. + The -q flag suppresses printing of matches. + +stdout [-count=N] [-q] 'pattern' file + find lines in the stdout buffer that match a pattern + + The command succeeds if at least one match (or the exact + count, if given) is found. + The -q flag suppresses printing of matches. + +stop [msg] + stop execution of the script + + The message is written to the script log, but no error is + reported from the script engine. + +symlink path -> target + create a symlink + + Creates path as a symlink to target. + The '->' token (like in 'ls -l' output on Unix) is required. + +wait + wait for completion of background commands + + Waits for all background commands to complete. + The output (and any error) from each command is printed to + the log in the order in which the commands were started. + After the call to 'wait', the script's stdout and stderr + buffers contain the concatenation of the background + commands' outputs. + + + +The available conditions are: +[GOARCH:*] + runtime.GOARCH == +[GODEBUG:*] + GODEBUG contains +[GOEXPERIMENT:*] + GOEXPERIMENT is enabled +[GOOS:*] + runtime.GOOS == +[asan] + GOOS/GOARCH supports -asan +[buildmode:*] + go supports -buildmode= +[cgo] + host CGO_ENABLED +[cgolinkext] + platform requires external linking for cgo +[compiler:*] + runtime.Compiler == +[cross] + cmd/go GOOS/GOARCH != GOHOSTOS/GOHOSTARCH +[exec:*] + names an executable in the test binary's PATH +[fuzz] + GOOS/GOARCH supports -fuzz +[fuzz-instrumented] + GOOS/GOARCH supports -fuzz with instrumentation +[go-builder] + GO_BUILDER_NAME is non-empty +[link] + testenv.HasLink() +[msan] + GOOS/GOARCH supports -msan +[mustlinkext] + platform always requires external linking +[pielinkext] + platform requires external linking for PIE +[race] + GOOS/GOARCH supports -race +[root] + os.Geteuid() == 0 +[short] + testing.Short() +[symlink] + testenv.HasSymlink() +[verbose] + testing.Verbose() + diff --git a/src/cmd/go/testdata/script/test_fuzz.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_cache.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_cache.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_cache.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_cache.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_cgo.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_cgo.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_cgo.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_cgo.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_chatty.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_chatty.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_chatty.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_chatty.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_cleanup.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_cleanup.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_cleanup.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_cleanup.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_context.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_context.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_context.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_context.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_cov.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_cov.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_cov.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_cov.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_deadline.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_deadline.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_deadline.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_deadline.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_dup_cache.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_dup_cache.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_dup_cache.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_dup_cache.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_err_deadlock.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_err_deadlock.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_err_deadlock.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_err_deadlock.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_fuzztime.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_fuzztime.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_fuzztime.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_fuzztime.txt diff --git a/src/cmd/internal/fuzztest/testdata/script/test_fuzz_fuzztime_timeout.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_fuzztime_timeout.txt new file mode 100644 index 00000000000000..a6d0d822cb18d4 --- /dev/null +++ b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_fuzztime_timeout.txt @@ -0,0 +1,35 @@ +# Regression test for go.dev/issue/75804. +# When -fuzztime expires, the coordinator must not report a spurious +# "context deadline exceeded" error. + +[!fuzz] skip +[short] skip +env GOCACHE=$WORK/cache + +go test -c -o $devnull + +env GOMAXPROCS=2 + +go test -fuzz=FuzzNoop -fuzztime=1000ms +go test -fuzz=FuzzNoop -fuzztime=100ms +go test -fuzz=FuzzNoop -fuzztime=100ms +go test -fuzz=FuzzNoop -fuzztime=100ms +go test -fuzz=FuzzNoop -fuzztime=100ms + +-- go.mod -- +module fuzz + +go 1.24 +-- fuzz_noop_test.go -- +package fuzz_test + +import ( + "testing" + "time" +) + +func FuzzNoop(f *testing.F) { + f.Fuzz(func(*testing.T, []byte) { + time.Sleep(time.Millisecond) + }) +} diff --git a/src/cmd/go/testdata/script/test_fuzz_io_error.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_io_error.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_io_error.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_io_error.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_limit_dup_entry.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_limit_dup_entry.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_limit_dup_entry.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_limit_dup_entry.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_match.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_match.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_match.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_match.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_minimize.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_minimize.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_minimize.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_minimize.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_minimize_dirty_cov.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_minimize_dirty_cov.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_minimize_dirty_cov.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_minimize_dirty_cov.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_minimize_interesting.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_minimize_interesting.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_minimize_interesting.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_minimize_interesting.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_multiple.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_multiple.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_multiple.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_multiple.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_mutate_crash.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_mutate_crash.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_mutate_crash.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_mutate_crash.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_mutate_fail.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_mutate_fail.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_mutate_fail.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_mutate_fail.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_mutator.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_mutator.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_mutator.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_mutator.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_mutator_repeat.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_mutator_repeat.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_mutator_repeat.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_mutator_repeat.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_non_crash_signal.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_non_crash_signal.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_non_crash_signal.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_non_crash_signal.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_parallel.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_parallel.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_parallel.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_parallel.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_profile_flags.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_profile_flags.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_profile_flags.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_profile_flags.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_return.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_return.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_return.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_return.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_run.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_run.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_run.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_run.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_seed_corpus.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_seed_corpus.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_seed_corpus.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_seed_corpus.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_setenv.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_setenv.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_setenv.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_setenv.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_test_race.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_test_race.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_test_race.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_test_race.txt diff --git a/src/cmd/go/testdata/script/test_fuzz_unsupported.txt b/src/cmd/internal/fuzztest/testdata/script/test_fuzz_unsupported.txt similarity index 100% rename from src/cmd/go/testdata/script/test_fuzz_unsupported.txt rename to src/cmd/internal/fuzztest/testdata/script/test_fuzz_unsupported.txt diff --git a/src/cmd/internal/goobj/builtinlist.go b/src/cmd/internal/goobj/builtinlist.go index 9e21544391b47d..1d4f09ae6ff8e1 100644 --- a/src/cmd/internal/goobj/builtinlist.go +++ b/src/cmd/internal/goobj/builtinlist.go @@ -35,12 +35,15 @@ var builtins = [...]struct { {"runtime.goPanicSlice3CU", 1}, {"runtime.goPanicSliceConvert", 1}, {"runtime.printbool", 1}, - {"runtime.printfloat", 1}, + {"runtime.printfloat64", 1}, + {"runtime.printfloat32", 1}, {"runtime.printint", 1}, {"runtime.printhex", 1}, {"runtime.printuint", 1}, - {"runtime.printcomplex", 1}, + {"runtime.printcomplex128", 1}, + {"runtime.printcomplex64", 1}, {"runtime.printstring", 1}, + {"runtime.printquoted", 1}, {"runtime.printpointer", 1}, {"runtime.printuintptr", 1}, {"runtime.printiface", 1}, @@ -109,13 +112,11 @@ var builtins = [...]struct { {"runtime.mapassign_fast64", 1}, {"runtime.mapassign_fast64ptr", 1}, {"runtime.mapassign_faststr", 1}, - {"runtime.mapiterinit", 1}, {"runtime.mapIterStart", 1}, {"runtime.mapdelete", 1}, {"runtime.mapdelete_fast32", 1}, {"runtime.mapdelete_fast64", 1}, {"runtime.mapdelete_faststr", 1}, - {"runtime.mapiternext", 1}, {"runtime.mapIterNext", 1}, {"runtime.mapclear", 1}, {"runtime.makechan64", 1}, @@ -139,12 +140,19 @@ var builtins = [...]struct { {"runtime.makeslice64", 1}, {"runtime.makeslicecopy", 1}, {"runtime.growslice", 1}, + {"runtime.growsliceBuf", 1}, + {"runtime.growsliceBufNoAlias", 1}, + {"runtime.growsliceNoAlias", 1}, {"runtime.unsafeslicecheckptr", 1}, {"runtime.panicunsafeslicelen", 1}, {"runtime.panicunsafeslicenilptr", 1}, {"runtime.unsafestringcheckptr", 1}, {"runtime.panicunsafestringlen", 1}, {"runtime.panicunsafestringnilptr", 1}, + {"runtime.moveSlice", 1}, + {"runtime.moveSliceNoScan", 1}, + {"runtime.moveSliceNoCap", 1}, + {"runtime.moveSliceNoCapNoScan", 1}, {"runtime.memmove", 1}, {"runtime.memclrNoHeapPointers", 1}, {"runtime.memclrHasPointers", 1}, @@ -213,28 +221,54 @@ var builtins = [...]struct { {"runtime.libfuzzerHookStrCmp", 1}, {"runtime.libfuzzerHookEqualFold", 1}, {"runtime.addCovMeta", 1}, + {"runtime.x86HasAVX", 0}, + {"runtime.x86HasFMA", 0}, {"runtime.x86HasPOPCNT", 0}, {"runtime.x86HasSSE41", 0}, - {"runtime.x86HasFMA", 0}, {"runtime.armHasVFPv4", 0}, {"runtime.arm64HasATOMICS", 0}, {"runtime.loong64HasLAMCAS", 0}, {"runtime.loong64HasLAM_BH", 0}, + {"runtime.loong64HasDBAR_HINTS", 0}, {"runtime.loong64HasLSX", 0}, {"runtime.riscv64HasZbb", 0}, {"runtime.asanregisterglobals", 1}, + {"runtime.KeepAlive", 1}, {"runtime.deferproc", 1}, {"runtime.deferprocStack", 1}, {"runtime.deferreturn", 1}, {"runtime.newproc", 1}, {"runtime.panicoverflow", 1}, {"runtime.sigpanic", 1}, - {"runtime.gcWriteBarrier", 1}, + {"runtime.gcWriteBarrier1", 1}, + {"runtime.gcWriteBarrier2", 1}, + {"runtime.gcWriteBarrier3", 1}, + {"runtime.gcWriteBarrier4", 1}, + {"runtime.gcWriteBarrier5", 1}, + {"runtime.gcWriteBarrier6", 1}, + {"runtime.gcWriteBarrier7", 1}, + {"runtime.gcWriteBarrier8", 1}, {"runtime.duffzero", 1}, {"runtime.duffcopy", 1}, {"runtime.morestack", 0}, {"runtime.morestackc", 0}, {"runtime.morestack_noctxt", 0}, + {"runtime.retpolineAX", 0}, + {"runtime.retpolineCX", 0}, + {"runtime.retpolineDX", 0}, + {"runtime.retpolineBX", 0}, + {"runtime.retpolineBP", 0}, + {"runtime.retpolineSI", 0}, + {"runtime.retpolineDI", 0}, + {"runtime.retpolineR8", 0}, + {"runtime.retpolineR9", 0}, + {"runtime.retpolineR10", 0}, + {"runtime.retpolineR11", 0}, + {"runtime.retpolineR12", 0}, + {"runtime.retpolineR13", 0}, + {"runtime.retpolineR14", 0}, + {"runtime.retpolineR15", 0}, + {"runtime.tls_g", 0}, {"type:int8", 0}, {"type:*int8", 0}, {"type:uint8", 0}, diff --git a/src/cmd/internal/goobj/mkbuiltin.go b/src/cmd/internal/goobj/mkbuiltin.go index 6d1e7bb4297ac5..7e1c425c9d18bd 100644 --- a/src/cmd/internal/goobj/mkbuiltin.go +++ b/src/cmd/internal/goobj/mkbuiltin.go @@ -50,10 +50,10 @@ func main() { } func mkbuiltin(w io.Writer) { - pkg := "runtime" + const pkg = "runtime" fset := token.NewFileSet() path := filepath.Join("..", "..", "compile", "internal", "typecheck", "_builtin", "runtime.go") - f, err := parser.ParseFile(fset, path, nil, 0) + f, err := parser.ParseFile(fset, path, nil, parser.SkipObjectResolution) if err != nil { log.Fatal(err) } @@ -149,7 +149,14 @@ var fextras = [...]extra{ {"sigpanic", 1}, // compiler backend inserted calls - {"gcWriteBarrier", 1}, + {"gcWriteBarrier1", 1}, + {"gcWriteBarrier2", 1}, + {"gcWriteBarrier3", 1}, + {"gcWriteBarrier4", 1}, + {"gcWriteBarrier5", 1}, + {"gcWriteBarrier6", 1}, + {"gcWriteBarrier7", 1}, + {"gcWriteBarrier8", 1}, {"duffzero", 1}, {"duffcopy", 1}, @@ -157,4 +164,20 @@ var fextras = [...]extra{ {"morestack", 0}, // asm function, ABI0 {"morestackc", 0}, // asm function, ABI0 {"morestack_noctxt", 0}, // asm function, ABI0 + {"retpolineAX", 0}, // asm function, ABI0, amd64 only + {"retpolineCX", 0}, // asm function, ABI0, amd64 only + {"retpolineDX", 0}, // asm function, ABI0, amd64 only + {"retpolineBX", 0}, // asm function, ABI0, amd64 only + {"retpolineBP", 0}, // asm function, ABI0, amd64 only + {"retpolineSI", 0}, // asm function, ABI0, amd64 only + {"retpolineDI", 0}, // asm function, ABI0, amd64 only + {"retpolineR8", 0}, // asm function, ABI0, amd64 only + {"retpolineR9", 0}, // asm function, ABI0, amd64 only + {"retpolineR10", 0}, // asm function, ABI0, amd64 only + {"retpolineR11", 0}, // asm function, ABI0, amd64 only + {"retpolineR12", 0}, // asm function, ABI0, amd64 only + {"retpolineR13", 0}, // asm function, ABI0, amd64 only + {"retpolineR14", 0}, // asm function, ABI0, amd64 only + {"retpolineR15", 0}, // asm function, ABI0, amd64 only + {"tls_g", 0}, // asm variable, amd64 and 386 only } diff --git a/src/cmd/internal/goobj/objfile.go b/src/cmd/internal/goobj/objfile.go index cca3c840e0e9dc..679f4357e24cfc 100644 --- a/src/cmd/internal/goobj/objfile.go +++ b/src/cmd/internal/goobj/objfile.go @@ -306,6 +306,7 @@ const ( SymFlagDict SymFlagPkgInit SymFlagLinkname + SymFlagLinknameStd SymFlagABIWrapper SymFlagWasmExport ) @@ -340,6 +341,7 @@ func (s *Sym) IsItab() bool { return s.Flag2()&SymFlagItab != 0 } func (s *Sym) IsDict() bool { return s.Flag2()&SymFlagDict != 0 } func (s *Sym) IsPkgInit() bool { return s.Flag2()&SymFlagPkgInit != 0 } func (s *Sym) IsLinkname() bool { return s.Flag2()&SymFlagLinkname != 0 } +func (s *Sym) IsLinknameStd() bool { return s.Flag2()&SymFlagLinknameStd != 0 } func (s *Sym) ABIWrapper() bool { return s.Flag2()&SymFlagABIWrapper != 0 } func (s *Sym) WasmExport() bool { return s.Flag2()&SymFlagWasmExport != 0 } diff --git a/src/cmd/internal/macho/macho.go b/src/cmd/internal/macho/macho.go index ad29c32c50a8de..6c9907dbb487f2 100644 --- a/src/cmd/internal/macho/macho.go +++ b/src/cmd/internal/macho/macho.go @@ -100,7 +100,7 @@ func (r *LoadCmdReader) Next() (LoadCmd, error) { return cmd, nil } -func (r LoadCmdReader) ReadAt(offset int64, data interface{}) error { +func (r LoadCmdReader) ReadAt(offset int64, data any) error { if _, err := r.f.Seek(r.offset+offset, 0); err != nil { return err } @@ -117,7 +117,7 @@ func NewLoadCmdUpdater(f io.ReadWriteSeeker, order binary.ByteOrder, nextOffset return LoadCmdUpdater{NewLoadCmdReader(f, order, nextOffset)} } -func (u LoadCmdUpdater) WriteAt(offset int64, data interface{}) error { +func (u LoadCmdUpdater) WriteAt(offset int64, data any) error { if _, err := u.f.Seek(u.offset+offset, 0); err != nil { return err } diff --git a/src/cmd/internal/obj/abi_string.go b/src/cmd/internal/obj/abi_string.go index 77868eeac0da40..babb4bc6f66df0 100644 --- a/src/cmd/internal/obj/abi_string.go +++ b/src/cmd/internal/obj/abi_string.go @@ -18,8 +18,9 @@ const _ABI_name = "ABI0ABIInternalABICount" var _ABI_index = [...]uint8{0, 4, 15, 23} func (i ABI) String() string { - if i >= ABI(len(_ABI_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_ABI_index)-1 { return "ABI(" + strconv.FormatInt(int64(i), 10) + ")" } - return _ABI_name[_ABI_index[i]:_ABI_index[i+1]] + return _ABI_name[_ABI_index[idx]:_ABI_index[idx+1]] } diff --git a/src/cmd/internal/obj/addrtype_string.go b/src/cmd/internal/obj/addrtype_string.go index e6277d39b01242..6fac40562498f5 100644 --- a/src/cmd/internal/obj/addrtype_string.go +++ b/src/cmd/internal/obj/addrtype_string.go @@ -30,8 +30,9 @@ const _AddrType_name = "TYPE_NONETYPE_BRANCHTYPE_TEXTSIZETYPE_MEMTYPE_CONSTTYPE_ var _AddrType_index = [...]uint8{0, 9, 20, 33, 41, 51, 62, 73, 81, 90, 100, 111, 123, 133, 145, 157} func (i AddrType) String() string { - if i >= AddrType(len(_AddrType_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_AddrType_index)-1 { return "AddrType(" + strconv.FormatInt(int64(i), 10) + ")" } - return _AddrType_name[_AddrType_index[i]:_AddrType_index[i+1]] + return _AddrType_name[_AddrType_index[idx]:_AddrType_index[idx+1]] } diff --git a/src/cmd/internal/obj/arm/asm5.go b/src/cmd/internal/obj/arm/asm5.go index 1e2891de0a7ddc..9f59e0a287e25d 100644 --- a/src/cmd/internal/obj/arm/asm5.go +++ b/src/cmd/internal/obj/arm/asm5.go @@ -141,8 +141,8 @@ var optab = []Optab{ {AMVN, C_NCON, C_NONE, C_REG, 12, 4, 0, 0, 0, 0}, {AADD, C_NCON, C_REG, C_REG, 13, 8, 0, 0, 0, C_SBIT}, {AADD, C_NCON, C_NONE, C_REG, 13, 8, 0, 0, 0, C_SBIT}, - {AAND, C_NCON, C_REG, C_REG, 13, 8, 0, 0, 0, C_SBIT}, - {AAND, C_NCON, C_NONE, C_REG, 13, 8, 0, 0, 0, C_SBIT}, + {AAND, C_NCON, C_REG, C_REG, 114, 4, 0, 0, 0, C_SBIT}, + {AAND, C_NCON, C_NONE, C_REG, 114, 4, 0, 0, 0, C_SBIT}, {AORR, C_NCON, C_REG, C_REG, 13, 8, 0, 0, 0, C_SBIT}, {AORR, C_NCON, C_NONE, C_REG, 13, 8, 0, 0, 0, C_SBIT}, {ACMP, C_NCON, C_REG, C_NONE, 13, 8, 0, 0, 0, 0}, @@ -2553,6 +2553,21 @@ func (c *ctxt5) asmout(p *obj.Prog, o *Optab, out []uint32) { c.ctxt.Diag("illegal mb option:\n%v", p) } o1 |= mbop + + case 114: /* AND $C_NCON, [R], R -> BIC $~C_NCON, [R], R */ + // AND with an immediate that is not encodable as a rotated 8-bit + // value, but whose bitwise complement is, can be emitted as a + // single BIC instruction without a scratch register. This avoids + // the MVN+AND synthesis used by case 13, which clobbers REGTMP. + c.aclass(&p.From) + o1 = c.oprrr(p, ABIC, int(p.Scond)) + o1 |= uint32(immrot(^uint32(c.instoffset))) + rt := int(p.To.Reg) + r := int(p.Reg) + if r == 0 { + r = rt + } + o1 |= (uint32(r)&15)<<16 | (uint32(rt)&15)<<12 } out[0] = o1 diff --git a/src/cmd/internal/obj/arm/obj5.go b/src/cmd/internal/obj/arm/obj5.go index 79f08a41eae37b..f76a9f7a6ec430 100644 --- a/src/cmd/internal/obj/arm/obj5.go +++ b/src/cmd/internal/obj/arm/obj5.go @@ -352,16 +352,27 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { case obj.ARET: nocache(p) + + retSym, retReg := p.To.Sym, p.To.Reg + if retReg == obj.REG_NONE { + retReg = REGLINK + } + p.To.Sym = nil + p.To.Name = obj.NAME_NONE + p.To.Reg = obj.REG_NONE + if cursym.Func().Text.Mark&LEAF != 0 { if autosize == 0 { p.As = AB p.From = obj.Addr{} - if p.To.Sym != nil { // retjmp + if retSym != nil { // retjmp p.To.Type = obj.TYPE_BRANCH + p.To.Name = obj.NAME_EXTERN + p.To.Sym = retSym } else { p.To.Type = obj.TYPE_MEM p.To.Offset = 0 - p.To.Reg = REGLINK + p.To.Reg = retReg } break @@ -378,16 +389,25 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { // If there are instructions following // this ARET, they come from a branch - // with the same stackframe, so no spadj. + // with the same stackframe, so spadj should + // sum to 0. - if p.To.Sym != nil { // retjmp + if retSym != nil || retReg != REGLINK { // retjmp p.To.Reg = REGLINK + // If ARET is a tail-call, the frame pop + // and jump are in separate instructions + // and spadj is needed. + p.Spadj = -autosize q2 = obj.Appendp(p, newprog) q2.As = AB - q2.To.Type = obj.TYPE_BRANCH - q2.To.Sym = p.To.Sym - p.To.Sym = nil - p.To.Name = obj.NAME_NONE + q2.Spadj = +autosize + if retSym != nil { + q2.To.Type = obj.TYPE_BRANCH + q2.To.Sym = retSym + } else { + q2.To.Type = obj.TYPE_MEM + q2.To.Reg = retReg + } p = q2 } diff --git a/src/cmd/internal/obj/arm64/a.out.go b/src/cmd/internal/obj/arm64/a.out.go index 814dba2c100b30..1426c72ee050eb 100644 --- a/src/cmd/internal/obj/arm64/a.out.go +++ b/src/cmd/internal/obj/arm64/a.out.go @@ -143,24 +143,106 @@ const ( REG_V30 REG_V31 - REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31 + // SVE (Scalable Vector Extension) scalable vector registers + // The order matters, make sure that each + // kind of register starts numbering from the lowest bit. + REG_Z0 + REG_Z1 + REG_Z2 + REG_Z3 + REG_Z4 + REG_Z5 + REG_Z6 + REG_Z7 + REG_Z8 + REG_Z9 + REG_Z10 + REG_Z11 + REG_Z12 + REG_Z13 + REG_Z14 + REG_Z15 + REG_Z16 + REG_Z17 + REG_Z18 + REG_Z19 + REG_Z20 + REG_Z21 + REG_Z22 + REG_Z23 + REG_Z24 + REG_Z25 + REG_Z26 + REG_Z27 + REG_Z28 + REG_Z29 + REG_Z30 + REG_Z31 + + REG_P0 + REG_P1 + REG_P2 + REG_P3 + REG_P4 + REG_P5 + REG_P6 + REG_P7 + REG_P8 + REG_P9 + REG_P10 + REG_P11 + REG_P12 + REG_P13 + REG_P14 + REG_P15 + + REG_PN0 + REG_PN1 + REG_PN2 + REG_PN3 + REG_PN4 + REG_PN5 + REG_PN6 + REG_PN7 + REG_PN8 + REG_PN9 + REG_PN10 + REG_PN11 + REG_PN12 + REG_PN13 + REG_PN14 + REG_PN15 + + REG_RSP = (REG_PN15 + 1) | 0x1f // to differentiate ZR/SP, REG_RSP&0x1f = 31 ) // bits 0-4 indicates register: Vn // bits 5-8 indicates arrangement: +// TODO: consider putting the register and arrangement in different fields of an +// [obj.Prog] to make the bit pattern less confusing. const ( - REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn. - REG_ELEM // Vn.[index] - REG_ELEM_END + REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn. + REG_ELEM // Vn.[index] + REG_ZARNG // Zn. + REG_ZARNGELEM // Zn.[index] + // PZELEM is taking a portion of the P or Z register. + // Since it does not have an arrangement, it interpret bit 5 differently: + // bit 5 = 0: Z register + // bit 5 = 1: P register + REG_PZELEM // Zn[index] or Pn[index] or PNd[index] + REG_PARNGZM // Pn. or Pn/M, Pn/Z + // This currently overlaps with REG_EXT, if more arrangements are to be added, + // move REG_EXT to a higher range and update RBase.*. + REG_PARNGZM_END ) // Not registers, but flags that can be combined with regular register // constants to indicate extended register conversion. When checking, -// you should subtract obj.RBaseARM64 first. From this difference, bit 11 +// you should subtract obj.RBaseARM64 first. From this difference, bit 12 // indicates extended register, bits 8-10 select the conversion mode. // REG_LSL is the index shift specifier, bit 9 indicates shifted offset register. const REG_LSL = obj.RBaseARM64 + 1<<9 -const REG_EXT = obj.RBaseARM64 + 1<<11 +const REG_EXT = obj.RBaseARM64 + 1<<12 const ( REG_UXTB = REG_EXT + iota<<8 @@ -173,14 +255,14 @@ const ( REG_SXTX ) -// Special registers, after subtracting obj.RBaseARM64, bit 12 indicates +// Special registers, after subtracting obj.RBaseARM64, bit 13 indicates // a special register and the low bits select the register. // SYSREG_END is the last item in the automatically generated system register // declaration, and it is defined in the sysRegEnc.go file. // Define the special register after REG_SPECIAL, the first value of it should be // REG_{name} = SYSREG_END + iota. const ( - REG_SPECIAL = obj.RBaseARM64 + 1<<12 + REG_SPECIAL = obj.RBaseARM64 + 1<<13 ) // Register assignments: @@ -250,6 +332,24 @@ var ARM64DWARFRegisters = map[int16]int16{ REG_R29: 29, REG_R30: 30, + // SVE predicate registers + REG_P0: 48, + REG_P1: 49, + REG_P2: 50, + REG_P3: 51, + REG_P4: 52, + REG_P5: 53, + REG_P6: 54, + REG_P7: 55, + REG_P8: 56, + REG_P9: 57, + REG_P10: 58, + REG_P11: 59, + REG_P12: 60, + REG_P13: 61, + REG_P14: 62, + REG_P15: 63, + // floating point REG_F0: 64, REG_F1: 65, @@ -317,6 +417,40 @@ var ARM64DWARFRegisters = map[int16]int16{ REG_V29: 93, REG_V30: 94, REG_V31: 95, + + // SVE vector registers + REG_Z0: 96, + REG_Z1: 97, + REG_Z2: 98, + REG_Z3: 99, + REG_Z4: 100, + REG_Z5: 101, + REG_Z6: 102, + REG_Z7: 103, + REG_Z8: 104, + REG_Z9: 105, + REG_Z10: 106, + REG_Z11: 107, + REG_Z12: 108, + REG_Z13: 109, + REG_Z14: 110, + REG_Z15: 111, + REG_Z16: 112, + REG_Z17: 113, + REG_Z18: 114, + REG_Z19: 115, + REG_Z20: 116, + REG_Z21: 117, + REG_Z22: 118, + REG_Z23: 119, + REG_Z24: 120, + REG_Z25: 121, + REG_Z26: 122, + REG_Z27: 123, + REG_Z28: 124, + REG_Z29: 125, + REG_Z30: 126, + REG_Z31: 127, } const ( @@ -485,6 +619,42 @@ const ( C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it ) +type AClass uint16 // operand type + +// [insts] is sorted based on the order of these constants and the first match is chosen. +const ( + AC_NONE AClass = iota + // TODO: probably make this AClass split into AC_REG (R0...R30), AC_RSP (R0...R30, RSP), AC_ZR (R0...R30, ZR). + AC_SPZGREG // general purpose registers R0..R30 and RSP and ZR + AC_VREG // vector registers, such as V1 + AC_ZREG // the scalable vector registers, such as Z1 + AC_PREG // the scalable predicate registers, such as P1 + AC_PREGZM // Pg.Z or Pg.M + AC_PREGIDX // P8[1] or PN1[1] or Z1[1] + AC_ZREGIDX // P8[1] or PN1[1] or Z1[1] + AC_PREGSEL // P0[R1, 1], index is calculated as R1 + 1 + AC_ARNG // vector register with arrangement, such as Z1.D + AC_ARNGIDX // vector register with arrangement and index, such as Z1.D[1] + + AC_IMM // constants + + AC_REGLIST1 // list of 1 vector register, such as [Z1] + AC_REGLIST2 // list of 2 vector registers, such as [Z0, Z8] + AC_REGLIST3 // list of 3 vector registers, such as [Z1, Z2, Z3] + AC_REGLIST4 // list of 4 vector registers, such as [Z0, Z4, Z8, Z12] + AC_REGLIST_RANGE // list of vector register lists in range format, such as [Z0-Z4]. + + AC_MEMOFF // address with optional constant offset, the offset is an immediate, such as 4(Z1.D) + AC_MEMOFFMULVL // address with optional constant offset, the offset is an immediate multiplied by the vector's in-memory size, such as (2*VL)(Z1.D) + AC_MEMEXT // address with register offset with extensions, such as (Z2.D.UXTW<<3)(RSP) + + AC_PREG_PATTERN // register with pattern, such as VL1*3(P1.D) + AC_REG_PATTERN // register with pattern, such as VL1*3(R1) + AC_ZREG_PATTERN // register with pattern, such as VL1*3(Z1.D) + + AC_SPECIAL // VL*i pattern, one of: VL*2, VL*4, or prefetch pattern, such as PLDL1KEEP, more patterns might come in the future. +) + //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64 const ( @@ -836,6 +1006,8 @@ const ( AREVW AROR ARORW + ARPRFM + ASB ASBC ASBCS ASBCSW @@ -951,13 +1123,31 @@ const ( AUXTW AVADD AVADDP + AVSHADD + AVSRHADD AVADDV + AVFMAXV + AVFMAXNMV + AVFMINV + AVFMINNMV + AVSMAXV + AVSMINV + AVUMAXV + AVUMINV AVAND AVBCAX AVBIF AVBIT AVBSL AVCMEQ + AVCLS + AVCLZ + AVCMGE + AVCMGT + AVCMHI + AVCMHS + AVCMLE + AVCMLT AVCMTST AVCNT AVDUP @@ -966,6 +1156,35 @@ const ( AVEXT AVFMLA AVFMLS + AVFCMEQ + AVFCMGE + AVFCMGT + AVFCMLE + AVFCMLT + AVFADDP + AVFADD + AVFSUB + AVFMUL + AVFDIV + AVFMAX + AVFMAXNM + AVFMAXP + AVFMIN + AVFMINNM + AVFMINP + AVFMAXNMP + AVFMINNMP + AVSQADD + AVUQADD + AVSQSUB + AVSQABS + AVSQNEG + AVUQSUB + AVUHADD + AVURHADD + AVMUL + AVMLA + AVMLS AVLD1 AVLD1R AVLD2 @@ -980,21 +1199,55 @@ const ( AVMOVQ AVMOVS AVORR + AVORN + AVBIC AVPMULL AVPMULL2 + AVSMLAL + AVSMLAL2 + AVSMLSL + AVSMLSL2 + AVSMULL + AVSMULL2 + AVUMLAL + AVUMLAL2 + AVUMLSL + AVUMLSL2 + AVUMULL + AVUMULL2 AVRAX1 AVRBIT AVREV16 AVREV32 AVREV64 + AVABS + AVFABS + AVFNEG + AVFSQRT + AVFRINTN + AVFRINTP + AVFRINTM + AVFRINTZ + AVNEG + AVNOT AVSHL + AVSHRN + AVSHRN2 AVSLI + AVSQSHL + AVSSHL + AVUSHL + AVUQSHL AVSRI AVST1 AVST2 AVST3 AVST4 AVSUB + AVSMAX + AVSMIN + AVSMAXP + AVSMINP AVTBL AVTBX AVTRN1 @@ -1004,12 +1257,36 @@ const ( AVUADDW2 AVUMAX AVUMIN + AVUMAXP + AVUMINP AVUSHLL AVUSHLL2 AVUSHR + AVSRSHR + AVSSHR AVUSRA AVUXTL AVUXTL2 + AVXTN + AVXTN2 + AVSSHLL + AVSSHLL2 + AVSXTL + AVSXTL2 + AVSQXTN + AVSQXTN2 + AVSQXTUN + AVSQXTUN2 + AVUQXTN + AVUQXTN2 + AVFCVTZS + AVFCVTZU + AVSCVTF + AVUCVTF + AVFCVTN + AVFCVTN2 + AVFCVTL + AVFCVTL2 AVUZP1 AVUZP2 AVXAR @@ -1026,7 +1303,7 @@ const ( AAUTIBSP AAUTIA1716 AAUTIB1716 - ALAST + ASVESTART AB = obj.AJMP ABL = obj.ACALL ) @@ -1055,6 +1332,9 @@ const ( ARNG_H ARNG_S ARNG_D + ARNG_Q + PRED_M + PRED_Z ) //go:generate stringer -type SpecialOperand -trimprefix SPOP_ @@ -1082,6 +1362,10 @@ const ( SPOP_PSTL3KEEP SPOP_PSTL3STRM + // VL + SPOP_VLx2 + SPOP_VLx4 + // TLBI SPOP_VMALLE1IS SPOP_VAE1IS @@ -1219,5 +1503,11 @@ const ( SPOP_J SPOP_JC + // Range PReFetch of Memory (RPRFM) + SPOP_PLDKEEP + SPOP_PSTKEEP + SPOP_PLDSTRM + SPOP_PSTSTRM + SPOP_END ) diff --git a/src/cmd/internal/obj/arm64/anames.go b/src/cmd/internal/obj/arm64/anames.go index 497429d9985922..62620e8737cd97 100644 --- a/src/cmd/internal/obj/arm64/anames.go +++ b/src/cmd/internal/obj/arm64/anames.go @@ -353,6 +353,8 @@ var Anames = []string{ "REVW", "ROR", "RORW", + "RPRFM", + "SB", "SBC", "SBCS", "SBCSW", @@ -468,13 +470,31 @@ var Anames = []string{ "UXTW", "VADD", "VADDP", + "VSHADD", + "VSRHADD", "VADDV", + "VFMAXV", + "VFMAXNMV", + "VFMINV", + "VFMINNMV", + "VSMAXV", + "VSMINV", + "VUMAXV", + "VUMINV", "VAND", "VBCAX", "VBIF", "VBIT", "VBSL", "VCMEQ", + "VCLS", + "VCLZ", + "VCMGE", + "VCMGT", + "VCMHI", + "VCMHS", + "VCMLE", + "VCMLT", "VCMTST", "VCNT", "VDUP", @@ -483,6 +503,35 @@ var Anames = []string{ "VEXT", "VFMLA", "VFMLS", + "VFCMEQ", + "VFCMGE", + "VFCMGT", + "VFCMLE", + "VFCMLT", + "VFADDP", + "VFADD", + "VFSUB", + "VFMUL", + "VFDIV", + "VFMAX", + "VFMAXNM", + "VFMAXP", + "VFMIN", + "VFMINNM", + "VFMINP", + "VFMAXNMP", + "VFMINNMP", + "VSQADD", + "VUQADD", + "VSQSUB", + "VSQABS", + "VSQNEG", + "VUQSUB", + "VUHADD", + "VURHADD", + "VMUL", + "VMLA", + "VMLS", "VLD1", "VLD1R", "VLD2", @@ -497,21 +546,55 @@ var Anames = []string{ "VMOVQ", "VMOVS", "VORR", + "VORN", + "VBIC", "VPMULL", "VPMULL2", + "VSMLAL", + "VSMLAL2", + "VSMLSL", + "VSMLSL2", + "VSMULL", + "VSMULL2", + "VUMLAL", + "VUMLAL2", + "VUMLSL", + "VUMLSL2", + "VUMULL", + "VUMULL2", "VRAX1", "VRBIT", "VREV16", "VREV32", "VREV64", + "VABS", + "VFABS", + "VFNEG", + "VFSQRT", + "VFRINTN", + "VFRINTP", + "VFRINTM", + "VFRINTZ", + "VNEG", + "VNOT", "VSHL", + "VSHRN", + "VSHRN2", "VSLI", + "VSQSHL", + "VSSHL", + "VUSHL", + "VUQSHL", "VSRI", "VST1", "VST2", "VST3", "VST4", "VSUB", + "VSMAX", + "VSMIN", + "VSMAXP", + "VSMINP", "VTBL", "VTBX", "VTRN1", @@ -521,12 +604,36 @@ var Anames = []string{ "VUADDW2", "VUMAX", "VUMIN", + "VUMAXP", + "VUMINP", "VUSHLL", "VUSHLL2", "VUSHR", + "VSRSHR", + "VSSHR", "VUSRA", "VUXTL", "VUXTL2", + "VXTN", + "VXTN2", + "VSSHLL", + "VSSHLL2", + "VSXTL", + "VSXTL2", + "VSQXTN", + "VSQXTN2", + "VSQXTUN", + "VSQXTUN2", + "VUQXTN", + "VUQXTN2", + "VFCVTZS", + "VFCVTZU", + "VSCVTF", + "VUCVTF", + "VFCVTN", + "VFCVTN2", + "VFCVTL", + "VFCVTL2", "VUZP1", "VUZP2", "VXAR", @@ -543,5 +650,4 @@ var Anames = []string{ "AUTIBSP", "AUTIA1716", "AUTIB1716", - "LAST", } diff --git a/src/cmd/internal/obj/arm64/anames_gen.go b/src/cmd/internal/obj/arm64/anames_gen.go new file mode 100644 index 00000000000000..7195f58fdd71f9 --- /dev/null +++ b/src/cmd/internal/obj/arm64/anames_gen.go @@ -0,0 +1,708 @@ +// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT. + +package arm64 + +var sveAnames = []string{ + "SVESTART", + "ADDPL", + "ADDVL", + "CTERMEQ", + "CTERMEQW", + "CTERMNE", + "CTERMNEW", + "PAND", + "PANDS", + "PBIC", + "PBICS", + "PBRKA", + "PBRKAS", + "PBRKB", + "PBRKBS", + "PBRKN", + "PBRKNS", + "PBRKPA", + "PBRKPAS", + "PBRKPB", + "PBRKPBS", + "PCNTP", + "PDECP", + "PEOR", + "PEORS", + "PFIRSTP", + "PINCP", + "PLASTP", + "PLDR", + "PNAND", + "PNANDS", + "PNOR", + "PNORS", + "PORN", + "PORNS", + "PORR", + "PORRS", + "PPEXT", + "PPFALSE", + "PPFIRST", + "PPNEXT", + "PPRFB", + "PPRFD", + "PPRFH", + "PPRFW", + "PPTEST", + "PPTRUE", + "PPUNPKHI", + "PPUNPKLO", + "PRDFFR", + "PRDFFRS", + "PREV", + "PSEL", + "PSQDECP", + "PSQDECPW", + "PSQINCP", + "PSQINCPW", + "PSTR", + "PTRN1", + "PTRN2", + "PUQDECP", + "PUQDECPW", + "PUQINCP", + "PUQINCPW", + "PUZP1", + "PUZP2", + "PWHILEGE", + "PWHILEGEW", + "PWHILEGT", + "PWHILEGTW", + "PWHILEHI", + "PWHILEHIW", + "PWHILEHS", + "PWHILEHSW", + "PWHILELE", + "PWHILELEW", + "PWHILELO", + "PWHILELOW", + "PWHILELS", + "PWHILELSW", + "PWHILELT", + "PWHILELTW", + "PWHILERW", + "PWHILEWR", + "PWRFFR", + "PZIP1", + "PZIP2", + "RDVL", + "SETFFR", + "ZABS", + "ZADCLB", + "ZADCLT", + "ZADD", + "ZADDHNB", + "ZADDHNT", + "ZADDP", + "ZADDPT", + "ZADDQP", + "ZADDQV", + "ZADDSUBP", + "ZADR", + "ZAESD", + "ZAESDIMC", + "ZAESE", + "ZAESEMC", + "ZAESIMC", + "ZAESMC", + "ZAND", + "ZANDQV", + "ZANDVB", + "ZANDVD", + "ZANDVH", + "ZANDVS", + "ZASR", + "ZASRD", + "ZASRR", + "ZBCAX", + "ZBDEP", + "ZBEXT", + "ZBF1CVT", + "ZBF1CVTLT", + "ZBF2CVT", + "ZBF2CVTLT", + "ZBFADD", + "ZBFCLAMP", + "ZBFCVT", + "ZBFCVTN", + "ZBFCVTNT", + "ZBFDOT", + "ZBFMAX", + "ZBFMAXNM", + "ZBFMIN", + "ZBFMINNM", + "ZBFMLA", + "ZBFMLALB", + "ZBFMLALT", + "ZBFMLS", + "ZBFMLSLB", + "ZBFMLSLT", + "ZBFMMLA", + "ZBFMUL", + "ZBFSCALE", + "ZBFSUB", + "ZBGRP", + "ZBIC", + "ZBSL", + "ZBSL1N", + "ZBSL2N", + "ZCADD", + "ZCDOT", + "ZCLASTA", + "ZCLASTAB", + "ZCLASTAD", + "ZCLASTAH", + "ZCLASTAS", + "ZCLASTAW", + "ZCLASTB", + "ZCLASTBB", + "ZCLASTBD", + "ZCLASTBH", + "ZCLASTBS", + "ZCLASTBW", + "ZCLS", + "ZCLZ", + "ZCMLA", + "ZCMPEQ", + "ZCMPGE", + "ZCMPGT", + "ZCMPHI", + "ZCMPHS", + "ZCMPLE", + "ZCMPLO", + "ZCMPLS", + "ZCMPLT", + "ZCMPNE", + "ZCNOT", + "ZCNT", + "ZCOMPACT", + "ZCPY", + "ZCPYB", + "ZCPYD", + "ZCPYH", + "ZCPYS", + "ZCPYW", + "ZDECP", + "ZDUP", + "ZDUPM", + "ZDUPQ", + "ZDUPW", + "ZEOR", + "ZEOR3", + "ZEORBT", + "ZEORQV", + "ZEORTB", + "ZEORVB", + "ZEORVD", + "ZEORVH", + "ZEORVS", + "ZEXPAND", + "ZEXT", + "ZEXTQ", + "ZF1CVT", + "ZF1CVTLT", + "ZF2CVT", + "ZF2CVTLT", + "ZFABD", + "ZFABS", + "ZFACGE", + "ZFACGT", + "ZFADD", + "ZFADDAD", + "ZFADDAH", + "ZFADDAS", + "ZFADDP", + "ZFADDQV", + "ZFADDVD", + "ZFADDVH", + "ZFADDVS", + "ZFAMAX", + "ZFAMIN", + "ZFCADD", + "ZFCLAMP", + "ZFCMEQ", + "ZFCMGE", + "ZFCMGT", + "ZFCMLA", + "ZFCMLE", + "ZFCMLT", + "ZFCMNE", + "ZFCMUO", + "ZFCPY", + "ZFCVT", + "ZFCVTLT", + "ZFCVTN", + "ZFCVTNB", + "ZFCVTNT", + "ZFCVTX", + "ZFCVTXNT", + "ZFCVTZS", + "ZFCVTZSN", + "ZFCVTZU", + "ZFCVTZUN", + "ZFDIV", + "ZFDIVR", + "ZFDOT", + "ZFDUP", + "ZFEXPA", + "ZFLOGB", + "ZFMAD", + "ZFMAX", + "ZFMAXNM", + "ZFMAXNMP", + "ZFMAXNMQV", + "ZFMAXNMVD", + "ZFMAXNMVH", + "ZFMAXNMVS", + "ZFMAXP", + "ZFMAXQV", + "ZFMAXVD", + "ZFMAXVH", + "ZFMAXVS", + "ZFMIN", + "ZFMINNM", + "ZFMINNMP", + "ZFMINNMQV", + "ZFMINNMVD", + "ZFMINNMVH", + "ZFMINNMVS", + "ZFMINP", + "ZFMINQV", + "ZFMINVD", + "ZFMINVH", + "ZFMINVS", + "ZFMLA", + "ZFMLALB", + "ZFMLALLBB", + "ZFMLALLBT", + "ZFMLALLTB", + "ZFMLALLTT", + "ZFMLALT", + "ZFMLS", + "ZFMLSLB", + "ZFMLSLT", + "ZFMMLA", + "ZFMSB", + "ZFMUL", + "ZFMULX", + "ZFNEG", + "ZFNMAD", + "ZFNMLA", + "ZFNMLS", + "ZFNMSB", + "ZFRECPE", + "ZFRECPS", + "ZFRECPX", + "ZFRINT32X", + "ZFRINT32Z", + "ZFRINT64X", + "ZFRINT64Z", + "ZFRINTA", + "ZFRINTI", + "ZFRINTM", + "ZFRINTN", + "ZFRINTP", + "ZFRINTX", + "ZFRINTZ", + "ZFRSQRTE", + "ZFRSQRTS", + "ZFSCALE", + "ZFSQRT", + "ZFSUB", + "ZFSUBR", + "ZFTMAD", + "ZFTSMUL", + "ZFTSSEL", + "ZHISTCNT", + "ZHISTSEG", + "ZINCP", + "ZINDEX", + "ZINDEXW", + "ZINSR", + "ZINSRB", + "ZINSRD", + "ZINSRH", + "ZINSRS", + "ZINSRW", + "ZLASTA", + "ZLASTAB", + "ZLASTAD", + "ZLASTAH", + "ZLASTAS", + "ZLASTAW", + "ZLASTB", + "ZLASTBB", + "ZLASTBD", + "ZLASTBH", + "ZLASTBS", + "ZLASTBW", + "ZLD1B", + "ZLD1D", + "ZLD1H", + "ZLD1Q", + "ZLD1RB", + "ZLD1RD", + "ZLD1RH", + "ZLD1ROB", + "ZLD1ROD", + "ZLD1ROH", + "ZLD1ROW", + "ZLD1RQB", + "ZLD1RQD", + "ZLD1RQH", + "ZLD1RQW", + "ZLD1RSB", + "ZLD1RSH", + "ZLD1RSW", + "ZLD1RW", + "ZLD1SB", + "ZLD1SH", + "ZLD1SW", + "ZLD1W", + "ZLD2B", + "ZLD2D", + "ZLD2H", + "ZLD2Q", + "ZLD2W", + "ZLD3B", + "ZLD3D", + "ZLD3H", + "ZLD3Q", + "ZLD3W", + "ZLD4B", + "ZLD4D", + "ZLD4H", + "ZLD4Q", + "ZLD4W", + "ZLDFF1B", + "ZLDFF1D", + "ZLDFF1H", + "ZLDFF1SB", + "ZLDFF1SH", + "ZLDFF1SW", + "ZLDFF1W", + "ZLDNF1B", + "ZLDNF1D", + "ZLDNF1H", + "ZLDNF1SB", + "ZLDNF1SH", + "ZLDNF1SW", + "ZLDNF1W", + "ZLDNT1B", + "ZLDNT1D", + "ZLDNT1H", + "ZLDNT1SB", + "ZLDNT1SH", + "ZLDNT1SW", + "ZLDNT1W", + "ZLDR", + "ZLSL", + "ZLSLR", + "ZLSR", + "ZLSRR", + "ZLUTI2", + "ZLUTI4", + "ZLUTI6", + "ZMAD", + "ZMADPT", + "ZMATCH", + "ZMLA", + "ZMLAPT", + "ZMLS", + "ZMOVPRFX", + "ZMSB", + "ZMUL", + "ZNBSL", + "ZNEG", + "ZNMATCH", + "ZNOT", + "ZORQV", + "ZORR", + "ZORVB", + "ZORVD", + "ZORVH", + "ZORVS", + "ZPMLAL", + "ZPMOV", + "ZPMUL", + "ZPMULL", + "ZPMULLB", + "ZPMULLT", + "ZPRFB", + "ZPRFD", + "ZPRFH", + "ZPRFW", + "ZRADDHNB", + "ZRADDHNT", + "ZRAX1", + "ZRBIT", + "ZREV", + "ZREVB", + "ZREVD", + "ZREVH", + "ZREVW", + "ZRSHRNB", + "ZRSHRNT", + "ZRSUBHNB", + "ZRSUBHNT", + "ZSABA", + "ZSABAL", + "ZSABALB", + "ZSABALT", + "ZSABD", + "ZSABDLB", + "ZSABDLT", + "ZSADALP", + "ZSADDLB", + "ZSADDLBT", + "ZSADDLT", + "ZSADDVD", + "ZSADDWB", + "ZSADDWT", + "ZSBCLB", + "ZSBCLT", + "ZSCLAMP", + "ZSCVTF", + "ZSCVTFLT", + "ZSDIV", + "ZSDIVR", + "ZSDOT", + "ZSEL", + "ZSHADD", + "ZSHRNB", + "ZSHRNT", + "ZSHSUB", + "ZSHSUBR", + "ZSLI", + "ZSM4E", + "ZSM4EKEY", + "ZSMAX", + "ZSMAXP", + "ZSMAXQV", + "ZSMAXVB", + "ZSMAXVD", + "ZSMAXVH", + "ZSMAXVS", + "ZSMIN", + "ZSMINP", + "ZSMINQV", + "ZSMINVB", + "ZSMINVD", + "ZSMINVH", + "ZSMINVS", + "ZSMLALB", + "ZSMLALT", + "ZSMLSLB", + "ZSMLSLT", + "ZSMMLA", + "ZSMULH", + "ZSMULLB", + "ZSMULLT", + "ZSPLICE", + "ZSQABS", + "ZSQADD", + "ZSQCADD", + "ZSQCVTN", + "ZSQCVTUN", + "ZSQDECP", + "ZSQDMLALB", + "ZSQDMLALBT", + "ZSQDMLALT", + "ZSQDMLSLB", + "ZSQDMLSLBT", + "ZSQDMLSLT", + "ZSQDMULH", + "ZSQDMULLB", + "ZSQDMULLT", + "ZSQINCP", + "ZSQNEG", + "ZSQRDCMLAH", + "ZSQRDMLAH", + "ZSQRDMLSH", + "ZSQRDMULH", + "ZSQRSHL", + "ZSQRSHLR", + "ZSQRSHRN", + "ZSQRSHRNB", + "ZSQRSHRNT", + "ZSQRSHRUN", + "ZSQRSHRUNB", + "ZSQRSHRUNT", + "ZSQSHL", + "ZSQSHLR", + "ZSQSHLU", + "ZSQSHRN", + "ZSQSHRNB", + "ZSQSHRNT", + "ZSQSHRUN", + "ZSQSHRUNB", + "ZSQSHRUNT", + "ZSQSUB", + "ZSQSUBR", + "ZSQXTNB", + "ZSQXTNT", + "ZSQXTUNB", + "ZSQXTUNT", + "ZSRHADD", + "ZSRI", + "ZSRSHL", + "ZSRSHLR", + "ZSRSHR", + "ZSRSRA", + "ZSSHLLB", + "ZSSHLLT", + "ZSSRA", + "ZSSUBLB", + "ZSSUBLBT", + "ZSSUBLT", + "ZSSUBLTB", + "ZSSUBWB", + "ZSSUBWT", + "ZST1B", + "ZST1D", + "ZST1H", + "ZST1Q", + "ZST1W", + "ZST2B", + "ZST2D", + "ZST2H", + "ZST2Q", + "ZST2W", + "ZST3B", + "ZST3D", + "ZST3H", + "ZST3Q", + "ZST3W", + "ZST4B", + "ZST4D", + "ZST4H", + "ZST4Q", + "ZST4W", + "ZSTNT1B", + "ZSTNT1D", + "ZSTNT1H", + "ZSTNT1W", + "ZSTR", + "ZSUB", + "ZSUBHNB", + "ZSUBHNT", + "ZSUBP", + "ZSUBPT", + "ZSUBR", + "ZSUDOT", + "ZSUNPKHI", + "ZSUNPKLO", + "ZSUQADD", + "ZSXTB", + "ZSXTH", + "ZSXTW", + "ZTBL", + "ZTBLQ", + "ZTBX", + "ZTBXQ", + "ZTRN1", + "ZTRN2", + "ZUABA", + "ZUABAL", + "ZUABALB", + "ZUABALT", + "ZUABD", + "ZUABDLB", + "ZUABDLT", + "ZUADALP", + "ZUADDLB", + "ZUADDLT", + "ZUADDVD", + "ZUADDWB", + "ZUADDWT", + "ZUCLAMP", + "ZUCVTF", + "ZUCVTFLT", + "ZUDIV", + "ZUDIVR", + "ZUDOT", + "ZUHADD", + "ZUHSUB", + "ZUHSUBR", + "ZUMAX", + "ZUMAXP", + "ZUMAXQV", + "ZUMAXVB", + "ZUMAXVD", + "ZUMAXVH", + "ZUMAXVS", + "ZUMIN", + "ZUMINP", + "ZUMINQV", + "ZUMINVB", + "ZUMINVD", + "ZUMINVH", + "ZUMINVS", + "ZUMLALB", + "ZUMLALT", + "ZUMLSLB", + "ZUMLSLT", + "ZUMMLA", + "ZUMULH", + "ZUMULLB", + "ZUMULLT", + "ZUQADD", + "ZUQCVTN", + "ZUQDECP", + "ZUQINCP", + "ZUQRSHL", + "ZUQRSHLR", + "ZUQRSHRN", + "ZUQRSHRNB", + "ZUQRSHRNT", + "ZUQSHL", + "ZUQSHLR", + "ZUQSHRN", + "ZUQSHRNB", + "ZUQSHRNT", + "ZUQSUB", + "ZUQSUBR", + "ZUQXTNB", + "ZUQXTNT", + "ZURECPE", + "ZURHADD", + "ZURSHL", + "ZURSHLR", + "ZURSHR", + "ZURSQRTE", + "ZURSRA", + "ZUSDOT", + "ZUSHLLB", + "ZUSHLLT", + "ZUSMMLA", + "ZUSQADD", + "ZUSRA", + "ZUSUBLB", + "ZUSUBLT", + "ZUSUBWB", + "ZUSUBWT", + "ZUUNPKHI", + "ZUUNPKLO", + "ZUXTB", + "ZUXTH", + "ZUXTW", + "ZUZP1", + "ZUZP2", + "ZUZPQ1", + "ZUZPQ2", + "ZXAR", + "ZZIP1", + "ZZIP2", + "ZZIPQ1", + "ZZIPQ2", + "LAST", +} + +func init() { + Anames = append(Anames, sveAnames...) +} diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go index befd1bee13d66f..5bd3c4a8f306d9 100644 --- a/src/cmd/internal/obj/arm64/asm7.go +++ b/src/cmd/internal/obj/arm64/asm7.go @@ -36,10 +36,11 @@ import ( "encoding/binary" "errors" "fmt" + "internal/buildcfg" "log" "math" + "math/bits" "slices" - "strings" ) // ctxt7 holds state while assembling a single function. @@ -196,7 +197,7 @@ var atomicCASP = map[obj.As]uint32{ ACASPW: 0<<30 | 0x41<<21 | 0x1f<<10, } -var oprange [ALAST & obj.AMask][]Optab +var oprange [obj.AllowedOpCodes][]Optab var xcmp [C_NCLASS][C_NCLASS]bool @@ -281,6 +282,30 @@ func MOVCONST(d int64, s int, rt int) uint32 { return uint32(((d>>uint(s*16))&0xFFFF)<<5) | uint32(s)&3<<21 | uint32(rt&31) } +func ASIMDALL(u, size, opcode uint32) uint32 { + return u<<29 | 0x7<<25 | size<<22 | 3<<20 | opcode<<12 | 1<<11 +} + +func ASIMDDIFF(u, opcode uint32) uint32 { + return u<<29 | 0x7<<25 | 1<<21 | opcode<<12 +} + +func ASIMDMISC(u, size, opcode uint32) uint32 { + return u<<29 | 0x7<<25 | size<<22 | 1<<21 | opcode<<12 | 1<<11 +} + +func ASIMDPERM(opcode uint32) uint32 { + return 0x7<<25 | opcode<<12 | 1<<11 +} + +func ASIMDSAME(u, size, opcode uint32) uint32 { + return u<<29 | 0x7<<25 | size<<22 | 1<<21 | opcode<<11 | 1<<10 +} + +func ASIMDSHF(u, opcode uint32) uint32 { + return u<<29 | 0xF<<24 | opcode<<11 | 1<<10 +} + const ( // Optab.flag LFROM = 1 << iota // p.From uses constant pool @@ -351,6 +376,13 @@ var optab = []Optab{ {AFCMPS, C_FREG, C_FREG, C_NONE, C_NONE, C_NONE, 56, 4, 0, 0, 0}, {AFCMPS, C_FCON, C_FREG, C_NONE, C_NONE, C_NONE, 56, 4, 0, 0, 0}, {AVADDP, C_ARNG, C_ARNG, C_NONE, C_ARNG, C_NONE, 72, 4, 0, 0, 0}, + {AVCMEQ, C_ARNG, C_ARNG, C_NONE, C_ARNG, C_NONE, 72, 4, 0, 0, 0}, + {AVCMEQ, C_ZCON, C_ARNG, C_NONE, C_ARNG, C_NONE, 109, 4, 0, 0, 0}, + {AVCMLE, C_ZCON, C_ARNG, C_NONE, C_ARNG, C_NONE, 109, 4, 0, 0, 0}, + {AVFCMEQ, C_ARNG, C_ARNG, C_NONE, C_ARNG, C_NONE, 72, 4, 0, 0, 0}, + {AVFCMEQ, C_FCON, C_ARNG, C_NONE, C_ARNG, C_NONE, 109, 4, 0, 0, 0}, + {AVFCMLE, C_FCON, C_ARNG, C_NONE, C_ARNG, C_NONE, 109, 4, 0, 0, 0}, + {AVADD, C_ARNG, C_ARNG, C_NONE, C_ARNG, C_NONE, 72, 4, 0, 0, 0}, {AVADD, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 89, 4, 0, 0, 0}, {AVADD, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 89, 4, 0, 0, 0}, @@ -484,6 +516,8 @@ var optab = []Optab{ {AFMOVS, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 65, 12, 0, 0, 0}, {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 64, 12, 0, 0, 0}, {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 65, 12, 0, 0, 0}, + {AFMOVQ, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 64, 12, 0, 0, 0}, + {AFMOVQ, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 65, 12, 0, 0, 0}, {AFMOVS, C_FCON, C_NONE, C_NONE, C_FREG, C_NONE, 55, 4, 0, 0, 0}, {AFMOVS, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 54, 4, 0, 0, 0}, {AFMOVD, C_FCON, C_NONE, C_NONE, C_FREG, C_NONE, 55, 4, 0, 0, 0}, @@ -509,7 +543,10 @@ var optab = []Optab{ {AVEXT, C_VCON, C_ARNG, C_ARNG, C_ARNG, C_NONE, 94, 4, 0, 0, 0}, {AVTBL, C_ARNG, C_NONE, C_LIST, C_ARNG, C_NONE, 100, 4, 0, 0, 0}, {AVUSHR, C_VCON, C_ARNG, C_NONE, C_ARNG, C_NONE, 95, 4, 0, 0, 0}, + {AVXTN, C_ARNG, C_NONE, C_NONE, C_ARNG, C_NONE, 95, 4, 0, 0, 0}, + {AVSQSHL, C_VCON, C_ARNG, C_NONE, C_ARNG, C_NONE, 95, 4, 0, 0, 0}, {AVZIP1, C_ARNG, C_ARNG, C_NONE, C_ARNG, C_NONE, 72, 4, 0, 0, 0}, + {AVSQSHL, C_ARNG, C_ARNG, C_NONE, C_ARNG, C_NONE, 72, 4, 0, 0, 0}, {AVUSHLL, C_VCON, C_ARNG, C_NONE, C_ARNG, C_NONE, 102, 4, 0, 0, 0}, {AVUXTL, C_ARNG, C_NONE, C_NONE, C_ARNG, C_NONE, 102, 4, 0, 0, 0}, {AVUADDW, C_ARNG, C_ARNG, C_NONE, C_ARNG, C_NONE, 105, 4, 0, 0, 0}, @@ -866,6 +903,8 @@ var optab = []Optab{ {AMSR, C_VCON, C_NONE, C_NONE, C_SPOP, C_NONE, 37, 4, 0, 0, 0}, {APRFM, C_UOREG32K, C_NONE, C_NONE, C_SPOP, C_NONE, 91, 4, 0, 0, 0}, {APRFM, C_UOREG32K, C_NONE, C_NONE, C_LCON, C_NONE, 91, 4, 0, 0, 0}, + {ARPRFM, C_ZOREG, C_REG, C_NONE, C_SPOP, C_NONE, 110, 4, 0, 0, 0}, + {ARPRFM, C_ZOREG, C_REG, C_NONE, C_LCON, C_NONE, 110, 4, 0, 0, 0}, {ADMB, C_VCON, C_NONE, C_NONE, C_NONE, C_NONE, 51, 4, 0, 0, 0}, {AHINT, C_VCON, C_NONE, C_NONE, C_NONE, C_NONE, 52, 4, 0, 0, 0}, {ASYS, C_VCON, C_NONE, C_NONE, C_NONE, C_NONE, 50, 4, 0, 0, 0}, @@ -875,6 +914,7 @@ var optab = []Optab{ {ATLBI, C_SPOP, C_NONE, C_NONE, C_ZREG, C_NONE, 107, 4, 0, 0, 0}, {ABTI, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 108, 4, 0, 0, 0}, {ABTI, C_SPOP, C_NONE, C_NONE, C_NONE, C_NONE, 108, 4, 0, 0, 0}, + {ASB, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 10, 4, 0, 0, 0}, /* encryption instructions */ {AAESD, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 26, 4, 0, 0, 0}, // for compatibility with old code @@ -907,6 +947,13 @@ var pstatefield = []struct { {SPOP_DAIFClr, 3<<16 | 4<<12 | 7<<5}, } +var rprfopfield = map[SpecialOperand]uint32{ + SPOP_PLDKEEP: 0, + SPOP_PSTKEEP: 1, + SPOP_PLDSTRM: 4, + SPOP_PSTSTRM: 5, +} + var prfopfield = map[SpecialOperand]uint32{ SPOP_PLDL1KEEP: 0, SPOP_PLDL1STRM: 1, @@ -1060,7 +1107,7 @@ const OP_NOOP = 0xd503201f func (o *Optab) size(ctxt *obj.Link, p *obj.Prog) int { // Optimize adrp+add+ld/st to adrp+ld/st(offset). sz := movesize(p.As) - if sz != -1 { + if 0 <= sz && sz <= 3 { // Relocations R_AARCH64_LDST{64,32,16,8}_ABS_LO12_NC can only generate 8-byte, 4-byte, // 2-byte and 1-byte aligned addresses, so the address of load/store must be aligned. // Also symbols with prefix of "go:string." are Go strings, which will go into @@ -1070,42 +1117,26 @@ func (o *Optab) size(ctxt *obj.Link, p *obj.Prog) int { // to decide whether to use the unaligned/aligned forms, so o.size's result is always // in sync with the code generation decisions, because it *is* the code generation decision. align := int64(1 << sz) - if o.a1 == C_ADDR && p.From.Offset%align == 0 && symAlign(p.From.Sym) >= align || - o.a4 == C_ADDR && p.To.Offset%align == 0 && symAlign(p.To.Sym) >= align { - return 8 + ok := func(a *obj.Addr) bool { + if a.Offset%align != 0 { + return false + } + s := a.Sym + if s.Align != 0 { + return int64(s.Align) >= align + } + // When Align==0, the linker chooses a big enough alignment that this will + // always be ok. (It chooses the biggest alignment that fits in the object + // size. See cmd/link/internal/ld/data.go:symalign. That alignment will + // always be at least as big as this operation is, because this operation + // must fit in the object.) See issue 78585. + return true } - } - return int(o.size_) -} - -// symAlign returns the expected symbol alignment of the symbol s. -// This must match the linker's own default alignment decisions. -func symAlign(s *obj.LSym) int64 { - name := s.Name - switch { - case strings.HasPrefix(name, "go:string."), - strings.HasPrefix(name, "type:.namedata."), - strings.HasPrefix(name, "type:.importpath."), - strings.HasSuffix(name, ".opendefer"), - strings.HasSuffix(name, ".arginfo0"), - strings.HasSuffix(name, ".arginfo1"), - strings.HasSuffix(name, ".argliveinfo"): - // These are just bytes, or varints. - return 1 - case strings.HasPrefix(name, "gclocals·"): - // It has 32-bit fields. - return 4 - default: - switch { - case s.Size%8 == 0: + if o.a1 == C_ADDR && ok(&p.From) || o.a4 == C_ADDR && ok(&p.To) { return 8 - case s.Size%4 == 0: - return 4 - case s.Size%2 == 0: - return 2 } } - return 1 + return int(o.size_) } func span7(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { @@ -1419,10 +1450,8 @@ func roundUp(x, to uint32) uint32 { return (x + to - 1) &^ (to - 1) } -// splitImm24uScaled splits an immediate into a scaled 12 bit unsigned lo value -// and an unscaled shifted 12 bit unsigned hi value. These are typically used -// by adding or subtracting the hi value and using the lo value as the offset -// for a load or store. +// splitImm24uScaled returns hi, lo such that v == hi + lo< 0xfff000+0xfff<> shift + if lo <= 0xfff { + return hi, lo, nil + } } + + // Try hi shifted left by 12 bits. lo := (v >> shift) & 0xfff - hi := v - (lo << shift) + hi = v - (lo << shift) if hi > 0xfff000 { hi = 0xfff000 lo = (v - hi) >> shift } - if hi & ^0xfff000 != 0 { - panic(fmt.Sprintf("bad split for %x with shift %v (%x, %x)", v, shift, hi, lo)) + if hi&^0xfff000 == 0 && hi+lo<= 1<<32 { - x >>= 32 - n += 32 - } - if x >= 1<<16 { - x >>= 16 - n += 16 - } - if x >= 1<<8 { - x >>= 8 - n += 8 - } - if x >= 1<<4 { - x >>= 4 - n += 4 - } - if x >= 1<<2 { - x >>= 2 - n += 2 - } - if x >= 1<<1 { - x >>= 1 - n += 1 - } - return n + return uint32(bits.Len64(x) - 1) } func autoclass(l int64) int { @@ -1876,7 +1889,7 @@ func rclass(r int16) int { return C_RSP case r >= REG_ARNG && r < REG_ELEM: return C_ARNG - case r >= REG_ELEM && r < REG_ELEM_END: + case r >= REG_ELEM && r < REG_ZARNG: return C_ELEM case r >= REG_UXTB && r < REG_SPECIAL, r >= REG_LSL && r < REG_ARNG: @@ -1976,7 +1989,18 @@ func (c *ctxt7) con64class(a *obj.Addr) int { return C_MOVCON } else if zeroCount == 2 || negCount == 2 { return C_MOVCON2 - } else if zeroCount == 1 || negCount == 1 { + } + // See omovlconst for description of this loop. + for i := 0; i < 4; i++ { + mask := uint64(0xffff) << (i * 16) + for period := 2; period <= 32; period *= 2 { + x := uint64(a.Offset)&^mask | bits.RotateLeft64(uint64(a.Offset), max(period, 16))&mask + if isbitcon(x) { + return C_MOVCON2 + } + } + } + if zeroCount == 1 || negCount == 1 { return C_MOVCON3 } else { return C_VCON @@ -2010,28 +2034,28 @@ func (c *ctxt7) loadStoreClass(p *obj.Prog, lsc int, v int64) int { if cmp(C_UAUTO8K, lsc) || cmp(C_UOREG8K, lsc) { return lsc } - if v >= 0 && v <= 0xfff000+0xfff<<1 && v&1 == 0 { + if v >= 0 && v <= 0xfff000+0xfff<<1 && (v&1 == 0 || v <= 0xfff+0xfff<<1) { needsPool = false } case AMOVW, AMOVWU, AFMOVS: if cmp(C_UAUTO16K, lsc) || cmp(C_UOREG16K, lsc) { return lsc } - if v >= 0 && v <= 0xfff000+0xfff<<2 && v&3 == 0 { + if v >= 0 && v <= 0xfff000+0xfff<<2 && (v&3 == 0 || v <= 0xfff+0xfff<<2) { needsPool = false } case AMOVD, AFMOVD: if cmp(C_UAUTO32K, lsc) || cmp(C_UOREG32K, lsc) { return lsc } - if v >= 0 && v <= 0xfff000+0xfff<<3 && v&7 == 0 { + if v >= 0 && v <= 0xfff000+0xfff<<3 && (v&7 == 0 || v <= 0xfff+0xfff<<3) { needsPool = false } case AFMOVQ: if cmp(C_UAUTO64K, lsc) || cmp(C_UOREG64K, lsc) { return lsc } - if v >= 0 && v <= 0xfff000+0xfff<<4 && v&15 == 0 { + if v >= 0 && v <= 0xfff000+0xfff<<4 && (v&15 == 0 || v <= 0xfff+0xfff<<4) { needsPool = false } } @@ -2217,7 +2241,23 @@ func (c *ctxt7) aclass(a *obj.Addr) int { return C_GOK } +// SVE instructions, type 127 is reserved for SVE instructions. +// All SVE instructions are sized 4 bytes. +var sveOptab = Optab{0, C_GOK, C_GOK, C_GOK, C_GOK, C_GOK, 127, 4, 0, 0, 0} + +func isSVE(as obj.As) bool { + // A64 opcodes are prefixed with AZ or AP for SVE/SVE2 + // In goops_gen.go they are defined starting from ASVESTART + 1. + return as > ASVESTART +} + func (c *ctxt7) oplook(p *obj.Prog) *Optab { + if buildcfg.Experiment.SIMD && isSVE(p.As) { + // All SVE instructions are in the Insts table. + // Matching happens in asmout. + return &sveOptab + } + a1 := int(p.Optab) if a1 != 0 { return &optab[a1-1] @@ -3198,18 +3238,54 @@ func buildop(ctxt *obj.Link) { case AVADDP: oprangeset(AVAND, t) - oprangeset(AVCMEQ, t) oprangeset(AVORR, t) oprangeset(AVEOR, t) + oprangeset(AVBIC, t) + oprangeset(AVORN, t) oprangeset(AVBSL, t) oprangeset(AVBIT, t) oprangeset(AVCMTST, t) + oprangeset(AVCMHI, t) + oprangeset(AVSQADD, t) + oprangeset(AVUQADD, t) + oprangeset(AVSQSUB, t) + oprangeset(AVUQSUB, t) + oprangeset(AVMUL, t) + oprangeset(AVMLA, t) + oprangeset(AVMLS, t) + oprangeset(AVSHADD, t) + oprangeset(AVSRHADD, t) + oprangeset(AVSSHL, t) + oprangeset(AVUSHL, t) + oprangeset(AVUHADD, t) + oprangeset(AVURHADD, t) + oprangeset(AVCMHS, t) oprangeset(AVUMAX, t) oprangeset(AVUMIN, t) + oprangeset(AVSMAX, t) + oprangeset(AVSMIN, t) + oprangeset(AVSMAXP, t) + oprangeset(AVSMINP, t) + oprangeset(AVUMAXP, t) + oprangeset(AVUMINP, t) oprangeset(AVUZP1, t) oprangeset(AVUZP2, t) oprangeset(AVBIF, t) + case AVCMEQ: + oprangeset(AVCMGE, t) + oprangeset(AVCMGT, t) + + case AVCMLE: + oprangeset(AVCMLT, t) + + case AVFCMEQ: + oprangeset(AVFCMGE, t) + oprangeset(AVFCMGT, t) + + case AVFCMLE: + oprangeset(AVFCMLT, t) + case AVADD: oprangeset(AVSUB, t) oprangeset(AVRAX1, t) @@ -3237,24 +3313,93 @@ func buildop(ctxt *obj.Link) { case AVADDV: oprangeset(AVUADDLV, t) + oprangeset(AVFMAXV, t) + oprangeset(AVFMAXNMV, t) + oprangeset(AVFMINV, t) + oprangeset(AVFMINNMV, t) + oprangeset(AVSMAXV, t) + oprangeset(AVSMINV, t) + oprangeset(AVUMAXV, t) + oprangeset(AVUMINV, t) case AVFMLA: oprangeset(AVFMLS, t) + oprangeset(AVFADD, t) + oprangeset(AVFSUB, t) + oprangeset(AVFMUL, t) + oprangeset(AVFDIV, t) + oprangeset(AVFMAX, t) + oprangeset(AVFMAXNM, t) + oprangeset(AVFMAXP, t) + oprangeset(AVFADDP, t) + oprangeset(AVFMIN, t) + oprangeset(AVFMINNM, t) + oprangeset(AVFMINP, t) + oprangeset(AVFMAXNMP, t) + oprangeset(AVFMINNMP, t) case AVPMULL: oprangeset(AVPMULL2, t) + oprangeset(AVSMLAL, t) + oprangeset(AVSMLAL2, t) + oprangeset(AVSMLSL, t) + oprangeset(AVSMLSL2, t) + oprangeset(AVSMULL, t) + oprangeset(AVSMULL2, t) + oprangeset(AVUMLAL, t) + oprangeset(AVUMLAL2, t) + oprangeset(AVUMLSL, t) + oprangeset(AVUMLSL2, t) + oprangeset(AVUMULL, t) + oprangeset(AVUMULL2, t) case AVUSHR: oprangeset(AVSHL, t) oprangeset(AVSRI, t) oprangeset(AVSLI, t) oprangeset(AVUSRA, t) + oprangeset(AVSSHR, t) + oprangeset(AVSRSHR, t) + oprangeset(AVSHRN, t) + oprangeset(AVSHRN2, t) + + case AVXTN: + oprangeset(AVXTN2, t) + oprangeset(AVSQXTN, t) + oprangeset(AVSQXTN2, t) + oprangeset(AVSQXTUN, t) + oprangeset(AVSQXTUN2, t) + oprangeset(AVUQXTN, t) + oprangeset(AVUQXTN2, t) + oprangeset(AVFCVTN, t) + oprangeset(AVFCVTN2, t) + + case AVSQSHL: + oprangeset(AVUQSHL, t) case AVREV32: oprangeset(AVCNT, t) + oprangeset(AVCLS, t) + oprangeset(AVCLZ, t) oprangeset(AVRBIT, t) oprangeset(AVREV64, t) oprangeset(AVREV16, t) + oprangeset(AVABS, t) + oprangeset(AVNEG, t) + oprangeset(AVFABS, t) + oprangeset(AVFNEG, t) + oprangeset(AVFSQRT, t) + oprangeset(AVFRINTN, t) + oprangeset(AVFRINTP, t) + oprangeset(AVFRINTM, t) + oprangeset(AVFRINTZ, t) + oprangeset(AVSQABS, t) + oprangeset(AVSQNEG, t) + oprangeset(AVNOT, t) + oprangeset(AVFCVTZS, t) + oprangeset(AVFCVTZU, t) + oprangeset(AVSCVTF, t) + oprangeset(AVUCVTF, t) case AVZIP1: oprangeset(AVZIP2, t) @@ -3263,9 +3408,15 @@ func buildop(ctxt *obj.Link) { case AVUXTL: oprangeset(AVUXTL2, t) + oprangeset(AVSXTL, t) + oprangeset(AVSXTL2, t) + oprangeset(AVFCVTL, t) + oprangeset(AVFCVTL2, t) case AVUSHLL: oprangeset(AVUSHLL2, t) + oprangeset(AVSSHLL, t) + oprangeset(AVSSHLL2, t) case AVLD1R: oprangeset(AVLD2, t) @@ -3284,6 +3435,9 @@ func buildop(ctxt *obj.Link) { case AVTBL: oprangeset(AVTBX, t) + case ASB: + break + case AVCNT, AVMOV, AVLD1, @@ -3294,6 +3448,7 @@ func buildop(ctxt *obj.Link) { AVDUP, AVMOVI, APRFM, + ARPRFM, AVEXT, AVXAR: break @@ -4740,27 +4895,27 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { } switch p.As { - case AVORR, AVAND, AVEOR, AVBIT, AVBSL, AVBIF: + case AVORR, AVAND, AVEOR, AVBIT, AVBSL, AVBIF, AVBIC, AVORN: if af != ARNG_16B && af != ARNG_8B { c.ctxt.Diag("invalid arrangement: %v", p) } - case AVFMLA, AVFMLS: + case AVFMLA, AVFMLS, AVFCMEQ, AVFCMGE, AVFCMGT, AVFADD, AVFSUB, AVFMUL, AVFDIV, AVFMAX, AVFMAXNM, AVFMAXP, AVFADDP, AVFMIN, AVFMINNM, AVFMINP, AVFMAXNMP, AVFMINNMP: if af != ARNG_2D && af != ARNG_2S && af != ARNG_4S { c.ctxt.Diag("invalid arrangement: %v", p) } - case AVUMAX, AVUMIN: + case AVUMAX, AVUMIN, AVUMAXP, AVUMINP, AVMUL, AVMLA, AVMLS, AVSMAX, AVSMIN, AVSMAXP, AVSMINP: if af == ARNG_2D { c.ctxt.Diag("invalid arrangement: %v", p) } } switch p.As { - case AVAND, AVEOR: + case AVAND, AVEOR, AVBIC, AVORN: size = 0 case AVBSL: size = 1 case AVORR, AVBIT, AVBIF: size = 2 - case AVFMLA, AVFMLS: + case AVFMLA, AVFMLS, AVFCMEQ, AVFCMGE, AVFCMGT, AVFADD, AVFSUB, AVFMUL, AVFDIV, AVFMAX, AVFMAXNM, AVFMAXP, AVFADDP, AVFMIN, AVFMINNM, AVFMINP, AVFMAXNMP, AVFMINNMP: if af == ARNG_2D { size = 1 } else { @@ -5060,7 +5215,7 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { } } o1 |= uint32(p.To.Offset) - // cmd/asm/internal/arch/arm64.go:ARM64RegisterListOffset + // RegisterListOffset // add opcode(bit 12-15) for vld1, mask it off if it's not vld1 o1 = c.maskOpvldvst(p, o1) @@ -5124,6 +5279,9 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { case ARNG_4S: Q = 1 size = 2 + case ARNG_2D: + Q = 1 + size = 3 default: c.ctxt.Diag("invalid arrangement: %v\n", p) } @@ -5140,6 +5298,31 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { c.ctxt.Diag("invalid arrangement: %v", p) } + if p.As == AVNOT && (af != ARNG_8B && af != ARNG_16B) { + c.ctxt.Diag("invalid arrangement: %v", p) + } + + // VCLS and VCLZ only support integer arrangements (B, H, S), not D arrangements + if (p.As == AVCLS || p.As == AVCLZ) && (af == ARNG_1D || af == ARNG_2D) { + c.ctxt.Diag("invalid arrangement: %v", p) + } + + // Floating-point instructions only allow floating-point arrangements + // and use 1-bit size field: 0 for S arrangements, 1 for D arrangements + if p.As == AVFABS || p.As == AVFNEG || p.As == AVFSQRT || + p.As == AVFRINTN || p.As == AVFRINTP || p.As == AVFRINTM || p.As == AVFRINTZ || + p.As == AVFCVTZS || p.As == AVFCVTZU || p.As == AVSCVTF || p.As == AVUCVTF { + if af != ARNG_2S && af != ARNG_4S && af != ARNG_2D { + c.ctxt.Diag("invalid arrangement: %v", p) + } + // Override size for floating-point instructions: 0 for S, 1 for D + if af == ARNG_2S || af == ARNG_4S { + size = 0 + } else if af == ARNG_2D { + size = 1 + } + } + if p.As == AVRBIT { size = 1 } @@ -5169,7 +5352,7 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { } } o1 |= uint32(p.From.Offset) - // cmd/asm/internal/arch/arm64.go:ARM64RegisterListOffset + // RegisterListOffset // add opcode(bit 12-15) for vst1, mask it off if it's not vst1 o1 = c.maskOpvldvst(p, o1) o1 |= uint32(r&31) << 5 @@ -5197,6 +5380,14 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { default: c.ctxt.Diag("invalid arrangement: %v\n", p) } + switch p.As { + // Floating-point reduction instructions only support .S4 arrangement and don't have a size field. + case AVFMAXV, AVFMINV, AVFMAXNMV, AVFMINNMV: + if af != ARNG_4S { + c.ctxt.Diag("invalid arrangement: %v\n", p) + } + size = 0 + } o1 = c.oprrr(p, p.As, p.To.Reg, p.From.Reg, obj.REG_NONE) o1 |= uint32(Q&1)<<30 | uint32(size&3)<<22 @@ -5336,7 +5527,7 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { } o1 |= (uint32(imm5&0x1f) << 16) | (uint32(imm4&0xf) << 11) | (uint32(rf&31) << 5) | uint32(rt&31) - case 93: /* vpmull{2} Vm., Vn., Vd. */ + case 93: /* vpmull{2}/v(s|u)(mla|mls|mul)l{2} Vm., Vn., Vd. */ af := uint8((p.From.Reg >> 5) & 15) at := uint8((p.To.Reg >> 5) & 15) a := uint8((p.Reg >> 5) & 15) @@ -5345,18 +5536,31 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { } var Q, size uint32 - if p.As == AVPMULL2 { + switch p.As { + case AVPMULL2, AVSMLAL2, AVSMLSL2, AVSMULL2, AVUMLAL2, AVUMLSL2, AVUMULL2: Q = 1 } switch pack(Q, at, af) { case pack(0, ARNG_8H, ARNG_8B), pack(1, ARNG_8H, ARNG_16B): size = 0 + case pack(0, ARNG_4S, ARNG_4H), pack(1, ARNG_4S, ARNG_8H): + size = 1 + case pack(0, ARNG_2D, ARNG_2S), pack(1, ARNG_2D, ARNG_4S): + size = 2 case pack(0, ARNG_1Q, ARNG_1D), pack(1, ARNG_1Q, ARNG_2D): size = 3 default: c.ctxt.Diag("operand mismatch: %v\n", p) } + if p.As == AVPMULL || p.As == AVPMULL2 { + if size != 0 && size != 3 { + c.ctxt.Diag("invalid arrangement: %v", p) + } + } else if size == 3 { + c.ctxt.Diag("invalid arrangement: %v", p) + } + o1 = c.oprrr(p, p.As, p.To.Reg, p.Reg, p.From.Reg) o1 |= (Q&1)<<30 | (size&3)<<22 @@ -5395,19 +5599,38 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { o1 |= ((Q & 1) << 30) | (uint32(r&31) << 16) | (uint32(index&15) << 11) | (uint32(rf&31) << 5) | uint32(rt&31) - case 95: /* vushr/vshl/vsri/vsli/vusra $shift, Vn., Vd. */ + case 95: /* shift: vushr/vshl/vsri/vsli/vusra/vsshr/vsrshr $shift, Vn., Vd.; narrowing shift: vshrn[2] $shift, Vn., Vd.; trunc: vxtn/v{s,u}qxt{n,un}/vfcvtn[2] Vn., Vd. */ at := int((p.To.Reg >> 5) & 15) - af := int((p.Reg >> 5) & 15) - shift := int(p.From.Offset) + rt := int((p.To.Reg) & 31) + var af, rf, shift int + + // Truncation instructions (narrow without immediate). + trunc := p.As == AVXTN || p.As == AVXTN2 || + p.As == AVSQXTN || p.As == AVSQXTN2 || + p.As == AVSQXTUN || p.As == AVSQXTUN2 || + p.As == AVUQXTN || p.As == AVUQXTN2 || + p.As == AVFCVTN || p.As == AVFCVTN2 + + if trunc { + af = int((p.From.Reg >> 5) & 15) + rf = int(p.From.Reg & 31) + shift = 0 + } else { + af = int((p.Reg >> 5) & 15) + rf = int((p.Reg) & 31) + shift = int(p.From.Offset) + } - if af != at { + narrow := trunc || p.As == AVSHRN || p.As == AVSHRN2 + if af != at && !narrow { c.ctxt.Diag("invalid arrangement on op Vn., Vd.: %v", p) + at = af } var Q uint32 var imax, esize int - switch af { + switch at { case ARNG_8B, ARNG_4H, ARNG_2S: Q = 0 case ARNG_16B, ARNG_8H, ARNG_4S, ARNG_2D: @@ -5416,42 +5639,62 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { c.ctxt.Diag("invalid arrangement on op Vn., Vd.: %v", p) } - switch af { + atwice := -1 + switch at { case ARNG_8B, ARNG_16B: imax = 15 esize = 8 + atwice = ARNG_8H case ARNG_4H, ARNG_8H: imax = 31 esize = 16 + atwice = ARNG_4S case ARNG_2S, ARNG_4S: imax = 63 esize = 32 + atwice = ARNG_2D case ARNG_2D: imax = 127 esize = 64 } - imm := 0 + if narrow { + wantQ := uint32(0) + if p.As == AVXTN2 || p.As == AVSQXTN2 || p.As == AVSQXTUN2 || + p.As == AVUQXTN2 || p.As == AVFCVTN2 || p.As == AVSHRN2 { + wantQ = 1 + } + if Q != wantQ || atwice != af { + c.ctxt.Diag("invalid arrangement on op: %v", p) + } + } + + o1 = c.opirr(p, p.As) + + if trunc && p.As != AVFCVTN && p.As != AVFCVTN2 { + // Integer trunc ops encode size from destination element width. + // FCVTN has size already in opirr base. + size := uint32(esize >> 4) + o1 |= (size << 22) + } + + // Shift instructions: encode immediate from shift amount. switch p.As { - case AVUSHR, AVSRI, AVUSRA: - imm = esize*2 - shift + case AVUSHR, AVSRI, AVUSRA, AVSSHR, AVSRSHR, AVSHRN, AVSHRN2: + imm := esize*2 - shift if imm < esize || imm > imax { c.ctxt.Diag("shift out of range: %v", p) } - case AVSHL, AVSLI: - imm = esize + shift + o1 |= (uint32(imm&0x7f) << 16) + case AVSHL, AVSLI, AVSQSHL, AVUQSHL: + imm := esize + shift if imm > imax { c.ctxt.Diag("shift out of range: %v", p) } - default: - c.ctxt.Diag("invalid instruction %v\n", p) + o1 |= (uint32(imm&0x7f) << 16) } - o1 = c.opirr(p, p.As) - rt := int((p.To.Reg) & 31) - rf := int((p.Reg) & 31) - - o1 |= ((Q & 1) << 30) | (uint32(imm&0x7f) << 16) | (uint32(rf&31) << 5) | uint32(rt&31) + o1 |= ((Q & 1) << 30) | (uint32(rf&31) << 5) | uint32(rt&31) case 96: /* vst1 Vt1.[index], offset(Rn) */ af := int((p.From.Reg >> 5) & 15) @@ -5668,19 +5911,30 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { o1 = q<<30 | 0xe<<24 | len<<13 | op<<12 o1 |= (uint32(rf&31) << 16) | uint32(offset&31)<<5 | uint32(rt&31) - case 102: /* vushll, vushll2, vuxtl, vuxtl2 */ + case 102: /* long shift: v{s,u}shll[2] $shift, Vn., Vd.; long: v{s,u}xtl[2], vfcvtl[2] Vn., Vd. */ o1 = c.opirr(p, p.As) rf := p.Reg af := uint8((p.Reg >> 5) & 15) at := uint8((p.To.Reg >> 5) & 15) shift := int(p.From.Offset) - if p.As == AVUXTL || p.As == AVUXTL2 { + if p.As == AVUXTL || p.As == AVUXTL2 || p.As == AVSXTL || p.As == AVSXTL2 || p.As == AVFCVTL || p.As == AVFCVTL2 { rf = p.From.Reg af = uint8((p.From.Reg >> 5) & 15) shift = 0 } + var Q uint32 + if p.As == AVUXTL2 || p.As == AVSXTL2 || p.As == AVUSHLL2 || p.As == AVSSHLL2 || p.As == AVFCVTL2 { + Q = 1 + } + + if p.As == AVFCVTL || p.As == AVFCVTL2 { + if af != ARNG_2S && af != ARNG_4S || at != ARNG_2D { + c.ctxt.Diag("operand mismatch: %v\n", p) + } + o1 |= Q<<30 | uint32(rf&31)<<5 | uint32(p.To.Reg&31) + break + } - Q := (o1 >> 30) & 1 var immh, width uint8 switch pack(Q, af, at) { case pack(0, ARNG_8B, ARNG_8H): @@ -5701,7 +5955,7 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { if !(0 <= shift && shift <= int(width-1)) { c.ctxt.Diag("shift amount out of range: %v\n", p) } - o1 |= uint32(immh)<<19 | uint32(shift)<<16 | uint32(rf&31)<<5 | uint32(p.To.Reg&31) + o1 |= Q<<30 | uint32(immh)<<19 | uint32(shift)<<16 | uint32(rf&31)<<5 | uint32(p.To.Reg&31) case 103: /* VEOR3/VBCAX Va.B16, Vm.B16, Vn.B16, Vd.B16 */ ta := (p.From.Reg >> 5) & 15 @@ -5839,6 +6093,119 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) { c.ctxt.Diag("illegal argument: %v\n", p) break } + + case 109: /* [cm|fcm][eq|ge|gt|le|lt] $0, Vn., Vd. */ + // Encoding is same as case 83 (this is a separate case because $0 occupies p.From) + if !(p.From.Type == obj.TYPE_CONST && p.From.Offset == 0) && + !(p.From.Type == obj.TYPE_FCONST && p.From.Val.(float64) == 0.0) { + c.ctxt.Diag("expected a constant zero immediate operand: %v\n", p) + } + an := int((p.Reg >> 5) & 15) + ad := int((p.To.Reg >> 5) & 15) + if an != ad { + c.ctxt.Diag("operand mismatch: %v", p) + break + } + var Q, size uint32 + if p.From.Type == obj.TYPE_FCONST { + switch an { + case ARNG_2D: + Q = 1 + size = 1 + case ARNG_2S: + Q = 0 + size = 0 + case ARNG_4S: + Q = 1 + size = 0 + default: + c.ctxt.Diag("invalid arrangement: %v", p) + } + } else { + switch an { + case ARNG_16B: + Q = 1 + size = 0 + case ARNG_2D: + Q = 1 + size = 3 + case ARNG_2S: + Q = 0 + size = 2 + case ARNG_4H: + Q = 0 + size = 1 + case ARNG_4S: + Q = 1 + size = 2 + case ARNG_8B: + Q = 0 + size = 0 + case ARNG_8H: + Q = 1 + size = 1 + default: + c.ctxt.Diag("invalid arrangement: %v", p) + } + } + o1 = c.opirr(p, p.As) + rd := uint32(p.To.Reg & 31) + rn := uint32(p.Reg & 31) + o1 |= Q<<30 | size<<22 | (rn << 5) | (rd) + + case 110: /*rprfm (Rn), Rm, */ + rn := p.From.Reg + rm := p.Reg + var operation uint32 + var ok bool + + // Operation is either a 6-bit immediate or named prefetch operation. + if p.To.Type == obj.TYPE_CONST { + operation = uint32(p.To.Offset) + if operation > 63 { + c.ctxt.Diag("range prefetch immediate must be 0 to 63: %v", p) + } + } else { + operation, ok = rprfopfield[SpecialOperand(p.To.Offset)] + if !ok { + c.ctxt.Diag("illegal range prefetch operand, expected PLDKEEP, PSTKEEP, PLDSTRM or PSTSTRM: %v", p) + } + } + + // 6-bit placement: the 6-bit value is scattered to match the + // architectural encoding (bits 15,13,12,2-0). This is because the + // instructions word reuses fields from the base load/store hint space. + // option2 (bit5) -> bit15 + // option0 (bit4) -> bit13 + // S (bit3) -> bit12 + // Rt<2:0> (bits2-0) -> bits2-0 + // Rt<4:3> are already set by c.opirr() and are fixed for RPRFM. + option2 := (operation & (1 << 5)) << 10 + option0 := (operation & (1 << 4)) << 9 + s := (operation & (1 << 3)) << 9 + rt := (operation & 0x7) + + encodedOperation := option2 | option0 | s | rt + + o1 = c.opirr(p, p.As) + o1 |= (uint32(rm&31) << 16) | (uint32(rn&31) << 5) | uint32(encodedOperation) + + case 127: + // Generic SVE instruction encoding + matched := false + groupIdx := int(p.As - ASVESTART - 1) + if groupIdx >= 0 && groupIdx < len(insts) { + for _, inst := range insts[groupIdx] { + if bin, ok := inst.tryEncode(p); ok { + o1 = bin + matched = true + break + } + } + } + if !matched { + c.ctxt.Diag("illegal combination from SVE: %v", p) + } } out[0] = o1 out[1] = o2 @@ -6423,73 +6790,280 @@ func (c *ctxt7) oprrr(p *obj.Prog, a obj.As, rd, rn, rm int16) uint32 { op = FPOP1S(0, 0, 3, 5) case AVADD: - op = 7<<25 | 1<<21 | 1<<15 | 1<<10 + op = ASIMDSAME(0, 0, 0x10) case AVSUB: - op = 0x17<<25 | 1<<21 | 1<<15 | 1<<10 + op = ASIMDSAME(1, 0, 0x10) + + case AVSHADD: + op = ASIMDSAME(0, 0, 0x0) + + case AVSRHADD: + op = ASIMDSAME(0, 0, 0x2) + + case AVSSHL: + op = ASIMDSAME(0, 0, 0x8) + + case AVUSHL: + op = ASIMDSAME(1, 0, 0x8) + + case AVUHADD: + op = ASIMDSAME(1, 0, 0x0) + + case AVURHADD: + op = ASIMDSAME(1, 0, 0x2) case AVADDP: - op = 7<<25 | 1<<21 | 1<<15 | 15<<10 + op = ASIMDSAME(0, 0, 0x17) + + case AVSQADD: + op = ASIMDSAME(0, 0, 0x1) + + case AVUQADD: + op = ASIMDSAME(1, 0, 0x1) + + case AVSQSHL: + op = ASIMDSAME(0, 0, 0x9) + + case AVUQSHL: + op = ASIMDSAME(1, 0, 0x9) + + case AVSQSUB: + op = ASIMDSAME(0, 0, 0x5) + + case AVUQSUB: + op = ASIMDSAME(1, 0, 0x5) + + case AVMUL: + op = ASIMDSAME(0, 0, 0x13) + + case AVMLA: + op = ASIMDSAME(0, 0, 0x12) + + case AVMLS: + op = ASIMDSAME(1, 0, 0x12) case AVAND: - op = 7<<25 | 1<<21 | 7<<10 + op = ASIMDSAME(0, 0, 0x03) + + case AVBIC: + op = ASIMDSAME(0, 1, 0x03) case AVBCAX: op = 0xCE<<24 | 1<<21 case AVCMEQ: - op = 1<<29 | 0x71<<21 | 0x23<<10 + op = ASIMDSAME(1, 0, 0x11) + + case AVCMGE: + op = ASIMDSAME(0, 0, 0x07) + + case AVCMGT: + op = ASIMDSAME(0, 0, 0x06) + + case AVCMHI: + op = ASIMDSAME(1, 0, 0x06) + + case AVCMHS: + op = ASIMDSAME(1, 0, 0x07) + + case AVFCMEQ: + op = ASIMDSAME(0, 0, 0x1C) + + case AVFCMGE: + op = ASIMDSAME(1, 0, 0x1C) + + case AVFCMGT: + op = ASIMDSAME(1, 2, 0x1C) case AVCNT: - op = 0xE<<24 | 0x10<<17 | 5<<12 | 2<<10 + op = ASIMDMISC(0, 0, 0x05) + + case AVCLS: + op = ASIMDMISC(0, 0, 0x04) + + case AVCLZ: + op = ASIMDMISC(1, 0, 0x04) case AVZIP1: - op = 0xE<<24 | 3<<12 | 2<<10 + op = ASIMDPERM(0x3) case AVZIP2: - op = 0xE<<24 | 1<<14 | 3<<12 | 2<<10 + op = ASIMDPERM(0x7) case AVEOR: - op = 1<<29 | 0x71<<21 | 7<<10 + op = ASIMDSAME(1, 0, 0x03) case AVEOR3: op = 0xCE << 24 case AVORR: - op = 7<<25 | 5<<21 | 7<<10 + op = ASIMDSAME(0, 2, 0x03) - case AVREV16: - op = 3<<26 | 2<<24 | 1<<21 | 3<<11 + case AVORN: + op = ASIMDSAME(0, 3, 0x03) case AVRAX1: op = 0xCE<<24 | 3<<21 | 1<<15 | 3<<10 + case AVREV16: + op = ASIMDMISC(0, 0, 0x01) + case AVREV32: - op = 11<<26 | 2<<24 | 1<<21 | 1<<11 + op = ASIMDMISC(1, 0, 0x00) case AVREV64: - op = 3<<26 | 2<<24 | 1<<21 | 1<<11 + op = ASIMDMISC(0, 0, 0x00) + + case AVABS: + op = ASIMDMISC(0, 0, 0xB) + + case AVNEG: + op = ASIMDMISC(1, 0, 0xB) + + case AVFABS: + op = ASIMDMISC(0, 2, 0xF) + + case AVFNEG: + op = ASIMDMISC(1, 2, 0xF) + + case AVFSQRT: + op = ASIMDMISC(1, 2, 0x1F) + + case AVFRINTN: + op = ASIMDMISC(0, 0, 0x18) + + case AVFRINTP: + op = ASIMDMISC(0, 2, 0x18) + + case AVFRINTM: + op = ASIMDMISC(0, 0, 0x19) + + case AVFRINTZ: + op = ASIMDMISC(0, 2, 0x19) + + case AVFCVTZS: + op = ASIMDMISC(0, 2, 0x1B) + + case AVFCVTZU: + op = ASIMDMISC(1, 2, 0x1B) + + case AVSCVTF: + op = ASIMDMISC(0, 0, 0x1D) + + case AVUCVTF: + op = ASIMDMISC(1, 0, 0x1D) + + case AVSQABS: + op = ASIMDMISC(0, 0, 0x7) + + case AVSQNEG: + op = ASIMDMISC(1, 0, 0x7) + + case AVNOT: + op = ASIMDMISC(1, 0, 0x5) case AVMOV: op = 7<<25 | 5<<21 | 7<<10 case AVADDV: - op = 7<<25 | 3<<20 | 3<<15 | 7<<11 + op = ASIMDALL(0, 0, 0x1B) + + case AVFMAXV: + op = ASIMDALL(1, 0, 0xF) + + case AVFMAXNMV: + op = ASIMDALL(1, 0, 0xC) + + case AVFMINV: + op = ASIMDALL(1, 2, 0xF) + + case AVFMINNMV: + op = ASIMDALL(1, 2, 0xC) + + case AVSMAXV: + op = ASIMDALL(0, 0, 0xA) + + case AVSMINV: + op = ASIMDALL(0, 0, 0x1A) + + case AVUMAXV: + op = ASIMDALL(1, 0, 0xA) + + case AVUMINV: + op = ASIMDALL(1, 0, 0x1A) case AVUADDLV: - op = 1<<29 | 7<<25 | 3<<20 | 7<<11 + op = ASIMDALL(1, 0, 0x03) case AVFMLA: - op = 7<<25 | 0<<23 | 1<<21 | 3<<14 | 3<<10 + op = ASIMDSAME(0, 0, 0x19) case AVFMLS: - op = 7<<25 | 1<<23 | 1<<21 | 3<<14 | 3<<10 + op = ASIMDSAME(0, 2, 0x19) + + case AVFADD: + op = ASIMDSAME(0, 0, 0x1A) + + case AVFSUB: + op = ASIMDSAME(0, 2, 0x1A) + + case AVFMUL: + op = ASIMDSAME(1, 0, 0x1B) + + case AVFDIV: + op = ASIMDSAME(1, 0, 0x1F) + + case AVFMAX: + op = ASIMDSAME(0, 0, 0x1E) + + case AVFMAXNM: + op = ASIMDSAME(0, 0, 0x18) + + case AVFMAXP: + op = ASIMDSAME(1, 0, 0x1E) + + case AVFADDP: + op = ASIMDSAME(1, 0, 0x1A) + + case AVFMIN: + op = ASIMDSAME(0, 2, 0x1E) + + case AVFMINNM: + op = ASIMDSAME(0, 2, 0x18) + + case AVFMINP: + op = ASIMDSAME(1, 2, 0x1E) + + case AVFMAXNMP: + op = ASIMDSAME(1, 0, 0x18) + + case AVFMINNMP: + op = ASIMDSAME(1, 2, 0x18) case AVPMULL, AVPMULL2: - op = 0xE<<24 | 1<<21 | 0x38<<10 + op = ASIMDDIFF(0, 0xE) + + case AVSMLAL, AVSMLAL2: + op = ASIMDDIFF(0, 0x8) + + case AVSMLSL, AVSMLSL2: + op = ASIMDDIFF(0, 0xA) + + case AVSMULL, AVSMULL2: + op = ASIMDDIFF(0, 0xC) + + case AVUMLAL, AVUMLAL2: + op = ASIMDDIFF(1, 0x8) + + case AVUMLSL, AVUMLSL2: + op = ASIMDDIFF(1, 0xA) + + case AVUMULL, AVUMULL2: + op = ASIMDDIFF(1, 0xC) case AVRBIT: - op = 0x2E<<24 | 1<<22 | 0x10<<17 | 5<<12 | 2<<10 + op = ASIMDMISC(1, 1, 0x05) case AVLD1, AVLD2, AVLD3, AVLD4: op = 3<<26 | 1<<22 @@ -6501,37 +7075,55 @@ func (c *ctxt7) oprrr(p *obj.Prog, a obj.As, rd, rn, rm int16) uint32 { op = 0xD<<24 | 3<<21 case AVBIF: - op = 1<<29 | 7<<25 | 7<<21 | 7<<10 + op = ASIMDSAME(1, 3, 0x03) case AVBIT: - op = 1<<29 | 0x75<<21 | 7<<10 + op = ASIMDSAME(1, 2, 0x03) case AVBSL: - op = 1<<29 | 0x73<<21 | 7<<10 + op = ASIMDSAME(1, 1, 0x03) case AVCMTST: - op = 0xE<<24 | 1<<21 | 0x23<<10 + op = ASIMDSAME(0, 0, 0x11) case AVUMAX: - op = 1<<29 | 7<<25 | 1<<21 | 0x19<<10 + op = ASIMDSAME(1, 0, 0x0C) case AVUMIN: - op = 1<<29 | 7<<25 | 1<<21 | 0x1b<<10 + op = ASIMDSAME(1, 0, 0x0D) + + case AVUMAXP: + op = ASIMDSAME(1, 0, 0x14) + + case AVUMINP: + op = ASIMDSAME(1, 0, 0x15) + + case AVSMAX: + op = ASIMDSAME(0, 0, 0x0C) + + case AVSMIN: + op = ASIMDSAME(0, 0, 0x0D) + + case AVSMAXP: + op = ASIMDSAME(0, 0, 0x14) + + case AVSMINP: + op = ASIMDSAME(0, 0, 0x15) case AVUZP1: - op = 7<<25 | 3<<11 + op = ASIMDPERM(0x1) case AVUZP2: - op = 7<<25 | 1<<14 | 3<<11 + op = ASIMDPERM(0x5) case AVUADDW, AVUADDW2: - op = 0x17<<25 | 1<<21 | 1<<12 + op = ASIMDDIFF(1, 0x1) case AVTRN1: - op = 7<<25 | 5<<11 + op = ASIMDPERM(0x2) case AVTRN2: - op = 7<<25 | 1<<14 | 5<<11 + op = ASIMDPERM(0x6) default: c.ctxt.Diag("%v: bad rrr %d %v", p, a, a) @@ -6728,35 +7320,101 @@ func (c *ctxt7) opirr(p *obj.Prog, a obj.As) uint32 { case AHINT: return SYSHINT(0) + case AVCMEQ: + return ASIMDMISC(0, 0, 0x09) + + case AVCMGE: + return ASIMDMISC(1, 0, 0x08) + + case AVCMGT: + return ASIMDMISC(0, 0, 0x08) + + case AVCMLE: + return ASIMDMISC(1, 0, 0x09) + + case AVCMLT: + return ASIMDMISC(0, 0, 0x0A) + + case AVFCMEQ: + return ASIMDMISC(0, 2, 0x0D) + + case AVFCMGE: + return ASIMDMISC(1, 2, 0x0C) + + case AVFCMGT: + return ASIMDMISC(0, 2, 0x0C) + + case AVFCMLE: + return ASIMDMISC(1, 2, 0x0D) + + case AVFCMLT: + return ASIMDMISC(0, 2, 0x0E) + case AVEXT: return 0x2E<<24 | 0<<23 | 0<<21 | 0<<15 case AVUSHR: - return 0x5E<<23 | 1<<10 + return ASIMDSHF(1, 0x00) + + case AVSSHR: + return ASIMDSHF(0, 0x00) + + case AVSRSHR: + return ASIMDSHF(0, 0x04) case AVSHL: - return 0x1E<<23 | 21<<10 + return ASIMDSHF(0, 0x0A) + + case AVSQSHL: + return ASIMDSHF(0, 0xE) + + case AVUQSHL: + return ASIMDSHF(1, 0xE) + + case AVSHRN, AVSHRN2: + return ASIMDSHF(0, 0x10) + + case AVXTN, AVXTN2: + return ASIMDMISC(0, 0, 0x12) + + case AVSQXTN, AVSQXTN2: + return ASIMDMISC(0, 0, 0x14) + + case AVSQXTUN, AVSQXTUN2: + return ASIMDMISC(1, 0, 0x12) + + case AVUQXTN, AVUQXTN2: + return ASIMDMISC(1, 0, 0x14) + + case AVFCVTN, AVFCVTN2: + return ASIMDMISC(0, 1, 0x16) + + case AVFCVTL, AVFCVTL2: + return ASIMDMISC(0, 1, 0x17) case AVSRI: - return 0x5E<<23 | 17<<10 + return ASIMDSHF(1, 0x08) case AVSLI: - return 0x5E<<23 | 21<<10 + return ASIMDSHF(1, 0x0A) - case AVUSHLL, AVUXTL: - return 1<<29 | 15<<24 | 0x29<<10 + case AVUSHLL, AVUXTL, AVUSHLL2, AVUXTL2: + return ASIMDSHF(1, 0x14) - case AVUSHLL2, AVUXTL2: - return 3<<29 | 15<<24 | 0x29<<10 + case AVSSHLL, AVSSHLL2, AVSXTL, AVSXTL2: + return ASIMDSHF(0, 0x14) case AVXAR: return 0xCE<<24 | 1<<23 case AVUSRA: - return 1<<29 | 15<<24 | 5<<10 + return ASIMDSHF(1, 0x02) case APRFM: return 0xf9<<24 | 2<<22 + + case ARPRFM: + return 0xf8<<24 | 5<<21 | 18<<10 | 3<<3 } c.ctxt.Diag("%v: bad irr %v", p, a) @@ -6883,6 +7541,9 @@ func (c *ctxt7) opimm(p *obj.Prog, a obj.As) uint32 { case ACLREX: return SYSOP(0, 0, 3, 3, 0, 2, 0x1F) + + case ASB: + return SYSOP(0, 0, 3, 3, 0, 0, 0xFF) } c.ctxt.Diag("%v: bad imm %v", p, a) @@ -7276,6 +7937,8 @@ func (c *ctxt7) opldrr(p *obj.Prog, a obj.As, rt, rn, rm int16, extension bool) op = OptionS<<10 | 0x3<<21 | 0x17<<27 | 1<<26 case AFMOVD: op = OptionS<<10 | 0x3<<21 | 0x1f<<27 | 1<<26 + case AFMOVQ: + op = OptionS<<10 | 0x7<<21 | 0x07<<27 | 1<<26 default: c.ctxt.Diag("bad opldrr %v\n%v", a, p) return 0 @@ -7308,6 +7971,8 @@ func (c *ctxt7) opstrr(p *obj.Prog, a obj.As, rt, rn, rm int16, extension bool) op = OptionS<<10 | 0x1<<21 | 0x17<<27 | 1<<26 case AFMOVD: op = OptionS<<10 | 0x1<<21 | 0x1f<<27 | 1<<26 + case AFMOVQ: + op = OptionS<<10 | 0x5<<21 | 0x07<<27 | 1<<26 default: c.ctxt.Diag("bad opstrr %v\n%v", a, p) return 0 @@ -7551,6 +8216,31 @@ func (c *ctxt7) omovlconst(as obj.As, p *obj.Prog, a *obj.Addr, rt int, os []uin } } return 2 + } + + // Look for a two instruction pair, a bit pattern encodeable + // as a bitcon immediate plus a fixup MOVK instruction. + // Constants like this often occur from strength reduction of divides. + for i = 0; i < 4; i++ { + mask := uint64(0xffff) << (i * 16) + for period := 2; period <= 32; period *= 2 { // TODO: handle period==64 somehow? + // Copy in bits from outside of the masked region + x := uint64(d)&^mask | bits.RotateLeft64(uint64(d), max(period, 16))&mask + if isbitcon(x) { + // ORR $c1, ZR, rt + os[0] = c.opirr(p, AORR) + os[0] |= bitconEncode(x, 64) | uint32(REGZERO&31)<<5 | uint32(rt&31) + // MOVK $c2<<(i*16), rt + os[1] = c.opirr(p, AMOVK) + os[1] |= MOVCONST(d, i, rt) + return 2 + } + } + } + // TODO: other fixups, like ADD or SUB? + // TODO: 3-instruction variant, instead of the full MOVD+3*MOVK version below? + + switch { case zeroCount == 1: // one MOVZ and two MOVKs @@ -7857,8 +8547,8 @@ func pack(q uint32, arngA, arngB uint8) uint32 { return q<<16 | uint32(arngA)<<8 | uint32(arngB) } -// ARM64RegisterExtension constructs an ARM64 register with extension or arrangement. -func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error { +// EncodeRegisterExtension constructs an ARM64 register with extension or arrangement in the argument a. +func EncodeRegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error { Rnum := (reg & 31) + num<<5 if isAmount { if num < 0 || num > 7 { @@ -7920,82 +8610,186 @@ func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, i return errors.New("unsupported general register extension type: " + ext) } - } else if reg <= REG_V31 && reg >= REG_V0 { + } else if REG_Z0 <= reg && reg <= REG_Z31 { + var arng int switch ext { - case "B8": - if isIndex { - return errors.New("invalid register extension") - } - a.Reg = REG_ARNG + (reg & 31) + ((ARNG_8B & 15) << 5) - case "B16": - if isIndex { - return errors.New("invalid register extension") - } - a.Reg = REG_ARNG + (reg & 31) + ((ARNG_16B & 15) << 5) - case "H4": - if isIndex { - return errors.New("invalid register extension") - } - a.Reg = REG_ARNG + (reg & 31) + ((ARNG_4H & 15) << 5) - case "H8": - if isIndex { - return errors.New("invalid register extension") - } - a.Reg = REG_ARNG + (reg & 31) + ((ARNG_8H & 15) << 5) - case "S2": + case "B": if isIndex { - return errors.New("invalid register extension") + a.Reg = REG_ZARNGELEM + (reg & 31) + int16((ARNG_B&15)<<5) + a.Index = num + return nil } - a.Reg = REG_ARNG + (reg & 31) + ((ARNG_2S & 15) << 5) - case "S4": + arng = ARNG_B + case "H": if isIndex { - return errors.New("invalid register extension") + a.Reg = REG_ZARNGELEM + (reg & 31) + int16((ARNG_H&15)<<5) + a.Index = num + return nil } - a.Reg = REG_ARNG + (reg & 31) + ((ARNG_4S & 15) << 5) - case "D1": + arng = ARNG_H + case "S": if isIndex { - return errors.New("invalid register extension") + a.Reg = REG_ZARNGELEM + (reg & 31) + int16((ARNG_S&15)<<5) + a.Index = num + return nil } - a.Reg = REG_ARNG + (reg & 31) + ((ARNG_1D & 15) << 5) - case "D2": + arng = ARNG_S + case "D": if isIndex { - return errors.New("invalid register extension") + a.Reg = REG_ZARNGELEM + (reg & 31) + int16((ARNG_D&15)<<5) + a.Index = num + return nil } - a.Reg = REG_ARNG + (reg & 31) + ((ARNG_2D & 15) << 5) - case "Q1": + arng = ARNG_D + case "Q": if isIndex { - return errors.New("invalid register extension") - } - a.Reg = REG_ARNG + (reg & 31) + ((ARNG_1Q & 15) << 5) - case "B": - if !isIndex { + a.Reg = REG_ZARNGELEM + (reg & 31) + int16((ARNG_Q&15)<<5) + a.Index = num return nil } - a.Reg = REG_ELEM + (reg & 31) + ((ARNG_B & 15) << 5) - a.Index = num - case "H": - if !isIndex { + arng = ARNG_Q + default: + if isIndex && ext == "" { + a.Reg = REG_PZELEM + (reg & 31) + a.Index = num return nil } - a.Reg = REG_ELEM + (reg & 31) + ((ARNG_H & 15) << 5) + return errors.New("invalid Z register arrangement: " + ext) + } + if isIndex { + a.Reg = REG_ZARNGELEM + (reg & 31) + int16((arng&15)<<5) a.Index = num - case "S": - if !isIndex { - return nil + } else { + if a.Type == obj.TYPE_MEM { + a.Index = REG_ZARNG + (reg & 31) + int16((arng&15)<<5) + } else { + a.Reg = REG_ZARNG + (reg & 31) + int16((arng&15)<<5) } - a.Reg = REG_ELEM + (reg & 31) + ((ARNG_S & 15) << 5) - a.Index = num + } + } else if REG_P0 <= reg && reg <= REG_PN15 { + var arng int + switch ext { + case "B": + arng = ARNG_B + case "H": + arng = ARNG_H + case "S": + arng = ARNG_S case "D": - if !isIndex { + arng = ARNG_D + case "Q": + arng = ARNG_Q + case "Z": + arng = PRED_Z + case "M": + arng = PRED_M + default: + if isIndex && ext == "" { + a.Reg = REG_PZELEM + (reg & 31) + (1 << 5) + a.Index = num return nil } - a.Reg = REG_ELEM + (reg & 31) + ((ARNG_D & 15) << 5) - a.Index = num - default: + return errors.New("invalid P register arrangement: " + ext) + } + a.Reg = REG_PARNGZM + (reg & 31) + int16((arng&15)<<5) + } else if reg <= REG_V31 && reg >= REG_V0 { + arng, elem := readArrangement(ext) + if arng == -1 { return errors.New("unsupported simd register extension type: " + ext) } + if elem && !isIndex { + return nil + } + var err error + if reg, err = RegisterArrangement(reg, arng, isIndex); err != nil { + return err + } + a.Reg = reg + if isIndex { + a.Index = num + } } else { return errors.New("invalid register and extension combination") } return nil } + +// readArrangement returns arrangement constant (or -1 for unknown arrangement) +// and a boolean flag specifying whether it refers to a vector element. +func readArrangement(name string) (arng int16, elem bool) { + switch name { + case "B8": + return ARNG_8B, false + case "B16": + return ARNG_16B, false + case "H4": + return ARNG_4H, false + case "H8": + return ARNG_8H, false + case "S2": + return ARNG_2S, false + case "S4": + return ARNG_4S, false + case "D1": + return ARNG_1D, false + case "D2": + return ARNG_2D, false + case "B": + return ARNG_B, true + case "H": + return ARNG_H, true + case "S": + return ARNG_S, true + case "D": + return ARNG_D, true + case "Q1": + return ARNG_1Q, false + default: + return -1, false + } +} + +// RegisterArrangement encodes specified simd register number and arrangement. +func RegisterArrangement(reg int16, arng int16, isIndex bool) (int16, error) { + arng &= 15 + arrangement := arng << 5 + switch arng { + case ARNG_B, ARNG_H, ARNG_S, ARNG_D: + if !isIndex { + return reg, nil + } + return REG_ELEM + (reg & 31) + arrangement, nil + case ARNG_16B, ARNG_8H, ARNG_4S, ARNG_2D, + ARNG_8B, ARNG_4H, ARNG_2S, ARNG_1D, ARNG_1Q: + if isIndex { + return 0, errors.New("invalid register extension") + } + return REG_ARNG + (reg & 31) + arrangement, nil + } + return 0, errors.New("unsupported simd register arrangement: " + fmt.Sprint(arng)) +} + +// RegisterListOffset generates offset encoding according to AArch64 specification. +func RegisterListOffset(firstReg, regCnt int, arrangement int64, scale int16) (int64, error) { + offset := int64(firstReg) + if scale == 0 { + switch regCnt { + case 1: + offset |= 0x7 << 12 + case 2: + offset |= 0xa << 12 + case 3: + offset |= 0x6 << 12 + case 4: + offset |= 0x2 << 12 + default: + return 0, errors.New("invalid register numbers in ARM64 register list") + } + } else { + // scale is either 1 or 3. + offset |= int64(scale) << 12 + } + offset |= arrangement + offset |= obj.RegListARM64Lo + return offset, nil +} diff --git a/src/cmd/internal/obj/arm64/asm_arm64_test.go b/src/cmd/internal/obj/arm64/asm_arm64_test.go index 83d137a08466bd..b83db60b40f118 100644 --- a/src/cmd/internal/obj/arm64/asm_arm64_test.go +++ b/src/cmd/internal/obj/arm64/asm_arm64_test.go @@ -38,3 +38,16 @@ func TestMOVK(t *testing.T) { t.Errorf("Got %x want %x\n", x, want) } } + +func testCombined() (a uint64, b uint64) +func TestCombined(t *testing.T) { + got1, got2 := testCombined() + want1 := uint64(0xaaaaaaaaaaaaaaab) + want2 := uint64(0x0ff019940ff00ff0) + if got1 != want1 { + t.Errorf("First result, got %x want %x", got1, want1) + } + if got2 != want2 { + t.Errorf("First result, got %x want %x", got2, want2) + } +} diff --git a/src/cmd/internal/obj/arm64/asm_arm64_test.s b/src/cmd/internal/obj/arm64/asm_arm64_test.s index e3fda57775f3af..65d80d1380f1cc 100644 --- a/src/cmd/internal/obj/arm64/asm_arm64_test.s +++ b/src/cmd/internal/obj/arm64/asm_arm64_test.s @@ -37,3 +37,11 @@ TEXT ·testmovk(SB), NOSPLIT, $0-8 MOVK $(40000<<48), R0 MOVD R0, ret+0(FP) RET + +// testCombined() (uint64, uint64) +TEXT ·testCombined(SB), NOSPLIT, $0-16 + MOVD $0xaaaaaaaaaaaaaaab, R0 + MOVD $0x0ff019940ff00ff0, R1 + MOVD R0, a+0(FP) + MOVD R1, b+8(FP) + RET diff --git a/src/cmd/internal/obj/arm64/asm_test.go b/src/cmd/internal/obj/arm64/asm_test.go index 6347bafc7e41c3..bf00e4648b6f77 100644 --- a/src/cmd/internal/obj/arm64/asm_test.go +++ b/src/cmd/internal/obj/arm64/asm_test.go @@ -46,8 +46,8 @@ func TestSplitImm24uScaled(t *testing.T) { { v: 0x1001, shift: 0, - wantHi: 0x1000, - wantLo: 0x1, + wantHi: 0x2, + wantLo: 0xfff, }, { v: 0xffffff, @@ -75,8 +75,8 @@ func TestSplitImm24uScaled(t *testing.T) { { v: 0x2002, shift: 1, - wantHi: 0x2000, - wantLo: 0x1, + wantHi: 0x4, + wantLo: 0xfff, }, { v: 0xfffffe, @@ -95,6 +95,11 @@ func TestSplitImm24uScaled(t *testing.T) { shift: 1, wantErr: true, }, + { + v: 0x1000001, + shift: 1, + wantErr: true, + }, { v: 0xfffffe, shift: 2, @@ -103,8 +108,8 @@ func TestSplitImm24uScaled(t *testing.T) { { v: 0x4004, shift: 2, - wantHi: 0x4000, - wantLo: 0x1, + wantHi: 0x8, + wantLo: 0xfff, }, { v: 0xfffffc, @@ -131,8 +136,8 @@ func TestSplitImm24uScaled(t *testing.T) { { v: 0x8008, shift: 3, - wantHi: 0x8000, - wantLo: 0x1, + wantHi: 0x10, + wantLo: 0xfff, }, { v: 0xfffff8, @@ -151,6 +156,127 @@ func TestSplitImm24uScaled(t *testing.T) { shift: 3, wantErr: true, }, + // Unshifted hi cases - hi <= 0xfff fits directly + { + v: 7, + shift: 3, + wantHi: 7, + wantLo: 0, + }, + { + v: 0x8ff7, + shift: 3, + wantHi: 0xfff, + wantLo: 0xfff, + }, + { + v: 0x7ff8, + shift: 3, + wantHi: 0, + wantLo: 0xfff, + }, + { + v: 0xfff, + shift: 1, + wantHi: 1, + wantLo: 0x7ff, + }, + { + v: 0xfff, + shift: 2, + wantHi: 3, + wantLo: 0x3ff, + }, + { + v: 0xfff, + shift: 3, + wantHi: 7, + wantLo: 0x1ff, + }, + { + v: 0x1ffe, + shift: 2, + wantHi: 2, + wantLo: 0x7ff, + }, + { + v: 0x1ffe, + shift: 3, + wantHi: 6, + wantLo: 0x3ff, + }, + { + v: 0x1fff, + shift: 1, + wantHi: 1, + wantLo: 0xfff, + }, + { + v: 0x1fff, + shift: 2, + wantHi: 3, + wantLo: 0x7ff, + }, + { + v: 0x1fff, + shift: 3, + wantHi: 7, + wantLo: 0x3ff, + }, + { + v: 0x1001, + shift: 1, + wantHi: 1, + wantLo: 0x800, + }, + { + v: 0x1001, + shift: 2, + wantHi: 1, + wantLo: 0x400, + }, + { + v: 0x1001, + shift: 3, + wantHi: 1, + wantLo: 0x200, + }, + { + v: 0x1000, + shift: 0, + wantHi: 0x1, + wantLo: 0xfff, + }, + { + v: 0x8000, + shift: 3, + wantHi: 0x8, + wantLo: 0xfff, + }, + { + v: 0xfff, + shift: 0, + wantHi: 0, + wantLo: 0xfff, + }, + { + v: 0x1ffe, + shift: 1, + wantHi: 0, + wantLo: 0xfff, + }, + { + v: 0x3ffc, + shift: 2, + wantHi: 0, + wantLo: 0xfff, + }, + { + v: 0x10fef, + shift: 4, + wantHi: 0xfff, + wantLo: 0xfff, + }, } for _, test := range tests { hi, lo, err := splitImm24uScaled(test.v, test.shift) @@ -179,6 +305,21 @@ func TestSplitImm24uScaled(t *testing.T) { } } } + + // Test the unshifted hi range specifically, including unaligned values. + // This exercises values where the unshifted path may be used. + for shift := 0; shift <= 3; shift++ { + maxUnshifted := int32(0xfff + 0xfff<= obj.RBaseARM64 { + if !(*v >= REG_Z0 && *v <= REG_Z31) && !(*v >= REG_ZARNG && *v < REG_ZARNGELEM) { + return false + } + } + *v = *v & 31 + return true +} + +// checkIsR checks if v is a scalar register: +// - if v is a raw register number or is within the ARM64 scalar register range, +// it returns true. +// - otherwise it returns false. +func checkIsR(v uint32) bool { + if v > REG_R31 && v != REG_RSP { + return false + } + return true +} + +const ( + enc_NIL component = iota + enc_i1_tsz + enc_i2h_i2l + enc_i3h_i3l + enc_i4h_i4l + enc_imm2_tsz + enc_imm8h_imm8l + enc_imm9h_imm9l + enc_tsize_imm3 + enc_tszh_tszl_imm3 + enc_tszh_tszl + enc_M + enc_PNd + enc_PNg + enc_PNn + enc_Pd + enc_Pdm + enc_Pdn + enc_Pg + enc_Pm + enc_Pn + enc_Pt + enc_Pv + enc_Rd + enc_Rdn + enc_Rm + enc_Rn + enc_Vd + enc_Vdn + enc_Vm + enc_Vn + enc_Za + enc_Zd + enc_Zda + enc_Zdn + enc_Zk + enc_Zm + enc_Zn + enc_Zt + enc_i1 + enc_i2 + enc_imm13 + enc_imm2 + enc_imm3 + enc_imm4 + enc_imm5 + enc_imm5b + enc_imm6 + enc_imm7 + enc_imm8 + enc_msz + enc_prfop + enc_rot + enc_size + enc_size0 + enc_sz + enc_tsize + enc_tsz + enc_vl + enc_xs +) + +// encodeNoModCheck is the implementation of the following encoding logic: +// Check that there is no modifier (UXTW, SXTW, LSL) +func encodeNoModCheck(v uint32) (uint32, bool) { + return 0, v == 0 +} + +// encodeNoAmtCheck is the implementation of the following encoding logic: +// Check that there is no modifier amount +func encodeNoAmtCheck(v uint32) (uint32, bool) { + return 0, v == 0 +} + +// encodeXCheck is the implementation of the following encoding logic: +// Check this is a 64-bit scalar register +func encodeXCheck(v uint32) (uint32, bool) { + return 0, true +} + +// encodeArngBCheck is the implementation of the following encoding logic: +// Check this is a B arrangement +func encodeArngBCheck(v uint32) (uint32, bool) { + if v == ARNG_B { + return 0, true + } + return 0, false +} + +// encodeArngDCheck is the implementation of the following encoding logic: +// Check this is a D arrangement +func encodeArngDCheck(v uint32) (uint32, bool) { + if v == ARNG_D { + return 0, true + } + return 0, false +} + +// encodeArngHCheck is the implementation of the following encoding logic: +// Check this is a H arrangement +func encodeArngHCheck(v uint32) (uint32, bool) { + if v == ARNG_H { + return 0, true + } + return 0, false +} + +// encodeArngQCheck is the implementation of the following encoding logic: +// Check this is a Q arrangement +func encodeArngQCheck(v uint32) (uint32, bool) { + if v == ARNG_Q { + return 0, true + } + return 0, false +} + +// encodeArngSCheck is the implementation of the following encoding logic: +// Check this is a S arrangement +func encodeArngSCheck(v uint32) (uint32, bool) { + if v == ARNG_S { + return 0, true + } + return 0, false +} + +// encodeMergePredCheck is the implementation of the following encoding logic: +// Check this is a merging predication +func encodeMergePredCheck(v uint32) (uint32, bool) { + if v == PRED_M { + return 0, true + } + return 0, false +} + +// encodeZeroPredCheck is the implementation of the following encoding logic: +// Check this is a zeroing predication +func encodeZeroPredCheck(v uint32) (uint32, bool) { + if v == PRED_Z { + return 0, true + } + return 0, false +} + +// encodeFimm0_0_56 is the implementation of the following encoding logic: +// Check this is immediate 0.0 +func encodeFimm0_0_56(v uint32) (uint32, bool) { + if (v & 0x7FFFFFFF) != 0 { + return 0, false + } + return 0, true +} + +// encodeModAmt1Check is the implementation of the following encoding logic: +// Check this is mod amount and is 1 +func encodeModAmt1Check(v uint32) (uint32, bool) { + if v == 1 { + return 0, true + } + return 0, false +} + +// encodeModAmt2Check is the implementation of the following encoding logic: +// Check this is mod amount and is 2 +func encodeModAmt2Check(v uint32) (uint32, bool) { + if v == 2 { + return 0, true + } + return 0, false +} + +// encodeModAmt3Check is the implementation of the following encoding logic: +// Check this is mod amount and is 3 +func encodeModAmt3Check(v uint32) (uint32, bool) { + if v == 3 { + return 0, true + } + return 0, false +} + +// encodeModAmt4Check is the implementation of the following encoding logic: +// Check this is mod amount and is 4 +func encodeModAmt4Check(v uint32) (uint32, bool) { + if v == 4 { + return 0, true + } + return 0, false +} + +// encodeModLSLCheck is the implementation of the following encoding logic: +// Check this is mod and is LSL +func encodeModLSLCheck(v uint32) (uint32, bool) { + if v&0b100 != 0 { + return 0, true + } + return 0, false +} + +// encodeModSXTWCheck is the implementation of the following encoding logic: +// Check this is mod and is SXTW +func encodeModSXTWCheck(v uint32) (uint32, bool) { + if v&0b10 != 0 { + return 0, true + } + return 0, false +} + +// encodeModUXTWCheck is the implementation of the following encoding logic: +// Check this is mod and is UXTW +func encodeModUXTWCheck(v uint32) (uint32, bool) { + if v&0b1 != 0 { + return 0, true + } + return 0, false +} + +// encodeI2_1921_16To32Bit is the implementation of the following encoding logic: +// For the "16-bit to 32-bit" variant: is the immediate index of a pair of 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI2_1921_16To32Bit(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + +// encodeI1_2021_16To64Bit is the implementation of the following encoding logic: +// For the "16-bit to 64-bit" variant: is the immediate index of a 64-bit group of four 16-bit values within each 128-bit vector segment, in the range 0 to 1, encoded in the "i1" field. +// bit range mappings: +// i1: [20:21) +func encodeI1_2021_16To64Bit(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 20, true +} + +// encodeZm1620_16To64Bit is the implementation of the following encoding logic: +// For the "16-bit to 64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:20) +func encodeZm1620_16To64Bit(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v > 15 { + return 0, false + } + return v << 16, true +} + +// encodeZm1619_16Bit32Bit is the implementation of the following encoding logic: +// For the "16-bit" and "32-bit" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:19) +func encodeZm1619_16Bit32Bit(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v > 7 { + return 0, false + } + return v << 16, true +} + +// encodeI2_1921_16bit is the implementation of the following encoding logic: +// For the "16-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI2_1921_16bit(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + +// encodeI3hI3l_1923_16Bit is the implementation of the following encoding logic: +// For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields. +// bit range mappings: +// i3h: [22:23) +// i3l: [19:21) +func encodeI3hI3l_1923_16Bit(v uint32) (uint32, bool) { + if v > 7 { + return 0, false + } + return (v&3)<<19 | (v>>2)<<22, true +} + +// encodeImm41620V7 is the implementation of the following encoding logic: +// For the "16-bit" variant: is the immediate shift amount, in the range 1 to 16, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm41620V7(v uint32) (uint32, bool) { + if v < 1 || v > 16 { + return 0, false + } + // From ARM ASL: let shift : integer = esize - UInt(imm3); + // very weird design. + return (16 - v) << 16, true +} + +// encodeZm_1619_Range0_7V1 is the implementation of the following encoding logic: +// For the "16-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:19) +func encodeZm_1619_Range0_7V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v <= 7 { + return v << 16, true + } + return 0, false +} + +// encodeI1_2021_32bit is the implementation of the following encoding logic: +// For the "32-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field. +// bit range mappings: +// i1: [20:21) +func encodeI1_2021_32bit(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 20, true +} + +// encodeI2_1921_32Bit is the implementation of the following encoding logic: +// For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI2_1921_32Bit(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + +// encodeI3hI3l_1119_32Bit is the implementation of the following encoding logic: +// For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields. +// bit range mappings: +// i3h: [19:21) +// i3l: [11:12) +func encodeI3hI3l_1119_32Bit(v uint32) (uint32, bool) { + if v > 7 { + return 0, false + } + return (v&1)<<11 | (v>>1)<<19, true +} + +// encodeZm_1620_Range0_15 is the implementation of the following encoding logic: +// For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:20) +func encodeZm_1620_Range0_15(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v <= 15 { + return v << 16, true + } + return 0, false +} + +// encodeZm1619_32Bit is the implementation of the following encoding logic: +// For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:19) +func encodeZm1619_32Bit(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v > 7 { + return 0, false + } + return v << 16, true +} + +// encodeI1_2021_64Bit is the implementation of the following encoding logic: +// For the "64-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field. +// bit range mappings: +// i1: [20:21) +func encodeI1_2021_64Bit(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 20, true +} + +// encodeI2hI2l_1120_64Bit is the implementation of the following encoding logic: +// For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields. +// bit range mappings: +// i2h: [20:21) +// i2l: [11:12) +func encodeI2hI2l_1120_64Bit(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return (v&1)<<11 | (v>>1)<<20, true +} + +// encodeZm1620_64Bit is the implementation of the following encoding logic: +// For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:20) +func encodeZm1620_64Bit(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v > 15 { + return 0, false + } + return v << 16, true +} + +// encodeI3hI3l_1923_8To16Bit is the implementation of the following encoding logic: +// For the "8-bit to 16-bit" variant: is the immediate index of a pair of 8-bit elements within each 128-bit vector segment, in the range 0 to 7, encoded in the "i3h:i3l" fields. +// bit range mappings: +// i3h: [22:23) +// i3l: [19:21) +func encodeI3hI3l_1923_8To16Bit(v uint32) (uint32, bool) { + if v > 7 { + return 0, false + } + return (v&3)<<19 | (v>>2)<<22, true +} + +// encodeI2_1921_8To32Bit is the implementation of the following encoding logic: +// For the "8-bit to 32-bit" variant: is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI2_1921_8To32Bit(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + +// encodeZm1619_8To32Bit is the implementation of the following encoding logic: +// For the "8-bit to 32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:19) +func encodeZm1619_8To32Bit(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v > 7 { + return 0, false + } + return v << 16, true +} + +// encodeImm31619 is the implementation of the following encoding logic: +// For the "8-bit" variant: is the immediate shift amount, in the range 1 to 8, encoded in the "imm3" field. +// bit range mappings: +// imm3: [16:19) +func encodeImm31619(v uint32) (uint32, bool) { + if v < 1 || v > 8 { + return 0, false + } + return v << 16, true +} + +// encodeSzByteHalfword is the implementation of the following encoding logic: +// For the "Byte and halfword" variant: is the size specifier, +// sz +// 0 B +// 1 H +// bit range mappings: +// sz: [22:23) +func encodeSzByteHalfword(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 0, true + case ARNG_H: + return 1 << 22, true + } + return 0, false +} + +// encodeI22224 is the implementation of the following encoding logic: +// For the "Byte" variant: is the vector segment index, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [22:24) +func encodeI22224(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 22, true +} + +// encodeSizeByteMergeZero is the implementation of the following encoding logic: +// For the "Byte, merging" and "Byte, zeroing" variants: is the size specifier, +// size +// 00 RESERVED +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [22:24) +func encodeSizeByteMergeZero(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 22, true + case ARNG_S: + return 2 << 22, true + case ARNG_D: + return 3 << 22, true + } + return 0, false +} + +// encodeI12324B is the implementation of the following encoding logic: +// For the "Byte, single register table" variant: is the vector segment index, in the range 0 to 1, encoded in the "i1" field. +// bit range mappings: +// i1: [23:24) +func encodeI12324B(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 23, true +} + +// encodeI1_2021_DoublePrecision is the implementation of the following encoding logic: +// For the "Double-precision" variant: is the immediate index, in the range 0 to 1, encoded in the "i1" field. +// bit range mappings: +// i1: [20:21) +func encodeI1_2021_DoublePrecision(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 20, true +} + +// encodeZm1620_DoublePrecision is the implementation of the following encoding logic: +// For the "Double-precision" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:20) +func encodeZm1620_DoublePrecision(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v > 15 { + return 0, false + } + return v << 16, true +} + +// encodeI3hI3l_1722_Doubleword is the implementation of the following encoding logic: +// For the "Doubleword" variant: is the optional portion index, in the range 0 to 7, defaulting to 0, encoded in the "i3h:i3l" fields. +// bit range mappings: +// i3h: [22:23) +// i3l: [17:19) +func encodeI3hI3l_1722_Doubleword(v uint32) (uint32, bool) { + if v > 7 { + return 0, false + } + return (v&3)<<17 | (v>>2)<<22, true +} + +// encodeImm5Signed_1621V2 is the implementation of the following encoding logic: +// For the "Equal", "Greater than or equal", "Greater than", "Less than or equal", "Less than", and "Not equal" variants: is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. +// bit range mappings: +// imm5: [16:21) +func encodeImm5Signed_1621V2(v uint32) (uint32, bool) { + if int32(v) >= -16 && int32(v) <= 15 { + return (v & 31) << 16, true + } + return 0, false +} + +// encodeZdn25V1 is the implementation of the following encoding logic: +// For the "Four registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4. +// bit range mappings: +// Zdn: [2:5) +func encodeZdn25V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v%4 != 0 { + return 0, false + } + return (v / 4) << 2, true +} + +// encodeZt25V1 is the implementation of the following encoding logic: +// For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4. +// bit range mappings: +// Zt: [2:5) +func encodeZt25V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v%4 != 0 { + return 0, false + } + return (v / 4) << 2, true +} + +// encodeImm41620V8 is the implementation of the following encoding logic: +// For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm41620V8(v uint32) (uint32, bool) { + val := int32(v) + if val < -32 || val > 28 || val%4 != 0 { + return 0, false + } + encoded := uint32((val >> 2) & 0xf) + return encoded << 16, true +} + +// encodeZm1619_HalfSinglePrecision is the implementation of the following encoding logic: +// For the "Half-precision" and "Single-precision" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:19) +func encodeZm1619_HalfSinglePrecision(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v > 7 { + return 0, false + } + return v << 16, true +} + +// encodeI3hI3l_1923_HalfPrecision is the implementation of the following encoding logic: +// For the "Half-precision" variant: is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields. +// bit range mappings: +// i3h: [22:23) +// i3l: [19:21) +func encodeI3hI3l_1923_HalfPrecision(v uint32) (uint32, bool) { + if v > 7 { + return 0, false + } + return (v&3)<<19 | (v>>2)<<22, true +} + +// encodeI2_1921_Half is the implementation of the following encoding logic: +// For the "Half-precision" variant: is the index of a Real and Imaginary pair, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI2_1921_Half(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + +// encodeZm_1619_Half is the implementation of the following encoding logic: +// For the "Half-precision" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:19) +func encodeZm_1619_Half(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v <= 7 { + return v << 16, true + } + return 0, false +} + +// encodeI1_1718_Halfword is the implementation of the following encoding logic: +// For the "Halfword" variant: is the optional portion index, in the range 0 to 1, defaulting to 0, encoded in the "i1" field. +// bit range mappings: +// i1: [17:18) +func encodeI1_1718_Halfword(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 17, true +} + +// encodeI3224I31213 is the implementation of the following encoding logic: +// For the "Halfword" variant: is the vector segment index, in the range 0 to 7, encoded in the "i3h:i3l" fields. +// bit range mappings: +// i3h: [22:24) +// i3l: [12:13) +func encodeI3224I31213(v uint32) (uint32, bool) { + if v > 7 { + return 0, false + } + return (v&1)<<12 | (v>>1)<<22, true +} + +// encodeSize0HalfwordMergeZero is the implementation of the following encoding logic: +// For the "Halfword, merging" and "Halfword, zeroing" variants: is the size specifier, +// size[0] +// 0 S +// 1 D +// bit range mappings: +// size: [22:23) +func encodeSize0HalfwordMergeZero(v uint32) (uint32, bool) { + switch v { + case ARNG_S: + return 0, true + case ARNG_D: + return 1 << 22, true + } + return 0, false +} + +// encodeI22224HW is the implementation of the following encoding logic: +// For the "Halfword, single register table" and "Halfword, two register table" variants: is the vector segment index, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [22:24) +func encodeI22224HW(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 22, true +} + +// encodeImm7Unsigned_1421 is the implementation of the following encoding logic: +// For the "Higher or same", "Higher", "Lower or same", and "Lower" variants: is the unsigned immediate operand, in the range 0 to 127, encoded in the "imm7" field. +// bit range mappings: +// imm7: [14:21) +func encodeImm7Unsigned_1421(v uint32) (uint32, bool) { + if v <= 127 { + return v << 14, true + } + return 0, false +} + +// encodeI2_1921_SinglePrecision is the implementation of the following encoding logic: +// For the "Single-precision" variant: is the immediate index, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI2_1921_SinglePrecision(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + +// encodeI1_2021_Single is the implementation of the following encoding logic: +// For the "Single-precision" variant: is the index of a Real and Imaginary pair, in the range 0 to 1, encoded in the "i1" field. +// bit range mappings: +// i1: [20:21) +func encodeI1_2021_Single(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 20, true +} + +// encodeZm_1620_Single is the implementation of the following encoding logic: +// For the "Single-precision" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:20) +func encodeZm_1620_Single(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v <= 15 { + return v << 16, true + } + return 0, false +} + +// encodeZdn15V1 is the implementation of the following encoding logic: +// For the "Two registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2. +// bit range mappings: +// Zdn: [1:5) +func encodeZdn15V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v%2 != 0 { + return 0, false + } + return (v / 2) << 1, true +} + +// encodeZt15V1 is the implementation of the following encoding logic: +// For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2. +// bit range mappings: +// Zt: [1:5) +func encodeZt15V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v%2 != 0 { + return 0, false + } + return (v / 2) << 1, true +} + +// encodeImm41620V9 is the implementation of the following encoding logic: +// For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm41620V9(v uint32) (uint32, bool) { + val := int32(v) + if val < -16 || val > 14 || val%2 != 0 { + return 0, false + } + encoded := uint32((val>>1)&0xf) << 16 + return encoded, true +} + +// encodeSzWordDoubleword is the implementation of the following encoding logic: +// For the "Word and doubleword" variant: is the size specifier, +// sz +// 0 S +// 1 D +// bit range mappings: +// sz: [22:23) +func encodeSzWordDoubleword(v uint32) (uint32, bool) { + switch v { + case ARNG_S: + return 0, true + case ARNG_D: + return 1 << 22, true + } + return 0, false +} + +// encodeI2_1719_Word is the implementation of the following encoding logic: +// For the "Word" variant: is the optional portion index, in the range 0 to 3, defaulting to 0, encoded in the "i2" field. +// bit range mappings: +// i2: [17:19) +func encodeI2_1719_Word(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 17, true +} + +// encodeImm13_518 is the implementation of the following encoding logic: +// Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field. +// bit range mappings: +// imm13: [5:18) +func encodeImm13_518(v uint32) (uint32, bool) { + return codeLogicalImmArrEncoding, false +} + +// encodeImm8_513_Fimm is the implementation of the following encoding logic: +// Is a floating-point immediate value expressible as ±n÷16×2^r, where n and r are integers such that 16 ≤ n ≤ 31 and -3 ≤ r ≤ 4, i.e. a normalized binary floating-point encoding with 1 sign bit, 3-bit exponent, and 4-bit fractional part, encoded in the "imm8" field. +// bit range mappings: +// imm8: [5:13) +func encodeImm8_513_Fimm(v uint32) (uint32, bool) { + if v <= 255 { + return v << 5, true + } + return 0, false +} + +// encodeImm8SignedLsl8 is the implementation of the following encoding logic: +// Is a signed immediate in the range -128 to 127, encoded in the "imm8" field. +// bit range mappings: +// imm8: [5:13) +// +// Is the optional left shift to apply to the immediate, defaulting to LSL #0 and +// sh +// 0 LSL #0 +// 1 LSL #8 +// bit range mappings: +// sh: [13:14) +func encodeImm8SignedLsl8(v uint32) (uint32, bool) { + vi := int32(v) + if vi >= -128 && vi <= 127 { + imm8 := uint32(uint8(int8(vi))) + return (imm8 << 5), true + } + if vi&255 == 0 { + unshifted := vi >> 8 + if unshifted >= -128 && unshifted <= 127 { + imm8 := uint32(uint8(int8(unshifted))) + return (imm8 << 5) | (1 << 13), true + } + } + return 0, false +} + +// encodeSize16B8H4S2D is the implementation of the following encoding logic: +// Is an arrangement specifier, +// size +// 00 16B +// 01 8H +// 10 4S +// 11 2D +// bit range mappings: +// size: [22:24) +func encodeSize16B8H4S2D(v uint32) (uint32, bool) { + switch v { + case ARNG_16B: + return 0, true + case ARNG_8H: + return 1 << 22, true + case ARNG_4S: + return 2 << 22, true + case ARNG_2D: + return 3 << 22, true + } + return 0, false +} + +// encodeSize8H4S2D is the implementation of the following encoding logic: +// Is an arrangement specifier, +// size +// 00 RESERVED +// 01 8H +// 10 4S +// 11 2D +// bit range mappings: +// size: [22:24) +func encodeSize8H4S2D(v uint32) (uint32, bool) { + switch v { + case ARNG_8H: + return 1 << 22, true + case ARNG_4S: + return 2 << 22, true + case ARNG_2D: + return 3 << 22, true + } + return 0, false +} + +// encodeImm8UnsignedLsl8 is the implementation of the following encoding logic: +// Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field. +// bit range mappings: +// imm8: [5:13) +// +// Is the optional left shift to apply to the immediate, defaulting to LSL #0 and +// sh +// 0 LSL #0 +// 1 LSL #8 +// bit range mappings: +// sh: [13:14) +func encodeImm8UnsignedLsl8(v uint32) (uint32, bool) { + if v <= 255 { + return v << 5, true + } + if v&255 == 0 { + unshifted := v >> 8 + if unshifted <= 255 { + return (unshifted << 5) | (1 << 13), true + } + } + return 0, false +} + +// encodeWdn05 is the implementation of the following encoding logic: +// Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field. +// bit range mappings: +// Rdn: [0:5) +func encodeWdn05(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return v & 31, true +} + +// encodeVd0564 is the implementation of the following encoding logic: +// Is the 64-bit name of the destination SIMD&FP register, encoded in the "Vd" field. +// bit range mappings: +// Vd: [0:5) +func encodeVd0564(v uint32) (uint32, bool) { + return v & 31, true +} + +// encodeRd05_SPAllowed is the implementation of the following encoding logic: +// Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field. +// bit range mappings: +// Rd: [0:5) +func encodeRd05_SPAllowed(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_R31 { + return 0, false + } + if v == REG_RSP { + return 31, true + } + return v & 31, true +} + +// encodeRd05 is the implementation of the following encoding logic: +// Is the 64-bit name of the destination general-purpose register, encoded in the "Rd" field. +// bit range mappings: +// Rd: [0:5) +func encodeRd05(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return v & 31, true +} + +// encodeRn510 is the implementation of the following encoding logic: +// Is the 64-bit name of the first source general-purpose register, encoded in the "Rn" field. +// bit range mappings: +// Rn: [5:10) +func encodeRn510(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return (v & 31) << 5, true +} + +// encodeRn510SPV2 is the implementation of the following encoding logic: +// Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. +// bit range mappings: +// Rn: [5:10) +func encodeRn510SPV2(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_R31 { + return 0, false + } + if v == REG_RSP { + return 31 << 5, true + } + return (v & 31) << 5, true +} + +// encodeRm1621V2 is the implementation of the following encoding logic: +// Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. +// bit range mappings: +// Rm: [16:21) +func encodeRm1621V2(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return (v & 31) << 16, true +} + +// encodeRm1621V1 is the implementation of the following encoding logic: +// Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field. +// bit range mappings: +// Rm: [16:21) +func encodeRm1621V1(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return (v & 31) << 16, true +} + +// encodeXdn05 is the implementation of the following encoding logic: +// Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field. +// bit range mappings: +// Rdn: [0:5) +func encodeXdn05(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return v & 31, true +} + +// encodeRn1621_SPAllowed is the implementation of the following encoding logic: +// Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field. +// bit range mappings: +// Rn: [16:21) +func encodeRn1621_SPAllowed(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_R31 { + return 0, false + } + if v == REG_RSP { + return 31 << 16, true + } + return (v & 31) << 16, true +} + +// encodeRot90_270_1011 is the implementation of the following encoding logic: +// Is the const specifier, +// rot +// 0 #90 +// 1 #270 +// bit range mappings: +// rot: [10:11) +func encodeRot90_270_1011(v uint32) (uint32, bool) { + switch v { + case 90: + return 0, true + case 270: + return 1 << 10, true + } + return 0, false +} + +// encodeRot90_270_1617 is the implementation of the following encoding logic: +// Is the const specifier, +// rot +// 0 #90 +// 1 #270 +// bit range mappings: +// rot: [16:17) +func encodeRot90_270_1617(v uint32) (uint32, bool) { + switch v { + case 90: + return 0, true + case 270: + return 1 << 16, true + } + return 0, false +} + +// encodeRot0_90_180_270_1012 is the implementation of the following encoding logic: +// Is the const specifier, +// rot +// 00 #0 +// 01 #90 +// 10 #180 +// 11 #270 +// bit range mappings: +// rot: [10:12) +func encodeRot0_90_180_270_1012(v uint32) (uint32, bool) { + switch v { + case 0: + return 0, true + case 90: + return 1 << 10, true + case 180: + return 2 << 10, true + case 270: + return 3 << 10, true + } + return 0, false +} + +// encodeRot0_90_180_270_1315 is the implementation of the following encoding logic: +// Is the const specifier, +// rot +// 00 #0 +// 01 #90 +// 10 #180 +// 11 #270 +// bit range mappings: +// rot: [13:15) +func encodeRot0_90_180_270_1315(v uint32) (uint32, bool) { + switch v { + case 0: + return 0, true + case 90: + return 1 << 13, true + case 180: + return 2 << 13, true + case 270: + return 3 << 13, true + } + return 0, false +} + +// encodeImm5Signed_510 is the implementation of the following encoding logic: +// Is the first signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. +// bit range mappings: +// imm5: [5:10) +func encodeImm5Signed_510(v uint32) (uint32, bool) { + if int32(v) >= -16 && int32(v) <= 15 { + return (v & 31) << 5, true + } + return 0, false +} + +// encodeFimm0_0_1_0_56 is the implementation of the following encoding logic: +// Is the floating-point immediate value, +// i1 +// 0 #0.0 +// 1 #1.0 +// bit range mappings: +// i1: [5:6) +func encodeFimm0_0_1_0_56(v uint32) (uint32, bool) { + switch v { + case 0: + return 0, true + case 0x3F800000: // 1.0 + return 1 << 5, true + } + return 0, false +} + +// encodeFimm0_5_1_0_56 is the implementation of the following encoding logic: +// Is the floating-point immediate value, +// i1 +// 0 #0.5 +// 1 #1.0 +// bit range mappings: +// i1: [5:6) +func encodeFimm0_5_1_0_56(v uint32) (uint32, bool) { + switch v { + case 0x3F000000: // 0.5 + return 0, true + case 0x3F800000: // 1.0 + return 1 << 5, true + } + return 0, false +} + +// encodeFimm0_5_2_0_56 is the implementation of the following encoding logic: +// Is the floating-point immediate value, +// i1 +// 0 #0.5 +// 1 #2.0 +// bit range mappings: +// i1: [5:6) +func encodeFimm0_5_2_0_56(v uint32) (uint32, bool) { + switch v { + case 0x3F000000: // 0.5 + return 0, true + case 0x40000000: // 2.0 + return 1 << 5, true + } + return 0, false +} + +// encodeI2_1921_8BitGroup is the implementation of the following encoding logic: +// Is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI2_1921_8BitGroup(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + +// encodeI2_1921_Pair16Bit is the implementation of the following encoding logic: +// Is the immediate index of a pair of 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI2_1921_Pair16Bit(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + +// encodeI3hI3l_1119_Pair8Bit is the implementation of the following encoding logic: +// Is the immediate index of a pair of 8-bit elements within each 128-bit vector segment, in the range 0 to 7, encoded in the "i3h:i3l" fields. +// bit range mappings: +// i3h: [19:21) +// i3l: [11:12) +func encodeI3hI3l_1119_Pair8Bit(v uint32) (uint32, bool) { + if v > 7 { + return 0, false + } + return (v&1)<<11 | (v>>1)<<19, true +} + +// encodeI4hI4l_1019 is the implementation of the following encoding logic: +// Is the immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields. +// bit range mappings: +// i4h: [19:21) +// i4l: [10:12) +func encodeI4hI4l_1019(v uint32) (uint32, bool) { + if v > 15 { + return 0, false + } + return (v&3)<<10 | (v>>2)<<19, true +} + +// encodeI3hI3l_1119 is the implementation of the following encoding logic: +// Is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields. +// bit range mappings: +// i3h: [19:21) +// i3l: [11:12) +func encodeI3hI3l_1119(v uint32) (uint32, bool) { + if v > 7 { + return 0, false + } + return (v&1)<<11 | (v>>1)<<19, true +} + +// encodeI3hI3l_1922 is the implementation of the following encoding logic: +// Is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields. +// bit range mappings: +// i3h: [22:23) +// i3l: [19:21) +func encodeI3hI3l_1922(v uint32) (uint32, bool) { + if v > 7 { + return 0, false + } + return (v&3)<<19 | (v>>2)<<22, true +} + +// encodeI1Tsz_Delegate is the implementation of the following encoding logic: +// Is the immediate index, in the range 0 to one less than the number of elements in 128 bits, encoded in "i1:tsz". +// bit range mappings: +// i1: [20:21) +// tsz: [16:20) +func encodeI1Tsz_Delegate(v uint32) (uint32, bool) { + // The statement "range 0 to one less than the number of elements in 128 bits" + // is not possible to handle here, we delegate this to the caller. + return codeI1Tsz, false +} + +// encodeImm2Tsz_Delegate is the implementation of the following encoding logic: +// Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz". +// bit range mappings: +// imm2: [22:24) +// tsz: [16:21) +func encodeImm2Tsz_Delegate(v uint32) (uint32, bool) { + // The statement "range 0 to one less than the number of elements in 512 bits" + // is not possible to handle here, we delegate this to the caller. + return codeImm2Tsz, false +} + +// encodeShiftTsz1619Range0V1 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [16:19) +// tszh: [22:23) +// tszl: [19:21) +func encodeShiftTsz1619Range0V1(v uint32) (uint32, bool) { + return codeShift161919212223, false +} + +// encodeShiftTsz1619Range0V2 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [16:19) +// tszh: [22:24) +// tszl: [19:21) +func encodeShiftTsz1619Range0V2(v uint32) (uint32, bool) { + return codeShift161919212224, false +} + +// encodeShiftTsz58Range0 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [5:8) +// tszh: [22:24) +// tszl: [8:10) +func encodeShiftTsz58Range0(v uint32) (uint32, bool) { + return codeShift588102224, false +} + +// encodeImm3Tsize1621Stub is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsize:imm3". +// bit range mappings: +// imm3: [16:19) +// tsize: [19:21) +func encodeImm3Tsize1621Stub(v uint32) (uint32, bool) { + return codeImm3Tsize1621, false +} + +// encodeShiftTsz1619Range1V1 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [16:19) +// tszh: [22:23) +// tszl: [19:21) +func encodeShiftTsz1619Range1V1(v uint32) (uint32, bool) { + return codeShift161919212223, false +} + +// encodeShiftTsz1619Range1V2 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [16:19) +// tszh: [22:24) +// tszl: [19:21) +func encodeShiftTsz1619Range1V2(v uint32) (uint32, bool) { + return codeShift161919212224, false +} + +// encodeShiftTsz58Range1 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [5:8) +// tszh: [22:24) +// tszl: [8:10) +func encodeShiftTsz58Range1(v uint32) (uint32, bool) { + return codeShift588102224, false +} + +// encodeMsz1012 is the implementation of the following encoding logic: +// Is the index extend and shift specifier, +// msz +// 00 [absent] +// x1 LSL +// 10 LSL +// bit range mappings: +// msz: [10:12) +func encodeMsz1012(v uint32) (uint32, bool) { + // This does not accept UXTW and SXTW, check that + if v&0b11 != 0 { + return 0, false + } + // Note: this encoding function's semantic is entailed by its peer that + // encode , so just do nothing. + return codeNoOp, false +} + +// encodeXs1415 is the implementation of the following encoding logic: +// Is the index extend and shift specifier, +// xs +// 0 UXTW +// 1 SXTW +// bit range mappings: +// xs: [14:15) +func encodeXs1415(v uint32) (uint32, bool) { + if v&0b1 != 0 { + return 0, true + } else if v&0b10 != 0 { + return 1 << 14, true + } + return 0, false +} + +// encodeXs2223 is the implementation of the following encoding logic: +// Is the index extend and shift specifier, +// xs +// 0 UXTW +// 1 SXTW +// bit range mappings: +// xs: [22:23) +func encodeXs2223(v uint32) (uint32, bool) { + if v&0b1 != 0 { + return 0, true + } else if v&0b10 != 0 { + return 1 << 22, true + } + return 0, false +} + +// encodeMsz1012Amount is the implementation of the following encoding logic: +// Is the index shift amount, +// msz +// 00 [absent] +// 01 #1 +// 10 #2 +// 11 #3 +// bit range mappings: +// msz: [10:12) +func encodeMsz1012Amount(v uint32) (uint32, bool) { + if v <= 3 { + return v << 10, true + } + return 0, false +} + +// encodeZn510V2 is the implementation of the following encoding logic: +// Is the name of the base scalable vector register, encoded in the "Zn" field. +// bit range mappings: +// Zn: [5:10) +func encodeZn510V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 5, true +} + +// encodeVd is the implementation of the following encoding logic: +// Is the name of the destination SIMD&FP register, encoded in the "Vd" field. +// bit range mappings: +// Vd: [0:5) +func encodeVd(v uint32) (uint32, bool) { + return v & 31, true +} + +// encodePNd is the implementation of the following encoding logic: +// Is the name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field. +// bit range mappings: +// PNd: [0:3) +func encodePNd(v uint32) (uint32, bool) { + if v >= 24 && v <= 31 { + // PN registers starts from 16. + return v - 24, true + } + return 0, false +} + +// encodePd is the implementation of the following encoding logic: +// Is the name of the destination scalable predicate register, encoded in the "Pd" field. +// bit range mappings: +// Pd: [0:4) +func encodePd(v uint32) (uint32, bool) { + return v, true +} + +// encodePt04V1 is the implementation of the following encoding logic: +// Is the name of the destination scalable predicate register, encoded in the "Pt" field. +// bit range mappings: +// Pt: [0:4) +func encodePt04V1(v uint32) (uint32, bool) { + if v > 15 { + return 0, false + } + return v, true +} + +// encodeZd is the implementation of the following encoding logic: +// Is the name of the destination scalable vector register, encoded in the "Zd" field. +// bit range mappings: +// Zd: [0:5) +func encodeZd(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v, true +} + +// encodePd14 is the implementation of the following encoding logic: +// Is the name of the first destination scalable predicate register, encoded as "Pd" times 2. +// bit range mappings: +// Pd: [1:4) +func encodePd14(v uint32) (uint32, bool) { + if v > 14 { + return 0, false + } + if v&1 != 0 { + return 0, false + } + return v, true +} + +// encodePd04 is the implementation of the following encoding logic: +// Is the name of the first destination scalable predicate register, encoded in the "Pd" field. +// bit range mappings: +// Pd: [0:4) +func encodePd04(v uint32) (uint32, bool) { + return v, true +} + +// encodeZd15V1 is the implementation of the following encoding logic: +// Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2. +// bit range mappings: +// Zd: [1:5) +func encodeZd15V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v%2 != 0 { + return 0, false + } + return (v / 2) << 1, true +} + +// encodeZda15V1 is the implementation of the following encoding logic: +// Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zda" times 2. +// bit range mappings: +// Zda: [1:5) +func encodeZda15V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v%2 != 0 { + return 0, false + } + return (v / 2) << 1, true +} + +// encodeGenZn510V1 is the implementation of the following encoding logic: +// Is the name of the first scalable vector register of the first source multi-vector group, encoded in the "Zn" field. +// bit range mappings: +// Zn: [5:10) +func encodeGenZn510V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 5, true +} + +// encodeZn610V1 is the implementation of the following encoding logic: +// Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. +// bit range mappings: +// Zn: [6:10) +func encodeZn610V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v%2 != 0 { + return 0, false + } + return (v / 2) << 6, true +} + +// encodeZn510MultiSrc1 is the implementation of the following encoding logic: +// Is the name of the first scalable vector register of the source multi-vector group, encoded in the "Zn" field. +// bit range mappings: +// Zn: [5:10) +func encodeZn510MultiSrc1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 5, true +} + +// encodeZt051 is the implementation of the following encoding logic: +// Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. +// bit range mappings: +// Zt: [0:5) +func encodeZt051(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v, true +} + +// encodePdnDest is the implementation of the following encoding logic: +// Is the name of the first source and destination scalable predicate register, encoded in the "Pdn" field. +// bit range mappings: +// Pdn: [0:4) +func encodePdnDest(v uint32) (uint32, bool) { + return v, true +} + +// encodeZdnDest is the implementation of the following encoding logic: +// Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. +// bit range mappings: +// Zdn: [0:5) +func encodeZdnDest(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v, true +} + +// encodePnN_58 is the implementation of the following encoding logic: +// Is the name of the first source scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNn" field. +// bit range mappings: +// PNn: [5:8) +func encodePnN_58(v uint32) (uint32, bool) { + if v >= 24 && v <= 31 { + // PN registers starts from 16. + return (v - 24) << 5, true + } + return 0, false +} + +// encodePn59 is the implementation of the following encoding logic: +// Is the name of the first source scalable predicate register, encoded in the "Pn" field. +// bit range mappings: +// Pn: [5:9) +func encodePn59(v uint32) (uint32, bool) { + return v << 5, true +} + +// encodeZn510V1 is the implementation of the following encoding logic: +// Is the name of the first source scalable vector register, encoded in the "Zn" field. +// bit range mappings: +// Zn: [5:10) +func encodeZn510V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 5, true +} + +// encodeZn510Table1 is the implementation of the following encoding logic: +// Is the name of the first table vector register, encoded as "Zn". +// bit range mappings: +// Zn: [5:10) +func encodeZn510Table1(v uint32) (uint32, bool) { + return v << 5, true +} + +// encodeZdn25V2 is the implementation of the following encoding logic: +// Is the name of the fourth scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4 plus 3. +// bit range mappings: +// Zdn: [2:5) +func encodeZdn25V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v < 3 || (v-3)%4 != 0 { + return 0, false + } + return ((v - 3) / 4) << 2, true +} + +// encodeZt054 is the implementation of the following encoding logic: +// Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32. +// bit range mappings: +// Zt: [0:5) +func encodeZt054(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v - 3) % 32, true +} + +// encodeZt25V2 is the implementation of the following encoding logic: +// Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3. +// bit range mappings: +// Zt: [2:5) +func encodeZt25V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v < 3 || (v-3)%4 != 0 { + return 0, false + } + return ((v - 3) / 4) << 2, true +} + +// encodePg1013 is the implementation of the following encoding logic: +// Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. +// bit range mappings: +// Pg: [10:13) +func encodePg1013(v uint32) (uint32, bool) { + if v <= 7 { + return v << 10, true + } + return 0, false +} + +// encodePNg1013 is the implementation of the following encoding logic: +// Is the name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field. +// bit range mappings: +// PNg: [10:13) +func encodePNg1013(v uint32) (uint32, bool) { + if v < 24 { + return 0, false + } + return (v - 24) << 10, true +} + +// encodePg1014 is the implementation of the following encoding logic: +// Is the name of the governing scalable predicate register, encoded in the "Pg" field. +// bit range mappings: +// Pg: [10:14) +func encodePg1014(v uint32) (uint32, bool) { + return v << 10, true +} + +// encodePg1620 is the implementation of the following encoding logic: +// Is the name of the governing scalable predicate register, encoded in the "Pg" field. +// bit range mappings: +// Pg: [16:20) +func encodePg1620(v uint32) (uint32, bool) { + return v << 16, true +} + +// encodePg59 is the implementation of the following encoding logic: +// Is the name of the governing scalable predicate register, encoded in the "Pg" field. +// bit range mappings: +// Pg: [5:9) +func encodePg59(v uint32) (uint32, bool) { + return v << 5, true +} + +// encodeZm1621V3 is the implementation of the following encoding logic: +// Is the name of the offset scalable vector register, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:21) +func encodeZm1621V3(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 16, true +} + +// encodePt04V2 is the implementation of the following encoding logic: +// Is the name of the scalable predicate transfer register, encoded in the "Pt" field. +// bit range mappings: +// Pt: [0:4) +func encodePt04V2(v uint32) (uint32, bool) { + if v > 15 { + return 0, false + } + return v, true +} + +// encodeZt05 is the implementation of the following encoding logic: +// Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. +// bit range mappings: +// Zt: [0:5) +func encodeZt05(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v, true +} + +// encodePd14Plus1 is the implementation of the following encoding logic: +// Is the name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1. +// bit range mappings: +// Pd: [1:4) +func encodePd14Plus1(v uint32) (uint32, bool) { + if v&1 == 0 { + return 0, false + } + return v - 1, true +} + +// encodePd04Plus1 is the implementation of the following encoding logic: +// Is the name of the second destination scalable predicate register, encoded in the "Pd" field. +// bit range mappings: +// Pd: [0:4) +func encodePd04Plus1(v uint32) (uint32, bool) { + // This "second destination" incurs Pd + 1 == v + return v - 1, true +} + +// encodeZdn15V2 is the implementation of the following encoding logic: +// Is the name of the second scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2 plus 1. +// bit range mappings: +// Zdn: [1:5) +func encodeZdn15V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v < 1 || (v-1)%2 != 0 { + return 0, false + } + return ((v - 1) / 2) << 1, true +} + +// encodeZd15V2 is the implementation of the following encoding logic: +// Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1. +// bit range mappings: +// Zd: [1:5) +func encodeZd15V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v%2 == 0 { + return 0, false + } + return ((v - 1) / 2) << 1, true +} + +// encodeZda15V2 is the implementation of the following encoding logic: +// Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zda" times 2 plus 1. +// bit range mappings: +// Zda: [1:5) +func encodeZda15V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v%2 == 0 { + return 0, false + } + return ((v - 1) / 2) << 1, true +} + +// encodeGenZn510V2 is the implementation of the following encoding logic: +// Is the name of the second scalable vector register of the first source multi-vector group, encoded in the "Zn" field. +// bit range mappings: +// Zn: [5:10) +func encodeGenZn510V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v - 1) << 5, true +} + +// encodeZn610V2 is the implementation of the following encoding logic: +// Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. +// bit range mappings: +// Zn: [6:10) +func encodeZn610V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v%2 == 0 { + return 0, false + } + return ((v - 1) / 2) << 6, true +} + +// encodeZn510MultiSrc2 is the implementation of the following encoding logic: +// Is the name of the second scalable vector register of the source multi-vector group, encoded in the "Zn" field. +// bit range mappings: +// Zn: [5:10) +func encodeZn510MultiSrc2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v - 1) << 5, true +} + +// encodeZt052 is the implementation of the following encoding logic: +// Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. +// bit range mappings: +// Zt: [0:5) +func encodeZt052(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v - 1) % 32, true +} + +// encodeZt15V2 is the implementation of the following encoding logic: +// Is the name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1. +// bit range mappings: +// Zt: [1:5) +func encodeZt15V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + if v < 1 || (v-1)%2 != 0 { + return 0, false + } + return ((v - 1) / 2) << 1, true +} + +// encodePdmDest is the implementation of the following encoding logic: +// Is the name of the second source and destination scalable predicate register, encoded in the "Pdm" field. +// bit range mappings: +// Pdm: [0:4) +func encodePdmDest(v uint32) (uint32, bool) { + return v, true +} + +// encodeZdaDest is the implementation of the following encoding logic: +// Is the name of the second source and destination scalable vector register, encoded in the "Zda" field. +// bit range mappings: +// Zda: [0:5) +func encodeZdaDest(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v, true +} + +// encodePm1620 is the implementation of the following encoding logic: +// Is the name of the second source scalable predicate register, encoded in the "Pm" field. +// bit range mappings: +// Pm: [16:20) +func encodePm1620(v uint32) (uint32, bool) { + return v << 16, true +} + +// encodeZm_1619_Range0_7V2 is the implementation of the following encoding logic: +// Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:19) +func encodeZm_1619_Range0_7V2(v uint32) (uint32, bool) { + if v <= 7 { + return v << 16, true + } + return 0, false +} + +// encodeZm1621V2 is the implementation of the following encoding logic: +// Is the name of the second source scalable vector register, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:21) +func encodeZm1621V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 16, true +} + +// encodeZm510V1 is the implementation of the following encoding logic: +// Is the name of the second source scalable vector register, encoded in the "Zm" field. +// bit range mappings: +// Zm: [5:10) +func encodeZm510V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v & 31) << 5, true +} + +// encodeZn510Table2 is the implementation of the following encoding logic: +// Is the name of the second table vector register, encoded as "Zn" plus 1 modulo 32. +// bit range mappings: +// Zn: [5:10) +func encodeZn510Table2(v uint32) (uint32, bool) { + return ((v - 1) & 0x1f) << 5, true +} + +// encodePdnSrcDst is the implementation of the following encoding logic: +// Is the name of the source and destination scalable predicate register, encoded in the "Pdn" field. +// bit range mappings: +// Pdn: [0:4) +func encodePdnSrcDst(v uint32) (uint32, bool) { + return v, true +} + +// encodeZdnSrcDst is the implementation of the following encoding logic: +// Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. +// bit range mappings: +// Zdn: [0:5) +func encodeZdnSrcDst(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v, true +} + +// encodePm59V1 is the implementation of the following encoding logic: +// Is the name of the source scalable predicate register, encoded in the "Pm" field. +// bit range mappings: +// Pm: [5:9) +func encodePm59V1(v uint32) (uint32, bool) { + return v << 5, true +} + +// encodePn59V2 is the implementation of the following encoding logic: +// Is the name of the source scalable predicate register, encoded in the "Pn" field. +// bit range mappings: +// Pn: [5:9) +func encodePn59V2(v uint32) (uint32, bool) { + return v << 5, true +} + +// encodePNn59 is the implementation of the following encoding logic: +// Is the name of the source scalable predicate register, with predicate-as-counter encoding, encoded in the "PNn" field. +// bit range mappings: +// PNn: [5:9) +func encodePNn59(v uint32) (uint32, bool) { + if v > 15 { + return (v - 16) << 5, true + } + return 0, false +} + +// encodeZm1621V1 is the implementation of the following encoding logic: +// Is the name of the source scalable vector register, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:21) +func encodeZm1621V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 16, true +} + +// encodeZm510V2 is the implementation of the following encoding logic: +// Is the name of the source scalable vector register, encoded in the "Zm" field. +// bit range mappings: +// Zm: [5:10) +func encodeZm510V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v & 31) << 5, true +} + +// encodeZn510Src is the implementation of the following encoding logic: +// Is the name of the source scalable vector register, encoded in the "Zn" field. +// bit range mappings: +// Zn: [5:10) +func encodeZn510Src(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v & 31) << 5, true +} + +// encodeZn510Table3 is the implementation of the following encoding logic: +// Is the name of the table vector register, encoded in the "Zn" field. +// bit range mappings: +// Zn: [5:10) +func encodeZn510Table3(v uint32) (uint32, bool) { + return v << 5, true +} + +// encodeZt053 is the implementation of the following encoding logic: +// Is the name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32. +// bit range mappings: +// Zt: [0:5) +func encodeZt053(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v - 2) % 32, true +} + +// encodeZda3RdSrcDst is the implementation of the following encoding logic: +// Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. +// bit range mappings: +// Zda: [0:5) +func encodeZda3RdSrcDst(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v, true +} + +// encodeZa16213Rd is the implementation of the following encoding logic: +// Is the name of the third source scalable vector register, encoded in the "Za" field. +// bit range mappings: +// Za: [16:21) +func encodeZa16213Rd(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 16, true +} + +// encodeZa5103Rd is the implementation of the following encoding logic: +// Is the name of the third source scalable vector register, encoded in the "Za" field. +// bit range mappings: +// Za: [5:10) +func encodeZa5103Rd(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 5, true +} + +// encodeZk5103Rd is the implementation of the following encoding logic: +// Is the name of the third source scalable vector register, encoded in the "Zk" field. +// bit range mappings: +// Zk: [5:10) +func encodeZk5103Rd(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 5, true +} + +// encodePv1013 is the implementation of the following encoding logic: +// Is the name of the vector select predicate register P0-P7, encoded in the "Pv" field. +// bit range mappings: +// Pv: [10:13) +func encodePv1013(v uint32) (uint32, bool) { + return v << 10, true +} + +// encodePv1014 is the implementation of the following encoding logic: +// Is the name of the vector select predicate register, encoded in the "Pv" field. +// bit range mappings: +// Pv: [10:14) +func encodePv1014(v uint32) (uint32, bool) { + return v << 10, true +} + +// encodePv59 is the implementation of the following encoding logic: +// Is the name of the vector select predicate register, encoded in the "Pv" field. +// bit range mappings: +// Pv: [5:9) +func encodePv59(v uint32) (uint32, bool) { + return v << 5, true +} + +// encodeRd05ZR is the implementation of the following encoding logic: +// Is the number [0-30] of the destination general-purpose register or the name ZR (31), encoded in the "Rd" field. +// bit range mappings: +// Rd: [0:5) +func encodeRd05ZR(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + // ZR is just R31 + return v & 31, true +} + +// encodeRn510SPV1 is the implementation of the following encoding logic: +// Is the number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field. +// bit range mappings: +// Rn: [5:10) +func encodeRn510SPV1(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_R31 { + return 0, false + } + if v == REG_RSP { + return (REG_R31 & 31) << 5, true + } + return (v & 31) << 5, true +} + +// encodeRdn05ZR is the implementation of the following encoding logic: +// Is the number [0-30] of the source and destination general-purpose register or the name ZR (31), encoded in the "Rdn" field. +// bit range mappings: +// Rdn: [0:5) +func encodeRdn05ZR(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return v & 31, true +} + +// encodeRm1621ZR is the implementation of the following encoding logic: +// Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field. +// bit range mappings: +// Rm: [16:21) +func encodeRm1621ZR(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return (v & 31) << 16, true +} + +// encodeRm510ZR is the implementation of the following encoding logic: +// Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field. +// bit range mappings: +// Rm: [5:10) +func encodeRm510ZR(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return (v & 31) << 5, true +} + +// encodeRn510ZR is the implementation of the following encoding logic: +// Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field. +// bit range mappings: +// Rn: [5:10) +func encodeRn510ZR(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return (v & 31) << 5, true +} + +// encodeVd05 is the implementation of the following encoding logic: +// Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field. +// bit range mappings: +// Vd: [0:5) +func encodeVd05(v uint32) (uint32, bool) { + return v & 31, true +} + +// encodeVm510 is the implementation of the following encoding logic: +// Is the number [0-31] of the source SIMD&FP register, encoded in the "Vm" field. +// bit range mappings: +// Vm: [5:10) +func encodeVm510(v uint32) (uint32, bool) { + return (v & 31) << 5, true +} + +// encodeVn510 is the implementation of the following encoding logic: +// Is the number [0-31] of the source SIMD&FP register, encoded in the "Vn" field. +// bit range mappings: +// Vn: [5:10) +func encodeVn510(v uint32) (uint32, bool) { + return (v & 31) << 5, true +} + +// encodeVdn05 is the implementation of the following encoding logic: +// Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field. +// bit range mappings: +// Vdn: [0:5) +func encodeVdn05(v uint32) (uint32, bool) { + return v & 31, true +} + +// encodeRm1621XZR is the implementation of the following encoding logic: +// Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. +// bit range mappings: +// Rm: [16:21) +func encodeRm1621XZR(v uint32) (uint32, bool) { + if v == 0 { + // absent case, according to the spec this should be ZR (R31) + return 31, true + } + if !checkIsR(v) { + return 0, false + } + return (v & 31) << 16, true +} + +// encodeImm41620V1 is the implementation of the following encoding logic: +// Is the optional signed immediate byte offset, a multiple of 16 in the range -128 to 112, defaulting to 0, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm41620V1(v uint32) (uint32, bool) { + vi := int32(v) + if vi >= -128 && vi <= 112 && vi%16 == 0 { + return uint32((vi/16)&15) << 16, true + } + return 0, false +} + +// encodeImm41620V2 is the implementation of the following encoding logic: +// Is the optional signed immediate byte offset, a multiple of 32 in the range -256 to 224, defaulting to 0, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm41620V2(v uint32) (uint32, bool) { + vi := int32(v) + if vi >= -256 && vi <= 224 && vi%32 == 0 { + return uint32((vi/32)&15) << 16, true + } + return 0, false +} + +// encodeImm41620V6 is the implementation of the following encoding logic: +// Is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm41620V6(v uint32) (uint32, bool) { + if v&1 != 0 { + return 0, false + } + vi := int32(v) + if vi >= -16 && vi <= 14 { + return (uint32(vi/2) & 15) << 16, true + } + return 0, false +} + +// encodeImm41620V3 is the implementation of the following encoding logic: +// Is the optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm41620V3(v uint32) (uint32, bool) { + vi := int32(v) + if vi >= -24 && vi <= 21 && vi%3 == 0 { + return uint32((vi/3)&15) << 16, true + } + return 0, false +} + +// encodeImm41620V4 is the implementation of the following encoding logic: +// Is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm41620V4(v uint32) (uint32, bool) { + vi := int32(v) + if vi >= -32 && vi <= 28 && vi%4 == 0 { + return uint32((vi/4)&15) << 16, true + } + return 0, false +} + +// encodeImm9h1622L1013 is the implementation of the following encoding logic: +// Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields. +// bit range mappings: +// imm9h: [16:22) +// imm9l: [10:13) +func encodeImm9h1622L1013(v uint32) (uint32, bool) { + vi := int32(v) + if vi >= -256 && vi <= 255 { + val := uint32(vi) & 0x1FF + return ((val & 7) << 10) | ((val >> 3) << 16), true + } + return 0, false +} + +// encodeImm61622V5 is the implementation of the following encoding logic: +// Is the optional signed immediate vector offset, in the range -32 to 31, defaulting to 0, encoded in the "imm6" field. +// bit range mappings: +// imm6: [16:22) +func encodeImm61622V5(v uint32) (uint32, bool) { + vi := int32(v) + if vi >= -32 && vi <= 31 { + return (uint32(vi) & 0x3F) << 16, true + } + return 0, false +} + +// encodeImm41620V5 is the implementation of the following encoding logic: +// Is the optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm41620V5(v uint32) (uint32, bool) { + vi := int32(v) + if vi >= -8 && vi <= 7 { + return (uint32(vi) & 0xF) << 16, true + } + return 0, false +} + +// encodeImm61622V1 is the implementation of the following encoding logic: +// Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 126, defaulting to 0, encoded in the "imm6" field. +// bit range mappings: +// imm6: [16:22) +func encodeImm61622V1(v uint32) (uint32, bool) { + if v <= 126 && v%2 == 0 { + return (v / 2) << 16, true + } + return 0, false +} + +// encodeImm51621V1 is the implementation of the following encoding logic: +// Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field. +// bit range mappings: +// imm5: [16:21) +func encodeImm51621V1(v uint32) (uint32, bool) { + if v <= 62 && v%2 == 0 { + return (v / 2) << 16, true + } + return 0, false +} + +// encodeImm51621V2 is the implementation of the following encoding logic: +// Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field. +// bit range mappings: +// imm5: [16:21) +func encodeImm51621V2(v uint32) (uint32, bool) { + if v <= 124 && v%4 == 0 { + return (v / 4) << 16, true + } + return 0, false +} + +// encodeImm61622V2 is the implementation of the following encoding logic: +// Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 252, defaulting to 0, encoded in the "imm6" field. +// bit range mappings: +// imm6: [16:22) +func encodeImm61622V2(v uint32) (uint32, bool) { + if v <= 252 && v%4 == 0 { + return (v / 4) << 16, true + } + return 0, false +} + +// encodeImm51621V3 is the implementation of the following encoding logic: +// Is the optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 248, defaulting to 0, encoded in the "imm5" field. +// bit range mappings: +// imm5: [16:21) +func encodeImm51621V3(v uint32) (uint32, bool) { + if v <= 248 && v%8 == 0 { + return (v / 8) << 16, true + } + return 0, false +} + +// encodeImm61622V3 is the implementation of the following encoding logic: +// Is the optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 504, defaulting to 0, encoded in the "imm6" field. +// bit range mappings: +// imm6: [16:22) +func encodeImm61622V3(v uint32) (uint32, bool) { + if v <= 504 && v%8 == 0 { + return (v / 8) << 16, true + } + return 0, false +} + +// encodeImm51621V4 is the implementation of the following encoding logic: +// Is the optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field. +// bit range mappings: +// imm5: [16:21) +func encodeImm51621V4(v uint32) (uint32, bool) { + if v <= 31 { + return v << 16, true + } + return 0, false +} + +// encodeImm61622V4 is the implementation of the following encoding logic: +// Is the optional unsigned immediate byte offset, in the range 0 to 63, defaulting to 0, encoded in the "imm6" field. +// bit range mappings: +// imm6: [16:22) +func encodeImm61622V4(v uint32) (uint32, bool) { + if v <= 63 { + return v << 16, true + } + return 0, false +} + +// encodeI189 is the implementation of the following encoding logic: +// Is the portion index, in the range 0 to 1, encoded in the "i1" field. +// bit range mappings: +// i1: [8:9) +func encodeI189(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 8, true +} + +// encodeImm2_810 is the implementation of the following encoding logic: +// Is the portion index, in the range 0 to 3, encoded in the "imm2" field. +// bit range mappings: +// imm2: [8:10) +func encodeImm2_810(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 8, true +} + +// encodePredQualM1617 is the implementation of the following encoding logic: +// Is the predication qualifier, +// M +// 0 Z +// 1 M +// bit range mappings: +// M: [16:17) +func encodePredQualM1617(v uint32) (uint32, bool) { + switch v { + case PRED_Z: + return 0, true + case PRED_M: + return 1 << 16, true + } + return 0, false +} + +// encodePredQualM45 is the implementation of the following encoding logic: +// Is the predication qualifier, +// M +// 0 Z +// 1 M +// bit range mappings: +// M: [4:5) +func encodePredQualM45(v uint32) (uint32, bool) { + switch v { + case PRED_Z: + return 0, true + case PRED_M: + return 1 << 4, true + } + return 0, false +} + +// encodePrfop04 is the implementation of the following encoding logic: +// Is the prefetch operation specifier, +// prfop +// 0000 PLDL1KEEP +// 0001 PLDL1STRM +// 0010 PLDL2KEEP +// 0011 PLDL2STRM +// 0100 PLDL3KEEP +// 0101 PLDL3STRM +// x11x #uimm4 +// 1000 PSTL1KEEP +// 1001 PSTL1STRM +// 1010 PSTL2KEEP +// 1011 PSTL2STRM +// 1100 PSTL3KEEP +// 1101 PSTL3STRM +// bit range mappings: +// prfop: [0:4) +func encodePrfop04(v uint32) (uint32, bool) { + switch SpecialOperand(v) { + case SPOP_PLDL1KEEP: + return 0, true + case SPOP_PLDL1STRM: + return 1, true + case SPOP_PLDL2KEEP: + return 2, true + case SPOP_PLDL2STRM: + return 3, true + case SPOP_PLDL3KEEP: + return 4, true + case SPOP_PLDL3STRM: + return 5, true + case SPOP_PSTL1KEEP: + return 8, true + case SPOP_PSTL1STRM: + return 9, true + case SPOP_PSTL2KEEP: + return 10, true + case SPOP_PSTL2STRM: + return 11, true + case SPOP_PSTL3KEEP: + return 12, true + case SPOP_PSTL3STRM: + return 13, true + default: + return 0, false + } +} + +// encodeI21921 is the implementation of the following encoding logic: +// Is the round key index, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI21921(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + +// encodeImm5bSigned_1621 is the implementation of the following encoding logic: +// Is the second signed immediate operand, in the range -16 to 15, encoded in the "imm5b" field. +// bit range mappings: +// imm5b: [16:21) +func encodeImm5bSigned_1621(v uint32) (uint32, bool) { + if int32(v) >= -16 && int32(v) <= 15 { + return (v & 31) << 16, true + } + return 0, false +} + +// encodeImm8Signed_513 is the implementation of the following encoding logic: +// Is the signed immediate operand, in the range -128 to 127, encoded in the "imm8" field. +// bit range mappings: +// imm8: [5:13) +func encodeImm8Signed_513(v uint32) (uint32, bool) { + if int32(v) >= -128 && int32(v) <= 127 { + return (v & 255) << 5, true + } + return 0, false +} + +// encodeImm5Signed_1621V1 is the implementation of the following encoding logic: +// Is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. +// bit range mappings: +// imm5: [16:21) +func encodeImm5Signed_1621V1(v uint32) (uint32, bool) { + if int32(v) >= -16 && int32(v) <= 15 { + return (v & 31) << 16, true + } + return 0, false +} + +// encodeImm5Signed510Unique is the implementation of the following encoding logic: +// Is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. +// bit range mappings: +// imm5: [5:10) +func encodeImm5Signed510Unique(v uint32) (uint32, bool) { + if int32(v) >= -16 && int32(v) <= 15 { + return (v & 31) << 5, true + } + return 0, false +} + +// encodeImm6Signed_511 is the implementation of the following encoding logic: +// Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field. +// bit range mappings: +// imm6: [5:11) +func encodeImm6Signed_511(v uint32) (uint32, bool) { + if int32(v) >= -32 && int32(v) <= 31 { + return (v & 63) << 5, true + } + return 0, false +} + +// encodeSizeImm13NoOp is the implementation of the following encoding logic: +// Is the size specifier, +// imm13 +// 0xxxxxx0xxxxx S +// 0xxxxxx10xxxx H +// 0xxxxxx110xxx B +// 0xxxxxx1110xx B +// 0xxxxxx11110x B +// 0xxxxxx11111x RESERVED +// 1xxxxxxxxxxxx D +// bit range mappings: +// imm13: [5:18) +func encodeSizeImm13NoOp(v uint32) (uint32, bool) { + return codeNoOp, false +} + +// encodeSize2123V1 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 B +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [21:23) +func encodeSize2123V1(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 0, true + case ARNG_H: + return 1 << 21, true + case ARNG_S: + return 2 << 21, true + case ARNG_D: + return 3 << 21, true + default: + return 0, false + } +} + +// encodeSizeBHSD2224 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 B +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [22:24) +func encodeSizeBHSD2224(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 0 << 22, true + case ARNG_H: + return 1 << 22, true + case ARNG_S: + return 2 << 22, true + case ARNG_D: + return 3 << 22, true + } + return 0, false +} + +// encodeSizeBHS2224 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 B +// 01 H +// 10 S +// 11 RESERVED +// bit range mappings: +// size: [22:24) +func encodeSizeBHS2224(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 0 << 22, true + case ARNG_H: + return 1 << 22, true + case ARNG_S: + return 2 << 22, true + } + return 0, false +} + +// encodeSizeBHS2224Offset1 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 RESERVED +// 01 B +// 10 H +// 11 S +// bit range mappings: +// size: [22:24) +func encodeSizeBHS2224Offset1(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 22, true + case ARNG_H: + return 2 << 22, true + case ARNG_S: + return 3 << 22, true + } + return 0, false +} + +// encodeSizeHSD1315 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 RESERVED +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [13:15) +func encodeSizeHSD1315(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 13, true + case ARNG_S: + return 2 << 13, true + case ARNG_D: + return 3 << 13, true + } + return 0, false +} + +// encodeSizeHSD1719 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 RESERVED +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [17:19) +func encodeSizeHSD1719(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 17, true + case ARNG_S: + return 2 << 17, true + case ARNG_D: + return 3 << 17, true + } + return 0, false +} + +// encodeSize2123V2 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 RESERVED +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [21:23) +func encodeSize2123V2(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 21, true + case ARNG_S: + return 2 << 21, true + case ARNG_D: + return 3 << 21, true + } + return 0, false +} + +// encodeSizeHSD2224 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 RESERVED +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [22:24) +func encodeSizeHSD2224(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 22, true + case ARNG_S: + return 2 << 22, true + case ARNG_D: + return 3 << 22, true + } + return 0, false +} + +// encodeSizeHSD2224No00 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [22:24) +func encodeSizeHSD2224No00(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 22, true + case ARNG_S: + return 2 << 22, true + case ARNG_D: + return 3 << 22, true + } + return 0, false +} + +// encodeSizeHD2224 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 01 H +// 1x D +// bit range mappings: +// size: [22:24) +func encodeSizeHD2224(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 22, true + case ARNG_D: + return 3 << 22, true + } + return 0, false +} + +// encodeSizeTbBHSD2224 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 B +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [22:24) +func encodeSizeTbBHSD2224(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 0 << 22, true + case ARNG_H: + return 1 << 22, true + case ARNG_S: + return 2 << 22, true + case ARNG_D: + return 3 << 22, true + } + return 0, false +} + +// encodeSizeTbBHS2224 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 RESERVED +// 01 B +// 10 H +// 11 S +// bit range mappings: +// size: [22:24) +func encodeSizeTbBHS2224(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 22, true + case ARNG_H: + return 2 << 22, true + case ARNG_S: + return 3 << 22, true + } + return 0, false +} + +// encodeSizeTbHSD2224Offset1 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 RESERVED +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [22:24) +func encodeSizeTbHSD2224Offset1(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 22, true + case ARNG_S: + return 2 << 22, true + case ARNG_D: + return 3 << 22, true + } + return 0, false +} + +// encodeSizeTbBS2224 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 01 B +// 1x S +// bit range mappings: +// size: [22:24) +func encodeSizeTbBS2224(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 22, true + case ARNG_S: + return 3 << 22, true + } + return 0, false +} + +// encodeSize0BH2223 is the implementation of the following encoding logic: +// Is the size specifier, +// size[0] +// 0 B +// 1 H +// bit range mappings: +// size: [22:23) +func encodeSize0BH2223(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 0 << 22, true + case ARNG_H: + return 1 << 22, true + } + return 0, false +} + +// encodeSize0SD2223 is the implementation of the following encoding logic: +// Is the size specifier, +// size[0] +// 0 S +// 1 D +// bit range mappings: +// size: [22:23) +func encodeSize0SD2223(v uint32) (uint32, bool) { + switch v { + case ARNG_S: + return 0 << 22, true + case ARNG_D: + return 1 << 22, true + } + return 0, false +} + +// encodeSize0TbBH2223 is the implementation of the following encoding logic: +// Is the size specifier, +// size[0] +// 0 B +// 1 H +// bit range mappings: +// size: [22:23) +func encodeSize0TbBH2223(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 0 << 22, true + case ARNG_H: + return 1 << 22, true + } + return 0, false +} + +// encodeSzSD1415 is the implementation of the following encoding logic: +// Is the size specifier, +// sz +// 0 S +// 1 D +// bit range mappings: +// sz: [14:15) +func encodeSzSD1415(v uint32) (uint32, bool) { + switch v { + case ARNG_S: + return 0 << 14, true + case ARNG_D: + return 1 << 14, true + } + return 0, false +} + +// encodeSzSD1718 is the implementation of the following encoding logic: +// Is the size specifier, +// sz +// 0 S +// 1 D +// bit range mappings: +// sz: [17:18) +func encodeSzSD1718(v uint32) (uint32, bool) { + switch v { + case ARNG_S: + return 0 << 17, true + case ARNG_D: + return 1 << 17, true + } + return 0, false +} + +// encodeSz2122 is the implementation of the following encoding logic: +// Is the size specifier, +// sz +// 0 S +// 1 D +// bit range mappings: +// sz: [21:22) +func encodeSz2122(v uint32) (uint32, bool) { + switch v { + case ARNG_S: + return 0, true + case ARNG_D: + return 1 << 21, true + } + return 0, false +} + +// encodeSzSD2223 is the implementation of the following encoding logic: +// Is the size specifier, +// sz +// 0 S +// 1 D +// bit range mappings: +// sz: [22:23) +func encodeSzSD2223(v uint32) (uint32, bool) { + switch v { + case ARNG_S: + return 0 << 22, true + case ARNG_D: + return 1 << 22, true + } + return 0, false +} + +// encodeTsize1921V1 is the implementation of the following encoding logic: +// Is the size specifier, +// tsize +// 00 RESERVED +// 01 B +// 1x H +// bit range mappings: +// tsize: [19:21) +func encodeTsize1921V1(v uint32) (uint32, bool) { + if v == uint32(ARNG_B) { + return 1 << 19, true + } + if v == uint32(ARNG_H) { + return 2 << 19, true // 2 is bit pattern 10 (1x) + } + return 0, false +} + +// encodeTsize1921V2 is the implementation of the following encoding logic: +// Is the size specifier, +// tsize +// 00 RESERVED +// 01 H +// 1x S +// bit range mappings: +// tsize: [19:21) +func encodeTsize1921V2(v uint32) (uint32, bool) { + if v == uint32(ARNG_H) { + return 1 << 19, true + } + if v == uint32(ARNG_S) { + return 2 << 19, true // 2 is bit pattern 10 (1x) + } + return 0, false +} + +// encodeTsz_1620_SizeSpecifier4 is the implementation of the following encoding logic: +// Is the size specifier, +// tsz +// 0000 RESERVED +// xxx1 B +// xx10 H +// x100 S +// 1000 D +// bit range mappings: +// tsz: [16:20) +func encodeTsz_1620_SizeSpecifier4(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 16, true + case ARNG_H: + return 2 << 16, true + case ARNG_S: + return 4 << 16, true + case ARNG_D: + return 8 << 16, true + } + return 0, false +} + +// encodeTsz_1621_SizeSpecifier5 is the implementation of the following encoding logic: +// Is the size specifier, +// tsz +// 00000 RESERVED +// xxxx1 B +// xxx10 H +// xx100 S +// x1000 D +// 10000 Q +// bit range mappings: +// tsz: [16:21) +func encodeTsz_1621_SizeSpecifier5(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 16, true + case ARNG_H: + return 2 << 16, true + case ARNG_S: + return 4 << 16, true + case ARNG_D: + return 8 << 16, true + case ARNG_Q: + return 16 << 16, true + } + return 0, false +} + +// encodeTszhTszlBHS is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl +// 0 00 RESERVED +// 0 01 B +// 0 10 H +// 0 11 RESERVED +// 1 00 S +// 1 01 RESERVED +// 1 1x RESERVED +// bit range mappings: +// tszh: [22:23) +// tszl: [19:21) +func encodeTszhTszlBHS(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 0<<22 | 1<<19, true + case ARNG_H: + return 0<<22 | 2<<19, true + case ARNG_S: + return 1 << 22, true + } + return 0, false +} + +// encodeSizeBhsTsz1921 is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl +// 0 00 RESERVED +// 0 01 B +// 0 1x H +// 1 xx S +// bit range mappings: +// tszh: [22:23) +// tszl: [19:21) +func encodeSizeBhsTsz1921(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 19, true + case ARNG_H: + return 2 << 19, true + case ARNG_S: + return 1 << 22, true + } + return 0, false +} + +// encodeSizeHsdTsz1921 is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl +// 0 00 RESERVED +// 0 01 H +// 0 1x S +// 1 xx D +// bit range mappings: +// tszh: [22:23) +// tszl: [19:21) +func encodeSizeHsdTsz1921(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 19, true + case ARNG_S: + return 2 << 19, true + case ARNG_D: + return 1 << 22, true + } + return 0, false +} + +// encodeSizeBhsdTsz1921 is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl +// 00 00 RESERVED +// 00 01 B +// 00 1x H +// 01 xx S +// 1x xx D +// bit range mappings: +// tszh: [22:24) +// tszl: [19:21) +func encodeSizeBhsdTsz1921(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 19, true + case ARNG_H: + return 2 << 19, true + case ARNG_S: + return 1 << 22, true + case ARNG_D: + return 1 << 23, true + } + return 0, false +} + +// encodeSizeBhsdTsz810 is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl +// 00 00 RESERVED +// 00 01 B +// 00 1x H +// 01 xx S +// 1x xx D +// bit range mappings: +// tszh: [22:24) +// tszl: [8:10) +func encodeSizeBhsdTsz810(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 8, true + case ARNG_H: + return 2 << 8, true + case ARNG_S: + return 1 << 22, true + case ARNG_D: + return 1 << 23, true + } + return 0, false +} + +// encodeSizeBhsTsz1921Unique is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl +// 0 00 RESERVED +// 0 01 B +// 0 1x H +// 1 xx S +// bit range mappings: +// tszh: [22:23) +// tszl: [19:21) +func encodeSizeBhsTsz1921Unique(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 19, true + case ARNG_H: + return 2 << 19, true + case ARNG_S: + return 1 << 22, true + } + return 0, false +} + +// encodeTszhTszlTbHSD is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl +// 0 00 RESERVED +// 0 01 H +// 0 10 S +// 0 11 RESERVED +// 1 00 D +// 1 01 RESERVED +// 1 1x RESERVED +// bit range mappings: +// tszh: [22:23) +// tszl: [19:21) +func encodeTszhTszlTbHSD(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 0<<22 | 1<<19, true + case ARNG_S: + return 0<<22 | 2<<19, true + case ARNG_D: + return 1 << 22, true + } + return 0, false +} + +// encodeSizeHsdTsz1921Unique is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl +// 0 00 RESERVED +// 0 01 H +// 0 1x S +// 1 xx D +// bit range mappings: +// tszh: [22:23) +// tszl: [19:21) +func encodeSizeHsdTsz1921Unique(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 19, true + case ARNG_S: + return 2 << 19, true + case ARNG_D: + return 1 << 22, true + } + return 0, false +} + +// encodeImm4Unsigned_1620 is the implementation of the following encoding logic: +// Is the unsigned immediate operand, in the range 0 to 15, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm4Unsigned_1620(v uint32) (uint32, bool) { + if v <= 15 { + return v << 16, true + } + return 0, false +} + +// encodeImm8Unsigned_513 is the implementation of the following encoding logic: +// Is the unsigned immediate operand, in the range 0 to 255, encoded in the "imm8" field. +// bit range mappings: +// imm8: [5:13) +func encodeImm8Unsigned_513(v uint32) (uint32, bool) { + if v <= 255 { + return v << 5, true + } + return 0, false +} + +// encodeImm8hImm8l_Unsigned is the implementation of the following encoding logic: +// Is the unsigned immediate operand, in the range 0 to 255, encoded in the "imm8h:imm8l" fields. +// bit range mappings: +// imm8h: [16:21) +// imm8l: [10:13) +func encodeImm8hImm8l_Unsigned(v uint32) (uint32, bool) { + if v <= 255 { + l := v & 7 + h := v >> 3 + return (l << 10) | (h << 16), true + } + return 0, false +} + +// encodeImm3Unsigned_1619 is the implementation of the following encoding logic: +// Is the unsigned immediate operand, in the range 0 to 7, encoded in the "imm3" field. +// bit range mappings: +// imm3: [16:19) +func encodeImm3Unsigned_1619(v uint32) (uint32, bool) { + if v <= 7 { + return v << 16, true + } + return 0, false +} + +// encodeI12324 is the implementation of the following encoding logic: +// Is the vector segment index, in the range 0 to 1, encoded in the "i1" field. +// bit range mappings: +// i1: [23:24) +func encodeI12324(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 23, true +} + +// encodeVl1011 is the implementation of the following encoding logic: +// Is the vl specifier, +// vl +// 0 VLx2 +// 1 VLx4 +// bit range mappings: +// vl: [10:11) +func encodeVl1011(v uint32) (uint32, bool) { + switch SpecialOperand(v) { + case SPOP_VLx2: + return 0, true + case SPOP_VLx4: + return 1 << 10, true + default: + return 0, false + } +} + +// encodeVl1314 is the implementation of the following encoding logic: +// Is the vl specifier, +// vl +// 0 VLx2 +// 1 VLx4 +// bit range mappings: +// vl: [13:14) +func encodeVl1314(v uint32) (uint32, bool) { + switch SpecialOperand(v) { + case SPOP_VLx2: + return 0, true + case SPOP_VLx4: + return 1 << 13, true + default: + return 0, false + } +} + +// encodeNoop is the implementation of the following encoding logic: +// No-op check, returns true +func encodeNoop(v uint32) (uint32, bool) { + return 0, true +} diff --git a/src/cmd/internal/obj/arm64/goops_gen.go b/src/cmd/internal/obj/arm64/goops_gen.go new file mode 100644 index 00000000000000..1b599e201b2e53 --- /dev/null +++ b/src/cmd/internal/obj/arm64/goops_gen.go @@ -0,0 +1,705 @@ +// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT. + +package arm64 + +import "cmd/internal/obj" + +const ( + AADDPL obj.As = ASVESTART + 1 + iota + AADDVL + ACTERMEQ + ACTERMEQW + ACTERMNE + ACTERMNEW + APAND + APANDS + APBIC + APBICS + APBRKA + APBRKAS + APBRKB + APBRKBS + APBRKN + APBRKNS + APBRKPA + APBRKPAS + APBRKPB + APBRKPBS + APCNTP + APDECP + APEOR + APEORS + APFIRSTP + APINCP + APLASTP + APLDR + APNAND + APNANDS + APNOR + APNORS + APORN + APORNS + APORR + APORRS + APPEXT + APPFALSE + APPFIRST + APPNEXT + APPRFB + APPRFD + APPRFH + APPRFW + APPTEST + APPTRUE + APPUNPKHI + APPUNPKLO + APRDFFR + APRDFFRS + APREV + APSEL + APSQDECP + APSQDECPW + APSQINCP + APSQINCPW + APSTR + APTRN1 + APTRN2 + APUQDECP + APUQDECPW + APUQINCP + APUQINCPW + APUZP1 + APUZP2 + APWHILEGE + APWHILEGEW + APWHILEGT + APWHILEGTW + APWHILEHI + APWHILEHIW + APWHILEHS + APWHILEHSW + APWHILELE + APWHILELEW + APWHILELO + APWHILELOW + APWHILELS + APWHILELSW + APWHILELT + APWHILELTW + APWHILERW + APWHILEWR + APWRFFR + APZIP1 + APZIP2 + ARDVL + ASETFFR + AZABS + AZADCLB + AZADCLT + AZADD + AZADDHNB + AZADDHNT + AZADDP + AZADDPT + AZADDQP + AZADDQV + AZADDSUBP + AZADR + AZAESD + AZAESDIMC + AZAESE + AZAESEMC + AZAESIMC + AZAESMC + AZAND + AZANDQV + AZANDVB + AZANDVD + AZANDVH + AZANDVS + AZASR + AZASRD + AZASRR + AZBCAX + AZBDEP + AZBEXT + AZBF1CVT + AZBF1CVTLT + AZBF2CVT + AZBF2CVTLT + AZBFADD + AZBFCLAMP + AZBFCVT + AZBFCVTN + AZBFCVTNT + AZBFDOT + AZBFMAX + AZBFMAXNM + AZBFMIN + AZBFMINNM + AZBFMLA + AZBFMLALB + AZBFMLALT + AZBFMLS + AZBFMLSLB + AZBFMLSLT + AZBFMMLA + AZBFMUL + AZBFSCALE + AZBFSUB + AZBGRP + AZBIC + AZBSL + AZBSL1N + AZBSL2N + AZCADD + AZCDOT + AZCLASTA + AZCLASTAB + AZCLASTAD + AZCLASTAH + AZCLASTAS + AZCLASTAW + AZCLASTB + AZCLASTBB + AZCLASTBD + AZCLASTBH + AZCLASTBS + AZCLASTBW + AZCLS + AZCLZ + AZCMLA + AZCMPEQ + AZCMPGE + AZCMPGT + AZCMPHI + AZCMPHS + AZCMPLE + AZCMPLO + AZCMPLS + AZCMPLT + AZCMPNE + AZCNOT + AZCNT + AZCOMPACT + AZCPY + AZCPYB + AZCPYD + AZCPYH + AZCPYS + AZCPYW + AZDECP + AZDUP + AZDUPM + AZDUPQ + AZDUPW + AZEOR + AZEOR3 + AZEORBT + AZEORQV + AZEORTB + AZEORVB + AZEORVD + AZEORVH + AZEORVS + AZEXPAND + AZEXT + AZEXTQ + AZF1CVT + AZF1CVTLT + AZF2CVT + AZF2CVTLT + AZFABD + AZFABS + AZFACGE + AZFACGT + AZFADD + AZFADDAD + AZFADDAH + AZFADDAS + AZFADDP + AZFADDQV + AZFADDVD + AZFADDVH + AZFADDVS + AZFAMAX + AZFAMIN + AZFCADD + AZFCLAMP + AZFCMEQ + AZFCMGE + AZFCMGT + AZFCMLA + AZFCMLE + AZFCMLT + AZFCMNE + AZFCMUO + AZFCPY + AZFCVT + AZFCVTLT + AZFCVTN + AZFCVTNB + AZFCVTNT + AZFCVTX + AZFCVTXNT + AZFCVTZS + AZFCVTZSN + AZFCVTZU + AZFCVTZUN + AZFDIV + AZFDIVR + AZFDOT + AZFDUP + AZFEXPA + AZFLOGB + AZFMAD + AZFMAX + AZFMAXNM + AZFMAXNMP + AZFMAXNMQV + AZFMAXNMVD + AZFMAXNMVH + AZFMAXNMVS + AZFMAXP + AZFMAXQV + AZFMAXVD + AZFMAXVH + AZFMAXVS + AZFMIN + AZFMINNM + AZFMINNMP + AZFMINNMQV + AZFMINNMVD + AZFMINNMVH + AZFMINNMVS + AZFMINP + AZFMINQV + AZFMINVD + AZFMINVH + AZFMINVS + AZFMLA + AZFMLALB + AZFMLALLBB + AZFMLALLBT + AZFMLALLTB + AZFMLALLTT + AZFMLALT + AZFMLS + AZFMLSLB + AZFMLSLT + AZFMMLA + AZFMSB + AZFMUL + AZFMULX + AZFNEG + AZFNMAD + AZFNMLA + AZFNMLS + AZFNMSB + AZFRECPE + AZFRECPS + AZFRECPX + AZFRINT32X + AZFRINT32Z + AZFRINT64X + AZFRINT64Z + AZFRINTA + AZFRINTI + AZFRINTM + AZFRINTN + AZFRINTP + AZFRINTX + AZFRINTZ + AZFRSQRTE + AZFRSQRTS + AZFSCALE + AZFSQRT + AZFSUB + AZFSUBR + AZFTMAD + AZFTSMUL + AZFTSSEL + AZHISTCNT + AZHISTSEG + AZINCP + AZINDEX + AZINDEXW + AZINSR + AZINSRB + AZINSRD + AZINSRH + AZINSRS + AZINSRW + AZLASTA + AZLASTAB + AZLASTAD + AZLASTAH + AZLASTAS + AZLASTAW + AZLASTB + AZLASTBB + AZLASTBD + AZLASTBH + AZLASTBS + AZLASTBW + AZLD1B + AZLD1D + AZLD1H + AZLD1Q + AZLD1RB + AZLD1RD + AZLD1RH + AZLD1ROB + AZLD1ROD + AZLD1ROH + AZLD1ROW + AZLD1RQB + AZLD1RQD + AZLD1RQH + AZLD1RQW + AZLD1RSB + AZLD1RSH + AZLD1RSW + AZLD1RW + AZLD1SB + AZLD1SH + AZLD1SW + AZLD1W + AZLD2B + AZLD2D + AZLD2H + AZLD2Q + AZLD2W + AZLD3B + AZLD3D + AZLD3H + AZLD3Q + AZLD3W + AZLD4B + AZLD4D + AZLD4H + AZLD4Q + AZLD4W + AZLDFF1B + AZLDFF1D + AZLDFF1H + AZLDFF1SB + AZLDFF1SH + AZLDFF1SW + AZLDFF1W + AZLDNF1B + AZLDNF1D + AZLDNF1H + AZLDNF1SB + AZLDNF1SH + AZLDNF1SW + AZLDNF1W + AZLDNT1B + AZLDNT1D + AZLDNT1H + AZLDNT1SB + AZLDNT1SH + AZLDNT1SW + AZLDNT1W + AZLDR + AZLSL + AZLSLR + AZLSR + AZLSRR + AZLUTI2 + AZLUTI4 + AZLUTI6 + AZMAD + AZMADPT + AZMATCH + AZMLA + AZMLAPT + AZMLS + AZMOVPRFX + AZMSB + AZMUL + AZNBSL + AZNEG + AZNMATCH + AZNOT + AZORQV + AZORR + AZORVB + AZORVD + AZORVH + AZORVS + AZPMLAL + AZPMOV + AZPMUL + AZPMULL + AZPMULLB + AZPMULLT + AZPRFB + AZPRFD + AZPRFH + AZPRFW + AZRADDHNB + AZRADDHNT + AZRAX1 + AZRBIT + AZREV + AZREVB + AZREVD + AZREVH + AZREVW + AZRSHRNB + AZRSHRNT + AZRSUBHNB + AZRSUBHNT + AZSABA + AZSABAL + AZSABALB + AZSABALT + AZSABD + AZSABDLB + AZSABDLT + AZSADALP + AZSADDLB + AZSADDLBT + AZSADDLT + AZSADDVD + AZSADDWB + AZSADDWT + AZSBCLB + AZSBCLT + AZSCLAMP + AZSCVTF + AZSCVTFLT + AZSDIV + AZSDIVR + AZSDOT + AZSEL + AZSHADD + AZSHRNB + AZSHRNT + AZSHSUB + AZSHSUBR + AZSLI + AZSM4E + AZSM4EKEY + AZSMAX + AZSMAXP + AZSMAXQV + AZSMAXVB + AZSMAXVD + AZSMAXVH + AZSMAXVS + AZSMIN + AZSMINP + AZSMINQV + AZSMINVB + AZSMINVD + AZSMINVH + AZSMINVS + AZSMLALB + AZSMLALT + AZSMLSLB + AZSMLSLT + AZSMMLA + AZSMULH + AZSMULLB + AZSMULLT + AZSPLICE + AZSQABS + AZSQADD + AZSQCADD + AZSQCVTN + AZSQCVTUN + AZSQDECP + AZSQDMLALB + AZSQDMLALBT + AZSQDMLALT + AZSQDMLSLB + AZSQDMLSLBT + AZSQDMLSLT + AZSQDMULH + AZSQDMULLB + AZSQDMULLT + AZSQINCP + AZSQNEG + AZSQRDCMLAH + AZSQRDMLAH + AZSQRDMLSH + AZSQRDMULH + AZSQRSHL + AZSQRSHLR + AZSQRSHRN + AZSQRSHRNB + AZSQRSHRNT + AZSQRSHRUN + AZSQRSHRUNB + AZSQRSHRUNT + AZSQSHL + AZSQSHLR + AZSQSHLU + AZSQSHRN + AZSQSHRNB + AZSQSHRNT + AZSQSHRUN + AZSQSHRUNB + AZSQSHRUNT + AZSQSUB + AZSQSUBR + AZSQXTNB + AZSQXTNT + AZSQXTUNB + AZSQXTUNT + AZSRHADD + AZSRI + AZSRSHL + AZSRSHLR + AZSRSHR + AZSRSRA + AZSSHLLB + AZSSHLLT + AZSSRA + AZSSUBLB + AZSSUBLBT + AZSSUBLT + AZSSUBLTB + AZSSUBWB + AZSSUBWT + AZST1B + AZST1D + AZST1H + AZST1Q + AZST1W + AZST2B + AZST2D + AZST2H + AZST2Q + AZST2W + AZST3B + AZST3D + AZST3H + AZST3Q + AZST3W + AZST4B + AZST4D + AZST4H + AZST4Q + AZST4W + AZSTNT1B + AZSTNT1D + AZSTNT1H + AZSTNT1W + AZSTR + AZSUB + AZSUBHNB + AZSUBHNT + AZSUBP + AZSUBPT + AZSUBR + AZSUDOT + AZSUNPKHI + AZSUNPKLO + AZSUQADD + AZSXTB + AZSXTH + AZSXTW + AZTBL + AZTBLQ + AZTBX + AZTBXQ + AZTRN1 + AZTRN2 + AZUABA + AZUABAL + AZUABALB + AZUABALT + AZUABD + AZUABDLB + AZUABDLT + AZUADALP + AZUADDLB + AZUADDLT + AZUADDVD + AZUADDWB + AZUADDWT + AZUCLAMP + AZUCVTF + AZUCVTFLT + AZUDIV + AZUDIVR + AZUDOT + AZUHADD + AZUHSUB + AZUHSUBR + AZUMAX + AZUMAXP + AZUMAXQV + AZUMAXVB + AZUMAXVD + AZUMAXVH + AZUMAXVS + AZUMIN + AZUMINP + AZUMINQV + AZUMINVB + AZUMINVD + AZUMINVH + AZUMINVS + AZUMLALB + AZUMLALT + AZUMLSLB + AZUMLSLT + AZUMMLA + AZUMULH + AZUMULLB + AZUMULLT + AZUQADD + AZUQCVTN + AZUQDECP + AZUQINCP + AZUQRSHL + AZUQRSHLR + AZUQRSHRN + AZUQRSHRNB + AZUQRSHRNT + AZUQSHL + AZUQSHLR + AZUQSHRN + AZUQSHRNB + AZUQSHRNT + AZUQSUB + AZUQSUBR + AZUQXTNB + AZUQXTNT + AZURECPE + AZURHADD + AZURSHL + AZURSHLR + AZURSHR + AZURSQRTE + AZURSRA + AZUSDOT + AZUSHLLB + AZUSHLLT + AZUSMMLA + AZUSQADD + AZUSRA + AZUSUBLB + AZUSUBLT + AZUSUBWB + AZUSUBWT + AZUUNPKHI + AZUUNPKLO + AZUXTB + AZUXTH + AZUXTW + AZUZP1 + AZUZP2 + AZUZPQ1 + AZUZPQ2 + AZXAR + AZZIP1 + AZZIP2 + AZZIPQ1 + AZZIPQ2 + ALAST +) diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go new file mode 100644 index 00000000000000..03b35155f536a7 --- /dev/null +++ b/src/cmd/internal/obj/arm64/inst.go @@ -0,0 +1,896 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package arm64 + +import ( + "cmd/internal/obj" + "fmt" + "iter" + "math" + "math/bits" +) + +// instEncoder represents an instruction encoder. +type instEncoder struct { + goOp obj.As // Go opcode mnemonic + fixedBits uint32 // Known bits + args []operand // Operands, in Go order +} + +type varBits struct { + // The low and high bit index in the binary encoding, exclusive on hi + lo, hi int + encoded bool // If true then its value is already encoded + bits uint32 +} + +// component is the component of an binary encoding. +// e.g. for operand ., 's encoding function might be described as: +// +// For the "Byte and halfword" variant: is the size specifier, +// sz +// 0 B +// 1 H +// bit range mappings: +// sz: [22:23) +// +// Then sz is the component of the binary encoding. +type component uint16 + +type elemEncoder struct { + fn func(uint32) (uint32, bool) + // comp is the component of the binary encoding. + comp component +} + +// operand is the operand type of an instruction. +type operand struct { + class AClass // Operand class, register, constant, memory operation etc. + // The elements that this operand includes, this only includes the encoding-related parts + // They are represented as a list of pointers to the encoding functions. + // The first returned value is the encoded binary, the second is the ok signal. + // The encoding functions return the ok signal for deduplication purposes: + // For example: + // SDOT ., ., . + // SDOT .H, .B, .B + // SDOT .S, .H, .H + // + // and are specified in the encoding text, that there is a constraint "T = 4*Tb". + // We don't know this fact by looking at the encoding format solely, without this information + // the first encoding domain entails the other 2. And at instruction matching phase we simply + // cannot deduplicate them. So we defer this deduplication to the encoding phase. + // We need the ok signal with [elemEncoder.comp] field to deduplicate them. + elemEncoders []elemEncoder +} + +// opsInProg returns an iterator over the operands ([Addr]) of p +func opsInProg(p *obj.Prog) iter.Seq[*obj.Addr] { + return func(yield func(*obj.Addr) bool) { + // Go order: From, Reg, RestArgs..., To + // For SVE, Reg is unused as it's so common that registers have arrangements. + if p.From.Type != obj.TYPE_NONE { + if !yield(&p.From) { + return + } + } + for j := range p.RestArgs { + if !yield(&p.RestArgs[j].Addr) { + return + } + } + if p.To.Type != obj.TYPE_NONE { + if !yield(&p.To) { + return + } + } + } +} + +// aclass returns the AClass of an Addr. +func aclass(a *obj.Addr) AClass { + if a.Type == obj.TYPE_REG { + if a.Offset&(int64(1)<<62) != 0 { + return AC_PREGSEL + } + if a.Reg >= REG_Z0 && a.Reg <= REG_Z31 { + return AC_ZREG + } + if a.Reg >= REG_P0 && a.Reg <= REG_PN15 { + return AC_PREG + } + if a.Reg >= REG_ARNG && a.Reg < REG_ELEM { + return AC_ARNG + } + if a.Reg >= REG_ZARNG && a.Reg < REG_ZARNGELEM { + return AC_ARNG + } + if a.Reg >= REG_ZARNGELEM && a.Reg < REG_PZELEM { + return AC_ARNGIDX + } + if a.Reg >= REG_PZELEM && a.Reg < REG_PARNGZM { + if a.Reg&(1<<5) == 0 { + return AC_ZREGIDX + } else { + return AC_PREGIDX + } + } + if a.Reg >= REG_PARNGZM && a.Reg < REG_PARNGZM_END { + switch (a.Reg >> 5) & 15 { + case PRED_M, PRED_Z: + return AC_PREGZM + default: + return AC_ARNG + } + } + if a.Reg >= REG_V0 && a.Reg <= REG_V31 { + return AC_VREG + } + if a.Reg >= REG_R0 && a.Reg <= REG_R31 || a.Reg == REG_RSP { + return AC_SPZGREG + } + } + if a.Type == obj.TYPE_CONST || a.Type == obj.TYPE_FCONST { + return AC_IMM + } + if a.Type == obj.TYPE_REGLIST { + if a.Scale > 0 { + return AC_REGLIST_RANGE + } + switch (a.Offset >> 12) & 0xf { + case 0x7: + return AC_REGLIST1 + case 0xa: + return AC_REGLIST2 + case 0x6: + return AC_REGLIST3 + case 0x2: + return AC_REGLIST4 + } + } + if a.Type == obj.TYPE_MEM { + if a.Index == 0 { + if a.Scale&-32768 != 0 { + return AC_MEMOFFMULVL + } + return AC_MEMOFF + } + return AC_MEMEXT + } + if a.Type == obj.TYPE_SPECIAL { + return AC_SPECIAL + } + panic(fmt.Errorf("unknown AClass, addr = %v\n", a)) +} + +// addrComponent returns the binary (component) of the stored element in a at index, for operand +// of type aclass. +// +// For example, for operand of type AC_ARNG, it has 2 permissible components (identified by index) +// 0. register: +// 1. arrangement: +// +// They are stored in a.Reg as: +// +// reg | (arrangement << 5) +// +// More details are in the comments in the switch cases of this function. +func addrComponent(a *obj.Addr, acl AClass, index int) uint32 { + switch acl { + // AClass: AC_PREGSEL + // GNU mnemonic: .[, ] + // Go mnemonic: + // [selreg, $idximm](preg.T) + // Encoding: + // Type = TYPE_REG + // Offset = packed bits: preg (5 bits) | T (4 bits) | selreg (5 bits) | idximm (6 bits) | sentinel (bit 62) + case AC_PREGSEL: + switch index { + case 0: + return uint32(a.Offset & 31) + case 1: + return uint32((a.Offset >> 5) & 15) + case 2: + return uint32((a.Offset>>9)&31 + REG_R0) // encoding functions assume a ARM64 register + case 3: + // This is to check the width of selreg, which is guaranteed to be W in AC_PREGSEL. + // W check always returns true as it's resolved in the generator already. + // So we just return a default value 0 here. + return 0 + case 4: + return uint32((a.Offset >> 14) & 63) + default: + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + // AClass: AC_ARNG, AC_PREG, AC_PREGZ, AC_PREGM, AC_ZREG + // GNU mnemonic: . Or / (T is M or Z) + // Go mnemonic: + // reg. + // Encoding: + // Type = TYPE_REG + // Reg = reg | (arrangement or predication << 5) + case AC_ARNG, AC_PREG, AC_PREGZM, AC_ZREG: + switch index { + case 0: + return uint32(a.Reg & 31) + case 1: + return uint32((a.Reg >> 5) & 15) + default: + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + // AClass: AC_ARNGIDX, AC_PREGIDX, AC_ZREGIDX + // GNU mnemonic: .[] + // Go mnemonic: + // reg.T[index] + // Encoding: + // Type = TYPE_REG + // Reg = reg | (arrangement << 5) + // Index = index + case AC_ARNGIDX, AC_PREGIDX, AC_ZREGIDX: + switch index { + case 0: + return uint32(a.Reg & 31) + case 1: + // Arrangement + return uint32((a.Reg >> 5) & 15) + case 2: + // Index + return uint32(a.Index) + default: + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + // AClass: AC_SPZGREG, AC_VREG + // GNU mnemonic: + // Go mnemonic: + // reg (the width is already represented in the opcode) + // Encoding: + // Type = TYPE_REG + // Reg = reg + case AC_SPZGREG, AC_VREG: + switch index { + case 0: + // These are all width checks, they should map to no-op checks altogether. + return 0 + case 1: + return uint32(a.Reg) + default: + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + // AClass: AC_IMM + // GNU mnemonic: , + // Go mnemonic: + // $imm<> 32 & 0b11 + sum := 32 + if prefix == 2 { + sum = 16 + } + switch acl { + case AC_REGLIST1: + if index > 2 { + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + case AC_REGLIST2: + if index > 4 { + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + case AC_REGLIST3: + if index > 6 { + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + case AC_REGLIST4: + if index > 8 { + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + case AC_REGLIST_RANGE: + // It behaves just like a AC_REGLIST2 + if index > 4 { + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + } + switch index % 2 { + case 0: + // register + if a.Scale > 0 { + // For register ranges in SVE we allow discontiguous registers. + return uint32((firstReg + (index/2)*int(a.Scale)) % sum) + } + return uint32((firstReg + index/2) % sum) + case 1: + // arrangement + curQ := a.Offset >> 30 & 0b11 + curSize := a.Offset >> 10 & 0b11 + switch curQ { + case 0: + switch curSize { + case 0: + return ARNG_8B + case 1: + return ARNG_4H + case 2: + return ARNG_2S + case 3: + return ARNG_1D + default: + panic(fmt.Errorf("unknown size value at %d in AClass %d", index, acl)) + } + case 1: + switch curSize { + case 0: + return ARNG_16B + case 1: + return ARNG_8H + case 2: + return ARNG_4S + case 3: + return ARNG_2D + default: + panic(fmt.Errorf("unknown size value at %d in AClass %d", index, acl)) + } + case 2: + switch curSize { + case 1: + return ARNG_B + case 2: + return ARNG_H + case 3: + return ARNG_S + default: + panic(fmt.Errorf("unknown size value at %d in AClass %d", index, acl)) + } + case 3: + switch curSize { + case 1: + return ARNG_D + case 2: + return ARNG_Q + default: + panic(fmt.Errorf("unknown size value at %d in AClass %d", index, acl)) + } + default: + panic(fmt.Errorf("unknown Q value at %d in AClass %d", index, acl)) + } + default: + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + // AClass: AC_SPECIAL + // GNU mnemonic: + // Go mnemonic: + // special + // Encoding: + // Type = TYPE_SPECIAL + // Offset = SpecialOperand enum value + case AC_SPECIAL: + switch index { + case 0: + return uint32(a.Offset) + default: + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + // AClass: AC_MEMOFF, AC_MEMOFFMULVL + // GNU mnemonic: [., #] + // Go mnemonic: + // imm(reg.T) + // Encoding: + // Type = TYPE_MEM + // Reg = Base register (with arrangement if applicable) + // Offset = Immediate offset + case AC_MEMOFF, AC_MEMOFFMULVL: + switch index { + case 0: + return uint32(a.Reg & 31) + case 1: + return uint32((a.Reg >> 5) & 15) + case 2: + return uint32(a.Offset) + default: + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + // AClass: AC_MEMEXT + // GNU mnemonic: [., ., ] + // Go mnemonic: + // (reg2.T2.mod<> 5) & 15) + case 2: + return uint32(a.Reg) + case 3: + return uint32((a.Reg >> 5) & 15) + case 4: + // mod is either 1 (UXTW), 2 (SXTW), or 4 (LSL) + mod := uint32((a.Scale >> 9) & 0x7) + amount := uint32((a.Scale >> 12) & 0x7) + if mod == 0 && amount > 0 { + // LSL is implied when no extension is specified but amount > 0 + mod |= 1 << 2 + } + return mod + case 5: + return uint32((a.Scale >> 12) & 0x7) + default: + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } + } + // TODO: handle more AClasses. + panic(fmt.Errorf("unknown AClass %d", acl)) +} + +var codeI1Tsz uint32 = 0xffffffff +var codeImm2Tsz uint32 = 0xfffffffe +var codeShift161919212223 uint32 = 0xfffffffd +var codeShift161919212224 uint32 = 0xfffffffc +var codeShift588102224 uint32 = 0xfffffffb +var codeLogicalImmArrEncoding uint32 = 0xfffffffa +var codeImm3Tsize1621 uint32 = 0xfffffff9 +var codeShiftI1TszhTszl uint32 = 0xfffffff8 +var codeNoOp uint32 = 0xfffffff7 + +// encodeI1Tsz is the implementation of the following encoding logic: +// Is the immediate index, in the range 0 to one less than the number of elements in 128 bits, encoded in "i1:tsz". +// bit range mappings: +// i1: [20:21) +// tsz: [16:20) +// Note: +// +// arr is the arrangement. +// This encoding is aligned to the high bit of the box, according to the spec. +func encodeI1Tsz(v, arr uint32) (uint32, bool) { + switch arr { + case ARNG_B: + if v > 15 { + return 0, false + } + return v << 17, true + case ARNG_H: + if v > 7 { + return 0, false + } + return v << 18, true + case ARNG_S: + if v > 3 { + return 0, false + } + return v << 19, true + case ARNG_D: + if v > 1 { + return 0, false + } + return v << 20, true + case ARNG_Q: + if v > 0 { + return 0, false + } + return 0, true + default: + return 0, false + } +} + +// encodeImm2Tsz is the implementation of the following encoding logic: +// Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz". +// bit range mappings: +// imm2: [22:24) +// tsz: [16:21) +// Note: +// +// arr is the arrangement. +// This encoding is aligned to the high bit of the box, according to the spec. +func encodeImm2Tsz(v, arr uint32) (uint32, bool) { + switch arr { + case ARNG_B: + if v > 63 { + return 0, false + } + v <<= 1 + return (v&31)<<16 | (v>>5)<<22, true + case ARNG_H: + if v > 31 { + return 0, false + } + v <<= 2 + return (v&31)<<16 | (v>>5)<<22, true + case ARNG_S: + if v > 15 { + return 0, false + } + v <<= 3 + return (v&31)<<16 | (v>>5)<<22, true + case ARNG_D: + if v > 7 { + return 0, false + } + v <<= 4 + return (v&31)<<16 | (v>>5)<<22, true + case ARNG_Q: + if v > 3 { + return 0, false + } + v <<= 5 + return (v&31)<<16 | (v>>5)<<22, true + default: + return 0, false + } +} + +type arrAlignType int + +const ( + arrAlignBHSD arrAlignType = iota + arrAlignHSD + arrAlignBHS +) + +// encodeShiftTriple encodes an shift immediate value in "tszh:tszl:imm3". +// tszh, tszl, imm3 are in ranges, sorted by bit position. +// These shifts are also bounded by arrangement element size. +func encodeShiftTriple(v uint32, r [6]int, prevAddr *obj.Addr, op obj.As) (uint32, bool) { + // The previous op must be a scalable vector, and we need its arrangement. + acl := aclass(prevAddr) + if acl != AC_ARNG { + return 0, false + } + arr := addrComponent(prevAddr, acl, 1) // Get arrangement + elemBits := uint32(0) + switch arr { + case ARNG_B: + elemBits = 8 + case ARNG_H: + elemBits = 16 + case ARNG_S: + elemBits = 32 + case ARNG_D: + elemBits = 64 + default: + return 0, false + } + if v >= elemBits { + return 0, false + } + var C uint32 + // Unfortunately these information are in the decoding ASL. + // For these instructions, the esize (see comment in the switch below) + // is derived from the destination arrangement, however how this function is called is deriving + // the esize from one of the source. + // We need to address this discrepancy. + effectiveEsize := elemBits + switch op { + case AZRSHRNB, AZRSHRNT, AZSHRNB, AZSHRNT, AZSQRSHRNB, AZSQRSHRNT, AZSQRSHRUNB, AZSQRSHRUNT, + AZSQSHRNB, AZSQSHRNT, AZSQSHRUNB, AZSQSHRUNT, AZUQRSHRNB, AZUQRSHRNT, AZUQSHRNB, AZUQSHRNT: + effectiveEsize = elemBits / 2 + } + switch op { + case AZASR, AZLSR, AZURSHR, AZASRD, + AZRSHRNB, AZRSHRNT, AZSHRNB, AZSHRNT, AZSQRSHRNB, AZSQRSHRNT, AZSQRSHRUNB, AZSQRSHRUNT, + AZSQSHRNB, AZSQSHRNT, AZSQSHRUNB, AZSQSHRUNT, AZSRSHR, AZUQRSHRNB, AZUQRSHRNT, AZUQSHRNB, AZUQSHRNT, + AZURSRA, AZUSRA, AZXAR, AZSRI, AZSRSRA, AZSSRA: + // ASL: let shift : integer = (2 * esize) - UInt(tsize::imm3); + if v == 0 { + return 0, false + } + C = (2 * effectiveEsize) - v + default: + // ASL: let shift : integer = UInt(tsize::imm3) - esize; + C = effectiveEsize + v + } + var chunks [3]uint32 + for i := 0; i < 6; i += 2 { + chunks[i/2] = C & ((1 << (r[i+1] - r[i])) - 1) + C >>= (r[i+1] - r[i]) + } + return uint32((chunks[0] << r[0]) | + (chunks[1] << r[2]) | + (chunks[2] << r[4])), true +} + +// encodeLogicalImmEncoding is the implementation of the following encoding logic: +// Is the size specifier, +// imm13 +// 0xxxxxx0xxxxx S +// 0xxxxxx10xxxx H +// 0xxxxxx110xxx B +// 0xxxxxx1110xx B +// 0xxxxxx11110x B +// 0xxxxxx11111x RESERVED +// 1xxxxxxxxxxxx D +// At the meantime: +// Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, +// each field containing a rotated run of non-zero bits, encoded in the "imm13" field. +// +// bit range mappings: +// imm13: [5:18) +// +// ARM created a "clever" recipe that can generate useful repeating 8-64 bit bitmasks. +// Instead of storing the literal binary number, the processor reads a 13-bit recipe +// using three fields (bits from high to low): +// N (1 bit), immr (6 bits), and imms (6 bits). +// +// How the recipe works: +// Every logical immediate represents a repeating pattern (like repeating tiles). The processor +// uses the three fields to figure out the size of the tile, how many 1s are in the tile, and +// how far to rotate it. +// The N bit combined with the upper bits of imms determines the width of the repeating block. +// Depending on these bits, the fundamental block can be 2, 4, 8, 16, 32, or 64 bits wide. +// The lower bits of imms dictate exactly how many contiguous 1s exist inside that block. +// The immr value tells the processor how many bits to rotate that block to the right. +// Finally, the resulting block is duplicated to fill a standard 64-bit lane. +func encodeLogicalImmArrEncoding(v uint64, adjacentAddr *obj.Addr) (uint32, bool) { + acl := aclass(adjacentAddr) + if acl != AC_ARNG { + return 0, false + } + arr := addrComponent(adjacentAddr, acl, 1) + + // Replicate the given immediate to fill a full 64-bit lane. + // This ensures our pattern-shrinking logic naturally respects the vector lane bounds. + var val uint64 + switch arr { + case ARNG_B: // 8-bit lane + v8 := uint64(v & 0xFF) + val = v8 * 0x0101010101010101 + case ARNG_H: // 16-bit lane + v16 := uint64(v & 0xFFFF) + val = v16 * 0x0001000100010001 + case ARNG_S: // 32-bit lane + v32 := uint64(v) + val = v32 | (v32 << 32) + case ARNG_D: // 64-bit lane + val = uint64(v) + default: + return 0, false + } + + // Reject all zeros or all ones (handled by MOV/EOR, invalid for AND/ORR immediates) + if val == 0 || val == ^uint64(0) { + return 0, false + } + + // Find the absolute smallest repeating pattern size (64 down to 2) + size := uint64(64) + for size > 2 { + half := size / 2 + mask := (uint64(1) << half) - 1 + lower := val & mask + upper := (val >> half) & mask + + // If the top half matches the bottom half, shrink our window + if lower == upper { + size = half + val = lower + } else { + break + } + } + + // Count the contiguous ones in this minimal pattern + mask := (uint64(1) << size) - 1 + val &= mask + ones := bits.OnesCount64(val) + + // Find the right-rotation (rot) needed to align the 1s at the bottom + expected := (uint64(1) << ones) - 1 + rot := -1 + for r := 0; r < int(size); r++ { + // Right rotate 'val' by 'r' bits within a 'size'-bit window + rotated := ((val >> r) | (val << (int(size) - r))) & mask + if rotated == expected { + rot = r + break + } + } + + if rot == -1 { + return 0, false + } + + // immr is the amount the hardware must right-rotate the base pattern. + // Since 'rot' is how much we right-rotated the target to find the base, + // the hardware needs the inverse rotation. + immr := uint32((int(size) - rot) % int(size)) + + // If we couldn't find a rotation that forms a perfect contiguous block of 1s, it's invalid. + if rot == -1 { + return 0, false + } + + // Encode N, immr, and imms + n := uint32(0) + if size == 64 { + n = 1 + } + + // The imms prefix is mathematically generated by (~(size*2 - 1) & 0x3F). + // We then OR it with the number of ones (minus 1). + imms := (uint32(^(size*2 - 1)) & 0x3F) | uint32(ones-1) + + // Construct the final 13-bit field: N (1) | immr (6) | imms (6) + imm13 := (n << 12) | (immr << 6) | imms + + // Shift by 5 to place imm13 into instruction bits [5:17] + return imm13 << 5, true +} + +// encodeImm3Tsize1621 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsize:imm3". +// bit range mappings: +// imm3: [16:19) +// tsize: [19:21) +// +// srcArr is the in the source reglist (ranged). +func encodeImm3Tsize1621(v uint32, srcArr uint32) (uint32, bool) { + // From ARM ASL: let shift : integer = (2 * esize) - UInt(tsize::imm3); + // Then tsize::imm3 = (2 * esize) - shift. + var size uint32 + switch srcArr { + case ARNG_H: + // It's the destination size, which is half the source. + size = 8 + case ARNG_S: + size = 16 + default: + return 0, false + } + if v < 1 || v > size { + return 0, false + } + return (((2*size - v) & 0x1f) << 16), true +} + +// encodeShiftI1TszhTszl is the implementation of the following encoding logic: +// Is the element index, in the range 0 to one less than the number of vector elements in a 128-bit vector register, encoded in "i1:tszh:tszl". +// bit range mappings: +// i1: [23:24) +// tszh: [22:23) +// tszl: [18:21) +// +// arr is the arrangement +func encodeShiftI1TszhTszl(v uint32, arr uint32) (uint32, bool) { + var shift, max uint32 + switch arr { + case ARNG_B: + shift = 1 + max = 16 + case ARNG_H: + shift = 2 + max = 8 + case ARNG_S: + shift = 3 + max = 4 + case ARNG_D: + shift = 4 + max = 2 + default: + return 0, false + } + if v >= max { + return 0, false + } + v <<= shift + return ((v & 0x7) << 18) | ((v >> 3) << 22), true +} + +// tryEncode tries to encode p with i, it returns the encoded binary and ok signal. +func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) { + bin := i.fixedBits + // Some elements are encoded in the same component, they need to be equal. + // For example { .-. }. + // The 2 instances of must encode to the same value. + encoded := map[component]uint32{} + var addrs []*obj.Addr + for addr := range opsInProg(p) { + addrs = append(addrs, addr) + } + if len(addrs) != len(i.args) { + return 0, false + } + for opIdx, addr := range addrs { + if opIdx >= len(i.args) { + return 0, false + } + op := i.args[opIdx] + acl := aclass(addr) + if acl != op.class { + return 0, false + } + for i, enc := range op.elemEncoders { + val := addrComponent(addr, acl, i) + if (p.As == AZFCPY || p.As == AZFDUP) && acl == AC_IMM { + // These instructions expects ARM's 8-bit float encoding. + // Reinterpret the uint32 bits back as a float32, then convert to float64 for chipfloat7 + fval := float64(math.Float32frombits(val)) + encode := (&ctxt7{}).chipfloat7(fval) + if encode == -1 { + // Handle error or return false to indicate mismatch + return 0, false + } + val = uint32(encode) + } + if b, ok := enc.fn(val); ok || b != 0 { + specialB := uint32(b) + if !ok { + specialB = b + switch b { + case codeI1Tsz: + b, ok = encodeI1Tsz(val, addrComponent(addr, acl, i-1)) + case codeImm2Tsz: + b, ok = encodeImm2Tsz(val, addrComponent(addr, acl, i-1)) + case codeShift161919212223: + b, ok = encodeShiftTriple(val, [6]int{16, 19, 19, 21, 22, 23}, addrs[opIdx+1], p.As) + case codeShift161919212224: + b, ok = encodeShiftTriple(val, [6]int{16, 19, 19, 21, 22, 24}, addrs[opIdx+1], p.As) + case codeShift588102224: + b, ok = encodeShiftTriple(val, [6]int{5, 8, 8, 10, 22, 24}, addrs[opIdx+1], p.As) + case codeLogicalImmArrEncoding: + // Now that we know this is an immediate. + // ARM64 allows imm13 to encode up to 64 bits of immediates. + // addrComponent is not the right fit here, we need to extract [Offset] fields manually. + b, ok = encodeLogicalImmArrEncoding(uint64(addr.Offset), addrs[opIdx+1]) + case codeImm3Tsize1621: + b, ok = encodeImm3Tsize1621(val, addrComponent(addrs[opIdx+1], aclass(addrs[opIdx+1]), 1)) + case codeShiftI1TszhTszl: + b, ok = encodeShiftI1TszhTszl(val, addrComponent(addr, AC_PREGSEL, 1)) + case codeNoOp: + b, ok = 0, true + default: + panic(fmt.Errorf("unknown encoding function code %d", b)) + } + } + if !ok { + return 0, false + } + bin |= b + if _, ok := encoded[enc.comp]; ok && b != encoded[enc.comp] { + if specialB == codeNoOp { + // NoOp encodings don't need checks. + continue + } + return 0, false + } + if enc.comp != enc_NIL && specialB != codeNoOp { + // NoOp encodings don't need bookkeeping. + encoded[enc.comp] = b + } + } else { + return 0, false + } + } + } + return bin, true +} diff --git a/src/cmd/internal/obj/arm64/inst_gen.go b/src/cmd/internal/obj/arm64/inst_gen.go new file mode 100644 index 00000000000000..ff98237b9546ca --- /dev/null +++ b/src/cmd/internal/obj/arm64/inst_gen.go @@ -0,0 +1,16111 @@ +// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT. + +// The following constants are generated from the XML specification. + +package arm64 + +// insts are grouped by [goOp]. +var insts = [][]instEncoder{ + // ADDPL + { + // ADDPL #, , + { + goOp: AADDPL, + fixedBits: 0x4605000, + args: cimm__XnSP__XdSP, + }, + }, + // ADDVL + { + // ADDVL #, , + { + goOp: AADDVL, + fixedBits: 0x4205000, + args: cimm__XnSP__XdSP, + }, + }, + // CTERMEQ + { + // CTERMEQ , + { + goOp: ACTERMEQ, + fixedBits: 0x25e02000, + args: Rm__Rn, + }, + }, + // CTERMEQW + { + // CTERMEQW , + { + goOp: ACTERMEQW, + fixedBits: 0x25a02000, + args: Rm__Rn, + }, + }, + // CTERMNE + { + // CTERMNE , + { + goOp: ACTERMNE, + fixedBits: 0x25e02010, + args: Rm__Rn, + }, + }, + // CTERMNEW + { + // CTERMNEW , + { + goOp: ACTERMNEW, + fixedBits: 0x25a02010, + args: Rm__Rn, + }, + }, + // PAND + { + // PAND .B, .B, /Z, .B + { + goOp: APAND, + fixedBits: 0x25004000, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PANDS + { + // PANDS .B, .B, /Z, .B + { + goOp: APANDS, + fixedBits: 0x25404000, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PBIC + { + // PBIC .B, .B, /Z, .B + { + goOp: APBIC, + fixedBits: 0x25004010, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PBICS + { + // PBICS .B, .B, /Z, .B + { + goOp: APBICS, + fixedBits: 0x25404010, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PBRKA + { + // PBRKA .B, /, .B + { + goOp: APBRKA, + fixedBits: 0x25104000, + args: Pn_B__PgZM__Pd_B, + }, + }, + // PBRKAS + { + // PBRKAS .B, /Z, .B + { + goOp: APBRKAS, + fixedBits: 0x25504000, + args: Pn_B__PgZ__Pd_B, + }, + }, + // PBRKB + { + // PBRKB .B, /, .B + { + goOp: APBRKB, + fixedBits: 0x25904000, + args: Pn_B__PgZM__Pd_B, + }, + }, + // PBRKBS + { + // PBRKBS .B, /Z, .B + { + goOp: APBRKBS, + fixedBits: 0x25d04000, + args: Pn_B__PgZ__Pd_B, + }, + }, + // PBRKN + { + // PBRKN .B, .B, /Z, .B + { + goOp: APBRKN, + fixedBits: 0x25184000, + args: Pdm_B__Pn_B__PgZ__Pdm_B, + }, + }, + // PBRKNS + { + // PBRKNS .B, .B, /Z, .B + { + goOp: APBRKNS, + fixedBits: 0x25584000, + args: Pdm_B__Pn_B__PgZ__Pdm_B, + }, + }, + // PBRKPA + { + // PBRKPA .B, .B, /Z, .B + { + goOp: APBRKPA, + fixedBits: 0x2500c000, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PBRKPAS + { + // PBRKPAS .B, .B, /Z, .B + { + goOp: APBRKPAS, + fixedBits: 0x2540c000, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PBRKPB + { + // PBRKPB .B, .B, /Z, .B + { + goOp: APBRKPB, + fixedBits: 0x2500c010, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PBRKPBS + { + // PBRKPBS .B, .B, /Z, .B + { + goOp: APBRKPBS, + fixedBits: 0x2540c010, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PCNTP + { + // PCNTP ., , + { + goOp: APCNTP, + fixedBits: 0x25208000, + args: Pn_T__Pg__Xd, + }, + // PCNTP , ., + { + goOp: APCNTP, + fixedBits: 0x25208200, + args: vl__PNn_T__Xd, + }, + }, + // PDECP + { + // PDECP ., + { + goOp: APDECP, + fixedBits: 0x252d8800, + args: Pm_T__Xdn, + }, + }, + // PEOR + { + // PEOR .B, .B, /Z, .B + { + goOp: APEOR, + fixedBits: 0x25004200, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PEORS + { + // PEORS .B, .B, /Z, .B + { + goOp: APEORS, + fixedBits: 0x25404200, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PFIRSTP + { + // PFIRSTP ., , + { + goOp: APFIRSTP, + fixedBits: 0x25218000, + args: Pn_T__Pg__Xd, + }, + }, + // PINCP + { + // PINCP ., + { + goOp: APINCP, + fixedBits: 0x252c8800, + args: Pm_T__Xdn, + }, + }, + // PLASTP + { + // PLASTP ., , + { + goOp: APLASTP, + fixedBits: 0x25228000, + args: Pn_T__Pg__Xd, + }, + }, + // PLDR + { + // PLDR [{, #, MUL VL}], + { + goOp: APLDR, + fixedBits: 0x85800000, + args: XnSP__cimm__MUL_VL___Pt, + }, + }, + // PNAND + { + // PNAND .B, .B, /Z, .B + { + goOp: APNAND, + fixedBits: 0x25804210, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PNANDS + { + // PNANDS .B, .B, /Z, .B + { + goOp: APNANDS, + fixedBits: 0x25c04210, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PNOR + { + // PNOR .B, .B, /Z, .B + { + goOp: APNOR, + fixedBits: 0x25804200, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PNORS + { + // PNORS .B, .B, /Z, .B + { + goOp: APNORS, + fixedBits: 0x25c04200, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PORN + { + // PORN .B, .B, /Z, .B + { + goOp: APORN, + fixedBits: 0x25804010, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PORNS + { + // PORNS .B, .B, /Z, .B + { + goOp: APORNS, + fixedBits: 0x25c04010, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PORR + { + // PORR .B, .B, /Z, .B + { + goOp: APORR, + fixedBits: 0x25804000, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PORRS + { + // PORRS .B, .B, /Z, .B + { + goOp: APORRS, + fixedBits: 0x25c04000, + args: Pm_B__Pn_B__PgZ__Pd_B, + }, + }, + // PPEXT + { + // PPEXT [], . + { + goOp: APPEXT, + fixedBits: 0x25207010, + args: PNn_imm___Pd_T, + }, + // PPEXT [], { ., . } + { + goOp: APPEXT, + fixedBits: 0x25207410, + args: PNn_imm____Pd1_T__Pd2_T_, + }, + }, + // PPFALSE + { + // PPFALSE .B + { + goOp: APPFALSE, + fixedBits: 0x2518e400, + args: Pd_B, + }, + }, + // PPFIRST + { + // PPFIRST .B, , .B + { + goOp: APPFIRST, + fixedBits: 0x2558c000, + args: Pdn_B__Pg__Pdn_B, + }, + }, + // PPNEXT + { + // PPNEXT ., , . + { + goOp: APPNEXT, + fixedBits: 0x2519c400, + args: Pdn_T__Pv__Pdn_T, + }, + }, + // PPRFB + { + // PPRFB [, ], , + { + goOp: APPRFB, + fixedBits: 0x8400c000, + args: XnSP__Xm___Pg__prfop, + }, + // PPRFB [{, #, MUL VL}], , + { + goOp: APPRFB, + fixedBits: 0x85c00000, + args: XnSP__cimm__MUL_VL___Pg__prfop, + }, + }, + // PPRFD + { + // PPRFD [, , LSL #3], , + { + goOp: APPRFD, + fixedBits: 0x8580c000, + args: XnSP__Xm__LSL_c3___Pg__prfop, + }, + // PPRFD [{, #, MUL VL}], , + { + goOp: APPRFD, + fixedBits: 0x85c06000, + args: XnSP__cimm__MUL_VL___Pg__prfop, + }, + }, + // PPRFH + { + // PPRFH [, , LSL #1], , + { + goOp: APPRFH, + fixedBits: 0x8480c000, + args: XnSP__Xm__LSL_c1___Pg__prfop, + }, + // PPRFH [{, #, MUL VL}], , + { + goOp: APPRFH, + fixedBits: 0x85c02000, + args: XnSP__cimm__MUL_VL___Pg__prfop, + }, + }, + // PPRFW + { + // PPRFW [, , LSL #2], , + { + goOp: APPRFW, + fixedBits: 0x8500c000, + args: XnSP__Xm__LSL_c2___Pg__prfop, + }, + // PPRFW [{, #, MUL VL}], , + { + goOp: APPRFW, + fixedBits: 0x85c04000, + args: XnSP__cimm__MUL_VL___Pg__prfop, + }, + }, + // PPTEST + { + // PPTEST .B, + { + goOp: APPTEST, + fixedBits: 0x2550c000, + args: Pn_B__Pg, + }, + }, + // PPTRUE + { + // PPTRUE . + { + goOp: APPTRUE, + fixedBits: 0x25207810, + args: PNd_T, + }, + }, + // PPUNPKHI + { + // PPUNPKHI .B, .H + { + goOp: APPUNPKHI, + fixedBits: 0x5314000, + args: Pn_B__Pd_H, + }, + }, + // PPUNPKLO + { + // PPUNPKLO .B, .H + { + goOp: APPUNPKLO, + fixedBits: 0x5304000, + args: Pn_B__Pd_H, + }, + }, + // PRDFFR + { + // PRDFFR .B + { + goOp: APRDFFR, + fixedBits: 0x2519f000, + args: Pd_B, + }, + // PRDFFR /Z, .B + { + goOp: APRDFFR, + fixedBits: 0x2518f000, + args: PgZ__Pd_B, + }, + }, + // PRDFFRS + { + // PRDFFRS /Z, .B + { + goOp: APRDFFRS, + fixedBits: 0x2558f000, + args: PgZ__Pd_B, + }, + }, + // PREV + { + // PREV ., . + { + goOp: APREV, + fixedBits: 0x5344000, + args: Pn_T__Pd_T, + }, + }, + // PSEL + { + // PSEL .B, .B, , .B + { + goOp: APSEL, + fixedBits: 0x25004210, + args: Pm_B__Pn_B__Pg__Pd_B, + }, + }, + // PSQDECP + { + // PSQDECP ., + { + goOp: APSQDECP, + fixedBits: 0x252a8c00, + args: Pm_T__Xdn, + }, + }, + // PSQDECPW + { + // PSQDECPW , ., + { + goOp: APSQDECPW, + fixedBits: 0x252a8800, + args: Wdn__Pm_T__Xdn, + }, + }, + // PSQINCP + { + // PSQINCP ., + { + goOp: APSQINCP, + fixedBits: 0x25288c00, + args: Pm_T__Xdn, + }, + }, + // PSQINCPW + { + // PSQINCPW , ., + { + goOp: APSQINCPW, + fixedBits: 0x25288800, + args: Wdn__Pm_T__Xdn, + }, + }, + // PSTR + { + // PSTR , [{, #, MUL VL}] + { + goOp: APSTR, + fixedBits: 0xe5800000, + args: Pt___XnSP__cimm__MUL_VL_, + }, + }, + // PTRN1 + { + // PTRN1 ., ., . + { + goOp: APTRN1, + fixedBits: 0x5205000, + args: Pm_T__Pn_T__Pd_T, + }, + }, + // PTRN2 + { + // PTRN2 ., ., . + { + goOp: APTRN2, + fixedBits: 0x5205400, + args: Pm_T__Pn_T__Pd_T, + }, + }, + // PUQDECP + { + // PUQDECP ., + { + goOp: APUQDECP, + fixedBits: 0x252b8c00, + args: Pm_T__Xdn, + }, + }, + // PUQDECPW + { + // PUQDECPW ., + { + goOp: APUQDECPW, + fixedBits: 0x252b8800, + args: Pm_T__Wdn, + }, + }, + // PUQINCP + { + // PUQINCP ., + { + goOp: APUQINCP, + fixedBits: 0x25298c00, + args: Pm_T__Xdn, + }, + }, + // PUQINCPW + { + // PUQINCPW ., + { + goOp: APUQINCPW, + fixedBits: 0x25298800, + args: Pm_T__Wdn, + }, + }, + // PUZP1 + { + // PUZP1 ., ., . + { + goOp: APUZP1, + fixedBits: 0x5204800, + args: Pm_T__Pn_T__Pd_T, + }, + }, + // PUZP2 + { + // PUZP2 ., ., . + { + goOp: APUZP2, + fixedBits: 0x5204c00, + args: Pm_T__Pn_T__Pd_T, + }, + }, + // PWHILEGE + { + // PWHILEGE , , . + { + goOp: APWHILEGE, + fixedBits: 0x25201000, + args: Rm__Rn__Pd_T, + }, + // PWHILEGE , , { ., . } + { + goOp: APWHILEGE, + fixedBits: 0x25205010, + args: Xm__Xn___Pd1_T__Pd2_T_, + }, + // PWHILEGE , , , . + { + goOp: APWHILEGE, + fixedBits: 0x25204010, + args: vl__Xm__Xn__PNd_T, + }, + }, + // PWHILEGEW + { + // PWHILEGEW , , . + { + goOp: APWHILEGEW, + fixedBits: 0x25200000, + args: Rm__Rn__Pd_T, + }, + }, + // PWHILEGT + { + // PWHILEGT , , . + { + goOp: APWHILEGT, + fixedBits: 0x25201010, + args: Rm__Rn__Pd_T, + }, + // PWHILEGT , , { ., . } + { + goOp: APWHILEGT, + fixedBits: 0x25205011, + args: Xm__Xn___Pd1_T__Pd2_T_, + }, + // PWHILEGT , , , . + { + goOp: APWHILEGT, + fixedBits: 0x25204018, + args: vl__Xm__Xn__PNd_T, + }, + }, + // PWHILEGTW + { + // PWHILEGTW , , . + { + goOp: APWHILEGTW, + fixedBits: 0x25200010, + args: Rm__Rn__Pd_T, + }, + }, + // PWHILEHI + { + // PWHILEHI , , . + { + goOp: APWHILEHI, + fixedBits: 0x25201810, + args: Rm__Rn__Pd_T, + }, + // PWHILEHI , , { ., . } + { + goOp: APWHILEHI, + fixedBits: 0x25205811, + args: Xm__Xn___Pd1_T__Pd2_T_, + }, + // PWHILEHI , , , . + { + goOp: APWHILEHI, + fixedBits: 0x25204818, + args: vl__Xm__Xn__PNd_T, + }, + }, + // PWHILEHIW + { + // PWHILEHIW , , . + { + goOp: APWHILEHIW, + fixedBits: 0x25200810, + args: Rm__Rn__Pd_T, + }, + }, + // PWHILEHS + { + // PWHILEHS , , . + { + goOp: APWHILEHS, + fixedBits: 0x25201800, + args: Rm__Rn__Pd_T, + }, + // PWHILEHS , , { ., . } + { + goOp: APWHILEHS, + fixedBits: 0x25205810, + args: Xm__Xn___Pd1_T__Pd2_T_, + }, + // PWHILEHS , , , . + { + goOp: APWHILEHS, + fixedBits: 0x25204810, + args: vl__Xm__Xn__PNd_T, + }, + }, + // PWHILEHSW + { + // PWHILEHSW , , . + { + goOp: APWHILEHSW, + fixedBits: 0x25200800, + args: Rm__Rn__Pd_T, + }, + }, + // PWHILELE + { + // PWHILELE , , . + { + goOp: APWHILELE, + fixedBits: 0x25201410, + args: Rm__Rn__Pd_T, + }, + // PWHILELE , , { ., . } + { + goOp: APWHILELE, + fixedBits: 0x25205411, + args: Xm__Xn___Pd1_T__Pd2_T_, + }, + // PWHILELE , , , . + { + goOp: APWHILELE, + fixedBits: 0x25204418, + args: vl__Xm__Xn__PNd_T, + }, + }, + // PWHILELEW + { + // PWHILELEW , , . + { + goOp: APWHILELEW, + fixedBits: 0x25200410, + args: Rm__Rn__Pd_T, + }, + }, + // PWHILELO + { + // PWHILELO , , . + { + goOp: APWHILELO, + fixedBits: 0x25201c00, + args: Rm__Rn__Pd_T, + }, + // PWHILELO , , { ., . } + { + goOp: APWHILELO, + fixedBits: 0x25205c10, + args: Xm__Xn___Pd1_T__Pd2_T_, + }, + // PWHILELO , , , . + { + goOp: APWHILELO, + fixedBits: 0x25204c10, + args: vl__Xm__Xn__PNd_T, + }, + }, + // PWHILELOW + { + // PWHILELOW , , . + { + goOp: APWHILELOW, + fixedBits: 0x25200c00, + args: Rm__Rn__Pd_T, + }, + }, + // PWHILELS + { + // PWHILELS , , . + { + goOp: APWHILELS, + fixedBits: 0x25201c10, + args: Rm__Rn__Pd_T, + }, + // PWHILELS , , { ., . } + { + goOp: APWHILELS, + fixedBits: 0x25205c11, + args: Xm__Xn___Pd1_T__Pd2_T_, + }, + // PWHILELS , , , . + { + goOp: APWHILELS, + fixedBits: 0x25204c18, + args: vl__Xm__Xn__PNd_T, + }, + }, + // PWHILELSW + { + // PWHILELSW , , . + { + goOp: APWHILELSW, + fixedBits: 0x25200c10, + args: Rm__Rn__Pd_T, + }, + }, + // PWHILELT + { + // PWHILELT , , . + { + goOp: APWHILELT, + fixedBits: 0x25201400, + args: Rm__Rn__Pd_T, + }, + // PWHILELT , , { ., . } + { + goOp: APWHILELT, + fixedBits: 0x25205410, + args: Xm__Xn___Pd1_T__Pd2_T_, + }, + // PWHILELT , , , . + { + goOp: APWHILELT, + fixedBits: 0x25204410, + args: vl__Xm__Xn__PNd_T, + }, + }, + // PWHILELTW + { + // PWHILELTW , , . + { + goOp: APWHILELTW, + fixedBits: 0x25200400, + args: Rm__Rn__Pd_T, + }, + }, + // PWHILERW + { + // PWHILERW , , . + { + goOp: APWHILERW, + fixedBits: 0x25203010, + args: Xm__Xn__Pd_T, + }, + }, + // PWHILEWR + { + // PWHILEWR , , . + { + goOp: APWHILEWR, + fixedBits: 0x25203000, + args: Xm__Xn__Pd_T, + }, + }, + // PWRFFR + { + // PWRFFR .B + { + goOp: APWRFFR, + fixedBits: 0x25289000, + args: Pn_B, + }, + }, + // PZIP1 + { + // PZIP1 ., ., . + { + goOp: APZIP1, + fixedBits: 0x5204000, + args: Pm_T__Pn_T__Pd_T, + }, + }, + // PZIP2 + { + // PZIP2 ., ., . + { + goOp: APZIP2, + fixedBits: 0x5204400, + args: Pm_T__Pn_T__Pd_T, + }, + }, + // RDVL + { + // RDVL #, + { + goOp: ARDVL, + fixedBits: 0x4bf5000, + args: cimm__Xd, + }, + }, + // SETFFR + { + // SETFFR + { + goOp: ASETFFR, + fixedBits: 0x252c9000, + args: oc, + }, + }, + // ZABS + { + // ZABS ., /M, . + { + goOp: AZABS, + fixedBits: 0x416a000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZABS ., /Z, . + { + goOp: AZABS, + fixedBits: 0x406a000, + args: Zn_T__PgZ__Zd_T__2, + }, + }, + // ZADCLB + { + // ZADCLB ., ., . + { + goOp: AZADCLB, + fixedBits: 0x4500d000, + args: Zm_T__Zn_T__Zda_T__1, + }, + }, + // ZADCLT + { + // ZADCLT ., ., . + { + goOp: AZADCLT, + fixedBits: 0x4500d400, + args: Zm_T__Zn_T__Zda_T__1, + }, + }, + // ZADD + { + // ZADD ., ., /M, . + { + goOp: AZADD, + fixedBits: 0x4000000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZADD ., ., . + { + goOp: AZADD, + fixedBits: 0x4200000, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZADD #{, }, ., . + { + goOp: AZADD, + fixedBits: 0x2520c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, + }, + // ZADDHNB + { + // ZADDHNB ., ., . + { + goOp: AZADDHNB, + fixedBits: 0x45206000, + args: Zm_Tb__Zn_Tb__Zd_T__2, + }, + }, + // ZADDHNT + { + // ZADDHNT ., ., . + { + goOp: AZADDHNT, + fixedBits: 0x45206400, + args: Zm_Tb__Zn_Tb__Zd_T__2, + }, + }, + // ZADDP + { + // ZADDP ., ., /M, . + { + goOp: AZADDP, + fixedBits: 0x4411a000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZADDPT + { + // ZADDPT .D, .D, /M, .D + { + goOp: AZADDPT, + fixedBits: 0x4c40000, + args: Zm_D__Zdn_D__PgM__Zdn_D, + }, + // ZADDPT .D, .D, .D + { + goOp: AZADDPT, + fixedBits: 0x4e00800, + args: Zm_D__Zn_D__Zd_D, + }, + }, + // ZADDQP + { + // ZADDQP ., ., . + { + goOp: AZADDQP, + fixedBits: 0x4207800, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZADDQV + { + // ZADDQV ., , . + { + goOp: AZADDQV, + fixedBits: 0x4052000, + args: Zn_Tb__Pg__Vd_T__1, + }, + }, + // ZADDSUBP + { + // ZADDSUBP ., ., . + { + goOp: AZADDSUBP, + fixedBits: 0x4207c00, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZADR + { + // ZADR [.D, .D, SXTW{}], .D + { + goOp: AZADR, + fixedBits: 0x420a000, + args: Zn_D__Zm_D__SXTWamount___Zd_D, + }, + // ZADR [.D, .D, UXTW{}], .D + { + goOp: AZADR, + fixedBits: 0x460a000, + args: Zn_D__Zm_D__UXTWamount___Zd_D, + }, + // ZADR [., .{, }], . + { + goOp: AZADR, + fixedBits: 0x4a0a000, + args: Zn_T__Zm_T__mod_amount___Zd_T, + }, + }, + // ZAESD + { + // ZAESD .B, .B, .B + { + goOp: AZAESD, + fixedBits: 0x4522e400, + args: Zm_B__Zdn_B__Zdn_B, + }, + // ZAESD .Q[], { .B-.B }, { .B-.B } + { + goOp: AZAESD, + fixedBits: 0x4522ec00, + args: Zm_Q_index____Zdn1_B_Zdn2_B____Zdn1_B_Zdn2_B_, + }, + // ZAESD .Q[], { .B-.B }, { .B-.B } + { + goOp: AZAESD, + fixedBits: 0x4526ec00, + args: Zm_Q_index____Zdn1_B_Zdn4_B____Zdn1_B_Zdn4_B_, + }, + }, + // ZAESDIMC + { + // ZAESDIMC .Q[], { .B-.B }, { .B-.B } + { + goOp: AZAESDIMC, + fixedBits: 0x4523ec00, + args: Zm_Q_index____Zdn1_B_Zdn2_B____Zdn1_B_Zdn2_B_, + }, + // ZAESDIMC .Q[], { .B-.B }, { .B-.B } + { + goOp: AZAESDIMC, + fixedBits: 0x4527ec00, + args: Zm_Q_index____Zdn1_B_Zdn4_B____Zdn1_B_Zdn4_B_, + }, + }, + // ZAESE + { + // ZAESE .B, .B, .B + { + goOp: AZAESE, + fixedBits: 0x4522e000, + args: Zm_B__Zdn_B__Zdn_B, + }, + // ZAESE .Q[], { .B-.B }, { .B-.B } + { + goOp: AZAESE, + fixedBits: 0x4522e800, + args: Zm_Q_index____Zdn1_B_Zdn2_B____Zdn1_B_Zdn2_B_, + }, + // ZAESE .Q[], { .B-.B }, { .B-.B } + { + goOp: AZAESE, + fixedBits: 0x4526e800, + args: Zm_Q_index____Zdn1_B_Zdn4_B____Zdn1_B_Zdn4_B_, + }, + }, + // ZAESEMC + { + // ZAESEMC .Q[], { .B-.B }, { .B-.B } + { + goOp: AZAESEMC, + fixedBits: 0x4523e800, + args: Zm_Q_index____Zdn1_B_Zdn2_B____Zdn1_B_Zdn2_B_, + }, + // ZAESEMC .Q[], { .B-.B }, { .B-.B } + { + goOp: AZAESEMC, + fixedBits: 0x4527e800, + args: Zm_Q_index____Zdn1_B_Zdn4_B____Zdn1_B_Zdn4_B_, + }, + }, + // ZAESIMC + { + // ZAESIMC .B, .B + { + goOp: AZAESIMC, + fixedBits: 0x4520e400, + args: Zdn_B__Zdn_B, + }, + }, + // ZAESMC + { + // ZAESMC .B, .B + { + goOp: AZAESMC, + fixedBits: 0x4520e000, + args: Zdn_B__Zdn_B, + }, + }, + // ZAND + { + // ZAND .D, .D, .D + { + goOp: AZAND, + fixedBits: 0x4203000, + args: Zm_D__Zn_D__Zd_D, + }, + // ZAND ., ., /M, . + { + goOp: AZAND, + fixedBits: 0x41a0000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZAND #, ., . + { + goOp: AZAND, + fixedBits: 0x5800000, + args: cconst__Zdn_T__Zdn_T, + }, + }, + // ZANDQV + { + // ZANDQV ., , . + { + goOp: AZANDQV, + fixedBits: 0x41e2000, + args: Zn_Tb__Pg__Vd_T__1, + }, + }, + // ZANDVB + { + // ZANDVB ., , + { + goOp: AZANDVB, + fixedBits: 0x41a2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZANDVD + { + // ZANDVD ., , + { + goOp: AZANDVD, + fixedBits: 0x4da2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZANDVH + { + // ZANDVH ., , + { + goOp: AZANDVH, + fixedBits: 0x45a2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZANDVS + { + // ZANDVS ., , + { + goOp: AZANDVS, + fixedBits: 0x49a2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZASR + { + // ZASR .D, ., /M, . + { + goOp: AZASR, + fixedBits: 0x4188000, + args: Zm_D__Zdn_T__PgM__Zdn_T, + }, + // ZASR .D, ., . + { + goOp: AZASR, + fixedBits: 0x4208000, + args: Zm_D__Zn_T__Zd_T, + }, + // ZASR ., ., /M, . + { + goOp: AZASR, + fixedBits: 0x4108000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZASR #, ., /M, . + { + goOp: AZASR, + fixedBits: 0x4008000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, + // ZASR #, ., . + { + goOp: AZASR, + fixedBits: 0x4209000, + args: cconst__Zn_T__Zd_T__1, + }, + }, + // ZASRD + { + // ZASRD #, ., /M, . + { + goOp: AZASRD, + fixedBits: 0x4048000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZASRR + { + // ZASRR ., ., /M, . + { + goOp: AZASRR, + fixedBits: 0x4148000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZBCAX + { + // ZBCAX .D, .D, .D, .D + { + goOp: AZBCAX, + fixedBits: 0x4603800, + args: Zk_D__Zm_D__Zdn_D__Zdn_D, + }, + }, + // ZBDEP + { + // ZBDEP ., ., . + { + goOp: AZBDEP, + fixedBits: 0x4500b400, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZBEXT + { + // ZBEXT ., ., . + { + goOp: AZBEXT, + fixedBits: 0x4500b000, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZBF1CVT + { + // ZBF1CVT .B, .H + { + goOp: AZBF1CVT, + fixedBits: 0x65083800, + args: Zn_B__Zd_H, + }, + }, + // ZBF1CVTLT + { + // ZBF1CVTLT .B, .H + { + goOp: AZBF1CVTLT, + fixedBits: 0x65093800, + args: Zn_B__Zd_H, + }, + }, + // ZBF2CVT + { + // ZBF2CVT .B, .H + { + goOp: AZBF2CVT, + fixedBits: 0x65083c00, + args: Zn_B__Zd_H, + }, + }, + // ZBF2CVTLT + { + // ZBF2CVTLT .B, .H + { + goOp: AZBF2CVTLT, + fixedBits: 0x65093c00, + args: Zn_B__Zd_H, + }, + }, + // ZBFADD + { + // ZBFADD .H, .H, /M, .H + { + goOp: AZBFADD, + fixedBits: 0x65008000, + args: Zm_H__Zdn_H__PgM__Zdn_H, + }, + // ZBFADD .H, .H, .H + { + goOp: AZBFADD, + fixedBits: 0x65000000, + args: Zm_H__Zn_H__Zd_H, + }, + }, + // ZBFCLAMP + { + // ZBFCLAMP .H, .H, .H + { + goOp: AZBFCLAMP, + fixedBits: 0x64202400, + args: Zm_H__Zn_H__Zd_H, + }, + }, + // ZBFCVT + { + // ZBFCVT .S, /M, .H + { + goOp: AZBFCVT, + fixedBits: 0x658aa000, + args: Zn_S__PgM__Zd_H, + }, + // ZBFCVT .S, /Z, .H + { + goOp: AZBFCVT, + fixedBits: 0x649ac000, + args: Zn_S__PgZ__Zd_H, + }, + }, + // ZBFCVTN + { + // ZBFCVTN { .H-.H }, .B + { + goOp: AZBFCVTN, + fixedBits: 0x650a3800, + args: Zn1_H_Zn2_H___Zd_B, + }, + }, + // ZBFCVTNT + { + // ZBFCVTNT .S, /M, .H + { + goOp: AZBFCVTNT, + fixedBits: 0x648aa000, + args: Zn_S__PgM__Zd_H, + }, + // ZBFCVTNT .S, /Z, .H + { + goOp: AZBFCVTNT, + fixedBits: 0x6482a000, + args: Zn_S__PgZ__Zd_H, + }, + }, + // ZBFDOT + { + // ZBFDOT .H, .H, .S + { + goOp: AZBFDOT, + fixedBits: 0x64608000, + args: Zm_H__Zn_H__Zda_S, + }, + // ZBFDOT .H[], .H, .S + { + goOp: AZBFDOT, + fixedBits: 0x64604000, + args: Zm_H_imm___Zn_H__Zda_S__3, + }, + }, + // ZBFMAX + { + // ZBFMAX .H, .H, /M, .H + { + goOp: AZBFMAX, + fixedBits: 0x65068000, + args: Zm_H__Zdn_H__PgM__Zdn_H, + }, + }, + // ZBFMAXNM + { + // ZBFMAXNM .H, .H, /M, .H + { + goOp: AZBFMAXNM, + fixedBits: 0x65048000, + args: Zm_H__Zdn_H__PgM__Zdn_H, + }, + }, + // ZBFMIN + { + // ZBFMIN .H, .H, /M, .H + { + goOp: AZBFMIN, + fixedBits: 0x65078000, + args: Zm_H__Zdn_H__PgM__Zdn_H, + }, + }, + // ZBFMINNM + { + // ZBFMINNM .H, .H, /M, .H + { + goOp: AZBFMINNM, + fixedBits: 0x65058000, + args: Zm_H__Zdn_H__PgM__Zdn_H, + }, + }, + // ZBFMLA + { + // ZBFMLA .H, .H, /M, .H + { + goOp: AZBFMLA, + fixedBits: 0x65200000, + args: Zm_H__Zn_H__PgM__Zda_H, + }, + // ZBFMLA .H[], .H, .H + { + goOp: AZBFMLA, + fixedBits: 0x64200800, + args: Zm_H_imm___Zn_H__Zda_H__2, + }, + }, + // ZBFMLALB + { + // ZBFMLALB .H, .H, .S + { + goOp: AZBFMLALB, + fixedBits: 0x64e08000, + args: Zm_H__Zn_H__Zda_S, + }, + // ZBFMLALB .H[], .H, .S + { + goOp: AZBFMLALB, + fixedBits: 0x64e04000, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, + }, + // ZBFMLALT + { + // ZBFMLALT .H, .H, .S + { + goOp: AZBFMLALT, + fixedBits: 0x64e08400, + args: Zm_H__Zn_H__Zda_S, + }, + // ZBFMLALT .H[], .H, .S + { + goOp: AZBFMLALT, + fixedBits: 0x64e04400, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, + }, + // ZBFMLS + { + // ZBFMLS .H, .H, /M, .H + { + goOp: AZBFMLS, + fixedBits: 0x65202000, + args: Zm_H__Zn_H__PgM__Zda_H, + }, + // ZBFMLS .H[], .H, .H + { + goOp: AZBFMLS, + fixedBits: 0x64200c00, + args: Zm_H_imm___Zn_H__Zda_H__2, + }, + }, + // ZBFMLSLB + { + // ZBFMLSLB .H, .H, .S + { + goOp: AZBFMLSLB, + fixedBits: 0x64e0a000, + args: Zm_H__Zn_H__Zda_S, + }, + // ZBFMLSLB .H[], .H, .S + { + goOp: AZBFMLSLB, + fixedBits: 0x64e06000, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, + }, + // ZBFMLSLT + { + // ZBFMLSLT .H, .H, .S + { + goOp: AZBFMLSLT, + fixedBits: 0x64e0a400, + args: Zm_H__Zn_H__Zda_S, + }, + // ZBFMLSLT .H[], .H, .S + { + goOp: AZBFMLSLT, + fixedBits: 0x64e06400, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, + }, + // ZBFMMLA + { + // ZBFMMLA .H, .H, .H + { + goOp: AZBFMMLA, + fixedBits: 0x64e0e000, + args: Zm_H__Zn_H__Zda_H, + }, + // ZBFMMLA .H, .H, .S + { + goOp: AZBFMMLA, + fixedBits: 0x6460e400, + args: Zm_H__Zn_H__Zda_S, + }, + }, + // ZBFMUL + { + // ZBFMUL .H, .H, /M, .H + { + goOp: AZBFMUL, + fixedBits: 0x65028000, + args: Zm_H__Zdn_H__PgM__Zdn_H, + }, + // ZBFMUL .H, .H, .H + { + goOp: AZBFMUL, + fixedBits: 0x65000800, + args: Zm_H__Zn_H__Zd_H, + }, + // ZBFMUL .H[], .H, .H + { + goOp: AZBFMUL, + fixedBits: 0x64202800, + args: Zm_H_imm___Zn_H__Zd_H__2, + }, + }, + // ZBFSCALE + { + // ZBFSCALE .H, .H, /M, .H + { + goOp: AZBFSCALE, + fixedBits: 0x65098000, + args: Zm_H__Zdn_H__PgM__Zdn_H, + }, + }, + // ZBFSUB + { + // ZBFSUB .H, .H, /M, .H + { + goOp: AZBFSUB, + fixedBits: 0x65018000, + args: Zm_H__Zdn_H__PgM__Zdn_H, + }, + // ZBFSUB .H, .H, .H + { + goOp: AZBFSUB, + fixedBits: 0x65000400, + args: Zm_H__Zn_H__Zd_H, + }, + }, + // ZBGRP + { + // ZBGRP ., ., . + { + goOp: AZBGRP, + fixedBits: 0x4500b800, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZBIC + { + // ZBIC .D, .D, .D + { + goOp: AZBIC, + fixedBits: 0x4e03000, + args: Zm_D__Zn_D__Zd_D, + }, + // ZBIC ., ., /M, . + { + goOp: AZBIC, + fixedBits: 0x41b0000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZBSL + { + // ZBSL .D, .D, .D, .D + { + goOp: AZBSL, + fixedBits: 0x4203c00, + args: Zk_D__Zm_D__Zdn_D__Zdn_D, + }, + }, + // ZBSL1N + { + // ZBSL1N .D, .D, .D, .D + { + goOp: AZBSL1N, + fixedBits: 0x4603c00, + args: Zk_D__Zm_D__Zdn_D__Zdn_D, + }, + }, + // ZBSL2N + { + // ZBSL2N .D, .D, .D, .D + { + goOp: AZBSL2N, + fixedBits: 0x4a03c00, + args: Zk_D__Zm_D__Zdn_D__Zdn_D, + }, + }, + // ZCADD + { + // ZCADD , ., ., . + { + goOp: AZCADD, + fixedBits: 0x4500d800, + args: const__Zm_T__Zdn_T__Zdn_T, + }, + }, + // ZCDOT + { + // ZCDOT , .B[], .B, .S + { + goOp: AZCDOT, + fixedBits: 0x44a04000, + args: const__Zm_B_imm___Zn_B__Zda_S, + }, + // ZCDOT , .H[], .H, .D + { + goOp: AZCDOT, + fixedBits: 0x44e04000, + args: const__Zm_H_imm___Zn_H__Zda_D, + }, + // ZCDOT , ., ., . + { + goOp: AZCDOT, + fixedBits: 0x44801000, + args: const__Zm_Tb__Zn_Tb__Zda_T, + }, + }, + // ZCLASTA + { + // ZCLASTA ., ., , . + { + goOp: AZCLASTA, + fixedBits: 0x5288000, + args: Zm_T__Zdn_T__Pg__Zdn_T, + }, + // ZCLASTA ., , , + { + goOp: AZCLASTA, + fixedBits: 0x5f0a000, + args: Zm_T__Rdn__Pg__Rdn, + }, + }, + // ZCLASTAB + { + // ZCLASTAB ., , , + { + goOp: AZCLASTAB, + fixedBits: 0x52a8000, + args: Zm_T__Vdn__Pg__Vdn__1, + }, + }, + // ZCLASTAD + { + // ZCLASTAD ., , , + { + goOp: AZCLASTAD, + fixedBits: 0x5ea8000, + args: Zm_T__Vdn__Pg__Vdn__1, + }, + }, + // ZCLASTAH + { + // ZCLASTAH ., , , + { + goOp: AZCLASTAH, + fixedBits: 0x56a8000, + args: Zm_T__Vdn__Pg__Vdn__1, + }, + }, + // ZCLASTAS + { + // ZCLASTAS ., , , + { + goOp: AZCLASTAS, + fixedBits: 0x5aa8000, + args: Zm_T__Vdn__Pg__Vdn__1, + }, + }, + // ZCLASTAW + { + // ZCLASTAW ., , , + { + goOp: AZCLASTAW, + fixedBits: 0x530a000, + args: Zm_T__Rdn__Pg__Rdn, + }, + }, + // ZCLASTB + { + // ZCLASTB ., ., , . + { + goOp: AZCLASTB, + fixedBits: 0x5298000, + args: Zm_T__Zdn_T__Pg__Zdn_T, + }, + // ZCLASTB ., , , + { + goOp: AZCLASTB, + fixedBits: 0x5f1a000, + args: Zm_T__Rdn__Pg__Rdn, + }, + }, + // ZCLASTBB + { + // ZCLASTBB ., , , + { + goOp: AZCLASTBB, + fixedBits: 0x52b8000, + args: Zm_T__Vdn__Pg__Vdn__1, + }, + }, + // ZCLASTBD + { + // ZCLASTBD ., , , + { + goOp: AZCLASTBD, + fixedBits: 0x5eb8000, + args: Zm_T__Vdn__Pg__Vdn__1, + }, + }, + // ZCLASTBH + { + // ZCLASTBH ., , , + { + goOp: AZCLASTBH, + fixedBits: 0x56b8000, + args: Zm_T__Vdn__Pg__Vdn__1, + }, + }, + // ZCLASTBS + { + // ZCLASTBS ., , , + { + goOp: AZCLASTBS, + fixedBits: 0x5ab8000, + args: Zm_T__Vdn__Pg__Vdn__1, + }, + }, + // ZCLASTBW + { + // ZCLASTBW ., , , + { + goOp: AZCLASTBW, + fixedBits: 0x531a000, + args: Zm_T__Rdn__Pg__Rdn, + }, + }, + // ZCLS + { + // ZCLS ., /M, . + { + goOp: AZCLS, + fixedBits: 0x418a000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZCLS ., /Z, . + { + goOp: AZCLS, + fixedBits: 0x408a000, + args: Zn_T__PgZ__Zd_T__2, + }, + }, + // ZCLZ + { + // ZCLZ ., /M, . + { + goOp: AZCLZ, + fixedBits: 0x419a000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZCLZ ., /Z, . + { + goOp: AZCLZ, + fixedBits: 0x409a000, + args: Zn_T__PgZ__Zd_T__2, + }, + }, + // ZCMLA + { + // ZCMLA , .H[], .H, .H + { + goOp: AZCMLA, + fixedBits: 0x44a06000, + args: const__Zm_H_imm___Zn_H__Zda_H__1, + }, + // ZCMLA , .S[], .S, .S + { + goOp: AZCMLA, + fixedBits: 0x44e06000, + args: const__Zm_S_imm___Zn_S__Zda_S__1, + }, + // ZCMLA , ., ., . + { + goOp: AZCMLA, + fixedBits: 0x44002000, + args: const__Zm_T__Zn_T__Zda_T, + }, + }, + // ZCMPEQ + { + // ZCMPEQ .D, ., /Z, . + { + goOp: AZCMPEQ, + fixedBits: 0x24002000, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, + // ZCMPEQ ., ., /Z, . + { + goOp: AZCMPEQ, + fixedBits: 0x2400a000, + args: Zm_T__Zn_T__PgZ__Pd_T__2, + }, + // ZCMPEQ #, ., /Z, . + { + goOp: AZCMPEQ, + fixedBits: 0x25008000, + args: cimm__Zn_T__PgZ__Pd_T__1, + }, + }, + // ZCMPGE + { + // ZCMPGE .D, ., /Z, . + { + goOp: AZCMPGE, + fixedBits: 0x24004000, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, + // ZCMPGE ., ., /Z, . + { + goOp: AZCMPGE, + fixedBits: 0x24008000, + args: Zm_T__Zn_T__PgZ__Pd_T__2, + }, + // ZCMPGE #, ., /Z, . + { + goOp: AZCMPGE, + fixedBits: 0x25000000, + args: cimm__Zn_T__PgZ__Pd_T__1, + }, + }, + // ZCMPGT + { + // ZCMPGT .D, ., /Z, . + { + goOp: AZCMPGT, + fixedBits: 0x24004010, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, + // ZCMPGT ., ., /Z, . + { + goOp: AZCMPGT, + fixedBits: 0x24008010, + args: Zm_T__Zn_T__PgZ__Pd_T__2, + }, + // ZCMPGT #, ., /Z, . + { + goOp: AZCMPGT, + fixedBits: 0x25000010, + args: cimm__Zn_T__PgZ__Pd_T__1, + }, + }, + // ZCMPHI + { + // ZCMPHI .D, ., /Z, . + { + goOp: AZCMPHI, + fixedBits: 0x2400c010, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, + // ZCMPHI ., ., /Z, . + { + goOp: AZCMPHI, + fixedBits: 0x24000010, + args: Zm_T__Zn_T__PgZ__Pd_T__2, + }, + // ZCMPHI #, ., /Z, . + { + goOp: AZCMPHI, + fixedBits: 0x24200010, + args: cimm__Zn_T__PgZ__Pd_T__2, + }, + }, + // ZCMPHS + { + // ZCMPHS .D, ., /Z, . + { + goOp: AZCMPHS, + fixedBits: 0x2400c000, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, + // ZCMPHS ., ., /Z, . + { + goOp: AZCMPHS, + fixedBits: 0x24000000, + args: Zm_T__Zn_T__PgZ__Pd_T__2, + }, + // ZCMPHS #, ., /Z, . + { + goOp: AZCMPHS, + fixedBits: 0x24200000, + args: cimm__Zn_T__PgZ__Pd_T__2, + }, + }, + // ZCMPLE + { + // ZCMPLE .D, ., /Z, . + { + goOp: AZCMPLE, + fixedBits: 0x24006010, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, + // ZCMPLE #, ., /Z, . + { + goOp: AZCMPLE, + fixedBits: 0x25002010, + args: cimm__Zn_T__PgZ__Pd_T__1, + }, + }, + // ZCMPLO + { + // ZCMPLO .D, ., /Z, . + { + goOp: AZCMPLO, + fixedBits: 0x2400e000, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, + // ZCMPLO #, ., /Z, . + { + goOp: AZCMPLO, + fixedBits: 0x24202000, + args: cimm__Zn_T__PgZ__Pd_T__2, + }, + }, + // ZCMPLS + { + // ZCMPLS .D, ., /Z, . + { + goOp: AZCMPLS, + fixedBits: 0x2400e010, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, + // ZCMPLS #, ., /Z, . + { + goOp: AZCMPLS, + fixedBits: 0x24202010, + args: cimm__Zn_T__PgZ__Pd_T__2, + }, + }, + // ZCMPLT + { + // ZCMPLT .D, ., /Z, . + { + goOp: AZCMPLT, + fixedBits: 0x24006000, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, + // ZCMPLT #, ., /Z, . + { + goOp: AZCMPLT, + fixedBits: 0x25002000, + args: cimm__Zn_T__PgZ__Pd_T__1, + }, + }, + // ZCMPNE + { + // ZCMPNE .D, ., /Z, . + { + goOp: AZCMPNE, + fixedBits: 0x24002010, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, + // ZCMPNE ., ., /Z, . + { + goOp: AZCMPNE, + fixedBits: 0x2400a010, + args: Zm_T__Zn_T__PgZ__Pd_T__2, + }, + // ZCMPNE #, ., /Z, . + { + goOp: AZCMPNE, + fixedBits: 0x25008010, + args: cimm__Zn_T__PgZ__Pd_T__1, + }, + }, + // ZCNOT + { + // ZCNOT ., /M, . + { + goOp: AZCNOT, + fixedBits: 0x41ba000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZCNOT ., /Z, . + { + goOp: AZCNOT, + fixedBits: 0x40ba000, + args: Zn_T__PgZ__Zd_T__2, + }, + }, + // ZCNT + { + // ZCNT ., /M, . + { + goOp: AZCNT, + fixedBits: 0x41aa000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZCNT ., /Z, . + { + goOp: AZCNT, + fixedBits: 0x40aa000, + args: Zn_T__PgZ__Zd_T__2, + }, + }, + // ZCOMPACT + { + // ZCOMPACT ., , . + { + goOp: AZCOMPACT, + fixedBits: 0x5218000, + args: Zn_T__Pg__Zd_T__1, + }, + // ZCOMPACT ., , . + { + goOp: AZCOMPACT, + fixedBits: 0x5a18000, + args: Zn_T__Pg__Zd_T__2, + }, + }, + // ZCPY + { + // ZCPY , /M, . + { + goOp: AZCPY, + fixedBits: 0x5e8a000, + args: RnSP__PgM__Zd_T, + }, + // ZCPY #{, }, /M, . + { + goOp: AZCPY, + fixedBits: 0x5104000, + args: cimm__shift__PgM__Zd_T, + }, + // ZCPY #{, }, /Z, . + { + goOp: AZCPY, + fixedBits: 0x5100000, + args: cimm__shift__PgZ__Zd_T, + }, + }, + // ZCPYB + { + // ZCPYB , /M, . + { + goOp: AZCPYB, + fixedBits: 0x5208000, + args: Vn__PgM__Zd_T, + }, + }, + // ZCPYD + { + // ZCPYD , /M, . + { + goOp: AZCPYD, + fixedBits: 0x5e08000, + args: Vn__PgM__Zd_T, + }, + }, + // ZCPYH + { + // ZCPYH , /M, . + { + goOp: AZCPYH, + fixedBits: 0x5608000, + args: Vn__PgM__Zd_T, + }, + }, + // ZCPYS + { + // ZCPYS , /M, . + { + goOp: AZCPYS, + fixedBits: 0x5a08000, + args: Vn__PgM__Zd_T, + }, + }, + // ZCPYW + { + // ZCPYW , /M, . + { + goOp: AZCPYW, + fixedBits: 0x528a000, + args: RnSP__PgM__Zd_T, + }, + }, + // ZDECP + { + // ZDECP ., . + { + goOp: AZDECP, + fixedBits: 0x252d8000, + args: Pm_T__Zdn_T, + }, + }, + // ZDUP + { + // ZDUP , . + { + goOp: AZDUP, + fixedBits: 0x5e03800, + args: RnSP__Zd_T, + }, + // ZDUP .[], . + { + goOp: AZDUP, + fixedBits: 0x5202000, + args: Zn_T_imm___Zd_T__1, + }, + // ZDUP #{, }, . + { + goOp: AZDUP, + fixedBits: 0x2538c000, + args: cimm__shift__Zd_T, + }, + }, + // ZDUPM + { + // ZDUPM #, . + { + goOp: AZDUPM, + fixedBits: 0x5c00000, + args: cconst__Zd_T__1, + }, + }, + // ZDUPQ + { + // ZDUPQ .[], . + { + goOp: AZDUPQ, + fixedBits: 0x5202400, + args: Zn_T_imm___Zd_T__2, + }, + }, + // ZDUPW + { + // ZDUPW , . + { + goOp: AZDUPW, + fixedBits: 0x5203800, + args: RnSP__Zd_T, + }, + }, + // ZEOR + { + // ZEOR .D, .D, .D + { + goOp: AZEOR, + fixedBits: 0x4a03000, + args: Zm_D__Zn_D__Zd_D, + }, + // ZEOR ., ., /M, . + { + goOp: AZEOR, + fixedBits: 0x4190000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZEOR #, ., . + { + goOp: AZEOR, + fixedBits: 0x5400000, + args: cconst__Zdn_T__Zdn_T, + }, + }, + // ZEOR3 + { + // ZEOR3 .D, .D, .D, .D + { + goOp: AZEOR3, + fixedBits: 0x4203800, + args: Zk_D__Zm_D__Zdn_D__Zdn_D, + }, + }, + // ZEORBT + { + // ZEORBT ., ., . + { + goOp: AZEORBT, + fixedBits: 0x45009000, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZEORQV + { + // ZEORQV ., , . + { + goOp: AZEORQV, + fixedBits: 0x41d2000, + args: Zn_Tb__Pg__Vd_T__1, + }, + }, + // ZEORTB + { + // ZEORTB ., ., . + { + goOp: AZEORTB, + fixedBits: 0x45009400, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZEORVB + { + // ZEORVB ., , + { + goOp: AZEORVB, + fixedBits: 0x4192000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZEORVD + { + // ZEORVD ., , + { + goOp: AZEORVD, + fixedBits: 0x4d92000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZEORVH + { + // ZEORVH ., , + { + goOp: AZEORVH, + fixedBits: 0x4592000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZEORVS + { + // ZEORVS ., , + { + goOp: AZEORVS, + fixedBits: 0x4992000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZEXPAND + { + // ZEXPAND ., , . + { + goOp: AZEXPAND, + fixedBits: 0x5318000, + args: Zn_T__Pg__Zd_T__3, + }, + }, + // ZEXT + { + // ZEXT #, .B, .B, .B + { + goOp: AZEXT, + fixedBits: 0x5200000, + args: cimm__Zm_B__Zdn_B__Zdn_B__1, + }, + // ZEXT #, { .B, .B }, .B + { + goOp: AZEXT, + fixedBits: 0x5600000, + args: cimm___Zn1_B__Zn2_B___Zd_B, + }, + }, + // ZEXTQ + { + // ZEXTQ #, .B, .B, .B + { + goOp: AZEXTQ, + fixedBits: 0x5602400, + args: cimm__Zm_B__Zdn_B__Zdn_B__2, + }, + }, + // ZF1CVT + { + // ZF1CVT .B, .H + { + goOp: AZF1CVT, + fixedBits: 0x65083000, + args: Zn_B__Zd_H, + }, + }, + // ZF1CVTLT + { + // ZF1CVTLT .B, .H + { + goOp: AZF1CVTLT, + fixedBits: 0x65093000, + args: Zn_B__Zd_H, + }, + }, + // ZF2CVT + { + // ZF2CVT .B, .H + { + goOp: AZF2CVT, + fixedBits: 0x65083400, + args: Zn_B__Zd_H, + }, + }, + // ZF2CVTLT + { + // ZF2CVTLT .B, .H + { + goOp: AZF2CVTLT, + fixedBits: 0x65093400, + args: Zn_B__Zd_H, + }, + }, + // ZFABD + { + // ZFABD ., ., /M, . + { + goOp: AZFABD, + fixedBits: 0x65088000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFABS + { + // ZFABS ., /M, . + { + goOp: AZFABS, + fixedBits: 0x41ca000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFABS ., /Z, . + { + goOp: AZFABS, + fixedBits: 0x40ca000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFACGE + { + // ZFACGE ., ., /Z, . + { + goOp: AZFACGE, + fixedBits: 0x6500c010, + args: Zm_T__Zn_T__PgZ__Pd_T__1, + }, + }, + // ZFACGT + { + // ZFACGT ., ., /Z, . + { + goOp: AZFACGT, + fixedBits: 0x6500e010, + args: Zm_T__Zn_T__PgZ__Pd_T__1, + }, + }, + // ZFADD + { + // ZFADD ., ., /M, . + { + goOp: AZFADD, + fixedBits: 0x65008000, + args: Zm_T__Zdn_T__PgM__Zdn_T__3, + }, + // ZFADD ., ., . + { + goOp: AZFADD, + fixedBits: 0x65000000, + args: Zm_T__Zn_T__Zd_T__2, + }, + // ZFADD , ., /M, . + { + goOp: AZFADD, + fixedBits: 0x65188000, + args: const__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFADDAD + { + // ZFADDAD ., , , + { + goOp: AZFADDAD, + fixedBits: 0x65d82000, + args: Zm_T__Vdn__Pg__Vdn__2, + }, + }, + // ZFADDAH + { + // ZFADDAH ., , , + { + goOp: AZFADDAH, + fixedBits: 0x65582000, + args: Zm_T__Vdn__Pg__Vdn__2, + }, + }, + // ZFADDAS + { + // ZFADDAS ., , , + { + goOp: AZFADDAS, + fixedBits: 0x65982000, + args: Zm_T__Vdn__Pg__Vdn__2, + }, + }, + // ZFADDP + { + // ZFADDP ., ., /M, . + { + goOp: AZFADDP, + fixedBits: 0x64108000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFADDQV + { + // ZFADDQV ., , . + { + goOp: AZFADDQV, + fixedBits: 0x6410a000, + args: Zn_Tb__Pg__Vd_T__2, + }, + }, + // ZFADDVD + { + // ZFADDVD ., , + { + goOp: AZFADDVD, + fixedBits: 0x65c02000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFADDVH + { + // ZFADDVH ., , + { + goOp: AZFADDVH, + fixedBits: 0x65402000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFADDVS + { + // ZFADDVS ., , + { + goOp: AZFADDVS, + fixedBits: 0x65802000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFAMAX + { + // ZFAMAX ., ., /M, . + { + goOp: AZFAMAX, + fixedBits: 0x650e8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFAMIN + { + // ZFAMIN ., ., /M, . + { + goOp: AZFAMIN, + fixedBits: 0x650f8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFCADD + { + // ZFCADD , ., ., /M, . + { + goOp: AZFCADD, + fixedBits: 0x64008000, + args: const__Zm_T__Zdn_T__PgM__Zdn_T, + }, + }, + // ZFCLAMP + { + // ZFCLAMP ., ., . + { + goOp: AZFCLAMP, + fixedBits: 0x64202400, + args: Zm_T__Zn_T__Zd_T__2, + }, + }, + // ZFCMEQ + { + // ZFCMEQ ., ., /Z, . + { + goOp: AZFCMEQ, + fixedBits: 0x65006000, + args: Zm_T__Zn_T__PgZ__Pd_T__1, + }, + // ZFCMEQ #0.0, ., /Z, . + { + goOp: AZFCMEQ, + fixedBits: 0x65122000, + args: c0_0__Zn_T__PgZ__Pd_T, + }, + }, + // ZFCMGE + { + // ZFCMGE ., ., /Z, . + { + goOp: AZFCMGE, + fixedBits: 0x65004000, + args: Zm_T__Zn_T__PgZ__Pd_T__1, + }, + // ZFCMGE #0.0, ., /Z, . + { + goOp: AZFCMGE, + fixedBits: 0x65102000, + args: c0_0__Zn_T__PgZ__Pd_T, + }, + }, + // ZFCMGT + { + // ZFCMGT ., ., /Z, . + { + goOp: AZFCMGT, + fixedBits: 0x65004010, + args: Zm_T__Zn_T__PgZ__Pd_T__1, + }, + // ZFCMGT #0.0, ., /Z, . + { + goOp: AZFCMGT, + fixedBits: 0x65102010, + args: c0_0__Zn_T__PgZ__Pd_T, + }, + }, + // ZFCMLA + { + // ZFCMLA , .H[], .H, .H + { + goOp: AZFCMLA, + fixedBits: 0x64a01000, + args: const__Zm_H_imm___Zn_H__Zda_H__2, + }, + // ZFCMLA , .S[], .S, .S + { + goOp: AZFCMLA, + fixedBits: 0x64e01000, + args: const__Zm_S_imm___Zn_S__Zda_S__2, + }, + // ZFCMLA , ., ., /M, . + { + goOp: AZFCMLA, + fixedBits: 0x64000000, + args: const__Zm_T__Zn_T__PgM__Zda_T, + }, + }, + // ZFCMLE + { + // ZFCMLE #0.0, ., /Z, . + { + goOp: AZFCMLE, + fixedBits: 0x65112010, + args: c0_0__Zn_T__PgZ__Pd_T, + }, + }, + // ZFCMLT + { + // ZFCMLT #0.0, ., /Z, . + { + goOp: AZFCMLT, + fixedBits: 0x65112000, + args: c0_0__Zn_T__PgZ__Pd_T, + }, + }, + // ZFCMNE + { + // ZFCMNE ., ., /Z, . + { + goOp: AZFCMNE, + fixedBits: 0x65006010, + args: Zm_T__Zn_T__PgZ__Pd_T__1, + }, + // ZFCMNE #0.0, ., /Z, . + { + goOp: AZFCMNE, + fixedBits: 0x65132000, + args: c0_0__Zn_T__PgZ__Pd_T, + }, + }, + // ZFCMUO + { + // ZFCMUO ., ., /Z, . + { + goOp: AZFCMUO, + fixedBits: 0x6500c000, + args: Zm_T__Zn_T__PgZ__Pd_T__1, + }, + }, + // ZFCPY + { + // ZFCPY #, /M, . + { + goOp: AZFCPY, + fixedBits: 0x510c000, + args: cconst__PgM__Zd_T, + }, + }, + // ZFCVT + { + // ZFCVT .D, /M, .H + { + goOp: AZFCVT, + fixedBits: 0x65c8a000, + args: Zn_D__PgM__Zd_H, + }, + // ZFCVT .D, /M, .S + { + goOp: AZFCVT, + fixedBits: 0x65caa000, + args: Zn_D__PgM__Zd_S, + }, + // ZFCVT .D, /Z, .H + { + goOp: AZFCVT, + fixedBits: 0x64da8000, + args: Zn_D__PgZ__Zd_H, + }, + // ZFCVT .D, /Z, .S + { + goOp: AZFCVT, + fixedBits: 0x64dac000, + args: Zn_D__PgZ__Zd_S, + }, + // ZFCVT .H, /M, .D + { + goOp: AZFCVT, + fixedBits: 0x65c9a000, + args: Zn_H__PgM__Zd_D, + }, + // ZFCVT .H, /M, .S + { + goOp: AZFCVT, + fixedBits: 0x6589a000, + args: Zn_H__PgM__Zd_S, + }, + // ZFCVT .H, /Z, .D + { + goOp: AZFCVT, + fixedBits: 0x64daa000, + args: Zn_H__PgZ__Zd_D, + }, + // ZFCVT .H, /Z, .S + { + goOp: AZFCVT, + fixedBits: 0x649aa000, + args: Zn_H__PgZ__Zd_S, + }, + // ZFCVT .S, /M, .D + { + goOp: AZFCVT, + fixedBits: 0x65cba000, + args: Zn_S__PgM__Zd_D, + }, + // ZFCVT .S, /M, .H + { + goOp: AZFCVT, + fixedBits: 0x6588a000, + args: Zn_S__PgM__Zd_H, + }, + // ZFCVT .S, /Z, .D + { + goOp: AZFCVT, + fixedBits: 0x64dae000, + args: Zn_S__PgZ__Zd_D, + }, + // ZFCVT .S, /Z, .H + { + goOp: AZFCVT, + fixedBits: 0x649a8000, + args: Zn_S__PgZ__Zd_H, + }, + }, + // ZFCVTLT + { + // ZFCVTLT .H, /M, .S + { + goOp: AZFCVTLT, + fixedBits: 0x6489a000, + args: Zn_H__PgM__Zd_S, + }, + // ZFCVTLT .H, /Z, .S + { + goOp: AZFCVTLT, + fixedBits: 0x6481a000, + args: Zn_H__PgZ__Zd_S, + }, + // ZFCVTLT .S, /M, .D + { + goOp: AZFCVTLT, + fixedBits: 0x64cba000, + args: Zn_S__PgM__Zd_D, + }, + // ZFCVTLT .S, /Z, .D + { + goOp: AZFCVTLT, + fixedBits: 0x64c3a000, + args: Zn_S__PgZ__Zd_D, + }, + }, + // ZFCVTN + { + // ZFCVTN { .H-.H }, .B + { + goOp: AZFCVTN, + fixedBits: 0x650a3000, + args: Zn1_H_Zn2_H___Zd_B, + }, + }, + // ZFCVTNB + { + // ZFCVTNB { .S-.S }, .B + { + goOp: AZFCVTNB, + fixedBits: 0x650a3400, + args: Zn1_S_Zn2_S___Zd_B, + }, + }, + // ZFCVTNT + { + // ZFCVTNT .D, /M, .S + { + goOp: AZFCVTNT, + fixedBits: 0x64caa000, + args: Zn_D__PgM__Zd_S, + }, + // ZFCVTNT .D, /Z, .S + { + goOp: AZFCVTNT, + fixedBits: 0x64c2a000, + args: Zn_D__PgZ__Zd_S, + }, + // ZFCVTNT .S, /M, .H + { + goOp: AZFCVTNT, + fixedBits: 0x6488a000, + args: Zn_S__PgM__Zd_H, + }, + // ZFCVTNT .S, /Z, .H + { + goOp: AZFCVTNT, + fixedBits: 0x6480a000, + args: Zn_S__PgZ__Zd_H, + }, + // ZFCVTNT { .S-.S }, .B + { + goOp: AZFCVTNT, + fixedBits: 0x650a3c00, + args: Zn1_S_Zn2_S___Zd_B, + }, + }, + // ZFCVTX + { + // ZFCVTX .D, /M, .S + { + goOp: AZFCVTX, + fixedBits: 0x650aa000, + args: Zn_D__PgM__Zd_S, + }, + // ZFCVTX .D, /Z, .S + { + goOp: AZFCVTX, + fixedBits: 0x641ac000, + args: Zn_D__PgZ__Zd_S, + }, + }, + // ZFCVTXNT + { + // ZFCVTXNT .D, /M, .S + { + goOp: AZFCVTXNT, + fixedBits: 0x640aa000, + args: Zn_D__PgM__Zd_S, + }, + // ZFCVTXNT .D, /Z, .S + { + goOp: AZFCVTXNT, + fixedBits: 0x6402a000, + args: Zn_D__PgZ__Zd_S, + }, + }, + // ZFCVTZS + { + // ZFCVTZS .D, /M, .D + { + goOp: AZFCVTZS, + fixedBits: 0x65dea000, + args: Zn_D__PgM__Zd_D, + }, + // ZFCVTZS .D, /M, .S + { + goOp: AZFCVTZS, + fixedBits: 0x65d8a000, + args: Zn_D__PgM__Zd_S, + }, + // ZFCVTZS .D, /Z, .D + { + goOp: AZFCVTZS, + fixedBits: 0x64dfc000, + args: Zn_D__PgZ__Zd_D, + }, + // ZFCVTZS .D, /Z, .S + { + goOp: AZFCVTZS, + fixedBits: 0x64de8000, + args: Zn_D__PgZ__Zd_S, + }, + // ZFCVTZS .H, /M, .D + { + goOp: AZFCVTZS, + fixedBits: 0x655ea000, + args: Zn_H__PgM__Zd_D, + }, + // ZFCVTZS .H, /M, .H + { + goOp: AZFCVTZS, + fixedBits: 0x655aa000, + args: Zn_H__PgM__Zd_H, + }, + // ZFCVTZS .H, /M, .S + { + goOp: AZFCVTZS, + fixedBits: 0x655ca000, + args: Zn_H__PgM__Zd_S, + }, + // ZFCVTZS .H, /Z, .D + { + goOp: AZFCVTZS, + fixedBits: 0x645fc000, + args: Zn_H__PgZ__Zd_D, + }, + // ZFCVTZS .H, /Z, .H + { + goOp: AZFCVTZS, + fixedBits: 0x645ec000, + args: Zn_H__PgZ__Zd_H, + }, + // ZFCVTZS .H, /Z, .S + { + goOp: AZFCVTZS, + fixedBits: 0x645f8000, + args: Zn_H__PgZ__Zd_S, + }, + // ZFCVTZS .S, /M, .D + { + goOp: AZFCVTZS, + fixedBits: 0x65dca000, + args: Zn_S__PgM__Zd_D, + }, + // ZFCVTZS .S, /M, .S + { + goOp: AZFCVTZS, + fixedBits: 0x659ca000, + args: Zn_S__PgM__Zd_S, + }, + // ZFCVTZS .S, /Z, .D + { + goOp: AZFCVTZS, + fixedBits: 0x64df8000, + args: Zn_S__PgZ__Zd_D, + }, + // ZFCVTZS .S, /Z, .S + { + goOp: AZFCVTZS, + fixedBits: 0x649f8000, + args: Zn_S__PgZ__Zd_S, + }, + }, + // ZFCVTZSN + { + // ZFCVTZSN { .-. }, . + { + goOp: AZFCVTZSN, + fixedBits: 0x650d3000, + args: Zn1_Tb_Zn2_Tb___Zd_T, + }, + }, + // ZFCVTZU + { + // ZFCVTZU .D, /M, .D + { + goOp: AZFCVTZU, + fixedBits: 0x65dfa000, + args: Zn_D__PgM__Zd_D, + }, + // ZFCVTZU .D, /M, .S + { + goOp: AZFCVTZU, + fixedBits: 0x65d9a000, + args: Zn_D__PgM__Zd_S, + }, + // ZFCVTZU .D, /Z, .D + { + goOp: AZFCVTZU, + fixedBits: 0x64dfe000, + args: Zn_D__PgZ__Zd_D, + }, + // ZFCVTZU .D, /Z, .S + { + goOp: AZFCVTZU, + fixedBits: 0x64dea000, + args: Zn_D__PgZ__Zd_S, + }, + // ZFCVTZU .H, /M, .D + { + goOp: AZFCVTZU, + fixedBits: 0x655fa000, + args: Zn_H__PgM__Zd_D, + }, + // ZFCVTZU .H, /M, .H + { + goOp: AZFCVTZU, + fixedBits: 0x655ba000, + args: Zn_H__PgM__Zd_H, + }, + // ZFCVTZU .H, /M, .S + { + goOp: AZFCVTZU, + fixedBits: 0x655da000, + args: Zn_H__PgM__Zd_S, + }, + // ZFCVTZU .H, /Z, .D + { + goOp: AZFCVTZU, + fixedBits: 0x645fe000, + args: Zn_H__PgZ__Zd_D, + }, + // ZFCVTZU .H, /Z, .H + { + goOp: AZFCVTZU, + fixedBits: 0x645ee000, + args: Zn_H__PgZ__Zd_H, + }, + // ZFCVTZU .H, /Z, .S + { + goOp: AZFCVTZU, + fixedBits: 0x645fa000, + args: Zn_H__PgZ__Zd_S, + }, + // ZFCVTZU .S, /M, .D + { + goOp: AZFCVTZU, + fixedBits: 0x65dda000, + args: Zn_S__PgM__Zd_D, + }, + // ZFCVTZU .S, /M, .S + { + goOp: AZFCVTZU, + fixedBits: 0x659da000, + args: Zn_S__PgM__Zd_S, + }, + // ZFCVTZU .S, /Z, .D + { + goOp: AZFCVTZU, + fixedBits: 0x64dfa000, + args: Zn_S__PgZ__Zd_D, + }, + // ZFCVTZU .S, /Z, .S + { + goOp: AZFCVTZU, + fixedBits: 0x649fa000, + args: Zn_S__PgZ__Zd_S, + }, + }, + // ZFCVTZUN + { + // ZFCVTZUN { .-. }, . + { + goOp: AZFCVTZUN, + fixedBits: 0x650d3400, + args: Zn1_Tb_Zn2_Tb___Zd_T, + }, + }, + // ZFDIV + { + // ZFDIV ., ., /M, . + { + goOp: AZFDIV, + fixedBits: 0x650d8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFDIVR + { + // ZFDIVR ., ., /M, . + { + goOp: AZFDIVR, + fixedBits: 0x650c8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFDOT + { + // ZFDOT .B, .B, .H + { + goOp: AZFDOT, + fixedBits: 0x64208400, + args: Zm_B__Zn_B__Zda_H, + }, + // ZFDOT .B, .B, .S + { + goOp: AZFDOT, + fixedBits: 0x64608400, + args: Zm_B__Zn_B__Zda_S, + }, + // ZFDOT .H, .H, .S + { + goOp: AZFDOT, + fixedBits: 0x64208000, + args: Zm_H__Zn_H__Zda_S, + }, + // ZFDOT .B[], .B, .H + { + goOp: AZFDOT, + fixedBits: 0x64204400, + args: Zm_B_imm___Zn_B__Zda_H__3, + }, + // ZFDOT .B[], .B, .S + { + goOp: AZFDOT, + fixedBits: 0x64604400, + args: Zm_B_imm___Zn_B__Zda_S__2, + }, + // ZFDOT .H[], .H, .S + { + goOp: AZFDOT, + fixedBits: 0x64204000, + args: Zm_H_imm___Zn_H__Zda_S__3, + }, + }, + // ZFDUP + { + // ZFDUP #, . + { + goOp: AZFDUP, + fixedBits: 0x2539c000, + args: cconst__Zd_T__2, + }, + }, + // ZFEXPA + { + // ZFEXPA ., . + { + goOp: AZFEXPA, + fixedBits: 0x420b800, + args: Zn_T__Zd_T__1, + }, + }, + // ZFLOGB + { + // ZFLOGB ., /M, . + { + goOp: AZFLOGB, + fixedBits: 0x6518a000, + args: Zn_T__PgM__Zd_T__6, + }, + // ZFLOGB ., /Z, . + { + goOp: AZFLOGB, + fixedBits: 0x641e8000, + args: Zn_T__PgZ__Zd_T__6, + }, + }, + // ZFMAD + { + // ZFMAD ., ., /M, . + { + goOp: AZFMAD, + fixedBits: 0x65208000, + args: Za_T__Zm_T__PgM__Zdn_T__1, + }, + }, + // ZFMAX + { + // ZFMAX ., ., /M, . + { + goOp: AZFMAX, + fixedBits: 0x65068000, + args: Zm_T__Zdn_T__PgM__Zdn_T__3, + }, + // ZFMAX , ., /M, . + { + goOp: AZFMAX, + fixedBits: 0x651e8000, + args: const__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZFMAXNM + { + // ZFMAXNM ., ., /M, . + { + goOp: AZFMAXNM, + fixedBits: 0x65048000, + args: Zm_T__Zdn_T__PgM__Zdn_T__3, + }, + // ZFMAXNM , ., /M, . + { + goOp: AZFMAXNM, + fixedBits: 0x651c8000, + args: const__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZFMAXNMP + { + // ZFMAXNMP ., ., /M, . + { + goOp: AZFMAXNMP, + fixedBits: 0x64148000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFMAXNMQV + { + // ZFMAXNMQV ., , . + { + goOp: AZFMAXNMQV, + fixedBits: 0x6414a000, + args: Zn_Tb__Pg__Vd_T__2, + }, + }, + // ZFMAXNMVD + { + // ZFMAXNMVD ., , + { + goOp: AZFMAXNMVD, + fixedBits: 0x65c42000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMAXNMVH + { + // ZFMAXNMVH ., , + { + goOp: AZFMAXNMVH, + fixedBits: 0x65442000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMAXNMVS + { + // ZFMAXNMVS ., , + { + goOp: AZFMAXNMVS, + fixedBits: 0x65842000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMAXP + { + // ZFMAXP ., ., /M, . + { + goOp: AZFMAXP, + fixedBits: 0x64168000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFMAXQV + { + // ZFMAXQV ., , . + { + goOp: AZFMAXQV, + fixedBits: 0x6416a000, + args: Zn_Tb__Pg__Vd_T__2, + }, + }, + // ZFMAXVD + { + // ZFMAXVD ., , + { + goOp: AZFMAXVD, + fixedBits: 0x65c62000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMAXVH + { + // ZFMAXVH ., , + { + goOp: AZFMAXVH, + fixedBits: 0x65462000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMAXVS + { + // ZFMAXVS ., , + { + goOp: AZFMAXVS, + fixedBits: 0x65862000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMIN + { + // ZFMIN ., ., /M, . + { + goOp: AZFMIN, + fixedBits: 0x65078000, + args: Zm_T__Zdn_T__PgM__Zdn_T__3, + }, + // ZFMIN , ., /M, . + { + goOp: AZFMIN, + fixedBits: 0x651f8000, + args: const__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZFMINNM + { + // ZFMINNM ., ., /M, . + { + goOp: AZFMINNM, + fixedBits: 0x65058000, + args: Zm_T__Zdn_T__PgM__Zdn_T__3, + }, + // ZFMINNM , ., /M, . + { + goOp: AZFMINNM, + fixedBits: 0x651d8000, + args: const__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZFMINNMP + { + // ZFMINNMP ., ., /M, . + { + goOp: AZFMINNMP, + fixedBits: 0x64158000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFMINNMQV + { + // ZFMINNMQV ., , . + { + goOp: AZFMINNMQV, + fixedBits: 0x6415a000, + args: Zn_Tb__Pg__Vd_T__2, + }, + }, + // ZFMINNMVD + { + // ZFMINNMVD ., , + { + goOp: AZFMINNMVD, + fixedBits: 0x65c52000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMINNMVH + { + // ZFMINNMVH ., , + { + goOp: AZFMINNMVH, + fixedBits: 0x65452000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMINNMVS + { + // ZFMINNMVS ., , + { + goOp: AZFMINNMVS, + fixedBits: 0x65852000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMINP + { + // ZFMINP ., ., /M, . + { + goOp: AZFMINP, + fixedBits: 0x64178000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFMINQV + { + // ZFMINQV ., , . + { + goOp: AZFMINQV, + fixedBits: 0x6417a000, + args: Zn_Tb__Pg__Vd_T__2, + }, + }, + // ZFMINVD + { + // ZFMINVD ., , + { + goOp: AZFMINVD, + fixedBits: 0x65c72000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMINVH + { + // ZFMINVH ., , + { + goOp: AZFMINVH, + fixedBits: 0x65472000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMINVS + { + // ZFMINVS ., , + { + goOp: AZFMINVS, + fixedBits: 0x65872000, + args: Zn_T__Pg__Vd__2, + }, + }, + // ZFMLA + { + // ZFMLA ., ., /M, . + { + goOp: AZFMLA, + fixedBits: 0x65200000, + args: Zm_T__Zn_T__PgM__Zda_T__1, + }, + // ZFMLA .D[], .D, .D + { + goOp: AZFMLA, + fixedBits: 0x64e00000, + args: Zm_D_imm___Zn_D__Zda_D__2, + }, + // ZFMLA .H[], .H, .H + { + goOp: AZFMLA, + fixedBits: 0x64200000, + args: Zm_H_imm___Zn_H__Zda_H__3, + }, + // ZFMLA .S[], .S, .S + { + goOp: AZFMLA, + fixedBits: 0x64a00000, + args: Zm_S_imm___Zn_S__Zda_S__2, + }, + }, + // ZFMLALB + { + // ZFMLALB .B, .B, .H + { + goOp: AZFMLALB, + fixedBits: 0x64a08800, + args: Zm_B__Zn_B__Zda_H, + }, + // ZFMLALB .H, .H, .S + { + goOp: AZFMLALB, + fixedBits: 0x64a08000, + args: Zm_H__Zn_H__Zda_S, + }, + // ZFMLALB .B[], .B, .H + { + goOp: AZFMLALB, + fixedBits: 0x64205000, + args: Zm_B_imm___Zn_B__Zda_H__1, + }, + // ZFMLALB .H[], .H, .S + { + goOp: AZFMLALB, + fixedBits: 0x64a04000, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, + }, + // ZFMLALLBB + { + // ZFMLALLBB .B, .B, .S + { + goOp: AZFMLALLBB, + fixedBits: 0x64208800, + args: Zm_B__Zn_B__Zda_S, + }, + // ZFMLALLBB .B[], .B, .S + { + goOp: AZFMLALLBB, + fixedBits: 0x6420c000, + args: Zm_B_imm___Zn_B__Zda_S__1, + }, + }, + // ZFMLALLBT + { + // ZFMLALLBT .B, .B, .S + { + goOp: AZFMLALLBT, + fixedBits: 0x64209800, + args: Zm_B__Zn_B__Zda_S, + }, + // ZFMLALLBT .B[], .B, .S + { + goOp: AZFMLALLBT, + fixedBits: 0x6460c000, + args: Zm_B_imm___Zn_B__Zda_S__1, + }, + }, + // ZFMLALLTB + { + // ZFMLALLTB .B, .B, .S + { + goOp: AZFMLALLTB, + fixedBits: 0x6420a800, + args: Zm_B__Zn_B__Zda_S, + }, + // ZFMLALLTB .B[], .B, .S + { + goOp: AZFMLALLTB, + fixedBits: 0x64a0c000, + args: Zm_B_imm___Zn_B__Zda_S__1, + }, + }, + // ZFMLALLTT + { + // ZFMLALLTT .B, .B, .S + { + goOp: AZFMLALLTT, + fixedBits: 0x6420b800, + args: Zm_B__Zn_B__Zda_S, + }, + // ZFMLALLTT .B[], .B, .S + { + goOp: AZFMLALLTT, + fixedBits: 0x64e0c000, + args: Zm_B_imm___Zn_B__Zda_S__1, + }, + }, + // ZFMLALT + { + // ZFMLALT .B, .B, .H + { + goOp: AZFMLALT, + fixedBits: 0x64a09800, + args: Zm_B__Zn_B__Zda_H, + }, + // ZFMLALT .H, .H, .S + { + goOp: AZFMLALT, + fixedBits: 0x64a08400, + args: Zm_H__Zn_H__Zda_S, + }, + // ZFMLALT .B[], .B, .H + { + goOp: AZFMLALT, + fixedBits: 0x64a05000, + args: Zm_B_imm___Zn_B__Zda_H__1, + }, + // ZFMLALT .H[], .H, .S + { + goOp: AZFMLALT, + fixedBits: 0x64a04400, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, + }, + // ZFMLS + { + // ZFMLS ., ., /M, . + { + goOp: AZFMLS, + fixedBits: 0x65202000, + args: Zm_T__Zn_T__PgM__Zda_T__1, + }, + // ZFMLS .D[], .D, .D + { + goOp: AZFMLS, + fixedBits: 0x64e00400, + args: Zm_D_imm___Zn_D__Zda_D__2, + }, + // ZFMLS .H[], .H, .H + { + goOp: AZFMLS, + fixedBits: 0x64200400, + args: Zm_H_imm___Zn_H__Zda_H__3, + }, + // ZFMLS .S[], .S, .S + { + goOp: AZFMLS, + fixedBits: 0x64a00400, + args: Zm_S_imm___Zn_S__Zda_S__2, + }, + }, + // ZFMLSLB + { + // ZFMLSLB .H, .H, .S + { + goOp: AZFMLSLB, + fixedBits: 0x64a0a000, + args: Zm_H__Zn_H__Zda_S, + }, + // ZFMLSLB .H[], .H, .S + { + goOp: AZFMLSLB, + fixedBits: 0x64a06000, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, + }, + // ZFMLSLT + { + // ZFMLSLT .H, .H, .S + { + goOp: AZFMLSLT, + fixedBits: 0x64a0a400, + args: Zm_H__Zn_H__Zda_S, + }, + // ZFMLSLT .H[], .H, .S + { + goOp: AZFMLSLT, + fixedBits: 0x64a06400, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, + }, + // ZFMMLA + { + // ZFMMLA .B, .B, .H + { + goOp: AZFMMLA, + fixedBits: 0x6460e000, + args: Zm_B__Zn_B__Zda_H, + }, + // ZFMMLA .B, .B, .S + { + goOp: AZFMMLA, + fixedBits: 0x6420e000, + args: Zm_B__Zn_B__Zda_S, + }, + // ZFMMLA .D, .D, .D + { + goOp: AZFMMLA, + fixedBits: 0x64e0e400, + args: Zm_D__Zn_D__Zda_D, + }, + // ZFMMLA .H, .H, .H + { + goOp: AZFMMLA, + fixedBits: 0x64a0e000, + args: Zm_H__Zn_H__Zda_H, + }, + // ZFMMLA .H, .H, .S + { + goOp: AZFMMLA, + fixedBits: 0x6420e400, + args: Zm_H__Zn_H__Zda_S, + }, + // ZFMMLA .S, .S, .S + { + goOp: AZFMMLA, + fixedBits: 0x64a0e400, + args: Zm_S__Zn_S__Zda_S, + }, + }, + // ZFMSB + { + // ZFMSB ., ., /M, . + { + goOp: AZFMSB, + fixedBits: 0x6520a000, + args: Za_T__Zm_T__PgM__Zdn_T__1, + }, + }, + // ZFMUL + { + // ZFMUL ., ., /M, . + { + goOp: AZFMUL, + fixedBits: 0x65028000, + args: Zm_T__Zdn_T__PgM__Zdn_T__3, + }, + // ZFMUL ., ., . + { + goOp: AZFMUL, + fixedBits: 0x65000800, + args: Zm_T__Zn_T__Zd_T__2, + }, + // ZFMUL .D[], .D, .D + { + goOp: AZFMUL, + fixedBits: 0x64e02000, + args: Zm_D_imm___Zn_D__Zd_D__2, + }, + // ZFMUL .H[], .H, .H + { + goOp: AZFMUL, + fixedBits: 0x64202000, + args: Zm_H_imm___Zn_H__Zd_H__3, + }, + // ZFMUL .S[], .S, .S + { + goOp: AZFMUL, + fixedBits: 0x64a02000, + args: Zm_S_imm___Zn_S__Zd_S__2, + }, + // ZFMUL , ., /M, . + { + goOp: AZFMUL, + fixedBits: 0x651a8000, + args: const__Zdn_T__PgM__Zdn_T__3, + }, + }, + // ZFMULX + { + // ZFMULX ., ., /M, . + { + goOp: AZFMULX, + fixedBits: 0x650a8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFNEG + { + // ZFNEG ., /M, . + { + goOp: AZFNEG, + fixedBits: 0x41da000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFNEG ., /Z, . + { + goOp: AZFNEG, + fixedBits: 0x40da000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFNMAD + { + // ZFNMAD ., ., /M, . + { + goOp: AZFNMAD, + fixedBits: 0x6520c000, + args: Za_T__Zm_T__PgM__Zdn_T__1, + }, + }, + // ZFNMLA + { + // ZFNMLA ., ., /M, . + { + goOp: AZFNMLA, + fixedBits: 0x65204000, + args: Zm_T__Zn_T__PgM__Zda_T__1, + }, + }, + // ZFNMLS + { + // ZFNMLS ., ., /M, . + { + goOp: AZFNMLS, + fixedBits: 0x65206000, + args: Zm_T__Zn_T__PgM__Zda_T__1, + }, + }, + // ZFNMSB + { + // ZFNMSB ., ., /M, . + { + goOp: AZFNMSB, + fixedBits: 0x6520e000, + args: Za_T__Zm_T__PgM__Zdn_T__1, + }, + }, + // ZFRECPE + { + // ZFRECPE ., . + { + goOp: AZFRECPE, + fixedBits: 0x650e3000, + args: Zn_T__Zd_T__1, + }, + }, + // ZFRECPS + { + // ZFRECPS ., ., . + { + goOp: AZFRECPS, + fixedBits: 0x65001800, + args: Zm_T__Zn_T__Zd_T__3, + }, + }, + // ZFRECPX + { + // ZFRECPX ., /M, . + { + goOp: AZFRECPX, + fixedBits: 0x650ca000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFRECPX ., /Z, . + { + goOp: AZFRECPX, + fixedBits: 0x641b8000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFRINT32X + { + // ZFRINT32X ., /M, . + { + goOp: AZFRINT32X, + fixedBits: 0x6511a000, + args: Zn_T__PgM__Zd_T__3, + }, + // ZFRINT32X ., /Z, . + { + goOp: AZFRINT32X, + fixedBits: 0x641ca000, + args: Zn_T__PgZ__Zd_T__3, + }, + }, + // ZFRINT32Z + { + // ZFRINT32Z ., /M, . + { + goOp: AZFRINT32Z, + fixedBits: 0x6510a000, + args: Zn_T__PgM__Zd_T__3, + }, + // ZFRINT32Z ., /Z, . + { + goOp: AZFRINT32Z, + fixedBits: 0x641c8000, + args: Zn_T__PgZ__Zd_T__3, + }, + }, + // ZFRINT64X + { + // ZFRINT64X ., /M, . + { + goOp: AZFRINT64X, + fixedBits: 0x6515a000, + args: Zn_T__PgM__Zd_T__3, + }, + // ZFRINT64X ., /Z, . + { + goOp: AZFRINT64X, + fixedBits: 0x641da000, + args: Zn_T__PgZ__Zd_T__3, + }, + }, + // ZFRINT64Z + { + // ZFRINT64Z ., /M, . + { + goOp: AZFRINT64Z, + fixedBits: 0x6514a000, + args: Zn_T__PgM__Zd_T__3, + }, + // ZFRINT64Z ., /Z, . + { + goOp: AZFRINT64Z, + fixedBits: 0x641d8000, + args: Zn_T__PgZ__Zd_T__3, + }, + }, + // ZFRINTA + { + // ZFRINTA ., /M, . + { + goOp: AZFRINTA, + fixedBits: 0x6504a000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFRINTA ., /Z, . + { + goOp: AZFRINTA, + fixedBits: 0x64198000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFRINTI + { + // ZFRINTI ., /M, . + { + goOp: AZFRINTI, + fixedBits: 0x6507a000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFRINTI ., /Z, . + { + goOp: AZFRINTI, + fixedBits: 0x6419e000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFRINTM + { + // ZFRINTM ., /M, . + { + goOp: AZFRINTM, + fixedBits: 0x6502a000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFRINTM ., /Z, . + { + goOp: AZFRINTM, + fixedBits: 0x6418c000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFRINTN + { + // ZFRINTN ., /M, . + { + goOp: AZFRINTN, + fixedBits: 0x6500a000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFRINTN ., /Z, . + { + goOp: AZFRINTN, + fixedBits: 0x64188000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFRINTP + { + // ZFRINTP ., /M, . + { + goOp: AZFRINTP, + fixedBits: 0x6501a000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFRINTP ., /Z, . + { + goOp: AZFRINTP, + fixedBits: 0x6418a000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFRINTX + { + // ZFRINTX ., /M, . + { + goOp: AZFRINTX, + fixedBits: 0x6506a000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFRINTX ., /Z, . + { + goOp: AZFRINTX, + fixedBits: 0x6419c000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFRINTZ + { + // ZFRINTZ ., /M, . + { + goOp: AZFRINTZ, + fixedBits: 0x6503a000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFRINTZ ., /Z, . + { + goOp: AZFRINTZ, + fixedBits: 0x6418e000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFRSQRTE + { + // ZFRSQRTE ., . + { + goOp: AZFRSQRTE, + fixedBits: 0x650f3000, + args: Zn_T__Zd_T__1, + }, + }, + // ZFRSQRTS + { + // ZFRSQRTS ., ., . + { + goOp: AZFRSQRTS, + fixedBits: 0x65001c00, + args: Zm_T__Zn_T__Zd_T__3, + }, + }, + // ZFSCALE + { + // ZFSCALE ., ., /M, . + { + goOp: AZFSCALE, + fixedBits: 0x65098000, + args: Zm_T__Zdn_T__PgM__Zdn_T__3, + }, + }, + // ZFSQRT + { + // ZFSQRT ., /M, . + { + goOp: AZFSQRT, + fixedBits: 0x650da000, + args: Zn_T__PgM__Zd_T__1, + }, + // ZFSQRT ., /Z, . + { + goOp: AZFSQRT, + fixedBits: 0x641ba000, + args: Zn_T__PgZ__Zd_T__1, + }, + }, + // ZFSUB + { + // ZFSUB ., ., /M, . + { + goOp: AZFSUB, + fixedBits: 0x65018000, + args: Zm_T__Zdn_T__PgM__Zdn_T__3, + }, + // ZFSUB ., ., . + { + goOp: AZFSUB, + fixedBits: 0x65000400, + args: Zm_T__Zn_T__Zd_T__2, + }, + // ZFSUB , ., /M, . + { + goOp: AZFSUB, + fixedBits: 0x65198000, + args: const__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFSUBR + { + // ZFSUBR ., ., /M, . + { + goOp: AZFSUBR, + fixedBits: 0x65038000, + args: Zm_T__Zdn_T__PgM__Zdn_T__2, + }, + // ZFSUBR , ., /M, . + { + goOp: AZFSUBR, + fixedBits: 0x651b8000, + args: const__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFTMAD + { + // ZFTMAD #, ., ., . + { + goOp: AZFTMAD, + fixedBits: 0x65108000, + args: cimm__Zm_T__Zdn_T__Zdn_T, + }, + }, + // ZFTSMUL + { + // ZFTSMUL ., ., . + { + goOp: AZFTSMUL, + fixedBits: 0x65000c00, + args: Zm_T__Zn_T__Zd_T__3, + }, + }, + // ZFTSSEL + { + // ZFTSSEL ., ., . + { + goOp: AZFTSSEL, + fixedBits: 0x420b000, + args: Zm_T__Zn_T__Zd_T__3, + }, + }, + // ZHISTCNT + { + // ZHISTCNT ., ., /Z, . + { + goOp: AZHISTCNT, + fixedBits: 0x45a0c000, + args: Zm_T__Zn_T__PgZ__Zd_T, + }, + }, + // ZHISTSEG + { + // ZHISTSEG .B, .B, .B + { + goOp: AZHISTSEG, + fixedBits: 0x4520a000, + args: Zm_B__Zn_B__Zd_B, + }, + }, + // ZINCP + { + // ZINCP ., . + { + goOp: AZINCP, + fixedBits: 0x252c8000, + args: Pm_T__Zdn_T, + }, + }, + // ZINDEX + { + // ZINDEX , , . + { + goOp: AZINDEX, + fixedBits: 0x4e04c00, + args: Rm__Rn__Zd_T, + }, + // ZINDEX , #, . + { + goOp: AZINDEX, + fixedBits: 0x4e04800, + args: Rm__cimm__Zd_T, + }, + // ZINDEX #, #, . + { + goOp: AZINDEX, + fixedBits: 0x4204000, + args: cimm2__cimm1__Zd_T, + }, + // ZINDEX #, , . + { + goOp: AZINDEX, + fixedBits: 0x4e04400, + args: cimm__Rn__Zd_T, + }, + }, + // ZINDEXW + { + // ZINDEXW , , . + { + goOp: AZINDEXW, + fixedBits: 0x4204c00, + args: Rm__Rn__Zd_T, + }, + // ZINDEXW , #, . + { + goOp: AZINDEXW, + fixedBits: 0x4204800, + args: Rm__cimm__Zd_T, + }, + // ZINDEXW #, , . + { + goOp: AZINDEXW, + fixedBits: 0x4204400, + args: cimm__Rn__Zd_T, + }, + }, + // ZINSR + { + // ZINSR , . + { + goOp: AZINSR, + fixedBits: 0x5e43800, + args: Rm__Zdn_T, + }, + }, + // ZINSRB + { + // ZINSRB , . + { + goOp: AZINSRB, + fixedBits: 0x5343800, + args: Vm__Zdn_T, + }, + }, + // ZINSRD + { + // ZINSRD , . + { + goOp: AZINSRD, + fixedBits: 0x5f43800, + args: Vm__Zdn_T, + }, + }, + // ZINSRH + { + // ZINSRH , . + { + goOp: AZINSRH, + fixedBits: 0x5743800, + args: Vm__Zdn_T, + }, + }, + // ZINSRS + { + // ZINSRS , . + { + goOp: AZINSRS, + fixedBits: 0x5b43800, + args: Vm__Zdn_T, + }, + }, + // ZINSRW + { + // ZINSRW , . + { + goOp: AZINSRW, + fixedBits: 0x5243800, + args: Rm__Zdn_T, + }, + }, + // ZLASTA + { + // ZLASTA ., , + { + goOp: AZLASTA, + fixedBits: 0x5e0a000, + args: Zn_T__Pg__Rd, + }, + }, + // ZLASTAB + { + // ZLASTAB ., , + { + goOp: AZLASTAB, + fixedBits: 0x5228000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZLASTAD + { + // ZLASTAD ., , + { + goOp: AZLASTAD, + fixedBits: 0x5e28000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZLASTAH + { + // ZLASTAH ., , + { + goOp: AZLASTAH, + fixedBits: 0x5628000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZLASTAS + { + // ZLASTAS ., , + { + goOp: AZLASTAS, + fixedBits: 0x5a28000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZLASTAW + { + // ZLASTAW ., , + { + goOp: AZLASTAW, + fixedBits: 0x520a000, + args: Zn_T__Pg__Rd, + }, + }, + // ZLASTB + { + // ZLASTB ., , + { + goOp: AZLASTB, + fixedBits: 0x5e1a000, + args: Zn_T__Pg__Rd, + }, + }, + // ZLASTBB + { + // ZLASTBB ., , + { + goOp: AZLASTBB, + fixedBits: 0x5238000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZLASTBD + { + // ZLASTBD ., , + { + goOp: AZLASTBD, + fixedBits: 0x5e38000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZLASTBH + { + // ZLASTBH ., , + { + goOp: AZLASTBH, + fixedBits: 0x5638000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZLASTBS + { + // ZLASTBS ., , + { + goOp: AZLASTBS, + fixedBits: 0x5a38000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZLASTBW + { + // ZLASTBW ., , + { + goOp: AZLASTBW, + fixedBits: 0x521a000, + args: Zn_T__Pg__Rd, + }, + }, + // ZLD1B + { + // ZLD1B [, ], /Z, { .B } + { + goOp: AZLD1B, + fixedBits: 0xa4004000, + args: XnSP__Xm___PgZ___Zt_B_, + }, + // ZLD1B [, ], /Z, { .D } + { + goOp: AZLD1B, + fixedBits: 0xa4604000, + args: XnSP__Xm___PgZ___Zt_D_, + }, + // ZLD1B [, ], /Z, { .H } + { + goOp: AZLD1B, + fixedBits: 0xa4204000, + args: XnSP__Xm___PgZ___Zt_H_, + }, + // ZLD1B [, ], /Z, { .S } + { + goOp: AZLD1B, + fixedBits: 0xa4404000, + args: XnSP__Xm___PgZ___Zt_S_, + }, + // ZLD1B [, .D], /Z, { .D } + { + goOp: AZLD1B, + fixedBits: 0xc440c000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1B [, .D, ], /Z, { .D } + { + goOp: AZLD1B, + fixedBits: 0xc4004000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1B [, .S, ], /Z, { .S } + { + goOp: AZLD1B, + fixedBits: 0x84004000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLD1B [.D{, #}], /Z, { .D } + { + goOp: AZLD1B, + fixedBits: 0xc420c000, + args: Zn_D__cimm___PgZ___Zt_D___1, + }, + // ZLD1B [.S{, #}], /Z, { .S } + { + goOp: AZLD1B, + fixedBits: 0x8420c000, + args: Zn_S__cimm___PgZ___Zt_S___1, + }, + // ZLD1B [{, #, MUL VL}], /Z, { .B } + { + goOp: AZLD1B, + fixedBits: 0xa400a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_B_, + }, + // ZLD1B [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLD1B, + fixedBits: 0xa460a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLD1B [{, #, MUL VL}], /Z, { .H } + { + goOp: AZLD1B, + fixedBits: 0xa420a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_H_, + }, + // ZLD1B [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLD1B, + fixedBits: 0xa440a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + // ZLD1B [, ], /Z, { .B-.B } + { + goOp: AZLD1B, + fixedBits: 0xa0000000, + args: XnSP__Xm___PNgZ___Zt1_B_Zt2_B_, + }, + // ZLD1B [, ], /Z, { .B-.B } + { + goOp: AZLD1B, + fixedBits: 0xa0008000, + args: XnSP__Xm___PNgZ___Zt1_B_Zt4_B_, + }, + // ZLD1B [{, #, MUL VL}], /Z, { .B-.B } + { + goOp: AZLD1B, + fixedBits: 0xa0400000, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt2_B_, + }, + // ZLD1B [{, #, MUL VL}], /Z, { .B-.B } + { + goOp: AZLD1B, + fixedBits: 0xa0408000, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt4_B_, + }, + }, + // ZLD1D + { + // ZLD1D [, , LSL #3], /Z, { .D } + { + goOp: AZLD1D, + fixedBits: 0xa5e04000, + args: XnSP__Xm__LSL_c3___PgZ___Zt_D_, + }, + // ZLD1D [, , LSL #3], /Z, { .Q } + { + goOp: AZLD1D, + fixedBits: 0xa5808000, + args: XnSP__Xm__LSL_c3___PgZ___Zt_Q_, + }, + // ZLD1D [, .D, LSL #3], /Z, { .D } + { + goOp: AZLD1D, + fixedBits: 0xc5e0c000, + args: XnSP__Zm_D__LSL_c3___PgZ___Zt_D_, + }, + // ZLD1D [, .D], /Z, { .D } + { + goOp: AZLD1D, + fixedBits: 0xc5c0c000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1D [, .D, ], /Z, { .D } + { + goOp: AZLD1D, + fixedBits: 0xc5804000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1D [, .D, #3], /Z, { .D } + { + goOp: AZLD1D, + fixedBits: 0xc5a04000, + args: XnSP__Zm_D__mod_c3___PgZ___Zt_D_, + }, + // ZLD1D [.D{, #}], /Z, { .D } + { + goOp: AZLD1D, + fixedBits: 0xc5a0c000, + args: Zn_D__cimm___PgZ___Zt_D___4, + }, + // ZLD1D [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLD1D, + fixedBits: 0xa5e0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLD1D [{, #, MUL VL}], /Z, { .Q } + { + goOp: AZLD1D, + fixedBits: 0xa5902000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_Q_, + }, + // ZLD1D [, , LSL #3], /Z, { .D-.D } + { + goOp: AZLD1D, + fixedBits: 0xa0006000, + args: XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt2_D_, + }, + // ZLD1D [, , LSL #3], /Z, { .D-.D } + { + goOp: AZLD1D, + fixedBits: 0xa000e000, + args: XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt4_D_, + }, + // ZLD1D [{, #, MUL VL}], /Z, { .D-.D } + { + goOp: AZLD1D, + fixedBits: 0xa0406000, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt2_D_, + }, + // ZLD1D [{, #, MUL VL}], /Z, { .D-.D } + { + goOp: AZLD1D, + fixedBits: 0xa040e000, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt4_D_, + }, + }, + // ZLD1H + { + // ZLD1H [, , LSL #1], /Z, { .D } + { + goOp: AZLD1H, + fixedBits: 0xa4e04000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_D_, + }, + // ZLD1H [, , LSL #1], /Z, { .H } + { + goOp: AZLD1H, + fixedBits: 0xa4a04000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_H_, + }, + // ZLD1H [, , LSL #1], /Z, { .S } + { + goOp: AZLD1H, + fixedBits: 0xa4c04000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_S_, + }, + // ZLD1H [, .D, LSL #1], /Z, { .D } + { + goOp: AZLD1H, + fixedBits: 0xc4e0c000, + args: XnSP__Zm_D__LSL_c1___PgZ___Zt_D_, + }, + // ZLD1H [, .D], /Z, { .D } + { + goOp: AZLD1H, + fixedBits: 0xc4c0c000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1H [, .D, ], /Z, { .D } + { + goOp: AZLD1H, + fixedBits: 0xc4804000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1H [, .D, #1], /Z, { .D } + { + goOp: AZLD1H, + fixedBits: 0xc4a04000, + args: XnSP__Zm_D__mod_c1___PgZ___Zt_D_, + }, + // ZLD1H [, .S, ], /Z, { .S } + { + goOp: AZLD1H, + fixedBits: 0x84804000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLD1H [, .S, #1], /Z, { .S } + { + goOp: AZLD1H, + fixedBits: 0x84a04000, + args: XnSP__Zm_S__mod_c1___PgZ___Zt_S_, + }, + // ZLD1H [.D{, #}], /Z, { .D } + { + goOp: AZLD1H, + fixedBits: 0xc4a0c000, + args: Zn_D__cimm___PgZ___Zt_D___2, + }, + // ZLD1H [.S{, #}], /Z, { .S } + { + goOp: AZLD1H, + fixedBits: 0x84a0c000, + args: Zn_S__cimm___PgZ___Zt_S___2, + }, + // ZLD1H [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLD1H, + fixedBits: 0xa4e0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLD1H [{, #, MUL VL}], /Z, { .H } + { + goOp: AZLD1H, + fixedBits: 0xa4a0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_H_, + }, + // ZLD1H [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLD1H, + fixedBits: 0xa4c0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + // ZLD1H [, , LSL #1], /Z, { .H-.H } + { + goOp: AZLD1H, + fixedBits: 0xa0002000, + args: XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt2_H_, + }, + // ZLD1H [, , LSL #1], /Z, { .H-.H } + { + goOp: AZLD1H, + fixedBits: 0xa000a000, + args: XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt4_H_, + }, + // ZLD1H [{, #, MUL VL}], /Z, { .H-.H } + { + goOp: AZLD1H, + fixedBits: 0xa0402000, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt2_H_, + }, + // ZLD1H [{, #, MUL VL}], /Z, { .H-.H } + { + goOp: AZLD1H, + fixedBits: 0xa040a000, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt4_H_, + }, + }, + // ZLD1Q + { + // ZLD1Q [.D{, }], /Z, { .Q } + { + goOp: AZLD1Q, + fixedBits: 0xc400a000, + args: Zn_D__Xm___PgZ___Zt_Q_, + }, + }, + // ZLD1RB + { + // ZLD1RB [{, #}], /Z, { .B } + { + goOp: AZLD1RB, + fixedBits: 0x84408000, + args: XnSP__cimm___PgZ___Zt_B___1, + }, + // ZLD1RB [{, #}], /Z, { .D } + { + goOp: AZLD1RB, + fixedBits: 0x8440e000, + args: XnSP__cimm___PgZ___Zt_D___1, + }, + // ZLD1RB [{, #}], /Z, { .H } + { + goOp: AZLD1RB, + fixedBits: 0x8440a000, + args: XnSP__cimm___PgZ___Zt_H___1, + }, + // ZLD1RB [{, #}], /Z, { .S } + { + goOp: AZLD1RB, + fixedBits: 0x8440c000, + args: XnSP__cimm___PgZ___Zt_S___1, + }, + }, + // ZLD1RD + { + // ZLD1RD [{, #}], /Z, { .D } + { + goOp: AZLD1RD, + fixedBits: 0x85c0e000, + args: XnSP__cimm___PgZ___Zt_D___4, + }, + }, + // ZLD1RH + { + // ZLD1RH [{, #}], /Z, { .D } + { + goOp: AZLD1RH, + fixedBits: 0x84c0e000, + args: XnSP__cimm___PgZ___Zt_D___2, + }, + // ZLD1RH [{, #}], /Z, { .H } + { + goOp: AZLD1RH, + fixedBits: 0x84c0a000, + args: XnSP__cimm___PgZ___Zt_H___2, + }, + // ZLD1RH [{, #}], /Z, { .S } + { + goOp: AZLD1RH, + fixedBits: 0x84c0c000, + args: XnSP__cimm___PgZ___Zt_S___2, + }, + }, + // ZLD1ROB + { + // ZLD1ROB [, ], /Z, { .B } + { + goOp: AZLD1ROB, + fixedBits: 0xa4200000, + args: XnSP__Xm___PgZ___Zt_B_, + }, + // ZLD1ROB [{, #}], /Z, { .B } + { + goOp: AZLD1ROB, + fixedBits: 0xa4202000, + args: XnSP__cimm___PgZ___Zt_B___2, + }, + }, + // ZLD1ROD + { + // ZLD1ROD [, , LSL #3], /Z, { .D } + { + goOp: AZLD1ROD, + fixedBits: 0xa5a00000, + args: XnSP__Xm__LSL_c3___PgZ___Zt_D_, + }, + // ZLD1ROD [{, #}], /Z, { .D } + { + goOp: AZLD1ROD, + fixedBits: 0xa5a02000, + args: XnSP__cimm___PgZ___Zt_D___5, + }, + }, + // ZLD1ROH + { + // ZLD1ROH [, , LSL #1], /Z, { .H } + { + goOp: AZLD1ROH, + fixedBits: 0xa4a00000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_H_, + }, + // ZLD1ROH [{, #}], /Z, { .H } + { + goOp: AZLD1ROH, + fixedBits: 0xa4a02000, + args: XnSP__cimm___PgZ___Zt_H___3, + }, + }, + // ZLD1ROW + { + // ZLD1ROW [, , LSL #2], /Z, { .S } + { + goOp: AZLD1ROW, + fixedBits: 0xa5200000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_S_, + }, + // ZLD1ROW [{, #}], /Z, { .S } + { + goOp: AZLD1ROW, + fixedBits: 0xa5202000, + args: XnSP__cimm___PgZ___Zt_S___3, + }, + }, + // ZLD1RQB + { + // ZLD1RQB [, ], /Z, { .B } + { + goOp: AZLD1RQB, + fixedBits: 0xa4000000, + args: XnSP__Xm___PgZ___Zt_B_, + }, + // ZLD1RQB [{, #}], /Z, { .B } + { + goOp: AZLD1RQB, + fixedBits: 0xa4002000, + args: XnSP__cimm___PgZ___Zt_B___3, + }, + }, + // ZLD1RQD + { + // ZLD1RQD [, , LSL #3], /Z, { .D } + { + goOp: AZLD1RQD, + fixedBits: 0xa5800000, + args: XnSP__Xm__LSL_c3___PgZ___Zt_D_, + }, + // ZLD1RQD [{, #}], /Z, { .D } + { + goOp: AZLD1RQD, + fixedBits: 0xa5802000, + args: XnSP__cimm___PgZ___Zt_D___6, + }, + }, + // ZLD1RQH + { + // ZLD1RQH [, , LSL #1], /Z, { .H } + { + goOp: AZLD1RQH, + fixedBits: 0xa4800000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_H_, + }, + // ZLD1RQH [{, #}], /Z, { .H } + { + goOp: AZLD1RQH, + fixedBits: 0xa4802000, + args: XnSP__cimm___PgZ___Zt_H___4, + }, + }, + // ZLD1RQW + { + // ZLD1RQW [, , LSL #2], /Z, { .S } + { + goOp: AZLD1RQW, + fixedBits: 0xa5000000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_S_, + }, + // ZLD1RQW [{, #}], /Z, { .S } + { + goOp: AZLD1RQW, + fixedBits: 0xa5002000, + args: XnSP__cimm___PgZ___Zt_S___4, + }, + }, + // ZLD1RSB + { + // ZLD1RSB [{, #}], /Z, { .D } + { + goOp: AZLD1RSB, + fixedBits: 0x85c08000, + args: XnSP__cimm___PgZ___Zt_D___1, + }, + // ZLD1RSB [{, #}], /Z, { .H } + { + goOp: AZLD1RSB, + fixedBits: 0x85c0c000, + args: XnSP__cimm___PgZ___Zt_H___1, + }, + // ZLD1RSB [{, #}], /Z, { .S } + { + goOp: AZLD1RSB, + fixedBits: 0x85c0a000, + args: XnSP__cimm___PgZ___Zt_S___1, + }, + }, + // ZLD1RSH + { + // ZLD1RSH [{, #}], /Z, { .D } + { + goOp: AZLD1RSH, + fixedBits: 0x85408000, + args: XnSP__cimm___PgZ___Zt_D___2, + }, + // ZLD1RSH [{, #}], /Z, { .S } + { + goOp: AZLD1RSH, + fixedBits: 0x8540a000, + args: XnSP__cimm___PgZ___Zt_S___2, + }, + }, + // ZLD1RSW + { + // ZLD1RSW [{, #}], /Z, { .D } + { + goOp: AZLD1RSW, + fixedBits: 0x84c08000, + args: XnSP__cimm___PgZ___Zt_D___3, + }, + }, + // ZLD1RW + { + // ZLD1RW [{, #}], /Z, { .D } + { + goOp: AZLD1RW, + fixedBits: 0x8540e000, + args: XnSP__cimm___PgZ___Zt_D___3, + }, + // ZLD1RW [{, #}], /Z, { .S } + { + goOp: AZLD1RW, + fixedBits: 0x8540c000, + args: XnSP__cimm___PgZ___Zt_S___5, + }, + }, + // ZLD1SB + { + // ZLD1SB [, ], /Z, { .D } + { + goOp: AZLD1SB, + fixedBits: 0xa5804000, + args: XnSP__Xm___PgZ___Zt_D_, + }, + // ZLD1SB [, ], /Z, { .H } + { + goOp: AZLD1SB, + fixedBits: 0xa5c04000, + args: XnSP__Xm___PgZ___Zt_H_, + }, + // ZLD1SB [, ], /Z, { .S } + { + goOp: AZLD1SB, + fixedBits: 0xa5a04000, + args: XnSP__Xm___PgZ___Zt_S_, + }, + // ZLD1SB [, .D], /Z, { .D } + { + goOp: AZLD1SB, + fixedBits: 0xc4408000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1SB [, .D, ], /Z, { .D } + { + goOp: AZLD1SB, + fixedBits: 0xc4000000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1SB [, .S, ], /Z, { .S } + { + goOp: AZLD1SB, + fixedBits: 0x84000000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLD1SB [.D{, #}], /Z, { .D } + { + goOp: AZLD1SB, + fixedBits: 0xc4208000, + args: Zn_D__cimm___PgZ___Zt_D___1, + }, + // ZLD1SB [.S{, #}], /Z, { .S } + { + goOp: AZLD1SB, + fixedBits: 0x84208000, + args: Zn_S__cimm___PgZ___Zt_S___1, + }, + // ZLD1SB [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLD1SB, + fixedBits: 0xa580a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLD1SB [{, #, MUL VL}], /Z, { .H } + { + goOp: AZLD1SB, + fixedBits: 0xa5c0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_H_, + }, + // ZLD1SB [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLD1SB, + fixedBits: 0xa5a0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + }, + // ZLD1SH + { + // ZLD1SH [, , LSL #1], /Z, { .D } + { + goOp: AZLD1SH, + fixedBits: 0xa5004000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_D_, + }, + // ZLD1SH [, , LSL #1], /Z, { .S } + { + goOp: AZLD1SH, + fixedBits: 0xa5204000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_S_, + }, + // ZLD1SH [, .D, LSL #1], /Z, { .D } + { + goOp: AZLD1SH, + fixedBits: 0xc4e08000, + args: XnSP__Zm_D__LSL_c1___PgZ___Zt_D_, + }, + // ZLD1SH [, .D], /Z, { .D } + { + goOp: AZLD1SH, + fixedBits: 0xc4c08000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1SH [, .D, ], /Z, { .D } + { + goOp: AZLD1SH, + fixedBits: 0xc4800000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1SH [, .D, #1], /Z, { .D } + { + goOp: AZLD1SH, + fixedBits: 0xc4a00000, + args: XnSP__Zm_D__mod_c1___PgZ___Zt_D_, + }, + // ZLD1SH [, .S, ], /Z, { .S } + { + goOp: AZLD1SH, + fixedBits: 0x84800000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLD1SH [, .S, #1], /Z, { .S } + { + goOp: AZLD1SH, + fixedBits: 0x84a00000, + args: XnSP__Zm_S__mod_c1___PgZ___Zt_S_, + }, + // ZLD1SH [.D{, #}], /Z, { .D } + { + goOp: AZLD1SH, + fixedBits: 0xc4a08000, + args: Zn_D__cimm___PgZ___Zt_D___2, + }, + // ZLD1SH [.S{, #}], /Z, { .S } + { + goOp: AZLD1SH, + fixedBits: 0x84a08000, + args: Zn_S__cimm___PgZ___Zt_S___2, + }, + // ZLD1SH [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLD1SH, + fixedBits: 0xa500a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLD1SH [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLD1SH, + fixedBits: 0xa520a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + }, + // ZLD1SW + { + // ZLD1SW [, , LSL #2], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xa4804000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_D_, + }, + // ZLD1SW [, .D, LSL #2], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xc5608000, + args: XnSP__Zm_D__LSL_c2___PgZ___Zt_D_, + }, + // ZLD1SW [, .D], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xc5408000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1SW [, .D, ], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xc5000000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1SW [, .D, #2], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xc5200000, + args: XnSP__Zm_D__mod_c2___PgZ___Zt_D_, + }, + // ZLD1SW [.D{, #}], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xc5208000, + args: Zn_D__cimm___PgZ___Zt_D___3, + }, + // ZLD1SW [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xa480a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + }, + // ZLD1W + { + // ZLD1W [, , LSL #2], /Z, { .D } + { + goOp: AZLD1W, + fixedBits: 0xa5604000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_D_, + }, + // ZLD1W [, , LSL #2], /Z, { .Q } + { + goOp: AZLD1W, + fixedBits: 0xa5008000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_Q_, + }, + // ZLD1W [, , LSL #2], /Z, { .S } + { + goOp: AZLD1W, + fixedBits: 0xa5404000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_S_, + }, + // ZLD1W [, .D, LSL #2], /Z, { .D } + { + goOp: AZLD1W, + fixedBits: 0xc560c000, + args: XnSP__Zm_D__LSL_c2___PgZ___Zt_D_, + }, + // ZLD1W [, .D], /Z, { .D } + { + goOp: AZLD1W, + fixedBits: 0xc540c000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1W [, .D, ], /Z, { .D } + { + goOp: AZLD1W, + fixedBits: 0xc5004000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1W [, .D, #2], /Z, { .D } + { + goOp: AZLD1W, + fixedBits: 0xc5204000, + args: XnSP__Zm_D__mod_c2___PgZ___Zt_D_, + }, + // ZLD1W [, .S, ], /Z, { .S } + { + goOp: AZLD1W, + fixedBits: 0x85004000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLD1W [, .S, #2], /Z, { .S } + { + goOp: AZLD1W, + fixedBits: 0x85204000, + args: XnSP__Zm_S__mod_c2___PgZ___Zt_S_, + }, + // ZLD1W [.D{, #}], /Z, { .D } + { + goOp: AZLD1W, + fixedBits: 0xc520c000, + args: Zn_D__cimm___PgZ___Zt_D___3, + }, + // ZLD1W [.S{, #}], /Z, { .S } + { + goOp: AZLD1W, + fixedBits: 0x8520c000, + args: Zn_S__cimm___PgZ___Zt_S___3, + }, + // ZLD1W [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLD1W, + fixedBits: 0xa560a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLD1W [{, #, MUL VL}], /Z, { .Q } + { + goOp: AZLD1W, + fixedBits: 0xa5102000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_Q_, + }, + // ZLD1W [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLD1W, + fixedBits: 0xa540a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + // ZLD1W [, , LSL #2], /Z, { .S-.S } + { + goOp: AZLD1W, + fixedBits: 0xa0004000, + args: XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt2_S_, + }, + // ZLD1W [, , LSL #2], /Z, { .S-.S } + { + goOp: AZLD1W, + fixedBits: 0xa000c000, + args: XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt4_S_, + }, + // ZLD1W [{, #, MUL VL}], /Z, { .S-.S } + { + goOp: AZLD1W, + fixedBits: 0xa0404000, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt2_S_, + }, + // ZLD1W [{, #, MUL VL}], /Z, { .S-.S } + { + goOp: AZLD1W, + fixedBits: 0xa040c000, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt4_S_, + }, + }, + // ZLD2B + { + // ZLD2B [, ], /Z, { .B, .B } + { + goOp: AZLD2B, + fixedBits: 0xa420c000, + args: XnSP__Xm___PgZ___Zt1_B__Zt2_B_, + }, + // ZLD2B [{, #, MUL VL}], /Z, { .B, .B } + { + goOp: AZLD2B, + fixedBits: 0xa420e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B_, + }, + }, + // ZLD2D + { + // ZLD2D [, , LSL #3], /Z, { .D, .D } + { + goOp: AZLD2D, + fixedBits: 0xa5a0c000, + args: XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D_, + }, + // ZLD2D [{, #, MUL VL}], /Z, { .D, .D } + { + goOp: AZLD2D, + fixedBits: 0xa5a0e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D_, + }, + }, + // ZLD2H + { + // ZLD2H [, , LSL #1], /Z, { .H, .H } + { + goOp: AZLD2H, + fixedBits: 0xa4a0c000, + args: XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H_, + }, + // ZLD2H [{, #, MUL VL}], /Z, { .H, .H } + { + goOp: AZLD2H, + fixedBits: 0xa4a0e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H_, + }, + }, + // ZLD2Q + { + // ZLD2Q [, , LSL #4], /Z, { .Q, .Q } + { + goOp: AZLD2Q, + fixedBits: 0xa4a08000, + args: XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q_, + }, + // ZLD2Q [{, #, MUL VL}], /Z, { .Q, .Q } + { + goOp: AZLD2Q, + fixedBits: 0xa490e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q_, + }, + }, + // ZLD2W + { + // ZLD2W [, , LSL #2], /Z, { .S, .S } + { + goOp: AZLD2W, + fixedBits: 0xa520c000, + args: XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S_, + }, + // ZLD2W [{, #, MUL VL}], /Z, { .S, .S } + { + goOp: AZLD2W, + fixedBits: 0xa520e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S_, + }, + }, + // ZLD3B + { + // ZLD3B [, ], /Z, { .B, .B, .B } + { + goOp: AZLD3B, + fixedBits: 0xa440c000, + args: XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B_, + }, + // ZLD3B [{, #, MUL VL}], /Z, { .B, .B, .B } + { + goOp: AZLD3B, + fixedBits: 0xa440e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B_, + }, + }, + // ZLD3D + { + // ZLD3D [, , LSL #3], /Z, { .D, .D, .D } + { + goOp: AZLD3D, + fixedBits: 0xa5c0c000, + args: XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D_, + }, + // ZLD3D [{, #, MUL VL}], /Z, { .D, .D, .D } + { + goOp: AZLD3D, + fixedBits: 0xa5c0e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D_, + }, + }, + // ZLD3H + { + // ZLD3H [, , LSL #1], /Z, { .H, .H, .H } + { + goOp: AZLD3H, + fixedBits: 0xa4c0c000, + args: XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H_, + }, + // ZLD3H [{, #, MUL VL}], /Z, { .H, .H, .H } + { + goOp: AZLD3H, + fixedBits: 0xa4c0e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H_, + }, + }, + // ZLD3Q + { + // ZLD3Q [, , LSL #4], /Z, { .Q, .Q, .Q } + { + goOp: AZLD3Q, + fixedBits: 0xa5208000, + args: XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_, + }, + // ZLD3Q [{, #, MUL VL}], /Z, { .Q, .Q, .Q } + { + goOp: AZLD3Q, + fixedBits: 0xa510e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_, + }, + }, + // ZLD3W + { + // ZLD3W [, , LSL #2], /Z, { .S, .S, .S } + { + goOp: AZLD3W, + fixedBits: 0xa540c000, + args: XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S_, + }, + // ZLD3W [{, #, MUL VL}], /Z, { .S, .S, .S } + { + goOp: AZLD3W, + fixedBits: 0xa540e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S_, + }, + }, + // ZLD4B + { + // ZLD4B [, ], /Z, { .B, .B, .B, .B } + { + goOp: AZLD4B, + fixedBits: 0xa460c000, + args: XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_, + }, + // ZLD4B [{, #, MUL VL}], /Z, { .B, .B, .B, .B } + { + goOp: AZLD4B, + fixedBits: 0xa460e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_, + }, + }, + // ZLD4D + { + // ZLD4D [, , LSL #3], /Z, { .D, .D, .D, .D } + { + goOp: AZLD4D, + fixedBits: 0xa5e0c000, + args: XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_, + }, + // ZLD4D [{, #, MUL VL}], /Z, { .D, .D, .D, .D } + { + goOp: AZLD4D, + fixedBits: 0xa5e0e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_, + }, + }, + // ZLD4H + { + // ZLD4H [, , LSL #1], /Z, { .H, .H, .H, .H } + { + goOp: AZLD4H, + fixedBits: 0xa4e0c000, + args: XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_, + }, + // ZLD4H [{, #, MUL VL}], /Z, { .H, .H, .H, .H } + { + goOp: AZLD4H, + fixedBits: 0xa4e0e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_, + }, + }, + // ZLD4Q + { + // ZLD4Q [, , LSL #4], /Z, { .Q, .Q, .Q, .Q } + { + goOp: AZLD4Q, + fixedBits: 0xa5a08000, + args: XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_, + }, + // ZLD4Q [{, #, MUL VL}], /Z, { .Q, .Q, .Q, .Q } + { + goOp: AZLD4Q, + fixedBits: 0xa590e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_, + }, + }, + // ZLD4W + { + // ZLD4W [, , LSL #2], /Z, { .S, .S, .S, .S } + { + goOp: AZLD4W, + fixedBits: 0xa560c000, + args: XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_, + }, + // ZLD4W [{, #, MUL VL}], /Z, { .S, .S, .S, .S } + { + goOp: AZLD4W, + fixedBits: 0xa560e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_, + }, + }, + // ZLDFF1B + { + // ZLDFF1B [{, }], /Z, { .B } + { + goOp: AZLDFF1B, + fixedBits: 0xa4006000, + args: XnSP__Xm___PgZ___Zt_B__V2, + }, + // ZLDFF1B [{, }], /Z, { .D } + { + goOp: AZLDFF1B, + fixedBits: 0xa4606000, + args: XnSP__Xm___PgZ___Zt_D__V2, + }, + // ZLDFF1B [{, }], /Z, { .H } + { + goOp: AZLDFF1B, + fixedBits: 0xa4206000, + args: XnSP__Xm___PgZ___Zt_H__V2, + }, + // ZLDFF1B [{, }], /Z, { .S } + { + goOp: AZLDFF1B, + fixedBits: 0xa4406000, + args: XnSP__Xm___PgZ___Zt_S__V2, + }, + // ZLDFF1B [, .D], /Z, { .D } + { + goOp: AZLDFF1B, + fixedBits: 0xc440e000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1B [, .D, ], /Z, { .D } + { + goOp: AZLDFF1B, + fixedBits: 0xc4006000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1B [, .S, ], /Z, { .S } + { + goOp: AZLDFF1B, + fixedBits: 0x84006000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLDFF1B [.D{, #}], /Z, { .D } + { + goOp: AZLDFF1B, + fixedBits: 0xc420e000, + args: Zn_D__cimm___PgZ___Zt_D___1, + }, + // ZLDFF1B [.S{, #}], /Z, { .S } + { + goOp: AZLDFF1B, + fixedBits: 0x8420e000, + args: Zn_S__cimm___PgZ___Zt_S___1, + }, + }, + // ZLDFF1D + { + // ZLDFF1D [{, , LSL #3}], /Z, { .D } + { + goOp: AZLDFF1D, + fixedBits: 0xa5e06000, + args: XnSP__Xm__LSL_c3___PgZ___Zt_D__V2, + }, + // ZLDFF1D [, .D, LSL #3], /Z, { .D } + { + goOp: AZLDFF1D, + fixedBits: 0xc5e0e000, + args: XnSP__Zm_D__LSL_c3___PgZ___Zt_D_, + }, + // ZLDFF1D [, .D], /Z, { .D } + { + goOp: AZLDFF1D, + fixedBits: 0xc5c0e000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1D [, .D, ], /Z, { .D } + { + goOp: AZLDFF1D, + fixedBits: 0xc5806000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1D [, .D, #3], /Z, { .D } + { + goOp: AZLDFF1D, + fixedBits: 0xc5a06000, + args: XnSP__Zm_D__mod_c3___PgZ___Zt_D_, + }, + // ZLDFF1D [.D{, #}], /Z, { .D } + { + goOp: AZLDFF1D, + fixedBits: 0xc5a0e000, + args: Zn_D__cimm___PgZ___Zt_D___4, + }, + }, + // ZLDFF1H + { + // ZLDFF1H [{, , LSL #1}], /Z, { .D } + { + goOp: AZLDFF1H, + fixedBits: 0xa4e06000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_D__V2, + }, + // ZLDFF1H [{, , LSL #1}], /Z, { .H } + { + goOp: AZLDFF1H, + fixedBits: 0xa4a06000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_H__V2, + }, + // ZLDFF1H [{, , LSL #1}], /Z, { .S } + { + goOp: AZLDFF1H, + fixedBits: 0xa4c06000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_S__V2, + }, + // ZLDFF1H [, .D, LSL #1], /Z, { .D } + { + goOp: AZLDFF1H, + fixedBits: 0xc4e0e000, + args: XnSP__Zm_D__LSL_c1___PgZ___Zt_D_, + }, + // ZLDFF1H [, .D], /Z, { .D } + { + goOp: AZLDFF1H, + fixedBits: 0xc4c0e000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1H [, .D, ], /Z, { .D } + { + goOp: AZLDFF1H, + fixedBits: 0xc4806000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1H [, .D, #1], /Z, { .D } + { + goOp: AZLDFF1H, + fixedBits: 0xc4a06000, + args: XnSP__Zm_D__mod_c1___PgZ___Zt_D_, + }, + // ZLDFF1H [, .S, ], /Z, { .S } + { + goOp: AZLDFF1H, + fixedBits: 0x84806000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLDFF1H [, .S, #1], /Z, { .S } + { + goOp: AZLDFF1H, + fixedBits: 0x84a06000, + args: XnSP__Zm_S__mod_c1___PgZ___Zt_S_, + }, + // ZLDFF1H [.D{, #}], /Z, { .D } + { + goOp: AZLDFF1H, + fixedBits: 0xc4a0e000, + args: Zn_D__cimm___PgZ___Zt_D___2, + }, + // ZLDFF1H [.S{, #}], /Z, { .S } + { + goOp: AZLDFF1H, + fixedBits: 0x84a0e000, + args: Zn_S__cimm___PgZ___Zt_S___2, + }, + }, + // ZLDFF1SB + { + // ZLDFF1SB [{, }], /Z, { .D } + { + goOp: AZLDFF1SB, + fixedBits: 0xa5806000, + args: XnSP__Xm___PgZ___Zt_D__V2, + }, + // ZLDFF1SB [{, }], /Z, { .H } + { + goOp: AZLDFF1SB, + fixedBits: 0xa5c06000, + args: XnSP__Xm___PgZ___Zt_H__V2, + }, + // ZLDFF1SB [{, }], /Z, { .S } + { + goOp: AZLDFF1SB, + fixedBits: 0xa5a06000, + args: XnSP__Xm___PgZ___Zt_S__V2, + }, + // ZLDFF1SB [, .D], /Z, { .D } + { + goOp: AZLDFF1SB, + fixedBits: 0xc440a000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1SB [, .D, ], /Z, { .D } + { + goOp: AZLDFF1SB, + fixedBits: 0xc4002000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1SB [, .S, ], /Z, { .S } + { + goOp: AZLDFF1SB, + fixedBits: 0x84002000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLDFF1SB [.D{, #}], /Z, { .D } + { + goOp: AZLDFF1SB, + fixedBits: 0xc420a000, + args: Zn_D__cimm___PgZ___Zt_D___1, + }, + // ZLDFF1SB [.S{, #}], /Z, { .S } + { + goOp: AZLDFF1SB, + fixedBits: 0x8420a000, + args: Zn_S__cimm___PgZ___Zt_S___1, + }, + }, + // ZLDFF1SH + { + // ZLDFF1SH [{, , LSL #1}], /Z, { .D } + { + goOp: AZLDFF1SH, + fixedBits: 0xa5006000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_D__V2, + }, + // ZLDFF1SH [{, , LSL #1}], /Z, { .S } + { + goOp: AZLDFF1SH, + fixedBits: 0xa5206000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_S__V2, + }, + // ZLDFF1SH [, .D, LSL #1], /Z, { .D } + { + goOp: AZLDFF1SH, + fixedBits: 0xc4e0a000, + args: XnSP__Zm_D__LSL_c1___PgZ___Zt_D_, + }, + // ZLDFF1SH [, .D], /Z, { .D } + { + goOp: AZLDFF1SH, + fixedBits: 0xc4c0a000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1SH [, .D, ], /Z, { .D } + { + goOp: AZLDFF1SH, + fixedBits: 0xc4802000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1SH [, .D, #1], /Z, { .D } + { + goOp: AZLDFF1SH, + fixedBits: 0xc4a02000, + args: XnSP__Zm_D__mod_c1___PgZ___Zt_D_, + }, + // ZLDFF1SH [, .S, ], /Z, { .S } + { + goOp: AZLDFF1SH, + fixedBits: 0x84802000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLDFF1SH [, .S, #1], /Z, { .S } + { + goOp: AZLDFF1SH, + fixedBits: 0x84a02000, + args: XnSP__Zm_S__mod_c1___PgZ___Zt_S_, + }, + // ZLDFF1SH [.D{, #}], /Z, { .D } + { + goOp: AZLDFF1SH, + fixedBits: 0xc4a0a000, + args: Zn_D__cimm___PgZ___Zt_D___2, + }, + // ZLDFF1SH [.S{, #}], /Z, { .S } + { + goOp: AZLDFF1SH, + fixedBits: 0x84a0a000, + args: Zn_S__cimm___PgZ___Zt_S___2, + }, + }, + // ZLDFF1SW + { + // ZLDFF1SW [{, , LSL #2}], /Z, { .D } + { + goOp: AZLDFF1SW, + fixedBits: 0xa4806000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_D__V2, + }, + // ZLDFF1SW [, .D, LSL #2], /Z, { .D } + { + goOp: AZLDFF1SW, + fixedBits: 0xc560a000, + args: XnSP__Zm_D__LSL_c2___PgZ___Zt_D_, + }, + // ZLDFF1SW [, .D], /Z, { .D } + { + goOp: AZLDFF1SW, + fixedBits: 0xc540a000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1SW [, .D, ], /Z, { .D } + { + goOp: AZLDFF1SW, + fixedBits: 0xc5002000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1SW [, .D, #2], /Z, { .D } + { + goOp: AZLDFF1SW, + fixedBits: 0xc5202000, + args: XnSP__Zm_D__mod_c2___PgZ___Zt_D_, + }, + // ZLDFF1SW [.D{, #}], /Z, { .D } + { + goOp: AZLDFF1SW, + fixedBits: 0xc520a000, + args: Zn_D__cimm___PgZ___Zt_D___3, + }, + }, + // ZLDFF1W + { + // ZLDFF1W [{, , LSL #2}], /Z, { .D } + { + goOp: AZLDFF1W, + fixedBits: 0xa5606000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_D__V2, + }, + // ZLDFF1W [{, , LSL #2}], /Z, { .S } + { + goOp: AZLDFF1W, + fixedBits: 0xa5406000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_S__V2, + }, + // ZLDFF1W [, .D, LSL #2], /Z, { .D } + { + goOp: AZLDFF1W, + fixedBits: 0xc560e000, + args: XnSP__Zm_D__LSL_c2___PgZ___Zt_D_, + }, + // ZLDFF1W [, .D], /Z, { .D } + { + goOp: AZLDFF1W, + fixedBits: 0xc540e000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1W [, .D, ], /Z, { .D } + { + goOp: AZLDFF1W, + fixedBits: 0xc5006000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1W [, .D, #2], /Z, { .D } + { + goOp: AZLDFF1W, + fixedBits: 0xc5206000, + args: XnSP__Zm_D__mod_c2___PgZ___Zt_D_, + }, + // ZLDFF1W [, .S, ], /Z, { .S } + { + goOp: AZLDFF1W, + fixedBits: 0x85006000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLDFF1W [, .S, #2], /Z, { .S } + { + goOp: AZLDFF1W, + fixedBits: 0x85206000, + args: XnSP__Zm_S__mod_c2___PgZ___Zt_S_, + }, + // ZLDFF1W [.D{, #}], /Z, { .D } + { + goOp: AZLDFF1W, + fixedBits: 0xc520e000, + args: Zn_D__cimm___PgZ___Zt_D___3, + }, + // ZLDFF1W [.S{, #}], /Z, { .S } + { + goOp: AZLDFF1W, + fixedBits: 0x8520e000, + args: Zn_S__cimm___PgZ___Zt_S___3, + }, + }, + // ZLDNF1B + { + // ZLDNF1B [{, #, MUL VL}], /Z, { .B } + { + goOp: AZLDNF1B, + fixedBits: 0xa410a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_B_, + }, + // ZLDNF1B [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLDNF1B, + fixedBits: 0xa470a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLDNF1B [{, #, MUL VL}], /Z, { .H } + { + goOp: AZLDNF1B, + fixedBits: 0xa430a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_H_, + }, + // ZLDNF1B [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLDNF1B, + fixedBits: 0xa450a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + }, + // ZLDNF1D + { + // ZLDNF1D [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLDNF1D, + fixedBits: 0xa5f0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + }, + // ZLDNF1H + { + // ZLDNF1H [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLDNF1H, + fixedBits: 0xa4f0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLDNF1H [{, #, MUL VL}], /Z, { .H } + { + goOp: AZLDNF1H, + fixedBits: 0xa4b0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_H_, + }, + // ZLDNF1H [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLDNF1H, + fixedBits: 0xa4d0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + }, + // ZLDNF1SB + { + // ZLDNF1SB [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLDNF1SB, + fixedBits: 0xa590a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLDNF1SB [{, #, MUL VL}], /Z, { .H } + { + goOp: AZLDNF1SB, + fixedBits: 0xa5d0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_H_, + }, + // ZLDNF1SB [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLDNF1SB, + fixedBits: 0xa5b0a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + }, + // ZLDNF1SH + { + // ZLDNF1SH [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLDNF1SH, + fixedBits: 0xa510a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLDNF1SH [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLDNF1SH, + fixedBits: 0xa530a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + }, + // ZLDNF1SW + { + // ZLDNF1SW [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLDNF1SW, + fixedBits: 0xa490a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + }, + // ZLDNF1W + { + // ZLDNF1W [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLDNF1W, + fixedBits: 0xa570a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLDNF1W [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLDNF1W, + fixedBits: 0xa550a000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + }, + // ZLDNT1B + { + // ZLDNT1B [, ], /Z, { .B } + { + goOp: AZLDNT1B, + fixedBits: 0xa400c000, + args: XnSP__Xm___PgZ___Zt_B_, + }, + // ZLDNT1B [.D{, }], /Z, { .D } + { + goOp: AZLDNT1B, + fixedBits: 0xc400c000, + args: Zn_D__Xm___PgZ___Zt_D_, + }, + // ZLDNT1B [.S{, }], /Z, { .S } + { + goOp: AZLDNT1B, + fixedBits: 0x8400a000, + args: Zn_S__Xm___PgZ___Zt_S_, + }, + // ZLDNT1B [{, #, MUL VL}], /Z, { .B } + { + goOp: AZLDNT1B, + fixedBits: 0xa400e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_B_, + }, + // ZLDNT1B [, ], /Z, { .B-.B } + { + goOp: AZLDNT1B, + fixedBits: 0xa0000001, + args: XnSP__Xm___PNgZ___Zt1_B_Zt2_B_, + }, + // ZLDNT1B [, ], /Z, { .B-.B } + { + goOp: AZLDNT1B, + fixedBits: 0xa0008001, + args: XnSP__Xm___PNgZ___Zt1_B_Zt4_B_, + }, + // ZLDNT1B [{, #, MUL VL}], /Z, { .B-.B } + { + goOp: AZLDNT1B, + fixedBits: 0xa0400001, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt2_B_, + }, + // ZLDNT1B [{, #, MUL VL}], /Z, { .B-.B } + { + goOp: AZLDNT1B, + fixedBits: 0xa0408001, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt4_B_, + }, + }, + // ZLDNT1D + { + // ZLDNT1D [, , LSL #3], /Z, { .D } + { + goOp: AZLDNT1D, + fixedBits: 0xa580c000, + args: XnSP__Xm__LSL_c3___PgZ___Zt_D_, + }, + // ZLDNT1D [.D{, }], /Z, { .D } + { + goOp: AZLDNT1D, + fixedBits: 0xc580c000, + args: Zn_D__Xm___PgZ___Zt_D_, + }, + // ZLDNT1D [{, #, MUL VL}], /Z, { .D } + { + goOp: AZLDNT1D, + fixedBits: 0xa580e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_D_, + }, + // ZLDNT1D [, , LSL #3], /Z, { .D-.D } + { + goOp: AZLDNT1D, + fixedBits: 0xa0006001, + args: XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt2_D_, + }, + // ZLDNT1D [, , LSL #3], /Z, { .D-.D } + { + goOp: AZLDNT1D, + fixedBits: 0xa000e001, + args: XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt4_D_, + }, + // ZLDNT1D [{, #, MUL VL}], /Z, { .D-.D } + { + goOp: AZLDNT1D, + fixedBits: 0xa0406001, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt2_D_, + }, + // ZLDNT1D [{, #, MUL VL}], /Z, { .D-.D } + { + goOp: AZLDNT1D, + fixedBits: 0xa040e001, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt4_D_, + }, + }, + // ZLDNT1H + { + // ZLDNT1H [, , LSL #1], /Z, { .H } + { + goOp: AZLDNT1H, + fixedBits: 0xa480c000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_H_, + }, + // ZLDNT1H [.D{, }], /Z, { .D } + { + goOp: AZLDNT1H, + fixedBits: 0xc480c000, + args: Zn_D__Xm___PgZ___Zt_D_, + }, + // ZLDNT1H [.S{, }], /Z, { .S } + { + goOp: AZLDNT1H, + fixedBits: 0x8480a000, + args: Zn_S__Xm___PgZ___Zt_S_, + }, + // ZLDNT1H [{, #, MUL VL}], /Z, { .H } + { + goOp: AZLDNT1H, + fixedBits: 0xa480e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_H_, + }, + // ZLDNT1H [, , LSL #1], /Z, { .H-.H } + { + goOp: AZLDNT1H, + fixedBits: 0xa0002001, + args: XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt2_H_, + }, + // ZLDNT1H [, , LSL #1], /Z, { .H-.H } + { + goOp: AZLDNT1H, + fixedBits: 0xa000a001, + args: XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt4_H_, + }, + // ZLDNT1H [{, #, MUL VL}], /Z, { .H-.H } + { + goOp: AZLDNT1H, + fixedBits: 0xa0402001, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt2_H_, + }, + // ZLDNT1H [{, #, MUL VL}], /Z, { .H-.H } + { + goOp: AZLDNT1H, + fixedBits: 0xa040a001, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt4_H_, + }, + }, + // ZLDNT1SB + { + // ZLDNT1SB [.D{, }], /Z, { .D } + { + goOp: AZLDNT1SB, + fixedBits: 0xc4008000, + args: Zn_D__Xm___PgZ___Zt_D_, + }, + // ZLDNT1SB [.S{, }], /Z, { .S } + { + goOp: AZLDNT1SB, + fixedBits: 0x84008000, + args: Zn_S__Xm___PgZ___Zt_S_, + }, + }, + // ZLDNT1SH + { + // ZLDNT1SH [.D{, }], /Z, { .D } + { + goOp: AZLDNT1SH, + fixedBits: 0xc4808000, + args: Zn_D__Xm___PgZ___Zt_D_, + }, + // ZLDNT1SH [.S{, }], /Z, { .S } + { + goOp: AZLDNT1SH, + fixedBits: 0x84808000, + args: Zn_S__Xm___PgZ___Zt_S_, + }, + }, + // ZLDNT1SW + { + // ZLDNT1SW [.D{, }], /Z, { .D } + { + goOp: AZLDNT1SW, + fixedBits: 0xc5008000, + args: Zn_D__Xm___PgZ___Zt_D_, + }, + }, + // ZLDNT1W + { + // ZLDNT1W [, , LSL #2], /Z, { .S } + { + goOp: AZLDNT1W, + fixedBits: 0xa500c000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_S_, + }, + // ZLDNT1W [.D{, }], /Z, { .D } + { + goOp: AZLDNT1W, + fixedBits: 0xc500c000, + args: Zn_D__Xm___PgZ___Zt_D_, + }, + // ZLDNT1W [.S{, }], /Z, { .S } + { + goOp: AZLDNT1W, + fixedBits: 0x8500a000, + args: Zn_S__Xm___PgZ___Zt_S_, + }, + // ZLDNT1W [{, #, MUL VL}], /Z, { .S } + { + goOp: AZLDNT1W, + fixedBits: 0xa500e000, + args: XnSP__cimm__MUL_VL___PgZ___Zt_S_, + }, + // ZLDNT1W [, , LSL #2], /Z, { .S-.S } + { + goOp: AZLDNT1W, + fixedBits: 0xa0004001, + args: XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt2_S_, + }, + // ZLDNT1W [, , LSL #2], /Z, { .S-.S } + { + goOp: AZLDNT1W, + fixedBits: 0xa000c001, + args: XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt4_S_, + }, + // ZLDNT1W [{, #, MUL VL}], /Z, { .S-.S } + { + goOp: AZLDNT1W, + fixedBits: 0xa0404001, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt2_S_, + }, + // ZLDNT1W [{, #, MUL VL}], /Z, { .S-.S } + { + goOp: AZLDNT1W, + fixedBits: 0xa040c001, + args: XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt4_S_, + }, + }, + // ZLDR + { + // ZLDR [{, #, MUL VL}], + { + goOp: AZLDR, + fixedBits: 0x85804000, + args: XnSP__cimm__MUL_VL___Zt, + }, + }, + // ZLSL + { + // ZLSL .D, ., /M, . + { + goOp: AZLSL, + fixedBits: 0x41b8000, + args: Zm_D__Zdn_T__PgM__Zdn_T, + }, + // ZLSL .D, ., . + { + goOp: AZLSL, + fixedBits: 0x4208c00, + args: Zm_D__Zn_T__Zd_T, + }, + // ZLSL ., ., /M, . + { + goOp: AZLSL, + fixedBits: 0x4138000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZLSL #, ., /M, . + { + goOp: AZLSL, + fixedBits: 0x4038000, + args: cconst__Zdn_T__PgM__Zdn_T__2, + }, + // ZLSL #, ., . + { + goOp: AZLSL, + fixedBits: 0x4209c00, + args: cconst__Zn_T__Zd_T__2, + }, + }, + // ZLSLR + { + // ZLSLR ., ., /M, . + { + goOp: AZLSLR, + fixedBits: 0x4178000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZLSR + { + // ZLSR .D, ., /M, . + { + goOp: AZLSR, + fixedBits: 0x4198000, + args: Zm_D__Zdn_T__PgM__Zdn_T, + }, + // ZLSR .D, ., . + { + goOp: AZLSR, + fixedBits: 0x4208400, + args: Zm_D__Zn_T__Zd_T, + }, + // ZLSR ., ., /M, . + { + goOp: AZLSR, + fixedBits: 0x4118000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZLSR #, ., /M, . + { + goOp: AZLSR, + fixedBits: 0x4018000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, + // ZLSR #, ., . + { + goOp: AZLSR, + fixedBits: 0x4209400, + args: cconst__Zn_T__Zd_T__1, + }, + }, + // ZLSRR + { + // ZLSRR ., ., /M, . + { + goOp: AZLSRR, + fixedBits: 0x4158000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZLUTI2 + { + // ZLUTI2 [], { .B }, .B + { + goOp: AZLUTI2, + fixedBits: 0x4520b000, + args: Zm_index____Zn_B___Zd_B__1, + }, + // ZLUTI2 [], { .H }, .H + { + goOp: AZLUTI2, + fixedBits: 0x4520a800, + args: Zm_index____Zn_H___Zd_H__1, + }, + }, + // ZLUTI4 + { + // ZLUTI4 [], { .H, .H }, .H + { + goOp: AZLUTI4, + fixedBits: 0x4520b400, + args: Zm_index____Zn1_H__Zn2_H___Zd_H__1, + }, + // ZLUTI4 [], { .B }, .B + { + goOp: AZLUTI4, + fixedBits: 0x4560a400, + args: Zm_index____Zn_B___Zd_B__2, + }, + // ZLUTI4 [], { .H }, .H + { + goOp: AZLUTI4, + fixedBits: 0x4520bc00, + args: Zm_index____Zn_H___Zd_H__2, + }, + }, + // ZLUTI6 + { + // ZLUTI6 , { .B, .B }, .B + { + goOp: AZLUTI6, + fixedBits: 0x4520ac00, + args: Zm___Zn1_B__Zn2_B___Zd_B, + }, + // ZLUTI6 [], { .H, .H }, .H + { + goOp: AZLUTI6, + fixedBits: 0x4560ac00, + args: Zm_index____Zn1_H__Zn2_H___Zd_H__2, + }, + }, + // ZMAD + { + // ZMAD ., ., /M, . + { + goOp: AZMAD, + fixedBits: 0x400c000, + args: Za_T__Zm_T__PgM__Zdn_T__2, + }, + }, + // ZMADPT + { + // ZMADPT .D, .D, .D + { + goOp: AZMADPT, + fixedBits: 0x44c0d800, + args: Za_D__Zm_D__Zdn_D, + }, + }, + // ZMATCH + { + // ZMATCH ., ., /Z, . + { + goOp: AZMATCH, + fixedBits: 0x45208000, + args: Zm_T__Zn_T__PgZ__Pd_T__3, + }, + }, + // ZMLA + { + // ZMLA ., ., /M, . + { + goOp: AZMLA, + fixedBits: 0x4004000, + args: Zm_T__Zn_T__PgM__Zda_T__2, + }, + // ZMLA .D[], .D, .D + { + goOp: AZMLA, + fixedBits: 0x44e00800, + args: Zm_D_imm___Zn_D__Zda_D__1, + }, + // ZMLA .H[], .H, .H + { + goOp: AZMLA, + fixedBits: 0x44200800, + args: Zm_H_imm___Zn_H__Zda_H__1, + }, + // ZMLA .S[], .S, .S + { + goOp: AZMLA, + fixedBits: 0x44a00800, + args: Zm_S_imm___Zn_S__Zda_S__1, + }, + }, + // ZMLAPT + { + // ZMLAPT .D, .D, .D + { + goOp: AZMLAPT, + fixedBits: 0x44c0d000, + args: Zm_D__Zn_D__Zda_D, + }, + }, + // ZMLS + { + // ZMLS ., ., /M, . + { + goOp: AZMLS, + fixedBits: 0x4006000, + args: Zm_T__Zn_T__PgM__Zda_T__2, + }, + // ZMLS .D[], .D, .D + { + goOp: AZMLS, + fixedBits: 0x44e00c00, + args: Zm_D_imm___Zn_D__Zda_D__1, + }, + // ZMLS .H[], .H, .H + { + goOp: AZMLS, + fixedBits: 0x44200c00, + args: Zm_H_imm___Zn_H__Zda_H__1, + }, + // ZMLS .S[], .S, .S + { + goOp: AZMLS, + fixedBits: 0x44a00c00, + args: Zm_S_imm___Zn_S__Zda_S__1, + }, + }, + // ZMOVPRFX + { + // ZMOVPRFX ., /, . + { + goOp: AZMOVPRFX, + fixedBits: 0x4102000, + args: Zn_T__PgZM__Zd_T, + }, + // ZMOVPRFX , + { + goOp: AZMOVPRFX, + fixedBits: 0x420bc00, + args: Zn__Zd, + }, + }, + // ZMSB + { + // ZMSB ., ., /M, . + { + goOp: AZMSB, + fixedBits: 0x400e000, + args: Za_T__Zm_T__PgM__Zdn_T__2, + }, + }, + // ZMUL + { + // ZMUL ., ., /M, . + { + goOp: AZMUL, + fixedBits: 0x4100000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZMUL ., ., . + { + goOp: AZMUL, + fixedBits: 0x4206000, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZMUL .D[], .D, .D + { + goOp: AZMUL, + fixedBits: 0x44e0f800, + args: Zm_D_imm___Zn_D__Zd_D__1, + }, + // ZMUL .H[], .H, .H + { + goOp: AZMUL, + fixedBits: 0x4420f800, + args: Zm_H_imm___Zn_H__Zd_H__1, + }, + // ZMUL .S[], .S, .S + { + goOp: AZMUL, + fixedBits: 0x44a0f800, + args: Zm_S_imm___Zn_S__Zd_S__1, + }, + // ZMUL #, ., . + { + goOp: AZMUL, + fixedBits: 0x2530c000, + args: cimm__Zdn_T__Zdn_T__1, + }, + }, + // ZNBSL + { + // ZNBSL .D, .D, .D, .D + { + goOp: AZNBSL, + fixedBits: 0x4e03c00, + args: Zk_D__Zm_D__Zdn_D__Zdn_D, + }, + }, + // ZNEG + { + // ZNEG ., /M, . + { + goOp: AZNEG, + fixedBits: 0x417a000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZNEG ., /Z, . + { + goOp: AZNEG, + fixedBits: 0x407a000, + args: Zn_T__PgZ__Zd_T__2, + }, + }, + // ZNMATCH + { + // ZNMATCH ., ., /Z, . + { + goOp: AZNMATCH, + fixedBits: 0x45208010, + args: Zm_T__Zn_T__PgZ__Pd_T__3, + }, + }, + // ZNOT + { + // ZNOT ., /M, . + { + goOp: AZNOT, + fixedBits: 0x41ea000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZNOT ., /Z, . + { + goOp: AZNOT, + fixedBits: 0x40ea000, + args: Zn_T__PgZ__Zd_T__2, + }, + }, + // ZORQV + { + // ZORQV ., , . + { + goOp: AZORQV, + fixedBits: 0x41c2000, + args: Zn_Tb__Pg__Vd_T__1, + }, + }, + // ZORR + { + // ZORR .D, .D, .D + { + goOp: AZORR, + fixedBits: 0x4603000, + args: Zm_D__Zn_D__Zd_D, + }, + // ZORR ., ., /M, . + { + goOp: AZORR, + fixedBits: 0x4180000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZORR #, ., . + { + goOp: AZORR, + fixedBits: 0x5000000, + args: cconst__Zdn_T__Zdn_T, + }, + }, + // ZORVB + { + // ZORVB ., , + { + goOp: AZORVB, + fixedBits: 0x4182000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZORVD + { + // ZORVD ., , + { + goOp: AZORVD, + fixedBits: 0x4d82000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZORVH + { + // ZORVH ., , + { + goOp: AZORVH, + fixedBits: 0x4582000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZORVS + { + // ZORVS ., , + { + goOp: AZORVS, + fixedBits: 0x4982000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZPMLAL + { + // ZPMLAL .D, .D, { .Q-.Q } + { + goOp: AZPMLAL, + fixedBits: 0x4520fc00, + args: Zm_D__Zn_D___Zda1_Q_Zda2_Q_, + }, + }, + // ZPMOV + { + // ZPMOV .B, + { + goOp: AZPMOV, + fixedBits: 0x52b3800, + args: Pn_B__Zd, + }, + // ZPMOV , .B + { + goOp: AZPMOV, + fixedBits: 0x52a3800, + args: Zn__Pd_B, + }, + // ZPMOV .D, {[]} + { + goOp: AZPMOV, + fixedBits: 0x5a93800, + args: Pn_D__Zd_imm_, + }, + // ZPMOV .H, {[]} + { + goOp: AZPMOV, + fixedBits: 0x52d3800, + args: Pn_H__Zd_imm_, + }, + // ZPMOV .S, {[]} + { + goOp: AZPMOV, + fixedBits: 0x5693800, + args: Pn_S__Zd_imm_, + }, + // ZPMOV {[]}, .D + { + goOp: AZPMOV, + fixedBits: 0x5a83800, + args: Zn_imm___Pd_D, + }, + // ZPMOV {[]}, .H + { + goOp: AZPMOV, + fixedBits: 0x52c3800, + args: Zn_imm___Pd_H, + }, + // ZPMOV {[]}, .S + { + goOp: AZPMOV, + fixedBits: 0x5683800, + args: Zn_imm___Pd_S, + }, + }, + // ZPMUL + { + // ZPMUL .B, .B, .B + { + goOp: AZPMUL, + fixedBits: 0x4206400, + args: Zm_B__Zn_B__Zd_B, + }, + }, + // ZPMULL + { + // ZPMULL .D, .D, { .Q-.Q } + { + goOp: AZPMULL, + fixedBits: 0x4520f800, + args: Zm_D__Zn_D___Zd1_Q_Zd2_Q_, + }, + }, + // ZPMULLB + { + // ZPMULLB .D, .D, .Q + { + goOp: AZPMULLB, + fixedBits: 0x45006800, + args: Zm_D__Zn_D__Zd_Q, + }, + // ZPMULLB ., ., . + { + goOp: AZPMULLB, + fixedBits: 0x45006800, + args: Zm_Tb__Zn_Tb__Zd_T__3, + }, + }, + // ZPMULLT + { + // ZPMULLT .D, .D, .Q + { + goOp: AZPMULLT, + fixedBits: 0x45006c00, + args: Zm_D__Zn_D__Zd_Q, + }, + // ZPMULLT ., ., . + { + goOp: AZPMULLT, + fixedBits: 0x45006c00, + args: Zm_Tb__Zn_Tb__Zd_T__3, + }, + }, + // ZPRFB + { + // ZPRFB [, .D], , + { + goOp: AZPRFB, + fixedBits: 0xc4608000, + args: XnSP__Zm_D___Pg__prfop, + }, + // ZPRFB [, .D, ], , + { + goOp: AZPRFB, + fixedBits: 0xc4200000, + args: XnSP__Zm_D__mod___Pg__prfop, + }, + // ZPRFB [, .S, ], , + { + goOp: AZPRFB, + fixedBits: 0x84200000, + args: XnSP__Zm_S__mod___Pg__prfop, + }, + // ZPRFB [.D{, #}], , + { + goOp: AZPRFB, + fixedBits: 0xc400e000, + args: Zn_D__cimm___Pg__prfop__1, + }, + // ZPRFB [.S{, #}], , + { + goOp: AZPRFB, + fixedBits: 0x8400e000, + args: Zn_S__cimm___Pg__prfop__1, + }, + }, + // ZPRFD + { + // ZPRFD [, .D, LSL #3], , + { + goOp: AZPRFD, + fixedBits: 0xc460e000, + args: XnSP__Zm_D__LSL_c3___Pg__prfop, + }, + // ZPRFD [, .D, #3], , + { + goOp: AZPRFD, + fixedBits: 0xc4206000, + args: XnSP__Zm_D__mod_c3___Pg__prfop, + }, + // ZPRFD [, .S, #3], , + { + goOp: AZPRFD, + fixedBits: 0x84206000, + args: XnSP__Zm_S__mod_c3___Pg__prfop, + }, + // ZPRFD [.D{, #}], , + { + goOp: AZPRFD, + fixedBits: 0xc580e000, + args: Zn_D__cimm___Pg__prfop__2, + }, + // ZPRFD [.S{, #}], , + { + goOp: AZPRFD, + fixedBits: 0x8580e000, + args: Zn_S__cimm___Pg__prfop__2, + }, + }, + // ZPRFH + { + // ZPRFH [, .D, LSL #1], , + { + goOp: AZPRFH, + fixedBits: 0xc460a000, + args: XnSP__Zm_D__LSL_c1___Pg__prfop, + }, + // ZPRFH [, .D, #1], , + { + goOp: AZPRFH, + fixedBits: 0xc4202000, + args: XnSP__Zm_D__mod_c1___Pg__prfop, + }, + // ZPRFH [, .S, #1], , + { + goOp: AZPRFH, + fixedBits: 0x84202000, + args: XnSP__Zm_S__mod_c1___Pg__prfop, + }, + // ZPRFH [.D{, #}], , + { + goOp: AZPRFH, + fixedBits: 0xc480e000, + args: Zn_D__cimm___Pg__prfop__3, + }, + // ZPRFH [.S{, #}], , + { + goOp: AZPRFH, + fixedBits: 0x8480e000, + args: Zn_S__cimm___Pg__prfop__3, + }, + }, + // ZPRFW + { + // ZPRFW [, .D, LSL #2], , + { + goOp: AZPRFW, + fixedBits: 0xc460c000, + args: XnSP__Zm_D__LSL_c2___Pg__prfop, + }, + // ZPRFW [, .D, #2], , + { + goOp: AZPRFW, + fixedBits: 0xc4204000, + args: XnSP__Zm_D__mod_c2___Pg__prfop, + }, + // ZPRFW [, .S, #2], , + { + goOp: AZPRFW, + fixedBits: 0x84204000, + args: XnSP__Zm_S__mod_c2___Pg__prfop, + }, + // ZPRFW [.D{, #}], , + { + goOp: AZPRFW, + fixedBits: 0xc500e000, + args: Zn_D__cimm___Pg__prfop__4, + }, + // ZPRFW [.S{, #}], , + { + goOp: AZPRFW, + fixedBits: 0x8500e000, + args: Zn_S__cimm___Pg__prfop__4, + }, + }, + // ZRADDHNB + { + // ZRADDHNB ., ., . + { + goOp: AZRADDHNB, + fixedBits: 0x45206800, + args: Zm_Tb__Zn_Tb__Zd_T__2, + }, + }, + // ZRADDHNT + { + // ZRADDHNT ., ., . + { + goOp: AZRADDHNT, + fixedBits: 0x45206c00, + args: Zm_Tb__Zn_Tb__Zd_T__2, + }, + }, + // ZRAX1 + { + // ZRAX1 .D, .D, .D + { + goOp: AZRAX1, + fixedBits: 0x4520f400, + args: Zm_D__Zn_D__Zd_D, + }, + }, + // ZRBIT + { + // ZRBIT ., /M, . + { + goOp: AZRBIT, + fixedBits: 0x5278000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZRBIT ., /Z, . + { + goOp: AZRBIT, + fixedBits: 0x527a000, + args: Zn_T__PgZ__Zd_T__2, + }, + }, + // ZREV + { + // ZREV ., . + { + goOp: AZREV, + fixedBits: 0x5383800, + args: Zn_T__Zd_T__2, + }, + }, + // ZREVB + { + // ZREVB ., /M, . + { + goOp: AZREVB, + fixedBits: 0x5248000, + args: Zn_T__PgM__Zd_T__4, + }, + // ZREVB ., /Z, . + { + goOp: AZREVB, + fixedBits: 0x524a000, + args: Zn_T__PgZ__Zd_T__4, + }, + }, + // ZREVD + { + // ZREVD .Q, /M, .Q + { + goOp: AZREVD, + fixedBits: 0x52e8000, + args: Zn_Q__PgM__Zd_Q, + }, + // ZREVD .Q, /Z, .Q + { + goOp: AZREVD, + fixedBits: 0x52ea000, + args: Zn_Q__PgZ__Zd_Q, + }, + }, + // ZREVH + { + // ZREVH ., /M, . + { + goOp: AZREVH, + fixedBits: 0x5a58000, + args: Zn_T__PgM__Zd_T__5, + }, + // ZREVH ., /Z, . + { + goOp: AZREVH, + fixedBits: 0x5a5a000, + args: Zn_T__PgZ__Zd_T__5, + }, + }, + // ZREVW + { + // ZREVW .D, /M, .D + { + goOp: AZREVW, + fixedBits: 0x5e68000, + args: Zn_D__PgM__Zd_D, + }, + // ZREVW .D, /Z, .D + { + goOp: AZREVW, + fixedBits: 0x5e6a000, + args: Zn_D__PgZ__Zd_D, + }, + }, + // ZRSHRNB + { + // ZRSHRNB #, ., . + { + goOp: AZRSHRNB, + fixedBits: 0x45201800, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZRSHRNT + { + // ZRSHRNT #, ., . + { + goOp: AZRSHRNT, + fixedBits: 0x45201c00, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZRSUBHNB + { + // ZRSUBHNB ., ., . + { + goOp: AZRSUBHNB, + fixedBits: 0x45207800, + args: Zm_Tb__Zn_Tb__Zd_T__2, + }, + }, + // ZRSUBHNT + { + // ZRSUBHNT ., ., . + { + goOp: AZRSUBHNT, + fixedBits: 0x45207c00, + args: Zm_Tb__Zn_Tb__Zd_T__2, + }, + }, + // ZSABA + { + // ZSABA ., ., . + { + goOp: AZSABA, + fixedBits: 0x4500f800, + args: Zm_T__Zn_T__Zda_T__2, + }, + }, + // ZSABAL + { + // ZSABAL ., ., . + { + goOp: AZSABAL, + fixedBits: 0x4400d400, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + }, + // ZSABALB + { + // ZSABALB ., ., . + { + goOp: AZSABALB, + fixedBits: 0x4500c000, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + }, + // ZSABALT + { + // ZSABALT ., ., . + { + goOp: AZSABALT, + fixedBits: 0x4500c400, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + }, + // ZSABD + { + // ZSABD ., ., /M, . + { + goOp: AZSABD, + fixedBits: 0x40c0000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSABDLB + { + // ZSABDLB ., ., . + { + goOp: AZSABDLB, + fixedBits: 0x45003000, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZSABDLT + { + // ZSABDLT ., ., . + { + goOp: AZSABDLT, + fixedBits: 0x45003400, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZSADALP + { + // ZSADALP ., /M, . + { + goOp: AZSADALP, + fixedBits: 0x4404a000, + args: Zn_Tb__PgM__Zda_T, + }, + }, + // ZSADDLB + { + // ZSADDLB ., ., . + { + goOp: AZSADDLB, + fixedBits: 0x45000000, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZSADDLBT + { + // ZSADDLBT ., ., . + { + goOp: AZSADDLBT, + fixedBits: 0x45008000, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZSADDLT + { + // ZSADDLT ., ., . + { + goOp: AZSADDLT, + fixedBits: 0x45000400, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZSADDVD + { + // ZSADDVD ., ,
    + { + goOp: AZSADDVD, + fixedBits: 0x4002000, + args: Zn_T__Pg__Dd__1, + }, + }, + // ZSADDWB + { + // ZSADDWB ., ., . + { + goOp: AZSADDWB, + fixedBits: 0x45004000, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZSADDWT + { + // ZSADDWT ., ., . + { + goOp: AZSADDWT, + fixedBits: 0x45004400, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZSBCLB + { + // ZSBCLB ., ., . + { + goOp: AZSBCLB, + fixedBits: 0x4580d000, + args: Zm_T__Zn_T__Zda_T__1, + }, + }, + // ZSBCLT + { + // ZSBCLT ., ., . + { + goOp: AZSBCLT, + fixedBits: 0x4580d400, + args: Zm_T__Zn_T__Zda_T__1, + }, + }, + // ZSCLAMP + { + // ZSCLAMP ., ., . + { + goOp: AZSCLAMP, + fixedBits: 0x4400c000, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZSCVTF + { + // ZSCVTF .D, /M, .D + { + goOp: AZSCVTF, + fixedBits: 0x65d6a000, + args: Zn_D__PgM__Zd_D, + }, + // ZSCVTF .D, /M, .H + { + goOp: AZSCVTF, + fixedBits: 0x6556a000, + args: Zn_D__PgM__Zd_H, + }, + // ZSCVTF .D, /M, .S + { + goOp: AZSCVTF, + fixedBits: 0x65d4a000, + args: Zn_D__PgM__Zd_S, + }, + // ZSCVTF .D, /Z, .D + { + goOp: AZSCVTF, + fixedBits: 0x64ddc000, + args: Zn_D__PgZ__Zd_D, + }, + // ZSCVTF .D, /Z, .H + { + goOp: AZSCVTF, + fixedBits: 0x645dc000, + args: Zn_D__PgZ__Zd_H, + }, + // ZSCVTF .D, /Z, .S + { + goOp: AZSCVTF, + fixedBits: 0x64dd8000, + args: Zn_D__PgZ__Zd_S, + }, + // ZSCVTF .H, /M, .H + { + goOp: AZSCVTF, + fixedBits: 0x6552a000, + args: Zn_H__PgM__Zd_H, + }, + // ZSCVTF .H, /Z, .H + { + goOp: AZSCVTF, + fixedBits: 0x645cc000, + args: Zn_H__PgZ__Zd_H, + }, + // ZSCVTF .S, /M, .D + { + goOp: AZSCVTF, + fixedBits: 0x65d0a000, + args: Zn_S__PgM__Zd_D, + }, + // ZSCVTF .S, /M, .H + { + goOp: AZSCVTF, + fixedBits: 0x6554a000, + args: Zn_S__PgM__Zd_H, + }, + // ZSCVTF .S, /M, .S + { + goOp: AZSCVTF, + fixedBits: 0x6594a000, + args: Zn_S__PgM__Zd_S, + }, + // ZSCVTF .S, /Z, .D + { + goOp: AZSCVTF, + fixedBits: 0x64dc8000, + args: Zn_S__PgZ__Zd_D, + }, + // ZSCVTF .S, /Z, .H + { + goOp: AZSCVTF, + fixedBits: 0x645d8000, + args: Zn_S__PgZ__Zd_H, + }, + // ZSCVTF .S, /Z, .S + { + goOp: AZSCVTF, + fixedBits: 0x649d8000, + args: Zn_S__PgZ__Zd_S, + }, + // ZSCVTF ., . + { + goOp: AZSCVTF, + fixedBits: 0x650c3000, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZSCVTFLT + { + // ZSCVTFLT ., . + { + goOp: AZSCVTFLT, + fixedBits: 0x650c3800, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZSDIV + { + // ZSDIV ., ., /M, . + { + goOp: AZSDIV, + fixedBits: 0x4940000, + args: Zm_T__Zdn_T__PgM__Zdn_T__4, + }, + }, + // ZSDIVR + { + // ZSDIVR ., ., /M, . + { + goOp: AZSDIVR, + fixedBits: 0x4960000, + args: Zm_T__Zdn_T__PgM__Zdn_T__4, + }, + }, + // ZSDOT + { + // ZSDOT .B, .B, .H + { + goOp: AZSDOT, + fixedBits: 0x44400000, + args: Zm_B__Zn_B__Zda_H, + }, + // ZSDOT .H, .H, .S + { + goOp: AZSDOT, + fixedBits: 0x4400c800, + args: Zm_H__Zn_H__Zda_S, + }, + // ZSDOT ., ., . + { + goOp: AZSDOT, + fixedBits: 0x44800000, + args: Zm_Tb__Zn_Tb__Zda_T__2, + }, + // ZSDOT .B[], .B, .H + { + goOp: AZSDOT, + fixedBits: 0x44200000, + args: Zm_B_imm___Zn_B__Zda_H__2, + }, + // ZSDOT .B[], .B, .S + { + goOp: AZSDOT, + fixedBits: 0x44a00000, + args: Zm_B_imm___Zn_B__Zda_S__3, + }, + // ZSDOT .H[], .H, .D + { + goOp: AZSDOT, + fixedBits: 0x44e00000, + args: Zm_H_imm___Zn_H__Zda_D, + }, + // ZSDOT .H[], .H, .S + { + goOp: AZSDOT, + fixedBits: 0x4480c800, + args: Zm_H_imm___Zn_H__Zda_S__4, + }, + }, + // ZSEL + { + // ZSEL ., ., , . + { + goOp: AZSEL, + fixedBits: 0x520c000, + args: Zm_T__Zn_T__Pv__Zd_T, + }, + }, + // ZSHADD + { + // ZSHADD ., ., /M, . + { + goOp: AZSHADD, + fixedBits: 0x44108000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSHRNB + { + // ZSHRNB #, ., . + { + goOp: AZSHRNB, + fixedBits: 0x45201000, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSHRNT + { + // ZSHRNT #, ., . + { + goOp: AZSHRNT, + fixedBits: 0x45201400, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSHSUB + { + // ZSHSUB ., ., /M, . + { + goOp: AZSHSUB, + fixedBits: 0x44128000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSHSUBR + { + // ZSHSUBR ., ., /M, . + { + goOp: AZSHSUBR, + fixedBits: 0x44168000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSLI + { + // ZSLI #, ., . + { + goOp: AZSLI, + fixedBits: 0x4500f400, + args: cconst__Zn_T__Zd_T__2, + }, + }, + // ZSM4E + { + // ZSM4E .S, .S, .S + { + goOp: AZSM4E, + fixedBits: 0x4523e000, + args: Zm_S__Zdn_S__Zdn_S, + }, + }, + // ZSM4EKEY + { + // ZSM4EKEY .S, .S, .S + { + goOp: AZSM4EKEY, + fixedBits: 0x4520f000, + args: Zm_S__Zn_S__Zd_S, + }, + }, + // ZSMAX + { + // ZSMAX ., ., /M, . + { + goOp: AZSMAX, + fixedBits: 0x4080000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZSMAX #, ., . + { + goOp: AZSMAX, + fixedBits: 0x2528c000, + args: cimm__Zdn_T__Zdn_T__1, + }, + }, + // ZSMAXP + { + // ZSMAXP ., ., /M, . + { + goOp: AZSMAXP, + fixedBits: 0x4414a000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSMAXQV + { + // ZSMAXQV ., , . + { + goOp: AZSMAXQV, + fixedBits: 0x40c2000, + args: Zn_Tb__Pg__Vd_T__1, + }, + }, + // ZSMAXVB + { + // ZSMAXVB ., , + { + goOp: AZSMAXVB, + fixedBits: 0x4082000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZSMAXVD + { + // ZSMAXVD ., , + { + goOp: AZSMAXVD, + fixedBits: 0x4c82000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZSMAXVH + { + // ZSMAXVH ., , + { + goOp: AZSMAXVH, + fixedBits: 0x4482000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZSMAXVS + { + // ZSMAXVS ., , + { + goOp: AZSMAXVS, + fixedBits: 0x4882000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZSMIN + { + // ZSMIN ., ., /M, . + { + goOp: AZSMIN, + fixedBits: 0x40a0000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZSMIN #, ., . + { + goOp: AZSMIN, + fixedBits: 0x252ac000, + args: cimm__Zdn_T__Zdn_T__1, + }, + }, + // ZSMINP + { + // ZSMINP ., ., /M, . + { + goOp: AZSMINP, + fixedBits: 0x4416a000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSMINQV + { + // ZSMINQV ., , . + { + goOp: AZSMINQV, + fixedBits: 0x40e2000, + args: Zn_Tb__Pg__Vd_T__1, + }, + }, + // ZSMINVB + { + // ZSMINVB ., , + { + goOp: AZSMINVB, + fixedBits: 0x40a2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZSMINVD + { + // ZSMINVD ., , + { + goOp: AZSMINVD, + fixedBits: 0x4ca2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZSMINVH + { + // ZSMINVH ., , + { + goOp: AZSMINVH, + fixedBits: 0x44a2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZSMINVS + { + // ZSMINVS ., , + { + goOp: AZSMINVS, + fixedBits: 0x48a2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZSMLALB + { + // ZSMLALB ., ., . + { + goOp: AZSMLALB, + fixedBits: 0x44004000, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZSMLALB .H[], .H, .S + { + goOp: AZSMLALB, + fixedBits: 0x44a08000, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZSMLALB .S[], .S, .D + { + goOp: AZSMLALB, + fixedBits: 0x44e08000, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZSMLALT + { + // ZSMLALT ., ., . + { + goOp: AZSMLALT, + fixedBits: 0x44004400, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZSMLALT .H[], .H, .S + { + goOp: AZSMLALT, + fixedBits: 0x44a08400, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZSMLALT .S[], .S, .D + { + goOp: AZSMLALT, + fixedBits: 0x44e08400, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZSMLSLB + { + // ZSMLSLB ., ., . + { + goOp: AZSMLSLB, + fixedBits: 0x44005000, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZSMLSLB .H[], .H, .S + { + goOp: AZSMLSLB, + fixedBits: 0x44a0a000, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZSMLSLB .S[], .S, .D + { + goOp: AZSMLSLB, + fixedBits: 0x44e0a000, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZSMLSLT + { + // ZSMLSLT ., ., . + { + goOp: AZSMLSLT, + fixedBits: 0x44005400, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZSMLSLT .H[], .H, .S + { + goOp: AZSMLSLT, + fixedBits: 0x44a0a400, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZSMLSLT .S[], .S, .D + { + goOp: AZSMLSLT, + fixedBits: 0x44e0a400, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZSMMLA + { + // ZSMMLA .B, .B, .S + { + goOp: AZSMMLA, + fixedBits: 0x45009800, + args: Zm_B__Zn_B__Zda_S, + }, + }, + // ZSMULH + { + // ZSMULH ., ., /M, . + { + goOp: AZSMULH, + fixedBits: 0x4120000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZSMULH ., ., . + { + goOp: AZSMULH, + fixedBits: 0x4206800, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZSMULLB + { + // ZSMULLB ., ., . + { + goOp: AZSMULLB, + fixedBits: 0x45007000, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + // ZSMULLB .H[], .H, .S + { + goOp: AZSMULLB, + fixedBits: 0x44a0c000, + args: Zm_H_imm___Zn_H__Zd_S, + }, + // ZSMULLB .S[], .S, .D + { + goOp: AZSMULLB, + fixedBits: 0x44e0c000, + args: Zm_S_imm___Zn_S__Zd_D, + }, + }, + // ZSMULLT + { + // ZSMULLT ., ., . + { + goOp: AZSMULLT, + fixedBits: 0x45007400, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + // ZSMULLT .H[], .H, .S + { + goOp: AZSMULLT, + fixedBits: 0x44a0c400, + args: Zm_H_imm___Zn_H__Zd_S, + }, + // ZSMULLT .S[], .S, .D + { + goOp: AZSMULLT, + fixedBits: 0x44e0c400, + args: Zm_S_imm___Zn_S__Zd_D, + }, + }, + // ZSPLICE + { + // ZSPLICE ., ., , . + { + goOp: AZSPLICE, + fixedBits: 0x52c8000, + args: Zm_T__Zdn_T__Pv__Zdn_T, + }, + // ZSPLICE { ., . }, , . + { + goOp: AZSPLICE, + fixedBits: 0x52d8000, + args: Zn1_T__Zn2_T___Pv__Zd_T, + }, + }, + // ZSQABS + { + // ZSQABS ., /M, . + { + goOp: AZSQABS, + fixedBits: 0x4408a000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZSQABS ., /Z, . + { + goOp: AZSQABS, + fixedBits: 0x440aa000, + args: Zn_T__PgZ__Zd_T__2, + }, + }, + // ZSQADD + { + // ZSQADD ., ., /M, . + { + goOp: AZSQADD, + fixedBits: 0x44188000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZSQADD ., ., . + { + goOp: AZSQADD, + fixedBits: 0x4201000, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZSQADD #{, }, ., . + { + goOp: AZSQADD, + fixedBits: 0x2524c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, + }, + // ZSQCADD + { + // ZSQCADD , ., ., . + { + goOp: AZSQCADD, + fixedBits: 0x4501d800, + args: const__Zm_T__Zdn_T__Zdn_T, + }, + }, + // ZSQCVTN + { + // ZSQCVTN { .S-.S }, .H + { + goOp: AZSQCVTN, + fixedBits: 0x45314000, + args: Zn1_S_Zn2_S___Zd_H, + }, + }, + // ZSQCVTUN + { + // ZSQCVTUN { .S-.S }, .H + { + goOp: AZSQCVTUN, + fixedBits: 0x45315000, + args: Zn1_S_Zn2_S___Zd_H, + }, + }, + // ZSQDECP + { + // ZSQDECP ., . + { + goOp: AZSQDECP, + fixedBits: 0x252a8000, + args: Pm_T__Zdn_T, + }, + }, + // ZSQDMLALB + { + // ZSQDMLALB ., ., . + { + goOp: AZSQDMLALB, + fixedBits: 0x44006000, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZSQDMLALB .H[], .H, .S + { + goOp: AZSQDMLALB, + fixedBits: 0x44a02000, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZSQDMLALB .S[], .S, .D + { + goOp: AZSQDMLALB, + fixedBits: 0x44e02000, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZSQDMLALBT + { + // ZSQDMLALBT ., ., . + { + goOp: AZSQDMLALBT, + fixedBits: 0x44000800, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + }, + // ZSQDMLALT + { + // ZSQDMLALT ., ., . + { + goOp: AZSQDMLALT, + fixedBits: 0x44006400, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZSQDMLALT .H[], .H, .S + { + goOp: AZSQDMLALT, + fixedBits: 0x44a02400, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZSQDMLALT .S[], .S, .D + { + goOp: AZSQDMLALT, + fixedBits: 0x44e02400, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZSQDMLSLB + { + // ZSQDMLSLB ., ., . + { + goOp: AZSQDMLSLB, + fixedBits: 0x44006800, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZSQDMLSLB .H[], .H, .S + { + goOp: AZSQDMLSLB, + fixedBits: 0x44a03000, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZSQDMLSLB .S[], .S, .D + { + goOp: AZSQDMLSLB, + fixedBits: 0x44e03000, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZSQDMLSLBT + { + // ZSQDMLSLBT ., ., . + { + goOp: AZSQDMLSLBT, + fixedBits: 0x44000c00, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + }, + // ZSQDMLSLT + { + // ZSQDMLSLT ., ., . + { + goOp: AZSQDMLSLT, + fixedBits: 0x44006c00, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZSQDMLSLT .H[], .H, .S + { + goOp: AZSQDMLSLT, + fixedBits: 0x44a03400, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZSQDMLSLT .S[], .S, .D + { + goOp: AZSQDMLSLT, + fixedBits: 0x44e03400, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZSQDMULH + { + // ZSQDMULH ., ., . + { + goOp: AZSQDMULH, + fixedBits: 0x4207000, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZSQDMULH .D[], .D, .D + { + goOp: AZSQDMULH, + fixedBits: 0x44e0f000, + args: Zm_D_imm___Zn_D__Zd_D__1, + }, + // ZSQDMULH .H[], .H, .H + { + goOp: AZSQDMULH, + fixedBits: 0x4420f000, + args: Zm_H_imm___Zn_H__Zd_H__1, + }, + // ZSQDMULH .S[], .S, .S + { + goOp: AZSQDMULH, + fixedBits: 0x44a0f000, + args: Zm_S_imm___Zn_S__Zd_S__1, + }, + }, + // ZSQDMULLB + { + // ZSQDMULLB ., ., . + { + goOp: AZSQDMULLB, + fixedBits: 0x45006000, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + // ZSQDMULLB .H[], .H, .S + { + goOp: AZSQDMULLB, + fixedBits: 0x44a0e000, + args: Zm_H_imm___Zn_H__Zd_S, + }, + // ZSQDMULLB .S[], .S, .D + { + goOp: AZSQDMULLB, + fixedBits: 0x44e0e000, + args: Zm_S_imm___Zn_S__Zd_D, + }, + }, + // ZSQDMULLT + { + // ZSQDMULLT ., ., . + { + goOp: AZSQDMULLT, + fixedBits: 0x45006400, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + // ZSQDMULLT .H[], .H, .S + { + goOp: AZSQDMULLT, + fixedBits: 0x44a0e400, + args: Zm_H_imm___Zn_H__Zd_S, + }, + // ZSQDMULLT .S[], .S, .D + { + goOp: AZSQDMULLT, + fixedBits: 0x44e0e400, + args: Zm_S_imm___Zn_S__Zd_D, + }, + }, + // ZSQINCP + { + // ZSQINCP ., . + { + goOp: AZSQINCP, + fixedBits: 0x25288000, + args: Pm_T__Zdn_T, + }, + }, + // ZSQNEG + { + // ZSQNEG ., /M, . + { + goOp: AZSQNEG, + fixedBits: 0x4409a000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZSQNEG ., /Z, . + { + goOp: AZSQNEG, + fixedBits: 0x440ba000, + args: Zn_T__PgZ__Zd_T__2, + }, + }, + // ZSQRDCMLAH + { + // ZSQRDCMLAH , .H[], .H, .H + { + goOp: AZSQRDCMLAH, + fixedBits: 0x44a07000, + args: const__Zm_H_imm___Zn_H__Zda_H__1, + }, + // ZSQRDCMLAH , .S[], .S, .S + { + goOp: AZSQRDCMLAH, + fixedBits: 0x44e07000, + args: const__Zm_S_imm___Zn_S__Zda_S__1, + }, + // ZSQRDCMLAH , ., ., . + { + goOp: AZSQRDCMLAH, + fixedBits: 0x44003000, + args: const__Zm_T__Zn_T__Zda_T, + }, + }, + // ZSQRDMLAH + { + // ZSQRDMLAH ., ., . + { + goOp: AZSQRDMLAH, + fixedBits: 0x44007000, + args: Zm_T__Zn_T__Zda_T__2, + }, + // ZSQRDMLAH .D[], .D, .D + { + goOp: AZSQRDMLAH, + fixedBits: 0x44e01000, + args: Zm_D_imm___Zn_D__Zda_D__1, + }, + // ZSQRDMLAH .H[], .H, .H + { + goOp: AZSQRDMLAH, + fixedBits: 0x44201000, + args: Zm_H_imm___Zn_H__Zda_H__1, + }, + // ZSQRDMLAH .S[], .S, .S + { + goOp: AZSQRDMLAH, + fixedBits: 0x44a01000, + args: Zm_S_imm___Zn_S__Zda_S__1, + }, + }, + // ZSQRDMLSH + { + // ZSQRDMLSH ., ., . + { + goOp: AZSQRDMLSH, + fixedBits: 0x44007400, + args: Zm_T__Zn_T__Zda_T__2, + }, + // ZSQRDMLSH .D[], .D, .D + { + goOp: AZSQRDMLSH, + fixedBits: 0x44e01400, + args: Zm_D_imm___Zn_D__Zda_D__1, + }, + // ZSQRDMLSH .H[], .H, .H + { + goOp: AZSQRDMLSH, + fixedBits: 0x44201400, + args: Zm_H_imm___Zn_H__Zda_H__1, + }, + // ZSQRDMLSH .S[], .S, .S + { + goOp: AZSQRDMLSH, + fixedBits: 0x44a01400, + args: Zm_S_imm___Zn_S__Zda_S__1, + }, + }, + // ZSQRDMULH + { + // ZSQRDMULH ., ., . + { + goOp: AZSQRDMULH, + fixedBits: 0x4207400, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZSQRDMULH .D[], .D, .D + { + goOp: AZSQRDMULH, + fixedBits: 0x44e0f400, + args: Zm_D_imm___Zn_D__Zd_D__1, + }, + // ZSQRDMULH .H[], .H, .H + { + goOp: AZSQRDMULH, + fixedBits: 0x4420f400, + args: Zm_H_imm___Zn_H__Zd_H__1, + }, + // ZSQRDMULH .S[], .S, .S + { + goOp: AZSQRDMULH, + fixedBits: 0x44a0f400, + args: Zm_S_imm___Zn_S__Zd_S__1, + }, + }, + // ZSQRSHL + { + // ZSQRSHL ., ., /M, . + { + goOp: AZSQRSHL, + fixedBits: 0x440a8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSQRSHLR + { + // ZSQRSHLR ., ., /M, . + { + goOp: AZSQRSHLR, + fixedBits: 0x440e8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSQRSHRN + { + // ZSQRSHRN #, { .H-.H }, .B + { + goOp: AZSQRSHRN, + fixedBits: 0x45a82800, + args: cconst___Zn1_H_Zn2_H___Zd_B, + }, + // ZSQRSHRN #, { .S-.S }, .H + { + goOp: AZSQRSHRN, + fixedBits: 0x45b02800, + args: cconst___Zn1_S_Zn2_S___Zd_H, + }, + }, + // ZSQRSHRNB + { + // ZSQRSHRNB #, ., . + { + goOp: AZSQRSHRNB, + fixedBits: 0x45202800, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQRSHRNT + { + // ZSQRSHRNT #, ., . + { + goOp: AZSQRSHRNT, + fixedBits: 0x45202c00, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQRSHRUN + { + // ZSQRSHRUN #, { .H-.H }, .B + { + goOp: AZSQRSHRUN, + fixedBits: 0x45a80800, + args: cconst___Zn1_H_Zn2_H___Zd_B, + }, + // ZSQRSHRUN #, { .S-.S }, .H + { + goOp: AZSQRSHRUN, + fixedBits: 0x45b00800, + args: cconst___Zn1_S_Zn2_S___Zd_H, + }, + }, + // ZSQRSHRUNB + { + // ZSQRSHRUNB #, ., . + { + goOp: AZSQRSHRUNB, + fixedBits: 0x45200800, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQRSHRUNT + { + // ZSQRSHRUNT #, ., . + { + goOp: AZSQRSHRUNT, + fixedBits: 0x45200c00, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQSHL + { + // ZSQSHL ., ., /M, . + { + goOp: AZSQSHL, + fixedBits: 0x44088000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZSQSHL #, ., /M, . + { + goOp: AZSQSHL, + fixedBits: 0x4068000, + args: cconst__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZSQSHLR + { + // ZSQSHLR ., ., /M, . + { + goOp: AZSQSHLR, + fixedBits: 0x440c8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSQSHLU + { + // ZSQSHLU #, ., /M, . + { + goOp: AZSQSHLU, + fixedBits: 0x40f8000, + args: cconst__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZSQSHRN + { + // ZSQSHRN #, { .-. }, . + { + goOp: AZSQSHRN, + fixedBits: 0x45a00000, + args: cconst___Zn1_Tb_Zn2_Tb___Zd_T, + }, + }, + // ZSQSHRNB + { + // ZSQSHRNB #, ., . + { + goOp: AZSQSHRNB, + fixedBits: 0x45202000, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQSHRNT + { + // ZSQSHRNT #, ., . + { + goOp: AZSQSHRNT, + fixedBits: 0x45202400, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQSHRUN + { + // ZSQSHRUN #, { .-. }, . + { + goOp: AZSQSHRUN, + fixedBits: 0x45a02000, + args: cconst___Zn1_Tb_Zn2_Tb___Zd_T, + }, + }, + // ZSQSHRUNB + { + // ZSQSHRUNB #, ., . + { + goOp: AZSQSHRUNB, + fixedBits: 0x45200000, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQSHRUNT + { + // ZSQSHRUNT #, ., . + { + goOp: AZSQSHRUNT, + fixedBits: 0x45200400, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQSUB + { + // ZSQSUB ., ., /M, . + { + goOp: AZSQSUB, + fixedBits: 0x441a8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZSQSUB ., ., . + { + goOp: AZSQSUB, + fixedBits: 0x4201800, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZSQSUB #{, }, ., . + { + goOp: AZSQSUB, + fixedBits: 0x2526c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, + }, + // ZSQSUBR + { + // ZSQSUBR ., ., /M, . + { + goOp: AZSQSUBR, + fixedBits: 0x441e8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSQXTNB + { + // ZSQXTNB ., . + { + goOp: AZSQXTNB, + fixedBits: 0x45204000, + args: Zn_Tb__Zd_T__2, + }, + }, + // ZSQXTNT + { + // ZSQXTNT ., . + { + goOp: AZSQXTNT, + fixedBits: 0x45204400, + args: Zn_Tb__Zd_T__2, + }, + }, + // ZSQXTUNB + { + // ZSQXTUNB ., . + { + goOp: AZSQXTUNB, + fixedBits: 0x45205000, + args: Zn_Tb__Zd_T__2, + }, + }, + // ZSQXTUNT + { + // ZSQXTUNT ., . + { + goOp: AZSQXTUNT, + fixedBits: 0x45205400, + args: Zn_Tb__Zd_T__2, + }, + }, + // ZSRHADD + { + // ZSRHADD ., ., /M, . + { + goOp: AZSRHADD, + fixedBits: 0x44148000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSRI + { + // ZSRI #, ., . + { + goOp: AZSRI, + fixedBits: 0x4500f000, + args: cconst__Zn_T__Zd_T__1, + }, + }, + // ZSRSHL + { + // ZSRSHL ., ., /M, . + { + goOp: AZSRSHL, + fixedBits: 0x44028000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSRSHLR + { + // ZSRSHLR ., ., /M, . + { + goOp: AZSRSHLR, + fixedBits: 0x44068000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSRSHR + { + // ZSRSHR #, ., /M, . + { + goOp: AZSRSHR, + fixedBits: 0x40c8000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSRSRA + { + // ZSRSRA #, ., . + { + goOp: AZSRSRA, + fixedBits: 0x4500e800, + args: cconst__Zn_T__Zda_T, + }, + }, + // ZSSHLLB + { + // ZSSHLLB #, ., . + { + goOp: AZSSHLLB, + fixedBits: 0x4500a000, + args: cconst__Zn_Tb__Zd_T__2, + }, + }, + // ZSSHLLT + { + // ZSSHLLT #, ., . + { + goOp: AZSSHLLT, + fixedBits: 0x4500a400, + args: cconst__Zn_Tb__Zd_T__2, + }, + }, + // ZSSRA + { + // ZSSRA #, ., . + { + goOp: AZSSRA, + fixedBits: 0x4500e000, + args: cconst__Zn_T__Zda_T, + }, + }, + // ZSSUBLB + { + // ZSSUBLB ., ., . + { + goOp: AZSSUBLB, + fixedBits: 0x45001000, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZSSUBLBT + { + // ZSSUBLBT ., ., . + { + goOp: AZSSUBLBT, + fixedBits: 0x45008800, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZSSUBLT + { + // ZSSUBLT ., ., . + { + goOp: AZSSUBLT, + fixedBits: 0x45001400, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZSSUBLTB + { + // ZSSUBLTB ., ., . + { + goOp: AZSSUBLTB, + fixedBits: 0x45008c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZSSUBWB + { + // ZSSUBWB ., ., . + { + goOp: AZSSUBWB, + fixedBits: 0x45005000, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZSSUBWT + { + // ZSSUBWT ., ., . + { + goOp: AZSSUBWT, + fixedBits: 0x45005400, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZST1B + { + // ZST1B { .D }, , [, .D] + { + goOp: AZST1B, + fixedBits: 0xe400a000, + args: Zt_D___Pg___XnSP__Zm_D_, + }, + // ZST1B { .D }, , [, .D, ] + { + goOp: AZST1B, + fixedBits: 0xe4008000, + args: Zt_D___Pg___XnSP__Zm_D__mod_, + }, + // ZST1B { .S }, , [, .S, ] + { + goOp: AZST1B, + fixedBits: 0xe4408000, + args: Zt_S___Pg___XnSP__Zm_S__mod_, + }, + // ZST1B { . }, , [, ] + { + goOp: AZST1B, + fixedBits: 0xe4004000, + args: Zt_T___Pg___XnSP__Xm_, + }, + // ZST1B { .D }, , [.D{, #}] + { + goOp: AZST1B, + fixedBits: 0xe440a000, + args: Zt_D___Pg___Zn_D__cimm___1, + }, + // ZST1B { .S }, , [.S{, #}] + { + goOp: AZST1B, + fixedBits: 0xe460a000, + args: Zt_S___Pg___Zn_S__cimm___1, + }, + // ZST1B { . }, , [{, #, MUL VL}] + { + goOp: AZST1B, + fixedBits: 0xe400e000, + args: Zt_T___Pg___XnSP__cimm__MUL_VL___1, + }, + // ZST1B { .B-.B }, , [, ] + { + goOp: AZST1B, + fixedBits: 0xa0200000, + args: Zt1_B_Zt2_B___PNg___XnSP__Xm_, + }, + // ZST1B { .B-.B }, , [{, #, MUL VL}] + { + goOp: AZST1B, + fixedBits: 0xa0600000, + args: Zt1_B_Zt2_B___PNg___XnSP__cimm__MUL_VL_, + }, + // ZST1B { .B-.B }, , [, ] + { + goOp: AZST1B, + fixedBits: 0xa0208000, + args: Zt1_B_Zt4_B___PNg___XnSP__Xm_, + }, + // ZST1B { .B-.B }, , [{, #, MUL VL}] + { + goOp: AZST1B, + fixedBits: 0xa0608000, + args: Zt1_B_Zt4_B___PNg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST1D + { + // ZST1D { .D }, , [, , LSL #3] + { + goOp: AZST1D, + fixedBits: 0xe5e04000, + args: Zt_D___Pg___XnSP__Xm__LSL_c3_, + }, + // ZST1D { .D }, , [, .D] + { + goOp: AZST1D, + fixedBits: 0xe580a000, + args: Zt_D___Pg___XnSP__Zm_D_, + }, + // ZST1D { .D }, , [, .D, LSL #3] + { + goOp: AZST1D, + fixedBits: 0xe5a0a000, + args: Zt_D___Pg___XnSP__Zm_D__LSL_c3_, + }, + // ZST1D { .D }, , [, .D, ] + { + goOp: AZST1D, + fixedBits: 0xe5808000, + args: Zt_D___Pg___XnSP__Zm_D__mod_, + }, + // ZST1D { .D }, , [, .D, #3] + { + goOp: AZST1D, + fixedBits: 0xe5a08000, + args: Zt_D___Pg___XnSP__Zm_D__mod_c3_, + }, + // ZST1D { .Q }, , [, , LSL #3] + { + goOp: AZST1D, + fixedBits: 0xe5c04000, + args: Zt_Q___Pg___XnSP__Xm__LSL_c3_, + }, + // ZST1D { .D }, , [.D{, #}] + { + goOp: AZST1D, + fixedBits: 0xe5c0a000, + args: Zt_D___Pg___Zn_D__cimm___2, + }, + // ZST1D { .D }, , [{, #, MUL VL}] + { + goOp: AZST1D, + fixedBits: 0xe5e0e000, + args: Zt_D___Pg___XnSP__cimm__MUL_VL_, + }, + // ZST1D { .Q }, , [{, #, MUL VL}] + { + goOp: AZST1D, + fixedBits: 0xe5c0e000, + args: Zt_Q___Pg___XnSP__cimm__MUL_VL_, + }, + // ZST1D { .D-.D }, , [, , LSL #3] + { + goOp: AZST1D, + fixedBits: 0xa0206000, + args: Zt1_D_Zt2_D___PNg___XnSP__Xm__LSL_c3_, + }, + // ZST1D { .D-.D }, , [{, #, MUL VL}] + { + goOp: AZST1D, + fixedBits: 0xa0606000, + args: Zt1_D_Zt2_D___PNg___XnSP__cimm__MUL_VL_, + }, + // ZST1D { .D-.D }, , [, , LSL #3] + { + goOp: AZST1D, + fixedBits: 0xa020e000, + args: Zt1_D_Zt4_D___PNg___XnSP__Xm__LSL_c3_, + }, + // ZST1D { .D-.D }, , [{, #, MUL VL}] + { + goOp: AZST1D, + fixedBits: 0xa060e000, + args: Zt1_D_Zt4_D___PNg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST1H + { + // ZST1H { .D }, , [, .D] + { + goOp: AZST1H, + fixedBits: 0xe480a000, + args: Zt_D___Pg___XnSP__Zm_D_, + }, + // ZST1H { .D }, , [, .D, LSL #1] + { + goOp: AZST1H, + fixedBits: 0xe4a0a000, + args: Zt_D___Pg___XnSP__Zm_D__LSL_c1_, + }, + // ZST1H { .D }, , [, .D, ] + { + goOp: AZST1H, + fixedBits: 0xe4808000, + args: Zt_D___Pg___XnSP__Zm_D__mod_, + }, + // ZST1H { .D }, , [, .D, #1] + { + goOp: AZST1H, + fixedBits: 0xe4a08000, + args: Zt_D___Pg___XnSP__Zm_D__mod_c1_, + }, + // ZST1H { .S }, , [, .S, ] + { + goOp: AZST1H, + fixedBits: 0xe4c08000, + args: Zt_S___Pg___XnSP__Zm_S__mod_, + }, + // ZST1H { .S }, , [, .S, #1] + { + goOp: AZST1H, + fixedBits: 0xe4e08000, + args: Zt_S___Pg___XnSP__Zm_S__mod_c1_, + }, + // ZST1H { . }, , [, , LSL #1] + { + goOp: AZST1H, + fixedBits: 0xe4804000, + args: Zt_T___Pg___XnSP__Xm__LSL_c1_, + }, + // ZST1H { .D }, , [.D{, #}] + { + goOp: AZST1H, + fixedBits: 0xe4c0a000, + args: Zt_D___Pg___Zn_D__cimm___3, + }, + // ZST1H { .S }, , [.S{, #}] + { + goOp: AZST1H, + fixedBits: 0xe4e0a000, + args: Zt_S___Pg___Zn_S__cimm___2, + }, + // ZST1H { . }, , [{, #, MUL VL}] + { + goOp: AZST1H, + fixedBits: 0xe480e000, + args: Zt_T___Pg___XnSP__cimm__MUL_VL___2, + }, + // ZST1H { .H-.H }, , [, , LSL #1] + { + goOp: AZST1H, + fixedBits: 0xa0202000, + args: Zt1_H_Zt2_H___PNg___XnSP__Xm__LSL_c1_, + }, + // ZST1H { .H-.H }, , [{, #, MUL VL}] + { + goOp: AZST1H, + fixedBits: 0xa0602000, + args: Zt1_H_Zt2_H___PNg___XnSP__cimm__MUL_VL_, + }, + // ZST1H { .H-.H }, , [, , LSL #1] + { + goOp: AZST1H, + fixedBits: 0xa020a000, + args: Zt1_H_Zt4_H___PNg___XnSP__Xm__LSL_c1_, + }, + // ZST1H { .H-.H }, , [{, #, MUL VL}] + { + goOp: AZST1H, + fixedBits: 0xa060a000, + args: Zt1_H_Zt4_H___PNg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST1Q + { + // ZST1Q { .Q }, , [.D{, }] + { + goOp: AZST1Q, + fixedBits: 0xe4202000, + args: Zt_Q___Pg___Zn_D__Xm_, + }, + }, + // ZST1W + { + // ZST1W { .D }, , [, .D] + { + goOp: AZST1W, + fixedBits: 0xe500a000, + args: Zt_D___Pg___XnSP__Zm_D_, + }, + // ZST1W { .D }, , [, .D, LSL #2] + { + goOp: AZST1W, + fixedBits: 0xe520a000, + args: Zt_D___Pg___XnSP__Zm_D__LSL_c2_, + }, + // ZST1W { .D }, , [, .D, ] + { + goOp: AZST1W, + fixedBits: 0xe5008000, + args: Zt_D___Pg___XnSP__Zm_D__mod_, + }, + // ZST1W { .D }, , [, .D, #2] + { + goOp: AZST1W, + fixedBits: 0xe5208000, + args: Zt_D___Pg___XnSP__Zm_D__mod_c2_, + }, + // ZST1W { .Q }, , [, , LSL #2] + { + goOp: AZST1W, + fixedBits: 0xe5004000, + args: Zt_Q___Pg___XnSP__Xm__LSL_c2_, + }, + // ZST1W { .S }, , [, .S, ] + { + goOp: AZST1W, + fixedBits: 0xe5408000, + args: Zt_S___Pg___XnSP__Zm_S__mod_, + }, + // ZST1W { .S }, , [, .S, #2] + { + goOp: AZST1W, + fixedBits: 0xe5608000, + args: Zt_S___Pg___XnSP__Zm_S__mod_c2_, + }, + // ZST1W { . }, , [, , LSL #2] + { + goOp: AZST1W, + fixedBits: 0xe5404000, + args: Zt_T___Pg___XnSP__Xm__LSL_c2_, + }, + // ZST1W { .D }, , [.D{, #}] + { + goOp: AZST1W, + fixedBits: 0xe540a000, + args: Zt_D___Pg___Zn_D__cimm___4, + }, + // ZST1W { .S }, , [.S{, #}] + { + goOp: AZST1W, + fixedBits: 0xe560a000, + args: Zt_S___Pg___Zn_S__cimm___3, + }, + // ZST1W { .Q }, , [{, #, MUL VL}] + { + goOp: AZST1W, + fixedBits: 0xe500e000, + args: Zt_Q___Pg___XnSP__cimm__MUL_VL_, + }, + // ZST1W { . }, , [{, #, MUL VL}] + { + goOp: AZST1W, + fixedBits: 0xe540e000, + args: Zt_T___Pg___XnSP__cimm__MUL_VL___3, + }, + // ZST1W { .S-.S }, , [, , LSL #2] + { + goOp: AZST1W, + fixedBits: 0xa0204000, + args: Zt1_S_Zt2_S___PNg___XnSP__Xm__LSL_c2_, + }, + // ZST1W { .S-.S }, , [{, #, MUL VL}] + { + goOp: AZST1W, + fixedBits: 0xa0604000, + args: Zt1_S_Zt2_S___PNg___XnSP__cimm__MUL_VL_, + }, + // ZST1W { .S-.S }, , [, , LSL #2] + { + goOp: AZST1W, + fixedBits: 0xa020c000, + args: Zt1_S_Zt4_S___PNg___XnSP__Xm__LSL_c2_, + }, + // ZST1W { .S-.S }, , [{, #, MUL VL}] + { + goOp: AZST1W, + fixedBits: 0xa060c000, + args: Zt1_S_Zt4_S___PNg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST2B + { + // ZST2B { .B, .B }, , [, ] + { + goOp: AZST2B, + fixedBits: 0xe4206000, + args: Zt1_B__Zt2_B___Pg___XnSP__Xm_, + }, + // ZST2B { .B, .B }, , [{, #, MUL VL}] + { + goOp: AZST2B, + fixedBits: 0xe430e000, + args: Zt1_B__Zt2_B___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST2D + { + // ZST2D { .D, .D }, , [, , LSL #3] + { + goOp: AZST2D, + fixedBits: 0xe5a06000, + args: Zt1_D__Zt2_D___Pg___XnSP__Xm__LSL_c3_, + }, + // ZST2D { .D, .D }, , [{, #, MUL VL}] + { + goOp: AZST2D, + fixedBits: 0xe5b0e000, + args: Zt1_D__Zt2_D___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST2H + { + // ZST2H { .H, .H }, , [, , LSL #1] + { + goOp: AZST2H, + fixedBits: 0xe4a06000, + args: Zt1_H__Zt2_H___Pg___XnSP__Xm__LSL_c1_, + }, + // ZST2H { .H, .H }, , [{, #, MUL VL}] + { + goOp: AZST2H, + fixedBits: 0xe4b0e000, + args: Zt1_H__Zt2_H___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST2Q + { + // ZST2Q { .Q, .Q }, , [, , LSL #4] + { + goOp: AZST2Q, + fixedBits: 0xe4600000, + args: Zt1_Q__Zt2_Q___Pg___XnSP__Xm__LSL_c4_, + }, + // ZST2Q { .Q, .Q }, , [{, #, MUL VL}] + { + goOp: AZST2Q, + fixedBits: 0xe4400000, + args: Zt1_Q__Zt2_Q___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST2W + { + // ZST2W { .S, .S }, , [, , LSL #2] + { + goOp: AZST2W, + fixedBits: 0xe5206000, + args: Zt1_S__Zt2_S___Pg___XnSP__Xm__LSL_c2_, + }, + // ZST2W { .S, .S }, , [{, #, MUL VL}] + { + goOp: AZST2W, + fixedBits: 0xe530e000, + args: Zt1_S__Zt2_S___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST3B + { + // ZST3B { .B, .B, .B }, , [, ] + { + goOp: AZST3B, + fixedBits: 0xe4406000, + args: Zt1_B__Zt2_B__Zt3_B___Pg___XnSP__Xm_, + }, + // ZST3B { .B, .B, .B }, , [{, #, MUL VL}] + { + goOp: AZST3B, + fixedBits: 0xe450e000, + args: Zt1_B__Zt2_B__Zt3_B___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST3D + { + // ZST3D { .D, .D, .D }, , [, , LSL #3] + { + goOp: AZST3D, + fixedBits: 0xe5c06000, + args: Zt1_D__Zt2_D__Zt3_D___Pg___XnSP__Xm__LSL_c3_, + }, + // ZST3D { .D, .D, .D }, , [{, #, MUL VL}] + { + goOp: AZST3D, + fixedBits: 0xe5d0e000, + args: Zt1_D__Zt2_D__Zt3_D___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST3H + { + // ZST3H { .H, .H, .H }, , [, , LSL #1] + { + goOp: AZST3H, + fixedBits: 0xe4c06000, + args: Zt1_H__Zt2_H__Zt3_H___Pg___XnSP__Xm__LSL_c1_, + }, + // ZST3H { .H, .H, .H }, , [{, #, MUL VL}] + { + goOp: AZST3H, + fixedBits: 0xe4d0e000, + args: Zt1_H__Zt2_H__Zt3_H___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST3Q + { + // ZST3Q { .Q, .Q, .Q }, , [, , LSL #4] + { + goOp: AZST3Q, + fixedBits: 0xe4a00000, + args: Zt1_Q__Zt2_Q__Zt3_Q___Pg___XnSP__Xm__LSL_c4_, + }, + // ZST3Q { .Q, .Q, .Q }, , [{, #, MUL VL}] + { + goOp: AZST3Q, + fixedBits: 0xe4800000, + args: Zt1_Q__Zt2_Q__Zt3_Q___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST3W + { + // ZST3W { .S, .S, .S }, , [, , LSL #2] + { + goOp: AZST3W, + fixedBits: 0xe5406000, + args: Zt1_S__Zt2_S__Zt3_S___Pg___XnSP__Xm__LSL_c2_, + }, + // ZST3W { .S, .S, .S }, , [{, #, MUL VL}] + { + goOp: AZST3W, + fixedBits: 0xe550e000, + args: Zt1_S__Zt2_S__Zt3_S___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST4B + { + // ZST4B { .B, .B, .B, .B }, , [, ] + { + goOp: AZST4B, + fixedBits: 0xe4606000, + args: Zt1_B__Zt2_B__Zt3_B__Zt4_B___Pg___XnSP__Xm_, + }, + // ZST4B { .B, .B, .B, .B }, , [{, #, MUL VL}] + { + goOp: AZST4B, + fixedBits: 0xe470e000, + args: Zt1_B__Zt2_B__Zt3_B__Zt4_B___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST4D + { + // ZST4D { .D, .D, .D, .D }, , [, , LSL #3] + { + goOp: AZST4D, + fixedBits: 0xe5e06000, + args: Zt1_D__Zt2_D__Zt3_D__Zt4_D___Pg___XnSP__Xm__LSL_c3_, + }, + // ZST4D { .D, .D, .D, .D }, , [{, #, MUL VL}] + { + goOp: AZST4D, + fixedBits: 0xe5f0e000, + args: Zt1_D__Zt2_D__Zt3_D__Zt4_D___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST4H + { + // ZST4H { .H, .H, .H, .H }, , [, , LSL #1] + { + goOp: AZST4H, + fixedBits: 0xe4e06000, + args: Zt1_H__Zt2_H__Zt3_H__Zt4_H___Pg___XnSP__Xm__LSL_c1_, + }, + // ZST4H { .H, .H, .H, .H }, , [{, #, MUL VL}] + { + goOp: AZST4H, + fixedBits: 0xe4f0e000, + args: Zt1_H__Zt2_H__Zt3_H__Zt4_H___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST4Q + { + // ZST4Q { .Q, .Q, .Q, .Q }, , [, , LSL #4] + { + goOp: AZST4Q, + fixedBits: 0xe4e00000, + args: Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q___Pg___XnSP__Xm__LSL_c4_, + }, + // ZST4Q { .Q, .Q, .Q, .Q }, , [{, #, MUL VL}] + { + goOp: AZST4Q, + fixedBits: 0xe4c00000, + args: Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZST4W + { + // ZST4W { .S, .S, .S, .S }, , [, , LSL #2] + { + goOp: AZST4W, + fixedBits: 0xe5606000, + args: Zt1_S__Zt2_S__Zt3_S__Zt4_S___Pg___XnSP__Xm__LSL_c2_, + }, + // ZST4W { .S, .S, .S, .S }, , [{, #, MUL VL}] + { + goOp: AZST4W, + fixedBits: 0xe570e000, + args: Zt1_S__Zt2_S__Zt3_S__Zt4_S___Pg___XnSP__cimm__MUL_VL_, + }, + }, + // ZSTNT1B + { + // ZSTNT1B { .B }, , [, ] + { + goOp: AZSTNT1B, + fixedBits: 0xe4006000, + args: Zt_B___Pg___XnSP__Xm_, + }, + // ZSTNT1B { .D }, , [.D{, }] + { + goOp: AZSTNT1B, + fixedBits: 0xe4002000, + args: Zt_D___Pg___Zn_D__Xm_, + }, + // ZSTNT1B { .S }, , [.S{, }] + { + goOp: AZSTNT1B, + fixedBits: 0xe4402000, + args: Zt_S___Pg___Zn_S__Xm_, + }, + // ZSTNT1B { .B }, , [{, #, MUL VL}] + { + goOp: AZSTNT1B, + fixedBits: 0xe410e000, + args: Zt_B___Pg___XnSP__cimm__MUL_VL_, + }, + // ZSTNT1B { .B-.B }, , [, ] + { + goOp: AZSTNT1B, + fixedBits: 0xa0200001, + args: Zt1_B_Zt2_B___PNg___XnSP__Xm_, + }, + // ZSTNT1B { .B-.B }, , [{, #, MUL VL}] + { + goOp: AZSTNT1B, + fixedBits: 0xa0600001, + args: Zt1_B_Zt2_B___PNg___XnSP__cimm__MUL_VL_, + }, + // ZSTNT1B { .B-.B }, , [, ] + { + goOp: AZSTNT1B, + fixedBits: 0xa0208001, + args: Zt1_B_Zt4_B___PNg___XnSP__Xm_, + }, + // ZSTNT1B { .B-.B }, , [{, #, MUL VL}] + { + goOp: AZSTNT1B, + fixedBits: 0xa0608001, + args: Zt1_B_Zt4_B___PNg___XnSP__cimm__MUL_VL_, + }, + }, + // ZSTNT1D + { + // ZSTNT1D { .D }, , [, , LSL #3] + { + goOp: AZSTNT1D, + fixedBits: 0xe5806000, + args: Zt_D___Pg___XnSP__Xm__LSL_c3_, + }, + // ZSTNT1D { .D }, , [.D{, }] + { + goOp: AZSTNT1D, + fixedBits: 0xe5802000, + args: Zt_D___Pg___Zn_D__Xm_, + }, + // ZSTNT1D { .D }, , [{, #, MUL VL}] + { + goOp: AZSTNT1D, + fixedBits: 0xe590e000, + args: Zt_D___Pg___XnSP__cimm__MUL_VL_, + }, + // ZSTNT1D { .D-.D }, , [, , LSL #3] + { + goOp: AZSTNT1D, + fixedBits: 0xa0206001, + args: Zt1_D_Zt2_D___PNg___XnSP__Xm__LSL_c3_, + }, + // ZSTNT1D { .D-.D }, , [{, #, MUL VL}] + { + goOp: AZSTNT1D, + fixedBits: 0xa0606001, + args: Zt1_D_Zt2_D___PNg___XnSP__cimm__MUL_VL_, + }, + // ZSTNT1D { .D-.D }, , [, , LSL #3] + { + goOp: AZSTNT1D, + fixedBits: 0xa020e001, + args: Zt1_D_Zt4_D___PNg___XnSP__Xm__LSL_c3_, + }, + // ZSTNT1D { .D-.D }, , [{, #, MUL VL}] + { + goOp: AZSTNT1D, + fixedBits: 0xa060e001, + args: Zt1_D_Zt4_D___PNg___XnSP__cimm__MUL_VL_, + }, + }, + // ZSTNT1H + { + // ZSTNT1H { .D }, , [.D{, }] + { + goOp: AZSTNT1H, + fixedBits: 0xe4802000, + args: Zt_D___Pg___Zn_D__Xm_, + }, + // ZSTNT1H { .H }, , [, , LSL #1] + { + goOp: AZSTNT1H, + fixedBits: 0xe4806000, + args: Zt_H___Pg___XnSP__Xm__LSL_c1_, + }, + // ZSTNT1H { .S }, , [.S{, }] + { + goOp: AZSTNT1H, + fixedBits: 0xe4c02000, + args: Zt_S___Pg___Zn_S__Xm_, + }, + // ZSTNT1H { .H }, , [{, #, MUL VL}] + { + goOp: AZSTNT1H, + fixedBits: 0xe490e000, + args: Zt_H___Pg___XnSP__cimm__MUL_VL_, + }, + // ZSTNT1H { .H-.H }, , [, , LSL #1] + { + goOp: AZSTNT1H, + fixedBits: 0xa0202001, + args: Zt1_H_Zt2_H___PNg___XnSP__Xm__LSL_c1_, + }, + // ZSTNT1H { .H-.H }, , [{, #, MUL VL}] + { + goOp: AZSTNT1H, + fixedBits: 0xa0602001, + args: Zt1_H_Zt2_H___PNg___XnSP__cimm__MUL_VL_, + }, + // ZSTNT1H { .H-.H }, , [, , LSL #1] + { + goOp: AZSTNT1H, + fixedBits: 0xa020a001, + args: Zt1_H_Zt4_H___PNg___XnSP__Xm__LSL_c1_, + }, + // ZSTNT1H { .H-.H }, , [{, #, MUL VL}] + { + goOp: AZSTNT1H, + fixedBits: 0xa060a001, + args: Zt1_H_Zt4_H___PNg___XnSP__cimm__MUL_VL_, + }, + }, + // ZSTNT1W + { + // ZSTNT1W { .D }, , [.D{, }] + { + goOp: AZSTNT1W, + fixedBits: 0xe5002000, + args: Zt_D___Pg___Zn_D__Xm_, + }, + // ZSTNT1W { .S }, , [, , LSL #2] + { + goOp: AZSTNT1W, + fixedBits: 0xe5006000, + args: Zt_S___Pg___XnSP__Xm__LSL_c2_, + }, + // ZSTNT1W { .S }, , [.S{, }] + { + goOp: AZSTNT1W, + fixedBits: 0xe5402000, + args: Zt_S___Pg___Zn_S__Xm_, + }, + // ZSTNT1W { .S }, , [{, #, MUL VL}] + { + goOp: AZSTNT1W, + fixedBits: 0xe510e000, + args: Zt_S___Pg___XnSP__cimm__MUL_VL_, + }, + // ZSTNT1W { .S-.S }, , [, , LSL #2] + { + goOp: AZSTNT1W, + fixedBits: 0xa0204001, + args: Zt1_S_Zt2_S___PNg___XnSP__Xm__LSL_c2_, + }, + // ZSTNT1W { .S-.S }, , [{, #, MUL VL}] + { + goOp: AZSTNT1W, + fixedBits: 0xa0604001, + args: Zt1_S_Zt2_S___PNg___XnSP__cimm__MUL_VL_, + }, + // ZSTNT1W { .S-.S }, , [, , LSL #2] + { + goOp: AZSTNT1W, + fixedBits: 0xa020c001, + args: Zt1_S_Zt4_S___PNg___XnSP__Xm__LSL_c2_, + }, + // ZSTNT1W { .S-.S }, , [{, #, MUL VL}] + { + goOp: AZSTNT1W, + fixedBits: 0xa060c001, + args: Zt1_S_Zt4_S___PNg___XnSP__cimm__MUL_VL_, + }, + }, + // ZSTR + { + // ZSTR , [{, #, MUL VL}] + { + goOp: AZSTR, + fixedBits: 0xe5804000, + args: Zt___XnSP__cimm__MUL_VL_, + }, + }, + // ZSUB + { + // ZSUB ., ., /M, . + { + goOp: AZSUB, + fixedBits: 0x4010000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZSUB ., ., . + { + goOp: AZSUB, + fixedBits: 0x4200400, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZSUB #{, }, ., . + { + goOp: AZSUB, + fixedBits: 0x2521c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, + }, + // ZSUBHNB + { + // ZSUBHNB ., ., . + { + goOp: AZSUBHNB, + fixedBits: 0x45207000, + args: Zm_Tb__Zn_Tb__Zd_T__2, + }, + }, + // ZSUBHNT + { + // ZSUBHNT ., ., . + { + goOp: AZSUBHNT, + fixedBits: 0x45207400, + args: Zm_Tb__Zn_Tb__Zd_T__2, + }, + }, + // ZSUBP + { + // ZSUBP ., ., /M, . + { + goOp: AZSUBP, + fixedBits: 0x4410a000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSUBPT + { + // ZSUBPT .D, .D, /M, .D + { + goOp: AZSUBPT, + fixedBits: 0x4c50000, + args: Zm_D__Zdn_D__PgM__Zdn_D, + }, + // ZSUBPT .D, .D, .D + { + goOp: AZSUBPT, + fixedBits: 0x4e00c00, + args: Zm_D__Zn_D__Zd_D, + }, + }, + // ZSUBR + { + // ZSUBR ., ., /M, . + { + goOp: AZSUBR, + fixedBits: 0x4030000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZSUBR #{, }, ., . + { + goOp: AZSUBR, + fixedBits: 0x2523c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, + }, + // ZSUDOT + { + // ZSUDOT .B[], .B, .S + { + goOp: AZSUDOT, + fixedBits: 0x44a01c00, + args: Zm_B_imm___Zn_B__Zda_S__2, + }, + }, + // ZSUNPKHI + { + // ZSUNPKHI ., . + { + goOp: AZSUNPKHI, + fixedBits: 0x5313800, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZSUNPKLO + { + // ZSUNPKLO ., . + { + goOp: AZSUNPKLO, + fixedBits: 0x5303800, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZSUQADD + { + // ZSUQADD ., ., /M, . + { + goOp: AZSUQADD, + fixedBits: 0x441c8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSXTB + { + // ZSXTB ., /M, . + { + goOp: AZSXTB, + fixedBits: 0x410a000, + args: Zn_T__PgM__Zd_T__4, + }, + // ZSXTB ., /Z, . + { + goOp: AZSXTB, + fixedBits: 0x400a000, + args: Zn_T__PgZ__Zd_T__4, + }, + }, + // ZSXTH + { + // ZSXTH ., /M, . + { + goOp: AZSXTH, + fixedBits: 0x492a000, + args: Zn_T__PgM__Zd_T__5, + }, + // ZSXTH ., /Z, . + { + goOp: AZSXTH, + fixedBits: 0x482a000, + args: Zn_T__PgZ__Zd_T__5, + }, + }, + // ZSXTW + { + // ZSXTW .D, /M, .D + { + goOp: AZSXTW, + fixedBits: 0x4d4a000, + args: Zn_D__PgM__Zd_D, + }, + // ZSXTW .D, /Z, .D + { + goOp: AZSXTW, + fixedBits: 0x4c4a000, + args: Zn_D__PgZ__Zd_D, + }, + }, + // ZTBL + { + // ZTBL ., { ., . }, . + { + goOp: AZTBL, + fixedBits: 0x5202800, + args: Zm_T___Zn1_T__Zn2_T___Zd_T, + }, + // ZTBL ., { . }, . + { + goOp: AZTBL, + fixedBits: 0x5203000, + args: Zm_T___Zn_T___Zd_T, + }, + }, + // ZTBLQ + { + // ZTBLQ ., { . }, . + { + goOp: AZTBLQ, + fixedBits: 0x4400f800, + args: Zm_T___Zn_T___Zd_T, + }, + }, + // ZTBX + { + // ZTBX ., ., . + { + goOp: AZTBX, + fixedBits: 0x5202c00, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZTBXQ + { + // ZTBXQ ., ., . + { + goOp: AZTBXQ, + fixedBits: 0x5203400, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZTRN1 + { + // ZTRN1 .Q, .Q, .Q + { + goOp: AZTRN1, + fixedBits: 0x5a01800, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZTRN1 ., ., . + { + goOp: AZTRN1, + fixedBits: 0x5207000, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZTRN2 + { + // ZTRN2 .Q, .Q, .Q + { + goOp: AZTRN2, + fixedBits: 0x5a01c00, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZTRN2 ., ., . + { + goOp: AZTRN2, + fixedBits: 0x5207400, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZUABA + { + // ZUABA ., ., . + { + goOp: AZUABA, + fixedBits: 0x4500fc00, + args: Zm_T__Zn_T__Zda_T__2, + }, + }, + // ZUABAL + { + // ZUABAL ., ., . + { + goOp: AZUABAL, + fixedBits: 0x4400dc00, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + }, + // ZUABALB + { + // ZUABALB ., ., . + { + goOp: AZUABALB, + fixedBits: 0x4500c800, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + }, + // ZUABALT + { + // ZUABALT ., ., . + { + goOp: AZUABALT, + fixedBits: 0x4500cc00, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + }, + // ZUABD + { + // ZUABD ., ., /M, . + { + goOp: AZUABD, + fixedBits: 0x40d0000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUABDLB + { + // ZUABDLB ., ., . + { + goOp: AZUABDLB, + fixedBits: 0x45003800, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZUABDLT + { + // ZUABDLT ., ., . + { + goOp: AZUABDLT, + fixedBits: 0x45003c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZUADALP + { + // ZUADALP ., /M, . + { + goOp: AZUADALP, + fixedBits: 0x4405a000, + args: Zn_Tb__PgM__Zda_T, + }, + }, + // ZUADDLB + { + // ZUADDLB ., ., . + { + goOp: AZUADDLB, + fixedBits: 0x45000800, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZUADDLT + { + // ZUADDLT ., ., . + { + goOp: AZUADDLT, + fixedBits: 0x45000c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZUADDVD + { + // ZUADDVD ., ,
    + { + goOp: AZUADDVD, + fixedBits: 0x4012000, + args: Zn_T__Pg__Dd__2, + }, + }, + // ZUADDWB + { + // ZUADDWB ., ., . + { + goOp: AZUADDWB, + fixedBits: 0x45004800, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZUADDWT + { + // ZUADDWT ., ., . + { + goOp: AZUADDWT, + fixedBits: 0x45004c00, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZUCLAMP + { + // ZUCLAMP ., ., . + { + goOp: AZUCLAMP, + fixedBits: 0x4400c400, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZUCVTF + { + // ZUCVTF .D, /M, .D + { + goOp: AZUCVTF, + fixedBits: 0x65d7a000, + args: Zn_D__PgM__Zd_D, + }, + // ZUCVTF .D, /M, .H + { + goOp: AZUCVTF, + fixedBits: 0x6557a000, + args: Zn_D__PgM__Zd_H, + }, + // ZUCVTF .D, /M, .S + { + goOp: AZUCVTF, + fixedBits: 0x65d5a000, + args: Zn_D__PgM__Zd_S, + }, + // ZUCVTF .D, /Z, .D + { + goOp: AZUCVTF, + fixedBits: 0x64dde000, + args: Zn_D__PgZ__Zd_D, + }, + // ZUCVTF .D, /Z, .H + { + goOp: AZUCVTF, + fixedBits: 0x645de000, + args: Zn_D__PgZ__Zd_H, + }, + // ZUCVTF .D, /Z, .S + { + goOp: AZUCVTF, + fixedBits: 0x64dda000, + args: Zn_D__PgZ__Zd_S, + }, + // ZUCVTF .H, /M, .H + { + goOp: AZUCVTF, + fixedBits: 0x6553a000, + args: Zn_H__PgM__Zd_H, + }, + // ZUCVTF .H, /Z, .H + { + goOp: AZUCVTF, + fixedBits: 0x645ce000, + args: Zn_H__PgZ__Zd_H, + }, + // ZUCVTF .S, /M, .D + { + goOp: AZUCVTF, + fixedBits: 0x65d1a000, + args: Zn_S__PgM__Zd_D, + }, + // ZUCVTF .S, /M, .H + { + goOp: AZUCVTF, + fixedBits: 0x6555a000, + args: Zn_S__PgM__Zd_H, + }, + // ZUCVTF .S, /M, .S + { + goOp: AZUCVTF, + fixedBits: 0x6595a000, + args: Zn_S__PgM__Zd_S, + }, + // ZUCVTF .S, /Z, .D + { + goOp: AZUCVTF, + fixedBits: 0x64dca000, + args: Zn_S__PgZ__Zd_D, + }, + // ZUCVTF .S, /Z, .H + { + goOp: AZUCVTF, + fixedBits: 0x645da000, + args: Zn_S__PgZ__Zd_H, + }, + // ZUCVTF .S, /Z, .S + { + goOp: AZUCVTF, + fixedBits: 0x649da000, + args: Zn_S__PgZ__Zd_S, + }, + // ZUCVTF ., . + { + goOp: AZUCVTF, + fixedBits: 0x650c3400, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZUCVTFLT + { + // ZUCVTFLT ., . + { + goOp: AZUCVTFLT, + fixedBits: 0x650c3c00, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZUDIV + { + // ZUDIV ., ., /M, . + { + goOp: AZUDIV, + fixedBits: 0x4950000, + args: Zm_T__Zdn_T__PgM__Zdn_T__4, + }, + }, + // ZUDIVR + { + // ZUDIVR ., ., /M, . + { + goOp: AZUDIVR, + fixedBits: 0x4970000, + args: Zm_T__Zdn_T__PgM__Zdn_T__4, + }, + }, + // ZUDOT + { + // ZUDOT .B, .B, .H + { + goOp: AZUDOT, + fixedBits: 0x44400400, + args: Zm_B__Zn_B__Zda_H, + }, + // ZUDOT .H, .H, .S + { + goOp: AZUDOT, + fixedBits: 0x4400cc00, + args: Zm_H__Zn_H__Zda_S, + }, + // ZUDOT ., ., . + { + goOp: AZUDOT, + fixedBits: 0x44800400, + args: Zm_Tb__Zn_Tb__Zda_T__2, + }, + // ZUDOT .B[], .B, .H + { + goOp: AZUDOT, + fixedBits: 0x44200400, + args: Zm_B_imm___Zn_B__Zda_H__2, + }, + // ZUDOT .B[], .B, .S + { + goOp: AZUDOT, + fixedBits: 0x44a00400, + args: Zm_B_imm___Zn_B__Zda_S__3, + }, + // ZUDOT .H[], .H, .D + { + goOp: AZUDOT, + fixedBits: 0x44e00400, + args: Zm_H_imm___Zn_H__Zda_D, + }, + // ZUDOT .H[], .H, .S + { + goOp: AZUDOT, + fixedBits: 0x4480cc00, + args: Zm_H_imm___Zn_H__Zda_S__4, + }, + }, + // ZUHADD + { + // ZUHADD ., ., /M, . + { + goOp: AZUHADD, + fixedBits: 0x44118000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUHSUB + { + // ZUHSUB ., ., /M, . + { + goOp: AZUHSUB, + fixedBits: 0x44138000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUHSUBR + { + // ZUHSUBR ., ., /M, . + { + goOp: AZUHSUBR, + fixedBits: 0x44178000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUMAX + { + // ZUMAX ., ., /M, . + { + goOp: AZUMAX, + fixedBits: 0x4090000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUMAX #, ., . + { + goOp: AZUMAX, + fixedBits: 0x2529c000, + args: cimm__Zdn_T__Zdn_T__2, + }, + }, + // ZUMAXP + { + // ZUMAXP ., ., /M, . + { + goOp: AZUMAXP, + fixedBits: 0x4415a000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUMAXQV + { + // ZUMAXQV ., , . + { + goOp: AZUMAXQV, + fixedBits: 0x40d2000, + args: Zn_Tb__Pg__Vd_T__1, + }, + }, + // ZUMAXVB + { + // ZUMAXVB ., , + { + goOp: AZUMAXVB, + fixedBits: 0x4092000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMAXVD + { + // ZUMAXVD ., , + { + goOp: AZUMAXVD, + fixedBits: 0x4c92000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMAXVH + { + // ZUMAXVH ., , + { + goOp: AZUMAXVH, + fixedBits: 0x4492000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMAXVS + { + // ZUMAXVS ., , + { + goOp: AZUMAXVS, + fixedBits: 0x4892000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMIN + { + // ZUMIN ., ., /M, . + { + goOp: AZUMIN, + fixedBits: 0x40b0000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUMIN #, ., . + { + goOp: AZUMIN, + fixedBits: 0x252bc000, + args: cimm__Zdn_T__Zdn_T__2, + }, + }, + // ZUMINP + { + // ZUMINP ., ., /M, . + { + goOp: AZUMINP, + fixedBits: 0x4417a000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUMINQV + { + // ZUMINQV ., , . + { + goOp: AZUMINQV, + fixedBits: 0x40f2000, + args: Zn_Tb__Pg__Vd_T__1, + }, + }, + // ZUMINVB + { + // ZUMINVB ., , + { + goOp: AZUMINVB, + fixedBits: 0x40b2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMINVD + { + // ZUMINVD ., , + { + goOp: AZUMINVD, + fixedBits: 0x4cb2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMINVH + { + // ZUMINVH ., , + { + goOp: AZUMINVH, + fixedBits: 0x44b2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMINVS + { + // ZUMINVS ., , + { + goOp: AZUMINVS, + fixedBits: 0x48b2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMLALB + { + // ZUMLALB ., ., . + { + goOp: AZUMLALB, + fixedBits: 0x44004800, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZUMLALB .H[], .H, .S + { + goOp: AZUMLALB, + fixedBits: 0x44a09000, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZUMLALB .S[], .S, .D + { + goOp: AZUMLALB, + fixedBits: 0x44e09000, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZUMLALT + { + // ZUMLALT ., ., . + { + goOp: AZUMLALT, + fixedBits: 0x44004c00, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZUMLALT .H[], .H, .S + { + goOp: AZUMLALT, + fixedBits: 0x44a09400, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZUMLALT .S[], .S, .D + { + goOp: AZUMLALT, + fixedBits: 0x44e09400, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZUMLSLB + { + // ZUMLSLB ., ., . + { + goOp: AZUMLSLB, + fixedBits: 0x44005800, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZUMLSLB .H[], .H, .S + { + goOp: AZUMLSLB, + fixedBits: 0x44a0b000, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZUMLSLB .S[], .S, .D + { + goOp: AZUMLSLB, + fixedBits: 0x44e0b000, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZUMLSLT + { + // ZUMLSLT ., ., . + { + goOp: AZUMLSLT, + fixedBits: 0x44005c00, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZUMLSLT .H[], .H, .S + { + goOp: AZUMLSLT, + fixedBits: 0x44a0b400, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZUMLSLT .S[], .S, .D + { + goOp: AZUMLSLT, + fixedBits: 0x44e0b400, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZUMMLA + { + // ZUMMLA .B, .B, .S + { + goOp: AZUMMLA, + fixedBits: 0x45c09800, + args: Zm_B__Zn_B__Zda_S, + }, + }, + // ZUMULH + { + // ZUMULH ., ., /M, . + { + goOp: AZUMULH, + fixedBits: 0x4130000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUMULH ., ., . + { + goOp: AZUMULH, + fixedBits: 0x4206c00, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZUMULLB + { + // ZUMULLB ., ., . + { + goOp: AZUMULLB, + fixedBits: 0x45007800, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + // ZUMULLB .H[], .H, .S + { + goOp: AZUMULLB, + fixedBits: 0x44a0d000, + args: Zm_H_imm___Zn_H__Zd_S, + }, + // ZUMULLB .S[], .S, .D + { + goOp: AZUMULLB, + fixedBits: 0x44e0d000, + args: Zm_S_imm___Zn_S__Zd_D, + }, + }, + // ZUMULLT + { + // ZUMULLT ., ., . + { + goOp: AZUMULLT, + fixedBits: 0x45007c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + // ZUMULLT .H[], .H, .S + { + goOp: AZUMULLT, + fixedBits: 0x44a0d400, + args: Zm_H_imm___Zn_H__Zd_S, + }, + // ZUMULLT .S[], .S, .D + { + goOp: AZUMULLT, + fixedBits: 0x44e0d400, + args: Zm_S_imm___Zn_S__Zd_D, + }, + }, + // ZUQADD + { + // ZUQADD ., ., /M, . + { + goOp: AZUQADD, + fixedBits: 0x44198000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUQADD ., ., . + { + goOp: AZUQADD, + fixedBits: 0x4201400, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZUQADD #{, }, ., . + { + goOp: AZUQADD, + fixedBits: 0x2525c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, + }, + // ZUQCVTN + { + // ZUQCVTN { .S-.S }, .H + { + goOp: AZUQCVTN, + fixedBits: 0x45314800, + args: Zn1_S_Zn2_S___Zd_H, + }, + }, + // ZUQDECP + { + // ZUQDECP ., . + { + goOp: AZUQDECP, + fixedBits: 0x252b8000, + args: Pm_T__Zdn_T, + }, + }, + // ZUQINCP + { + // ZUQINCP ., . + { + goOp: AZUQINCP, + fixedBits: 0x25298000, + args: Pm_T__Zdn_T, + }, + }, + // ZUQRSHL + { + // ZUQRSHL ., ., /M, . + { + goOp: AZUQRSHL, + fixedBits: 0x440b8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUQRSHLR + { + // ZUQRSHLR ., ., /M, . + { + goOp: AZUQRSHLR, + fixedBits: 0x440f8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUQRSHRN + { + // ZUQRSHRN #, { .H-.H }, .B + { + goOp: AZUQRSHRN, + fixedBits: 0x45a83800, + args: cconst___Zn1_H_Zn2_H___Zd_B, + }, + // ZUQRSHRN #, { .S-.S }, .H + { + goOp: AZUQRSHRN, + fixedBits: 0x45b03800, + args: cconst___Zn1_S_Zn2_S___Zd_H, + }, + }, + // ZUQRSHRNB + { + // ZUQRSHRNB #, ., . + { + goOp: AZUQRSHRNB, + fixedBits: 0x45203800, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZUQRSHRNT + { + // ZUQRSHRNT #, ., . + { + goOp: AZUQRSHRNT, + fixedBits: 0x45203c00, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZUQSHL + { + // ZUQSHL ., ., /M, . + { + goOp: AZUQSHL, + fixedBits: 0x44098000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUQSHL #, ., /M, . + { + goOp: AZUQSHL, + fixedBits: 0x4078000, + args: cconst__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZUQSHLR + { + // ZUQSHLR ., ., /M, . + { + goOp: AZUQSHLR, + fixedBits: 0x440d8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUQSHRN + { + // ZUQSHRN #, { .-. }, . + { + goOp: AZUQSHRN, + fixedBits: 0x45a01000, + args: cconst___Zn1_Tb_Zn2_Tb___Zd_T, + }, + }, + // ZUQSHRNB + { + // ZUQSHRNB #, ., . + { + goOp: AZUQSHRNB, + fixedBits: 0x45203000, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZUQSHRNT + { + // ZUQSHRNT #, ., . + { + goOp: AZUQSHRNT, + fixedBits: 0x45203400, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZUQSUB + { + // ZUQSUB ., ., /M, . + { + goOp: AZUQSUB, + fixedBits: 0x441b8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUQSUB ., ., . + { + goOp: AZUQSUB, + fixedBits: 0x4201c00, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZUQSUB #{, }, ., . + { + goOp: AZUQSUB, + fixedBits: 0x2527c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, + }, + // ZUQSUBR + { + // ZUQSUBR ., ., /M, . + { + goOp: AZUQSUBR, + fixedBits: 0x441f8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUQXTNB + { + // ZUQXTNB ., . + { + goOp: AZUQXTNB, + fixedBits: 0x45204800, + args: Zn_Tb__Zd_T__2, + }, + }, + // ZUQXTNT + { + // ZUQXTNT ., . + { + goOp: AZUQXTNT, + fixedBits: 0x45204c00, + args: Zn_Tb__Zd_T__2, + }, + }, + // ZURECPE + { + // ZURECPE .S, /M, .S + { + goOp: AZURECPE, + fixedBits: 0x4480a000, + args: Zn_S__PgM__Zd_S, + }, + // ZURECPE .S, /Z, .S + { + goOp: AZURECPE, + fixedBits: 0x4482a000, + args: Zn_S__PgZ__Zd_S, + }, + }, + // ZURHADD + { + // ZURHADD ., ., /M, . + { + goOp: AZURHADD, + fixedBits: 0x44158000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZURSHL + { + // ZURSHL ., ., /M, . + { + goOp: AZURSHL, + fixedBits: 0x44038000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZURSHLR + { + // ZURSHLR ., ., /M, . + { + goOp: AZURSHLR, + fixedBits: 0x44078000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZURSHR + { + // ZURSHR #, ., /M, . + { + goOp: AZURSHR, + fixedBits: 0x40d8000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZURSQRTE + { + // ZURSQRTE .S, /M, .S + { + goOp: AZURSQRTE, + fixedBits: 0x4481a000, + args: Zn_S__PgM__Zd_S, + }, + // ZURSQRTE .S, /Z, .S + { + goOp: AZURSQRTE, + fixedBits: 0x4483a000, + args: Zn_S__PgZ__Zd_S, + }, + }, + // ZURSRA + { + // ZURSRA #, ., . + { + goOp: AZURSRA, + fixedBits: 0x4500ec00, + args: cconst__Zn_T__Zda_T, + }, + }, + // ZUSDOT + { + // ZUSDOT .B, .B, .S + { + goOp: AZUSDOT, + fixedBits: 0x44807800, + args: Zm_B__Zn_B__Zda_S, + }, + // ZUSDOT .B[], .B, .S + { + goOp: AZUSDOT, + fixedBits: 0x44a01800, + args: Zm_B_imm___Zn_B__Zda_S__2, + }, + }, + // ZUSHLLB + { + // ZUSHLLB #, ., . + { + goOp: AZUSHLLB, + fixedBits: 0x4500a800, + args: cconst__Zn_Tb__Zd_T__2, + }, + }, + // ZUSHLLT + { + // ZUSHLLT #, ., . + { + goOp: AZUSHLLT, + fixedBits: 0x4500ac00, + args: cconst__Zn_Tb__Zd_T__2, + }, + }, + // ZUSMMLA + { + // ZUSMMLA .B, .B, .S + { + goOp: AZUSMMLA, + fixedBits: 0x45809800, + args: Zm_B__Zn_B__Zda_S, + }, + }, + // ZUSQADD + { + // ZUSQADD ., ., /M, . + { + goOp: AZUSQADD, + fixedBits: 0x441d8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUSRA + { + // ZUSRA #, ., . + { + goOp: AZUSRA, + fixedBits: 0x4500e400, + args: cconst__Zn_T__Zda_T, + }, + }, + // ZUSUBLB + { + // ZUSUBLB ., ., . + { + goOp: AZUSUBLB, + fixedBits: 0x45001800, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZUSUBLT + { + // ZUSUBLT ., ., . + { + goOp: AZUSUBLT, + fixedBits: 0x45001c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZUSUBWB + { + // ZUSUBWB ., ., . + { + goOp: AZUSUBWB, + fixedBits: 0x45005800, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZUSUBWT + { + // ZUSUBWT ., ., . + { + goOp: AZUSUBWT, + fixedBits: 0x45005c00, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZUUNPKHI + { + // ZUUNPKHI ., . + { + goOp: AZUUNPKHI, + fixedBits: 0x5333800, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZUUNPKLO + { + // ZUUNPKLO ., . + { + goOp: AZUUNPKLO, + fixedBits: 0x5323800, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZUXTB + { + // ZUXTB ., /M, . + { + goOp: AZUXTB, + fixedBits: 0x411a000, + args: Zn_T__PgM__Zd_T__4, + }, + // ZUXTB ., /Z, . + { + goOp: AZUXTB, + fixedBits: 0x401a000, + args: Zn_T__PgZ__Zd_T__4, + }, + }, + // ZUXTH + { + // ZUXTH ., /M, . + { + goOp: AZUXTH, + fixedBits: 0x493a000, + args: Zn_T__PgM__Zd_T__5, + }, + // ZUXTH ., /Z, . + { + goOp: AZUXTH, + fixedBits: 0x483a000, + args: Zn_T__PgZ__Zd_T__5, + }, + }, + // ZUXTW + { + // ZUXTW .D, /M, .D + { + goOp: AZUXTW, + fixedBits: 0x4d5a000, + args: Zn_D__PgM__Zd_D, + }, + // ZUXTW .D, /Z, .D + { + goOp: AZUXTW, + fixedBits: 0x4c5a000, + args: Zn_D__PgZ__Zd_D, + }, + }, + // ZUZP1 + { + // ZUZP1 .Q, .Q, .Q + { + goOp: AZUZP1, + fixedBits: 0x5a00800, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZUZP1 ., ., . + { + goOp: AZUZP1, + fixedBits: 0x5206800, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZUZP2 + { + // ZUZP2 .Q, .Q, .Q + { + goOp: AZUZP2, + fixedBits: 0x5a00c00, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZUZP2 ., ., . + { + goOp: AZUZP2, + fixedBits: 0x5206c00, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZUZPQ1 + { + // ZUZPQ1 ., ., . + { + goOp: AZUZPQ1, + fixedBits: 0x4400e800, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZUZPQ2 + { + // ZUZPQ2 ., ., . + { + goOp: AZUZPQ2, + fixedBits: 0x4400ec00, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZXAR + { + // ZXAR #, ., ., . + { + goOp: AZXAR, + fixedBits: 0x4203400, + args: cconst__Zm_T__Zdn_T__Zdn_T, + }, + }, + // ZZIP1 + { + // ZZIP1 .Q, .Q, .Q + { + goOp: AZZIP1, + fixedBits: 0x5a00000, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZZIP1 ., ., . + { + goOp: AZZIP1, + fixedBits: 0x5206000, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZZIP2 + { + // ZZIP2 .Q, .Q, .Q + { + goOp: AZZIP2, + fixedBits: 0x5a00400, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZZIP2 ., ., . + { + goOp: AZZIP2, + fixedBits: 0x5206400, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZZIPQ1 + { + // ZZIPQ1 ., ., . + { + goOp: AZZIPQ1, + fixedBits: 0x4400e000, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZZIPQ2 + { + // ZZIPQ2 ., ., . + { + goOp: AZZIPQ2, + fixedBits: 0x4400e400, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, +} + +var a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_16Bit32Bit, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI3hI3l_1923_16Bit, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_16Bit32Bit, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI2_1921_32Bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_32Bit, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI3hI3l_1119_32Bit, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_8To32Bit, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + {encodeI2_1921_8To32Bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_HalfSinglePrecision, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI3hI3l_1923_HalfPrecision, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_HalfSinglePrecision, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI2_1921_SinglePrecision, enc_i2}, + }, +} + +var a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1620_16To64Bit, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI1_2021_16To64Bit, enc_i1}, + }, +} + +var a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1620_64Bit, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeI1_2021_64Bit, enc_i1}, + }, +} + +var a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1620_64Bit, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI2hI2l_1120_64Bit, enc_i2h_i2l}, + }, +} + +var a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1620_DoublePrecision, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeI1_2021_DoublePrecision, enc_i1}, + }, +} + +var a_ARNGIDX_Zm510V1_ArngQCheck_I21921 = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeArngQCheck, enc_NIL}, + {encodeI21921, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Half_ArngHCheck_I2_1921_Half = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Half, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI2_1921_Half, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V1_ArngHCheck_I2_1921_16bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V1, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI2_1921_16bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I2_1921_8BitGroup = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + {encodeI2_1921_8BitGroup, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1119_Pair8Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + {encodeI3hI3l_1119_Pair8Bit, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1923_8To16Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + {encodeI3hI3l_1923_8To16Bit, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019 = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + {encodeI4hI4l_1019, enc_i4h_i4l}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_16To32Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI2_1921_16To32Bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_Pair16Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI2_1921_Pair16Bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1119 = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI3hI3l_1119, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922 = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI3hI3l_1922, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm_1620_Range0_15_ArngSCheck_I1_2021_32bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1620_Range0_15, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI1_2021_32bit, enc_i1}, + }, +} + +var a_ARNGIDX_Zm_1620_Single_ArngSCheck_I1_2021_Single = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1620_Single, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI1_2021_Single, enc_i1}, + }, +} + +var a_ARNGIDX_Zn510Src_Tsz_1620_SizeSpecifier4_I1Tsz_Delegate = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeTsz_1620_SizeSpecifier4, enc_tsz}, + {encodeI1Tsz_Delegate, enc_i1_tsz}, + }, +} + +var a_ARNGIDX_Zn510Src_Tsz_1621_SizeSpecifier5_Imm2Tsz_Delegate = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeTsz_1621_SizeSpecifier5, enc_tsz}, + {encodeImm2Tsz_Delegate, enc_imm2_tsz}, + }, +} + +var a_ARNG_PNd_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePNd, enc_PNd}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_PNn59_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePNn59, enc_PNn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Pd_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Pd_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Pd_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Pd_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Pd_Size0BH2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeSize0BH2223, enc_size0}, + }, +} + +var a_ARNG_Pd_SizeBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeSizeBHS2224, enc_size}, + }, +} + +var a_ARNG_Pd_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Pd_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_PdmDest_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePdmDest, enc_Pdm}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_PdnDest_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePdnDest, enc_Pdn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_PdnSrcDst_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePdnSrcDst, enc_Pdn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Pm1620_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePm1620, enc_Pm}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Pm1620_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePm1620, enc_Pm}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Pm59V1_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePm59V1, enc_Pm}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Pm59V1_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePm59V1, enc_Pm}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Pn59V2_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59V2, enc_Pn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Pn59V2_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59V2, enc_Pn}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Pn59V2_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59V2, enc_Pn}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Pn59V2_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59V2, enc_Pn}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Pn59V2_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59V2, enc_Pn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Pn59_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59, enc_Pn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Pn59_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59, enc_Pn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Vd_Size16B8H4S2D = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeVd, enc_Vd}, + {encodeSize16B8H4S2D, enc_size}, + }, +} + +var a_ARNG_Vd_Size8H4S2D = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeVd, enc_Vd}, + {encodeSize8H4S2D, enc_size}, + }, +} + +var a_ARNG_Za16213Rd_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZa16213Rd, enc_Za}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Za5103Rd_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZa5103Rd, enc_Za}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Za5103Rd_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZa5103Rd, enc_Za}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zd_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Zd_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zd_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Zd_ArngQCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_ARNG_Zd_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Zd_Size0HalfwordMergeZero = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSize0HalfwordMergeZero, enc_size0}, + }, +} + +var a_ARNG_Zd_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSize0SD2223, enc_size0}, + }, +} + +var a_ARNG_Zd_SizeBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBHS2224, enc_size}, + }, +} + +var a_ARNG_Zd_SizeBHS2224Offset1 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBHS2224Offset1, enc_size}, + }, +} + +var a_ARNG_Zd_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zd_SizeBhsTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBhsTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zd_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zd_SizeByteMergeZero = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeByteMergeZero, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHD2224, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHSD1315 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHSD1315, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHSD1719 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHSD1719, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHSD2224No00, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zd_SizeImm13NoOp = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeImm13NoOp, enc_imm13}, + }, +} + +var a_ARNG_Zd_SzByteHalfword = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSzByteHalfword, enc_sz}, + }, +} + +var a_ARNG_Zd_SzSD1415 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSzSD1415, enc_sz}, + }, +} + +var a_ARNG_Zd_SzSD1718 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSzSD1718, enc_sz}, + }, +} + +var a_ARNG_Zd_SzSD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSzSD2223, enc_sz}, + }, +} + +var a_ARNG_Zd_SzWordDoubleword = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSzWordDoubleword, enc_sz}, + }, +} + +var a_ARNG_Zd_Tsize1921V1 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeTsize1921V1, enc_tsize}, + }, +} + +var a_ARNG_Zd_Tsz_1620_SizeSpecifier4 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeTsz_1620_SizeSpecifier4, enc_tsz}, + }, +} + +var a_ARNG_Zd_Tsz_1621_SizeSpecifier5 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeTsz_1621_SizeSpecifier5, enc_tsz}, + }, +} + +var a_ARNG_Zd_TszhTszlBHS = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeTszhTszlBHS, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zda3RdSrcDst_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zda3RdSrcDst_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Zda3RdSrcDst_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Zda3RdSrcDst_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSize0SD2223, enc_size0}, + }, +} + +var a_ARNG_Zda3RdSrcDst_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zda3RdSrcDst_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zda3RdSrcDst_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Zda3RdSrcDst_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSizeHSD2224No00, enc_size}, + }, +} + +var a_ARNG_Zda3RdSrcDst_SzSD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSzSD2223, enc_sz}, + }, +} + +var a_ARNG_ZdaDest_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdaDest, enc_Zda}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_ZdnDest_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_ZdnDest_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_ZdnDest_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_ZdnDest_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_ZdnDest_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSize0SD2223, enc_size0}, + }, +} + +var a_ARNG_ZdnDest_SizeBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeBHS2224, enc_size}, + }, +} + +var a_ARNG_ZdnDest_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_ZdnDest_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_ZdnDest_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_ZdnDest_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeHSD2224No00, enc_size}, + }, +} + +var a_ARNG_ZdnSrcDst_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_ZdnSrcDst_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_ZdnSrcDst_SizeBhsdTsz810 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeSizeBhsdTsz810, enc_tszh_tszl}, + }, +} + +var a_ARNG_ZdnSrcDst_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_ZdnSrcDst_SizeImm13NoOp = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeSizeImm13NoOp, enc_imm13}, + }, +} + +var a_ARNG_Zk5103Rd_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZk5103Rd, enc_Zk}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_ArngQCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_Size0BH2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSize0BH2223, enc_size0}, + }, +} + +var a_ARNG_Zm1621V2_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSize0SD2223, enc_size0}, + }, +} + +var a_ARNG_Zm1621V2_Size0TbBH2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSize0TbBH2223, enc_size0}, + }, +} + +var a_ARNG_Zm1621V2_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeHSD2224No00, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SizeTbBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeTbBHS2224, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SizeTbBS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeTbBS2224, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SizeTbHSD2224Offset1 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeTbHSD2224Offset1, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SzSD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSzSD2223, enc_sz}, + }, +} + +var a_ARNG_Zm510V1_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm510V1_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm510V1_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm510V1_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm510V1_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSize0SD2223, enc_size0}, + }, +} + +var a_ARNG_Zm510V1_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zm510V1_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zm510V1_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Zm510V1_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSizeHSD2224No00, enc_size}, + }, +} + +var a_ARNG_Zm510V2_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V2, enc_Zm}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zm510V2_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V2, enc_Zm}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Zn510Src_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510Src_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510Src_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510Src_ArngQCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510Src_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510Src_Size0HalfwordMergeZero = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSize0HalfwordMergeZero, enc_size0}, + }, +} + +var a_ARNG_Zn510Src_SizeBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeBHS2224, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SizeBhsTsz1921Unique = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeBhsTsz1921Unique, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zn510Src_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zn510Src_SizeByteMergeZero = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeByteMergeZero, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SizeHSD1315 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeHSD1315, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SizeHSD1719 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeHSD1719, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SizeHsdTsz1921Unique = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeHsdTsz1921Unique, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zn510Src_SizeTbBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeTbBHS2224, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SizeTbBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeTbBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SizeTbHSD2224Offset1 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeTbHSD2224Offset1, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SzByteHalfword = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSzByteHalfword, enc_sz}, + }, +} + +var a_ARNG_Zn510Src_SzSD1415 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSzSD1415, enc_sz}, + }, +} + +var a_ARNG_Zn510Src_SzSD1718 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSzSD1718, enc_sz}, + }, +} + +var a_ARNG_Zn510Src_SzWordDoubleword = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSzWordDoubleword, enc_sz}, + }, +} + +var a_ARNG_Zn510Src_TszhTszlTbHSD = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeTszhTszlTbHSD, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zn510V1_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510V1_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510V1_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510V1_ArngQCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510V1_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510V1_Size0BH2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSize0BH2223, enc_size0}, + }, +} + +var a_ARNG_Zn510V1_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSize0SD2223, enc_size0}, + }, +} + +var a_ARNG_Zn510V1_Size0TbBH2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSize0TbBH2223, enc_size0}, + }, +} + +var a_ARNG_Zn510V1_SizeBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSizeBHS2224, enc_size}, + }, +} + +var a_ARNG_Zn510V1_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zn510V1_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zn510V1_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Zn510V1_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSizeHSD2224No00, enc_size}, + }, +} + +var a_ARNG_Zn510V1_SizeTbBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSizeTbBHS2224, enc_size}, + }, +} + +var a_ARNG_Zn510V1_SizeTbBS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSizeTbBS2224, enc_size}, + }, +} + +var a_ARNG_Zn510V1_SizeTbHSD2224Offset1 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSizeTbHSD2224Offset1, enc_size}, + }, +} + +var a_ARNG_Zn510V1_SzSD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSzSD2223, enc_sz}, + }, +} + +var a_IMM_Fimm0_0_1_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_0_1_0_56, enc_i1}, + }, +} + +var a_IMM_Fimm0_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_0_56, enc_NIL}, + }, +} + +var a_IMM_Fimm0_5_1_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_5_1_0_56, enc_i1}, + }, +} + +var a_IMM_Fimm0_5_2_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_5_2_0_56, enc_i1}, + }, +} + +var a_IMM_Imm13_518 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm13_518, enc_imm13}, + }, +} + +var a_IMM_Imm31619 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm31619, enc_imm3}, + }, +} + +var a_IMM_Imm3Tsize1621Stub = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm3Tsize1621Stub, enc_tsize_imm3}, + }, +} + +var a_IMM_Imm3Unsigned_1619 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm3Unsigned_1619, enc_imm3}, + }, +} + +var a_IMM_Imm41620V7 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm41620V7, enc_imm4}, + }, +} + +var a_IMM_Imm4Unsigned_1620 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm4Unsigned_1620, enc_imm4}, + }, +} + +var a_IMM_Imm5Signed510Unique = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed510Unique, enc_imm5}, + }, +} + +var a_IMM_Imm5Signed_1621V1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed_1621V1, enc_imm5}, + }, +} + +var a_IMM_Imm5Signed_1621V2 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed_1621V2, enc_imm5}, + }, +} + +var a_IMM_Imm5Signed_510 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed_510, enc_imm5}, + }, +} + +var a_IMM_Imm5bSigned_1621 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5bSigned_1621, enc_imm5b}, + }, +} + +var a_IMM_Imm6Signed_511 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm6Signed_511, enc_imm6}, + }, +} + +var a_IMM_Imm7Unsigned_1421 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm7Unsigned_1421, enc_imm7}, + }, +} + +var a_IMM_Imm8SignedLsl8 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8SignedLsl8, enc_imm8}, + }, +} + +var a_IMM_Imm8Signed_513 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8Signed_513, enc_imm8}, + }, +} + +var a_IMM_Imm8UnsignedLsl8 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8UnsignedLsl8, enc_imm8}, + }, +} + +var a_IMM_Imm8Unsigned_513 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8Unsigned_513, enc_imm8}, + }, +} + +var a_IMM_Imm8_513_Fimm = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8_513_Fimm, enc_imm8}, + }, +} + +var a_IMM_Imm8hImm8l_Unsigned = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8hImm8l_Unsigned, enc_imm8h_imm8l}, + }, +} + +var a_IMM_Rot0_90_180_270_1012 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot0_90_180_270_1012, enc_rot}, + }, +} + +var a_IMM_Rot0_90_180_270_1315 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot0_90_180_270_1315, enc_rot}, + }, +} + +var a_IMM_Rot90_270_1011 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot90_270_1011, enc_rot}, + }, +} + +var a_IMM_Rot90_270_1617 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot90_270_1617, enc_rot}, + }, +} + +var a_IMM_ShiftTsz1619Range0V1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range0V1, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz1619Range0V2 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range0V2, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz1619Range1V1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range1V1, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz1619Range1V2 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range1V2, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz58Range0 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz58Range0, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz58Range1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz58Range1, enc_tszh_tszl_imm3}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621V2, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt1Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621V2, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt2Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621V2, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt3Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621V2, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt4Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621V2, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeNoModCheck, enc_NIL}, + {encodeNoAmtCheck, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt1Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt2Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt3Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeNoModCheck, enc_NIL}, + {encodeNoAmtCheck, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt1Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt2Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt3Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeNoModCheck, enc_NIL}, + {encodeNoAmtCheck, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeModAmt1Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeModAmt2Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeModAmt3Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeNoAmtCheck, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt1Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt2Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt3Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeNoAmtCheck, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeModAmt1Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeModAmt2Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeNoAmtCheck, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt1Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt2Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt3Check, enc_NIL}, + }, +} + +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeNoAmtCheck, enc_NIL}, + }, +} + +var a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeNoModCheck, enc_NIL}, + {encodeNoAmtCheck, enc_NIL}, + }, +} + +var a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModSXTWCheck_Msz1012Amount = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeModSXTWCheck, enc_NIL}, + {encodeMsz1012Amount, enc_msz}, + }, +} + +var a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModUXTWCheck_Msz1012Amount = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeModUXTWCheck, enc_NIL}, + {encodeMsz1012Amount, enc_msz}, + }, +} + +var a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngSCheck, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeNoModCheck, enc_NIL}, + {encodeNoAmtCheck, enc_NIL}, + }, +} + +var a_MEMEXT_Zn510V2_SzSD2223_Zm1621V3_SzSD2223_Msz1012_Msz1012Amount = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeSzSD2223, enc_sz}, + {encodeZm1621V3, enc_Zm}, + {encodeSzSD2223, enc_sz}, + {encodeMsz1012, enc_msz}, + {encodeMsz1012Amount, enc_msz}, + }, +} + +var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3 = operand{ + class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm41620V3, enc_imm4}, + }, +} + +var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4 = operand{ + class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm41620V4, enc_imm4}, + }, +} + +var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5 = operand{ + class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm41620V5, enc_imm4}, + }, +} + +var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6 = operand{ + class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm41620V6, enc_imm4}, + }, +} + +var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8 = operand{ + class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm41620V8, enc_imm4}, + }, +} + +var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9 = operand{ + class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm41620V9, enc_imm4}, + }, +} + +var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm61622V5 = operand{ + class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm61622V5, enc_imm6}, + }, +} + +var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013 = operand{ + class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm9h1622L1013, enc_imm9h_imm9l}, + }, +} + +var a_MEMOFF_Rn510SPV2_Noop_Imm41620V1 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm41620V1, enc_imm4}, + }, +} + +var a_MEMOFF_Rn510SPV2_Noop_Imm41620V2 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm41620V2, enc_imm4}, + }, +} + +var a_MEMOFF_Rn510SPV2_Noop_Imm61622V1 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm61622V1, enc_imm6}, + }, +} + +var a_MEMOFF_Rn510SPV2_Noop_Imm61622V2 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm61622V2, enc_imm6}, + }, +} + +var a_MEMOFF_Rn510SPV2_Noop_Imm61622V3 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm61622V3, enc_imm6}, + }, +} + +var a_MEMOFF_Rn510SPV2_Noop_Imm61622V4 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeImm61622V4, enc_imm6}, + }, +} + +var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + {encodeImm51621V1, enc_imm5}, + }, +} + +var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + {encodeImm51621V2, enc_imm5}, + }, +} + +var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + {encodeImm51621V3, enc_imm5}, + }, +} + +var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + {encodeImm51621V4, enc_imm5}, + }, +} + +var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngSCheck, enc_NIL}, + {encodeImm51621V1, enc_imm5}, + }, +} + +var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngSCheck, enc_NIL}, + {encodeImm51621V2, enc_imm5}, + }, +} + +var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V3 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngSCheck, enc_NIL}, + {encodeImm51621V3, enc_imm5}, + }, +} + +var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4 = operand{ + class: AC_MEMOFF, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngSCheck, enc_NIL}, + {encodeImm51621V4, enc_imm5}, + }, +} + +var a_PREGIDX_PnN_58_Noop_I189 = operand{ + class: AC_PREGIDX, elemEncoders: []elemEncoder{ + {encodePnN_58, enc_PNn}, + {encodeNoop, enc_NIL}, + {encodeI189, enc_i1}, + }, +} + +var a_PREGIDX_PnN_58_Noop_Imm2_810 = operand{ + class: AC_PREGIDX, elemEncoders: []elemEncoder{ + {encodePnN_58, enc_PNn}, + {encodeNoop, enc_NIL}, + {encodeImm2_810, enc_imm2}, + }, +} + +var a_PREGZM_PNg1013_ZeroPredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePNg1013, enc_PNg}, + {encodeZeroPredCheck, enc_NIL}, + }, +} + +var a_PREGZM_Pg1013_MergePredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1013, enc_Pg}, + {encodeMergePredCheck, enc_NIL}, + }, +} + +var a_PREGZM_Pg1013_PredQualM1617 = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1013, enc_Pg}, + {encodePredQualM1617, enc_M}, + }, +} + +var a_PREGZM_Pg1013_ZeroPredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1013, enc_Pg}, + {encodeZeroPredCheck, enc_NIL}, + }, +} + +var a_PREGZM_Pg1014_PredQualM45 = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1014, enc_Pg}, + {encodePredQualM45, enc_M}, + }, +} + +var a_PREGZM_Pg1014_ZeroPredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1014, enc_Pg}, + {encodeZeroPredCheck, enc_NIL}, + }, +} + +var a_PREGZM_Pg1620_MergePredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1620, enc_Pg}, + {encodeMergePredCheck, enc_NIL}, + }, +} + +var a_PREGZM_Pg1620_ZeroPredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1620, enc_Pg}, + {encodeZeroPredCheck, enc_NIL}, + }, +} + +var a_PREGZM_Pg59_ZeroPredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg59, enc_Pg}, + {encodeZeroPredCheck, enc_NIL}, + }, +} + +var a_PREG_PNg1013_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePNg1013, enc_PNg}, + {encodeNoop, enc_NIL}, + }, +} + +var a_PREG_Pg1013_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePg1013, enc_Pg}, + {encodeNoop, enc_NIL}, + }, +} + +var a_PREG_Pg1014_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePg1014, enc_Pg}, + {encodeNoop, enc_NIL}, + }, +} + +var a_PREG_Pg59_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePg59, enc_Pg}, + {encodeNoop, enc_NIL}, + }, +} + +var a_PREG_Pt04V1_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePt04V1, enc_Pt}, + {encodeNoop, enc_NIL}, + }, +} + +var a_PREG_Pt04V2_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePt04V2, enc_Pt}, + {encodeNoop, enc_NIL}, + }, +} + +var a_PREG_Pv1013_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePv1013, enc_Pv}, + {encodeNoop, enc_NIL}, + }, +} + +var a_PREG_Pv1014_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePv1014, enc_Pv}, + {encodeNoop, enc_NIL}, + }, +} + +var a_PREG_Pv59_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePv59, enc_Pv}, + {encodeNoop, enc_NIL}, + }, +} + +var a_REGLIST1_Zn510Table3_ArngBCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZn510Table3, enc_Zn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST1_Zn510Table3_ArngHCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZn510Table3, enc_Zn}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_REGLIST1_Zn510V1_SizeBHSD2224 = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_REGLIST1_Zt05_ArngBCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST1_Zt05_ArngDCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_REGLIST1_Zt05_ArngHCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_REGLIST1_Zt05_ArngQCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_REGLIST1_Zt05_ArngSCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_REGLIST1_Zt05_Size2123V1 = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeSize2123V1, enc_size}, + }, +} + +var a_REGLIST1_Zt05_Size2123V2 = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeSize2123V2, enc_size}, + }, +} + +var a_REGLIST1_Zt05_Sz2122 = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeSz2122, enc_sz}, + }, +} + +var a_REGLIST2_GenZn510V1_SizeBHSD2224_GenZn510V2_SizeBHSD2224 = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeGenZn510V1, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, + {encodeGenZn510V2, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224 = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodePd04, enc_Pd}, + {encodeSizeBHSD2224, enc_size}, + {encodePd04Plus1, enc_Pd}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224 = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodePd14, enc_Pd}, + {encodeSizeBHSD2224, enc_size}, + {encodePd14Plus1, enc_Pd}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_REGLIST2_Zn510MultiSrc1_ArngBCheck_Zn510MultiSrc2_ArngBCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZn510MultiSrc1, enc_Zn}, + {encodeArngBCheck, enc_NIL}, + {encodeZn510MultiSrc2, enc_Zn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224 = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZn510MultiSrc1, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, + {encodeZn510MultiSrc2, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_REGLIST2_Zn510Table1_ArngBCheck_Zn510Table2_ArngBCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZn510Table1, enc_Zn}, + {encodeArngBCheck, enc_NIL}, + {encodeZn510Table2, enc_Zn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZn510Table1, enc_Zn}, + {encodeArngHCheck, enc_NIL}, + {encodeZn510Table2, enc_Zn}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck = operand{ + class: AC_REGLIST3, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck = operand{ + class: AC_REGLIST3, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck = operand{ + class: AC_REGLIST3, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck = operand{ + class: AC_REGLIST3, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck = operand{ + class: AC_REGLIST3, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck = operand{ + class: AC_REGLIST4, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt054, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck = operand{ + class: AC_REGLIST4, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt054, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck = operand{ + class: AC_REGLIST4, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt054, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck = operand{ + class: AC_REGLIST4, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt054, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck = operand{ + class: AC_REGLIST4, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt054, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zd15V1_ArngQCheck_Zd15V2_ArngQCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZd15V1, enc_Zd}, + {encodeArngQCheck, enc_NIL}, + {encodeZd15V2, enc_Zd}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zda15V1_ArngQCheck_Zda15V2_ArngQCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZda15V1, enc_Zda}, + {encodeArngQCheck, enc_NIL}, + {encodeZda15V2, enc_Zda}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zdn15V1_ArngBCheck_Zdn15V2_ArngBCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZdn15V1, enc_Zdn}, + {encodeArngBCheck, enc_NIL}, + {encodeZdn15V2, enc_Zdn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zdn25V1_ArngBCheck_Zdn25V2_ArngBCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZdn25V1, enc_Zdn}, + {encodeArngBCheck, enc_NIL}, + {encodeZdn25V2, enc_Zdn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zn610V1_ArngHCheck_Zn610V2_ArngHCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZn610V1, enc_Zn}, + {encodeArngHCheck, enc_NIL}, + {encodeZn610V2, enc_Zn}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zn610V1_ArngSCheck_Zn610V2_ArngSCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZn610V1, enc_Zn}, + {encodeArngSCheck, enc_NIL}, + {encodeZn610V2, enc_Zn}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zn610V1_SizeTbHSD2224Offset1_Zn610V2_SizeTbHSD2224Offset1 = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZn610V1, enc_Zn}, + {encodeSizeTbHSD2224Offset1, enc_size}, + {encodeZn610V2, enc_Zn}, + {encodeSizeTbHSD2224Offset1, enc_size}, + }, +} + +var a_REGLIST_RANGE_Zn610V1_Tsize1921V2_Zn610V2_Tsize1921V2 = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZn610V1, enc_Zn}, + {encodeTsize1921V2, enc_tsize}, + {encodeZn610V2, enc_Zn}, + {encodeTsize1921V2, enc_tsize}, + }, +} + +var a_REGLIST_RANGE_Zt15V1_ArngBCheck_Zt15V2_ArngBCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZt15V1, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt15V2, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zt15V1_ArngDCheck_Zt15V2_ArngDCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZt15V1, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt15V2, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zt15V1_ArngHCheck_Zt15V2_ArngHCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZt15V1, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt15V2, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zt15V1_ArngSCheck_Zt15V2_ArngSCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZt15V1, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt15V2, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zt25V1_ArngBCheck_Zt25V2_ArngBCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZt25V1, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt25V2, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zt25V1_ArngDCheck_Zt25V2_ArngDCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZt25V1, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt25V2, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zt25V1_ArngHCheck_Zt25V2_ArngHCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZt25V1, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt25V2, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_REGLIST_RANGE_Zt25V1_ArngSCheck_Zt25V2_ArngSCheck = operand{ + class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{ + {encodeZt25V1, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt25V2, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_SPECIAL_Prfop04 = operand{ + class: AC_SPECIAL, elemEncoders: []elemEncoder{ + {encodePrfop04, enc_prfop}, + }, +} + +var a_SPECIAL_Vl1011 = operand{ + class: AC_SPECIAL, elemEncoders: []elemEncoder{ + {encodeVl1011, enc_vl}, + }, +} + +var a_SPECIAL_Vl1314 = operand{ + class: AC_SPECIAL, elemEncoders: []elemEncoder{ + {encodeVl1314, enc_vl}, + }, +} + +var a_SPZGREG_Noop_Rd05 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRd05, enc_Rd}, + }, +} + +var a_SPZGREG_Noop_Rd05ZR = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRd05ZR, enc_Rd}, + }, +} + +var a_SPZGREG_Noop_Rdn05ZR = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRdn05ZR, enc_Rdn}, + }, +} + +var a_SPZGREG_Noop_Rm1621V1 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRm1621V1, enc_Rm}, + }, +} + +var a_SPZGREG_Noop_Rm1621ZR = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRm1621ZR, enc_Rm}, + }, +} + +var a_SPZGREG_Noop_Rm510ZR = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRm510ZR, enc_Rm}, + }, +} + +var a_SPZGREG_Noop_Rn510 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRn510, enc_Rn}, + }, +} + +var a_SPZGREG_Noop_Rn510SPV1 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRn510SPV1, enc_Rn}, + }, +} + +var a_SPZGREG_Noop_Rn510ZR = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRn510ZR, enc_Rn}, + }, +} + +var a_SPZGREG_Noop_Wdn05 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeWdn05, enc_Rdn}, + }, +} + +var a_SPZGREG_Noop_Xdn05 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeXdn05, enc_Rdn}, + }, +} + +var a_SPZGREG_XCheck_Rd05_SPAllowed = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeXCheck, enc_NIL}, + {encodeRd05_SPAllowed, enc_Rd}, + }, +} + +var a_SPZGREG_XCheck_Rn1621_SPAllowed = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeXCheck, enc_NIL}, + {encodeRn1621_SPAllowed, enc_Rn}, + }, +} + +var a_VREG_Noop_Vd05 = operand{ + class: AC_VREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeVd05, enc_Vd}, + }, +} + +var a_VREG_Noop_Vd0564 = operand{ + class: AC_VREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeVd0564, enc_Vd}, + }, +} + +var a_VREG_Noop_Vdn05 = operand{ + class: AC_VREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeVdn05, enc_Vdn}, + }, +} + +var a_VREG_Noop_Vm510 = operand{ + class: AC_VREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeVm510, enc_Vm}, + }, +} + +var a_VREG_Noop_Vn510 = operand{ + class: AC_VREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeVn510, enc_Vn}, + }, +} + +var a_ZREGIDX_Zd_Noop_I1_1718_Halfword = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeNoop, enc_NIL}, + {encodeI1_1718_Halfword, enc_i1}, + }, +} + +var a_ZREGIDX_Zd_Noop_I2_1719_Word = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeNoop, enc_NIL}, + {encodeI2_1719_Word, enc_i2}, + }, +} + +var a_ZREGIDX_Zd_Noop_I3hI3l_1722_Doubleword = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeNoop, enc_NIL}, + {encodeI3hI3l_1722_Doubleword, enc_i3h_i3l}, + }, +} + +var a_ZREGIDX_Zm1621V1_Noop_I12324 = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + {encodeI12324, enc_i1}, + }, +} + +var a_ZREGIDX_Zm1621V1_Noop_I12324B = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + {encodeI12324B, enc_i1}, + }, +} + +var a_ZREGIDX_Zm1621V1_Noop_I22224 = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + {encodeI22224, enc_i2}, + }, +} + +var a_ZREGIDX_Zm1621V1_Noop_I22224HW = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + {encodeI22224HW, enc_i2}, + }, +} + +var a_ZREGIDX_Zm1621V1_Noop_I3224I31213 = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + {encodeI3224I31213, enc_i3h_i3l}, + }, +} + +var a_ZREGIDX_Zn510Src_Noop_I1_1718_Halfword = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeNoop, enc_NIL}, + {encodeI1_1718_Halfword, enc_i1}, + }, +} + +var a_ZREGIDX_Zn510Src_Noop_I2_1719_Word = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeNoop, enc_NIL}, + {encodeI2_1719_Word, enc_i2}, + }, +} + +var a_ZREGIDX_Zn510Src_Noop_I3hI3l_1722_Doubleword = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeNoop, enc_NIL}, + {encodeI3hI3l_1722_Doubleword, enc_i3h_i3l}, + }, +} + +var a_ZREG_Zd_Noop = operand{ + class: AC_ZREG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeNoop, enc_NIL}, + }, +} + +var a_ZREG_Zm1621V1_Noop = operand{ + class: AC_ZREG, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + }, +} + +var a_ZREG_Zn510Src_Noop = operand{ + class: AC_ZREG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeNoop, enc_NIL}, + }, +} + +var a_ZREG_Zt05_Noop = operand{ + class: AC_ZREG, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeNoop, enc_NIL}, + }, +} + +var PNd_T = []operand{ + a_ARNG_PNd_SizeBHSD2224, +} + +var PNn_imm___Pd_T = []operand{ + a_PREGIDX_PnN_58_Noop_Imm2_810, + a_ARNG_Pd_SizeBHSD2224, +} + +var PNn_imm____Pd1_T__Pd2_T_ = []operand{ + a_PREGIDX_PnN_58_Noop_I189, + a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224, +} + +var Pd_B = []operand{ + a_ARNG_Pd_ArngBCheck, +} + +var Pdm_B__Pn_B__PgZ__Pdm_B = []operand{ + a_ARNG_PdmDest_ArngBCheck, + a_ARNG_Pn59_ArngBCheck, + a_PREGZM_Pg1014_ZeroPredCheck, + a_ARNG_PdmDest_ArngBCheck, +} + +var Pdn_B__Pg__Pdn_B = []operand{ + a_ARNG_PdnSrcDst_ArngBCheck, + a_PREG_Pg59_Noop, + a_ARNG_PdnSrcDst_ArngBCheck, +} + +var Pdn_T__Pv__Pdn_T = []operand{ + a_ARNG_PdnDest_SizeBHSD2224, + a_PREG_Pv59_Noop, + a_ARNG_PdnDest_SizeBHSD2224, +} + +var PgZ__Pd_B = []operand{ + a_PREGZM_Pg59_ZeroPredCheck, + a_ARNG_Pd_ArngBCheck, +} + +var Pm_B__Pn_B__PgZ__Pd_B = []operand{ + a_ARNG_Pm1620_ArngBCheck, + a_ARNG_Pn59_ArngBCheck, + a_PREGZM_Pg1014_ZeroPredCheck, + a_ARNG_Pd_ArngBCheck, +} + +var Pm_B__Pn_B__Pg__Pd_B = []operand{ + a_ARNG_Pm1620_ArngBCheck, + a_ARNG_Pn59_ArngBCheck, + a_PREG_Pg1014_Noop, + a_ARNG_Pd_ArngBCheck, +} + +var Pm_T__Pn_T__Pd_T = []operand{ + a_ARNG_Pm1620_SizeBHSD2224, + a_ARNG_Pn59_SizeBHSD2224, + a_ARNG_Pd_SizeBHSD2224, +} + +var Pm_T__Wdn = []operand{ + a_ARNG_Pm59V1_SizeBHSD2224, + a_SPZGREG_Noop_Wdn05, +} + +var Pm_T__Xdn = []operand{ + a_ARNG_Pm59V1_SizeBHSD2224, + a_SPZGREG_Noop_Xdn05, +} + +var Pm_T__Zdn_T = []operand{ + a_ARNG_Pm59V1_SizeHSD2224, + a_ARNG_ZdnSrcDst_SizeHSD2224, +} + +var Pn_B = []operand{ + a_ARNG_Pn59V2_ArngBCheck, +} + +var Pn_B__Pd_H = []operand{ + a_ARNG_Pn59V2_ArngBCheck, + a_ARNG_Pd_ArngHCheck, +} + +var Pn_B__Pg = []operand{ + a_ARNG_Pn59V2_ArngBCheck, + a_PREG_Pg1014_Noop, +} + +var Pn_B__PgZM__Pd_B = []operand{ + a_ARNG_Pn59V2_ArngBCheck, + a_PREGZM_Pg1014_PredQualM45, + a_ARNG_Pd_ArngBCheck, +} + +var Pn_B__PgZ__Pd_B = []operand{ + a_ARNG_Pn59V2_ArngBCheck, + a_PREGZM_Pg1014_ZeroPredCheck, + a_ARNG_Pd_ArngBCheck, +} + +var Pn_B__Zd = []operand{ + a_ARNG_Pn59V2_ArngBCheck, + a_ZREG_Zd_Noop, +} + +var Pn_D__Zd_imm_ = []operand{ + a_ARNG_Pn59V2_ArngDCheck, + a_ZREGIDX_Zd_Noop_I3hI3l_1722_Doubleword, +} + +var Pn_H__Zd_imm_ = []operand{ + a_ARNG_Pn59V2_ArngHCheck, + a_ZREGIDX_Zd_Noop_I1_1718_Halfword, +} + +var Pn_S__Zd_imm_ = []operand{ + a_ARNG_Pn59V2_ArngSCheck, + a_ZREGIDX_Zd_Noop_I2_1719_Word, +} + +var Pn_T__Pd_T = []operand{ + a_ARNG_Pn59V2_SizeBHSD2224, + a_ARNG_Pd_SizeBHSD2224, +} + +var Pn_T__Pg__Xd = []operand{ + a_ARNG_Pn59V2_SizeBHSD2224, + a_PREG_Pg1014_Noop, + a_SPZGREG_Noop_Rd05, +} + +var Pt___XnSP__cimm__MUL_VL_ = []operand{ + a_PREG_Pt04V2_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013, +} + +var Rm__Rn = []operand{ + a_SPZGREG_Noop_Rm1621ZR, + a_SPZGREG_Noop_Rn510ZR, +} + +var Rm__Rn__Pd_T = []operand{ + a_SPZGREG_Noop_Rm1621ZR, + a_SPZGREG_Noop_Rn510ZR, + a_ARNG_Pd_SizeBHSD2224, +} + +var Rm__Rn__Zd_T = []operand{ + a_SPZGREG_Noop_Rm1621ZR, + a_SPZGREG_Noop_Rn510ZR, + a_ARNG_Zd_SizeBHSD2224, +} + +var Rm__Zdn_T = []operand{ + a_SPZGREG_Noop_Rm510ZR, + a_ARNG_ZdnSrcDst_SizeBHSD2224, +} + +var Rm__cimm__Zd_T = []operand{ + a_SPZGREG_Noop_Rm1621ZR, + a_IMM_Imm5Signed510Unique, + a_ARNG_Zd_SizeBHSD2224, +} + +var RnSP__PgM__Zd_T = []operand{ + a_SPZGREG_Noop_Rn510SPV1, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_SizeBHSD2224, +} + +var RnSP__Zd_T = []operand{ + a_SPZGREG_Noop_Rn510SPV1, + a_ARNG_Zd_SizeBHSD2224, +} + +var Vm__Zdn_T = []operand{ + a_VREG_Noop_Vm510, + a_ARNG_ZdnSrcDst_SizeBHSD2224, +} + +var Vn__PgM__Zd_T = []operand{ + a_VREG_Noop_Vn510, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_SizeBHSD2224, +} + +var Wdn__Pm_T__Xdn = []operand{ + a_SPZGREG_Noop_Wdn05, + a_ARNG_Pm59V1_SizeBHSD2224, + a_SPZGREG_Noop_Xdn05, +} + +var Xm__Xn__Pd_T = []operand{ + a_SPZGREG_Noop_Rm1621V1, + a_SPZGREG_Noop_Rn510, + a_ARNG_Pd_SizeBHSD2224, +} + +var Xm__Xn___Pd1_T__Pd2_T_ = []operand{ + a_SPZGREG_Noop_Rm1621V1, + a_SPZGREG_Noop_Rn510, + a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224, +} + +var XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt2_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt15V1_ArngHCheck_Zt15V2_ArngHCheck, +} + +var XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt4_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt25V1_ArngHCheck_Zt25V2_ArngHCheck, +} + +var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck, +} + +var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck, +} + +var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck, +} + +var XnSP__Xm__LSL_c1___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Xm__LSL_c1___PgZ___Zt_D__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Xm__LSL_c1___PgZ___Zt_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, +} + +var XnSP__Xm__LSL_c1___PgZ___Zt_H__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, +} + +var XnSP__Xm__LSL_c1___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Xm__LSL_c1___PgZ___Zt_S__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Xm__LSL_c1___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt2_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt15V1_ArngSCheck_Zt15V2_ArngSCheck, +} + +var XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt4_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt25V1_ArngSCheck_Zt25V2_ArngSCheck, +} + +var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck, +} + +var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck, +} + +var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck, +} + +var XnSP__Xm__LSL_c2___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Xm__LSL_c2___PgZ___Zt_D__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Xm__LSL_c2___PgZ___Zt_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngQCheck, +} + +var XnSP__Xm__LSL_c2___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Xm__LSL_c2___PgZ___Zt_S__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Xm__LSL_c2___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt2_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt15V1_ArngDCheck_Zt15V2_ArngDCheck, +} + +var XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt4_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt25V1_ArngDCheck_Zt25V2_ArngDCheck, +} + +var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck, +} + +var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck, +} + +var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck, +} + +var XnSP__Xm__LSL_c3___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Xm__LSL_c3___PgZ___Zt_D__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Xm__LSL_c3___PgZ___Zt_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngQCheck, +} + +var XnSP__Xm__LSL_c3___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck, +} + +var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck, +} + +var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck, +} + +var XnSP__Xm___PNgZ___Zt1_B_Zt2_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt15V1_ArngBCheck_Zt15V2_ArngBCheck, +} + +var XnSP__Xm___PNgZ___Zt1_B_Zt4_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt25V1_ArngBCheck_Zt25V2_ArngBCheck, +} + +var XnSP__Xm___PgZ___Zt1_B__Zt2_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck, +} + +var XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck, +} + +var XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck, +} + +var XnSP__Xm___PgZ___Zt_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngBCheck, +} + +var XnSP__Xm___PgZ___Zt_B__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngBCheck, +} + +var XnSP__Xm___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Xm___PgZ___Zt_D__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Xm___PgZ___Zt_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, +} + +var XnSP__Xm___PgZ___Zt_H__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, +} + +var XnSP__Xm___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Xm___PgZ___Zt_S__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Xm___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_D__LSL_c1___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Zm_D__LSL_c1___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_D__LSL_c2___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Zm_D__LSL_c2___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_D__LSL_c3___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Zm_D__LSL_c3___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_D___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Zm_D___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_D__mod___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Zm_D__mod___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_D__mod_c1___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Zm_D__mod_c1___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_D__mod_c2___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Zm_D__mod_c2___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_D__mod_c3___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__Zm_D__mod_c3___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_S__mod___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Zm_S__mod___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_S__mod_c1___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Zm_S__mod_c1___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_S__mod_c2___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Zm_S__mod_c2___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__Zm_S__mod_c3___Pg__prfop = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt3Check, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt2_B_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt15V1_ArngBCheck_Zt15V2_ArngBCheck, +} + +var XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt4_B_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt25V1_ArngBCheck_Zt25V2_ArngBCheck, +} + +var XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt2_D_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt15V1_ArngDCheck_Zt15V2_ArngDCheck, +} + +var XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt4_D_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt25V1_ArngDCheck_Zt25V2_ArngDCheck, +} + +var XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt2_H_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt15V1_ArngHCheck_Zt15V2_ArngHCheck, +} + +var XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt4_H_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt25V1_ArngHCheck_Zt25V2_ArngHCheck, +} + +var XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt2_S_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt15V1_ArngSCheck_Zt15V2_ArngSCheck, +} + +var XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt4_S_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8, + a_PREGZM_PNg1013_ZeroPredCheck, + a_REGLIST_RANGE_Zt25V1_ArngSCheck_Zt25V2_ArngSCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt_B_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngBCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt_D_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt_H_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt_Q_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngQCheck, +} + +var XnSP__cimm__MUL_VL___PgZ___Zt_S_ = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__cimm__MUL_VL___Pg__prfop = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm61622V5, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var XnSP__cimm__MUL_VL___Pt = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013, + a_PREG_Pt04V1_Noop, +} + +var XnSP__cimm__MUL_VL___Zt = []operand{ + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013, + a_ZREG_Zt05_Noop, +} + +var XnSP__cimm___PgZ___Zt_B___1 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm61622V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngBCheck, +} + +var XnSP__cimm___PgZ___Zt_B___2 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm41620V2, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngBCheck, +} + +var XnSP__cimm___PgZ___Zt_B___3 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm41620V1, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngBCheck, +} + +var XnSP__cimm___PgZ___Zt_D___1 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm61622V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__cimm___PgZ___Zt_D___2 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm61622V1, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__cimm___PgZ___Zt_D___3 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm61622V2, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__cimm___PgZ___Zt_D___4 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm61622V3, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__cimm___PgZ___Zt_D___5 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm41620V2, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__cimm___PgZ___Zt_D___6 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm41620V1, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var XnSP__cimm___PgZ___Zt_H___1 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm61622V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, +} + +var XnSP__cimm___PgZ___Zt_H___2 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm61622V1, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, +} + +var XnSP__cimm___PgZ___Zt_H___3 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm41620V2, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, +} + +var XnSP__cimm___PgZ___Zt_H___4 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm41620V1, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, +} + +var XnSP__cimm___PgZ___Zt_S___1 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm61622V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__cimm___PgZ___Zt_S___2 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm61622V1, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__cimm___PgZ___Zt_S___3 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm41620V2, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__cimm___PgZ___Zt_S___4 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm41620V1, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__cimm___PgZ___Zt_S___5 = []operand{ + a_MEMOFF_Rn510SPV2_Noop_Imm61622V2, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var Za_D__Zm_D__Zdn_D = []operand{ + a_ARNG_Za5103Rd_ArngDCheck, + a_ARNG_Zm1621V2_ArngDCheck, + a_ARNG_ZdnDest_ArngDCheck, +} + +var Za_T__Zm_T__PgM__Zdn_T__1 = []operand{ + a_ARNG_Za16213Rd_SizeHSD2224, + a_ARNG_Zm510V1_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_SizeHSD2224, +} + +var Za_T__Zm_T__PgM__Zdn_T__2 = []operand{ + a_ARNG_Za5103Rd_SizeBHSD2224, + a_ARNG_Zm1621V2_SizeBHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_SizeBHSD2224, +} + +var Zdn_B__Zdn_B = []operand{ + a_ARNG_ZdnSrcDst_ArngBCheck, + a_ARNG_ZdnSrcDst_ArngBCheck, +} + +var Zk_D__Zm_D__Zdn_D__Zdn_D = []operand{ + a_ARNG_Zk5103Rd_ArngDCheck, + a_ARNG_Zm1621V2_ArngDCheck, + a_ARNG_ZdnDest_ArngDCheck, + a_ARNG_ZdnDest_ArngDCheck, +} + +var Zm_B__Zdn_B__Zdn_B = []operand{ + a_ARNG_Zm510V1_ArngBCheck, + a_ARNG_ZdnDest_ArngBCheck, + a_ARNG_ZdnDest_ArngBCheck, +} + +var Zm_B__Zn_B__Zd_B = []operand{ + a_ARNG_Zm1621V2_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, + a_ARNG_Zd_ArngBCheck, +} + +var Zm_B__Zn_B__Zda_H = []operand{ + a_ARNG_Zm1621V2_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var Zm_B__Zn_B__Zda_S = []operand{ + a_ARNG_Zm1621V2_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_B_imm___Zn_B__Zda_H__1 = []operand{ + a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019, + a_ARNG_Zn510V1_ArngBCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var Zm_B_imm___Zn_B__Zda_H__2 = []operand{ + a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1923_8To16Bit, + a_ARNG_Zn510V1_ArngBCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var Zm_B_imm___Zn_B__Zda_H__3 = []operand{ + a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1119_Pair8Bit, + a_ARNG_Zn510V1_ArngBCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var Zm_B_imm___Zn_B__Zda_S__1 = []operand{ + a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019, + a_ARNG_Zn510V1_ArngBCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_B_imm___Zn_B__Zda_S__2 = []operand{ + a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I2_1921_8BitGroup, + a_ARNG_Zn510V1_ArngBCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_B_imm___Zn_B__Zda_S__3 = []operand{ + a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit, + a_ARNG_Zn510V1_ArngBCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_D__Zdn_D__PgM__Zdn_D = []operand{ + a_ARNG_Zm510V1_ArngDCheck, + a_ARNG_ZdnDest_ArngDCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_ArngDCheck, +} + +var Zm_D__Zdn_T__PgM__Zdn_T = []operand{ + a_ARNG_Zm510V1_ArngDCheck, + a_ARNG_ZdnDest_SizeBHS2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_SizeBHS2224, +} + +var Zm_D__Zn_D__Zd_D = []operand{ + a_ARNG_Zm1621V2_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, + a_ARNG_Zd_ArngDCheck, +} + +var Zm_D__Zn_D__Zd_Q = []operand{ + a_ARNG_Zm1621V2_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, + a_ARNG_Zd_ArngQCheck, +} + +var Zm_D__Zn_D__Zda_D = []operand{ + a_ARNG_Zm1621V2_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, + a_ARNG_Zda3RdSrcDst_ArngDCheck, +} + +var Zm_D__Zn_D___Zd1_Q_Zd2_Q_ = []operand{ + a_ARNG_Zm1621V2_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, + a_REGLIST_RANGE_Zd15V1_ArngQCheck_Zd15V2_ArngQCheck, +} + +var Zm_D__Zn_D___Zda1_Q_Zda2_Q_ = []operand{ + a_ARNG_Zm1621V2_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, + a_REGLIST_RANGE_Zda15V1_ArngQCheck_Zda15V2_ArngQCheck, +} + +var Zm_D__Zn_T__PgZ__Pd_T = []operand{ + a_ARNG_Zm1621V2_ArngDCheck, + a_ARNG_Zn510V1_SizeBHS2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Pd_SizeBHS2224, +} + +var Zm_D__Zn_T__Zd_T = []operand{ + a_ARNG_Zm1621V2_ArngDCheck, + a_ARNG_Zn510V1_SizeBHS2224, + a_ARNG_Zd_SizeBHS2224, +} + +var Zm_D_imm___Zn_D__Zd_D__1 = []operand{ + a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit, + a_ARNG_Zn510V1_ArngDCheck, + a_ARNG_Zd_ArngDCheck, +} + +var Zm_D_imm___Zn_D__Zd_D__2 = []operand{ + a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision, + a_ARNG_Zn510V1_ArngDCheck, + a_ARNG_Zd_ArngDCheck, +} + +var Zm_D_imm___Zn_D__Zda_D__1 = []operand{ + a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit, + a_ARNG_Zn510V1_ArngDCheck, + a_ARNG_Zda3RdSrcDst_ArngDCheck, +} + +var Zm_D_imm___Zn_D__Zda_D__2 = []operand{ + a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision, + a_ARNG_Zn510V1_ArngDCheck, + a_ARNG_Zda3RdSrcDst_ArngDCheck, +} + +var Zm_H__Zdn_H__PgM__Zdn_H = []operand{ + a_ARNG_Zm510V1_ArngHCheck, + a_ARNG_ZdnDest_ArngHCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_ArngHCheck, +} + +var Zm_H__Zn_H__PgM__Zda_H = []operand{ + a_ARNG_Zm1621V2_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var Zm_H__Zn_H__Zd_H = []operand{ + a_ARNG_Zm1621V2_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zm_H__Zn_H__Zda_H = []operand{ + a_ARNG_Zm1621V2_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var Zm_H__Zn_H__Zda_S = []operand{ + a_ARNG_Zm1621V2_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_H_imm___Zn_H__Zd_H__1 = []operand{ + a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zm_H_imm___Zn_H__Zd_H__2 = []operand{ + a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zm_H_imm___Zn_H__Zd_H__3 = []operand{ + a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zm_H_imm___Zn_H__Zd_S = []operand{ + a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zd_ArngSCheck, +} + +var Zm_H_imm___Zn_H__Zda_D = []operand{ + a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngDCheck, +} + +var Zm_H_imm___Zn_H__Zda_H__1 = []operand{ + a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var Zm_H_imm___Zn_H__Zda_H__2 = []operand{ + a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var Zm_H_imm___Zn_H__Zda_H__3 = []operand{ + a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var Zm_H_imm___Zn_H__Zda_S__1 = []operand{ + a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_H_imm___Zn_H__Zda_S__2 = []operand{ + a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1119, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_H_imm___Zn_H__Zda_S__3 = []operand{ + a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_Pair16Bit, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_H_imm___Zn_H__Zda_S__4 = []operand{ + a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_16To32Bit, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_Q__Zn_Q__Zd_Q = []operand{ + a_ARNG_Zm1621V2_ArngQCheck, + a_ARNG_Zn510V1_ArngQCheck, + a_ARNG_Zd_ArngQCheck, +} + +var Zm_Q_index____Zdn1_B_Zdn2_B____Zdn1_B_Zdn2_B_ = []operand{ + a_ARNGIDX_Zm510V1_ArngQCheck_I21921, + a_REGLIST_RANGE_Zdn15V1_ArngBCheck_Zdn15V2_ArngBCheck, + a_REGLIST_RANGE_Zdn15V1_ArngBCheck_Zdn15V2_ArngBCheck, +} + +var Zm_Q_index____Zdn1_B_Zdn4_B____Zdn1_B_Zdn4_B_ = []operand{ + a_ARNGIDX_Zm510V1_ArngQCheck_I21921, + a_REGLIST_RANGE_Zdn25V1_ArngBCheck_Zdn25V2_ArngBCheck, + a_REGLIST_RANGE_Zdn25V1_ArngBCheck_Zdn25V2_ArngBCheck, +} + +var Zm_S__Zdn_S__Zdn_S = []operand{ + a_ARNG_Zm510V1_ArngSCheck, + a_ARNG_ZdnDest_ArngSCheck, + a_ARNG_ZdnDest_ArngSCheck, +} + +var Zm_S__Zn_S__Zd_S = []operand{ + a_ARNG_Zm1621V2_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, + a_ARNG_Zd_ArngSCheck, +} + +var Zm_S__Zn_S__Zda_S = []operand{ + a_ARNG_Zm1621V2_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_S_imm___Zn_S__Zd_D = []operand{ + a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit, + a_ARNG_Zn510V1_ArngSCheck, + a_ARNG_Zd_ArngDCheck, +} + +var Zm_S_imm___Zn_S__Zd_S__1 = []operand{ + a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit, + a_ARNG_Zn510V1_ArngSCheck, + a_ARNG_Zd_ArngSCheck, +} + +var Zm_S_imm___Zn_S__Zd_S__2 = []operand{ + a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision, + a_ARNG_Zn510V1_ArngSCheck, + a_ARNG_Zd_ArngSCheck, +} + +var Zm_S_imm___Zn_S__Zda_D = []operand{ + a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit, + a_ARNG_Zn510V1_ArngSCheck, + a_ARNG_Zda3RdSrcDst_ArngDCheck, +} + +var Zm_S_imm___Zn_S__Zda_S__1 = []operand{ + a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit, + a_ARNG_Zn510V1_ArngSCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_S_imm___Zn_S__Zda_S__2 = []operand{ + a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision, + a_ARNG_Zn510V1_ArngSCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var Zm_T__Rdn__Pg__Rdn = []operand{ + a_ARNG_Zm510V2_SizeBHSD2224, + a_SPZGREG_Noop_Rdn05ZR, + a_PREG_Pg1013_Noop, + a_SPZGREG_Noop_Rdn05ZR, +} + +var Zm_T__Vdn__Pg__Vdn__1 = []operand{ + a_ARNG_Zm510V2_SizeBHSD2224, + a_VREG_Noop_Vdn05, + a_PREG_Pg1013_Noop, + a_VREG_Noop_Vdn05, +} + +var Zm_T__Vdn__Pg__Vdn__2 = []operand{ + a_ARNG_Zm510V2_SizeHSD2224, + a_VREG_Noop_Vdn05, + a_PREG_Pg1013_Noop, + a_VREG_Noop_Vdn05, +} + +var Zm_T__Zdn_T__PgM__Zdn_T__1 = []operand{ + a_ARNG_Zm510V1_SizeBHSD2224, + a_ARNG_ZdnDest_SizeBHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_SizeBHSD2224, +} + +var Zm_T__Zdn_T__PgM__Zdn_T__2 = []operand{ + a_ARNG_Zm510V1_SizeHSD2224, + a_ARNG_ZdnDest_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_SizeHSD2224, +} + +var Zm_T__Zdn_T__PgM__Zdn_T__3 = []operand{ + a_ARNG_Zm510V1_SizeHSD2224No00, + a_ARNG_ZdnDest_SizeHSD2224No00, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_SizeHSD2224No00, +} + +var Zm_T__Zdn_T__PgM__Zdn_T__4 = []operand{ + a_ARNG_Zm510V1_Size0SD2223, + a_ARNG_ZdnDest_Size0SD2223, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_Size0SD2223, +} + +var Zm_T__Zdn_T__Pg__Zdn_T = []operand{ + a_ARNG_Zm510V1_SizeBHSD2224, + a_ARNG_ZdnDest_SizeBHSD2224, + a_PREG_Pg1013_Noop, + a_ARNG_ZdnDest_SizeBHSD2224, +} + +var Zm_T__Zdn_T__Pv__Zdn_T = []operand{ + a_ARNG_Zm510V1_SizeBHSD2224, + a_ARNG_ZdnDest_SizeBHSD2224, + a_PREG_Pv1013_Noop, + a_ARNG_ZdnDest_SizeBHSD2224, +} + +var Zm_T__Zn_T__PgM__Zda_T__1 = []operand{ + a_ARNG_Zm1621V2_SizeHSD2224No00, + a_ARNG_Zn510V1_SizeHSD2224No00, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zda3RdSrcDst_SizeHSD2224No00, +} + +var Zm_T__Zn_T__PgM__Zda_T__2 = []operand{ + a_ARNG_Zm1621V2_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zda3RdSrcDst_SizeBHSD2224, +} + +var Zm_T__Zn_T__PgZ__Pd_T__1 = []operand{ + a_ARNG_Zm1621V2_SizeHSD2224, + a_ARNG_Zn510V1_SizeHSD2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Pd_SizeHSD2224, +} + +var Zm_T__Zn_T__PgZ__Pd_T__2 = []operand{ + a_ARNG_Zm1621V2_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Pd_SizeBHSD2224, +} + +var Zm_T__Zn_T__PgZ__Pd_T__3 = []operand{ + a_ARNG_Zm1621V2_Size0BH2223, + a_ARNG_Zn510V1_Size0BH2223, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Pd_Size0BH2223, +} + +var Zm_T__Zn_T__PgZ__Zd_T = []operand{ + a_ARNG_Zm1621V2_Size0SD2223, + a_ARNG_Zn510V1_Size0SD2223, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_Size0SD2223, +} + +var Zm_T__Zn_T__Pv__Zd_T = []operand{ + a_ARNG_Zm1621V2_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, + a_PREG_Pv1014_Noop, + a_ARNG_Zd_SizeBHSD2224, +} + +var Zm_T__Zn_T__Zd_T__1 = []operand{ + a_ARNG_Zm1621V2_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, + a_ARNG_Zd_SizeBHSD2224, +} + +var Zm_T__Zn_T__Zd_T__2 = []operand{ + a_ARNG_Zm1621V2_SizeHSD2224No00, + a_ARNG_Zn510V1_SizeHSD2224No00, + a_ARNG_Zd_SizeHSD2224No00, +} + +var Zm_T__Zn_T__Zd_T__3 = []operand{ + a_ARNG_Zm1621V2_SizeHSD2224, + a_ARNG_Zn510V1_SizeHSD2224, + a_ARNG_Zd_SizeHSD2224, +} + +var Zm_T__Zn_T__Zda_T__1 = []operand{ + a_ARNG_Zm1621V2_SzSD2223, + a_ARNG_Zn510V1_SzSD2223, + a_ARNG_Zda3RdSrcDst_SzSD2223, +} + +var Zm_T__Zn_T__Zda_T__2 = []operand{ + a_ARNG_Zm1621V2_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, + a_ARNG_Zda3RdSrcDst_SizeBHSD2224, +} + +var Zm_T___Zn1_T__Zn2_T___Zd_T = []operand{ + a_ARNG_Zm1621V2_SizeBHSD2224, + a_REGLIST2_GenZn510V1_SizeBHSD2224_GenZn510V2_SizeBHSD2224, + a_ARNG_Zd_SizeBHSD2224, +} + +var Zm_T___Zn_T___Zd_T = []operand{ + a_ARNG_Zm1621V2_SizeBHSD2224, + a_REGLIST1_Zn510V1_SizeBHSD2224, + a_ARNG_Zd_SizeBHSD2224, +} + +var Zm_Tb__Zn_T__Zd_T = []operand{ + a_ARNG_Zm1621V2_SizeTbBHS2224, + a_ARNG_Zn510V1_SizeHSD2224, + a_ARNG_Zd_SizeHSD2224, +} + +var Zm_Tb__Zn_Tb__Zd_T__1 = []operand{ + a_ARNG_Zm1621V2_SizeTbBHS2224, + a_ARNG_Zn510V1_SizeTbBHS2224, + a_ARNG_Zd_SizeHSD2224, +} + +var Zm_Tb__Zn_Tb__Zd_T__2 = []operand{ + a_ARNG_Zm1621V2_SizeTbHSD2224Offset1, + a_ARNG_Zn510V1_SizeTbHSD2224Offset1, + a_ARNG_Zd_SizeBHS2224Offset1, +} + +var Zm_Tb__Zn_Tb__Zd_T__3 = []operand{ + a_ARNG_Zm1621V2_SizeTbBS2224, + a_ARNG_Zn510V1_SizeTbBS2224, + a_ARNG_Zd_SizeHD2224, +} + +var Zm_Tb__Zn_Tb__Zda_T__1 = []operand{ + a_ARNG_Zm1621V2_SizeTbBHS2224, + a_ARNG_Zn510V1_SizeTbBHS2224, + a_ARNG_Zda3RdSrcDst_SizeHSD2224, +} + +var Zm_Tb__Zn_Tb__Zda_T__2 = []operand{ + a_ARNG_Zm1621V2_Size0TbBH2223, + a_ARNG_Zn510V1_Size0TbBH2223, + a_ARNG_Zda3RdSrcDst_Size0SD2223, +} + +var Zm___Zn1_B__Zn2_B___Zd_B = []operand{ + a_ZREG_Zm1621V1_Noop, + a_REGLIST2_Zn510Table1_ArngBCheck_Zn510Table2_ArngBCheck, + a_ARNG_Zd_ArngBCheck, +} + +var Zm_index____Zn1_H__Zn2_H___Zd_H__1 = []operand{ + a_ZREGIDX_Zm1621V1_Noop_I22224HW, + a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zm_index____Zn1_H__Zn2_H___Zd_H__2 = []operand{ + a_ZREGIDX_Zm1621V1_Noop_I12324, + a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zm_index____Zn_B___Zd_B__1 = []operand{ + a_ZREGIDX_Zm1621V1_Noop_I22224, + a_REGLIST1_Zn510Table3_ArngBCheck, + a_ARNG_Zd_ArngBCheck, +} + +var Zm_index____Zn_B___Zd_B__2 = []operand{ + a_ZREGIDX_Zm1621V1_Noop_I12324B, + a_REGLIST1_Zn510Table3_ArngBCheck, + a_ARNG_Zd_ArngBCheck, +} + +var Zm_index____Zn_H___Zd_H__1 = []operand{ + a_ZREGIDX_Zm1621V1_Noop_I3224I31213, + a_REGLIST1_Zn510Table3_ArngHCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zm_index____Zn_H___Zd_H__2 = []operand{ + a_ZREGIDX_Zm1621V1_Noop_I22224HW, + a_REGLIST1_Zn510Table3_ArngHCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zn1_H_Zn2_H___Zd_B = []operand{ + a_REGLIST_RANGE_Zn610V1_ArngHCheck_Zn610V2_ArngHCheck, + a_ARNG_Zd_ArngBCheck, +} + +var Zn1_S_Zn2_S___Zd_B = []operand{ + a_REGLIST_RANGE_Zn610V1_ArngSCheck_Zn610V2_ArngSCheck, + a_ARNG_Zd_ArngBCheck, +} + +var Zn1_S_Zn2_S___Zd_H = []operand{ + a_REGLIST_RANGE_Zn610V1_ArngSCheck_Zn610V2_ArngSCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zn1_T__Zn2_T___Pv__Zd_T = []operand{ + a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224, + a_PREG_Pv1013_Noop, + a_ARNG_Zd_SizeBHSD2224, +} + +var Zn1_Tb_Zn2_Tb___Zd_T = []operand{ + a_REGLIST_RANGE_Zn610V1_SizeTbHSD2224Offset1_Zn610V2_SizeTbHSD2224Offset1, + a_ARNG_Zd_SizeBHS2224Offset1, +} + +var Zn_B__Zd_H = []operand{ + a_ARNG_Zn510Src_ArngBCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zn_D__PgM__Zd_D = []operand{ + a_ARNG_Zn510Src_ArngDCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_ArngDCheck, +} + +var Zn_D__PgM__Zd_H = []operand{ + a_ARNG_Zn510Src_ArngDCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zn_D__PgM__Zd_S = []operand{ + a_ARNG_Zn510Src_ArngDCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_ArngSCheck, +} + +var Zn_D__PgZ__Zd_D = []operand{ + a_ARNG_Zn510Src_ArngDCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_ArngDCheck, +} + +var Zn_D__PgZ__Zd_H = []operand{ + a_ARNG_Zn510Src_ArngDCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zn_D__PgZ__Zd_S = []operand{ + a_ARNG_Zn510Src_ArngDCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_ArngSCheck, +} + +var Zn_D__Xm___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var Zn_D__Xm___PgZ___Zt_Q_ = []operand{ + a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngQCheck, +} + +var Zn_D__Zm_D__SXTWamount___Zd_D = []operand{ + a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModSXTWCheck_Msz1012Amount, + a_ARNG_Zd_ArngDCheck, +} + +var Zn_D__Zm_D__UXTWamount___Zd_D = []operand{ + a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModUXTWCheck_Msz1012Amount, + a_ARNG_Zd_ArngDCheck, +} + +var Zn_D__cimm___PgZ___Zt_D___1 = []operand{ + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var Zn_D__cimm___PgZ___Zt_D___2 = []operand{ + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var Zn_D__cimm___PgZ___Zt_D___3 = []operand{ + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var Zn_D__cimm___PgZ___Zt_D___4 = []operand{ + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var Zn_D__cimm___Pg__prfop__1 = []operand{ + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var Zn_D__cimm___Pg__prfop__2 = []operand{ + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var Zn_D__cimm___Pg__prfop__3 = []operand{ + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var Zn_D__cimm___Pg__prfop__4 = []operand{ + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var Zn_H__PgM__Zd_D = []operand{ + a_ARNG_Zn510Src_ArngHCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_ArngDCheck, +} + +var Zn_H__PgM__Zd_H = []operand{ + a_ARNG_Zn510Src_ArngHCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zn_H__PgM__Zd_S = []operand{ + a_ARNG_Zn510Src_ArngHCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_ArngSCheck, +} + +var Zn_H__PgZ__Zd_D = []operand{ + a_ARNG_Zn510Src_ArngHCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_ArngDCheck, +} + +var Zn_H__PgZ__Zd_H = []operand{ + a_ARNG_Zn510Src_ArngHCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zn_H__PgZ__Zd_S = []operand{ + a_ARNG_Zn510Src_ArngHCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_ArngSCheck, +} + +var Zn_Q__PgM__Zd_Q = []operand{ + a_ARNG_Zn510Src_ArngQCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_ArngQCheck, +} + +var Zn_Q__PgZ__Zd_Q = []operand{ + a_ARNG_Zn510Src_ArngQCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_ArngQCheck, +} + +var Zn_S__PgM__Zd_D = []operand{ + a_ARNG_Zn510Src_ArngSCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_ArngDCheck, +} + +var Zn_S__PgM__Zd_H = []operand{ + a_ARNG_Zn510Src_ArngSCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zn_S__PgM__Zd_S = []operand{ + a_ARNG_Zn510Src_ArngSCheck, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_ArngSCheck, +} + +var Zn_S__PgZ__Zd_D = []operand{ + a_ARNG_Zn510Src_ArngSCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_ArngDCheck, +} + +var Zn_S__PgZ__Zd_H = []operand{ + a_ARNG_Zn510Src_ArngSCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_ArngHCheck, +} + +var Zn_S__PgZ__Zd_S = []operand{ + a_ARNG_Zn510Src_ArngSCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_ArngSCheck, +} + +var Zn_S__Xm___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var Zn_S__cimm___PgZ___Zt_S___1 = []operand{ + a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var Zn_S__cimm___PgZ___Zt_S___2 = []operand{ + a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var Zn_S__cimm___PgZ___Zt_S___3 = []operand{ + a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var Zn_S__cimm___Pg__prfop__1 = []operand{ + a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var Zn_S__cimm___Pg__prfop__2 = []operand{ + a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V3, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var Zn_S__cimm___Pg__prfop__3 = []operand{ + a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var Zn_S__cimm___Pg__prfop__4 = []operand{ + a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2, + a_PREG_Pg1013_Noop, + a_SPECIAL_Prfop04, +} + +var Zn_T__PgM__Zd_T__1 = []operand{ + a_ARNG_Zn510Src_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_SizeHSD2224, +} + +var Zn_T__PgM__Zd_T__2 = []operand{ + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_SizeBHSD2224, +} + +var Zn_T__PgM__Zd_T__3 = []operand{ + a_ARNG_Zn510Src_SzSD1718, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_SzSD1718, +} + +var Zn_T__PgM__Zd_T__4 = []operand{ + a_ARNG_Zn510Src_SizeByteMergeZero, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_SizeByteMergeZero, +} + +var Zn_T__PgM__Zd_T__5 = []operand{ + a_ARNG_Zn510Src_Size0HalfwordMergeZero, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_Size0HalfwordMergeZero, +} + +var Zn_T__PgM__Zd_T__6 = []operand{ + a_ARNG_Zn510Src_SizeHSD1719, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_SizeHSD1719, +} + +var Zn_T__PgZM__Zd_T = []operand{ + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREGZM_Pg1013_PredQualM1617, + a_ARNG_Zd_SizeBHSD2224, +} + +var Zn_T__PgZ__Zd_T__1 = []operand{ + a_ARNG_Zn510Src_SizeHSD2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_SizeHSD2224, +} + +var Zn_T__PgZ__Zd_T__2 = []operand{ + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_SizeBHSD2224, +} + +var Zn_T__PgZ__Zd_T__3 = []operand{ + a_ARNG_Zn510Src_SzSD1415, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_SzSD1415, +} + +var Zn_T__PgZ__Zd_T__4 = []operand{ + a_ARNG_Zn510Src_SizeByteMergeZero, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_SizeByteMergeZero, +} + +var Zn_T__PgZ__Zd_T__5 = []operand{ + a_ARNG_Zn510Src_Size0HalfwordMergeZero, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_Size0HalfwordMergeZero, +} + +var Zn_T__PgZ__Zd_T__6 = []operand{ + a_ARNG_Zn510Src_SizeHSD1315, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Zd_SizeHSD1315, +} + +var Zn_T__Pg__Dd__1 = []operand{ + a_ARNG_Zn510Src_SizeBHS2224, + a_PREG_Pg1013_Noop, + a_VREG_Noop_Vd0564, +} + +var Zn_T__Pg__Dd__2 = []operand{ + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREG_Pg1013_Noop, + a_VREG_Noop_Vd0564, +} + +var Zn_T__Pg__Rd = []operand{ + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREG_Pg1013_Noop, + a_SPZGREG_Noop_Rd05ZR, +} + +var Zn_T__Pg__Vd__1 = []operand{ + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREG_Pg1013_Noop, + a_VREG_Noop_Vd05, +} + +var Zn_T__Pg__Vd__2 = []operand{ + a_ARNG_Zn510Src_SizeHSD2224, + a_PREG_Pg1013_Noop, + a_VREG_Noop_Vd05, +} + +var Zn_T__Pg__Zd_T__1 = []operand{ + a_ARNG_Zn510Src_SzByteHalfword, + a_PREG_Pg1013_Noop, + a_ARNG_Zd_SzByteHalfword, +} + +var Zn_T__Pg__Zd_T__2 = []operand{ + a_ARNG_Zn510Src_SzWordDoubleword, + a_PREG_Pg1013_Noop, + a_ARNG_Zd_SzWordDoubleword, +} + +var Zn_T__Pg__Zd_T__3 = []operand{ + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREG_Pg1013_Noop, + a_ARNG_Zd_SizeBHSD2224, +} + +var Zn_T__Zd_T__1 = []operand{ + a_ARNG_Zn510Src_SizeHSD2224, + a_ARNG_Zd_SizeHSD2224, +} + +var Zn_T__Zd_T__2 = []operand{ + a_ARNG_Zn510Src_SizeBHSD2224, + a_ARNG_Zd_SizeBHSD2224, +} + +var Zn_T__Zm_T__mod_amount___Zd_T = []operand{ + a_MEMEXT_Zn510V2_SzSD2223_Zm1621V3_SzSD2223_Msz1012_Msz1012Amount, + a_ARNG_Zd_SzSD2223, +} + +var Zn_T_imm___Zd_T__1 = []operand{ + a_ARNGIDX_Zn510Src_Tsz_1621_SizeSpecifier5_Imm2Tsz_Delegate, + a_ARNG_Zd_Tsz_1621_SizeSpecifier5, +} + +var Zn_T_imm___Zd_T__2 = []operand{ + a_ARNGIDX_Zn510Src_Tsz_1620_SizeSpecifier4_I1Tsz_Delegate, + a_ARNG_Zd_Tsz_1620_SizeSpecifier4, +} + +var Zn_Tb__PgM__Zda_T = []operand{ + a_ARNG_Zn510V1_SizeTbBHS2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdaDest_SizeHSD2224, +} + +var Zn_Tb__Pg__Vd_T__1 = []operand{ + a_ARNG_Zn510Src_SizeTbBHSD2224, + a_PREG_Pg1013_Noop, + a_ARNG_Vd_Size16B8H4S2D, +} + +var Zn_Tb__Pg__Vd_T__2 = []operand{ + a_ARNG_Zn510Src_SizeTbHSD2224Offset1, + a_PREG_Pg1013_Noop, + a_ARNG_Vd_Size8H4S2D, +} + +var Zn_Tb__Zd_T__1 = []operand{ + a_ARNG_Zn510Src_SizeTbBHS2224, + a_ARNG_Zd_SizeHSD2224, +} + +var Zn_Tb__Zd_T__2 = []operand{ + a_ARNG_Zn510Src_TszhTszlTbHSD, + a_ARNG_Zd_TszhTszlBHS, +} + +var Zn__Pd_B = []operand{ + a_ZREG_Zn510Src_Noop, + a_ARNG_Pd_ArngBCheck, +} + +var Zn__Zd = []operand{ + a_ZREG_Zn510Src_Noop, + a_ZREG_Zd_Noop, +} + +var Zn_imm___Pd_D = []operand{ + a_ZREGIDX_Zn510Src_Noop_I3hI3l_1722_Doubleword, + a_ARNG_Pd_ArngDCheck, +} + +var Zn_imm___Pd_H = []operand{ + a_ZREGIDX_Zn510Src_Noop_I1_1718_Halfword, + a_ARNG_Pd_ArngHCheck, +} + +var Zn_imm___Pd_S = []operand{ + a_ZREGIDX_Zn510Src_Noop_I2_1719_Word, + a_ARNG_Pd_ArngSCheck, +} + +var Zt1_B_Zt2_B___PNg___XnSP__Xm_ = []operand{ + a_REGLIST_RANGE_Zt15V1_ArngBCheck_Zt15V2_ArngBCheck, + a_PREG_PNg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, +} + +var Zt1_B_Zt2_B___PNg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST_RANGE_Zt15V1_ArngBCheck_Zt15V2_ArngBCheck, + a_PREG_PNg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9, +} + +var Zt1_B_Zt4_B___PNg___XnSP__Xm_ = []operand{ + a_REGLIST_RANGE_Zt25V1_ArngBCheck_Zt25V2_ArngBCheck, + a_PREG_PNg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, +} + +var Zt1_B_Zt4_B___PNg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST_RANGE_Zt25V1_ArngBCheck_Zt25V2_ArngBCheck, + a_PREG_PNg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8, +} + +var Zt1_B__Zt2_B__Zt3_B__Zt4_B___Pg___XnSP__Xm_ = []operand{ + a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, +} + +var Zt1_B__Zt2_B__Zt3_B__Zt4_B___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4, +} + +var Zt1_B__Zt2_B__Zt3_B___Pg___XnSP__Xm_ = []operand{ + a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, +} + +var Zt1_B__Zt2_B__Zt3_B___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3, +} + +var Zt1_B__Zt2_B___Pg___XnSP__Xm_ = []operand{ + a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, +} + +var Zt1_B__Zt2_B___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6, +} + +var Zt1_D_Zt2_D___PNg___XnSP__Xm__LSL_c3_ = []operand{ + a_REGLIST_RANGE_Zt15V1_ArngDCheck_Zt15V2_ArngDCheck, + a_PREG_PNg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, +} + +var Zt1_D_Zt2_D___PNg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST_RANGE_Zt15V1_ArngDCheck_Zt15V2_ArngDCheck, + a_PREG_PNg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9, +} + +var Zt1_D_Zt4_D___PNg___XnSP__Xm__LSL_c3_ = []operand{ + a_REGLIST_RANGE_Zt25V1_ArngDCheck_Zt25V2_ArngDCheck, + a_PREG_PNg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, +} + +var Zt1_D_Zt4_D___PNg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST_RANGE_Zt25V1_ArngDCheck_Zt25V2_ArngDCheck, + a_PREG_PNg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8, +} + +var Zt1_D__Zt2_D__Zt3_D__Zt4_D___Pg___XnSP__Xm__LSL_c3_ = []operand{ + a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, +} + +var Zt1_D__Zt2_D__Zt3_D__Zt4_D___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4, +} + +var Zt1_D__Zt2_D__Zt3_D___Pg___XnSP__Xm__LSL_c3_ = []operand{ + a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, +} + +var Zt1_D__Zt2_D__Zt3_D___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3, +} + +var Zt1_D__Zt2_D___Pg___XnSP__Xm__LSL_c3_ = []operand{ + a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, +} + +var Zt1_D__Zt2_D___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6, +} + +var Zt1_H_Zt2_H___PNg___XnSP__Xm__LSL_c1_ = []operand{ + a_REGLIST_RANGE_Zt15V1_ArngHCheck_Zt15V2_ArngHCheck, + a_PREG_PNg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, +} + +var Zt1_H_Zt2_H___PNg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST_RANGE_Zt15V1_ArngHCheck_Zt15V2_ArngHCheck, + a_PREG_PNg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9, +} + +var Zt1_H_Zt4_H___PNg___XnSP__Xm__LSL_c1_ = []operand{ + a_REGLIST_RANGE_Zt25V1_ArngHCheck_Zt25V2_ArngHCheck, + a_PREG_PNg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, +} + +var Zt1_H_Zt4_H___PNg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST_RANGE_Zt25V1_ArngHCheck_Zt25V2_ArngHCheck, + a_PREG_PNg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8, +} + +var Zt1_H__Zt2_H__Zt3_H__Zt4_H___Pg___XnSP__Xm__LSL_c1_ = []operand{ + a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, +} + +var Zt1_H__Zt2_H__Zt3_H__Zt4_H___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4, +} + +var Zt1_H__Zt2_H__Zt3_H___Pg___XnSP__Xm__LSL_c1_ = []operand{ + a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, +} + +var Zt1_H__Zt2_H__Zt3_H___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3, +} + +var Zt1_H__Zt2_H___Pg___XnSP__Xm__LSL_c1_ = []operand{ + a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, +} + +var Zt1_H__Zt2_H___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6, +} + +var Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q___Pg___XnSP__Xm__LSL_c4_ = []operand{ + a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, +} + +var Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4, +} + +var Zt1_Q__Zt2_Q__Zt3_Q___Pg___XnSP__Xm__LSL_c4_ = []operand{ + a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, +} + +var Zt1_Q__Zt2_Q__Zt3_Q___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3, +} + +var Zt1_Q__Zt2_Q___Pg___XnSP__Xm__LSL_c4_ = []operand{ + a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, +} + +var Zt1_Q__Zt2_Q___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6, +} + +var Zt1_S_Zt2_S___PNg___XnSP__Xm__LSL_c2_ = []operand{ + a_REGLIST_RANGE_Zt15V1_ArngSCheck_Zt15V2_ArngSCheck, + a_PREG_PNg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, +} + +var Zt1_S_Zt2_S___PNg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST_RANGE_Zt15V1_ArngSCheck_Zt15V2_ArngSCheck, + a_PREG_PNg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9, +} + +var Zt1_S_Zt4_S___PNg___XnSP__Xm__LSL_c2_ = []operand{ + a_REGLIST_RANGE_Zt25V1_ArngSCheck_Zt25V2_ArngSCheck, + a_PREG_PNg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, +} + +var Zt1_S_Zt4_S___PNg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST_RANGE_Zt25V1_ArngSCheck_Zt25V2_ArngSCheck, + a_PREG_PNg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8, +} + +var Zt1_S__Zt2_S__Zt3_S__Zt4_S___Pg___XnSP__Xm__LSL_c2_ = []operand{ + a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, +} + +var Zt1_S__Zt2_S__Zt3_S__Zt4_S___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4, +} + +var Zt1_S__Zt2_S__Zt3_S___Pg___XnSP__Xm__LSL_c2_ = []operand{ + a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, +} + +var Zt1_S__Zt2_S__Zt3_S___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3, +} + +var Zt1_S__Zt2_S___Pg___XnSP__Xm__LSL_c2_ = []operand{ + a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, +} + +var Zt1_S__Zt2_S___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6, +} + +var Zt_B___Pg___XnSP__Xm_ = []operand{ + a_REGLIST1_Zt05_ArngBCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, +} + +var Zt_B___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST1_Zt05_ArngBCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, +} + +var Zt_D___Pg___XnSP__Xm__LSL_c3_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, +} + +var Zt_D___Pg___XnSP__Zm_D_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck, +} + +var Zt_D___Pg___XnSP__Zm_D__LSL_c1_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check, +} + +var Zt_D___Pg___XnSP__Zm_D__LSL_c2_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check, +} + +var Zt_D___Pg___XnSP__Zm_D__LSL_c3_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check, +} + +var Zt_D___Pg___XnSP__Zm_D__mod_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_NoAmtCheck, +} + +var Zt_D___Pg___XnSP__Zm_D__mod_c1_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt1Check, +} + +var Zt_D___Pg___XnSP__Zm_D__mod_c2_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt2Check, +} + +var Zt_D___Pg___XnSP__Zm_D__mod_c3_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt3Check, +} + +var Zt_D___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, +} + +var Zt_D___Pg___Zn_D__Xm_ = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, +} + +var Zt_D___Pg___Zn_D__cimm___1 = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4, +} + +var Zt_D___Pg___Zn_D__cimm___2 = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3, +} + +var Zt_D___Pg___Zn_D__cimm___3 = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1, +} + +var Zt_D___Pg___Zn_D__cimm___4 = []operand{ + a_REGLIST1_Zt05_ArngDCheck, + a_PREG_Pg1013_Noop, + a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2, +} + +var Zt_H___Pg___XnSP__Xm__LSL_c1_ = []operand{ + a_REGLIST1_Zt05_ArngHCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, +} + +var Zt_H___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST1_Zt05_ArngHCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, +} + +var Zt_Q___Pg___XnSP__Xm__LSL_c2_ = []operand{ + a_REGLIST1_Zt05_ArngQCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, +} + +var Zt_Q___Pg___XnSP__Xm__LSL_c3_ = []operand{ + a_REGLIST1_Zt05_ArngQCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, +} + +var Zt_Q___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST1_Zt05_ArngQCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, +} + +var Zt_Q___Pg___Zn_D__Xm_ = []operand{ + a_REGLIST1_Zt05_ArngQCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, +} + +var Zt_S___Pg___XnSP__Xm__LSL_c2_ = []operand{ + a_REGLIST1_Zt05_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, +} + +var Zt_S___Pg___XnSP__Zm_S__mod_ = []operand{ + a_REGLIST1_Zt05_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_NoAmtCheck, +} + +var Zt_S___Pg___XnSP__Zm_S__mod_c1_ = []operand{ + a_REGLIST1_Zt05_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt1Check, +} + +var Zt_S___Pg___XnSP__Zm_S__mod_c2_ = []operand{ + a_REGLIST1_Zt05_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt2Check, +} + +var Zt_S___Pg___XnSP__cimm__MUL_VL_ = []operand{ + a_REGLIST1_Zt05_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, +} + +var Zt_S___Pg___Zn_S__Xm_ = []operand{ + a_REGLIST1_Zt05_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, +} + +var Zt_S___Pg___Zn_S__cimm___1 = []operand{ + a_REGLIST1_Zt05_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4, +} + +var Zt_S___Pg___Zn_S__cimm___2 = []operand{ + a_REGLIST1_Zt05_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1, +} + +var Zt_S___Pg___Zn_S__cimm___3 = []operand{ + a_REGLIST1_Zt05_ArngSCheck, + a_PREG_Pg1013_Noop, + a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2, +} + +var Zt_T___Pg___XnSP__Xm_ = []operand{ + a_REGLIST1_Zt05_Size2123V1, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, +} + +var Zt_T___Pg___XnSP__Xm__LSL_c1_ = []operand{ + a_REGLIST1_Zt05_Size2123V2, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, +} + +var Zt_T___Pg___XnSP__Xm__LSL_c2_ = []operand{ + a_REGLIST1_Zt05_Sz2122, + a_PREG_Pg1013_Noop, + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, +} + +var Zt_T___Pg___XnSP__cimm__MUL_VL___1 = []operand{ + a_REGLIST1_Zt05_Size2123V1, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, +} + +var Zt_T___Pg___XnSP__cimm__MUL_VL___2 = []operand{ + a_REGLIST1_Zt05_Size2123V2, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, +} + +var Zt_T___Pg___XnSP__cimm__MUL_VL___3 = []operand{ + a_REGLIST1_Zt05_Sz2122, + a_PREG_Pg1013_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5, +} + +var Zt___XnSP__cimm__MUL_VL_ = []operand{ + a_ZREG_Zt05_Noop, + a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013, +} + +var c0_0__Zn_T__PgZ__Pd_T = []operand{ + a_IMM_Fimm0_0_56, + a_ARNG_Zn510Src_SizeHSD2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Pd_SizeHSD2224, +} + +var cconst__PgM__Zd_T = []operand{ + a_IMM_Imm8_513_Fimm, + a_PREGZM_Pg1620_MergePredCheck, + a_ARNG_Zd_SizeHSD2224, +} + +var cconst__Zd_T__1 = []operand{ + a_IMM_Imm13_518, + a_ARNG_Zd_SizeImm13NoOp, +} + +var cconst__Zd_T__2 = []operand{ + a_IMM_Imm8_513_Fimm, + a_ARNG_Zd_SizeHSD2224, +} + +var cconst__Zdn_T__PgM__Zdn_T__1 = []operand{ + a_IMM_ShiftTsz58Range1, + a_ARNG_ZdnSrcDst_SizeBhsdTsz810, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnSrcDst_SizeBhsdTsz810, +} + +var cconst__Zdn_T__PgM__Zdn_T__2 = []operand{ + a_IMM_ShiftTsz58Range0, + a_ARNG_ZdnSrcDst_SizeBhsdTsz810, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnSrcDst_SizeBhsdTsz810, +} + +var cconst__Zdn_T__Zdn_T = []operand{ + a_IMM_Imm13_518, + a_ARNG_ZdnSrcDst_SizeImm13NoOp, + a_ARNG_ZdnSrcDst_SizeImm13NoOp, +} + +var cconst__Zm_T__Zdn_T__Zdn_T = []operand{ + a_IMM_ShiftTsz1619Range1V2, + a_ARNG_Zm510V1_SizeBhsdTsz1921, + a_ARNG_ZdnDest_SizeBhsdTsz1921, + a_ARNG_ZdnDest_SizeBhsdTsz1921, +} + +var cconst__Zn_T__Zd_T__1 = []operand{ + a_IMM_ShiftTsz1619Range1V2, + a_ARNG_Zn510Src_SizeBhsdTsz1921, + a_ARNG_Zd_SizeBhsdTsz1921, +} + +var cconst__Zn_T__Zd_T__2 = []operand{ + a_IMM_ShiftTsz1619Range0V2, + a_ARNG_Zn510Src_SizeBhsdTsz1921, + a_ARNG_Zd_SizeBhsdTsz1921, +} + +var cconst__Zn_T__Zda_T = []operand{ + a_IMM_ShiftTsz1619Range1V2, + a_ARNG_Zn510V1_SizeBhsdTsz1921, + a_ARNG_Zda3RdSrcDst_SizeBhsdTsz1921, +} + +var cconst__Zn_Tb__Zd_T__1 = []operand{ + a_IMM_ShiftTsz1619Range1V1, + a_ARNG_Zn510Src_SizeHsdTsz1921Unique, + a_ARNG_Zd_SizeBhsTsz1921, +} + +var cconst__Zn_Tb__Zd_T__2 = []operand{ + a_IMM_ShiftTsz1619Range0V1, + a_ARNG_Zn510Src_SizeBhsTsz1921Unique, + a_ARNG_Zd_SizeHsdTsz1921, +} + +var cconst___Zn1_H_Zn2_H___Zd_B = []operand{ + a_IMM_Imm31619, + a_REGLIST_RANGE_Zn610V1_ArngHCheck_Zn610V2_ArngHCheck, + a_ARNG_Zd_ArngBCheck, +} + +var cconst___Zn1_S_Zn2_S___Zd_H = []operand{ + a_IMM_Imm41620V7, + a_REGLIST_RANGE_Zn610V1_ArngSCheck_Zn610V2_ArngSCheck, + a_ARNG_Zd_ArngHCheck, +} + +var cconst___Zn1_Tb_Zn2_Tb___Zd_T = []operand{ + a_IMM_Imm3Tsize1621Stub, + a_REGLIST_RANGE_Zn610V1_Tsize1921V2_Zn610V2_Tsize1921V2, + a_ARNG_Zd_Tsize1921V1, +} + +var cimm2__cimm1__Zd_T = []operand{ + a_IMM_Imm5bSigned_1621, + a_IMM_Imm5Signed_510, + a_ARNG_Zd_SizeBHSD2224, +} + +var cimm__Rn__Zd_T = []operand{ + a_IMM_Imm5Signed_1621V1, + a_SPZGREG_Noop_Rn510ZR, + a_ARNG_Zd_SizeBHSD2224, +} + +var cimm__Xd = []operand{ + a_IMM_Imm6Signed_511, + a_SPZGREG_Noop_Rd05, +} + +var cimm__XnSP__XdSP = []operand{ + a_IMM_Imm6Signed_511, + a_SPZGREG_XCheck_Rn1621_SPAllowed, + a_SPZGREG_XCheck_Rd05_SPAllowed, +} + +var cimm__Zdn_T__Zdn_T__1 = []operand{ + a_IMM_Imm8Signed_513, + a_ARNG_ZdnSrcDst_SizeBHSD2224, + a_ARNG_ZdnSrcDst_SizeBHSD2224, +} + +var cimm__Zdn_T__Zdn_T__2 = []operand{ + a_IMM_Imm8Unsigned_513, + a_ARNG_ZdnSrcDst_SizeBHSD2224, + a_ARNG_ZdnSrcDst_SizeBHSD2224, +} + +var cimm__Zm_B__Zdn_B__Zdn_B__1 = []operand{ + a_IMM_Imm8hImm8l_Unsigned, + a_ARNG_Zm510V1_ArngBCheck, + a_ARNG_ZdnDest_ArngBCheck, + a_ARNG_ZdnDest_ArngBCheck, +} + +var cimm__Zm_B__Zdn_B__Zdn_B__2 = []operand{ + a_IMM_Imm4Unsigned_1620, + a_ARNG_Zm510V1_ArngBCheck, + a_ARNG_ZdnDest_ArngBCheck, + a_ARNG_ZdnDest_ArngBCheck, +} + +var cimm__Zm_T__Zdn_T__Zdn_T = []operand{ + a_IMM_Imm3Unsigned_1619, + a_ARNG_Zm510V1_SizeHSD2224, + a_ARNG_ZdnDest_SizeHSD2224, + a_ARNG_ZdnDest_SizeHSD2224, +} + +var cimm__Zn_T__PgZ__Pd_T__1 = []operand{ + a_IMM_Imm5Signed_1621V2, + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Pd_SizeBHSD2224, +} + +var cimm__Zn_T__PgZ__Pd_T__2 = []operand{ + a_IMM_Imm7Unsigned_1421, + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Pd_SizeBHSD2224, +} + +var cimm___Zn1_B__Zn2_B___Zd_B = []operand{ + a_IMM_Imm8hImm8l_Unsigned, + a_REGLIST2_Zn510MultiSrc1_ArngBCheck_Zn510MultiSrc2_ArngBCheck, + a_ARNG_Zd_ArngBCheck, +} + +var cimm__shift__PgM__Zd_T = []operand{ + a_IMM_Imm8SignedLsl8, + a_PREGZM_Pg1620_MergePredCheck, + a_ARNG_Zd_SizeBHSD2224, +} + +var cimm__shift__PgZ__Zd_T = []operand{ + a_IMM_Imm8SignedLsl8, + a_PREGZM_Pg1620_ZeroPredCheck, + a_ARNG_Zd_SizeBHSD2224, +} + +var cimm__shift__Zd_T = []operand{ + a_IMM_Imm8SignedLsl8, + a_ARNG_Zd_SizeBHSD2224, +} + +var cimm__shift__Zdn_T__Zdn_T = []operand{ + a_IMM_Imm8UnsignedLsl8, + a_ARNG_ZdnSrcDst_SizeBHSD2224, + a_ARNG_ZdnSrcDst_SizeBHSD2224, +} + +var const__Zdn_T__PgM__Zdn_T__1 = []operand{ + a_IMM_Fimm0_0_1_0_56, + a_ARNG_ZdnSrcDst_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnSrcDst_SizeHSD2224, +} + +var const__Zdn_T__PgM__Zdn_T__2 = []operand{ + a_IMM_Fimm0_5_1_0_56, + a_ARNG_ZdnSrcDst_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnSrcDst_SizeHSD2224, +} + +var const__Zdn_T__PgM__Zdn_T__3 = []operand{ + a_IMM_Fimm0_5_2_0_56, + a_ARNG_ZdnSrcDst_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnSrcDst_SizeHSD2224, +} + +var const__Zm_B_imm___Zn_B__Zda_S = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit, + a_ARNG_Zn510V1_ArngBCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var const__Zm_H_imm___Zn_H__Zda_D = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngDCheck, +} + +var const__Zm_H_imm___Zn_H__Zda_H__1 = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm_1619_Range0_7V1_ArngHCheck_I2_1921_16bit, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var const__Zm_H_imm___Zn_H__Zda_H__2 = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm_1619_Half_ArngHCheck_I2_1921_Half, + a_ARNG_Zn510V1_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var const__Zm_S_imm___Zn_S__Zda_S__1 = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm_1620_Range0_15_ArngSCheck_I1_2021_32bit, + a_ARNG_Zn510V1_ArngSCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var const__Zm_S_imm___Zn_S__Zda_S__2 = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm_1620_Single_ArngSCheck_I1_2021_Single, + a_ARNG_Zn510V1_ArngSCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var const__Zm_T__Zdn_T__PgM__Zdn_T = []operand{ + a_IMM_Rot90_270_1617, + a_ARNG_Zm510V1_SizeHSD2224, + a_ARNG_ZdnDest_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_SizeHSD2224, +} + +var const__Zm_T__Zdn_T__Zdn_T = []operand{ + a_IMM_Rot90_270_1011, + a_ARNG_Zm510V1_SizeBHSD2224, + a_ARNG_ZdnDest_SizeBHSD2224, + a_ARNG_ZdnDest_SizeBHSD2224, +} + +var const__Zm_T__Zn_T__PgM__Zda_T = []operand{ + a_IMM_Rot0_90_180_270_1315, + a_ARNG_Zm1621V2_SizeHSD2224, + a_ARNG_Zn510V1_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zda3RdSrcDst_SizeHSD2224, +} + +var const__Zm_T__Zn_T__Zda_T = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNG_Zm1621V2_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, + a_ARNG_Zda3RdSrcDst_SizeBHSD2224, +} + +var const__Zm_Tb__Zn_Tb__Zda_T = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNG_Zm1621V2_Size0TbBH2223, + a_ARNG_Zn510V1_Size0TbBH2223, + a_ARNG_Zda3RdSrcDst_Size0SD2223, +} + +var oc = []operand{} + +var vl__PNn_T__Xd = []operand{ + a_SPECIAL_Vl1011, + a_ARNG_PNn59_SizeBHSD2224, + a_SPZGREG_Noop_Rd05, +} + +var vl__Xm__Xn__PNd_T = []operand{ + a_SPECIAL_Vl1314, + a_SPZGREG_Noop_Rm1621V1, + a_SPZGREG_Noop_Rn510, + a_ARNG_PNd_SizeBHSD2224, +} diff --git a/src/cmd/internal/obj/arm64/inst_test.go b/src/cmd/internal/obj/arm64/inst_test.go new file mode 100644 index 00000000000000..7e2bfc55bdffea --- /dev/null +++ b/src/cmd/internal/obj/arm64/inst_test.go @@ -0,0 +1,126 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package arm64 + +import ( + "math/bits" + "testing" + + "cmd/internal/obj" +) + +// decodeLogicalImmArrEncoding is translated from DecodeBitMasks in ARM64 +// ASL. It implements the decoding logic of imm13 defined by ARM64 specification. +func decodeLogicalImmArrEncoding(imm13 uint32, arr uint32) (uint64, bool) { + n := (imm13 >> 12) & 1 + immr := (imm13 >> 6) & 0x3F + imms := imm13 & 0x3F + + notImms := (^imms) & 0x3F + combined := (n << 6) | notImms + + // if immN::NOT(imms) == '000000x' then Undefined(); end; + if combined <= 1 { + return 0, false + } + + lenVal := bits.Len32(uint32(combined)) - 1 + esize := uint64(1 << lenVal) + + levels := uint32((1 << lenVal) - 1) + // if immediate && (imms AND levels) == levels then Undefined(); end; + if (imms & levels) == levels { + return 0, false + } + + s := uint64(imms & levels) + r := uint64(immr & levels) + + // welem has s + 1 ones + welem := (uint64(1) << (s + 1)) - 1 + + // Rotate right welem by r bits within esize bits window + rotated := welem + mask := (uint64(1) << esize) - 1 + if r > 0 { + r %= esize + rotated = ((welem >> r) | (welem << (esize - r))) & mask + } + + // Replicate rotated to fill 64 bits (as encode replicates to 64 bits) + wmask := uint64(0) + for i := uint64(0); i < 64; i += esize { + wmask |= rotated << i + } + + // Now mask back to the arrangement's lane size M + var M uint64 + switch arr { + case ARNG_B: + M = 8 + case ARNG_H: + M = 16 + case ARNG_S: + M = 32 + case ARNG_D: + M = 64 + default: + return 0, false + } + + mask = (uint64(1) << M) - 1 + return wmask & mask, true +} + +func FuzzLogicalImmArrEncoding(f *testing.F) { + f.Add(uint64(0x55), uint32(ARNG_B)) + f.Add(uint64(0xAA), uint32(ARNG_B)) + f.Add(uint64(0x0F), uint32(ARNG_B)) + f.Add(uint64(0x0101), uint32(ARNG_H)) + f.Add(uint64(0x00FF), uint32(ARNG_H)) + f.Add(uint64(0x0000FFFF), uint32(ARNG_S)) + f.Add(uint64(0x55555555), uint32(ARNG_S)) + f.Add(uint64(0x0000FFFF), uint32(ARNG_D)) + f.Add(uint64(0x0101010101010101), uint32(ARNG_D)) + + f.Fuzz(func(t *testing.T, v uint64, arr uint32) { + if arr != ARNG_B && arr != ARNG_H && arr != ARNG_S && arr != ARNG_D { + return + } + adjacentAddr := &obj.Addr{ + Type: obj.TYPE_REG, + Reg: int16(REG_ZARNG) + 0 + (int16(arr) << 5), + } + + encoded, ok := encodeLogicalImmArrEncoding(v, adjacentAddr) + if !ok { + return + } + + imm13 := encoded >> 5 + decoded, ok := decodeLogicalImmArrEncoding(imm13, arr) + if !ok { + t.Errorf("Failed to decode imm13=0x%x arr=%d", imm13, arr) + return + } + + var mask uint64 + switch arr { + case ARNG_B: + mask = 0xFF + case ARNG_H: + mask = 0xFFFF + case ARNG_S: + mask = 0xFFFFFFFF + case ARNG_D: + mask = 0xFFFFFFFFFFFFFFFF + } + expected := v & mask + + if decoded != expected { + t.Errorf("Fuzz roundtrip failed for v=0x%x arr=%d. Expected 0x%x, got 0x%x (imm13=0x%x)", v, arr, expected, decoded, imm13) + } + }) +} diff --git a/src/cmd/internal/obj/arm64/list7.go b/src/cmd/internal/obj/arm64/list7.go index 0654139642e339..bcbd77a27b4d6e 100644 --- a/src/cmd/internal/obj/arm64/list7.go +++ b/src/cmd/internal/obj/arm64/list7.go @@ -90,6 +90,12 @@ func arrange(a int) string { return "D" case ARNG_1Q: return "Q1" + case ARNG_Q: + return "Q" + case PRED_M: + return "M" + case PRED_Z: + return "Z" default: return "" } @@ -109,6 +115,12 @@ func rconv(r int) string { return fmt.Sprintf("F%d", r-REG_F0) case REG_V0 <= r && r <= REG_V31: return fmt.Sprintf("V%d", r-REG_V0) + case REG_Z0 <= r && r <= REG_Z31: + return fmt.Sprintf("Z%d", r-REG_Z0) + case REG_P0 <= r && r <= REG_P15: + return fmt.Sprintf("P%d", r-REG_P0) + case REG_PN0 <= r && r <= REG_PN15: + return fmt.Sprintf("PN%d", r-REG_PN0) case r == REGSP: return "RSP" case REG_UXTB <= r && r < REG_UXTH: @@ -164,8 +176,32 @@ func rconv(r int) string { return fmt.Sprintf("R%d<<%d", r&31, (r>>5)&7) case REG_ARNG <= r && r < REG_ELEM: return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15)) - case REG_ELEM <= r && r < REG_ELEM_END: + case REG_ELEM <= r && r < REG_ZARNG: return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15)) + case REG_ZARNG <= r && r < REG_PZELEM: + return fmt.Sprintf("Z%d.%s", r&31, arrange((r>>5)&15)) + case REG_PZELEM <= r && r < REG_PARNGZM: + regPrefix := "Z" + reg := r & 31 + if r&(1<<5) != 0 { + regPrefix = "P" + if reg >= 16 { + regPrefix = "PN" + reg -= 16 + } + } + return fmt.Sprintf("%s%d", regPrefix, reg) + case REG_PARNGZM <= r && r < REG_PARNGZM_END: + // SVE predicate register with arrangement. + // Pn. or Pn/M, Pn/Z. + arng := (r >> 5) & 15 + suffix := arrange(arng) + reg := r & 31 + if reg >= 16 { + // PN registers + return fmt.Sprintf("PN%d.%s", reg-16, suffix) + } + return fmt.Sprintf("P%d.%s", reg, suffix) } // Return system register name. name, _, _ := SysRegEnc(int16(r)) @@ -193,11 +229,18 @@ func SPCconv(a int64) string { func rlconv(list int64) string { str := "" - // ARM64 register list follows ARM64 instruction decode schema + // For SIMD&FP register list in ARM64, the conv + // follows the ARM64 instruction decode schema // | 31 | 30 | ... | 15 - 12 | 11 - 10 | ... | // +----+----+-----+---------+---------+-----+ // | | Q | ... | opcode | size | ... | + // For Scalable Vector register lists, the conv + // follows: + // | 33 - 32 | 31 - 30 | ... | 15 - 12 | 11 - 10 | ... | 5 - 0 | + // +----+----+----+----+-----+---------+---------+-----+-------+ + // |regprefix| class 1 | ... | reg cnt | class 2 | ... | reg | + firstReg := int(list & 31) opcode := (list >> 12) & 15 var regCnt int @@ -211,11 +254,27 @@ func rlconv(list int64) string { regCnt = 3 case 0x2: regCnt = 4 + case 0x1: + // 5 is the specifier for register range list, size is 1 register + regCnt = 5 + case 0x3: + // 6 is the specifier for register range list, size is 4 register + regCnt = 6 default: regCnt = -1 } // Q:size - arng := ((list>>30)&1)<<2 | (list>>10)&3 + var regPrefix string + regType := (list >> 32) & 3 + switch regType { + case 0: + regPrefix = "V" + case 1: + regPrefix = "Z" + case 2: + regPrefix = "P" + } + arng := ((list>>30)&3)<<2 | (list>>10)&3 switch arng { case 0: t = "B8" @@ -233,17 +292,32 @@ func rlconv(list int64) string { t = "D1" case 7: t = "D2" + case 9: + t = "B" + case 10: + t = "H" + case 11: + t = "S" + case 13: + t = "D" + case 14: + t = "Q" } - for i := 0; i < regCnt; i++ { - if str == "" { - str += "[" - } else { - str += "," + if regCnt > 4 { + rangeSize := 2 << (regCnt - 5) + str = fmt.Sprintf("[%s%d.%s-%s%d.%s]", regPrefix, firstReg, t, regPrefix, (firstReg+rangeSize-1)&31, t) + } else { + for i := 0; i < regCnt; i++ { + if str == "" { + str += "[" + } else { + str += "," + } + str += fmt.Sprintf("%s%d.", regPrefix, (firstReg+i)&31) + str += t } - str += fmt.Sprintf("V%d.", (firstReg+i)&31) - str += t + str += "]" } - str += "]" return str } diff --git a/src/cmd/internal/obj/arm64/specialoperand_string.go b/src/cmd/internal/obj/arm64/specialoperand_string.go index 8fb3e9603e97f0..a8b69d1a31976a 100644 --- a/src/cmd/internal/obj/arm64/specialoperand_string.go +++ b/src/cmd/internal/obj/arm64/specialoperand_string.go @@ -27,143 +27,150 @@ func _() { _ = x[SPOP_PSTL2STRM-15] _ = x[SPOP_PSTL3KEEP-16] _ = x[SPOP_PSTL3STRM-17] - _ = x[SPOP_VMALLE1IS-18] - _ = x[SPOP_VAE1IS-19] - _ = x[SPOP_ASIDE1IS-20] - _ = x[SPOP_VAAE1IS-21] - _ = x[SPOP_VALE1IS-22] - _ = x[SPOP_VAALE1IS-23] - _ = x[SPOP_VMALLE1-24] - _ = x[SPOP_VAE1-25] - _ = x[SPOP_ASIDE1-26] - _ = x[SPOP_VAAE1-27] - _ = x[SPOP_VALE1-28] - _ = x[SPOP_VAALE1-29] - _ = x[SPOP_IPAS2E1IS-30] - _ = x[SPOP_IPAS2LE1IS-31] - _ = x[SPOP_ALLE2IS-32] - _ = x[SPOP_VAE2IS-33] - _ = x[SPOP_ALLE1IS-34] - _ = x[SPOP_VALE2IS-35] - _ = x[SPOP_VMALLS12E1IS-36] - _ = x[SPOP_IPAS2E1-37] - _ = x[SPOP_IPAS2LE1-38] - _ = x[SPOP_ALLE2-39] - _ = x[SPOP_VAE2-40] - _ = x[SPOP_ALLE1-41] - _ = x[SPOP_VALE2-42] - _ = x[SPOP_VMALLS12E1-43] - _ = x[SPOP_ALLE3IS-44] - _ = x[SPOP_VAE3IS-45] - _ = x[SPOP_VALE3IS-46] - _ = x[SPOP_ALLE3-47] - _ = x[SPOP_VAE3-48] - _ = x[SPOP_VALE3-49] - _ = x[SPOP_VMALLE1OS-50] - _ = x[SPOP_VAE1OS-51] - _ = x[SPOP_ASIDE1OS-52] - _ = x[SPOP_VAAE1OS-53] - _ = x[SPOP_VALE1OS-54] - _ = x[SPOP_VAALE1OS-55] - _ = x[SPOP_RVAE1IS-56] - _ = x[SPOP_RVAAE1IS-57] - _ = x[SPOP_RVALE1IS-58] - _ = x[SPOP_RVAALE1IS-59] - _ = x[SPOP_RVAE1OS-60] - _ = x[SPOP_RVAAE1OS-61] - _ = x[SPOP_RVALE1OS-62] - _ = x[SPOP_RVAALE1OS-63] - _ = x[SPOP_RVAE1-64] - _ = x[SPOP_RVAAE1-65] - _ = x[SPOP_RVALE1-66] - _ = x[SPOP_RVAALE1-67] - _ = x[SPOP_RIPAS2E1IS-68] - _ = x[SPOP_RIPAS2LE1IS-69] - _ = x[SPOP_ALLE2OS-70] - _ = x[SPOP_VAE2OS-71] - _ = x[SPOP_ALLE1OS-72] - _ = x[SPOP_VALE2OS-73] - _ = x[SPOP_VMALLS12E1OS-74] - _ = x[SPOP_RVAE2IS-75] - _ = x[SPOP_RVALE2IS-76] - _ = x[SPOP_IPAS2E1OS-77] - _ = x[SPOP_RIPAS2E1-78] - _ = x[SPOP_RIPAS2E1OS-79] - _ = x[SPOP_IPAS2LE1OS-80] - _ = x[SPOP_RIPAS2LE1-81] - _ = x[SPOP_RIPAS2LE1OS-82] - _ = x[SPOP_RVAE2OS-83] - _ = x[SPOP_RVALE2OS-84] - _ = x[SPOP_RVAE2-85] - _ = x[SPOP_RVALE2-86] - _ = x[SPOP_ALLE3OS-87] - _ = x[SPOP_VAE3OS-88] - _ = x[SPOP_VALE3OS-89] - _ = x[SPOP_RVAE3IS-90] - _ = x[SPOP_RVALE3IS-91] - _ = x[SPOP_RVAE3OS-92] - _ = x[SPOP_RVALE3OS-93] - _ = x[SPOP_RVAE3-94] - _ = x[SPOP_RVALE3-95] - _ = x[SPOP_IVAC-96] - _ = x[SPOP_ISW-97] - _ = x[SPOP_CSW-98] - _ = x[SPOP_CISW-99] - _ = x[SPOP_ZVA-100] - _ = x[SPOP_CVAC-101] - _ = x[SPOP_CVAU-102] - _ = x[SPOP_CIVAC-103] - _ = x[SPOP_IGVAC-104] - _ = x[SPOP_IGSW-105] - _ = x[SPOP_IGDVAC-106] - _ = x[SPOP_IGDSW-107] - _ = x[SPOP_CGSW-108] - _ = x[SPOP_CGDSW-109] - _ = x[SPOP_CIGSW-110] - _ = x[SPOP_CIGDSW-111] - _ = x[SPOP_GVA-112] - _ = x[SPOP_GZVA-113] - _ = x[SPOP_CGVAC-114] - _ = x[SPOP_CGDVAC-115] - _ = x[SPOP_CGVAP-116] - _ = x[SPOP_CGDVAP-117] - _ = x[SPOP_CGVADP-118] - _ = x[SPOP_CGDVADP-119] - _ = x[SPOP_CIGVAC-120] - _ = x[SPOP_CIGDVAC-121] - _ = x[SPOP_CVAP-122] - _ = x[SPOP_CVADP-123] - _ = x[SPOP_DAIFSet-124] - _ = x[SPOP_DAIFClr-125] - _ = x[SPOP_EQ-126] - _ = x[SPOP_NE-127] - _ = x[SPOP_HS-128] - _ = x[SPOP_LO-129] - _ = x[SPOP_MI-130] - _ = x[SPOP_PL-131] - _ = x[SPOP_VS-132] - _ = x[SPOP_VC-133] - _ = x[SPOP_HI-134] - _ = x[SPOP_LS-135] - _ = x[SPOP_GE-136] - _ = x[SPOP_LT-137] - _ = x[SPOP_GT-138] - _ = x[SPOP_LE-139] - _ = x[SPOP_AL-140] - _ = x[SPOP_NV-141] - _ = x[SPOP_C-142] - _ = x[SPOP_J-143] - _ = x[SPOP_JC-144] - _ = x[SPOP_END-145] + _ = x[SPOP_VLx2-18] + _ = x[SPOP_VLx4-19] + _ = x[SPOP_VMALLE1IS-20] + _ = x[SPOP_VAE1IS-21] + _ = x[SPOP_ASIDE1IS-22] + _ = x[SPOP_VAAE1IS-23] + _ = x[SPOP_VALE1IS-24] + _ = x[SPOP_VAALE1IS-25] + _ = x[SPOP_VMALLE1-26] + _ = x[SPOP_VAE1-27] + _ = x[SPOP_ASIDE1-28] + _ = x[SPOP_VAAE1-29] + _ = x[SPOP_VALE1-30] + _ = x[SPOP_VAALE1-31] + _ = x[SPOP_IPAS2E1IS-32] + _ = x[SPOP_IPAS2LE1IS-33] + _ = x[SPOP_ALLE2IS-34] + _ = x[SPOP_VAE2IS-35] + _ = x[SPOP_ALLE1IS-36] + _ = x[SPOP_VALE2IS-37] + _ = x[SPOP_VMALLS12E1IS-38] + _ = x[SPOP_IPAS2E1-39] + _ = x[SPOP_IPAS2LE1-40] + _ = x[SPOP_ALLE2-41] + _ = x[SPOP_VAE2-42] + _ = x[SPOP_ALLE1-43] + _ = x[SPOP_VALE2-44] + _ = x[SPOP_VMALLS12E1-45] + _ = x[SPOP_ALLE3IS-46] + _ = x[SPOP_VAE3IS-47] + _ = x[SPOP_VALE3IS-48] + _ = x[SPOP_ALLE3-49] + _ = x[SPOP_VAE3-50] + _ = x[SPOP_VALE3-51] + _ = x[SPOP_VMALLE1OS-52] + _ = x[SPOP_VAE1OS-53] + _ = x[SPOP_ASIDE1OS-54] + _ = x[SPOP_VAAE1OS-55] + _ = x[SPOP_VALE1OS-56] + _ = x[SPOP_VAALE1OS-57] + _ = x[SPOP_RVAE1IS-58] + _ = x[SPOP_RVAAE1IS-59] + _ = x[SPOP_RVALE1IS-60] + _ = x[SPOP_RVAALE1IS-61] + _ = x[SPOP_RVAE1OS-62] + _ = x[SPOP_RVAAE1OS-63] + _ = x[SPOP_RVALE1OS-64] + _ = x[SPOP_RVAALE1OS-65] + _ = x[SPOP_RVAE1-66] + _ = x[SPOP_RVAAE1-67] + _ = x[SPOP_RVALE1-68] + _ = x[SPOP_RVAALE1-69] + _ = x[SPOP_RIPAS2E1IS-70] + _ = x[SPOP_RIPAS2LE1IS-71] + _ = x[SPOP_ALLE2OS-72] + _ = x[SPOP_VAE2OS-73] + _ = x[SPOP_ALLE1OS-74] + _ = x[SPOP_VALE2OS-75] + _ = x[SPOP_VMALLS12E1OS-76] + _ = x[SPOP_RVAE2IS-77] + _ = x[SPOP_RVALE2IS-78] + _ = x[SPOP_IPAS2E1OS-79] + _ = x[SPOP_RIPAS2E1-80] + _ = x[SPOP_RIPAS2E1OS-81] + _ = x[SPOP_IPAS2LE1OS-82] + _ = x[SPOP_RIPAS2LE1-83] + _ = x[SPOP_RIPAS2LE1OS-84] + _ = x[SPOP_RVAE2OS-85] + _ = x[SPOP_RVALE2OS-86] + _ = x[SPOP_RVAE2-87] + _ = x[SPOP_RVALE2-88] + _ = x[SPOP_ALLE3OS-89] + _ = x[SPOP_VAE3OS-90] + _ = x[SPOP_VALE3OS-91] + _ = x[SPOP_RVAE3IS-92] + _ = x[SPOP_RVALE3IS-93] + _ = x[SPOP_RVAE3OS-94] + _ = x[SPOP_RVALE3OS-95] + _ = x[SPOP_RVAE3-96] + _ = x[SPOP_RVALE3-97] + _ = x[SPOP_IVAC-98] + _ = x[SPOP_ISW-99] + _ = x[SPOP_CSW-100] + _ = x[SPOP_CISW-101] + _ = x[SPOP_ZVA-102] + _ = x[SPOP_CVAC-103] + _ = x[SPOP_CVAU-104] + _ = x[SPOP_CIVAC-105] + _ = x[SPOP_IGVAC-106] + _ = x[SPOP_IGSW-107] + _ = x[SPOP_IGDVAC-108] + _ = x[SPOP_IGDSW-109] + _ = x[SPOP_CGSW-110] + _ = x[SPOP_CGDSW-111] + _ = x[SPOP_CIGSW-112] + _ = x[SPOP_CIGDSW-113] + _ = x[SPOP_GVA-114] + _ = x[SPOP_GZVA-115] + _ = x[SPOP_CGVAC-116] + _ = x[SPOP_CGDVAC-117] + _ = x[SPOP_CGVAP-118] + _ = x[SPOP_CGDVAP-119] + _ = x[SPOP_CGVADP-120] + _ = x[SPOP_CGDVADP-121] + _ = x[SPOP_CIGVAC-122] + _ = x[SPOP_CIGDVAC-123] + _ = x[SPOP_CVAP-124] + _ = x[SPOP_CVADP-125] + _ = x[SPOP_DAIFSet-126] + _ = x[SPOP_DAIFClr-127] + _ = x[SPOP_EQ-128] + _ = x[SPOP_NE-129] + _ = x[SPOP_HS-130] + _ = x[SPOP_LO-131] + _ = x[SPOP_MI-132] + _ = x[SPOP_PL-133] + _ = x[SPOP_VS-134] + _ = x[SPOP_VC-135] + _ = x[SPOP_HI-136] + _ = x[SPOP_LS-137] + _ = x[SPOP_GE-138] + _ = x[SPOP_LT-139] + _ = x[SPOP_GT-140] + _ = x[SPOP_LE-141] + _ = x[SPOP_AL-142] + _ = x[SPOP_NV-143] + _ = x[SPOP_C-144] + _ = x[SPOP_J-145] + _ = x[SPOP_JC-146] + _ = x[SPOP_PLDKEEP-147] + _ = x[SPOP_PSTKEEP-148] + _ = x[SPOP_PLDSTRM-149] + _ = x[SPOP_PSTSTRM-150] + _ = x[SPOP_END-151] } -const _SpecialOperand_name = "PLDL1KEEPPLDL1STRMPLDL2KEEPPLDL2STRMPLDL3KEEPPLDL3STRMPLIL1KEEPPLIL1STRMPLIL2KEEPPLIL2STRMPLIL3KEEPPLIL3STRMPSTL1KEEPPSTL1STRMPSTL2KEEPPSTL2STRMPSTL3KEEPPSTL3STRMVMALLE1ISVAE1ISASIDE1ISVAAE1ISVALE1ISVAALE1ISVMALLE1VAE1ASIDE1VAAE1VALE1VAALE1IPAS2E1ISIPAS2LE1ISALLE2ISVAE2ISALLE1ISVALE2ISVMALLS12E1ISIPAS2E1IPAS2LE1ALLE2VAE2ALLE1VALE2VMALLS12E1ALLE3ISVAE3ISVALE3ISALLE3VAE3VALE3VMALLE1OSVAE1OSASIDE1OSVAAE1OSVALE1OSVAALE1OSRVAE1ISRVAAE1ISRVALE1ISRVAALE1ISRVAE1OSRVAAE1OSRVALE1OSRVAALE1OSRVAE1RVAAE1RVALE1RVAALE1RIPAS2E1ISRIPAS2LE1ISALLE2OSVAE2OSALLE1OSVALE2OSVMALLS12E1OSRVAE2ISRVALE2ISIPAS2E1OSRIPAS2E1RIPAS2E1OSIPAS2LE1OSRIPAS2LE1RIPAS2LE1OSRVAE2OSRVALE2OSRVAE2RVALE2ALLE3OSVAE3OSVALE3OSRVAE3ISRVALE3ISRVAE3OSRVALE3OSRVAE3RVALE3IVACISWCSWCISWZVACVACCVAUCIVACIGVACIGSWIGDVACIGDSWCGSWCGDSWCIGSWCIGDSWGVAGZVACGVACCGDVACCGVAPCGDVAPCGVADPCGDVADPCIGVACCIGDVACCVAPCVADPDAIFSetDAIFClrEQNEHSLOMIPLVSVCHILSGELTGTLEALNVCJJCEND" +const _SpecialOperand_name = "PLDL1KEEPPLDL1STRMPLDL2KEEPPLDL2STRMPLDL3KEEPPLDL3STRMPLIL1KEEPPLIL1STRMPLIL2KEEPPLIL2STRMPLIL3KEEPPLIL3STRMPSTL1KEEPPSTL1STRMPSTL2KEEPPSTL2STRMPSTL3KEEPPSTL3STRMVLx2VLx4VMALLE1ISVAE1ISASIDE1ISVAAE1ISVALE1ISVAALE1ISVMALLE1VAE1ASIDE1VAAE1VALE1VAALE1IPAS2E1ISIPAS2LE1ISALLE2ISVAE2ISALLE1ISVALE2ISVMALLS12E1ISIPAS2E1IPAS2LE1ALLE2VAE2ALLE1VALE2VMALLS12E1ALLE3ISVAE3ISVALE3ISALLE3VAE3VALE3VMALLE1OSVAE1OSASIDE1OSVAAE1OSVALE1OSVAALE1OSRVAE1ISRVAAE1ISRVALE1ISRVAALE1ISRVAE1OSRVAAE1OSRVALE1OSRVAALE1OSRVAE1RVAAE1RVALE1RVAALE1RIPAS2E1ISRIPAS2LE1ISALLE2OSVAE2OSALLE1OSVALE2OSVMALLS12E1OSRVAE2ISRVALE2ISIPAS2E1OSRIPAS2E1RIPAS2E1OSIPAS2LE1OSRIPAS2LE1RIPAS2LE1OSRVAE2OSRVALE2OSRVAE2RVALE2ALLE3OSVAE3OSVALE3OSRVAE3ISRVALE3ISRVAE3OSRVALE3OSRVAE3RVALE3IVACISWCSWCISWZVACVACCVAUCIVACIGVACIGSWIGDVACIGDSWCGSWCGDSWCIGSWCIGDSWGVAGZVACGVACCGDVACCGVAPCGDVAPCGVADPCGDVADPCIGVACCIGDVACCVAPCVADPDAIFSetDAIFClrEQNEHSLOMIPLVSVCHILSGELTGTLEALNVCJJCPLDKEEPPSTKEEPPLDSTRMPSTSTRMEND" -var _SpecialOperand_index = [...]uint16{0, 9, 18, 27, 36, 45, 54, 63, 72, 81, 90, 99, 108, 117, 126, 135, 144, 153, 162, 171, 177, 185, 192, 199, 207, 214, 218, 224, 229, 234, 240, 249, 259, 266, 272, 279, 286, 298, 305, 313, 318, 322, 327, 332, 342, 349, 355, 362, 367, 371, 376, 385, 391, 399, 406, 413, 421, 428, 436, 444, 453, 460, 468, 476, 485, 490, 496, 502, 509, 519, 530, 537, 543, 550, 557, 569, 576, 584, 593, 601, 611, 621, 630, 641, 648, 656, 661, 667, 674, 680, 687, 694, 702, 709, 717, 722, 728, 732, 735, 738, 742, 745, 749, 753, 758, 763, 767, 773, 778, 782, 787, 792, 798, 801, 805, 810, 816, 821, 827, 833, 840, 846, 853, 857, 862, 869, 876, 878, 880, 882, 884, 886, 888, 890, 892, 894, 896, 898, 900, 902, 904, 906, 908, 909, 910, 912, 915} +var _SpecialOperand_index = [...]uint16{0, 9, 18, 27, 36, 45, 54, 63, 72, 81, 90, 99, 108, 117, 126, 135, 144, 153, 162, 166, 170, 179, 185, 193, 200, 207, 215, 222, 226, 232, 237, 242, 248, 257, 267, 274, 280, 287, 294, 306, 313, 321, 326, 330, 335, 340, 350, 357, 363, 370, 375, 379, 384, 393, 399, 407, 414, 421, 429, 436, 444, 452, 461, 468, 476, 484, 493, 498, 504, 510, 517, 527, 538, 545, 551, 558, 565, 577, 584, 592, 601, 609, 619, 629, 638, 649, 656, 664, 669, 675, 682, 688, 695, 702, 710, 717, 725, 730, 736, 740, 743, 746, 750, 753, 757, 761, 766, 771, 775, 781, 786, 790, 795, 800, 806, 809, 813, 818, 824, 829, 835, 841, 848, 854, 861, 865, 870, 877, 884, 886, 888, 890, 892, 894, 896, 898, 900, 902, 904, 906, 908, 910, 912, 914, 916, 917, 918, 920, 927, 934, 941, 948, 951} func (i SpecialOperand) String() string { - if i < 0 || i >= SpecialOperand(len(_SpecialOperand_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_SpecialOperand_index)-1 { return "SpecialOperand(" + strconv.FormatInt(int64(i), 10) + ")" } - return _SpecialOperand_name[_SpecialOperand_index[i]:_SpecialOperand_index[i+1]] + return _SpecialOperand_name[_SpecialOperand_index[idx]:_SpecialOperand_index[idx+1]] } diff --git a/src/cmd/internal/obj/data.go b/src/cmd/internal/obj/data.go index 73669a15b9dbf0..384f0348e961f1 100644 --- a/src/cmd/internal/obj/data.go +++ b/src/cmd/internal/obj/data.go @@ -71,13 +71,12 @@ func (s *LSym) prepwrite(ctxt *Link, off int64, siz int) { switch s.Type { case objabi.Sxxx, objabi.SBSS: s.Type = objabi.SDATA - s.setFIPSType(ctxt) case objabi.SNOPTRBSS: s.Type = objabi.SNOPTRDATA - s.setFIPSType(ctxt) case objabi.STLSBSS: ctxt.Diag("cannot supply data for %v var %v", s.Type, s.Name) } + s.setFIPSType(ctxt) l := off + int64(siz) s.Grow(l) if l > s.Size { diff --git a/src/cmd/internal/obj/dwarf.go b/src/cmd/internal/obj/dwarf.go index 670b0f3510f8c2..1332efe4cc5049 100644 --- a/src/cmd/internal/obj/dwarf.go +++ b/src/cmd/internal/obj/dwarf.go @@ -231,7 +231,7 @@ func (c dwCtxt) AddString(s dwarf.Sym, v string) { ls.WriteString(c.Link, ls.Size, len(v), v) ls.WriteInt(c.Link, ls.Size, 1, 0) } -func (c dwCtxt) AddAddress(s dwarf.Sym, data interface{}, value int64) { +func (c dwCtxt) AddAddress(s dwarf.Sym, data any, value int64) { ls := s.(*LSym) size := c.PtrSize() if data != nil { @@ -241,15 +241,15 @@ func (c dwCtxt) AddAddress(s dwarf.Sym, data interface{}, value int64) { ls.WriteInt(c.Link, ls.Size, size, value) } } -func (c dwCtxt) AddCURelativeAddress(s dwarf.Sym, data interface{}, value int64) { +func (c dwCtxt) AddCURelativeAddress(s dwarf.Sym, data any, value int64) { ls := s.(*LSym) rsym := data.(*LSym) ls.WriteCURelativeAddr(c.Link, ls.Size, rsym, value) } -func (c dwCtxt) AddSectionOffset(s dwarf.Sym, size int, t interface{}, ofs int64) { +func (c dwCtxt) AddSectionOffset(s dwarf.Sym, size int, t any, ofs int64) { panic("should be used only in the linker") } -func (c dwCtxt) AddDWARFAddrSectionOffset(s dwarf.Sym, t interface{}, ofs int64) { +func (c dwCtxt) AddDWARFAddrSectionOffset(s dwarf.Sym, t any, ofs int64) { size := 4 if isDwarf64(c.Link) { size = 8 @@ -284,11 +284,11 @@ func (c dwCtxt) RecordChildDieOffsets(s dwarf.Sym, vars []*dwarf.Var, offsets [] c.Link.DwFixups.RegisterChildDIEOffsets(ls, vars, offsets) } -func (c dwCtxt) Logf(format string, args ...interface{}) { +func (c dwCtxt) Logf(format string, args ...any) { c.Link.Logf(format, args...) } -func (c dwCtxt) AddIndirectTextRef(s dwarf.Sym, t interface{}) { +func (c dwCtxt) AddIndirectTextRef(s dwarf.Sym, t any) { ls := s.(*LSym) tsym := t.(*LSym) // Note the doubling below -- DwTextCount is an estimate and @@ -363,7 +363,7 @@ func (ctxt *Link) populateDWARF(curfn Func, s *LSym) { panic("bad startPos") } fnstate := &dwarf.FnState{ - Name: s.Name, + Name: TrimInlineHash(s.Name), Info: info, Loc: loc, Ranges: ranges, @@ -435,7 +435,7 @@ func (ctxt *Link) DwarfAbstractFunc(curfn Func, s *LSym) { scopes, _ := ctxt.DebugInfo(ctxt, s, absfn, curfn) dwctxt := dwCtxt{ctxt} fnstate := dwarf.FnState{ - Name: s.Name, + Name: TrimInlineHash(s.Name), Info: absfn, Absfn: absfn, StartPos: ctxt.InnermostPos(curfn.Pos()), diff --git a/src/cmd/internal/obj/fips140.go b/src/cmd/internal/obj/fips140.go index da18b641786718..0e4f2a47a38126 100644 --- a/src/cmd/internal/obj/fips140.go +++ b/src/cmd/internal/obj/fips140.go @@ -354,17 +354,22 @@ func (s *LSym) checkFIPSReloc(ctxt *Link, rel Reloc) { objabi.R_CALLLOONG64, objabi.R_CALLPOWER, objabi.R_GOTPCREL, - objabi.R_LOONG64_ADDR_LO, // used with PC-relative load - objabi.R_LOONG64_ADDR_HI, // used with PC-relative load + objabi.R_LOONG64_ADDR_LO, // used with PC-relative load + objabi.R_LOONG64_ADDR_HI, // used with PC-relative load + objabi.R_LOONG64_ADDR64_LO, // used with PC-relative load + objabi.R_LOONG64_ADDR64_HI, // used with PC-relative load + objabi.R_LOONG64_ADDR_PCREL20_S2, // used with PC-relative load + objabi.R_LOONG64_CALL36, objabi.R_LOONG64_TLS_LE_HI, objabi.R_LOONG64_TLS_LE_LO, objabi.R_LOONG64_TLS_IE_HI, objabi.R_LOONG64_TLS_IE_LO, objabi.R_LOONG64_GOT_HI, objabi.R_LOONG64_GOT_LO, + objabi.R_LOONG64_GOT64_HI, + objabi.R_LOONG64_GOT64_LO, objabi.R_JMP16LOONG64, objabi.R_JMP21LOONG64, - objabi.R_JMPLOONG64, objabi.R_PCREL, objabi.R_PCRELDBL, objabi.R_POWER_TLS_LE, diff --git a/src/cmd/internal/obj/inl.go b/src/cmd/internal/obj/inl.go index 6874471891d927..7b6f07b6f75086 100644 --- a/src/cmd/internal/obj/inl.go +++ b/src/cmd/internal/obj/inl.go @@ -89,6 +89,14 @@ func (tree *InlTree) InlinedFunction(inlIndex int) *LSym { return tree.nodes[inlIndex].Func } +func (tree *InlTree) InlinedFuncName(inlIndex int) string { + return tree.nodes[inlIndex].Name +} + +func (tree *InlTree) InlinedFuncPkg(inlIndex int) string { + return tree.nodes[inlIndex].Func.Pkg +} + func (tree *InlTree) CallPos(inlIndex int) src.XPos { return tree.nodes[inlIndex].Pos } diff --git a/src/cmd/internal/obj/line_test.go b/src/cmd/internal/obj/line_test.go index de7ef1a22eb1c9..2cf3d3088b1bd5 100644 --- a/src/cmd/internal/obj/line_test.go +++ b/src/cmd/internal/obj/line_test.go @@ -12,7 +12,6 @@ import ( func TestGetFileSymbolAndLine(t *testing.T) { ctxt := new(Link) - ctxt.hash = make(map[string]*LSym) ctxt.statichash = make(map[string]*LSym) afile := src.NewFileBase("a.go", "a.go") diff --git a/src/cmd/internal/obj/link.go b/src/cmd/internal/obj/link.go index 9f3814e748aa5f..d35c4154c7387a 100644 --- a/src/cmd/internal/obj/link.go +++ b/src/cmd/internal/obj/link.go @@ -211,7 +211,7 @@ type Addr struct { // for TYPE_FCONST, a float64 // for TYPE_BRANCH, a *Prog (optional) // for TYPE_TEXTSIZE, an int32 (optional) - Val interface{} + Val any } type AddrName int8 @@ -456,15 +456,16 @@ const ( // It represents Go symbols in a flat pkg+"."+name namespace. type LSym struct { Name string - Type objabi.SymKind Attribute + Type objabi.SymKind + Align int16 Size int64 Gotype *LSym P []byte R []Reloc - Extra *interface{} // *FuncInfo, *VarInfo, *FileInfo, *TypeInfo, or *ItabInfo, if present + Extra *any // *FuncInfo, *VarInfo, *FileInfo, *TypeInfo, or *ItabInfo, if present Pkg string PkgIdx int32 @@ -475,7 +476,6 @@ type LSym struct { type FuncInfo struct { Args int32 Locals int32 - Align int32 FuncID abi.FuncID FuncFlag abi.FuncFlag StartLine int32 @@ -523,7 +523,7 @@ func (s *LSym) NewFuncInfo() *FuncInfo { panic(fmt.Sprintf("invalid use of LSym - NewFuncInfo with Extra of type %T", *s.Extra)) } f := new(FuncInfo) - s.Extra = new(interface{}) + s.Extra = new(any) *s.Extra = f return f } @@ -547,7 +547,7 @@ func (s *LSym) NewVarInfo() *VarInfo { panic(fmt.Sprintf("invalid use of LSym - NewVarInfo with Extra of type %T", *s.Extra)) } f := new(VarInfo) - s.Extra = new(interface{}) + s.Extra = new(any) *s.Extra = f return f } @@ -574,7 +574,7 @@ func (s *LSym) NewFileInfo() *FileInfo { panic(fmt.Sprintf("invalid use of LSym - NewFileInfo with Extra of type %T", *s.Extra)) } f := new(FileInfo) - s.Extra = new(interface{}) + s.Extra = new(any) *s.Extra = f return f } @@ -591,7 +591,7 @@ func (s *LSym) File() *FileInfo { // A TypeInfo contains information for a symbol // that contains a runtime._type. type TypeInfo struct { - Type interface{} // a *cmd/compile/internal/types.Type + Type any // a *cmd/compile/internal/types.Type } func (s *LSym) NewTypeInfo() *TypeInfo { @@ -599,7 +599,7 @@ func (s *LSym) NewTypeInfo() *TypeInfo { panic(fmt.Sprintf("invalid use of LSym - NewTypeInfo with Extra of type %T", *s.Extra)) } t := new(TypeInfo) - s.Extra = new(interface{}) + s.Extra = new(any) *s.Extra = t return t } @@ -616,7 +616,7 @@ func (s *LSym) TypeInfo() *TypeInfo { // An ItabInfo contains information for a symbol // that contains a runtime.itab. type ItabInfo struct { - Type interface{} // a *cmd/compile/internal/types.Type + Type any // a *cmd/compile/internal/types.Type } func (s *LSym) NewItabInfo() *ItabInfo { @@ -624,7 +624,7 @@ func (s *LSym) NewItabInfo() *ItabInfo { panic(fmt.Sprintf("invalid use of LSym - NewItabInfo with Extra of type %T", *s.Extra)) } t := new(ItabInfo) - s.Extra = new(interface{}) + s.Extra = new(any) *s.Extra = t return t } @@ -799,6 +799,7 @@ const ( WasmF32 WasmF64 WasmPtr + WasmV128 // bool is not really a wasm type, but we allow it on wasmimport/wasmexport // function parameters/results. 32-bit on Wasm side, 8-bit on Go side. @@ -977,6 +978,9 @@ const ( // Linkname indicates this is a go:linkname'd symbol. AttrLinkname + // LinknameStd indicates this is a go:linknamestd'd symbol. + AttrLinknameStd + // attrABIBase is the value at which the ABI is encoded in // Attribute. This must be last; all bits after this are // assumed to be an ABI value. @@ -1007,6 +1011,7 @@ func (a *Attribute) ABIWrapper() bool { return a.load()&AttrABIWrapper ! func (a *Attribute) IsPcdata() bool { return a.load()&AttrPcdata != 0 } func (a *Attribute) IsPkgInit() bool { return a.load()&AttrPkgInit != 0 } func (a *Attribute) IsLinkname() bool { return a.load()&AttrLinkname != 0 } +func (a *Attribute) IsLinknameStd() bool { return a.load()&AttrLinknameStd != 0 } func (a *Attribute) Set(flag Attribute, value bool) { for { @@ -1057,6 +1062,7 @@ var textAttrStrings = [...]struct { {bit: AttrABIWrapper, s: "ABIWRAPPER"}, {bit: AttrPkgInit, s: "PKGINIT"}, {bit: AttrLinkname, s: "LINKNAME"}, + {bit: AttrLinknameStd, s: "LINKNAMESTD"}, } // String formats a for printing in as part of a TEXT prog. @@ -1153,36 +1159,38 @@ type Func interface { // Link holds the context for writing object code from a compiler // to be linker input or for reading that input into the linker. type Link struct { - Headtype objabi.HeadType - Arch *LinkArch - Debugasm int - Debugvlog bool - Debugpcln string - Flag_shared bool - Flag_dynlink bool - Flag_linkshared bool - Flag_optimize bool - Flag_locationlists bool - Flag_noRefName bool // do not include referenced symbol names in object file - Retpoline bool // emit use of retpoline stubs for indirect jmp/call - Flag_maymorestack string // If not "", call this function before stack checks - Bso *bufio.Writer - Pathname string - Pkgpath string // the current package's import path - hashmu sync.Mutex // protects hash, funchash - hash map[string]*LSym // name -> sym mapping - funchash map[string]*LSym // name -> sym mapping for ABIInternal syms - statichash map[string]*LSym // name -> sym mapping for static syms - PosTable src.PosTable - InlTree InlTree // global inlining tree used by gc/inl.go - DwFixups *DwarfFixupTable - DwTextCount int - Imports []goobj.ImportedPkg - DiagFunc func(string, ...interface{}) - DiagFlush func() - DebugInfo func(ctxt *Link, fn *LSym, info *LSym, curfn Func) ([]dwarf.Scope, dwarf.InlCalls) - GenAbstractFunc func(fn *LSym) - Errors int + Headtype objabi.HeadType + Arch *LinkArch + CompressInstructions bool // use compressed instructions where possible (if supported by architecture) + Debugasm int + Debugvlog bool + Debugpcln string + Flag_shared bool + Flag_dynlink bool + Flag_linkshared bool + Flag_optimize bool + Flag_locationlists bool + Flag_noRefName bool // do not include referenced symbol names in object file + Retpoline bool // emit use of retpoline stubs for indirect jmp/call + Flag_maymorestack string // If not "", call this function before stack checks + Bso *bufio.Writer + Pathname string + Pkgpath string // the current package's import path + + hashmu sync.Mutex // protects hash, funchash + hash sync.Map // name(string) -> sym(*syncOnce) mapping + funchash sync.Map // name(string) -> sym(*syncOnce) mapping for ABIInternal syms + statichash map[string]*LSym // name -> sym mapping for static syms + PosTable src.PosTable + InlTree InlTree // global inlining tree used by gc/inl.go + DwFixups *DwarfFixupTable + DwTextCount int + Imports []goobj.ImportedPkg + DiagFunc func(string, ...any) + DiagFlush func() + DebugInfo func(ctxt *Link, fn *LSym, info *LSym, curfn Func) ([]dwarf.Scope, dwarf.InlCalls) + GenAbstractFunc func(fn *LSym) + Errors int InParallel bool // parallel backend phase in effect UseBASEntries bool // use Base Address Selection Entries in location lists and PC ranges @@ -1216,6 +1224,13 @@ type Link struct { Fingerprint goobj.FingerprintType // fingerprint of symbol indices, to catch index mismatch } +// symOnce is a "marker" value for our sync.Maps. We insert it on lookup and +// use the atomic value to check whether initialization has been completed. +type symOnce struct { + sym LSym + inited atomic.Bool +} + // Assert to vet's printf checker that Link.DiagFunc is a printf-like. func _(ctxt *Link) { ctxt.DiagFunc = func(format string, args ...any) { @@ -1223,12 +1238,12 @@ func _(ctxt *Link) { } } -func (ctxt *Link) Diag(format string, args ...interface{}) { +func (ctxt *Link) Diag(format string, args ...any) { ctxt.Errors++ ctxt.DiagFunc(format, args...) } -func (ctxt *Link) Logf(format string, args ...interface{}) { +func (ctxt *Link) Logf(format string, args ...any) { fmt.Fprintf(ctxt.Bso, format, args...) ctxt.Bso.Flush() } diff --git a/src/cmd/internal/obj/loong64/a.out.go b/src/cmd/internal/obj/loong64/a.out.go deleted file mode 100644 index 3cdbeb12a37395..00000000000000 --- a/src/cmd/internal/obj/loong64/a.out.go +++ /dev/null @@ -1,1158 +0,0 @@ -// Copyright 2022 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -package loong64 - -import ( - "cmd/internal/obj" -) - -//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64 - -const ( - NSNAME = 8 - NSYM = 50 - NREG = 32 // number of general registers - NFREG = 32 // number of floating point registers - NVREG = 32 // number of LSX registers - NXREG = 32 // number of LASX registers -) - -const ( - REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32 - REG_R1 - REG_R2 - REG_R3 - REG_R4 - REG_R5 - REG_R6 - REG_R7 - REG_R8 - REG_R9 - REG_R10 - REG_R11 - REG_R12 - REG_R13 - REG_R14 - REG_R15 - REG_R16 - REG_R17 - REG_R18 - REG_R19 - REG_R20 - REG_R21 - REG_R22 - REG_R23 - REG_R24 - REG_R25 - REG_R26 - REG_R27 - REG_R28 - REG_R29 - REG_R30 - REG_R31 - - REG_F0 // must be a multiple of 32 - REG_F1 - REG_F2 - REG_F3 - REG_F4 - REG_F5 - REG_F6 - REG_F7 - REG_F8 - REG_F9 - REG_F10 - REG_F11 - REG_F12 - REG_F13 - REG_F14 - REG_F15 - REG_F16 - REG_F17 - REG_F18 - REG_F19 - REG_F20 - REG_F21 - REG_F22 - REG_F23 - REG_F24 - REG_F25 - REG_F26 - REG_F27 - REG_F28 - REG_F29 - REG_F30 - REG_F31 - - REG_FCSR0 // must be a multiple of 32 - REG_FCSR1 - REG_FCSR2 - REG_FCSR3 // only four registers are needed - REG_FCSR4 - REG_FCSR5 - REG_FCSR6 - REG_FCSR7 - REG_FCSR8 - REG_FCSR9 - REG_FCSR10 - REG_FCSR11 - REG_FCSR12 - REG_FCSR13 - REG_FCSR14 - REG_FCSR15 - REG_FCSR16 - REG_FCSR17 - REG_FCSR18 - REG_FCSR19 - REG_FCSR20 - REG_FCSR21 - REG_FCSR22 - REG_FCSR23 - REG_FCSR24 - REG_FCSR25 - REG_FCSR26 - REG_FCSR27 - REG_FCSR28 - REG_FCSR29 - REG_FCSR30 - REG_FCSR31 - - REG_FCC0 // must be a multiple of 32 - REG_FCC1 - REG_FCC2 - REG_FCC3 - REG_FCC4 - REG_FCC5 - REG_FCC6 - REG_FCC7 // only eight registers are needed - REG_FCC8 - REG_FCC9 - REG_FCC10 - REG_FCC11 - REG_FCC12 - REG_FCC13 - REG_FCC14 - REG_FCC15 - REG_FCC16 - REG_FCC17 - REG_FCC18 - REG_FCC19 - REG_FCC20 - REG_FCC21 - REG_FCC22 - REG_FCC23 - REG_FCC24 - REG_FCC25 - REG_FCC26 - REG_FCC27 - REG_FCC28 - REG_FCC29 - REG_FCC30 - REG_FCC31 - - // LSX: 128-bit vector register - REG_V0 - REG_V1 - REG_V2 - REG_V3 - REG_V4 - REG_V5 - REG_V6 - REG_V7 - REG_V8 - REG_V9 - REG_V10 - REG_V11 - REG_V12 - REG_V13 - REG_V14 - REG_V15 - REG_V16 - REG_V17 - REG_V18 - REG_V19 - REG_V20 - REG_V21 - REG_V22 - REG_V23 - REG_V24 - REG_V25 - REG_V26 - REG_V27 - REG_V28 - REG_V29 - REG_V30 - REG_V31 - - // LASX: 256-bit vector register - REG_X0 - REG_X1 - REG_X2 - REG_X3 - REG_X4 - REG_X5 - REG_X6 - REG_X7 - REG_X8 - REG_X9 - REG_X10 - REG_X11 - REG_X12 - REG_X13 - REG_X14 - REG_X15 - REG_X16 - REG_X17 - REG_X18 - REG_X19 - REG_X20 - REG_X21 - REG_X22 - REG_X23 - REG_X24 - REG_X25 - REG_X26 - REG_X27 - REG_X28 - REG_X29 - REG_X30 - REG_X31 - - REG_SPECIAL = REG_FCSR0 - - REGZERO = REG_R0 // set to zero - REGLINK = REG_R1 - REGSP = REG_R3 - REGCTXT = REG_R29 // context for closures - REGG = REG_R22 // G in loong64 - REGTMP = REG_R30 // used by the assembler - FREGRET = REG_F0 // not use -) - -var LOONG64DWARFRegisters = map[int16]int16{} - -func init() { - // f assigns dwarfregisters[from:to] = (base):(to-from+base) - f := func(from, to, base int16) { - for r := from; r <= to; r++ { - LOONG64DWARFRegisters[r] = (r - from) + base - } - } - f(REG_R0, REG_R31, 0) - f(REG_F0, REG_F31, 32) - - // The lower bits of V and X registers are alias to F registers - f(REG_V0, REG_V31, 32) - f(REG_X0, REG_X31, 32) -} - -const ( - BIG = 2046 -) - -const ( - // mark flags - LABEL = 1 << 0 - LEAF = 1 << 1 - SYNC = 1 << 2 - BRANCH = 1 << 3 -) - -// Arrangement for Loong64 SIMD instructions -const ( - // arrangement types - ARNG_32B int16 = iota - ARNG_16H - ARNG_8W - ARNG_4V - ARNG_2Q - ARNG_16B - ARNG_8H - ARNG_4W - ARNG_2V - ARNG_B - ARNG_H - ARNG_W - ARNG_V - ARNG_BU - ARNG_HU - ARNG_WU - ARNG_VU -) - -// LoongArch64 SIMD extension type -const ( - LSX int16 = iota - LASX -) - -// bits 0-4 indicates register: Vn or Xn -// bits 5-9 indicates arrangement: -// bits 10 indicates SMID type: 0: LSX, 1: LASX -const ( - REG_ARNG = obj.RBaseLOONG64 + (1 << 10) + (iota << 11) // Vn. - REG_ELEM // Vn.[index] - REG_ELEM_END -) - -const ( - EXT_REG_SHIFT = 0 - EXT_REG_MASK = 0x1f - - EXT_TYPE_SHIFT = 5 - EXT_TYPE_MASK = 0x1f - - EXT_SIMDTYPE_SHIFT = 10 - EXT_SIMDTYPE_MASK = 0x1 -) - -const ( - REG_LAST = REG_ELEM_END // the last defined register -) - -//go:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64 -const ( - C_NONE = iota - C_REG - C_FREG - C_FCSRREG - C_FCCREG - C_VREG - C_XREG - C_ARNG // Vn. - C_ELEM // Vn.[index] - - C_ZCON - C_U1CON // 1 bit unsigned constant - C_U2CON // 2 bit unsigned constant - C_U3CON // 3 bit unsigned constant - C_U4CON // 4 bit unsigned constant - C_U5CON // 5 bit unsigned constant - C_U6CON // 6 bit unsigned constant - C_U7CON // 7 bit unsigned constant - C_U8CON // 8 bit unsigned constant - C_S5CON // 5 bit signed constant - C_US12CON // same as C_S12CON, increase the priority of C_S12CON in special cases. - C_UU12CON // same as C_U12CON, increase the priority of C_U12CON in special cases. - C_S12CON // 12 bit signed constant, -0x800 < v <= 0x7ff - C_U12CON // 12 bit unsigned constant, 0 < v <= 0xfff - C_12CON // 12 bit signed constant, or 12 bit unsigned constant - C_S13CON20_0 // 13 bit signed constant, low 12 bits 0 - C_S13CON // 13 bit signed constant - C_U13CON20_0 // 13 bit unsigned constant, low 12 bits 0 - C_U13CON // 13 bit unsigned constant - C_13CON // 13 bit signed constant, or 13 bit unsigned constant - C_U15CON // 15 bit unsigned constant - C_U15CON20_0 // 15 bit unsigned constant, low 12 bits 0 - C_32CON20_0 // 32 bit signed, low 12 bits 0 - C_32CON // other 32 bit signed - - // 64 bit signed, lo32 bits 0, hi20 bits are not 0, hi12 bits can - // be obtained by sign extension of the hi20 bits. - C_DCON20S_0 - // 64 bit signed, lo52 bits 0, hi12 bits are not 0. - C_DCON12_0 - // 64 bit signed, lo32 bits 0, hi32 bits are not 0. - C_DCON32_0 - // 64 bit signed, lo12 bits 0, lo20 bits are not 0, hi20 bits can be - // obtained by sign extension of the lo20 bits, other bits are not 0. - C_DCON12_20S - // 64 bit signed, lo12 bits 0, hi20 bits are not 0, hi12 bits can be - // obtained by sign extension of the hi20 bits, other bits are not 0. - C_DCON20S_20 - // 64 bit signed, lo12 bits 0, other bits are not 0. - C_DCON32_20 - // 64 bit signed, lo12 bits are not 0, 12~51 bits can be obtained - // by sign extension of the lo12 bits, other bits are not 0. - C_DCON12_12S - // 64 bit signed, hi20 bits and lo12 bits are not 0, hi12 bits can - // be obtained by sign extension of the hi20 bits, lo20 bits can - // be obtained by sign extension of the lo12 bits. - C_DCON20S_12S - // 64 bit signed, lo12 bits are not 0, lo20 bits can be obtained by sign - // extension of the lo12 bits, other bits are not 0. - C_DCON32_12S - // 64 bit signed, lo20 and lo12 bits are not 0, hi20 bits can be obtained by sign - // extension of the lo20 bits. other bits are not 0. - C_DCON12_32S - // 64 bit signed, hi20 bits are not 0, hi12 bits can be obtained by sign - // extension of the hi20 bits, lo32 bits are not 0. - C_DCON20S_32 - // 64 bit signed, 12~51 bits 0, other bits are not 0. - C_DCON12_12U - // 64 bit signed, lo20 bits 0, hi20 bits are not 0, hi12 bits can be - // obtained by sign extension of the hi20 bits, lo12 bits are not 0. - C_DCON20S_12U - // 64 bit signed, lo20 bits 0, other bits are not 0. - C_DCON32_12U - // other 64 - C_DCON - - C_SACON // $n(REG) where n <= int12 - C_LACON // $n(REG) where int12 < n <= int32 - C_DACON // $n(REG) where int32 < n - C_EXTADDR // external symbol address - C_BRAN - C_SAUTO - C_LAUTO - C_ZOREG - C_SOREG - C_LOREG - C_ROFF // register offset - C_ADDR - C_TLS_LE - C_TLS_IE - C_GOTADDR - C_TEXTSIZE - - C_GOK - C_NCLASS // must be the last -) - -const ( - AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota - AABSF - AADD - AADDD - AADDF - AADDU - - AADDW - AAND - ABEQ - ABGEZ - ABLEZ - ABGTZ - ABLTZ - ABFPF - ABFPT - - ABNE - ABREAK - - ACMPEQD - ACMPEQF - - ACMPGED // ACMPGED -> fcmp.sle.d - ACMPGEF // ACMPGEF -> fcmp.sle.s - ACMPGTD // ACMPGTD -> fcmp.slt.d - ACMPGTF // ACMPGTF -> fcmp.slt.s - - ALU12IW - ALU32ID - ALU52ID - APCALAU12I - APCADDU12I - AJIRL - ABGE - ABLT - ABLTU - ABGEU - - ADIV - ADIVD - ADIVF - ADIVU - ADIVW - - ALL - ALLV - - ALUI - - AMOVB - AMOVBU - - AMOVD - AMOVDF - AMOVDW - AMOVF - AMOVFD - AMOVFW - - AMOVH - AMOVHU - AMOVW - - AMOVWD - AMOVWF - - AMUL - AMULD - AMULF - AMULU - AMULH - AMULHU - AMULW - ANEGD - ANEGF - - ANEGW - ANEGV - - ANOOP // hardware nop - ANOR - AOR - AREM - AREMU - - ARFE - - ASC - ASCV - - ASGT - ASGTU - - ASLL - ASQRTD - ASQRTF - ASRA - ASRL - AROTR - ASUB - ASUBD - ASUBF - - ASUBU - ASUBW - ADBAR - ASYSCALL - - ATEQ - ATNE - - AWORD - - AXOR - - AMASKEQZ - AMASKNEZ - - // 64-bit - AMOVV - - ASLLV - ASRAV - ASRLV - AROTRV - ADIVV - ADIVVU - - AREMV - AREMVU - - AMULV - AMULVU - AMULHV - AMULHVU - AADDV - AADDVU - ASUBV - ASUBVU - - // 64-bit FP - ATRUNCFV - ATRUNCDV - ATRUNCFW - ATRUNCDW - - AMOVWU - AMOVFV - AMOVDV - AMOVVF - AMOVVD - - // 2.2.1.2 - AADDV16 - - // 2.2.1.3 - AALSLW - AALSLWU - AALSLV - - // 2.2.1.8 - AORN - AANDN - - // 2.2.7. Atomic Memory Access Instructions - AAMSWAPB - AAMSWAPH - AAMSWAPW - AAMSWAPV - AAMCASB - AAMCASH - AAMCASW - AAMCASV - AAMADDW - AAMADDV - AAMANDW - AAMANDV - AAMORW - AAMORV - AAMXORW - AAMXORV - AAMMAXW - AAMMAXV - AAMMINW - AAMMINV - AAMMAXWU - AAMMAXVU - AAMMINWU - AAMMINVU - AAMSWAPDBB - AAMSWAPDBH - AAMSWAPDBW - AAMSWAPDBV - AAMCASDBB - AAMCASDBH - AAMCASDBW - AAMCASDBV - AAMADDDBW - AAMADDDBV - AAMANDDBW - AAMANDDBV - AAMORDBW - AAMORDBV - AAMXORDBW - AAMXORDBV - AAMMAXDBW - AAMMAXDBV - AAMMINDBW - AAMMINDBV - AAMMAXDBWU - AAMMAXDBVU - AAMMINDBWU - AAMMINDBVU - - // 2.2.3.1 - AEXTWB - AEXTWH - - // 2.2.3.2 - ACLOW - ACLOV - ACLZW - ACLZV - ACTOW - ACTOV - ACTZW - ACTZV - - // 2.2.3.4 - AREVBV - AREVB2W - AREVB4H - AREVB2H - - // 2.2.3.5 - AREVH2W - AREVHV - - // 2.2.3.6 - ABITREV4B - ABITREV8B - - // 2.2.3.7 - ABITREVW - ABITREVV - - // 2.2.3.8 - ABSTRINSW - ABSTRINSV - - // 2.2.3.9 - ABSTRPICKW - ABSTRPICKV - - // 2.2.5.3 - AMOVWP - AMOVVP - - // 2.2.5.4. Prefetch Instructions - APRELD - APRELDX - - // 2.2.9. CRC Check Instructions - ACRCWBW - ACRCWHW - ACRCWWW - ACRCWVW - ACRCCWBW - ACRCCWHW - ACRCCWWW - ACRCCWVW - - // 2.2.10. Other Miscellaneous Instructions - ARDTIMELW - ARDTIMEHW - ARDTIMED - ACPUCFG - - // 3.2.1.2 - AFMADDF - AFMADDD - AFMSUBF - AFMSUBD - AFNMADDF - AFNMADDD - AFNMSUBF - AFNMSUBD - - // 3.2.1.3 - AFMINF - AFMIND - AFMAXF - AFMAXD - - // 3.2.1.4 - AFMAXAF - AFMAXAD - AFMINAF - AFMINAD - - // 3.2.1.7 - AFCOPYSGF - AFCOPYSGD - AFSCALEBF - AFSCALEBD - AFLOGBF - AFLOGBD - - // 3.2.1.8 - AFCLASSF - AFCLASSD - - // 3.2.3.2 - AFFINTFW - AFFINTFV - AFFINTDW - AFFINTDV - AFTINTWF - AFTINTWD - AFTINTVF - AFTINTVD - - // 3.2.3.3 - AFTINTRPWF - AFTINTRPWD - AFTINTRPVF - AFTINTRPVD - AFTINTRMWF - AFTINTRMWD - AFTINTRMVF - AFTINTRMVD - AFTINTRZWF - AFTINTRZWD - AFTINTRZVF - AFTINTRZVD - AFTINTRNEWF - AFTINTRNEWD - AFTINTRNEVF - AFTINTRNEVD - - // 3.2.4.2 - AFSEL - - // LSX and LASX memory access instructions - AVMOVQ - AXVMOVQ - - // LSX and LASX arithmetic instructions - AVADDB - AVADDH - AVADDW - AVADDV - AVADDQ - AXVADDB - AXVADDH - AXVADDW - AXVADDV - AXVADDQ - AVSUBB - AVSUBH - AVSUBW - AVSUBV - AVSUBQ - AXVSUBB - AXVSUBH - AXVSUBW - AXVSUBV - AXVSUBQ - AVADDBU - AVADDHU - AVADDWU - AVADDVU - AVSUBBU - AVSUBHU - AVSUBWU - AVSUBVU - AXVADDBU - AXVADDHU - AXVADDWU - AXVADDVU - AXVSUBBU - AXVSUBHU - AXVSUBWU - AXVSUBVU - - // LSX and LASX Bit-manipulation Instructions - AVANDB - AVORB - AVXORB - AVNORB - AXVANDB - AXVORB - AXVXORB - AXVNORB - AVANDV - AVORV - AVXORV - AVNORV - AVANDNV - AVORNV - AXVANDV - AXVORV - AXVXORV - AXVNORV - AXVANDNV - AXVORNV - - AVPCNTB - AVPCNTH - AVPCNTW - AVPCNTV - AXVPCNTB - AXVPCNTH - AXVPCNTW - AXVPCNTV - - AVBITCLRB - AVBITCLRH - AVBITCLRW - AVBITCLRV - AVBITSETB - AVBITSETH - AVBITSETW - AVBITSETV - AVBITREVB - AVBITREVH - AVBITREVW - AVBITREVV - AXVBITCLRB - AXVBITCLRH - AXVBITCLRW - AXVBITCLRV - AXVBITSETB - AXVBITSETH - AXVBITSETW - AXVBITSETV - AXVBITREVB - AXVBITREVH - AXVBITREVW - AXVBITREVV - - // LSX and LASX integer comparison instruction - AVSEQB - AXVSEQB - AVSEQH - AXVSEQH - AVSEQW - AXVSEQW - AVSEQV - AXVSEQV - - // LSX and LASX integer div and mod instructions - AVDIVB - AVDIVH - AVDIVW - AVDIVV - AVDIVBU - AVDIVHU - AVDIVWU - AVDIVVU - AVMODB - AVMODH - AVMODW - AVMODV - AVMODBU - AVMODHU - AVMODWU - AVMODVU - AXVDIVB - AXVDIVH - AXVDIVW - AXVDIVV - AXVDIVBU - AXVDIVHU - AXVDIVWU - AXVDIVVU - AXVMODB - AXVMODH - AXVMODW - AXVMODV - AXVMODBU - AXVMODHU - AXVMODWU - AXVMODVU - - // LSX and LASX shift operation instructions - AVSLLB - AVSLLH - AVSLLW - AVSLLV - AVSRLB - AVSRLH - AVSRLW - AVSRLV - AVSRAB - AVSRAH - AVSRAW - AVSRAV - AVROTRB - AVROTRH - AVROTRW - AVROTRV - AXVSLLB - AXVSLLH - AXVSLLW - AXVSLLV - AXVSRLB - AXVSRLH - AXVSRLW - AXVSRLV - AXVSRAB - AXVSRAH - AXVSRAW - AXVSRAV - AXVROTRB - AXVROTRH - AXVROTRW - AXVROTRV - - // LSX and LASX move and shuffle instructions - AVILVLB - AVILVLH - AVILVLW - AVILVLV - AVILVHB - AVILVHH - AVILVHW - AVILVHV - AXVILVLB - AXVILVLH - AXVILVLW - AXVILVLV - AXVILVHB - AXVILVHH - AXVILVHW - AXVILVHV - - // LSX and LASX integer mul instructions - AVMULB - AVMULH - AVMULW - AVMULV - AVMUHB - AVMUHH - AVMUHW - AVMUHV - AVMUHBU - AVMUHHU - AVMUHWU - AVMUHVU - AXVMULB - AXVMULH - AXVMULW - AXVMULV - AXVMUHB - AXVMUHH - AXVMUHW - AXVMUHV - AXVMUHBU - AXVMUHHU - AXVMUHWU - AXVMUHVU - - // LSX and LASX floating point instructions - AVFSQRTF - AVFSQRTD - AVFRECIPF - AVFRECIPD - AVFRSQRTF - AVFRSQRTD - AXVFSQRTF - AXVFSQRTD - AXVFRECIPF - AXVFRECIPD - AXVFRSQRTF - AXVFRSQRTD - - AVADDF - AVADDD - AVSUBF - AVSUBD - AVMULF - AVMULD - AVDIVF - AVDIVD - AXVADDF - AXVADDD - AXVSUBF - AXVSUBD - AXVMULF - AXVMULD - AXVDIVF - AXVDIVD - - AVFCLASSF - AVFCLASSD - AXVFCLASSF - AXVFCLASSD - - // LSX and LASX floating point conversion instructions - AVFRINTRNEF - AVFRINTRNED - AVFRINTRZF - AVFRINTRZD - AVFRINTRPF - AVFRINTRPD - AVFRINTRMF - AVFRINTRMD - AVFRINTF - AVFRINTD - AXVFRINTRNEF - AXVFRINTRNED - AXVFRINTRZF - AXVFRINTRZD - AXVFRINTRPF - AXVFRINTRPD - AXVFRINTRMF - AXVFRINTRMD - AXVFRINTF - AXVFRINTD - - // LSX and LASX integer neg instructions - AVNEGB - AVNEGH - AVNEGW - AVNEGV - AXVNEGB - AXVNEGH - AXVNEGW - AXVNEGV - - // LSX and LASX mul instructions that operate on even or odd positions - AVMULWEVHB - AVMULWEVWH - AVMULWEVVW - AVMULWEVQV - AVMULWODHB - AVMULWODWH - AVMULWODVW - AVMULWODQV - AVMULWEVHBU - AVMULWEVWHU - AVMULWEVVWU - AVMULWEVQVU - AVMULWODHBU - AVMULWODWHU - AVMULWODVWU - AVMULWODQVU - AXVMULWEVHB - AXVMULWEVWH - AXVMULWEVVW - AXVMULWEVQV - AXVMULWODHB - AXVMULWODWH - AXVMULWODVW - AXVMULWODQV - AXVMULWEVHBU - AXVMULWEVWHU - AXVMULWEVVWU - AXVMULWEVQVU - AXVMULWODHBU - AXVMULWODWHU - AXVMULWODVWU - AXVMULWODQVU - AVMULWEVHBUB - AVMULWEVWHUH - AVMULWEVVWUW - AVMULWEVQVUV - AVMULWODHBUB - AVMULWODWHUH - AVMULWODVWUW - AVMULWODQVUV - AXVMULWEVHBUB - AXVMULWEVWHUH - AXVMULWEVVWUW - AXVMULWEVQVUV - AXVMULWODHBUB - AXVMULWODWHUH - AXVMULWODVWUW - AXVMULWODQVUV - - AVSHUF4IB - AVSHUF4IH - AVSHUF4IW - AVSHUF4IV - AXVSHUF4IB - AXVSHUF4IH - AXVSHUF4IW - AXVSHUF4IV - - AVSETEQV - AVSETNEV - AVSETANYEQB - AVSETANYEQH - AVSETANYEQW - AVSETANYEQV - AVSETALLNEB - AVSETALLNEH - AVSETALLNEW - AVSETALLNEV - AXVSETEQV - AXVSETNEV - AXVSETANYEQB - AXVSETANYEQH - AXVSETANYEQW - AXVSETANYEQV - AXVSETALLNEB - AXVSETALLNEH - AXVSETALLNEW - AXVSETALLNEV - - ALAST - - // aliases - AJMP = obj.AJMP - AJAL = obj.ACALL - ARET = obj.ARET -) - -func init() { - // The asm encoder generally assumes that the lowest 5 bits of the - // REG_XX constants match the machine instruction encoding, i.e. - // the lowest 5 bits is the register number. - // Check this here. - if REG_R0%32 != 0 { - panic("REG_R0 is not a multiple of 32") - } - if REG_F0%32 != 0 { - panic("REG_F0 is not a multiple of 32") - } - if REG_FCSR0%32 != 0 { - panic("REG_FCSR0 is not a multiple of 32") - } - if REG_FCC0%32 != 0 { - panic("REG_FCC0 is not a multiple of 32") - } - if REG_V0%32 != 0 { - panic("REG_V0 is not a multiple of 32") - } - if REG_X0%32 != 0 { - panic("REG_X0 is not a multiple of 32") - } -} diff --git a/src/cmd/internal/obj/loong64/anames.go b/src/cmd/internal/obj/loong64/anames.go index 422ccbd9b0bc0a..0244a8f9e58811 100644 --- a/src/cmd/internal/obj/loong64/anames.go +++ b/src/cmd/internal/obj/loong64/anames.go @@ -1,4 +1,4 @@ -// Code generated by stringer -i a.out.go -o anames.go -p loong64; DO NOT EDIT. +// Code generated by stringer -i inst.go -o anames.go -p loong64; DO NOT EDIT. package loong64 @@ -10,7 +10,6 @@ var Anames = []string{ "ADD", "ADDD", "ADDF", - "ADDU", "ADDW", "AND", "BEQ", @@ -43,8 +42,7 @@ var Anames = []string{ "DIVF", "DIVU", "DIVW", - "LL", - "LLV", + "DIVWU", "LUI", "MOVB", "MOVBU", @@ -62,7 +60,6 @@ var Anames = []string{ "MUL", "MULD", "MULF", - "MULU", "MULH", "MULHU", "MULW", @@ -74,10 +71,10 @@ var Anames = []string{ "NOR", "OR", "REM", + "REMW", "REMU", + "REMWU", "RFE", - "SC", - "SCV", "SGT", "SGTU", "SLL", @@ -89,7 +86,6 @@ var Anames = []string{ "SUB", "SUBD", "SUBF", - "SUBU", "SUBW", "DBAR", "SYSCALL", @@ -131,6 +127,8 @@ var Anames = []string{ "ALSLV", "ORN", "ANDN", + "MULWVW", + "MULWVWU", "AMSWAPB", "AMSWAPH", "AMSWAPW", @@ -179,6 +177,17 @@ var Anames = []string{ "AMMAXDBVU", "AMMINDBWU", "AMMINDBVU", + "LL", + "LLW", + "LLV", + "SC", + "SCW", + "SCV", + "SCQ", + "LLACQW", + "LLACQV", + "SCRELW", + "SCRELV", "EXTWB", "EXTWH", "CLOW", @@ -267,6 +276,8 @@ var Anames = []string{ "FTINTRNEWD", "FTINTRNEVF", "FTINTRNEVD", + "FRINTF", + "FRINTD", "FSEL", "VMOVQ", "XVMOVQ", @@ -306,6 +317,38 @@ var Anames = []string{ "XVSUBHU", "XVSUBWU", "XVSUBVU", + "VSADDB", + "VSADDH", + "VSADDW", + "VSADDV", + "VSSUBB", + "VSSUBH", + "VSSUBW", + "VSSUBV", + "VSADDBU", + "VSADDHU", + "VSADDWU", + "VSADDVU", + "VSSUBBU", + "VSSUBHU", + "VSSUBWU", + "VSSUBVU", + "XVSADDB", + "XVSADDH", + "XVSADDW", + "XVSADDV", + "XVSSUBB", + "XVSSUBH", + "XVSSUBW", + "XVSSUBV", + "XVSADDBU", + "XVSADDHU", + "XVSADDWU", + "XVSADDVU", + "XVSSUBBU", + "XVSSUBHU", + "XVSSUBWU", + "XVSSUBVU", "VANDB", "VORB", "VXORB", @@ -366,6 +409,22 @@ var Anames = []string{ "XVSEQW", "VSEQV", "XVSEQV", + "VSLTB", + "VSLTH", + "VSLTW", + "VSLTV", + "VSLTBU", + "VSLTHU", + "VSLTWU", + "VSLTVU", + "XVSLTB", + "XVSLTH", + "XVSLTW", + "XVSLTV", + "XVSLTBU", + "XVSLTHU", + "XVSLTWU", + "XVSLTVU", "VDIVB", "VDIVH", "VDIVW", @@ -578,6 +637,134 @@ var Anames = []string{ "XVMULWODWHUH", "XVMULWODVWUW", "XVMULWODQVUV", + "VADDWEVHB", + "VADDWEVWH", + "VADDWEVVW", + "VADDWEVQV", + "VSUBWEVHB", + "VSUBWEVWH", + "VSUBWEVVW", + "VSUBWEVQV", + "VADDWODHB", + "VADDWODWH", + "VADDWODVW", + "VADDWODQV", + "VSUBWODHB", + "VSUBWODWH", + "VSUBWODVW", + "VSUBWODQV", + "XVADDWEVHB", + "XVADDWEVWH", + "XVADDWEVVW", + "XVADDWEVQV", + "XVSUBWEVHB", + "XVSUBWEVWH", + "XVSUBWEVVW", + "XVSUBWEVQV", + "XVADDWODHB", + "XVADDWODWH", + "XVADDWODVW", + "XVADDWODQV", + "XVSUBWODHB", + "XVSUBWODWH", + "XVSUBWODVW", + "XVSUBWODQV", + "VADDWEVHBU", + "VADDWEVWHU", + "VADDWEVVWU", + "VADDWEVQVU", + "VSUBWEVHBU", + "VSUBWEVWHU", + "VSUBWEVVWU", + "VSUBWEVQVU", + "VADDWODHBU", + "VADDWODWHU", + "VADDWODVWU", + "VADDWODQVU", + "VSUBWODHBU", + "VSUBWODWHU", + "VSUBWODVWU", + "VSUBWODQVU", + "XVADDWEVHBU", + "XVADDWEVWHU", + "XVADDWEVVWU", + "XVADDWEVQVU", + "XVSUBWEVHBU", + "XVSUBWEVWHU", + "XVSUBWEVVWU", + "XVSUBWEVQVU", + "XVADDWODHBU", + "XVADDWODWHU", + "XVADDWODVWU", + "XVADDWODQVU", + "XVSUBWODHBU", + "XVSUBWODWHU", + "XVSUBWODVWU", + "XVSUBWODQVU", + "VMADDB", + "VMADDH", + "VMADDW", + "VMADDV", + "VMSUBB", + "VMSUBH", + "VMSUBW", + "VMSUBV", + "XVMADDB", + "XVMADDH", + "XVMADDW", + "XVMADDV", + "XVMSUBB", + "XVMSUBH", + "XVMSUBW", + "XVMSUBV", + "VMADDWEVHB", + "VMADDWEVWH", + "VMADDWEVVW", + "VMADDWEVQV", + "VMADDWODHB", + "VMADDWODWH", + "VMADDWODVW", + "VMADDWODQV", + "VMADDWEVHBU", + "VMADDWEVWHU", + "VMADDWEVVWU", + "VMADDWEVQVU", + "VMADDWODHBU", + "VMADDWODWHU", + "VMADDWODVWU", + "VMADDWODQVU", + "VMADDWEVHBUB", + "VMADDWEVWHUH", + "VMADDWEVVWUW", + "VMADDWEVQVUV", + "VMADDWODHBUB", + "VMADDWODWHUH", + "VMADDWODVWUW", + "VMADDWODQVUV", + "XVMADDWEVHB", + "XVMADDWEVWH", + "XVMADDWEVVW", + "XVMADDWEVQV", + "XVMADDWODHB", + "XVMADDWODWH", + "XVMADDWODVW", + "XVMADDWODQV", + "XVMADDWEVHBU", + "XVMADDWEVWHU", + "XVMADDWEVVWU", + "XVMADDWEVQVU", + "XVMADDWODHBU", + "XVMADDWODWHU", + "XVMADDWODVWU", + "XVMADDWODQVU", + "XVMADDWEVHBUB", + "XVMADDWEVWHUH", + "XVMADDWEVVWUW", + "XVMADDWEVQVUV", + "XVMADDWODHBUB", + "XVMADDWODWHUH", + "XVMADDWODVWUW", + "XVMADDWODQVUV", "VSHUF4IB", "VSHUF4IH", "VSHUF4IW", @@ -586,6 +773,26 @@ var Anames = []string{ "XVSHUF4IH", "XVSHUF4IW", "XVSHUF4IV", + "VSHUFB", + "VSHUFH", + "VSHUFW", + "VSHUFV", + "XVSHUFB", + "XVSHUFH", + "XVSHUFW", + "XVSHUFV", + "VPERMIW", + "XVPERMIW", + "XVPERMIV", + "XVPERMIQ", + "VEXTRINSB", + "VEXTRINSH", + "VEXTRINSW", + "VEXTRINSV", + "XVEXTRINSB", + "XVEXTRINSH", + "XVEXTRINSW", + "XVEXTRINSV", "VSETEQV", "VSETNEV", "VSETANYEQB", diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go index 5a61acac8741d6..2ed2f23d11090a 100644 --- a/src/cmd/internal/obj/loong64/asm.go +++ b/src/cmd/internal/obj/loong64/asm.go @@ -56,383 +56,376 @@ const ( var optab = []Optab{ {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, C_NONE, 0, 0, 0, 0}, - {AMOVW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0}, - {AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0}, - {AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0}, - {AMOVWU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0}, - {ASUB, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {ASUBV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {AADD, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {AADDV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {AAND, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {ASUB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {ASUBV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, + + {AADD, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {AADD, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, + {AADD, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, + {AADD, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, + {AADD, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, + {AADD, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, + {AADD, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, + {AADD, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, + {AADD, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, + {AADD, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, + + {AADDV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {AADDV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, + {AADDV, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, + {AADDV, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, + {AADDV, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, + {AADDV, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, + {AADDV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, + {AADDV, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, + {AADDV, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, + {AADDV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, + {AADDV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0}, + {AADDV, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0}, + {AADDV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0}, + {AADDV, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0}, + {AADDV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0}, + {AADDV, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0}, + {AADDV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0}, + {AADDV, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0}, + + {AAND, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {AAND, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {ANEGV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, + {AAND, C_UU12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, + {AAND, C_UU12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, + {AAND, C_S12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, + {AAND, C_S12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, + {AAND, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, + {AAND, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, + {AAND, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, + {AAND, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, + {AAND, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0}, + {AAND, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0}, + {AAND, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0}, + {AAND, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0}, + {AAND, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0}, + {AAND, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0}, + {AAND, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0}, + {AAND, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0}, + {ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, + {ASLL, C_U5CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0}, + {ASLL, C_U5CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0}, {ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0}, - {AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0}, - {ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0}, - - {AVSEQB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AXVSEQB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AVSEQB, C_S5CON, C_VREG, C_NONE, C_VREG, C_NONE, 22, 4, 0, 0}, - {AXVSEQB, C_S5CON, C_XREG, C_NONE, C_XREG, C_NONE, 22, 4, 0, 0}, - {AVANDV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AVANDV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AXVANDV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AXVANDV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AVANDB, C_U8CON, C_VREG, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0}, - {AVANDB, C_U8CON, C_NONE, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0}, - {AXVANDB, C_U8CON, C_XREG, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0}, - {AXVANDB, C_U8CON, C_NONE, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0}, - - {AVADDB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AVADDB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AXVADDB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AXVADDB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - - {AVSLLB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AVSLLB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AXVSLLB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AXVSLLB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AVSLLB, C_U3CON, C_VREG, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0}, - {AXVSLLB, C_U3CON, C_XREG, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0}, - {AVSLLB, C_U3CON, C_NONE, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0}, - {AXVSLLB, C_U3CON, C_NONE, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0}, - - {AVSLLH, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AVSLLH, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AXVSLLH, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AXVSLLH, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AVSLLH, C_U4CON, C_VREG, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0}, - {AXVSLLH, C_U4CON, C_XREG, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0}, - {AVSLLH, C_U4CON, C_NONE, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0}, - {AXVSLLH, C_U4CON, C_NONE, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0}, - - {AVSLLW, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AVSLLW, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AXVSLLW, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AXVSLLW, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AVSLLW, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0}, - {AXVSLLW, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0}, - {AVSLLW, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0}, - {AXVSLLW, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0}, - - {AVSLLV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AVSLLV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, - {AXVSLLV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AXVSLLV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - {AVSLLV, C_U6CON, C_VREG, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0}, - {AXVSLLV, C_U6CON, C_XREG, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0}, - {AVSLLV, C_U6CON, C_NONE, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0}, - {AXVSLLV, C_U6CON, C_NONE, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0}, - - {ACLOW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0}, - {AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0}, - {AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0}, - {AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0}, - {AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0}, - {AVPCNTB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 9, 4, 0, 0}, - {AXVPCNTB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 9, 4, 0, 0}, - {AVSETEQV, C_VREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0}, - {AXVSETEQV, C_XREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0}, - - {AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0}, - {AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0}, + {ASLLV, C_U6CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0}, + {ASLLV, C_U6CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0}, - {AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0}, - {AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0}, + {AADDV16, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, + {AADDV16, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, - {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, - {AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, + // memory access {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, - {AMOVBU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, - {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0}, - {AMOVWU, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0}, - {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0}, - {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0}, - {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0}, - {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0}, - {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0}, - {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0}, - {ASC, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0}, - {ASCV, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0}, - - {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0}, - {AMOVWU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0}, - {AMOVV, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0}, + {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0}, {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0}, - {AMOVBU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0}, - {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, - {AMOVWU, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, - {AMOVV, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, - {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, - {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, - {AVMOVQ, C_SOREG, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0}, - {AXVMOVQ, C_SOREG, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0}, - {AVMOVQ, C_SAUTO, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0}, - {AXVMOVQ, C_SAUTO, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0}, - {ALL, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, - {ALLV, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, + {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0}, + {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0}, + {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0}, + {AMOVB, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, + {AMOVB, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, + {AMOVB, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, + {AMOVB, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0}, + // variable access + {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, + {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, + // TLS access + {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0}, + {AMOVB, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0}, + {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0}, + {AMOVB, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0}, + // moving data between registers + {AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0}, - {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0}, - {AMOVWU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0}, - {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0}, + // memory access + {AMOVBU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, + {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0}, + {AMOVBU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0}, + {AMOVBU, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, {AMOVBU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0}, - {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0}, - {AMOVWU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0}, - {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0}, - {AMOVBU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0}, - {ASC, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0}, - {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - {AMOVWU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, + {AMOVBU, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0}, + {AMOVBU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0}, + {AMOVBU, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, + {AMOVBU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0}, + // variable access {AMOVBU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0}, - {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0}, - {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0}, + {AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, + // TLS access {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0}, - {AMOVWP, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 73, 4, 0, 0}, - {AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 73, 4, 0, 0}, + {AMOVBU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0}, + {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0}, + {AMOVBU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0}, + // moving data between registers + {AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0}, + // memory access + {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, + {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0}, + {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0}, {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0}, - {AMOVWU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0}, - {AMOVV, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0}, - {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0}, - {AMOVBU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0}, - {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, - {AMOVWU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, - {AMOVV, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, - {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, - {AMOVBU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, + {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0}, + {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0}, + {AMOVW, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, + {AMOVW, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, + {AMOVW, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, + {AMOVW, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0}, + // variable access + {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, - {AMOVWU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, - {AMOVV, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, - {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, - {AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, + // TLS access + {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0}, {AMOVW, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0}, - {AMOVWU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0}, - {AMOVV, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0}, - {AMOVB, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0}, - {AMOVBU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0}, - {AMOVWP, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 74, 4, 0, 0}, - {AMOVWP, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 74, 4, 0, 0}, - + {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0}, + {AMOVW, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0}, + // moving data between registers + {AMOVW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0}, + {AMOVW, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0}, + {AMOVW, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0}, + // immediate load + {AMOVW, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0}, + {AMOVW, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP}, + {AMOVW, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0}, + {AMOVW, C_12CON, C_NONE, C_NONE, C_FREG, C_NONE, 34, 8, 0, 0}, + // get a stack address {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0}, - {AMOVV, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0}, - {AMOVW, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP}, - {AMOVV, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP}, - {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0}, - {AMOVV, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0}, - {AMOVW, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0}, - {AMOVV, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0}, - {AMOVW, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0}, - {AMOVV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0}, - {AMOVW, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP}, + // memory access + {AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, + {AMOVV, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0}, + {AMOVV, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0}, + {AMOVV, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0}, + {AMOVV, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0}, + {AMOVV, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0}, + {AMOVV, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0}, + {AMOVV, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, + {AMOVV, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, + {AMOVV, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0}, + // variable access, need relocation + {AMOVV, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, + {AMOVV, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, + // TLS access + {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0}, + {AMOVV, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0}, + {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0}, + {AMOVV, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0}, + // moving data between registers + {AMOVV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0}, + {AMOVV, C_FCCREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0}, + {AMOVV, C_FCSRREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0}, + {AMOVV, C_REG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0}, + {AMOVV, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0}, + {AMOVV, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0}, + {AMOVV, C_REG, C_NONE, C_NONE, C_FCSRREG, C_NONE, 30, 4, 0, 0}, + {AMOVV, C_FREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0}, + {AMOVV, C_FCCREG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0}, + // immediate load + {AMOVV, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0}, {AMOVV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP}, + {AMOVV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0}, {AMOVV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 67, 4, 0, NOTUSETMP}, {AMOVV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 68, 8, 0, NOTUSETMP}, {AMOVV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 69, 12, 0, NOTUSETMP}, {AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP}, + // get a stack address + {AMOVV, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0}, + {AMOVV, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0}, + // get an external address, need relocation + {AMOVV, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP}, + // get a got address, need relocation + {AMOVV, C_GOTADDR, C_NONE, C_NONE, C_REG, C_NONE, 65, 8, 0, 0}, - {AADD, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, - {AADD, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, - {AADD, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, - {AADD, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, + // memory access + {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0}, + {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0}, + {AVMOVQ, C_SAUTO, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0}, + {AVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0}, + {AVMOVQ, C_VREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, + {AVMOVQ, C_ROFF, C_NONE, C_NONE, C_VREG, C_NONE, 21, 4, 0, 0}, + {AVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_ARNG, C_NONE, 42, 4, 0, 0}, // vldrepl.{b/h/w/d} + // moving data between registers + {AVMOVQ, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 1, 4, 0, 0}, + {AVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0}, // vinsgr2vr.{b/h/w/d} + {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0}, // vpickve2gr.{b/h/w/d} + {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 40, 4, 0, 0}, // vreplvei.{b/h/w/d} + {AVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0}, // vreplgr2vr.{b/h/w/d} + + // memory access + {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0}, + {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0}, + {AXVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0}, + {AXVMOVQ, C_SAUTO, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0}, + {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, + {AXVMOVQ, C_ROFF, C_NONE, C_NONE, C_XREG, C_NONE, 21, 4, 0, 0}, + {AXVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_ARNG, C_NONE, 42, 4, 0, 0}, // xvldrepl.{b/h/w/d} + // moving data between registers + {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 1, 4, 0, 0}, + {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0}, // vinsgr2vr.{b/h/w/d} + {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0}, // xvinsve0.{w/d} + {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0}, // vpickve2gr.{b/h/w/d} + {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_XREG, C_NONE, 40, 4, 0, 0}, // xvpickve.{w/d} + {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0}, // xvreplgr2vr.{b/h/w/d} + {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0}, // xvreplve0.{b/h/w/d/q} + + // memory access + {AMOVWP, C_REG, C_NONE, C_NONE, C_SOREG_16, C_NONE, 73, 4, 0, 0}, + {AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 73, 12, 0, 0}, + {AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG_64, C_NONE, 73, 24, 0, 0}, + {AMOVWP, C_SOREG_16, C_NONE, C_NONE, C_REG, C_NONE, 74, 4, 0, 0}, + {AMOVWP, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 74, 12, 0, 0}, + {AMOVWP, C_LOREG_64, C_NONE, C_NONE, C_REG, C_NONE, 74, 24, 0, 0}, + + // condition branch + {ABEQ, C_REG, C_REG, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0}, + {ABEQ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0}, + {ABLEZ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0}, + {ABFPT, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0}, + {ABFPT, C_FCCREG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0}, + // jmp and call + {AJMP, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0}, // b + {AJAL, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0}, // bl + {AJMP, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGZERO, 0}, // jirl r0, rj, 0 + {AJAL, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGLINK, 0}, // jirl r1, rj, 0 - {AADDV, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, - {AADDV, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, - {AADDV, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, - {AADDV, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, + {ABSTRPICKW, C_U6CON, C_REG, C_U6CON, C_REG, C_NONE, 17, 4, 0, 0}, + {ABSTRPICKW, C_U6CON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0}, + {ABSTRPICKW, C_ZCON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0}, - {AADDV16, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, - {AADDV16, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, + // preload + {APRELD, C_SOREG_12, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0}, + {APRELDX, C_SOREG_16, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0}, - {AAND, C_UU12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, - {AAND, C_UU12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, - {AAND, C_S12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, - {AAND, C_S12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, - - {AADD, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, - {AADD, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, - {AADDV, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, - {AADDV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, - {AAND, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, - {AAND, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0}, + {AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, - {AADD, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, - {AADDV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, - {AAND, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, - {AADD, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, - {AADDV, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, - {AAND, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0}, + {ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0}, - {AADDV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0}, - {AADDV, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0}, - {AAND, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0}, - {AAND, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0}, - {AADDV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0}, - {AADDV, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0}, - {AAND, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0}, - {AAND, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0}, - {AADDV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0}, - {AADDV, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0}, - {AAND, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0}, - {AAND, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0}, - {AADDV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0}, - {AADDV, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0}, - {AAND, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0}, - {AAND, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0}, + {ARDTIMELW, C_NONE, C_NONE, C_NONE, C_REG, C_REG, 62, 4, 0, 0}, - {ASLL, C_U5CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0}, - {ASLL, C_U5CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0}, + {AALSLV, C_U3CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0}, - {ASLLV, C_U6CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0}, - {ASLLV, C_U6CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0}, + {AAMSWAPW, C_REG, C_NONE, C_NONE, C_ZOREG, C_REG, 66, 4, 0, 0}, - {ABSTRPICKW, C_U6CON, C_REG, C_U6CON, C_REG, C_NONE, 17, 4, 0, 0}, - {ABSTRPICKW, C_U6CON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0}, - {ABSTRPICKW, C_ZCON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0}, + {ASCQ, C_REG, C_REG, C_NONE, C_ZOREG, C_NONE, 45, 4, 0, 0}, + {ALLACQW, C_ZOREG, C_NONE, C_NONE, C_REG, C_NONE, 46, 4, 0, 0}, + {ASCRELW, C_REG, C_NONE, C_NONE, C_ZOREG, C_NONE, 46, 4, 0, 0}, {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0}, {ASYSCALL, C_U15CON, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0}, - {ABEQ, C_REG, C_REG, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0}, - {ABEQ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0}, - {ABLEZ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0}, - {ABFPT, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0}, - {ABFPT, C_FCCREG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0}, + {AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0}, + {AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0}, - {AJMP, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0}, // b - {AJAL, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0}, // bl + {AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0}, + {AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0}, - {AJMP, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGZERO, 0}, // jirl r0, rj, 0 - {AJAL, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGLINK, 0}, // jirl r1, rj, 0 + {AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0}, + {AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0}, - {AMOVF, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0}, - {AMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0}, - {AMOVF, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0}, - {AMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0}, + {ACLOW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0}, + {AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0}, - {AMOVF, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0}, - {AMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0}, - {AMOVF, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0}, - {AMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0}, - {AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0}, - {AMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0}, + {AVSETEQV, C_VREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0}, + {AXVSETEQV, C_XREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0}, - {AMOVF, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0}, - {AMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0}, - {AMOVF, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 29, 4, REGZERO, 0}, - {AMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 29, 4, REGZERO, 0}, + {AVPCNTB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 9, 4, 0, 0}, + {AXVPCNTB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 9, 4, 0, 0}, - {AMOVF, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0}, - {AMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0}, - {AMOVF, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 29, 12, REGZERO, 0}, - {AMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 29, 12, REGZERO, 0}, + // memory access + {AMOVF, C_SOREG_12, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0}, + {AMOVF, C_LOREG_32, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0}, + {AMOVF, C_FREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 29, 4, REGZERO, 0}, + {AMOVF, C_FREG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 29, 12, REGZERO, 0}, + {AMOVF, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, + {AMOVF, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0}, + // variable access {AMOVF, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - {AMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - - {AMOVW, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0}, - {AMOVW, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0}, - {AMOVV, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0}, - {AMOVV, C_FCCREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0}, - {AMOVV, C_FCSRREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_FCSRREG, C_NONE, 30, 4, 0, 0}, - {AMOVV, C_FREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0}, - {AMOVV, C_FCCREG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0}, - - {AMOVW, C_12CON, C_NONE, C_NONE, C_FREG, C_NONE, 34, 8, 0, 0}, - - {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0}, - {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0}, - {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0}, - {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0}, - - {AMOVB, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0}, - {AMOVW, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0}, - {AMOVV, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0}, - {AMOVBU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0}, - {AMOVWU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0}, + {AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0}, + // moving data between registers + {AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0}, + // load data from stack + {AMOVF, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0}, + {AMOVF, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0}, + // store data to stack + {AMOVF, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0}, + {AMOVF, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0}, - {AWORD, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0}, - {AWORD, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 61, 4, 0, 0}, + {AVSHUFB, C_VREG, C_VREG, C_VREG, C_VREG, C_NONE, 37, 4, 0, 0}, + {AXVSHUFB, C_XREG, C_XREG, C_XREG, C_XREG, C_NONE, 37, 4, 0, 0}, - {AMOVV, C_GOTADDR, C_NONE, C_NONE, C_REG, C_NONE, 65, 8, 0, 0}, + {AVSEQB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSEQB, C_S5CON, C_VREG, C_NONE, C_VREG, C_NONE, 22, 4, 0, 0}, + {AXVSEQB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSEQB, C_S5CON, C_XREG, C_NONE, C_XREG, C_NONE, 22, 4, 0, 0}, - {ATEQ, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 15, 8, 0, 0}, - {ATEQ, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 15, 8, 0, 0}, + {AVSLTBU, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLTBU, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0}, + {AXVSLTBU, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLTBU, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0}, - {ARDTIMELW, C_NONE, C_NONE, C_NONE, C_REG, C_REG, 62, 4, 0, 0}, - {AAMSWAPW, C_REG, C_NONE, C_NONE, C_ZOREG, C_REG, 66, 4, 0, 0}, - {ANOOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0}, + {AVANDB, C_U8CON, C_VREG, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0}, + {AVANDB, C_U8CON, C_NONE, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0}, + {AXVANDB, C_U8CON, C_XREG, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0}, + {AXVANDB, C_U8CON, C_NONE, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0}, - /* store with extended register offset */ - {AMOVB, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, - {AMOVW, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, - {AMOVV, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, - {AMOVF, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, - {AMOVD, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, - {AVMOVQ, C_VREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, - {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0}, + {AVADDB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVADDB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AXVADDB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVADDB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, - /* load with extended register offset */ - {AMOVB, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0}, - {AMOVBU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0}, - {AMOVW, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0}, - {AMOVWU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0}, - {AMOVV, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0}, - {AMOVF, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0}, - {AMOVD, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0}, - {AVMOVQ, C_ROFF, C_NONE, C_NONE, C_VREG, C_NONE, 21, 4, 0, 0}, - {AXVMOVQ, C_ROFF, C_NONE, C_NONE, C_XREG, C_NONE, 21, 4, 0, 0}, + {AVADDBU, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0}, + {AVADDBU, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0}, + {AXVADDBU, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0}, + {AXVADDBU, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0}, - {AVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0}, - {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0}, - {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0}, - {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0}, + {AVSLLB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLB, C_U3CON, C_VREG, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0}, + {AVSLLB, C_U3CON, C_NONE, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0}, + {AXVSLLB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLB, C_U3CON, C_XREG, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0}, + {AXVSLLB, C_U3CON, C_NONE, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0}, - {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ELEM, C_NONE, 43, 4, 0, 0}, - {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_XREG, C_NONE, 44, 4, 0, 0}, + {AVSLLH, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLH, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLH, C_U4CON, C_VREG, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0}, + {AVSLLH, C_U4CON, C_NONE, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0}, + {AXVSLLH, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLH, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLH, C_U4CON, C_XREG, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0}, + {AXVSLLH, C_U4CON, C_NONE, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0}, - {AVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0}, - {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0}, - {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ARNG, C_NONE, 42, 4, 0, 0}, + {AVSLLW, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLW, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLW, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0}, + {AVSLLW, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0}, + {AXVSLLW, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLW, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLW, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0}, + {AXVSLLW, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0}, - {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 45, 4, 0, 0}, + {AVSLLV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLV, C_U6CON, C_VREG, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0}, + {AVSLLV, C_U6CON, C_NONE, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0}, + {AXVSLLV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLV, C_U6CON, C_XREG, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0}, + {AXVSLLV, C_U6CON, C_NONE, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0}, - {AVMOVQ, C_SOREG, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0}, - {AXVMOVQ, C_SOREG, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0}, + {AWORD, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0}, + {AWORD, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 61, 4, 0, 0}, - {APRELD, C_SOREG, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0}, - {APRELDX, C_SOREG, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0}, + {ANOOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0}, - {AALSLV, C_U3CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0}, + {ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, + {ATEQ, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 15, 8, 0, 0}, + {ATEQ, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 15, 8, 0, 0}, {obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0}, {obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0}, @@ -445,57 +438,6 @@ var optab = []Optab{ {obj.ANOP, C_FREG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0}, } -var atomicInst = map[obj.As]uint32{ - AAMSWAPB: 0x070B8 << 15, // amswap.b - AAMSWAPH: 0x070B9 << 15, // amswap.h - AAMSWAPW: 0x070C0 << 15, // amswap.w - AAMSWAPV: 0x070C1 << 15, // amswap.d - AAMCASB: 0x070B0 << 15, // amcas.b - AAMCASH: 0x070B1 << 15, // amcas.h - AAMCASW: 0x070B2 << 15, // amcas.w - AAMCASV: 0x070B3 << 15, // amcas.d - AAMADDW: 0x070C2 << 15, // amadd.w - AAMADDV: 0x070C3 << 15, // amadd.d - AAMANDW: 0x070C4 << 15, // amand.w - AAMANDV: 0x070C5 << 15, // amand.d - AAMORW: 0x070C6 << 15, // amor.w - AAMORV: 0x070C7 << 15, // amor.d - AAMXORW: 0x070C8 << 15, // amxor.w - AAMXORV: 0x070C9 << 15, // amxor.d - AAMMAXW: 0x070CA << 15, // ammax.w - AAMMAXV: 0x070CB << 15, // ammax.d - AAMMINW: 0x070CC << 15, // ammin.w - AAMMINV: 0x070CD << 15, // ammin.d - AAMMAXWU: 0x070CE << 15, // ammax.wu - AAMMAXVU: 0x070CF << 15, // ammax.du - AAMMINWU: 0x070D0 << 15, // ammin.wu - AAMMINVU: 0x070D1 << 15, // ammin.du - AAMSWAPDBB: 0x070BC << 15, // amswap_db.b - AAMSWAPDBH: 0x070BD << 15, // amswap_db.h - AAMSWAPDBW: 0x070D2 << 15, // amswap_db.w - AAMSWAPDBV: 0x070D3 << 15, // amswap_db.d - AAMCASDBB: 0x070B4 << 15, // amcas_db.b - AAMCASDBH: 0x070B5 << 15, // amcas_db.h - AAMCASDBW: 0x070B6 << 15, // amcas_db.w - AAMCASDBV: 0x070B7 << 15, // amcas_db.d - AAMADDDBW: 0x070D4 << 15, // amadd_db.w - AAMADDDBV: 0x070D5 << 15, // amadd_db.d - AAMANDDBW: 0x070D6 << 15, // amand_db.w - AAMANDDBV: 0x070D7 << 15, // amand_db.d - AAMORDBW: 0x070D8 << 15, // amor_db.w - AAMORDBV: 0x070D9 << 15, // amor_db.d - AAMXORDBW: 0x070DA << 15, // amxor_db.w - AAMXORDBV: 0x070DB << 15, // amxor_db.d - AAMMAXDBW: 0x070DC << 15, // ammax_db.w - AAMMAXDBV: 0x070DD << 15, // ammax_db.d - AAMMINDBW: 0x070DE << 15, // ammin_db.w - AAMMINDBV: 0x070DF << 15, // ammin_db.d - AAMMAXDBWU: 0x070E0 << 15, // ammax_db.wu - AAMMAXDBVU: 0x070E1 << 15, // ammax_db.du - AAMMINDBWU: 0x070E2 << 15, // ammin_db.wu - AAMMINDBVU: 0x070E3 << 15, // ammin_db.du -} - func IsAtomicInst(as obj.As) bool { _, ok := atomicInst[as] @@ -547,8 +489,8 @@ func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { alignedValue := p.From.Offset m = pcAlignPadLength(ctxt, pc, alignedValue) // Update the current text symbol alignment value. - if int32(alignedValue) > cursym.Func().Align { - cursym.Func().Align = int32(alignedValue) + if int16(alignedValue) > cursym.Align { + cursym.Align = int16(alignedValue) } break case obj.ANOP, obj.AFUNCDATA, obj.APCDATA: @@ -678,7 +620,7 @@ func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { bp := c.cursym.P var i int32 - var out [5]uint32 + var out [6]uint32 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link { c.pc = p.Pc o = c.oplook(p) @@ -778,7 +720,7 @@ func (c *ctxt0) aclass(a *obj.Addr) int { a.Reg = obj.REG_NONE } c.instoffset = int64(c.autosize) + a.Offset - if c.instoffset >= -BIG && c.instoffset < BIG { + if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 { return C_SAUTO } return C_LAUTO @@ -790,7 +732,7 @@ func (c *ctxt0) aclass(a *obj.Addr) int { a.Reg = obj.REG_NONE } c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize - if c.instoffset >= -BIG && c.instoffset < BIG { + if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 { return C_SAUTO } return C_LAUTO @@ -808,10 +750,23 @@ func (c *ctxt0) aclass(a *obj.Addr) int { if c.instoffset == 0 { return C_ZOREG } - if c.instoffset >= -BIG && c.instoffset < BIG { - return C_SOREG + if c.instoffset >= -BIG_8 && c.instoffset < BIG_8 { + return C_SOREG_8 + } else if c.instoffset >= -BIG_9 && c.instoffset < BIG_9 { + return C_SOREG_9 + } else if c.instoffset >= -BIG_10 && c.instoffset < BIG_10 { + return C_SOREG_10 + } else if c.instoffset >= -BIG_11 && c.instoffset < BIG_11 { + return C_SOREG_11 + } else if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 { + return C_SOREG_12 + } else if c.instoffset >= -BIG_16 && c.instoffset < BIG_16 { + return C_SOREG_16 + } else if c.instoffset >= -BIG_32 && c.instoffset < BIG_32 { + return C_LOREG_32 + } else { + return C_LOREG_64 } - return C_LOREG case obj.NAME_GOTREF: return C_GOTADDR @@ -828,7 +783,7 @@ func (c *ctxt0) aclass(a *obj.Addr) int { case obj.NAME_NONE: c.instoffset = a.Offset if a.Reg != 0 { - if -BIG <= c.instoffset && c.instoffset <= BIG { + if -BIG_12 <= c.instoffset && c.instoffset <= BIG_12 { return C_SACON } if isint32(c.instoffset) { @@ -857,7 +812,7 @@ func (c *ctxt0) aclass(a *obj.Addr) int { a.Reg = obj.REG_NONE } c.instoffset = int64(c.autosize) + a.Offset - if c.instoffset >= -BIG && c.instoffset < BIG { + if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 { return C_SACON } return C_LACON @@ -869,7 +824,7 @@ func (c *ctxt0) aclass(a *obj.Addr) int { a.Reg = obj.REG_NONE } c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize - if c.instoffset >= -BIG && c.instoffset < BIG { + if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 { return C_SACON } return C_LACON @@ -1271,10 +1226,33 @@ func cmp(a int, b int) bool { case C_REG: return b == C_ZCON - case C_LOREG: - return b == C_ZOREG || b == C_SOREG + case C_LOREG_64: + if b == C_ZOREG || b == C_SOREG_8 || + b == C_SOREG_9 || b == C_SOREG_10 || + b == C_SOREG_11 || b == C_SOREG_12 || + b == C_SOREG_16 || b == C_LOREG_32 { + return true + } + + case C_LOREG_32: + return cmp(C_SOREG_16, b) + + case C_SOREG_16: + return cmp(C_SOREG_12, b) + + case C_SOREG_12: + return cmp(C_SOREG_11, b) - case C_SOREG: + case C_SOREG_11: + return cmp(C_SOREG_10, b) + + case C_SOREG_10: + return cmp(C_SOREG_9, b) + + case C_SOREG_9: + return cmp(C_SOREG_8, b) + + case C_SOREG_8: return b == C_ZOREG } @@ -1303,7 +1281,7 @@ func opset(a, b0 obj.As) { func buildop(ctxt *obj.Link) { if ctxt.DiagFunc == nil { - ctxt.DiagFunc = func(format string, args ...interface{}) { + ctxt.DiagFunc = func(format string, args ...any) { log.Printf(format, args...) } } @@ -1346,6 +1324,20 @@ func buildop(ctxt *obj.Link) { opset(AMOVFW, r0) opset(AMOVWD, r0) opset(AMOVDW, r0) + opset(AMOVVF, r0) + opset(AMOVVD, r0) + opset(AMOVFV, r0) + opset(AMOVDV, r0) + opset(AFFINTFW, r0) + opset(AFFINTFV, r0) + opset(AFFINTDW, r0) + opset(AFFINTDV, r0) + opset(AFTINTWF, r0) + opset(AFTINTWD, r0) + opset(AFTINTVF, r0) + opset(AFTINTVD, r0) + opset(AFRINTF, r0) + opset(AFRINTD, r0) opset(ANEGF, r0) opset(ANEGD, r0) opset(AABSD, r0) @@ -1357,21 +1349,8 @@ func buildop(ctxt *obj.Link) { opset(AFCLASSD, r0) opset(AFLOGBF, r0) opset(AFLOGBD, r0) - - case AMOVVF: - opset(AMOVVD, r0) - opset(AMOVFV, r0) - opset(AMOVDV, r0) opset(ATRUNCDV, r0) opset(ATRUNCFV, r0) - opset(AFFINTFW, r0) - opset(AFFINTFV, r0) - opset(AFFINTDW, r0) - opset(AFFINTDV, r0) - opset(AFTINTWF, r0) - opset(AFTINTWD, r0) - opset(AFTINTVF, r0) - opset(AFTINTVD, r0) opset(AFTINTRPWF, r0) opset(AFTINTRPWD, r0) opset(AFTINTRPVF, r0) @@ -1390,9 +1369,9 @@ func buildop(ctxt *obj.Link) { opset(AFTINTRNEVD, r0) case AADD: + opset(AADDW, r0) opset(ASGT, r0) opset(ASGTU, r0) - opset(AADDU, r0) case AADDV: opset(AADDVU, r0) @@ -1450,27 +1429,16 @@ func buildop(ctxt *obj.Link) { case AMOVBU: opset(AMOVHU, r0) + opset(AMOVWU, r0) case AMOVWP: opset(AMOVVP, r0) - - case AMUL: - opset(AMULU, r0) - opset(AMULH, r0) - opset(AMULHU, r0) - opset(AREM, r0) - opset(AREMU, r0) - opset(ADIV, r0) - opset(ADIVU, r0) - - case AMULV: - opset(AMULVU, r0) - opset(AMULHV, r0) - opset(AMULHVU, r0) - opset(AREMV, r0) - opset(AREMVU, r0) - opset(ADIVV, r0) - opset(ADIVVU, r0) + opset(ASC, r0) + opset(ASCW, r0) + opset(ASCV, r0) + opset(ALL, r0) + opset(ALLW, r0) + opset(ALLV, r0) case ASLL: opset(ASRL, r0) @@ -1488,11 +1456,32 @@ func buildop(ctxt *obj.Link) { opset(ABSTRINSV, r0) case ASUB: - opset(ASUBU, r0) + opset(ASUBW, r0) opset(ANOR, r0) - - case ASUBV: + opset(ASUBV, r0) opset(ASUBVU, r0) + opset(AMUL, r0) + opset(AMULW, r0) + opset(AMULH, r0) + opset(AMULHU, r0) + opset(AREM, r0) + opset(AREMW, r0) + opset(AREMU, r0) + opset(AREMWU, r0) + opset(ADIV, r0) + opset(ADIVW, r0) + opset(ADIVU, r0) + opset(ADIVWU, r0) + opset(AMULV, r0) + opset(AMULVU, r0) + opset(AMULHV, r0) + opset(AMULHVU, r0) + opset(AREMV, r0) + opset(AREMVU, r0) + opset(ADIVV, r0) + opset(ADIVVU, r0) + opset(AMULWVW, r0) + opset(AMULWVWU, r0) case ASYSCALL: opset(ADBAR, r0) @@ -1512,27 +1501,27 @@ func buildop(ctxt *obj.Link) { opset(AALSLW, r0) opset(AALSLWU, r0) + case ANEGW: + opset(ANEGV, r0) + + case AMOVF: + opset(AMOVD, r0) + case AMOVW, - AMOVD, - AMOVF, AMOVV, ARFE, AJAL, AJMP, - AMOVWU, AVMOVQ, AXVMOVQ, - ALL, - ALLV, - ASC, - ASCV, - ANEGW, - ANEGV, + AVSHUFB, + AXVSHUFB, AWORD, APRELD, APRELDX, AFSEL, AADDV16, + ASCQ, obj.ANOP, obj.ATEXT, obj.AFUNCDATA, @@ -1591,10 +1580,113 @@ func buildop(ctxt *obj.Link) { opset(i, r0) } + case ALLACQW: + opset(ALLACQV, r0) + + case ASCRELW: + opset(ASCRELV, r0) + + // vseq.b vd, vj, vk + // vseqi.b vd, vj, si5 case AVSEQB: opset(AVSEQH, r0) opset(AVSEQW, r0) opset(AVSEQV, r0) + opset(AVSLTB, r0) + opset(AVSLTH, r0) + opset(AVSLTW, r0) + opset(AVSLTV, r0) + + // xvseq.b xd, xj, xk + // xvseqi.b xd, xj, si5 + case AXVSEQB: + opset(AXVSEQH, r0) + opset(AXVSEQW, r0) + opset(AXVSEQV, r0) + opset(AXVSLTB, r0) + opset(AXVSLTH, r0) + opset(AXVSLTW, r0) + opset(AXVSLTV, r0) + + // vslt.bu vd, vj, vk + // vslti.bu vd, vj, ui5 + case AVSLTBU: + opset(AVSLTHU, r0) + opset(AVSLTWU, r0) + opset(AVSLTVU, r0) + + // xvslt.bu xd, xj, xk + // xvslti.bu xd, xj, ui5 + case AXVSLTBU: + opset(AXVSLTHU, r0) + opset(AXVSLTWU, r0) + opset(AXVSLTVU, r0) + + // vandi.b vd, vj, ui8 + case AVANDB: + opset(AVORB, r0) + opset(AVXORB, r0) + opset(AVNORB, r0) + opset(AVSHUF4IB, r0) + opset(AVSHUF4IH, r0) + opset(AVSHUF4IW, r0) + opset(AVSHUF4IV, r0) + opset(AVPERMIW, r0) + opset(AVEXTRINSB, r0) + opset(AVEXTRINSH, r0) + opset(AVEXTRINSW, r0) + opset(AVEXTRINSV, r0) + + // xvandi.b xd, xj, ui8 + case AXVANDB: + opset(AXVORB, r0) + opset(AXVXORB, r0) + opset(AXVNORB, r0) + opset(AXVSHUF4IB, r0) + opset(AXVSHUF4IH, r0) + opset(AXVSHUF4IW, r0) + opset(AXVSHUF4IV, r0) + opset(AXVPERMIW, r0) + opset(AXVPERMIV, r0) + opset(AXVPERMIQ, r0) + opset(AXVEXTRINSB, r0) + opset(AXVEXTRINSH, r0) + opset(AXVEXTRINSW, r0) + opset(AXVEXTRINSV, r0) + + // vadd.b vd, vj, vk + case AVADDB: + opset(AVADDH, r0) + opset(AVADDW, r0) + opset(AVADDV, r0) + opset(AVADDQ, r0) + opset(AVSUBB, r0) + opset(AVSUBH, r0) + opset(AVSUBW, r0) + opset(AVSUBV, r0) + opset(AVSUBQ, r0) + opset(AVSADDB, r0) + opset(AVSADDH, r0) + opset(AVSADDW, r0) + opset(AVSADDV, r0) + opset(AVSSUBB, r0) + opset(AVSSUBH, r0) + opset(AVSSUBW, r0) + opset(AVSSUBV, r0) + opset(AVSADDBU, r0) + opset(AVSADDHU, r0) + opset(AVSADDWU, r0) + opset(AVSADDVU, r0) + opset(AVSSUBBU, r0) + opset(AVSSUBHU, r0) + opset(AVSSUBWU, r0) + opset(AVSSUBVU, r0) + opset(AVANDV, r0) + opset(AVORV, r0) + opset(AVXORV, r0) + opset(AVNORV, r0) + opset(AVANDNV, r0) + opset(AVORNV, r0) opset(AVILVLB, r0) opset(AVILVLH, r0) opset(AVILVLW, r0) @@ -1663,11 +1755,107 @@ func buildop(ctxt *obj.Link) { opset(AVMULD, r0) opset(AVDIVF, r0) opset(AVDIVD, r0) - - case AXVSEQB: - opset(AXVSEQH, r0) - opset(AXVSEQW, r0) - opset(AXVSEQV, r0) + opset(AVSHUFH, r0) + opset(AVSHUFW, r0) + opset(AVSHUFV, r0) + opset(AVADDWEVHB, r0) + opset(AVADDWEVWH, r0) + opset(AVADDWEVVW, r0) + opset(AVADDWEVQV, r0) + opset(AVSUBWEVHB, r0) + opset(AVSUBWEVWH, r0) + opset(AVSUBWEVVW, r0) + opset(AVSUBWEVQV, r0) + opset(AVADDWODHB, r0) + opset(AVADDWODWH, r0) + opset(AVADDWODVW, r0) + opset(AVADDWODQV, r0) + opset(AVSUBWODHB, r0) + opset(AVSUBWODWH, r0) + opset(AVSUBWODVW, r0) + opset(AVSUBWODQV, r0) + opset(AVADDWEVHBU, r0) + opset(AVADDWEVWHU, r0) + opset(AVADDWEVVWU, r0) + opset(AVADDWEVQVU, r0) + opset(AVSUBWEVHBU, r0) + opset(AVSUBWEVWHU, r0) + opset(AVSUBWEVVWU, r0) + opset(AVSUBWEVQVU, r0) + opset(AVADDWODHBU, r0) + opset(AVADDWODWHU, r0) + opset(AVADDWODVWU, r0) + opset(AVADDWODQVU, r0) + opset(AVSUBWODHBU, r0) + opset(AVSUBWODWHU, r0) + opset(AVSUBWODVWU, r0) + opset(AVSUBWODQVU, r0) + opset(AVMADDB, r0) + opset(AVMADDH, r0) + opset(AVMADDW, r0) + opset(AVMADDV, r0) + opset(AVMSUBB, r0) + opset(AVMSUBH, r0) + opset(AVMSUBW, r0) + opset(AVMSUBV, r0) + opset(AVMADDWEVHB, r0) + opset(AVMADDWEVWH, r0) + opset(AVMADDWEVVW, r0) + opset(AVMADDWEVQV, r0) + opset(AVMADDWODHB, r0) + opset(AVMADDWODWH, r0) + opset(AVMADDWODVW, r0) + opset(AVMADDWODQV, r0) + opset(AVMADDWEVHBU, r0) + opset(AVMADDWEVWHU, r0) + opset(AVMADDWEVVWU, r0) + opset(AVMADDWEVQVU, r0) + opset(AVMADDWODHBU, r0) + opset(AVMADDWODWHU, r0) + opset(AVMADDWODVWU, r0) + opset(AVMADDWODQVU, r0) + opset(AVMADDWEVHBUB, r0) + opset(AVMADDWEVWHUH, r0) + opset(AVMADDWEVVWUW, r0) + opset(AVMADDWEVQVUV, r0) + opset(AVMADDWODHBUB, r0) + opset(AVMADDWODWHUH, r0) + opset(AVMADDWODVWUW, r0) + opset(AVMADDWODQVUV, r0) + + // xvadd.b xd, xj, xk + case AXVADDB: + opset(AXVADDH, r0) + opset(AXVADDW, r0) + opset(AXVADDV, r0) + opset(AXVADDQ, r0) + opset(AXVSUBB, r0) + opset(AXVSUBH, r0) + opset(AXVSUBW, r0) + opset(AXVSUBV, r0) + opset(AXVSUBQ, r0) + opset(AXVSADDB, r0) + opset(AXVSADDH, r0) + opset(AXVSADDW, r0) + opset(AXVSADDV, r0) + opset(AXVSSUBB, r0) + opset(AXVSSUBH, r0) + opset(AXVSSUBW, r0) + opset(AXVSSUBV, r0) + opset(AXVSADDBU, r0) + opset(AXVSADDHU, r0) + opset(AXVSADDWU, r0) + opset(AXVSADDVU, r0) + opset(AXVSSUBBU, r0) + opset(AXVSSUBHU, r0) + opset(AXVSSUBWU, r0) + opset(AXVSSUBVU, r0) + opset(AXVANDV, r0) + opset(AXVORV, r0) + opset(AXVXORV, r0) + opset(AXVNORV, r0) + opset(AXVANDNV, r0) + opset(AXVORNV, r0) opset(AXVILVLB, r0) opset(AXVILVLH, r0) opset(AXVILVLW, r0) @@ -1736,39 +1924,75 @@ func buildop(ctxt *obj.Link) { opset(AXVMULD, r0) opset(AXVDIVF, r0) opset(AXVDIVD, r0) - - case AVANDB: - opset(AVORB, r0) - opset(AVXORB, r0) - opset(AVNORB, r0) - opset(AVSHUF4IB, r0) - opset(AVSHUF4IH, r0) - opset(AVSHUF4IW, r0) - opset(AVSHUF4IV, r0) - - case AXVANDB: - opset(AXVORB, r0) - opset(AXVXORB, r0) - opset(AXVNORB, r0) - opset(AXVSHUF4IB, r0) - opset(AXVSHUF4IH, r0) - opset(AXVSHUF4IW, r0) - opset(AXVSHUF4IV, r0) - - case AVANDV: - opset(AVORV, r0) - opset(AVXORV, r0) - opset(AVNORV, r0) - opset(AVANDNV, r0) - opset(AVORNV, r0) - - case AXVANDV: - opset(AXVORV, r0) - opset(AXVXORV, r0) - opset(AXVNORV, r0) - opset(AXVANDNV, r0) - opset(AXVORNV, r0) - + opset(AXVSHUFH, r0) + opset(AXVSHUFW, r0) + opset(AXVSHUFV, r0) + opset(AXVADDWEVHB, r0) + opset(AXVADDWEVWH, r0) + opset(AXVADDWEVVW, r0) + opset(AXVADDWEVQV, r0) + opset(AXVSUBWEVHB, r0) + opset(AXVSUBWEVWH, r0) + opset(AXVSUBWEVVW, r0) + opset(AXVSUBWEVQV, r0) + opset(AXVADDWODHB, r0) + opset(AXVADDWODWH, r0) + opset(AXVADDWODVW, r0) + opset(AXVADDWODQV, r0) + opset(AXVSUBWODHB, r0) + opset(AXVSUBWODWH, r0) + opset(AXVSUBWODVW, r0) + opset(AXVSUBWODQV, r0) + opset(AXVADDWEVHBU, r0) + opset(AXVADDWEVWHU, r0) + opset(AXVADDWEVVWU, r0) + opset(AXVADDWEVQVU, r0) + opset(AXVSUBWEVHBU, r0) + opset(AXVSUBWEVWHU, r0) + opset(AXVSUBWEVVWU, r0) + opset(AXVSUBWEVQVU, r0) + opset(AXVADDWODHBU, r0) + opset(AXVADDWODWHU, r0) + opset(AXVADDWODVWU, r0) + opset(AXVADDWODQVU, r0) + opset(AXVSUBWODHBU, r0) + opset(AXVSUBWODWHU, r0) + opset(AXVSUBWODVWU, r0) + opset(AXVSUBWODQVU, r0) + opset(AXVMADDB, r0) + opset(AXVMADDH, r0) + opset(AXVMADDW, r0) + opset(AXVMADDV, r0) + opset(AXVMSUBB, r0) + opset(AXVMSUBH, r0) + opset(AXVMSUBW, r0) + opset(AXVMSUBV, r0) + opset(AXVMADDWEVHB, r0) + opset(AXVMADDWEVWH, r0) + opset(AXVMADDWEVVW, r0) + opset(AXVMADDWEVQV, r0) + opset(AXVMADDWODHB, r0) + opset(AXVMADDWODWH, r0) + opset(AXVMADDWODVW, r0) + opset(AXVMADDWODQV, r0) + opset(AXVMADDWEVHBU, r0) + opset(AXVMADDWEVWHU, r0) + opset(AXVMADDWEVVWU, r0) + opset(AXVMADDWEVQVU, r0) + opset(AXVMADDWODHBU, r0) + opset(AXVMADDWODWHU, r0) + opset(AXVMADDWODVWU, r0) + opset(AXVMADDWODQVU, r0) + opset(AXVMADDWEVHBUB, r0) + opset(AXVMADDWEVWHUH, r0) + opset(AXVMADDWEVVWUW, r0) + opset(AXVMADDWEVQVUV, r0) + opset(AXVMADDWODHBUB, r0) + opset(AXVMADDWODWHUH, r0) + opset(AXVMADDWODVWUW, r0) + opset(AXVMADDWODQVUV, r0) + + // vpcnt.b vd, vj case AVPCNTB: opset(AVPCNTH, r0) opset(AVPCNTW, r0) @@ -1796,6 +2020,7 @@ func buildop(ctxt *obj.Link) { opset(AVFCLASSF, r0) opset(AVFCLASSD, r0) + // xvpcnt.b xd, xj case AXVPCNTB: opset(AXVPCNTH, r0) opset(AXVPCNTW, r0) @@ -1823,28 +2048,8 @@ func buildop(ctxt *obj.Link) { opset(AXVFCLASSF, r0) opset(AXVFCLASSD, r0) - case AVADDB: - opset(AVADDH, r0) - opset(AVADDW, r0) - opset(AVADDV, r0) - opset(AVADDQ, r0) - opset(AVSUBB, r0) - opset(AVSUBH, r0) - opset(AVSUBW, r0) - opset(AVSUBV, r0) - opset(AVSUBQ, r0) - - case AXVADDB: - opset(AXVADDH, r0) - opset(AXVADDW, r0) - opset(AXVADDV, r0) - opset(AXVADDQ, r0) - opset(AXVSUBB, r0) - opset(AXVSUBH, r0) - opset(AXVSUBW, r0) - opset(AXVSUBV, r0) - opset(AXVSUBQ, r0) - + // vsll.b vd, vj, vk + // vslli.b vd, vj, ui3 case AVSLLB: opset(AVSRLB, r0) opset(AVSRAB, r0) @@ -1853,6 +2058,8 @@ func buildop(ctxt *obj.Link) { opset(AVBITSETB, r0) opset(AVBITREVB, r0) + // xvsll.b xd, xj, xk + // xvslli.b xd, xj, ui3 case AXVSLLB: opset(AXVSRLB, r0) opset(AXVSRAB, r0) @@ -1861,6 +2068,8 @@ func buildop(ctxt *obj.Link) { opset(AXVBITSETB, r0) opset(AXVBITREVB, r0) + // vsll.h vd, vj, vk + // vslli.h vd, vj, ui4 case AVSLLH: opset(AVSRLH, r0) opset(AVSRAH, r0) @@ -1869,6 +2078,8 @@ func buildop(ctxt *obj.Link) { opset(AVBITSETH, r0) opset(AVBITREVH, r0) + // xvsll.h xd, xj, xk + // xvslli.h xd, xj, ui4 case AXVSLLH: opset(AXVSRLH, r0) opset(AXVSRAH, r0) @@ -1877,38 +2088,28 @@ func buildop(ctxt *obj.Link) { opset(AXVBITSETH, r0) opset(AXVBITREVH, r0) + // vsll.w vd, vj, vk + // vslli.w vd, vj, ui5 case AVSLLW: opset(AVSRLW, r0) opset(AVSRAW, r0) opset(AVROTRW, r0) - opset(AVADDBU, r0) - opset(AVADDHU, r0) - opset(AVADDWU, r0) - opset(AVADDVU, r0) - opset(AVSUBBU, r0) - opset(AVSUBHU, r0) - opset(AVSUBWU, r0) - opset(AVSUBVU, r0) opset(AVBITCLRW, r0) opset(AVBITSETW, r0) opset(AVBITREVW, r0) + // xvsll.w xd, xj, xk + // xvslli.w xd, xj, ui5 case AXVSLLW: opset(AXVSRLW, r0) opset(AXVSRAW, r0) opset(AXVROTRW, r0) - opset(AXVADDBU, r0) - opset(AXVADDHU, r0) - opset(AXVADDWU, r0) - opset(AXVADDVU, r0) - opset(AXVSUBBU, r0) - opset(AXVSUBHU, r0) - opset(AXVSUBWU, r0) - opset(AXVSUBVU, r0) opset(AXVBITCLRW, r0) opset(AXVBITSETW, r0) opset(AXVBITREVW, r0) + // vsll.d vd, vj, vk + // vslli.d vd, vj, ui6 case AVSLLV: opset(AVSRLV, r0) opset(AVSRAV, r0) @@ -1917,6 +2118,8 @@ func buildop(ctxt *obj.Link) { opset(AVBITSETV, r0) opset(AVBITREVV, r0) + // xvsll.d xd, xj, xk + // xvslli.d xd, xj, ui6 case AXVSLLV: opset(AXVSRLV, r0) opset(AXVSRAV, r0) @@ -1925,6 +2128,27 @@ func buildop(ctxt *obj.Link) { opset(AXVBITSETV, r0) opset(AXVBITREVV, r0) + // vaddi.bu vd, vj, ui5 + case AVADDBU: + opset(AVADDHU, r0) + opset(AVADDWU, r0) + opset(AVADDVU, r0) + opset(AVSUBBU, r0) + opset(AVSUBHU, r0) + opset(AVSUBWU, r0) + opset(AVSUBVU, r0) + + // xvaddi.bu xd, xj, ui5 + case AXVADDBU: + opset(AXVADDHU, r0) + opset(AXVADDWU, r0) + opset(AXVADDVU, r0) + opset(AXVSUBBU, r0) + opset(AXVSUBHU, r0) + opset(AXVSUBWU, r0) + opset(AXVSUBVU, r0) + + // vseteqz.v cd, vj case AVSETEQV: opset(AVSETNEV, r0) opset(AVSETANYEQB, r0) @@ -1936,6 +2160,7 @@ func buildop(ctxt *obj.Link) { opset(AVSETALLNEW, r0) opset(AVSETALLNEV, r0) + // xvseteqz.v cd, xj case AXVSETEQV: opset(AXVSETNEV, r0) opset(AXVSETANYEQB, r0) @@ -2051,9 +2276,9 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { o3 := uint32(0) o4 := uint32(0) o5 := uint32(0) + o6 := uint32(0) - add := AADDU - add = AADDVU + add := AADDVU switch o.type_ { default: @@ -2063,12 +2288,29 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { case 0: // pseudo ops break - case 1: // mov r1,r2 ==> OR r1,r0,r2 - a := AOR - if p.As == AMOVW { - a = ASLL + case 1: // mov rj, rd + switch p.As { + case AMOVB: + o1 = OP_RR(c.oprr(AEXTWB), uint32(p.From.Reg), uint32(p.To.Reg)) + case AMOVH: + o1 = OP_RR(c.oprr(AEXTWH), uint32(p.From.Reg), uint32(p.To.Reg)) + case AMOVW: + o1 = OP_RRR(c.oprrr(ASLL), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg)) + case AMOVV: + o1 = OP_RRR(c.oprrr(AOR), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg)) + case AMOVBU: + o1 = OP_12IRR(c.opirr(AAND), uint32(0xff), uint32(p.From.Reg), uint32(p.To.Reg)) + case AMOVHU: + o1 = OP_IRIR(c.opirir(ABSTRPICKV), 15, uint32(p.From.Reg), 0, uint32(p.To.Reg)) + case AMOVWU: + o1 = OP_IRIR(c.opirir(ABSTRPICKV), 31, uint32(p.From.Reg), 0, uint32(p.To.Reg)) + case AVMOVQ: + o1 = OP_6IRR(c.opirr(AVSLLV), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg)) + case AXVMOVQ: + o1 = OP_6IRR(c.opirr(AXVSLLV), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg)) + default: + c.ctxt.Diag("unexpected encoding\n%v", p) } - o1 = OP_RRR(c.oprrr(a), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg)) case 2: // add/sub r1,[r2],r3 r := int(p.Reg) @@ -2177,7 +2419,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { v := c.regoff(&p.From) a := AOR if v < 0 { - a = AADDU + a = AADD } o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP)) r := int(p.Reg) @@ -2190,6 +2432,9 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { v := int32(0) if p.To.Target() != nil { v = int32(p.To.Target().Pc-p.Pc) >> 2 + if v < -1<<25 || v >= 1<<25 { + c.ctxt.Diag("branch too far \n%v", p) + } } o1 = OP_B_BL(c.opirr(p.As), uint32(v)) if p.To.Sym != nil { @@ -2202,22 +2447,6 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { }) } - case 12: // movbs r,r - switch p.As { - case AMOVB: - o1 = OP_RR(c.oprr(AEXTWB), uint32(p.From.Reg), uint32(p.To.Reg)) - case AMOVH: - o1 = OP_RR(c.oprr(AEXTWH), uint32(p.From.Reg), uint32(p.To.Reg)) - case AMOVBU: - o1 = OP_12IRR(c.opirr(AAND), uint32(0xff), uint32(p.From.Reg), uint32(p.To.Reg)) - case AMOVHU: - o1 = OP_IRIR(c.opirir(ABSTRPICKV), 15, uint32(p.From.Reg), 0, uint32(p.To.Reg)) - case AMOVWU: - o1 = OP_IRIR(c.opirir(ABSTRPICKV), 31, uint32(p.From.Reg), 0, uint32(p.To.Reg)) - default: - c.ctxt.Diag("unexpected encoding\n%v", p) - } - case 13: // vsll $ui3, [vr1], vr2 v := c.regoff(&p.From) r := int(p.Reg) @@ -2436,7 +2665,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { case 34: // mov $con,fr v := c.regoff(&p.From) - a := AADDU + a := AADD if v > 0 { a = AOR } @@ -2480,11 +2709,11 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { c.ctxt.Diag("illegal arng type combination: %v\n", p) } - Rj := uint32(p.From.Reg & EXT_REG_MASK) - Vd := uint32(p.To.Reg & EXT_REG_MASK) + rj := uint32(p.From.Reg & EXT_REG_MASK) + rd := uint32(p.To.Reg & EXT_REG_MASK) index := uint32(p.To.Index) c.checkindex(p, index, m) - o1 = v | (index << 10) | (Rj << 5) | Vd + o1 = v | (index << 10) | (rj << 5) | rd case 40: // vmov Vd.[index], Rn v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false) @@ -2492,11 +2721,11 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { c.ctxt.Diag("illegal arng type combination: %v\n", p) } - Vj := uint32(p.From.Reg & EXT_REG_MASK) - Rd := uint32(p.To.Reg & EXT_REG_MASK) + rj := uint32(p.From.Reg & EXT_REG_MASK) + rd := uint32(p.To.Reg & EXT_REG_MASK) index := uint32(p.From.Index) c.checkindex(p, index, m) - o1 = v | (index << 10) | (Vj << 5) | Rd + o1 = v | (index << 10) | (rj << 5) | rd case 41: // vmov Rn, Vd. v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false) @@ -2504,57 +2733,11 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { c.ctxt.Diag("illegal arng type combination: %v\n", p) } - Rj := uint32(p.From.Reg & EXT_REG_MASK) - Vd := uint32(p.To.Reg & EXT_REG_MASK) - o1 = v | (Rj << 5) | Vd - - case 42: // vmov xj, xd. - v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false) - if v == 0 { - c.ctxt.Diag("illegal arng type combination: %v\n", p) - } - - Xj := uint32(p.From.Reg & EXT_REG_MASK) - Xd := uint32(p.To.Reg & EXT_REG_MASK) - o1 = v | (Xj << 5) | Xd - - case 43: // vmov xj, xd.[index] - v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false) - if v == 0 { - c.ctxt.Diag("illegal arng type combination: %v\n", p) - } - - Xj := uint32(p.From.Reg & EXT_REG_MASK) - Xd := uint32(p.To.Reg & EXT_REG_MASK) - index := uint32(p.To.Index) - c.checkindex(p, index, m) - o1 = v | (index << 10) | (Xj << 5) | Xd - - case 44: // vmov xj.[index], xd - v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false) - if v == 0 { - c.ctxt.Diag("illegal arng type combination: %v\n", p) - } - - Xj := uint32(p.From.Reg & EXT_REG_MASK) - Xd := uint32(p.To.Reg & EXT_REG_MASK) - index := uint32(p.From.Index) - c.checkindex(p, index, m) - o1 = v | (index << 10) | (Xj << 5) | Xd - - case 45: // vmov vj.[index], vd. - v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false) - if v == 0 { - c.ctxt.Diag("illegal arng type combination: %v\n", p) - } - - vj := uint32(p.From.Reg & EXT_REG_MASK) - vd := uint32(p.To.Reg & EXT_REG_MASK) - index := uint32(p.From.Index) - c.checkindex(p, index, m) - o1 = v | (index << 10) | (vj << 5) | vd + rj := uint32(p.From.Reg & EXT_REG_MASK) + rd := uint32(p.To.Reg & EXT_REG_MASK) + o1 = v | (rj << 5) | rd - case 46: // vmov offset(vj), vd. + case 42: // vmov offset(vj), vd. v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, true) if v == 0 { c.ctxt.Diag("illegal arng type combination: %v\n", p) @@ -2586,6 +2769,23 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { } } + case 45: + // sc.q rd, rk, (rj) + o1 = OP_RRR(c.oprrr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) + + case 46: + // ll.acq.{w/d} (rj), rd + rj := uint32(p.From.Reg) + rd := uint32(p.To.Reg) + + switch p.As { + case ASCRELW, ASCRELV: + rj = uint32(p.To.Reg) + rd = uint32(p.From.Reg) + } + + o1 = OP_RR(c.oprr(p.As), rj, rd) + case 47: // preld offset(Rbase), $hint offs := c.regoff(&p.From) hint := p.GetFrom3().Offset @@ -2606,7 +2806,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { } if blkNums > 256 { - c.ctxt.Diag("%v: block_nums amount out of range[1, 256]: %v\n", p, blkSize) + c.ctxt.Diag("%v: block_nums amount out of range[1, 256]: %v\n", p, blkNums) } v := (uint64(offs) & 0xffff) @@ -2955,18 +3155,51 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { o4 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg)) case 73: - v := c.regoff(&p.To) + v := c.vregoff(&p.To) + r := p.To.Reg if v&3 != 0 { c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p) } - o1 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(p.To.Reg), uint32(p.From.Reg)) + + switch o.size { + case 4: // 16 bit + o1 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(r), uint32(p.From.Reg)) + case 12: // 32 bit + o1 = OP_16IRR(c.opirr(AADDV16), uint32(v>>16), uint32(REG_R0), uint32(REGTMP)) + o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP)) + o3 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(REGTMP), uint32(p.From.Reg)) + case 24: // 64 bit + o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP)) + o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP)) + o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP)) + o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP)) + o5 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(r)) + o6 = OP_14IRR(c.opirr(p.As), uint32(0), uint32(r), uint32(p.From.Reg)) + } case 74: - v := c.regoff(&p.From) + v := c.vregoff(&p.From) + r := p.From.Reg if v&3 != 0 { c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p) } - o1 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(p.From.Reg), uint32(p.To.Reg)) + + switch o.size { + case 4: // 16 bit + o1 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(r), uint32(p.To.Reg)) + case 12: // 32 bit + o1 = OP_16IRR(c.opirr(AADDV16), uint32(v>>16), uint32(REG_R0), uint32(REGTMP)) + o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP)) + o3 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(REGTMP), uint32(p.To.Reg)) + case 24: // 64 bit + o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP)) + o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP)) + o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP)) + o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP)) + o5 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(r)) + o6 = OP_14IRR(c.opirr(p.As), uint32(0), uint32(r), uint32(p.To.Reg)) + } + } out[0] = o1 @@ -2974,6 +3207,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { out[2] = o3 out[3] = o4 out[4] = o5 + out[5] = o6 } // checkoperand checks if operand >= 0 && operand <= maxoperand @@ -3001,1639 +3235,86 @@ func (c *ctxt0) regoff(a *obj.Addr) int32 { } func (c *ctxt0) oprrrr(a obj.As) uint32 { - switch a { - case AFMADDF: - return 0x81 << 20 // fmadd.s - case AFMADDD: - return 0x82 << 20 // fmadd.d - case AFMSUBF: - return 0x85 << 20 // fmsub.s - case AFMSUBD: - return 0x86 << 20 // fmsub.d - case AFNMADDF: - return 0x89 << 20 // fnmadd.f - case AFNMADDD: - return 0x8a << 20 // fnmadd.d - case AFNMSUBF: - return 0x8d << 20 // fnmsub.s - case AFNMSUBD: - return 0x8e << 20 // fnmsub.d + op, ok := oprrrr[a] + if ok { + return op } - c.ctxt.Diag("bad rrrr opcode %v", a) return 0 } func (c *ctxt0) oprrr(a obj.As) uint32 { - switch a { - case AADD: - return 0x20 << 15 - case AADDU: - return 0x20 << 15 - case ASGT: - return 0x24 << 15 // SLT - case ASGTU: - return 0x25 << 15 // SLTU - case AMASKEQZ: - return 0x26 << 15 - case AMASKNEZ: - return 0x27 << 15 - case AAND: - return 0x29 << 15 - case AOR: - return 0x2a << 15 - case AXOR: - return 0x2b << 15 - case AORN: - return 0x2c << 15 // orn - case AANDN: - return 0x2d << 15 // andn - case ASUB: - return 0x22 << 15 - case ASUBU, ANEGW: - return 0x22 << 15 - case ANOR: - return 0x28 << 15 - case ASLL: - return 0x2e << 15 - case ASRL: - return 0x2f << 15 - case ASRA: - return 0x30 << 15 - case AROTR: - return 0x36 << 15 - case ASLLV: - return 0x31 << 15 - case ASRLV: - return 0x32 << 15 - case ASRAV: - return 0x33 << 15 - case AROTRV: - return 0x37 << 15 - case AADDV: - return 0x21 << 15 - case AADDVU: - return 0x21 << 15 - case ASUBV: - return 0x23 << 15 - case ASUBVU, ANEGV: - return 0x23 << 15 - - case AMUL: - return 0x38 << 15 // mul.w - case AMULU: - return 0x38 << 15 // mul.w - case AMULH: - return 0x39 << 15 // mulh.w - case AMULHU: - return 0x3a << 15 // mulhu.w - case AMULV: - return 0x3b << 15 // mul.d - case AMULVU: - return 0x3b << 15 // mul.d - case AMULHV: - return 0x3c << 15 // mulh.d - case AMULHVU: - return 0x3d << 15 // mulhu.d - case ADIV: - return 0x40 << 15 // div.w - case ADIVU: - return 0x42 << 15 // div.wu - case ADIVV: - return 0x44 << 15 // div.d - case ADIVVU: - return 0x46 << 15 // div.du - case AREM: - return 0x41 << 15 // mod.w - case AREMU: - return 0x43 << 15 // mod.wu - case AREMV: - return 0x45 << 15 // mod.d - case AREMVU: - return 0x47 << 15 // mod.du - case ACRCWBW: - return 0x48 << 15 // crc.w.b.w - case ACRCWHW: - return 0x49 << 15 // crc.w.h.w - case ACRCWWW: - return 0x4a << 15 // crc.w.w.w - case ACRCWVW: - return 0x4b << 15 // crc.w.d.w - case ACRCCWBW: - return 0x4c << 15 // crcc.w.b.w - case ACRCCWHW: - return 0x4d << 15 // crcc.w.h.w - case ACRCCWWW: - return 0x4e << 15 // crcc.w.w.w - case ACRCCWVW: - return 0x4f << 15 // crcc.w.d.w - case AJMP: - return 0x13 << 26 // jirl r0, rj, 0 - case AJAL: - return (0x13 << 26) | 1 // jirl r1, rj, 0 - - case ADIVF: - return 0x20d << 15 - case ADIVD: - return 0x20e << 15 - case AMULF: - return 0x209 << 15 - case AMULD: - return 0x20a << 15 - case ASUBF: - return 0x205 << 15 - case ASUBD: - return 0x206 << 15 - case AADDF: - return 0x201 << 15 - case AADDD: - return 0x202 << 15 - case ACMPEQF: - return 0x0c1<<20 | 0x4<<15 // FCMP.CEQ.S - case ACMPEQD: - return 0x0c2<<20 | 0x4<<15 // FCMP.CEQ.D - case ACMPGED: - return 0x0c2<<20 | 0x7<<15 // FCMP.SLE.D - case ACMPGEF: - return 0x0c1<<20 | 0x7<<15 // FCMP.SLE.S - case ACMPGTD: - return 0x0c2<<20 | 0x3<<15 // FCMP.SLT.D - case ACMPGTF: - return 0x0c1<<20 | 0x3<<15 // FCMP.SLT.S - case AFMINF: - return 0x215 << 15 // fmin.s - case AFMIND: - return 0x216 << 15 // fmin.d - case AFMAXF: - return 0x211 << 15 // fmax.s - case AFMAXD: - return 0x212 << 15 // fmax.d - case AFMAXAF: - return 0x219 << 15 // fmaxa.s - case AFMAXAD: - return 0x21a << 15 // fmaxa.d - case AFMINAF: - return 0x21d << 15 // fmina.s - case AFMINAD: - return 0x21e << 15 // fmina.d - case AFSCALEBF: - return 0x221 << 15 // fscaleb.s - case AFSCALEBD: - return 0x222 << 15 // fscaleb.d - case AFCOPYSGF: - return 0x225 << 15 // fcopysign.s - case AFCOPYSGD: - return 0x226 << 15 // fcopysign.d - case -AMOVB: - return 0x07000 << 15 // ldx.b - case -AMOVH: - return 0x07008 << 15 // ldx.h - case -AMOVW: - return 0x07010 << 15 // ldx.w - case -AMOVV: - return 0x07018 << 15 // ldx.d - case -AMOVBU: - return 0x07040 << 15 // ldx.bu - case -AMOVHU: - return 0x07048 << 15 // ldx.hu - case -AMOVWU: - return 0x07050 << 15 // ldx.wu - case AMOVB: - return 0x07020 << 15 // stx.b - case AMOVH: - return 0x07028 << 15 // stx.h - case AMOVW: - return 0x07030 << 15 // stx.w - case AMOVV: - return 0x07038 << 15 // stx.d - case -AMOVF: - return 0x07060 << 15 // fldx.s - case -AMOVD: - return 0x07068 << 15 // fldx.d - case AMOVF: - return 0x07070 << 15 // fstx.s - case AMOVD: - return 0x07078 << 15 // fstx.d - case -AVMOVQ: - return 0x07080 << 15 // vldx - case -AXVMOVQ: - return 0x07090 << 15 // xvldx - case AVMOVQ: - return 0x07088 << 15 // vstx - case AXVMOVQ: - return 0x07098 << 15 // xvstx - case AVSEQB: - return 0x0e000 << 15 // vseq.b - case AXVSEQB: - return 0x0e800 << 15 // xvseq.b - case AVSEQH: - return 0x0e001 << 15 // vseq.h - case AXVSEQH: - return 0x0e801 << 15 // xvseq.h - case AVSEQW: - return 0x0e002 << 15 // vseq.w - case AXVSEQW: - return 0x0e802 << 15 // xvseq.w - case AVSEQV: - return 0x0e003 << 15 // vseq.d - case AXVSEQV: - return 0x0e803 << 15 // xvseq.d - case AVANDV: - return 0x0E24C << 15 // vand.v - case AVORV: - return 0x0E24D << 15 // vor.v - case AVXORV: - return 0x0E24E << 15 // vxor.v - case AVNORV: - return 0x0E24F << 15 // vnor.v - case AVANDNV: - return 0x0E250 << 15 // vandn.v - case AVORNV: - return 0x0E251 << 15 // vorn.v - case AXVANDV: - return 0x0EA4C << 15 // xvand.v - case AXVORV: - return 0x0EA4D << 15 // xvor.v - case AXVXORV: - return 0x0EA4E << 15 // xvxor.v - case AXVNORV: - return 0x0EA4F << 15 // xvnor.v - case AXVANDNV: - return 0x0EA50 << 15 // xvandn.v - case AXVORNV: - return 0x0EA51 << 15 // xvorn.v - case AVDIVB: - return 0xe1c0 << 15 // vdiv.b - case AVDIVH: - return 0xe1c1 << 15 // vdiv.h - case AVDIVW: - return 0xe1c2 << 15 // vdiv.w - case AVDIVV: - return 0xe1c3 << 15 // vdiv.d - case AVMODB: - return 0xe1c4 << 15 // vmod.b - case AVMODH: - return 0xe1c5 << 15 // vmod.h - case AVMODW: - return 0xe1c6 << 15 // vmod.w - case AVMODV: - return 0xe1c7 << 15 // vmod.d - case AVDIVBU: - return 0xe1c8 << 15 // vdiv.bu - case AVDIVHU: - return 0xe1c9 << 15 // vdiv.hu - case AVDIVWU: - return 0xe1ca << 15 // vdiv.wu - case AVDIVVU: - return 0xe1cb << 15 // vdiv.du - case AVMODBU: - return 0xe1cc << 15 // vmod.bu - case AVMODHU: - return 0xe1cd << 15 // vmod.hu - case AVMODWU: - return 0xe1ce << 15 // vmod.wu - case AVMODVU: - return 0xe1cf << 15 // vmod.du - case AXVDIVB: - return 0xe9c0 << 15 // xvdiv.b - case AXVDIVH: - return 0xe9c1 << 15 // xvdiv.h - case AXVDIVW: - return 0xe9c2 << 15 // xvdiv.w - case AXVDIVV: - return 0xe9c3 << 15 // xvdiv.d - case AXVMODB: - return 0xe9c4 << 15 // xvmod.b - case AXVMODH: - return 0xe9c5 << 15 // xvmod.h - case AXVMODW: - return 0xe9c6 << 15 // xvmod.w - case AXVMODV: - return 0xe9c7 << 15 // xvmod.d - case AXVDIVBU: - return 0xe9c8 << 15 // xvdiv.bu - case AXVDIVHU: - return 0xe9c9 << 15 // xvdiv.hu - case AXVDIVWU: - return 0xe9ca << 15 // xvdiv.wu - case AXVDIVVU: - return 0xe9cb << 15 // xvdiv.du - case AXVMODBU: - return 0xe9cc << 15 // xvmod.bu - case AXVMODHU: - return 0xe9cd << 15 // xvmod.hu - case AXVMODWU: - return 0xe9ce << 15 // xvmod.wu - case AXVMODVU: - return 0xe9cf << 15 // xvmod.du - case AVMULWEVHB: - return 0xe120 << 15 // vmulwev.h.b - case AVMULWEVWH: - return 0xe121 << 15 // vmulwev.w.h - case AVMULWEVVW: - return 0xe122 << 15 // vmulwev.d.w - case AVMULWEVQV: - return 0xe123 << 15 // vmulwev.q.d - case AVMULWODHB: - return 0xe124 << 15 // vmulwod.h.b - case AVMULWODWH: - return 0xe125 << 15 // vmulwod.w.h - case AVMULWODVW: - return 0xe126 << 15 // vmulwod.d.w - case AVMULWODQV: - return 0xe127 << 15 // vmulwod.q.d - case AVMULWEVHBU: - return 0xe130 << 15 // vmulwev.h.bu - case AVMULWEVWHU: - return 0xe131 << 15 // vmulwev.w.hu - case AVMULWEVVWU: - return 0xe132 << 15 // vmulwev.d.wu - case AVMULWEVQVU: - return 0xe133 << 15 // vmulwev.q.du - case AVMULWODHBU: - return 0xe134 << 15 // vmulwod.h.bu - case AVMULWODWHU: - return 0xe135 << 15 // vmulwod.w.hu - case AVMULWODVWU: - return 0xe136 << 15 // vmulwod.d.wu - case AVMULWODQVU: - return 0xe137 << 15 // vmulwod.q.du - case AVMULWEVHBUB: - return 0xe140 << 15 // vmulwev.h.bu.b - case AVMULWEVWHUH: - return 0xe141 << 15 // vmulwev.w.hu.h - case AVMULWEVVWUW: - return 0xe142 << 15 // vmulwev.d.wu.w - case AVMULWEVQVUV: - return 0xe143 << 15 // vmulwev.q.du.d - case AVMULWODHBUB: - return 0xe144 << 15 // vmulwod.h.bu.b - case AVMULWODWHUH: - return 0xe145 << 15 // vmulwod.w.hu.h - case AVMULWODVWUW: - return 0xe146 << 15 // vmulwod.d.wu.w - case AVMULWODQVUV: - return 0xe147 << 15 // vmulwod.q.du.d - case AXVMULWEVHB: - return 0xe920 << 15 // xvmulwev.h.b - case AXVMULWEVWH: - return 0xe921 << 15 // xvmulwev.w.h - case AXVMULWEVVW: - return 0xe922 << 15 // xvmulwev.d.w - case AXVMULWEVQV: - return 0xe923 << 15 // xvmulwev.q.d - case AXVMULWODHB: - return 0xe924 << 15 // xvmulwod.h.b - case AXVMULWODWH: - return 0xe925 << 15 // xvmulwod.w.h - case AXVMULWODVW: - return 0xe926 << 15 // xvmulwod.d.w - case AXVMULWODQV: - return 0xe927 << 15 // xvmulwod.q.d - case AXVMULWEVHBU: - return 0xe930 << 15 // xvmulwev.h.bu - case AXVMULWEVWHU: - return 0xe931 << 15 // xvmulwev.w.hu - case AXVMULWEVVWU: - return 0xe932 << 15 // xvmulwev.d.wu - case AXVMULWEVQVU: - return 0xe933 << 15 // xvmulwev.q.du - case AXVMULWODHBU: - return 0xe934 << 15 // xvmulwod.h.bu - case AXVMULWODWHU: - return 0xe935 << 15 // xvmulwod.w.hu - case AXVMULWODVWU: - return 0xe936 << 15 // xvmulwod.d.wu - case AXVMULWODQVU: - return 0xe937 << 15 // xvmulwod.q.du - case AXVMULWEVHBUB: - return 0xe940 << 15 // xvmulwev.h.bu.b - case AXVMULWEVWHUH: - return 0xe941 << 15 // xvmulwev.w.hu.h - case AXVMULWEVVWUW: - return 0xe942 << 15 // xvmulwev.d.wu.w - case AXVMULWEVQVUV: - return 0xe943 << 15 // xvmulwev.q.du.d - case AXVMULWODHBUB: - return 0xe944 << 15 // xvmulwod.h.bu.b - case AXVMULWODWHUH: - return 0xe945 << 15 // xvmulwod.w.hu.h - case AXVMULWODVWUW: - return 0xe946 << 15 // xvmulwod.d.wu.w - case AXVMULWODQVUV: - return 0xe947 << 15 // xvmulwod.q.du.d - case AVSLLB: - return 0xe1d0 << 15 // vsll.b - case AVSLLH: - return 0xe1d1 << 15 // vsll.h - case AVSLLW: - return 0xe1d2 << 15 // vsll.w - case AVSLLV: - return 0xe1d3 << 15 // vsll.d - case AVSRLB: - return 0xe1d4 << 15 // vsrl.b - case AVSRLH: - return 0xe1d5 << 15 // vsrl.h - case AVSRLW: - return 0xe1d6 << 15 // vsrl.w - case AVSRLV: - return 0xe1d7 << 15 // vsrl.d - case AVSRAB: - return 0xe1d8 << 15 // vsra.b - case AVSRAH: - return 0xe1d9 << 15 // vsra.h - case AVSRAW: - return 0xe1da << 15 // vsra.w - case AVSRAV: - return 0xe1db << 15 // vsra.d - case AVROTRB: - return 0xe1dc << 15 // vrotr.b - case AVROTRH: - return 0xe1dd << 15 // vrotr.h - case AVROTRW: - return 0xe1de << 15 // vrotr.w - case AVROTRV: - return 0xe1df << 15 // vrotr.d - case AXVSLLB: - return 0xe9d0 << 15 // xvsll.b - case AXVSLLH: - return 0xe9d1 << 15 // xvsll.h - case AXVSLLW: - return 0xe9d2 << 15 // xvsll.w - case AXVSLLV: - return 0xe9d3 << 15 // xvsll.d - case AXVSRLB: - return 0xe9d4 << 15 // xvsrl.b - case AXVSRLH: - return 0xe9d5 << 15 // xvsrl.h - case AXVSRLW: - return 0xe9d6 << 15 // xvsrl.w - case AXVSRLV: - return 0xe9d7 << 15 // xvsrl.d - case AXVSRAB: - return 0xe9d8 << 15 // xvsra.b - case AXVSRAH: - return 0xe9d9 << 15 // xvsra.h - case AXVSRAW: - return 0xe9da << 15 // xvsra.w - case AXVSRAV: - return 0xe9db << 15 // xvsra.d - case AXVROTRB: - return 0xe9dc << 15 // xvrotr.b - case AXVROTRH: - return 0xe9dd << 15 // xvrotr.h - case AXVROTRW: - return 0xe9de << 15 // xvrotr.w - case AXVROTRV: - return 0xe9df << 15 // xvrotr.d - case AVADDB: - return 0xe014 << 15 // vadd.b - case AVADDH: - return 0xe015 << 15 // vadd.h - case AVADDW: - return 0xe016 << 15 // vadd.w - case AVADDV: - return 0xe017 << 15 // vadd.d - case AVADDQ: - return 0xe25a << 15 // vadd.q - case AVSUBB: - return 0xe018 << 15 // vsub.b - case AVSUBH: - return 0xe019 << 15 // vsub.h - case AVSUBW: - return 0xe01a << 15 // vsub.w - case AVSUBV: - return 0xe01b << 15 // vsub.d - case AVSUBQ: - return 0xe25b << 15 // vsub.q - case AXVADDB: - return 0xe814 << 15 // xvadd.b - case AXVADDH: - return 0xe815 << 15 // xvadd.h - case AXVADDW: - return 0xe816 << 15 // xvadd.w - case AXVADDV: - return 0xe817 << 15 // xvadd.d - case AXVADDQ: - return 0xea5a << 15 // xvadd.q - case AXVSUBB: - return 0xe818 << 15 // xvsub.b - case AXVSUBH: - return 0xe819 << 15 // xvsub.h - case AXVSUBW: - return 0xe81a << 15 // xvsub.w - case AXVSUBV: - return 0xe81b << 15 // xvsub.d - case AXVSUBQ: - return 0xea5b << 15 // xvsub.q - case AVILVLB: - return 0xe234 << 15 // vilvl.b - case AVILVLH: - return 0xe235 << 15 // vilvl.h - case AVILVLW: - return 0xe236 << 15 // vilvl.w - case AVILVLV: - return 0xe237 << 15 // vilvl.d - case AVILVHB: - return 0xe238 << 15 // vilvh.b - case AVILVHH: - return 0xe239 << 15 // vilvh.h - case AVILVHW: - return 0xe23a << 15 // vilvh.w - case AVILVHV: - return 0xe23b << 15 // vilvh.d - case AXVILVLB: - return 0xea34 << 15 // xvilvl.b - case AXVILVLH: - return 0xea35 << 15 // xvilvl.h - case AXVILVLW: - return 0xea36 << 15 // xvilvl.w - case AXVILVLV: - return 0xea37 << 15 // xvilvl.d - case AXVILVHB: - return 0xea38 << 15 // xvilvh.b - case AXVILVHH: - return 0xea39 << 15 // xvilvh.h - case AXVILVHW: - return 0xea3a << 15 // xvilvh.w - case AXVILVHV: - return 0xea3b << 15 // xvilvh.d - case AVMULB: - return 0xe108 << 15 // vmul.b - case AVMULH: - return 0xe109 << 15 // vmul.h - case AVMULW: - return 0xe10a << 15 // vmul.w - case AVMULV: - return 0xe10b << 15 // vmul.d - case AVMUHB: - return 0xe10c << 15 // vmuh.b - case AVMUHH: - return 0xe10d << 15 // vmuh.h - case AVMUHW: - return 0xe10e << 15 // vmuh.w - case AVMUHV: - return 0xe10f << 15 // vmuh.d - case AVMUHBU: - return 0xe110 << 15 // vmuh.bu - case AVMUHHU: - return 0xe111 << 15 // vmuh.hu - case AVMUHWU: - return 0xe112 << 15 // vmuh.wu - case AVMUHVU: - return 0xe113 << 15 // vmuh.du - case AXVMULB: - return 0xe908 << 15 // xvmul.b - case AXVMULH: - return 0xe909 << 15 // xvmul.h - case AXVMULW: - return 0xe90a << 15 // xvmul.w - case AXVMULV: - return 0xe90b << 15 // xvmul.d - case AXVMUHB: - return 0xe90c << 15 // xvmuh.b - case AXVMUHH: - return 0xe90d << 15 // xvmuh.h - case AXVMUHW: - return 0xe90e << 15 // xvmuh.w - case AXVMUHV: - return 0xe90f << 15 // xvmuh.d - case AXVMUHBU: - return 0xe910 << 15 // xvmuh.bu - case AXVMUHHU: - return 0xe911 << 15 // xvmuh.hu - case AXVMUHWU: - return 0xe912 << 15 // xvmuh.wu - case AXVMUHVU: - return 0xe913 << 15 // xvmuh.du - case AVADDF: - return 0xe261 << 15 // vfadd.s - case AVADDD: - return 0xe262 << 15 // vfadd.d - case AVSUBF: - return 0xe265 << 15 // vfsub.s - case AVSUBD: - return 0xe266 << 15 // vfsub.d - case AVMULF: - return 0xe271 << 15 // vfmul.s - case AVMULD: - return 0xe272 << 15 // vfmul.d - case AVDIVF: - return 0xe275 << 15 // vfdiv.s - case AVDIVD: - return 0xe276 << 15 // vfdiv.d - case AXVADDF: - return 0xea61 << 15 // xvfadd.s - case AXVADDD: - return 0xea62 << 15 // xvfadd.d - case AXVSUBF: - return 0xea65 << 15 // xvfsub.s - case AXVSUBD: - return 0xea66 << 15 // xvfsub.d - case AXVMULF: - return 0xea71 << 15 // xvfmul.s - case AXVMULD: - return 0xea72 << 15 // xvfmul.d - case AXVDIVF: - return 0xea75 << 15 // xvfdiv.s - case AXVDIVD: - return 0xea76 << 15 // xvfdiv.d - case AVBITCLRB: - return 0xe218 << 15 // vbitclr.b - case AVBITCLRH: - return 0xe219 << 15 // vbitclr.h - case AVBITCLRW: - return 0xe21a << 15 // vbitclr.w - case AVBITCLRV: - return 0xe21b << 15 // vbitclr.d - case AVBITSETB: - return 0xe21c << 15 // vbitset.b - case AVBITSETH: - return 0xe21d << 15 // vbitset.h - case AVBITSETW: - return 0xe21e << 15 // vbitset.w - case AVBITSETV: - return 0xe21f << 15 // vbitset.d - case AVBITREVB: - return 0xe220 << 15 // vbitrev.b - case AVBITREVH: - return 0xe221 << 15 // vbitrev.h - case AVBITREVW: - return 0xe222 << 15 // vbitrev.w - case AVBITREVV: - return 0xe223 << 15 // vbitrev.d - case AXVBITCLRB: - return 0xea18 << 15 // xvbitclr.b - case AXVBITCLRH: - return 0xea19 << 15 // xvbitclr.h - case AXVBITCLRW: - return 0xea1a << 15 // xvbitclr.w - case AXVBITCLRV: - return 0xea1b << 15 // xvbitclr.d - case AXVBITSETB: - return 0xea1c << 15 // xvbitset.b - case AXVBITSETH: - return 0xea1d << 15 // xvbitset.h - case AXVBITSETW: - return 0xea1e << 15 // xvbitset.w - case AXVBITSETV: - return 0xea1f << 15 // xvbitset.d - case AXVBITREVB: - return 0xea20 << 15 // xvbitrev.b - case AXVBITREVH: - return 0xea21 << 15 // xvbitrev.h - case AXVBITREVW: - return 0xea22 << 15 // xvbitrev.w - case AXVBITREVV: - return 0xea23 << 15 // xvbitrev.d - } - - if a < 0 { - c.ctxt.Diag("bad rrr opcode -%v", -a) - } else { - c.ctxt.Diag("bad rrr opcode %v", a) + op, ok := oprrr[a] + if ok { + return op } + c.ctxt.Diag("bad rrr opcode %v", a) return 0 } func (c *ctxt0) oprr(a obj.As) uint32 { - switch a { - case ACLOW: - return 0x4 << 10 // clo.w - case ACLZW: - return 0x5 << 10 // clz.w - case ACTOW: - return 0x6 << 10 // cto.w - case ACTZW: - return 0x7 << 10 // ctz.w - case ACLOV: - return 0x8 << 10 // clo.d - case ACLZV: - return 0x9 << 10 // clz.d - case ACTOV: - return 0xa << 10 // cto.d - case ACTZV: - return 0xb << 10 // ctz.d - case AREVB2H: - return 0xc << 10 // revb.2h - case AREVB4H: - return 0xd << 10 // revb.4h - case AREVB2W: - return 0xe << 10 // revb.2w - case AREVBV: - return 0xf << 10 // revb.d - case AREVH2W: - return 0x10 << 10 // revh.2w - case AREVHV: - return 0x11 << 10 // revh.d - case ABITREV4B: - return 0x12 << 10 // bitrev.4b - case ABITREV8B: - return 0x13 << 10 // bitrev.8b - case ABITREVW: - return 0x14 << 10 // bitrev.w - case ABITREVV: - return 0x15 << 10 // bitrev.d - case AEXTWH: - return 0x16 << 10 // ext.w.h - case AEXTWB: - return 0x17 << 10 // ext.w.h - case ACPUCFG: - return 0x1b << 10 - case ARDTIMELW: - return 0x18 << 10 - case ARDTIMEHW: - return 0x19 << 10 - case ARDTIMED: - return 0x1a << 10 - case ATRUNCFV: - return 0x46a9 << 10 - case ATRUNCDV: - return 0x46aa << 10 - case ATRUNCFW: - return 0x46a1 << 10 - case ATRUNCDW: - return 0x46a2 << 10 - case AMOVFV: - return 0x46c9 << 10 - case AMOVDV: - return 0x46ca << 10 - case AMOVVF: - return 0x4746 << 10 - case AMOVVD: - return 0x474a << 10 - case AMOVFW: - return 0x46c1 << 10 - case AMOVDW: - return 0x46c2 << 10 - case AMOVWF: - return 0x4744 << 10 - case AMOVDF: - return 0x4646 << 10 - case AMOVWD: - return 0x4748 << 10 - case AMOVFD: - return 0x4649 << 10 - case AABSF: - return 0x4501 << 10 - case AABSD: - return 0x4502 << 10 - case AMOVF: - return 0x4525 << 10 - case AMOVD: - return 0x4526 << 10 - case ANEGF: - return 0x4505 << 10 - case ANEGD: - return 0x4506 << 10 - case ASQRTF: - return 0x4511 << 10 - case ASQRTD: - return 0x4512 << 10 - case AFLOGBF: - return 0x4509 << 10 // flogb.s - case AFLOGBD: - return 0x450a << 10 // flogb.d - case AFCLASSF: - return 0x450d << 10 // fclass.s - case AFCLASSD: - return 0x450e << 10 // fclass.d - case AFFINTFW: - return 0x4744 << 10 // ffint.s.w - case AFFINTFV: - return 0x4746 << 10 // ffint.s.l - case AFFINTDW: - return 0x4748 << 10 // ffint.d.w - case AFFINTDV: - return 0x474a << 10 // ffint.d.l - case AFTINTWF: - return 0x46c1 << 10 // ftint.w.s - case AFTINTWD: - return 0x46c2 << 10 // ftint.w.d - case AFTINTVF: - return 0x46c9 << 10 // ftint.l.s - case AFTINTVD: - return 0x46ca << 10 // ftint.l.d - case AFTINTRMWF: - return 0x4681 << 10 // ftintrm.w.s - case AFTINTRMWD: - return 0x4682 << 10 // ftintrm.w.d - case AFTINTRMVF: - return 0x4689 << 10 // ftintrm.l.s - case AFTINTRMVD: - return 0x468a << 10 // ftintrm.l.d - case AFTINTRPWF: - return 0x4691 << 10 // ftintrp.w.s - case AFTINTRPWD: - return 0x4692 << 10 // ftintrp.w.d - case AFTINTRPVF: - return 0x4699 << 10 // ftintrp.l.s - case AFTINTRPVD: - return 0x469a << 10 // ftintrp.l.d - case AFTINTRZWF: - return 0x46a1 << 10 // ftintrz.w.s - case AFTINTRZWD: - return 0x46a2 << 10 // ftintrz.w.d - case AFTINTRZVF: - return 0x46a9 << 10 // ftintrz.l.s - case AFTINTRZVD: - return 0x46aa << 10 // ftintrz.l.d - case AFTINTRNEWF: - return 0x46b1 << 10 // ftintrne.w.s - case AFTINTRNEWD: - return 0x46b2 << 10 // ftintrne.w.d - case AFTINTRNEVF: - return 0x46b9 << 10 // ftintrne.l.s - case AFTINTRNEVD: - return 0x46ba << 10 // ftintrne.l.d - case AVPCNTB: - return 0x1ca708 << 10 // vpcnt.b - case AVPCNTH: - return 0x1ca709 << 10 // vpcnt.h - case AVPCNTW: - return 0x1ca70a << 10 // vpcnt.w - case AVPCNTV: - return 0x1ca70b << 10 // vpcnt.v - case AXVPCNTB: - return 0x1da708 << 10 // xvpcnt.b - case AXVPCNTH: - return 0x1da709 << 10 // xvpcnt.h - case AXVPCNTW: - return 0x1da70a << 10 // xvpcnt.w - case AXVPCNTV: - return 0x1da70b << 10 // xvpcnt.v - case AVFSQRTF: - return 0x1ca739 << 10 // vfsqrt.s - case AVFSQRTD: - return 0x1ca73a << 10 // vfsqrt.d - case AVFRECIPF: - return 0x1ca73d << 10 // vfrecip.s - case AVFRECIPD: - return 0x1ca73e << 10 // vfrecip.d - case AVFRSQRTF: - return 0x1ca741 << 10 // vfrsqrt.s - case AVFRSQRTD: - return 0x1ca742 << 10 // vfrsqrt.d - case AXVFSQRTF: - return 0x1da739 << 10 // xvfsqrt.s - case AXVFSQRTD: - return 0x1da73a << 10 // xvfsqrt.d - case AXVFRECIPF: - return 0x1da73d << 10 // xvfrecip.s - case AXVFRECIPD: - return 0x1da73e << 10 // xvfrecip.d - case AXVFRSQRTF: - return 0x1da741 << 10 // xvfrsqrt.s - case AXVFRSQRTD: - return 0x1da742 << 10 // xvfrsqrt.d - case AVNEGB: - return 0x1ca70c << 10 // vneg.b - case AVNEGH: - return 0x1ca70d << 10 // vneg.h - case AVNEGW: - return 0x1ca70e << 10 // vneg.w - case AVNEGV: - return 0x1ca70f << 10 // vneg.d - case AXVNEGB: - return 0x1da70c << 10 // xvneg.b - case AXVNEGH: - return 0x1da70d << 10 // xvneg.h - case AXVNEGW: - return 0x1da70e << 10 // xvneg.w - case AXVNEGV: - return 0x1da70f << 10 // xvneg.d - case AVFRINTRNEF: - return 0x1ca75d << 10 // vfrintrne.s - case AVFRINTRNED: - return 0x1ca75e << 10 // vfrintrne.d - case AVFRINTRZF: - return 0x1ca759 << 10 // vfrintrz.s - case AVFRINTRZD: - return 0x1ca75a << 10 // vfrintrz.d - case AVFRINTRPF: - return 0x1ca755 << 10 // vfrintrp.s - case AVFRINTRPD: - return 0x1ca756 << 10 // vfrintrp.d - case AVFRINTRMF: - return 0x1ca751 << 10 // vfrintrm.s - case AVFRINTRMD: - return 0x1ca752 << 10 // vfrintrm.d - case AVFRINTF: - return 0x1ca74d << 10 // vfrint.s - case AVFRINTD: - return 0x1ca74e << 10 // vfrint.d - case AXVFRINTRNEF: - return 0x1da75d << 10 // xvfrintrne.s - case AXVFRINTRNED: - return 0x1da75e << 10 // xvfrintrne.d - case AXVFRINTRZF: - return 0x1da759 << 10 // xvfrintrz.s - case AXVFRINTRZD: - return 0x1da75a << 10 // xvfrintrz.d - case AXVFRINTRPF: - return 0x1da755 << 10 // xvfrintrp.s - case AXVFRINTRPD: - return 0x1da756 << 10 // xvfrintrp.d - case AXVFRINTRMF: - return 0x1da751 << 10 // xvfrintrm.s - case AXVFRINTRMD: - return 0x1da752 << 10 // xvfrintrm.d - case AXVFRINTF: - return 0x1da74d << 10 // xvfrint.s - case AXVFRINTD: - return 0x1da74e << 10 // xvfrint.d - case AVFCLASSF: - return 0x1ca735 << 10 // vfclass.s - case AVFCLASSD: - return 0x1ca736 << 10 // vfclass.d - case AXVFCLASSF: - return 0x1da735 << 10 // xvfclass.s - case AXVFCLASSD: - return 0x1da736 << 10 // xvfclass.d - case AVSETEQV: - return 0x1ca726<<10 | 0x0<<3 // vseteqz.v - case AVSETNEV: - return 0x1ca727<<10 | 0x0<<3 // vsetnez.v - case AVSETANYEQB: - return 0x1ca728<<10 | 0x0<<3 // vsetanyeqz.b - case AVSETANYEQH: - return 0x1ca729<<10 | 0x0<<3 // vsetanyeqz.h - case AVSETANYEQW: - return 0x1ca72a<<10 | 0x0<<3 // vsetanyeqz.w - case AVSETANYEQV: - return 0x1ca72b<<10 | 0x0<<3 // vsetanyeqz.d - case AVSETALLNEB: - return 0x1ca72c<<10 | 0x0<<3 // vsetallnez.b - case AVSETALLNEH: - return 0x1ca72d<<10 | 0x0<<3 // vsetallnez.h - case AVSETALLNEW: - return 0x1ca72e<<10 | 0x0<<3 // vsetallnez.w - case AVSETALLNEV: - return 0x1ca72f<<10 | 0x0<<3 // vsetallnez.d - case AXVSETEQV: - return 0x1da726<<10 | 0x0<<3 // xvseteqz.v - case AXVSETNEV: - return 0x1da727<<10 | 0x0<<3 // xvsetnez.v - case AXVSETANYEQB: - return 0x1da728<<10 | 0x0<<3 // xvsetanyeqz.b - case AXVSETANYEQH: - return 0x1da729<<10 | 0x0<<3 // xvsetanyeqz.h - case AXVSETANYEQW: - return 0x1da72a<<10 | 0x0<<3 // xvsetanyeqz.w - case AXVSETANYEQV: - return 0x1da72b<<10 | 0x0<<3 // xvsetanyeqz.d - case AXVSETALLNEB: - return 0x1da72c<<10 | 0x0<<3 // xvsetallnez.b - case AXVSETALLNEH: - return 0x1da72d<<10 | 0x0<<3 // xvsetallnez.h - case AXVSETALLNEW: - return 0x1da72e<<10 | 0x0<<3 // xvsetallnez.w - case AXVSETALLNEV: - return 0x1da72f<<10 | 0x0<<3 // xvsetallnez.d + op, ok := oprr[a] + if ok { + return op } - c.ctxt.Diag("bad rr opcode %v", a) return 0 } func (c *ctxt0) opi(a obj.As) uint32 { - switch a { - case ASYSCALL: - return 0x56 << 15 - case ABREAK: - return 0x54 << 15 - case ADBAR: - return 0x70e4 << 15 + op, ok := opi[a] + if ok { + return op } - - c.ctxt.Diag("bad ic opcode %v", a) - + c.ctxt.Diag("bad i opcode %v", a) return 0 } func (c *ctxt0) opir(a obj.As) uint32 { - switch a { - case ALU12IW: - return 0x0a << 25 - case ALU32ID: - return 0x0b << 25 - case APCALAU12I: - return 0x0d << 25 - case APCADDU12I: - return 0x0e << 25 + op, ok := opir[a] + if ok { + return op } + c.ctxt.Diag("bad ir opcode %v", a) return 0 } func (c *ctxt0) opirr(a obj.As) uint32 { - switch a { - case AADD, AADDU: - return 0x00a << 22 - case ASGT: - return 0x008 << 22 - case ASGTU: - return 0x009 << 22 - case AAND: - return 0x00d << 22 - case AOR: - return 0x00e << 22 - case ALU52ID: - return 0x00c << 22 - case AXOR: - return 0x00f << 22 - case ASLL: - return 0x00081 << 15 - case ASRL: - return 0x00089 << 15 - case ASRA: - return 0x00091 << 15 - case AROTR: - return 0x00099 << 15 - case AADDV: - return 0x00b << 22 - case AADDVU: - return 0x00b << 22 - case AADDV16: - return 0x4 << 26 - - case AJMP: - return 0x14 << 26 - case AJAL: - return 0x15 << 26 - - case AJIRL: - return 0x13 << 26 - case ABLTU: - return 0x1a << 26 - case ABLT, ABLTZ, ABGTZ: - return 0x18 << 26 - case ABGEU: - return 0x1b << 26 - case ABGE, ABGEZ, ABLEZ: - return 0x19 << 26 - case -ABEQ: // beqz - return 0x10 << 26 - case -ABNE: // bnez - return 0x11 << 26 - case ABEQ: - return 0x16 << 26 - case ABNE: - return 0x17 << 26 - case ABFPT: - return 0x12<<26 | 0x1<<8 - case ABFPF: - return 0x12<<26 | 0x0<<8 - case APRELDX: - return 0x07058 << 15 // preldx - case AMOVB, - AMOVBU: - return 0x0a4 << 22 - case AMOVH, - AMOVHU: - return 0x0a5 << 22 - case AMOVW, - AMOVWU: - return 0x0a6 << 22 - case AMOVV: - return 0x0a7 << 22 - case AMOVF: - return 0x0ad << 22 - case AMOVD: - return 0x0af << 22 - case AMOVVP: - return 0x27 << 24 // stptr.d - case AMOVWP: - return 0x25 << 24 // stptr.w - case -AMOVB: - return 0x0a0 << 22 - case -AMOVBU: - return 0x0a8 << 22 - case -AMOVH: - return 0x0a1 << 22 - case -AMOVHU: - return 0x0a9 << 22 - case -AMOVW: - return 0x0a2 << 22 - case -AMOVWU: - return 0x0aa << 22 - case -AMOVV: - return 0x0a3 << 22 - case -AMOVF: - return 0x0ac << 22 - case -AMOVD: - return 0x0ae << 22 - case -AMOVVP: - return 0x26 << 24 // ldptr.d - case -AMOVWP: - return 0x24 << 24 // ldptr.w - case -AVMOVQ: - return 0x0b0 << 22 // vld - case -AXVMOVQ: - return 0x0b2 << 22 // xvld - case AVMOVQ: - return 0x0b1 << 22 // vst - case AXVMOVQ: - return 0x0b3 << 22 // xvst - case ASLLV: - return 0x0041 << 16 - case ASRLV: - return 0x0045 << 16 - case ASRAV: - return 0x0049 << 16 - case AROTRV: - return 0x004d << 16 - case -ALL: - return 0x020 << 24 - case -ALLV: - return 0x022 << 24 - case ASC: - return 0x021 << 24 - case ASCV: - return 0x023 << 24 - case AVANDB: - return 0x1CF4 << 18 // vandi.b - case AVORB: - return 0x1CF5 << 18 // vori.b - case AVXORB: - return 0x1CF6 << 18 // xori.b - case AVNORB: - return 0x1CF7 << 18 // xnori.b - case AXVANDB: - return 0x1DF4 << 18 // xvandi.b - case AXVORB: - return 0x1DF5 << 18 // xvori.b - case AXVXORB: - return 0x1DF6 << 18 // xvxori.b - case AXVNORB: - return 0x1DF7 << 18 // xvnor.b - case AVSEQB: - return 0x0E500 << 15 //vseqi.b - case AVSEQH: - return 0x0E501 << 15 // vseqi.h - case AVSEQW: - return 0x0E502 << 15 //vseqi.w - case AVSEQV: - return 0x0E503 << 15 //vseqi.d - case AXVSEQB: - return 0x0ED00 << 15 //xvseqi.b - case AXVSEQH: - return 0x0ED01 << 15 // xvseqi.h - case AXVSEQW: - return 0x0ED02 << 15 // xvseqi.w - case AXVSEQV: - return 0x0ED03 << 15 // xvseqi.d - case AVROTRB: - return 0x1ca8<<18 | 0x1<<13 // vrotri.b - case AVROTRH: - return 0x1ca8<<18 | 0x1<<14 // vrotri.h - case AVROTRW: - return 0x1ca8<<18 | 0x1<<15 // vrotri.w - case AVROTRV: - return 0x1ca8<<18 | 0x1<<16 // vrotri.d - case AXVROTRB: - return 0x1da8<<18 | 0x1<<13 // xvrotri.b - case AXVROTRH: - return 0x1da8<<18 | 0x1<<14 // xvrotri.h - case AXVROTRW: - return 0x1da8<<18 | 0x1<<15 // xvrotri.w - case AXVROTRV: - return 0x1da8<<18 | 0x1<<16 // xvrotri.d - case AVSLLB: - return 0x1ccb<<18 | 0x1<<13 // vslli.b - case AVSLLH: - return 0x1ccb<<18 | 0x1<<14 // vslli.h - case AVSLLW: - return 0x1ccb<<18 | 0x1<<15 // vslli.w - case AVSLLV: - return 0x1ccb<<18 | 0x1<<16 // vslli.d - case AVSRLB: - return 0x1ccc<<18 | 0x1<<13 // vsrli.b - case AVSRLH: - return 0x1ccc<<18 | 0x1<<14 // vsrli.h - case AVSRLW: - return 0x1ccc<<18 | 0x1<<15 // vsrli.w - case AVSRLV: - return 0x1ccc<<18 | 0x1<<16 // vsrli.d - case AVSRAB: - return 0x1ccd<<18 | 0x1<<13 // vsrai.b - case AVSRAH: - return 0x1ccd<<18 | 0x1<<14 // vsrai.h - case AVSRAW: - return 0x1ccd<<18 | 0x1<<15 // vsrai.w - case AVSRAV: - return 0x1ccd<<18 | 0x1<<16 // vsrai.d - case AXVSLLB: - return 0x1dcb<<18 | 0x1<<13 // xvslli.b - case AXVSLLH: - return 0x1dcb<<18 | 0x1<<14 // xvslli.h - case AXVSLLW: - return 0x1dcb<<18 | 0x1<<15 // xvslli.w - case AXVSLLV: - return 0x1dcb<<18 | 0x1<<16 // xvslli.d - case AXVSRLB: - return 0x1dcc<<18 | 0x1<<13 // xvsrli.b - case AXVSRLH: - return 0x1dcc<<18 | 0x1<<14 // xvsrli.h - case AXVSRLW: - return 0x1dcc<<18 | 0x1<<15 // xvsrli.w - case AXVSRLV: - return 0x1dcc<<18 | 0x1<<16 // xvsrli.d - case AXVSRAB: - return 0x1dcd<<18 | 0x1<<13 // xvsrai.b - case AXVSRAH: - return 0x1dcd<<18 | 0x1<<14 // xvsrai.h - case AXVSRAW: - return 0x1dcd<<18 | 0x1<<15 // xvsrai.w - case AXVSRAV: - return 0x1dcd<<18 | 0x1<<16 // xvsrai.d - case AVADDBU: - return 0xe514 << 15 // vaddi.bu - case AVADDHU: - return 0xe515 << 15 // vaddi.hu - case AVADDWU: - return 0xe516 << 15 // vaddi.wu - case AVADDVU: - return 0xe517 << 15 // vaddi.du - case AVSUBBU: - return 0xe518 << 15 // vsubi.bu - case AVSUBHU: - return 0xe519 << 15 // vsubi.hu - case AVSUBWU: - return 0xe51a << 15 // vsubi.wu - case AVSUBVU: - return 0xe51b << 15 // vsubi.du - case AXVADDBU: - return 0xed14 << 15 // xvaddi.bu - case AXVADDHU: - return 0xed15 << 15 // xvaddi.hu - case AXVADDWU: - return 0xed16 << 15 // xvaddi.wu - case AXVADDVU: - return 0xed17 << 15 // xvaddi.du - case AXVSUBBU: - return 0xed18 << 15 // xvsubi.bu - case AXVSUBHU: - return 0xed19 << 15 // xvsubi.hu - case AXVSUBWU: - return 0xed1a << 15 // xvsubi.wu - case AXVSUBVU: - return 0xed1b << 15 // xvsubi.du - case AVSHUF4IB: - return 0x1ce4 << 18 // vshuf4i.b - case AVSHUF4IH: - return 0x1ce5 << 18 // vshuf4i.h - case AVSHUF4IW: - return 0x1ce6 << 18 // vshuf4i.w - case AVSHUF4IV: - return 0x1ce7 << 18 // vshuf4i.d - case AXVSHUF4IB: - return 0x1de4 << 18 // xvshuf4i.b - case AXVSHUF4IH: - return 0x1de5 << 18 // xvshuf4i.h - case AXVSHUF4IW: - return 0x1de6 << 18 // xvshuf4i.w - case AXVSHUF4IV: - return 0x1de7 << 18 // xvshuf4i.d - case AVBITCLRB: - return 0x1CC4<<18 | 0x1<<13 // vbitclri.b - case AVBITCLRH: - return 0x1CC4<<18 | 0x1<<14 // vbitclri.h - case AVBITCLRW: - return 0x1CC4<<18 | 0x1<<15 // vbitclri.w - case AVBITCLRV: - return 0x1CC4<<18 | 0x1<<16 // vbitclri.d - case AVBITSETB: - return 0x1CC5<<18 | 0x1<<13 // vbitseti.b - case AVBITSETH: - return 0x1CC5<<18 | 0x1<<14 // vbitseti.h - case AVBITSETW: - return 0x1CC5<<18 | 0x1<<15 // vbitseti.w - case AVBITSETV: - return 0x1CC5<<18 | 0x1<<16 // vbitseti.d - case AVBITREVB: - return 0x1CC6<<18 | 0x1<<13 // vbitrevi.b - case AVBITREVH: - return 0x1CC6<<18 | 0x1<<14 // vbitrevi.h - case AVBITREVW: - return 0x1CC6<<18 | 0x1<<15 // vbitrevi.w - case AVBITREVV: - return 0x1CC6<<18 | 0x1<<16 // vbitrevi.d - case AXVBITCLRB: - return 0x1DC4<<18 | 0x1<<13 // xvbitclri.b - case AXVBITCLRH: - return 0x1DC4<<18 | 0x1<<14 // xvbitclri.h - case AXVBITCLRW: - return 0x1DC4<<18 | 0x1<<15 // xvbitclri.w - case AXVBITCLRV: - return 0x1DC4<<18 | 0x1<<16 // xvbitclri.d - case AXVBITSETB: - return 0x1DC5<<18 | 0x1<<13 // xvbitseti.b - case AXVBITSETH: - return 0x1DC5<<18 | 0x1<<14 // xvbitseti.h - case AXVBITSETW: - return 0x1DC5<<18 | 0x1<<15 // xvbitseti.w - case AXVBITSETV: - return 0x1DC5<<18 | 0x1<<16 // xvbitseti.d - case AXVBITREVB: - return 0x1DC6<<18 | 0x1<<13 // xvbitrevi.b - case AXVBITREVH: - return 0x1DC6<<18 | 0x1<<14 // xvbitrevi.h - case AXVBITREVW: - return 0x1DC6<<18 | 0x1<<15 // xvbitrevi.w - case AXVBITREVV: - return 0x1DC6<<18 | 0x1<<16 // xvbitrevi.d - } - - if a < 0 { - c.ctxt.Diag("bad irr opcode -%v", -a) - } else { - c.ctxt.Diag("bad irr opcode %v", a) + op, ok := opirr[a] + if ok { + return op } + c.ctxt.Diag("bad irr opcode %v", a) return 0 } func (c *ctxt0) opirrr(a obj.As) uint32 { - switch a { - case AALSLW: - return 0x2 << 17 // alsl.w - case AALSLWU: - return 0x3 << 17 // alsl.wu - case AALSLV: - return 0x16 << 17 // alsl.d + op, ok := opirrr[a] + if ok { + return op } - + c.ctxt.Diag("bad irrr opcode %v", a) return 0 } func (c *ctxt0) opirir(a obj.As) uint32 { - switch a { - case ABSTRINSW: - return 0x3<<21 | 0x0<<15 // bstrins.w - case ABSTRINSV: - return 0x2 << 22 // bstrins.d - case ABSTRPICKW: - return 0x3<<21 | 0x1<<15 // bstrpick.w - case ABSTRPICKV: - return 0x3 << 22 // bstrpick.d + op, ok := opirir[a] + if ok { + return op } - + c.ctxt.Diag("bad irir opcode %v", a) return 0 } func (c *ctxt0) opiir(a obj.As) uint32 { - switch a { - case APRELD: - return 0x0AB << 22 // preld - } - - return 0 -} - -func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32 { - switch a { - case AMOVV: - switch fclass { - case C_REG: - switch tclass { - case C_FREG: - return 0x452a << 10 // movgr2fr.d - case C_FCCREG: - return 0x4536 << 10 // movgr2cf - case C_FCSRREG: - return 0x4530 << 10 // movgr2fcsr - } - case C_FREG: - switch tclass { - case C_REG: - return 0x452e << 10 // movfr2gr.d - case C_FCCREG: - return 0x4534 << 10 // movfr2cf - } - case C_FCCREG: - switch tclass { - case C_REG: - return 0x4537 << 10 // movcf2gr - case C_FREG: - return 0x4535 << 10 // movcf2fr - } - case C_FCSRREG: - switch tclass { - case C_REG: - return 0x4532 << 10 // movfcsr2gr - } - } - - case AMOVW: - switch fclass { - case C_REG: - switch tclass { - case C_FREG: - return 0x4529 << 10 // movgr2fr.w - } - case C_FREG: - switch tclass { - case C_REG: - return 0x452d << 10 // movfr2gr.s - } - } + op, ok := opiir[a] + if ok { + return op } - - c.ctxt.Diag("bad class combination: %s %d,%d\n", a, fclass, tclass) - + c.ctxt.Diag("bad iir opcode %v", a) return 0 } -func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16, offset_flag bool) (op_code, index_mask uint32) { - farng := (fReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK - tarng := (tReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK - fclass := c.rclass(fReg) - tclass := c.rclass(tReg) - - switch fclass | (tclass << 16) { - case C_REG | (C_ELEM << 16): - // vmov Rn, Vd.[index] - switch a { - case AVMOVQ: - switch tarng { - case ARNG_B: - return (0x01CBAE << 14), 0xf // vinsgr2vr.b - case ARNG_H: - return (0x03975E << 13), 0x7 // vinsgr2vr.h - case ARNG_W: - return (0x072EBE << 12), 0x3 // vinsgr2vr.w - case ARNG_V: - return (0x0E5D7E << 11), 0x1 // vinsgr2vr.d - } - case AXVMOVQ: - switch tarng { - case ARNG_W: - return (0x03B75E << 13), 0x7 // xvinsgr2vr.w - case ARNG_V: - return (0x076EBE << 12), 0x3 // xvinsgr2vr.d - } - } - - case C_ELEM | (C_REG << 16): - // vmov Vd.[index], Rn - switch a { - case AVMOVQ: - switch farng { - case ARNG_B: - return (0x01CBBE << 14), 0xf // vpickve2gr.b - case ARNG_H: - return (0x03977E << 13), 0x7 // vpickve2gr.h - case ARNG_W: - return (0x072EFE << 12), 0x3 // vpickve2gr.w - case ARNG_V: - return (0x0E5DFE << 11), 0x1 // vpickve2gr.d - case ARNG_BU: - return (0x01CBCE << 14), 0xf // vpickve2gr.bu - case ARNG_HU: - return (0x03979E << 13), 0x7 // vpickve2gr.hu - case ARNG_WU: - return (0x072F3E << 12), 0x3 // vpickve2gr.wu - case ARNG_VU: - return (0x0E5E7E << 11), 0x1 // vpickve2gr.du - } - case AXVMOVQ: - switch farng { - case ARNG_W: - return (0x03B77E << 13), 0x7 // xvpickve2gr.w - case ARNG_V: - return (0x076EFE << 12), 0x3 // xvpickve2gr.d - case ARNG_WU: - return (0x03B79E << 13), 0x7 // xvpickve2gr.wu - case ARNG_VU: - return (0x076F3E << 12), 0x3 // xvpickve2gr.du - } - } - - case C_REG | (C_ARNG << 16): - switch { - case offset_flag: - // vmov offset(vj), vd. - switch a { - case AVMOVQ: - switch tarng { - case ARNG_16B: - return (0xC2 << 22), 0x0 // vldrepl.b - case ARNG_8H: - return (0x182 << 21), 0x0 // vldrepl.h - case ARNG_4W: - return (0x302 << 20), 0x0 // vldrepl.w - case ARNG_2V: - return (0x602 << 19), 0x0 // vldrepl.d - } - case AXVMOVQ: - switch tarng { - case ARNG_32B: - return (0xCA << 22), 0x0 // xvldrepl.b - case ARNG_16H: - return (0x192 << 21), 0x0 // xvldrepl.h - case ARNG_8W: - return (0x322 << 20), 0x0 // xvldrepl.w - case ARNG_4V: - return (0x642 << 19), 0x0 // xvldrepl.d - } - } - default: - // vmov Rn, Vd. - switch a { - case AVMOVQ: - switch tarng { - case ARNG_16B: - return (0x1CA7C0 << 10), 0x0 // vreplgr2vr.b - case ARNG_8H: - return (0x1CA7C1 << 10), 0x0 // vreplgr2vr.h - case ARNG_4W: - return (0x1CA7C2 << 10), 0x0 // vreplgr2vr.w - case ARNG_2V: - return (0x1CA7C3 << 10), 0x0 // vreplgr2vr.d - } - case AXVMOVQ: - switch tarng { - case ARNG_32B: - return (0x1DA7C0 << 10), 0x0 // xvreplgr2vr.b - case ARNG_16H: - return (0x1DA7C1 << 10), 0x0 // xvreplgr2vr.h - case ARNG_8W: - return (0x1DA7C2 << 10), 0x0 // xvreplgr2vr.w - case ARNG_4V: - return (0x1DA7C3 << 10), 0x0 // xvreplgr2vr.d - } - } - } - - case C_XREG | (C_ARNG << 16): - // vmov xj, xd. - switch a { - case AVMOVQ: - return 0, 0 // unsupported op - case AXVMOVQ: - switch tarng { - case ARNG_32B: - return (0x1DC1C0 << 10), 0x0 // xvreplve0.b - case ARNG_16H: - return (0x1DC1E0 << 10), 0x0 // xvreplve0.h - case ARNG_8W: - return (0x1DC1F0 << 10), 0x0 // xvreplve0.w - case ARNG_4V: - return (0x1DC1F8 << 10), 0x0 // xvreplve0.d - case ARNG_2Q: - return (0x1DC1FC << 10), 0x0 // xvreplve0.q - } - } - - case C_XREG | (C_ELEM << 16): - // vmov xj, xd.[index] - switch a { - case AVMOVQ: - return 0, 0 // unsupported op - case AXVMOVQ: - switch tarng { - case ARNG_W: - return (0x03B7FE << 13), 0x7 // xvinsve0.w - case ARNG_V: - return (0x076FFE << 12), 0x3 // xvinsve0.d - } - } - - case C_ELEM | (C_XREG << 16): - // vmov xj.[index], xd - switch a { - case AVMOVQ: - return 0, 0 // unsupported op - case AXVMOVQ: - switch farng { - case ARNG_W: - return (0x03B81E << 13), 0x7 // xvpickve.w - case ARNG_V: - return (0x07703E << 12), 0x3 // xvpickve.d - } - } - - case C_ELEM | (C_ARNG << 16): - // vmov vj.[index], vd. - switch a { - case AVMOVQ: - switch int32(farng) | (int32(tarng) << 16) { - case int32(ARNG_B) | (int32(ARNG_16B) << 16): - return (0x01CBDE << 14), 0xf // vreplvei.b - case int32(ARNG_H) | (int32(ARNG_8H) << 16): - return (0x0397BE << 13), 0x7 // vreplvei.h - case int32(ARNG_W) | (int32(ARNG_4W) << 16): - return (0x072F7E << 12), 0x3 // vreplvei.w - case int32(ARNG_V) | (int32(ARNG_2V) << 16): - return (0x0E5EFE << 11), 0x1 // vreplvei.d - } - case AXVMOVQ: - return 0, 0 // unsupported op - } - } - - return 0, 0 -} - func vshift(a obj.As) bool { switch a { case ASLLV, diff --git a/src/cmd/internal/obj/loong64/cnames.go b/src/cmd/internal/obj/loong64/cnames.go index 28cd18fd6f50ad..999c3bba2cbd4c 100644 --- a/src/cmd/internal/obj/loong64/cnames.go +++ b/src/cmd/internal/obj/loong64/cnames.go @@ -1,4 +1,4 @@ -// Code generated by mkcnames -i a.out.go -o cnames.go -p loong64; DO NOT EDIT. +// Code generated by mkcnames -i cpu.go -o cnames.go -p loong64; DO NOT EDIT. package loong64 @@ -60,8 +60,14 @@ var cnames0 = []string{ "SAUTO", "LAUTO", "ZOREG", - "SOREG", - "LOREG", + "SOREG_8", + "SOREG_9", + "SOREG_10", + "SOREG_11", + "SOREG_12", + "SOREG_16", + "LOREG_32", + "LOREG_64", "ROFF", "ADDR", "TLS_LE", diff --git a/src/cmd/internal/obj/loong64/cpu.go b/src/cmd/internal/obj/loong64/cpu.go new file mode 100644 index 00000000000000..cb9c03fd4f068d --- /dev/null +++ b/src/cmd/internal/obj/loong64/cpu.go @@ -0,0 +1,449 @@ +// Copyright 2022 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64 + +import ( + "cmd/internal/obj" +) + +//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64 + +const ( + NSNAME = 8 + NSYM = 50 + NREG = 32 // number of general registers + NFREG = 32 // number of floating point registers + NVREG = 32 // number of LSX registers + NXREG = 32 // number of LASX registers +) + +const ( + REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32 + REG_R1 + REG_R2 + REG_R3 + REG_R4 + REG_R5 + REG_R6 + REG_R7 + REG_R8 + REG_R9 + REG_R10 + REG_R11 + REG_R12 + REG_R13 + REG_R14 + REG_R15 + REG_R16 + REG_R17 + REG_R18 + REG_R19 + REG_R20 + REG_R21 + REG_R22 + REG_R23 + REG_R24 + REG_R25 + REG_R26 + REG_R27 + REG_R28 + REG_R29 + REG_R30 + REG_R31 + + REG_F0 // must be a multiple of 32 + REG_F1 + REG_F2 + REG_F3 + REG_F4 + REG_F5 + REG_F6 + REG_F7 + REG_F8 + REG_F9 + REG_F10 + REG_F11 + REG_F12 + REG_F13 + REG_F14 + REG_F15 + REG_F16 + REG_F17 + REG_F18 + REG_F19 + REG_F20 + REG_F21 + REG_F22 + REG_F23 + REG_F24 + REG_F25 + REG_F26 + REG_F27 + REG_F28 + REG_F29 + REG_F30 + REG_F31 + + REG_FCSR0 // must be a multiple of 32 + REG_FCSR1 + REG_FCSR2 + REG_FCSR3 // only four registers are needed + REG_FCSR4 + REG_FCSR5 + REG_FCSR6 + REG_FCSR7 + REG_FCSR8 + REG_FCSR9 + REG_FCSR10 + REG_FCSR11 + REG_FCSR12 + REG_FCSR13 + REG_FCSR14 + REG_FCSR15 + REG_FCSR16 + REG_FCSR17 + REG_FCSR18 + REG_FCSR19 + REG_FCSR20 + REG_FCSR21 + REG_FCSR22 + REG_FCSR23 + REG_FCSR24 + REG_FCSR25 + REG_FCSR26 + REG_FCSR27 + REG_FCSR28 + REG_FCSR29 + REG_FCSR30 + REG_FCSR31 + + REG_FCC0 // must be a multiple of 32 + REG_FCC1 + REG_FCC2 + REG_FCC3 + REG_FCC4 + REG_FCC5 + REG_FCC6 + REG_FCC7 // only eight registers are needed + REG_FCC8 + REG_FCC9 + REG_FCC10 + REG_FCC11 + REG_FCC12 + REG_FCC13 + REG_FCC14 + REG_FCC15 + REG_FCC16 + REG_FCC17 + REG_FCC18 + REG_FCC19 + REG_FCC20 + REG_FCC21 + REG_FCC22 + REG_FCC23 + REG_FCC24 + REG_FCC25 + REG_FCC26 + REG_FCC27 + REG_FCC28 + REG_FCC29 + REG_FCC30 + REG_FCC31 + + // LSX: 128-bit vector register + REG_V0 + REG_V1 + REG_V2 + REG_V3 + REG_V4 + REG_V5 + REG_V6 + REG_V7 + REG_V8 + REG_V9 + REG_V10 + REG_V11 + REG_V12 + REG_V13 + REG_V14 + REG_V15 + REG_V16 + REG_V17 + REG_V18 + REG_V19 + REG_V20 + REG_V21 + REG_V22 + REG_V23 + REG_V24 + REG_V25 + REG_V26 + REG_V27 + REG_V28 + REG_V29 + REG_V30 + REG_V31 + + // LASX: 256-bit vector register + REG_X0 + REG_X1 + REG_X2 + REG_X3 + REG_X4 + REG_X5 + REG_X6 + REG_X7 + REG_X8 + REG_X9 + REG_X10 + REG_X11 + REG_X12 + REG_X13 + REG_X14 + REG_X15 + REG_X16 + REG_X17 + REG_X18 + REG_X19 + REG_X20 + REG_X21 + REG_X22 + REG_X23 + REG_X24 + REG_X25 + REG_X26 + REG_X27 + REG_X28 + REG_X29 + REG_X30 + REG_X31 + + REG_SPECIAL = REG_FCSR0 + + REGZERO = REG_R0 // set to zero + REGLINK = REG_R1 + REGSP = REG_R3 + REGCTXT = REG_R29 // context for closures + REGG = REG_R22 // G in loong64 + REGTMP = REG_R30 // used by the assembler + FREGRET = REG_F0 // not use +) + +var LOONG64DWARFRegisters = map[int16]int16{} + +func init() { + // f assigns dwarfregisters[from:to] = (base):(to-from+base) + f := func(from, to, base int16) { + for r := from; r <= to; r++ { + LOONG64DWARFRegisters[r] = (r - from) + base + } + } + f(REG_R0, REG_R31, 0) + f(REG_F0, REG_F31, 32) + + // The lower bits of V and X registers are alias to F registers + f(REG_V0, REG_V31, 32) + f(REG_X0, REG_X31, 32) +} + +const ( + BIG_8 = 128 - 2 // FIXME (not sure if -2 is appropriate) + BIG_9 = 256 - 2 + BIG_10 = 512 - 2 + BIG_11 = 1024 - 2 + BIG_12 = 2046 + BIG_16 = 32768 - 2 + BIG_32 = 2147483648 - 2 +) + +const ( + // mark flags + LABEL = 1 << 0 + LEAF = 1 << 1 + SYNC = 1 << 2 + BRANCH = 1 << 3 +) + +// Arrangement for Loong64 SIMD instructions +const ( + // arrangement types + ARNG_32B int16 = iota + ARNG_16H + ARNG_8W + ARNG_4V + ARNG_2Q + ARNG_16B + ARNG_8H + ARNG_4W + ARNG_2V + ARNG_B + ARNG_H + ARNG_W + ARNG_V + ARNG_BU + ARNG_HU + ARNG_WU + ARNG_VU +) + +// LoongArch64 SIMD extension type +const ( + LSX int16 = iota + LASX +) + +// bits 0-4 indicates register: Vn or Xn +// bits 5-9 indicates arrangement: +// bits 10 indicates SMID type: 0: LSX, 1: LASX +const ( + REG_ARNG = obj.RBaseLOONG64 + (1 << 10) + (iota << 11) // Vn. + REG_ELEM // Vn.[index] + REG_ELEM_END +) + +const ( + EXT_REG_SHIFT = 0 + EXT_REG_MASK = 0x1f + + EXT_TYPE_SHIFT = 5 + EXT_TYPE_MASK = 0x1f + + EXT_SIMDTYPE_SHIFT = 10 + EXT_SIMDTYPE_MASK = 0x1 +) + +const ( + REG_LAST = REG_ELEM_END // the last defined register +) + +//go:generate go run ../mkcnames.go -i cpu.go -o cnames.go -p loong64 +const ( + C_NONE = iota + C_REG + C_FREG + C_FCSRREG + C_FCCREG + C_VREG + C_XREG + C_ARNG // Vn. + C_ELEM // Vn.[index] + + C_ZCON + C_U1CON // 1 bit unsigned constant + C_U2CON // 2 bit unsigned constant + C_U3CON // 3 bit unsigned constant + C_U4CON // 4 bit unsigned constant + C_U5CON // 5 bit unsigned constant + C_U6CON // 6 bit unsigned constant + C_U7CON // 7 bit unsigned constant + C_U8CON // 8 bit unsigned constant + C_S5CON // 5 bit signed constant + C_US12CON // same as C_S12CON, increase the priority of C_S12CON in special cases. + C_UU12CON // same as C_U12CON, increase the priority of C_U12CON in special cases. + C_S12CON // 12 bit signed constant, -0x800 < v <= 0x7ff + C_U12CON // 12 bit unsigned constant, 0 < v <= 0xfff + C_12CON // 12 bit signed constant, or 12 bit unsigned constant + C_S13CON20_0 // 13 bit signed constant, low 12 bits 0 + C_S13CON // 13 bit signed constant + C_U13CON20_0 // 13 bit unsigned constant, low 12 bits 0 + C_U13CON // 13 bit unsigned constant + C_13CON // 13 bit signed constant, or 13 bit unsigned constant + C_U15CON // 15 bit unsigned constant + C_U15CON20_0 // 15 bit unsigned constant, low 12 bits 0 + C_32CON20_0 // 32 bit signed, low 12 bits 0 + C_32CON // other 32 bit signed + + // 64 bit signed, lo32 bits 0, hi20 bits are not 0, hi12 bits can + // be obtained by sign extension of the hi20 bits. + C_DCON20S_0 + // 64 bit signed, lo52 bits 0, hi12 bits are not 0. + C_DCON12_0 + // 64 bit signed, lo32 bits 0, hi32 bits are not 0. + C_DCON32_0 + // 64 bit signed, lo12 bits 0, lo20 bits are not 0, hi20 bits can be + // obtained by sign extension of the lo20 bits, other bits are not 0. + C_DCON12_20S + // 64 bit signed, lo12 bits 0, hi20 bits are not 0, hi12 bits can be + // obtained by sign extension of the hi20 bits, other bits are not 0. + C_DCON20S_20 + // 64 bit signed, lo12 bits 0, other bits are not 0. + C_DCON32_20 + // 64 bit signed, lo12 bits are not 0, 12~51 bits can be obtained + // by sign extension of the lo12 bits, other bits are not 0. + C_DCON12_12S + // 64 bit signed, hi20 bits and lo12 bits are not 0, hi12 bits can + // be obtained by sign extension of the hi20 bits, lo20 bits can + // be obtained by sign extension of the lo12 bits. + C_DCON20S_12S + // 64 bit signed, lo12 bits are not 0, lo20 bits can be obtained by sign + // extension of the lo12 bits, other bits are not 0. + C_DCON32_12S + // 64 bit signed, lo20 and lo12 bits are not 0, hi20 bits can be obtained by sign + // extension of the lo20 bits. other bits are not 0. + C_DCON12_32S + // 64 bit signed, hi20 bits are not 0, hi12 bits can be obtained by sign + // extension of the hi20 bits, lo32 bits are not 0. + C_DCON20S_32 + // 64 bit signed, 12~51 bits 0, other bits are not 0. + C_DCON12_12U + // 64 bit signed, lo20 bits 0, hi20 bits are not 0, hi12 bits can be + // obtained by sign extension of the hi20 bits, lo12 bits are not 0. + C_DCON20S_12U + // 64 bit signed, lo20 bits 0, other bits are not 0. + C_DCON32_12U + // other 64 + C_DCON + + C_SACON // $n(REG) where n <= int12 + C_LACON // $n(REG) where int12 < n <= int32 + C_DACON // $n(REG) where int32 < n + C_EXTADDR // external symbol address + C_BRAN + C_SAUTO + C_LAUTO + C_ZOREG // An $0+reg memory op + C_SOREG_8 // An $n+reg memory arg where n is a 8 bit signed offset + C_SOREG_9 // An $n+reg memory arg where n is a 9 bit signed offset + C_SOREG_10 // An $n+reg memory arg where n is a 10 bit signed offset + C_SOREG_11 // An $n+reg memory arg where n is a 11 bit signed offset + C_SOREG_12 // An $n+reg memory arg where n is a 12 bit signed offset + C_SOREG_16 // An $n+reg memory arg where n is a 16 bit signed offset + C_LOREG_32 // An $n+reg memory arg where n is a 32 bit signed offset + C_LOREG_64 // An $n+reg memory arg where n is a 64 bit signed offset + C_ROFF // register offset + C_ADDR + C_TLS_LE + C_TLS_IE + C_GOTADDR + C_TEXTSIZE + + C_GOK + C_NCLASS // must be the last +) + +func init() { + // The asm encoder generally assumes that the lowest 5 bits of the + // REG_XX constants match the machine instruction encoding, i.e. + // the lowest 5 bits is the register number. + // Check this here. + if REG_R0%32 != 0 { + panic("REG_R0 is not a multiple of 32") + } + if REG_F0%32 != 0 { + panic("REG_F0 is not a multiple of 32") + } + if REG_FCSR0%32 != 0 { + panic("REG_FCSR0 is not a multiple of 32") + } + if REG_FCC0%32 != 0 { + panic("REG_FCC0 is not a multiple of 32") + } + if REG_V0%32 != 0 { + panic("REG_V0 is not a multiple of 32") + } + if REG_X0%32 != 0 { + panic("REG_X0 is not a multiple of 32") + } +} diff --git a/src/cmd/internal/obj/loong64/doc.go b/src/cmd/internal/obj/loong64/doc.go index f7e5a4fb4279ea..e3ff421b7d7c84 100644 --- a/src/cmd/internal/obj/loong64/doc.go +++ b/src/cmd/internal/obj/loong64/doc.go @@ -6,6 +6,18 @@ Package loong64 implements an LoongArch64 assembler. Go assembly syntax is different from GNU LoongArch64 syntax, but we can still follow the general rules to map between them. +# Register Convention + + Name | Alias | Meaning + ----------------------------------------------------------------------------------------------------------------------- + R0 | REGZERO | Constant zero + R1 | REGLINK | Return address + R3 | REGSP | Stack pointer + R12,R13,R14,R15,R20 | | For plt and trampoline, use with caution in assembly code, save before calling function + R22 | REGG | Goroutine pointer + R29 | REGCTXT | Context for closures + R30 | REGTMP | Tmp register used by assembler + # Instructions mnemonics mapping rules 1. Bit widths represented by various instruction suffixes and prefixes @@ -203,6 +215,15 @@ Note: In the following sections 3.1 to 3.6, "ui4" (4-bit unsigned int immediate) VMOVQ Vj.W[index], Vd.W4 | vreplvei.w vd, vj, ui2 | for i in range(4) : VR[vd].w[i] = VR[vj].w[ui2] VMOVQ Vj.V[index], Vd.V2 | vreplvei.d vd, vj, ui1 | for i in range(2) : VR[vd].d[i] = VR[vj].d[ui1] +3.7 Move vector register to vector register. + Instruction format: + VMOVQ Vj, Vd + + Mapping between Go and platform assembly: + Go assembly | platform assembly | semantics + VMOVQ Vj, Vd | vslli.d vd, vj, 0x0 | for i in range(2) : VR[vd].D[i] = SLL(VR[vj].D[i], 0) + VXMOVQ Xj, Xd | xvslli.d xd, xj, 0x0 | for i in range(4) : XR[xd].D[i] = SLL(XR[xj].D[i], 0) + 3.7 Load data from memory and broadcast to each element of a vector register. Instruction format: @@ -229,6 +250,40 @@ Note: In the following sections 3.1 to 3.6, "ui4" (4-bit unsigned int immediate) VMOVQ 8(R4), V5.W4 | vldrepl.w v5, r4, $2 VMOVQ 8(R4), V5.V2 | vldrepl.d v5, r4, $1 +3.8 Vector permutation instruction + Instruction format: + VPERMIW ui8, Vj, Vd + + Mapping between Go and platform assembly: + Go assembly | platform assembly | semantics + VPERMIW ui8, Vj, Vd | vpermi.w vd, vj, ui8 | VR[vd].W[0] = VR[vj].W[ui8[1:0]], VR[vd].W[1] = VR[vj].W[ui8[3:2]], + | | VR[vd].W[2] = VR[vd].W[ui8[5:4]], VR[vd].W[3] = VR[vd].W[ui8[7:6]] + XVPERMIW ui8, Xj, Xd | xvpermi.w xd, xj, ui8 | XR[xd].W[0] = XR[xj].W[ui8[1:0]], XR[xd].W[1] = XR[xj].W[ui8[3:2]], + | | XR[xd].W[3] = XR[xd].W[ui8[7:6]], XR[xd].W[2] = XR[xd].W[ui8[5:4]], + | | XR[xd].W[4] = XR[xj].W[ui8[1:0]+4], XR[xd].W[5] = XR[xj].W[ui8[3:2]+4], + | | XR[xd].W[6] = XR[xd].W[ui8[5:4]+4], XR[xd].W[7] = XR[xd].W[ui8[7:6]+4] + XVPERMIV ui8, Xj, Xd | xvpermi.d xd, xj, ui8 | XR[xd].D[0] = XR[xj].D[ui8[1:0]], XR[xd].D[1] = XR[xj].D[ui8[3:2]], + | | XR[xd].D[2] = XR[xj].D[ui8[5:4]], XR[xd].D[3] = XR[xj].D[ui8[7:6]] + XVPERMIQ ui8, Xj, Xd | xvpermi.q xd, xj, ui8 | vec = {XR[xd], XR[xj]}, XR[xd].Q[0] = vec.Q[ui8[1:0]], XR[xd].Q[1] = vec.Q[ui8[5:4]] + +3.9 Vector misc instruction + +3.9.1 {,X}VEXTRINS.{B,H,W,V} + + Instruction format: + VEXTRINSB ui8, Vj, Vd + + Mapping between Go and platform assembly: + Go assembly | platform assembly | semantics + VEXTRINSB ui8, Vj, Vd | vextrins.b vd, vj, ui8 | VR[vd].B[ui8[7:4]] = VR[vj].B[ui8[3:0]] + VEXTRINSH ui8, Vj, Vd | vextrins.h vd, vj, ui8 | VR[vd].H[ui8[6:4]] = VR[vj].H[ui8[2:0]] + VEXTRINSW ui8, Vj, Vd | vextrins.w vd, vj, ui8 | VR[vd].W[ui8[5:4]] = VR[vj].W[ui8[1:0]] + VEXTRINSV ui8, Vj, Vd | vextrins.d vd, vj, ui8 | VR[vd].D[ui8[4]] = VR[vj].D[ui8[0]] + XVEXTRINSB ui8, Vj, Vd | xvextrins.b vd, vj, ui8 | XR[xd].B[ui8[7:4]] = XR[xj].B[ui8[3:0]], XR[xd].B[ui8[7:4]+16] = XR[xj].B[ui8[3:0]+16] + XVEXTRINSH ui8, Vj, Vd | xvextrins.h vd, vj, ui8 | XR[xd].H[ui8[6:4]] = XR[xj].H[ui8[2:0]], XR[xd].H[ui8[6:4]+8] = XR[xj].H[ui8[2:0]+8] + XVEXTRINSW ui8, Vj, Vd | xvextrins.w vd, vj, ui8 | XR[xd].W[ui8[5:4]] = XR[xj].W[ui8[1:0]], XR[xd].W[ui8[5:4]+4] = XR[xj].W[ui8[1:0]+4] + XVEXTRINSV ui8, Vj, Vd | xvextrins.d vd, vj, ui8 | XR[xd].D[ui8[4]] = XR[xj].D[ui8[0]],XR[xd].D[ui8[4]+2] = XR[xj].D[ui8[0]+2] + # Special instruction encoding definition and description on LoongArch 1. DBAR hint encoding for LA664(Loongson 3A6000) and later micro-architectures, paraphrased @@ -326,7 +381,7 @@ Note: In the following sections 3.1 to 3.6, "ui4" (4-bit unsigned int immediate) Go assembly | platform assembly MOVWP 8(R4), R5 | ldptr.w r5, r4, $2 -6. Note of special add instrction +6. Note of special add instruction Mapping between Go and platform assembly: Go assembly | platform assembly ADDV16 si16<<16, Rj, Rd | addu16i.d rd, rj, si16 diff --git a/src/cmd/internal/obj/loong64/inst.go b/src/cmd/internal/obj/loong64/inst.go new file mode 100644 index 00000000000000..3e9cd0c7dc4dba --- /dev/null +++ b/src/cmd/internal/obj/loong64/inst.go @@ -0,0 +1,953 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64 + +import ( + "cmd/internal/obj" +) + +//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64 +const ( + AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota + AABSF + AADD + AADDD + AADDF + + AADDW + AAND + ABEQ + ABGEZ + ABLEZ + ABGTZ + ABLTZ + ABFPF + ABFPT + + ABNE + ABREAK + + ACMPEQD + ACMPEQF + + ACMPGED // ACMPGED -> fcmp.sle.d + ACMPGEF // ACMPGEF -> fcmp.sle.s + ACMPGTD // ACMPGTD -> fcmp.slt.d + ACMPGTF // ACMPGTF -> fcmp.slt.s + + ALU12IW + ALU32ID + ALU52ID + APCALAU12I + APCADDU12I + AJIRL + ABGE + ABLT + ABLTU + ABGEU + + ADIV + ADIVD + ADIVF + ADIVU + ADIVW + ADIVWU + + ALUI + + AMOVB + AMOVBU + + AMOVD + AMOVDF + AMOVDW + AMOVF + AMOVFD + AMOVFW + + AMOVH + AMOVHU + AMOVW + + AMOVWD + AMOVWF + + AMUL + AMULD + AMULF + AMULH + AMULHU + AMULW + ANEGD + ANEGF + + ANEGW + ANEGV + + ANOOP // hardware nop + ANOR + AOR + AREM + AREMW + AREMU + AREMWU + + ARFE + + ASGT + ASGTU + + ASLL + ASQRTD + ASQRTF + ASRA + ASRL + AROTR + ASUB + ASUBD + ASUBF + + ASUBW + ADBAR + ASYSCALL + + ATEQ + ATNE + + AWORD + + AXOR + + AMASKEQZ + AMASKNEZ + + // 64-bit + AMOVV + + ASLLV + ASRAV + ASRLV + AROTRV + ADIVV + ADIVVU + + AREMV + AREMVU + + AMULV + AMULVU + AMULHV + AMULHVU + AADDV + AADDVU + ASUBV + ASUBVU + + // 64-bit FP + ATRUNCFV + ATRUNCDV + ATRUNCFW + ATRUNCDW + + AMOVWU + AMOVFV + AMOVDV + AMOVVF + AMOVVD + + // 2.2.1.2 + AADDV16 + + // 2.2.1.3 + AALSLW + AALSLWU + AALSLV + + // 2.2.1.8 + AORN + AANDN + + // 2.2.1.12 + AMULWVW + AMULWVWU + + // 2.2.7. Atomic Memory Access Instructions + AAMSWAPB + AAMSWAPH + AAMSWAPW + AAMSWAPV + AAMCASB + AAMCASH + AAMCASW + AAMCASV + AAMADDW + AAMADDV + AAMANDW + AAMANDV + AAMORW + AAMORV + AAMXORW + AAMXORV + AAMMAXW + AAMMAXV + AAMMINW + AAMMINV + AAMMAXWU + AAMMAXVU + AAMMINWU + AAMMINVU + AAMSWAPDBB + AAMSWAPDBH + AAMSWAPDBW + AAMSWAPDBV + AAMCASDBB + AAMCASDBH + AAMCASDBW + AAMCASDBV + AAMADDDBW + AAMADDDBV + AAMANDDBW + AAMANDDBV + AAMORDBW + AAMORDBV + AAMXORDBW + AAMXORDBV + AAMMAXDBW + AAMMAXDBV + AAMMINDBW + AAMMINDBV + AAMMAXDBWU + AAMMAXDBVU + AAMMINDBWU + AAMMINDBVU + ALL + ALLW + ALLV + ASC + ASCW + ASCV + ASCQ + ALLACQW + ALLACQV + ASCRELW + ASCRELV + + // 2.2.3.1 + AEXTWB + AEXTWH + + // 2.2.3.2 + ACLOW + ACLOV + ACLZW + ACLZV + ACTOW + ACTOV + ACTZW + ACTZV + + // 2.2.3.4 + AREVBV + AREVB2W + AREVB4H + AREVB2H + + // 2.2.3.5 + AREVH2W + AREVHV + + // 2.2.3.6 + ABITREV4B + ABITREV8B + + // 2.2.3.7 + ABITREVW + ABITREVV + + // 2.2.3.8 + ABSTRINSW + ABSTRINSV + + // 2.2.3.9 + ABSTRPICKW + ABSTRPICKV + + // 2.2.5.3 + AMOVWP + AMOVVP + + // 2.2.5.4. Prefetch Instructions + APRELD + APRELDX + + // 2.2.9. CRC Check Instructions + ACRCWBW + ACRCWHW + ACRCWWW + ACRCWVW + ACRCCWBW + ACRCCWHW + ACRCCWWW + ACRCCWVW + + // 2.2.10. Other Miscellaneous Instructions + ARDTIMELW + ARDTIMEHW + ARDTIMED + ACPUCFG + + // 3.2.1.2 + AFMADDF + AFMADDD + AFMSUBF + AFMSUBD + AFNMADDF + AFNMADDD + AFNMSUBF + AFNMSUBD + + // 3.2.1.3 + AFMINF + AFMIND + AFMAXF + AFMAXD + + // 3.2.1.4 + AFMAXAF + AFMAXAD + AFMINAF + AFMINAD + + // 3.2.1.7 + AFCOPYSGF + AFCOPYSGD + AFSCALEBF + AFSCALEBD + AFLOGBF + AFLOGBD + + // 3.2.1.8 + AFCLASSF + AFCLASSD + + // 3.2.3.2 + AFFINTFW + AFFINTFV + AFFINTDW + AFFINTDV + AFTINTWF + AFTINTWD + AFTINTVF + AFTINTVD + + // 3.2.3.3 + AFTINTRPWF + AFTINTRPWD + AFTINTRPVF + AFTINTRPVD + AFTINTRMWF + AFTINTRMWD + AFTINTRMVF + AFTINTRMVD + AFTINTRZWF + AFTINTRZWD + AFTINTRZVF + AFTINTRZVD + AFTINTRNEWF + AFTINTRNEWD + AFTINTRNEVF + AFTINTRNEVD + + // 3.2.3.4 + AFRINTF + AFRINTD + + // 3.2.4.2 + AFSEL + + // LSX and LASX memory access instructions + AVMOVQ + AXVMOVQ + + // LSX and LASX arithmetic instructions + AVADDB + AVADDH + AVADDW + AVADDV + AVADDQ + AXVADDB + AXVADDH + AXVADDW + AXVADDV + AXVADDQ + AVSUBB + AVSUBH + AVSUBW + AVSUBV + AVSUBQ + AXVSUBB + AXVSUBH + AXVSUBW + AXVSUBV + AXVSUBQ + AVADDBU + AVADDHU + AVADDWU + AVADDVU + AVSUBBU + AVSUBHU + AVSUBWU + AVSUBVU + AXVADDBU + AXVADDHU + AXVADDWU + AXVADDVU + AXVSUBBU + AXVSUBHU + AXVSUBWU + AXVSUBVU + AVSADDB + AVSADDH + AVSADDW + AVSADDV + AVSSUBB + AVSSUBH + AVSSUBW + AVSSUBV + AVSADDBU + AVSADDHU + AVSADDWU + AVSADDVU + AVSSUBBU + AVSSUBHU + AVSSUBWU + AVSSUBVU + AXVSADDB + AXVSADDH + AXVSADDW + AXVSADDV + AXVSSUBB + AXVSSUBH + AXVSSUBW + AXVSSUBV + AXVSADDBU + AXVSADDHU + AXVSADDWU + AXVSADDVU + AXVSSUBBU + AXVSSUBHU + AXVSSUBWU + AXVSSUBVU + + // LSX and LASX Bit-manipulation Instructions + AVANDB + AVORB + AVXORB + AVNORB + AXVANDB + AXVORB + AXVXORB + AXVNORB + AVANDV + AVORV + AVXORV + AVNORV + AVANDNV + AVORNV + AXVANDV + AXVORV + AXVXORV + AXVNORV + AXVANDNV + AXVORNV + + AVPCNTB + AVPCNTH + AVPCNTW + AVPCNTV + AXVPCNTB + AXVPCNTH + AXVPCNTW + AXVPCNTV + + AVBITCLRB + AVBITCLRH + AVBITCLRW + AVBITCLRV + AVBITSETB + AVBITSETH + AVBITSETW + AVBITSETV + AVBITREVB + AVBITREVH + AVBITREVW + AVBITREVV + AXVBITCLRB + AXVBITCLRH + AXVBITCLRW + AXVBITCLRV + AXVBITSETB + AXVBITSETH + AXVBITSETW + AXVBITSETV + AXVBITREVB + AXVBITREVH + AXVBITREVW + AXVBITREVV + + // LSX and LASX integer comparison instruction + AVSEQB + AXVSEQB + AVSEQH + AXVSEQH + AVSEQW + AXVSEQW + AVSEQV + AXVSEQV + + AVSLTB + AVSLTH + AVSLTW + AVSLTV + AVSLTBU + AVSLTHU + AVSLTWU + AVSLTVU + AXVSLTB + AXVSLTH + AXVSLTW + AXVSLTV + AXVSLTBU + AXVSLTHU + AXVSLTWU + AXVSLTVU + + // LSX and LASX integer div and mod instructions + AVDIVB + AVDIVH + AVDIVW + AVDIVV + AVDIVBU + AVDIVHU + AVDIVWU + AVDIVVU + AVMODB + AVMODH + AVMODW + AVMODV + AVMODBU + AVMODHU + AVMODWU + AVMODVU + AXVDIVB + AXVDIVH + AXVDIVW + AXVDIVV + AXVDIVBU + AXVDIVHU + AXVDIVWU + AXVDIVVU + AXVMODB + AXVMODH + AXVMODW + AXVMODV + AXVMODBU + AXVMODHU + AXVMODWU + AXVMODVU + + // LSX and LASX shift operation instructions + AVSLLB + AVSLLH + AVSLLW + AVSLLV + AVSRLB + AVSRLH + AVSRLW + AVSRLV + AVSRAB + AVSRAH + AVSRAW + AVSRAV + AVROTRB + AVROTRH + AVROTRW + AVROTRV + AXVSLLB + AXVSLLH + AXVSLLW + AXVSLLV + AXVSRLB + AXVSRLH + AXVSRLW + AXVSRLV + AXVSRAB + AXVSRAH + AXVSRAW + AXVSRAV + AXVROTRB + AXVROTRH + AXVROTRW + AXVROTRV + + // LSX and LASX move and shuffle instructions + AVILVLB + AVILVLH + AVILVLW + AVILVLV + AVILVHB + AVILVHH + AVILVHW + AVILVHV + AXVILVLB + AXVILVLH + AXVILVLW + AXVILVLV + AXVILVHB + AXVILVHH + AXVILVHW + AXVILVHV + + // LSX and LASX integer mul instructions + AVMULB + AVMULH + AVMULW + AVMULV + AVMUHB + AVMUHH + AVMUHW + AVMUHV + AVMUHBU + AVMUHHU + AVMUHWU + AVMUHVU + AXVMULB + AXVMULH + AXVMULW + AXVMULV + AXVMUHB + AXVMUHH + AXVMUHW + AXVMUHV + AXVMUHBU + AXVMUHHU + AXVMUHWU + AXVMUHVU + + // LSX and LASX floating point instructions + AVFSQRTF + AVFSQRTD + AVFRECIPF + AVFRECIPD + AVFRSQRTF + AVFRSQRTD + AXVFSQRTF + AXVFSQRTD + AXVFRECIPF + AXVFRECIPD + AXVFRSQRTF + AXVFRSQRTD + + AVADDF + AVADDD + AVSUBF + AVSUBD + AVMULF + AVMULD + AVDIVF + AVDIVD + AXVADDF + AXVADDD + AXVSUBF + AXVSUBD + AXVMULF + AXVMULD + AXVDIVF + AXVDIVD + + AVFCLASSF + AVFCLASSD + AXVFCLASSF + AXVFCLASSD + + // LSX and LASX floating point conversion instructions + AVFRINTRNEF + AVFRINTRNED + AVFRINTRZF + AVFRINTRZD + AVFRINTRPF + AVFRINTRPD + AVFRINTRMF + AVFRINTRMD + AVFRINTF + AVFRINTD + AXVFRINTRNEF + AXVFRINTRNED + AXVFRINTRZF + AXVFRINTRZD + AXVFRINTRPF + AXVFRINTRPD + AXVFRINTRMF + AXVFRINTRMD + AXVFRINTF + AXVFRINTD + + // LSX and LASX integer neg instructions + AVNEGB + AVNEGH + AVNEGW + AVNEGV + AXVNEGB + AXVNEGH + AXVNEGW + AXVNEGV + + // LSX and LASX mul instructions that operate on even or odd positions + AVMULWEVHB + AVMULWEVWH + AVMULWEVVW + AVMULWEVQV + AVMULWODHB + AVMULWODWH + AVMULWODVW + AVMULWODQV + AVMULWEVHBU + AVMULWEVWHU + AVMULWEVVWU + AVMULWEVQVU + AVMULWODHBU + AVMULWODWHU + AVMULWODVWU + AVMULWODQVU + AXVMULWEVHB + AXVMULWEVWH + AXVMULWEVVW + AXVMULWEVQV + AXVMULWODHB + AXVMULWODWH + AXVMULWODVW + AXVMULWODQV + AXVMULWEVHBU + AXVMULWEVWHU + AXVMULWEVVWU + AXVMULWEVQVU + AXVMULWODHBU + AXVMULWODWHU + AXVMULWODVWU + AXVMULWODQVU + AVMULWEVHBUB + AVMULWEVWHUH + AVMULWEVVWUW + AVMULWEVQVUV + AVMULWODHBUB + AVMULWODWHUH + AVMULWODVWUW + AVMULWODQVUV + AXVMULWEVHBUB + AXVMULWEVWHUH + AXVMULWEVVWUW + AXVMULWEVQVUV + AXVMULWODHBUB + AXVMULWODWHUH + AXVMULWODVWUW + AXVMULWODQVUV + + AVADDWEVHB + AVADDWEVWH + AVADDWEVVW + AVADDWEVQV + AVSUBWEVHB + AVSUBWEVWH + AVSUBWEVVW + AVSUBWEVQV + AVADDWODHB + AVADDWODWH + AVADDWODVW + AVADDWODQV + AVSUBWODHB + AVSUBWODWH + AVSUBWODVW + AVSUBWODQV + AXVADDWEVHB + AXVADDWEVWH + AXVADDWEVVW + AXVADDWEVQV + AXVSUBWEVHB + AXVSUBWEVWH + AXVSUBWEVVW + AXVSUBWEVQV + AXVADDWODHB + AXVADDWODWH + AXVADDWODVW + AXVADDWODQV + AXVSUBWODHB + AXVSUBWODWH + AXVSUBWODVW + AXVSUBWODQV + AVADDWEVHBU + AVADDWEVWHU + AVADDWEVVWU + AVADDWEVQVU + AVSUBWEVHBU + AVSUBWEVWHU + AVSUBWEVVWU + AVSUBWEVQVU + AVADDWODHBU + AVADDWODWHU + AVADDWODVWU + AVADDWODQVU + AVSUBWODHBU + AVSUBWODWHU + AVSUBWODVWU + AVSUBWODQVU + AXVADDWEVHBU + AXVADDWEVWHU + AXVADDWEVVWU + AXVADDWEVQVU + AXVSUBWEVHBU + AXVSUBWEVWHU + AXVSUBWEVVWU + AXVSUBWEVQVU + AXVADDWODHBU + AXVADDWODWHU + AXVADDWODVWU + AXVADDWODQVU + AXVSUBWODHBU + AXVSUBWODWHU + AXVSUBWODVWU + AXVSUBWODQVU + + AVMADDB + AVMADDH + AVMADDW + AVMADDV + AVMSUBB + AVMSUBH + AVMSUBW + AVMSUBV + + AXVMADDB + AXVMADDH + AXVMADDW + AXVMADDV + AXVMSUBB + AXVMSUBH + AXVMSUBW + AXVMSUBV + + AVMADDWEVHB + AVMADDWEVWH + AVMADDWEVVW + AVMADDWEVQV + AVMADDWODHB + AVMADDWODWH + AVMADDWODVW + AVMADDWODQV + + AVMADDWEVHBU + AVMADDWEVWHU + AVMADDWEVVWU + AVMADDWEVQVU + AVMADDWODHBU + AVMADDWODWHU + AVMADDWODVWU + AVMADDWODQVU + + AVMADDWEVHBUB + AVMADDWEVWHUH + AVMADDWEVVWUW + AVMADDWEVQVUV + AVMADDWODHBUB + AVMADDWODWHUH + AVMADDWODVWUW + AVMADDWODQVUV + + AXVMADDWEVHB + AXVMADDWEVWH + AXVMADDWEVVW + AXVMADDWEVQV + AXVMADDWODHB + AXVMADDWODWH + AXVMADDWODVW + AXVMADDWODQV + + AXVMADDWEVHBU + AXVMADDWEVWHU + AXVMADDWEVVWU + AXVMADDWEVQVU + AXVMADDWODHBU + AXVMADDWODWHU + AXVMADDWODVWU + AXVMADDWODQVU + + AXVMADDWEVHBUB + AXVMADDWEVWHUH + AXVMADDWEVVWUW + AXVMADDWEVQVUV + AXVMADDWODHBUB + AXVMADDWODWHUH + AXVMADDWODVWUW + AXVMADDWODQVUV + + AVSHUF4IB + AVSHUF4IH + AVSHUF4IW + AVSHUF4IV + AXVSHUF4IB + AXVSHUF4IH + AXVSHUF4IW + AXVSHUF4IV + + AVSHUFB + AVSHUFH + AVSHUFW + AVSHUFV + AXVSHUFB + AXVSHUFH + AXVSHUFW + AXVSHUFV + + AVPERMIW + AXVPERMIW + AXVPERMIV + AXVPERMIQ + + AVEXTRINSB + AVEXTRINSH + AVEXTRINSW + AVEXTRINSV + AXVEXTRINSB + AXVEXTRINSH + AXVEXTRINSW + AXVEXTRINSV + + AVSETEQV + AVSETNEV + AVSETANYEQB + AVSETANYEQH + AVSETANYEQW + AVSETANYEQV + AVSETALLNEB + AVSETALLNEH + AVSETALLNEW + AVSETALLNEV + AXVSETEQV + AXVSETNEV + AXVSETANYEQB + AXVSETANYEQH + AXVSETANYEQW + AXVSETANYEQV + AXVSETALLNEB + AXVSETALLNEH + AXVSETALLNEW + AXVSETALLNEV + + ALAST + + // aliases + AJMP = obj.AJMP + AJAL = obj.ACALL + ARET = obj.ARET +) diff --git a/src/cmd/internal/obj/loong64/instOp.go b/src/cmd/internal/obj/loong64/instOp.go new file mode 100644 index 00000000000000..c2fa45ae573494 --- /dev/null +++ b/src/cmd/internal/obj/loong64/instOp.go @@ -0,0 +1,1222 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64 + +import ( + "cmd/internal/obj" +) + +var oprrrr = map[obj.As]uint32{ + AFMADDF: 0x81 << 20, // fmadd.s + AFMADDD: 0x82 << 20, // fmadd.d + AFMSUBF: 0x85 << 20, // fmsub.s + AFMSUBD: 0x86 << 20, // fmsub.d + AFNMADDF: 0x89 << 20, // fnmadd.f + AFNMADDD: 0x8a << 20, // fnmadd.d + AFNMSUBF: 0x8d << 20, // fnmsub.s + AFNMSUBD: 0x8e << 20, // fnmsub.d + AVSHUFB: 0x0d5 << 20, // vshuf.b + AXVSHUFB: 0x0d6 << 20, // xvshuf.b +} + +var oprrr = map[obj.As]uint32{ + AADD: 0x20 << 15, // add.w + AADDW: 0x20 << 15, // add.w + AADDV: 0x21 << 15, // add.d + AADDVU: 0x21 << 15, // add.d + ASUB: 0x22 << 15, // sub.w + ASUBW: 0x22 << 15, // sub.w + ANEGW: 0x22 << 15, // sub.w + ASUBV: 0x23 << 15, // sub.d + ASUBVU: 0x23 << 15, // sub.d + ANEGV: 0x23 << 15, // sub.d + ASGT: 0x24 << 15, // slt + ASGTU: 0x25 << 15, // sltu + AMASKEQZ: 0x26 << 15, // maskeqz + AMASKNEZ: 0x27 << 15, // masknez + ASCQ: 0x070AE << 15, // sc.q + ANOR: 0x28 << 15, // nor + AAND: 0x29 << 15, // and + AOR: 0x2a << 15, // or + AXOR: 0x2b << 15, // xor + AORN: 0x2c << 15, // orn + AANDN: 0x2d << 15, // andn + ASLL: 0x2e << 15, // sll.w + ASRL: 0x2f << 15, // srl.w + ASRA: 0x30 << 15, // sra.w + ASLLV: 0x31 << 15, // sll.d + ASRLV: 0x32 << 15, // srl.d + ASRAV: 0x33 << 15, // sra.d + AROTR: 0x36 << 15, // rotr.w + AROTRV: 0x37 << 15, // rotr.d + AMUL: 0x38 << 15, // mul.w + AMULW: 0x38 << 15, // mul.w + AMULH: 0x39 << 15, // mulh.w + AMULHU: 0x3a << 15, // mulhu.w + AMULV: 0x3b << 15, // mul.d + AMULVU: 0x3b << 15, // mul.d + AMULHV: 0x3c << 15, // mulh.d + AMULHVU: 0x3d << 15, // mulhu.d + AMULWVW: 0x3e << 15, // mulw.d.w + AMULWVWU: 0x3f << 15, // mulw.d.wu + ADIV: 0x40 << 15, // div.w + ADIVW: 0x40 << 15, // div.w + AREM: 0x41 << 15, // mod.w + AREMW: 0x41 << 15, // mod.w + ADIVU: 0x42 << 15, // div.wu + ADIVWU: 0x42 << 15, // div.wu + AREMU: 0x43 << 15, // mod.wu + AREMWU: 0x43 << 15, // mod.wu + ADIVV: 0x44 << 15, // div.d + AREMV: 0x45 << 15, // mod.d + ADIVVU: 0x46 << 15, // div.du + AREMVU: 0x47 << 15, // mod.du + ACRCWBW: 0x48 << 15, // crc.w.b.w + ACRCWHW: 0x49 << 15, // crc.w.h.w + ACRCWWW: 0x4a << 15, // crc.w.w.w + ACRCWVW: 0x4b << 15, // crc.w.d.w + ACRCCWBW: 0x4c << 15, // crcc.w.b.w + ACRCCWHW: 0x4d << 15, // crcc.w.h.w + ACRCCWWW: 0x4e << 15, // crcc.w.w.w + ACRCCWVW: 0x4f << 15, // crcc.w.d.w + AJMP: 0x13 << 26, // jirl r0, rj, 0 + AJAL: 0x13<<26 | 1<<0, // jirl r1, rj, 0 + AMULF: 0x209 << 15, // fmul.s + AMULD: 0x20a << 15, // fmul.d + ADIVF: 0x20d << 15, // fdiv.s + ADIVD: 0x20e << 15, // fdiv.d + ASUBF: 0x205 << 15, // fsub.s + ASUBD: 0x206 << 15, // fsub.d + AADDF: 0x201 << 15, // fadd.s + AADDD: 0x202 << 15, // fadd.d + ACMPEQF: 0x0c1<<20 | 0x4<<15, // FCMP.CEQ.S + ACMPEQD: 0x0c2<<20 | 0x4<<15, // FCMP.CEQ.D + ACMPGED: 0x0c2<<20 | 0x7<<15, // FCMP.SLE.D + ACMPGEF: 0x0c1<<20 | 0x7<<15, // FCMP.SLE.S + ACMPGTD: 0x0c2<<20 | 0x3<<15, // FCMP.SLT.D + ACMPGTF: 0x0c1<<20 | 0x3<<15, // FCMP.SLT.S + AFMINF: 0x215 << 15, // fmin.s + AFMIND: 0x216 << 15, // fmin.d + AFMAXF: 0x211 << 15, // fmax.s + AFMAXD: 0x212 << 15, // fmax.d + AFMAXAF: 0x219 << 15, // fmaxa.s + AFMAXAD: 0x21a << 15, // fmaxa.d + AFMINAF: 0x21d << 15, // fmina.s + AFMINAD: 0x21e << 15, // fmina.d + AFSCALEBF: 0x221 << 15, // fscaleb.s + AFSCALEBD: 0x222 << 15, // fscaleb.d + AFCOPYSGF: 0x225 << 15, // fcopysign.s + AFCOPYSGD: 0x226 << 15, // fcopysign.d + -AMOVB: 0x07000 << 15, // ldx.b + -AMOVH: 0x07008 << 15, // ldx.h + -AMOVW: 0x07010 << 15, // ldx.w + -AMOVV: 0x07018 << 15, // ldx.d + -AMOVBU: 0x07040 << 15, // ldx.bu + -AMOVHU: 0x07048 << 15, // ldx.hu + -AMOVWU: 0x07050 << 15, // ldx.wu + AMOVB: 0x07020 << 15, // stx.b + AMOVH: 0x07028 << 15, // stx.h + AMOVW: 0x07030 << 15, // stx.w + AMOVV: 0x07038 << 15, // stx.d + -AMOVF: 0x07060 << 15, // fldx.s + -AMOVD: 0x07068 << 15, // fldx.d + AMOVF: 0x07070 << 15, // fstx.s + AMOVD: 0x07078 << 15, // fstx.d + -AVMOVQ: 0x07080 << 15, // vldx + -AXVMOVQ: 0x07090 << 15, // xvldx + AVMOVQ: 0x07088 << 15, // vstx + AXVMOVQ: 0x07098 << 15, // xvstx + AVSEQB: 0x0e000 << 15, // vseq.b + AXVSEQB: 0x0e800 << 15, // xvseq.b + AVSEQH: 0x0e001 << 15, // vseq.h + AXVSEQH: 0x0e801 << 15, // xvseq.h + AVSEQW: 0x0e002 << 15, // vseq.w + AXVSEQW: 0x0e802 << 15, // xvseq.w + AVSEQV: 0x0e003 << 15, // vseq.d + AXVSEQV: 0x0e803 << 15, // xvseq.d + AVSLTB: 0x0e00c << 15, // vslt.b + AVSLTH: 0x0e00d << 15, // vslt.h + AVSLTW: 0x0e00e << 15, // vslt.w + AVSLTV: 0x0e00f << 15, // vslt.d + AVSLTBU: 0x0e010 << 15, // vslt.bu + AVSLTHU: 0x0e011 << 15, // vslt.hu + AVSLTWU: 0x0e012 << 15, // vslt.wu + AVSLTVU: 0x0e013 << 15, // vslt.du + AXVSLTB: 0x0e80c << 15, // xvslt.b + AXVSLTH: 0x0e80d << 15, // xvslt.h + AXVSLTW: 0x0e80e << 15, // xvslt.w + AXVSLTV: 0x0e80f << 15, // xvslt.d + AXVSLTBU: 0x0e810 << 15, // xvslt.bu + AXVSLTHU: 0x0e811 << 15, // xvslt.hu + AXVSLTWU: 0x0e812 << 15, // xvslt.wu + AXVSLTVU: 0x0e813 << 15, // xvslt.du + AVANDV: 0x0e24c << 15, // vand.v + AVORV: 0x0e24d << 15, // vor.v + AVXORV: 0x0e24e << 15, // vxor.v + AVNORV: 0x0e24f << 15, // vnor.v + AVANDNV: 0x0e250 << 15, // vandn.v + AVORNV: 0x0e251 << 15, // vorn.v + AXVANDV: 0x0ea4c << 15, // xvand.v + AXVORV: 0x0ea4d << 15, // xvor.v + AXVXORV: 0x0ea4e << 15, // xvxor.v + AXVNORV: 0x0ea4f << 15, // xvnor.v + AXVANDNV: 0x0ea50 << 15, // xvandn.v + AXVORNV: 0x0ea51 << 15, // xvorn.v + AVDIVB: 0xe1c0 << 15, // vdiv.b + AVDIVH: 0xe1c1 << 15, // vdiv.h + AVDIVW: 0xe1c2 << 15, // vdiv.w + AVDIVV: 0xe1c3 << 15, // vdiv.d + AVMODB: 0xe1c4 << 15, // vmod.b + AVMODH: 0xe1c5 << 15, // vmod.h + AVMODW: 0xe1c6 << 15, // vmod.w + AVMODV: 0xe1c7 << 15, // vmod.d + AVDIVBU: 0xe1c8 << 15, // vdiv.bu + AVDIVHU: 0xe1c9 << 15, // vdiv.hu + AVDIVWU: 0xe1ca << 15, // vdiv.wu + AVDIVVU: 0xe1cb << 15, // vdiv.du + AVMODBU: 0xe1cc << 15, // vmod.bu + AVMODHU: 0xe1cd << 15, // vmod.hu + AVMODWU: 0xe1ce << 15, // vmod.wu + AVMODVU: 0xe1cf << 15, // vmod.du + AXVDIVB: 0xe9c0 << 15, // xvdiv.b + AXVDIVH: 0xe9c1 << 15, // xvdiv.h + AXVDIVW: 0xe9c2 << 15, // xvdiv.w + AXVDIVV: 0xe9c3 << 15, // xvdiv.d + AXVMODB: 0xe9c4 << 15, // xvmod.b + AXVMODH: 0xe9c5 << 15, // xvmod.h + AXVMODW: 0xe9c6 << 15, // xvmod.w + AXVMODV: 0xe9c7 << 15, // xvmod.d + AXVDIVBU: 0xe9c8 << 15, // xvdiv.bu + AXVDIVHU: 0xe9c9 << 15, // xvdiv.hu + AXVDIVWU: 0xe9ca << 15, // xvdiv.wu + AXVDIVVU: 0xe9cb << 15, // xvdiv.du + AXVMODBU: 0xe9cc << 15, // xvmod.bu + AXVMODHU: 0xe9cd << 15, // xvmod.hu + AXVMODWU: 0xe9ce << 15, // xvmod.wu + AXVMODVU: 0xe9cf << 15, // xvmod.du + AVMULWEVHB: 0xe120 << 15, // vmulwev.h.b + AVMULWEVWH: 0xe121 << 15, // vmulwev.w.h + AVMULWEVVW: 0xe122 << 15, // vmulwev.d.w + AVMULWEVQV: 0xe123 << 15, // vmulwev.q.d + AVMULWODHB: 0xe124 << 15, // vmulwod.h.b + AVMULWODWH: 0xe125 << 15, // vmulwod.w.h + AVMULWODVW: 0xe126 << 15, // vmulwod.d.w + AVMULWODQV: 0xe127 << 15, // vmulwod.q.d + AVMULWEVHBU: 0xe130 << 15, // vmulwev.h.bu + AVMULWEVWHU: 0xe131 << 15, // vmulwev.w.hu + AVMULWEVVWU: 0xe132 << 15, // vmulwev.d.wu + AVMULWEVQVU: 0xe133 << 15, // vmulwev.q.du + AVMULWODHBU: 0xe134 << 15, // vmulwod.h.bu + AVMULWODWHU: 0xe135 << 15, // vmulwod.w.hu + AVMULWODVWU: 0xe136 << 15, // vmulwod.d.wu + AVMULWODQVU: 0xe137 << 15, // vmulwod.q.du + AVMULWEVHBUB: 0xe140 << 15, // vmulwev.h.bu.b + AVMULWEVWHUH: 0xe141 << 15, // vmulwev.w.hu.h + AVMULWEVVWUW: 0xe142 << 15, // vmulwev.d.wu.w + AVMULWEVQVUV: 0xe143 << 15, // vmulwev.q.du.d + AVMULWODHBUB: 0xe144 << 15, // vmulwod.h.bu.b + AVMULWODWHUH: 0xe145 << 15, // vmulwod.w.hu.h + AVMULWODVWUW: 0xe146 << 15, // vmulwod.d.wu.w + AVMULWODQVUV: 0xe147 << 15, // vmulwod.q.du.d + AXVMULWEVHB: 0xe920 << 15, // xvmulwev.h.b + AXVMULWEVWH: 0xe921 << 15, // xvmulwev.w.h + AXVMULWEVVW: 0xe922 << 15, // xvmulwev.d.w + AXVMULWEVQV: 0xe923 << 15, // xvmulwev.q.d + AXVMULWODHB: 0xe924 << 15, // xvmulwod.h.b + AXVMULWODWH: 0xe925 << 15, // xvmulwod.w.h + AXVMULWODVW: 0xe926 << 15, // xvmulwod.d.w + AXVMULWODQV: 0xe927 << 15, // xvmulwod.q.d + AXVMULWEVHBU: 0xe930 << 15, // xvmulwev.h.bu + AXVMULWEVWHU: 0xe931 << 15, // xvmulwev.w.hu + AXVMULWEVVWU: 0xe932 << 15, // xvmulwev.d.wu + AXVMULWEVQVU: 0xe933 << 15, // xvmulwev.q.du + AXVMULWODHBU: 0xe934 << 15, // xvmulwod.h.bu + AXVMULWODWHU: 0xe935 << 15, // xvmulwod.w.hu + AXVMULWODVWU: 0xe936 << 15, // xvmulwod.d.wu + AXVMULWODQVU: 0xe937 << 15, // xvmulwod.q.du + AXVMULWEVHBUB: 0xe940 << 15, // xvmulwev.h.bu.b + AXVMULWEVWHUH: 0xe941 << 15, // xvmulwev.w.hu.h + AXVMULWEVVWUW: 0xe942 << 15, // xvmulwev.d.wu.w + AXVMULWEVQVUV: 0xe943 << 15, // xvmulwev.q.du.d + AXVMULWODHBUB: 0xe944 << 15, // xvmulwod.h.bu.b + AXVMULWODWHUH: 0xe945 << 15, // xvmulwod.w.hu.h + AXVMULWODVWUW: 0xe946 << 15, // xvmulwod.d.wu.w + AXVMULWODQVUV: 0xe947 << 15, // xvmulwod.q.du.d + AVADDWEVHB: 0x0e03c << 15, // vaddwev.h.b + AVADDWEVWH: 0x0e03d << 15, // vaddwev.w.h + AVADDWEVVW: 0x0e03e << 15, // vaddwev.d.w + AVADDWEVQV: 0x0e03f << 15, // vaddwev.q.d + AVSUBWEVHB: 0x0e040 << 15, // vsubwev.h.b + AVSUBWEVWH: 0x0e041 << 15, // vsubwev.w.h + AVSUBWEVVW: 0x0e042 << 15, // vsubwev.d.w + AVSUBWEVQV: 0x0e043 << 15, // vsubwev.q.d + AVADDWODHB: 0x0e044 << 15, // vaddwod.h.b + AVADDWODWH: 0x0e045 << 15, // vaddwod.w.h + AVADDWODVW: 0x0e046 << 15, // vaddwod.d.w + AVADDWODQV: 0x0e047 << 15, // vaddwod.q.d + AVSUBWODHB: 0x0e048 << 15, // vsubwod.h.b + AVSUBWODWH: 0x0e049 << 15, // vsubwod.w.h + AVSUBWODVW: 0x0e04a << 15, // vsubwod.d.w + AVSUBWODQV: 0x0e04b << 15, // vsubwod.q.d + AXVADDWEVHB: 0x0e83c << 15, // xvaddwev.h.b + AXVADDWEVWH: 0x0e83d << 15, // xvaddwev.w.h + AXVADDWEVVW: 0x0e83e << 15, // xvaddwev.d.w + AXVADDWEVQV: 0x0e83f << 15, // xvaddwev.q.d + AXVSUBWEVHB: 0x0e840 << 15, // xvsubwev.h.b + AXVSUBWEVWH: 0x0e841 << 15, // xvsubwev.w.h + AXVSUBWEVVW: 0x0e842 << 15, // xvsubwev.d.w + AXVSUBWEVQV: 0x0e843 << 15, // xvsubwev.q.d + AXVADDWODHB: 0x0e844 << 15, // xvaddwod.h.b + AXVADDWODWH: 0x0e845 << 15, // xvaddwod.w.h + AXVADDWODVW: 0x0e846 << 15, // xvaddwod.d.w + AXVADDWODQV: 0x0e847 << 15, // xvaddwod.q.d + AXVSUBWODHB: 0x0e848 << 15, // xvsubwod.h.b + AXVSUBWODWH: 0x0e849 << 15, // xvsubwod.w.h + AXVSUBWODVW: 0x0e84a << 15, // xvsubwod.d.w + AXVSUBWODQV: 0x0e84b << 15, // xvsubwod.q.d + AVADDWEVHBU: 0x0e05c << 15, // vaddwev.h.bu + AVADDWEVWHU: 0x0e05d << 15, // vaddwev.w.hu + AVADDWEVVWU: 0x0e05e << 15, // vaddwev.d.wu + AVADDWEVQVU: 0x0e05f << 15, // vaddwev.q.du + AVSUBWEVHBU: 0x0e060 << 15, // vsubwev.h.bu + AVSUBWEVWHU: 0x0e061 << 15, // vsubwev.w.hu + AVSUBWEVVWU: 0x0e062 << 15, // vsubwev.d.wu + AVSUBWEVQVU: 0x0e063 << 15, // vsubwev.q.du + AVADDWODHBU: 0x0e064 << 15, // vaddwod.h.bu + AVADDWODWHU: 0x0e065 << 15, // vaddwod.w.hu + AVADDWODVWU: 0x0e066 << 15, // vaddwod.d.wu + AVADDWODQVU: 0x0e067 << 15, // vaddwod.q.du + AVSUBWODHBU: 0x0e068 << 15, // vsubwod.h.bu + AVSUBWODWHU: 0x0e069 << 15, // vsubwod.w.hu + AVSUBWODVWU: 0x0e06a << 15, // vsubwod.d.wu + AVSUBWODQVU: 0x0e06b << 15, // vsubwod.q.du + AXVADDWEVHBU: 0x0e85c << 15, // xvaddwev.h.bu + AXVADDWEVWHU: 0x0e85d << 15, // xvaddwev.w.hu + AXVADDWEVVWU: 0x0e85e << 15, // xvaddwev.d.wu + AXVADDWEVQVU: 0x0e85f << 15, // xvaddwev.q.du + AXVSUBWEVHBU: 0x0e860 << 15, // xvsubwev.h.bu + AXVSUBWEVWHU: 0x0e861 << 15, // xvsubwev.w.hu + AXVSUBWEVVWU: 0x0e862 << 15, // xvsubwev.d.wu + AXVSUBWEVQVU: 0x0e863 << 15, // xvsubwev.q.du + AXVADDWODHBU: 0x0e864 << 15, // xvaddwod.h.bu + AXVADDWODWHU: 0x0e865 << 15, // xvaddwod.w.hu + AXVADDWODVWU: 0x0e866 << 15, // xvaddwod.d.wu + AXVADDWODQVU: 0x0e867 << 15, // xvaddwod.q.du + AXVSUBWODHBU: 0x0e868 << 15, // xvsubwod.h.bu + AXVSUBWODWHU: 0x0e869 << 15, // xvsubwod.w.hu + AXVSUBWODVWU: 0x0e86a << 15, // xvsubwod.d.wu + AXVSUBWODQVU: 0x0e86b << 15, // xvsubwod.q.du + AVMADDB: 0x0e150 << 15, // vmadd.b + AVMADDH: 0x0e151 << 15, // vmadd.h + AVMADDW: 0x0e152 << 15, // vmadd.w + AVMADDV: 0x0e153 << 15, // vmadd.d + AVMSUBB: 0x0e154 << 15, // vmsub.b + AVMSUBH: 0x0e155 << 15, // vmsub.h + AVMSUBW: 0x0e156 << 15, // vmsub.w + AVMSUBV: 0x0e157 << 15, // vmsub.d + AXVMADDB: 0x0e950 << 15, // xvmadd.b + AXVMADDH: 0x0e951 << 15, // xvmadd.h + AXVMADDW: 0x0e952 << 15, // xvmadd.w + AXVMADDV: 0x0e953 << 15, // xvmadd.d + AXVMSUBB: 0x0e954 << 15, // xvmsub.b + AXVMSUBH: 0x0e955 << 15, // xvmsub.h + AXVMSUBW: 0x0e956 << 15, // xvmsub.w + AXVMSUBV: 0x0e957 << 15, // xvmsub.d + AVMADDWEVHB: 0x0e158 << 15, // vmaddwev.h.b + AVMADDWEVWH: 0x0e159 << 15, // vmaddwev.w.h + AVMADDWEVVW: 0x0e15a << 15, // vmaddwev.d.w + AVMADDWEVQV: 0x0e15b << 15, // vmaddwev.q.d + AVMADDWODHB: 0x0e15c << 15, // vmaddwod.h.b + AVMADDWODWH: 0x0e15d << 15, // vmaddwod.w.h + AVMADDWODVW: 0x0e15e << 15, // vmaddwod.d.w + AVMADDWODQV: 0x0e15f << 15, // vmaddwod.q.d + AVMADDWEVHBU: 0x0e168 << 15, // vmaddwev.h.bu + AVMADDWEVWHU: 0x0e169 << 15, // vmaddwev.w.hu + AVMADDWEVVWU: 0x0e16a << 15, // vmaddwev.d.wu + AVMADDWEVQVU: 0x0e16b << 15, // vmaddwev.q.du + AVMADDWODHBU: 0x0e16c << 15, // vmaddwod.h.bu + AVMADDWODWHU: 0x0e16d << 15, // vmaddwod.w.hu + AVMADDWODVWU: 0x0e16e << 15, // vmaddwod.d.wu + AVMADDWODQVU: 0x0e16f << 15, // vmaddwod.q.du + AVMADDWEVHBUB: 0x0e178 << 15, // vmaddwev.h.bu.b + AVMADDWEVWHUH: 0x0e179 << 15, // vmaddwev.w.hu.h + AVMADDWEVVWUW: 0x0e17a << 15, // vmaddwev.d.wu.w + AVMADDWEVQVUV: 0x0e17b << 15, // vmaddwev.q.du.d + AVMADDWODHBUB: 0x0e17c << 15, // vmaddwod.h.bu.b + AVMADDWODWHUH: 0x0e17d << 15, // vmaddwod.w.hu.h + AVMADDWODVWUW: 0x0e17e << 15, // vmaddwod.d.wu.w + AVMADDWODQVUV: 0x0e17f << 15, // vmaddwod.q.du.d + AXVMADDWEVHB: 0x0e958 << 15, // xvmaddwev.h.b + AXVMADDWEVWH: 0x0e959 << 15, // xvmaddwev.w.h + AXVMADDWEVVW: 0x0e95a << 15, // xvmaddwev.d.w + AXVMADDWEVQV: 0x0e95b << 15, // xvmaddwev.q.d + AXVMADDWODHB: 0x0e95c << 15, // xvmaddwod.h.b + AXVMADDWODWH: 0x0e95d << 15, // xvmaddwod.w.h + AXVMADDWODVW: 0x0e95e << 15, // xvmaddwod.d.w + AXVMADDWODQV: 0x0e95f << 15, // xvmaddwod.q.d + AXVMADDWEVHBU: 0x0e968 << 15, // xvmaddwev.h.bu + AXVMADDWEVWHU: 0x0e969 << 15, // xvmaddwev.w.hu + AXVMADDWEVVWU: 0x0e96a << 15, // xvmaddwev.d.wu + AXVMADDWEVQVU: 0x0e96b << 15, // xvmaddwev.q.du + AXVMADDWODHBU: 0x0e96c << 15, // xvmaddwod.h.bu + AXVMADDWODWHU: 0x0e96d << 15, // xvmaddwod.w.hu + AXVMADDWODVWU: 0x0e96e << 15, // xvmaddwod.d.wu + AXVMADDWODQVU: 0x0e96f << 15, // xvmaddwod.q.du + AXVMADDWEVHBUB: 0x0e978 << 15, // xvmaddwev.h.bu.b + AXVMADDWEVWHUH: 0x0e979 << 15, // xvmaddwev.w.hu.h + AXVMADDWEVVWUW: 0x0e97a << 15, // xvmaddwev.d.wu.w + AXVMADDWEVQVUV: 0x0e97b << 15, // xvmaddwev.q.du.d + AXVMADDWODHBUB: 0x0e97c << 15, // xvmaddwod.h.bu.b + AXVMADDWODWHUH: 0x0e97d << 15, // xvmaddwod.w.hu.h + AXVMADDWODVWUW: 0x0e97e << 15, // xvmaddwod.d.wu.w + AXVMADDWODQVUV: 0x0e97f << 15, // xvmaddwod.q.du.d + AVSLLB: 0xe1d0 << 15, // vsll.b + AVSLLH: 0xe1d1 << 15, // vsll.h + AVSLLW: 0xe1d2 << 15, // vsll.w + AVSLLV: 0xe1d3 << 15, // vsll.d + AVSRLB: 0xe1d4 << 15, // vsrl.b + AVSRLH: 0xe1d5 << 15, // vsrl.h + AVSRLW: 0xe1d6 << 15, // vsrl.w + AVSRLV: 0xe1d7 << 15, // vsrl.d + AVSRAB: 0xe1d8 << 15, // vsra.b + AVSRAH: 0xe1d9 << 15, // vsra.h + AVSRAW: 0xe1da << 15, // vsra.w + AVSRAV: 0xe1db << 15, // vsra.d + AVROTRB: 0xe1dc << 15, // vrotr.b + AVROTRH: 0xe1dd << 15, // vrotr.h + AVROTRW: 0xe1de << 15, // vrotr.w + AVROTRV: 0xe1df << 15, // vrotr.d + AXVSLLB: 0xe9d0 << 15, // xvsll.b + AXVSLLH: 0xe9d1 << 15, // xvsll.h + AXVSLLW: 0xe9d2 << 15, // xvsll.w + AXVSLLV: 0xe9d3 << 15, // xvsll.d + AXVSRLB: 0xe9d4 << 15, // xvsrl.b + AXVSRLH: 0xe9d5 << 15, // xvsrl.h + AXVSRLW: 0xe9d6 << 15, // xvsrl.w + AXVSRLV: 0xe9d7 << 15, // xvsrl.d + AXVSRAB: 0xe9d8 << 15, // xvsra.b + AXVSRAH: 0xe9d9 << 15, // xvsra.h + AXVSRAW: 0xe9da << 15, // xvsra.w + AXVSRAV: 0xe9db << 15, // xvsra.d + AXVROTRB: 0xe9dc << 15, // xvrotr.b + AXVROTRH: 0xe9dd << 15, // xvrotr.h + AXVROTRW: 0xe9de << 15, // xvrotr.w + AXVROTRV: 0xe9df << 15, // xvrotr.d + AVADDB: 0xe014 << 15, // vadd.b + AVADDH: 0xe015 << 15, // vadd.h + AVADDW: 0xe016 << 15, // vadd.w + AVADDV: 0xe017 << 15, // vadd.d + AVADDQ: 0xe25a << 15, // vadd.q + AVSUBB: 0xe018 << 15, // vsub.b + AVSUBH: 0xe019 << 15, // vsub.h + AVSUBW: 0xe01a << 15, // vsub.w + AVSUBV: 0xe01b << 15, // vsub.d + AVSUBQ: 0xe25b << 15, // vsub.q + AXVADDB: 0xe814 << 15, // xvadd.b + AXVADDH: 0xe815 << 15, // xvadd.h + AXVADDW: 0xe816 << 15, // xvadd.w + AXVADDV: 0xe817 << 15, // xvadd.d + AXVADDQ: 0xea5a << 15, // xvadd.q + AXVSUBB: 0xe818 << 15, // xvsub.b + AXVSUBH: 0xe819 << 15, // xvsub.h + AXVSUBW: 0xe81a << 15, // xvsub.w + AXVSUBV: 0xe81b << 15, // xvsub.d + AXVSUBQ: 0xea5b << 15, // xvsub.q + AVSADDB: 0x0e08c << 15, // vsadd.b + AVSADDH: 0x0e08d << 15, // vsadd.h + AVSADDW: 0x0e08e << 15, // vsadd.w + AVSADDV: 0x0e08f << 15, // vsadd.d + AVSSUBB: 0x0e090 << 15, // vssub.b + AVSSUBH: 0x0e091 << 15, // vssub.w + AVSSUBW: 0x0e092 << 15, // vssub.h + AVSSUBV: 0x0e093 << 15, // vssub.d + AVSADDBU: 0x0e094 << 15, // vsadd.bu + AVSADDHU: 0x0e095 << 15, // vsadd.hu + AVSADDWU: 0x0e096 << 15, // vsadd.wu + AVSADDVU: 0x0e097 << 15, // vsadd.du + AVSSUBBU: 0x0e098 << 15, // vssub.bu + AVSSUBHU: 0x0e099 << 15, // vssub.wu + AVSSUBWU: 0x0e09a << 15, // vssub.hu + AVSSUBVU: 0x0e09b << 15, // vssub.du + AXVSADDB: 0x0e88c << 15, // vxsadd.b + AXVSADDH: 0x0e88d << 15, // vxsadd.h + AXVSADDW: 0x0e88e << 15, // vxsadd.w + AXVSADDV: 0x0e88f << 15, // vxsadd.d + AXVSSUBB: 0x0e890 << 15, // xvssub.b + AXVSSUBH: 0x0e891 << 15, // xvssub.h + AXVSSUBW: 0x0e892 << 15, // xvssub.w + AXVSSUBV: 0x0e893 << 15, // xvssub.d + AXVSADDBU: 0x0e894 << 15, // vxsadd.bu + AXVSADDHU: 0x0e895 << 15, // vxsadd.hu + AXVSADDWU: 0x0e896 << 15, // vxsadd.wu + AXVSADDVU: 0x0e897 << 15, // vxsadd.du + AXVSSUBBU: 0x0e898 << 15, // xvssub.bu + AXVSSUBHU: 0x0e899 << 15, // xvssub.hu + AXVSSUBWU: 0x0e89a << 15, // xvssub.wu + AXVSSUBVU: 0x0e89b << 15, // xvssub.du + AVILVLB: 0xe234 << 15, // vilvl.b + AVILVLH: 0xe235 << 15, // vilvl.h + AVILVLW: 0xe236 << 15, // vilvl.w + AVILVLV: 0xe237 << 15, // vilvl.d + AVILVHB: 0xe238 << 15, // vilvh.b + AVILVHH: 0xe239 << 15, // vilvh.h + AVILVHW: 0xe23a << 15, // vilvh.w + AVILVHV: 0xe23b << 15, // vilvh.d + AXVILVLB: 0xea34 << 15, // xvilvl.b + AXVILVLH: 0xea35 << 15, // xvilvl.h + AXVILVLW: 0xea36 << 15, // xvilvl.w + AXVILVLV: 0xea37 << 15, // xvilvl.d + AXVILVHB: 0xea38 << 15, // xvilvh.b + AXVILVHH: 0xea39 << 15, // xvilvh.h + AXVILVHW: 0xea3a << 15, // xvilvh.w + AXVILVHV: 0xea3b << 15, // xvilvh.d + AVMULB: 0xe108 << 15, // vmul.b + AVMULH: 0xe109 << 15, // vmul.h + AVMULW: 0xe10a << 15, // vmul.w + AVMULV: 0xe10b << 15, // vmul.d + AVMUHB: 0xe10c << 15, // vmuh.b + AVMUHH: 0xe10d << 15, // vmuh.h + AVMUHW: 0xe10e << 15, // vmuh.w + AVMUHV: 0xe10f << 15, // vmuh.d + AVMUHBU: 0xe110 << 15, // vmuh.bu + AVMUHHU: 0xe111 << 15, // vmuh.hu + AVMUHWU: 0xe112 << 15, // vmuh.wu + AVMUHVU: 0xe113 << 15, // vmuh.du + AXVMULB: 0xe908 << 15, // xvmul.b + AXVMULH: 0xe909 << 15, // xvmul.h + AXVMULW: 0xe90a << 15, // xvmul.w + AXVMULV: 0xe90b << 15, // xvmul.d + AXVMUHB: 0xe90c << 15, // xvmuh.b + AXVMUHH: 0xe90d << 15, // xvmuh.h + AXVMUHW: 0xe90e << 15, // xvmuh.w + AXVMUHV: 0xe90f << 15, // xvmuh.d + AXVMUHBU: 0xe910 << 15, // xvmuh.bu + AXVMUHHU: 0xe911 << 15, // xvmuh.hu + AXVMUHWU: 0xe912 << 15, // xvmuh.wu + AXVMUHVU: 0xe913 << 15, // xvmuh.du + AVADDF: 0xe261 << 15, // vfadd.s + AVADDD: 0xe262 << 15, // vfadd.d + AVSUBF: 0xe265 << 15, // vfsub.s + AVSUBD: 0xe266 << 15, // vfsub.d + AVMULF: 0xe271 << 15, // vfmul.s + AVMULD: 0xe272 << 15, // vfmul.d + AVDIVF: 0xe275 << 15, // vfdiv.s + AVDIVD: 0xe276 << 15, // vfdiv.d + AXVADDF: 0xea61 << 15, // xvfadd.s + AXVADDD: 0xea62 << 15, // xvfadd.d + AXVSUBF: 0xea65 << 15, // xvfsub.s + AXVSUBD: 0xea66 << 15, // xvfsub.d + AXVMULF: 0xea71 << 15, // xvfmul.s + AXVMULD: 0xea72 << 15, // xvfmul.d + AXVDIVF: 0xea75 << 15, // xvfdiv.s + AXVDIVD: 0xea76 << 15, // xvfdiv.d + AVBITCLRB: 0xe218 << 15, // vbitclr.b + AVBITCLRH: 0xe219 << 15, // vbitclr.h + AVBITCLRW: 0xe21a << 15, // vbitclr.w + AVBITCLRV: 0xe21b << 15, // vbitclr.d + AVBITSETB: 0xe21c << 15, // vbitset.b + AVBITSETH: 0xe21d << 15, // vbitset.h + AVBITSETW: 0xe21e << 15, // vbitset.w + AVBITSETV: 0xe21f << 15, // vbitset.d + AVBITREVB: 0xe220 << 15, // vbitrev.b + AVBITREVH: 0xe221 << 15, // vbitrev.h + AVBITREVW: 0xe222 << 15, // vbitrev.w + AVBITREVV: 0xe223 << 15, // vbitrev.d + AXVBITCLRB: 0xea18 << 15, // xvbitclr.b + AXVBITCLRH: 0xea19 << 15, // xvbitclr.h + AXVBITCLRW: 0xea1a << 15, // xvbitclr.w + AXVBITCLRV: 0xea1b << 15, // xvbitclr.d + AXVBITSETB: 0xea1c << 15, // xvbitset.b + AXVBITSETH: 0xea1d << 15, // xvbitset.h + AXVBITSETW: 0xea1e << 15, // xvbitset.w + AXVBITSETV: 0xea1f << 15, // xvbitset.d + AXVBITREVB: 0xea20 << 15, // xvbitrev.b + AXVBITREVH: 0xea21 << 15, // xvbitrev.h + AXVBITREVW: 0xea22 << 15, // xvbitrev.w + AXVBITREVV: 0xea23 << 15, // xvbitrev.d + AVSHUFH: 0x0e2f5 << 15, // vshuf.h + AVSHUFW: 0x0e2f6 << 15, // vshuf.w + AVSHUFV: 0x0e2f7 << 15, // vshuf.d + AXVSHUFH: 0x0eaf5 << 15, // xvshuf.h + AXVSHUFW: 0x0eaf6 << 15, // xvshuf.w + AXVSHUFV: 0x0eaf7 << 15, // xvshuf.d +} + +var oprr = map[obj.As]uint32{ + ACLOW: 0x4 << 10, // clo.w + ACLZW: 0x5 << 10, // clz.w + ACTOW: 0x6 << 10, // cto.w + ACTZW: 0x7 << 10, // ctz.w + ACLOV: 0x8 << 10, // clo.d + ACLZV: 0x9 << 10, // clz.d + ACTOV: 0xa << 10, // cto.d + ACTZV: 0xb << 10, // ctz.d + AREVB2H: 0xc << 10, // revb.2h + AREVB4H: 0xd << 10, // revb.4h + AREVB2W: 0xe << 10, // revb.2w + AREVBV: 0xf << 10, // revb.d + AREVH2W: 0x10 << 10, // revh.2w + AREVHV: 0x11 << 10, // revh.d + ABITREV4B: 0x12 << 10, // bitrev.4b + ABITREV8B: 0x13 << 10, // bitrev.8b + ABITREVW: 0x14 << 10, // bitrev.w + ABITREVV: 0x15 << 10, // bitrev.d + AEXTWH: 0x16 << 10, // ext.w.h + AEXTWB: 0x17 << 10, // ext.w.h + ACPUCFG: 0x1b << 10, // cpucfg + ARDTIMELW: 0x18 << 10, // rdtimel.w + ARDTIMEHW: 0x19 << 10, // rdtimeh.w + ARDTIMED: 0x1a << 10, // rdtime.d + ALLACQW: 0x0E15E0 << 10, // ll.acq.w + ASCRELW: 0x0E15E1 << 10, // sc.rel.w + ALLACQV: 0x0E15E2 << 10, // ll.acq.d + ASCRELV: 0x0E15E3 << 10, // sc.rel.d + ATRUNCFV: 0x46a9 << 10, // ftintrz.l.s + ATRUNCDV: 0x46aa << 10, // ftintrz.l.d + ATRUNCFW: 0x46a1 << 10, // ftintrz.w.s + ATRUNCDW: 0x46a2 << 10, // ftintrz.w.d + AMOVWF: 0x4744 << 10, // ffint.s.w + AFFINTFW: 0x4744 << 10, // ffint.s.w + AMOVVF: 0x4746 << 10, // ffint.s.l + AFFINTFV: 0x4746 << 10, // ffint.s.l + AMOVWD: 0x4748 << 10, // ffint.d.w + AFFINTDW: 0x4748 << 10, // ffint.d.w + AMOVVD: 0x474a << 10, // ffint.d.l + AFFINTDV: 0x474a << 10, // ffint.d.l + AMOVFW: 0x46c1 << 10, // ftint.w.s + AFTINTWF: 0x46c1 << 10, // ftint.w.s + AMOVDW: 0x46c2 << 10, // ftint.w.d + AFTINTWD: 0x46c2 << 10, // ftint.w.d + AMOVFV: 0x46c9 << 10, // ftint.l.s + AFTINTVF: 0x46c9 << 10, // ftint.l.s + AMOVDV: 0x46ca << 10, // ftint.l.d + AFTINTVD: 0x46ca << 10, // ftint.l.d + AFRINTF: 0x4791 << 10, // frint.s + AFRINTD: 0x4792 << 10, // frint.d + AMOVDF: 0x4646 << 10, // fcvt.s.d + AMOVFD: 0x4649 << 10, // fcvt.d.s + AABSF: 0x4501 << 10, // fabs.s + AABSD: 0x4502 << 10, // fabs.d + AMOVF: 0x4525 << 10, // fmov.s + AMOVD: 0x4526 << 10, // fmov.d + ANEGF: 0x4505 << 10, // fneg.s + ANEGD: 0x4506 << 10, // fneg.d + ASQRTF: 0x4511 << 10, // fsqrt.s + ASQRTD: 0x4512 << 10, // fsqrt.d + AFLOGBF: 0x4509 << 10, // flogb.s + AFLOGBD: 0x450a << 10, // flogb.d + AFCLASSF: 0x450d << 10, // fclass.s + AFCLASSD: 0x450e << 10, // fclass.d + AFTINTRMWF: 0x4681 << 10, // ftintrm.w.s + AFTINTRMWD: 0x4682 << 10, // ftintrm.w.d + AFTINTRMVF: 0x4689 << 10, // ftintrm.l.s + AFTINTRMVD: 0x468a << 10, // ftintrm.l.d + AFTINTRPWF: 0x4691 << 10, // ftintrp.w.s + AFTINTRPWD: 0x4692 << 10, // ftintrp.w.d + AFTINTRPVF: 0x4699 << 10, // ftintrp.l.s + AFTINTRPVD: 0x469a << 10, // ftintrp.l.d + AFTINTRZWF: 0x46a1 << 10, // ftintrz.w.s + AFTINTRZWD: 0x46a2 << 10, // ftintrz.w.d + AFTINTRZVF: 0x46a9 << 10, // ftintrz.l.s + AFTINTRZVD: 0x46aa << 10, // ftintrz.l.d + AFTINTRNEWF: 0x46b1 << 10, // ftintrne.w.s + AFTINTRNEWD: 0x46b2 << 10, // ftintrne.w.d + AFTINTRNEVF: 0x46b9 << 10, // ftintrne.l.s + AFTINTRNEVD: 0x46ba << 10, // ftintrne.l.d + AVPCNTB: 0x1ca708 << 10, // vpcnt.b + AVPCNTH: 0x1ca709 << 10, // vpcnt.h + AVPCNTW: 0x1ca70a << 10, // vpcnt.w + AVPCNTV: 0x1ca70b << 10, // vpcnt.v + AXVPCNTB: 0x1da708 << 10, // xvpcnt.b + AXVPCNTH: 0x1da709 << 10, // xvpcnt.h + AXVPCNTW: 0x1da70a << 10, // xvpcnt.w + AXVPCNTV: 0x1da70b << 10, // xvpcnt.v + AVFSQRTF: 0x1ca739 << 10, // vfsqrt.s + AVFSQRTD: 0x1ca73a << 10, // vfsqrt.d + AVFRECIPF: 0x1ca73d << 10, // vfrecip.s + AVFRECIPD: 0x1ca73e << 10, // vfrecip.d + AVFRSQRTF: 0x1ca741 << 10, // vfrsqrt.s + AVFRSQRTD: 0x1ca742 << 10, // vfrsqrt.d + AXVFSQRTF: 0x1da739 << 10, // xvfsqrt.s + AXVFSQRTD: 0x1da73a << 10, // xvfsqrt.d + AXVFRECIPF: 0x1da73d << 10, // xvfrecip.s + AXVFRECIPD: 0x1da73e << 10, // xvfrecip.d + AXVFRSQRTF: 0x1da741 << 10, // xvfrsqrt.s + AXVFRSQRTD: 0x1da742 << 10, // xvfrsqrt.d + AVNEGB: 0x1ca70c << 10, // vneg.b + AVNEGH: 0x1ca70d << 10, // vneg.h + AVNEGW: 0x1ca70e << 10, // vneg.w + AVNEGV: 0x1ca70f << 10, // vneg.d + AXVNEGB: 0x1da70c << 10, // xvneg.b + AXVNEGH: 0x1da70d << 10, // xvneg.h + AXVNEGW: 0x1da70e << 10, // xvneg.w + AXVNEGV: 0x1da70f << 10, // xvneg.d + AVFRINTRNEF: 0x1ca75d << 10, // vfrintrne.s + AVFRINTRNED: 0x1ca75e << 10, // vfrintrne.d + AVFRINTRZF: 0x1ca759 << 10, // vfrintrz.s + AVFRINTRZD: 0x1ca75a << 10, // vfrintrz.d + AVFRINTRPF: 0x1ca755 << 10, // vfrintrp.s + AVFRINTRPD: 0x1ca756 << 10, // vfrintrp.d + AVFRINTRMF: 0x1ca751 << 10, // vfrintrm.s + AVFRINTRMD: 0x1ca752 << 10, // vfrintrm.d + AVFRINTF: 0x1ca74d << 10, // vfrint.s + AVFRINTD: 0x1ca74e << 10, // vfrint.d + AXVFRINTRNEF: 0x1da75d << 10, // xvfrintrne.s + AXVFRINTRNED: 0x1da75e << 10, // xvfrintrne.d + AXVFRINTRZF: 0x1da759 << 10, // xvfrintrz.s + AXVFRINTRZD: 0x1da75a << 10, // xvfrintrz.d + AXVFRINTRPF: 0x1da755 << 10, // xvfrintrp.s + AXVFRINTRPD: 0x1da756 << 10, // xvfrintrp.d + AXVFRINTRMF: 0x1da751 << 10, // xvfrintrm.s + AXVFRINTRMD: 0x1da752 << 10, // xvfrintrm.d + AXVFRINTF: 0x1da74d << 10, // xvfrint.s + AXVFRINTD: 0x1da74e << 10, // xvfrint.d + AVFCLASSF: 0x1ca735 << 10, // vfclass.s + AVFCLASSD: 0x1ca736 << 10, // vfclass.d + AXVFCLASSF: 0x1da735 << 10, // xvfclass.s + AXVFCLASSD: 0x1da736 << 10, // xvfclass.d + AVSETEQV: 0x1ca726<<10 | 0x0<<3, // vseteqz.v + AVSETNEV: 0x1ca727<<10 | 0x0<<3, // vsetnez.v + AVSETANYEQB: 0x1ca728<<10 | 0x0<<3, // vsetanyeqz.b + AVSETANYEQH: 0x1ca729<<10 | 0x0<<3, // vsetanyeqz.h + AVSETANYEQW: 0x1ca72a<<10 | 0x0<<3, // vsetanyeqz.w + AVSETANYEQV: 0x1ca72b<<10 | 0x0<<3, // vsetanyeqz.d + AVSETALLNEB: 0x1ca72c<<10 | 0x0<<3, // vsetallnez.b + AVSETALLNEH: 0x1ca72d<<10 | 0x0<<3, // vsetallnez.h + AVSETALLNEW: 0x1ca72e<<10 | 0x0<<3, // vsetallnez.w + AVSETALLNEV: 0x1ca72f<<10 | 0x0<<3, // vsetallnez.d + AXVSETEQV: 0x1da726<<10 | 0x0<<3, // xvseteqz.v + AXVSETNEV: 0x1da727<<10 | 0x0<<3, // xvsetnez.v + AXVSETANYEQB: 0x1da728<<10 | 0x0<<3, // xvsetanyeqz.b + AXVSETANYEQH: 0x1da729<<10 | 0x0<<3, // xvsetanyeqz.h + AXVSETANYEQW: 0x1da72a<<10 | 0x0<<3, // xvsetanyeqz.w + AXVSETANYEQV: 0x1da72b<<10 | 0x0<<3, // xvsetanyeqz.d + AXVSETALLNEB: 0x1da72c<<10 | 0x0<<3, // xvsetallnez.b + AXVSETALLNEH: 0x1da72d<<10 | 0x0<<3, // xvsetallnez.h + AXVSETALLNEW: 0x1da72e<<10 | 0x0<<3, // xvsetallnez.w + AXVSETALLNEV: 0x1da72f<<10 | 0x0<<3, // xvsetallnez.d +} + +var opi = map[obj.As]uint32{ + ASYSCALL: 0x56 << 15, // syscall + ABREAK: 0x54 << 15, // break + ADBAR: 0x70e4 << 15, // dbar +} + +var opir = map[obj.As]uint32{ + ALU12IW: 0x0a << 25, // lu12i.w + ALU32ID: 0x0b << 25, // lu32i.d + APCALAU12I: 0x0d << 25, // pcalau12i + APCADDU12I: 0x0e << 25, // pcaddu12i +} + +var opirr = map[obj.As]uint32{ + ASGT: 0x008 << 22, // slti + ASGTU: 0x009 << 22, // sltui + AADD: 0x00a << 22, // addi.w + AADDW: 0x00a << 22, // addi.w + AADDV: 0x00b << 22, // addi.d + AADDVU: 0x00b << 22, // addi.d + ALU52ID: 0x00c << 22, // lu52i.d + AAND: 0x00d << 22, // andi + AOR: 0x00e << 22, // ori + AXOR: 0x00f << 22, // xori + ASLL: 0x00081 << 15, // slli.w + ASRL: 0x00089 << 15, // srli.w + ASRA: 0x00091 << 15, // srai.w + AROTR: 0x00099 << 15, // rotri.w + AADDV16: 0x4 << 26, // addu16i.d + -ABEQ: 0x10 << 26, // beqz + -ABNE: 0x11 << 26, // bnez + AJIRL: 0x13 << 26, // jirl + AJMP: 0x14 << 26, // b + AJAL: 0x15 << 26, // bl + ABEQ: 0x16 << 26, // beq + ABNE: 0x17 << 26, // bne + ABLT: 0x18 << 26, // blt + ABLTZ: 0x18 << 26, // blt + ABGTZ: 0x18 << 26, // blt + ABGE: 0x19 << 26, // bge + ABGEZ: 0x19 << 26, // bge + ABLEZ: 0x19 << 26, // bge + ABLTU: 0x1a << 26, // bltu + ABGEU: 0x1b << 26, // bgeu + ABFPT: 0x12<<26 | 0x1<<8, // bcnez + ABFPF: 0x12<<26 | 0x0<<8, // bceqz + APRELDX: 0x07058 << 15, // preldx + -AMOVB: 0x0a0 << 22, // ld.b + -AMOVH: 0x0a1 << 22, // ld.h + -AMOVW: 0x0a2 << 22, // ld.w + -AMOVV: 0x0a3 << 22, // ld.d + AMOVB: 0x0a4 << 22, // st.b + AMOVBU: 0x0a4 << 22, // st.b + AMOVH: 0x0a5 << 22, // st.h + AMOVHU: 0x0a5 << 22, // st.h + AMOVW: 0x0a6 << 22, // st.w + AMOVWU: 0x0a6 << 22, // st.w + AMOVV: 0x0a7 << 22, // st.d + -AMOVBU: 0x0a8 << 22, // ld.bu + -AMOVHU: 0x0a9 << 22, // ld.hu + -AMOVWU: 0x0aa << 22, // ld.wu + -AMOVF: 0x0ac << 22, // fld.s + AMOVF: 0x0ad << 22, // fst.s + -AMOVD: 0x0ae << 22, // fld.d + AMOVD: 0x0af << 22, // fst.d + -ALL: 0x020 << 24, // ll.w + -ALLW: 0x020 << 24, // ll.w + ASC: 0x021 << 24, // sc.w + ASCW: 0x021 << 24, // sc.w + -ALLV: 0x022 << 24, // ll.d + ASCV: 0x023 << 24, // sc.d + -AMOVWP: 0x24 << 24, // ldptr.w + AMOVWP: 0x25 << 24, // stptr.w + -AMOVVP: 0x26 << 24, // ldptr.d + AMOVVP: 0x27 << 24, // stptr.d + -AVMOVQ: 0x0b0 << 22, // vld + AVMOVQ: 0x0b1 << 22, // vst + -AXVMOVQ: 0x0b2 << 22, // xvld + AXVMOVQ: 0x0b3 << 22, // xvst + ASLLV: 0x0041 << 16, // slli.d + ASRLV: 0x0045 << 16, // srli.d + ASRAV: 0x0049 << 16, // srai.d + AROTRV: 0x004d << 16, // rotri.d + AVANDB: 0x1cf4 << 18, // vandi.b + AVORB: 0x1cf5 << 18, // vori.b + AVXORB: 0x1cf6 << 18, // xori.b + AVNORB: 0x1cf7 << 18, // xnori.b + AXVANDB: 0x1df4 << 18, // xvandi.b + AXVORB: 0x1df5 << 18, // xvori.b + AXVXORB: 0x1df6 << 18, // xvxori.b + AXVNORB: 0x1df7 << 18, // xvnor.b + AVSEQB: 0x0e500 << 15, // vseqi.b + AVSEQH: 0x0e501 << 15, // vseqi.h + AVSEQW: 0x0e502 << 15, // vseqi.w + AVSEQV: 0x0e503 << 15, // vseqi.d + AXVSEQB: 0x0ed00 << 15, // xvseqi.b + AXVSEQH: 0x0ed01 << 15, // xvseqi.h + AXVSEQW: 0x0ed02 << 15, // xvseqi.w + AXVSEQV: 0x0ed03 << 15, // xvseqi.d + AVSLTB: 0x0e50c << 15, // vslti.b + AVSLTH: 0x0e50d << 15, // vslti.h + AVSLTW: 0x0e50e << 15, // vslti.w + AVSLTV: 0x0e50f << 15, // vslti.d + AVSLTBU: 0x0e510 << 15, // vslti.bu + AVSLTHU: 0x0e511 << 15, // vslti.hu + AVSLTWU: 0x0e512 << 15, // vslti.wu + AVSLTVU: 0x0e513 << 15, // vslti.du + AXVSLTB: 0x0ed0c << 15, // xvslti.b + AXVSLTH: 0x0ed0d << 15, // xvslti.h + AXVSLTW: 0x0ed0e << 15, // xvslti.w + AXVSLTV: 0x0ed0f << 15, // xvslti.d + AXVSLTBU: 0x0ed10 << 15, // xvslti.bu + AXVSLTHU: 0x0ed11 << 15, // xvslti.hu + AXVSLTWU: 0x0ed12 << 15, // xvslti.wu + AXVSLTVU: 0x0ed13 << 15, // xvslti.du + AVROTRB: 0x1ca8<<18 | 0x1<<13, // vrotri.b + AVROTRH: 0x1ca8<<18 | 0x1<<14, // vrotri.h + AVROTRW: 0x1ca8<<18 | 0x1<<15, // vrotri.w + AVROTRV: 0x1ca8<<18 | 0x1<<16, // vrotri.d + AXVROTRB: 0x1da8<<18 | 0x1<<13, // xvrotri.b + AXVROTRH: 0x1da8<<18 | 0x1<<14, // xvrotri.h + AXVROTRW: 0x1da8<<18 | 0x1<<15, // xvrotri.w + AXVROTRV: 0x1da8<<18 | 0x1<<16, // xvrotri.d + AVSLLB: 0x1ccb<<18 | 0x1<<13, // vslli.b + AVSLLH: 0x1ccb<<18 | 0x1<<14, // vslli.h + AVSLLW: 0x1ccb<<18 | 0x1<<15, // vslli.w + AVSLLV: 0x1ccb<<18 | 0x1<<16, // vslli.d + AVSRLB: 0x1ccc<<18 | 0x1<<13, // vsrli.b + AVSRLH: 0x1ccc<<18 | 0x1<<14, // vsrli.h + AVSRLW: 0x1ccc<<18 | 0x1<<15, // vsrli.w + AVSRLV: 0x1ccc<<18 | 0x1<<16, // vsrli.d + AVSRAB: 0x1ccd<<18 | 0x1<<13, // vsrai.b + AVSRAH: 0x1ccd<<18 | 0x1<<14, // vsrai.h + AVSRAW: 0x1ccd<<18 | 0x1<<15, // vsrai.w + AVSRAV: 0x1ccd<<18 | 0x1<<16, // vsrai.d + AXVSLLB: 0x1dcb<<18 | 0x1<<13, // xvslli.b + AXVSLLH: 0x1dcb<<18 | 0x1<<14, // xvslli.h + AXVSLLW: 0x1dcb<<18 | 0x1<<15, // xvslli.w + AXVSLLV: 0x1dcb<<18 | 0x1<<16, // xvslli.d + AXVSRLB: 0x1dcc<<18 | 0x1<<13, // xvsrli.b + AXVSRLH: 0x1dcc<<18 | 0x1<<14, // xvsrli.h + AXVSRLW: 0x1dcc<<18 | 0x1<<15, // xvsrli.w + AXVSRLV: 0x1dcc<<18 | 0x1<<16, // xvsrli.d + AXVSRAB: 0x1dcd<<18 | 0x1<<13, // xvsrai.b + AXVSRAH: 0x1dcd<<18 | 0x1<<14, // xvsrai.h + AXVSRAW: 0x1dcd<<18 | 0x1<<15, // xvsrai.w + AXVSRAV: 0x1dcd<<18 | 0x1<<16, // xvsrai.d + AVADDBU: 0xe514 << 15, // vaddi.bu + AVADDHU: 0xe515 << 15, // vaddi.hu + AVADDWU: 0xe516 << 15, // vaddi.wu + AVADDVU: 0xe517 << 15, // vaddi.du + AVSUBBU: 0xe518 << 15, // vsubi.bu + AVSUBHU: 0xe519 << 15, // vsubi.hu + AVSUBWU: 0xe51a << 15, // vsubi.wu + AVSUBVU: 0xe51b << 15, // vsubi.du + AXVADDBU: 0xed14 << 15, // xvaddi.bu + AXVADDHU: 0xed15 << 15, // xvaddi.hu + AXVADDWU: 0xed16 << 15, // xvaddi.wu + AXVADDVU: 0xed17 << 15, // xvaddi.du + AXVSUBBU: 0xed18 << 15, // xvsubi.bu + AXVSUBHU: 0xed19 << 15, // xvsubi.hu + AXVSUBWU: 0xed1a << 15, // xvsubi.wu + AXVSUBVU: 0xed1b << 15, // xvsubi.du + AVSHUF4IB: 0x1ce4 << 18, // vshuf4i.b + AVSHUF4IH: 0x1ce5 << 18, // vshuf4i.h + AVSHUF4IW: 0x1ce6 << 18, // vshuf4i.w + AVSHUF4IV: 0x1ce7 << 18, // vshuf4i.d + AXVSHUF4IB: 0x1de4 << 18, // xvshuf4i.b + AXVSHUF4IH: 0x1de5 << 18, // xvshuf4i.h + AXVSHUF4IW: 0x1de6 << 18, // xvshuf4i.w + AXVSHUF4IV: 0x1de7 << 18, // xvshuf4i.d + AVPERMIW: 0x1cf9 << 18, // vpermi.w + AXVPERMIW: 0x1df9 << 18, // xvpermi.w + AXVPERMIV: 0x1dfa << 18, // xvpermi.d + AXVPERMIQ: 0x1dfb << 18, // xvpermi.q + AVEXTRINSB: 0x1ce3 << 18, // vextrins.b + AVEXTRINSH: 0x1ce2 << 18, // vextrins.h + AVEXTRINSW: 0x1ce1 << 18, // vextrins.w + AVEXTRINSV: 0x1ce0 << 18, // vextrins.d + AXVEXTRINSB: 0x1de3 << 18, // xvextrins.b + AXVEXTRINSH: 0x1de2 << 18, // xvextrins.h + AXVEXTRINSW: 0x1de1 << 18, // xvextrins.w + AXVEXTRINSV: 0x1de0 << 18, // xvextrins.d + AVBITCLRB: 0x1cc4<<18 | 0x1<<13, // vbitclri.b + AVBITCLRH: 0x1cc4<<18 | 0x1<<14, // vbitclri.h + AVBITCLRW: 0x1cc4<<18 | 0x1<<15, // vbitclri.w + AVBITCLRV: 0x1cc4<<18 | 0x1<<16, // vbitclri.d + AVBITSETB: 0x1cc5<<18 | 0x1<<13, // vbitseti.b + AVBITSETH: 0x1cc5<<18 | 0x1<<14, // vbitseti.h + AVBITSETW: 0x1cc5<<18 | 0x1<<15, // vbitseti.w + AVBITSETV: 0x1cc5<<18 | 0x1<<16, // vbitseti.d + AVBITREVB: 0x1cc6<<18 | 0x1<<13, // vbitrevi.b + AVBITREVH: 0x1cc6<<18 | 0x1<<14, // vbitrevi.h + AVBITREVW: 0x1cc6<<18 | 0x1<<15, // vbitrevi.w + AVBITREVV: 0x1cc6<<18 | 0x1<<16, // vbitrevi.d + AXVBITCLRB: 0x1dc4<<18 | 0x1<<13, // xvbitclri.b + AXVBITCLRH: 0x1dc4<<18 | 0x1<<14, // xvbitclri.h + AXVBITCLRW: 0x1dc4<<18 | 0x1<<15, // xvbitclri.w + AXVBITCLRV: 0x1dc4<<18 | 0x1<<16, // xvbitclri.d + AXVBITSETB: 0x1dc5<<18 | 0x1<<13, // xvbitseti.b + AXVBITSETH: 0x1dc5<<18 | 0x1<<14, // xvbitseti.h + AXVBITSETW: 0x1dc5<<18 | 0x1<<15, // xvbitseti.w + AXVBITSETV: 0x1dc5<<18 | 0x1<<16, // xvbitseti.d + AXVBITREVB: 0x1dc6<<18 | 0x1<<13, // xvbitrevi.b + AXVBITREVH: 0x1dc6<<18 | 0x1<<14, // xvbitrevi.h + AXVBITREVW: 0x1dc6<<18 | 0x1<<15, // xvbitrevi.w + AXVBITREVV: 0x1dc6<<18 | 0x1<<16, // xvbitrevi.d +} + +var opirrr = map[obj.As]uint32{ + AALSLW: 0x2 << 17, // alsl.w + AALSLWU: 0x3 << 17, // alsl.wu + AALSLV: 0x16 << 17, // alsl.d +} + +var opirir = map[obj.As]uint32{ + ABSTRINSW: 0x3<<21 | 0x0<<15, // bstrins.w + ABSTRINSV: 0x2 << 22, // bstrins.d + ABSTRPICKW: 0x3<<21 | 0x1<<15, // bstrpick.w + ABSTRPICKV: 0x3 << 22, // bstrpick.d +} + +var opiir = map[obj.As]uint32{ + APRELD: 0x0ab << 22, // preld +} + +var atomicInst = map[obj.As]uint32{ + AAMSWAPB: 0x070B8 << 15, // amswap.b + AAMSWAPH: 0x070B9 << 15, // amswap.h + AAMSWAPW: 0x070C0 << 15, // amswap.w + AAMSWAPV: 0x070C1 << 15, // amswap.d + AAMCASB: 0x070B0 << 15, // amcas.b + AAMCASH: 0x070B1 << 15, // amcas.h + AAMCASW: 0x070B2 << 15, // amcas.w + AAMCASV: 0x070B3 << 15, // amcas.d + AAMADDW: 0x070C2 << 15, // amadd.w + AAMADDV: 0x070C3 << 15, // amadd.d + AAMANDW: 0x070C4 << 15, // amand.w + AAMANDV: 0x070C5 << 15, // amand.d + AAMORW: 0x070C6 << 15, // amor.w + AAMORV: 0x070C7 << 15, // amor.d + AAMXORW: 0x070C8 << 15, // amxor.w + AAMXORV: 0x070C9 << 15, // amxor.d + AAMMAXW: 0x070CA << 15, // ammax.w + AAMMAXV: 0x070CB << 15, // ammax.d + AAMMINW: 0x070CC << 15, // ammin.w + AAMMINV: 0x070CD << 15, // ammin.d + AAMMAXWU: 0x070CE << 15, // ammax.wu + AAMMAXVU: 0x070CF << 15, // ammax.du + AAMMINWU: 0x070D0 << 15, // ammin.wu + AAMMINVU: 0x070D1 << 15, // ammin.du + AAMSWAPDBB: 0x070BC << 15, // amswap_db.b + AAMSWAPDBH: 0x070BD << 15, // amswap_db.h + AAMSWAPDBW: 0x070D2 << 15, // amswap_db.w + AAMSWAPDBV: 0x070D3 << 15, // amswap_db.d + AAMCASDBB: 0x070B4 << 15, // amcas_db.b + AAMCASDBH: 0x070B5 << 15, // amcas_db.h + AAMCASDBW: 0x070B6 << 15, // amcas_db.w + AAMCASDBV: 0x070B7 << 15, // amcas_db.d + AAMADDDBW: 0x070D4 << 15, // amadd_db.w + AAMADDDBV: 0x070D5 << 15, // amadd_db.d + AAMANDDBW: 0x070D6 << 15, // amand_db.w + AAMANDDBV: 0x070D7 << 15, // amand_db.d + AAMORDBW: 0x070D8 << 15, // amor_db.w + AAMORDBV: 0x070D9 << 15, // amor_db.d + AAMXORDBW: 0x070DA << 15, // amxor_db.w + AAMXORDBV: 0x070DB << 15, // amxor_db.d + AAMMAXDBW: 0x070DC << 15, // ammax_db.w + AAMMAXDBV: 0x070DD << 15, // ammax_db.d + AAMMINDBW: 0x070DE << 15, // ammin_db.w + AAMMINDBV: 0x070DF << 15, // ammin_db.d + AAMMAXDBWU: 0x070E0 << 15, // ammax_db.wu + AAMMAXDBVU: 0x070E1 << 15, // ammax_db.du + AAMMINDBWU: 0x070E2 << 15, // ammin_db.wu + AAMMINDBVU: 0x070E3 << 15, // ammin_db.du +} + +func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32 { + switch a { + case AMOVV: + switch fclass { + case C_REG: + switch tclass { + case C_FREG: + return 0x452a << 10 // movgr2fr.d + case C_FCCREG: + return 0x4536 << 10 // movgr2cf + case C_FCSRREG: + return 0x4530 << 10 // movgr2fcsr + } + case C_FREG: + switch tclass { + case C_REG: + return 0x452e << 10 // movfr2gr.d + case C_FCCREG: + return 0x4534 << 10 // movfr2cf + } + case C_FCCREG: + switch tclass { + case C_REG: + return 0x4537 << 10 // movcf2gr + case C_FREG: + return 0x4535 << 10 // movcf2fr + } + case C_FCSRREG: + switch tclass { + case C_REG: + return 0x4532 << 10 // movfcsr2gr + } + } + + case AMOVW: + switch fclass { + case C_REG: + switch tclass { + case C_FREG: + return 0x4529 << 10 // movgr2fr.w + } + case C_FREG: + switch tclass { + case C_REG: + return 0x452d << 10 // movfr2gr.s + } + } + } + + c.ctxt.Diag("bad class combination: %s %d,%d\n", a, fclass, tclass) + + return 0 +} + +func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16, offset_flag bool) (op_code, index_mask uint32) { + farng := (fReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK + tarng := (tReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK + fclass := c.rclass(fReg) + tclass := c.rclass(tReg) + + switch fclass | (tclass << 16) { + case C_REG | (C_ELEM << 16): + // vmov Rn, Vd.[index] + switch a { + case AVMOVQ: + switch tarng { + case ARNG_B: + return (0x01CBAE << 14), 0xf // vinsgr2vr.b + case ARNG_H: + return (0x03975E << 13), 0x7 // vinsgr2vr.h + case ARNG_W: + return (0x072EBE << 12), 0x3 // vinsgr2vr.w + case ARNG_V: + return (0x0E5D7E << 11), 0x1 // vinsgr2vr.d + } + case AXVMOVQ: + switch tarng { + case ARNG_W: + return (0x03B75E << 13), 0x7 // xvinsgr2vr.w + case ARNG_V: + return (0x076EBE << 12), 0x3 // xvinsgr2vr.d + } + } + + case C_ELEM | (C_REG << 16): + // vmov Vd.[index], Rn + switch a { + case AVMOVQ: + switch farng { + case ARNG_B: + return (0x01CBBE << 14), 0xf // vpickve2gr.b + case ARNG_H: + return (0x03977E << 13), 0x7 // vpickve2gr.h + case ARNG_W: + return (0x072EFE << 12), 0x3 // vpickve2gr.w + case ARNG_V: + return (0x0E5DFE << 11), 0x1 // vpickve2gr.d + case ARNG_BU: + return (0x01CBCE << 14), 0xf // vpickve2gr.bu + case ARNG_HU: + return (0x03979E << 13), 0x7 // vpickve2gr.hu + case ARNG_WU: + return (0x072F3E << 12), 0x3 // vpickve2gr.wu + case ARNG_VU: + return (0x0E5E7E << 11), 0x1 // vpickve2gr.du + } + case AXVMOVQ: + switch farng { + case ARNG_W: + return (0x03B77E << 13), 0x7 // xvpickve2gr.w + case ARNG_V: + return (0x076EFE << 12), 0x3 // xvpickve2gr.d + case ARNG_WU: + return (0x03B79E << 13), 0x7 // xvpickve2gr.wu + case ARNG_VU: + return (0x076F3E << 12), 0x3 // xvpickve2gr.du + } + } + + case C_REG | (C_ARNG << 16): + switch { + case offset_flag: + // vmov offset(vj), vd. + switch a { + case AVMOVQ: + switch tarng { + case ARNG_16B: + return (0xC2 << 22), 0x0 // vldrepl.b + case ARNG_8H: + return (0x182 << 21), 0x0 // vldrepl.h + case ARNG_4W: + return (0x302 << 20), 0x0 // vldrepl.w + case ARNG_2V: + return (0x602 << 19), 0x0 // vldrepl.d + } + case AXVMOVQ: + switch tarng { + case ARNG_32B: + return (0xCA << 22), 0x0 // xvldrepl.b + case ARNG_16H: + return (0x192 << 21), 0x0 // xvldrepl.h + case ARNG_8W: + return (0x322 << 20), 0x0 // xvldrepl.w + case ARNG_4V: + return (0x642 << 19), 0x0 // xvldrepl.d + } + } + default: + // vmov Rn, Vd. + switch a { + case AVMOVQ: + switch tarng { + case ARNG_16B: + return (0x1CA7C0 << 10), 0x0 // vreplgr2vr.b + case ARNG_8H: + return (0x1CA7C1 << 10), 0x0 // vreplgr2vr.h + case ARNG_4W: + return (0x1CA7C2 << 10), 0x0 // vreplgr2vr.w + case ARNG_2V: + return (0x1CA7C3 << 10), 0x0 // vreplgr2vr.d + } + case AXVMOVQ: + switch tarng { + case ARNG_32B: + return (0x1DA7C0 << 10), 0x0 // xvreplgr2vr.b + case ARNG_16H: + return (0x1DA7C1 << 10), 0x0 // xvreplgr2vr.h + case ARNG_8W: + return (0x1DA7C2 << 10), 0x0 // xvreplgr2vr.w + case ARNG_4V: + return (0x1DA7C3 << 10), 0x0 // xvreplgr2vr.d + } + } + } + + case C_XREG | (C_ARNG << 16): + // vmov xj, xd. + switch a { + case AVMOVQ: + return 0, 0 // unsupported op + case AXVMOVQ: + switch tarng { + case ARNG_32B: + return (0x1DC1C0 << 10), 0x0 // xvreplve0.b + case ARNG_16H: + return (0x1DC1E0 << 10), 0x0 // xvreplve0.h + case ARNG_8W: + return (0x1DC1F0 << 10), 0x0 // xvreplve0.w + case ARNG_4V: + return (0x1DC1F8 << 10), 0x0 // xvreplve0.d + case ARNG_2Q: + return (0x1DC1FC << 10), 0x0 // xvreplve0.q + } + } + + case C_XREG | (C_ELEM << 16): + // vmov xj, xd.[index] + switch a { + case AVMOVQ: + return 0, 0 // unsupported op + case AXVMOVQ: + switch tarng { + case ARNG_W: + return (0x03B7FE << 13), 0x7 // xvinsve0.w + case ARNG_V: + return (0x076FFE << 12), 0x3 // xvinsve0.d + } + } + + case C_ELEM | (C_XREG << 16): + // vmov xj.[index], xd + switch a { + case AVMOVQ: + return 0, 0 // unsupported op + case AXVMOVQ: + switch farng { + case ARNG_W: + return (0x03B81E << 13), 0x7 // xvpickve.w + case ARNG_V: + return (0x07703E << 12), 0x3 // xvpickve.d + } + } + + case C_ELEM | (C_ARNG << 16): + // vmov vj.[index], vd. + switch a { + case AVMOVQ: + switch int32(farng) | (int32(tarng) << 16) { + case int32(ARNG_B) | (int32(ARNG_16B) << 16): + return (0x01CBDE << 14), 0xf // vreplvei.b + case int32(ARNG_H) | (int32(ARNG_8H) << 16): + return (0x0397BE << 13), 0x7 // vreplvei.h + case int32(ARNG_W) | (int32(ARNG_4W) << 16): + return (0x072F7E << 12), 0x3 // vreplvei.w + case int32(ARNG_V) | (int32(ARNG_2V) << 16): + return (0x0E5EFE << 11), 0x1 // vreplvei.d + } + case AXVMOVQ: + return 0, 0 // unsupported op + } + } + + return 0, 0 +} diff --git a/src/cmd/internal/obj/loong64/list.go b/src/cmd/internal/obj/loong64/list.go index dba8aab0290b91..1a7926f8186a90 100644 --- a/src/cmd/internal/obj/loong64/list.go +++ b/src/cmd/internal/obj/loong64/list.go @@ -10,52 +10,73 @@ import ( ) func init() { - obj.RegisterRegister(obj.RBaseLOONG64, REG_LAST, rconv) + obj.RegisterRegister(obj.RBaseLOONG64, REG_LAST, RegName) obj.RegisterOpcode(obj.ABaseLoong64, Anames) } -func arrange(a int16) string { - switch a { +func arrange(valid int16) string { + var regPrefix string + var arngName string + + // bits 0-4 indicates register: Vn or Xn + // bits 5-9 indicates arrangement: + // bits 10 indicates SMID type: 0: LSX, 1: LASX + simdType := (valid >> EXT_SIMDTYPE_SHIFT) & EXT_SIMDTYPE_MASK + simdReg := (valid >> EXT_REG_SHIFT) & EXT_REG_MASK + arngType := (valid >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK + + switch simdType { + case LSX: + regPrefix = "V" + case LASX: + regPrefix = "X" + default: + regPrefix = "#" + } + + switch arngType { case ARNG_32B: - return "B32" + arngName = "B32" case ARNG_16H: - return "H16" + arngName = "H16" case ARNG_8W: - return "W8" + arngName = "W8" case ARNG_4V: - return "V4" + arngName = "V4" case ARNG_2Q: - return "Q2" + arngName = "Q2" case ARNG_16B: - return "B16" + arngName = "B16" case ARNG_8H: - return "H8" + arngName = "H8" case ARNG_4W: - return "W4" + arngName = "W4" case ARNG_2V: - return "V2" + arngName = "V2" case ARNG_B: - return "B" + arngName = "B" case ARNG_H: - return "H" + arngName = "H" case ARNG_W: - return "W" + arngName = "W" case ARNG_V: - return "V" + arngName = "V" case ARNG_BU: - return "BU" + arngName = "BU" case ARNG_HU: - return "HU" + arngName = "HU" case ARNG_WU: - return "WU" + arngName = "WU" case ARNG_VU: - return "VU" + arngName = "VU" default: - return "ARNG_???" + arngName = "ARNG_???" } + + return fmt.Sprintf("%s%d.%s", regPrefix, simdReg, arngName) } -func rconv(r int) string { +func RegName(r int) string { switch { case r == 0: return "NONE" @@ -74,28 +95,10 @@ func rconv(r int) string { return fmt.Sprintf("V%d", r-REG_V0) case REG_X0 <= r && r <= REG_X31: return fmt.Sprintf("X%d", r-REG_X0) - } - - // bits 0-4 indicates register: Vn or Xn - // bits 5-9 indicates arrangement: - // bits 10 indicates SMID type: 0: LSX, 1: LASX - simd_type := (int16(r) >> EXT_SIMDTYPE_SHIFT) & EXT_SIMDTYPE_MASK - reg_num := (int16(r) >> EXT_REG_SHIFT) & EXT_REG_MASK - arng_type := (int16(r) >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK - reg_prefix := "#" - switch simd_type { - case LSX: - reg_prefix = "V" - case LASX: - reg_prefix = "X" - } - - switch { case REG_ARNG <= r && r < REG_ELEM: - return fmt.Sprintf("%s%d.%s", reg_prefix, reg_num, arrange(arng_type)) - + return arrange(int16(r - REG_ARNG)) case REG_ELEM <= r && r < REG_ELEM_END: - return fmt.Sprintf("%s%d.%s", reg_prefix, reg_num, arrange(arng_type)) + return arrange(int16(r - REG_ELEM)) } return fmt.Sprintf("badreg(%d)", r-obj.RBaseLOONG64) diff --git a/src/cmd/internal/obj/loong64/obj.go b/src/cmd/internal/obj/loong64/obj.go index a97217d31657cf..fcf10d23071c56 100644 --- a/src/cmd/internal/obj/loong64/obj.go +++ b/src/cmd/internal/obj/loong64/obj.go @@ -64,12 +64,6 @@ func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { p.As = AADD } - case ASUBU: - if p.From.Type == obj.TYPE_CONST { - p.From.Offset = -p.From.Offset - p.As = AADDU - } - case ASUBV: if p.From.Type == obj.TYPE_CONST { p.From.Offset = -p.From.Offset @@ -365,9 +359,13 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { break } - retSym := p.To.Sym + retSym, retReg := p.To.Sym, p.To.Reg + if retReg == obj.REG_NONE { + retReg = REGLINK + } p.To.Name = obj.NAME_NONE // clear fields as we may modify p to other instruction p.To.Sym = nil + p.To.Reg = obj.REG_NONE if c.cursym.Func().Text.Mark&LEAF != 0 { if autosize == 0 { @@ -379,7 +377,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { p.To.Sym = retSym } else { p.To.Type = obj.TYPE_MEM - p.To.Reg = REGLINK + p.To.Reg = retReg p.To.Offset = 0 } p.Mark |= BRANCH @@ -403,7 +401,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { } else { q.To.Type = obj.TYPE_MEM q.To.Offset = 0 - q.To.Reg = REGLINK + q.To.Reg = retReg } q.Mark |= BRANCH q.Spadj = +autosize @@ -444,7 +442,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { } else { q1.To.Type = obj.TYPE_MEM q1.To.Offset = 0 - q1.To.Reg = REGLINK + q1.To.Reg = retReg } q1.Mark |= BRANCH q1.Spadj = +autosize @@ -453,7 +451,6 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { q.Link = q1 case AADD, - AADDU, AADDV, AADDVU: if p.To.Type == obj.TYPE_REG && p.To.Reg == REGSP && p.From.Type == obj.TYPE_CONST { diff --git a/src/cmd/internal/obj/mips/asm0.go b/src/cmd/internal/obj/mips/asm0.go index a55953e741432a..dd4f2717d8676e 100644 --- a/src/cmd/internal/obj/mips/asm0.go +++ b/src/cmd/internal/obj/mips/asm0.go @@ -1508,6 +1508,9 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { if r == obj.REG_NONE { r = o.param } + if p.From.Reg == REGTMP { + c.ctxt.Diag("cannot store REGTMP to large offset (REGTMP needed for address materialization): %v", p) + } v := c.regoff(&p.To) o1 = OP_IRR(c.opirr(ALUI), uint32((v+1<<15)>>16), REGZERO, REGTMP) o2 = OP_RRR(c.oprrr(add), r, REGTMP, REGTMP) diff --git a/src/cmd/internal/obj/mips/obj0.go b/src/cmd/internal/obj/mips/obj0.go index bbed88e9d6ad10..4ade03a77837c1 100644 --- a/src/cmd/internal/obj/mips/obj0.go +++ b/src/cmd/internal/obj/mips/obj0.go @@ -364,9 +364,13 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { break } - retSym := p.To.Sym + retSym, retReg := p.To.Sym, p.To.Reg + if retReg == obj.REG_NONE { + retReg = REGLINK + } p.To.Name = obj.NAME_NONE // clear fields as we may modify p to other instruction p.To.Sym = nil + p.To.Reg = obj.REG_NONE if c.cursym.Func().Text.Mark&LEAF != 0 { if autosize == 0 { @@ -378,7 +382,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { p.To.Sym = retSym } else { p.To.Type = obj.TYPE_MEM - p.To.Reg = REGLINK + p.To.Reg = retReg p.To.Offset = 0 } p.Mark |= BRANCH @@ -401,7 +405,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { q.To.Sym = retSym } else { q.To.Type = obj.TYPE_MEM - q.To.Reg = REGLINK + q.To.Reg = retReg q.To.Offset = 0 } q.Mark |= BRANCH @@ -443,7 +447,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { } else { q1.To.Type = obj.TYPE_MEM q1.To.Offset = 0 - q1.To.Reg = REGLINK + q1.To.Reg = retReg } q1.Mark |= BRANCH q1.Spadj = +autosize diff --git a/src/cmd/internal/obj/objfile.go b/src/cmd/internal/obj/objfile.go index 4401f1bb74e0a9..6bd5bca04462b4 100644 --- a/src/cmd/internal/obj/objfile.go +++ b/src/cmd/internal/obj/objfile.go @@ -14,6 +14,7 @@ import ( "cmd/internal/objabi" "cmd/internal/sys" "cmp" + "encoding/base64" "encoding/binary" "fmt" "internal/abi" @@ -276,6 +277,22 @@ func (w *writer) writeFile(ctxt *Link, file *FileInfo) { } } +var inlHashLen = base64.StdEncoding.EncodedLen(8) + +// TrimInlineHash strips the content hash of inlined call stacks from a symbol name. +func TrimInlineHash(name string) string { + // The inline hash is in the form of #NNNN#, where NNNN is + // the base64 encoding of a 8-byte hash value. + a, b, ok := strings.Cut(name, "#") + if !ok { + return name + } + if len(b) < inlHashLen+1 || b[inlHashLen] != '#' { + return name + } + return a + b[inlHashLen+1:] +} + func (w *writer) StringTable() { w.AddString("") for _, p := range w.ctxt.Imports { @@ -300,7 +317,7 @@ func (w *writer) StringTable() { if strings.HasPrefix(s.Name, `"".`) { w.ctxt.Diag("unqualified symbol name: %v", s.Name) } - w.AddString(s.Name) + w.AddString(TrimInlineHash(s.Name)) }) // All filenames are in the postable. @@ -309,9 +326,9 @@ func (w *writer) StringTable() { } } -// cutoff is the maximum data section size permitted by the linker +// MaxSymSize is the maximum data section size permitted by the linker // (see issue #9862). -const cutoff = int64(2e9) // 2 GB (or so; looks better in errors than 2^31) +const MaxSymSize = int64(2e9) // 2 GB (or so; looks better in errors than 2^31) func (w *writer) Sym(s *LSym) { name := s.Name @@ -354,12 +371,13 @@ func (w *writer) Sym(s *LSym) { if s.IsPkgInit() { flag2 |= goobj.SymFlagPkgInit } - if s.IsLinkname() || (w.ctxt.IsAsm && name != "") || name == "main.main" { - // Assembly reference is treated the same as linkname, - // but not for unnamed (aux) symbols. + if s.IsLinkname() || name == "main.main" { // The runtime linknames main.main. flag2 |= goobj.SymFlagLinkname } + if s.IsLinknameStd() { + flag2 |= goobj.SymFlagLinknameStd + } if s.ABIWrapper() { flag2 |= goobj.SymFlagABIWrapper } @@ -369,49 +387,17 @@ func (w *writer) Sym(s *LSym) { if strings.HasPrefix(name, "gofile..") { name = filepath.ToSlash(name) } - var align uint32 - if fn := s.Func(); fn != nil { - align = uint32(fn.Align) - } - if s.ContentAddressable() && s.Size != 0 { - // We generally assume data symbols are naturally aligned - // (e.g. integer constants), except for strings and a few - // compiler-emitted funcdata. If we dedup a string symbol and - // a non-string symbol with the same content, we should keep - // the largest alignment. - // TODO: maybe the compiler could set the alignment for all - // data symbols more carefully. - switch { - case strings.HasPrefix(s.Name, "go:string."), - strings.HasPrefix(name, "type:.namedata."), - strings.HasPrefix(name, "type:.importpath."), - strings.HasSuffix(name, ".opendefer"), - strings.HasSuffix(name, ".arginfo0"), - strings.HasSuffix(name, ".arginfo1"), - strings.HasSuffix(name, ".argliveinfo"): - // These are just bytes, or varints. - align = 1 - case strings.HasPrefix(name, "gclocals·"): - // It has 32-bit fields. - align = 4 - default: - switch { - case w.ctxt.Arch.PtrSize == 8 && s.Size%8 == 0: - align = 8 - case s.Size%4 == 0: - align = 4 - case s.Size%2 == 0: - align = 2 - default: - align = 1 - } - } + align := uint32(s.Align) + if s.ContentAddressable() && s.Size != 0 && align == 0 && s.Type != objabi.STEXT && s.Type != objabi.STEXTFIPS { + // The linker applies a default alignment for text symbols, so they are okay. + // TODO: Check that alignment is set for all symbols. + w.ctxt.Diag("%s: is content-addressable but alignment is not set (size is %d)", s.Name, s.Size) } - if s.Size > cutoff { - w.ctxt.Diag("%s: symbol too large (%d bytes > %d bytes)", s.Name, s.Size, cutoff) + if s.Size > MaxSymSize { + w.ctxt.Diag("%s: symbol too large (%d bytes > %d bytes)", s.Name, s.Size, MaxSymSize) } o := &w.tmpSym - o.SetName(name, w.Writer) + o.SetName(TrimInlineHash(name), w.Writer) o.SetABI(abi) o.SetType(uint8(s.Type)) o.SetFlag(flag) @@ -446,10 +432,16 @@ func (w *writer) Hash(s *LSym) { // Some of these conditions are duplicated in cmd/link/internal/ld.(*Link).symtab. // TODO: instead of duplicating them, have the compiler decide where symbols go. func contentHashSection(s *LSym) byte { - name := s.Name + if s.Type == objabi.STEXT { + return 't' + } + if s.Type == objabi.STEXTFIPS { + return 'f' + } if s.IsPcdata() { return 'P' } + name := s.Name if strings.HasPrefix(name, "gcargs.") || strings.HasPrefix(name, "gclocals.") || strings.HasPrefix(name, "gclocals·") || @@ -510,6 +502,14 @@ func (w *writer) contentHash(s *LSym) goobj.HashType { tmp[8] = contentHashSection(s) h.Write(tmp[:9]) + if s.Type == objabi.STEXT || s.Type == objabi.STEXTFIPS { + // We don't want to combine irrelevant functions. + // Include the name to distinguish, without the temporary + // inline hash, so different inlined copies do get a chance + // to be combined. + io.WriteString(h, TrimInlineHash(s.Name)) + } + // The compiler trims trailing zeros _sometimes_. We just do // it always. h.Write(bytes.TrimRight(s.P, "\x00")) @@ -522,9 +522,14 @@ func (w *writer) contentHash(s *LSym) goobj.HashType { h.Write(tmp[:]) rs := r.Sym if rs == nil { - fmt.Printf("symbol: %s\n", s) - fmt.Printf("relocation: %#v\n", r) - panic("nil symbol target in relocation") + // marker relocation + io.WriteString(h, "nil symbol") + continue + } + if rs == s { + io.WriteString(h, "self symbol") + continue + // TODO: mutual recursion? } switch rs.PkgIdx { case goobj.PkgIdxHashed64: @@ -895,10 +900,10 @@ func (ctxt *Link) writeSymDebugNamed(s *LSym, name string) { if s.Func() != nil && s.Func().FuncFlag&abi.FuncFlagAsm != 0 { fmt.Fprintf(ctxt.Bso, "asm ") } - fmt.Fprintf(ctxt.Bso, "size=%d", s.Size) + fmt.Fprintf(ctxt.Bso, "size=%d align=%#x", s.Size, s.Align) if s.Type.IsText() { fn := s.Func() - fmt.Fprintf(ctxt.Bso, " args=%#x locals=%#x funcid=%#x align=%#x", uint64(fn.Args), uint64(fn.Locals), uint64(fn.FuncID), uint64(fn.Align)) + fmt.Fprintf(ctxt.Bso, " args=%#x locals=%#x funcid=%#x", uint64(fn.Args), uint64(fn.Locals), uint64(fn.FuncID)) if s.Leaf() { fmt.Fprintf(ctxt.Bso, " leaf") } diff --git a/src/cmd/internal/obj/pcln.go b/src/cmd/internal/obj/pcln.go index 67a078091c54b6..852c7069fdc92c 100644 --- a/src/cmd/internal/obj/pcln.go +++ b/src/cmd/internal/obj/pcln.go @@ -22,12 +22,13 @@ import ( // // where func is the function, val is the current value, p is the instruction being // considered, and arg can be used to further parameterize valfunc. -func funcpctab(ctxt *Link, func_ *LSym, desc string, valfunc func(*Link, *LSym, int32, *Prog, int32, interface{}) int32, arg interface{}) *LSym { +func funcpctab(ctxt *Link, func_ *LSym, desc string, valfunc func(*Link, *LSym, int32, *Prog, int32, any) int32, arg any) *LSym { dbg := desc == ctxt.Debugpcln dst := []byte{} sym := &LSym{ Type: objabi.SRODATA, Attribute: AttrContentAddressable | AttrPcdata, + Align: 1, } if dbg { @@ -138,7 +139,7 @@ func funcpctab(ctxt *Link, func_ *LSym, desc string, valfunc func(*Link, *LSym, // or the line number (arg == 1) to use at p. // Because p.Pos applies to p, phase == 0 (before p) // takes care of the update. -func pctofileline(ctxt *Link, sym *LSym, oldval int32, p *Prog, phase int32, arg interface{}) int32 { +func pctofileline(ctxt *Link, sym *LSym, oldval int32, p *Prog, phase int32, arg any) int32 { if p.As == ATEXT || p.As == ANOP || p.Pos.Line() == 0 || phase == 1 { return oldval } @@ -198,7 +199,7 @@ func (s *pcinlineState) setParentPC(ctxt *Link, globalIndex int, pc int32) { // pctoinline computes the index into the local inlining tree to use at p. // If p is not the result of inlining, pctoinline returns -1. Because p.Pos // applies to p, phase == 0 (before p) takes care of the update. -func (s *pcinlineState) pctoinline(ctxt *Link, sym *LSym, oldval int32, p *Prog, phase int32, arg interface{}) int32 { +func (s *pcinlineState) pctoinline(ctxt *Link, sym *LSym, oldval int32, p *Prog, phase int32, arg any) int32 { if phase == 1 { return oldval } @@ -224,7 +225,7 @@ func (s *pcinlineState) pctoinline(ctxt *Link, sym *LSym, oldval int32, p *Prog, // It is oldval plus any adjustment made by p itself. // The adjustment by p takes effect only after p, so we // apply the change during phase == 1. -func pctospadj(ctxt *Link, sym *LSym, oldval int32, p *Prog, phase int32, arg interface{}) int32 { +func pctospadj(ctxt *Link, sym *LSym, oldval int32, p *Prog, phase int32, arg any) int32 { if oldval == -1 { // starting oldval = 0 } @@ -245,7 +246,7 @@ func pctospadj(ctxt *Link, sym *LSym, oldval int32, p *Prog, phase int32, arg in // non-PCDATA instructions. // Since PCDATA instructions have no width in the final code, // it does not matter which phase we use for the update. -func pctopcdata(ctxt *Link, sym *LSym, oldval int32, p *Prog, phase int32, arg interface{}) int32 { +func pctopcdata(ctxt *Link, sym *LSym, oldval int32, p *Prog, phase int32, arg any) int32 { if phase == 0 || p.As != APCDATA || p.From.Offset != int64(arg.(uint32)) { return oldval } @@ -335,9 +336,10 @@ func linkpcln(ctxt *Link, cursym *LSym) { pcln.Pcdata[i] = &LSym{ Type: objabi.SRODATA, Attribute: AttrContentAddressable | AttrPcdata, + Align: 1, } } else { - pcln.Pcdata[i] = funcpctab(ctxt, cursym, "pctopcdata", pctopcdata, interface{}(uint32(i))) + pcln.Pcdata[i] = funcpctab(ctxt, cursym, "pctopcdata", pctopcdata, any(uint32(i))) } } diff --git a/src/cmd/internal/obj/plist.go b/src/cmd/internal/obj/plist.go index 69914b1c1f36d5..f0fe68eb4349ca 100644 --- a/src/cmd/internal/obj/plist.go +++ b/src/cmd/internal/obj/plist.go @@ -183,7 +183,11 @@ func (ctxt *Link) InitTextSym(s *LSym, flag int, start src.XPos) { return } if s.Func() != nil { - ctxt.Diag("%s: symbol %s redeclared\n\t%s: other declaration of symbol %s", ctxt.PosTable.Pos(start), s.Name, ctxt.PosTable.Pos(s.Func().Text.Pos), s.Name) + otherPos := src.NoPos + if s.Func().Text != nil { + otherPos = ctxt.PosTable.Pos(s.Func().Text.Pos) + } + ctxt.Diag("%s: symbol %s redeclared\n\t%s: other declaration of symbol %s", ctxt.PosTable.Pos(start), s.Name, otherPos, s.Name) return } s.NewFuncInfo() diff --git a/src/cmd/internal/obj/ppc64/asm9.go b/src/cmd/internal/obj/ppc64/asm9.go index a39c206c22da9e..06ad72eed83584 100644 --- a/src/cmd/internal/obj/ppc64/asm9.go +++ b/src/cmd/internal/obj/ppc64/asm9.go @@ -595,8 +595,8 @@ func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int { // requested then the function alignment must also be promoted. // The function alignment is not promoted on AIX at this time. // TODO: Investigate AIX function alignment. - if ctxt.Headtype != objabi.Haix && cursym.Func().Align < int32(a) { - cursym.Func().Align = int32(a) + if ctxt.Headtype != objabi.Haix && cursym.Align < int16(a) { + cursym.Align = int16(a) } if pc&(a-1) != 0 { return int(a - (pc & (a - 1))) @@ -796,7 +796,7 @@ func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { } c.cursym.Size = pc - c.cursym.Func().Align = falign + c.cursym.Align = int16(falign) c.cursym.Grow(c.cursym.Size) // lay out the code, emitting code and data relocations. diff --git a/src/cmd/internal/obj/ppc64/asm_test.go b/src/cmd/internal/obj/ppc64/asm_test.go index ab7af2205e64c3..8b6d22e69243be 100644 --- a/src/cmd/internal/obj/ppc64/asm_test.go +++ b/src/cmd/internal/obj/ppc64/asm_test.go @@ -13,9 +13,12 @@ import ( "os" "path/filepath" "regexp" + "strconv" "strings" "testing" + "internal/abi" + "cmd/internal/obj" "cmd/internal/objabi" ) @@ -439,7 +442,7 @@ func TestAddrClassifier(t *testing.T) { } tsts := [...]struct { arg obj.Addr - output interface{} + output any }{ // Supported register type args {obj.Addr{Type: obj.TYPE_REG, Reg: REG_R1}, C_REG}, @@ -556,3 +559,109 @@ func TestOptabReinit(t *testing.T) { t.Errorf("rerunning buildop changes optab size from %d to %d", optabLen, reinitOptabLen) } } + +// A tail call is lowered to "MOVD Rx, CTR; BR (CTR)". runtime.asyncPreempt +// does not preserve CTR, and its resume sequence leaves CTR holding the resume +// PC, so a goroutine preempted anywhere between the load of CTR and the branch +// would resume by branching to the wrong place (for a preemption at the branch +// itself, to that very instruction, spinning there forever). Check that the +// whole sequence is marked as an unsafe point. See go.dev/issue/78576. +const tailCallSrc = ` +// 4 = NOSPLIT, 512 = NOFRAME (see textflag.h). +TEXT ·leafNoFrame(SB),4|512,$0-0 + MOVD $0, R3 + RET (R3) + +TEXT ·leafFrame(SB),4,$8-0 + MOVD $0, R3 + RET (R3) + +TEXT ·nonLeaf(SB),4,$8-0 + CALL ·leafNoFrame(SB) + MOVD $0, R3 + RET (R3) + +// A tail call that is not the last instruction in the function, +// to check that the unsafe point ends at the branch and does not +// swallow the rest of the function. +TEXT ·leafNoFrameCond(SB),4|512,$0-0 + CMP R3, $0 + BEQ skip + RET (R3) +skip: + MOVD $0, R3 + RET +` + +func TestTailCallUnsafePoint(t *testing.T) { + testenv.MustHaveGoBuild(t) + + dir := t.TempDir() + tmpfile := filepath.Join(dir, "x.s") + if err := os.WriteFile(tmpfile, []byte(tailCallSrc), 0644); err != nil { + t.Fatalf("can't write output: %v\n", err) + } + + for _, goarch := range []string{"ppc64", "ppc64le"} { + cmd := testenv.Command(t, testenv.GoToolPath(t), "tool", "asm", "-o", filepath.Join(dir, "x.o"), "-S", tmpfile) + cmd.Env = append(os.Environ(), "GOARCH="+goarch, "GOOS=linux") + out, err := cmd.CombinedOutput() + if err != nil { + t.Fatalf("GOARCH=%s: assembly failed: %v, output:\n%s", goarch, err, out) + } + + // Walk the -S output tracking the current PCDATA_UnsafePoint value. + // Every branch through CTR must be an unsafe point, and the unsafe + // point must end at the branch: the next instruction, if any, must be + // a safe point again, and so must the end of the function. + branches := 0 + sym := "" + unsafePoint := int64(abi.UnsafePointSafe) + atBranch := false + endFunc := func() { + if sym != "" && unsafePoint != abi.UnsafePointSafe { + t.Errorf("GOARCH=%s: %s: unsafe point %d at end of function, want %d", + goarch, sym, unsafePoint, abi.UnsafePointSafe) + } + } + for _, line := range strings.Split(string(out), "\n") { + f := strings.Fields(line) + // Lines look like: + // sym STEXT ... + // 0x0014 00020 (x.s:14)PCDATA$0,$-2 + // Other lines (hex dumps, relocations) have no (file:line) field. + switch { + case len(f) >= 2 && f[1] == "STEXT": + endFunc() + sym, unsafePoint, atBranch = f[0], abi.UnsafePointSafe, false + case len(f) < 4 || !strings.HasPrefix(f[2], "("): + // Not an instruction. + case len(f) >= 6 && f[3] == "PCDATA" && f[4] == fmt.Sprintf("$%d,", abi.PCDATA_UnsafePoint): + v, err := strconv.ParseInt(strings.TrimPrefix(f[5], "$"), 10, 64) + if err != nil { + t.Fatalf("GOARCH=%s: can't parse %q: %v", goarch, line, err) + } + unsafePoint = v + case f[3] == "PCDATA" || f[3] == "FUNCDATA" || f[3] == "TEXT": + // Not a real instruction. + case len(f) >= 5 && f[3] == "JMP" && f[4] == "CTR": + branches++ + atBranch = true + if unsafePoint != abi.UnsafePointUnsafe { + t.Errorf("GOARCH=%s: %s\n\tbranch through CTR has unsafe point %d, want %d", + goarch, strings.TrimSpace(line), unsafePoint, abi.UnsafePointUnsafe) + } + case atBranch: + atBranch = false + if unsafePoint != abi.UnsafePointSafe { + t.Errorf("GOARCH=%s: %s\n\tinstruction after branch through CTR has unsafe point %d, want %d", + goarch, strings.TrimSpace(line), unsafePoint, abi.UnsafePointSafe) + } + } + } + endFunc() + if want := strings.Count(tailCallSrc, "RET\t(R3)"); branches != want { + t.Errorf("GOARCH=%s: found %d branches through CTR, want %d; output:\n%s", goarch, branches, want, out) + } + } +} diff --git a/src/cmd/internal/obj/ppc64/obj9.go b/src/cmd/internal/obj/ppc64/obj9.go index bae2965639721f..fc5d05b4fe0cdb 100644 --- a/src/cmd/internal/obj/ppc64/obj9.go +++ b/src/cmd/internal/obj/ppc64/obj9.go @@ -965,7 +965,33 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { break } - retTarget := p.To.Sym + retTarget, retReg := p.To.Sym, p.To.Reg + finish := func(last *obj.Prog) {} + if retReg == obj.REG_NONE { + retReg = REG_LR + } else { + // Move target address into REG_CTR. + // (Indirect branches can only go to REG_LR or REG_CTR.) + x := newprog() + *x = *p + p.As = AMOVD + p.From.Type = obj.TYPE_REG + p.From.Reg = retReg + p.To.Type = obj.TYPE_REG + p.To.Reg = REG_CTR + retReg = REG_CTR + p.Link = x + // Everything from here through the BR (CTR) must be an + // unsafe point. runtime.asyncPreempt does not preserve CTR, + // and its resume sequence leaves CTR holding the resume PC, + // so a goroutine preempted at the BR (CTR) would resume by + // branching to that very instruction and spin there forever. + c.ctxt.StartUnsafePoint(p, c.newprog) + finish = func(last *obj.Prog) { + c.ctxt.EndUnsafePoint(last, c.newprog, -1) + } + p = x + } if c.cursym.Func().Text.Mark&LEAF != 0 { if autosize == 0 { @@ -973,12 +999,13 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { p.From = obj.Addr{} if retTarget == nil { p.To.Type = obj.TYPE_REG - p.To.Reg = REG_LR + p.To.Reg = retReg } else { p.To.Type = obj.TYPE_BRANCH p.To.Sym = retTarget } p.Mark |= BRANCH + finish(p) break } @@ -994,7 +1021,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { q.Pos = p.Pos if retTarget == nil { q.To.Type = obj.TYPE_REG - q.To.Reg = REG_LR + q.To.Reg = retReg } else { q.To.Type = obj.TYPE_BRANCH q.To.Sym = retTarget @@ -1004,6 +1031,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { q.Link = p.Link p.Link = q + finish(q) break } @@ -1063,7 +1091,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { q1.Pos = p.Pos if retTarget == nil { q1.To.Type = obj.TYPE_REG - q1.To.Reg = REG_LR + q1.To.Reg = retReg } else { q1.To.Type = obj.TYPE_BRANCH q1.To.Sym = retTarget @@ -1073,6 +1101,8 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { q1.Link = q.Link prev.Link = q1 + finish(q1) + case AADD: if p.To.Type == obj.TYPE_REG && p.To.Reg == REGSP && p.From.Type == obj.TYPE_CONST { p.Spadj = int32(-p.From.Offset) diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go index 6c48e2f7de4799..761efce67aa8bd 100644 --- a/src/cmd/internal/obj/riscv/anames.go +++ b/src/cmd/internal/obj/riscv/anames.go @@ -263,6 +263,9 @@ var Anames = []string{ "RORW", "ORCB", "REV8", + "CLMUL", + "CLMULH", + "CLMULR", "BCLR", "BCLRI", "BEXT", @@ -898,6 +901,26 @@ var Anames = []string{ "VMV2RV", "VMV4RV", "VMV8RV", + "VANDNVV", + "VANDNVX", + "VBREVV", + "VBREV8V", + "VREV8V", + "VCLZV", + "VCTZV", + "VCPOPV", + "VROLVV", + "VROLVX", + "VRORVV", + "VRORVX", + "VRORVI", + "VWSLLVV", + "VWSLLVX", + "VWSLLVI", + "VCLMULVV", + "VCLMULVX", + "VCLMULHVV", + "VCLMULHVX", "ECALL", "SCALL", "EBREAK", @@ -918,6 +941,13 @@ var Anames = []string{ "BLEZ", "BLTZ", "BNEZ", + "CSRC", + "CSRCI", + "CSRR", + "CSRS", + "CSRSI", + "CSRW", + "CSRWI", "FABSD", "FABSS", "FNED", @@ -936,6 +966,7 @@ var Anames = []string{ "NEG", "NEGW", "NOT", + "PAUSE", "RDCYCLE", "RDINSTRET", "RDTIME", diff --git a/src/cmd/internal/obj/riscv/asm_test.go b/src/cmd/internal/obj/riscv/asm_test.go index f40e57fa64885e..f143e70103d4ac 100644 --- a/src/cmd/internal/obj/riscv/asm_test.go +++ b/src/cmd/internal/obj/riscv/asm_test.go @@ -11,13 +11,14 @@ import ( "os" "os/exec" "path/filepath" + "regexp" "runtime" - "strings" "testing" ) // TestLargeBranch generates a large function with a very far conditional -// branch, in order to ensure that it assembles successfully. +// branch, in order to ensure that it assembles correctly. This requires +// inverting the branch and using a jump to reach the target. func TestLargeBranch(t *testing.T) { if testing.Short() { t.Skip("Skipping test in short mode") @@ -26,6 +27,23 @@ func TestLargeBranch(t *testing.T) { dir := t.TempDir() + if err := os.WriteFile(filepath.Join(dir, "go.mod"), []byte("module largecall"), 0644); err != nil { + t.Fatalf("Failed to write file: %v\n", err) + } + main := `package main + +import "fmt" + +func main() { + fmt.Print(x()) +} + +func x() uint64 +` + if err := os.WriteFile(filepath.Join(dir, "x.go"), []byte(main), 0644); err != nil { + t.Fatalf("failed to write main: %v\n", err) + } + // Generate a very large function. buf := bytes.NewBuffer(make([]byte, 0, 7000000)) genLargeBranch(buf) @@ -36,27 +54,62 @@ func TestLargeBranch(t *testing.T) { } // Assemble generated file. - cmd := testenv.Command(t, testenv.GoToolPath(t), "tool", "asm", "-o", filepath.Join(dir, "x.o"), tmpfile) + cmd := exec.Command(testenv.GoToolPath(t), "tool", "asm", "-o", filepath.Join(dir, "x.o"), "-S", tmpfile) cmd.Env = append(os.Environ(), "GOARCH=riscv64", "GOOS=linux") out, err := cmd.CombinedOutput() + if err != nil { + t.Errorf("Failed to assemble: %v\n%s", err, out) + } + + // The expected instruction sequence for the long branch is: + // BNEZ + // AUIPC $..., X31 + // JALR X0, $..., X31 + want := regexp.MustCompile(`\sBNEZ\s.*\s.*\n.*\n.*AUIPC\s\$\d+, X31.*\n.*JALR\sX0, \$\d+, ?X31`) + if !want.Match(out) { + t.Error("Missing assembly instructions") + } + + // Build generated files. + cmd = testenv.Command(t, testenv.GoToolPath(t), "build", "-o", "x.exe", "-ldflags=-linkmode=internal") + cmd.Dir = dir + cmd.Env = append(os.Environ(), "GOARCH=riscv64", "GOOS=linux") + out, err = cmd.CombinedOutput() if err != nil { t.Errorf("Build failed: %v, output: %s", err, out) } + + if runtime.GOARCH == "riscv64" && runtime.GOOS == "linux" { + cmd = testenv.Command(t, filepath.Join(dir, "x.exe")) + out, err = cmd.CombinedOutput() + if err != nil { + t.Errorf("Failed to run test binary: %v", err) + } + if string(out) != "1" { + t.Errorf(`Got test output %q, want "2"`, string(out)) + } + } } func genLargeBranch(buf *bytes.Buffer) { - fmt.Fprintln(buf, "TEXT f(SB),0,$0-0") - fmt.Fprintln(buf, "BEQ X0, X0, label") - for i := 0; i < 1<<19; i++ { - fmt.Fprintln(buf, "ADD $0, X0, X0") + fmt.Fprintln(buf, "TEXT ·x(SB),0,$0-8") + fmt.Fprintln(buf, "MOV X0, X10") + fmt.Fprintln(buf, "BEQZ X10, label") + for i := 0; i < 1<<18; i++ { + // Use a non-compressable instruction. + fmt.Fprintln(buf, "ADD $0, X5, X0") } + fmt.Fprintln(buf, "ADD $1, X10, X10") fmt.Fprintln(buf, "label:") - fmt.Fprintln(buf, "ADD $0, X0, X0") + fmt.Fprintln(buf, "ADD $1, X10, X10") + fmt.Fprintln(buf, "MOV X10, r+0(FP)") + fmt.Fprintln(buf, "RET") } // TestLargeCall generates a large function (>1MB of text) with a call to // a following function, in order to ensure that it assembles and links -// correctly. +// correctly. This requires the use of AUIPC+JALR instruction sequences, +// which are fixed up by the linker. func TestLargeCall(t *testing.T) { if testing.Short() { t.Skip("Skipping test in short mode") @@ -69,12 +122,15 @@ func TestLargeCall(t *testing.T) { t.Fatalf("Failed to write file: %v\n", err) } main := `package main + +import "fmt" + func main() { - x() + fmt.Print(x()) } -func x() -func y() +func x() uint64 +func y() uint64 ` if err := os.WriteFile(filepath.Join(dir, "x.go"), []byte(main), 0644); err != nil { t.Fatalf("failed to write main: %v\n", err) @@ -84,51 +140,94 @@ func y() buf := bytes.NewBuffer(make([]byte, 0, 7000000)) genLargeCall(buf) - if err := os.WriteFile(filepath.Join(dir, "x.s"), buf.Bytes(), 0644); err != nil { + tmpfile := filepath.Join(dir, "x.s") + if err := os.WriteFile(tmpfile, buf.Bytes(), 0644); err != nil { t.Fatalf("Failed to write file: %v\n", err) } + // Assemble generated file. + cmd := exec.Command(testenv.GoToolPath(t), "tool", "asm", "-o", filepath.Join(dir, "x.o"), "-S", tmpfile) + cmd.Env = append(os.Environ(), "GOARCH=riscv64", "GOOS=linux") + out, err := cmd.CombinedOutput() + if err != nil { + t.Errorf("Failed to assemble: %v\n%s", err, out) + } + + // The expected instruction sequence for the long call is: + // AUIPC $0, $0, X31 + // JALR X.., X31 + want := regexp.MustCompile(`\sAUIPC\s\$0, \$0, X31.*\n.*\sJALR\sX.*, X31`) + if !want.Match(out) { + t.Error("Missing assembly instructions") + } + // Build generated files. - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-linkmode=internal") + cmd = testenv.Command(t, testenv.GoToolPath(t), "build", "-o", "x.exe", "-ldflags=-linkmode=internal") cmd.Dir = dir cmd.Env = append(os.Environ(), "GOARCH=riscv64", "GOOS=linux") - out, err := cmd.CombinedOutput() + out, err = cmd.CombinedOutput() if err != nil { t.Errorf("Build failed: %v, output: %s", err, out) } + if runtime.GOARCH == "riscv64" && runtime.GOOS == "linux" { + cmd = testenv.Command(t, filepath.Join(dir, "x.exe")) + out, err = cmd.CombinedOutput() + if err != nil { + t.Errorf("Failed to run test binary: %v", err) + } + if string(out) != "2" { + t.Errorf(`Got test output %q, want "2"`, string(out)) + } + } + if runtime.GOARCH == "riscv64" && testenv.HasCGO() { - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-linkmode=external") + cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", "x.exe", "-ldflags=-linkmode=external") cmd.Dir = dir cmd.Env = append(os.Environ(), "GOARCH=riscv64", "GOOS=linux") out, err := cmd.CombinedOutput() if err != nil { t.Errorf("Build failed: %v, output: %s", err, out) } + + if runtime.GOARCH == "riscv64" && runtime.GOOS == "linux" { + cmd = testenv.Command(t, filepath.Join(dir, "x.exe")) + out, err = cmd.CombinedOutput() + if err != nil { + t.Errorf("Failed to run test binary: %v", err) + } + if string(out) != "2" { + t.Errorf(`Got test output %q, want "2"`, string(out)) + } + } } } func genLargeCall(buf *bytes.Buffer) { - fmt.Fprintln(buf, "TEXT ·x(SB),0,$0-0") + fmt.Fprintln(buf, "TEXT ·x(SB),0,$0-8") + fmt.Fprintln(buf, "MOV X0, X10") fmt.Fprintln(buf, "CALL ·y(SB)") - for i := 0; i < 1<<19; i++ { - fmt.Fprintln(buf, "ADD $0, X0, X0") + fmt.Fprintln(buf, "ADD $1, X10, X10") + fmt.Fprintln(buf, "MOV X10, r+0(FP)") + fmt.Fprintln(buf, "RET") + for i := 0; i < 1<<18; i++ { + // Use a non-compressable instruction. + fmt.Fprintln(buf, "ADD $0, X5, X0") } + fmt.Fprintln(buf, "ADD $1, X10, X10") fmt.Fprintln(buf, "RET") fmt.Fprintln(buf, "TEXT ·y(SB),0,$0-0") - fmt.Fprintln(buf, "ADD $0, X0, X0") + fmt.Fprintln(buf, "ADD $1, X10, X10") fmt.Fprintln(buf, "RET") } // TestLargeJump generates a large jump (>1MB of text) with a JMP to the // end of the function, in order to ensure that it assembles correctly. +// This requires the use of AUIPC+JALR instruction sequences. func TestLargeJump(t *testing.T) { if testing.Short() { t.Skip("Skipping test in short mode") } - if runtime.GOARCH != "riscv64" { - t.Skip("Require riscv64 to run") - } testenv.MustHaveGoBuild(t) dir := t.TempDir() @@ -154,22 +253,46 @@ func x() uint64 buf := bytes.NewBuffer(make([]byte, 0, 7000000)) genLargeJump(buf) - if err := os.WriteFile(filepath.Join(dir, "x.s"), buf.Bytes(), 0644); err != nil { + tmpfile := filepath.Join(dir, "x.s") + if err := os.WriteFile(tmpfile, buf.Bytes(), 0644); err != nil { t.Fatalf("Failed to write file: %v\n", err) } + // Assemble generated file. + cmd := exec.Command(testenv.GoToolPath(t), "tool", "asm", "-o", filepath.Join(dir, "x.o"), "-S", tmpfile) + cmd.Env = append(os.Environ(), "GOARCH=riscv64", "GOOS=linux") + out, err := cmd.CombinedOutput() + if err != nil { + t.Errorf("Failed to assemble: %v\n%s", err, out) + } + + // The expected instruction sequence for the long call is: + // AUIPC $..., X31 + // JALR X0, $.., X31 + want := regexp.MustCompile(`\sAUIPC\s\$\d+, X31.*\n.*\sJALR\sX0, \$\d+, ?X31`) + if !want.Match(out) { + t.Error("Missing assembly instructions") + t.Errorf("%s", out) + } + // Build generated files. - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", "x.exe") + cmd = testenv.Command(t, testenv.GoToolPath(t), "build", "-o", "x.exe") cmd.Dir = dir - out, err := cmd.CombinedOutput() + cmd.Env = append(os.Environ(), "GOARCH=riscv64", "GOOS=linux") + out, err = cmd.CombinedOutput() if err != nil { t.Errorf("Build failed: %v, output: %s", err, out) } - cmd = testenv.Command(t, filepath.Join(dir, "x.exe")) - out, err = cmd.CombinedOutput() - if string(out) != "1" { - t.Errorf(`Got test output %q, want "1"`, string(out)) + if runtime.GOARCH == "riscv64" && runtime.GOOS == "linux" { + cmd = testenv.Command(t, filepath.Join(dir, "x.exe")) + out, err = cmd.CombinedOutput() + if err != nil { + t.Errorf("Failed to run test binary: %v", err) + } + if string(out) != "1" { + t.Errorf(`Got test output %q, want "1"`, string(out)) + } } } @@ -178,8 +301,10 @@ func genLargeJump(buf *bytes.Buffer) { fmt.Fprintln(buf, "MOV X0, X10") fmt.Fprintln(buf, "JMP end") for i := 0; i < 1<<18; i++ { - fmt.Fprintln(buf, "ADD $1, X10, X10") + // Use a non-compressable instruction. + fmt.Fprintln(buf, "ADD $0, X5, X0") } + fmt.Fprintln(buf, "ADD $1, X10, X10") fmt.Fprintln(buf, "end:") fmt.Fprintln(buf, "ADD $1, X10, X10") fmt.Fprintln(buf, "MOV X10, r+0(FP)") @@ -301,9 +426,9 @@ TEXT _stub(SB),$0-0 // FENCE // NOP // FENCE - // RET - want := "0f 00 f0 0f 13 00 00 00 0f 00 f0 0f 67 80 00 00" - if !strings.Contains(string(out), want) { + // RET (CJALR or JALR) + want := regexp.MustCompile("0x0000 0f 00 f0 0f 13 00 00 00 0f 00 f0 0f (82 80|67 80 00 00) ") + if !want.Match(out) { t.Errorf("PCALIGN test failed - got %s\nwant %s", out, want) } } diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go index 60174a0b3a245f..59e12ed3fbbe0b 100644 --- a/src/cmd/internal/obj/riscv/cpu.go +++ b/src/cmd/internal/obj/riscv/cpu.go @@ -326,6 +326,9 @@ const ( NEED_GOT_PCREL_ITYPE_RELOC ) +const NEED_RELOC = NEED_JAL_RELOC | NEED_CALL_RELOC | NEED_PCREL_ITYPE_RELOC | + NEED_PCREL_STYPE_RELOC | NEED_GOT_PCREL_ITYPE_RELOC + // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files // at https://github.com/riscv/riscv-opcodes. // @@ -336,7 +339,7 @@ const ( // If you modify this table, you MUST run 'go generate' to regenerate anames.go! const ( // - // Unprivileged ISA (version 20240411) + // Unprivileged ISA (version 20260120) // // 2.4: Integer Computational Instructions @@ -401,7 +404,7 @@ const ( ALD ASD - // 7.1: CSR Instructions (Zicsr) + // 6.1: CSR Instructions (Zicsr) ACSRRW ACSRRS ACSRRC @@ -409,18 +412,18 @@ const ( ACSRRSI ACSRRCI - // 12.3: Integer Conditional Operations (Zicond) + // 11.1: Integer Conditional Operations (Zicond) ACZEROEQZ ACZERONEZ - // 13.1: Multiplication Operations + // 12.1: Multiplication Operations AMUL AMULH AMULHU AMULHSU AMULW - // 13.2: Division Operations + // 12.2: Division Operations ADIV ADIVU AREM @@ -430,13 +433,13 @@ const ( AREMW AREMUW - // 14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc) + // 13.2: Load-Reserved/Store-Conditional Instructions (Zalrsc) ALRD ASCD ALRW ASCW - // 14.4: Atomic Memory Operations (Zaamo) + // 13.4: Atomic Memory Operations (Zaamo) AAMOSWAPD AAMOADDD AAMOANDD @@ -456,11 +459,11 @@ const ( AAMOMINW AAMOMINUW - // 20.5: Single-Precision Load and Store Instructions + // 21.5: Single-Precision Load and Store Instructions AFLW AFSW - // 20.6: Single-Precision Floating-Point Computational Instructions + // 21.6: Single-Precision Floating-Point Computational Instructions AFADDS AFSUBS AFMULS @@ -473,7 +476,7 @@ const ( AFNMADDS AFNMSUBS - // 20.7: Single-Precision Floating-Point Conversion and Move Instructions + // 21.7: Single-Precision Floating-Point Conversion and Move Instructions AFCVTWS AFCVTLS AFCVTSW @@ -490,19 +493,19 @@ const ( AFMVXW AFMVWX - // 20.8: Single-Precision Floating-Point Compare Instructions + // 21.8: Single-Precision Floating-Point Compare Instructions AFEQS AFLTS AFLES - // 20.9: Single-Precision Floating-Point Classify Instruction + // 21.9: Single-Precision Floating-Point Classify Instruction AFCLASSS - // 21.3: Double-Precision Load and Store Instructions + // 22.3: Double-Precision Load and Store Instructions AFLD AFSD - // 21.4: Double-Precision Floating-Point Computational Instructions + // 22.4: Double-Precision Floating-Point Computational Instructions AFADDD AFSUBD AFMULD @@ -515,7 +518,7 @@ const ( AFNMADDD AFNMSUBD - // 21.5: Double-Precision Floating-Point Conversion and Move Instructions + // 22.5: Double-Precision Floating-Point Conversion and Move Instructions AFCVTWD AFCVTLD AFCVTDW @@ -532,19 +535,19 @@ const ( AFMVXD AFMVDX - // 21.6: Double-Precision Floating-Point Compare Instructions + // 22.6: Double-Precision Floating-Point Compare Instructions AFEQD AFLTD AFLED - // 21.7: Double-Precision Floating-Point Classify Instruction + // 22.7: Double-Precision Floating-Point Classify Instruction AFCLASSD - // 22.1 Quad-Precision Load and Store Instructions + // 23.1: Quad-Precision Load and Store Instructions AFLQ AFSQ - // 22.2: Quad-Precision Computational Instructions + // 23.2: Quad-Precision Computational Instructions AFADDQ AFSUBQ AFMULQ @@ -557,7 +560,7 @@ const ( AFNMADDQ AFNMSUBQ - // 22.3: Quad-Precision Convert and Move Instructions + // 23.3: Quad-Precision Convert and Move Instructions AFCVTWQ AFCVTLQ AFCVTSQ @@ -574,19 +577,19 @@ const ( AFSGNJNQ AFSGNJXQ - // 22.4: Quad-Precision Floating-Point Compare Instructions + // 23.4: Quad-Precision Floating-Point Compare Instructions AFEQQ AFLEQ AFLTQ - // 22.5: Quad-Precision Floating-Point Classify Instruction + // 23.5: Quad-Precision Floating-Point Classify Instruction AFCLASSQ // // "C" Extension for Compressed Instructions // - // 26.3.1: Compressed Stack-Pointer-Based Loads and Stores + // 28.3.1: Compressed Stack-Pointer-Based Loads and Stores ACLWSP ACLDSP ACFLDSP @@ -594,7 +597,7 @@ const ( ACSDSP ACFSDSP - // 26.3.2: Compressed Register-Based Loads and Stores + // 28.3.2: Compressed Register-Based Loads and Stores ACLW ACLD ACFLD @@ -602,16 +605,18 @@ const ( ACSD ACFSD - // 26.4: Compressed Control Transfer Instructions + // 28.4: Compressed Control Transfer Instructions ACJ ACJR ACJALR ACBEQZ ACBNEZ - // 26.5.1: Compressed Integer Constant-Generation Instructions + // 28.5.1: Compressed Integer Constant-Generation Instructions ACLI ACLUI + + // 28.5.2: Compressed Integer Register-Immediate Operations ACADDI ACADDIW ACADDI16SP @@ -621,7 +626,7 @@ const ( ACSRAI ACANDI - // 26.5.3: Compressed Integer Register-Register Operations + // 28.5.3: Compressed Integer Register-Register Operations ACMV ACADD ACAND @@ -631,17 +636,17 @@ const ( ACADDW ACSUBW - // 26.5.5: Compressed NOP Instruction + // 28.5.5: Compressed NOP Instruction ACNOP - // 26.5.6: Compressed Breakpoint Instruction + // 28.5.6: Compressed Breakpoint Instruction ACEBREAK // // "B" Extension for Bit Manipulation, Version 1.0.0 // - // 28.4.1: Address Generation Instructions (Zba) + // 30.2: Address Generation Instructions (Zba) AADDUW ASH1ADD ASH1ADDUW @@ -651,7 +656,7 @@ const ( ASH3ADDUW ASLLIUW - // 28.4.2: Basic Bit Manipulation (Zbb) + // 30.3: Basic Bit Manipulation (Zbb) AANDN AORN AXNOR @@ -668,8 +673,6 @@ const ( ASEXTB ASEXTH AZEXTH - - // 28.4.3: Bitwise Rotation (Zbb) AROL AROLW AROR @@ -679,7 +682,12 @@ const ( AORCB AREV8 - // 28.4.4: Single-bit Instructions (Zbs) + // 30.4: Carry-less multiplication (Zbc) + ACLMUL + ACLMULH + ACLMULR + + // 30.5: Single-bit Instructions (Zbs) ABCLR ABCLRI ABEXT @@ -710,7 +718,7 @@ const ( AVLMV AVSMV - // 31.7.5: Vector Strided Instructions + // 31.7.5: Vector Constant-Stride Instructions AVLSE8V AVLSE16V AVLSE32V @@ -738,15 +746,13 @@ const ( AVSOXEI32V AVSOXEI64V - // 31.7.7: Unit-stride Fault-Only-First Loads + // 31.7.7: Vector Unit-Stride Fault-Only-First Loads AVLE8FFV AVLE16FFV AVLE32FFV AVLE64FFV - // 31.7.8. Vector Load/Store Segment Instructions - - // 31.7.8.1. Vector Unit-Stride Segment Loads and Stores + // 31.7.8.1: Vector Unit-Stride Segment Loads and Stores AVLSEG2E8V AVLSEG3E8V AVLSEG4E8V @@ -834,7 +840,7 @@ const ( AVLSEG7E64FFV AVLSEG8E64FFV - // 31.7.8.2. Vector Strided Segment Loads and Stores + // 31.7.8.2: Vector Constant-Stride Segment Loads and Stores AVLSSEG2E8V AVLSSEG3E8V AVLSSEG4E8V @@ -893,7 +899,7 @@ const ( AVSSSEG7E64V AVSSSEG8E64V - // 31.7.8.3. Vector Indexed Segment Loads and Stores + // 31.7.8.3: Vector Indexed Segment Loads and Stores AVLOXSEG2EI8V AVLOXSEG3EI8V AVLOXSEG4EI8V @@ -1446,8 +1452,32 @@ const ( AVMV4RV AVMV8RV + // 33.2.1: Vector Basic Bit-manipulation (Zvbb) + AVANDNVV + AVANDNVX + AVBREVV + AVBREV8V + AVREV8V + AVCLZV + AVCTZV + AVCPOPV + AVROLVV + AVROLVX + AVRORVV + AVRORVX + AVRORVI + AVWSLLVV + AVWSLLVX + AVWSLLVI + + // 33.2.2: Vector Carryless Multiplication (Zvbc) + AVCLMULVV + AVCLMULVX + AVCLMULHVV + AVCLMULHVX + // - // Privileged ISA (version 20240411) + // Privileged ISA (version 20260120) // // 3.3.1: Environment Call and Breakpoint @@ -1464,7 +1494,7 @@ const ( // 3.3.3: Wait for Interrupt AWFI - // 10.2: Supervisor Memory-Management Fence Instruction + // 12.2.1: Supervisor Memory-Management Fence Instruction ASFENCEVMA // The escape hatch. Inserts a single 32-bit word. @@ -1482,6 +1512,13 @@ const ( ABLEZ ABLTZ ABNEZ + ACSRC + ACSRCI + ACSRR + ACSRS + ACSRSI + ACSRW + ACSRWI AFABSD AFABSS AFNED @@ -1500,6 +1537,7 @@ const ( ANEG ANEGW ANOT + APAUSE ARDCYCLE ARDINSTRET ARDTIME @@ -1544,7 +1582,10 @@ var rmSuffixSet = map[string]uint8{ "RMM": RM_RMM, } -const rmSuffixBit uint8 = 1 << 7 +const ( + fenceTsoSuffixBit uint8 = 1 << 0 + rmSuffixBit uint8 = 1 << 7 +) func rmSuffixEncode(s string) (uint8, error) { if s == "" { @@ -1613,7 +1654,28 @@ const ( SPOP_CSR_BEGIN = SPOP_RVV_END SPOP_CSR_END = SPOP_CSR_BEGIN + 4096 - SPOP_END = SPOP_CSR_END + 1 + // FENCE operands. 16 special operands are reserved for FENCE flags (4 bits: IORW). + SPOP_FENCE_BEGIN = SPOP_CSR_END + + SPOP_FENCE_W SpecialOperand = SPOP_FENCE_BEGIN + iota - 20 + SPOP_FENCE_R + SPOP_FENCE_RW + SPOP_FENCE_O + SPOP_FENCE_OW + SPOP_FENCE_OR + SPOP_FENCE_ORW + SPOP_FENCE_I + SPOP_FENCE_IW + SPOP_FENCE_IR + SPOP_FENCE_IRW + SPOP_FENCE_IO + SPOP_FENCE_IOW + SPOP_FENCE_IOR + SPOP_FENCE_IORW + + SPOP_FENCE_END = SPOP_FENCE_BEGIN + 16 + + SPOP_END = SPOP_FENCE_END + 1 ) var specialOperands = map[SpecialOperand]struct { @@ -1638,6 +1700,22 @@ var specialOperands = map[SpecialOperand]struct { SPOP_E16: {encoding: 1, name: "E16"}, SPOP_E32: {encoding: 2, name: "E32"}, SPOP_E64: {encoding: 3, name: "E64"}, + + SPOP_FENCE_W: {encoding: 1, name: "W"}, + SPOP_FENCE_R: {encoding: 2, name: "R"}, + SPOP_FENCE_RW: {encoding: 3, name: "RW"}, + SPOP_FENCE_O: {encoding: 4, name: "O"}, + SPOP_FENCE_OW: {encoding: 5, name: "OW"}, + SPOP_FENCE_OR: {encoding: 6, name: "OR"}, + SPOP_FENCE_ORW: {encoding: 7, name: "ORW"}, + SPOP_FENCE_I: {encoding: 8, name: "I"}, + SPOP_FENCE_IW: {encoding: 9, name: "IW"}, + SPOP_FENCE_IR: {encoding: 10, name: "IR"}, + SPOP_FENCE_IRW: {encoding: 11, name: "IRW"}, + SPOP_FENCE_IO: {encoding: 12, name: "IO"}, + SPOP_FENCE_IOW: {encoding: 13, name: "IOW"}, + SPOP_FENCE_IOR: {encoding: 14, name: "IOR"}, + SPOP_FENCE_IORW: {encoding: 15, name: "IORW"}, } func (so SpecialOperand) encode() uint32 { @@ -1652,6 +1730,11 @@ func (so SpecialOperand) encode() uint32 { if _, ok := csrs[csrNum]; ok { return uint32(csrNum) } + case so > SPOP_FENCE_BEGIN && so < SPOP_FENCE_END: + op, ok := specialOperands[so] + if ok { + return op.encoding + } } return 0 } @@ -1668,6 +1751,11 @@ func (so SpecialOperand) String() string { if csrName, ok := csrs[uint16(so-SPOP_CSR_BEGIN)]; ok { return csrName } + case so > SPOP_FENCE_BEGIN && so < SPOP_FENCE_END: + op, ok := specialOperands[so] + if ok { + return op.name + } } return "" } diff --git a/src/cmd/internal/obj/riscv/doc.go b/src/cmd/internal/obj/riscv/doc.go new file mode 100644 index 00000000000000..d8b2c9ad7193c3 --- /dev/null +++ b/src/cmd/internal/obj/riscv/doc.go @@ -0,0 +1,344 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +/* +Package riscv implements the riscv64 assembler. + +# Register naming + +The integer registers are named X0 through to X31, however X4 must be accessed +through its RISC-V ABI name, TP, and X27, which holds a pointer to the Go +routine structure, must be referred to as g. Additionally, when building in +shared mode, X3 is unavailable and must be accessed via its RISC-V ABI name, +GP. + +The floating-point registers are named F0 through to F31. + +The vector registers are named V0 through to V31. + +Both integer and floating-point registers can be referred to by their RISC-V +ABI names, e.g., A0 or FT0, with the exception that X27 cannot be referred to +by its RISC-V ABI name, S11. It must be referred to as g. + +Some of the integer registers are used by the Go runtime and assembler - X26 is +the closure pointer, X27 points to the Go routine structure and X31 is a +temporary register used by the Go assembler. Use of X31 should be avoided in +hand written assembly code as its value could be altered by the instruction +sequences emitted by the assembler. + +# Instruction naming + +Many RISC-V instructions contain one or more suffixes in their names. In the +[RISC-V ISA Manual] these suffixes are separated from themselves and the +name of the instruction mnemonic with a dot ('.'). In the Go assembler, the +separators are omitted and the suffixes are written in upper case. + +Example: + + FMVWX <=> fmv.w.x + +# Rounding modes + +The Go toolchain does not set the FCSR register and requires the desired +rounding mode to be explicitly encoded within floating-point instructions. +The syntax the Go assembler uses to specify the rounding modes differs +from the syntax in the RISC-V specifications. In the [RISC-V ISA Manual] +the rounding mode is given as an extra operand at the end of an +assembly language instruction. In the Go assembler, the rounding modes are +converted to uppercase and follow the instruction mnemonic from which they +are separated with a dot ('.'). + +Example: + + FCVTLUS.RNE F0, X5 <=> fcvt.lu.s x5, f0, rne + +RTZ is assumed if the rounding mode is omitted. + +# RISC-V extensions + +By default the Go compiler targets the [rva20u64] profile. This profile mandates +all the general RISC-V instructions, allowing Go to use integer, multiplication, +division, floating-point and atomic instructions without having to +perform compile time or runtime checks to verify that their use is appropriate +for the target hardware. All widely available riscv64 devices support at least +[rva20u64]. The Go toolchain can be instructed to target later RISC-V profiles, +including, [rva22u64] and [rva23u64], via the GORISCV64 environment variable. +Instructions that are provided by newer profiles cannot typically be used in +handwritten assembly code without compile time guards (or runtime checks) +that ensure they are hardware supported. + +The file asm_riscv64.h defines macros for each RISC-V extension that is enabled +by setting the GORISCV64 environment variable to a value other than [rva20u64]. +For example, if GORISCV64=rva22u64 the macros hasZba, hasZbb and hasZbs will be +defined. If GORISCV64=rva23u64 hasV will be defined in addition to hasZba, +hasZbb and hasZbs. These macros can be used to determine whether it's safe +to use an instruction in hand-written assembly. + +It is not always necessary to include asm_riscv64.h and use #ifdefs in your +code to safely take advantage of instructions present in the [rva22u64] +profile. In some cases the assembler can generate [rva20u64] compatible code +even when an [rva22u64] instruction is used in an assembly source file. When +GORISCV64=rva20u64 the assembler will synthesize certain [rva22u64] +instructions, e.g., ANDN, using multiple [rva20u64] instructions. Instructions +such as ANDN can then be freely used in assembly code without checking to see +whether the instruction is supported by the target profile. When building a +source file containing the ANDN instruction with GORISCV64=rva22u64 the +assembler will emit the Zbb ANDN instruction directly. When building the same +source file with GORISCV64=rva20u64 the assembler will emit multiple [rva20u64] +instructions to synthesize ANDN. + +The assembler will also use [rva22u64] instructions to implement the zero and +sign extension instructions, e.g., MOVB and MOVHU, when GORISCV64=rva22u64 or +greater. + +The instructions not implemented in the default profile ([rva20u64]) that can +be safely used in assembly code without compile time checks are: + + - ANDN + - MAX + - MAXU + - MIN + - MINU + - MOVB + - MOVH + - MOVHU + - MOVWU + - ORN + - ROL + - ROLW + - ROR + - RORI + - RORIW + - RORW + - XNOR + +# Operand ordering + +The ordering used for instruction operands in the Go assembler differs from the +ordering defined in the [RISC-V ISA Manual]. + +1. R-Type instructions + +R-Type instructions are written in the reverse order to that given in the +[RISC-V ISA Manual], with the register order being rs2, rs1, rd. + +Examples: + + ADD X10, X11, X12 <=> add x12, x11, x10 + FADDD F10, F11, F12 <=> fadd.d f12, f11, f10 + +2. I-Type arithmetic instructions + +I-Type arithmetic instructions (not loads, fences, ebreak, ecall) use the same +ordering as the R-Type instructions, typically, imm12, rs1, rd. + +Examples: + + ADDI $1, X11, X12 <=> add x12, x11, 1 + SLTI $1, X11, X12 <=> slti x12, x11, 1 + +3. Loads and Stores + +Load instructions are written with the source operand (whether it be a register +or a memory address), first followed by the destination operand. + +Examples: + + MOV 16(X2), X10 <=> ld x10, 16(x2) + MOV X10, (X2) <=> sd x10, 0(x2) + +4. Branch instructions + +The branch instructions use the same operand ordering as is given in the +[RISC-V ISA Manual], e.g., rs1, rs2, label. + +Example: + + BLT X12, X23, loop1 <=> blt x12, x23, loop1 + +BLT X12, X23, label will jump to label if X12 < X23. Note this is not the +same ordering as is used for the SLT instructions. + +5. FMA instructions + +The Go assembler uses a different ordering for the RISC-V FMA operands to +the ordering given in the [RISC-V ISA Manual]. The operands are rotated one +place to the left, so that the destination operand comes last. + +Example: + + FMADDS F1, F2, F3, F4 <=> fmadd.s f4, f1, f2, f3 + +6. AMO instructions + +The ordering used for the AMO operations is rs2, rs1, rd, i.e., the operands +as specified in the [RISC-V ISA Manual] are rotated one place to the left. + +Example: + + AMOSWAPW X5, (X6), X7 <=> amoswap.w x7, x5, (x6) + +7. Vector instructions + +The VSETVLI instruction uses the same symbolic names as the [RISC-V ISA Manual] +to represent the components of vtype, with the exception +that they are written in upper case. The ordering of the operands in the Go +assembler differs from the [RISC-V ISA Manual] in that the operands are +rotated one place to the left so that the destination register, the register +that holds the new vl, is the last operand. + +Example: + + VSETVLI X10, E8, M1, TU, MU, X12 <=> vsetvli x12, x10, e8, m1, tu, mu + +Vector load and store instructions follow the pattern set by scalar loads and +stores, i.e., the source is always the first operand and the destination the +last. However, the ordering of the operands of these instructions is +complicated by the optional mask register and, in some cases, the use of an +additional stride or index register. In the Go assembler the index and stride +registers appear as the second operand in indexed or strided loads and stores, +while the mask register, if present, is always the penultimate operand. + +Examples: + + VLE8V (X10), V3 <=> vle8.v v3, (x10) + VSE8V V3, (X10) <=> vse8.v v3, (x10) + VLE8V (X10), V0, V3 <=> vle8.v v3, (x10), v0.t + VSE8V V3, V0, (X10) <=> vse8.v v3, (x10), v0.t + VLSE8V (X10), X11, V3 <=> vlse8.v v3, (x10), x11 + VSSE8V V3, X11, (X10) <=> vsse8.v v3, (x10), x11 + VLSE8V (X10), X11, V0, V3 <=> vlse8.v v3, (x10), x11, v0.t + VSSE8V V3, X11, V0, (X10) <=> vsse8.v v3, (x10), x11, v0.t + VLUXEI8V (X10), V2, V3 <=> vluxei8.v v3, (x10), v2 + VSUXEI8V V3, V2, (X10) <=> vsuxei8.v v3, (x10), v2 + VLUXEI8V (X10), V2, V0, V3 <=> vluxei8.v v3, (x10), v2, v0.t + VSUXEI8V V3, V2, V0, (X10) <=> vsuxei8.v v3, (x10), v2, v0.t + VL1RE8V (X10), V3 <=> vl1re8.v v3, (x10) + VS1RV V3, (X11) <=> vs1r.v v3, (x11) + +The ordering of operands for two and three argument vector arithmetic instructions is +reversed in the Go assembler. + +Examples: + + VMVVV V2, V3 <=> vmv.v.v v3, v2 + VADDVV V1, V2, V3 <=> vadd.vv v3, v2, v1 + VADDVX X10, V2, V3 <=> vadd.vx v3, v2, x10 + VMADCVI $15, V2, V3 <=> vmadc.vi v3, v2, 15 + +The mask register, when specified, is always the penultimate operand in a vector +arithmetic instruction, appearing before the destination register. + +Examples: + + VANDVV V1, V2, V0, V3 <=> vand.vv v3, v2, v1, v0.t + +# Ternary instructions + +The Go assembler allows the second operand to be omitted from most ternary +instructions if it matches the third (destination) operand. + +Examples: + + ADD X10, X12, X12 <=> ADD X10, X12 + ANDI $3, X12, X12 <=> ANDI $3, X12 + +The use of this abbreviated syntax is encouraged. + +# Ordering of atomic instructions + +The FENCE instruction supports all of the bits in the predecessor and successor +sets. The predecessor set is specified before the successor set. The letters +representing the bits in both sets must be given in uppercase. For example, + + FENCE R, RW + +specifies a FENCE instruction with the R bit set in the predecessor set and +the R and W bits set in the successor set. + +If neither set is provided a full fence is emitted, e.g., + + FENCE + +and + + FENCE IORW, IORW + +are equivalent. + +The FENCE.TSO instruction is supported. + +It is not possible to specify the ordering bits in the LR, SC or AMO +instructions. The acquire and release bits are always set for the AMO +instructions, the acquire bit is always set for the LR instructions while +the release bit is set for the SC instructions. + +# Immediate operands + +In many cases, where an R-Type instruction has a corresponding I-Type +instruction, the R-Type mnemonic can be used in place of the I-Type mnemonic. +The assembler assumes that the immediate form of the instruction was intended +when the first operand is given as an immediate value rather than a register. + +Example: + + AND $3, X12, X13 <=> ANDI $3, X12, X13 + +# Integer constant materialization + +The MOV instruction can be used to set a register to the value of any 64 bit +constant literal. The way this is achieved by the assembler varies depending +on the value of the constant. Where possible the assembler will synthesize the +constant using one or more RISC-V arithmetic instructions. If it is unable +to easily materialize the constant it will load the 64 bit literal from memory. + +A 32 bit constant literal can be specified as an argument to ADDI, ANDI, ORI and +XORI. If the specified literal does not fit into 12 bits the assembler will +generate extra instructions to synthesize it. + +Integer constants provided as operands to all other instructions must fit into +the number of bits allowed by the instructions' encodings for immediate values. +Otherwise, an error will be generated. + +# Floating point constant materialization + +The MOVF and MOVD instructions can be used to set a register to the value +of any 32 bit or 64 bit floating point constant literal, respectively. Unless +the constant literal is 0.0, MOVF and MOVD will be encoded as FLW and FLD +instructions that load the constant from a location within the program's +binary. + +# Compressed instructions + +The Go assembler converts 32 bit RISC-V instructions to compressed +instructions when generating machine code. This conversion happens +automatically without the need for any direct involvement from the programmer, +although judicious choice of registers can improve the compression rate for +certain instructions (see the [RISC-V ISA Manual] for more details). This +behaviour is enabled by default for all of the supported RISC-V profiles, i.e., +it is not affected by the value of the GORISCV64 environment variable. + +The use of compressed instructions can be disabled via a debug flag, +compressinstructions: + + - Use -gcflags=all=-d=compressinstructions=0 to disable compressed + instructions in Go code. + - Use -asmflags=all=-d=compressinstructions=0 to disable compressed + instructions in assembly code. + +To completely disable automatic instruction compression in a Go binary both +options must be specified. + +The assembler also permits the use of compressed instructions in hand coded +assembly language, but this should generally be avoided. Note that the +compressinstructions flag only prevents the automatic compression of 32 +bit instructions. It has no effect on compressed instructions that are +hand coded directly into an assembly file. + +[RISC-V ISA Manual]: https://github.com/riscv/riscv-isa-manual +[rva20u64]: https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#51-rva20u64-profile +[rva22u64]: https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#rva22u64-profile +[rva23u64]: https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile +*/ +package riscv diff --git a/src/cmd/internal/obj/riscv/inst.go b/src/cmd/internal/obj/riscv/inst.go index a5b3acdb18110c..367cc44f192059 100644 --- a/src/cmd/internal/obj/riscv/inst.go +++ b/src/cmd/internal/obj/riscv/inst.go @@ -1,4 +1,4 @@ -// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicond rv_zicsr; DO NOT EDIT. +// Code generated by make inst.go EXTENSIONS="rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbc rv_zbs rv_zicond rv_zicsr rv_zvbb rv_zvbc"; DO NOT EDIT. package riscv import "cmd/internal/obj" @@ -170,6 +170,12 @@ func encode(a obj.As) *inst { return &inst{0x2, 0x4, 0x1, 0x0, 0, 0x0} case ACXOR: return &inst{0x21, 0x0, 0x1, 0x0, 0, 0x0} + case ACLMUL: + return &inst{0x33, 0x1, 0x0, 0x0, 160, 0x5} + case ACLMULH: + return &inst{0x33, 0x3, 0x0, 0x0, 160, 0x5} + case ACLMULR: + return &inst{0x33, 0x2, 0x0, 0x0, 160, 0x5} case ACLZ: return &inst{0x13, 0x1, 0x0, 0x0, 1536, 0x30} case ACLZW: @@ -570,6 +576,10 @@ func encode(a obj.As) *inst { return &inst{0x57, 0x0, 0x0, 0x0, 576, 0x12} case AVANDVX: return &inst{0x57, 0x4, 0x0, 0x0, 576, 0x12} + case AVANDNVV: + return &inst{0x57, 0x0, 0x0, 0x0, 64, 0x2} + case AVANDNVX: + return &inst{0x57, 0x4, 0x0, 0x0, 64, 0x2} case AVASUBVV: return &inst{0x57, 0x2, 0x0, 0x0, 704, 0x16} case AVASUBVX: @@ -578,10 +588,28 @@ func encode(a obj.As) *inst { return &inst{0x57, 0x2, 0x0, 0x0, 640, 0x14} case AVASUBUVX: return &inst{0x57, 0x6, 0x0, 0x0, 640, 0x14} + case AVBREV8V: + return &inst{0x57, 0x2, 0x8, 0x0, 1152, 0x24} + case AVBREVV: + return &inst{0x57, 0x2, 0xa, 0x0, 1152, 0x24} + case AVCLMULVV: + return &inst{0x57, 0x2, 0x0, 0x0, 768, 0x18} + case AVCLMULVX: + return &inst{0x57, 0x6, 0x0, 0x0, 768, 0x18} + case AVCLMULHVV: + return &inst{0x57, 0x2, 0x0, 0x0, 832, 0x1a} + case AVCLMULHVX: + return &inst{0x57, 0x6, 0x0, 0x0, 832, 0x1a} + case AVCLZV: + return &inst{0x57, 0x2, 0xc, 0x0, 1152, 0x24} case AVCOMPRESSVM: return &inst{0x57, 0x2, 0x0, 0x0, 1504, 0x2f} case AVCPOPM: return &inst{0x57, 0x2, 0x10, 0x0, 1024, 0x20} + case AVCPOPV: + return &inst{0x57, 0x2, 0xe, 0x0, 1152, 0x24} + case AVCTZV: + return &inst{0x57, 0x2, 0xd, 0x0, 1152, 0x24} case AVDIVVV: return &inst{0x57, 0x2, 0x0, 0x0, -1984, 0x42} case AVDIVVX: @@ -1360,6 +1388,8 @@ func encode(a obj.As) *inst { return &inst{0x57, 0x2, 0x0, 0x0, -1920, 0x44} case AVREMUVX: return &inst{0x57, 0x6, 0x0, 0x0, -1920, 0x44} + case AVREV8V: + return &inst{0x57, 0x2, 0x9, 0x0, 1152, 0x24} case AVRGATHERVI: return &inst{0x57, 0x3, 0x0, 0x0, 768, 0x18} case AVRGATHERVV: @@ -1368,6 +1398,16 @@ func encode(a obj.As) *inst { return &inst{0x57, 0x4, 0x0, 0x0, 768, 0x18} case AVRGATHEREI16VV: return &inst{0x57, 0x0, 0x0, 0x0, 896, 0x1c} + case AVROLVV: + return &inst{0x57, 0x0, 0x0, 0x0, 1344, 0x2a} + case AVROLVX: + return &inst{0x57, 0x4, 0x0, 0x0, 1344, 0x2a} + case AVRORVI: + return &inst{0x57, 0x3, 0x0, 0x0, 1280, 0x28} + case AVRORVV: + return &inst{0x57, 0x0, 0x0, 0x0, 1280, 0x28} + case AVRORVX: + return &inst{0x57, 0x4, 0x0, 0x0, 1280, 0x28} case AVRSUBVI: return &inst{0x57, 0x3, 0x0, 0x0, 192, 0x6} case AVRSUBVX: @@ -1770,6 +1810,12 @@ func encode(a obj.As) *inst { return &inst{0x57, 0x0, 0x0, 0x0, -960, 0x62} case AVWREDSUMUVS: return &inst{0x57, 0x0, 0x0, 0x0, -1024, 0x60} + case AVWSLLVI: + return &inst{0x57, 0x3, 0x0, 0x0, -704, 0x6a} + case AVWSLLVV: + return &inst{0x57, 0x0, 0x0, 0x0, -704, 0x6a} + case AVWSLLVX: + return &inst{0x57, 0x4, 0x0, 0x0, -704, 0x6a} case AVWSUBVV: return &inst{0x57, 0x2, 0x0, 0x0, -832, 0x66} case AVWSUBVX: @@ -1829,8 +1875,6 @@ var csrs = map[uint16]string{ 0x48: "USCRATCHCSW", 0x49: "USCRATCHCSWL", 0x100: "SSTATUS", - 0x102: "SEDELEG", - 0x103: "SIDELEG", 0x104: "SIE", 0x105: "STVEC", 0x106: "SCOUNTEREN", @@ -1864,6 +1908,7 @@ var csrs = map[uint16]string{ 0x15f: "SCTRDEPTH", 0x180: "SATP", 0x181: "SRMCFG", + 0x183: "SPMPEN", 0x200: "VSSTATUS", 0x204: "VSIE", 0x205: "VSTVEC", @@ -1898,6 +1943,7 @@ var csrs = map[uint16]string{ 0x30d: "MSTATEEN1", 0x30e: "MSTATEEN2", 0x30f: "MSTATEEN3", + 0x316: "MPMPDELEG", 0x320: "MCOUNTINHIBIT", 0x321: "MCYCLECFG", 0x322: "MINSTRETCFG", diff --git a/src/cmd/internal/obj/riscv/list.go b/src/cmd/internal/obj/riscv/list.go index da703c02ad228f..2e064eb823736f 100644 --- a/src/cmd/internal/obj/riscv/list.go +++ b/src/cmd/internal/obj/riscv/list.go @@ -37,6 +37,9 @@ func RegName(r int) string { } func opSuffixString(s uint8) string { + if s == fenceTsoSuffixBit { + return ".TSO" + } if s&rmSuffixBit == 0 { return "" } diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go index e55c206a98e434..629a49a91b4b9c 100644 --- a/src/cmd/internal/obj/riscv/obj.go +++ b/src/cmd/internal/obj/riscv/obj.go @@ -70,6 +70,10 @@ func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { // form of the instruction. if p.From.Type == obj.TYPE_CONST { switch p.As { + case ACSUB: + p.As, p.From.Offset = ACADDI, -p.From.Offset + case ACSUBW: + p.As, p.From.Offset = ACADDIW, -p.From.Offset case ASUB: p.As, p.From.Offset = AADDI, -p.From.Offset case ASUBW: @@ -135,11 +139,11 @@ func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { p.As = AEBREAK case AMOV: - if p.From.Type == obj.TYPE_CONST && p.From.Name == obj.NAME_NONE && p.From.Reg == obj.REG_NONE && int64(int32(p.From.Offset)) != p.From.Offset { - if isShiftConst(p.From.Offset) { + if p.From.Type == obj.TYPE_CONST && p.From.Name == obj.NAME_NONE && p.From.Reg == obj.REG_NONE { + if isMaterialisableConst(p.From.Offset) { break } - // Put >32-bit constants in memory and load them. + // Put non-materialisable constants in memory and load them. p.From.Type = obj.TYPE_MEM p.From.Sym = ctxt.Int64Sym(p.From.Offset) p.From.Name = obj.NAME_EXTERN @@ -381,6 +385,10 @@ func InvertBranch(as obj.As) obj.As { return ABEQ case ABNEZ: return ABEQZ + case ACBEQZ: + return ACBNEZ + case ACBNEZ: + return ACBEQZ default: panic("InvertBranch: not a branch") } @@ -394,7 +402,7 @@ func containsCall(sym *obj.LSym) bool { switch p.As { case obj.ACALL: return true - case AJAL, AJALR: + case ACJALR, AJAL, AJALR: if p.From.Type == obj.TYPE_REG && p.From.Reg == REG_LR { return true } @@ -406,10 +414,10 @@ func containsCall(sym *obj.LSym) bool { // setPCs sets the Pc field in all instructions reachable from p. // It uses pc as the initial value and returns the next available pc. -func setPCs(p *obj.Prog, pc int64) int64 { +func setPCs(p *obj.Prog, pc int64, compress bool) int64 { for ; p != nil; p = p.Link { p.Pc = pc - for _, ins := range instructionsForProg(p) { + for _, ins := range instructionsForProg(p, compress) { pc += int64(ins.length()) } @@ -588,7 +596,10 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { case obj.ARET: // Replace RET with epilogue. - retJMP := p.To.Sym + retJMP, retReg := p.To.Sym, p.To.Reg + if retReg == obj.REG_NONE { + retReg = REG_LR + } if stacksize != 0 { // Restore LR. @@ -613,7 +624,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { p.As = AJALR p.From = obj.Addr{Type: obj.TYPE_REG, Reg: REG_ZERO} p.Reg = obj.REG_NONE - p.To = obj.Addr{Type: obj.TYPE_REG, Reg: REG_LR} + p.To = obj.Addr{Type: obj.TYPE_REG, Reg: retReg} } // "Add back" the stack removed in the previous instruction. @@ -663,14 +674,14 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { // a fixed point will be reached). No attempt to handle functions > 2GiB. for { big, rescan := false, false - maxPC := setPCs(cursym.Func().Text, 0) + maxPC := setPCs(cursym.Func().Text, 0, ctxt.CompressInstructions) if maxPC+maxTrampSize > (1 << 20) { big = true } for p := cursym.Func().Text; p != nil; p = p.Link { switch p.As { - case ABEQ, ABEQZ, ABGE, ABGEU, ABGEZ, ABGT, ABGTU, ABGTZ, ABLE, ABLEU, ABLEZ, ABLT, ABLTU, ABLTZ, ABNE, ABNEZ: + case ABEQ, ABEQZ, ABGE, ABGEU, ABGEZ, ABGT, ABGTU, ABGTZ, ABLE, ABLEU, ABLEZ, ABLT, ABLTU, ABLTZ, ABNE, ABNEZ, ACBEQZ, ACBNEZ, ACJ: if p.To.Type != obj.TYPE_BRANCH { ctxt.Diag("%v: instruction with branch-like opcode lacks destination", p) break @@ -752,7 +763,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { // instructions will break everything--don't do it! for p := cursym.Func().Text; p != nil; p = p.Link { switch p.As { - case ABEQ, ABEQZ, ABGE, ABGEU, ABGEZ, ABGT, ABGTU, ABGTZ, ABLE, ABLEU, ABLEZ, ABLT, ABLTU, ABLTZ, ABNE, ABNEZ: + case ABEQ, ABEQZ, ABGE, ABGEU, ABGEZ, ABGT, ABGTU, ABGTZ, ABLE, ABLEU, ABLEZ, ABLT, ABLTU, ABLTZ, ABNE, ABNEZ, ACBEQZ, ACBNEZ, ACJ: switch p.To.Type { case obj.TYPE_BRANCH: p.To.Type, p.To.Offset = obj.TYPE_CONST, p.To.Target().Pc-p.Pc @@ -785,15 +796,15 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { ctxt.Diag("alignment value of an instruction must be a power of two and in the range [4, 2048], got %d\n", alignedValue) } // Update the current text symbol alignment value. - if int32(alignedValue) > cursym.Func().Align { - cursym.Func().Align = int32(alignedValue) + if int16(alignedValue) > cursym.Align { + cursym.Align = int16(alignedValue) } } } // Validate all instructions - this provides nice error messages. for p := cursym.Func().Text; p != nil; p = p.Link { - for _, ins := range instructionsForProg(p) { + for _, ins := range instructionsForProg(p, ctxt.CompressInstructions) { ins.validate(ctxt) } } @@ -1042,6 +1053,16 @@ func regVal(r, min, max uint32) uint32 { return r - min } +// regCI returns an integer register for use in a compressed instruction. +func regCI(r uint32) uint32 { + return regVal(r, REG_X8, REG_X15) +} + +// regCF returns a float register for use in a compressed instruction. +func regCF(r uint32) uint32 { + return regVal(r, REG_F8, REG_F15) +} + // regI returns an integer register. func regI(r uint32) uint32 { return regVal(r, REG_X0, REG_X31) @@ -1123,6 +1144,32 @@ func wantImmU(ctxt *obj.Link, ins *instruction, imm int64, nbits uint) { } } +func isScaledImmI(imm int64, nbits uint, scale int64) bool { + return immFits(imm, nbits, true) == nil && imm%scale == 0 +} + +func isScaledImmU(imm int64, nbits uint, scale int64) bool { + return immFits(imm, nbits, false) == nil && imm%scale == 0 +} + +func wantScaledImm(ctxt *obj.Link, ins *instruction, imm int64, nbits uint, scale int64, signed bool) { + if err := immFits(imm, nbits, signed); err != nil { + ctxt.Diag("%v: %v", ins, err) + return + } + if imm%scale != 0 { + ctxt.Diag("%v: unsigned immediate %d must be a multiple of %d", ins, imm, scale) + } +} + +func wantScaledImmI(ctxt *obj.Link, ins *instruction, imm int64, nbits uint, scale int64) { + wantScaledImm(ctxt, ins, imm, nbits, scale, true) +} + +func wantScaledImmU(ctxt *obj.Link, ins *instruction, imm int64, nbits uint, scale int64) { + wantScaledImm(ctxt, ins, imm, nbits, scale, false) +} + func wantReg(ctxt *obj.Link, ins *instruction, pos string, descr string, r, min, max uint32) { if r < min || r > max { var suffix string @@ -1144,11 +1191,31 @@ func wantIntReg(ctxt *obj.Link, ins *instruction, pos string, r uint32) { wantReg(ctxt, ins, pos, "integer", r, REG_X0, REG_X31) } +func isIntPrimeReg(r uint32) bool { + return r >= REG_X8 && r <= REG_X15 +} + +// wantIntPrimeReg checks that r is an integer register that can be used +// in a prime register field of a compressed instruction. +func wantIntPrimeReg(ctxt *obj.Link, ins *instruction, pos string, r uint32) { + wantReg(ctxt, ins, pos, "integer prime", r, REG_X8, REG_X15) +} + // wantFloatReg checks that r is a floating-point register. func wantFloatReg(ctxt *obj.Link, ins *instruction, pos string, r uint32) { wantReg(ctxt, ins, pos, "float", r, REG_F0, REG_F31) } +func isFloatPrimeReg(r uint32) bool { + return r >= REG_F8 && r <= REG_F15 +} + +// wantFloatPrimeReg checks that r is an floating-point register that can +// be used in a prime register field of a compressed instruction. +func wantFloatPrimeReg(ctxt *obj.Link, ins *instruction, pos string, r uint32) { + wantReg(ctxt, ins, pos, "float prime", r, REG_F8, REG_F15) +} + // wantVectorReg checks that r is a vector register. func wantVectorReg(ctxt *obj.Link, ins *instruction, pos string, r uint32) { wantReg(ctxt, ins, pos, "vector", r, REG_V0, REG_V31) @@ -1161,6 +1228,206 @@ func wantEvenOffset(ctxt *obj.Link, ins *instruction, offset int64) { } } +func validateCA(ctxt *obj.Link, ins *instruction) { + wantIntPrimeReg(ctxt, ins, "rd", ins.rd) + if ins.rd != ins.rs1 { + ctxt.Diag("%v: rd must be the same as rs1", ins) + } + wantIntPrimeReg(ctxt, ins, "rs2", ins.rs2) +} + +func validateCB(ctxt *obj.Link, ins *instruction) { + if (ins.as == ACSRAI || ins.as == ACSRLI) && ins.imm == 0 { + ctxt.Diag("%v: immediate cannot be zero", ins) + } else if ins.as == ACSRAI || ins.as == ACSRLI { + wantImmU(ctxt, ins, ins.imm, 6) + } else if ins.as == ACBEQZ || ins.as == ACBNEZ { + wantImmI(ctxt, ins, ins.imm, 9) + } else { + wantImmI(ctxt, ins, ins.imm, 6) + } + if ins.as == ACBEQZ || ins.as == ACBNEZ { + wantNoneReg(ctxt, ins, "rd", ins.rd) + wantIntPrimeReg(ctxt, ins, "rs1", ins.rs1) + } else { + wantIntPrimeReg(ctxt, ins, "rd", ins.rd) + if ins.rd != ins.rs1 { + ctxt.Diag("%v: rd must be the same as rs1", ins) + } + } + wantNoneReg(ctxt, ins, "rs2", ins.rs2) +} + +func validateCI(ctxt *obj.Link, ins *instruction) { + if ins.as != ACNOP && ins.rd == REG_X0 { + ctxt.Diag("%v: cannot use register X0 in rd", ins) + } + if ins.as == ACLUI && ins.rd == REG_X2 { + ctxt.Diag("%v: cannot use register SP/X2 in rd", ins) + } + if ins.as != ACLI && ins.as != ACLUI && ins.as != ACLWSP && ins.as != ACLDSP && ins.as != ACFLDSP && ins.rd != ins.rs1 { + ctxt.Diag("%v: rd must be the same as rs1", ins) + } + if ins.as == ACADDI16SP && ins.rd != REG_SP { + ctxt.Diag("%v: rd must be SP/X2", ins) + } + if (ins.as == ACLWSP || ins.as == ACLDSP || ins.as == ACFLDSP) && ins.rs2 != REG_SP { + ctxt.Diag("%v: rs2 must be SP/X2", ins) + } + if (ins.as == ACADDI || ins.as == ACADDI16SP || ins.as == ACLUI || ins.as == ACSLLI) && ins.imm == 0 { + ctxt.Diag("%v: immediate cannot be zero", ins) + } else if ins.as == ACSLLI { + wantImmU(ctxt, ins, ins.imm, 6) + } else if ins.as == ACLWSP { + wantScaledImmU(ctxt, ins, ins.imm, 8, 4) + } else if ins.as == ACLDSP || ins.as == ACFLDSP { + wantScaledImmU(ctxt, ins, ins.imm, 9, 8) + } else if ins.as == ACADDI16SP { + wantScaledImmI(ctxt, ins, ins.imm, 10, 16) + } else { + wantImmI(ctxt, ins, ins.imm, 6) + } + switch ins.as { + case ACNOP, ACADDI, ACADDIW, ACSLLI: + wantIntReg(ctxt, ins, "rd", ins.rd) + wantIntReg(ctxt, ins, "rs1", ins.rs1) + wantNoneReg(ctxt, ins, "rs2", ins.rs2) + case ACLWSP, ACLDSP: + wantIntReg(ctxt, ins, "rd", ins.rd) + wantNoneReg(ctxt, ins, "rs1", ins.rs1) + wantIntReg(ctxt, ins, "rs2", ins.rs2) + case ACFLDSP: + wantFloatReg(ctxt, ins, "rd", ins.rd) + wantNoneReg(ctxt, ins, "rs1", ins.rs1) + wantIntReg(ctxt, ins, "rs2", ins.rs2) + case ACADDI16SP: + wantIntReg(ctxt, ins, "rd", ins.rd) + wantIntReg(ctxt, ins, "rs1", ins.rs1) + wantNoneReg(ctxt, ins, "rs2", ins.rs2) + default: + wantIntReg(ctxt, ins, "rd", ins.rd) + wantNoneReg(ctxt, ins, "rs1", ins.rs1) + wantNoneReg(ctxt, ins, "rs2", ins.rs2) + } +} + +func validateCIW(ctxt *obj.Link, ins *instruction) { + wantScaledImmU(ctxt, ins, ins.imm, 10, 4) + wantIntPrimeReg(ctxt, ins, "rd", ins.rd) + wantIntReg(ctxt, ins, "rs1", ins.rs1) + wantNoneReg(ctxt, ins, "rs2", ins.rs2) + if ins.imm == 0 { + ctxt.Diag("%v: immediate cannot be zero", ins) + } + if ins.rs1 != REG_SP { + ctxt.Diag("%v: SP/X2 must be in rs1", ins) + } +} + +func validateCJ(ctxt *obj.Link, ins *instruction) { + wantEvenOffset(ctxt, ins, ins.imm) + wantImmI(ctxt, ins, ins.imm, 12) + if ins.as != ACJ { + wantNoneReg(ctxt, ins, "rd", ins.rd) + wantIntReg(ctxt, ins, "rs1", ins.rs1) + wantIntReg(ctxt, ins, "rs2", ins.rs2) + if ins.rs1 == REG_X0 { + ctxt.Diag("%v: cannot use register X0 in rs1", ins) + } + } +} + +func validateCL(ctxt *obj.Link, ins *instruction) { + if ins.as == ACLW { + wantScaledImmU(ctxt, ins, ins.imm, 7, 4) + } else if ins.as == ACLD || ins.as == ACFLD { + wantScaledImmU(ctxt, ins, ins.imm, 8, 8) + } else { + wantImmI(ctxt, ins, ins.imm, 5) + } + if ins.as == ACFLD { + wantFloatPrimeReg(ctxt, ins, "rd", ins.rd) + } else { + wantIntPrimeReg(ctxt, ins, "rd", ins.rd) + } + wantIntPrimeReg(ctxt, ins, "rs1", ins.rs1) + wantNoneReg(ctxt, ins, "rs2", ins.rs2) +} + +func validateCR(ctxt *obj.Link, ins *instruction) { + switch ins.as { + case ACJR, ACJALR: + wantNoneReg(ctxt, ins, "rd", ins.rd) + wantIntReg(ctxt, ins, "rs1", ins.rs1) + wantNoneReg(ctxt, ins, "rs2", ins.rs2) + if ins.rs1 == REG_X0 { + ctxt.Diag("%v: cannot use register X0 in rs1", ins) + } + case ACMV: + wantIntReg(ctxt, ins, "rd", ins.rd) + wantNoneReg(ctxt, ins, "rs1", ins.rs1) + wantIntReg(ctxt, ins, "rs2", ins.rs2) + if ins.rd == REG_X0 { + ctxt.Diag("%v: cannot use register X0 in rd", ins) + } + if ins.rs2 == REG_X0 { + ctxt.Diag("%v: cannot use register X0 in rs2", ins) + } + case ACEBREAK: + wantNoneReg(ctxt, ins, "rd", ins.rd) + wantNoneReg(ctxt, ins, "rs1", ins.rs1) + wantNoneReg(ctxt, ins, "rs2", ins.rs2) + case ACADD: + wantIntReg(ctxt, ins, "rd", ins.rd) + if ins.rd == REG_X0 { + ctxt.Diag("%v: cannot use register X0 in rd", ins) + } + if ins.rd != ins.rs1 { + ctxt.Diag("%v: rd must be the same as rs1", ins) + } + wantIntReg(ctxt, ins, "rs2", ins.rs2) + if ins.rs2 == REG_X0 { + ctxt.Diag("%v: cannot use register X0 in rs2", ins) + } + } +} + +func validateCS(ctxt *obj.Link, ins *instruction) { + if ins.as == ACSW { + wantScaledImmU(ctxt, ins, ins.imm, 7, 4) + } else if ins.as == ACSD || ins.as == ACFSD { + wantScaledImmU(ctxt, ins, ins.imm, 8, 8) + } else { + wantImmI(ctxt, ins, ins.imm, 5) + } + wantNoneReg(ctxt, ins, "rd", ins.rd) + wantIntPrimeReg(ctxt, ins, "rs1", ins.rs1) + if ins.as == ACFSD { + wantFloatPrimeReg(ctxt, ins, "rs2", ins.rs2) + } else { + wantIntPrimeReg(ctxt, ins, "rs2", ins.rs2) + } +} + +func validateCSS(ctxt *obj.Link, ins *instruction) { + if ins.rd != REG_SP { + ctxt.Diag("%v: rd must be SP/X2", ins) + } + if ins.as == ACSWSP { + wantScaledImmU(ctxt, ins, ins.imm, 8, 4) + } else if ins.as == ACSDSP || ins.as == ACFSDSP { + wantScaledImmU(ctxt, ins, ins.imm, 9, 8) + } else { + wantImmI(ctxt, ins, ins.imm, 6) + } + wantNoneReg(ctxt, ins, "rs1", ins.rs1) + if ins.as == ACFSDSP { + wantFloatReg(ctxt, ins, "rs2", ins.rs2) + } else { + wantIntReg(ctxt, ins, "rs2", ins.rs2) + } +} + func validateRII(ctxt *obj.Link, ins *instruction) { wantIntReg(ctxt, ins, "rd", ins.rd) wantIntReg(ctxt, ins, "rs1", ins.rs1) @@ -1422,10 +1689,244 @@ func validateRaw(ctxt *obj.Link, ins *instruction) { wantImmU(ctxt, ins, ins.imm, 32) } -// extractBitAndShift extracts the specified bit from the given immediate, -// before shifting it to the requested position and returning it. -func extractBitAndShift(imm uint32, bit, pos int) uint32 { - return ((imm >> bit) & 1) << pos +// compressedEncoding returns the fixed instruction encoding for a compressed +// instruction. +func compressedEncoding(as obj.As) uint32 { + enc := encode(as) + if enc == nil { + panic("compressedEncoding: could not encode instruction") + } + + // TODO: this can be removed once encode is reworked to return the + // necessary bits. + op := uint32(0) + switch as { + case ACSUB: + op = 0b100011<<10 | 0b00<<5 + case ACXOR: + op = 0b100011<<10 | 0b01<<5 + case ACOR: + op = 0b100011<<10 | 0b10<<5 + case ACAND: + op = 0b100011<<10 | 0b11<<5 + case ACSUBW: + op = 0b100111<<10 | 0b00<<5 + case ACADDW: + op = 0b100111<<10 | 0b01<<5 + case ACBEQZ: + op = 0b110 << 13 + case ACBNEZ: + op = 0b111 << 13 + case ACANDI: + op = 0b100<<13 | 0b10<<10 + case ACSRAI: + op = 0b100<<13 | 0b01<<10 + case ACSRLI: + op = 0b100<<13 | 0b00<<10 + case ACLI: + op = 0b010 << 13 + case ACLUI: + op = 0b011 << 13 + case ACLWSP: + op = 0b010 << 13 + case ACLDSP: + op = 0b011 << 13 + case ACFLDSP: + op = 0b001 << 13 + case ACADDIW: + op = 0b001 << 13 + case ACADDI16SP: + op = 0b011 << 13 + case ACADDI4SPN: + op = 0b000 << 13 + case ACJ: + op = 0b101 << 13 + case ACLW: + op = 0b010 << 13 + case ACLD: + op = 0b011 << 13 + case ACFLD: + op = 0b001 << 13 + case ACJR: + op = 0b1000 << 12 + case ACMV: + op = 0b1000 << 12 + case ACEBREAK: + op = 0b1001 << 12 + case ACJALR: + op = 0b1001 << 12 + case ACADD: + op = 0b1001 << 12 + case ACSW: + op = 0b110 << 13 + case ACSD: + op = 0b111 << 13 + case ACFSD: + op = 0b101 << 13 + case ACSWSP: + op = 0b110 << 13 + case ACSDSP: + op = 0b111 << 13 + case ACFSDSP: + op = 0b101 << 13 + } + + return op | enc.opcode +} + +// encodeBitPattern encodes an immediate value by extracting the specified +// bit pattern from the given immediate. Each value in the pattern specifies +// the position of the bit to extract from the immediate, which are then +// encoded in sequence. +func encodeBitPattern(imm uint32, pattern []int) uint32 { + outImm := uint32(0) + for _, bit := range pattern { + outImm = outImm<<1 | (imm>>bit)&1 + } + return outImm +} + +// encodeCA encodes a compressed arithmetic (CA-type) instruction. +func encodeCA(ins *instruction) uint32 { + return compressedEncoding(ins.as) | regCI(ins.rd)<<7 | regCI(ins.rs2)<<2 +} + +// encodeCBImmediate encodes an immediate for a CB-type RISC-V instruction. +func encodeCBImmediate(imm uint32) uint32 { + // Bit order - [8|4:3|7:6|2:1|5] + bits := encodeBitPattern(imm, []int{8, 4, 3, 7, 6, 2, 1, 5}) + return (bits>>5)<<10 | (bits&0x1f)<<2 +} + +// encodeCB encodes a compressed branch (CB-type) instruction. +func encodeCB(ins *instruction) uint32 { + imm := uint32(0) + if ins.as == ACBEQZ || ins.as == ACBNEZ { + imm = immI(ins.as, ins.imm, 9) + imm = encodeBitPattern(imm, []int{8, 4, 3, 7, 6, 2, 1, 5}) + } else if ins.as == ACANDI { + imm = immI(ins.as, ins.imm, 6) + imm = (imm>>5)<<7 | imm&0x1f + } else if ins.as == ACSRAI || ins.as == ACSRLI { + imm = immU(ins.as, ins.imm, 6) + imm = (imm>>5)<<7 | imm&0x1f + } + return compressedEncoding(ins.as) | (imm>>5)<<10 | regCI(ins.rs1)<<7 | (imm&0x1f)<<2 +} + +// encodeCI encodes a compressed immediate (CI-type) instruction. +func encodeCI(ins *instruction) uint32 { + imm := uint32(ins.imm) + if ins.as == ACLWSP { + // Bit order [5:2|7:6] + imm = encodeBitPattern(imm, []int{5, 4, 3, 2, 7, 6}) + } else if ins.as == ACLDSP || ins.as == ACFLDSP { + // Bit order [5:3|8:6] + imm = encodeBitPattern(imm, []int{5, 4, 3, 8, 7, 6}) + } else if ins.as == ACADDI16SP { + // Bit order [9|4|6|8:7|5] + imm = encodeBitPattern(imm, []int{9, 4, 6, 8, 7, 5}) + } + rd := uint32(0) + if ins.as == ACFLDSP { + rd = regF(ins.rd) + } else { + rd = regI(ins.rd) + } + return compressedEncoding(ins.as) | ((imm>>5)&0x1)<<12 | rd<<7 | (imm&0x1f)<<2 +} + +// encodeCIW encodes a compressed immediate wide (CIW-type) instruction. +func encodeCIW(ins *instruction) uint32 { + imm := uint32(ins.imm) + if ins.as == ACADDI4SPN { + // Bit order [5:4|9:6|2|3] + imm = encodeBitPattern(imm, []int{5, 4, 9, 8, 7, 6, 2, 3}) + } + return compressedEncoding(ins.as) | imm<<5 | regCI(ins.rd)<<2 +} + +// encodeCJImmediate encodes an immediate for a CJ-type RISC-V instruction. +func encodeCJImmediate(imm uint32) uint32 { + // Bit order - [11|4|9:8|10|6|7|3:1|5] + bits := encodeBitPattern(imm, []int{11, 4, 9, 8, 10, 6, 7, 3, 2, 1, 5}) + return bits << 2 +} + +// encodeCJ encodes a compressed jump (CJ-type) instruction. +func encodeCJ(ins *instruction) uint32 { + return compressedEncoding(ins.as) | encodeCJImmediate(uint32(ins.imm)) +} + +// encodeCL encodes a compressed load (CL-type) instruction. +func encodeCL(ins *instruction) uint32 { + imm := uint32(ins.imm) + if ins.as == ACLW { + // Bit order [5:2|6] + imm = encodeBitPattern(imm, []int{5, 4, 3, 2, 6}) + } else if ins.as == ACLD || ins.as == ACFLD { + // Bit order [5:3|7:6] + imm = encodeBitPattern(imm, []int{5, 4, 3, 7, 6}) + } + rd := uint32(0) + if ins.as == ACFLD { + rd = regCF(ins.rd) + } else { + rd = regCI(ins.rd) + } + return compressedEncoding(ins.as) | (imm>>2)<<10 | regCI(ins.rs1)<<7 | (imm&0x3)<<5 | rd<<2 +} + +// encodeCR encodes a compressed register (CR-type) instruction. +func encodeCR(ins *instruction) uint32 { + rs1, rs2 := uint32(0), uint32(0) + switch ins.as { + case ACJR, ACJALR: + rs1 = regI(ins.rs1) + case ACMV: + rs1, rs2 = regI(ins.rd), regI(ins.rs2) + case ACADD: + rs1, rs2 = regI(ins.rs1), regI(ins.rs2) + } + return compressedEncoding(ins.as) | rs1<<7 | rs2<<2 +} + +// encodeCS encodes a compressed store (CS-type) instruction. +func encodeCS(ins *instruction) uint32 { + imm := uint32(ins.imm) + if ins.as == ACSW { + // Bit order [5:3|2|6] + imm = encodeBitPattern(imm, []int{5, 4, 3, 2, 6}) + } else if ins.as == ACSD || ins.as == ACFSD { + // Bit order [5:3|7:6] + imm = encodeBitPattern(imm, []int{5, 4, 3, 7, 6}) + } + rs2 := uint32(0) + if ins.as == ACFSD { + rs2 = regCF(ins.rs2) + } else { + rs2 = regCI(ins.rs2) + } + return compressedEncoding(ins.as) | ((imm>>2)&0x7)<<10 | regCI(ins.rs1)<<7 | (imm&3)<<5 | rs2<<2 +} + +// encodeCSS encodes a compressed stack-relative store (CSS-type) instruction. +func encodeCSS(ins *instruction) uint32 { + imm := uint32(ins.imm) + if ins.as == ACSWSP { + // Bit order [5:2|7:6] + imm = encodeBitPattern(imm, []int{5, 4, 3, 2, 7, 6}) + } else if ins.as == ACSDSP || ins.as == ACFSDSP { + // Bit order [5:3|8:6] + imm = encodeBitPattern(imm, []int{5, 4, 3, 8, 7, 6}) + } + rs2 := uint32(0) + if ins.as == ACFSDSP { + rs2 = regF(ins.rs2) + } else { + rs2 = regI(ins.rs2) + } + return compressedEncoding(ins.as) | imm<<7 | rs2<<2 } // encodeR encodes an R-type RISC-V instruction. @@ -1647,37 +2148,6 @@ func encodeJ(ins *instruction) uint32 { return encodeJImmediate(imm) | rd<<7 | enc.opcode } -// encodeCBImmediate encodes an immediate for a CB-type RISC-V instruction. -func encodeCBImmediate(imm uint32) uint32 { - // Bit order - [8|4:3|7:6|2:1|5] - bits := extractBitAndShift(imm, 8, 7) - bits |= extractBitAndShift(imm, 4, 6) - bits |= extractBitAndShift(imm, 3, 5) - bits |= extractBitAndShift(imm, 7, 4) - bits |= extractBitAndShift(imm, 6, 3) - bits |= extractBitAndShift(imm, 2, 2) - bits |= extractBitAndShift(imm, 1, 1) - bits |= extractBitAndShift(imm, 5, 0) - return (bits>>5)<<10 | (bits&0x1f)<<2 -} - -// encodeCJImmediate encodes an immediate for a CJ-type RISC-V instruction. -func encodeCJImmediate(imm uint32) uint32 { - // Bit order - [11|4|9:8|10|6|7|3:1|5] - bits := extractBitAndShift(imm, 11, 10) - bits |= extractBitAndShift(imm, 4, 9) - bits |= extractBitAndShift(imm, 9, 8) - bits |= extractBitAndShift(imm, 8, 7) - bits |= extractBitAndShift(imm, 10, 6) - bits |= extractBitAndShift(imm, 6, 5) - bits |= extractBitAndShift(imm, 7, 4) - bits |= extractBitAndShift(imm, 3, 3) - bits |= extractBitAndShift(imm, 2, 2) - bits |= extractBitAndShift(imm, 1, 1) - bits |= extractBitAndShift(imm, 5, 0) - return bits << 2 -} - func encodeVset(as obj.As, rs1, rs2, rd uint32) uint32 { enc := encode(as) if enc == nil { @@ -1792,7 +2262,7 @@ func EncodeVectorType(vsew, vlmul, vtail, vmask int64) (int64, error) { type encoding struct { encode func(*instruction) uint32 // encode returns the machine code for an instruction validate func(*obj.Link, *instruction) // validate validates an instruction - length int // length of encoded instruction; 0 for pseudo-ops, 4 otherwise + length int // length of encoded instruction; 0 for pseudo-ops, 2 for compressed instructions, 4 otherwise } var ( @@ -1842,6 +2312,17 @@ var ( uEncoding = encoding{encode: encodeU, validate: validateU, length: 4} jEncoding = encoding{encode: encodeJ, validate: validateJ, length: 4} + // Compressed encodings. + caEncoding = encoding{encode: encodeCA, validate: validateCA, length: 2} + cbEncoding = encoding{encode: encodeCB, validate: validateCB, length: 2} + ciEncoding = encoding{encode: encodeCI, validate: validateCI, length: 2} + ciwEncoding = encoding{encode: encodeCIW, validate: validateCIW, length: 2} + cjEncoding = encoding{encode: encodeCJ, validate: validateCJ, length: 2} + clEncoding = encoding{encode: encodeCL, validate: validateCL, length: 2} + crEncoding = encoding{encode: encodeCR, validate: validateCR, length: 2} + csEncoding = encoding{encode: encodeCS, validate: validateCS, length: 2} + cssEncoding = encoding{encode: encodeCSS, validate: validateCSS, length: 2} + // Encodings for vector configuration setting instruction. vsetvliEncoding = encoding{encode: encodeVsetvli, validate: validateVsetvli, length: 4} vsetivliEncoding = encoding{encode: encodeVsetivli, validate: validateVsetivli, length: 4} @@ -1935,7 +2416,7 @@ var instructions = [ALAST & obj.AMask]instructionData{ ALD & obj.AMask: {enc: iIIEncoding}, ASD & obj.AMask: {enc: sIEncoding}, - // 7.1: CSR Instructions + // 6.1: CSR Instructions ACSRRC & obj.AMask: {enc: iIIEncoding, immForm: ACSRRCI}, ACSRRCI & obj.AMask: {enc: iIIEncoding}, ACSRRS & obj.AMask: {enc: iIIEncoding, immForm: ACSRRSI}, @@ -1943,11 +2424,11 @@ var instructions = [ALAST & obj.AMask]instructionData{ ACSRRW & obj.AMask: {enc: iIIEncoding, immForm: ACSRRWI}, ACSRRWI & obj.AMask: {enc: iIIEncoding}, - // 12.3: "Zicond" Extension for Integer Conditional Operations + // 11.1: Integer Conditional Operations (Zicond) ACZERONEZ & obj.AMask: {enc: rIIIEncoding, ternary: true}, ACZEROEQZ & obj.AMask: {enc: rIIIEncoding, ternary: true}, - // 13.1: Multiplication Operations + // 12.1: Multiplication Operations AMUL & obj.AMask: {enc: rIIIEncoding, ternary: true}, AMULH & obj.AMask: {enc: rIIIEncoding, ternary: true}, AMULHU & obj.AMask: {enc: rIIIEncoding, ternary: true}, @@ -1962,13 +2443,13 @@ var instructions = [ALAST & obj.AMask]instructionData{ AREMW & obj.AMask: {enc: rIIIEncoding, ternary: true}, AREMUW & obj.AMask: {enc: rIIIEncoding, ternary: true}, - // 14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc) + // 13.2: Load-Reserved/Store-Conditional Instructions (Zalrsc) ALRW & obj.AMask: {enc: rIIIEncoding}, ALRD & obj.AMask: {enc: rIIIEncoding}, ASCW & obj.AMask: {enc: rIIIEncoding}, ASCD & obj.AMask: {enc: rIIIEncoding}, - // 14.4: Atomic Memory Operations (Zaamo) + // 13.4: Atomic Memory Operations (Zaamo) AAMOSWAPW & obj.AMask: {enc: rIIIEncoding}, AAMOSWAPD & obj.AMask: {enc: rIIIEncoding}, AAMOADDW & obj.AMask: {enc: rIIIEncoding}, @@ -1988,11 +2469,11 @@ var instructions = [ALAST & obj.AMask]instructionData{ AAMOMINUW & obj.AMask: {enc: rIIIEncoding}, AAMOMINUD & obj.AMask: {enc: rIIIEncoding}, - // 20.5: Single-Precision Load and Store Instructions + // 21.5: Single-Precision Load and Store Instructions AFLW & obj.AMask: {enc: iFEncoding}, AFSW & obj.AMask: {enc: sFEncoding}, - // 20.6: Single-Precision Floating-Point Computational Instructions + // 21.6: Single-Precision Floating-Point Computational Instructions AFADDS & obj.AMask: {enc: rFFFEncoding}, AFSUBS & obj.AMask: {enc: rFFFEncoding}, AFMULS & obj.AMask: {enc: rFFFEncoding}, @@ -2005,7 +2486,7 @@ var instructions = [ALAST & obj.AMask]instructionData{ AFNMSUBS & obj.AMask: {enc: rFFFFEncoding}, AFNMADDS & obj.AMask: {enc: rFFFFEncoding}, - // 20.7: Single-Precision Floating-Point Conversion and Move Instructions + // 21.7: Single-Precision Floating-Point Conversion and Move Instructions AFCVTWS & obj.AMask: {enc: rFIEncoding}, AFCVTLS & obj.AMask: {enc: rFIEncoding}, AFCVTSW & obj.AMask: {enc: rIFEncoding}, @@ -2020,19 +2501,19 @@ var instructions = [ALAST & obj.AMask]instructionData{ AFMVXW & obj.AMask: {enc: rFIEncoding}, AFMVWX & obj.AMask: {enc: rIFEncoding}, - // 20.8: Single-Precision Floating-Point Compare Instructions + // 21.8: Single-Precision Floating-Point Compare Instructions AFEQS & obj.AMask: {enc: rFFIEncoding}, AFLTS & obj.AMask: {enc: rFFIEncoding}, AFLES & obj.AMask: {enc: rFFIEncoding}, - // 20.9: Single-Precision Floating-Point Classify Instruction + // 21.9: Single-Precision Floating-Point Classify Instruction AFCLASSS & obj.AMask: {enc: rFIEncoding}, - // 12.3: Double-Precision Load and Store Instructions + // 22.3: Double-Precision Load and Store Instructions AFLD & obj.AMask: {enc: iFEncoding}, AFSD & obj.AMask: {enc: sFEncoding}, - // 21.4: Double-Precision Floating-Point Computational Instructions + // 22.4: Double-Precision Floating-Point Computational Instructions AFADDD & obj.AMask: {enc: rFFFEncoding}, AFSUBD & obj.AMask: {enc: rFFFEncoding}, AFMULD & obj.AMask: {enc: rFFFEncoding}, @@ -2045,7 +2526,7 @@ var instructions = [ALAST & obj.AMask]instructionData{ AFNMSUBD & obj.AMask: {enc: rFFFFEncoding}, AFNMADDD & obj.AMask: {enc: rFFFFEncoding}, - // 21.5: Double-Precision Floating-Point Conversion and Move Instructions + // 22.5: Double-Precision Floating-Point Conversion and Move Instructions AFCVTWD & obj.AMask: {enc: rFIEncoding}, AFCVTLD & obj.AMask: {enc: rFIEncoding}, AFCVTDW & obj.AMask: {enc: rIFEncoding}, @@ -2062,19 +2543,76 @@ var instructions = [ALAST & obj.AMask]instructionData{ AFMVXD & obj.AMask: {enc: rFIEncoding}, AFMVDX & obj.AMask: {enc: rIFEncoding}, - // 21.6: Double-Precision Floating-Point Compare Instructions + // 22.6: Double-Precision Floating-Point Compare Instructions AFEQD & obj.AMask: {enc: rFFIEncoding}, AFLTD & obj.AMask: {enc: rFFIEncoding}, AFLED & obj.AMask: {enc: rFFIEncoding}, - // 21.7: Double-Precision Floating-Point Classify Instruction + // 22.7: Double-Precision Floating-Point Classify Instruction AFCLASSD & obj.AMask: {enc: rFIEncoding}, + // + // "C" Extension for Compressed Instructions, Version 2.0 + // + + // 28.3.1: Compressed Stack-Pointer-Based Loads and Stores + ACLWSP & obj.AMask: {enc: ciEncoding}, + ACLDSP & obj.AMask: {enc: ciEncoding}, + ACFLDSP & obj.AMask: {enc: ciEncoding}, + ACSWSP & obj.AMask: {enc: cssEncoding}, + ACSDSP & obj.AMask: {enc: cssEncoding}, + ACFSDSP & obj.AMask: {enc: cssEncoding}, + + // 28.3.2: Compressed Register-Based Loads and Stores + ACLW & obj.AMask: {enc: clEncoding}, + ACLD & obj.AMask: {enc: clEncoding}, + ACFLD & obj.AMask: {enc: clEncoding}, + ACSW & obj.AMask: {enc: csEncoding}, + ACSD & obj.AMask: {enc: csEncoding}, + ACFSD & obj.AMask: {enc: csEncoding}, + + // 28.4: Compressed Control Transfer Instructions + ACJ & obj.AMask: {enc: cjEncoding}, + ACJR & obj.AMask: {enc: crEncoding}, + ACJALR & obj.AMask: {enc: crEncoding}, + ACBEQZ & obj.AMask: {enc: cbEncoding}, + ACBNEZ & obj.AMask: {enc: cbEncoding}, + + // 28.5.1: Compressed Integer Constant-Generation Instructions + ACLI & obj.AMask: {enc: ciEncoding}, + ACLUI & obj.AMask: {enc: ciEncoding}, + + // 28.5.2: Compressed Integer Register-Immediate Operations + ACADDI & obj.AMask: {enc: ciEncoding, ternary: true}, + ACADDIW & obj.AMask: {enc: ciEncoding, ternary: true}, + ACADDI16SP & obj.AMask: {enc: ciEncoding, ternary: true}, + ACADDI4SPN & obj.AMask: {enc: ciwEncoding, ternary: true}, + ACSLLI & obj.AMask: {enc: ciEncoding, ternary: true}, + ACSRLI & obj.AMask: {enc: cbEncoding, ternary: true}, + ACSRAI & obj.AMask: {enc: cbEncoding, ternary: true}, + ACANDI & obj.AMask: {enc: cbEncoding, ternary: true}, + + // 28.5.3: Compressed Integer Register-Register Operations + ACMV & obj.AMask: {enc: crEncoding}, + ACADD & obj.AMask: {enc: crEncoding, immForm: ACADDI, ternary: true}, + ACAND & obj.AMask: {enc: caEncoding, immForm: ACANDI, ternary: true}, + ACOR & obj.AMask: {enc: caEncoding, ternary: true}, + ACXOR & obj.AMask: {enc: caEncoding, ternary: true}, + ACSUB & obj.AMask: {enc: caEncoding, ternary: true}, + ACADDW & obj.AMask: {enc: caEncoding, immForm: ACADDIW, ternary: true}, + ACSUBW & obj.AMask: {enc: caEncoding, ternary: true}, + + // 28.5.5: Compressed NOP Instruction + ACNOP & obj.AMask: {enc: ciEncoding}, + + // 28.5.6: Compressed Breakpoint Instruction + ACEBREAK & obj.AMask: {enc: crEncoding}, + // // "B" Extension for Bit Manipulation, Version 1.0.0 // - // 28.4.1: Address Generation Instructions (Zba) + // 30.2: Address Generation Instructions (Zba) AADDUW & obj.AMask: {enc: rIIIEncoding, ternary: true}, ASH1ADD & obj.AMask: {enc: rIIIEncoding, ternary: true}, ASH1ADDUW & obj.AMask: {enc: rIIIEncoding, ternary: true}, @@ -2084,7 +2622,7 @@ var instructions = [ALAST & obj.AMask]instructionData{ ASH3ADDUW & obj.AMask: {enc: rIIIEncoding, ternary: true}, ASLLIUW & obj.AMask: {enc: iIIEncoding, ternary: true}, - // 28.4.2: Basic Bit Manipulation (Zbb) + // 30.3: Basic Bit Manipulation (Zbb) AANDN & obj.AMask: {enc: rIIIEncoding, ternary: true}, ACLZ & obj.AMask: {enc: rIIEncoding}, ACLZW & obj.AMask: {enc: rIIEncoding}, @@ -2101,8 +2639,6 @@ var instructions = [ALAST & obj.AMask]instructionData{ ASEXTH & obj.AMask: {enc: rIIEncoding}, AXNOR & obj.AMask: {enc: rIIIEncoding, ternary: true}, AZEXTH & obj.AMask: {enc: rIIEncoding}, - - // 28.4.3: Bitwise Rotation (Zbb) AROL & obj.AMask: {enc: rIIIEncoding, ternary: true}, AROLW & obj.AMask: {enc: rIIIEncoding, ternary: true}, AROR & obj.AMask: {enc: rIIIEncoding, immForm: ARORI, ternary: true}, @@ -2112,7 +2648,12 @@ var instructions = [ALAST & obj.AMask]instructionData{ AORCB & obj.AMask: {enc: rIIEncoding}, AREV8 & obj.AMask: {enc: rIIEncoding}, - // 28.4.4: Single-bit Instructions (Zbs) + // 30.4: Carry-less Multiplication (Zbc) + ACLMUL & obj.AMask: {enc: rIIIEncoding, ternary: true}, + ACLMULH & obj.AMask: {enc: rIIIEncoding, ternary: true}, + ACLMULR & obj.AMask: {enc: rIIIEncoding, ternary: true}, + + // 30.5: Single-bit Instructions (Zbs) ABCLR & obj.AMask: {enc: rIIIEncoding, immForm: ABCLRI, ternary: true}, ABCLRI & obj.AMask: {enc: iIIEncoding, ternary: true}, ABEXT & obj.AMask: {enc: rIIIEncoding, immForm: ABEXTI, ternary: true}, @@ -2143,7 +2684,7 @@ var instructions = [ALAST & obj.AMask]instructionData{ AVLMV & obj.AMask: {enc: iVEncoding}, AVSMV & obj.AMask: {enc: sVEncoding}, - // 31.7.5: Vector Strided Instructions + // 31.7.5: Vector Constant-Stride Instructions AVLSE8V & obj.AMask: {enc: iIIVEncoding}, AVLSE16V & obj.AMask: {enc: iIIVEncoding}, AVLSE32V & obj.AMask: {enc: iIIVEncoding}, @@ -2171,153 +2712,157 @@ var instructions = [ALAST & obj.AMask]instructionData{ AVSOXEI32V & obj.AMask: {enc: sVIVEncoding}, AVSOXEI64V & obj.AMask: {enc: sVIVEncoding}, - // 31.7.7: Unit-stride Fault-Only-First Loads + // 31.7.7: Vector Unit-Stride Fault-Only-First Loads AVLE8FFV & obj.AMask: {enc: iVEncoding}, AVLE16FFV & obj.AMask: {enc: iVEncoding}, AVLE32FFV & obj.AMask: {enc: iVEncoding}, AVLE64FFV & obj.AMask: {enc: iVEncoding}, - // 31.7.8: Vector Load/Store Segment Instructions - AVLSEG2E8V & obj.AMask: {enc: iVEncoding}, - AVLSEG3E8V & obj.AMask: {enc: iVEncoding}, - AVLSEG4E8V & obj.AMask: {enc: iVEncoding}, - AVLSEG5E8V & obj.AMask: {enc: iVEncoding}, - AVLSEG6E8V & obj.AMask: {enc: iVEncoding}, - AVLSEG7E8V & obj.AMask: {enc: iVEncoding}, - AVLSEG8E8V & obj.AMask: {enc: iVEncoding}, - AVLSEG2E16V & obj.AMask: {enc: iVEncoding}, - AVLSEG3E16V & obj.AMask: {enc: iVEncoding}, - AVLSEG4E16V & obj.AMask: {enc: iVEncoding}, - AVLSEG5E16V & obj.AMask: {enc: iVEncoding}, - AVLSEG6E16V & obj.AMask: {enc: iVEncoding}, - AVLSEG7E16V & obj.AMask: {enc: iVEncoding}, - AVLSEG8E16V & obj.AMask: {enc: iVEncoding}, - AVLSEG2E32V & obj.AMask: {enc: iVEncoding}, - AVLSEG3E32V & obj.AMask: {enc: iVEncoding}, - AVLSEG4E32V & obj.AMask: {enc: iVEncoding}, - AVLSEG5E32V & obj.AMask: {enc: iVEncoding}, - AVLSEG6E32V & obj.AMask: {enc: iVEncoding}, - AVLSEG7E32V & obj.AMask: {enc: iVEncoding}, - AVLSEG8E32V & obj.AMask: {enc: iVEncoding}, - AVLSEG2E64V & obj.AMask: {enc: iVEncoding}, - AVLSEG3E64V & obj.AMask: {enc: iVEncoding}, - AVLSEG4E64V & obj.AMask: {enc: iVEncoding}, - AVLSEG5E64V & obj.AMask: {enc: iVEncoding}, - AVLSEG6E64V & obj.AMask: {enc: iVEncoding}, - AVLSEG7E64V & obj.AMask: {enc: iVEncoding}, - AVLSEG8E64V & obj.AMask: {enc: iVEncoding}, - AVSSEG2E8V & obj.AMask: {enc: sVEncoding}, - AVSSEG3E8V & obj.AMask: {enc: sVEncoding}, - AVSSEG4E8V & obj.AMask: {enc: sVEncoding}, - AVSSEG5E8V & obj.AMask: {enc: sVEncoding}, - AVSSEG6E8V & obj.AMask: {enc: sVEncoding}, - AVSSEG7E8V & obj.AMask: {enc: sVEncoding}, - AVSSEG8E8V & obj.AMask: {enc: sVEncoding}, - AVSSEG2E16V & obj.AMask: {enc: sVEncoding}, - AVSSEG3E16V & obj.AMask: {enc: sVEncoding}, - AVSSEG4E16V & obj.AMask: {enc: sVEncoding}, - AVSSEG5E16V & obj.AMask: {enc: sVEncoding}, - AVSSEG6E16V & obj.AMask: {enc: sVEncoding}, - AVSSEG7E16V & obj.AMask: {enc: sVEncoding}, - AVSSEG8E16V & obj.AMask: {enc: sVEncoding}, - AVSSEG2E32V & obj.AMask: {enc: sVEncoding}, - AVSSEG3E32V & obj.AMask: {enc: sVEncoding}, - AVSSEG4E32V & obj.AMask: {enc: sVEncoding}, - AVSSEG5E32V & obj.AMask: {enc: sVEncoding}, - AVSSEG6E32V & obj.AMask: {enc: sVEncoding}, - AVSSEG7E32V & obj.AMask: {enc: sVEncoding}, - AVSSEG8E32V & obj.AMask: {enc: sVEncoding}, - AVSSEG2E64V & obj.AMask: {enc: sVEncoding}, - AVSSEG3E64V & obj.AMask: {enc: sVEncoding}, - AVSSEG4E64V & obj.AMask: {enc: sVEncoding}, - AVSSEG5E64V & obj.AMask: {enc: sVEncoding}, - AVSSEG6E64V & obj.AMask: {enc: sVEncoding}, - AVSSEG7E64V & obj.AMask: {enc: sVEncoding}, - AVSSEG8E64V & obj.AMask: {enc: sVEncoding}, - AVLSEG2E8FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG3E8FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG4E8FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG5E8FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG6E8FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG7E8FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG8E8FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG2E16FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG3E16FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG4E16FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG5E16FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG6E16FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG7E16FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG8E16FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG2E32FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG3E32FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG4E32FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG5E32FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG6E32FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG7E32FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG8E32FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG2E64FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG3E64FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG4E64FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG5E64FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG6E64FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG7E64FFV & obj.AMask: {enc: iVEncoding}, - AVLSEG8E64FFV & obj.AMask: {enc: iVEncoding}, - AVLSSEG2E8V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG3E8V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG4E8V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG5E8V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG6E8V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG7E8V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG8E8V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG2E16V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG3E16V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG4E16V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG5E16V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG6E16V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG7E16V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG8E16V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG2E32V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG3E32V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG4E32V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG5E32V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG6E32V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG7E32V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG8E32V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG2E64V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG3E64V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG4E64V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG5E64V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG6E64V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG7E64V & obj.AMask: {enc: iIIVEncoding}, - AVLSSEG8E64V & obj.AMask: {enc: iIIVEncoding}, - AVSSSEG2E8V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG3E8V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG4E8V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG5E8V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG6E8V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG7E8V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG8E8V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG2E16V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG3E16V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG4E16V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG5E16V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG6E16V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG7E16V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG8E16V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG2E32V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG3E32V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG4E32V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG5E32V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG6E32V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG7E32V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG8E32V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG2E64V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG3E64V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG4E64V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG5E64V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG6E64V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG7E64V & obj.AMask: {enc: sVIIEncoding}, - AVSSSEG8E64V & obj.AMask: {enc: sVIIEncoding}, + // 31.7.8.1: Vector Unit-Stride Segment Loads and Stores + AVLSEG2E8V & obj.AMask: {enc: iVEncoding}, + AVLSEG3E8V & obj.AMask: {enc: iVEncoding}, + AVLSEG4E8V & obj.AMask: {enc: iVEncoding}, + AVLSEG5E8V & obj.AMask: {enc: iVEncoding}, + AVLSEG6E8V & obj.AMask: {enc: iVEncoding}, + AVLSEG7E8V & obj.AMask: {enc: iVEncoding}, + AVLSEG8E8V & obj.AMask: {enc: iVEncoding}, + AVLSEG2E16V & obj.AMask: {enc: iVEncoding}, + AVLSEG3E16V & obj.AMask: {enc: iVEncoding}, + AVLSEG4E16V & obj.AMask: {enc: iVEncoding}, + AVLSEG5E16V & obj.AMask: {enc: iVEncoding}, + AVLSEG6E16V & obj.AMask: {enc: iVEncoding}, + AVLSEG7E16V & obj.AMask: {enc: iVEncoding}, + AVLSEG8E16V & obj.AMask: {enc: iVEncoding}, + AVLSEG2E32V & obj.AMask: {enc: iVEncoding}, + AVLSEG3E32V & obj.AMask: {enc: iVEncoding}, + AVLSEG4E32V & obj.AMask: {enc: iVEncoding}, + AVLSEG5E32V & obj.AMask: {enc: iVEncoding}, + AVLSEG6E32V & obj.AMask: {enc: iVEncoding}, + AVLSEG7E32V & obj.AMask: {enc: iVEncoding}, + AVLSEG8E32V & obj.AMask: {enc: iVEncoding}, + AVLSEG2E64V & obj.AMask: {enc: iVEncoding}, + AVLSEG3E64V & obj.AMask: {enc: iVEncoding}, + AVLSEG4E64V & obj.AMask: {enc: iVEncoding}, + AVLSEG5E64V & obj.AMask: {enc: iVEncoding}, + AVLSEG6E64V & obj.AMask: {enc: iVEncoding}, + AVLSEG7E64V & obj.AMask: {enc: iVEncoding}, + AVLSEG8E64V & obj.AMask: {enc: iVEncoding}, + AVSSEG2E8V & obj.AMask: {enc: sVEncoding}, + AVSSEG3E8V & obj.AMask: {enc: sVEncoding}, + AVSSEG4E8V & obj.AMask: {enc: sVEncoding}, + AVSSEG5E8V & obj.AMask: {enc: sVEncoding}, + AVSSEG6E8V & obj.AMask: {enc: sVEncoding}, + AVSSEG7E8V & obj.AMask: {enc: sVEncoding}, + AVSSEG8E8V & obj.AMask: {enc: sVEncoding}, + AVSSEG2E16V & obj.AMask: {enc: sVEncoding}, + AVSSEG3E16V & obj.AMask: {enc: sVEncoding}, + AVSSEG4E16V & obj.AMask: {enc: sVEncoding}, + AVSSEG5E16V & obj.AMask: {enc: sVEncoding}, + AVSSEG6E16V & obj.AMask: {enc: sVEncoding}, + AVSSEG7E16V & obj.AMask: {enc: sVEncoding}, + AVSSEG8E16V & obj.AMask: {enc: sVEncoding}, + AVSSEG2E32V & obj.AMask: {enc: sVEncoding}, + AVSSEG3E32V & obj.AMask: {enc: sVEncoding}, + AVSSEG4E32V & obj.AMask: {enc: sVEncoding}, + AVSSEG5E32V & obj.AMask: {enc: sVEncoding}, + AVSSEG6E32V & obj.AMask: {enc: sVEncoding}, + AVSSEG7E32V & obj.AMask: {enc: sVEncoding}, + AVSSEG8E32V & obj.AMask: {enc: sVEncoding}, + AVSSEG2E64V & obj.AMask: {enc: sVEncoding}, + AVSSEG3E64V & obj.AMask: {enc: sVEncoding}, + AVSSEG4E64V & obj.AMask: {enc: sVEncoding}, + AVSSEG5E64V & obj.AMask: {enc: sVEncoding}, + AVSSEG6E64V & obj.AMask: {enc: sVEncoding}, + AVSSEG7E64V & obj.AMask: {enc: sVEncoding}, + AVSSEG8E64V & obj.AMask: {enc: sVEncoding}, + AVLSEG2E8FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG3E8FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG4E8FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG5E8FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG6E8FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG7E8FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG8E8FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG2E16FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG3E16FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG4E16FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG5E16FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG6E16FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG7E16FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG8E16FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG2E32FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG3E32FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG4E32FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG5E32FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG6E32FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG7E32FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG8E32FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG2E64FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG3E64FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG4E64FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG5E64FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG6E64FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG7E64FFV & obj.AMask: {enc: iVEncoding}, + AVLSEG8E64FFV & obj.AMask: {enc: iVEncoding}, + + // 31.7.8.2: Vector Constant-Stride Segment Loads and Stores + AVLSSEG2E8V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG3E8V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG4E8V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG5E8V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG6E8V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG7E8V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG8E8V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG2E16V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG3E16V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG4E16V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG5E16V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG6E16V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG7E16V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG8E16V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG2E32V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG3E32V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG4E32V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG5E32V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG6E32V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG7E32V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG8E32V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG2E64V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG3E64V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG4E64V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG5E64V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG6E64V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG7E64V & obj.AMask: {enc: iIIVEncoding}, + AVLSSEG8E64V & obj.AMask: {enc: iIIVEncoding}, + AVSSSEG2E8V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG3E8V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG4E8V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG5E8V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG6E8V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG7E8V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG8E8V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG2E16V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG3E16V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG4E16V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG5E16V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG6E16V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG7E16V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG8E16V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG2E32V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG3E32V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG4E32V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG5E32V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG6E32V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG7E32V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG8E32V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG2E64V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG3E64V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG4E64V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG5E64V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG6E64V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG7E64V & obj.AMask: {enc: sVIIEncoding}, + AVSSSEG8E64V & obj.AMask: {enc: sVIIEncoding}, + + // 31.7.8.3: Vector Indexed Segment Loads and Stores AVLOXSEG2EI8V & obj.AMask: {enc: iVIVEncoding}, AVLOXSEG3EI8V & obj.AMask: {enc: iVIVEncoding}, AVLOXSEG4EI8V & obj.AMask: {enc: iVIVEncoding}, @@ -2867,6 +3412,30 @@ var instructions = [ALAST & obj.AMask]instructionData{ AVMV4RV & obj.AMask: {enc: rVVEncoding}, AVMV8RV & obj.AMask: {enc: rVVEncoding}, + // 33.2.1: Vector Basic Bit-manipulation + AVANDNVV & obj.AMask: {enc: rVVVEncoding}, + AVANDNVX & obj.AMask: {enc: rVIVEncoding}, + AVBREVV & obj.AMask: {enc: rVVEncoding}, + AVBREV8V & obj.AMask: {enc: rVVEncoding}, + AVREV8V & obj.AMask: {enc: rVVEncoding}, + AVCLZV & obj.AMask: {enc: rVVEncoding}, + AVCTZV & obj.AMask: {enc: rVVEncoding}, + AVCPOPV & obj.AMask: {enc: rVVEncoding}, + AVROLVV & obj.AMask: {enc: rVVVEncoding}, + AVROLVX & obj.AMask: {enc: rVIVEncoding}, + AVRORVV & obj.AMask: {enc: rVVVEncoding}, + AVRORVX & obj.AMask: {enc: rVIVEncoding}, + AVRORVI & obj.AMask: {enc: rVVuEncoding}, + AVWSLLVV & obj.AMask: {enc: rVVVEncoding}, + AVWSLLVX & obj.AMask: {enc: rVIVEncoding}, + AVWSLLVI & obj.AMask: {enc: rVVuEncoding}, + + // 33.2.2: Vector Carryless Multiplication + AVCLMULVV & obj.AMask: {enc: rVVVEncoding}, + AVCLMULVX & obj.AMask: {enc: rVIVEncoding}, + AVCLMULHVV & obj.AMask: {enc: rVVVEncoding}, + AVCLMULHVX & obj.AMask: {enc: rVIVEncoding}, + // // Privileged ISA // @@ -2923,24 +3492,44 @@ func splitShiftConst(v int64) (imm int64, lsh int, rsh int, ok bool) { // See if we can reconstruct this value from a small negative constant. rsh = bits.LeadingZeros64(uint64(v)) ones := bits.OnesCount64((uint64(v) >> lsh) >> 11) - c = signExtend(1<<11|((v>>lsh)&0x7ff), 12) if rsh+ones+lsh+11 == 64 { + c = signExtend(1<<11|((v>>lsh)&0x7ff), 12) if lsh > 0 || c != -1 { lsh += rsh } return c, lsh, rsh, true } + // See if we can reconstruct this value from a zero extended signed + // 32 bit integer. This will require four instructions on rva20u64 + // and three instructions on rva22u64 or higher. + if int64(uint32(c)) == c { + c = int64(int32(c)) + lsh, rsh = 32, 32-lsh + return c, lsh, rsh, true + } + return 0, 0, 0, false } // isShiftConst indicates whether a constant can be represented as a signed -// 32 bit integer that is left shifted. +// 32 bit integer that is left and/or right shifted. func isShiftConst(v int64) bool { _, lsh, rsh, ok := splitShiftConst(v) return ok && (lsh > 0 || rsh > 0) } +// isMaterialisableConst indicates whether a constant can be materialised +// via a small sequence of instructions. +func isMaterialisableConst(v int64) bool { + // Signed 32 bit value that can be constructed with one or two instructions + // (ADDIW or LUI+ADDIW). + if int64(int32(v)) == v { + return true + } + return isShiftConst(v) +} + type instruction struct { p *obj.Prog // Prog that instruction is for as obj.As // Assembler opcode @@ -2996,6 +3585,157 @@ func (ins *instruction) usesRegTmp() bool { return ins.rd == REG_TMP || ins.rs1 == REG_TMP || ins.rs2 == REG_TMP } +func (ins *instruction) compress() { + switch ins.as { + case ALW: + if ins.rd != REG_X0 && ins.rs1 == REG_SP && isScaledImmU(ins.imm, 8, 4) { + ins.as, ins.rs1, ins.rs2 = ACLWSP, obj.REG_NONE, ins.rs1 + } else if isIntPrimeReg(ins.rd) && isIntPrimeReg(ins.rs1) && isScaledImmU(ins.imm, 7, 4) { + ins.as = ACLW + } + + case ALD: + if ins.rs1 == REG_SP && ins.rd != REG_X0 && isScaledImmU(ins.imm, 9, 8) { + ins.as, ins.rs1, ins.rs2 = ACLDSP, obj.REG_NONE, ins.rs1 + } else if isIntPrimeReg(ins.rd) && isIntPrimeReg(ins.rs1) && isScaledImmU(ins.imm, 8, 8) { + ins.as = ACLD + } + + case AFLD: + if ins.rs1 == REG_SP && isScaledImmU(ins.imm, 9, 8) { + ins.as, ins.rs1, ins.rs2 = ACFLDSP, obj.REG_NONE, ins.rs1 + } else if isFloatPrimeReg(ins.rd) && isIntPrimeReg(ins.rs1) && isScaledImmU(ins.imm, 8, 8) { + ins.as = ACFLD + } + + case ASW: + if ins.rd == REG_SP && isScaledImmU(ins.imm, 8, 4) { + ins.as, ins.rs1, ins.rs2 = ACSWSP, obj.REG_NONE, ins.rs1 + } else if isIntPrimeReg(ins.rd) && isIntPrimeReg(ins.rs1) && isScaledImmU(ins.imm, 7, 4) { + ins.as, ins.rd, ins.rs1, ins.rs2 = ACSW, obj.REG_NONE, ins.rd, ins.rs1 + } + + case ASD: + if ins.rd == REG_SP && isScaledImmU(ins.imm, 9, 8) { + ins.as, ins.rs1, ins.rs2 = ACSDSP, obj.REG_NONE, ins.rs1 + } else if isIntPrimeReg(ins.rd) && isIntPrimeReg(ins.rs1) && isScaledImmU(ins.imm, 8, 8) { + ins.as, ins.rd, ins.rs1, ins.rs2 = ACSD, obj.REG_NONE, ins.rd, ins.rs1 + } + + case AFSD: + if ins.rd == REG_SP && isScaledImmU(ins.imm, 9, 8) { + ins.as, ins.rs1, ins.rs2 = ACFSDSP, obj.REG_NONE, ins.rs1 + } else if isIntPrimeReg(ins.rd) && isFloatPrimeReg(ins.rs1) && isScaledImmU(ins.imm, 8, 8) { + ins.as, ins.rd, ins.rs1, ins.rs2 = ACFSD, obj.REG_NONE, ins.rd, ins.rs1 + } + + case AADDI: + if ins.rd == REG_SP && ins.rs1 == REG_SP && ins.imm != 0 && isScaledImmI(ins.imm, 10, 16) { + ins.as = ACADDI16SP + } else if ins.rd != REG_X0 && ins.rd == ins.rs1 && ins.imm != 0 && immIFits(ins.imm, 6) == nil { + ins.as = ACADDI + } else if isIntPrimeReg(ins.rd) && ins.rs1 == REG_SP && ins.imm != 0 && isScaledImmU(ins.imm, 10, 4) { + ins.as = ACADDI4SPN + } else if ins.rd != REG_X0 && ins.rs1 == REG_X0 && immIFits(ins.imm, 6) == nil { + ins.as, ins.rs1 = ACLI, obj.REG_NONE + } else if ins.rd != REG_X0 && ins.rs1 != REG_X0 && ins.imm == 0 { + ins.as, ins.rs1, ins.rs2 = ACMV, obj.REG_NONE, ins.rs1 + } else if ins.rd == REG_X0 && ins.rs1 == REG_X0 && ins.imm == 0 { + ins.as, ins.rs1 = ACNOP, ins.rd + } + + case AADDIW: + if ins.rd == ins.rs1 && immIFits(ins.imm, 6) == nil { + ins.as = ACADDIW + } + + case ALUI: + if ins.rd != REG_X0 && ins.rd != REG_SP && ins.imm != 0 && immIFits(ins.imm, 6) == nil { + ins.as = ACLUI + } + + case ASLLI: + if ins.rd != REG_X0 && ins.rd == ins.rs1 && ins.imm != 0 { + ins.as = ACSLLI + } + + case ASRLI: + if isIntPrimeReg(ins.rd) && ins.rd == ins.rs1 && ins.imm != 0 { + ins.as = ACSRLI + } + + case ASRAI: + if isIntPrimeReg(ins.rd) && ins.rd == ins.rs1 && ins.imm != 0 { + ins.as = ACSRAI + } + + case AANDI: + if isIntPrimeReg(ins.rd) && ins.rd == ins.rs1 && immIFits(ins.imm, 6) == nil { + ins.as = ACANDI + } + + case AADD: + if ins.rd != REG_X0 && ins.rd == ins.rs1 && ins.rs2 != REG_X0 { + ins.as = ACADD + } else if ins.rd != REG_X0 && ins.rd == ins.rs2 && ins.rs1 != REG_X0 { + ins.as, ins.rs1, ins.rs2 = ACADD, ins.rs2, ins.rs1 + } else if ins.rd != REG_X0 && ins.rs1 == REG_X0 && ins.rs2 != REG_X0 { + ins.as = ACMV + } + + case AADDW: + if isIntPrimeReg(ins.rd) && ins.rd == ins.rs1 && isIntPrimeReg(ins.rs2) { + ins.as = ACADDW + } else if isIntPrimeReg(ins.rd) && isIntPrimeReg(ins.rs1) && ins.rd == ins.rs2 { + ins.as, ins.rs1, ins.rs2 = ACADDW, ins.rs2, ins.rs1 + } + + case ASUB: + if isIntPrimeReg(ins.rd) && ins.rd == ins.rs1 && isIntPrimeReg(ins.rs2) { + ins.as = ACSUB + } + + case ASUBW: + if isIntPrimeReg(ins.rd) && ins.rd == ins.rs1 && isIntPrimeReg(ins.rs2) { + ins.as = ACSUBW + } + + case AAND: + if isIntPrimeReg(ins.rd) && ins.rd == ins.rs1 && isIntPrimeReg(ins.rs2) { + ins.as = ACAND + } else if isIntPrimeReg(ins.rd) && isIntPrimeReg(ins.rs1) && ins.rd == ins.rs2 { + ins.as, ins.rs1, ins.rs2 = ACAND, ins.rs2, ins.rs1 + } + + case AOR: + if isIntPrimeReg(ins.rd) && ins.rd == ins.rs1 && isIntPrimeReg(ins.rs2) { + ins.as = ACOR + } else if isIntPrimeReg(ins.rd) && isIntPrimeReg(ins.rs1) && ins.rd == ins.rs2 { + ins.as, ins.rs1, ins.rs2 = ACOR, ins.rs2, ins.rs1 + } + + case AXOR: + if isIntPrimeReg(ins.rd) && ins.rd == ins.rs1 && isIntPrimeReg(ins.rs2) { + ins.as = ACXOR + } else if isIntPrimeReg(ins.rd) && isIntPrimeReg(ins.rs1) && ins.rd == ins.rs2 { + ins.as, ins.rs1, ins.rs2 = ACXOR, ins.rs2, ins.rs1 + } + + case AEBREAK: + ins.as, ins.rd, ins.rs1 = ACEBREAK, obj.REG_NONE, obj.REG_NONE + } +} + +func encodeFenceOperand(a *obj.Addr) (uint32, bool) { + if a.Type == obj.TYPE_SPECIAL && a.Offset > int64(SPOP_FENCE_BEGIN) && a.Offset < int64(SPOP_FENCE_END) { + return SpecialOperand(a.Offset).encode(), true + } + if a.Type == obj.TYPE_NONE { + return SPOP_FENCE_IORW.encode(), true + } + return 0, false +} + // instructionForProg returns the default *obj.Prog to instruction mapping. func instructionForProg(p *obj.Prog) *instruction { ins := &instruction{ @@ -3193,6 +3933,81 @@ func instructionsForTLSStore(p *obj.Prog) []*instruction { return instructionsForTLS(p, ins) } +func instructionsForMOVConst(p *obj.Prog) []*instruction { + ins := instructionForProg(p) + inss := []*instruction{ins} + + // For constants larger than 32 bits in size that have trailing zeros, + // use the value with the trailing zeros removed and then use a SLLI + // instruction to restore the original constant. + // + // For example: + // MOV $0x8000000000000000, X10 + // becomes + // MOV $1, X10 + // SLLI $63, X10, X10 + // + // Similarly, we can construct large constants that have a consecutive + // sequence of ones from a small negative constant, with a right and/or + // left shift. + // + // For example: + // MOV $0x000fffffffffffda, X10 + // becomes + // MOV $-19, X10 + // SLLI $13, X10 + // SRLI $12, X10 + // + var insSLLI, insSRLI, insMOVWU *instruction + if err := immIFits(ins.imm, 32); err != nil { + if c, lsh, rsh, ok := splitShiftConst(ins.imm); ok { + ins.imm = c + if buildcfg.GORISCV64 >= 22 && lsh == 32 && rsh == 32 { + insMOVWU = &instruction{as: AADDUW, rd: ins.rd, rs1: ins.rd, rs2: REG_ZERO} + lsh, rsh = 0, 0 + } + if lsh > 0 { + insSLLI = &instruction{as: ASLLI, rd: ins.rd, rs1: ins.rd, imm: int64(lsh)} + } + if rsh > 0 { + insSRLI = &instruction{as: ASRLI, rd: ins.rd, rs1: ins.rd, imm: int64(rsh)} + } + } + } + + low, high, err := Split32BitImmediate(ins.imm) + if err != nil { + p.Ctxt.Diag("%v: constant %d too large: %v", p, ins.imm, err) + return nil + } + + // MOV $c, R -> ADD $c, ZERO, R + ins.as, ins.rs1, ins.rs2, ins.imm = AADDI, REG_ZERO, obj.REG_NONE, low + + // LUI is only necessary if the constant does not fit in 12 bits. + if high != 0 { + // LUI top20bits(c), R + // ADD bottom12bits(c), R, R + insLUI := &instruction{as: ALUI, rd: ins.rd, imm: high} + inss = []*instruction{insLUI} + if low != 0 { + ins.as, ins.rs1 = AADDIW, ins.rd + inss = append(inss, ins) + } + } + if insMOVWU != nil { + inss = append(inss, insMOVWU) + } + if insSLLI != nil { + inss = append(inss, insSLLI) + } + if insSRLI != nil { + inss = append(inss, insSRLI) + } + + return inss +} + // instructionsForMOV returns the machine instructions for an *obj.Prog that // uses a MOV pseudo-instruction. func instructionsForMOV(p *obj.Prog) []*instruction { @@ -3211,67 +4026,7 @@ func instructionsForMOV(p *obj.Prog) []*instruction { p.Ctxt.Diag("%v: unsupported constant load", p) return nil } - - // For constants larger than 32 bits in size that have trailing zeros, - // use the value with the trailing zeros removed and then use a SLLI - // instruction to restore the original constant. - // - // For example: - // MOV $0x8000000000000000, X10 - // becomes - // MOV $1, X10 - // SLLI $63, X10, X10 - // - // Similarly, we can construct large constants that have a consecutive - // sequence of ones from a small negative constant, with a right and/or - // left shift. - // - // For example: - // MOV $0x000fffffffffffda, X10 - // becomes - // MOV $-19, X10 - // SLLI $13, X10 - // SRLI $12, X10 - // - var insSLLI, insSRLI *instruction - if err := immIFits(ins.imm, 32); err != nil { - if c, lsh, rsh, ok := splitShiftConst(ins.imm); ok { - ins.imm = c - if lsh > 0 { - insSLLI = &instruction{as: ASLLI, rd: ins.rd, rs1: ins.rd, imm: int64(lsh)} - } - if rsh > 0 { - insSRLI = &instruction{as: ASRLI, rd: ins.rd, rs1: ins.rd, imm: int64(rsh)} - } - } - } - - low, high, err := Split32BitImmediate(ins.imm) - if err != nil { - p.Ctxt.Diag("%v: constant %d too large: %v", p, ins.imm, err) - return nil - } - - // MOV $c, R -> ADD $c, ZERO, R - ins.as, ins.rs1, ins.rs2, ins.imm = AADDI, REG_ZERO, obj.REG_NONE, low - - // LUI is only necessary if the constant does not fit in 12 bits. - if high != 0 { - // LUI top20bits(c), R - // ADD bottom12bits(c), R, R - insLUI := &instruction{as: ALUI, rd: ins.rd, imm: high} - inss = []*instruction{insLUI} - if low != 0 { - ins.as, ins.rs1 = AADDIW, ins.rd - inss = append(inss, ins) - } - } - if insSLLI != nil { - inss = append(inss, insSLLI) - } - if insSRLI != nil { - inss = append(inss, insSRLI) - } + return instructionsForMOVConst(p) case p.From.Type == obj.TYPE_CONST && p.To.Type != obj.TYPE_REG: p.Ctxt.Diag("%v: constant load must target register", p) @@ -3538,7 +4293,7 @@ func instructionsForMinMax(p *obj.Prog, ins *instruction) []*instruction { } // instructionsForProg returns the machine instructions for an *obj.Prog. -func instructionsForProg(p *obj.Prog) []*instruction { +func instructionsForProg(p *obj.Prog, compress bool) []*instruction { ins := instructionForProg(p) inss := []*instruction{ins} @@ -3553,7 +4308,7 @@ func instructionsForProg(p *obj.Prog) []*instruction { } switch ins.as { - case AJAL, AJALR: + case ACJALR, AJAL, AJALR: ins.rd, ins.rs1, ins.rs2 = uint32(p.From.Reg), uint32(p.To.Reg), obj.REG_NONE ins.imm = p.To.Offset @@ -3633,12 +4388,41 @@ func instructionsForProg(p *obj.Prog) []*instruction { ins.imm = -1022 } - case ACSRRC, ACSRRCI, ACSRRS, ACSRRSI, ACSRRW, ACSRRWI: + case ACSRC, ACSRRC, ACSRCI, ACSRRCI, ACSRR, ACSRS, ACSRSI, ACSRRS, ACSRRSI, ACSRRW, ACSRRWI, ACSRW, ACSRWI: + switch { + case ins.as == ACSRCI || (ins.as == ACSRC && p.From.Type == obj.TYPE_CONST): + ins.as = ACSRRCI + ins.rd = REG_ZERO + case ins.as == ACSRC: + ins.as = ACSRRC + ins.rd = REG_ZERO + case ins.as == ACSRSI || (ins.as == ACSRS && p.From.Type == obj.TYPE_CONST): + ins.as = ACSRRSI + ins.rd = REG_ZERO + case ins.as == ACSRS: + ins.as = ACSRRS + ins.rd = REG_ZERO + case ins.as == ACSRWI || (ins.as == ACSRW && p.From.Type == obj.TYPE_CONST): + ins.as = ACSRRWI + ins.rd = REG_ZERO + case ins.as == ACSRW: + ins.as = ACSRRW + ins.rd = REG_ZERO + default: + if p.To.Type != obj.TYPE_REG { + p.Ctxt.Diag("%v: needs an integer register output", p) + return nil + } + } + if len(p.RestArgs) == 0 || p.RestArgs[0].Type != obj.TYPE_SPECIAL { p.Ctxt.Diag("%v: missing CSR name", p) return nil } - if p.From.Type == obj.TYPE_CONST { + if ins.as == ACSRR { + ins.as = ACSRRS + ins.rs1 = REG_ZERO + } else if p.From.Type == obj.TYPE_CONST { imm := p.From.Offset if imm < 0 || imm >= 32 { p.Ctxt.Diag("%v: immediate out of range 0 to 31", p) @@ -3651,10 +4435,6 @@ func instructionsForProg(p *obj.Prog) []*instruction { p.Ctxt.Diag("%v: integer register or immediate expected for 1st operand", p) return nil } - if p.To.Type != obj.TYPE_REG { - p.Ctxt.Diag("%v: needs an integer register output", p) - return nil - } csrNum := SpecialOperand(p.RestArgs[0].Offset).encode() if csrNum >= 1<<12 { p.Ctxt.Diag("%v: unknown CSR", p) @@ -3672,7 +4452,29 @@ func instructionsForProg(p *obj.Prog) []*instruction { case AFENCE: ins.rd, ins.rs1, ins.rs2 = REG_ZERO, REG_ZERO, obj.REG_NONE - ins.imm = 0x0ff + if p.Scond == fenceTsoSuffixBit { + if p.From.Type != obj.TYPE_NONE || p.To.Type != obj.TYPE_NONE { + p.Ctxt.Diag("FENCE.TSO must not have operands: %v", p) + } + // FENCE.TSO is encoded as a FENCE instruction with fm=1000(8), pred=RW(3), succ=RW(3) + ins.imm = signExtend((8<<8)|(3<<4)|3, 12) + } else { + pred, ok := encodeFenceOperand(&p.From) + if !ok { + p.Ctxt.Diag("invalid FENCE predecessor operand: %v", p) + } + succ, ok := encodeFenceOperand(&p.To) + if !ok { + p.Ctxt.Diag("invalid FENCE successor operand: %v", p) + } + // FENCE pred, succ + // pred(4 bits), succ(4 bits) + ins.imm = int64((pred << 4) | succ) + } + + case APAUSE: + ins.as, ins.rd, ins.rs1, ins.rs2 = AFENCE, REG_ZERO, REG_ZERO, obj.REG_NONE + ins.imm = 0x010 case AFCVTWS, AFCVTLS, AFCVTWUS, AFCVTLUS, AFCVTWD, AFCVTLD, AFCVTWUD, AFCVTLUD: // Set the default rounding mode in funct3 to round to zero. @@ -3764,6 +4566,32 @@ func instructionsForProg(p *obj.Prog) []*instruction { ins.as = AFSGNJND ins.rs1 = uint32(p.From.Reg) + case ACLW, ACLD, ACFLD: + ins.rs1, ins.rs2 = ins.rs2, obj.REG_NONE + + case ACSW, ACSD, ACFSD: + ins.rs1, ins.rd = ins.rd, obj.REG_NONE + ins.imm = p.To.Offset + + case ACSWSP, ACSDSP, ACFSDSP: + ins.imm = p.To.Offset + + case ACANDI, ACSRLI, ACSRAI: + ins.rs1, ins.rd = ins.rd, ins.rs1 + + case ACBEQZ, ACBNEZ: + ins.rd, ins.rs1, ins.rs2 = obj.REG_NONE, uint32(p.From.Reg), obj.REG_NONE + ins.imm = p.To.Offset + + case ACJR: + ins.rd, ins.rs1 = obj.REG_NONE, uint32(p.To.Reg) + + case ACJ: + ins.imm = p.To.Offset + + case ACNOP: + ins.rd, ins.rs1 = REG_ZERO, REG_ZERO + case AROL, AROLW, AROR, ARORW: inss = instructionsForRotate(p, ins) @@ -3954,7 +4782,9 @@ func instructionsForProg(p *obj.Prog) []*instruction { AVREDSUMVS, AVREDMAXUVS, AVREDMAXVS, AVREDMINUVS, AVREDMINVS, AVREDANDVS, AVREDORVS, AVREDXORVS, AVWREDSUMUVS, AVWREDSUMVS, AVFREDOSUMVS, AVFREDUSUMVS, AVFREDMAXVS, AVFREDMINVS, AVFWREDOSUMVS, AVFWREDUSUMVS, AVSLIDEUPVX, AVSLIDEDOWNVX, AVSLIDE1UPVX, AVFSLIDE1UPVF, AVSLIDE1DOWNVX, AVFSLIDE1DOWNVF, - AVRGATHERVV, AVRGATHEREI16VV, AVRGATHERVX: + AVRGATHERVV, AVRGATHEREI16VV, AVRGATHERVX, + AVANDNVV, AVANDNVX, AVROLVV, AVROLVX, AVRORVV, AVRORVX, + AVWSLLVV, AVWSLLVX, AVCLMULVV, AVCLMULVX, AVCLMULHVV, AVCLMULHVX: // Set mask bit switch { case ins.rs3 == obj.REG_NONE: @@ -3978,7 +4808,8 @@ func instructionsForProg(p *obj.Prog) []*instruction { ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), obj.REG_NONE case AVADDVI, AVRSUBVI, AVANDVI, AVORVI, AVXORVI, AVMSEQVI, AVMSNEVI, AVMSLEUVI, AVMSLEVI, AVMSGTUVI, AVMSGTVI, - AVSLLVI, AVSRLVI, AVSRAVI, AVNSRLWI, AVNSRAWI, AVRGATHERVI, AVSLIDEUPVI, AVSLIDEDOWNVI: + AVSLLVI, AVSRLVI, AVSRAVI, AVNSRLWI, AVNSRAWI, AVRGATHERVI, AVSLIDEUPVI, AVSLIDEDOWNVI, + AVRORVI, AVWSLLVI: // Set mask bit switch { case ins.rs3 == obj.REG_NONE: @@ -3988,10 +4819,13 @@ func instructionsForProg(p *obj.Prog) []*instruction { } ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), obj.REG_NONE, uint32(p.Reg), obj.REG_NONE - case AVZEXTVF2, AVSEXTVF2, AVZEXTVF4, AVSEXTVF4, AVZEXTVF8, AVSEXTVF8, AVFSQRTV, AVFRSQRT7V, AVFREC7V, AVFCLASSV, + case AVZEXTVF2, AVSEXTVF2, AVZEXTVF4, AVSEXTVF4, AVZEXTVF8, AVSEXTVF8, + AVFSQRTV, AVFRSQRT7V, AVFREC7V, AVFCLASSV, AVFCVTXUFV, AVFCVTXFV, AVFCVTRTZXUFV, AVFCVTRTZXFV, AVFCVTFXUV, AVFCVTFXV, - AVFWCVTXUFV, AVFWCVTXFV, AVFWCVTRTZXUFV, AVFWCVTRTZXFV, AVFWCVTFXUV, AVFWCVTFXV, AVFWCVTFFV, - AVFNCVTXUFW, AVFNCVTXFW, AVFNCVTRTZXUFW, AVFNCVTRTZXFW, AVFNCVTFXUW, AVFNCVTFXW, AVFNCVTFFW, AVFNCVTRODFFW: + AVFWCVTXUFV, AVFWCVTXFV, AVFWCVTRTZXUFV, AVFWCVTRTZXFV, AVFWCVTFXUV, AVFWCVTFXV, + AVFWCVTFFV, AVFNCVTXUFW, AVFNCVTXFW, AVFNCVTRTZXUFW, AVFNCVTRTZXFW, AVFNCVTFXUW, + AVFNCVTFXW, AVFNCVTFFW, AVFNCVTRODFFW, + AVBREVV, AVBREV8V, AVREV8V, AVCLZV, AVCTZV, AVCPOPV: // Set mask bit switch { case ins.rs1 == obj.REG_NONE: @@ -4165,6 +4999,15 @@ func instructionsForProg(p *obj.Prog) []*instruction { ins.rs1, ins.rs2 = obj.REG_NONE, REG_V0 } + // Only compress instructions when there is no relocation, since + // relocation relies on knowledge about the exact instructions that + // are in use. + if compress && p.Mark&NEED_RELOC == 0 { + for _, ins := range inss { + ins.compress() + } + } + for _, ins := range inss { ins.p = p } @@ -4198,7 +5041,8 @@ func assemble(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { Add: p.To.Offset, }) } - case AJALR: + + case ACJALR, AJALR: if p.To.Sym != nil { ctxt.Diag("%v: unexpected AJALR with to symbol", p) } @@ -4253,15 +5097,22 @@ func assemble(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { v := pcAlignPadLength(p.Pc, alignedValue) offset := p.Pc for ; v >= 4; v -= 4 { - // NOP - cursym.WriteBytes(ctxt, offset, []byte{0x13, 0, 0, 0}) + // NOP (ADDI $0, X0, X0) + cursym.WriteBytes(ctxt, offset, []byte{0x13, 0x00, 0x00, 0x00}) offset += 4 } + if v == 2 { + // CNOP + cursym.WriteBytes(ctxt, offset, []byte{0x01, 0x00}) + offset += 2 + } else if v != 0 { + ctxt.Diag("bad PCALIGN pad length") + } continue } offset := p.Pc - for _, ins := range instructionsForProg(p) { + for _, ins := range instructionsForProg(p, ctxt.CompressInstructions) { if ic, err := ins.encode(); err == nil { cursym.WriteInt(ctxt, offset, ins.length(), int64(ic)) offset += int64(ins.length()) @@ -4280,9 +5131,20 @@ func isUnsafePoint(p *obj.Prog) bool { } func ParseSuffix(prog *obj.Prog, cond string) (err error) { + cond = strings.TrimPrefix(cond, ".") switch prog.As { case AFCVTWS, AFCVTLS, AFCVTWUS, AFCVTLUS, AFCVTWD, AFCVTLD, AFCVTWUD, AFCVTLUD: - prog.Scond, err = rmSuffixEncode(strings.TrimPrefix(cond, ".")) + prog.Scond, err = rmSuffixEncode(cond) + case AFENCE: + if cond == "TSO" { + prog.Scond = fenceTsoSuffixBit + } else { + err = fmt.Errorf("unrecognized suffix .%q", cond) + } + default: + if cond != "" { + err = fmt.Errorf("unrecognized suffix .%q", cond) + } } return } diff --git a/src/cmd/internal/obj/riscv/obj_test.go b/src/cmd/internal/obj/riscv/obj_test.go index 87b31e5a896c24..d4e7e14db6539c 100644 --- a/src/cmd/internal/obj/riscv/obj_test.go +++ b/src/cmd/internal/obj/riscv/obj_test.go @@ -17,12 +17,13 @@ func TestSplitShiftConst(t *testing.T) { wantRsh int wantOk bool }{ - {0x100000000, 1, 32, 0, true}, - {0xfffff001, 0, 0, 0, false}, + {0xfffff001, -4095, 32, 32, true}, {0xfffff801, -2047, 32, 32, true}, {0xfffffff1, -15, 32, 32, true}, {0xffffffff, -1, 0, 32, true}, {0xfffffffe, 0x7fffffff, 1, 0, true}, + {0x80a9b553, -2136361645, 32, 32, true}, + {0x100000000, 1, 32, 0, true}, {0xfffffffffffda, -19, 13, 12, true}, {0xfffffffffffde, -17, 13, 12, true}, {0x000003ffffffffff, -1, 0, 22, true}, @@ -31,7 +32,7 @@ func TestSplitShiftConst(t *testing.T) { {0x7fffffffffffffff, -1, 0, 1, true}, {0x7f7f7f7f7f7f7f7f, 0, 0, 0, false}, {0x0080000010000000, 0x8000001, 28, 0, true}, - {0x0abcdabcd0000000, 0, 0, 0, false}, + {0x0abcdabcd0000000, -1412584499, 32, 4, true}, {-4503599610593281, 0, 0, 0, false}, // 0x8abcdabcd0000000 {-7543254330000000, 0, 0, 0, false}, // 0xfff0000000ffffff } diff --git a/src/cmd/internal/obj/s390x/a.out.go b/src/cmd/internal/obj/s390x/a.out.go index caf5ec09358a03..db038080ee66b4 100644 --- a/src/cmd/internal/obj/s390x/a.out.go +++ b/src/cmd/internal/obj/s390x/a.out.go @@ -139,8 +139,8 @@ const ( REG_RESERVED // end of allocated registers REGARG = -1 // -1 disables passing the first argument in register - REGRT1 = REG_R3 // used during zeroing of the stack - not reserved - REGRT2 = REG_R4 // used during zeroing of the stack - not reserved + REGRT1 = REG_R1 // used during zeroing of the stack - not reserved + REGRT2 = REG_R10 // used during zeroing of the stack - not reserved REGTMP = REG_R10 // scratch register used in the assembler and linker REGTMP2 = REG_R11 // scratch register used in the assembler and linker REGCTXT = REG_R12 // context for closures @@ -946,6 +946,7 @@ const ( AVSTEG AVSTEB AVSTM + AVSTRL AVSTL AVSTRC AVSTRCB diff --git a/src/cmd/internal/obj/s390x/anames.go b/src/cmd/internal/obj/s390x/anames.go index a6f2820f85d524..85f846b714e2d0 100644 --- a/src/cmd/internal/obj/s390x/anames.go +++ b/src/cmd/internal/obj/s390x/anames.go @@ -669,6 +669,7 @@ var Anames = []string{ "VSTEG", "VSTEB", "VSTM", + "VSTRL", "VSTL", "VSTRC", "VSTRCB", diff --git a/src/cmd/internal/obj/s390x/asmz.go b/src/cmd/internal/obj/s390x/asmz.go index 3706bb1b74e0cd..ba8cff4e6d725c 100644 --- a/src/cmd/internal/obj/s390x/asmz.go +++ b/src/cmd/internal/obj/s390x/asmz.go @@ -458,6 +458,10 @@ var optab = []Optab{ // MVC storage and storage {i: 127, as: AMVCLE, a1: C_LOREG, a2: C_REG, a6: C_REG}, {i: 127, as: AMVCLE, a1: C_SCON, a2: C_REG, a6: C_REG}, + + // VSI store rightmost with length + {i: 129, as: AVSTRL, a1: C_VREG, a3: C_SCON, a6: C_SOREG}, + {i: 129, as: AVSTRL, a1: C_VREG, a3: C_SCON, a6: C_SAUTO}, } var oprange [ALAST & obj.AMask][]Optab @@ -2634,6 +2638,7 @@ const ( op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE + op_VSTRL uint32 = 0xE63D // VSI VECTOR STORE RIGHTMOST WITH LENGTH op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT @@ -4459,7 +4464,7 @@ func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { } zRRF(opcode, uint32(p.Reg), 0, uint32(p.From.Reg), uint32(p.To.Reg), asm) - case 127: + case 127: // RS-a Move Long Extended // NOTE: Mapping MVCLE operands is as follows: // Instruction Format: MVCLE R1,R3,D2(B2) // R1 - prog.To (for Destination) @@ -4482,6 +4487,17 @@ func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { m5 := singleElementMask(p.As) m6 := uint32(c.vregoff(&p.From)) zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), m6, m5, m4, asm) + + case 129: // VSI Vector Store Rightmost with Length + op, _, _ := vop(p.As) + v1 := p.From.Reg + b2 := p.To.Reg + if b2 == 0 { + b2 = REGSP + } + d2 := uint32(c.vregoff(&p.To)) + i3 := uint32(c.vregoff(p.GetFrom3())) + zVSI(op, uint32(v1), uint32(b2), d2, i3, asm) } } @@ -4547,7 +4563,7 @@ func (c *ctxtz) zopload(a obj.As) uint32 { return op_LRVH } - c.ctxt.Diag("unknown store opcode %v", a) + c.ctxt.Diag("unknown zopload opcode %v", a) return 0 } @@ -5081,3 +5097,13 @@ func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { (uint8(m4)<<4)|rxb(v1, v2, 0, 0), uint8(op)) } + +func zVSI(op, v1, b2, d2, i3 uint32, asm *[]byte) { + *asm = append(*asm, + uint8(op>>8), + uint8(i3), + (uint8(b2)<<4)|(uint8(d2>>8)&0xf), + uint8(d2), + (uint8(v1)<<4)|rxb(v1, 0, 0, 0), + uint8(op)) +} diff --git a/src/cmd/internal/obj/s390x/objz.go b/src/cmd/internal/obj/s390x/objz.go index 44c1a7d586d5f2..d877589573527b 100644 --- a/src/cmd/internal/obj/s390x/objz.go +++ b/src/cmd/internal/obj/s390x/objz.go @@ -385,7 +385,10 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { } case obj.ARET: - retTarget := p.To.Sym + retTarget, retReg := p.To.Sym, p.To.Reg + if retReg == obj.REG_NONE { + retReg = REG_LR + } if c.cursym.Func().Text.Mark&LEAF != 0 { if autosize == 0 { @@ -393,7 +396,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { p.From = obj.Addr{} if retTarget == nil { p.To.Type = obj.TYPE_REG - p.To.Reg = REG_LR + p.To.Reg = retReg } else { p.To.Type = obj.TYPE_BRANCH p.To.Sym = retTarget @@ -414,7 +417,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { q.From = obj.Addr{} if retTarget == nil { q.To.Type = obj.TYPE_REG - q.To.Reg = REG_LR + q.To.Reg = retReg } else { q.To.Type = obj.TYPE_BRANCH q.To.Sym = retTarget @@ -450,7 +453,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { q.From = obj.Addr{} if retTarget == nil { q.To.Type = obj.TYPE_REG - q.To.Reg = REG_LR + q.To.Reg = retReg } else { q.To.Type = obj.TYPE_BRANCH q.To.Sym = retTarget @@ -506,7 +509,13 @@ func (c *ctxtz) stacksplitPre(p *obj.Prog, framesize int32) (pPre, pPreempt, pCh // Save LR and REGCTXT const frameSize = 16 p = c.ctxt.StartUnsafePoint(p, c.newprog) + + // Spill arguments. This has to happen before we open + // any more frame space. + p = c.cursym.Func().SpillRegisterArgs(p, c.newprog) + // MOVD LR, -16(SP) + p = obj.Appendp(p, c.newprog) p.As = AMOVD p.From = obj.Addr{Type: obj.TYPE_REG, Reg: REG_LR} @@ -549,10 +558,12 @@ func (c *ctxtz) stacksplitPre(p *obj.Prog, framesize int32) (pPre, pPreempt, pCh p.To = obj.Addr{Type: obj.TYPE_REG, Reg: REGSP} p.Spadj = -frameSize + // Unspill arguments + p = c.cursym.Func().UnspillRegisterArgs(p, c.newprog) p = c.ctxt.EndUnsafePoint(p, c.newprog, -1) } - // MOVD g_stackguard(g), R3 + // MOVD g_stackguard(g), R10 p = obj.Appendp(p, c.newprog) // Jump back to here after morestack returns. pCheck = p @@ -565,7 +576,7 @@ func (c *ctxtz) stacksplitPre(p *obj.Prog, framesize int32) (pPre, pPreempt, pCh p.From.Offset = 3 * int64(c.ctxt.Arch.PtrSize) // G.stackguard1 } p.To.Type = obj.TYPE_REG - p.To.Reg = REG_R3 + p.To.Reg = REG_R10 // Mark the stack bound check and morestack call async nonpreemptible. // If we get preempted here, when resumed the preemption request is @@ -579,7 +590,7 @@ func (c *ctxtz) stacksplitPre(p *obj.Prog, framesize int32) (pPre, pPreempt, pCh p = obj.Appendp(p, c.newprog) p.From.Type = obj.TYPE_REG - p.From.Reg = REG_R3 + p.From.Reg = REG_R10 p.Reg = REGSP p.As = ACMPUBGE p.To.Type = obj.TYPE_BRANCH @@ -598,40 +609,40 @@ func (c *ctxtz) stacksplitPre(p *obj.Prog, framesize int32) (pPre, pPreempt, pCh // stack guard to incorrectly succeed. We explicitly // guard against underflow. // - // MOVD $(framesize-StackSmall), R4 - // CMPUBLT SP, R4, label-of-call-to-morestack + // MOVD $(framesize-StackSmall), R11 + // CMPUBLT SP, R11, label-of-call-to-morestack p = obj.Appendp(p, c.newprog) p.As = AMOVD p.From.Type = obj.TYPE_CONST p.From.Offset = offset p.To.Type = obj.TYPE_REG - p.To.Reg = REG_R4 + p.To.Reg = REG_R11 p = obj.Appendp(p, c.newprog) pPreempt = p p.As = ACMPUBLT p.From.Type = obj.TYPE_REG p.From.Reg = REGSP - p.Reg = REG_R4 + p.Reg = REG_R11 p.To.Type = obj.TYPE_BRANCH } // Check against the stack guard. We've ensured this won't underflow. - // ADD $-(framesize-StackSmall), SP, R4 - // CMPUBGE stackguard, R4, label-of-call-to-morestack + // ADD $-(framesize-StackSmall), SP, R11 + // CMPUBGE stackguard, R11, label-of-call-to-morestack p = obj.Appendp(p, c.newprog) p.As = AADD p.From.Type = obj.TYPE_CONST p.From.Offset = -offset p.Reg = REGSP p.To.Type = obj.TYPE_REG - p.To.Reg = REG_R4 + p.To.Reg = REG_R11 p = obj.Appendp(p, c.newprog) p.From.Type = obj.TYPE_REG - p.From.Reg = REG_R3 - p.Reg = REG_R4 + p.From.Reg = REG_R10 + p.Reg = REG_R11 p.As = ACMPUBGE p.To.Type = obj.TYPE_BRANCH @@ -654,18 +665,22 @@ func (c *ctxtz) stacksplitPost(p *obj.Prog, pPre, pPreempt, pCheck *obj.Prog, fr pcdata := c.ctxt.EmitEntryStackMap(c.cursym, spfix, c.newprog) pcdata = c.ctxt.StartUnsafePoint(pcdata, c.newprog) + if pPreempt != nil { + pPreempt.To.SetTarget(pcdata) + } + pPre.To.SetTarget(pcdata) + + // Spill the register args that could be clobbered by the + // morestack code. + spill := c.cursym.Func().SpillRegisterArgs(pcdata, c.newprog) // MOVD LR, R5 - p = obj.Appendp(pcdata, c.newprog) - pPre.To.SetTarget(p) + p = obj.Appendp(spill, c.newprog) p.As = AMOVD p.From.Type = obj.TYPE_REG p.From.Reg = REG_LR p.To.Type = obj.TYPE_REG p.To.Reg = REG_R5 - if pPreempt != nil { - pPreempt.To.SetTarget(p) - } // BL runtime.morestack(SB) p = obj.Appendp(p, c.newprog) @@ -680,10 +695,12 @@ func (c *ctxtz) stacksplitPost(p *obj.Prog, pPre, pPreempt, pCheck *obj.Prog, fr p.To.Sym = c.ctxt.Lookup("runtime.morestack") } + // The instructions which unspill regs should be preemptible. p = c.ctxt.EndUnsafePoint(p, c.newprog, -1) + unspill := c.cursym.Func().UnspillRegisterArgs(p, c.newprog) // BR pCheck - p = obj.Appendp(p, c.newprog) + p = obj.Appendp(unspill, c.newprog) p.As = ABR p.To.Type = obj.TYPE_BRANCH diff --git a/src/cmd/internal/obj/s390x/vector.go b/src/cmd/internal/obj/s390x/vector.go index 966cd04c277c38..ecb9c96ddc7ca1 100644 --- a/src/cmd/internal/obj/s390x/vector.go +++ b/src/cmd/internal/obj/s390x/vector.go @@ -915,6 +915,8 @@ func vop(as obj.As) (opcode, es, cs uint32) { return op_VSTEB, 0, 0 case AVSTM: return op_VSTM, 0, 0 + case AVSTRL: + return op_VSTRL, 0, 0 case AVSTL: return op_VSTL, 0, 0 case AVSTRC: diff --git a/src/cmd/internal/obj/sizeof_test.go b/src/cmd/internal/obj/sizeof_test.go index 69e60473f50ac8..fdee114f5b45a7 100644 --- a/src/cmd/internal/obj/sizeof_test.go +++ b/src/cmd/internal/obj/sizeof_test.go @@ -16,9 +16,9 @@ func TestSizeof(t *testing.T) { const _64bit = unsafe.Sizeof(uintptr(0)) == 8 var tests = []struct { - val interface{} // type as a value - _32bit uintptr // size on 32bit platforms - _64bit uintptr // size on 64bit platforms + val any // type as a value + _32bit uintptr // size on 32bit platforms + _64bit uintptr // size on 64bit platforms }{ {Addr{}, 32, 48}, {LSym{}, 72, 120}, diff --git a/src/cmd/internal/obj/stringer.go b/src/cmd/internal/obj/stringer.go index b2b0df83ad0d97..efce8516d7e4c3 100644 --- a/src/cmd/internal/obj/stringer.go +++ b/src/cmd/internal/obj/stringer.go @@ -93,7 +93,7 @@ func main() { } } -const header = `// Code generated by stringer -i %s -o %s -p %s; DO NOT EDIT. +const header = `// Code generated by go run ../stringer.go -i %s -o %s -p %s; DO NOT EDIT. package %s diff --git a/src/cmd/internal/obj/sym.go b/src/cmd/internal/obj/sym.go index 08c50ec72b6a5c..08508ed438ba22 100644 --- a/src/cmd/internal/obj/sym.go +++ b/src/cmd/internal/obj/sym.go @@ -42,12 +42,11 @@ import ( "log" "math" "sort" + "sync" ) func Linknew(arch *LinkArch) *Link { ctxt := new(Link) - ctxt.hash = make(map[string]*LSym) - ctxt.funchash = make(map[string]*LSym) ctxt.statichash = make(map[string]*LSym) ctxt.Arch = arch ctxt.Pathname = objabi.WorkingDir() @@ -90,28 +89,34 @@ func (ctxt *Link) LookupABI(name string, abi ABI) *LSym { // If it does not exist, it creates it and // passes it to init for one-time initialization. func (ctxt *Link) LookupABIInit(name string, abi ABI, init func(s *LSym)) *LSym { - var hash map[string]*LSym + var hash *sync.Map switch abi { case ABI0: - hash = ctxt.hash + hash = &ctxt.hash case ABIInternal: - hash = ctxt.funchash + hash = &ctxt.funchash default: panic("unknown ABI") } - ctxt.hashmu.Lock() - s := hash[name] - if s == nil { - s = &LSym{Name: name} - s.SetABI(abi) - hash[name] = s - if init != nil { - init(s) + c, _ := hash.Load(name) + if c == nil { + once := &symOnce{ + sym: LSym{Name: name}, } + once.sym.SetABI(abi) + c, _ = hash.LoadOrStore(name, once) } - ctxt.hashmu.Unlock() - return s + once := c.(*symOnce) + if init != nil && !once.inited.Load() { + ctxt.hashmu.Lock() + if !once.inited.Load() { + init(&once.sym) + once.inited.Store(true) + } + ctxt.hashmu.Unlock() + } + return &once.sym } // Lookup looks up the symbol with name name. @@ -124,17 +129,31 @@ func (ctxt *Link) Lookup(name string) *LSym { // If it does not exist, it creates it and // passes it to init for one-time initialization. func (ctxt *Link) LookupInit(name string, init func(s *LSym)) *LSym { - ctxt.hashmu.Lock() - s := ctxt.hash[name] - if s == nil { - s = &LSym{Name: name} - ctxt.hash[name] = s - if init != nil { - init(s) + c, _ := ctxt.hash.Load(name) + if c == nil { + once := &symOnce{ + sym: LSym{Name: name}, } + c, _ = ctxt.hash.LoadOrStore(name, once) } - ctxt.hashmu.Unlock() - return s + once := c.(*symOnce) + if init != nil && !once.inited.Load() { + // TODO(dmo): some of our init functions modify other fields + // in the symbol table. They are only implicitly protected since + // we serialize all inits under the hashmu lock. + // Consider auditing the functions and have them lock their + // concurrent access values explicitly. This would make it possible + // to have more than one than one init going at a time (although this might + // be a theoretical concern, I have yet to catch this lock actually being waited + // on). + ctxt.hashmu.Lock() + if !once.inited.Load() { + init(&once.sym) + once.inited.Store(true) + } + ctxt.hashmu.Unlock() + } + return &once.sym } func (ctxt *Link) rodataKind() (suffix string, typ objabi.SymKind) { @@ -147,6 +166,7 @@ func (ctxt *Link) Float32Sym(f float32) *LSym { name := fmt.Sprintf("$f32.%08x%s", i, suffix) return ctxt.LookupInit(name, func(s *LSym) { s.Size = 4 + s.Align = 4 s.WriteFloat32(ctxt, 0, f) s.Type = typ s.Set(AttrLocal, true) @@ -161,6 +181,7 @@ func (ctxt *Link) Float64Sym(f float64) *LSym { name := fmt.Sprintf("$f64.%016x%s", i, suffix) return ctxt.LookupInit(name, func(s *LSym) { s.Size = 8 + s.Align = int16(ctxt.Arch.PtrSize) s.WriteFloat64(ctxt, 0, f) s.Type = typ s.Set(AttrLocal, true) @@ -174,6 +195,7 @@ func (ctxt *Link) Int32Sym(i int64) *LSym { name := fmt.Sprintf("$i32.%08x%s", uint64(i), suffix) return ctxt.LookupInit(name, func(s *LSym) { s.Size = 4 + s.Align = 4 s.WriteInt(ctxt, 0, 4, i) s.Type = typ s.Set(AttrLocal, true) @@ -187,6 +209,7 @@ func (ctxt *Link) Int64Sym(i int64) *LSym { name := fmt.Sprintf("$i64.%016x%s", uint64(i), suffix) return ctxt.LookupInit(name, func(s *LSym) { s.Size = 8 + s.Align = int16(ctxt.Arch.PtrSize) s.WriteInt(ctxt, 0, 8, i) s.Type = typ s.Set(AttrLocal, true) @@ -200,6 +223,7 @@ func (ctxt *Link) Int128Sym(hi, lo int64) *LSym { name := fmt.Sprintf("$i128.%016x%016x%s", uint64(hi), uint64(lo), suffix) return ctxt.LookupInit(name, func(s *LSym) { s.Size = 16 + s.Align = int16(ctxt.Arch.PtrSize) if ctxt.Arch.ByteOrder == binary.LittleEndian { s.WriteInt(ctxt, 0, 8, lo) s.WriteInt(ctxt, 8, 8, hi) @@ -221,6 +245,7 @@ func (ctxt *Link) GCLocalsSym(data []byte) *LSym { return ctxt.LookupInit(fmt.Sprintf("gclocals·%s", str), func(lsym *LSym) { lsym.P = data lsym.Set(AttrContentAddressable, true) + lsym.Align = 4 }) } diff --git a/src/cmd/internal/obj/util.go b/src/cmd/internal/obj/util.go index 7d87bff94918b4..336ddcad0d541f 100644 --- a/src/cmd/internal/obj/util.go +++ b/src/cmd/internal/obj/util.go @@ -222,6 +222,11 @@ func (ctxt *Link) CanReuseProgs() bool { return ctxt.Debugasm == 0 } +func isZReg(r int) bool { + return (r >= RBaseARM64+96 && r <= RBaseARM64+127) || + (r >= RBaseARM64+2048 && r < RBaseARM64+3072) +} + // Dconv accepts an argument 'a' within a prog 'p' and returns a string // with a formatted version of the argument. func Dconv(p *Prog, a *Addr) string { @@ -257,6 +262,30 @@ func writeDconv(w io.Writer, p *Prog, a *Addr, abiDetail bool) { } case TYPE_REG: + if buildcfg.GOARCH == "arm64" && a.Offset&(int64(1)<<62) != 0 { + preg := int((a.Offset)&31) + RBaseARM64 + 128 + arng2 := (a.Offset >> 5) & 15 + selreg := int((a.Offset>>9)&31) + RBaseARM64 + idximm := (a.Offset >> 14) & 63 + + arngStr := "" + switch arng2 { + case 9: + arngStr = ".B" + case 10: + arngStr = ".H" + case 11: + arngStr = ".S" + case 12: + arngStr = ".D" + case 13: + arngStr = ".Q" + } + + fmt.Fprintf(w, "[%s,$%d](%s%s)", Rconv(selreg), idximm, Rconv(preg), arngStr) + return + } + // TODO(rsc): This special case is for x86 instructions like // PINSRQ CX,$1,X6 // where the $1 is included in the p->to Addr. @@ -273,8 +302,8 @@ func writeDconv(w io.Writer, p *Prog, a *Addr, abiDetail bool) { io.WriteString(w, Rconv(int(a.Reg))) } - if (RBaseARM64+1<<10+1<<9) /* arm64.REG_ELEM */ <= a.Reg && - a.Reg < (RBaseARM64+1<<11) /* arm64.REG_ELEM_END */ { + if ((RBaseARM64+1<<10+1<<9) /* arm64.REG_ELEM */ <= a.Reg && a.Reg < (RBaseARM64+1<<11) /* arm64.REG_ZARNG */) || + ((RBaseARM64+1<<11+1<<9) /* arm64.REG_ZARNGELEM */ <= a.Reg && a.Reg < (RBaseARM64+1<<11+1<<10+1<<9) /* arm64.REG_PARNGZM */) { fmt.Fprintf(w, "[%d]", a.Index) } @@ -297,13 +326,43 @@ func writeDconv(w io.Writer, p *Prog, a *Addr, abiDetail bool) { a.writeNameTo(w, abiDetail) case TYPE_MEM: - a.WriteNameTo(w) - if a.Index != REG_NONE { - if a.Scale == 0 { - // arm64 shifted or extended register offset, scale = 0. - fmt.Fprintf(w, "(%v)", Rconv(int(a.Index))) + if buildcfg.GOARCH == "arm64" && (a.Scale < 0 || (a.Index != REG_NONE && (isZReg(int(a.Reg)) || isZReg(int(a.Index))))) { + // SVE extended addressing pattern + if a.Index == REG_NONE { + if a.Offset < 0 { + fmt.Fprintf(w, "(-VL*%d)(%v)", -a.Offset, Rconv(int(a.Reg))) + } else { + fmt.Fprintf(w, "(VL*%d)(%v)", a.Offset, Rconv(int(a.Reg))) + } } else { - fmt.Fprintf(w, "(%v*%d)", Rconv(int(a.Index)), int(a.Scale)) + amount := 0 + mod := 0 + if a.Scale < 0 { + amount = int((a.Scale >> 12) & 0x7) + mod = int((a.Scale >> 9) & 0x7) + } + modStr := "" + switch mod { + case 1: + modStr = ".UXTW" + case 2: + modStr = ".SXTW" + } + amountStr := "" + if amount != 0 { + amountStr = fmt.Sprintf("<<%d", amount) + } + fmt.Fprintf(w, "(%v%s%s)(%v)", Rconv(int(a.Reg)), modStr, amountStr, Rconv(int(a.Index))) + } + } else { + a.WriteNameTo(w) + if a.Index != REG_NONE { + if a.Scale == 0 { + // arm64 shifted or extended register offset, scale = 0. + fmt.Fprintf(w, "(%v)", Rconv(int(a.Index))) + } else { + fmt.Fprintf(w, "(%v*%d)", Rconv(int(a.Index)), int(a.Scale)) + } } } @@ -514,12 +573,12 @@ const ( RBaseAMD64 = 2 * 1024 RBaseARM = 3 * 1024 RBasePPC64 = 4 * 1024 // range [4k, 8k) - RBaseARM64 = 8 * 1024 // range [8k, 13k) - RBaseMIPS = 13 * 1024 // range [13k, 14k) - RBaseS390X = 14 * 1024 // range [14k, 15k) - RBaseRISCV = 15 * 1024 // range [15k, 16k) - RBaseWasm = 16 * 1024 - RBaseLOONG64 = 19 * 1024 // range [19K, 22k) + RBaseARM64 = 8 * 1024 // range [8k, 18k) + RBaseMIPS = 18 * 1024 // range [18k, 19k) + RBaseS390X = 19 * 1024 // range [19k, 20k) + RBaseRISCV = 20 * 1024 // range [20k, 21k) + RBaseWasm = 21 * 1024 + RBaseLOONG64 = 22 * 1024 // range [22K, 25k) ) // RegisterRegister binds a pretty-printer (Rconv) for register @@ -737,7 +796,7 @@ func AlignmentPaddingLength(pc int32, p *Prog, ctxt *Link) int { // the required code alignment func requireAlignment(a int64, ctxt *Link, cursym *LSym) { // TODO remove explicit knowledge about AIX. - if ctxt.Headtype != objabi.Haix && cursym.Func().Align < int32(a) { - cursym.Func().Align = int32(a) + if ctxt.Headtype != objabi.Haix && cursym.Align < int16(a) { + cursym.Align = int16(a) } } diff --git a/src/cmd/internal/obj/wasm/a.out.go b/src/cmd/internal/obj/wasm/a.out.go index 0262630d5a78a0..0fc6d3dcaba23d 100644 --- a/src/cmd/internal/obj/wasm/a.out.go +++ b/src/cmd/internal/obj/wasm/a.out.go @@ -241,6 +241,290 @@ const ( ATableSize ATableFill + // WASM Vector instructions 0xFD 0x00 and following + AV128Load + AV128Load8x8S + AV128Load8x8U + AV128Load16x4S + AV128Load16x4U + AV128Load32x2S + AV128Load32x2U + AV128Load8Splat + AV128Load16Splat + AV128Load32Splat + AV128Load64Splat + AV128Store + AV128Const + AI8x16Shuffle16 + AI8x16Swizzle + AI8x16Splat + AI16x8Splat + AI32x4Splat + AI64x2Splat + AF32x4Splat + AF64x2Splat + AI8x16ExtractLaneS + AI8x16ExtractLaneU + AI8x16ReplaceLane + AI16x8ExtractLaneS + AI16x8ExtractLaneU + AI16x8ReplaceLane + AI32x4ExtractLane + AI32x4ReplaceLane + AI64x2ExtractLane + AI64x2ReplaceLane + AF32x4ExtractLane + AF32x4ReplaceLane + AF64x2ExtractLane + AF64x2ReplaceLane + AI8x16Eq + AI8x16Ne + AI8x16LtS + AI8x16LtU + AI8x16GtS + AI8x16GtU + AI8x16LeS + AI8x16LeU + AI8x16GeS + AI8x16GeU + AI16x8Eq + AI16x8Ne + AI16x8LtS + AI16x8LtU + AI16x8GtS + AI16x8GtU + AI16x8LeS + AI16x8LeU + AI16x8GeS + AI16x8GeU + AI32x4Eq + AI32x4Ne + AI32x4LtS + AI32x4LtU + AI32x4GtS + AI32x4GtU + AI32x4LeS + AI32x4LeU + AI32x4GeS + AI32x4GeU + AF32x4Eq + AF32x4Ne + AF32x4Lt + AF32x4Gt + AF32x4Le + AF32x4Ge + AF64x2Eq + AF64x2Ne + AF64x2Lt + AF64x2Gt + AF64x2Le + AF64x2Ge + AV128Not + AV128And + AV128Andnot + AV128Or + AV128Xor + AV128Bitselect + AV128AnyTrue + AV128Load8Lane + AV128Load16Lane + AV128Load32Lane + AV128Load64Lane + AV128Store8Lane + AV128Store16Lane + AV128Store32Lane + AV128Store64Lane + AV128Load32Zero + AV128Load64Zero + AF32x4DemoteF64x2Zero + AF64x2PromoteLowF32x4 + AI8x16Abs + AI8x16Neg + AI8x16Popcnt + AI8x16AllTrue + AI8x16Bitmask + AI8x16NarrowI16x8S + AI8x16NarrowI16x8U + AF32x4Ceil + AF32x4Floor + AF32x4Trunc + AF32x4Nearest + AI8x16Shl + AI8x16ShrS + AI8x16ShrU + AI8x16Add + AI8x16AddSatS + AI8x16AddSatU + AI8x16Sub + AI8x16SubSatS + AI8x16SubSatU + AF64x2Ceil + AF64x2Floor + AI8x16MinS + AI8x16MinU + AI8x16MaxS + AI8x16MaxU + AF64x2Trunc + AI8x16AvgrU + AI16x8ExtaddPairwiseI8x16S + AI16x8ExtaddPairwiseI8x16U + AI32x4ExtaddPairwiseI16x8S + AI32x4ExtaddPairwiseI16x8U + + // WASM Vector instructions 0xFD 0x80 and following but followed by a 0x01 + // e.g. 0xFD 0x80 0x01, 0xFD 0x81 0x01, etc. + AI16x8Abs + AI16x8Neg + AI16x8Q15MulrSatS + AI16x8AllTrue + AI16x8Bitmask + AI16x8NarrowI32x4S + AI16x8NarrowI32x4U + AI16x8ExtendLowI8x16S + AI16x8ExtendHighI8x16S + AI16x8ExtendLowI8x16U + AI16x8ExtendHighI8x16U + AI16x8Shl + AI16x8ShrS + AI16x8ShrU + AI16x8Add + AI16x8AddSatS + AI16x8AddSatU + AI16x8Sub + AI16x8SubSatS + AI16x8SubSatU + AF64x2Nearest + AI16x8Mul + AI16x8MinS + AI16x8MinU + AI16x8MaxS + AI16x8MaxU + AReservedFD9A01 // 0xFD 0x9A 0x01 + AI16x8AvgrU + AI16x8ExtmulLowI8x16S + AI16x8ExtmulHighI8x16S + AI16x8ExtmulLowI8x16U + AI16x8ExtmulHighI8x16U + AI32x4Abs + AI32x4Neg + AReservedFDA201 + AI32x4AllTrue + AI32x4Bitmask + AReservedFDA501 + AReservedFDA601 + AI32x4ExtendLowI16x8S + AI32x4ExtendHighI16x8S + AI32x4ExtendLowI16x8U + AI32x4ExtendHighI16x8U + AI32x4Shl + AI32x4ShrS + AI32x4ShrU + AI32x4Add + AReservedFDAF01 + AReservedFDB001 + AI32x4Sub + AReservedFDB201 + AReservedFDB301 + AReservedFDB401 + AI32x4Mul + AI32x4MinS + AI32x4MinU + AI32x4MaxS + AI32x4MaxU + AI32x4DotI16x8S + AReservedFDBB01 + AI32x4ExtmulLowI16x8S + AI32x4ExtmulHighI16x8S + AI32x4ExtmulLowI16x8U + AI32x4ExtmulHighI16x8U + AI64x2Abs + AI64x2Neg + AReservedFDC201 + AI64x2AllTrue + AI64x2Bitmask + AReservedFDC501 + AReservedFDC601 + AI64x2ExtendLowI32x4S + AI64x2ExtendHighI32x4S + AI64x2ExtendLowI32x4U + AI64x2ExtendHighI32x4U + AI64x2Shl + AI64x2ShrS + AI64x2ShrU + AI64x2Add + AReservedFDCF01 + AReservedFDD001 + AI64x2Sub + AReservedFDD201 + AReservedFDD301 + AReservedFDD401 + AI64x2Mul + AI64x2Eq + AI64x2Ne + AI64x2LtS + AI64x2GtS + AI64x2LeS + AI64x2GeS + AI64x2ExtmulLowI32x4S + AI64x2ExtmulHighI32x4S + AI64x2ExtmulLowI32x4U + AI64x2ExtmulHighI32x4U + AF32x4Abs + AF32x4Neg + AReservedFDE201 + AF32x4Sqrt + AF32x4Add + AF32x4Sub + AF32x4Mul + AF32x4Div + AF32x4Min + AF32x4Max + AF32x4Pmin + AF32x4Pmax + AF64x2Abs + AF64x2Neg + AReservedFDEE01 + AF64x2Sqrt + AF64x2Add + AF64x2Sub + AF64x2Mul + AF64x2Div + AF64x2Min + AF64x2Max + AF64x2Pmin + AF64x2Pmax + AI32x4TruncSatF32x4S + AI32x4TruncSatF32x4U + AF32x4ConvertI32x4S + AF32x4ConvertI32x4U + AI32x4TruncSatF64x2SZero + AI32x4TruncSatF64x2UZero + AF64x2ConvertLowI32x4S + AF64x2ConvertLowI32x4U + + // WASM Vector instructions 0xFD 0x80 and following but followed by a 0x02 + // e.g. 0xFD 0x80 0x02, 0xFD 0x81 0x02, etc. + AI8x16RelaxedSwizzle + AI32x4RelaxedTruncF32x4S + AI32x4RelaxedTruncF32x4U + AI32x4RelaxedTruncF64x2S + AI32x4RelaxedTruncF64x2U + AF32x4RelaxedMadd + AF32x4RelaxedNmadd + AF64x2RelaxedMadd + AF64x2RelaxedNmadd + AI8x16RelaxedLaneselect + AI16x8RelaxedLaneselect + AI32x4RelaxedLaneselect + AI64x2RelaxedLaneselect + AF32x4RelaxedMin + AF32x4RelaxedMax + AF64x2RelaxedMin + AF64x2RelaxedMax + AI16x8RelaxedQ15MulrS + AI16x8RelaxedDotI8x16I7x16S + AI32x4RelaxedDotI8x16I7x16AddS + ALast // Sentinel: End of low-level WebAssembly instructions. ARESUMEPOINT @@ -330,6 +614,24 @@ const ( REG_F30 REG_F31 + // v128 locals + REG_V0 + REG_V1 + REG_V2 + REG_V3 + REG_V4 + REG_V5 + REG_V6 + REG_V7 + REG_V8 + REG_V9 + REG_V10 + REG_V11 + REG_V12 + REG_V13 + REG_V14 + REG_V15 + REG_PC_B // also first parameter, i32 MAXREG diff --git a/src/cmd/internal/obj/wasm/anames.go b/src/cmd/internal/obj/wasm/anames.go index 6f1a6629602800..03990fbffc7e3f 100644 --- a/src/cmd/internal/obj/wasm/anames.go +++ b/src/cmd/internal/obj/wasm/anames.go @@ -1,4 +1,4 @@ -// Code generated by stringer -i a.out.go -o anames.go -p wasm; DO NOT EDIT. +// Code generated by go run ../stringer.go -i a.out.go -o anames.go -p wasm; DO NOT EDIT. package wasm @@ -204,6 +204,282 @@ var Anames = []string{ "TableGrow", "TableSize", "TableFill", + "V128Load", + "V128Load8x8S", + "V128Load8x8U", + "V128Load16x4S", + "V128Load16x4U", + "V128Load32x2S", + "V128Load32x2U", + "V128Load8Splat", + "V128Load16Splat", + "V128Load32Splat", + "V128Load64Splat", + "V128Store", + "V128Const", + "I8x16Shuffle16", + "I8x16Swizzle", + "I8x16Splat", + "I16x8Splat", + "I32x4Splat", + "I64x2Splat", + "F32x4Splat", + "F64x2Splat", + "I8x16ExtractLaneS", + "I8x16ExtractLaneU", + "I8x16ReplaceLane", + "I16x8ExtractLaneS", + "I16x8ExtractLaneU", + "I16x8ReplaceLane", + "I32x4ExtractLane", + "I32x4ReplaceLane", + "I64x2ExtractLane", + "I64x2ReplaceLane", + "F32x4ExtractLane", + "F32x4ReplaceLane", + "F64x2ExtractLane", + "F64x2ReplaceLane", + "I8x16Eq", + "I8x16Ne", + "I8x16LtS", + "I8x16LtU", + "I8x16GtS", + "I8x16GtU", + "I8x16LeS", + "I8x16LeU", + "I8x16GeS", + "I8x16GeU", + "I16x8Eq", + "I16x8Ne", + "I16x8LtS", + "I16x8LtU", + "I16x8GtS", + "I16x8GtU", + "I16x8LeS", + "I16x8LeU", + "I16x8GeS", + "I16x8GeU", + "I32x4Eq", + "I32x4Ne", + "I32x4LtS", + "I32x4LtU", + "I32x4GtS", + "I32x4GtU", + "I32x4LeS", + "I32x4LeU", + "I32x4GeS", + "I32x4GeU", + "F32x4Eq", + "F32x4Ne", + "F32x4Lt", + "F32x4Gt", + "F32x4Le", + "F32x4Ge", + "F64x2Eq", + "F64x2Ne", + "F64x2Lt", + "F64x2Gt", + "F64x2Le", + "F64x2Ge", + "V128Not", + "V128And", + "V128Andnot", + "V128Or", + "V128Xor", + "V128Bitselect", + "V128AnyTrue", + "V128Load8Lane", + "V128Load16Lane", + "V128Load32Lane", + "V128Load64Lane", + "V128Store8Lane", + "V128Store16Lane", + "V128Store32Lane", + "V128Store64Lane", + "V128Load32Zero", + "V128Load64Zero", + "F32x4DemoteF64x2Zero", + "F64x2PromoteLowF32x4", + "I8x16Abs", + "I8x16Neg", + "I8x16Popcnt", + "I8x16AllTrue", + "I8x16Bitmask", + "I8x16NarrowI16x8S", + "I8x16NarrowI16x8U", + "F32x4Ceil", + "F32x4Floor", + "F32x4Trunc", + "F32x4Nearest", + "I8x16Shl", + "I8x16ShrS", + "I8x16ShrU", + "I8x16Add", + "I8x16AddSatS", + "I8x16AddSatU", + "I8x16Sub", + "I8x16SubSatS", + "I8x16SubSatU", + "F64x2Ceil", + "F64x2Floor", + "I8x16MinS", + "I8x16MinU", + "I8x16MaxS", + "I8x16MaxU", + "F64x2Trunc", + "I8x16AvgrU", + "I16x8ExtaddPairwiseI8x16S", + "I16x8ExtaddPairwiseI8x16U", + "I32x4ExtaddPairwiseI16x8S", + "I32x4ExtaddPairwiseI16x8U", + "I16x8Abs", + "I16x8Neg", + "I16x8Q15MulrSatS", + "I16x8AllTrue", + "I16x8Bitmask", + "I16x8NarrowI32x4S", + "I16x8NarrowI32x4U", + "I16x8ExtendLowI8x16S", + "I16x8ExtendHighI8x16S", + "I16x8ExtendLowI8x16U", + "I16x8ExtendHighI8x16U", + "I16x8Shl", + "I16x8ShrS", + "I16x8ShrU", + "I16x8Add", + "I16x8AddSatS", + "I16x8AddSatU", + "I16x8Sub", + "I16x8SubSatS", + "I16x8SubSatU", + "F64x2Nearest", + "I16x8Mul", + "I16x8MinS", + "I16x8MinU", + "I16x8MaxS", + "I16x8MaxU", + "ReservedFD9A01", + "I16x8AvgrU", + "I16x8ExtmulLowI8x16S", + "I16x8ExtmulHighI8x16S", + "I16x8ExtmulLowI8x16U", + "I16x8ExtmulHighI8x16U", + "I32x4Abs", + "I32x4Neg", + "ReservedFDA201", + "I32x4AllTrue", + "I32x4Bitmask", + "ReservedFDA501", + "ReservedFDA601", + "I32x4ExtendLowI16x8S", + "I32x4ExtendHighI16x8S", + "I32x4ExtendLowI16x8U", + "I32x4ExtendHighI16x8U", + "I32x4Shl", + "I32x4ShrS", + "I32x4ShrU", + "I32x4Add", + "ReservedFDAF01", + "ReservedFDB001", + "I32x4Sub", + "ReservedFDB201", + "ReservedFDB301", + "ReservedFDB401", + "I32x4Mul", + "I32x4MinS", + "I32x4MinU", + "I32x4MaxS", + "I32x4MaxU", + "I32x4DotI16x8S", + "ReservedFDBB01", + "I32x4ExtmulLowI16x8S", + "I32x4ExtmulHighI16x8S", + "I32x4ExtmulLowI16x8U", + "I32x4ExtmulHighI16x8U", + "I64x2Abs", + "I64x2Neg", + "ReservedFDC201", + "I64x2AllTrue", + "I64x2Bitmask", + "ReservedFDC501", + "ReservedFDC601", + "I64x2ExtendLowI32x4S", + "I64x2ExtendHighI32x4S", + "I64x2ExtendLowI32x4U", + "I64x2ExtendHighI32x4U", + "I64x2Shl", + "I64x2ShrS", + "I64x2ShrU", + "I64x2Add", + "ReservedFDCF01", + "ReservedFDD001", + "I64x2Sub", + "ReservedFDD201", + "ReservedFDD301", + "ReservedFDD401", + "I64x2Mul", + "I64x2Eq", + "I64x2Ne", + "I64x2LtS", + "I64x2GtS", + "I64x2LeS", + "I64x2GeS", + "I64x2ExtmulLowI32x4S", + "I64x2ExtmulHighI32x4S", + "I64x2ExtmulLowI32x4U", + "I64x2ExtmulHighI32x4U", + "F32x4Abs", + "F32x4Neg", + "ReservedFDE201", + "F32x4Sqrt", + "F32x4Add", + "F32x4Sub", + "F32x4Mul", + "F32x4Div", + "F32x4Min", + "F32x4Max", + "F32x4Pmin", + "F32x4Pmax", + "F64x2Abs", + "F64x2Neg", + "ReservedFDEE01", + "F64x2Sqrt", + "F64x2Add", + "F64x2Sub", + "F64x2Mul", + "F64x2Div", + "F64x2Min", + "F64x2Max", + "F64x2Pmin", + "F64x2Pmax", + "I32x4TruncSatF32x4S", + "I32x4TruncSatF32x4U", + "F32x4ConvertI32x4S", + "F32x4ConvertI32x4U", + "I32x4TruncSatF64x2SZero", + "I32x4TruncSatF64x2UZero", + "F64x2ConvertLowI32x4S", + "F64x2ConvertLowI32x4U", + "I8x16RelaxedSwizzle", + "I32x4RelaxedTruncF32x4S", + "I32x4RelaxedTruncF32x4U", + "I32x4RelaxedTruncF64x2S", + "I32x4RelaxedTruncF64x2U", + "F32x4RelaxedMadd", + "F32x4RelaxedNmadd", + "F64x2RelaxedMadd", + "F64x2RelaxedNmadd", + "I8x16RelaxedLaneselect", + "I16x8RelaxedLaneselect", + "I32x4RelaxedLaneselect", + "I64x2RelaxedLaneselect", + "F32x4RelaxedMin", + "F32x4RelaxedMax", + "F64x2RelaxedMin", + "F64x2RelaxedMax", + "I16x8RelaxedQ15MulrS", + "I16x8RelaxedDotI8x16I7x16S", + "I32x4RelaxedDotI8x16I7x16AddS", "Last", "RESUMEPOINT", "CALLNORESUME", diff --git a/src/cmd/internal/obj/wasm/wasmobj.go b/src/cmd/internal/obj/wasm/wasmobj.go index 011294597a4de5..9de841d63e7097 100644 --- a/src/cmd/internal/obj/wasm/wasmobj.go +++ b/src/cmd/internal/obj/wasm/wasmobj.go @@ -77,6 +77,23 @@ var Register = map[string]int16{ "F30": REG_F30, "F31": REG_F31, + "V0": REG_V0, + "V1": REG_V1, + "V2": REG_V2, + "V3": REG_V3, + "V4": REG_V4, + "V5": REG_V5, + "V6": REG_V6, + "V7": REG_V7, + "V8": REG_V8, + "V9": REG_V9, + "V10": REG_V10, + "V11": REG_V11, + "V12": REG_V12, + "V13": REG_V13, + "V14": REG_V14, + "V15": REG_V15, + "PC_B": REG_PC_B, } @@ -584,7 +601,8 @@ func preprocess(ctxt *obj.Link, s *obj.LSym, newprog obj.ProgAlloc) { } } - case AI32Load, AI64Load, AF32Load, AF64Load, AI32Load8S, AI32Load8U, AI32Load16S, AI32Load16U, AI64Load8S, AI64Load8U, AI64Load16S, AI64Load16U, AI64Load32S, AI64Load32U: + case AI32Load, AI64Load, AF32Load, AF64Load, AI32Load8S, AI32Load8U, AI32Load16S, AI32Load16U, + AI64Load8S, AI64Load8U, AI64Load16S, AI64Load16U, AI64Load32S, AI64Load32U, AV128Load: if p.From.Type == obj.TYPE_MEM { as := p.As from := p.From @@ -804,6 +822,8 @@ func genWasmImportWrapper(s *obj.LSym, appendp func(p *obj.Prog, as obj.As, args p = appendp(p, AF32Load, constAddr(loadOffset)) case obj.WasmF64: p = appendp(p, AF64Load, constAddr(loadOffset)) + case obj.WasmV128: + p = appendp(p, AV128Load, constAddr(loadOffset)) case obj.WasmPtr: p = appendp(p, AI32Load, constAddr(loadOffset)) case obj.WasmBool: @@ -853,6 +873,11 @@ func genWasmImportWrapper(s *obj.LSym, appendp func(p *obj.Prog, as obj.As, args p = appendp(p, AGet, regAddr(REG_SP)) p = appendp(p, AGet, regAddr(REG_F16)) p = appendp(p, AF64Store, constAddr(storeOffset)) + case obj.WasmV128: + p = appendp(p, ASet, regAddr(REG_V0)) + p = appendp(p, AGet, regAddr(REG_SP)) + p = appendp(p, AGet, regAddr(REG_V0)) + p = appendp(p, AV128Store, constAddr(storeOffset)) case obj.WasmPtr: p = appendp(p, AI64ExtendI32U) p = appendp(p, ASet, regAddr(REG_R0)) @@ -917,6 +942,8 @@ func genWasmExportWrapper(s *obj.LSym, appendp func(p *obj.Prog, as obj.As, args p = appendp(p, AF32Store, constAddr(f.Offset)) case obj.WasmF64: p = appendp(p, AF64Store, constAddr(f.Offset)) + case obj.WasmV128: + p = appendp(p, AV128Store, constAddr(f.Offset)) case obj.WasmPtr: p = appendp(p, AI64ExtendI32U) p = appendp(p, AI64Store, constAddr(f.Offset)) @@ -978,6 +1005,8 @@ func genWasmExportWrapper(s *obj.LSym, appendp func(p *obj.Prog, as obj.As, args p = appendp(p, AF32Load, constAddr(f.Offset)) case obj.WasmF64: p = appendp(p, AF64Load, constAddr(f.Offset)) + case obj.WasmV128: + p = appendp(p, AV128Load, constAddr(f.Offset)) case obj.WasmPtr: p = appendp(p, AI32Load, constAddr(f.Offset)) case obj.WasmBool: @@ -1118,7 +1147,7 @@ func assemble(ctxt *obj.Link, s *obj.LSym, newprog obj.ProgAlloc) { } regs := []int16{REG_SP} - for reg := int16(REG_R0); reg <= REG_F31; reg++ { + for reg := int16(REG_R0); reg <= REG_V15; reg++ { if regUsed[reg-MINREG] { regs = append(regs, reg) } @@ -1228,6 +1257,13 @@ func assemble(ctxt *obj.Link, s *obj.LSym, newprog obj.ProgAlloc) { case obj.ANOP, obj.ATEXT, obj.AFUNCDATA, obj.APCDATA: // ignore continue + + case AV128Const: + writeOpcode(w, AV128Const) + // Despite what the spec implies, this is the format of a 128-bit constant. + writeLE64(w, p.From.Offset) + writeLE64(w, p.To.Offset) + continue } writeOpcode(w, p.As) @@ -1283,6 +1319,22 @@ func assemble(ctxt *obj.Link, s *obj.LSym, newprog obj.ProgAlloc) { panic("bad type for Call") } + case AI8x16ExtractLaneS, + AI8x16ExtractLaneU, + AI8x16ReplaceLane, + AI16x8ExtractLaneS, + AI16x8ExtractLaneU, + AI16x8ReplaceLane, + AI32x4ExtractLane, + AI32x4ReplaceLane, + AI64x2ExtractLane, + AI64x2ReplaceLane, + AF32x4ExtractLane, + AF32x4ReplaceLane, + AF64x2ExtractLane, + AF64x2ReplaceLane: + writeUleb128(w, uint64(p.To.Offset)) + case ACallIndirect: writeUleb128(w, uint64(p.To.Offset)) w.WriteByte(0x00) // reserved value @@ -1314,12 +1366,13 @@ func assemble(ctxt *obj.Link, s *obj.LSym, newprog obj.ProgAlloc) { binary.LittleEndian.PutUint64(b, math.Float64bits(p.From.Val.(float64))) w.Write(b) - case AI32Load, AI64Load, AF32Load, AF64Load, AI32Load8S, AI32Load8U, AI32Load16S, AI32Load16U, AI64Load8S, AI64Load8U, AI64Load16S, AI64Load16U, AI64Load32S, AI64Load32U: + case AI32Load, AI64Load, AF32Load, AF64Load, AI32Load8S, AI32Load8U, AI32Load16S, AI32Load16U, + AI64Load8S, AI64Load8U, AI64Load16S, AI64Load16U, AI64Load32S, AI64Load32U, AV128Load: if p.From.Offset < 0 { panic("negative offset for *Load") } if p.From.Type != obj.TYPE_CONST { - panic("bad type for *Load") + panic(fmt.Errorf("bad type for *Load, wanted TYPE_CONST, got %v", p.From.Type)) } if p.From.Offset > math.MaxUint32 { ctxt.Diag("bad offset in %v", p) @@ -1327,11 +1380,11 @@ func assemble(ctxt *obj.Link, s *obj.LSym, newprog obj.ProgAlloc) { writeUleb128(w, align(p.As)) writeUleb128(w, uint64(p.From.Offset)) - case AI32Store, AI64Store, AF32Store, AF64Store, AI32Store8, AI32Store16, AI64Store8, AI64Store16, AI64Store32: + case AI32Store, AI64Store, AF32Store, AF64Store, AI32Store8, AI32Store16, AI64Store8, AI64Store16, AI64Store32, AV128Store: if p.To.Offset < 0 { panic("negative offset") } - if p.From.Offset > math.MaxUint32 { + if p.To.Offset > math.MaxUint32 { ctxt.Diag("bad offset in %v", p) } writeUleb128(w, align(p.As)) @@ -1373,9 +1426,21 @@ func writeOpcode(w *bytes.Buffer, as obj.As) { w.WriteByte(byte(as - ALocalGet + 0x20)) case as < AI32TruncSatF32S: w.WriteByte(byte(as - AI32Load + 0x28)) - case as < ALast: + case as < AV128Load: w.WriteByte(0xFC) w.WriteByte(byte(as - AI32TruncSatF32S + 0x00)) + case as < AI16x8Abs: // [AV128Load, AI16x8Abs) + w.WriteByte(0xFD) + writeUleb128(w, uint64(as-AV128Load+0x00)) + case as < AI8x16RelaxedSwizzle: // [AI16x8Abs, AI8x16RelaxedSwizzle) + w.WriteByte(0xFD) + writeUleb128(w, uint64(as-AI16x8Abs+0x80)) + w.WriteByte(0x01) + case as <= AI32x4RelaxedDotI8x16I7x16AddS: // [AI8x16RelaxedSwizzle, AI32x4RelaxedDotI8x16I7x16AddS] + w.WriteByte(0xFD) + writeUleb128(w, uint64(as-AI8x16RelaxedSwizzle+0x80)) + w.WriteByte(0x02) + default: panic(fmt.Sprintf("unexpected assembler op: %s", as)) } @@ -1384,10 +1449,11 @@ func writeOpcode(w *bytes.Buffer, as obj.As) { type valueType byte const ( - i32 valueType = 0x7F - i64 valueType = 0x7E - f32 valueType = 0x7D - f64 valueType = 0x7C + i32 valueType = 0x7F + i64 valueType = 0x7E + f32 valueType = 0x7D + f64 valueType = 0x7C + v128 valueType = 0x7b ) func regType(reg int16) valueType { @@ -1400,6 +1466,8 @@ func regType(reg int16) valueType { return f32 case reg >= REG_F16 && reg <= REG_F31: return f64 + case reg >= REG_V0 && reg <= REG_V15: + return v128 default: panic("invalid register") } @@ -1415,6 +1483,8 @@ func align(as obj.As) uint64 { return 2 case AI64Load, AF64Load, AI64Store, AF64Store: return 3 + case AV128Load, AV128Store: + return 0 // TODO do we want more alignment default: panic("align: bad op") } @@ -1450,3 +1520,10 @@ func writeSleb128(w io.ByteWriter, v int64) { w.WriteByte(c) } } + +func writeLE64(w io.ByteWriter, v int64) { + for i := 0; i < 8; i++ { + w.WriteByte(uint8(v & 0xff)) + v >>= 8 + } +} diff --git a/src/cmd/internal/obj/x86/asm6.go b/src/cmd/internal/obj/x86/asm6.go index 4110fd7d8a7425..89b64f4eedd8ea 100644 --- a/src/cmd/internal/obj/x86/asm6.go +++ b/src/cmd/internal/obj/x86/asm6.go @@ -484,8 +484,7 @@ var ymovq = []ytab{ // valid only in 64-bit mode, usually with 64-bit prefix {Zr_m, 1, argList{Yrl, Yml}}, // 0x89 {Zm_r, 1, argList{Yml, Yrl}}, // 0x8b - {Zilo_m, 2, argList{Ys32, Yrl}}, // 32 bit signed 0xc7,(0) - {Ziq_rp, 1, argList{Yi64, Yrl}}, // 0xb8 -- 32/64 bit immediate + {Ziq_rp, 1, argList{Yi64, Yrl}}, // 0xb8 -- 32/64 bit immediate (Ziq_rp picks 5/7/10-byte form) {Zilo_m, 2, argList{Yi32, Yml}}, // 0xc7,(0) {Zm_r_xm, 1, argList{Ymm, Ymr}}, // 0x6e MMX MOVD {Zr_m_xm, 1, argList{Ymr, Ymm}}, // 0x7e MMX MOVD @@ -1225,7 +1224,7 @@ var optab = {AMOVNTPD, yxr_ml, Pe, opBytes{0x2b}}, {AMOVNTPS, yxr_ml, Pm, opBytes{0x2b}}, {AMOVNTQ, ymr_ml, Pm, opBytes{0xe7}}, - {AMOVQ, ymovq, Pw8, opBytes{0x6f, 0x7f, Pf2, 0xd6, Pf3, 0x7e, Pe, 0xd6, 0x89, 0x8b, 0xc7, 00, 0xb8, 0xc7, 00, 0x6e, 0x7e, Pe, 0x6e, Pe, 0x7e, 0}}, + {AMOVQ, ymovq, Pw8, opBytes{0x6f, 0x7f, Pf2, 0xd6, Pf3, 0x7e, Pe, 0xd6, 0x89, 0x8b, 0xb8, 0xc7, 00, 0x6e, 0x7e, Pe, 0x6e, Pe, 0x7e, 0}}, {AMOVQOZX, ymrxr, Pf3, opBytes{0xd6, 0x7e}}, {AMOVSB, ynone, Pb, opBytes{0xa4}}, {AMOVSD, yxmov, Pf2, opBytes{0x10, 0x11}}, @@ -2266,7 +2265,16 @@ func instinit(ctxt *obj.Link) { switch ctxt.Headtype { case objabi.Hplan9: + // _privates is a special symbol on Plan 9 that + // points to per–process private data (like TLS area). + // See https://9p.io/magic/man2html/2/exec . + // The assembler inserts a reference to this symbol + // for accessing the G. Mark it as linkname so it is + // allowed to access from anywhere. (Would be nice to + // mark it external, but we don't have a mechanism for + // that.) plan9privates = ctxt.Lookup("_privates") + plan9privates.Set(obj.AttrLinkname, true) } for i := range avxOptab { diff --git a/src/cmd/internal/obj/x86/obj6.go b/src/cmd/internal/obj/x86/obj6.go index 48287546b38769..8125acfa2967ff 100644 --- a/src/cmd/internal/obj/x86/obj6.go +++ b/src/cmd/internal/obj/x86/obj6.go @@ -236,7 +236,7 @@ func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { // Rewrite float constants to values stored in memory. switch p.As { // Convert AMOVSS $(0), Xx to AXORPS Xx, Xx - case AMOVSS: + case AMOVSS, AVMOVSS: if p.From.Type == obj.TYPE_FCONST { // f == 0 can't be used here due to -0, so use Float64bits if f := p.From.Val.(float64); math.Float64bits(f) == 0 { @@ -272,7 +272,7 @@ func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { p.From.Offset = 0 } - case AMOVSD: + case AMOVSD, AVMOVSD: // Convert AMOVSD $(0), Xx to AXORPS Xx, Xx if p.From.Type == obj.TYPE_FCONST { // f == 0 can't be used here due to -0, so use Float64bits @@ -423,8 +423,12 @@ func rewriteToUseGot(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { q.From.Reg = reg } } - if p.GetFrom3() != nil && p.GetFrom3().Name == obj.NAME_EXTERN { - ctxt.Diag("don't know how to handle %v with -dynlink", p) + from3 := p.GetFrom3() + for i := range p.RestArgs { + a := &p.RestArgs[i].Addr + if a != from3 && a.Name == obj.NAME_EXTERN && !a.Sym.Local() { + ctxt.Diag("don't know how to handle %v with -dynlink", p) + } } var source *obj.Addr // MOVx sym, Ry becomes $MOV sym@GOT, R15; MOVx (R15), Ry @@ -434,9 +438,17 @@ func rewriteToUseGot(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { if p.To.Name == obj.NAME_EXTERN && !p.To.Sym.Local() { ctxt.Diag("cannot handle NAME_EXTERN on both sides in %v with -dynlink", p) } + if from3 != nil && from3.Name == obj.NAME_EXTERN && !from3.Sym.Local() { + ctxt.Diag("cannot handle NAME_EXTERN on multiple operands in %v with -dynlink", p) + } source = &p.From } else if p.To.Name == obj.NAME_EXTERN && !p.To.Sym.Local() { + if from3 != nil && from3.Name == obj.NAME_EXTERN && !from3.Sym.Local() { + ctxt.Diag("cannot handle NAME_EXTERN on multiple operands in %v with -dynlink", p) + } source = &p.To + } else if from3 != nil && from3.Name == obj.NAME_EXTERN && !from3.Sym.Local() { + source = from3 } else { return } @@ -501,9 +513,7 @@ func rewriteToUseGot(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { p2.As = p.As p2.From = p.From p2.To = p.To - if from3 := p.GetFrom3(); from3 != nil { - p2.AddRestSource(*from3) - } + p2.RestArgs = p.RestArgs if p.From.Name == obj.NAME_EXTERN { p2.From.Reg = reg p2.From.Name = obj.NAME_NONE @@ -512,6 +522,11 @@ func rewriteToUseGot(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { p2.To.Reg = reg p2.To.Name = obj.NAME_NONE p2.To.Sym = nil + } else if p.GetFrom3() != nil && p.GetFrom3().Name == obj.NAME_EXTERN { + from3 = p2.GetFrom3() + from3.Reg = reg + from3.Name = obj.NAME_NONE + from3.Sym = nil } else { return } @@ -835,7 +850,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { p.Spadj = +autoffset } - if p.To.Sym != nil { // retjmp + if p.As == obj.ARET && (p.To.Sym != nil || p.To.Type == obj.TYPE_REG) { // retjmp p.As = obj.AJMP } } diff --git a/src/cmd/internal/obj/x86/seh.go b/src/cmd/internal/obj/x86/seh.go index ceca94936367a2..19ff0a4c8a7976 100644 --- a/src/cmd/internal/obj/x86/seh.go +++ b/src/cmd/internal/obj/x86/seh.go @@ -148,6 +148,7 @@ func populateSeh(ctxt *obj.Link, s *obj.LSym) (sehsym *obj.LSym) { symname := fmt.Sprintf("%d.%s", len(buf.data), hash) return ctxt.LookupInit("go:sehuw."+symname, func(s *obj.LSym) { s.WriteBytes(ctxt, 0, buf.data) + s.Align = 4 s.Type = objabi.SSEHUNWINDINFO s.Set(obj.AttrDuplicateOK, true) s.Set(obj.AttrLocal, true) diff --git a/src/cmd/internal/objabi/flag.go b/src/cmd/internal/objabi/flag.go index 8709c4e5cf530e..ae56e2b0b08b05 100644 --- a/src/cmd/internal/objabi/flag.go +++ b/src/cmd/internal/objabi/flag.go @@ -40,11 +40,12 @@ func Flagparse(usage func()) { // expandArgs expands "response files" arguments in the provided slice. // // A "response file" argument starts with '@' and the rest of that -// argument is a filename with CR-or-CRLF-separated arguments. Each -// argument in the named files can also contain response file -// arguments. See Issue 18468. +// argument is a filename with arguments. Arguments are separated by +// whitespace, and can use single quotes (literal) or double quotes +// (with escape sequences). Each argument in the named files can also +// contain response file arguments. See Issue 77177. // -// The returned slice 'out' aliases 'in' iff the input did not contain +// The returned slice 'out' aliases 'in' if the input did not contain // any response file arguments. // // TODO: handle relative paths of recursive expansions in different directories? @@ -61,10 +62,7 @@ func expandArgs(in []string) (out []string) { if err != nil { log.Fatal(err) } - args := strings.Split(strings.TrimSpace(strings.ReplaceAll(string(slurp), "\r", "")), "\n") - for i, arg := range args { - args[i] = DecodeArg(arg) - } + args := ParseArgs(slurp) out = append(out, expandArgs(args)...) } else if out != nil { out = append(out, s) @@ -76,6 +74,130 @@ func expandArgs(in []string) (out []string) { return } +// ParseArgs parses response file content into arguments using GCC-compatible rules. +// Arguments are separated by whitespace. Single quotes preserve content literally. +// Double quotes allow escape sequences: \\, \", \$, \`, and backslash-newline +// for line continuation (both LF and CRLF). Outside quotes, backslash escapes the +// next character, backslash-newline is line continuation (both LF and CRLF). +// We aim to follow GCC's buildargv implementation. +// Source code: https://github.com/gcc-mirror/gcc/blob/releases/gcc-15.2.0/libiberty/argv.c#L167 +// Known deviations from GCC: +// - CRLF is treated as line continuation to be Windows-friendly; GCC only recognizes LF. +// - Obsolete \f and \v are not treated as whitespaces +// This function is public to test with cmd/go/internal/work.encodeArg +func ParseArgs(s []byte) []string { + var args []string + var arg strings.Builder + hasArg := false // tracks if we've started an argument (for empty quotes) + inSingleQuote := false + inDoubleQuote := false + i := 0 + + for i < len(s) { + c := s[i] + + if inSingleQuote { + if c == '\'' { + inSingleQuote = false + } else { + arg.WriteByte(c) // No escape processing in single quotes + } + i++ + continue + } + + if inDoubleQuote { + if c == '\\' && i+1 < len(s) { + next := s[i+1] + switch next { + case '\\': + arg.WriteByte('\\') + i += 2 + case '"': + arg.WriteByte('"') + i += 2 + case '$': + arg.WriteByte('$') + i += 2 + case '`': + arg.WriteByte('`') + i += 2 + case '\n': + // Line continuation - skip backslash and newline + i += 2 + case '\r': + // Line continuation for CRLF - skip backslash, CR, and LF + if i+2 < len(s) && s[i+2] == '\n' { + i += 3 + } else { + arg.WriteByte(c) + i++ + } + default: + // Unknown escape - keep backslash and char + arg.WriteByte(c) + i++ + } + } else if c == '"' { + inDoubleQuote = false + i++ + } else { + arg.WriteByte(c) + i++ + } + continue + } + + // Normal mode (outside quotes) + switch c { + case ' ', '\t', '\n', '\r': + if arg.Len() > 0 || hasArg { + args = append(args, arg.String()) + arg.Reset() + hasArg = false + } + case '\'': + inSingleQuote = true + hasArg = true // Empty quotes still produce an arg + case '"': + inDoubleQuote = true + hasArg = true // Empty quotes still produce an arg + case '\\': + // Backslash escapes the next character outside quotes. + // Backslash-newline is line continuation (handles both LF and CRLF). + if i+1 < len(s) { + next := s[i+1] + if next == '\n' { + i += 2 + continue + } + if next == '\r' && i+2 < len(s) && s[i+2] == '\n' { + i += 3 + continue + } + // Backslash escapes the next character + arg.WriteByte(next) + hasArg = true + i += 2 + continue + } + // Trailing backslash at end of input — consumed and discarded + i++ + continue + default: + arg.WriteByte(c) + } + i++ + } + + // Don't forget the last argument + if arg.Len() > 0 || hasArg { + args = append(args, arg.String()) + } + + return args +} + func AddVersionFlag() { flag.Var(versionFlag{}, "V", "print version and exit") } @@ -85,7 +207,7 @@ var buildID string // filled in by linker type versionFlag struct{} func (versionFlag) IsBoolFlag() bool { return true } -func (versionFlag) Get() interface{} { return nil } +func (versionFlag) Get() any { return nil } func (versionFlag) String() string { return "" } func (versionFlag) Set(s string) error { name := os.Args[0] @@ -95,16 +217,10 @@ func (versionFlag) Set(s string) error { p := "" - if s == "goexperiment" { - // test/run.go uses this to discover the full set of - // experiment tags. Report everything. - p = " X:" + strings.Join(buildcfg.Experiment.All(), ",") - } else { - // If the enabled experiments differ from the baseline, - // include that difference. - if goexperiment := buildcfg.Experiment.String(); goexperiment != "" { - p = " X:" + goexperiment - } + // If the enabled experiments differ from the baseline, + // include that difference. + if goexperiment := buildcfg.Experiment.String(); goexperiment != "" { + p = " X:" + goexperiment } // The go command invokes -V=full to get a unique identifier @@ -148,7 +264,7 @@ func (c *count) Set(s string) error { return nil } -func (c *count) Get() interface{} { +func (c *count) Get() any { return int(*c) } @@ -169,45 +285,11 @@ func (f fn1) Set(s string) error { func (f fn1) String() string { return "" } -// DecodeArg decodes an argument. -// -// This function is public for testing with the parallel encoder. -func DecodeArg(arg string) string { - // If no encoding, fastpath out. - if !strings.ContainsAny(arg, "\\\n") { - return arg - } - - var b strings.Builder - var wasBS bool - for _, r := range arg { - if wasBS { - switch r { - case '\\': - b.WriteByte('\\') - case 'n': - b.WriteByte('\n') - default: - // This shouldn't happen. The only backslashes that reach here - // should encode '\n' and '\\' exclusively. - panic("badly formatted input") - } - } else if r == '\\' { - wasBS = true - continue - } else { - b.WriteRune(r) - } - wasBS = false - } - return b.String() -} - type debugField struct { name string help string - concurrentOk bool // true if this field/flag is compatible with concurrent compilation - val interface{} // *int or *string + concurrentOk bool // true if this field/flag is compatible with concurrent compilation + val any // *int or *string } type DebugFlag struct { @@ -234,7 +316,7 @@ type DebugSSA func(phase, flag string, val int, valString string) string // // If debugSSA is non-nil, any debug flags of the form ssa/... will be // passed to debugSSA for processing. -func NewDebugFlag(debug interface{}, debugSSA DebugSSA) *DebugFlag { +func NewDebugFlag(debug any, debugSSA DebugSSA) *DebugFlag { flag := &DebugFlag{ tab: make(map[string]debugField), debugSSA: debugSSA, diff --git a/src/cmd/internal/objabi/flag_test.go b/src/cmd/internal/objabi/flag_test.go index 935b9c2193124e..f9bedbb08e2e98 100644 --- a/src/cmd/internal/objabi/flag_test.go +++ b/src/cmd/internal/objabi/flag_test.go @@ -4,23 +4,57 @@ package objabi -import "testing" +import ( + "slices" + "testing" +) -func TestDecodeArg(t *testing.T) { +func TestParseArgs(t *testing.T) { t.Parallel() tests := []struct { - arg, want string + name string + input string + want []string }{ - {"", ""}, - {"hello", "hello"}, - {"hello\\n", "hello\n"}, - {"hello\\nthere", "hello\nthere"}, - {"hello\\\\there", "hello\\there"}, - {"\\\\\\n", "\\\n"}, + // GCC-compatibility test cases from test-expandargv.c + // Source code: https://github.com/gcc-mirror/gcc/blob/releases/gcc-15.2.0/libiberty/testsuite/test-expandargv.c#L72 + {`crlf`, "a\r\nb", []string{"a", "b"}}, // test 0 + {"newline", "a\nb", []string{"a", "b"}}, // test 1 + {"null byte in arg", "a\x00b", []string{"a\x00b"}}, // test 2: GCC parser gives ["a"] + {"null byte only", "\x00", []string{"\x00"}}, // test 3: GCC parser gives [] + {"leading newline", "\na\nb", []string{"a", "b"}}, // test 4 + {"empty quotes", "a\n''\nb", []string{"a", "", "b"}}, // test 5 + {"quoted newlines", "a\n'a\n\nb'\nb", []string{"a", "a\n\nb", "b"}}, // test 6 + {"single quote no escapes", "'a\\$VAR' '\\\"'", []string{"a\\$VAR", "\\\""}}, // test 7 + {"line continuation", "\"ab\\\ncd\" ef\\\ngh", []string{"abcd", "efgh"}}, // test 8 + // test 8.1 (additional verification for Windows line separators) + {"line continuation crlf", "\"ab\\\r\ncd\" ef\\\r\ngh", []string{"abcd", "efgh"}}, + {"double quote escapes", "\"\\$VAR\" \"\\`\" \"\\\"\" \"\\\\\" \"\\n\" \"\\t\"", + []string{"$VAR", "`", `"`, `\`, `\n`, `\t`}}, // test 9 + {"whitespace only", "\t \n \t ", nil}, // test 10 + {"single space", " ", nil}, // test 11 + {"multiple spaces", " ", nil}, // test 12 + + // Additional edge cases for peace of mind + {"basic split", "a b c", []string{"a", "b", "c"}}, + {"tabs", "a\tb\tc", []string{"a", "b", "c"}}, + {"mixed quotes", `a 'b c' "d e"`, []string{"a", "b c", "d e"}}, + {"adjacent quotes", `'a'"b"`, []string{"ab"}}, // no whitespace - no split + {"empty input", "", nil}, + {"empty single quotes", "''", []string{""}}, + {"empty double quotes", `""`, []string{""}}, + {"nested quotes in single", `'"hello"'`, []string{`"hello"`}}, + {"nested quotes in double", `"'hello'"`, []string{"'hello'"}}, + // GCC-specific (differs from LLVM): backslash outside quotes escapes the next character + {"backslash escape outside quotes", `\abc`, []string{"abc"}}, + {"trailing backslash", `abc\`, []string{"abc"}}, } - for _, test := range tests { - if got := DecodeArg(test.arg); got != test.want { - t.Errorf("decodoeArg(%q) = %q, want %q", test.arg, got, test.want) - } + for _, tt := range tests { + t.Run(tt.name, func(t *testing.T) { + got := ParseArgs([]byte(tt.input)) + if !slices.Equal(got, tt.want) { + t.Errorf("parseArgs(%q) = %q, want %q", tt.input, got, tt.want) + } + }) } } diff --git a/src/cmd/internal/objabi/pkgspecial.go b/src/cmd/internal/objabi/pkgspecial.go index 94efa6883bd3e3..d7e147b3ce0bd8 100644 --- a/src/cmd/internal/objabi/pkgspecial.go +++ b/src/cmd/internal/objabi/pkgspecial.go @@ -55,7 +55,6 @@ var runtimePkgs = []string{ "internal/runtime/gc/scan", "internal/runtime/maps", "internal/runtime/math", - "internal/runtime/strconv", "internal/runtime/sys", "internal/runtime/syscall/linux", "internal/runtime/syscall/windows", @@ -71,6 +70,7 @@ var runtimePkgs = []string{ "internal/goexperiment", "internal/goos", "internal/profilerecord", + "internal/strconv", "internal/stringslite", } @@ -99,6 +99,7 @@ var allowAsmABIPkgs = []string{ "internal/runtime/syscall/linux", "internal/runtime/syscall/windows", "internal/runtime/startlinetest", + "internal/runtime/maps", } // LookupPkgSpecial returns special build properties for the given package path. diff --git a/src/cmd/internal/objabi/reloctype.go b/src/cmd/internal/objabi/reloctype.go index 2fbd19e20c82c5..0fafbd4baa6306 100644 --- a/src/cmd/internal/objabi/reloctype.go +++ b/src/cmd/internal/objabi/reloctype.go @@ -327,13 +327,24 @@ const ( // Loong64. - // R_LOONG64_ADDR_HI resolves to the sign-adjusted "upper" 20 bits (bit 5-24) of an - // external address, by encoding it into the instruction. + // R_LOONG64_ADDR_HI resolves [31...12]bits of 32/64-bit PC-relative offset of an + // external address, by encoding it into addi.w/addi.d instruction // R_LOONG64_ADDR_LO resolves to the low 12 bits of an external address, by encoding - // it into the instruction. + // it into pcalau12i instruction. R_LOONG64_ADDR_HI R_LOONG64_ADDR_LO + // R_LOONG64_ADDR64_HI resolves [63...52]bits of 64-bit PC-relative offset of an + // external address, by encoding it into lu52i.d instruction + // R_LOONG64_ADDR64_LO resolves [51...32]bits of 64-bit PC-relative offset of an + // external address, by encoding it into lu32i.d instruction + R_LOONG64_ADDR64_HI + R_LOONG64_ADDR64_LO + + // R_LOONG64_ADDR_PCREL20_S2 resolves to the 22-bit, 4-byte aligned offset of an + // external address, by encoding it into a PCADDI instruction. + R_LOONG64_ADDR_PCREL20_S2 + // R_LOONG64_TLS_LE_HI resolves to the high 20 bits of a TLS address (offset from // thread pointer), by encoding it into the instruction. // R_LOONG64_TLS_LE_LO resolves to the low 12 bits of a TLS address (offset from @@ -341,35 +352,47 @@ const ( R_LOONG64_TLS_LE_HI R_LOONG64_TLS_LE_LO - // R_CALLLOONG64 resolves to non-PC-relative target address of a CALL (BL/JIRL) - // instruction, by encoding the address into the instruction. + // R_CALLLOONG64 resolves to the 28-bit 4-byte aligned PC-relative target + // address of a BL instruction, by encoding it into the instruction. R_CALLLOONG64 + // R_LOONG64_CALL36 resolves to the 38-bit 4-byte aligned PC-relative target + // address of a PCADDU18I + JIRL pair, by encoding it into the instructions. + R_LOONG64_CALL36 + // R_LOONG64_TLS_IE_HI and R_LOONG64_TLS_IE_LO relocates a pcalau12i, ld.d // pair to compute the address of the GOT slot of the tls symbol. R_LOONG64_TLS_IE_HI R_LOONG64_TLS_IE_LO - // R_LOONG64_GOT_HI and R_LOONG64_GOT_LO resolves a GOT-relative instruction sequence, - // usually an pcalau12i followed by another ld or addi instruction. + // R_LOONG64_GOT_HI resolves [31...12]bits of 32/64-bit PC-relative offset of + // GOT entry, by encoding it into pcalau12i instruction + // R_LOONG64_GOT_LO resolves [11...0]bits of 32/64-bit PC-relative offset of + // GOT entry, by encoding it into ld.w/ld.d instruction R_LOONG64_GOT_HI R_LOONG64_GOT_LO + // R_LOONG64_GOT64_HI resolves [63...52]bits of 64-bit PC-relative offset of + // GOT entry, by encoding it into lu52i.d instruction + // R_LOONG64_GOT64_LO resolves [51...32]bits of 64-bit PC-relative offset of + // GOT entry, by encoding it into lu32i.d instruction + R_LOONG64_GOT64_HI + R_LOONG64_GOT64_LO + // 64-bit in-place addition. R_LOONG64_ADD64 // 64-bit in-place subtraction. R_LOONG64_SUB64 - // R_JMP16LOONG64 resolves to 18-bit PC-relative target address of a JMP instructions. + // R_JMP16LOONG64 resolves to the 18-bit 4-byte aligned PC-relative target + // address of a BEQ/BNE/BLT/BGE/BLTU/BGEU instruction, by encoding it into + // the instruction. R_JMP16LOONG64 - // R_JMP21LOONG64 resolves to 23-bit PC-relative target address of a JMP instructions. + // R_JMP21LOONG64 resolves to the 23-bit 4-byte aligned PC-relative target + // address of a BEQZ/BNEZ instruction, by encoding it into the instruction. R_JMP21LOONG64 - // R_JMPLOONG64 resolves to non-PC-relative target address of a JMP instruction, - // by encoding the address into the instruction. - R_JMPLOONG64 - // R_ADDRMIPSU (only used on mips/mips64) resolves to the sign-adjusted "upper" 16 // bits (bit 16-31) of an external address, by encoding it into the instruction. R_ADDRMIPSU @@ -448,8 +471,6 @@ func (r RelocType) IsDirectJump() bool { switch r { case R_JMPMIPS: return true - case R_JMPLOONG64: - return true } return false } @@ -496,7 +517,7 @@ func FuncCountToDwTxtAddrFlavor(fncount int) (RelocType, int) { // // Background/motivation: let's say we have a package P with some // assembly functions (in "a.s") and some Go functions (in -// "b.go"). The compilation sequence used by the Go commmand will be: +// "b.go"). The compilation sequence used by the Go command will be: // // 1. run the assembler on a.s to generate a "symabis" file // 2. run the compiler on b.go passing it the symabis file and generating a "go_defs.h" asm header diff --git a/src/cmd/internal/objabi/reloctype_string.go b/src/cmd/internal/objabi/reloctype_string.go index 1ad1d0663305ab..c7a5e6c07af72d 100644 --- a/src/cmd/internal/objabi/reloctype_string.go +++ b/src/cmd/internal/objabi/reloctype_string.go @@ -86,39 +86,44 @@ func _() { _ = x[R_PCRELDBL-76] _ = x[R_LOONG64_ADDR_HI-77] _ = x[R_LOONG64_ADDR_LO-78] - _ = x[R_LOONG64_TLS_LE_HI-79] - _ = x[R_LOONG64_TLS_LE_LO-80] - _ = x[R_CALLLOONG64-81] - _ = x[R_LOONG64_TLS_IE_HI-82] - _ = x[R_LOONG64_TLS_IE_LO-83] - _ = x[R_LOONG64_GOT_HI-84] - _ = x[R_LOONG64_GOT_LO-85] - _ = x[R_LOONG64_ADD64-86] - _ = x[R_LOONG64_SUB64-87] - _ = x[R_JMP16LOONG64-88] - _ = x[R_JMP21LOONG64-89] - _ = x[R_JMPLOONG64-90] - _ = x[R_ADDRMIPSU-91] - _ = x[R_ADDRMIPSTLS-92] - _ = x[R_ADDRCUOFF-93] - _ = x[R_WASMIMPORT-94] - _ = x[R_XCOFFREF-95] - _ = x[R_PEIMAGEOFF-96] - _ = x[R_INITORDER-97] - _ = x[R_DWTXTADDR_U1-98] - _ = x[R_DWTXTADDR_U2-99] - _ = x[R_DWTXTADDR_U3-100] - _ = x[R_DWTXTADDR_U4-101] + _ = x[R_LOONG64_ADDR64_HI-79] + _ = x[R_LOONG64_ADDR64_LO-80] + _ = x[R_LOONG64_ADDR_PCREL20_S2-81] + _ = x[R_LOONG64_TLS_LE_HI-82] + _ = x[R_LOONG64_TLS_LE_LO-83] + _ = x[R_CALLLOONG64-84] + _ = x[R_LOONG64_CALL36-85] + _ = x[R_LOONG64_TLS_IE_HI-86] + _ = x[R_LOONG64_TLS_IE_LO-87] + _ = x[R_LOONG64_GOT_HI-88] + _ = x[R_LOONG64_GOT_LO-89] + _ = x[R_LOONG64_GOT64_HI-90] + _ = x[R_LOONG64_GOT64_LO-91] + _ = x[R_LOONG64_ADD64-92] + _ = x[R_LOONG64_SUB64-93] + _ = x[R_JMP16LOONG64-94] + _ = x[R_JMP21LOONG64-95] + _ = x[R_ADDRMIPSU-96] + _ = x[R_ADDRMIPSTLS-97] + _ = x[R_ADDRCUOFF-98] + _ = x[R_WASMIMPORT-99] + _ = x[R_XCOFFREF-100] + _ = x[R_PEIMAGEOFF-101] + _ = x[R_INITORDER-102] + _ = x[R_DWTXTADDR_U1-103] + _ = x[R_DWTXTADDR_U2-104] + _ = x[R_DWTXTADDR_U3-105] + _ = x[R_DWTXTADDR_U4-106] } -const _RelocType_name = "R_ADDRR_ADDRPOWERR_ADDRARM64R_ADDRMIPSR_ADDROFFR_SIZER_CALLR_CALLARMR_CALLARM64R_CALLINDR_CALLPOWERR_CALLMIPSR_CONSTR_PCRELR_TLS_LER_TLS_IER_GOTOFFR_PLT0R_PLT1R_PLT2R_USEFIELDR_USETYPER_USEIFACER_USEIFACEMETHODR_USENAMEDMETHODR_METHODOFFR_KEEPR_POWER_TOCR_GOTPCRELR_JMPMIPSR_DWARFSECREFR_ARM64_TLS_LER_ARM64_TLS_IER_ARM64_GOTPCRELR_ARM64_GOTR_ARM64_PCRELR_ARM64_PCREL_LDST8R_ARM64_PCREL_LDST16R_ARM64_PCREL_LDST32R_ARM64_PCREL_LDST64R_ARM64_LDST8R_ARM64_LDST16R_ARM64_LDST32R_ARM64_LDST64R_ARM64_LDST128R_POWER_TLS_LER_POWER_TLS_IER_POWER_TLSR_POWER_TLS_IE_PCREL34R_POWER_TLS_LE_TPREL34R_ADDRPOWER_DSR_ADDRPOWER_GOTR_ADDRPOWER_GOT_PCREL34R_ADDRPOWER_PCRELR_ADDRPOWER_TOCRELR_ADDRPOWER_TOCREL_DSR_ADDRPOWER_D34R_ADDRPOWER_PCREL34R_RISCV_JALR_RISCV_JAL_TRAMPR_RISCV_CALLR_RISCV_PCREL_ITYPER_RISCV_PCREL_STYPER_RISCV_TLS_IER_RISCV_TLS_LER_RISCV_GOT_HI20R_RISCV_GOT_PCREL_ITYPER_RISCV_PCREL_HI20R_RISCV_PCREL_LO12_IR_RISCV_PCREL_LO12_SR_RISCV_BRANCHR_RISCV_ADD32R_RISCV_SUB32R_RISCV_RVC_BRANCHR_RISCV_RVC_JUMPR_PCRELDBLR_LOONG64_ADDR_HIR_LOONG64_ADDR_LOR_LOONG64_TLS_LE_HIR_LOONG64_TLS_LE_LOR_CALLLOONG64R_LOONG64_TLS_IE_HIR_LOONG64_TLS_IE_LOR_LOONG64_GOT_HIR_LOONG64_GOT_LOR_LOONG64_ADD64R_LOONG64_SUB64R_JMP16LOONG64R_JMP21LOONG64R_JMPLOONG64R_ADDRMIPSUR_ADDRMIPSTLSR_ADDRCUOFFR_WASMIMPORTR_XCOFFREFR_PEIMAGEOFFR_INITORDERR_DWTXTADDR_U1R_DWTXTADDR_U2R_DWTXTADDR_U3R_DWTXTADDR_U4" +const _RelocType_name = "R_ADDRR_ADDRPOWERR_ADDRARM64R_ADDRMIPSR_ADDROFFR_SIZER_CALLR_CALLARMR_CALLARM64R_CALLINDR_CALLPOWERR_CALLMIPSR_CONSTR_PCRELR_TLS_LER_TLS_IER_GOTOFFR_PLT0R_PLT1R_PLT2R_USEFIELDR_USETYPER_USEIFACER_USEIFACEMETHODR_USENAMEDMETHODR_METHODOFFR_KEEPR_POWER_TOCR_GOTPCRELR_JMPMIPSR_DWARFSECREFR_ARM64_TLS_LER_ARM64_TLS_IER_ARM64_GOTPCRELR_ARM64_GOTR_ARM64_PCRELR_ARM64_PCREL_LDST8R_ARM64_PCREL_LDST16R_ARM64_PCREL_LDST32R_ARM64_PCREL_LDST64R_ARM64_LDST8R_ARM64_LDST16R_ARM64_LDST32R_ARM64_LDST64R_ARM64_LDST128R_POWER_TLS_LER_POWER_TLS_IER_POWER_TLSR_POWER_TLS_IE_PCREL34R_POWER_TLS_LE_TPREL34R_ADDRPOWER_DSR_ADDRPOWER_GOTR_ADDRPOWER_GOT_PCREL34R_ADDRPOWER_PCRELR_ADDRPOWER_TOCRELR_ADDRPOWER_TOCREL_DSR_ADDRPOWER_D34R_ADDRPOWER_PCREL34R_RISCV_JALR_RISCV_JAL_TRAMPR_RISCV_CALLR_RISCV_PCREL_ITYPER_RISCV_PCREL_STYPER_RISCV_TLS_IER_RISCV_TLS_LER_RISCV_GOT_HI20R_RISCV_GOT_PCREL_ITYPER_RISCV_PCREL_HI20R_RISCV_PCREL_LO12_IR_RISCV_PCREL_LO12_SR_RISCV_BRANCHR_RISCV_ADD32R_RISCV_SUB32R_RISCV_RVC_BRANCHR_RISCV_RVC_JUMPR_PCRELDBLR_LOONG64_ADDR_HIR_LOONG64_ADDR_LOR_LOONG64_ADDR64_HIR_LOONG64_ADDR64_LOR_LOONG64_ADDR_PCREL20_S2R_LOONG64_TLS_LE_HIR_LOONG64_TLS_LE_LOR_CALLLOONG64R_LOONG64_CALL36R_LOONG64_TLS_IE_HIR_LOONG64_TLS_IE_LOR_LOONG64_GOT_HIR_LOONG64_GOT_LOR_LOONG64_GOT64_HIR_LOONG64_GOT64_LOR_LOONG64_ADD64R_LOONG64_SUB64R_JMP16LOONG64R_JMP21LOONG64R_ADDRMIPSUR_ADDRMIPSTLSR_ADDRCUOFFR_WASMIMPORTR_XCOFFREFR_PEIMAGEOFFR_INITORDERR_DWTXTADDR_U1R_DWTXTADDR_U2R_DWTXTADDR_U3R_DWTXTADDR_U4" -var _RelocType_index = [...]uint16{0, 6, 17, 28, 38, 47, 53, 59, 68, 79, 88, 99, 109, 116, 123, 131, 139, 147, 153, 159, 165, 175, 184, 194, 210, 226, 237, 243, 254, 264, 273, 286, 300, 314, 330, 341, 354, 373, 393, 413, 433, 446, 460, 474, 488, 503, 517, 531, 542, 564, 586, 600, 615, 638, 655, 673, 694, 709, 728, 739, 756, 768, 787, 806, 820, 834, 850, 873, 891, 911, 931, 945, 958, 971, 989, 1005, 1015, 1032, 1049, 1068, 1087, 1100, 1119, 1138, 1154, 1170, 1185, 1200, 1214, 1228, 1240, 1251, 1264, 1275, 1287, 1297, 1309, 1320, 1334, 1348, 1362, 1376} +var _RelocType_index = [...]uint16{0, 6, 17, 28, 38, 47, 53, 59, 68, 79, 88, 99, 109, 116, 123, 131, 139, 147, 153, 159, 165, 175, 184, 194, 210, 226, 237, 243, 254, 264, 273, 286, 300, 314, 330, 341, 354, 373, 393, 413, 433, 446, 460, 474, 488, 503, 517, 531, 542, 564, 586, 600, 615, 638, 655, 673, 694, 709, 728, 739, 756, 768, 787, 806, 820, 834, 850, 873, 891, 911, 931, 945, 958, 971, 989, 1005, 1015, 1032, 1049, 1068, 1087, 1112, 1131, 1150, 1163, 1179, 1198, 1217, 1233, 1249, 1267, 1285, 1300, 1315, 1329, 1343, 1354, 1367, 1378, 1390, 1400, 1412, 1423, 1437, 1451, 1465, 1479} func (i RelocType) String() string { - i -= 1 - if i < 0 || i >= RelocType(len(_RelocType_index)-1) { - return "RelocType(" + strconv.FormatInt(int64(i+1), 10) + ")" + idx := int(i) - 1 + if i < 1 || idx >= len(_RelocType_index)-1 { + return "RelocType(" + strconv.FormatInt(int64(i), 10) + ")" } - return _RelocType_name[_RelocType_index[i]:_RelocType_index[i+1]] + return _RelocType_name[_RelocType_index[idx]:_RelocType_index[idx+1]] } diff --git a/src/cmd/internal/objabi/symkind_string.go b/src/cmd/internal/objabi/symkind_string.go index fbf6a826a4a757..a22f9a6a1cbfb2 100644 --- a/src/cmd/internal/objabi/symkind_string.go +++ b/src/cmd/internal/objabi/symkind_string.go @@ -41,8 +41,9 @@ const _SymKind_name = "SxxxSTEXTSTEXTFIPSSRODATASRODATAFIPSSNOPTRDATASNOPTRDATAF var _SymKind_index = [...]uint16{0, 4, 9, 18, 25, 36, 46, 60, 65, 74, 78, 87, 94, 106, 117, 126, 138, 148, 157, 168, 177, 188, 198, 221, 238, 254, 268} func (i SymKind) String() string { - if i >= SymKind(len(_SymKind_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_SymKind_index)-1 { return "SymKind(" + strconv.FormatInt(int64(i), 10) + ")" } - return _SymKind_name[_SymKind_index[i]:_SymKind_index[i+1]] + return _SymKind_name[_SymKind_index[idx]:_SymKind_index[idx+1]] } diff --git a/src/cmd/internal/objfile/elf.go b/src/cmd/internal/objfile/elf.go index 8923290cffefe8..6da31906b5f9a4 100644 --- a/src/cmd/internal/objfile/elf.go +++ b/src/cmd/internal/objfile/elf.go @@ -52,7 +52,11 @@ func (f *elfFile) symbols() ([]Sym, error) { case elf.SHF_ALLOC: sym.Code = 'R' case elf.SHF_ALLOC | elf.SHF_WRITE: - sym.Code = 'D' + if sect.Type == elf.SHT_NOBITS { + sym.Code = 'B' + } else { + sym.Code = 'D' + } } } if elf.ST_BIND(s.Info) == elf.STB_LOCAL { @@ -64,40 +68,26 @@ func (f *elfFile) symbols() ([]Sym, error) { return syms, nil } -func (f *elfFile) pcln() (textStart uint64, symtab, pclntab []byte, err error) { +func (f *elfFile) pcln() (textStart uint64, pclntab []byte, err error) { if sect := f.elf.Section(".text"); sect != nil { textStart = sect.Addr } - sect := f.elf.Section(".gosymtab") - if sect == nil { - // try .data.rel.ro.gosymtab, for PIE binaries - sect = f.elf.Section(".data.rel.ro.gosymtab") - } - if sect != nil { - if symtab, err = sect.Data(); err != nil { - return 0, nil, nil, err - } - } else { - // if both sections failed, try the symbol - symtab = f.symbolData("runtime.symtab", "runtime.esymtab") - } - - sect = f.elf.Section(".gopclntab") + sect := f.elf.Section(".gopclntab") if sect == nil { // try .data.rel.ro.gopclntab, for PIE binaries sect = f.elf.Section(".data.rel.ro.gopclntab") } if sect != nil { if pclntab, err = sect.Data(); err != nil { - return 0, nil, nil, err + return 0, nil, err } } else { // if both sections failed, try the symbol pclntab = f.symbolData("runtime.pclntab", "runtime.epclntab") } - return textStart, symtab, pclntab, nil + return textStart, pclntab, nil } func (f *elfFile) text() (textStart uint64, text []byte, err error) { diff --git a/src/cmd/internal/objfile/goobj.go b/src/cmd/internal/objfile/goobj.go index 7d564a2661d951..ec852d0669fac9 100644 --- a/src/cmd/internal/objfile/goobj.go +++ b/src/cmd/internal/objfile/goobj.go @@ -221,10 +221,10 @@ func (f *goobjFile) symbols() ([]Sym, error) { return syms, nil } -func (f *goobjFile) pcln() (textStart uint64, symtab, pclntab []byte, err error) { +func (f *goobjFile) pcln() (textStart uint64, pclntab []byte, err error) { // Should never be called. We implement Liner below, callers // should use that instead. - return 0, nil, nil, fmt.Errorf("pcln not available in go object file") + return 0, nil, fmt.Errorf("pcln not available in go object file") } // PCToLine returns the file name, line, and function data for the given pc. diff --git a/src/cmd/internal/objfile/macho.go b/src/cmd/internal/objfile/macho.go index 8258145f26f342..eaf665faee91e8 100644 --- a/src/cmd/internal/objfile/macho.go +++ b/src/cmd/internal/objfile/macho.go @@ -79,21 +79,16 @@ func (f *machoFile) symbols() ([]Sym, error) { return syms, nil } -func (f *machoFile) pcln() (textStart uint64, symtab, pclntab []byte, err error) { +func (f *machoFile) pcln() (textStart uint64, pclntab []byte, err error) { if sect := f.macho.Section("__text"); sect != nil { textStart = sect.Addr } - if sect := f.macho.Section("__gosymtab"); sect != nil { - if symtab, err = sect.Data(); err != nil { - return 0, nil, nil, err - } - } if sect := f.macho.Section("__gopclntab"); sect != nil { if pclntab, err = sect.Data(); err != nil { - return 0, nil, nil, err + return 0, nil, err } } - return textStart, symtab, pclntab, nil + return textStart, pclntab, nil } func (f *machoFile) text() (textStart uint64, text []byte, err error) { diff --git a/src/cmd/internal/objfile/objfile.go b/src/cmd/internal/objfile/objfile.go index ed9aae280e5579..32e06dfd991420 100644 --- a/src/cmd/internal/objfile/objfile.go +++ b/src/cmd/internal/objfile/objfile.go @@ -18,7 +18,7 @@ import ( type rawFile interface { symbols() (syms []Sym, err error) - pcln() (textStart uint64, symtab, pclntab []byte, err error) + pcln() (textStart uint64, pclntab []byte, err error) text() (textStart uint64, text []byte, err error) goarch() string loadAddress() (uint64, error) @@ -141,7 +141,7 @@ func (e *Entry) PCLineTable() (Liner, error) { return pcln, nil } // Otherwise, read the pcln tables and build a Liner out of that. - textStart, symtab, pclntab, err := e.raw.pcln() + textStart, pclntab, err := e.raw.pcln() if err != nil { return nil, err } @@ -154,7 +154,7 @@ func (e *Entry) PCLineTable() (Liner, error) { } } } - return gosym.NewTable(symtab, gosym.NewLineTable(pclntab, textStart)) + return gosym.NewTable(nil, gosym.NewLineTable(pclntab, textStart)) } func (e *Entry) Text() (uint64, []byte, error) { diff --git a/src/cmd/internal/objfile/pe.go b/src/cmd/internal/objfile/pe.go index c5c08264a9cdb0..7bbfaa54d1c4aa 100644 --- a/src/cmd/internal/objfile/pe.go +++ b/src/cmd/internal/objfile/pe.go @@ -34,6 +34,25 @@ func (f *peFile) symbols() ([]Sym, error) { imageBase, _ := f.imageBase() + // When using internal linking we currently put BSS into the + // .data section. In order to set the B code correctly, + // we find the address of runtime.bss. Anything in a data section + // past runtime.bss is a BSS symbol. + // + // Just checking the section size in insufficient, + // as it will be rounded up to the page size. + // That is, there can be BSS symbols at the end of the page + // that holds the last data symbols. + var bssAddr uint32 + var bssSectionNumber int16 + for _, s := range f.pe.Symbols { + if s.Name == "runtime.bss" { + bssAddr = s.Value + bssSectionNumber = s.SectionNumber + break + } + } + var syms []Sym for _, s := range f.pe.Symbols { const ( @@ -67,6 +86,12 @@ func (f *peFile) symbols() ([]Sym, error) { case ch&data != 0: if ch&permW == 0 { sym.Code = 'R' + } else if bssSectionNumber == s.SectionNumber && bssAddr > 0 && s.Value >= bssAddr { + // Past runtime.bss is BSS. + sym.Code = 'B' + } else if s.Value >= sect.Size { + // Past section size is BSS. + sym.Code = 'B' } else { sym.Code = 'D' } @@ -90,10 +115,10 @@ func (f *peFile) symbols() ([]Sym, error) { return syms, nil } -func (f *peFile) pcln() (textStart uint64, symtab, pclntab []byte, err error) { +func (f *peFile) pcln() (textStart uint64, pclntab []byte, err error) { imageBase, err := f.imageBase() if err != nil { - return 0, nil, nil, err + return 0, nil, err } if sect := f.pe.Section(".text"); sect != nil { @@ -104,17 +129,10 @@ func (f *peFile) pcln() (textStart uint64, symtab, pclntab []byte, err error) { // TODO: Remove code looking for the old symbols when we no longer care about 1.3. var err2 error if pclntab, err2 = loadPETable(f.pe, "pclntab", "epclntab"); err2 != nil { - return 0, nil, nil, err - } - } - if symtab, err = loadPETable(f.pe, "runtime.symtab", "runtime.esymtab"); err != nil { - // Same as above. - var err2 error - if symtab, err2 = loadPETable(f.pe, "symtab", "esymtab"); err2 != nil { - return 0, nil, nil, err + return 0, nil, err } } - return textStart, symtab, pclntab, nil + return textStart, pclntab, nil } func (f *peFile) text() (textStart uint64, text []byte, err error) { diff --git a/src/cmd/internal/objfile/plan9obj.go b/src/cmd/internal/objfile/plan9obj.go index c91970762c79ee..edd40230cec0c2 100644 --- a/src/cmd/internal/objfile/plan9obj.go +++ b/src/cmd/internal/objfile/plan9obj.go @@ -71,24 +71,17 @@ func (f *plan9File) symbols() ([]Sym, error) { return syms, nil } -func (f *plan9File) pcln() (textStart uint64, symtab, pclntab []byte, err error) { +func (f *plan9File) pcln() (textStart uint64, pclntab []byte, err error) { textStart = f.plan9.LoadAddress + f.plan9.HdrSize if pclntab, err = loadPlan9Table(f.plan9, "runtime.pclntab", "runtime.epclntab"); err != nil { // We didn't find the symbols, so look for the names used in 1.3 and earlier. // TODO: Remove code looking for the old symbols when we no longer care about 1.3. var err2 error if pclntab, err2 = loadPlan9Table(f.plan9, "pclntab", "epclntab"); err2 != nil { - return 0, nil, nil, err + return 0, nil, err } } - if symtab, err = loadPlan9Table(f.plan9, "runtime.symtab", "runtime.esymtab"); err != nil { - // Same as above. - var err2 error - if symtab, err2 = loadPlan9Table(f.plan9, "symtab", "esymtab"); err2 != nil { - return 0, nil, nil, err - } - } - return textStart, symtab, pclntab, nil + return textStart, pclntab, nil } func (f *plan9File) text() (textStart uint64, text []byte, err error) { diff --git a/src/cmd/internal/objfile/xcoff.go b/src/cmd/internal/objfile/xcoff.go index 24f42760c9dd60..85928621f1837c 100644 --- a/src/cmd/internal/objfile/xcoff.go +++ b/src/cmd/internal/objfile/xcoff.go @@ -87,15 +87,14 @@ func (f *xcoffFile) symbols() ([]Sym, error) { return syms, nil } -func (f *xcoffFile) pcln() (textStart uint64, symtab, pclntab []byte, err error) { +func (f *xcoffFile) pcln() (textStart uint64, pclntab []byte, err error) { if sect := f.xcoff.Section(".text"); sect != nil { textStart = sect.VirtualAddress } if pclntab, err = loadXCOFFTable(f.xcoff, "runtime.pclntab", "runtime.epclntab"); err != nil { - return 0, nil, nil, err + return 0, nil, err } - symtab, _ = loadXCOFFTable(f.xcoff, "runtime.symtab", "runtime.esymtab") // ignore error, this symbol is not useful anyway - return textStart, symtab, pclntab, nil + return textStart, pclntab, nil } func (f *xcoffFile) text() (textStart uint64, text []byte, err error) { diff --git a/src/cmd/internal/pgo/pprof.go b/src/cmd/internal/pgo/pprof.go index 5e61a11141c048..5bcd8c588d75e0 100644 --- a/src/cmd/internal/pgo/pprof.go +++ b/src/cmd/internal/pgo/pprof.go @@ -50,6 +50,12 @@ func FromPProf(r io.Reader) (*Profile, error) { SampleValue: func(v []int64) int64 { return v[valueIndex] }, }) + if len(g.Nodes) == 0 { + // If all sample values are 0, the graph will have no nodes. + // In this case, treat it as an empty profile. + return emptyProfile(), nil + } + namedEdgeMap, totalWeight, err := createNamedEdgeMap(g) if err != nil { return nil, err diff --git a/src/cmd/internal/script/cmds.go b/src/cmd/internal/script/cmds.go index a682d9b3f66863..7e2e507a02157e 100644 --- a/src/cmd/internal/script/cmds.go +++ b/src/cmd/internal/script/cmds.go @@ -468,6 +468,9 @@ func startCommand(s *State, name, path string, args []string, cancel func(*exec. wait := func(s *State) (stdout, stderr string, err error) { err = cmd.Wait() + if errors.Is(err, exec.ErrWaitDelay) { + err = fmt.Errorf("%w: output pipes not closed after waiting %v", err, cmd.WaitDelay) + } return stdoutBuf.String(), stderrBuf.String(), err } return wait, nil diff --git a/src/cmd/internal/script/conds.go b/src/cmd/internal/script/conds.go index 30759d2a58d48e..c9783dd1631fd4 100644 --- a/src/cmd/internal/script/conds.go +++ b/src/cmd/internal/script/conds.go @@ -38,7 +38,7 @@ func DefaultConds() map[string]Cond { return true, nil } if _, ok := syslist.KnownArch[suffix]; !ok { - return false, fmt.Errorf("unrecognized GOOS %q", suffix) + return false, fmt.Errorf("unrecognized GOARCH %q", suffix) } return false, nil }) diff --git a/src/cmd/internal/script/engine.go b/src/cmd/internal/script/engine.go index 4607868379488a..7ca2be1a770618 100644 --- a/src/cmd/internal/script/engine.go +++ b/src/cmd/internal/script/engine.go @@ -55,6 +55,8 @@ import ( "errors" "fmt" "io" + "maps" + "slices" "sort" "strings" "time" @@ -491,15 +493,13 @@ func expandArgs(s *State, rawArgs [][]argFragment, regexpArgs []int) []string { } // quoteArgs returns a string that parse would parse as args when passed to a command. -// -// TODO(bcmills): This function should have a fuzz test. func quoteArgs(args []string) string { var b strings.Builder for i, arg := range args { if i > 0 { b.WriteString(" ") } - if strings.ContainsAny(arg, "'"+argSepChars) { + if len(arg) == 0 || strings.ContainsAny(arg, "&'$"+argSepChars) { // Quote the argument to a form that would be parsed as a single argument. b.WriteString("'") b.WriteString(strings.ReplaceAll(arg, "'", "''")) @@ -518,7 +518,7 @@ func (e *Engine) conditionsActive(s *State, conds []condition) (bool, error) { if ok { impl = e.Conds[prefix] if impl == nil { - return false, fmt.Errorf("unknown condition prefix %q", prefix) + return false, fmt.Errorf("unknown condition prefix %q; known: %v", prefix, slices.Collect(maps.Keys(e.Conds))) } if !impl.Usage().Prefix { return false, fmt.Errorf("condition %q cannot be used with a suffix", prefix) @@ -578,23 +578,21 @@ func (e *Engine) runCommand(s *State, cmd *command, impl Cmd) error { return nil } - if wait != nil { - stdout, stderr, waitErr := wait(s) - s.stdout = stdout - s.stderr = stderr - if stdout != "" { - s.Logf("[stdout]\n%s", stdout) - } - if stderr != "" { - s.Logf("[stderr]\n%s", stderr) - } - if cmdErr := checkStatus(cmd, waitErr); cmdErr != nil { - return cmdErr - } - if waitErr != nil { - // waitErr was expected (by cmd.want), so log it instead of returning it. - s.Logf("[%v]\n", waitErr) - } + stdout, stderr, waitErr := wait(s) + s.stdout = stdout + s.stderr = stderr + if stdout != "" { + s.Logf("[stdout]\n%s", stdout) + } + if stderr != "" { + s.Logf("[stderr]\n%s", stderr) + } + if cmdErr := checkStatus(cmd, waitErr); cmdErr != nil { + return cmdErr + } + if waitErr != nil { + // waitErr was expected (by cmd.want), so log it instead of returning it. + s.Logf("[%v]\n", waitErr) } return nil } diff --git a/src/cmd/internal/script/engine_test.go b/src/cmd/internal/script/engine_test.go new file mode 100644 index 00000000000000..45d0a0faf9d2e2 --- /dev/null +++ b/src/cmd/internal/script/engine_test.go @@ -0,0 +1,35 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package script + +import ( + "context" + "slices" + "testing" +) + +func FuzzQuoteArgs(f *testing.F) { + state, err := NewState(context.Background(), f.TempDir(), nil /* env */) + if err != nil { + f.Fatalf("failed to create state: %v", err) + } + + f.Add("foo") + f.Add(`"foo"`) + f.Add(`'foo'`) + f.Fuzz(func(t *testing.T, s string) { + give := []string{s} + quoted := quoteArgs(give) + cmd, err := parse("file.txt", 42, "cmd "+quoted) + if err != nil { + t.Fatalf("quoteArgs(%q) = %q cannot be parsed: %v", give, quoted, err) + } + args := expandArgs(state, cmd.rawArgs, nil /* regexpArgs */) + + if !slices.Equal(give, args) { + t.Fatalf("quoteArgs failed to round-trip.\ninput:\n\t%#q\nquoted:\n\t%q\nparsed:\n\t%#q", give, quoted, args) + } + }) +} diff --git a/src/cmd/internal/script/scripttest/readme.go b/src/cmd/internal/script/scripttest/readme.go index af7397223f5574..8f333b06c2ecb0 100644 --- a/src/cmd/internal/script/scripttest/readme.go +++ b/src/cmd/internal/script/scripttest/readme.go @@ -37,6 +37,7 @@ func checkScriptReadme(t *testing.T, engine *script.Engine, env []string, script doc := new(strings.Builder) cmd := testenv.Command(t, gotool, "doc", "cmd/internal/script") + cmd.Dir = t.TempDir() // make sure the test is not running inside the std or cmd module of another GOROOT cmd.Env = env cmd.Stdout = doc if err := cmd.Run(); err != nil { diff --git a/src/cmd/internal/script/scripttest/run.go b/src/cmd/internal/script/scripttest/run.go index 8dff13e22edfc4..ecd91b84be2ad7 100644 --- a/src/cmd/internal/script/scripttest/run.go +++ b/src/cmd/internal/script/scripttest/run.go @@ -12,6 +12,7 @@ import ( "fmt" "internal/testenv" "internal/txtar" + "io/fs" "os" "os/exec" "path/filepath" @@ -29,12 +30,9 @@ type ToolReplacement struct { EnvVar string // env var setting (e.g. "FOO=BAR") } -// RunToolScriptTest kicks off a set of script tests runs for -// a tool of some sort (compiler, linker, etc). The expectation -// is that we'll be called from the top level cmd/X dir for tool X, -// and that instead of executing the install tool X we'll use the -// test binary instead. -func RunToolScriptTest(t *testing.T, repls []ToolReplacement, scriptsdir string, fixReadme bool) { +// NewEngine constructs a new [script.Engine] and environment to be used with +// [RunTests]. +func NewEngine(t *testing.T, repls []ToolReplacement) (*script.Engine, []string) { // Nearly all script tests involve doing builds, so don't // bother here if we don't have "go build". testenv.MustHaveGoBuild(t) @@ -106,9 +104,17 @@ func RunToolScriptTest(t *testing.T, repls []ToolReplacement, scriptsdir string, } interrupt := func(cmd *exec.Cmd) error { + // TODO(thepudds): currently cmd/go/script_test.go uses a platform-specific cancel + // that we could consider emulating here. return cmd.Process.Signal(os.Interrupt) } - gracePeriod := 60 * time.Second // arbitrary + + // Customize the subprocess termination grace period to reduce flakes on busy builders (#76685). + // The grace period is the max of 100ms or 5% of the time remaining until any t.Deadline. + gracePeriod := subprocessGracePeriod(t.Deadline()) + + cmdExec := script.Exec(interrupt, gracePeriod) + cmds["exec"] = cmdExec // Set up an alternate go root for running script tests, since it // is possible that we might want to replace one of the installed @@ -126,7 +132,6 @@ func RunToolScriptTest(t *testing.T, repls []ToolReplacement, scriptsdir string, testgo := filepath.Join(tgr, "bin", "go") gocmd := script.Program(testgo, interrupt, gracePeriod) addcmd("go", gocmd) - cmdExec := cmds["exec"] addcmd("cc", scriptCC(cmdExec, goEnv("CC"))) // Add various helpful conditions related to builds and toolchain use. @@ -137,6 +142,9 @@ func RunToolScriptTest(t *testing.T, repls []ToolReplacement, scriptsdir string, env := os.Environ() prependToPath(env, filepath.Join(tgr, "bin")) env = setenv(env, "GOROOT", tgr) + // GOOS and GOARCH are expected to be set by the toolchain script conditions. + env = setenv(env, "GOOS", runtime.GOOS) + env = setenv(env, "GOARCH", runtime.GOARCH) for _, repl := range repls { // consistency check chunks := strings.Split(repl.EnvVar, "=") @@ -153,6 +161,23 @@ func RunToolScriptTest(t *testing.T, repls []ToolReplacement, scriptsdir string, Quiet: !testing.Verbose(), } + return engine, env +} + +// RunToolScriptTest kicks off a set of script tests runs for +// a tool of some sort (compiler, linker, etc). The expectation +// is that we'll be called from the top level cmd/X dir for tool X, +// and that instead of executing the install tool X we'll use the +// test binary instead. +func RunToolScriptTest(t *testing.T, repls []ToolReplacement, scriptsdir string, fixReadme bool) { + // Locate our Go tool. + gotool, err := testenv.GoTool() + if err != nil { + t.Fatalf("locating go tool: %v", err) + } + + engine, env := NewEngine(t, repls) + t.Run("README", func(t *testing.T) { checkScriptReadme(t, engine, env, scriptsdir, gotool, fixReadme) }) @@ -163,36 +188,56 @@ func RunToolScriptTest(t *testing.T, repls []ToolReplacement, scriptsdir string, RunTests(t, ctx, engine, env, pattern) } +// ScriptTestContext returns a context with a grace period for cleaning up +// subprocesses of a script test. +// +// When we run commands that execute subprocesses, we want to reserve two grace +// periods to clean up. We will send the first termination signal when the +// context expires, then wait one grace period for the process to produce +// whatever useful output it can (such as a stack trace). After the first grace +// period expires, we'll escalate to os.Kill, leaving the second grace period +// for the test function to record its output before the test process itself +// terminates. +// +// The grace period is 100ms or 5% of the time remaining until +// [testing.T.Deadline], whichever is greater. +func ScriptTestContext(t *testing.T, ctx context.Context) context.Context { + deadline, ok := t.Deadline() + if !ok { + return ctx + } + + gracePeriod := subprocessGracePeriod(deadline, ok) + + // Reserve two grace periods to clean up + timeout := time.Until(deadline) + timeout -= 2 * gracePeriod + + ctx, cancel := context.WithTimeout(ctx, timeout) + t.Cleanup(cancel) + return ctx +} + +// subprocessGracePeriod returns a grace period for terminating subprocesses +// created by the commands of a script test. +func subprocessGracePeriod(deadline time.Time, hasDeadline bool) time.Duration { + gracePeriod := 100 * time.Millisecond // arbitrary + if !hasDeadline { + return gracePeriod + } + + // If time allows, increase the termination grace period to 5% of the + // remaining time. + timeout := time.Until(deadline) + return max(gracePeriod, timeout/20) +} + // RunTests kicks off one or more script-based tests using the // specified engine, running all test files that match pattern. // This function adapted from Russ's rsc.io/script/scripttest#Run // function, which was in turn forked off cmd/go's runner. func RunTests(t *testing.T, ctx context.Context, engine *script.Engine, env []string, pattern string) { - gracePeriod := 100 * time.Millisecond - if deadline, ok := t.Deadline(); ok { - timeout := time.Until(deadline) - - // If time allows, increase the termination grace period to 5% of the - // remaining time. - if gp := timeout / 20; gp > gracePeriod { - gracePeriod = gp - } - - // When we run commands that execute subprocesses, we want to - // reserve two grace periods to clean up. We will send the - // first termination signal when the context expires, then - // wait one grace period for the process to produce whatever - // useful output it can (such as a stack trace). After the - // first grace period expires, we'll escalate to os.Kill, - // leaving the second grace period for the test function to - // record its output before the test process itself - // terminates. - timeout -= 2 * gracePeriod - - var cancel context.CancelFunc - ctx, cancel = context.WithTimeout(ctx, timeout) - t.Cleanup(cancel) - } + ctx = ScriptTestContext(t, ctx) files, _ := filepath.Glob(pattern) if len(files) == 0 { @@ -210,12 +255,17 @@ func RunTests(t *testing.T, ctx context.Context, engine *script.Engine, env []st t.Fatal(err) } + // Call fixPermissions at the end of the test case in case + // it uses the go modcache, which writes read-only files. + // fixPermissions fixes up the permissions so a later removal can succeed. + defer fixPermissions(t, workdir) + // Unpack archive. a, err := txtar.ParseFile(file) if err != nil { t.Fatal(err) } - initScriptDirs(t, s) + InitScriptDirs(t, s) if err := s.ExtractFiles(a); err != nil { t.Fatal(err) } @@ -234,7 +284,27 @@ func RunTests(t *testing.T, ctx context.Context, engine *script.Engine, env []st } } -func initScriptDirs(t testing.TB, s *script.State) { +func fixPermissions(t *testing.T, dir string) { + t.Helper() + + // module cache has 0444 directories; + // make them writable in order to remove content. + filepath.WalkDir(dir, func(path string, info fs.DirEntry, err error) error { + // chmod not only directories, but also things that we couldn't even stat + // due to permission errors: they may also be unreadable directories. + if err != nil || info.IsDir() { + os.Chmod(path, 0777) + } + return nil + }) +} + +// InitScriptDirs sets up directories for executing a script test. +// +// - WORK (env var) is set to the current working directory. +// - TMPDIR (env var; TMP on Windows) is set to $WORK/tmp. +// - $TMPDIR is created. +func InitScriptDirs(t testing.TB, s *script.State) { must := func(err error) { if err != nil { t.Helper() diff --git a/src/cmd/internal/script/scripttest/scripttest.go b/src/cmd/internal/script/scripttest/scripttest.go index 349201fd188c1b..418b063b28618b 100644 --- a/src/cmd/internal/script/scripttest/scripttest.go +++ b/src/cmd/internal/script/scripttest/scripttest.go @@ -89,7 +89,7 @@ func Run(t testing.TB, e *script.Engine, s *script.State, filename string, testS return e.Execute(s, filename, bufio.NewReader(testScript), log) }() - if skip, ok := errors.AsType[skipError](err); ok { + if skip, ok := errors.AsType[SkipError](err); ok { if skip.msg == "" { t.Skip("SKIP") } else { @@ -113,17 +113,18 @@ func Skip() script.Cmd { return nil, script.ErrUsage } if len(args) == 0 { - return nil, skipError{""} + return nil, SkipError{""} } - return nil, skipError{args[0]} + return nil, SkipError{args[0]} }) } -type skipError struct { +// SkipError is returned by a script test that executes the [Skip] command. +type SkipError struct { msg string } -func (s skipError) Error() string { +func (s SkipError) Error() string { if s.msg == "" { return "skip" } diff --git a/src/cmd/internal/script/scripttest/setup.go b/src/cmd/internal/script/scripttest/setup.go index f9d650af1c48fc..07cf8ea2f914af 100644 --- a/src/cmd/internal/script/scripttest/setup.go +++ b/src/cmd/internal/script/scripttest/setup.go @@ -6,8 +6,10 @@ package scripttest import ( + "errors" "internal/testenv" "io" + "io/fs" "os" "path/filepath" "runtime" @@ -83,7 +85,7 @@ func ReplaceGoToolInTestGoRoot(t *testing.T, testgoroot, toolname, newtoolpath s exename += ".exe" } toolpath := filepath.Join(testgoroot, toolsub, exename) - if err := os.Remove(toolpath); err != nil { + if err := os.Remove(toolpath); err != nil && !errors.Is(err, fs.ErrNotExist) { t.Fatalf("removing %s: %v", toolpath, err) } linkOrCopy(t, newtoolpath, toolpath) diff --git a/src/cmd/internal/script/testdata/fuzz/FuzzQuoteArgs/2abacd54f8b6b056 b/src/cmd/internal/script/testdata/fuzz/FuzzQuoteArgs/2abacd54f8b6b056 new file mode 100644 index 00000000000000..8e2be246c5b259 --- /dev/null +++ b/src/cmd/internal/script/testdata/fuzz/FuzzQuoteArgs/2abacd54f8b6b056 @@ -0,0 +1,2 @@ +go test fuzz v1 +string("0\xa2$000") diff --git a/src/cmd/internal/script/testdata/fuzz/FuzzQuoteArgs/5838cdfae7b16cde b/src/cmd/internal/script/testdata/fuzz/FuzzQuoteArgs/5838cdfae7b16cde new file mode 100644 index 00000000000000..64c3abaff82f69 --- /dev/null +++ b/src/cmd/internal/script/testdata/fuzz/FuzzQuoteArgs/5838cdfae7b16cde @@ -0,0 +1,2 @@ +go test fuzz v1 +string("") diff --git a/src/cmd/internal/script/testdata/fuzz/FuzzQuoteArgs/e6019c3e89cc4df9 b/src/cmd/internal/script/testdata/fuzz/FuzzQuoteArgs/e6019c3e89cc4df9 new file mode 100644 index 00000000000000..67f8cfc58b0564 --- /dev/null +++ b/src/cmd/internal/script/testdata/fuzz/FuzzQuoteArgs/e6019c3e89cc4df9 @@ -0,0 +1,2 @@ +go test fuzz v1 +string("&") diff --git a/src/cmd/internal/src/xpos.go b/src/cmd/internal/src/xpos.go index a74505997d2cfd..77c08712ac15d5 100644 --- a/src/cmd/internal/src/xpos.go +++ b/src/cmd/internal/src/xpos.go @@ -7,6 +7,8 @@ package src +import "fmt" + // XPos is a more compact representation of Pos. type XPos struct { index int32 @@ -93,6 +95,14 @@ func (p XPos) LineNumber() string { return p.lico.lineNumber() } +// ColumnNumber returns a string for the column number, "?" if it is not known. +func (p XPos) ColumnNumber() string { + if !p.IsKnown() { + return "?" + } + return fmt.Sprintf("%d", p.lico.Col()) +} + // FileIndex returns a smallish non-negative integer corresponding to the // file for this source position. Smallish is relative; it can be thousands // large, but not millions. diff --git a/src/cmd/internal/sys/arch.go b/src/cmd/internal/sys/arch.go index 3c92a6bbf25619..2738fe3b54c9e5 100644 --- a/src/cmd/internal/sys/arch.go +++ b/src/cmd/internal/sys/arch.go @@ -143,7 +143,7 @@ var ArchLoong64 = &Arch{ PtrSize: 8, RegSize: 8, MinLC: 4, - Alignment: 8, // Unaligned accesses are not guaranteed to be fast + Alignment: 1, CanMergeLoads: true, CanJumpTable: true, HasLR: true, @@ -236,7 +236,7 @@ var ArchRISCV64 = &Arch{ ByteOrder: binary.LittleEndian, PtrSize: 8, RegSize: 8, - MinLC: 4, + MinLC: 2, Alignment: 8, // riscv unaligned loads work, but are really slow (trap + simulated by OS) CanMergeLoads: false, HasLR: true, diff --git a/src/cmd/internal/test2json/test2json.go b/src/cmd/internal/test2json/test2json.go index f28051e1771db8..f8aa93f3bba377 100644 --- a/src/cmd/internal/test2json/test2json.go +++ b/src/cmd/internal/test2json/test2json.go @@ -35,6 +35,7 @@ type event struct { Test string `json:",omitempty"` Elapsed *float64 `json:",omitempty"` Output *textBytes `json:",omitempty"` + OutputType string `json:",omitempty"` FailedBuild string `json:",omitempty"` Key string `json:",omitempty"` Value string `json:",omitempty"` @@ -53,16 +54,19 @@ func (b textBytes) MarshalText() ([]byte, error) { return b, nil } // It implements io.WriteCloser; the caller writes test output in, // and the converter writes JSON output to w. type Converter struct { - w io.Writer // JSON output stream - pkg string // package to name in events - mode Mode // mode bits - start time.Time // time converter started - testName string // name of current test, for output attribution - report []*event // pending test result reports (nested for subtests) - result string // overall test result if seen - input lineBuffer // input buffer - output lineBuffer // output buffer - needMarker bool // require ^V marker to introduce test framing line + w io.Writer // JSON output stream + pkg string // package to name in events + mode Mode // mode bits + start time.Time // time converter started + testName string // name of current test, for output attribution + report []*event // pending test result reports (nested for subtests) + result string // overall test result if seen + input lineBuffer // input buffer + output lineBuffer // output buffer + markFraming bool // require ^V marker to introduce test framing line + markErrEnd bool // within an error, require ^N marker to end + markEscape bool // the next character should be considered to be escaped + isFraming bool // indicates the output being written is framing // failedBuild is set to the package ID of the cause of a build failure, // if that's what caused this test to fail. @@ -97,6 +101,15 @@ var ( // Writes on the returned writer are written as JSON to w, // with minimal delay. // +// Writes on the returned writer are expected to contain markers. Test framing +// such as "=== RUN" and friends are expected to be prefixed with ^V (\x22). +// Error output is expected to be prefixed with ^O (\x0f) and suffixed with ^N +// (\x0e). Other occurrences of these control characters (e.g. calls to T.Log) +// must be escaped with ^[ (\x1b). Test framing will generate events such as +// start, run, etc as well as output events with an output type of "frame". +// Error output will generate output events with an output type of "error" or +// "error-continue". See cmd/test2json help for details. +// // The writes to w are whole JSON events ending in \n, // so that it is safe to run multiple tests writing to multiple converters // writing to a single underlying output stream w. @@ -155,7 +168,12 @@ func (c *Converter) SetFailedBuild(pkgID string) { c.failedBuild = pkgID } -const marker = byte(0x16) // ^V +const ( + markFraming byte = 'V' &^ '@' // ^V: framing + markErrBegin byte = 'O' &^ '@' // ^O: start of error + markErrEnd byte = 'N' &^ '@' // ^N: end of error + markEscape byte = '[' &^ '@' // ^[: escape +) var ( // printed by test on successful run. @@ -205,11 +223,11 @@ func (c *Converter) handleInputLine(line []byte) { return } sawMarker := false - if c.needMarker && line[0] != marker { + if c.markFraming && line[0] != markFraming { c.output.write(line) return } - if line[0] == marker { + if line[0] == markFraming { c.output.flush() sawMarker = true line = line[1:] @@ -234,8 +252,8 @@ func (c *Converter) handleInputLine(line []byte) { if bytes.Equal(trim, bigPass) || bytes.Equal(trim, bigFail) || bytes.HasPrefix(trim, bigFailErrorPrefix) { c.flushReport(0) c.testName = "" - c.needMarker = sawMarker - c.output.write(line) + c.markFraming = sawMarker + c.writeFraming(line) if bytes.Equal(trim, bigPass) { c.result = "pass" } else { @@ -323,12 +341,12 @@ func (c *Converter) handleInputLine(line []byte) { return } // Flush reports at this indentation level or deeper. - c.needMarker = sawMarker + c.markFraming = sawMarker c.flushReport(indent) e.Test = name c.testName = name c.report = append(c.report, e) - c.output.write(origLine) + c.writeFraming(origLine) return } switch action { @@ -341,7 +359,7 @@ func (c *Converter) handleInputLine(line []byte) { } // === update. // Finish any pending PASS/FAIL reports. - c.needMarker = sawMarker + c.markFraming = sawMarker c.flushReport(0) c.testName = name @@ -355,16 +373,24 @@ func (c *Converter) handleInputLine(line []byte) { // For a pause, we want to write the pause notification before // delivering the pause event, just so it doesn't look like the test // is generating output immediately after being paused. - c.output.write(origLine) + c.writeFraming(origLine) } c.writeEvent(e) if action != "pause" { - c.output.write(origLine) + c.writeFraming(origLine) } return } +func (c *Converter) writeFraming(line []byte) { + // This is a less than ideal way to 'pass' state around, but it's the best + // we can do without substantially modifying the line buffer. + c.isFraming = true + defer func() { c.isFraming = false }() + c.output.write(line) +} + // flushReport flushes all pending PASS/FAIL reports at levels >= depth. func (c *Converter) flushReport(depth int) { c.testName = "" @@ -397,10 +423,91 @@ func (c *Converter) Close() error { // writeOutputEvent writes a single output event with the given bytes. func (c *Converter) writeOutputEvent(out []byte) { - c.writeEvent(&event{ - Action: "output", - Output: (*textBytes)(&out), - }) + var typ string + if c.isFraming { + typ = "frame" + } else if c.markErrEnd { + typ = "error-continue" + } + + // Check for markers. + // + // An escape mark and the character it escapes may be passed in separate + // buffers. We must maintain state between calls to account for this, thus + // [Converter.markEscape] is set on one loop iteration and used to skip a + // character on the next. + // + // In most cases, [markErrBegin] will be the first character of a line and + // [markErrEnd] will be the last. However we cannot rely on that. For + // example, if a call to [T.Error] is preceded by a call to [fmt.Print] that + // does not print a newline. Thus we track the error status with + // [Converter.markErrEnd] and issue separate events if there is content + // before [markErrBegin] or after [markErrEnd]. + for i := 0; i < len(out); i++ { + if c.markEscape { + c.markEscape = false + continue + } + + switch out[i] { + case markEscape: + // Elide the mark + out = append(out[:i], out[i+1:]...) + i-- + + // Skip the next character + c.markEscape = true + + case markErrBegin: + // If there is content before the mark, emit it as a separate event + if i > 0 { + out2 := out[:i] + c.writeEvent(&event{ + Action: "output", + Output: (*textBytes)(&out2), + OutputType: typ, + }) + } + + // Process the error + c.markErrEnd = true + typ = "error" + out = out[i+1:] + i = 0 + + case markErrEnd: + // Elide the mark + out = append(out[:i], out[i+1:]...) + + // If the next character is \n, include it + if i < len(out) && out[i] == '\n' { + i++ + } + + // Emit the error + out2 := out[:i] + c.writeEvent(&event{ + Action: "output", + Output: (*textBytes)(&out2), + OutputType: typ, + }) + + // Process the rest + c.markErrEnd = false + typ = "" + out = out[i:] + i = 0 + } + } + + // Send the remaining output + if len(out) > 0 { + c.writeEvent(&event{ + Action: "output", + Output: (*textBytes)(&out), + OutputType: typ, + }) + } } // writeEvent writes a single event. @@ -435,10 +542,11 @@ func (c *Converter) writeEvent(e *event) { // calling part(x) for sections of the line. The line will be split at UTF8 boundaries, // and the final call to part for a long line includes the final newline. type lineBuffer struct { - b []byte // buffer - mid bool // whether we're in the middle of a long line - line func([]byte) // line callback - part func([]byte) // partial line callback + b []byte // buffer + mid bool // whether we're in the middle of a long line + line func([]byte) // line callback + part func([]byte) // partial line callback + escaped bool } // write writes b to the buffer. @@ -452,7 +560,7 @@ func (l *lineBuffer) write(b []byte) { // Process lines in l.b. i := 0 for i < len(l.b) { - j, w := indexEOL(l.b[i:]) + j, w := l.indexEOL(l.b[i:]) if j < 0 { if !l.mid { if j := bytes.IndexByte(l.b[i:], '\t'); j >= 0 { @@ -500,12 +608,26 @@ func (l *lineBuffer) write(b []byte) { // A line ending is either a \n or the empty string just before a ^V not beginning a line. // The output width for \n is 1 (meaning it should be printed) // but the output width for ^V is 0 (meaning it should be left to begin the next line). -func indexEOL(b []byte) (pos, wid int) { +func (l *lineBuffer) indexEOL(b []byte) (pos, wid int) { for i, c := range b { + // Escape has no effect on \n if c == '\n' { return i, 1 } - if c == marker && i > 0 { // test -v=json emits ^V at start of framing lines + + // Ignore this character if the previous one was ^[ + if l.escaped { + l.escaped = false + continue + } + + // If this character is `^[`, set the escaped flag and continue + if c == markEscape { + l.escaped = true + continue + } + + if c == markFraming && i > 0 { // test -v=json emits ^V at start of framing lines return i, 0 } } diff --git a/src/cmd/internal/test2json/test2json_test.go b/src/cmd/internal/test2json/test2json_test.go index c1aecc85e2fdfb..7f36a9f8762204 100644 --- a/src/cmd/internal/test2json/test2json_test.go +++ b/src/cmd/internal/test2json/test2json_test.go @@ -5,14 +5,22 @@ package test2json import ( + "bufio" "bytes" + "cmd/internal/script" + "cmd/internal/script/scripttest" + "context" "encoding/json" + "errors" "flag" "fmt" + "internal/txtar" "io" + "io/fs" "os" "path/filepath" "reflect" + "regexp" "strings" "testing" "unicode/utf8" @@ -21,6 +29,8 @@ import ( var update = flag.Bool("update", false, "rewrite testdata/*.json files") func TestGolden(t *testing.T) { + ctx := scripttest.ScriptTestContext(t, context.Background()) + engine, env := scripttest.NewEngine(t, nil) files, err := filepath.Glob("testdata/*.test") if err != nil { t.Fatal(err) @@ -33,6 +43,29 @@ func TestGolden(t *testing.T) { t.Fatal(err) } + // If there's a corresponding *.src script, execute it + srcFile := strings.TrimSuffix(file, ".test") + ".src" + if st, err := os.Stat(srcFile); err != nil { + if !errors.Is(err, fs.ErrNotExist) { + t.Fatal(err) + } + } else if !st.IsDir() { + t.Run("go test", func(t *testing.T) { + stdout := runTest(t, ctx, engine, env, srcFile) + + if *update { + t.Logf("rewriting %s", file) + if err := os.WriteFile(file, []byte(stdout), 0666); err != nil { + t.Fatal(err) + } + orig = []byte(stdout) + return + } + + diffRaw(t, []byte(stdout), orig) + }) + } + // Test one line written to c at a time. // Assume that's the most likely to be handled correctly. var buf bytes.Buffer @@ -141,6 +174,78 @@ func TestGolden(t *testing.T) { } } +func runTest(t *testing.T, ctx context.Context, engine *script.Engine, env []string, srcFile string) string { + workdir := t.TempDir() + s, err := script.NewState(ctx, workdir, env) + if err != nil { + t.Fatal(err) + } + + // Unpack archive. + a, err := txtar.ParseFile(srcFile) + if err != nil { + t.Fatal(err) + } + scripttest.InitScriptDirs(t, s) + if err := s.ExtractFiles(a); err != nil { + t.Fatal(err) + } + + err, stdout := func() (err error, stdout string) { + log := new(strings.Builder) + + // Defer writing to the test log in case the script engine panics during execution, + // but write the log before we write the final "skip" or "FAIL" line. + t.Helper() + defer func() { + t.Helper() + + stdout = s.Stdout() + if closeErr := s.CloseAndWait(log); err == nil { + err = closeErr + } + + if log.Len() > 0 && (testing.Verbose() || err != nil) { + t.Log(strings.TrimSuffix(log.String(), "\n")) + } + }() + + if testing.Verbose() { + // Add the environment to the start of the script log. + wait, err := script.Env().Run(s) + if err != nil { + t.Fatal(err) + } + if wait != nil { + stdout, stderr, err := wait(s) + if err != nil { + t.Fatalf("env: %v\n%s", err, stderr) + } + if len(stdout) > 0 { + s.Logf("%s\n", stdout) + } + } + } + + testScript := bytes.NewReader(a.Comment) + err = engine.Execute(s, srcFile, bufio.NewReader(testScript), log) + return + }() + if skip := (scripttest.SkipError{}); errors.As(err, &skip) { + t.Skipf("SKIP: %v", skip) + } else if err != nil { + t.Fatalf("FAIL: %v", err) + } + + // Remove the output after "=== NAME" + i := strings.LastIndex(stdout, "\n\x16=== NAME") + if i >= 0 { + stdout = stdout[:i+1] + } + + return stdout +} + // writeAndKill writes b to w and then fills b with Zs. // The filling makes sure that if w is holding onto b for // future use, that future use will have obviously wrong data. @@ -271,6 +376,56 @@ func diffJSON(t *testing.T, have, want []byte) { } } +var reRuntime = regexp.MustCompile(`\d*\.\d*s`) + +func diffRaw(t *testing.T, have, want []byte) { + have = bytes.TrimSpace(have) + want = bytes.TrimSpace(want) + + // Replace durations (e.g. 0.01s) with a placeholder + have = reRuntime.ReplaceAll(have, []byte("X.XXs")) + want = reRuntime.ReplaceAll(want, []byte("X.XXs")) + + // Compare + if bytes.Equal(have, want) { + return + } + + // Escape non-printing characters to make the error more legible + have = escapeNonPrinting(have) + want = escapeNonPrinting(want) + + // Find where the output differs and remember the last newline + var i, nl int + for i < len(have) && i < len(want) && have[i] == want[i] { + if have[i] == '\n' { + nl = i + } + } + + if nl == 0 { + t.Fatalf("\nhave:\n%s\nwant:\n%s", have, want) + } else { + nl++ + t.Fatalf("\nhave:\n%s» %s\nwant:\n%s» %s", have[:nl], have[nl:], want[:nl], want[nl:]) + } +} + +func escapeNonPrinting(buf []byte) []byte { + for i := 0; i < len(buf); i++ { + c := buf[i] + if 0x20 <= c && c < 0x7F || c > 0x7F || c == '\n' { + continue + } + escaped := fmt.Sprintf(`\x%02x`, c) + buf = append(buf[:i+len(escaped)], buf[i+1:]...) + for j := 0; j < len(escaped); j++ { + buf[i+j] = escaped[j] + } + } + return buf +} + func TestTrimUTF8(t *testing.T) { s := "hello α ☺ 😂 world" // α is 2-byte, ☺ is 3-byte, 😂 is 4-byte b := []byte(s) diff --git a/src/cmd/internal/test2json/testdata/README.md b/src/cmd/internal/test2json/testdata/README.md new file mode 100644 index 00000000000000..e86c88f51c8278 --- /dev/null +++ b/src/cmd/internal/test2json/testdata/README.md @@ -0,0 +1,11 @@ +# test2json test artifacts + +This directory contains test artifacts for `TestGolden` in +[test2json_test.go](../test2json_test.go). For each set of `.*` files: + +- If `.src` is present, TestGolden executes it as a script test and verifies + that the output matches `.test`. This verifies that the testing package + produces the output expected by test2json. +- TestGolden reads `.test` and processes it with a `Converter`, verifying + that the output matches `.json`.This verifies that test2json produces + the expected output events. \ No newline at end of file diff --git a/src/cmd/internal/test2json/testdata/ascii.json b/src/cmd/internal/test2json/testdata/ascii.json index 94695a10c5541e..3f3cf9e081bc74 100644 --- a/src/cmd/internal/test2json/testdata/ascii.json +++ b/src/cmd/internal/test2json/testdata/ascii.json @@ -1,11 +1,11 @@ {"Action":"start"} {"Action":"run","Test":"TestAscii"} -{"Action":"output","Test":"TestAscii","Output":"=== RUN TestAscii\n"} +{"Action":"output","Test":"TestAscii","Output":"=== RUN TestAscii\n","OutputType":"frame"} {"Action":"output","Test":"TestAscii","Output":"I can eat glass, and it doesn't hurt me. I can eat glass, and it doesn't hurt me.\n"} {"Action":"output","Test":"TestAscii","Output":"I CAN EAT GLASS, AND IT DOESN'T HURT ME. I CAN EAT GLASS, AND IT DOESN'T HURT ME.\n"} -{"Action":"output","Test":"TestAscii","Output":"--- PASS: TestAscii\n"} +{"Action":"output","Test":"TestAscii","Output":"--- PASS: TestAscii\n","OutputType":"frame"} {"Action":"output","Test":"TestAscii","Output":" i can eat glass, and it doesn't hurt me. i can eat glass, and it doesn't hurt me.\n"} {"Action":"output","Test":"TestAscii","Output":" V PNA RNG TYNFF, NAQ VG QBRFA'G UHEG ZR. V PNA RNG TYNFF, NAQ VG QBRFA'G UHEG ZR.\n"} {"Action":"pass","Test":"TestAscii"} -{"Action":"output","Output":"PASS\n"} +{"Action":"output","Output":"PASS\n","OutputType":"frame"} {"Action":"pass"} diff --git a/src/cmd/internal/test2json/testdata/bench.json b/src/cmd/internal/test2json/testdata/bench.json index 102e189ed7ad3c..8981e42eb47f5b 100644 --- a/src/cmd/internal/test2json/testdata/bench.json +++ b/src/cmd/internal/test2json/testdata/bench.json @@ -2,7 +2,7 @@ {"Action":"output","Output":"goos: darwin\n"} {"Action":"output","Output":"goarch: 386\n"} {"Action":"output","Output":"BenchmarkFoo-8 \t2000000000\t 0.00 ns/op\n"} -{"Action":"output","Test":"BenchmarkFoo-8","Output":"--- BENCH: BenchmarkFoo-8\n"} +{"Action":"output","Test":"BenchmarkFoo-8","Output":"--- BENCH: BenchmarkFoo-8\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkFoo-8","Output":"\tx_test.go:8: My benchmark\n"} {"Action":"output","Test":"BenchmarkFoo-8","Output":"\tx_test.go:8: My benchmark\n"} {"Action":"output","Test":"BenchmarkFoo-8","Output":"\tx_test.go:8: My benchmark\n"} @@ -10,6 +10,6 @@ {"Action":"output","Test":"BenchmarkFoo-8","Output":"\tx_test.go:8: My benchmark\n"} {"Action":"output","Test":"BenchmarkFoo-8","Output":"\tx_test.go:8: My benchmark\n"} {"Action":"bench","Test":"BenchmarkFoo-8"} -{"Action":"output","Output":"PASS\n"} +{"Action":"output","Output":"PASS\n","OutputType":"frame"} {"Action":"output","Output":"ok \tcommand-line-arguments\t0.009s\n"} {"Action":"pass"} diff --git a/src/cmd/internal/test2json/testdata/benchfail.json b/src/cmd/internal/test2json/testdata/benchfail.json index d2d968191c4ffc..de5d8098e7e0a5 100644 --- a/src/cmd/internal/test2json/testdata/benchfail.json +++ b/src/cmd/internal/test2json/testdata/benchfail.json @@ -1,7 +1,7 @@ {"Action":"start"} -{"Action":"output","Test":"BenchmarkFoo","Output":"--- FAIL: BenchmarkFoo\n"} +{"Action":"output","Test":"BenchmarkFoo","Output":"--- FAIL: BenchmarkFoo\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkFoo","Output":"\tx_test.go:8: My benchmark\n"} {"Action":"fail","Test":"BenchmarkFoo"} -{"Action":"output","Output":"FAIL\n"} -{"Action":"output","Output":"FAIL\tcommand-line-arguments\t0.008s\n"} +{"Action":"output","Output":"FAIL\n","OutputType":"frame"} +{"Action":"output","Output":"FAIL\tcommand-line-arguments\t0.008s\n","OutputType":"frame"} {"Action":"fail"} diff --git a/src/cmd/internal/test2json/testdata/frame.json b/src/cmd/internal/test2json/testdata/frame.json index 9dd29ae97758b4..fb87f5e44cf54b 100644 --- a/src/cmd/internal/test2json/testdata/frame.json +++ b/src/cmd/internal/test2json/testdata/frame.json @@ -1,10 +1,10 @@ {"Action":"start"} {"Action":"run","Test":"TestAscii"} -{"Action":"output","Test":"TestAscii","Output":"=== RUN TestAscii\n"} +{"Action":"output","Test":"TestAscii","Output":"=== RUN TestAscii\n","OutputType":"frame"} {"Action":"output","Test":"TestAscii","Output":"=== RUN TestNotReally\n"} -{"Action":"output","Test":"TestAscii","Output":"--- PASS: TestAscii\n"} +{"Action":"output","Test":"TestAscii","Output":"--- PASS: TestAscii\n","OutputType":"frame"} {"Action":"output","Test":"TestAscii","Output":" i can eat glass, and it doesn't hurt me. i can eat glass, and it doesn't hurt me.\n"} {"Action":"output","Test":"TestAscii","Output":"FAIL\n"} {"Action":"pass","Test":"TestAscii"} -{"Action":"output","Output":"PASS\n"} +{"Action":"output","Output":"PASS\n","OutputType":"frame"} {"Action":"pass"} diff --git a/src/cmd/internal/test2json/testdata/framebig.json b/src/cmd/internal/test2json/testdata/framebig.json index 54a8a524fe4708..d2b2b56fb36c6e 100644 --- a/src/cmd/internal/test2json/testdata/framebig.json +++ b/src/cmd/internal/test2json/testdata/framebig.json @@ -1,168 +1,168 @@ {"Action":"start"} {"Action":"run","Test":"TestIndex"} -{"Action":"output","Test":"TestIndex","Output":"=== RUN TestIndex\n"} -{"Action":"output","Test":"TestIndex","Output":"--- PASS: TestIndex (0.00s)\n"} +{"Action":"output","Test":"TestIndex","Output":"=== RUN TestIndex\n","OutputType":"frame"} +{"Action":"output","Test":"TestIndex","Output":"--- PASS: TestIndex (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestIndex"} {"Action":"pass","Test":"TestIndex"} -{"Action":"output","Test":"TestIndex","Output":"=== PASS TestIndex\n"} +{"Action":"output","Test":"TestIndex","Output":"=== PASS TestIndex\n","OutputType":"frame"} {"Action":"run","Test":"TestLastIndex"} -{"Action":"output","Test":"TestLastIndex","Output":"=== RUN TestLastIndex\n"} -{"Action":"output","Test":"TestLastIndex","Output":"--- PASS: TestLastIndex (0.00s)\n"} +{"Action":"output","Test":"TestLastIndex","Output":"=== RUN TestLastIndex\n","OutputType":"frame"} +{"Action":"output","Test":"TestLastIndex","Output":"--- PASS: TestLastIndex (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestLastIndex"} {"Action":"pass","Test":"TestLastIndex"} -{"Action":"output","Test":"TestLastIndex","Output":"=== PASS TestLastIndex\n"} +{"Action":"output","Test":"TestLastIndex","Output":"=== PASS TestLastIndex\n","OutputType":"frame"} {"Action":"run","Test":"TestIndexAny"} -{"Action":"output","Test":"TestIndexAny","Output":"=== RUN TestIndexAny\n"} -{"Action":"output","Test":"TestIndexAny","Output":"--- PASS: TestIndexAny (0.00s)\n"} +{"Action":"output","Test":"TestIndexAny","Output":"=== RUN TestIndexAny\n","OutputType":"frame"} +{"Action":"output","Test":"TestIndexAny","Output":"--- PASS: TestIndexAny (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestIndexAny"} {"Action":"pass","Test":"TestIndexAny"} -{"Action":"output","Test":"TestIndexAny","Output":"=== PASS TestIndexAny\n"} +{"Action":"output","Test":"TestIndexAny","Output":"=== PASS TestIndexAny\n","OutputType":"frame"} {"Action":"run","Test":"TestLastIndexAny"} -{"Action":"output","Test":"TestLastIndexAny","Output":"=== RUN TestLastIndexAny\n"} -{"Action":"output","Test":"TestLastIndexAny","Output":"--- PASS: TestLastIndexAny (0.00s)\n"} +{"Action":"output","Test":"TestLastIndexAny","Output":"=== RUN TestLastIndexAny\n","OutputType":"frame"} +{"Action":"output","Test":"TestLastIndexAny","Output":"--- PASS: TestLastIndexAny (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestLastIndexAny"} {"Action":"pass","Test":"TestLastIndexAny"} -{"Action":"output","Test":"TestLastIndexAny","Output":"=== PASS TestLastIndexAny\n"} +{"Action":"output","Test":"TestLastIndexAny","Output":"=== PASS TestLastIndexAny\n","OutputType":"frame"} {"Action":"run","Test":"TestIndexByte"} -{"Action":"output","Test":"TestIndexByte","Output":"=== RUN TestIndexByte\n"} -{"Action":"output","Test":"TestIndexByte","Output":"--- PASS: TestIndexByte (0.00s)\n"} +{"Action":"output","Test":"TestIndexByte","Output":"=== RUN TestIndexByte\n","OutputType":"frame"} +{"Action":"output","Test":"TestIndexByte","Output":"--- PASS: TestIndexByte (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestIndexByte"} {"Action":"pass","Test":"TestIndexByte"} -{"Action":"output","Test":"TestIndexByte","Output":"=== PASS TestIndexByte\n"} +{"Action":"output","Test":"TestIndexByte","Output":"=== PASS TestIndexByte\n","OutputType":"frame"} {"Action":"run","Test":"TestLastIndexByte"} -{"Action":"output","Test":"TestLastIndexByte","Output":"=== RUN TestLastIndexByte\n"} -{"Action":"output","Test":"TestLastIndexByte","Output":"--- PASS: TestLastIndexByte (0.00s)\n"} +{"Action":"output","Test":"TestLastIndexByte","Output":"=== RUN TestLastIndexByte\n","OutputType":"frame"} +{"Action":"output","Test":"TestLastIndexByte","Output":"--- PASS: TestLastIndexByte (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestLastIndexByte"} {"Action":"pass","Test":"TestLastIndexByte"} -{"Action":"output","Test":"TestLastIndexByte","Output":"=== PASS TestLastIndexByte\n"} +{"Action":"output","Test":"TestLastIndexByte","Output":"=== PASS TestLastIndexByte\n","OutputType":"frame"} {"Action":"run","Test":"TestIndexRandom"} -{"Action":"output","Test":"TestIndexRandom","Output":"=== RUN TestIndexRandom\n"} -{"Action":"output","Test":"TestIndexRandom","Output":"--- PASS: TestIndexRandom (0.00s)\n"} +{"Action":"output","Test":"TestIndexRandom","Output":"=== RUN TestIndexRandom\n","OutputType":"frame"} +{"Action":"output","Test":"TestIndexRandom","Output":"--- PASS: TestIndexRandom (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestIndexRandom"} {"Action":"pass","Test":"TestIndexRandom"} -{"Action":"output","Test":"TestIndexRandom","Output":"=== PASS TestIndexRandom\n"} +{"Action":"output","Test":"TestIndexRandom","Output":"=== PASS TestIndexRandom\n","OutputType":"frame"} {"Action":"run","Test":"TestIndexRune"} -{"Action":"output","Test":"TestIndexRune","Output":"=== RUN TestIndexRune\n"} -{"Action":"output","Test":"TestIndexRune","Output":"--- PASS: TestIndexRune (0.00s)\n"} +{"Action":"output","Test":"TestIndexRune","Output":"=== RUN TestIndexRune\n","OutputType":"frame"} +{"Action":"output","Test":"TestIndexRune","Output":"--- PASS: TestIndexRune (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestIndexRune"} {"Action":"pass","Test":"TestIndexRune"} -{"Action":"output","Test":"TestIndexRune","Output":"=== PASS TestIndexRune\n"} +{"Action":"output","Test":"TestIndexRune","Output":"=== PASS TestIndexRune\n","OutputType":"frame"} {"Action":"run","Test":"TestIndexFunc"} -{"Action":"output","Test":"TestIndexFunc","Output":"=== RUN TestIndexFunc\n"} -{"Action":"output","Test":"TestIndexFunc","Output":"--- PASS: TestIndexFunc (0.00s)\n"} +{"Action":"output","Test":"TestIndexFunc","Output":"=== RUN TestIndexFunc\n","OutputType":"frame"} +{"Action":"output","Test":"TestIndexFunc","Output":"--- PASS: TestIndexFunc (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestIndexFunc"} {"Action":"pass","Test":"TestIndexFunc"} -{"Action":"output","Test":"TestIndexFunc","Output":"=== PASS TestIndexFunc\n"} +{"Action":"output","Test":"TestIndexFunc","Output":"=== PASS TestIndexFunc\n","OutputType":"frame"} {"Action":"run","Test":"ExampleIndex"} -{"Action":"output","Test":"ExampleIndex","Output":"=== RUN ExampleIndex\n"} -{"Action":"output","Test":"ExampleIndex","Output":"--- PASS: ExampleIndex (0.00s)\n"} +{"Action":"output","Test":"ExampleIndex","Output":"=== RUN ExampleIndex\n","OutputType":"frame"} +{"Action":"output","Test":"ExampleIndex","Output":"--- PASS: ExampleIndex (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"ExampleIndex"} {"Action":"run","Test":"ExampleIndexFunc"} -{"Action":"output","Test":"ExampleIndexFunc","Output":"=== RUN ExampleIndexFunc\n"} -{"Action":"output","Test":"ExampleIndexFunc","Output":"--- PASS: ExampleIndexFunc (0.00s)\n"} +{"Action":"output","Test":"ExampleIndexFunc","Output":"=== RUN ExampleIndexFunc\n","OutputType":"frame"} +{"Action":"output","Test":"ExampleIndexFunc","Output":"--- PASS: ExampleIndexFunc (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"ExampleIndexFunc"} {"Action":"run","Test":"ExampleIndexAny"} -{"Action":"output","Test":"ExampleIndexAny","Output":"=== RUN ExampleIndexAny\n"} -{"Action":"output","Test":"ExampleIndexAny","Output":"--- PASS: ExampleIndexAny (0.00s)\n"} +{"Action":"output","Test":"ExampleIndexAny","Output":"=== RUN ExampleIndexAny\n","OutputType":"frame"} +{"Action":"output","Test":"ExampleIndexAny","Output":"--- PASS: ExampleIndexAny (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"ExampleIndexAny"} {"Action":"run","Test":"ExampleIndexByte"} -{"Action":"output","Test":"ExampleIndexByte","Output":"=== RUN ExampleIndexByte\n"} -{"Action":"output","Test":"ExampleIndexByte","Output":"--- PASS: ExampleIndexByte (0.00s)\n"} +{"Action":"output","Test":"ExampleIndexByte","Output":"=== RUN ExampleIndexByte\n","OutputType":"frame"} +{"Action":"output","Test":"ExampleIndexByte","Output":"--- PASS: ExampleIndexByte (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"ExampleIndexByte"} {"Action":"run","Test":"ExampleIndexRune"} -{"Action":"output","Test":"ExampleIndexRune","Output":"=== RUN ExampleIndexRune\n"} -{"Action":"output","Test":"ExampleIndexRune","Output":"--- PASS: ExampleIndexRune (0.00s)\n"} +{"Action":"output","Test":"ExampleIndexRune","Output":"=== RUN ExampleIndexRune\n","OutputType":"frame"} +{"Action":"output","Test":"ExampleIndexRune","Output":"--- PASS: ExampleIndexRune (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"ExampleIndexRune"} {"Action":"run","Test":"ExampleLastIndex"} -{"Action":"output","Test":"ExampleLastIndex","Output":"=== RUN ExampleLastIndex\n"} -{"Action":"output","Test":"ExampleLastIndex","Output":"--- PASS: ExampleLastIndex (0.00s)\n"} +{"Action":"output","Test":"ExampleLastIndex","Output":"=== RUN ExampleLastIndex\n","OutputType":"frame"} +{"Action":"output","Test":"ExampleLastIndex","Output":"--- PASS: ExampleLastIndex (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"ExampleLastIndex"} {"Action":"run","Test":"ExampleLastIndexAny"} -{"Action":"output","Test":"ExampleLastIndexAny","Output":"=== RUN ExampleLastIndexAny\n"} -{"Action":"output","Test":"ExampleLastIndexAny","Output":"--- PASS: ExampleLastIndexAny (0.00s)\n"} +{"Action":"output","Test":"ExampleLastIndexAny","Output":"=== RUN ExampleLastIndexAny\n","OutputType":"frame"} +{"Action":"output","Test":"ExampleLastIndexAny","Output":"--- PASS: ExampleLastIndexAny (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"ExampleLastIndexAny"} {"Action":"run","Test":"ExampleLastIndexByte"} -{"Action":"output","Test":"ExampleLastIndexByte","Output":"=== RUN ExampleLastIndexByte\n"} -{"Action":"output","Test":"ExampleLastIndexByte","Output":"--- PASS: ExampleLastIndexByte (0.00s)\n"} +{"Action":"output","Test":"ExampleLastIndexByte","Output":"=== RUN ExampleLastIndexByte\n","OutputType":"frame"} +{"Action":"output","Test":"ExampleLastIndexByte","Output":"--- PASS: ExampleLastIndexByte (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"ExampleLastIndexByte"} {"Action":"run","Test":"ExampleLastIndexFunc"} -{"Action":"output","Test":"ExampleLastIndexFunc","Output":"=== RUN ExampleLastIndexFunc\n"} -{"Action":"output","Test":"ExampleLastIndexFunc","Output":"--- PASS: ExampleLastIndexFunc (0.00s)\n"} +{"Action":"output","Test":"ExampleLastIndexFunc","Output":"=== RUN ExampleLastIndexFunc\n","OutputType":"frame"} +{"Action":"output","Test":"ExampleLastIndexFunc","Output":"--- PASS: ExampleLastIndexFunc (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"ExampleLastIndexFunc"} {"Action":"output","Output":"goos: darwin\n"} {"Action":"output","Output":"goarch: amd64\n"} {"Action":"output","Output":"pkg: strings\n"} {"Action":"output","Output":"cpu: Intel(R) Core(TM) i9-9980HK CPU @ 2.40GHz\n"} {"Action":"run","Test":"BenchmarkIndexRune"} -{"Action":"output","Test":"BenchmarkIndexRune","Output":"=== RUN BenchmarkIndexRune\n"} +{"Action":"output","Test":"BenchmarkIndexRune","Output":"=== RUN BenchmarkIndexRune\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexRune","Output":"BenchmarkIndexRune\n"} {"Action":"output","Test":"BenchmarkIndexRune","Output":"BenchmarkIndexRune-16 \t87335496\t 14.27 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexRuneLongString"} -{"Action":"output","Test":"BenchmarkIndexRuneLongString","Output":"=== RUN BenchmarkIndexRuneLongString\n"} +{"Action":"output","Test":"BenchmarkIndexRuneLongString","Output":"=== RUN BenchmarkIndexRuneLongString\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexRuneLongString","Output":"BenchmarkIndexRuneLongString\n"} {"Action":"output","Test":"BenchmarkIndexRuneLongString","Output":"BenchmarkIndexRuneLongString-16 \t57104472\t 18.66 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexRuneFastPath"} -{"Action":"output","Test":"BenchmarkIndexRuneFastPath","Output":"=== RUN BenchmarkIndexRuneFastPath\n"} +{"Action":"output","Test":"BenchmarkIndexRuneFastPath","Output":"=== RUN BenchmarkIndexRuneFastPath\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexRuneFastPath","Output":"BenchmarkIndexRuneFastPath\n"} {"Action":"output","Test":"BenchmarkIndexRuneFastPath","Output":"BenchmarkIndexRuneFastPath-16 \t262380160\t 4.499 ns/op\n"} {"Action":"run","Test":"BenchmarkIndex"} -{"Action":"output","Test":"BenchmarkIndex","Output":"=== RUN BenchmarkIndex\n"} +{"Action":"output","Test":"BenchmarkIndex","Output":"=== RUN BenchmarkIndex\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndex","Output":"BenchmarkIndex\n"} {"Action":"output","Test":"BenchmarkIndex","Output":"BenchmarkIndex-16 \t248529364\t 4.697 ns/op\n"} {"Action":"run","Test":"BenchmarkLastIndex"} -{"Action":"output","Test":"BenchmarkLastIndex","Output":"=== RUN BenchmarkLastIndex\n"} +{"Action":"output","Test":"BenchmarkLastIndex","Output":"=== RUN BenchmarkLastIndex\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkLastIndex","Output":"BenchmarkLastIndex\n"} {"Action":"output","Test":"BenchmarkLastIndex","Output":"BenchmarkLastIndex-16 \t293688756\t 4.166 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexByte"} -{"Action":"output","Test":"BenchmarkIndexByte","Output":"=== RUN BenchmarkIndexByte\n"} +{"Action":"output","Test":"BenchmarkIndexByte","Output":"=== RUN BenchmarkIndexByte\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexByte","Output":"BenchmarkIndexByte\n"} {"Action":"output","Test":"BenchmarkIndexByte","Output":"BenchmarkIndexByte-16 \t310338391\t 3.608 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexHard1"} -{"Action":"output","Test":"BenchmarkIndexHard1","Output":"=== RUN BenchmarkIndexHard1\n"} +{"Action":"output","Test":"BenchmarkIndexHard1","Output":"=== RUN BenchmarkIndexHard1\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexHard1","Output":"BenchmarkIndexHard1\n"} {"Action":"output","Test":"BenchmarkIndexHard1","Output":"BenchmarkIndexHard1-16 \t 12852\t 92380 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexHard2"} -{"Action":"output","Test":"BenchmarkIndexHard2","Output":"=== RUN BenchmarkIndexHard2\n"} +{"Action":"output","Test":"BenchmarkIndexHard2","Output":"=== RUN BenchmarkIndexHard2\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexHard2","Output":"BenchmarkIndexHard2\n"} {"Action":"output","Test":"BenchmarkIndexHard2","Output":"BenchmarkIndexHard2-16 \t 8977\t 135080 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexHard3"} -{"Action":"output","Test":"BenchmarkIndexHard3","Output":"=== RUN BenchmarkIndexHard3\n"} +{"Action":"output","Test":"BenchmarkIndexHard3","Output":"=== RUN BenchmarkIndexHard3\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexHard3","Output":"BenchmarkIndexHard3\n"} {"Action":"output","Test":"BenchmarkIndexHard3","Output":"BenchmarkIndexHard3-16 \t 1885\t 532079 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexHard4"} -{"Action":"output","Test":"BenchmarkIndexHard4","Output":"=== RUN BenchmarkIndexHard4\n"} +{"Action":"output","Test":"BenchmarkIndexHard4","Output":"=== RUN BenchmarkIndexHard4\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexHard4","Output":"BenchmarkIndexHard4\n"} {"Action":"output","Test":"BenchmarkIndexHard4","Output":"BenchmarkIndexHard4-16 \t 2298\t 533435 ns/op\n"} {"Action":"run","Test":"BenchmarkLastIndexHard1"} -{"Action":"output","Test":"BenchmarkLastIndexHard1","Output":"=== RUN BenchmarkLastIndexHard1\n"} +{"Action":"output","Test":"BenchmarkLastIndexHard1","Output":"=== RUN BenchmarkLastIndexHard1\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkLastIndexHard1","Output":"BenchmarkLastIndexHard1\n"} {"Action":"output","Test":"BenchmarkLastIndexHard1","Output":"BenchmarkLastIndexHard1-16 \t 813\t 1295767 ns/op\n"} {"Action":"run","Test":"BenchmarkLastIndexHard2"} -{"Action":"output","Test":"BenchmarkLastIndexHard2","Output":"=== RUN BenchmarkLastIndexHard2\n"} +{"Action":"output","Test":"BenchmarkLastIndexHard2","Output":"=== RUN BenchmarkLastIndexHard2\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkLastIndexHard2","Output":"BenchmarkLastIndexHard2\n"} {"Action":"output","Test":"BenchmarkLastIndexHard2","Output":"BenchmarkLastIndexHard2-16 \t 784\t 1389403 ns/op\n"} {"Action":"run","Test":"BenchmarkLastIndexHard3"} -{"Action":"output","Test":"BenchmarkLastIndexHard3","Output":"=== RUN BenchmarkLastIndexHard3\n"} +{"Action":"output","Test":"BenchmarkLastIndexHard3","Output":"=== RUN BenchmarkLastIndexHard3\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkLastIndexHard3","Output":"BenchmarkLastIndexHard3\n"} {"Action":"output","Test":"BenchmarkLastIndexHard3","Output":"BenchmarkLastIndexHard3-16 \t 913\t 1316608 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexTorture"} -{"Action":"output","Test":"BenchmarkIndexTorture","Output":"=== RUN BenchmarkIndexTorture\n"} +{"Action":"output","Test":"BenchmarkIndexTorture","Output":"=== RUN BenchmarkIndexTorture\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexTorture","Output":"BenchmarkIndexTorture\n"} {"Action":"output","Test":"BenchmarkIndexTorture","Output":"BenchmarkIndexTorture-16 \t 98090\t 10201 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexAnyASCII"} -{"Action":"output","Test":"BenchmarkIndexAnyASCII","Output":"=== RUN BenchmarkIndexAnyASCII\n"} +{"Action":"output","Test":"BenchmarkIndexAnyASCII","Output":"=== RUN BenchmarkIndexAnyASCII\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexAnyASCII","Output":"BenchmarkIndexAnyASCII\n"} {"Action":"run","Test":"BenchmarkIndexAnyASCII/1:1"} -{"Action":"output","Test":"BenchmarkIndexAnyASCII/1:1","Output":"=== RUN BenchmarkIndexAnyASCII/1:1\n"} +{"Action":"output","Test":"BenchmarkIndexAnyASCII/1:1","Output":"=== RUN BenchmarkIndexAnyASCII/1:1\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexAnyASCII/1:1","Output":"BenchmarkIndexAnyASCII/1:1\n"} {"Action":"output","Test":"BenchmarkIndexAnyASCII/1:1","Output":"BenchmarkIndexAnyASCII/1:1-16 \t214829462\t 5.592 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexAnyASCII/1:2"} -{"Action":"output","Test":"BenchmarkIndexAnyASCII/1:2","Output":"=== RUN BenchmarkIndexAnyASCII/1:2\n"} +{"Action":"output","Test":"BenchmarkIndexAnyASCII/1:2","Output":"=== RUN BenchmarkIndexAnyASCII/1:2\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexAnyASCII/1:2","Output":"BenchmarkIndexAnyASCII/1:2\n"} {"Action":"output","Test":"BenchmarkIndexAnyASCII/1:2","Output":"BenchmarkIndexAnyASCII/1:2-16 \t155499682\t 7.214 ns/op\n"} {"Action":"run","Test":"BenchmarkIndexAnyASCII/1:4"} -{"Action":"output","Test":"BenchmarkIndexAnyASCII/1:4","Output":"=== RUN BenchmarkIndexAnyASCII/1:4\n"} +{"Action":"output","Test":"BenchmarkIndexAnyASCII/1:4","Output":"=== RUN BenchmarkIndexAnyASCII/1:4\n","OutputType":"frame"} {"Action":"output","Test":"BenchmarkIndexAnyASCII/1:4","Output":"BenchmarkIndexAnyASCII/1:4\n"} {"Action":"output","Test":"BenchmarkIndexAnyASCII/1:4","Output":"BenchmarkIndexAnyASCII/1:4-16 \t172757770\t 7.092 ns/op\n"} -{"Action":"output","Output":"PASS\n"} +{"Action":"output","Output":"PASS\n","OutputType":"frame"} {"Action":"pass"} diff --git a/src/cmd/internal/test2json/testdata/frameescape.json b/src/cmd/internal/test2json/testdata/frameescape.json new file mode 100644 index 00000000000000..99df01ad042a7b --- /dev/null +++ b/src/cmd/internal/test2json/testdata/frameescape.json @@ -0,0 +1,270 @@ +{"Action":"start"} +{"Action":"run","Test":"TestAscii"} +{"Action":"output","Test":"TestAscii","Output":"=== RUN TestAscii\n","OutputType":"frame"} +{"Action":"run","Test":"TestAscii/Log"} +{"Action":"output","Test":"TestAscii/Log","Output":"=== RUN TestAscii/Log\n","OutputType":"frame"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0000\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0001\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0002\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0003\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0004\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0005\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0006\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0007\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \b\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \t\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \n"} +{"Action":"output","Test":"TestAscii/Log","Output":" \n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u000b\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \f\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \r\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u000e\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u000f\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0010\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0011\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0012\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0013\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0014\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0015\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0016\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0017\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0018\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0019\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u001a\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u001b\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u001c\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u001d\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u001e\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u001f\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: !\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \"\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: #\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: $\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: %\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u0026\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: '\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: (\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: )\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: *\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: +\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: ,\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: -\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: .\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: /\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: 0\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: 1\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: 2\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: 3\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: 4\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: 5\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: 6\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: 7\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: 8\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: 9\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: :\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: ;\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u003c\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: =\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \u003e\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: ?\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: @\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: A\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: B\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: C\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: D\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: E\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: F\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: G\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: H\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: I\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: J\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: K\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: L\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: M\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: N\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: O\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: P\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: Q\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: R\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: S\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: T\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: U\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: V\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: W\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: X\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: Y\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: Z\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: [\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \\\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: ]\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: ^\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: _\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: `\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: a\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: b\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: c\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: d\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: e\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: f\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: g\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: h\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: i\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: j\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: k\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: l\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: m\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: n\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: o\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: p\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: q\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: r\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: s\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: t\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: u\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: v\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: w\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: x\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: y\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: z\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: {\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: |\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: }\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: ~\n"} +{"Action":"output","Test":"TestAscii/Log","Output":" x_test.go:8: \n"} +{"Action":"output","Test":"TestAscii/Log","Output":"--- PASS: TestAscii/Log (0.00s)\n","OutputType":"frame"} +{"Action":"pass","Test":"TestAscii/Log"} +{"Action":"run","Test":"TestAscii/Error"} +{"Action":"output","Test":"TestAscii/Error","Output":"=== RUN TestAscii/Error\n","OutputType":"frame"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0000\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0001\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0002\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0003\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0004\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0005\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0006\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0007\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \b\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \t\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" \n","OutputType":"error-continue"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u000b\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \f\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \r\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u000e\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u000f\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0010\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0011\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0012\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0013\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0014\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0015\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0016\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0017\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0018\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0019\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u001a\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u001b\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u001c\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u001d\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u001e\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u001f\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: !\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \"\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: #\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: $\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: %\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u0026\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: '\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: (\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: )\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: *\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: +\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: ,\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: -\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: .\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: /\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: 0\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: 1\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: 2\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: 3\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: 4\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: 5\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: 6\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: 7\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: 8\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: 9\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: :\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: ;\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u003c\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: =\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \u003e\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: ?\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: @\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: A\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: B\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: C\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: D\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: E\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: F\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: G\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: H\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: I\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: J\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: K\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: L\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: M\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: N\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: O\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: P\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: Q\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: R\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: S\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: T\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: U\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: V\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: W\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: X\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: Y\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: Z\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: [\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \\\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: ]\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: ^\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: _\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: `\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: a\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: b\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: c\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: d\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: e\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: f\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: g\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: h\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: i\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: j\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: k\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: l\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: m\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: n\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: o\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: p\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: q\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: r\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: s\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: t\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: u\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: v\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: w\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: x\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: y\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: z\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: {\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: |\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: }\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: ~\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":" x_test.go:13: \n","OutputType":"error"} +{"Action":"output","Test":"TestAscii/Error","Output":"--- FAIL: TestAscii/Error (0.00s)\n","OutputType":"frame"} +{"Action":"fail","Test":"TestAscii/Error"} +{"Action":"output","Test":"TestAscii","Output":"--- FAIL: TestAscii (0.00s)\n","OutputType":"frame"} diff --git a/src/cmd/internal/test2json/testdata/frameescape.src b/src/cmd/internal/test2json/testdata/frameescape.src new file mode 100644 index 00000000000000..4bad6dac774005 --- /dev/null +++ b/src/cmd/internal/test2json/testdata/frameescape.src @@ -0,0 +1,24 @@ +! go test -v=test2json + +stdout '=== RUN TestAscii' + +-- go.mod -- +module p + +-- x_test.go -- +package p + +import "testing" + +func TestAscii(t *testing.T) { + t.Run("Log", func(t *testing.T) { + for i := rune(0); i < 0x80; i++ { + t.Log(string(i)) + } + }) + t.Run("Error", func(t *testing.T) { + for i := rune(0); i < 0x80; i++ { + t.Error(string(i)) + } + }) +} diff --git a/src/cmd/internal/test2json/testdata/frameescape.test b/src/cmd/internal/test2json/testdata/frameescape.test new file mode 100644 index 00000000000000..e2abe668309379 Binary files /dev/null and b/src/cmd/internal/test2json/testdata/frameescape.test differ diff --git a/src/cmd/internal/test2json/testdata/framefail.json b/src/cmd/internal/test2json/testdata/framefail.json new file mode 100644 index 00000000000000..e355d703038902 --- /dev/null +++ b/src/cmd/internal/test2json/testdata/framefail.json @@ -0,0 +1,11 @@ +{"Action":"start"} +{"Action":"run","Test":"TestAscii"} +{"Action":"output","Test":"TestAscii","Output":"=== RUN TestAscii\n","OutputType":"frame"} +{"Action":"output","Test":"TestAscii","Output":"foo\n"} +{"Action":"output","Test":"TestAscii","Output":" one line\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii","Output":"bar\n"} +{"Action":"output","Test":"TestAscii","Output":" two\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii","Output":" lines\n","OutputType":"error-continue"} +{"Action":"output","Test":"TestAscii","Output":"baz"} +{"Action":"output","Test":"TestAscii","Output":" same line\n","OutputType":"error"} +{"Action":"output","Test":"TestAscii","Output":"--- FAIL: TestAscii\n","OutputType":"frame"} diff --git a/src/cmd/internal/test2json/testdata/framefail.test b/src/cmd/internal/test2json/testdata/framefail.test new file mode 100644 index 00000000000000..35666076df92af --- /dev/null +++ b/src/cmd/internal/test2json/testdata/framefail.test @@ -0,0 +1,8 @@ +=== RUN TestAscii +foo + one line +bar + two + lines +baz same line +--- FAIL: TestAscii diff --git a/src/cmd/internal/test2json/testdata/framefuzz.json b/src/cmd/internal/test2json/testdata/framefuzz.json index 25869ee7408d5b..c8647dad3a7fb5 100644 --- a/src/cmd/internal/test2json/testdata/framefuzz.json +++ b/src/cmd/internal/test2json/testdata/framefuzz.json @@ -1,43 +1,43 @@ {"Action":"start"} {"Action":"run","Test":"TestAddrStringAllocs"} -{"Action":"output","Test":"TestAddrStringAllocs","Output":"=== RUN TestAddrStringAllocs\n"} +{"Action":"output","Test":"TestAddrStringAllocs","Output":"=== RUN TestAddrStringAllocs\n","OutputType":"frame"} {"Action":"run","Test":"TestAddrStringAllocs/zero"} -{"Action":"output","Test":"TestAddrStringAllocs/zero","Output":"=== RUN TestAddrStringAllocs/zero\n"} +{"Action":"output","Test":"TestAddrStringAllocs/zero","Output":"=== RUN TestAddrStringAllocs/zero\n","OutputType":"frame"} {"Action":"run","Test":"TestAddrStringAllocs/ipv4"} -{"Action":"output","Test":"TestAddrStringAllocs/ipv4","Output":"=== RUN TestAddrStringAllocs/ipv4\n"} +{"Action":"output","Test":"TestAddrStringAllocs/ipv4","Output":"=== RUN TestAddrStringAllocs/ipv4\n","OutputType":"frame"} {"Action":"run","Test":"TestAddrStringAllocs/ipv6"} -{"Action":"output","Test":"TestAddrStringAllocs/ipv6","Output":"=== RUN TestAddrStringAllocs/ipv6\n"} +{"Action":"output","Test":"TestAddrStringAllocs/ipv6","Output":"=== RUN TestAddrStringAllocs/ipv6\n","OutputType":"frame"} {"Action":"run","Test":"TestAddrStringAllocs/ipv6+zone"} -{"Action":"output","Test":"TestAddrStringAllocs/ipv6+zone","Output":"=== RUN TestAddrStringAllocs/ipv6+zone\n"} +{"Action":"output","Test":"TestAddrStringAllocs/ipv6+zone","Output":"=== RUN TestAddrStringAllocs/ipv6+zone\n","OutputType":"frame"} {"Action":"run","Test":"TestAddrStringAllocs/ipv4-in-ipv6"} -{"Action":"output","Test":"TestAddrStringAllocs/ipv4-in-ipv6","Output":"=== RUN TestAddrStringAllocs/ipv4-in-ipv6\n"} +{"Action":"output","Test":"TestAddrStringAllocs/ipv4-in-ipv6","Output":"=== RUN TestAddrStringAllocs/ipv4-in-ipv6\n","OutputType":"frame"} {"Action":"run","Test":"TestAddrStringAllocs/ipv4-in-ipv6+zone"} -{"Action":"output","Test":"TestAddrStringAllocs/ipv4-in-ipv6+zone","Output":"=== RUN TestAddrStringAllocs/ipv4-in-ipv6+zone\n"} -{"Action":"output","Test":"TestAddrStringAllocs","Output":"--- PASS: TestAddrStringAllocs (0.00s)\n"} -{"Action":"output","Test":"TestAddrStringAllocs/zero","Output":" --- PASS: TestAddrStringAllocs/zero (0.00s)\n"} +{"Action":"output","Test":"TestAddrStringAllocs/ipv4-in-ipv6+zone","Output":"=== RUN TestAddrStringAllocs/ipv4-in-ipv6+zone\n","OutputType":"frame"} +{"Action":"output","Test":"TestAddrStringAllocs","Output":"--- PASS: TestAddrStringAllocs (0.00s)\n","OutputType":"frame"} +{"Action":"output","Test":"TestAddrStringAllocs/zero","Output":" --- PASS: TestAddrStringAllocs/zero (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestAddrStringAllocs/zero"} -{"Action":"output","Test":"TestAddrStringAllocs/ipv4","Output":" --- PASS: TestAddrStringAllocs/ipv4 (0.00s)\n"} +{"Action":"output","Test":"TestAddrStringAllocs/ipv4","Output":" --- PASS: TestAddrStringAllocs/ipv4 (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestAddrStringAllocs/ipv4"} -{"Action":"output","Test":"TestAddrStringAllocs/ipv6","Output":" --- PASS: TestAddrStringAllocs/ipv6 (0.00s)\n"} +{"Action":"output","Test":"TestAddrStringAllocs/ipv6","Output":" --- PASS: TestAddrStringAllocs/ipv6 (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestAddrStringAllocs/ipv6"} -{"Action":"output","Test":"TestAddrStringAllocs/ipv6+zone","Output":" --- PASS: TestAddrStringAllocs/ipv6+zone (0.00s)\n"} +{"Action":"output","Test":"TestAddrStringAllocs/ipv6+zone","Output":" --- PASS: TestAddrStringAllocs/ipv6+zone (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestAddrStringAllocs/ipv6+zone"} -{"Action":"output","Test":"TestAddrStringAllocs/ipv4-in-ipv6","Output":" --- PASS: TestAddrStringAllocs/ipv4-in-ipv6 (0.00s)\n"} +{"Action":"output","Test":"TestAddrStringAllocs/ipv4-in-ipv6","Output":" --- PASS: TestAddrStringAllocs/ipv4-in-ipv6 (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestAddrStringAllocs/ipv4-in-ipv6"} -{"Action":"output","Test":"TestAddrStringAllocs/ipv4-in-ipv6+zone","Output":" --- PASS: TestAddrStringAllocs/ipv4-in-ipv6+zone (0.00s)\n"} +{"Action":"output","Test":"TestAddrStringAllocs/ipv4-in-ipv6+zone","Output":" --- PASS: TestAddrStringAllocs/ipv4-in-ipv6+zone (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestAddrStringAllocs/ipv4-in-ipv6+zone"} {"Action":"pass","Test":"TestAddrStringAllocs"} {"Action":"run","Test":"TestPrefixString"} -{"Action":"output","Test":"TestPrefixString","Output":"=== RUN TestPrefixString\n"} -{"Action":"output","Test":"TestPrefixString","Output":"--- PASS: TestPrefixString (0.00s)\n"} +{"Action":"output","Test":"TestPrefixString","Output":"=== RUN TestPrefixString\n","OutputType":"frame"} +{"Action":"output","Test":"TestPrefixString","Output":"--- PASS: TestPrefixString (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestPrefixString"} {"Action":"run","Test":"TestInvalidAddrPortString"} -{"Action":"output","Test":"TestInvalidAddrPortString","Output":"=== RUN TestInvalidAddrPortString\n"} -{"Action":"output","Test":"TestInvalidAddrPortString","Output":"--- PASS: TestInvalidAddrPortString (0.00s)\n"} +{"Action":"output","Test":"TestInvalidAddrPortString","Output":"=== RUN TestInvalidAddrPortString\n","OutputType":"frame"} +{"Action":"output","Test":"TestInvalidAddrPortString","Output":"--- PASS: TestInvalidAddrPortString (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestInvalidAddrPortString"} {"Action":"run","Test":"TestAsSlice"} -{"Action":"output","Test":"TestAsSlice","Output":"=== RUN TestAsSlice\n"} -{"Action":"output","Test":"TestAsSlice","Output":"--- PASS: TestAsSlice (0.00s)\n"} +{"Action":"output","Test":"TestAsSlice","Output":"=== RUN TestAsSlice\n","OutputType":"frame"} +{"Action":"output","Test":"TestAsSlice","Output":"--- PASS: TestAsSlice (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestAsSlice"} {"Action":"output","Test":"TestInlining","Output":" inlining_test.go:102: not in expected set, but also inlinable: \"Addr.string4\"\n"} {"Action":"output","Test":"TestInlining","Output":" inlining_test.go:102: not in expected set, but also inlinable: \"Prefix.isZero\"\n"} @@ -55,15 +55,15 @@ {"Action":"output","Test":"TestInlining","Output":" inlining_test.go:102: not in expected set, but also inlinable: \"beUint64\"\n"} {"Action":"output","Test":"TestInlining","Output":" inlining_test.go:102: not in expected set, but also inlinable: \"appendHexPad\"\n"} {"Action":"output","Test":"TestInlining","Output":" inlining_test.go:102: not in expected set, but also inlinable: \"lePutUint16\"\n"} -{"Action":"output","Test":"TestInlining","Output":"--- PASS: TestInlining (0.10s)\n"} +{"Action":"output","Test":"TestInlining","Output":"--- PASS: TestInlining (0.10s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestInlining"} {"Action":"run","Test":"FuzzParse"} -{"Action":"output","Test":"FuzzParse","Output":"=== RUN FuzzParse\n"} +{"Action":"output","Test":"FuzzParse","Output":"=== RUN FuzzParse\n","OutputType":"frame"} {"Action":"output","Test":"FuzzParse","Output":"fuzz: elapsed: 0s, gathering baseline coverage: 0/390 completed\n"} {"Action":"output","Test":"FuzzParse","Output":"fuzz: elapsed: 0s, gathering baseline coverage: 390/390 completed, now fuzzing with 16 workers\n"} {"Action":"output","Test":"FuzzParse","Output":"fuzz: elapsed: 3s, execs: 438666 (146173/sec), new interesting: 12 (total: 402)\n"} {"Action":"output","Test":"FuzzParse","Output":"\u0003fuzz: elapsed: 4s, execs: 558467 (147850/sec), new interesting: 15 (total: 405)\n"} -{"Action":"output","Test":"FuzzParse","Output":"--- PASS: FuzzParse (3.85s)\n"} +{"Action":"output","Test":"FuzzParse","Output":"--- PASS: FuzzParse (3.85s)\n","OutputType":"frame"} {"Action":"pass","Test":"FuzzParse"} -{"Action":"output","Output":"PASS\n"} +{"Action":"output","Output":"PASS\n","OutputType":"frame"} {"Action":"pass"} diff --git a/src/cmd/internal/test2json/testdata/issue23036.json b/src/cmd/internal/test2json/testdata/issue23036.json index bfdc3e5e0f8fd4..40a8b67bc568ac 100644 --- a/src/cmd/internal/test2json/testdata/issue23036.json +++ b/src/cmd/internal/test2json/testdata/issue23036.json @@ -1,13 +1,13 @@ {"Action":"start"} {"Action":"run","Test":"TestActualCase"} -{"Action":"output","Test":"TestActualCase","Output":"=== RUN TestActualCase\n"} -{"Action":"output","Test":"TestActualCase","Output":"--- FAIL: TestActualCase (0.00s)\n"} +{"Action":"output","Test":"TestActualCase","Output":"=== RUN TestActualCase\n","OutputType":"frame"} +{"Action":"output","Test":"TestActualCase","Output":"--- FAIL: TestActualCase (0.00s)\n","OutputType":"frame"} {"Action":"output","Test":"TestActualCase","Output":" foo_test.go:14: Differed.\n"} {"Action":"output","Test":"TestActualCase","Output":" Expected: MyTest:\n"} {"Action":"output","Test":"TestActualCase","Output":" --- FAIL: Test output from other tool\n"} {"Action":"output","Test":"TestActualCase","Output":" Actual: not expected\n"} {"Action":"fail","Test":"TestActualCase"} -{"Action":"output","Output":"FAIL\n"} +{"Action":"output","Output":"FAIL\n","OutputType":"frame"} {"Action":"output","Output":"exit status 1\n"} {"Action":"output","Output":"FAIL github.com/org/project/badtest 0.049s\n"} {"Action":"fail"} diff --git a/src/cmd/internal/test2json/testdata/issue23920.json b/src/cmd/internal/test2json/testdata/issue23920.json index 17e8de6e917c66..9e49a1c6120a21 100644 --- a/src/cmd/internal/test2json/testdata/issue23920.json +++ b/src/cmd/internal/test2json/testdata/issue23920.json @@ -1,15 +1,15 @@ {"Action":"start"} {"Action":"run","Test":"TestWithColons"} -{"Action":"output","Test":"TestWithColons","Output":"=== RUN TestWithColons\n"} +{"Action":"output","Test":"TestWithColons","Output":"=== RUN TestWithColons\n","OutputType":"frame"} {"Action":"run","Test":"TestWithColons/[::1]"} -{"Action":"output","Test":"TestWithColons/[::1]","Output":"=== RUN TestWithColons/[::1]\n"} +{"Action":"output","Test":"TestWithColons/[::1]","Output":"=== RUN TestWithColons/[::1]\n","OutputType":"frame"} {"Action":"run","Test":"TestWithColons/127.0.0.1:0"} -{"Action":"output","Test":"TestWithColons/127.0.0.1:0","Output":"=== RUN TestWithColons/127.0.0.1:0\n"} -{"Action":"output","Test":"TestWithColons","Output":"--- PASS: TestWithColons (0.00s)\n"} -{"Action":"output","Test":"TestWithColons/[::1]","Output":" --- PASS: TestWithColons/[::1] (0.00s)\n"} +{"Action":"output","Test":"TestWithColons/127.0.0.1:0","Output":"=== RUN TestWithColons/127.0.0.1:0\n","OutputType":"frame"} +{"Action":"output","Test":"TestWithColons","Output":"--- PASS: TestWithColons (0.00s)\n","OutputType":"frame"} +{"Action":"output","Test":"TestWithColons/[::1]","Output":" --- PASS: TestWithColons/[::1] (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestWithColons/[::1]"} -{"Action":"output","Test":"TestWithColons/127.0.0.1:0","Output":" --- PASS: TestWithColons/127.0.0.1:0 (0.00s)\n"} +{"Action":"output","Test":"TestWithColons/127.0.0.1:0","Output":" --- PASS: TestWithColons/127.0.0.1:0 (0.00s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestWithColons/127.0.0.1:0"} {"Action":"pass","Test":"TestWithColons"} -{"Action":"output","Output":"PASS\n"} +{"Action":"output","Output":"PASS\n","OutputType":"frame"} {"Action":"pass"} diff --git a/src/cmd/internal/test2json/testdata/issue29755.json b/src/cmd/internal/test2json/testdata/issue29755.json index c49bf92ce2a49a..31af660e0e092b 100644 --- a/src/cmd/internal/test2json/testdata/issue29755.json +++ b/src/cmd/internal/test2json/testdata/issue29755.json @@ -1,39 +1,39 @@ {"Action":"start"} {"Action":"run","Test":"TestOutputWithSubtest"} -{"Action":"output","Test":"TestOutputWithSubtest","Output":"=== RUN TestOutputWithSubtest\n"} +{"Action":"output","Test":"TestOutputWithSubtest","Output":"=== RUN TestOutputWithSubtest\n","OutputType":"frame"} {"Action":"run","Test":"TestOutputWithSubtest/sub_test"} -{"Action":"output","Test":"TestOutputWithSubtest/sub_test","Output":"=== RUN TestOutputWithSubtest/sub_test\n"} +{"Action":"output","Test":"TestOutputWithSubtest/sub_test","Output":"=== RUN TestOutputWithSubtest/sub_test\n","OutputType":"frame"} {"Action":"run","Test":"TestOutputWithSubtest/sub_test/sub2"} -{"Action":"output","Test":"TestOutputWithSubtest/sub_test/sub2","Output":"=== RUN TestOutputWithSubtest/sub_test/sub2\n"} +{"Action":"output","Test":"TestOutputWithSubtest/sub_test/sub2","Output":"=== RUN TestOutputWithSubtest/sub_test/sub2\n","OutputType":"frame"} {"Action":"run","Test":"TestOutputWithSubtest/sub_test2"} -{"Action":"output","Test":"TestOutputWithSubtest/sub_test2","Output":"=== RUN TestOutputWithSubtest/sub_test2\n"} +{"Action":"output","Test":"TestOutputWithSubtest/sub_test2","Output":"=== RUN TestOutputWithSubtest/sub_test2\n","OutputType":"frame"} {"Action":"run","Test":"TestOutputWithSubtest/sub_test2/sub2"} -{"Action":"output","Test":"TestOutputWithSubtest/sub_test2/sub2","Output":"=== RUN TestOutputWithSubtest/sub_test2/sub2\n"} -{"Action":"output","Test":"TestOutputWithSubtest","Output":"--- FAIL: TestOutputWithSubtest (0.00s)\n"} +{"Action":"output","Test":"TestOutputWithSubtest/sub_test2/sub2","Output":"=== RUN TestOutputWithSubtest/sub_test2/sub2\n","OutputType":"frame"} +{"Action":"output","Test":"TestOutputWithSubtest","Output":"--- FAIL: TestOutputWithSubtest (0.00s)\n","OutputType":"frame"} {"Action":"output","Test":"TestOutputWithSubtest","Output":" foo_test.go:6: output before sub tests\n"} {"Action":"output","Test":"TestOutputWithSubtest","Output":" foo_test.go:10: output from root test\n"} {"Action":"output","Test":"TestOutputWithSubtest","Output":" foo_test.go:15: output from root test\n"} -{"Action":"output","Test":"TestOutputWithSubtest/sub_test","Output":" --- PASS: TestOutputWithSubtest/sub_test (0.00s)\n"} +{"Action":"output","Test":"TestOutputWithSubtest/sub_test","Output":" --- PASS: TestOutputWithSubtest/sub_test (0.00s)\n","OutputType":"frame"} {"Action":"output","Test":"TestOutputWithSubtest/sub_test","Output":" foo_test.go:9: output from sub test\n"} {"Action":"output","Test":"TestOutputWithSubtest/sub_test","Output":" foo_test.go:11: more output from sub test\n"} {"Action":"output","Test":"TestOutputWithSubtest/sub_test","Output":" foo_test.go:16: more output from sub test\n"} -{"Action":"output","Test":"TestOutputWithSubtest/sub_test/sub2","Output":" --- PASS: TestOutputWithSubtest/sub_test/sub2 (0.00s)\n"} +{"Action":"output","Test":"TestOutputWithSubtest/sub_test/sub2","Output":" --- PASS: TestOutputWithSubtest/sub_test/sub2 (0.00s)\n","OutputType":"frame"} {"Action":"output","Test":"TestOutputWithSubtest/sub_test/sub2","Output":" foo_test.go:14: output from sub2 test\n"} {"Action":"output","Test":"TestOutputWithSubtest","Output":" foo_test.go:22: output from root test\n"} {"Action":"output","Test":"TestOutputWithSubtest","Output":" foo_test.go:27: output from root test\n"} {"Action":"pass","Test":"TestOutputWithSubtest/sub_test/sub2"} {"Action":"pass","Test":"TestOutputWithSubtest/sub_test"} -{"Action":"output","Test":"TestOutputWithSubtest/sub_test2","Output":" --- PASS: TestOutputWithSubtest/sub_test2 (0.00s)\n"} +{"Action":"output","Test":"TestOutputWithSubtest/sub_test2","Output":" --- PASS: TestOutputWithSubtest/sub_test2 (0.00s)\n","OutputType":"frame"} {"Action":"output","Test":"TestOutputWithSubtest/sub_test2","Output":" foo_test.go:21: output from sub test2\n"} {"Action":"output","Test":"TestOutputWithSubtest/sub_test2","Output":" foo_test.go:23: more output from sub test2\n"} {"Action":"output","Test":"TestOutputWithSubtest/sub_test2","Output":" foo_test.go:28: more output from sub test2\n"} -{"Action":"output","Test":"TestOutputWithSubtest/sub_test2/sub2","Output":" --- PASS: TestOutputWithSubtest/sub_test2/sub2 (0.00s)\n"} +{"Action":"output","Test":"TestOutputWithSubtest/sub_test2/sub2","Output":" --- PASS: TestOutputWithSubtest/sub_test2/sub2 (0.00s)\n","OutputType":"frame"} {"Action":"output","Test":"TestOutputWithSubtest/sub_test2/sub2","Output":" foo_test.go:26: output from sub2 test\n"} {"Action":"output","Test":"TestOutputWithSubtest","Output":" foo_test.go:32: output after sub test\n"} {"Action":"pass","Test":"TestOutputWithSubtest/sub_test2/sub2"} {"Action":"pass","Test":"TestOutputWithSubtest/sub_test2"} {"Action":"fail","Test":"TestOutputWithSubtest"} -{"Action":"output","Output":"FAIL\n"} -{"Action":"output","Output":"FAIL\tgotest.tools/gotestsum/foo\t0.001s\n"} -{"Action":"output","Output":"FAIL\n"} +{"Action":"output","Output":"FAIL\n","OutputType":"frame"} +{"Action":"output","Output":"FAIL\tgotest.tools/gotestsum/foo\t0.001s\n","OutputType":"frame"} +{"Action":"output","Output":"FAIL\n","OutputType":"frame"} {"Action":"fail"} diff --git a/src/cmd/internal/test2json/testdata/multiline-error.src b/src/cmd/internal/test2json/testdata/multiline-error.src new file mode 100644 index 00000000000000..a09570bd820af5 --- /dev/null +++ b/src/cmd/internal/test2json/testdata/multiline-error.src @@ -0,0 +1,15 @@ +! go test -v=test2json + +stdout '=== RUN Test' + +-- go.mod -- +module p + +-- x_test.go -- +package p + +import "testing" + +func Test(t *testing.T) { + t.Error("Error1\nError2\r") +} diff --git a/src/cmd/internal/test2json/testdata/panic.json b/src/cmd/internal/test2json/testdata/panic.json index 1cd43846298b5c..47ee1a6eeb6fca 100644 --- a/src/cmd/internal/test2json/testdata/panic.json +++ b/src/cmd/internal/test2json/testdata/panic.json @@ -1,5 +1,5 @@ {"Action":"start"} -{"Action":"output","Test":"TestPanic","Output":"--- FAIL: TestPanic (0.00s)\n"} +{"Action":"output","Test":"TestPanic","Output":"--- FAIL: TestPanic (0.00s)\n","OutputType":"frame"} {"Action":"output","Test":"TestPanic","Output":"panic: oops [recovered]\n"} {"Action":"output","Test":"TestPanic","Output":"\tpanic: oops\n"} {"Action":"output","Test":"TestPanic","Output":"\n"} @@ -15,6 +15,6 @@ {"Action":"output","Test":"TestPanic","Output":"created by testing.(*T).Run\n"} {"Action":"output","Test":"TestPanic","Output":"\tgo/src/testing/testing.go:960 +0x350\n"} {"Action":"fail","Test":"TestPanic"} -{"Action":"output","Output":"FAIL\tcommand-line-arguments\t0.042s\n"} -{"Action":"output","Output":"FAIL\n"} +{"Action":"output","Output":"FAIL\tcommand-line-arguments\t0.042s\n","OutputType":"frame"} +{"Action":"output","Output":"FAIL\n","OutputType":"frame"} {"Action":"fail"} diff --git a/src/cmd/internal/test2json/testdata/smiley.json b/src/cmd/internal/test2json/testdata/smiley.json index 858843f3af2174..196bbf29067f65 100644 --- a/src/cmd/internal/test2json/testdata/smiley.json +++ b/src/cmd/internal/test2json/testdata/smiley.json @@ -1,183 +1,183 @@ {"Action":"start"} {"Action":"run","Test":"Test☺☹"} -{"Action":"output","Test":"Test☺☹","Output":"=== RUN Test☺☹\n"} -{"Action":"output","Test":"Test☺☹","Output":"=== PAUSE Test☺☹\n"} +{"Action":"output","Test":"Test☺☹","Output":"=== RUN Test☺☹\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹","Output":"=== PAUSE Test☺☹\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹"} {"Action":"run","Test":"Test☺☹Asm"} -{"Action":"output","Test":"Test☺☹Asm","Output":"=== RUN Test☺☹Asm\n"} -{"Action":"output","Test":"Test☺☹Asm","Output":"=== PAUSE Test☺☹Asm\n"} +{"Action":"output","Test":"Test☺☹Asm","Output":"=== RUN Test☺☹Asm\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹Asm","Output":"=== PAUSE Test☺☹Asm\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹Asm"} {"Action":"run","Test":"Test☺☹Dirs"} -{"Action":"output","Test":"Test☺☹Dirs","Output":"=== RUN Test☺☹Dirs\n"} -{"Action":"output","Test":"Test☺☹Dirs","Output":"=== PAUSE Test☺☹Dirs\n"} +{"Action":"output","Test":"Test☺☹Dirs","Output":"=== RUN Test☺☹Dirs\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹Dirs","Output":"=== PAUSE Test☺☹Dirs\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹Dirs"} {"Action":"run","Test":"TestTags"} -{"Action":"output","Test":"TestTags","Output":"=== RUN TestTags\n"} -{"Action":"output","Test":"TestTags","Output":"=== PAUSE TestTags\n"} +{"Action":"output","Test":"TestTags","Output":"=== RUN TestTags\n","OutputType":"frame"} +{"Action":"output","Test":"TestTags","Output":"=== PAUSE TestTags\n","OutputType":"frame"} {"Action":"pause","Test":"TestTags"} {"Action":"run","Test":"Test☺☹Verbose"} -{"Action":"output","Test":"Test☺☹Verbose","Output":"=== RUN Test☺☹Verbose\n"} -{"Action":"output","Test":"Test☺☹Verbose","Output":"=== PAUSE Test☺☹Verbose\n"} +{"Action":"output","Test":"Test☺☹Verbose","Output":"=== RUN Test☺☹Verbose\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹Verbose","Output":"=== PAUSE Test☺☹Verbose\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹Verbose"} {"Action":"cont","Test":"Test☺☹"} -{"Action":"output","Test":"Test☺☹","Output":"=== CONT Test☺☹\n"} +{"Action":"output","Test":"Test☺☹","Output":"=== CONT Test☺☹\n","OutputType":"frame"} {"Action":"cont","Test":"TestTags"} -{"Action":"output","Test":"TestTags","Output":"=== CONT TestTags\n"} +{"Action":"output","Test":"TestTags","Output":"=== CONT TestTags\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹Verbose"} -{"Action":"output","Test":"Test☺☹Verbose","Output":"=== CONT Test☺☹Verbose\n"} +{"Action":"output","Test":"Test☺☹Verbose","Output":"=== CONT Test☺☹Verbose\n","OutputType":"frame"} {"Action":"run","Test":"TestTags/testtag"} -{"Action":"output","Test":"TestTags/testtag","Output":"=== RUN TestTags/testtag\n"} -{"Action":"output","Test":"TestTags/testtag","Output":"=== PAUSE TestTags/testtag\n"} +{"Action":"output","Test":"TestTags/testtag","Output":"=== RUN TestTags/testtag\n","OutputType":"frame"} +{"Action":"output","Test":"TestTags/testtag","Output":"=== PAUSE TestTags/testtag\n","OutputType":"frame"} {"Action":"pause","Test":"TestTags/testtag"} {"Action":"cont","Test":"Test☺☹Dirs"} -{"Action":"output","Test":"Test☺☹Dirs","Output":"=== CONT Test☺☹Dirs\n"} +{"Action":"output","Test":"Test☺☹Dirs","Output":"=== CONT Test☺☹Dirs\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹Asm"} -{"Action":"output","Test":"Test☺☹Asm","Output":"=== CONT Test☺☹Asm\n"} +{"Action":"output","Test":"Test☺☹Asm","Output":"=== CONT Test☺☹Asm\n","OutputType":"frame"} {"Action":"run","Test":"Test☺☹/0"} -{"Action":"output","Test":"Test☺☹/0","Output":"=== RUN Test☺☹/0\n"} -{"Action":"output","Test":"Test☺☹/0","Output":"=== PAUSE Test☺☹/0\n"} +{"Action":"output","Test":"Test☺☹/0","Output":"=== RUN Test☺☹/0\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹/0","Output":"=== PAUSE Test☺☹/0\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹/0"} {"Action":"run","Test":"Test☺☹/1"} -{"Action":"output","Test":"Test☺☹/1","Output":"=== RUN Test☺☹/1\n"} -{"Action":"output","Test":"Test☺☹/1","Output":"=== PAUSE Test☺☹/1\n"} +{"Action":"output","Test":"Test☺☹/1","Output":"=== RUN Test☺☹/1\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹/1","Output":"=== PAUSE Test☺☹/1\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹/1"} {"Action":"run","Test":"Test☺☹/2"} -{"Action":"output","Test":"Test☺☹/2","Output":"=== RUN Test☺☹/2\n"} -{"Action":"output","Test":"Test☺☹/2","Output":"=== PAUSE Test☺☹/2\n"} +{"Action":"output","Test":"Test☺☹/2","Output":"=== RUN Test☺☹/2\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹/2","Output":"=== PAUSE Test☺☹/2\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹/2"} {"Action":"run","Test":"Test☺☹/3"} -{"Action":"output","Test":"Test☺☹/3","Output":"=== RUN Test☺☹/3\n"} -{"Action":"output","Test":"Test☺☹/3","Output":"=== PAUSE Test☺☹/3\n"} +{"Action":"output","Test":"Test☺☹/3","Output":"=== RUN Test☺☹/3\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹/3","Output":"=== PAUSE Test☺☹/3\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹/3"} {"Action":"run","Test":"Test☺☹/4"} -{"Action":"output","Test":"Test☺☹/4","Output":"=== RUN Test☺☹/4\n"} +{"Action":"output","Test":"Test☺☹/4","Output":"=== RUN Test☺☹/4\n","OutputType":"frame"} {"Action":"run","Test":"TestTags/x_testtag_y"} -{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== RUN TestTags/x_testtag_y\n"} -{"Action":"output","Test":"Test☺☹/4","Output":"=== PAUSE Test☺☹/4\n"} +{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== RUN TestTags/x_testtag_y\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹/4","Output":"=== PAUSE Test☺☹/4\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹/4"} {"Action":"run","Test":"Test☺☹/5"} -{"Action":"output","Test":"Test☺☹/5","Output":"=== RUN Test☺☹/5\n"} -{"Action":"output","Test":"Test☺☹/5","Output":"=== PAUSE Test☺☹/5\n"} +{"Action":"output","Test":"Test☺☹/5","Output":"=== RUN Test☺☹/5\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹/5","Output":"=== PAUSE Test☺☹/5\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹/5"} -{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== PAUSE TestTags/x_testtag_y\n"} +{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== PAUSE TestTags/x_testtag_y\n","OutputType":"frame"} {"Action":"pause","Test":"TestTags/x_testtag_y"} {"Action":"run","Test":"Test☺☹/6"} -{"Action":"output","Test":"Test☺☹/6","Output":"=== RUN Test☺☹/6\n"} +{"Action":"output","Test":"Test☺☹/6","Output":"=== RUN Test☺☹/6\n","OutputType":"frame"} {"Action":"run","Test":"TestTags/x,testtag,y"} -{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== RUN TestTags/x,testtag,y\n"} -{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== PAUSE TestTags/x,testtag,y\n"} +{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== RUN TestTags/x,testtag,y\n","OutputType":"frame"} +{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== PAUSE TestTags/x,testtag,y\n","OutputType":"frame"} {"Action":"pause","Test":"TestTags/x,testtag,y"} {"Action":"run","Test":"Test☺☹Dirs/testingpkg"} -{"Action":"output","Test":"Test☺☹Dirs/testingpkg","Output":"=== RUN Test☺☹Dirs/testingpkg\n"} -{"Action":"output","Test":"Test☺☹/6","Output":"=== PAUSE Test☺☹/6\n"} +{"Action":"output","Test":"Test☺☹Dirs/testingpkg","Output":"=== RUN Test☺☹Dirs/testingpkg\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹/6","Output":"=== PAUSE Test☺☹/6\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹/6"} {"Action":"cont","Test":"TestTags/x,testtag,y"} -{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== CONT TestTags/x,testtag,y\n"} -{"Action":"output","Test":"Test☺☹Dirs/testingpkg","Output":"=== PAUSE Test☺☹Dirs/testingpkg\n"} +{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== CONT TestTags/x,testtag,y\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹Dirs/testingpkg","Output":"=== PAUSE Test☺☹Dirs/testingpkg\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹Dirs/testingpkg"} {"Action":"run","Test":"Test☺☹Dirs/divergent"} -{"Action":"output","Test":"Test☺☹Dirs/divergent","Output":"=== RUN Test☺☹Dirs/divergent\n"} +{"Action":"output","Test":"Test☺☹Dirs/divergent","Output":"=== RUN Test☺☹Dirs/divergent\n","OutputType":"frame"} {"Action":"run","Test":"Test☺☹/7"} -{"Action":"output","Test":"Test☺☹/7","Output":"=== RUN Test☺☹/7\n"} -{"Action":"output","Test":"Test☺☹/7","Output":"=== PAUSE Test☺☹/7\n"} +{"Action":"output","Test":"Test☺☹/7","Output":"=== RUN Test☺☹/7\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹/7","Output":"=== PAUSE Test☺☹/7\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹/7"} -{"Action":"output","Test":"Test☺☹Dirs/divergent","Output":"=== PAUSE Test☺☹Dirs/divergent\n"} +{"Action":"output","Test":"Test☺☹Dirs/divergent","Output":"=== PAUSE Test☺☹Dirs/divergent\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹Dirs/divergent"} {"Action":"cont","Test":"TestTags/x_testtag_y"} -{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== CONT TestTags/x_testtag_y\n"} +{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== CONT TestTags/x_testtag_y\n","OutputType":"frame"} {"Action":"cont","Test":"TestTags/testtag"} -{"Action":"output","Test":"TestTags/testtag","Output":"=== CONT TestTags/testtag\n"} +{"Action":"output","Test":"TestTags/testtag","Output":"=== CONT TestTags/testtag\n","OutputType":"frame"} {"Action":"run","Test":"Test☺☹Dirs/buildtag"} -{"Action":"output","Test":"Test☺☹Dirs/buildtag","Output":"=== RUN Test☺☹Dirs/buildtag\n"} -{"Action":"output","Test":"Test☺☹Dirs/buildtag","Output":"=== PAUSE Test☺☹Dirs/buildtag\n"} +{"Action":"output","Test":"Test☺☹Dirs/buildtag","Output":"=== RUN Test☺☹Dirs/buildtag\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹Dirs/buildtag","Output":"=== PAUSE Test☺☹Dirs/buildtag\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹Dirs/buildtag"} {"Action":"cont","Test":"Test☺☹/0"} -{"Action":"output","Test":"Test☺☹/0","Output":"=== CONT Test☺☹/0\n"} +{"Action":"output","Test":"Test☺☹/0","Output":"=== CONT Test☺☹/0\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹/4"} -{"Action":"output","Test":"Test☺☹/4","Output":"=== CONT Test☺☹/4\n"} +{"Action":"output","Test":"Test☺☹/4","Output":"=== CONT Test☺☹/4\n","OutputType":"frame"} {"Action":"run","Test":"Test☺☹Dirs/incomplete"} -{"Action":"output","Test":"Test☺☹Dirs/incomplete","Output":"=== RUN Test☺☹Dirs/incomplete\n"} -{"Action":"output","Test":"Test☺☹Dirs/incomplete","Output":"=== PAUSE Test☺☹Dirs/incomplete\n"} +{"Action":"output","Test":"Test☺☹Dirs/incomplete","Output":"=== RUN Test☺☹Dirs/incomplete\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹Dirs/incomplete","Output":"=== PAUSE Test☺☹Dirs/incomplete\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹Dirs/incomplete"} {"Action":"run","Test":"Test☺☹Dirs/cgo"} -{"Action":"output","Test":"Test☺☹Dirs/cgo","Output":"=== RUN Test☺☹Dirs/cgo\n"} -{"Action":"output","Test":"Test☺☹Dirs/cgo","Output":"=== PAUSE Test☺☹Dirs/cgo\n"} +{"Action":"output","Test":"Test☺☹Dirs/cgo","Output":"=== RUN Test☺☹Dirs/cgo\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹Dirs/cgo","Output":"=== PAUSE Test☺☹Dirs/cgo\n","OutputType":"frame"} {"Action":"pause","Test":"Test☺☹Dirs/cgo"} {"Action":"cont","Test":"Test☺☹/7"} -{"Action":"output","Test":"Test☺☹/7","Output":"=== CONT Test☺☹/7\n"} +{"Action":"output","Test":"Test☺☹/7","Output":"=== CONT Test☺☹/7\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹/6"} -{"Action":"output","Test":"Test☺☹/6","Output":"=== CONT Test☺☹/6\n"} -{"Action":"output","Test":"Test☺☹Verbose","Output":"--- PASS: Test☺☹Verbose (0.04s)\n"} +{"Action":"output","Test":"Test☺☹/6","Output":"=== CONT Test☺☹/6\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹Verbose","Output":"--- PASS: Test☺☹Verbose (0.04s)\n","OutputType":"frame"} {"Action":"pass","Test":"Test☺☹Verbose"} {"Action":"cont","Test":"Test☺☹/5"} -{"Action":"output","Test":"Test☺☹/5","Output":"=== CONT Test☺☹/5\n"} +{"Action":"output","Test":"Test☺☹/5","Output":"=== CONT Test☺☹/5\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹/3"} -{"Action":"output","Test":"Test☺☹/3","Output":"=== CONT Test☺☹/3\n"} +{"Action":"output","Test":"Test☺☹/3","Output":"=== CONT Test☺☹/3\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹/2"} -{"Action":"output","Test":"Test☺☹/2","Output":"=== CONT Test☺☹/2\n"} -{"Action":"output","Test":"TestTags","Output":"--- PASS: TestTags (0.00s)\n"} -{"Action":"output","Test":"TestTags/x_testtag_y","Output":" --- PASS: TestTags/x_testtag_y (0.04s)\n"} +{"Action":"output","Test":"Test☺☹/2","Output":"=== CONT Test☺☹/2\n","OutputType":"frame"} +{"Action":"output","Test":"TestTags","Output":"--- PASS: TestTags (0.00s)\n","OutputType":"frame"} +{"Action":"output","Test":"TestTags/x_testtag_y","Output":" --- PASS: TestTags/x_testtag_y (0.04s)\n","OutputType":"frame"} {"Action":"output","Test":"TestTags/x_testtag_y","Output":" vet_test.go:187: -tags=x testtag y\n"} {"Action":"pass","Test":"TestTags/x_testtag_y"} -{"Action":"output","Test":"TestTags/x,testtag,y","Output":" --- PASS: TestTags/x,testtag,y (0.04s)\n"} +{"Action":"output","Test":"TestTags/x,testtag,y","Output":" --- PASS: TestTags/x,testtag,y (0.04s)\n","OutputType":"frame"} {"Action":"output","Test":"TestTags/x,testtag,y","Output":" vet_test.go:187: -tags=x,testtag,y\n"} {"Action":"pass","Test":"TestTags/x,testtag,y"} -{"Action":"output","Test":"TestTags/testtag","Output":" --- PASS: TestTags/testtag (0.04s)\n"} +{"Action":"output","Test":"TestTags/testtag","Output":" --- PASS: TestTags/testtag (0.04s)\n","OutputType":"frame"} {"Action":"output","Test":"TestTags/testtag","Output":" vet_test.go:187: -tags=testtag\n"} {"Action":"pass","Test":"TestTags/testtag"} {"Action":"pass","Test":"TestTags"} {"Action":"cont","Test":"Test☺☹/1"} -{"Action":"output","Test":"Test☺☹/1","Output":"=== CONT Test☺☹/1\n"} +{"Action":"output","Test":"Test☺☹/1","Output":"=== CONT Test☺☹/1\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹Dirs/testingpkg"} -{"Action":"output","Test":"Test☺☹Dirs/testingpkg","Output":"=== CONT Test☺☹Dirs/testingpkg\n"} +{"Action":"output","Test":"Test☺☹Dirs/testingpkg","Output":"=== CONT Test☺☹Dirs/testingpkg\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹Dirs/buildtag"} -{"Action":"output","Test":"Test☺☹Dirs/buildtag","Output":"=== CONT Test☺☹Dirs/buildtag\n"} +{"Action":"output","Test":"Test☺☹Dirs/buildtag","Output":"=== CONT Test☺☹Dirs/buildtag\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹Dirs/divergent"} -{"Action":"output","Test":"Test☺☹Dirs/divergent","Output":"=== CONT Test☺☹Dirs/divergent\n"} +{"Action":"output","Test":"Test☺☹Dirs/divergent","Output":"=== CONT Test☺☹Dirs/divergent\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹Dirs/incomplete"} -{"Action":"output","Test":"Test☺☹Dirs/incomplete","Output":"=== CONT Test☺☹Dirs/incomplete\n"} +{"Action":"output","Test":"Test☺☹Dirs/incomplete","Output":"=== CONT Test☺☹Dirs/incomplete\n","OutputType":"frame"} {"Action":"cont","Test":"Test☺☹Dirs/cgo"} -{"Action":"output","Test":"Test☺☹Dirs/cgo","Output":"=== CONT Test☺☹Dirs/cgo\n"} -{"Action":"output","Test":"Test☺☹","Output":"--- PASS: Test☺☹ (0.39s)\n"} -{"Action":"output","Test":"Test☺☹/5","Output":" --- PASS: Test☺☹/5 (0.07s)\n"} +{"Action":"output","Test":"Test☺☹Dirs/cgo","Output":"=== CONT Test☺☹Dirs/cgo\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹","Output":"--- PASS: Test☺☹ (0.39s)\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹/5","Output":" --- PASS: Test☺☹/5 (0.07s)\n","OutputType":"frame"} {"Action":"output","Test":"Test☺☹/5","Output":" vet_test.go:114: φιλεσ: [\"testdata/copylock_func.go\" \"testdata/rangeloop.go\"]\n"} {"Action":"pass","Test":"Test☺☹/5"} -{"Action":"output","Test":"Test☺☹/3","Output":" --- PASS: Test☺☹/3 (0.07s)\n"} +{"Action":"output","Test":"Test☺☹/3","Output":" --- PASS: Test☺☹/3 (0.07s)\n","OutputType":"frame"} {"Action":"output","Test":"Test☺☹/3","Output":" vet_test.go:114: φιλεσ: [\"testdata/composite.go\" \"testdata/nilfunc.go\"]\n"} {"Action":"pass","Test":"Test☺☹/3"} -{"Action":"output","Test":"Test☺☹/6","Output":" --- PASS: Test☺☹/6 (0.07s)\n"} +{"Action":"output","Test":"Test☺☹/6","Output":" --- PASS: Test☺☹/6 (0.07s)\n","OutputType":"frame"} {"Action":"output","Test":"Test☺☹/6","Output":" vet_test.go:114: φιλεσ: [\"testdata/copylock_range.go\" \"testdata/shadow.go\"]\n"} {"Action":"pass","Test":"Test☺☹/6"} -{"Action":"output","Test":"Test☺☹/2","Output":" --- PASS: Test☺☹/2 (0.07s)\n"} +{"Action":"output","Test":"Test☺☹/2","Output":" --- PASS: Test☺☹/2 (0.07s)\n","OutputType":"frame"} {"Action":"output","Test":"Test☺☹/2","Output":" vet_test.go:114: φιλεσ: [\"testdata/bool.go\" \"testdata/method.go\" \"testdata/unused.go\"]\n"} {"Action":"pass","Test":"Test☺☹/2"} -{"Action":"output","Test":"Test☺☹/0","Output":" --- PASS: Test☺☹/0 (0.13s)\n"} +{"Action":"output","Test":"Test☺☹/0","Output":" --- PASS: Test☺☹/0 (0.13s)\n","OutputType":"frame"} {"Action":"output","Test":"Test☺☹/0","Output":" vet_test.go:114: φιλεσ: [\"testdata/assign.go\" \"testdata/httpresponse.go\" \"testdata/structtag.go\"]\n"} {"Action":"pass","Test":"Test☺☹/0"} -{"Action":"output","Test":"Test☺☹/4","Output":" --- PASS: Test☺☹/4 (0.16s)\n"} +{"Action":"output","Test":"Test☺☹/4","Output":" --- PASS: Test☺☹/4 (0.16s)\n","OutputType":"frame"} {"Action":"output","Test":"Test☺☹/4","Output":" vet_test.go:114: φιλεσ: [\"testdata/copylock.go\" \"testdata/print.go\"]\n"} {"Action":"pass","Test":"Test☺☹/4"} -{"Action":"output","Test":"Test☺☹/1","Output":" --- PASS: Test☺☹/1 (0.07s)\n"} +{"Action":"output","Test":"Test☺☹/1","Output":" --- PASS: Test☺☹/1 (0.07s)\n","OutputType":"frame"} {"Action":"output","Test":"Test☺☹/1","Output":" vet_test.go:114: φιλεσ: [\"testdata/atomic.go\" \"testdata/lostcancel.go\" \"testdata/unsafeptr.go\"]\n"} {"Action":"pass","Test":"Test☺☹/1"} -{"Action":"output","Test":"Test☺☹/7","Output":" --- PASS: Test☺☹/7 (0.19s)\n"} +{"Action":"output","Test":"Test☺☹/7","Output":" --- PASS: Test☺☹/7 (0.19s)\n","OutputType":"frame"} {"Action":"output","Test":"Test☺☹/7","Output":" vet_test.go:114: φιλεσ: [\"testdata/deadcode.go\" \"testdata/shift.go\"]\n"} {"Action":"pass","Test":"Test☺☹/7"} {"Action":"pass","Test":"Test☺☹"} -{"Action":"output","Test":"Test☺☹Dirs","Output":"--- PASS: Test☺☹Dirs (0.01s)\n"} -{"Action":"output","Test":"Test☺☹Dirs/testingpkg","Output":" --- PASS: Test☺☹Dirs/testingpkg (0.06s)\n"} +{"Action":"output","Test":"Test☺☹Dirs","Output":"--- PASS: Test☺☹Dirs (0.01s)\n","OutputType":"frame"} +{"Action":"output","Test":"Test☺☹Dirs/testingpkg","Output":" --- PASS: Test☺☹Dirs/testingpkg (0.06s)\n","OutputType":"frame"} {"Action":"pass","Test":"Test☺☹Dirs/testingpkg"} -{"Action":"output","Test":"Test☺☹Dirs/divergent","Output":" --- PASS: Test☺☹Dirs/divergent (0.05s)\n"} +{"Action":"output","Test":"Test☺☹Dirs/divergent","Output":" --- PASS: Test☺☹Dirs/divergent (0.05s)\n","OutputType":"frame"} {"Action":"pass","Test":"Test☺☹Dirs/divergent"} -{"Action":"output","Test":"Test☺☹Dirs/buildtag","Output":" --- PASS: Test☺☹Dirs/buildtag (0.06s)\n"} +{"Action":"output","Test":"Test☺☹Dirs/buildtag","Output":" --- PASS: Test☺☹Dirs/buildtag (0.06s)\n","OutputType":"frame"} {"Action":"pass","Test":"Test☺☹Dirs/buildtag"} -{"Action":"output","Test":"Test☺☹Dirs/incomplete","Output":" --- PASS: Test☺☹Dirs/incomplete (0.05s)\n"} +{"Action":"output","Test":"Test☺☹Dirs/incomplete","Output":" --- PASS: Test☺☹Dirs/incomplete (0.05s)\n","OutputType":"frame"} {"Action":"pass","Test":"Test☺☹Dirs/incomplete"} -{"Action":"output","Test":"Test☺☹Dirs/cgo","Output":" --- PASS: Test☺☹Dirs/cgo (0.04s)\n"} +{"Action":"output","Test":"Test☺☹Dirs/cgo","Output":" --- PASS: Test☺☹Dirs/cgo (0.04s)\n","OutputType":"frame"} {"Action":"pass","Test":"Test☺☹Dirs/cgo"} {"Action":"pass","Test":"Test☺☹Dirs"} -{"Action":"output","Test":"Test☺☹Asm","Output":"--- PASS: Test☺☹Asm (0.75s)\n"} +{"Action":"output","Test":"Test☺☹Asm","Output":"--- PASS: Test☺☹Asm (0.75s)\n","OutputType":"frame"} {"Action":"pass","Test":"Test☺☹Asm"} -{"Action":"output","Output":"PASS\n"} +{"Action":"output","Output":"PASS\n","OutputType":"frame"} {"Action":"output","Output":"ok \tcmd/vet\t(cached)\n"} {"Action":"pass"} diff --git a/src/cmd/internal/test2json/testdata/timeout.json b/src/cmd/internal/test2json/testdata/timeout.json index dc225262f7c326..325d811d0e7c30 100644 --- a/src/cmd/internal/test2json/testdata/timeout.json +++ b/src/cmd/internal/test2json/testdata/timeout.json @@ -1,8 +1,8 @@ {"Action":"start"} {"Action":"run","Test":"Test"} -{"Action":"output","Test":"Test","Output":"=== RUN Test\n"} +{"Action":"output","Test":"Test","Output":"=== RUN Test\n","OutputType":"frame"} {"Action":"output","Test":"Test","Output":"panic: test timed out after 1s\n"} {"Action":"output","Test":"Test","Output":"\n"} -{"Action":"output","Output":"FAIL\tp\t1.111s\n"} -{"Action":"output","Output":"FAIL\n"} +{"Action":"output","Output":"FAIL\tp\t1.111s\n","OutputType":"frame"} +{"Action":"output","Output":"FAIL\n","OutputType":"frame"} {"Action":"fail"} diff --git a/src/cmd/internal/test2json/testdata/unicode.json b/src/cmd/internal/test2json/testdata/unicode.json index 2cc3e7322ddf48..aa6e52acb8ac3b 100644 --- a/src/cmd/internal/test2json/testdata/unicode.json +++ b/src/cmd/internal/test2json/testdata/unicode.json @@ -1,11 +1,11 @@ {"Action":"start"} {"Action":"run","Test":"TestUnicode"} -{"Action":"output","Test":"TestUnicode","Output":"=== RUN TestUnicode\n"} +{"Action":"output","Test":"TestUnicode","Output":"=== RUN TestUnicode\n","OutputType":"frame"} {"Action":"output","Test":"TestUnicode","Output":"Μπορώ να φάω σπασμένα γυαλιά χωρίς να πάθω τίποτα. Μπορώ να φάω σπασμένα γυαλιά χωρίς να πάθω τίποτα.\n"} {"Action":"output","Test":"TestUnicode","Output":"私はガラスを食べられます。それは私を傷つけません。私はガラスを食べられます。それは私を傷つけません。\n"} -{"Action":"output","Test":"TestUnicode","Output":"--- PASS: TestUnicode\n"} +{"Action":"output","Test":"TestUnicode","Output":"--- PASS: TestUnicode\n","OutputType":"frame"} {"Action":"output","Test":"TestUnicode","Output":" ฉันกินกระจกได้ แต่มันไม่ทำให้ฉันเจ็บ ฉันกินกระจกได้ แต่มันไม่ทำให้ฉันเจ็บ\n"} {"Action":"output","Test":"TestUnicode","Output":" אני יכול לאכול זכוכית וזה לא מזיק לי. אני יכול לאכול זכוכית וזה לא מזיק לי.\n"} {"Action":"pass","Test":"TestUnicode"} -{"Action":"output","Output":"PASS\n"} +{"Action":"output","Output":"PASS\n","OutputType":"frame"} {"Action":"pass"} diff --git a/src/cmd/internal/test2json/testdata/vet.json b/src/cmd/internal/test2json/testdata/vet.json index 5b09104522af94..fcdc46e097855f 100644 --- a/src/cmd/internal/test2json/testdata/vet.json +++ b/src/cmd/internal/test2json/testdata/vet.json @@ -1,183 +1,183 @@ {"Action":"start"} {"Action":"run","Test":"TestVet"} -{"Action":"output","Test":"TestVet","Output":"=== RUN TestVet\n"} -{"Action":"output","Test":"TestVet","Output":"=== PAUSE TestVet\n"} +{"Action":"output","Test":"TestVet","Output":"=== RUN TestVet\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet","Output":"=== PAUSE TestVet\n","OutputType":"frame"} {"Action":"pause","Test":"TestVet"} {"Action":"run","Test":"TestVetAsm"} -{"Action":"output","Test":"TestVetAsm","Output":"=== RUN TestVetAsm\n"} -{"Action":"output","Test":"TestVetAsm","Output":"=== PAUSE TestVetAsm\n"} +{"Action":"output","Test":"TestVetAsm","Output":"=== RUN TestVetAsm\n","OutputType":"frame"} +{"Action":"output","Test":"TestVetAsm","Output":"=== PAUSE TestVetAsm\n","OutputType":"frame"} {"Action":"pause","Test":"TestVetAsm"} {"Action":"run","Test":"TestVetDirs"} -{"Action":"output","Test":"TestVetDirs","Output":"=== RUN TestVetDirs\n"} -{"Action":"output","Test":"TestVetDirs","Output":"=== PAUSE TestVetDirs\n"} +{"Action":"output","Test":"TestVetDirs","Output":"=== RUN TestVetDirs\n","OutputType":"frame"} +{"Action":"output","Test":"TestVetDirs","Output":"=== PAUSE TestVetDirs\n","OutputType":"frame"} {"Action":"pause","Test":"TestVetDirs"} {"Action":"run","Test":"TestTags"} -{"Action":"output","Test":"TestTags","Output":"=== RUN TestTags\n"} -{"Action":"output","Test":"TestTags","Output":"=== PAUSE TestTags\n"} +{"Action":"output","Test":"TestTags","Output":"=== RUN TestTags\n","OutputType":"frame"} +{"Action":"output","Test":"TestTags","Output":"=== PAUSE TestTags\n","OutputType":"frame"} {"Action":"pause","Test":"TestTags"} {"Action":"run","Test":"TestVetVerbose"} -{"Action":"output","Test":"TestVetVerbose","Output":"=== RUN TestVetVerbose\n"} -{"Action":"output","Test":"TestVetVerbose","Output":"=== PAUSE TestVetVerbose\n"} +{"Action":"output","Test":"TestVetVerbose","Output":"=== RUN TestVetVerbose\n","OutputType":"frame"} +{"Action":"output","Test":"TestVetVerbose","Output":"=== PAUSE TestVetVerbose\n","OutputType":"frame"} {"Action":"pause","Test":"TestVetVerbose"} {"Action":"cont","Test":"TestVet"} -{"Action":"output","Test":"TestVet","Output":"=== CONT TestVet\n"} +{"Action":"output","Test":"TestVet","Output":"=== CONT TestVet\n","OutputType":"frame"} {"Action":"cont","Test":"TestTags"} -{"Action":"output","Test":"TestTags","Output":"=== CONT TestTags\n"} +{"Action":"output","Test":"TestTags","Output":"=== CONT TestTags\n","OutputType":"frame"} {"Action":"cont","Test":"TestVetVerbose"} -{"Action":"output","Test":"TestVetVerbose","Output":"=== CONT TestVetVerbose\n"} +{"Action":"output","Test":"TestVetVerbose","Output":"=== CONT TestVetVerbose\n","OutputType":"frame"} {"Action":"run","Test":"TestTags/testtag"} -{"Action":"output","Test":"TestTags/testtag","Output":"=== RUN TestTags/testtag\n"} -{"Action":"output","Test":"TestTags/testtag","Output":"=== PAUSE TestTags/testtag\n"} +{"Action":"output","Test":"TestTags/testtag","Output":"=== RUN TestTags/testtag\n","OutputType":"frame"} +{"Action":"output","Test":"TestTags/testtag","Output":"=== PAUSE TestTags/testtag\n","OutputType":"frame"} {"Action":"pause","Test":"TestTags/testtag"} {"Action":"cont","Test":"TestVetDirs"} -{"Action":"output","Test":"TestVetDirs","Output":"=== CONT TestVetDirs\n"} +{"Action":"output","Test":"TestVetDirs","Output":"=== CONT TestVetDirs\n","OutputType":"frame"} {"Action":"cont","Test":"TestVetAsm"} -{"Action":"output","Test":"TestVetAsm","Output":"=== CONT TestVetAsm\n"} +{"Action":"output","Test":"TestVetAsm","Output":"=== CONT TestVetAsm\n","OutputType":"frame"} {"Action":"run","Test":"TestVet/0"} -{"Action":"output","Test":"TestVet/0","Output":"=== RUN TestVet/0\n"} -{"Action":"output","Test":"TestVet/0","Output":"=== PAUSE TestVet/0\n"} +{"Action":"output","Test":"TestVet/0","Output":"=== RUN TestVet/0\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet/0","Output":"=== PAUSE TestVet/0\n","OutputType":"frame"} {"Action":"pause","Test":"TestVet/0"} {"Action":"run","Test":"TestVet/1"} -{"Action":"output","Test":"TestVet/1","Output":"=== RUN TestVet/1\n"} -{"Action":"output","Test":"TestVet/1","Output":"=== PAUSE TestVet/1\n"} +{"Action":"output","Test":"TestVet/1","Output":"=== RUN TestVet/1\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet/1","Output":"=== PAUSE TestVet/1\n","OutputType":"frame"} {"Action":"pause","Test":"TestVet/1"} {"Action":"run","Test":"TestVet/2"} -{"Action":"output","Test":"TestVet/2","Output":"=== RUN TestVet/2\n"} -{"Action":"output","Test":"TestVet/2","Output":"=== PAUSE TestVet/2\n"} +{"Action":"output","Test":"TestVet/2","Output":"=== RUN TestVet/2\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet/2","Output":"=== PAUSE TestVet/2\n","OutputType":"frame"} {"Action":"pause","Test":"TestVet/2"} {"Action":"run","Test":"TestVet/3"} -{"Action":"output","Test":"TestVet/3","Output":"=== RUN TestVet/3\n"} -{"Action":"output","Test":"TestVet/3","Output":"=== PAUSE TestVet/3\n"} +{"Action":"output","Test":"TestVet/3","Output":"=== RUN TestVet/3\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet/3","Output":"=== PAUSE TestVet/3\n","OutputType":"frame"} {"Action":"pause","Test":"TestVet/3"} {"Action":"run","Test":"TestVet/4"} -{"Action":"output","Test":"TestVet/4","Output":"=== RUN TestVet/4\n"} +{"Action":"output","Test":"TestVet/4","Output":"=== RUN TestVet/4\n","OutputType":"frame"} {"Action":"run","Test":"TestTags/x_testtag_y"} -{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== RUN TestTags/x_testtag_y\n"} -{"Action":"output","Test":"TestVet/4","Output":"=== PAUSE TestVet/4\n"} +{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== RUN TestTags/x_testtag_y\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet/4","Output":"=== PAUSE TestVet/4\n","OutputType":"frame"} {"Action":"pause","Test":"TestVet/4"} {"Action":"run","Test":"TestVet/5"} -{"Action":"output","Test":"TestVet/5","Output":"=== RUN TestVet/5\n"} -{"Action":"output","Test":"TestVet/5","Output":"=== PAUSE TestVet/5\n"} +{"Action":"output","Test":"TestVet/5","Output":"=== RUN TestVet/5\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet/5","Output":"=== PAUSE TestVet/5\n","OutputType":"frame"} {"Action":"pause","Test":"TestVet/5"} -{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== PAUSE TestTags/x_testtag_y\n"} +{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== PAUSE TestTags/x_testtag_y\n","OutputType":"frame"} {"Action":"pause","Test":"TestTags/x_testtag_y"} {"Action":"run","Test":"TestVet/6"} -{"Action":"output","Test":"TestVet/6","Output":"=== RUN TestVet/6\n"} +{"Action":"output","Test":"TestVet/6","Output":"=== RUN TestVet/6\n","OutputType":"frame"} {"Action":"run","Test":"TestTags/x,testtag,y"} -{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== RUN TestTags/x,testtag,y\n"} -{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== PAUSE TestTags/x,testtag,y\n"} +{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== RUN TestTags/x,testtag,y\n","OutputType":"frame"} +{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== PAUSE TestTags/x,testtag,y\n","OutputType":"frame"} {"Action":"pause","Test":"TestTags/x,testtag,y"} {"Action":"run","Test":"TestVetDirs/testingpkg"} -{"Action":"output","Test":"TestVetDirs/testingpkg","Output":"=== RUN TestVetDirs/testingpkg\n"} -{"Action":"output","Test":"TestVet/6","Output":"=== PAUSE TestVet/6\n"} +{"Action":"output","Test":"TestVetDirs/testingpkg","Output":"=== RUN TestVetDirs/testingpkg\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet/6","Output":"=== PAUSE TestVet/6\n","OutputType":"frame"} {"Action":"pause","Test":"TestVet/6"} {"Action":"cont","Test":"TestTags/x,testtag,y"} -{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== CONT TestTags/x,testtag,y\n"} -{"Action":"output","Test":"TestVetDirs/testingpkg","Output":"=== PAUSE TestVetDirs/testingpkg\n"} +{"Action":"output","Test":"TestTags/x,testtag,y","Output":"=== CONT TestTags/x,testtag,y\n","OutputType":"frame"} +{"Action":"output","Test":"TestVetDirs/testingpkg","Output":"=== PAUSE TestVetDirs/testingpkg\n","OutputType":"frame"} {"Action":"pause","Test":"TestVetDirs/testingpkg"} {"Action":"run","Test":"TestVetDirs/divergent"} -{"Action":"output","Test":"TestVetDirs/divergent","Output":"=== RUN TestVetDirs/divergent\n"} +{"Action":"output","Test":"TestVetDirs/divergent","Output":"=== RUN TestVetDirs/divergent\n","OutputType":"frame"} {"Action":"run","Test":"TestVet/7"} -{"Action":"output","Test":"TestVet/7","Output":"=== RUN TestVet/7\n"} -{"Action":"output","Test":"TestVet/7","Output":"=== PAUSE TestVet/7\n"} +{"Action":"output","Test":"TestVet/7","Output":"=== RUN TestVet/7\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet/7","Output":"=== PAUSE TestVet/7\n","OutputType":"frame"} {"Action":"pause","Test":"TestVet/7"} -{"Action":"output","Test":"TestVetDirs/divergent","Output":"=== PAUSE TestVetDirs/divergent\n"} +{"Action":"output","Test":"TestVetDirs/divergent","Output":"=== PAUSE TestVetDirs/divergent\n","OutputType":"frame"} {"Action":"pause","Test":"TestVetDirs/divergent"} {"Action":"cont","Test":"TestTags/x_testtag_y"} -{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== CONT TestTags/x_testtag_y\n"} +{"Action":"output","Test":"TestTags/x_testtag_y","Output":"=== CONT TestTags/x_testtag_y\n","OutputType":"frame"} {"Action":"cont","Test":"TestTags/testtag"} -{"Action":"output","Test":"TestTags/testtag","Output":"=== CONT TestTags/testtag\n"} +{"Action":"output","Test":"TestTags/testtag","Output":"=== CONT TestTags/testtag\n","OutputType":"frame"} {"Action":"run","Test":"TestVetDirs/buildtag"} -{"Action":"output","Test":"TestVetDirs/buildtag","Output":"=== RUN TestVetDirs/buildtag\n"} -{"Action":"output","Test":"TestVetDirs/buildtag","Output":"=== PAUSE TestVetDirs/buildtag\n"} +{"Action":"output","Test":"TestVetDirs/buildtag","Output":"=== RUN TestVetDirs/buildtag\n","OutputType":"frame"} +{"Action":"output","Test":"TestVetDirs/buildtag","Output":"=== PAUSE TestVetDirs/buildtag\n","OutputType":"frame"} {"Action":"pause","Test":"TestVetDirs/buildtag"} {"Action":"cont","Test":"TestVet/0"} -{"Action":"output","Test":"TestVet/0","Output":"=== CONT TestVet/0\n"} +{"Action":"output","Test":"TestVet/0","Output":"=== CONT TestVet/0\n","OutputType":"frame"} {"Action":"cont","Test":"TestVet/4"} -{"Action":"output","Test":"TestVet/4","Output":"=== CONT TestVet/4\n"} +{"Action":"output","Test":"TestVet/4","Output":"=== CONT TestVet/4\n","OutputType":"frame"} {"Action":"run","Test":"TestVetDirs/incomplete"} -{"Action":"output","Test":"TestVetDirs/incomplete","Output":"=== RUN TestVetDirs/incomplete\n"} -{"Action":"output","Test":"TestVetDirs/incomplete","Output":"=== PAUSE TestVetDirs/incomplete\n"} +{"Action":"output","Test":"TestVetDirs/incomplete","Output":"=== RUN TestVetDirs/incomplete\n","OutputType":"frame"} +{"Action":"output","Test":"TestVetDirs/incomplete","Output":"=== PAUSE TestVetDirs/incomplete\n","OutputType":"frame"} {"Action":"pause","Test":"TestVetDirs/incomplete"} {"Action":"run","Test":"TestVetDirs/cgo"} -{"Action":"output","Test":"TestVetDirs/cgo","Output":"=== RUN TestVetDirs/cgo\n"} -{"Action":"output","Test":"TestVetDirs/cgo","Output":"=== PAUSE TestVetDirs/cgo\n"} +{"Action":"output","Test":"TestVetDirs/cgo","Output":"=== RUN TestVetDirs/cgo\n","OutputType":"frame"} +{"Action":"output","Test":"TestVetDirs/cgo","Output":"=== PAUSE TestVetDirs/cgo\n","OutputType":"frame"} {"Action":"pause","Test":"TestVetDirs/cgo"} {"Action":"cont","Test":"TestVet/7"} -{"Action":"output","Test":"TestVet/7","Output":"=== CONT TestVet/7\n"} +{"Action":"output","Test":"TestVet/7","Output":"=== CONT TestVet/7\n","OutputType":"frame"} {"Action":"cont","Test":"TestVet/6"} -{"Action":"output","Test":"TestVet/6","Output":"=== CONT TestVet/6\n"} -{"Action":"output","Test":"TestVetVerbose","Output":"--- PASS: TestVetVerbose (0.04s)\n"} +{"Action":"output","Test":"TestVet/6","Output":"=== CONT TestVet/6\n","OutputType":"frame"} +{"Action":"output","Test":"TestVetVerbose","Output":"--- PASS: TestVetVerbose (0.04s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestVetVerbose"} {"Action":"cont","Test":"TestVet/5"} -{"Action":"output","Test":"TestVet/5","Output":"=== CONT TestVet/5\n"} +{"Action":"output","Test":"TestVet/5","Output":"=== CONT TestVet/5\n","OutputType":"frame"} {"Action":"cont","Test":"TestVet/3"} -{"Action":"output","Test":"TestVet/3","Output":"=== CONT TestVet/3\n"} +{"Action":"output","Test":"TestVet/3","Output":"=== CONT TestVet/3\n","OutputType":"frame"} {"Action":"cont","Test":"TestVet/2"} -{"Action":"output","Test":"TestVet/2","Output":"=== CONT TestVet/2\n"} -{"Action":"output","Test":"TestTags","Output":"--- PASS: TestTags (0.00s)\n"} -{"Action":"output","Test":"TestTags/x_testtag_y","Output":" --- PASS: TestTags/x_testtag_y (0.04s)\n"} +{"Action":"output","Test":"TestVet/2","Output":"=== CONT TestVet/2\n","OutputType":"frame"} +{"Action":"output","Test":"TestTags","Output":"--- PASS: TestTags (0.00s)\n","OutputType":"frame"} +{"Action":"output","Test":"TestTags/x_testtag_y","Output":" --- PASS: TestTags/x_testtag_y (0.04s)\n","OutputType":"frame"} {"Action":"output","Test":"TestTags/x_testtag_y","Output":" vet_test.go:187: -tags=x testtag y\n"} {"Action":"pass","Test":"TestTags/x_testtag_y"} -{"Action":"output","Test":"TestTags/x,testtag,y","Output":" --- PASS: TestTags/x,testtag,y (0.04s)\n"} +{"Action":"output","Test":"TestTags/x,testtag,y","Output":" --- PASS: TestTags/x,testtag,y (0.04s)\n","OutputType":"frame"} {"Action":"output","Test":"TestTags/x,testtag,y","Output":" vet_test.go:187: -tags=x,testtag,y\n"} {"Action":"pass","Test":"TestTags/x,testtag,y"} -{"Action":"output","Test":"TestTags/testtag","Output":" --- PASS: TestTags/testtag (0.04s)\n"} +{"Action":"output","Test":"TestTags/testtag","Output":" --- PASS: TestTags/testtag (0.04s)\n","OutputType":"frame"} {"Action":"output","Test":"TestTags/testtag","Output":" vet_test.go:187: -tags=testtag\n"} {"Action":"pass","Test":"TestTags/testtag"} {"Action":"pass","Test":"TestTags"} {"Action":"cont","Test":"TestVet/1"} -{"Action":"output","Test":"TestVet/1","Output":"=== CONT TestVet/1\n"} +{"Action":"output","Test":"TestVet/1","Output":"=== CONT TestVet/1\n","OutputType":"frame"} {"Action":"cont","Test":"TestVetDirs/testingpkg"} -{"Action":"output","Test":"TestVetDirs/testingpkg","Output":"=== CONT TestVetDirs/testingpkg\n"} +{"Action":"output","Test":"TestVetDirs/testingpkg","Output":"=== CONT TestVetDirs/testingpkg\n","OutputType":"frame"} {"Action":"cont","Test":"TestVetDirs/buildtag"} -{"Action":"output","Test":"TestVetDirs/buildtag","Output":"=== CONT TestVetDirs/buildtag\n"} +{"Action":"output","Test":"TestVetDirs/buildtag","Output":"=== CONT TestVetDirs/buildtag\n","OutputType":"frame"} {"Action":"cont","Test":"TestVetDirs/divergent"} -{"Action":"output","Test":"TestVetDirs/divergent","Output":"=== CONT TestVetDirs/divergent\n"} +{"Action":"output","Test":"TestVetDirs/divergent","Output":"=== CONT TestVetDirs/divergent\n","OutputType":"frame"} {"Action":"cont","Test":"TestVetDirs/incomplete"} -{"Action":"output","Test":"TestVetDirs/incomplete","Output":"=== CONT TestVetDirs/incomplete\n"} +{"Action":"output","Test":"TestVetDirs/incomplete","Output":"=== CONT TestVetDirs/incomplete\n","OutputType":"frame"} {"Action":"cont","Test":"TestVetDirs/cgo"} -{"Action":"output","Test":"TestVetDirs/cgo","Output":"=== CONT TestVetDirs/cgo\n"} -{"Action":"output","Test":"TestVet","Output":"--- PASS: TestVet (0.39s)\n"} -{"Action":"output","Test":"TestVet/5","Output":" --- PASS: TestVet/5 (0.07s)\n"} +{"Action":"output","Test":"TestVetDirs/cgo","Output":"=== CONT TestVetDirs/cgo\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet","Output":"--- PASS: TestVet (0.39s)\n","OutputType":"frame"} +{"Action":"output","Test":"TestVet/5","Output":" --- PASS: TestVet/5 (0.07s)\n","OutputType":"frame"} {"Action":"output","Test":"TestVet/5","Output":" vet_test.go:114: files: [\"testdata/copylock_func.go\" \"testdata/rangeloop.go\"]\n"} {"Action":"pass","Test":"TestVet/5"} -{"Action":"output","Test":"TestVet/3","Output":" --- PASS: TestVet/3 (0.07s)\n"} +{"Action":"output","Test":"TestVet/3","Output":" --- PASS: TestVet/3 (0.07s)\n","OutputType":"frame"} {"Action":"output","Test":"TestVet/3","Output":" vet_test.go:114: files: [\"testdata/composite.go\" \"testdata/nilfunc.go\"]\n"} {"Action":"pass","Test":"TestVet/3"} -{"Action":"output","Test":"TestVet/6","Output":" --- PASS: TestVet/6 (0.07s)\n"} +{"Action":"output","Test":"TestVet/6","Output":" --- PASS: TestVet/6 (0.07s)\n","OutputType":"frame"} {"Action":"output","Test":"TestVet/6","Output":" vet_test.go:114: files: [\"testdata/copylock_range.go\" \"testdata/shadow.go\"]\n"} {"Action":"pass","Test":"TestVet/6"} -{"Action":"output","Test":"TestVet/2","Output":" --- PASS: TestVet/2 (0.07s)\n"} +{"Action":"output","Test":"TestVet/2","Output":" --- PASS: TestVet/2 (0.07s)\n","OutputType":"frame"} {"Action":"output","Test":"TestVet/2","Output":" vet_test.go:114: files: [\"testdata/bool.go\" \"testdata/method.go\" \"testdata/unused.go\"]\n"} {"Action":"pass","Test":"TestVet/2"} -{"Action":"output","Test":"TestVet/0","Output":" --- PASS: TestVet/0 (0.13s)\n"} +{"Action":"output","Test":"TestVet/0","Output":" --- PASS: TestVet/0 (0.13s)\n","OutputType":"frame"} {"Action":"output","Test":"TestVet/0","Output":" vet_test.go:114: files: [\"testdata/assign.go\" \"testdata/httpresponse.go\" \"testdata/structtag.go\"]\n"} {"Action":"pass","Test":"TestVet/0"} -{"Action":"output","Test":"TestVet/4","Output":" --- PASS: TestVet/4 (0.16s)\n"} +{"Action":"output","Test":"TestVet/4","Output":" --- PASS: TestVet/4 (0.16s)\n","OutputType":"frame"} {"Action":"output","Test":"TestVet/4","Output":" vet_test.go:114: files: [\"testdata/copylock.go\" \"testdata/print.go\"]\n"} {"Action":"pass","Test":"TestVet/4"} -{"Action":"output","Test":"TestVet/1","Output":" --- PASS: TestVet/1 (0.07s)\n"} +{"Action":"output","Test":"TestVet/1","Output":" --- PASS: TestVet/1 (0.07s)\n","OutputType":"frame"} {"Action":"output","Test":"TestVet/1","Output":" vet_test.go:114: files: [\"testdata/atomic.go\" \"testdata/lostcancel.go\" \"testdata/unsafeptr.go\"]\n"} {"Action":"pass","Test":"TestVet/1"} -{"Action":"output","Test":"TestVet/7","Output":" --- PASS: TestVet/7 (0.19s)\n"} +{"Action":"output","Test":"TestVet/7","Output":" --- PASS: TestVet/7 (0.19s)\n","OutputType":"frame"} {"Action":"output","Test":"TestVet/7","Output":" vet_test.go:114: files: [\"testdata/deadcode.go\" \"testdata/shift.go\"]\n"} {"Action":"pass","Test":"TestVet/7"} {"Action":"pass","Test":"TestVet"} -{"Action":"output","Test":"TestVetDirs","Output":"--- PASS: TestVetDirs (0.01s)\n"} -{"Action":"output","Test":"TestVetDirs/testingpkg","Output":" --- PASS: TestVetDirs/testingpkg (0.06s)\n"} +{"Action":"output","Test":"TestVetDirs","Output":"--- PASS: TestVetDirs (0.01s)\n","OutputType":"frame"} +{"Action":"output","Test":"TestVetDirs/testingpkg","Output":" --- PASS: TestVetDirs/testingpkg (0.06s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestVetDirs/testingpkg"} -{"Action":"output","Test":"TestVetDirs/divergent","Output":" --- PASS: TestVetDirs/divergent (0.05s)\n"} +{"Action":"output","Test":"TestVetDirs/divergent","Output":" --- PASS: TestVetDirs/divergent (0.05s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestVetDirs/divergent"} -{"Action":"output","Test":"TestVetDirs/buildtag","Output":" --- PASS: TestVetDirs/buildtag (0.06s)\n"} +{"Action":"output","Test":"TestVetDirs/buildtag","Output":" --- PASS: TestVetDirs/buildtag (0.06s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestVetDirs/buildtag"} -{"Action":"output","Test":"TestVetDirs/incomplete","Output":" --- PASS: TestVetDirs/incomplete (0.05s)\n"} +{"Action":"output","Test":"TestVetDirs/incomplete","Output":" --- PASS: TestVetDirs/incomplete (0.05s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestVetDirs/incomplete"} -{"Action":"output","Test":"TestVetDirs/cgo","Output":" --- PASS: TestVetDirs/cgo (0.04s)\n"} +{"Action":"output","Test":"TestVetDirs/cgo","Output":" --- PASS: TestVetDirs/cgo (0.04s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestVetDirs/cgo"} {"Action":"pass","Test":"TestVetDirs"} -{"Action":"output","Test":"TestVetAsm","Output":"--- PASS: TestVetAsm (0.75s)\n"} +{"Action":"output","Test":"TestVetAsm","Output":"--- PASS: TestVetAsm (0.75s)\n","OutputType":"frame"} {"Action":"pass","Test":"TestVetAsm"} -{"Action":"output","Output":"PASS\n"} +{"Action":"output","Output":"PASS\n","OutputType":"frame"} {"Action":"output","Output":"ok \tcmd/vet\t(cached)\n"} {"Action":"pass"} diff --git a/src/cmd/internal/testdir/testdir_test.go b/src/cmd/internal/testdir/testdir_test.go index c5aa91ba4732e7..56842845a1d05e 100644 --- a/src/cmd/internal/testdir/testdir_test.go +++ b/src/cmd/internal/testdir/testdir_test.go @@ -52,7 +52,11 @@ var ( // the linux-amd64 builder that's already very fast, so we get more // test coverage on trybots. See https://go.dev/issue/34297. func defaultAllCodeGen() bool { - return testenv.Builder() == "gotip-linux-amd64" + // Note: Checking with HasPrefix allows us to enable -all_codegen + // on builders with experimental features like `gotip-linux-amd64-simd` + // + // See issue #79899. + return strings.HasPrefix(testenv.Builder(), "gotip-linux-amd64") } var ( @@ -67,7 +71,7 @@ var ( // dirs are the directories to look for *.go files in. // TODO(bradfitz): just use all directories? - dirs = []string{".", "ken", "chan", "interface", "internal/runtime/sys", "syntax", "dwarf", "fixedbugs", "codegen", "abi", "typeparam", "typeparam/mdempsky", "arenas"} + dirs = []string{".", "ken", "chan", "interface", "internal/runtime/sys", "syntax", "dwarf", "fixedbugs", "codegen", "abi", "typeparam", "typeparam/mdempsky", "arenas", "simd"} ) // Test is the main entrypoint that runs tests in the GOROOT/test directory. @@ -366,6 +370,7 @@ func goDirPackages(t *testing.T, dir string, singlefilepkgs bool) []*goDirPkg { type context struct { GOOS string GOARCH string + allGOARCH bool cgoEnabled bool noOptEnv bool } @@ -376,16 +381,31 @@ func shouldTest(src string, goos, goarch string) (ok bool, whyNot string) { if *runSkips { return true, "" } + + allGOARCH := false for _, line := range strings.Split(src, "\n") { if strings.HasPrefix(line, "package ") { break } + if *allCodegen && strings.TrimSpace(strings.TrimPrefix(line, "//")) == "asmcheck" { + // For asmcheck tests run under -all_codegen, treat all GOARCH build tags as satisied. + // These tests only verify generated assembly and can be cross-compiled, so they + // should not be skipped just because the host GOARCH doesn't match. + // + // For example: previously, test/codegen/simd_arm64.go was skipped on + // CI because the only builder with GOEXPERIMENT=simd was amd64, while the + // test file also requires arm64. + // + // See issue #79899. + allGOARCH = true + } if expr, err := constraint.Parse(line); err == nil { gcFlags := os.Getenv("GO_GCFLAGS") ctxt := &context{ GOOS: goos, GOARCH: goarch, + allGOARCH: allGOARCH, cgoEnabled: cgoEnabled, noOptEnv: strings.Contains(gcFlags, "-N") || strings.Contains(gcFlags, "-l"), } @@ -423,10 +443,19 @@ func (ctxt *context) match(name string) bool { return true } - if name == ctxt.GOOS || name == ctxt.GOARCH || name == "gc" { + if name == ctxt.GOOS || name == "gc" { return true } + if ctxt.allGOARCH { + if _, ok := archVariants[name]; ok { + return ok + } + } else { + if name == ctxt.GOARCH { + return true + } + } if ctxt.noOptEnv && name == "gcflags_noopt" { return true } @@ -696,6 +725,7 @@ func (t test) run() error { // against a set of regexps in comments. ops := t.wantedAsmOpcodes(long) self := runtime.GOOS + "/" + runtime.GOARCH + var lastErr error for _, env := range ops.Envs() { // Only run checks relevant to the current GOOS/GOARCH, // to avoid triggering a cross-compile of the runtime. @@ -733,15 +763,20 @@ func (t test) run() error { var buf bytes.Buffer cmd.Stdout, cmd.Stderr = &buf, &buf if err := cmd.Run(); err != nil { + lastErr = err t.Log(env, "\n", cmd.Stderr) - return err } err := t.asmCheck(buf.String(), long, env, ops[env]) if err != nil { - return err + lastErr = err + t.Log(err) } } + // The error(s) have been logged earlier. Pass up a generic one. + if lastErr != nil { + return errors.New("One or more asmcheck tests failed. Check log for failure details.") + } return nil case "errorcheck": @@ -1357,11 +1392,12 @@ func (test) updateErrors(out, file string) { // That is, it needs the file name prefix followed by a : or a [, // and possibly preceded by a directory name. func matchPrefix(s, prefix string) bool { + s = s[len(filepath.VolumeName(s)):] i := strings.Index(s, ":") if i < 0 { return false } - j := strings.LastIndex(s[:i], "/") + j := strings.LastIndex(s[:i], string(filepath.Separator)) s = s[j+1:] if len(s) <= len(prefix) || s[:len(prefix)] != prefix { return false @@ -1394,10 +1430,11 @@ type wantedError struct { } var ( - errRx = regexp.MustCompile(`// (?:GC_)?ERROR (.*)`) - errAutoRx = regexp.MustCompile(`// (?:GC_)?ERRORAUTO (.*)`) - errQuotesRx = regexp.MustCompile(`"([^"]*)"`) - lineRx = regexp.MustCompile(`LINE(([+-])(\d+))?`) + errRx = regexp.MustCompile(`// (?:GC_)?ERROR (.*)`) + errAutoRx = regexp.MustCompile(`// (?:GC_)?ERRORAUTO (.*)`) + errQuotesRx = regexp.MustCompile(`"([^"]*)"`) + lineRx = regexp.MustCompile(`LINE(([+-])(\d+))?`) + possibleOpcodeRx = regexp.MustCompile(`([A-Z][A-Z]|[IF](32|64))`) // two caps, or a wasm prefix ) func (t test) wantedErrors(file, short string) (errs []wantedError) { @@ -1477,7 +1514,7 @@ var ( // followed by semi-colon, followed by a comma-separated list of opcode checks. // Extraneous spaces are ignored. // - // An example: arm64/v8.1 : -`ADD` , `SUB` + // An example: arm64/v8.1 : -`ADD` `SUB` // "(\w+)" matches "arm64" (architecture name) // "(/[\w.]+)?" matches "v8.1" (architecture version) // "(/\w*)?" doesn't match anything here (it's an optional part of the triplet) @@ -1485,10 +1522,10 @@ var ( // "(" starts a capturing group // first reMatchCheck matches "-`ADD`" // `(?:" starts a non-capturing group - // "\s*,\s*` matches " , " + // "[\s,]+" matches " " // second reMatchCheck matches "`SUB`" - // ")*)" closes started groups; "*" means that there might be other elements in the comma-separated list - rxAsmPlatform = regexp.MustCompile(`(\w+)(/[\w.]+)?(/\w*)?\s*:\s*(` + reMatchCheck + `(?:\s*,\s*` + reMatchCheck + `)*)`) + // ")*)" closes started groups; "*" means that there might be other elements in the space-separated list + rxAsmPlatform = regexp.MustCompile(`(\w+)(/[\w.]+)?(/\w*)?\s*:\s*(` + reMatchCheck + `(?:[\s,]+` + reMatchCheck + `)*)`) // Regexp to extract a single opcoded check rxAsmCheck = regexp.MustCompile(reMatchCheck) @@ -1582,9 +1619,10 @@ func (t test) wantedAsmOpcodes(fn string) asmChecks { // Parse and extract any architecture check from comments, // made by one architecture name and multiple checks. lnum := fn + ":" + strconv.Itoa(i+1) + lastUsed := 0 for _, ac := range rxAsmPlatform.FindAllStringSubmatch(comment, -1) { archspec, allchecks := ac[1:4], ac[4] - + lastUsed = strings.LastIndex(comment, allchecks) + len(allchecks) var arch, subarch, os string switch { case archspec[2] != "": // 3 components: "linux/386/sse2" @@ -1670,6 +1708,22 @@ func (t test) wantedAsmOpcodes(fn string) asmChecks { } } } + if lastUsed > 0 { + // There was an asm spec in this comment. Check for possible syntax + // errors, which would leave some asm patterns unused. We want + // to allow some tail, for example for English comments. The + // heuristic we use here is we look for two consecutive capital + // letters (or a wasm prefix). Those are probably assembly mnemonics + // that weren't used. + tail := comment[lastUsed:] + if possibleOpcodeRx.MatchString(tail) { + t.Errorf("%s:%d: possible unused assembly pattern: %v", t.goFileName(), i+1, tail) + } else if strings.Count(comment, "\"")%2 != 0 || strings.Count(comment, "`")%2 != 0 { + t.Errorf("%s:%d: unbalanced quotes: %v", t.goFileName(), i+1, comment) + } else if strings.Contains(comment, "\",") || strings.Contains(comment, "`,") { + t.Errorf("%s:%d: comma separator - use space instead: %v", t.goFileName(), i+1, comment) + } + } comment = "" } @@ -1701,6 +1755,9 @@ func (t test) asmCheck(outStr string, fn string, env buildEnv, fullops map[strin } srcFileLine, asm := matches[1], matches[2] + // Replace tabs with single spaces to make matches easier to write. + asm = strings.ReplaceAll(asm, "\t", " ") + // Associate the original file/line information to the current // function in the output; it will be useful to dump it in case // of error. @@ -1752,11 +1809,11 @@ func (t test) asmCheck(outStr string, fn string, env buildEnv, fullops map[strin } if o.negative { - fmt.Fprintf(&errbuf, "%s:%d: %s: wrong opcode found: %q\n", t.goFileName(), o.line, env, o.opcode.String()) + fmt.Fprintf(&errbuf, "%s:%d: %s: wrong opcode found: %#q\n", t.goFileName(), o.line, env, o.opcode.String()) } else if o.expected > 0 { - fmt.Fprintf(&errbuf, "%s:%d: %s: wrong number of opcodes: %q\n", t.goFileName(), o.line, env, o.opcode.String()) + fmt.Fprintf(&errbuf, "%s:%d: %s: wrong number of opcodes: %#q\n", t.goFileName(), o.line, env, o.opcode.String()) } else { - fmt.Fprintf(&errbuf, "%s:%d: %s: opcode not found: %q\n", t.goFileName(), o.line, env, o.opcode.String()) + fmt.Fprintf(&errbuf, "%s:%d: %s: opcode not found: %#q\n", t.goFileName(), o.line, env, o.opcode.String()) } } return errors.New(errbuf.String()) diff --git a/src/cmd/link/cgo_test.go b/src/cmd/link/cgo_test.go index 52db70e1ad8d4c..a684edd5f3b7d5 100644 --- a/src/cmd/link/cgo_test.go +++ b/src/cmd/link/cgo_test.go @@ -115,10 +115,10 @@ func testCGOLTO(t *testing.T, cc, cgoCflags string, test int) { t.Fatalf("bad case %d", test) } - cmd := testenv.Command(t, testenv.GoToolPath(t), "build") + cmd := goCmd(t, "build") cmd.Dir = dir cgoCflags += " -flto" - cmd.Env = append(cmd.Environ(), "CGO_CFLAGS="+cgoCflags) + cmd.Env = append(cmd.Env, "CGO_CFLAGS="+cgoCflags) t.Logf("CGO_CFLAGS=%q %v", cgoCflags, cmd) out, err := cmd.CombinedOutput() diff --git a/src/cmd/link/dwarf_test.go b/src/cmd/link/dwarf_test.go index 56a076002a92d4..2ed684c92f2f97 100644 --- a/src/cmd/link/dwarf_test.go +++ b/src/cmd/link/dwarf_test.go @@ -21,56 +21,6 @@ import ( "testing" ) -// TestMain allows this test binary to run as a -toolexec wrapper for -// the 'go' command. If LINK_TEST_TOOLEXEC is set, TestMain runs the -// binary as if it were cmd/link, and otherwise runs the requested -// tool as a subprocess. -// -// This allows the test to verify the behavior of the current contents of the -// cmd/link package even if the installed cmd/link binary is stale. -func TestMain(m *testing.M) { - // Are we running as a toolexec wrapper? If so then run either - // the correct tool or this executable itself (for the linker). - // Running as toolexec wrapper. - if os.Getenv("LINK_TEST_TOOLEXEC") != "" { - if strings.TrimSuffix(filepath.Base(os.Args[1]), ".exe") == "link" { - // Running as a -toolexec linker, and the tool is cmd/link. - // Substitute this test binary for the linker. - os.Args = os.Args[1:] - main() - os.Exit(0) - } - // Running some other tool. - cmd := exec.Command(os.Args[1], os.Args[2:]...) - cmd.Stdin = os.Stdin - cmd.Stdout = os.Stdout - cmd.Stderr = os.Stderr - if err := cmd.Run(); err != nil { - os.Exit(1) - } - os.Exit(0) - } - - // Are we being asked to run as the linker (without toolexec)? - // If so then kick off main. - if os.Getenv("LINK_TEST_EXEC_LINKER") != "" { - main() - os.Exit(0) - } - - if testExe, err := os.Executable(); err == nil { - // on wasm, some phones, we expect an error from os.Executable() - testLinker = testExe - } - - // Not running as a -toolexec wrapper or as a linker executable. - // Just run the tests. - os.Exit(m.Run()) -} - -// Path of the test executable being run. -var testLinker string - func testDWARF(t *testing.T, buildmode string, expectDWARF bool, env ...string) { testenv.MustHaveCGO(t) testenv.MustHaveGoBuild(t) @@ -82,7 +32,6 @@ func testDWARF(t *testing.T, buildmode string, expectDWARF bool, env ...string) t.Parallel() for _, prog := range []string{"testprog", "testprogcgo"} { - prog := prog expectDWARF := expectDWARF if runtime.GOOS == "aix" && prog == "testprogcgo" { extld := os.Getenv("CC") @@ -106,14 +55,13 @@ func testDWARF(t *testing.T, buildmode string, expectDWARF bool, env ...string) exe := filepath.Join(tmpDir, prog+".exe") dir := "../../runtime/testdata/" + prog - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-toolexec", os.Args[0], "-o", exe) + cmd := goCmd(t, "build", "-o", exe) if buildmode != "" { cmd.Args = append(cmd.Args, "-buildmode", buildmode) } cmd.Args = append(cmd.Args, dir) - cmd.Env = append(os.Environ(), env...) + cmd.Env = append(cmd.Env, env...) cmd.Env = append(cmd.Env, "CGO_CFLAGS=") // ensure CGO_CFLAGS does not contain any flags. Issue #35459 - cmd.Env = append(cmd.Env, "LINK_TEST_TOOLEXEC=1") out, err := cmd.CombinedOutput() if err != nil { t.Fatalf("go build -o %v %v: %v\n%s", exe, dir, err, out) @@ -207,10 +155,102 @@ func testDWARF(t *testing.T, buildmode string, expectDWARF bool, env ...string) if !strings.HasSuffix(line.File.Name, wantFile) || line.Line != wantLine { t.Errorf("%#x is %s:%d, want %s:%d", addr, line.File.Name, line.Line, filepath.Join("...", wantFile), wantLine) } + + if buildmode != "c-archive" { + testModuledata(t, d) + } }) } } +// testModuledata makes sure that runtime.firstmoduledata exists +// and has a type. Issue #76731. +func testModuledata(t *testing.T, d *dwarf.Data) { + const symName = "runtime.firstmoduledata" + + r := d.Reader() + for { + e, err := r.Next() + if err != nil { + t.Error(err) + return + } + if e == nil { + t.Errorf("did not find DWARF entry for %s", symName) + return + } + + switch e.Tag { + case dwarf.TagVariable: + // carry on after switch + case dwarf.TagCompileUnit, dwarf.TagSubprogram: + continue + default: + r.SkipChildren() + continue + } + + nameIdx, typeIdx := -1, -1 + for i := range e.Field { + f := &e.Field[i] + switch f.Attr { + case dwarf.AttrName: + nameIdx = i + case dwarf.AttrType: + typeIdx = i + } + } + if nameIdx == -1 { + // unnamed variable? + r.SkipChildren() + continue + } + nameStr, ok := e.Field[nameIdx].Val.(string) + if !ok { + // variable name is not a string? + r.SkipChildren() + continue + } + if nameStr != symName { + r.SkipChildren() + continue + } + + if typeIdx == -1 { + t.Errorf("%s has no DWARF type", symName) + return + } + off, ok := e.Field[typeIdx].Val.(dwarf.Offset) + if !ok { + t.Errorf("unexpected Go type %T for DWARF type for %s; expected %T", e.Field[typeIdx].Val, symName, dwarf.Offset(0)) + return + } + + typeInfo, err := d.Type(off) + if err != nil { + t.Error(err) + return + } + + typeName := typeInfo.Common().Name + if want := "runtime.moduledata"; typeName != want { + t.Errorf("type of %s is %s, expected %s", symName, typeName, want) + } + for { + typedef, ok := typeInfo.(*dwarf.TypedefType) + if !ok { + break + } + typeInfo = typedef.Type + } + if _, ok := typeInfo.(*dwarf.StructType); !ok { + t.Errorf("type of %s is %T, expected %T", symName, typeInfo, dwarf.StructType{}) + } + + return + } +} + func TestDWARF(t *testing.T) { testDWARF(t, "", true) if !testing.Short() { @@ -282,9 +322,8 @@ func TestDWARFLocationList(t *testing.T) { exe := filepath.Join(tmpDir, "issue65405.exe") dir := "./testdata/dwarf/issue65405" - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-toolexec", os.Args[0], "-gcflags=all=-N -l", "-o", exe, dir) - cmd.Env = append(os.Environ(), "CGO_CFLAGS=") - cmd.Env = append(cmd.Env, "LINK_TEST_TOOLEXEC=1") + cmd := goCmd(t, "build", "-gcflags=all=-N -l", "-o", exe, dir) + cmd.Env = append(cmd.Env, "CGO_CFLAGS=") out, err := cmd.CombinedOutput() if err != nil { t.Fatalf("go build -o %v %v: %v\n%s", exe, dir, err, out) @@ -386,7 +425,7 @@ func TestFlagW(t *testing.T) { {"-s", false}, // -s implies -w {"-s -w=0", true}, // -w=0 negates the implied -w } - if testenv.HasCGO() && runtime.GOOS != "solaris" { // Solaris linker doesn't support the -S flag + if testenv.HasCGO() && runtime.GOOS != "solaris" && runtime.GOOS != "illumos" { // Solaris linker doesn't support the -S flag tests = append(tests, testCase{"-w -linkmode=external", false}, testCase{"-s -linkmode=external", false}, @@ -402,7 +441,7 @@ func TestFlagW(t *testing.T) { t.Run(name, func(t *testing.T) { ldflags := "-ldflags=" + test.flag exe := filepath.Join(t.TempDir(), "a.exe") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", ldflags, "-o", exe, src) + cmd := goCmd(t, "build", ldflags, "-o", exe, src) out, err := cmd.CombinedOutput() if err != nil { t.Fatalf("build failed: %v\n%s", err, out) diff --git a/src/cmd/link/elf_test.go b/src/cmd/link/elf_test.go index dc52c091f65d17..9b06d71cda2887 100644 --- a/src/cmd/link/elf_test.go +++ b/src/cmd/link/elf_test.go @@ -2,7 +2,7 @@ // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. -//go:build dragonfly || freebsd || linux || netbsd || openbsd +//go:build dragonfly || freebsd || linux || netbsd || openbsd || solaris package main @@ -11,6 +11,7 @@ import ( "cmd/internal/hash" "cmd/link/internal/ld" "debug/elf" + "encoding/binary" "fmt" "internal/platform" "internal/testenv" @@ -22,6 +23,7 @@ import ( "sync" "testing" "text/template" + "unsafe" ) func getCCAndCCFLAGS(t *testing.T, env []string) (string, []string) { @@ -80,7 +82,8 @@ func TestSectionsWithSameName(t *testing.T) { dir := t.TempDir() gopath := filepath.Join(dir, "GOPATH") - env := append(os.Environ(), "GOPATH="+gopath) + gopathEnv := "GOPATH=" + gopath + env := append(os.Environ(), gopathEnv) if err := os.WriteFile(filepath.Join(dir, "go.mod"), []byte("module elf_test\n"), 0666); err != nil { t.Fatal(err) @@ -91,7 +94,6 @@ func TestSectionsWithSameName(t *testing.T) { t.Fatal(err) } - goTool := testenv.GoToolPath(t) cc, cflags := getCCAndCCFLAGS(t, env) asmObj := filepath.Join(dir, "x.o") @@ -119,10 +121,10 @@ func TestSectionsWithSameName(t *testing.T) { t.Fatal(err) } - cmd := testenv.Command(t, goTool, "build") + cmd := goCmd(t, "build") cmd.Dir = dir - cmd.Env = env - t.Logf("%s build", goTool) + cmd.Env = append(cmd.Env, gopathEnv) + t.Logf("%s build", testenv.GoToolPath(t)) if out, err := cmd.CombinedOutput(); err != nil { t.Logf("%s", out) t.Fatal(err) @@ -150,13 +152,13 @@ func TestMinusRSymsWithSameName(t *testing.T) { dir := t.TempDir() gopath := filepath.Join(dir, "GOPATH") - env := append(os.Environ(), "GOPATH="+gopath) + gopathEnv := "GOPATH=" + gopath + env := append(os.Environ(), gopathEnv) if err := os.WriteFile(filepath.Join(dir, "go.mod"), []byte("module elf_test\n"), 0666); err != nil { t.Fatal(err) } - goTool := testenv.GoToolPath(t) cc, cflags := getCCAndCCFLAGS(t, env) objs := []string{} @@ -198,10 +200,10 @@ func TestMinusRSymsWithSameName(t *testing.T) { t.Fatal(err) } - t.Logf("%s build", goTool) - cmd := testenv.Command(t, goTool, "build") + t.Logf("%s build", testenv.GoToolPath(t)) + cmd := goCmd(t, "build") cmd.Dir = dir - cmd.Env = env + cmd.Env = append(cmd.Env, gopathEnv) if out, err := cmd.CombinedOutput(); err != nil { t.Logf("%s", out) t.Fatal(err) @@ -243,7 +245,7 @@ func TestGNUBuildID(t *testing.T) { for _, test := range tests { t.Run(test.name, func(t *testing.T) { exe := filepath.Join(tmpdir, test.name) - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-buildid="+gobuildid+" "+test.ldflags, "-o", exe, goFile) + cmd := goCmd(t, "build", "-ldflags=-buildid="+gobuildid+" "+test.ldflags, "-o", exe, goFile) if out, err := cmd.CombinedOutput(); err != nil { t.Fatalf("%v: %v:\n%s", cmd.Args, err, out) } @@ -277,11 +279,9 @@ func TestMergeNoteSections(t *testing.T) { t.Fatal(err) } outFile := filepath.Join(t.TempDir(), "notes.exe") - goTool := testenv.GoToolPath(t) // sha1sum of "gopher" id := "0xf4e8cd51ce8bae2996dc3b74639cdeaa1f7fee5f" - cmd := testenv.Command(t, goTool, "build", "-o", outFile, "-ldflags", - "-B "+id, goFile) + cmd := goCmd(t, "build", "-o", outFile, "-ldflags", "-B "+id, goFile) cmd.Dir = t.TempDir() if out, err := cmd.CombinedOutput(); err != nil { t.Logf("%s", out) @@ -383,7 +383,7 @@ func TestPIESize(t *testing.T) { binpie += linkmode build := func(bin, mode string) error { - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", bin, "-buildmode="+mode, "-ldflags=-linkmode="+linkmode) + cmd := goCmd(t, "build", "-o", bin, "-buildmode="+mode, "-ldflags=-linkmode="+linkmode) cmd.Args = append(cmd.Args, "pie.go") cmd.Dir = dir t.Logf("%v", cmd.Args) @@ -532,8 +532,7 @@ func TestIssue51939(t *testing.T) { t.Fatal(err) } outFile := filepath.Join(td, "issue51939.exe") - goTool := testenv.GoToolPath(t) - cmd := testenv.Command(t, goTool, "build", "-o", outFile, goFile) + cmd := goCmd(t, "build", "-o", outFile, goFile) if out, err := cmd.CombinedOutput(); err != nil { t.Logf("%s", out) t.Fatal(err) @@ -565,7 +564,7 @@ func TestFlagR(t *testing.T) { } exe := filepath.Join(tmpdir, "x.exe") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-R=0x100000", "-o", exe, src) + cmd := goCmd(t, "build", "-ldflags=-R=0x100000", "-o", exe, src) if out, err := cmd.CombinedOutput(); err != nil { t.Fatalf("build failed: %v, output:\n%s", err, out) } @@ -610,7 +609,7 @@ func testFlagD(t *testing.T, dataAddr string, roundQuantum string, expectedAddr ldflags += " -R=" + roundQuantum } - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags="+ldflags, "-o", exe, src) + cmd := goCmd(t, "build", "-ldflags="+ldflags, "-o", exe, src) if out, err := cmd.CombinedOutput(); err != nil { t.Fatalf("build failed: %v, output:\n%s", err, out) } @@ -669,7 +668,7 @@ func testFlagDError(t *testing.T, dataAddr string, roundQuantum string, expected ldflags += " -R=" + roundQuantum } - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags="+ldflags, "-o", exe, src) + cmd := goCmd(t, "build", "-ldflags="+ldflags, "-o", exe, src) out, err := cmd.CombinedOutput() if err == nil { t.Fatalf("expected build to fail with unaligned data address, but it succeeded") @@ -678,3 +677,129 @@ func testFlagDError(t *testing.T, dataAddr string, roundQuantum string, expected t.Errorf("expected error message to contain %q, got:\n%s", expectedError, out) } } + +func TestELFHeadersSorted(t *testing.T) { + for _, buildmode := range []string{"exe", "pie"} { + t.Run(buildmode, func(t *testing.T) { + testELFHeadersSorted(t, buildmode) + }) + } +} + +func testELFHeadersSorted(t *testing.T, buildmode string) { + testenv.MustHaveGoBuild(t) + + // We can only test this for internal linking mode. + // For external linking the external linker will + // decide how to sort the sections. + testenv.MustInternalLink(t, testenv.NoSpecialBuildTypes) + if buildmode == "pie" { + testenv.MustInternalLinkPIE(t) + } + + t.Parallel() + + tmpdir := t.TempDir() + src := filepath.Join(tmpdir, "x.go") + if err := os.WriteFile(src, []byte(goSourceWithData), 0o444); err != nil { + t.Fatal(err) + } + + exe := filepath.Join(tmpdir, "x.exe") + cmd := goCmd(t, "build", "-buildmode="+buildmode, "-ldflags=-linkmode=internal", "-o", exe, src) + if out, err := cmd.CombinedOutput(); err != nil { + t.Fatalf("build failed: %v, output:\n%s", err, out) + } + + // Check that the first section header is all zeroes. + f, err := os.Open(exe) + if err != nil { + t.Fatal(err) + } + defer f.Close() + + var ident [elf.EI_NIDENT]byte + if _, err := f.Read(ident[:]); err != nil { + t.Fatal(err) + } + + var bo binary.ByteOrder + switch elf.Data(ident[elf.EI_DATA]) { + case elf.ELFDATA2LSB: + bo = binary.LittleEndian + case elf.ELFDATA2MSB: + bo = binary.BigEndian + default: + t.Fatalf("unrecognized data encoding %d", ident[elf.EI_DATA]) + } + + var shoff int64 + var shsize int + switch elf.Class(ident[elf.EI_CLASS]) { + case elf.ELFCLASS32: + var hdr elf.Header32 + data := make([]byte, unsafe.Sizeof(hdr)) + if _, err := f.ReadAt(data, 0); err != nil { + t.Fatal(err) + } + shoff = int64(bo.Uint32(data[unsafe.Offsetof(hdr.Shoff):])) + shsize = int(unsafe.Sizeof(elf.Section32{})) + + case elf.ELFCLASS64: + var hdr elf.Header64 + data := make([]byte, unsafe.Sizeof(hdr)) + if _, err := f.ReadAt(data, 0); err != nil { + t.Fatal(err) + } + shoff = int64(bo.Uint64(data[unsafe.Offsetof(hdr.Shoff):])) + shsize = int(unsafe.Sizeof(elf.Section64{})) + + default: + t.Fatalf("unrecognized class %d", ident[elf.EI_CLASS]) + } + + if shoff > 0 { + data := make([]byte, shsize) + if _, err := f.ReadAt(data, shoff); err != nil { + t.Fatal(err) + } + for i, c := range data { + if c != 0 { + t.Errorf("section header 0 byte %d is %d, should be zero", i, c) + } + } + } + + ef, err := elf.NewFile(f) + if err != nil { + t.Fatal(err) + } + defer ef.Close() + + // After the first zero section header, + // we should see allocated sections, + // then unallocated sections. + // The allocated sections should be sorted by address. + i := 1 + lastAddr := uint64(0) + for i < len(ef.Sections) { + sec := ef.Sections[i] + if sec.Flags&elf.SHF_ALLOC == 0 { + break + } + if sec.Addr < lastAddr { + t.Errorf("section %d %q address %#x less than previous address %#x", i, sec.Name, sec.Addr, lastAddr) + } + lastAddr = sec.Addr + i++ + } + + firstUnalc := i + for i < len(ef.Sections) { + sec := ef.Sections[i] + if sec.Flags&elf.SHF_ALLOC != 0 { + t.Errorf("allocated section %d %q follows first unallocated section %d %q", i, sec.Name, firstUnalc, ef.Sections[firstUnalc].Name) + } + i++ + } +} diff --git a/src/cmd/link/internal/amd64/asm.go b/src/cmd/link/internal/amd64/asm.go index d27342f23fb5fb..918c6c12a523d8 100644 --- a/src/cmd/link/internal/amd64/asm.go +++ b/src/cmd/link/internal/amd64/asm.go @@ -164,9 +164,6 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade su := ldr.MakeSymbolUpdater(s) su.SetRelocType(rIdx, objabi.R_ADDR) - if targType == sym.SDYNIMPORT { - ldr.Errorf(s, "unexpected reloc for dynamic symbol %s", ldr.SymName(targ)) - } if target.IsPIE() && target.IsInternal() { // For internal linking PIE, this R_ADDR relocation cannot // be resolved statically. We need to generate a dynamic @@ -179,6 +176,9 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade ldr.Errorf(s, "unsupported relocation for PIE: %v", rt) } } + if targType == sym.SDYNIMPORT { + ldr.Errorf(s, "unexpected reloc for dynamic symbol %s", ldr.SymName(targ)) + } return true case objabi.MachoRelocOffset + ld.MACHO_X86_64_RELOC_SUBTRACTOR*2 + 0: @@ -419,7 +419,13 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade // Mach-O relocations are a royal pain to lay out. // They use a compact stateful bytecode representation. // Here we record what are needed and encode them later. - ld.MachoAddRebase(s, int64(r.Off())) + if targType == sym.SDYNIMPORT { + // Dynamic import: the pointer must be bound by + // the dynamic linker at load time. + ld.MachoAddBind(s, int64(r.Off()), targ) + } else { + ld.MachoAddRebase(s, int64(r.Off())) + } // Not mark r done here. So we still apply it statically, // so in the file content we'll also have the right offset // to the relocation target. So it can be examined statically diff --git a/src/cmd/link/internal/arm64/asm.go b/src/cmd/link/internal/arm64/asm.go index 1f4282adecc747..9864788e1b6125 100644 --- a/src/cmd/link/internal/arm64/asm.go +++ b/src/cmd/link/internal/arm64/asm.go @@ -211,9 +211,6 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade // Handle relocations found in Mach-O object files. case objabi.MachoRelocOffset + ld.MACHO_ARM64_RELOC_UNSIGNED*2: - if targType == sym.SDYNIMPORT { - ldr.Errorf(s, "unexpected reloc for dynamic symbol %s", ldr.SymName(targ)) - } su := ldr.MakeSymbolUpdater(s) su.SetRelocType(rIdx, objabi.R_ADDR) if target.IsPIE() && target.IsInternal() { @@ -222,6 +219,9 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade // relocation. Let the code below handle it. break } + if targType == sym.SDYNIMPORT { + ldr.Errorf(s, "unexpected reloc for dynamic symbol %s", ldr.SymName(targ)) + } return true case objabi.MachoRelocOffset + ld.MACHO_ARM64_RELOC_SUBTRACTOR*2: @@ -469,7 +469,13 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade // Mach-O relocations are a royal pain to lay out. // They use a compact stateful bytecode representation. // Here we record what are needed and encode them later. - ld.MachoAddRebase(s, int64(r.Off())) + if targType == sym.SDYNIMPORT { + // Dynamic import: the pointer must be bound by + // the dynamic linker at load time. + ld.MachoAddBind(s, int64(r.Off()), targ) + } else { + ld.MachoAddRebase(s, int64(r.Off())) + } // Not mark r done here. So we still apply it statically, // so in the file content we'll also have the right offset // to the relocation target. So it can be examined statically @@ -1027,25 +1033,35 @@ func archreloc(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, r loade } case objabi.R_ARM64_PCREL: + // When targetting Windows, the instruction immediate field is cleared + // before applying relocations, as it contains the offset as bytes + // instead of pages. It has already been accounted for in loadpe.Load + // by adjusting r.Add(). if (val>>24)&0x9f == 0x90 { - // R_AARCH64_ADR_PREL_PG_HI21 + // ELF R_AARCH64_ADR_PREL_PG_HI21, or Mach-O ARM64_RELOC_PAGE21, or PE IMAGE_REL_ARM64_PAGEBASE_REL21 // patch instruction: adrp t := ldr.SymAddr(rs) + r.Add() - ((ldr.SymValue(s) + int64(r.Off())) &^ 0xfff) if t >= 1<<32 || t < -1<<32 { ldr.Errorf(s, "program too large, address relocation distance = %d", t) } o0 := (uint32((t>>12)&3) << 29) | (uint32((t>>12>>2)&0x7ffff) << 5) + if target.IsWindows() { + val &^= 3<<29 | 0x7ffff<<5 + } return val | int64(o0), noExtReloc, isOk } else if (val>>24)&0x9f == 0x91 { - // ELF R_AARCH64_ADD_ABS_LO12_NC or Mach-O ARM64_RELOC_PAGEOFF12 + // ELF R_AARCH64_ADD_ABS_LO12_NC, or Mach-O ARM64_RELOC_PAGEOFF12, or PE IMAGE_REL_ARM64_PAGEOFFSET_12A // patch instruction: add t := ldr.SymAddr(rs) + r.Add() - ((ldr.SymValue(s) + int64(r.Off())) &^ 0xfff) o1 := uint32(t&0xfff) << 10 + if target.IsWindows() { + val &^= 0xfff << 10 + } return val | int64(o1), noExtReloc, isOk } else if (val>>24)&0x3b == 0x39 { - // Mach-O ARM64_RELOC_PAGEOFF12 + // Mach-O ARM64_RELOC_PAGEOFF12 or PE IMAGE_REL_ARM64_PAGEOFFSET_12L // patch ldr/str(b/h/w/d/q) (integer or vector) instructions, which have different scaling factors. - // Mach-O uses same relocation type for them. + // Mach-O and PE use same relocation type for them. shift := uint32(val) >> 30 if shift == 0 && (val>>20)&0x048 == 0x048 { // 128-bit vector load shift = 4 @@ -1055,6 +1071,9 @@ func archreloc(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, r loade ldr.Errorf(s, "invalid address: %x for relocation type: ARM64_RELOC_PAGEOFF12", t) } o1 := (uint32(t&0xfff) >> shift) << 10 + if target.IsWindows() { + val &^= 0xfff << 10 + } return val | int64(o1), noExtReloc, isOk } else { ldr.Errorf(s, "unsupported instruction for %x R_ARM64_PCREL", val) @@ -1254,9 +1273,6 @@ func gensymlate(ctxt *ld.Link, ldr *loader.Loader) { // addend. For large symbols, we generate "label" symbols in the middle, so // that relocations can target them with smaller addends. // On Windows, we only get 21 bits, again (presumably) signed. - // Also, on Windows (always) and Darwin (for very large binaries), the external - // linker doesn't support CALL relocations with addend, so we generate "label" - // symbols for functions of which we can target the middle (Duff's devices). if !ctxt.IsDarwin() && !ctxt.IsWindows() || !ctxt.IsExternal() { return } @@ -1268,6 +1284,9 @@ func gensymlate(ctxt *ld.Link, ldr *loader.Loader) { // addLabelSyms adds "label" symbols at s+limit, s+2*limit, etc. addLabelSyms := func(s loader.Sym, limit, sz int64) { + if ldr.SymSect(s) == nil { + log.Fatalf("gensymlate: symbol %s has no section (type=%v)", ldr.SymName(s), ldr.SymType(s)) + } v := ldr.SymValue(s) for off := limit; off < sz; off += limit { p := ldr.LookupOrCreateSym(offsetLabelName(ldr, s, off), ldr.SymVersion(s)) @@ -1285,14 +1304,6 @@ func gensymlate(ctxt *ld.Link, ldr *loader.Loader) { } } - // Generate symbol names for every offset we need in duffcopy/duffzero (only 64 each). - if s := ldr.Lookup("runtime.duffcopy", sym.SymVerABIInternal); s != 0 && ldr.AttrReachable(s) { - addLabelSyms(s, 8, 8*64) - } - if s := ldr.Lookup("runtime.duffzero", sym.SymVerABIInternal); s != 0 && ldr.AttrReachable(s) { - addLabelSyms(s, 4, 4*64) - } - if ctxt.IsDarwin() { big := false for _, seg := range ld.Segments { @@ -1312,13 +1323,16 @@ func gensymlate(ctxt *ld.Link, ldr *loader.Loader) { } t := ldr.SymType(s) if t.IsText() { - // Except for Duff's devices (handled above), we don't - // target the middle of a function. + // We don't target the middle of a function. continue } if t >= sym.SDWARFSECT { continue // no need to add label for DWARF symbols } + if ldr.AttrSpecial(s) || !ldr.TopLevelSym(s) { + // no need to add label for special symbols and non-top-level symbols + continue + } sz := ldr.SymSize(s) if sz <= limit { continue diff --git a/src/cmd/link/internal/ld/config.go b/src/cmd/link/internal/ld/config.go index 802fb35aee4e65..acbebf28598a9c 100644 --- a/src/cmd/link/internal/ld/config.go +++ b/src/cmd/link/internal/ld/config.go @@ -213,15 +213,7 @@ func determineLinkMode(ctxt *Link) { } } - switch ctxt.LinkMode { - case LinkInternal: - if extNeeded { - Exitf("internal linking requested %sbut external linking required: %s", via, extReason) - } - case LinkExternal: - switch { - case buildcfg.GOARCH == "ppc64" && buildcfg.GOOS == "linux": - Exitf("external linking not supported for %s/ppc64", buildcfg.GOOS) - } + if ctxt.LinkMode == LinkInternal && extNeeded { + Exitf("internal linking requested %sbut external linking required: %s", via, extReason) } } diff --git a/src/cmd/link/internal/ld/data.go b/src/cmd/link/internal/ld/data.go index dfb1d7bafbd51d..4a27db5a42ef88 100644 --- a/src/cmd/link/internal/ld/data.go +++ b/src/cmd/link/internal/ld/data.go @@ -913,6 +913,23 @@ func windynrelocsym(ctxt *Link, rel *loader.SymbolBuilder, s loader.Sym) error { rel.AddPCRelPlus(ctxt.Arch, targ, 0) rel.AddUint8(0x90) rel.AddUint8(0x90) + case sys.ARM64: + // adrp x16, addr + rel.AddUint32(ctxt.Arch, 0x90000010) + r, _ := rel.AddRel(objabi.R_ARM64_PCREL) + r.SetOff(int32(rel.Size() - 4)) + r.SetSiz(4) + r.SetSym(targ) + + // ldr x17, [x16, ] + rel.AddUint32(ctxt.Arch, 0xf9400211) + r, _ = rel.AddRel(objabi.R_ARM64_PCREL) + r.SetOff(int32(rel.Size() - 4)) + r.SetSiz(4) + r.SetSym(targ) + + // br x17 + rel.AddUint32(ctxt.Arch, 0xd61f0220) } } else if tplt >= 0 { if su == nil { @@ -1452,6 +1469,8 @@ func checkSectSize(sect *sym.Section) { // fixZeroSizedSymbols gives a few special symbols with zero size some space. func fixZeroSizedSymbols(ctxt *Link) { + ldr := ctxt.loader + // The values in moduledata are filled out by relocations // pointing to the addresses of these special symbols. // Typically these symbols have no size and are not laid @@ -1475,11 +1494,29 @@ func fixZeroSizedSymbols(ctxt *Link) { // aren't real symbols, their alignment might not match the // first symbol alignment. Therefore, there are explicitly put at the // beginning of their section with the same alignment. + + defineRuntimeTypes := func() { + types := ldr.CreateSymForUpdate("runtime.types", 0) + types.SetType(sym.STYPE) + types.SetSize(int64(ctxt.Arch.PtrSize)) + types.SetAlign(int32(ctxt.Arch.PtrSize)) + ldr.SetAttrSpecial(types.Sym(), false) + } + if !(ctxt.DynlinkingGo() && ctxt.HeadType == objabi.Hdarwin) && !(ctxt.HeadType == objabi.Haix && ctxt.LinkMode == LinkExternal) { + + // On AIX, below, we give runtime.types a size. + // That means that the type descriptors will actually + // follow runtime.types plus that size. + // To simplify matters for the runtime, + // always give runtime.types a size. + if ctxt.HeadType == objabi.Haix { + defineRuntimeTypes() + } + return } - ldr := ctxt.loader bss := ldr.CreateSymForUpdate("runtime.bss", 0) bss.SetSize(8) ldr.SetAttrSpecial(bss.Sym(), false) @@ -1513,13 +1550,10 @@ func fixZeroSizedSymbols(ctxt *Link) { enoptrdata := ldr.CreateSymForUpdate("runtime.enoptrdata", 0) ldr.SetAttrSpecial(enoptrdata.Sym(), false) - types := ldr.CreateSymForUpdate("runtime.types", 0) - types.SetType(sym.STYPE) - types.SetSize(8) - ldr.SetAttrSpecial(types.Sym(), false) + defineRuntimeTypes() etypes := ldr.CreateSymForUpdate("runtime.etypes", 0) - etypes.SetType(sym.SFUNCTAB) + etypes.SetType(sym.STYPE) ldr.SetAttrSpecial(etypes.Sym(), false) if ctxt.HeadType == objabi.Haix { @@ -1541,67 +1575,40 @@ func (state *dodataState) makeRelroForSharedLib(target *Link) { // "read only" data with relocations needs to go in its own section // when building a shared library. We do this by boosting objects of - // type SXXX with relocations to type SXXXRELRO. + // type SRODATA with relocations to type SRODATARELRO. ldr := target.loader - for _, symnro := range sym.ReadOnly { - symnrelro := sym.RelROMap[symnro] - - ro := []loader.Sym{} - relro := state.data[symnrelro] - - for _, s := range state.data[symnro] { - relocs := ldr.Relocs(s) - isRelro := relocs.Count() > 0 - switch state.symType(s) { - case sym.STYPE, sym.STYPERELRO, sym.SGOFUNCRELRO: - // Symbols are not sorted yet, so it is possible - // that an Outer symbol has been changed to a - // relro Type before it reaches here. - isRelro = true - case sym.SFUNCTAB: - if ldr.SymName(s) == "runtime.etypes" { - // runtime.etypes must be at the end of - // the relro data. - isRelro = true - } - case sym.SGOFUNC: - // The only SGOFUNC symbols that contain relocations are .stkobj, - // and their relocations are of type objabi.R_ADDROFF, - // which always get resolved during linking. - isRelro = false - } - if isRelro { - if symnrelro == sym.Sxxx { - state.ctxt.Errorf(s, "cannot contain relocations (type %v)", symnro) - } - state.setSymType(s, symnrelro) - if outer := ldr.OuterSym(s); outer != 0 { - state.setSymType(outer, symnrelro) - } - relro = append(relro, s) - } else { - ro = append(ro, s) + ro := []loader.Sym{} + relro := state.data[sym.SRODATARELRO] + for _, s := range state.data[sym.SRODATA] { + relocs := ldr.Relocs(s) + if relocs.Count() == 0 { + ro = append(ro, s) + } else { + state.setSymType(s, sym.SRODATARELRO) + if outer := ldr.OuterSym(s); outer != 0 { + state.setSymType(outer, sym.SRODATARELRO) } + relro = append(relro, s) } + } - // Check that we haven't made two symbols with the same .Outer into - // different types (because references two symbols with non-nil Outer - // become references to the outer symbol + offset it's vital that the - // symbol and the outer end up in the same section). - for _, s := range relro { - if outer := ldr.OuterSym(s); outer != 0 { - st := state.symType(s) - ost := state.symType(outer) - if st != ost { - state.ctxt.Errorf(s, "inconsistent types for symbol and its Outer %s (%v != %v)", - ldr.SymName(outer), st, ost) - } + // Check that we haven't made two symbols with the same .Outer into + // different types (because references two symbols with non-nil Outer + // become references to the outer symbol + offset it's vital that the + // symbol and the outer end up in the same section). + for _, s := range relro { + if outer := ldr.OuterSym(s); outer != 0 { + st := state.symType(s) + ost := state.symType(outer) + if st != ost { + state.ctxt.Errorf(s, "inconsistent types for symbol and its Outer %s (%v != %v)", + ldr.SymName(outer), st, ost) } } - - state.data[symnro] = ro - state.data[symnrelro] = relro } + + state.data[sym.SRODATA] = ro + state.data[sym.SRODATARELRO] = relro } // dodataState holds bits of state information needed by dodata() and the @@ -1611,9 +1618,9 @@ type dodataState struct { // Link context ctxt *Link // Data symbols bucketed by type. - data [sym.SXREF][]loader.Sym + data [sym.SFirstUnallocated][]loader.Sym // Max alignment for each flavor of data symbol. - dataMaxAlign [sym.SXREF]int32 + dataMaxAlign [sym.SFirstUnallocated]int32 // Overridden sym type symGroupType []sym.SymKind // Current data size so far. @@ -1670,7 +1677,7 @@ func (ctxt *Link) dodata(symGroupType []sym.SymKind) { st := state.symType(s) - if st <= sym.STEXTFIPSEND || st >= sym.SXREF { + if st <= sym.STEXTEND || st >= sym.SFirstUnallocated { continue } state.data[st] = append(state.data[st], s) @@ -1682,6 +1689,20 @@ func (ctxt *Link) dodata(symGroupType []sym.SymKind) { ldr.SetAttrOnList(s, true) } + // SEH symbols are tracked in side lists (sehp.pdata/xdata), so make + // them follow the same reachability decision used for all other data. + filterReachableSEH := func(syms []loader.Sym) []loader.Sym { + out := syms[:0] + for _, s := range syms { + if ldr.AttrReachable(s) { + out = append(out, s) + } + } + return out + } + sehp.pdata = filterReachableSEH(sehp.pdata) + sehp.xdata = filterReachableSEH(sehp.xdata) + // Now that we have the data symbols, but before we start // to assign addresses, record all the necessary // dynamic relocations. These will grow the relocation @@ -1920,6 +1941,26 @@ func (state *dodataState) allocateDataSections(ctxt *Link) { } ldr := ctxt.loader + // SMODULEDATA needs to be writable, but the GC doesn't need to + // look at it. We don't use allocateSingleSymSections because + // the name of the section is not the name of the symbol. + if len(state.data[sym.SMODULEDATA]) > 0 { + if len(state.data[sym.SMODULEDATA]) != 1 { + Errorf("internal error: more than one SMODULEDATA symbol") + } + s := state.data[sym.SMODULEDATA][0] + sect := addsection(ldr, ctxt.Arch, &Segdata, ".go.module", 06) + sect.Align = symalign(ldr, s) + state.datsize = Rnd(state.datsize, int64(sect.Align)) + sect.Vaddr = uint64(state.datsize) + ldr.SetSymSect(s, sect) + state.setSymType(s, sym.SDATA) + ldr.SetSymValue(s, int64(uint64(state.datsize)-sect.Vaddr)) + state.datsize += ldr.SymSize(s) + sect.Length = uint64(state.datsize) - sect.Vaddr + state.checkdatsize(sym.SMODULEDATA) + } + // writable .got (note that for PIE binaries .got goes in relro) if len(state.data[sym.SELFGOT]) > 0 { state.allocateNamedSectionAndAssignSyms(&Segdata, ".got", sym.SELFGOT, sym.SDATA, 06) @@ -2003,6 +2044,15 @@ func (state *dodataState) allocateDataSections(ctxt *Link) { ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.noptrbss", 0), sect) ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.enoptrbss", 0), sect) + // Put gcmask symbols together. + gcmaskSym := ldr.LookupOrCreateSym("runtime.gcmask.*", 0) + ldr.SetSymValue(gcmaskSym, int64(sect.Length)) + ldr.SetSymSect(gcmaskSym, sect) + state.assignToSection(sect, sym.SGCMASK, sym.SNOPTRBSS) + if ctxt.HeadType == objabi.Haix { + xcoffUpdateOuterSize(ctxt, int64(sect.Length)-ldr.SymValue(gcmaskSym), sym.SGCMASK) + } + // Code coverage counters are assigned to the .noptrbss section. // We assign them in a separate pass so that they stay aggregated // together in a single blob (coverage runtime depends on this). @@ -2012,6 +2062,13 @@ func (state *dodataState) allocateDataSections(ctxt *Link) { ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.covctrs", 0), sect) ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.ecovctrs", 0), sect) + // If we started this blob at an odd alignment, then covctrs will + // not be correctly aligned. Each individual entry is aligned properly, + // but the start marker may be before any padding inserted to enforce + // that alignment. Fix that here. See issue 58936. + covCounterDataStartOff += covCounterDataLen % 4 + covCounterDataLen -= covCounterDataLen % 4 + // Coverage instrumentation counters for libfuzzer. if len(state.data[sym.SLIBFUZZER_8BIT_COUNTER]) > 0 { sect := state.allocateNamedSectionAndAssignSyms(&Segdata, ".go.fuzzcntrs", sym.SLIBFUZZER_8BIT_COUNTER, sym.Sxxx, 06) @@ -2082,10 +2139,6 @@ func (state *dodataState) allocateDataSections(ctxt *Link) { sect = state.allocateNamedDataSection(segro, ".rodata", sym.ReadOnly, 04) ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.rodata", 0), sect) ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.erodata", 0), sect) - if !ctxt.UseRelro() { - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.types", 0), sect) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.etypes", 0), sect) - } for _, symn := range sym.ReadOnly { symnStartValue := state.datsize if len(state.data[symn]) != 0 { @@ -2102,32 +2155,41 @@ func (state *dodataState) allocateDataSections(ctxt *Link) { } } + /* gopclntab */ + sect = state.allocateNamedSectionAndAssignSyms(segro, ".gopclntab", sym.SPCLNTAB, sym.SRODATA, 04) + ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.pclntab", 0), sect) + ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.pcheader", 0), sect) + ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.funcnametab", 0), sect) + ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.cutab", 0), sect) + ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.filetab", 0), sect) + ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.pctab", 0), sect) + ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.functab", 0), sect) + ldr.SetSymSect(ldr.LookupOrCreateSym("go:func.*", 0), sect) + ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.epclntab", 0), sect) + setCarrierSize(sym.SPCLNTAB, int64(sect.Length)) + if ctxt.HeadType == objabi.Haix { + xcoffUpdateOuterSize(ctxt, int64(sect.Length), sym.SPCLNTAB) + } + /* read-only ELF, Mach-O sections */ state.allocateSingleSymSections(segro, sym.SELFROSECT, sym.SRODATA, 04) - // There is some data that are conceptually read-only but are written to by - // relocations. On GNU systems, we can arrange for the dynamic linker to + // Read-only data that may require dynamic relocations at run time. + // + // On GNU systems, we can arrange for the dynamic linker to // mprotect sections after relocations are applied by giving them write - // permissions in the object file and calling them ".data.rel.ro.FOO". We - // divide the .rodata section between actual .rodata and .data.rel.ro.rodata, - // but for the other sections that this applies to, we just write a read-only - // .FOO section or a read-write .data.rel.ro.FOO section depending on the - // situation. - // TODO(mwhudson): It would make sense to do this more widely, but it makes - // the system linker segfault on darwin. - const relroPerm = 06 - const fallbackPerm = 04 - relroSecPerm := fallbackPerm + // permissions in the object file and calling them ".data.rel.ro.FOO". + + relroPerm := 04 genrelrosecname := func(suffix string) string { if suffix == "" { return ".rodata" } return suffix } - seg := segro + segRelro := segro if ctxt.UseRelro() { - segrelro := &Segrelrodata if ctxt.LinkMode == LinkExternal && !ctxt.IsAIX() && !ctxt.IsDarwin() { // Using a separate segment with an external // linker results in some programs moving @@ -2135,111 +2197,84 @@ func (state *dodataState) allocateDataSections(ctxt *Link) { // corrupts the moduledata. So we use the // rodata segment and let the external linker // sort out a rel.ro segment. - segrelro = segro } else { + segRelro = &Segrelrodata // Reset datsize for new segment. state.datsize = 0 } + relroPerm = 06 + if !ctxt.IsDarwin() { // We don't need the special names on darwin. genrelrosecname = func(suffix string) string { return ".data.rel.ro" + suffix } } + } - relroReadOnly := []sym.SymKind{} - for _, symnro := range sym.ReadOnly { - symn := sym.RelROMap[symnro] - relroReadOnly = append(relroReadOnly, symn) + // checkOuter is a sanity check that for all the symbols of some kind, + // which are in a given section, any carrier symbol is also in + // that section. + checkOuter := func(sect *sym.Section, symn sym.SymKind) { + for _, s := range state.data[symn] { + outer := ldr.OuterSym(s) + if s != 0 && ldr.SymSect(outer) != nil && ldr.SymSect(outer) != sect { + ctxt.Errorf(s, "s.Outer (%s) in different section from s, %s != %s", ldr.SymName(outer), ldr.SymSect(outer).Name, sect.Name) + } } - seg = segrelro - relroSecPerm = relroPerm - - /* data only written by relocations */ - sect = state.allocateNamedDataSection(segrelro, genrelrosecname(""), relroReadOnly, relroSecPerm) + } - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.types", 0), sect) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.etypes", 0), sect) + // createRelroSect will create a section that wil be a relro + // section if this link is using relro. + createRelroSect := func(name string, symn sym.SymKind) *sym.Section { + sect := state.allocateNamedDataSection(segRelro, genrelrosecname(name), []sym.SymKind{symn}, relroPerm) - for i, symnro := range sym.ReadOnly { - if i == 0 && symnro == sym.STYPE && ctxt.HeadType != objabi.Haix { - // Skip forward so that no type - // reference uses a zero offset. - // This is unlikely but possible in small - // programs with no other read-only data. - state.datsize++ + if symn == sym.STYPE { + // Increment state.datsize so that no type + // reference uses a zero offset. + // This is unlikely but possible in small + // programs with no other read-only data. + // + // But don't skip ahead if there is a runtime.types + // symbol with non-zero size. That can be created + // in fixZeroSizedSymbols. In that case the + // runtime.types symbol itself serves as the skip. + typesSym := ldr.Lookup("runtime.types", 0) + if typesSym == 0 || ldr.SymSize(typesSym) == 0 { + state.datsize += int64(ctxt.Arch.PtrSize) } + } - symn := sym.RelROMap[symnro] - if symn == sym.Sxxx { - continue - } - symnStartValue := state.datsize - if len(state.data[symn]) != 0 { - symnStartValue = aligndatsize(state, symnStartValue, state.data[symn][0]) - } + // Align to first symbol. + symnStartValue := state.datsize + if len(state.data[symn]) > 0 { + symnStartValue = aligndatsize(state, state.datsize, state.data[symn][0]) + } - for _, s := range state.data[symn] { - outer := ldr.OuterSym(s) - if s != 0 && ldr.SymSect(outer) != nil && ldr.SymSect(outer) != sect { - ctxt.Errorf(s, "s.Outer (%s) in different section from s, %s != %s", ldr.SymName(outer), ldr.SymSect(outer).Name, sect.Name) - } - } - state.assignToSection(sect, symn, sym.SRODATA) - setCarrierSize(symn, state.datsize-symnStartValue) - if ctxt.HeadType == objabi.Haix { - // Read-only symbols might be wrapped inside their outer - // symbol. - // XCOFF symbol table needs to know the size of - // these outer symbols. - xcoffUpdateOuterSize(ctxt, state.datsize-symnStartValue, symn) - } + checkOuter(sect, symn) + state.assignToSection(sect, symn, sym.SRODATA) + setCarrierSize(symn, state.datsize-symnStartValue) + if ctxt.HeadType == objabi.Haix { + // XCOFF symbol table needs to know the size + // of outer symbols. + xcoffUpdateOuterSize(ctxt, state.datsize-symnStartValue, symn) } sect.Length = uint64(state.datsize) - sect.Vaddr - - state.allocateSingleSymSections(segrelro, sym.SELFRELROSECT, sym.SRODATA, relroSecPerm) - state.allocateSingleSymSections(segrelro, sym.SMACHORELROSECT, sym.SRODATA, relroSecPerm) + return sect } - /* typelink */ - sect = state.allocateNamedDataSection(seg, genrelrosecname(".typelink"), []sym.SymKind{sym.STYPELINK}, relroSecPerm) - - typelink := ldr.CreateSymForUpdate("runtime.typelink", 0) - ldr.SetSymSect(typelink.Sym(), sect) - typelink.SetType(sym.SRODATA) - state.datsize += typelink.Size() - state.checkdatsize(sym.STYPELINK) - sect.Length = uint64(state.datsize) - sect.Vaddr + if len(state.data[sym.SRODATARELRO]) > 0 { + createRelroSect("", sym.SRODATARELRO) + } - /* itablink */ - sect = state.allocateNamedDataSection(seg, genrelrosecname(".itablink"), []sym.SymKind{sym.SITABLINK}, relroSecPerm) + sect = createRelroSect(".go.type", sym.STYPE) + ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.types", 0), sect) + ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.etypes", 0), sect) - itablink := ldr.CreateSymForUpdate("runtime.itablink", 0) - ldr.SetSymSect(itablink.Sym(), sect) - itablink.SetType(sym.SRODATA) - state.datsize += itablink.Size() - state.checkdatsize(sym.SITABLINK) - sect.Length = uint64(state.datsize) - sect.Vaddr + sect = createRelroSect(".go.func", sym.SGOFUNC) - /* gosymtab */ - sect = state.allocateNamedSectionAndAssignSyms(seg, genrelrosecname(".gosymtab"), sym.SSYMTAB, sym.SRODATA, relroSecPerm) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.symtab", 0), sect) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.esymtab", 0), sect) - - /* gopclntab */ - sect = state.allocateNamedSectionAndAssignSyms(seg, genrelrosecname(".gopclntab"), sym.SPCLNTAB, sym.SRODATA, relroSecPerm) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.pclntab", 0), sect) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.pcheader", 0), sect) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.funcnametab", 0), sect) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.cutab", 0), sect) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.filetab", 0), sect) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.pctab", 0), sect) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.functab", 0), sect) - ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.epclntab", 0), sect) - setCarrierSize(sym.SPCLNTAB, int64(sect.Length)) - if ctxt.HeadType == objabi.Haix { - xcoffUpdateOuterSize(ctxt, int64(sect.Length), sym.SPCLNTAB) - } + state.allocateSingleSymSections(segRelro, sym.SELFRELROSECT, sym.SRODATA, relroPerm) + state.allocateSingleSymSections(segRelro, sym.SMACHORELROSECT, sym.SRODATA, relroPerm) // 6g uses 4-byte relocation offsets, so the entire segment must fit in 32 bits. if state.datsize != int64(uint32(state.datsize)) { @@ -2247,11 +2282,11 @@ func (state *dodataState) allocateDataSections(ctxt *Link) { } siz := 0 - for symn := sym.SELFRXSECT; symn < sym.SXREF; symn++ { + for symn := sym.SELFRXSECT; symn < sym.SFirstUnallocated; symn++ { siz += len(state.data[symn]) } ctxt.datap = make([]loader.Sym, 0, siz) - for symn := sym.SELFRXSECT; symn < sym.SXREF; symn++ { + for symn := sym.SELFRXSECT; symn < sym.SFirstUnallocated; symn++ { ctxt.datap = append(ctxt.datap, state.data[symn]...) } } @@ -2307,10 +2342,13 @@ func (state *dodataState) allocateSEHSections(ctxt *Link) { } type symNameSize struct { - name string - sz int64 - val int64 - sym loader.Sym + name string + sz int64 + val int64 + sym loader.Sym + isTypelink bool + isItab bool + typeStr string } func (state *dodataState) dodataSect(ctxt *Link, symn sym.SymKind, syms []loader.Sym) (result []loader.Sym, maxAlign int32) { @@ -2354,43 +2392,190 @@ func (state *dodataState) dodataSect(ctxt *Link, symn sym.SymKind, syms []loader tail = s continue } + } else if ctxt.HeadType == objabi.Haix && ldr.SymName(s) == "runtime.types" { + // We always use runtime.types on AIX. + // See the comment in fixZeroSizedSymbols. + head = s } } zerobase = ldr.Lookup("runtime.zerobase", 0) + sortHeadTail := func(si, sj loader.Sym) (less bool, matched bool) { + switch { + case si == head, sj == tail: + return true, true + case sj == head, si == tail: + return false, true + } + return false, false + } + + sortFn := func(i, j int) bool { + si, sj := sl[i].sym, sl[j].sym + isz, jsz := sl[i].sz, sl[j].sz + if ret, matched := sortHeadTail(si, sj); matched { + return ret + } + if sortBySize { + switch { + // put zerobase right after all the zero-sized symbols, + // so zero-sized symbols have the same address as zerobase. + case si == zerobase: + return jsz != 0 // zerobase < nonzero-sized, zerobase > zero-sized + case sj == zerobase: + return isz == 0 // 0-sized < zerobase, nonzero-sized > zerobase + case isz != jsz: + return isz < jsz + } + } else { + iname := sl[i].name + jname := sl[j].name + if iname != jname { + return iname < jname + } + } + return si < sj // break ties by symbol number + } + // Perform the sort. - if symn != sym.SPCLNTAB { + switch symn { + case sym.SPCLNTAB: + // PCLNTAB was built internally, and already has the proper order. + + case sym.STYPE: + // Sort type descriptors with the typelink flag first, + // sorted by type string. The reflect package will use + // this to ensure that type descriptor pointers are unique. + // Sort itabs after type descriptors. + + // We define type:* for some links. + typeStar := ldr.Lookup("type:*", 0) + + // Pre-compute per-symbol sort keys into sl so the comparison + // function does only field reads instead of map lookups and + // loader dispatches on every call. + for k := range sl { + s := sl[k].sym + sl[k].isItab = ldr.IsItab(s) + if !sl[k].isItab { + sl[k].isTypelink = ldr.IsTypelink(s) + if sl[k].isTypelink { + sl[k].typeStr = decodetypeStr(ldr, ctxt.Arch, s) + } + } + } + sort.Slice(sl, func(i, j int) bool { si, sj := sl[i].sym, sl[j].sym - isz, jsz := sl[i].sz, sl[j].sz - switch { - case si == head, sj == tail: - return true - case sj == head, si == tail: - return false + + // Sort head and tail regardless of typelink. + if ret, matched := sortHeadTail(si, sj); matched { + return ret } - if sortBySize { - switch { - // put zerobase right after all the zero-sized symbols, - // so zero-sized symbols have the same address as zerobase. - case si == zerobase: - return jsz != 0 // zerobase < nonzero-sized, zerobase > zero-sized - case sj == zerobase: - return isz == 0 // 0-sized < zerobase, nonzero-sized > zerobase - case isz != jsz: - return isz < jsz + if typeStar != 0 { + // type:* comes first, after runtime.types + if si == typeStar { + return true + } else if sj == typeStar { + return false } - } else { - iname := sl[i].name - jname := sl[j].name - if iname != jname { - return iname < jname + } + + iIsType := !sl[i].isItab + jIsType := !sl[j].isItab + if iIsType && jIsType { + iIsTypelink := sl[i].isTypelink + jIsTypelink := sl[j].isTypelink + + if iIsTypelink && jIsTypelink { + // typelink symbols sort by type string + return sl[i].typeStr < sl[j].typeStr + } else if iIsTypelink { + // typelink < non-typelink + return true + } else if jIsTypelink { + // non-typelink > typelink + return false } + } else if iIsType { + // type < itab + return true + } else if jIsType { + // itab > type + return false } - return si < sj // break ties by symbol number + + // Otherwise, within non-typelink types and itabs, + // sort by size as usual. + return sortFn(i, j) }) - } else { - // PCLNTAB was built internally, and already has the proper order. + + // Find the end of the typelink descriptors. + // The size starts at PtrSize to match the value in + // createRelroSect in allocateDataSections. + // Note that we skip runtime.types in the loop, + // so we don't need to worry about that case; + // there will be an increment either way. + // TODO: This wastes some space. + typeLinkSize := int64(ctxt.Arch.PtrSize) + i := 0 + for ; i < len(sl); i++ { + si := sl[i].sym + if si == head || si == typeStar { + continue + } + if !sl[i].isTypelink { + break + } + typeLinkSize = Rnd(typeLinkSize, int64(symalign(ldr, si))) + typeLinkSize += sl[i].sz + } + + // Store the length of the typelink descriptors + // in the typedesclen field of moduledata. + if ctxt.moduledataTypeDescOffset == 0 { + Errorf("internal error: phase error: moduledataTypeDescOffset not set in dodataSect") + } else { + su := ldr.MakeSymbolUpdater(ctxt.Moduledata) + su.SetUint(ctxt.Arch, ctxt.moduledataTypeDescOffset, uint64(typeLinkSize)) + } + + // Find the end of the type descriptors. + typeSize := typeLinkSize + for ; i < len(sl); i++ { + if sl[i].isItab { + break + } + typeSize = Rnd(typeSize, int64(symalign(ldr, sl[i].sym))) + typeSize += sl[i].sz + } + + if i < len(sl) { + typeSize = Rnd(typeSize, int64(symalign(ldr, sl[i].sym))) + } + + if ctxt.moduledataItabOffset == 0 { + Errorf("internal error: phase error: moduledataItabOffset not set in dodataSect") + } else { + su := ldr.MakeSymbolUpdater(ctxt.Moduledata) + su.SetUint(ctxt.Arch, ctxt.moduledataItabOffset, uint64(typeSize)) + } + + itabSize := int64(0) + for ; i < len(sl); i++ { + itabSize = Rnd(itabSize, int64(symalign(ldr, sl[i].sym))) + itabSize += sl[i].sz + } + + if ctxt.moduledataItabSizeOffset == 0 { + Errorf("internal error: phase error: moduledataItabSizeOffset not set in dodataSect") + } else { + su := ldr.MakeSymbolUpdater(ctxt.Moduledata) + su.SetUint(ctxt.Arch, ctxt.moduledataItabSizeOffset, uint64(itabSize)) + } + + default: + sort.Slice(sl, sortFn) } // Set alignment, construct result @@ -2659,6 +2844,11 @@ func (ctxt *Link) textaddress() { ldr.SetSymValue(etext, int64(va)) ldr.SetSymValue(text, int64(Segtext.Sections[0].Vaddr)) } + if ctxt.IsWindows() { + // .pdata entries should be sorted by address, so process them now + // that we have final addresses for the text symbols. + collectSEH(ctxt) + } } // assigns address for a text symbol, returns (possibly new) section, its number, and the address. @@ -2835,9 +3025,6 @@ func (ctxt *Link) address() []*sym.Segment { // will be such that the last page of the text segment will be // mapped twice, once r-x and once starting out rw- and, after // relocation processing, changed to r--. - // - // Ideally the last page of the text segment would not be - // writable even for this short period. va = uint64(Rnd(int64(va), *FlagRound)) order = append(order, &Segrodata) @@ -2971,7 +3158,6 @@ func (ctxt *Link) address() []*sym.Segment { ldr := ctxt.loader var ( rodata = ldr.SymSect(ldr.LookupOrCreateSym("runtime.rodata", 0)) - symtab = ldr.SymSect(ldr.LookupOrCreateSym("runtime.symtab", 0)) pclntab = ldr.SymSect(ldr.LookupOrCreateSym("runtime.pclntab", 0)) types = ldr.SymSect(ldr.LookupOrCreateSym("runtime.types", 0)) ) @@ -3051,8 +3237,6 @@ func (ctxt *Link) address() []*sym.Segment { ctxt.xdefine("runtime.egcbss", sym.SRODATA, ldr.SymAddr(s)+ldr.SymSize(s)) ldr.SetSymSect(ldr.LookupOrCreateSym("runtime.egcbss", 0), ldr.SymSect(s)) - ctxt.xdefine("runtime.symtab", sym.SRODATA, int64(symtab.Vaddr)) - ctxt.xdefine("runtime.esymtab", sym.SRODATA, int64(symtab.Vaddr+symtab.Length)) ctxt.xdefine("runtime.pclntab", sym.SRODATA, int64(pclntab.Vaddr)) ctxt.defineInternal("runtime.pcheader", sym.SRODATA) ctxt.defineInternal("runtime.funcnametab", sym.SRODATA) @@ -3060,6 +3244,7 @@ func (ctxt *Link) address() []*sym.Segment { ctxt.defineInternal("runtime.filetab", sym.SRODATA) ctxt.defineInternal("runtime.pctab", sym.SRODATA) ctxt.defineInternal("runtime.functab", sym.SRODATA) + ctxt.defineInternal("go:func.*", sym.SRODATA) ctxt.xdefine("runtime.epclntab", sym.SRODATA, int64(pclntab.Vaddr+pclntab.Length)) ctxt.xdefine("runtime.noptrdata", sym.SNOPTRDATA, int64(noptr.Vaddr)) ctxt.xdefine("runtime.enoptrdata", sym.SNOPTRDATAEND, int64(noptr.Vaddr+noptr.Length)) @@ -3069,6 +3254,8 @@ func (ctxt *Link) address() []*sym.Segment { ctxt.xdefine("runtime.edata", sym.SDATAEND, int64(data.Vaddr+data.Length)) ctxt.xdefine("runtime.noptrbss", sym.SNOPTRBSS, int64(noptrbss.Vaddr)) ctxt.xdefine("runtime.enoptrbss", sym.SNOPTRBSS, int64(noptrbss.Vaddr+noptrbss.Length)) + s = ldr.Lookup("runtime.gcmask.*", 0) + ctxt.xdefine("runtime.gcmask.*", sym.SGCMASK, int64(noptrbss.Vaddr+uint64(ldr.SymValue(s)))) ctxt.xdefine("runtime.covctrs", sym.SCOVERAGE_COUNTER, int64(noptrbss.Vaddr+covCounterDataStartOff)) ctxt.xdefine("runtime.ecovctrs", sym.SCOVERAGE_COUNTER, int64(noptrbss.Vaddr+covCounterDataStartOff+covCounterDataLen)) ctxt.xdefine("runtime.end", sym.SBSS, int64(Segdata.Vaddr+Segdata.Length)) diff --git a/src/cmd/link/internal/ld/deadcode.go b/src/cmd/link/internal/ld/deadcode.go index 055b4efe5d403c..c540a8f21abc5f 100644 --- a/src/cmd/link/internal/ld/deadcode.go +++ b/src/cmd/link/internal/ld/deadcode.go @@ -545,30 +545,7 @@ func (d *deadcodePass) decodetypeMethods(ldr *loader.Loader, arch *sys.Arch, sym if !decodetypeHasUncommon(arch, p) { panic(fmt.Sprintf("no methods on %q", ldr.SymName(symIdx))) } - off := commonsize(arch) // reflect.rtype - switch decodetypeKind(arch, p) { - case abi.Struct: // reflect.structType - off += 4 * arch.PtrSize - case abi.Pointer: // reflect.ptrType - off += arch.PtrSize - case abi.Func: // reflect.funcType - off += arch.PtrSize // 4 bytes, pointer aligned - case abi.Slice: // reflect.sliceType - off += arch.PtrSize - case abi.Array: // reflect.arrayType - off += 3 * arch.PtrSize - case abi.Chan: // reflect.chanType - off += 2 * arch.PtrSize - case abi.Map: - off += 7*arch.PtrSize + 4 // internal/abi.MapType - if arch.PtrSize == 8 { - off += 4 // padding for final uint32 field (Flags). - } - case abi.Interface: // reflect.interfaceType - off += 3 * arch.PtrSize - default: - // just Sizeof(rtype) - } + off := abi.RTypeSize(decodetypeKind(arch, p), arch.PtrSize) mcount := int(decodeInuxi(arch, p[off+4:], 2)) moff := int(decodeInuxi(arch, p[off+4+2+2:], 4)) diff --git a/src/cmd/link/internal/ld/deadcode_test.go b/src/cmd/link/internal/ld/deadcode_test.go index 6962a4eba01195..95de54d54adc98 100644 --- a/src/cmd/link/internal/ld/deadcode_test.go +++ b/src/cmd/link/internal/ld/deadcode_test.go @@ -34,7 +34,6 @@ func TestDeadcode(t *testing.T) { []string{"main.large"}}, } for _, test := range tests { - test := test t.Run(test.src, func(t *testing.T) { t.Parallel() src := filepath.Join("testdata", "deadcode", test.src+".go") diff --git a/src/cmd/link/internal/ld/decodesym.go b/src/cmd/link/internal/ld/decodesym.go index 949ea5590589ae..79d985e3b24bdd 100644 --- a/src/cmd/link/internal/ld/decodesym.go +++ b/src/cmd/link/internal/ld/decodesym.go @@ -120,10 +120,7 @@ func decodetypeNameEmbedded(ldr *loader.Loader, symIdx loader.Sym, relocs *loade } func decodetypeFuncInType(ldr *loader.Loader, arch *sys.Arch, symIdx loader.Sym, relocs *loader.Relocs, i int) loader.Sym { - uadd := commonsize(arch) + 4 - if arch.PtrSize == 8 { - uadd += 4 - } + uadd := abi.RTypeSize(abi.Func, arch.PtrSize) if decodetypeHasUncommon(arch, ldr.Data(symIdx)) { uadd += uncommonSize(arch) } @@ -175,7 +172,7 @@ func decodetypeStructFieldCount(ldr *loader.Loader, arch *sys.Arch, symIdx loade func decodetypeStructFieldArrayOff(ldr *loader.Loader, arch *sys.Arch, symIdx loader.Sym, i int) int { data := ldr.Data(symIdx) - off := commonsize(arch) + 4*arch.PtrSize + off := abi.RTypeSize(abi.Struct, arch.PtrSize) if decodetypeHasUncommon(arch, data) { off += uncommonSize(arch) } diff --git a/src/cmd/link/internal/ld/dwarf.go b/src/cmd/link/internal/ld/dwarf.go index 222e712edeb608..1c51a7365210b5 100644 --- a/src/cmd/link/internal/ld/dwarf.go +++ b/src/cmd/link/internal/ld/dwarf.go @@ -100,7 +100,7 @@ func (c dwctxt) AddString(s dwarf.Sym, v string) { dsu.Addstring(v) } -func (c dwctxt) AddAddress(s dwarf.Sym, data interface{}, value int64) { +func (c dwctxt) AddAddress(s dwarf.Sym, data any, value int64) { ds := loader.Sym(s.(dwSym)) dsu := c.ldr.MakeSymbolUpdater(ds) if value != 0 { @@ -110,7 +110,7 @@ func (c dwctxt) AddAddress(s dwarf.Sym, data interface{}, value int64) { dsu.AddAddrPlus(c.arch, tgtds, value) } -func (c dwctxt) AddCURelativeAddress(s dwarf.Sym, data interface{}, value int64) { +func (c dwctxt) AddCURelativeAddress(s dwarf.Sym, data any, value int64) { ds := loader.Sym(s.(dwSym)) dsu := c.ldr.MakeSymbolUpdater(ds) if value != 0 { @@ -120,7 +120,7 @@ func (c dwctxt) AddCURelativeAddress(s dwarf.Sym, data interface{}, value int64) dsu.AddCURelativeAddrPlus(c.arch, tgtds, value) } -func (c dwctxt) AddSectionOffset(s dwarf.Sym, size int, t interface{}, ofs int64) { +func (c dwctxt) AddSectionOffset(s dwarf.Sym, size int, t any, ofs int64) { ds := loader.Sym(s.(dwSym)) dsu := c.ldr.MakeSymbolUpdater(ds) tds := loader.Sym(t.(dwSym)) @@ -132,7 +132,7 @@ func (c dwctxt) AddSectionOffset(s dwarf.Sym, size int, t interface{}, ofs int64 dsu.AddSymRef(c.arch, tds, ofs, objabi.R_ADDROFF, size) } -func (c dwctxt) AddDWARFAddrSectionOffset(s dwarf.Sym, t interface{}, ofs int64) { +func (c dwctxt) AddDWARFAddrSectionOffset(s dwarf.Sym, t any, ofs int64) { size := 4 if isDwarf64(c.linkctxt) { size = 8 @@ -148,14 +148,14 @@ func (c dwctxt) AddDWARFAddrSectionOffset(s dwarf.Sym, t interface{}, ofs int64) dsu.AddSymRef(c.arch, tds, ofs, objabi.R_DWARFSECREF, size) } -func (c dwctxt) AddIndirectTextRef(s dwarf.Sym, t interface{}) { +func (c dwctxt) AddIndirectTextRef(s dwarf.Sym, t any) { ds := loader.Sym(s.(dwSym)) dsu := c.ldr.MakeSymbolUpdater(ds) tds := loader.Sym(t.(dwSym)) dsu.AddSymRef(c.arch, tds, 0, objabi.R_DWTXTADDR_U4, 4) } -func (c dwctxt) Logf(format string, args ...interface{}) { +func (c dwctxt) Logf(format string, args ...any) { c.linkctxt.Logf(format, args...) } @@ -239,7 +239,7 @@ var dwtypes dwarf.DWDie // up all attrs in a single large table, then store indices into the // table in the DIE. This would allow us to common up storage for // attributes that are shared by many DIEs (ex: byte size of N). -func newattr(die *dwarf.DWDie, attr uint16, cls int, value int64, data interface{}) { +func newattr(die *dwarf.DWDie, attr uint16, cls int, value int64, data any) { a := new(dwarf.DWAttr) a.Link = die.Attr die.Attr = a @@ -1120,7 +1120,7 @@ func expandFile(fname string) string { // are emitted to the directory table first, then the file table is // emitted after that. // -// Note that there are some differences betwen DWARF versions 4 and 5 +// Note that there are some differences between DWARF versions 4 and 5 // regarding how files and directories are handled; the chief item is // that in version 4 we have an implicit directory index 0 that holds // the compilation dir, and an implicit file index 0 that holds the @@ -2036,7 +2036,7 @@ func dwarfGenerateDebugInfo(ctxt *Link) { t := d.ldr.SymType(idx) switch { case t.IsRODATA(), t.IsDATA(), t.IsNOPTRDATA(), - t == sym.STYPE, t == sym.SBSS, t == sym.SNOPTRBSS, t == sym.STLSBSS: + t == sym.STYPE, t == sym.SBSS, t == sym.SNOPTRBSS, t == sym.STLSBSS, t == sym.SMODULEDATA: // ok default: continue @@ -2394,28 +2394,6 @@ func (d *dwctxt) collectUnitLocs(u *sym.CompilationUnit) []loader.Sym { return syms } -// Add DWARF section names to the section header string table, by calling add -// on each name. ELF only. -func dwarfaddshstrings(ctxt *Link, add func(string)) { - if *FlagW { // disable dwarf - return - } - - secs := []string{"abbrev", "frame", "info", "loc", "line", "gdb_scripts"} - if buildcfg.Experiment.Dwarf5 { - secs = append(secs, "addr", "rnglists", "loclists") - } else { - secs = append(secs, "ranges", "loc") - } - - for _, sec := range secs { - add(".debug_" + sec) - if ctxt.IsExternal() { - add(elfRelType + ".debug_" + sec) - } - } -} - func dwarfaddelfsectionsyms(ctxt *Link) { if *FlagW { // disable dwarf return @@ -2428,7 +2406,7 @@ func dwarfaddelfsectionsyms(ctxt *Link) { for _, si := range dwarfp { s := si.secSym() sect := ldr.SymSect(si.secSym()) - putelfsectionsym(ctxt, ctxt.Out, s, sect.Elfsect.(*ElfShdr).shnum) + putelfsectionsym(ctxt, ctxt.Out, s, elfShdrShnum(sect.Elfsect.(*ElfShdr))) } } @@ -2507,19 +2485,19 @@ func dwarfcompress(ctxt *Link) { var prevSect *sym.Section for _, si := range dwarfp { for _, s := range si.syms { - ldr.SetSymValue(s, int64(pos)) sect := ldr.SymSect(s) if sect != prevSect { + if ctxt.IsWindows() { + pos = uint64(Rnd(int64(pos), PEFILEALIGN)) + } sect.Vaddr = pos prevSect = sect } + ldr.SetSymValue(s, int64(pos)) if ldr.SubSym(s) != 0 { log.Fatalf("%s: unexpected sub-symbols", ldr.SymName(s)) } pos += uint64(ldr.SymSize(s)) - if ctxt.IsWindows() { - pos = uint64(Rnd(int64(pos), PEFILEALIGN)) - } } } Segdwarf.Length = pos - Segdwarf.Vaddr diff --git a/src/cmd/link/internal/ld/dwarf_test.go b/src/cmd/link/internal/ld/dwarf_test.go index cc493f2c699814..8c2ac0d46a8e1c 100644 --- a/src/cmd/link/internal/ld/dwarf_test.go +++ b/src/cmd/link/internal/ld/dwarf_test.go @@ -279,7 +279,7 @@ func TestSizes(t *testing.T) { // External linking may bring in C symbols with unknown size. Skip. // - // N.B. go build below explictly doesn't pass through + // N.B. go build below explicitly doesn't pass through // -asan/-msan/-race, so we don't care about those. testenv.MustInternalLink(t, testenv.NoSpecialBuildTypes) @@ -408,7 +408,6 @@ func main() {} }, } for _, tc := range tests { - tc := tc t.Run(tc.name, func(t *testing.T) { t.Parallel() @@ -473,7 +472,6 @@ func main() { }, } for _, tc := range tests { - tc := tc t.Run(tc.name, func(t *testing.T) { t.Parallel() @@ -555,7 +553,6 @@ func main() { }, } for _, tc := range tests { - tc := tc t.Run(tc.name, func(t *testing.T) { t.Parallel() @@ -855,7 +852,7 @@ func TestAbstractOriginSanityIssue26237(t *testing.T) { func TestRuntimeTypeAttrInternal(t *testing.T) { testenv.MustHaveGoBuild(t) - // N.B. go build below explictly doesn't pass through + // N.B. go build below explicitly doesn't pass through // -asan/-msan/-race, so we don't care about those. testenv.MustInternalLink(t, testenv.NoSpecialBuildTypes) @@ -871,11 +868,12 @@ func TestRuntimeTypeAttrExternal(t *testing.T) { mustHaveDWARF(t) - // Explicitly test external linking, for dsymutil compatibility on Darwin. - if runtime.GOARCH == "ppc64" { - t.Skip("-linkmode=external not supported on ppc64") + if runtime.GOOS == "aix" { + // This fails with something like: DWARF type offset was 0xf18+0x200008b8, but test program said 0x1100017d0 + t.Skip("-linkmode=external not supported on aix") } + // Explicitly test external linking, for dsymutil compatibility on Darwin. testRuntimeTypeAttr(t, "-ldflags=-linkmode=external") } @@ -893,6 +891,10 @@ func main() { var x interface{} = &X{} p := *(*uintptr)(unsafe.Pointer(&x)) print(p) + f(nil) +} +//go:noinline +func f(x *X) { // Make sure that there is dwarf recorded for *X. } ` dir := t.TempDir() @@ -1489,7 +1491,7 @@ func TestIssue42484(t *testing.T) { testenv.MustHaveGoBuild(t) // Avoid spurious failures from external linkers. // - // N.B. go build below explictly doesn't pass through + // N.B. go build below explicitly doesn't pass through // -asan/-msan/-race, so we don't care about those. testenv.MustInternalLink(t, testenv.NoSpecialBuildTypes) @@ -1980,7 +1982,6 @@ func TestZeroSizedVariable(t *testing.T) { // See go.dev/issues/54615. for _, opt := range []string{NoOpt, DefaultOpt} { - opt := opt t.Run(opt, func(t *testing.T) { _, ex := gobuildAndExamine(t, zeroSizedVarProg, opt) diff --git a/src/cmd/link/internal/ld/elf.go b/src/cmd/link/internal/ld/elf.go index ed215d7fe50128..949ca6a3f698ae 100644 --- a/src/cmd/link/internal/ld/elf.go +++ b/src/cmd/link/internal/ld/elf.go @@ -10,6 +10,7 @@ import ( "cmd/internal/sys" "cmd/link/internal/loader" "cmd/link/internal/sym" + "cmp" "debug/elf" "encoding/binary" "encoding/hex" @@ -61,80 +62,44 @@ import ( * */ -/* - * ELF definitions that are independent of architecture or word size. - */ - -/* - * Note header. The ".note" section contains an array of notes. Each - * begins with this header, aligned to a word boundary. Immediately - * following the note header is n_namesz bytes of name, padded to the - * next word boundary. Then comes n_descsz bytes of descriptor, again - * padded to a word boundary. The values of n_namesz and n_descsz do - * not include the padding. - */ -type elfNote struct { - nNamesz uint32 - nDescsz uint32 - nType uint32 -} +// ELF definitions that are independent of architecture or word size. -/* For accessing the fields of r_info. */ - -/* For constructing r_info from field values. */ - -/* - * Relocation types. - */ -const ( - ARM_MAGIC_TRAMP_NUMBER = 0x5c000003 -) +// We use the 64-bit data structures on both 32- and 64-bit machines +// in order to write the code just once. The 64-bit data structure is +// written in the 32-bit format on the 32-bit machines. -/* - * Symbol table entries. - */ - -/* For accessing the fields of st_info. */ - -/* For constructing st_info from field values. */ - -/* For accessing the fields of st_other. */ - -/* - * ELF header. - */ +// ElfEhdr is the ELF file header. type ElfEhdr elf.Header64 -/* - * Section header. - */ +// ElfShdr is an ELF section table entry. type ElfShdr struct { elf.Section64 - shnum elf.SectionIndex -} - -/* - * Program header. - */ -type ElfPhdr elf.ProgHeader - -/* For accessing the fields of r_info. */ -/* For constructing r_info from field values. */ + // nameString is the section name as a string. + // This is not to be confused with Name, + // inherited from elf.Section64, which is an offset. + nameString string -/* - * Symbol table entries. - */ - -/* For accessing the fields of st_info. */ + // The section index, set by elfSortShdrs. + // Don't read this directly, use elfShdrShnum. + shnum elf.SectionIndex -/* For constructing st_info from field values. */ + // Because we don't compute the final section number + // until late in the link, when the link and info fields + // hold section indexes, we store pointers, and fetch + // the final section index when we write them out. + link *ElfShdr + info *ElfShdr + + // We compute the section offsets of reloc sections + // after we create the ELF section header. + // This field lets us fetch the section offset and size. + relocSect *sym.Section +} -/* For accessing the fields of st_other. */ +// ElfPhdr is the ELF program, or segment, header. +type ElfPhdr elf.ProgHeader -/* - * Go linker interface - */ const ( ELF64HDRSIZE = 64 ELF64PHDRSIZE = 56 @@ -149,32 +114,13 @@ const ( ELF32RELSIZE = 8 ) -/* - * The interface uses the 64-bit structures always, - * to avoid code duplication. The writers know how to - * marshal a 32-bit representation from the 64-bit structure. - */ +var elfstrdat []byte -var elfstrdat, elfshstrdat []byte - -/* - * Total amount of space to reserve at the start of the file - * for Header, PHeaders, SHeaders, and interp. - * May waste some. - * On FreeBSD, cannot be larger than a page. - */ -const ( - ELFRESERVE = 4096 -) - -/* - * We use the 64-bit data structures on both 32- and 64-bit machines - * in order to write the code just once. The 64-bit data structure is - * written in the 32-bit format on the 32-bit machines. - */ -const ( - NSECT = 400 -) +// ELFRESERVE is the total amount of space to reserve at the +// start of the file for Header, PHeaders, SHeaders, and interp. +// May waste some space. +// On FreeBSD, cannot be larger than a page. +const ELFRESERVE = 4096 var ( Nelfsym = 1 @@ -184,9 +130,10 @@ var ( // target platform uses. elfRelType string - ehdr ElfEhdr - phdr [NSECT]*ElfPhdr - shdr [NSECT]*ElfShdr + ehdr ElfEhdr + phdr = make([]*ElfPhdr, 0, 8) + shdr = make([]*ElfShdr, 0, 64) + shdrSorted bool interp string ) @@ -216,21 +163,10 @@ type ELFArch struct { DynamicReadOnly bool } -type Elfstring struct { - s string - off int -} - -var elfstr [100]Elfstring - -var nelfstr int - var buildinfo []byte -/* -Initialize the global variable that describes the ELF header. It will be updated as -we write section and prog headers. -*/ +// Elfinit initializes the global ehdr variable that holds the ELF header. +// It will be updated as write section and program headers. func Elfinit(ctxt *Link) { ctxt.IsELF = true @@ -242,30 +178,29 @@ func Elfinit(ctxt *Link) { switch ctxt.Arch.Family { // 64-bit architectures - case sys.PPC64, sys.S390X: - if ctxt.Arch.ByteOrder == binary.BigEndian && ctxt.HeadType != objabi.Hopenbsd { - ehdr.Flags = 1 /* Version 1 ABI */ - } else { - ehdr.Flags = 2 /* Version 2 ABI */ - } - fallthrough - case sys.AMD64, sys.ARM64, sys.Loong64, sys.MIPS64, sys.RISCV64: + case sys.AMD64, sys.ARM64, sys.Loong64, sys.MIPS64, sys.PPC64, sys.RISCV64, sys.S390X: if ctxt.Arch.Family == sys.MIPS64 { - ehdr.Flags = 0x20000004 /* MIPS 3 CPIC */ + ehdr.Flags = 0x20000004 // MIPS 3 CPIC } if ctxt.Arch.Family == sys.Loong64 { - ehdr.Flags = 0x43 /* DOUBLE_FLOAT, OBJABI_V1 */ + ehdr.Flags = 0x43 // DOUBLE_FLOAT, OBJABI_V1 } if ctxt.Arch.Family == sys.RISCV64 { - ehdr.Flags = 0x4 /* RISCV Float ABI Double */ + ehdr.Flags = 0x4 // RISCV Float ABI Double + } + if ctxt.Arch.Family == sys.S390X { + ehdr.Flags = 1 // Version 1 ABI + } + if ctxt.Arch.Family == sys.PPC64 { + ehdr.Flags = 2 // Version 2 ABI } elf64 = true - ehdr.Phoff = ELF64HDRSIZE /* Must be ELF64HDRSIZE: first PHdr must follow ELF header */ - ehdr.Shoff = ELF64HDRSIZE /* Will move as we add PHeaders */ - ehdr.Ehsize = ELF64HDRSIZE /* Must be ELF64HDRSIZE */ - ehdr.Phentsize = ELF64PHDRSIZE /* Must be ELF64PHDRSIZE */ - ehdr.Shentsize = ELF64SHDRSIZE /* Must be ELF64SHDRSIZE */ + ehdr.Phoff = ELF64HDRSIZE // Must be ELF64HDRSIZE: first PHdr must follow ELF header + ehdr.Shoff = ELF64HDRSIZE // Will move as we add PHeaders + ehdr.Ehsize = ELF64HDRSIZE // Must be ELF64HDRSIZE + ehdr.Phentsize = ELF64PHDRSIZE // Must be ELF64PHDRSIZE + ehdr.Shentsize = ELF64SHDRSIZE // Must be ELF64SHDRSIZE // 32-bit architectures case sys.ARM, sys.MIPS: @@ -283,22 +218,21 @@ func Elfinit(ctxt *Link) { ehdr.Flags = 0x5000002 // has entry point, Version5 EABI } } else if ctxt.Arch.Family == sys.MIPS { - ehdr.Flags = 0x50001004 /* MIPS 32 CPIC O32*/ + ehdr.Flags = 0x50001004 // MIPS 32 CPIC O32 } fallthrough default: ehdr.Phoff = ELF32HDRSIZE - /* Must be ELF32HDRSIZE: first PHdr must follow ELF header */ - ehdr.Shoff = ELF32HDRSIZE /* Will move as we add PHeaders */ - ehdr.Ehsize = ELF32HDRSIZE /* Must be ELF32HDRSIZE */ - ehdr.Phentsize = ELF32PHDRSIZE /* Must be ELF32PHDRSIZE */ - ehdr.Shentsize = ELF32SHDRSIZE /* Must be ELF32SHDRSIZE */ + // Must be ELF32HDRSIZE: first PHdr must follow ELF header + ehdr.Shoff = ELF32HDRSIZE // Will move as we add PHeaders + ehdr.Ehsize = ELF32HDRSIZE // Must be ELF32HDRSIZE + ehdr.Phentsize = ELF32PHDRSIZE // Must be ELF32PHDRSIZE + ehdr.Shentsize = ELF32SHDRSIZE // Must be ELF32SHDRSIZE } } -// Make sure PT_LOAD is aligned properly and -// that there is no gap, -// correct ELF loaders will do this implicitly, +// fixElfPhdr makes sure PT_LOAD is aligned properly and that there is no gap. +// Correct ELF loaders will do this implicitly, // but buggy ELF loaders like the one in some // versions of QEMU and UPX won't. func fixElfPhdr(e *ElfPhdr) { @@ -341,15 +275,72 @@ func elf32phdr(out *OutBuf, e *ElfPhdr) { out.Write32(uint32(e.Align)) } +// elfShdrShnum returns the section index of an ElfShdr. +func elfShdrShnum(e *ElfShdr) elf.SectionIndex { + if e.shnum == -1 { + Errorf("internal error: retrieved section index before it is set") + errorexit() + } + return e.shnum +} + +// elfShdrOff returns the section offset for an ElfShdr. +func elfShdrOff(e *ElfShdr) uint64 { + if e.relocSect != nil { + if e.Off != 0 { + Errorf("internal error: ElfShdr relocSect == %p Off == %d", e.relocSect, e.Off) + errorexit() + } + return e.relocSect.Reloff + } + return e.Off +} + +// elfShdrSize returns the section size for an ElfShdr. +func elfShdrSize(e *ElfShdr) uint64 { + if e.relocSect != nil { + if e.Size != 0 { + Errorf("internal error: ElfShdr relocSect == %p Size == %d", e.relocSect, e.Size) + errorexit() + } + return e.relocSect.Rellen + } + return e.Size +} + +// elfShdrLink returns the link value for an ElfShdr. +func elfShdrLink(e *ElfShdr) uint32 { + if e.link != nil { + if e.Link != 0 { + Errorf("internal error: ElfShdr link == %p Link == %d", e.link, e.Link) + errorexit() + } + return uint32(elfShdrShnum(e.link)) + } + return e.Link +} + +// elfShdrInfo returns the info value for an ElfShdr. +func elfShdrInfo(e *ElfShdr) uint32 { + if e.info != nil { + if e.Info != 0 { + Errorf("internal error: ElfShdr info == %p Info == %d", e.info, e.Info) + errorexit() + } + return uint32(elfShdrShnum(e.info)) + } + return e.Info +} + func elf64shdr(out *OutBuf, e *ElfShdr) { out.Write32(e.Name) out.Write32(e.Type) out.Write64(e.Flags) out.Write64(e.Addr) - out.Write64(e.Off) - out.Write64(e.Size) - out.Write32(e.Link) - out.Write32(e.Info) + out.Write64(elfShdrOff(e)) + out.Write64(elfShdrSize(e)) + out.Write32(elfShdrLink(e)) + out.Write32(elfShdrInfo(e)) out.Write64(e.Addralign) out.Write64(e.Entsize) } @@ -359,37 +350,106 @@ func elf32shdr(out *OutBuf, e *ElfShdr) { out.Write32(e.Type) out.Write32(uint32(e.Flags)) out.Write32(uint32(e.Addr)) - out.Write32(uint32(e.Off)) - out.Write32(uint32(e.Size)) - out.Write32(e.Link) - out.Write32(e.Info) + out.Write32(uint32(elfShdrOff(e))) + out.Write32(uint32(elfShdrSize(e))) + out.Write32(elfShdrLink(e)) + out.Write32(elfShdrInfo(e)) out.Write32(uint32(e.Addralign)) out.Write32(uint32(e.Entsize)) } func elfwriteshdrs(out *OutBuf) uint32 { if elf64 { - for i := 0; i < int(ehdr.Shnum); i++ { - elf64shdr(out, shdr[i]) + for _, sh := range shdr { + elf64shdr(out, sh) } - return uint32(ehdr.Shnum) * ELF64SHDRSIZE + return uint32(len(shdr)) * ELF64SHDRSIZE } - for i := 0; i < int(ehdr.Shnum); i++ { - elf32shdr(out, shdr[i]) + for _, sh := range shdr { + elf32shdr(out, sh) } - return uint32(ehdr.Shnum) * ELF32SHDRSIZE + return uint32(len(shdr)) * ELF32SHDRSIZE } -func elfsetstring(ctxt *Link, s loader.Sym, str string, off int) { - if nelfstr >= len(elfstr) { - ctxt.Errorf(s, "too many elf strings") - errorexit() +// elfSortShdrs sorts the section headers so that allocated sections +// are first, in address order. This isn't required for correctness, +// but it makes the ELF file easier for humans to read. +// We only do this for an executable, not an object file. +func elfSortShdrs(ctxt *Link) { + if ctxt.LinkMode != LinkExternal { + // Use [1:] to leave the empty section header zero in place. + slices.SortStableFunc(shdr[1:], func(a, b *ElfShdr) int { + isAllocated := func(h *ElfShdr) bool { + return elf.SectionFlag(h.Flags)&elf.SHF_ALLOC != 0 + } + if isAllocated(a) { + if isAllocated(b) { + if r := cmp.Compare(a.Addr, b.Addr); r != 0 { + return r + } + // With same address, sort smallest + // section first. + return cmp.Compare(a.Size, b.Size) + } + // Allocated before unallocated. + return -1 + } + if isAllocated(b) { + // Allocated before unallocated. + return 1 + } + return 0 + }) + } + for i, h := range shdr { + h.shnum = elf.SectionIndex(i) + } + shdrSorted = true +} + +// elfWriteShstrtab writes out the ELF section string table. +// It also sets the Name field of the section headers. +// It returns the length of the string table. +func elfWriteShstrtab(ctxt *Link) uint32 { + // Map from section name to shstrtab offset. + m := make(map[string]uint32, len(shdr)) + + m[""] = 0 + ctxt.Out.WriteByte(0) + off := uint32(1) + + writeString := func(s string) { + m[s] = off + ctxt.Out.WriteString(s) + ctxt.Out.WriteByte(0) + off += uint32(len(s)) + 1 + } + + // As a minor optimization, do the relocation sections first, + // as they may let us reuse the suffix. + // That is, the offset for ".text" can point into ".rel.text". + // We don't do a full suffix search as the relocation sections + // are likely to be the only match. + for _, sh := range shdr { + if suffix, ok := strings.CutPrefix(sh.nameString, elfRelType); ok { + if _, found := m[suffix]; !found { + m[suffix] = off + uint32(len(elfRelType)) + } + writeString(sh.nameString) + } + } + + for _, sh := range shdr { + if shOff, ok := m[sh.nameString]; ok { + sh.Name = shOff + } else { + sh.Name = off + writeString(sh.nameString) + } } - elfstr[nelfstr].s = str - elfstr[nelfstr].off = off - nelfstr++ + return off } func elfwritephdrs(out *OutBuf) uint32 { @@ -408,12 +468,8 @@ func elfwritephdrs(out *OutBuf) uint32 { func newElfPhdr() *ElfPhdr { e := new(ElfPhdr) - if ehdr.Phnum >= NSECT { - Errorf("too many phdrs") - } else { - phdr[ehdr.Phnum] = e - ehdr.Phnum++ - } + phdr = append(phdr, e) + ehdr.Phnum++ if elf64 { ehdr.Shoff += ELF64PHDRSIZE } else { @@ -422,17 +478,17 @@ func newElfPhdr() *ElfPhdr { return e } -func newElfShdr(name int64) *ElfShdr { - e := new(ElfShdr) - e.Name = uint32(name) - e.shnum = elf.SectionIndex(ehdr.Shnum) - if ehdr.Shnum >= NSECT { - Errorf("too many shdrs") - } else { - shdr[ehdr.Shnum] = e - ehdr.Shnum++ +func newElfShdr(name string) *ElfShdr { + if shdrSorted { + Errorf("internal error: creating a section header after they were sorted") + errorexit() } + e := &ElfShdr{ + nameString: name, + shnum: -1, // make invalid for now, set by elfSortShdrs + } + shdr = append(shdr, e) return e } @@ -483,7 +539,10 @@ func elfwritehdr(out *OutBuf) uint32 { return elf32writehdr(out) } -/* Taken directly from the definition document for ELF64. */ +// elfhash is the dynamic symbol hash function . +// This is taken directly from the definition document for ELF, +// except that instead of finishing with "h &^= g" we just write +// "h &= 0xfffffff", which results in the same value. func elfhash(name string) uint32 { var h uint32 for i := 0; i < len(name); i++ { @@ -578,6 +637,8 @@ func elfMipsAbiFlags(sh *ElfShdr, startva uint64, resoff uint64) int { return n } +// elfWriteMipsAbiFlags writes the .MIPS.abiflags section. +// // Layout is given by this C definition: // // typedef struct @@ -668,7 +729,7 @@ const ( ELF_NOTE_NETBSD_NAMESZ = 7 ELF_NOTE_NETBSD_DESCSZ = 4 ELF_NOTE_NETBSD_TAG = 1 - ELF_NOTE_NETBSD_VERSION = 700000000 /* NetBSD 7.0 */ + ELF_NOTE_NETBSD_VERSION = 700000000 // NetBSD 7.0 ) var ELF_NOTE_NETBSD_NAME = []byte("NetBSD\x00") @@ -817,7 +878,7 @@ func addbuildinfo(ctxt *Link) { } if ctxt.IsDarwin() { - buildinfo = uuidFromGoBuildId(buildID) + buildinfo = uuidFromHash(hash.Sum32([]byte(buildID))) return } @@ -1133,37 +1194,20 @@ func elfphrelro(seg *sym.Segment) { ph.Align = uint64(*FlagRound) } +// elfshname finds or creates a section given its name. func elfshname(name string) *ElfShdr { - for i := 0; i < nelfstr; i++ { - if name != elfstr[i].s { - continue + for _, sh := range shdr { + if sh.nameString == name { + return sh } - off := elfstr[i].off - for i = 0; i < int(ehdr.Shnum); i++ { - sh := shdr[i] - if sh.Name == uint32(off) { - return sh - } - } - return newElfShdr(int64(off)) } - Exitf("cannot find elf name %s", name) - return nil + return newElfShdr(name) } -// Create an ElfShdr for the section with name. -// Create a duplicate if one already exists with that name. +// elfshnamedup creates a new section with a given name. +// If there is an existing section with this name, it creates a duplicate. func elfshnamedup(name string) *ElfShdr { - for i := 0; i < nelfstr; i++ { - if name == elfstr[i].s { - off := elfstr[i].off - return newElfShdr(int64(off)) - } - } - - Errorf("cannot find elf name %s", name) - errorexit() - return nil + return newElfShdr(name) } func elfshalloc(sect *sym.Section) *ElfShdr { @@ -1250,11 +1294,12 @@ func elfshbits(linkmode LinkMode, sect *sym.Section) *ElfShdr { func elfshreloc(arch *sys.Arch, sect *sym.Section) *ElfShdr { // If main section is SHT_NOBITS, nothing to relocate. - // Also nothing to relocate in .shstrtab or notes. + // Also nothing to relocate in .shstrtab or notes or .gopclntab. if sect.Vaddr >= sect.Seg.Vaddr+sect.Seg.Filelen { return nil } - if sect.Name == ".shstrtab" || sect.Name == ".tbss" { + switch sect.Name { + case ".shstrtab", ".tbss", ".gopclntab": return nil } if sect.Elfsect.(*ElfShdr).Type == uint32(elf.SHT_NOTE) { @@ -1271,7 +1316,7 @@ func elfshreloc(arch *sys.Arch, sect *sym.Section) *ElfShdr { // its own .rela.text. if sect.Name == ".text" { - if sh.Info != 0 && sh.Info != uint32(sect.Elfsect.(*ElfShdr).shnum) { + if sh.info != nil && sh.info != sect.Elfsect.(*ElfShdr) { sh = elfshnamedup(elfRelType + sect.Name) } } @@ -1281,10 +1326,9 @@ func elfshreloc(arch *sys.Arch, sect *sym.Section) *ElfShdr { if typ == elf.SHT_RELA { sh.Entsize += uint64(arch.RegSize) } - sh.Link = uint32(elfshname(".symtab").shnum) - sh.Info = uint32(sect.Elfsect.(*ElfShdr).shnum) - sh.Off = sect.Reloff - sh.Size = sect.Rellen + sh.link = elfshname(".symtab") + sh.info = sect.Elfsect.(*ElfShdr) + sh.relocSect = sect sh.Addralign = uint64(arch.RegSize) return sh } @@ -1415,144 +1459,12 @@ func addgonote(ctxt *Link, sectionName string, tag uint32, desc []byte) { func (ctxt *Link) doelf() { ldr := ctxt.loader - /* predefine strings we need for section headers */ - - addshstr := func(s string) int { - off := len(elfshstrdat) - elfshstrdat = append(elfshstrdat, s...) - elfshstrdat = append(elfshstrdat, 0) - return off - } - - shstrtabAddstring := func(s string) { - off := addshstr(s) - elfsetstring(ctxt, 0, s, off) - } - - shstrtabAddstring("") - shstrtabAddstring(".text") - shstrtabAddstring(".noptrdata") - shstrtabAddstring(".data") - shstrtabAddstring(".bss") - shstrtabAddstring(".noptrbss") - shstrtabAddstring(".go.fuzzcntrs") - shstrtabAddstring(".go.buildinfo") - shstrtabAddstring(".go.fipsinfo") - if ctxt.IsMIPS() { - shstrtabAddstring(".MIPS.abiflags") - shstrtabAddstring(".gnu.attributes") - } - - // generate .tbss section for dynamic internal linker or external - // linking, so that various binutils could correctly calculate - // PT_TLS size. See https://golang.org/issue/5200. - if !*FlagD || ctxt.IsExternal() { - shstrtabAddstring(".tbss") - } - if ctxt.IsNetbsd() { - shstrtabAddstring(".note.netbsd.ident") - if *flagRace { - shstrtabAddstring(".note.netbsd.pax") - } - } - if ctxt.IsOpenbsd() { - shstrtabAddstring(".note.openbsd.ident") - } - if ctxt.IsFreebsd() { - shstrtabAddstring(".note.tag") - } - if len(buildinfo) > 0 { - shstrtabAddstring(".note.gnu.build-id") - } - if *flagBuildid != "" { - shstrtabAddstring(".note.go.buildid") - } - shstrtabAddstring(".elfdata") - shstrtabAddstring(".rodata") - // See the comment about data.rel.ro.FOO section names in data.go. - relro_prefix := "" - if ctxt.UseRelro() { - shstrtabAddstring(".data.rel.ro") - relro_prefix = ".data.rel.ro" - } - shstrtabAddstring(relro_prefix + ".typelink") - shstrtabAddstring(relro_prefix + ".itablink") - shstrtabAddstring(relro_prefix + ".gosymtab") - shstrtabAddstring(relro_prefix + ".gopclntab") - if ctxt.IsExternal() { *FlagD = true - - shstrtabAddstring(elfRelType + ".text") - shstrtabAddstring(elfRelType + ".rodata") - shstrtabAddstring(elfRelType + relro_prefix + ".typelink") - shstrtabAddstring(elfRelType + relro_prefix + ".itablink") - shstrtabAddstring(elfRelType + relro_prefix + ".gosymtab") - shstrtabAddstring(elfRelType + relro_prefix + ".gopclntab") - shstrtabAddstring(elfRelType + ".noptrdata") - shstrtabAddstring(elfRelType + ".data") - if ctxt.UseRelro() { - shstrtabAddstring(elfRelType + ".data.rel.ro") - } - shstrtabAddstring(elfRelType + ".go.buildinfo") - shstrtabAddstring(elfRelType + ".go.fipsinfo") - if ctxt.IsMIPS() { - shstrtabAddstring(elfRelType + ".MIPS.abiflags") - shstrtabAddstring(elfRelType + ".gnu.attributes") - } - - // add a .note.GNU-stack section to mark the stack as non-executable - shstrtabAddstring(".note.GNU-stack") - - if ctxt.IsShared() { - shstrtabAddstring(".note.go.abihash") - shstrtabAddstring(".note.go.pkg-list") - shstrtabAddstring(".note.go.deps") - } - } - - hasinitarr := ctxt.linkShared - - /* shared library initializer */ - switch ctxt.BuildMode { - case BuildModeCArchive, BuildModeCShared, BuildModeShared, BuildModePlugin: - hasinitarr = true - } - - if hasinitarr { - shstrtabAddstring(".init_array") - shstrtabAddstring(elfRelType + ".init_array") } - if !*FlagS { - shstrtabAddstring(".symtab") - shstrtabAddstring(".strtab") - } - if !*FlagW { - dwarfaddshstrings(ctxt, shstrtabAddstring) - } - - shstrtabAddstring(".shstrtab") - - if !*FlagD { /* -d suppresses dynamic loader format */ - shstrtabAddstring(".interp") - shstrtabAddstring(".hash") - shstrtabAddstring(".got") - if ctxt.IsPPC64() { - shstrtabAddstring(".glink") - } - shstrtabAddstring(".got.plt") - shstrtabAddstring(".dynamic") - shstrtabAddstring(".dynsym") - shstrtabAddstring(".dynstr") - shstrtabAddstring(elfRelType) - shstrtabAddstring(elfRelType + ".plt") - - shstrtabAddstring(".plt") - shstrtabAddstring(".gnu.version") - shstrtabAddstring(".gnu.version_r") - - /* dynamic symbol table - first entry all zeros */ + if !*FlagD { // -d suppresses dynamic loader format + // dynamic symbol table - first entry all zeros dynsym := ldr.CreateSymForUpdate(".dynsym", 0) dynsym.SetType(sym.SELFROSECT) @@ -1562,7 +1474,7 @@ func (ctxt *Link) doelf() { dynsym.SetSize(dynsym.Size() + ELF32SYMSIZE) } - /* dynamic string table */ + // dynamic string table dynstr := ldr.CreateSymForUpdate(".dynstr", 0) dynstr.SetType(sym.SELFROSECT) @@ -1570,11 +1482,11 @@ func (ctxt *Link) doelf() { dynstr.Addstring("") } - /* relocation table */ + // relocation table s := ldr.CreateSymForUpdate(elfRelType, 0) s.SetType(sym.SELFROSECT) - /* global offset table */ + // global offset table got := ldr.CreateSymForUpdate(".got", 0) if ctxt.UseRelro() { got.SetType(sym.SELFRELROSECT) @@ -1582,13 +1494,13 @@ func (ctxt *Link) doelf() { got.SetType(sym.SELFGOT) // writable } - /* ppc64 glink resolver */ + // ppc64 glink resolver if ctxt.IsPPC64() { s := ldr.CreateSymForUpdate(".glink", 0) s.SetType(sym.SELFRXSECT) } - /* hash */ + // hash hash := ldr.CreateSymForUpdate(".hash", 0) hash.SetType(sym.SELFROSECT) @@ -1617,7 +1529,7 @@ func (ctxt *Link) doelf() { s = ldr.CreateSymForUpdate(".gnu.version_r", 0) s.SetType(sym.SELFROSECT) - /* define dynamic elf table */ + // define dynamic elf table dynamic := ldr.CreateSymForUpdate(".dynamic", 0) switch { case thearch.ELF.DynamicReadOnly: @@ -1628,15 +1540,9 @@ func (ctxt *Link) doelf() { dynamic.SetType(sym.SELFSECT) } - if ctxt.IsS390X() { - // S390X uses .got instead of .got.plt - gotplt = got - } thearch.ELF.SetupPLT(ctxt, ctxt.loader, plt, gotplt, dynamic.Sym()) - /* - * .dynamic table - */ + // .dynamic table elfWriteDynEntSym(ctxt, dynamic, elf.DT_HASH, hash.Sym()) elfWriteDynEntSym(ctxt, dynamic, elf.DT_SYMTAB, dynsym.Sym()) @@ -1741,7 +1647,7 @@ func (ctxt *Link) doelf() { } } -// Do not write DT_NULL. elfdynhash will finish it. +// shsym fills in fields of sh where s contains the contents of the section. func shsym(sh *ElfShdr, ldr *loader.Loader, s loader.Sym) { if s == 0 { panic("bad symbol in shsym2") @@ -1764,7 +1670,7 @@ func phsh(ph *ElfPhdr, sh *ElfShdr) { } func Asmbelfsetup() { - /* This null SHdr must appear before all others */ + // This null SHdr must appear before all others. elfshname("") for _, sect := range Segtext.Sections { @@ -1796,19 +1702,6 @@ func asmbElf(ctxt *Link) { var symo int64 symo = int64(Segdwarf.Fileoff + Segdwarf.Filelen) symo = Rnd(symo, int64(ctxt.Arch.PtrSize)) - ctxt.Out.SeekSet(symo) - if *FlagS { - ctxt.Out.Write(elfshstrdat) - } else { - ctxt.Out.SeekSet(symo) - asmElfSym(ctxt) - ctxt.Out.Write(elfstrdat) - ctxt.Out.Write(elfshstrdat) - if ctxt.IsExternal() { - elfEmitReloc(ctxt) - } - } - ctxt.Out.SeekSet(0) ldr := ctxt.loader eh := getElfEhdr() @@ -1872,7 +1765,7 @@ func asmbElf(ctxt *Link) { phsh(getpnote(), sh) } if ctxt.LinkMode == LinkExternal { - /* skip program headers */ + // skip program headers eh.Phoff = 0 eh.Phentsize = 0 @@ -1896,7 +1789,7 @@ func asmbElf(ctxt *Link) { goto elfobj } - /* program header info */ + // program header info pph = newElfPhdr() pph.Type = elf.PT_PHDR @@ -1906,10 +1799,8 @@ func asmbElf(ctxt *Link) { pph.Paddr = uint64(*FlagTextAddr) - uint64(HEADR) + pph.Off pph.Align = uint64(*FlagRound) - /* - * PHDR must be in a loaded segment. Adjust the text - * segment boundaries downwards to include it. - */ + // PHDR must be in a loaded segment. Adjust the text + // segment boundaries downwards to include it. { o := int64(Segtext.Vaddr - pph.Vaddr) Segtext.Vaddr -= uint64(o) @@ -1919,8 +1810,8 @@ func asmbElf(ctxt *Link) { Segtext.Filelen += uint64(o) } - if !*FlagD { /* -d suppresses dynamic loader format */ - /* interpreter */ + if !*FlagD { // -d suppresses dynamic loader format + // interpreter sh := elfshname(".interp") sh.Type = uint32(elf.SHT_PROGBITS) @@ -2024,7 +1915,7 @@ func asmbElf(ctxt *Link) { } elfphload(&Segdata) - /* Dynamic linking sections */ + // Dynamic linking sections if !*FlagD { sh := elfshname(".dynsym") sh.Type = uint32(elf.SHT_DYNSYM) @@ -2035,9 +1926,9 @@ func asmbElf(ctxt *Link) { sh.Entsize = ELF32SYMSIZE } sh.Addralign = uint64(ctxt.Arch.RegSize) - sh.Link = uint32(elfshname(".dynstr").shnum) + sh.link = elfshname(".dynstr") - // sh.info is the index of first non-local symbol (number of local symbols) + // sh.Info is the index of first non-local symbol (number of local symbols) s := ldr.Lookup(".dynsym", 0) i := uint32(0) for sub := s; sub != 0; sub = ldr.SubSym(sub) { @@ -2060,7 +1951,7 @@ func asmbElf(ctxt *Link) { sh.Type = uint32(elf.SHT_GNU_VERSYM) sh.Flags = uint64(elf.SHF_ALLOC) sh.Addralign = 2 - sh.Link = uint32(elfshname(".dynsym").shnum) + sh.link = elfshname(".dynsym") sh.Entsize = 2 shsym(sh, ldr, ldr.Lookup(".gnu.version", 0)) @@ -2069,7 +1960,7 @@ func asmbElf(ctxt *Link) { sh.Flags = uint64(elf.SHF_ALLOC) sh.Addralign = uint64(ctxt.Arch.RegSize) sh.Info = uint32(elfverneed) - sh.Link = uint32(elfshname(".dynstr").shnum) + sh.link = elfshname(".dynstr") shsym(sh, ldr, ldr.Lookup(".gnu.version_r", 0)) } @@ -2079,8 +1970,8 @@ func asmbElf(ctxt *Link) { sh.Flags = uint64(elf.SHF_ALLOC) sh.Entsize = ELF64RELASIZE sh.Addralign = uint64(ctxt.Arch.RegSize) - sh.Link = uint32(elfshname(".dynsym").shnum) - sh.Info = uint32(elfshname(".plt").shnum) + sh.link = elfshname(".dynsym") + sh.info = elfshname(".plt") shsym(sh, ldr, ldr.Lookup(".rela.plt", 0)) sh = elfshname(".rela") @@ -2088,7 +1979,7 @@ func asmbElf(ctxt *Link) { sh.Flags = uint64(elf.SHF_ALLOC) sh.Entsize = ELF64RELASIZE sh.Addralign = 8 - sh.Link = uint32(elfshname(".dynsym").shnum) + sh.link = elfshname(".dynsym") shsym(sh, ldr, ldr.Lookup(".rela", 0)) } else { sh := elfshname(".rel.plt") @@ -2096,7 +1987,7 @@ func asmbElf(ctxt *Link) { sh.Flags = uint64(elf.SHF_ALLOC) sh.Entsize = ELF32RELSIZE sh.Addralign = 4 - sh.Link = uint32(elfshname(".dynsym").shnum) + sh.link = elfshname(".dynsym") shsym(sh, ldr, ldr.Lookup(".rel.plt", 0)) sh = elfshname(".rel") @@ -2104,7 +1995,7 @@ func asmbElf(ctxt *Link) { sh.Flags = uint64(elf.SHF_ALLOC) sh.Entsize = ELF32RELSIZE sh.Addralign = 4 - sh.Link = uint32(elfshname(".dynsym").shnum) + sh.link = elfshname(".dynsym") shsym(sh, ldr, ldr.Lookup(".rel", 0)) } @@ -2159,26 +2050,24 @@ func asmbElf(ctxt *Link) { sh.Flags = uint64(elf.SHF_ALLOC) sh.Entsize = 4 sh.Addralign = uint64(ctxt.Arch.RegSize) - sh.Link = uint32(elfshname(".dynsym").shnum) + sh.link = elfshname(".dynsym") shsym(sh, ldr, ldr.Lookup(".hash", 0)) - /* sh and elf.PT_DYNAMIC for .dynamic section */ + // sh and elf.PT_DYNAMIC for .dynamic section sh = elfshname(".dynamic") sh.Type = uint32(elf.SHT_DYNAMIC) sh.Flags = uint64(elf.SHF_ALLOC + elf.SHF_WRITE) sh.Entsize = 2 * uint64(ctxt.Arch.RegSize) sh.Addralign = uint64(ctxt.Arch.RegSize) - sh.Link = uint32(elfshname(".dynstr").shnum) + sh.link = elfshname(".dynstr") shsym(sh, ldr, ldr.Lookup(".dynamic", 0)) ph := newElfPhdr() ph.Type = elf.PT_DYNAMIC ph.Flags = elf.PF_R + elf.PF_W phsh(ph, sh) - /* - * Thread-local storage segment (really just size). - */ + // Thread-local storage segment (really just size). tlssize := uint64(0) for _, sect := range Segdata.Sections { if sect.Name == ".tbss" { @@ -2210,11 +2099,8 @@ func asmbElf(ctxt *Link) { } elfobj: - sh := elfshname(".shstrtab") - eh.Shstrndx = uint16(sh.shnum) - if ctxt.IsMIPS() { - sh = elfshname(".MIPS.abiflags") + sh := elfshname(".MIPS.abiflags") sh.Type = uint32(elf.SHT_MIPS_ABIFLAGS) sh.Flags = uint64(elf.SHF_ALLOC) sh.Addralign = 8 @@ -2280,6 +2166,25 @@ elfobj: sh.Flags = 0 } + elfSortShdrs(ctxt) + + sh := elfshname(".shstrtab") + eh.Shstrndx = uint16(elfShdrShnum(sh)) + + var shstrtabLen uint32 + ctxt.Out.SeekSet(symo) + if *FlagS { + shstrtabLen = elfWriteShstrtab(ctxt) + } else { + asmElfSym(ctxt) + ctxt.Out.Write(elfstrdat) + shstrtabLen = elfWriteShstrtab(ctxt) + if ctxt.IsExternal() { + elfEmitReloc(ctxt) + } + } + ctxt.Out.SeekSet(0) + var shstroff uint64 if !*FlagS { sh := elfshname(".symtab") @@ -2288,7 +2193,7 @@ elfobj: sh.Size = uint64(symSize) sh.Addralign = uint64(ctxt.Arch.RegSize) sh.Entsize = 8 + 2*uint64(ctxt.Arch.RegSize) - sh.Link = uint32(elfshname(".strtab").shnum) + sh.link = elfshname(".strtab") sh.Info = uint32(elfglobalsymndx) sh = elfshname(".strtab") @@ -2304,10 +2209,10 @@ elfobj: sh = elfshname(".shstrtab") sh.Type = uint32(elf.SHT_STRTAB) sh.Off = shstroff - sh.Size = uint64(len(elfshstrdat)) + sh.Size = uint64(shstrtabLen) sh.Addralign = 1 - /* Main header */ + // Main header copy(eh.Ident[:], elf.ELFMAG) var osabi elf.OSABI @@ -2354,6 +2259,11 @@ elfobj: pph.Memsz = pph.Filesz } + if len(shdr) >= 0xffff { + Errorf("too many ELF sections") + } + eh.Shnum = uint16(len(shdr)) + ctxt.Out.SeekSet(0) a := int64(0) a += int64(elfwritehdr(ctxt.Out)) @@ -2412,8 +2322,7 @@ func elfadddynsym(ldr *loader.Loader, target *Target, syms *ArchSyms, s loader.S d.AddUint32(target.Arch, uint32(dstru.Addstring(name))) if elf64 { - - /* type */ + // type var t uint8 if cgoexp && st.IsText() { @@ -2423,24 +2332,24 @@ func elfadddynsym(ldr *loader.Loader, target *Target, syms *ArchSyms, s loader.S } d.AddUint8(t) - /* reserved */ + // reserved d.AddUint8(0) - /* section where symbol is defined */ + // section where symbol is defined if st == sym.SDYNIMPORT { d.AddUint16(target.Arch, uint16(elf.SHN_UNDEF)) } else { d.AddUint16(target.Arch, 1) } - /* value */ + // value if st == sym.SDYNIMPORT { d.AddUint64(target.Arch, 0) } else { d.AddAddrPlus(target.Arch, s, 0) } - /* size of object */ + // size of object d.AddUint64(target.Arch, uint64(len(ldr.Data(s)))) dil := ldr.SymDynimplib(s) @@ -2452,17 +2361,17 @@ func elfadddynsym(ldr *loader.Loader, target *Target, syms *ArchSyms, s loader.S } } else { - /* value */ + // value if st == sym.SDYNIMPORT { d.AddUint32(target.Arch, 0) } else { d.AddAddrPlus(target.Arch, s, 0) } - /* size of object */ + // size of object d.AddUint32(target.Arch, uint32(len(ldr.Data(s)))) - /* type */ + // type var t uint8 // TODO(mwhudson): presumably the behavior should actually be the same on both arm and 386. @@ -2476,7 +2385,7 @@ func elfadddynsym(ldr *loader.Loader, target *Target, syms *ArchSyms, s loader.S d.AddUint8(t) d.AddUint8(0) - /* shndx */ + // shndx if st == sym.SDYNIMPORT { d.AddUint16(target.Arch, uint16(elf.SHN_UNDEF)) } else { diff --git a/src/cmd/link/internal/ld/elf_test.go b/src/cmd/link/internal/ld/elf_test.go index c2a1bc0b9442e0..92916187c5f63f 100644 --- a/src/cmd/link/internal/ld/elf_test.go +++ b/src/cmd/link/internal/ld/elf_test.go @@ -2,7 +2,7 @@ // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. -//go:build cgo +//go:build cgo && (dragonfly || freebsd || linux || netbsd || openbsd || solaris) package ld @@ -52,7 +52,7 @@ func main() { elfFile, err := elf.NewFile(fi) if err != nil { - t.Skip("The system may not support ELF, skipped.") + t.Fatal(err) } section := elfFile.Section(".dynsym") @@ -153,7 +153,7 @@ func main() { elfFile, err := elf.NewFile(fi) if err != nil { - t.Skip("The system may not support ELF, skipped.") + t.Fatal(err) } section := elfFile.Section(".shstrtab") @@ -316,7 +316,7 @@ func TestElfBindNow(t *testing.T) { elfFile, err := elf.NewFile(fi) if err != nil { - t.Skip("The system may not support ELF, skipped.") + t.Fatal(err) } defer elfFile.Close() @@ -408,8 +408,7 @@ func TestElfBindNow(t *testing.T) { } // This program is intended to be just big/complicated enough that -// we wind up with decent-sized .data.rel.ro.{typelink,itablink,gopclntab} -// sections. +// we wind up with a decent-sized .data.rel.ro.go.type section. const ifacecallsProg = ` package main @@ -488,7 +487,7 @@ func TestRelroSectionOverlapIssue67261(t *testing.T) { elfFile, err := elf.NewFile(fi) if err != nil { - t.Skip("The system may not support ELF, skipped.") + t.Fatal(err) } defer elfFile.Close() diff --git a/src/cmd/link/internal/ld/fips140.go b/src/cmd/link/internal/ld/fips140.go index c1887ee50a337e..8ab6f399102482 100644 --- a/src/cmd/link/internal/ld/fips140.go +++ b/src/cmd/link/internal/ld/fips140.go @@ -398,7 +398,7 @@ func machofips(ctxt *Link, exe, fipso string) error { return f.Close() } -// machofips updates go:fipsinfo after external linking +// elffips updates go:fipsinfo after external linking // on systems using ELF (most Unix systems). func elffips(ctxt *Link, exe, fipso string) error { // Open executable both for reading ELF and for the fipsObj. diff --git a/src/cmd/link/internal/ld/ld_test.go b/src/cmd/link/internal/ld/ld_test.go index 9a27ac8c764fc5..3cddcf797fc958 100644 --- a/src/cmd/link/internal/ld/ld_test.go +++ b/src/cmd/link/internal/ld/ld_test.go @@ -22,7 +22,7 @@ func TestUndefinedRelocErrors(t *testing.T) { // When external linking, symbols may be defined externally, so we allow // undefined symbols and let external linker resolve. Skip the test. // - // N.B. go build below explictly doesn't pass through + // N.B. go build below explicitly doesn't pass through // -asan/-msan/-race, so we don't care about those. testenv.MustInternalLink(t, testenv.NoSpecialBuildTypes) @@ -199,6 +199,49 @@ func TestWindowsBuildmodeCSharedASLR(t *testing.T) { }) } +func TestWindowsBuildmodeCSharedTrailingDotOutput(t *testing.T) { + if runtime.GOOS != "windows" { + t.Skip("skipping windows only test") + } + + t.Parallel() + testenv.MustHaveGoBuild(t) + testenv.MustHaveCGO(t) + testenv.MustHaveBuildMode(t, "c-shared") + + dir := t.TempDir() + srcfile := filepath.Join(dir, "test.go") + objfile := filepath.Join(dir, "mypackage.") + linktmp := filepath.Join(dir, "linktmp") + if err := os.Mkdir(linktmp, 0777); err != nil { + t.Fatal(err) + } + if err := os.WriteFile(srcfile, []byte(`package main +import "C" + +//export Hello +func Hello() {} + +func main() {} +`), 0666); err != nil { + t.Fatal(err) + } + + argv := []string{"build", "-buildmode=c-shared", "-o", objfile, "-ldflags", "-tmpdir=" + linktmp, srcfile} + out, err := testenv.Command(t, testenv.GoToolPath(t), argv...).CombinedOutput() + if err != nil { + t.Fatalf("build failure: %s\n%s\n", err, string(out)) + } + + def, err := os.ReadFile(filepath.Join(linktmp, "export_file.def")) + if err != nil { + t.Fatal(err) + } + if want := []byte("LIBRARY \"mypackage.\"\n"); !bytes.HasPrefix(def, want) { + t.Fatalf("export_file.def begins with %q, want %q", def, want) + } +} + func testWindowsBuildmodeCSharedASLR(t *testing.T, useASLR bool) { t.Parallel() testenv.MustHaveGoBuild(t) @@ -354,7 +397,6 @@ func main() { }, } for _, tt := range tests { - tt := tt t.Run(tt.name, func(t *testing.T) { t.Parallel() tempDir := t.TempDir() @@ -387,7 +429,7 @@ func TestRISCVTrampolines(t *testing.T) { buf := new(bytes.Buffer) fmt.Fprintf(buf, "TEXT a(SB),$0-0\n") for i := 0; i < 1<<17; i++ { - fmt.Fprintf(buf, "\tADD $0, X0, X0\n") + fmt.Fprintf(buf, "\tADD $0, X5, X0\n") } fmt.Fprintf(buf, "\tCALL b(SB)\n") fmt.Fprintf(buf, "\tRET\n") @@ -398,7 +440,7 @@ func TestRISCVTrampolines(t *testing.T) { fmt.Fprintf(buf, "\tRET\n") fmt.Fprintf(buf, "TEXT ·d(SB),0,$0-0\n") for i := 0; i < 1<<17; i++ { - fmt.Fprintf(buf, "\tADD $0, X0, X0\n") + fmt.Fprintf(buf, "\tADD $0, X5, X0\n") } fmt.Fprintf(buf, "\tCALL a(SB)\n") fmt.Fprintf(buf, "\tCALL c(SB)\n") diff --git a/src/cmd/link/internal/ld/lib.go b/src/cmd/link/internal/ld/lib.go index 2c861129b52f9a..b9848b232ce4ec 100644 --- a/src/cmd/link/internal/ld/lib.go +++ b/src/cmd/link/internal/ld/lib.go @@ -34,10 +34,12 @@ import ( "bytes" "debug/elf" "debug/macho" + "debug/pe" "encoding/base64" "encoding/binary" "fmt" "internal/buildcfg" + "internal/platform" "io" "log" "os" @@ -576,7 +578,8 @@ func (ctxt *Link) loadlib() { // Plugins a require cgo support to function. Similarly, plugins may require additional // internal linker support on some platforms which may not be implemented. - ctxt.canUsePlugins = ctxt.LibraryByPkg["plugin"] != nil && iscgo + ctxt.canUsePlugins = ctxt.LibraryByPkg["plugin"] != nil && iscgo && + platform.BuildModeSupported("gc", "plugin", buildcfg.GOOS, buildcfg.GOARCH) // We now have enough information to determine the link mode. determineLinkMode(ctxt) @@ -923,9 +926,7 @@ func (ctxt *Link) linksetup() { mdsb = ctxt.loader.MakeSymbolUpdater(moduledata) ctxt.loader.SetAttrLocal(moduledata, true) } - // In all cases way we mark the moduledata as noptrdata to hide it from - // the GC. - mdsb.SetType(sym.SNOPTRDATA) + mdsb.SetType(sym.SMODULEDATA) ctxt.loader.SetAttrReachable(moduledata, true) ctxt.Moduledata = moduledata @@ -1461,7 +1462,7 @@ func (ctxt *Link) hostlink() { // Only macOS supports unmapped segments such as our __DWARF segment. combineDwarf := ctxt.IsDarwin() && !*FlagW && machoPlatform == PLATFORM_MACOS - var isMSVC bool // used on Windows + var isMSVC, isLLD bool // used on Windows wlPrefix := "-Wl,--" switch ctxt.HeadType { @@ -1478,6 +1479,14 @@ func (ctxt *Link) hostlink() { // resolving a lazy binding. See issue 38824. // Force eager resolution to work around. argv = append(argv, "-Wl,-flat_namespace", "-Wl,-bind_at_load") + if combineDwarf && linkerFlagSupported(ctxt.Arch, argv[0], "", "-Wl,-no_fixup_chains") { + // As of macOS 27, the dynamic linker checks the number of segments + // in recorded in LC_DYLD_CHAINED_FIXUPS and reject the shared object + // with a mismatch. When combining DWARF, we add a segment but + // currently don't fix up the recorded number. Pass -no_fixup_chains to + // the C linker as a workaround. See issue 81793. + argv = append(argv, "-Wl,-no_fixup_chains") + } } if !combineDwarf { argv = append(argv, "-Wl,-S") // suppress STAB (symbolic debugging) symbols @@ -1488,6 +1497,12 @@ func (ctxt *Link) hostlink() { argv = append(argv, "-Wl,-x") } } + if *flagRace { + // With https://github.com/llvm/llvm-project/pull/182943, the race object + // has a weak import of __dyld_get_dyld_header, which is only defined on + // newer macOS (26.4+). + argv = append(argv, "-Wl,-U,__dyld_get_dyld_header") + } if *flagHostBuildid == "none" { argv = append(argv, "-Wl,-no_uuid") } @@ -1509,6 +1524,7 @@ func (ctxt *Link) hostlink() { } case objabi.Hwindows: isMSVC = ctxt.isMSVC() + isLLD = ctxt.isLLD() if isMSVC { // For various options, MSVC lld-link only accepts one dash. // TODO: It seems mingw clang supports one or two dashes, @@ -1531,10 +1547,22 @@ func (ctxt *Link) hostlink() { argv = append(argv, wlPrefix+"nxcompat") if !isMSVC { - argv = append(argv, fmt.Sprintf("-Wl,--major-os-version=%d", PeMinimumTargetMajorVersion)) - argv = append(argv, fmt.Sprintf("-Wl,--minor-os-version=%d", PeMinimumTargetMinorVersion)) - argv = append(argv, fmt.Sprintf("-Wl,--major-subsystem-version=%d", PeMinimumTargetMajorVersion)) - argv = append(argv, fmt.Sprintf("-Wl,--minor-subsystem-version=%d", PeMinimumTargetMinorVersion)) + peMajorVersion := PeMinimumTargetMajorVersion + peMinorVersion := PeMinimumTargetMinorVersion + if peMajorVersion >= 10 && !isLLD && + !peHasLoadConfigDirectorySupport(ctxt.Arch, argv[0]) { + // The external linker doesn't support wiring up + // _load_config_used to the PE Load Configuration + // Directory. Windows 10+ validates this directory, + // so fall back to an older version to avoid + // load failures. + peMajorVersion = 6 + peMinorVersion = 1 + } + argv = append(argv, fmt.Sprintf("-Wl,--major-os-version=%d", peMajorVersion)) + argv = append(argv, fmt.Sprintf("-Wl,--minor-os-version=%d", peMinorVersion)) + argv = append(argv, fmt.Sprintf("-Wl,--major-subsystem-version=%d", peMajorVersion)) + argv = append(argv, fmt.Sprintf("-Wl,--minor-subsystem-version=%d", peMinorVersion)) } case objabi.Haix: argv = append(argv, "-pthread") @@ -1700,22 +1728,48 @@ func (ctxt *Link) hostlink() { } if ctxt.Arch.InFamily(sys.ARM64) && buildcfg.GOOS == "linux" { - // On ARM64, the GNU linker will fail with - // -znocopyreloc if it thinks a COPY relocation is - // required. Switch to gold. + // On ARM64, the GNU linker had issues with -znocopyreloc + // and COPY relocations. This was fixed in GNU ld 2.36+. // https://sourceware.org/bugzilla/show_bug.cgi?id=19962 // https://go.dev/issue/22040 - altLinker = "gold" + // And newer gold is deprecated, may lack new features/flags, or even missing - // If gold is not installed, gcc will silently switch - // back to ld.bfd. So we parse the version information - // and provide a useful error if gold is missing. + // If the default linker is GNU ld 2.35 or older, use gold + useGold := false name, args := flagExtld[0], flagExtld[1:] - args = append(args, "-fuse-ld=gold", "-Wl,--version") + args = append(args, "-Wl,--version") cmd := exec.Command(name, args...) if out, err := cmd.CombinedOutput(); err == nil { - if !bytes.Contains(out, []byte("GNU gold")) { - log.Fatalf("ARM64 external linker must be gold (issue #15696, 22040), but is not: %s", out) + // Parse version from output like "GNU ld (GNU Binutils for Distro) 2.36.1" + for line := range strings.Lines(string(out)) { + if !strings.HasPrefix(line, "GNU ld ") { + continue + } + fields := strings.Fields(line[len("GNU ld "):]) + var major, minor int + if ret, err := fmt.Sscanf(fields[len(fields)-1], "%d.%d", &major, &minor); ret == 2 && err == nil { + if major == 2 && minor <= 35 { + useGold = true + } + break + } + } + } + + if useGold { + // Use gold for older linkers + altLinker = "gold" + + // If gold is not installed, gcc will silently switch + // back to ld.bfd. So we parse the version information + // and provide a useful error if gold is missing. + args = flagExtld[1:] + args = append(args, "-fuse-ld=gold", "-Wl,--version") + cmd = exec.Command(name, args...) + if out, err := cmd.CombinedOutput(); err == nil { + if !bytes.Contains(out, []byte("GNU gold")) { + log.Fatalf("ARM64 external linker must be ld>=2.36 or gold (issue #15696, 22040), but is not: %s", out) + } } } } @@ -1933,23 +1987,9 @@ func (ctxt *Link) hostlink() { checkStatic(p) } if ctxt.HeadType == objabi.Hwindows { - // Determine which linker we're using. Add in the extldflags in - // case used has specified "-fuse-ld=...". - extld := ctxt.extld() - name, args := extld[0], extld[1:] - args = append(args, trimLinkerArgv(flagExtldflags)...) - args = append(args, "-Wl,--version") - cmd := exec.Command(name, args...) - usingLLD := false - if out, err := cmd.CombinedOutput(); err == nil { - if bytes.Contains(out, []byte("LLD ")) { - usingLLD = true - } - } - // use gcc linker script to work around gcc bug // (see https://golang.org/issue/20183 for details). - if !usingLLD { + if !isLLD { p := writeGDBLinkerScript() argv = append(argv, "-Wl,-T,"+p) } @@ -2202,26 +2242,84 @@ func linkerFlagSupported(arch *sys.Arch, linker, altLinker, flag string) bool { return err == nil && !bytes.Contains(out, []byte("unrecognized")) && !bytes.Contains(out, []byte("unknown")) } +// peHasLoadConfigDirectorySupport checks whether the external linker +// populates the PE Load Configuration Directory data directory entry +// when it encounters a _load_config_used symbol. +// +// GNU ld gained this support in binutils 2.45. MSVC link.exe and +// LLVM lld-link have always supported it. +func peHasLoadConfigDirectorySupport(arch *sys.Arch, linker string) bool { + src := filepath.Join(*flagTmpdir, "loadcfg_test.c") + if err := os.WriteFile(src, []byte(` +#ifdef _WIN64 +typedef unsigned long long uintptr; +#else +typedef unsigned long uintptr; +#endif +const uintptr _load_config_used[2] = { sizeof(_load_config_used), 0 }; +int main() { return 0; } +`), 0666); err != nil { + return false + } + + outPath := filepath.Join(*flagTmpdir, "loadcfg_test.exe") + flags := hostlinkArchArgs(arch) + flags = append(flags, "-o", outPath, src) + cmd := exec.Command(linker, flags...) + cmd.Env = append([]string{"LC_ALL=C"}, os.Environ()...) + if err := cmd.Run(); err != nil { + return false + } + + f, err := pe.Open(outPath) + if err != nil { + return false + } + defer f.Close() + + switch oh := f.OptionalHeader.(type) { + case *pe.OptionalHeader64: + if int(pe.IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG) < len(oh.DataDirectory) { + return oh.DataDirectory[pe.IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG].VirtualAddress != 0 + } + case *pe.OptionalHeader32: + if int(pe.IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG) < len(oh.DataDirectory) { + return oh.DataDirectory[pe.IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG].VirtualAddress != 0 + } + } + return false +} + // trimLinkerArgv returns a new copy of argv that does not include flags // that are not relevant for testing whether some linker option works. func trimLinkerArgv(argv []string) []string { flagsWithNextArgSkip := []string{ "-F", "-l", - "-L", "-framework", "-Wl,-framework", "-Wl,-rpath", "-Wl,-undefined", } flagsWithNextArgKeep := []string{ + "-B", + "-L", "-arch", "-isysroot", "--sysroot", "-target", "--target", + "-resource-dir", + "-rtlib", + "--rtlib", + "-stdlib", + "--stdlib", + "-unwindlib", + "--unwindlib", } prefixesToKeep := []string{ + "-B", + "-L", "-f", "-m", "-p", @@ -2231,6 +2329,20 @@ func trimLinkerArgv(argv []string) []string { "--sysroot", "-target", "--target", + "-resource-dir", + "-rtlib", + "--rtlib", + "-stdlib", + "--stdlib", + "-unwindlib", + "--unwindlib", + "-nostdlib++", + "-nostdlib", + "-nodefaultlibs", + "-nostartfiles", + "-nostdinc++", + "-nostdinc", + "-nobuiltininc", } var flags []string @@ -2355,9 +2467,7 @@ func ldobj(ctxt *Link, f *bio.Reader, lib *sym.Library, length int64, pn string, if len(ls.Resources) != 0 { setpersrc(ctxt, ls.Resources) } - if ls.PData != 0 { - sehp.pdata = append(sehp.pdata, ls.PData) - } + sehp.pdata = append(sehp.pdata, ls.PData...) if ls.XData != 0 { sehp.xdata = append(sehp.xdata, ls.XData) } @@ -2410,7 +2520,7 @@ func ldobj(ctxt *Link, f *bio.Reader, lib *sym.Library, length int64, pn string, } // First, check that the basic GOOS, GOARCH, and Version match. - if line != wantHdr { + if line != wantHdr && !*flagF { Errorf("%s: linked object header mismatch:\nhave %q\nwant %q\n", pn, line, wantHdr) } @@ -2997,7 +3107,7 @@ func AddGotSym(target *Target, ldr *loader.Loader, syms *ArchSyms, s loader.Sym, // Mach-O relocations are a royal pain to lay out. // They use a compact stateful bytecode representation. // Here we record what are needed and encode them later. - MachoAddBind(int64(ldr.SymGot(s)), s) + MachoAddBind(syms.GOT, int64(ldr.SymGot(s)), s) } } else { ldr.Errorf(s, "addgotsym: unsupported binary format") @@ -3079,3 +3189,18 @@ func (ctxt *Link) isMSVC() bool { } return false } + +// isLLD reports whether the C toolchain is using LLD as the linker. +func (ctxt *Link) isLLD() bool { + extld := ctxt.extld() + name, args := extld[0], extld[1:] + args = append(args, trimLinkerArgv(flagExtldflags)...) + args = append(args, "-Wl,--version") + cmd := exec.Command(name, args...) + if out, err := cmd.CombinedOutput(); err == nil { + if bytes.Contains(out, []byte("LLD ")) { + return true + } + } + return false +} diff --git a/src/cmd/link/internal/ld/link.go b/src/cmd/link/internal/ld/link.go index df1fc7feabac30..c0d20680a709b9 100644 --- a/src/cmd/link/internal/ld/link.go +++ b/src/cmd/link/internal/ld/link.go @@ -96,6 +96,10 @@ type Link struct { Textp []loader.Sym Moduledata loader.Sym + moduledataTypeDescOffset int64 + moduledataItabOffset int64 + moduledataItabSizeOffset int64 + PackageFile map[string]string PackageShlib map[string]string @@ -126,7 +130,7 @@ type cgodata struct { directives [][]string } -func (ctxt *Link) Logf(format string, args ...interface{}) { +func (ctxt *Link) Logf(format string, args ...any) { fmt.Fprintf(ctxt.Bso, format, args...) ctxt.Bso.Flush() } diff --git a/src/cmd/link/internal/ld/macho.go b/src/cmd/link/internal/ld/macho.go index 8e059f299ffa73..9d984fa7a3d878 100644 --- a/src/cmd/link/internal/ld/macho.go +++ b/src/cmd/link/internal/ld/macho.go @@ -7,6 +7,7 @@ package ld import ( "bytes" "cmd/internal/codesign" + "cmd/internal/hash" imacho "cmd/internal/macho" "cmd/internal/objabi" "cmd/internal/sys" @@ -19,6 +20,7 @@ import ( "io" "os" "sort" + "strconv" "strings" "unsafe" ) @@ -180,6 +182,8 @@ const ( BIND_SPECIAL_DYLIB_FLAT_LOOKUP = -2 BIND_SPECIAL_DYLIB_WEAK_LOOKUP = -3 + BIND_SYMBOL_FLAGS_WEAK_IMPORT = 0x1 + BIND_OPCODE_MASK = 0xF0 BIND_IMMEDIATE_MASK = 0x0F BIND_OPCODE_DONE = 0x00 @@ -402,6 +406,50 @@ func machowrite(ctxt *Link, arch *sys.Arch, out *OutBuf, linkmode LinkMode) int return int(out.Offset() - o1) } +type macVersionFlag [3]byte + +func (f *macVersionFlag) String() string { + return fmt.Sprintf("%d.%d.%d", f[0], f[1], f[2]) +} + +func (f *macVersionFlag) Set(s string) error { + var parsed macVersionFlag + nums := strings.Split(s, ".") + if len(nums) > 3 { + goto Error + } + for i, num := range nums { + n, err := strconv.Atoi(num) + if err != nil || n < 0 || n > 0xFF { + goto Error + } + parsed[i] = byte(n) + } + // success, now modify f + *f = parsed + return nil + +Error: + return fmt.Errorf("invalid version %q", s) +} + +func (f *macVersionFlag) version() uint32 { + return uint32(f[0])<<16 | uint32(f[1])<<8 | uint32(f[2]) +} + +var ( + // On advice from Apple engineers, we keep macOS set to the + // oldest supported macOS version but keep macSDK to the newest + // tested OS/SDK version. If these defaults are not good enough, + // the -macos and -macsdk linker flags can override them. + // For past problems involving these values, see + // go.dev/issue/30488 + // go.dev/issue/56784 + // go.dev/issue/77917 + macOS = macVersionFlag{13, 0, 0} + macSDK = macVersionFlag{26, 2, 0} +) + func (ctxt *Link) domacho() { if *FlagD { return @@ -413,8 +461,7 @@ func (ctxt *Link) domacho() { if err != nil { Exitf("%v", err) } - if load != nil { - machoPlatform = load.platform + if load != nil && load.platform != PLATFORM_MACOS { ml := newMachoLoad(ctxt.Arch, load.cmd.type_, uint32(len(load.cmd.data))) copy(ml.data, load.cmd.data) break @@ -425,23 +472,12 @@ func (ctxt *Link) domacho() { if buildcfg.GOOS == "ios" { machoPlatform = PLATFORM_IOS } - if ctxt.LinkMode == LinkInternal && machoPlatform == PLATFORM_MACOS { - var version uint32 - switch ctxt.Arch.Family { - case sys.ARM64, sys.AMD64: - // This must be fairly recent for Apple signing (go.dev/issue/30488). - // Having too old a version here was also implicated in some problems - // calling into macOS libraries (go.dev/issue/56784). - // CL 460476 noted that in general this can be the most recent supported - // macOS version, but we haven't tested if going higher than Go's oldest - // supported macOS version could cause new problems. - version = 12<<16 | 0<<8 | 0<<0 // 12.0.0 - } + if load == nil && machoPlatform == PLATFORM_MACOS { ml := newMachoLoad(ctxt.Arch, imacho.LC_BUILD_VERSION, 4) ml.data[0] = uint32(machoPlatform) - ml.data[1] = version // OS version - ml.data[2] = version // SDK version - ml.data[3] = 0 // ntools + ml.data[1] = macOS.version() + ml.data[2] = macSDK.version() + ml.data[3] = 0 // ntools } } @@ -804,18 +840,24 @@ func asmbMacho(ctxt *Link) { } } - if ctxt.IsInternal() && len(buildinfo) > 0 { + if ctxt.IsInternal() && *flagHostBuildid != "none" { ml := newMachoLoad(ctxt.Arch, imacho.LC_UUID, 4) - // Mach-O UUID is 16 bytes - if len(buildinfo) < 16 { - buildinfo = append(buildinfo, make([]byte, 16)...) + var uuid [16]byte + if len(buildinfo) >= 16 { + copy(uuid[:], buildinfo) + } else { + // Note: When setting macSDK to 26.2, dyld refuses to run any + // binary without an LC_UUID, which makes bootstrap fail. + // To work around that situation, if buildinfo is missing we + // construct a hash of the binary written so far and use that. + // Using -B none will bypass this if desired, + // but the resulting binary may not be runnable. + copy(uuid[:], uuidFromHash(hash.Sum32(ctxt.Out.Data()))) } - // By default, buildinfo is already in UUIDv3 format - // (see uuidFromGoBuildId). - ml.data[0] = ctxt.Arch.ByteOrder.Uint32(buildinfo) - ml.data[1] = ctxt.Arch.ByteOrder.Uint32(buildinfo[4:]) - ml.data[2] = ctxt.Arch.ByteOrder.Uint32(buildinfo[8:]) - ml.data[3] = ctxt.Arch.ByteOrder.Uint32(buildinfo[12:]) + ml.data[0] = ctxt.Arch.ByteOrder.Uint32(uuid[0:]) + ml.data[1] = ctxt.Arch.ByteOrder.Uint32(uuid[4:]) + ml.data[2] = ctxt.Arch.ByteOrder.Uint32(uuid[8:]) + ml.data[3] = ctxt.Arch.ByteOrder.Uint32(uuid[12:]) } if ctxt.IsInternal() && ctxt.NeedCodeSign() { @@ -838,7 +880,7 @@ func asmbMacho(ctxt *Link) { if int64(len(data)) != codesigOff { panic("wrong size") } - codesign.Sign(ldr.Data(cs), bytes.NewReader(data), "a.out", codesigOff, int64(mstext.fileoffset), int64(mstext.filesize), ctxt.IsExe() || ctxt.IsPIE()) + codesign.Sign(ldr.Data(cs), bytes.NewBuffer(data), "a.out", codesigOff, int64(mstext.fileoffset), int64(mstext.filesize), ctxt.IsExe() || ctxt.IsPIE()) ctxt.Out.SeekSet(codesigOff) ctxt.Out.Write(ldr.Data(cs)) } @@ -919,7 +961,7 @@ func collectmachosyms(ctxt *Link) { continue } t := ldr.SymType(s) - if t >= sym.SELFRXSECT && t < sym.SXREF { // data sections handled in dodata + if t >= sym.SELFRXSECT && t < sym.SFirstUnallocated { // data sections handled in dodata if t == sym.STLSBSS { // TLSBSS is not used on darwin. See data.go:allocateDataSections continue @@ -1004,7 +1046,7 @@ func AddMachoSym(ldr *loader.Loader, s loader.Sym) { // When dynamically linking, all non-local variables and plugin-exported // symbols need to be exported. func machoShouldExport(ctxt *Link, ldr *loader.Loader, s loader.Sym) bool { - if !ctxt.DynlinkingGo() || ldr.AttrLocal(s) { + if !ctxt.DynlinkingGo() || ldr.AttrLocal(s) || (ldr.IsContentHashed(s) && ldr.SymType(s).IsText()) { return false } if ctxt.BuildMode == BuildModePlugin && strings.HasPrefix(ldr.SymExtname(s), objabi.PathToPrefix(*flagPluginPath)) { @@ -1336,21 +1378,24 @@ func MachoAddRebase(s loader.Sym, off int64) { machorebase = append(machorebase, machoRebaseRecord{s, off}) } -// A bind entry tells the dynamic linker the data at GOT+off should be bound +// A bind entry tells the dynamic linker the data at sym+off should be bound // to the address of the target symbol, which is a dynamic import. +// sym is the symbol containing the pointer (e.g. the GOT or a data symbol), +// off is the offset within that symbol, and targ is the dynamic import target. // For now, the only kind of entry we support is that the data is an absolute -// address, and the source symbol is always the GOT. That seems all we need. +// address. That seems all we need. // In the binary it uses a compact stateful bytecode encoding. So we record // entries as we go and build the table at the end. type machoBindRecord struct { + sym loader.Sym off int64 targ loader.Sym } var machobind []machoBindRecord -func MachoAddBind(off int64, targ loader.Sym) { - machobind = append(machobind, machoBindRecord{off, targ}) +func MachoAddBind(sym loader.Sym, off int64, targ loader.Sym) { + machobind = append(machobind, machoBindRecord{sym, off, targ}) } // Generate data for the dynamic linker, used in LC_DYLD_INFO_ONLY load command. @@ -1410,12 +1455,10 @@ func machoDyldInfo(ctxt *Link) { // Bind table. // TODO: compact encoding, as above. // TODO: lazy binding? - got := ctxt.GOT - seg := ldr.SymSect(got).Seg - gotAddr := ldr.SymValue(got) bind.AddUint8(BIND_OPCODE_SET_TYPE_IMM | BIND_TYPE_POINTER) for _, r := range machobind { - off := uint64(gotAddr+r.off) - seg.Vaddr + seg := ldr.SymSect(r.sym).Seg + off := uint64(ldr.SymValue(r.sym)+r.off) - seg.Vaddr bind.AddUint8(BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB | segId(seg)) bind.AddUleb(off) @@ -1429,7 +1472,11 @@ func machoDyldInfo(ctxt *Link) { bind.AddUint8(BIND_OPCODE_SET_DYLIB_SPECIAL_IMM | uint8(d)&0xf) } - bind.AddUint8(BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM) + flags := uint8(0) + if ldr.SymWeakBinding(r.targ) { + flags |= BIND_SYMBOL_FLAGS_WEAK_IMPORT + } + bind.AddUint8(BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM | flags) // target symbol name as a C string, with _ prefix bind.AddUint8('_') bind.Addstring(ldr.SymExtname(r.targ)) diff --git a/src/cmd/link/internal/ld/macho_combine_dwarf.go b/src/cmd/link/internal/ld/macho_combine_dwarf.go index d60755f147d511..2b303cbdae138e 100644 --- a/src/cmd/link/internal/ld/macho_combine_dwarf.go +++ b/src/cmd/link/internal/ld/macho_combine_dwarf.go @@ -392,7 +392,7 @@ func machoUpdateDwarfHeader(r *imacho.LoadCmdUpdater, compressedSects []*macho.S return machoUpdateSections(*r, &seg, uint64(dwarfstart)-realdwarf.Offset, compressedSects) } -func machoUpdateLoadCommand(r imacho.LoadCmdUpdater, linkseg *macho.Segment, linkoffset uint64, cmd interface{}, fields ...string) error { +func machoUpdateLoadCommand(r imacho.LoadCmdUpdater, linkseg *macho.Segment, linkoffset uint64, cmd any, fields ...string) error { if err := r.ReadAt(0, cmd); err != nil { return err } diff --git a/src/cmd/link/internal/ld/macho_test.go b/src/cmd/link/internal/ld/macho_test.go index 29adc0b78b1165..000b5f2ab212ed 100644 --- a/src/cmd/link/internal/ld/macho_test.go +++ b/src/cmd/link/internal/ld/macho_test.go @@ -37,14 +37,14 @@ func TestMachoSectionsReadOnly(t *testing.T) { args: []string{"-ldflags", "-linkmode=internal"}, prog: prog, mustInternalLink: true, - wantSecsRO: []string{"__got", "__rodata", "__itablink", "__typelink", "__gosymtab", "__gopclntab"}, + wantSecsRO: []string{"__got", "__rodata"}, }, { name: "linkmode-external", args: []string{"-ldflags", "-linkmode=external"}, prog: prog, mustHaveCGO: true, - wantSecsRO: []string{"__got", "__rodata", "__itablink", "__typelink", "__gopclntab"}, + wantSecsRO: []string{"__got", "__rodata"}, }, { name: "cgo-linkmode-internal", @@ -52,14 +52,14 @@ func TestMachoSectionsReadOnly(t *testing.T) { prog: progC, mustHaveCGO: true, mustInternalLink: true, - wantSecsRO: []string{"__got", "__rodata", "__itablink", "__typelink", "__gopclntab"}, + wantSecsRO: []string{"__got", "__rodata"}, }, { name: "cgo-linkmode-external", args: []string{"-ldflags", "-linkmode=external"}, prog: progC, mustHaveCGO: true, - wantSecsRO: []string{"__got", "__rodata", "__itablink", "__typelink", "__gopclntab"}, + wantSecsRO: []string{"__got", "__rodata"}, }, } @@ -111,7 +111,8 @@ func TestMachoSectionsReadOnly(t *testing.T) { for _, wsroname := range test.wantSecsRO { // Now walk the sections. Section should be part of - // some segment that is readonly. + // some segment that is made readonly after + // relocations are appied. var wsro *macho.Section foundRO := false for _, s := range machoFile.Sections { diff --git a/src/cmd/link/internal/ld/macho_update_uuid.go b/src/cmd/link/internal/ld/macho_update_uuid.go index 968bd7bb2554af..71e1fbf6b9b6d4 100644 --- a/src/cmd/link/internal/ld/macho_update_uuid.go +++ b/src/cmd/link/internal/ld/macho_update_uuid.go @@ -18,7 +18,6 @@ package ld // final executable generated by the external linker. import ( - "cmd/internal/hash" imacho "cmd/internal/macho" "debug/macho" @@ -26,27 +25,19 @@ import ( "os" ) -// uuidFromGoBuildId hashes the Go build ID and returns a slice of 16 -// bytes suitable for use as the payload in a Macho LC_UUID load -// command. -func uuidFromGoBuildId(buildID string) []byte { - if buildID == "" { - return make([]byte, 16) - } - hashedBuildID := hash.Sum32([]byte(buildID)) - rv := hashedBuildID[:16] +// uuidFromHash converts a hash to a UUID +// suitable for use in the Macho LC_UUID load command. +func uuidFromHash(hashed [32]byte) []byte { + rv := make([]byte, 16) + copy(rv, hashed[:16]) - // RFC 4122 conformance (see RFC 4122 Sections 4.2.2, 4.1.3). We - // want the "version" of this UUID to appear as 'hashed' as opposed - // to random or time-based. This is something of a fiction since - // we're not actually hashing using MD5 or SHA1, but it seems better - // to use this UUID flavor than any of the others. This is similar - // to how other linkers handle this (for example this code in lld: - // https://github.com/llvm/llvm-project/blob/2a3a79ce4c2149d7787d56f9841b66cacc9061d0/lld/MachO/Writer.cpp#L524). - rv[6] &= 0x0f - rv[6] |= 0x30 - rv[8] &= 0x3f - rv[8] |= 0xc0 + // Mark the UUID as version 3, variant 1, which is an MD5-hash-based UUID. + // We are not actually using MD5, but we're also not using SHA1 (version 5), + // and LLVM also uses version 3 [1] so this seems good enough. + // + // [1] https://github.com/llvm/llvm-project/blob/2a3a79ce4c2149d7787d56f9841b66cacc9061d0/lld/MachO/Writer.cpp#L524 + rv[6] = (rv[6] &^ 0xF0) | 0x30 // version 3 + rv[8] = (rv[8] &^ 0xC0) | 0x80 // variant 1 return rv } @@ -74,7 +65,7 @@ func machoRewriteUuid(ctxt *Link, exef *os.File, exem *macho.File, outexe string // Read the load commands, looking for the LC_UUID cmd. If/when we // locate it, overwrite it with a new value produced by - // uuidFromGoBuildId. + // uuidFromHash. reader := imacho.NewLoadCmdUpdater(outf, exem.ByteOrder, cmdOffset) for i := uint32(0); i < exem.Ncmd; i++ { cmd, err := reader.Next() diff --git a/src/cmd/link/internal/ld/main.go b/src/cmd/link/internal/ld/main.go index d913953944bc43..19ed197a20b57e 100644 --- a/src/cmd/link/internal/ld/main.go +++ b/src/cmd/link/internal/ld/main.go @@ -55,9 +55,11 @@ var ( ) func init() { - flag.Var(&rpath, "r", "set the ELF dynamic linker search `path` to dir1:dir2:...") flag.Var(&flagExtld, "extld", "use `linker` when linking in external mode") flag.Var(&flagExtldflags, "extldflags", "pass `flags` to external linker") + flag.Var(&macOS, "macos", "mac OS version to write in build info (only used in internal linking)") + flag.Var(&macSDK, "macsdk", "mac SDK version to write in build info (only used in internal linking)") + flag.Var(&rpath, "r", "set the ELF dynamic linker search `path` to dir1:dir2:...") flag.Var(&flagW, "w", "disable DWARF generation") } @@ -188,7 +190,11 @@ func Main(arch *sys.Arch, theArch Arch) { buildVersion := buildcfg.Version if goexperiment := buildcfg.Experiment.String(); goexperiment != "" { - buildVersion += " X:" + goexperiment + sep := " " + if !strings.Contains(buildVersion, "-") { // See go.dev/issue/75953. + sep = "-" + } + buildVersion += sep + "X:" + goexperiment } addstrdata1(ctxt, "runtime.buildVersion="+buildVersion) @@ -418,8 +424,6 @@ func Main(arch *sys.Arch, theArch Arch) { bench.Start("textaddress") ctxt.textaddress() - bench.Start("typelink") - ctxt.typelink() bench.Start("buildinfo") ctxt.buildinfo() bench.Start("pclntab") diff --git a/src/cmd/link/internal/ld/pcln.go b/src/cmd/link/internal/ld/pcln.go index 2b3687c37e4a6a..08c4d4db830949 100644 --- a/src/cmd/link/internal/ld/pcln.go +++ b/src/cmd/link/internal/ld/pcln.go @@ -10,10 +10,12 @@ import ( "cmd/internal/sys" "cmd/link/internal/loader" "cmd/link/internal/sym" + "cmp" "fmt" "internal/abi" "internal/buildcfg" "path/filepath" + "slices" "strings" ) @@ -36,6 +38,7 @@ type pclntab struct { cutab loader.Sym filetab loader.Sym pctab loader.Sym + funcdata loader.Sym // The number of functions + number of TEXT sections - 1. This is such an // unexpected value because platforms that have more than one TEXT section @@ -52,13 +55,20 @@ type pclntab struct { // addGeneratedSym adds a generator symbol to pclntab, returning the new Sym. // It is the caller's responsibility to save the symbol in state. -func (state *pclntab) addGeneratedSym(ctxt *Link, name string, size int64, f generatorFunc) loader.Sym { +func (state *pclntab) addGeneratedSym(ctxt *Link, name string, size int64, align int32, f generatorFunc) loader.Sym { size = Rnd(size, int64(ctxt.Arch.PtrSize)) state.size += size s := ctxt.createGeneratorSymbol(name, 0, sym.SPCLNTAB, size, f) - ctxt.loader.SetAttrReachable(s, true) - ctxt.loader.SetCarrierSym(s, state.carrier) - ctxt.loader.SetAttrNotInSymbolTable(s, true) + ldr := ctxt.loader + ldr.SetSymAlign(s, align) + ldr.SetAttrReachable(s, true) + ldr.SetCarrierSym(s, state.carrier) + ldr.SetAttrNotInSymbolTable(s, true) + + if align > ldr.SymAlign(state.carrier) { + ldr.SetSymAlign(state.carrier, align) + } + return s } @@ -183,7 +193,7 @@ func genInlTreeSym(ctxt *Link, cu *sym.CompilationUnit, fi loader.FuncInfo, arch // signal to the symtab() phase that it needs to be grouped in with // other similar symbols (gcdata, etc); the dodata() phase will // eventually switch the type back to SRODATA. - inlTreeSym.SetType(sym.SGOFUNC) + inlTreeSym.SetType(sym.SPCLNTAB) ldr.SetAttrReachable(its, true) ldr.SetSymAlign(its, 4) // it has 32-bit fields ninl := fi.NumInlTree() @@ -243,7 +253,6 @@ func makeInlSyms(ctxt *Link, funcs []loader.Sym, nameOffsets map[loader.Sym]uint // generator to fill in its data later. func (state *pclntab) generatePCHeader(ctxt *Link) { ldr := ctxt.loader - textStartOff := int64(8 + 2*ctxt.Arch.PtrSize) size := int64(8 + 8*ctxt.Arch.PtrSize) writeHeader := func(ctxt *Link, s loader.Sym) { header := ctxt.loader.MakeSymbolUpdater(s) @@ -259,15 +268,12 @@ func (state *pclntab) generatePCHeader(ctxt *Link) { // Write header. // Keep in sync with runtime/symtab.go:pcHeader and package debug/gosym. - header.SetUint32(ctxt.Arch, 0, 0xfffffff1) + header.SetUint32(ctxt.Arch, 0, uint32(abi.CurrentPCLnTabMagic)) header.SetUint8(ctxt.Arch, 6, uint8(ctxt.Arch.MinLC)) header.SetUint8(ctxt.Arch, 7, uint8(ctxt.Arch.PtrSize)) off := header.SetUint(ctxt.Arch, 8, uint64(state.nfunc)) off = header.SetUint(ctxt.Arch, off, uint64(state.nfiles)) - if off != textStartOff { - panic(fmt.Sprintf("pcHeader textStartOff: %d != %d", off, textStartOff)) - } - off += int64(ctxt.Arch.PtrSize) // skip runtimeText relocation + off = header.SetUintptr(ctxt.Arch, off, 0) // unused off = writeSymOffset(off, state.funcnametab) off = writeSymOffset(off, state.cutab) off = writeSymOffset(off, state.filetab) @@ -278,10 +284,7 @@ func (state *pclntab) generatePCHeader(ctxt *Link) { } } - state.pcheader = state.addGeneratedSym(ctxt, "runtime.pcheader", size, writeHeader) - // Create the runtimeText relocation. - sb := ldr.MakeSymbolUpdater(state.pcheader) - sb.SetAddr(ctxt.Arch, textStartOff, ldr.Lookup("runtime.text", 0)) + state.pcheader = state.addGeneratedSym(ctxt, "runtime.pcheader", size, int32(ctxt.Arch.PtrSize), writeHeader) } // walkFuncs iterates over the funcs, calling a function for each unique @@ -330,7 +333,7 @@ func (state *pclntab) generateFuncnametab(ctxt *Link, funcs []loader.Sym) map[lo size += int64(len(ctxt.loader.SymName(s)) + 1) // NULL terminate }) - state.funcnametab = state.addGeneratedSym(ctxt, "runtime.funcnametab", size, writeFuncNameTab) + state.funcnametab = state.addGeneratedSym(ctxt, "runtime.funcnametab", size, 1, writeFuncNameTab) return nameOffsets } @@ -446,7 +449,7 @@ func (state *pclntab) generateFilenameTabs(ctxt *Link, compUnits []*sym.Compilat } } } - state.cutab = state.addGeneratedSym(ctxt, "runtime.cutab", int64(totalEntries*4), writeCutab) + state.cutab = state.addGeneratedSym(ctxt, "runtime.cutab", int64(totalEntries*4), 4, writeCutab) // Write filetab. writeFiletab := func(ctxt *Link, s loader.Sym) { @@ -458,7 +461,7 @@ func (state *pclntab) generateFilenameTabs(ctxt *Link, compUnits []*sym.Compilat } } state.nfiles = uint32(len(fileOffsets)) - state.filetab = state.addGeneratedSym(ctxt, "runtime.filetab", fileSize, writeFiletab) + state.filetab = state.addGeneratedSym(ctxt, "runtime.filetab", fileSize, 1, writeFiletab) return cuOffsets } @@ -522,7 +525,158 @@ func (state *pclntab) generatePctab(ctxt *Link, funcs []loader.Sym) { } } - state.pctab = state.addGeneratedSym(ctxt, "runtime.pctab", size, writePctab) + state.pctab = state.addGeneratedSym(ctxt, "runtime.pctab", size, 1, writePctab) +} + +// generateFuncdata writes out the funcdata information. +func (state *pclntab) generateFuncdata(ctxt *Link, funcs []loader.Sym, inlsyms map[loader.Sym]loader.Sym) { + ldr := ctxt.loader + + // Walk the functions and collect the funcdata. + seen := make(map[loader.Sym]struct{}, len(funcs)) + fdSyms := make([]loader.Sym, 0, len(funcs)) + fd := []loader.Sym{} + for _, s := range funcs { + fi := ldr.FuncInfo(s) + if !fi.Valid() { + continue + } + fi.Preload() + fd := funcData(ldr, s, fi, inlsyms[s], fd) + for j, fdSym := range fd { + if ignoreFuncData(ldr, s, j, fdSym) { + continue + } + + if _, ok := seen[fdSym]; !ok { + fdSyms = append(fdSyms, fdSym) + seen[fdSym] = struct{}{} + } + } + } + seen = nil + + // Sort the funcdata in reverse order by alignment + // to minimize alignment gaps. Use a stable sort + // for reproducible results. + var maxAlign int32 + slices.SortStableFunc(fdSyms, func(a, b loader.Sym) int { + aAlign := symalign(ldr, a) + bAlign := symalign(ldr, b) + + // Remember maximum alignment. + maxAlign = max(maxAlign, aAlign, bAlign) + + // Negate to sort by decreasing alignment. + return -cmp.Compare(aAlign, bAlign) + }) + + // We will output the symbols in the order of fdSyms. + // Set the value of each symbol to its offset in the funcdata. + // This way when writeFuncs writes out the funcdata offset, + // it can simply write out the symbol value. + + // Accumulated size of funcdata info. + size := int64(0) + + for _, fdSym := range fdSyms { + datSize := ldr.SymSize(fdSym) + if datSize == 0 { + ctxt.Errorf(fdSym, "zero size funcdata") + continue + } + + size = Rnd(size, int64(symalign(ldr, fdSym))) + ldr.SetSymValue(fdSym, size) + size += datSize + + // We do not put the funcdata symbols in the symbol table. + ldr.SetAttrNotInSymbolTable(fdSym, true) + + // Mark the symbol as special so that it does not get + // adjusted by the section offset. + ldr.SetAttrSpecial(fdSym, true) + } + + // Funcdata symbols are permitted to have R_ADDROFF relocations, + // which the linker can fully resolve. + resolveRelocs := func(ldr *loader.Loader, fdSym loader.Sym, data []byte) { + relocs := ldr.Relocs(fdSym) + for i := 0; i < relocs.Count(); i++ { + r := relocs.At(i) + if r.Type() != objabi.R_ADDROFF { + ctxt.Errorf(fdSym, "unsupported reloc %d (%s) for funcdata symbol", r.Type(), sym.RelocName(ctxt.Target.Arch, r.Type())) + return + } + if r.Siz() != 4 { + ctxt.Errorf(fdSym, "unsupported ADDROFF reloc size %d for funcdata symbol", r.Siz()) + return + } + rs := r.Sym() + if r.Weak() && !ldr.AttrReachable(rs) { + return + } + sect := ldr.SymSect(rs) + if sect == nil { + ctxt.Errorf(fdSym, "missing section for relocation target %s for funcdata symbol", ldr.SymName(rs)) + } + o := ldr.SymValue(rs) + if sect.Name != ".text" { + o -= int64(sect.Vaddr) + } else { + // With multiple .text sections the offset + // is from the start of the first one. + o -= int64(Segtext.Sections[0].Vaddr) + if ctxt.Target.IsWasm() { + if o&(1<<16-1) != 0 { + ctxt.Errorf(fdSym, "textoff relocation does not target function entry for funcdata symbol: %s %#x", ldr.SymName(rs), o) + } + o >>= 16 + } + } + o += r.Add() + if o != int64(int32(o)) && o != int64(uint32(o)) { + ctxt.Errorf(fdSym, "ADDROFF relocation out of range for funcdata symbol: %#x", o) + } + ctxt.Target.Arch.ByteOrder.PutUint32(data[r.Off():], uint32(o)) + } + } + + writeFuncData := func(ctxt *Link, s loader.Sym) { + ldr := ctxt.loader + sb := ldr.MakeSymbolUpdater(s) + for _, fdSym := range fdSyms { + off := ldr.SymValue(fdSym) + fdSymData := ldr.Data(fdSym) + sb.SetBytesAt(off, fdSymData) + // Resolve any R_ADDROFF relocations. + resolveRelocs(ldr, fdSym, sb.Data()[off:off+int64(len(fdSymData))]) + } + } + + state.funcdata = state.addGeneratedSym(ctxt, "go:func.*", size, maxAlign, writeFuncData) + + // Because the funcdata previously was not in pclntab, + // we need to keep the visible symbol so that tools can find it. + ldr.SetAttrNotInSymbolTable(state.funcdata, false) +} + +// ignoreFuncData reports whether we should ignore a funcdata symbol. +// +// cmd/internal/obj optimistically populates ArgsPointerMaps and +// ArgInfo for assembly functions, hoping that the compiler will +// emit appropriate symbols from their Go stub declarations. If +// it didn't though, just ignore it. +// +// TODO(cherryyz): Fix arg map generation (see discussion on CL 523335). +func ignoreFuncData(ldr *loader.Loader, s loader.Sym, j int, fdSym loader.Sym) bool { + if fdSym == 0 { + return true + } + if (j == abi.FUNCDATA_ArgsPointerMaps || j == abi.FUNCDATA_ArgInfo) && ldr.IsFromAssembly(s) && ldr.Data(fdSym) == nil { + return true + } + return false } // numPCData returns the number of PCData syms for the FuncInfo. @@ -556,7 +710,7 @@ func (state *pclntab) generateFunctab(ctxt *Link, funcs []loader.Sym, inlSyms ma writePCToFunc(ctxt, sb, funcs, startLocations) writeFuncs(ctxt, sb, funcs, inlSyms, startLocations, cuOffsets, nameOffsets) } - state.pclntab = state.addGeneratedSym(ctxt, "runtime.functab", size, writePcln) + state.pclntab = state.addGeneratedSym(ctxt, "runtime.functab", size, 4, writePcln) } // funcData returns the funcdata and offsets for the FuncInfo. @@ -663,8 +817,6 @@ func writePCToFunc(ctxt *Link, sb *loader.SymbolBuilder, funcs []loader.Sym, sta func writeFuncs(ctxt *Link, sb *loader.SymbolBuilder, funcs []loader.Sym, inlSyms map[loader.Sym]loader.Sym, startLocations, cuOffsets []uint32, nameOffsets map[loader.Sym]uint32) { ldr := ctxt.loader deferReturnSym := ldr.Lookup("runtime.deferreturn", abiInternalVer) - gofunc := ldr.Lookup("go:func.*", 0) - gofuncBase := ldr.SymValue(gofunc) textStart := ldr.SymValue(ldr.Lookup("runtime.text", 0)) funcdata := []loader.Sym{} var pcsp, pcfile, pcline, pcinline loader.Sym @@ -762,25 +914,12 @@ func writeFuncs(ctxt *Link, sb *loader.SymbolBuilder, funcs []loader.Sym, inlSym dataoff := off + int64(4*j) fdsym := funcdata[j] - // cmd/internal/obj optimistically populates ArgsPointerMaps and - // ArgInfo for assembly functions, hoping that the compiler will - // emit appropriate symbols from their Go stub declarations. If - // it didn't though, just ignore it. - // - // TODO(cherryyz): Fix arg map generation (see discussion on CL 523335). - if fdsym != 0 && (j == abi.FUNCDATA_ArgsPointerMaps || j == abi.FUNCDATA_ArgInfo) && ldr.IsFromAssembly(s) && ldr.Data(fdsym) == nil { - fdsym = 0 - } - - if fdsym == 0 { + if ignoreFuncData(ldr, s, j, fdsym) { sb.SetUint32(ctxt.Arch, dataoff, ^uint32(0)) // ^0 is a sentinel for "no value" continue } - if outer := ldr.OuterSym(fdsym); outer != gofunc { - panic(fmt.Sprintf("bad carrier sym for symbol %s (funcdata %s#%d), want go:func.* got %s", ldr.SymName(fdsym), ldr.SymName(s), j, ldr.SymName(outer))) - } - sb.SetUint32(ctxt.Arch, dataoff, uint32(ldr.SymValue(fdsym)-gofuncBase)) + sb.SetUint32(ctxt.Arch, dataoff, uint32(ldr.SymValue(fdsym))) } } } @@ -823,6 +962,9 @@ func (ctxt *Link) pclntab(container loader.Bitmap) *pclntab { // function table, alternating PC and offset to func struct [each entry thearch.ptrsize bytes] // end PC [thearch.ptrsize bytes] // func structures, pcdata offsets, func data. + // + // runtime.funcdata + // []byte of deduplicated funcdata state, compUnits, funcs := makePclntab(ctxt, container) @@ -832,12 +974,17 @@ func (ctxt *Link) pclntab(container loader.Bitmap) *pclntab { ldr.SetAttrReachable(state.carrier, true) setCarrierSym(sym.SPCLNTAB, state.carrier) + // Aign pclntab to at least a pointer boundary, + // for pcHeader. This may be raised further by subsymbols. + ldr.SetSymAlign(state.carrier, int32(ctxt.Arch.PtrSize)) + state.generatePCHeader(ctxt) nameOffsets := state.generateFuncnametab(ctxt, funcs) cuOffsets := state.generateFilenameTabs(ctxt, compUnits, funcs) state.generatePctab(ctxt, funcs) inlSyms := makeInlSyms(ctxt, funcs, nameOffsets) state.generateFunctab(ctxt, funcs, inlSyms, cuOffsets, nameOffsets) + state.generateFuncdata(ctxt, funcs, inlSyms) return state } @@ -939,7 +1086,8 @@ func (ctxt *Link) findfunctab(state *pclntab, container loader.Bitmap) { } } - state.findfunctab = ctxt.createGeneratorSymbol("runtime.findfunctab", 0, sym.SRODATA, size, writeFindFuncTab) + state.findfunctab = ctxt.createGeneratorSymbol("runtime.findfunctab", 0, sym.SPCLNTAB, size, writeFindFuncTab) + ldr.SetSymAlign(state.findfunctab, 4) ldr.SetAttrReachable(state.findfunctab, true) ldr.SetAttrLocal(state.findfunctab, true) } diff --git a/src/cmd/link/internal/ld/pe.go b/src/cmd/link/internal/ld/pe.go index f5b7580fda3307..8376ddefe56bb7 100644 --- a/src/cmd/link/internal/ld/pe.go +++ b/src/cmd/link/internal/ld/pe.go @@ -151,9 +151,139 @@ const ( IMAGE_REL_BASED_DIR64 = 10 ) +// IMAGE_LOAD_CONFIG_DIRECTORY64.GuardFlags and IMAGE_LOAD_CONFIG_DIRECTORY32.GuardFlags +// values. These can be combined together. const ( - PeMinimumTargetMajorVersion = 6 - PeMinimumTargetMinorVersion = 1 + IMAGE_GUARD_CF_INSTRUMENTED = 0x00000100 // Module performs control flow integrity checks using system-supplied support + IMAGE_GUARD_CFW_INSTRUMENTED = 0x00000200 // Module performs control flow and write integrity checks + IMAGE_GUARD_CF_FUNCTION_TABLE_PRESENT = 0x00000400 // Module contains valid control flow target metadata + IMAGE_GUARD_SECURITY_COOKIE_UNUSED = 0x00000800 // Module does not make use of the /GS security cookie + IMAGE_GUARD_PROTECT_DELAYLOAD_IAT = 0x00001000 // Module supports read only delay load IAT + IMAGE_GUARD_DELAYLOAD_IAT_IN_ITS_OWN_SECTION = 0x00002000 // Delayload import table in its own .didat section (with nothing else in it) that can be freely reprotected + IMAGE_GUARD_CF_EXPORT_SUPPRESSION_INFO_PRESENT = 0x00004000 // Module contains suppressed export information + IMAGE_GUARD_CF_ENABLE_EXPORT_SUPPRESSION = 0x00008000 // Module enables suppression of exports + IMAGE_GUARD_CF_LONGJUMP_TABLE_PRESENT = 0x00010000 // Module contains longjmp target information + IMAGE_GUARD_RF_INSTRUMENTED = 0x00020000 // Module contains return flow instrumentation and metadata + IMAGE_GUARD_RF_ENABLE = 0x00040000 // Module requests that the OS enable return flow protection + IMAGE_GUARD_RF_STRICT = 0x00080000 // Module requests that the OS enable return flow protection in strict mode + IMAGE_GUARD_CF_FUNCTION_TABLE_SIZE_MASK = 0xF0000000 // Stride of Guard CF function table encoded in these bits (additional count of bytes per element) + IMAGE_GUARD_CF_FUNCTION_TABLE_SIZE_SHIFT = 28 // Shift to right-justify Guard CF function table stride +) + +type IMAGE_LOAD_CONFIG_CODE_INTEGRITY struct { + Flags uint16 + Catalog uint16 + CatalogOffset uint32 + Reserved uint32 +} + +type IMAGE_LOAD_CONFIG_DIRECTORY32 struct { + Size uint32 + TimeDateStamp uint32 + MajorVersion uint16 + MinorVersion uint16 + GlobalFlagsClear uint32 + GlobalFlagsSet uint32 + CriticalSectionDefaultTimeout uint32 + DeCommitFreeBlockThreshold uint32 + DeCommitTotalFreeThreshold uint32 + LockPrefixTable uint32 + MaximumAllocationSize uint32 + VirtualMemoryThreshold uint32 + ProcessHeapFlags uint32 + ProcessAffinityMask uint32 + CSDVersion uint16 + DependentLoadFlags uint16 + EditList uint32 + SecurityCookie uint32 + SEHandlerTable uint32 + SEHandlerCount uint32 + GuardCFCheckFunctionPointer uint32 + GuardCFDispatchFunctionPointer uint32 + GuardCFFunctionTable uint32 + GuardCFFunctionCount uint32 + GuardFlags uint32 + CodeIntegrity IMAGE_LOAD_CONFIG_CODE_INTEGRITY + GuardAddressTakenIatEntryTable uint32 + GuardAddressTakenIatEntryCount uint32 + GuardLongJumpTargetTable uint32 + GuardLongJumpTargetCount uint32 + DynamicValueRelocTable uint32 + CHPEMetadataPointer uint32 + GuardRFFailureRoutine uint32 + GuardRFFailureRoutineFunctionPointer uint32 + DynamicValueRelocTableOffset uint32 + DynamicValueRelocTableSection uint16 + Reserved2 uint16 + GuardRFVerifyStackPointerFunctionPointer uint32 + HotPatchTableOffset uint32 + Reserved3 uint32 + EnclaveConfigurationPointer uint32 + VolatileMetadataPointer uint32 + GuardEHContinuationTable uint32 + GuardEHContinuationCount uint32 + GuardXFGCheckFunctionPointer uint32 + GuardXFGDispatchFunctionPointer uint32 + GuardXFGTableDispatchFunctionPointer uint32 + CastGuardOsDeterminedFailureMode uint32 + GuardMemcpyFunctionPointer uint32 +} + +type IMAGE_LOAD_CONFIG_DIRECTORY64 struct { + Size uint32 + TimeDateStamp uint32 + MajorVersion uint16 + MinorVersion uint16 + GlobalFlagsClear uint32 + GlobalFlagsSet uint32 + CriticalSectionDefaultTimeout uint32 + DeCommitFreeBlockThreshold uint64 + DeCommitTotalFreeThreshold uint64 + LockPrefixTable uint64 + MaximumAllocationSize uint64 + VirtualMemoryThreshold uint64 + ProcessAffinityMask uint64 + ProcessHeapFlags uint32 + CSDVersion uint16 + DependentLoadFlags uint16 + EditList uint64 + SecurityCookie uint64 + SEHandlerTable uint64 + SEHandlerCount uint64 + GuardCFCheckFunctionPointer uint64 + GuardCFDispatchFunctionPointer uint64 + GuardCFFunctionTable uint64 + GuardCFFunctionCount uint64 + GuardFlags uint32 + CodeIntegrity IMAGE_LOAD_CONFIG_CODE_INTEGRITY + GuardAddressTakenIatEntryTable uint64 + GuardAddressTakenIatEntryCount uint64 + GuardLongJumpTargetTable uint64 + GuardLongJumpTargetCount uint64 + DynamicValueRelocTable uint64 + CHPEMetadataPointer uint64 + GuardRFFailureRoutine uint64 + GuardRFFailureRoutineFunctionPointer uint64 + DynamicValueRelocTableOffset uint32 + DynamicValueRelocTableSection uint16 + Reserved2 uint16 + GuardRFVerifyStackPointerFunctionPointer uint64 + HotPatchTableOffset uint32 + Reserved3 uint32 + EnclaveConfigurationPointer uint64 + VolatileMetadataPointer uint64 + GuardEHContinuationTable uint64 + GuardEHContinuationCount uint64 + GuardXFGCheckFunctionPointer uint64 + GuardXFGDispatchFunctionPointer uint64 + GuardXFGTableDispatchFunctionPointer uint64 + CastGuardOsDeterminedFailureMode uint64 + GuardMemcpyFunctionPointer uint64 +} + +const ( + PeMinimumTargetMajorVersion = 10 + PeMinimumTargetMinorVersion = 0 ) // DOS stub that prints out @@ -807,7 +937,8 @@ func (f *peFile) writeSymbols(ctxt *Link) { } } class := IMAGE_SYM_CLASS_EXTERNAL - if ldr.IsFileLocal(s) || ldr.AttrVisibilityHidden(s) || ldr.AttrLocal(s) { + if ldr.IsFileLocal(s) || ldr.AttrVisibilityHidden(s) || ldr.AttrLocal(s) || + (ldr.IsContentHashed(s) && ldr.SymType(s).IsText()) { class = IMAGE_SYM_CLASS_STATIC } f.writeSymbol(ctxt.Out, ldr, s, name, value, sect, peSymType, uint8(class)) @@ -854,7 +985,7 @@ func (f *peFile) writeSymbols(ctxt *Link) { continue } t := ldr.SymType(s) - if t >= sym.SELFRXSECT && t < sym.SXREF { // data sections handled in dodata + if t >= sym.SELFRXSECT && t < sym.SFirstUnallocated { // data sections handled in dodata if t == sym.STLSBSS { continue } @@ -1141,6 +1272,29 @@ func Peinit(ctxt *Link) { ctxt.loader.SetAttrSpecial(sb.Sym(), true) ctxt.loader.SetAttrLocal(sb.Sym(), true) } + + // The _load_config_used symbol is required to be present on modern + // Windows. We later wire this up to the PE data directory. + sb := ctxt.loader.CreateSymForUpdate("_load_config_used", 0) + sb.SetType(sym.SRODATA) + sb.SetAlign(int32(ctxt.Arch.PtrSize)) + var buf bytes.Buffer + if pe64 { + lc := IMAGE_LOAD_CONFIG_DIRECTORY64{ + Size: uint32(binary.Size(&IMAGE_LOAD_CONFIG_DIRECTORY64{})), + GuardFlags: IMAGE_GUARD_SECURITY_COOKIE_UNUSED, + } + binary.Write(&buf, binary.LittleEndian, &lc) + } else { + lc := IMAGE_LOAD_CONFIG_DIRECTORY32{ + Size: uint32(binary.Size(&IMAGE_LOAD_CONFIG_DIRECTORY32{})), + GuardFlags: IMAGE_GUARD_SECURITY_COOKIE_UNUSED, + } + binary.Write(&buf, binary.LittleEndian, &lc) + } + sb.SetData(buf.Bytes()) + sb.SetSize(int64(buf.Len())) + ctxt.loader.SetAttrReachable(sb.Sym(), true) } HEADR = PEFILEHEADR @@ -1635,7 +1789,6 @@ func addPEBaseReloc(ctxt *Link) { func (ctxt *Link) dope() { initdynimport(ctxt) initdynexport(ctxt) - writeSEH(ctxt) } func setpersrc(ctxt *Link, syms []loader.Sym) { @@ -1712,6 +1865,14 @@ func asmbPe(ctxt *Link) { ro.checkSegment(&Segrodata) pefile.rdataSect = ro + // This should have been added in Peinit and by now is part of the + // just-written .rdata section. + s := ctxt.loader.Lookup("_load_config_used", 0) + if s != 0 { + pefile.dataDirectory[pe.IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG].VirtualAddress = uint32(ctxt.loader.SymValue(s) - PEBASE) + pefile.dataDirectory[pe.IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG].Size = uint32(ctxt.loader.SymSize(s)) + } + var d *peSection if ctxt.LinkMode != LinkExternal { d = pefile.addSection(".data", int(Segdata.Length), int(Segdata.Filelen)) @@ -1759,7 +1920,7 @@ func peCreateExportFile(ctxt *Link, libName string) (fname string) { var buf bytes.Buffer if ctxt.BuildMode == BuildModeCShared { - fmt.Fprintf(&buf, "LIBRARY %s\n", libName) + fmt.Fprintf(&buf, "LIBRARY %q\n", libName) } buf.WriteString("EXPORTS\n") diff --git a/src/cmd/link/internal/ld/seh.go b/src/cmd/link/internal/ld/seh.go index 9f0f747c042b15..2bee6d4cf7a97a 100644 --- a/src/cmd/link/internal/ld/seh.go +++ b/src/cmd/link/internal/ld/seh.go @@ -8,6 +8,8 @@ import ( "cmd/internal/sys" "cmd/link/internal/loader" "cmd/link/internal/sym" + "cmp" + "slices" ) var sehp struct { @@ -15,14 +17,16 @@ var sehp struct { xdata []sym.LoaderSym } -func writeSEH(ctxt *Link) { +// collectSEH collects the SEH unwind information for all functions and organizes +// it into .pdata and .xdata sections. +func collectSEH(ctxt *Link) { switch ctxt.Arch.Family { case sys.AMD64: - writeSEHAMD64(ctxt) + collectSEHAMD64(ctxt) } } -func writeSEHAMD64(ctxt *Link) { +func collectSEHAMD64(ctxt *Link) { ldr := ctxt.loader mkSecSym := func(name string, kind sym.SymKind) *loader.SymbolBuilder { s := ldr.CreateSymForUpdate(name, 0) @@ -39,6 +43,11 @@ func writeSEHAMD64(ctxt *Link) { // an RVA, so it is possible, and binary-size wise, // to deduplicate .xdata entries. uwcache := make(map[string]int64) // aux symbol name --> .xdata offset + type pdataEntry struct { + start sym.LoaderSym + xdataOff int64 + } + var entries []pdataEntry for _, s := range ctxt.Textp { if fi := ldr.FuncInfo(s); !fi.Valid() { continue @@ -66,12 +75,22 @@ func writeSEHAMD64(ctxt *Link) { } } + entries = append(entries, pdataEntry{start: s, xdataOff: off}) + } + slices.SortFunc(entries, func(a, b pdataEntry) int { + return cmp.Compare(ldr.SymAddr(a.start), ldr.SymAddr(b.start)) + }) + for _, ent := range entries { // Reference: // https://learn.microsoft.com/en-us/cpp/build/exception-handling-x64#struct-runtime_function - pdata.AddPEImageRelativeAddrPlus(ctxt.Arch, s, 0) - pdata.AddPEImageRelativeAddrPlus(ctxt.Arch, s, ldr.SymSize(s)) - pdata.AddPEImageRelativeAddrPlus(ctxt.Arch, xdata.Sym(), off) + pdata.AddPEImageRelativeAddrPlus(ctxt.Arch, ent.start, 0) // function start address + pdata.AddPEImageRelativeAddrPlus(ctxt.Arch, ent.start, ldr.SymSize(ent.start)) // function end address + pdata.AddPEImageRelativeAddrPlus(ctxt.Arch, xdata.Sym(), ent.xdataOff) // xdata symbol offset + } + if pdata.Size() > 0 { + sehp.pdata = append(sehp.pdata, pdata.Sym()) + } + if xdata.Size() > 0 { + sehp.xdata = append(sehp.xdata, xdata.Sym()) } - sehp.pdata = append(sehp.pdata, pdata.Sym()) - sehp.xdata = append(sehp.xdata, xdata.Sym()) } diff --git a/src/cmd/link/internal/ld/symtab.go b/src/cmd/link/internal/ld/symtab.go index 2c999ccc4e3a19..e1bddecb708460 100644 --- a/src/cmd/link/internal/ld/symtab.go +++ b/src/cmd/link/internal/ld/symtab.go @@ -101,7 +101,7 @@ func putelfsym(ctxt *Link, x loader.Sym, typ elf.SymType, curbind elf.SymBind) { ldr.Errorf(x, "missing ELF section in putelfsym") return } - elfshnum = xosect.Elfsect.(*ElfShdr).shnum + elfshnum = elfShdrShnum(xosect.Elfsect.(*ElfShdr)) } sname := ldr.SymExtname(x) @@ -110,9 +110,12 @@ func putelfsym(ctxt *Link, x loader.Sym, typ elf.SymType, curbind elf.SymBind) { // One pass for each binding: elf.STB_LOCAL, elf.STB_GLOBAL, // maybe one day elf.STB_WEAK. bind := elf.STB_GLOBAL - if ldr.IsFileLocal(x) && !isStaticTmp(sname) || ldr.AttrVisibilityHidden(x) || ldr.AttrLocal(x) { + if ldr.IsFileLocal(x) && !isStaticTmp(sname) || ldr.AttrVisibilityHidden(x) || ldr.AttrLocal(x) || + (ldr.IsContentHashed(x) && ldr.SymType(x).IsText()) { // Static tmp is package local, but a package can be shared among multiple DSOs. // They need to have a single view of the static tmp that are writable. + // Content-hashed text symbols may have the same name. Mark them local to avoid + // collision. bind = elf.STB_LOCAL } @@ -244,7 +247,7 @@ func genelfsym(ctxt *Link, elfbind elf.SymBind) { continue } st := ldr.SymType(s) - if st >= sym.SELFRXSECT && st < sym.SXREF { + if st >= sym.SELFRXSECT && st < sym.SFirstUnallocated { typ := elf.STT_OBJECT if st == sym.STLSBSS { if ctxt.IsInternal() { @@ -345,7 +348,7 @@ func asmbPlan9Sym(ctxt *Link) { continue } t := ldr.SymType(s) - if t >= sym.SELFRXSECT && t < sym.SXREF { // data sections handled in dodata + if t >= sym.SELFRXSECT && t < sym.SFirstUnallocated { // data sections handled in dodata if t == sym.STLSBSS { continue } @@ -442,11 +445,11 @@ func (ctxt *Link) symtab(pcln *pclntab) []sym.SymKind { ctxt.xdefine("runtime.ebss", sym.SBSS, 0) ctxt.xdefine("runtime.noptrbss", sym.SNOPTRBSS, 0) ctxt.xdefine("runtime.enoptrbss", sym.SNOPTRBSS, 0) + ctxt.xdefine("runtime.gcmask.*", sym.SNOPTRBSS, 0) ctxt.xdefine("runtime.covctrs", sym.SNOPTRBSS, 0) ctxt.xdefine("runtime.ecovctrs", sym.SNOPTRBSS, 0) ctxt.xdefine("runtime.end", sym.SBSS, 0) ctxt.xdefine("runtime.epclntab", sym.SRODATA, 0) - ctxt.xdefine("runtime.esymtab", sym.SRODATA, 0) // garbage collection symbols s := ldr.CreateSymForUpdate("runtime.gcdata", 0) @@ -460,31 +463,12 @@ func (ctxt *Link) symtab(pcln *pclntab) []sym.SymKind { ctxt.xdefine("runtime.egcbss", sym.SRODATA, 0) // pseudo-symbols to mark locations of type, string, and go string data. - var symtype, symtyperel loader.Sym - if !ctxt.DynlinkingGo() { - if ctxt.UseRelro() && (ctxt.BuildMode == BuildModeCArchive || ctxt.BuildMode == BuildModeCShared || ctxt.BuildMode == BuildModePIE) { - s = ldr.CreateSymForUpdate("type:*", 0) - s.SetType(sym.STYPE) - s.SetSize(0) - s.SetAlign(int32(ctxt.Arch.PtrSize)) - symtype = s.Sym() - - s = ldr.CreateSymForUpdate("typerel.*", 0) - s.SetType(sym.STYPERELRO) - s.SetSize(0) - s.SetAlign(int32(ctxt.Arch.PtrSize)) - symtyperel = s.Sym() - } else { - s = ldr.CreateSymForUpdate("type:*", 0) - s.SetType(sym.STYPE) - s.SetSize(0) - s.SetAlign(int32(ctxt.Arch.PtrSize)) - symtype = s.Sym() - symtyperel = s.Sym() - } - setCarrierSym(sym.STYPE, symtype) - setCarrierSym(sym.STYPERELRO, symtyperel) - } + s = ldr.CreateSymForUpdate("type:*", 0) + s.SetType(sym.STYPE) + s.SetSize(0) + s.SetAlign(int32(ctxt.Arch.PtrSize)) + symtype := s.Sym() + setCarrierSym(sym.STYPE, symtype) groupSym := func(name string, t sym.SymKind) loader.Sym { s := ldr.CreateSymForUpdate(name, 0) @@ -497,20 +481,11 @@ func (ctxt *Link) symtab(pcln *pclntab) []sym.SymKind { } var ( symgostring = groupSym("go:string.*", sym.SGOSTRING) - symgofunc = groupSym("go:func.*", sym.SGOFUNC) + symgofunc = groupSym("go:funcdesc", sym.SGOFUNC) symgcbits = groupSym("runtime.gcbits.*", sym.SGCBITS) + symgcmask = groupSym("runtime.gcmask.*", sym.SGCMASK) ) - symgofuncrel := symgofunc - if ctxt.UseRelro() { - symgofuncrel = groupSym("go:funcrel.*", sym.SGOFUNCRELRO) - } - - symt := ldr.CreateSymForUpdate("runtime.symtab", 0) - symt.SetType(sym.SSYMTAB) - symt.SetSize(0) - symt.SetLocal(true) - // assign specific types so that they sort together. // within a type they sort by size, so the .* symbols // just defined above will be first. @@ -523,7 +498,19 @@ func (ctxt *Link) symtab(pcln *pclntab) []sym.SymKind { if (!ctxt.IsExternal() && ldr.IsFileLocal(s) && !ldr.IsFromAssembly(s) && ldr.SymPkg(s) != "") || (ctxt.LinkMode == LinkInternal && ldr.SymType(s) == sym.SCOVERAGE_COUNTER) { ldr.SetAttrNotInSymbolTable(s, true) } - if !ldr.AttrReachable(s) || ldr.AttrSpecial(s) || (ldr.SymType(s) != sym.SRODATA && ldr.SymType(s) != sym.SGOFUNC) { + + if !ldr.AttrReachable(s) || ldr.AttrSpecial(s) { + continue + } + + if ldr.SymType(s) == sym.SNOPTRBSS && strings.HasPrefix(ldr.SymName(s), "type:.gcmask.") { + symGroupType[s] = sym.SGCMASK + ldr.SetAttrNotInSymbolTable(s, true) + ldr.SetCarrierSym(s, symgcmask) + continue + } + + if ldr.SymType(s) != sym.SRODATA && ldr.SymType(s) != sym.SGOFUNC { continue } @@ -534,8 +521,7 @@ func (ctxt *Link) symtab(pcln *pclntab) []sym.SymKind { ldr.SetAttrNotInSymbolTable(s, true) ldr.SetCarrierSym(s, symgostring) - case strings.HasPrefix(name, "runtime.gcbits."), - strings.HasPrefix(name, "type:.gcprog."): + case strings.HasPrefix(name, "runtime.gcbits."): symGroupType[s] = sym.SGCBITS ldr.SetAttrNotInSymbolTable(s, true) ldr.SetCarrierSym(s, symgcbits) @@ -543,54 +529,23 @@ func (ctxt *Link) symtab(pcln *pclntab) []sym.SymKind { case strings.HasSuffix(name, "·f"): if !ctxt.DynlinkingGo() { ldr.SetAttrNotInSymbolTable(s, true) - } - if ctxt.UseRelro() { - symGroupType[s] = sym.SGOFUNCRELRO - if !ctxt.DynlinkingGo() { - ldr.SetCarrierSym(s, symgofuncrel) - } - } else { - symGroupType[s] = sym.SGOFUNC ldr.SetCarrierSym(s, symgofunc) } - - case strings.HasPrefix(name, "gcargs."), - strings.HasPrefix(name, "gclocals."), - strings.HasPrefix(name, "gclocals·"), - ldr.SymType(s) == sym.SGOFUNC && s != symgofunc, // inltree, see pcln.go - strings.HasSuffix(name, ".opendefer"), - strings.HasSuffix(name, ".arginfo0"), - strings.HasSuffix(name, ".arginfo1"), - strings.HasSuffix(name, ".argliveinfo"), - strings.HasSuffix(name, ".wrapinfo"), - strings.HasSuffix(name, ".args_stackmap"), - strings.HasSuffix(name, ".stkobj"): - ldr.SetAttrNotInSymbolTable(s, true) symGroupType[s] = sym.SGOFUNC - ldr.SetCarrierSym(s, symgofunc) - if ctxt.Debugvlog != 0 { - align := ldr.SymAlign(s) - liveness += (ldr.SymSize(s) + int64(align) - 1) &^ (int64(align) - 1) - } - // Note: Check for "type:" prefix after checking for .arginfo1 suffix. - // That way symbols like "type:.eq.[2]interface {}.arginfo1" that belong - // in go:func.* end up there. case strings.HasPrefix(name, "type:"): if !ctxt.DynlinkingGo() { ldr.SetAttrNotInSymbolTable(s, true) + ldr.SetCarrierSym(s, symtype) } - if ctxt.UseRelro() { - symGroupType[s] = sym.STYPERELRO - if symtyperel != 0 { - ldr.SetCarrierSym(s, symtyperel) - } - } else { - symGroupType[s] = sym.STYPE - if symtyperel != 0 { - ldr.SetCarrierSym(s, symtype) - } + symGroupType[s] = sym.STYPE + + case ldr.IsItab(s): + if !ctxt.DynlinkingGo() { + ldr.SetAttrNotInSymbolTable(s, true) + ldr.SetCarrierSym(s, symtype) } + symGroupType[s] = sym.STYPE } } @@ -681,9 +636,16 @@ func (ctxt *Link) symtab(pcln *pclntab) []sym.SymKind { moduledata.AddAddr(ctxt.Arch, ldr.Lookup("runtime.gcdata", 0)) moduledata.AddAddr(ctxt.Arch, ldr.Lookup("runtime.gcbss", 0)) moduledata.AddAddr(ctxt.Arch, ldr.Lookup("runtime.types", 0)) + ctxt.moduledataTypeDescOffset = moduledata.Size() + moduledata.AddUint(ctxt.Arch, 0) // filled in by dodataSect moduledata.AddAddr(ctxt.Arch, ldr.Lookup("runtime.etypes", 0)) + ctxt.moduledataItabOffset = moduledata.Size() + moduledata.AddUint(ctxt.Arch, 0) // filled in by dodataSect + ctxt.moduledataItabSizeOffset = moduledata.Size() + moduledata.AddUint(ctxt.Arch, 0) // filled in by dodataSect moduledata.AddAddr(ctxt.Arch, ldr.Lookup("runtime.rodata", 0)) moduledata.AddAddr(ctxt.Arch, ldr.Lookup("go:func.*", 0)) + moduledata.AddAddr(ctxt.Arch, ldr.Lookup("runtime.epclntab", 0)) if ctxt.IsAIX() && ctxt.IsExternal() { // Add R_XCOFFREF relocation to prevent ld's garbage collection of @@ -700,6 +662,7 @@ func (ctxt *Link) symtab(pcln *pclntab) []sym.SymKind { addRef("runtime.rodata") addRef("runtime.erodata") addRef("runtime.epclntab") + addRef("go:func.*") // As we use relative addressing for text symbols in functab, it is // important that the offsets we computed stay unchanged by the external // linker, i.e. all symbols in Textp should not be removed. @@ -722,16 +685,6 @@ func (ctxt *Link) symtab(pcln *pclntab) []sym.SymKind { // text section information slice(textsectionmapSym, uint64(nsections)) - // The typelinks slice - typelinkSym := ldr.Lookup("runtime.typelink", 0) - ntypelinks := uint64(ldr.SymSize(typelinkSym)) / 4 - slice(typelinkSym, ntypelinks) - - // The itablinks slice - itablinkSym := ldr.Lookup("runtime.itablink", 0) - nitablinks := uint64(ldr.SymSize(itablinkSym)) / uint64(ctxt.Arch.PtrSize) - slice(itablinkSym, nitablinks) - // The ptab slice if ptab := ldr.Lookup("go:plugin.tabs", 0); ptab != 0 && ldr.AttrReachable(ptab) { ldr.SetAttrLocal(ptab, true) @@ -843,7 +796,7 @@ func (ctxt *Link) symtab(pcln *pclntab) []sym.SymKind { } // CarrierSymByType tracks carrier symbols and their sizes. -var CarrierSymByType [sym.SXREF]struct { +var CarrierSymByType [sym.SFirstUnallocated]struct { Sym loader.Sym Size int64 } diff --git a/src/cmd/link/internal/ld/testdata/issue10978/main.s b/src/cmd/link/internal/ld/testdata/issue10978/main.s index 1d00e76c1dd31d..37759684ebbb55 100644 --- a/src/cmd/link/internal/ld/testdata/issue10978/main.s +++ b/src/cmd/link/internal/ld/testdata/issue10978/main.s @@ -1 +1 @@ -// This file is needed to make "go build" work for package with external functions. +// This file is needed to make "go build" work for package with external functions. diff --git a/src/cmd/link/internal/ld/typelink.go b/src/cmd/link/internal/ld/typelink.go deleted file mode 100644 index 966de5571c3077..00000000000000 --- a/src/cmd/link/internal/ld/typelink.go +++ /dev/null @@ -1,69 +0,0 @@ -// Copyright 2016 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -package ld - -import ( - "cmd/internal/objabi" - "cmd/link/internal/loader" - "cmd/link/internal/sym" - "slices" - "strings" -) - -type typelinkSortKey struct { - TypeStr string - Type loader.Sym -} - -// typelink generates the typelink table which is used by reflect.typelinks(). -// Types that should be added to the typelinks table are marked with the -// MakeTypelink attribute by the compiler. -func (ctxt *Link) typelink() { - ldr := ctxt.loader - var typelinks []typelinkSortKey - var itabs []loader.Sym - for s := loader.Sym(1); s < loader.Sym(ldr.NSym()); s++ { - if !ldr.AttrReachable(s) { - continue - } - if ldr.IsTypelink(s) { - typelinks = append(typelinks, typelinkSortKey{decodetypeStr(ldr, ctxt.Arch, s), s}) - } else if ldr.IsItab(s) { - itabs = append(itabs, s) - } - } - slices.SortFunc(typelinks, func(a, b typelinkSortKey) int { - return strings.Compare(a.TypeStr, b.TypeStr) - }) - - tl := ldr.CreateSymForUpdate("runtime.typelink", 0) - tl.SetType(sym.STYPELINK) - ldr.SetAttrLocal(tl.Sym(), true) - tl.SetSize(int64(4 * len(typelinks))) - tl.Grow(tl.Size()) - relocs := tl.AddRelocs(len(typelinks)) - for i, s := range typelinks { - r := relocs.At(i) - r.SetSym(s.Type) - r.SetOff(int32(i * 4)) - r.SetSiz(4) - r.SetType(objabi.R_ADDROFF) - } - - ptrsize := ctxt.Arch.PtrSize - il := ldr.CreateSymForUpdate("runtime.itablink", 0) - il.SetType(sym.SITABLINK) - ldr.SetAttrLocal(il.Sym(), true) - il.SetSize(int64(ptrsize * len(itabs))) - il.Grow(il.Size()) - relocs = il.AddRelocs(len(itabs)) - for i, s := range itabs { - r := relocs.At(i) - r.SetSym(s) - r.SetOff(int32(i * ptrsize)) - r.SetSiz(uint8(ptrsize)) - r.SetType(objabi.R_ADDR) - } -} diff --git a/src/cmd/link/internal/ld/util.go b/src/cmd/link/internal/ld/util.go index 556c77d7326258..f3787ff50b4293 100644 --- a/src/cmd/link/internal/ld/util.go +++ b/src/cmd/link/internal/ld/util.go @@ -32,7 +32,7 @@ func Exit(code int) { } // Exitf logs an error message then calls Exit(2). -func Exitf(format string, a ...interface{}) { +func Exitf(format string, a ...any) { fmt.Fprintf(os.Stderr, os.Args[0]+": "+format+"\n", a...) nerrors++ if *flagH { @@ -60,7 +60,7 @@ func afterErrorAction() { // // Logging an error means that on exit cmd/link will delete any // output file and return a non-zero error code. -func Errorf(format string, args ...interface{}) { +func Errorf(format string, args ...any) { format += "\n" fmt.Fprintf(os.Stderr, format, args...) afterErrorAction() @@ -72,7 +72,7 @@ func Errorf(format string, args ...interface{}) { // // Logging an error means that on exit cmd/link will delete any // output file and return a non-zero error code. -func (ctxt *Link) Errorf(s loader.Sym, format string, args ...interface{}) { +func (ctxt *Link) Errorf(s loader.Sym, format string, args ...any) { if ctxt.loader != nil { ctxt.loader.Errorf(s, format, args...) return diff --git a/src/cmd/link/internal/ld/xcoff.go b/src/cmd/link/internal/ld/xcoff.go index fdc16ac48f9d2b..4b5010eadec4f8 100644 --- a/src/cmd/link/internal/ld/xcoff.go +++ b/src/cmd/link/internal/ld/xcoff.go @@ -167,8 +167,7 @@ const ( ) // Type representing all XCOFF symbols. -type xcoffSym interface { -} +type xcoffSym any // Symbol Table Entry type XcoffSymEnt64 struct { @@ -584,34 +583,30 @@ func xcoffUpdateOuterSize(ctxt *Link, size int64, stype sym.SymKind) { switch stype { default: Errorf("unknown XCOFF outer symbol for type %s", stype.String()) - case sym.SRODATA, sym.SRODATARELRO, sym.SFUNCTAB, sym.SSTRING: + case sym.SRODATA, sym.SRODATARELRO, sym.SSTRING: // Nothing to do - case sym.STYPERELRO: - if ctxt.UseRelro() && (ctxt.BuildMode == BuildModeCArchive || ctxt.BuildMode == BuildModeCShared || ctxt.BuildMode == BuildModePIE) { - // runtime.types size must be removed, as it's a real symbol. - tsize := ldr.SymSize(ldr.Lookup("runtime.types", 0)) - outerSymSize["typerel.*"] = size - tsize - return - } - fallthrough case sym.STYPE: - if !ctxt.DynlinkingGo() { - // runtime.types size must be removed, as it's a real symbol. - tsize := ldr.SymSize(ldr.Lookup("runtime.types", 0)) - outerSymSize["type:*"] = size - tsize - } + // runtime.types size must be removed, as it's a real symbol. + tsize := ldr.SymSize(ldr.Lookup("runtime.types", 0)) + outerSymSize["type:*"] = size - tsize case sym.SGOSTRING: outerSymSize["go:string.*"] = size case sym.SGOFUNC: if !ctxt.DynlinkingGo() { - outerSymSize["go:func.*"] = size + outerSymSize["go:funcdesc"] = size } - case sym.SGOFUNCRELRO: - outerSymSize["go:funcrel.*"] = size case sym.SGCBITS: outerSymSize["runtime.gcbits.*"] = size case sym.SPCLNTAB: - outerSymSize["runtime.pclntab"] = size + // go:func.* size must be removed from pclntab, + // as it's a real symbol. Same for runtime.findfunctab. + fsize := ldr.SymSize(ldr.Lookup("go:func.*", 0)) + fft := ldr.Lookup("runtime.findfunctab", 0) + fsize = Rnd(fsize, int64(symalign(ldr, fft))) + tsize := ldr.SymSize(fft) + outerSymSize["runtime.pclntab"] = size - (fsize + tsize) + case sym.SGCMASK: + outerSymSize["runtime.gcmask.*"] = size } } @@ -834,7 +829,7 @@ func (f *xcoffFile) writeSymbolFunc(ctxt *Link, x loader.Sym) []xcoffSym { Nnumaux: 2, } - if ldr.IsFileLocal(x) || ldr.AttrVisibilityHidden(x) || ldr.AttrLocal(x) { + if ldr.IsFileLocal(x) || ldr.AttrVisibilityHidden(x) || ldr.AttrLocal(x) || ldr.IsContentHashed(x) { s.Nsclass = C_HIDEXT } @@ -954,7 +949,7 @@ func putaixsym(ctxt *Link, x loader.Sym, t SymbolType) { Xscnlenhi: uint32(size >> 32), } - if ty := ldr.SymType(x); ty >= sym.STYPE && ty <= sym.SPCLNTAB { + if ty := ldr.SymType(x); ty >= sym.SSTRING && ty <= sym.SPCLNTAB { if ctxt.IsExternal() && strings.HasPrefix(ldr.SymSect(x).Name, ".data.rel.ro") { // During external linking, read-only datas with relocation // must be in .data. @@ -1112,7 +1107,7 @@ func (f *xcoffFile) asmaixsym(ctxt *Link) { putaixsym(ctxt, s, TLSSym) } - case st == sym.SBSS, st == sym.SNOPTRBSS, st == sym.SLIBFUZZER_8BIT_COUNTER, st == sym.SCOVERAGE_COUNTER: + case st == sym.SBSS, st == sym.SNOPTRBSS, st == sym.SGCMASK, st == sym.SLIBFUZZER_8BIT_COUNTER, st == sym.SCOVERAGE_COUNTER: if ldr.AttrReachable(s) { data := ldr.Data(s) if len(data) > 0 { @@ -1121,7 +1116,7 @@ func (f *xcoffFile) asmaixsym(ctxt *Link) { putaixsym(ctxt, s, BSSSym) } - case st >= sym.SELFRXSECT && st < sym.SXREF: // data sections handled in dodata + case st >= sym.SELFRXSECT && st < sym.SFirstUnallocated: // data sections handled in dodata if ldr.AttrReachable(s) { putaixsym(ctxt, s, DataSym) } @@ -1255,7 +1250,7 @@ func Xcoffadddynrel(target *Target, ldr *loader.Loader, syms *ArchSyms, s loader break } } - } else if t := ldr.SymType(s); t.IsDATA() || t.IsNOPTRDATA() || t == sym.SBUILDINFO || t == sym.SXCOFFTOC { + } else if t := ldr.SymType(s); t.IsDATA() || t.IsNOPTRDATA() || t == sym.SBUILDINFO || t == sym.SXCOFFTOC || t == sym.SMODULEDATA { switch ldr.SymSect(targ).Seg { default: ldr.Errorf(s, "unknown segment for .loader relocation with symbol %s", ldr.SymName(targ)) @@ -1263,7 +1258,7 @@ func Xcoffadddynrel(target *Target, ldr *loader.Loader, syms *ArchSyms, s loader case &Segrodata: xldr.symndx = 0 // .text case &Segdata: - if targType == sym.SBSS || targType == sym.SNOPTRBSS { + if targType == sym.SBSS || targType == sym.SNOPTRBSS || targType == sym.SGCMASK { xldr.symndx = 2 // .bss } else { xldr.symndx = 1 // .data diff --git a/src/cmd/link/internal/loadelf/ldelf.go b/src/cmd/link/internal/loadelf/ldelf.go index 9434704be4dc99..50bce8613b92c8 100644 --- a/src/cmd/link/internal/loadelf/ldelf.go +++ b/src/cmd/link/internal/loadelf/ldelf.go @@ -242,7 +242,7 @@ func parseArmAttributes(e binary.ByteOrder, data []byte) (found bool, ehdrFlags // object, and the returned ehdrFlags contains what this Load function computes. // TODO: find a better place for this logic. func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, f *bio.Reader, pkg string, length int64, pn string, initEhdrFlags uint32) (textp []loader.Sym, ehdrFlags uint32, err error) { - errorf := func(str string, args ...interface{}) ([]loader.Sym, uint32, error) { + errorf := func(str string, args ...any) ([]loader.Sym, uint32, error) { return nil, 0, fmt.Errorf("loadelf: %s: %v", pn, fmt.Sprintf(str, args...)) } @@ -615,6 +615,14 @@ func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, f *bio.Reader, // Symbols generated by the relax feature of gcc and binutils on loong64. continue } + + if strings.HasPrefix(elfsym.name, "wm4.") || strings.HasPrefix(elfsym.name, "wm8.") { + // Symbols generated by GCC as + // group symbols to eliminate + // duplicate debug info for + // preprocessor symbols. + continue + } } if strings.HasPrefix(elfsym.name, ".Linfo_string") { @@ -627,7 +635,7 @@ func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, f *bio.Reader, continue } - return errorf("%v: sym#%d (%q): ignoring symbol in section %d (%q) (type %d)", elfsym.sym, i, elfsym.name, elfsym.shndx, sect.name, elfsym.type_) + return errorf("%v: sym#%d (%q): unrecognized symbol in section %d (%q) (type %d)", elfsym.sym, i, elfsym.name, elfsym.shndx, sect.name, elfsym.type_) } s := elfsym.sym @@ -1063,15 +1071,21 @@ func relSize(arch *sys.Arch, pn string, elftype uint32) (uint8, uint8, error) { LOONG64 | uint32(elf.R_LARCH_B26)<<16, LOONG64 | uint32(elf.R_LARCH_PCALA_HI20)<<16, LOONG64 | uint32(elf.R_LARCH_PCALA_LO12)<<16, + LOONG64 | uint32(elf.R_LARCH_PCALA64_HI12)<<16, + LOONG64 | uint32(elf.R_LARCH_PCALA64_LO20)<<16, LOONG64 | uint32(elf.R_LARCH_GOT_PC_HI20)<<16, LOONG64 | uint32(elf.R_LARCH_GOT_PC_LO12)<<16, - LOONG64 | uint32(elf.R_LARCH_32_PCREL)<<16: + LOONG64 | uint32(elf.R_LARCH_GOT64_PC_LO20)<<16, + LOONG64 | uint32(elf.R_LARCH_GOT64_PC_HI12)<<16, + LOONG64 | uint32(elf.R_LARCH_32_PCREL)<<16, + LOONG64 | uint32(elf.R_LARCH_PCREL20_S2)<<16: return 4, 4, nil case LOONG64 | uint32(elf.R_LARCH_64)<<16, LOONG64 | uint32(elf.R_LARCH_ADD64)<<16, LOONG64 | uint32(elf.R_LARCH_SUB64)<<16, - LOONG64 | uint32(elf.R_LARCH_64_PCREL)<<16: + LOONG64 | uint32(elf.R_LARCH_64_PCREL)<<16, + LOONG64 | uint32(elf.R_LARCH_CALL36)<<16: return 8, 8, nil case S390X | uint32(elf.R_390_8)<<16: diff --git a/src/cmd/link/internal/loader/loader.go b/src/cmd/link/internal/loader/loader.go index 3fb2e86514a086..04601b32a00af6 100644 --- a/src/cmd/link/internal/loader/loader.go +++ b/src/cmd/link/internal/loader/loader.go @@ -15,6 +15,7 @@ import ( "debug/elf" "fmt" "internal/abi" + "internal/buildcfg" "io" "iter" "log" @@ -92,6 +93,13 @@ type oReader struct { // non-package symbols). func (r *oReader) NAlldef() int { return r.ndef + r.nhashed64def + r.nhasheddef + r.NNonpkgdef() } +// whether the symbol at local index li is a content hashed symbol +func (r *oReader) IsContentHashed(li uint32) bool { + start := uint32(r.ndef + r.nhashed64def) + end := start + uint32(r.nhasheddef) + return start <= li && li < end +} + // objSym represents a symbol in an object file. It is a tuple of // the object and the symbol's local index. // For external symbols, objidx is the index of l.extReader (extObj), @@ -230,17 +238,19 @@ type Loader struct { outer []Sym // indexed by global index sub map[Sym]Sym - dynimplib map[Sym]string // stores Dynimplib symbol attribute - dynimpvers map[Sym]string // stores Dynimpvers symbol attribute - localentry map[Sym]uint8 // stores Localentry symbol attribute - extname map[Sym]string // stores Extname symbol attribute - elfType map[Sym]elf.SymType // stores elf type symbol property - elfSym map[Sym]int32 // stores elf sym symbol property - localElfSym map[Sym]int32 // stores "local" elf sym symbol property - symPkg map[Sym]string // stores package for symbol, or library for shlib-derived syms - plt map[Sym]int32 // stores dynimport for pe objects - got map[Sym]int32 // stores got for pe objects - dynid map[Sym]int32 // stores Dynid for symbol + dynimplib map[Sym]string // stores Dynimplib symbol attribute + dynimpvers map[Sym]string // stores Dynimpvers symbol attribute + localentry map[Sym]uint8 // stores Localentry symbol attribute + extname map[Sym]string // stores Extname symbol attribute + elfType map[Sym]elf.SymType // stores elf type symbol property + elfSym map[Sym]int32 // stores elf sym symbol property + localElfSym map[Sym]int32 // stores "local" elf sym symbol property + symPkg map[Sym]string // stores package for symbol, or library for shlib-derived syms + plt map[Sym]int32 // stores dynimport for pe objects + got map[Sym]int32 // stores got for pe objects + dynid map[Sym]int32 // stores Dynid for symbol + weakBinding map[Sym]bool // stores whether a symbol has a weak binding + contentHashed map[Sym]bool // whether a symbol is a content hashed symbol, for external symbol only relocVariant map[relocId]sym.RelocVariant // stores variant relocs @@ -326,9 +336,11 @@ func NewLoader(flags uint32, reporter *ErrorReporter) *Loader { plt: make(map[Sym]int32), got: make(map[Sym]int32), dynid: make(map[Sym]int32), + weakBinding: make(map[Sym]bool), attrCgoExportDynamic: make(map[Sym]struct{}), attrCgoExportStatic: make(map[Sym]struct{}), deferReturnTramp: make(map[Sym]bool), + contentHashed: make(map[Sym]bool), extStaticSyms: make(map[nameVer]Sym), builtinSyms: make([]Sym, nbuiltin), flags: flags, @@ -444,19 +456,24 @@ func (st *loadState) addSym(name string, ver int, r *oReader, li uint32, kind in // issue #46653 and #72032. oldsz := l.SymSize(oldi) sz := int64(r.Sym(li).Siz()) + oldr, oldli := l.toLocal(oldi) + oldsym := oldr.Sym(oldli) if osym.Dupok() { - if l.flags&FlagStrictDups != 0 { - l.checkdup(name, r, li, oldi) - } - if oldsz < sz { - // new symbol overwrites old symbol. - l.objSyms[oldi] = objSym{r.objidx, li} + if oldsym.Dupok() { + if l.flags&FlagStrictDups != 0 { + l.checkdup(name, r, li, oldi) + } + if oldsz < sz { + // new symbol overwrites old symbol. + l.objSyms[oldi] = objSym{r.objidx, li} + } } return oldi } - oldr, oldli := l.toLocal(oldi) - oldsym := oldr.Sym(oldli) if oldsym.Dupok() { + // oldsym is Dupok, new is not. + // new symbol overwrites old symbol. + l.objSyms[oldi] = objSym{r.objidx, li} return oldi } // If one is a DATA symbol (i.e. has content, DataSize != 0, @@ -809,6 +826,14 @@ func (l *Loader) SymVersion(i Sym) int { return abiToVer(r.Sym(li).ABI(), r.version) } +func (l *Loader) IsContentHashed(i Sym) bool { + if l.IsExternal(i) { + return l.contentHashed[i] + } + r, li := l.toLocal(i) + return r.IsContentHashed(li) +} + func (l *Loader) IsFileLocal(i Sym) bool { return l.SymVersion(i) >= sym.SymVerStatic } @@ -1447,6 +1472,18 @@ func (l *Loader) SetSymExtname(i Sym, value string) { } } +func (l *Loader) SymWeakBinding(i Sym) bool { + return l.weakBinding[i] +} + +func (l *Loader) SetSymWeakBinding(i Sym, v bool) { + // reject bad symbols + if i >= Sym(len(l.objSyms)) || i == 0 { + panic("bad symbol index in SetSymWeakBinding") + } + l.weakBinding[i] = v +} + // SymElfType returns the previously recorded ELF type for a symbol // (used only for symbols read from shared libraries by ldshlibsyms). // It is not set for symbols defined by the packages being linked or @@ -2206,7 +2243,7 @@ type loadState struct { } type linknameVarRef struct { - pkg string // package of reference (not definition) + pkg *oReader // package of reference (not definition) name string sym Sym } @@ -2243,7 +2280,7 @@ func (st *loadState) preloadSyms(r *oReader, kind int) { } gi := st.addSym(name, v, r, i, kind, osym) r.syms[i] = gi - if kind == nonPkgDef && osym.IsLinkname() && r.DataSize(i) == 0 && strings.Contains(name, ".") { + if kind == nonPkgDef && (osym.IsLinkname() || osym.IsLinknameStd()) && r.DataSize(i) == 0 && strings.Contains(name, ".") { // This is a linknamed "var" "reference" (var x T with no data and //go:linkname x). // We want to check if a linkname reference is allowed. Here we haven't loaded all // symbol definitions, so we don't yet know all the push linknames. So we add to a @@ -2254,7 +2291,7 @@ func (st *loadState) preloadSyms(r *oReader, kind int) { // This use of linkname is usually for referencing C symbols, so allow symbols // with no "." in its name (not a regular Go symbol). // Linkname is always a non-package reference. - st.linknameVarRefs = append(st.linknameVarRefs, linknameVarRef{r.unit.Lib.Pkg, name, gi}) + st.linknameVarRefs = append(st.linknameVarRefs, linknameVarRef{r, name, gi}) } if osym.Local() { l.SetAttrLocal(gi, true) @@ -2332,12 +2369,12 @@ func loadObjRefs(l *Loader, r *oReader, arch *sys.Arch) { v := abiToVer(osym.ABI(), r.version) gi := l.LookupOrCreateSym(name, v) r.syms[ndef+i] = gi - if osym.IsLinkname() { + if osym.IsLinkname() || osym.IsLinknameStd() || r.FromAssembly() { // Check if a linkname reference is allowed. // Only check references (pull), not definitions (push), // so push is always allowed. // Linkname is always a non-package reference. - l.checkLinkname(r.unit.Lib.Pkg, name, gi) + l.checkLinkname(r, name, gi) } if osym.Local() { l.SetAttrLocal(gi, true) @@ -2390,9 +2427,6 @@ func abiToVer(abi uint16, localSymVersion int) int { // If a name is in this map, it is allowed only in listed packages, // even if it has a linknamed definition. var blockedLinknames = map[string][]string{ - // coroutines - "runtime.coroswitch": {"iter"}, - "runtime.newcoro": {"iter"}, // fips info "go:fipsinfo": {"crypto/internal/fips140/check"}, // New internal linknames in Go 1.24 @@ -2406,6 +2440,7 @@ var blockedLinknames = map[string][]string{ "internal/runtime/maps.fatal": {"internal/runtime/maps"}, "internal/runtime/maps.newarray": {"internal/runtime/maps"}, "internal/runtime/maps.newobject": {"internal/runtime/maps"}, + "internal/runtime/maps.rand": {"internal/runtime/maps"}, "internal/runtime/maps.typedmemclr": {"internal/runtime/maps"}, "internal/runtime/maps.typedmemmove": {"internal/runtime/maps"}, "internal/sync.fatal": {"internal/sync"}, @@ -2447,21 +2482,43 @@ var blockedLinknames = map[string][]string{ "sync_test.runtime_blockUntilEmptyCleanupQueue": {"sync_test"}, "time.runtimeIsBubbled": {"time"}, "unique.runtime_blockUntilEmptyCleanupQueue": {"unique"}, - // Experimental features - "runtime.goroutineLeakGC": {"runtime/pprof"}, - "runtime.goroutineleakcount": {"runtime/pprof"}, // Others "net.newWindowsFile": {"net"}, // pushed from os "testing/synctest.testingSynctestTest": {"testing/synctest"}, // pushed from testing - "runtime.addmoduledata": {}, // disallow all package + // New internal linknames in Go 1.26 + // Pushed from runtime + "crypto/fips140.isBypassed": {"crypto/fips140"}, + "crypto/fips140.setBypass": {"crypto/fips140"}, + "crypto/fips140.unsetBypass": {"crypto/fips140"}, + "crypto/subtle.setDITEnabled": {"crypto/subtle"}, + "crypto/subtle.setDITDisabled": {"crypto/subtle"}, + "internal/cpu.sysctlbynameBytes": {"internal/cpu"}, + "internal/cpu.sysctlbynameInt32": {"internal/cpu"}, + "runtime.pprof_goroutineLeakProfileWithLabels": {"runtime/pprof"}, + "runtime/pprof.runtime_goroutineLeakGC": {"runtime/pprof"}, + "runtime/pprof.runtime_goroutineleakcount": {"runtime/pprof"}, + "runtime/secret.appendSignalStacks": {"runtime/secret"}, + "runtime/secret.count": {"runtime/secret"}, + "runtime/secret.dec": {"runtime/secret"}, + "runtime/secret.eraseSecrets": {"runtime/secret"}, + "runtime/secret.getStack": {"runtime/secret"}, + "runtime/secret.inc": {"runtime/secret"}, + "syscall.rawsyscalln": {"syscall"}, + "syscall.runtimeClearenv": {"syscall"}, + "syscall.syscalln": {"syscall"}, + // Others + "crypto/internal/rand.SetTestingReader": {"testing/cryptotest"}, // pushed from crypto/internal/rand + "testing.checkParallel": {"testing/cryptotest"}, // pushed from testing + "runtime.addmoduledata": {}, // assembly symbol, disallow all packages } -// check if a linkname reference to symbol s from pkg is allowed -func (l *Loader) checkLinkname(pkg, name string, s Sym) { +// check if a linkname reference to symbol s from refpkg is allowed +func (l *Loader) checkLinkname(refpkg *oReader, name string, s Sym) { if l.flags&FlagCheckLinkname == 0 { return } + pkg := refpkg.unit.Lib.Pkg error := func() { log.Fatalf("%s: invalid reference to %s", pkg, name) } @@ -2495,12 +2552,44 @@ func (l *Loader) checkLinkname(pkg, name string, s Sym) { return } osym := r.Sym(li) - if osym.IsLinkname() || osym.ABIWrapper() { + if r.FromAssembly() && !osym.IsLinknameStd() && !osym.IsLinkname() { + if strings.HasPrefix(name, pkg) { + // Allow if by name it is pushed to pkg, e.g. in package a, + // an assembly function is defined as b.F, then it is allowed + // to be used in package b. + return + } + if !strings.Contains(name, ".") { + // Symbol without "." in its name is meant to be accessed + // in non-Go code. Usually non-Go access is not checked, but + // it can also be from Go code via assembly or linkname. + // Notable member of the hall of shame is + // github.com/ebitengine/purego accessing crosscall2. + return + } + // For an assembly symbol, check if there is a linkname applied + // to its ABI wrapper. + if !buildcfg.Experiment.RegabiWrappers { + // If ABI wrapper is not enabled (i.e. non-regabi platform), + // permit for now, as there is no good way to check. + return + } + otherABI := 1 - abiToVer(osym.ABI(), r.version) // for now, we only have ABI 0 and 1 + w := l.Lookup(name, otherABI) // TODO: use an aux symbol instead of name lookup? + if w != 0 { + r, li = l.toLocal(w) + osym = r.Sym(li) + } + } + if osym.IsLinknameStd() { + // It is pushed with linknamestd. Allow only pulls from the + // standard library. + if refpkg.Std() { + return + } + } + if osym.IsLinkname() { // Allow if the def has a linkname (push). - // ABI wrapper usually wraps an assembly symbol, a linknamed symbol, - // or an external symbol, or provide access of a Go symbol to assembly. - // For now, allow ABI wrappers. - // TODO: check the wrapped symbol? return } error() @@ -2589,6 +2678,9 @@ func (l *Loader) cloneToExternal(symIdx Sym) *extSymPayload { // Some attributes were encoded in the object file. Copy them over. l.SetAttrDuplicateOK(symIdx, r.Sym(li).Dupok()) l.SetAttrShared(symIdx, r.Shared()) + if r.IsContentHashed(li) { + l.contentHashed[symIdx] = true + } return pp } @@ -2807,7 +2899,7 @@ type ErrorReporter struct { // // Logging an error means that on exit cmd/link will delete any // output file and return a non-zero error code. -func (reporter *ErrorReporter) Errorf(s Sym, format string, args ...interface{}) { +func (reporter *ErrorReporter) Errorf(s Sym, format string, args ...any) { if s != 0 && reporter.ldr.SymName(s) != "" { // Note: Replace is needed here because symbol names might have % in them, // due to the use of LinkString for names of instantiating types. @@ -2826,7 +2918,7 @@ func (l *Loader) GetErrorReporter() *ErrorReporter { } // Errorf method logs an error message. See ErrorReporter.Errorf for details. -func (l *Loader) Errorf(s Sym, format string, args ...interface{}) { +func (l *Loader) Errorf(s Sym, format string, args ...any) { l.errorReporter.Errorf(s, format, args...) } diff --git a/src/cmd/link/internal/loader/loader_test.go b/src/cmd/link/internal/loader/loader_test.go index 541f42b7d1a99a..7f7a75d9f4330b 100644 --- a/src/cmd/link/internal/loader/loader_test.go +++ b/src/cmd/link/internal/loader/loader_test.go @@ -14,7 +14,7 @@ import ( "testing" ) -// dummyAddSym adds the named symbol to the loader as if it had been +// addDummyObjSym adds the named symbol to the loader as if it had been // read from a Go object file. Note that it allocates a global // index without creating an associated object reader, so one can't // do anything interesting with this symbol (such as look at its diff --git a/src/cmd/link/internal/loadmacho/ldmacho.go b/src/cmd/link/internal/loadmacho/ldmacho.go index 5e8022ce69bb36..41d99b80d74bd3 100644 --- a/src/cmd/link/internal/loadmacho/ldmacho.go +++ b/src/cmd/link/internal/loadmacho/ldmacho.go @@ -424,7 +424,7 @@ func macholoadsym(m *ldMachoObj, symtab *ldMachoSymtab) int { // Load the Mach-O file pn from f. // Symbols are written into syms, and a slice of the text symbols is returned. func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, f *bio.Reader, pkg string, length int64, pn string) (textp []loader.Sym, err error) { - errorf := func(str string, args ...interface{}) ([]loader.Sym, error) { + errorf := func(str string, args ...any) ([]loader.Sym, error) { return nil, fmt.Errorf("loadmacho: %v: %v", pn, fmt.Sprintf(str, args...)) } @@ -570,6 +570,9 @@ func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, f *bio.Reader, bld.SetData(dat[sect.addr-c.seg.vmaddr:][:sect.size]) } bld.SetSize(int64(len(bld.Data()))) + if sect.align != 0 { + bld.SetAlign(1 << sect.align) + } if sect.segname == "__TEXT" { if sect.name == "__text" { @@ -613,6 +616,9 @@ func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, f *bio.Reader, } if machsym.desc&(N_WEAK_REF|N_WEAK_DEF) != 0 { l.SetAttrDuplicateOK(s, true) + if machsym.desc&N_WEAK_REF != 0 { + l.SetSymWeakBinding(s, true) + } } machsym.sym = s if machsym.sectnum == 0 { // undefined diff --git a/src/cmd/link/internal/loadpe/ldpe.go b/src/cmd/link/internal/loadpe/ldpe.go index d3a050135c2828..fe39fad429d1f8 100644 --- a/src/cmd/link/internal/loadpe/ldpe.go +++ b/src/cmd/link/internal/loadpe/ldpe.go @@ -222,7 +222,7 @@ var comdatDefinitions map[string]int64 type Symbols struct { Textp []loader.Sym // text symbols Resources []loader.Sym // .rsrc section or set of .rsrc$xx sections - PData loader.Sym + PData []loader.Sym XData loader.Sym } @@ -256,7 +256,10 @@ func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, input *bio.Read defer f.Close() state.f = f - var ls Symbols + var ( + ls Symbols + pdata loader.Sym + ) // TODO return error if found .cormeta @@ -312,7 +315,7 @@ func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, input *bio.Read ls.Resources = append(ls.Resources, s) } else if bld.Type() == sym.SSEHSECT { if sect.Name == ".pdata" { - ls.PData = s + pdata = s } else if sect.Name == ".xdata" { ls.XData = s } @@ -392,21 +395,59 @@ func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, input *bio.Read switch r.Type { case IMAGE_REL_ARM64_ADDR32: rType = objabi.R_ADDR + case IMAGE_REL_ARM64_ADDR64: + rType = objabi.R_ADDR + rSize = 8 case IMAGE_REL_ARM64_ADDR32NB: rType = objabi.R_PEIMAGEOFF + case IMAGE_REL_ARM64_BRANCH26: + rType = objabi.R_CALLARM64 + case IMAGE_REL_ARM64_PAGEBASE_REL21, + IMAGE_REL_ARM64_PAGEOFFSET_12A, + IMAGE_REL_ARM64_PAGEOFFSET_12L: + rType = objabi.R_ARM64_PCREL } } if rType == 0 { return nil, fmt.Errorf("%s: %v: unknown relocation type %v", pn, state.sectsyms[rsect], r.Type) } - var rAdd int64 + var val int64 switch rSize { default: panic("unexpected relocation size " + strconv.Itoa(int(rSize))) case 4: - rAdd = int64(int32(binary.LittleEndian.Uint32(state.sectdata[rsect][rOff:]))) + val = int64(int32(binary.LittleEndian.Uint32(state.sectdata[rsect][rOff:]))) case 8: - rAdd = int64(binary.LittleEndian.Uint64(state.sectdata[rsect][rOff:])) + val = int64(binary.LittleEndian.Uint64(state.sectdata[rsect][rOff:])) + } + var rAdd int64 + if arch.Family == sys.ARM64 { + switch r.Type { + case IMAGE_REL_ARM64_BRANCH26: + // This instruction doesn't support an addend. + case IMAGE_REL_ARM64_PAGEOFFSET_12A: + // The addend is stored in the immediate field of the instruction. + // Get the addend from the instruction. + rAdd = (val >> 10) & 0xfff + case IMAGE_REL_ARM64_PAGEOFFSET_12L: + // Same as IMAGE_REL_ARM64_PAGEOFFSET_12A, but taking into account the shift. + shift := uint32(val) >> 30 + if shift == 0 && (val>>20)&0x048 == 0x048 { // 128-bit vector load + shift = 4 + } + rAdd = ((val >> 10) & 0xfff) << shift + case IMAGE_REL_ARM64_PAGEBASE_REL21: + // The addend is stored in the immediate field of the instruction + // as a byte offset. Get the addend from the instruction and clear + // the immediate bits. + immlo := (val >> 29) & 3 + immhi := (val >> 5) & 0x7ffff + rAdd = (immhi << 2) | immlo + default: + rAdd = val + } + } else { + rAdd = val } // ld -r could generate multiple section symbols for the // same section but with different values, we have to take @@ -558,8 +599,12 @@ func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, input *bio.Read } } - if ls.PData != 0 { - processSEH(l, arch, ls.PData, ls.XData) + if pdata != 0 { + subs, err := processSEH(l, arch, pdata) + if err != nil { + return nil, err + } + ls.PData = subs } return &ls, nil diff --git a/src/cmd/link/internal/loadpe/seh.go b/src/cmd/link/internal/loadpe/seh.go index 545958f1d60bee..91d67c67fa7380 100644 --- a/src/cmd/link/internal/loadpe/seh.go +++ b/src/cmd/link/internal/loadpe/seh.go @@ -21,24 +21,19 @@ const ( unwCodeSize = 2 // Bytes per unwind code. ) -// processSEH walks all pdata relocations looking for exception handler function symbols. -// We want to mark these as reachable if the function that they protect is reachable -// in the final binary. -func processSEH(ldr *loader.Loader, arch *sys.Arch, pdata sym.LoaderSym, xdata sym.LoaderSym) error { +// processSEH walks host-object pdata relocations and returns the set of +// per-entry pdata symbols created from the input section. +func processSEH(ldr *loader.Loader, arch *sys.Arch, pdata sym.LoaderSym) ([]loader.Sym, error) { switch arch.Family { case sys.AMD64: - ldr.SetAttrReachable(pdata, true) - if xdata != 0 { - ldr.SetAttrReachable(xdata, true) - } return processSEHAMD64(ldr, pdata) default: // TODO: support SEH on other architectures. - return fmt.Errorf("unsupported architecture for SEH: %v", arch.Family) + return nil, fmt.Errorf("unsupported architecture for SEH: %v", arch.Family) } } -func processSEHAMD64(ldr *loader.Loader, pdata sym.LoaderSym) error { +func processSEHAMD64(ldr *loader.Loader, pdata sym.LoaderSym) ([]loader.Sym, error) { // The following loop traverses a list of pdata entries, // each entry being 3 relocations long. The first relocation // is a pointer to the function symbol to which the pdata entry @@ -48,18 +43,58 @@ func processSEHAMD64(ldr *loader.Loader, pdata sym.LoaderSym) error { // https://learn.microsoft.com/en-us/cpp/build/exception-handling-x64#struct-runtime_function rels := ldr.Relocs(pdata) if rels.Count()%3 != 0 { - return fmt.Errorf(".pdata symbol %q has invalid relocation count", ldr.SymName(pdata)) + return nil, fmt.Errorf(".pdata symbol %q has invalid relocation count", ldr.SymName(pdata)) } + data := ldr.Data(pdata) + entries := make([]loader.Sym, 0, rels.Count()/3) + for i := 0; i < rels.Count(); i += 3 { - xrel := rels.At(i + 2) - handler := findHandlerInXDataAMD64(ldr, xrel.Sym(), xrel.Add()) - if handler != 0 { - sb := ldr.MakeSymbolUpdater(rels.At(i).Sym()) + // Create a new symbol for the pdata entry. + entry := ldr.MakeSymbolBuilder("") + entry.SetType(sym.SSEHSECT) + entry.SetAlign(4) + entry.SetSize(12) + entryOff := int(rels.At(i).Off()) + entryEnd := entryOff + 4*3 + entry.SetData(data[entryOff:entryEnd:entryEnd]) + + // Add a relocation from the target function to the pdata entry + // and to the exception handler, if present, to ensure they are + // retained by dead code elimination. + if targetFunc := rels.At(i).Sym(); targetFunc != 0 { + sb := ldr.MakeSymbolUpdater(targetFunc) r, _ := sb.AddRel(objabi.R_KEEP) - r.SetSym(handler) + r.SetSym(entry.Sym()) + xrel := rels.At(i + 2) + if xrel.Sym() != 0 { + r, _ = sb.AddRel(objabi.R_KEEP) + r.SetSym(xrel.Sym()) + } + handler := findHandlerInXDataAMD64(ldr, xrel.Sym(), xrel.Add()) + if handler != 0 { + r, _ = sb.AddRel(objabi.R_KEEP) + r.SetSym(handler) + } } + + // Copy the relocations from the original .pdata entry to the new symbol, + // adjusting the offsets. + for j := range 3 { + rOld := rels.At(i + j) + typ := rOld.Type() + if rOld.Weak() { + typ |= objabi.R_WEAK + } + rel, _ := entry.AddRel(typ) + rel.SetOff(int32(j * 4)) + rel.SetSiz(rOld.Siz()) + rel.SetSym(rOld.Sym()) + rel.SetAdd(rOld.Add()) + } + + entries = append(entries, entry.Sym()) } - return nil + return entries, nil } // findHandlerInXDataAMD64 finds the symbol in the .xdata section that diff --git a/src/cmd/link/internal/loadxcoff/ldxcoff.go b/src/cmd/link/internal/loadxcoff/ldxcoff.go index fd116d54207133..8c0949ec70a76b 100644 --- a/src/cmd/link/internal/loadxcoff/ldxcoff.go +++ b/src/cmd/link/internal/loadxcoff/ldxcoff.go @@ -42,7 +42,7 @@ func (f *xcoffBiobuf) ReadAt(p []byte, off int64) (int, error) { // loads the Xcoff file pn from f. // Symbols are written into loader, and a slice of the text symbols is returned. func Load(l *loader.Loader, arch *sys.Arch, localSymVersion int, input *bio.Reader, pkg string, length int64, pn string) (textp []loader.Sym, err error) { - errorf := func(str string, args ...interface{}) ([]loader.Sym, error) { + errorf := func(str string, args ...any) ([]loader.Sym, error) { return nil, fmt.Errorf("loadxcoff: %v: %v", pn, fmt.Sprintf(str, args...)) } diff --git a/src/cmd/link/internal/loong64/asm.go b/src/cmd/link/internal/loong64/asm.go index e7f3fd1d9817ad..e1a8dcaaa8d599 100644 --- a/src/cmd/link/internal/loong64/asm.go +++ b/src/cmd/link/internal/loong64/asm.go @@ -85,7 +85,8 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade } return true - case objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_B26): + case objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_B26), + objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_CALL36): if targType == sym.SDYNIMPORT { addpltsym(target, ldr, syms, targ) su := ldr.MakeSymbolUpdater(s) @@ -95,29 +96,47 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade if targType == 0 || targType == sym.SXREF { ldr.Errorf(s, "unknown symbol %s in callloong64", ldr.SymName(targ)) } + relocType := objabi.R_CALLLOONG64 + if r.Type() == objabi.ElfRelocOffset+objabi.RelocType(elf.R_LARCH_CALL36) { + relocType = objabi.R_LOONG64_CALL36 + } su := ldr.MakeSymbolUpdater(s) - su.SetRelocType(rIdx, objabi.R_CALLLOONG64) + su.SetRelocType(rIdx, relocType) return true case objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_GOT_PC_HI20), - objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_GOT_PC_LO12): + objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_GOT_PC_LO12), + objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_GOT64_PC_HI12), + objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_GOT64_PC_LO20): if targType != sym.SDYNIMPORT { // TODO: turn LDR of GOT entry into ADR of symbol itself } ld.AddGotSym(target, ldr, syms, targ, uint32(elf.R_LARCH_64)) su := ldr.MakeSymbolUpdater(s) - if r.Type() == objabi.ElfRelocOffset+objabi.RelocType(elf.R_LARCH_GOT_PC_HI20) { - su.SetRelocType(rIdx, objabi.R_LOONG64_ADDR_HI) - } else { - su.SetRelocType(rIdx, objabi.R_LOONG64_ADDR_LO) + + var relocType objabi.RelocType + switch r.Type() - objabi.ElfRelocOffset { + case objabi.RelocType(elf.R_LARCH_GOT_PC_HI20): + relocType = objabi.R_LOONG64_ADDR_HI + case objabi.RelocType(elf.R_LARCH_GOT_PC_LO12): + relocType = objabi.R_LOONG64_ADDR_LO + case objabi.RelocType(elf.R_LARCH_GOT64_PC_HI12): + relocType = objabi.R_LOONG64_ADDR64_HI + case objabi.RelocType(elf.R_LARCH_GOT64_PC_LO20): + relocType = objabi.R_LOONG64_ADDR64_LO } + + su.SetRelocType(rIdx, relocType) su.SetRelocSym(rIdx, syms.GOT) su.SetRelocAdd(rIdx, r.Add()+int64(ldr.SymGot(targ))) return true case objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_PCALA_HI20), - objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_PCALA_LO12): + objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_PCALA_LO12), + objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_PCALA64_HI12), + objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_PCALA64_LO20), + objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_PCREL20_S2): if targType == sym.SDYNIMPORT { ldr.Errorf(s, "unexpected relocation for dynamic symbol %s", ldr.SymName(targ)) } @@ -125,12 +144,22 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade ldr.Errorf(s, "unknown symbol %s", ldr.SymName(targ)) } - su := ldr.MakeSymbolUpdater(s) - if r.Type() == objabi.ElfRelocOffset+objabi.RelocType(elf.R_LARCH_PCALA_HI20) { - su.SetRelocType(rIdx, objabi.R_LOONG64_ADDR_HI) - } else { - su.SetRelocType(rIdx, objabi.R_LOONG64_ADDR_LO) + var relocType objabi.RelocType + switch r.Type() - objabi.ElfRelocOffset { + case objabi.RelocType(elf.R_LARCH_PCALA_HI20): + relocType = objabi.R_LOONG64_ADDR_HI + case objabi.RelocType(elf.R_LARCH_PCALA_LO12): + relocType = objabi.R_LOONG64_ADDR_LO + case objabi.RelocType(elf.R_LARCH_PCALA64_HI12): + relocType = objabi.R_LOONG64_ADDR64_HI + case objabi.RelocType(elf.R_LARCH_PCALA64_LO20): + relocType = objabi.R_LOONG64_ADDR64_LO + case objabi.RelocType(elf.R_LARCH_PCREL20_S2): + relocType = objabi.R_LOONG64_ADDR_PCREL20_S2 } + + su := ldr.MakeSymbolUpdater(s) + su.SetRelocType(rIdx, relocType) return true case objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_ADD64), @@ -278,14 +307,25 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade } case objabi.R_LOONG64_GOT_HI, - objabi.R_LOONG64_GOT_LO: + objabi.R_LOONG64_GOT_LO, + objabi.R_LOONG64_GOT64_HI, + objabi.R_LOONG64_GOT64_LO: ld.AddGotSym(target, ldr, syms, targ, uint32(elf.R_LARCH_64)) su := ldr.MakeSymbolUpdater(s) - if r.Type() == objabi.R_LOONG64_GOT_HI { - su.SetRelocType(rIdx, objabi.R_LOONG64_ADDR_HI) - } else { - su.SetRelocType(rIdx, objabi.R_LOONG64_ADDR_LO) + + var relocType objabi.RelocType + switch r.Type() { + case objabi.R_LOONG64_GOT_HI: + relocType = objabi.R_LOONG64_ADDR_HI + case objabi.R_LOONG64_GOT_LO: + relocType = objabi.R_LOONG64_ADDR_LO + case objabi.R_LOONG64_GOT64_HI: + relocType = objabi.R_LOONG64_ADDR64_HI + case objabi.R_LOONG64_GOT64_LO: + relocType = objabi.R_LOONG64_ADDR64_LO } + + su.SetRelocType(rIdx, relocType) su.SetRelocSym(rIdx, syms.GOT) su.SetRelocAdd(rIdx, r.Add()+int64(ldr.SymGot(targ))) return true @@ -418,6 +458,11 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, out.Write64(uint64(elf.R_LARCH_B26) | uint64(elfsym)<<32) out.Write64(uint64(r.Xadd)) + case objabi.R_LOONG64_CALL36: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_CALL36) | uint64(elfsym)<<32) + out.Write64(uint64(r.Xadd)) + case objabi.R_LOONG64_TLS_IE_HI: out.Write64(uint64(sectoff)) out.Write64(uint64(elf.R_LARCH_TLS_IE_PC_HI20) | uint64(elfsym)<<32) @@ -438,6 +483,21 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, out.Write64(uint64(elf.R_LARCH_PCALA_HI20) | uint64(elfsym)<<32) out.Write64(uint64(r.Xadd)) + case objabi.R_LOONG64_ADDR64_LO: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_PCALA64_LO20) | uint64(elfsym)<<32) + out.Write64(uint64(r.Xadd)) + + case objabi.R_LOONG64_ADDR64_HI: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_PCALA64_HI12) | uint64(elfsym)<<32) + out.Write64(uint64(r.Xadd)) + + case objabi.R_LOONG64_ADDR_PCREL20_S2: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_PCREL20_S2) | uint64(elfsym)<<32) + out.Write64(uint64(r.Xadd)) + case objabi.R_LOONG64_GOT_HI: out.Write64(uint64(sectoff)) out.Write64(uint64(elf.R_LARCH_GOT_PC_HI20) | uint64(elfsym)<<32) @@ -447,6 +507,16 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, out.Write64(uint64(sectoff)) out.Write64(uint64(elf.R_LARCH_GOT_PC_LO12) | uint64(elfsym)<<32) out.Write64(uint64(0x0)) + + case objabi.R_LOONG64_GOT64_HI: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_GOT64_PC_HI12) | uint64(elfsym)<<32) + out.Write64(uint64(0x0)) + + case objabi.R_LOONG64_GOT64_LO: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_GOT64_PC_LO20) | uint64(elfsym)<<32) + out.Write64(uint64(0x0)) } return true @@ -463,7 +533,10 @@ func archreloc(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, r loade default: return val, 0, false case objabi.R_LOONG64_ADDR_HI, - objabi.R_LOONG64_ADDR_LO: + objabi.R_LOONG64_ADDR_LO, + objabi.R_LOONG64_ADDR64_HI, + objabi.R_LOONG64_ADDR64_LO, + objabi.R_LOONG64_ADDR_PCREL20_S2: // set up addend for eventual relocation via outer symbol. rs, _ := ld.FoldSubSymbolOffset(ldr, rs) rst := ldr.SymType(rs) @@ -471,14 +544,17 @@ func archreloc(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, r loade ldr.Errorf(s, "missing section for %s", ldr.SymName(rs)) } return val, 1, true + case objabi.R_LOONG64_TLS_LE_HI, objabi.R_LOONG64_TLS_LE_LO, objabi.R_CALLLOONG64, - objabi.R_JMPLOONG64, + objabi.R_LOONG64_CALL36, objabi.R_LOONG64_TLS_IE_HI, objabi.R_LOONG64_TLS_IE_LO, objabi.R_LOONG64_GOT_HI, - objabi.R_LOONG64_GOT_LO: + objabi.R_LOONG64_GOT_LO, + objabi.R_LOONG64_GOT64_HI, + objabi.R_LOONG64_GOT64_LO: return val, 1, true } } @@ -487,38 +563,91 @@ func archreloc(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, r loade const noExtReloc = 0 switch r.Type() { - case objabi.R_CONST: - return r.Add(), noExtReloc, isOk - case objabi.R_GOTOFF: - return ldr.SymValue(r.Sym()) + r.Add() - ldr.SymValue(syms.GOT), noExtReloc, isOk case objabi.R_LOONG64_ADDR_HI, - objabi.R_LOONG64_ADDR_LO: + objabi.R_LOONG64_ADDR_LO, + objabi.R_LOONG64_ADDR64_HI, + objabi.R_LOONG64_ADDR64_LO: + pc := ldr.SymValue(s) + int64(r.Off()) + var t int64 + + switch r.Type() { + case objabi.R_LOONG64_ADDR_LO: + // pcalau12i + t = pc32RelocBits(r.Type(), ldr.SymAddr(rs)+r.Add(), pc) + o = val&0xffc003ff | (t << 10) + case objabi.R_LOONG64_ADDR_HI: + // addi.w/addi.d + t = pc32RelocBits(r.Type(), ldr.SymAddr(rs)+r.Add(), pc) + o = val&0xfe00001f | (t << 5) + case objabi.R_LOONG64_ADDR64_LO: + // lu32i.d + t = pc64RelocBits(r.Type(), ldr.SymAddr(rs)+r.Add(), pc-8) + o = val&0xfe00001f | (t << 5) + case objabi.R_LOONG64_ADDR64_HI: + // lu52i.d + t = pc64RelocBits(r.Type(), ldr.SymAddr(rs)+r.Add(), pc-12) + o = val&0xffc003ff | (t << 10) + } + + return o, noExtReloc, isOk + + case objabi.R_LOONG64_ADDR_PCREL20_S2: pc := ldr.SymValue(s) + int64(r.Off()) - t := calculatePCAlignedReloc(r.Type(), ldr.SymAddr(rs)+r.Add(), pc) - if r.Type() == objabi.R_LOONG64_ADDR_LO { - return val&0xffc003ff | (t << 10), noExtReloc, isOk + t := (ldr.SymAddr(rs) + r.Add() - pc) >> 2 + if t < -1<<21 || t >= 1<<21 { + ldr.Errorf(s, "reloc: R_LOONG64_ADDR_PCREL20_S2, offset out of range %d", t) } - return val&0xfe00001f | (t << 5), noExtReloc, isOk + // pcaddi + return val&0xfe00001f | ((t & 0xfffff) << 5), noExtReloc, isOk + case objabi.R_LOONG64_TLS_LE_HI, objabi.R_LOONG64_TLS_LE_LO: t := ldr.SymAddr(rs) + r.Add() + if t < -1<<31 || t >= 1<<31 { + ldr.Errorf(s, "reloc: R_LOONG64_TLS_LE_HI/LO, TLS offset out of range %d", t) + } if r.Type() == objabi.R_LOONG64_TLS_LE_LO { + // ori return val&0xffc003ff | ((t & 0xfff) << 10), noExtReloc, isOk } + // lu12i.w return val&0xfe00001f | (((t) >> 12 << 5) & 0x1ffffe0), noExtReloc, isOk - case objabi.R_CALLLOONG64, - objabi.R_JMPLOONG64: + + case objabi.R_CALLLOONG64: pc := ldr.SymValue(s) + int64(r.Off()) t := ldr.SymAddr(rs) + r.Add() - pc + if t < -1<<27 || t >= 1<<27 { + ldr.Errorf(s, "reloc: R_CALLLOONG64, program too large, call relocation distance = %d", t) + } + // bl return val&0xfc000000 | (((t >> 2) & 0xffff) << 10) | (((t >> 2) & 0x3ff0000) >> 16), noExtReloc, isOk + case objabi.R_LOONG64_CALL36: + pc := ldr.SymValue(s) + int64(r.Off()) + t := (ldr.SymAddr(rs) + r.Add() - pc) >> 2 + if t < -1<<37 || t >= 1<<37 { + ldr.Errorf(s, "reloc: R_LOONG64_CALL36, program too large, call relocation distance = %d", t) + } + // val is pcaddu18i (lower half) + jirl (upper half) + pcaddu18i := (val & 0xfe00001f) | (((t + 0x8000) >> 16) << 5) + jirl := ((val >> 32) & 0xfc0003ff) | ((t & 0xffff) << 10) + return pcaddu18i | (jirl << 32), noExtReloc, isOk + case objabi.R_JMP16LOONG64, objabi.R_JMP21LOONG64: pc := ldr.SymValue(s) + int64(r.Off()) t := ldr.SymAddr(rs) + r.Add() - pc if r.Type() == objabi.R_JMP16LOONG64 { + if t < -1<<17 || t >= 1<<17 { + ldr.Errorf(s, "reloc: R_JMP16LOONG64, program too large, jmp relocation distance = %d", t) + } + // beq/bne/blt[u]/bge[u] return val&0xfc0003ff | (((t >> 2) & 0xffff) << 10), noExtReloc, isOk } + if t < -1<<22 || t >= 1<<22 { + ldr.Errorf(s, "reloc: R_JMP21LOONG64, program too large, call relocation distance = %d", t) + } + // beqz/bnez return val&0xfc0003e0 | (((t >> 2) & 0xffff) << 10) | (((t >> 2) & 0x1f0000) >> 16), noExtReloc, isOk case objabi.R_LOONG64_TLS_IE_HI, @@ -528,6 +657,9 @@ func archreloc(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, r loade ldr.Errorf(s, "TLS reloc on unsupported OS %v", target.HeadType) } t := ldr.SymAddr(rs) + r.Add() + if t < -1<<31 || t >= 1<<31 { + ldr.Errorf(s, "reloc: R_LOONG64_TLS_IE_HI/LO, TLS offset out of range %d", t) + } if r.Type() == objabi.R_LOONG64_TLS_IE_HI { // pcalau12i -> lu12i.w return (0x14000000 | (val & 0x1f) | ((t >> 12) << 5)), noExtReloc, isOk @@ -556,16 +688,17 @@ func extreloc(target *ld.Target, ldr *loader.Loader, r loader.Reloc, s loader.Sy switch r.Type() { case objabi.R_LOONG64_ADDR_HI, objabi.R_LOONG64_ADDR_LO, + objabi.R_LOONG64_ADDR64_HI, + objabi.R_LOONG64_ADDR64_LO, objabi.R_LOONG64_GOT_HI, - objabi.R_LOONG64_GOT_LO: + objabi.R_LOONG64_GOT_LO, + objabi.R_LOONG64_GOT64_HI, + objabi.R_LOONG64_GOT64_LO: return ld.ExtrelocViaOuterSym(ldr, r, s), true case objabi.R_LOONG64_TLS_LE_HI, objabi.R_LOONG64_TLS_LE_LO, - objabi.R_CONST, - objabi.R_GOTOFF, objabi.R_CALLLOONG64, - objabi.R_JMPLOONG64, objabi.R_LOONG64_TLS_IE_HI, objabi.R_LOONG64_TLS_IE_LO: return ld.ExtrelocSimple(ldr, r), true @@ -573,34 +706,71 @@ func extreloc(target *ld.Target, ldr *loader.Loader, r loader.Reloc, s loader.Sy return loader.ExtReloc{}, false } -func isRequestingLowPageBits(t objabi.RelocType) bool { - switch t { - case objabi.R_LOONG64_ADDR_LO: - return true +// Comments from copying binutils/bfd/elfnn-loongarch.c +// +// For example: pc is 0x11000010000100, symbol is 0x1812348ffff812 +// +// offset = (0x1812348ffff812 & ~0xfff) - (0x11000010000100 & ~0xfff) +// offset = 0x712347ffff000 +// +// lo12: 0x1812348ffff812 & 0xfff = 0x812 +// hi20: 0x7ffff + 0x1(lo12 > 0x7ff) = 0x80000 +// lo20: 0x71234 - 0x1(lo12 > 0x7ff) + 0x1(hi20 > 0x7ffff) +// hi12: 0x0 +// +// pcalau12i $t1, hi20 (0x80000) +// +// $t1 = 0x11000010000100 + sign-extend(0x80000 << 12) +// = 0x11000010000100 + 0xffffffff80000000 +// = 0x10ffff90000000 +// +// addi.d $t0, $zero, lo12 (0x812) +// +// $t0 = 0xfffffffffffff812 (if lo12 > 0x7ff, because sign-extend, +// lo20 need to sub 0x1) +// +// lu32i.d $t0, lo20 (0x71234) +// +// $t0 = {0x71234, 0xfffff812} +// = 0x71234fffff812 +// +// lu52i.d $t0, hi12 (0x0) +// +// $t0 = {0x0, 0x71234fffff812} +// = 0x71234fffff812 +func pc32RelocBits(reloc objabi.RelocType, tgt int64, pc int64) int64 { + lo12 := tgt & 0xfff + if reloc == objabi.R_LOONG64_ADDR_LO { + return lo12 } - return false + + off := (tgt & ^0xfff) - (pc & ^0xfff) + if lo12 >= 0x800 { + off += 0x1000 + } + + // objabi.R_LOONG64_ADDR_HI + return (off >> 12) & 0xfffff } -// Calculates the value to put into the immediate slot, according to the -// desired relocation type, target and PC. -// The value to use varies based on the reloc type. Namely, the absolute low -// bits of the target are to be used for the low part, while the page-aligned -// offset is to be used for the higher part. A "page" here is not related to -// the system's actual page size, but rather a fixed 12-bit range (designed to -// cooperate with ADDI/LD/ST's 12-bit immediates). -func calculatePCAlignedReloc(t objabi.RelocType, tgt int64, pc int64) int64 { - if isRequestingLowPageBits(t) { - // corresponding immediate field is 12 bits wide - return tgt & 0xfff +func pc64RelocBits(reloc objabi.RelocType, tgt int64, pc int64) int64 { + lo12 := tgt & 0xfff + off := (tgt & ^0xfff) - (pc & ^0xfff) + + if lo12 >= 0x800 { + off += (0x1000 - 0x100000000) } - pageDelta := (tgt >> 12) - (pc >> 12) - if tgt&0xfff >= 0x800 { - // adjust for sign-extended addition of the low bits - pageDelta += 1 + if (off & 0x80000000) != 0 { + off += 0x100000000 } - // corresponding immediate field is 20 bits wide - return pageDelta & 0xfffff + + if reloc == objabi.R_LOONG64_ADDR64_LO { + return (off >> 32) & 0xfffff + } + + // objabi.R_LOONG64_ADDR64_HI + return (off >> 52) & 0xfff } // Convert the direct jump relocation r to refer to a trampoline if the target is too far. @@ -608,11 +778,7 @@ func trampoline(ctxt *ld.Link, ldr *loader.Loader, ri int, rs, s loader.Sym) { relocs := ldr.Relocs(s) r := relocs.At(ri) switch r.Type() { - case objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_B26): - // Nothing to do. - // The plt symbol has not been added. If we add tramp - // here, plt will not work. - case objabi.R_CALLLOONG64: + case objabi.ElfRelocOffset + objabi.RelocType(elf.R_LARCH_B26), objabi.R_CALLLOONG64: var t int64 // ldr.SymValue(rs) == 0 indicates a cross-package jump to a function that is not yet // laid out. Conservatively use a trampoline. This should be rare, as we lay out packages @@ -681,7 +847,7 @@ func gentramp(ctxt *ld.Link, ldr *loader.Loader, tramp *loader.SymbolBuilder, ta tramp.SetSize(12) // 3 instructions P := make([]byte, tramp.Size()) - o1 := uint32(0x1a00001e) // pcalau12i $r30, 0 + o1 := uint32(0x1a000014) // pcalau12i $r20, 0 ctxt.Arch.ByteOrder.PutUint32(P, o1) r1, _ := tramp.AddRel(objabi.R_LOONG64_ADDR_HI) r1.SetOff(0) @@ -689,7 +855,7 @@ func gentramp(ctxt *ld.Link, ldr *loader.Loader, tramp *loader.SymbolBuilder, ta r1.SetSym(target) r1.SetAdd(offset) - o2 := uint32(0x02c003de) // addi.d $r30, $r30, 0 + o2 := uint32(0x02c00294) // addi.d $r20, $r20, 0 ctxt.Arch.ByteOrder.PutUint32(P[4:], o2) r2, _ := tramp.AddRel(objabi.R_LOONG64_ADDR_LO) r2.SetOff(4) @@ -697,7 +863,7 @@ func gentramp(ctxt *ld.Link, ldr *loader.Loader, tramp *loader.SymbolBuilder, ta r2.SetSym(target) r2.SetAdd(offset) - o3 := uint32(0x4c0003c0) // jirl $r0, $r30, 0 + o3 := uint32(0x4c000280) // jirl $r0, $r20, 0 ctxt.Arch.ByteOrder.PutUint32(P[8:], o3) tramp.SetData(P) @@ -707,21 +873,21 @@ func gentrampgot(ctxt *ld.Link, ldr *loader.Loader, tramp *loader.SymbolBuilder, tramp.SetSize(12) // 3 instructions P := make([]byte, tramp.Size()) - o1 := uint32(0x1a00001e) // pcalau12i $r30, 0 + o1 := uint32(0x1a000014) // pcalau12i $r20, 0 ctxt.Arch.ByteOrder.PutUint32(P, o1) r1, _ := tramp.AddRel(objabi.R_LOONG64_GOT_HI) r1.SetOff(0) r1.SetSiz(4) r1.SetSym(target) - o2 := uint32(0x28c003de) // ld.d $r30, $r30, 0 + o2 := uint32(0x28c00294) // ld.d $r20, $r20, 0 ctxt.Arch.ByteOrder.PutUint32(P[4:], o2) r2, _ := tramp.AddRel(objabi.R_LOONG64_GOT_LO) r2.SetOff(4) r2.SetSiz(4) r2.SetSym(target) - o3 := uint32(0x4c0003c0) // jirl $r0, $r30, 0 + o3 := uint32(0x4c000280) // jirl $r0, $r20, 0 ctxt.Arch.ByteOrder.PutUint32(P[8:], o3) tramp.SetData(P) diff --git a/src/cmd/link/internal/mips64/asm.go b/src/cmd/link/internal/mips64/asm.go index a86ded65f289fc..6d582ba4c6e260 100644 --- a/src/cmd/link/internal/mips64/asm.go +++ b/src/cmd/link/internal/mips64/asm.go @@ -142,8 +142,6 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, // type uint8 // addend int64 - addend := r.Xadd - out.Write64(uint64(sectoff)) elfsym := ld.ElfSymForReloc(ctxt, r.Xsym) @@ -169,17 +167,11 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, out.Write8(uint8(elf.R_MIPS_HI16)) case objabi.R_ADDRMIPSTLS: out.Write8(uint8(elf.R_MIPS_TLS_TPREL_LO16)) - if ctxt.Target.IsOpenbsd() { - // OpenBSD mips64 does not currently offset TLS by 0x7000, - // as such we need to add this back to get the correct offset - // via the external linker. - addend += 0x7000 - } case objabi.R_CALLMIPS, objabi.R_JMPMIPS: out.Write8(uint8(elf.R_MIPS_26)) } - out.Write64(uint64(addend)) + out.Write64(uint64(r.Xadd)) return true } @@ -304,11 +296,6 @@ func archreloc(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, r loade case objabi.R_ADDRMIPSTLS: // thread pointer is at 0x7000 offset from the start of TLS data area t := ldr.SymValue(rs) + r.Add() - 0x7000 - if target.IsOpenbsd() { - // OpenBSD mips64 does not currently offset TLS by 0x7000, - // as such we need to add this back to get the correct offset. - t += 0x7000 - } if t < -32768 || t >= 32678 { ldr.Errorf(s, "TLS offset out of range %d", t) } diff --git a/src/cmd/link/internal/mips64/obj.go b/src/cmd/link/internal/mips64/obj.go index 193ad1f27110b8..96c46cffa2595c 100644 --- a/src/cmd/link/internal/mips64/obj.go +++ b/src/cmd/link/internal/mips64/obj.go @@ -63,7 +63,7 @@ func Init() (*sys.Arch, ld.Arch) { Linuxdynld: "/lib64/ld64.so.1", LinuxdynldMusl: musl, Freebsddynld: "XXX", - Openbsddynld: "/usr/libexec/ld.so", + Openbsddynld: "XXX", Netbsddynld: "XXX", Dragonflydynld: "XXX", Solarisdynld: "XXX", @@ -95,8 +95,7 @@ func archinit(ctxt *ld.Link) { *ld.FlagTextAddr = ld.Rnd(16*1024, *ld.FlagRound) + int64(ld.HEADR) } - case objabi.Hlinux, /* mips64 elf */ - objabi.Hopenbsd: + case objabi.Hlinux: /* mips64 elf */ ld.Elfinit(ctxt) ld.HEADR = ld.ELFRESERVE if *ld.FlagRound == -1 { diff --git a/src/cmd/link/internal/ppc64/asm.go b/src/cmd/link/internal/ppc64/asm.go index 5ceab3aa5a1255..36ba79f30a74f6 100644 --- a/src/cmd/link/internal/ppc64/asm.go +++ b/src/cmd/link/internal/ppc64/asm.go @@ -905,15 +905,20 @@ func xcoffreloc1(arch *sys.Arch, out *ld.OutBuf, ldr *loader.Loader, s loader.Sy } func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, r loader.ExtReloc, ri int, sectoff int64) bool { - // Beware that bit0~bit15 start from the third byte of an instruction in Big-Endian machines. rt := r.Type - if rt == objabi.R_ADDR || rt == objabi.R_POWER_TLS || rt == objabi.R_CALLPOWER || rt == objabi.R_DWARFSECREF { - } else { - if ctxt.Arch.ByteOrder == binary.BigEndian { - sectoff += 2 - } + fixupBe := int64(0) + // 32 bit Go relocations which translate into two 16 bit ELF relocations need to be adjusted + // to account for BE ordering. + if ctxt.Arch.ByteOrder == binary.BigEndian { + fixupBe = 2 + } + + // Helper to write one 64b ELF relocation entry. + writeElfReloc := func(rtyp elf.R_PPC64, offset int64, sym int32, addend int64) { + out.Write64(uint64(offset)) + out.Write64(uint64(rtyp) | uint64(sym)<<32) + out.Write64(uint64(addend)) } - out.Write64(uint64(sectoff)) elfsym := ld.ElfSymForReloc(ctxt, r.Xsym) switch rt { @@ -922,78 +927,68 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, case objabi.R_ADDR, objabi.R_DWARFSECREF: switch r.Size { case 4: - out.Write64(uint64(elf.R_PPC64_ADDR32) | uint64(elfsym)<<32) + writeElfReloc(elf.R_PPC64_ADDR32, sectoff, elfsym, r.Xadd) case 8: - out.Write64(uint64(elf.R_PPC64_ADDR64) | uint64(elfsym)<<32) + writeElfReloc(elf.R_PPC64_ADDR64, sectoff, elfsym, r.Xadd) default: return false } case objabi.R_ADDRPOWER_D34: - out.Write64(uint64(elf.R_PPC64_D34) | uint64(elfsym)<<32) + writeElfReloc(elf.R_PPC64_D34, sectoff, elfsym, r.Xadd) case objabi.R_ADDRPOWER_PCREL34: - out.Write64(uint64(elf.R_PPC64_PCREL34) | uint64(elfsym)<<32) + writeElfReloc(elf.R_PPC64_PCREL34, sectoff, elfsym, r.Xadd) case objabi.R_POWER_TLS: - out.Write64(uint64(elf.R_PPC64_TLS) | uint64(elfsym)<<32) + writeElfReloc(elf.R_PPC64_TLS, sectoff, elfsym, r.Xadd) case objabi.R_POWER_TLS_LE: - out.Write64(uint64(elf.R_PPC64_TPREL16_HA) | uint64(elfsym)<<32) - out.Write64(uint64(r.Xadd)) - out.Write64(uint64(sectoff + 4)) - out.Write64(uint64(elf.R_PPC64_TPREL16_LO) | uint64(elfsym)<<32) + sectoff += fixupBe + writeElfReloc(elf.R_PPC64_TPREL16_HA, sectoff, elfsym, r.Xadd) + writeElfReloc(elf.R_PPC64_TPREL16_LO, sectoff+4, elfsym, r.Xadd) case objabi.R_POWER_TLS_LE_TPREL34: - out.Write64(uint64(elf.R_PPC64_TPREL34) | uint64(elfsym)<<32) + writeElfReloc(elf.R_PPC64_TPREL34, sectoff, elfsym, r.Xadd) case objabi.R_POWER_TLS_IE_PCREL34: - out.Write64(uint64(elf.R_PPC64_GOT_TPREL_PCREL34) | uint64(elfsym)<<32) + writeElfReloc(elf.R_PPC64_GOT_TPREL_PCREL34, sectoff, elfsym, r.Xadd) case objabi.R_POWER_TLS_IE: - out.Write64(uint64(elf.R_PPC64_GOT_TPREL16_HA) | uint64(elfsym)<<32) - out.Write64(uint64(r.Xadd)) - out.Write64(uint64(sectoff + 4)) - out.Write64(uint64(elf.R_PPC64_GOT_TPREL16_LO_DS) | uint64(elfsym)<<32) + sectoff += fixupBe + writeElfReloc(elf.R_PPC64_GOT_TPREL16_HA, sectoff, elfsym, r.Xadd) + writeElfReloc(elf.R_PPC64_GOT_TPREL16_LO_DS, sectoff+4, elfsym, r.Xadd) case objabi.R_ADDRPOWER: - out.Write64(uint64(elf.R_PPC64_ADDR16_HA) | uint64(elfsym)<<32) - out.Write64(uint64(r.Xadd)) - out.Write64(uint64(sectoff + 4)) - out.Write64(uint64(elf.R_PPC64_ADDR16_LO) | uint64(elfsym)<<32) + sectoff += fixupBe + writeElfReloc(elf.R_PPC64_ADDR16_HA, sectoff, elfsym, r.Xadd) + writeElfReloc(elf.R_PPC64_ADDR16_LO, sectoff+4, elfsym, r.Xadd) case objabi.R_ADDRPOWER_DS: - out.Write64(uint64(elf.R_PPC64_ADDR16_HA) | uint64(elfsym)<<32) - out.Write64(uint64(r.Xadd)) - out.Write64(uint64(sectoff + 4)) - out.Write64(uint64(elf.R_PPC64_ADDR16_LO_DS) | uint64(elfsym)<<32) + sectoff += fixupBe + writeElfReloc(elf.R_PPC64_ADDR16_HA, sectoff, elfsym, r.Xadd) + writeElfReloc(elf.R_PPC64_ADDR16_LO_DS, sectoff+4, elfsym, r.Xadd) case objabi.R_ADDRPOWER_GOT: - out.Write64(uint64(elf.R_PPC64_GOT16_HA) | uint64(elfsym)<<32) - out.Write64(uint64(r.Xadd)) - out.Write64(uint64(sectoff + 4)) - out.Write64(uint64(elf.R_PPC64_GOT16_LO_DS) | uint64(elfsym)<<32) + sectoff += fixupBe + writeElfReloc(elf.R_PPC64_GOT16_HA, sectoff, elfsym, r.Xadd) + writeElfReloc(elf.R_PPC64_GOT16_LO_DS, sectoff+4, elfsym, r.Xadd) case objabi.R_ADDRPOWER_GOT_PCREL34: - out.Write64(uint64(elf.R_PPC64_GOT_PCREL34) | uint64(elfsym)<<32) + writeElfReloc(elf.R_PPC64_GOT_PCREL34, sectoff, elfsym, r.Xadd) case objabi.R_ADDRPOWER_PCREL: - out.Write64(uint64(elf.R_PPC64_REL16_HA) | uint64(elfsym)<<32) - out.Write64(uint64(r.Xadd)) - out.Write64(uint64(sectoff + 4)) - out.Write64(uint64(elf.R_PPC64_REL16_LO) | uint64(elfsym)<<32) - r.Xadd += 4 + sectoff += fixupBe + addend := r.Xadd + fixupBe + writeElfReloc(elf.R_PPC64_REL16_HA, sectoff, elfsym, addend) + writeElfReloc(elf.R_PPC64_REL16_LO, sectoff+4, elfsym, addend+4) case objabi.R_ADDRPOWER_TOCREL: - out.Write64(uint64(elf.R_PPC64_TOC16_HA) | uint64(elfsym)<<32) - out.Write64(uint64(r.Xadd)) - out.Write64(uint64(sectoff + 4)) - out.Write64(uint64(elf.R_PPC64_TOC16_LO) | uint64(elfsym)<<32) + sectoff += fixupBe + writeElfReloc(elf.R_PPC64_TOC16_HA, sectoff, elfsym, r.Xadd) + writeElfReloc(elf.R_PPC64_TOC16_LO, sectoff+4, elfsym, r.Xadd) case objabi.R_ADDRPOWER_TOCREL_DS: - out.Write64(uint64(elf.R_PPC64_TOC16_HA) | uint64(elfsym)<<32) - out.Write64(uint64(r.Xadd)) - out.Write64(uint64(sectoff + 4)) - out.Write64(uint64(elf.R_PPC64_TOC16_LO_DS) | uint64(elfsym)<<32) + sectoff += fixupBe + writeElfReloc(elf.R_PPC64_TOC16_HA, sectoff, elfsym, r.Xadd) + writeElfReloc(elf.R_PPC64_TOC16_LO_DS, sectoff+4, elfsym, r.Xadd) case objabi.R_CALLPOWER: if r.Size != 4 { return false } if !hasPCrel { - out.Write64(uint64(elf.R_PPC64_REL24) | uint64(elfsym)<<32) + writeElfReloc(elf.R_PPC64_REL24, sectoff, elfsym, r.Xadd) } else { // TOC is not used in PCrel compiled Go code. - out.Write64(uint64(elf.R_PPC64_REL24_NOTOC) | uint64(elfsym)<<32) + writeElfReloc(elf.R_PPC64_REL24_NOTOC, sectoff, elfsym, r.Xadd) } - } - out.Write64(uint64(r.Xadd)) return true } diff --git a/src/cmd/link/internal/ppc64/obj.go b/src/cmd/link/internal/ppc64/obj.go index 703c8ec2e85c0c..3a170d17bdab3a 100644 --- a/src/cmd/link/internal/ppc64/obj.go +++ b/src/cmd/link/internal/ppc64/obj.go @@ -44,7 +44,7 @@ func Init() (*sys.Arch, ld.Arch) { if buildcfg.GOARCH == "ppc64" { arch = sys.ArchPPC64 - dynld = "/lib64/ld64.so.1" + dynld = "/lib64/ld64.so.2" musl = "/lib/ld-musl-powerpc64.so.1" } diff --git a/src/cmd/link/internal/riscv64/obj.go b/src/cmd/link/internal/riscv64/obj.go index 940a8d611c8c17..87f4986823c4e2 100644 --- a/src/cmd/link/internal/riscv64/obj.go +++ b/src/cmd/link/internal/riscv64/obj.go @@ -38,7 +38,8 @@ func Init() (*sys.Arch, ld.Arch) { Machoreloc1: machoreloc1, ELF: ld.ELFArch{ - Linuxdynld: "/lib/ld.so.1", + Linuxdynld: "/lib/ld-linux-riscv64-lp64d.so.1", + LinuxdynldMusl: "/lib/ld-musl-riscv64.so.1", Freebsddynld: "/usr/libexec/ld-elf.so.1", Netbsddynld: "XXX", diff --git a/src/cmd/link/internal/s390x/asm.go b/src/cmd/link/internal/s390x/asm.go index dee03484102bb1..9a802f458b4494 100644 --- a/src/cmd/link/internal/s390x/asm.go +++ b/src/cmd/link/internal/s390x/asm.go @@ -37,6 +37,7 @@ import ( "cmd/link/internal/loader" "cmd/link/internal/sym" "debug/elf" + "log" ) // gentext generates assembly to append the local moduledata to the global @@ -87,7 +88,7 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade return false } - // Handle relocations found in ELF object files. + // Handle relocations found in ELF object files. case objabi.ElfRelocOffset + objabi.RelocType(elf.R_390_12), objabi.ElfRelocOffset + objabi.RelocType(elf.R_390_GOT12): ldr.Errorf(s, "s390x 12-bit relocations have not been implemented (relocation type %d)", r.Type()-objabi.ElfRelocOffset) @@ -100,9 +101,14 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade if targType == sym.SDYNIMPORT { ldr.Errorf(s, "unexpected R_390_nn relocation for dynamic symbol %s", ldr.SymName(targ)) } - su := ldr.MakeSymbolUpdater(s) su.SetRelocType(rIdx, objabi.R_ADDR) + if target.IsPIE() && target.IsInternal() { + // For internal linking PIE, this R_ADDR relocation cannot + // be resolved statically. We need to generate a dynamic + // relocation. Let the code below handle it. + break + } return true case objabi.ElfRelocOffset + objabi.RelocType(elf.R_390_PC16), @@ -209,6 +215,101 @@ func adddynrel(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade su.SetRelocAdd(rIdx, r.Add()+int64(ldr.SymGot(targ))+int64(r.Siz())) return true } + + // Reread the reloc to incorporate any changes in type above. + relocs := ldr.Relocs(s) + r = relocs.At(rIdx) + + switch r.Type() { + case objabi.R_CALL, objabi.R_PCRELDBL: + if targType != sym.SDYNIMPORT { + // nothing to do, the relocation will be laid out in reloc + return true + } + if target.IsExternal() { + // External linker will do this relocation. + return true + } + // Internal linking: build a PLT entry and redirect to it. + addpltsym(target, ldr, syms, targ) + su := ldr.MakeSymbolUpdater(s) + su.SetRelocSym(rIdx, syms.PLT) + su.SetRelocAdd(rIdx, r.Add()+int64(ldr.SymPlt(targ))) + return true + + case objabi.R_ADDR: + if ldr.SymType(s).IsText() && target.IsElf() { + // The code is asking for the address of an external + // function. We provide it with the address of the + // correspondent GOT symbol. + ld.AddGotSym(target, ldr, syms, targ, uint32(elf.R_390_GLOB_DAT)) + su := ldr.MakeSymbolUpdater(s) + su.SetRelocSym(rIdx, syms.GOT) + su.SetRelocAdd(rIdx, r.Add()+int64(ldr.SymGot(targ))) + return true + } + + // Process dynamic relocations for the data sections. + if target.IsPIE() && target.IsInternal() { + // When internally linking, generate dynamic relocations + // for all typical R_ADDR relocations. The exception + // are those R_ADDR that are created as part of generating + // the dynamic relocations and must be resolved statically. + // + // These synthetic static R_ADDR relocs must be skipped + // now, or else we will be caught in an infinite loop + // of generating synthetic relocs for our synthetic + // relocs. + switch ldr.SymName(s) { + case ".dynsym", ".rela", ".rela.plt", ".got.plt", ".dynamic": + return false + } + } else { + // Either internally linking a static executable, + // in which case we can resolve these relocations + // statically in the 'reloc' phase, or externally + // linking, in which case the relocation will be + // prepared in the 'reloc' phase and passed to the + // external linker in the 'asmb' phase. + if t := ldr.SymType(s); !t.IsDATA() && !t.IsRODATA() { + break + } + } + + if target.IsElf() { + // Generate R_390_RELATIVE relocations for best + // efficiency in the dynamic linker. + // + // As noted above, symbol addresses have not been + // assigned yet, so we can't generate the final reloc + // entry yet. We ultimately want: + // + // r_offset = s + r.Off + // r_info = R_390_RELATIVE + // r_addend = targ + r.Add + // + // The dynamic linker will set *offset = base address + + // addend. + // + // AddAddrPlus is used for r_offset and r_addend to + // generate new R_ADDR relocations that will update + // these fields in the 'reloc' phase. + rela := ldr.MakeSymbolUpdater(syms.Rela) + rela.AddAddrPlus(target.Arch, s, int64(r.Off())) + if r.Siz() == 8 { + rela.AddUint64(target.Arch, elf.R_INFO(0, uint32(elf.R_390_RELATIVE))) + } else { + ldr.Errorf(s, "unexpected relocation for dynamic symbol %s", ldr.SymName(targ)) + } + rela.AddAddrPlus(target.Arch, targ, r.Add()) + // Not mark r done here. So we still apply it statically, + // so in the file content we'll also have the right offset + // to the relocation target. So it can be examined statically + // (e.g. go version). + return true + } + } + // Handle references to ELF symbols from our own object files. return targType != sym.SDYNIMPORT } @@ -309,7 +410,7 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, return true } -func elfsetupplt(ctxt *ld.Link, ldr *loader.Loader, plt, got *loader.SymbolBuilder, dynamic loader.Sym) { +func elfsetupplt(ctxt *ld.Link, ldr *loader.Loader, plt, gotplt *loader.SymbolBuilder, dynamic loader.Sym) { if plt.Size() == 0 { // stg %r1,56(%r15) plt.AddUint8(0xe3) @@ -321,7 +422,7 @@ func elfsetupplt(ctxt *ld.Link, ldr *loader.Loader, plt, got *loader.SymbolBuild // larl %r1,_GLOBAL_OFFSET_TABLE_ plt.AddUint8(0xc0) plt.AddUint8(0x10) - plt.AddSymRef(ctxt.Arch, got.Sym(), 6, objabi.R_PCRELDBL, 4) + plt.AddSymRef(ctxt.Arch, gotplt.Sym(), 6, objabi.R_PCRELDBL, 4) // mvc 48(8,%r15),8(%r1) plt.AddUint8(0xd2) plt.AddUint8(0x07) @@ -349,11 +450,11 @@ func elfsetupplt(ctxt *ld.Link, ldr *loader.Loader, plt, got *loader.SymbolBuild plt.AddUint8(0x07) plt.AddUint8(0x00) - // assume got->size == 0 too - got.AddAddrPlus(ctxt.Arch, dynamic, 0) + // assume gotplt.size == 0 too + gotplt.AddAddrPlus(ctxt.Arch, dynamic, 0) - got.AddUint64(ctxt.Arch, 0) - got.AddUint64(ctxt.Arch, 0) + gotplt.AddUint64(ctxt.Arch, 0) + gotplt.AddUint64(ctxt.Arch, 0) } } @@ -391,7 +492,7 @@ func addpltsym(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade if target.IsElf() { plt := ldr.MakeSymbolUpdater(syms.PLT) - got := ldr.MakeSymbolUpdater(syms.GOT) + gotplt := ldr.MakeSymbolUpdater(syms.GOTPLT) rela := ldr.MakeSymbolUpdater(syms.RelaPLT) if plt.Size() == 0 { panic("plt is not set up") @@ -400,12 +501,12 @@ func addpltsym(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade plt.AddUint8(0xc0) plt.AddUint8(0x10) - plt.AddPCRelPlus(target.Arch, got.Sym(), got.Size()+6) + plt.AddPCRelPlus(target.Arch, gotplt.Sym(), gotplt.Size()+6) pltrelocs := plt.Relocs() ldr.SetRelocVariant(plt.Sym(), pltrelocs.Count()-1, sym.RV_390_DBL) - // add to got: pointer to current pos in plt - got.AddAddrPlus(target.Arch, plt.Sym(), plt.Size()+8) // weird but correct + // add to gotplt: pointer to current pos in plt + gotplt.AddAddrPlus(target.Arch, plt.Sym(), plt.Size()+8) // weird but correct // lg %r1,0(%r1) plt.AddUint8(0xe3) plt.AddUint8(0x10) @@ -435,7 +536,7 @@ func addpltsym(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade plt.AddUint32(target.Arch, uint32(rela.Size())) // rela size before current entry // rela - rela.AddAddrPlus(target.Arch, got.Sym(), got.Size()-8) + rela.AddAddrPlus(target.Arch, gotplt.Sym(), gotplt.Size()-8) sDynid := ldr.SymDynid(s) rela.AddUint64(target.Arch, elf.R_INFO(uint32(sDynid), uint32(elf.R_390_JMP_SLOT))) @@ -447,3 +548,53 @@ func addpltsym(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, s loade ldr.Errorf(s, "addpltsym: unsupported binary format") } } + +// tlsIEtoLE converts TLS Initial Exec (IE) relocation to TLS Local Exec (LE). +// +// On s390x, the TLS IE sequence is: +// +// LARL %rN, @INDNTPOFF ; 6 bytes - load address of GOT entry +// LG %rN, 0(%rN) ; 6 bytes - load offset from GOT +// +// We convert this to TLS LE by replacing it with: +// +// LGFI %rN, ; 6 bytes - load 32-bit sign-extended immediate +// BCR 0,0 ; 2 bytes - NOP +// BCR 0,0 ; 2 bytes - NOP +// BCR 0,0 ; 2 bytes - NOP +// +// The relocation offset points to byte 2 of the LARL instruction (the immediate field). +func tlsIEtoLE(P []byte, off, size int) { + // off is the offset of the relocation within the instruction sequence, + // which is at byte 2 of the LARL instruction (the 4-byte immediate). + // We need to work with the beginning of LARL (off-2) through LG (off+10). + + if off < 2 { + log.Fatalf("R_390_TLS_IEENT relocation at offset %d is too small", off) + } + + // Verify we have a LARL instruction (opcode 0xC0, second nibble 0x0) + // LARL format: C0 R0 I2 I2 I2 I2 (where R is register, I2 is 32-bit immediate) + if P[off-2] != 0xc0 || P[off-1]&0x0f != 0x00 { + log.Fatalf("R_390_TLS_IEENT relocation not preceded by LARL instruction: %02x %02x", P[off-2], P[off-1]) + } + + // Extract the register from LARL (upper nibble of second byte) + reg := P[off-1] >> 4 + + // Convert LARL to LGFI: change opcode from C0x0 to C0x1 + // LGFI format: C0 R1 I2 I2 I2 I2 + P[off-1] = (reg << 4) | 0x01 + + // The immediate field (bytes off to off+3) will be filled in by the linker + // with the TLS offset value. + + // Replace the LG instruction (6 bytes starting at off+4) with NOPs + // BCR 0,0 = 0x07 0x00 (2 bytes each, need 3 of them) + P[off+4] = 0x07 + P[off+5] = 0x00 + P[off+6] = 0x07 + P[off+7] = 0x00 + P[off+8] = 0x07 + P[off+9] = 0x00 +} diff --git a/src/cmd/link/internal/s390x/obj.go b/src/cmd/link/internal/s390x/obj.go index 76aa962a82b954..e20b25680d0edf 100644 --- a/src/cmd/link/internal/s390x/obj.go +++ b/src/cmd/link/internal/s390x/obj.go @@ -52,9 +52,10 @@ func Init() (*sys.Arch, ld.Arch) { Archrelocvariant: archrelocvariant, Gentext: gentext, Machoreloc1: machoreloc1, + TLSIEtoLE: tlsIEtoLE, ELF: ld.ELFArch{ - Linuxdynld: "/lib64/ld64.so.1", + Linuxdynld: "/lib/ld64.so.1", LinuxdynldMusl: "/lib/ld-musl-s390x.so.1", // not relevant for s390x diff --git a/src/cmd/link/internal/sym/segment.go b/src/cmd/link/internal/sym/segment.go index c889e71ad64b8b..d397b8457076c0 100644 --- a/src/cmd/link/internal/sym/segment.go +++ b/src/cmd/link/internal/sym/segment.go @@ -52,7 +52,7 @@ type Section struct { Vaddr uint64 Length uint64 Seg *Segment - Elfsect interface{} // an *ld.ElfShdr + Elfsect any // an *ld.ElfShdr Reloff uint64 Rellen uint64 // Relcount is the number of *host* relocations applied to this section diff --git a/src/cmd/link/internal/sym/symkind.go b/src/cmd/link/internal/sym/symkind.go index 0671d9d724d25d..e61c9650fe02e9 100644 --- a/src/cmd/link/internal/sym/symkind.go +++ b/src/cmd/link/internal/sym/symkind.go @@ -41,98 +41,92 @@ type SymKind uint8 // //go:generate stringer -type=SymKind const ( + // An otherwise invalid zero value for the type. Sxxx SymKind = iota - STEXT - STEXTFIPSSTART - STEXTFIPS - STEXTFIPSEND - STEXTEND - SELFRXSECT - SMACHOPLT - - // Read-only sections. - STYPE - SSTRING - SGOSTRING - SGOFUNC - SGCBITS - SRODATA - SRODATAFIPSSTART - SRODATAFIPS - SRODATAFIPSEND - SRODATAEND - SFUNCTAB - - SELFROSECT - - // Read-only sections with relocations. + // The text segment, containing executable instructions. + STEXT // General executable code. + STEXTFIPSSTART // Start of FIPS text section. + STEXTFIPS // Instructions hashed for FIPS checks. + STEXTFIPSEND // End of FIPS text section. + STEXTEND // End of text section. + SELFRXSECT // Executable PLT; PPC64 .glink. + SMACHOPLT // Mach-O PLT. + + // Read-only, non-executable, unrelocated segment. + SSTRING // Used only for XCOFF runtime.rodata symbol? + SGOSTRING // Go string constants. + SGCBITS // GC bit masks and programs. + SRODATA // General read-only data. + SRODATAFIPSSTART // Start of FIPS read-only data. + SRODATAFIPS // FIPS read-only data. + SRODATAFIPSEND // End of FIPS read-only data. + SRODATAEND // End of read-only data. + SPCLNTAB // Pclntab data. + SELFROSECT // ELF read-only data: relocs, dynamic linking info. + + // Read-only, non-executable, dynamically relocatable segment. + // + // This segment holds read-only data that contains pointers to + // other parts of the program. When generating a position + // independent executable or a shared library, these sections + // are "relro", meaning that they start as writable, and are + // changed to be read-only after dynamic relocations are applied. // - // Types STYPE-SFUNCTAB above are written to the .rodata section by default. - // When linking a shared object, some conceptually "read only" types need to - // be written to by relocations and putting them in a section called - // ".rodata" interacts poorly with the system linkers. The GNU linkers - // support this situation by arranging for sections of the name - // ".data.rel.ro.XXX" to be mprotected read only by the dynamic linker after - // relocations have applied, so when the Go linker is creating a shared - // object it checks all objects of the above types and bumps any object that - // has a relocation to it to the corresponding type below, which are then - // written to sections with appropriate magic names. - STYPERELRO - SSTRINGRELRO - SGOSTRINGRELRO - SGOFUNCRELRO - SGCBITSRELRO + // When no dynamic relocations are required, as when generating + // an executable that is not position independent, this is just + // part of the normal read-only segment. SRODATARELRO - SFUNCTABRELRO - SELFRELROSECT - SMACHORELROSECT - - // Part of .data.rel.ro if it exists, otherwise part of .rodata. - STYPELINK - SITABLINK - SSYMTAB - SPCLNTAB + STYPE + SGOFUNC + SELFRELROSECT // ELF-specific read-only relocatable: PLT, etc. + SMACHORELROSECT // Mach-O specific read-only relocatable. - // Writable sections. + // Allocated writable segment. SFirstWritable - SBUILDINFO - SFIPSINFO - SELFSECT - SMACHO - SMACHOGOT - SWINDOWS - SELFGOT - SNOPTRDATA - SNOPTRDATAFIPSSTART - SNOPTRDATAFIPS - SNOPTRDATAFIPSEND - SNOPTRDATAEND - SINITARR - SDATA - SDATAFIPSSTART - SDATAFIPS - SDATAFIPSEND - SDATAEND - SXCOFFTOC - SBSS - SNOPTRBSS - SLIBFUZZER_8BIT_COUNTER - SCOVERAGE_COUNTER - SCOVERAGE_AUXVAR - STLSBSS - SXREF - SMACHOSYMSTR - SMACHOSYMTAB - SMACHOINDIRECTPLT - SMACHOINDIRECTGOT - SFILEPATH - SDYNIMPORT - SHOSTOBJ - SUNDEFEXT // Undefined symbol for resolution by external linker - - // Sections for debugging information + SBUILDINFO // debug/buildinfo data (why is this writable?). + SFIPSINFO // go:fipsinfo aka crypto/internal/fips140/check.Linkinfo (why is this writable)? + SELFSECT // .got.plt, .plt, .dynamic where appropriate. + SMACHO // Used only for .llvmasm? + SWINDOWS // Windows dynamic symbols. + SMODULEDATA // Linker generated moduledata struct. + SELFGOT // Writable ELF GOT section. + SMACHOGOT // Mach-O GOT. + SNOPTRDATA // Data with no heap pointers. + SNOPTRDATAFIPSSTART // Start of FIPS non-pointer writable data. + SNOPTRDATAFIPS // FIPS non-pointer writable data. + SNOPTRDATAFIPSEND // End of FIPS non-pointer writable data. + SNOPTRDATAEND // End of data with no heap pointers. + SINITARR // ELF .init_array section. + SDATA // Data that may have heap pointers. + SDATAFIPSSTART // Start of FIPS writable data. + SDATAFIPS // FIPS writable data. + SDATAFIPSEND // End of FIPS writable data. + SDATAEND // End of data that may have heap pointers. + SXCOFFTOC // AIX TOC entries. + + // Allocated zero-initialized segment. + SBSS // Zeroed data that may have heap pointers. + SNOPTRBSS // Zeroed data with no heap pointers. + SGCMASK // Pointers to generated GC masks. + SLIBFUZZER_8BIT_COUNTER // Fuzzer counters. + SCOVERAGE_COUNTER // Coverage counters. + SCOVERAGE_AUXVAR // Compiler generated coverage symbols. + STLSBSS // Thread-local zeroed data. + + // Unallocated segment. + SFirstUnallocated + SXREF // Reference from non-Go object file. + SMACHOSYMSTR // Mach-O string table. + SMACHOSYMTAB // Mach-O symbol table. + SMACHOINDIRECTPLT // Mach-O indirect PLT. + SMACHOINDIRECTGOT // Mach-O indirect GOT. + SDYNIMPORT // Reference to symbol defined in shared library. + SHOSTOBJ // Symbol defined in non-Go object file. + SUNDEFEXT // Undefined symbol for resolution by external linker. + + // Unallocated DWARF debugging segment. SDWARFSECT - // DWARF symbol types + // DWARF symbol types created by compiler or linker. SDWARFCUINFO SDWARFCONST SDWARFFCN @@ -144,9 +138,9 @@ const ( SDWARFLINES SDWARFADDR - // SEH symbol types - SSEHUNWINDINFO - SSEHSECT + // SEH symbol types. These are probably allocated at run time. + SSEHUNWINDINFO // Compiler generated Windows SEH info. + SSEHSECT // Windows SEH data. ) // AbiSymKindToSymKind maps values read from object files (which are @@ -180,33 +174,17 @@ var AbiSymKindToSymKind = [...]SymKind{ objabi.SSEHUNWINDINFO: SSEHUNWINDINFO, } -// ReadOnly are the symbol kinds that form read-only sections. In some -// cases, if they will require relocations, they are transformed into -// rel-ro sections using relROMap. +// ReadOnly are the symbol kinds that form read-only sections +// that never require runtime relocations. var ReadOnly = []SymKind{ - STYPE, SSTRING, SGOSTRING, - SGOFUNC, SGCBITS, SRODATA, SRODATAFIPSSTART, SRODATAFIPS, SRODATAFIPSEND, SRODATAEND, - SFUNCTAB, -} - -// RelROMap describes the transformation of read-only symbols to rel-ro -// symbols. -var RelROMap = map[SymKind]SymKind{ - STYPE: STYPERELRO, - SSTRING: SSTRINGRELRO, - SGOSTRING: SGOSTRINGRELRO, - SGOFUNC: SGOFUNCRELRO, - SGCBITS: SGCBITSRELRO, - SRODATA: SRODATARELRO, - SFUNCTAB: SFUNCTABRELRO, } // IsText returns true if t is a text type. diff --git a/src/cmd/link/internal/sym/symkind_string.go b/src/cmd/link/internal/sym/symkind_string.go index 5395c9571ba8b8..5f5da3bee87910 100644 --- a/src/cmd/link/internal/sym/symkind_string.go +++ b/src/cmd/link/internal/sym/symkind_string.go @@ -16,88 +16,81 @@ func _() { _ = x[STEXTEND-5] _ = x[SELFRXSECT-6] _ = x[SMACHOPLT-7] - _ = x[STYPE-8] - _ = x[SSTRING-9] - _ = x[SGOSTRING-10] - _ = x[SGOFUNC-11] - _ = x[SGCBITS-12] - _ = x[SRODATA-13] - _ = x[SRODATAFIPSSTART-14] - _ = x[SRODATAFIPS-15] - _ = x[SRODATAFIPSEND-16] - _ = x[SRODATAEND-17] - _ = x[SFUNCTAB-18] - _ = x[SELFROSECT-19] - _ = x[STYPERELRO-20] - _ = x[SSTRINGRELRO-21] - _ = x[SGOSTRINGRELRO-22] - _ = x[SGOFUNCRELRO-23] - _ = x[SGCBITSRELRO-24] - _ = x[SRODATARELRO-25] - _ = x[SFUNCTABRELRO-26] - _ = x[SELFRELROSECT-27] - _ = x[SMACHORELROSECT-28] - _ = x[STYPELINK-29] - _ = x[SITABLINK-30] - _ = x[SSYMTAB-31] - _ = x[SPCLNTAB-32] - _ = x[SFirstWritable-33] - _ = x[SBUILDINFO-34] - _ = x[SFIPSINFO-35] - _ = x[SELFSECT-36] - _ = x[SMACHO-37] - _ = x[SMACHOGOT-38] - _ = x[SWINDOWS-39] - _ = x[SELFGOT-40] - _ = x[SNOPTRDATA-41] - _ = x[SNOPTRDATAFIPSSTART-42] - _ = x[SNOPTRDATAFIPS-43] - _ = x[SNOPTRDATAFIPSEND-44] - _ = x[SNOPTRDATAEND-45] - _ = x[SINITARR-46] - _ = x[SDATA-47] - _ = x[SDATAFIPSSTART-48] - _ = x[SDATAFIPS-49] - _ = x[SDATAFIPSEND-50] - _ = x[SDATAEND-51] - _ = x[SXCOFFTOC-52] - _ = x[SBSS-53] - _ = x[SNOPTRBSS-54] - _ = x[SLIBFUZZER_8BIT_COUNTER-55] - _ = x[SCOVERAGE_COUNTER-56] - _ = x[SCOVERAGE_AUXVAR-57] - _ = x[STLSBSS-58] - _ = x[SXREF-59] - _ = x[SMACHOSYMSTR-60] - _ = x[SMACHOSYMTAB-61] - _ = x[SMACHOINDIRECTPLT-62] - _ = x[SMACHOINDIRECTGOT-63] - _ = x[SFILEPATH-64] - _ = x[SDYNIMPORT-65] - _ = x[SHOSTOBJ-66] - _ = x[SUNDEFEXT-67] - _ = x[SDWARFSECT-68] - _ = x[SDWARFCUINFO-69] - _ = x[SDWARFCONST-70] - _ = x[SDWARFFCN-71] - _ = x[SDWARFABSFCN-72] - _ = x[SDWARFTYPE-73] - _ = x[SDWARFVAR-74] - _ = x[SDWARFRANGE-75] - _ = x[SDWARFLOC-76] - _ = x[SDWARFLINES-77] - _ = x[SDWARFADDR-78] - _ = x[SSEHUNWINDINFO-79] - _ = x[SSEHSECT-80] + _ = x[SSTRING-8] + _ = x[SGOSTRING-9] + _ = x[SGCBITS-10] + _ = x[SRODATA-11] + _ = x[SRODATAFIPSSTART-12] + _ = x[SRODATAFIPS-13] + _ = x[SRODATAFIPSEND-14] + _ = x[SRODATAEND-15] + _ = x[SPCLNTAB-16] + _ = x[SELFROSECT-17] + _ = x[SRODATARELRO-18] + _ = x[STYPE-19] + _ = x[SGOFUNC-20] + _ = x[SELFRELROSECT-21] + _ = x[SMACHORELROSECT-22] + _ = x[SFirstWritable-23] + _ = x[SBUILDINFO-24] + _ = x[SFIPSINFO-25] + _ = x[SELFSECT-26] + _ = x[SMACHO-27] + _ = x[SWINDOWS-28] + _ = x[SMODULEDATA-29] + _ = x[SELFGOT-30] + _ = x[SMACHOGOT-31] + _ = x[SNOPTRDATA-32] + _ = x[SNOPTRDATAFIPSSTART-33] + _ = x[SNOPTRDATAFIPS-34] + _ = x[SNOPTRDATAFIPSEND-35] + _ = x[SNOPTRDATAEND-36] + _ = x[SINITARR-37] + _ = x[SDATA-38] + _ = x[SDATAFIPSSTART-39] + _ = x[SDATAFIPS-40] + _ = x[SDATAFIPSEND-41] + _ = x[SDATAEND-42] + _ = x[SXCOFFTOC-43] + _ = x[SBSS-44] + _ = x[SNOPTRBSS-45] + _ = x[SGCMASK-46] + _ = x[SLIBFUZZER_8BIT_COUNTER-47] + _ = x[SCOVERAGE_COUNTER-48] + _ = x[SCOVERAGE_AUXVAR-49] + _ = x[STLSBSS-50] + _ = x[SFirstUnallocated-51] + _ = x[SXREF-52] + _ = x[SMACHOSYMSTR-53] + _ = x[SMACHOSYMTAB-54] + _ = x[SMACHOINDIRECTPLT-55] + _ = x[SMACHOINDIRECTGOT-56] + _ = x[SDYNIMPORT-57] + _ = x[SHOSTOBJ-58] + _ = x[SUNDEFEXT-59] + _ = x[SDWARFSECT-60] + _ = x[SDWARFCUINFO-61] + _ = x[SDWARFCONST-62] + _ = x[SDWARFFCN-63] + _ = x[SDWARFABSFCN-64] + _ = x[SDWARFTYPE-65] + _ = x[SDWARFVAR-66] + _ = x[SDWARFRANGE-67] + _ = x[SDWARFLOC-68] + _ = x[SDWARFLINES-69] + _ = x[SDWARFADDR-70] + _ = x[SSEHUNWINDINFO-71] + _ = x[SSEHSECT-72] } -const _SymKind_name = "SxxxSTEXTSTEXTFIPSSTARTSTEXTFIPSSTEXTFIPSENDSTEXTENDSELFRXSECTSMACHOPLTSTYPESSTRINGSGOSTRINGSGOFUNCSGCBITSSRODATASRODATAFIPSSTARTSRODATAFIPSSRODATAFIPSENDSRODATAENDSFUNCTABSELFROSECTSTYPERELROSSTRINGRELROSGOSTRINGRELROSGOFUNCRELROSGCBITSRELROSRODATARELROSFUNCTABRELROSELFRELROSECTSMACHORELROSECTSTYPELINKSITABLINKSSYMTABSPCLNTABSFirstWritableSBUILDINFOSFIPSINFOSELFSECTSMACHOSMACHOGOTSWINDOWSSELFGOTSNOPTRDATASNOPTRDATAFIPSSTARTSNOPTRDATAFIPSSNOPTRDATAFIPSENDSNOPTRDATAENDSINITARRSDATASDATAFIPSSTARTSDATAFIPSSDATAFIPSENDSDATAENDSXCOFFTOCSBSSSNOPTRBSSSLIBFUZZER_8BIT_COUNTERSCOVERAGE_COUNTERSCOVERAGE_AUXVARSTLSBSSSXREFSMACHOSYMSTRSMACHOSYMTABSMACHOINDIRECTPLTSMACHOINDIRECTGOTSFILEPATHSDYNIMPORTSHOSTOBJSUNDEFEXTSDWARFSECTSDWARFCUINFOSDWARFCONSTSDWARFFCNSDWARFABSFCNSDWARFTYPESDWARFVARSDWARFRANGESDWARFLOCSDWARFLINESSDWARFADDRSSEHUNWINDINFOSSEHSECT" +const _SymKind_name = "SxxxSTEXTSTEXTFIPSSTARTSTEXTFIPSSTEXTFIPSENDSTEXTENDSELFRXSECTSMACHOPLTSSTRINGSGOSTRINGSGCBITSSRODATASRODATAFIPSSTARTSRODATAFIPSSRODATAFIPSENDSRODATAENDSPCLNTABSELFROSECTSRODATARELROSTYPESGOFUNCSELFRELROSECTSMACHORELROSECTSFirstWritableSBUILDINFOSFIPSINFOSELFSECTSMACHOSWINDOWSSMODULEDATASELFGOTSMACHOGOTSNOPTRDATASNOPTRDATAFIPSSTARTSNOPTRDATAFIPSSNOPTRDATAFIPSENDSNOPTRDATAENDSINITARRSDATASDATAFIPSSTARTSDATAFIPSSDATAFIPSENDSDATAENDSXCOFFTOCSBSSSNOPTRBSSSGCMASKSLIBFUZZER_8BIT_COUNTERSCOVERAGE_COUNTERSCOVERAGE_AUXVARSTLSBSSSFirstUnallocatedSXREFSMACHOSYMSTRSMACHOSYMTABSMACHOINDIRECTPLTSMACHOINDIRECTGOTSDYNIMPORTSHOSTOBJSUNDEFEXTSDWARFSECTSDWARFCUINFOSDWARFCONSTSDWARFFCNSDWARFABSFCNSDWARFTYPESDWARFVARSDWARFRANGESDWARFLOCSDWARFLINESSDWARFADDRSSEHUNWINDINFOSSEHSECT" -var _SymKind_index = [...]uint16{0, 4, 9, 23, 32, 44, 52, 62, 71, 76, 83, 92, 99, 106, 113, 129, 140, 154, 164, 172, 182, 192, 204, 218, 230, 242, 254, 267, 280, 295, 304, 313, 320, 328, 342, 352, 361, 369, 375, 384, 392, 399, 409, 428, 442, 459, 472, 480, 485, 499, 508, 520, 528, 537, 541, 550, 573, 590, 606, 613, 618, 630, 642, 659, 676, 685, 695, 703, 712, 722, 734, 745, 754, 766, 776, 785, 796, 805, 816, 826, 840, 848} +var _SymKind_index = [...]uint16{0, 4, 9, 23, 32, 44, 52, 62, 71, 78, 87, 94, 101, 117, 128, 142, 152, 160, 170, 182, 187, 194, 207, 222, 236, 246, 255, 263, 269, 277, 288, 295, 304, 314, 333, 347, 364, 377, 385, 390, 404, 413, 425, 433, 442, 446, 455, 462, 485, 502, 518, 525, 542, 547, 559, 571, 588, 605, 615, 623, 632, 642, 654, 665, 674, 686, 696, 705, 716, 725, 736, 746, 760, 768} func (i SymKind) String() string { - if i >= SymKind(len(_SymKind_index)-1) { + idx := int(i) - 0 + if i < 0 || idx >= len(_SymKind_index)-1 { return "SymKind(" + strconv.FormatInt(int64(i), 10) + ")" } - return _SymKind_name[_SymKind_index[i]:_SymKind_index[i+1]] + return _SymKind_name[_SymKind_index[idx]:_SymKind_index[idx+1]] } diff --git a/src/cmd/link/internal/wasm/asm.go b/src/cmd/link/internal/wasm/asm.go index 2ddf5b33ba273a..d8f4a3cd9d0184 100644 --- a/src/cmd/link/internal/wasm/asm.go +++ b/src/cmd/link/internal/wasm/asm.go @@ -20,10 +20,11 @@ import ( ) const ( - I32 = 0x7F - I64 = 0x7E - F32 = 0x7D - F64 = 0x7C + I32 = 0x7F + I64 = 0x7E + F32 = 0x7D + F64 = 0x7C + V128 = 0x7B ) const ( @@ -125,9 +126,9 @@ var dataSects []wasmDataSect func asmb(ctxt *ld.Link, ldr *loader.Loader) { sections := []*sym.Section{ ldr.SymSect(ldr.Lookup("runtime.rodata", 0)), - ldr.SymSect(ldr.Lookup("runtime.typelink", 0)), - ldr.SymSect(ldr.Lookup("runtime.itablink", 0)), - ldr.SymSect(ldr.Lookup("runtime.symtab", 0)), + ldr.SymSect(ldr.Lookup("runtime.types", 0)), + ldr.SymSect(ldr.Lookup("go:funcdesc", 0)), + ldr.SymSect(ldr.Lookup("runtime.firstmoduledata", 0)), ldr.SymSect(ldr.Lookup("runtime.pclntab", 0)), ldr.SymSect(ldr.Lookup("runtime.noptrdata", 0)), ldr.SymSect(ldr.Lookup("runtime.data", 0)), @@ -698,6 +699,8 @@ func fieldsToTypes(fields []obj.WasmField) []byte { b[i] = F32 case obj.WasmF64: b[i] = F64 + case obj.WasmV128: + b[i] = V128 default: panic(fmt.Sprintf("fieldsToTypes: unknown field type: %d", f.Type)) } diff --git a/src/cmd/link/internal/x86/asm.go b/src/cmd/link/internal/x86/asm.go index 036514819a0b06..2c38473702f646 100644 --- a/src/cmd/link/internal/x86/asm.go +++ b/src/cmd/link/internal/x86/asm.go @@ -72,6 +72,9 @@ func gentext(ctxt *ld.Link, ldr *loader.Loader) { {"di", 7}, } { thunkfunc := ldr.CreateSymForUpdate("__x86.get_pc_thunk."+r.name, 0) + if t := thunkfunc.Type(); t != 0 && t != sym.SXREF && t != sym.SDYNIMPORT && t != sym.SUNDEFEXT { + continue // symbol already exists, probably loaded from a C object + } thunkfunc.SetType(sym.STEXT) ldr.SetAttrLocal(thunkfunc.Sym(), true) o := func(op ...uint8) { diff --git a/src/cmd/link/link_test.go b/src/cmd/link/link_test.go index 31822d21f39d31..e7c406c4ad1eb8 100644 --- a/src/cmd/link/link_test.go +++ b/src/cmd/link/link_test.go @@ -7,10 +7,15 @@ package main import ( "bufio" "bytes" + "debug/elf" "debug/macho" + "debug/pe" "errors" + "internal/abi" + "internal/buildcfg" "internal/platform" "internal/testenv" + "internal/xcoff" "os" "os/exec" "path/filepath" @@ -19,12 +24,90 @@ import ( "strconv" "strings" "testing" + "unsafe" imacho "cmd/internal/macho" "cmd/internal/objfile" "cmd/internal/sys" ) +// TestMain allows this test binary to run as a -toolexec wrapper for +// the 'go' command. If LINK_TEST_TOOLEXEC is set, TestMain runs the +// binary as if it were cmd/link, and otherwise runs the requested +// tool as a subprocess. +// +// This allows the test to verify the behavior of the current contents of the +// cmd/link package even if the installed cmd/link binary is stale. +func TestMain(m *testing.M) { + // Are we running as a toolexec wrapper? If so then run either + // the correct tool or this executable itself (for the linker). + // Running as toolexec wrapper. + if os.Getenv("LINK_TEST_TOOLEXEC") != "" { + if strings.TrimSuffix(filepath.Base(os.Args[1]), ".exe") == "link" { + // Running as a -toolexec linker, and the tool is cmd/link. + // Substitute this test binary for the linker. + os.Args = os.Args[1:] + main() + os.Exit(0) + } + // Running some other tool. + cmd := exec.Command(os.Args[1], os.Args[2:]...) + cmd.Stdin = os.Stdin + cmd.Stdout = os.Stdout + cmd.Stderr = os.Stderr + if err := cmd.Run(); err != nil { + os.Exit(1) + } + os.Exit(0) + } + + // Are we being asked to run as the linker (without toolexec)? + // If so then kick off main. + if os.Getenv("LINK_TEST_EXEC_LINKER") != "" { + main() + os.Exit(0) + } + + if testExe, err := os.Executable(); err == nil { + // on wasm, some phones, we expect an error from os.Executable() + testLinker = testExe + } + + // Not running as a -toolexec wrapper or as a linker executable. + // Just run the tests. + os.Exit(m.Run()) +} + +// testLinker is the path of the test executable being run. +// This is used by [TestScript]. +var testLinker string + +// goCmd returns a [*exec.Cmd] that runs the go tool using +// the current linker sources rather than the installed linker. +// The first element of the args parameter should be the go subcommand +// to run, such as "build" or "run". It must be a subcommand that +// takes the go command's build flags. +func goCmd(t *testing.T, args ...string) *exec.Cmd { + goArgs := []string{args[0], "-toolexec", testenv.Executable(t)} + args = append(goArgs, args[1:]...) + cmd := testenv.Command(t, testenv.GoToolPath(t), args...) + cmd = testenv.CleanCmdEnv(cmd) + cmd.Env = append(cmd.Env, "LINK_TEST_TOOLEXEC=1") + return cmd +} + +// linkCmd returns a [*exec.Cmd] that runs the linker built from +// the current sources. This is like "go tool link", but runs the +// current linker rather than the installed one. +func linkCmd(t *testing.T, args ...string) *exec.Cmd { + // Set up the arguments that TestMain looks for. + args = append([]string{"link"}, args...) + cmd := testenv.Command(t, testenv.Executable(t), args...) + cmd = testenv.CleanCmdEnv(cmd) + cmd.Env = append(cmd.Env, "LINK_TEST_TOOLEXEC=1") + return cmd +} + var AuthorPaidByTheColumnInch struct { fog int `text:"London. Michaelmas term lately over, and the Lord Chancellor sitting in Lincoln’s Inn Hall. Implacable November weather. As much mud in the streets as if the waters had but newly retired from the face of the earth, and it would not be wonderful to meet a Megalosaurus, forty feet long or so, waddling like an elephantine lizard up Holborn Hill. Smoke lowering down from chimney-pots, making a soft black drizzle, with flakes of soot in it as big as full-grown snowflakes—gone into mourning, one might imagine, for the death of the sun. Dogs, undistinguishable in mire. Horses, scarcely better; splashed to their very blinkers. Foot passengers, jostling one another’s umbrellas in a general infection of ill temper, and losing their foot-hold at street-corners, where tens of thousands of other foot passengers have been slipping and sliding since the day broke (if this day ever broke), adding new deposits to the crust upon crust of mud, sticking at those points tenaciously to the pavement, and accumulating at compound interest. Fog everywhere. Fog up the river, where it flows among green aits and meadows; fog down the river, where it rolls defiled among the tiers of shipping and the waterside pollutions of a great (and dirty) city. Fog on the Essex marshes, fog on the Kentish heights. Fog creeping into the cabooses of collier-brigs; fog lying out on the yards and hovering in the rigging of great ships; fog drooping on the gunwales of barges and small boats. Fog in the eyes and throats of ancient Greenwich pensioners, wheezing by the firesides of their wards; fog in the stem and bowl of the afternoon pipe of the wrathful skipper, down in his close cabin; fog cruelly pinching the toes and fingers of his shivering little ‘prentice boy on deck. Chance people on the bridges peeping over the parapets into a nether sky of fog, with fog all round them, as if they were up in a balloon and hanging in the misty clouds. Gas looming through the fog in divers places in the streets, much as the sun may, from the spongey fields, be seen to loom by husbandman and ploughboy. Most of the shops lighted two hours before their time—as the gas seems to know, for it has a haggard and unwilling look. The raw afternoon is rawest, and the dense fog is densest, and the muddy streets are muddiest near that leaden-headed old obstruction, appropriate ornament for the threshold of a leaden-headed old corporation, Temple Bar. And hard by Temple Bar, in Lincoln’s Inn Hall, at the very heart of the fog, sits the Lord High Chancellor in his High Court of Chancery."` @@ -46,7 +129,7 @@ func TestIssue21703(t *testing.T) { t.Parallel() testenv.MustHaveGoBuild(t) - // N.B. the build below explictly doesn't pass through + // N.B. the build below explicitly doesn't pass through // -asan/-msan/-race, so we don't care about those. testenv.MustInternalLink(t, testenv.NoSpecialBuildTypes) @@ -74,7 +157,7 @@ func main() {} t.Fatalf("failed to compile main.go: %v, output: %s\n", err, out) } - cmd = testenv.Command(t, testenv.GoToolPath(t), "tool", "link", "-importcfg="+importcfgfile, "main.o") + cmd = linkCmd(t, "-importcfg="+importcfgfile, "main.o") cmd.Dir = tmpdir out, err = cmd.CombinedOutput() if err != nil { @@ -93,7 +176,7 @@ func TestIssue28429(t *testing.T) { t.Parallel() testenv.MustHaveGoBuild(t) - // N.B. go build below explictly doesn't pass through + // N.B. go build below explicitly doesn't pass through // -asan/-msan/-race, so we don't care about those. testenv.MustInternalLink(t, testenv.NoSpecialBuildTypes) @@ -111,9 +194,6 @@ func TestIssue28429(t *testing.T) { cmd.Dir = tmpdir out, err := cmd.CombinedOutput() if err != nil { - if len(args) >= 2 && args[1] == "link" && runtime.GOOS == "android" && runtime.GOARCH == "arm64" { - testenv.SkipFlaky(t, 58806) - } t.Fatalf("'go %s' failed: %v, output: %s", strings.Join(args, " "), err, out) } @@ -133,7 +213,15 @@ func TestIssue28429(t *testing.T) { // Verify that the linker does not attempt // to compile the extra section. - runGo("tool", "link", "-importcfg="+importcfgfile, "main.a") + cmd := linkCmd(t, "-importcfg="+importcfgfile, "main.a") + cmd.Dir = tmpdir + out, err := cmd.CombinedOutput() + if err != nil { + if runtime.GOOS == "android" && runtime.GOARCH == "arm64" { + testenv.SkipFlaky(t, 58806) + } + t.Fatalf("linker failed: %v, output %s", err, out) + } } func TestUnresolved(t *testing.T) { @@ -171,9 +259,9 @@ TEXT ·x(SB),0,$0 MOVD ·zero(SB), AX RET `) - cmd := testenv.Command(t, testenv.GoToolPath(t), "build") + cmd := goCmd(t, "build") cmd.Dir = tmpdir - cmd.Env = append(os.Environ(), + cmd.Env = append(cmd.Env, "GOARCH=amd64", "GOOS=linux", "GOPATH="+filepath.Join(tmpdir, "_gopath")) out, err := cmd.CombinedOutput() if err == nil { @@ -193,7 +281,7 @@ main.x: relocation target main.zero not defined func TestIssue33979(t *testing.T) { testenv.MustHaveGoBuild(t) testenv.MustHaveCGO(t) - // N.B. go build below explictly doesn't pass through + // N.B. go build below explicitly doesn't pass through // -asan/-msan/-race, so we don't care about those. testenv.MustInternalLink(t, testenv.SpecialBuildTypes{Cgo: true}) @@ -260,7 +348,7 @@ void foo() { runGo("tool", "pack", "c", "x.a", "x1.o", "x2.o", "x3.o") // Now attempt to link using the internal linker. - cmd := testenv.Command(t, testenv.GoToolPath(t), "tool", "link", "-importcfg="+importcfgfile, "-linkmode=internal", "x.a") + cmd := linkCmd(t, "-importcfg="+importcfgfile, "-linkmode=internal", "x.a") cmd.Dir = tmpdir out, err := cmd.CombinedOutput() if err == nil { @@ -306,7 +394,7 @@ func TestBuildForTvOS(t *testing.T) { tmpDir := t.TempDir() ar := filepath.Join(tmpDir, "lib.a") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-o", ar, lib) + cmd := goCmd(t, "build", "-buildmode=c-archive", "-o", ar, lib) env := []string{ "CGO_ENABLED=1", "GOOS=ios", @@ -315,7 +403,7 @@ func TestBuildForTvOS(t *testing.T) { "CGO_CFLAGS=", // ensure CGO_CFLAGS does not contain any flags. Issue #35459 "CGO_LDFLAGS=" + strings.Join(CGO_LDFLAGS, " "), } - cmd.Env = append(os.Environ(), env...) + cmd.Env = append(cmd.Env, env...) t.Logf("%q %v", env, cmd) if out, err := cmd.CombinedOutput(); err != nil { t.Fatalf("%v: %v:\n%s", cmd.Args, err, out) @@ -351,7 +439,7 @@ func TestXFlag(t *testing.T) { t.Fatal(err) } - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-X=main.X=meow", "-o", filepath.Join(tmpdir, "main"), src) + cmd := goCmd(t, "build", "-ldflags=-X=main.X=meow", "-o", filepath.Join(tmpdir, "main"), src) if out, err := cmd.CombinedOutput(); err != nil { t.Errorf("%v: %v:\n%s", cmd.Args, err, out) } @@ -364,7 +452,9 @@ func main() { } func TestMachOBuildVersion(t *testing.T) { testenv.MustHaveGoBuild(t) - + if runtime.GOOS != "darwin" { + t.Skip("skip on non-Mach-O platforms") + } t.Parallel() tmpdir := t.TempDir() @@ -376,12 +466,8 @@ func TestMachOBuildVersion(t *testing.T) { } exe := filepath.Join(tmpdir, "main") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-linkmode=internal", "-o", exe, src) - cmd.Env = append(os.Environ(), - "CGO_ENABLED=0", - "GOOS=darwin", - "GOARCH=amd64", - ) + cmd := goCmd(t, "build", "-ldflags=-linkmode=internal", "-o", exe, src) + cmd.Env = append(cmd.Env, "CGO_ENABLED=0") if out, err := cmd.CombinedOutput(); err != nil { t.Fatalf("%v: %v:\n%s", cmd.Args, err, out) } @@ -397,8 +483,8 @@ func TestMachOBuildVersion(t *testing.T) { found := false checkMin := func(ver uint32) { major, minor, patch := (ver>>16)&0xff, (ver>>8)&0xff, (ver>>0)&0xff - if major < 12 { - t.Errorf("LC_BUILD_VERSION version %d.%d.%d < 12.0.0", major, minor, patch) + if major < 13 { + t.Errorf("LC_BUILD_VERSION version %d.%d.%d < 13.0.0", major, minor, patch) } } for _, cmd := range exem.Loads { @@ -469,7 +555,7 @@ func TestMachOUUID(t *testing.T) { for _, test := range tests { t.Run(test.name, func(t *testing.T) { exe := filepath.Join(tmpdir, test.name) - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags="+test.ldflags, "-o", exe, src) + cmd := goCmd(t, "build", "-ldflags="+test.ldflags, "-o", exe, src) if out, err := cmd.CombinedOutput(); err != nil { t.Fatalf("%v: %v:\n%s", cmd.Args, err, out) } @@ -610,7 +696,7 @@ func TestStrictDup(t *testing.T) { t.Fatal(err) } - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-strictdups=1") + cmd := goCmd(t, "build", "-ldflags=-strictdups=1") cmd.Dir = tmpdir out, err := cmd.CombinedOutput() if err != nil { @@ -620,7 +706,7 @@ func TestStrictDup(t *testing.T) { t.Errorf("unexpected output:\n%s", out) } - cmd = testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-strictdups=2") + cmd = goCmd(t, "build", "-ldflags=-strictdups=2") cmd.Dir = tmpdir out, err = cmd.CombinedOutput() if err == nil { @@ -708,7 +794,7 @@ func TestFuncAlign(t *testing.T) { t.Fatal(err) } - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", "falign") + cmd := goCmd(t, "build", "-o", "falign") cmd.Dir = tmpdir out, err := cmd.CombinedOutput() if err != nil { @@ -758,7 +844,7 @@ func TestFuncAlignOption(t *testing.T) { alignTest := func(align uint64) { exeName := "falign.exe" - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-funcalign="+strconv.FormatUint(align, 10), "-o", exeName, "falign.go") + cmd := goCmd(t, "build", "-ldflags=-funcalign="+strconv.FormatUint(align, 10), "-o", exeName, "falign.go") cmd.Dir = tmpdir out, err := cmd.CombinedOutput() if err != nil { @@ -782,6 +868,9 @@ func TestFuncAlignOption(t *testing.T) { "_main.bar": false, "_main.baz": false} syms, err := f.Symbols() + if err != nil { + t.Errorf("failed to get symbols with err %v", err) + } for _, s := range syms { fn := s.Name if _, ok := fname[fn]; !ok { @@ -831,10 +920,16 @@ func TestTrampoline(t *testing.T) { // calls will use trampolines. buildmodes := []string{"default"} switch runtime.GOARCH { - case "arm", "arm64", "ppc64", "loong64": - case "ppc64le": - // Trampolines are generated differently when internal linking PIE, test them too. - buildmodes = append(buildmodes, "pie") + case "arm", "arm64", "loong64": + case "ppc64le", "ppc64": + switch runtime.GOOS { + case "aix": + case "linux": + // Trampolines are generated differently when internal linking PIE, test them too. + buildmodes = append(buildmodes, "pie") + default: + t.Skipf("trampoline insertion is not implemented on %s-%s", runtime.GOARCH, runtime.GOOS) + } default: t.Skipf("trampoline insertion is not implemented on %s", runtime.GOARCH) } @@ -853,7 +948,7 @@ func TestTrampoline(t *testing.T) { exe := filepath.Join(tmpdir, "hello.exe") for _, mode := range buildmodes { - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-buildmode="+mode, "-ldflags=-debugtramp=2", "-o", exe, src) + cmd := goCmd(t, "build", "-buildmode="+mode, "-ldflags=-debugtramp=2", "-o", exe, src) out, err := cmd.CombinedOutput() if err != nil { t.Fatalf("build (%s) failed: %v\n%s", mode, err, out) @@ -896,8 +991,8 @@ func TestTrampolineCgo(t *testing.T) { // calls will use trampolines. buildmodes := []string{"default"} switch runtime.GOARCH { - case "arm", "arm64", "ppc64", "loong64": - case "ppc64le": + case "arm", "arm64", "loong64": + case "ppc64le", "ppc64": // Trampolines are generated differently when internal linking PIE, test them too. buildmodes = append(buildmodes, "pie") default: @@ -919,7 +1014,7 @@ func TestTrampolineCgo(t *testing.T) { exe := filepath.Join(tmpdir, "hello.exe") for _, mode := range buildmodes { - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-buildmode="+mode, "-ldflags=-debugtramp=2", "-o", exe, src) + cmd := goCmd(t, "build", "-buildmode="+mode, "-ldflags=-debugtramp=2", "-o", exe, src) out, err := cmd.CombinedOutput() if err != nil { t.Fatalf("build (%s) failed: %v\n%s", mode, err, out) @@ -938,7 +1033,7 @@ func TestTrampolineCgo(t *testing.T) { if !testenv.CanInternalLink(true) { continue } - cmd = testenv.Command(t, testenv.GoToolPath(t), "build", "-buildmode="+mode, "-ldflags=-debugtramp=2 -linkmode=internal", "-o", exe, src) + cmd = goCmd(t, "build", "-buildmode="+mode, "-ldflags=-debugtramp=2 -linkmode=internal", "-o", exe, src) out, err = cmd.CombinedOutput() if err != nil { t.Fatalf("build (%s) failed: %v\n%s", mode, err, out) @@ -959,7 +1054,7 @@ func TestIndexMismatch(t *testing.T) { // This shouldn't happen with "go build". We invoke the compiler and the linker // manually, and try to "trick" the linker with an inconsistent object file. testenv.MustHaveGoBuild(t) - // N.B. the build below explictly doesn't pass through + // N.B. the build below explicitly doesn't pass through // -asan/-msan/-race, so we don't care about those. testenv.MustInternalLink(t, testenv.NoSpecialBuildTypes) @@ -992,7 +1087,7 @@ func TestIndexMismatch(t *testing.T) { if err != nil { t.Fatalf("compiling main.go failed: %v\n%s", err, out) } - cmd = testenv.Command(t, testenv.GoToolPath(t), "tool", "link", "-importcfg="+importcfgWithAFile, "-L", tmpdir, "-o", exe, mObj) + cmd = linkCmd(t, "-importcfg="+importcfgWithAFile, "-L", tmpdir, "-o", exe, mObj) t.Log(cmd) out, err = cmd.CombinedOutput() if err != nil { @@ -1010,7 +1105,7 @@ func TestIndexMismatch(t *testing.T) { if err != nil { t.Fatalf("compiling a.go failed: %v\n%s", err, out) } - cmd = testenv.Command(t, testenv.GoToolPath(t), "tool", "link", "-importcfg="+importcfgWithAFile, "-L", tmpdir, "-o", exe, mObj) + cmd = linkCmd(t, "-importcfg="+importcfgWithAFile, "-L", tmpdir, "-o", exe, mObj) t.Log(cmd) out, err = cmd.CombinedOutput() if err == nil { @@ -1036,7 +1131,7 @@ func TestPErsrcBinutils(t *testing.T) { pkgdir := filepath.Join("testdata", "pe-binutils") exe := filepath.Join(tmpdir, "a.exe") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", exe) + cmd := goCmd(t, "build", "-o", exe) cmd.Dir = pkgdir // cmd.Env = append(os.Environ(), "GOOS=windows", "GOARCH=amd64") // uncomment if debugging in a cross-compiling environment out, err := cmd.CombinedOutput() @@ -1068,7 +1163,7 @@ func TestPErsrcLLVM(t *testing.T) { pkgdir := filepath.Join("testdata", "pe-llvm") exe := filepath.Join(tmpdir, "a.exe") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", exe) + cmd := goCmd(t, "build", "-o", exe) cmd.Dir = pkgdir // cmd.Env = append(os.Environ(), "GOOS=windows", "GOARCH=amd64") // uncomment if debugging in a cross-compiling environment out, err := cmd.CombinedOutput() @@ -1093,7 +1188,7 @@ func TestContentAddressableSymbols(t *testing.T) { t.Parallel() src := filepath.Join("testdata", "testHashedSyms", "p.go") - cmd := testenv.Command(t, testenv.GoToolPath(t), "run", src) + cmd := goCmd(t, "run", src) out, err := cmd.CombinedOutput() if err != nil { t.Errorf("command %s failed: %v\n%s", cmd, err, out) @@ -1107,7 +1202,7 @@ func TestReadOnly(t *testing.T) { t.Parallel() src := filepath.Join("testdata", "testRO", "x.go") - cmd := testenv.Command(t, testenv.GoToolPath(t), "run", src) + cmd := goCmd(t, "run", src) out, err := cmd.CombinedOutput() if err == nil { t.Errorf("running test program did not fail. output:\n%s", out) @@ -1143,7 +1238,7 @@ func TestIssue38554(t *testing.T) { t.Fatalf("failed to write source file: %v", err) } exe := filepath.Join(tmpdir, "x.exe") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", exe, src) + cmd := goCmd(t, "build", "-o", exe, src) out, err := cmd.CombinedOutput() if err != nil { t.Fatalf("build failed: %v\n%s", err, out) @@ -1193,7 +1288,7 @@ func TestIssue42396(t *testing.T) { t.Fatalf("failed to write source file: %v", err) } exe := filepath.Join(tmpdir, "main.exe") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-gcflags=-race", "-o", exe, src) + cmd := goCmd(t, "build", "-gcflags=-race", "-o", exe, src) out, err := cmd.CombinedOutput() if err == nil { t.Fatalf("build unexpectedly succeeded") @@ -1263,14 +1358,14 @@ func TestLargeReloc(t *testing.T) { if err != nil { t.Fatalf("failed to write source file: %v", err) } - cmd := testenv.Command(t, testenv.GoToolPath(t), "run", src) + cmd := goCmd(t, "run", src) out, err := cmd.CombinedOutput() if err != nil { t.Errorf("build failed: %v. output:\n%s", err, out) } if testenv.HasCGO() { // currently all targets that support cgo can external link - cmd = testenv.Command(t, testenv.GoToolPath(t), "run", "-ldflags=-linkmode=external", src) + cmd = goCmd(t, "run", "-ldflags=-linkmode=external", src) out, err = cmd.CombinedOutput() if err != nil { t.Fatalf("build failed: %v. output:\n%s", err, out) @@ -1314,7 +1409,7 @@ func TestUnlinkableObj(t *testing.T) { if err != nil { t.Fatalf("compile x.go failed: %v. output:\n%s", err, out) } - cmd = testenv.Command(t, testenv.GoToolPath(t), "tool", "link", "-importcfg="+importcfgfile, "-o", exe, xObj) + cmd = linkCmd(t, "-importcfg="+importcfgfile, "-o", exe, xObj) out, err = cmd.CombinedOutput() if err == nil { t.Fatalf("link did not fail") @@ -1335,7 +1430,7 @@ func TestUnlinkableObj(t *testing.T) { t.Fatalf("compile failed: %v. output:\n%s", err, out) } - cmd = testenv.Command(t, testenv.GoToolPath(t), "tool", "link", "-importcfg="+importcfgfile, "-o", exe, xObj) + cmd = linkCmd(t, "-importcfg="+importcfgfile, "-o", exe, xObj) out, err = cmd.CombinedOutput() if err != nil { t.Errorf("link failed: %v. output:\n%s", err, out) @@ -1378,10 +1473,11 @@ func main() {} // Link with -v -linkmode=external to see the flags we pass to the // external linker. ldflags := "-ldflags=-v -linkmode=external -tmpdir=" + linktmp - var out0 []byte + var out0, fullOut0 []byte for i := 0; i < 5; i++ { - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", ldflags, "-o", exe, src) - out, err := cmd.CombinedOutput() + cmd := goCmd(t, "build", ldflags, "-x", "-o", exe, src) + fullOut, err := cmd.CombinedOutput() + out := fullOut if err != nil { t.Fatalf("build failed: %v, output:\n%s", err, out) } @@ -1414,10 +1510,12 @@ func main() {} if i == 0 { out0 = out + fullOut0 = fullOut continue } if !bytes.Equal(out0, out) { - t.Fatalf("output differ:\n%s\n==========\n%s", out0, out) + t.Fatalf("output differ:\n%s\n==========\n%s\n\nfull output:\n%s\n==========\n%s", + out0, out, fullOut0, fullOut) } } } @@ -1440,6 +1538,9 @@ func TestResponseFile(t *testing.T) { t.Fatal(err) } + // We don't use goCmd here, as -toolexec doesn't use response files. + // This test is more for the go command than the linker anyhow. + cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", "output", "x.go") cmd.Dir = tmpdir @@ -1482,7 +1583,7 @@ func TestDynimportVar(t *testing.T) { src := filepath.Join("testdata", "dynimportvar", "main.go") for _, mode := range []string{"internal", "external"} { - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-linkmode="+mode, "-o", exe, src) + cmd := goCmd(t, "build", "-ldflags=-linkmode="+mode, "-o", exe, src) out, err := cmd.CombinedOutput() if err != nil { t.Fatalf("build (linkmode=%s) failed: %v\n%s", mode, err, out) @@ -1525,7 +1626,7 @@ func TestFlagS(t *testing.T) { syms := []string{"main.main", "main.X", "main.Y"} for _, mode := range modes { - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-s -linkmode="+mode, "-o", exe, src) + cmd := goCmd(t, "build", "-ldflags=-s -linkmode="+mode, "-o", exe, src) out, err := cmd.CombinedOutput() if err != nil { t.Fatalf("build (linkmode=%s) failed: %v\n%s", mode, err, out) @@ -1566,7 +1667,7 @@ func TestRandLayout(t *testing.T) { var syms [2]string for i, seed := range []string{"123", "456"} { exe := filepath.Join(tmpdir, "hello"+seed+".exe") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-ldflags=-randlayout="+seed, "-o", exe, src) + cmd := goCmd(t, "build", "-ldflags=-randlayout="+seed, "-o", exe, src) out, err := cmd.CombinedOutput() if err != nil { t.Fatalf("seed=%v: build failed: %v\n%s", seed, err, out) @@ -1615,18 +1716,22 @@ func TestCheckLinkname(t *testing.T) { {"coro2.go", false}, // pull linkname of a builtin symbol is not ok {"builtin.go", false}, + // using a linkname to reference a runtime assembly + // function is not ok (except on non-regabi platforms) + {"systemstack.go", !buildcfg.Experiment.RegabiWrappers}, + // misc {"addmoduledata.go", false}, + {"freegc.go", false}, // legacy bad linkname is ok, for now {"fastrand.go", true}, {"badlinkname.go", true}, } for _, test := range tests { - test := test t.Run(test.src, func(t *testing.T) { t.Parallel() src := "./testdata/linkname/" + test.src exe := filepath.Join(tmpdir, test.src+".exe") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", exe, src) + cmd := goCmd(t, "build", "-o", exe, src) out, err := cmd.CombinedOutput() if test.ok && err != nil { t.Errorf("build failed unexpectedly: %v:\n%s", err, out) @@ -1648,7 +1753,7 @@ func TestLinknameBSS(t *testing.T) { src := filepath.Join("testdata", "linkname", "sched.go") exe := filepath.Join(tmpdir, "sched.exe") - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", exe, src) + cmd := goCmd(t, "build", "-o", exe, src) out, err := cmd.CombinedOutput() if err != nil { t.Fatalf("build failed unexpectedly: %v:\n%s", err, out) @@ -1687,3 +1792,694 @@ func TestLinknameBSS(t *testing.T) { t.Errorf("executable failed to run: %v\n%s", err, out) } } + +// setValueFromBytes copies from a []byte to a variable. +// This is used to get correctly aligned values in TestFuncdataPlacement. +func setValueFromBytes[T any](p *T, s []byte) { + copy(unsafe.Slice((*byte)(unsafe.Pointer(p)), unsafe.Sizeof(*p)), s) +} + +// Test that all funcdata values are stored in the .gopclntab section. +// This is pretty ugly as there is no API for accessing this data. +// This test will have to be updated when the data formats change. +func TestFuncdataPlacement(t *testing.T) { + testenv.MustHaveGoBuild(t) + t.Parallel() + + tmpdir := t.TempDir() + src := filepath.Join(tmpdir, "x.go") + if err := os.WriteFile(src, []byte(trivialSrc), 0o444); err != nil { + t.Fatal(err) + } + + exe := filepath.Join(tmpdir, "x.exe") + cmd := goCmd(t, "build", "-o", exe, src) + if out, err := cmd.CombinedOutput(); err != nil { + t.Fatalf("build failed; %v, output:\n%s", err, out) + } + + // We want to find the funcdata in the executable. + // We look at the section table to find the .gopclntab section, + // which starts with the pcHeader. + // That will give us the table of functions, + // which we can use to find the funcdata. + + ef, _ := elf.Open(exe) + mf, _ := macho.Open(exe) + pf, _ := pe.Open(exe) + xf, _ := xcoff.Open(exe) + // TODO: plan9 + if ef == nil && mf == nil && pf == nil && xf == nil { + t.Skip("unrecognized executable file format") + } + + const moddataSymName = "runtime.firstmoduledata" + const gofuncSymName = "go:func.*" + var ( + pclntab []byte + pclntabAddr uint64 + pclntabEnd uint64 + moddataAddr uint64 + moddataBytes []byte + gofuncAddr uint64 + imageBase uint64 + ) + switch { + case ef != nil: + defer ef.Close() + + syms, err := ef.Symbols() + if err != nil { + t.Fatal(err) + } + for _, sym := range syms { + switch sym.Name { + case moddataSymName: + moddataAddr = sym.Value + case gofuncSymName: + gofuncAddr = sym.Value + } + } + + for _, sec := range ef.Sections { + if sec.Name == ".gopclntab" { + data, err := sec.Data() + if err != nil { + t.Fatal(err) + } + pclntab = data + pclntabAddr = sec.Addr + pclntabEnd = sec.Addr + sec.Size + } + if sec.Flags&elf.SHF_ALLOC != 0 && moddataAddr >= sec.Addr && moddataAddr < sec.Addr+sec.Size { + data, err := sec.Data() + if err != nil { + t.Fatal(err) + } + moddataBytes = data[moddataAddr-sec.Addr:] + } + } + + case mf != nil: + defer mf.Close() + + for _, sym := range mf.Symtab.Syms { + switch sym.Name { + case moddataSymName: + moddataAddr = sym.Value + case gofuncSymName: + gofuncAddr = sym.Value + } + } + + for _, sec := range mf.Sections { + if sec.Name == "__gopclntab" { + data, err := sec.Data() + if err != nil { + t.Fatal(err) + } + pclntab = data + pclntabAddr = sec.Addr + pclntabEnd = sec.Addr + sec.Size + } + if moddataAddr >= sec.Addr && moddataAddr < sec.Addr+sec.Size { + data, err := sec.Data() + if err != nil { + t.Fatal(err) + } + moddataBytes = data[moddataAddr-sec.Addr:] + } + } + + case pf != nil: + defer pf.Close() + + switch ohdr := pf.OptionalHeader.(type) { + case *pe.OptionalHeader32: + imageBase = uint64(ohdr.ImageBase) + case *pe.OptionalHeader64: + imageBase = ohdr.ImageBase + } + + var moddataSym, gofuncSym, pclntabSym, epclntabSym *pe.Symbol + for _, sym := range pf.Symbols { + switch sym.Name { + case moddataSymName: + moddataSym = sym + case gofuncSymName: + gofuncSym = sym + case "runtime.pclntab": + pclntabSym = sym + case "runtime.epclntab": + epclntabSym = sym + } + } + + if moddataSym == nil { + t.Fatalf("could not find symbol %s", moddataSymName) + } + if gofuncSym == nil { + t.Fatalf("could not find symbol %s", gofuncSymName) + } + if pclntabSym == nil { + t.Fatal("could not find symbol runtime.pclntab") + } + if epclntabSym == nil { + t.Fatal("could not find symbol runtime.epclntab") + } + + sec := pf.Sections[moddataSym.SectionNumber-1] + data, err := sec.Data() + if err != nil { + t.Fatal(err) + } + moddataBytes = data[moddataSym.Value:] + moddataAddr = uint64(sec.VirtualAddress + moddataSym.Value) + + sec = pf.Sections[gofuncSym.SectionNumber-1] + gofuncAddr = uint64(sec.VirtualAddress + gofuncSym.Value) + + if pclntabSym.SectionNumber != epclntabSym.SectionNumber { + t.Fatalf("runtime.pclntab section %d != runtime.epclntab section %d", pclntabSym.SectionNumber, epclntabSym.SectionNumber) + } + sec = pf.Sections[pclntabSym.SectionNumber-1] + data, err = sec.Data() + if err != nil { + t.Fatal(err) + } + pclntab = data[pclntabSym.Value:epclntabSym.Value] + pclntabAddr = uint64(sec.VirtualAddress + pclntabSym.Value) + pclntabEnd = uint64(sec.VirtualAddress + epclntabSym.Value) + + case xf != nil: + defer xf.Close() + + var moddataSym, gofuncSym, pclntabSym, epclntabSym *xcoff.Symbol + for _, sym := range xf.Symbols { + switch sym.Name { + case moddataSymName: + moddataSym = sym + case gofuncSymName: + gofuncSym = sym + case "runtime.pclntab": + pclntabSym = sym + case "runtime.epclntab": + epclntabSym = sym + } + } + + if moddataSym == nil { + t.Fatalf("could not find symbol %s", moddataSymName) + } + if gofuncSym == nil { + t.Fatalf("could not find symbol %s", gofuncSymName) + } + if pclntabSym == nil { + t.Fatal("could not find symbol runtime.pclntab") + } + if epclntabSym == nil { + t.Fatal("could not find symbol runtime.epclntab") + } + + sec := xf.Sections[moddataSym.SectionNumber-1] + data, err := sec.Data() + if err != nil { + t.Fatal(err) + } + moddataBytes = data[moddataSym.Value:] + moddataAddr = uint64(sec.VirtualAddress + moddataSym.Value) + + sec = xf.Sections[gofuncSym.SectionNumber-1] + gofuncAddr = uint64(sec.VirtualAddress + gofuncSym.Value) + + if pclntabSym.SectionNumber != epclntabSym.SectionNumber { + t.Fatalf("runtime.pclntab section %d != runtime.epclntab section %d", pclntabSym.SectionNumber, epclntabSym.SectionNumber) + } + sec = xf.Sections[pclntabSym.SectionNumber-1] + data, err = sec.Data() + if err != nil { + t.Fatal(err) + } + pclntab = data[pclntabSym.Value:epclntabSym.Value] + pclntabAddr = uint64(sec.VirtualAddress + pclntabSym.Value) + pclntabEnd = uint64(sec.VirtualAddress + epclntabSym.Value) + + default: + panic("can't happen") + } + + if len(pclntab) == 0 { + t.Fatal("could not find pclntab section") + } + if moddataAddr == 0 { + t.Fatalf("could not find %s symbol", moddataSymName) + } + if gofuncAddr == 0 { + t.Fatalf("could not find %s symbol", gofuncSymName) + } + if gofuncAddr < pclntabAddr || gofuncAddr >= pclntabEnd { + t.Fatalf("%s out of range: value %#x not between %#x and %#x", gofuncSymName, gofuncAddr, pclntabAddr, pclntabEnd) + } + if len(moddataBytes) == 0 { + t.Fatal("could not find module data") + } + + // What a slice looks like in the object file. + type moddataSlice struct { + addr uintptr + len int + cap int + } + + // This needs to match the struct defined in runtime/symtab.go, + // and written out by (*Link).symtab. + // This is not the complete moddata struct, only what we need here. + type moddataType struct { + pcHeader uintptr + funcnametab moddataSlice + cutab moddataSlice + filetab moddataSlice + pctab moddataSlice + pclntable moddataSlice + ftab moddataSlice + findfunctab uintptr + minpc, maxpc uintptr + + text, etext uintptr + noptrdata, enoptrdata uintptr + data, edata uintptr + bss, ebss uintptr + noptrbss, enoptrbss uintptr + covctrs, ecovctrs uintptr + end, gcdata, gcbss uintptr + types, etypes uintptr + rodata uintptr + gofunc uintptr + } + + // The executable is on the same system as we are running, + // so the sizes and alignments should match. + // But moddataBytes itself may not be aligned as needed. + // Copy to a variable to ensure alignment. + var moddata moddataType + setValueFromBytes(&moddata, moddataBytes) + + ftabAddr := uint64(moddata.ftab.addr) - imageBase + if ftabAddr < pclntabAddr || ftabAddr >= pclntabEnd { + t.Fatalf("ftab address %#x not between %#x and %#x", ftabAddr, pclntabAddr, pclntabEnd) + } + + // From runtime/symtab.go and the linker function writePCToFunc. + type functab struct { + entryoff uint32 + funcoff uint32 + } + // The ftab slice in moddata has one extra entry used to record + // the final PC. + ftabLen := moddata.ftab.len - 1 + ftab := make([]functab, ftabLen) + copy(ftab, unsafe.Slice((*functab)(unsafe.Pointer(&pclntab[ftabAddr-pclntabAddr])), ftabLen)) + + ftabBase := uint64(moddata.pclntable.addr) - imageBase + + // From runtime/runtime2.go _func and the linker function writeFuncs. + type funcEntry struct { + entryOff uint32 + nameOff int32 + + args int32 + deferreturn uint32 + + pcsp uint32 + pcfile uint32 + pcln uint32 + npcdata uint32 + cuOffset uint32 + startLine int32 + funcID abi.FuncID + flag abi.FuncFlag + _ [1]byte + nfuncdata uint8 + } + + for i, ftabEntry := range ftab { + funcAddr := ftabBase + uint64(ftabEntry.funcoff) + if funcAddr < pclntabAddr || funcAddr >= pclntabEnd { + t.Errorf("ftab entry %d address %#x not between %#x and %#x", i, funcAddr, pclntabAddr, pclntabEnd) + continue + } + + var fe funcEntry + setValueFromBytes(&fe, pclntab[funcAddr-pclntabAddr:]) + + funcdataVals := funcAddr + uint64(unsafe.Sizeof(fe)) + uint64(fe.npcdata*4) + for j := range fe.nfuncdata { + var funcdataVal uint32 + setValueFromBytes(&funcdataVal, pclntab[funcdataVals+uint64(j)*4-pclntabAddr:]) + if funcdataVal == ^uint32(0) { + continue + } + funcdataAddr := gofuncAddr + uint64(funcdataVal) + if funcdataAddr < pclntabAddr || funcdataAddr >= pclntabEnd { + t.Errorf("ftab entry %d funcdata %d address %#x not between %#x and %#x", i, j, funcdataAddr, pclntabAddr, pclntabEnd) + } + } + } + + if uint64(moddata.findfunctab)-imageBase < pclntabAddr || uint64(moddata.findfunctab)-imageBase >= pclntabEnd { + t.Errorf("findfunctab address %#x not between %#x and %#x", moddata.findfunctab, pclntabAddr, pclntabEnd) + } +} + +// Test that moduledata winds up in its own .go.module section. +func TestModuledataPlacement(t *testing.T) { + testenv.MustHaveGoBuild(t) + t.Parallel() + + tmpdir := t.TempDir() + src := filepath.Join(tmpdir, "x.go") + if err := os.WriteFile(src, []byte(trivialSrc), 0o444); err != nil { + t.Fatal(err) + } + + exe := filepath.Join(tmpdir, "x.exe") + cmd := goCmd(t, "build", "-o", exe, src) + if out, err := cmd.CombinedOutput(); err != nil { + t.Fatalf("build failed; %v, output:\n%s", err, out) + } + + ef, _ := elf.Open(exe) + mf, _ := macho.Open(exe) + pf, _ := pe.Open(exe) + xf, _ := xcoff.Open(exe) + // TODO: plan9 + if ef == nil && mf == nil && pf == nil && xf == nil { + t.Skip("unrecognized executable file format") + } + + const moddataSymName = "runtime.firstmoduledata" + switch { + case ef != nil: + defer ef.Close() + + syms, err := ef.Symbols() + if err != nil { + t.Fatal(err) + } + for _, sym := range syms { + if sym.Name == moddataSymName { + sec := ef.Sections[sym.Section] + if sec.Name != ".go.module" { + t.Errorf("moduledata in section %s, not .go.module", sec.Name) + } + if sym.Value != sec.Addr { + t.Errorf("moduledata address %#x != section start address %#x", sym.Value, sec.Addr) + } + break + } + } + + case mf != nil: + defer mf.Close() + + for _, sym := range mf.Symtab.Syms { + if sym.Name == moddataSymName { + if sym.Sect == 0 { + t.Error("moduledata not in a section") + } else { + sec := mf.Sections[sym.Sect-1] + if sec.Name != "__go_module" { + t.Errorf("moduledata in section %s, not __go.module", sec.Name) + } + if sym.Value != sec.Addr { + t.Errorf("moduledata address %#x != section start address %#x", sym.Value, sec.Addr) + } + } + break + } + } + + case pf != nil, xf != nil: + if pf != nil { + defer pf.Close() + } + if xf != nil { + defer xf.Close() + } + + // On Windows and AIX all the Go specific sections + // get stuffed into a few sections, + // so there is nothing to test here. + } +} + +const typeSrc = ` +package main + +import ( + "fmt" + "unsafe" +) + +type MyInt int + +var vals = []any{ + 0, + 0.1, + "", + MyInt(0), + struct{ f int }{0}, + func() {}, +} + +var global int + +func main() { + fmt.Printf("global %#x\n", &global) + for _, v := range vals { + // Unsafe assumption: the first word of a value + // of type any is the type descriptor. + td := *(*uintptr)(unsafe.Pointer(&v)) + fmt.Printf("%#x\n", td) + } +} +` + +// Test that type data is stored in the types section. +func TestTypePlacement(t *testing.T) { + testenv.MustHaveGoRun(t) + t.Parallel() + + tmpdir := t.TempDir() + src := filepath.Join(tmpdir, "x.go") + if err := os.WriteFile(src, []byte(typeSrc), 0o444); err != nil { + t.Fatal(err) + } + + exe := filepath.Join(tmpdir, "x.exe") + cmd := goCmd(t, "build", "-o", exe, src) + if out, err := cmd.CombinedOutput(); err != nil { + t.Fatalf("build failed; %v, output:\n%s", err, out) + } + + cmd = testenv.Command(t, exe) + var stdout, stderr strings.Builder + cmd.Stdout = &stdout + cmd.Stderr = &stderr + if err := cmd.Run(); err != nil { + t.Fatalf("running test program failed: %v, stdout:\n%s\nstderr:\n%s", err, &stdout, &stderr) + } + stderrString := stderr.String() + if stderrString != "" { + t.Fatalf("running test program printed to stderr:\n%s", stderrString) + } + + t.Logf("\n%s", &stdout) + + var globalExeAddr uint64 + var addrs []uint64 + globalNext := false + for s := range strings.FieldsSeq(stdout.String()) { + if globalNext { + v, err := strconv.ParseUint(s, 0, 64) + if err != nil { + t.Errorf("failed to parse test program output %s: %v", s, err) + } + globalExeAddr = v + globalNext = false + } else if s == "global" { + globalNext = true + } else { + addr, err := strconv.ParseUint(s, 0, 64) + if err != nil { + t.Errorf("failed to parse test program output %q: %v", s, err) + } + addrs = append(addrs, addr) + } + } + + ef, _ := elf.Open(exe) + mf, _ := macho.Open(exe) + pf, _ := pe.Open(exe) + xf, _ := xcoff.Open(exe) + // TODO: plan9 + if ef == nil && mf == nil && pf == nil && xf == nil { + t.Skip("unrecognized executable file format") + } + + const globalName = "main.global" + var typeStart, typeEnd uint64 + var globalObjAddr uint64 + switch { + case ef != nil: + defer ef.Close() + + for _, sec := range ef.Sections { + if sec.Name == ".go.type" { + typeStart = sec.Addr + typeEnd = sec.Addr + sec.Size + break + } + } + + syms, err := ef.Symbols() + if err != nil { + t.Fatal(err) + } + + if typeStart == 0 && typeEnd == 0 { + // We can fail to find the section for PIE. + // Fall back to symbols. + for _, sym := range syms { + switch sym.Name { + case "runtime.types": + typeStart = sym.Value + case "runtime.etypes": + typeEnd = sym.Value + } + } + } + + for _, sym := range syms { + if sym.Name == globalName { + globalObjAddr = sym.Value + break + } + } + + case mf != nil: + defer mf.Close() + + for _, sec := range mf.Sections { + if sec.Name == "__go_type" { + typeStart = sec.Addr + typeEnd = sec.Addr + sec.Size + break + } + } + + for _, sym := range mf.Symtab.Syms { + if sym.Name == globalName { + globalObjAddr = sym.Value + break + } + } + + case pf != nil: + defer pf.Close() + + var imageBase uint64 + switch ohdr := pf.OptionalHeader.(type) { + case *pe.OptionalHeader32: + imageBase = uint64(ohdr.ImageBase) + case *pe.OptionalHeader64: + imageBase = ohdr.ImageBase + } + + var typeSym, eTypeSym *pe.Symbol + for _, sym := range pf.Symbols { + switch sym.Name { + case "runtime.types": + typeSym = sym + case "runtime.etypes": + eTypeSym = sym + case globalName: + globalSec := pf.Sections[sym.SectionNumber-1] + globalObjAddr = imageBase + uint64(globalSec.VirtualAddress+sym.Value) + } + } + + if typeSym == nil { + t.Fatal("could not find symbol runtime.types") + } + if eTypeSym == nil { + t.Fatal("could not find symbol runtime.etypes") + } + if typeSym.SectionNumber != eTypeSym.SectionNumber { + t.Fatalf("runtime.types section %d != runtime.etypes section %d", typeSym.SectionNumber, eTypeSym.SectionNumber) + } + + sec := pf.Sections[typeSym.SectionNumber-1] + + typeStart = imageBase + uint64(sec.VirtualAddress+typeSym.Value) + typeEnd = imageBase + uint64(sec.VirtualAddress+eTypeSym.Value) + + case xf != nil: + defer xf.Close() + + // On XCOFF the .go.type section, + // like all relro sections, + // gets folded into the .data section. + var typeSym, eTypeSym *xcoff.Symbol + for _, sym := range xf.Symbols { + switch sym.Name { + case "runtime.types": + typeSym = sym + case "runtime.etypes": + eTypeSym = sym + case globalName: + globalSec := xf.Sections[sym.SectionNumber-1] + globalObjAddr = uint64(globalSec.VirtualAddress + sym.Value) + } + } + + if typeSym == nil { + t.Fatal("could not find symbol runtime.types") + } + if eTypeSym == nil { + t.Fatal("could not find symbol runtime.etypes") + } + if typeSym.SectionNumber != eTypeSym.SectionNumber { + t.Fatalf("runtime.types section %d != runtime.etypes section %d", typeSym.SectionNumber, eTypeSym.SectionNumber) + } + + sec := xf.Sections[typeSym.SectionNumber-1] + + typeStart = uint64(sec.VirtualAddress + typeSym.Value) + + typeEnd = uint64(sec.VirtualAddress + eTypeSym.Value) + } + + if typeStart == 0 || typeEnd == 0 { + t.Fatalf("failed to find type descriptor addresses; found %#x to %#x", typeStart, typeEnd) + } + t.Logf("type start: %#x type end: %#x", typeStart, typeEnd) + + offset := globalExeAddr - globalObjAddr + t.Logf("execution offset: %#x", offset) + + // On AIX with internal linking the type descriptors are + // currently put in the .text section, whereas the global + // variable will be in the .data section. We must ignore + // the offset. This would change if using external linking. + if runtime.GOOS == "aix" { + offset = 0 + } + + for _, addr := range addrs { + addr -= offset + if addr < typeStart || addr >= typeEnd { + t.Errorf("type descriptor address %#x out of range: not between %#x and %#x", addr, typeStart, typeEnd) + } + } +} diff --git a/src/cmd/link/linkbig_test.go b/src/cmd/link/linkbig_test.go index ae9a38fa7ba229..36c01c3b4af936 100644 --- a/src/cmd/link/linkbig_test.go +++ b/src/cmd/link/linkbig_test.go @@ -82,7 +82,7 @@ func TestLargeText(t *testing.T) { } // Build and run with internal linking. - cmd := testenv.Command(t, testenv.GoToolPath(t), "build", "-o", "bigtext") + cmd := goCmd(t, "build", "-o", "bigtext") cmd.Dir = tmpdir out, err := cmd.CombinedOutput() if err != nil { @@ -96,7 +96,7 @@ func TestLargeText(t *testing.T) { } // Build and run with external linking - cmd = testenv.Command(t, testenv.GoToolPath(t), "build", "-o", "bigtext", "-ldflags", "-linkmode=external") + cmd = goCmd(t, "build", "-o", "bigtext", "-ldflags", "-linkmode=external") cmd.Dir = tmpdir out, err = cmd.CombinedOutput() if err != nil { diff --git a/src/cmd/link/testdata/linkname/badlinkname.go b/src/cmd/link/testdata/linkname/badlinkname.go index fb9f9c6b7d164e..29e645126d0ba5 100644 --- a/src/cmd/link/testdata/linkname/badlinkname.go +++ b/src/cmd/link/testdata/linkname/badlinkname.go @@ -3,7 +3,8 @@ // license that can be found in the LICENSE file. // Existing pull linknames in the wild are allowed _for now_, -// for legacy reason. Test a function and a method. +// for legacy reason. Test a function, a method, and an +// assembly symbol. // NOTE: this may not be allowed in the future. Don't do this! package main @@ -19,6 +20,12 @@ func noescape(unsafe.Pointer) unsafe.Pointer //go:linkname rtype_String reflect.(*rtype).String func rtype_String(unsafe.Pointer) string +//go:linkname memmove runtime.memmove +func memmove(to, from unsafe.Pointer, n uintptr) + +var n uintptr // use a global to prevent compiler optimize out memmove call + func main() { println(rtype_String(noescape(nil))) + memmove(nil, nil, n) } diff --git a/src/cmd/link/testdata/linkname/freegc.go b/src/cmd/link/testdata/linkname/freegc.go new file mode 100644 index 00000000000000..390063f8e9e743 --- /dev/null +++ b/src/cmd/link/testdata/linkname/freegc.go @@ -0,0 +1,18 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Linkname runtime.freegc is not allowed. + +package main + +import ( + _ "unsafe" +) + +//go:linkname freegc runtime.freegc +func freegc() + +func main() { + freegc() +} diff --git a/src/cmd/link/testdata/linkname/systemstack.go b/src/cmd/link/testdata/linkname/systemstack.go new file mode 100644 index 00000000000000..7fc575d6eb7679 --- /dev/null +++ b/src/cmd/link/testdata/linkname/systemstack.go @@ -0,0 +1,19 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Linkname systemstack is not allowed, even if it is +// defined in assembly. + +package main + +import _ "unsafe" + +func f() {} + +func main() { + systemstack(f) +} + +//go:linkname systemstack runtime.systemstack +func systemstack(func()) diff --git a/src/cmd/nm/nm_cgo_test.go b/src/cmd/nm/nm_cgo_test.go index 13c93fb459eef4..498337830b3ba3 100644 --- a/src/cmd/nm/nm_cgo_test.go +++ b/src/cmd/nm/nm_cgo_test.go @@ -11,7 +11,7 @@ import ( func TestInternalLinkerCgoExec(t *testing.T) { testenv.MustHaveCGO(t) - // N.B. the go build explictly doesn't pass through + // N.B. the go build explicitly doesn't pass through // -asan/-msan/-race, so we don't care about those. testenv.MustInternalLink(t, testenv.SpecialBuildTypes{Cgo: true}) testGoExec(t, true, false) diff --git a/src/cmd/nm/nm_test.go b/src/cmd/nm/nm_test.go index f740a3f738a866..ce1bd7cd5747d7 100644 --- a/src/cmd/nm/nm_test.go +++ b/src/cmd/nm/nm_test.go @@ -116,11 +116,8 @@ func testGoExec(t *testing.T, iscgo, isexternallinker bool) { "runtime.erodata": "R", "runtime.epclntab": "R", "runtime.noptrdata": "D", - } - - if runtime.GOOS == "aix" && iscgo { - // pclntab is moved to .data section on AIX. - runtimeSyms["runtime.epclntab"] = "D" + "runtime.bss": "B", + "runtime.noptrbss": "B", } out, err = testenv.Command(t, testenv.Executable(t), exe).CombinedOutput() diff --git a/src/cmd/nm/script_test.go b/src/cmd/nm/script_test.go new file mode 100644 index 00000000000000..025817d652556e --- /dev/null +++ b/src/cmd/nm/script_test.go @@ -0,0 +1,35 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import ( + "cmd/internal/script/scripttest" + "flag" + "internal/testenv" + "os" + "testing" +) + +//go:generate go test cmd/nm -v -run=TestScript/README --fixreadme + +var fixReadme = flag.Bool("fixreadme", false, "if true, update README for script tests") + +func TestScript(t *testing.T) { + testenv.MustHaveGoBuild(t) + + testExe, testExeErr := os.Executable() + + repls := []scripttest.ToolReplacement{} + if testExeErr == nil { + repls = []scripttest.ToolReplacement{ + scripttest.ToolReplacement{ + ToolName: "nm", + ReplacementPath: testExe, + EnvVar: "GO_NMTEST_IS_NM=1", + }, + } + } + scripttest.RunToolScriptTest(t, repls, "testdata/script", *fixReadme) +} diff --git a/src/cmd/nm/testdata/script/README b/src/cmd/nm/testdata/script/README new file mode 100644 index 00000000000000..9ec997a138f0f2 --- /dev/null +++ b/src/cmd/nm/testdata/script/README @@ -0,0 +1,286 @@ +This file is generated by 'go generate'. DO NOT EDIT. + +This directory holds test scripts *.txt run during 'go test cmd/'. +To run a specific script foo.txt + + go test cmd/ -run=Script/^foo$ + +In general script files should have short names: a few words, + not whole sentences. +The first word should be the general category of behavior being tested, +often the name of a go subcommand (build, link, compile, ...) or concept (vendor, pattern). + +Each script is a text archive (go doc internal/txtar). +The script begins with an actual command script to run +followed by the content of zero or more supporting files to +create in the script's temporary file system before it starts executing. + +As an example, run_hello.txt says: + + # hello world + go run hello.go + stderr 'hello world' + ! stdout . + + -- hello.go -- + package main + func main() { println("hello world") } + +Each script runs in a fresh temporary work directory tree, available to scripts as $WORK. +Scripts also have access to other environment variables, including: + + GOARCH= + GOOS= + TMPDIR=$WORK/tmp + devnull= + goversion= + +On Plan 9, the variables $path and $home are set instead of $PATH and $HOME. +On Windows, the variables $USERPROFILE and $TMP are set instead of +$HOME and $TMPDIR. + +The lines at the top of the script are a sequence of commands to be executed by +a small script engine configured in .../cmd/internal/script/scripttest/run.go (not the system shell). + +Each line of a script is parsed into a sequence of space-separated command +words, with environment variable expansion within each word and # marking +an end-of-line comment. Additional variables named ':' and '/' are expanded +within script arguments (expanding to the value of os.PathListSeparator and +os.PathSeparator respectively) but are not inherited in subprocess environments. + +Adding single quotes around text keeps spaces in that text from being treated +as word separators and also disables environment variable expansion. Inside a +single-quoted block of text, a repeated single quote indicates a literal single +quote, as in: + + 'Don''t communicate by sharing memory.' + +A line beginning with # is a comment and conventionally explains what is being +done or tested at the start of a new section of the script. + +Commands are executed one at a time, and errors are checked for each command; +if any command fails unexpectedly, no subsequent commands in the script are +executed. The command prefix ! indicates that the command on the rest of the +line (typically go or a matching predicate) must fail instead of succeeding. +The command prefix ? indicates that the command may or may not succeed, but the +script should continue regardless. + +The command prefix [cond] indicates that the command on the rest of the line +should only run when the condition is satisfied. + +A condition can be negated: [!root] means to run the rest of the line only if +the user is not root. Multiple conditions may be given for a single command, +for example, '[linux] [amd64] skip'. The command will run if all conditions are +satisfied. + +When TestScript runs a script and the script fails, by default TestScript shows +the execution of the most recent phase of the script (since the last # comment) +and only shows the # comments for earlier phases. + +Note also that in reported output, the actual name of the per-script temporary directory +has been consistently replaced with the literal string $WORK. + +The available commands are: +cat files... + concatenate files and print to the script's stdout buffer + + +cc args... + run the platform C compiler + + +cd dir + change the working directory + + +chmod perm paths... + change file mode bits + + Changes the permissions of the named files or directories to + be equal to perm. + Only numerical permissions are supported. + +cmp [-q] file1 file2 + compare files for differences + + By convention, file1 is the actual data and file2 is the + expected data. + The command succeeds if the file contents are identical. + File1 can be 'stdout' or 'stderr' to compare the stdout or + stderr buffer from the most recent command. + +cmpenv [-q] file1 file2 + compare files for differences, with environment expansion + + By convention, file1 is the actual data and file2 is the + expected data. + The command succeeds if the file contents are identical + after substituting variables from the script environment. + File1 can be 'stdout' or 'stderr' to compare the script's + stdout or stderr buffer. + +cp src... dst + copy files to a target file or directory + + src can include 'stdout' or 'stderr' to copy from the + script's stdout or stderr buffer. + +echo string... + display a line of text + + +env [key[=value]...] + set or log the values of environment variables + + With no arguments, print the script environment to the log. + Otherwise, add the listed key=value pairs to the environment + or print the listed keys. + +exec program [args...] [&] + run an executable program with arguments + + Note that 'exec' does not terminate the script (unlike Unix + shells). + +exists [-readonly] [-exec] file... + check that files exist + + +go [args...] [&] + run the 'go' program provided by the script host + + +grep [-count=N] [-q] 'pattern' file + find lines in a file that match a pattern + + The command succeeds if at least one match (or the exact + count, if given) is found. + The -q flag suppresses printing of matches. + +help [-v] name... + log help text for commands and conditions + + To display help for a specific condition, enclose it in + brackets: 'help [amd64]'. + To display complete documentation when listing all commands, + pass the -v flag. + +mkdir path... + create directories, if they do not already exist + + Unlike Unix mkdir, parent directories are always created if + needed. + +mv old new + rename a file or directory to a new path + + OS-specific restrictions may apply when old and new are in + different directories. + +replace [old new]... file + replace strings in a file + + The 'old' and 'new' arguments are unquoted as if in quoted + Go strings. + +rm path... + remove a file or directory + + If the path is a directory, its contents are removed + recursively. + +skip [msg] + skip the current test + + +sleep duration [&] + sleep for a specified duration + + The duration must be given as a Go time.Duration string. + +stderr [-count=N] [-q] 'pattern' file + find lines in the stderr buffer that match a pattern + + The command succeeds if at least one match (or the exact + count, if given) is found. + The -q flag suppresses printing of matches. + +stdout [-count=N] [-q] 'pattern' file + find lines in the stdout buffer that match a pattern + + The command succeeds if at least one match (or the exact + count, if given) is found. + The -q flag suppresses printing of matches. + +stop [msg] + stop execution of the script + + The message is written to the script log, but no error is + reported from the script engine. + +symlink path -> target + create a symlink + + Creates path as a symlink to target. + The '->' token (like in 'ls -l' output on Unix) is required. + +wait + wait for completion of background commands + + Waits for all background commands to complete. + The output (and any error) from each command is printed to + the log in the order in which the commands were started. + After the call to 'wait', the script's stdout and stderr + buffers contain the concatenation of the background + commands' outputs. + + + +The available conditions are: +[GOARCH:*] + runtime.GOARCH == +[GODEBUG:*] + GODEBUG contains +[GOEXPERIMENT:*] + GOEXPERIMENT is enabled +[GOOS:*] + runtime.GOOS == +[asan] + GOOS/GOARCH supports -asan +[buildmode:*] + go supports -buildmode= +[cgo] + host CGO_ENABLED +[cgolinkext] + platform requires external linking for cgo +[compiler:*] + runtime.Compiler == +[cross] + cmd/go GOOS/GOARCH != GOHOSTOS/GOHOSTARCH +[exec:*] + names an executable in the test binary's PATH +[fuzz] + GOOS/GOARCH supports -fuzz +[fuzz-instrumented] + GOOS/GOARCH supports -fuzz with instrumentation +[go-builder] + GO_BUILDER_NAME is non-empty +[link] + testenv.HasLink() +[msan] + GOOS/GOARCH supports -msan +[mustlinkext] + platform always requires external linking +[pielinkext] + platform requires external linking for PIE +[race] + GOOS/GOARCH supports -race +[root] + os.Geteuid() == 0 +[short] + testing.Short() +[symlink] + testenv.HasSymlink() +[verbose] + testing.Verbose() + diff --git a/src/cmd/nm/testdata/script/issue77301.txt b/src/cmd/nm/testdata/script/issue77301.txt new file mode 100644 index 00000000000000..aa0c9c60db81c0 --- /dev/null +++ b/src/cmd/nm/testdata/script/issue77301.txt @@ -0,0 +1,20 @@ +# Tests the correct symbol placement for initialized vs uninitialized +# globals in the respective sections: https://go.dev/issues/77301 +go build -o main +exec go tool nm main +stdout 'B main.globalUninitialized' +stdout 'D main.globalInitialized' + +-- go.mod -- +module nm_bss_symbol_check + +-- main.go -- +package main + +var globalUninitialized int64 +var globalInitialized int64 = 42 + +func main() { + println(globalUninitialized) + println(globalInitialized) +} diff --git a/src/cmd/pack/pack.go b/src/cmd/pack/pack.go index 4ac6ce995fe918..5269c7465cbae9 100644 --- a/src/cmd/pack/pack.go +++ b/src/cmd/pack/pack.go @@ -6,6 +6,7 @@ package main import ( "cmd/internal/archive" + "cmd/internal/objabi" "cmd/internal/telemetry/counter" "fmt" "io" @@ -32,6 +33,7 @@ func main() { log.SetFlags(0) log.SetPrefix("pack: ") counter.Open() + objabi.Flagparse(usage) // need "pack op archive" at least. if len(os.Args) < 3 { log.Print("not enough arguments") @@ -139,6 +141,11 @@ func openArchive(name string, mode int, files []string) *Archive { if err != nil { log.Fatal(err) } + for _, f := range a.Entries { + if !filepath.IsLocal(f.Name) || filepath.Base(f.Name) != f.Name { + log.Fatalf("%q: invalid name", f.Name) + } + } return &Archive{ a: a, files: files, diff --git a/src/cmd/pack/pack_test.go b/src/cmd/pack/pack_test.go index 2922ada8e923cb..ac42d3162b9c57 100644 --- a/src/cmd/pack/pack_test.go +++ b/src/cmd/pack/pack_test.go @@ -6,6 +6,7 @@ package main import ( "bufio" + "bytes" "cmd/internal/archive" "fmt" "internal/testenv" @@ -163,7 +164,7 @@ func TestExtract(t *testing.T) { // Test that pack-created archives can be understood by the tools. func TestHello(t *testing.T) { testenv.MustHaveGoBuild(t) - // N.B. the build below explictly doesn't pass through + // N.B. the build below explicitly doesn't pass through // -asan/-msan/-race, so we don't care about those. testenv.MustInternalLink(t, testenv.NoSpecialBuildTypes) @@ -382,6 +383,49 @@ func TestRWithNonexistentFile(t *testing.T) { run(packPath(t), "r", "p.a", "p.o") // should succeed } +func TestOutputPathSanitization(t *testing.T) { + dir := t.TempDir() + + // Create pack.a containing a file named "longpathname". + // Note that "go tool pack" requires that all files be at least 8 bytes long. + const validPathName = "longpathname" + if err := os.WriteFile(dir+"/"+validPathName, make([]byte, 8), 0o666); err != nil { + t.Fatal(err) + } + doRun(t, dir, packPath(t), "grc", "pack.a", validPathName) + + // Create evil.a from pack.a, replacing "longpathname" with "out/pathname". + b, err := os.ReadFile(dir + "/pack.a") + if err != nil { + t.Fatal(err) + } + idx := bytes.Index(b, []byte(validPathName)) + if idx < 0 { + t.Fatalf("%v not found in pack.a", validPathName) + } + copy(b[idx:], "out/") + os.WriteFile(dir+"/evil.a", b, 0o666) + + // Extract evil.a. It should fail and not extract a file to /out. + os.Mkdir(dir+"/out", 0o777) + + cmd := testenv.Command(t, packPath(t), "x", "evil.a") + cmd.Dir = dir + _, err = cmd.CombinedOutput() + if err == nil { + t.Errorf("pack x evil.a: unexpected success") + } + + ents, err := os.ReadDir(dir + "/out") + if err != nil { + t.Error(err) + } + for _, e := range ents { + t.Errorf("unexpected file in /out: %q", e.Name()) + } + +} + // doRun runs a program in a directory and returns the output. func doRun(t *testing.T, dir string, args ...string) string { cmd := testenv.Command(t, args[0], args[1:]...) diff --git a/src/cmd/test2json/main.go b/src/cmd/test2json/main.go index dc033b1d5cb165..ff8cc9c8d5b123 100644 --- a/src/cmd/test2json/main.go +++ b/src/cmd/test2json/main.go @@ -41,6 +41,7 @@ // Test string // Elapsed float64 // seconds // Output string +// OutputType string // FailedBuild string // } // @@ -85,6 +86,14 @@ // failed to build. This matches the ImportPath field of the "go list" output, // as well as the BuildEvent.ImportPath field as emitted by "go build -json". // +// The OutputType field *may* be set for Action == "output" and indicates the +// type of output. OutputType will be one of the following: +// +// (blank) - regular output +// frame - test framing, such as "=== RUN ..." or "--- FAIL: ..." +// error - an error produced by Error(f) or Fatal(f) +// error-continue - continuation of a multi-line error +// // When a benchmark runs, it typically produces a single line of output // giving timing results. That line is reported in an event with Action == "output" // and no Test field. If a benchmark logs output or reports a failure diff --git a/src/cmd/trace/main.go b/src/cmd/trace/main.go index 7786e02d00b2a7..0f557ac02dfa2a 100644 --- a/src/cmd/trace/main.go +++ b/src/cmd/trace/main.go @@ -19,6 +19,7 @@ import ( "net" "net/http" _ "net/http/pprof" // Required to use pprof + "net/netip" "os" "slices" "sync/atomic" @@ -47,10 +48,13 @@ Supported profile types are: - sched: scheduler latency profile Flags: - -http=addr: HTTP service address (e.g., ':6060') + -http=addr: HTTP server listen address (e.g., ':6060') -pprof=type: print a pprof-like profile instead -d=mode: print debug info and exit (modes: wire, parsed, footprint) +When providing only a port to -http (e.g., ':6060'), the tool listens only on localhost. +To listen on all addresses, explicitly add the unspecified address (e.g., '0.0.0.0:6060'). + Note that while the various profiles available when launching 'go tool trace' work on every browser, the trace viewer itself (the 'view trace' page) comes from the Chrome/Chromium project @@ -58,7 +62,7 @@ and is only actively tested on that browser. ` var ( - httpFlag = flag.String("http", "localhost:0", "HTTP service address (e.g., ':6060')") + httpFlag = flag.String("http", "localhost:0", "HTTP server listen address (e.g., ':6060')") pprofFlag = flag.String("pprof", "", "print a pprof-like profile instead") debugFlag = flag.String("d", "", "print debug info and exit (modes: wire, parsed, footprint)") @@ -145,11 +149,21 @@ func main() { } } - ln, err := net.Listen("tcp", *httpFlag) + addr, err := listenAddr(*httpFlag) + if err != nil { + logAndDie(fmt.Errorf("malformed -http value %q: %v", *httpFlag, err)) + } + + ln, err := net.Listen("tcp", addr) if err != nil { logAndDie(fmt.Errorf("failed to create server socket: %w", err)) } - addr := "http://" + ln.Addr().String() + + addr = ln.Addr().String() + url, simplified, err := addrURL(addr) + if err != nil { + logAndDie(fmt.Errorf("failed to compute server URL: %v", err)) + } log.Print("Preparing trace for viewer...") parsed, err := parseTraceInteractive(tracef, traceSize) @@ -175,7 +189,14 @@ func main() { logAndDie(err) } - log.Printf("Opening browser. Trace viewer is listening on %s", addr) + if simplified { + // Warn that the URL below is simplified. i.e., we are actually + // listening on more addresses than the URL implies. + log.Printf("Full server listen address: %s", addr) + } + // N.B. gopls depends on the format of this log message. See + // golang.org/x/tools/gopls/internal/debug.startFlightRecorder. + log.Printf("Opening browser. Trace viewer is listening on %s", url) browser.Open(addr) mutatorUtil := func(flags trace.UtilFlags) ([][]trace.MutatorUtil, error) { @@ -237,6 +258,63 @@ func logAndDie(err error) { os.Exit(1) } +// listenAddr returns the address to listen on given the addr address flag. +// +// If addr does not specify a host (e.g., ":8080"), then default to listening +// only on localhost rather than all addresses. To listen on all addresses, +// explicitly set the unspecified address (e.g., "0.0.0.0:8080"). +func listenAddr(addr string) (string, error) { + host, port, err := net.SplitHostPort(addr) + if err != nil { + return "", err + } + if host == "" { + host = "localhost" + } + return net.JoinHostPort(host, port), nil +} + +// addrURL returns an HTTP URL that may be used to connect to addr. +// +// It also returns a bool indicating if the returned URL uses a rewritten address. +func addrURL(addr string) (string, bool, error) { + host, port, err := net.SplitHostPort(addr) + if err != nil { + return "", false, err + } + + if host == "" { + // No host implies unspecified address, so rewrite to + // localhost, as below. + // + // addr should come from a net.Listener and thus always include + // a host, but handle this just in case. + host = "localhost" + return "http://" + net.JoinHostPort(host, port), true, nil + } + + ipaddr, err := netip.ParseAddr(host) + if err != nil { + // Not an IP address, no change required. + return "http://" + net.JoinHostPort(host, port), false, nil + } + + if ipaddr.IsUnspecified() { + // An unspecified address means (e.g., 0.0.0.0) this addr is + // listening on all addresses. It doesn't make sense to connect + // to the unspecified address [1], so rewrite to localhost. A + // connection to localhost with route to the same place. + // + // [1] Linux happens to treat connect to the unspecified + // address as loopback, but other OSes, such as Windows, treat + // it as an error. + host = "localhost" + return "http://" + net.JoinHostPort(host, port), true, nil + } + + return "http://" + net.JoinHostPort(host, port), false, nil +} + func parseTraceInteractive(tr io.Reader, size int64) (parsed *parsedTrace, err error) { done := make(chan struct{}) cr := countingReader{r: tr} diff --git a/src/cmd/trace/main_test.go b/src/cmd/trace/main_test.go new file mode 100644 index 00000000000000..7ec07e7be5d8de --- /dev/null +++ b/src/cmd/trace/main_test.go @@ -0,0 +1,115 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import "testing" + +func TestListenAddr(t *testing.T) { + tests := []struct { + name string + addr string + wantAddr string + wantErr bool + }{ + { + name: "empty host", + addr: ":8080", + wantAddr: "localhost:8080", + }, + { + name: "with host", + addr: "localhost:8080", + wantAddr: "localhost:8080", + }, + { + name: "with IP", + addr: "127.0.0.1:8080", + wantAddr: "127.0.0.1:8080", + }, + { + name: "unspecified host", + addr: "0.0.0.0:8080", + wantAddr: "0.0.0.0:8080", + }, + { + name: "host only", + addr: "127.0.0.1", + wantErr: true, + }, + { + name: "port only", + addr: "8080", + wantErr: true, + }, + } + + for _, tt := range tests { + t.Run(tt.name, func(t *testing.T) { + got, err := listenAddr(tt.addr) + if tt.wantErr && err == nil { + t.Errorf("listenAddr(%q) got nil err want non-nil", tt.addr) + } else if !tt.wantErr && err != nil { + t.Errorf("listenAddr(%q) got err %v want nil", tt.addr, err) + } else if got != tt.wantAddr { + t.Errorf("listenAddr(%q) = %q, want %q", tt.addr, got, tt.wantAddr) + } + }) + } +} + +func TestAddrURL(t *testing.T) { + tests := []struct { + name string + addr string + wantURL string + wantSimplified bool + }{ + { + name: "empty host", + addr: ":8080", + wantURL: "http://localhost:8080", + wantSimplified: true, + }, + { + name: "with host", + addr: "localhost:8080", + wantURL: "http://localhost:8080", + wantSimplified: false, + }, + { + name: "with ip", + addr: "10.10.10.10:8080", + wantURL: "http://10.10.10.10:8080", + wantSimplified: false, + }, + { + name: "unspecified ipv4", + addr: "0.0.0.0:8080", + wantURL: "http://localhost:8080", + wantSimplified: true, + }, + { + name: "unspecified ipv6", + addr: "[::]:8080", + wantURL: "http://localhost:8080", + wantSimplified: true, + }, + } + + for _, tt := range tests { + t.Run(tt.name, func(t *testing.T) { + gotURL, gotSimplified, err := addrURL(tt.addr) + if err != nil { + t.Fatalf("addrURL(%q) got err %v want nil", tt.addr, err) + } + if gotURL != tt.wantURL { + t.Errorf("addrURL(%q) = %q, want %q", tt.addr, gotURL, tt.wantURL) + } + if gotSimplified != tt.wantSimplified { + t.Errorf("addrURL(%q) simplified = %v, want %v", tt.addr, gotSimplified, tt.wantSimplified) + } + }) + } +} diff --git a/src/cmd/trace/pprof.go b/src/cmd/trace/pprof.go index b472ffa759114b..0e5761ba22649c 100644 --- a/src/cmd/trace/pprof.go +++ b/src/cmd/trace/pprof.go @@ -305,12 +305,12 @@ func (m *stackMap) profile() []traceviewer.ProfileRecord { var i int for frame := range stack.Frames() { rec.Stack = append(rec.Stack, frame) + i++ // Cut this off at pprofMaxStack because that's as far // as our deduplication goes. if i >= pprofMaxStack { break } - i++ } prof = append(prof, rec) } @@ -320,9 +320,9 @@ func (m *stackMap) profile() []traceviewer.ProfileRecord { // pcsForStack extracts the first pprofMaxStack PCs from stack into pcs. func pcsForStack(stack trace.Stack, pcs *[pprofMaxStack]uint64) { for i, frame := range slices.Collect(stack.Frames()) { - pcs[i] = frame.PC if i >= len(pcs) { break } + pcs[i] = frame.PC } } diff --git a/src/cmd/trace/pprof_test.go b/src/cmd/trace/pprof_test.go index 6d18e7d5d16a0f..ec5bbd681626ac 100644 --- a/src/cmd/trace/pprof_test.go +++ b/src/cmd/trace/pprof_test.go @@ -14,6 +14,7 @@ import ( "testing/synctest" "time" + itrace "internal/trace" "internal/trace/testtrace" ) @@ -81,6 +82,31 @@ func TestSyscallProfile74850(t *testing.T) { } } +// Regression test: pcsForStack must not panic when the stack has more than +// pprofMaxStack (128) frames. Before the fix, pcs[i] was written before +// checking i >= len(pcs), causing an index-out-of-range panic. +func TestFillPCsOverflow(t *testing.T) { + var pcs [pprofMaxStack]uint64 + + // Build a stack with more frames than pprofMaxStack. + n := pprofMaxStack + 10 + frames := make([]itrace.StackFrame, n) + for i := range frames { + frames[i].PC = uint64(0x1000 + i) + } + stack := itrace.MakeStack(frames) + + // This must not panic. + pcsForStack(stack, &pcs) + + // Verify the first pprofMaxStack entries were written correctly. + for i := 0; i < pprofMaxStack; i++ { + if pcs[i] != uint64(0x1000+i) { + t.Errorf("pcs[%d] = %#x, want %#x", i, pcs[i], 0x1000+i) + } + } +} + func stat(t *testing.T) { _, err := os.Stat(".") if err != nil { diff --git a/src/cmd/trace/procgen.go b/src/cmd/trace/procgen.go index 060e62fe04ba3f..fc0a00e7ce7f24 100644 --- a/src/cmd/trace/procgen.go +++ b/src/cmd/trace/procgen.go @@ -143,6 +143,13 @@ func (g *procGenerator) ProcTransition(ctx *traceContext, ev *trace.Event) { viewerEv := traceviewer.InstantEvent{ Resource: uint64(proc), Stack: ctx.Stack(viewerFrames(ev.Stack())), + + // Annotate with the thread and proc. The proc is redundant, but this is to + // stay consistent with the thread view, where it's useful information. + Arg: format.SchedCtxArg{ + ProcID: uint64(st.Resource.Proc()), + ThreadID: uint64(ev.Thread()), + }, } from, to := st.Proc() @@ -156,7 +163,6 @@ func (g *procGenerator) ProcTransition(ctx *traceContext, ev *trace.Event) { start = ctx.startTime } viewerEv.Name = "proc start" - viewerEv.Arg = format.ThreadIDArg{ThreadID: uint64(ev.Thread())} viewerEv.Ts = ctx.elapsed(start) ctx.IncThreadStateCount(ctx.elapsed(start), traceviewer.ThreadStateRunning, 1) } diff --git a/src/cmd/trace/tasks.go b/src/cmd/trace/tasks.go index 8cb5a83a08bd11..03ee955bb1f33b 100644 --- a/src/cmd/trace/tasks.go +++ b/src/cmd/trace/tasks.go @@ -426,12 +426,12 @@ func describeEvent(ev *trace.Event) string { return fmt.Sprintf("region %q end", ev.Region().Type) case trace.EventTaskBegin: t := ev.Task() - return fmt.Sprintf("task %q (D %d, parent %d) begin", t.Type, t.ID, t.Parent) + return fmt.Sprintf("task %q (ID %d, parent %d) begin", t.Type, t.ID, t.Parent) case trace.EventTaskEnd: return "task end" case trace.EventLog: log := ev.Log() - if log.Category != "" { + if log.Category == "" { return fmt.Sprintf("log %q", log.Message) } return fmt.Sprintf("log (category: %s): %q", log.Category, log.Message) diff --git a/src/cmd/trace/threadgen.go b/src/cmd/trace/threadgen.go index c2e2c86f6cde8c..7f9e7a72f0f9ea 100644 --- a/src/cmd/trace/threadgen.go +++ b/src/cmd/trace/threadgen.go @@ -138,14 +138,17 @@ func (g *threadGenerator) ProcTransition(ctx *traceContext, ev *trace.Event) { } } - type procArg struct { - Proc uint64 `json:"proc,omitempty"` - } st := ev.StateTransition() viewerEv := traceviewer.InstantEvent{ Resource: uint64(ev.Thread()), Stack: ctx.Stack(viewerFrames(ev.Stack())), - Arg: procArg{Proc: uint64(st.Resource.Proc())}, + + // Annotate with the thread and proc. The thread is redundant, but this is to + // stay consistent with the proc view. + Arg: format.SchedCtxArg{ + ProcID: uint64(st.Resource.Proc()), + ThreadID: uint64(ev.Thread()), + }, } from, to := st.Proc() @@ -159,7 +162,6 @@ func (g *threadGenerator) ProcTransition(ctx *traceContext, ev *trace.Event) { start = ctx.startTime } viewerEv.Name = "proc start" - viewerEv.Arg = format.ThreadIDArg{ThreadID: uint64(ev.Thread())} viewerEv.Ts = ctx.elapsed(start) // TODO(mknyszek): We don't have a state machine for threads, so approximate // running threads with running Ps. diff --git a/src/cmd/vendor/github.com/google/pprof/internal/binutils/addr2liner_llvm.go b/src/cmd/vendor/github.com/google/pprof/internal/binutils/addr2liner_llvm.go index 2f5d97e89a669c..c5c7cc0e10ca56 100644 --- a/src/cmd/vendor/github.com/google/pprof/internal/binutils/addr2liner_llvm.go +++ b/src/cmd/vendor/github.com/google/pprof/internal/binutils/addr2liner_llvm.go @@ -151,11 +151,11 @@ func (d *llvmSymbolizer) readCodeFrames() ([]plugin.Frame, error) { Address string `json:"Address"` ModuleName string `json:"ModuleName"` Symbol []struct { - Line int `json:"Line"` - Column int `json:"Column"` - FunctionName string `json:"FunctionName"` - FileName string `json:"FileName"` - StartLine int `json:"StartLine"` + Line int `json:"Line"` + Column int `json:"Column"` + FunctionName string `json:"FunctionName"` + FileName string `json:"FileName"` + StartLine int `json:"StartLine"` } `json:"Symbol"` } if err := json.Unmarshal([]byte(line), &frame); err != nil { diff --git a/src/cmd/vendor/github.com/google/pprof/internal/driver/cli.go b/src/cmd/vendor/github.com/google/pprof/internal/driver/cli.go index b97ef8516934ae..7b8c3fc60781fd 100644 --- a/src/cmd/vendor/github.com/google/pprof/internal/driver/cli.go +++ b/src/cmd/vendor/github.com/google/pprof/internal/driver/cli.go @@ -37,6 +37,7 @@ type source struct { HTTPHostport string HTTPDisableBrowser bool Comment string + AllFrames bool } // parseFlags parses the command lines through the specified flags package @@ -51,7 +52,8 @@ func parseFlags(o *plugin.Options) (*source, []string, error) { flagSymbolize := flag.String("symbolize", "", "Options for profile symbolization") flagBuildID := flag.String("buildid", "", "Override build id for first mapping") flagTimeout := flag.Int("timeout", -1, "Timeout in seconds for fetching a profile") - flagAddComment := flag.String("add_comment", "", "Annotation string to record in the profile") + flagAddComment := flag.String("add_comment", "", "Free-form annotation to add to the profile") + flagAllFrames := flag.Bool("all_frames", false, "Ignore drop_frames and keep_frames regexps") // CPU profile options flagSeconds := flag.Int("seconds", -1, "Length of time for dynamic profiles") // Heap profile options @@ -145,6 +147,7 @@ func parseFlags(o *plugin.Options) (*source, []string, error) { HTTPHostport: *flagHTTP, HTTPDisableBrowser: *flagNoBrowser, Comment: *flagAddComment, + AllFrames: *flagAllFrames, } if err := source.addBaseProfiles(*flagBase, *flagDiffBase); err != nil { @@ -338,6 +341,8 @@ var usageMsgVars = "\n\n" + " Port is optional and a randomly available port by default.\n" + " -no_browser Skip opening a browser for the interactive web UI.\n" + " -tools Search path for object tools\n" + + " -all_frames Ignore drop_frames and keep_frames regexps in the profile\n" + + " Rarely needed, mainly used for debugging pprof itself\n" + "\n" + " Legacy convenience options:\n" + " -inuse_space Same as -sample_index=inuse_space\n" + diff --git a/src/cmd/vendor/github.com/google/pprof/internal/driver/config.go b/src/cmd/vendor/github.com/google/pprof/internal/driver/config.go index 184de397ef57e4..20d169c8f68e87 100644 --- a/src/cmd/vendor/github.com/google/pprof/internal/driver/config.go +++ b/src/cmd/vendor/github.com/google/pprof/internal/driver/config.go @@ -164,7 +164,7 @@ func init() { def := defaultConfig() configFieldMap = map[string]configField{} - t := reflect.TypeOf(config{}) + t := reflect.TypeFor[config]() for i, n := 0, t.NumField(); i < n; i++ { field := t.Field(i) js := strings.Split(field.Tag.Get("json"), ",") diff --git a/src/cmd/vendor/github.com/google/pprof/internal/driver/fetch.go b/src/cmd/vendor/github.com/google/pprof/internal/driver/fetch.go index 969c1dac11ef35..0809cd0814386e 100644 --- a/src/cmd/vendor/github.com/google/pprof/internal/driver/fetch.go +++ b/src/cmd/vendor/github.com/google/pprof/internal/driver/fetch.go @@ -77,6 +77,11 @@ func fetchProfiles(s *source, o *plugin.Options) (*profile.Profile, error) { } } + if s.AllFrames { + p.DropFrames = "" + p.KeepFrames = "" + } + // Symbolize the merged profile. if err := o.Sym.Symbolize(s.Symbolize, m, p); err != nil { return nil, err @@ -425,7 +430,9 @@ mapping: // Llvm buildid protocol: the first two characters of the build id // are used as directory, and the remaining part is in the filename. // e.g. `/ab/cdef0123456.debug` - fileNames = append(fileNames, filepath.Join(path, m.BuildID[:2], m.BuildID[2:]+".debug")) + if len(m.BuildID) >= 2 { + fileNames = append(fileNames, filepath.Join(path, m.BuildID[:2], m.BuildID[2:]+".debug")) + } } if m.File != "" { // Try both the basename and the full path, to support the same directory diff --git a/src/cmd/vendor/github.com/google/pprof/internal/driver/html/header.html b/src/cmd/vendor/github.com/google/pprof/internal/driver/html/header.html index 5405a0be955421..4d0f198a695984 100644 --- a/src/cmd/vendor/github.com/google/pprof/internal/driver/html/header.html +++ b/src/cmd/vendor/github.com/google/pprof/internal/driver/html/header.html @@ -10,7 +10,7 @@

    pprof